diff --git a/Makefile b/Makefile index 69b071da0..062571492 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,7 @@ COREIR_INCLUDE = $(COREIR_PATH)/include COREIR_LIB = $(COREIR_PATH)/lib CXX_FLAGS += -I $(COREIR_INCLUDE) -D COREIR -LINK_FLAGS += -L $(COREIR_LIB) -Wl,-rpath $(COREIR_LIB) -lcoreir -lcoreirsim -lcoreir-commonlib +LINK_FLAGS += -L $(COREIR_LIB) -Wl,-rpath $(COREIR_LIB) -lcoreir -lcoreirsim -lcoreir-commonlib -lcoreir-float -lcoreir-float_DW endif ifeq ($(CGRAFLOW),1) @@ -43,7 +43,7 @@ LIB_HEADER_FILES = $(patsubst %.cpp,%.h,$(TEST_FILES)) PROGS_CPP_FILES := $(shell find example_progs -name "*.cpp") PROGS_OBJ := $(patsubst example_progs/%.cpp, $(BUILD_DIR)/%.o, $(PROGS_CPP_FILES)) -LIB_CPP_FILES = qexpr.cpp expr.cpp app.cpp isl_utils.cpp prog.cpp codegen.cpp ubuffer.cpp coreir_backend.cpp cgralib.cpp cwlib.cpp options.cpp lake_target.cpp utils.cpp simple_example_progs.cpp rdai_collateral.cpp verilog_backend.cpp +LIB_CPP_FILES = qexpr.cpp expr.cpp app.cpp isl_utils.cpp prog.cpp codegen.cpp ubuffer.cpp coreir_backend.cpp cgralib.cpp cwlib.cpp options.cpp lake_target.cpp utils.cpp simple_example_progs.cpp rdai_collateral.cpp verilog_backend.cpp cgra_flow.cpp LIB_CPP_FILES += build_set_test.cpp prog_splitting_test.cpp LIB_HEADER_FILES = $(patsubst %.cpp,%.h,$(LIB_CPP_FILES)) #LIB_CPP_FILES += $(PROGS_CPP_FILES) diff --git a/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new.json b/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new.json index 7fd1db09f..3f5e8c593 100644 --- a/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new.json +++ b/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "affine_controller__U64":{ + "affine_controller__U33":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17,13 +17,13 @@ }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U65"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U65"} + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U66"} + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -45,7 +45,7 @@ ["op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const.out","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2.rst_n"] ] }, - "affine_controller__U73":{ + "affine_controller__U42":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -60,13 +60,13 @@ }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U74"} + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U75"} + "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -88,7 +88,7 @@ ["op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const.out","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2.rst_n"] ] }, - "affine_controller__U82":{ + "affine_controller__U51":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -103,13 +103,13 @@ }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U83"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U83"} + "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U84"} + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -142,18 +142,10 @@ ["op_hcompute_demosaicked_1_stencil_2_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_b_b_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[339],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[332],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_b_b_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -161,8 +153,8 @@ }, "ub_b_b_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[339],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[332],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[606],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[606],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}},"mode":"lake"} }, "ub_b_b_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -170,8 +162,6 @@ } }, "connections":[ - ["ub_b_b_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_b_b_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], ["ub_b_b_stencil_BANK_0.clk","self.clk"], ["ub_b_b_stencil_BANK_1.clk","self.clk"], ["ub_b_b_stencil_BANK_0.data_in_0","self.op_hcompute_b_b_stencil_write.0"], @@ -194,15 +184,15 @@ ["reset","BitIn"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid","Bit"], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write_valid","Bit"], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid","Bit"], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid","Bit"], ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U95":{ + "_U64":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -259,70 +249,70 @@ "modref":"global.cu_op_hcompute_demosaicked_1_stencil_1" }, "op_hcompute_demosaicked_1_stencil_1_exe_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U78" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U47" }, "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U79" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U48" }, "op_hcompute_demosaicked_1_stencil_1_port_controller":{ - "modref":"global.affine_controller__U73" + "modref":"global.affine_controller__U42" }, "op_hcompute_demosaicked_1_stencil_1_read_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_pt__U76" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_pt__U45" }, "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U77" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U46" }, "op_hcompute_demosaicked_1_stencil_1_write_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_pt__U80" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_pt__U49" }, "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U81" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U50" }, "op_hcompute_demosaicked_1_stencil_2":{ "modref":"global.cu_op_hcompute_demosaicked_1_stencil_2" }, "op_hcompute_demosaicked_1_stencil_2_exe_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U69" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U38" }, "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U70" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U39" }, "op_hcompute_demosaicked_1_stencil_2_port_controller":{ - "modref":"global.affine_controller__U64" + "modref":"global.affine_controller__U33" }, "op_hcompute_demosaicked_1_stencil_2_read_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_pt__U67" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_pt__U36" }, "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U68" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U37" }, "op_hcompute_demosaicked_1_stencil_2_write_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_pt__U71" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_pt__U40" }, "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U72" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U41" }, "op_hcompute_demosaicked_1_stencil_exe_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_pt__U87" + "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_pt__U56" }, "op_hcompute_demosaicked_1_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U88" + "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U57" }, "op_hcompute_demosaicked_1_stencil_port_controller":{ - "modref":"global.affine_controller__U82" + "modref":"global.affine_controller__U51" }, "op_hcompute_demosaicked_1_stencil_read_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_pt__U85" + "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_pt__U54" }, "op_hcompute_demosaicked_1_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U86" + "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U55" }, "op_hcompute_demosaicked_1_stencil_write_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_pt__U89" + "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_pt__U58" }, "op_hcompute_demosaicked_1_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U90" + "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U59" }, "op_hcompute_denoised_1_stencil":{ "modref":"global.cu_op_hcompute_denoised_1_stencil" @@ -337,22 +327,22 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U93" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U62" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U91"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U91"} + "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U92" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U61" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U94" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U63" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" @@ -361,61 +351,61 @@ "modref":"global.cu_op_hcompute_hw_output_stencil_1" }, "op_hcompute_hw_output_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U58" + "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U27" }, "op_hcompute_hw_output_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U56"} + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U57" + "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U26" }, "op_hcompute_hw_output_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U59" + "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U28" }, "op_hcompute_hw_output_stencil_2":{ "modref":"global.cu_op_hcompute_hw_output_stencil_2" }, "op_hcompute_hw_output_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U54" + "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U23" }, "op_hcompute_hw_output_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U52"} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U53" + "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U22" }, "op_hcompute_hw_output_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U55" + "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U24" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U62" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U31" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U60"} + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U61" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U30" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U63" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U32" }, "op_hcompute_r_r_stencil":{ "modref":"global.cu_op_hcompute_r_r_stencil" @@ -425,8 +415,8 @@ } }, "connections":[ - ["self.clk","_U95.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U95.in"], + ["self.clk","_U64.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U64.in"], ["self.clk","b_b_stencil.clk"], ["op_hcompute_b_b_stencil.b_b_stencil_op_hcompute_b_b_stencil_write","b_b_stencil.op_hcompute_b_b_stencil_write"], ["op_hcompute_demosaicked_1_stencil_2.b_b_stencil_op_hcompute_demosaicked_1_stencil_2_read","b_b_stencil.op_hcompute_demosaicked_1_stencil_2_read"], @@ -533,9 +523,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], ["self.clk","op_hcompute_hw_output_stencil.clk"], - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write"], + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write"], ["self.clk","op_hcompute_hw_output_stencil_1.clk"], - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write","op_hcompute_hw_output_stencil_1.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write","op_hcompute_hw_output_stencil_1.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write"], ["op_hcompute_hw_output_stencil_1_port_controller.stencil_valid","op_hcompute_hw_output_stencil_1_exe_start.in"], ["self.clk","op_hcompute_hw_output_stencil_1_port_controller.clk"], ["op_hcompute_hw_output_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_1_port_controller.clk_en"], @@ -543,7 +533,7 @@ ["op_hcompute_hw_output_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_1_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_1_read_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_1_write_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid","op_hcompute_hw_output_stencil_1_write_start.out"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid","op_hcompute_hw_output_stencil_1_write_start.out"], ["self.clk","op_hcompute_hw_output_stencil_2.clk"], ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write","op_hcompute_hw_output_stencil_2.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write"], ["op_hcompute_hw_output_stencil_2_port_controller.stencil_valid","op_hcompute_hw_output_stencil_2_exe_start.in"], @@ -561,7 +551,7 @@ ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_read_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_write_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"], + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"], ["self.clk","op_hcompute_r_r_stencil.clk"], ["r_r_stencil.op_hcompute_r_r_stencil_write","op_hcompute_r_r_stencil.r_r_stencil_op_hcompute_r_r_stencil_write"], ["self.clk","r_r_stencil.clk"], @@ -929,7 +919,7 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["curved_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -938,7 +928,7 @@ }, "connections":[ ["self.curved_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in0_curved_stencil.0"], - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -948,7 +938,7 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["curved_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -957,7 +947,7 @@ }, "connections":[ ["self.curved_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute.in0_curved_stencil.0"], - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1070,24 +1060,15 @@ ["op_hcompute_r_r_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U6":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "d_reg__U7":{ + "d_reg__U3":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_denoised_1_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[268],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[264],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[328],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[330],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[268],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[264],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[393],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"sram2tb_1":{"cycle_starting_addr":[327],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[395],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]},"tb2out_1":{"cycle_starting_addr":[330],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake"} }, "ub_denoised_1_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1095,17 +1076,14 @@ } }, "connections":[ - ["ub_denoised_1_stencil_BANK_0.chain_chain_en","chain_en_const_U5.out"], - ["self.clk","d_reg__U6.clk"], - ["self.op_hcompute_denoised_1_stencil_write.0","d_reg__U6.in"], - ["self.op_hcompute_b_b_stencil_read.0","d_reg__U6.out"], - ["self.clk","d_reg__U7.clk"], - ["ub_denoised_1_stencil_BANK_0.data_out_0","d_reg__U7.in"], - ["self.op_hcompute_r_r_stencil_read.0","d_reg__U7.out"], + ["self.clk","d_reg__U3.clk"], + ["ub_denoised_1_stencil_BANK_0.data_out_1","d_reg__U3.in"], + ["self.op_hcompute_r_r_stencil_read.0","d_reg__U3.out"], ["ub_denoised_1_stencil_BANK_0.clk","self.clk"], + ["ub_denoised_1_stencil_BANK_0.data_out_0","self.op_hcompute_b_b_stencil_read.0"], ["self.op_hcompute_g_gb_stencil_read.0","self.op_hcompute_denoised_1_stencil_write.0"], ["ub_denoised_1_stencil_BANK_0.data_in_0","self.op_hcompute_denoised_1_stencil_write.0"], - ["ub_denoised_1_stencil_BANK_0.data_out_0","self.op_hcompute_g_gr_stencil_read.0"], + ["ub_denoised_1_stencil_BANK_0.data_out_1","self.op_hcompute_g_gr_stencil_read.0"], ["ub_denoised_1_stencil_BANK_0.flush","self.reset"], ["ub_denoised_1_stencil_BANK_0_clk_en_const.out","ub_denoised_1_stencil_BANK_0.clk_en"], ["ub_denoised_1_stencil_BANK_0_clk_en_const.out","ub_denoised_1_stencil_BANK_0.rst_n"] @@ -1126,42 +1104,10 @@ ["op_hcompute_g_gb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U19":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U21":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U23":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_g_gb_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_g_gb_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1169,8 +1115,8 @@ }, "ub_g_gb_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_g_gb_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -1178,8 +1124,8 @@ }, "ub_g_gb_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]}},"mode":"lake"} }, "ub_g_gb_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -1187,98 +1133,42 @@ }, "ub_g_gb_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_g_gb_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} - }, - "ub_g_gb_stencil_BANK_4":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U16"} - }, - "ub_g_gb_stencil_BANK_4_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ub_g_gb_stencil_BANK_5":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U18"} - }, - "ub_g_gb_stencil_BANK_5_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ub_g_gb_stencil_BANK_6":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}},"mode":"lake","verilog_name":"lake__U20"} - }, - "ub_g_gb_stencil_BANK_6_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ub_g_gb_stencil_BANK_7":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U22"} - }, - "ub_g_gb_stencil_BANK_7_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} } }, "connections":[ - ["ub_g_gb_stencil_BANK_1.chain_chain_en","chain_en_const_U11.out"], - ["ub_g_gb_stencil_BANK_2.chain_chain_en","chain_en_const_U13.out"], - ["ub_g_gb_stencil_BANK_3.chain_chain_en","chain_en_const_U15.out"], - ["ub_g_gb_stencil_BANK_4.chain_chain_en","chain_en_const_U17.out"], - ["ub_g_gb_stencil_BANK_5.chain_chain_en","chain_en_const_U19.out"], - ["ub_g_gb_stencil_BANK_6.chain_chain_en","chain_en_const_U21.out"], - ["ub_g_gb_stencil_BANK_7.chain_chain_en","chain_en_const_U23.out"], - ["ub_g_gb_stencil_BANK_0.chain_chain_en","chain_en_const_U9.out"], ["ub_g_gb_stencil_BANK_0.clk","self.clk"], ["ub_g_gb_stencil_BANK_1.clk","self.clk"], ["ub_g_gb_stencil_BANK_2.clk","self.clk"], ["ub_g_gb_stencil_BANK_3.clk","self.clk"], - ["ub_g_gb_stencil_BANK_4.clk","self.clk"], - ["ub_g_gb_stencil_BANK_5.clk","self.clk"], - ["ub_g_gb_stencil_BANK_6.clk","self.clk"], - ["ub_g_gb_stencil_BANK_7.clk","self.clk"], - ["ub_g_gb_stencil_BANK_7.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], - ["ub_g_gb_stencil_BANK_6.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.1"], - ["ub_g_gb_stencil_BANK_6.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.2"], - ["ub_g_gb_stencil_BANK_5.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], - ["ub_g_gb_stencil_BANK_5.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.1"], - ["ub_g_gb_stencil_BANK_4.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.2"], - ["ub_g_gb_stencil_BANK_4.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.3"], - ["ub_g_gb_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], - ["ub_g_gb_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], - ["ub_g_gb_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], - ["ub_g_gb_stencil_BANK_2.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], - ["ub_g_gb_stencil_BANK_1.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.2"], - ["ub_g_gb_stencil_BANK_1.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.3"], + ["ub_g_gb_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], + ["ub_g_gb_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.1"], + ["ub_g_gb_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.2"], + ["ub_g_gb_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], + ["ub_g_gb_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.1"], + ["ub_g_gb_stencil_BANK_2.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.2"], + ["ub_g_gb_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.3"], + ["ub_g_gb_stencil_BANK_1.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], + ["ub_g_gb_stencil_BANK_1.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], + ["ub_g_gb_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], + ["ub_g_gb_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], + ["ub_g_gb_stencil_BANK_2.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.2"], + ["ub_g_gb_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.3"], ["ub_g_gb_stencil_BANK_0.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.4"], ["ub_g_gb_stencil_BANK_0.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.5"], ["ub_g_gb_stencil_BANK_0.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_1.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_2.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_3.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_4.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_5.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_6.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_7.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_0.flush","self.reset"], ["ub_g_gb_stencil_BANK_1.flush","self.reset"], ["ub_g_gb_stencil_BANK_2.flush","self.reset"], ["ub_g_gb_stencil_BANK_3.flush","self.reset"], - ["ub_g_gb_stencil_BANK_4.flush","self.reset"], - ["ub_g_gb_stencil_BANK_5.flush","self.reset"], - ["ub_g_gb_stencil_BANK_6.flush","self.reset"], - ["ub_g_gb_stencil_BANK_7.flush","self.reset"], ["ub_g_gb_stencil_BANK_0_clk_en_const.out","ub_g_gb_stencil_BANK_0.clk_en"], ["ub_g_gb_stencil_BANK_0_clk_en_const.out","ub_g_gb_stencil_BANK_0.rst_n"], ["ub_g_gb_stencil_BANK_1_clk_en_const.out","ub_g_gb_stencil_BANK_1.clk_en"], @@ -1286,15 +1176,7 @@ ["ub_g_gb_stencil_BANK_2_clk_en_const.out","ub_g_gb_stencil_BANK_2.clk_en"], ["ub_g_gb_stencil_BANK_2_clk_en_const.out","ub_g_gb_stencil_BANK_2.rst_n"], ["ub_g_gb_stencil_BANK_3_clk_en_const.out","ub_g_gb_stencil_BANK_3.clk_en"], - ["ub_g_gb_stencil_BANK_3_clk_en_const.out","ub_g_gb_stencil_BANK_3.rst_n"], - ["ub_g_gb_stencil_BANK_4_clk_en_const.out","ub_g_gb_stencil_BANK_4.clk_en"], - ["ub_g_gb_stencil_BANK_4_clk_en_const.out","ub_g_gb_stencil_BANK_4.rst_n"], - ["ub_g_gb_stencil_BANK_5_clk_en_const.out","ub_g_gb_stencil_BANK_5.clk_en"], - ["ub_g_gb_stencil_BANK_5_clk_en_const.out","ub_g_gb_stencil_BANK_5.rst_n"], - ["ub_g_gb_stencil_BANK_6_clk_en_const.out","ub_g_gb_stencil_BANK_6.clk_en"], - ["ub_g_gb_stencil_BANK_6_clk_en_const.out","ub_g_gb_stencil_BANK_6.rst_n"], - ["ub_g_gb_stencil_BANK_7_clk_en_const.out","ub_g_gb_stencil_BANK_7.clk_en"], - ["ub_g_gb_stencil_BANK_7_clk_en_const.out","ub_g_gb_stencil_BANK_7.rst_n"] + ["ub_g_gb_stencil_BANK_3_clk_en_const.out","ub_g_gb_stencil_BANK_3.rst_n"] ] }, "g_gr_stencil_ub":{ @@ -1312,42 +1194,10 @@ ["op_hcompute_g_gr_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U31":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_g_gr_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U24"} + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]}},"mode":"lake"} }, "ub_g_gr_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1355,8 +1205,8 @@ }, "ub_g_gr_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U26"} + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_g_gr_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -1364,8 +1214,8 @@ }, "ub_g_gr_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U28"} + "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_g_gr_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -1373,98 +1223,42 @@ }, "ub_g_gr_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U30"} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_g_gr_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} - }, - "ub_g_gr_stencil_BANK_4":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U32"} - }, - "ub_g_gr_stencil_BANK_4_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ub_g_gr_stencil_BANK_5":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U34"} - }, - "ub_g_gr_stencil_BANK_5_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ub_g_gr_stencil_BANK_6":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U36"} - }, - "ub_g_gr_stencil_BANK_6_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ub_g_gr_stencil_BANK_7":{ - "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U38"} - }, - "ub_g_gr_stencil_BANK_7_clk_en_const":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} } }, "connections":[ - ["ub_g_gr_stencil_BANK_0.chain_chain_en","chain_en_const_U25.out"], - ["ub_g_gr_stencil_BANK_1.chain_chain_en","chain_en_const_U27.out"], - ["ub_g_gr_stencil_BANK_2.chain_chain_en","chain_en_const_U29.out"], - ["ub_g_gr_stencil_BANK_3.chain_chain_en","chain_en_const_U31.out"], - ["ub_g_gr_stencil_BANK_4.chain_chain_en","chain_en_const_U33.out"], - ["ub_g_gr_stencil_BANK_5.chain_chain_en","chain_en_const_U35.out"], - ["ub_g_gr_stencil_BANK_6.chain_chain_en","chain_en_const_U37.out"], - ["ub_g_gr_stencil_BANK_7.chain_chain_en","chain_en_const_U39.out"], ["ub_g_gr_stencil_BANK_0.clk","self.clk"], ["ub_g_gr_stencil_BANK_1.clk","self.clk"], ["ub_g_gr_stencil_BANK_2.clk","self.clk"], ["ub_g_gr_stencil_BANK_3.clk","self.clk"], - ["ub_g_gr_stencil_BANK_4.clk","self.clk"], - ["ub_g_gr_stencil_BANK_5.clk","self.clk"], - ["ub_g_gr_stencil_BANK_6.clk","self.clk"], - ["ub_g_gr_stencil_BANK_7.clk","self.clk"], - ["ub_g_gr_stencil_BANK_7.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], - ["ub_g_gr_stencil_BANK_6.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.1"], - ["ub_g_gr_stencil_BANK_6.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.2"], - ["ub_g_gr_stencil_BANK_5.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], - ["ub_g_gr_stencil_BANK_5.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.1"], - ["ub_g_gr_stencil_BANK_4.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.2"], - ["ub_g_gr_stencil_BANK_4.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.3"], - ["ub_g_gr_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], - ["ub_g_gr_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], - ["ub_g_gr_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], - ["ub_g_gr_stencil_BANK_2.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], - ["ub_g_gr_stencil_BANK_1.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.2"], - ["ub_g_gr_stencil_BANK_1.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.3"], - ["ub_g_gr_stencil_BANK_0.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.4"], - ["ub_g_gr_stencil_BANK_0.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.5"], + ["ub_g_gr_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], + ["ub_g_gr_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.1"], + ["ub_g_gr_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.2"], + ["ub_g_gr_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], + ["ub_g_gr_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.1"], + ["ub_g_gr_stencil_BANK_2.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.2"], + ["ub_g_gr_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.3"], + ["ub_g_gr_stencil_BANK_1.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], + ["ub_g_gr_stencil_BANK_1.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], + ["ub_g_gr_stencil_BANK_3.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], + ["ub_g_gr_stencil_BANK_3.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], + ["ub_g_gr_stencil_BANK_0.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.2"], + ["ub_g_gr_stencil_BANK_2.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.3"], + ["ub_g_gr_stencil_BANK_0.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.4"], + ["ub_g_gr_stencil_BANK_1.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.5"], ["ub_g_gr_stencil_BANK_0.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_1.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_2.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_3.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_4.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_5.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_6.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_7.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_0.flush","self.reset"], ["ub_g_gr_stencil_BANK_1.flush","self.reset"], ["ub_g_gr_stencil_BANK_2.flush","self.reset"], ["ub_g_gr_stencil_BANK_3.flush","self.reset"], - ["ub_g_gr_stencil_BANK_4.flush","self.reset"], - ["ub_g_gr_stencil_BANK_5.flush","self.reset"], - ["ub_g_gr_stencil_BANK_6.flush","self.reset"], - ["ub_g_gr_stencil_BANK_7.flush","self.reset"], ["ub_g_gr_stencil_BANK_0_clk_en_const.out","ub_g_gr_stencil_BANK_0.clk_en"], ["ub_g_gr_stencil_BANK_0_clk_en_const.out","ub_g_gr_stencil_BANK_0.rst_n"], ["ub_g_gr_stencil_BANK_1_clk_en_const.out","ub_g_gr_stencil_BANK_1.clk_en"], @@ -1472,15 +1266,7 @@ ["ub_g_gr_stencil_BANK_2_clk_en_const.out","ub_g_gr_stencil_BANK_2.clk_en"], ["ub_g_gr_stencil_BANK_2_clk_en_const.out","ub_g_gr_stencil_BANK_2.rst_n"], ["ub_g_gr_stencil_BANK_3_clk_en_const.out","ub_g_gr_stencil_BANK_3.clk_en"], - ["ub_g_gr_stencil_BANK_3_clk_en_const.out","ub_g_gr_stencil_BANK_3.rst_n"], - ["ub_g_gr_stencil_BANK_4_clk_en_const.out","ub_g_gr_stencil_BANK_4.clk_en"], - ["ub_g_gr_stencil_BANK_4_clk_en_const.out","ub_g_gr_stencil_BANK_4.rst_n"], - ["ub_g_gr_stencil_BANK_5_clk_en_const.out","ub_g_gr_stencil_BANK_5.clk_en"], - ["ub_g_gr_stencil_BANK_5_clk_en_const.out","ub_g_gr_stencil_BANK_5.rst_n"], - ["ub_g_gr_stencil_BANK_6_clk_en_const.out","ub_g_gr_stencil_BANK_6.clk_en"], - ["ub_g_gr_stencil_BANK_6_clk_en_const.out","ub_g_gr_stencil_BANK_6.rst_n"], - ["ub_g_gr_stencil_BANK_7_clk_en_const.out","ub_g_gr_stencil_BANK_7.clk_en"], - ["ub_g_gr_stencil_BANK_7_clk_en_const.out","ub_g_gr_stencil_BANK_7.rst_n"] + ["ub_g_gr_stencil_BANK_3_clk_en_const.out","ub_g_gr_stencil_BANK_3.rst_n"] ] }, "hcompute_b_b_stencil":{ @@ -4042,44 +3828,40 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U42":{ + "d_reg__U13":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U43":{ + "d_reg__U14":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U44":{ + "d_reg__U15":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U45":{ + "d_reg__U16":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U46":{ + "d_reg__U17":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U47":{ + "d_reg__U18":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[258],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[127],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[262],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[130],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U40"} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[258],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[127],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[262],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[130],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -4087,22 +3869,21 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U41.out"], - ["self.clk","d_reg__U42.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U42.in"], - ["d_reg__U43.in","d_reg__U42.out"], - ["self.clk","d_reg__U43.clk"], - ["self.op_hcompute_denoised_1_stencil_read.1","d_reg__U43.out"], - ["self.clk","d_reg__U44.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U44.in"], - ["d_reg__U45.in","d_reg__U44.out"], - ["self.clk","d_reg__U45.clk"], - ["d_reg__U46.in","d_reg__U45.out"], - ["self.op_hcompute_denoised_1_stencil_read.0","d_reg__U45.out"], - ["self.clk","d_reg__U46.clk"], - ["d_reg__U47.in","d_reg__U46.out"], - ["self.clk","d_reg__U47.clk"], - ["self.op_hcompute_denoised_1_stencil_read.3","d_reg__U47.out"], + ["self.clk","d_reg__U13.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U13.in"], + ["d_reg__U14.in","d_reg__U13.out"], + ["self.clk","d_reg__U14.clk"], + ["self.op_hcompute_denoised_1_stencil_read.1","d_reg__U14.out"], + ["self.clk","d_reg__U15.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U15.in"], + ["d_reg__U16.in","d_reg__U15.out"], + ["self.clk","d_reg__U16.clk"], + ["d_reg__U17.in","d_reg__U16.out"], + ["self.op_hcompute_denoised_1_stencil_read.0","d_reg__U16.out"], + ["self.clk","d_reg__U17.clk"], + ["d_reg__U18.in","d_reg__U17.out"], + ["self.clk","d_reg__U18.clk"], + ["self.op_hcompute_denoised_1_stencil_read.3","d_reg__U18.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_denoised_1_stencil_read.2"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","self.op_hcompute_denoised_1_stencil_read.4"], @@ -4112,7 +3893,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U79":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U48":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4121,7 +3902,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U78":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U47":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4130,7 +3911,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U77":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U46":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4139,7 +3920,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U76":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U45":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4148,7 +3929,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U81":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U50":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4157,7 +3938,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U80":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U49":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4166,7 +3947,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U70":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U39":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4175,7 +3956,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U69":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4184,7 +3965,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U68":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U37":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4193,7 +3974,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U67":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4202,7 +3983,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U72":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U41":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4211,7 +3992,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U71":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4220,7 +4001,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U88":{ + "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U57":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4229,7 +4010,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_pt__U87":{ + "op_hcompute_demosaicked_1_stencil_exe_start_pt__U56":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4238,7 +4019,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U86":{ + "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U55":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4247,7 +4028,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_pt__U85":{ + "op_hcompute_demosaicked_1_stencil_read_start_pt__U54":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4256,7 +4037,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U90":{ + "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U59":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4265,7 +4046,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_pt__U89":{ + "op_hcompute_demosaicked_1_stencil_write_start_pt__U58":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4274,7 +4055,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U93":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U62":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4283,7 +4064,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U92":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U61":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4292,7 +4073,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U94":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U63":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4301,7 +4082,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U58":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U27":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4310,7 +4091,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U57":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4319,7 +4100,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U59":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U28":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4328,7 +4109,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U54":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U23":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4337,7 +4118,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U53":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U22":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4346,7 +4127,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U55":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U24":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4355,7 +4136,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U62":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U31":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4364,7 +4145,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U61":{ + "op_hcompute_hw_output_stencil_read_start_pt__U30":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4373,7 +4154,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U63":{ + "op_hcompute_hw_output_stencil_write_start_pt__U32":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4393,18 +4174,10 @@ ["op_hcompute_r_r_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_r_r_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U48"} + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_r_r_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -4412,8 +4185,8 @@ }, "ub_r_r_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U50"} + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_r_r_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -4421,8 +4194,6 @@ } }, "connections":[ - ["ub_r_r_stencil_BANK_0.chain_chain_en","chain_en_const_U49.out"], - ["ub_r_r_stencil_BANK_1.chain_chain_en","chain_en_const_U51.out"], ["ub_r_r_stencil_BANK_0.clk","self.clk"], ["ub_r_r_stencil_BANK_1.clk","self.clk"], ["ub_r_r_stencil_BANK_1.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], diff --git a/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new_garnet.json b/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new_garnet.json index 178195bdf..f5ceab94b 100644 --- a/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new_garnet.json +++ b/aha_garnet_design_new/camera_pipeline_new/camera_pipeline_new_garnet.json @@ -310,7 +310,7 @@ }, "global":{ "modules":{ - "affine_controller__U64":{ + "affine_controller__U33":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -318,29 +318,29 @@ ["rst_n","BitIn"] ]], "instances":{ - "PE_init_U98":{ + "PE_init_U67":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U96":{ + "_U65":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U97":{ + "_U66":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U65"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst":{ @@ -355,9 +355,9 @@ } }, "connections":[ - ["_U96.out","PE_init_U98.data.in.0"], - ["_U97.out","PE_init_U98.data.in.1"], - ["self.d.0","PE_init_U98.data.out"], + ["_U65.out","PE_init_U67.data.in.0"], + ["_U66.out","PE_init_U67.data.in.1"], + ["self.d.0","PE_init_U67.data.out"], ["self.clk","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk"], ["op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk_en"], ["self.d.1","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.data_out_0"], @@ -369,7 +369,7 @@ ["self.rst_n","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet.flush"] ] }, - "affine_controller__U73":{ + "affine_controller__U42":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -377,29 +377,29 @@ ["rst_n","BitIn"] ]], "instances":{ - "PE_init_U101":{ + "PE_init_U70":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U100":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U99":{ + "_U69":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst":{ @@ -414,9 +414,9 @@ } }, "connections":[ - ["_U99.out","PE_init_U101.data.in.0"], - ["_U100.out","PE_init_U101.data.in.1"], - ["self.d.0","PE_init_U101.data.out"], + ["_U68.out","PE_init_U70.data.in.0"], + ["_U69.out","PE_init_U70.data.in.1"], + ["self.d.0","PE_init_U70.data.out"], ["self.clk","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk"], ["op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk_en"], ["self.d.1","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.data_out_0"], @@ -428,7 +428,7 @@ ["self.rst_n","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.flush"] ] }, - "affine_controller__U82":{ + "affine_controller__U51":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -436,29 +436,29 @@ ["rst_n","BitIn"] ]], "instances":{ - "PE_init_U104":{ + "PE_init_U73":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U102":{ + "_U71":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U103":{ + "_U72":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U83"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -473,9 +473,9 @@ } }, "connections":[ - ["_U102.out","PE_init_U104.data.in.0"], - ["_U103.out","PE_init_U104.data.in.1"], - ["self.d.0","PE_init_U104.data.out"], + ["_U71.out","PE_init_U73.data.in.0"], + ["_U72.out","PE_init_U73.data.in.1"], + ["self.d.0","PE_init_U73.data.out"], ["self.clk","op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.clk"], ["op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.clk_en"], ["self.d.1","op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.data_out_0"], @@ -498,14 +498,6 @@ ["op_hcompute_demosaicked_1_stencil_2_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_b_b_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -513,8 +505,8 @@ }, "ub_b_b_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[339],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[332],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_b_b_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -523,8 +515,8 @@ }, "ub_b_b_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[339],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[332],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[606],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[606],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -548,22 +540,14 @@ ["reset","BitIn"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid","Bit"], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write_valid","Bit"], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid","Bit"], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid","Bit"], ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "b_b_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "b_b_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "b_b_stencil$ub_b_b_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -571,8 +555,8 @@ }, "b_b_stencil$ub_b_b_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[339],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[332],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "b_b_stencil$ub_b_b_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -581,19 +565,10 @@ }, "b_b_stencil$ub_b_b_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[339],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[332],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[606],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "denoised_1_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[606],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} }, - "denoised_1_stencil$d_reg__U6$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, - "denoised_1_stencil$d_reg__U7$reg0":{ + "denoised_1_stencil$d_reg__U3$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -605,40 +580,8 @@ }, "denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[268],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[264],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[328],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[330],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gb_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gb_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gb_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gb_stencil$chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gb_stencil$chain_en_const_U19":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gb_stencil$chain_en_const_U21":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gb_stencil$chain_en_const_U23":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gb_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[268],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[264],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[393],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"sram2tb_1":{"cycle_starting_addr":[327],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[395],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]},"tb2out_1":{"cycle_starting_addr":[330],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gb_stencil$ub_g_gb_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -647,8 +590,8 @@ }, "g_gb_stencil$ub_g_gb_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gb_stencil$ub_g_gb_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -657,8 +600,8 @@ }, "g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gb_stencil$ub_g_gb_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -667,8 +610,8 @@ }, "g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gb_stencil$ub_g_gb_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -677,80 +620,8 @@ }, "g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_4_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_5_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_6_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_7_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gb_stencil$ub_g_gb_stencil_BANK_7_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gr_stencil$chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gr_stencil$chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gr_stencil$chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gr_stencil$chain_en_const_U31":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gr_stencil$chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gr_stencil$chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gr_stencil$chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "g_gr_stencil$chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gr_stencil$ub_g_gr_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -759,8 +630,8 @@ }, "g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gr_stencil$ub_g_gr_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -769,8 +640,8 @@ }, "g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gr_stencil$ub_g_gr_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -779,8 +650,8 @@ }, "g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "g_gr_stencil$ub_g_gr_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -789,79 +660,35 @@ }, "g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_4_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_5_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_6_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_7_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "hw_input_global_wrapper_stencil$d_reg__U42$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U13$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U43$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U14$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U44$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U15$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U45$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U16$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U46$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U17$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U47$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U18$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -873,16 +700,16 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[258],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[127],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[262],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[130],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_0":{ + "io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, "metadata":{"in2glb_0":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"write_data_starting_addr":[0],"write_data_stride":[1,56]}} }, - "io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write_0":{ + "io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, @@ -900,11 +727,11 @@ "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,64]}} }, - "io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid":{ + "io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, - "io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write_valid":{ + "io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, @@ -2313,12 +2140,12 @@ }, "op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst":{ @@ -3063,12 +2890,12 @@ }, "op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U65"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst":{ @@ -3088,12 +2915,12 @@ }, "op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U83"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[260],"dimensionality":1,"extent":[14],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55],"sram2tb_0":{"cycle_starting_addr":[607],"cycle_stride":[4,65],"dimensionality":2,"extent":[14,56],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -3138,7 +2965,7 @@ }, "op_hcompute_hw_output_stencil_1_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const_lutcnst":{ @@ -3148,7 +2975,7 @@ }, "op_hcompute_hw_output_stencil_2_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -3158,17 +2985,9 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[611],"cycle_stride":[1,65],"dimensionality":2,"extent":[56,56]}}], "init":["Json",null], "mode":["String","lake"]} }, - "r_r_stencil$chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "r_r_stencil$chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "r_r_stencil$ub_r_r_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -3176,8 +2995,8 @@ }, "r_r_stencil$ub_r_r_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "r_r_stencil$ub_r_r_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -3186,13 +3005,13 @@ }, "r_r_stencil$ub_r_r_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ ["b_b_stencil$ub_b_b_stencil_BANK_0_garnet.clk_en","b_b_stencil$ub_b_b_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], - ["denoised_1_stencil$d_reg__U6$reg0.out","b_b_stencil$ub_b_b_stencil_BANK_0_garnet.data_in_0"], + ["denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0","b_b_stencil$ub_b_b_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_2_b_b_stencil_3_1078$sub$binop.data.in.1","b_b_stencil$ub_b_b_stencil_BANK_0_garnet.data_out_0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_b_b_stencil_3_b_b_stencil_2_1081$binop.data.in.0","b_b_stencil$ub_b_b_stencil_BANK_0_garnet.data_out_0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_4_b_b_stencil_1_1079$sub$binop.data.in.0","b_b_stencil$ub_b_b_stencil_BANK_0_garnet.data_out_1"], @@ -3200,7 +3019,7 @@ ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_b_b_stencil_4_b_b_stencil_2_1129$binop.data.in.0","b_b_stencil$ub_b_b_stencil_BANK_0_garnet.data_out_1"], ["io1in_reset.out","b_b_stencil$ub_b_b_stencil_BANK_0_garnet.flush"], ["b_b_stencil$ub_b_b_stencil_BANK_1_garnet.clk_en","b_b_stencil$ub_b_b_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], - ["denoised_1_stencil$d_reg__U6$reg0.out","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.data_in_0"], + ["denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.data_in_0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_4_b_b_stencil_1_1079$sub$binop.data.in.1","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.data_out_0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_b_b_stencil_1_b_b_stencil_2_1049$binop.data.in.0","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.data_out_0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_b_b_stencil_1_b_b_stencil_4_1109$binop.data.in.0","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.data_out_0"], @@ -3210,20 +3029,15 @@ ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_b_b_stencil_4_b_b_stencil_2_1129$binop.data.in.1","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.data_out_1"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_1048_b_b_stencil_2_1136$mux.data.in.0","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.data_out_1"], ["io1in_reset.out","b_b_stencil$ub_b_b_stencil_BANK_1_garnet.flush"], - ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","denoised_1_stencil$d_reg__U6$reg0.in"], - ["denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0","denoised_1_stencil$d_reg__U7$reg0.in"], - ["r_r_stencil$ub_r_r_stencil_BANK_0_garnet.data_in_0","denoised_1_stencil$d_reg__U7$reg0.out"], - ["r_r_stencil$ub_r_r_stencil_BANK_1_garnet.data_in_0","denoised_1_stencil$d_reg__U7$reg0.out"], + ["denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_1","denoised_1_stencil$d_reg__U3$reg0.in"], + ["r_r_stencil$ub_r_r_stencil_BANK_0_garnet.data_in_0","denoised_1_stencil$d_reg__U3$reg0.out"], + ["r_r_stencil$ub_r_r_stencil_BANK_1_garnet.data_in_0","denoised_1_stencil$d_reg__U3$reg0.out"], ["denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.clk_en","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_in_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_0"], + ["g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_1"], + ["g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_1"], + ["g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_1"], + ["g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_in_0","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.data_out_1"], ["io1in_reset.out","denoised_1_stencil$ub_denoised_1_stencil_BANK_0_garnet.flush"], ["g_gb_stencil$ub_g_gb_stencil_BANK_0_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_0_garnet.data_in_0"], @@ -3234,159 +3048,139 @@ ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_0_garnet.flush"], ["g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_in_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_3_g_gb_stencil_4_535$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_3_540$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_3_g_gb_stencil_4_535$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_4_g_gb_stencil_2_555$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_4_g_gb_stencil_5_567$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_2_558$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_3_540$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_5_g_gb_stencil_4_572$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_14_1095$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_14_g_gb_stencil_13_1098$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_11_g_gb_stencil_15_1113$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_15_g_gb_stencil_11_1116$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.data_out_1"], ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_1_garnet.flush"], ["g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_in_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_1_g_gb_stencil_2_525$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_2_g_gb_stencil_1_530$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_1_g_gb_stencil_2_525$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_2_g_gb_stencil_6_585$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_4_g_gb_stencil_2_555$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_2_601_602$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_2_g_gb_stencil_1_530$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_2_558$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_6_g_gb_stencil_2_590$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_3_g_gb_stencil_4_535$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_4_g_gb_stencil_2_555$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_4_g_gb_stencil_5_567$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_2_558$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_3_540$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_5_g_gb_stencil_4_572$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_9_g_gb_stencil_8_834$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_9_g_gb_stencil_8_837$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_10_g_gb_stencil_11_1054$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_10_g_gb_stencil_11_1057$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_3_g_gb_stencil_4_535$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_3_540$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_12_g_gb_stencil_13_1064$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_12_g_gb_stencil_13_1067$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.data_out_1"], ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_2_garnet.flush"], ["g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_in_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_14_1095$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_14_g_gb_stencil_13_1098$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_11_g_gb_stencil_15_1113$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_15_g_gb_stencil_11_1116$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_1_g_gb_stencil_2_525$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_2_g_gb_stencil_1_530$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_7_g_gb_stencil_8_823$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_8_g_gb_stencil_7_829$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_12_g_gb_stencil_13_1064$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_11_1085$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_14_1095$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_11_g_gb_stencil_13_1090$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_12_g_gb_stencil_13_1067$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_14_g_gb_stencil_13_1098$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_1_g_gb_stencil_2_525$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_2_g_gb_stencil_6_585$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gb_stencil_4_g_gb_stencil_2_555$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_2_601_602$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_2_g_gb_stencil_1_530$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_4_g_gb_stencil_2_558$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gb_stencil_6_g_gb_stencil_2_590$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_7_g_gb_stencil_8_823$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_9_g_gb_stencil_8_834$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_8_g_gb_stencil_7_829$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_9_g_gb_stencil_8_837$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_821_843_g_gb_stencil_8$mux.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_10_g_gb_stencil_11_1054$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_11_g_gb_stencil_15_1113$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_11_1085$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_10_g_gb_stencil_11_1057$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_11_1131_1132$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_11_g_gb_stencil_13_1090$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_15_g_gb_stencil_11_1116$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.data_out_1"], ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_3_garnet.flush"], - ["g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_in_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_12_g_gb_stencil_13_1064$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_12_g_gb_stencil_13_1067$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_12_g_gb_stencil_13_1064$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_11_1085$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_14_1095$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_11_g_gb_stencil_13_1090$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_12_g_gb_stencil_13_1067$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_14_g_gb_stencil_13_1098$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.data_out_1"], - ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_4_garnet.flush"], - ["g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_in_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_10_g_gb_stencil_11_1054$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_10_g_gb_stencil_11_1057$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_10_g_gb_stencil_11_1054$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_11_g_gb_stencil_15_1113$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gb_stencil_13_g_gb_stencil_11_1085$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_10_g_gb_stencil_11_1057$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_11_1131_1132$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_11_g_gb_stencil_13_1090$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gb_stencil_15_g_gb_stencil_11_1116$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.data_out_1"], - ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_5_garnet.flush"], - ["g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_in_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_7_g_gb_stencil_8_823$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_9_g_gb_stencil_8_834$sub$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_8_g_gb_stencil_7_829$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_9_g_gb_stencil_8_837$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_821_843_g_gb_stencil_8$mux.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_9_g_gb_stencil_8_834$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_9_g_gb_stencil_8_837$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.data_out_1"], - ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_6_garnet.flush"], - ["g_gb_stencil$ub_g_gb_stencil_BANK_7_garnet.clk_en","g_gb_stencil$ub_g_gb_stencil_BANK_7_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.out","g_gb_stencil$ub_g_gb_stencil_BANK_7_garnet.data_in_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gb_stencil_7_g_gb_stencil_8_823$sub$binop.data.in.0","g_gb_stencil$ub_g_gb_stencil_BANK_7_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gb_stencil_8_g_gb_stencil_7_829$binop.data.in.1","g_gb_stencil$ub_g_gb_stencil_BANK_7_garnet.data_out_0"], - ["io1in_reset.out","g_gb_stencil$ub_g_gb_stencil_BANK_7_garnet.flush"], ["g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_5_566$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_5_g_gr_stencil_4_569$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_6_g_gr_stencil_4_584$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_6_g_gr_stencil_4_587$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_1_g_gr_stencil_3_534$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_3_g_gr_stencil_1_537$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_5_566$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_5_g_gr_stencil_4_569$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.data_out_1"], ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_0_garnet.flush"], ["g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_1_g_gr_stencil_3_534$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_3_g_gr_stencil_1_537$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_1_556$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_5_566$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_6_g_gr_stencil_4_584$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_4_g_gr_stencil_1_561$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_5_g_gr_stencil_4_569$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_6_g_gr_stencil_4_587$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_14_1096$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_14_g_gr_stencil_13_1101$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_6_g_gr_stencil_4_584$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_6_g_gr_stencil_4_587$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_15_g_gr_stencil_13_1114$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_15_g_gr_stencil_13_1119$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.data_out_1"], ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_1_garnet.flush"], ["g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_1_g_gr_stencil_3_534$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_2_g_gr_stencil_1_524$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_1_556$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_1_522_523$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_1_g_gr_stencil_2_527$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_3_g_gr_stencil_1_537$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_4_g_gr_stencil_1_561$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_2_g_gr_stencil_1_524$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_1_g_gr_stencil_2_527$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_1_556$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_5_566$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_6_g_gr_stencil_4_584$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_4_g_gr_stencil_1_561$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_5_g_gr_stencil_4_569$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_6_g_gr_stencil_4_587$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_9_g_gr_stencil_7_835$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_9_g_gr_stencil_7_840$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_11_g_gr_stencil_10_1055$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_11_g_gr_stencil_10_1060$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_10_g_gr_stencil_12_1065$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_12_g_gr_stencil_10_1070$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.data_out_1"], ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_2_garnet.flush"], ["g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_14_1096$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_14_g_gr_stencil_13_1101$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_15_g_gr_stencil_13_1114$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_15_g_gr_stencil_13_1119$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_1_g_gr_stencil_3_534$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_2_g_gr_stencil_1_524$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_4_g_gr_stencil_1_556$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_1_522_523$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_1_g_gr_stencil_2_527$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_3_g_gr_stencil_1_537$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_4_g_gr_stencil_1_561$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_8_g_gr_stencil_7_822$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_9_g_gr_stencil_7_835$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_7_g_gr_stencil_8_825$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_9_g_gr_stencil_7_840$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_821_g_gr_stencil_7_832$mux.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_10_g_gr_stencil_12_1065$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_11_g_gr_stencil_10_1055$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_10_1084$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_10_1052_1053$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_10_g_gr_stencil_13_1087$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_11_g_gr_stencil_10_1060$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_12_g_gr_stencil_10_1070$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_0"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_g_gr_stencil_2_g_gr_stencil_1_524$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_g_gr_stencil_1_g_gr_stencil_2_527$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_8_g_gr_stencil_7_822$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_7_g_gr_stencil_8_825$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_10_1084$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_14_1096$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_15_g_gr_stencil_13_1114$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_10_g_gr_stencil_13_1087$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_14_g_gr_stencil_13_1101$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_15_g_gr_stencil_13_1119$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.data_out_1"], ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_3_garnet.flush"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_10_g_gr_stencil_12_1065$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_12_g_gr_stencil_10_1070$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_10_1084$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_14_1096$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_15_g_gr_stencil_13_1114$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_10_g_gr_stencil_13_1087$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_14_g_gr_stencil_13_1101$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_15_g_gr_stencil_13_1119$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.data_out_1"], - ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_4_garnet.flush"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_10_g_gr_stencil_12_1065$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_11_g_gr_stencil_10_1055$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_13_g_gr_stencil_10_1084$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_10_1052_1053$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_10_g_gr_stencil_13_1087$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_11_g_gr_stencil_10_1060$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_12_g_gr_stencil_10_1070$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_g_gr_stencil_11_g_gr_stencil_10_1055$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_g_gr_stencil_11_g_gr_stencil_10_1060$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.data_out_1"], - ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_5_garnet.flush"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_8_g_gr_stencil_7_822$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_7_g_gr_stencil_8_825$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_9_g_gr_stencil_7_835$sub$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet.data_out_1"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_9_g_gr_stencil_7_840$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet.data_out_1"], - ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_6_garnet.flush"], - ["g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.clk_en","g_gr_stencil$ub_g_gr_stencil_BANK_7_clk_en_const_lutcnst.bit.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_8_g_gr_stencil_7_822$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_g_gr_stencil_9_g_gr_stencil_7_835$sub$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_7_g_gr_stencil_8_825$binop.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_g_gr_stencil_9_g_gr_stencil_7_840$binop.data.in.1","g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.data_out_0"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_821_g_gr_stencil_7_832$mux.data.in.0","g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.data_out_0"], - ["io1in_reset.out","g_gr_stencil$ub_g_gr_stencil_BANK_7_garnet.flush"], - ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U42$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U43$reg0.in","hw_input_global_wrapper_stencil$d_reg__U42$reg0.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_2_328_329$cgramax.data.in.0","hw_input_global_wrapper_stencil$d_reg__U43$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U44$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U45$reg0.in","hw_input_global_wrapper_stencil$d_reg__U44$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U46$reg0.in","hw_input_global_wrapper_stencil$d_reg__U45$reg0.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.in.0","hw_input_global_wrapper_stencil$d_reg__U45$reg0.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$ucomp$compop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U45$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U47$reg0.in","hw_input_global_wrapper_stencil$d_reg__U46$reg0.out"], - ["op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_5_327$cgramax.data.in.0","hw_input_global_wrapper_stencil$d_reg__U47$reg0.out"], + ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U13$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U14$reg0.in","hw_input_global_wrapper_stencil$d_reg__U13$reg0.out"], + ["op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_2_328_329$cgramax.data.in.0","hw_input_global_wrapper_stencil$d_reg__U14$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U15$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U16$reg0.in","hw_input_global_wrapper_stencil$d_reg__U15$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U17$reg0.in","hw_input_global_wrapper_stencil$d_reg__U16$reg0.out"], + ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$min_mux$mux.data.in.0","hw_input_global_wrapper_stencil$d_reg__U16$reg0.out"], + ["op_hcompute_denoised_1_stencil$inner_compute$umin_hw_input_global_wrapper_stencil_1_329_330$ucomp$compop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U16$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U18$reg0.in","hw_input_global_wrapper_stencil$d_reg__U17$reg0.out"], + ["op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_5_327$cgramax.data.in.0","hw_input_global_wrapper_stencil$d_reg__U18$reg0.out"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_3_327_328$cgramax.data.in.0","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0"], ["op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_5_327$cgramax.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.flush"], - ["op_hcompute_curved_stencil_1$inner_compute$rom_curvea0$1_rom.data_out_0","io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_0.in"], - ["op_hcompute_curved_stencil$inner_compute$rom_curvea0_rom.data_out_0","io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write_0.in"], + ["op_hcompute_curved_stencil$inner_compute$rom_curvea0_rom.data_out_0","io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_0.in"], + ["op_hcompute_curved_stencil_1$inner_compute$rom_curvea0$1_rom.data_out_0","io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_0.in"], ["op_hcompute_curved_stencil_2$inner_compute$rom_curvea0$2_rom.data_out_0","io16_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_0.in"], - ["op_hcompute_hw_output_stencil_1_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid.in"], - ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write_valid.in"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid.in"], + ["op_hcompute_hw_output_stencil_1_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid.in"], ["op_hcompute_hw_output_stencil_2_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid.in"], ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.flush","io1in_reset.out"], ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.flush","io1in_reset.out"], @@ -3412,8 +3206,8 @@ ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_2_1323_1331$min_mux$mux.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p10000__1323$11.out"], ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_3_1323_1338$ucomp$compop.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p10000__1323$2.out"], ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_3_1323_1338$min_mux$mux.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p10000__1323$21.out"], - ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_1_1323_1324$ucomp$compop.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p10000__1323.out"], - ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p10000__13231.out"], + ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p10000__1323.out"], + ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_1_1323_1324$ucomp$compop.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p10000__13231.out"], ["op_hcompute_corrected_stencil$inner_compute$mult_middle_1325549_1330$mult_1.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p549_549$1.out"], ["op_hcompute_corrected_stencil$inner_compute$mult_middle_13397_1343$mult_1.data.in.1","op_hcompute_corrected_stencil$inner_compute$const_p7_7$1.out"], ["op_hcompute_corrected_stencil$inner_compute$umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.out","op_hcompute_corrected_stencil$inner_compute$mult_middle_1325549_1330$mult_1.data.in.0"], @@ -3467,8 +3261,8 @@ ["op_hcompute_curved_stencil_2$inner_compute$smin_corrected_stencil_3_5651_5652$scomp$compop.data.in.0","op_hcompute_corrected_stencil_2$inner_compute$add_1478_1479_1480$binop.data.out"], ["op_hcompute_corrected_stencil_2$inner_compute$mult_middle_1466n261_1470$mult_1.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_n261_n261$1.out"], ["op_hcompute_corrected_stencil_2$inner_compute$mult_middle_1459n31_1464$mult_1.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_n31_n31$1.out"], - ["op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_8_1457_1465$ucomp$compop.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_p10000__1457$1.out"], - ["op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_8_1457_1465$min_mux$mux.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_p10000__1457$11.out"], + ["op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_8_1457_1465$min_mux$mux.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_p10000__1457$1.out"], + ["op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_8_1457_1465$ucomp$compop.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_p10000__1457$11.out"], ["op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_9_1457_1472$ucomp$compop.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_p10000__1457$2.out"], ["op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_9_1457_1472$min_mux$mux.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_p10000__1457$21.out"], ["op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_7_1457_1458$ucomp$compop.data.in.1","op_hcompute_corrected_stencil_2$inner_compute$const_p10000__1457.out"], @@ -3487,8 +3281,8 @@ ["op_hcompute_demosaicked_1_stencil$inner_compute$mux_516_548_607$mux.data.out","op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_9_1457_1472$min_mux$mux.data.in.0"], ["op_hcompute_demosaicked_1_stencil$inner_compute$mux_516_548_607$mux.data.out","op_hcompute_corrected_stencil_2$inner_compute$umin_demosaicked_1_stencil_9_1457_1472$ucomp$compop.data.in.0"], ["op_hcompute_curved_stencil$inner_compute$smax_3560_3561_3562$cgramax.data.in.1","op_hcompute_curved_stencil$inner_compute$const_p0__3561.out"], - ["op_hcompute_curved_stencil$inner_compute$smin_corrected_stencil_1_3559_3560$min_mux$mux.data.in.1","op_hcompute_curved_stencil$inner_compute$const_p1023__3559.out"], - ["op_hcompute_curved_stencil$inner_compute$smin_corrected_stencil_1_3559_3560$scomp$compop.data.in.1","op_hcompute_curved_stencil$inner_compute$const_p1023__35591.out"], + ["op_hcompute_curved_stencil$inner_compute$smin_corrected_stencil_1_3559_3560$scomp$compop.data.in.1","op_hcompute_curved_stencil$inner_compute$const_p1023__3559.out"], + ["op_hcompute_curved_stencil$inner_compute$smin_corrected_stencil_1_3559_3560$min_mux$mux.data.in.1","op_hcompute_curved_stencil$inner_compute$const_p1023__35591.out"], ["op_hcompute_curved_stencil$inner_compute$rom_curvea0_rom.ren_in_0","op_hcompute_curved_stencil$inner_compute$rom_curvea0_ren_lutcnst.bit.out"], ["op_hcompute_curved_stencil$inner_compute$smax_3560_3561_3562$cgramax.data.out","op_hcompute_curved_stencil$inner_compute$rom_curvea0_rom.addr_in_0"], ["op_hcompute_curved_stencil$inner_compute$smin_corrected_stencil_1_3559_3560$min_mux$mux.data.out","op_hcompute_curved_stencil$inner_compute$smax_3560_3561_3562$cgramax.data.in.0"], @@ -3501,8 +3295,8 @@ ["op_hcompute_curved_stencil_1$inner_compute$smin_corrected_stencil_2_4605_4606$min_mux$mux.data.out","op_hcompute_curved_stencil_1$inner_compute$smax_4606_4607_4608$cgramax.data.in.0"], ["op_hcompute_curved_stencil_1$inner_compute$smin_corrected_stencil_2_4605_4606$scomp$compop.bit.out","op_hcompute_curved_stencil_1$inner_compute$smin_corrected_stencil_2_4605_4606$min_mux$mux.bit.in.0"], ["op_hcompute_curved_stencil_2$inner_compute$smax_5652_5653_5654$cgramax.data.in.1","op_hcompute_curved_stencil_2$inner_compute$const_p0__5653.out"], - ["op_hcompute_curved_stencil_2$inner_compute$smin_corrected_stencil_3_5651_5652$min_mux$mux.data.in.1","op_hcompute_curved_stencil_2$inner_compute$const_p1023__5651.out"], - ["op_hcompute_curved_stencil_2$inner_compute$smin_corrected_stencil_3_5651_5652$scomp$compop.data.in.1","op_hcompute_curved_stencil_2$inner_compute$const_p1023__56511.out"], + ["op_hcompute_curved_stencil_2$inner_compute$smin_corrected_stencil_3_5651_5652$scomp$compop.data.in.1","op_hcompute_curved_stencil_2$inner_compute$const_p1023__5651.out"], + ["op_hcompute_curved_stencil_2$inner_compute$smin_corrected_stencil_3_5651_5652$min_mux$mux.data.in.1","op_hcompute_curved_stencil_2$inner_compute$const_p1023__56511.out"], ["op_hcompute_curved_stencil_2$inner_compute$rom_curvea0$2_rom.ren_in_0","op_hcompute_curved_stencil_2$inner_compute$rom_curvea0$2_ren_lutcnst.bit.out"], ["op_hcompute_curved_stencil_2$inner_compute$smax_5652_5653_5654$cgramax.data.out","op_hcompute_curved_stencil_2$inner_compute$rom_curvea0$2_rom.addr_in_0"], ["op_hcompute_curved_stencil_2$inner_compute$smin_corrected_stencil_3_5651_5652$min_mux$mux.data.out","op_hcompute_curved_stencil_2$inner_compute$smax_5652_5653_5654$cgramax.data.in.0"], @@ -3717,8 +3511,8 @@ ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_824_828_831$mux.data.out","op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_821_g_gr_stencil_7_832$mux.data.in.1"], ["op_hcompute_demosaicked_1_stencil_1$inner_compute$ult_822_823_824$compop.bit.out","op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_824_828_831$mux.bit.in.0"], ["op_hcompute_demosaicked_1_stencil_1$inner_compute$ult_834_835_836$compop.bit.out","op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_836_839_842$mux.bit.in.0"], - ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_2_b_b_stencil_3_1078$sub$binop.data.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_2_b_b_stencil_3_1078$abs$abs.data.in.0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_1078_1079_1080$compop.data.in.0","op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_2_b_b_stencil_3_1078$abs$abs.data.out"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_4_b_b_stencil_1_1079$sub$binop.data.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_b_b_stencil_4_b_b_stencil_1_1079$abs$abs.data.in.0"], @@ -3871,8 +3665,8 @@ ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_1084_1085_1086$compop.bit.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_1086_1089_1092$mux.bit.in.0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_1095_1096_1097$compop.bit.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_1097_1100_1103$mux.bit.in.0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_1113_1114_1115$compop.bit.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_1115_1118_1121$mux.bit.in.0"], - ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.clk_en"], ["op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_3_327_328$cgramax.data.out","op_hcompute_denoised_1_stencil$inner_compute$umax_hw_input_global_wrapper_stencil_2_328_329$cgramax.data.in.1"], @@ -4057,8 +3851,8 @@ ["inner_compute$umin_demosaicked_1_stencil_2_1323_1331$min_mux$mux.data.in.1","inner_compute$const_p10000__1323$11.out"], ["inner_compute$umin_demosaicked_1_stencil_3_1323_1338$ucomp$compop.data.in.1","inner_compute$const_p10000__1323$2.out"], ["inner_compute$umin_demosaicked_1_stencil_3_1323_1338$min_mux$mux.data.in.1","inner_compute$const_p10000__1323$21.out"], - ["inner_compute$umin_demosaicked_1_stencil_1_1323_1324$ucomp$compop.data.in.1","inner_compute$const_p10000__1323.out"], - ["inner_compute$umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.in.1","inner_compute$const_p10000__13231.out"], + ["inner_compute$umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.in.1","inner_compute$const_p10000__1323.out"], + ["inner_compute$umin_demosaicked_1_stencil_1_1323_1324$ucomp$compop.data.in.1","inner_compute$const_p10000__13231.out"], ["inner_compute$mult_middle_1325549_1330$mult_1.data.in.1","inner_compute$const_p549_549$1.out"], ["inner_compute$mult_middle_13397_1343$mult_1.data.in.1","inner_compute$const_p7_7$1.out"], ["inner_compute$umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.out","inner_compute$mult_middle_1325549_1330$mult_1.data.in.0"], @@ -4358,8 +4152,8 @@ ["self.corrected_stencil_op_hcompute_corrected_stencil_2_write.0","inner_compute$add_1478_1479_1480$binop.data.out"], ["inner_compute$mult_middle_1466n261_1470$mult_1.data.in.1","inner_compute$const_n261_n261$1.out"], ["inner_compute$mult_middle_1459n31_1464$mult_1.data.in.1","inner_compute$const_n31_n31$1.out"], - ["inner_compute$umin_demosaicked_1_stencil_8_1457_1465$ucomp$compop.data.in.1","inner_compute$const_p10000__1457$1.out"], - ["inner_compute$umin_demosaicked_1_stencil_8_1457_1465$min_mux$mux.data.in.1","inner_compute$const_p10000__1457$11.out"], + ["inner_compute$umin_demosaicked_1_stencil_8_1457_1465$min_mux$mux.data.in.1","inner_compute$const_p10000__1457$1.out"], + ["inner_compute$umin_demosaicked_1_stencil_8_1457_1465$ucomp$compop.data.in.1","inner_compute$const_p10000__1457$11.out"], ["inner_compute$umin_demosaicked_1_stencil_9_1457_1472$ucomp$compop.data.in.1","inner_compute$const_p10000__1457$2.out"], ["inner_compute$umin_demosaicked_1_stencil_9_1457_1472$min_mux$mux.data.in.1","inner_compute$const_p10000__1457$21.out"], ["inner_compute$umin_demosaicked_1_stencil_7_1457_1458$ucomp$compop.data.in.1","inner_compute$const_p10000__1457.out"], @@ -4432,8 +4226,8 @@ }, "connections":[ ["inner_compute$smax_3560_3561_3562$cgramax.data.in.1","inner_compute$const_p0__3561.out"], - ["inner_compute$smin_corrected_stencil_1_3559_3560$min_mux$mux.data.in.1","inner_compute$const_p1023__3559.out"], - ["inner_compute$smin_corrected_stencil_1_3559_3560$scomp$compop.data.in.1","inner_compute$const_p1023__35591.out"], + ["inner_compute$smin_corrected_stencil_1_3559_3560$scomp$compop.data.in.1","inner_compute$const_p1023__3559.out"], + ["inner_compute$smin_corrected_stencil_1_3559_3560$min_mux$mux.data.in.1","inner_compute$const_p1023__35591.out"], ["inner_compute$rom_curvea0_rom.ren_in_0","inner_compute$rom_curvea0_ren_lutcnst.bit.out"], ["inner_compute$smax_3560_3561_3562$cgramax.data.out","inner_compute$rom_curvea0_rom.addr_in_0"], ["self.curved_stencil_op_hcompute_curved_stencil_write.0","inner_compute$rom_curvea0_rom.data_out_0"], @@ -4560,8 +4354,8 @@ }, "connections":[ ["inner_compute$smax_5652_5653_5654$cgramax.data.in.1","inner_compute$const_p0__5653.out"], - ["inner_compute$smin_corrected_stencil_3_5651_5652$min_mux$mux.data.in.1","inner_compute$const_p1023__5651.out"], - ["inner_compute$smin_corrected_stencil_3_5651_5652$scomp$compop.data.in.1","inner_compute$const_p1023__56511.out"], + ["inner_compute$smin_corrected_stencil_3_5651_5652$scomp$compop.data.in.1","inner_compute$const_p1023__5651.out"], + ["inner_compute$smin_corrected_stencil_3_5651_5652$min_mux$mux.data.in.1","inner_compute$const_p1023__56511.out"], ["inner_compute$rom_curvea0$2_rom.ren_in_0","inner_compute$rom_curvea0$2_ren_lutcnst.bit.out"], ["inner_compute$smax_5652_5653_5654$cgramax.data.out","inner_compute$rom_curvea0$2_rom.addr_in_0"], ["self.curved_stencil_op_hcompute_curved_stencil_2_write.0","inner_compute$rom_curvea0$2_rom.data_out_0"], @@ -6866,10 +6660,10 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["curved_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_write.0","self.curved_stencil_op_hcompute_hw_output_stencil_read.0"], + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write.0","self.curved_stencil_op_hcompute_hw_output_stencil_read.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6879,10 +6673,10 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["curved_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write.0","self.curved_stencil_op_hcompute_hw_output_stencil_1_read.0"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write.0","self.curved_stencil_op_hcompute_hw_output_stencil_1_read.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6983,16 +6777,7 @@ ["op_hcompute_r_r_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U6$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, - "d_reg__U7$reg0":{ + "d_reg__U3$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -7004,21 +6789,19 @@ }, "ub_denoised_1_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[268],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[264],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[328],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[330],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[268],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[264],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[393],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"sram2tb_1":{"cycle_starting_addr":[327],"cycle_stride":[4,65],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[395],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]},"tb2out_1":{"cycle_starting_addr":[330],"cycle_stride":[1,65],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["self.clk","d_reg__U6$reg0.clk"], - ["self.op_hcompute_denoised_1_stencil_write.0","d_reg__U6$reg0.in"], - ["self.op_hcompute_b_b_stencil_read.0","d_reg__U6$reg0.out"], - ["self.clk","d_reg__U7$reg0.clk"], - ["ub_denoised_1_stencil_BANK_0_garnet.data_out_0","d_reg__U7$reg0.in"], - ["self.op_hcompute_r_r_stencil_read.0","d_reg__U7$reg0.out"], + ["self.clk","d_reg__U3$reg0.clk"], + ["ub_denoised_1_stencil_BANK_0_garnet.data_out_1","d_reg__U3$reg0.in"], + ["self.op_hcompute_r_r_stencil_read.0","d_reg__U3$reg0.out"], ["ub_denoised_1_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_denoised_1_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_b_b_stencil_read.0"], ["self.op_hcompute_g_gb_stencil_read.0","self.op_hcompute_denoised_1_stencil_write.0"], ["ub_denoised_1_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_denoised_1_stencil_write.0"], - ["ub_denoised_1_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_g_gr_stencil_read.0"], + ["ub_denoised_1_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_g_gr_stencil_read.0"], ["ub_denoised_1_stencil_BANK_0_garnet.flush","self.reset"], ["ub_denoised_1_stencil_BANK_0_garnet.clk_en","ub_denoised_1_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] @@ -7038,38 +6821,6 @@ ["op_hcompute_g_gb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U19":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U21":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U23":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_g_gb_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -7077,8 +6828,8 @@ }, "ub_g_gb_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_g_gb_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -7087,8 +6838,8 @@ }, "ub_g_gb_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_g_gb_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -7097,8 +6848,8 @@ }, "ub_g_gb_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_g_gb_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -7107,48 +6858,8 @@ }, "ub_g_gb_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gb_stencil_BANK_4_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gb_stencil_BANK_4_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gb_stencil_BANK_5_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gb_stencil_BANK_5_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gb_stencil_BANK_6_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gb_stencil_BANK_6_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gb_stencil_BANK_7_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gb_stencil_BANK_7_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -7156,49 +6867,33 @@ ["ub_g_gb_stencil_BANK_1_garnet.clk","self.clk"], ["ub_g_gb_stencil_BANK_2_garnet.clk","self.clk"], ["ub_g_gb_stencil_BANK_3_garnet.clk","self.clk"], - ["ub_g_gb_stencil_BANK_4_garnet.clk","self.clk"], - ["ub_g_gb_stencil_BANK_5_garnet.clk","self.clk"], - ["ub_g_gb_stencil_BANK_6_garnet.clk","self.clk"], - ["ub_g_gb_stencil_BANK_7_garnet.clk","self.clk"], - ["ub_g_gb_stencil_BANK_7_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], - ["ub_g_gb_stencil_BANK_6_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.1"], - ["ub_g_gb_stencil_BANK_6_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.2"], - ["ub_g_gb_stencil_BANK_5_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], - ["ub_g_gb_stencil_BANK_5_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.1"], - ["ub_g_gb_stencil_BANK_4_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.2"], - ["ub_g_gb_stencil_BANK_4_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.3"], - ["ub_g_gb_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], - ["ub_g_gb_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], - ["ub_g_gb_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], - ["ub_g_gb_stencil_BANK_2_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], - ["ub_g_gb_stencil_BANK_1_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.2"], - ["ub_g_gb_stencil_BANK_1_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.3"], + ["ub_g_gb_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], + ["ub_g_gb_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.1"], + ["ub_g_gb_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.2"], + ["ub_g_gb_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], + ["ub_g_gb_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.1"], + ["ub_g_gb_stencil_BANK_2_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.2"], + ["ub_g_gb_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.3"], + ["ub_g_gb_stencil_BANK_1_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], + ["ub_g_gb_stencil_BANK_1_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], + ["ub_g_gb_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], + ["ub_g_gb_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], + ["ub_g_gb_stencil_BANK_2_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.2"], + ["ub_g_gb_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.3"], ["ub_g_gb_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.4"], ["ub_g_gb_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.5"], ["ub_g_gb_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_1_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_2_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_3_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_4_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_5_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_6_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], - ["ub_g_gb_stencil_BANK_7_garnet.data_in_0","self.op_hcompute_g_gb_stencil_write.0"], ["ub_g_gb_stencil_BANK_0_garnet.flush","self.reset"], ["ub_g_gb_stencil_BANK_1_garnet.flush","self.reset"], ["ub_g_gb_stencil_BANK_2_garnet.flush","self.reset"], ["ub_g_gb_stencil_BANK_3_garnet.flush","self.reset"], - ["ub_g_gb_stencil_BANK_4_garnet.flush","self.reset"], - ["ub_g_gb_stencil_BANK_5_garnet.flush","self.reset"], - ["ub_g_gb_stencil_BANK_6_garnet.flush","self.reset"], - ["ub_g_gb_stencil_BANK_7_garnet.flush","self.reset"], ["ub_g_gb_stencil_BANK_0_garnet.clk_en","ub_g_gb_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["ub_g_gb_stencil_BANK_1_garnet.clk_en","ub_g_gb_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], ["ub_g_gb_stencil_BANK_2_garnet.clk_en","ub_g_gb_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], - ["ub_g_gb_stencil_BANK_3_garnet.clk_en","ub_g_gb_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], - ["ub_g_gb_stencil_BANK_4_garnet.clk_en","ub_g_gb_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], - ["ub_g_gb_stencil_BANK_5_garnet.clk_en","ub_g_gb_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], - ["ub_g_gb_stencil_BANK_6_garnet.clk_en","ub_g_gb_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], - ["ub_g_gb_stencil_BANK_7_garnet.clk_en","ub_g_gb_stencil_BANK_7_clk_en_const_lutcnst.bit.out"] + ["ub_g_gb_stencil_BANK_3_garnet.clk_en","ub_g_gb_stencil_BANK_3_clk_en_const_lutcnst.bit.out"] ] }, "g_gr_stencil_ub":{ @@ -7216,38 +6911,6 @@ ["op_hcompute_g_gr_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U31":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_g_gr_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -7255,8 +6918,8 @@ }, "ub_g_gr_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[607],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[14],"write_data_stride":[1,0,3]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[56],"read_data_stride":[0,1,0,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_g_gr_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -7265,8 +6928,8 @@ }, "ub_g_gr_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_g_gr_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -7275,8 +6938,8 @@ }, "ub_g_gr_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_g_gr_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -7285,48 +6948,8 @@ }, "ub_g_gr_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[2],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[66],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gr_stencil_BANK_4_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gr_stencil_BANK_4_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gr_stencil_BANK_5_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gr_stencil_BANK_5_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gr_stencil_BANK_6_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gr_stencil_BANK_6_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[16],"read_data_stride":[1,0,8],"write_data_starting_addr":[16],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[65],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "ub_g_gr_stencil_BANK_7_clk_en_const_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "ub_g_gr_stencil_BANK_7_garnet":{ - "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[337],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[330],"cycle_stride":[2,130],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[603],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[34],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -7334,49 +6957,33 @@ ["ub_g_gr_stencil_BANK_1_garnet.clk","self.clk"], ["ub_g_gr_stencil_BANK_2_garnet.clk","self.clk"], ["ub_g_gr_stencil_BANK_3_garnet.clk","self.clk"], - ["ub_g_gr_stencil_BANK_4_garnet.clk","self.clk"], - ["ub_g_gr_stencil_BANK_5_garnet.clk","self.clk"], - ["ub_g_gr_stencil_BANK_6_garnet.clk","self.clk"], - ["ub_g_gr_stencil_BANK_7_garnet.clk","self.clk"], - ["ub_g_gr_stencil_BANK_7_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], - ["ub_g_gr_stencil_BANK_6_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.1"], - ["ub_g_gr_stencil_BANK_6_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.2"], - ["ub_g_gr_stencil_BANK_5_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], - ["ub_g_gr_stencil_BANK_5_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.1"], - ["ub_g_gr_stencil_BANK_4_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.2"], - ["ub_g_gr_stencil_BANK_4_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.3"], - ["ub_g_gr_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], - ["ub_g_gr_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], - ["ub_g_gr_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], - ["ub_g_gr_stencil_BANK_2_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], - ["ub_g_gr_stencil_BANK_1_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.2"], - ["ub_g_gr_stencil_BANK_1_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.3"], - ["ub_g_gr_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.4"], - ["ub_g_gr_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.5"], + ["ub_g_gr_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.0"], + ["ub_g_gr_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_1_read.1"], + ["ub_g_gr_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.2"], + ["ub_g_gr_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.0"], + ["ub_g_gr_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.1"], + ["ub_g_gr_stencil_BANK_2_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.2"], + ["ub_g_gr_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.3"], + ["ub_g_gr_stencil_BANK_1_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_2_read.4"], + ["ub_g_gr_stencil_BANK_1_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_2_read.5"], + ["ub_g_gr_stencil_BANK_3_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.0"], + ["ub_g_gr_stencil_BANK_3_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.1"], + ["ub_g_gr_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.2"], + ["ub_g_gr_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_read.3"], + ["ub_g_gr_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.4"], + ["ub_g_gr_stencil_BANK_1_garnet.data_out_1","self.op_hcompute_demosaicked_1_stencil_read.5"], ["ub_g_gr_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_1_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_2_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_3_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_4_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_5_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_6_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], - ["ub_g_gr_stencil_BANK_7_garnet.data_in_0","self.op_hcompute_g_gr_stencil_write.0"], ["ub_g_gr_stencil_BANK_0_garnet.flush","self.reset"], ["ub_g_gr_stencil_BANK_1_garnet.flush","self.reset"], ["ub_g_gr_stencil_BANK_2_garnet.flush","self.reset"], ["ub_g_gr_stencil_BANK_3_garnet.flush","self.reset"], - ["ub_g_gr_stencil_BANK_4_garnet.flush","self.reset"], - ["ub_g_gr_stencil_BANK_5_garnet.flush","self.reset"], - ["ub_g_gr_stencil_BANK_6_garnet.flush","self.reset"], - ["ub_g_gr_stencil_BANK_7_garnet.flush","self.reset"], ["ub_g_gr_stencil_BANK_0_garnet.clk_en","ub_g_gr_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["ub_g_gr_stencil_BANK_1_garnet.clk_en","ub_g_gr_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], ["ub_g_gr_stencil_BANK_2_garnet.clk_en","ub_g_gr_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], - ["ub_g_gr_stencil_BANK_3_garnet.clk_en","ub_g_gr_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], - ["ub_g_gr_stencil_BANK_4_garnet.clk_en","ub_g_gr_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], - ["ub_g_gr_stencil_BANK_5_garnet.clk_en","ub_g_gr_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], - ["ub_g_gr_stencil_BANK_6_garnet.clk_en","ub_g_gr_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], - ["ub_g_gr_stencil_BANK_7_garnet.clk_en","ub_g_gr_stencil_BANK_7_clk_en_const_lutcnst.bit.out"] + ["ub_g_gr_stencil_BANK_3_garnet.clk_en","ub_g_gr_stencil_BANK_3_clk_en_const_lutcnst.bit.out"] ] }, "hcompute_b_b_stencil":{ @@ -7518,8 +7125,8 @@ ["umin_demosaicked_1_stencil_2_1323_1331$min_mux$mux.data.in.1","const_p10000__1323$11.out"], ["umin_demosaicked_1_stencil_3_1323_1338$ucomp$compop.data.in.1","const_p10000__1323$2.out"], ["umin_demosaicked_1_stencil_3_1323_1338$min_mux$mux.data.in.1","const_p10000__1323$21.out"], - ["umin_demosaicked_1_stencil_1_1323_1324$ucomp$compop.data.in.1","const_p10000__1323.out"], - ["umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.in.1","const_p10000__13231.out"], + ["umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.in.1","const_p10000__1323.out"], + ["umin_demosaicked_1_stencil_1_1323_1324$ucomp$compop.data.in.1","const_p10000__13231.out"], ["mult_middle_1325549_1330$mult_1.data.in.1","const_p549_549$1.out"], ["mult_middle_13397_1343$mult_1.data.in.1","const_p7_7$1.out"], ["umin_demosaicked_1_stencil_1_1323_1324$min_mux$mux.data.out","mult_middle_1325549_1330$mult_1.data.in.0"], @@ -7811,8 +7418,8 @@ ["self.out_corrected_stencil","add_1478_1479_1480$binop.data.out"], ["mult_middle_1466n261_1470$mult_1.data.in.1","const_n261_n261$1.out"], ["mult_middle_1459n31_1464$mult_1.data.in.1","const_n31_n31$1.out"], - ["umin_demosaicked_1_stencil_8_1457_1465$ucomp$compop.data.in.1","const_p10000__1457$1.out"], - ["umin_demosaicked_1_stencil_8_1457_1465$min_mux$mux.data.in.1","const_p10000__1457$11.out"], + ["umin_demosaicked_1_stencil_8_1457_1465$min_mux$mux.data.in.1","const_p10000__1457$1.out"], + ["umin_demosaicked_1_stencil_8_1457_1465$ucomp$compop.data.in.1","const_p10000__1457$11.out"], ["umin_demosaicked_1_stencil_9_1457_1472$ucomp$compop.data.in.1","const_p10000__1457$2.out"], ["umin_demosaicked_1_stencil_9_1457_1472$min_mux$mux.data.in.1","const_p10000__1457$21.out"], ["umin_demosaicked_1_stencil_7_1457_1458$ucomp$compop.data.in.1","const_p10000__1457.out"], @@ -10322,36 +9929,32 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U42$reg0":{ + "d_reg__U13$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U43$reg0":{ + "d_reg__U14$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U44$reg0":{ + "d_reg__U15$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U45$reg0":{ + "d_reg__U16$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U46$reg0":{ + "d_reg__U17$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U47$reg0":{ + "d_reg__U18$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -10363,26 +9966,26 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[258],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[127],"cycle_stride":[4,65],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[262],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[130],"cycle_stride":[1,65],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["self.clk","d_reg__U42$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U42$reg0.in"], - ["d_reg__U43$reg0.in","d_reg__U42$reg0.out"], - ["self.clk","d_reg__U43$reg0.clk"], - ["self.op_hcompute_denoised_1_stencil_read.1","d_reg__U43$reg0.out"], - ["self.clk","d_reg__U44$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U44$reg0.in"], - ["d_reg__U45$reg0.in","d_reg__U44$reg0.out"], - ["self.clk","d_reg__U45$reg0.clk"], - ["d_reg__U46$reg0.in","d_reg__U45$reg0.out"], - ["self.op_hcompute_denoised_1_stencil_read.0","d_reg__U45$reg0.out"], - ["self.clk","d_reg__U46$reg0.clk"], - ["d_reg__U47$reg0.in","d_reg__U46$reg0.out"], - ["self.clk","d_reg__U47$reg0.clk"], - ["self.op_hcompute_denoised_1_stencil_read.3","d_reg__U47$reg0.out"], + ["self.clk","d_reg__U13$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U13$reg0.in"], + ["d_reg__U14$reg0.in","d_reg__U13$reg0.out"], + ["self.clk","d_reg__U14$reg0.clk"], + ["self.op_hcompute_denoised_1_stencil_read.1","d_reg__U14$reg0.out"], + ["self.clk","d_reg__U15$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U15$reg0.in"], + ["d_reg__U16$reg0.in","d_reg__U15$reg0.out"], + ["self.clk","d_reg__U16$reg0.clk"], + ["d_reg__U17$reg0.in","d_reg__U16$reg0.out"], + ["self.op_hcompute_denoised_1_stencil_read.0","d_reg__U16$reg0.out"], + ["self.clk","d_reg__U17$reg0.clk"], + ["d_reg__U18$reg0.in","d_reg__U17$reg0.out"], + ["self.clk","d_reg__U18$reg0.clk"], + ["self.op_hcompute_denoised_1_stencil_read.3","d_reg__U18$reg0.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_denoised_1_stencil_read.2"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_denoised_1_stencil_read.4"], @@ -10391,7 +9994,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U79":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U48":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10400,7 +10003,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U78":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U47":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10409,7 +10012,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U77":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U46":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10418,7 +10021,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U76":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U45":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10427,7 +10030,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U81":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U50":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10436,7 +10039,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U80":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U49":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10445,7 +10048,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U70":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U39":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10454,7 +10057,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U69":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10463,7 +10066,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U68":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U37":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10472,7 +10075,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U67":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10481,7 +10084,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U72":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U41":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10490,7 +10093,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U71":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10499,7 +10102,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U88":{ + "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U57":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10508,7 +10111,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_pt__U87":{ + "op_hcompute_demosaicked_1_stencil_exe_start_pt__U56":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10517,7 +10120,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U86":{ + "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U55":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10526,7 +10129,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_pt__U85":{ + "op_hcompute_demosaicked_1_stencil_read_start_pt__U54":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10535,7 +10138,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U90":{ + "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U59":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -10544,7 +10147,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_pt__U89":{ + "op_hcompute_demosaicked_1_stencil_write_start_pt__U58":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10553,7 +10156,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U93":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U62":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10562,7 +10165,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U92":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U61":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10571,7 +10174,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U94":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U63":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10580,7 +10183,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U58":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U27":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10589,7 +10192,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U57":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10598,7 +10201,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U59":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U28":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10607,7 +10210,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U54":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U23":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10616,7 +10219,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U53":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U22":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10625,7 +10228,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U55":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U24":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10634,7 +10237,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U62":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U31":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10643,7 +10246,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U61":{ + "op_hcompute_hw_output_stencil_read_start_pt__U30":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10652,7 +10255,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U63":{ + "op_hcompute_hw_output_stencil_write_start_pt__U32":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10672,14 +10275,6 @@ ["op_hcompute_r_r_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_r_r_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10687,8 +10282,8 @@ }, "ub_r_r_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[7],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[8],"read_data_stride":[1,0,8],"write_data_starting_addr":[8],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[28],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[33],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_r_r_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -10697,8 +10292,8 @@ }, "ub_r_r_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[32,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[469],"cycle_stride":[8,130],"dimensionality":2,"extent":[8,29],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[462],"cycle_stride":[2,130],"dimensionality":2,"extent":[29,29],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[608],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[7,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,3]},"sram2tb_1":{"cycle_starting_addr":[604],"cycle_stride":[8,65,130],"dimensionality":3,"extent":[8,2,28],"read_data_starting_addr":[0],"read_data_stride":[1,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,12]},"tb2out_1":{"cycle_starting_addr":[610],"cycle_stride":[1,2,65,130],"dimensionality":4,"extent":[2,28,2,28],"read_data_starting_addr":[1],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ diff --git a/aha_garnet_design_new/cascade/cascade.json b/aha_garnet_design_new/cascade/cascade.json index 1f46dd28e..1016dc452 100644 --- a/aha_garnet_design_new/cascade/cascade.json +++ b/aha_garnet_design_new/cascade/cascade.json @@ -12,7 +12,7 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U24":{ + "_U22":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -48,48 +48,48 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U22" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U20" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U20"} + "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U21" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U19" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U23" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U21" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U18" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U16" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U16"} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U17" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U15" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U19" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U17" } }, "connections":[ - ["self.clk","_U24.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U24.in"], + ["self.clk","_U22.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U22.in"], ["self.clk","conv1_stencil.clk"], ["op_hcompute_conv1_stencil_1.conv1_stencil_op_hcompute_conv1_stencil_1_write","conv1_stencil.op_hcompute_conv1_stencil_1_write"], ["op_hcompute_conv2_stencil_1.conv1_stencil_op_hcompute_conv2_stencil_1_read","conv1_stencil.op_hcompute_conv2_stencil_1_read"], @@ -161,9 +161,10 @@ ["op_hcompute_conv2_stencil_1_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2":{ "genref":"mantle.reg", @@ -190,15 +191,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "ub_conv1_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[192],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[255],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[192],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[255],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_conv1_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -206,25 +202,24 @@ } }, "connections":[ - ["ub_conv1_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], + ["self.clk","d_reg__U1.clk"], + ["self.op_hcompute_conv1_stencil_1_write.0","d_reg__U1.in"], + ["d_reg__U2.in","d_reg__U1.out"], + ["self.op_hcompute_conv2_stencil_1_read.0","d_reg__U1.out"], ["self.clk","d_reg__U2.clk"], - ["self.op_hcompute_conv1_stencil_1_write.0","d_reg__U2.in"], - ["d_reg__U3.in","d_reg__U2.out"], - ["self.op_hcompute_conv2_stencil_1_read.0","d_reg__U2.out"], + ["self.op_hcompute_conv2_stencil_1_read.7","d_reg__U2.out"], ["self.clk","d_reg__U3.clk"], - ["self.op_hcompute_conv2_stencil_1_read.7","d_reg__U3.out"], + ["ub_conv1_stencil_BANK_0.data_out_0","d_reg__U3.in"], + ["d_reg__U4.in","d_reg__U3.out"], + ["self.op_hcompute_conv2_stencil_1_read.5","d_reg__U3.out"], ["self.clk","d_reg__U4.clk"], - ["ub_conv1_stencil_BANK_0.data_out_0","d_reg__U4.in"], - ["d_reg__U5.in","d_reg__U4.out"], - ["self.op_hcompute_conv2_stencil_1_read.5","d_reg__U4.out"], + ["self.op_hcompute_conv2_stencil_1_read.4","d_reg__U4.out"], ["self.clk","d_reg__U5.clk"], - ["self.op_hcompute_conv2_stencil_1_read.4","d_reg__U5.out"], + ["ub_conv1_stencil_BANK_0.data_out_1","d_reg__U5.in"], + ["d_reg__U6.in","d_reg__U5.out"], + ["self.op_hcompute_conv2_stencil_1_read.2","d_reg__U5.out"], ["self.clk","d_reg__U6.clk"], - ["ub_conv1_stencil_BANK_0.data_out_1","d_reg__U6.in"], - ["d_reg__U7.in","d_reg__U6.out"], - ["self.op_hcompute_conv2_stencil_1_read.2","d_reg__U6.out"], - ["self.clk","d_reg__U7.clk"], - ["self.op_hcompute_conv2_stencil_1_read.1","d_reg__U7.out"], + ["self.op_hcompute_conv2_stencil_1_read.1","d_reg__U6.out"], ["ub_conv1_stencil_BANK_0.clk","self.clk"], ["self.op_hcompute_conv2_stencil_1_read.8","self.op_hcompute_conv1_stencil_1_write.0"], ["ub_conv1_stencil_BANK_0.data_in_0","self.op_hcompute_conv1_stencil_1_write.0"], @@ -694,10 +689,6 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "d_reg__U10":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -718,20 +709,20 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U14":{ + "d_reg__U8":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U15":{ + "d_reg__U9":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -739,25 +730,24 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U9.out"], ["self.clk","d_reg__U10.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U10.in"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U10.in"], ["d_reg__U11.in","d_reg__U10.out"], - ["self.op_hcompute_conv1_stencil_1_read.5","d_reg__U10.out"], + ["self.op_hcompute_conv1_stencil_1_read.4","d_reg__U10.out"], ["self.clk","d_reg__U11.clk"], - ["self.op_hcompute_conv1_stencil_1_read.2","d_reg__U11.out"], + ["self.op_hcompute_conv1_stencil_1_read.1","d_reg__U11.out"], ["self.clk","d_reg__U12.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U12.in"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U12.in"], ["d_reg__U13.in","d_reg__U12.out"], - ["self.op_hcompute_conv1_stencil_1_read.4","d_reg__U12.out"], + ["self.op_hcompute_conv1_stencil_1_read.3","d_reg__U12.out"], ["self.clk","d_reg__U13.clk"], - ["self.op_hcompute_conv1_stencil_1_read.1","d_reg__U13.out"], - ["self.clk","d_reg__U14.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U14.in"], - ["d_reg__U15.in","d_reg__U14.out"], - ["self.op_hcompute_conv1_stencil_1_read.3","d_reg__U14.out"], - ["self.clk","d_reg__U15.clk"], - ["self.op_hcompute_conv1_stencil_1_read.0","d_reg__U15.out"], + ["self.op_hcompute_conv1_stencil_1_read.0","d_reg__U13.out"], + ["self.clk","d_reg__U8.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U8.in"], + ["d_reg__U9.in","d_reg__U8.out"], + ["self.op_hcompute_conv1_stencil_1_read.5","d_reg__U8.out"], + ["self.clk","d_reg__U9.clk"], + ["self.op_hcompute_conv1_stencil_1_read.2","d_reg__U9.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_conv1_stencil_1_read.6"], ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","self.op_hcompute_conv1_stencil_1_read.7"], @@ -768,7 +758,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U22":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U20":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -777,7 +767,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U21":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U19":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -786,7 +776,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U23":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U21":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -795,7 +785,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U18":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U16":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -804,7 +794,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U17":{ + "op_hcompute_hw_output_stencil_read_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -813,7 +803,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U19":{ + "op_hcompute_hw_output_stencil_write_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/cascade/cascade_garnet.json b/aha_garnet_design_new/cascade/cascade_garnet.json index 279409688..8049e5b7e 100644 --- a/aha_garnet_design_new/cascade/cascade_garnet.json +++ b/aha_garnet_design_new/cascade/cascade_garnet.json @@ -153,9 +153,10 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "conv1_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "conv1_stencil$d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "conv1_stencil$d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -182,11 +183,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "conv1_stencil$d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "conv1_stencil$ub_conv1_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -194,12 +190,8 @@ }, "conv1_stencil$ub_conv1_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[192],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[255],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[192],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[255],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$d_reg__U10$reg0":{ "genref":"coreir.reg", @@ -221,12 +213,12 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U14$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U8$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U15$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U9$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -238,7 +230,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -468,40 +460,40 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_1_290_291$binop.data.out","conv1_stencil$d_reg__U2$reg0.in"], - ["conv1_stencil$d_reg__U3$reg0.in","conv1_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_10_341_347$binop.data.in.0","conv1_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_conv2_stencil_1$inner_compute$add_conv1_stencil_8_348_349$binop.data.in.0","conv1_stencil$d_reg__U3$reg0.out"], - ["conv1_stencil$ub_conv1_stencil_BANK_0_garnet.data_out_0","conv1_stencil$d_reg__U4$reg0.in"], - ["conv1_stencil$d_reg__U5$reg0.in","conv1_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_6_344_345$binop.data.in.0","conv1_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_5_341_343$binop.data.in.0","conv1_stencil$d_reg__U5$reg0.out"], - ["conv1_stencil$ub_conv1_stencil_BANK_0_garnet.data_out_1","conv1_stencil$d_reg__U6$reg0.in"], - ["conv1_stencil$d_reg__U7$reg0.in","conv1_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_3_341_342$binop.data.in.0","conv1_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_conv2_stencil_1$inner_compute$add_conv1_stencil_2_355_356$binop.data.in.0","conv1_stencil$d_reg__U7$reg0.out"], + ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_1_290_291$binop.data.out","conv1_stencil$d_reg__U1$reg0.in"], + ["conv1_stencil$d_reg__U2$reg0.in","conv1_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_10_341_347$binop.data.in.0","conv1_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_conv2_stencil_1$inner_compute$add_conv1_stencil_8_348_349$binop.data.in.0","conv1_stencil$d_reg__U2$reg0.out"], + ["conv1_stencil$ub_conv1_stencil_BANK_0_garnet.data_out_0","conv1_stencil$d_reg__U3$reg0.in"], + ["conv1_stencil$d_reg__U4$reg0.in","conv1_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_6_344_345$binop.data.in.0","conv1_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_5_341_343$binop.data.in.0","conv1_stencil$d_reg__U4$reg0.out"], + ["conv1_stencil$ub_conv1_stencil_BANK_0_garnet.data_out_1","conv1_stencil$d_reg__U5$reg0.in"], + ["conv1_stencil$d_reg__U6$reg0.in","conv1_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_3_341_342$binop.data.in.0","conv1_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_conv2_stencil_1$inner_compute$add_conv1_stencil_2_355_356$binop.data.in.0","conv1_stencil$d_reg__U6$reg0.out"], ["conv1_stencil$ub_conv1_stencil_BANK_0_garnet.clk_en","conv1_stencil$ub_conv1_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_1_290_291$binop.data.out","conv1_stencil$ub_conv1_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_conv2_stencil_1$inner_compute$mul_conv1_stencil_7_341_346$binop.data.in.0","conv1_stencil$ub_conv1_stencil_BANK_0_garnet.data_out_0"], ["op_hcompute_conv2_stencil_1$inner_compute$add_conv1_stencil_4_352_353$binop.data.in.0","conv1_stencil$ub_conv1_stencil_BANK_0_garnet.data_out_1"], ["io1in_reset.out","conv1_stencil$ub_conv1_stencil_BANK_0_garnet.flush"], - ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U10$reg0.in"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U10$reg0.in"], ["hw_input_global_wrapper_stencil$d_reg__U11$reg0.in","hw_input_global_wrapper_stencil$d_reg__U10$reg0.out"], - ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_6_276_281$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U10$reg0.out"], - ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_3_287_288$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U11$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U12$reg0.in"], + ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_5_279_280$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U10$reg0.out"], + ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_2_276_277$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U11$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U12$reg0.in"], ["hw_input_global_wrapper_stencil$d_reg__U13$reg0.in","hw_input_global_wrapper_stencil$d_reg__U12$reg0.out"], - ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_5_279_280$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U12$reg0.out"], - ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_2_276_277$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U13$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U14$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U15$reg0.in","hw_input_global_wrapper_stencil$d_reg__U14$reg0.out"], - ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_4_276_278$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U14$reg0.out"], - ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_1_290_291$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U15$reg0.out"], + ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_4_276_278$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U12$reg0.out"], + ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_1_290_291$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U13$reg0.out"], + ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U8$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U9$reg0.in","hw_input_global_wrapper_stencil$d_reg__U8$reg0.out"], + ["op_hcompute_conv1_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_6_276_281$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U8$reg0.out"], + ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_3_287_288$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U9$reg0.out"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_conv1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_7_283_284$binop.data.in.0","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0"], @@ -578,9 +570,10 @@ ["op_hcompute_conv2_stencil_1_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -607,11 +600,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "ub_conv1_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -619,29 +607,29 @@ }, "ub_conv1_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[192],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[255],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[192],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[255],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U1$reg0.clk"], + ["self.op_hcompute_conv1_stencil_1_write.0","d_reg__U1$reg0.in"], + ["d_reg__U2$reg0.in","d_reg__U1$reg0.out"], + ["self.op_hcompute_conv2_stencil_1_read.0","d_reg__U1$reg0.out"], ["self.clk","d_reg__U2$reg0.clk"], - ["self.op_hcompute_conv1_stencil_1_write.0","d_reg__U2$reg0.in"], - ["d_reg__U3$reg0.in","d_reg__U2$reg0.out"], - ["self.op_hcompute_conv2_stencil_1_read.0","d_reg__U2$reg0.out"], + ["self.op_hcompute_conv2_stencil_1_read.7","d_reg__U2$reg0.out"], ["self.clk","d_reg__U3$reg0.clk"], - ["self.op_hcompute_conv2_stencil_1_read.7","d_reg__U3$reg0.out"], + ["ub_conv1_stencil_BANK_0_garnet.data_out_0","d_reg__U3$reg0.in"], + ["d_reg__U4$reg0.in","d_reg__U3$reg0.out"], + ["self.op_hcompute_conv2_stencil_1_read.5","d_reg__U3$reg0.out"], ["self.clk","d_reg__U4$reg0.clk"], - ["ub_conv1_stencil_BANK_0_garnet.data_out_0","d_reg__U4$reg0.in"], - ["d_reg__U5$reg0.in","d_reg__U4$reg0.out"], - ["self.op_hcompute_conv2_stencil_1_read.5","d_reg__U4$reg0.out"], + ["self.op_hcompute_conv2_stencil_1_read.4","d_reg__U4$reg0.out"], ["self.clk","d_reg__U5$reg0.clk"], - ["self.op_hcompute_conv2_stencil_1_read.4","d_reg__U5$reg0.out"], + ["ub_conv1_stencil_BANK_0_garnet.data_out_1","d_reg__U5$reg0.in"], + ["d_reg__U6$reg0.in","d_reg__U5$reg0.out"], + ["self.op_hcompute_conv2_stencil_1_read.2","d_reg__U5$reg0.out"], ["self.clk","d_reg__U6$reg0.clk"], - ["ub_conv1_stencil_BANK_0_garnet.data_out_1","d_reg__U6$reg0.in"], - ["d_reg__U7$reg0.in","d_reg__U6$reg0.out"], - ["self.op_hcompute_conv2_stencil_1_read.2","d_reg__U6$reg0.out"], - ["self.clk","d_reg__U7$reg0.clk"], - ["self.op_hcompute_conv2_stencil_1_read.1","d_reg__U7$reg0.out"], + ["self.op_hcompute_conv2_stencil_1_read.1","d_reg__U6$reg0.out"], ["ub_conv1_stencil_BANK_0_garnet.clk","self.clk"], ["self.op_hcompute_conv2_stencil_1_read.8","self.op_hcompute_conv1_stencil_1_write.0"], ["ub_conv1_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_conv1_stencil_1_write.0"], @@ -687,26 +675,26 @@ ["conv1_stencil_clkwrk_dsa0_op_hcompute_conv1_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U27":{ + "PE_init_U25":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U25":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U26":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U25.out","PE_init_U27.data.in.0"], - ["_U26.out","PE_init_U27.data.in.1"], - ["self.conv1_stencil_clkwrk_dsa0_op_hcompute_conv1_stencil_write.0","PE_init_U27.data.out"], + ["_U23.out","PE_init_U25.data.in.0"], + ["_U24.out","PE_init_U25.data.in.1"], + ["self.conv1_stencil_clkwrk_dsa0_op_hcompute_conv1_stencil_write.0","PE_init_U25.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -857,26 +845,26 @@ ["conv2_stencil_clkwrk_dsa1_op_hcompute_conv2_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U30":{ + "PE_init_U28":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U28":{ + "_U26":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U29":{ + "_U27":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U28.out","PE_init_U30.data.in.0"], - ["_U29.out","PE_init_U30.data.in.1"], - ["self.conv2_stencil_clkwrk_dsa1_op_hcompute_conv2_stencil_write.0","PE_init_U30.data.out"], + ["_U26.out","PE_init_U28.data.in.0"], + ["_U27.out","PE_init_U28.data.in.1"], + ["self.conv2_stencil_clkwrk_dsa1_op_hcompute_conv2_stencil_write.0","PE_init_U28.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1050,26 +1038,26 @@ ["out_conv1_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U33":{ + "PE_init_U31":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U31":{ + "_U29":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U32":{ + "_U30":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U31.out","PE_init_U33.data.in.0"], - ["_U32.out","PE_init_U33.data.in.1"], - ["self.out_conv1_stencil","PE_init_U33.data.out"] + ["_U29.out","PE_init_U31.data.in.0"], + ["_U30.out","PE_init_U31.data.in.1"], + ["self.out_conv1_stencil","PE_init_U31.data.out"] ] }, "hcompute_conv1_stencil_1":{ @@ -1212,26 +1200,26 @@ ["out_conv2_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U36":{ + "PE_init_U34":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U34":{ + "_U32":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U35":{ + "_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U34.out","PE_init_U36.data.in.0"], - ["_U35.out","PE_init_U36.data.in.1"], - ["self.out_conv2_stencil","PE_init_U36.data.out"] + ["_U32.out","PE_init_U34.data.in.0"], + ["_U33.out","PE_init_U34.data.in.1"], + ["self.out_conv2_stencil","PE_init_U34.data.out"] ] }, "hcompute_conv2_stencil_1":{ @@ -1398,10 +1386,6 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "d_reg__U10$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, @@ -1422,12 +1406,12 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U14$reg0":{ + "d_reg__U8$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U15$reg0":{ + "d_reg__U9$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -1439,29 +1423,29 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ ["self.clk","d_reg__U10$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U10$reg0.in"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U10$reg0.in"], ["d_reg__U11$reg0.in","d_reg__U10$reg0.out"], - ["self.op_hcompute_conv1_stencil_1_read.5","d_reg__U10$reg0.out"], + ["self.op_hcompute_conv1_stencil_1_read.4","d_reg__U10$reg0.out"], ["self.clk","d_reg__U11$reg0.clk"], - ["self.op_hcompute_conv1_stencil_1_read.2","d_reg__U11$reg0.out"], + ["self.op_hcompute_conv1_stencil_1_read.1","d_reg__U11$reg0.out"], ["self.clk","d_reg__U12$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U12$reg0.in"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U12$reg0.in"], ["d_reg__U13$reg0.in","d_reg__U12$reg0.out"], - ["self.op_hcompute_conv1_stencil_1_read.4","d_reg__U12$reg0.out"], + ["self.op_hcompute_conv1_stencil_1_read.3","d_reg__U12$reg0.out"], ["self.clk","d_reg__U13$reg0.clk"], - ["self.op_hcompute_conv1_stencil_1_read.1","d_reg__U13$reg0.out"], - ["self.clk","d_reg__U14$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U14$reg0.in"], - ["d_reg__U15$reg0.in","d_reg__U14$reg0.out"], - ["self.op_hcompute_conv1_stencil_1_read.3","d_reg__U14$reg0.out"], - ["self.clk","d_reg__U15$reg0.clk"], - ["self.op_hcompute_conv1_stencil_1_read.0","d_reg__U15$reg0.out"], + ["self.op_hcompute_conv1_stencil_1_read.0","d_reg__U13$reg0.out"], + ["self.clk","d_reg__U8$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U8$reg0.in"], + ["d_reg__U9$reg0.in","d_reg__U8$reg0.out"], + ["self.op_hcompute_conv1_stencil_1_read.5","d_reg__U8$reg0.out"], + ["self.clk","d_reg__U9$reg0.clk"], + ["self.op_hcompute_conv1_stencil_1_read.2","d_reg__U9$reg0.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_conv1_stencil_1_read.6"], ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","self.op_hcompute_conv1_stencil_1_read.7"], @@ -1471,7 +1455,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U22":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U20":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1480,7 +1464,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U21":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U19":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1489,7 +1473,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U23":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U21":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1498,7 +1482,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U18":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U16":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1507,7 +1491,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U17":{ + "op_hcompute_hw_output_stencil_read_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1516,7 +1500,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U19":{ + "op_hcompute_hw_output_stencil_write_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/conv_1_2/conv_1_2.json b/aha_garnet_design_new/conv_1_2/conv_1_2.json index 78ac435cb..b774444c0 100644 --- a/aha_garnet_design_new/conv_1_2/conv_1_2.json +++ b/aha_garnet_design_new/conv_1_2/conv_1_2.json @@ -40,8 +40,8 @@ }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U5"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -61,8 +61,8 @@ }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1],"cycle_stride":[1,64],"dimensionality":2,"extent":[63,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U1"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1],"cycle_stride":[1,64],"dimensionality":2,"extent":[63,64]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", diff --git a/aha_garnet_design_new/conv_1_2/conv_1_2_garnet.json b/aha_garnet_design_new/conv_1_2/conv_1_2_garnet.json index f83b94480..f13ffe05f 100644 --- a/aha_garnet_design_new/conv_1_2/conv_1_2_garnet.json +++ b/aha_garnet_design_new/conv_1_2/conv_1_2_garnet.json @@ -210,7 +210,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1],"cycle_stride":[1,64],"dimensionality":2,"extent":[63,64]}}], "init":["Json",null], "mode":["String","lake"]} } }, diff --git a/aha_garnet_design_new/conv_3_3/conv_3_3.json b/aha_garnet_design_new/conv_3_3/conv_3_3.json index 59bae0d96..c69daa84c 100644 --- a/aha_garnet_design_new/conv_3_3/conv_3_3.json +++ b/aha_garnet_design_new/conv_3_3/conv_3_3.json @@ -12,7 +12,7 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U16":{ + "_U15":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -36,48 +36,48 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U13" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U12"} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U12" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U14" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U10" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U9" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U8"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U9" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U8" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U11" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U10" } }, "connections":[ - ["self.clk","_U16.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U16.in"], + ["self.clk","_U15.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U15.in"], ["self.clk","conv_stencil.clk"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], ["op_hcompute_hw_output_stencil.conv_stencil_op_hcompute_hw_output_stencil_read","conv_stencil.op_hcompute_hw_output_stencil_read"], @@ -435,9 +435,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2":{ "genref":"mantle.reg", @@ -464,15 +465,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -480,25 +476,24 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], + ["self.clk","d_reg__U1.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U1.in"], + ["d_reg__U2.in","d_reg__U1.out"], + ["self.op_hcompute_conv_stencil_1_read.8","d_reg__U1.out"], ["self.clk","d_reg__U2.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U2.in"], - ["d_reg__U3.in","d_reg__U2.out"], - ["self.op_hcompute_conv_stencil_1_read.8","d_reg__U2.out"], + ["self.op_hcompute_conv_stencil_1_read.6","d_reg__U2.out"], ["self.clk","d_reg__U3.clk"], - ["self.op_hcompute_conv_stencil_1_read.6","d_reg__U3.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U3.in"], + ["d_reg__U4.in","d_reg__U3.out"], + ["self.op_hcompute_conv_stencil_1_read.4","d_reg__U3.out"], ["self.clk","d_reg__U4.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U4.in"], - ["d_reg__U5.in","d_reg__U4.out"], - ["self.op_hcompute_conv_stencil_1_read.4","d_reg__U4.out"], + ["self.op_hcompute_conv_stencil_1_read.3","d_reg__U4.out"], ["self.clk","d_reg__U5.clk"], - ["self.op_hcompute_conv_stencil_1_read.3","d_reg__U5.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U5.in"], + ["d_reg__U6.in","d_reg__U5.out"], + ["self.op_hcompute_conv_stencil_1_read.1","d_reg__U5.out"], ["self.clk","d_reg__U6.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U6.in"], - ["d_reg__U7.in","d_reg__U6.out"], - ["self.op_hcompute_conv_stencil_1_read.1","d_reg__U6.out"], - ["self.clk","d_reg__U7.clk"], - ["self.op_hcompute_conv_stencil_1_read.0","d_reg__U7.out"], + ["self.op_hcompute_conv_stencil_1_read.0","d_reg__U6.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","self.op_hcompute_conv_stencil_1_read.2"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.5"], @@ -509,7 +504,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -518,7 +513,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -527,7 +522,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -536,7 +531,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -545,7 +540,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U9":{ + "op_hcompute_hw_output_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -554,7 +549,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U11":{ + "op_hcompute_hw_output_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/conv_3_3/conv_3_3_garnet.json b/aha_garnet_design_new/conv_3_3/conv_3_3_garnet.json index 96da99b6a..af51e9ea6 100644 --- a/aha_garnet_design_new/conv_3_3/conv_3_3_garnet.json +++ b/aha_garnet_design_new/conv_3_3/conv_3_3_garnet.json @@ -153,9 +153,10 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "hw_input_global_wrapper_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "hw_input_global_wrapper_stencil$d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "hw_input_global_wrapper_stencil$d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -182,11 +183,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -194,7 +190,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -364,23 +360,23 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U2$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U3$reg0.in","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_9_303_304$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_7_299_300$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U5$reg0.in","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_5_295_296$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_4_293_294$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U7$reg0.in","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_2_289_290$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_1_287_288$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U7$reg0.out"], + ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U1$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U2$reg0.in","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_9_303_304$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_7_299_300$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U4$reg0.in","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_5_295_296$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_4_293_294$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U6$reg0.in","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_2_289_290$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_1_287_288$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_conv_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_6_297_298$binop.data.in.0","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0"], @@ -456,26 +452,26 @@ ["conv_stencil_clkwrk_dsa0_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U19":{ + "PE_init_U18":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U17":{ + "_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U18":{ + "_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U17.out","PE_init_U19.data.in.0"], - ["_U18.out","PE_init_U19.data.in.1"], - ["self.conv_stencil_clkwrk_dsa0_op_hcompute_conv_stencil_write.0","PE_init_U19.data.out"], + ["_U16.out","PE_init_U18.data.in.0"], + ["_U17.out","PE_init_U18.data.in.1"], + ["self.conv_stencil_clkwrk_dsa0_op_hcompute_conv_stencil_write.0","PE_init_U18.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -697,26 +693,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U22":{ + "PE_init_U21":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U20":{ + "_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U21":{ + "_U20":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U20.out","PE_init_U22.data.in.0"], - ["_U21.out","PE_init_U22.data.in.1"], - ["self.out_conv_stencil","PE_init_U22.data.out"] + ["_U19.out","PE_init_U21.data.in.0"], + ["_U20.out","PE_init_U21.data.in.1"], + ["self.out_conv_stencil","PE_init_U21.data.out"] ] }, "hcompute_conv_stencil_1":{ @@ -931,9 +927,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -960,11 +957,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -972,29 +964,29 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U1$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U1$reg0.in"], + ["d_reg__U2$reg0.in","d_reg__U1$reg0.out"], + ["self.op_hcompute_conv_stencil_1_read.8","d_reg__U1$reg0.out"], ["self.clk","d_reg__U2$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U2$reg0.in"], - ["d_reg__U3$reg0.in","d_reg__U2$reg0.out"], - ["self.op_hcompute_conv_stencil_1_read.8","d_reg__U2$reg0.out"], + ["self.op_hcompute_conv_stencil_1_read.6","d_reg__U2$reg0.out"], ["self.clk","d_reg__U3$reg0.clk"], - ["self.op_hcompute_conv_stencil_1_read.6","d_reg__U3$reg0.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U3$reg0.in"], + ["d_reg__U4$reg0.in","d_reg__U3$reg0.out"], + ["self.op_hcompute_conv_stencil_1_read.4","d_reg__U3$reg0.out"], ["self.clk","d_reg__U4$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U4$reg0.in"], - ["d_reg__U5$reg0.in","d_reg__U4$reg0.out"], - ["self.op_hcompute_conv_stencil_1_read.4","d_reg__U4$reg0.out"], + ["self.op_hcompute_conv_stencil_1_read.3","d_reg__U4$reg0.out"], ["self.clk","d_reg__U5$reg0.clk"], - ["self.op_hcompute_conv_stencil_1_read.3","d_reg__U5$reg0.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U5$reg0.in"], + ["d_reg__U6$reg0.in","d_reg__U5$reg0.out"], + ["self.op_hcompute_conv_stencil_1_read.1","d_reg__U5$reg0.out"], ["self.clk","d_reg__U6$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U6$reg0.in"], - ["d_reg__U7$reg0.in","d_reg__U6$reg0.out"], - ["self.op_hcompute_conv_stencil_1_read.1","d_reg__U6$reg0.out"], - ["self.clk","d_reg__U7$reg0.clk"], - ["self.op_hcompute_conv_stencil_1_read.0","d_reg__U7$reg0.out"], + ["self.op_hcompute_conv_stencil_1_read.0","d_reg__U6$reg0.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_conv_stencil_1_read.2"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_conv_stencil_1_read.5"], @@ -1004,7 +996,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1013,7 +1005,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1022,7 +1014,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1031,7 +1023,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1040,7 +1032,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U9":{ + "op_hcompute_hw_output_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1049,7 +1041,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U11":{ + "op_hcompute_hw_output_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/counter/counter.json b/aha_garnet_design_new/counter/counter.json index 5165b5987..4d13a9d63 100644 --- a/aha_garnet_design_new/counter/counter.json +++ b/aha_garnet_design_new/counter/counter.json @@ -17,13 +17,13 @@ }, "op_hcompute_hw_output_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U4"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U5"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -71,8 +71,8 @@ }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U12"} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", diff --git a/aha_garnet_design_new/counter/counter_garnet.json b/aha_garnet_design_new/counter/counter_garnet.json index e6b3134ad..561a53b48 100644 --- a/aha_garnet_design_new/counter/counter_garnet.json +++ b/aha_garnet_design_new/counter/counter_garnet.json @@ -168,12 +168,12 @@ }, "op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -269,12 +269,12 @@ }, "op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[3],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -302,8 +302,8 @@ ["op_hcompute_hw_output_stencil$inner_compute$add_264_263_265$binop.data.in.0","op_hcompute_hw_output_stencil$inner_compute$add_262_263_264$binop.data.out"], ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet.data_out_0","op_hcompute_hw_output_stencil$inner_compute$add_hw_output_s0_x_xi_hw_output_s0_y_yi_262$binop.data.in.0"], ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet.data_out_0","op_hcompute_hw_output_stencil$inner_compute$add_hw_output_s0_x_xi_hw_output_s0_y_yi_262$binop.data.in.1"], - ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet.clk_en"] + ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet.clk_en"] ] }, "cu_op_hcompute_hw_input_global_wrapper_stencil":{ diff --git a/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled.json b/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled.json index 50c214736..d5981a98b 100644 --- a/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled.json +++ b/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "affine_controller__U20":{ + "affine_controller__U19":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17,13 +17,13 @@ }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U21"} + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U22"} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -45,7 +45,7 @@ ["op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const.out","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2.rst_n"] ] }, - "affine_controller__U29":{ + "affine_controller__U28":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -60,13 +60,13 @@ }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U30"} + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U31"} + "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -88,7 +88,7 @@ ["op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const.out","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2.rst_n"] ] }, - "affine_controller__U38":{ + "affine_controller__U37":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -103,13 +103,13 @@ }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U39"} + "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U40"} + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -243,7 +243,7 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["demosaicked_1_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -252,7 +252,7 @@ }, "connections":[ ["self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in0_demosaicked_1_stencil.0"], - ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -262,7 +262,7 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["demosaicked_1_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -271,7 +271,7 @@ }, "connections":[ ["self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute.in0_demosaicked_1_stencil.0"], - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -281,7 +281,7 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["demosaicked_1_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -290,7 +290,7 @@ }, "connections":[ ["self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_2_read.0","inner_compute.in0_demosaicked_1_stencil.0"], - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -300,15 +300,15 @@ ["reset","BitIn"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid","Bit"], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write_valid","Bit"], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write_valid","Bit"], - ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid","Bit"], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid","Bit"], + ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U51":{ + "_U50":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -326,91 +326,91 @@ "modref":"global.cu_op_hcompute_demosaicked_1_stencil_1" }, "op_hcompute_demosaicked_1_stencil_1_exe_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U34" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U33" }, "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U35" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U34" }, "op_hcompute_demosaicked_1_stencil_1_port_controller":{ - "modref":"global.affine_controller__U29" + "modref":"global.affine_controller__U28" }, "op_hcompute_demosaicked_1_stencil_1_read_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_pt__U32" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_pt__U31" }, "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U33" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U32" }, "op_hcompute_demosaicked_1_stencil_1_write_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_pt__U36" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_pt__U35" }, "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U37" + "modref":"global.op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U36" }, "op_hcompute_demosaicked_1_stencil_2":{ "modref":"global.cu_op_hcompute_demosaicked_1_stencil_2" }, "op_hcompute_demosaicked_1_stencil_2_exe_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U25" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U24" }, "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U26" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U25" }, "op_hcompute_demosaicked_1_stencil_2_port_controller":{ - "modref":"global.affine_controller__U20" + "modref":"global.affine_controller__U19" }, "op_hcompute_demosaicked_1_stencil_2_read_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_pt__U23" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_pt__U22" }, "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U24" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U23" }, "op_hcompute_demosaicked_1_stencil_2_write_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_pt__U27" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_pt__U26" }, "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U28" + "modref":"global.op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U27" }, "op_hcompute_demosaicked_1_stencil_exe_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_pt__U43" + "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_pt__U42" }, "op_hcompute_demosaicked_1_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U44" + "modref":"global.op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U43" }, "op_hcompute_demosaicked_1_stencil_port_controller":{ - "modref":"global.affine_controller__U38" + "modref":"global.affine_controller__U37" }, "op_hcompute_demosaicked_1_stencil_read_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_pt__U41" + "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_pt__U40" }, "op_hcompute_demosaicked_1_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U42" + "modref":"global.op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U41" }, "op_hcompute_demosaicked_1_stencil_write_start":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_pt__U45" + "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_pt__U44" }, "op_hcompute_demosaicked_1_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U46" + "modref":"global.op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U45" }, "op_hcompute_hw_input_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U49" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U48" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U47"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U47"} + "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U48" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U47" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U50" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U49" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" @@ -419,66 +419,66 @@ "modref":"global.cu_op_hcompute_hw_output_stencil_1" }, "op_hcompute_hw_output_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U14" + "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U13" }, "op_hcompute_hw_output_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U12"} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U13" + "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U12" }, "op_hcompute_hw_output_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U15" + "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U14" }, "op_hcompute_hw_output_stencil_2":{ "modref":"global.cu_op_hcompute_hw_output_stencil_2" }, "op_hcompute_hw_output_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U10" + "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U9" }, "op_hcompute_hw_output_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U8"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U9" + "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U8" }, "op_hcompute_hw_output_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U11" + "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U10" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U18" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U17" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U16"} + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U17" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U16" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U19" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U18" } }, "connections":[ - ["self.clk","_U51.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U51.in"], + ["self.clk","_U50.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U50.in"], ["self.clk","demosaicked_1_stencil.clk"], ["op_hcompute_demosaicked_1_stencil_1.demosaicked_1_stencil_op_hcompute_demosaicked_1_stencil_1_write","demosaicked_1_stencil.op_hcompute_demosaicked_1_stencil_1_write"], ["op_hcompute_demosaicked_1_stencil_2.demosaicked_1_stencil_op_hcompute_demosaicked_1_stencil_2_write","demosaicked_1_stencil.op_hcompute_demosaicked_1_stencil_2_write"], @@ -537,9 +537,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], ["self.clk","op_hcompute_hw_output_stencil.clk"], - ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write"], + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write"], ["self.clk","op_hcompute_hw_output_stencil_1.clk"], - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write","op_hcompute_hw_output_stencil_1.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write","op_hcompute_hw_output_stencil_1.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write"], ["op_hcompute_hw_output_stencil_1_port_controller.stencil_valid","op_hcompute_hw_output_stencil_1_exe_start.in"], ["self.clk","op_hcompute_hw_output_stencil_1_port_controller.clk"], ["op_hcompute_hw_output_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_1_port_controller.clk_en"], @@ -547,9 +547,9 @@ ["op_hcompute_hw_output_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_1_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_1_read_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_1_write_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid","op_hcompute_hw_output_stencil_1_write_start.out"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid","op_hcompute_hw_output_stencil_1_write_start.out"], ["self.clk","op_hcompute_hw_output_stencil_2.clk"], - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write","op_hcompute_hw_output_stencil_2.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write"], + ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write","op_hcompute_hw_output_stencil_2.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write"], ["op_hcompute_hw_output_stencil_2_port_controller.stencil_valid","op_hcompute_hw_output_stencil_2_exe_start.in"], ["self.clk","op_hcompute_hw_output_stencil_2_port_controller.clk"], ["op_hcompute_hw_output_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_2_port_controller.clk_en"], @@ -557,7 +557,7 @@ ["op_hcompute_hw_output_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_2_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_2_read_start.in","op_hcompute_hw_output_stencil_2_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_2_write_start.in","op_hcompute_hw_output_stencil_2_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write_valid","op_hcompute_hw_output_stencil_2_write_start.out"], + ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid","op_hcompute_hw_output_stencil_2_write_start.out"], ["op_hcompute_hw_output_stencil_port_controller.stencil_valid","op_hcompute_hw_output_stencil_exe_start.in"], ["self.clk","op_hcompute_hw_output_stencil_port_controller.clk"], ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.clk_en"], @@ -565,7 +565,7 @@ ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_read_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_write_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"] + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"] ] }, "demosaicked_1_stencil_ub":{ @@ -2219,9 +2219,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2":{ "genref":"mantle.reg", @@ -2248,15 +2249,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -2264,34 +2260,33 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], + ["self.clk","d_reg__U1.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U1.in"], + ["d_reg__U2.in","d_reg__U1.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.1","d_reg__U1.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.1","d_reg__U1.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.4","d_reg__U1.out"], ["self.clk","d_reg__U2.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U2.in"], - ["d_reg__U3.in","d_reg__U2.out"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.1","d_reg__U2.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.1","d_reg__U2.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.4","d_reg__U2.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.5","d_reg__U2.out"], ["self.clk","d_reg__U3.clk"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.5","d_reg__U3.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U3.in"], + ["d_reg__U4.in","d_reg__U3.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.4","d_reg__U3.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.0","d_reg__U3.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.0","d_reg__U3.out"], ["self.clk","d_reg__U4.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U4.in"], - ["d_reg__U5.in","d_reg__U4.out"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.4","d_reg__U4.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.0","d_reg__U4.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.0","d_reg__U4.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.0","d_reg__U4.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.6","d_reg__U4.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.3","d_reg__U4.out"], ["self.clk","d_reg__U5.clk"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.0","d_reg__U5.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.6","d_reg__U5.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.3","d_reg__U5.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U5.in"], + ["d_reg__U6.in","d_reg__U5.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.3","d_reg__U5.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.4","d_reg__U5.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.6","d_reg__U5.out"], ["self.clk","d_reg__U6.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U6.in"], - ["d_reg__U7.in","d_reg__U6.out"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.3","d_reg__U6.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.4","d_reg__U6.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.6","d_reg__U6.out"], - ["self.clk","d_reg__U7.clk"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.7","d_reg__U7.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.7","d_reg__U7.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.7","d_reg__U6.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.7","d_reg__U6.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.2"], ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","self.op_hcompute_demosaicked_1_stencil_2_read.2"], @@ -2305,7 +2300,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U35":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U34":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2314,7 +2309,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U34":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U33":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2323,7 +2318,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U33":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U32":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2332,7 +2327,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U32":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U31":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2341,7 +2336,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U37":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U36":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2350,7 +2345,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U36":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U35":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2359,7 +2354,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U26":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U25":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2368,7 +2363,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U25":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U24":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2377,7 +2372,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U24":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U23":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2386,7 +2381,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U23":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U22":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2395,7 +2390,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U28":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U27":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2404,7 +2399,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U27":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2413,7 +2408,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U44":{ + "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U43":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2422,7 +2417,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_pt__U43":{ + "op_hcompute_demosaicked_1_stencil_exe_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2431,7 +2426,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U42":{ + "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U41":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2440,7 +2435,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_pt__U41":{ + "op_hcompute_demosaicked_1_stencil_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2449,7 +2444,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U46":{ + "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U45":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -2458,7 +2453,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_pt__U45":{ + "op_hcompute_demosaicked_1_stencil_write_start_pt__U44":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2467,7 +2462,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U49":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U48":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2476,7 +2471,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U48":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U47":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2485,7 +2480,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U50":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U49":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2494,7 +2489,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U14":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2503,7 +2498,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U13":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2512,7 +2507,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U15":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2521,7 +2516,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U10":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2530,7 +2525,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U9":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2539,7 +2534,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U11":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2548,7 +2543,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U18":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2557,7 +2552,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U17":{ + "op_hcompute_hw_output_stencil_read_start_pt__U16":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2566,7 +2561,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U19":{ + "op_hcompute_hw_output_stencil_write_start_pt__U18":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled_garnet.json b/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled_garnet.json index df2a5d08e..5b893ea29 100644 --- a/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled_garnet.json +++ b/aha_garnet_design_new/demosaic_unrolled/demosaic_unrolled_garnet.json @@ -189,7 +189,7 @@ }, "global":{ "modules":{ - "affine_controller__U20":{ + "affine_controller__U19":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -197,29 +197,29 @@ ["rst_n","BitIn"] ]], "instances":{ - "PE_init_U54":{ + "PE_init_U53":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U52":{ + "_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U53":{ + "_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst":{ @@ -234,9 +234,9 @@ } }, "connections":[ - ["_U52.out","PE_init_U54.data.in.0"], - ["_U53.out","PE_init_U54.data.in.1"], - ["self.d.0","PE_init_U54.data.out"], + ["_U51.out","PE_init_U53.data.in.0"], + ["_U52.out","PE_init_U53.data.in.1"], + ["self.d.0","PE_init_U53.data.out"], ["self.clk","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk"], ["op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk_en"], ["self.d.1","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.data_out_0"], @@ -248,7 +248,7 @@ ["self.rst_n","op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet.flush"] ] }, - "affine_controller__U29":{ + "affine_controller__U28":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -256,29 +256,29 @@ ["rst_n","BitIn"] ]], "instances":{ - "PE_init_U57":{ + "PE_init_U56":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U55":{ + "_U54":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U56":{ + "_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst":{ @@ -293,9 +293,9 @@ } }, "connections":[ - ["_U55.out","PE_init_U57.data.in.0"], - ["_U56.out","PE_init_U57.data.in.1"], - ["self.d.0","PE_init_U57.data.out"], + ["_U54.out","PE_init_U56.data.in.0"], + ["_U55.out","PE_init_U56.data.in.1"], + ["self.d.0","PE_init_U56.data.out"], ["self.clk","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk"], ["op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk_en"], ["self.d.1","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.data_out_0"], @@ -307,7 +307,7 @@ ["self.rst_n","op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.flush"] ] }, - "affine_controller__U38":{ + "affine_controller__U37":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -315,29 +315,29 @@ ["rst_n","BitIn"] ]], "instances":{ - "PE_init_U60":{ + "PE_init_U59":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U58":{ + "_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U59":{ + "_U58":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -352,9 +352,9 @@ } }, "connections":[ - ["_U58.out","PE_init_U60.data.in.0"], - ["_U59.out","PE_init_U60.data.in.1"], - ["self.d.0","PE_init_U60.data.out"], + ["_U57.out","PE_init_U59.data.in.0"], + ["_U58.out","PE_init_U59.data.in.1"], + ["self.d.0","PE_init_U59.data.out"], ["self.clk","op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.clk"], ["op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.clk_en"], ["self.d.1","op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.data_out_0"], @@ -2330,10 +2330,10 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["demosaicked_1_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write.0","self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_read.0"], + ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write.0","self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_read.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -2343,10 +2343,10 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["demosaicked_1_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write.0","self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_1_read.0"], + ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write.0","self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_1_read.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -2356,10 +2356,10 @@ ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], ["demosaicked_1_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write.0","self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_2_read.0"], + ["self.hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write.0","self.demosaicked_1_stencil_op_hcompute_hw_output_stencil_2_read.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -2369,17 +2369,18 @@ ["reset","BitIn"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid","Bit"], - ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write_valid","Bit"], - ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write_valid","Bit"], - ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid","Bit"], + ["hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid","Bit"], + ["hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "hw_input_global_wrapper_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "hw_input_global_wrapper_stencil$d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "hw_input_global_wrapper_stencil$d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -2406,11 +2407,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2418,22 +2414,22 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_0":{ + "io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, "metadata":{"in2glb_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,62]}} }, - "io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write_0":{ + "io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, "metadata":{"in2glb_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,62]}} }, - "io16_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write_0":{ + "io16_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, @@ -2445,15 +2441,15 @@ "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[4096],"read_data_starting_addr":[0],"read_data_stride":[1]}} }, - "io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid":{ + "io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, - "io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write_valid":{ + "io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, - "io1_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write_valid":{ + "io1_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, @@ -3308,12 +3304,12 @@ }, "op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst":{ @@ -3958,12 +3954,12 @@ }, "op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst":{ @@ -3983,12 +3979,12 @@ }, "op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[256],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63],"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -4008,7 +4004,7 @@ }, "op_hcompute_hw_output_stencil_1_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const_lutcnst":{ @@ -4018,7 +4014,7 @@ }, "op_hcompute_hw_output_stencil_2_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -4028,106 +4024,106 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U2$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U3$reg0.in","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_5_465$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_1_470$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_11_718$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_9_724$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_958$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_14_931$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_16_930$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_952$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_965$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_925$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_979$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_15_933$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_968$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_951$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_965$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_966$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_954$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_968$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_971$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U5$reg0.in","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_485$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_4_464$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_5_465$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_486$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_1_457$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_1_479$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_1_512$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_455_456$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_490_523$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_452$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_6_482$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_488$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_1_467$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_1_470$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$mux_451_477_hw_input_global_wrapper_stencil_1$mux.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_10_717$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_11_718$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_12_729$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_13_730$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_9_720$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_9_724$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_9_732$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_9_735$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_716_738_hw_input_global_wrapper_stencil_9$mux.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_716_hw_input_global_wrapper_stencil_9_727$mux.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_958$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_17_937$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_18_938$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_957$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_14_931$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_951$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_14_983$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_928_929$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_962_996$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_925$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_960$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_17_hw_input_global_wrapper_stencil_14_940$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_18_hw_input_global_wrapper_stencil_14_943$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_954$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_924_hw_input_global_wrapper_stencil_14_1000$mux.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_4_464$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_1_467$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_10_717$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_9_720$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_957$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_952$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_966$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_14_983$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_21_984$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_960$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_979$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_971$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_21_hw_input_global_wrapper_stencil_20_986$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U7$reg0.in","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_486$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_7_493$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_1_512$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_2_480$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_8_511$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_488$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_7_507$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_6_496$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_7_514$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_13_730$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_9_735$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_18_938$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_18_hw_input_global_wrapper_stencil_14_943$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_8_511$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U7$reg0.out"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_7_514$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U7$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_21_984$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U7$reg0.out"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_21_hw_input_global_wrapper_stencil_20_986$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U7$reg0.out"], + ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U1$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U2$reg0.in","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_5_465$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_1_470$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_11_718$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_9_724$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_958$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_14_931$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_16_930$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_952$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_965$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_925$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_979$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_15_933$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_968$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_951$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_965$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_966$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_954$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_15_968$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_971$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U4$reg0.in","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_485$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_4_464$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_5_465$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_486$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_1_457$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_1_479$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_1_512$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_455_456$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_490_523$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_452$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_6_482$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_488$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_1_467$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_1_470$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$mux_451_477_hw_input_global_wrapper_stencil_1$mux.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_10_717$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_11_718$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_12_729$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_13_730$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_9_720$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_9_724$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_9_732$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_9_735$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_716_738_hw_input_global_wrapper_stencil_9$mux.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_716_hw_input_global_wrapper_stencil_9_727$mux.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_958$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_17_937$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_18_938$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_957$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_14_931$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_951$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_14_983$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_928_929$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_962_996$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_925$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_960$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_17_hw_input_global_wrapper_stencil_14_940$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_18_hw_input_global_wrapper_stencil_14_943$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_14_954$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_924_hw_input_global_wrapper_stencil_14_1000$mux.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_4_464$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_1_467$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_10_717$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_9_720$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_957$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_952$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_966$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_14_983$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_21_984$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_20_960$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_20_979$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_20_971$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_21_hw_input_global_wrapper_stencil_20_986$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U6$reg0.in","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_486$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_7_493$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_1_512$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_2_480$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_8_511$sub$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_7_488$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_7_507$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_6_496$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_7_514$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$absd_hw_input_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_13_730$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$add_hw_input_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_9_735$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_18_938$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_18_hw_input_global_wrapper_stencil_14_943$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_8_511$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_7_514$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_21_984$sub$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_21_hw_input_global_wrapper_stencil_20_986$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_485$sub$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0"], @@ -4150,16 +4146,16 @@ ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_2_499$binop.data.in.0","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1"], ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_6_496$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.flush"], - ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_714_728_739$mux.data.out","io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_0.in"], - ["op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_922_995_1001$mux.data.out","io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write_0.in"], - ["op_hcompute_demosaicked_1_stencil$inner_compute$mux_449_478_528$mux.data.out","io16_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write_0.in"], + ["op_hcompute_demosaicked_1_stencil$inner_compute$mux_449_478_528$mux.data.out","io16_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_0.in"], + ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_714_728_739$mux.data.out","io16_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_0.in"], + ["op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_922_995_1001$mux.data.out","io16_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_0.in"], ["op_hcompute_demosaicked_1_stencil$inner_compute$absd_hw_input_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_3_458$sub$binop.data.in.1","io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out"], ["op_hcompute_demosaicked_1_stencil$inner_compute$add_hw_input_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_3_460$binop.data.in.1","io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_16_930$sub$binop.data.in.1","io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$add_hw_input_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_15_933$binop.data.in.0","io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out"], - ["op_hcompute_hw_output_stencil_1_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_1_write_valid.in"], - ["op_hcompute_hw_output_stencil_2_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_2_write_valid.in"], - ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_write_valid.in"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_0_op_hcompute_hw_output_stencil_write_valid.in"], + ["op_hcompute_hw_output_stencil_1_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_1_op_hcompute_hw_output_stencil_1_write_valid.in"], + ["op_hcompute_hw_output_stencil_2_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_2_op_hcompute_hw_output_stencil_2_write_valid.in"], ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.flush","io1in_reset.out"], ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.flush","io1in_reset.out"], ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.flush","io1in_reset.out"], @@ -4350,8 +4346,8 @@ ["op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_719_723_726$mux.data.out","op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_716_hw_input_global_wrapper_stencil_9_727$mux.data.in.1"], ["op_hcompute_demosaicked_1_stencil_1$inner_compute$ult_717_718_719$compop.bit.out","op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_719_723_726$mux.bit.in.0"], ["op_hcompute_demosaicked_1_stencil_1$inner_compute$ult_729_730_731$compop.bit.out","op_hcompute_demosaicked_1_stencil_1$inner_compute$mux_731_734_737$mux.bit.in.0"], - ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_1_port_controller$op_hcompute_demosaicked_1_stencil_1_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_958$sub$binop.data.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_958$abs$abs.data.in.0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_957_958_959$compop.data.in.1","op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_15_958$abs$abs.data.out"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_17_937$sub$binop.data.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$absd_hw_input_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_17_937$abs$abs.data.in.0"], @@ -4488,8 +4484,8 @@ ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_957_958_959$compop.bit.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_959_962_928$mux.bit.in.0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_965_966_967$compop.bit.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_967_970_973$mux.bit.in.0"], ["op_hcompute_demosaicked_1_stencil_2$inner_compute$ult_983_984_985$compop.bit.out","op_hcompute_demosaicked_1_stencil_2$inner_compute$mux_985_962_988$mux.bit.in.0"], - ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_2_port_controller$op_hcompute_demosaicked_1_stencil_2_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_1_garnet.clk_en"], ["op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_demosaicked_1_stencil_port_controller$op_hcompute_demosaicked_1_stencil_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_hw_output_stencil_1_port_controller_garnet.clk_en","op_hcompute_hw_output_stencil_1_port_controller_clk_en_const_lutcnst.bit.out"], @@ -6505,9 +6501,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -6534,11 +6531,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6546,38 +6538,38 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U1$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U1$reg0.in"], + ["d_reg__U2$reg0.in","d_reg__U1$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.1","d_reg__U1$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.1","d_reg__U1$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.4","d_reg__U1$reg0.out"], ["self.clk","d_reg__U2$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U2$reg0.in"], - ["d_reg__U3$reg0.in","d_reg__U2$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.1","d_reg__U2$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.1","d_reg__U2$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.4","d_reg__U2$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.5","d_reg__U2$reg0.out"], ["self.clk","d_reg__U3$reg0.clk"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.5","d_reg__U3$reg0.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U3$reg0.in"], + ["d_reg__U4$reg0.in","d_reg__U3$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.4","d_reg__U3$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.0","d_reg__U3$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.0","d_reg__U3$reg0.out"], ["self.clk","d_reg__U4$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U4$reg0.in"], - ["d_reg__U5$reg0.in","d_reg__U4$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.4","d_reg__U4$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.0","d_reg__U4$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.0","d_reg__U4$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.0","d_reg__U4$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.6","d_reg__U4$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.3","d_reg__U4$reg0.out"], ["self.clk","d_reg__U5$reg0.clk"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.0","d_reg__U5$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.6","d_reg__U5$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.3","d_reg__U5$reg0.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U5$reg0.in"], + ["d_reg__U6$reg0.in","d_reg__U5$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_1_read.3","d_reg__U5$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.4","d_reg__U5$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.6","d_reg__U5$reg0.out"], ["self.clk","d_reg__U6$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U6$reg0.in"], - ["d_reg__U7$reg0.in","d_reg__U6$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_1_read.3","d_reg__U6$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.4","d_reg__U6$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.6","d_reg__U6$reg0.out"], - ["self.clk","d_reg__U7$reg0.clk"], - ["self.op_hcompute_demosaicked_1_stencil_2_read.7","d_reg__U7$reg0.out"], - ["self.op_hcompute_demosaicked_1_stencil_read.7","d_reg__U7$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_2_read.7","d_reg__U6$reg0.out"], + ["self.op_hcompute_demosaicked_1_stencil_read.7","d_reg__U6$reg0.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_demosaicked_1_stencil_1_read.2"], ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","self.op_hcompute_demosaicked_1_stencil_2_read.2"], @@ -6590,7 +6582,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U35":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_control_vars_pt__U34":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6599,7 +6591,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U34":{ + "op_hcompute_demosaicked_1_stencil_1_exe_start_pt__U33":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6608,7 +6600,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U33":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_control_vars_pt__U32":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6617,7 +6609,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U32":{ + "op_hcompute_demosaicked_1_stencil_1_read_start_pt__U31":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6626,7 +6618,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U37":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_control_vars_pt__U36":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6635,7 +6627,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U36":{ + "op_hcompute_demosaicked_1_stencil_1_write_start_pt__U35":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6644,7 +6636,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U26":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_control_vars_pt__U25":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6653,7 +6645,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U25":{ + "op_hcompute_demosaicked_1_stencil_2_exe_start_pt__U24":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6662,7 +6654,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U24":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_control_vars_pt__U23":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6671,7 +6663,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U23":{ + "op_hcompute_demosaicked_1_stencil_2_read_start_pt__U22":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6680,7 +6672,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U28":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_control_vars_pt__U27":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6689,7 +6681,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U27":{ + "op_hcompute_demosaicked_1_stencil_2_write_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6698,7 +6690,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U44":{ + "op_hcompute_demosaicked_1_stencil_exe_start_control_vars_pt__U43":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6707,7 +6699,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_exe_start_pt__U43":{ + "op_hcompute_demosaicked_1_stencil_exe_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6716,7 +6708,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U42":{ + "op_hcompute_demosaicked_1_stencil_read_start_control_vars_pt__U41":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6725,7 +6717,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_read_start_pt__U41":{ + "op_hcompute_demosaicked_1_stencil_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6734,7 +6726,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U46":{ + "op_hcompute_demosaicked_1_stencil_write_start_control_vars_pt__U45":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -6743,7 +6735,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_demosaicked_1_stencil_write_start_pt__U45":{ + "op_hcompute_demosaicked_1_stencil_write_start_pt__U44":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6752,7 +6744,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U49":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U48":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6761,7 +6753,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U48":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U47":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6770,7 +6762,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U50":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U49":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6779,7 +6771,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U14":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6788,7 +6780,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U13":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6797,7 +6789,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U15":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6806,7 +6798,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U10":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6815,7 +6807,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U9":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6824,7 +6816,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U11":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6833,7 +6825,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U18":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6842,7 +6834,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U17":{ + "op_hcompute_hw_output_stencil_read_start_pt__U16":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6851,7 +6843,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U19":{ + "op_hcompute_hw_output_stencil_write_start_pt__U18":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/gaussian/gaussian.json b/aha_garnet_design_new/gaussian/gaussian.json index 226b653bc..c826d5bae 100644 --- a/aha_garnet_design_new/gaussian/gaussian.json +++ b/aha_garnet_design_new/gaussian/gaussian.json @@ -157,7 +157,7 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U16":{ + "_U15":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -187,48 +187,48 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U13" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U12"} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U12" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U14" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U10" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U9" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U8"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U9" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U8" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U11" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U10" } }, "connections":[ - ["self.clk","_U16.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U16.in"], + ["self.clk","_U15.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U15.in"], ["self.clk","blur_stencil.clk"], ["op_hcompute_blur_stencil.blur_stencil_op_hcompute_blur_stencil_write","blur_stencil.op_hcompute_blur_stencil_write"], ["op_hcompute_hw_output_stencil.blur_stencil_op_hcompute_hw_output_stencil_read","blur_stencil.op_hcompute_hw_output_stencil_read"], @@ -501,9 +501,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2":{ "genref":"mantle.reg", @@ -530,15 +531,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -546,25 +542,24 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], + ["self.clk","d_reg__U1.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U1.in"], + ["d_reg__U2.in","d_reg__U1.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U1.out"], ["self.clk","d_reg__U2.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U2.in"], - ["d_reg__U3.in","d_reg__U2.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U2.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.6","d_reg__U2.out"], ["self.clk","d_reg__U3.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.6","d_reg__U3.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U3.in"], + ["d_reg__U4.in","d_reg__U3.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U3.out"], ["self.clk","d_reg__U4.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U4.in"], - ["d_reg__U5.in","d_reg__U4.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U4.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U4.out"], ["self.clk","d_reg__U5.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U5.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U5.in"], + ["d_reg__U6.in","d_reg__U5.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.1","d_reg__U5.out"], ["self.clk","d_reg__U6.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U6.in"], - ["d_reg__U7.in","d_reg__U6.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.1","d_reg__U6.out"], - ["self.clk","d_reg__U7.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U7.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U6.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_1","self.op_hcompute_blur_unnormalized_stencil_1_read.2"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_blur_unnormalized_stencil_1_read.5"], @@ -575,7 +570,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -584,7 +579,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -593,7 +588,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -602,7 +597,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -611,7 +606,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U9":{ + "op_hcompute_hw_output_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -620,7 +615,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U11":{ + "op_hcompute_hw_output_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/gaussian/gaussian_garnet.json b/aha_garnet_design_new/gaussian/gaussian_garnet.json index 1cf81748a..a6dc3b6e6 100644 --- a/aha_garnet_design_new/gaussian/gaussian_garnet.json +++ b/aha_garnet_design_new/gaussian/gaussian_garnet.json @@ -220,26 +220,26 @@ ["blur_unnormalized_stencil_clkwrk_dsa0_op_hcompute_blur_unnormalized_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U19":{ + "PE_init_U18":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U17":{ + "_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U18":{ + "_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U17.out","PE_init_U19.data.in.0"], - ["_U18.out","PE_init_U19.data.in.1"], - ["self.blur_unnormalized_stencil_clkwrk_dsa0_op_hcompute_blur_unnormalized_stencil_write.0","PE_init_U19.data.out"], + ["_U16.out","PE_init_U18.data.in.0"], + ["_U17.out","PE_init_U18.data.in.1"], + ["self.blur_unnormalized_stencil_clkwrk_dsa0_op_hcompute_blur_unnormalized_stencil_write.0","PE_init_U18.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -466,9 +466,10 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "hw_input_global_wrapper_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "hw_input_global_wrapper_stencil$d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "hw_input_global_wrapper_stencil$d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -495,11 +496,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -507,7 +503,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -687,23 +683,23 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U2$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U3$reg0.in","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_9_283_292$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_7_281_290$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U5$reg0.in","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_5_287_288$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_4_283_286$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U6$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U7$reg0.in","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_2_283_284$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_1_281_282$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U7$reg0.out"], + ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U1$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U2$reg0.in","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_9_283_292$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_7_281_290$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U2$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U4$reg0.in","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_5_287_288$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_4_283_286$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U4$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U5$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U6$reg0.in","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_2_283_284$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_1_281_282$binop.data.in.0","hw_input_global_wrapper_stencil$d_reg__U6$reg0.out"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_hw_input_global_wrapper_stencil_6_283_289$binop.data.in.0","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0"], @@ -773,26 +769,26 @@ ["out_blur_unnormalized_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U22":{ + "PE_init_U21":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U20":{ + "_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U21":{ + "_U20":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U20.out","PE_init_U22.data.in.0"], - ["_U21.out","PE_init_U22.data.in.1"], - ["self.out_blur_unnormalized_stencil","PE_init_U22.data.out"] + ["_U19.out","PE_init_U21.data.in.0"], + ["_U20.out","PE_init_U21.data.in.1"], + ["self.out_blur_unnormalized_stencil","PE_init_U21.data.out"] ] }, "hcompute_blur_unnormalized_stencil_1":{ @@ -1007,9 +1003,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -1036,11 +1033,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -1048,29 +1040,29 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[125],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U1$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U1$reg0.in"], + ["d_reg__U2$reg0.in","d_reg__U1$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U1$reg0.out"], ["self.clk","d_reg__U2$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U2$reg0.in"], - ["d_reg__U3$reg0.in","d_reg__U2$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U2$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.6","d_reg__U2$reg0.out"], ["self.clk","d_reg__U3$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.6","d_reg__U3$reg0.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U3$reg0.in"], + ["d_reg__U4$reg0.in","d_reg__U3$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U3$reg0.out"], ["self.clk","d_reg__U4$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U4$reg0.in"], - ["d_reg__U5$reg0.in","d_reg__U4$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U4$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U4$reg0.out"], ["self.clk","d_reg__U5$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U5$reg0.out"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U5$reg0.in"], + ["d_reg__U6$reg0.in","d_reg__U5$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.1","d_reg__U5$reg0.out"], ["self.clk","d_reg__U6$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U6$reg0.in"], - ["d_reg__U7$reg0.in","d_reg__U6$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.1","d_reg__U6$reg0.out"], - ["self.clk","d_reg__U7$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U7$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U6$reg0.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_blur_unnormalized_stencil_1_read.2"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_blur_unnormalized_stencil_1_read.5"], @@ -1080,7 +1072,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1089,7 +1081,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1098,7 +1090,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1107,7 +1099,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1116,7 +1108,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U9":{ + "op_hcompute_hw_output_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1125,7 +1117,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U11":{ + "op_hcompute_hw_output_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction.json b/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction.json index 5367af3bb..1f5e50196 100644 --- a/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction.json +++ b/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction.json @@ -2,490 +2,490 @@ "namespaces":{ "global":{ "modules":{ - "aff__U107":{ + "aff__U100":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U113":{ + "add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U108":{ + "coeff_0_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U110":{ + "coeff_1_U103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U112":{ + "const_term_U105":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U109":{ + "mul_d0__U102":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U111":{ + "mul_d1__U104":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U109.out","add_all__U113.in0"], - ["mul_d1__U111.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U112.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U109.in0","coeff_0_U108.out"], - ["mul_d1__U111.in0","coeff_1_U110.out"], - ["self.d.0","mul_d0__U109.in1"], - ["self.d.1","mul_d1__U111.in1"] + ["mul_d0__U102.out","add_all__U106.in0"], + ["mul_d1__U104.out","add_all__U106.in1"], + ["add_all__U107.in0","add_all__U106.out"], + ["const_term_U105.out","add_all__U107.in1"], + ["self.out","add_all__U107.out"], + ["mul_d0__U102.in0","coeff_0_U101.out"], + ["mul_d1__U104.in0","coeff_1_U103.out"], + ["self.d.0","mul_d0__U102.in1"], + ["self.d.1","mul_d1__U104.in1"] ] }, - "aff__U122":{ + "aff__U114":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U128":{ + "add_all__U120":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U129":{ + "add_all__U121":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U123":{ + "coeff_0_U115":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U125":{ + "coeff_1_U117":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U127":{ + "const_term_U119":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U124":{ + "mul_d0__U116":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U126":{ + "mul_d1__U118":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U124.out","add_all__U128.in0"], - ["mul_d1__U126.out","add_all__U128.in1"], - ["add_all__U129.in0","add_all__U128.out"], - ["const_term_U127.out","add_all__U129.in1"], - ["self.out","add_all__U129.out"], - ["mul_d0__U124.in0","coeff_0_U123.out"], - ["mul_d1__U126.in0","coeff_1_U125.out"], - ["self.d.0","mul_d0__U124.in1"], - ["self.d.1","mul_d1__U126.in1"] + ["mul_d0__U116.out","add_all__U120.in0"], + ["mul_d1__U118.out","add_all__U120.in1"], + ["add_all__U121.in0","add_all__U120.out"], + ["const_term_U119.out","add_all__U121.in1"], + ["self.out","add_all__U121.out"], + ["mul_d0__U116.in0","coeff_0_U115.out"], + ["mul_d1__U118.in0","coeff_1_U117.out"], + ["self.d.0","mul_d0__U116.in1"], + ["self.d.1","mul_d1__U118.in1"] ] }, - "aff__U137":{ + "aff__U127":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U147":{ + "add_all__U137":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U148":{ + "add_all__U138":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U149":{ + "add_all__U139":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U150":{ + "add_all__U140":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U138":{ + "coeff_0_U128":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U140":{ + "coeff_1_U130":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U142":{ + "coeff_2_U132":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U144":{ + "coeff_3_U134":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U146":{ + "const_term_U136":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U139":{ + "mul_d0__U129":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U141":{ + "mul_d1__U131":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U143":{ + "mul_d2__U133":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U145":{ + "mul_d3__U135":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U139.out","add_all__U147.in0"], - ["mul_d1__U141.out","add_all__U147.in1"], - ["add_all__U148.in0","add_all__U147.out"], - ["mul_d2__U143.out","add_all__U148.in1"], - ["add_all__U149.in0","add_all__U148.out"], - ["mul_d3__U145.out","add_all__U149.in1"], - ["add_all__U150.in0","add_all__U149.out"], - ["const_term_U146.out","add_all__U150.in1"], - ["self.out","add_all__U150.out"], - ["mul_d0__U139.in0","coeff_0_U138.out"], - ["mul_d1__U141.in0","coeff_1_U140.out"], - ["mul_d2__U143.in0","coeff_2_U142.out"], - ["mul_d3__U145.in0","coeff_3_U144.out"], - ["self.d.0","mul_d0__U139.in1"], - ["self.d.1","mul_d1__U141.in1"], - ["self.d.2","mul_d2__U143.in1"], - ["self.d.3","mul_d3__U145.in1"] + ["mul_d0__U129.out","add_all__U137.in0"], + ["mul_d1__U131.out","add_all__U137.in1"], + ["add_all__U138.in0","add_all__U137.out"], + ["mul_d2__U133.out","add_all__U138.in1"], + ["add_all__U139.in0","add_all__U138.out"], + ["mul_d3__U135.out","add_all__U139.in1"], + ["add_all__U140.in0","add_all__U139.out"], + ["const_term_U136.out","add_all__U140.in1"], + ["self.out","add_all__U140.out"], + ["mul_d0__U129.in0","coeff_0_U128.out"], + ["mul_d1__U131.in0","coeff_1_U130.out"], + ["mul_d2__U133.in0","coeff_2_U132.out"], + ["mul_d3__U135.in0","coeff_3_U134.out"], + ["self.d.0","mul_d0__U129.in1"], + ["self.d.1","mul_d1__U131.in1"], + ["self.d.2","mul_d2__U133.in1"], + ["self.d.3","mul_d3__U135.in1"] ] }, - "aff__U160":{ + "aff__U150":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U170":{ + "add_all__U160":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U171":{ + "add_all__U161":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U172":{ + "add_all__U162":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U173":{ + "add_all__U163":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U161":{ + "coeff_0_U151":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U163":{ + "coeff_1_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U165":{ + "coeff_2_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U167":{ + "coeff_3_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U169":{ + "const_term_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U162":{ + "mul_d0__U152":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U164":{ + "mul_d1__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U166":{ + "mul_d2__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U168":{ + "mul_d3__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U162.out","add_all__U170.in0"], - ["mul_d1__U164.out","add_all__U170.in1"], - ["add_all__U171.in0","add_all__U170.out"], - ["mul_d2__U166.out","add_all__U171.in1"], - ["add_all__U172.in0","add_all__U171.out"], - ["mul_d3__U168.out","add_all__U172.in1"], - ["add_all__U173.in0","add_all__U172.out"], - ["const_term_U169.out","add_all__U173.in1"], - ["self.out","add_all__U173.out"], - ["mul_d0__U162.in0","coeff_0_U161.out"], - ["mul_d1__U164.in0","coeff_1_U163.out"], - ["mul_d2__U166.in0","coeff_2_U165.out"], - ["mul_d3__U168.in0","coeff_3_U167.out"], - ["self.d.0","mul_d0__U162.in1"], - ["self.d.1","mul_d1__U164.in1"], - ["self.d.2","mul_d2__U166.in1"], - ["self.d.3","mul_d3__U168.in1"] + ["mul_d0__U152.out","add_all__U160.in0"], + ["mul_d1__U154.out","add_all__U160.in1"], + ["add_all__U161.in0","add_all__U160.out"], + ["mul_d2__U156.out","add_all__U161.in1"], + ["add_all__U162.in0","add_all__U161.out"], + ["mul_d3__U158.out","add_all__U162.in1"], + ["add_all__U163.in0","add_all__U162.out"], + ["const_term_U159.out","add_all__U163.in1"], + ["self.out","add_all__U163.out"], + ["mul_d0__U152.in0","coeff_0_U151.out"], + ["mul_d1__U154.in0","coeff_1_U153.out"], + ["mul_d2__U156.in0","coeff_2_U155.out"], + ["mul_d3__U158.in0","coeff_3_U157.out"], + ["self.d.0","mul_d0__U152.in1"], + ["self.d.1","mul_d1__U154.in1"], + ["self.d.2","mul_d2__U156.in1"], + ["self.d.3","mul_d3__U158.in1"] ] }, - "aff__U17":{ + "aff__U16":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U23":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U24":{ + "add_all__U23":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U18":{ + "coeff_0_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U20":{ + "coeff_1_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U22":{ + "const_term_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U19":{ + "mul_d0__U18":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U21":{ + "mul_d1__U20":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U19.out","add_all__U23.in0"], - ["mul_d1__U21.out","add_all__U23.in1"], - ["add_all__U24.in0","add_all__U23.out"], - ["const_term_U22.out","add_all__U24.in1"], - ["self.out","add_all__U24.out"], - ["mul_d0__U19.in0","coeff_0_U18.out"], - ["mul_d1__U21.in0","coeff_1_U20.out"], - ["self.d.0","mul_d0__U19.in1"], - ["self.d.1","mul_d1__U21.in1"] + ["mul_d0__U18.out","add_all__U22.in0"], + ["mul_d1__U20.out","add_all__U22.in1"], + ["add_all__U23.in0","add_all__U22.out"], + ["const_term_U21.out","add_all__U23.in1"], + ["self.out","add_all__U23.out"], + ["mul_d0__U18.in0","coeff_0_U17.out"], + ["mul_d1__U20.in0","coeff_1_U19.out"], + ["self.d.0","mul_d0__U18.in1"], + ["self.d.1","mul_d1__U20.in1"] ] }, - "aff__U176":{ + "aff__U166":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U186":{ + "add_all__U176":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U187":{ + "add_all__U177":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U188":{ + "add_all__U178":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U189":{ + "add_all__U179":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U177":{ + "coeff_0_U167":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U179":{ + "coeff_1_U169":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U181":{ + "coeff_2_U171":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U183":{ + "coeff_3_U173":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U185":{ + "const_term_U175":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0001ffff"]} }, - "mul_d0__U178":{ + "mul_d0__U168":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U180":{ + "mul_d1__U170":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U182":{ + "mul_d2__U172":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U184":{ + "mul_d3__U174":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U178.out","add_all__U186.in0"], - ["mul_d1__U180.out","add_all__U186.in1"], - ["add_all__U187.in0","add_all__U186.out"], - ["mul_d2__U182.out","add_all__U187.in1"], - ["add_all__U188.in0","add_all__U187.out"], - ["mul_d3__U184.out","add_all__U188.in1"], - ["add_all__U189.in0","add_all__U188.out"], - ["const_term_U185.out","add_all__U189.in1"], - ["self.out","add_all__U189.out"], - ["mul_d0__U178.in0","coeff_0_U177.out"], - ["mul_d1__U180.in0","coeff_1_U179.out"], - ["mul_d2__U182.in0","coeff_2_U181.out"], - ["mul_d3__U184.in0","coeff_3_U183.out"], - ["self.d.0","mul_d0__U178.in1"], - ["self.d.1","mul_d1__U180.in1"], - ["self.d.2","mul_d2__U182.in1"], - ["self.d.3","mul_d3__U184.in1"] + ["mul_d0__U168.out","add_all__U176.in0"], + ["mul_d1__U170.out","add_all__U176.in1"], + ["add_all__U177.in0","add_all__U176.out"], + ["mul_d2__U172.out","add_all__U177.in1"], + ["add_all__U178.in0","add_all__U177.out"], + ["mul_d3__U174.out","add_all__U178.in1"], + ["add_all__U179.in0","add_all__U178.out"], + ["const_term_U175.out","add_all__U179.in1"], + ["self.out","add_all__U179.out"], + ["mul_d0__U168.in0","coeff_0_U167.out"], + ["mul_d1__U170.in0","coeff_1_U169.out"], + ["mul_d2__U172.in0","coeff_2_U171.out"], + ["mul_d3__U174.in0","coeff_3_U173.out"], + ["self.d.0","mul_d0__U168.in1"], + ["self.d.1","mul_d1__U170.in1"], + ["self.d.2","mul_d2__U172.in1"], + ["self.d.3","mul_d3__U174.in1"] ] }, - "aff__U199":{ + "aff__U189":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U209":{ + "add_all__U199":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U210":{ + "add_all__U200":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U211":{ + "add_all__U201":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U212":{ + "add_all__U202":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U200":{ + "coeff_0_U190":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U202":{ + "coeff_1_U192":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U204":{ + "coeff_2_U194":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U206":{ + "coeff_3_U196":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U208":{ + "const_term_U198":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U201":{ + "mul_d0__U191":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U203":{ + "mul_d1__U193":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U205":{ + "mul_d2__U195":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U207":{ + "mul_d3__U197":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U201.out","add_all__U209.in0"], - ["mul_d1__U203.out","add_all__U209.in1"], - ["add_all__U210.in0","add_all__U209.out"], - ["mul_d2__U205.out","add_all__U210.in1"], - ["add_all__U211.in0","add_all__U210.out"], - ["mul_d3__U207.out","add_all__U211.in1"], - ["add_all__U212.in0","add_all__U211.out"], - ["const_term_U208.out","add_all__U212.in1"], - ["self.out","add_all__U212.out"], - ["mul_d0__U201.in0","coeff_0_U200.out"], - ["mul_d1__U203.in0","coeff_1_U202.out"], - ["mul_d2__U205.in0","coeff_2_U204.out"], - ["mul_d3__U207.in0","coeff_3_U206.out"], - ["self.d.0","mul_d0__U201.in1"], - ["self.d.1","mul_d1__U203.in1"], - ["self.d.2","mul_d2__U205.in1"], - ["self.d.3","mul_d3__U207.in1"] + ["mul_d0__U191.out","add_all__U199.in0"], + ["mul_d1__U193.out","add_all__U199.in1"], + ["add_all__U200.in0","add_all__U199.out"], + ["mul_d2__U195.out","add_all__U200.in1"], + ["add_all__U201.in0","add_all__U200.out"], + ["mul_d3__U197.out","add_all__U201.in1"], + ["add_all__U202.in0","add_all__U201.out"], + ["const_term_U198.out","add_all__U202.in1"], + ["self.out","add_all__U202.out"], + ["mul_d0__U191.in0","coeff_0_U190.out"], + ["mul_d1__U193.in0","coeff_1_U192.out"], + ["mul_d2__U195.in0","coeff_2_U194.out"], + ["mul_d3__U197.in0","coeff_3_U196.out"], + ["self.d.0","mul_d0__U191.in1"], + ["self.d.1","mul_d1__U193.in1"], + ["self.d.2","mul_d2__U195.in1"], + ["self.d.3","mul_d3__U197.in1"] ] }, "aff__U2":{ @@ -538,623 +538,623 @@ ["self.d.1","mul_d1__U6.in1"] ] }, - "aff__U217":{ + "aff__U206":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U227":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U228":{ + "add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U229":{ + "add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U230":{ + "add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U218":{ + "coeff_0_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U220":{ + "coeff_1_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_2_U222":{ + "coeff_2_U211":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_3_U224":{ + "coeff_3_U213":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U226":{ + "const_term_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00022400"]} }, - "mul_d0__U219":{ + "mul_d0__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U221":{ + "mul_d1__U210":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U223":{ + "mul_d2__U212":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U225":{ + "mul_d3__U214":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U219.out","add_all__U227.in0"], - ["mul_d1__U221.out","add_all__U227.in1"], - ["add_all__U228.in0","add_all__U227.out"], - ["mul_d2__U223.out","add_all__U228.in1"], - ["add_all__U229.in0","add_all__U228.out"], - ["mul_d3__U225.out","add_all__U229.in1"], - ["add_all__U230.in0","add_all__U229.out"], - ["const_term_U226.out","add_all__U230.in1"], - ["self.out","add_all__U230.out"], - ["mul_d0__U219.in0","coeff_0_U218.out"], - ["mul_d1__U221.in0","coeff_1_U220.out"], - ["mul_d2__U223.in0","coeff_2_U222.out"], - ["mul_d3__U225.in0","coeff_3_U224.out"], - ["self.d.0","mul_d0__U219.in1"], - ["self.d.1","mul_d1__U221.in1"], - ["self.d.2","mul_d2__U223.in1"], - ["self.d.3","mul_d3__U225.in1"] + ["mul_d0__U208.out","add_all__U216.in0"], + ["mul_d1__U210.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d2__U212.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d3__U214.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["const_term_U215.out","add_all__U219.in1"], + ["self.out","add_all__U219.out"], + ["mul_d0__U208.in0","coeff_0_U207.out"], + ["mul_d1__U210.in0","coeff_1_U209.out"], + ["mul_d2__U212.in0","coeff_2_U211.out"], + ["mul_d3__U214.in0","coeff_3_U213.out"], + ["self.d.0","mul_d0__U208.in1"], + ["self.d.1","mul_d1__U210.in1"], + ["self.d.2","mul_d2__U212.in1"], + ["self.d.3","mul_d3__U214.in1"] ] }, - "aff__U240":{ + "aff__U229":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U250":{ + "add_all__U239":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U251":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U252":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U253":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U241":{ + "coeff_0_U230":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U243":{ + "coeff_1_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_2_U245":{ + "coeff_2_U234":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U247":{ + "coeff_3_U236":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U249":{ + "const_term_U238":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U242":{ + "mul_d0__U231":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U244":{ + "mul_d1__U233":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U246":{ + "mul_d2__U235":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U248":{ + "mul_d3__U237":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U242.out","add_all__U250.in0"], - ["mul_d1__U244.out","add_all__U250.in1"], - ["add_all__U251.in0","add_all__U250.out"], - ["mul_d2__U246.out","add_all__U251.in1"], - ["add_all__U252.in0","add_all__U251.out"], - ["mul_d3__U248.out","add_all__U252.in1"], - ["add_all__U253.in0","add_all__U252.out"], - ["const_term_U249.out","add_all__U253.in1"], - ["self.out","add_all__U253.out"], - ["mul_d0__U242.in0","coeff_0_U241.out"], - ["mul_d1__U244.in0","coeff_1_U243.out"], - ["mul_d2__U246.in0","coeff_2_U245.out"], - ["mul_d3__U248.in0","coeff_3_U247.out"], - ["self.d.0","mul_d0__U242.in1"], - ["self.d.1","mul_d1__U244.in1"], - ["self.d.2","mul_d2__U246.in1"], - ["self.d.3","mul_d3__U248.in1"] + ["mul_d0__U231.out","add_all__U239.in0"], + ["mul_d1__U233.out","add_all__U239.in1"], + ["add_all__U240.in0","add_all__U239.out"], + ["mul_d2__U235.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d3__U237.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["const_term_U238.out","add_all__U242.in1"], + ["self.out","add_all__U242.out"], + ["mul_d0__U231.in0","coeff_0_U230.out"], + ["mul_d1__U233.in0","coeff_1_U232.out"], + ["mul_d2__U235.in0","coeff_2_U234.out"], + ["mul_d3__U237.in0","coeff_3_U236.out"], + ["self.d.0","mul_d0__U231.in1"], + ["self.d.1","mul_d1__U233.in1"], + ["self.d.2","mul_d2__U235.in1"], + ["self.d.3","mul_d3__U237.in1"] ] }, - "aff__U256":{ + "aff__U245":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U264":{ + "add_all__U253":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U265":{ + "add_all__U254":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U266":{ + "add_all__U255":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U257":{ + "coeff_0_U246":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U259":{ + "coeff_1_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U261":{ + "coeff_2_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U263":{ + "const_term_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000407ff"]} }, - "mul_d0__U258":{ + "mul_d0__U247":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U260":{ + "mul_d1__U249":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U262":{ + "mul_d2__U251":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U258.out","add_all__U264.in0"], - ["mul_d1__U260.out","add_all__U264.in1"], - ["add_all__U265.in0","add_all__U264.out"], - ["mul_d2__U262.out","add_all__U265.in1"], - ["add_all__U266.in0","add_all__U265.out"], - ["const_term_U263.out","add_all__U266.in1"], - ["self.out","add_all__U266.out"], - ["mul_d0__U258.in0","coeff_0_U257.out"], - ["mul_d1__U260.in0","coeff_1_U259.out"], - ["mul_d2__U262.in0","coeff_2_U261.out"], - ["self.d.0","mul_d0__U258.in1"], - ["self.d.1","mul_d1__U260.in1"], - ["self.d.2","mul_d2__U262.in1"] + ["mul_d0__U247.out","add_all__U253.in0"], + ["mul_d1__U249.out","add_all__U253.in1"], + ["add_all__U254.in0","add_all__U253.out"], + ["mul_d2__U251.out","add_all__U254.in1"], + ["add_all__U255.in0","add_all__U254.out"], + ["const_term_U252.out","add_all__U255.in1"], + ["self.out","add_all__U255.out"], + ["mul_d0__U247.in0","coeff_0_U246.out"], + ["mul_d1__U249.in0","coeff_1_U248.out"], + ["mul_d2__U251.in0","coeff_2_U250.out"], + ["self.d.0","mul_d0__U247.in1"], + ["self.d.1","mul_d1__U249.in1"], + ["self.d.2","mul_d2__U251.in1"] ] }, - "aff__U273":{ + "aff__U262":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U281":{ + "add_all__U270":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U282":{ + "add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U283":{ + "add_all__U272":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U274":{ + "coeff_0_U263":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U276":{ + "coeff_1_U265":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U278":{ + "coeff_2_U267":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U280":{ + "const_term_U269":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U275":{ + "mul_d0__U264":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U277":{ + "mul_d1__U266":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U279":{ + "mul_d2__U268":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U275.out","add_all__U281.in0"], - ["mul_d1__U277.out","add_all__U281.in1"], - ["add_all__U282.in0","add_all__U281.out"], - ["mul_d2__U279.out","add_all__U282.in1"], - ["add_all__U283.in0","add_all__U282.out"], - ["const_term_U280.out","add_all__U283.in1"], - ["self.out","add_all__U283.out"], - ["mul_d0__U275.in0","coeff_0_U274.out"], - ["mul_d1__U277.in0","coeff_1_U276.out"], - ["mul_d2__U279.in0","coeff_2_U278.out"], - ["self.d.0","mul_d0__U275.in1"], - ["self.d.1","mul_d1__U277.in1"], - ["self.d.2","mul_d2__U279.in1"] + ["mul_d0__U264.out","add_all__U270.in0"], + ["mul_d1__U266.out","add_all__U270.in1"], + ["add_all__U271.in0","add_all__U270.out"], + ["mul_d2__U268.out","add_all__U271.in1"], + ["add_all__U272.in0","add_all__U271.out"], + ["const_term_U269.out","add_all__U272.in1"], + ["self.out","add_all__U272.out"], + ["mul_d0__U264.in0","coeff_0_U263.out"], + ["mul_d1__U266.in0","coeff_1_U265.out"], + ["mul_d2__U268.in0","coeff_2_U267.out"], + ["self.d.0","mul_d0__U264.in1"], + ["self.d.1","mul_d1__U266.in1"], + ["self.d.2","mul_d2__U268.in1"] ] }, - "aff__U287":{ + "aff__U276":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U295":{ + "add_all__U284":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U296":{ + "add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U297":{ + "add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U288":{ + "coeff_0_U277":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U290":{ + "coeff_1_U279":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U292":{ + "coeff_2_U281":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U294":{ + "const_term_U283":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00040800"]} }, - "mul_d0__U289":{ + "mul_d0__U278":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U291":{ + "mul_d1__U280":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U293":{ + "mul_d2__U282":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U289.out","add_all__U295.in0"], - ["mul_d1__U291.out","add_all__U295.in1"], - ["add_all__U296.in0","add_all__U295.out"], - ["mul_d2__U293.out","add_all__U296.in1"], - ["add_all__U297.in0","add_all__U296.out"], - ["const_term_U294.out","add_all__U297.in1"], - ["self.out","add_all__U297.out"], - ["mul_d0__U289.in0","coeff_0_U288.out"], - ["mul_d1__U291.in0","coeff_1_U290.out"], - ["mul_d2__U293.in0","coeff_2_U292.out"], - ["self.d.0","mul_d0__U289.in1"], - ["self.d.1","mul_d1__U291.in1"], - ["self.d.2","mul_d2__U293.in1"] + ["mul_d0__U278.out","add_all__U284.in0"], + ["mul_d1__U280.out","add_all__U284.in1"], + ["add_all__U285.in0","add_all__U284.out"], + ["mul_d2__U282.out","add_all__U285.in1"], + ["add_all__U286.in0","add_all__U285.out"], + ["const_term_U283.out","add_all__U286.in1"], + ["self.out","add_all__U286.out"], + ["mul_d0__U278.in0","coeff_0_U277.out"], + ["mul_d1__U280.in0","coeff_1_U279.out"], + ["mul_d2__U282.in0","coeff_2_U281.out"], + ["self.d.0","mul_d0__U278.in1"], + ["self.d.1","mul_d1__U280.in1"], + ["self.d.2","mul_d2__U282.in1"] ] }, - "aff__U32":{ + "aff__U30":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U38":{ + "add_all__U36":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U39":{ + "add_all__U37":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U33":{ + "coeff_0_U31":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U35":{ + "coeff_1_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U37":{ + "const_term_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U34":{ + "mul_d0__U32":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U36":{ + "mul_d1__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U34.out","add_all__U38.in0"], - ["mul_d1__U36.out","add_all__U38.in1"], - ["add_all__U39.in0","add_all__U38.out"], - ["const_term_U37.out","add_all__U39.in1"], - ["self.out","add_all__U39.out"], - ["mul_d0__U34.in0","coeff_0_U33.out"], - ["mul_d1__U36.in0","coeff_1_U35.out"], - ["self.d.0","mul_d0__U34.in1"], - ["self.d.1","mul_d1__U36.in1"] + ["mul_d0__U32.out","add_all__U36.in0"], + ["mul_d1__U34.out","add_all__U36.in1"], + ["add_all__U37.in0","add_all__U36.out"], + ["const_term_U35.out","add_all__U37.in1"], + ["self.out","add_all__U37.out"], + ["mul_d0__U32.in0","coeff_0_U31.out"], + ["mul_d1__U34.in0","coeff_1_U33.out"], + ["self.d.0","mul_d0__U32.in1"], + ["self.d.1","mul_d1__U34.in1"] ] }, - "aff__U47":{ + "aff__U44":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U53":{ + "add_all__U50":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U51":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U48":{ + "coeff_0_U45":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U50":{ + "coeff_1_U47":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U52":{ + "const_term_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U49":{ + "mul_d0__U46":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U51":{ + "mul_d1__U48":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U49.out","add_all__U53.in0"], - ["mul_d1__U51.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U52.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U49.in0","coeff_0_U48.out"], - ["mul_d1__U51.in0","coeff_1_U50.out"], - ["self.d.0","mul_d0__U49.in1"], - ["self.d.1","mul_d1__U51.in1"] + ["mul_d0__U46.out","add_all__U50.in0"], + ["mul_d1__U48.out","add_all__U50.in1"], + ["add_all__U51.in0","add_all__U50.out"], + ["const_term_U49.out","add_all__U51.in1"], + ["self.out","add_all__U51.out"], + ["mul_d0__U46.in0","coeff_0_U45.out"], + ["mul_d1__U48.in0","coeff_1_U47.out"], + ["self.d.0","mul_d0__U46.in1"], + ["self.d.1","mul_d1__U48.in1"] ] }, - "aff__U62":{ + "aff__U58":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U68":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U69":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U63":{ + "coeff_0_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U65":{ + "coeff_1_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U67":{ + "const_term_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U64":{ + "mul_d0__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U66":{ + "mul_d1__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U64.out","add_all__U68.in0"], - ["mul_d1__U66.out","add_all__U68.in1"], - ["add_all__U69.in0","add_all__U68.out"], - ["const_term_U67.out","add_all__U69.in1"], - ["self.out","add_all__U69.out"], - ["mul_d0__U64.in0","coeff_0_U63.out"], - ["mul_d1__U66.in0","coeff_1_U65.out"], - ["self.d.0","mul_d0__U64.in1"], - ["self.d.1","mul_d1__U66.in1"] + ["mul_d0__U60.out","add_all__U64.in0"], + ["mul_d1__U62.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["const_term_U63.out","add_all__U65.in1"], + ["self.out","add_all__U65.out"], + ["mul_d0__U60.in0","coeff_0_U59.out"], + ["mul_d1__U62.in0","coeff_1_U61.out"], + ["self.d.0","mul_d0__U60.in1"], + ["self.d.1","mul_d1__U62.in1"] ] }, - "aff__U77":{ + "aff__U72":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U83":{ + "add_all__U78":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U84":{ + "add_all__U79":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U78":{ + "coeff_0_U73":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U80":{ + "coeff_1_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U82":{ + "const_term_U77":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U79":{ + "mul_d0__U74":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U81":{ + "mul_d1__U76":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U79.out","add_all__U83.in0"], - ["mul_d1__U81.out","add_all__U83.in1"], - ["add_all__U84.in0","add_all__U83.out"], - ["const_term_U82.out","add_all__U84.in1"], - ["self.out","add_all__U84.out"], - ["mul_d0__U79.in0","coeff_0_U78.out"], - ["mul_d1__U81.in0","coeff_1_U80.out"], - ["self.d.0","mul_d0__U79.in1"], - ["self.d.1","mul_d1__U81.in1"] + ["mul_d0__U74.out","add_all__U78.in0"], + ["mul_d1__U76.out","add_all__U78.in1"], + ["add_all__U79.in0","add_all__U78.out"], + ["const_term_U77.out","add_all__U79.in1"], + ["self.out","add_all__U79.out"], + ["mul_d0__U74.in0","coeff_0_U73.out"], + ["mul_d1__U76.in0","coeff_1_U75.out"], + ["self.d.0","mul_d0__U74.in1"], + ["self.d.1","mul_d1__U76.in1"] ] }, - "aff__U92":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U98":{ + "add_all__U92":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U99":{ + "add_all__U93":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U93":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U95":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U97":{ + "const_term_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U94":{ + "mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U96":{ + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U94.out","add_all__U98.in0"], - ["mul_d1__U96.out","add_all__U98.in1"], - ["add_all__U99.in0","add_all__U98.out"], - ["const_term_U97.out","add_all__U99.in1"], - ["self.out","add_all__U99.out"], - ["mul_d0__U94.in0","coeff_0_U93.out"], - ["mul_d1__U96.in0","coeff_1_U95.out"], - ["self.d.0","mul_d0__U94.in1"], - ["self.d.1","mul_d1__U96.in1"] + ["mul_d0__U88.out","add_all__U92.in0"], + ["mul_d1__U90.out","add_all__U92.in1"], + ["add_all__U93.in0","add_all__U92.out"], + ["const_term_U91.out","add_all__U93.in1"], + ["self.out","add_all__U93.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"] ] }, "affine_controller__U1":{ @@ -1304,7 +1304,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U106":{ + "affine_controller__U113":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1312,18 +1312,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U115":{ + "_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U116":{ + "_U123":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U107" + "modref":"global.aff__U114" }, "cmp_time":{ "genref":"coreir.eq", @@ -1333,7 +1333,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U117":{ + "d_0_am__U124":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1408,9 +1408,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U115.out"], - ["d_1_inc.in1","_U115.out"], - ["cmp_time.in1","_U116.out"], + ["d_0_inc.in1","_U122.out"], + ["d_1_inc.in1","_U122.out"], + ["cmp_time.in1","_U123.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -1421,9 +1421,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U117.in0"], - ["d_1_at_max.out","d_0_am__U117.in1"], - ["d_0_next_value.sel","d_0_am__U117.out"], + ["true.out","d_0_am__U124.in0"], + ["d_1_at_max.out","d_0_am__U124.in1"], + ["d_0_next_value.sel","d_0_am__U124.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1451,154 +1451,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U121":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U130":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U131":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U122" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U132":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U130.out"], - ["d_1_inc.in1","_U130.out"], - ["cmp_time.in1","_U131.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U132.in0"], - ["d_1_at_max.out","d_0_am__U132.in1"], - ["d_0_next_value.sel","d_0_am__U132.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] - ] - }, - "affine_controller__U136":{ + "affine_controller__U126":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1606,18 +1459,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U151":{ + "_U141":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U152":{ + "_U142":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U137" + "modref":"global.aff__U127" }, "cmp_time":{ "genref":"coreir.eq", @@ -1627,13 +1480,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U153":{ + "d_0_am__U143":{ "modref":"corebit.and" }, - "d_0_am__U154":{ + "d_0_am__U144":{ "modref":"corebit.and" }, - "d_0_am__U155":{ + "d_0_am__U145":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1667,10 +1520,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U156":{ + "d_1_am__U146":{ "modref":"corebit.and" }, - "d_1_am__U157":{ + "d_1_am__U147":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1704,7 +1557,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U158":{ + "d_2_am__U148":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -1779,11 +1632,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U151.out"], - ["d_1_inc.in1","_U151.out"], - ["d_2_inc.in1","_U151.out"], - ["d_3_inc.in1","_U151.out"], - ["cmp_time.in1","_U152.out"], + ["d_0_inc.in1","_U141.out"], + ["d_1_inc.in1","_U141.out"], + ["d_2_inc.in1","_U141.out"], + ["d_3_inc.in1","_U141.out"], + ["cmp_time.in1","_U142.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -1798,13 +1651,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U153.in0"], - ["d_1_at_max.out","d_0_am__U153.in1"], - ["d_0_am__U154.in0","d_0_am__U153.out"], - ["d_2_at_max.out","d_0_am__U154.in1"], - ["d_0_am__U155.in0","d_0_am__U154.out"], - ["d_3_at_max.out","d_0_am__U155.in1"], - ["d_0_next_value.sel","d_0_am__U155.out"], + ["true.out","d_0_am__U143.in0"], + ["d_1_at_max.out","d_0_am__U143.in1"], + ["d_0_am__U144.in0","d_0_am__U143.out"], + ["d_2_at_max.out","d_0_am__U144.in1"], + ["d_0_am__U145.in0","d_0_am__U144.out"], + ["d_3_at_max.out","d_0_am__U145.in1"], + ["d_0_next_value.sel","d_0_am__U145.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1817,11 +1670,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U156.in0"], - ["d_2_at_max.out","d_1_am__U156.in1"], - ["d_1_am__U157.in0","d_1_am__U156.out"], - ["d_3_at_max.out","d_1_am__U157.in1"], - ["d_1_next_value.sel","d_1_am__U157.out"], + ["true.out","d_1_am__U146.in0"], + ["d_2_at_max.out","d_1_am__U146.in1"], + ["d_1_am__U147.in0","d_1_am__U146.out"], + ["d_3_at_max.out","d_1_am__U147.in1"], + ["d_1_next_value.sel","d_1_am__U147.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1834,9 +1687,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U158.in0"], - ["d_3_at_max.out","d_2_am__U158.in1"], - ["d_2_next_value.sel","d_2_am__U158.out"], + ["true.out","d_2_am__U148.in0"], + ["d_3_at_max.out","d_2_am__U148.in1"], + ["d_2_next_value.sel","d_2_am__U148.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -1864,7 +1717,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U16":{ + "affine_controller__U15":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1872,18 +1725,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U25":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U26":{ + "_U25":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U17" + "modref":"global.aff__U16" }, "cmp_time":{ "genref":"coreir.eq", @@ -1893,7 +1746,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U27":{ + "d_0_am__U26":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1968,9 +1821,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U25.out"], - ["d_1_inc.in1","_U25.out"], - ["cmp_time.in1","_U26.out"], + ["d_0_inc.in1","_U24.out"], + ["d_1_inc.in1","_U24.out"], + ["cmp_time.in1","_U25.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -1981,9 +1834,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U27.in0"], - ["d_1_at_max.out","d_0_am__U27.in1"], - ["d_0_next_value.sel","d_0_am__U27.out"], + ["true.out","d_0_am__U26.in0"], + ["d_1_at_max.out","d_0_am__U26.in1"], + ["d_0_next_value.sel","d_0_am__U26.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2011,7 +1864,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U175":{ + "affine_controller__U165":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2019,18 +1872,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U190":{ + "_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U191":{ + "_U181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U176" + "modref":"global.aff__U166" }, "cmp_time":{ "genref":"coreir.eq", @@ -2040,13 +1893,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U192":{ + "d_0_am__U182":{ "modref":"corebit.and" }, - "d_0_am__U193":{ + "d_0_am__U183":{ "modref":"corebit.and" }, - "d_0_am__U194":{ + "d_0_am__U184":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2080,10 +1933,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U195":{ + "d_1_am__U185":{ "modref":"corebit.and" }, - "d_1_am__U196":{ + "d_1_am__U186":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2117,7 +1970,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U197":{ + "d_2_am__U187":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2192,11 +2045,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U190.out"], - ["d_1_inc.in1","_U190.out"], - ["d_2_inc.in1","_U190.out"], - ["d_3_inc.in1","_U190.out"], - ["cmp_time.in1","_U191.out"], + ["d_0_inc.in1","_U180.out"], + ["d_1_inc.in1","_U180.out"], + ["d_2_inc.in1","_U180.out"], + ["d_3_inc.in1","_U180.out"], + ["cmp_time.in1","_U181.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2211,13 +2064,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U192.in0"], - ["d_1_at_max.out","d_0_am__U192.in1"], - ["d_0_am__U193.in0","d_0_am__U192.out"], - ["d_2_at_max.out","d_0_am__U193.in1"], - ["d_0_am__U194.in0","d_0_am__U193.out"], - ["d_3_at_max.out","d_0_am__U194.in1"], - ["d_0_next_value.sel","d_0_am__U194.out"], + ["true.out","d_0_am__U182.in0"], + ["d_1_at_max.out","d_0_am__U182.in1"], + ["d_0_am__U183.in0","d_0_am__U182.out"], + ["d_2_at_max.out","d_0_am__U183.in1"], + ["d_0_am__U184.in0","d_0_am__U183.out"], + ["d_3_at_max.out","d_0_am__U184.in1"], + ["d_0_next_value.sel","d_0_am__U184.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2230,11 +2083,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U195.in0"], - ["d_2_at_max.out","d_1_am__U195.in1"], - ["d_1_am__U196.in0","d_1_am__U195.out"], - ["d_3_at_max.out","d_1_am__U196.in1"], - ["d_1_next_value.sel","d_1_am__U196.out"], + ["true.out","d_1_am__U185.in0"], + ["d_2_at_max.out","d_1_am__U185.in1"], + ["d_1_am__U186.in0","d_1_am__U185.out"], + ["d_3_at_max.out","d_1_am__U186.in1"], + ["d_1_next_value.sel","d_1_am__U186.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2247,9 +2100,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U197.in0"], - ["d_3_at_max.out","d_2_am__U197.in1"], - ["d_2_next_value.sel","d_2_am__U197.out"], + ["true.out","d_2_am__U187.in0"], + ["d_3_at_max.out","d_2_am__U187.in1"], + ["d_2_next_value.sel","d_2_am__U187.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2277,7 +2130,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U216":{ + "affine_controller__U205":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2285,18 +2138,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U231":{ + "_U220":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U232":{ + "_U221":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U217" + "modref":"global.aff__U206" }, "cmp_time":{ "genref":"coreir.eq", @@ -2306,13 +2159,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U233":{ + "d_0_am__U222":{ "modref":"corebit.and" }, - "d_0_am__U234":{ + "d_0_am__U223":{ "modref":"corebit.and" }, - "d_0_am__U235":{ + "d_0_am__U224":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2346,10 +2199,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U236":{ + "d_1_am__U225":{ "modref":"corebit.and" }, - "d_1_am__U237":{ + "d_1_am__U226":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2383,7 +2236,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U238":{ + "d_2_am__U227":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2458,11 +2311,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U231.out"], - ["d_1_inc.in1","_U231.out"], - ["d_2_inc.in1","_U231.out"], - ["d_3_inc.in1","_U231.out"], - ["cmp_time.in1","_U232.out"], + ["d_0_inc.in1","_U220.out"], + ["d_1_inc.in1","_U220.out"], + ["d_2_inc.in1","_U220.out"], + ["d_3_inc.in1","_U220.out"], + ["cmp_time.in1","_U221.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2477,13 +2330,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U233.in0"], - ["d_1_at_max.out","d_0_am__U233.in1"], - ["d_0_am__U234.in0","d_0_am__U233.out"], - ["d_2_at_max.out","d_0_am__U234.in1"], - ["d_0_am__U235.in0","d_0_am__U234.out"], - ["d_3_at_max.out","d_0_am__U235.in1"], - ["d_0_next_value.sel","d_0_am__U235.out"], + ["true.out","d_0_am__U222.in0"], + ["d_1_at_max.out","d_0_am__U222.in1"], + ["d_0_am__U223.in0","d_0_am__U222.out"], + ["d_2_at_max.out","d_0_am__U223.in1"], + ["d_0_am__U224.in0","d_0_am__U223.out"], + ["d_3_at_max.out","d_0_am__U224.in1"], + ["d_0_next_value.sel","d_0_am__U224.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2496,11 +2349,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U236.in0"], - ["d_2_at_max.out","d_1_am__U236.in1"], - ["d_1_am__U237.in0","d_1_am__U236.out"], - ["d_3_at_max.out","d_1_am__U237.in1"], - ["d_1_next_value.sel","d_1_am__U237.out"], + ["true.out","d_1_am__U225.in0"], + ["d_2_at_max.out","d_1_am__U225.in1"], + ["d_1_am__U226.in0","d_1_am__U225.out"], + ["d_3_at_max.out","d_1_am__U226.in1"], + ["d_1_next_value.sel","d_1_am__U226.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2513,9 +2366,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U238.in0"], - ["d_3_at_max.out","d_2_am__U238.in1"], - ["d_2_next_value.sel","d_2_am__U238.out"], + ["true.out","d_2_am__U227.in0"], + ["d_3_at_max.out","d_2_am__U227.in1"], + ["d_2_next_value.sel","d_2_am__U227.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2543,7 +2396,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U255":{ + "affine_controller__U244":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2551,18 +2404,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U267":{ + "_U256":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U268":{ + "_U257":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U256" + "modref":"global.aff__U245" }, "cmp_time":{ "genref":"coreir.eq", @@ -2572,10 +2425,10 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U269":{ + "d_0_am__U258":{ "modref":"corebit.and" }, - "d_0_am__U270":{ + "d_0_am__U259":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2609,7 +2462,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U271":{ + "d_1_am__U260":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2684,10 +2537,10 @@ } }, "connections":[ - ["d_0_inc.in1","_U267.out"], - ["d_1_inc.in1","_U267.out"], - ["d_2_inc.in1","_U267.out"], - ["cmp_time.in1","_U268.out"], + ["d_0_inc.in1","_U256.out"], + ["d_1_inc.in1","_U256.out"], + ["d_2_inc.in1","_U256.out"], + ["cmp_time.in1","_U257.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2700,11 +2553,11 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U269.in0"], - ["d_1_at_max.out","d_0_am__U269.in1"], - ["d_0_am__U270.in0","d_0_am__U269.out"], - ["d_2_at_max.out","d_0_am__U270.in1"], - ["d_0_next_value.sel","d_0_am__U270.out"], + ["true.out","d_0_am__U258.in0"], + ["d_1_at_max.out","d_0_am__U258.in1"], + ["d_0_am__U259.in0","d_0_am__U258.out"], + ["d_2_at_max.out","d_0_am__U259.in1"], + ["d_0_next_value.sel","d_0_am__U259.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2717,9 +2570,9 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U271.in0"], - ["d_2_at_max.out","d_1_am__U271.in1"], - ["d_1_next_value.sel","d_1_am__U271.out"], + ["true.out","d_1_am__U260.in0"], + ["d_2_at_max.out","d_1_am__U260.in1"], + ["d_1_next_value.sel","d_1_am__U260.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2747,7 +2600,7 @@ ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U286":{ + "affine_controller__U275":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2755,18 +2608,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U298":{ + "_U287":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U299":{ + "_U288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U287" + "modref":"global.aff__U276" }, "cmp_time":{ "genref":"coreir.eq", @@ -2776,10 +2629,10 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U300":{ + "d_0_am__U289":{ "modref":"corebit.and" }, - "d_0_am__U301":{ + "d_0_am__U290":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2813,7 +2666,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U302":{ + "d_1_am__U291":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2888,10 +2741,10 @@ } }, "connections":[ - ["d_0_inc.in1","_U298.out"], - ["d_1_inc.in1","_U298.out"], - ["d_2_inc.in1","_U298.out"], - ["cmp_time.in1","_U299.out"], + ["d_0_inc.in1","_U287.out"], + ["d_1_inc.in1","_U287.out"], + ["d_2_inc.in1","_U287.out"], + ["cmp_time.in1","_U288.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2904,11 +2757,11 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U300.in0"], - ["d_1_at_max.out","d_0_am__U300.in1"], - ["d_0_am__U301.in0","d_0_am__U300.out"], - ["d_2_at_max.out","d_0_am__U301.in1"], - ["d_0_next_value.sel","d_0_am__U301.out"], + ["true.out","d_0_am__U289.in0"], + ["d_1_at_max.out","d_0_am__U289.in1"], + ["d_0_am__U290.in0","d_0_am__U289.out"], + ["d_2_at_max.out","d_0_am__U290.in1"], + ["d_0_next_value.sel","d_0_am__U290.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2921,9 +2774,9 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U302.in0"], - ["d_2_at_max.out","d_1_am__U302.in1"], - ["d_1_next_value.sel","d_1_am__U302.out"], + ["true.out","d_1_am__U291.in0"], + ["d_2_at_max.out","d_1_am__U291.in1"], + ["d_1_next_value.sel","d_1_am__U291.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2951,7 +2804,7 @@ ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U31":{ + "affine_controller__U29":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2959,18 +2812,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U40":{ + "_U38":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U41":{ + "_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U32" + "modref":"global.aff__U30" }, "cmp_time":{ "genref":"coreir.eq", @@ -2980,7 +2833,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U42":{ + "d_0_am__U40":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3055,9 +2908,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U40.out"], - ["d_1_inc.in1","_U40.out"], - ["cmp_time.in1","_U41.out"], + ["d_0_inc.in1","_U38.out"], + ["d_1_inc.in1","_U38.out"], + ["cmp_time.in1","_U39.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3068,9 +2921,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U42.in0"], - ["d_1_at_max.out","d_0_am__U42.in1"], - ["d_0_next_value.sel","d_0_am__U42.out"], + ["true.out","d_0_am__U40.in0"], + ["d_1_at_max.out","d_0_am__U40.in1"], + ["d_0_next_value.sel","d_0_am__U40.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3098,7 +2951,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U46":{ + "affine_controller__U43":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3106,18 +2959,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U55":{ + "_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U56":{ + "_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U47" + "modref":"global.aff__U44" }, "cmp_time":{ "genref":"coreir.eq", @@ -3127,7 +2980,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U57":{ + "d_0_am__U54":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3202,9 +3055,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U55.out"], - ["d_1_inc.in1","_U55.out"], - ["cmp_time.in1","_U56.out"], + ["d_0_inc.in1","_U52.out"], + ["d_1_inc.in1","_U52.out"], + ["cmp_time.in1","_U53.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3215,9 +3068,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U57.in0"], - ["d_1_at_max.out","d_0_am__U57.in1"], - ["d_0_next_value.sel","d_0_am__U57.out"], + ["true.out","d_0_am__U54.in0"], + ["d_1_at_max.out","d_0_am__U54.in1"], + ["d_0_next_value.sel","d_0_am__U54.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3245,7 +3098,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U61":{ + "affine_controller__U57":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3253,18 +3106,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U70":{ + "_U66":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U71":{ + "_U67":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U62" + "modref":"global.aff__U58" }, "cmp_time":{ "genref":"coreir.eq", @@ -3274,7 +3127,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U72":{ + "d_0_am__U68":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3349,9 +3202,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U70.out"], - ["d_1_inc.in1","_U70.out"], - ["cmp_time.in1","_U71.out"], + ["d_0_inc.in1","_U66.out"], + ["d_1_inc.in1","_U66.out"], + ["cmp_time.in1","_U67.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3362,9 +3215,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U72.in0"], - ["d_1_at_max.out","d_0_am__U72.in1"], - ["d_0_next_value.sel","d_0_am__U72.out"], + ["true.out","d_0_am__U68.in0"], + ["d_1_at_max.out","d_0_am__U68.in1"], + ["d_0_next_value.sel","d_0_am__U68.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3392,7 +3245,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U76":{ + "affine_controller__U71":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3400,18 +3253,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U85":{ + "_U80":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U86":{ + "_U81":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U77" + "modref":"global.aff__U72" }, "cmp_time":{ "genref":"coreir.eq", @@ -3421,7 +3274,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U87":{ + "d_0_am__U82":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3496,9 +3349,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U85.out"], - ["d_1_inc.in1","_U85.out"], - ["cmp_time.in1","_U86.out"], + ["d_0_inc.in1","_U80.out"], + ["d_1_inc.in1","_U80.out"], + ["cmp_time.in1","_U81.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3509,9 +3362,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U87.in0"], - ["d_1_at_max.out","d_0_am__U87.in1"], - ["d_0_next_value.sel","d_0_am__U87.out"], + ["true.out","d_0_am__U82.in0"], + ["d_1_at_max.out","d_0_am__U82.in1"], + ["d_0_next_value.sel","d_0_am__U82.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3539,7 +3392,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U91":{ + "affine_controller__U85":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3547,18 +3400,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U100":{ + "_U94":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U101":{ + "_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U92" + "modref":"global.aff__U86" }, "cmp_time":{ "genref":"coreir.eq", @@ -3568,7 +3421,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U102":{ + "d_0_am__U96":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3643,9 +3496,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U100.out"], - ["d_1_inc.in1","_U100.out"], - ["cmp_time.in1","_U101.out"], + ["d_0_inc.in1","_U94.out"], + ["d_1_inc.in1","_U94.out"], + ["cmp_time.in1","_U95.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3656,9 +3509,156 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U102.in0"], - ["d_1_at_max.out","d_0_am__U102.in1"], - ["d_0_next_value.sel","d_0_am__U102.out"], + ["true.out","d_0_am__U96.in0"], + ["d_1_at_max.out","d_0_am__U96.in1"], + ["d_0_next_value.sel","d_0_am__U96.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"] + ] + }, + "affine_controller__U99":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U108":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U109":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U100" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U110":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U108.out"], + ["d_1_inc.in1","_U108.out"], + ["cmp_time.in1","_U109.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U110.in0"], + ["d_1_at_max.out","d_0_am__U110.in1"], + ["d_0_next_value.sel","d_0_am__U110.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3701,18 +3701,14 @@ ["op_hcompute_output_gb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U14":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ctrl__U13":{ "modref":"global.affine_controller__U1", "metadata":{"garnet_rewire_flush":true} }, "ub_conv_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[8196],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[9214],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[8196],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[9214],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_conv_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -3720,7 +3716,6 @@ } }, "connections":[ - ["ub_conv_stencil_BANK_0.chain_chain_en","chain_en_const_U14.out"], ["self.clk","ctrl__U13.clk"], ["ub_conv_stencil_BANK_0.flush","ctrl__U13.valid"], ["ub_conv_stencil_BANK_0.clk","self.clk"], @@ -3863,7 +3858,7 @@ ["input_host_stencil_op_hcompute_input_gb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U313":{ + "_U302":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -3890,47 +3885,47 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U305" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U294" }, "op_hcompute_hw_output_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U306" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U295" }, "op_hcompute_hw_output_stencil_port_controller":{ - "modref":"global.affine_controller__U286", + "modref":"global.affine_controller__U275", "metadata":{"lake_config":{"stencil_valid":{"cycle_starting_addr":[264192],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}}} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U303" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U292" }, "op_hcompute_hw_output_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U304" + "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U293" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U307" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U296" }, "op_hcompute_hw_output_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U308" + "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U297" }, "op_hcompute_input_gb_stencil":{ "modref":"global.cu_op_hcompute_input_gb_stencil" }, "op_hcompute_input_gb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_gb_stencil_exe_start_pt__U311" + "modref":"global.op_hcompute_input_gb_stencil_exe_start_pt__U300" }, "op_hcompute_input_gb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U309"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,1024],"dimensionality":3,"extent":[8,128,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U309"} + "genargs":{"ID":["String","_U298"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,1024],"dimensionality":3,"extent":[8,128,128]}},"mode":"lake"} }, "op_hcompute_input_gb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_gb_stencil_read_start":{ - "modref":"global.op_hcompute_input_gb_stencil_read_start_pt__U310" + "modref":"global.op_hcompute_input_gb_stencil_read_start_pt__U299" }, "op_hcompute_input_gb_stencil_write_start":{ - "modref":"global.op_hcompute_input_gb_stencil_write_start_pt__U312" + "modref":"global.op_hcompute_input_gb_stencil_write_start_pt__U301" }, "op_hcompute_output_gb_stencil":{ "modref":"global.cu_op_hcompute_output_gb_stencil" @@ -3940,8 +3935,8 @@ } }, "connections":[ - ["self.clk","_U313.clk"], - ["self.input_host_stencil_op_hcompute_input_gb_stencil_read.0","_U313.in"], + ["self.clk","_U302.clk"], + ["self.input_host_stencil_op_hcompute_input_gb_stencil_read.0","_U302.in"], ["self.clk","conv_stencil.clk"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_read","conv_stencil.op_hcompute_conv_stencil_1_read"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], @@ -4109,74 +4104,42 @@ ["op_hcompute_hw_input_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U104":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U44":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U74":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "ctrl__U103":{ - "modref":"global.affine_controller__U91", + "ctrl__U111":{ + "modref":"global.affine_controller__U99", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U118":{ - "modref":"global.affine_controller__U106", + "ctrl__U125":{ + "modref":"global.affine_controller__U113", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U133":{ - "modref":"global.affine_controller__U121", + "ctrl__U27":{ + "modref":"global.affine_controller__U15", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U28":{ - "modref":"global.affine_controller__U16", + "ctrl__U41":{ + "modref":"global.affine_controller__U29", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U43":{ - "modref":"global.affine_controller__U31", + "ctrl__U55":{ + "modref":"global.affine_controller__U43", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U58":{ - "modref":"global.affine_controller__U46", + "ctrl__U69":{ + "modref":"global.affine_controller__U57", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U73":{ - "modref":"global.affine_controller__U61", + "ctrl__U83":{ + "modref":"global.affine_controller__U71", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U88":{ - "modref":"global.affine_controller__U76", + "ctrl__U97":{ + "modref":"global.affine_controller__U85", "metadata":{"garnet_rewire_flush":true} }, "ub_hw_input_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U15"} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -4184,8 +4147,8 @@ }, "ub_hw_input_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U30"} + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -4193,8 +4156,8 @@ }, "ub_hw_input_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U45"} + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -4202,8 +4165,8 @@ }, "ub_hw_input_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U60"} + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -4211,8 +4174,8 @@ }, "ub_hw_input_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U75"} + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -4220,8 +4183,8 @@ }, "ub_hw_input_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U90"} + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -4229,8 +4192,8 @@ }, "ub_hw_input_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U105"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U105"} + "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -4238,8 +4201,8 @@ }, "ub_hw_input_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U120"} + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_hw_input_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -4247,30 +4210,22 @@ } }, "connections":[ - ["ub_hw_input_stencil_BANK_5.chain_chain_en","chain_en_const_U104.out"], - ["ub_hw_input_stencil_BANK_6.chain_chain_en","chain_en_const_U119.out"], - ["ub_hw_input_stencil_BANK_7.chain_chain_en","chain_en_const_U134.out"], - ["ub_hw_input_stencil_BANK_0.chain_chain_en","chain_en_const_U29.out"], - ["ub_hw_input_stencil_BANK_1.chain_chain_en","chain_en_const_U44.out"], - ["ub_hw_input_stencil_BANK_2.chain_chain_en","chain_en_const_U59.out"], - ["ub_hw_input_stencil_BANK_3.chain_chain_en","chain_en_const_U74.out"], - ["ub_hw_input_stencil_BANK_4.chain_chain_en","chain_en_const_U89.out"], - ["self.clk","ctrl__U103.clk"], - ["ub_hw_input_stencil_BANK_5.flush","ctrl__U103.valid"], - ["self.clk","ctrl__U118.clk"], - ["ub_hw_input_stencil_BANK_6.flush","ctrl__U118.valid"], - ["self.clk","ctrl__U133.clk"], - ["ub_hw_input_stencil_BANK_7.flush","ctrl__U133.valid"], - ["self.clk","ctrl__U28.clk"], - ["ub_hw_input_stencil_BANK_0.flush","ctrl__U28.valid"], - ["self.clk","ctrl__U43.clk"], - ["ub_hw_input_stencil_BANK_1.flush","ctrl__U43.valid"], - ["self.clk","ctrl__U58.clk"], - ["ub_hw_input_stencil_BANK_2.flush","ctrl__U58.valid"], - ["self.clk","ctrl__U73.clk"], - ["ub_hw_input_stencil_BANK_3.flush","ctrl__U73.valid"], - ["self.clk","ctrl__U88.clk"], - ["ub_hw_input_stencil_BANK_4.flush","ctrl__U88.valid"], + ["self.clk","ctrl__U111.clk"], + ["ub_hw_input_stencil_BANK_6.flush","ctrl__U111.valid"], + ["self.clk","ctrl__U125.clk"], + ["ub_hw_input_stencil_BANK_7.flush","ctrl__U125.valid"], + ["self.clk","ctrl__U27.clk"], + ["ub_hw_input_stencil_BANK_0.flush","ctrl__U27.valid"], + ["self.clk","ctrl__U41.clk"], + ["ub_hw_input_stencil_BANK_1.flush","ctrl__U41.valid"], + ["self.clk","ctrl__U55.clk"], + ["ub_hw_input_stencil_BANK_2.flush","ctrl__U55.valid"], + ["self.clk","ctrl__U69.clk"], + ["ub_hw_input_stencil_BANK_3.flush","ctrl__U69.valid"], + ["self.clk","ctrl__U83.clk"], + ["ub_hw_input_stencil_BANK_4.flush","ctrl__U83.valid"], + ["self.clk","ctrl__U97.clk"], + ["ub_hw_input_stencil_BANK_5.flush","ctrl__U97.valid"], ["ub_hw_input_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_stencil_BANK_1.clk","self.clk"], ["ub_hw_input_stencil_BANK_2.clk","self.clk"], @@ -4324,49 +4279,49 @@ ["op_hcompute_input_gb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_hw_input_stencil_7_U213":{ - "modref":"global.aff__U199" + "addrgen_input_glb_stencil_op_hcompute_hw_input_stencil_7_U203":{ + "modref":"global.aff__U189" }, - "addrgen_input_glb_stencil_op_hcompute_input_gb_stencil_2_U174":{ - "modref":"global.aff__U160" + "addrgen_input_glb_stencil_op_hcompute_input_gb_stencil_2_U164":{ + "modref":"global.aff__U150" }, - "chain_en_const_U214":{ + "chain_en_const_U204":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U159":{ - "modref":"global.affine_controller__U136", + "ctrl__U149":{ + "modref":"global.affine_controller__U126", "metadata":{"garnet_remove":true} }, - "ctrl__U198":{ - "modref":"global.affine_controller__U175", + "ctrl__U188":{ + "modref":"global.affine_controller__U165", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[131072],"cycle_stride":[1],"dimensionality":1,"extent":[131072],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[131072],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U135"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[131072],"cycle_stride":[1],"dimensionality":1,"extent":[131072],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[131072],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U198.d","addrgen_input_glb_stencil_op_hcompute_hw_input_stencil_7_U213.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_hw_input_stencil_7_U213.out"], - ["ctrl__U159.d","addrgen_input_glb_stencil_op_hcompute_input_gb_stencil_2_U174.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_gb_stencil_2_U174.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U214.out"], - ["self.clk","ctrl__U159.clk"], - ["self.reset","ctrl__U159.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U159.valid"], - ["self.clk","ctrl__U198.clk"], - ["self.reset","ctrl__U198.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U198.valid"], + ["ctrl__U188.d","addrgen_input_glb_stencil_op_hcompute_hw_input_stencil_7_U203.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_hw_input_stencil_7_U203.out"], + ["ctrl__U149.d","addrgen_input_glb_stencil_op_hcompute_input_gb_stencil_2_U164.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_gb_stencil_2_U164.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U204.out"], + ["self.clk","ctrl__U149.clk"], + ["self.reset","ctrl__U149.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U149.valid"], + ["self.clk","ctrl__U188.clk"], + ["self.reset","ctrl__U188.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U188.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_gb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_input_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], ["self.reset","input_glb_stencil_BANK_0_ubuf.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U306":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U295":{ "type":["Record",[ ["in",["Array",3,["Array",32,"BitIn"]]], ["out",["Array",3,["Array",32,"Bit"]]] @@ -4375,7 +4330,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U305":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U294":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4384,7 +4339,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U304":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U293":{ "type":["Record",[ ["in",["Array",3,["Array",32,"BitIn"]]], ["out",["Array",3,["Array",32,"Bit"]]] @@ -4393,7 +4348,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U303":{ + "op_hcompute_hw_output_stencil_read_start_pt__U292":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4402,7 +4357,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U308":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U297":{ "type":["Record",[ ["in",["Array",3,["Array",32,"BitIn"]]], ["out",["Array",3,["Array",32,"Bit"]]] @@ -4411,7 +4366,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U307":{ + "op_hcompute_hw_output_stencil_write_start_pt__U296":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4420,7 +4375,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_gb_stencil_exe_start_pt__U311":{ + "op_hcompute_input_gb_stencil_exe_start_pt__U300":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4429,7 +4384,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_gb_stencil_read_start_pt__U310":{ + "op_hcompute_input_gb_stencil_read_start_pt__U299":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4438,7 +4393,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_gb_stencil_write_start_pt__U312":{ + "op_hcompute_input_gb_stencil_write_start_pt__U301":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4458,42 +4413,42 @@ ["op_hcompute_output_gb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_5_U284":{ - "modref":"global.aff__U273" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_5_U273":{ + "modref":"global.aff__U262" }, - "addrgen_output_glb_stencil_op_hcompute_output_gb_stencil_0_U254":{ - "modref":"global.aff__U240" + "addrgen_output_glb_stencil_op_hcompute_output_gb_stencil_0_U243":{ + "modref":"global.aff__U229" }, - "chain_en_const_U285":{ + "chain_en_const_U274":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U239":{ - "modref":"global.affine_controller__U216", + "ctrl__U228":{ + "modref":"global.affine_controller__U205", "metadata":{"garnet_remove":true} }, - "ctrl__U272":{ - "modref":"global.affine_controller__U255", + "ctrl__U261":{ + "modref":"global.affine_controller__U244", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[264192],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[140288],"cycle_stride":[1,8192],"dimensionality":2,"extent":[1024,16],"write_data_starting_addr":[0],"write_data_stride":[1,1024]}},"mode":"glb","verilog_name":"glb__U215"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[264192],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[140288],"cycle_stride":[1,8192],"dimensionality":2,"extent":[1024,16],"write_data_starting_addr":[0],"write_data_stride":[1,1024]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U272.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_5_U284.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_5_U284.out"], - ["ctrl__U239.d","addrgen_output_glb_stencil_op_hcompute_output_gb_stencil_0_U254.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_gb_stencil_0_U254.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U285.out"], - ["self.clk","ctrl__U239.clk"], - ["self.reset","ctrl__U239.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U239.valid"], - ["self.clk","ctrl__U272.clk"], - ["self.reset","ctrl__U272.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U272.valid"], + ["ctrl__U261.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_5_U273.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_5_U273.out"], + ["ctrl__U228.d","addrgen_output_glb_stencil_op_hcompute_output_gb_stencil_0_U243.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_gb_stencil_0_U243.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U274.out"], + ["self.clk","ctrl__U228.clk"], + ["self.reset","ctrl__U228.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U228.valid"], + ["self.clk","ctrl__U261.clk"], + ["self.reset","ctrl__U261.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U261.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_gb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], diff --git a/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction_garnet.json b/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction_garnet.json index 6772934b9..efb11174c 100644 --- a/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction_garnet.json +++ b/aha_garnet_design_new/glb_channel_reduction/glb_channel_reduction_garnet.json @@ -232,490 +232,490 @@ }, "global":{ "modules":{ - "aff__U107":{ + "aff__U100":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U113":{ + "add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U108":{ + "coeff_0_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U110":{ + "coeff_1_U103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U112":{ + "const_term_U105":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U109":{ + "mul_d0__U102":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U111":{ + "mul_d1__U104":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U109.out","add_all__U113.in0"], - ["mul_d1__U111.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U112.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U109.in0","coeff_0_U108.out"], - ["mul_d1__U111.in0","coeff_1_U110.out"], - ["self.d.0","mul_d0__U109.in1"], - ["self.d.1","mul_d1__U111.in1"] + ["mul_d0__U102.out","add_all__U106.in0"], + ["mul_d1__U104.out","add_all__U106.in1"], + ["add_all__U107.in0","add_all__U106.out"], + ["const_term_U105.out","add_all__U107.in1"], + ["self.out","add_all__U107.out"], + ["mul_d0__U102.in0","coeff_0_U101.out"], + ["mul_d1__U104.in0","coeff_1_U103.out"], + ["self.d.0","mul_d0__U102.in1"], + ["self.d.1","mul_d1__U104.in1"] ] }, - "aff__U122":{ + "aff__U114":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U128":{ + "add_all__U120":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U129":{ + "add_all__U121":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U123":{ + "coeff_0_U115":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U125":{ + "coeff_1_U117":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U127":{ + "const_term_U119":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U124":{ + "mul_d0__U116":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U126":{ + "mul_d1__U118":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U124.out","add_all__U128.in0"], - ["mul_d1__U126.out","add_all__U128.in1"], - ["add_all__U129.in0","add_all__U128.out"], - ["const_term_U127.out","add_all__U129.in1"], - ["self.out","add_all__U129.out"], - ["mul_d0__U124.in0","coeff_0_U123.out"], - ["mul_d1__U126.in0","coeff_1_U125.out"], - ["self.d.0","mul_d0__U124.in1"], - ["self.d.1","mul_d1__U126.in1"] + ["mul_d0__U116.out","add_all__U120.in0"], + ["mul_d1__U118.out","add_all__U120.in1"], + ["add_all__U121.in0","add_all__U120.out"], + ["const_term_U119.out","add_all__U121.in1"], + ["self.out","add_all__U121.out"], + ["mul_d0__U116.in0","coeff_0_U115.out"], + ["mul_d1__U118.in0","coeff_1_U117.out"], + ["self.d.0","mul_d0__U116.in1"], + ["self.d.1","mul_d1__U118.in1"] ] }, - "aff__U137":{ + "aff__U127":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U147":{ + "add_all__U137":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U148":{ + "add_all__U138":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U149":{ + "add_all__U139":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U150":{ + "add_all__U140":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U138":{ + "coeff_0_U128":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U140":{ + "coeff_1_U130":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U142":{ + "coeff_2_U132":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U144":{ + "coeff_3_U134":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U146":{ + "const_term_U136":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U139":{ + "mul_d0__U129":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U141":{ + "mul_d1__U131":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U143":{ + "mul_d2__U133":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U145":{ + "mul_d3__U135":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U139.out","add_all__U147.in0"], - ["mul_d1__U141.out","add_all__U147.in1"], - ["add_all__U148.in0","add_all__U147.out"], - ["mul_d2__U143.out","add_all__U148.in1"], - ["add_all__U149.in0","add_all__U148.out"], - ["mul_d3__U145.out","add_all__U149.in1"], - ["add_all__U150.in0","add_all__U149.out"], - ["const_term_U146.out","add_all__U150.in1"], - ["self.out","add_all__U150.out"], - ["mul_d0__U139.in0","coeff_0_U138.out"], - ["mul_d1__U141.in0","coeff_1_U140.out"], - ["mul_d2__U143.in0","coeff_2_U142.out"], - ["mul_d3__U145.in0","coeff_3_U144.out"], - ["self.d.0","mul_d0__U139.in1"], - ["self.d.1","mul_d1__U141.in1"], - ["self.d.2","mul_d2__U143.in1"], - ["self.d.3","mul_d3__U145.in1"] + ["mul_d0__U129.out","add_all__U137.in0"], + ["mul_d1__U131.out","add_all__U137.in1"], + ["add_all__U138.in0","add_all__U137.out"], + ["mul_d2__U133.out","add_all__U138.in1"], + ["add_all__U139.in0","add_all__U138.out"], + ["mul_d3__U135.out","add_all__U139.in1"], + ["add_all__U140.in0","add_all__U139.out"], + ["const_term_U136.out","add_all__U140.in1"], + ["self.out","add_all__U140.out"], + ["mul_d0__U129.in0","coeff_0_U128.out"], + ["mul_d1__U131.in0","coeff_1_U130.out"], + ["mul_d2__U133.in0","coeff_2_U132.out"], + ["mul_d3__U135.in0","coeff_3_U134.out"], + ["self.d.0","mul_d0__U129.in1"], + ["self.d.1","mul_d1__U131.in1"], + ["self.d.2","mul_d2__U133.in1"], + ["self.d.3","mul_d3__U135.in1"] ] }, - "aff__U160":{ + "aff__U150":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U170":{ + "add_all__U160":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U171":{ + "add_all__U161":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U172":{ + "add_all__U162":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U173":{ + "add_all__U163":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U161":{ + "coeff_0_U151":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U163":{ + "coeff_1_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U165":{ + "coeff_2_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U167":{ + "coeff_3_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U169":{ + "const_term_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U162":{ + "mul_d0__U152":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U164":{ + "mul_d1__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U166":{ + "mul_d2__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U168":{ + "mul_d3__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U162.out","add_all__U170.in0"], - ["mul_d1__U164.out","add_all__U170.in1"], - ["add_all__U171.in0","add_all__U170.out"], - ["mul_d2__U166.out","add_all__U171.in1"], - ["add_all__U172.in0","add_all__U171.out"], - ["mul_d3__U168.out","add_all__U172.in1"], - ["add_all__U173.in0","add_all__U172.out"], - ["const_term_U169.out","add_all__U173.in1"], - ["self.out","add_all__U173.out"], - ["mul_d0__U162.in0","coeff_0_U161.out"], - ["mul_d1__U164.in0","coeff_1_U163.out"], - ["mul_d2__U166.in0","coeff_2_U165.out"], - ["mul_d3__U168.in0","coeff_3_U167.out"], - ["self.d.0","mul_d0__U162.in1"], - ["self.d.1","mul_d1__U164.in1"], - ["self.d.2","mul_d2__U166.in1"], - ["self.d.3","mul_d3__U168.in1"] + ["mul_d0__U152.out","add_all__U160.in0"], + ["mul_d1__U154.out","add_all__U160.in1"], + ["add_all__U161.in0","add_all__U160.out"], + ["mul_d2__U156.out","add_all__U161.in1"], + ["add_all__U162.in0","add_all__U161.out"], + ["mul_d3__U158.out","add_all__U162.in1"], + ["add_all__U163.in0","add_all__U162.out"], + ["const_term_U159.out","add_all__U163.in1"], + ["self.out","add_all__U163.out"], + ["mul_d0__U152.in0","coeff_0_U151.out"], + ["mul_d1__U154.in0","coeff_1_U153.out"], + ["mul_d2__U156.in0","coeff_2_U155.out"], + ["mul_d3__U158.in0","coeff_3_U157.out"], + ["self.d.0","mul_d0__U152.in1"], + ["self.d.1","mul_d1__U154.in1"], + ["self.d.2","mul_d2__U156.in1"], + ["self.d.3","mul_d3__U158.in1"] ] }, - "aff__U17":{ + "aff__U16":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U23":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U24":{ + "add_all__U23":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U18":{ + "coeff_0_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U20":{ + "coeff_1_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U22":{ + "const_term_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U19":{ + "mul_d0__U18":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U21":{ + "mul_d1__U20":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U19.out","add_all__U23.in0"], - ["mul_d1__U21.out","add_all__U23.in1"], - ["add_all__U24.in0","add_all__U23.out"], - ["const_term_U22.out","add_all__U24.in1"], - ["self.out","add_all__U24.out"], - ["mul_d0__U19.in0","coeff_0_U18.out"], - ["mul_d1__U21.in0","coeff_1_U20.out"], - ["self.d.0","mul_d0__U19.in1"], - ["self.d.1","mul_d1__U21.in1"] + ["mul_d0__U18.out","add_all__U22.in0"], + ["mul_d1__U20.out","add_all__U22.in1"], + ["add_all__U23.in0","add_all__U22.out"], + ["const_term_U21.out","add_all__U23.in1"], + ["self.out","add_all__U23.out"], + ["mul_d0__U18.in0","coeff_0_U17.out"], + ["mul_d1__U20.in0","coeff_1_U19.out"], + ["self.d.0","mul_d0__U18.in1"], + ["self.d.1","mul_d1__U20.in1"] ] }, - "aff__U176":{ + "aff__U166":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U186":{ + "add_all__U176":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U187":{ + "add_all__U177":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U188":{ + "add_all__U178":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U189":{ + "add_all__U179":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U177":{ + "coeff_0_U167":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U179":{ + "coeff_1_U169":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U181":{ + "coeff_2_U171":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U183":{ + "coeff_3_U173":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U185":{ + "const_term_U175":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0001ffff"]} }, - "mul_d0__U178":{ + "mul_d0__U168":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U180":{ + "mul_d1__U170":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U182":{ + "mul_d2__U172":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U184":{ + "mul_d3__U174":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U178.out","add_all__U186.in0"], - ["mul_d1__U180.out","add_all__U186.in1"], - ["add_all__U187.in0","add_all__U186.out"], - ["mul_d2__U182.out","add_all__U187.in1"], - ["add_all__U188.in0","add_all__U187.out"], - ["mul_d3__U184.out","add_all__U188.in1"], - ["add_all__U189.in0","add_all__U188.out"], - ["const_term_U185.out","add_all__U189.in1"], - ["self.out","add_all__U189.out"], - ["mul_d0__U178.in0","coeff_0_U177.out"], - ["mul_d1__U180.in0","coeff_1_U179.out"], - ["mul_d2__U182.in0","coeff_2_U181.out"], - ["mul_d3__U184.in0","coeff_3_U183.out"], - ["self.d.0","mul_d0__U178.in1"], - ["self.d.1","mul_d1__U180.in1"], - ["self.d.2","mul_d2__U182.in1"], - ["self.d.3","mul_d3__U184.in1"] + ["mul_d0__U168.out","add_all__U176.in0"], + ["mul_d1__U170.out","add_all__U176.in1"], + ["add_all__U177.in0","add_all__U176.out"], + ["mul_d2__U172.out","add_all__U177.in1"], + ["add_all__U178.in0","add_all__U177.out"], + ["mul_d3__U174.out","add_all__U178.in1"], + ["add_all__U179.in0","add_all__U178.out"], + ["const_term_U175.out","add_all__U179.in1"], + ["self.out","add_all__U179.out"], + ["mul_d0__U168.in0","coeff_0_U167.out"], + ["mul_d1__U170.in0","coeff_1_U169.out"], + ["mul_d2__U172.in0","coeff_2_U171.out"], + ["mul_d3__U174.in0","coeff_3_U173.out"], + ["self.d.0","mul_d0__U168.in1"], + ["self.d.1","mul_d1__U170.in1"], + ["self.d.2","mul_d2__U172.in1"], + ["self.d.3","mul_d3__U174.in1"] ] }, - "aff__U199":{ + "aff__U189":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U209":{ + "add_all__U199":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U210":{ + "add_all__U200":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U211":{ + "add_all__U201":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U212":{ + "add_all__U202":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U200":{ + "coeff_0_U190":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U202":{ + "coeff_1_U192":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U204":{ + "coeff_2_U194":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_3_U206":{ + "coeff_3_U196":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U208":{ + "const_term_U198":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U201":{ + "mul_d0__U191":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U203":{ + "mul_d1__U193":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U205":{ + "mul_d2__U195":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U207":{ + "mul_d3__U197":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U201.out","add_all__U209.in0"], - ["mul_d1__U203.out","add_all__U209.in1"], - ["add_all__U210.in0","add_all__U209.out"], - ["mul_d2__U205.out","add_all__U210.in1"], - ["add_all__U211.in0","add_all__U210.out"], - ["mul_d3__U207.out","add_all__U211.in1"], - ["add_all__U212.in0","add_all__U211.out"], - ["const_term_U208.out","add_all__U212.in1"], - ["self.out","add_all__U212.out"], - ["mul_d0__U201.in0","coeff_0_U200.out"], - ["mul_d1__U203.in0","coeff_1_U202.out"], - ["mul_d2__U205.in0","coeff_2_U204.out"], - ["mul_d3__U207.in0","coeff_3_U206.out"], - ["self.d.0","mul_d0__U201.in1"], - ["self.d.1","mul_d1__U203.in1"], - ["self.d.2","mul_d2__U205.in1"], - ["self.d.3","mul_d3__U207.in1"] + ["mul_d0__U191.out","add_all__U199.in0"], + ["mul_d1__U193.out","add_all__U199.in1"], + ["add_all__U200.in0","add_all__U199.out"], + ["mul_d2__U195.out","add_all__U200.in1"], + ["add_all__U201.in0","add_all__U200.out"], + ["mul_d3__U197.out","add_all__U201.in1"], + ["add_all__U202.in0","add_all__U201.out"], + ["const_term_U198.out","add_all__U202.in1"], + ["self.out","add_all__U202.out"], + ["mul_d0__U191.in0","coeff_0_U190.out"], + ["mul_d1__U193.in0","coeff_1_U192.out"], + ["mul_d2__U195.in0","coeff_2_U194.out"], + ["mul_d3__U197.in0","coeff_3_U196.out"], + ["self.d.0","mul_d0__U191.in1"], + ["self.d.1","mul_d1__U193.in1"], + ["self.d.2","mul_d2__U195.in1"], + ["self.d.3","mul_d3__U197.in1"] ] }, "aff__U2":{ @@ -768,623 +768,623 @@ ["self.d.1","mul_d1__U6.in1"] ] }, - "aff__U217":{ + "aff__U206":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U227":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U228":{ + "add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U229":{ + "add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U230":{ + "add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U218":{ + "coeff_0_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U220":{ + "coeff_1_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_2_U222":{ + "coeff_2_U211":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_3_U224":{ + "coeff_3_U213":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U226":{ + "const_term_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00022400"]} }, - "mul_d0__U219":{ + "mul_d0__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U221":{ + "mul_d1__U210":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U223":{ + "mul_d2__U212":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U225":{ + "mul_d3__U214":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U219.out","add_all__U227.in0"], - ["mul_d1__U221.out","add_all__U227.in1"], - ["add_all__U228.in0","add_all__U227.out"], - ["mul_d2__U223.out","add_all__U228.in1"], - ["add_all__U229.in0","add_all__U228.out"], - ["mul_d3__U225.out","add_all__U229.in1"], - ["add_all__U230.in0","add_all__U229.out"], - ["const_term_U226.out","add_all__U230.in1"], - ["self.out","add_all__U230.out"], - ["mul_d0__U219.in0","coeff_0_U218.out"], - ["mul_d1__U221.in0","coeff_1_U220.out"], - ["mul_d2__U223.in0","coeff_2_U222.out"], - ["mul_d3__U225.in0","coeff_3_U224.out"], - ["self.d.0","mul_d0__U219.in1"], - ["self.d.1","mul_d1__U221.in1"], - ["self.d.2","mul_d2__U223.in1"], - ["self.d.3","mul_d3__U225.in1"] + ["mul_d0__U208.out","add_all__U216.in0"], + ["mul_d1__U210.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d2__U212.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d3__U214.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["const_term_U215.out","add_all__U219.in1"], + ["self.out","add_all__U219.out"], + ["mul_d0__U208.in0","coeff_0_U207.out"], + ["mul_d1__U210.in0","coeff_1_U209.out"], + ["mul_d2__U212.in0","coeff_2_U211.out"], + ["mul_d3__U214.in0","coeff_3_U213.out"], + ["self.d.0","mul_d0__U208.in1"], + ["self.d.1","mul_d1__U210.in1"], + ["self.d.2","mul_d2__U212.in1"], + ["self.d.3","mul_d3__U214.in1"] ] }, - "aff__U240":{ + "aff__U229":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U250":{ + "add_all__U239":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U251":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U252":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U253":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U241":{ + "coeff_0_U230":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U243":{ + "coeff_1_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_2_U245":{ + "coeff_2_U234":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U247":{ + "coeff_3_U236":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U249":{ + "const_term_U238":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U242":{ + "mul_d0__U231":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U244":{ + "mul_d1__U233":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U246":{ + "mul_d2__U235":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U248":{ + "mul_d3__U237":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U242.out","add_all__U250.in0"], - ["mul_d1__U244.out","add_all__U250.in1"], - ["add_all__U251.in0","add_all__U250.out"], - ["mul_d2__U246.out","add_all__U251.in1"], - ["add_all__U252.in0","add_all__U251.out"], - ["mul_d3__U248.out","add_all__U252.in1"], - ["add_all__U253.in0","add_all__U252.out"], - ["const_term_U249.out","add_all__U253.in1"], - ["self.out","add_all__U253.out"], - ["mul_d0__U242.in0","coeff_0_U241.out"], - ["mul_d1__U244.in0","coeff_1_U243.out"], - ["mul_d2__U246.in0","coeff_2_U245.out"], - ["mul_d3__U248.in0","coeff_3_U247.out"], - ["self.d.0","mul_d0__U242.in1"], - ["self.d.1","mul_d1__U244.in1"], - ["self.d.2","mul_d2__U246.in1"], - ["self.d.3","mul_d3__U248.in1"] + ["mul_d0__U231.out","add_all__U239.in0"], + ["mul_d1__U233.out","add_all__U239.in1"], + ["add_all__U240.in0","add_all__U239.out"], + ["mul_d2__U235.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d3__U237.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["const_term_U238.out","add_all__U242.in1"], + ["self.out","add_all__U242.out"], + ["mul_d0__U231.in0","coeff_0_U230.out"], + ["mul_d1__U233.in0","coeff_1_U232.out"], + ["mul_d2__U235.in0","coeff_2_U234.out"], + ["mul_d3__U237.in0","coeff_3_U236.out"], + ["self.d.0","mul_d0__U231.in1"], + ["self.d.1","mul_d1__U233.in1"], + ["self.d.2","mul_d2__U235.in1"], + ["self.d.3","mul_d3__U237.in1"] ] }, - "aff__U256":{ + "aff__U245":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U264":{ + "add_all__U253":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U265":{ + "add_all__U254":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U266":{ + "add_all__U255":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U257":{ + "coeff_0_U246":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U259":{ + "coeff_1_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U261":{ + "coeff_2_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U263":{ + "const_term_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000407ff"]} }, - "mul_d0__U258":{ + "mul_d0__U247":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U260":{ + "mul_d1__U249":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U262":{ + "mul_d2__U251":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U258.out","add_all__U264.in0"], - ["mul_d1__U260.out","add_all__U264.in1"], - ["add_all__U265.in0","add_all__U264.out"], - ["mul_d2__U262.out","add_all__U265.in1"], - ["add_all__U266.in0","add_all__U265.out"], - ["const_term_U263.out","add_all__U266.in1"], - ["self.out","add_all__U266.out"], - ["mul_d0__U258.in0","coeff_0_U257.out"], - ["mul_d1__U260.in0","coeff_1_U259.out"], - ["mul_d2__U262.in0","coeff_2_U261.out"], - ["self.d.0","mul_d0__U258.in1"], - ["self.d.1","mul_d1__U260.in1"], - ["self.d.2","mul_d2__U262.in1"] + ["mul_d0__U247.out","add_all__U253.in0"], + ["mul_d1__U249.out","add_all__U253.in1"], + ["add_all__U254.in0","add_all__U253.out"], + ["mul_d2__U251.out","add_all__U254.in1"], + ["add_all__U255.in0","add_all__U254.out"], + ["const_term_U252.out","add_all__U255.in1"], + ["self.out","add_all__U255.out"], + ["mul_d0__U247.in0","coeff_0_U246.out"], + ["mul_d1__U249.in0","coeff_1_U248.out"], + ["mul_d2__U251.in0","coeff_2_U250.out"], + ["self.d.0","mul_d0__U247.in1"], + ["self.d.1","mul_d1__U249.in1"], + ["self.d.2","mul_d2__U251.in1"] ] }, - "aff__U273":{ + "aff__U262":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U281":{ + "add_all__U270":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U282":{ + "add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U283":{ + "add_all__U272":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U274":{ + "coeff_0_U263":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U276":{ + "coeff_1_U265":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U278":{ + "coeff_2_U267":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U280":{ + "const_term_U269":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U275":{ + "mul_d0__U264":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U277":{ + "mul_d1__U266":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U279":{ + "mul_d2__U268":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U275.out","add_all__U281.in0"], - ["mul_d1__U277.out","add_all__U281.in1"], - ["add_all__U282.in0","add_all__U281.out"], - ["mul_d2__U279.out","add_all__U282.in1"], - ["add_all__U283.in0","add_all__U282.out"], - ["const_term_U280.out","add_all__U283.in1"], - ["self.out","add_all__U283.out"], - ["mul_d0__U275.in0","coeff_0_U274.out"], - ["mul_d1__U277.in0","coeff_1_U276.out"], - ["mul_d2__U279.in0","coeff_2_U278.out"], - ["self.d.0","mul_d0__U275.in1"], - ["self.d.1","mul_d1__U277.in1"], - ["self.d.2","mul_d2__U279.in1"] + ["mul_d0__U264.out","add_all__U270.in0"], + ["mul_d1__U266.out","add_all__U270.in1"], + ["add_all__U271.in0","add_all__U270.out"], + ["mul_d2__U268.out","add_all__U271.in1"], + ["add_all__U272.in0","add_all__U271.out"], + ["const_term_U269.out","add_all__U272.in1"], + ["self.out","add_all__U272.out"], + ["mul_d0__U264.in0","coeff_0_U263.out"], + ["mul_d1__U266.in0","coeff_1_U265.out"], + ["mul_d2__U268.in0","coeff_2_U267.out"], + ["self.d.0","mul_d0__U264.in1"], + ["self.d.1","mul_d1__U266.in1"], + ["self.d.2","mul_d2__U268.in1"] ] }, - "aff__U287":{ + "aff__U276":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U295":{ + "add_all__U284":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U296":{ + "add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U297":{ + "add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U288":{ + "coeff_0_U277":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U290":{ + "coeff_1_U279":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U292":{ + "coeff_2_U281":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U294":{ + "const_term_U283":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00040800"]} }, - "mul_d0__U289":{ + "mul_d0__U278":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U291":{ + "mul_d1__U280":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U293":{ + "mul_d2__U282":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U289.out","add_all__U295.in0"], - ["mul_d1__U291.out","add_all__U295.in1"], - ["add_all__U296.in0","add_all__U295.out"], - ["mul_d2__U293.out","add_all__U296.in1"], - ["add_all__U297.in0","add_all__U296.out"], - ["const_term_U294.out","add_all__U297.in1"], - ["self.out","add_all__U297.out"], - ["mul_d0__U289.in0","coeff_0_U288.out"], - ["mul_d1__U291.in0","coeff_1_U290.out"], - ["mul_d2__U293.in0","coeff_2_U292.out"], - ["self.d.0","mul_d0__U289.in1"], - ["self.d.1","mul_d1__U291.in1"], - ["self.d.2","mul_d2__U293.in1"] + ["mul_d0__U278.out","add_all__U284.in0"], + ["mul_d1__U280.out","add_all__U284.in1"], + ["add_all__U285.in0","add_all__U284.out"], + ["mul_d2__U282.out","add_all__U285.in1"], + ["add_all__U286.in0","add_all__U285.out"], + ["const_term_U283.out","add_all__U286.in1"], + ["self.out","add_all__U286.out"], + ["mul_d0__U278.in0","coeff_0_U277.out"], + ["mul_d1__U280.in0","coeff_1_U279.out"], + ["mul_d2__U282.in0","coeff_2_U281.out"], + ["self.d.0","mul_d0__U278.in1"], + ["self.d.1","mul_d1__U280.in1"], + ["self.d.2","mul_d2__U282.in1"] ] }, - "aff__U32":{ + "aff__U30":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U38":{ + "add_all__U36":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U39":{ + "add_all__U37":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U33":{ + "coeff_0_U31":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U35":{ + "coeff_1_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U37":{ + "const_term_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U34":{ + "mul_d0__U32":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U36":{ + "mul_d1__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U34.out","add_all__U38.in0"], - ["mul_d1__U36.out","add_all__U38.in1"], - ["add_all__U39.in0","add_all__U38.out"], - ["const_term_U37.out","add_all__U39.in1"], - ["self.out","add_all__U39.out"], - ["mul_d0__U34.in0","coeff_0_U33.out"], - ["mul_d1__U36.in0","coeff_1_U35.out"], - ["self.d.0","mul_d0__U34.in1"], - ["self.d.1","mul_d1__U36.in1"] + ["mul_d0__U32.out","add_all__U36.in0"], + ["mul_d1__U34.out","add_all__U36.in1"], + ["add_all__U37.in0","add_all__U36.out"], + ["const_term_U35.out","add_all__U37.in1"], + ["self.out","add_all__U37.out"], + ["mul_d0__U32.in0","coeff_0_U31.out"], + ["mul_d1__U34.in0","coeff_1_U33.out"], + ["self.d.0","mul_d0__U32.in1"], + ["self.d.1","mul_d1__U34.in1"] ] }, - "aff__U47":{ + "aff__U44":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U53":{ + "add_all__U50":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U51":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U48":{ + "coeff_0_U45":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U50":{ + "coeff_1_U47":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U52":{ + "const_term_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U49":{ + "mul_d0__U46":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U51":{ + "mul_d1__U48":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U49.out","add_all__U53.in0"], - ["mul_d1__U51.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U52.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U49.in0","coeff_0_U48.out"], - ["mul_d1__U51.in0","coeff_1_U50.out"], - ["self.d.0","mul_d0__U49.in1"], - ["self.d.1","mul_d1__U51.in1"] + ["mul_d0__U46.out","add_all__U50.in0"], + ["mul_d1__U48.out","add_all__U50.in1"], + ["add_all__U51.in0","add_all__U50.out"], + ["const_term_U49.out","add_all__U51.in1"], + ["self.out","add_all__U51.out"], + ["mul_d0__U46.in0","coeff_0_U45.out"], + ["mul_d1__U48.in0","coeff_1_U47.out"], + ["self.d.0","mul_d0__U46.in1"], + ["self.d.1","mul_d1__U48.in1"] ] }, - "aff__U62":{ + "aff__U58":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U68":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U69":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U63":{ + "coeff_0_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U65":{ + "coeff_1_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U67":{ + "const_term_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U64":{ + "mul_d0__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U66":{ + "mul_d1__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U64.out","add_all__U68.in0"], - ["mul_d1__U66.out","add_all__U68.in1"], - ["add_all__U69.in0","add_all__U68.out"], - ["const_term_U67.out","add_all__U69.in1"], - ["self.out","add_all__U69.out"], - ["mul_d0__U64.in0","coeff_0_U63.out"], - ["mul_d1__U66.in0","coeff_1_U65.out"], - ["self.d.0","mul_d0__U64.in1"], - ["self.d.1","mul_d1__U66.in1"] + ["mul_d0__U60.out","add_all__U64.in0"], + ["mul_d1__U62.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["const_term_U63.out","add_all__U65.in1"], + ["self.out","add_all__U65.out"], + ["mul_d0__U60.in0","coeff_0_U59.out"], + ["mul_d1__U62.in0","coeff_1_U61.out"], + ["self.d.0","mul_d0__U60.in1"], + ["self.d.1","mul_d1__U62.in1"] ] }, - "aff__U77":{ + "aff__U72":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U83":{ + "add_all__U78":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U84":{ + "add_all__U79":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U78":{ + "coeff_0_U73":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U80":{ + "coeff_1_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U82":{ + "const_term_U77":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U79":{ + "mul_d0__U74":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U81":{ + "mul_d1__U76":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U79.out","add_all__U83.in0"], - ["mul_d1__U81.out","add_all__U83.in1"], - ["add_all__U84.in0","add_all__U83.out"], - ["const_term_U82.out","add_all__U84.in1"], - ["self.out","add_all__U84.out"], - ["mul_d0__U79.in0","coeff_0_U78.out"], - ["mul_d1__U81.in0","coeff_1_U80.out"], - ["self.d.0","mul_d0__U79.in1"], - ["self.d.1","mul_d1__U81.in1"] + ["mul_d0__U74.out","add_all__U78.in0"], + ["mul_d1__U76.out","add_all__U78.in1"], + ["add_all__U79.in0","add_all__U78.out"], + ["const_term_U77.out","add_all__U79.in1"], + ["self.out","add_all__U79.out"], + ["mul_d0__U74.in0","coeff_0_U73.out"], + ["mul_d1__U76.in0","coeff_1_U75.out"], + ["self.d.0","mul_d0__U74.in1"], + ["self.d.1","mul_d1__U76.in1"] ] }, - "aff__U92":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U98":{ + "add_all__U92":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U99":{ + "add_all__U93":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U93":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U95":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U97":{ + "const_term_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "mul_d0__U94":{ + "mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U96":{ + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U94.out","add_all__U98.in0"], - ["mul_d1__U96.out","add_all__U98.in1"], - ["add_all__U99.in0","add_all__U98.out"], - ["const_term_U97.out","add_all__U99.in1"], - ["self.out","add_all__U99.out"], - ["mul_d0__U94.in0","coeff_0_U93.out"], - ["mul_d1__U96.in0","coeff_1_U95.out"], - ["self.d.0","mul_d0__U94.in1"], - ["self.d.1","mul_d1__U96.in1"] + ["mul_d0__U88.out","add_all__U92.in0"], + ["mul_d1__U90.out","add_all__U92.in1"], + ["add_all__U93.in0","add_all__U92.out"], + ["const_term_U91.out","add_all__U93.in1"], + ["self.out","add_all__U93.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"] ] }, "affine_controller__U1":{ @@ -1698,7 +1698,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U106":{ + "affine_controller__U113":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1706,49 +1706,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U115":{ + "_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1151":{ + "_U1221":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U116":{ + "_U123":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U113":{ + "affine_func$add_all__U120":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U114":{ + "affine_func$add_all__U121":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U108":{ + "affine_func$coeff_0_U115":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U110":{ + "affine_func$coeff_1_U117":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U112":{ + "affine_func$const_term_U119":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d0__U109":{ + "affine_func$mul_d0__U116":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U111":{ + "affine_func$mul_d1__U118":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -1812,12 +1812,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U117$c0_lutcnst":{ + "d_0_am__U124$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U117$lut$lut":{ + "d_0_am__U124$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1936,18 +1936,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U115.out"], - ["d_1_inc.in1","_U1151.out"], - ["cmp_time.in1","_U116.out"], - ["affine_func$mul_d0__U109.out","affine_func$add_all__U113.in0"], - ["affine_func$mul_d1__U111.out","affine_func$add_all__U113.in1"], - ["affine_func$add_all__U114.in0","affine_func$add_all__U113.out"], - ["affine_func$const_term_U112.out","affine_func$add_all__U114.in1"], - ["time_diff.in0","affine_func$add_all__U114.out"], - ["affine_func$mul_d0__U109.in0","affine_func$coeff_0_U108.out"], - ["affine_func$mul_d1__U111.in0","affine_func$coeff_1_U110.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U109.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U111.in1"], + ["d_0_inc.in1","_U122.out"], + ["d_1_inc.in1","_U1221.out"], + ["cmp_time.in1","_U123.out"], + ["affine_func$mul_d0__U116.out","affine_func$add_all__U120.in0"], + ["affine_func$mul_d1__U118.out","affine_func$add_all__U120.in1"], + ["affine_func$add_all__U121.in0","affine_func$add_all__U120.out"], + ["affine_func$const_term_U119.out","affine_func$add_all__U121.in1"], + ["time_diff.in0","affine_func$add_all__U121.out"], + ["affine_func$mul_d0__U116.in0","affine_func$coeff_0_U115.out"], + ["affine_func$mul_d1__U118.in0","affine_func$coeff_1_U117.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U116.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U118.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -1970,10 +1970,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U117$lut$lut.bit.in.2","d_0_am__U117$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U117$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U117$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U117$lut$lut.bit.out"], + ["d_0_am__U124$lut$lut.bit.in.2","d_0_am__U124$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U124$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U124$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U124$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2009,57 +2009,93 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U121":{ + "affine_controller__U126":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U130":{ + "_U141":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1411":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1412":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1301":{ + "_U1413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U131":{ + "_U142":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U128":{ + "affine_func$add_all__U137":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U138":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U139":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U129":{ + "affine_func$add_all__U140":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U123":{ + "affine_func$coeff_0_U128":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U125":{ + "affine_func$coeff_1_U130":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "affine_func$const_term_U127":{ + "affine_func$coeff_2_U132":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00020000"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} + }, + "affine_func$coeff_3_U134":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U136":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U124":{ + "affine_func$mul_d0__U129":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U126":{ + "affine_func$mul_d1__U131":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U133":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U135":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2123,12 +2159,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U132$c0_lutcnst":{ + "d_0_am__U143$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U143$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U144$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U144$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U145$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U132$lut$lut":{ + "d_0_am__U145$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2177,6 +2233,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U146$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U146$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U147$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U147$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -2188,7 +2264,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2221,6 +2297,104 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_2_am__U148$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U148$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -2240,6 +2414,16 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2247,21 +2431,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U130.out"], - ["d_1_inc.in1","_U1301.out"], - ["cmp_time.in1","_U131.out"], - ["affine_func$mul_d0__U124.out","affine_func$add_all__U128.in0"], - ["affine_func$mul_d1__U126.out","affine_func$add_all__U128.in1"], - ["affine_func$add_all__U129.in0","affine_func$add_all__U128.out"], - ["affine_func$const_term_U127.out","affine_func$add_all__U129.in1"], - ["time_diff.in0","affine_func$add_all__U129.out"], - ["affine_func$mul_d0__U124.in0","affine_func$coeff_0_U123.out"], - ["affine_func$mul_d1__U126.in0","affine_func$coeff_1_U125.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U124.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U126.in1"], + ["d_0_inc.in1","_U141.out"], + ["d_1_inc.in1","_U1411.out"], + ["d_2_inc.in1","_U1412.out"], + ["d_3_inc.in1","_U1413.out"], + ["cmp_time.in1","_U142.out"], + ["affine_func$mul_d0__U129.out","affine_func$add_all__U137.in0"], + ["affine_func$mul_d1__U131.out","affine_func$add_all__U137.in1"], + ["affine_func$add_all__U138.in0","affine_func$add_all__U137.out"], + ["affine_func$mul_d2__U133.out","affine_func$add_all__U138.in1"], + ["affine_func$add_all__U139.in0","affine_func$add_all__U138.out"], + ["affine_func$mul_d3__U135.out","affine_func$add_all__U139.in1"], + ["affine_func$add_all__U140.in0","affine_func$add_all__U139.out"], + ["affine_func$const_term_U136.out","affine_func$add_all__U140.in1"], + ["time_diff.in0","affine_func$add_all__U140.out"], + ["affine_func$mul_d0__U129.in0","affine_func$coeff_0_U128.out"], + ["affine_func$mul_d1__U131.in0","affine_func$coeff_1_U130.out"], + ["affine_func$mul_d2__U133.in0","affine_func$coeff_2_U132.out"], + ["affine_func$mul_d3__U135.in0","affine_func$coeff_3_U134.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U129.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U131.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U133.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U135.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -2269,22 +2465,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U132$lut$lut.bit.in.2","d_0_am__U132$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U132$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U132$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U132$lut$lut.bit.out"], + ["d_0_am__U143$lut$lut.bit.in.2","d_0_am__U143$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U143$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U143$lut$lut.bit.in.1"], + ["d_0_am__U144$lut$lut.bit.in.0","d_0_am__U143$lut$lut.bit.out"], + ["d_0_am__U144$lut$lut.bit.in.2","d_0_am__U144$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U144$lut$lut.bit.in.1"], + ["d_0_am__U145$lut$lut.bit.in.0","d_0_am__U144$lut$lut.bit.out"], + ["d_0_am__U145$lut$lut.bit.in.2","d_0_am__U145$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U145$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U145$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2301,6 +2503,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U146$lut$lut.bit.in.2","d_1_am__U146$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U146$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U146$lut$lut.bit.in.1"], + ["d_1_am__U147$lut$lut.bit.in.0","d_1_am__U146$lut$lut.bit.out"], + ["d_1_am__U147$lut$lut.bit.in.2","d_1_am__U147$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U147$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U147$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2310,103 +2519,103 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U148$lut$lut.bit.in.2","d_2_am__U148$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U148$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U148$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U148$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U136":{ + "affine_controller__U15":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U151":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1511":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1512":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1513":{ + "_U241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U152":{ + "_U25":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U147":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U148":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U149":{ + "affine_func$add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U150":{ + "affine_func$add_all__U23":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U138":{ + "affine_func$coeff_0_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U140":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} - }, - "affine_func$coeff_2_U142":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "affine_func$coeff_3_U144":{ + "affine_func$coeff_1_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U146":{ + "affine_func$const_term_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$mul_d0__U139":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U141":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d2__U143":{ + "affine_func$mul_d0__U18":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U145":{ + "affine_func$mul_d1__U20":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2470,32 +2679,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U153$c0_lutcnst":{ + "d_0_am__U26$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U153$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U154$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U154$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U155$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U155$lut$lut":{ + "d_0_am__U26$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2544,26 +2733,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U156$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U156$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U157$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U157$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -2575,7 +2744,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2608,104 +2777,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U158$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U158$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -2725,16 +2796,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2742,33 +2803,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U151.out"], - ["d_1_inc.in1","_U1511.out"], - ["d_2_inc.in1","_U1512.out"], - ["d_3_inc.in1","_U1513.out"], - ["cmp_time.in1","_U152.out"], - ["affine_func$mul_d0__U139.out","affine_func$add_all__U147.in0"], - ["affine_func$mul_d1__U141.out","affine_func$add_all__U147.in1"], - ["affine_func$add_all__U148.in0","affine_func$add_all__U147.out"], - ["affine_func$mul_d2__U143.out","affine_func$add_all__U148.in1"], - ["affine_func$add_all__U149.in0","affine_func$add_all__U148.out"], - ["affine_func$mul_d3__U145.out","affine_func$add_all__U149.in1"], - ["affine_func$add_all__U150.in0","affine_func$add_all__U149.out"], - ["affine_func$const_term_U146.out","affine_func$add_all__U150.in1"], - ["time_diff.in0","affine_func$add_all__U150.out"], - ["affine_func$mul_d0__U139.in0","affine_func$coeff_0_U138.out"], - ["affine_func$mul_d1__U141.in0","affine_func$coeff_1_U140.out"], - ["affine_func$mul_d2__U143.in0","affine_func$coeff_2_U142.out"], - ["affine_func$mul_d3__U145.in0","affine_func$coeff_3_U144.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U139.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U141.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U143.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U145.in1"], + ["d_0_inc.in1","_U24.out"], + ["d_1_inc.in1","_U241.out"], + ["cmp_time.in1","_U25.out"], + ["affine_func$mul_d0__U18.out","affine_func$add_all__U22.in0"], + ["affine_func$mul_d1__U20.out","affine_func$add_all__U22.in1"], + ["affine_func$add_all__U23.in0","affine_func$add_all__U22.out"], + ["affine_func$const_term_U21.out","affine_func$add_all__U23.in1"], + ["time_diff.in0","affine_func$add_all__U23.out"], + ["affine_func$mul_d0__U18.in0","affine_func$coeff_0_U17.out"], + ["affine_func$mul_d1__U20.in0","affine_func$coeff_1_U19.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U18.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U20.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -2776,28 +2825,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U153$lut$lut.bit.in.2","d_0_am__U153$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U153$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U153$lut$lut.bit.in.1"], - ["d_0_am__U154$lut$lut.bit.in.0","d_0_am__U153$lut$lut.bit.out"], - ["d_0_am__U154$lut$lut.bit.in.2","d_0_am__U154$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U154$lut$lut.bit.in.1"], - ["d_0_am__U155$lut$lut.bit.in.0","d_0_am__U154$lut$lut.bit.out"], - ["d_0_am__U155$lut$lut.bit.in.2","d_0_am__U155$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U155$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U155$lut$lut.bit.out"], + ["d_0_am__U26$lut$lut.bit.in.2","d_0_am__U26$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U26$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U26$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U26$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2814,13 +2857,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U156$lut$lut.bit.in.2","d_1_am__U156$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U156$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U156$lut$lut.bit.in.1"], - ["d_1_am__U157$lut$lut.bit.in.0","d_1_am__U156$lut$lut.bit.out"], - ["d_1_am__U157$lut$lut.bit.in.2","d_1_am__U157$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U157$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U157$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2830,103 +2866,103 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U158$lut$lut.bit.in.2","d_2_am__U158$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U158$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U158$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U158$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U16":{ + "affine_controller__U165":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U25":{ + "_U180":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1801":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1802":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U251":{ + "_U1803":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U26":{ + "_U181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U23":{ + "affine_func$add_all__U176":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U177":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U178":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U24":{ + "affine_func$add_all__U179":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U18":{ + "affine_func$coeff_0_U167":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U20":{ + "affine_func$coeff_1_U169":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "affine_func$const_term_U22":{ + "affine_func$coeff_2_U171":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00020000"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$mul_d0__U19":{ + "affine_func$coeff_3_U173":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U175":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0001ffff"]} + }, + "affine_func$mul_d0__U168":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U170":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U172":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U21":{ + "affine_func$mul_d3__U174":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2990,12 +3026,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U27$c0_lutcnst":{ + "d_0_am__U182$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U27$lut$lut":{ + "d_0_am__U182$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U183$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U183$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U184$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U184$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3044,6 +3100,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U185$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U185$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U186$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U186$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -3055,7 +3131,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -3088,6 +3164,104 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_2_am__U187$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U187$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -3107,6 +3281,16 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -3114,21 +3298,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U25.out"], - ["d_1_inc.in1","_U251.out"], - ["cmp_time.in1","_U26.out"], - ["affine_func$mul_d0__U19.out","affine_func$add_all__U23.in0"], - ["affine_func$mul_d1__U21.out","affine_func$add_all__U23.in1"], - ["affine_func$add_all__U24.in0","affine_func$add_all__U23.out"], - ["affine_func$const_term_U22.out","affine_func$add_all__U24.in1"], - ["time_diff.in0","affine_func$add_all__U24.out"], - ["affine_func$mul_d0__U19.in0","affine_func$coeff_0_U18.out"], - ["affine_func$mul_d1__U21.in0","affine_func$coeff_1_U20.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U19.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U21.in1"], + ["d_0_inc.in1","_U180.out"], + ["d_1_inc.in1","_U1801.out"], + ["d_2_inc.in1","_U1802.out"], + ["d_3_inc.in1","_U1803.out"], + ["cmp_time.in1","_U181.out"], + ["affine_func$mul_d0__U168.out","affine_func$add_all__U176.in0"], + ["affine_func$mul_d1__U170.out","affine_func$add_all__U176.in1"], + ["affine_func$add_all__U177.in0","affine_func$add_all__U176.out"], + ["affine_func$mul_d2__U172.out","affine_func$add_all__U177.in1"], + ["affine_func$add_all__U178.in0","affine_func$add_all__U177.out"], + ["affine_func$mul_d3__U174.out","affine_func$add_all__U178.in1"], + ["affine_func$add_all__U179.in0","affine_func$add_all__U178.out"], + ["affine_func$const_term_U175.out","affine_func$add_all__U179.in1"], + ["time_diff.in0","affine_func$add_all__U179.out"], + ["affine_func$mul_d0__U168.in0","affine_func$coeff_0_U167.out"], + ["affine_func$mul_d1__U170.in0","affine_func$coeff_1_U169.out"], + ["affine_func$mul_d2__U172.in0","affine_func$coeff_2_U171.out"], + ["affine_func$mul_d3__U174.in0","affine_func$coeff_3_U173.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U168.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U170.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U172.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U174.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -3136,22 +3332,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U27$lut$lut.bit.in.2","d_0_am__U27$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U27$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U27$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U27$lut$lut.bit.out"], + ["d_0_am__U182$lut$lut.bit.in.2","d_0_am__U182$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U182$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U182$lut$lut.bit.in.1"], + ["d_0_am__U183$lut$lut.bit.in.0","d_0_am__U182$lut$lut.bit.out"], + ["d_0_am__U183$lut$lut.bit.in.2","d_0_am__U183$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U183$lut$lut.bit.in.1"], + ["d_0_am__U184$lut$lut.bit.in.0","d_0_am__U183$lut$lut.bit.out"], + ["d_0_am__U184$lut$lut.bit.in.2","d_0_am__U184$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U184$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U184$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3168,6 +3370,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U185$lut$lut.bit.in.2","d_1_am__U185$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U185$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U185$lut$lut.bit.in.1"], + ["d_1_am__U186$lut$lut.bit.in.0","d_1_am__U185$lut$lut.bit.out"], + ["d_1_am__U186$lut$lut.bit.in.2","d_1_am__U186$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U186$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U186$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3177,17 +3386,53 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U187$lut$lut.bit.in.2","d_2_am__U187$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U187$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U187$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U187$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U175":{ + "affine_controller__U205":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3195,85 +3440,85 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U190":{ + "_U220":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1901":{ + "_U2201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1902":{ + "_U2202":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1903":{ + "_U2203":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U191":{ + "_U221":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U186":{ + "affine_func$add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U187":{ + "affine_func$add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U188":{ + "affine_func$add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U189":{ + "affine_func$add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U177":{ + "affine_func$coeff_0_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U179":{ + "affine_func$coeff_1_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "affine_func$coeff_2_U181":{ + "affine_func$coeff_2_U211":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "affine_func$coeff_3_U183":{ + "affine_func$coeff_3_U213":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U185":{ + "affine_func$const_term_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0001ffff"]} + "modargs":{"value":[["BitVector",32],"32'h00022400"]} }, - "affine_func$mul_d0__U178":{ + "affine_func$mul_d0__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U180":{ + "affine_func$mul_d1__U210":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U182":{ + "affine_func$mul_d2__U212":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U184":{ + "affine_func$mul_d3__U214":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -3337,32 +3582,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U192$c0_lutcnst":{ + "d_0_am__U222$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U192$lut$lut":{ + "d_0_am__U222$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U193$c0_lutcnst":{ + "d_0_am__U223$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U193$lut$lut":{ + "d_0_am__U223$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U194$c0_lutcnst":{ + "d_0_am__U224$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U194$lut$lut":{ + "d_0_am__U224$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3411,22 +3656,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U195$c0_lutcnst":{ + "d_1_am__U225$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U195$lut$lut":{ + "d_1_am__U225$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U196$c0_lutcnst":{ + "d_1_am__U226$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U196$lut$lut":{ + "d_1_am__U226$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3442,7 +3687,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -3475,12 +3720,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U197$c0_lutcnst":{ + "d_2_am__U227$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U197$lut$lut":{ + "d_2_am__U227$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3496,7 +3741,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, "d_2_min":{ "genref":"coreir.const", @@ -3540,7 +3785,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -3609,28 +3854,28 @@ } }, "connections":[ - ["d_0_inc.in1","_U190.out"], - ["d_1_inc.in1","_U1901.out"], - ["d_2_inc.in1","_U1902.out"], - ["d_3_inc.in1","_U1903.out"], - ["cmp_time.in1","_U191.out"], - ["affine_func$mul_d0__U178.out","affine_func$add_all__U186.in0"], - ["affine_func$mul_d1__U180.out","affine_func$add_all__U186.in1"], - ["affine_func$add_all__U187.in0","affine_func$add_all__U186.out"], - ["affine_func$mul_d2__U182.out","affine_func$add_all__U187.in1"], - ["affine_func$add_all__U188.in0","affine_func$add_all__U187.out"], - ["affine_func$mul_d3__U184.out","affine_func$add_all__U188.in1"], - ["affine_func$add_all__U189.in0","affine_func$add_all__U188.out"], - ["affine_func$const_term_U185.out","affine_func$add_all__U189.in1"], - ["time_diff.in0","affine_func$add_all__U189.out"], - ["affine_func$mul_d0__U178.in0","affine_func$coeff_0_U177.out"], - ["affine_func$mul_d1__U180.in0","affine_func$coeff_1_U179.out"], - ["affine_func$mul_d2__U182.in0","affine_func$coeff_2_U181.out"], - ["affine_func$mul_d3__U184.in0","affine_func$coeff_3_U183.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U178.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U180.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U182.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U184.in1"], + ["d_0_inc.in1","_U220.out"], + ["d_1_inc.in1","_U2201.out"], + ["d_2_inc.in1","_U2202.out"], + ["d_3_inc.in1","_U2203.out"], + ["cmp_time.in1","_U221.out"], + ["affine_func$mul_d0__U208.out","affine_func$add_all__U216.in0"], + ["affine_func$mul_d1__U210.out","affine_func$add_all__U216.in1"], + ["affine_func$add_all__U217.in0","affine_func$add_all__U216.out"], + ["affine_func$mul_d2__U212.out","affine_func$add_all__U217.in1"], + ["affine_func$add_all__U218.in0","affine_func$add_all__U217.out"], + ["affine_func$mul_d3__U214.out","affine_func$add_all__U218.in1"], + ["affine_func$add_all__U219.in0","affine_func$add_all__U218.out"], + ["affine_func$const_term_U215.out","affine_func$add_all__U219.in1"], + ["time_diff.in0","affine_func$add_all__U219.out"], + ["affine_func$mul_d0__U208.in0","affine_func$coeff_0_U207.out"], + ["affine_func$mul_d1__U210.in0","affine_func$coeff_1_U209.out"], + ["affine_func$mul_d2__U212.in0","affine_func$coeff_2_U211.out"], + ["affine_func$mul_d3__U214.in0","affine_func$coeff_3_U213.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U208.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U210.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U212.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U214.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -3655,16 +3900,16 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U192$lut$lut.bit.in.2","d_0_am__U192$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U192$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U192$lut$lut.bit.in.1"], - ["d_0_am__U193$lut$lut.bit.in.0","d_0_am__U192$lut$lut.bit.out"], - ["d_0_am__U193$lut$lut.bit.in.2","d_0_am__U193$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U193$lut$lut.bit.in.1"], - ["d_0_am__U194$lut$lut.bit.in.0","d_0_am__U193$lut$lut.bit.out"], - ["d_0_am__U194$lut$lut.bit.in.2","d_0_am__U194$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U194$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U194$lut$lut.bit.out"], + ["d_0_am__U222$lut$lut.bit.in.2","d_0_am__U222$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U222$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U222$lut$lut.bit.in.1"], + ["d_0_am__U223$lut$lut.bit.in.0","d_0_am__U222$lut$lut.bit.out"], + ["d_0_am__U223$lut$lut.bit.in.2","d_0_am__U223$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U223$lut$lut.bit.in.1"], + ["d_0_am__U224$lut$lut.bit.in.0","d_0_am__U223$lut$lut.bit.out"], + ["d_0_am__U224$lut$lut.bit.in.2","d_0_am__U224$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U224$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U224$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3681,13 +3926,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U195$lut$lut.bit.in.2","d_1_am__U195$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U195$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U195$lut$lut.bit.in.1"], - ["d_1_am__U196$lut$lut.bit.in.0","d_1_am__U195$lut$lut.bit.out"], - ["d_1_am__U196$lut$lut.bit.in.2","d_1_am__U196$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U196$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U196$lut$lut.bit.out"], + ["d_1_am__U225$lut$lut.bit.in.2","d_1_am__U225$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U225$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U225$lut$lut.bit.in.1"], + ["d_1_am__U226$lut$lut.bit.in.0","d_1_am__U225$lut$lut.bit.out"], + ["d_1_am__U226$lut$lut.bit.in.2","d_1_am__U226$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U226$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U226$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3704,10 +3949,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U197$lut$lut.bit.in.2","d_2_am__U197$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U197$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U197$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U197$lut$lut.bit.out"], + ["d_2_am__U227$lut$lut.bit.in.2","d_2_am__U227$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U227$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U227$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U227$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3743,93 +3988,75 @@ ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U216":{ + "affine_controller__U244":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",3,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U231":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U2311":{ + "_U256":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2312":{ + "_U2561":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2313":{ + "_U2562":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U232":{ + "_U257":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U227":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U228":{ + "affine_func$add_all__U253":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U229":{ + "affine_func$add_all__U254":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U230":{ + "affine_func$add_all__U255":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U218":{ + "affine_func$coeff_0_U246":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U220":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00002000"]} - }, - "affine_func$coeff_2_U222":{ + "affine_func$coeff_1_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "affine_func$coeff_3_U224":{ + "affine_func$coeff_2_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U226":{ + "affine_func$const_term_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00022400"]} - }, - "affine_func$mul_d0__U219":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h000407ff"]} }, - "affine_func$mul_d1__U221":{ + "affine_func$mul_d0__U247":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U223":{ + "affine_func$mul_d1__U249":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U225":{ + "affine_func$mul_d2__U251":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -3893,32 +4120,22 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U233$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U233$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U234$c0_lutcnst":{ + "d_0_am__U258$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U234$lut$lut":{ + "d_0_am__U258$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U235$c0_lutcnst":{ + "d_0_am__U259$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U235$lut$lut":{ + "d_0_am__U259$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3967,22 +4184,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U236$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U236$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U237$c0_lutcnst":{ + "d_1_am__U260$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U237$lut$lut":{ + "d_1_am__U260$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3998,7 +4205,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -4031,16 +4238,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U238$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U238$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -4052,7 +4249,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, "d_2_min":{ "genref":"coreir.const", @@ -4085,50 +4282,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -4153,11 +4306,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4165,33 +4313,27 @@ } }, "connections":[ - ["d_0_inc.in1","_U231.out"], - ["d_1_inc.in1","_U2311.out"], - ["d_2_inc.in1","_U2312.out"], - ["d_3_inc.in1","_U2313.out"], - ["cmp_time.in1","_U232.out"], - ["affine_func$mul_d0__U219.out","affine_func$add_all__U227.in0"], - ["affine_func$mul_d1__U221.out","affine_func$add_all__U227.in1"], - ["affine_func$add_all__U228.in0","affine_func$add_all__U227.out"], - ["affine_func$mul_d2__U223.out","affine_func$add_all__U228.in1"], - ["affine_func$add_all__U229.in0","affine_func$add_all__U228.out"], - ["affine_func$mul_d3__U225.out","affine_func$add_all__U229.in1"], - ["affine_func$add_all__U230.in0","affine_func$add_all__U229.out"], - ["affine_func$const_term_U226.out","affine_func$add_all__U230.in1"], - ["time_diff.in0","affine_func$add_all__U230.out"], - ["affine_func$mul_d0__U219.in0","affine_func$coeff_0_U218.out"], - ["affine_func$mul_d1__U221.in0","affine_func$coeff_1_U220.out"], - ["affine_func$mul_d2__U223.in0","affine_func$coeff_2_U222.out"], - ["affine_func$mul_d3__U225.in0","affine_func$coeff_3_U224.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U219.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U221.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U223.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U225.in1"], + ["d_0_inc.in1","_U256.out"], + ["d_1_inc.in1","_U2561.out"], + ["d_2_inc.in1","_U2562.out"], + ["cmp_time.in1","_U257.out"], + ["affine_func$mul_d0__U247.out","affine_func$add_all__U253.in0"], + ["affine_func$mul_d1__U249.out","affine_func$add_all__U253.in1"], + ["affine_func$add_all__U254.in0","affine_func$add_all__U253.out"], + ["affine_func$mul_d2__U251.out","affine_func$add_all__U254.in1"], + ["affine_func$add_all__U255.in0","affine_func$add_all__U254.out"], + ["affine_func$const_term_U252.out","affine_func$add_all__U255.in1"], + ["time_diff.in0","affine_func$add_all__U255.out"], + ["affine_func$mul_d0__U247.in0","affine_func$coeff_0_U246.out"], + ["affine_func$mul_d1__U249.in0","affine_func$coeff_1_U248.out"], + ["affine_func$mul_d2__U251.in0","affine_func$coeff_2_U250.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U247.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U249.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U251.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -4199,28 +4341,25 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true4_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U233$lut$lut.bit.in.2","d_0_am__U233$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U233$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U233$lut$lut.bit.in.1"], - ["d_0_am__U234$lut$lut.bit.in.0","d_0_am__U233$lut$lut.bit.out"], - ["d_0_am__U234$lut$lut.bit.in.2","d_0_am__U234$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U234$lut$lut.bit.in.1"], - ["d_0_am__U235$lut$lut.bit.in.0","d_0_am__U234$lut$lut.bit.out"], - ["d_0_am__U235$lut$lut.bit.in.2","d_0_am__U235$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U235$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U235$lut$lut.bit.out"], + ["d_0_am__U258$lut$lut.bit.in.2","d_0_am__U258$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U258$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U258$lut$lut.bit.in.1"], + ["d_0_am__U259$lut$lut.bit.in.0","d_0_am__U258$lut$lut.bit.out"], + ["d_0_am__U259$lut$lut.bit.in.2","d_0_am__U259$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U259$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U259$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4237,13 +4376,10 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U236$lut$lut.bit.in.2","d_1_am__U236$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U236$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U236$lut$lut.bit.in.1"], - ["d_1_am__U237$lut$lut.bit.in.0","d_1_am__U236$lut$lut.bit.out"], - ["d_1_am__U237$lut$lut.bit.in.2","d_1_am__U237$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U237$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U237$lut$lut.bit.out"], + ["d_1_am__U260$lut$lut.bit.in.2","d_1_am__U260$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U260$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U260$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U260$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4260,10 +4396,6 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U238$lut$lut.bit.in.2","d_2_am__U238$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U238$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U238$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U238$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4273,33 +4405,17 @@ ["d_2_reg$reg0.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["true_lutcnst.bit.out","d_2_next_value.sel"], ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], ["self.rst_n","d_2_reg$clrMux.sel"], ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.2","d_2_reg$reg0.out"] ] }, - "affine_controller__U255":{ + "affine_controller__U275":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4307,67 +4423,67 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U267":{ + "_U287":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2671":{ + "_U2871":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2672":{ + "_U2872":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U268":{ + "_U288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U264":{ + "affine_func$add_all__U284":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U265":{ + "affine_func$add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U266":{ + "affine_func$add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U257":{ + "affine_func$coeff_0_U277":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U259":{ + "affine_func$coeff_1_U279":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "affine_func$coeff_2_U261":{ + "affine_func$coeff_2_U281":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U263":{ + "affine_func$const_term_U283":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000407ff"]} + "modargs":{"value":[["BitVector",32],"32'h00040800"]} }, - "affine_func$mul_d0__U258":{ + "affine_func$mul_d0__U278":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U260":{ + "affine_func$mul_d1__U280":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U262":{ + "affine_func$mul_d2__U282":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4431,22 +4547,22 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U269$c0_lutcnst":{ + "d_0_am__U289$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U269$lut$lut":{ + "d_0_am__U289$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U270$c0_lutcnst":{ + "d_0_am__U290$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U270$lut$lut":{ + "d_0_am__U290$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4495,12 +4611,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U271$c0_lutcnst":{ + "d_1_am__U291$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U271$lut$lut":{ + "d_1_am__U291$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4624,23 +4740,23 @@ } }, "connections":[ - ["d_0_inc.in1","_U267.out"], - ["d_1_inc.in1","_U2671.out"], - ["d_2_inc.in1","_U2672.out"], - ["cmp_time.in1","_U268.out"], - ["affine_func$mul_d0__U258.out","affine_func$add_all__U264.in0"], - ["affine_func$mul_d1__U260.out","affine_func$add_all__U264.in1"], - ["affine_func$add_all__U265.in0","affine_func$add_all__U264.out"], - ["affine_func$mul_d2__U262.out","affine_func$add_all__U265.in1"], - ["affine_func$add_all__U266.in0","affine_func$add_all__U265.out"], - ["affine_func$const_term_U263.out","affine_func$add_all__U266.in1"], - ["time_diff.in0","affine_func$add_all__U266.out"], - ["affine_func$mul_d0__U258.in0","affine_func$coeff_0_U257.out"], - ["affine_func$mul_d1__U260.in0","affine_func$coeff_1_U259.out"], - ["affine_func$mul_d2__U262.in0","affine_func$coeff_2_U261.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U258.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U260.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U262.in1"], + ["d_0_inc.in1","_U287.out"], + ["d_1_inc.in1","_U2871.out"], + ["d_2_inc.in1","_U2872.out"], + ["cmp_time.in1","_U288.out"], + ["affine_func$mul_d0__U278.out","affine_func$add_all__U284.in0"], + ["affine_func$mul_d1__U280.out","affine_func$add_all__U284.in1"], + ["affine_func$add_all__U285.in0","affine_func$add_all__U284.out"], + ["affine_func$mul_d2__U282.out","affine_func$add_all__U285.in1"], + ["affine_func$add_all__U286.in0","affine_func$add_all__U285.out"], + ["affine_func$const_term_U283.out","affine_func$add_all__U286.in1"], + ["time_diff.in0","affine_func$add_all__U286.out"], + ["affine_func$mul_d0__U278.in0","affine_func$coeff_0_U277.out"], + ["affine_func$mul_d1__U280.in0","affine_func$coeff_1_U279.out"], + ["affine_func$mul_d2__U282.in0","affine_func$coeff_2_U281.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U278.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U280.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U282.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -4664,13 +4780,13 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U269$lut$lut.bit.in.2","d_0_am__U269$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U269$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U269$lut$lut.bit.in.1"], - ["d_0_am__U270$lut$lut.bit.in.0","d_0_am__U269$lut$lut.bit.out"], - ["d_0_am__U270$lut$lut.bit.in.2","d_0_am__U270$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U270$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U270$lut$lut.bit.out"], + ["d_0_am__U289$lut$lut.bit.in.2","d_0_am__U289$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U289$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U289$lut$lut.bit.in.1"], + ["d_0_am__U290$lut$lut.bit.in.0","d_0_am__U289$lut$lut.bit.out"], + ["d_0_am__U290$lut$lut.bit.in.2","d_0_am__U290$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U290$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U290$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4687,10 +4803,10 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U271$lut$lut.bit.in.2","d_1_am__U271$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U271$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U271$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U271$lut$lut.bit.out"], + ["d_1_am__U291$lut$lut.bit.in.2","d_1_am__U291$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U291$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U291$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U291$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4726,75 +4842,57 @@ ["self.d.2","d_2_reg$reg0.out"] ] }, - "affine_controller__U286":{ + "affine_controller__U29":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",3,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U298":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U2981":{ + "_U38":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2982":{ + "_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U299":{ + "_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U295":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U296":{ + "affine_func$add_all__U36":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U297":{ + "affine_func$add_all__U37":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U288":{ + "affine_func$coeff_0_U31":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U290":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "affine_func$coeff_2_U292":{ + "affine_func$coeff_1_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U294":{ + "affine_func$const_term_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00040800"]} - }, - "affine_func$mul_d0__U289":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d1__U291":{ + "affine_func$mul_d0__U32":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U293":{ + "affine_func$mul_d1__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4858,22 +4956,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U300$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U300$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U301$c0_lutcnst":{ + "d_0_am__U40$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U301$lut$lut":{ + "d_0_am__U40$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4922,16 +5010,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U302$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U302$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -4943,7 +5021,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -4976,50 +5054,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -5039,11 +5073,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -5051,27 +5080,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U298.out"], - ["d_1_inc.in1","_U2981.out"], - ["d_2_inc.in1","_U2982.out"], - ["cmp_time.in1","_U299.out"], - ["affine_func$mul_d0__U289.out","affine_func$add_all__U295.in0"], - ["affine_func$mul_d1__U291.out","affine_func$add_all__U295.in1"], - ["affine_func$add_all__U296.in0","affine_func$add_all__U295.out"], - ["affine_func$mul_d2__U293.out","affine_func$add_all__U296.in1"], - ["affine_func$add_all__U297.in0","affine_func$add_all__U296.out"], - ["affine_func$const_term_U294.out","affine_func$add_all__U297.in1"], - ["time_diff.in0","affine_func$add_all__U297.out"], - ["affine_func$mul_d0__U289.in0","affine_func$coeff_0_U288.out"], - ["affine_func$mul_d1__U291.in0","affine_func$coeff_1_U290.out"], - ["affine_func$mul_d2__U293.in0","affine_func$coeff_2_U292.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U289.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U291.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U293.in1"], + ["d_0_inc.in1","_U38.out"], + ["d_1_inc.in1","_U381.out"], + ["cmp_time.in1","_U39.out"], + ["affine_func$mul_d0__U32.out","affine_func$add_all__U36.in0"], + ["affine_func$mul_d1__U34.out","affine_func$add_all__U36.in1"], + ["affine_func$add_all__U37.in0","affine_func$add_all__U36.out"], + ["affine_func$const_term_U35.out","affine_func$add_all__U37.in1"], + ["time_diff.in0","affine_func$add_all__U37.out"], + ["affine_func$mul_d0__U32.in0","affine_func$coeff_0_U31.out"], + ["affine_func$mul_d1__U34.in0","affine_func$coeff_1_U33.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U32.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U34.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -5079,25 +5102,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true4_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U300$lut$lut.bit.in.2","d_0_am__U300$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U300$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U300$lut$lut.bit.in.1"], - ["d_0_am__U301$lut$lut.bit.in.0","d_0_am__U300$lut$lut.bit.out"], - ["d_0_am__U301$lut$lut.bit.in.2","d_0_am__U301$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U301$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U301$lut$lut.bit.out"], + ["d_0_am__U40$lut$lut.bit.in.2","d_0_am__U40$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U40$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U40$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U40$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5114,10 +5134,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U302$lut$lut.bit.in.2","d_1_am__U302$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U302$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U302$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U302$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5127,33 +5143,17 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["true_lutcnst.bit.out","d_2_next_value.sel"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U31":{ + "affine_controller__U43":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5161,49 +5161,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U40":{ + "_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U401":{ + "_U521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U41":{ + "_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U38":{ + "affine_func$add_all__U50":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U39":{ + "affine_func$add_all__U51":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U33":{ + "affine_func$coeff_0_U45":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U35":{ + "affine_func$coeff_1_U47":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U37":{ + "affine_func$const_term_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d0__U34":{ + "affine_func$mul_d0__U46":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U36":{ + "affine_func$mul_d1__U48":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5267,12 +5267,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U42$c0_lutcnst":{ + "d_0_am__U54$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U42$lut$lut":{ + "d_0_am__U54$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5391,18 +5391,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U40.out"], - ["d_1_inc.in1","_U401.out"], - ["cmp_time.in1","_U41.out"], - ["affine_func$mul_d0__U34.out","affine_func$add_all__U38.in0"], - ["affine_func$mul_d1__U36.out","affine_func$add_all__U38.in1"], - ["affine_func$add_all__U39.in0","affine_func$add_all__U38.out"], - ["affine_func$const_term_U37.out","affine_func$add_all__U39.in1"], - ["time_diff.in0","affine_func$add_all__U39.out"], - ["affine_func$mul_d0__U34.in0","affine_func$coeff_0_U33.out"], - ["affine_func$mul_d1__U36.in0","affine_func$coeff_1_U35.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U34.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U36.in1"], + ["d_0_inc.in1","_U52.out"], + ["d_1_inc.in1","_U521.out"], + ["cmp_time.in1","_U53.out"], + ["affine_func$mul_d0__U46.out","affine_func$add_all__U50.in0"], + ["affine_func$mul_d1__U48.out","affine_func$add_all__U50.in1"], + ["affine_func$add_all__U51.in0","affine_func$add_all__U50.out"], + ["affine_func$const_term_U49.out","affine_func$add_all__U51.in1"], + ["time_diff.in0","affine_func$add_all__U51.out"], + ["affine_func$mul_d0__U46.in0","affine_func$coeff_0_U45.out"], + ["affine_func$mul_d1__U48.in0","affine_func$coeff_1_U47.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U46.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U48.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5425,10 +5425,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U42$lut$lut.bit.in.2","d_0_am__U42$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U42$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U42$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U42$lut$lut.bit.out"], + ["d_0_am__U54$lut$lut.bit.in.2","d_0_am__U54$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U54$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U54$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U54$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5464,7 +5464,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U46":{ + "affine_controller__U57":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5472,49 +5472,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U55":{ + "_U66":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U551":{ + "_U661":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U56":{ + "_U67":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U53":{ + "affine_func$add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U54":{ + "affine_func$add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U48":{ + "affine_func$coeff_0_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U50":{ + "affine_func$coeff_1_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U52":{ + "affine_func$const_term_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d0__U49":{ + "affine_func$mul_d0__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U51":{ + "affine_func$mul_d1__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5578,12 +5578,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U57$c0_lutcnst":{ + "d_0_am__U68$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U57$lut$lut":{ + "d_0_am__U68$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5702,18 +5702,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U55.out"], - ["d_1_inc.in1","_U551.out"], - ["cmp_time.in1","_U56.out"], - ["affine_func$mul_d0__U49.out","affine_func$add_all__U53.in0"], - ["affine_func$mul_d1__U51.out","affine_func$add_all__U53.in1"], - ["affine_func$add_all__U54.in0","affine_func$add_all__U53.out"], - ["affine_func$const_term_U52.out","affine_func$add_all__U54.in1"], - ["time_diff.in0","affine_func$add_all__U54.out"], - ["affine_func$mul_d0__U49.in0","affine_func$coeff_0_U48.out"], - ["affine_func$mul_d1__U51.in0","affine_func$coeff_1_U50.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U49.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U51.in1"], + ["d_0_inc.in1","_U66.out"], + ["d_1_inc.in1","_U661.out"], + ["cmp_time.in1","_U67.out"], + ["affine_func$mul_d0__U60.out","affine_func$add_all__U64.in0"], + ["affine_func$mul_d1__U62.out","affine_func$add_all__U64.in1"], + ["affine_func$add_all__U65.in0","affine_func$add_all__U64.out"], + ["affine_func$const_term_U63.out","affine_func$add_all__U65.in1"], + ["time_diff.in0","affine_func$add_all__U65.out"], + ["affine_func$mul_d0__U60.in0","affine_func$coeff_0_U59.out"], + ["affine_func$mul_d1__U62.in0","affine_func$coeff_1_U61.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U60.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U62.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5736,10 +5736,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U57$lut$lut.bit.in.2","d_0_am__U57$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U57$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U57$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U57$lut$lut.bit.out"], + ["d_0_am__U68$lut$lut.bit.in.2","d_0_am__U68$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U68$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U68$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U68$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5775,7 +5775,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U61":{ + "affine_controller__U71":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5783,49 +5783,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U70":{ + "_U80":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U701":{ + "_U801":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U71":{ + "_U81":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U68":{ + "affine_func$add_all__U78":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U69":{ + "affine_func$add_all__U79":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U63":{ + "affine_func$coeff_0_U73":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U65":{ + "affine_func$coeff_1_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U67":{ + "affine_func$const_term_U77":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d0__U64":{ + "affine_func$mul_d0__U74":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U66":{ + "affine_func$mul_d1__U76":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5889,12 +5889,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U72$c0_lutcnst":{ + "d_0_am__U82$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U72$lut$lut":{ + "d_0_am__U82$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6013,18 +6013,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U70.out"], - ["d_1_inc.in1","_U701.out"], - ["cmp_time.in1","_U71.out"], - ["affine_func$mul_d0__U64.out","affine_func$add_all__U68.in0"], - ["affine_func$mul_d1__U66.out","affine_func$add_all__U68.in1"], - ["affine_func$add_all__U69.in0","affine_func$add_all__U68.out"], - ["affine_func$const_term_U67.out","affine_func$add_all__U69.in1"], - ["time_diff.in0","affine_func$add_all__U69.out"], - ["affine_func$mul_d0__U64.in0","affine_func$coeff_0_U63.out"], - ["affine_func$mul_d1__U66.in0","affine_func$coeff_1_U65.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U64.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U66.in1"], + ["d_0_inc.in1","_U80.out"], + ["d_1_inc.in1","_U801.out"], + ["cmp_time.in1","_U81.out"], + ["affine_func$mul_d0__U74.out","affine_func$add_all__U78.in0"], + ["affine_func$mul_d1__U76.out","affine_func$add_all__U78.in1"], + ["affine_func$add_all__U79.in0","affine_func$add_all__U78.out"], + ["affine_func$const_term_U77.out","affine_func$add_all__U79.in1"], + ["time_diff.in0","affine_func$add_all__U79.out"], + ["affine_func$mul_d0__U74.in0","affine_func$coeff_0_U73.out"], + ["affine_func$mul_d1__U76.in0","affine_func$coeff_1_U75.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U74.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U76.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6047,10 +6047,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U72$lut$lut.bit.in.2","d_0_am__U72$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U72$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U72$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U72$lut$lut.bit.out"], + ["d_0_am__U82$lut$lut.bit.in.2","d_0_am__U82$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U82$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U82$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U82$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6086,7 +6086,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U76":{ + "affine_controller__U85":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6094,49 +6094,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U85":{ + "_U94":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U851":{ + "_U941":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U86":{ + "_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U83":{ + "affine_func$add_all__U92":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U84":{ + "affine_func$add_all__U93":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U78":{ + "affine_func$coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U80":{ + "affine_func$coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U82":{ + "affine_func$const_term_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d0__U79":{ + "affine_func$mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U81":{ + "affine_func$mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6200,12 +6200,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U87$c0_lutcnst":{ + "d_0_am__U96$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U87$lut$lut":{ + "d_0_am__U96$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6324,18 +6324,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U85.out"], - ["d_1_inc.in1","_U851.out"], - ["cmp_time.in1","_U86.out"], - ["affine_func$mul_d0__U79.out","affine_func$add_all__U83.in0"], - ["affine_func$mul_d1__U81.out","affine_func$add_all__U83.in1"], - ["affine_func$add_all__U84.in0","affine_func$add_all__U83.out"], - ["affine_func$const_term_U82.out","affine_func$add_all__U84.in1"], - ["time_diff.in0","affine_func$add_all__U84.out"], - ["affine_func$mul_d0__U79.in0","affine_func$coeff_0_U78.out"], - ["affine_func$mul_d1__U81.in0","affine_func$coeff_1_U80.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U79.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U81.in1"], + ["d_0_inc.in1","_U94.out"], + ["d_1_inc.in1","_U941.out"], + ["cmp_time.in1","_U95.out"], + ["affine_func$mul_d0__U88.out","affine_func$add_all__U92.in0"], + ["affine_func$mul_d1__U90.out","affine_func$add_all__U92.in1"], + ["affine_func$add_all__U93.in0","affine_func$add_all__U92.out"], + ["affine_func$const_term_U91.out","affine_func$add_all__U93.in1"], + ["time_diff.in0","affine_func$add_all__U93.out"], + ["affine_func$mul_d0__U88.in0","affine_func$coeff_0_U87.out"], + ["affine_func$mul_d1__U90.in0","affine_func$coeff_1_U89.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U88.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U90.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6358,10 +6358,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U87$lut$lut.bit.in.2","d_0_am__U87$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U87$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U87$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U87$lut$lut.bit.out"], + ["d_0_am__U96$lut$lut.bit.in.2","d_0_am__U96$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U96$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U96$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U96$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6397,7 +6397,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U91":{ + "affine_controller__U99":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6405,49 +6405,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U100":{ + "_U108":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1001":{ + "_U1081":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U101":{ + "_U109":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U98":{ + "affine_func$add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U99":{ + "affine_func$add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U93":{ + "affine_func$coeff_0_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U95":{ + "affine_func$coeff_1_U103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U97":{ + "affine_func$const_term_U105":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00020000"]} }, - "affine_func$mul_d0__U94":{ + "affine_func$mul_d0__U102":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U96":{ + "affine_func$mul_d1__U104":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6511,12 +6511,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U102$c0_lutcnst":{ + "d_0_am__U110$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U102$lut$lut":{ + "d_0_am__U110$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6635,18 +6635,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U100.out"], - ["d_1_inc.in1","_U1001.out"], - ["cmp_time.in1","_U101.out"], - ["affine_func$mul_d0__U94.out","affine_func$add_all__U98.in0"], - ["affine_func$mul_d1__U96.out","affine_func$add_all__U98.in1"], - ["affine_func$add_all__U99.in0","affine_func$add_all__U98.out"], - ["affine_func$const_term_U97.out","affine_func$add_all__U99.in1"], - ["time_diff.in0","affine_func$add_all__U99.out"], - ["affine_func$mul_d0__U94.in0","affine_func$coeff_0_U93.out"], - ["affine_func$mul_d1__U96.in0","affine_func$coeff_1_U95.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U94.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U96.in1"], + ["d_0_inc.in1","_U108.out"], + ["d_1_inc.in1","_U1081.out"], + ["cmp_time.in1","_U109.out"], + ["affine_func$mul_d0__U102.out","affine_func$add_all__U106.in0"], + ["affine_func$mul_d1__U104.out","affine_func$add_all__U106.in1"], + ["affine_func$add_all__U107.in0","affine_func$add_all__U106.out"], + ["affine_func$const_term_U105.out","affine_func$add_all__U107.in1"], + ["time_diff.in0","affine_func$add_all__U107.out"], + ["affine_func$mul_d0__U102.in0","affine_func$coeff_0_U101.out"], + ["affine_func$mul_d1__U104.in0","affine_func$coeff_1_U103.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U102.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U104.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6669,10 +6669,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U102$lut$lut.bit.in.2","d_0_am__U102$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U102$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U102$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U102$lut$lut.bit.out"], + ["d_0_am__U110$lut$lut.bit.in.2","d_0_am__U110$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U110$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U110$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U110$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6723,10 +6723,6 @@ ["op_hcompute_output_gb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U14":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6734,7 +6730,7 @@ }, "ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[8196],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[9214],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -6756,26 +6752,26 @@ ["conv_stencil_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U317":{ + "PE_init_U306":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U315":{ + "_U304":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U316":{ + "_U305":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U315.out","PE_init_U317.data.in.0"], - ["_U316.out","PE_init_U317.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U317.data.out"], + ["_U304.out","PE_init_U306.data.in.0"], + ["_U305.out","PE_init_U306.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U306.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6913,25 +6909,21 @@ ["input_host_stencil_op_hcompute_input_gb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U320":{ + "PE_init_U309":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U318":{ + "_U307":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U319":{ + "_U308":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "conv_stencil$chain_en_const_U14":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6939,41 +6931,9 @@ }, "conv_stencil$ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[8196],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[9214],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "hw_input_stencil$chain_en_const_U104":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_stencil$chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_stencil$chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_stencil$chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_stencil$chain_en_const_U44":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_stencil$chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_stencil$chain_en_const_U74":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_stencil$chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_input_stencil$ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6981,7 +6941,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -6991,7 +6951,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -7001,7 +6961,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -7011,7 +6971,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -7021,7 +6981,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -7031,7 +6991,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -7041,7 +7001,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U105"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -7051,7 +7011,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -7121,14 +7081,14 @@ }, "op_hcompute_hw_output_stencil_port_controller_lake_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U303"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[9216],"cycle_stride":[1,8192],"dimensionality":2,"extent":[1024,16],"write_data_starting_addr":[0],"write_data_stride":[1,1024]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U318.out","PE_init_U320.data.in.0"], - ["_U319.out","PE_init_U320.data.in.1"], - ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U320.data.out"], + ["_U307.out","PE_init_U309.data.in.0"], + ["_U308.out","PE_init_U309.data.in.1"], + ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U309.data.out"], ["conv_stencil$ub_conv_stencil_BANK_0_garnet.clk_en","conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_conv_stencil_1$inner_compute$add_hw_input_stencil_1_362_363$binop.data.out","conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_conv_stencil_1$inner_compute$add_conv_stencil_1_361_362$binop.data.in.0","conv_stencil$ub_conv_stencil_BANK_0_garnet.data_out_0"], @@ -7183,26 +7143,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U323":{ + "PE_init_U312":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U321":{ + "_U310":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U322":{ + "_U311":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U321.out","PE_init_U323.data.in.0"], - ["_U322.out","PE_init_U323.data.in.1"], - ["self.out_conv_stencil","PE_init_U323.data.out"] + ["_U310.out","PE_init_U312.data.in.0"], + ["_U311.out","PE_init_U312.data.in.1"], + ["self.out_conv_stencil","PE_init_U312.data.out"] ] }, "hcompute_conv_stencil_1":{ @@ -7320,38 +7280,6 @@ ["op_hcompute_hw_input_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U104":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U44":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U74":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -7359,7 +7287,7 @@ }, "ub_hw_input_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -7369,7 +7297,7 @@ }, "ub_hw_input_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -7379,7 +7307,7 @@ }, "ub_hw_input_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -7389,7 +7317,7 @@ }, "ub_hw_input_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -7399,7 +7327,7 @@ }, "ub_hw_input_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -7409,7 +7337,7 @@ }, "ub_hw_input_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8189],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -7419,7 +7347,7 @@ }, "ub_hw_input_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U105"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -7429,7 +7357,7 @@ }, "ub_hw_input_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,1024,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,32,256]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,1024,8192],"dimensionality":3,"extent":[128,8,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[8190],"cycle_stride":[4,128,8192],"dimensionality":3,"extent":[32,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,32,256],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8192],"cycle_stride":[1,128,8192],"dimensionality":3,"extent":[128,8,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -7490,7 +7418,7 @@ ["self.op_hcompute_input_gb_stencil_write.0","self.op_hcompute_hw_input_stencil_read.0"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U306":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U295":{ "type":["Record",[ ["in",["Array",3,["Array",32,"BitIn"]]], ["out",["Array",3,["Array",32,"Bit"]]] @@ -7499,7 +7427,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U305":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U294":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -7508,7 +7436,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U304":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U293":{ "type":["Record",[ ["in",["Array",3,["Array",32,"BitIn"]]], ["out",["Array",3,["Array",32,"Bit"]]] @@ -7517,7 +7445,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U303":{ + "op_hcompute_hw_output_stencil_read_start_pt__U292":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -7526,7 +7454,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U308":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U297":{ "type":["Record",[ ["in",["Array",3,["Array",32,"BitIn"]]], ["out",["Array",3,["Array",32,"Bit"]]] @@ -7535,7 +7463,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U307":{ + "op_hcompute_hw_output_stencil_write_start_pt__U296":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -7544,7 +7472,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_gb_stencil_exe_start_pt__U311":{ + "op_hcompute_input_gb_stencil_exe_start_pt__U300":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -7553,7 +7481,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_gb_stencil_read_start_pt__U310":{ + "op_hcompute_input_gb_stencil_read_start_pt__U299":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -7562,7 +7490,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_gb_stencil_write_start_pt__U312":{ + "op_hcompute_input_gb_stencil_write_start_pt__U301":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] diff --git a/aha_garnet_design_new/harris/harris.json b/aha_garnet_design_new/harris/harris.json index 804e99d52..19868c228 100644 --- a/aha_garnet_design_new/harris/harris.json +++ b/aha_garnet_design_new/harris/harris.json @@ -27,9 +27,10 @@ ["op_hcompute_cim_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2":{ "genref":"mantle.reg", @@ -56,15 +57,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "ub_cim_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[264],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[386],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"sram2tb_1":{"cycle_starting_addr":[321],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[388],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]},"tb2out_1":{"cycle_starting_addr":[324],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[264],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[386],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"sram2tb_1":{"cycle_starting_addr":[321],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[388],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]},"tb2out_1":{"cycle_starting_addr":[324],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake"} }, "ub_cim_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -72,25 +68,24 @@ } }, "connections":[ - ["ub_cim_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], + ["self.clk","d_reg__U1.clk"], + ["self.op_hcompute_cim_stencil_write.0","d_reg__U1.in"], + ["d_reg__U2.in","d_reg__U1.out"], + ["self.op_hcompute_cim_output_stencil_read.7","d_reg__U1.out"], ["self.clk","d_reg__U2.clk"], - ["self.op_hcompute_cim_stencil_write.0","d_reg__U2.in"], - ["d_reg__U3.in","d_reg__U2.out"], - ["self.op_hcompute_cim_output_stencil_read.7","d_reg__U2.out"], + ["self.op_hcompute_cim_output_stencil_read.6","d_reg__U2.out"], ["self.clk","d_reg__U3.clk"], - ["self.op_hcompute_cim_output_stencil_read.6","d_reg__U3.out"], + ["ub_cim_stencil_BANK_0.data_out_1","d_reg__U3.in"], + ["d_reg__U4.in","d_reg__U3.out"], + ["self.op_hcompute_cim_output_stencil_read.1","d_reg__U3.out"], ["self.clk","d_reg__U4.clk"], - ["ub_cim_stencil_BANK_0.data_out_1","d_reg__U4.in"], - ["d_reg__U5.in","d_reg__U4.out"], - ["self.op_hcompute_cim_output_stencil_read.1","d_reg__U4.out"], + ["self.op_hcompute_cim_output_stencil_read.4","d_reg__U4.out"], ["self.clk","d_reg__U5.clk"], - ["self.op_hcompute_cim_output_stencil_read.4","d_reg__U5.out"], + ["ub_cim_stencil_BANK_0.data_out_0","d_reg__U5.in"], + ["d_reg__U6.in","d_reg__U5.out"], + ["self.op_hcompute_cim_output_stencil_read.2","d_reg__U5.out"], ["self.clk","d_reg__U6.clk"], - ["ub_cim_stencil_BANK_0.data_out_0","d_reg__U6.in"], - ["d_reg__U7.in","d_reg__U6.out"], - ["self.op_hcompute_cim_output_stencil_read.2","d_reg__U6.out"], - ["self.clk","d_reg__U7.clk"], - ["self.op_hcompute_cim_output_stencil_read.0","d_reg__U7.out"], + ["self.op_hcompute_cim_output_stencil_read.0","d_reg__U6.out"], ["ub_cim_stencil_BANK_0.clk","self.clk"], ["ub_cim_stencil_BANK_0.data_out_0","self.op_hcompute_cim_output_stencil_read.3"], ["ub_cim_stencil_BANK_0.data_out_1","self.op_hcompute_cim_output_stencil_read.5"], @@ -478,7 +473,7 @@ ["padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U48":{ + "_U43":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -538,22 +533,22 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U42" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U37" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[390],"cycle_stride":[1,64],"dimensionality":2,"extent":[58,58]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U40"} + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[390],"cycle_stride":[1,64],"dimensionality":2,"extent":[58,58]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U41" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U36" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U43" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U38" }, "op_hcompute_lgxx_stencil":{ "modref":"global.cu_op_hcompute_lgxx_stencil" @@ -586,30 +581,30 @@ "modref":"global.cu_op_hcompute_padded16_global_wrapper_stencil" }, "op_hcompute_padded16_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_padded16_global_wrapper_stencil_exe_start_pt__U46" + "modref":"global.op_hcompute_padded16_global_wrapper_stencil_exe_start_pt__U41" }, "op_hcompute_padded16_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U44"} + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_padded16_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_padded16_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_padded16_global_wrapper_stencil_read_start_pt__U45" + "modref":"global.op_hcompute_padded16_global_wrapper_stencil_read_start_pt__U40" }, "op_hcompute_padded16_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_padded16_global_wrapper_stencil_write_start_pt__U47" + "modref":"global.op_hcompute_padded16_global_wrapper_stencil_write_start_pt__U42" }, "padded16_global_wrapper_stencil":{ "modref":"global.padded16_global_wrapper_stencil_ub" } }, "connections":[ - ["self.clk","_U48.clk"], - ["self.padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read.0","_U48.in"], + ["self.clk","_U43.clk"], + ["self.padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read.0","_U43.in"], ["self.clk","cim_output_stencil.clk"], ["op_hcompute_cim_output_stencil.cim_output_stencil_op_hcompute_cim_output_stencil_write","cim_output_stencil.op_hcompute_cim_output_stencil_write"], ["op_hcompute_hw_output_stencil.cim_output_stencil_op_hcompute_hw_output_stencil_read","cim_output_stencil.op_hcompute_hw_output_stencil_read"], @@ -1535,10 +1530,6 @@ ["op_hcompute_lxx_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "d_reg__U10":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -1559,20 +1550,20 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U14":{ + "d_reg__U8":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U15":{ + "d_reg__U9":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_lxx_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_lxx_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1580,25 +1571,24 @@ } }, "connections":[ - ["ub_lxx_stencil_BANK_0.chain_chain_en","chain_en_const_U9.out"], ["self.clk","d_reg__U10.clk"], - ["self.op_hcompute_lxx_stencil_write.0","d_reg__U10.in"], + ["ub_lxx_stencil_BANK_0.data_out_1","d_reg__U10.in"], ["d_reg__U11.in","d_reg__U10.out"], - ["self.op_hcompute_lgxx_stencil_1_read.8","d_reg__U10.out"], + ["self.op_hcompute_lgxx_stencil_1_read.4","d_reg__U10.out"], ["self.clk","d_reg__U11.clk"], - ["self.op_hcompute_lgxx_stencil_1_read.6","d_reg__U11.out"], + ["self.op_hcompute_lgxx_stencil_1_read.3","d_reg__U11.out"], ["self.clk","d_reg__U12.clk"], - ["ub_lxx_stencil_BANK_0.data_out_1","d_reg__U12.in"], + ["ub_lxx_stencil_BANK_0.data_out_0","d_reg__U12.in"], ["d_reg__U13.in","d_reg__U12.out"], - ["self.op_hcompute_lgxx_stencil_1_read.4","d_reg__U12.out"], + ["self.op_hcompute_lgxx_stencil_1_read.1","d_reg__U12.out"], ["self.clk","d_reg__U13.clk"], - ["self.op_hcompute_lgxx_stencil_1_read.3","d_reg__U13.out"], - ["self.clk","d_reg__U14.clk"], - ["ub_lxx_stencil_BANK_0.data_out_0","d_reg__U14.in"], - ["d_reg__U15.in","d_reg__U14.out"], - ["self.op_hcompute_lgxx_stencil_1_read.1","d_reg__U14.out"], - ["self.clk","d_reg__U15.clk"], - ["self.op_hcompute_lgxx_stencil_1_read.0","d_reg__U15.out"], + ["self.op_hcompute_lgxx_stencil_1_read.0","d_reg__U13.out"], + ["self.clk","d_reg__U8.clk"], + ["self.op_hcompute_lxx_stencil_write.0","d_reg__U8.in"], + ["d_reg__U9.in","d_reg__U8.out"], + ["self.op_hcompute_lgxx_stencil_1_read.8","d_reg__U8.out"], + ["self.clk","d_reg__U9.clk"], + ["self.op_hcompute_lgxx_stencil_1_read.6","d_reg__U9.out"], ["ub_lxx_stencil_BANK_0.clk","self.clk"], ["ub_lxx_stencil_BANK_0.data_out_0","self.op_hcompute_lgxx_stencil_1_read.2"], ["ub_lxx_stencil_BANK_0.data_out_1","self.op_hcompute_lgxx_stencil_1_read.5"], @@ -1620,44 +1610,40 @@ ["op_hcompute_lxy_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U18":{ + "d_reg__U15":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U19":{ + "d_reg__U16":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U20":{ + "d_reg__U17":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U21":{ + "d_reg__U18":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U22":{ + "d_reg__U19":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U23":{ + "d_reg__U20":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_lxy_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U16"} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_lxy_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1665,25 +1651,24 @@ } }, "connections":[ - ["ub_lxy_stencil_BANK_0.chain_chain_en","chain_en_const_U17.out"], + ["self.clk","d_reg__U15.clk"], + ["self.op_hcompute_lxy_stencil_write.0","d_reg__U15.in"], + ["d_reg__U16.in","d_reg__U15.out"], + ["self.op_hcompute_lgxy_stencil_1_read.8","d_reg__U15.out"], + ["self.clk","d_reg__U16.clk"], + ["self.op_hcompute_lgxy_stencil_1_read.6","d_reg__U16.out"], + ["self.clk","d_reg__U17.clk"], + ["ub_lxy_stencil_BANK_0.data_out_1","d_reg__U17.in"], + ["d_reg__U18.in","d_reg__U17.out"], + ["self.op_hcompute_lgxy_stencil_1_read.4","d_reg__U17.out"], ["self.clk","d_reg__U18.clk"], - ["self.op_hcompute_lxy_stencil_write.0","d_reg__U18.in"], - ["d_reg__U19.in","d_reg__U18.out"], - ["self.op_hcompute_lgxy_stencil_1_read.8","d_reg__U18.out"], + ["self.op_hcompute_lgxy_stencil_1_read.3","d_reg__U18.out"], ["self.clk","d_reg__U19.clk"], - ["self.op_hcompute_lgxy_stencil_1_read.6","d_reg__U19.out"], + ["ub_lxy_stencil_BANK_0.data_out_0","d_reg__U19.in"], + ["d_reg__U20.in","d_reg__U19.out"], + ["self.op_hcompute_lgxy_stencil_1_read.1","d_reg__U19.out"], ["self.clk","d_reg__U20.clk"], - ["ub_lxy_stencil_BANK_0.data_out_1","d_reg__U20.in"], - ["d_reg__U21.in","d_reg__U20.out"], - ["self.op_hcompute_lgxy_stencil_1_read.4","d_reg__U20.out"], - ["self.clk","d_reg__U21.clk"], - ["self.op_hcompute_lgxy_stencil_1_read.3","d_reg__U21.out"], - ["self.clk","d_reg__U22.clk"], - ["ub_lxy_stencil_BANK_0.data_out_0","d_reg__U22.in"], - ["d_reg__U23.in","d_reg__U22.out"], - ["self.op_hcompute_lgxy_stencil_1_read.1","d_reg__U22.out"], - ["self.clk","d_reg__U23.clk"], - ["self.op_hcompute_lgxy_stencil_1_read.0","d_reg__U23.out"], + ["self.op_hcompute_lgxy_stencil_1_read.0","d_reg__U20.out"], ["ub_lxy_stencil_BANK_0.clk","self.clk"], ["ub_lxy_stencil_BANK_0.data_out_0","self.op_hcompute_lgxy_stencil_1_read.2"], ["ub_lxy_stencil_BANK_0.data_out_1","self.op_hcompute_lgxy_stencil_1_read.5"], @@ -1705,44 +1690,40 @@ ["op_hcompute_lyy_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U26":{ + "d_reg__U22":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U27":{ + "d_reg__U23":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U28":{ + "d_reg__U24":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U29":{ + "d_reg__U25":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U30":{ + "d_reg__U26":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U31":{ + "d_reg__U27":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_lyy_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U24"} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_lyy_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1750,25 +1731,24 @@ } }, "connections":[ - ["ub_lyy_stencil_BANK_0.chain_chain_en","chain_en_const_U25.out"], + ["self.clk","d_reg__U22.clk"], + ["self.op_hcompute_lyy_stencil_write.0","d_reg__U22.in"], + ["d_reg__U23.in","d_reg__U22.out"], + ["self.op_hcompute_lgyy_stencil_1_read.8","d_reg__U22.out"], + ["self.clk","d_reg__U23.clk"], + ["self.op_hcompute_lgyy_stencil_1_read.6","d_reg__U23.out"], + ["self.clk","d_reg__U24.clk"], + ["ub_lyy_stencil_BANK_0.data_out_1","d_reg__U24.in"], + ["d_reg__U25.in","d_reg__U24.out"], + ["self.op_hcompute_lgyy_stencil_1_read.4","d_reg__U24.out"], + ["self.clk","d_reg__U25.clk"], + ["self.op_hcompute_lgyy_stencil_1_read.3","d_reg__U25.out"], ["self.clk","d_reg__U26.clk"], - ["self.op_hcompute_lyy_stencil_write.0","d_reg__U26.in"], + ["ub_lyy_stencil_BANK_0.data_out_0","d_reg__U26.in"], ["d_reg__U27.in","d_reg__U26.out"], - ["self.op_hcompute_lgyy_stencil_1_read.8","d_reg__U26.out"], + ["self.op_hcompute_lgyy_stencil_1_read.1","d_reg__U26.out"], ["self.clk","d_reg__U27.clk"], - ["self.op_hcompute_lgyy_stencil_1_read.6","d_reg__U27.out"], - ["self.clk","d_reg__U28.clk"], - ["ub_lyy_stencil_BANK_0.data_out_1","d_reg__U28.in"], - ["d_reg__U29.in","d_reg__U28.out"], - ["self.op_hcompute_lgyy_stencil_1_read.4","d_reg__U28.out"], - ["self.clk","d_reg__U29.clk"], - ["self.op_hcompute_lgyy_stencil_1_read.3","d_reg__U29.out"], - ["self.clk","d_reg__U30.clk"], - ["ub_lyy_stencil_BANK_0.data_out_0","d_reg__U30.in"], - ["d_reg__U31.in","d_reg__U30.out"], - ["self.op_hcompute_lgyy_stencil_1_read.1","d_reg__U30.out"], - ["self.clk","d_reg__U31.clk"], - ["self.op_hcompute_lgyy_stencil_1_read.0","d_reg__U31.out"], + ["self.op_hcompute_lgyy_stencil_1_read.0","d_reg__U27.out"], ["ub_lyy_stencil_BANK_0.clk","self.clk"], ["ub_lyy_stencil_BANK_0.data_out_0","self.op_hcompute_lgyy_stencil_1_read.2"], ["ub_lyy_stencil_BANK_0.data_out_1","self.op_hcompute_lgyy_stencil_1_read.5"], @@ -1779,7 +1759,7 @@ ["ub_lyy_stencil_BANK_0_clk_en_const.out","ub_lyy_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U42":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U37":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1788,7 +1768,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U41":{ + "op_hcompute_hw_output_stencil_read_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1797,7 +1777,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U43":{ + "op_hcompute_hw_output_stencil_write_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1806,7 +1786,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_padded16_global_wrapper_stencil_exe_start_pt__U46":{ + "op_hcompute_padded16_global_wrapper_stencil_exe_start_pt__U41":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1815,7 +1795,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_padded16_global_wrapper_stencil_read_start_pt__U45":{ + "op_hcompute_padded16_global_wrapper_stencil_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1824,7 +1804,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_padded16_global_wrapper_stencil_write_start_pt__U47":{ + "op_hcompute_padded16_global_wrapper_stencil_write_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1846,44 +1826,40 @@ ["op_hcompute_padded16_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U34":{ + "d_reg__U29":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U35":{ + "d_reg__U30":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U36":{ + "d_reg__U31":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U37":{ + "d_reg__U32":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U38":{ + "d_reg__U33":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U39":{ + "d_reg__U34":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_padded16_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U32"} + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_padded16_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1891,26 +1867,25 @@ } }, "connections":[ - ["ub_padded16_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U33.out"], + ["self.clk","d_reg__U29.clk"], + ["self.op_hcompute_padded16_global_wrapper_stencil_write.0","d_reg__U29.in"], + ["d_reg__U30.in","d_reg__U29.out"], + ["self.op_hcompute_grad_y_stencil_read.5","d_reg__U29.out"], + ["self.clk","d_reg__U30.clk"], + ["self.op_hcompute_grad_x_stencil_read.5","d_reg__U30.out"], + ["self.op_hcompute_grad_y_stencil_read.3","d_reg__U30.out"], + ["self.clk","d_reg__U31.clk"], + ["ub_padded16_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U31.in"], + ["d_reg__U32.in","d_reg__U31.out"], + ["self.clk","d_reg__U32.clk"], + ["self.op_hcompute_grad_x_stencil_read.4","d_reg__U32.out"], + ["self.clk","d_reg__U33.clk"], + ["ub_padded16_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U33.in"], + ["d_reg__U34.in","d_reg__U33.out"], + ["self.op_hcompute_grad_y_stencil_read.1","d_reg__U33.out"], ["self.clk","d_reg__U34.clk"], - ["self.op_hcompute_padded16_global_wrapper_stencil_write.0","d_reg__U34.in"], - ["d_reg__U35.in","d_reg__U34.out"], - ["self.op_hcompute_grad_y_stencil_read.5","d_reg__U34.out"], - ["self.clk","d_reg__U35.clk"], - ["self.op_hcompute_grad_x_stencil_read.5","d_reg__U35.out"], - ["self.op_hcompute_grad_y_stencil_read.3","d_reg__U35.out"], - ["self.clk","d_reg__U36.clk"], - ["ub_padded16_global_wrapper_stencil_BANK_0.data_out_1","d_reg__U36.in"], - ["d_reg__U37.in","d_reg__U36.out"], - ["self.clk","d_reg__U37.clk"], - ["self.op_hcompute_grad_x_stencil_read.4","d_reg__U37.out"], - ["self.clk","d_reg__U38.clk"], - ["ub_padded16_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U38.in"], - ["d_reg__U39.in","d_reg__U38.out"], - ["self.op_hcompute_grad_y_stencil_read.1","d_reg__U38.out"], - ["self.clk","d_reg__U39.clk"], - ["self.op_hcompute_grad_x_stencil_read.3","d_reg__U39.out"], - ["self.op_hcompute_grad_y_stencil_read.0","d_reg__U39.out"], + ["self.op_hcompute_grad_x_stencil_read.3","d_reg__U34.out"], + ["self.op_hcompute_grad_y_stencil_read.0","d_reg__U34.out"], ["ub_padded16_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_padded16_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_grad_x_stencil_read.0"], ["self.op_hcompute_padded16_global_wrapper_stencil_write.0","self.op_hcompute_grad_x_stencil_read.1"], diff --git a/aha_garnet_design_new/harris/harris_garnet.json b/aha_garnet_design_new/harris/harris_garnet.json index 744ed6e95..75398ee4a 100644 --- a/aha_garnet_design_new/harris/harris_garnet.json +++ b/aha_garnet_design_new/harris/harris_garnet.json @@ -218,9 +218,10 @@ ["op_hcompute_cim_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -247,11 +248,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "ub_cim_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -259,29 +255,29 @@ }, "ub_cim_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[264],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[386],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"sram2tb_1":{"cycle_starting_addr":[321],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[388],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]},"tb2out_1":{"cycle_starting_addr":[324],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U1$reg0.clk"], + ["self.op_hcompute_cim_stencil_write.0","d_reg__U1$reg0.in"], + ["d_reg__U2$reg0.in","d_reg__U1$reg0.out"], + ["self.op_hcompute_cim_output_stencil_read.7","d_reg__U1$reg0.out"], ["self.clk","d_reg__U2$reg0.clk"], - ["self.op_hcompute_cim_stencil_write.0","d_reg__U2$reg0.in"], - ["d_reg__U3$reg0.in","d_reg__U2$reg0.out"], - ["self.op_hcompute_cim_output_stencil_read.7","d_reg__U2$reg0.out"], + ["self.op_hcompute_cim_output_stencil_read.6","d_reg__U2$reg0.out"], ["self.clk","d_reg__U3$reg0.clk"], - ["self.op_hcompute_cim_output_stencil_read.6","d_reg__U3$reg0.out"], + ["ub_cim_stencil_BANK_0_garnet.data_out_1","d_reg__U3$reg0.in"], + ["d_reg__U4$reg0.in","d_reg__U3$reg0.out"], + ["self.op_hcompute_cim_output_stencil_read.1","d_reg__U3$reg0.out"], ["self.clk","d_reg__U4$reg0.clk"], - ["ub_cim_stencil_BANK_0_garnet.data_out_1","d_reg__U4$reg0.in"], - ["d_reg__U5$reg0.in","d_reg__U4$reg0.out"], - ["self.op_hcompute_cim_output_stencil_read.1","d_reg__U4$reg0.out"], + ["self.op_hcompute_cim_output_stencil_read.4","d_reg__U4$reg0.out"], ["self.clk","d_reg__U5$reg0.clk"], - ["self.op_hcompute_cim_output_stencil_read.4","d_reg__U5$reg0.out"], + ["ub_cim_stencil_BANK_0_garnet.data_out_0","d_reg__U5$reg0.in"], + ["d_reg__U6$reg0.in","d_reg__U5$reg0.out"], + ["self.op_hcompute_cim_output_stencil_read.2","d_reg__U5$reg0.out"], ["self.clk","d_reg__U6$reg0.clk"], - ["ub_cim_stencil_BANK_0_garnet.data_out_0","d_reg__U6$reg0.in"], - ["d_reg__U7$reg0.in","d_reg__U6$reg0.out"], - ["self.op_hcompute_cim_output_stencil_read.2","d_reg__U6$reg0.out"], - ["self.clk","d_reg__U7$reg0.clk"], - ["self.op_hcompute_cim_output_stencil_read.0","d_reg__U7$reg0.out"], + ["self.op_hcompute_cim_output_stencil_read.0","d_reg__U6$reg0.out"], ["ub_cim_stencil_BANK_0_garnet.clk","self.clk"], ["ub_cim_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_cim_output_stencil_read.3"], ["ub_cim_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_cim_output_stencil_read.5"], @@ -846,26 +842,26 @@ ["lgxx_stencil_clkwrk_dsa0_op_hcompute_lgxx_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U51":{ + "PE_init_U46":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U49":{ + "_U44":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U50":{ + "_U45":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U49.out","PE_init_U51.data.in.0"], - ["_U50.out","PE_init_U51.data.in.1"], - ["self.lgxx_stencil_clkwrk_dsa0_op_hcompute_lgxx_stencil_write.0","PE_init_U51.data.out"], + ["_U44.out","PE_init_U46.data.in.0"], + ["_U45.out","PE_init_U46.data.in.1"], + ["self.lgxx_stencil_clkwrk_dsa0_op_hcompute_lgxx_stencil_write.0","PE_init_U46.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -956,26 +952,26 @@ ["lgxy_stencil_clkwrk_dsa1_op_hcompute_lgxy_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U54":{ + "PE_init_U49":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U52":{ + "_U47":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U53":{ + "_U48":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U52.out","PE_init_U54.data.in.0"], - ["_U53.out","PE_init_U54.data.in.1"], - ["self.lgxy_stencil_clkwrk_dsa1_op_hcompute_lgxy_stencil_write.0","PE_init_U54.data.out"], + ["_U47.out","PE_init_U49.data.in.0"], + ["_U48.out","PE_init_U49.data.in.1"], + ["self.lgxy_stencil_clkwrk_dsa1_op_hcompute_lgxy_stencil_write.0","PE_init_U49.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1066,26 +1062,26 @@ ["lgyy_stencil_clkwrk_dsa2_op_hcompute_lgyy_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U57":{ + "PE_init_U52":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U55":{ + "_U50":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U56":{ + "_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U55.out","PE_init_U57.data.in.0"], - ["_U56.out","PE_init_U57.data.in.1"], - ["self.lgyy_stencil_clkwrk_dsa2_op_hcompute_lgyy_stencil_write.0","PE_init_U57.data.out"], + ["_U50.out","PE_init_U52.data.in.0"], + ["_U51.out","PE_init_U52.data.in.1"], + ["self.lgyy_stencil_clkwrk_dsa2_op_hcompute_lgyy_stencil_write.0","PE_init_U52.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1328,9 +1324,10 @@ ["padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "cim_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "cim_stencil$d_reg__U1$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, "cim_stencil$d_reg__U2$reg0":{ "genref":"coreir.reg", @@ -1357,11 +1354,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "cim_stencil$d_reg__U7$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",16]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} - }, "cim_stencil$ub_cim_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -1369,7 +1361,7 @@ }, "cim_stencil$ub_cim_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[264],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,15]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[386],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"sram2tb_1":{"cycle_starting_addr":[321],"cycle_stride":[4,64],"dimensionality":2,"extent":[15,60],"read_data_starting_addr":[0],"read_data_stride":[1,15],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[388],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]},"tb2out_1":{"cycle_starting_addr":[324],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -1392,10 +1384,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "lxx_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "lxx_stencil$d_reg__U10$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, @@ -1416,12 +1404,12 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lxx_stencil$d_reg__U14$reg0":{ + "lxx_stencil$d_reg__U8$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lxx_stencil$d_reg__U15$reg0":{ + "lxx_stencil$d_reg__U9$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -1433,39 +1421,35 @@ }, "lxx_stencil$ub_lxx_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "lxy_stencil$chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "lxy_stencil$d_reg__U18$reg0":{ + "lxy_stencil$d_reg__U15$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lxy_stencil$d_reg__U19$reg0":{ + "lxy_stencil$d_reg__U16$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lxy_stencil$d_reg__U20$reg0":{ + "lxy_stencil$d_reg__U17$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lxy_stencil$d_reg__U21$reg0":{ + "lxy_stencil$d_reg__U18$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lxy_stencil$d_reg__U22$reg0":{ + "lxy_stencil$d_reg__U19$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lxy_stencil$d_reg__U23$reg0":{ + "lxy_stencil$d_reg__U20$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -1477,39 +1461,35 @@ }, "lxy_stencil$ub_lxy_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "lyy_stencil$chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "lyy_stencil$d_reg__U26$reg0":{ + "lyy_stencil$d_reg__U22$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lyy_stencil$d_reg__U27$reg0":{ + "lyy_stencil$d_reg__U23$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lyy_stencil$d_reg__U28$reg0":{ + "lyy_stencil$d_reg__U24$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lyy_stencil$d_reg__U29$reg0":{ + "lyy_stencil$d_reg__U25$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lyy_stencil$d_reg__U30$reg0":{ + "lyy_stencil$d_reg__U26$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "lyy_stencil$d_reg__U31$reg0":{ + "lyy_stencil$d_reg__U27$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -1521,8 +1501,8 @@ }, "lyy_stencil$ub_lyy_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_cim_output_stencil$inner_compute$bitand_575_576_577$c0_lutcnst":{ "genref":"cgralib.PE", @@ -1896,7 +1876,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[390],"cycle_stride":[1,64],"dimensionality":2,"extent":[58,58]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_lgxx_stencil$inner_compute$const_p0__318":{ @@ -2094,36 +2074,32 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "padded16_global_wrapper_stencil$chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "padded16_global_wrapper_stencil$d_reg__U34$reg0":{ + "padded16_global_wrapper_stencil$d_reg__U29$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "padded16_global_wrapper_stencil$d_reg__U35$reg0":{ + "padded16_global_wrapper_stencil$d_reg__U30$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "padded16_global_wrapper_stencil$d_reg__U36$reg0":{ + "padded16_global_wrapper_stencil$d_reg__U31$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "padded16_global_wrapper_stencil$d_reg__U37$reg0":{ + "padded16_global_wrapper_stencil$d_reg__U32$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "padded16_global_wrapper_stencil$d_reg__U38$reg0":{ + "padded16_global_wrapper_stencil$d_reg__U33$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "padded16_global_wrapper_stencil$d_reg__U39$reg0":{ + "padded16_global_wrapper_stencil$d_reg__U34$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -2135,31 +2111,31 @@ }, "padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["op_hcompute_cim_stencil$inner_compute$sub_534_538_539$binop.data.out","cim_stencil$d_reg__U2$reg0.in"], - ["cim_stencil$d_reg__U3$reg0.in","cim_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_8_cim_stencil_2_586$compop.data.in.0","cim_stencil$d_reg__U2$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_7_cim_stencil_2_584$compop.data.in.0","cim_stencil$d_reg__U3$reg0.out"], - ["cim_stencil$ub_cim_stencil_BANK_0_garnet.data_out_1","cim_stencil$d_reg__U4$reg0.in"], - ["cim_stencil$d_reg__U5$reg0.in","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$sle_590_cim_stencil_2_591$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_1_cim_stencil_2_575$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_3_cim_stencil_2_576$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_4_cim_stencil_2_578$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_5_cim_stencil_2_580$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_6_cim_stencil_2_582$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_7_cim_stencil_2_584$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_8_cim_stencil_2_586$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_9_cim_stencil_2_588$compop.data.in.1","cim_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_5_cim_stencil_2_580$compop.data.in.0","cim_stencil$d_reg__U5$reg0.out"], - ["cim_stencil$ub_cim_stencil_BANK_0_garnet.data_out_0","cim_stencil$d_reg__U6$reg0.in"], - ["cim_stencil$d_reg__U7$reg0.in","cim_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_3_cim_stencil_2_576$compop.data.in.0","cim_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_1_cim_stencil_2_575$compop.data.in.0","cim_stencil$d_reg__U7$reg0.out"], + ["op_hcompute_cim_stencil$inner_compute$sub_534_538_539$binop.data.out","cim_stencil$d_reg__U1$reg0.in"], + ["cim_stencil$d_reg__U2$reg0.in","cim_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_8_cim_stencil_2_586$compop.data.in.0","cim_stencil$d_reg__U1$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_7_cim_stencil_2_584$compop.data.in.0","cim_stencil$d_reg__U2$reg0.out"], + ["cim_stencil$ub_cim_stencil_BANK_0_garnet.data_out_1","cim_stencil$d_reg__U3$reg0.in"], + ["cim_stencil$d_reg__U4$reg0.in","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$sle_590_cim_stencil_2_591$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_1_cim_stencil_2_575$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_3_cim_stencil_2_576$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_4_cim_stencil_2_578$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_5_cim_stencil_2_580$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_6_cim_stencil_2_582$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_7_cim_stencil_2_584$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_8_cim_stencil_2_586$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_9_cim_stencil_2_588$compop.data.in.1","cim_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_5_cim_stencil_2_580$compop.data.in.0","cim_stencil$d_reg__U4$reg0.out"], + ["cim_stencil$ub_cim_stencil_BANK_0_garnet.data_out_0","cim_stencil$d_reg__U5$reg0.in"], + ["cim_stencil$d_reg__U6$reg0.in","cim_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_3_cim_stencil_2_576$compop.data.in.0","cim_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_1_cim_stencil_2_575$compop.data.in.0","cim_stencil$d_reg__U6$reg0.out"], ["cim_stencil$ub_cim_stencil_BANK_0_garnet.clk_en","cim_stencil$ub_cim_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_cim_stencil$inner_compute$sub_534_538_539$binop.data.out","cim_stencil$ub_cim_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_cim_output_stencil$inner_compute$slt_cim_stencil_4_cim_stencil_2_578$compop.data.in.0","cim_stencil$ub_cim_stencil_BANK_0_garnet.data_out_0"], @@ -2168,7 +2144,7 @@ ["op_hcompute_cim_output_stencil$inner_compute$mux_5922550$mux.data.out","io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0.in"], ["op_hcompute_grad_x_stencil$inner_compute$add_padded16_global_wrapper_stencil_2_274_275$binop.data.in.0","io16in_padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read_0.out"], ["op_hcompute_grad_y_stencil$inner_compute$add_padded16_global_wrapper_stencil_8_374_375$binop.data.in.0","io16in_padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read_0.out"], - ["padded16_global_wrapper_stencil$d_reg__U34$reg0.in","io16in_padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read_0.out"], + ["padded16_global_wrapper_stencil$d_reg__U29$reg0.in","io16in_padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read_0.out"], ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_in_0","io16in_padded16_stencil_op_hcompute_padded16_global_wrapper_stencil_read_0.out"], ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_op_hcompute_hw_output_stencil_write_valid.in"], ["lxx_stencil$ub_lxx_stencil_BANK_0_garnet.flush","io1in_reset.out"], @@ -2176,50 +2152,50 @@ ["lyy_stencil$ub_lyy_stencil_BANK_0_garnet.flush","io1in_reset.out"], ["op_hcompute_hw_output_stencil_port_controller_garnet.flush","io1in_reset.out"], ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.flush","io1in_reset.out"], - ["op_hcompute_lxx_stencil$inner_compute$ashr_310_311_312$binop.data.out","lxx_stencil$d_reg__U10$reg0.in"], + ["lxx_stencil$ub_lxx_stencil_BANK_0_garnet.data_out_1","lxx_stencil$d_reg__U10$reg0.in"], ["lxx_stencil$d_reg__U11$reg0.in","lxx_stencil$d_reg__U10$reg0.out"], - ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_8_lxx_stencil_9_329$binop.data.in.1","lxx_stencil$d_reg__U10$reg0.out"], - ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_7_329_330$binop.data.in.0","lxx_stencil$d_reg__U11$reg0.out"], - ["lxx_stencil$ub_lxx_stencil_BANK_0_garnet.data_out_1","lxx_stencil$d_reg__U12$reg0.in"], + ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_5_331_332$binop.data.in.0","lxx_stencil$d_reg__U10$reg0.out"], + ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_4_332_333$binop.data.in.0","lxx_stencil$d_reg__U11$reg0.out"], + ["lxx_stencil$ub_lxx_stencil_BANK_0_garnet.data_out_0","lxx_stencil$d_reg__U12$reg0.in"], ["lxx_stencil$d_reg__U13$reg0.in","lxx_stencil$d_reg__U12$reg0.out"], - ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_5_331_332$binop.data.in.0","lxx_stencil$d_reg__U12$reg0.out"], - ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_4_332_333$binop.data.in.0","lxx_stencil$d_reg__U13$reg0.out"], - ["lxx_stencil$ub_lxx_stencil_BANK_0_garnet.data_out_0","lxx_stencil$d_reg__U14$reg0.in"], - ["lxx_stencil$d_reg__U15$reg0.in","lxx_stencil$d_reg__U14$reg0.out"], - ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_2_334_335$binop.data.in.0","lxx_stencil$d_reg__U14$reg0.out"], - ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_1_336_337$binop.data.in.0","lxx_stencil$d_reg__U15$reg0.out"], + ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_2_334_335$binop.data.in.0","lxx_stencil$d_reg__U12$reg0.out"], + ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_1_336_337$binop.data.in.0","lxx_stencil$d_reg__U13$reg0.out"], + ["op_hcompute_lxx_stencil$inner_compute$ashr_310_311_312$binop.data.out","lxx_stencil$d_reg__U8$reg0.in"], + ["lxx_stencil$d_reg__U9$reg0.in","lxx_stencil$d_reg__U8$reg0.out"], + ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_8_lxx_stencil_9_329$binop.data.in.1","lxx_stencil$d_reg__U8$reg0.out"], + ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_7_329_330$binop.data.in.0","lxx_stencil$d_reg__U9$reg0.out"], ["lxx_stencil$ub_lxx_stencil_BANK_0_garnet.clk_en","lxx_stencil$ub_lxx_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_lxx_stencil$inner_compute$ashr_310_311_312$binop.data.out","lxx_stencil$ub_lxx_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_3_333_334$binop.data.in.0","lxx_stencil$ub_lxx_stencil_BANK_0_garnet.data_out_0"], ["op_hcompute_lgxx_stencil_1$inner_compute$add_lxx_stencil_6_330_331$binop.data.in.0","lxx_stencil$ub_lxx_stencil_BANK_0_garnet.data_out_1"], - ["op_hcompute_lxy_stencil$inner_compute$ashr_410_411_412$binop.data.out","lxy_stencil$d_reg__U18$reg0.in"], - ["lxy_stencil$d_reg__U19$reg0.in","lxy_stencil$d_reg__U18$reg0.out"], - ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_8_lxy_stencil_9_430$binop.data.in.1","lxy_stencil$d_reg__U18$reg0.out"], - ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_7_430_431$binop.data.in.0","lxy_stencil$d_reg__U19$reg0.out"], - ["lxy_stencil$ub_lxy_stencil_BANK_0_garnet.data_out_1","lxy_stencil$d_reg__U20$reg0.in"], - ["lxy_stencil$d_reg__U21$reg0.in","lxy_stencil$d_reg__U20$reg0.out"], - ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_5_432_433$binop.data.in.0","lxy_stencil$d_reg__U20$reg0.out"], - ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_4_433_434$binop.data.in.0","lxy_stencil$d_reg__U21$reg0.out"], - ["lxy_stencil$ub_lxy_stencil_BANK_0_garnet.data_out_0","lxy_stencil$d_reg__U22$reg0.in"], - ["lxy_stencil$d_reg__U23$reg0.in","lxy_stencil$d_reg__U22$reg0.out"], - ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_2_435_436$binop.data.in.0","lxy_stencil$d_reg__U22$reg0.out"], - ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_1_437_438$binop.data.in.0","lxy_stencil$d_reg__U23$reg0.out"], + ["op_hcompute_lxy_stencil$inner_compute$ashr_410_411_412$binop.data.out","lxy_stencil$d_reg__U15$reg0.in"], + ["lxy_stencil$d_reg__U16$reg0.in","lxy_stencil$d_reg__U15$reg0.out"], + ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_8_lxy_stencil_9_430$binop.data.in.1","lxy_stencil$d_reg__U15$reg0.out"], + ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_7_430_431$binop.data.in.0","lxy_stencil$d_reg__U16$reg0.out"], + ["lxy_stencil$ub_lxy_stencil_BANK_0_garnet.data_out_1","lxy_stencil$d_reg__U17$reg0.in"], + ["lxy_stencil$d_reg__U18$reg0.in","lxy_stencil$d_reg__U17$reg0.out"], + ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_5_432_433$binop.data.in.0","lxy_stencil$d_reg__U17$reg0.out"], + ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_4_433_434$binop.data.in.0","lxy_stencil$d_reg__U18$reg0.out"], + ["lxy_stencil$ub_lxy_stencil_BANK_0_garnet.data_out_0","lxy_stencil$d_reg__U19$reg0.in"], + ["lxy_stencil$d_reg__U20$reg0.in","lxy_stencil$d_reg__U19$reg0.out"], + ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_2_435_436$binop.data.in.0","lxy_stencil$d_reg__U19$reg0.out"], + ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_1_437_438$binop.data.in.0","lxy_stencil$d_reg__U20$reg0.out"], ["lxy_stencil$ub_lxy_stencil_BANK_0_garnet.clk_en","lxy_stencil$ub_lxy_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_lxy_stencil$inner_compute$ashr_410_411_412$binop.data.out","lxy_stencil$ub_lxy_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_3_434_435$binop.data.in.0","lxy_stencil$ub_lxy_stencil_BANK_0_garnet.data_out_0"], ["op_hcompute_lgxy_stencil_1$inner_compute$add_lxy_stencil_6_431_432$binop.data.in.0","lxy_stencil$ub_lxy_stencil_BANK_0_garnet.data_out_1"], - ["op_hcompute_lyy_stencil$inner_compute$ashr_465_466_467$binop.data.out","lyy_stencil$d_reg__U26$reg0.in"], + ["op_hcompute_lyy_stencil$inner_compute$ashr_465_466_467$binop.data.out","lyy_stencil$d_reg__U22$reg0.in"], + ["lyy_stencil$d_reg__U23$reg0.in","lyy_stencil$d_reg__U22$reg0.out"], + ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_8_lyy_stencil_9_484$binop.data.in.1","lyy_stencil$d_reg__U22$reg0.out"], + ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_7_484_485$binop.data.in.0","lyy_stencil$d_reg__U23$reg0.out"], + ["lyy_stencil$ub_lyy_stencil_BANK_0_garnet.data_out_1","lyy_stencil$d_reg__U24$reg0.in"], + ["lyy_stencil$d_reg__U25$reg0.in","lyy_stencil$d_reg__U24$reg0.out"], + ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_5_486_487$binop.data.in.0","lyy_stencil$d_reg__U24$reg0.out"], + ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_4_487_488$binop.data.in.0","lyy_stencil$d_reg__U25$reg0.out"], + ["lyy_stencil$ub_lyy_stencil_BANK_0_garnet.data_out_0","lyy_stencil$d_reg__U26$reg0.in"], ["lyy_stencil$d_reg__U27$reg0.in","lyy_stencil$d_reg__U26$reg0.out"], - ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_8_lyy_stencil_9_484$binop.data.in.1","lyy_stencil$d_reg__U26$reg0.out"], - ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_7_484_485$binop.data.in.0","lyy_stencil$d_reg__U27$reg0.out"], - ["lyy_stencil$ub_lyy_stencil_BANK_0_garnet.data_out_1","lyy_stencil$d_reg__U28$reg0.in"], - ["lyy_stencil$d_reg__U29$reg0.in","lyy_stencil$d_reg__U28$reg0.out"], - ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_5_486_487$binop.data.in.0","lyy_stencil$d_reg__U28$reg0.out"], - ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_4_487_488$binop.data.in.0","lyy_stencil$d_reg__U29$reg0.out"], - ["lyy_stencil$ub_lyy_stencil_BANK_0_garnet.data_out_0","lyy_stencil$d_reg__U30$reg0.in"], - ["lyy_stencil$d_reg__U31$reg0.in","lyy_stencil$d_reg__U30$reg0.out"], - ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_2_489_490$binop.data.in.0","lyy_stencil$d_reg__U30$reg0.out"], - ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_1_491_492$binop.data.in.0","lyy_stencil$d_reg__U31$reg0.out"], + ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_2_489_490$binop.data.in.0","lyy_stencil$d_reg__U26$reg0.out"], + ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_1_491_492$binop.data.in.0","lyy_stencil$d_reg__U27$reg0.out"], ["lyy_stencil$ub_lyy_stencil_BANK_0_garnet.clk_en","lyy_stencil$ub_lyy_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_lyy_stencil$inner_compute$ashr_465_466_467$binop.data.out","lyy_stencil$ub_lyy_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_lgyy_stencil_1$inner_compute$add_lyy_stencil_3_488_489$binop.data.in.0","lyy_stencil$ub_lyy_stencil_BANK_0_garnet.data_out_0"], @@ -2283,7 +2259,7 @@ ["op_hcompute_grad_x_stencil$inner_compute$mul_padded16_global_wrapper_stencil_5_273_278$binop.data.in.1","op_hcompute_grad_x_stencil$inner_compute$const_p2__273$1.out"], ["op_hcompute_grad_x_stencil$inner_compute$mul_padded16_global_wrapper_stencil_3_273_274$binop.data.in.1","op_hcompute_grad_x_stencil$inner_compute$const_p2__273.out"], ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_1","op_hcompute_grad_x_stencil$inner_compute$mul_padded16_global_wrapper_stencil_3_273_274$binop.data.in.0"], - ["padded16_global_wrapper_stencil$d_reg__U37$reg0.out","op_hcompute_grad_x_stencil$inner_compute$mul_padded16_global_wrapper_stencil_5_273_278$binop.data.in.0"], + ["padded16_global_wrapper_stencil$d_reg__U32$reg0.out","op_hcompute_grad_x_stencil$inner_compute$mul_padded16_global_wrapper_stencil_5_273_278$binop.data.in.0"], ["op_hcompute_grad_x_stencil$inner_compute$sub_277_278_279$binop.data.in.1","op_hcompute_grad_x_stencil$inner_compute$mul_padded16_global_wrapper_stencil_5_273_278$binop.data.out"], ["op_hcompute_grad_x_stencil$inner_compute$smin_280_281_282$min_mux$mux.data.out","op_hcompute_grad_x_stencil$inner_compute$smax_282_283_284$cgramax.data.in.0"], ["op_hcompute_lxx_stencil$inner_compute$mul_grad_x_stencil_1_grad_x_stencil_1_310$binop.data.in.0","op_hcompute_grad_x_stencil$inner_compute$smax_282_283_284$cgramax.data.out"], @@ -2292,11 +2268,11 @@ ["op_hcompute_grad_x_stencil$inner_compute$smin_280_281_282$scomp$compop.bit.out","op_hcompute_grad_x_stencil$inner_compute$smin_280_281_282$min_mux$mux.bit.in.0"], ["op_hcompute_grad_x_stencil$inner_compute$sub_279_padded16_global_wrapper_stencil_6_280$binop.data.out","op_hcompute_grad_x_stencil$inner_compute$smin_280_281_282$min_mux$mux.data.in.0"], ["op_hcompute_grad_x_stencil$inner_compute$sub_279_padded16_global_wrapper_stencil_6_280$binop.data.out","op_hcompute_grad_x_stencil$inner_compute$smin_280_281_282$scomp$compop.data.in.0"], - ["padded16_global_wrapper_stencil$d_reg__U39$reg0.out","op_hcompute_grad_x_stencil$inner_compute$sub_276_padded16_global_wrapper_stencil_4_277$binop.data.in.1"], + ["padded16_global_wrapper_stencil$d_reg__U34$reg0.out","op_hcompute_grad_x_stencil$inner_compute$sub_276_padded16_global_wrapper_stencil_4_277$binop.data.in.1"], ["op_hcompute_grad_x_stencil$inner_compute$sub_277_278_279$binop.data.in.0","op_hcompute_grad_x_stencil$inner_compute$sub_276_padded16_global_wrapper_stencil_4_277$binop.data.out"], ["op_hcompute_grad_x_stencil$inner_compute$sub_279_padded16_global_wrapper_stencil_6_280$binop.data.in.0","op_hcompute_grad_x_stencil$inner_compute$sub_277_278_279$binop.data.out"], - ["padded16_global_wrapper_stencil$d_reg__U35$reg0.out","op_hcompute_grad_x_stencil$inner_compute$sub_279_padded16_global_wrapper_stencil_6_280$binop.data.in.1"], - ["padded16_global_wrapper_stencil$d_reg__U35$reg0.out","op_hcompute_grad_y_stencil$inner_compute$add_padded16_global_wrapper_stencil_7_375_376$binop.data.in.0"], + ["padded16_global_wrapper_stencil$d_reg__U30$reg0.out","op_hcompute_grad_x_stencil$inner_compute$sub_279_padded16_global_wrapper_stencil_6_280$binop.data.in.1"], + ["padded16_global_wrapper_stencil$d_reg__U30$reg0.out","op_hcompute_grad_y_stencil$inner_compute$add_padded16_global_wrapper_stencil_7_375_376$binop.data.in.0"], ["op_hcompute_grad_y_stencil$inner_compute$add_padded16_global_wrapper_stencil_8_374_375$binop.data.out","op_hcompute_grad_y_stencil$inner_compute$add_padded16_global_wrapper_stencil_7_375_376$binop.data.in.1"], ["op_hcompute_grad_y_stencil$inner_compute$sub_376_padded16_global_wrapper_stencil_10_377$binop.data.in.0","op_hcompute_grad_y_stencil$inner_compute$add_padded16_global_wrapper_stencil_7_375_376$binop.data.out"], ["op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_9_373_374$binop.data.out","op_hcompute_grad_y_stencil$inner_compute$add_padded16_global_wrapper_stencil_8_374_375$binop.data.in.1"], @@ -2305,9 +2281,9 @@ ["op_hcompute_grad_y_stencil$inner_compute$smin_380_381_382$min_mux$mux.data.in.1","op_hcompute_grad_y_stencil$inner_compute$const_p255__3811.out"], ["op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_11_373_378$binop.data.in.1","op_hcompute_grad_y_stencil$inner_compute$const_p2__373$1.out"], ["op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_9_373_374$binop.data.in.1","op_hcompute_grad_y_stencil$inner_compute$const_p2__373.out"], - ["padded16_global_wrapper_stencil$d_reg__U38$reg0.out","op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_11_373_378$binop.data.in.0"], + ["padded16_global_wrapper_stencil$d_reg__U33$reg0.out","op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_11_373_378$binop.data.in.0"], ["op_hcompute_grad_y_stencil$inner_compute$sub_377_378_379$binop.data.in.1","op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_11_373_378$binop.data.out"], - ["padded16_global_wrapper_stencil$d_reg__U34$reg0.out","op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_9_373_374$binop.data.in.0"], + ["padded16_global_wrapper_stencil$d_reg__U29$reg0.out","op_hcompute_grad_y_stencil$inner_compute$mul_padded16_global_wrapper_stencil_9_373_374$binop.data.in.0"], ["op_hcompute_grad_y_stencil$inner_compute$smin_380_381_382$min_mux$mux.data.out","op_hcompute_grad_y_stencil$inner_compute$smax_382_383_384$cgramax.data.in.0"], ["op_hcompute_lxy_stencil$inner_compute$mul_grad_x_stencil_2_grad_y_stencil_1_410$binop.data.in.1","op_hcompute_grad_y_stencil$inner_compute$smax_382_383_384$cgramax.data.out"], ["op_hcompute_lyy_stencil$inner_compute$mul_grad_y_stencil_2_grad_y_stencil_2_465$binop.data.in.0","op_hcompute_grad_y_stencil$inner_compute$smax_382_383_384$cgramax.data.out"], @@ -2315,7 +2291,7 @@ ["op_hcompute_grad_y_stencil$inner_compute$smin_380_381_382$scomp$compop.bit.out","op_hcompute_grad_y_stencil$inner_compute$smin_380_381_382$min_mux$mux.bit.in.0"], ["op_hcompute_grad_y_stencil$inner_compute$sub_379_padded16_global_wrapper_stencil_12_380$binop.data.out","op_hcompute_grad_y_stencil$inner_compute$smin_380_381_382$min_mux$mux.data.in.0"], ["op_hcompute_grad_y_stencil$inner_compute$sub_379_padded16_global_wrapper_stencil_12_380$binop.data.out","op_hcompute_grad_y_stencil$inner_compute$smin_380_381_382$scomp$compop.data.in.0"], - ["padded16_global_wrapper_stencil$d_reg__U39$reg0.out","op_hcompute_grad_y_stencil$inner_compute$sub_376_padded16_global_wrapper_stencil_10_377$binop.data.in.1"], + ["padded16_global_wrapper_stencil$d_reg__U34$reg0.out","op_hcompute_grad_y_stencil$inner_compute$sub_376_padded16_global_wrapper_stencil_10_377$binop.data.in.1"], ["op_hcompute_grad_y_stencil$inner_compute$sub_377_378_379$binop.data.in.0","op_hcompute_grad_y_stencil$inner_compute$sub_376_padded16_global_wrapper_stencil_10_377$binop.data.out"], ["op_hcompute_grad_y_stencil$inner_compute$sub_379_padded16_global_wrapper_stencil_12_380$binop.data.in.0","op_hcompute_grad_y_stencil$inner_compute$sub_377_378_379$binop.data.out"], ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_0","op_hcompute_grad_y_stencil$inner_compute$sub_379_padded16_global_wrapper_stencil_12_380$binop.data.in.1"], @@ -2356,11 +2332,11 @@ ["op_hcompute_lxy_stencil$inner_compute$const_p7__411.out","op_hcompute_lxy_stencil$inner_compute$ashr_410_411_412$binop.data.in.1"], ["op_hcompute_lyy_stencil$inner_compute$mul_grad_y_stencil_2_grad_y_stencil_2_465$binop.data.out","op_hcompute_lyy_stencil$inner_compute$ashr_465_466_467$binop.data.in.0"], ["op_hcompute_lyy_stencil$inner_compute$const_p7__466.out","op_hcompute_lyy_stencil$inner_compute$ashr_465_466_467$binop.data.in.1"], - ["padded16_global_wrapper_stencil$d_reg__U35$reg0.in","padded16_global_wrapper_stencil$d_reg__U34$reg0.out"], - ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_1","padded16_global_wrapper_stencil$d_reg__U36$reg0.in"], - ["padded16_global_wrapper_stencil$d_reg__U37$reg0.in","padded16_global_wrapper_stencil$d_reg__U36$reg0.out"], - ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_0","padded16_global_wrapper_stencil$d_reg__U38$reg0.in"], - ["padded16_global_wrapper_stencil$d_reg__U39$reg0.in","padded16_global_wrapper_stencil$d_reg__U38$reg0.out"], + ["padded16_global_wrapper_stencil$d_reg__U30$reg0.in","padded16_global_wrapper_stencil$d_reg__U29$reg0.out"], + ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_1","padded16_global_wrapper_stencil$d_reg__U31$reg0.in"], + ["padded16_global_wrapper_stencil$d_reg__U32$reg0.in","padded16_global_wrapper_stencil$d_reg__U31$reg0.out"], + ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_0","padded16_global_wrapper_stencil$d_reg__U33$reg0.in"], + ["padded16_global_wrapper_stencil$d_reg__U34$reg0.in","padded16_global_wrapper_stencil$d_reg__U33$reg0.out"], ["padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_garnet.clk_en","padded16_global_wrapper_stencil$ub_padded16_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, @@ -2896,26 +2872,26 @@ ["out_lgxx_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U60":{ + "PE_init_U55":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U58":{ + "_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U59":{ + "_U54":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U58.out","PE_init_U60.data.in.0"], - ["_U59.out","PE_init_U60.data.in.1"], - ["self.out_lgxx_stencil","PE_init_U60.data.out"] + ["_U53.out","PE_init_U55.data.in.0"], + ["_U54.out","PE_init_U55.data.in.1"], + ["self.out_lgxx_stencil","PE_init_U55.data.out"] ] }, "hcompute_lgxx_stencil_1":{ @@ -2998,26 +2974,26 @@ ["out_lgxy_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U63":{ + "PE_init_U58":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U61":{ + "_U56":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U62":{ + "_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U61.out","PE_init_U63.data.in.0"], - ["_U62.out","PE_init_U63.data.in.1"], - ["self.out_lgxy_stencil","PE_init_U63.data.out"] + ["_U56.out","PE_init_U58.data.in.0"], + ["_U57.out","PE_init_U58.data.in.1"], + ["self.out_lgxy_stencil","PE_init_U58.data.out"] ] }, "hcompute_lgxy_stencil_1":{ @@ -3100,26 +3076,26 @@ ["out_lgyy_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U66":{ + "PE_init_U61":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U64":{ + "_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U65":{ + "_U60":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U64.out","PE_init_U66.data.in.0"], - ["_U65.out","PE_init_U66.data.in.1"], - ["self.out_lgyy_stencil","PE_init_U66.data.out"] + ["_U59.out","PE_init_U61.data.in.0"], + ["_U60.out","PE_init_U61.data.in.1"], + ["self.out_lgyy_stencil","PE_init_U61.data.out"] ] }, "hcompute_lgyy_stencil_1":{ @@ -3392,10 +3368,6 @@ ["op_hcompute_lxx_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "d_reg__U10$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, @@ -3416,12 +3388,12 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U14$reg0":{ + "d_reg__U8$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U15$reg0":{ + "d_reg__U9$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -3433,29 +3405,29 @@ }, "ub_lxx_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ ["self.clk","d_reg__U10$reg0.clk"], - ["self.op_hcompute_lxx_stencil_write.0","d_reg__U10$reg0.in"], + ["ub_lxx_stencil_BANK_0_garnet.data_out_1","d_reg__U10$reg0.in"], ["d_reg__U11$reg0.in","d_reg__U10$reg0.out"], - ["self.op_hcompute_lgxx_stencil_1_read.8","d_reg__U10$reg0.out"], + ["self.op_hcompute_lgxx_stencil_1_read.4","d_reg__U10$reg0.out"], ["self.clk","d_reg__U11$reg0.clk"], - ["self.op_hcompute_lgxx_stencil_1_read.6","d_reg__U11$reg0.out"], + ["self.op_hcompute_lgxx_stencil_1_read.3","d_reg__U11$reg0.out"], ["self.clk","d_reg__U12$reg0.clk"], - ["ub_lxx_stencil_BANK_0_garnet.data_out_1","d_reg__U12$reg0.in"], + ["ub_lxx_stencil_BANK_0_garnet.data_out_0","d_reg__U12$reg0.in"], ["d_reg__U13$reg0.in","d_reg__U12$reg0.out"], - ["self.op_hcompute_lgxx_stencil_1_read.4","d_reg__U12$reg0.out"], + ["self.op_hcompute_lgxx_stencil_1_read.1","d_reg__U12$reg0.out"], ["self.clk","d_reg__U13$reg0.clk"], - ["self.op_hcompute_lgxx_stencil_1_read.3","d_reg__U13$reg0.out"], - ["self.clk","d_reg__U14$reg0.clk"], - ["ub_lxx_stencil_BANK_0_garnet.data_out_0","d_reg__U14$reg0.in"], - ["d_reg__U15$reg0.in","d_reg__U14$reg0.out"], - ["self.op_hcompute_lgxx_stencil_1_read.1","d_reg__U14$reg0.out"], - ["self.clk","d_reg__U15$reg0.clk"], - ["self.op_hcompute_lgxx_stencil_1_read.0","d_reg__U15$reg0.out"], + ["self.op_hcompute_lgxx_stencil_1_read.0","d_reg__U13$reg0.out"], + ["self.clk","d_reg__U8$reg0.clk"], + ["self.op_hcompute_lxx_stencil_write.0","d_reg__U8$reg0.in"], + ["d_reg__U9$reg0.in","d_reg__U8$reg0.out"], + ["self.op_hcompute_lgxx_stencil_1_read.8","d_reg__U8$reg0.out"], + ["self.clk","d_reg__U9$reg0.clk"], + ["self.op_hcompute_lgxx_stencil_1_read.6","d_reg__U9$reg0.out"], ["ub_lxx_stencil_BANK_0_garnet.clk","self.clk"], ["ub_lxx_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_lgxx_stencil_1_read.2"], ["ub_lxx_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_lgxx_stencil_1_read.5"], @@ -3476,36 +3448,32 @@ ["op_hcompute_lxy_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U18$reg0":{ + "d_reg__U15$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U19$reg0":{ + "d_reg__U16$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U20$reg0":{ + "d_reg__U17$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U21$reg0":{ + "d_reg__U18$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U22$reg0":{ + "d_reg__U19$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U23$reg0":{ + "d_reg__U20$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -3517,29 +3485,29 @@ }, "ub_lxy_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U15$reg0.clk"], + ["self.op_hcompute_lxy_stencil_write.0","d_reg__U15$reg0.in"], + ["d_reg__U16$reg0.in","d_reg__U15$reg0.out"], + ["self.op_hcompute_lgxy_stencil_1_read.8","d_reg__U15$reg0.out"], + ["self.clk","d_reg__U16$reg0.clk"], + ["self.op_hcompute_lgxy_stencil_1_read.6","d_reg__U16$reg0.out"], + ["self.clk","d_reg__U17$reg0.clk"], + ["ub_lxy_stencil_BANK_0_garnet.data_out_1","d_reg__U17$reg0.in"], + ["d_reg__U18$reg0.in","d_reg__U17$reg0.out"], + ["self.op_hcompute_lgxy_stencil_1_read.4","d_reg__U17$reg0.out"], ["self.clk","d_reg__U18$reg0.clk"], - ["self.op_hcompute_lxy_stencil_write.0","d_reg__U18$reg0.in"], - ["d_reg__U19$reg0.in","d_reg__U18$reg0.out"], - ["self.op_hcompute_lgxy_stencil_1_read.8","d_reg__U18$reg0.out"], + ["self.op_hcompute_lgxy_stencil_1_read.3","d_reg__U18$reg0.out"], ["self.clk","d_reg__U19$reg0.clk"], - ["self.op_hcompute_lgxy_stencil_1_read.6","d_reg__U19$reg0.out"], + ["ub_lxy_stencil_BANK_0_garnet.data_out_0","d_reg__U19$reg0.in"], + ["d_reg__U20$reg0.in","d_reg__U19$reg0.out"], + ["self.op_hcompute_lgxy_stencil_1_read.1","d_reg__U19$reg0.out"], ["self.clk","d_reg__U20$reg0.clk"], - ["ub_lxy_stencil_BANK_0_garnet.data_out_1","d_reg__U20$reg0.in"], - ["d_reg__U21$reg0.in","d_reg__U20$reg0.out"], - ["self.op_hcompute_lgxy_stencil_1_read.4","d_reg__U20$reg0.out"], - ["self.clk","d_reg__U21$reg0.clk"], - ["self.op_hcompute_lgxy_stencil_1_read.3","d_reg__U21$reg0.out"], - ["self.clk","d_reg__U22$reg0.clk"], - ["ub_lxy_stencil_BANK_0_garnet.data_out_0","d_reg__U22$reg0.in"], - ["d_reg__U23$reg0.in","d_reg__U22$reg0.out"], - ["self.op_hcompute_lgxy_stencil_1_read.1","d_reg__U22$reg0.out"], - ["self.clk","d_reg__U23$reg0.clk"], - ["self.op_hcompute_lgxy_stencil_1_read.0","d_reg__U23$reg0.out"], + ["self.op_hcompute_lgxy_stencil_1_read.0","d_reg__U20$reg0.out"], ["ub_lxy_stencil_BANK_0_garnet.clk","self.clk"], ["ub_lxy_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_lgxy_stencil_1_read.2"], ["ub_lxy_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_lgxy_stencil_1_read.5"], @@ -3560,36 +3528,32 @@ ["op_hcompute_lyy_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U26$reg0":{ + "d_reg__U22$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U27$reg0":{ + "d_reg__U23$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U28$reg0":{ + "d_reg__U24$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U29$reg0":{ + "d_reg__U25$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U30$reg0":{ + "d_reg__U26$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U31$reg0":{ + "d_reg__U27$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -3601,29 +3565,29 @@ }, "ub_lyy_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[134],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[191],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,62],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[194],"cycle_stride":[1,64],"dimensionality":2,"extent":[62,62],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U22$reg0.clk"], + ["self.op_hcompute_lyy_stencil_write.0","d_reg__U22$reg0.in"], + ["d_reg__U23$reg0.in","d_reg__U22$reg0.out"], + ["self.op_hcompute_lgyy_stencil_1_read.8","d_reg__U22$reg0.out"], + ["self.clk","d_reg__U23$reg0.clk"], + ["self.op_hcompute_lgyy_stencil_1_read.6","d_reg__U23$reg0.out"], + ["self.clk","d_reg__U24$reg0.clk"], + ["ub_lyy_stencil_BANK_0_garnet.data_out_1","d_reg__U24$reg0.in"], + ["d_reg__U25$reg0.in","d_reg__U24$reg0.out"], + ["self.op_hcompute_lgyy_stencil_1_read.4","d_reg__U24$reg0.out"], + ["self.clk","d_reg__U25$reg0.clk"], + ["self.op_hcompute_lgyy_stencil_1_read.3","d_reg__U25$reg0.out"], ["self.clk","d_reg__U26$reg0.clk"], - ["self.op_hcompute_lyy_stencil_write.0","d_reg__U26$reg0.in"], + ["ub_lyy_stencil_BANK_0_garnet.data_out_0","d_reg__U26$reg0.in"], ["d_reg__U27$reg0.in","d_reg__U26$reg0.out"], - ["self.op_hcompute_lgyy_stencil_1_read.8","d_reg__U26$reg0.out"], + ["self.op_hcompute_lgyy_stencil_1_read.1","d_reg__U26$reg0.out"], ["self.clk","d_reg__U27$reg0.clk"], - ["self.op_hcompute_lgyy_stencil_1_read.6","d_reg__U27$reg0.out"], - ["self.clk","d_reg__U28$reg0.clk"], - ["ub_lyy_stencil_BANK_0_garnet.data_out_1","d_reg__U28$reg0.in"], - ["d_reg__U29$reg0.in","d_reg__U28$reg0.out"], - ["self.op_hcompute_lgyy_stencil_1_read.4","d_reg__U28$reg0.out"], - ["self.clk","d_reg__U29$reg0.clk"], - ["self.op_hcompute_lgyy_stencil_1_read.3","d_reg__U29$reg0.out"], - ["self.clk","d_reg__U30$reg0.clk"], - ["ub_lyy_stencil_BANK_0_garnet.data_out_0","d_reg__U30$reg0.in"], - ["d_reg__U31$reg0.in","d_reg__U30$reg0.out"], - ["self.op_hcompute_lgyy_stencil_1_read.1","d_reg__U30$reg0.out"], - ["self.clk","d_reg__U31$reg0.clk"], - ["self.op_hcompute_lgyy_stencil_1_read.0","d_reg__U31$reg0.out"], + ["self.op_hcompute_lgyy_stencil_1_read.0","d_reg__U27$reg0.out"], ["ub_lyy_stencil_BANK_0_garnet.clk","self.clk"], ["ub_lyy_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_lgyy_stencil_1_read.2"], ["ub_lyy_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_lgyy_stencil_1_read.5"], @@ -3633,7 +3597,7 @@ ["ub_lyy_stencil_BANK_0_garnet.clk_en","ub_lyy_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U42":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U37":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3642,7 +3606,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U41":{ + "op_hcompute_hw_output_stencil_read_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3651,7 +3615,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U43":{ + "op_hcompute_hw_output_stencil_write_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3660,7 +3624,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_padded16_global_wrapper_stencil_exe_start_pt__U46":{ + "op_hcompute_padded16_global_wrapper_stencil_exe_start_pt__U41":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3669,7 +3633,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_padded16_global_wrapper_stencil_read_start_pt__U45":{ + "op_hcompute_padded16_global_wrapper_stencil_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3678,7 +3642,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_padded16_global_wrapper_stencil_write_start_pt__U47":{ + "op_hcompute_padded16_global_wrapper_stencil_write_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3700,36 +3664,32 @@ ["op_hcompute_padded16_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U34$reg0":{ + "d_reg__U29$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U35$reg0":{ + "d_reg__U30$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U36$reg0":{ + "d_reg__U31$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U37$reg0":{ + "d_reg__U32$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U38$reg0":{ + "d_reg__U33$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U39$reg0":{ + "d_reg__U34$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -3741,30 +3701,30 @@ }, "ub_padded16_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U29$reg0.clk"], + ["self.op_hcompute_padded16_global_wrapper_stencil_write.0","d_reg__U29$reg0.in"], + ["d_reg__U30$reg0.in","d_reg__U29$reg0.out"], + ["self.op_hcompute_grad_y_stencil_read.5","d_reg__U29$reg0.out"], + ["self.clk","d_reg__U30$reg0.clk"], + ["self.op_hcompute_grad_x_stencil_read.5","d_reg__U30$reg0.out"], + ["self.op_hcompute_grad_y_stencil_read.3","d_reg__U30$reg0.out"], + ["self.clk","d_reg__U31$reg0.clk"], + ["ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U31$reg0.in"], + ["d_reg__U32$reg0.in","d_reg__U31$reg0.out"], + ["self.clk","d_reg__U32$reg0.clk"], + ["self.op_hcompute_grad_x_stencil_read.4","d_reg__U32$reg0.out"], + ["self.clk","d_reg__U33$reg0.clk"], + ["ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U33$reg0.in"], + ["d_reg__U34$reg0.in","d_reg__U33$reg0.out"], + ["self.op_hcompute_grad_y_stencil_read.1","d_reg__U33$reg0.out"], ["self.clk","d_reg__U34$reg0.clk"], - ["self.op_hcompute_padded16_global_wrapper_stencil_write.0","d_reg__U34$reg0.in"], - ["d_reg__U35$reg0.in","d_reg__U34$reg0.out"], - ["self.op_hcompute_grad_y_stencil_read.5","d_reg__U34$reg0.out"], - ["self.clk","d_reg__U35$reg0.clk"], - ["self.op_hcompute_grad_x_stencil_read.5","d_reg__U35$reg0.out"], - ["self.op_hcompute_grad_y_stencil_read.3","d_reg__U35$reg0.out"], - ["self.clk","d_reg__U36$reg0.clk"], - ["ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_1","d_reg__U36$reg0.in"], - ["d_reg__U37$reg0.in","d_reg__U36$reg0.out"], - ["self.clk","d_reg__U37$reg0.clk"], - ["self.op_hcompute_grad_x_stencil_read.4","d_reg__U37$reg0.out"], - ["self.clk","d_reg__U38$reg0.clk"], - ["ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U38$reg0.in"], - ["d_reg__U39$reg0.in","d_reg__U38$reg0.out"], - ["self.op_hcompute_grad_y_stencil_read.1","d_reg__U38$reg0.out"], - ["self.clk","d_reg__U39$reg0.clk"], - ["self.op_hcompute_grad_x_stencil_read.3","d_reg__U39$reg0.out"], - ["self.op_hcompute_grad_y_stencil_read.0","d_reg__U39$reg0.out"], + ["self.op_hcompute_grad_x_stencil_read.3","d_reg__U34$reg0.out"], + ["self.op_hcompute_grad_y_stencil_read.0","d_reg__U34$reg0.out"], ["ub_padded16_global_wrapper_stencil_BANK_0_garnet.clk","self.clk"], ["ub_padded16_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_grad_x_stencil_read.0"], ["self.op_hcompute_padded16_global_wrapper_stencil_write.0","self.op_hcompute_grad_x_stencil_read.1"], diff --git a/aha_garnet_design_new/matmul/matmul.json b/aha_garnet_design_new/matmul/matmul.json index 4822343d3..5f9374a8f 100644 --- a/aha_garnet_design_new/matmul/matmul.json +++ b/aha_garnet_design_new/matmul/matmul.json @@ -2,1423 +2,1219 @@ "namespaces":{ "global":{ "modules":{ - "aff__U18":{ + "aff__U176":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U26":{ + "add_all__U184":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U27":{ + "add_all__U185":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U28":{ + "add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U19":{ + "coeff_0_U177":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U21":{ + "coeff_1_U179":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U23":{ + "coeff_2_U181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U25":{ + "const_term_U183":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U20":{ + "mul_d0__U178":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U22":{ + "mul_d1__U180":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U24":{ + "mul_d2__U182":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U20.out","add_all__U26.in0"], - ["mul_d1__U22.out","add_all__U26.in1"], - ["add_all__U27.in0","add_all__U26.out"], - ["mul_d2__U24.out","add_all__U27.in1"], - ["add_all__U28.in0","add_all__U27.out"], - ["const_term_U25.out","add_all__U28.in1"], - ["self.out","add_all__U28.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"] + ["mul_d0__U178.out","add_all__U184.in0"], + ["mul_d1__U180.out","add_all__U184.in1"], + ["add_all__U185.in0","add_all__U184.out"], + ["mul_d2__U182.out","add_all__U185.in1"], + ["add_all__U186.in0","add_all__U185.out"], + ["const_term_U183.out","add_all__U186.in1"], + ["self.out","add_all__U186.out"], + ["mul_d0__U178.in0","coeff_0_U177.out"], + ["mul_d1__U180.in0","coeff_1_U179.out"], + ["mul_d2__U182.in0","coeff_2_U181.out"], + ["self.d.0","mul_d0__U178.in1"], + ["self.d.1","mul_d1__U180.in1"], + ["self.d.2","mul_d2__U182.in1"] ] }, - "aff__U250":{ + "aff__U193":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U258":{ + "add_all__U201":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U259":{ + "add_all__U202":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U260":{ + "add_all__U203":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U251":{ + "coeff_0_U194":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U253":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "coeff_2_U255":{ + "coeff_1_U196":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U257":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U252":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U254":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U256":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U252.out","add_all__U258.in0"], - ["mul_d1__U254.out","add_all__U258.in1"], - ["add_all__U259.in0","add_all__U258.out"], - ["mul_d2__U256.out","add_all__U259.in1"], - ["add_all__U260.in0","add_all__U259.out"], - ["const_term_U257.out","add_all__U260.in1"], - ["self.out","add_all__U260.out"], - ["mul_d0__U252.in0","coeff_0_U251.out"], - ["mul_d1__U254.in0","coeff_1_U253.out"], - ["mul_d2__U256.in0","coeff_2_U255.out"], - ["self.d.0","mul_d0__U252.in1"], - ["self.d.1","mul_d1__U254.in1"], - ["self.d.2","mul_d2__U256.in1"] - ] - }, - "aff__U267":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",3,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U275":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U276":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U277":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U268":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U270":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_2_U272":{ + "coeff_2_U198":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U274":{ + "const_term_U200":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U269":{ + "mul_d0__U195":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U271":{ + "mul_d1__U197":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U273":{ + "mul_d2__U199":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U269.out","add_all__U275.in0"], - ["mul_d1__U271.out","add_all__U275.in1"], - ["add_all__U276.in0","add_all__U275.out"], - ["mul_d2__U273.out","add_all__U276.in1"], - ["add_all__U277.in0","add_all__U276.out"], - ["const_term_U274.out","add_all__U277.in1"], - ["self.out","add_all__U277.out"], - ["mul_d0__U269.in0","coeff_0_U268.out"], - ["mul_d1__U271.in0","coeff_1_U270.out"], - ["mul_d2__U273.in0","coeff_2_U272.out"], - ["self.d.0","mul_d0__U269.in1"], - ["self.d.1","mul_d1__U271.in1"], - ["self.d.2","mul_d2__U273.in1"] + ["mul_d0__U195.out","add_all__U201.in0"], + ["mul_d1__U197.out","add_all__U201.in1"], + ["add_all__U202.in0","add_all__U201.out"], + ["mul_d2__U199.out","add_all__U202.in1"], + ["add_all__U203.in0","add_all__U202.out"], + ["const_term_U200.out","add_all__U203.in1"], + ["self.out","add_all__U203.out"], + ["mul_d0__U195.in0","coeff_0_U194.out"], + ["mul_d1__U197.in0","coeff_1_U196.out"], + ["mul_d2__U199.in0","coeff_2_U198.out"], + ["self.d.0","mul_d0__U195.in1"], + ["self.d.1","mul_d1__U197.in1"], + ["self.d.2","mul_d2__U199.in1"] ] }, - "aff__U280":{ + "aff__U206":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U298":{ + "add_all__U224":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U299":{ + "add_all__U225":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U300":{ + "add_all__U226":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U301":{ + "add_all__U227":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U302":{ + "add_all__U228":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U303":{ + "add_all__U229":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U304":{ + "add_all__U230":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U305":{ + "add_all__U231":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U281":{ + "coeff_0_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U283":{ + "coeff_1_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004000"]} }, - "coeff_2_U285":{ + "coeff_2_U211":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U287":{ + "coeff_3_U213":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001000"]} }, - "coeff_4_U289":{ + "coeff_4_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000200"]} }, - "coeff_5_U291":{ + "coeff_5_U217":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_6_U293":{ + "coeff_6_U219":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U295":{ + "coeff_7_U221":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U297":{ + "const_term_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003fff"]} }, - "mul_d0__U282":{ + "mul_d0__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U284":{ + "mul_d1__U210":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U286":{ + "mul_d2__U212":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U288":{ + "mul_d3__U214":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U290":{ + "mul_d4__U216":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U292":{ + "mul_d5__U218":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d6__U220":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d7__U222":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U208.out","add_all__U224.in0"], + ["mul_d1__U210.out","add_all__U224.in1"], + ["add_all__U225.in0","add_all__U224.out"], + ["mul_d2__U212.out","add_all__U225.in1"], + ["add_all__U226.in0","add_all__U225.out"], + ["mul_d3__U214.out","add_all__U226.in1"], + ["add_all__U227.in0","add_all__U226.out"], + ["mul_d4__U216.out","add_all__U227.in1"], + ["add_all__U228.in0","add_all__U227.out"], + ["mul_d5__U218.out","add_all__U228.in1"], + ["add_all__U229.in0","add_all__U228.out"], + ["mul_d6__U220.out","add_all__U229.in1"], + ["add_all__U230.in0","add_all__U229.out"], + ["mul_d7__U222.out","add_all__U230.in1"], + ["add_all__U231.in0","add_all__U230.out"], + ["const_term_U223.out","add_all__U231.in1"], + ["self.out","add_all__U231.out"], + ["mul_d0__U208.in0","coeff_0_U207.out"], + ["mul_d1__U210.in0","coeff_1_U209.out"], + ["mul_d2__U212.in0","coeff_2_U211.out"], + ["mul_d3__U214.in0","coeff_3_U213.out"], + ["mul_d4__U216.in0","coeff_4_U215.out"], + ["mul_d5__U218.in0","coeff_5_U217.out"], + ["mul_d6__U220.in0","coeff_6_U219.out"], + ["mul_d7__U222.in0","coeff_7_U221.out"], + ["self.d.0","mul_d0__U208.in1"], + ["self.d.1","mul_d1__U210.in1"], + ["self.d.2","mul_d2__U212.in1"], + ["self.d.3","mul_d3__U214.in1"], + ["self.d.4","mul_d4__U216.in1"], + ["self.d.5","mul_d5__U218.in1"], + ["self.d.6","mul_d6__U220.in1"], + ["self.d.7","mul_d7__U222.in1"] + ] + }, + "aff__U26":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",3,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U34":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U35":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U36":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "coeff_2_U31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "const_term_U33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U28":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U294":{ + "mul_d1__U30":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U296":{ + "mul_d2__U32":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U282.out","add_all__U298.in0"], - ["mul_d1__U284.out","add_all__U298.in1"], - ["add_all__U299.in0","add_all__U298.out"], - ["mul_d2__U286.out","add_all__U299.in1"], - ["add_all__U300.in0","add_all__U299.out"], - ["mul_d3__U288.out","add_all__U300.in1"], - ["add_all__U301.in0","add_all__U300.out"], - ["mul_d4__U290.out","add_all__U301.in1"], - ["add_all__U302.in0","add_all__U301.out"], - ["mul_d5__U292.out","add_all__U302.in1"], - ["add_all__U303.in0","add_all__U302.out"], - ["mul_d6__U294.out","add_all__U303.in1"], - ["add_all__U304.in0","add_all__U303.out"], - ["mul_d7__U296.out","add_all__U304.in1"], - ["add_all__U305.in0","add_all__U304.out"], - ["const_term_U297.out","add_all__U305.in1"], - ["self.out","add_all__U305.out"], - ["mul_d0__U282.in0","coeff_0_U281.out"], - ["mul_d1__U284.in0","coeff_1_U283.out"], - ["mul_d2__U286.in0","coeff_2_U285.out"], - ["mul_d3__U288.in0","coeff_3_U287.out"], - ["mul_d4__U290.in0","coeff_4_U289.out"], - ["mul_d5__U292.in0","coeff_5_U291.out"], - ["mul_d6__U294.in0","coeff_6_U293.out"], - ["mul_d7__U296.in0","coeff_7_U295.out"], - ["self.d.0","mul_d0__U282.in1"], - ["self.d.1","mul_d1__U284.in1"], - ["self.d.2","mul_d2__U286.in1"], - ["self.d.3","mul_d3__U288.in1"], - ["self.d.4","mul_d4__U290.in1"], - ["self.d.5","mul_d5__U292.in1"], - ["self.d.6","mul_d6__U294.in1"], - ["self.d.7","mul_d7__U296.in1"] + ["mul_d0__U28.out","add_all__U34.in0"], + ["mul_d1__U30.out","add_all__U34.in1"], + ["add_all__U35.in0","add_all__U34.out"], + ["mul_d2__U32.out","add_all__U35.in1"], + ["add_all__U36.in0","add_all__U35.out"], + ["const_term_U33.out","add_all__U36.in1"], + ["self.out","add_all__U36.out"], + ["mul_d0__U28.in0","coeff_0_U27.out"], + ["mul_d1__U30.in0","coeff_1_U29.out"], + ["mul_d2__U32.in0","coeff_2_U31.out"], + ["self.d.0","mul_d0__U28.in1"], + ["self.d.1","mul_d1__U30.in1"], + ["self.d.2","mul_d2__U32.in1"] ] }, - "aff__U337":{ + "aff__U263":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U355":{ + "add_all__U281":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U356":{ + "add_all__U282":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U357":{ + "add_all__U283":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U358":{ + "add_all__U284":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U359":{ + "add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U360":{ + "add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U361":{ + "add_all__U287":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U362":{ + "add_all__U288":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U338":{ + "coeff_0_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U340":{ + "coeff_1_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U342":{ + "coeff_2_U268":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U344":{ + "coeff_3_U270":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U346":{ + "coeff_4_U272":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U348":{ + "coeff_5_U274":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U350":{ + "coeff_6_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_7_U352":{ + "coeff_7_U278":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U354":{ + "const_term_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U339":{ + "mul_d0__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U341":{ + "mul_d1__U267":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U343":{ + "mul_d2__U269":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U345":{ + "mul_d3__U271":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U347":{ + "mul_d4__U273":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U349":{ + "mul_d5__U275":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U351":{ + "mul_d6__U277":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U353":{ + "mul_d7__U279":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U339.out","add_all__U355.in0"], - ["mul_d1__U341.out","add_all__U355.in1"], - ["add_all__U356.in0","add_all__U355.out"], - ["mul_d2__U343.out","add_all__U356.in1"], - ["add_all__U357.in0","add_all__U356.out"], - ["mul_d3__U345.out","add_all__U357.in1"], - ["add_all__U358.in0","add_all__U357.out"], - ["mul_d4__U347.out","add_all__U358.in1"], - ["add_all__U359.in0","add_all__U358.out"], - ["mul_d5__U349.out","add_all__U359.in1"], - ["add_all__U360.in0","add_all__U359.out"], - ["mul_d6__U351.out","add_all__U360.in1"], - ["add_all__U361.in0","add_all__U360.out"], - ["mul_d7__U353.out","add_all__U361.in1"], - ["add_all__U362.in0","add_all__U361.out"], - ["const_term_U354.out","add_all__U362.in1"], - ["self.out","add_all__U362.out"], - ["mul_d0__U339.in0","coeff_0_U338.out"], - ["mul_d1__U341.in0","coeff_1_U340.out"], - ["mul_d2__U343.in0","coeff_2_U342.out"], - ["mul_d3__U345.in0","coeff_3_U344.out"], - ["mul_d4__U347.in0","coeff_4_U346.out"], - ["mul_d5__U349.in0","coeff_5_U348.out"], - ["mul_d6__U351.in0","coeff_6_U350.out"], - ["mul_d7__U353.in0","coeff_7_U352.out"], - ["self.d.0","mul_d0__U339.in1"], - ["self.d.1","mul_d1__U341.in1"], - ["self.d.2","mul_d2__U343.in1"], - ["self.d.3","mul_d3__U345.in1"], - ["self.d.4","mul_d4__U347.in1"], - ["self.d.5","mul_d5__U349.in1"], - ["self.d.6","mul_d6__U351.in1"], - ["self.d.7","mul_d7__U353.in1"] + ["mul_d0__U265.out","add_all__U281.in0"], + ["mul_d1__U267.out","add_all__U281.in1"], + ["add_all__U282.in0","add_all__U281.out"], + ["mul_d2__U269.out","add_all__U282.in1"], + ["add_all__U283.in0","add_all__U282.out"], + ["mul_d3__U271.out","add_all__U283.in1"], + ["add_all__U284.in0","add_all__U283.out"], + ["mul_d4__U273.out","add_all__U284.in1"], + ["add_all__U285.in0","add_all__U284.out"], + ["mul_d5__U275.out","add_all__U285.in1"], + ["add_all__U286.in0","add_all__U285.out"], + ["mul_d6__U277.out","add_all__U286.in1"], + ["add_all__U287.in0","add_all__U286.out"], + ["mul_d7__U279.out","add_all__U287.in1"], + ["add_all__U288.in0","add_all__U287.out"], + ["const_term_U280.out","add_all__U288.in1"], + ["self.out","add_all__U288.out"], + ["mul_d0__U265.in0","coeff_0_U264.out"], + ["mul_d1__U267.in0","coeff_1_U266.out"], + ["mul_d2__U269.in0","coeff_2_U268.out"], + ["mul_d3__U271.in0","coeff_3_U270.out"], + ["mul_d4__U273.in0","coeff_4_U272.out"], + ["mul_d5__U275.in0","coeff_5_U274.out"], + ["mul_d6__U277.in0","coeff_6_U276.out"], + ["mul_d7__U279.in0","coeff_7_U278.out"], + ["self.d.0","mul_d0__U265.in1"], + ["self.d.1","mul_d1__U267.in1"], + ["self.d.2","mul_d2__U269.in1"], + ["self.d.3","mul_d3__U271.in1"], + ["self.d.4","mul_d4__U273.in1"], + ["self.d.5","mul_d5__U275.in1"], + ["self.d.6","mul_d6__U277.in1"], + ["self.d.7","mul_d7__U279.in1"] ] }, - "aff__U35":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",3,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U43":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U44":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U45":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U36":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U38":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_2_U40":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "const_term_U42":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U37":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U39":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U41":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U37.out","add_all__U43.in0"], - ["mul_d1__U39.out","add_all__U43.in1"], - ["add_all__U44.in0","add_all__U43.out"], - ["mul_d2__U41.out","add_all__U44.in1"], - ["add_all__U45.in0","add_all__U44.out"], - ["const_term_U42.out","add_all__U45.in1"], - ["self.out","add_all__U45.out"], - ["mul_d0__U37.in0","coeff_0_U36.out"], - ["mul_d1__U39.in0","coeff_1_U38.out"], - ["mul_d2__U41.in0","coeff_2_U40.out"], - ["self.d.0","mul_d0__U37.in1"], - ["self.d.1","mul_d1__U39.in1"], - ["self.d.2","mul_d2__U41.in1"] - ] - }, - "aff__U383":{ + "aff__U300":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U397":{ + "add_all__U314":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U398":{ + "add_all__U315":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U399":{ + "add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U400":{ + "add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U401":{ + "add_all__U318":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U402":{ + "add_all__U319":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U384":{ + "coeff_0_U301":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U386":{ + "coeff_1_U303":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004000"]} }, - "coeff_2_U388":{ + "coeff_2_U305":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U390":{ + "coeff_3_U307":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U392":{ + "coeff_4_U309":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U394":{ + "coeff_5_U311":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U396":{ + "const_term_U313":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007000"]} }, - "mul_d0__U385":{ + "mul_d0__U302":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U387":{ + "mul_d1__U304":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U389":{ + "mul_d2__U306":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U391":{ + "mul_d3__U308":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U393":{ + "mul_d4__U310":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U395":{ + "mul_d5__U312":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U385.out","add_all__U397.in0"], - ["mul_d1__U387.out","add_all__U397.in1"], - ["add_all__U398.in0","add_all__U397.out"], - ["mul_d2__U389.out","add_all__U398.in1"], - ["add_all__U399.in0","add_all__U398.out"], - ["mul_d3__U391.out","add_all__U399.in1"], - ["add_all__U400.in0","add_all__U399.out"], - ["mul_d4__U393.out","add_all__U400.in1"], - ["add_all__U401.in0","add_all__U400.out"], - ["mul_d5__U395.out","add_all__U401.in1"], - ["add_all__U402.in0","add_all__U401.out"], - ["const_term_U396.out","add_all__U402.in1"], - ["self.out","add_all__U402.out"], - ["mul_d0__U385.in0","coeff_0_U384.out"], - ["mul_d1__U387.in0","coeff_1_U386.out"], - ["mul_d2__U389.in0","coeff_2_U388.out"], - ["mul_d3__U391.in0","coeff_3_U390.out"], - ["mul_d4__U393.in0","coeff_4_U392.out"], - ["mul_d5__U395.in0","coeff_5_U394.out"], - ["self.d.0","mul_d0__U385.in1"], - ["self.d.1","mul_d1__U387.in1"], - ["self.d.2","mul_d2__U389.in1"], - ["self.d.3","mul_d3__U391.in1"], - ["self.d.4","mul_d4__U393.in1"], - ["self.d.5","mul_d5__U395.in1"] + ["mul_d0__U302.out","add_all__U314.in0"], + ["mul_d1__U304.out","add_all__U314.in1"], + ["add_all__U315.in0","add_all__U314.out"], + ["mul_d2__U306.out","add_all__U315.in1"], + ["add_all__U316.in0","add_all__U315.out"], + ["mul_d3__U308.out","add_all__U316.in1"], + ["add_all__U317.in0","add_all__U316.out"], + ["mul_d4__U310.out","add_all__U317.in1"], + ["add_all__U318.in0","add_all__U317.out"], + ["mul_d5__U312.out","add_all__U318.in1"], + ["add_all__U319.in0","add_all__U318.out"], + ["const_term_U313.out","add_all__U319.in1"], + ["self.out","add_all__U319.out"], + ["mul_d0__U302.in0","coeff_0_U301.out"], + ["mul_d1__U304.in0","coeff_1_U303.out"], + ["mul_d2__U306.in0","coeff_2_U305.out"], + ["mul_d3__U308.in0","coeff_3_U307.out"], + ["mul_d4__U310.in0","coeff_4_U309.out"], + ["mul_d5__U312.in0","coeff_5_U311.out"], + ["self.d.0","mul_d0__U302.in1"], + ["self.d.1","mul_d1__U304.in1"], + ["self.d.2","mul_d2__U306.in1"], + ["self.d.3","mul_d3__U308.in1"], + ["self.d.4","mul_d4__U310.in1"], + ["self.d.5","mul_d5__U312.in1"] ] }, - "aff__U421":{ + "aff__U338":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U435":{ + "add_all__U352":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U436":{ + "add_all__U353":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U437":{ + "add_all__U354":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U438":{ + "add_all__U355":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U439":{ + "add_all__U356":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U440":{ + "add_all__U357":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U422":{ + "coeff_0_U339":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U424":{ + "coeff_1_U341":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_2_U426":{ + "coeff_2_U343":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U428":{ + "coeff_3_U345":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U430":{ + "coeff_4_U347":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_5_U432":{ + "coeff_5_U349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U434":{ + "const_term_U351":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U423":{ + "mul_d0__U340":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U425":{ + "mul_d1__U342":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U427":{ + "mul_d2__U344":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U429":{ + "mul_d3__U346":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U431":{ + "mul_d4__U348":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U433":{ + "mul_d5__U350":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U423.out","add_all__U435.in0"], - ["mul_d1__U425.out","add_all__U435.in1"], - ["add_all__U436.in0","add_all__U435.out"], - ["mul_d2__U427.out","add_all__U436.in1"], - ["add_all__U437.in0","add_all__U436.out"], - ["mul_d3__U429.out","add_all__U437.in1"], - ["add_all__U438.in0","add_all__U437.out"], - ["mul_d4__U431.out","add_all__U438.in1"], - ["add_all__U439.in0","add_all__U438.out"], - ["mul_d5__U433.out","add_all__U439.in1"], - ["add_all__U440.in0","add_all__U439.out"], - ["const_term_U434.out","add_all__U440.in1"], - ["self.out","add_all__U440.out"], - ["mul_d0__U423.in0","coeff_0_U422.out"], - ["mul_d1__U425.in0","coeff_1_U424.out"], - ["mul_d2__U427.in0","coeff_2_U426.out"], - ["mul_d3__U429.in0","coeff_3_U428.out"], - ["mul_d4__U431.in0","coeff_4_U430.out"], - ["mul_d5__U433.in0","coeff_5_U432.out"], - ["self.d.0","mul_d0__U423.in1"], - ["self.d.1","mul_d1__U425.in1"], - ["self.d.2","mul_d2__U427.in1"], - ["self.d.3","mul_d3__U429.in1"], - ["self.d.4","mul_d4__U431.in1"], - ["self.d.5","mul_d5__U433.in1"] + ["mul_d0__U340.out","add_all__U352.in0"], + ["mul_d1__U342.out","add_all__U352.in1"], + ["add_all__U353.in0","add_all__U352.out"], + ["mul_d2__U344.out","add_all__U353.in1"], + ["add_all__U354.in0","add_all__U353.out"], + ["mul_d3__U346.out","add_all__U354.in1"], + ["add_all__U355.in0","add_all__U354.out"], + ["mul_d4__U348.out","add_all__U355.in1"], + ["add_all__U356.in0","add_all__U355.out"], + ["mul_d5__U350.out","add_all__U356.in1"], + ["add_all__U357.in0","add_all__U356.out"], + ["const_term_U351.out","add_all__U357.in1"], + ["self.out","add_all__U357.out"], + ["mul_d0__U340.in0","coeff_0_U339.out"], + ["mul_d1__U342.in0","coeff_1_U341.out"], + ["mul_d2__U344.in0","coeff_2_U343.out"], + ["mul_d3__U346.in0","coeff_3_U345.out"], + ["mul_d4__U348.in0","coeff_4_U347.out"], + ["mul_d5__U350.in0","coeff_5_U349.out"], + ["self.d.0","mul_d0__U340.in1"], + ["self.d.1","mul_d1__U342.in1"], + ["self.d.2","mul_d2__U344.in1"], + ["self.d.3","mul_d3__U346.in1"], + ["self.d.4","mul_d4__U348.in1"], + ["self.d.5","mul_d5__U350.in1"] ] }, - "aff__U443":{ + "aff__U360":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U453":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U444":{ + "coeff_0_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U446":{ + "coeff_1_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U448":{ + "coeff_2_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U450":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000dfff"]} }, - "mul_d0__U445":{ + "mul_d0__U362":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U447":{ + "mul_d1__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U449":{ + "mul_d2__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U445.out","add_all__U451.in0"], - ["mul_d1__U447.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["mul_d2__U449.out","add_all__U452.in1"], - ["add_all__U453.in0","add_all__U452.out"], - ["const_term_U450.out","add_all__U453.in1"], - ["self.out","add_all__U453.out"], - ["mul_d0__U445.in0","coeff_0_U444.out"], - ["mul_d1__U447.in0","coeff_1_U446.out"], - ["mul_d2__U449.in0","coeff_2_U448.out"], - ["self.d.0","mul_d0__U445.in1"], - ["self.d.1","mul_d1__U447.in1"], - ["self.d.2","mul_d2__U449.in1"] + ["mul_d0__U362.out","add_all__U368.in0"], + ["mul_d1__U364.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["mul_d2__U366.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["const_term_U367.out","add_all__U370.in1"], + ["self.out","add_all__U370.out"], + ["mul_d0__U362.in0","coeff_0_U361.out"], + ["mul_d1__U364.in0","coeff_1_U363.out"], + ["mul_d2__U366.in0","coeff_2_U365.out"], + ["self.d.0","mul_d0__U362.in1"], + ["self.d.1","mul_d1__U364.in1"], + ["self.d.2","mul_d2__U366.in1"] ] }, - "aff__U460":{ + "aff__U377":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U468":{ + "add_all__U385":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U469":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U470":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U461":{ + "coeff_0_U378":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U463":{ + "coeff_1_U380":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U465":{ + "coeff_2_U382":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U467":{ + "const_term_U384":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U462":{ + "mul_d0__U379":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U464":{ + "mul_d1__U381":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U466":{ + "mul_d2__U383":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U462.out","add_all__U468.in0"], - ["mul_d1__U464.out","add_all__U468.in1"], - ["add_all__U469.in0","add_all__U468.out"], - ["mul_d2__U466.out","add_all__U469.in1"], - ["add_all__U470.in0","add_all__U469.out"], - ["const_term_U467.out","add_all__U470.in1"], - ["self.out","add_all__U470.out"], - ["mul_d0__U462.in0","coeff_0_U461.out"], - ["mul_d1__U464.in0","coeff_1_U463.out"], - ["mul_d2__U466.in0","coeff_2_U465.out"], - ["self.d.0","mul_d0__U462.in1"], - ["self.d.1","mul_d1__U464.in1"], - ["self.d.2","mul_d2__U466.in1"] + ["mul_d0__U379.out","add_all__U385.in0"], + ["mul_d1__U381.out","add_all__U385.in1"], + ["add_all__U386.in0","add_all__U385.out"], + ["mul_d2__U383.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["const_term_U384.out","add_all__U387.in1"], + ["self.out","add_all__U387.out"], + ["mul_d0__U379.in0","coeff_0_U378.out"], + ["mul_d1__U381.in0","coeff_1_U380.out"], + ["mul_d2__U383.in0","coeff_2_U382.out"], + ["self.d.0","mul_d0__U379.in1"], + ["self.d.1","mul_d1__U381.in1"], + ["self.d.2","mul_d2__U383.in1"] ] }, - "aff__U48":{ + "aff__U39":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U64":{ + "add_all__U55":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U65":{ + "add_all__U56":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U66":{ + "add_all__U57":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U67":{ + "add_all__U58":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U68":{ + "add_all__U59":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U69":{ + "add_all__U60":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U70":{ + "add_all__U61":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U49":{ + "coeff_0_U40":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U51":{ + "coeff_1_U42":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004000"]} }, - "coeff_2_U53":{ + "coeff_2_U44":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U55":{ + "coeff_3_U46":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001000"]} }, - "coeff_4_U57":{ + "coeff_4_U48":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_5_U59":{ + "coeff_5_U50":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_6_U61":{ + "coeff_6_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U63":{ + "const_term_U54":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003fff"]} }, - "mul_d0__U50":{ + "mul_d0__U41":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U52":{ + "mul_d1__U43":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U54":{ + "mul_d2__U45":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U56":{ + "mul_d3__U47":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U58":{ + "mul_d4__U49":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U60":{ + "mul_d5__U51":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U62":{ + "mul_d6__U53":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U50.out","add_all__U64.in0"], - ["mul_d1__U52.out","add_all__U64.in1"], - ["add_all__U65.in0","add_all__U64.out"], - ["mul_d2__U54.out","add_all__U65.in1"], - ["add_all__U66.in0","add_all__U65.out"], - ["mul_d3__U56.out","add_all__U66.in1"], - ["add_all__U67.in0","add_all__U66.out"], - ["mul_d4__U58.out","add_all__U67.in1"], - ["add_all__U68.in0","add_all__U67.out"], - ["mul_d5__U60.out","add_all__U68.in1"], - ["add_all__U69.in0","add_all__U68.out"], - ["mul_d6__U62.out","add_all__U69.in1"], - ["add_all__U70.in0","add_all__U69.out"], - ["const_term_U63.out","add_all__U70.in1"], - ["self.out","add_all__U70.out"], - ["mul_d0__U50.in0","coeff_0_U49.out"], - ["mul_d1__U52.in0","coeff_1_U51.out"], - ["mul_d2__U54.in0","coeff_2_U53.out"], - ["mul_d3__U56.in0","coeff_3_U55.out"], - ["mul_d4__U58.in0","coeff_4_U57.out"], - ["mul_d5__U60.in0","coeff_5_U59.out"], - ["mul_d6__U62.in0","coeff_6_U61.out"], - ["self.d.0","mul_d0__U50.in1"], - ["self.d.1","mul_d1__U52.in1"], - ["self.d.2","mul_d2__U54.in1"], - ["self.d.3","mul_d3__U56.in1"], - ["self.d.4","mul_d4__U58.in1"], - ["self.d.5","mul_d5__U60.in1"], - ["self.d.6","mul_d6__U62.in1"] + ["mul_d0__U41.out","add_all__U55.in0"], + ["mul_d1__U43.out","add_all__U55.in1"], + ["add_all__U56.in0","add_all__U55.out"], + ["mul_d2__U45.out","add_all__U56.in1"], + ["add_all__U57.in0","add_all__U56.out"], + ["mul_d3__U47.out","add_all__U57.in1"], + ["add_all__U58.in0","add_all__U57.out"], + ["mul_d4__U49.out","add_all__U58.in1"], + ["add_all__U59.in0","add_all__U58.out"], + ["mul_d5__U51.out","add_all__U59.in1"], + ["add_all__U60.in0","add_all__U59.out"], + ["mul_d6__U53.out","add_all__U60.in1"], + ["add_all__U61.in0","add_all__U60.out"], + ["const_term_U54.out","add_all__U61.in1"], + ["self.out","add_all__U61.out"], + ["mul_d0__U41.in0","coeff_0_U40.out"], + ["mul_d1__U43.in0","coeff_1_U42.out"], + ["mul_d2__U45.in0","coeff_2_U44.out"], + ["mul_d3__U47.in0","coeff_3_U46.out"], + ["mul_d4__U49.in0","coeff_4_U48.out"], + ["mul_d5__U51.in0","coeff_5_U50.out"], + ["mul_d6__U53.in0","coeff_6_U52.out"], + ["self.d.0","mul_d0__U41.in1"], + ["self.d.1","mul_d1__U43.in1"], + ["self.d.2","mul_d2__U45.in1"], + ["self.d.3","mul_d3__U47.in1"], + ["self.d.4","mul_d4__U49.in1"], + ["self.d.5","mul_d5__U51.in1"], + ["self.d.6","mul_d6__U53.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U115":{ + "add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U116":{ + "add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U117":{ + "add_all__U108":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_6_U108":{ + "coeff_6_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U110":{ + "const_term_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U101":{ + "mul_d2__U92":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d3__U94":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d5__U98":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U109":{ + "mul_d6__U100":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U111.in0"], - ["mul_d1__U99.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d2__U101.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d3__U103.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["mul_d4__U105.out","add_all__U114.in1"], - ["add_all__U115.in0","add_all__U114.out"], - ["mul_d5__U107.out","add_all__U115.in1"], - ["add_all__U116.in0","add_all__U115.out"], - ["mul_d6__U109.out","add_all__U116.in1"], - ["add_all__U117.in0","add_all__U116.out"], - ["const_term_U110.out","add_all__U117.in1"], - ["self.out","add_all__U117.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["mul_d6__U109.in0","coeff_6_U108.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"], - ["self.d.6","mul_d6__U109.in1"] + ["mul_d0__U88.out","add_all__U102.in0"], + ["mul_d1__U90.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d2__U92.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d3__U94.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["mul_d4__U96.out","add_all__U105.in1"], + ["add_all__U106.in0","add_all__U105.out"], + ["mul_d5__U98.out","add_all__U106.in1"], + ["add_all__U107.in0","add_all__U106.out"], + ["mul_d6__U100.out","add_all__U107.in1"], + ["add_all__U108.in0","add_all__U107.out"], + ["const_term_U101.out","add_all__U108.in1"], + ["self.out","add_all__U108.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["mul_d6__U100.in0","coeff_6_U99.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"], + ["self.d.6","mul_d6__U100.in1"] ] }, - "affine_controller__U17":{ + "aff__U9":{ "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",3,["Array",32,"Bit"]]], - ["rst_n","BitIn"] + ["out",["Array",32,"Bit"]], + ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "_U29":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U30":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U18" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U31":{ - "modref":"corebit.and" - }, - "d_0_am__U32":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ + "add_all__U17":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U33":{ - "modref":"corebit.and" - }, - "d_1_at_max":{ - "genref":"coreir.eq", + "add_all__U18":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_min":{ + "coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "d_2_max":{ + "coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_min":{ + "const_term_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ - "genref":"coreir.mux", + "mul_d0__U11":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", + "mul_d1__U13":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", + "mul_d2__U15":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} } }, "connections":[ - ["d_0_inc.in1","_U29.out"], - ["d_1_inc.in1","_U29.out"], - ["d_2_inc.in1","_U29.out"], - ["cmp_time.in1","_U30.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U31.in0"], - ["d_1_at_max.out","d_0_am__U31.in1"], - ["d_0_am__U32.in0","d_0_am__U31.out"], - ["d_2_at_max.out","d_0_am__U32.in1"], - ["d_0_next_value.sel","d_0_am__U32.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U33.in0"], - ["d_2_at_max.out","d_1_am__U33.in1"], - ["d_1_next_value.sel","d_1_am__U33.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["true.out","d_2_next_value.sel"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"] + ["mul_d0__U11.out","add_all__U17.in0"], + ["mul_d1__U13.out","add_all__U17.in1"], + ["add_all__U18.in0","add_all__U17.out"], + ["mul_d2__U15.out","add_all__U18.in1"], + ["add_all__U19.in0","add_all__U18.out"], + ["const_term_U16.out","add_all__U19.in1"], + ["self.out","add_all__U19.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"] ] }, - "affine_controller__U249":{ + "affine_controller__U175":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1426,18 +1222,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U261":{ + "_U187":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U262":{ + "_U188":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U250" + "modref":"global.aff__U176" }, "cmp_time":{ "genref":"coreir.eq", @@ -1447,10 +1243,10 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U263":{ + "d_0_am__U189":{ "modref":"corebit.and" }, - "d_0_am__U264":{ + "d_0_am__U190":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1484,7 +1280,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U265":{ + "d_1_am__U191":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1559,10 +1355,10 @@ } }, "connections":[ - ["d_0_inc.in1","_U261.out"], - ["d_1_inc.in1","_U261.out"], - ["d_2_inc.in1","_U261.out"], - ["cmp_time.in1","_U262.out"], + ["d_0_inc.in1","_U187.out"], + ["d_1_inc.in1","_U187.out"], + ["d_2_inc.in1","_U187.out"], + ["cmp_time.in1","_U188.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -1575,11 +1371,11 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U263.in0"], - ["d_1_at_max.out","d_0_am__U263.in1"], - ["d_0_am__U264.in0","d_0_am__U263.out"], - ["d_2_at_max.out","d_0_am__U264.in1"], - ["d_0_next_value.sel","d_0_am__U264.out"], + ["true.out","d_0_am__U189.in0"], + ["d_1_at_max.out","d_0_am__U189.in1"], + ["d_0_am__U190.in0","d_0_am__U189.out"], + ["d_2_at_max.out","d_0_am__U190.in1"], + ["d_0_next_value.sel","d_0_am__U190.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1592,9 +1388,9 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U265.in0"], - ["d_2_at_max.out","d_1_am__U265.in1"], - ["d_1_next_value.sel","d_1_am__U265.out"], + ["true.out","d_1_am__U191.in0"], + ["d_2_at_max.out","d_1_am__U191.in1"], + ["d_1_next_value.sel","d_1_am__U191.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1622,7 +1418,7 @@ ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U279":{ + "affine_controller__U205":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1630,18 +1426,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U306":{ + "_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U307":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U280" + "modref":"global.aff__U206" }, "cmp_time":{ "genref":"coreir.eq", @@ -1651,25 +1447,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U308":{ + "d_0_am__U234":{ "modref":"corebit.and" }, - "d_0_am__U309":{ + "d_0_am__U235":{ "modref":"corebit.and" }, - "d_0_am__U310":{ + "d_0_am__U236":{ "modref":"corebit.and" }, - "d_0_am__U311":{ + "d_0_am__U237":{ "modref":"corebit.and" }, - "d_0_am__U312":{ + "d_0_am__U238":{ "modref":"corebit.and" }, - "d_0_am__U313":{ + "d_0_am__U239":{ "modref":"corebit.and" }, - "d_0_am__U314":{ + "d_0_am__U240":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1703,22 +1499,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U315":{ + "d_1_am__U241":{ "modref":"corebit.and" }, - "d_1_am__U316":{ + "d_1_am__U242":{ "modref":"corebit.and" }, - "d_1_am__U317":{ + "d_1_am__U243":{ "modref":"corebit.and" }, - "d_1_am__U318":{ + "d_1_am__U244":{ "modref":"corebit.and" }, - "d_1_am__U319":{ + "d_1_am__U245":{ "modref":"corebit.and" }, - "d_1_am__U320":{ + "d_1_am__U246":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1752,19 +1548,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U321":{ + "d_2_am__U247":{ "modref":"corebit.and" }, - "d_2_am__U322":{ + "d_2_am__U248":{ "modref":"corebit.and" }, - "d_2_am__U323":{ + "d_2_am__U249":{ "modref":"corebit.and" }, - "d_2_am__U324":{ + "d_2_am__U250":{ "modref":"corebit.and" }, - "d_2_am__U325":{ + "d_2_am__U251":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -1798,16 +1594,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U326":{ + "d_3_am__U252":{ "modref":"corebit.and" }, - "d_3_am__U327":{ + "d_3_am__U253":{ "modref":"corebit.and" }, - "d_3_am__U328":{ + "d_3_am__U254":{ "modref":"corebit.and" }, - "d_3_am__U329":{ + "d_3_am__U255":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -1841,13 +1637,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U330":{ + "d_4_am__U256":{ "modref":"corebit.and" }, - "d_4_am__U331":{ + "d_4_am__U257":{ "modref":"corebit.and" }, - "d_4_am__U332":{ + "d_4_am__U258":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -1881,10 +1677,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U333":{ + "d_5_am__U259":{ "modref":"corebit.and" }, - "d_5_am__U334":{ + "d_5_am__U260":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -1918,7 +1714,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U335":{ + "d_6_am__U261":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -1993,15 +1789,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U306.out"], - ["d_1_inc.in1","_U306.out"], - ["d_2_inc.in1","_U306.out"], - ["d_3_inc.in1","_U306.out"], - ["d_4_inc.in1","_U306.out"], - ["d_5_inc.in1","_U306.out"], - ["d_6_inc.in1","_U306.out"], - ["d_7_inc.in1","_U306.out"], - ["cmp_time.in1","_U307.out"], + ["d_0_inc.in1","_U232.out"], + ["d_1_inc.in1","_U232.out"], + ["d_2_inc.in1","_U232.out"], + ["d_3_inc.in1","_U232.out"], + ["d_4_inc.in1","_U232.out"], + ["d_5_inc.in1","_U232.out"], + ["d_6_inc.in1","_U232.out"], + ["d_7_inc.in1","_U232.out"], + ["cmp_time.in1","_U233.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2024,21 +1820,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U308.in0"], - ["d_1_at_max.out","d_0_am__U308.in1"], - ["d_0_am__U309.in0","d_0_am__U308.out"], - ["d_2_at_max.out","d_0_am__U309.in1"], - ["d_0_am__U310.in0","d_0_am__U309.out"], - ["d_3_at_max.out","d_0_am__U310.in1"], - ["d_0_am__U311.in0","d_0_am__U310.out"], - ["d_4_at_max.out","d_0_am__U311.in1"], - ["d_0_am__U312.in0","d_0_am__U311.out"], - ["d_5_at_max.out","d_0_am__U312.in1"], - ["d_0_am__U313.in0","d_0_am__U312.out"], - ["d_6_at_max.out","d_0_am__U313.in1"], - ["d_0_am__U314.in0","d_0_am__U313.out"], - ["d_7_at_max.out","d_0_am__U314.in1"], - ["d_0_next_value.sel","d_0_am__U314.out"], + ["true.out","d_0_am__U234.in0"], + ["d_1_at_max.out","d_0_am__U234.in1"], + ["d_0_am__U235.in0","d_0_am__U234.out"], + ["d_2_at_max.out","d_0_am__U235.in1"], + ["d_0_am__U236.in0","d_0_am__U235.out"], + ["d_3_at_max.out","d_0_am__U236.in1"], + ["d_0_am__U237.in0","d_0_am__U236.out"], + ["d_4_at_max.out","d_0_am__U237.in1"], + ["d_0_am__U238.in0","d_0_am__U237.out"], + ["d_5_at_max.out","d_0_am__U238.in1"], + ["d_0_am__U239.in0","d_0_am__U238.out"], + ["d_6_at_max.out","d_0_am__U239.in1"], + ["d_0_am__U240.in0","d_0_am__U239.out"], + ["d_7_at_max.out","d_0_am__U240.in1"], + ["d_0_next_value.sel","d_0_am__U240.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2051,19 +1847,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U315.in0"], - ["d_2_at_max.out","d_1_am__U315.in1"], - ["d_1_am__U316.in0","d_1_am__U315.out"], - ["d_3_at_max.out","d_1_am__U316.in1"], - ["d_1_am__U317.in0","d_1_am__U316.out"], - ["d_4_at_max.out","d_1_am__U317.in1"], - ["d_1_am__U318.in0","d_1_am__U317.out"], - ["d_5_at_max.out","d_1_am__U318.in1"], - ["d_1_am__U319.in0","d_1_am__U318.out"], - ["d_6_at_max.out","d_1_am__U319.in1"], - ["d_1_am__U320.in0","d_1_am__U319.out"], - ["d_7_at_max.out","d_1_am__U320.in1"], - ["d_1_next_value.sel","d_1_am__U320.out"], + ["true.out","d_1_am__U241.in0"], + ["d_2_at_max.out","d_1_am__U241.in1"], + ["d_1_am__U242.in0","d_1_am__U241.out"], + ["d_3_at_max.out","d_1_am__U242.in1"], + ["d_1_am__U243.in0","d_1_am__U242.out"], + ["d_4_at_max.out","d_1_am__U243.in1"], + ["d_1_am__U244.in0","d_1_am__U243.out"], + ["d_5_at_max.out","d_1_am__U244.in1"], + ["d_1_am__U245.in0","d_1_am__U244.out"], + ["d_6_at_max.out","d_1_am__U245.in1"], + ["d_1_am__U246.in0","d_1_am__U245.out"], + ["d_7_at_max.out","d_1_am__U246.in1"], + ["d_1_next_value.sel","d_1_am__U246.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2076,17 +1872,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U321.in0"], - ["d_3_at_max.out","d_2_am__U321.in1"], - ["d_2_am__U322.in0","d_2_am__U321.out"], - ["d_4_at_max.out","d_2_am__U322.in1"], - ["d_2_am__U323.in0","d_2_am__U322.out"], - ["d_5_at_max.out","d_2_am__U323.in1"], - ["d_2_am__U324.in0","d_2_am__U323.out"], - ["d_6_at_max.out","d_2_am__U324.in1"], - ["d_2_am__U325.in0","d_2_am__U324.out"], - ["d_7_at_max.out","d_2_am__U325.in1"], - ["d_2_next_value.sel","d_2_am__U325.out"], + ["true.out","d_2_am__U247.in0"], + ["d_3_at_max.out","d_2_am__U247.in1"], + ["d_2_am__U248.in0","d_2_am__U247.out"], + ["d_4_at_max.out","d_2_am__U248.in1"], + ["d_2_am__U249.in0","d_2_am__U248.out"], + ["d_5_at_max.out","d_2_am__U249.in1"], + ["d_2_am__U250.in0","d_2_am__U249.out"], + ["d_6_at_max.out","d_2_am__U250.in1"], + ["d_2_am__U251.in0","d_2_am__U250.out"], + ["d_7_at_max.out","d_2_am__U251.in1"], + ["d_2_next_value.sel","d_2_am__U251.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2099,15 +1895,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U326.in0"], - ["d_4_at_max.out","d_3_am__U326.in1"], - ["d_3_am__U327.in0","d_3_am__U326.out"], - ["d_5_at_max.out","d_3_am__U327.in1"], - ["d_3_am__U328.in0","d_3_am__U327.out"], - ["d_6_at_max.out","d_3_am__U328.in1"], - ["d_3_am__U329.in0","d_3_am__U328.out"], - ["d_7_at_max.out","d_3_am__U329.in1"], - ["d_3_next_value.sel","d_3_am__U329.out"], + ["true.out","d_3_am__U252.in0"], + ["d_4_at_max.out","d_3_am__U252.in1"], + ["d_3_am__U253.in0","d_3_am__U252.out"], + ["d_5_at_max.out","d_3_am__U253.in1"], + ["d_3_am__U254.in0","d_3_am__U253.out"], + ["d_6_at_max.out","d_3_am__U254.in1"], + ["d_3_am__U255.in0","d_3_am__U254.out"], + ["d_7_at_max.out","d_3_am__U255.in1"], + ["d_3_next_value.sel","d_3_am__U255.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2120,13 +1916,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U330.in0"], - ["d_5_at_max.out","d_4_am__U330.in1"], - ["d_4_am__U331.in0","d_4_am__U330.out"], - ["d_6_at_max.out","d_4_am__U331.in1"], - ["d_4_am__U332.in0","d_4_am__U331.out"], - ["d_7_at_max.out","d_4_am__U332.in1"], - ["d_4_next_value.sel","d_4_am__U332.out"], + ["true.out","d_4_am__U256.in0"], + ["d_5_at_max.out","d_4_am__U256.in1"], + ["d_4_am__U257.in0","d_4_am__U256.out"], + ["d_6_at_max.out","d_4_am__U257.in1"], + ["d_4_am__U258.in0","d_4_am__U257.out"], + ["d_7_at_max.out","d_4_am__U258.in1"], + ["d_4_next_value.sel","d_4_am__U258.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2139,11 +1935,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U333.in0"], - ["d_6_at_max.out","d_5_am__U333.in1"], - ["d_5_am__U334.in0","d_5_am__U333.out"], - ["d_7_at_max.out","d_5_am__U334.in1"], - ["d_5_next_value.sel","d_5_am__U334.out"], + ["true.out","d_5_am__U259.in0"], + ["d_6_at_max.out","d_5_am__U259.in1"], + ["d_5_am__U260.in0","d_5_am__U259.out"], + ["d_7_at_max.out","d_5_am__U260.in1"], + ["d_5_next_value.sel","d_5_am__U260.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -2156,9 +1952,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U335.in0"], - ["d_7_at_max.out","d_6_am__U335.in1"], - ["d_6_next_value.sel","d_6_am__U335.out"], + ["true.out","d_6_am__U261.in0"], + ["d_7_at_max.out","d_6_am__U261.in1"], + ["d_6_next_value.sel","d_6_am__U261.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -2186,7 +1982,7 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U382":{ + "affine_controller__U299":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2194,18 +1990,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U403":{ + "_U320":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U404":{ + "_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U383" + "modref":"global.aff__U300" }, "cmp_time":{ "genref":"coreir.eq", @@ -2215,19 +2011,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U405":{ + "d_0_am__U322":{ "modref":"corebit.and" }, - "d_0_am__U406":{ + "d_0_am__U323":{ "modref":"corebit.and" }, - "d_0_am__U407":{ + "d_0_am__U324":{ "modref":"corebit.and" }, - "d_0_am__U408":{ + "d_0_am__U325":{ "modref":"corebit.and" }, - "d_0_am__U409":{ + "d_0_am__U326":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2261,16 +2057,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U410":{ + "d_1_am__U327":{ "modref":"corebit.and" }, - "d_1_am__U411":{ + "d_1_am__U328":{ "modref":"corebit.and" }, - "d_1_am__U412":{ + "d_1_am__U329":{ "modref":"corebit.and" }, - "d_1_am__U413":{ + "d_1_am__U330":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2304,13 +2100,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U414":{ + "d_2_am__U331":{ "modref":"corebit.and" }, - "d_2_am__U415":{ + "d_2_am__U332":{ "modref":"corebit.and" }, - "d_2_am__U416":{ + "d_2_am__U333":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2344,10 +2140,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U417":{ + "d_3_am__U334":{ "modref":"corebit.and" }, - "d_3_am__U418":{ + "d_3_am__U335":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2381,7 +2177,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U419":{ + "d_4_am__U336":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2456,13 +2252,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U403.out"], - ["d_1_inc.in1","_U403.out"], - ["d_2_inc.in1","_U403.out"], - ["d_3_inc.in1","_U403.out"], - ["d_4_inc.in1","_U403.out"], - ["d_5_inc.in1","_U403.out"], - ["cmp_time.in1","_U404.out"], + ["d_0_inc.in1","_U320.out"], + ["d_1_inc.in1","_U320.out"], + ["d_2_inc.in1","_U320.out"], + ["d_3_inc.in1","_U320.out"], + ["d_4_inc.in1","_U320.out"], + ["d_5_inc.in1","_U320.out"], + ["cmp_time.in1","_U321.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2481,17 +2277,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U405.in0"], - ["d_1_at_max.out","d_0_am__U405.in1"], - ["d_0_am__U406.in0","d_0_am__U405.out"], - ["d_2_at_max.out","d_0_am__U406.in1"], - ["d_0_am__U407.in0","d_0_am__U406.out"], - ["d_3_at_max.out","d_0_am__U407.in1"], - ["d_0_am__U408.in0","d_0_am__U407.out"], - ["d_4_at_max.out","d_0_am__U408.in1"], - ["d_0_am__U409.in0","d_0_am__U408.out"], - ["d_5_at_max.out","d_0_am__U409.in1"], - ["d_0_next_value.sel","d_0_am__U409.out"], + ["true.out","d_0_am__U322.in0"], + ["d_1_at_max.out","d_0_am__U322.in1"], + ["d_0_am__U323.in0","d_0_am__U322.out"], + ["d_2_at_max.out","d_0_am__U323.in1"], + ["d_0_am__U324.in0","d_0_am__U323.out"], + ["d_3_at_max.out","d_0_am__U324.in1"], + ["d_0_am__U325.in0","d_0_am__U324.out"], + ["d_4_at_max.out","d_0_am__U325.in1"], + ["d_0_am__U326.in0","d_0_am__U325.out"], + ["d_5_at_max.out","d_0_am__U326.in1"], + ["d_0_next_value.sel","d_0_am__U326.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2504,15 +2300,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U410.in0"], - ["d_2_at_max.out","d_1_am__U410.in1"], - ["d_1_am__U411.in0","d_1_am__U410.out"], - ["d_3_at_max.out","d_1_am__U411.in1"], - ["d_1_am__U412.in0","d_1_am__U411.out"], - ["d_4_at_max.out","d_1_am__U412.in1"], - ["d_1_am__U413.in0","d_1_am__U412.out"], - ["d_5_at_max.out","d_1_am__U413.in1"], - ["d_1_next_value.sel","d_1_am__U413.out"], + ["true.out","d_1_am__U327.in0"], + ["d_2_at_max.out","d_1_am__U327.in1"], + ["d_1_am__U328.in0","d_1_am__U327.out"], + ["d_3_at_max.out","d_1_am__U328.in1"], + ["d_1_am__U329.in0","d_1_am__U328.out"], + ["d_4_at_max.out","d_1_am__U329.in1"], + ["d_1_am__U330.in0","d_1_am__U329.out"], + ["d_5_at_max.out","d_1_am__U330.in1"], + ["d_1_next_value.sel","d_1_am__U330.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2525,13 +2321,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U414.in0"], - ["d_3_at_max.out","d_2_am__U414.in1"], - ["d_2_am__U415.in0","d_2_am__U414.out"], - ["d_4_at_max.out","d_2_am__U415.in1"], - ["d_2_am__U416.in0","d_2_am__U415.out"], - ["d_5_at_max.out","d_2_am__U416.in1"], - ["d_2_next_value.sel","d_2_am__U416.out"], + ["true.out","d_2_am__U331.in0"], + ["d_3_at_max.out","d_2_am__U331.in1"], + ["d_2_am__U332.in0","d_2_am__U331.out"], + ["d_4_at_max.out","d_2_am__U332.in1"], + ["d_2_am__U333.in0","d_2_am__U332.out"], + ["d_5_at_max.out","d_2_am__U333.in1"], + ["d_2_next_value.sel","d_2_am__U333.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2544,11 +2340,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U417.in0"], - ["d_4_at_max.out","d_3_am__U417.in1"], - ["d_3_am__U418.in0","d_3_am__U417.out"], - ["d_5_at_max.out","d_3_am__U418.in1"], - ["d_3_next_value.sel","d_3_am__U418.out"], + ["true.out","d_3_am__U334.in0"], + ["d_4_at_max.out","d_3_am__U334.in1"], + ["d_3_am__U335.in0","d_3_am__U334.out"], + ["d_5_at_max.out","d_3_am__U335.in1"], + ["d_3_next_value.sel","d_3_am__U335.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2561,9 +2357,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U419.in0"], - ["d_5_at_max.out","d_4_am__U419.in1"], - ["d_4_next_value.sel","d_4_am__U419.out"], + ["true.out","d_4_am__U336.in0"], + ["d_5_at_max.out","d_4_am__U336.in1"], + ["d_4_next_value.sel","d_4_am__U336.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2591,7 +2387,7 @@ ["self.d.5","d_5_reg.out"] ] }, - "affine_controller__U442":{ + "affine_controller__U359":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2599,18 +2395,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U454":{ + "_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U455":{ + "_U372":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U443" + "modref":"global.aff__U360" }, "cmp_time":{ "genref":"coreir.eq", @@ -2620,10 +2416,10 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U456":{ + "d_0_am__U373":{ "modref":"corebit.and" }, - "d_0_am__U457":{ + "d_0_am__U374":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2657,7 +2453,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U458":{ + "d_1_am__U375":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2732,10 +2528,10 @@ } }, "connections":[ - ["d_0_inc.in1","_U454.out"], - ["d_1_inc.in1","_U454.out"], - ["d_2_inc.in1","_U454.out"], - ["cmp_time.in1","_U455.out"], + ["d_0_inc.in1","_U371.out"], + ["d_1_inc.in1","_U371.out"], + ["d_2_inc.in1","_U371.out"], + ["cmp_time.in1","_U372.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2748,11 +2544,11 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U456.in0"], - ["d_1_at_max.out","d_0_am__U456.in1"], - ["d_0_am__U457.in0","d_0_am__U456.out"], - ["d_2_at_max.out","d_0_am__U457.in1"], - ["d_0_next_value.sel","d_0_am__U457.out"], + ["true.out","d_0_am__U373.in0"], + ["d_1_at_max.out","d_0_am__U373.in1"], + ["d_0_am__U374.in0","d_0_am__U373.out"], + ["d_2_at_max.out","d_0_am__U374.in1"], + ["d_0_next_value.sel","d_0_am__U374.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2765,9 +2561,9 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U458.in0"], - ["d_2_at_max.out","d_1_am__U458.in1"], - ["d_1_next_value.sel","d_1_am__U458.out"], + ["true.out","d_1_am__U375.in0"], + ["d_2_at_max.out","d_1_am__U375.in1"], + ["d_1_next_value.sel","d_1_am__U375.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2795,7 +2591,7 @@ ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U47":{ + "affine_controller__U38":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2803,18 +2599,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U71":{ + "_U62":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U72":{ + "_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U48" + "modref":"global.aff__U39" }, "cmp_time":{ "genref":"coreir.eq", @@ -2824,22 +2620,22 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U73":{ + "d_0_am__U64":{ "modref":"corebit.and" }, - "d_0_am__U74":{ + "d_0_am__U65":{ "modref":"corebit.and" }, - "d_0_am__U75":{ + "d_0_am__U66":{ "modref":"corebit.and" }, - "d_0_am__U76":{ + "d_0_am__U67":{ "modref":"corebit.and" }, - "d_0_am__U77":{ + "d_0_am__U68":{ "modref":"corebit.and" }, - "d_0_am__U78":{ + "d_0_am__U69":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2873,19 +2669,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U79":{ + "d_1_am__U70":{ "modref":"corebit.and" }, - "d_1_am__U80":{ + "d_1_am__U71":{ "modref":"corebit.and" }, - "d_1_am__U81":{ + "d_1_am__U72":{ "modref":"corebit.and" }, - "d_1_am__U82":{ + "d_1_am__U73":{ "modref":"corebit.and" }, - "d_1_am__U83":{ + "d_1_am__U74":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2919,16 +2715,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U84":{ + "d_2_am__U75":{ "modref":"corebit.and" }, - "d_2_am__U85":{ + "d_2_am__U76":{ "modref":"corebit.and" }, - "d_2_am__U86":{ + "d_2_am__U77":{ "modref":"corebit.and" }, - "d_2_am__U87":{ + "d_2_am__U78":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2962,13 +2758,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U88":{ + "d_3_am__U79":{ "modref":"corebit.and" }, - "d_3_am__U89":{ + "d_3_am__U80":{ "modref":"corebit.and" }, - "d_3_am__U90":{ + "d_3_am__U81":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -3002,10 +2798,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U91":{ + "d_4_am__U82":{ "modref":"corebit.and" }, - "d_4_am__U92":{ + "d_4_am__U83":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -3039,7 +2835,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U93":{ + "d_5_am__U84":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -3114,14 +2910,14 @@ } }, "connections":[ - ["d_0_inc.in1","_U71.out"], - ["d_1_inc.in1","_U71.out"], - ["d_2_inc.in1","_U71.out"], - ["d_3_inc.in1","_U71.out"], - ["d_4_inc.in1","_U71.out"], - ["d_5_inc.in1","_U71.out"], - ["d_6_inc.in1","_U71.out"], - ["cmp_time.in1","_U72.out"], + ["d_0_inc.in1","_U62.out"], + ["d_1_inc.in1","_U62.out"], + ["d_2_inc.in1","_U62.out"], + ["d_3_inc.in1","_U62.out"], + ["d_4_inc.in1","_U62.out"], + ["d_5_inc.in1","_U62.out"], + ["d_6_inc.in1","_U62.out"], + ["cmp_time.in1","_U63.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3142,19 +2938,19 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U73.in0"], - ["d_1_at_max.out","d_0_am__U73.in1"], - ["d_0_am__U74.in0","d_0_am__U73.out"], - ["d_2_at_max.out","d_0_am__U74.in1"], - ["d_0_am__U75.in0","d_0_am__U74.out"], - ["d_3_at_max.out","d_0_am__U75.in1"], - ["d_0_am__U76.in0","d_0_am__U75.out"], - ["d_4_at_max.out","d_0_am__U76.in1"], - ["d_0_am__U77.in0","d_0_am__U76.out"], - ["d_5_at_max.out","d_0_am__U77.in1"], - ["d_0_am__U78.in0","d_0_am__U77.out"], - ["d_6_at_max.out","d_0_am__U78.in1"], - ["d_0_next_value.sel","d_0_am__U78.out"], + ["true.out","d_0_am__U64.in0"], + ["d_1_at_max.out","d_0_am__U64.in1"], + ["d_0_am__U65.in0","d_0_am__U64.out"], + ["d_2_at_max.out","d_0_am__U65.in1"], + ["d_0_am__U66.in0","d_0_am__U65.out"], + ["d_3_at_max.out","d_0_am__U66.in1"], + ["d_0_am__U67.in0","d_0_am__U66.out"], + ["d_4_at_max.out","d_0_am__U67.in1"], + ["d_0_am__U68.in0","d_0_am__U67.out"], + ["d_5_at_max.out","d_0_am__U68.in1"], + ["d_0_am__U69.in0","d_0_am__U68.out"], + ["d_6_at_max.out","d_0_am__U69.in1"], + ["d_0_next_value.sel","d_0_am__U69.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3167,17 +2963,17 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U79.in0"], - ["d_2_at_max.out","d_1_am__U79.in1"], - ["d_1_am__U80.in0","d_1_am__U79.out"], - ["d_3_at_max.out","d_1_am__U80.in1"], - ["d_1_am__U81.in0","d_1_am__U80.out"], - ["d_4_at_max.out","d_1_am__U81.in1"], - ["d_1_am__U82.in0","d_1_am__U81.out"], - ["d_5_at_max.out","d_1_am__U82.in1"], - ["d_1_am__U83.in0","d_1_am__U82.out"], - ["d_6_at_max.out","d_1_am__U83.in1"], - ["d_1_next_value.sel","d_1_am__U83.out"], + ["true.out","d_1_am__U70.in0"], + ["d_2_at_max.out","d_1_am__U70.in1"], + ["d_1_am__U71.in0","d_1_am__U70.out"], + ["d_3_at_max.out","d_1_am__U71.in1"], + ["d_1_am__U72.in0","d_1_am__U71.out"], + ["d_4_at_max.out","d_1_am__U72.in1"], + ["d_1_am__U73.in0","d_1_am__U72.out"], + ["d_5_at_max.out","d_1_am__U73.in1"], + ["d_1_am__U74.in0","d_1_am__U73.out"], + ["d_6_at_max.out","d_1_am__U74.in1"], + ["d_1_next_value.sel","d_1_am__U74.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3190,15 +2986,15 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U84.in0"], - ["d_3_at_max.out","d_2_am__U84.in1"], - ["d_2_am__U85.in0","d_2_am__U84.out"], - ["d_4_at_max.out","d_2_am__U85.in1"], - ["d_2_am__U86.in0","d_2_am__U85.out"], - ["d_5_at_max.out","d_2_am__U86.in1"], - ["d_2_am__U87.in0","d_2_am__U86.out"], - ["d_6_at_max.out","d_2_am__U87.in1"], - ["d_2_next_value.sel","d_2_am__U87.out"], + ["true.out","d_2_am__U75.in0"], + ["d_3_at_max.out","d_2_am__U75.in1"], + ["d_2_am__U76.in0","d_2_am__U75.out"], + ["d_4_at_max.out","d_2_am__U76.in1"], + ["d_2_am__U77.in0","d_2_am__U76.out"], + ["d_5_at_max.out","d_2_am__U77.in1"], + ["d_2_am__U78.in0","d_2_am__U77.out"], + ["d_6_at_max.out","d_2_am__U78.in1"], + ["d_2_next_value.sel","d_2_am__U78.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3211,13 +3007,13 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U88.in0"], - ["d_4_at_max.out","d_3_am__U88.in1"], - ["d_3_am__U89.in0","d_3_am__U88.out"], - ["d_5_at_max.out","d_3_am__U89.in1"], - ["d_3_am__U90.in0","d_3_am__U89.out"], - ["d_6_at_max.out","d_3_am__U90.in1"], - ["d_3_next_value.sel","d_3_am__U90.out"], + ["true.out","d_3_am__U79.in0"], + ["d_4_at_max.out","d_3_am__U79.in1"], + ["d_3_am__U80.in0","d_3_am__U79.out"], + ["d_5_at_max.out","d_3_am__U80.in1"], + ["d_3_am__U81.in0","d_3_am__U80.out"], + ["d_6_at_max.out","d_3_am__U81.in1"], + ["d_3_next_value.sel","d_3_am__U81.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3230,11 +3026,11 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U91.in0"], - ["d_5_at_max.out","d_4_am__U91.in1"], - ["d_4_am__U92.in0","d_4_am__U91.out"], - ["d_6_at_max.out","d_4_am__U92.in1"], - ["d_4_next_value.sel","d_4_am__U92.out"], + ["true.out","d_4_am__U82.in0"], + ["d_5_at_max.out","d_4_am__U82.in1"], + ["d_4_am__U83.in0","d_4_am__U82.out"], + ["d_6_at_max.out","d_4_am__U83.in1"], + ["d_4_next_value.sel","d_4_am__U83.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3247,9 +3043,9 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U93.in0"], - ["d_6_at_max.out","d_5_am__U93.in1"], - ["d_5_next_value.sel","d_5_am__U93.out"], + ["true.out","d_5_am__U84.in0"], + ["d_6_at_max.out","d_5_am__U84.in1"], + ["d_5_next_value.sel","d_5_am__U84.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -3277,6 +3073,210 @@ ["self.d.6","d_6_reg.out"] ] }, + "affine_controller__U8":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",3,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U9" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U22":{ + "modref":"corebit.and" + }, + "d_0_am__U23":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U24":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U20.out"], + ["d_1_inc.in1","_U20.out"], + ["d_2_inc.in1","_U20.out"], + ["cmp_time.in1","_U21.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U22.in0"], + ["d_1_at_max.out","d_0_am__U22.in1"], + ["d_0_am__U23.in0","d_0_am__U22.out"], + ["d_2_at_max.out","d_0_am__U23.in1"], + ["d_0_next_value.sel","d_0_am__U23.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U24.in0"], + ["d_2_at_max.out","d_1_am__U24.in1"], + ["d_1_next_value.sel","d_1_am__U24.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["true.out","d_2_next_value.sel"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"] + ] + }, "cu_op_hcompute_hw_output_stencil":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], @@ -4894,42 +4894,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16409],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16384],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16409],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16384],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -4937,8 +4905,8 @@ }, "ub_input_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16410],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16385],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16410],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16385],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -4946,8 +4914,8 @@ }, "ub_input_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16411],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16386],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16411],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16386],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -4955,8 +4923,8 @@ }, "ub_input_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16412],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16387],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16412],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16387],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -4964,8 +4932,8 @@ }, "ub_input_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16413],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16388],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16413],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16388],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -4973,8 +4941,8 @@ }, "ub_input_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16414],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16389],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16414],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16389],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -4982,8 +4950,8 @@ }, "ub_input_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16415],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16390],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16415],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16390],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -4991,8 +4959,8 @@ }, "ub_input_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16416],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16391],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16416],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[16391],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -5000,14 +4968,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_input_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U11.out"], - ["ub_input_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U13.out"], - ["ub_input_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U15.out"], - ["ub_input_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_input_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], - ["ub_input_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U7.out"], - ["ub_input_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U9.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_1.clk","self.clk"], ["ub_input_cgra_stencil_BANK_2.clk","self.clk"], @@ -5125,42 +5085,42 @@ ["op_hcompute_input_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U118":{ - "modref":"global.aff__U95" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U109":{ + "modref":"global.aff__U86" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46":{ - "modref":"global.aff__U35" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U37":{ + "modref":"global.aff__U26" }, - "chain_en_const_U119":{ + "chain_en_const_U110":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U34":{ - "modref":"global.affine_controller__U17", + "ctrl__U25":{ + "modref":"global.affine_controller__U8", "metadata":{"garnet_remove":true} }, - "ctrl__U94":{ - "modref":"global.affine_controller__U47", + "ctrl__U85":{ + "modref":"global.affine_controller__U38", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[16384],"cycle_stride":[1,64,4096,8192,16384],"dimensionality":5,"extent":[64,64,2,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,128,64,0,8192]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U16"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[16384],"cycle_stride":[1,64,4096,8192,16384],"dimensionality":5,"extent":[64,64,2,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,128,64,0,8192]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U94.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U118.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U118.out"], - ["ctrl__U34.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U119.out"], - ["self.clk","ctrl__U34.clk"], - ["self.reset","ctrl__U34.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U34.valid"], - ["self.clk","ctrl__U94.clk"], - ["self.reset","ctrl__U94.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U94.valid"], + ["ctrl__U85.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U109.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U109.out"], + ["ctrl__U25.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U37.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U37.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U110.out"], + ["self.clk","ctrl__U25.clk"], + ["self.reset","ctrl__U25.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U25.valid"], + ["self.clk","ctrl__U85.clk"], + ["self.reset","ctrl__U85.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U85.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_glb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_input_cgra_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -5192,266 +5152,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U121":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U123":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U125":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U127":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U129":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U131":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U133":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U135":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U137":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U139":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U141":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16409],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16384],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U120"} + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16409],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16384],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -5459,13 +5163,13 @@ }, "ub_kernel_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16473],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16448],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U122"} + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16473],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16448],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16538],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16513],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U140"} + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16538],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16513],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -5473,8 +5177,8 @@ }, "ub_kernel_cgra_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16602],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16577],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U142"} + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16602],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16577],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -5482,8 +5186,8 @@ }, "ub_kernel_cgra_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16666],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16641],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U144"} + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16666],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16641],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -5491,8 +5195,8 @@ }, "ub_kernel_cgra_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16730],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16705],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U146"} + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16730],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16705],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -5500,8 +5204,8 @@ }, "ub_kernel_cgra_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16794],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16769],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U148"} + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16794],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16769],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -5509,8 +5213,8 @@ }, "ub_kernel_cgra_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16858],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16833],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U150"} + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16858],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16833],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -5518,8 +5222,8 @@ }, "ub_kernel_cgra_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16411],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16386],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U152"} + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16411],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16386],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -5527,8 +5231,8 @@ }, "ub_kernel_cgra_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16475],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16450],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U154"} + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16475],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16450],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -5536,8 +5240,8 @@ }, "ub_kernel_cgra_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16539],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16514],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U156"} + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16539],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16514],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -5545,8 +5249,8 @@ }, "ub_kernel_cgra_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16603],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16578],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U158"} + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16603],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16578],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -5558,13 +5262,13 @@ }, "ub_kernel_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16537],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16512],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U124"} + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16537],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16512],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16667],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16642],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U160"} + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16667],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16642],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -5572,8 +5276,8 @@ }, "ub_kernel_cgra_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16731],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16706],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U162"} + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16731],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16706],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -5581,8 +5285,8 @@ }, "ub_kernel_cgra_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16795],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16770],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U164"} + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16795],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16770],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -5590,8 +5294,8 @@ }, "ub_kernel_cgra_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16859],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16834],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U166"} + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16859],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16834],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -5599,8 +5303,8 @@ }, "ub_kernel_cgra_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16412],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16387],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U168"} + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16412],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16387],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -5608,8 +5312,8 @@ }, "ub_kernel_cgra_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16476],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16451],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U170"} + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16476],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16451],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -5617,8 +5321,8 @@ }, "ub_kernel_cgra_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16540],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16515],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U172"} + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16540],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16515],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -5626,8 +5330,8 @@ }, "ub_kernel_cgra_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16604],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16579],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U174"} + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16604],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16579],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -5635,8 +5339,8 @@ }, "ub_kernel_cgra_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16668],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16643],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U176"} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16668],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16643],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -5644,8 +5348,8 @@ }, "ub_kernel_cgra_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16732],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16707],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U178"} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16732],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16707],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -5657,13 +5361,13 @@ }, "ub_kernel_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16601],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16576],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U126"} + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16601],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16576],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16796],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16771],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U180"} + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16796],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16771],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -5671,8 +5375,8 @@ }, "ub_kernel_cgra_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16860],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16835],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U182"} + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16860],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16835],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -5680,8 +5384,8 @@ }, "ub_kernel_cgra_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16413],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16388],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U184"} + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16413],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16388],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -5689,8 +5393,8 @@ }, "ub_kernel_cgra_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16477],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16452],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U186"} + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16477],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16452],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -5698,8 +5402,8 @@ }, "ub_kernel_cgra_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16541],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16516],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U188"} + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16541],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16516],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -5707,8 +5411,8 @@ }, "ub_kernel_cgra_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16605],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16580],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U190"} + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16605],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16580],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -5716,8 +5420,8 @@ }, "ub_kernel_cgra_stencil_BANK_36":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16669],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16644],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U192"} + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16669],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16644],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const":{ "modref":"corebit.const", @@ -5725,8 +5429,8 @@ }, "ub_kernel_cgra_stencil_BANK_37":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16733],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16708],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U194"} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16733],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16708],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const":{ "modref":"corebit.const", @@ -5734,8 +5438,8 @@ }, "ub_kernel_cgra_stencil_BANK_38":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16797],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16772],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U196"} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16797],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16772],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const":{ "modref":"corebit.const", @@ -5743,8 +5447,8 @@ }, "ub_kernel_cgra_stencil_BANK_39":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16861],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16836],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U198"} + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16861],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16836],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const":{ "modref":"corebit.const", @@ -5756,13 +5460,13 @@ }, "ub_kernel_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16665],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16640],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U128"} + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16665],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16640],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16414],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16389],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U200"} + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16414],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16389],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const":{ "modref":"corebit.const", @@ -5770,8 +5474,8 @@ }, "ub_kernel_cgra_stencil_BANK_41":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16478],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16453],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U202"} + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16478],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16453],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const":{ "modref":"corebit.const", @@ -5779,8 +5483,8 @@ }, "ub_kernel_cgra_stencil_BANK_42":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16542],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16517],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U204"} + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16542],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16517],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const":{ "modref":"corebit.const", @@ -5788,8 +5492,8 @@ }, "ub_kernel_cgra_stencil_BANK_43":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16606],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16581],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U206"} + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16606],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16581],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const":{ "modref":"corebit.const", @@ -5797,8 +5501,8 @@ }, "ub_kernel_cgra_stencil_BANK_44":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16670],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16645],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U208"} + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16670],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16645],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const":{ "modref":"corebit.const", @@ -5806,8 +5510,8 @@ }, "ub_kernel_cgra_stencil_BANK_45":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16734],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16709],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U210"} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16734],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16709],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const":{ "modref":"corebit.const", @@ -5815,8 +5519,8 @@ }, "ub_kernel_cgra_stencil_BANK_46":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16798],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16773],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U212"} + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16798],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16773],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const":{ "modref":"corebit.const", @@ -5824,8 +5528,8 @@ }, "ub_kernel_cgra_stencil_BANK_47":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16862],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16837],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U214"} + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16862],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16837],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const":{ "modref":"corebit.const", @@ -5833,8 +5537,8 @@ }, "ub_kernel_cgra_stencil_BANK_48":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16415],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16390],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U216"} + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16415],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16390],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const":{ "modref":"corebit.const", @@ -5842,8 +5546,8 @@ }, "ub_kernel_cgra_stencil_BANK_49":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16479],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16454],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U218"} + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16479],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16454],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const":{ "modref":"corebit.const", @@ -5855,13 +5559,13 @@ }, "ub_kernel_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16729],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16704],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U130"} + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16729],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16704],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16543],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16518],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U220"} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16543],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16518],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const":{ "modref":"corebit.const", @@ -5869,8 +5573,8 @@ }, "ub_kernel_cgra_stencil_BANK_51":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16607],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16582],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U222"} + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16607],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16582],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const":{ "modref":"corebit.const", @@ -5878,8 +5582,8 @@ }, "ub_kernel_cgra_stencil_BANK_52":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16671],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16646],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U224"} + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16671],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16646],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const":{ "modref":"corebit.const", @@ -5887,8 +5591,8 @@ }, "ub_kernel_cgra_stencil_BANK_53":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16735],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16710],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U226"} + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16735],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16710],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const":{ "modref":"corebit.const", @@ -5896,8 +5600,8 @@ }, "ub_kernel_cgra_stencil_BANK_54":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16799],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16774],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U228"} + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16799],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16774],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const":{ "modref":"corebit.const", @@ -5905,8 +5609,8 @@ }, "ub_kernel_cgra_stencil_BANK_55":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16863],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16838],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U230"} + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16863],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16838],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const":{ "modref":"corebit.const", @@ -5914,8 +5618,8 @@ }, "ub_kernel_cgra_stencil_BANK_56":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16416],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16391],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U232"} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16416],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16391],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const":{ "modref":"corebit.const", @@ -5923,8 +5627,8 @@ }, "ub_kernel_cgra_stencil_BANK_57":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16480],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16455],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U234"} + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16480],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16455],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const":{ "modref":"corebit.const", @@ -5932,8 +5636,8 @@ }, "ub_kernel_cgra_stencil_BANK_58":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16544],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16519],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U236"} + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16544],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16519],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const":{ "modref":"corebit.const", @@ -5941,8 +5645,8 @@ }, "ub_kernel_cgra_stencil_BANK_59":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16608],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16583],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U238"} + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16608],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16583],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const":{ "modref":"corebit.const", @@ -5954,13 +5658,13 @@ }, "ub_kernel_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16793],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16768],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U132"} + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16793],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16768],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16672],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16647],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U240"} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16672],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16647],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const":{ "modref":"corebit.const", @@ -5968,8 +5672,8 @@ }, "ub_kernel_cgra_stencil_BANK_61":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16736],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16711],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U242"} + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16736],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16711],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const":{ "modref":"corebit.const", @@ -5977,8 +5681,8 @@ }, "ub_kernel_cgra_stencil_BANK_62":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16800],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16775],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U244"} + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16800],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16775],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const":{ "modref":"corebit.const", @@ -5986,8 +5690,8 @@ }, "ub_kernel_cgra_stencil_BANK_63":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16864],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16839],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U246"} + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16864],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16839],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const":{ "modref":"corebit.const", @@ -5999,8 +5703,8 @@ }, "ub_kernel_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16857],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16832],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U134"} + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16857],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16832],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -6008,8 +5712,8 @@ }, "ub_kernel_cgra_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16410],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16385],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U136"} + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16410],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16385],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -6017,8 +5721,8 @@ }, "ub_kernel_cgra_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16474],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16449],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake","verilog_name":"lake__U138"} + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16474],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[16449],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20477],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -6026,70 +5730,6 @@ } }, "connections":[ - ["ub_kernel_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U121.out"], - ["ub_kernel_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U123.out"], - ["ub_kernel_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U125.out"], - ["ub_kernel_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U127.out"], - ["ub_kernel_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U129.out"], - ["ub_kernel_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U131.out"], - ["ub_kernel_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U133.out"], - ["ub_kernel_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U135.out"], - ["ub_kernel_cgra_stencil_BANK_8.chain_chain_en","chain_en_const_U137.out"], - ["ub_kernel_cgra_stencil_BANK_9.chain_chain_en","chain_en_const_U139.out"], - ["ub_kernel_cgra_stencil_BANK_10.chain_chain_en","chain_en_const_U141.out"], - ["ub_kernel_cgra_stencil_BANK_11.chain_chain_en","chain_en_const_U143.out"], - ["ub_kernel_cgra_stencil_BANK_12.chain_chain_en","chain_en_const_U145.out"], - ["ub_kernel_cgra_stencil_BANK_13.chain_chain_en","chain_en_const_U147.out"], - ["ub_kernel_cgra_stencil_BANK_14.chain_chain_en","chain_en_const_U149.out"], - ["ub_kernel_cgra_stencil_BANK_15.chain_chain_en","chain_en_const_U151.out"], - ["ub_kernel_cgra_stencil_BANK_16.chain_chain_en","chain_en_const_U153.out"], - ["ub_kernel_cgra_stencil_BANK_17.chain_chain_en","chain_en_const_U155.out"], - ["ub_kernel_cgra_stencil_BANK_18.chain_chain_en","chain_en_const_U157.out"], - ["ub_kernel_cgra_stencil_BANK_19.chain_chain_en","chain_en_const_U159.out"], - ["ub_kernel_cgra_stencil_BANK_20.chain_chain_en","chain_en_const_U161.out"], - ["ub_kernel_cgra_stencil_BANK_21.chain_chain_en","chain_en_const_U163.out"], - ["ub_kernel_cgra_stencil_BANK_22.chain_chain_en","chain_en_const_U165.out"], - ["ub_kernel_cgra_stencil_BANK_23.chain_chain_en","chain_en_const_U167.out"], - ["ub_kernel_cgra_stencil_BANK_24.chain_chain_en","chain_en_const_U169.out"], - ["ub_kernel_cgra_stencil_BANK_25.chain_chain_en","chain_en_const_U171.out"], - ["ub_kernel_cgra_stencil_BANK_26.chain_chain_en","chain_en_const_U173.out"], - ["ub_kernel_cgra_stencil_BANK_27.chain_chain_en","chain_en_const_U175.out"], - ["ub_kernel_cgra_stencil_BANK_28.chain_chain_en","chain_en_const_U177.out"], - ["ub_kernel_cgra_stencil_BANK_29.chain_chain_en","chain_en_const_U179.out"], - ["ub_kernel_cgra_stencil_BANK_30.chain_chain_en","chain_en_const_U181.out"], - ["ub_kernel_cgra_stencil_BANK_31.chain_chain_en","chain_en_const_U183.out"], - ["ub_kernel_cgra_stencil_BANK_32.chain_chain_en","chain_en_const_U185.out"], - ["ub_kernel_cgra_stencil_BANK_33.chain_chain_en","chain_en_const_U187.out"], - ["ub_kernel_cgra_stencil_BANK_34.chain_chain_en","chain_en_const_U189.out"], - ["ub_kernel_cgra_stencil_BANK_35.chain_chain_en","chain_en_const_U191.out"], - ["ub_kernel_cgra_stencil_BANK_36.chain_chain_en","chain_en_const_U193.out"], - ["ub_kernel_cgra_stencil_BANK_37.chain_chain_en","chain_en_const_U195.out"], - ["ub_kernel_cgra_stencil_BANK_38.chain_chain_en","chain_en_const_U197.out"], - ["ub_kernel_cgra_stencil_BANK_39.chain_chain_en","chain_en_const_U199.out"], - ["ub_kernel_cgra_stencil_BANK_40.chain_chain_en","chain_en_const_U201.out"], - ["ub_kernel_cgra_stencil_BANK_41.chain_chain_en","chain_en_const_U203.out"], - ["ub_kernel_cgra_stencil_BANK_42.chain_chain_en","chain_en_const_U205.out"], - ["ub_kernel_cgra_stencil_BANK_43.chain_chain_en","chain_en_const_U207.out"], - ["ub_kernel_cgra_stencil_BANK_44.chain_chain_en","chain_en_const_U209.out"], - ["ub_kernel_cgra_stencil_BANK_45.chain_chain_en","chain_en_const_U211.out"], - ["ub_kernel_cgra_stencil_BANK_46.chain_chain_en","chain_en_const_U213.out"], - ["ub_kernel_cgra_stencil_BANK_47.chain_chain_en","chain_en_const_U215.out"], - ["ub_kernel_cgra_stencil_BANK_48.chain_chain_en","chain_en_const_U217.out"], - ["ub_kernel_cgra_stencil_BANK_49.chain_chain_en","chain_en_const_U219.out"], - ["ub_kernel_cgra_stencil_BANK_50.chain_chain_en","chain_en_const_U221.out"], - ["ub_kernel_cgra_stencil_BANK_51.chain_chain_en","chain_en_const_U223.out"], - ["ub_kernel_cgra_stencil_BANK_52.chain_chain_en","chain_en_const_U225.out"], - ["ub_kernel_cgra_stencil_BANK_53.chain_chain_en","chain_en_const_U227.out"], - ["ub_kernel_cgra_stencil_BANK_54.chain_chain_en","chain_en_const_U229.out"], - ["ub_kernel_cgra_stencil_BANK_55.chain_chain_en","chain_en_const_U231.out"], - ["ub_kernel_cgra_stencil_BANK_56.chain_chain_en","chain_en_const_U233.out"], - ["ub_kernel_cgra_stencil_BANK_57.chain_chain_en","chain_en_const_U235.out"], - ["ub_kernel_cgra_stencil_BANK_58.chain_chain_en","chain_en_const_U237.out"], - ["ub_kernel_cgra_stencil_BANK_59.chain_chain_en","chain_en_const_U239.out"], - ["ub_kernel_cgra_stencil_BANK_60.chain_chain_en","chain_en_const_U241.out"], - ["ub_kernel_cgra_stencil_BANK_61.chain_chain_en","chain_en_const_U243.out"], - ["ub_kernel_cgra_stencil_BANK_62.chain_chain_en","chain_en_const_U245.out"], - ["ub_kernel_cgra_stencil_BANK_63.chain_chain_en","chain_en_const_U247.out"], ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_1.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_10.clk","self.clk"], @@ -6487,42 +6127,42 @@ ["op_hcompute_kernel_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U363":{ - "modref":"global.aff__U337" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U289":{ + "modref":"global.aff__U263" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U278":{ - "modref":"global.aff__U267" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U204":{ + "modref":"global.aff__U193" }, - "chain_en_const_U364":{ + "chain_en_const_U290":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U266":{ - "modref":"global.affine_controller__U249", + "ctrl__U192":{ + "modref":"global.affine_controller__U175", "metadata":{"garnet_remove":true} }, - "ctrl__U336":{ - "modref":"global.affine_controller__U279", + "ctrl__U262":{ + "modref":"global.affine_controller__U205", "metadata":{"garnet_remove":true} }, "kernel_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[16384],"cycle_stride":[1,64,8192,16384],"dimensionality":4,"extent":[64,128,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,128,64,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U248"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[16384],"cycle_stride":[1,64,8192,16384],"dimensionality":4,"extent":[64,128,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,128,64,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U336.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U363.d"], - ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U363.out"], - ["ctrl__U266.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U278.d"], - ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U278.out"], - ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U364.out"], - ["self.clk","ctrl__U266.clk"], - ["self.reset","ctrl__U266.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U266.valid"], - ["self.clk","ctrl__U336.clk"], - ["self.reset","ctrl__U336.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U336.valid"], + ["ctrl__U262.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U289.d"], + ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U289.out"], + ["ctrl__U192.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U204.d"], + ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U204.out"], + ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U290.out"], + ["self.clk","ctrl__U192.clk"], + ["self.reset","ctrl__U192.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U192.valid"], + ["self.clk","ctrl__U262.clk"], + ["self.reset","ctrl__U262.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U262.valid"], ["self.clk","kernel_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_kernel_glb_stencil_write.0","kernel_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_kernel_cgra_stencil_read.0","kernel_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -6541,12 +6181,12 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U481":{ + "_U398":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U486":{ + "_U403":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -6567,22 +6207,22 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U475" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U392" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U473"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[57344],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U473"} + "genargs":{"ID":["String","_U390"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[57344],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U474" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U391" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U476" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U393" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" @@ -6591,22 +6231,22 @@ "modref":"global.cu_op_hcompute_input_glb_stencil" }, "op_hcompute_input_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U484" + "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U401" }, "op_hcompute_input_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U482"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U482"} + "genargs":{"ID":["String","_U399"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake"} }, "op_hcompute_input_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_glb_stencil_read_start":{ - "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U483" + "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U400" }, "op_hcompute_input_glb_stencil_write_start":{ - "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U485" + "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U402" }, "op_hcompute_kernel_cgra_stencil":{ "modref":"global.cu_op_hcompute_kernel_cgra_stencil" @@ -6615,22 +6255,22 @@ "modref":"global.cu_op_hcompute_kernel_glb_stencil" }, "op_hcompute_kernel_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U479" + "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U396" }, "op_hcompute_kernel_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U477"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U477"} + "genargs":{"ID":["String","_U394"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake"} }, "op_hcompute_kernel_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_kernel_glb_stencil_read_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U478" + "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U395" }, "op_hcompute_kernel_glb_stencil_write_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U480" + "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U397" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -6691,10 +6331,10 @@ } }, "connections":[ - ["self.clk","_U481.clk"], - ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U481.in"], - ["self.clk","_U486.clk"], - ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U486.in"], + ["self.clk","_U398.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U398.in"], + ["self.clk","_U403.clk"], + ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U403.in"], ["self.clk","input_cgra_stencil.clk"], ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], ["op_hcompute_output_cgra_stencil_10.input_cgra_stencil_op_hcompute_output_cgra_stencil_10_read","input_cgra_stencil.op_hcompute_output_cgra_stencil_10_read"], @@ -6807,7 +6447,7 @@ ["self.reset","output_glb_stencil.reset"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U475":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U392":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6816,7 +6456,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U474":{ + "op_hcompute_hw_output_stencil_read_start_pt__U391":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6825,7 +6465,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U476":{ + "op_hcompute_hw_output_stencil_write_start_pt__U393":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6834,7 +6474,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U484":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U401":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6843,7 +6483,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U483":{ + "op_hcompute_input_glb_stencil_read_start_pt__U400":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6852,7 +6492,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U485":{ + "op_hcompute_input_glb_stencil_write_start_pt__U402":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6861,7 +6501,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U479":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U396":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6870,7 +6510,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U478":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U395":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6879,7 +6519,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U480":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U397":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6945,42 +6585,10 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U366":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U368":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U370":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U372":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U374":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U376":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U378":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U380":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U365"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28669],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28672],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U365"} + "genargs":{"ID":["String","_U291"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28669],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28672],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -6988,8 +6596,8 @@ }, "ub_output_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U367"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16388],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"agg2sram_1":{"cycle_starting_addr":[20485],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"in2agg_1":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28671],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28673],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U367"} + "genargs":{"ID":["String","_U292"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[16388],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"agg2sram_1":{"cycle_starting_addr":[20485],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"in2agg_1":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28671],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28673],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -6997,8 +6605,8 @@ }, "ub_output_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U369"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28671],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28674],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U369"} + "genargs":{"ID":["String","_U293"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28671],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28674],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -7006,8 +6614,8 @@ }, "ub_output_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U371"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28673],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28675],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U371"} + "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28673],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28675],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -7015,8 +6623,8 @@ }, "ub_output_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U373"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28673],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28676],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U373"} + "genargs":{"ID":["String","_U295"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28673],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28676],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -7024,8 +6632,8 @@ }, "ub_output_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U375"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28675],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28677],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U375"} + "genargs":{"ID":["String","_U296"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28675],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28677],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -7033,8 +6641,8 @@ }, "ub_output_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U377"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28675],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28678],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U377"} + "genargs":{"ID":["String","_U297"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28675],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28678],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -7042,8 +6650,8 @@ }, "ub_output_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U379"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28677],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28679],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake","verilog_name":"lake__U379"} + "genargs":{"ID":["String","_U298"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[20484],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[16389],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[16384],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[20478],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[28677],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[20480],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[28679],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -7051,14 +6659,6 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U366.out"], - ["ub_output_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U368.out"], - ["ub_output_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U370.out"], - ["ub_output_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U372.out"], - ["ub_output_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U374.out"], - ["ub_output_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U376.out"], - ["ub_output_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U378.out"], - ["ub_output_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U380.out"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], @@ -7136,42 +6736,42 @@ ["op_hcompute_output_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U471":{ - "modref":"global.aff__U460" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U388":{ + "modref":"global.aff__U377" }, - "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U441":{ - "modref":"global.aff__U421" + "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U358":{ + "modref":"global.aff__U338" }, - "chain_en_const_U472":{ + "chain_en_const_U389":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U420":{ - "modref":"global.affine_controller__U382", + "ctrl__U337":{ + "modref":"global.affine_controller__U299", "metadata":{"garnet_remove":true} }, - "ctrl__U459":{ - "modref":"global.affine_controller__U442", + "ctrl__U376":{ + "modref":"global.affine_controller__U359", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[57344],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[28672],"cycle_stride":[1,64,8192,16384],"dimensionality":4,"extent":[64,64,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,128,64,8192]}},"mode":"glb","verilog_name":"glb__U381"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[57344],"cycle_stride":[1],"dimensionality":1,"extent":[16384],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[28672],"cycle_stride":[1,64,8192,16384],"dimensionality":4,"extent":[64,64,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,128,64,8192]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U459.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U471.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U471.out"], - ["ctrl__U420.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U441.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U441.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U472.out"], - ["self.clk","ctrl__U420.clk"], - ["self.reset","ctrl__U420.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U420.valid"], - ["self.clk","ctrl__U459.clk"], - ["self.reset","ctrl__U459.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U459.valid"], + ["ctrl__U376.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U388.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U388.out"], + ["ctrl__U337.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U358.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U358.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U389.out"], + ["self.clk","ctrl__U337.clk"], + ["self.reset","ctrl__U337.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U337.valid"], + ["self.clk","ctrl__U376.clk"], + ["self.reset","ctrl__U376.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U376.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_glb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], diff --git a/aha_garnet_design_new/matmul/matmul_garnet.json b/aha_garnet_design_new/matmul/matmul_garnet.json index 6dc8aaf14..3f7a714df 100644 --- a/aha_garnet_design_new/matmul/matmul_garnet.json +++ b/aha_garnet_design_new/matmul/matmul_garnet.json @@ -232,1219 +232,1219 @@ }, "global":{ "modules":{ - "aff__U18":{ + "aff__U176":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U26":{ + "add_all__U184":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U27":{ + "add_all__U185":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U28":{ + "add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U19":{ + "coeff_0_U177":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U21":{ + "coeff_1_U179":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U23":{ + "coeff_2_U181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U25":{ + "const_term_U183":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U20":{ + "mul_d0__U178":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U22":{ + "mul_d1__U180":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U24":{ + "mul_d2__U182":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U20.out","add_all__U26.in0"], - ["mul_d1__U22.out","add_all__U26.in1"], - ["add_all__U27.in0","add_all__U26.out"], - ["mul_d2__U24.out","add_all__U27.in1"], - ["add_all__U28.in0","add_all__U27.out"], - ["const_term_U25.out","add_all__U28.in1"], - ["self.out","add_all__U28.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"] + ["mul_d0__U178.out","add_all__U184.in0"], + ["mul_d1__U180.out","add_all__U184.in1"], + ["add_all__U185.in0","add_all__U184.out"], + ["mul_d2__U182.out","add_all__U185.in1"], + ["add_all__U186.in0","add_all__U185.out"], + ["const_term_U183.out","add_all__U186.in1"], + ["self.out","add_all__U186.out"], + ["mul_d0__U178.in0","coeff_0_U177.out"], + ["mul_d1__U180.in0","coeff_1_U179.out"], + ["mul_d2__U182.in0","coeff_2_U181.out"], + ["self.d.0","mul_d0__U178.in1"], + ["self.d.1","mul_d1__U180.in1"], + ["self.d.2","mul_d2__U182.in1"] ] }, - "aff__U250":{ + "aff__U193":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U258":{ + "add_all__U201":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U259":{ + "add_all__U202":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U260":{ + "add_all__U203":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U251":{ + "coeff_0_U194":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U253":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "coeff_2_U255":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U257":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U252":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U254":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U256":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U252.out","add_all__U258.in0"], - ["mul_d1__U254.out","add_all__U258.in1"], - ["add_all__U259.in0","add_all__U258.out"], - ["mul_d2__U256.out","add_all__U259.in1"], - ["add_all__U260.in0","add_all__U259.out"], - ["const_term_U257.out","add_all__U260.in1"], - ["self.out","add_all__U260.out"], - ["mul_d0__U252.in0","coeff_0_U251.out"], - ["mul_d1__U254.in0","coeff_1_U253.out"], - ["mul_d2__U256.in0","coeff_2_U255.out"], - ["self.d.0","mul_d0__U252.in1"], - ["self.d.1","mul_d1__U254.in1"], - ["self.d.2","mul_d2__U256.in1"] - ] - }, - "aff__U267":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",3,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U275":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U276":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U277":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U268":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U270":{ + "coeff_1_U196":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U272":{ + "coeff_2_U198":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U274":{ + "const_term_U200":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U269":{ + "mul_d0__U195":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U271":{ + "mul_d1__U197":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U273":{ + "mul_d2__U199":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U269.out","add_all__U275.in0"], - ["mul_d1__U271.out","add_all__U275.in1"], - ["add_all__U276.in0","add_all__U275.out"], - ["mul_d2__U273.out","add_all__U276.in1"], - ["add_all__U277.in0","add_all__U276.out"], - ["const_term_U274.out","add_all__U277.in1"], - ["self.out","add_all__U277.out"], - ["mul_d0__U269.in0","coeff_0_U268.out"], - ["mul_d1__U271.in0","coeff_1_U270.out"], - ["mul_d2__U273.in0","coeff_2_U272.out"], - ["self.d.0","mul_d0__U269.in1"], - ["self.d.1","mul_d1__U271.in1"], - ["self.d.2","mul_d2__U273.in1"] + ["mul_d0__U195.out","add_all__U201.in0"], + ["mul_d1__U197.out","add_all__U201.in1"], + ["add_all__U202.in0","add_all__U201.out"], + ["mul_d2__U199.out","add_all__U202.in1"], + ["add_all__U203.in0","add_all__U202.out"], + ["const_term_U200.out","add_all__U203.in1"], + ["self.out","add_all__U203.out"], + ["mul_d0__U195.in0","coeff_0_U194.out"], + ["mul_d1__U197.in0","coeff_1_U196.out"], + ["mul_d2__U199.in0","coeff_2_U198.out"], + ["self.d.0","mul_d0__U195.in1"], + ["self.d.1","mul_d1__U197.in1"], + ["self.d.2","mul_d2__U199.in1"] ] }, - "aff__U280":{ + "aff__U206":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U298":{ + "add_all__U224":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U299":{ + "add_all__U225":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U300":{ + "add_all__U226":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U301":{ + "add_all__U227":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U302":{ + "add_all__U228":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U303":{ + "add_all__U229":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U304":{ + "add_all__U230":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U305":{ + "add_all__U231":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U281":{ + "coeff_0_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U283":{ + "coeff_1_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004000"]} }, - "coeff_2_U285":{ + "coeff_2_U211":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U287":{ + "coeff_3_U213":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001000"]} }, - "coeff_4_U289":{ + "coeff_4_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000200"]} }, - "coeff_5_U291":{ + "coeff_5_U217":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_6_U293":{ + "coeff_6_U219":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U295":{ + "coeff_7_U221":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U297":{ + "const_term_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003fff"]} }, - "mul_d0__U282":{ + "mul_d0__U208":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U210":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U212":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U214":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U284":{ + "mul_d4__U216":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U286":{ + "mul_d5__U218":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U288":{ + "mul_d6__U220":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U290":{ + "mul_d7__U222":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U208.out","add_all__U224.in0"], + ["mul_d1__U210.out","add_all__U224.in1"], + ["add_all__U225.in0","add_all__U224.out"], + ["mul_d2__U212.out","add_all__U225.in1"], + ["add_all__U226.in0","add_all__U225.out"], + ["mul_d3__U214.out","add_all__U226.in1"], + ["add_all__U227.in0","add_all__U226.out"], + ["mul_d4__U216.out","add_all__U227.in1"], + ["add_all__U228.in0","add_all__U227.out"], + ["mul_d5__U218.out","add_all__U228.in1"], + ["add_all__U229.in0","add_all__U228.out"], + ["mul_d6__U220.out","add_all__U229.in1"], + ["add_all__U230.in0","add_all__U229.out"], + ["mul_d7__U222.out","add_all__U230.in1"], + ["add_all__U231.in0","add_all__U230.out"], + ["const_term_U223.out","add_all__U231.in1"], + ["self.out","add_all__U231.out"], + ["mul_d0__U208.in0","coeff_0_U207.out"], + ["mul_d1__U210.in0","coeff_1_U209.out"], + ["mul_d2__U212.in0","coeff_2_U211.out"], + ["mul_d3__U214.in0","coeff_3_U213.out"], + ["mul_d4__U216.in0","coeff_4_U215.out"], + ["mul_d5__U218.in0","coeff_5_U217.out"], + ["mul_d6__U220.in0","coeff_6_U219.out"], + ["mul_d7__U222.in0","coeff_7_U221.out"], + ["self.d.0","mul_d0__U208.in1"], + ["self.d.1","mul_d1__U210.in1"], + ["self.d.2","mul_d2__U212.in1"], + ["self.d.3","mul_d3__U214.in1"], + ["self.d.4","mul_d4__U216.in1"], + ["self.d.5","mul_d5__U218.in1"], + ["self.d.6","mul_d6__U220.in1"], + ["self.d.7","mul_d7__U222.in1"] + ] + }, + "aff__U26":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",3,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U34":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "mul_d5__U292":{ + "add_all__U35":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U36":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "coeff_2_U31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "const_term_U33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U28":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U294":{ + "mul_d1__U30":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U296":{ + "mul_d2__U32":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U282.out","add_all__U298.in0"], - ["mul_d1__U284.out","add_all__U298.in1"], - ["add_all__U299.in0","add_all__U298.out"], - ["mul_d2__U286.out","add_all__U299.in1"], - ["add_all__U300.in0","add_all__U299.out"], - ["mul_d3__U288.out","add_all__U300.in1"], - ["add_all__U301.in0","add_all__U300.out"], - ["mul_d4__U290.out","add_all__U301.in1"], - ["add_all__U302.in0","add_all__U301.out"], - ["mul_d5__U292.out","add_all__U302.in1"], - ["add_all__U303.in0","add_all__U302.out"], - ["mul_d6__U294.out","add_all__U303.in1"], - ["add_all__U304.in0","add_all__U303.out"], - ["mul_d7__U296.out","add_all__U304.in1"], - ["add_all__U305.in0","add_all__U304.out"], - ["const_term_U297.out","add_all__U305.in1"], - ["self.out","add_all__U305.out"], - ["mul_d0__U282.in0","coeff_0_U281.out"], - ["mul_d1__U284.in0","coeff_1_U283.out"], - ["mul_d2__U286.in0","coeff_2_U285.out"], - ["mul_d3__U288.in0","coeff_3_U287.out"], - ["mul_d4__U290.in0","coeff_4_U289.out"], - ["mul_d5__U292.in0","coeff_5_U291.out"], - ["mul_d6__U294.in0","coeff_6_U293.out"], - ["mul_d7__U296.in0","coeff_7_U295.out"], - ["self.d.0","mul_d0__U282.in1"], - ["self.d.1","mul_d1__U284.in1"], - ["self.d.2","mul_d2__U286.in1"], - ["self.d.3","mul_d3__U288.in1"], - ["self.d.4","mul_d4__U290.in1"], - ["self.d.5","mul_d5__U292.in1"], - ["self.d.6","mul_d6__U294.in1"], - ["self.d.7","mul_d7__U296.in1"] + ["mul_d0__U28.out","add_all__U34.in0"], + ["mul_d1__U30.out","add_all__U34.in1"], + ["add_all__U35.in0","add_all__U34.out"], + ["mul_d2__U32.out","add_all__U35.in1"], + ["add_all__U36.in0","add_all__U35.out"], + ["const_term_U33.out","add_all__U36.in1"], + ["self.out","add_all__U36.out"], + ["mul_d0__U28.in0","coeff_0_U27.out"], + ["mul_d1__U30.in0","coeff_1_U29.out"], + ["mul_d2__U32.in0","coeff_2_U31.out"], + ["self.d.0","mul_d0__U28.in1"], + ["self.d.1","mul_d1__U30.in1"], + ["self.d.2","mul_d2__U32.in1"] ] }, - "aff__U337":{ + "aff__U263":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U355":{ + "add_all__U281":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U356":{ + "add_all__U282":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U357":{ + "add_all__U283":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U358":{ + "add_all__U284":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U359":{ + "add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U360":{ + "add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U361":{ + "add_all__U287":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U362":{ + "add_all__U288":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U338":{ + "coeff_0_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U340":{ + "coeff_1_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U342":{ + "coeff_2_U268":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U344":{ + "coeff_3_U270":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U346":{ + "coeff_4_U272":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U348":{ + "coeff_5_U274":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U350":{ + "coeff_6_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_7_U352":{ + "coeff_7_U278":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U354":{ + "const_term_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U339":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U341":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U343":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U345":{ + "mul_d0__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U347":{ + "mul_d1__U267":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U349":{ + "mul_d2__U269":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U351":{ + "mul_d3__U271":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U353":{ + "mul_d4__U273":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U339.out","add_all__U355.in0"], - ["mul_d1__U341.out","add_all__U355.in1"], - ["add_all__U356.in0","add_all__U355.out"], - ["mul_d2__U343.out","add_all__U356.in1"], - ["add_all__U357.in0","add_all__U356.out"], - ["mul_d3__U345.out","add_all__U357.in1"], - ["add_all__U358.in0","add_all__U357.out"], - ["mul_d4__U347.out","add_all__U358.in1"], - ["add_all__U359.in0","add_all__U358.out"], - ["mul_d5__U349.out","add_all__U359.in1"], - ["add_all__U360.in0","add_all__U359.out"], - ["mul_d6__U351.out","add_all__U360.in1"], - ["add_all__U361.in0","add_all__U360.out"], - ["mul_d7__U353.out","add_all__U361.in1"], - ["add_all__U362.in0","add_all__U361.out"], - ["const_term_U354.out","add_all__U362.in1"], - ["self.out","add_all__U362.out"], - ["mul_d0__U339.in0","coeff_0_U338.out"], - ["mul_d1__U341.in0","coeff_1_U340.out"], - ["mul_d2__U343.in0","coeff_2_U342.out"], - ["mul_d3__U345.in0","coeff_3_U344.out"], - ["mul_d4__U347.in0","coeff_4_U346.out"], - ["mul_d5__U349.in0","coeff_5_U348.out"], - ["mul_d6__U351.in0","coeff_6_U350.out"], - ["mul_d7__U353.in0","coeff_7_U352.out"], - ["self.d.0","mul_d0__U339.in1"], - ["self.d.1","mul_d1__U341.in1"], - ["self.d.2","mul_d2__U343.in1"], - ["self.d.3","mul_d3__U345.in1"], - ["self.d.4","mul_d4__U347.in1"], - ["self.d.5","mul_d5__U349.in1"], - ["self.d.6","mul_d6__U351.in1"], - ["self.d.7","mul_d7__U353.in1"] - ] - }, - "aff__U35":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",3,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U43":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U44":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U45":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U36":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U38":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_2_U40":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "const_term_U42":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U37":{ + "mul_d5__U275":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U39":{ + "mul_d6__U277":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U41":{ + "mul_d7__U279":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U37.out","add_all__U43.in0"], - ["mul_d1__U39.out","add_all__U43.in1"], - ["add_all__U44.in0","add_all__U43.out"], - ["mul_d2__U41.out","add_all__U44.in1"], - ["add_all__U45.in0","add_all__U44.out"], - ["const_term_U42.out","add_all__U45.in1"], - ["self.out","add_all__U45.out"], - ["mul_d0__U37.in0","coeff_0_U36.out"], - ["mul_d1__U39.in0","coeff_1_U38.out"], - ["mul_d2__U41.in0","coeff_2_U40.out"], - ["self.d.0","mul_d0__U37.in1"], - ["self.d.1","mul_d1__U39.in1"], - ["self.d.2","mul_d2__U41.in1"] + ["mul_d0__U265.out","add_all__U281.in0"], + ["mul_d1__U267.out","add_all__U281.in1"], + ["add_all__U282.in0","add_all__U281.out"], + ["mul_d2__U269.out","add_all__U282.in1"], + ["add_all__U283.in0","add_all__U282.out"], + ["mul_d3__U271.out","add_all__U283.in1"], + ["add_all__U284.in0","add_all__U283.out"], + ["mul_d4__U273.out","add_all__U284.in1"], + ["add_all__U285.in0","add_all__U284.out"], + ["mul_d5__U275.out","add_all__U285.in1"], + ["add_all__U286.in0","add_all__U285.out"], + ["mul_d6__U277.out","add_all__U286.in1"], + ["add_all__U287.in0","add_all__U286.out"], + ["mul_d7__U279.out","add_all__U287.in1"], + ["add_all__U288.in0","add_all__U287.out"], + ["const_term_U280.out","add_all__U288.in1"], + ["self.out","add_all__U288.out"], + ["mul_d0__U265.in0","coeff_0_U264.out"], + ["mul_d1__U267.in0","coeff_1_U266.out"], + ["mul_d2__U269.in0","coeff_2_U268.out"], + ["mul_d3__U271.in0","coeff_3_U270.out"], + ["mul_d4__U273.in0","coeff_4_U272.out"], + ["mul_d5__U275.in0","coeff_5_U274.out"], + ["mul_d6__U277.in0","coeff_6_U276.out"], + ["mul_d7__U279.in0","coeff_7_U278.out"], + ["self.d.0","mul_d0__U265.in1"], + ["self.d.1","mul_d1__U267.in1"], + ["self.d.2","mul_d2__U269.in1"], + ["self.d.3","mul_d3__U271.in1"], + ["self.d.4","mul_d4__U273.in1"], + ["self.d.5","mul_d5__U275.in1"], + ["self.d.6","mul_d6__U277.in1"], + ["self.d.7","mul_d7__U279.in1"] ] }, - "aff__U383":{ + "aff__U300":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U397":{ + "add_all__U314":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U398":{ + "add_all__U315":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U399":{ + "add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U400":{ + "add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U401":{ + "add_all__U318":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U402":{ + "add_all__U319":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U384":{ + "coeff_0_U301":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U386":{ + "coeff_1_U303":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004000"]} }, - "coeff_2_U388":{ + "coeff_2_U305":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U390":{ + "coeff_3_U307":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U392":{ + "coeff_4_U309":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U394":{ + "coeff_5_U311":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U396":{ + "const_term_U313":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007000"]} }, - "mul_d0__U385":{ + "mul_d0__U302":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U387":{ + "mul_d1__U304":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U389":{ + "mul_d2__U306":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U391":{ + "mul_d3__U308":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U393":{ + "mul_d4__U310":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U395":{ + "mul_d5__U312":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U385.out","add_all__U397.in0"], - ["mul_d1__U387.out","add_all__U397.in1"], - ["add_all__U398.in0","add_all__U397.out"], - ["mul_d2__U389.out","add_all__U398.in1"], - ["add_all__U399.in0","add_all__U398.out"], - ["mul_d3__U391.out","add_all__U399.in1"], - ["add_all__U400.in0","add_all__U399.out"], - ["mul_d4__U393.out","add_all__U400.in1"], - ["add_all__U401.in0","add_all__U400.out"], - ["mul_d5__U395.out","add_all__U401.in1"], - ["add_all__U402.in0","add_all__U401.out"], - ["const_term_U396.out","add_all__U402.in1"], - ["self.out","add_all__U402.out"], - ["mul_d0__U385.in0","coeff_0_U384.out"], - ["mul_d1__U387.in0","coeff_1_U386.out"], - ["mul_d2__U389.in0","coeff_2_U388.out"], - ["mul_d3__U391.in0","coeff_3_U390.out"], - ["mul_d4__U393.in0","coeff_4_U392.out"], - ["mul_d5__U395.in0","coeff_5_U394.out"], - ["self.d.0","mul_d0__U385.in1"], - ["self.d.1","mul_d1__U387.in1"], - ["self.d.2","mul_d2__U389.in1"], - ["self.d.3","mul_d3__U391.in1"], - ["self.d.4","mul_d4__U393.in1"], - ["self.d.5","mul_d5__U395.in1"] + ["mul_d0__U302.out","add_all__U314.in0"], + ["mul_d1__U304.out","add_all__U314.in1"], + ["add_all__U315.in0","add_all__U314.out"], + ["mul_d2__U306.out","add_all__U315.in1"], + ["add_all__U316.in0","add_all__U315.out"], + ["mul_d3__U308.out","add_all__U316.in1"], + ["add_all__U317.in0","add_all__U316.out"], + ["mul_d4__U310.out","add_all__U317.in1"], + ["add_all__U318.in0","add_all__U317.out"], + ["mul_d5__U312.out","add_all__U318.in1"], + ["add_all__U319.in0","add_all__U318.out"], + ["const_term_U313.out","add_all__U319.in1"], + ["self.out","add_all__U319.out"], + ["mul_d0__U302.in0","coeff_0_U301.out"], + ["mul_d1__U304.in0","coeff_1_U303.out"], + ["mul_d2__U306.in0","coeff_2_U305.out"], + ["mul_d3__U308.in0","coeff_3_U307.out"], + ["mul_d4__U310.in0","coeff_4_U309.out"], + ["mul_d5__U312.in0","coeff_5_U311.out"], + ["self.d.0","mul_d0__U302.in1"], + ["self.d.1","mul_d1__U304.in1"], + ["self.d.2","mul_d2__U306.in1"], + ["self.d.3","mul_d3__U308.in1"], + ["self.d.4","mul_d4__U310.in1"], + ["self.d.5","mul_d5__U312.in1"] ] }, - "aff__U421":{ + "aff__U338":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U435":{ + "add_all__U352":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U436":{ + "add_all__U353":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U437":{ + "add_all__U354":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U438":{ + "add_all__U355":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U439":{ + "add_all__U356":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U440":{ + "add_all__U357":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U422":{ + "coeff_0_U339":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U424":{ + "coeff_1_U341":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_2_U426":{ + "coeff_2_U343":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U428":{ + "coeff_3_U345":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U430":{ + "coeff_4_U347":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_5_U432":{ + "coeff_5_U349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U434":{ + "const_term_U351":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U423":{ + "mul_d0__U340":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U425":{ + "mul_d1__U342":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U427":{ + "mul_d2__U344":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U429":{ + "mul_d3__U346":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U431":{ + "mul_d4__U348":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U433":{ + "mul_d5__U350":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U423.out","add_all__U435.in0"], - ["mul_d1__U425.out","add_all__U435.in1"], - ["add_all__U436.in0","add_all__U435.out"], - ["mul_d2__U427.out","add_all__U436.in1"], - ["add_all__U437.in0","add_all__U436.out"], - ["mul_d3__U429.out","add_all__U437.in1"], - ["add_all__U438.in0","add_all__U437.out"], - ["mul_d4__U431.out","add_all__U438.in1"], - ["add_all__U439.in0","add_all__U438.out"], - ["mul_d5__U433.out","add_all__U439.in1"], - ["add_all__U440.in0","add_all__U439.out"], - ["const_term_U434.out","add_all__U440.in1"], - ["self.out","add_all__U440.out"], - ["mul_d0__U423.in0","coeff_0_U422.out"], - ["mul_d1__U425.in0","coeff_1_U424.out"], - ["mul_d2__U427.in0","coeff_2_U426.out"], - ["mul_d3__U429.in0","coeff_3_U428.out"], - ["mul_d4__U431.in0","coeff_4_U430.out"], - ["mul_d5__U433.in0","coeff_5_U432.out"], - ["self.d.0","mul_d0__U423.in1"], - ["self.d.1","mul_d1__U425.in1"], - ["self.d.2","mul_d2__U427.in1"], - ["self.d.3","mul_d3__U429.in1"], - ["self.d.4","mul_d4__U431.in1"], - ["self.d.5","mul_d5__U433.in1"] + ["mul_d0__U340.out","add_all__U352.in0"], + ["mul_d1__U342.out","add_all__U352.in1"], + ["add_all__U353.in0","add_all__U352.out"], + ["mul_d2__U344.out","add_all__U353.in1"], + ["add_all__U354.in0","add_all__U353.out"], + ["mul_d3__U346.out","add_all__U354.in1"], + ["add_all__U355.in0","add_all__U354.out"], + ["mul_d4__U348.out","add_all__U355.in1"], + ["add_all__U356.in0","add_all__U355.out"], + ["mul_d5__U350.out","add_all__U356.in1"], + ["add_all__U357.in0","add_all__U356.out"], + ["const_term_U351.out","add_all__U357.in1"], + ["self.out","add_all__U357.out"], + ["mul_d0__U340.in0","coeff_0_U339.out"], + ["mul_d1__U342.in0","coeff_1_U341.out"], + ["mul_d2__U344.in0","coeff_2_U343.out"], + ["mul_d3__U346.in0","coeff_3_U345.out"], + ["mul_d4__U348.in0","coeff_4_U347.out"], + ["mul_d5__U350.in0","coeff_5_U349.out"], + ["self.d.0","mul_d0__U340.in1"], + ["self.d.1","mul_d1__U342.in1"], + ["self.d.2","mul_d2__U344.in1"], + ["self.d.3","mul_d3__U346.in1"], + ["self.d.4","mul_d4__U348.in1"], + ["self.d.5","mul_d5__U350.in1"] ] }, - "aff__U443":{ + "aff__U360":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U453":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U444":{ + "coeff_0_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U446":{ + "coeff_1_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_2_U448":{ + "coeff_2_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U450":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000dfff"]} }, - "mul_d0__U445":{ + "mul_d0__U362":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U447":{ + "mul_d1__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U449":{ + "mul_d2__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U445.out","add_all__U451.in0"], - ["mul_d1__U447.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["mul_d2__U449.out","add_all__U452.in1"], - ["add_all__U453.in0","add_all__U452.out"], - ["const_term_U450.out","add_all__U453.in1"], - ["self.out","add_all__U453.out"], - ["mul_d0__U445.in0","coeff_0_U444.out"], - ["mul_d1__U447.in0","coeff_1_U446.out"], - ["mul_d2__U449.in0","coeff_2_U448.out"], - ["self.d.0","mul_d0__U445.in1"], - ["self.d.1","mul_d1__U447.in1"], - ["self.d.2","mul_d2__U449.in1"] + ["mul_d0__U362.out","add_all__U368.in0"], + ["mul_d1__U364.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["mul_d2__U366.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["const_term_U367.out","add_all__U370.in1"], + ["self.out","add_all__U370.out"], + ["mul_d0__U362.in0","coeff_0_U361.out"], + ["mul_d1__U364.in0","coeff_1_U363.out"], + ["mul_d2__U366.in0","coeff_2_U365.out"], + ["self.d.0","mul_d0__U362.in1"], + ["self.d.1","mul_d1__U364.in1"], + ["self.d.2","mul_d2__U366.in1"] ] }, - "aff__U460":{ + "aff__U377":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",3,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U468":{ + "add_all__U385":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U469":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U470":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U461":{ + "coeff_0_U378":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U463":{ + "coeff_1_U380":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U465":{ + "coeff_2_U382":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U467":{ + "const_term_U384":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U462":{ + "mul_d0__U379":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U464":{ + "mul_d1__U381":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U466":{ + "mul_d2__U383":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U462.out","add_all__U468.in0"], - ["mul_d1__U464.out","add_all__U468.in1"], - ["add_all__U469.in0","add_all__U468.out"], - ["mul_d2__U466.out","add_all__U469.in1"], - ["add_all__U470.in0","add_all__U469.out"], - ["const_term_U467.out","add_all__U470.in1"], - ["self.out","add_all__U470.out"], - ["mul_d0__U462.in0","coeff_0_U461.out"], - ["mul_d1__U464.in0","coeff_1_U463.out"], - ["mul_d2__U466.in0","coeff_2_U465.out"], - ["self.d.0","mul_d0__U462.in1"], - ["self.d.1","mul_d1__U464.in1"], - ["self.d.2","mul_d2__U466.in1"] + ["mul_d0__U379.out","add_all__U385.in0"], + ["mul_d1__U381.out","add_all__U385.in1"], + ["add_all__U386.in0","add_all__U385.out"], + ["mul_d2__U383.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["const_term_U384.out","add_all__U387.in1"], + ["self.out","add_all__U387.out"], + ["mul_d0__U379.in0","coeff_0_U378.out"], + ["mul_d1__U381.in0","coeff_1_U380.out"], + ["mul_d2__U383.in0","coeff_2_U382.out"], + ["self.d.0","mul_d0__U379.in1"], + ["self.d.1","mul_d1__U381.in1"], + ["self.d.2","mul_d2__U383.in1"] ] }, - "aff__U48":{ + "aff__U39":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U64":{ + "add_all__U55":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U65":{ + "add_all__U56":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U66":{ + "add_all__U57":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U67":{ + "add_all__U58":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U68":{ + "add_all__U59":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U69":{ + "add_all__U60":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U70":{ + "add_all__U61":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U49":{ + "coeff_0_U40":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U51":{ + "coeff_1_U42":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004000"]} }, - "coeff_2_U53":{ + "coeff_2_U44":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U55":{ + "coeff_3_U46":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001000"]} }, - "coeff_4_U57":{ + "coeff_4_U48":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_5_U59":{ + "coeff_5_U50":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_6_U61":{ + "coeff_6_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U63":{ + "const_term_U54":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003fff"]} }, - "mul_d0__U50":{ + "mul_d0__U41":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U52":{ + "mul_d1__U43":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U54":{ + "mul_d2__U45":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U56":{ + "mul_d3__U47":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U58":{ + "mul_d4__U49":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U60":{ + "mul_d5__U51":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U62":{ + "mul_d6__U53":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U50.out","add_all__U64.in0"], - ["mul_d1__U52.out","add_all__U64.in1"], - ["add_all__U65.in0","add_all__U64.out"], - ["mul_d2__U54.out","add_all__U65.in1"], - ["add_all__U66.in0","add_all__U65.out"], - ["mul_d3__U56.out","add_all__U66.in1"], - ["add_all__U67.in0","add_all__U66.out"], - ["mul_d4__U58.out","add_all__U67.in1"], - ["add_all__U68.in0","add_all__U67.out"], - ["mul_d5__U60.out","add_all__U68.in1"], - ["add_all__U69.in0","add_all__U68.out"], - ["mul_d6__U62.out","add_all__U69.in1"], - ["add_all__U70.in0","add_all__U69.out"], - ["const_term_U63.out","add_all__U70.in1"], - ["self.out","add_all__U70.out"], - ["mul_d0__U50.in0","coeff_0_U49.out"], - ["mul_d1__U52.in0","coeff_1_U51.out"], - ["mul_d2__U54.in0","coeff_2_U53.out"], - ["mul_d3__U56.in0","coeff_3_U55.out"], - ["mul_d4__U58.in0","coeff_4_U57.out"], - ["mul_d5__U60.in0","coeff_5_U59.out"], - ["mul_d6__U62.in0","coeff_6_U61.out"], - ["self.d.0","mul_d0__U50.in1"], - ["self.d.1","mul_d1__U52.in1"], - ["self.d.2","mul_d2__U54.in1"], - ["self.d.3","mul_d3__U56.in1"], - ["self.d.4","mul_d4__U58.in1"], - ["self.d.5","mul_d5__U60.in1"], - ["self.d.6","mul_d6__U62.in1"] + ["mul_d0__U41.out","add_all__U55.in0"], + ["mul_d1__U43.out","add_all__U55.in1"], + ["add_all__U56.in0","add_all__U55.out"], + ["mul_d2__U45.out","add_all__U56.in1"], + ["add_all__U57.in0","add_all__U56.out"], + ["mul_d3__U47.out","add_all__U57.in1"], + ["add_all__U58.in0","add_all__U57.out"], + ["mul_d4__U49.out","add_all__U58.in1"], + ["add_all__U59.in0","add_all__U58.out"], + ["mul_d5__U51.out","add_all__U59.in1"], + ["add_all__U60.in0","add_all__U59.out"], + ["mul_d6__U53.out","add_all__U60.in1"], + ["add_all__U61.in0","add_all__U60.out"], + ["const_term_U54.out","add_all__U61.in1"], + ["self.out","add_all__U61.out"], + ["mul_d0__U41.in0","coeff_0_U40.out"], + ["mul_d1__U43.in0","coeff_1_U42.out"], + ["mul_d2__U45.in0","coeff_2_U44.out"], + ["mul_d3__U47.in0","coeff_3_U46.out"], + ["mul_d4__U49.in0","coeff_4_U48.out"], + ["mul_d5__U51.in0","coeff_5_U50.out"], + ["mul_d6__U53.in0","coeff_6_U52.out"], + ["self.d.0","mul_d0__U41.in1"], + ["self.d.1","mul_d1__U43.in1"], + ["self.d.2","mul_d2__U45.in1"], + ["self.d.3","mul_d3__U47.in1"], + ["self.d.4","mul_d4__U49.in1"], + ["self.d.5","mul_d5__U51.in1"], + ["self.d.6","mul_d6__U53.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U115":{ + "add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U116":{ + "add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U117":{ + "add_all__U108":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_6_U108":{ + "coeff_6_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "const_term_U110":{ + "const_term_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U90":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U92":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U94":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U101":{ + "mul_d5__U98":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d6__U100":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U88.out","add_all__U102.in0"], + ["mul_d1__U90.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d2__U92.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d3__U94.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["mul_d4__U96.out","add_all__U105.in1"], + ["add_all__U106.in0","add_all__U105.out"], + ["mul_d5__U98.out","add_all__U106.in1"], + ["add_all__U107.in0","add_all__U106.out"], + ["mul_d6__U100.out","add_all__U107.in1"], + ["add_all__U108.in0","add_all__U107.out"], + ["const_term_U101.out","add_all__U108.in1"], + ["self.out","add_all__U108.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["mul_d6__U100.in0","coeff_6_U99.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"], + ["self.d.6","mul_d6__U100.in1"] + ] + }, + "aff__U9":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",3,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U17":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "add_all__U18":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U19":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "const_term_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U109":{ + "mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U111.in0"], - ["mul_d1__U99.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d2__U101.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d3__U103.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["mul_d4__U105.out","add_all__U114.in1"], - ["add_all__U115.in0","add_all__U114.out"], - ["mul_d5__U107.out","add_all__U115.in1"], - ["add_all__U116.in0","add_all__U115.out"], - ["mul_d6__U109.out","add_all__U116.in1"], - ["add_all__U117.in0","add_all__U116.out"], - ["const_term_U110.out","add_all__U117.in1"], - ["self.out","add_all__U117.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["mul_d6__U109.in0","coeff_6_U108.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"], - ["self.d.6","mul_d6__U109.in1"] + ["mul_d0__U11.out","add_all__U17.in0"], + ["mul_d1__U13.out","add_all__U17.in1"], + ["add_all__U18.in0","add_all__U17.out"], + ["mul_d2__U15.out","add_all__U18.in1"], + ["add_all__U19.in0","add_all__U18.out"], + ["const_term_U16.out","add_all__U19.in1"], + ["self.out","add_all__U19.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"] ] }, - "affine_controller__U17":{ + "affine_controller__U175":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1452,67 +1452,67 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U29":{ + "_U187":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U291":{ + "_U1871":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U292":{ + "_U1872":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U30":{ + "_U188":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U26":{ + "affine_func$add_all__U184":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U27":{ + "affine_func$add_all__U185":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U28":{ + "affine_func$add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U19":{ + "affine_func$coeff_0_U177":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U21":{ + "affine_func$coeff_1_U179":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "affine_func$coeff_2_U23":{ + "affine_func$coeff_2_U181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U25":{ + "affine_func$const_term_U183":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U20":{ + "affine_func$mul_d0__U178":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U22":{ + "affine_func$mul_d1__U180":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U24":{ + "affine_func$mul_d2__U182":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -1576,22 +1576,22 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U31$c0_lutcnst":{ + "d_0_am__U189$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U31$lut$lut":{ + "d_0_am__U189$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U32$c0_lutcnst":{ + "d_0_am__U190$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U32$lut$lut":{ + "d_0_am__U190$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1640,12 +1640,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U33$c0_lutcnst":{ + "d_1_am__U191$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U33$lut$lut":{ + "d_1_am__U191$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1769,23 +1769,23 @@ } }, "connections":[ - ["d_0_inc.in1","_U29.out"], - ["d_1_inc.in1","_U291.out"], - ["d_2_inc.in1","_U292.out"], - ["cmp_time.in1","_U30.out"], - ["affine_func$mul_d0__U20.out","affine_func$add_all__U26.in0"], - ["affine_func$mul_d1__U22.out","affine_func$add_all__U26.in1"], - ["affine_func$add_all__U27.in0","affine_func$add_all__U26.out"], - ["affine_func$mul_d2__U24.out","affine_func$add_all__U27.in1"], - ["affine_func$add_all__U28.in0","affine_func$add_all__U27.out"], - ["affine_func$const_term_U25.out","affine_func$add_all__U28.in1"], - ["time_diff.in0","affine_func$add_all__U28.out"], - ["affine_func$mul_d0__U20.in0","affine_func$coeff_0_U19.out"], - ["affine_func$mul_d1__U22.in0","affine_func$coeff_1_U21.out"], - ["affine_func$mul_d2__U24.in0","affine_func$coeff_2_U23.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U20.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U22.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U24.in1"], + ["d_0_inc.in1","_U187.out"], + ["d_1_inc.in1","_U1871.out"], + ["d_2_inc.in1","_U1872.out"], + ["cmp_time.in1","_U188.out"], + ["affine_func$mul_d0__U178.out","affine_func$add_all__U184.in0"], + ["affine_func$mul_d1__U180.out","affine_func$add_all__U184.in1"], + ["affine_func$add_all__U185.in0","affine_func$add_all__U184.out"], + ["affine_func$mul_d2__U182.out","affine_func$add_all__U185.in1"], + ["affine_func$add_all__U186.in0","affine_func$add_all__U185.out"], + ["affine_func$const_term_U183.out","affine_func$add_all__U186.in1"], + ["time_diff.in0","affine_func$add_all__U186.out"], + ["affine_func$mul_d0__U178.in0","affine_func$coeff_0_U177.out"], + ["affine_func$mul_d1__U180.in0","affine_func$coeff_1_U179.out"], + ["affine_func$mul_d2__U182.in0","affine_func$coeff_2_U181.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U178.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U180.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U182.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -1809,13 +1809,13 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U31$lut$lut.bit.in.2","d_0_am__U31$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U31$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U31$lut$lut.bit.in.1"], - ["d_0_am__U32$lut$lut.bit.in.0","d_0_am__U31$lut$lut.bit.out"], - ["d_0_am__U32$lut$lut.bit.in.2","d_0_am__U32$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U32$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U32$lut$lut.bit.out"], + ["d_0_am__U189$lut$lut.bit.in.2","d_0_am__U189$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U189$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U189$lut$lut.bit.in.1"], + ["d_0_am__U190$lut$lut.bit.in.0","d_0_am__U189$lut$lut.bit.out"], + ["d_0_am__U190$lut$lut.bit.in.2","d_0_am__U190$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U190$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U190$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1832,10 +1832,10 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U33$lut$lut.bit.in.2","d_1_am__U33$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U33$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U33$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U33$lut$lut.bit.out"], + ["d_1_am__U191$lut$lut.bit.in.2","d_1_am__U191$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U191$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U191$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U191$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1871,130 +1871,220 @@ ["self.d.2","d_2_reg$reg0.out"] ] }, - "affine_controller__U249":{ + "affine_controller__U205":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",3,["Array",32,"Bit"]]], + ["d",["Array",8,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U261":{ + "_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2611":{ + "_U2321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2612":{ + "_U2322":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U262":{ + "_U2323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$add_all__U258":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U259":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$add_all__U260":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "_U2324":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$coeff_0_U251":{ + "_U2325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$coeff_1_U253":{ + "_U2326":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$coeff_2_U255":{ + "_U2327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U257":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U252":{ - "genref":"coreir.mul", + "affine_func$add_all__U224":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U254":{ - "genref":"coreir.mul", + "affine_func$add_all__U225":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U256":{ - "genref":"coreir.mul", + "affine_func$add_all__U226":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "cmp_time":{ - "genref":"coreir.eq", + "affine_func$add_all__U227":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "cycle_time$add":{ + "affine_func$add_all__U228":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "cycle_time$and$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$add_all__U229":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "cycle_time$and$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "affine_func$add_all__U230":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "cycle_time$count$c0":{ + "affine_func$add_all__U231":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$count$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func$coeff_1_U209":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00004000"]} }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", + "affine_func$coeff_2_U211":{ + "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "cycle_time$inc":{ + "affine_func$coeff_3_U213":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00001000"]} }, - "cycle_time$max":{ + "affine_func$coeff_4_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + "modargs":{"value":[["BitVector",32],"32'h00000200"]} }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$coeff_5_U217":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "cycle_time$resetOr$lut$lut":{ + "affine_func$coeff_6_U219":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} + }, + "affine_func$coeff_7_U221":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U223":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00003fff"]} + }, + "affine_func$mul_d0__U208":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U210":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U212":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U214":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d4__U216":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U218":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d6__U220":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d7__U222":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$count$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} @@ -2003,22 +2093,72 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U263$c0_lutcnst":{ + "d_0_am__U234$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U234$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U235$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U235$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U236$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U236$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U237$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U237$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U238$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U238$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U239$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U263$lut$lut":{ + "d_0_am__U239$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U264$c0_lutcnst":{ + "d_0_am__U240$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U264$lut$lut":{ + "d_0_am__U240$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2067,12 +2207,62 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U265$c0_lutcnst":{ + "d_1_am__U241$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U265$lut$lut":{ + "d_1_am__U241$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U242$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U242$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U243$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U243$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U244$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U244$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U245$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U245$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U246$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U246$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2088,7 +2278,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2121,6 +2311,56 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_2_am__U247$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U247$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U248$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U248$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U249$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U249$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U250$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U250$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U251$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U251$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -2132,7 +2372,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2165,1091 +2405,424 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} + "d_3_am__U252$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true1_lutcnst":{ + "d_3_am__U252$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true2_lutcnst":{ + "d_3_am__U253$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true3_lutcnst":{ + "d_3_am__U253$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true4_lutcnst":{ + "d_3_am__U254$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true_lutcnst":{ + "d_3_am__U254$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U261.out"], - ["d_1_inc.in1","_U2611.out"], - ["d_2_inc.in1","_U2612.out"], - ["cmp_time.in1","_U262.out"], - ["affine_func$mul_d0__U252.out","affine_func$add_all__U258.in0"], - ["affine_func$mul_d1__U254.out","affine_func$add_all__U258.in1"], - ["affine_func$add_all__U259.in0","affine_func$add_all__U258.out"], - ["affine_func$mul_d2__U256.out","affine_func$add_all__U259.in1"], - ["affine_func$add_all__U260.in0","affine_func$add_all__U259.out"], - ["affine_func$const_term_U257.out","affine_func$add_all__U260.in1"], - ["time_diff.in0","affine_func$add_all__U260.out"], - ["affine_func$mul_d0__U252.in0","affine_func$coeff_0_U251.out"], - ["affine_func$mul_d1__U254.in0","affine_func$coeff_1_U253.out"], - ["affine_func$mul_d2__U256.in0","affine_func$coeff_2_U255.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U252.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U254.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U256.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true4_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U263$lut$lut.bit.in.2","d_0_am__U263$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U263$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U263$lut$lut.bit.in.1"], - ["d_0_am__U264$lut$lut.bit.in.0","d_0_am__U263$lut$lut.bit.out"], - ["d_0_am__U264$lut$lut.bit.in.2","d_0_am__U264$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U264$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U264$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U265$lut$lut.bit.in.2","d_1_am__U265$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U265$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U265$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U265$lut$lut.bit.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["true_lutcnst.bit.out","d_2_next_value.sel"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"] - ] - }, - "affine_controller__U279":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",8,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U306":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "_U3061":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_3_am__U255$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "_U3062":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_3_am__U255$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "_U3063":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, - "_U3064":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "_U3065":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3066":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "_U3067":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "_U307":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U298":{ - "genref":"coreir.add", + "d_3_reg$clrMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U299":{ - "genref":"coreir.add", + "d_3_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U300":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U301":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_4_am__U256$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$add_all__U302":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_4_am__U256$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$add_all__U303":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_4_am__U257$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$add_all__U304":{ - "genref":"coreir.add", + "d_4_am__U257$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U258$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U258$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U305":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U281":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$coeff_1_U283":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00004000"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "affine_func$coeff_2_U285":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00002000"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_3_U287":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001000"]} + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "affine_func$coeff_4_U289":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000200"]} + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "affine_func$coeff_5_U291":{ + "d_4_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_6_U293":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "affine_func$coeff_7_U295":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "affine_func$const_term_U297":{ - "genref":"coreir.const", + "d_4_reg$reg0":{ + "genref":"coreir.reg", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003fff"]} + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U282":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_5_am__U259$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$mul_d1__U284":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_5_am__U259$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$mul_d2__U286":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_5_am__U260$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$mul_d3__U288":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_5_am__U260$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$mul_d4__U290":{ - "genref":"coreir.mul", + "d_5_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U292":{ - "genref":"coreir.mul", + "d_5_inc":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U294":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "affine_func$mul_d7__U296":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cmp_time":{ - "genref":"coreir.eq", + "d_5_next_value":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$add":{ - "genref":"coreir.add", + "d_5_next_value_at_max":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$and$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$and$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "cycle_time$count$c0":{ + "d_5_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$count$clrMux":{ + "d_5_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$enMux":{ + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} - }, - "cycle_time$ult":{ - "genref":"coreir.ult", - "genargs":{"width":["Int",32]} - }, - "d_0_am__U308$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U308$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U309$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U309$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U310$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U310$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U311$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U311$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U312$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U312$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U313$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U313$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U314$c0_lutcnst":{ + "d_6_am__U261$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U314$lut$lut":{ + "d_6_am__U261$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_6_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_6_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_6_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_0_min":{ + "d_6_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_6_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_6_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_6_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_6_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_6_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_6_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U315$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U315$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U316$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U316$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U317$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U317$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U318$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U318$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U319$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U319$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U320$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U320$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_at_max":{ + "d_7_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_7_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_7_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_1_min":{ + "d_7_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_7_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_7_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$c0":{ + "d_7_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ + "d_7_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ + "d_7_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ + "d_7_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U321$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U321$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U322$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U322$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U323$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} }, - "d_2_am__U323$lut$lut":{ + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U324$c0_lutcnst":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U324$lut$lut":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U325$c0_lutcnst":{ + "true4_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U325$lut$lut":{ + "true5_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_3_am__U326$c0_lutcnst":{ + "true6_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_3_am__U326$lut$lut":{ + "true7_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_3_am__U327$c0_lutcnst":{ + "true8_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_3_am__U327$lut$lut":{ + "true9_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_3_am__U328$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U328$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U329$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U329$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_am__U330$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U330$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U331$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U331$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U332$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U332$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_5_am__U333$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U333$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U334$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U334$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_5_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_5_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_5_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_6_am__U335$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_6_am__U335$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_6_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_6_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_6_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_6_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_7_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_7_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_7_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_7_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true2_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true3_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true_lutcnst":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} } }, "connections":[ - ["d_0_inc.in1","_U306.out"], - ["d_1_inc.in1","_U3061.out"], - ["d_2_inc.in1","_U3062.out"], - ["d_3_inc.in1","_U3063.out"], - ["d_4_inc.in1","_U3064.out"], - ["d_5_inc.in1","_U3065.out"], - ["d_6_inc.in1","_U3066.out"], - ["d_7_inc.in1","_U3067.out"], - ["cmp_time.in1","_U307.out"], - ["affine_func$mul_d0__U282.out","affine_func$add_all__U298.in0"], - ["affine_func$mul_d1__U284.out","affine_func$add_all__U298.in1"], - ["affine_func$add_all__U299.in0","affine_func$add_all__U298.out"], - ["affine_func$mul_d2__U286.out","affine_func$add_all__U299.in1"], - ["affine_func$add_all__U300.in0","affine_func$add_all__U299.out"], - ["affine_func$mul_d3__U288.out","affine_func$add_all__U300.in1"], - ["affine_func$add_all__U301.in0","affine_func$add_all__U300.out"], - ["affine_func$mul_d4__U290.out","affine_func$add_all__U301.in1"], - ["affine_func$add_all__U302.in0","affine_func$add_all__U301.out"], - ["affine_func$mul_d5__U292.out","affine_func$add_all__U302.in1"], - ["affine_func$add_all__U303.in0","affine_func$add_all__U302.out"], - ["affine_func$mul_d6__U294.out","affine_func$add_all__U303.in1"], - ["affine_func$add_all__U304.in0","affine_func$add_all__U303.out"], - ["affine_func$mul_d7__U296.out","affine_func$add_all__U304.in1"], - ["affine_func$add_all__U305.in0","affine_func$add_all__U304.out"], - ["affine_func$const_term_U297.out","affine_func$add_all__U305.in1"], - ["time_diff.in0","affine_func$add_all__U305.out"], - ["affine_func$mul_d0__U282.in0","affine_func$coeff_0_U281.out"], - ["affine_func$mul_d1__U284.in0","affine_func$coeff_1_U283.out"], - ["affine_func$mul_d2__U286.in0","affine_func$coeff_2_U285.out"], - ["affine_func$mul_d3__U288.in0","affine_func$coeff_3_U287.out"], - ["affine_func$mul_d4__U290.in0","affine_func$coeff_4_U289.out"], - ["affine_func$mul_d5__U292.in0","affine_func$coeff_5_U291.out"], - ["affine_func$mul_d6__U294.in0","affine_func$coeff_6_U293.out"], - ["affine_func$mul_d7__U296.in0","affine_func$coeff_7_U295.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U282.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U284.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U286.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U288.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U290.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U292.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U294.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U296.in1"], + ["d_0_inc.in1","_U232.out"], + ["d_1_inc.in1","_U2321.out"], + ["d_2_inc.in1","_U2322.out"], + ["d_3_inc.in1","_U2323.out"], + ["d_4_inc.in1","_U2324.out"], + ["d_5_inc.in1","_U2325.out"], + ["d_6_inc.in1","_U2326.out"], + ["d_7_inc.in1","_U2327.out"], + ["cmp_time.in1","_U233.out"], + ["affine_func$mul_d0__U208.out","affine_func$add_all__U224.in0"], + ["affine_func$mul_d1__U210.out","affine_func$add_all__U224.in1"], + ["affine_func$add_all__U225.in0","affine_func$add_all__U224.out"], + ["affine_func$mul_d2__U212.out","affine_func$add_all__U225.in1"], + ["affine_func$add_all__U226.in0","affine_func$add_all__U225.out"], + ["affine_func$mul_d3__U214.out","affine_func$add_all__U226.in1"], + ["affine_func$add_all__U227.in0","affine_func$add_all__U226.out"], + ["affine_func$mul_d4__U216.out","affine_func$add_all__U227.in1"], + ["affine_func$add_all__U228.in0","affine_func$add_all__U227.out"], + ["affine_func$mul_d5__U218.out","affine_func$add_all__U228.in1"], + ["affine_func$add_all__U229.in0","affine_func$add_all__U228.out"], + ["affine_func$mul_d6__U220.out","affine_func$add_all__U229.in1"], + ["affine_func$add_all__U230.in0","affine_func$add_all__U229.out"], + ["affine_func$mul_d7__U222.out","affine_func$add_all__U230.in1"], + ["affine_func$add_all__U231.in0","affine_func$add_all__U230.out"], + ["affine_func$const_term_U223.out","affine_func$add_all__U231.in1"], + ["time_diff.in0","affine_func$add_all__U231.out"], + ["affine_func$mul_d0__U208.in0","affine_func$coeff_0_U207.out"], + ["affine_func$mul_d1__U210.in0","affine_func$coeff_1_U209.out"], + ["affine_func$mul_d2__U212.in0","affine_func$coeff_2_U211.out"], + ["affine_func$mul_d3__U214.in0","affine_func$coeff_3_U213.out"], + ["affine_func$mul_d4__U216.in0","affine_func$coeff_4_U215.out"], + ["affine_func$mul_d5__U218.in0","affine_func$coeff_5_U217.out"], + ["affine_func$mul_d6__U220.in0","affine_func$coeff_6_U219.out"], + ["affine_func$mul_d7__U222.in0","affine_func$coeff_7_U221.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U208.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U210.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U212.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U214.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U216.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U218.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U220.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U222.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -3278,28 +2851,28 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U308$lut$lut.bit.in.2","d_0_am__U308$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U308$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U308$lut$lut.bit.in.1"], - ["d_0_am__U309$lut$lut.bit.in.0","d_0_am__U308$lut$lut.bit.out"], - ["d_0_am__U309$lut$lut.bit.in.2","d_0_am__U309$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U309$lut$lut.bit.in.1"], - ["d_0_am__U310$lut$lut.bit.in.0","d_0_am__U309$lut$lut.bit.out"], - ["d_0_am__U310$lut$lut.bit.in.2","d_0_am__U310$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U310$lut$lut.bit.in.1"], - ["d_0_am__U311$lut$lut.bit.in.0","d_0_am__U310$lut$lut.bit.out"], - ["d_0_am__U311$lut$lut.bit.in.2","d_0_am__U311$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U311$lut$lut.bit.in.1"], - ["d_0_am__U312$lut$lut.bit.in.0","d_0_am__U311$lut$lut.bit.out"], - ["d_0_am__U312$lut$lut.bit.in.2","d_0_am__U312$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U312$lut$lut.bit.in.1"], - ["d_0_am__U313$lut$lut.bit.in.0","d_0_am__U312$lut$lut.bit.out"], - ["d_0_am__U313$lut$lut.bit.in.2","d_0_am__U313$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U313$lut$lut.bit.in.1"], - ["d_0_am__U314$lut$lut.bit.in.0","d_0_am__U313$lut$lut.bit.out"], - ["d_0_am__U314$lut$lut.bit.in.2","d_0_am__U314$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U314$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U314$lut$lut.bit.out"], + ["d_0_am__U234$lut$lut.bit.in.2","d_0_am__U234$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U234$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U234$lut$lut.bit.in.1"], + ["d_0_am__U235$lut$lut.bit.in.0","d_0_am__U234$lut$lut.bit.out"], + ["d_0_am__U235$lut$lut.bit.in.2","d_0_am__U235$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U235$lut$lut.bit.in.1"], + ["d_0_am__U236$lut$lut.bit.in.0","d_0_am__U235$lut$lut.bit.out"], + ["d_0_am__U236$lut$lut.bit.in.2","d_0_am__U236$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U236$lut$lut.bit.in.1"], + ["d_0_am__U237$lut$lut.bit.in.0","d_0_am__U236$lut$lut.bit.out"], + ["d_0_am__U237$lut$lut.bit.in.2","d_0_am__U237$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U237$lut$lut.bit.in.1"], + ["d_0_am__U238$lut$lut.bit.in.0","d_0_am__U237$lut$lut.bit.out"], + ["d_0_am__U238$lut$lut.bit.in.2","d_0_am__U238$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U238$lut$lut.bit.in.1"], + ["d_0_am__U239$lut$lut.bit.in.0","d_0_am__U238$lut$lut.bit.out"], + ["d_0_am__U239$lut$lut.bit.in.2","d_0_am__U239$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U239$lut$lut.bit.in.1"], + ["d_0_am__U240$lut$lut.bit.in.0","d_0_am__U239$lut$lut.bit.out"], + ["d_0_am__U240$lut$lut.bit.in.2","d_0_am__U240$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U240$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U240$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3316,25 +2889,25 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U315$lut$lut.bit.in.2","d_1_am__U315$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U315$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U315$lut$lut.bit.in.1"], - ["d_1_am__U316$lut$lut.bit.in.0","d_1_am__U315$lut$lut.bit.out"], - ["d_1_am__U316$lut$lut.bit.in.2","d_1_am__U316$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U316$lut$lut.bit.in.1"], - ["d_1_am__U317$lut$lut.bit.in.0","d_1_am__U316$lut$lut.bit.out"], - ["d_1_am__U317$lut$lut.bit.in.2","d_1_am__U317$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U317$lut$lut.bit.in.1"], - ["d_1_am__U318$lut$lut.bit.in.0","d_1_am__U317$lut$lut.bit.out"], - ["d_1_am__U318$lut$lut.bit.in.2","d_1_am__U318$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U318$lut$lut.bit.in.1"], - ["d_1_am__U319$lut$lut.bit.in.0","d_1_am__U318$lut$lut.bit.out"], - ["d_1_am__U319$lut$lut.bit.in.2","d_1_am__U319$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U319$lut$lut.bit.in.1"], - ["d_1_am__U320$lut$lut.bit.in.0","d_1_am__U319$lut$lut.bit.out"], - ["d_1_am__U320$lut$lut.bit.in.2","d_1_am__U320$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U320$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U320$lut$lut.bit.out"], + ["d_1_am__U241$lut$lut.bit.in.2","d_1_am__U241$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U241$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U241$lut$lut.bit.in.1"], + ["d_1_am__U242$lut$lut.bit.in.0","d_1_am__U241$lut$lut.bit.out"], + ["d_1_am__U242$lut$lut.bit.in.2","d_1_am__U242$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U242$lut$lut.bit.in.1"], + ["d_1_am__U243$lut$lut.bit.in.0","d_1_am__U242$lut$lut.bit.out"], + ["d_1_am__U243$lut$lut.bit.in.2","d_1_am__U243$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U243$lut$lut.bit.in.1"], + ["d_1_am__U244$lut$lut.bit.in.0","d_1_am__U243$lut$lut.bit.out"], + ["d_1_am__U244$lut$lut.bit.in.2","d_1_am__U244$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U244$lut$lut.bit.in.1"], + ["d_1_am__U245$lut$lut.bit.in.0","d_1_am__U244$lut$lut.bit.out"], + ["d_1_am__U245$lut$lut.bit.in.2","d_1_am__U245$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U245$lut$lut.bit.in.1"], + ["d_1_am__U246$lut$lut.bit.in.0","d_1_am__U245$lut$lut.bit.out"], + ["d_1_am__U246$lut$lut.bit.in.2","d_1_am__U246$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U246$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U246$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3351,22 +2924,22 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U321$lut$lut.bit.in.2","d_2_am__U321$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U321$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U321$lut$lut.bit.in.1"], - ["d_2_am__U322$lut$lut.bit.in.0","d_2_am__U321$lut$lut.bit.out"], - ["d_2_am__U322$lut$lut.bit.in.2","d_2_am__U322$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U322$lut$lut.bit.in.1"], - ["d_2_am__U323$lut$lut.bit.in.0","d_2_am__U322$lut$lut.bit.out"], - ["d_2_am__U323$lut$lut.bit.in.2","d_2_am__U323$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U323$lut$lut.bit.in.1"], - ["d_2_am__U324$lut$lut.bit.in.0","d_2_am__U323$lut$lut.bit.out"], - ["d_2_am__U324$lut$lut.bit.in.2","d_2_am__U324$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U324$lut$lut.bit.in.1"], - ["d_2_am__U325$lut$lut.bit.in.0","d_2_am__U324$lut$lut.bit.out"], - ["d_2_am__U325$lut$lut.bit.in.2","d_2_am__U325$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U325$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U325$lut$lut.bit.out"], + ["d_2_am__U247$lut$lut.bit.in.2","d_2_am__U247$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U247$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U247$lut$lut.bit.in.1"], + ["d_2_am__U248$lut$lut.bit.in.0","d_2_am__U247$lut$lut.bit.out"], + ["d_2_am__U248$lut$lut.bit.in.2","d_2_am__U248$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U248$lut$lut.bit.in.1"], + ["d_2_am__U249$lut$lut.bit.in.0","d_2_am__U248$lut$lut.bit.out"], + ["d_2_am__U249$lut$lut.bit.in.2","d_2_am__U249$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U249$lut$lut.bit.in.1"], + ["d_2_am__U250$lut$lut.bit.in.0","d_2_am__U249$lut$lut.bit.out"], + ["d_2_am__U250$lut$lut.bit.in.2","d_2_am__U250$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U250$lut$lut.bit.in.1"], + ["d_2_am__U251$lut$lut.bit.in.0","d_2_am__U250$lut$lut.bit.out"], + ["d_2_am__U251$lut$lut.bit.in.2","d_2_am__U251$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U251$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U251$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3383,19 +2956,19 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U326$lut$lut.bit.in.2","d_3_am__U326$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U326$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U326$lut$lut.bit.in.1"], - ["d_3_am__U327$lut$lut.bit.in.0","d_3_am__U326$lut$lut.bit.out"], - ["d_3_am__U327$lut$lut.bit.in.2","d_3_am__U327$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U327$lut$lut.bit.in.1"], - ["d_3_am__U328$lut$lut.bit.in.0","d_3_am__U327$lut$lut.bit.out"], - ["d_3_am__U328$lut$lut.bit.in.2","d_3_am__U328$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U328$lut$lut.bit.in.1"], - ["d_3_am__U329$lut$lut.bit.in.0","d_3_am__U328$lut$lut.bit.out"], - ["d_3_am__U329$lut$lut.bit.in.2","d_3_am__U329$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U329$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U329$lut$lut.bit.out"], + ["d_3_am__U252$lut$lut.bit.in.2","d_3_am__U252$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U252$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U252$lut$lut.bit.in.1"], + ["d_3_am__U253$lut$lut.bit.in.0","d_3_am__U252$lut$lut.bit.out"], + ["d_3_am__U253$lut$lut.bit.in.2","d_3_am__U253$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U253$lut$lut.bit.in.1"], + ["d_3_am__U254$lut$lut.bit.in.0","d_3_am__U253$lut$lut.bit.out"], + ["d_3_am__U254$lut$lut.bit.in.2","d_3_am__U254$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U254$lut$lut.bit.in.1"], + ["d_3_am__U255$lut$lut.bit.in.0","d_3_am__U254$lut$lut.bit.out"], + ["d_3_am__U255$lut$lut.bit.in.2","d_3_am__U255$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U255$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U255$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3412,16 +2985,16 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U330$lut$lut.bit.in.2","d_4_am__U330$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U330$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U330$lut$lut.bit.in.1"], - ["d_4_am__U331$lut$lut.bit.in.0","d_4_am__U330$lut$lut.bit.out"], - ["d_4_am__U331$lut$lut.bit.in.2","d_4_am__U331$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U331$lut$lut.bit.in.1"], - ["d_4_am__U332$lut$lut.bit.in.0","d_4_am__U331$lut$lut.bit.out"], - ["d_4_am__U332$lut$lut.bit.in.2","d_4_am__U332$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U332$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U332$lut$lut.bit.out"], + ["d_4_am__U256$lut$lut.bit.in.2","d_4_am__U256$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U256$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U256$lut$lut.bit.in.1"], + ["d_4_am__U257$lut$lut.bit.in.0","d_4_am__U256$lut$lut.bit.out"], + ["d_4_am__U257$lut$lut.bit.in.2","d_4_am__U257$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U257$lut$lut.bit.in.1"], + ["d_4_am__U258$lut$lut.bit.in.0","d_4_am__U257$lut$lut.bit.out"], + ["d_4_am__U258$lut$lut.bit.in.2","d_4_am__U258$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U258$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U258$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3438,13 +3011,13 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U333$lut$lut.bit.in.2","d_5_am__U333$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U333$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U333$lut$lut.bit.in.1"], - ["d_5_am__U334$lut$lut.bit.in.0","d_5_am__U333$lut$lut.bit.out"], - ["d_5_am__U334$lut$lut.bit.in.2","d_5_am__U334$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U334$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U334$lut$lut.bit.out"], + ["d_5_am__U259$lut$lut.bit.in.2","d_5_am__U259$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U259$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U259$lut$lut.bit.in.1"], + ["d_5_am__U260$lut$lut.bit.in.0","d_5_am__U259$lut$lut.bit.out"], + ["d_5_am__U260$lut$lut.bit.in.2","d_5_am__U260$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U260$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U260$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -3461,10 +3034,10 @@ ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U335$lut$lut.bit.in.2","d_6_am__U335$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U335$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U335$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U335$lut$lut.bit.out"], + ["d_6_am__U261$lut$lut.bit.in.2","d_6_am__U261$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U261$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U261$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U261$lut$lut.bit.out"], ["d_6_reg$reg0.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -3500,7 +3073,7 @@ ["self.d.7","d_7_reg$reg0.out"] ] }, - "affine_controller__U382":{ + "affine_controller__U299":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3508,594 +3081,1141 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U403":{ + "_U320":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4031":{ + "_U3201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4032":{ + "_U3202":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4033":{ + "_U3203":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4034":{ + "_U3204":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4035":{ + "_U3205":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U404":{ + "_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U397":{ + "affine_func$add_all__U314":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U315":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U398":{ + "affine_func$add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U399":{ + "affine_func$add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U400":{ + "affine_func$add_all__U318":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U401":{ - "genref":"coreir.add", + "affine_func$add_all__U319":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U301":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$coeff_1_U303":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00004000"]} + }, + "affine_func$coeff_2_U305":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00002000"]} + }, + "affine_func$coeff_3_U307":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_4_U309":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} + }, + "affine_func$coeff_5_U311":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U313":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00007000"]} + }, + "affine_func$mul_d0__U302":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U304":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U306":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U308":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d4__U310":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U312":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$count$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} + }, + "d_0_am__U322$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U322$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U323$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U323$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U324$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U324$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U325$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U325$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U326$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U326$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U402":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U384":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U386":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00004000"]} - }, - "affine_func$coeff_2_U388":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00002000"]} - }, - "affine_func$coeff_3_U390":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_4_U392":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "affine_func$coeff_5_U394":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "affine_func$const_term_U396":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00007000"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U385":{ - "genref":"coreir.mul", + "d_0_reg$clrMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U387":{ - "genref":"coreir.mul", + "d_0_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U389":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_0_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d3__U391":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_1_am__U327$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$mul_d4__U393":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_1_am__U327$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$mul_d5__U395":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_1_am__U328$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_1_am__U328$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_1_am__U329$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$c0_lutcnst":{ + "d_1_am__U329$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U330$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$lut$lut":{ + "d_1_am__U330$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$c0":{ + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$count$clrMux":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$enMux":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$max":{ - "genref":"coreir.const", + "d_1_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$reg0":{ + "genref":"coreir.reg", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$resetOr$c0_lutcnst":{ + "d_2_am__U331$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$resetOr$lut$lut":{ + "d_2_am__U331$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} - }, - "cycle_time$ult":{ - "genref":"coreir.ult", - "genargs":{"width":["Int",32]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U405$c0_lutcnst":{ + "d_2_am__U332$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U405$lut$lut":{ + "d_2_am__U332$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U406$c0_lutcnst":{ + "d_2_am__U333$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U406$lut$lut":{ + "d_2_am__U333$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U407$c0_lutcnst":{ + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_am__U334$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U407$lut$lut":{ + "d_3_am__U334$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U408$c0_lutcnst":{ + "d_3_am__U335$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U408$lut$lut":{ + "d_3_am__U335$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U409$c0_lutcnst":{ + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U336$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U409$lut$lut":{ + "d_4_am__U336$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_5_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_0_min":{ + "d_5_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_5_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_5_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_5_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_5_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U410$c0_lutcnst":{ + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U410$lut$lut":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U411$c0_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U411$lut$lut":{ + "true4_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U412$c0_lutcnst":{ + "true5_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U412$lut$lut":{ + "true6_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U413$c0_lutcnst":{ + "true7_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U413$lut$lut":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U320.out"], + ["d_1_inc.in1","_U3201.out"], + ["d_2_inc.in1","_U3202.out"], + ["d_3_inc.in1","_U3203.out"], + ["d_4_inc.in1","_U3204.out"], + ["d_5_inc.in1","_U3205.out"], + ["cmp_time.in1","_U321.out"], + ["affine_func$mul_d0__U302.out","affine_func$add_all__U314.in0"], + ["affine_func$mul_d1__U304.out","affine_func$add_all__U314.in1"], + ["affine_func$add_all__U315.in0","affine_func$add_all__U314.out"], + ["affine_func$mul_d2__U306.out","affine_func$add_all__U315.in1"], + ["affine_func$add_all__U316.in0","affine_func$add_all__U315.out"], + ["affine_func$mul_d3__U308.out","affine_func$add_all__U316.in1"], + ["affine_func$add_all__U317.in0","affine_func$add_all__U316.out"], + ["affine_func$mul_d4__U310.out","affine_func$add_all__U317.in1"], + ["affine_func$add_all__U318.in0","affine_func$add_all__U317.out"], + ["affine_func$mul_d5__U312.out","affine_func$add_all__U318.in1"], + ["affine_func$add_all__U319.in0","affine_func$add_all__U318.out"], + ["affine_func$const_term_U313.out","affine_func$add_all__U319.in1"], + ["time_diff.in0","affine_func$add_all__U319.out"], + ["affine_func$mul_d0__U302.in0","affine_func$coeff_0_U301.out"], + ["affine_func$mul_d1__U304.in0","affine_func$coeff_1_U303.out"], + ["affine_func$mul_d2__U306.in0","affine_func$coeff_2_U305.out"], + ["affine_func$mul_d3__U308.in0","affine_func$coeff_3_U307.out"], + ["affine_func$mul_d4__U310.in0","affine_func$coeff_4_U309.out"], + ["affine_func$mul_d5__U312.in0","affine_func$coeff_5_U311.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U302.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U304.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U306.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U308.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U310.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U312.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U322$lut$lut.bit.in.2","d_0_am__U322$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U322$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U322$lut$lut.bit.in.1"], + ["d_0_am__U323$lut$lut.bit.in.0","d_0_am__U322$lut$lut.bit.out"], + ["d_0_am__U323$lut$lut.bit.in.2","d_0_am__U323$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U323$lut$lut.bit.in.1"], + ["d_0_am__U324$lut$lut.bit.in.0","d_0_am__U323$lut$lut.bit.out"], + ["d_0_am__U324$lut$lut.bit.in.2","d_0_am__U324$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U324$lut$lut.bit.in.1"], + ["d_0_am__U325$lut$lut.bit.in.0","d_0_am__U324$lut$lut.bit.out"], + ["d_0_am__U325$lut$lut.bit.in.2","d_0_am__U325$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U325$lut$lut.bit.in.1"], + ["d_0_am__U326$lut$lut.bit.in.0","d_0_am__U325$lut$lut.bit.out"], + ["d_0_am__U326$lut$lut.bit.in.2","d_0_am__U326$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U326$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U326$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U327$lut$lut.bit.in.2","d_1_am__U327$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U327$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U327$lut$lut.bit.in.1"], + ["d_1_am__U328$lut$lut.bit.in.0","d_1_am__U327$lut$lut.bit.out"], + ["d_1_am__U328$lut$lut.bit.in.2","d_1_am__U328$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U328$lut$lut.bit.in.1"], + ["d_1_am__U329$lut$lut.bit.in.0","d_1_am__U328$lut$lut.bit.out"], + ["d_1_am__U329$lut$lut.bit.in.2","d_1_am__U329$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U329$lut$lut.bit.in.1"], + ["d_1_am__U330$lut$lut.bit.in.0","d_1_am__U329$lut$lut.bit.out"], + ["d_1_am__U330$lut$lut.bit.in.2","d_1_am__U330$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U330$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U330$lut$lut.bit.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U331$lut$lut.bit.in.2","d_2_am__U331$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U331$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U331$lut$lut.bit.in.1"], + ["d_2_am__U332$lut$lut.bit.in.0","d_2_am__U331$lut$lut.bit.out"], + ["d_2_am__U332$lut$lut.bit.in.2","d_2_am__U332$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U332$lut$lut.bit.in.1"], + ["d_2_am__U333$lut$lut.bit.in.0","d_2_am__U332$lut$lut.bit.out"], + ["d_2_am__U333$lut$lut.bit.in.2","d_2_am__U333$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U333$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U333$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U334$lut$lut.bit.in.2","d_3_am__U334$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U334$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U334$lut$lut.bit.in.1"], + ["d_3_am__U335$lut$lut.bit.in.0","d_3_am__U334$lut$lut.bit.out"], + ["d_3_am__U335$lut$lut.bit.in.2","d_3_am__U335$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U335$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U335$lut$lut.bit.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U336$lut$lut.bit.in.2","d_4_am__U336$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U336$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U336$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U336$lut$lut.bit.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["true_lutcnst.bit.out","d_5_next_value.sel"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"] + ] + }, + "affine_controller__U359":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",3,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_1_min":{ + "_U3711":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "_U3712":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_1_reg$c0":{ + "_U372":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ - "genref":"coreir.mux", + "affine_func$add_all__U368":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ - "genref":"coreir.mux", + "affine_func$add_all__U369":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U414$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U414$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U415$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U415$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U416$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U416$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", + "affine_func$add_all__U370":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "affine_func$coeff_0_U361":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$coeff_1_U363":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "d_2_max":{ + "affine_func$coeff_2_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_min":{ + "affine_func$const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000dfff"]} }, - "d_2_next_value":{ - "genref":"coreir.mux", + "affine_func$mul_d0__U362":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", + "affine_func$mul_d1__U364":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_2_reg$c0":{ + "affine_func$mul_d2__U366":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ + "cycle_time$count$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$enMux":{ + "cycle_time$count$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$reg0":{ + "cycle_time$count$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U417$c0_lutcnst":{ + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} + }, + "d_0_am__U373$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U417$lut$lut":{ + "d_0_am__U373$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U418$c0_lutcnst":{ + "d_0_am__U374$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U418$lut$lut":{ + "d_0_am__U374$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_3_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U419$c0_lutcnst":{ + "d_1_am__U375$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U419$lut$lut":{ + "d_1_am__U375$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_4_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_5_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -4124,21 +4244,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4146,45 +4251,27 @@ } }, "connections":[ - ["d_0_inc.in1","_U403.out"], - ["d_1_inc.in1","_U4031.out"], - ["d_2_inc.in1","_U4032.out"], - ["d_3_inc.in1","_U4033.out"], - ["d_4_inc.in1","_U4034.out"], - ["d_5_inc.in1","_U4035.out"], - ["cmp_time.in1","_U404.out"], - ["affine_func$mul_d0__U385.out","affine_func$add_all__U397.in0"], - ["affine_func$mul_d1__U387.out","affine_func$add_all__U397.in1"], - ["affine_func$add_all__U398.in0","affine_func$add_all__U397.out"], - ["affine_func$mul_d2__U389.out","affine_func$add_all__U398.in1"], - ["affine_func$add_all__U399.in0","affine_func$add_all__U398.out"], - ["affine_func$mul_d3__U391.out","affine_func$add_all__U399.in1"], - ["affine_func$add_all__U400.in0","affine_func$add_all__U399.out"], - ["affine_func$mul_d4__U393.out","affine_func$add_all__U400.in1"], - ["affine_func$add_all__U401.in0","affine_func$add_all__U400.out"], - ["affine_func$mul_d5__U395.out","affine_func$add_all__U401.in1"], - ["affine_func$add_all__U402.in0","affine_func$add_all__U401.out"], - ["affine_func$const_term_U396.out","affine_func$add_all__U402.in1"], - ["time_diff.in0","affine_func$add_all__U402.out"], - ["affine_func$mul_d0__U385.in0","affine_func$coeff_0_U384.out"], - ["affine_func$mul_d1__U387.in0","affine_func$coeff_1_U386.out"], - ["affine_func$mul_d2__U389.in0","affine_func$coeff_2_U388.out"], - ["affine_func$mul_d3__U391.in0","affine_func$coeff_3_U390.out"], - ["affine_func$mul_d4__U393.in0","affine_func$coeff_4_U392.out"], - ["affine_func$mul_d5__U395.in0","affine_func$coeff_5_U394.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U385.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U387.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U389.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U391.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U393.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U395.in1"], + ["d_0_inc.in1","_U371.out"], + ["d_1_inc.in1","_U3711.out"], + ["d_2_inc.in1","_U3712.out"], + ["cmp_time.in1","_U372.out"], + ["affine_func$mul_d0__U362.out","affine_func$add_all__U368.in0"], + ["affine_func$mul_d1__U364.out","affine_func$add_all__U368.in1"], + ["affine_func$add_all__U369.in0","affine_func$add_all__U368.out"], + ["affine_func$mul_d2__U366.out","affine_func$add_all__U369.in1"], + ["affine_func$add_all__U370.in0","affine_func$add_all__U369.out"], + ["affine_func$const_term_U367.out","affine_func$add_all__U370.in1"], + ["time_diff.in0","affine_func$add_all__U370.out"], + ["affine_func$mul_d0__U362.in0","affine_func$coeff_0_U361.out"], + ["affine_func$mul_d1__U364.in0","affine_func$coeff_1_U363.out"], + ["affine_func$mul_d2__U366.in0","affine_func$coeff_2_U365.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U362.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U364.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U366.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -4192,34 +4279,25 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true4_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U405$lut$lut.bit.in.2","d_0_am__U405$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U405$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U405$lut$lut.bit.in.1"], - ["d_0_am__U406$lut$lut.bit.in.0","d_0_am__U405$lut$lut.bit.out"], - ["d_0_am__U406$lut$lut.bit.in.2","d_0_am__U406$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U406$lut$lut.bit.in.1"], - ["d_0_am__U407$lut$lut.bit.in.0","d_0_am__U406$lut$lut.bit.out"], - ["d_0_am__U407$lut$lut.bit.in.2","d_0_am__U407$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U407$lut$lut.bit.in.1"], - ["d_0_am__U408$lut$lut.bit.in.0","d_0_am__U407$lut$lut.bit.out"], - ["d_0_am__U408$lut$lut.bit.in.2","d_0_am__U408$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U408$lut$lut.bit.in.1"], - ["d_0_am__U409$lut$lut.bit.in.0","d_0_am__U408$lut$lut.bit.out"], - ["d_0_am__U409$lut$lut.bit.in.2","d_0_am__U409$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U409$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U409$lut$lut.bit.out"], + ["d_0_am__U373$lut$lut.bit.in.2","d_0_am__U373$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U373$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U373$lut$lut.bit.in.1"], + ["d_0_am__U374$lut$lut.bit.in.0","d_0_am__U373$lut$lut.bit.out"], + ["d_0_am__U374$lut$lut.bit.in.2","d_0_am__U374$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U374$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U374$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4236,19 +4314,10 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U410$lut$lut.bit.in.2","d_1_am__U410$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U410$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U410$lut$lut.bit.in.1"], - ["d_1_am__U411$lut$lut.bit.in.0","d_1_am__U410$lut$lut.bit.out"], - ["d_1_am__U411$lut$lut.bit.in.2","d_1_am__U411$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U411$lut$lut.bit.in.1"], - ["d_1_am__U412$lut$lut.bit.in.0","d_1_am__U411$lut$lut.bit.out"], - ["d_1_am__U412$lut$lut.bit.in.2","d_1_am__U412$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U412$lut$lut.bit.in.1"], - ["d_1_am__U413$lut$lut.bit.in.0","d_1_am__U412$lut$lut.bit.out"], - ["d_1_am__U413$lut$lut.bit.in.2","d_1_am__U413$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U413$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U413$lut$lut.bit.out"], + ["d_1_am__U375$lut$lut.bit.in.2","d_1_am__U375$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U375$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U375$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U375$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4265,16 +4334,6 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U414$lut$lut.bit.in.2","d_2_am__U414$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U414$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U414$lut$lut.bit.in.1"], - ["d_2_am__U415$lut$lut.bit.in.0","d_2_am__U414$lut$lut.bit.out"], - ["d_2_am__U415$lut$lut.bit.in.2","d_2_am__U415$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U415$lut$lut.bit.in.1"], - ["d_2_am__U416$lut$lut.bit.in.0","d_2_am__U415$lut$lut.bit.out"], - ["d_2_am__U416$lut$lut.bit.in.2","d_2_am__U416$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U416$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U416$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4284,144 +4343,157 @@ ["d_2_reg$reg0.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["true_lutcnst.bit.out","d_2_next_value.sel"], ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], ["self.rst_n","d_2_reg$clrMux.sel"], ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U417$lut$lut.bit.in.2","d_3_am__U417$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U417$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U417$lut$lut.bit.in.1"], - ["d_3_am__U418$lut$lut.bit.in.0","d_3_am__U417$lut$lut.bit.out"], - ["d_3_am__U418$lut$lut.bit.in.2","d_3_am__U418$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U418$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U418$lut$lut.bit.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U419$lut$lut.bit.in.2","d_4_am__U419$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U419$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U419$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U419$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["true_lutcnst.bit.out","d_5_next_value.sel"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"] + ["self.d.2","d_2_reg$reg0.out"] ] }, - "affine_controller__U442":{ + "affine_controller__U38":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",3,["Array",32,"Bit"]]], + ["d",["Array",7,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U454":{ + "_U62":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4541":{ + "_U621":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4542":{ + "_U622":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U455":{ + "_U623":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U624":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U625":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U626":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U451":{ + "affine_func$add_all__U55":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U56":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U57":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U58":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U59":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U452":{ + "affine_func$add_all__U60":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U453":{ + "affine_func$add_all__U61":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U444":{ + "affine_func$coeff_0_U40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$coeff_1_U42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00004000"]} + }, + "affine_func$coeff_2_U44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00002000"]} + }, + "affine_func$coeff_3_U46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00001000"]} + }, + "affine_func$coeff_4_U48":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "affine_func$coeff_1_U446":{ + "affine_func$coeff_5_U50":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_2_U448":{ + "affine_func$coeff_6_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U450":{ + "affine_func$const_term_U54":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000dfff"]} + "modargs":{"value":[["BitVector",32],"32'h00003fff"]} + }, + "affine_func$mul_d0__U41":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U43":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U45":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U47":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U445":{ + "affine_func$mul_d4__U49":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U447":{ + "affine_func$mul_d5__U51":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U449":{ + "affine_func$mul_d6__U53":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4485,22 +4557,62 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U456$c0_lutcnst":{ + "d_0_am__U64$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U64$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U65$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U65$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U66$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U66$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U67$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U67$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U68$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U456$lut$lut":{ + "d_0_am__U68$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U457$c0_lutcnst":{ + "d_0_am__U69$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U457$lut$lut":{ + "d_0_am__U69$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4549,999 +4661,1033 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U458$c0_lutcnst":{ + "d_1_am__U70$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U458$lut$lut":{ + "d_1_am__U70$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "d_1_am__U71$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "d_1_am__U71$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} + "d_1_am__U72$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true1_lutcnst":{ + "d_1_am__U72$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true2_lutcnst":{ + "d_1_am__U73$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true3_lutcnst":{ + "d_1_am__U73$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true4_lutcnst":{ + "d_1_am__U74$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true_lutcnst":{ + "d_1_am__U74$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U454.out"], - ["d_1_inc.in1","_U4541.out"], - ["d_2_inc.in1","_U4542.out"], - ["cmp_time.in1","_U455.out"], - ["affine_func$mul_d0__U445.out","affine_func$add_all__U451.in0"], - ["affine_func$mul_d1__U447.out","affine_func$add_all__U451.in1"], - ["affine_func$add_all__U452.in0","affine_func$add_all__U451.out"], - ["affine_func$mul_d2__U449.out","affine_func$add_all__U452.in1"], - ["affine_func$add_all__U453.in0","affine_func$add_all__U452.out"], - ["affine_func$const_term_U450.out","affine_func$add_all__U453.in1"], - ["time_diff.in0","affine_func$add_all__U453.out"], - ["affine_func$mul_d0__U445.in0","affine_func$coeff_0_U444.out"], - ["affine_func$mul_d1__U447.in0","affine_func$coeff_1_U446.out"], - ["affine_func$mul_d2__U449.in0","affine_func$coeff_2_U448.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U445.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U447.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U449.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true4_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U456$lut$lut.bit.in.2","d_0_am__U456$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U456$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U456$lut$lut.bit.in.1"], - ["d_0_am__U457$lut$lut.bit.in.0","d_0_am__U456$lut$lut.bit.out"], - ["d_0_am__U457$lut$lut.bit.in.2","d_0_am__U457$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U457$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U457$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U458$lut$lut.bit.in.2","d_1_am__U458$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U458$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U458$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U458$lut$lut.bit.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["true_lutcnst.bit.out","d_2_next_value.sel"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"] - ] - }, - "affine_controller__U47":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",7,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U71":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "_U711":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, - "_U712":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "_U713":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U714":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "_U715":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "_U716":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "_U72":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U64":{ - "genref":"coreir.add", + "d_1_reg$clrMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U65":{ - "genref":"coreir.add", + "d_1_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U66":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_1_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U67":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_2_am__U75$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$add_all__U68":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_2_am__U75$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$add_all__U69":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_2_am__U76$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$add_all__U70":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_2_am__U76$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$coeff_0_U49":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "d_2_am__U77$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$coeff_1_U51":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00004000"]} + "d_2_am__U77$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$coeff_2_U53":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00002000"]} + "d_2_am__U78$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$coeff_3_U55":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001000"]} + "d_2_am__U78$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$coeff_4_U57":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, - "affine_func$coeff_5_U59":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "affine_func$coeff_6_U61":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U63":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003fff"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U50":{ - "genref":"coreir.mul", + "d_2_next_value":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U52":{ - "genref":"coreir.mul", + "d_2_next_value_at_max":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U54":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d3__U56":{ - "genref":"coreir.mul", + "d_2_reg$clrMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U58":{ - "genref":"coreir.mul", + "d_2_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U60":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d6__U62":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_3_am__U79$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_3_am__U79$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_3_am__U80$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$c0_lutcnst":{ + "d_3_am__U80$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U81$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$lut$lut":{ + "d_3_am__U81$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$c0":{ + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$count$clrMux":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$enMux":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cycle_time$ult":{ - "genref":"coreir.ult", + "d_3_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_am__U73$c0_lutcnst":{ + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U82$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U73$lut$lut":{ + "d_4_am__U82$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U74$c0_lutcnst":{ + "d_4_am__U83$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U74$lut$lut":{ + "d_4_am__U83$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U75$c0_lutcnst":{ + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_5_am__U84$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U75$lut$lut":{ + "d_5_am__U84$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U76$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_0_am__U76$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_0_am__U77$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_am__U77$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_0_am__U78$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_5_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_0_am__U78$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_5_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_0_at_max":{ + "d_6_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_6_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_6_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_0_min":{ + "d_6_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_6_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_6_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_6_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_6_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_6_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_6_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U79$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} }, - "d_1_am__U79$lut$lut":{ + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U80$c0_lutcnst":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U80$lut$lut":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U81$c0_lutcnst":{ + "true4_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U81$lut$lut":{ + "true5_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U82$c0_lutcnst":{ + "true6_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U82$lut$lut":{ + "true7_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U83$c0_lutcnst":{ + "true8_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_1_am__U83$lut$lut":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U62.out"], + ["d_1_inc.in1","_U621.out"], + ["d_2_inc.in1","_U622.out"], + ["d_3_inc.in1","_U623.out"], + ["d_4_inc.in1","_U624.out"], + ["d_5_inc.in1","_U625.out"], + ["d_6_inc.in1","_U626.out"], + ["cmp_time.in1","_U63.out"], + ["affine_func$mul_d0__U41.out","affine_func$add_all__U55.in0"], + ["affine_func$mul_d1__U43.out","affine_func$add_all__U55.in1"], + ["affine_func$add_all__U56.in0","affine_func$add_all__U55.out"], + ["affine_func$mul_d2__U45.out","affine_func$add_all__U56.in1"], + ["affine_func$add_all__U57.in0","affine_func$add_all__U56.out"], + ["affine_func$mul_d3__U47.out","affine_func$add_all__U57.in1"], + ["affine_func$add_all__U58.in0","affine_func$add_all__U57.out"], + ["affine_func$mul_d4__U49.out","affine_func$add_all__U58.in1"], + ["affine_func$add_all__U59.in0","affine_func$add_all__U58.out"], + ["affine_func$mul_d5__U51.out","affine_func$add_all__U59.in1"], + ["affine_func$add_all__U60.in0","affine_func$add_all__U59.out"], + ["affine_func$mul_d6__U53.out","affine_func$add_all__U60.in1"], + ["affine_func$add_all__U61.in0","affine_func$add_all__U60.out"], + ["affine_func$const_term_U54.out","affine_func$add_all__U61.in1"], + ["time_diff.in0","affine_func$add_all__U61.out"], + ["affine_func$mul_d0__U41.in0","affine_func$coeff_0_U40.out"], + ["affine_func$mul_d1__U43.in0","affine_func$coeff_1_U42.out"], + ["affine_func$mul_d2__U45.in0","affine_func$coeff_2_U44.out"], + ["affine_func$mul_d3__U47.in0","affine_func$coeff_3_U46.out"], + ["affine_func$mul_d4__U49.in0","affine_func$coeff_4_U48.out"], + ["affine_func$mul_d5__U51.in0","affine_func$coeff_5_U50.out"], + ["affine_func$mul_d6__U53.in0","affine_func$coeff_6_U52.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U41.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U43.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U45.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U47.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U49.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U51.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U53.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true8_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true7_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U64$lut$lut.bit.in.2","d_0_am__U64$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U64$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U64$lut$lut.bit.in.1"], + ["d_0_am__U65$lut$lut.bit.in.0","d_0_am__U64$lut$lut.bit.out"], + ["d_0_am__U65$lut$lut.bit.in.2","d_0_am__U65$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U65$lut$lut.bit.in.1"], + ["d_0_am__U66$lut$lut.bit.in.0","d_0_am__U65$lut$lut.bit.out"], + ["d_0_am__U66$lut$lut.bit.in.2","d_0_am__U66$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U66$lut$lut.bit.in.1"], + ["d_0_am__U67$lut$lut.bit.in.0","d_0_am__U66$lut$lut.bit.out"], + ["d_0_am__U67$lut$lut.bit.in.2","d_0_am__U67$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U67$lut$lut.bit.in.1"], + ["d_0_am__U68$lut$lut.bit.in.0","d_0_am__U67$lut$lut.bit.out"], + ["d_0_am__U68$lut$lut.bit.in.2","d_0_am__U68$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U68$lut$lut.bit.in.1"], + ["d_0_am__U69$lut$lut.bit.in.0","d_0_am__U68$lut$lut.bit.out"], + ["d_0_am__U69$lut$lut.bit.in.2","d_0_am__U69$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U69$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U69$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U70$lut$lut.bit.in.2","d_1_am__U70$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U70$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U70$lut$lut.bit.in.1"], + ["d_1_am__U71$lut$lut.bit.in.0","d_1_am__U70$lut$lut.bit.out"], + ["d_1_am__U71$lut$lut.bit.in.2","d_1_am__U71$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U71$lut$lut.bit.in.1"], + ["d_1_am__U72$lut$lut.bit.in.0","d_1_am__U71$lut$lut.bit.out"], + ["d_1_am__U72$lut$lut.bit.in.2","d_1_am__U72$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U72$lut$lut.bit.in.1"], + ["d_1_am__U73$lut$lut.bit.in.0","d_1_am__U72$lut$lut.bit.out"], + ["d_1_am__U73$lut$lut.bit.in.2","d_1_am__U73$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U73$lut$lut.bit.in.1"], + ["d_1_am__U74$lut$lut.bit.in.0","d_1_am__U73$lut$lut.bit.out"], + ["d_1_am__U74$lut$lut.bit.in.2","d_1_am__U74$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U74$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U74$lut$lut.bit.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U75$lut$lut.bit.in.2","d_2_am__U75$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U75$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U75$lut$lut.bit.in.1"], + ["d_2_am__U76$lut$lut.bit.in.0","d_2_am__U75$lut$lut.bit.out"], + ["d_2_am__U76$lut$lut.bit.in.2","d_2_am__U76$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U76$lut$lut.bit.in.1"], + ["d_2_am__U77$lut$lut.bit.in.0","d_2_am__U76$lut$lut.bit.out"], + ["d_2_am__U77$lut$lut.bit.in.2","d_2_am__U77$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U77$lut$lut.bit.in.1"], + ["d_2_am__U78$lut$lut.bit.in.0","d_2_am__U77$lut$lut.bit.out"], + ["d_2_am__U78$lut$lut.bit.in.2","d_2_am__U78$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U78$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U78$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U79$lut$lut.bit.in.2","d_3_am__U79$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U79$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U79$lut$lut.bit.in.1"], + ["d_3_am__U80$lut$lut.bit.in.0","d_3_am__U79$lut$lut.bit.out"], + ["d_3_am__U80$lut$lut.bit.in.2","d_3_am__U80$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U80$lut$lut.bit.in.1"], + ["d_3_am__U81$lut$lut.bit.in.0","d_3_am__U80$lut$lut.bit.out"], + ["d_3_am__U81$lut$lut.bit.in.2","d_3_am__U81$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U81$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U81$lut$lut.bit.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U82$lut$lut.bit.in.2","d_4_am__U82$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U82$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U82$lut$lut.bit.in.1"], + ["d_4_am__U83$lut$lut.bit.in.0","d_4_am__U82$lut$lut.bit.out"], + ["d_4_am__U83$lut$lut.bit.in.2","d_4_am__U83$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U83$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U83$lut$lut.bit.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U84$lut$lut.bit.in.2","d_5_am__U84$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U84$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U84$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U84$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["true_lutcnst.bit.out","d_6_next_value.sel"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"] + ] + }, + "affine_controller__U8":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",3,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U20":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_1_min":{ + "_U201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "_U202":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_1_reg$c0":{ + "_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$enMux":{ - "genref":"coreir.mux", + "affine_func$add_all__U17":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U84$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U84$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U85$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U85$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U86$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U86$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U87$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U87$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", + "affine_func$add_all__U18":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_inc":{ + "affine_func$add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_max":{ + "affine_func$coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_min":{ + "affine_func$coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func$coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_reg$c0":{ + "affine_func$const_term_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", + "affine_func$mul_d0__U11":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", + "affine_func$mul_d1__U13":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U88$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U88$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "affine_func$mul_d2__U15":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U89$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, - "d_3_am__U89$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "d_3_am__U90$c0_lutcnst":{ + "cycle_time$and$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U90$lut$lut":{ + "cycle_time$and$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_3_min":{ + "cycle_time$count$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "cycle_time$count$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "cycle_time$count$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$c0":{ + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} }, - "d_4_am__U91$c0_lutcnst":{ + "d_0_am__U22$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U91$lut$lut":{ + "d_0_am__U22$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U92$c0_lutcnst":{ + "d_0_am__U23$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U92$lut$lut":{ + "d_0_am__U23$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U93$c0_lutcnst":{ + "d_1_am__U24$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U93$lut$lut":{ + "d_1_am__U24$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_5_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_5_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_6_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_6_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_6_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true2_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true3_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} }, - "true5_lutcnst":{ + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true7_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true8_lutcnst":{ + "true4_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} @@ -5553,51 +5699,27 @@ } }, "connections":[ - ["d_0_inc.in1","_U71.out"], - ["d_1_inc.in1","_U711.out"], - ["d_2_inc.in1","_U712.out"], - ["d_3_inc.in1","_U713.out"], - ["d_4_inc.in1","_U714.out"], - ["d_5_inc.in1","_U715.out"], - ["d_6_inc.in1","_U716.out"], - ["cmp_time.in1","_U72.out"], - ["affine_func$mul_d0__U50.out","affine_func$add_all__U64.in0"], - ["affine_func$mul_d1__U52.out","affine_func$add_all__U64.in1"], - ["affine_func$add_all__U65.in0","affine_func$add_all__U64.out"], - ["affine_func$mul_d2__U54.out","affine_func$add_all__U65.in1"], - ["affine_func$add_all__U66.in0","affine_func$add_all__U65.out"], - ["affine_func$mul_d3__U56.out","affine_func$add_all__U66.in1"], - ["affine_func$add_all__U67.in0","affine_func$add_all__U66.out"], - ["affine_func$mul_d4__U58.out","affine_func$add_all__U67.in1"], - ["affine_func$add_all__U68.in0","affine_func$add_all__U67.out"], - ["affine_func$mul_d5__U60.out","affine_func$add_all__U68.in1"], - ["affine_func$add_all__U69.in0","affine_func$add_all__U68.out"], - ["affine_func$mul_d6__U62.out","affine_func$add_all__U69.in1"], - ["affine_func$add_all__U70.in0","affine_func$add_all__U69.out"], - ["affine_func$const_term_U63.out","affine_func$add_all__U70.in1"], - ["time_diff.in0","affine_func$add_all__U70.out"], - ["affine_func$mul_d0__U50.in0","affine_func$coeff_0_U49.out"], - ["affine_func$mul_d1__U52.in0","affine_func$coeff_1_U51.out"], - ["affine_func$mul_d2__U54.in0","affine_func$coeff_2_U53.out"], - ["affine_func$mul_d3__U56.in0","affine_func$coeff_3_U55.out"], - ["affine_func$mul_d4__U58.in0","affine_func$coeff_4_U57.out"], - ["affine_func$mul_d5__U60.in0","affine_func$coeff_5_U59.out"], - ["affine_func$mul_d6__U62.in0","affine_func$coeff_6_U61.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U50.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U52.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U54.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U56.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U58.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U60.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U62.in1"], + ["d_0_inc.in1","_U20.out"], + ["d_1_inc.in1","_U201.out"], + ["d_2_inc.in1","_U202.out"], + ["cmp_time.in1","_U21.out"], + ["affine_func$mul_d0__U11.out","affine_func$add_all__U17.in0"], + ["affine_func$mul_d1__U13.out","affine_func$add_all__U17.in1"], + ["affine_func$add_all__U18.in0","affine_func$add_all__U17.out"], + ["affine_func$mul_d2__U15.out","affine_func$add_all__U18.in1"], + ["affine_func$add_all__U19.in0","affine_func$add_all__U18.out"], + ["affine_func$const_term_U16.out","affine_func$add_all__U19.in1"], + ["time_diff.in0","affine_func$add_all__U19.out"], + ["affine_func$mul_d0__U11.in0","affine_func$coeff_0_U10.out"], + ["affine_func$mul_d1__U13.in0","affine_func$coeff_1_U12.out"], + ["affine_func$mul_d2__U15.in0","affine_func$coeff_2_U14.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U11.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U13.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U15.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -5605,37 +5727,25 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true8_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true4_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true7_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U73$lut$lut.bit.in.2","d_0_am__U73$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U73$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U73$lut$lut.bit.in.1"], - ["d_0_am__U74$lut$lut.bit.in.0","d_0_am__U73$lut$lut.bit.out"], - ["d_0_am__U74$lut$lut.bit.in.2","d_0_am__U74$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U74$lut$lut.bit.in.1"], - ["d_0_am__U75$lut$lut.bit.in.0","d_0_am__U74$lut$lut.bit.out"], - ["d_0_am__U75$lut$lut.bit.in.2","d_0_am__U75$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U75$lut$lut.bit.in.1"], - ["d_0_am__U76$lut$lut.bit.in.0","d_0_am__U75$lut$lut.bit.out"], - ["d_0_am__U76$lut$lut.bit.in.2","d_0_am__U76$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U76$lut$lut.bit.in.1"], - ["d_0_am__U77$lut$lut.bit.in.0","d_0_am__U76$lut$lut.bit.out"], - ["d_0_am__U77$lut$lut.bit.in.2","d_0_am__U77$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U77$lut$lut.bit.in.1"], - ["d_0_am__U78$lut$lut.bit.in.0","d_0_am__U77$lut$lut.bit.out"], - ["d_0_am__U78$lut$lut.bit.in.2","d_0_am__U78$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U78$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U78$lut$lut.bit.out"], + ["d_0_am__U22$lut$lut.bit.in.2","d_0_am__U22$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U22$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U22$lut$lut.bit.in.1"], + ["d_0_am__U23$lut$lut.bit.in.0","d_0_am__U22$lut$lut.bit.out"], + ["d_0_am__U23$lut$lut.bit.in.2","d_0_am__U23$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U23$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U23$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5652,22 +5762,10 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U79$lut$lut.bit.in.2","d_1_am__U79$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U79$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U79$lut$lut.bit.in.1"], - ["d_1_am__U80$lut$lut.bit.in.0","d_1_am__U79$lut$lut.bit.out"], - ["d_1_am__U80$lut$lut.bit.in.2","d_1_am__U80$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U80$lut$lut.bit.in.1"], - ["d_1_am__U81$lut$lut.bit.in.0","d_1_am__U80$lut$lut.bit.out"], - ["d_1_am__U81$lut$lut.bit.in.2","d_1_am__U81$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U81$lut$lut.bit.in.1"], - ["d_1_am__U82$lut$lut.bit.in.0","d_1_am__U81$lut$lut.bit.out"], - ["d_1_am__U82$lut$lut.bit.in.2","d_1_am__U82$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U82$lut$lut.bit.in.1"], - ["d_1_am__U83$lut$lut.bit.in.0","d_1_am__U82$lut$lut.bit.out"], - ["d_1_am__U83$lut$lut.bit.in.2","d_1_am__U83$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U83$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U83$lut$lut.bit.out"], + ["d_1_am__U24$lut$lut.bit.in.2","d_1_am__U24$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U24$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U24$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U24$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5684,19 +5782,6 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U84$lut$lut.bit.in.2","d_2_am__U84$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U84$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U84$lut$lut.bit.in.1"], - ["d_2_am__U85$lut$lut.bit.in.0","d_2_am__U84$lut$lut.bit.out"], - ["d_2_am__U85$lut$lut.bit.in.2","d_2_am__U85$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U85$lut$lut.bit.in.1"], - ["d_2_am__U86$lut$lut.bit.in.0","d_2_am__U85$lut$lut.bit.out"], - ["d_2_am__U86$lut$lut.bit.in.2","d_2_am__U86$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U86$lut$lut.bit.in.1"], - ["d_2_am__U87$lut$lut.bit.in.0","d_2_am__U86$lut$lut.bit.out"], - ["d_2_am__U87$lut$lut.bit.in.2","d_2_am__U87$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U87$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U87$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5706,99 +5791,14 @@ ["d_2_reg$reg0.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["true_lutcnst.bit.out","d_2_next_value.sel"], ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], ["self.rst_n","d_2_reg$clrMux.sel"], ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U88$lut$lut.bit.in.2","d_3_am__U88$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U88$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U88$lut$lut.bit.in.1"], - ["d_3_am__U89$lut$lut.bit.in.0","d_3_am__U88$lut$lut.bit.out"], - ["d_3_am__U89$lut$lut.bit.in.2","d_3_am__U89$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U89$lut$lut.bit.in.1"], - ["d_3_am__U90$lut$lut.bit.in.0","d_3_am__U89$lut$lut.bit.out"], - ["d_3_am__U90$lut$lut.bit.in.2","d_3_am__U90$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U90$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U90$lut$lut.bit.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U91$lut$lut.bit.in.2","d_4_am__U91$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U91$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U91$lut$lut.bit.in.1"], - ["d_4_am__U92$lut$lut.bit.in.0","d_4_am__U91$lut$lut.bit.out"], - ["d_4_am__U92$lut$lut.bit.in.2","d_4_am__U92$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U92$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U92$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U93$lut$lut.bit.in.2","d_5_am__U93$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U93$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U93$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U93$lut$lut.bit.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["true_lutcnst.bit.out","d_6_next_value.sel"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"] + ["self.d.2","d_2_reg$reg0.out"] ] }, "cu_op_hcompute_hw_output_stencil":{ @@ -5874,26 +5874,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U489":{ + "PE_init_U406":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U487":{ + "_U404":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U488":{ + "_U405":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U487.out","PE_init_U489.data.in.0"], - ["_U488.out","PE_init_U489.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U489.data.out"], + ["_U404.out","PE_init_U406.data.in.0"], + ["_U405.out","PE_init_U406.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U406.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -5905,26 +5905,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U492":{ + "PE_init_U409":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U490":{ + "_U407":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U491":{ + "_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U490.out","PE_init_U492.data.in.0"], - ["_U491.out","PE_init_U492.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U492.data.out"], + ["_U407.out","PE_init_U409.data.in.0"], + ["_U408.out","PE_init_U409.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U409.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6710,26 +6710,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U495":{ + "PE_init_U412":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U493":{ + "_U410":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U494":{ + "_U411":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U493.out","PE_init_U495.data.in.0"], - ["_U494.out","PE_init_U495.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U495.data.out"], + ["_U410.out","PE_init_U412.data.in.0"], + ["_U411.out","PE_init_U412.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U412.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6741,26 +6741,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U498":{ + "PE_init_U415":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U496":{ + "_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U497":{ + "_U414":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U496.out","PE_init_U498.data.in.0"], - ["_U497.out","PE_init_U498.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U498.data.out"], + ["_U413.out","PE_init_U415.data.in.0"], + ["_U414.out","PE_init_U415.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U415.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6772,26 +6772,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U501":{ + "PE_init_U418":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U499":{ + "_U416":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U500":{ + "_U417":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U499.out","PE_init_U501.data.in.0"], - ["_U500.out","PE_init_U501.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U501.data.out"], + ["_U416.out","PE_init_U418.data.in.0"], + ["_U417.out","PE_init_U418.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U418.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6803,26 +6803,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U504":{ + "PE_init_U421":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U502":{ + "_U419":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U503":{ + "_U420":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U502.out","PE_init_U504.data.in.0"], - ["_U503.out","PE_init_U504.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U504.data.out"], + ["_U419.out","PE_init_U421.data.in.0"], + ["_U420.out","PE_init_U421.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U421.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6834,26 +6834,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U507":{ + "PE_init_U424":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U505":{ + "_U422":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U506":{ + "_U423":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U505.out","PE_init_U507.data.in.0"], - ["_U506.out","PE_init_U507.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U507.data.out"], + ["_U422.out","PE_init_U424.data.in.0"], + ["_U423.out","PE_init_U424.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U424.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6865,26 +6865,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U510":{ + "PE_init_U427":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U508":{ + "_U425":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U509":{ + "_U426":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U508.out","PE_init_U510.data.in.0"], - ["_U509.out","PE_init_U510.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U510.data.out"], + ["_U425.out","PE_init_U427.data.in.0"], + ["_U426.out","PE_init_U427.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U427.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7209,26 +7209,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U513":{ + "PE_init_U430":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U511":{ + "_U428":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U512":{ + "_U429":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U511.out","PE_init_U513.data.in.0"], - ["_U512.out","PE_init_U513.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U513.data.out"] + ["_U428.out","PE_init_U430.data.in.0"], + ["_U429.out","PE_init_U430.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U430.data.out"] ] }, "hcompute_output_cgra_stencil_1":{ @@ -7236,26 +7236,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U516":{ + "PE_init_U433":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U514":{ + "_U431":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U515":{ + "_U432":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U514.out","PE_init_U516.data.in.0"], - ["_U515.out","PE_init_U516.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U516.data.out"] + ["_U431.out","PE_init_U433.data.in.0"], + ["_U432.out","PE_init_U433.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U433.data.out"] ] }, "hcompute_output_cgra_stencil_10":{ @@ -8013,26 +8013,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U519":{ + "PE_init_U436":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U517":{ + "_U434":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U518":{ + "_U435":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U517.out","PE_init_U519.data.in.0"], - ["_U518.out","PE_init_U519.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U519.data.out"] + ["_U434.out","PE_init_U436.data.in.0"], + ["_U435.out","PE_init_U436.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U436.data.out"] ] }, "hcompute_output_cgra_stencil_3":{ @@ -8040,26 +8040,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U522":{ + "PE_init_U439":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U520":{ + "_U437":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U521":{ + "_U438":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U520.out","PE_init_U522.data.in.0"], - ["_U521.out","PE_init_U522.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U522.data.out"] + ["_U437.out","PE_init_U439.data.in.0"], + ["_U438.out","PE_init_U439.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U439.data.out"] ] }, "hcompute_output_cgra_stencil_4":{ @@ -8067,26 +8067,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U525":{ + "PE_init_U442":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U523":{ + "_U440":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U524":{ + "_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U523.out","PE_init_U525.data.in.0"], - ["_U524.out","PE_init_U525.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U525.data.out"] + ["_U440.out","PE_init_U442.data.in.0"], + ["_U441.out","PE_init_U442.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U442.data.out"] ] }, "hcompute_output_cgra_stencil_5":{ @@ -8094,26 +8094,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U528":{ + "PE_init_U445":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U526":{ + "_U443":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U527":{ + "_U444":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U526.out","PE_init_U528.data.in.0"], - ["_U527.out","PE_init_U528.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U528.data.out"] + ["_U443.out","PE_init_U445.data.in.0"], + ["_U444.out","PE_init_U445.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U445.data.out"] ] }, "hcompute_output_cgra_stencil_6":{ @@ -8121,26 +8121,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U531":{ + "PE_init_U448":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U529":{ + "_U446":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U530":{ + "_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U529.out","PE_init_U531.data.in.0"], - ["_U530.out","PE_init_U531.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U531.data.out"] + ["_U446.out","PE_init_U448.data.in.0"], + ["_U447.out","PE_init_U448.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U448.data.out"] ] }, "hcompute_output_cgra_stencil_7":{ @@ -8148,26 +8148,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U534":{ + "PE_init_U451":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U532":{ + "_U449":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U533":{ + "_U450":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U532.out","PE_init_U534.data.in.0"], - ["_U533.out","PE_init_U534.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U534.data.out"] + ["_U449.out","PE_init_U451.data.in.0"], + ["_U450.out","PE_init_U451.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U451.data.out"] ] }, "hcompute_output_cgra_stencil_8":{ @@ -8454,38 +8454,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -8493,7 +8461,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -8503,7 +8471,7 @@ }, "ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -8513,7 +8481,7 @@ }, "ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -8523,7 +8491,7 @@ }, "ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -8533,7 +8501,7 @@ }, "ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -8543,7 +8511,7 @@ }, "ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -8553,7 +8521,7 @@ }, "ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -8563,7 +8531,7 @@ }, "ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -8705,262 +8673,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U121":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U123":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U125":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U127":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U129":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U131":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U133":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U135":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U137":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U139":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U141":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -8968,7 +8680,7 @@ }, "ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -8978,7 +8690,7 @@ }, "ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[154],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[129],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -8988,7 +8700,7 @@ }, "ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[193],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -8998,7 +8710,7 @@ }, "ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[282],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[257],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -9008,7 +8720,7 @@ }, "ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[346],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[321],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -9018,7 +8730,7 @@ }, "ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[410],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[385],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -9028,7 +8740,7 @@ }, "ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[474],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[449],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -9038,7 +8750,7 @@ }, "ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -9048,7 +8760,7 @@ }, "ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[66],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -9058,7 +8770,7 @@ }, "ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[155],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -9068,7 +8780,7 @@ }, "ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[194],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -9078,7 +8790,7 @@ }, "ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[64],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -9088,7 +8800,7 @@ }, "ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[283],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[258],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -9098,7 +8810,7 @@ }, "ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[347],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[322],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -9108,7 +8820,7 @@ }, "ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[411],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[386],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -9118,7 +8830,7 @@ }, "ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[475],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[450],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -9128,7 +8840,7 @@ }, "ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -9138,7 +8850,7 @@ }, "ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[67],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -9148,7 +8860,7 @@ }, "ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[156],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[131],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -9158,7 +8870,7 @@ }, "ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[195],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -9168,7 +8880,7 @@ }, "ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[284],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[259],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -9178,7 +8890,7 @@ }, "ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[348],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[323],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -9188,7 +8900,7 @@ }, "ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[153],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[128],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -9198,7 +8910,7 @@ }, "ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[412],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[387],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -9208,7 +8920,7 @@ }, "ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[476],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[451],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -9218,7 +8930,7 @@ }, "ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -9228,7 +8940,7 @@ }, "ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[68],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -9238,7 +8950,7 @@ }, "ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[157],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[132],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -9248,7 +8960,7 @@ }, "ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[196],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -9258,7 +8970,7 @@ }, "ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[285],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -9268,7 +8980,7 @@ }, "ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[349],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[324],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -9278,7 +8990,7 @@ }, "ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[413],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[388],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -9288,7 +9000,7 @@ }, "ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[477],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[452],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -9298,7 +9010,7 @@ }, "ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[192],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -9308,7 +9020,7 @@ }, "ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -9318,7 +9030,7 @@ }, "ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[69],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -9328,7 +9040,7 @@ }, "ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[158],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[133],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -9338,7 +9050,7 @@ }, "ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[197],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -9348,7 +9060,7 @@ }, "ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[286],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[261],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -9358,7 +9070,7 @@ }, "ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[350],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[325],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -9368,7 +9080,7 @@ }, "ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[414],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[389],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -9378,7 +9090,7 @@ }, "ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[478],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[453],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -9388,7 +9100,7 @@ }, "ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -9398,7 +9110,7 @@ }, "ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[70],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -9408,7 +9120,7 @@ }, "ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[281],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[256],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -9418,7 +9130,7 @@ }, "ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[159],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[134],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -9428,7 +9140,7 @@ }, "ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[198],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -9438,7 +9150,7 @@ }, "ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[287],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[262],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -9448,7 +9160,7 @@ }, "ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[351],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[326],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -9458,7 +9170,7 @@ }, "ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[415],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[390],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -9468,7 +9180,7 @@ }, "ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[479],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[454],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -9478,7 +9190,7 @@ }, "ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -9488,7 +9200,7 @@ }, "ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[71],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -9498,7 +9210,7 @@ }, "ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[160],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[135],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -9508,7 +9220,7 @@ }, "ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[199],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -9518,7 +9230,7 @@ }, "ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[345],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[320],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -9528,7 +9240,7 @@ }, "ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[288],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[263],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -9538,7 +9250,7 @@ }, "ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[352],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[327],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -9548,7 +9260,7 @@ }, "ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[416],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[391],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -9558,7 +9270,7 @@ }, "ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[480],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[455],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -9568,7 +9280,7 @@ }, "ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[409],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[384],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -9578,7 +9290,7 @@ }, "ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[473],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[448],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -9588,7 +9300,7 @@ }, "ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -9598,7 +9310,7 @@ }, "ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[65],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -9951,158 +9663,126 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U537":{ + "PE_init_U454":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U540":{ + "PE_init_U457":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U543":{ + "PE_init_U460":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U546":{ + "PE_init_U463":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U549":{ + "PE_init_U466":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U552":{ + "PE_init_U469":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U555":{ + "PE_init_U472":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U558":{ + "PE_init_U475":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U535":{ + "_U452":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U536":{ + "_U453":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U538":{ + "_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U539":{ + "_U456":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U541":{ + "_U458":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U542":{ + "_U459":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U544":{ + "_U461":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U545":{ + "_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U547":{ + "_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U548":{ + "_U465":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U550":{ + "_U467":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U551":{ + "_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U553":{ + "_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U554":{ + "_U471":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U556":{ + "_U473":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U557":{ + "_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "input_cgra_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10110,7 +9790,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -10120,7 +9800,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -10130,7 +9810,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -10140,7 +9820,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -10150,7 +9830,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -10160,7 +9840,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -10170,7 +9850,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -10180,7 +9860,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,64,4096],"dimensionality":3,"extent":[8,64,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[32,64,4096],"dimensionality":3,"extent":[2,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -10209,262 +9889,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "kernel_cgra_stencil$chain_en_const_U121":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U123":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U125":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U127":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U129":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U131":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U133":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U135":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U137":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U139":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U141":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10472,7 +9896,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -10482,7 +9906,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[154],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[129],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -10492,7 +9916,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[193],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -10502,7 +9926,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[282],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[257],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -10512,7 +9936,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[346],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[321],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -10522,7 +9946,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[410],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[385],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -10532,7 +9956,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[474],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[449],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -10542,7 +9966,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -10552,7 +9976,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[66],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -10562,7 +9986,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[155],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -10572,7 +9996,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[194],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -10582,7 +10006,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[64],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -10592,7 +10016,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[283],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[258],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -10602,7 +10026,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[347],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[322],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -10612,7 +10036,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[411],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[386],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -10622,7 +10046,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[475],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[450],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -10632,7 +10056,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -10642,7 +10066,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[67],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -10652,7 +10076,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[156],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[131],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -10662,7 +10086,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[195],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -10672,7 +10096,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[284],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[259],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -10682,7 +10106,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[348],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[323],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -10692,7 +10116,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[153],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[128],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -10702,7 +10126,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[412],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[387],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -10712,7 +10136,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[476],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[451],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -10722,7 +10146,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -10732,7 +10156,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[68],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -10742,7 +10166,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[157],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[132],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -10752,7 +10176,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[196],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -10762,7 +10186,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[285],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -10772,7 +10196,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[349],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[324],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -10782,7 +10206,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[413],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[388],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -10792,7 +10216,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[477],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[452],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -10802,7 +10226,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[192],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -10812,7 +10236,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -10822,7 +10246,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[69],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -10832,7 +10256,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[158],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[133],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -10842,7 +10266,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[197],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -10852,7 +10276,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[286],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[261],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -10862,7 +10286,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[350],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[325],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -10872,7 +10296,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[414],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[389],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -10882,7 +10306,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[478],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[453],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -10892,7 +10316,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -10902,7 +10326,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[70],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -10912,7 +10336,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[281],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[256],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -10922,7 +10346,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[159],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[134],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -10932,7 +10356,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[198],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -10942,7 +10366,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[287],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[262],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -10952,7 +10376,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[351],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[326],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -10962,7 +10386,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[415],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[390],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -10972,7 +10396,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[479],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[454],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -10982,7 +10406,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -10992,7 +10416,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[71],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -11002,7 +10426,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[160],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[135],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -11012,7 +10436,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[199],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -11022,7 +10446,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[345],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[320],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -11032,7 +10456,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[288],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[263],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -11042,7 +10466,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[352],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[327],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -11052,7 +10476,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[416],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[391],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -11062,7 +10486,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[480],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[455],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -11072,7 +10496,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[409],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[384],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -11082,7 +10506,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[473],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[448],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -11092,7 +10516,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -11102,7 +10526,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[32,512,4096],"dimensionality":3,"extent":[2,8,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16]},"in2agg_0":{"cycle_starting_addr":[65],"cycle_stride":[8,512,4096],"dimensionality":3,"extent":[8,8,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4093],"cycle_stride":[4,8,64,4096],"dimensionality":4,"extent":[2,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096],"dimensionality":4,"extent":[8,8,64,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -11112,7 +10536,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U473"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U390"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[12288],"cycle_stride":[1,64,8192,16384],"dimensionality":4,"extent":[64,64,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,128,64,8192]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_output_cgra_stencil_10$inner_compute$add_957_971_972$binop":{ @@ -11755,38 +11179,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "output_cgra_stencil$chain_en_const_U366":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U368":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U370":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U372":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U374":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U376":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U378":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U380":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -11794,7 +11186,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U365"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U291"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12285],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12288],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -11804,7 +11196,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U367"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U292"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"agg2sram_1":{"cycle_starting_addr":[4101],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"in2agg_1":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12287],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12289],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -11814,7 +11206,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U369"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U293"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12287],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12290],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -11824,7 +11216,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U371"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12289],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12291],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -11834,7 +11226,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U373"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U295"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12289],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12292],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -11844,7 +11236,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U375"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U296"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12291],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12293],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -11854,7 +11246,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U377"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U297"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12291],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12294],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -11864,35 +11256,35 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U379"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U298"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12293],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12295],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U535.out","PE_init_U537.data.in.0"], - ["_U536.out","PE_init_U537.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U537.data.out"], - ["_U538.out","PE_init_U540.data.in.0"], - ["_U539.out","PE_init_U540.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U540.data.out"], - ["_U541.out","PE_init_U543.data.in.0"], - ["_U542.out","PE_init_U543.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U543.data.out"], - ["_U544.out","PE_init_U546.data.in.0"], - ["_U545.out","PE_init_U546.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U546.data.out"], - ["_U547.out","PE_init_U549.data.in.0"], - ["_U548.out","PE_init_U549.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U549.data.out"], - ["_U550.out","PE_init_U552.data.in.0"], - ["_U551.out","PE_init_U552.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U552.data.out"], - ["_U553.out","PE_init_U555.data.in.0"], - ["_U554.out","PE_init_U555.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U555.data.out"], - ["_U556.out","PE_init_U558.data.in.0"], - ["_U557.out","PE_init_U558.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U558.data.out"], + ["_U452.out","PE_init_U454.data.in.0"], + ["_U453.out","PE_init_U454.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U454.data.out"], + ["_U455.out","PE_init_U457.data.in.0"], + ["_U456.out","PE_init_U457.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U457.data.out"], + ["_U458.out","PE_init_U460.data.in.0"], + ["_U459.out","PE_init_U460.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U460.data.out"], + ["_U461.out","PE_init_U463.data.in.0"], + ["_U462.out","PE_init_U463.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U463.data.out"], + ["_U464.out","PE_init_U466.data.in.0"], + ["_U465.out","PE_init_U466.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U466.data.out"], + ["_U467.out","PE_init_U469.data.in.0"], + ["_U468.out","PE_init_U469.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U469.data.out"], + ["_U470.out","PE_init_U472.data.in.0"], + ["_U471.out","PE_init_U472.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U472.data.out"], + ["_U473.out","PE_init_U475.data.in.0"], + ["_U474.out","PE_init_U475.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U475.data.out"], ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_input_host_stencil_op_hcompute_input_glb_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_output_cgra_stencil_10$inner_compute$mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957$binop.data.in.1","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], @@ -12402,7 +11794,7 @@ ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.clk_en","output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U475":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U392":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12411,7 +11803,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U474":{ + "op_hcompute_hw_output_stencil_read_start_pt__U391":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12420,7 +11812,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U476":{ + "op_hcompute_hw_output_stencil_write_start_pt__U393":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12429,7 +11821,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U484":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U401":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12438,7 +11830,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U483":{ + "op_hcompute_input_glb_stencil_read_start_pt__U400":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12447,7 +11839,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U485":{ + "op_hcompute_input_glb_stencil_write_start_pt__U402":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12456,7 +11848,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U479":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U396":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12465,7 +11857,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U478":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U395":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12474,7 +11866,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U480":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U397":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -12540,38 +11932,6 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U366":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U368":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U370":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U372":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U374":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U376":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U378":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U380":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -12579,7 +11939,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U365"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U291"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12285],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12288],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -12589,7 +11949,7 @@ }, "ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U367"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U292"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"agg2sram_1":{"cycle_starting_addr":[4101],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"in2agg_1":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12287],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12289],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -12599,7 +11959,7 @@ }, "ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U369"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U293"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12287],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12290],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -12609,7 +11969,7 @@ }, "ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U371"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12289],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12291],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -12619,7 +11979,7 @@ }, "ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U373"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U295"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12289],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12292],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -12629,7 +11989,7 @@ }, "ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U375"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U296"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12291],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12293],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -12639,7 +11999,7 @@ }, "ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U377"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U297"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12291],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12294],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -12649,7 +12009,7 @@ }, "ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U379"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U298"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4100],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,128]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,128]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,8192],"dimensionality":3,"extent":[8,64,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[4094],"cycle_stride":[4,8,64,4096,8192],"dimensionality":5,"extent":[2,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,128],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0]},"sram2tb_1":{"cycle_starting_addr":[12293],"cycle_stride":[32,64,8192],"dimensionality":3,"extent":[2,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,128],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[4096],"cycle_stride":[1,8,64,4096,8192],"dimensionality":5,"extent":[8,8,64,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0]},"tb2out_1":{"cycle_starting_addr":[12295],"cycle_stride":[8,64,8192],"dimensionality":3,"extent":[8,64,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, diff --git a/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled.json b/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled.json index 8f2708c31..5b412ad14 100644 --- a/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled.json +++ b/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled.json @@ -231,7 +231,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -240,7 +240,7 @@ } }, "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], + ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], ["self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_write.0","inner_compute.out_hw_filter_dw_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -250,7 +250,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -259,7 +259,7 @@ } }, "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], + ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], ["self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write.0","inner_compute.out_hw_filter_dw_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -269,7 +269,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -278,7 +278,7 @@ } }, "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], + ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], ["self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write.0","inner_compute.out_hw_filter_dw_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -288,7 +288,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -297,7 +297,7 @@ } }, "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], + ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read.0","inner_compute.in0_hw_filter_dw_stencil.0"], ["self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write.0","inner_compute.out_hw_filter_dw_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -326,7 +326,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -335,7 +335,7 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -345,7 +345,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -354,7 +354,7 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -364,7 +364,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -373,7 +373,7 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -383,7 +383,7 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -392,7 +392,7 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] @@ -1785,154 +1785,10 @@ ["op_hcompute_hw_filter_dw_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U101":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U103":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U43":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U45":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U47":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U53":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U55":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U57":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U61":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U63":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U65":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U67":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U69":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U71":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U73":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U75":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U77":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U79":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U81":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U83":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U85":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U87":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U91":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U93":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U95":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U97":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U99":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U32"} + "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1940,13 +1796,13 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U34"} + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U52"} + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -1954,8 +1810,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U54"} + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -1963,8 +1819,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U56"} + "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -1972,8 +1828,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U58"} + "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -1981,8 +1837,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U60"} + "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -1990,8 +1846,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U62"} + "genargs":{"ID":["String","_U47"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -1999,8 +1855,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U64"} + "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -2008,8 +1864,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U66"} + "genargs":{"ID":["String","_U49"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -2017,8 +1873,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U68"} + "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -2026,8 +1882,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U70"} + "genargs":{"ID":["String","_U51"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -2039,13 +1895,13 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U36"} + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U72"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U72"} + "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -2053,8 +1909,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U74"} + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -2062,8 +1918,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U76"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U76"} + "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -2071,8 +1927,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U78"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U78"} + "genargs":{"ID":["String","_U55"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -2080,8 +1936,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U80"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U80"} + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -2089,8 +1945,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U82"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U82"} + "genargs":{"ID":["String","_U57"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -2098,8 +1954,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U84"} + "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -2107,8 +1963,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U86"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U86"} + "genargs":{"ID":["String","_U59"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -2116,8 +1972,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U88"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U88"} + "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -2125,8 +1981,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U90"} + "genargs":{"ID":["String","_U61"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -2138,13 +1994,13 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U38"} + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U92"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U92"} + "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -2152,8 +2008,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U94"} + "genargs":{"ID":["String","_U63"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -2161,8 +2017,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U96"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U96"} + "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -2170,8 +2026,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U98"} + "genargs":{"ID":["String","_U65"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -2179,8 +2035,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U100"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U100"} + "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -2188,8 +2044,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U102"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U102"} + "genargs":{"ID":["String","_U67"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -2201,8 +2057,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U40"} + "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -2210,8 +2066,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U42"} + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -2219,8 +2075,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U44"} + "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -2228,8 +2084,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U46"} + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -2237,8 +2093,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U48"} + "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -2246,8 +2102,8 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U50"} + "genargs":{"ID":["String","_U41"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -2255,42 +2111,6 @@ } }, "connections":[ - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_34.chain_chain_en","chain_en_const_U101.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_35.chain_chain_en","chain_en_const_U103.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U33.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_1.chain_chain_en","chain_en_const_U35.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_2.chain_chain_en","chain_en_const_U37.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_3.chain_chain_en","chain_en_const_U39.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_4.chain_chain_en","chain_en_const_U41.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_5.chain_chain_en","chain_en_const_U43.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_6.chain_chain_en","chain_en_const_U45.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_7.chain_chain_en","chain_en_const_U47.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_8.chain_chain_en","chain_en_const_U49.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_9.chain_chain_en","chain_en_const_U51.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_10.chain_chain_en","chain_en_const_U53.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_11.chain_chain_en","chain_en_const_U55.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_12.chain_chain_en","chain_en_const_U57.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_13.chain_chain_en","chain_en_const_U59.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_14.chain_chain_en","chain_en_const_U61.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_15.chain_chain_en","chain_en_const_U63.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_16.chain_chain_en","chain_en_const_U65.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_17.chain_chain_en","chain_en_const_U67.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_18.chain_chain_en","chain_en_const_U69.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_19.chain_chain_en","chain_en_const_U71.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_20.chain_chain_en","chain_en_const_U73.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_21.chain_chain_en","chain_en_const_U75.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_22.chain_chain_en","chain_en_const_U77.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_23.chain_chain_en","chain_en_const_U79.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_24.chain_chain_en","chain_en_const_U81.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_25.chain_chain_en","chain_en_const_U83.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_26.chain_chain_en","chain_en_const_U85.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_27.chain_chain_en","chain_en_const_U87.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_28.chain_chain_en","chain_en_const_U89.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_29.chain_chain_en","chain_en_const_U91.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_30.chain_chain_en","chain_en_const_U93.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_31.chain_chain_en","chain_en_const_U95.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_32.chain_chain_en","chain_en_const_U97.out"], - ["ub_hw_filter_dw_global_wrapper_stencil_BANK_33.chain_chain_en","chain_en_const_U99.out"], ["ub_hw_filter_dw_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_filter_dw_global_wrapper_stencil_BANK_1.clk","self.clk"], ["ub_hw_filter_dw_global_wrapper_stencil_BANK_10.clk","self.clk"], @@ -2524,58 +2344,10 @@ ["op_hcompute_pw_conv_reduction_stencil_5_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U105":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U107":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U109":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U111":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U113":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U115":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U117":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U121":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U123":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U125":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U127":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U104"} + "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -2583,13 +2355,13 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U106"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U106"} + "genargs":{"ID":["String","_U69"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U124"} + "genargs":{"ID":["String","_U78"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -2597,8 +2369,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[18],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U126"} + "genargs":{"ID":["String","_U79"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[18],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -2610,8 +2382,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U108"} + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -2619,8 +2391,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[16],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U110"} + "genargs":{"ID":["String","_U71"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[16],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -2628,8 +2400,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U112"} + "genargs":{"ID":["String","_U72"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -2637,8 +2409,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U114"} + "genargs":{"ID":["String","_U73"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -2646,8 +2418,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U116"} + "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -2655,8 +2427,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[17],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U118"} + "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[17],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -2664,8 +2436,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U120"} + "genargs":{"ID":["String","_U76"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -2673,8 +2445,8 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake","verilog_name":"lake__U122"} + "genargs":{"ID":["String","_U77"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}},"mode":"lake"} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -2682,18 +2454,6 @@ } }, "connections":[ - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U105.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_1.chain_chain_en","chain_en_const_U107.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_2.chain_chain_en","chain_en_const_U109.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_3.chain_chain_en","chain_en_const_U111.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_4.chain_chain_en","chain_en_const_U113.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_5.chain_chain_en","chain_en_const_U115.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_6.chain_chain_en","chain_en_const_U117.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_7.chain_chain_en","chain_en_const_U119.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_8.chain_chain_en","chain_en_const_U121.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_9.chain_chain_en","chain_en_const_U123.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_10.chain_chain_en","chain_en_const_U125.out"], - ["ub_hw_filter_pw_global_wrapper_stencil_BANK_11.chain_chain_en","chain_en_const_U127.out"], ["ub_hw_filter_pw_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_filter_pw_global_wrapper_stencil_BANK_1.clk","self.clk"], ["ub_hw_filter_pw_global_wrapper_stencil_BANK_10.clk","self.clk"], @@ -2791,318 +2551,290 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U129":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U131":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U133":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U135":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U137":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U139":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U141":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U142":{ + "d_reg__U100":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U143":{ + "d_reg__U101":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U144":{ + "d_reg__U102":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U145":{ + "d_reg__U103":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U146":{ + "d_reg__U104":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U147":{ + "d_reg__U105":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U148":{ + "d_reg__U106":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U149":{ + "d_reg__U107":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U150":{ + "d_reg__U108":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U151":{ + "d_reg__U109":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U152":{ + "d_reg__U110":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U153":{ + "d_reg__U111":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U154":{ + "d_reg__U112":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U155":{ + "d_reg__U113":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U156":{ + "d_reg__U114":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U157":{ + "d_reg__U115":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U158":{ + "d_reg__U116":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U159":{ + "d_reg__U117":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U160":{ + "d_reg__U118":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U161":{ + "d_reg__U119":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U162":{ + "d_reg__U120":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U163":{ + "d_reg__U121":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U164":{ + "d_reg__U122":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U165":{ + "d_reg__U123":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U166":{ + "d_reg__U124":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U167":{ + "d_reg__U125":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U168":{ + "d_reg__U126":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U169":{ + "d_reg__U127":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U170":{ + "d_reg__U128":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U171":{ + "d_reg__U129":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U172":{ + "d_reg__U130":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U173":{ + "d_reg__U131":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U174":{ + "d_reg__U132":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U175":{ + "d_reg__U133":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U176":{ + "d_reg__U134":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U177":{ + "d_reg__U135":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U178":{ + "d_reg__U136":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U179":{ + "d_reg__U137":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U180":{ + "d_reg__U138":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U181":{ + "d_reg__U139":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U182":{ + "d_reg__U140":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U183":{ + "d_reg__U141":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U184":{ + "d_reg__U142":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U185":{ + "d_reg__U87":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U186":{ + "d_reg__U88":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U187":{ + "d_reg__U89":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U188":{ + "d_reg__U90":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U189":{ + "d_reg__U91":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U190":{ + "d_reg__U92":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U191":{ + "d_reg__U93":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U192":{ + "d_reg__U94":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U193":{ + "d_reg__U95":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U194":{ + "d_reg__U96":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U195":{ + "d_reg__U97":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U196":{ + "d_reg__U98":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U197":{ + "d_reg__U99":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U128"} + "genargs":{"ID":["String","_U80"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -3110,8 +2842,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U130"} + "genargs":{"ID":["String","_U81"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -3119,8 +2851,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U132"} + "genargs":{"ID":["String","_U82"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -3128,8 +2860,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U134"} + "genargs":{"ID":["String","_U83"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -3137,8 +2869,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U136"} + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -3146,8 +2878,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U138"} + "genargs":{"ID":["String","_U85"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -3155,8 +2887,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[69],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U140"} + "genargs":{"ID":["String","_U86"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[69],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -3164,153 +2896,146 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U129.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_1.chain_chain_en","chain_en_const_U131.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_2.chain_chain_en","chain_en_const_U133.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_3.chain_chain_en","chain_en_const_U135.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_4.chain_chain_en","chain_en_const_U137.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_5.chain_chain_en","chain_en_const_U139.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_6.chain_chain_en","chain_en_const_U141.out"], + ["self.clk","d_reg__U100.clk"], + ["d_reg__U99.out","d_reg__U100.in"], + ["d_reg__U101.in","d_reg__U100.out"], + ["self.clk","d_reg__U101.clk"], + ["d_reg__U102.in","d_reg__U101.out"], + ["self.clk","d_reg__U102.clk"], + ["d_reg__U119.in","d_reg__U102.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.7","d_reg__U102.out"], + ["self.clk","d_reg__U103.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0","d_reg__U103.in"], + ["d_reg__U104.in","d_reg__U103.out"], + ["self.clk","d_reg__U104.clk"], + ["d_reg__U105.in","d_reg__U104.out"], + ["self.clk","d_reg__U105.clk"], + ["d_reg__U106.in","d_reg__U105.out"], + ["self.clk","d_reg__U106.clk"], + ["d_reg__U107.in","d_reg__U106.out"], + ["self.clk","d_reg__U107.clk"], + ["d_reg__U108.in","d_reg__U107.out"], + ["self.clk","d_reg__U108.clk"], + ["d_reg__U109.in","d_reg__U108.out"], + ["self.clk","d_reg__U109.clk"], + ["d_reg__U110.in","d_reg__U109.out"], + ["self.clk","d_reg__U110.clk"], + ["d_reg__U125.in","d_reg__U110.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.7","d_reg__U110.out"], + ["self.clk","d_reg__U111.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_3_write.0","d_reg__U111.in"], + ["d_reg__U112.in","d_reg__U111.out"], + ["self.clk","d_reg__U112.clk"], + ["d_reg__U113.in","d_reg__U112.out"], + ["self.clk","d_reg__U113.clk"], + ["d_reg__U114.in","d_reg__U113.out"], + ["self.clk","d_reg__U114.clk"], + ["d_reg__U115.in","d_reg__U114.out"], + ["self.clk","d_reg__U115.clk"], + ["d_reg__U116.in","d_reg__U115.out"], + ["self.clk","d_reg__U116.clk"], + ["d_reg__U117.in","d_reg__U116.out"], + ["self.clk","d_reg__U117.clk"], + ["d_reg__U118.in","d_reg__U117.out"], + ["self.clk","d_reg__U118.clk"], + ["d_reg__U131.in","d_reg__U118.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.7","d_reg__U118.out"], + ["self.clk","d_reg__U119.clk"], + ["d_reg__U120.in","d_reg__U119.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.8","d_reg__U119.out"], + ["self.clk","d_reg__U120.clk"], + ["self.op_hcompute_dw_conv_stencil_5_read.6","d_reg__U120.out"], + ["self.clk","d_reg__U121.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_6.data_out_1","d_reg__U121.in"], + ["d_reg__U122.in","d_reg__U121.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.4","d_reg__U121.out"], + ["self.clk","d_reg__U122.clk"], + ["self.op_hcompute_dw_conv_stencil_5_read.3","d_reg__U122.out"], + ["self.clk","d_reg__U123.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_6.data_out_0","d_reg__U123.in"], + ["d_reg__U124.in","d_reg__U123.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.1","d_reg__U123.out"], + ["self.clk","d_reg__U124.clk"], + ["self.op_hcompute_dw_conv_stencil_5_read.0","d_reg__U124.out"], + ["self.clk","d_reg__U125.clk"], + ["d_reg__U126.in","d_reg__U125.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.8","d_reg__U125.out"], + ["self.clk","d_reg__U126.clk"], + ["self.op_hcompute_dw_conv_stencil_6_read.6","d_reg__U126.out"], + ["self.clk","d_reg__U127.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U127.in"], + ["d_reg__U128.in","d_reg__U127.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.4","d_reg__U127.out"], + ["self.clk","d_reg__U128.clk"], + ["self.op_hcompute_dw_conv_stencil_6_read.3","d_reg__U128.out"], + ["self.clk","d_reg__U129.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.data_out_0","d_reg__U129.in"], + ["d_reg__U130.in","d_reg__U129.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.1","d_reg__U129.out"], + ["self.clk","d_reg__U130.clk"], + ["self.op_hcompute_dw_conv_stencil_6_read.0","d_reg__U130.out"], + ["self.clk","d_reg__U131.clk"], + ["d_reg__U132.in","d_reg__U131.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.8","d_reg__U131.out"], + ["self.clk","d_reg__U132.clk"], + ["self.op_hcompute_dw_conv_stencil_7_read.6","d_reg__U132.out"], + ["self.clk","d_reg__U133.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.data_out_0","d_reg__U133.in"], + ["d_reg__U134.in","d_reg__U133.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.4","d_reg__U133.out"], + ["self.clk","d_reg__U134.clk"], + ["self.op_hcompute_dw_conv_stencil_7_read.3","d_reg__U134.out"], + ["self.clk","d_reg__U135.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.data_out_0","d_reg__U135.in"], + ["d_reg__U136.in","d_reg__U135.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.1","d_reg__U135.out"], + ["self.clk","d_reg__U136.clk"], + ["self.op_hcompute_dw_conv_stencil_7_read.0","d_reg__U136.out"], + ["self.clk","d_reg__U137.clk"], + ["d_reg__U94.out","d_reg__U137.in"], + ["d_reg__U138.in","d_reg__U137.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.8","d_reg__U137.out"], + ["self.clk","d_reg__U138.clk"], + ["self.op_hcompute_dw_conv_stencil_4_read.6","d_reg__U138.out"], + ["self.clk","d_reg__U139.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.data_out_0","d_reg__U139.in"], + ["d_reg__U140.in","d_reg__U139.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.4","d_reg__U139.out"], + ["self.clk","d_reg__U140.clk"], + ["self.op_hcompute_dw_conv_stencil_4_read.3","d_reg__U140.out"], + ["self.clk","d_reg__U141.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.data_out_0","d_reg__U141.in"], + ["d_reg__U142.in","d_reg__U141.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.1","d_reg__U141.out"], ["self.clk","d_reg__U142.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U142.in"], - ["d_reg__U143.in","d_reg__U142.out"], - ["self.clk","d_reg__U143.clk"], - ["d_reg__U144.in","d_reg__U143.out"], - ["self.clk","d_reg__U144.clk"], - ["d_reg__U145.in","d_reg__U144.out"], - ["self.clk","d_reg__U145.clk"], - ["d_reg__U146.in","d_reg__U145.out"], - ["self.clk","d_reg__U146.clk"], - ["d_reg__U147.in","d_reg__U146.out"], - ["self.clk","d_reg__U147.clk"], - ["d_reg__U148.in","d_reg__U147.out"], - ["self.clk","d_reg__U148.clk"], - ["d_reg__U149.in","d_reg__U148.out"], - ["self.clk","d_reg__U149.clk"], - ["d_reg__U192.in","d_reg__U149.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.7","d_reg__U149.out"], - ["self.clk","d_reg__U150.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0","d_reg__U150.in"], - ["d_reg__U151.in","d_reg__U150.out"], - ["self.clk","d_reg__U151.clk"], - ["d_reg__U152.in","d_reg__U151.out"], - ["self.clk","d_reg__U152.clk"], - ["d_reg__U153.in","d_reg__U152.out"], - ["self.clk","d_reg__U153.clk"], - ["d_reg__U154.in","d_reg__U153.out"], - ["self.clk","d_reg__U154.clk"], - ["d_reg__U155.in","d_reg__U154.out"], - ["self.clk","d_reg__U155.clk"], - ["d_reg__U156.in","d_reg__U155.out"], - ["self.clk","d_reg__U156.clk"], - ["d_reg__U157.in","d_reg__U156.out"], - ["self.clk","d_reg__U157.clk"], - ["d_reg__U174.in","d_reg__U157.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.7","d_reg__U157.out"], - ["self.clk","d_reg__U158.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0","d_reg__U158.in"], - ["d_reg__U159.in","d_reg__U158.out"], - ["self.clk","d_reg__U159.clk"], - ["d_reg__U160.in","d_reg__U159.out"], - ["self.clk","d_reg__U160.clk"], - ["d_reg__U161.in","d_reg__U160.out"], - ["self.clk","d_reg__U161.clk"], - ["d_reg__U162.in","d_reg__U161.out"], - ["self.clk","d_reg__U162.clk"], - ["d_reg__U163.in","d_reg__U162.out"], - ["self.clk","d_reg__U163.clk"], - ["d_reg__U164.in","d_reg__U163.out"], - ["self.clk","d_reg__U164.clk"], - ["d_reg__U165.in","d_reg__U164.out"], - ["self.clk","d_reg__U165.clk"], - ["d_reg__U180.in","d_reg__U165.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.7","d_reg__U165.out"], - ["self.clk","d_reg__U166.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_3_write.0","d_reg__U166.in"], - ["d_reg__U167.in","d_reg__U166.out"], - ["self.clk","d_reg__U167.clk"], - ["d_reg__U168.in","d_reg__U167.out"], - ["self.clk","d_reg__U168.clk"], - ["d_reg__U169.in","d_reg__U168.out"], - ["self.clk","d_reg__U169.clk"], - ["d_reg__U170.in","d_reg__U169.out"], - ["self.clk","d_reg__U170.clk"], - ["d_reg__U171.in","d_reg__U170.out"], - ["self.clk","d_reg__U171.clk"], - ["d_reg__U172.in","d_reg__U171.out"], - ["self.clk","d_reg__U172.clk"], - ["d_reg__U173.in","d_reg__U172.out"], - ["self.clk","d_reg__U173.clk"], - ["d_reg__U186.in","d_reg__U173.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.7","d_reg__U173.out"], - ["self.clk","d_reg__U174.clk"], - ["d_reg__U175.in","d_reg__U174.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.8","d_reg__U174.out"], - ["self.clk","d_reg__U175.clk"], - ["self.op_hcompute_dw_conv_stencil_5_read.6","d_reg__U175.out"], - ["self.clk","d_reg__U176.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_6.data_out_1","d_reg__U176.in"], - ["d_reg__U177.in","d_reg__U176.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.4","d_reg__U176.out"], - ["self.clk","d_reg__U177.clk"], - ["self.op_hcompute_dw_conv_stencil_5_read.3","d_reg__U177.out"], - ["self.clk","d_reg__U178.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_6.data_out_0","d_reg__U178.in"], - ["d_reg__U179.in","d_reg__U178.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.1","d_reg__U178.out"], - ["self.clk","d_reg__U179.clk"], - ["self.op_hcompute_dw_conv_stencil_5_read.0","d_reg__U179.out"], - ["self.clk","d_reg__U180.clk"], - ["d_reg__U181.in","d_reg__U180.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.8","d_reg__U180.out"], - ["self.clk","d_reg__U181.clk"], - ["self.op_hcompute_dw_conv_stencil_6_read.6","d_reg__U181.out"], - ["self.clk","d_reg__U182.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","d_reg__U182.in"], - ["d_reg__U183.in","d_reg__U182.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.4","d_reg__U182.out"], - ["self.clk","d_reg__U183.clk"], - ["self.op_hcompute_dw_conv_stencil_6_read.3","d_reg__U183.out"], - ["self.clk","d_reg__U184.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_1.data_out_0","d_reg__U184.in"], - ["d_reg__U185.in","d_reg__U184.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.1","d_reg__U184.out"], - ["self.clk","d_reg__U185.clk"], - ["self.op_hcompute_dw_conv_stencil_6_read.0","d_reg__U185.out"], - ["self.clk","d_reg__U186.clk"], - ["d_reg__U187.in","d_reg__U186.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.8","d_reg__U186.out"], - ["self.clk","d_reg__U187.clk"], - ["self.op_hcompute_dw_conv_stencil_7_read.6","d_reg__U187.out"], - ["self.clk","d_reg__U188.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_2.data_out_0","d_reg__U188.in"], - ["d_reg__U189.in","d_reg__U188.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.4","d_reg__U188.out"], - ["self.clk","d_reg__U189.clk"], - ["self.op_hcompute_dw_conv_stencil_7_read.3","d_reg__U189.out"], - ["self.clk","d_reg__U190.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_3.data_out_0","d_reg__U190.in"], - ["d_reg__U191.in","d_reg__U190.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.1","d_reg__U190.out"], - ["self.clk","d_reg__U191.clk"], - ["self.op_hcompute_dw_conv_stencil_7_read.0","d_reg__U191.out"], - ["self.clk","d_reg__U192.clk"], - ["d_reg__U193.in","d_reg__U192.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.8","d_reg__U192.out"], - ["self.clk","d_reg__U193.clk"], - ["self.op_hcompute_dw_conv_stencil_4_read.6","d_reg__U193.out"], - ["self.clk","d_reg__U194.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_4.data_out_0","d_reg__U194.in"], - ["d_reg__U195.in","d_reg__U194.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.4","d_reg__U194.out"], - ["self.clk","d_reg__U195.clk"], - ["self.op_hcompute_dw_conv_stencil_4_read.3","d_reg__U195.out"], - ["self.clk","d_reg__U196.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_5.data_out_0","d_reg__U196.in"], - ["d_reg__U197.in","d_reg__U196.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.1","d_reg__U196.out"], - ["self.clk","d_reg__U197.clk"], - ["self.op_hcompute_dw_conv_stencil_4_read.0","d_reg__U197.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.0","d_reg__U142.out"], + ["self.clk","d_reg__U87.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U87.in"], + ["d_reg__U88.in","d_reg__U87.out"], + ["self.clk","d_reg__U88.clk"], + ["d_reg__U89.in","d_reg__U88.out"], + ["self.clk","d_reg__U89.clk"], + ["d_reg__U90.in","d_reg__U89.out"], + ["self.clk","d_reg__U90.clk"], + ["d_reg__U91.in","d_reg__U90.out"], + ["self.clk","d_reg__U91.clk"], + ["d_reg__U92.in","d_reg__U91.out"], + ["self.clk","d_reg__U92.clk"], + ["d_reg__U93.in","d_reg__U92.out"], + ["self.clk","d_reg__U93.clk"], + ["d_reg__U94.in","d_reg__U93.out"], + ["self.clk","d_reg__U94.clk"], + ["self.op_hcompute_dw_conv_stencil_4_read.7","d_reg__U94.out"], + ["self.clk","d_reg__U95.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0","d_reg__U95.in"], + ["d_reg__U96.in","d_reg__U95.out"], + ["self.clk","d_reg__U96.clk"], + ["d_reg__U97.in","d_reg__U96.out"], + ["self.clk","d_reg__U97.clk"], + ["d_reg__U98.in","d_reg__U97.out"], + ["self.clk","d_reg__U98.clk"], + ["d_reg__U99.in","d_reg__U98.out"], + ["self.clk","d_reg__U99.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_1.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_2.clk","self.clk"], @@ -3360,24 +3085,24 @@ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["reset","BitIn"], - ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read_en","Bit"], ["hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","Bit"], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], - ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","Bit"], + ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_output_stencil_clkwrk_10_op_hcompute_hw_output_stencil_2_write_valid","Bit"], ["hw_output_stencil_clkwrk_10_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]], ["hw_output_stencil_clkwrk_8_op_hcompute_hw_output_stencil_write_valid","Bit"], @@ -3386,47 +3111,47 @@ ["hw_output_stencil_clkwrk_9_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U238":{ + "_U183":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U243":{ + "_U188":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U248":{ + "_U193":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U253":{ + "_U198":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U258":{ + "_U203":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U263":{ + "_U208":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U268":{ + "_U213":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U273":{ + "_U218":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U278":{ + "_U223":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -3477,103 +3202,103 @@ "modref":"global.cu_op_hcompute_hw_filter_dw_global_wrapper_stencil_1" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start_pt__U271" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start_pt__U216" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U269"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U269"} + "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake"} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start_pt__U270" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start_pt__U215" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start_pt__U272" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start_pt__U217" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_2":{ "modref":"global.cu_op_hcompute_hw_filter_dw_global_wrapper_stencil_2" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start_pt__U266" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start_pt__U211" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U264"} + "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake"} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start_pt__U265" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start_pt__U210" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start_pt__U267" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start_pt__U212" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_3":{ "modref":"global.cu_op_hcompute_hw_filter_dw_global_wrapper_stencil_3" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start_pt__U261" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start_pt__U206" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U259"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U259"} + "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake"} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start_pt__U260" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start_pt__U205" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start_pt__U262" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start_pt__U207" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start_pt__U276" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start_pt__U221" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U274"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U274"} + "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3]}},"mode":"lake"} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start_pt__U275" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start_pt__U220" }, "op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start_pt__U277" + "modref":"global.op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start_pt__U222" }, "op_hcompute_hw_filter_pw_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_filter_pw_global_wrapper_stencil" }, "op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start_pt__U236" + "modref":"global.op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start_pt__U181" }, "op_hcompute_hw_filter_pw_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,4]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U234"} + "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,4]}},"mode":"lake"} }, "op_hcompute_hw_filter_pw_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start_pt__U235" + "modref":"global.op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start_pt__U180" }, "op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start_pt__U237" + "modref":"global.op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start_pt__U182" }, "op_hcompute_hw_input_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" @@ -3582,82 +3307,82 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_1" }, "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U251" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U196" }, "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U249"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U249"} + "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U250" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U195" }, "op_hcompute_hw_input_global_wrapper_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U252" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U197" }, "op_hcompute_hw_input_global_wrapper_stencil_2":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_2" }, "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U246" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U191" }, "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U244"} + "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U245" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U190" }, "op_hcompute_hw_input_global_wrapper_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U247" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U192" }, "op_hcompute_hw_input_global_wrapper_stencil_3":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_3" }, "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U241" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U186" }, "op_hcompute_hw_input_global_wrapper_stencil_3_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U239"} + "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_3_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U240" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U185" }, "op_hcompute_hw_input_global_wrapper_stencil_3_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U242" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U187" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U256" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U201" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U254"} + "genargs":{"ID":["String","_U199"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U255" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U200" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U257" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U202" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" @@ -3666,61 +3391,61 @@ "modref":"global.cu_op_hcompute_hw_output_stencil_1" }, "op_hcompute_hw_output_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U228" + "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U173" }, "op_hcompute_hw_output_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U226"} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U227" + "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U172" }, "op_hcompute_hw_output_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U229" + "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U174" }, "op_hcompute_hw_output_stencil_2":{ "modref":"global.cu_op_hcompute_hw_output_stencil_2" }, "op_hcompute_hw_output_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U224" + "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U169" }, "op_hcompute_hw_output_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U222"} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U223" + "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U168" }, "op_hcompute_hw_output_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U225" + "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U170" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U232" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U177" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U230"} + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U231" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U176" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U233" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U178" }, "op_hcompute_pw_conv_reduction_stencil":{ "modref":"global.cu_op_hcompute_pw_conv_reduction_stencil" @@ -3748,24 +3473,24 @@ } }, "connections":[ - ["self.clk","_U238.clk"], - ["self.hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read.0","_U238.in"], - ["self.clk","_U243.clk"], - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","_U243.in"], - ["self.clk","_U248.clk"], - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","_U248.in"], - ["self.clk","_U253.clk"], - ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","_U253.in"], - ["self.clk","_U258.clk"], - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U258.in"], - ["self.clk","_U263.clk"], - ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read.0","_U263.in"], - ["self.clk","_U268.clk"], - ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read.0","_U268.in"], - ["self.clk","_U273.clk"], - ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read.0","_U273.in"], - ["self.clk","_U278.clk"], - ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read.0","_U278.in"], + ["self.clk","_U183.clk"], + ["self.hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read.0","_U183.in"], + ["self.clk","_U188.clk"], + ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","_U188.in"], + ["self.clk","_U193.clk"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","_U193.in"], + ["self.clk","_U198.clk"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","_U198.in"], + ["self.clk","_U203.clk"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U203.in"], + ["self.clk","_U208.clk"], + ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read.0","_U208.in"], + ["self.clk","_U213.clk"], + ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read.0","_U213.in"], + ["self.clk","_U218.clk"], + ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read.0","_U218.in"], + ["self.clk","_U223.clk"], + ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read.0","_U223.in"], ["self.clk","dw_conv_stencil.clk"], ["op_hcompute_dw_conv_stencil_4.dw_conv_stencil_op_hcompute_dw_conv_stencil_4_write","dw_conv_stencil.op_hcompute_dw_conv_stencil_4_write"], ["op_hcompute_dw_conv_stencil_5.dw_conv_stencil_op_hcompute_dw_conv_stencil_5_write","dw_conv_stencil.op_hcompute_dw_conv_stencil_5_write"], @@ -3820,9 +3545,9 @@ ["self.clk","op_hcompute_dw_conv_stencil_6.clk"], ["self.clk","op_hcompute_dw_conv_stencil_7.clk"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil.clk"], - ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read","op_hcompute_hw_filter_dw_global_wrapper_stencil.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read"], + ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read","op_hcompute_hw_filter_dw_global_wrapper_stencil.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil_1.clk"], - ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read","op_hcompute_hw_filter_dw_global_wrapper_stencil_1.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read"], + ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read","op_hcompute_hw_filter_dw_global_wrapper_stencil_1.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller.stencil_valid","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start.in"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller.clk"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller.clk_en"], @@ -3830,9 +3555,9 @@ ["op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller.rst_n"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller.stencil_valid"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_port_controller.stencil_valid"], - ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start.out"], + ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start.out"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil_2.clk"], - ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read","op_hcompute_hw_filter_dw_global_wrapper_stencil_2.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read"], + ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read","op_hcompute_hw_filter_dw_global_wrapper_stencil_2.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller.stencil_valid","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start.in"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller.clk"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller.clk_en"], @@ -3840,9 +3565,9 @@ ["op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller.rst_n"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller.stencil_valid"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_port_controller.stencil_valid"], - ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start.out"], + ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start.out"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil_3.clk"], - ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read","op_hcompute_hw_filter_dw_global_wrapper_stencil_3.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read"], + ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read","op_hcompute_hw_filter_dw_global_wrapper_stencil_3.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller.stencil_valid","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start.in"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller.clk"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller.clk_en"], @@ -3850,7 +3575,7 @@ ["op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller.rst_n"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller.stencil_valid"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_port_controller.stencil_valid"], - ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start.out"], + ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start.out"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller.stencil_valid","op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start.in"], ["self.clk","op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller.clk"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller.clk_en"], @@ -3858,7 +3583,7 @@ ["op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller.rst_n"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller.stencil_valid"], ["op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start.in","op_hcompute_hw_filter_dw_global_wrapper_stencil_port_controller.stencil_valid"], - ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start.out"], + ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_en","op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start.out"], ["self.clk","op_hcompute_hw_filter_pw_global_wrapper_stencil.clk"], ["self.hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read","op_hcompute_hw_filter_pw_global_wrapper_stencil.hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read"], ["op_hcompute_hw_filter_pw_global_wrapper_stencil_port_controller.stencil_valid","op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start.in"], @@ -3870,9 +3595,9 @@ ["op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start.in","op_hcompute_hw_filter_pw_global_wrapper_stencil_port_controller.stencil_valid"], ["self.hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read_en","op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil.clk"], - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read","op_hcompute_hw_input_global_wrapper_stencil.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read","op_hcompute_hw_input_global_wrapper_stencil.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1.clk"], - ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read","op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read","op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read"], ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_1_exe_start.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.clk"], ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.clk_en"], @@ -3880,9 +3605,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.rst_n"], ["op_hcompute_hw_input_global_wrapper_stencil_1_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid"], ["op_hcompute_hw_input_global_wrapper_stencil_1_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid"], - ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","op_hcompute_hw_input_global_wrapper_stencil_1_read_start.out"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","op_hcompute_hw_input_global_wrapper_stencil_1_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2.clk"], - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read","op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read","op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read"], ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_2_exe_start.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.clk"], ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.clk_en"], @@ -3890,9 +3615,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.rst_n"], ["op_hcompute_hw_input_global_wrapper_stencil_2_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid"], ["op_hcompute_hw_input_global_wrapper_stencil_2_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid"], - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","op_hcompute_hw_input_global_wrapper_stencil_2_read_start.out"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","op_hcompute_hw_input_global_wrapper_stencil_2_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_3.clk"], - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read","op_hcompute_hw_input_global_wrapper_stencil_3.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read"], + ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read","op_hcompute_hw_input_global_wrapper_stencil_3.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read"], ["op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_3_exe_start.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.clk"], ["op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.clk_en"], @@ -3900,7 +3625,7 @@ ["op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.rst_n"], ["op_hcompute_hw_input_global_wrapper_stencil_3_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.stencil_valid"], ["op_hcompute_hw_input_global_wrapper_stencil_3_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.stencil_valid"], - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","op_hcompute_hw_input_global_wrapper_stencil_3_read_start.out"], + ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","op_hcompute_hw_input_global_wrapper_stencil_3_read_start.out"], ["op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_exe_start.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk"], ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk_en"], @@ -3908,7 +3633,7 @@ ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.rst_n"], ["op_hcompute_hw_input_global_wrapper_stencil_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], ["self.clk","op_hcompute_hw_output_stencil.clk"], ["self.hw_output_stencil_clkwrk_8_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_8_op_hcompute_hw_output_stencil_write"], ["pw_conv_reduction_stencil.op_hcompute_hw_output_stencil_read","op_hcompute_hw_output_stencil.pw_conv_reduction_stencil_op_hcompute_hw_output_stencil_read"], @@ -3963,7 +3688,7 @@ ["self.reset","pw_conv_reduction_stencil_clkwrk_dsa12.reset"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start_pt__U271":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start_pt__U216":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3972,7 +3697,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start_pt__U270":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start_pt__U215":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3981,7 +3706,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start_pt__U272":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start_pt__U217":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3990,7 +3715,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start_pt__U266":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start_pt__U211":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -3999,7 +3724,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start_pt__U265":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start_pt__U210":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4008,7 +3733,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start_pt__U267":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start_pt__U212":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4017,7 +3742,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start_pt__U261":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start_pt__U206":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4026,7 +3751,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start_pt__U260":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start_pt__U205":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4035,7 +3760,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start_pt__U262":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start_pt__U207":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4044,7 +3769,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start_pt__U276":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start_pt__U221":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4053,7 +3778,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start_pt__U275":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start_pt__U220":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4062,7 +3787,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start_pt__U277":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start_pt__U222":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4071,7 +3796,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start_pt__U236":{ + "op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start_pt__U181":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4080,7 +3805,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start_pt__U235":{ + "op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start_pt__U180":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4089,7 +3814,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start_pt__U237":{ + "op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start_pt__U182":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4098,7 +3823,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U251":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U196":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4107,7 +3832,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U250":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U195":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4116,7 +3841,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U252":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U197":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4125,7 +3850,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U246":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U191":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4134,7 +3859,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U245":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U190":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4143,7 +3868,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U247":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U192":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4152,7 +3877,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U241":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U186":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4161,7 +3886,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U240":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U185":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4170,7 +3895,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U242":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U187":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4179,7 +3904,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U256":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U201":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4188,7 +3913,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U255":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U200":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4197,7 +3922,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U257":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U202":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4206,7 +3931,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U228":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U173":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4215,7 +3940,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U227":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U172":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4224,7 +3949,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U229":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U174":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4233,7 +3958,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U224":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U169":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4242,7 +3967,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U223":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U168":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4251,7 +3976,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U225":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U170":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4260,7 +3985,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U232":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U177":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4269,7 +3994,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U231":{ + "op_hcompute_hw_output_stencil_read_start_pt__U176":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4278,7 +4003,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U233":{ + "op_hcompute_hw_output_stencil_write_start_pt__U178":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4306,179 +4031,179 @@ ["op_hcompute_pw_conv_reduction_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "d_reg__U198":{ + "d_reg__U143":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U199":{ + "d_reg__U144":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U200":{ + "d_reg__U145":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U201":{ + "d_reg__U146":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U202":{ + "d_reg__U147":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U203":{ + "d_reg__U148":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U204":{ + "d_reg__U149":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U205":{ + "d_reg__U150":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U206":{ + "d_reg__U151":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U207":{ + "d_reg__U152":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U208":{ + "d_reg__U153":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U209":{ + "d_reg__U154":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U210":{ + "d_reg__U155":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U211":{ + "d_reg__U156":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U212":{ + "d_reg__U157":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U213":{ + "d_reg__U158":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U214":{ + "d_reg__U159":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U215":{ + "d_reg__U160":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U216":{ + "d_reg__U161":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U217":{ + "d_reg__U162":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U218":{ + "d_reg__U163":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U219":{ + "d_reg__U164":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U220":{ + "d_reg__U165":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U221":{ + "d_reg__U166":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","d_reg__U198.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_write.0","d_reg__U198.in"], - ["d_reg__U199.in","d_reg__U198.out"], - ["self.clk","d_reg__U199.clk"], - ["d_reg__U200.in","d_reg__U199.out"], - ["self.clk","d_reg__U200.clk"], - ["d_reg__U201.in","d_reg__U200.out"], - ["self.clk","d_reg__U201.clk"], - ["d_reg__U202.in","d_reg__U201.out"], - ["self.clk","d_reg__U202.clk"], - ["d_reg__U203.in","d_reg__U202.out"], - ["self.clk","d_reg__U203.clk"], - ["d_reg__U204.in","d_reg__U203.out"], - ["self.clk","d_reg__U204.clk"], - ["d_reg__U205.in","d_reg__U204.out"], - ["self.clk","d_reg__U205.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_3_read.0","d_reg__U205.out"], - ["self.clk","d_reg__U206.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_1_write.0","d_reg__U206.in"], - ["d_reg__U207.in","d_reg__U206.out"], - ["self.clk","d_reg__U207.clk"], - ["d_reg__U208.in","d_reg__U207.out"], - ["self.clk","d_reg__U208.clk"], - ["d_reg__U209.in","d_reg__U208.out"], - ["self.clk","d_reg__U209.clk"], - ["d_reg__U210.in","d_reg__U209.out"], - ["self.clk","d_reg__U210.clk"], - ["d_reg__U211.in","d_reg__U210.out"], - ["self.clk","d_reg__U211.clk"], - ["d_reg__U212.in","d_reg__U211.out"], - ["self.clk","d_reg__U212.clk"], - ["d_reg__U213.in","d_reg__U212.out"], - ["self.clk","d_reg__U213.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_4_read.0","d_reg__U213.out"], - ["self.clk","d_reg__U214.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_2_write.0","d_reg__U214.in"], - ["d_reg__U215.in","d_reg__U214.out"], - ["self.clk","d_reg__U215.clk"], - ["d_reg__U216.in","d_reg__U215.out"], - ["self.clk","d_reg__U216.clk"], - ["d_reg__U217.in","d_reg__U216.out"], - ["self.clk","d_reg__U217.clk"], - ["d_reg__U218.in","d_reg__U217.out"], - ["self.clk","d_reg__U218.clk"], - ["d_reg__U219.in","d_reg__U218.out"], - ["self.clk","d_reg__U219.clk"], - ["d_reg__U220.in","d_reg__U219.out"], - ["self.clk","d_reg__U220.clk"], - ["d_reg__U221.in","d_reg__U220.out"], - ["self.clk","d_reg__U221.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_5_read.0","d_reg__U221.out"] + ["self.clk","d_reg__U143.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_write.0","d_reg__U143.in"], + ["d_reg__U144.in","d_reg__U143.out"], + ["self.clk","d_reg__U144.clk"], + ["d_reg__U145.in","d_reg__U144.out"], + ["self.clk","d_reg__U145.clk"], + ["d_reg__U146.in","d_reg__U145.out"], + ["self.clk","d_reg__U146.clk"], + ["d_reg__U147.in","d_reg__U146.out"], + ["self.clk","d_reg__U147.clk"], + ["d_reg__U148.in","d_reg__U147.out"], + ["self.clk","d_reg__U148.clk"], + ["d_reg__U149.in","d_reg__U148.out"], + ["self.clk","d_reg__U149.clk"], + ["d_reg__U150.in","d_reg__U149.out"], + ["self.clk","d_reg__U150.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_3_read.0","d_reg__U150.out"], + ["self.clk","d_reg__U151.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_1_write.0","d_reg__U151.in"], + ["d_reg__U152.in","d_reg__U151.out"], + ["self.clk","d_reg__U152.clk"], + ["d_reg__U153.in","d_reg__U152.out"], + ["self.clk","d_reg__U153.clk"], + ["d_reg__U154.in","d_reg__U153.out"], + ["self.clk","d_reg__U154.clk"], + ["d_reg__U155.in","d_reg__U154.out"], + ["self.clk","d_reg__U155.clk"], + ["d_reg__U156.in","d_reg__U155.out"], + ["self.clk","d_reg__U156.clk"], + ["d_reg__U157.in","d_reg__U156.out"], + ["self.clk","d_reg__U157.clk"], + ["d_reg__U158.in","d_reg__U157.out"], + ["self.clk","d_reg__U158.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_4_read.0","d_reg__U158.out"], + ["self.clk","d_reg__U159.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_2_write.0","d_reg__U159.in"], + ["d_reg__U160.in","d_reg__U159.out"], + ["self.clk","d_reg__U160.clk"], + ["d_reg__U161.in","d_reg__U160.out"], + ["self.clk","d_reg__U161.clk"], + ["d_reg__U162.in","d_reg__U161.out"], + ["self.clk","d_reg__U162.clk"], + ["d_reg__U163.in","d_reg__U162.out"], + ["self.clk","d_reg__U163.clk"], + ["d_reg__U164.in","d_reg__U163.out"], + ["self.clk","d_reg__U164.clk"], + ["d_reg__U165.in","d_reg__U164.out"], + ["self.clk","d_reg__U165.clk"], + ["d_reg__U166.in","d_reg__U165.out"], + ["self.clk","d_reg__U166.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_5_read.0","d_reg__U166.out"] ] }, "pw_conv_reduction_stencil_ub":{ diff --git a/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled_garnet.json b/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled_garnet.json index 2b2fd4733..7fd3c62e4 100644 --- a/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled_garnet.json +++ b/aha_garnet_design_new/mobilenet_unrolled/mobilenet_unrolled_garnet.json @@ -151,26 +151,26 @@ ["dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U281":{ + "PE_init_U226":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U279":{ + "_U224":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U280":{ + "_U225":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U279.out","PE_init_U281.data.in.0"], - ["_U280.out","PE_init_U281.data.in.1"], - ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_write.0","PE_init_U281.data.out"], + ["_U224.out","PE_init_U226.data.in.0"], + ["_U225.out","PE_init_U226.data.in.1"], + ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_write.0","PE_init_U226.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -182,26 +182,26 @@ ["dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U284":{ + "PE_init_U229":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U282":{ + "_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U283":{ + "_U228":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U282.out","PE_init_U284.data.in.0"], - ["_U283.out","PE_init_U284.data.in.1"], - ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_1_write.0","PE_init_U284.data.out"], + ["_U227.out","PE_init_U229.data.in.0"], + ["_U228.out","PE_init_U229.data.in.1"], + ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_1_write.0","PE_init_U229.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -213,26 +213,26 @@ ["dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U287":{ + "PE_init_U232":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U285":{ + "_U230":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U286":{ + "_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U285.out","PE_init_U287.data.in.0"], - ["_U286.out","PE_init_U287.data.in.1"], - ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_2_write.0","PE_init_U287.data.out"], + ["_U230.out","PE_init_U232.data.in.0"], + ["_U231.out","PE_init_U232.data.in.1"], + ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_2_write.0","PE_init_U232.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -244,26 +244,26 @@ ["dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U290":{ + "PE_init_U235":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U288":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U289":{ + "_U234":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U288.out","PE_init_U290.data.in.0"], - ["_U289.out","PE_init_U290.data.in.1"], - ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_3_write.0","PE_init_U290.data.out"], + ["_U233.out","PE_init_U235.data.in.0"], + ["_U234.out","PE_init_U235.data.in.1"], + ["self.dw_conv_stencil_clkwrk_dsa11_op_hcompute_dw_conv_stencil_3_write.0","PE_init_U235.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -844,11 +844,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_write.0"], + ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -857,11 +857,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write.0"], + ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -870,11 +870,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write.0"], + ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -883,11 +883,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write.0"], + ["self.hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read.0","self.hw_filter_dw_global_wrapper_stencil_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -909,11 +909,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write.0"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -922,11 +922,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write.0"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -935,11 +935,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write.0"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -948,11 +948,11 @@ ["clk",["Named","coreir.clkIn"]], ["valid_pass_in","BitIn"], ["valid_pass_out","Bit"], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "connections":[ - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write.0"], + ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write.0"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1003,26 +1003,26 @@ ["pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U293":{ + "PE_init_U238":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U291":{ + "_U236":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U292":{ + "_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U291.out","PE_init_U293.data.in.0"], - ["_U292.out","PE_init_U293.data.in.1"], - ["self.pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_write.0","PE_init_U293.data.out"], + ["_U236.out","PE_init_U238.data.in.0"], + ["_U237.out","PE_init_U238.data.in.1"], + ["self.pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_write.0","PE_init_U238.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1034,26 +1034,26 @@ ["pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U296":{ + "PE_init_U241":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U294":{ + "_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U295":{ + "_U240":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U294.out","PE_init_U296.data.in.0"], - ["_U295.out","PE_init_U296.data.in.1"], - ["self.pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_1_write.0","PE_init_U296.data.out"], + ["_U239.out","PE_init_U241.data.in.0"], + ["_U240.out","PE_init_U241.data.in.1"], + ["self.pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_1_write.0","PE_init_U241.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1065,26 +1065,26 @@ ["pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U299":{ + "PE_init_U244":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U297":{ + "_U242":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U298":{ + "_U243":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U297.out","PE_init_U299.data.in.0"], - ["_U298.out","PE_init_U299.data.in.1"], - ["self.pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_2_write.0","PE_init_U299.data.out"], + ["_U242.out","PE_init_U244.data.in.0"], + ["_U243.out","PE_init_U244.data.in.1"], + ["self.pw_conv_reduction_stencil_clkwrk_dsa12_op_hcompute_pw_conv_reduction_stencil_2_write.0","PE_init_U244.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1602,26 +1602,26 @@ ["out_dw_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U302":{ + "PE_init_U247":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U300":{ + "_U245":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U301":{ + "_U246":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U300.out","PE_init_U302.data.in.0"], - ["_U301.out","PE_init_U302.data.in.1"], - ["self.out_dw_conv_stencil","PE_init_U302.data.out"] + ["_U245.out","PE_init_U247.data.in.0"], + ["_U246.out","PE_init_U247.data.in.1"], + ["self.out_dw_conv_stencil","PE_init_U247.data.out"] ] }, "hcompute_dw_conv_stencil_1":{ @@ -1629,26 +1629,26 @@ ["out_dw_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U305":{ + "PE_init_U250":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U303":{ + "_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U304":{ + "_U249":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U303.out","PE_init_U305.data.in.0"], - ["_U304.out","PE_init_U305.data.in.1"], - ["self.out_dw_conv_stencil","PE_init_U305.data.out"] + ["_U248.out","PE_init_U250.data.in.0"], + ["_U249.out","PE_init_U250.data.in.1"], + ["self.out_dw_conv_stencil","PE_init_U250.data.out"] ] }, "hcompute_dw_conv_stencil_2":{ @@ -1656,26 +1656,26 @@ ["out_dw_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U308":{ + "PE_init_U253":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U306":{ + "_U251":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U307":{ + "_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U306.out","PE_init_U308.data.in.0"], - ["_U307.out","PE_init_U308.data.in.1"], - ["self.out_dw_conv_stencil","PE_init_U308.data.out"] + ["_U251.out","PE_init_U253.data.in.0"], + ["_U252.out","PE_init_U253.data.in.1"], + ["self.out_dw_conv_stencil","PE_init_U253.data.out"] ] }, "hcompute_dw_conv_stencil_3":{ @@ -1683,26 +1683,26 @@ ["out_dw_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U311":{ + "PE_init_U256":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U309":{ + "_U254":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U310":{ + "_U255":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U309.out","PE_init_U311.data.in.0"], - ["_U310.out","PE_init_U311.data.in.1"], - ["self.out_dw_conv_stencil","PE_init_U311.data.out"] + ["_U254.out","PE_init_U256.data.in.0"], + ["_U255.out","PE_init_U256.data.in.1"], + ["self.out_dw_conv_stencil","PE_init_U256.data.out"] ] }, "hcompute_dw_conv_stencil_4":{ @@ -2374,26 +2374,26 @@ ["out_pw_conv_reduction_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U314":{ + "PE_init_U259":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U312":{ + "_U257":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U313":{ + "_U258":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U312.out","PE_init_U314.data.in.0"], - ["_U313.out","PE_init_U314.data.in.1"], - ["self.out_pw_conv_reduction_stencil","PE_init_U314.data.out"] + ["_U257.out","PE_init_U259.data.in.0"], + ["_U258.out","PE_init_U259.data.in.1"], + ["self.out_pw_conv_reduction_stencil","PE_init_U259.data.out"] ] }, "hcompute_pw_conv_reduction_stencil_1":{ @@ -2401,26 +2401,26 @@ ["out_pw_conv_reduction_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U317":{ + "PE_init_U262":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U315":{ + "_U260":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U316":{ + "_U261":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U315.out","PE_init_U317.data.in.0"], - ["_U316.out","PE_init_U317.data.in.1"], - ["self.out_pw_conv_reduction_stencil","PE_init_U317.data.out"] + ["_U260.out","PE_init_U262.data.in.0"], + ["_U261.out","PE_init_U262.data.in.1"], + ["self.out_pw_conv_reduction_stencil","PE_init_U262.data.out"] ] }, "hcompute_pw_conv_reduction_stencil_2":{ @@ -2428,26 +2428,26 @@ ["out_pw_conv_reduction_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U320":{ + "PE_init_U265":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U318":{ + "_U263":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U319":{ + "_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U318.out","PE_init_U320.data.in.0"], - ["_U319.out","PE_init_U320.data.in.1"], - ["self.out_pw_conv_reduction_stencil","PE_init_U320.data.out"] + ["_U263.out","PE_init_U265.data.in.0"], + ["_U264.out","PE_init_U265.data.in.1"], + ["self.out_pw_conv_reduction_stencil","PE_init_U265.data.out"] ] }, "hcompute_pw_conv_reduction_stencil_3":{ @@ -2680,150 +2680,6 @@ ["op_hcompute_hw_filter_dw_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U101":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U103":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U43":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U45":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U47":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U53":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U55":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U57":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U61":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U63":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U65":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U67":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U69":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U71":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U73":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U75":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U77":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U79":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U81":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U83":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U85":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U87":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U91":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U93":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U95":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U97":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U99":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2831,7 +2687,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -2841,7 +2697,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -2851,7 +2707,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -2861,7 +2717,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -2871,7 +2727,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -2881,7 +2737,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -2891,7 +2747,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U47"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -2901,7 +2757,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -2911,7 +2767,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U49"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -2921,7 +2777,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -2931,7 +2787,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U51"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -2941,7 +2797,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -2951,7 +2807,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U72"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -2961,7 +2817,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -2971,7 +2827,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U76"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -2981,7 +2837,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U78"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U55"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -2991,7 +2847,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U80"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -3001,7 +2857,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U82"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U57"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -3011,7 +2867,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -3021,7 +2877,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U86"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U59"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -3031,7 +2887,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U88"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -3041,7 +2897,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U61"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -3051,7 +2907,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -3061,7 +2917,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U92"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -3071,7 +2927,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U63"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -3081,7 +2937,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U96"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -3091,7 +2947,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U65"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -3101,7 +2957,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U100"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -3111,7 +2967,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U102"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U67"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -3121,7 +2977,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -3131,7 +2987,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -3141,7 +2997,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -3151,7 +3007,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -3161,7 +3017,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -3171,7 +3027,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -3181,7 +3037,7 @@ }, "ub_hw_filter_dw_global_wrapper_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U41"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -3383,54 +3239,6 @@ ["op_hcompute_pw_conv_reduction_stencil_5_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U105":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U107":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U109":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U111":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U113":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U115":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U117":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U121":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U123":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U125":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U127":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -3438,7 +3246,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -3448,7 +3256,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U78"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -3458,7 +3266,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U79"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[18],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -3468,7 +3276,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U106"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U69"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -3478,7 +3286,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -3488,7 +3296,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U71"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[16],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -3498,7 +3306,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U72"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -3508,7 +3316,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U73"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -3518,7 +3326,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -3528,7 +3336,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[17],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -3538,7 +3346,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U76"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -3548,7 +3356,7 @@ }, "ub_hw_filter_pw_global_wrapper_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U77"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -3638,310 +3446,282 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U129":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U131":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U133":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U135":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U137":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U139":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U141":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "d_reg__U142$reg0":{ + "d_reg__U100$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U143$reg0":{ + "d_reg__U101$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U144$reg0":{ + "d_reg__U102$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U145$reg0":{ + "d_reg__U103$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U146$reg0":{ + "d_reg__U104$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U147$reg0":{ + "d_reg__U105$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U148$reg0":{ + "d_reg__U106$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U149$reg0":{ + "d_reg__U107$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U150$reg0":{ + "d_reg__U108$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U151$reg0":{ + "d_reg__U109$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U152$reg0":{ + "d_reg__U110$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U153$reg0":{ + "d_reg__U111$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U154$reg0":{ + "d_reg__U112$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U155$reg0":{ + "d_reg__U113$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U156$reg0":{ + "d_reg__U114$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U157$reg0":{ + "d_reg__U115$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U158$reg0":{ + "d_reg__U116$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U159$reg0":{ + "d_reg__U117$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U160$reg0":{ + "d_reg__U118$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U161$reg0":{ + "d_reg__U119$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U162$reg0":{ + "d_reg__U120$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U163$reg0":{ + "d_reg__U121$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U164$reg0":{ + "d_reg__U122$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U165$reg0":{ + "d_reg__U123$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U166$reg0":{ + "d_reg__U124$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U167$reg0":{ + "d_reg__U125$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U168$reg0":{ + "d_reg__U126$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U169$reg0":{ + "d_reg__U127$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U170$reg0":{ + "d_reg__U128$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U171$reg0":{ + "d_reg__U129$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U172$reg0":{ + "d_reg__U130$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U173$reg0":{ + "d_reg__U131$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U174$reg0":{ + "d_reg__U132$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U175$reg0":{ + "d_reg__U133$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U176$reg0":{ + "d_reg__U134$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U177$reg0":{ + "d_reg__U135$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U178$reg0":{ + "d_reg__U136$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U179$reg0":{ + "d_reg__U137$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U180$reg0":{ + "d_reg__U138$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U181$reg0":{ + "d_reg__U139$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U182$reg0":{ + "d_reg__U140$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U183$reg0":{ + "d_reg__U141$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U184$reg0":{ + "d_reg__U142$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U185$reg0":{ + "d_reg__U87$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U186$reg0":{ + "d_reg__U88$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U187$reg0":{ + "d_reg__U89$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U188$reg0":{ + "d_reg__U90$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U189$reg0":{ + "d_reg__U91$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U190$reg0":{ + "d_reg__U92$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U191$reg0":{ + "d_reg__U93$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U192$reg0":{ + "d_reg__U94$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U193$reg0":{ + "d_reg__U95$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U194$reg0":{ + "d_reg__U96$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U195$reg0":{ + "d_reg__U97$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U196$reg0":{ + "d_reg__U98$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U197$reg0":{ + "d_reg__U99$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -3953,7 +3733,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U80"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -3963,7 +3743,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U81"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -3973,7 +3753,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U82"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -3983,7 +3763,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U83"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -3993,7 +3773,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -4003,7 +3783,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U85"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -4013,151 +3793,151 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U86"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[69],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ + ["self.clk","d_reg__U100$reg0.clk"], + ["d_reg__U99$reg0.out","d_reg__U100$reg0.in"], + ["d_reg__U101$reg0.in","d_reg__U100$reg0.out"], + ["self.clk","d_reg__U101$reg0.clk"], + ["d_reg__U102$reg0.in","d_reg__U101$reg0.out"], + ["self.clk","d_reg__U102$reg0.clk"], + ["d_reg__U119$reg0.in","d_reg__U102$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.7","d_reg__U102$reg0.out"], + ["self.clk","d_reg__U103$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0","d_reg__U103$reg0.in"], + ["d_reg__U104$reg0.in","d_reg__U103$reg0.out"], + ["self.clk","d_reg__U104$reg0.clk"], + ["d_reg__U105$reg0.in","d_reg__U104$reg0.out"], + ["self.clk","d_reg__U105$reg0.clk"], + ["d_reg__U106$reg0.in","d_reg__U105$reg0.out"], + ["self.clk","d_reg__U106$reg0.clk"], + ["d_reg__U107$reg0.in","d_reg__U106$reg0.out"], + ["self.clk","d_reg__U107$reg0.clk"], + ["d_reg__U108$reg0.in","d_reg__U107$reg0.out"], + ["self.clk","d_reg__U108$reg0.clk"], + ["d_reg__U109$reg0.in","d_reg__U108$reg0.out"], + ["self.clk","d_reg__U109$reg0.clk"], + ["d_reg__U110$reg0.in","d_reg__U109$reg0.out"], + ["self.clk","d_reg__U110$reg0.clk"], + ["d_reg__U125$reg0.in","d_reg__U110$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.7","d_reg__U110$reg0.out"], + ["self.clk","d_reg__U111$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_3_write.0","d_reg__U111$reg0.in"], + ["d_reg__U112$reg0.in","d_reg__U111$reg0.out"], + ["self.clk","d_reg__U112$reg0.clk"], + ["d_reg__U113$reg0.in","d_reg__U112$reg0.out"], + ["self.clk","d_reg__U113$reg0.clk"], + ["d_reg__U114$reg0.in","d_reg__U113$reg0.out"], + ["self.clk","d_reg__U114$reg0.clk"], + ["d_reg__U115$reg0.in","d_reg__U114$reg0.out"], + ["self.clk","d_reg__U115$reg0.clk"], + ["d_reg__U116$reg0.in","d_reg__U115$reg0.out"], + ["self.clk","d_reg__U116$reg0.clk"], + ["d_reg__U117$reg0.in","d_reg__U116$reg0.out"], + ["self.clk","d_reg__U117$reg0.clk"], + ["d_reg__U118$reg0.in","d_reg__U117$reg0.out"], + ["self.clk","d_reg__U118$reg0.clk"], + ["d_reg__U131$reg0.in","d_reg__U118$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.7","d_reg__U118$reg0.out"], + ["self.clk","d_reg__U119$reg0.clk"], + ["d_reg__U120$reg0.in","d_reg__U119$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.8","d_reg__U119$reg0.out"], + ["self.clk","d_reg__U120$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_5_read.6","d_reg__U120$reg0.out"], + ["self.clk","d_reg__U121$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_1","d_reg__U121$reg0.in"], + ["d_reg__U122$reg0.in","d_reg__U121$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.4","d_reg__U121$reg0.out"], + ["self.clk","d_reg__U122$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_5_read.3","d_reg__U122$reg0.out"], + ["self.clk","d_reg__U123$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_0","d_reg__U123$reg0.in"], + ["d_reg__U124$reg0.in","d_reg__U123$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_5_read.1","d_reg__U123$reg0.out"], + ["self.clk","d_reg__U124$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_5_read.0","d_reg__U124$reg0.out"], + ["self.clk","d_reg__U125$reg0.clk"], + ["d_reg__U126$reg0.in","d_reg__U125$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.8","d_reg__U125$reg0.out"], + ["self.clk","d_reg__U126$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_6_read.6","d_reg__U126$reg0.out"], + ["self.clk","d_reg__U127$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U127$reg0.in"], + ["d_reg__U128$reg0.in","d_reg__U127$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.4","d_reg__U127$reg0.out"], + ["self.clk","d_reg__U128$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_6_read.3","d_reg__U128$reg0.out"], + ["self.clk","d_reg__U129$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_1_garnet.data_out_0","d_reg__U129$reg0.in"], + ["d_reg__U130$reg0.in","d_reg__U129$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_6_read.1","d_reg__U129$reg0.out"], + ["self.clk","d_reg__U130$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_6_read.0","d_reg__U130$reg0.out"], + ["self.clk","d_reg__U131$reg0.clk"], + ["d_reg__U132$reg0.in","d_reg__U131$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.8","d_reg__U131$reg0.out"], + ["self.clk","d_reg__U132$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_7_read.6","d_reg__U132$reg0.out"], + ["self.clk","d_reg__U133$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_out_0","d_reg__U133$reg0.in"], + ["d_reg__U134$reg0.in","d_reg__U133$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.4","d_reg__U133$reg0.out"], + ["self.clk","d_reg__U134$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_7_read.3","d_reg__U134$reg0.out"], + ["self.clk","d_reg__U135$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_3_garnet.data_out_0","d_reg__U135$reg0.in"], + ["d_reg__U136$reg0.in","d_reg__U135$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_7_read.1","d_reg__U135$reg0.out"], + ["self.clk","d_reg__U136$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_7_read.0","d_reg__U136$reg0.out"], + ["self.clk","d_reg__U137$reg0.clk"], + ["d_reg__U94$reg0.out","d_reg__U137$reg0.in"], + ["d_reg__U138$reg0.in","d_reg__U137$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.8","d_reg__U137$reg0.out"], + ["self.clk","d_reg__U138$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_4_read.6","d_reg__U138$reg0.out"], + ["self.clk","d_reg__U139$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_4_garnet.data_out_0","d_reg__U139$reg0.in"], + ["d_reg__U140$reg0.in","d_reg__U139$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.4","d_reg__U139$reg0.out"], + ["self.clk","d_reg__U140$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_4_read.3","d_reg__U140$reg0.out"], + ["self.clk","d_reg__U141$reg0.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_5_garnet.data_out_0","d_reg__U141$reg0.in"], + ["d_reg__U142$reg0.in","d_reg__U141$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.1","d_reg__U141$reg0.out"], ["self.clk","d_reg__U142$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U142$reg0.in"], - ["d_reg__U143$reg0.in","d_reg__U142$reg0.out"], - ["self.clk","d_reg__U143$reg0.clk"], - ["d_reg__U144$reg0.in","d_reg__U143$reg0.out"], - ["self.clk","d_reg__U144$reg0.clk"], - ["d_reg__U145$reg0.in","d_reg__U144$reg0.out"], - ["self.clk","d_reg__U145$reg0.clk"], - ["d_reg__U146$reg0.in","d_reg__U145$reg0.out"], - ["self.clk","d_reg__U146$reg0.clk"], - ["d_reg__U147$reg0.in","d_reg__U146$reg0.out"], - ["self.clk","d_reg__U147$reg0.clk"], - ["d_reg__U148$reg0.in","d_reg__U147$reg0.out"], - ["self.clk","d_reg__U148$reg0.clk"], - ["d_reg__U149$reg0.in","d_reg__U148$reg0.out"], - ["self.clk","d_reg__U149$reg0.clk"], - ["d_reg__U192$reg0.in","d_reg__U149$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.7","d_reg__U149$reg0.out"], - ["self.clk","d_reg__U150$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0","d_reg__U150$reg0.in"], - ["d_reg__U151$reg0.in","d_reg__U150$reg0.out"], - ["self.clk","d_reg__U151$reg0.clk"], - ["d_reg__U152$reg0.in","d_reg__U151$reg0.out"], - ["self.clk","d_reg__U152$reg0.clk"], - ["d_reg__U153$reg0.in","d_reg__U152$reg0.out"], - ["self.clk","d_reg__U153$reg0.clk"], - ["d_reg__U154$reg0.in","d_reg__U153$reg0.out"], - ["self.clk","d_reg__U154$reg0.clk"], - ["d_reg__U155$reg0.in","d_reg__U154$reg0.out"], - ["self.clk","d_reg__U155$reg0.clk"], - ["d_reg__U156$reg0.in","d_reg__U155$reg0.out"], - ["self.clk","d_reg__U156$reg0.clk"], - ["d_reg__U157$reg0.in","d_reg__U156$reg0.out"], - ["self.clk","d_reg__U157$reg0.clk"], - ["d_reg__U174$reg0.in","d_reg__U157$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.7","d_reg__U157$reg0.out"], - ["self.clk","d_reg__U158$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0","d_reg__U158$reg0.in"], - ["d_reg__U159$reg0.in","d_reg__U158$reg0.out"], - ["self.clk","d_reg__U159$reg0.clk"], - ["d_reg__U160$reg0.in","d_reg__U159$reg0.out"], - ["self.clk","d_reg__U160$reg0.clk"], - ["d_reg__U161$reg0.in","d_reg__U160$reg0.out"], - ["self.clk","d_reg__U161$reg0.clk"], - ["d_reg__U162$reg0.in","d_reg__U161$reg0.out"], - ["self.clk","d_reg__U162$reg0.clk"], - ["d_reg__U163$reg0.in","d_reg__U162$reg0.out"], - ["self.clk","d_reg__U163$reg0.clk"], - ["d_reg__U164$reg0.in","d_reg__U163$reg0.out"], - ["self.clk","d_reg__U164$reg0.clk"], - ["d_reg__U165$reg0.in","d_reg__U164$reg0.out"], - ["self.clk","d_reg__U165$reg0.clk"], - ["d_reg__U180$reg0.in","d_reg__U165$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.7","d_reg__U165$reg0.out"], - ["self.clk","d_reg__U166$reg0.clk"], - ["self.op_hcompute_hw_input_global_wrapper_stencil_3_write.0","d_reg__U166$reg0.in"], - ["d_reg__U167$reg0.in","d_reg__U166$reg0.out"], - ["self.clk","d_reg__U167$reg0.clk"], - ["d_reg__U168$reg0.in","d_reg__U167$reg0.out"], - ["self.clk","d_reg__U168$reg0.clk"], - ["d_reg__U169$reg0.in","d_reg__U168$reg0.out"], - ["self.clk","d_reg__U169$reg0.clk"], - ["d_reg__U170$reg0.in","d_reg__U169$reg0.out"], - ["self.clk","d_reg__U170$reg0.clk"], - ["d_reg__U171$reg0.in","d_reg__U170$reg0.out"], - ["self.clk","d_reg__U171$reg0.clk"], - ["d_reg__U172$reg0.in","d_reg__U171$reg0.out"], - ["self.clk","d_reg__U172$reg0.clk"], - ["d_reg__U173$reg0.in","d_reg__U172$reg0.out"], - ["self.clk","d_reg__U173$reg0.clk"], - ["d_reg__U186$reg0.in","d_reg__U173$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.7","d_reg__U173$reg0.out"], - ["self.clk","d_reg__U174$reg0.clk"], - ["d_reg__U175$reg0.in","d_reg__U174$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.8","d_reg__U174$reg0.out"], - ["self.clk","d_reg__U175$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_5_read.6","d_reg__U175$reg0.out"], - ["self.clk","d_reg__U176$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_1","d_reg__U176$reg0.in"], - ["d_reg__U177$reg0.in","d_reg__U176$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.4","d_reg__U176$reg0.out"], - ["self.clk","d_reg__U177$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_5_read.3","d_reg__U177$reg0.out"], - ["self.clk","d_reg__U178$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_0","d_reg__U178$reg0.in"], - ["d_reg__U179$reg0.in","d_reg__U178$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_5_read.1","d_reg__U178$reg0.out"], - ["self.clk","d_reg__U179$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_5_read.0","d_reg__U179$reg0.out"], - ["self.clk","d_reg__U180$reg0.clk"], - ["d_reg__U181$reg0.in","d_reg__U180$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.8","d_reg__U180$reg0.out"], - ["self.clk","d_reg__U181$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_6_read.6","d_reg__U181$reg0.out"], - ["self.clk","d_reg__U182$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","d_reg__U182$reg0.in"], - ["d_reg__U183$reg0.in","d_reg__U182$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.4","d_reg__U182$reg0.out"], - ["self.clk","d_reg__U183$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_6_read.3","d_reg__U183$reg0.out"], - ["self.clk","d_reg__U184$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_1_garnet.data_out_0","d_reg__U184$reg0.in"], - ["d_reg__U185$reg0.in","d_reg__U184$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_6_read.1","d_reg__U184$reg0.out"], - ["self.clk","d_reg__U185$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_6_read.0","d_reg__U185$reg0.out"], - ["self.clk","d_reg__U186$reg0.clk"], - ["d_reg__U187$reg0.in","d_reg__U186$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.8","d_reg__U186$reg0.out"], - ["self.clk","d_reg__U187$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_7_read.6","d_reg__U187$reg0.out"], - ["self.clk","d_reg__U188$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_out_0","d_reg__U188$reg0.in"], - ["d_reg__U189$reg0.in","d_reg__U188$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.4","d_reg__U188$reg0.out"], - ["self.clk","d_reg__U189$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_7_read.3","d_reg__U189$reg0.out"], - ["self.clk","d_reg__U190$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_3_garnet.data_out_0","d_reg__U190$reg0.in"], - ["d_reg__U191$reg0.in","d_reg__U190$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_7_read.1","d_reg__U190$reg0.out"], - ["self.clk","d_reg__U191$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_7_read.0","d_reg__U191$reg0.out"], - ["self.clk","d_reg__U192$reg0.clk"], - ["d_reg__U193$reg0.in","d_reg__U192$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.8","d_reg__U192$reg0.out"], - ["self.clk","d_reg__U193$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_4_read.6","d_reg__U193$reg0.out"], - ["self.clk","d_reg__U194$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_4_garnet.data_out_0","d_reg__U194$reg0.in"], - ["d_reg__U195$reg0.in","d_reg__U194$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.4","d_reg__U194$reg0.out"], - ["self.clk","d_reg__U195$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_4_read.3","d_reg__U195$reg0.out"], - ["self.clk","d_reg__U196$reg0.clk"], - ["ub_hw_input_global_wrapper_stencil_BANK_5_garnet.data_out_0","d_reg__U196$reg0.in"], - ["d_reg__U197$reg0.in","d_reg__U196$reg0.out"], - ["self.op_hcompute_dw_conv_stencil_4_read.1","d_reg__U196$reg0.out"], - ["self.clk","d_reg__U197$reg0.clk"], - ["self.op_hcompute_dw_conv_stencil_4_read.0","d_reg__U197$reg0.out"], + ["self.op_hcompute_dw_conv_stencil_4_read.0","d_reg__U142$reg0.out"], + ["self.clk","d_reg__U87$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_write.0","d_reg__U87$reg0.in"], + ["d_reg__U88$reg0.in","d_reg__U87$reg0.out"], + ["self.clk","d_reg__U88$reg0.clk"], + ["d_reg__U89$reg0.in","d_reg__U88$reg0.out"], + ["self.clk","d_reg__U89$reg0.clk"], + ["d_reg__U90$reg0.in","d_reg__U89$reg0.out"], + ["self.clk","d_reg__U90$reg0.clk"], + ["d_reg__U91$reg0.in","d_reg__U90$reg0.out"], + ["self.clk","d_reg__U91$reg0.clk"], + ["d_reg__U92$reg0.in","d_reg__U91$reg0.out"], + ["self.clk","d_reg__U92$reg0.clk"], + ["d_reg__U93$reg0.in","d_reg__U92$reg0.out"], + ["self.clk","d_reg__U93$reg0.clk"], + ["d_reg__U94$reg0.in","d_reg__U93$reg0.out"], + ["self.clk","d_reg__U94$reg0.clk"], + ["self.op_hcompute_dw_conv_stencil_4_read.7","d_reg__U94$reg0.out"], + ["self.clk","d_reg__U95$reg0.clk"], + ["self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0","d_reg__U95$reg0.in"], + ["d_reg__U96$reg0.in","d_reg__U95$reg0.out"], + ["self.clk","d_reg__U96$reg0.clk"], + ["d_reg__U97$reg0.in","d_reg__U96$reg0.out"], + ["self.clk","d_reg__U97$reg0.clk"], + ["d_reg__U98$reg0.in","d_reg__U97$reg0.out"], + ["self.clk","d_reg__U98$reg0.clk"], + ["d_reg__U99$reg0.in","d_reg__U98$reg0.out"], + ["self.clk","d_reg__U99$reg0.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_1_garnet.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_2_garnet.clk","self.clk"], @@ -4200,24 +3980,24 @@ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["reset","BitIn"], - ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_en","Bit"], - ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_en","Bit"], + ["hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read_en","Bit"], ["hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","Bit"], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], - ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","Bit"], + ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_output_stencil_clkwrk_10_op_hcompute_hw_output_stencil_2_write_valid","Bit"], ["hw_output_stencil_clkwrk_10_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]], ["hw_output_stencil_clkwrk_8_op_hcompute_hw_output_stencil_write_valid","Bit"], @@ -4386,150 +4166,6 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U101":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U103":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U43":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U45":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U47":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U53":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U55":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U57":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U61":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U63":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U65":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U67":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U69":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U71":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U73":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U75":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U77":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U79":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U81":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U83":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U85":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U87":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U91":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U93":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U95":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U97":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_dw_global_wrapper_stencil$chain_en_const_U99":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4537,7 +4173,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -4547,7 +4183,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -4557,7 +4193,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -4567,7 +4203,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -4577,7 +4213,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -4587,7 +4223,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -4597,7 +4233,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U47"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -4607,7 +4243,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -4617,7 +4253,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U49"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -4627,7 +4263,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -4637,7 +4273,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U51"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -4647,7 +4283,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -4657,7 +4293,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U72"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -4667,7 +4303,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -4677,7 +4313,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U76"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -4687,7 +4323,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U78"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U55"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -4697,7 +4333,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U80"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -4707,7 +4343,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U82"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U57"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -4717,7 +4353,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -4727,7 +4363,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U86"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U59"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -4737,7 +4373,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U88"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -4747,7 +4383,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U61"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -4757,7 +4393,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -4767,7 +4403,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U92"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -4777,7 +4413,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U63"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -4787,7 +4423,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U96"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -4797,7 +4433,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U65"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -4807,7 +4443,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U100"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -4817,7 +4453,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U102"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U67"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -4827,7 +4463,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -4837,7 +4473,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -4847,7 +4483,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -4857,7 +4493,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -4867,7 +4503,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -4877,7 +4513,7 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -4887,57 +4523,9 @@ }, "hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U41"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U105":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U107":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U109":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U111":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U113":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U115":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U117":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U121":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U123":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U125":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_filter_pw_global_wrapper_stencil$chain_en_const_U127":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4945,7 +4533,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -4955,7 +4543,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U78"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[11],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -4965,7 +4553,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U79"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[18],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -4975,7 +4563,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U106"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U69"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -4985,7 +4573,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -4995,7 +4583,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U71"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[16],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -5005,7 +4593,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U72"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -5015,7 +4603,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U73"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -5025,7 +4613,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[2],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -5035,7 +4623,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[3],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[17],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[3],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -5045,7 +4633,7 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U76"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[3],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -5055,313 +4643,285 @@ }, "hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U77"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"sram2tb_0":{"cycle_starting_addr":[10],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[1],"read_data_stride":[0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "hw_input_global_wrapper_stencil$chain_en_const_U129":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U131":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U133":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U135":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U137":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U139":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U141":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$d_reg__U142$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U100$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U143$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U101$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U144$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U102$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U145$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U103$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U146$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U104$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U147$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U105$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U148$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U106$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U149$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U107$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U150$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U108$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U151$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U109$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U152$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U110$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U153$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U111$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U154$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U112$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U155$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U113$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U156$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U114$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U157$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U115$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U158$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U116$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U159$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U117$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U160$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U118$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U161$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U119$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U162$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U120$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U163$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U121$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U164$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U122$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U165$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U123$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U166$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U124$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U167$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U125$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U168$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U126$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U169$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U127$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U170$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U128$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U171$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U129$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U172$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U130$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U173$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U131$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U174$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U132$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U175$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U133$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U176$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U134$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U177$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U135$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U178$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U136$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U179$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U137$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U180$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U138$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U181$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U139$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U182$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U140$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U183$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U141$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U184$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U142$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U185$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U87$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U186$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U88$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U187$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U89$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U188$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U90$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U189$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U91$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U190$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U92$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U191$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U93$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U192$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U94$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U193$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U95$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U194$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U96$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U195$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U97$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U196$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U98$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "hw_input_global_wrapper_stencil$d_reg__U197$reg0":{ + "hw_input_global_wrapper_stencil$d_reg__U99$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -5373,7 +4933,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U80"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -5383,7 +4943,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U81"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -5393,7 +4953,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U82"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -5403,7 +4963,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U83"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -5413,7 +4973,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[70],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -5423,7 +4983,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U85"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -5433,7 +4993,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U86"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[36],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[102],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[69],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[104],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[72],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_clkwrk_10_op_hcompute_hw_output_stencil_2_write_0":{ @@ -5454,25 +5014,25 @@ "modargs":{"mode":["String","out"]}, "metadata":{"in2glb_0":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,30]}} }, - "io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0":{ + "io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3]}} }, - "io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0":{ + "io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3]}} }, - "io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0":{ + "io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3]}} }, - "io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0":{ + "io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, @@ -5484,25 +5044,25 @@ "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4],"dimensionality":2,"extent":[3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3]}} }, - "io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read_0":{ + "io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[1024],"read_data_starting_addr":[0],"read_data_stride":[1]}} }, - "io16in_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read_0":{ + "io16in_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[1024],"read_data_starting_addr":[0],"read_data_stride":[1]}} }, - "io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_0":{ + "io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[1024],"read_data_starting_addr":[0],"read_data_stride":[1]}} }, - "io16in_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read_0":{ + "io16in_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, @@ -5911,7 +5471,7 @@ }, "op_hcompute_hw_output_stencil_1_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const_lutcnst":{ @@ -5921,7 +5481,7 @@ }, "op_hcompute_hw_output_stencil_2_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -5931,7 +5491,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_pw_conv_reduction_stencil$inner_compute$const_p0__1060":{ @@ -6069,122 +5629,122 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U198$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U143$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U199$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U144$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U200$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U145$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U201$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U146$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U202$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U147$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U203$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U148$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U204$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U149$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U205$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U150$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U206$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U151$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U207$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U152$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U208$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U153$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U209$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U154$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U210$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U155$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U211$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U156$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U212$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U157$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U213$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U158$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U214$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U159$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U215$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U160$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U216$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U161$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U217$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U162$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U218$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U163$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U219$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U164$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U220$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U165$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U221$reg0":{ + "pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U166$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -6228,147 +5788,147 @@ ["op_hcompute_dw_conv_stencil_1$inner_compute$const_p0__742.out","dw_conv_stencil_clkwrk_dsa11$d_reg__U8$reg0.in"], ["dw_conv_stencil_clkwrk_dsa11$d_reg__U9$reg0.in","dw_conv_stencil_clkwrk_dsa11$d_reg__U8$reg0.out"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_768$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_0_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_848$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_10_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_851$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_11_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_846$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_12_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_849$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_13_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_18_hw_input_global_wrapper_stencil_18_853$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_14_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_847$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_15_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_850$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_16_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_17_hw_input_global_wrapper_stencil_17_852$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_17_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_19_922$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_18_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_22_hw_input_global_wrapper_stencil_22_925$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_19_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_771$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_1_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_928$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_20_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_20_923$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_21_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_23_hw_input_global_wrapper_stencil_23_926$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_22_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_930$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_23_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_21_hw_input_global_wrapper_stencil_21_924$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_24_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_24_hw_input_global_wrapper_stencil_24_927$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_25_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_929$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_26_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_999$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_27_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_1002$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_28_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_1005$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_29_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_774$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_2_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_1000$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_30_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_1003$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_31_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_1007$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_32_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_1001$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_33_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_1004$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_34_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_2_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_1006$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_35_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_769$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_3_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_772$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_4_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_776$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_5_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_770$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_6_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_773$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_7_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_3_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_775$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_8_garnet.flush"], ["hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_garnet.clk_en","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_filter_dw_stencil_clkwrk_0_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_garnet.data_in_0"], + ["io16in_hw_filter_dw_stencil_clkwrk_1_op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_0.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_845$binop.data.in.0","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_garnet.data_out_0"], ["io1in_reset.out","hw_filter_dw_global_wrapper_stencil$ub_hw_filter_dw_global_wrapper_stencil_BANK_9_garnet.flush"], ["hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], @@ -6419,116 +5979,116 @@ ["io16in_hw_filter_pw_stencil_op_hcompute_hw_filter_pw_global_wrapper_stencil_read_0.out","hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_9_garnet.data_in_0"], ["op_hcompute_pw_conv_reduction_stencil_5$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_10_dw_conv_stencil_14_1143$binop.data.in.0","hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_9_garnet.data_out_0"], ["io1in_reset.out","hw_filter_pw_global_wrapper_stencil$ub_hw_filter_pw_global_wrapper_stencil_BANK_9_garnet.flush"], - ["io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U142$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U143$reg0.in","hw_input_global_wrapper_stencil$d_reg__U142$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U144$reg0.in","hw_input_global_wrapper_stencil$d_reg__U143$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U145$reg0.in","hw_input_global_wrapper_stencil$d_reg__U144$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U146$reg0.in","hw_input_global_wrapper_stencil$d_reg__U145$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U147$reg0.in","hw_input_global_wrapper_stencil$d_reg__U146$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U148$reg0.in","hw_input_global_wrapper_stencil$d_reg__U147$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U149$reg0.in","hw_input_global_wrapper_stencil$d_reg__U148$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U192$reg0.in","hw_input_global_wrapper_stencil$d_reg__U149$reg0.out"], - ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_775$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U149$reg0.out"], - ["io16in_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read_0.out","hw_input_global_wrapper_stencil$d_reg__U150$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U151$reg0.in","hw_input_global_wrapper_stencil$d_reg__U150$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U152$reg0.in","hw_input_global_wrapper_stencil$d_reg__U151$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U153$reg0.in","hw_input_global_wrapper_stencil$d_reg__U152$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U154$reg0.in","hw_input_global_wrapper_stencil$d_reg__U153$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U155$reg0.in","hw_input_global_wrapper_stencil$d_reg__U154$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U156$reg0.in","hw_input_global_wrapper_stencil$d_reg__U155$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U157$reg0.in","hw_input_global_wrapper_stencil$d_reg__U156$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U174$reg0.in","hw_input_global_wrapper_stencil$d_reg__U157$reg0.out"], - ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_17_hw_input_global_wrapper_stencil_17_852$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U157$reg0.out"], - ["io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out","hw_input_global_wrapper_stencil$d_reg__U158$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U159$reg0.in","hw_input_global_wrapper_stencil$d_reg__U158$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U160$reg0.in","hw_input_global_wrapper_stencil$d_reg__U159$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U161$reg0.in","hw_input_global_wrapper_stencil$d_reg__U160$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U162$reg0.in","hw_input_global_wrapper_stencil$d_reg__U161$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U163$reg0.in","hw_input_global_wrapper_stencil$d_reg__U162$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U164$reg0.in","hw_input_global_wrapper_stencil$d_reg__U163$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U165$reg0.in","hw_input_global_wrapper_stencil$d_reg__U164$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U180$reg0.in","hw_input_global_wrapper_stencil$d_reg__U165$reg0.out"], - ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_929$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U165$reg0.out"], - ["io16in_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read_0.out","hw_input_global_wrapper_stencil$d_reg__U166$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U167$reg0.in","hw_input_global_wrapper_stencil$d_reg__U166$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U168$reg0.in","hw_input_global_wrapper_stencil$d_reg__U167$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U169$reg0.in","hw_input_global_wrapper_stencil$d_reg__U168$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U170$reg0.in","hw_input_global_wrapper_stencil$d_reg__U169$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U171$reg0.in","hw_input_global_wrapper_stencil$d_reg__U170$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U172$reg0.in","hw_input_global_wrapper_stencil$d_reg__U171$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U173$reg0.in","hw_input_global_wrapper_stencil$d_reg__U172$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U186$reg0.in","hw_input_global_wrapper_stencil$d_reg__U173$reg0.out"], - ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_1006$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U173$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U175$reg0.in","hw_input_global_wrapper_stencil$d_reg__U174$reg0.out"], - ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_18_hw_input_global_wrapper_stencil_18_853$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U174$reg0.out"], - ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_851$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U175$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U176$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U177$reg0.in","hw_input_global_wrapper_stencil$d_reg__U176$reg0.out"], - ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_849$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U176$reg0.out"], - ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_848$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U177$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U178$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U179$reg0.in","hw_input_global_wrapper_stencil$d_reg__U178$reg0.out"], - ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_846$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U178$reg0.out"], - ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_845$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U179$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U181$reg0.in","hw_input_global_wrapper_stencil$d_reg__U180$reg0.out"], - ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_930$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U180$reg0.out"], - ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_928$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U181$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U182$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U183$reg0.in","hw_input_global_wrapper_stencil$d_reg__U182$reg0.out"], - ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_23_hw_input_global_wrapper_stencil_23_926$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U182$reg0.out"], - ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_22_hw_input_global_wrapper_stencil_22_925$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U183$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U184$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U185$reg0.in","hw_input_global_wrapper_stencil$d_reg__U184$reg0.out"], - ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_20_923$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U184$reg0.out"], - ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_19_922$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U185$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U187$reg0.in","hw_input_global_wrapper_stencil$d_reg__U186$reg0.out"], - ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_1007$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U186$reg0.out"], - ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_1005$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U187$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U188$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U189$reg0.in","hw_input_global_wrapper_stencil$d_reg__U188$reg0.out"], - ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_1003$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U188$reg0.out"], - ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_1002$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U189$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U190$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U191$reg0.in","hw_input_global_wrapper_stencil$d_reg__U190$reg0.out"], - ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_1000$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U190$reg0.out"], - ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_999$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U191$reg0.out"], - ["hw_input_global_wrapper_stencil$d_reg__U193$reg0.in","hw_input_global_wrapper_stencil$d_reg__U192$reg0.out"], - ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_776$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U192$reg0.out"], - ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_774$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U193$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U194$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U195$reg0.in","hw_input_global_wrapper_stencil$d_reg__U194$reg0.out"], - ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_772$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U194$reg0.out"], - ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_771$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U195$reg0.out"], - ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U196$reg0.in"], - ["hw_input_global_wrapper_stencil$d_reg__U197$reg0.in","hw_input_global_wrapper_stencil$d_reg__U196$reg0.out"], - ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_769$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U196$reg0.out"], - ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_768$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U197$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U99$reg0.out","hw_input_global_wrapper_stencil$d_reg__U100$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U101$reg0.in","hw_input_global_wrapper_stencil$d_reg__U100$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U102$reg0.in","hw_input_global_wrapper_stencil$d_reg__U101$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U119$reg0.in","hw_input_global_wrapper_stencil$d_reg__U102$reg0.out"], + ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_17_hw_input_global_wrapper_stencil_17_852$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U102$reg0.out"], + ["io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out","hw_input_global_wrapper_stencil$d_reg__U103$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U104$reg0.in","hw_input_global_wrapper_stencil$d_reg__U103$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U105$reg0.in","hw_input_global_wrapper_stencil$d_reg__U104$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U106$reg0.in","hw_input_global_wrapper_stencil$d_reg__U105$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U107$reg0.in","hw_input_global_wrapper_stencil$d_reg__U106$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U108$reg0.in","hw_input_global_wrapper_stencil$d_reg__U107$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U109$reg0.in","hw_input_global_wrapper_stencil$d_reg__U108$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U110$reg0.in","hw_input_global_wrapper_stencil$d_reg__U109$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U125$reg0.in","hw_input_global_wrapper_stencil$d_reg__U110$reg0.out"], + ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_929$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U110$reg0.out"], + ["io16in_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read_0.out","hw_input_global_wrapper_stencil$d_reg__U111$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U112$reg0.in","hw_input_global_wrapper_stencil$d_reg__U111$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U113$reg0.in","hw_input_global_wrapper_stencil$d_reg__U112$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U114$reg0.in","hw_input_global_wrapper_stencil$d_reg__U113$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U115$reg0.in","hw_input_global_wrapper_stencil$d_reg__U114$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U116$reg0.in","hw_input_global_wrapper_stencil$d_reg__U115$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U117$reg0.in","hw_input_global_wrapper_stencil$d_reg__U116$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U118$reg0.in","hw_input_global_wrapper_stencil$d_reg__U117$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U131$reg0.in","hw_input_global_wrapper_stencil$d_reg__U118$reg0.out"], + ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_1006$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U118$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U120$reg0.in","hw_input_global_wrapper_stencil$d_reg__U119$reg0.out"], + ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_18_hw_input_global_wrapper_stencil_18_853$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U119$reg0.out"], + ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_851$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U120$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_1","hw_input_global_wrapper_stencil$d_reg__U121$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U122$reg0.in","hw_input_global_wrapper_stencil$d_reg__U121$reg0.out"], + ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_849$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U121$reg0.out"], + ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_848$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U122$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U123$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U124$reg0.in","hw_input_global_wrapper_stencil$d_reg__U123$reg0.out"], + ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_846$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U123$reg0.out"], + ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_845$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U124$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U126$reg0.in","hw_input_global_wrapper_stencil$d_reg__U125$reg0.out"], + ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_930$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U125$reg0.out"], + ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_928$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U126$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U127$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U128$reg0.in","hw_input_global_wrapper_stencil$d_reg__U127$reg0.out"], + ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_23_hw_input_global_wrapper_stencil_23_926$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U127$reg0.out"], + ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_22_hw_input_global_wrapper_stencil_22_925$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U128$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U129$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U130$reg0.in","hw_input_global_wrapper_stencil$d_reg__U129$reg0.out"], + ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_20_hw_input_global_wrapper_stencil_20_923$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U129$reg0.out"], + ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_19_hw_input_global_wrapper_stencil_19_922$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U130$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U132$reg0.in","hw_input_global_wrapper_stencil$d_reg__U131$reg0.out"], + ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_1007$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U131$reg0.out"], + ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_1005$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U132$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U133$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U134$reg0.in","hw_input_global_wrapper_stencil$d_reg__U133$reg0.out"], + ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_1003$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U133$reg0.out"], + ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_1002$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U134$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U135$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U136$reg0.in","hw_input_global_wrapper_stencil$d_reg__U135$reg0.out"], + ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_1000$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U135$reg0.out"], + ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_999$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U136$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U94$reg0.out","hw_input_global_wrapper_stencil$d_reg__U137$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U138$reg0.in","hw_input_global_wrapper_stencil$d_reg__U137$reg0.out"], + ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_776$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U137$reg0.out"], + ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_774$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U138$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U139$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U140$reg0.in","hw_input_global_wrapper_stencil$d_reg__U139$reg0.out"], + ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_772$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U139$reg0.out"], + ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_771$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U140$reg0.out"], + ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet.data_out_0","hw_input_global_wrapper_stencil$d_reg__U141$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U142$reg0.in","hw_input_global_wrapper_stencil$d_reg__U141$reg0.out"], + ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_769$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U141$reg0.out"], + ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_768$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U142$reg0.out"], + ["io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$d_reg__U87$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U88$reg0.in","hw_input_global_wrapper_stencil$d_reg__U87$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U89$reg0.in","hw_input_global_wrapper_stencil$d_reg__U88$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U90$reg0.in","hw_input_global_wrapper_stencil$d_reg__U89$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U91$reg0.in","hw_input_global_wrapper_stencil$d_reg__U90$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U92$reg0.in","hw_input_global_wrapper_stencil$d_reg__U91$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U93$reg0.in","hw_input_global_wrapper_stencil$d_reg__U92$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U94$reg0.in","hw_input_global_wrapper_stencil$d_reg__U93$reg0.out"], + ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_775$binop.data.in.1","hw_input_global_wrapper_stencil$d_reg__U94$reg0.out"], + ["io16in_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read_0.out","hw_input_global_wrapper_stencil$d_reg__U95$reg0.in"], + ["hw_input_global_wrapper_stencil$d_reg__U96$reg0.in","hw_input_global_wrapper_stencil$d_reg__U95$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U97$reg0.in","hw_input_global_wrapper_stencil$d_reg__U96$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U98$reg0.in","hw_input_global_wrapper_stencil$d_reg__U97$reg0.out"], + ["hw_input_global_wrapper_stencil$d_reg__U99$reg0.in","hw_input_global_wrapper_stencil$d_reg__U98$reg0.out"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_in_0"], + ["io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_24_hw_input_global_wrapper_stencil_24_927$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet.flush"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet.data_in_0"], + ["io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_6$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_21_hw_input_global_wrapper_stencil_21_924$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet.flush"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_in_0"], + ["io16in_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_1004$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.flush"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_3_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet.data_in_0"], + ["io16in_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_3_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_7$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_1001$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet.flush"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet.data_in_0"], + ["io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_773$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet.flush"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet.data_in_0"], + ["io16in_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_4$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_770$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet.flush"], ["hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.clk_en","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], - ["io16in_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_1_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_in_0"], + ["io16in_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_1_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_in_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_847$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_0"], ["op_hcompute_dw_conv_stencil_5$inner_compute$mul_hw_filter_dw_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_850$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.data_out_1"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet.flush"], @@ -6624,9 +6184,9 @@ ["op_hcompute_hw_output_stencil_1_port_controller_garnet.clk_en","op_hcompute_hw_output_stencil_1_port_controller_clk_en_const_lutcnst.bit.out"], ["op_hcompute_hw_output_stencil_2_port_controller_garnet.clk_en","op_hcompute_hw_output_stencil_2_port_controller_clk_en_const_lutcnst.bit.out"], ["op_hcompute_hw_output_stencil_port_controller_garnet.clk_en","op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst.bit.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U198$reg0.in","op_hcompute_pw_conv_reduction_stencil$inner_compute$const_p0__1060.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U206$reg0.in","op_hcompute_pw_conv_reduction_stencil_1$inner_compute$const_p0__1063.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U214$reg0.in","op_hcompute_pw_conv_reduction_stencil_2$inner_compute$const_p0__1066.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U143$reg0.in","op_hcompute_pw_conv_reduction_stencil$inner_compute$const_p0__1060.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U151$reg0.in","op_hcompute_pw_conv_reduction_stencil_1$inner_compute$const_p0__1063.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U159$reg0.in","op_hcompute_pw_conv_reduction_stencil_2$inner_compute$const_p0__1066.out"], ["op_hcompute_pw_conv_reduction_stencil_3$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_1_dw_conv_stencil_5_1076$binop.data.out","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_1076_1082_1083$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_pw_conv_reduction_stencil_1_1081_1082$binop.data.out","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_1076_1082_1083$binop.data.in.1"], ["op_hcompute_pw_conv_reduction_stencil_3$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_2_dw_conv_stencil_6_1077$binop.data.out","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_1077_1080_1081$binop.data.in.0"], @@ -6634,7 +6194,7 @@ ["op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_pw_conv_reduction_stencil_1_1081_1082$binop.data.in.1","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_1077_1080_1081$binop.data.out"], ["op_hcompute_pw_conv_reduction_stencil_3$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_3_dw_conv_stencil_7_1078$binop.data.out","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_1078_1079_1080$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_3$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_4_dw_conv_stencil_8_1079$binop.data.out","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_1078_1079_1080$binop.data.in.1"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U205$reg0.out","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_pw_conv_reduction_stencil_1_1081_1082$binop.data.in.0"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U150$reg0.out","op_hcompute_pw_conv_reduction_stencil_3$inner_compute$add_pw_conv_reduction_stencil_1_1081_1082$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_4$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_5_dw_conv_stencil_9_1109$binop.data.out","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_1109_1115_1116$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_pw_conv_reduction_stencil_2_1114_1115$binop.data.out","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_1109_1115_1116$binop.data.in.1"], ["op_hcompute_pw_conv_reduction_stencil_4$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_6_dw_conv_stencil_10_1110$binop.data.out","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_1110_1113_1114$binop.data.in.0"], @@ -6642,7 +6202,7 @@ ["op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_pw_conv_reduction_stencil_2_1114_1115$binop.data.in.1","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_1110_1113_1114$binop.data.out"], ["op_hcompute_pw_conv_reduction_stencil_4$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_7_dw_conv_stencil_11_1111$binop.data.out","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_1111_1112_1113$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_4$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_8_dw_conv_stencil_12_1112$binop.data.out","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_1111_1112_1113$binop.data.in.1"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U213$reg0.out","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_pw_conv_reduction_stencil_2_1114_1115$binop.data.in.0"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U158$reg0.out","op_hcompute_pw_conv_reduction_stencil_4$inner_compute$add_pw_conv_reduction_stencil_2_1114_1115$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_5$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_9_dw_conv_stencil_13_1142$binop.data.out","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_1142_1148_1149$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_pw_conv_reduction_stencil_3_1147_1148$binop.data.out","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_1142_1148_1149$binop.data.in.1"], ["op_hcompute_pw_conv_reduction_stencil_5$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_10_dw_conv_stencil_14_1143$binop.data.out","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_1143_1146_1147$binop.data.in.0"], @@ -6650,31 +6210,31 @@ ["op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_pw_conv_reduction_stencil_3_1147_1148$binop.data.in.1","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_1143_1146_1147$binop.data.out"], ["op_hcompute_pw_conv_reduction_stencil_5$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_11_dw_conv_stencil_15_1144$binop.data.out","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_1144_1145_1146$binop.data.in.0"], ["op_hcompute_pw_conv_reduction_stencil_5$inner_compute$mul_hw_filter_pw_global_wrapper_stencil_12_dw_conv_stencil_16_1145$binop.data.out","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_1144_1145_1146$binop.data.in.1"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U221$reg0.out","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_pw_conv_reduction_stencil_3_1147_1148$binop.data.in.0"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U199$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U198$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U200$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U199$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U201$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U200$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U202$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U201$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U203$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U202$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U204$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U203$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U205$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U204$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U207$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U206$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U208$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U207$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U209$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U208$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U210$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U209$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U211$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U210$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U212$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U211$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U213$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U212$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U215$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U214$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U216$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U215$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U217$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U216$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U218$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U217$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U219$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U218$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U220$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U219$reg0.out"], - ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U221$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U220$reg0.out"] + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U166$reg0.out","op_hcompute_pw_conv_reduction_stencil_5$inner_compute$add_pw_conv_reduction_stencil_3_1147_1148$binop.data.in.0"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U144$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U143$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U145$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U144$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U146$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U145$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U147$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U146$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U148$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U147$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U149$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U148$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U150$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U149$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U152$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U151$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U153$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U152$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U154$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U153$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U155$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U154$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U156$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U155$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U157$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U156$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U158$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U157$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U160$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U159$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U161$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U160$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U162$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U161$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U163$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U162$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U164$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U163$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U165$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U164$reg0.out"], + ["pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U166$reg0.in","pw_conv_reduction_stencil_clkwrk_dsa12$d_reg__U165$reg0.out"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start_pt__U271":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_exe_start_pt__U216":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6683,7 +6243,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start_pt__U270":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_read_start_pt__U215":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6692,7 +6252,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start_pt__U272":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_1_write_start_pt__U217":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6701,7 +6261,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start_pt__U266":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_exe_start_pt__U211":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6710,7 +6270,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start_pt__U265":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_read_start_pt__U210":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6719,7 +6279,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start_pt__U267":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_2_write_start_pt__U212":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6728,7 +6288,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start_pt__U261":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_exe_start_pt__U206":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6737,7 +6297,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start_pt__U260":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_read_start_pt__U205":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6746,7 +6306,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start_pt__U262":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_3_write_start_pt__U207":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6755,7 +6315,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start_pt__U276":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_exe_start_pt__U221":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6764,7 +6324,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start_pt__U275":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_read_start_pt__U220":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6773,7 +6333,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start_pt__U277":{ + "op_hcompute_hw_filter_dw_global_wrapper_stencil_write_start_pt__U222":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6782,7 +6342,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start_pt__U236":{ + "op_hcompute_hw_filter_pw_global_wrapper_stencil_exe_start_pt__U181":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6791,7 +6351,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start_pt__U235":{ + "op_hcompute_hw_filter_pw_global_wrapper_stencil_read_start_pt__U180":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6800,7 +6360,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start_pt__U237":{ + "op_hcompute_hw_filter_pw_global_wrapper_stencil_write_start_pt__U182":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6809,7 +6369,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U251":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U196":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6818,7 +6378,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U250":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U195":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6827,7 +6387,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U252":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U197":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6836,7 +6396,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U246":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U191":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6845,7 +6405,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U245":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U190":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6854,7 +6414,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U247":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U192":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6863,7 +6423,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U241":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U186":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6872,7 +6432,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U240":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U185":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6881,7 +6441,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U242":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U187":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6890,7 +6450,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U256":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U201":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6899,7 +6459,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U255":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U200":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6908,7 +6468,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U257":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U202":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6917,7 +6477,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U228":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U173":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6926,7 +6486,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U227":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U172":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6935,7 +6495,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U229":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U174":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6944,7 +6504,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U224":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U169":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6953,7 +6513,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U223":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U168":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6962,7 +6522,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U225":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U170":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6971,7 +6531,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U232":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U177":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6980,7 +6540,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U231":{ + "op_hcompute_hw_output_stencil_read_start_pt__U176":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6989,7 +6549,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U233":{ + "op_hcompute_hw_output_stencil_write_start_pt__U178":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -7017,179 +6577,179 @@ ["op_hcompute_pw_conv_reduction_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "d_reg__U198$reg0":{ + "d_reg__U143$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U199$reg0":{ + "d_reg__U144$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U200$reg0":{ + "d_reg__U145$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U201$reg0":{ + "d_reg__U146$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U202$reg0":{ + "d_reg__U147$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U203$reg0":{ + "d_reg__U148$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U204$reg0":{ + "d_reg__U149$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U205$reg0":{ + "d_reg__U150$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U206$reg0":{ + "d_reg__U151$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U207$reg0":{ + "d_reg__U152$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U208$reg0":{ + "d_reg__U153$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U209$reg0":{ + "d_reg__U154$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U210$reg0":{ + "d_reg__U155$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U211$reg0":{ + "d_reg__U156$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U212$reg0":{ + "d_reg__U157$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U213$reg0":{ + "d_reg__U158$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U214$reg0":{ + "d_reg__U159$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U215$reg0":{ + "d_reg__U160$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U216$reg0":{ + "d_reg__U161$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U217$reg0":{ + "d_reg__U162$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U218$reg0":{ + "d_reg__U163$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U219$reg0":{ + "d_reg__U164$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U220$reg0":{ + "d_reg__U165$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U221$reg0":{ + "d_reg__U166$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","d_reg__U198$reg0.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_write.0","d_reg__U198$reg0.in"], - ["d_reg__U199$reg0.in","d_reg__U198$reg0.out"], - ["self.clk","d_reg__U199$reg0.clk"], - ["d_reg__U200$reg0.in","d_reg__U199$reg0.out"], - ["self.clk","d_reg__U200$reg0.clk"], - ["d_reg__U201$reg0.in","d_reg__U200$reg0.out"], - ["self.clk","d_reg__U201$reg0.clk"], - ["d_reg__U202$reg0.in","d_reg__U201$reg0.out"], - ["self.clk","d_reg__U202$reg0.clk"], - ["d_reg__U203$reg0.in","d_reg__U202$reg0.out"], - ["self.clk","d_reg__U203$reg0.clk"], - ["d_reg__U204$reg0.in","d_reg__U203$reg0.out"], - ["self.clk","d_reg__U204$reg0.clk"], - ["d_reg__U205$reg0.in","d_reg__U204$reg0.out"], - ["self.clk","d_reg__U205$reg0.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_3_read.0","d_reg__U205$reg0.out"], - ["self.clk","d_reg__U206$reg0.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_1_write.0","d_reg__U206$reg0.in"], - ["d_reg__U207$reg0.in","d_reg__U206$reg0.out"], - ["self.clk","d_reg__U207$reg0.clk"], - ["d_reg__U208$reg0.in","d_reg__U207$reg0.out"], - ["self.clk","d_reg__U208$reg0.clk"], - ["d_reg__U209$reg0.in","d_reg__U208$reg0.out"], - ["self.clk","d_reg__U209$reg0.clk"], - ["d_reg__U210$reg0.in","d_reg__U209$reg0.out"], - ["self.clk","d_reg__U210$reg0.clk"], - ["d_reg__U211$reg0.in","d_reg__U210$reg0.out"], - ["self.clk","d_reg__U211$reg0.clk"], - ["d_reg__U212$reg0.in","d_reg__U211$reg0.out"], - ["self.clk","d_reg__U212$reg0.clk"], - ["d_reg__U213$reg0.in","d_reg__U212$reg0.out"], - ["self.clk","d_reg__U213$reg0.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_4_read.0","d_reg__U213$reg0.out"], - ["self.clk","d_reg__U214$reg0.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_2_write.0","d_reg__U214$reg0.in"], - ["d_reg__U215$reg0.in","d_reg__U214$reg0.out"], - ["self.clk","d_reg__U215$reg0.clk"], - ["d_reg__U216$reg0.in","d_reg__U215$reg0.out"], - ["self.clk","d_reg__U216$reg0.clk"], - ["d_reg__U217$reg0.in","d_reg__U216$reg0.out"], - ["self.clk","d_reg__U217$reg0.clk"], - ["d_reg__U218$reg0.in","d_reg__U217$reg0.out"], - ["self.clk","d_reg__U218$reg0.clk"], - ["d_reg__U219$reg0.in","d_reg__U218$reg0.out"], - ["self.clk","d_reg__U219$reg0.clk"], - ["d_reg__U220$reg0.in","d_reg__U219$reg0.out"], - ["self.clk","d_reg__U220$reg0.clk"], - ["d_reg__U221$reg0.in","d_reg__U220$reg0.out"], - ["self.clk","d_reg__U221$reg0.clk"], - ["self.op_hcompute_pw_conv_reduction_stencil_5_read.0","d_reg__U221$reg0.out"] + ["self.clk","d_reg__U143$reg0.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_write.0","d_reg__U143$reg0.in"], + ["d_reg__U144$reg0.in","d_reg__U143$reg0.out"], + ["self.clk","d_reg__U144$reg0.clk"], + ["d_reg__U145$reg0.in","d_reg__U144$reg0.out"], + ["self.clk","d_reg__U145$reg0.clk"], + ["d_reg__U146$reg0.in","d_reg__U145$reg0.out"], + ["self.clk","d_reg__U146$reg0.clk"], + ["d_reg__U147$reg0.in","d_reg__U146$reg0.out"], + ["self.clk","d_reg__U147$reg0.clk"], + ["d_reg__U148$reg0.in","d_reg__U147$reg0.out"], + ["self.clk","d_reg__U148$reg0.clk"], + ["d_reg__U149$reg0.in","d_reg__U148$reg0.out"], + ["self.clk","d_reg__U149$reg0.clk"], + ["d_reg__U150$reg0.in","d_reg__U149$reg0.out"], + ["self.clk","d_reg__U150$reg0.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_3_read.0","d_reg__U150$reg0.out"], + ["self.clk","d_reg__U151$reg0.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_1_write.0","d_reg__U151$reg0.in"], + ["d_reg__U152$reg0.in","d_reg__U151$reg0.out"], + ["self.clk","d_reg__U152$reg0.clk"], + ["d_reg__U153$reg0.in","d_reg__U152$reg0.out"], + ["self.clk","d_reg__U153$reg0.clk"], + ["d_reg__U154$reg0.in","d_reg__U153$reg0.out"], + ["self.clk","d_reg__U154$reg0.clk"], + ["d_reg__U155$reg0.in","d_reg__U154$reg0.out"], + ["self.clk","d_reg__U155$reg0.clk"], + ["d_reg__U156$reg0.in","d_reg__U155$reg0.out"], + ["self.clk","d_reg__U156$reg0.clk"], + ["d_reg__U157$reg0.in","d_reg__U156$reg0.out"], + ["self.clk","d_reg__U157$reg0.clk"], + ["d_reg__U158$reg0.in","d_reg__U157$reg0.out"], + ["self.clk","d_reg__U158$reg0.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_4_read.0","d_reg__U158$reg0.out"], + ["self.clk","d_reg__U159$reg0.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_2_write.0","d_reg__U159$reg0.in"], + ["d_reg__U160$reg0.in","d_reg__U159$reg0.out"], + ["self.clk","d_reg__U160$reg0.clk"], + ["d_reg__U161$reg0.in","d_reg__U160$reg0.out"], + ["self.clk","d_reg__U161$reg0.clk"], + ["d_reg__U162$reg0.in","d_reg__U161$reg0.out"], + ["self.clk","d_reg__U162$reg0.clk"], + ["d_reg__U163$reg0.in","d_reg__U162$reg0.out"], + ["self.clk","d_reg__U163$reg0.clk"], + ["d_reg__U164$reg0.in","d_reg__U163$reg0.out"], + ["self.clk","d_reg__U164$reg0.clk"], + ["d_reg__U165$reg0.in","d_reg__U164$reg0.out"], + ["self.clk","d_reg__U165$reg0.clk"], + ["d_reg__U166$reg0.in","d_reg__U165$reg0.out"], + ["self.clk","d_reg__U166$reg0.clk"], + ["self.op_hcompute_pw_conv_reduction_stencil_5_read.0","d_reg__U166$reg0.out"] ] }, "pw_conv_reduction_stencil_ub":{ diff --git a/aha_garnet_design_new/nlmeans_simple_trunc/nlmeans_simple_trunc.json b/aha_garnet_design_new/nlmeans_simple_trunc/nlmeans_simple_trunc.json new file mode 100644 index 000000000..299f343ba --- /dev/null +++ b/aha_garnet_design_new/nlmeans_simple_trunc/nlmeans_simple_trunc.json @@ -0,0 +1,1126 @@ +{"top":"global.nlmeans_simple_trunc", +"namespaces":{ + "global":{ + "modules":{ + "cu_op_hcompute_d_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["d_stencil_clkwrk_dsa3_op_hcompute_d_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_d_stencil" + } + }, + "connections":[ + ["self.d_stencil_clkwrk_dsa3_op_hcompute_d_stencil_write.0","inner_compute.out_d_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_d_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["d_stencil_clkwrk_dsa3_op_hcompute_d_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read",["Array",6,["Array",16,"BitIn"]]], + ["d_stencil_op_hcompute_d_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_d_stencil_1" + } + }, + "connections":[ + ["self.d_stencil_clkwrk_dsa3_op_hcompute_d_stencil_1_read.0","inner_compute.in0_d_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.0","inner_compute.in1_hw_input_global_wrapper_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.1","inner_compute.in1_hw_input_global_wrapper_stencil.1"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.2","inner_compute.in1_hw_input_global_wrapper_stencil.2"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.3","inner_compute.in1_hw_input_global_wrapper_stencil.3"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.4","inner_compute.in1_hw_input_global_wrapper_stencil.4"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.5","inner_compute.in1_hw_input_global_wrapper_stencil.5"], + ["self.d_stencil_op_hcompute_d_stencil_1_write.0","inner_compute.out_d_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_d_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["d_stencil_op_hcompute_d_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["d_stencil_out_op_hcompute_d_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_d_stencil_2" + } + }, + "connections":[ + ["self.d_stencil_op_hcompute_d_stencil_2_read.0","inner_compute.in0_d_stencil.0"], + ["self.d_stencil_out_op_hcompute_d_stencil_2_write.0","inner_compute.out_d_stencil_out"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_input_global_wrapper_stencil" + } + }, + "connections":[ + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_input_global_wrapper_stencil_1" + } + }, + "connections":[ + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_input_global_wrapper_stencil_2" + } + }, + "connections":[ + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "d_stencil_clkwrk_dsa3_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_d_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_d_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_d_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_d_stencil_write_extra_ctrl","BitIn"] + ]], + "connections":[ + ["self.op_hcompute_d_stencil_write.0","self.op_hcompute_d_stencil_1_read.0"] + ] + }, + "d_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_d_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_d_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_d_stencil_2_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_d_stencil_2_read_extra_ctrl","Bit"] + ]], + "connections":[ + ["self.op_hcompute_d_stencil_2_read.0","self.op_hcompute_d_stencil_1_write.0"] + ] + }, + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__760":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_stencil","const_p0__760.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_stencil_1_769_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_2_770_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_3_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_4_blur_d_y_stencil_5_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","add_blur_d_stencil_1_769_770.in0"], + ["add_blur_d_y_stencil_3_768_769.out","add_blur_d_stencil_1_769_770.in1"], + ["add_blur_d_y_stencil_2_770_771.in1","add_blur_d_stencil_1_769_770.out"], + ["self.in1_blur_d_y_stencil.0","add_blur_d_y_stencil_2_770_771.in0"], + ["self.out_blur_d_stencil","add_blur_d_y_stencil_2_770_771.out"], + ["self.in1_blur_d_y_stencil.1","add_blur_d_y_stencil_3_768_769.in0"], + ["add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.out","add_blur_d_y_stencil_3_768_769.in1"], + ["self.in1_blur_d_y_stencil.2","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in0"], + ["self.in1_blur_d_y_stencil.3","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in1"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__731":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","const_p0__731.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_y_stencil_1_741_742":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_2_742_743":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_3_740_741":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_4_d_stencil_5_740":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","add_blur_d_y_stencil_1_741_742.in0"], + ["add_d_stencil_3_740_741.out","add_blur_d_y_stencil_1_741_742.in1"], + ["add_d_stencil_2_742_743.in1","add_blur_d_y_stencil_1_741_742.out"], + ["self.in1_d_stencil.0","add_d_stencil_2_742_743.in0"], + ["self.out_blur_d_y_stencil","add_d_stencil_2_742_743.out"], + ["self.in1_d_stencil.1","add_d_stencil_3_740_741.in0"], + ["add_d_stencil_4_d_stencil_5_740.out","add_d_stencil_3_740_741.in1"], + ["self.in1_d_stencil.2","add_d_stencil_4_d_stencil_5_740.in0"], + ["self.in1_d_stencil.3","add_d_stencil_4_d_stencil_5_740.in1"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__680":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_d_stencil","const_p0__680.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_696_702_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_698_700_701":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_1_701_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_695_695_696":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_697_697_698":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_699_699_700":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_695_695_696.out","add_696_702_703.in0"], + ["add_d_stencil_1_701_702.out","add_696_702_703.in1"], + ["self.out_d_stencil","add_696_702_703.out"], + ["mul_697_697_698.out","add_698_700_701.in0"], + ["mul_699_699_700.out","add_698_700_701.in1"], + ["add_d_stencil_1_701_702.in1","add_698_700_701.out"], + ["self.in0_d_stencil.0","add_d_stencil_1_701_702.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in0"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in1"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in0"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in1"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in0","self.in1_hw_input_global_wrapper_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in1","self.in1_hw_input_global_wrapper_stencil.1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in0","self.in1_hw_input_global_wrapper_stencil.2"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in1","self.in1_hw_input_global_wrapper_stencil.3"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in0","self.in1_hw_input_global_wrapper_stencil.4"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in1","self.in1_hw_input_global_wrapper_stencil.5"] + ] + }, + "hcompute_d_stencil_2":{ + "type":["Record",[ + ["out_d_stencil_out",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_d_stencil_out","self.in0_d_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__882":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__880":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_881_882_883":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_879_880_881":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_881_882_883.in1","const_p0__882.out"], + ["smin_879_880_881.in1","const_p255__880.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in1"], + ["smin_879_880_881.in0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.out"], + ["smax_881_882_883.out","self.out_hw_output_stencil"], + ["smin_879_880_881.out","smax_881_882_883.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__899":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__897":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_898_899_900":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_896_897_898":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_898_899_900.in1","const_p0__899.out"], + ["smin_896_897_898.in1","const_p255__897.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in1"], + ["smin_896_897_898.in0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.out"], + ["smax_898_899_900.out","self.out_hw_output_stencil"], + ["smin_896_897_898.out","smax_898_899_900.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__916":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__914":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_915_916_917":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_913_914_915":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_915_916_917.in1","const_p0__916.out"], + ["smin_913_914_915.in1","const_p255__914.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in1"], + ["smin_913_914_915.in0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.out"], + ["smax_915_916_917.out","self.out_hw_output_stencil"], + ["smin_913_914_915.out","smax_915_916_917.in0"] + ] + }, + "hcompute_non_local_means_div_stencil":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__787":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_div_stencil","const_p0__787.out"] + ] + }, + "hcompute_non_local_means_div_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_div_stencil_1_793_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_2_792_793":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__792":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + } + }, + "connections":[ + ["self.in1_non_local_means_div_stencil.0","add_non_local_means_div_stencil_1_793_794.in0"], + ["ashr_blur_d_stencil_2_792_793.out","add_non_local_means_div_stencil_1_793_794.in1"], + ["self.out_non_local_means_div_stencil","add_non_local_means_div_stencil_1_793_794.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_2_792_793.in0"], + ["const_p4__792.out","ashr_blur_d_stencil_2_792_793.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__803":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__803.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__806":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__806.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__809":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__809.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_1_817_818":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_3_815_816":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__815":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_7_816_817":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_1_817_818.in0"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.out","add_non_local_means_sum_stencil_1_817_818.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_1_817_818.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_3_815_816.in0"], + ["const_p4__815.out","ashr_blur_d_stencil_3_815_816.in1"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.in1","ashr_blur_d_stencil_3_815_816.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_7_816_817.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_2_838_839":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_4_836_837":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__836":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_8_837_838":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_2_838_839.in0"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.out","add_non_local_means_sum_stencil_2_838_839.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_2_838_839.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_4_836_837.in0"], + ["const_p4__836.out","ashr_blur_d_stencil_4_836_837.in1"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.in1","ashr_blur_d_stencil_4_836_837.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_8_837_838.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_3_859_860":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_5_857_858":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__857":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_9_858_859":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_3_859_860.in0"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.out","add_non_local_means_sum_stencil_3_859_860.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_3_859_860.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_5_857_858.in0"], + ["const_p4__857.out","ashr_blur_d_stencil_5_857_858.in1"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.in1","ashr_blur_d_stencil_5_857_858.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_9_858_859.in0"] + ] + }, + "hw_input_global_wrapper_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_d_stencil_1_read",["Array",6,["Array",16,"Bit"]]], + ["op_hcompute_d_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_input_global_wrapper_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_input_global_wrapper_stencil_2_write_extra_ctrl","BitIn"], + ["op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_hw_input_global_wrapper_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2062],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,35],"read_data_starting_addr":[20],"read_data_stride":[1,10],"write_data_starting_addr":[20],"write_data_stride":[1,2]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[82],"read_data_stride":[0,0,1,4,8]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_1":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2092],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_2":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2062],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,35],"read_data_starting_addr":[20],"read_data_stride":[1,10],"write_data_starting_addr":[20],"write_data_stride":[1,2]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[82],"read_data_stride":[0,0,1,4,8]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_3":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2092],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_4":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2062],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,35],"read_data_starting_addr":[20],"read_data_stride":[1,10],"write_data_starting_addr":[20],"write_data_stride":[1,2]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[82],"read_data_stride":[0,0,1,4,8]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_5":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2092],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_d_stencil_1_read.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.data_out_0","self.op_hcompute_d_stencil_1_read.1"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.data_out_0","self.op_hcompute_d_stencil_1_read.2"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.data_out_0","self.op_hcompute_d_stencil_1_read.3"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.data_out_0","self.op_hcompute_d_stencil_1_read.4"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.data_out_0","self.op_hcompute_d_stencil_1_read.5"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_1.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_1.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_2.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_2.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_3.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_3.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_4.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_4.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_5.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_5.rst_n"] + ] + }, + "nlmeans_simple_trunc":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["reset","BitIn"], + ["d_stencil_out_op_hcompute_d_stencil_2_write_valid","Bit"], + ["d_stencil_out_op_hcompute_d_stencil_2_write",["Array",1,["Array",16,"Bit"]]], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "_U14":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U19":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U24":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_stencil":{ + "modref":"global.d_stencil_ub" + }, + "d_stencil_clkwrk_dsa3":{ + "modref":"global.d_stencil_clkwrk_dsa3_ub" + }, + "hw_input_global_wrapper_stencil":{ + "modref":"global.hw_input_global_wrapper_stencil_ub" + }, + "op_hcompute_d_stencil":{ + "modref":"global.cu_op_hcompute_d_stencil" + }, + "op_hcompute_d_stencil_1":{ + "modref":"global.cu_op_hcompute_d_stencil_1" + }, + "op_hcompute_d_stencil_2":{ + "modref":"global.cu_op_hcompute_d_stencil_2" + }, + "op_hcompute_d_stencil_2_exe_start":{ + "modref":"global.op_hcompute_d_stencil_2_exe_start_pt__U8" + }, + "op_hcompute_d_stencil_2_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,640],"dimensionality":4,"extent":[4,4,36,35]}},"mode":"lake"} + }, + "op_hcompute_d_stencil_2_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_d_stencil_2_read_start":{ + "modref":"global.op_hcompute_d_stencil_2_read_start_pt__U7" + }, + "op_hcompute_d_stencil_2_write_start":{ + "modref":"global.op_hcompute_d_stencil_2_write_start_pt__U9" + }, + "op_hcompute_hw_input_global_wrapper_stencil":{ + "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1":{ + "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_1" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U17" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40]}},"mode":"lake"} + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U16" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U18" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2":{ + "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_2" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U12" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40]}},"mode":"lake"} + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U11" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U13" + }, + "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U22" + }, + "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40]}},"mode":"lake"} + }, + "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U21" + }, + "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U23" + } + }, + "connections":[ + ["self.clk","_U14.clk"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","_U14.in"], + ["self.clk","_U19.clk"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","_U19.in"], + ["self.clk","_U24.clk"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U24.in"], + ["self.clk","d_stencil.clk"], + ["op_hcompute_d_stencil_1.d_stencil_op_hcompute_d_stencil_1_write","d_stencil.op_hcompute_d_stencil_1_write"], + ["op_hcompute_d_stencil_2.d_stencil_op_hcompute_d_stencil_2_read","d_stencil.op_hcompute_d_stencil_2_read"], + ["self.reset","d_stencil.reset"], + ["self.clk","d_stencil_clkwrk_dsa3.clk"], + ["op_hcompute_d_stencil_1.d_stencil_clkwrk_dsa3_op_hcompute_d_stencil_1_read","d_stencil_clkwrk_dsa3.op_hcompute_d_stencil_1_read"], + ["op_hcompute_d_stencil.d_stencil_clkwrk_dsa3_op_hcompute_d_stencil_write","d_stencil_clkwrk_dsa3.op_hcompute_d_stencil_write"], + ["self.reset","d_stencil_clkwrk_dsa3.reset"], + ["self.clk","hw_input_global_wrapper_stencil.clk"], + ["op_hcompute_d_stencil_1.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read","hw_input_global_wrapper_stencil.op_hcompute_d_stencil_1_read"], + ["op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write","hw_input_global_wrapper_stencil.op_hcompute_hw_input_global_wrapper_stencil_1_write"], + ["op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write","hw_input_global_wrapper_stencil.op_hcompute_hw_input_global_wrapper_stencil_2_write"], + ["op_hcompute_hw_input_global_wrapper_stencil.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write","hw_input_global_wrapper_stencil.op_hcompute_hw_input_global_wrapper_stencil_write"], + ["self.reset","hw_input_global_wrapper_stencil.reset"], + ["self.clk","op_hcompute_d_stencil.clk"], + ["self.clk","op_hcompute_d_stencil_1.clk"], + ["self.clk","op_hcompute_d_stencil_2.clk"], + ["self.d_stencil_out_op_hcompute_d_stencil_2_write","op_hcompute_d_stencil_2.d_stencil_out_op_hcompute_d_stencil_2_write"], + ["op_hcompute_d_stencil_2_port_controller.stencil_valid","op_hcompute_d_stencil_2_exe_start.in"], + ["self.clk","op_hcompute_d_stencil_2_port_controller.clk"], + ["op_hcompute_d_stencil_2_port_controller_clk_en_const.out","op_hcompute_d_stencil_2_port_controller.clk_en"], + ["self.reset","op_hcompute_d_stencil_2_port_controller.flush"], + ["op_hcompute_d_stencil_2_port_controller_clk_en_const.out","op_hcompute_d_stencil_2_port_controller.rst_n"], + ["op_hcompute_d_stencil_2_read_start.in","op_hcompute_d_stencil_2_port_controller.stencil_valid"], + ["op_hcompute_d_stencil_2_write_start.in","op_hcompute_d_stencil_2_port_controller.stencil_valid"], + ["self.d_stencil_out_op_hcompute_d_stencil_2_write_valid","op_hcompute_d_stencil_2_write_start.out"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil.clk"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read","op_hcompute_hw_input_global_wrapper_stencil.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1.clk"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read","op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_1_exe_start.in"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.clk"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.flush"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.rst_n"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","op_hcompute_hw_input_global_wrapper_stencil_1_read_start.out"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2.clk"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read","op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_2_exe_start.in"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.clk"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.flush"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.rst_n"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","op_hcompute_hw_input_global_wrapper_stencil_2_read_start.out"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_input_global_wrapper_stencil_port_controller.flush"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.rst_n"], + ["op_hcompute_hw_input_global_wrapper_stencil_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"] + ] + }, + "op_hcompute_d_stencil_2_exe_start_pt__U8":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_d_stencil_2_read_start_pt__U7":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_d_stencil_2_write_start_pt__U9":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U17":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U16":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U18":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U12":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U11":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U13":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U22":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U21":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U23":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + } + }, + "generators":{ + "delay_tile":{ + "typegen":"global.delay_tile_TG", + "genparams":{"delay":"Int"} + }, + "raw_dual_port_sram_tile":{ + "typegen":"global.raw_dual_port_sram_TG", + "genparams":{"depth":"Int"} + }, + "raw_quad_port_memtile":{ + "typegen":"global.raw_quad_port_memtile_TG", + "genparams":{"depth":"Int"} + }, + "tahoe":{ + "typegen":"global.tahoe_TG", + "genparams":{"depth":"Int"} + } + }, + "typegens":{ + "delay_tile_TG":[{"delay":"Int"},"implicit"], + "raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"], + "raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"], + "tahoe_TG":[{"depth":"Int"},"implicit"] + } + } +} +} diff --git a/aha_garnet_design_new/resnet/resnet.json b/aha_garnet_design_new/resnet/resnet.json index c2a4e185f..e82a4da79 100644 --- a/aha_garnet_design_new/resnet/resnet.json +++ b/aha_garnet_design_new/resnet/resnet.json @@ -29,22 +29,10 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_conv_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[15262],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[15264],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[15262],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[15264],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake"} }, "ub_conv_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -52,8 +40,8 @@ }, "ub_conv_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16046],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16048],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16046],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16048],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake"} }, "ub_conv_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -61,8 +49,8 @@ }, "ub_conv_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16830],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16832],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16830],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16832],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake"} }, "ub_conv_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -70,9 +58,6 @@ } }, "connections":[ - ["ub_conv_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_conv_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_conv_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], ["ub_conv_stencil_BANK_0.clk","self.clk"], ["ub_conv_stencil_BANK_1.clk","self.clk"], ["ub_conv_stencil_BANK_2.clk","self.clk"], @@ -732,42 +717,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U19":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U21":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -775,8 +728,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -784,8 +737,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -793,8 +746,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -802,8 +755,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -811,8 +764,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U16"} + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -820,8 +773,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U18"} + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -829,8 +782,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U20"} + "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -838,14 +791,6 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_2.chain_chain_en","chain_en_const_U11.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_3.chain_chain_en","chain_en_const_U13.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_4.chain_chain_en","chain_en_const_U15.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_5.chain_chain_en","chain_en_const_U17.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_6.chain_chain_en","chain_en_const_U19.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_7.chain_chain_en","chain_en_const_U21.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U7.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_1.chain_chain_en","chain_en_const_U9.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_1.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_2.clk","self.clk"], @@ -927,106 +872,10 @@ ["op_hcompute_hw_kernel_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U23":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U31":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U43":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U45":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U47":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U53":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U55":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U57":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U61":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U63":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U65":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U67":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U69":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_kernel_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[73],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U22"} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[73],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1034,13 +883,13 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[81],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U24"} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[81],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[84],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U42"} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[84],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -1048,8 +897,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U44"} + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -1057,8 +906,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[77],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U46"} + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[77],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -1066,8 +915,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[85],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U48"} + "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[85],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -1075,8 +924,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U50"} + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -1084,8 +933,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[78],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U52"} + "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[78],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -1093,8 +942,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[86],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U54"} + "genargs":{"ID":["String","_U27"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[86],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -1102,8 +951,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U56"} + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -1111,8 +960,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[79],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U58"} + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[79],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -1120,8 +969,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[87],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U60"} + "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[87],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -1133,13 +982,13 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U26"} + "genargs":{"ID":["String","_U13"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U62"} + "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -1147,8 +996,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[80],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U64"} + "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[80],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -1156,8 +1005,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[88],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U66"} + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[88],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -1165,8 +1014,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U68"} + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -1178,8 +1027,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[74],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U28"} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[74],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -1187,8 +1036,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[82],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U30"} + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[82],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -1196,8 +1045,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U32"} + "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -1205,8 +1054,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[75],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U34"} + "genargs":{"ID":["String","_U17"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[75],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -1214,8 +1063,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[83],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U36"} + "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[83],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -1223,8 +1072,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U38"} + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -1232,8 +1081,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[76],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U40"} + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[76],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -1241,30 +1090,6 @@ } }, "connections":[ - ["ub_hw_kernel_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U23.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_1.chain_chain_en","chain_en_const_U25.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_2.chain_chain_en","chain_en_const_U27.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_3.chain_chain_en","chain_en_const_U29.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_4.chain_chain_en","chain_en_const_U31.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_5.chain_chain_en","chain_en_const_U33.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_6.chain_chain_en","chain_en_const_U35.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_7.chain_chain_en","chain_en_const_U37.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_8.chain_chain_en","chain_en_const_U39.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_9.chain_chain_en","chain_en_const_U41.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_10.chain_chain_en","chain_en_const_U43.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_11.chain_chain_en","chain_en_const_U45.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_12.chain_chain_en","chain_en_const_U47.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_13.chain_chain_en","chain_en_const_U49.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_14.chain_chain_en","chain_en_const_U51.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_15.chain_chain_en","chain_en_const_U53.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_16.chain_chain_en","chain_en_const_U55.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_17.chain_chain_en","chain_en_const_U57.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_18.chain_chain_en","chain_en_const_U59.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_19.chain_chain_en","chain_en_const_U61.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_20.chain_chain_en","chain_en_const_U63.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_21.chain_chain_en","chain_en_const_U65.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_22.chain_chain_en","chain_en_const_U67.out"], - ["ub_hw_kernel_global_wrapper_stencil_BANK_23.chain_chain_en","chain_en_const_U69.out"], ["ub_hw_kernel_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_kernel_global_wrapper_stencil_BANK_1.clk","self.clk"], ["ub_hw_kernel_global_wrapper_stencil_BANK_10.clk","self.clk"], @@ -1411,7 +1236,7 @@ ["ub_hw_kernel_global_wrapper_stencil_BANK_9_clk_en_const.out","ub_hw_kernel_global_wrapper_stencil_BANK_9.rst_n"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U81":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U46":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1420,7 +1245,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U80":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U45":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1429,7 +1254,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U82":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U47":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1438,7 +1263,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U76":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U41":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1447,7 +1272,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U75":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1456,7 +1281,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U77":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1465,7 +1290,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U72":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U37":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1474,7 +1299,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U71":{ + "op_hcompute_hw_output_stencil_read_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1483,7 +1308,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U73":{ + "op_hcompute_hw_output_stencil_write_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1504,12 +1329,12 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U78":{ + "_U43":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U83":{ + "_U48":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -1545,71 +1370,71 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U81" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U46" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U79"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,240],"dimensionality":3,"extent":[8,30,30]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U79"} + "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,240],"dimensionality":3,"extent":[8,30,30]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U80" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U45" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U82" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U47" }, "op_hcompute_hw_kernel_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_kernel_global_wrapper_stencil" }, "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U76" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U41" }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24,72],"dimensionality":4,"extent":[8,3,3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U74"} + "genargs":{"ID":["String","_U39"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24,72],"dimensionality":4,"extent":[8,3,3,3]}},"mode":"lake"} }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_kernel_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U75" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U40" }, "op_hcompute_hw_kernel_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U77" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U42" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U72" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U37" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[15264],"cycle_stride":[1,28,784],"dimensionality":3,"extent":[28,28,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U70"} + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[15264],"cycle_stride":[1,28,784],"dimensionality":3,"extent":[28,28,3]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U71" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U36" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U73" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U38" } }, "connections":[ - ["self.clk","_U78.clk"], - ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","_U78.in"], - ["self.clk","_U83.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U83.in"], + ["self.clk","_U43.clk"], + ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","_U43.in"], + ["self.clk","_U48.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U48.in"], ["self.clk","conv_stencil.clk"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], ["op_hcompute_conv_stencil_2.conv_stencil_op_hcompute_conv_stencil_2_write","conv_stencil.op_hcompute_conv_stencil_2_write"], diff --git a/aha_garnet_design_new/resnet/resnet_garnet.json b/aha_garnet_design_new/resnet/resnet_garnet.json index e614a12e4..932ab4e71 100644 --- a/aha_garnet_design_new/resnet/resnet_garnet.json +++ b/aha_garnet_design_new/resnet/resnet_garnet.json @@ -170,18 +170,6 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -189,7 +177,7 @@ }, "ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[15262],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[15264],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_conv_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -199,7 +187,7 @@ }, "ub_conv_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16046],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16048],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_conv_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -209,7 +197,7 @@ }, "ub_conv_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16830],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16832],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -245,26 +233,26 @@ ["conv_stencil_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U86":{ + "PE_init_U51":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U84":{ + "_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U85":{ + "_U50":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U84.out","PE_init_U86.data.in.0"], - ["_U85.out","PE_init_U86.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U86.data.out"], + ["_U49.out","PE_init_U51.data.in.0"], + ["_U50.out","PE_init_U51.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U51.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -276,26 +264,26 @@ ["conv_stencil_op_hcompute_conv_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U89":{ + "PE_init_U54":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U87":{ + "_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U88":{ + "_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U87.out","PE_init_U89.data.in.0"], - ["_U88.out","PE_init_U89.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_1_write.0","PE_init_U89.data.out"], + ["_U52.out","PE_init_U54.data.in.0"], + ["_U53.out","PE_init_U54.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_1_write.0","PE_init_U54.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -307,26 +295,26 @@ ["conv_stencil_op_hcompute_conv_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U92":{ + "PE_init_U57":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U90":{ + "_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U91":{ + "_U56":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U90.out","PE_init_U92.data.in.0"], - ["_U91.out","PE_init_U92.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_2_write.0","PE_init_U92.data.out"], + ["_U55.out","PE_init_U57.data.in.0"], + ["_U56.out","PE_init_U57.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_2_write.0","PE_init_U57.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -761,26 +749,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U95":{ + "PE_init_U60":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U93":{ + "_U58":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U94":{ + "_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U93.out","PE_init_U95.data.in.0"], - ["_U94.out","PE_init_U95.data.in.1"], - ["self.out_conv_stencil","PE_init_U95.data.out"] + ["_U58.out","PE_init_U60.data.in.0"], + ["_U59.out","PE_init_U60.data.in.1"], + ["self.out_conv_stencil","PE_init_U60.data.out"] ] }, "hcompute_conv_stencil_1":{ @@ -788,26 +776,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U98":{ + "PE_init_U63":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U96":{ + "_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U97":{ + "_U62":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U96.out","PE_init_U98.data.in.0"], - ["_U97.out","PE_init_U98.data.in.1"], - ["self.out_conv_stencil","PE_init_U98.data.out"] + ["_U61.out","PE_init_U63.data.in.0"], + ["_U62.out","PE_init_U63.data.in.1"], + ["self.out_conv_stencil","PE_init_U63.data.out"] ] }, "hcompute_conv_stencil_2":{ @@ -815,26 +803,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U101":{ + "PE_init_U66":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U100":{ + "_U64":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U99":{ + "_U65":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U99.out","PE_init_U101.data.in.0"], - ["_U100.out","PE_init_U101.data.in.1"], - ["self.out_conv_stencil","PE_init_U101.data.out"] + ["_U64.out","PE_init_U66.data.in.0"], + ["_U65.out","PE_init_U66.data.in.1"], + ["self.out_conv_stencil","PE_init_U66.data.out"] ] }, "hcompute_conv_stencil_3":{ @@ -1254,38 +1242,6 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U19":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U21":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -1293,7 +1249,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -1303,7 +1259,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -1313,7 +1269,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -1323,7 +1279,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -1333,7 +1289,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -1343,7 +1299,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -1353,7 +1309,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -1363,7 +1319,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -1441,102 +1397,6 @@ ["op_hcompute_hw_kernel_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U23":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U31":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U43":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U45":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U47":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U53":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U55":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U57":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U61":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U63":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U65":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U67":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U69":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -1544,8 +1404,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[73],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[73],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_10_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1554,8 +1414,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[84],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[84],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_11_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1564,8 +1424,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_12_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1574,8 +1434,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[77],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[77],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_13_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1584,8 +1444,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[85],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[85],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_14_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1594,8 +1454,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_15_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1604,8 +1464,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[78],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[78],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_16_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1614,8 +1474,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[86],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U27"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[86],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_17_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1624,8 +1484,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_18_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1634,8 +1494,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[79],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[79],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_19_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1644,8 +1504,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[87],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[87],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1654,8 +1514,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[81],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[81],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_20_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1664,8 +1524,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_21_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1674,8 +1534,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[80],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[80],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_22_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1684,8 +1544,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[88],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[88],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_23_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1694,8 +1554,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1704,8 +1564,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U13"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1714,8 +1574,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[74],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[74],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1724,8 +1584,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[82],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[82],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1734,8 +1594,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1744,8 +1604,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[75],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U17"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[75],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1754,8 +1614,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[83],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[83],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_8_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1764,8 +1624,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_kernel_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1774,8 +1634,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[76],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[76],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -1901,7 +1761,7 @@ ["ub_hw_kernel_global_wrapper_stencil_BANK_9_garnet.clk_en","ub_hw_kernel_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U81":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U46":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1910,7 +1770,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U80":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U45":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1919,7 +1779,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U82":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U47":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1928,7 +1788,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U76":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U41":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1937,7 +1797,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U75":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1946,7 +1806,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U77":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1955,7 +1815,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U72":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U37":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1964,7 +1824,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U71":{ + "op_hcompute_hw_output_stencil_read_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1973,7 +1833,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U73":{ + "op_hcompute_hw_output_stencil_write_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1994,63 +1854,51 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U104":{ + "PE_init_U69":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U107":{ + "PE_init_U72":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U110":{ + "PE_init_U75":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U102":{ + "_U67":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U103":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U105":{ + "_U70":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U106":{ + "_U71":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U108":{ + "_U73":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U109":{ + "_U74":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "conv_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "conv_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "conv_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2058,7 +1906,7 @@ }, "conv_stencil$ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[15262],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[15264],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "conv_stencil$ub_conv_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -2068,7 +1916,7 @@ }, "conv_stencil$ub_conv_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16046],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16048],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "conv_stencil$ub_conv_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -2078,41 +1926,9 @@ }, "conv_stencil$ub_conv_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"agg2sram_1":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[16830],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[16832],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, - "hw_input_global_wrapper_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U17":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U19":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U21":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2120,7 +1936,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -2130,7 +1946,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -2140,7 +1956,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -2150,7 +1966,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -2160,7 +1976,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -2170,7 +1986,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -2180,7 +1996,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -2190,105 +2006,9 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U23":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U31":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U33":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U35":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U37":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U39":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U41":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U43":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U45":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U47":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U49":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U51":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U53":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U55":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U57":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U61":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U63":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U65":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U67":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U69":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2296,8 +2016,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[73],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[73],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_10_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2306,8 +2026,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[84],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[84],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_11_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2316,8 +2036,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U44"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_12_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2326,8 +2046,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[77],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[77],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_13_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2336,8 +2056,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[85],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[85],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_14_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2346,8 +2066,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_15_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2356,8 +2076,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[78],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[78],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_16_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2366,8 +2086,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[86],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U27"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[86],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_17_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2376,8 +2096,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_18_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2386,8 +2106,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[79],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[79],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_19_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2396,8 +2116,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[87],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[87],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2406,8 +2126,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[81],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[81],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_20_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2416,8 +2136,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U62"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_21_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2426,8 +2146,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U64"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[80],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[80],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_22_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2436,8 +2156,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[88],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[88],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_23_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2446,8 +2166,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2456,8 +2176,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U13"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2466,8 +2186,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[74],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[74],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_4_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2476,8 +2196,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[82],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[82],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_5_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2486,8 +2206,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_6_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2496,8 +2216,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[75],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U17"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[75],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_7_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2506,8 +2226,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U36"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[83],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[83],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_8_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2516,8 +2236,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_9_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -2526,8 +2246,8 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[76],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[24],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U20"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[76],"cycle_stride":[96],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[24],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ "genref":"cgralib.IO", @@ -2802,20 +2522,20 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[15264],"cycle_stride":[1,28,784],"dimensionality":3,"extent":[28,28,3]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U102.out","PE_init_U104.data.in.0"], - ["_U103.out","PE_init_U104.data.in.1"], - ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U104.data.out"], - ["_U105.out","PE_init_U107.data.in.0"], - ["_U106.out","PE_init_U107.data.in.1"], - ["conv_stencil$ub_conv_stencil_BANK_1_garnet.data_in_0","PE_init_U107.data.out"], - ["_U108.out","PE_init_U110.data.in.0"], - ["_U109.out","PE_init_U110.data.in.1"], - ["conv_stencil$ub_conv_stencil_BANK_2_garnet.data_in_0","PE_init_U110.data.out"], + ["_U67.out","PE_init_U69.data.in.0"], + ["_U68.out","PE_init_U69.data.in.1"], + ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U69.data.out"], + ["_U70.out","PE_init_U72.data.in.0"], + ["_U71.out","PE_init_U72.data.in.1"], + ["conv_stencil$ub_conv_stencil_BANK_1_garnet.data_in_0","PE_init_U72.data.out"], + ["_U73.out","PE_init_U75.data.in.0"], + ["_U74.out","PE_init_U75.data.in.1"], + ["conv_stencil$ub_conv_stencil_BANK_2_garnet.data_in_0","PE_init_U75.data.out"], ["conv_stencil$ub_conv_stencil_BANK_0_garnet.clk_en","conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["conv_stencil$ub_conv_stencil_BANK_1_garnet.data_out_1","conv_stencil$ub_conv_stencil_BANK_0_garnet.chain_data_in_1"], ["op_hcompute_conv_stencil_3$inner_compute$add_691_705_706$binop.data.out","conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_0"], diff --git a/aha_garnet_design_new/resnet3_1/resnet3_1.json b/aha_garnet_design_new/resnet3_1/resnet3_1.json index 7c9bedb21..29849126b 100644 --- a/aha_garnet_design_new/resnet3_1/resnet3_1.json +++ b/aha_garnet_design_new/resnet3_1/resnet3_1.json @@ -2,2275 +2,2009 @@ "namespaces":{ "global":{ "modules":{ - "aff__U114":{ + "aff__U105":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U132":{ + "add_all__U123":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U133":{ + "add_all__U124":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U134":{ + "add_all__U125":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U135":{ + "add_all__U126":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U136":{ + "add_all__U127":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U137":{ + "add_all__U128":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U138":{ + "add_all__U129":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U139":{ + "add_all__U130":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U115":{ + "coeff_0_U106":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U117":{ + "coeff_1_U108":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_2_U119":{ + "coeff_2_U110":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000658"]} }, - "coeff_3_U121":{ + "coeff_3_U112":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_4_U123":{ + "coeff_4_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006920"]} }, - "coeff_5_U125":{ + "coeff_5_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U127":{ + "coeff_6_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000003a"]} }, - "coeff_7_U129":{ + "coeff_7_U120":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000d24"]} }, - "const_term_U131":{ + "const_term_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U116":{ + "mul_d0__U107":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U118":{ + "mul_d1__U109":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U120":{ + "mul_d2__U111":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U122":{ + "mul_d3__U113":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U124":{ + "mul_d4__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U126":{ + "mul_d5__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U128":{ + "mul_d6__U119":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U130":{ + "mul_d7__U121":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U116.out","add_all__U132.in0"], - ["mul_d1__U118.out","add_all__U132.in1"], - ["add_all__U133.in0","add_all__U132.out"], - ["mul_d2__U120.out","add_all__U133.in1"], - ["add_all__U134.in0","add_all__U133.out"], - ["mul_d3__U122.out","add_all__U134.in1"], - ["add_all__U135.in0","add_all__U134.out"], - ["mul_d4__U124.out","add_all__U135.in1"], - ["add_all__U136.in0","add_all__U135.out"], - ["mul_d5__U126.out","add_all__U136.in1"], - ["add_all__U137.in0","add_all__U136.out"], - ["mul_d6__U128.out","add_all__U137.in1"], - ["add_all__U138.in0","add_all__U137.out"], - ["mul_d7__U130.out","add_all__U138.in1"], - ["add_all__U139.in0","add_all__U138.out"], - ["const_term_U131.out","add_all__U139.in1"], - ["self.out","add_all__U139.out"], - ["mul_d0__U116.in0","coeff_0_U115.out"], - ["mul_d1__U118.in0","coeff_1_U117.out"], - ["mul_d2__U120.in0","coeff_2_U119.out"], - ["mul_d3__U122.in0","coeff_3_U121.out"], - ["mul_d4__U124.in0","coeff_4_U123.out"], - ["mul_d5__U126.in0","coeff_5_U125.out"], - ["mul_d6__U128.in0","coeff_6_U127.out"], - ["mul_d7__U130.in0","coeff_7_U129.out"], - ["self.d.0","mul_d0__U116.in1"], - ["self.d.1","mul_d1__U118.in1"], - ["self.d.2","mul_d2__U120.in1"], - ["self.d.3","mul_d3__U122.in1"], - ["self.d.4","mul_d4__U124.in1"], - ["self.d.5","mul_d5__U126.in1"], - ["self.d.6","mul_d6__U128.in1"], - ["self.d.7","mul_d7__U130.in1"] + ["mul_d0__U107.out","add_all__U123.in0"], + ["mul_d1__U109.out","add_all__U123.in1"], + ["add_all__U124.in0","add_all__U123.out"], + ["mul_d2__U111.out","add_all__U124.in1"], + ["add_all__U125.in0","add_all__U124.out"], + ["mul_d3__U113.out","add_all__U125.in1"], + ["add_all__U126.in0","add_all__U125.out"], + ["mul_d4__U115.out","add_all__U126.in1"], + ["add_all__U127.in0","add_all__U126.out"], + ["mul_d5__U117.out","add_all__U127.in1"], + ["add_all__U128.in0","add_all__U127.out"], + ["mul_d6__U119.out","add_all__U128.in1"], + ["add_all__U129.in0","add_all__U128.out"], + ["mul_d7__U121.out","add_all__U129.in1"], + ["add_all__U130.in0","add_all__U129.out"], + ["const_term_U122.out","add_all__U130.in1"], + ["self.out","add_all__U130.out"], + ["mul_d0__U107.in0","coeff_0_U106.out"], + ["mul_d1__U109.in0","coeff_1_U108.out"], + ["mul_d2__U111.in0","coeff_2_U110.out"], + ["mul_d3__U113.in0","coeff_3_U112.out"], + ["mul_d4__U115.in0","coeff_4_U114.out"], + ["mul_d5__U117.in0","coeff_5_U116.out"], + ["mul_d6__U119.in0","coeff_6_U118.out"], + ["mul_d7__U121.in0","coeff_7_U120.out"], + ["self.d.0","mul_d0__U107.in1"], + ["self.d.1","mul_d1__U109.in1"], + ["self.d.2","mul_d2__U111.in1"], + ["self.d.3","mul_d3__U113.in1"], + ["self.d.4","mul_d4__U115.in1"], + ["self.d.5","mul_d5__U117.in1"], + ["self.d.6","mul_d6__U119.in1"], + ["self.d.7","mul_d7__U121.in1"] ] }, - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000003a0"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U272":{ + "aff__U198":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U284":{ + "add_all__U210":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U285":{ + "add_all__U211":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U286":{ + "add_all__U212":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U287":{ + "add_all__U213":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U288":{ + "add_all__U214":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U273":{ + "coeff_0_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U275":{ + "coeff_1_U201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U277":{ + "coeff_2_U203":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U279":{ + "coeff_3_U205":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U281":{ + "coeff_4_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U283":{ + "const_term_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U274":{ + "mul_d0__U200":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U276":{ + "mul_d1__U202":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U278":{ + "mul_d2__U204":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U280":{ + "mul_d3__U206":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U282":{ + "mul_d4__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U274.out","add_all__U284.in0"], - ["mul_d1__U276.out","add_all__U284.in1"], - ["add_all__U285.in0","add_all__U284.out"], - ["mul_d2__U278.out","add_all__U285.in1"], - ["add_all__U286.in0","add_all__U285.out"], - ["mul_d3__U280.out","add_all__U286.in1"], - ["add_all__U287.in0","add_all__U286.out"], - ["mul_d4__U282.out","add_all__U287.in1"], - ["add_all__U288.in0","add_all__U287.out"], - ["const_term_U283.out","add_all__U288.in1"], - ["self.out","add_all__U288.out"], - ["mul_d0__U274.in0","coeff_0_U273.out"], - ["mul_d1__U276.in0","coeff_1_U275.out"], - ["mul_d2__U278.in0","coeff_2_U277.out"], - ["mul_d3__U280.in0","coeff_3_U279.out"], - ["mul_d4__U282.in0","coeff_4_U281.out"], - ["self.d.0","mul_d0__U274.in1"], - ["self.d.1","mul_d1__U276.in1"], - ["self.d.2","mul_d2__U278.in1"], - ["self.d.3","mul_d3__U280.in1"], - ["self.d.4","mul_d4__U282.in1"] + ["mul_d0__U200.out","add_all__U210.in0"], + ["mul_d1__U202.out","add_all__U210.in1"], + ["add_all__U211.in0","add_all__U210.out"], + ["mul_d2__U204.out","add_all__U211.in1"], + ["add_all__U212.in0","add_all__U211.out"], + ["mul_d3__U206.out","add_all__U212.in1"], + ["add_all__U213.in0","add_all__U212.out"], + ["mul_d4__U208.out","add_all__U213.in1"], + ["add_all__U214.in0","add_all__U213.out"], + ["const_term_U209.out","add_all__U214.in1"], + ["self.out","add_all__U214.out"], + ["mul_d0__U200.in0","coeff_0_U199.out"], + ["mul_d1__U202.in0","coeff_1_U201.out"], + ["mul_d2__U204.in0","coeff_2_U203.out"], + ["mul_d3__U206.in0","coeff_3_U205.out"], + ["mul_d4__U208.in0","coeff_4_U207.out"], + ["self.d.0","mul_d0__U200.in1"], + ["self.d.1","mul_d1__U202.in1"], + ["self.d.2","mul_d2__U204.in1"], + ["self.d.3","mul_d3__U206.in1"], + ["self.d.4","mul_d4__U208.in1"] ] }, - "aff__U302":{ + "aff__U228":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U303":{ + "coeff_0_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U305":{ + "coeff_1_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U307":{ + "coeff_2_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U309":{ + "coeff_3_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U311":{ + "coeff_4_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U304":{ + "mul_d0__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U306":{ + "mul_d1__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U308":{ + "mul_d2__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U310":{ + "mul_d3__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U312":{ + "mul_d4__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U304.out","add_all__U314.in0"], - ["mul_d1__U306.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U308.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U310.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U312.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["const_term_U313.out","add_all__U318.in1"], - ["self.out","add_all__U318.out"], - ["mul_d0__U304.in0","coeff_0_U303.out"], - ["mul_d1__U306.in0","coeff_1_U305.out"], - ["mul_d2__U308.in0","coeff_2_U307.out"], - ["mul_d3__U310.in0","coeff_3_U309.out"], - ["mul_d4__U312.in0","coeff_4_U311.out"], - ["self.d.0","mul_d0__U304.in1"], - ["self.d.1","mul_d1__U306.in1"], - ["self.d.2","mul_d2__U308.in1"], - ["self.d.3","mul_d3__U310.in1"], - ["self.d.4","mul_d4__U312.in1"] + ["mul_d0__U230.out","add_all__U240.in0"], + ["mul_d1__U232.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U234.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U236.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U238.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["const_term_U239.out","add_all__U244.in1"], + ["self.out","add_all__U244.out"], + ["mul_d0__U230.in0","coeff_0_U229.out"], + ["mul_d1__U232.in0","coeff_1_U231.out"], + ["mul_d2__U234.in0","coeff_2_U233.out"], + ["mul_d3__U236.in0","coeff_3_U235.out"], + ["mul_d4__U238.in0","coeff_4_U237.out"], + ["self.d.0","mul_d0__U230.in1"], + ["self.d.1","mul_d1__U232.in1"], + ["self.d.2","mul_d2__U234.in1"], + ["self.d.3","mul_d3__U236.in1"], + ["self.d.4","mul_d4__U238.in1"] ] }, - "aff__U321":{ + "aff__U247":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",10,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U343":{ + "add_all__U269":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U344":{ + "add_all__U270":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U345":{ + "add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U346":{ + "add_all__U272":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U347":{ + "add_all__U273":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U348":{ + "add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U349":{ + "add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U350":{ + "add_all__U276":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U351":{ + "add_all__U277":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U352":{ + "add_all__U278":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U322":{ + "coeff_0_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U324":{ + "coeff_1_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U326":{ + "coeff_2_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U328":{ + "coeff_3_U254":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U330":{ + "coeff_4_U256":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U332":{ + "coeff_5_U258":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_6_U334":{ + "coeff_6_U260":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_7_U336":{ + "coeff_7_U262":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_8_U338":{ + "coeff_8_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_9_U340":{ + "coeff_9_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U342":{ + "const_term_U268":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U323":{ + "mul_d0__U249":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U325":{ + "mul_d1__U251":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U327":{ + "mul_d2__U253":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U329":{ + "mul_d3__U255":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U331":{ + "mul_d4__U257":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U333":{ + "mul_d5__U259":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U335":{ + "mul_d6__U261":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U337":{ + "mul_d7__U263":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U339":{ + "mul_d8__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d9__U341":{ + "mul_d9__U267":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U323.out","add_all__U343.in0"], - ["mul_d1__U325.out","add_all__U343.in1"], - ["add_all__U344.in0","add_all__U343.out"], - ["mul_d2__U327.out","add_all__U344.in1"], - ["add_all__U345.in0","add_all__U344.out"], - ["mul_d3__U329.out","add_all__U345.in1"], - ["add_all__U346.in0","add_all__U345.out"], - ["mul_d4__U331.out","add_all__U346.in1"], - ["add_all__U347.in0","add_all__U346.out"], - ["mul_d5__U333.out","add_all__U347.in1"], - ["add_all__U348.in0","add_all__U347.out"], - ["mul_d6__U335.out","add_all__U348.in1"], - ["add_all__U349.in0","add_all__U348.out"], - ["mul_d7__U337.out","add_all__U349.in1"], - ["add_all__U350.in0","add_all__U349.out"], - ["mul_d8__U339.out","add_all__U350.in1"], - ["add_all__U351.in0","add_all__U350.out"], - ["mul_d9__U341.out","add_all__U351.in1"], - ["add_all__U352.in0","add_all__U351.out"], - ["const_term_U342.out","add_all__U352.in1"], - ["self.out","add_all__U352.out"], - ["mul_d0__U323.in0","coeff_0_U322.out"], - ["mul_d1__U325.in0","coeff_1_U324.out"], - ["mul_d2__U327.in0","coeff_2_U326.out"], - ["mul_d3__U329.in0","coeff_3_U328.out"], - ["mul_d4__U331.in0","coeff_4_U330.out"], - ["mul_d5__U333.in0","coeff_5_U332.out"], - ["mul_d6__U335.in0","coeff_6_U334.out"], - ["mul_d7__U337.in0","coeff_7_U336.out"], - ["mul_d8__U339.in0","coeff_8_U338.out"], - ["mul_d9__U341.in0","coeff_9_U340.out"], - ["self.d.0","mul_d0__U323.in1"], - ["self.d.1","mul_d1__U325.in1"], - ["self.d.2","mul_d2__U327.in1"], - ["self.d.3","mul_d3__U329.in1"], - ["self.d.4","mul_d4__U331.in1"], - ["self.d.5","mul_d5__U333.in1"], - ["self.d.6","mul_d6__U335.in1"], - ["self.d.7","mul_d7__U337.in1"], - ["self.d.8","mul_d8__U339.in1"], - ["self.d.9","mul_d9__U341.in1"] + ["mul_d0__U249.out","add_all__U269.in0"], + ["mul_d1__U251.out","add_all__U269.in1"], + ["add_all__U270.in0","add_all__U269.out"], + ["mul_d2__U253.out","add_all__U270.in1"], + ["add_all__U271.in0","add_all__U270.out"], + ["mul_d3__U255.out","add_all__U271.in1"], + ["add_all__U272.in0","add_all__U271.out"], + ["mul_d4__U257.out","add_all__U272.in1"], + ["add_all__U273.in0","add_all__U272.out"], + ["mul_d5__U259.out","add_all__U273.in1"], + ["add_all__U274.in0","add_all__U273.out"], + ["mul_d6__U261.out","add_all__U274.in1"], + ["add_all__U275.in0","add_all__U274.out"], + ["mul_d7__U263.out","add_all__U275.in1"], + ["add_all__U276.in0","add_all__U275.out"], + ["mul_d8__U265.out","add_all__U276.in1"], + ["add_all__U277.in0","add_all__U276.out"], + ["mul_d9__U267.out","add_all__U277.in1"], + ["add_all__U278.in0","add_all__U277.out"], + ["const_term_U268.out","add_all__U278.in1"], + ["self.out","add_all__U278.out"], + ["mul_d0__U249.in0","coeff_0_U248.out"], + ["mul_d1__U251.in0","coeff_1_U250.out"], + ["mul_d2__U253.in0","coeff_2_U252.out"], + ["mul_d3__U255.in0","coeff_3_U254.out"], + ["mul_d4__U257.in0","coeff_4_U256.out"], + ["mul_d5__U259.in0","coeff_5_U258.out"], + ["mul_d6__U261.in0","coeff_6_U260.out"], + ["mul_d7__U263.in0","coeff_7_U262.out"], + ["mul_d8__U265.in0","coeff_8_U264.out"], + ["mul_d9__U267.in0","coeff_9_U266.out"], + ["self.d.0","mul_d0__U249.in1"], + ["self.d.1","mul_d1__U251.in1"], + ["self.d.2","mul_d2__U253.in1"], + ["self.d.3","mul_d3__U255.in1"], + ["self.d.4","mul_d4__U257.in1"], + ["self.d.5","mul_d5__U259.in1"], + ["self.d.6","mul_d6__U261.in1"], + ["self.d.7","mul_d7__U263.in1"], + ["self.d.8","mul_d8__U265.in1"], + ["self.d.9","mul_d9__U267.in1"] + ] + }, + "aff__U32":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U42":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U43":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U44":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U45":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "coeff_2_U37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000003a"]} + }, + "coeff_3_U39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000d24"]} + }, + "const_term_U41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U34":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U36":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U38":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U40":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U401":{ + "aff__U327":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",10,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U423":{ + "add_all__U349":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U424":{ + "add_all__U350":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U425":{ + "add_all__U351":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U426":{ + "add_all__U352":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U427":{ + "add_all__U353":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U428":{ + "add_all__U354":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U429":{ + "add_all__U355":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U430":{ + "add_all__U356":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U431":{ + "add_all__U357":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U432":{ + "add_all__U358":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U402":{ + "coeff_0_U328":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U404":{ + "coeff_1_U330":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U406":{ + "coeff_2_U332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_3_U408":{ + "coeff_3_U334":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_4_U410":{ + "coeff_4_U336":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_5_U412":{ + "coeff_5_U338":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U414":{ + "coeff_6_U340":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_7_U416":{ + "coeff_7_U342":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_8_U418":{ + "coeff_8_U344":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_9_U420":{ + "coeff_9_U346":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U422":{ + "const_term_U348":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U403":{ + "mul_d0__U329":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U405":{ + "mul_d1__U331":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U407":{ + "mul_d2__U333":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U409":{ + "mul_d3__U335":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U411":{ + "mul_d4__U337":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U413":{ + "mul_d5__U339":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U415":{ + "mul_d6__U341":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U417":{ + "mul_d7__U343":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U419":{ + "mul_d8__U345":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d9__U421":{ + "mul_d9__U347":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U403.out","add_all__U423.in0"], - ["mul_d1__U405.out","add_all__U423.in1"], - ["add_all__U424.in0","add_all__U423.out"], - ["mul_d2__U407.out","add_all__U424.in1"], - ["add_all__U425.in0","add_all__U424.out"], - ["mul_d3__U409.out","add_all__U425.in1"], - ["add_all__U426.in0","add_all__U425.out"], - ["mul_d4__U411.out","add_all__U426.in1"], - ["add_all__U427.in0","add_all__U426.out"], - ["mul_d5__U413.out","add_all__U427.in1"], - ["add_all__U428.in0","add_all__U427.out"], - ["mul_d6__U415.out","add_all__U428.in1"], - ["add_all__U429.in0","add_all__U428.out"], - ["mul_d7__U417.out","add_all__U429.in1"], - ["add_all__U430.in0","add_all__U429.out"], - ["mul_d8__U419.out","add_all__U430.in1"], - ["add_all__U431.in0","add_all__U430.out"], - ["mul_d9__U421.out","add_all__U431.in1"], - ["add_all__U432.in0","add_all__U431.out"], - ["const_term_U422.out","add_all__U432.in1"], - ["self.out","add_all__U432.out"], - ["mul_d0__U403.in0","coeff_0_U402.out"], - ["mul_d1__U405.in0","coeff_1_U404.out"], - ["mul_d2__U407.in0","coeff_2_U406.out"], - ["mul_d3__U409.in0","coeff_3_U408.out"], - ["mul_d4__U411.in0","coeff_4_U410.out"], - ["mul_d5__U413.in0","coeff_5_U412.out"], - ["mul_d6__U415.in0","coeff_6_U414.out"], - ["mul_d7__U417.in0","coeff_7_U416.out"], - ["mul_d8__U419.in0","coeff_8_U418.out"], - ["mul_d9__U421.in0","coeff_9_U420.out"], - ["self.d.0","mul_d0__U403.in1"], - ["self.d.1","mul_d1__U405.in1"], - ["self.d.2","mul_d2__U407.in1"], - ["self.d.3","mul_d3__U409.in1"], - ["self.d.4","mul_d4__U411.in1"], - ["self.d.5","mul_d5__U413.in1"], - ["self.d.6","mul_d6__U415.in1"], - ["self.d.7","mul_d7__U417.in1"], - ["self.d.8","mul_d8__U419.in1"], - ["self.d.9","mul_d9__U421.in1"] - ] - }, - "aff__U41":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U51":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U52":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U53":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U54":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U42":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U44":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_2_U46":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003a"]} - }, - "coeff_3_U48":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000d24"]} - }, - "const_term_U50":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U43":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U45":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U47":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U49":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U329.out","add_all__U349.in0"], + ["mul_d1__U331.out","add_all__U349.in1"], + ["add_all__U350.in0","add_all__U349.out"], + ["mul_d2__U333.out","add_all__U350.in1"], + ["add_all__U351.in0","add_all__U350.out"], + ["mul_d3__U335.out","add_all__U351.in1"], + ["add_all__U352.in0","add_all__U351.out"], + ["mul_d4__U337.out","add_all__U352.in1"], + ["add_all__U353.in0","add_all__U352.out"], + ["mul_d5__U339.out","add_all__U353.in1"], + ["add_all__U354.in0","add_all__U353.out"], + ["mul_d6__U341.out","add_all__U354.in1"], + ["add_all__U355.in0","add_all__U354.out"], + ["mul_d7__U343.out","add_all__U355.in1"], + ["add_all__U356.in0","add_all__U355.out"], + ["mul_d8__U345.out","add_all__U356.in1"], + ["add_all__U357.in0","add_all__U356.out"], + ["mul_d9__U347.out","add_all__U357.in1"], + ["add_all__U358.in0","add_all__U357.out"], + ["const_term_U348.out","add_all__U358.in1"], + ["self.out","add_all__U358.out"], + ["mul_d0__U329.in0","coeff_0_U328.out"], + ["mul_d1__U331.in0","coeff_1_U330.out"], + ["mul_d2__U333.in0","coeff_2_U332.out"], + ["mul_d3__U335.in0","coeff_3_U334.out"], + ["mul_d4__U337.in0","coeff_4_U336.out"], + ["mul_d5__U339.in0","coeff_5_U338.out"], + ["mul_d6__U341.in0","coeff_6_U340.out"], + ["mul_d7__U343.in0","coeff_7_U342.out"], + ["mul_d8__U345.in0","coeff_8_U344.out"], + ["mul_d9__U347.in0","coeff_9_U346.out"], + ["self.d.0","mul_d0__U329.in1"], + ["self.d.1","mul_d1__U331.in1"], + ["self.d.2","mul_d2__U333.in1"], + ["self.d.3","mul_d3__U335.in1"], + ["self.d.4","mul_d4__U337.in1"], + ["self.d.5","mul_d5__U339.in1"], + ["self.d.6","mul_d6__U341.in1"], + ["self.d.7","mul_d7__U343.in1"], + ["self.d.8","mul_d8__U345.in1"], + ["self.d.9","mul_d9__U347.in1"] ] }, - "aff__U437":{ + "aff__U363":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U443":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U444":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U364":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U366":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U442":{ + "const_term_U368":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U439":{ + "mul_d0__U365":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U367":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U443.in0"], - ["mul_d1__U441.out","add_all__U443.in1"], - ["add_all__U444.in0","add_all__U443.out"], - ["const_term_U442.out","add_all__U444.in1"], - ["self.out","add_all__U444.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"] + ["mul_d0__U365.out","add_all__U369.in0"], + ["mul_d1__U367.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["const_term_U368.out","add_all__U370.in1"], + ["self.out","add_all__U370.out"], + ["mul_d0__U365.in0","coeff_0_U364.out"], + ["mul_d1__U367.in0","coeff_1_U366.out"], + ["self.d.0","mul_d0__U365.in1"], + ["self.d.1","mul_d1__U367.in1"] ] }, - "aff__U452":{ + "aff__U377":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U458":{ + "add_all__U383":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U459":{ + "add_all__U384":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U453":{ + "coeff_0_U378":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U455":{ + "coeff_1_U380":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U457":{ + "const_term_U382":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U454":{ + "mul_d0__U379":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U456":{ + "mul_d1__U381":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U454.out","add_all__U458.in0"], - ["mul_d1__U456.out","add_all__U458.in1"], - ["add_all__U459.in0","add_all__U458.out"], - ["const_term_U457.out","add_all__U459.in1"], - ["self.out","add_all__U459.out"], - ["mul_d0__U454.in0","coeff_0_U453.out"], - ["mul_d1__U456.in0","coeff_1_U455.out"], - ["self.d.0","mul_d0__U454.in1"], - ["self.d.1","mul_d1__U456.in1"] + ["mul_d0__U379.out","add_all__U383.in0"], + ["mul_d1__U381.out","add_all__U383.in1"], + ["add_all__U384.in0","add_all__U383.out"], + ["const_term_U382.out","add_all__U384.in1"], + ["self.out","add_all__U384.out"], + ["mul_d0__U379.in0","coeff_0_U378.out"], + ["mul_d1__U381.in0","coeff_1_U380.out"], + ["self.d.0","mul_d0__U379.in1"], + ["self.d.1","mul_d1__U381.in1"] ] }, - "aff__U467":{ + "aff__U391":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U473":{ + "add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U474":{ + "add_all__U398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U468":{ + "coeff_0_U392":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U470":{ + "coeff_1_U394":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U472":{ + "const_term_U396":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U469":{ + "mul_d0__U393":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U471":{ + "mul_d1__U395":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U469.out","add_all__U473.in0"], - ["mul_d1__U471.out","add_all__U473.in1"], - ["add_all__U474.in0","add_all__U473.out"], - ["const_term_U472.out","add_all__U474.in1"], - ["self.out","add_all__U474.out"], - ["mul_d0__U469.in0","coeff_0_U468.out"], - ["mul_d1__U471.in0","coeff_1_U470.out"], - ["self.d.0","mul_d0__U469.in1"], - ["self.d.1","mul_d1__U471.in1"] + ["mul_d0__U393.out","add_all__U397.in0"], + ["mul_d1__U395.out","add_all__U397.in1"], + ["add_all__U398.in0","add_all__U397.out"], + ["const_term_U396.out","add_all__U398.in1"], + ["self.out","add_all__U398.out"], + ["mul_d0__U393.in0","coeff_0_U392.out"], + ["mul_d1__U395.in0","coeff_1_U394.out"], + ["self.d.0","mul_d0__U393.in1"], + ["self.d.1","mul_d1__U395.in1"] ] }, - "aff__U482":{ + "aff__U405":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U488":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U489":{ + "add_all__U412":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U406":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U487":{ + "const_term_U410":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U484":{ + "mul_d0__U407":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U409":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U488.in0"], - ["mul_d1__U486.out","add_all__U488.in1"], - ["add_all__U489.in0","add_all__U488.out"], - ["const_term_U487.out","add_all__U489.in1"], - ["self.out","add_all__U489.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"] + ["mul_d0__U407.out","add_all__U411.in0"], + ["mul_d1__U409.out","add_all__U411.in1"], + ["add_all__U412.in0","add_all__U411.out"], + ["const_term_U410.out","add_all__U412.in1"], + ["self.out","add_all__U412.out"], + ["mul_d0__U407.in0","coeff_0_U406.out"], + ["mul_d1__U409.in0","coeff_1_U408.out"], + ["self.d.0","mul_d0__U407.in1"], + ["self.d.1","mul_d1__U409.in1"] ] }, - "aff__U497":{ + "aff__U419":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U503":{ + "add_all__U425":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U504":{ + "add_all__U426":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U498":{ + "coeff_0_U420":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U500":{ + "coeff_1_U422":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U502":{ + "const_term_U424":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U499":{ + "mul_d0__U421":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U501":{ + "mul_d1__U423":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U499.out","add_all__U503.in0"], - ["mul_d1__U501.out","add_all__U503.in1"], - ["add_all__U504.in0","add_all__U503.out"], - ["const_term_U502.out","add_all__U504.in1"], - ["self.out","add_all__U504.out"], - ["mul_d0__U499.in0","coeff_0_U498.out"], - ["mul_d1__U501.in0","coeff_1_U500.out"], - ["self.d.0","mul_d0__U499.in1"], - ["self.d.1","mul_d1__U501.in1"] + ["mul_d0__U421.out","add_all__U425.in0"], + ["mul_d1__U423.out","add_all__U425.in1"], + ["add_all__U426.in0","add_all__U425.out"], + ["const_term_U424.out","add_all__U426.in1"], + ["self.out","add_all__U426.out"], + ["mul_d0__U421.in0","coeff_0_U420.out"], + ["mul_d1__U423.in0","coeff_1_U422.out"], + ["self.d.0","mul_d0__U421.in1"], + ["self.d.1","mul_d1__U423.in1"] ] }, - "aff__U512":{ + "aff__U433":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U518":{ + "add_all__U439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U519":{ + "add_all__U440":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U513":{ + "coeff_0_U434":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U515":{ + "coeff_1_U436":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U517":{ + "const_term_U438":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U514":{ + "mul_d0__U435":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U516":{ + "mul_d1__U437":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U514.out","add_all__U518.in0"], - ["mul_d1__U516.out","add_all__U518.in1"], - ["add_all__U519.in0","add_all__U518.out"], - ["const_term_U517.out","add_all__U519.in1"], - ["self.out","add_all__U519.out"], - ["mul_d0__U514.in0","coeff_0_U513.out"], - ["mul_d1__U516.in0","coeff_1_U515.out"], - ["self.d.0","mul_d0__U514.in1"], - ["self.d.1","mul_d1__U516.in1"] + ["mul_d0__U435.out","add_all__U439.in0"], + ["mul_d1__U437.out","add_all__U439.in1"], + ["add_all__U440.in0","add_all__U439.out"], + ["const_term_U438.out","add_all__U440.in1"], + ["self.out","add_all__U440.out"], + ["mul_d0__U435.in0","coeff_0_U434.out"], + ["mul_d1__U437.in0","coeff_1_U436.out"], + ["self.d.0","mul_d0__U435.in1"], + ["self.d.1","mul_d1__U437.in1"] ] }, - "aff__U527":{ + "aff__U447":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U533":{ + "add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U534":{ + "add_all__U454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U528":{ + "coeff_0_U448":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U530":{ + "coeff_1_U450":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U532":{ + "const_term_U452":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U529":{ + "mul_d0__U449":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U531":{ + "mul_d1__U451":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U529.out","add_all__U533.in0"], - ["mul_d1__U531.out","add_all__U533.in1"], - ["add_all__U534.in0","add_all__U533.out"], - ["const_term_U532.out","add_all__U534.in1"], - ["self.out","add_all__U534.out"], - ["mul_d0__U529.in0","coeff_0_U528.out"], - ["mul_d1__U531.in0","coeff_1_U530.out"], - ["self.d.0","mul_d0__U529.in1"], - ["self.d.1","mul_d1__U531.in1"] + ["mul_d0__U449.out","add_all__U453.in0"], + ["mul_d1__U451.out","add_all__U453.in1"], + ["add_all__U454.in0","add_all__U453.out"], + ["const_term_U452.out","add_all__U454.in1"], + ["self.out","add_all__U454.out"], + ["mul_d0__U449.in0","coeff_0_U448.out"], + ["mul_d1__U451.in0","coeff_1_U450.out"], + ["self.d.0","mul_d0__U449.in1"], + ["self.d.1","mul_d1__U451.in1"] ] }, - "aff__U542":{ + "aff__U461":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U548":{ + "add_all__U467":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U549":{ + "add_all__U468":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U543":{ + "coeff_0_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U545":{ + "coeff_1_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U547":{ + "const_term_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U544":{ + "mul_d0__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U546":{ + "mul_d1__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U544.out","add_all__U548.in0"], - ["mul_d1__U546.out","add_all__U548.in1"], - ["add_all__U549.in0","add_all__U548.out"], - ["const_term_U547.out","add_all__U549.in1"], - ["self.out","add_all__U549.out"], - ["mul_d0__U544.in0","coeff_0_U543.out"], - ["mul_d1__U546.in0","coeff_1_U545.out"], - ["self.d.0","mul_d0__U544.in1"], - ["self.d.1","mul_d1__U546.in1"] + ["mul_d0__U463.out","add_all__U467.in0"], + ["mul_d1__U465.out","add_all__U467.in1"], + ["add_all__U468.in0","add_all__U467.out"], + ["const_term_U466.out","add_all__U468.in1"], + ["self.out","add_all__U468.out"], + ["mul_d0__U463.in0","coeff_0_U462.out"], + ["mul_d1__U465.in0","coeff_1_U464.out"], + ["self.d.0","mul_d0__U463.in1"], + ["self.d.1","mul_d1__U465.in1"] ] }, - "aff__U557":{ + "aff__U474":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U575":{ + "add_all__U492":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U576":{ + "add_all__U493":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U577":{ + "add_all__U494":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U578":{ + "add_all__U495":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U579":{ + "add_all__U496":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U580":{ + "add_all__U497":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U581":{ + "add_all__U498":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U582":{ + "add_all__U499":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U558":{ + "coeff_0_U475":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U560":{ + "coeff_1_U477":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U562":{ + "coeff_2_U479":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U564":{ + "coeff_3_U481":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U566":{ + "coeff_4_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_5_U568":{ + "coeff_5_U485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_6_U570":{ + "coeff_6_U487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U572":{ + "coeff_7_U489":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U574":{ + "const_term_U491":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012d60"]} }, - "mul_d0__U559":{ + "mul_d0__U476":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U561":{ + "mul_d1__U478":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U563":{ + "mul_d2__U480":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U565":{ + "mul_d3__U482":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U567":{ + "mul_d4__U484":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U569":{ + "mul_d5__U486":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U571":{ + "mul_d6__U488":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U573":{ + "mul_d7__U490":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U559.out","add_all__U575.in0"], - ["mul_d1__U561.out","add_all__U575.in1"], - ["add_all__U576.in0","add_all__U575.out"], - ["mul_d2__U563.out","add_all__U576.in1"], - ["add_all__U577.in0","add_all__U576.out"], - ["mul_d3__U565.out","add_all__U577.in1"], - ["add_all__U578.in0","add_all__U577.out"], - ["mul_d4__U567.out","add_all__U578.in1"], - ["add_all__U579.in0","add_all__U578.out"], - ["mul_d5__U569.out","add_all__U579.in1"], - ["add_all__U580.in0","add_all__U579.out"], - ["mul_d6__U571.out","add_all__U580.in1"], - ["add_all__U581.in0","add_all__U580.out"], - ["mul_d7__U573.out","add_all__U581.in1"], - ["add_all__U582.in0","add_all__U581.out"], - ["const_term_U574.out","add_all__U582.in1"], - ["self.out","add_all__U582.out"], - ["mul_d0__U559.in0","coeff_0_U558.out"], - ["mul_d1__U561.in0","coeff_1_U560.out"], - ["mul_d2__U563.in0","coeff_2_U562.out"], - ["mul_d3__U565.in0","coeff_3_U564.out"], - ["mul_d4__U567.in0","coeff_4_U566.out"], - ["mul_d5__U569.in0","coeff_5_U568.out"], - ["mul_d6__U571.in0","coeff_6_U570.out"], - ["mul_d7__U573.in0","coeff_7_U572.out"], - ["self.d.0","mul_d0__U559.in1"], - ["self.d.1","mul_d1__U561.in1"], - ["self.d.2","mul_d2__U563.in1"], - ["self.d.3","mul_d3__U565.in1"], - ["self.d.4","mul_d4__U567.in1"], - ["self.d.5","mul_d5__U569.in1"], - ["self.d.6","mul_d6__U571.in1"], - ["self.d.7","mul_d7__U573.in1"] + ["mul_d0__U476.out","add_all__U492.in0"], + ["mul_d1__U478.out","add_all__U492.in1"], + ["add_all__U493.in0","add_all__U492.out"], + ["mul_d2__U480.out","add_all__U493.in1"], + ["add_all__U494.in0","add_all__U493.out"], + ["mul_d3__U482.out","add_all__U494.in1"], + ["add_all__U495.in0","add_all__U494.out"], + ["mul_d4__U484.out","add_all__U495.in1"], + ["add_all__U496.in0","add_all__U495.out"], + ["mul_d5__U486.out","add_all__U496.in1"], + ["add_all__U497.in0","add_all__U496.out"], + ["mul_d6__U488.out","add_all__U497.in1"], + ["add_all__U498.in0","add_all__U497.out"], + ["mul_d7__U490.out","add_all__U498.in1"], + ["add_all__U499.in0","add_all__U498.out"], + ["const_term_U491.out","add_all__U499.in1"], + ["self.out","add_all__U499.out"], + ["mul_d0__U476.in0","coeff_0_U475.out"], + ["mul_d1__U478.in0","coeff_1_U477.out"], + ["mul_d2__U480.in0","coeff_2_U479.out"], + ["mul_d3__U482.in0","coeff_3_U481.out"], + ["mul_d4__U484.in0","coeff_4_U483.out"], + ["mul_d5__U486.in0","coeff_5_U485.out"], + ["mul_d6__U488.in0","coeff_6_U487.out"], + ["mul_d7__U490.in0","coeff_7_U489.out"], + ["self.d.0","mul_d0__U476.in1"], + ["self.d.1","mul_d1__U478.in1"], + ["self.d.2","mul_d2__U480.in1"], + ["self.d.3","mul_d3__U482.in1"], + ["self.d.4","mul_d4__U484.in1"], + ["self.d.5","mul_d5__U486.in1"], + ["self.d.6","mul_d6__U488.in1"], + ["self.d.7","mul_d7__U490.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U77":{ + "add_all__U68":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U78":{ + "add_all__U69":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U79":{ + "add_all__U70":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U80":{ + "add_all__U71":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U81":{ + "add_all__U72":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U82":{ + "add_all__U73":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000f0"]} }, - "coeff_6_U70":{ + "coeff_6_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U72":{ + "coeff_7_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U74":{ + "const_term_U65":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U71":{ + "mul_d6__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U73":{ + "mul_d7__U64":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U75.in0"], - ["mul_d1__U61.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["mul_d2__U63.out","add_all__U76.in1"], - ["add_all__U77.in0","add_all__U76.out"], - ["mul_d3__U65.out","add_all__U77.in1"], - ["add_all__U78.in0","add_all__U77.out"], - ["mul_d4__U67.out","add_all__U78.in1"], - ["add_all__U79.in0","add_all__U78.out"], - ["mul_d5__U69.out","add_all__U79.in1"], - ["add_all__U80.in0","add_all__U79.out"], - ["mul_d6__U71.out","add_all__U80.in1"], - ["add_all__U81.in0","add_all__U80.out"], - ["mul_d7__U73.out","add_all__U81.in1"], - ["add_all__U82.in0","add_all__U81.out"], - ["const_term_U74.out","add_all__U82.in1"], - ["self.out","add_all__U82.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["mul_d6__U71.in0","coeff_6_U70.out"], - ["mul_d7__U73.in0","coeff_7_U72.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"], - ["self.d.6","mul_d6__U71.in1"], - ["self.d.7","mul_d7__U73.in1"] + ["mul_d0__U50.out","add_all__U66.in0"], + ["mul_d1__U52.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["mul_d2__U54.out","add_all__U67.in1"], + ["add_all__U68.in0","add_all__U67.out"], + ["mul_d3__U56.out","add_all__U68.in1"], + ["add_all__U69.in0","add_all__U68.out"], + ["mul_d4__U58.out","add_all__U69.in1"], + ["add_all__U70.in0","add_all__U69.out"], + ["mul_d5__U60.out","add_all__U70.in1"], + ["add_all__U71.in0","add_all__U70.out"], + ["mul_d6__U62.out","add_all__U71.in1"], + ["add_all__U72.in0","add_all__U71.out"], + ["mul_d7__U64.out","add_all__U72.in1"], + ["add_all__U73.in0","add_all__U72.out"], + ["const_term_U65.out","add_all__U73.in1"], + ["self.out","add_all__U73.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["mul_d6__U62.in0","coeff_6_U61.out"], + ["mul_d7__U64.in0","coeff_7_U63.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"], + ["self.d.6","mul_d6__U62.in1"], + ["self.d.7","mul_d7__U64.in1"] ] }, - "aff__U614":{ + "aff__U531":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U632":{ + "add_all__U549":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U633":{ + "add_all__U550":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U634":{ + "add_all__U551":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U635":{ + "add_all__U552":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U636":{ + "add_all__U553":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U637":{ + "add_all__U554":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U638":{ + "add_all__U555":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U639":{ + "add_all__U556":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U615":{ + "coeff_0_U532":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U617":{ + "coeff_1_U534":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000e"]} }, - "coeff_2_U619":{ + "coeff_2_U536":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_3_U621":{ + "coeff_3_U538":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006200"]} }, - "coeff_4_U623":{ + "coeff_4_U540":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_5_U625":{ + "coeff_5_U542":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_6_U627":{ + "coeff_6_U544":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001880"]} }, - "coeff_7_U629":{ + "coeff_7_U546":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000310"]} }, - "const_term_U631":{ + "const_term_U548":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U616":{ + "mul_d0__U533":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U618":{ + "mul_d1__U535":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U620":{ + "mul_d2__U537":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U622":{ + "mul_d3__U539":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U624":{ + "mul_d4__U541":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U626":{ + "mul_d5__U543":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U628":{ + "mul_d6__U545":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U630":{ + "mul_d7__U547":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U616.out","add_all__U632.in0"], - ["mul_d1__U618.out","add_all__U632.in1"], - ["add_all__U633.in0","add_all__U632.out"], - ["mul_d2__U620.out","add_all__U633.in1"], - ["add_all__U634.in0","add_all__U633.out"], - ["mul_d3__U622.out","add_all__U634.in1"], - ["add_all__U635.in0","add_all__U634.out"], - ["mul_d4__U624.out","add_all__U635.in1"], - ["add_all__U636.in0","add_all__U635.out"], - ["mul_d5__U626.out","add_all__U636.in1"], - ["add_all__U637.in0","add_all__U636.out"], - ["mul_d6__U628.out","add_all__U637.in1"], - ["add_all__U638.in0","add_all__U637.out"], - ["mul_d7__U630.out","add_all__U638.in1"], - ["add_all__U639.in0","add_all__U638.out"], - ["const_term_U631.out","add_all__U639.in1"], - ["self.out","add_all__U639.out"], - ["mul_d0__U616.in0","coeff_0_U615.out"], - ["mul_d1__U618.in0","coeff_1_U617.out"], - ["mul_d2__U620.in0","coeff_2_U619.out"], - ["mul_d3__U622.in0","coeff_3_U621.out"], - ["mul_d4__U624.in0","coeff_4_U623.out"], - ["mul_d5__U626.in0","coeff_5_U625.out"], - ["mul_d6__U628.in0","coeff_6_U627.out"], - ["mul_d7__U630.in0","coeff_7_U629.out"], - ["self.d.0","mul_d0__U616.in1"], - ["self.d.1","mul_d1__U618.in1"], - ["self.d.2","mul_d2__U620.in1"], - ["self.d.3","mul_d3__U622.in1"], - ["self.d.4","mul_d4__U624.in1"], - ["self.d.5","mul_d5__U626.in1"], - ["self.d.6","mul_d6__U628.in1"], - ["self.d.7","mul_d7__U630.in1"] + ["mul_d0__U533.out","add_all__U549.in0"], + ["mul_d1__U535.out","add_all__U549.in1"], + ["add_all__U550.in0","add_all__U549.out"], + ["mul_d2__U537.out","add_all__U550.in1"], + ["add_all__U551.in0","add_all__U550.out"], + ["mul_d3__U539.out","add_all__U551.in1"], + ["add_all__U552.in0","add_all__U551.out"], + ["mul_d4__U541.out","add_all__U552.in1"], + ["add_all__U553.in0","add_all__U552.out"], + ["mul_d5__U543.out","add_all__U553.in1"], + ["add_all__U554.in0","add_all__U553.out"], + ["mul_d6__U545.out","add_all__U554.in1"], + ["add_all__U555.in0","add_all__U554.out"], + ["mul_d7__U547.out","add_all__U555.in1"], + ["add_all__U556.in0","add_all__U555.out"], + ["const_term_U548.out","add_all__U556.in1"], + ["self.out","add_all__U556.out"], + ["mul_d0__U533.in0","coeff_0_U532.out"], + ["mul_d1__U535.in0","coeff_1_U534.out"], + ["mul_d2__U537.in0","coeff_2_U536.out"], + ["mul_d3__U539.in0","coeff_3_U538.out"], + ["mul_d4__U541.in0","coeff_4_U540.out"], + ["mul_d5__U543.in0","coeff_5_U542.out"], + ["mul_d6__U545.in0","coeff_6_U544.out"], + ["mul_d7__U547.in0","coeff_7_U546.out"], + ["self.d.0","mul_d0__U533.in1"], + ["self.d.1","mul_d1__U535.in1"], + ["self.d.2","mul_d2__U537.in1"], + ["self.d.3","mul_d3__U539.in1"], + ["self.d.4","mul_d4__U541.in1"], + ["self.d.5","mul_d5__U543.in1"], + ["self.d.6","mul_d6__U545.in1"], + ["self.d.7","mul_d7__U547.in1"] ] }, - "aff__U642":{ + "aff__U559":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U652":{ + "add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U653":{ + "add_all__U570":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U654":{ + "add_all__U571":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U655":{ + "add_all__U572":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U643":{ + "coeff_0_U560":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U645":{ + "coeff_1_U562":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000700"]} }, - "coeff_2_U647":{ + "coeff_2_U564":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U649":{ + "coeff_3_U566":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U651":{ + "const_term_U568":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} }, - "mul_d0__U644":{ + "mul_d0__U561":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U646":{ + "mul_d1__U563":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U648":{ + "mul_d2__U565":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U650":{ + "mul_d3__U567":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U644.out","add_all__U652.in0"], - ["mul_d1__U646.out","add_all__U652.in1"], - ["add_all__U653.in0","add_all__U652.out"], - ["mul_d2__U648.out","add_all__U653.in1"], - ["add_all__U654.in0","add_all__U653.out"], - ["mul_d3__U650.out","add_all__U654.in1"], - ["add_all__U655.in0","add_all__U654.out"], - ["const_term_U651.out","add_all__U655.in1"], - ["self.out","add_all__U655.out"], - ["mul_d0__U644.in0","coeff_0_U643.out"], - ["mul_d1__U646.in0","coeff_1_U645.out"], - ["mul_d2__U648.in0","coeff_2_U647.out"], - ["mul_d3__U650.in0","coeff_3_U649.out"], - ["self.d.0","mul_d0__U644.in1"], - ["self.d.1","mul_d1__U646.in1"], - ["self.d.2","mul_d2__U648.in1"], - ["self.d.3","mul_d3__U650.in1"] + ["mul_d0__U561.out","add_all__U569.in0"], + ["mul_d1__U563.out","add_all__U569.in1"], + ["add_all__U570.in0","add_all__U569.out"], + ["mul_d2__U565.out","add_all__U570.in1"], + ["add_all__U571.in0","add_all__U570.out"], + ["mul_d3__U567.out","add_all__U571.in1"], + ["add_all__U572.in0","add_all__U571.out"], + ["const_term_U568.out","add_all__U572.in1"], + ["self.out","add_all__U572.out"], + ["mul_d0__U561.in0","coeff_0_U560.out"], + ["mul_d1__U563.in0","coeff_1_U562.out"], + ["mul_d2__U565.in0","coeff_2_U564.out"], + ["mul_d3__U567.in0","coeff_3_U566.out"], + ["self.d.0","mul_d0__U561.in1"], + ["self.d.1","mul_d1__U563.in1"], + ["self.d.2","mul_d2__U565.in1"], + ["self.d.3","mul_d3__U567.in1"] ] }, - "aff__U665":{ + "aff__U582":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U675":{ + "add_all__U592":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U676":{ + "add_all__U593":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U677":{ + "add_all__U594":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U678":{ + "add_all__U595":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U666":{ + "coeff_0_U583":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U668":{ + "coeff_1_U585":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U670":{ + "coeff_2_U587":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_3_U672":{ + "coeff_3_U589":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000310"]} }, - "const_term_U674":{ + "const_term_U591":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U667":{ + "mul_d0__U584":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U669":{ + "mul_d1__U586":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U671":{ + "mul_d2__U588":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U673":{ + "mul_d3__U590":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U667.out","add_all__U675.in0"], - ["mul_d1__U669.out","add_all__U675.in1"], - ["add_all__U676.in0","add_all__U675.out"], - ["mul_d2__U671.out","add_all__U676.in1"], - ["add_all__U677.in0","add_all__U676.out"], - ["mul_d3__U673.out","add_all__U677.in1"], - ["add_all__U678.in0","add_all__U677.out"], - ["const_term_U674.out","add_all__U678.in1"], - ["self.out","add_all__U678.out"], - ["mul_d0__U667.in0","coeff_0_U666.out"], - ["mul_d1__U669.in0","coeff_1_U668.out"], - ["mul_d2__U671.in0","coeff_2_U670.out"], - ["mul_d3__U673.in0","coeff_3_U672.out"], - ["self.d.0","mul_d0__U667.in1"], - ["self.d.1","mul_d1__U669.in1"], - ["self.d.2","mul_d2__U671.in1"], - ["self.d.3","mul_d3__U673.in1"] + ["mul_d0__U584.out","add_all__U592.in0"], + ["mul_d1__U586.out","add_all__U592.in1"], + ["add_all__U593.in0","add_all__U592.out"], + ["mul_d2__U588.out","add_all__U593.in1"], + ["add_all__U594.in0","add_all__U593.out"], + ["mul_d3__U590.out","add_all__U594.in1"], + ["add_all__U595.in0","add_all__U594.out"], + ["const_term_U591.out","add_all__U595.in1"], + ["self.out","add_all__U595.out"], + ["mul_d0__U584.in0","coeff_0_U583.out"], + ["mul_d1__U586.in0","coeff_1_U585.out"], + ["mul_d2__U588.in0","coeff_2_U587.out"], + ["mul_d3__U590.in0","coeff_3_U589.out"], + ["self.d.0","mul_d0__U584.in1"], + ["self.d.1","mul_d1__U586.in1"], + ["self.d.2","mul_d2__U588.in1"], + ["self.d.3","mul_d3__U590.in1"] ] }, - "aff__U682":{ + "aff__U599":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U692":{ + "add_all__U609":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U693":{ + "add_all__U610":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U694":{ + "add_all__U611":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U695":{ + "add_all__U612":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U683":{ + "coeff_0_U600":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U685":{ + "coeff_1_U602":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000700"]} }, - "coeff_2_U687":{ + "coeff_2_U604":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U689":{ + "coeff_3_U606":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U691":{ + "const_term_U608":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} }, - "mul_d0__U684":{ + "mul_d0__U601":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U686":{ + "mul_d1__U603":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U688":{ + "mul_d2__U605":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U690":{ + "mul_d3__U607":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U684.out","add_all__U692.in0"], - ["mul_d1__U686.out","add_all__U692.in1"], - ["add_all__U693.in0","add_all__U692.out"], - ["mul_d2__U688.out","add_all__U693.in1"], - ["add_all__U694.in0","add_all__U693.out"], - ["mul_d3__U690.out","add_all__U694.in1"], - ["add_all__U695.in0","add_all__U694.out"], - ["const_term_U691.out","add_all__U695.in1"], - ["self.out","add_all__U695.out"], - ["mul_d0__U684.in0","coeff_0_U683.out"], - ["mul_d1__U686.in0","coeff_1_U685.out"], - ["mul_d2__U688.in0","coeff_2_U687.out"], - ["mul_d3__U690.in0","coeff_3_U689.out"], - ["self.d.0","mul_d0__U684.in1"], - ["self.d.1","mul_d1__U686.in1"], - ["self.d.2","mul_d2__U688.in1"], - ["self.d.3","mul_d3__U690.in1"] + ["mul_d0__U601.out","add_all__U609.in0"], + ["mul_d1__U603.out","add_all__U609.in1"], + ["add_all__U610.in0","add_all__U609.out"], + ["mul_d2__U605.out","add_all__U610.in1"], + ["add_all__U611.in0","add_all__U610.out"], + ["mul_d3__U607.out","add_all__U611.in1"], + ["add_all__U612.in0","add_all__U611.out"], + ["const_term_U608.out","add_all__U612.in1"], + ["self.out","add_all__U612.out"], + ["mul_d0__U601.in0","coeff_0_U600.out"], + ["mul_d1__U603.in0","coeff_1_U602.out"], + ["mul_d2__U605.in0","coeff_2_U604.out"], + ["mul_d3__U607.in0","coeff_3_U606.out"], + ["self.d.0","mul_d0__U601.in1"], + ["self.d.1","mul_d1__U603.in1"], + ["self.d.2","mul_d2__U605.in1"], + ["self.d.3","mul_d3__U607.in1"] ] }, - "affine_controller__U17":{ + "aff__U9":{ "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], - ["rst_n","BitIn"] + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "_U32":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U33":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U18" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U34":{ - "modref":"corebit.and" - }, - "d_0_am__U35":{ - "modref":"corebit.and" - }, - "d_0_am__U36":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ + "add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", + "add_all__U20":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U37":{ - "modref":"corebit.and" - }, - "d_1_am__U38":{ - "modref":"corebit.and" - }, - "d_1_at_max":{ - "genref":"coreir.eq", + "add_all__U21":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} - }, - "d_1_min":{ + "coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U39":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ + "coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} + "modargs":{"value":[["BitVector",32],"32'h000003a0"]} }, - "d_2_min":{ + "coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "d_3_max":{ + "coeff_3_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_3_min":{ + "const_term_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ - "genref":"coreir.mux", + "mul_d0__U11":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", + "mul_d1__U13":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", + "mul_d2__U15":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} + "mul_d3__U17":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} } }, "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U32.out"], - ["d_2_inc.in1","_U32.out"], - ["d_3_inc.in1","_U32.out"], - ["cmp_time.in1","_U33.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U34.in0"], - ["d_1_at_max.out","d_0_am__U34.in1"], - ["d_0_am__U35.in0","d_0_am__U34.out"], - ["d_2_at_max.out","d_0_am__U35.in1"], - ["d_0_am__U36.in0","d_0_am__U35.out"], - ["d_3_at_max.out","d_0_am__U36.in1"], - ["d_0_next_value.sel","d_0_am__U36.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U37.in0"], - ["d_2_at_max.out","d_1_am__U37.in1"], - ["d_1_am__U38.in0","d_1_am__U37.out"], - ["d_3_at_max.out","d_1_am__U38.in1"], - ["d_1_next_value.sel","d_1_am__U38.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U39.in0"], - ["d_3_at_max.out","d_2_am__U39.in1"], - ["d_2_next_value.sel","d_2_am__U39.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U271":{ + "affine_controller__U197":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2278,18 +2012,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U289":{ + "_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U290":{ + "_U216":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U272" + "modref":"global.aff__U198" }, "cmp_time":{ "genref":"coreir.eq", @@ -2299,16 +2033,16 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U291":{ + "d_0_am__U217":{ "modref":"corebit.and" }, - "d_0_am__U292":{ + "d_0_am__U218":{ "modref":"corebit.and" }, - "d_0_am__U293":{ + "d_0_am__U219":{ "modref":"corebit.and" }, - "d_0_am__U294":{ + "d_0_am__U220":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2342,13 +2076,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U295":{ + "d_1_am__U221":{ "modref":"corebit.and" }, - "d_1_am__U296":{ + "d_1_am__U222":{ "modref":"corebit.and" }, - "d_1_am__U297":{ + "d_1_am__U223":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2382,10 +2116,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U298":{ + "d_2_am__U224":{ "modref":"corebit.and" }, - "d_2_am__U299":{ + "d_2_am__U225":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2419,7 +2153,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U300":{ + "d_3_am__U226":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2494,12 +2228,12 @@ } }, "connections":[ - ["d_0_inc.in1","_U289.out"], - ["d_1_inc.in1","_U289.out"], - ["d_2_inc.in1","_U289.out"], - ["d_3_inc.in1","_U289.out"], - ["d_4_inc.in1","_U289.out"], - ["cmp_time.in1","_U290.out"], + ["d_0_inc.in1","_U215.out"], + ["d_1_inc.in1","_U215.out"], + ["d_2_inc.in1","_U215.out"], + ["d_3_inc.in1","_U215.out"], + ["d_4_inc.in1","_U215.out"], + ["cmp_time.in1","_U216.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2516,15 +2250,15 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U291.in0"], - ["d_1_at_max.out","d_0_am__U291.in1"], - ["d_0_am__U292.in0","d_0_am__U291.out"], - ["d_2_at_max.out","d_0_am__U292.in1"], - ["d_0_am__U293.in0","d_0_am__U292.out"], - ["d_3_at_max.out","d_0_am__U293.in1"], - ["d_0_am__U294.in0","d_0_am__U293.out"], - ["d_4_at_max.out","d_0_am__U294.in1"], - ["d_0_next_value.sel","d_0_am__U294.out"], + ["true.out","d_0_am__U217.in0"], + ["d_1_at_max.out","d_0_am__U217.in1"], + ["d_0_am__U218.in0","d_0_am__U217.out"], + ["d_2_at_max.out","d_0_am__U218.in1"], + ["d_0_am__U219.in0","d_0_am__U218.out"], + ["d_3_at_max.out","d_0_am__U219.in1"], + ["d_0_am__U220.in0","d_0_am__U219.out"], + ["d_4_at_max.out","d_0_am__U220.in1"], + ["d_0_next_value.sel","d_0_am__U220.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2537,13 +2271,13 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U295.in0"], - ["d_2_at_max.out","d_1_am__U295.in1"], - ["d_1_am__U296.in0","d_1_am__U295.out"], - ["d_3_at_max.out","d_1_am__U296.in1"], - ["d_1_am__U297.in0","d_1_am__U296.out"], - ["d_4_at_max.out","d_1_am__U297.in1"], - ["d_1_next_value.sel","d_1_am__U297.out"], + ["true.out","d_1_am__U221.in0"], + ["d_2_at_max.out","d_1_am__U221.in1"], + ["d_1_am__U222.in0","d_1_am__U221.out"], + ["d_3_at_max.out","d_1_am__U222.in1"], + ["d_1_am__U223.in0","d_1_am__U222.out"], + ["d_4_at_max.out","d_1_am__U223.in1"], + ["d_1_next_value.sel","d_1_am__U223.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2556,11 +2290,11 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U298.in0"], - ["d_3_at_max.out","d_2_am__U298.in1"], - ["d_2_am__U299.in0","d_2_am__U298.out"], - ["d_4_at_max.out","d_2_am__U299.in1"], - ["d_2_next_value.sel","d_2_am__U299.out"], + ["true.out","d_2_am__U224.in0"], + ["d_3_at_max.out","d_2_am__U224.in1"], + ["d_2_am__U225.in0","d_2_am__U224.out"], + ["d_4_at_max.out","d_2_am__U225.in1"], + ["d_2_next_value.sel","d_2_am__U225.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2573,9 +2307,9 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U300.in0"], - ["d_4_at_max.out","d_3_am__U300.in1"], - ["d_3_next_value.sel","d_3_am__U300.out"], + ["true.out","d_3_am__U226.in0"], + ["d_4_at_max.out","d_3_am__U226.in1"], + ["d_3_next_value.sel","d_3_am__U226.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2603,7 +2337,7 @@ ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U320":{ + "affine_controller__U246":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2611,18 +2345,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U353":{ + "_U279":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U354":{ + "_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U321" + "modref":"global.aff__U247" }, "cmp_time":{ "genref":"coreir.eq", @@ -2632,31 +2366,31 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U355":{ + "d_0_am__U281":{ "modref":"corebit.and" }, - "d_0_am__U356":{ + "d_0_am__U282":{ "modref":"corebit.and" }, - "d_0_am__U357":{ + "d_0_am__U283":{ "modref":"corebit.and" }, - "d_0_am__U358":{ + "d_0_am__U284":{ "modref":"corebit.and" }, - "d_0_am__U359":{ + "d_0_am__U285":{ "modref":"corebit.and" }, - "d_0_am__U360":{ + "d_0_am__U286":{ "modref":"corebit.and" }, - "d_0_am__U361":{ + "d_0_am__U287":{ "modref":"corebit.and" }, - "d_0_am__U362":{ + "d_0_am__U288":{ "modref":"corebit.and" }, - "d_0_am__U363":{ + "d_0_am__U289":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2690,28 +2424,28 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U364":{ + "d_1_am__U290":{ "modref":"corebit.and" }, - "d_1_am__U365":{ + "d_1_am__U291":{ "modref":"corebit.and" }, - "d_1_am__U366":{ + "d_1_am__U292":{ "modref":"corebit.and" }, - "d_1_am__U367":{ + "d_1_am__U293":{ "modref":"corebit.and" }, - "d_1_am__U368":{ + "d_1_am__U294":{ "modref":"corebit.and" }, - "d_1_am__U369":{ + "d_1_am__U295":{ "modref":"corebit.and" }, - "d_1_am__U370":{ + "d_1_am__U296":{ "modref":"corebit.and" }, - "d_1_am__U371":{ + "d_1_am__U297":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2745,25 +2479,25 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U372":{ + "d_2_am__U298":{ "modref":"corebit.and" }, - "d_2_am__U373":{ + "d_2_am__U299":{ "modref":"corebit.and" }, - "d_2_am__U374":{ + "d_2_am__U300":{ "modref":"corebit.and" }, - "d_2_am__U375":{ + "d_2_am__U301":{ "modref":"corebit.and" }, - "d_2_am__U376":{ + "d_2_am__U302":{ "modref":"corebit.and" }, - "d_2_am__U377":{ + "d_2_am__U303":{ "modref":"corebit.and" }, - "d_2_am__U378":{ + "d_2_am__U304":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2797,22 +2531,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U379":{ + "d_3_am__U305":{ "modref":"corebit.and" }, - "d_3_am__U380":{ + "d_3_am__U306":{ "modref":"corebit.and" }, - "d_3_am__U381":{ + "d_3_am__U307":{ "modref":"corebit.and" }, - "d_3_am__U382":{ + "d_3_am__U308":{ "modref":"corebit.and" }, - "d_3_am__U383":{ + "d_3_am__U309":{ "modref":"corebit.and" }, - "d_3_am__U384":{ + "d_3_am__U310":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2846,19 +2580,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U385":{ + "d_4_am__U311":{ "modref":"corebit.and" }, - "d_4_am__U386":{ + "d_4_am__U312":{ "modref":"corebit.and" }, - "d_4_am__U387":{ + "d_4_am__U313":{ "modref":"corebit.and" }, - "d_4_am__U388":{ + "d_4_am__U314":{ "modref":"corebit.and" }, - "d_4_am__U389":{ + "d_4_am__U315":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2892,16 +2626,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U390":{ + "d_5_am__U316":{ "modref":"corebit.and" }, - "d_5_am__U391":{ + "d_5_am__U317":{ "modref":"corebit.and" }, - "d_5_am__U392":{ + "d_5_am__U318":{ "modref":"corebit.and" }, - "d_5_am__U393":{ + "d_5_am__U319":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -2935,13 +2669,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U394":{ + "d_6_am__U320":{ "modref":"corebit.and" }, - "d_6_am__U395":{ + "d_6_am__U321":{ "modref":"corebit.and" }, - "d_6_am__U396":{ + "d_6_am__U322":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -2975,10 +2709,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_7_am__U397":{ + "d_7_am__U323":{ "modref":"corebit.and" }, - "d_7_am__U398":{ + "d_7_am__U324":{ "modref":"corebit.and" }, "d_7_at_max":{ @@ -3012,7 +2746,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_8_am__U399":{ + "d_8_am__U325":{ "modref":"corebit.and" }, "d_8_at_max":{ @@ -3087,17 +2821,17 @@ } }, "connections":[ - ["d_0_inc.in1","_U353.out"], - ["d_1_inc.in1","_U353.out"], - ["d_2_inc.in1","_U353.out"], - ["d_3_inc.in1","_U353.out"], - ["d_4_inc.in1","_U353.out"], - ["d_5_inc.in1","_U353.out"], - ["d_6_inc.in1","_U353.out"], - ["d_7_inc.in1","_U353.out"], - ["d_8_inc.in1","_U353.out"], - ["d_9_inc.in1","_U353.out"], - ["cmp_time.in1","_U354.out"], + ["d_0_inc.in1","_U279.out"], + ["d_1_inc.in1","_U279.out"], + ["d_2_inc.in1","_U279.out"], + ["d_3_inc.in1","_U279.out"], + ["d_4_inc.in1","_U279.out"], + ["d_5_inc.in1","_U279.out"], + ["d_6_inc.in1","_U279.out"], + ["d_7_inc.in1","_U279.out"], + ["d_8_inc.in1","_U279.out"], + ["d_9_inc.in1","_U279.out"], + ["cmp_time.in1","_U280.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3124,25 +2858,25 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U355.in0"], - ["d_1_at_max.out","d_0_am__U355.in1"], - ["d_0_am__U356.in0","d_0_am__U355.out"], - ["d_2_at_max.out","d_0_am__U356.in1"], - ["d_0_am__U357.in0","d_0_am__U356.out"], - ["d_3_at_max.out","d_0_am__U357.in1"], - ["d_0_am__U358.in0","d_0_am__U357.out"], - ["d_4_at_max.out","d_0_am__U358.in1"], - ["d_0_am__U359.in0","d_0_am__U358.out"], - ["d_5_at_max.out","d_0_am__U359.in1"], - ["d_0_am__U360.in0","d_0_am__U359.out"], - ["d_6_at_max.out","d_0_am__U360.in1"], - ["d_0_am__U361.in0","d_0_am__U360.out"], - ["d_7_at_max.out","d_0_am__U361.in1"], - ["d_0_am__U362.in0","d_0_am__U361.out"], - ["d_8_at_max.out","d_0_am__U362.in1"], - ["d_0_am__U363.in0","d_0_am__U362.out"], - ["d_9_at_max.out","d_0_am__U363.in1"], - ["d_0_next_value.sel","d_0_am__U363.out"], + ["true.out","d_0_am__U281.in0"], + ["d_1_at_max.out","d_0_am__U281.in1"], + ["d_0_am__U282.in0","d_0_am__U281.out"], + ["d_2_at_max.out","d_0_am__U282.in1"], + ["d_0_am__U283.in0","d_0_am__U282.out"], + ["d_3_at_max.out","d_0_am__U283.in1"], + ["d_0_am__U284.in0","d_0_am__U283.out"], + ["d_4_at_max.out","d_0_am__U284.in1"], + ["d_0_am__U285.in0","d_0_am__U284.out"], + ["d_5_at_max.out","d_0_am__U285.in1"], + ["d_0_am__U286.in0","d_0_am__U285.out"], + ["d_6_at_max.out","d_0_am__U286.in1"], + ["d_0_am__U287.in0","d_0_am__U286.out"], + ["d_7_at_max.out","d_0_am__U287.in1"], + ["d_0_am__U288.in0","d_0_am__U287.out"], + ["d_8_at_max.out","d_0_am__U288.in1"], + ["d_0_am__U289.in0","d_0_am__U288.out"], + ["d_9_at_max.out","d_0_am__U289.in1"], + ["d_0_next_value.sel","d_0_am__U289.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3155,23 +2889,23 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U364.in0"], - ["d_2_at_max.out","d_1_am__U364.in1"], - ["d_1_am__U365.in0","d_1_am__U364.out"], - ["d_3_at_max.out","d_1_am__U365.in1"], - ["d_1_am__U366.in0","d_1_am__U365.out"], - ["d_4_at_max.out","d_1_am__U366.in1"], - ["d_1_am__U367.in0","d_1_am__U366.out"], - ["d_5_at_max.out","d_1_am__U367.in1"], - ["d_1_am__U368.in0","d_1_am__U367.out"], - ["d_6_at_max.out","d_1_am__U368.in1"], - ["d_1_am__U369.in0","d_1_am__U368.out"], - ["d_7_at_max.out","d_1_am__U369.in1"], - ["d_1_am__U370.in0","d_1_am__U369.out"], - ["d_8_at_max.out","d_1_am__U370.in1"], - ["d_1_am__U371.in0","d_1_am__U370.out"], - ["d_9_at_max.out","d_1_am__U371.in1"], - ["d_1_next_value.sel","d_1_am__U371.out"], + ["true.out","d_1_am__U290.in0"], + ["d_2_at_max.out","d_1_am__U290.in1"], + ["d_1_am__U291.in0","d_1_am__U290.out"], + ["d_3_at_max.out","d_1_am__U291.in1"], + ["d_1_am__U292.in0","d_1_am__U291.out"], + ["d_4_at_max.out","d_1_am__U292.in1"], + ["d_1_am__U293.in0","d_1_am__U292.out"], + ["d_5_at_max.out","d_1_am__U293.in1"], + ["d_1_am__U294.in0","d_1_am__U293.out"], + ["d_6_at_max.out","d_1_am__U294.in1"], + ["d_1_am__U295.in0","d_1_am__U294.out"], + ["d_7_at_max.out","d_1_am__U295.in1"], + ["d_1_am__U296.in0","d_1_am__U295.out"], + ["d_8_at_max.out","d_1_am__U296.in1"], + ["d_1_am__U297.in0","d_1_am__U296.out"], + ["d_9_at_max.out","d_1_am__U297.in1"], + ["d_1_next_value.sel","d_1_am__U297.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3184,21 +2918,21 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U372.in0"], - ["d_3_at_max.out","d_2_am__U372.in1"], - ["d_2_am__U373.in0","d_2_am__U372.out"], - ["d_4_at_max.out","d_2_am__U373.in1"], - ["d_2_am__U374.in0","d_2_am__U373.out"], - ["d_5_at_max.out","d_2_am__U374.in1"], - ["d_2_am__U375.in0","d_2_am__U374.out"], - ["d_6_at_max.out","d_2_am__U375.in1"], - ["d_2_am__U376.in0","d_2_am__U375.out"], - ["d_7_at_max.out","d_2_am__U376.in1"], - ["d_2_am__U377.in0","d_2_am__U376.out"], - ["d_8_at_max.out","d_2_am__U377.in1"], - ["d_2_am__U378.in0","d_2_am__U377.out"], - ["d_9_at_max.out","d_2_am__U378.in1"], - ["d_2_next_value.sel","d_2_am__U378.out"], + ["true.out","d_2_am__U298.in0"], + ["d_3_at_max.out","d_2_am__U298.in1"], + ["d_2_am__U299.in0","d_2_am__U298.out"], + ["d_4_at_max.out","d_2_am__U299.in1"], + ["d_2_am__U300.in0","d_2_am__U299.out"], + ["d_5_at_max.out","d_2_am__U300.in1"], + ["d_2_am__U301.in0","d_2_am__U300.out"], + ["d_6_at_max.out","d_2_am__U301.in1"], + ["d_2_am__U302.in0","d_2_am__U301.out"], + ["d_7_at_max.out","d_2_am__U302.in1"], + ["d_2_am__U303.in0","d_2_am__U302.out"], + ["d_8_at_max.out","d_2_am__U303.in1"], + ["d_2_am__U304.in0","d_2_am__U303.out"], + ["d_9_at_max.out","d_2_am__U304.in1"], + ["d_2_next_value.sel","d_2_am__U304.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3211,19 +2945,19 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U379.in0"], - ["d_4_at_max.out","d_3_am__U379.in1"], - ["d_3_am__U380.in0","d_3_am__U379.out"], - ["d_5_at_max.out","d_3_am__U380.in1"], - ["d_3_am__U381.in0","d_3_am__U380.out"], - ["d_6_at_max.out","d_3_am__U381.in1"], - ["d_3_am__U382.in0","d_3_am__U381.out"], - ["d_7_at_max.out","d_3_am__U382.in1"], - ["d_3_am__U383.in0","d_3_am__U382.out"], - ["d_8_at_max.out","d_3_am__U383.in1"], - ["d_3_am__U384.in0","d_3_am__U383.out"], - ["d_9_at_max.out","d_3_am__U384.in1"], - ["d_3_next_value.sel","d_3_am__U384.out"], + ["true.out","d_3_am__U305.in0"], + ["d_4_at_max.out","d_3_am__U305.in1"], + ["d_3_am__U306.in0","d_3_am__U305.out"], + ["d_5_at_max.out","d_3_am__U306.in1"], + ["d_3_am__U307.in0","d_3_am__U306.out"], + ["d_6_at_max.out","d_3_am__U307.in1"], + ["d_3_am__U308.in0","d_3_am__U307.out"], + ["d_7_at_max.out","d_3_am__U308.in1"], + ["d_3_am__U309.in0","d_3_am__U308.out"], + ["d_8_at_max.out","d_3_am__U309.in1"], + ["d_3_am__U310.in0","d_3_am__U309.out"], + ["d_9_at_max.out","d_3_am__U310.in1"], + ["d_3_next_value.sel","d_3_am__U310.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3236,17 +2970,17 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U385.in0"], - ["d_5_at_max.out","d_4_am__U385.in1"], - ["d_4_am__U386.in0","d_4_am__U385.out"], - ["d_6_at_max.out","d_4_am__U386.in1"], - ["d_4_am__U387.in0","d_4_am__U386.out"], - ["d_7_at_max.out","d_4_am__U387.in1"], - ["d_4_am__U388.in0","d_4_am__U387.out"], - ["d_8_at_max.out","d_4_am__U388.in1"], - ["d_4_am__U389.in0","d_4_am__U388.out"], - ["d_9_at_max.out","d_4_am__U389.in1"], - ["d_4_next_value.sel","d_4_am__U389.out"], + ["true.out","d_4_am__U311.in0"], + ["d_5_at_max.out","d_4_am__U311.in1"], + ["d_4_am__U312.in0","d_4_am__U311.out"], + ["d_6_at_max.out","d_4_am__U312.in1"], + ["d_4_am__U313.in0","d_4_am__U312.out"], + ["d_7_at_max.out","d_4_am__U313.in1"], + ["d_4_am__U314.in0","d_4_am__U313.out"], + ["d_8_at_max.out","d_4_am__U314.in1"], + ["d_4_am__U315.in0","d_4_am__U314.out"], + ["d_9_at_max.out","d_4_am__U315.in1"], + ["d_4_next_value.sel","d_4_am__U315.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3259,15 +2993,15 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U390.in0"], - ["d_6_at_max.out","d_5_am__U390.in1"], - ["d_5_am__U391.in0","d_5_am__U390.out"], - ["d_7_at_max.out","d_5_am__U391.in1"], - ["d_5_am__U392.in0","d_5_am__U391.out"], - ["d_8_at_max.out","d_5_am__U392.in1"], - ["d_5_am__U393.in0","d_5_am__U392.out"], - ["d_9_at_max.out","d_5_am__U393.in1"], - ["d_5_next_value.sel","d_5_am__U393.out"], + ["true.out","d_5_am__U316.in0"], + ["d_6_at_max.out","d_5_am__U316.in1"], + ["d_5_am__U317.in0","d_5_am__U316.out"], + ["d_7_at_max.out","d_5_am__U317.in1"], + ["d_5_am__U318.in0","d_5_am__U317.out"], + ["d_8_at_max.out","d_5_am__U318.in1"], + ["d_5_am__U319.in0","d_5_am__U318.out"], + ["d_9_at_max.out","d_5_am__U319.in1"], + ["d_5_next_value.sel","d_5_am__U319.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -3280,13 +3014,13 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U394.in0"], - ["d_7_at_max.out","d_6_am__U394.in1"], - ["d_6_am__U395.in0","d_6_am__U394.out"], - ["d_8_at_max.out","d_6_am__U395.in1"], - ["d_6_am__U396.in0","d_6_am__U395.out"], - ["d_9_at_max.out","d_6_am__U396.in1"], - ["d_6_next_value.sel","d_6_am__U396.out"], + ["true.out","d_6_am__U320.in0"], + ["d_7_at_max.out","d_6_am__U320.in1"], + ["d_6_am__U321.in0","d_6_am__U320.out"], + ["d_8_at_max.out","d_6_am__U321.in1"], + ["d_6_am__U322.in0","d_6_am__U321.out"], + ["d_9_at_max.out","d_6_am__U322.in1"], + ["d_6_next_value.sel","d_6_am__U322.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -3299,11 +3033,11 @@ ["self.clk","d_6_reg.clk"], ["self.rst_n","d_6_reg.clr"], ["self.d.6","d_6_reg.out"], - ["true.out","d_7_am__U397.in0"], - ["d_8_at_max.out","d_7_am__U397.in1"], - ["d_7_am__U398.in0","d_7_am__U397.out"], - ["d_9_at_max.out","d_7_am__U398.in1"], - ["d_7_next_value.sel","d_7_am__U398.out"], + ["true.out","d_7_am__U323.in0"], + ["d_8_at_max.out","d_7_am__U323.in1"], + ["d_7_am__U324.in0","d_7_am__U323.out"], + ["d_9_at_max.out","d_7_am__U324.in1"], + ["d_7_next_value.sel","d_7_am__U324.out"], ["d_7_reg.out","d_7_at_max.in0"], ["d_7_max.out","d_7_at_max.in1"], ["d_7_next_value_at_max.sel","d_7_at_max.out"], @@ -3316,9 +3050,9 @@ ["self.clk","d_7_reg.clk"], ["self.rst_n","d_7_reg.clr"], ["self.d.7","d_7_reg.out"], - ["true.out","d_8_am__U399.in0"], - ["d_9_at_max.out","d_8_am__U399.in1"], - ["d_8_next_value.sel","d_8_am__U399.out"], + ["true.out","d_8_am__U325.in0"], + ["d_9_at_max.out","d_8_am__U325.in1"], + ["d_8_next_value.sel","d_8_am__U325.out"], ["d_8_reg.out","d_8_at_max.in0"], ["d_8_max.out","d_8_at_max.in1"], ["d_8_next_value_at_max.sel","d_8_at_max.out"], @@ -3346,7 +3080,7 @@ ["self.d.9","d_9_reg.out"] ] }, - "affine_controller__U436":{ + "affine_controller__U362":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3354,18 +3088,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U445":{ + "_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U446":{ + "_U372":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U437" + "modref":"global.aff__U363" }, "cmp_time":{ "genref":"coreir.eq", @@ -3375,7 +3109,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U447":{ + "d_0_am__U373":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3450,9 +3184,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U445.out"], - ["d_1_inc.in1","_U445.out"], - ["cmp_time.in1","_U446.out"], + ["d_0_inc.in1","_U371.out"], + ["d_1_inc.in1","_U371.out"], + ["cmp_time.in1","_U372.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3463,9 +3197,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U447.in0"], - ["d_1_at_max.out","d_0_am__U447.in1"], - ["d_0_next_value.sel","d_0_am__U447.out"], + ["true.out","d_0_am__U373.in0"], + ["d_1_at_max.out","d_0_am__U373.in1"], + ["d_0_next_value.sel","d_0_am__U373.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3493,7 +3227,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U451":{ + "affine_controller__U376":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3501,18 +3235,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U460":{ + "_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U461":{ + "_U386":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U452" + "modref":"global.aff__U377" }, "cmp_time":{ "genref":"coreir.eq", @@ -3522,7 +3256,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U462":{ + "d_0_am__U387":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3597,9 +3331,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U460.out"], - ["d_1_inc.in1","_U460.out"], - ["cmp_time.in1","_U461.out"], + ["d_0_inc.in1","_U385.out"], + ["d_1_inc.in1","_U385.out"], + ["cmp_time.in1","_U386.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3610,9 +3344,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U462.in0"], - ["d_1_at_max.out","d_0_am__U462.in1"], - ["d_0_next_value.sel","d_0_am__U462.out"], + ["true.out","d_0_am__U387.in0"], + ["d_1_at_max.out","d_0_am__U387.in1"], + ["d_0_next_value.sel","d_0_am__U387.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3640,7 +3374,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U466":{ + "affine_controller__U390":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3648,18 +3382,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U475":{ + "_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U476":{ + "_U400":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U467" + "modref":"global.aff__U391" }, "cmp_time":{ "genref":"coreir.eq", @@ -3669,7 +3403,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U477":{ + "d_0_am__U401":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3744,9 +3478,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U475.out"], - ["d_1_inc.in1","_U475.out"], - ["cmp_time.in1","_U476.out"], + ["d_0_inc.in1","_U399.out"], + ["d_1_inc.in1","_U399.out"], + ["cmp_time.in1","_U400.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3757,9 +3491,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U477.in0"], - ["d_1_at_max.out","d_0_am__U477.in1"], - ["d_0_next_value.sel","d_0_am__U477.out"], + ["true.out","d_0_am__U401.in0"], + ["d_1_at_max.out","d_0_am__U401.in1"], + ["d_0_next_value.sel","d_0_am__U401.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3787,7 +3521,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U481":{ + "affine_controller__U404":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3795,18 +3529,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U490":{ + "_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U491":{ + "_U414":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U482" + "modref":"global.aff__U405" }, "cmp_time":{ "genref":"coreir.eq", @@ -3816,7 +3550,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U492":{ + "d_0_am__U415":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3891,9 +3625,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U490.out"], - ["d_1_inc.in1","_U490.out"], - ["cmp_time.in1","_U491.out"], + ["d_0_inc.in1","_U413.out"], + ["d_1_inc.in1","_U413.out"], + ["cmp_time.in1","_U414.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3904,9 +3638,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U492.in0"], - ["d_1_at_max.out","d_0_am__U492.in1"], - ["d_0_next_value.sel","d_0_am__U492.out"], + ["true.out","d_0_am__U415.in0"], + ["d_1_at_max.out","d_0_am__U415.in1"], + ["d_0_next_value.sel","d_0_am__U415.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3934,7 +3668,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U496":{ + "affine_controller__U418":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3942,18 +3676,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U505":{ + "_U427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U506":{ + "_U428":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U497" + "modref":"global.aff__U419" }, "cmp_time":{ "genref":"coreir.eq", @@ -3963,7 +3697,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U507":{ + "d_0_am__U429":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4038,9 +3772,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U505.out"], - ["d_1_inc.in1","_U505.out"], - ["cmp_time.in1","_U506.out"], + ["d_0_inc.in1","_U427.out"], + ["d_1_inc.in1","_U427.out"], + ["cmp_time.in1","_U428.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -4051,9 +3785,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U507.in0"], - ["d_1_at_max.out","d_0_am__U507.in1"], - ["d_0_next_value.sel","d_0_am__U507.out"], + ["true.out","d_0_am__U429.in0"], + ["d_1_at_max.out","d_0_am__U429.in1"], + ["d_0_next_value.sel","d_0_am__U429.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4081,7 +3815,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U511":{ + "affine_controller__U432":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4089,18 +3823,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U520":{ + "_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U521":{ + "_U442":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U512" + "modref":"global.aff__U433" }, "cmp_time":{ "genref":"coreir.eq", @@ -4110,7 +3844,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U522":{ + "d_0_am__U443":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4185,9 +3919,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U520.out"], - ["d_1_inc.in1","_U520.out"], - ["cmp_time.in1","_U521.out"], + ["d_0_inc.in1","_U441.out"], + ["d_1_inc.in1","_U441.out"], + ["cmp_time.in1","_U442.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -4198,9 +3932,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U522.in0"], - ["d_1_at_max.out","d_0_am__U522.in1"], - ["d_0_next_value.sel","d_0_am__U522.out"], + ["true.out","d_0_am__U443.in0"], + ["d_1_at_max.out","d_0_am__U443.in1"], + ["d_0_next_value.sel","d_0_am__U443.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4228,7 +3962,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U526":{ + "affine_controller__U446":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4236,18 +3970,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U535":{ + "_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U536":{ + "_U456":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U527" + "modref":"global.aff__U447" }, "cmp_time":{ "genref":"coreir.eq", @@ -4257,7 +3991,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U537":{ + "d_0_am__U457":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4332,9 +4066,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U535.out"], - ["d_1_inc.in1","_U535.out"], - ["cmp_time.in1","_U536.out"], + ["d_0_inc.in1","_U455.out"], + ["d_1_inc.in1","_U455.out"], + ["cmp_time.in1","_U456.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -4345,9 +4079,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U537.in0"], - ["d_1_at_max.out","d_0_am__U537.in1"], - ["d_0_next_value.sel","d_0_am__U537.out"], + ["true.out","d_0_am__U457.in0"], + ["d_1_at_max.out","d_0_am__U457.in1"], + ["d_0_next_value.sel","d_0_am__U457.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4375,7 +4109,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U541":{ + "affine_controller__U460":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4383,18 +4117,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U550":{ + "_U469":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U551":{ + "_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U542" + "modref":"global.aff__U461" }, "cmp_time":{ "genref":"coreir.eq", @@ -4404,7 +4138,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U552":{ + "d_0_am__U471":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4479,9 +4213,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U550.out"], - ["d_1_inc.in1","_U550.out"], - ["cmp_time.in1","_U551.out"], + ["d_0_inc.in1","_U469.out"], + ["d_1_inc.in1","_U469.out"], + ["cmp_time.in1","_U470.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -4492,9 +4226,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U552.in0"], - ["d_1_at_max.out","d_0_am__U552.in1"], - ["d_0_next_value.sel","d_0_am__U552.out"], + ["true.out","d_0_am__U471.in0"], + ["d_1_at_max.out","d_0_am__U471.in1"], + ["d_0_next_value.sel","d_0_am__U471.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4522,7 +4256,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U556":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4530,18 +4264,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U583":{ + "_U74":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U584":{ + "_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U557" + "modref":"global.aff__U48" }, "cmp_time":{ "genref":"coreir.eq", @@ -4551,25 +4285,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U585":{ + "d_0_am__U76":{ "modref":"corebit.and" }, - "d_0_am__U586":{ + "d_0_am__U77":{ "modref":"corebit.and" }, - "d_0_am__U587":{ + "d_0_am__U78":{ "modref":"corebit.and" }, - "d_0_am__U588":{ + "d_0_am__U79":{ "modref":"corebit.and" }, - "d_0_am__U589":{ + "d_0_am__U80":{ "modref":"corebit.and" }, - "d_0_am__U590":{ + "d_0_am__U81":{ "modref":"corebit.and" }, - "d_0_am__U591":{ + "d_0_am__U82":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4603,22 +4337,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U592":{ + "d_1_am__U83":{ "modref":"corebit.and" }, - "d_1_am__U593":{ + "d_1_am__U84":{ "modref":"corebit.and" }, - "d_1_am__U594":{ + "d_1_am__U85":{ "modref":"corebit.and" }, - "d_1_am__U595":{ + "d_1_am__U86":{ "modref":"corebit.and" }, - "d_1_am__U596":{ + "d_1_am__U87":{ "modref":"corebit.and" }, - "d_1_am__U597":{ + "d_1_am__U88":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -4652,19 +4386,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U598":{ + "d_2_am__U89":{ "modref":"corebit.and" }, - "d_2_am__U599":{ + "d_2_am__U90":{ "modref":"corebit.and" }, - "d_2_am__U600":{ + "d_2_am__U91":{ "modref":"corebit.and" }, - "d_2_am__U601":{ + "d_2_am__U92":{ "modref":"corebit.and" }, - "d_2_am__U602":{ + "d_2_am__U93":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -4698,16 +4432,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U603":{ + "d_3_am__U94":{ "modref":"corebit.and" }, - "d_3_am__U604":{ + "d_3_am__U95":{ "modref":"corebit.and" }, - "d_3_am__U605":{ + "d_3_am__U96":{ "modref":"corebit.and" }, - "d_3_am__U606":{ + "d_3_am__U97":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -4741,13 +4475,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U607":{ + "d_4_am__U100":{ "modref":"corebit.and" }, - "d_4_am__U608":{ + "d_4_am__U98":{ "modref":"corebit.and" }, - "d_4_am__U609":{ + "d_4_am__U99":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -4761,7 +4495,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_4_min":{ "genref":"coreir.const", @@ -4781,10 +4515,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U610":{ + "d_5_am__U101":{ "modref":"corebit.and" }, - "d_5_am__U611":{ + "d_5_am__U102":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -4798,7 +4532,7 @@ "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + "modargs":{"value":[["BitVector",32],"32'h0000001d"]} }, "d_5_min":{ "genref":"coreir.const", @@ -4818,7 +4552,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U612":{ + "d_6_am__U103":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -4832,7 +4566,7 @@ "d_6_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h0000001d"]} }, "d_6_min":{ "genref":"coreir.const", @@ -4893,15 +4627,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U583.out"], - ["d_1_inc.in1","_U583.out"], - ["d_2_inc.in1","_U583.out"], - ["d_3_inc.in1","_U583.out"], - ["d_4_inc.in1","_U583.out"], - ["d_5_inc.in1","_U583.out"], - ["d_6_inc.in1","_U583.out"], - ["d_7_inc.in1","_U583.out"], - ["cmp_time.in1","_U584.out"], + ["d_0_inc.in1","_U74.out"], + ["d_1_inc.in1","_U74.out"], + ["d_2_inc.in1","_U74.out"], + ["d_3_inc.in1","_U74.out"], + ["d_4_inc.in1","_U74.out"], + ["d_5_inc.in1","_U74.out"], + ["d_6_inc.in1","_U74.out"], + ["d_7_inc.in1","_U74.out"], + ["cmp_time.in1","_U75.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -4924,21 +4658,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U585.in0"], - ["d_1_at_max.out","d_0_am__U585.in1"], - ["d_0_am__U586.in0","d_0_am__U585.out"], - ["d_2_at_max.out","d_0_am__U586.in1"], - ["d_0_am__U587.in0","d_0_am__U586.out"], - ["d_3_at_max.out","d_0_am__U587.in1"], - ["d_0_am__U588.in0","d_0_am__U587.out"], - ["d_4_at_max.out","d_0_am__U588.in1"], - ["d_0_am__U589.in0","d_0_am__U588.out"], - ["d_5_at_max.out","d_0_am__U589.in1"], - ["d_0_am__U590.in0","d_0_am__U589.out"], - ["d_6_at_max.out","d_0_am__U590.in1"], - ["d_0_am__U591.in0","d_0_am__U590.out"], - ["d_7_at_max.out","d_0_am__U591.in1"], - ["d_0_next_value.sel","d_0_am__U591.out"], + ["true.out","d_0_am__U76.in0"], + ["d_1_at_max.out","d_0_am__U76.in1"], + ["d_0_am__U77.in0","d_0_am__U76.out"], + ["d_2_at_max.out","d_0_am__U77.in1"], + ["d_0_am__U78.in0","d_0_am__U77.out"], + ["d_3_at_max.out","d_0_am__U78.in1"], + ["d_0_am__U79.in0","d_0_am__U78.out"], + ["d_4_at_max.out","d_0_am__U79.in1"], + ["d_0_am__U80.in0","d_0_am__U79.out"], + ["d_5_at_max.out","d_0_am__U80.in1"], + ["d_0_am__U81.in0","d_0_am__U80.out"], + ["d_6_at_max.out","d_0_am__U81.in1"], + ["d_0_am__U82.in0","d_0_am__U81.out"], + ["d_7_at_max.out","d_0_am__U82.in1"], + ["d_0_next_value.sel","d_0_am__U82.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4951,19 +4685,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U592.in0"], - ["d_2_at_max.out","d_1_am__U592.in1"], - ["d_1_am__U593.in0","d_1_am__U592.out"], - ["d_3_at_max.out","d_1_am__U593.in1"], - ["d_1_am__U594.in0","d_1_am__U593.out"], - ["d_4_at_max.out","d_1_am__U594.in1"], - ["d_1_am__U595.in0","d_1_am__U594.out"], - ["d_5_at_max.out","d_1_am__U595.in1"], - ["d_1_am__U596.in0","d_1_am__U595.out"], - ["d_6_at_max.out","d_1_am__U596.in1"], - ["d_1_am__U597.in0","d_1_am__U596.out"], - ["d_7_at_max.out","d_1_am__U597.in1"], - ["d_1_next_value.sel","d_1_am__U597.out"], + ["true.out","d_1_am__U83.in0"], + ["d_2_at_max.out","d_1_am__U83.in1"], + ["d_1_am__U84.in0","d_1_am__U83.out"], + ["d_3_at_max.out","d_1_am__U84.in1"], + ["d_1_am__U85.in0","d_1_am__U84.out"], + ["d_4_at_max.out","d_1_am__U85.in1"], + ["d_1_am__U86.in0","d_1_am__U85.out"], + ["d_5_at_max.out","d_1_am__U86.in1"], + ["d_1_am__U87.in0","d_1_am__U86.out"], + ["d_6_at_max.out","d_1_am__U87.in1"], + ["d_1_am__U88.in0","d_1_am__U87.out"], + ["d_7_at_max.out","d_1_am__U88.in1"], + ["d_1_next_value.sel","d_1_am__U88.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4976,17 +4710,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U598.in0"], - ["d_3_at_max.out","d_2_am__U598.in1"], - ["d_2_am__U599.in0","d_2_am__U598.out"], - ["d_4_at_max.out","d_2_am__U599.in1"], - ["d_2_am__U600.in0","d_2_am__U599.out"], - ["d_5_at_max.out","d_2_am__U600.in1"], - ["d_2_am__U601.in0","d_2_am__U600.out"], - ["d_6_at_max.out","d_2_am__U601.in1"], - ["d_2_am__U602.in0","d_2_am__U601.out"], - ["d_7_at_max.out","d_2_am__U602.in1"], - ["d_2_next_value.sel","d_2_am__U602.out"], + ["true.out","d_2_am__U89.in0"], + ["d_3_at_max.out","d_2_am__U89.in1"], + ["d_2_am__U90.in0","d_2_am__U89.out"], + ["d_4_at_max.out","d_2_am__U90.in1"], + ["d_2_am__U91.in0","d_2_am__U90.out"], + ["d_5_at_max.out","d_2_am__U91.in1"], + ["d_2_am__U92.in0","d_2_am__U91.out"], + ["d_6_at_max.out","d_2_am__U92.in1"], + ["d_2_am__U93.in0","d_2_am__U92.out"], + ["d_7_at_max.out","d_2_am__U93.in1"], + ["d_2_next_value.sel","d_2_am__U93.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4999,15 +4733,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U603.in0"], - ["d_4_at_max.out","d_3_am__U603.in1"], - ["d_3_am__U604.in0","d_3_am__U603.out"], - ["d_5_at_max.out","d_3_am__U604.in1"], - ["d_3_am__U605.in0","d_3_am__U604.out"], - ["d_6_at_max.out","d_3_am__U605.in1"], - ["d_3_am__U606.in0","d_3_am__U605.out"], - ["d_7_at_max.out","d_3_am__U606.in1"], - ["d_3_next_value.sel","d_3_am__U606.out"], + ["true.out","d_3_am__U94.in0"], + ["d_4_at_max.out","d_3_am__U94.in1"], + ["d_3_am__U95.in0","d_3_am__U94.out"], + ["d_5_at_max.out","d_3_am__U95.in1"], + ["d_3_am__U96.in0","d_3_am__U95.out"], + ["d_6_at_max.out","d_3_am__U96.in1"], + ["d_3_am__U97.in0","d_3_am__U96.out"], + ["d_7_at_max.out","d_3_am__U97.in1"], + ["d_3_next_value.sel","d_3_am__U97.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5020,13 +4754,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U607.in0"], - ["d_5_at_max.out","d_4_am__U607.in1"], - ["d_4_am__U608.in0","d_4_am__U607.out"], - ["d_6_at_max.out","d_4_am__U608.in1"], - ["d_4_am__U609.in0","d_4_am__U608.out"], - ["d_7_at_max.out","d_4_am__U609.in1"], - ["d_4_next_value.sel","d_4_am__U609.out"], + ["d_4_am__U99.out","d_4_am__U100.in0"], + ["d_7_at_max.out","d_4_am__U100.in1"], + ["d_4_next_value.sel","d_4_am__U100.out"], + ["true.out","d_4_am__U98.in0"], + ["d_5_at_max.out","d_4_am__U98.in1"], + ["d_4_am__U99.in0","d_4_am__U98.out"], + ["d_6_at_max.out","d_4_am__U99.in1"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -5039,11 +4773,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U610.in0"], - ["d_6_at_max.out","d_5_am__U610.in1"], - ["d_5_am__U611.in0","d_5_am__U610.out"], - ["d_7_at_max.out","d_5_am__U611.in1"], - ["d_5_next_value.sel","d_5_am__U611.out"], + ["true.out","d_5_am__U101.in0"], + ["d_6_at_max.out","d_5_am__U101.in1"], + ["d_5_am__U102.in0","d_5_am__U101.out"], + ["d_7_at_max.out","d_5_am__U102.in1"], + ["d_5_next_value.sel","d_5_am__U102.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -5056,9 +4790,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U612.in0"], - ["d_7_at_max.out","d_6_am__U612.in1"], - ["d_6_next_value.sel","d_6_am__U612.out"], + ["true.out","d_6_am__U103.in0"], + ["d_7_at_max.out","d_6_am__U103.in1"], + ["d_6_next_value.sel","d_6_am__U103.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -5086,7 +4820,7 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U473":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5094,18 +4828,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U83":{ + "_U500":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U84":{ + "_U501":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U57" + "modref":"global.aff__U474" }, "cmp_time":{ "genref":"coreir.eq", @@ -5115,25 +4849,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U85":{ + "d_0_am__U502":{ "modref":"corebit.and" }, - "d_0_am__U86":{ + "d_0_am__U503":{ "modref":"corebit.and" }, - "d_0_am__U87":{ + "d_0_am__U504":{ "modref":"corebit.and" }, - "d_0_am__U88":{ + "d_0_am__U505":{ "modref":"corebit.and" }, - "d_0_am__U89":{ + "d_0_am__U506":{ "modref":"corebit.and" }, - "d_0_am__U90":{ + "d_0_am__U507":{ "modref":"corebit.and" }, - "d_0_am__U91":{ + "d_0_am__U508":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5167,22 +4901,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U92":{ + "d_1_am__U509":{ "modref":"corebit.and" }, - "d_1_am__U93":{ + "d_1_am__U510":{ "modref":"corebit.and" }, - "d_1_am__U94":{ + "d_1_am__U511":{ "modref":"corebit.and" }, - "d_1_am__U95":{ + "d_1_am__U512":{ "modref":"corebit.and" }, - "d_1_am__U96":{ + "d_1_am__U513":{ "modref":"corebit.and" }, - "d_1_am__U97":{ + "d_1_am__U514":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -5216,19 +4950,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U100":{ + "d_2_am__U515":{ "modref":"corebit.and" }, - "d_2_am__U101":{ + "d_2_am__U516":{ "modref":"corebit.and" }, - "d_2_am__U102":{ + "d_2_am__U517":{ "modref":"corebit.and" }, - "d_2_am__U98":{ + "d_2_am__U518":{ "modref":"corebit.and" }, - "d_2_am__U99":{ + "d_2_am__U519":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5262,16 +4996,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U103":{ + "d_3_am__U520":{ "modref":"corebit.and" }, - "d_3_am__U104":{ + "d_3_am__U521":{ "modref":"corebit.and" }, - "d_3_am__U105":{ + "d_3_am__U522":{ "modref":"corebit.and" }, - "d_3_am__U106":{ + "d_3_am__U523":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -5305,13 +5039,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U107":{ + "d_4_am__U524":{ "modref":"corebit.and" }, - "d_4_am__U108":{ + "d_4_am__U525":{ "modref":"corebit.and" }, - "d_4_am__U109":{ + "d_4_am__U526":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -5325,7 +5059,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h0000000d"]} }, "d_4_min":{ "genref":"coreir.const", @@ -5345,10 +5079,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U110":{ + "d_5_am__U527":{ "modref":"corebit.and" }, - "d_5_am__U111":{ + "d_5_am__U528":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -5362,7 +5096,7 @@ "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + "modargs":{"value":[["BitVector",32],"32'h0000000d"]} }, "d_5_min":{ "genref":"coreir.const", @@ -5382,7 +5116,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U112":{ + "d_6_am__U529":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -5396,7 +5130,7 @@ "d_6_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, "d_6_min":{ "genref":"coreir.const", @@ -5457,15 +5191,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U83.out"], - ["d_1_inc.in1","_U83.out"], - ["d_2_inc.in1","_U83.out"], - ["d_3_inc.in1","_U83.out"], - ["d_4_inc.in1","_U83.out"], - ["d_5_inc.in1","_U83.out"], - ["d_6_inc.in1","_U83.out"], - ["d_7_inc.in1","_U83.out"], - ["cmp_time.in1","_U84.out"], + ["d_0_inc.in1","_U500.out"], + ["d_1_inc.in1","_U500.out"], + ["d_2_inc.in1","_U500.out"], + ["d_3_inc.in1","_U500.out"], + ["d_4_inc.in1","_U500.out"], + ["d_5_inc.in1","_U500.out"], + ["d_6_inc.in1","_U500.out"], + ["d_7_inc.in1","_U500.out"], + ["cmp_time.in1","_U501.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5488,21 +5222,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U85.in0"], - ["d_1_at_max.out","d_0_am__U85.in1"], - ["d_0_am__U86.in0","d_0_am__U85.out"], - ["d_2_at_max.out","d_0_am__U86.in1"], - ["d_0_am__U87.in0","d_0_am__U86.out"], - ["d_3_at_max.out","d_0_am__U87.in1"], - ["d_0_am__U88.in0","d_0_am__U87.out"], - ["d_4_at_max.out","d_0_am__U88.in1"], - ["d_0_am__U89.in0","d_0_am__U88.out"], - ["d_5_at_max.out","d_0_am__U89.in1"], - ["d_0_am__U90.in0","d_0_am__U89.out"], - ["d_6_at_max.out","d_0_am__U90.in1"], - ["d_0_am__U91.in0","d_0_am__U90.out"], - ["d_7_at_max.out","d_0_am__U91.in1"], - ["d_0_next_value.sel","d_0_am__U91.out"], + ["true.out","d_0_am__U502.in0"], + ["d_1_at_max.out","d_0_am__U502.in1"], + ["d_0_am__U503.in0","d_0_am__U502.out"], + ["d_2_at_max.out","d_0_am__U503.in1"], + ["d_0_am__U504.in0","d_0_am__U503.out"], + ["d_3_at_max.out","d_0_am__U504.in1"], + ["d_0_am__U505.in0","d_0_am__U504.out"], + ["d_4_at_max.out","d_0_am__U505.in1"], + ["d_0_am__U506.in0","d_0_am__U505.out"], + ["d_5_at_max.out","d_0_am__U506.in1"], + ["d_0_am__U507.in0","d_0_am__U506.out"], + ["d_6_at_max.out","d_0_am__U507.in1"], + ["d_0_am__U508.in0","d_0_am__U507.out"], + ["d_7_at_max.out","d_0_am__U508.in1"], + ["d_0_next_value.sel","d_0_am__U508.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5515,19 +5249,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U92.in0"], - ["d_2_at_max.out","d_1_am__U92.in1"], - ["d_1_am__U93.in0","d_1_am__U92.out"], - ["d_3_at_max.out","d_1_am__U93.in1"], - ["d_1_am__U94.in0","d_1_am__U93.out"], - ["d_4_at_max.out","d_1_am__U94.in1"], - ["d_1_am__U95.in0","d_1_am__U94.out"], - ["d_5_at_max.out","d_1_am__U95.in1"], - ["d_1_am__U96.in0","d_1_am__U95.out"], - ["d_6_at_max.out","d_1_am__U96.in1"], - ["d_1_am__U97.in0","d_1_am__U96.out"], - ["d_7_at_max.out","d_1_am__U97.in1"], - ["d_1_next_value.sel","d_1_am__U97.out"], + ["true.out","d_1_am__U509.in0"], + ["d_2_at_max.out","d_1_am__U509.in1"], + ["d_1_am__U510.in0","d_1_am__U509.out"], + ["d_3_at_max.out","d_1_am__U510.in1"], + ["d_1_am__U511.in0","d_1_am__U510.out"], + ["d_4_at_max.out","d_1_am__U511.in1"], + ["d_1_am__U512.in0","d_1_am__U511.out"], + ["d_5_at_max.out","d_1_am__U512.in1"], + ["d_1_am__U513.in0","d_1_am__U512.out"], + ["d_6_at_max.out","d_1_am__U513.in1"], + ["d_1_am__U514.in0","d_1_am__U513.out"], + ["d_7_at_max.out","d_1_am__U514.in1"], + ["d_1_next_value.sel","d_1_am__U514.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5540,17 +5274,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["d_2_am__U99.out","d_2_am__U100.in0"], - ["d_5_at_max.out","d_2_am__U100.in1"], - ["d_2_am__U101.in0","d_2_am__U100.out"], - ["d_6_at_max.out","d_2_am__U101.in1"], - ["d_2_am__U102.in0","d_2_am__U101.out"], - ["d_7_at_max.out","d_2_am__U102.in1"], - ["d_2_next_value.sel","d_2_am__U102.out"], - ["true.out","d_2_am__U98.in0"], - ["d_3_at_max.out","d_2_am__U98.in1"], - ["d_2_am__U99.in0","d_2_am__U98.out"], - ["d_4_at_max.out","d_2_am__U99.in1"], + ["true.out","d_2_am__U515.in0"], + ["d_3_at_max.out","d_2_am__U515.in1"], + ["d_2_am__U516.in0","d_2_am__U515.out"], + ["d_4_at_max.out","d_2_am__U516.in1"], + ["d_2_am__U517.in0","d_2_am__U516.out"], + ["d_5_at_max.out","d_2_am__U517.in1"], + ["d_2_am__U518.in0","d_2_am__U517.out"], + ["d_6_at_max.out","d_2_am__U518.in1"], + ["d_2_am__U519.in0","d_2_am__U518.out"], + ["d_7_at_max.out","d_2_am__U519.in1"], + ["d_2_next_value.sel","d_2_am__U519.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5563,15 +5297,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U103.in0"], - ["d_4_at_max.out","d_3_am__U103.in1"], - ["d_3_am__U104.in0","d_3_am__U103.out"], - ["d_5_at_max.out","d_3_am__U104.in1"], - ["d_3_am__U105.in0","d_3_am__U104.out"], - ["d_6_at_max.out","d_3_am__U105.in1"], - ["d_3_am__U106.in0","d_3_am__U105.out"], - ["d_7_at_max.out","d_3_am__U106.in1"], - ["d_3_next_value.sel","d_3_am__U106.out"], + ["true.out","d_3_am__U520.in0"], + ["d_4_at_max.out","d_3_am__U520.in1"], + ["d_3_am__U521.in0","d_3_am__U520.out"], + ["d_5_at_max.out","d_3_am__U521.in1"], + ["d_3_am__U522.in0","d_3_am__U521.out"], + ["d_6_at_max.out","d_3_am__U522.in1"], + ["d_3_am__U523.in0","d_3_am__U522.out"], + ["d_7_at_max.out","d_3_am__U523.in1"], + ["d_3_next_value.sel","d_3_am__U523.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5584,13 +5318,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U107.in0"], - ["d_5_at_max.out","d_4_am__U107.in1"], - ["d_4_am__U108.in0","d_4_am__U107.out"], - ["d_6_at_max.out","d_4_am__U108.in1"], - ["d_4_am__U109.in0","d_4_am__U108.out"], - ["d_7_at_max.out","d_4_am__U109.in1"], - ["d_4_next_value.sel","d_4_am__U109.out"], + ["true.out","d_4_am__U524.in0"], + ["d_5_at_max.out","d_4_am__U524.in1"], + ["d_4_am__U525.in0","d_4_am__U524.out"], + ["d_6_at_max.out","d_4_am__U525.in1"], + ["d_4_am__U526.in0","d_4_am__U525.out"], + ["d_7_at_max.out","d_4_am__U526.in1"], + ["d_4_next_value.sel","d_4_am__U526.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -5603,11 +5337,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U110.in0"], - ["d_6_at_max.out","d_5_am__U110.in1"], - ["d_5_am__U111.in0","d_5_am__U110.out"], - ["d_7_at_max.out","d_5_am__U111.in1"], - ["d_5_next_value.sel","d_5_am__U111.out"], + ["true.out","d_5_am__U527.in0"], + ["d_6_at_max.out","d_5_am__U527.in1"], + ["d_5_am__U528.in0","d_5_am__U527.out"], + ["d_7_at_max.out","d_5_am__U528.in1"], + ["d_5_next_value.sel","d_5_am__U528.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -5620,9 +5354,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U112.in0"], - ["d_7_at_max.out","d_6_am__U112.in1"], - ["d_6_next_value.sel","d_6_am__U112.out"], + ["true.out","d_6_am__U529.in0"], + ["d_7_at_max.out","d_6_am__U529.in1"], + ["d_6_next_value.sel","d_6_am__U529.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -5650,7 +5384,273 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U641":{ + "affine_controller__U558":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",4,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U573":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U574":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U559" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U575":{ + "modref":"corebit.and" + }, + "d_0_am__U576":{ + "modref":"corebit.and" + }, + "d_0_am__U577":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U578":{ + "modref":"corebit.and" + }, + "d_1_am__U579":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000001b"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_am__U580":{ + "modref":"corebit.and" + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000001b"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U573.out"], + ["d_1_inc.in1","_U573.out"], + ["d_2_inc.in1","_U573.out"], + ["d_3_inc.in1","_U573.out"], + ["cmp_time.in1","_U574.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U575.in0"], + ["d_1_at_max.out","d_0_am__U575.in1"], + ["d_0_am__U576.in0","d_0_am__U575.out"], + ["d_2_at_max.out","d_0_am__U576.in1"], + ["d_0_am__U577.in0","d_0_am__U576.out"], + ["d_3_at_max.out","d_0_am__U577.in1"], + ["d_0_next_value.sel","d_0_am__U577.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U578.in0"], + ["d_2_at_max.out","d_1_am__U578.in1"], + ["d_1_am__U579.in0","d_1_am__U578.out"], + ["d_3_at_max.out","d_1_am__U579.in1"], + ["d_1_next_value.sel","d_1_am__U579.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U580.in0"], + ["d_3_at_max.out","d_2_am__U580.in1"], + ["d_2_next_value.sel","d_2_am__U580.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] + ] + }, + "affine_controller__U598":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5658,18 +5658,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U656":{ + "_U613":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U657":{ + "_U614":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U642" + "modref":"global.aff__U599" }, "cmp_time":{ "genref":"coreir.eq", @@ -5679,13 +5679,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U658":{ + "d_0_am__U615":{ "modref":"corebit.and" }, - "d_0_am__U659":{ + "d_0_am__U616":{ "modref":"corebit.and" }, - "d_0_am__U660":{ + "d_0_am__U617":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5719,10 +5719,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U661":{ + "d_1_am__U618":{ "modref":"corebit.and" }, - "d_1_am__U662":{ + "d_1_am__U619":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -5756,7 +5756,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U663":{ + "d_2_am__U620":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5831,11 +5831,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U656.out"], - ["d_1_inc.in1","_U656.out"], - ["d_2_inc.in1","_U656.out"], - ["d_3_inc.in1","_U656.out"], - ["cmp_time.in1","_U657.out"], + ["d_0_inc.in1","_U613.out"], + ["d_1_inc.in1","_U613.out"], + ["d_2_inc.in1","_U613.out"], + ["d_3_inc.in1","_U613.out"], + ["cmp_time.in1","_U614.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5850,13 +5850,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U658.in0"], - ["d_1_at_max.out","d_0_am__U658.in1"], - ["d_0_am__U659.in0","d_0_am__U658.out"], - ["d_2_at_max.out","d_0_am__U659.in1"], - ["d_0_am__U660.in0","d_0_am__U659.out"], - ["d_3_at_max.out","d_0_am__U660.in1"], - ["d_0_next_value.sel","d_0_am__U660.out"], + ["true.out","d_0_am__U615.in0"], + ["d_1_at_max.out","d_0_am__U615.in1"], + ["d_0_am__U616.in0","d_0_am__U615.out"], + ["d_2_at_max.out","d_0_am__U616.in1"], + ["d_0_am__U617.in0","d_0_am__U616.out"], + ["d_3_at_max.out","d_0_am__U617.in1"], + ["d_0_next_value.sel","d_0_am__U617.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5869,11 +5869,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U661.in0"], - ["d_2_at_max.out","d_1_am__U661.in1"], - ["d_1_am__U662.in0","d_1_am__U661.out"], - ["d_3_at_max.out","d_1_am__U662.in1"], - ["d_1_next_value.sel","d_1_am__U662.out"], + ["true.out","d_1_am__U618.in0"], + ["d_2_at_max.out","d_1_am__U618.in1"], + ["d_1_am__U619.in0","d_1_am__U618.out"], + ["d_3_at_max.out","d_1_am__U619.in1"], + ["d_1_next_value.sel","d_1_am__U619.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5886,9 +5886,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U663.in0"], - ["d_3_at_max.out","d_2_am__U663.in1"], - ["d_2_next_value.sel","d_2_am__U663.out"], + ["true.out","d_2_am__U620.in0"], + ["d_3_at_max.out","d_2_am__U620.in1"], + ["d_2_next_value.sel","d_2_am__U620.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5916,7 +5916,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U681":{ + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5924,18 +5924,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U696":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U697":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U682" + "modref":"global.aff__U9" }, "cmp_time":{ "genref":"coreir.eq", @@ -5945,13 +5945,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U698":{ + "d_0_am__U25":{ "modref":"corebit.and" }, - "d_0_am__U699":{ + "d_0_am__U26":{ "modref":"corebit.and" }, - "d_0_am__U700":{ + "d_0_am__U27":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5985,10 +5985,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U701":{ + "d_1_am__U28":{ "modref":"corebit.and" }, - "d_1_am__U702":{ + "d_1_am__U29":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -6002,7 +6002,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001b"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_1_min":{ "genref":"coreir.const", @@ -6022,7 +6022,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U703":{ + "d_2_am__U30":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -6036,7 +6036,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001b"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_2_min":{ "genref":"coreir.const", @@ -6067,7 +6067,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -6097,11 +6097,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U696.out"], - ["d_1_inc.in1","_U696.out"], - ["d_2_inc.in1","_U696.out"], - ["d_3_inc.in1","_U696.out"], - ["cmp_time.in1","_U697.out"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U23.out"], + ["d_2_inc.in1","_U23.out"], + ["d_3_inc.in1","_U23.out"], + ["cmp_time.in1","_U24.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -6116,13 +6116,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U698.in0"], - ["d_1_at_max.out","d_0_am__U698.in1"], - ["d_0_am__U699.in0","d_0_am__U698.out"], - ["d_2_at_max.out","d_0_am__U699.in1"], - ["d_0_am__U700.in0","d_0_am__U699.out"], - ["d_3_at_max.out","d_0_am__U700.in1"], - ["d_0_next_value.sel","d_0_am__U700.out"], + ["true.out","d_0_am__U25.in0"], + ["d_1_at_max.out","d_0_am__U25.in1"], + ["d_0_am__U26.in0","d_0_am__U25.out"], + ["d_2_at_max.out","d_0_am__U26.in1"], + ["d_0_am__U27.in0","d_0_am__U26.out"], + ["d_3_at_max.out","d_0_am__U27.in1"], + ["d_0_next_value.sel","d_0_am__U27.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6135,11 +6135,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U701.in0"], - ["d_2_at_max.out","d_1_am__U701.in1"], - ["d_1_am__U702.in0","d_1_am__U701.out"], - ["d_3_at_max.out","d_1_am__U702.in1"], - ["d_1_next_value.sel","d_1_am__U702.out"], + ["true.out","d_1_am__U28.in0"], + ["d_2_at_max.out","d_1_am__U28.in1"], + ["d_1_am__U29.in0","d_1_am__U28.out"], + ["d_3_at_max.out","d_1_am__U29.in1"], + ["d_1_next_value.sel","d_1_am__U29.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -6152,9 +6152,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U703.in0"], - ["d_3_at_max.out","d_2_am__U703.in1"], - ["d_2_next_value.sel","d_2_am__U703.out"], + ["true.out","d_2_am__U30.in0"], + ["d_3_at_max.out","d_2_am__U30.in1"], + ["d_2_next_value.sel","d_2_am__U30.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -7799,42 +7799,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53849],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53849],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -7842,8 +7810,8 @@ }, "ub_input_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53850],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61025],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53850],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61025],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -7851,8 +7819,8 @@ }, "ub_input_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53851],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53851],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -7860,8 +7828,8 @@ }, "ub_input_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53852],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53852],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -7869,8 +7837,8 @@ }, "ub_input_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53853],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53853],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -7878,8 +7846,8 @@ }, "ub_input_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53854],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53854],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -7887,8 +7855,8 @@ }, "ub_input_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53855],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53855],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -7896,8 +7864,8 @@ }, "ub_input_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53856],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53856],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -7905,14 +7873,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_input_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U11.out"], - ["ub_input_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U13.out"], - ["ub_input_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U15.out"], - ["ub_input_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_input_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], - ["ub_input_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U7.out"], - ["ub_input_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U9.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_1.clk","self.clk"], ["ub_input_cgra_stencil_BANK_2.clk","self.clk"], @@ -8030,42 +7990,42 @@ ["op_hcompute_input_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U140":{ - "modref":"global.aff__U114" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U131":{ + "modref":"global.aff__U105" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55":{ - "modref":"global.aff__U41" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46":{ + "modref":"global.aff__U32" }, - "chain_en_const_U141":{ + "chain_en_const_U132":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U113":{ - "modref":"global.affine_controller__U56", + "ctrl__U104":{ + "modref":"global.affine_controller__U47", "metadata":{"garnet_remove":true} }, - "ctrl__U40":{ - "modref":"global.affine_controller__U17", + "ctrl__U31":{ + "modref":"global.affine_controller__U8", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,240,8064,16128,32256,64512],"dimensionality":7,"extent":[8,30,30,2,2,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,928,8,0,448,25984]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[53824],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U16"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,240,8064,16128,32256,64512],"dimensionality":7,"extent":[8,30,30,2,2,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,928,8,0,448,25984]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[53824],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U113.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U140.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U140.out"], - ["ctrl__U40.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U141.out"], - ["self.clk","ctrl__U113.clk"], - ["self.reset","ctrl__U113.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U113.valid"], - ["self.clk","ctrl__U40.clk"], - ["self.reset","ctrl__U40.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U40.valid"], + ["ctrl__U104.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U131.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U131.out"], + ["ctrl__U31.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U132.out"], + ["self.clk","ctrl__U104.clk"], + ["self.reset","ctrl__U104.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U104.valid"], + ["self.clk","ctrl__U31.clk"], + ["self.reset","ctrl__U31.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U31.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_glb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_input_cgra_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -8097,266 +8057,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54017],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U142"} + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54017],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -8364,13 +8068,13 @@ }, "ub_kernel_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54025],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53832],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U144"} + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54025],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53832],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54034],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53841],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U162"} + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54034],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53841],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -8378,8 +8082,8 @@ }, "ub_kernel_cgra_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54042],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53849],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U164"} + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54042],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53849],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -8387,8 +8091,8 @@ }, "ub_kernel_cgra_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54050],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53857],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U166"} + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54050],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53857],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -8396,8 +8100,8 @@ }, "ub_kernel_cgra_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54058],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53865],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U168"} + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54058],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53865],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -8405,8 +8109,8 @@ }, "ub_kernel_cgra_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54066],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53873],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U170"} + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54066],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53873],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -8414,8 +8118,8 @@ }, "ub_kernel_cgra_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54074],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53881],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U172"} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54074],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53881],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -8423,8 +8127,8 @@ }, "ub_kernel_cgra_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54019],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U174"} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54019],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -8432,8 +8136,8 @@ }, "ub_kernel_cgra_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54027],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53834],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U176"} + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54027],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53834],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -8441,8 +8145,8 @@ }, "ub_kernel_cgra_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54035],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53842],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U178"} + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54035],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53842],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -8450,8 +8154,8 @@ }, "ub_kernel_cgra_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54043],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53850],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U180"} + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54043],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53850],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -8463,13 +8167,13 @@ }, "ub_kernel_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54033],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53840],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U146"} + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54033],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53840],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54051],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53858],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U182"} + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54051],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53858],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -8477,8 +8181,8 @@ }, "ub_kernel_cgra_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54059],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53866],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U184"} + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54059],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53866],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -8486,8 +8190,8 @@ }, "ub_kernel_cgra_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54067],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53874],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U186"} + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54067],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53874],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -8495,8 +8199,8 @@ }, "ub_kernel_cgra_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54075],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53882],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U188"} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54075],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53882],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -8504,8 +8208,8 @@ }, "ub_kernel_cgra_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54020],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U190"} + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54020],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -8513,8 +8217,8 @@ }, "ub_kernel_cgra_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54028],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53835],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U192"} + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54028],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53835],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -8522,8 +8226,8 @@ }, "ub_kernel_cgra_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54036],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53843],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U194"} + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54036],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53843],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -8531,8 +8235,8 @@ }, "ub_kernel_cgra_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54044],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53851],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U196"} + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54044],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53851],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -8540,8 +8244,8 @@ }, "ub_kernel_cgra_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54052],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53859],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U198"} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54052],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53859],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -8549,8 +8253,8 @@ }, "ub_kernel_cgra_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54060],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53867],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U200"} + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54060],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53867],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -8562,13 +8266,13 @@ }, "ub_kernel_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54041],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53848],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U148"} + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54041],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53848],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54068],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53875],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U202"} + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54068],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53875],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -8576,8 +8280,8 @@ }, "ub_kernel_cgra_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54076],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53883],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U204"} + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54076],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53883],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -8585,8 +8289,8 @@ }, "ub_kernel_cgra_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54021],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U206"} + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54021],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -8594,8 +8298,8 @@ }, "ub_kernel_cgra_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54029],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53836],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U208"} + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54029],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53836],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -8603,8 +8307,8 @@ }, "ub_kernel_cgra_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54037],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53844],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U210"} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54037],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53844],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -8612,8 +8316,8 @@ }, "ub_kernel_cgra_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54045],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53852],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U212"} + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54045],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53852],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -8621,8 +8325,8 @@ }, "ub_kernel_cgra_stencil_BANK_36":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54053],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53860],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U214"} + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54053],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53860],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const":{ "modref":"corebit.const", @@ -8630,8 +8334,8 @@ }, "ub_kernel_cgra_stencil_BANK_37":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54061],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53868],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U216"} + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54061],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53868],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const":{ "modref":"corebit.const", @@ -8639,8 +8343,8 @@ }, "ub_kernel_cgra_stencil_BANK_38":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54069],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53876],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U218"} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54069],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53876],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const":{ "modref":"corebit.const", @@ -8648,8 +8352,8 @@ }, "ub_kernel_cgra_stencil_BANK_39":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54077],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53884],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U220"} + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54077],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53884],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const":{ "modref":"corebit.const", @@ -8661,13 +8365,13 @@ }, "ub_kernel_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54049],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53856],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U150"} + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54049],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53856],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54022],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U222"} + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54022],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const":{ "modref":"corebit.const", @@ -8675,8 +8379,8 @@ }, "ub_kernel_cgra_stencil_BANK_41":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54030],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53837],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U224"} + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54030],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53837],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const":{ "modref":"corebit.const", @@ -8684,8 +8388,8 @@ }, "ub_kernel_cgra_stencil_BANK_42":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54038],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53845],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U226"} + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54038],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53845],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const":{ "modref":"corebit.const", @@ -8693,8 +8397,8 @@ }, "ub_kernel_cgra_stencil_BANK_43":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54046],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53853],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U228"} + "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54046],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53853],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const":{ "modref":"corebit.const", @@ -8702,8 +8406,8 @@ }, "ub_kernel_cgra_stencil_BANK_44":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54054],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53861],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U230"} + "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54054],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53861],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const":{ "modref":"corebit.const", @@ -8711,8 +8415,8 @@ }, "ub_kernel_cgra_stencil_BANK_45":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54062],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53869],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U232"} + "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54062],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53869],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const":{ "modref":"corebit.const", @@ -8720,8 +8424,8 @@ }, "ub_kernel_cgra_stencil_BANK_46":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54070],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53877],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U234"} + "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54070],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53877],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const":{ "modref":"corebit.const", @@ -8729,8 +8433,8 @@ }, "ub_kernel_cgra_stencil_BANK_47":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54078],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53885],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U236"} + "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54078],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53885],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const":{ "modref":"corebit.const", @@ -8738,8 +8442,8 @@ }, "ub_kernel_cgra_stencil_BANK_48":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54023],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U238"} + "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54023],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const":{ "modref":"corebit.const", @@ -8747,8 +8451,8 @@ }, "ub_kernel_cgra_stencil_BANK_49":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54031],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53838],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U240"} + "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54031],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53838],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const":{ "modref":"corebit.const", @@ -8760,13 +8464,13 @@ }, "ub_kernel_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54057],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53864],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U152"} + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54057],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53864],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54039],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53846],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U242"} + "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54039],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53846],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const":{ "modref":"corebit.const", @@ -8774,8 +8478,8 @@ }, "ub_kernel_cgra_stencil_BANK_51":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54047],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53854],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U244"} + "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54047],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53854],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const":{ "modref":"corebit.const", @@ -8783,8 +8487,8 @@ }, "ub_kernel_cgra_stencil_BANK_52":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54055],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53862],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U246"} + "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54055],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53862],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const":{ "modref":"corebit.const", @@ -8792,8 +8496,8 @@ }, "ub_kernel_cgra_stencil_BANK_53":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54063],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53870],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U248"} + "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54063],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53870],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const":{ "modref":"corebit.const", @@ -8801,8 +8505,8 @@ }, "ub_kernel_cgra_stencil_BANK_54":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54071],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53878],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U250"} + "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54071],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53878],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const":{ "modref":"corebit.const", @@ -8810,8 +8514,8 @@ }, "ub_kernel_cgra_stencil_BANK_55":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54079],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53886],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U252"} + "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54079],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53886],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const":{ "modref":"corebit.const", @@ -8819,8 +8523,8 @@ }, "ub_kernel_cgra_stencil_BANK_56":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54024],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U254"} + "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54024],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const":{ "modref":"corebit.const", @@ -8828,8 +8532,8 @@ }, "ub_kernel_cgra_stencil_BANK_57":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54032],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53839],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U256"} + "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54032],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53839],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const":{ "modref":"corebit.const", @@ -8837,8 +8541,8 @@ }, "ub_kernel_cgra_stencil_BANK_58":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54040],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53847],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U258"} + "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54040],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53847],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const":{ "modref":"corebit.const", @@ -8846,8 +8550,8 @@ }, "ub_kernel_cgra_stencil_BANK_59":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54048],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53855],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U260"} + "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54048],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53855],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const":{ "modref":"corebit.const", @@ -8859,13 +8563,13 @@ }, "ub_kernel_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54065],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53872],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U154"} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54065],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53872],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54056],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53863],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U262"} + "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54056],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53863],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const":{ "modref":"corebit.const", @@ -8873,8 +8577,8 @@ }, "ub_kernel_cgra_stencil_BANK_61":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54064],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53871],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U264"} + "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54064],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53871],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const":{ "modref":"corebit.const", @@ -8882,8 +8586,8 @@ }, "ub_kernel_cgra_stencil_BANK_62":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54072],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53879],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U266"} + "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54072],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53879],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const":{ "modref":"corebit.const", @@ -8891,8 +8595,8 @@ }, "ub_kernel_cgra_stencil_BANK_63":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54080],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53887],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U268"} + "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54080],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53887],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const":{ "modref":"corebit.const", @@ -8904,8 +8608,8 @@ }, "ub_kernel_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54073],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53880],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U156"} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54073],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53880],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61030],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -8913,8 +8617,8 @@ }, "ub_kernel_cgra_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54018],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U158"} + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54018],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -8922,8 +8626,8 @@ }, "ub_kernel_cgra_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54026],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53833],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U160"} + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54026],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53833],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[61029],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[61032],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -8931,70 +8635,6 @@ } }, "connections":[ - ["ub_kernel_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U143.out"], - ["ub_kernel_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U145.out"], - ["ub_kernel_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U147.out"], - ["ub_kernel_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U149.out"], - ["ub_kernel_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U151.out"], - ["ub_kernel_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U153.out"], - ["ub_kernel_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U155.out"], - ["ub_kernel_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U157.out"], - ["ub_kernel_cgra_stencil_BANK_8.chain_chain_en","chain_en_const_U159.out"], - ["ub_kernel_cgra_stencil_BANK_9.chain_chain_en","chain_en_const_U161.out"], - ["ub_kernel_cgra_stencil_BANK_10.chain_chain_en","chain_en_const_U163.out"], - ["ub_kernel_cgra_stencil_BANK_11.chain_chain_en","chain_en_const_U165.out"], - ["ub_kernel_cgra_stencil_BANK_12.chain_chain_en","chain_en_const_U167.out"], - ["ub_kernel_cgra_stencil_BANK_13.chain_chain_en","chain_en_const_U169.out"], - ["ub_kernel_cgra_stencil_BANK_14.chain_chain_en","chain_en_const_U171.out"], - ["ub_kernel_cgra_stencil_BANK_15.chain_chain_en","chain_en_const_U173.out"], - ["ub_kernel_cgra_stencil_BANK_16.chain_chain_en","chain_en_const_U175.out"], - ["ub_kernel_cgra_stencil_BANK_17.chain_chain_en","chain_en_const_U177.out"], - ["ub_kernel_cgra_stencil_BANK_18.chain_chain_en","chain_en_const_U179.out"], - ["ub_kernel_cgra_stencil_BANK_19.chain_chain_en","chain_en_const_U181.out"], - ["ub_kernel_cgra_stencil_BANK_20.chain_chain_en","chain_en_const_U183.out"], - ["ub_kernel_cgra_stencil_BANK_21.chain_chain_en","chain_en_const_U185.out"], - ["ub_kernel_cgra_stencil_BANK_22.chain_chain_en","chain_en_const_U187.out"], - ["ub_kernel_cgra_stencil_BANK_23.chain_chain_en","chain_en_const_U189.out"], - ["ub_kernel_cgra_stencil_BANK_24.chain_chain_en","chain_en_const_U191.out"], - ["ub_kernel_cgra_stencil_BANK_25.chain_chain_en","chain_en_const_U193.out"], - ["ub_kernel_cgra_stencil_BANK_26.chain_chain_en","chain_en_const_U195.out"], - ["ub_kernel_cgra_stencil_BANK_27.chain_chain_en","chain_en_const_U197.out"], - ["ub_kernel_cgra_stencil_BANK_28.chain_chain_en","chain_en_const_U199.out"], - ["ub_kernel_cgra_stencil_BANK_29.chain_chain_en","chain_en_const_U201.out"], - ["ub_kernel_cgra_stencil_BANK_30.chain_chain_en","chain_en_const_U203.out"], - ["ub_kernel_cgra_stencil_BANK_31.chain_chain_en","chain_en_const_U205.out"], - ["ub_kernel_cgra_stencil_BANK_32.chain_chain_en","chain_en_const_U207.out"], - ["ub_kernel_cgra_stencil_BANK_33.chain_chain_en","chain_en_const_U209.out"], - ["ub_kernel_cgra_stencil_BANK_34.chain_chain_en","chain_en_const_U211.out"], - ["ub_kernel_cgra_stencil_BANK_35.chain_chain_en","chain_en_const_U213.out"], - ["ub_kernel_cgra_stencil_BANK_36.chain_chain_en","chain_en_const_U215.out"], - ["ub_kernel_cgra_stencil_BANK_37.chain_chain_en","chain_en_const_U217.out"], - ["ub_kernel_cgra_stencil_BANK_38.chain_chain_en","chain_en_const_U219.out"], - ["ub_kernel_cgra_stencil_BANK_39.chain_chain_en","chain_en_const_U221.out"], - ["ub_kernel_cgra_stencil_BANK_40.chain_chain_en","chain_en_const_U223.out"], - ["ub_kernel_cgra_stencil_BANK_41.chain_chain_en","chain_en_const_U225.out"], - ["ub_kernel_cgra_stencil_BANK_42.chain_chain_en","chain_en_const_U227.out"], - ["ub_kernel_cgra_stencil_BANK_43.chain_chain_en","chain_en_const_U229.out"], - ["ub_kernel_cgra_stencil_BANK_44.chain_chain_en","chain_en_const_U231.out"], - ["ub_kernel_cgra_stencil_BANK_45.chain_chain_en","chain_en_const_U233.out"], - ["ub_kernel_cgra_stencil_BANK_46.chain_chain_en","chain_en_const_U235.out"], - ["ub_kernel_cgra_stencil_BANK_47.chain_chain_en","chain_en_const_U237.out"], - ["ub_kernel_cgra_stencil_BANK_48.chain_chain_en","chain_en_const_U239.out"], - ["ub_kernel_cgra_stencil_BANK_49.chain_chain_en","chain_en_const_U241.out"], - ["ub_kernel_cgra_stencil_BANK_50.chain_chain_en","chain_en_const_U243.out"], - ["ub_kernel_cgra_stencil_BANK_51.chain_chain_en","chain_en_const_U245.out"], - ["ub_kernel_cgra_stencil_BANK_52.chain_chain_en","chain_en_const_U247.out"], - ["ub_kernel_cgra_stencil_BANK_53.chain_chain_en","chain_en_const_U249.out"], - ["ub_kernel_cgra_stencil_BANK_54.chain_chain_en","chain_en_const_U251.out"], - ["ub_kernel_cgra_stencil_BANK_55.chain_chain_en","chain_en_const_U253.out"], - ["ub_kernel_cgra_stencil_BANK_56.chain_chain_en","chain_en_const_U255.out"], - ["ub_kernel_cgra_stencil_BANK_57.chain_chain_en","chain_en_const_U257.out"], - ["ub_kernel_cgra_stencil_BANK_58.chain_chain_en","chain_en_const_U259.out"], - ["ub_kernel_cgra_stencil_BANK_59.chain_chain_en","chain_en_const_U261.out"], - ["ub_kernel_cgra_stencil_BANK_60.chain_chain_en","chain_en_const_U263.out"], - ["ub_kernel_cgra_stencil_BANK_61.chain_chain_en","chain_en_const_U265.out"], - ["ub_kernel_cgra_stencil_BANK_62.chain_chain_en","chain_en_const_U267.out"], - ["ub_kernel_cgra_stencil_BANK_63.chain_chain_en","chain_en_const_U269.out"], ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_1.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_10.clk","self.clk"], @@ -9392,49 +9032,49 @@ ["op_hcompute_kernel_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U433":{ - "modref":"global.aff__U401" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U359":{ + "modref":"global.aff__U327" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U319":{ - "modref":"global.aff__U302" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U245":{ + "modref":"global.aff__U228" }, - "chain_en_const_U434":{ + "chain_en_const_U360":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U301":{ - "modref":"global.affine_controller__U271", + "ctrl__U227":{ + "modref":"global.affine_controller__U197", "metadata":{"garnet_remove":true} }, - "ctrl__U400":{ - "modref":"global.affine_controller__U320", + "ctrl__U326":{ + "modref":"global.affine_controller__U246", "metadata":{"garnet_remove":true} }, "kernel_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,256,8064,16128,32256],"dimensionality":6,"extent":[8,32,9,2,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,16,1024,8,512,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9216],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U270"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,256,8064,16128,32256],"dimensionality":6,"extent":[8,32,9,2,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,16,1024,8,512,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9216],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U400.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U433.d"], - ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U433.out"], - ["ctrl__U301.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U319.d"], - ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U319.out"], - ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U434.out"], - ["self.clk","ctrl__U301.clk"], - ["self.reset","ctrl__U301.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U301.valid"], - ["self.clk","ctrl__U400.clk"], - ["self.reset","ctrl__U400.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U400.valid"], + ["ctrl__U326.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U359.d"], + ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U359.out"], + ["ctrl__U227.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U245.d"], + ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U245.out"], + ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U360.out"], + ["self.clk","ctrl__U227.clk"], + ["self.reset","ctrl__U227.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U227.valid"], + ["self.clk","ctrl__U326.clk"], + ["self.reset","ctrl__U326.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U326.valid"], ["self.clk","kernel_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_kernel_glb_stencil_write.0","kernel_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_kernel_cgra_stencil_read.0","kernel_glb_stencil_BANK_0_ubuf.data_out_0"], ["self.reset","kernel_glb_stencil_BANK_0_ubuf.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U707":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U624":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -9443,7 +9083,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U706":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U623":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9452,7 +9092,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U705":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U622":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -9461,7 +9101,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U704":{ + "op_hcompute_hw_output_stencil_read_start_pt__U621":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9470,7 +9110,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U709":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U626":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -9479,7 +9119,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U708":{ + "op_hcompute_hw_output_stencil_write_start_pt__U625":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9488,7 +9128,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U717":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U634":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9497,7 +9137,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U716":{ + "op_hcompute_input_glb_stencil_read_start_pt__U633":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9506,7 +9146,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U718":{ + "op_hcompute_input_glb_stencil_write_start_pt__U635":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9515,7 +9155,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U712":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U629":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9524,7 +9164,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U711":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U628":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9533,7 +9173,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U713":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U630":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9599,74 +9239,42 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U449":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U464":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U479":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U494":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U509":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U524":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U539":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U554":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ctrl__U448":{ - "modref":"global.affine_controller__U436", + "ctrl__U374":{ + "modref":"global.affine_controller__U362", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U463":{ - "modref":"global.affine_controller__U451", + "ctrl__U388":{ + "modref":"global.affine_controller__U376", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U478":{ - "modref":"global.affine_controller__U466", + "ctrl__U402":{ + "modref":"global.affine_controller__U390", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U493":{ - "modref":"global.affine_controller__U481", + "ctrl__U416":{ + "modref":"global.affine_controller__U404", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U508":{ - "modref":"global.affine_controller__U496", + "ctrl__U430":{ + "modref":"global.affine_controller__U418", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U523":{ - "modref":"global.affine_controller__U511", + "ctrl__U444":{ + "modref":"global.affine_controller__U432", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U538":{ - "modref":"global.affine_controller__U526", + "ctrl__U458":{ + "modref":"global.affine_controller__U446", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U553":{ - "modref":"global.affine_controller__U541", + "ctrl__U472":{ + "modref":"global.affine_controller__U460", "metadata":{"garnet_rewire_flush":true} }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U435"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23325],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U435"} + "genargs":{"ID":["String","_U361"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23325],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -9674,8 +9282,8 @@ }, "ub_output_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U450"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[7213],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U450"} + "genargs":{"ID":["String","_U375"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[7213],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -9683,8 +9291,8 @@ }, "ub_output_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U465"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U465"} + "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -9692,8 +9300,8 @@ }, "ub_output_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U480"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U480"} + "genargs":{"ID":["String","_U403"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -9701,8 +9309,8 @@ }, "ub_output_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U495"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U495"} + "genargs":{"ID":["String","_U417"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -9710,8 +9318,8 @@ }, "ub_output_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U510"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U510"} + "genargs":{"ID":["String","_U431"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -9719,8 +9327,8 @@ }, "ub_output_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U525"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U525"} + "genargs":{"ID":["String","_U445"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -9728,8 +9336,8 @@ }, "ub_output_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U540"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U540"} + "genargs":{"ID":["String","_U459"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -9737,30 +9345,22 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U449.out"], - ["ub_output_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U464.out"], - ["ub_output_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U479.out"], - ["ub_output_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U494.out"], - ["ub_output_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U509.out"], - ["ub_output_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U524.out"], - ["ub_output_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U539.out"], - ["ub_output_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U554.out"], - ["self.clk","ctrl__U448.clk"], - ["ub_output_cgra_stencil_BANK_0.flush","ctrl__U448.valid"], - ["self.clk","ctrl__U463.clk"], - ["ub_output_cgra_stencil_BANK_1.flush","ctrl__U463.valid"], - ["self.clk","ctrl__U478.clk"], - ["ub_output_cgra_stencil_BANK_2.flush","ctrl__U478.valid"], - ["self.clk","ctrl__U493.clk"], - ["ub_output_cgra_stencil_BANK_3.flush","ctrl__U493.valid"], - ["self.clk","ctrl__U508.clk"], - ["ub_output_cgra_stencil_BANK_4.flush","ctrl__U508.valid"], - ["self.clk","ctrl__U523.clk"], - ["ub_output_cgra_stencil_BANK_5.flush","ctrl__U523.valid"], - ["self.clk","ctrl__U538.clk"], - ["ub_output_cgra_stencil_BANK_6.flush","ctrl__U538.valid"], - ["self.clk","ctrl__U553.clk"], - ["ub_output_cgra_stencil_BANK_7.flush","ctrl__U553.valid"], + ["self.clk","ctrl__U374.clk"], + ["ub_output_cgra_stencil_BANK_0.flush","ctrl__U374.valid"], + ["self.clk","ctrl__U388.clk"], + ["ub_output_cgra_stencil_BANK_1.flush","ctrl__U388.valid"], + ["self.clk","ctrl__U402.clk"], + ["ub_output_cgra_stencil_BANK_2.flush","ctrl__U402.valid"], + ["self.clk","ctrl__U416.clk"], + ["ub_output_cgra_stencil_BANK_3.flush","ctrl__U416.valid"], + ["self.clk","ctrl__U430.clk"], + ["ub_output_cgra_stencil_BANK_4.flush","ctrl__U430.valid"], + ["self.clk","ctrl__U444.clk"], + ["ub_output_cgra_stencil_BANK_5.flush","ctrl__U444.valid"], + ["self.clk","ctrl__U458.clk"], + ["ub_output_cgra_stencil_BANK_6.flush","ctrl__U458.valid"], + ["self.clk","ctrl__U472.clk"], + ["ub_output_cgra_stencil_BANK_7.flush","ctrl__U472.valid"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], @@ -9830,42 +9430,42 @@ ["op_hcompute_output_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U679":{ - "modref":"global.aff__U665" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U596":{ + "modref":"global.aff__U582" }, - "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U640":{ - "modref":"global.aff__U614" + "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U557":{ + "modref":"global.aff__U531" }, - "chain_en_const_U680":{ + "chain_en_const_U597":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U613":{ - "modref":"global.affine_controller__U556", + "ctrl__U530":{ + "modref":"global.affine_controller__U473", "metadata":{"garnet_remove":true} }, - "ctrl__U664":{ - "modref":"global.affine_controller__U641", + "ctrl__U581":{ + "modref":"global.affine_controller__U558", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[196320],"cycle_stride":[1],"dimensionality":1,"extent":[50176],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[77152],"cycle_stride":[1,32,448,16128,32256,64512],"dimensionality":6,"extent":[32,14,14,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,1792,32,896,25088]}},"mode":"glb","verilog_name":"glb__U555"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[196320],"cycle_stride":[1],"dimensionality":1,"extent":[50176],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[77152],"cycle_stride":[1,32,448,16128,32256,64512],"dimensionality":6,"extent":[32,14,14,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,1792,32,896,25088]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U664.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U679.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U679.out"], - ["ctrl__U613.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U640.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U640.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U680.out"], - ["self.clk","ctrl__U613.clk"], - ["self.reset","ctrl__U613.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U613.valid"], - ["self.clk","ctrl__U664.clk"], - ["self.reset","ctrl__U664.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U664.valid"], + ["ctrl__U581.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U596.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U596.out"], + ["ctrl__U530.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U557.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U557.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U597.out"], + ["self.clk","ctrl__U530.clk"], + ["self.reset","ctrl__U530.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U530.valid"], + ["self.clk","ctrl__U581.clk"], + ["self.reset","ctrl__U581.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U581.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_glb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -9884,12 +9484,12 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U714":{ + "_U631":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U719":{ + "_U636":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -9910,26 +9510,26 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U706" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U623" }, "op_hcompute_hw_output_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U707" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U624" }, "op_hcompute_hw_output_stencil_port_controller":{ - "modref":"global.affine_controller__U681", + "modref":"global.affine_controller__U598", "metadata":{"lake_config":{"stencil_valid":{"cycle_starting_addr":[196320],"cycle_stride":[1,64,1792],"dimensionality":3,"extent":[64,28,28]}}} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U704" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U621" }, "op_hcompute_hw_output_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U705" + "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U622" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U708" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U625" }, "op_hcompute_hw_output_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U709" + "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U626" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" @@ -9938,22 +9538,22 @@ "modref":"global.cu_op_hcompute_input_glb_stencil" }, "op_hcompute_input_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U717" + "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U634" }, "op_hcompute_input_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U715"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,928],"dimensionality":3,"extent":[16,58,58]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U715"} + "genargs":{"ID":["String","_U632"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,928],"dimensionality":3,"extent":[16,58,58]}},"mode":"lake"} }, "op_hcompute_input_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_glb_stencil_read_start":{ - "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U716" + "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U633" }, "op_hcompute_input_glb_stencil_write_start":{ - "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U718" + "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U635" }, "op_hcompute_kernel_cgra_stencil":{ "modref":"global.cu_op_hcompute_kernel_cgra_stencil" @@ -9962,22 +9562,22 @@ "modref":"global.cu_op_hcompute_kernel_glb_stencil" }, "op_hcompute_kernel_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U712" + "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U629" }, "op_hcompute_kernel_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U710"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,1024,3072],"dimensionality":4,"extent":[16,64,3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U710"} + "genargs":{"ID":["String","_U627"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,1024,3072],"dimensionality":4,"extent":[16,64,3,3]}},"mode":"lake"} }, "op_hcompute_kernel_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_kernel_glb_stencil_read_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U711" + "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U628" }, "op_hcompute_kernel_glb_stencil_write_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U713" + "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U630" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -10038,10 +9638,10 @@ } }, "connections":[ - ["self.clk","_U714.clk"], - ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U714.in"], - ["self.clk","_U719.clk"], - ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U719.in"], + ["self.clk","_U631.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U631.in"], + ["self.clk","_U636.clk"], + ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U636.in"], ["self.clk","input_cgra_stencil.clk"], ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], ["op_hcompute_output_cgra_stencil_10.input_cgra_stencil_op_hcompute_output_cgra_stencil_10_read","input_cgra_stencil.op_hcompute_output_cgra_stencil_10_read"], diff --git a/aha_garnet_design_new/resnet3_1/resnet3_1_garnet.json b/aha_garnet_design_new/resnet3_1/resnet3_1_garnet.json index 877d203e2..fac8a4dc0 100644 --- a/aha_garnet_design_new/resnet3_1/resnet3_1_garnet.json +++ b/aha_garnet_design_new/resnet3_1/resnet3_1_garnet.json @@ -232,2095 +232,2113 @@ }, "global":{ "modules":{ - "aff__U114":{ + "aff__U105":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U132":{ + "add_all__U123":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U133":{ + "add_all__U124":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U134":{ + "add_all__U125":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U135":{ + "add_all__U126":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U136":{ + "add_all__U127":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U137":{ + "add_all__U128":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U138":{ + "add_all__U129":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U139":{ + "add_all__U130":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U115":{ + "coeff_0_U106":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U117":{ + "coeff_1_U108":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_2_U119":{ + "coeff_2_U110":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000658"]} }, - "coeff_3_U121":{ + "coeff_3_U112":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_4_U123":{ + "coeff_4_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006920"]} }, - "coeff_5_U125":{ + "coeff_5_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U127":{ + "coeff_6_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000003a"]} }, - "coeff_7_U129":{ + "coeff_7_U120":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000d24"]} }, - "const_term_U131":{ + "const_term_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U116":{ + "mul_d0__U107":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U118":{ + "mul_d1__U109":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U120":{ + "mul_d2__U111":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U122":{ + "mul_d3__U113":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U124":{ + "mul_d4__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U126":{ + "mul_d5__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U128":{ + "mul_d6__U119":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U130":{ + "mul_d7__U121":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U116.out","add_all__U132.in0"], - ["mul_d1__U118.out","add_all__U132.in1"], - ["add_all__U133.in0","add_all__U132.out"], - ["mul_d2__U120.out","add_all__U133.in1"], - ["add_all__U134.in0","add_all__U133.out"], - ["mul_d3__U122.out","add_all__U134.in1"], - ["add_all__U135.in0","add_all__U134.out"], - ["mul_d4__U124.out","add_all__U135.in1"], - ["add_all__U136.in0","add_all__U135.out"], - ["mul_d5__U126.out","add_all__U136.in1"], - ["add_all__U137.in0","add_all__U136.out"], - ["mul_d6__U128.out","add_all__U137.in1"], - ["add_all__U138.in0","add_all__U137.out"], - ["mul_d7__U130.out","add_all__U138.in1"], - ["add_all__U139.in0","add_all__U138.out"], - ["const_term_U131.out","add_all__U139.in1"], - ["self.out","add_all__U139.out"], - ["mul_d0__U116.in0","coeff_0_U115.out"], - ["mul_d1__U118.in0","coeff_1_U117.out"], - ["mul_d2__U120.in0","coeff_2_U119.out"], - ["mul_d3__U122.in0","coeff_3_U121.out"], - ["mul_d4__U124.in0","coeff_4_U123.out"], - ["mul_d5__U126.in0","coeff_5_U125.out"], - ["mul_d6__U128.in0","coeff_6_U127.out"], - ["mul_d7__U130.in0","coeff_7_U129.out"], - ["self.d.0","mul_d0__U116.in1"], - ["self.d.1","mul_d1__U118.in1"], - ["self.d.2","mul_d2__U120.in1"], - ["self.d.3","mul_d3__U122.in1"], - ["self.d.4","mul_d4__U124.in1"], - ["self.d.5","mul_d5__U126.in1"], - ["self.d.6","mul_d6__U128.in1"], - ["self.d.7","mul_d7__U130.in1"] + ["mul_d0__U107.out","add_all__U123.in0"], + ["mul_d1__U109.out","add_all__U123.in1"], + ["add_all__U124.in0","add_all__U123.out"], + ["mul_d2__U111.out","add_all__U124.in1"], + ["add_all__U125.in0","add_all__U124.out"], + ["mul_d3__U113.out","add_all__U125.in1"], + ["add_all__U126.in0","add_all__U125.out"], + ["mul_d4__U115.out","add_all__U126.in1"], + ["add_all__U127.in0","add_all__U126.out"], + ["mul_d5__U117.out","add_all__U127.in1"], + ["add_all__U128.in0","add_all__U127.out"], + ["mul_d6__U119.out","add_all__U128.in1"], + ["add_all__U129.in0","add_all__U128.out"], + ["mul_d7__U121.out","add_all__U129.in1"], + ["add_all__U130.in0","add_all__U129.out"], + ["const_term_U122.out","add_all__U130.in1"], + ["self.out","add_all__U130.out"], + ["mul_d0__U107.in0","coeff_0_U106.out"], + ["mul_d1__U109.in0","coeff_1_U108.out"], + ["mul_d2__U111.in0","coeff_2_U110.out"], + ["mul_d3__U113.in0","coeff_3_U112.out"], + ["mul_d4__U115.in0","coeff_4_U114.out"], + ["mul_d5__U117.in0","coeff_5_U116.out"], + ["mul_d6__U119.in0","coeff_6_U118.out"], + ["mul_d7__U121.in0","coeff_7_U120.out"], + ["self.d.0","mul_d0__U107.in1"], + ["self.d.1","mul_d1__U109.in1"], + ["self.d.2","mul_d2__U111.in1"], + ["self.d.3","mul_d3__U113.in1"], + ["self.d.4","mul_d4__U115.in1"], + ["self.d.5","mul_d5__U117.in1"], + ["self.d.6","mul_d6__U119.in1"], + ["self.d.7","mul_d7__U121.in1"] ] }, - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000003a0"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U272":{ + "aff__U198":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U284":{ + "add_all__U210":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U285":{ + "add_all__U211":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U286":{ + "add_all__U212":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U287":{ + "add_all__U213":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U288":{ + "add_all__U214":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U273":{ + "coeff_0_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U275":{ + "coeff_1_U201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U277":{ + "coeff_2_U203":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U279":{ + "coeff_3_U205":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U281":{ + "coeff_4_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U283":{ + "const_term_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U274":{ + "mul_d0__U200":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U276":{ + "mul_d1__U202":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U278":{ + "mul_d2__U204":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U280":{ + "mul_d3__U206":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U282":{ + "mul_d4__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U274.out","add_all__U284.in0"], - ["mul_d1__U276.out","add_all__U284.in1"], - ["add_all__U285.in0","add_all__U284.out"], - ["mul_d2__U278.out","add_all__U285.in1"], - ["add_all__U286.in0","add_all__U285.out"], - ["mul_d3__U280.out","add_all__U286.in1"], - ["add_all__U287.in0","add_all__U286.out"], - ["mul_d4__U282.out","add_all__U287.in1"], - ["add_all__U288.in0","add_all__U287.out"], - ["const_term_U283.out","add_all__U288.in1"], - ["self.out","add_all__U288.out"], - ["mul_d0__U274.in0","coeff_0_U273.out"], - ["mul_d1__U276.in0","coeff_1_U275.out"], - ["mul_d2__U278.in0","coeff_2_U277.out"], - ["mul_d3__U280.in0","coeff_3_U279.out"], - ["mul_d4__U282.in0","coeff_4_U281.out"], - ["self.d.0","mul_d0__U274.in1"], - ["self.d.1","mul_d1__U276.in1"], - ["self.d.2","mul_d2__U278.in1"], - ["self.d.3","mul_d3__U280.in1"], - ["self.d.4","mul_d4__U282.in1"] + ["mul_d0__U200.out","add_all__U210.in0"], + ["mul_d1__U202.out","add_all__U210.in1"], + ["add_all__U211.in0","add_all__U210.out"], + ["mul_d2__U204.out","add_all__U211.in1"], + ["add_all__U212.in0","add_all__U211.out"], + ["mul_d3__U206.out","add_all__U212.in1"], + ["add_all__U213.in0","add_all__U212.out"], + ["mul_d4__U208.out","add_all__U213.in1"], + ["add_all__U214.in0","add_all__U213.out"], + ["const_term_U209.out","add_all__U214.in1"], + ["self.out","add_all__U214.out"], + ["mul_d0__U200.in0","coeff_0_U199.out"], + ["mul_d1__U202.in0","coeff_1_U201.out"], + ["mul_d2__U204.in0","coeff_2_U203.out"], + ["mul_d3__U206.in0","coeff_3_U205.out"], + ["mul_d4__U208.in0","coeff_4_U207.out"], + ["self.d.0","mul_d0__U200.in1"], + ["self.d.1","mul_d1__U202.in1"], + ["self.d.2","mul_d2__U204.in1"], + ["self.d.3","mul_d3__U206.in1"], + ["self.d.4","mul_d4__U208.in1"] ] }, - "aff__U302":{ + "aff__U228":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U303":{ + "coeff_0_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U305":{ + "coeff_1_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U307":{ + "coeff_2_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U309":{ + "coeff_3_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U311":{ + "coeff_4_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U304":{ + "mul_d0__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U306":{ + "mul_d1__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U308":{ + "mul_d2__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U310":{ + "mul_d3__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U312":{ + "mul_d4__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U304.out","add_all__U314.in0"], - ["mul_d1__U306.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U308.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U310.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U312.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["const_term_U313.out","add_all__U318.in1"], - ["self.out","add_all__U318.out"], - ["mul_d0__U304.in0","coeff_0_U303.out"], - ["mul_d1__U306.in0","coeff_1_U305.out"], - ["mul_d2__U308.in0","coeff_2_U307.out"], - ["mul_d3__U310.in0","coeff_3_U309.out"], - ["mul_d4__U312.in0","coeff_4_U311.out"], - ["self.d.0","mul_d0__U304.in1"], - ["self.d.1","mul_d1__U306.in1"], - ["self.d.2","mul_d2__U308.in1"], - ["self.d.3","mul_d3__U310.in1"], - ["self.d.4","mul_d4__U312.in1"] + ["mul_d0__U230.out","add_all__U240.in0"], + ["mul_d1__U232.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U234.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U236.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U238.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["const_term_U239.out","add_all__U244.in1"], + ["self.out","add_all__U244.out"], + ["mul_d0__U230.in0","coeff_0_U229.out"], + ["mul_d1__U232.in0","coeff_1_U231.out"], + ["mul_d2__U234.in0","coeff_2_U233.out"], + ["mul_d3__U236.in0","coeff_3_U235.out"], + ["mul_d4__U238.in0","coeff_4_U237.out"], + ["self.d.0","mul_d0__U230.in1"], + ["self.d.1","mul_d1__U232.in1"], + ["self.d.2","mul_d2__U234.in1"], + ["self.d.3","mul_d3__U236.in1"], + ["self.d.4","mul_d4__U238.in1"] ] }, - "aff__U321":{ + "aff__U247":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",10,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U343":{ + "add_all__U269":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U344":{ + "add_all__U270":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U345":{ + "add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U346":{ + "add_all__U272":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U347":{ + "add_all__U273":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U348":{ + "add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U349":{ + "add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U350":{ + "add_all__U276":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U351":{ + "add_all__U277":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U352":{ + "add_all__U278":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U322":{ + "coeff_0_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U324":{ + "coeff_1_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U326":{ + "coeff_2_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U328":{ + "coeff_3_U254":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U330":{ + "coeff_4_U256":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U332":{ + "coeff_5_U258":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_6_U334":{ + "coeff_6_U260":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_7_U336":{ + "coeff_7_U262":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_8_U338":{ + "coeff_8_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_9_U340":{ + "coeff_9_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U342":{ + "const_term_U268":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U323":{ + "mul_d0__U249":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U325":{ + "mul_d1__U251":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U327":{ + "mul_d2__U253":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U329":{ + "mul_d3__U255":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U331":{ + "mul_d4__U257":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U333":{ + "mul_d5__U259":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U335":{ + "mul_d6__U261":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U337":{ + "mul_d7__U263":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U339":{ + "mul_d8__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d9__U341":{ + "mul_d9__U267":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U323.out","add_all__U343.in0"], - ["mul_d1__U325.out","add_all__U343.in1"], - ["add_all__U344.in0","add_all__U343.out"], - ["mul_d2__U327.out","add_all__U344.in1"], - ["add_all__U345.in0","add_all__U344.out"], - ["mul_d3__U329.out","add_all__U345.in1"], - ["add_all__U346.in0","add_all__U345.out"], - ["mul_d4__U331.out","add_all__U346.in1"], - ["add_all__U347.in0","add_all__U346.out"], - ["mul_d5__U333.out","add_all__U347.in1"], - ["add_all__U348.in0","add_all__U347.out"], - ["mul_d6__U335.out","add_all__U348.in1"], - ["add_all__U349.in0","add_all__U348.out"], - ["mul_d7__U337.out","add_all__U349.in1"], - ["add_all__U350.in0","add_all__U349.out"], - ["mul_d8__U339.out","add_all__U350.in1"], - ["add_all__U351.in0","add_all__U350.out"], - ["mul_d9__U341.out","add_all__U351.in1"], - ["add_all__U352.in0","add_all__U351.out"], - ["const_term_U342.out","add_all__U352.in1"], - ["self.out","add_all__U352.out"], - ["mul_d0__U323.in0","coeff_0_U322.out"], - ["mul_d1__U325.in0","coeff_1_U324.out"], - ["mul_d2__U327.in0","coeff_2_U326.out"], - ["mul_d3__U329.in0","coeff_3_U328.out"], - ["mul_d4__U331.in0","coeff_4_U330.out"], - ["mul_d5__U333.in0","coeff_5_U332.out"], - ["mul_d6__U335.in0","coeff_6_U334.out"], - ["mul_d7__U337.in0","coeff_7_U336.out"], - ["mul_d8__U339.in0","coeff_8_U338.out"], - ["mul_d9__U341.in0","coeff_9_U340.out"], - ["self.d.0","mul_d0__U323.in1"], - ["self.d.1","mul_d1__U325.in1"], - ["self.d.2","mul_d2__U327.in1"], - ["self.d.3","mul_d3__U329.in1"], - ["self.d.4","mul_d4__U331.in1"], - ["self.d.5","mul_d5__U333.in1"], - ["self.d.6","mul_d6__U335.in1"], - ["self.d.7","mul_d7__U337.in1"], - ["self.d.8","mul_d8__U339.in1"], - ["self.d.9","mul_d9__U341.in1"] + ["mul_d0__U249.out","add_all__U269.in0"], + ["mul_d1__U251.out","add_all__U269.in1"], + ["add_all__U270.in0","add_all__U269.out"], + ["mul_d2__U253.out","add_all__U270.in1"], + ["add_all__U271.in0","add_all__U270.out"], + ["mul_d3__U255.out","add_all__U271.in1"], + ["add_all__U272.in0","add_all__U271.out"], + ["mul_d4__U257.out","add_all__U272.in1"], + ["add_all__U273.in0","add_all__U272.out"], + ["mul_d5__U259.out","add_all__U273.in1"], + ["add_all__U274.in0","add_all__U273.out"], + ["mul_d6__U261.out","add_all__U274.in1"], + ["add_all__U275.in0","add_all__U274.out"], + ["mul_d7__U263.out","add_all__U275.in1"], + ["add_all__U276.in0","add_all__U275.out"], + ["mul_d8__U265.out","add_all__U276.in1"], + ["add_all__U277.in0","add_all__U276.out"], + ["mul_d9__U267.out","add_all__U277.in1"], + ["add_all__U278.in0","add_all__U277.out"], + ["const_term_U268.out","add_all__U278.in1"], + ["self.out","add_all__U278.out"], + ["mul_d0__U249.in0","coeff_0_U248.out"], + ["mul_d1__U251.in0","coeff_1_U250.out"], + ["mul_d2__U253.in0","coeff_2_U252.out"], + ["mul_d3__U255.in0","coeff_3_U254.out"], + ["mul_d4__U257.in0","coeff_4_U256.out"], + ["mul_d5__U259.in0","coeff_5_U258.out"], + ["mul_d6__U261.in0","coeff_6_U260.out"], + ["mul_d7__U263.in0","coeff_7_U262.out"], + ["mul_d8__U265.in0","coeff_8_U264.out"], + ["mul_d9__U267.in0","coeff_9_U266.out"], + ["self.d.0","mul_d0__U249.in1"], + ["self.d.1","mul_d1__U251.in1"], + ["self.d.2","mul_d2__U253.in1"], + ["self.d.3","mul_d3__U255.in1"], + ["self.d.4","mul_d4__U257.in1"], + ["self.d.5","mul_d5__U259.in1"], + ["self.d.6","mul_d6__U261.in1"], + ["self.d.7","mul_d7__U263.in1"], + ["self.d.8","mul_d8__U265.in1"], + ["self.d.9","mul_d9__U267.in1"] + ] + }, + "aff__U32":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U42":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U43":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U44":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U45":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "coeff_2_U37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000003a"]} + }, + "coeff_3_U39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000d24"]} + }, + "const_term_U41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U34":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U36":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U38":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U40":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U401":{ + "aff__U327":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",10,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U423":{ + "add_all__U349":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U424":{ + "add_all__U350":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U425":{ + "add_all__U351":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U426":{ + "add_all__U352":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U427":{ + "add_all__U353":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U428":{ + "add_all__U354":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U429":{ + "add_all__U355":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U430":{ + "add_all__U356":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U431":{ + "add_all__U357":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U432":{ + "add_all__U358":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U402":{ + "coeff_0_U328":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U404":{ + "coeff_1_U330":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U406":{ + "coeff_2_U332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_3_U408":{ + "coeff_3_U334":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_4_U410":{ + "coeff_4_U336":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_5_U412":{ + "coeff_5_U338":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U414":{ + "coeff_6_U340":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_7_U416":{ + "coeff_7_U342":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_8_U418":{ + "coeff_8_U344":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_9_U420":{ + "coeff_9_U346":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U422":{ + "const_term_U348":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U403":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U405":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U407":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U409":{ + "mul_d0__U329":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U411":{ + "mul_d1__U331":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U413":{ + "mul_d2__U333":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U415":{ + "mul_d3__U335":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U417":{ + "mul_d4__U337":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U419":{ + "mul_d5__U339":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d9__U421":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U403.out","add_all__U423.in0"], - ["mul_d1__U405.out","add_all__U423.in1"], - ["add_all__U424.in0","add_all__U423.out"], - ["mul_d2__U407.out","add_all__U424.in1"], - ["add_all__U425.in0","add_all__U424.out"], - ["mul_d3__U409.out","add_all__U425.in1"], - ["add_all__U426.in0","add_all__U425.out"], - ["mul_d4__U411.out","add_all__U426.in1"], - ["add_all__U427.in0","add_all__U426.out"], - ["mul_d5__U413.out","add_all__U427.in1"], - ["add_all__U428.in0","add_all__U427.out"], - ["mul_d6__U415.out","add_all__U428.in1"], - ["add_all__U429.in0","add_all__U428.out"], - ["mul_d7__U417.out","add_all__U429.in1"], - ["add_all__U430.in0","add_all__U429.out"], - ["mul_d8__U419.out","add_all__U430.in1"], - ["add_all__U431.in0","add_all__U430.out"], - ["mul_d9__U421.out","add_all__U431.in1"], - ["add_all__U432.in0","add_all__U431.out"], - ["const_term_U422.out","add_all__U432.in1"], - ["self.out","add_all__U432.out"], - ["mul_d0__U403.in0","coeff_0_U402.out"], - ["mul_d1__U405.in0","coeff_1_U404.out"], - ["mul_d2__U407.in0","coeff_2_U406.out"], - ["mul_d3__U409.in0","coeff_3_U408.out"], - ["mul_d4__U411.in0","coeff_4_U410.out"], - ["mul_d5__U413.in0","coeff_5_U412.out"], - ["mul_d6__U415.in0","coeff_6_U414.out"], - ["mul_d7__U417.in0","coeff_7_U416.out"], - ["mul_d8__U419.in0","coeff_8_U418.out"], - ["mul_d9__U421.in0","coeff_9_U420.out"], - ["self.d.0","mul_d0__U403.in1"], - ["self.d.1","mul_d1__U405.in1"], - ["self.d.2","mul_d2__U407.in1"], - ["self.d.3","mul_d3__U409.in1"], - ["self.d.4","mul_d4__U411.in1"], - ["self.d.5","mul_d5__U413.in1"], - ["self.d.6","mul_d6__U415.in1"], - ["self.d.7","mul_d7__U417.in1"], - ["self.d.8","mul_d8__U419.in1"], - ["self.d.9","mul_d9__U421.in1"] - ] - }, - "aff__U41":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U51":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U52":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U53":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U54":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U42":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U44":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_2_U46":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003a"]} - }, - "coeff_3_U48":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000d24"]} - }, - "const_term_U50":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U43":{ + "mul_d6__U341":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d7__U343":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d8__U345":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d9__U347":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U329.out","add_all__U349.in0"], + ["mul_d1__U331.out","add_all__U349.in1"], + ["add_all__U350.in0","add_all__U349.out"], + ["mul_d2__U333.out","add_all__U350.in1"], + ["add_all__U351.in0","add_all__U350.out"], + ["mul_d3__U335.out","add_all__U351.in1"], + ["add_all__U352.in0","add_all__U351.out"], + ["mul_d4__U337.out","add_all__U352.in1"], + ["add_all__U353.in0","add_all__U352.out"], + ["mul_d5__U339.out","add_all__U353.in1"], + ["add_all__U354.in0","add_all__U353.out"], + ["mul_d6__U341.out","add_all__U354.in1"], + ["add_all__U355.in0","add_all__U354.out"], + ["mul_d7__U343.out","add_all__U355.in1"], + ["add_all__U356.in0","add_all__U355.out"], + ["mul_d8__U345.out","add_all__U356.in1"], + ["add_all__U357.in0","add_all__U356.out"], + ["mul_d9__U347.out","add_all__U357.in1"], + ["add_all__U358.in0","add_all__U357.out"], + ["const_term_U348.out","add_all__U358.in1"], + ["self.out","add_all__U358.out"], + ["mul_d0__U329.in0","coeff_0_U328.out"], + ["mul_d1__U331.in0","coeff_1_U330.out"], + ["mul_d2__U333.in0","coeff_2_U332.out"], + ["mul_d3__U335.in0","coeff_3_U334.out"], + ["mul_d4__U337.in0","coeff_4_U336.out"], + ["mul_d5__U339.in0","coeff_5_U338.out"], + ["mul_d6__U341.in0","coeff_6_U340.out"], + ["mul_d7__U343.in0","coeff_7_U342.out"], + ["mul_d8__U345.in0","coeff_8_U344.out"], + ["mul_d9__U347.in0","coeff_9_U346.out"], + ["self.d.0","mul_d0__U329.in1"], + ["self.d.1","mul_d1__U331.in1"], + ["self.d.2","mul_d2__U333.in1"], + ["self.d.3","mul_d3__U335.in1"], + ["self.d.4","mul_d4__U337.in1"], + ["self.d.5","mul_d5__U339.in1"], + ["self.d.6","mul_d6__U341.in1"], + ["self.d.7","mul_d7__U343.in1"], + ["self.d.8","mul_d8__U345.in1"], + ["self.d.9","mul_d9__U347.in1"] ] }, - "aff__U437":{ + "aff__U363":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U443":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U444":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U364":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U366":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U442":{ + "const_term_U368":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U439":{ + "mul_d0__U365":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U367":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U443.in0"], - ["mul_d1__U441.out","add_all__U443.in1"], - ["add_all__U444.in0","add_all__U443.out"], - ["const_term_U442.out","add_all__U444.in1"], - ["self.out","add_all__U444.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"] + ["mul_d0__U365.out","add_all__U369.in0"], + ["mul_d1__U367.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["const_term_U368.out","add_all__U370.in1"], + ["self.out","add_all__U370.out"], + ["mul_d0__U365.in0","coeff_0_U364.out"], + ["mul_d1__U367.in0","coeff_1_U366.out"], + ["self.d.0","mul_d0__U365.in1"], + ["self.d.1","mul_d1__U367.in1"] ] }, - "aff__U452":{ + "aff__U377":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U458":{ + "add_all__U383":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U459":{ + "add_all__U384":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U453":{ + "coeff_0_U378":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U455":{ + "coeff_1_U380":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U457":{ + "const_term_U382":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U454":{ + "mul_d0__U379":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U456":{ + "mul_d1__U381":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U454.out","add_all__U458.in0"], - ["mul_d1__U456.out","add_all__U458.in1"], - ["add_all__U459.in0","add_all__U458.out"], - ["const_term_U457.out","add_all__U459.in1"], - ["self.out","add_all__U459.out"], - ["mul_d0__U454.in0","coeff_0_U453.out"], - ["mul_d1__U456.in0","coeff_1_U455.out"], - ["self.d.0","mul_d0__U454.in1"], - ["self.d.1","mul_d1__U456.in1"] + ["mul_d0__U379.out","add_all__U383.in0"], + ["mul_d1__U381.out","add_all__U383.in1"], + ["add_all__U384.in0","add_all__U383.out"], + ["const_term_U382.out","add_all__U384.in1"], + ["self.out","add_all__U384.out"], + ["mul_d0__U379.in0","coeff_0_U378.out"], + ["mul_d1__U381.in0","coeff_1_U380.out"], + ["self.d.0","mul_d0__U379.in1"], + ["self.d.1","mul_d1__U381.in1"] ] }, - "aff__U467":{ + "aff__U391":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U473":{ + "add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U474":{ + "add_all__U398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U468":{ + "coeff_0_U392":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U470":{ + "coeff_1_U394":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U472":{ + "const_term_U396":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U469":{ + "mul_d0__U393":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U471":{ + "mul_d1__U395":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U469.out","add_all__U473.in0"], - ["mul_d1__U471.out","add_all__U473.in1"], - ["add_all__U474.in0","add_all__U473.out"], - ["const_term_U472.out","add_all__U474.in1"], - ["self.out","add_all__U474.out"], - ["mul_d0__U469.in0","coeff_0_U468.out"], - ["mul_d1__U471.in0","coeff_1_U470.out"], - ["self.d.0","mul_d0__U469.in1"], - ["self.d.1","mul_d1__U471.in1"] + ["mul_d0__U393.out","add_all__U397.in0"], + ["mul_d1__U395.out","add_all__U397.in1"], + ["add_all__U398.in0","add_all__U397.out"], + ["const_term_U396.out","add_all__U398.in1"], + ["self.out","add_all__U398.out"], + ["mul_d0__U393.in0","coeff_0_U392.out"], + ["mul_d1__U395.in0","coeff_1_U394.out"], + ["self.d.0","mul_d0__U393.in1"], + ["self.d.1","mul_d1__U395.in1"] ] }, - "aff__U482":{ + "aff__U405":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U488":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U489":{ + "add_all__U412":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U406":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U487":{ + "const_term_U410":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U484":{ + "mul_d0__U407":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U409":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U488.in0"], - ["mul_d1__U486.out","add_all__U488.in1"], - ["add_all__U489.in0","add_all__U488.out"], - ["const_term_U487.out","add_all__U489.in1"], - ["self.out","add_all__U489.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"] + ["mul_d0__U407.out","add_all__U411.in0"], + ["mul_d1__U409.out","add_all__U411.in1"], + ["add_all__U412.in0","add_all__U411.out"], + ["const_term_U410.out","add_all__U412.in1"], + ["self.out","add_all__U412.out"], + ["mul_d0__U407.in0","coeff_0_U406.out"], + ["mul_d1__U409.in0","coeff_1_U408.out"], + ["self.d.0","mul_d0__U407.in1"], + ["self.d.1","mul_d1__U409.in1"] ] }, - "aff__U497":{ + "aff__U419":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U503":{ + "add_all__U425":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U504":{ + "add_all__U426":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U498":{ + "coeff_0_U420":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U500":{ + "coeff_1_U422":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U502":{ + "const_term_U424":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U499":{ + "mul_d0__U421":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U501":{ + "mul_d1__U423":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U499.out","add_all__U503.in0"], - ["mul_d1__U501.out","add_all__U503.in1"], - ["add_all__U504.in0","add_all__U503.out"], - ["const_term_U502.out","add_all__U504.in1"], - ["self.out","add_all__U504.out"], - ["mul_d0__U499.in0","coeff_0_U498.out"], - ["mul_d1__U501.in0","coeff_1_U500.out"], - ["self.d.0","mul_d0__U499.in1"], - ["self.d.1","mul_d1__U501.in1"] + ["mul_d0__U421.out","add_all__U425.in0"], + ["mul_d1__U423.out","add_all__U425.in1"], + ["add_all__U426.in0","add_all__U425.out"], + ["const_term_U424.out","add_all__U426.in1"], + ["self.out","add_all__U426.out"], + ["mul_d0__U421.in0","coeff_0_U420.out"], + ["mul_d1__U423.in0","coeff_1_U422.out"], + ["self.d.0","mul_d0__U421.in1"], + ["self.d.1","mul_d1__U423.in1"] ] }, - "aff__U512":{ + "aff__U433":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U518":{ + "add_all__U439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U519":{ + "add_all__U440":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U513":{ + "coeff_0_U434":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U515":{ + "coeff_1_U436":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U517":{ + "const_term_U438":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U514":{ + "mul_d0__U435":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U516":{ + "mul_d1__U437":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U514.out","add_all__U518.in0"], - ["mul_d1__U516.out","add_all__U518.in1"], - ["add_all__U519.in0","add_all__U518.out"], - ["const_term_U517.out","add_all__U519.in1"], - ["self.out","add_all__U519.out"], - ["mul_d0__U514.in0","coeff_0_U513.out"], - ["mul_d1__U516.in0","coeff_1_U515.out"], - ["self.d.0","mul_d0__U514.in1"], - ["self.d.1","mul_d1__U516.in1"] + ["mul_d0__U435.out","add_all__U439.in0"], + ["mul_d1__U437.out","add_all__U439.in1"], + ["add_all__U440.in0","add_all__U439.out"], + ["const_term_U438.out","add_all__U440.in1"], + ["self.out","add_all__U440.out"], + ["mul_d0__U435.in0","coeff_0_U434.out"], + ["mul_d1__U437.in0","coeff_1_U436.out"], + ["self.d.0","mul_d0__U435.in1"], + ["self.d.1","mul_d1__U437.in1"] ] }, - "aff__U527":{ + "aff__U447":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U533":{ + "add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U534":{ + "add_all__U454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U528":{ + "coeff_0_U448":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U530":{ + "coeff_1_U450":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U532":{ + "const_term_U452":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U529":{ + "mul_d0__U449":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U531":{ + "mul_d1__U451":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U529.out","add_all__U533.in0"], - ["mul_d1__U531.out","add_all__U533.in1"], - ["add_all__U534.in0","add_all__U533.out"], - ["const_term_U532.out","add_all__U534.in1"], - ["self.out","add_all__U534.out"], - ["mul_d0__U529.in0","coeff_0_U528.out"], - ["mul_d1__U531.in0","coeff_1_U530.out"], - ["self.d.0","mul_d0__U529.in1"], - ["self.d.1","mul_d1__U531.in1"] + ["mul_d0__U449.out","add_all__U453.in0"], + ["mul_d1__U451.out","add_all__U453.in1"], + ["add_all__U454.in0","add_all__U453.out"], + ["const_term_U452.out","add_all__U454.in1"], + ["self.out","add_all__U454.out"], + ["mul_d0__U449.in0","coeff_0_U448.out"], + ["mul_d1__U451.in0","coeff_1_U450.out"], + ["self.d.0","mul_d0__U449.in1"], + ["self.d.1","mul_d1__U451.in1"] ] }, - "aff__U542":{ + "aff__U461":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U548":{ + "add_all__U467":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U549":{ + "add_all__U468":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U543":{ + "coeff_0_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U545":{ + "coeff_1_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U547":{ + "const_term_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U544":{ + "mul_d0__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U546":{ + "mul_d1__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U544.out","add_all__U548.in0"], - ["mul_d1__U546.out","add_all__U548.in1"], - ["add_all__U549.in0","add_all__U548.out"], - ["const_term_U547.out","add_all__U549.in1"], - ["self.out","add_all__U549.out"], - ["mul_d0__U544.in0","coeff_0_U543.out"], - ["mul_d1__U546.in0","coeff_1_U545.out"], - ["self.d.0","mul_d0__U544.in1"], - ["self.d.1","mul_d1__U546.in1"] + ["mul_d0__U463.out","add_all__U467.in0"], + ["mul_d1__U465.out","add_all__U467.in1"], + ["add_all__U468.in0","add_all__U467.out"], + ["const_term_U466.out","add_all__U468.in1"], + ["self.out","add_all__U468.out"], + ["mul_d0__U463.in0","coeff_0_U462.out"], + ["mul_d1__U465.in0","coeff_1_U464.out"], + ["self.d.0","mul_d0__U463.in1"], + ["self.d.1","mul_d1__U465.in1"] ] }, - "aff__U557":{ + "aff__U474":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U575":{ + "add_all__U492":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U576":{ + "add_all__U493":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U577":{ + "add_all__U494":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U578":{ + "add_all__U495":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U579":{ + "add_all__U496":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U580":{ + "add_all__U497":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U581":{ + "add_all__U498":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U582":{ + "add_all__U499":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U558":{ + "coeff_0_U475":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U560":{ + "coeff_1_U477":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U562":{ + "coeff_2_U479":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U564":{ + "coeff_3_U481":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U566":{ + "coeff_4_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_5_U568":{ + "coeff_5_U485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_6_U570":{ + "coeff_6_U487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U572":{ + "coeff_7_U489":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U574":{ + "const_term_U491":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012d60"]} }, - "mul_d0__U559":{ + "mul_d0__U476":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U561":{ + "mul_d1__U478":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U563":{ + "mul_d2__U480":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U565":{ + "mul_d3__U482":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U567":{ + "mul_d4__U484":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U569":{ + "mul_d5__U486":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U571":{ + "mul_d6__U488":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U573":{ + "mul_d7__U490":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U559.out","add_all__U575.in0"], - ["mul_d1__U561.out","add_all__U575.in1"], - ["add_all__U576.in0","add_all__U575.out"], - ["mul_d2__U563.out","add_all__U576.in1"], - ["add_all__U577.in0","add_all__U576.out"], - ["mul_d3__U565.out","add_all__U577.in1"], - ["add_all__U578.in0","add_all__U577.out"], - ["mul_d4__U567.out","add_all__U578.in1"], - ["add_all__U579.in0","add_all__U578.out"], - ["mul_d5__U569.out","add_all__U579.in1"], - ["add_all__U580.in0","add_all__U579.out"], - ["mul_d6__U571.out","add_all__U580.in1"], - ["add_all__U581.in0","add_all__U580.out"], - ["mul_d7__U573.out","add_all__U581.in1"], - ["add_all__U582.in0","add_all__U581.out"], - ["const_term_U574.out","add_all__U582.in1"], - ["self.out","add_all__U582.out"], - ["mul_d0__U559.in0","coeff_0_U558.out"], - ["mul_d1__U561.in0","coeff_1_U560.out"], - ["mul_d2__U563.in0","coeff_2_U562.out"], - ["mul_d3__U565.in0","coeff_3_U564.out"], - ["mul_d4__U567.in0","coeff_4_U566.out"], - ["mul_d5__U569.in0","coeff_5_U568.out"], - ["mul_d6__U571.in0","coeff_6_U570.out"], - ["mul_d7__U573.in0","coeff_7_U572.out"], - ["self.d.0","mul_d0__U559.in1"], - ["self.d.1","mul_d1__U561.in1"], - ["self.d.2","mul_d2__U563.in1"], - ["self.d.3","mul_d3__U565.in1"], - ["self.d.4","mul_d4__U567.in1"], - ["self.d.5","mul_d5__U569.in1"], - ["self.d.6","mul_d6__U571.in1"], - ["self.d.7","mul_d7__U573.in1"] + ["mul_d0__U476.out","add_all__U492.in0"], + ["mul_d1__U478.out","add_all__U492.in1"], + ["add_all__U493.in0","add_all__U492.out"], + ["mul_d2__U480.out","add_all__U493.in1"], + ["add_all__U494.in0","add_all__U493.out"], + ["mul_d3__U482.out","add_all__U494.in1"], + ["add_all__U495.in0","add_all__U494.out"], + ["mul_d4__U484.out","add_all__U495.in1"], + ["add_all__U496.in0","add_all__U495.out"], + ["mul_d5__U486.out","add_all__U496.in1"], + ["add_all__U497.in0","add_all__U496.out"], + ["mul_d6__U488.out","add_all__U497.in1"], + ["add_all__U498.in0","add_all__U497.out"], + ["mul_d7__U490.out","add_all__U498.in1"], + ["add_all__U499.in0","add_all__U498.out"], + ["const_term_U491.out","add_all__U499.in1"], + ["self.out","add_all__U499.out"], + ["mul_d0__U476.in0","coeff_0_U475.out"], + ["mul_d1__U478.in0","coeff_1_U477.out"], + ["mul_d2__U480.in0","coeff_2_U479.out"], + ["mul_d3__U482.in0","coeff_3_U481.out"], + ["mul_d4__U484.in0","coeff_4_U483.out"], + ["mul_d5__U486.in0","coeff_5_U485.out"], + ["mul_d6__U488.in0","coeff_6_U487.out"], + ["mul_d7__U490.in0","coeff_7_U489.out"], + ["self.d.0","mul_d0__U476.in1"], + ["self.d.1","mul_d1__U478.in1"], + ["self.d.2","mul_d2__U480.in1"], + ["self.d.3","mul_d3__U482.in1"], + ["self.d.4","mul_d4__U484.in1"], + ["self.d.5","mul_d5__U486.in1"], + ["self.d.6","mul_d6__U488.in1"], + ["self.d.7","mul_d7__U490.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U77":{ + "add_all__U68":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U78":{ + "add_all__U69":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U79":{ + "add_all__U70":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U80":{ + "add_all__U71":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U81":{ + "add_all__U72":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U82":{ + "add_all__U73":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000f0"]} }, - "coeff_6_U70":{ + "coeff_6_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U72":{ + "coeff_7_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U74":{ + "const_term_U65":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U71":{ + "mul_d6__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U73":{ + "mul_d7__U64":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U75.in0"], - ["mul_d1__U61.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["mul_d2__U63.out","add_all__U76.in1"], - ["add_all__U77.in0","add_all__U76.out"], - ["mul_d3__U65.out","add_all__U77.in1"], - ["add_all__U78.in0","add_all__U77.out"], - ["mul_d4__U67.out","add_all__U78.in1"], - ["add_all__U79.in0","add_all__U78.out"], - ["mul_d5__U69.out","add_all__U79.in1"], - ["add_all__U80.in0","add_all__U79.out"], - ["mul_d6__U71.out","add_all__U80.in1"], - ["add_all__U81.in0","add_all__U80.out"], - ["mul_d7__U73.out","add_all__U81.in1"], - ["add_all__U82.in0","add_all__U81.out"], - ["const_term_U74.out","add_all__U82.in1"], - ["self.out","add_all__U82.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["mul_d6__U71.in0","coeff_6_U70.out"], - ["mul_d7__U73.in0","coeff_7_U72.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"], - ["self.d.6","mul_d6__U71.in1"], - ["self.d.7","mul_d7__U73.in1"] + ["mul_d0__U50.out","add_all__U66.in0"], + ["mul_d1__U52.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["mul_d2__U54.out","add_all__U67.in1"], + ["add_all__U68.in0","add_all__U67.out"], + ["mul_d3__U56.out","add_all__U68.in1"], + ["add_all__U69.in0","add_all__U68.out"], + ["mul_d4__U58.out","add_all__U69.in1"], + ["add_all__U70.in0","add_all__U69.out"], + ["mul_d5__U60.out","add_all__U70.in1"], + ["add_all__U71.in0","add_all__U70.out"], + ["mul_d6__U62.out","add_all__U71.in1"], + ["add_all__U72.in0","add_all__U71.out"], + ["mul_d7__U64.out","add_all__U72.in1"], + ["add_all__U73.in0","add_all__U72.out"], + ["const_term_U65.out","add_all__U73.in1"], + ["self.out","add_all__U73.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["mul_d6__U62.in0","coeff_6_U61.out"], + ["mul_d7__U64.in0","coeff_7_U63.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"], + ["self.d.6","mul_d6__U62.in1"], + ["self.d.7","mul_d7__U64.in1"] ] }, - "aff__U614":{ + "aff__U531":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U632":{ + "add_all__U549":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U633":{ + "add_all__U550":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U634":{ + "add_all__U551":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U635":{ + "add_all__U552":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U636":{ + "add_all__U553":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U637":{ + "add_all__U554":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U638":{ + "add_all__U555":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U639":{ + "add_all__U556":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U615":{ + "coeff_0_U532":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U617":{ + "coeff_1_U534":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000e"]} }, - "coeff_2_U619":{ + "coeff_2_U536":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_3_U621":{ + "coeff_3_U538":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006200"]} }, - "coeff_4_U623":{ + "coeff_4_U540":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_5_U625":{ + "coeff_5_U542":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_6_U627":{ + "coeff_6_U544":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001880"]} }, - "coeff_7_U629":{ + "coeff_7_U546":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000310"]} }, - "const_term_U631":{ + "const_term_U548":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U616":{ + "mul_d0__U533":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U618":{ + "mul_d1__U535":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U620":{ + "mul_d2__U537":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U622":{ + "mul_d3__U539":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U624":{ + "mul_d4__U541":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U626":{ + "mul_d5__U543":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U628":{ + "mul_d6__U545":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U630":{ + "mul_d7__U547":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U616.out","add_all__U632.in0"], - ["mul_d1__U618.out","add_all__U632.in1"], - ["add_all__U633.in0","add_all__U632.out"], - ["mul_d2__U620.out","add_all__U633.in1"], - ["add_all__U634.in0","add_all__U633.out"], - ["mul_d3__U622.out","add_all__U634.in1"], - ["add_all__U635.in0","add_all__U634.out"], - ["mul_d4__U624.out","add_all__U635.in1"], - ["add_all__U636.in0","add_all__U635.out"], - ["mul_d5__U626.out","add_all__U636.in1"], - ["add_all__U637.in0","add_all__U636.out"], - ["mul_d6__U628.out","add_all__U637.in1"], - ["add_all__U638.in0","add_all__U637.out"], - ["mul_d7__U630.out","add_all__U638.in1"], - ["add_all__U639.in0","add_all__U638.out"], - ["const_term_U631.out","add_all__U639.in1"], - ["self.out","add_all__U639.out"], - ["mul_d0__U616.in0","coeff_0_U615.out"], - ["mul_d1__U618.in0","coeff_1_U617.out"], - ["mul_d2__U620.in0","coeff_2_U619.out"], - ["mul_d3__U622.in0","coeff_3_U621.out"], - ["mul_d4__U624.in0","coeff_4_U623.out"], - ["mul_d5__U626.in0","coeff_5_U625.out"], - ["mul_d6__U628.in0","coeff_6_U627.out"], - ["mul_d7__U630.in0","coeff_7_U629.out"], - ["self.d.0","mul_d0__U616.in1"], - ["self.d.1","mul_d1__U618.in1"], - ["self.d.2","mul_d2__U620.in1"], - ["self.d.3","mul_d3__U622.in1"], - ["self.d.4","mul_d4__U624.in1"], - ["self.d.5","mul_d5__U626.in1"], - ["self.d.6","mul_d6__U628.in1"], - ["self.d.7","mul_d7__U630.in1"] + ["mul_d0__U533.out","add_all__U549.in0"], + ["mul_d1__U535.out","add_all__U549.in1"], + ["add_all__U550.in0","add_all__U549.out"], + ["mul_d2__U537.out","add_all__U550.in1"], + ["add_all__U551.in0","add_all__U550.out"], + ["mul_d3__U539.out","add_all__U551.in1"], + ["add_all__U552.in0","add_all__U551.out"], + ["mul_d4__U541.out","add_all__U552.in1"], + ["add_all__U553.in0","add_all__U552.out"], + ["mul_d5__U543.out","add_all__U553.in1"], + ["add_all__U554.in0","add_all__U553.out"], + ["mul_d6__U545.out","add_all__U554.in1"], + ["add_all__U555.in0","add_all__U554.out"], + ["mul_d7__U547.out","add_all__U555.in1"], + ["add_all__U556.in0","add_all__U555.out"], + ["const_term_U548.out","add_all__U556.in1"], + ["self.out","add_all__U556.out"], + ["mul_d0__U533.in0","coeff_0_U532.out"], + ["mul_d1__U535.in0","coeff_1_U534.out"], + ["mul_d2__U537.in0","coeff_2_U536.out"], + ["mul_d3__U539.in0","coeff_3_U538.out"], + ["mul_d4__U541.in0","coeff_4_U540.out"], + ["mul_d5__U543.in0","coeff_5_U542.out"], + ["mul_d6__U545.in0","coeff_6_U544.out"], + ["mul_d7__U547.in0","coeff_7_U546.out"], + ["self.d.0","mul_d0__U533.in1"], + ["self.d.1","mul_d1__U535.in1"], + ["self.d.2","mul_d2__U537.in1"], + ["self.d.3","mul_d3__U539.in1"], + ["self.d.4","mul_d4__U541.in1"], + ["self.d.5","mul_d5__U543.in1"], + ["self.d.6","mul_d6__U545.in1"], + ["self.d.7","mul_d7__U547.in1"] ] }, - "aff__U642":{ + "aff__U559":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U652":{ + "add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U653":{ + "add_all__U570":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U654":{ + "add_all__U571":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U655":{ + "add_all__U572":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U643":{ + "coeff_0_U560":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U645":{ + "coeff_1_U562":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000700"]} }, - "coeff_2_U647":{ + "coeff_2_U564":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U649":{ + "coeff_3_U566":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U651":{ + "const_term_U568":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} }, - "mul_d0__U644":{ + "mul_d0__U561":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U646":{ + "mul_d1__U563":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U648":{ + "mul_d2__U565":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U650":{ + "mul_d3__U567":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U644.out","add_all__U652.in0"], - ["mul_d1__U646.out","add_all__U652.in1"], - ["add_all__U653.in0","add_all__U652.out"], - ["mul_d2__U648.out","add_all__U653.in1"], - ["add_all__U654.in0","add_all__U653.out"], - ["mul_d3__U650.out","add_all__U654.in1"], - ["add_all__U655.in0","add_all__U654.out"], - ["const_term_U651.out","add_all__U655.in1"], - ["self.out","add_all__U655.out"], - ["mul_d0__U644.in0","coeff_0_U643.out"], - ["mul_d1__U646.in0","coeff_1_U645.out"], - ["mul_d2__U648.in0","coeff_2_U647.out"], - ["mul_d3__U650.in0","coeff_3_U649.out"], - ["self.d.0","mul_d0__U644.in1"], - ["self.d.1","mul_d1__U646.in1"], - ["self.d.2","mul_d2__U648.in1"], - ["self.d.3","mul_d3__U650.in1"] + ["mul_d0__U561.out","add_all__U569.in0"], + ["mul_d1__U563.out","add_all__U569.in1"], + ["add_all__U570.in0","add_all__U569.out"], + ["mul_d2__U565.out","add_all__U570.in1"], + ["add_all__U571.in0","add_all__U570.out"], + ["mul_d3__U567.out","add_all__U571.in1"], + ["add_all__U572.in0","add_all__U571.out"], + ["const_term_U568.out","add_all__U572.in1"], + ["self.out","add_all__U572.out"], + ["mul_d0__U561.in0","coeff_0_U560.out"], + ["mul_d1__U563.in0","coeff_1_U562.out"], + ["mul_d2__U565.in0","coeff_2_U564.out"], + ["mul_d3__U567.in0","coeff_3_U566.out"], + ["self.d.0","mul_d0__U561.in1"], + ["self.d.1","mul_d1__U563.in1"], + ["self.d.2","mul_d2__U565.in1"], + ["self.d.3","mul_d3__U567.in1"] ] }, - "aff__U665":{ + "aff__U582":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U675":{ + "add_all__U592":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U676":{ + "add_all__U593":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U677":{ + "add_all__U594":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U678":{ + "add_all__U595":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U666":{ + "coeff_0_U583":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U668":{ + "coeff_1_U585":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U670":{ + "coeff_2_U587":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_3_U672":{ + "coeff_3_U589":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000310"]} }, - "const_term_U674":{ + "const_term_U591":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U667":{ + "mul_d0__U584":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U669":{ + "mul_d1__U586":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U671":{ + "mul_d2__U588":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U673":{ + "mul_d3__U590":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U667.out","add_all__U675.in0"], - ["mul_d1__U669.out","add_all__U675.in1"], - ["add_all__U676.in0","add_all__U675.out"], - ["mul_d2__U671.out","add_all__U676.in1"], - ["add_all__U677.in0","add_all__U676.out"], - ["mul_d3__U673.out","add_all__U677.in1"], - ["add_all__U678.in0","add_all__U677.out"], - ["const_term_U674.out","add_all__U678.in1"], - ["self.out","add_all__U678.out"], - ["mul_d0__U667.in0","coeff_0_U666.out"], - ["mul_d1__U669.in0","coeff_1_U668.out"], - ["mul_d2__U671.in0","coeff_2_U670.out"], - ["mul_d3__U673.in0","coeff_3_U672.out"], - ["self.d.0","mul_d0__U667.in1"], - ["self.d.1","mul_d1__U669.in1"], - ["self.d.2","mul_d2__U671.in1"], - ["self.d.3","mul_d3__U673.in1"] + ["mul_d0__U584.out","add_all__U592.in0"], + ["mul_d1__U586.out","add_all__U592.in1"], + ["add_all__U593.in0","add_all__U592.out"], + ["mul_d2__U588.out","add_all__U593.in1"], + ["add_all__U594.in0","add_all__U593.out"], + ["mul_d3__U590.out","add_all__U594.in1"], + ["add_all__U595.in0","add_all__U594.out"], + ["const_term_U591.out","add_all__U595.in1"], + ["self.out","add_all__U595.out"], + ["mul_d0__U584.in0","coeff_0_U583.out"], + ["mul_d1__U586.in0","coeff_1_U585.out"], + ["mul_d2__U588.in0","coeff_2_U587.out"], + ["mul_d3__U590.in0","coeff_3_U589.out"], + ["self.d.0","mul_d0__U584.in1"], + ["self.d.1","mul_d1__U586.in1"], + ["self.d.2","mul_d2__U588.in1"], + ["self.d.3","mul_d3__U590.in1"] ] }, - "aff__U682":{ + "aff__U599":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U692":{ + "add_all__U609":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U693":{ + "add_all__U610":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U694":{ + "add_all__U611":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U695":{ + "add_all__U612":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U683":{ + "coeff_0_U600":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U685":{ + "coeff_1_U602":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000700"]} }, - "coeff_2_U687":{ + "coeff_2_U604":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U689":{ + "coeff_3_U606":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U691":{ + "const_term_U608":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} }, - "mul_d0__U684":{ + "mul_d0__U601":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U603":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U605":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U607":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U601.out","add_all__U609.in0"], + ["mul_d1__U603.out","add_all__U609.in1"], + ["add_all__U610.in0","add_all__U609.out"], + ["mul_d2__U605.out","add_all__U610.in1"], + ["add_all__U611.in0","add_all__U610.out"], + ["mul_d3__U607.out","add_all__U611.in1"], + ["add_all__U612.in0","add_all__U611.out"], + ["const_term_U608.out","add_all__U612.in1"], + ["self.out","add_all__U612.out"], + ["mul_d0__U601.in0","coeff_0_U600.out"], + ["mul_d1__U603.in0","coeff_1_U602.out"], + ["mul_d2__U605.in0","coeff_2_U604.out"], + ["mul_d3__U607.in0","coeff_3_U606.out"], + ["self.d.0","mul_d0__U601.in1"], + ["self.d.1","mul_d1__U603.in1"], + ["self.d.2","mul_d2__U605.in1"], + ["self.d.3","mul_d3__U607.in1"] + ] + }, + "aff__U9":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U19":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U20":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U21":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U22":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h000003a0"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U686":{ + "mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U688":{ + "mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U690":{ + "mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U684.out","add_all__U692.in0"], - ["mul_d1__U686.out","add_all__U692.in1"], - ["add_all__U693.in0","add_all__U692.out"], - ["mul_d2__U688.out","add_all__U693.in1"], - ["add_all__U694.in0","add_all__U693.out"], - ["mul_d3__U690.out","add_all__U694.in1"], - ["add_all__U695.in0","add_all__U694.out"], - ["const_term_U691.out","add_all__U695.in1"], - ["self.out","add_all__U695.out"], - ["mul_d0__U684.in0","coeff_0_U683.out"], - ["mul_d1__U686.in0","coeff_1_U685.out"], - ["mul_d2__U688.in0","coeff_2_U687.out"], - ["mul_d3__U690.in0","coeff_3_U689.out"], - ["self.d.0","mul_d0__U684.in1"], - ["self.d.1","mul_d1__U686.in1"], - ["self.d.2","mul_d2__U688.in1"], - ["self.d.3","mul_d3__U690.in1"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U17":{ + "affine_controller__U197":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",5,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U32":{ + "_U215":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2151":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U321":{ + "_U2152":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U322":{ + "_U2153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U2154":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U33":{ + "_U216":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U28":{ + "affine_func$add_all__U210":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U29":{ + "affine_func$add_all__U211":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U30":{ + "affine_func$add_all__U212":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U31":{ + "affine_func$add_all__U213":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U19":{ + "affine_func$add_all__U214":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U21":{ + "affine_func$coeff_1_U201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000003a0"]} + "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + }, + "affine_func$coeff_2_U203":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "affine_func$coeff_2_U23":{ + "affine_func$coeff_3_U205":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U25":{ + "affine_func$coeff_4_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U27":{ + "affine_func$const_term_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U20":{ + "affine_func$mul_d0__U200":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U202":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U22":{ + "affine_func$mul_d2__U204":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U24":{ + "affine_func$mul_d3__U206":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U26":{ + "affine_func$mul_d4__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2384,40 +2402,50 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U34$c0_lutcnst":{ + "d_0_am__U217$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U34$lut$lut":{ + "d_0_am__U217$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U35$c0_lutcnst":{ + "d_0_am__U218$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U35$lut$lut":{ + "d_0_am__U218$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U36$c0_lutcnst":{ + "d_0_am__U219$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U36$lut$lut":{ + "d_0_am__U219$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, + "d_0_am__U220$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U220$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} @@ -2458,22 +2486,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U37$c0_lutcnst":{ + "d_1_am__U221$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U221$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U222$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U37$lut$lut":{ + "d_1_am__U222$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U38$c0_lutcnst":{ + "d_1_am__U223$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U38$lut$lut":{ + "d_1_am__U223$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2489,7 +2527,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2522,12 +2560,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U39$c0_lutcnst":{ + "d_2_am__U224$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U224$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U225$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U39$lut$lut":{ + "d_2_am__U225$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2543,7 +2591,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2576,6 +2624,16 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U226$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U226$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -2587,7 +2645,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -2620,6 +2678,50 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -2649,6 +2751,11 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2656,33 +2763,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U321.out"], - ["d_2_inc.in1","_U322.out"], - ["d_3_inc.in1","_U323.out"], - ["cmp_time.in1","_U33.out"], - ["affine_func$mul_d0__U20.out","affine_func$add_all__U28.in0"], - ["affine_func$mul_d1__U22.out","affine_func$add_all__U28.in1"], - ["affine_func$add_all__U29.in0","affine_func$add_all__U28.out"], - ["affine_func$mul_d2__U24.out","affine_func$add_all__U29.in1"], - ["affine_func$add_all__U30.in0","affine_func$add_all__U29.out"], - ["affine_func$mul_d3__U26.out","affine_func$add_all__U30.in1"], - ["affine_func$add_all__U31.in0","affine_func$add_all__U30.out"], - ["affine_func$const_term_U27.out","affine_func$add_all__U31.in1"], - ["time_diff.in0","affine_func$add_all__U31.out"], - ["affine_func$mul_d0__U20.in0","affine_func$coeff_0_U19.out"], - ["affine_func$mul_d1__U22.in0","affine_func$coeff_1_U21.out"], - ["affine_func$mul_d2__U24.in0","affine_func$coeff_2_U23.out"], - ["affine_func$mul_d3__U26.in0","affine_func$coeff_3_U25.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U20.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U22.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U24.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U26.in1"], + ["d_0_inc.in1","_U215.out"], + ["d_1_inc.in1","_U2151.out"], + ["d_2_inc.in1","_U2152.out"], + ["d_3_inc.in1","_U2153.out"], + ["d_4_inc.in1","_U2154.out"], + ["cmp_time.in1","_U216.out"], + ["affine_func$mul_d0__U200.out","affine_func$add_all__U210.in0"], + ["affine_func$mul_d1__U202.out","affine_func$add_all__U210.in1"], + ["affine_func$add_all__U211.in0","affine_func$add_all__U210.out"], + ["affine_func$mul_d2__U204.out","affine_func$add_all__U211.in1"], + ["affine_func$add_all__U212.in0","affine_func$add_all__U211.out"], + ["affine_func$mul_d3__U206.out","affine_func$add_all__U212.in1"], + ["affine_func$add_all__U213.in0","affine_func$add_all__U212.out"], + ["affine_func$mul_d4__U208.out","affine_func$add_all__U213.in1"], + ["affine_func$add_all__U214.in0","affine_func$add_all__U213.out"], + ["affine_func$const_term_U209.out","affine_func$add_all__U214.in1"], + ["time_diff.in0","affine_func$add_all__U214.out"], + ["affine_func$mul_d0__U200.in0","affine_func$coeff_0_U199.out"], + ["affine_func$mul_d1__U202.in0","affine_func$coeff_1_U201.out"], + ["affine_func$mul_d2__U204.in0","affine_func$coeff_2_U203.out"], + ["affine_func$mul_d3__U206.in0","affine_func$coeff_3_U205.out"], + ["affine_func$mul_d4__U208.in0","affine_func$coeff_4_U207.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U200.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U202.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U204.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U206.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U208.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -2690,28 +2803,31 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U34$lut$lut.bit.in.2","d_0_am__U34$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U34$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U34$lut$lut.bit.in.1"], - ["d_0_am__U35$lut$lut.bit.in.0","d_0_am__U34$lut$lut.bit.out"], - ["d_0_am__U35$lut$lut.bit.in.2","d_0_am__U35$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U35$lut$lut.bit.in.1"], - ["d_0_am__U36$lut$lut.bit.in.0","d_0_am__U35$lut$lut.bit.out"], - ["d_0_am__U36$lut$lut.bit.in.2","d_0_am__U36$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U36$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U36$lut$lut.bit.out"], + ["d_0_am__U217$lut$lut.bit.in.2","d_0_am__U217$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U217$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U217$lut$lut.bit.in.1"], + ["d_0_am__U218$lut$lut.bit.in.0","d_0_am__U217$lut$lut.bit.out"], + ["d_0_am__U218$lut$lut.bit.in.2","d_0_am__U218$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U218$lut$lut.bit.in.1"], + ["d_0_am__U219$lut$lut.bit.in.0","d_0_am__U218$lut$lut.bit.out"], + ["d_0_am__U219$lut$lut.bit.in.2","d_0_am__U219$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U219$lut$lut.bit.in.1"], + ["d_0_am__U220$lut$lut.bit.in.0","d_0_am__U219$lut$lut.bit.out"], + ["d_0_am__U220$lut$lut.bit.in.2","d_0_am__U220$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U220$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U220$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2728,13 +2844,16 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U37$lut$lut.bit.in.2","d_1_am__U37$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U37$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U37$lut$lut.bit.in.1"], - ["d_1_am__U38$lut$lut.bit.in.0","d_1_am__U37$lut$lut.bit.out"], - ["d_1_am__U38$lut$lut.bit.in.2","d_1_am__U38$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U38$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U38$lut$lut.bit.out"], + ["d_1_am__U221$lut$lut.bit.in.2","d_1_am__U221$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U221$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U221$lut$lut.bit.in.1"], + ["d_1_am__U222$lut$lut.bit.in.0","d_1_am__U221$lut$lut.bit.out"], + ["d_1_am__U222$lut$lut.bit.in.2","d_1_am__U222$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U222$lut$lut.bit.in.1"], + ["d_1_am__U223$lut$lut.bit.in.0","d_1_am__U222$lut$lut.bit.out"], + ["d_1_am__U223$lut$lut.bit.in.2","d_1_am__U223$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U223$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U223$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2751,10 +2870,13 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U39$lut$lut.bit.in.2","d_2_am__U39$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U39$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U39$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U39$lut$lut.bit.out"], + ["d_2_am__U224$lut$lut.bit.in.2","d_2_am__U224$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U224$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U224$lut$lut.bit.in.1"], + ["d_2_am__U225$lut$lut.bit.in.0","d_2_am__U224$lut$lut.bit.out"], + ["d_2_am__U225$lut$lut.bit.in.2","d_2_am__U225$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U225$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U225$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2771,6 +2893,10 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U226$lut$lut.bit.in.2","d_3_am__U226$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U226$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U226$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U226$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2780,121 +2906,227 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["true_lutcnst.bit.out","d_4_next_value.sel"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"] ] }, - "affine_controller__U271":{ + "affine_controller__U246":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], + ["d",["Array",10,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U289":{ + "_U279":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2791":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2792":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2793":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2794":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2795":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2891":{ + "_U2796":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2892":{ + "_U2797":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2893":{ + "_U2798":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2894":{ + "_U2799":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U290":{ + "_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U284":{ + "affine_func$add_all__U269":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U270":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U285":{ + "affine_func$add_all__U272":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U286":{ + "affine_func$add_all__U273":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U287":{ + "affine_func$add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U288":{ + "affine_func$add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U273":{ + "affine_func$add_all__U276":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U277":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U278":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U275":{ + "affine_func$coeff_1_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "affine_func$coeff_2_U277":{ + "affine_func$coeff_2_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "affine_func$coeff_3_U279":{ + "affine_func$coeff_3_U254":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00003f00"]} + }, + "affine_func$coeff_4_U256":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00001f80"]} + }, + "affine_func$coeff_5_U258":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000300"]} + }, + "affine_func$coeff_6_U260":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "affine_func$coeff_7_U262":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_8_U264":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_4_U281":{ + "affine_func$coeff_9_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U283":{ + "affine_func$const_term_U268":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} + }, + "affine_func$mul_d0__U249":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U251":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U253":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U255":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d4__U257":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U274":{ + "affine_func$mul_d5__U259":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U276":{ + "affine_func$mul_d6__U261":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U278":{ + "affine_func$mul_d7__U263":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U280":{ + "affine_func$mul_d8__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U282":{ + "affine_func$mul_d9__U267":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2958,42 +3190,92 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U291$c0_lutcnst":{ + "d_0_am__U281$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U281$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U282$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U282$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U283$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U283$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U284$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U284$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U285$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U285$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U286$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U291$lut$lut":{ + "d_0_am__U286$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U292$c0_lutcnst":{ + "d_0_am__U287$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U292$lut$lut":{ + "d_0_am__U287$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U293$c0_lutcnst":{ + "d_0_am__U288$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U293$lut$lut":{ + "d_0_am__U288$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U294$c0_lutcnst":{ + "d_0_am__U289$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U294$lut$lut":{ + "d_0_am__U289$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3042,48 +3324,98 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U295$c0_lutcnst":{ + "d_1_am__U290$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U295$lut$lut":{ + "d_1_am__U290$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U296$c0_lutcnst":{ + "d_1_am__U291$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U296$lut$lut":{ + "d_1_am__U291$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U297$c0_lutcnst":{ + "d_1_am__U292$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U297$lut$lut":{ + "d_1_am__U292$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_1_am__U293$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_1_am__U293$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_max":{ - "genref":"coreir.const", + "d_1_am__U294$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U294$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U295$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U295$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U296$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U296$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U297$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U297$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -3136,6 +3468,56 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, + "d_2_am__U300$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U300$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U301$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U301$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U302$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U302$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U303$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U303$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U304$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U304$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -3147,7 +3529,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -3180,12 +3562,62 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U300$c0_lutcnst":{ + "d_3_am__U305$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U305$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U306$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U306$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U307$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U307$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U308$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U308$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U309$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U309$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U310$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U300$lut$lut":{ + "d_3_am__U310$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3201,7 +3633,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_3_min":{ "genref":"coreir.const", @@ -3234,6 +3666,56 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_am__U311$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U311$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U312$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U312$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U313$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U313$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U314$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U314$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U315$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U315$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -3245,7 +3727,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_4_min":{ "genref":"coreir.const", @@ -3278,1080 +3760,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} + "d_5_am__U316$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true1_lutcnst":{ + "d_5_am__U316$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true2_lutcnst":{ + "d_5_am__U317$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true3_lutcnst":{ + "d_5_am__U317$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true4_lutcnst":{ + "d_5_am__U318$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true5_lutcnst":{ + "d_5_am__U318$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true6_lutcnst":{ + "d_5_am__U319$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U289.out"], - ["d_1_inc.in1","_U2891.out"], - ["d_2_inc.in1","_U2892.out"], - ["d_3_inc.in1","_U2893.out"], - ["d_4_inc.in1","_U2894.out"], - ["cmp_time.in1","_U290.out"], - ["affine_func$mul_d0__U274.out","affine_func$add_all__U284.in0"], - ["affine_func$mul_d1__U276.out","affine_func$add_all__U284.in1"], - ["affine_func$add_all__U285.in0","affine_func$add_all__U284.out"], - ["affine_func$mul_d2__U278.out","affine_func$add_all__U285.in1"], - ["affine_func$add_all__U286.in0","affine_func$add_all__U285.out"], - ["affine_func$mul_d3__U280.out","affine_func$add_all__U286.in1"], - ["affine_func$add_all__U287.in0","affine_func$add_all__U286.out"], - ["affine_func$mul_d4__U282.out","affine_func$add_all__U287.in1"], - ["affine_func$add_all__U288.in0","affine_func$add_all__U287.out"], - ["affine_func$const_term_U283.out","affine_func$add_all__U288.in1"], - ["time_diff.in0","affine_func$add_all__U288.out"], - ["affine_func$mul_d0__U274.in0","affine_func$coeff_0_U273.out"], - ["affine_func$mul_d1__U276.in0","affine_func$coeff_1_U275.out"], - ["affine_func$mul_d2__U278.in0","affine_func$coeff_2_U277.out"], - ["affine_func$mul_d3__U280.in0","affine_func$coeff_3_U279.out"], - ["affine_func$mul_d4__U282.in0","affine_func$coeff_4_U281.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U274.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U276.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U278.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U280.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U282.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U291$lut$lut.bit.in.2","d_0_am__U291$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U291$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U291$lut$lut.bit.in.1"], - ["d_0_am__U292$lut$lut.bit.in.0","d_0_am__U291$lut$lut.bit.out"], - ["d_0_am__U292$lut$lut.bit.in.2","d_0_am__U292$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U292$lut$lut.bit.in.1"], - ["d_0_am__U293$lut$lut.bit.in.0","d_0_am__U292$lut$lut.bit.out"], - ["d_0_am__U293$lut$lut.bit.in.2","d_0_am__U293$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U293$lut$lut.bit.in.1"], - ["d_0_am__U294$lut$lut.bit.in.0","d_0_am__U293$lut$lut.bit.out"], - ["d_0_am__U294$lut$lut.bit.in.2","d_0_am__U294$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U294$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U294$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U295$lut$lut.bit.in.2","d_1_am__U295$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U295$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U295$lut$lut.bit.in.1"], - ["d_1_am__U296$lut$lut.bit.in.0","d_1_am__U295$lut$lut.bit.out"], - ["d_1_am__U296$lut$lut.bit.in.2","d_1_am__U296$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U296$lut$lut.bit.in.1"], - ["d_1_am__U297$lut$lut.bit.in.0","d_1_am__U296$lut$lut.bit.out"], - ["d_1_am__U297$lut$lut.bit.in.2","d_1_am__U297$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U297$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U297$lut$lut.bit.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U298$lut$lut.bit.in.2","d_2_am__U298$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U298$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U298$lut$lut.bit.in.1"], - ["d_2_am__U299$lut$lut.bit.in.0","d_2_am__U298$lut$lut.bit.out"], - ["d_2_am__U299$lut$lut.bit.in.2","d_2_am__U299$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U299$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U299$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U300$lut$lut.bit.in.2","d_3_am__U300$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U300$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U300$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U300$lut$lut.bit.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["true_lutcnst.bit.out","d_4_next_value.sel"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"] - ] - }, - "affine_controller__U320":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",10,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U353":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3531":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3532":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3533":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3534":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3535":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3536":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3537":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3538":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3539":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U354":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$add_all__U343":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U344":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U345":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U346":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U347":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U348":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U349":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U350":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U351":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U352":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U322":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$coeff_1_U324":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} - }, - "affine_func$coeff_2_U326":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00007e00"]} - }, - "affine_func$coeff_3_U328":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003f00"]} - }, - "affine_func$coeff_4_U330":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001f80"]} - }, - "affine_func$coeff_5_U332":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000300"]} - }, - "affine_func$coeff_6_U334":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} - }, - "affine_func$coeff_7_U336":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} - }, - "affine_func$coeff_8_U338":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "affine_func$coeff_9_U340":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "affine_func$const_term_U342":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} - }, - "affine_func$mul_d0__U323":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U325":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d2__U327":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d3__U329":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d4__U331":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d5__U333":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d6__U335":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d7__U337":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d8__U339":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d9__U341":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "cycle_time$and$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$and$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "cycle_time$count$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$count$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} - }, - "cycle_time$ult":{ - "genref":"coreir.ult", - "genargs":{"width":["Int",32]} - }, - "d_0_am__U355$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U355$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U356$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U356$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U357$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U357$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U358$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U358$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U359$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U359$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U360$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U360$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U361$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U361$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U362$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U362$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U363$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U363$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U364$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U364$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U365$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U365$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U366$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U366$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U367$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U367$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U368$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U368$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U369$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U369$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U370$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U370$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U371$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U371$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U372$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U372$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U373$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U373$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U374$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U374$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U375$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U375$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U376$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U376$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U377$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U377$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U378$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U378$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U379$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U379$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U380$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U380$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U381$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U381$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U382$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U382$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U383$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U383$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U384$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U384$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_am__U385$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U385$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U386$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U386$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U387$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U387$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U388$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U388$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U389$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U389$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_5_am__U390$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U390$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U391$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U391$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U392$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U392$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U393$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U393$lut$lut":{ + "d_5_am__U319$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4400,32 +3844,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U394$c0_lutcnst":{ + "d_6_am__U320$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U394$lut$lut":{ + "d_6_am__U320$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_6_am__U395$c0_lutcnst":{ + "d_6_am__U321$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U395$lut$lut":{ + "d_6_am__U321$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_6_am__U396$c0_lutcnst":{ + "d_6_am__U322$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U396$lut$lut":{ + "d_6_am__U322$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4474,22 +3918,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_7_am__U397$c0_lutcnst":{ + "d_7_am__U323$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_7_am__U397$lut$lut":{ + "d_7_am__U323$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_7_am__U398$c0_lutcnst":{ + "d_7_am__U324$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_7_am__U398$lut$lut":{ + "d_7_am__U324$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4538,12 +3982,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_8_am__U399$c0_lutcnst":{ + "d_8_am__U325$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_8_am__U399$lut$lut":{ + "d_8_am__U325$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4702,58 +4146,58 @@ } }, "connections":[ - ["d_0_inc.in1","_U353.out"], - ["d_1_inc.in1","_U3531.out"], - ["d_2_inc.in1","_U3532.out"], - ["d_3_inc.in1","_U3533.out"], - ["d_4_inc.in1","_U3534.out"], - ["d_5_inc.in1","_U3535.out"], - ["d_6_inc.in1","_U3536.out"], - ["d_7_inc.in1","_U3537.out"], - ["d_8_inc.in1","_U3538.out"], - ["d_9_inc.in1","_U3539.out"], - ["cmp_time.in1","_U354.out"], - ["affine_func$mul_d0__U323.out","affine_func$add_all__U343.in0"], - ["affine_func$mul_d1__U325.out","affine_func$add_all__U343.in1"], - ["affine_func$add_all__U344.in0","affine_func$add_all__U343.out"], - ["affine_func$mul_d2__U327.out","affine_func$add_all__U344.in1"], - ["affine_func$add_all__U345.in0","affine_func$add_all__U344.out"], - ["affine_func$mul_d3__U329.out","affine_func$add_all__U345.in1"], - ["affine_func$add_all__U346.in0","affine_func$add_all__U345.out"], - ["affine_func$mul_d4__U331.out","affine_func$add_all__U346.in1"], - ["affine_func$add_all__U347.in0","affine_func$add_all__U346.out"], - ["affine_func$mul_d5__U333.out","affine_func$add_all__U347.in1"], - ["affine_func$add_all__U348.in0","affine_func$add_all__U347.out"], - ["affine_func$mul_d6__U335.out","affine_func$add_all__U348.in1"], - ["affine_func$add_all__U349.in0","affine_func$add_all__U348.out"], - ["affine_func$mul_d7__U337.out","affine_func$add_all__U349.in1"], - ["affine_func$add_all__U350.in0","affine_func$add_all__U349.out"], - ["affine_func$mul_d8__U339.out","affine_func$add_all__U350.in1"], - ["affine_func$add_all__U351.in0","affine_func$add_all__U350.out"], - ["affine_func$mul_d9__U341.out","affine_func$add_all__U351.in1"], - ["affine_func$add_all__U352.in0","affine_func$add_all__U351.out"], - ["affine_func$const_term_U342.out","affine_func$add_all__U352.in1"], - ["time_diff.in0","affine_func$add_all__U352.out"], - ["affine_func$mul_d0__U323.in0","affine_func$coeff_0_U322.out"], - ["affine_func$mul_d1__U325.in0","affine_func$coeff_1_U324.out"], - ["affine_func$mul_d2__U327.in0","affine_func$coeff_2_U326.out"], - ["affine_func$mul_d3__U329.in0","affine_func$coeff_3_U328.out"], - ["affine_func$mul_d4__U331.in0","affine_func$coeff_4_U330.out"], - ["affine_func$mul_d5__U333.in0","affine_func$coeff_5_U332.out"], - ["affine_func$mul_d6__U335.in0","affine_func$coeff_6_U334.out"], - ["affine_func$mul_d7__U337.in0","affine_func$coeff_7_U336.out"], - ["affine_func$mul_d8__U339.in0","affine_func$coeff_8_U338.out"], - ["affine_func$mul_d9__U341.in0","affine_func$coeff_9_U340.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U323.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U325.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U327.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U329.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U331.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U333.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U335.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U337.in1"], - ["d_8_reg$reg0.out","affine_func$mul_d8__U339.in1"], - ["d_9_reg$reg0.out","affine_func$mul_d9__U341.in1"], + ["d_0_inc.in1","_U279.out"], + ["d_1_inc.in1","_U2791.out"], + ["d_2_inc.in1","_U2792.out"], + ["d_3_inc.in1","_U2793.out"], + ["d_4_inc.in1","_U2794.out"], + ["d_5_inc.in1","_U2795.out"], + ["d_6_inc.in1","_U2796.out"], + ["d_7_inc.in1","_U2797.out"], + ["d_8_inc.in1","_U2798.out"], + ["d_9_inc.in1","_U2799.out"], + ["cmp_time.in1","_U280.out"], + ["affine_func$mul_d0__U249.out","affine_func$add_all__U269.in0"], + ["affine_func$mul_d1__U251.out","affine_func$add_all__U269.in1"], + ["affine_func$add_all__U270.in0","affine_func$add_all__U269.out"], + ["affine_func$mul_d2__U253.out","affine_func$add_all__U270.in1"], + ["affine_func$add_all__U271.in0","affine_func$add_all__U270.out"], + ["affine_func$mul_d3__U255.out","affine_func$add_all__U271.in1"], + ["affine_func$add_all__U272.in0","affine_func$add_all__U271.out"], + ["affine_func$mul_d4__U257.out","affine_func$add_all__U272.in1"], + ["affine_func$add_all__U273.in0","affine_func$add_all__U272.out"], + ["affine_func$mul_d5__U259.out","affine_func$add_all__U273.in1"], + ["affine_func$add_all__U274.in0","affine_func$add_all__U273.out"], + ["affine_func$mul_d6__U261.out","affine_func$add_all__U274.in1"], + ["affine_func$add_all__U275.in0","affine_func$add_all__U274.out"], + ["affine_func$mul_d7__U263.out","affine_func$add_all__U275.in1"], + ["affine_func$add_all__U276.in0","affine_func$add_all__U275.out"], + ["affine_func$mul_d8__U265.out","affine_func$add_all__U276.in1"], + ["affine_func$add_all__U277.in0","affine_func$add_all__U276.out"], + ["affine_func$mul_d9__U267.out","affine_func$add_all__U277.in1"], + ["affine_func$add_all__U278.in0","affine_func$add_all__U277.out"], + ["affine_func$const_term_U268.out","affine_func$add_all__U278.in1"], + ["time_diff.in0","affine_func$add_all__U278.out"], + ["affine_func$mul_d0__U249.in0","affine_func$coeff_0_U248.out"], + ["affine_func$mul_d1__U251.in0","affine_func$coeff_1_U250.out"], + ["affine_func$mul_d2__U253.in0","affine_func$coeff_2_U252.out"], + ["affine_func$mul_d3__U255.in0","affine_func$coeff_3_U254.out"], + ["affine_func$mul_d4__U257.in0","affine_func$coeff_4_U256.out"], + ["affine_func$mul_d5__U259.in0","affine_func$coeff_5_U258.out"], + ["affine_func$mul_d6__U261.in0","affine_func$coeff_6_U260.out"], + ["affine_func$mul_d7__U263.in0","affine_func$coeff_7_U262.out"], + ["affine_func$mul_d8__U265.in0","affine_func$coeff_8_U264.out"], + ["affine_func$mul_d9__U267.in0","affine_func$coeff_9_U266.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U249.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U251.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U253.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U255.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U257.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U259.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U261.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U263.in1"], + ["d_8_reg$reg0.out","affine_func$mul_d8__U265.in1"], + ["d_9_reg$reg0.out","affine_func$mul_d9__U267.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -4784,34 +4228,34 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U355$lut$lut.bit.in.2","d_0_am__U355$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U355$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U355$lut$lut.bit.in.1"], - ["d_0_am__U356$lut$lut.bit.in.0","d_0_am__U355$lut$lut.bit.out"], - ["d_0_am__U356$lut$lut.bit.in.2","d_0_am__U356$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U356$lut$lut.bit.in.1"], - ["d_0_am__U357$lut$lut.bit.in.0","d_0_am__U356$lut$lut.bit.out"], - ["d_0_am__U357$lut$lut.bit.in.2","d_0_am__U357$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U357$lut$lut.bit.in.1"], - ["d_0_am__U358$lut$lut.bit.in.0","d_0_am__U357$lut$lut.bit.out"], - ["d_0_am__U358$lut$lut.bit.in.2","d_0_am__U358$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U358$lut$lut.bit.in.1"], - ["d_0_am__U359$lut$lut.bit.in.0","d_0_am__U358$lut$lut.bit.out"], - ["d_0_am__U359$lut$lut.bit.in.2","d_0_am__U359$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U359$lut$lut.bit.in.1"], - ["d_0_am__U360$lut$lut.bit.in.0","d_0_am__U359$lut$lut.bit.out"], - ["d_0_am__U360$lut$lut.bit.in.2","d_0_am__U360$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U360$lut$lut.bit.in.1"], - ["d_0_am__U361$lut$lut.bit.in.0","d_0_am__U360$lut$lut.bit.out"], - ["d_0_am__U361$lut$lut.bit.in.2","d_0_am__U361$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U361$lut$lut.bit.in.1"], - ["d_0_am__U362$lut$lut.bit.in.0","d_0_am__U361$lut$lut.bit.out"], - ["d_0_am__U362$lut$lut.bit.in.2","d_0_am__U362$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_0_am__U362$lut$lut.bit.in.1"], - ["d_0_am__U363$lut$lut.bit.in.0","d_0_am__U362$lut$lut.bit.out"], - ["d_0_am__U363$lut$lut.bit.in.2","d_0_am__U363$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_0_am__U363$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U363$lut$lut.bit.out"], + ["d_0_am__U281$lut$lut.bit.in.2","d_0_am__U281$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U281$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U281$lut$lut.bit.in.1"], + ["d_0_am__U282$lut$lut.bit.in.0","d_0_am__U281$lut$lut.bit.out"], + ["d_0_am__U282$lut$lut.bit.in.2","d_0_am__U282$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U282$lut$lut.bit.in.1"], + ["d_0_am__U283$lut$lut.bit.in.0","d_0_am__U282$lut$lut.bit.out"], + ["d_0_am__U283$lut$lut.bit.in.2","d_0_am__U283$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U283$lut$lut.bit.in.1"], + ["d_0_am__U284$lut$lut.bit.in.0","d_0_am__U283$lut$lut.bit.out"], + ["d_0_am__U284$lut$lut.bit.in.2","d_0_am__U284$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U284$lut$lut.bit.in.1"], + ["d_0_am__U285$lut$lut.bit.in.0","d_0_am__U284$lut$lut.bit.out"], + ["d_0_am__U285$lut$lut.bit.in.2","d_0_am__U285$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U285$lut$lut.bit.in.1"], + ["d_0_am__U286$lut$lut.bit.in.0","d_0_am__U285$lut$lut.bit.out"], + ["d_0_am__U286$lut$lut.bit.in.2","d_0_am__U286$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U286$lut$lut.bit.in.1"], + ["d_0_am__U287$lut$lut.bit.in.0","d_0_am__U286$lut$lut.bit.out"], + ["d_0_am__U287$lut$lut.bit.in.2","d_0_am__U287$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U287$lut$lut.bit.in.1"], + ["d_0_am__U288$lut$lut.bit.in.0","d_0_am__U287$lut$lut.bit.out"], + ["d_0_am__U288$lut$lut.bit.in.2","d_0_am__U288$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_0_am__U288$lut$lut.bit.in.1"], + ["d_0_am__U289$lut$lut.bit.in.0","d_0_am__U288$lut$lut.bit.out"], + ["d_0_am__U289$lut$lut.bit.in.2","d_0_am__U289$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_0_am__U289$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U289$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4828,31 +4272,31 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U364$lut$lut.bit.in.2","d_1_am__U364$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U364$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U364$lut$lut.bit.in.1"], - ["d_1_am__U365$lut$lut.bit.in.0","d_1_am__U364$lut$lut.bit.out"], - ["d_1_am__U365$lut$lut.bit.in.2","d_1_am__U365$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U365$lut$lut.bit.in.1"], - ["d_1_am__U366$lut$lut.bit.in.0","d_1_am__U365$lut$lut.bit.out"], - ["d_1_am__U366$lut$lut.bit.in.2","d_1_am__U366$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U366$lut$lut.bit.in.1"], - ["d_1_am__U367$lut$lut.bit.in.0","d_1_am__U366$lut$lut.bit.out"], - ["d_1_am__U367$lut$lut.bit.in.2","d_1_am__U367$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U367$lut$lut.bit.in.1"], - ["d_1_am__U368$lut$lut.bit.in.0","d_1_am__U367$lut$lut.bit.out"], - ["d_1_am__U368$lut$lut.bit.in.2","d_1_am__U368$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U368$lut$lut.bit.in.1"], - ["d_1_am__U369$lut$lut.bit.in.0","d_1_am__U368$lut$lut.bit.out"], - ["d_1_am__U369$lut$lut.bit.in.2","d_1_am__U369$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U369$lut$lut.bit.in.1"], - ["d_1_am__U370$lut$lut.bit.in.0","d_1_am__U369$lut$lut.bit.out"], - ["d_1_am__U370$lut$lut.bit.in.2","d_1_am__U370$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_1_am__U370$lut$lut.bit.in.1"], - ["d_1_am__U371$lut$lut.bit.in.0","d_1_am__U370$lut$lut.bit.out"], - ["d_1_am__U371$lut$lut.bit.in.2","d_1_am__U371$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_1_am__U371$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U371$lut$lut.bit.out"], + ["d_1_am__U290$lut$lut.bit.in.2","d_1_am__U290$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U290$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U290$lut$lut.bit.in.1"], + ["d_1_am__U291$lut$lut.bit.in.0","d_1_am__U290$lut$lut.bit.out"], + ["d_1_am__U291$lut$lut.bit.in.2","d_1_am__U291$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U291$lut$lut.bit.in.1"], + ["d_1_am__U292$lut$lut.bit.in.0","d_1_am__U291$lut$lut.bit.out"], + ["d_1_am__U292$lut$lut.bit.in.2","d_1_am__U292$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U292$lut$lut.bit.in.1"], + ["d_1_am__U293$lut$lut.bit.in.0","d_1_am__U292$lut$lut.bit.out"], + ["d_1_am__U293$lut$lut.bit.in.2","d_1_am__U293$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U293$lut$lut.bit.in.1"], + ["d_1_am__U294$lut$lut.bit.in.0","d_1_am__U293$lut$lut.bit.out"], + ["d_1_am__U294$lut$lut.bit.in.2","d_1_am__U294$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U294$lut$lut.bit.in.1"], + ["d_1_am__U295$lut$lut.bit.in.0","d_1_am__U294$lut$lut.bit.out"], + ["d_1_am__U295$lut$lut.bit.in.2","d_1_am__U295$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U295$lut$lut.bit.in.1"], + ["d_1_am__U296$lut$lut.bit.in.0","d_1_am__U295$lut$lut.bit.out"], + ["d_1_am__U296$lut$lut.bit.in.2","d_1_am__U296$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_1_am__U296$lut$lut.bit.in.1"], + ["d_1_am__U297$lut$lut.bit.in.0","d_1_am__U296$lut$lut.bit.out"], + ["d_1_am__U297$lut$lut.bit.in.2","d_1_am__U297$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_1_am__U297$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U297$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4869,28 +4313,28 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U372$lut$lut.bit.in.2","d_2_am__U372$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U372$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U372$lut$lut.bit.in.1"], - ["d_2_am__U373$lut$lut.bit.in.0","d_2_am__U372$lut$lut.bit.out"], - ["d_2_am__U373$lut$lut.bit.in.2","d_2_am__U373$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U373$lut$lut.bit.in.1"], - ["d_2_am__U374$lut$lut.bit.in.0","d_2_am__U373$lut$lut.bit.out"], - ["d_2_am__U374$lut$lut.bit.in.2","d_2_am__U374$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U374$lut$lut.bit.in.1"], - ["d_2_am__U375$lut$lut.bit.in.0","d_2_am__U374$lut$lut.bit.out"], - ["d_2_am__U375$lut$lut.bit.in.2","d_2_am__U375$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U375$lut$lut.bit.in.1"], - ["d_2_am__U376$lut$lut.bit.in.0","d_2_am__U375$lut$lut.bit.out"], - ["d_2_am__U376$lut$lut.bit.in.2","d_2_am__U376$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U376$lut$lut.bit.in.1"], - ["d_2_am__U377$lut$lut.bit.in.0","d_2_am__U376$lut$lut.bit.out"], - ["d_2_am__U377$lut$lut.bit.in.2","d_2_am__U377$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_2_am__U377$lut$lut.bit.in.1"], - ["d_2_am__U378$lut$lut.bit.in.0","d_2_am__U377$lut$lut.bit.out"], - ["d_2_am__U378$lut$lut.bit.in.2","d_2_am__U378$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_2_am__U378$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U378$lut$lut.bit.out"], + ["d_2_am__U298$lut$lut.bit.in.2","d_2_am__U298$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U298$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U298$lut$lut.bit.in.1"], + ["d_2_am__U299$lut$lut.bit.in.0","d_2_am__U298$lut$lut.bit.out"], + ["d_2_am__U299$lut$lut.bit.in.2","d_2_am__U299$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U299$lut$lut.bit.in.1"], + ["d_2_am__U300$lut$lut.bit.in.0","d_2_am__U299$lut$lut.bit.out"], + ["d_2_am__U300$lut$lut.bit.in.2","d_2_am__U300$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U300$lut$lut.bit.in.1"], + ["d_2_am__U301$lut$lut.bit.in.0","d_2_am__U300$lut$lut.bit.out"], + ["d_2_am__U301$lut$lut.bit.in.2","d_2_am__U301$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U301$lut$lut.bit.in.1"], + ["d_2_am__U302$lut$lut.bit.in.0","d_2_am__U301$lut$lut.bit.out"], + ["d_2_am__U302$lut$lut.bit.in.2","d_2_am__U302$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U302$lut$lut.bit.in.1"], + ["d_2_am__U303$lut$lut.bit.in.0","d_2_am__U302$lut$lut.bit.out"], + ["d_2_am__U303$lut$lut.bit.in.2","d_2_am__U303$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_2_am__U303$lut$lut.bit.in.1"], + ["d_2_am__U304$lut$lut.bit.in.0","d_2_am__U303$lut$lut.bit.out"], + ["d_2_am__U304$lut$lut.bit.in.2","d_2_am__U304$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_2_am__U304$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U304$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4907,25 +4351,25 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U379$lut$lut.bit.in.2","d_3_am__U379$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U379$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U379$lut$lut.bit.in.1"], - ["d_3_am__U380$lut$lut.bit.in.0","d_3_am__U379$lut$lut.bit.out"], - ["d_3_am__U380$lut$lut.bit.in.2","d_3_am__U380$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U380$lut$lut.bit.in.1"], - ["d_3_am__U381$lut$lut.bit.in.0","d_3_am__U380$lut$lut.bit.out"], - ["d_3_am__U381$lut$lut.bit.in.2","d_3_am__U381$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U381$lut$lut.bit.in.1"], - ["d_3_am__U382$lut$lut.bit.in.0","d_3_am__U381$lut$lut.bit.out"], - ["d_3_am__U382$lut$lut.bit.in.2","d_3_am__U382$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U382$lut$lut.bit.in.1"], - ["d_3_am__U383$lut$lut.bit.in.0","d_3_am__U382$lut$lut.bit.out"], - ["d_3_am__U383$lut$lut.bit.in.2","d_3_am__U383$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_3_am__U383$lut$lut.bit.in.1"], - ["d_3_am__U384$lut$lut.bit.in.0","d_3_am__U383$lut$lut.bit.out"], - ["d_3_am__U384$lut$lut.bit.in.2","d_3_am__U384$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_3_am__U384$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U384$lut$lut.bit.out"], + ["d_3_am__U305$lut$lut.bit.in.2","d_3_am__U305$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U305$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U305$lut$lut.bit.in.1"], + ["d_3_am__U306$lut$lut.bit.in.0","d_3_am__U305$lut$lut.bit.out"], + ["d_3_am__U306$lut$lut.bit.in.2","d_3_am__U306$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U306$lut$lut.bit.in.1"], + ["d_3_am__U307$lut$lut.bit.in.0","d_3_am__U306$lut$lut.bit.out"], + ["d_3_am__U307$lut$lut.bit.in.2","d_3_am__U307$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U307$lut$lut.bit.in.1"], + ["d_3_am__U308$lut$lut.bit.in.0","d_3_am__U307$lut$lut.bit.out"], + ["d_3_am__U308$lut$lut.bit.in.2","d_3_am__U308$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U308$lut$lut.bit.in.1"], + ["d_3_am__U309$lut$lut.bit.in.0","d_3_am__U308$lut$lut.bit.out"], + ["d_3_am__U309$lut$lut.bit.in.2","d_3_am__U309$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_3_am__U309$lut$lut.bit.in.1"], + ["d_3_am__U310$lut$lut.bit.in.0","d_3_am__U309$lut$lut.bit.out"], + ["d_3_am__U310$lut$lut.bit.in.2","d_3_am__U310$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_3_am__U310$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U310$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4942,22 +4386,22 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U385$lut$lut.bit.in.2","d_4_am__U385$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U385$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U385$lut$lut.bit.in.1"], - ["d_4_am__U386$lut$lut.bit.in.0","d_4_am__U385$lut$lut.bit.out"], - ["d_4_am__U386$lut$lut.bit.in.2","d_4_am__U386$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U386$lut$lut.bit.in.1"], - ["d_4_am__U387$lut$lut.bit.in.0","d_4_am__U386$lut$lut.bit.out"], - ["d_4_am__U387$lut$lut.bit.in.2","d_4_am__U387$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U387$lut$lut.bit.in.1"], - ["d_4_am__U388$lut$lut.bit.in.0","d_4_am__U387$lut$lut.bit.out"], - ["d_4_am__U388$lut$lut.bit.in.2","d_4_am__U388$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_4_am__U388$lut$lut.bit.in.1"], - ["d_4_am__U389$lut$lut.bit.in.0","d_4_am__U388$lut$lut.bit.out"], - ["d_4_am__U389$lut$lut.bit.in.2","d_4_am__U389$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_4_am__U389$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U389$lut$lut.bit.out"], + ["d_4_am__U311$lut$lut.bit.in.2","d_4_am__U311$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U311$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U311$lut$lut.bit.in.1"], + ["d_4_am__U312$lut$lut.bit.in.0","d_4_am__U311$lut$lut.bit.out"], + ["d_4_am__U312$lut$lut.bit.in.2","d_4_am__U312$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U312$lut$lut.bit.in.1"], + ["d_4_am__U313$lut$lut.bit.in.0","d_4_am__U312$lut$lut.bit.out"], + ["d_4_am__U313$lut$lut.bit.in.2","d_4_am__U313$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U313$lut$lut.bit.in.1"], + ["d_4_am__U314$lut$lut.bit.in.0","d_4_am__U313$lut$lut.bit.out"], + ["d_4_am__U314$lut$lut.bit.in.2","d_4_am__U314$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_4_am__U314$lut$lut.bit.in.1"], + ["d_4_am__U315$lut$lut.bit.in.0","d_4_am__U314$lut$lut.bit.out"], + ["d_4_am__U315$lut$lut.bit.in.2","d_4_am__U315$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_4_am__U315$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U315$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -4974,19 +4418,19 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U390$lut$lut.bit.in.2","d_5_am__U390$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U390$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U390$lut$lut.bit.in.1"], - ["d_5_am__U391$lut$lut.bit.in.0","d_5_am__U390$lut$lut.bit.out"], - ["d_5_am__U391$lut$lut.bit.in.2","d_5_am__U391$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U391$lut$lut.bit.in.1"], - ["d_5_am__U392$lut$lut.bit.in.0","d_5_am__U391$lut$lut.bit.out"], - ["d_5_am__U392$lut$lut.bit.in.2","d_5_am__U392$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_5_am__U392$lut$lut.bit.in.1"], - ["d_5_am__U393$lut$lut.bit.in.0","d_5_am__U392$lut$lut.bit.out"], - ["d_5_am__U393$lut$lut.bit.in.2","d_5_am__U393$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_5_am__U393$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U393$lut$lut.bit.out"], + ["d_5_am__U316$lut$lut.bit.in.2","d_5_am__U316$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U316$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U316$lut$lut.bit.in.1"], + ["d_5_am__U317$lut$lut.bit.in.0","d_5_am__U316$lut$lut.bit.out"], + ["d_5_am__U317$lut$lut.bit.in.2","d_5_am__U317$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U317$lut$lut.bit.in.1"], + ["d_5_am__U318$lut$lut.bit.in.0","d_5_am__U317$lut$lut.bit.out"], + ["d_5_am__U318$lut$lut.bit.in.2","d_5_am__U318$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_5_am__U318$lut$lut.bit.in.1"], + ["d_5_am__U319$lut$lut.bit.in.0","d_5_am__U318$lut$lut.bit.out"], + ["d_5_am__U319$lut$lut.bit.in.2","d_5_am__U319$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_5_am__U319$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U319$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -5003,16 +4447,16 @@ ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U394$lut$lut.bit.in.2","d_6_am__U394$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U394$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U394$lut$lut.bit.in.1"], - ["d_6_am__U395$lut$lut.bit.in.0","d_6_am__U394$lut$lut.bit.out"], - ["d_6_am__U395$lut$lut.bit.in.2","d_6_am__U395$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_6_am__U395$lut$lut.bit.in.1"], - ["d_6_am__U396$lut$lut.bit.in.0","d_6_am__U395$lut$lut.bit.out"], - ["d_6_am__U396$lut$lut.bit.in.2","d_6_am__U396$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_6_am__U396$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U396$lut$lut.bit.out"], + ["d_6_am__U320$lut$lut.bit.in.2","d_6_am__U320$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U320$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U320$lut$lut.bit.in.1"], + ["d_6_am__U321$lut$lut.bit.in.0","d_6_am__U320$lut$lut.bit.out"], + ["d_6_am__U321$lut$lut.bit.in.2","d_6_am__U321$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_6_am__U321$lut$lut.bit.in.1"], + ["d_6_am__U322$lut$lut.bit.in.0","d_6_am__U321$lut$lut.bit.out"], + ["d_6_am__U322$lut$lut.bit.in.2","d_6_am__U322$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_6_am__U322$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U322$lut$lut.bit.out"], ["d_6_reg$reg0.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -5029,13 +4473,13 @@ ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], ["self.clk","d_6_reg$reg0.clk"], ["self.d.6","d_6_reg$reg0.out"], - ["d_7_am__U397$lut$lut.bit.in.2","d_7_am__U397$c0_lutcnst.bit.out"], - ["true8_lutcnst.bit.out","d_7_am__U397$lut$lut.bit.in.0"], - ["d_8_at_max.out","d_7_am__U397$lut$lut.bit.in.1"], - ["d_7_am__U398$lut$lut.bit.in.0","d_7_am__U397$lut$lut.bit.out"], - ["d_7_am__U398$lut$lut.bit.in.2","d_7_am__U398$c0_lutcnst.bit.out"], - ["d_9_at_max.out","d_7_am__U398$lut$lut.bit.in.1"], - ["d_7_next_value.sel","d_7_am__U398$lut$lut.bit.out"], + ["d_7_am__U323$lut$lut.bit.in.2","d_7_am__U323$c0_lutcnst.bit.out"], + ["true8_lutcnst.bit.out","d_7_am__U323$lut$lut.bit.in.0"], + ["d_8_at_max.out","d_7_am__U323$lut$lut.bit.in.1"], + ["d_7_am__U324$lut$lut.bit.in.0","d_7_am__U323$lut$lut.bit.out"], + ["d_7_am__U324$lut$lut.bit.in.2","d_7_am__U324$c0_lutcnst.bit.out"], + ["d_9_at_max.out","d_7_am__U324$lut$lut.bit.in.1"], + ["d_7_next_value.sel","d_7_am__U324$lut$lut.bit.out"], ["d_7_reg$reg0.out","d_7_at_max.in0"], ["d_7_max.out","d_7_at_max.in1"], ["d_7_next_value_at_max.sel","d_7_at_max.out"], @@ -5052,10 +4496,10 @@ ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], ["self.clk","d_7_reg$reg0.clk"], ["self.d.7","d_7_reg$reg0.out"], - ["d_8_am__U399$lut$lut.bit.in.2","d_8_am__U399$c0_lutcnst.bit.out"], - ["true9_lutcnst.bit.out","d_8_am__U399$lut$lut.bit.in.0"], - ["d_9_at_max.out","d_8_am__U399$lut$lut.bit.in.1"], - ["d_8_next_value.sel","d_8_am__U399$lut$lut.bit.out"], + ["d_8_am__U325$lut$lut.bit.in.2","d_8_am__U325$c0_lutcnst.bit.out"], + ["true9_lutcnst.bit.out","d_8_am__U325$lut$lut.bit.in.0"], + ["d_9_at_max.out","d_8_am__U325$lut$lut.bit.in.1"], + ["d_8_next_value.sel","d_8_am__U325$lut$lut.bit.out"], ["d_8_reg$reg0.out","d_8_at_max.in0"], ["d_8_max.out","d_8_at_max.in1"], ["d_8_next_value_at_max.sel","d_8_at_max.out"], @@ -5091,7 +4535,7 @@ ["self.d.9","d_9_reg$reg0.out"] ] }, - "affine_controller__U436":{ + "affine_controller__U362":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5099,49 +4543,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U445":{ + "_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4451":{ + "_U3711":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U446":{ + "_U372":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U443":{ + "affine_func$add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U444":{ + "affine_func$add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U438":{ + "affine_func$coeff_0_U364":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U440":{ + "affine_func$coeff_1_U366":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U442":{ + "affine_func$const_term_U368":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U439":{ + "affine_func$mul_d0__U365":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U441":{ + "affine_func$mul_d1__U367":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5205,12 +4649,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U447$c0_lutcnst":{ + "d_0_am__U373$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U447$lut$lut":{ + "d_0_am__U373$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5329,18 +4773,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U445.out"], - ["d_1_inc.in1","_U4451.out"], - ["cmp_time.in1","_U446.out"], - ["affine_func$mul_d0__U439.out","affine_func$add_all__U443.in0"], - ["affine_func$mul_d1__U441.out","affine_func$add_all__U443.in1"], - ["affine_func$add_all__U444.in0","affine_func$add_all__U443.out"], - ["affine_func$const_term_U442.out","affine_func$add_all__U444.in1"], - ["time_diff.in0","affine_func$add_all__U444.out"], - ["affine_func$mul_d0__U439.in0","affine_func$coeff_0_U438.out"], - ["affine_func$mul_d1__U441.in0","affine_func$coeff_1_U440.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U439.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U441.in1"], + ["d_0_inc.in1","_U371.out"], + ["d_1_inc.in1","_U3711.out"], + ["cmp_time.in1","_U372.out"], + ["affine_func$mul_d0__U365.out","affine_func$add_all__U369.in0"], + ["affine_func$mul_d1__U367.out","affine_func$add_all__U369.in1"], + ["affine_func$add_all__U370.in0","affine_func$add_all__U369.out"], + ["affine_func$const_term_U368.out","affine_func$add_all__U370.in1"], + ["time_diff.in0","affine_func$add_all__U370.out"], + ["affine_func$mul_d0__U365.in0","affine_func$coeff_0_U364.out"], + ["affine_func$mul_d1__U367.in0","affine_func$coeff_1_U366.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U365.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U367.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5363,10 +4807,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U447$lut$lut.bit.in.2","d_0_am__U447$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U447$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U447$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U447$lut$lut.bit.out"], + ["d_0_am__U373$lut$lut.bit.in.2","d_0_am__U373$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U373$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U373$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U373$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5402,7 +4846,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U451":{ + "affine_controller__U376":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5410,49 +4854,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U460":{ + "_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4601":{ + "_U3851":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U461":{ + "_U386":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U458":{ + "affine_func$add_all__U383":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U459":{ + "affine_func$add_all__U384":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U453":{ + "affine_func$coeff_0_U378":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U455":{ + "affine_func$coeff_1_U380":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U457":{ + "affine_func$const_term_U382":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U454":{ + "affine_func$mul_d0__U379":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U456":{ + "affine_func$mul_d1__U381":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5516,12 +4960,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U462$c0_lutcnst":{ + "d_0_am__U387$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U462$lut$lut":{ + "d_0_am__U387$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5640,18 +5084,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U460.out"], - ["d_1_inc.in1","_U4601.out"], - ["cmp_time.in1","_U461.out"], - ["affine_func$mul_d0__U454.out","affine_func$add_all__U458.in0"], - ["affine_func$mul_d1__U456.out","affine_func$add_all__U458.in1"], - ["affine_func$add_all__U459.in0","affine_func$add_all__U458.out"], - ["affine_func$const_term_U457.out","affine_func$add_all__U459.in1"], - ["time_diff.in0","affine_func$add_all__U459.out"], - ["affine_func$mul_d0__U454.in0","affine_func$coeff_0_U453.out"], - ["affine_func$mul_d1__U456.in0","affine_func$coeff_1_U455.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U454.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U456.in1"], + ["d_0_inc.in1","_U385.out"], + ["d_1_inc.in1","_U3851.out"], + ["cmp_time.in1","_U386.out"], + ["affine_func$mul_d0__U379.out","affine_func$add_all__U383.in0"], + ["affine_func$mul_d1__U381.out","affine_func$add_all__U383.in1"], + ["affine_func$add_all__U384.in0","affine_func$add_all__U383.out"], + ["affine_func$const_term_U382.out","affine_func$add_all__U384.in1"], + ["time_diff.in0","affine_func$add_all__U384.out"], + ["affine_func$mul_d0__U379.in0","affine_func$coeff_0_U378.out"], + ["affine_func$mul_d1__U381.in0","affine_func$coeff_1_U380.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U379.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U381.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5674,10 +5118,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U462$lut$lut.bit.in.2","d_0_am__U462$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U462$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U462$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U462$lut$lut.bit.out"], + ["d_0_am__U387$lut$lut.bit.in.2","d_0_am__U387$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U387$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U387$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U387$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5713,7 +5157,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U466":{ + "affine_controller__U390":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5721,49 +5165,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U475":{ + "_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4751":{ + "_U3991":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U476":{ + "_U400":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U473":{ + "affine_func$add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U474":{ + "affine_func$add_all__U398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U468":{ + "affine_func$coeff_0_U392":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U470":{ + "affine_func$coeff_1_U394":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U472":{ + "affine_func$const_term_U396":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U469":{ + "affine_func$mul_d0__U393":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U471":{ + "affine_func$mul_d1__U395":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5827,12 +5271,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U477$c0_lutcnst":{ + "d_0_am__U401$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U477$lut$lut":{ + "d_0_am__U401$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5951,18 +5395,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U475.out"], - ["d_1_inc.in1","_U4751.out"], - ["cmp_time.in1","_U476.out"], - ["affine_func$mul_d0__U469.out","affine_func$add_all__U473.in0"], - ["affine_func$mul_d1__U471.out","affine_func$add_all__U473.in1"], - ["affine_func$add_all__U474.in0","affine_func$add_all__U473.out"], - ["affine_func$const_term_U472.out","affine_func$add_all__U474.in1"], - ["time_diff.in0","affine_func$add_all__U474.out"], - ["affine_func$mul_d0__U469.in0","affine_func$coeff_0_U468.out"], - ["affine_func$mul_d1__U471.in0","affine_func$coeff_1_U470.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U469.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U471.in1"], + ["d_0_inc.in1","_U399.out"], + ["d_1_inc.in1","_U3991.out"], + ["cmp_time.in1","_U400.out"], + ["affine_func$mul_d0__U393.out","affine_func$add_all__U397.in0"], + ["affine_func$mul_d1__U395.out","affine_func$add_all__U397.in1"], + ["affine_func$add_all__U398.in0","affine_func$add_all__U397.out"], + ["affine_func$const_term_U396.out","affine_func$add_all__U398.in1"], + ["time_diff.in0","affine_func$add_all__U398.out"], + ["affine_func$mul_d0__U393.in0","affine_func$coeff_0_U392.out"], + ["affine_func$mul_d1__U395.in0","affine_func$coeff_1_U394.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U393.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U395.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5985,10 +5429,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U477$lut$lut.bit.in.2","d_0_am__U477$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U477$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U477$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U477$lut$lut.bit.out"], + ["d_0_am__U401$lut$lut.bit.in.2","d_0_am__U401$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U401$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U401$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U401$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6024,7 +5468,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U481":{ + "affine_controller__U404":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6032,49 +5476,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U490":{ + "_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4901":{ + "_U4131":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U491":{ + "_U414":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U488":{ + "affine_func$add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U489":{ + "affine_func$add_all__U412":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U483":{ + "affine_func$coeff_0_U406":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U485":{ + "affine_func$coeff_1_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U487":{ + "affine_func$const_term_U410":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U484":{ + "affine_func$mul_d0__U407":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U486":{ + "affine_func$mul_d1__U409":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6138,12 +5582,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U492$c0_lutcnst":{ + "d_0_am__U415$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U492$lut$lut":{ + "d_0_am__U415$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6262,18 +5706,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U490.out"], - ["d_1_inc.in1","_U4901.out"], - ["cmp_time.in1","_U491.out"], - ["affine_func$mul_d0__U484.out","affine_func$add_all__U488.in0"], - ["affine_func$mul_d1__U486.out","affine_func$add_all__U488.in1"], - ["affine_func$add_all__U489.in0","affine_func$add_all__U488.out"], - ["affine_func$const_term_U487.out","affine_func$add_all__U489.in1"], - ["time_diff.in0","affine_func$add_all__U489.out"], - ["affine_func$mul_d0__U484.in0","affine_func$coeff_0_U483.out"], - ["affine_func$mul_d1__U486.in0","affine_func$coeff_1_U485.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U484.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U486.in1"], + ["d_0_inc.in1","_U413.out"], + ["d_1_inc.in1","_U4131.out"], + ["cmp_time.in1","_U414.out"], + ["affine_func$mul_d0__U407.out","affine_func$add_all__U411.in0"], + ["affine_func$mul_d1__U409.out","affine_func$add_all__U411.in1"], + ["affine_func$add_all__U412.in0","affine_func$add_all__U411.out"], + ["affine_func$const_term_U410.out","affine_func$add_all__U412.in1"], + ["time_diff.in0","affine_func$add_all__U412.out"], + ["affine_func$mul_d0__U407.in0","affine_func$coeff_0_U406.out"], + ["affine_func$mul_d1__U409.in0","affine_func$coeff_1_U408.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U407.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U409.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6296,10 +5740,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U492$lut$lut.bit.in.2","d_0_am__U492$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U492$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U492$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U492$lut$lut.bit.out"], + ["d_0_am__U415$lut$lut.bit.in.2","d_0_am__U415$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U415$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U415$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U415$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6335,7 +5779,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U496":{ + "affine_controller__U418":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6343,49 +5787,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U505":{ + "_U427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5051":{ + "_U4271":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U506":{ + "_U428":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U503":{ + "affine_func$add_all__U425":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U504":{ + "affine_func$add_all__U426":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U498":{ + "affine_func$coeff_0_U420":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U500":{ + "affine_func$coeff_1_U422":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U502":{ + "affine_func$const_term_U424":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U499":{ + "affine_func$mul_d0__U421":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U501":{ + "affine_func$mul_d1__U423":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6449,12 +5893,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U507$c0_lutcnst":{ + "d_0_am__U429$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U507$lut$lut":{ + "d_0_am__U429$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6573,18 +6017,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U505.out"], - ["d_1_inc.in1","_U5051.out"], - ["cmp_time.in1","_U506.out"], - ["affine_func$mul_d0__U499.out","affine_func$add_all__U503.in0"], - ["affine_func$mul_d1__U501.out","affine_func$add_all__U503.in1"], - ["affine_func$add_all__U504.in0","affine_func$add_all__U503.out"], - ["affine_func$const_term_U502.out","affine_func$add_all__U504.in1"], - ["time_diff.in0","affine_func$add_all__U504.out"], - ["affine_func$mul_d0__U499.in0","affine_func$coeff_0_U498.out"], - ["affine_func$mul_d1__U501.in0","affine_func$coeff_1_U500.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U499.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U501.in1"], + ["d_0_inc.in1","_U427.out"], + ["d_1_inc.in1","_U4271.out"], + ["cmp_time.in1","_U428.out"], + ["affine_func$mul_d0__U421.out","affine_func$add_all__U425.in0"], + ["affine_func$mul_d1__U423.out","affine_func$add_all__U425.in1"], + ["affine_func$add_all__U426.in0","affine_func$add_all__U425.out"], + ["affine_func$const_term_U424.out","affine_func$add_all__U426.in1"], + ["time_diff.in0","affine_func$add_all__U426.out"], + ["affine_func$mul_d0__U421.in0","affine_func$coeff_0_U420.out"], + ["affine_func$mul_d1__U423.in0","affine_func$coeff_1_U422.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U421.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U423.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6607,10 +6051,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U507$lut$lut.bit.in.2","d_0_am__U507$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U507$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U507$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U507$lut$lut.bit.out"], + ["d_0_am__U429$lut$lut.bit.in.2","d_0_am__U429$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U429$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U429$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U429$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6646,7 +6090,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U511":{ + "affine_controller__U432":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6654,49 +6098,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U520":{ + "_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5201":{ + "_U4411":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U521":{ + "_U442":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U518":{ + "affine_func$add_all__U439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U519":{ + "affine_func$add_all__U440":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U513":{ + "affine_func$coeff_0_U434":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U515":{ + "affine_func$coeff_1_U436":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U517":{ + "affine_func$const_term_U438":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U514":{ + "affine_func$mul_d0__U435":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U516":{ + "affine_func$mul_d1__U437":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6760,12 +6204,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U522$c0_lutcnst":{ + "d_0_am__U443$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U522$lut$lut":{ + "d_0_am__U443$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6884,18 +6328,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U520.out"], - ["d_1_inc.in1","_U5201.out"], - ["cmp_time.in1","_U521.out"], - ["affine_func$mul_d0__U514.out","affine_func$add_all__U518.in0"], - ["affine_func$mul_d1__U516.out","affine_func$add_all__U518.in1"], - ["affine_func$add_all__U519.in0","affine_func$add_all__U518.out"], - ["affine_func$const_term_U517.out","affine_func$add_all__U519.in1"], - ["time_diff.in0","affine_func$add_all__U519.out"], - ["affine_func$mul_d0__U514.in0","affine_func$coeff_0_U513.out"], - ["affine_func$mul_d1__U516.in0","affine_func$coeff_1_U515.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U514.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U516.in1"], + ["d_0_inc.in1","_U441.out"], + ["d_1_inc.in1","_U4411.out"], + ["cmp_time.in1","_U442.out"], + ["affine_func$mul_d0__U435.out","affine_func$add_all__U439.in0"], + ["affine_func$mul_d1__U437.out","affine_func$add_all__U439.in1"], + ["affine_func$add_all__U440.in0","affine_func$add_all__U439.out"], + ["affine_func$const_term_U438.out","affine_func$add_all__U440.in1"], + ["time_diff.in0","affine_func$add_all__U440.out"], + ["affine_func$mul_d0__U435.in0","affine_func$coeff_0_U434.out"], + ["affine_func$mul_d1__U437.in0","affine_func$coeff_1_U436.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U435.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U437.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6918,10 +6362,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U522$lut$lut.bit.in.2","d_0_am__U522$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U522$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U522$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U522$lut$lut.bit.out"], + ["d_0_am__U443$lut$lut.bit.in.2","d_0_am__U443$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U443$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U443$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U443$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6957,7 +6401,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U526":{ + "affine_controller__U446":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6965,49 +6409,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U535":{ + "_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5351":{ + "_U4551":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U536":{ + "_U456":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U533":{ + "affine_func$add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U534":{ + "affine_func$add_all__U454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U528":{ + "affine_func$coeff_0_U448":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U530":{ + "affine_func$coeff_1_U450":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U532":{ + "affine_func$const_term_U452":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U529":{ + "affine_func$mul_d0__U449":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U531":{ + "affine_func$mul_d1__U451":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7071,12 +6515,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U537$c0_lutcnst":{ + "d_0_am__U457$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U537$lut$lut":{ + "d_0_am__U457$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7195,18 +6639,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U535.out"], - ["d_1_inc.in1","_U5351.out"], - ["cmp_time.in1","_U536.out"], - ["affine_func$mul_d0__U529.out","affine_func$add_all__U533.in0"], - ["affine_func$mul_d1__U531.out","affine_func$add_all__U533.in1"], - ["affine_func$add_all__U534.in0","affine_func$add_all__U533.out"], - ["affine_func$const_term_U532.out","affine_func$add_all__U534.in1"], - ["time_diff.in0","affine_func$add_all__U534.out"], - ["affine_func$mul_d0__U529.in0","affine_func$coeff_0_U528.out"], - ["affine_func$mul_d1__U531.in0","affine_func$coeff_1_U530.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U529.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U531.in1"], + ["d_0_inc.in1","_U455.out"], + ["d_1_inc.in1","_U4551.out"], + ["cmp_time.in1","_U456.out"], + ["affine_func$mul_d0__U449.out","affine_func$add_all__U453.in0"], + ["affine_func$mul_d1__U451.out","affine_func$add_all__U453.in1"], + ["affine_func$add_all__U454.in0","affine_func$add_all__U453.out"], + ["affine_func$const_term_U452.out","affine_func$add_all__U454.in1"], + ["time_diff.in0","affine_func$add_all__U454.out"], + ["affine_func$mul_d0__U449.in0","affine_func$coeff_0_U448.out"], + ["affine_func$mul_d1__U451.in0","affine_func$coeff_1_U450.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U449.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U451.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -7229,10 +6673,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U537$lut$lut.bit.in.2","d_0_am__U537$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U537$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U537$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U537$lut$lut.bit.out"], + ["d_0_am__U457$lut$lut.bit.in.2","d_0_am__U457$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U457$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U457$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U457$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7268,7 +6712,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U541":{ + "affine_controller__U460":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -7276,49 +6720,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U550":{ + "_U469":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5501":{ + "_U4691":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U551":{ + "_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U548":{ + "affine_func$add_all__U467":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U549":{ + "affine_func$add_all__U468":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U543":{ + "affine_func$coeff_0_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U545":{ + "affine_func$coeff_1_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U547":{ + "affine_func$const_term_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U544":{ + "affine_func$mul_d0__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U546":{ + "affine_func$mul_d1__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7382,12 +6826,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U552$c0_lutcnst":{ + "d_0_am__U471$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U552$lut$lut":{ + "d_0_am__U471$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7506,18 +6950,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U550.out"], - ["d_1_inc.in1","_U5501.out"], - ["cmp_time.in1","_U551.out"], - ["affine_func$mul_d0__U544.out","affine_func$add_all__U548.in0"], - ["affine_func$mul_d1__U546.out","affine_func$add_all__U548.in1"], - ["affine_func$add_all__U549.in0","affine_func$add_all__U548.out"], - ["affine_func$const_term_U547.out","affine_func$add_all__U549.in1"], - ["time_diff.in0","affine_func$add_all__U549.out"], - ["affine_func$mul_d0__U544.in0","affine_func$coeff_0_U543.out"], - ["affine_func$mul_d1__U546.in0","affine_func$coeff_1_U545.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U544.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U546.in1"], + ["d_0_inc.in1","_U469.out"], + ["d_1_inc.in1","_U4691.out"], + ["cmp_time.in1","_U470.out"], + ["affine_func$mul_d0__U463.out","affine_func$add_all__U467.in0"], + ["affine_func$mul_d1__U465.out","affine_func$add_all__U467.in1"], + ["affine_func$add_all__U468.in0","affine_func$add_all__U467.out"], + ["affine_func$const_term_U466.out","affine_func$add_all__U468.in1"], + ["time_diff.in0","affine_func$add_all__U468.out"], + ["affine_func$mul_d0__U463.in0","affine_func$coeff_0_U462.out"], + ["affine_func$mul_d1__U465.in0","affine_func$coeff_1_U464.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U463.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U465.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -7540,10 +6984,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U552$lut$lut.bit.in.2","d_0_am__U552$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U552$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U552$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U552$lut$lut.bit.out"], + ["d_0_am__U471$lut$lut.bit.in.2","d_0_am__U471$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U471$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U471$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U471$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7579,7 +7023,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U556":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -7587,157 +7031,157 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U583":{ + "_U74":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5831":{ + "_U741":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5832":{ + "_U742":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5833":{ + "_U743":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5834":{ + "_U744":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5835":{ + "_U745":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5836":{ + "_U746":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5837":{ + "_U747":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U584":{ + "_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U575":{ + "affine_func$add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U576":{ + "affine_func$add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U577":{ + "affine_func$add_all__U68":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U578":{ + "affine_func$add_all__U69":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U579":{ + "affine_func$add_all__U70":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U580":{ + "affine_func$add_all__U71":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U581":{ + "affine_func$add_all__U72":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U582":{ + "affine_func$add_all__U73":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U558":{ + "affine_func$coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U560":{ + "affine_func$coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "affine_func$coeff_2_U562":{ + "affine_func$coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "affine_func$coeff_3_U564":{ + "affine_func$coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "affine_func$coeff_4_U566":{ + "affine_func$coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000001c0"]} + "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "affine_func$coeff_5_U568":{ + "affine_func$coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000020"]} + "modargs":{"value":[["BitVector",32],"32'h000000f0"]} }, - "affine_func$coeff_6_U570":{ + "affine_func$coeff_6_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_7_U572":{ + "affine_func$coeff_7_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U574":{ + "affine_func$const_term_U65":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012d60"]} + "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "affine_func$mul_d0__U559":{ + "affine_func$mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U561":{ + "affine_func$mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U563":{ + "affine_func$mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U565":{ + "affine_func$mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U567":{ + "affine_func$mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U569":{ + "affine_func$mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U571":{ + "affine_func$mul_d6__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d7__U573":{ + "affine_func$mul_d7__U64":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7801,72 +7245,72 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U585$c0_lutcnst":{ + "d_0_am__U76$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U585$lut$lut":{ + "d_0_am__U76$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U586$c0_lutcnst":{ + "d_0_am__U77$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U586$lut$lut":{ + "d_0_am__U77$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U587$c0_lutcnst":{ + "d_0_am__U78$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U587$lut$lut":{ + "d_0_am__U78$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U588$c0_lutcnst":{ + "d_0_am__U79$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U588$lut$lut":{ + "d_0_am__U79$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U589$c0_lutcnst":{ + "d_0_am__U80$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U589$lut$lut":{ + "d_0_am__U80$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U590$c0_lutcnst":{ + "d_0_am__U81$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U590$lut$lut":{ + "d_0_am__U81$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U591$c0_lutcnst":{ + "d_0_am__U82$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U591$lut$lut":{ + "d_0_am__U82$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7915,62 +7359,62 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U592$c0_lutcnst":{ + "d_1_am__U83$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U592$lut$lut":{ + "d_1_am__U83$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U593$c0_lutcnst":{ + "d_1_am__U84$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U593$lut$lut":{ + "d_1_am__U84$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U594$c0_lutcnst":{ + "d_1_am__U85$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U594$lut$lut":{ + "d_1_am__U85$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U595$c0_lutcnst":{ + "d_1_am__U86$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U595$lut$lut":{ + "d_1_am__U86$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U596$c0_lutcnst":{ + "d_1_am__U87$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U596$lut$lut":{ + "d_1_am__U87$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U597$c0_lutcnst":{ + "d_1_am__U88$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U597$lut$lut":{ + "d_1_am__U88$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8019,52 +7463,52 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U598$c0_lutcnst":{ + "d_2_am__U89$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U598$lut$lut":{ + "d_2_am__U89$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U599$c0_lutcnst":{ + "d_2_am__U90$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U599$lut$lut":{ + "d_2_am__U90$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U600$c0_lutcnst":{ + "d_2_am__U91$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U600$lut$lut":{ + "d_2_am__U91$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U601$c0_lutcnst":{ + "d_2_am__U92$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U601$lut$lut":{ + "d_2_am__U92$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U602$c0_lutcnst":{ + "d_2_am__U93$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U602$lut$lut":{ + "d_2_am__U93$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8113,42 +7557,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U603$c0_lutcnst":{ + "d_3_am__U94$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U603$lut$lut":{ + "d_3_am__U94$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U604$c0_lutcnst":{ + "d_3_am__U95$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U604$lut$lut":{ + "d_3_am__U95$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U605$c0_lutcnst":{ + "d_3_am__U96$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U605$lut$lut":{ + "d_3_am__U96$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U606$c0_lutcnst":{ + "d_3_am__U97$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U606$lut$lut":{ + "d_3_am__U97$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8197,32 +7641,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U607$c0_lutcnst":{ + "d_4_am__U100$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U607$lut$lut":{ + "d_4_am__U100$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U608$c0_lutcnst":{ + "d_4_am__U98$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U608$lut$lut":{ + "d_4_am__U98$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U609$c0_lutcnst":{ + "d_4_am__U99$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U609$lut$lut":{ + "d_4_am__U99$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8238,7 +7682,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_4_min":{ "genref":"coreir.const", @@ -8271,22 +7715,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U610$c0_lutcnst":{ + "d_5_am__U101$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U610$lut$lut":{ + "d_5_am__U101$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_5_am__U611$c0_lutcnst":{ + "d_5_am__U102$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U611$lut$lut":{ + "d_5_am__U102$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8302,7 +7746,7 @@ "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + "modargs":{"value":[["BitVector",32],"32'h0000001d"]} }, "d_5_min":{ "genref":"coreir.const", @@ -8335,12 +7779,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U612$c0_lutcnst":{ + "d_6_am__U103$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U612$lut$lut":{ + "d_6_am__U103$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8356,7 +7800,7 @@ "d_6_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h0000001d"]} }, "d_6_min":{ "genref":"coreir.const", @@ -8489,48 +7933,48 @@ } }, "connections":[ - ["d_0_inc.in1","_U583.out"], - ["d_1_inc.in1","_U5831.out"], - ["d_2_inc.in1","_U5832.out"], - ["d_3_inc.in1","_U5833.out"], - ["d_4_inc.in1","_U5834.out"], - ["d_5_inc.in1","_U5835.out"], - ["d_6_inc.in1","_U5836.out"], - ["d_7_inc.in1","_U5837.out"], - ["cmp_time.in1","_U584.out"], - ["affine_func$mul_d0__U559.out","affine_func$add_all__U575.in0"], - ["affine_func$mul_d1__U561.out","affine_func$add_all__U575.in1"], - ["affine_func$add_all__U576.in0","affine_func$add_all__U575.out"], - ["affine_func$mul_d2__U563.out","affine_func$add_all__U576.in1"], - ["affine_func$add_all__U577.in0","affine_func$add_all__U576.out"], - ["affine_func$mul_d3__U565.out","affine_func$add_all__U577.in1"], - ["affine_func$add_all__U578.in0","affine_func$add_all__U577.out"], - ["affine_func$mul_d4__U567.out","affine_func$add_all__U578.in1"], - ["affine_func$add_all__U579.in0","affine_func$add_all__U578.out"], - ["affine_func$mul_d5__U569.out","affine_func$add_all__U579.in1"], - ["affine_func$add_all__U580.in0","affine_func$add_all__U579.out"], - ["affine_func$mul_d6__U571.out","affine_func$add_all__U580.in1"], - ["affine_func$add_all__U581.in0","affine_func$add_all__U580.out"], - ["affine_func$mul_d7__U573.out","affine_func$add_all__U581.in1"], - ["affine_func$add_all__U582.in0","affine_func$add_all__U581.out"], - ["affine_func$const_term_U574.out","affine_func$add_all__U582.in1"], - ["time_diff.in0","affine_func$add_all__U582.out"], - ["affine_func$mul_d0__U559.in0","affine_func$coeff_0_U558.out"], - ["affine_func$mul_d1__U561.in0","affine_func$coeff_1_U560.out"], - ["affine_func$mul_d2__U563.in0","affine_func$coeff_2_U562.out"], - ["affine_func$mul_d3__U565.in0","affine_func$coeff_3_U564.out"], - ["affine_func$mul_d4__U567.in0","affine_func$coeff_4_U566.out"], - ["affine_func$mul_d5__U569.in0","affine_func$coeff_5_U568.out"], - ["affine_func$mul_d6__U571.in0","affine_func$coeff_6_U570.out"], - ["affine_func$mul_d7__U573.in0","affine_func$coeff_7_U572.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U559.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U561.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U563.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U565.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U567.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U569.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U571.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U573.in1"], + ["d_0_inc.in1","_U74.out"], + ["d_1_inc.in1","_U741.out"], + ["d_2_inc.in1","_U742.out"], + ["d_3_inc.in1","_U743.out"], + ["d_4_inc.in1","_U744.out"], + ["d_5_inc.in1","_U745.out"], + ["d_6_inc.in1","_U746.out"], + ["d_7_inc.in1","_U747.out"], + ["cmp_time.in1","_U75.out"], + ["affine_func$mul_d0__U50.out","affine_func$add_all__U66.in0"], + ["affine_func$mul_d1__U52.out","affine_func$add_all__U66.in1"], + ["affine_func$add_all__U67.in0","affine_func$add_all__U66.out"], + ["affine_func$mul_d2__U54.out","affine_func$add_all__U67.in1"], + ["affine_func$add_all__U68.in0","affine_func$add_all__U67.out"], + ["affine_func$mul_d3__U56.out","affine_func$add_all__U68.in1"], + ["affine_func$add_all__U69.in0","affine_func$add_all__U68.out"], + ["affine_func$mul_d4__U58.out","affine_func$add_all__U69.in1"], + ["affine_func$add_all__U70.in0","affine_func$add_all__U69.out"], + ["affine_func$mul_d5__U60.out","affine_func$add_all__U70.in1"], + ["affine_func$add_all__U71.in0","affine_func$add_all__U70.out"], + ["affine_func$mul_d6__U62.out","affine_func$add_all__U71.in1"], + ["affine_func$add_all__U72.in0","affine_func$add_all__U71.out"], + ["affine_func$mul_d7__U64.out","affine_func$add_all__U72.in1"], + ["affine_func$add_all__U73.in0","affine_func$add_all__U72.out"], + ["affine_func$const_term_U65.out","affine_func$add_all__U73.in1"], + ["time_diff.in0","affine_func$add_all__U73.out"], + ["affine_func$mul_d0__U50.in0","affine_func$coeff_0_U49.out"], + ["affine_func$mul_d1__U52.in0","affine_func$coeff_1_U51.out"], + ["affine_func$mul_d2__U54.in0","affine_func$coeff_2_U53.out"], + ["affine_func$mul_d3__U56.in0","affine_func$coeff_3_U55.out"], + ["affine_func$mul_d4__U58.in0","affine_func$coeff_4_U57.out"], + ["affine_func$mul_d5__U60.in0","affine_func$coeff_5_U59.out"], + ["affine_func$mul_d6__U62.in0","affine_func$coeff_6_U61.out"], + ["affine_func$mul_d7__U64.in0","affine_func$coeff_7_U63.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U50.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U52.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U54.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U56.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U58.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U60.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U62.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U64.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -8559,28 +8003,28 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U585$lut$lut.bit.in.2","d_0_am__U585$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U585$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U585$lut$lut.bit.in.1"], - ["d_0_am__U586$lut$lut.bit.in.0","d_0_am__U585$lut$lut.bit.out"], - ["d_0_am__U586$lut$lut.bit.in.2","d_0_am__U586$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U586$lut$lut.bit.in.1"], - ["d_0_am__U587$lut$lut.bit.in.0","d_0_am__U586$lut$lut.bit.out"], - ["d_0_am__U587$lut$lut.bit.in.2","d_0_am__U587$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U587$lut$lut.bit.in.1"], - ["d_0_am__U588$lut$lut.bit.in.0","d_0_am__U587$lut$lut.bit.out"], - ["d_0_am__U588$lut$lut.bit.in.2","d_0_am__U588$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U588$lut$lut.bit.in.1"], - ["d_0_am__U589$lut$lut.bit.in.0","d_0_am__U588$lut$lut.bit.out"], - ["d_0_am__U589$lut$lut.bit.in.2","d_0_am__U589$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U589$lut$lut.bit.in.1"], - ["d_0_am__U590$lut$lut.bit.in.0","d_0_am__U589$lut$lut.bit.out"], - ["d_0_am__U590$lut$lut.bit.in.2","d_0_am__U590$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U590$lut$lut.bit.in.1"], - ["d_0_am__U591$lut$lut.bit.in.0","d_0_am__U590$lut$lut.bit.out"], - ["d_0_am__U591$lut$lut.bit.in.2","d_0_am__U591$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U591$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U591$lut$lut.bit.out"], + ["d_0_am__U76$lut$lut.bit.in.2","d_0_am__U76$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U76$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U76$lut$lut.bit.in.1"], + ["d_0_am__U77$lut$lut.bit.in.0","d_0_am__U76$lut$lut.bit.out"], + ["d_0_am__U77$lut$lut.bit.in.2","d_0_am__U77$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U77$lut$lut.bit.in.1"], + ["d_0_am__U78$lut$lut.bit.in.0","d_0_am__U77$lut$lut.bit.out"], + ["d_0_am__U78$lut$lut.bit.in.2","d_0_am__U78$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U78$lut$lut.bit.in.1"], + ["d_0_am__U79$lut$lut.bit.in.0","d_0_am__U78$lut$lut.bit.out"], + ["d_0_am__U79$lut$lut.bit.in.2","d_0_am__U79$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U79$lut$lut.bit.in.1"], + ["d_0_am__U80$lut$lut.bit.in.0","d_0_am__U79$lut$lut.bit.out"], + ["d_0_am__U80$lut$lut.bit.in.2","d_0_am__U80$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U80$lut$lut.bit.in.1"], + ["d_0_am__U81$lut$lut.bit.in.0","d_0_am__U80$lut$lut.bit.out"], + ["d_0_am__U81$lut$lut.bit.in.2","d_0_am__U81$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U81$lut$lut.bit.in.1"], + ["d_0_am__U82$lut$lut.bit.in.0","d_0_am__U81$lut$lut.bit.out"], + ["d_0_am__U82$lut$lut.bit.in.2","d_0_am__U82$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U82$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U82$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8597,25 +8041,25 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U592$lut$lut.bit.in.2","d_1_am__U592$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U592$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U592$lut$lut.bit.in.1"], - ["d_1_am__U593$lut$lut.bit.in.0","d_1_am__U592$lut$lut.bit.out"], - ["d_1_am__U593$lut$lut.bit.in.2","d_1_am__U593$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U593$lut$lut.bit.in.1"], - ["d_1_am__U594$lut$lut.bit.in.0","d_1_am__U593$lut$lut.bit.out"], - ["d_1_am__U594$lut$lut.bit.in.2","d_1_am__U594$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U594$lut$lut.bit.in.1"], - ["d_1_am__U595$lut$lut.bit.in.0","d_1_am__U594$lut$lut.bit.out"], - ["d_1_am__U595$lut$lut.bit.in.2","d_1_am__U595$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U595$lut$lut.bit.in.1"], - ["d_1_am__U596$lut$lut.bit.in.0","d_1_am__U595$lut$lut.bit.out"], - ["d_1_am__U596$lut$lut.bit.in.2","d_1_am__U596$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U596$lut$lut.bit.in.1"], - ["d_1_am__U597$lut$lut.bit.in.0","d_1_am__U596$lut$lut.bit.out"], - ["d_1_am__U597$lut$lut.bit.in.2","d_1_am__U597$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U597$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U597$lut$lut.bit.out"], + ["d_1_am__U83$lut$lut.bit.in.2","d_1_am__U83$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U83$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U83$lut$lut.bit.in.1"], + ["d_1_am__U84$lut$lut.bit.in.0","d_1_am__U83$lut$lut.bit.out"], + ["d_1_am__U84$lut$lut.bit.in.2","d_1_am__U84$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U84$lut$lut.bit.in.1"], + ["d_1_am__U85$lut$lut.bit.in.0","d_1_am__U84$lut$lut.bit.out"], + ["d_1_am__U85$lut$lut.bit.in.2","d_1_am__U85$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U85$lut$lut.bit.in.1"], + ["d_1_am__U86$lut$lut.bit.in.0","d_1_am__U85$lut$lut.bit.out"], + ["d_1_am__U86$lut$lut.bit.in.2","d_1_am__U86$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U86$lut$lut.bit.in.1"], + ["d_1_am__U87$lut$lut.bit.in.0","d_1_am__U86$lut$lut.bit.out"], + ["d_1_am__U87$lut$lut.bit.in.2","d_1_am__U87$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U87$lut$lut.bit.in.1"], + ["d_1_am__U88$lut$lut.bit.in.0","d_1_am__U87$lut$lut.bit.out"], + ["d_1_am__U88$lut$lut.bit.in.2","d_1_am__U88$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U88$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U88$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -8632,22 +8076,22 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U598$lut$lut.bit.in.2","d_2_am__U598$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U598$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U598$lut$lut.bit.in.1"], - ["d_2_am__U599$lut$lut.bit.in.0","d_2_am__U598$lut$lut.bit.out"], - ["d_2_am__U599$lut$lut.bit.in.2","d_2_am__U599$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U599$lut$lut.bit.in.1"], - ["d_2_am__U600$lut$lut.bit.in.0","d_2_am__U599$lut$lut.bit.out"], - ["d_2_am__U600$lut$lut.bit.in.2","d_2_am__U600$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U600$lut$lut.bit.in.1"], - ["d_2_am__U601$lut$lut.bit.in.0","d_2_am__U600$lut$lut.bit.out"], - ["d_2_am__U601$lut$lut.bit.in.2","d_2_am__U601$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U601$lut$lut.bit.in.1"], - ["d_2_am__U602$lut$lut.bit.in.0","d_2_am__U601$lut$lut.bit.out"], - ["d_2_am__U602$lut$lut.bit.in.2","d_2_am__U602$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U602$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U602$lut$lut.bit.out"], + ["d_2_am__U89$lut$lut.bit.in.2","d_2_am__U89$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U89$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U89$lut$lut.bit.in.1"], + ["d_2_am__U90$lut$lut.bit.in.0","d_2_am__U89$lut$lut.bit.out"], + ["d_2_am__U90$lut$lut.bit.in.2","d_2_am__U90$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U90$lut$lut.bit.in.1"], + ["d_2_am__U91$lut$lut.bit.in.0","d_2_am__U90$lut$lut.bit.out"], + ["d_2_am__U91$lut$lut.bit.in.2","d_2_am__U91$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U91$lut$lut.bit.in.1"], + ["d_2_am__U92$lut$lut.bit.in.0","d_2_am__U91$lut$lut.bit.out"], + ["d_2_am__U92$lut$lut.bit.in.2","d_2_am__U92$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U92$lut$lut.bit.in.1"], + ["d_2_am__U93$lut$lut.bit.in.0","d_2_am__U92$lut$lut.bit.out"], + ["d_2_am__U93$lut$lut.bit.in.2","d_2_am__U93$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U93$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U93$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -8664,19 +8108,19 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U603$lut$lut.bit.in.2","d_3_am__U603$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U603$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U603$lut$lut.bit.in.1"], - ["d_3_am__U604$lut$lut.bit.in.0","d_3_am__U603$lut$lut.bit.out"], - ["d_3_am__U604$lut$lut.bit.in.2","d_3_am__U604$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U604$lut$lut.bit.in.1"], - ["d_3_am__U605$lut$lut.bit.in.0","d_3_am__U604$lut$lut.bit.out"], - ["d_3_am__U605$lut$lut.bit.in.2","d_3_am__U605$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U605$lut$lut.bit.in.1"], - ["d_3_am__U606$lut$lut.bit.in.0","d_3_am__U605$lut$lut.bit.out"], - ["d_3_am__U606$lut$lut.bit.in.2","d_3_am__U606$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U606$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U606$lut$lut.bit.out"], + ["d_3_am__U94$lut$lut.bit.in.2","d_3_am__U94$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U94$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U94$lut$lut.bit.in.1"], + ["d_3_am__U95$lut$lut.bit.in.0","d_3_am__U94$lut$lut.bit.out"], + ["d_3_am__U95$lut$lut.bit.in.2","d_3_am__U95$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U95$lut$lut.bit.in.1"], + ["d_3_am__U96$lut$lut.bit.in.0","d_3_am__U95$lut$lut.bit.out"], + ["d_3_am__U96$lut$lut.bit.in.2","d_3_am__U96$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U96$lut$lut.bit.in.1"], + ["d_3_am__U97$lut$lut.bit.in.0","d_3_am__U96$lut$lut.bit.out"], + ["d_3_am__U97$lut$lut.bit.in.2","d_3_am__U97$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U97$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U97$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -8693,16 +8137,16 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U607$lut$lut.bit.in.2","d_4_am__U607$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U607$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U607$lut$lut.bit.in.1"], - ["d_4_am__U608$lut$lut.bit.in.0","d_4_am__U607$lut$lut.bit.out"], - ["d_4_am__U608$lut$lut.bit.in.2","d_4_am__U608$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U608$lut$lut.bit.in.1"], - ["d_4_am__U609$lut$lut.bit.in.0","d_4_am__U608$lut$lut.bit.out"], - ["d_4_am__U609$lut$lut.bit.in.2","d_4_am__U609$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U609$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U609$lut$lut.bit.out"], + ["d_4_am__U100$lut$lut.bit.in.2","d_4_am__U100$c0_lutcnst.bit.out"], + ["d_4_am__U99$lut$lut.bit.out","d_4_am__U100$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_4_am__U100$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U100$lut$lut.bit.out"], + ["d_4_am__U98$lut$lut.bit.in.2","d_4_am__U98$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U98$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U98$lut$lut.bit.in.1"], + ["d_4_am__U99$lut$lut.bit.in.0","d_4_am__U98$lut$lut.bit.out"], + ["d_4_am__U99$lut$lut.bit.in.2","d_4_am__U99$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U99$lut$lut.bit.in.1"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -8719,13 +8163,13 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U610$lut$lut.bit.in.2","d_5_am__U610$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U610$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U610$lut$lut.bit.in.1"], - ["d_5_am__U611$lut$lut.bit.in.0","d_5_am__U610$lut$lut.bit.out"], - ["d_5_am__U611$lut$lut.bit.in.2","d_5_am__U611$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U611$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U611$lut$lut.bit.out"], + ["d_5_am__U101$lut$lut.bit.in.2","d_5_am__U101$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U101$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U101$lut$lut.bit.in.1"], + ["d_5_am__U102$lut$lut.bit.in.0","d_5_am__U101$lut$lut.bit.out"], + ["d_5_am__U102$lut$lut.bit.in.2","d_5_am__U102$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U102$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U102$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -8742,10 +8186,10 @@ ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U612$lut$lut.bit.in.2","d_6_am__U612$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U612$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U612$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U612$lut$lut.bit.out"], + ["d_6_am__U103$lut$lut.bit.in.2","d_6_am__U103$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U103$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U103$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U103$lut$lut.bit.out"], ["d_6_reg$reg0.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -8781,7 +8225,7 @@ ["self.d.7","d_7_reg$reg0.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U473":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -8789,848 +8233,1582 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U83":{ + "_U500":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U831":{ + "_U5001":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U832":{ + "_U5002":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U833":{ + "_U5003":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U834":{ + "_U5004":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U835":{ + "_U5005":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U836":{ + "_U5006":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U837":{ + "_U5007":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U84":{ + "_U501":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U75":{ + "affine_func$add_all__U492":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U76":{ + "affine_func$add_all__U493":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U77":{ + "affine_func$add_all__U494":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U78":{ + "affine_func$add_all__U495":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U79":{ + "affine_func$add_all__U496":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U80":{ + "affine_func$add_all__U497":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U81":{ + "affine_func$add_all__U498":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U82":{ + "affine_func$add_all__U499":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U58":{ + "affine_func$coeff_0_U475":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U60":{ + "affine_func$coeff_1_U477":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "affine_func$coeff_2_U62":{ + "affine_func$coeff_2_U479":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "affine_func$coeff_3_U64":{ + "affine_func$coeff_3_U481":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "affine_func$coeff_4_U66":{ + "affine_func$coeff_4_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001f80"]} + "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "affine_func$coeff_5_U68":{ + "affine_func$coeff_5_U485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000000f0"]} + "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "affine_func$coeff_6_U70":{ + "affine_func$coeff_6_U487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_7_U72":{ + "affine_func$coeff_7_U489":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U491":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012d60"]} + }, + "affine_func$mul_d0__U476":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U478":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U480":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U482":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d4__U484":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U486":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d6__U488":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d7__U490":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$count$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} + }, + "d_0_am__U502$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U502$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U503$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U503$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U504$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U504$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U505$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U505$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U506$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U506$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U507$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U507$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U508$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U508$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U509$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U509$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U510$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U510$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U511$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U511$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U512$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U512$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U513$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U513$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U514$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U514$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U74":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U59":{ - "genref":"coreir.mul", + "d_1_next_value":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U61":{ - "genref":"coreir.mul", + "d_1_next_value_at_max":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U63":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_1_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d3__U65":{ - "genref":"coreir.mul", + "d_1_reg$clrMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U67":{ - "genref":"coreir.mul", + "d_1_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U69":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_1_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d6__U71":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_am__U515$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$mul_d7__U73":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_am__U515$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_2_am__U516$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_2_am__U516$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$and$c0_lutcnst":{ + "d_2_am__U517$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$lut$lut":{ + "d_2_am__U517$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "d_2_am__U518$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$count$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "d_2_am__U518$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$enMux":{ - "genref":"coreir.mux", + "d_2_am__U519$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U519$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "cycle_time$inc":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "cycle_time$max":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cycle_time$ult":{ - "genref":"coreir.ult", + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_am__U85$c0_lutcnst":{ + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_am__U520$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U85$lut$lut":{ + "d_3_am__U520$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U86$c0_lutcnst":{ + "d_3_am__U521$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U86$lut$lut":{ + "d_3_am__U521$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U87$c0_lutcnst":{ + "d_3_am__U522$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U87$lut$lut":{ + "d_3_am__U522$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U88$c0_lutcnst":{ + "d_3_am__U523$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U88$lut$lut":{ + "d_3_am__U523$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U89$c0_lutcnst":{ + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U524$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U89$lut$lut":{ + "d_4_am__U524$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U90$c0_lutcnst":{ + "d_4_am__U525$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U90$lut$lut":{ + "d_4_am__U525$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U91$c0_lutcnst":{ + "d_4_am__U526$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U91$lut$lut":{ + "d_4_am__U526$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000000d"]} }, - "d_0_min":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_4_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_4_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_4_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_4_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_4_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_4_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U92$c0_lutcnst":{ + "d_5_am__U527$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U92$lut$lut":{ + "d_5_am__U527$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U93$c0_lutcnst":{ + "d_5_am__U528$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U93$lut$lut":{ + "d_5_am__U528$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U94$c0_lutcnst":{ + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_6_am__U529$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U94$lut$lut":{ + "d_6_am__U529$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U95$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000003"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U95$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U96$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_6_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U96$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_6_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U97$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_6_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U97$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_6_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_7_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_7_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_7_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_1_min":{ + "d_7_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_7_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_7_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$c0":{ + "d_7_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ + "d_7_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ + "d_7_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ + "d_7_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U100$c0_lutcnst":{ + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U100$lut$lut":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U101$c0_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U101$lut$lut":{ + "true4_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U102$c0_lutcnst":{ + "true5_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U102$lut$lut":{ + "true6_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U98$c0_lutcnst":{ + "true7_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U98$lut$lut":{ + "true8_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U99$c0_lutcnst":{ + "true9_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U99$lut$lut":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U500.out"], + ["d_1_inc.in1","_U5001.out"], + ["d_2_inc.in1","_U5002.out"], + ["d_3_inc.in1","_U5003.out"], + ["d_4_inc.in1","_U5004.out"], + ["d_5_inc.in1","_U5005.out"], + ["d_6_inc.in1","_U5006.out"], + ["d_7_inc.in1","_U5007.out"], + ["cmp_time.in1","_U501.out"], + ["affine_func$mul_d0__U476.out","affine_func$add_all__U492.in0"], + ["affine_func$mul_d1__U478.out","affine_func$add_all__U492.in1"], + ["affine_func$add_all__U493.in0","affine_func$add_all__U492.out"], + ["affine_func$mul_d2__U480.out","affine_func$add_all__U493.in1"], + ["affine_func$add_all__U494.in0","affine_func$add_all__U493.out"], + ["affine_func$mul_d3__U482.out","affine_func$add_all__U494.in1"], + ["affine_func$add_all__U495.in0","affine_func$add_all__U494.out"], + ["affine_func$mul_d4__U484.out","affine_func$add_all__U495.in1"], + ["affine_func$add_all__U496.in0","affine_func$add_all__U495.out"], + ["affine_func$mul_d5__U486.out","affine_func$add_all__U496.in1"], + ["affine_func$add_all__U497.in0","affine_func$add_all__U496.out"], + ["affine_func$mul_d6__U488.out","affine_func$add_all__U497.in1"], + ["affine_func$add_all__U498.in0","affine_func$add_all__U497.out"], + ["affine_func$mul_d7__U490.out","affine_func$add_all__U498.in1"], + ["affine_func$add_all__U499.in0","affine_func$add_all__U498.out"], + ["affine_func$const_term_U491.out","affine_func$add_all__U499.in1"], + ["time_diff.in0","affine_func$add_all__U499.out"], + ["affine_func$mul_d0__U476.in0","affine_func$coeff_0_U475.out"], + ["affine_func$mul_d1__U478.in0","affine_func$coeff_1_U477.out"], + ["affine_func$mul_d2__U480.in0","affine_func$coeff_2_U479.out"], + ["affine_func$mul_d3__U482.in0","affine_func$coeff_3_U481.out"], + ["affine_func$mul_d4__U484.in0","affine_func$coeff_4_U483.out"], + ["affine_func$mul_d5__U486.in0","affine_func$coeff_5_U485.out"], + ["affine_func$mul_d6__U488.in0","affine_func$coeff_6_U487.out"], + ["affine_func$mul_d7__U490.in0","affine_func$coeff_7_U489.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U476.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U478.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U480.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U482.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U484.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U486.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U488.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U490.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["d_7_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U502$lut$lut.bit.in.2","d_0_am__U502$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U502$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U502$lut$lut.bit.in.1"], + ["d_0_am__U503$lut$lut.bit.in.0","d_0_am__U502$lut$lut.bit.out"], + ["d_0_am__U503$lut$lut.bit.in.2","d_0_am__U503$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U503$lut$lut.bit.in.1"], + ["d_0_am__U504$lut$lut.bit.in.0","d_0_am__U503$lut$lut.bit.out"], + ["d_0_am__U504$lut$lut.bit.in.2","d_0_am__U504$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U504$lut$lut.bit.in.1"], + ["d_0_am__U505$lut$lut.bit.in.0","d_0_am__U504$lut$lut.bit.out"], + ["d_0_am__U505$lut$lut.bit.in.2","d_0_am__U505$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U505$lut$lut.bit.in.1"], + ["d_0_am__U506$lut$lut.bit.in.0","d_0_am__U505$lut$lut.bit.out"], + ["d_0_am__U506$lut$lut.bit.in.2","d_0_am__U506$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U506$lut$lut.bit.in.1"], + ["d_0_am__U507$lut$lut.bit.in.0","d_0_am__U506$lut$lut.bit.out"], + ["d_0_am__U507$lut$lut.bit.in.2","d_0_am__U507$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U507$lut$lut.bit.in.1"], + ["d_0_am__U508$lut$lut.bit.in.0","d_0_am__U507$lut$lut.bit.out"], + ["d_0_am__U508$lut$lut.bit.in.2","d_0_am__U508$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U508$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U508$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U509$lut$lut.bit.in.2","d_1_am__U509$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U509$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U509$lut$lut.bit.in.1"], + ["d_1_am__U510$lut$lut.bit.in.0","d_1_am__U509$lut$lut.bit.out"], + ["d_1_am__U510$lut$lut.bit.in.2","d_1_am__U510$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U510$lut$lut.bit.in.1"], + ["d_1_am__U511$lut$lut.bit.in.0","d_1_am__U510$lut$lut.bit.out"], + ["d_1_am__U511$lut$lut.bit.in.2","d_1_am__U511$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U511$lut$lut.bit.in.1"], + ["d_1_am__U512$lut$lut.bit.in.0","d_1_am__U511$lut$lut.bit.out"], + ["d_1_am__U512$lut$lut.bit.in.2","d_1_am__U512$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U512$lut$lut.bit.in.1"], + ["d_1_am__U513$lut$lut.bit.in.0","d_1_am__U512$lut$lut.bit.out"], + ["d_1_am__U513$lut$lut.bit.in.2","d_1_am__U513$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U513$lut$lut.bit.in.1"], + ["d_1_am__U514$lut$lut.bit.in.0","d_1_am__U513$lut$lut.bit.out"], + ["d_1_am__U514$lut$lut.bit.in.2","d_1_am__U514$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U514$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U514$lut$lut.bit.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U515$lut$lut.bit.in.2","d_2_am__U515$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U515$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U515$lut$lut.bit.in.1"], + ["d_2_am__U516$lut$lut.bit.in.0","d_2_am__U515$lut$lut.bit.out"], + ["d_2_am__U516$lut$lut.bit.in.2","d_2_am__U516$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U516$lut$lut.bit.in.1"], + ["d_2_am__U517$lut$lut.bit.in.0","d_2_am__U516$lut$lut.bit.out"], + ["d_2_am__U517$lut$lut.bit.in.2","d_2_am__U517$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U517$lut$lut.bit.in.1"], + ["d_2_am__U518$lut$lut.bit.in.0","d_2_am__U517$lut$lut.bit.out"], + ["d_2_am__U518$lut$lut.bit.in.2","d_2_am__U518$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U518$lut$lut.bit.in.1"], + ["d_2_am__U519$lut$lut.bit.in.0","d_2_am__U518$lut$lut.bit.out"], + ["d_2_am__U519$lut$lut.bit.in.2","d_2_am__U519$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U519$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U519$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U520$lut$lut.bit.in.2","d_3_am__U520$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U520$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U520$lut$lut.bit.in.1"], + ["d_3_am__U521$lut$lut.bit.in.0","d_3_am__U520$lut$lut.bit.out"], + ["d_3_am__U521$lut$lut.bit.in.2","d_3_am__U521$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U521$lut$lut.bit.in.1"], + ["d_3_am__U522$lut$lut.bit.in.0","d_3_am__U521$lut$lut.bit.out"], + ["d_3_am__U522$lut$lut.bit.in.2","d_3_am__U522$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U522$lut$lut.bit.in.1"], + ["d_3_am__U523$lut$lut.bit.in.0","d_3_am__U522$lut$lut.bit.out"], + ["d_3_am__U523$lut$lut.bit.in.2","d_3_am__U523$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U523$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U523$lut$lut.bit.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U524$lut$lut.bit.in.2","d_4_am__U524$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U524$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U524$lut$lut.bit.in.1"], + ["d_4_am__U525$lut$lut.bit.in.0","d_4_am__U524$lut$lut.bit.out"], + ["d_4_am__U525$lut$lut.bit.in.2","d_4_am__U525$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U525$lut$lut.bit.in.1"], + ["d_4_am__U526$lut$lut.bit.in.0","d_4_am__U525$lut$lut.bit.out"], + ["d_4_am__U526$lut$lut.bit.in.2","d_4_am__U526$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U526$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U526$lut$lut.bit.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U527$lut$lut.bit.in.2","d_5_am__U527$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U527$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U527$lut$lut.bit.in.1"], + ["d_5_am__U528$lut$lut.bit.in.0","d_5_am__U527$lut$lut.bit.out"], + ["d_5_am__U528$lut$lut.bit.in.2","d_5_am__U528$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U528$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U528$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_am__U529$lut$lut.bit.in.2","d_6_am__U529$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U529$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U529$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U529$lut$lut.bit.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"], + ["d_7_reg$reg0.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg$reg0.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg$reg0.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg$enMux.in1","d_7_next_value.out"], + ["true_lutcnst.bit.out","d_7_next_value.sel"], + ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], + ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], + ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], + ["self.rst_n","d_7_reg$clrMux.sel"], + ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], + ["self.clk","d_7_reg$reg0.clk"], + ["self.d.7","d_7_reg$reg0.out"] + ] + }, + "affine_controller__U558":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",4,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U573":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "_U5731":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "_U5732":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_max":{ + "_U5733":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_min":{ + "_U574":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ - "genref":"coreir.mux", + "affine_func$add_all__U569":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", + "affine_func$add_all__U570":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_reg$c0":{ + "affine_func$add_all__U571":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U572":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U560":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func$coeff_1_U562":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000700"]} }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func$coeff_2_U564":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", + "affine_func$coeff_3_U566":{ + "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_3_am__U103$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$const_term_U568":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} }, - "d_3_am__U103$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "affine_func$mul_d0__U561":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U104$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$mul_d1__U563":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U104$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "affine_func$mul_d2__U565":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U105$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$mul_d3__U567":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U105$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "d_3_am__U106$c0_lutcnst":{ + "cycle_time$and$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U106$lut$lut":{ + "cycle_time$and$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_3_min":{ + "cycle_time$count$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "cycle_time$count$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "cycle_time$count$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$c0":{ + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} }, - "d_4_am__U107$c0_lutcnst":{ + "d_0_am__U575$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U107$lut$lut":{ + "d_0_am__U575$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U108$c0_lutcnst":{ + "d_0_am__U576$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U108$lut$lut":{ + "d_0_am__U576$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U109$c0_lutcnst":{ + "d_0_am__U577$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U109$lut$lut":{ + "d_0_am__U577$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U110$c0_lutcnst":{ + "d_1_am__U578$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U110$lut$lut":{ + "d_1_am__U578$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_5_am__U111$c0_lutcnst":{ + "d_1_am__U579$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U111$lut$lut":{ + "d_1_am__U579$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_5_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + "modargs":{"value":[["BitVector",32],"32'h0000001b"]} }, - "d_5_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U112$c0_lutcnst":{ + "d_2_am__U580$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U112$lut$lut":{ + "d_2_am__U580$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_6_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_6_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_6_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + "modargs":{"value":[["BitVector",32],"32'h0000001b"]} }, - "d_6_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_7_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_7_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_7_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, - "d_7_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -9664,26 +9842,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9691,57 +9849,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U83.out"], - ["d_1_inc.in1","_U831.out"], - ["d_2_inc.in1","_U832.out"], - ["d_3_inc.in1","_U833.out"], - ["d_4_inc.in1","_U834.out"], - ["d_5_inc.in1","_U835.out"], - ["d_6_inc.in1","_U836.out"], - ["d_7_inc.in1","_U837.out"], - ["cmp_time.in1","_U84.out"], - ["affine_func$mul_d0__U59.out","affine_func$add_all__U75.in0"], - ["affine_func$mul_d1__U61.out","affine_func$add_all__U75.in1"], - ["affine_func$add_all__U76.in0","affine_func$add_all__U75.out"], - ["affine_func$mul_d2__U63.out","affine_func$add_all__U76.in1"], - ["affine_func$add_all__U77.in0","affine_func$add_all__U76.out"], - ["affine_func$mul_d3__U65.out","affine_func$add_all__U77.in1"], - ["affine_func$add_all__U78.in0","affine_func$add_all__U77.out"], - ["affine_func$mul_d4__U67.out","affine_func$add_all__U78.in1"], - ["affine_func$add_all__U79.in0","affine_func$add_all__U78.out"], - ["affine_func$mul_d5__U69.out","affine_func$add_all__U79.in1"], - ["affine_func$add_all__U80.in0","affine_func$add_all__U79.out"], - ["affine_func$mul_d6__U71.out","affine_func$add_all__U80.in1"], - ["affine_func$add_all__U81.in0","affine_func$add_all__U80.out"], - ["affine_func$mul_d7__U73.out","affine_func$add_all__U81.in1"], - ["affine_func$add_all__U82.in0","affine_func$add_all__U81.out"], - ["affine_func$const_term_U74.out","affine_func$add_all__U82.in1"], - ["time_diff.in0","affine_func$add_all__U82.out"], - ["affine_func$mul_d0__U59.in0","affine_func$coeff_0_U58.out"], - ["affine_func$mul_d1__U61.in0","affine_func$coeff_1_U60.out"], - ["affine_func$mul_d2__U63.in0","affine_func$coeff_2_U62.out"], - ["affine_func$mul_d3__U65.in0","affine_func$coeff_3_U64.out"], - ["affine_func$mul_d4__U67.in0","affine_func$coeff_4_U66.out"], - ["affine_func$mul_d5__U69.in0","affine_func$coeff_5_U68.out"], - ["affine_func$mul_d6__U71.in0","affine_func$coeff_6_U70.out"], - ["affine_func$mul_d7__U73.in0","affine_func$coeff_7_U72.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U59.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U61.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U63.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U65.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U67.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U69.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U71.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U73.in1"], + ["d_0_inc.in1","_U573.out"], + ["d_1_inc.in1","_U5731.out"], + ["d_2_inc.in1","_U5732.out"], + ["d_3_inc.in1","_U5733.out"], + ["cmp_time.in1","_U574.out"], + ["affine_func$mul_d0__U561.out","affine_func$add_all__U569.in0"], + ["affine_func$mul_d1__U563.out","affine_func$add_all__U569.in1"], + ["affine_func$add_all__U570.in0","affine_func$add_all__U569.out"], + ["affine_func$mul_d2__U565.out","affine_func$add_all__U570.in1"], + ["affine_func$add_all__U571.in0","affine_func$add_all__U570.out"], + ["affine_func$mul_d3__U567.out","affine_func$add_all__U571.in1"], + ["affine_func$add_all__U572.in0","affine_func$add_all__U571.out"], + ["affine_func$const_term_U568.out","affine_func$add_all__U572.in1"], + ["time_diff.in0","affine_func$add_all__U572.out"], + ["affine_func$mul_d0__U561.in0","affine_func$coeff_0_U560.out"], + ["affine_func$mul_d1__U563.in0","affine_func$coeff_1_U562.out"], + ["affine_func$mul_d2__U565.in0","affine_func$coeff_2_U564.out"], + ["affine_func$mul_d3__U567.in0","affine_func$coeff_3_U566.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U561.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U563.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U565.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U567.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], - ["d_7_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -9749,40 +9883,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U85$lut$lut.bit.in.2","d_0_am__U85$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U85$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U85$lut$lut.bit.in.1"], - ["d_0_am__U86$lut$lut.bit.in.0","d_0_am__U85$lut$lut.bit.out"], - ["d_0_am__U86$lut$lut.bit.in.2","d_0_am__U86$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U86$lut$lut.bit.in.1"], - ["d_0_am__U87$lut$lut.bit.in.0","d_0_am__U86$lut$lut.bit.out"], - ["d_0_am__U87$lut$lut.bit.in.2","d_0_am__U87$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U87$lut$lut.bit.in.1"], - ["d_0_am__U88$lut$lut.bit.in.0","d_0_am__U87$lut$lut.bit.out"], - ["d_0_am__U88$lut$lut.bit.in.2","d_0_am__U88$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U88$lut$lut.bit.in.1"], - ["d_0_am__U89$lut$lut.bit.in.0","d_0_am__U88$lut$lut.bit.out"], - ["d_0_am__U89$lut$lut.bit.in.2","d_0_am__U89$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U89$lut$lut.bit.in.1"], - ["d_0_am__U90$lut$lut.bit.in.0","d_0_am__U89$lut$lut.bit.out"], - ["d_0_am__U90$lut$lut.bit.in.2","d_0_am__U90$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U90$lut$lut.bit.in.1"], - ["d_0_am__U91$lut$lut.bit.in.0","d_0_am__U90$lut$lut.bit.out"], - ["d_0_am__U91$lut$lut.bit.in.2","d_0_am__U91$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U91$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U91$lut$lut.bit.out"], + ["d_0_am__U575$lut$lut.bit.in.2","d_0_am__U575$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U575$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U575$lut$lut.bit.in.1"], + ["d_0_am__U576$lut$lut.bit.in.0","d_0_am__U575$lut$lut.bit.out"], + ["d_0_am__U576$lut$lut.bit.in.2","d_0_am__U576$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U576$lut$lut.bit.in.1"], + ["d_0_am__U577$lut$lut.bit.in.0","d_0_am__U576$lut$lut.bit.out"], + ["d_0_am__U577$lut$lut.bit.in.2","d_0_am__U577$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U577$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U577$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9799,25 +9921,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U92$lut$lut.bit.in.2","d_1_am__U92$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U92$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U92$lut$lut.bit.in.1"], - ["d_1_am__U93$lut$lut.bit.in.0","d_1_am__U92$lut$lut.bit.out"], - ["d_1_am__U93$lut$lut.bit.in.2","d_1_am__U93$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U93$lut$lut.bit.in.1"], - ["d_1_am__U94$lut$lut.bit.in.0","d_1_am__U93$lut$lut.bit.out"], - ["d_1_am__U94$lut$lut.bit.in.2","d_1_am__U94$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U94$lut$lut.bit.in.1"], - ["d_1_am__U95$lut$lut.bit.in.0","d_1_am__U94$lut$lut.bit.out"], - ["d_1_am__U95$lut$lut.bit.in.2","d_1_am__U95$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U95$lut$lut.bit.in.1"], - ["d_1_am__U96$lut$lut.bit.in.0","d_1_am__U95$lut$lut.bit.out"], - ["d_1_am__U96$lut$lut.bit.in.2","d_1_am__U96$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U96$lut$lut.bit.in.1"], - ["d_1_am__U97$lut$lut.bit.in.0","d_1_am__U96$lut$lut.bit.out"], - ["d_1_am__U97$lut$lut.bit.in.2","d_1_am__U97$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U97$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U97$lut$lut.bit.out"], + ["d_1_am__U578$lut$lut.bit.in.2","d_1_am__U578$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U578$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U578$lut$lut.bit.in.1"], + ["d_1_am__U579$lut$lut.bit.in.0","d_1_am__U578$lut$lut.bit.out"], + ["d_1_am__U579$lut$lut.bit.in.2","d_1_am__U579$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U579$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U579$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -9834,22 +9944,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U100$lut$lut.bit.in.2","d_2_am__U100$c0_lutcnst.bit.out"], - ["d_2_am__U99$lut$lut.bit.out","d_2_am__U100$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_2_am__U100$lut$lut.bit.in.1"], - ["d_2_am__U101$lut$lut.bit.in.0","d_2_am__U100$lut$lut.bit.out"], - ["d_2_am__U101$lut$lut.bit.in.2","d_2_am__U101$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U101$lut$lut.bit.in.1"], - ["d_2_am__U102$lut$lut.bit.in.0","d_2_am__U101$lut$lut.bit.out"], - ["d_2_am__U102$lut$lut.bit.in.2","d_2_am__U102$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U102$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U102$lut$lut.bit.out"], - ["d_2_am__U98$lut$lut.bit.in.2","d_2_am__U98$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U98$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U98$lut$lut.bit.in.1"], - ["d_2_am__U99$lut$lut.bit.in.0","d_2_am__U98$lut$lut.bit.out"], - ["d_2_am__U99$lut$lut.bit.in.2","d_2_am__U99$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U99$lut$lut.bit.in.1"], + ["d_2_am__U580$lut$lut.bit.in.2","d_2_am__U580$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U580$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U580$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U580$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -9866,19 +9964,6 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U103$lut$lut.bit.in.2","d_3_am__U103$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U103$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U103$lut$lut.bit.in.1"], - ["d_3_am__U104$lut$lut.bit.in.0","d_3_am__U103$lut$lut.bit.out"], - ["d_3_am__U104$lut$lut.bit.in.2","d_3_am__U104$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U104$lut$lut.bit.in.1"], - ["d_3_am__U105$lut$lut.bit.in.0","d_3_am__U104$lut$lut.bit.out"], - ["d_3_am__U105$lut$lut.bit.in.2","d_3_am__U105$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U105$lut$lut.bit.in.1"], - ["d_3_am__U106$lut$lut.bit.in.0","d_3_am__U105$lut$lut.bit.out"], - ["d_3_am__U106$lut$lut.bit.in.2","d_3_am__U106$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U106$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U106$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -9888,102 +9973,17 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U107$lut$lut.bit.in.2","d_4_am__U107$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U107$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U107$lut$lut.bit.in.1"], - ["d_4_am__U108$lut$lut.bit.in.0","d_4_am__U107$lut$lut.bit.out"], - ["d_4_am__U108$lut$lut.bit.in.2","d_4_am__U108$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U108$lut$lut.bit.in.1"], - ["d_4_am__U109$lut$lut.bit.in.0","d_4_am__U108$lut$lut.bit.out"], - ["d_4_am__U109$lut$lut.bit.in.2","d_4_am__U109$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U109$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U109$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U110$lut$lut.bit.in.2","d_5_am__U110$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U110$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U110$lut$lut.bit.in.1"], - ["d_5_am__U111$lut$lut.bit.in.0","d_5_am__U110$lut$lut.bit.out"], - ["d_5_am__U111$lut$lut.bit.in.2","d_5_am__U111$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U111$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U111$lut$lut.bit.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U112$lut$lut.bit.in.2","d_6_am__U112$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U112$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U112$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U112$lut$lut.bit.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"], - ["d_7_reg$reg0.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg$reg0.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg$reg0.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg$enMux.in1","d_7_next_value.out"], - ["true_lutcnst.bit.out","d_7_next_value.sel"], - ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], - ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], - ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], - ["self.rst_n","d_7_reg$clrMux.sel"], - ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], - ["self.clk","d_7_reg$reg0.clk"], - ["self.d.7","d_7_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U641":{ + "affine_controller__U598":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -9991,85 +9991,85 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U656":{ + "_U613":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6561":{ + "_U6131":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6562":{ + "_U6132":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6563":{ + "_U6133":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U657":{ + "_U614":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U652":{ + "affine_func$add_all__U609":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U653":{ + "affine_func$add_all__U610":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U654":{ + "affine_func$add_all__U611":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U655":{ + "affine_func$add_all__U612":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U643":{ + "affine_func$coeff_0_U600":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U645":{ + "affine_func$coeff_1_U602":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000700"]} }, - "affine_func$coeff_2_U647":{ + "affine_func$coeff_2_U604":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "affine_func$coeff_3_U649":{ + "affine_func$coeff_3_U606":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U651":{ + "affine_func$const_term_U608":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} + "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} }, - "affine_func$mul_d0__U644":{ + "affine_func$mul_d0__U601":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U646":{ + "affine_func$mul_d1__U603":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U648":{ + "affine_func$mul_d2__U605":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U650":{ + "affine_func$mul_d3__U607":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -10133,32 +10133,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U658$c0_lutcnst":{ + "d_0_am__U615$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U658$lut$lut":{ + "d_0_am__U615$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U659$c0_lutcnst":{ + "d_0_am__U616$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U659$lut$lut":{ + "d_0_am__U616$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U660$c0_lutcnst":{ + "d_0_am__U617$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U660$lut$lut":{ + "d_0_am__U617$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10207,22 +10207,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U661$c0_lutcnst":{ + "d_1_am__U618$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U661$lut$lut":{ + "d_1_am__U618$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U662$c0_lutcnst":{ + "d_1_am__U619$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U662$lut$lut":{ + "d_1_am__U619$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10271,12 +10271,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U663$c0_lutcnst":{ + "d_2_am__U620$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U663$lut$lut":{ + "d_2_am__U620$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10405,28 +10405,28 @@ } }, "connections":[ - ["d_0_inc.in1","_U656.out"], - ["d_1_inc.in1","_U6561.out"], - ["d_2_inc.in1","_U6562.out"], - ["d_3_inc.in1","_U6563.out"], - ["cmp_time.in1","_U657.out"], - ["affine_func$mul_d0__U644.out","affine_func$add_all__U652.in0"], - ["affine_func$mul_d1__U646.out","affine_func$add_all__U652.in1"], - ["affine_func$add_all__U653.in0","affine_func$add_all__U652.out"], - ["affine_func$mul_d2__U648.out","affine_func$add_all__U653.in1"], - ["affine_func$add_all__U654.in0","affine_func$add_all__U653.out"], - ["affine_func$mul_d3__U650.out","affine_func$add_all__U654.in1"], - ["affine_func$add_all__U655.in0","affine_func$add_all__U654.out"], - ["affine_func$const_term_U651.out","affine_func$add_all__U655.in1"], - ["time_diff.in0","affine_func$add_all__U655.out"], - ["affine_func$mul_d0__U644.in0","affine_func$coeff_0_U643.out"], - ["affine_func$mul_d1__U646.in0","affine_func$coeff_1_U645.out"], - ["affine_func$mul_d2__U648.in0","affine_func$coeff_2_U647.out"], - ["affine_func$mul_d3__U650.in0","affine_func$coeff_3_U649.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U644.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U646.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U648.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U650.in1"], + ["d_0_inc.in1","_U613.out"], + ["d_1_inc.in1","_U6131.out"], + ["d_2_inc.in1","_U6132.out"], + ["d_3_inc.in1","_U6133.out"], + ["cmp_time.in1","_U614.out"], + ["affine_func$mul_d0__U601.out","affine_func$add_all__U609.in0"], + ["affine_func$mul_d1__U603.out","affine_func$add_all__U609.in1"], + ["affine_func$add_all__U610.in0","affine_func$add_all__U609.out"], + ["affine_func$mul_d2__U605.out","affine_func$add_all__U610.in1"], + ["affine_func$add_all__U611.in0","affine_func$add_all__U610.out"], + ["affine_func$mul_d3__U607.out","affine_func$add_all__U611.in1"], + ["affine_func$add_all__U612.in0","affine_func$add_all__U611.out"], + ["affine_func$const_term_U608.out","affine_func$add_all__U612.in1"], + ["time_diff.in0","affine_func$add_all__U612.out"], + ["affine_func$mul_d0__U601.in0","affine_func$coeff_0_U600.out"], + ["affine_func$mul_d1__U603.in0","affine_func$coeff_1_U602.out"], + ["affine_func$mul_d2__U605.in0","affine_func$coeff_2_U604.out"], + ["affine_func$mul_d3__U607.in0","affine_func$coeff_3_U606.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U601.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U603.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U605.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U607.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -10451,16 +10451,16 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U658$lut$lut.bit.in.2","d_0_am__U658$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U658$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U658$lut$lut.bit.in.1"], - ["d_0_am__U659$lut$lut.bit.in.0","d_0_am__U658$lut$lut.bit.out"], - ["d_0_am__U659$lut$lut.bit.in.2","d_0_am__U659$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U659$lut$lut.bit.in.1"], - ["d_0_am__U660$lut$lut.bit.in.0","d_0_am__U659$lut$lut.bit.out"], - ["d_0_am__U660$lut$lut.bit.in.2","d_0_am__U660$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U660$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U660$lut$lut.bit.out"], + ["d_0_am__U615$lut$lut.bit.in.2","d_0_am__U615$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U615$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U615$lut$lut.bit.in.1"], + ["d_0_am__U616$lut$lut.bit.in.0","d_0_am__U615$lut$lut.bit.out"], + ["d_0_am__U616$lut$lut.bit.in.2","d_0_am__U616$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U616$lut$lut.bit.in.1"], + ["d_0_am__U617$lut$lut.bit.in.0","d_0_am__U616$lut$lut.bit.out"], + ["d_0_am__U617$lut$lut.bit.in.2","d_0_am__U617$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U617$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U617$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10477,13 +10477,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U661$lut$lut.bit.in.2","d_1_am__U661$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U661$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U661$lut$lut.bit.in.1"], - ["d_1_am__U662$lut$lut.bit.in.0","d_1_am__U661$lut$lut.bit.out"], - ["d_1_am__U662$lut$lut.bit.in.2","d_1_am__U662$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U662$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U662$lut$lut.bit.out"], + ["d_1_am__U618$lut$lut.bit.in.2","d_1_am__U618$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U618$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U618$lut$lut.bit.in.1"], + ["d_1_am__U619$lut$lut.bit.in.0","d_1_am__U618$lut$lut.bit.out"], + ["d_1_am__U619$lut$lut.bit.in.2","d_1_am__U619$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U619$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U619$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10500,10 +10500,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U663$lut$lut.bit.in.2","d_2_am__U663$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U663$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U663$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U663$lut$lut.bit.out"], + ["d_2_am__U620$lut$lut.bit.in.2","d_2_am__U620$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U620$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U620$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U620$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -10539,7 +10539,7 @@ ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U681":{ + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -10547,85 +10547,85 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U696":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6961":{ + "_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6962":{ + "_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6963":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U697":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U692":{ + "affine_func$add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U693":{ + "affine_func$add_all__U20":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U694":{ + "affine_func$add_all__U21":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U695":{ + "affine_func$add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U683":{ + "affine_func$coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U685":{ + "affine_func$coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000700"]} + "modargs":{"value":[["BitVector",32],"32'h000003a0"]} }, - "affine_func$coeff_2_U687":{ + "affine_func$coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U689":{ + "affine_func$coeff_3_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U691":{ + "affine_func$const_term_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U684":{ + "affine_func$mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U686":{ + "affine_func$mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U688":{ + "affine_func$mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U690":{ + "affine_func$mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -10689,32 +10689,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U698$c0_lutcnst":{ + "d_0_am__U25$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U698$lut$lut":{ + "d_0_am__U25$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U699$c0_lutcnst":{ + "d_0_am__U26$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U699$lut$lut":{ + "d_0_am__U26$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U700$c0_lutcnst":{ + "d_0_am__U27$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U700$lut$lut":{ + "d_0_am__U27$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10763,22 +10763,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U701$c0_lutcnst":{ + "d_1_am__U28$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U701$lut$lut":{ + "d_1_am__U28$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U702$c0_lutcnst":{ + "d_1_am__U29$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U702$lut$lut":{ + "d_1_am__U29$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10794,7 +10794,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001b"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_1_min":{ "genref":"coreir.const", @@ -10827,12 +10827,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U703$c0_lutcnst":{ + "d_2_am__U30$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U703$lut$lut":{ + "d_2_am__U30$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10848,7 +10848,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001b"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_2_min":{ "genref":"coreir.const", @@ -10892,7 +10892,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -10961,28 +10961,28 @@ } }, "connections":[ - ["d_0_inc.in1","_U696.out"], - ["d_1_inc.in1","_U6961.out"], - ["d_2_inc.in1","_U6962.out"], - ["d_3_inc.in1","_U6963.out"], - ["cmp_time.in1","_U697.out"], - ["affine_func$mul_d0__U684.out","affine_func$add_all__U692.in0"], - ["affine_func$mul_d1__U686.out","affine_func$add_all__U692.in1"], - ["affine_func$add_all__U693.in0","affine_func$add_all__U692.out"], - ["affine_func$mul_d2__U688.out","affine_func$add_all__U693.in1"], - ["affine_func$add_all__U694.in0","affine_func$add_all__U693.out"], - ["affine_func$mul_d3__U690.out","affine_func$add_all__U694.in1"], - ["affine_func$add_all__U695.in0","affine_func$add_all__U694.out"], - ["affine_func$const_term_U691.out","affine_func$add_all__U695.in1"], - ["time_diff.in0","affine_func$add_all__U695.out"], - ["affine_func$mul_d0__U684.in0","affine_func$coeff_0_U683.out"], - ["affine_func$mul_d1__U686.in0","affine_func$coeff_1_U685.out"], - ["affine_func$mul_d2__U688.in0","affine_func$coeff_2_U687.out"], - ["affine_func$mul_d3__U690.in0","affine_func$coeff_3_U689.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U684.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U686.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U688.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U690.in1"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U231.out"], + ["d_2_inc.in1","_U232.out"], + ["d_3_inc.in1","_U233.out"], + ["cmp_time.in1","_U24.out"], + ["affine_func$mul_d0__U11.out","affine_func$add_all__U19.in0"], + ["affine_func$mul_d1__U13.out","affine_func$add_all__U19.in1"], + ["affine_func$add_all__U20.in0","affine_func$add_all__U19.out"], + ["affine_func$mul_d2__U15.out","affine_func$add_all__U20.in1"], + ["affine_func$add_all__U21.in0","affine_func$add_all__U20.out"], + ["affine_func$mul_d3__U17.out","affine_func$add_all__U21.in1"], + ["affine_func$add_all__U22.in0","affine_func$add_all__U21.out"], + ["affine_func$const_term_U18.out","affine_func$add_all__U22.in1"], + ["time_diff.in0","affine_func$add_all__U22.out"], + ["affine_func$mul_d0__U11.in0","affine_func$coeff_0_U10.out"], + ["affine_func$mul_d1__U13.in0","affine_func$coeff_1_U12.out"], + ["affine_func$mul_d2__U15.in0","affine_func$coeff_2_U14.out"], + ["affine_func$mul_d3__U17.in0","affine_func$coeff_3_U16.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U11.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U13.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U15.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U17.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -11007,16 +11007,16 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U698$lut$lut.bit.in.2","d_0_am__U698$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U698$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U698$lut$lut.bit.in.1"], - ["d_0_am__U699$lut$lut.bit.in.0","d_0_am__U698$lut$lut.bit.out"], - ["d_0_am__U699$lut$lut.bit.in.2","d_0_am__U699$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U699$lut$lut.bit.in.1"], - ["d_0_am__U700$lut$lut.bit.in.0","d_0_am__U699$lut$lut.bit.out"], - ["d_0_am__U700$lut$lut.bit.in.2","d_0_am__U700$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U700$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U700$lut$lut.bit.out"], + ["d_0_am__U25$lut$lut.bit.in.2","d_0_am__U25$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U25$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U25$lut$lut.bit.in.1"], + ["d_0_am__U26$lut$lut.bit.in.0","d_0_am__U25$lut$lut.bit.out"], + ["d_0_am__U26$lut$lut.bit.in.2","d_0_am__U26$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U26$lut$lut.bit.in.1"], + ["d_0_am__U27$lut$lut.bit.in.0","d_0_am__U26$lut$lut.bit.out"], + ["d_0_am__U27$lut$lut.bit.in.2","d_0_am__U27$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U27$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U27$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11033,13 +11033,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U701$lut$lut.bit.in.2","d_1_am__U701$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U701$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U701$lut$lut.bit.in.1"], - ["d_1_am__U702$lut$lut.bit.in.0","d_1_am__U701$lut$lut.bit.out"], - ["d_1_am__U702$lut$lut.bit.in.2","d_1_am__U702$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U702$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U702$lut$lut.bit.out"], + ["d_1_am__U28$lut$lut.bit.in.2","d_1_am__U28$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U28$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U28$lut$lut.bit.in.1"], + ["d_1_am__U29$lut$lut.bit.in.0","d_1_am__U28$lut$lut.bit.out"], + ["d_1_am__U29$lut$lut.bit.in.2","d_1_am__U29$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U29$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U29$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -11056,10 +11056,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U703$lut$lut.bit.in.2","d_2_am__U703$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U703$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U703$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U703$lut$lut.bit.out"], + ["d_2_am__U30$lut$lut.bit.in.2","d_2_am__U30$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U30$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U30$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U30$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -11168,26 +11168,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U723":{ + "PE_init_U640":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U721":{ + "_U638":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U722":{ + "_U639":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U721.out","PE_init_U723.data.in.0"], - ["_U722.out","PE_init_U723.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U723.data.out"], + ["_U638.out","PE_init_U640.data.in.0"], + ["_U639.out","PE_init_U640.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U640.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11199,26 +11199,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U726":{ + "PE_init_U643":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U724":{ + "_U641":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U725":{ + "_U642":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U724.out","PE_init_U726.data.in.0"], - ["_U725.out","PE_init_U726.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U726.data.out"], + ["_U641.out","PE_init_U643.data.in.0"], + ["_U642.out","PE_init_U643.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U643.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12004,26 +12004,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U729":{ + "PE_init_U646":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U727":{ + "_U644":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U728":{ + "_U645":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U727.out","PE_init_U729.data.in.0"], - ["_U728.out","PE_init_U729.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U729.data.out"], + ["_U644.out","PE_init_U646.data.in.0"], + ["_U645.out","PE_init_U646.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U646.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12035,26 +12035,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U732":{ + "PE_init_U649":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U730":{ + "_U647":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U731":{ + "_U648":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U730.out","PE_init_U732.data.in.0"], - ["_U731.out","PE_init_U732.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U732.data.out"], + ["_U647.out","PE_init_U649.data.in.0"], + ["_U648.out","PE_init_U649.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U649.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12066,26 +12066,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U735":{ + "PE_init_U652":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U733":{ + "_U650":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U734":{ + "_U651":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U733.out","PE_init_U735.data.in.0"], - ["_U734.out","PE_init_U735.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U735.data.out"], + ["_U650.out","PE_init_U652.data.in.0"], + ["_U651.out","PE_init_U652.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U652.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12097,26 +12097,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U738":{ + "PE_init_U655":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U736":{ + "_U653":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U737":{ + "_U654":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U736.out","PE_init_U738.data.in.0"], - ["_U737.out","PE_init_U738.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U738.data.out"], + ["_U653.out","PE_init_U655.data.in.0"], + ["_U654.out","PE_init_U655.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U655.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12128,26 +12128,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U741":{ + "PE_init_U658":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U739":{ + "_U656":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U740":{ + "_U657":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U739.out","PE_init_U741.data.in.0"], - ["_U740.out","PE_init_U741.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U741.data.out"], + ["_U656.out","PE_init_U658.data.in.0"], + ["_U657.out","PE_init_U658.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U658.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12159,26 +12159,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U744":{ + "PE_init_U661":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U742":{ + "_U659":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U743":{ + "_U660":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U742.out","PE_init_U744.data.in.0"], - ["_U743.out","PE_init_U744.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U744.data.out"], + ["_U659.out","PE_init_U661.data.in.0"], + ["_U660.out","PE_init_U661.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U661.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12503,26 +12503,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U747":{ + "PE_init_U664":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U745":{ + "_U662":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U746":{ + "_U663":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U745.out","PE_init_U747.data.in.0"], - ["_U746.out","PE_init_U747.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U747.data.out"] + ["_U662.out","PE_init_U664.data.in.0"], + ["_U663.out","PE_init_U664.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U664.data.out"] ] }, "hcompute_output_cgra_stencil_1":{ @@ -12530,26 +12530,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U750":{ + "PE_init_U667":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U748":{ + "_U665":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U749":{ + "_U666":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U748.out","PE_init_U750.data.in.0"], - ["_U749.out","PE_init_U750.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U750.data.out"] + ["_U665.out","PE_init_U667.data.in.0"], + ["_U666.out","PE_init_U667.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U667.data.out"] ] }, "hcompute_output_cgra_stencil_10":{ @@ -13307,26 +13307,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U753":{ + "PE_init_U670":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U751":{ + "_U668":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U752":{ + "_U669":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U751.out","PE_init_U753.data.in.0"], - ["_U752.out","PE_init_U753.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U753.data.out"] + ["_U668.out","PE_init_U670.data.in.0"], + ["_U669.out","PE_init_U670.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U670.data.out"] ] }, "hcompute_output_cgra_stencil_3":{ @@ -13334,26 +13334,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U756":{ + "PE_init_U673":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U754":{ + "_U671":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U755":{ + "_U672":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U754.out","PE_init_U756.data.in.0"], - ["_U755.out","PE_init_U756.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U756.data.out"] + ["_U671.out","PE_init_U673.data.in.0"], + ["_U672.out","PE_init_U673.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U673.data.out"] ] }, "hcompute_output_cgra_stencil_4":{ @@ -13361,26 +13361,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U759":{ + "PE_init_U676":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U757":{ + "_U674":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U758":{ + "_U675":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U757.out","PE_init_U759.data.in.0"], - ["_U758.out","PE_init_U759.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U759.data.out"] + ["_U674.out","PE_init_U676.data.in.0"], + ["_U675.out","PE_init_U676.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U676.data.out"] ] }, "hcompute_output_cgra_stencil_5":{ @@ -13388,26 +13388,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U762":{ + "PE_init_U679":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U760":{ + "_U677":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U761":{ + "_U678":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U760.out","PE_init_U762.data.in.0"], - ["_U761.out","PE_init_U762.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U762.data.out"] + ["_U677.out","PE_init_U679.data.in.0"], + ["_U678.out","PE_init_U679.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U679.data.out"] ] }, "hcompute_output_cgra_stencil_6":{ @@ -13415,26 +13415,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U765":{ + "PE_init_U682":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U763":{ + "_U680":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U764":{ + "_U681":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U763.out","PE_init_U765.data.in.0"], - ["_U764.out","PE_init_U765.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U765.data.out"] + ["_U680.out","PE_init_U682.data.in.0"], + ["_U681.out","PE_init_U682.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U682.data.out"] ] }, "hcompute_output_cgra_stencil_7":{ @@ -13442,26 +13442,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U768":{ + "PE_init_U685":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U766":{ + "_U683":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U767":{ + "_U684":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U766.out","PE_init_U768.data.in.0"], - ["_U767.out","PE_init_U768.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U768.data.out"] + ["_U683.out","PE_init_U685.data.in.0"], + ["_U684.out","PE_init_U685.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U685.data.out"] ] }, "hcompute_output_cgra_stencil_8":{ @@ -13748,38 +13748,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -13787,7 +13755,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -13797,7 +13765,7 @@ }, "ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7201],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -13807,7 +13775,7 @@ }, "ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -13817,7 +13785,7 @@ }, "ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -13827,7 +13795,7 @@ }, "ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -13837,7 +13805,7 @@ }, "ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -13847,7 +13815,7 @@ }, "ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -13857,7 +13825,7 @@ }, "ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -13999,262 +13967,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -14262,7 +13974,7 @@ }, "ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -14272,7 +13984,7 @@ }, "ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -14282,7 +13994,7 @@ }, "ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -14292,7 +14004,7 @@ }, "ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -14302,7 +14014,7 @@ }, "ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -14312,7 +14024,7 @@ }, "ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -14322,7 +14034,7 @@ }, "ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -14332,7 +14044,7 @@ }, "ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -14342,7 +14054,7 @@ }, "ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -14352,7 +14064,7 @@ }, "ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -14362,7 +14074,7 @@ }, "ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -14372,7 +14084,7 @@ }, "ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -14382,7 +14094,7 @@ }, "ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -14392,7 +14104,7 @@ }, "ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -14402,7 +14114,7 @@ }, "ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -14412,7 +14124,7 @@ }, "ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -14422,7 +14134,7 @@ }, "ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -14432,7 +14144,7 @@ }, "ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -14442,7 +14154,7 @@ }, "ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -14452,7 +14164,7 @@ }, "ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -14462,7 +14174,7 @@ }, "ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -14472,7 +14184,7 @@ }, "ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -14482,7 +14194,7 @@ }, "ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -14492,7 +14204,7 @@ }, "ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -14502,7 +14214,7 @@ }, "ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -14512,7 +14224,7 @@ }, "ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -14522,7 +14234,7 @@ }, "ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -14532,7 +14244,7 @@ }, "ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -14542,7 +14254,7 @@ }, "ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -14552,7 +14264,7 @@ }, "ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -14562,7 +14274,7 @@ }, "ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -14572,7 +14284,7 @@ }, "ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -14582,7 +14294,7 @@ }, "ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -14592,7 +14304,7 @@ }, "ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -14602,7 +14314,7 @@ }, "ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -14612,7 +14324,7 @@ }, "ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -14622,7 +14334,7 @@ }, "ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -14632,7 +14344,7 @@ }, "ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -14642,7 +14354,7 @@ }, "ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -14652,7 +14364,7 @@ }, "ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -14662,7 +14374,7 @@ }, "ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -14672,7 +14384,7 @@ }, "ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -14682,7 +14394,7 @@ }, "ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -14692,7 +14404,7 @@ }, "ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -14702,7 +14414,7 @@ }, "ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -14712,7 +14424,7 @@ }, "ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -14722,7 +14434,7 @@ }, "ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -14732,7 +14444,7 @@ }, "ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -14742,7 +14454,7 @@ }, "ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -14752,7 +14464,7 @@ }, "ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -14762,7 +14474,7 @@ }, "ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -14772,7 +14484,7 @@ }, "ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -14782,7 +14494,7 @@ }, "ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -14792,7 +14504,7 @@ }, "ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -14802,7 +14514,7 @@ }, "ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -14812,7 +14524,7 @@ }, "ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -14822,7 +14534,7 @@ }, "ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -14832,7 +14544,7 @@ }, "ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -14842,7 +14554,7 @@ }, "ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -14852,7 +14564,7 @@ }, "ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -14862,7 +14574,7 @@ }, "ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -14872,7 +14584,7 @@ }, "ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -14882,7 +14594,7 @@ }, "ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -14892,7 +14604,7 @@ }, "ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -15233,7 +14945,7 @@ ["self.op_hcompute_kernel_glb_stencil_write.0","self.op_hcompute_kernel_cgra_stencil_read.0"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U707":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U624":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -15242,7 +14954,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U706":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U623":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15251,7 +14963,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U705":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U622":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -15260,7 +14972,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U704":{ + "op_hcompute_hw_output_stencil_read_start_pt__U621":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15269,7 +14981,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U709":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U626":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -15278,7 +14990,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U708":{ + "op_hcompute_hw_output_stencil_write_start_pt__U625":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15287,7 +14999,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U717":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U634":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15296,7 +15008,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U716":{ + "op_hcompute_input_glb_stencil_read_start_pt__U633":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15305,7 +15017,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U718":{ + "op_hcompute_input_glb_stencil_write_start_pt__U635":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15314,7 +15026,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U712":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U629":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15323,7 +15035,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U711":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U628":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15332,7 +15044,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U713":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U630":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -15398,38 +15110,6 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U449":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U464":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U479":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U494":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U509":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U524":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U539":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U554":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -15437,7 +15117,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U435"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U361"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23325],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -15447,7 +15127,7 @@ }, "ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U450"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U375"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[7213],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -15457,7 +15137,7 @@ }, "ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U465"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -15467,7 +15147,7 @@ }, "ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U480"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U403"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -15477,7 +15157,7 @@ }, "ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U495"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U417"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -15487,7 +15167,7 @@ }, "ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U510"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U431"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -15497,7 +15177,7 @@ }, "ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U525"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U445"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -15507,7 +15187,7 @@ }, "ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U540"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U459"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -15596,158 +15276,126 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U771":{ + "PE_init_U688":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U774":{ + "PE_init_U691":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U777":{ + "PE_init_U694":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U780":{ + "PE_init_U697":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U783":{ + "PE_init_U700":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U786":{ + "PE_init_U703":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U789":{ + "PE_init_U706":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U792":{ + "PE_init_U709":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U769":{ + "_U686":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U770":{ + "_U687":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U772":{ + "_U689":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U773":{ + "_U690":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U775":{ + "_U692":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U776":{ + "_U693":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U778":{ + "_U695":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U779":{ + "_U696":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U781":{ + "_U698":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U782":{ + "_U699":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U784":{ + "_U701":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U785":{ + "_U702":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U787":{ + "_U704":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U788":{ + "_U705":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U790":{ + "_U707":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U791":{ + "_U708":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "input_cgra_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -15755,7 +15403,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -15765,7 +15413,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7201],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -15775,7 +15423,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -15785,7 +15433,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -15795,7 +15443,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -15805,7 +15453,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -15815,7 +15463,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -15825,7 +15473,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[8,64,896,2688,8064],"dimensionality":5,"extent":[8,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,16,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -15854,262 +15502,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "kernel_cgra_stencil$chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -16117,7 +15509,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -16127,7 +15519,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -16137,7 +15529,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -16147,7 +15539,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -16157,7 +15549,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -16167,7 +15559,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -16177,7 +15569,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -16187,7 +15579,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -16197,7 +15589,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -16207,7 +15599,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -16217,7 +15609,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -16227,7 +15619,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -16237,7 +15629,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -16247,7 +15639,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -16257,7 +15649,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -16267,7 +15659,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -16277,7 +15669,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -16287,7 +15679,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -16297,7 +15689,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -16307,7 +15699,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -16317,7 +15709,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -16327,7 +15719,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -16337,7 +15729,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -16347,7 +15739,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -16357,7 +15749,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -16367,7 +15759,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -16377,7 +15769,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -16387,7 +15779,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -16397,7 +15789,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -16407,7 +15799,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -16417,7 +15809,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -16427,7 +15819,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -16437,7 +15829,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -16447,7 +15839,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -16457,7 +15849,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -16467,7 +15859,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -16477,7 +15869,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -16487,7 +15879,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -16497,7 +15889,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -16507,7 +15899,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -16517,7 +15909,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -16527,7 +15919,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -16537,7 +15929,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -16547,7 +15939,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -16557,7 +15949,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -16567,7 +15959,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -16577,7 +15969,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -16587,7 +15979,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -16597,7 +15989,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -16607,7 +15999,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -16617,7 +16009,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -16627,7 +16019,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -16637,7 +16029,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -16647,7 +16039,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -16657,7 +16049,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -16667,7 +16059,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -16677,7 +16069,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -16687,7 +16079,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -16697,7 +16089,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -16707,7 +16099,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -16717,7 +16109,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -16727,7 +16119,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -16737,7 +16129,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -16747,7 +16139,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,16],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[7205],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -16757,7 +16149,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_lake_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U720"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U637"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[23328],"cycle_stride":[1,32,448,16128,32256,64512],"dimensionality":6,"extent":[32,14,14,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,1792,32,896,25088]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_output_cgra_stencil_10$inner_compute$add_953_967_968$binop":{ @@ -17400,38 +16792,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "output_cgra_stencil$chain_en_const_U449":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U464":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U479":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U494":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U509":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U524":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U539":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U554":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -17439,7 +16799,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U435"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U361"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23325],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -17449,7 +16809,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U450"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U375"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[7213],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -17459,7 +16819,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U465"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -17469,7 +16829,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U480"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U403"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -17479,7 +16839,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U495"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U417"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -17489,7 +16849,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U510"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U431"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -17499,7 +16859,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U525"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U445"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -17509,35 +16869,35 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U540"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U459"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7212],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,8],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[7206],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[7208],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,8],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,8],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U769.out","PE_init_U771.data.in.0"], - ["_U770.out","PE_init_U771.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U771.data.out"], - ["_U772.out","PE_init_U774.data.in.0"], - ["_U773.out","PE_init_U774.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U774.data.out"], - ["_U775.out","PE_init_U777.data.in.0"], - ["_U776.out","PE_init_U777.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U777.data.out"], - ["_U778.out","PE_init_U780.data.in.0"], - ["_U779.out","PE_init_U780.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U780.data.out"], - ["_U781.out","PE_init_U783.data.in.0"], - ["_U782.out","PE_init_U783.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U783.data.out"], - ["_U784.out","PE_init_U786.data.in.0"], - ["_U785.out","PE_init_U786.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U786.data.out"], - ["_U787.out","PE_init_U789.data.in.0"], - ["_U788.out","PE_init_U789.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U789.data.out"], - ["_U790.out","PE_init_U792.data.in.0"], - ["_U791.out","PE_init_U792.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U792.data.out"], + ["_U686.out","PE_init_U688.data.in.0"], + ["_U687.out","PE_init_U688.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U688.data.out"], + ["_U689.out","PE_init_U691.data.in.0"], + ["_U690.out","PE_init_U691.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U691.data.out"], + ["_U692.out","PE_init_U694.data.in.0"], + ["_U693.out","PE_init_U694.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U694.data.out"], + ["_U695.out","PE_init_U697.data.in.0"], + ["_U696.out","PE_init_U697.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U697.data.out"], + ["_U698.out","PE_init_U700.data.in.0"], + ["_U699.out","PE_init_U700.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U700.data.out"], + ["_U701.out","PE_init_U703.data.in.0"], + ["_U702.out","PE_init_U703.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U703.data.out"], + ["_U704.out","PE_init_U706.data.in.0"], + ["_U705.out","PE_init_U706.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U706.data.out"], + ["_U707.out","PE_init_U709.data.in.0"], + ["_U708.out","PE_init_U709.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U709.data.out"], ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_input_host_stencil_op_hcompute_input_glb_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_output_cgra_stencil_10$inner_compute$mul_kernel_cgra_stencil_17_input_cgra_stencil_17_953$binop.data.in.1","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_new/resnet4_x/resnet4_x.json b/aha_garnet_design_new/resnet4_x/resnet4_x.json index 4d838877a..d24c07a54 100644 --- a/aha_garnet_design_new/resnet4_x/resnet4_x.json +++ b/aha_garnet_design_new/resnet4_x/resnet4_x.json @@ -2,1587 +2,1321 @@ "namespaces":{ "global":{ "modules":{ - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U247":{ + "aff__U173":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U259":{ + "add_all__U185":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U260":{ + "add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U261":{ + "add_all__U187":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U262":{ + "add_all__U188":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U263":{ + "add_all__U189":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U248":{ + "coeff_0_U174":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U250":{ + "coeff_1_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U252":{ + "coeff_2_U178":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U254":{ + "coeff_3_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U256":{ + "coeff_4_U182":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U258":{ + "const_term_U184":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U249":{ + "mul_d0__U175":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U251":{ + "mul_d1__U177":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U253":{ + "mul_d2__U179":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U255":{ + "mul_d3__U181":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U257":{ + "mul_d4__U183":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U249.out","add_all__U259.in0"], - ["mul_d1__U251.out","add_all__U259.in1"], - ["add_all__U260.in0","add_all__U259.out"], - ["mul_d2__U253.out","add_all__U260.in1"], - ["add_all__U261.in0","add_all__U260.out"], - ["mul_d3__U255.out","add_all__U261.in1"], - ["add_all__U262.in0","add_all__U261.out"], - ["mul_d4__U257.out","add_all__U262.in1"], - ["add_all__U263.in0","add_all__U262.out"], - ["const_term_U258.out","add_all__U263.in1"], - ["self.out","add_all__U263.out"], - ["mul_d0__U249.in0","coeff_0_U248.out"], - ["mul_d1__U251.in0","coeff_1_U250.out"], - ["mul_d2__U253.in0","coeff_2_U252.out"], - ["mul_d3__U255.in0","coeff_3_U254.out"], - ["mul_d4__U257.in0","coeff_4_U256.out"], - ["self.d.0","mul_d0__U249.in1"], - ["self.d.1","mul_d1__U251.in1"], - ["self.d.2","mul_d2__U253.in1"], - ["self.d.3","mul_d3__U255.in1"], - ["self.d.4","mul_d4__U257.in1"] + ["mul_d0__U175.out","add_all__U185.in0"], + ["mul_d1__U177.out","add_all__U185.in1"], + ["add_all__U186.in0","add_all__U185.out"], + ["mul_d2__U179.out","add_all__U186.in1"], + ["add_all__U187.in0","add_all__U186.out"], + ["mul_d3__U181.out","add_all__U187.in1"], + ["add_all__U188.in0","add_all__U187.out"], + ["mul_d4__U183.out","add_all__U188.in1"], + ["add_all__U189.in0","add_all__U188.out"], + ["const_term_U184.out","add_all__U189.in1"], + ["self.out","add_all__U189.out"], + ["mul_d0__U175.in0","coeff_0_U174.out"], + ["mul_d1__U177.in0","coeff_1_U176.out"], + ["mul_d2__U179.in0","coeff_2_U178.out"], + ["mul_d3__U181.in0","coeff_3_U180.out"], + ["mul_d4__U183.in0","coeff_4_U182.out"], + ["self.d.0","mul_d0__U175.in1"], + ["self.d.1","mul_d1__U177.in1"], + ["self.d.2","mul_d2__U179.in1"], + ["self.d.3","mul_d3__U181.in1"], + ["self.d.4","mul_d4__U183.in1"] ] }, - "aff__U277":{ + "aff__U203":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U289":{ + "add_all__U215":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U290":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U291":{ + "add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U292":{ + "add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U293":{ + "add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U278":{ + "coeff_0_U204":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U280":{ + "coeff_1_U206":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U282":{ + "coeff_2_U208":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U284":{ + "coeff_3_U210":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U286":{ + "coeff_4_U212":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U288":{ + "const_term_U214":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U279":{ + "mul_d0__U205":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U281":{ + "mul_d1__U207":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U283":{ + "mul_d2__U209":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U285":{ + "mul_d3__U211":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U287":{ + "mul_d4__U213":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U279.out","add_all__U289.in0"], - ["mul_d1__U281.out","add_all__U289.in1"], - ["add_all__U290.in0","add_all__U289.out"], - ["mul_d2__U283.out","add_all__U290.in1"], - ["add_all__U291.in0","add_all__U290.out"], - ["mul_d3__U285.out","add_all__U291.in1"], - ["add_all__U292.in0","add_all__U291.out"], - ["mul_d4__U287.out","add_all__U292.in1"], - ["add_all__U293.in0","add_all__U292.out"], - ["const_term_U288.out","add_all__U293.in1"], - ["self.out","add_all__U293.out"], - ["mul_d0__U279.in0","coeff_0_U278.out"], - ["mul_d1__U281.in0","coeff_1_U280.out"], - ["mul_d2__U283.in0","coeff_2_U282.out"], - ["mul_d3__U285.in0","coeff_3_U284.out"], - ["mul_d4__U287.in0","coeff_4_U286.out"], - ["self.d.0","mul_d0__U279.in1"], - ["self.d.1","mul_d1__U281.in1"], - ["self.d.2","mul_d2__U283.in1"], - ["self.d.3","mul_d3__U285.in1"], - ["self.d.4","mul_d4__U287.in1"] + ["mul_d0__U205.out","add_all__U215.in0"], + ["mul_d1__U207.out","add_all__U215.in1"], + ["add_all__U216.in0","add_all__U215.out"], + ["mul_d2__U209.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d3__U211.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d4__U213.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["const_term_U214.out","add_all__U219.in1"], + ["self.out","add_all__U219.out"], + ["mul_d0__U205.in0","coeff_0_U204.out"], + ["mul_d1__U207.in0","coeff_1_U206.out"], + ["mul_d2__U209.in0","coeff_2_U208.out"], + ["mul_d3__U211.in0","coeff_3_U210.out"], + ["mul_d4__U213.in0","coeff_4_U212.out"], + ["self.d.0","mul_d0__U205.in1"], + ["self.d.1","mul_d1__U207.in1"], + ["self.d.2","mul_d2__U209.in1"], + ["self.d.3","mul_d3__U211.in1"], + ["self.d.4","mul_d4__U213.in1"] ] }, - "aff__U296":{ + "aff__U222":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U319":{ + "add_all__U245":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U320":{ + "add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U321":{ + "add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U297":{ + "coeff_0_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U299":{ + "coeff_1_U225":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_2_U301":{ + "coeff_2_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_3_U303":{ + "coeff_3_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_4_U305":{ + "coeff_4_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_5_U307":{ + "coeff_5_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_6_U309":{ + "coeff_6_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U311":{ + "coeff_7_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U298":{ + "mul_d0__U224":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U300":{ + "mul_d1__U226":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U302":{ + "mul_d2__U228":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U304":{ + "mul_d3__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U306":{ + "mul_d4__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U308":{ + "mul_d5__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U310":{ + "mul_d6__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U312":{ + "mul_d7__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U298.out","add_all__U314.in0"], - ["mul_d1__U300.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U302.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U304.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U306.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["mul_d5__U308.out","add_all__U318.in1"], - ["add_all__U319.in0","add_all__U318.out"], - ["mul_d6__U310.out","add_all__U319.in1"], - ["add_all__U320.in0","add_all__U319.out"], - ["mul_d7__U312.out","add_all__U320.in1"], - ["add_all__U321.in0","add_all__U320.out"], - ["const_term_U313.out","add_all__U321.in1"], - ["self.out","add_all__U321.out"], - ["mul_d0__U298.in0","coeff_0_U297.out"], - ["mul_d1__U300.in0","coeff_1_U299.out"], - ["mul_d2__U302.in0","coeff_2_U301.out"], - ["mul_d3__U304.in0","coeff_3_U303.out"], - ["mul_d4__U306.in0","coeff_4_U305.out"], - ["mul_d5__U308.in0","coeff_5_U307.out"], - ["mul_d6__U310.in0","coeff_6_U309.out"], - ["mul_d7__U312.in0","coeff_7_U311.out"], - ["self.d.0","mul_d0__U298.in1"], - ["self.d.1","mul_d1__U300.in1"], - ["self.d.2","mul_d2__U302.in1"], - ["self.d.3","mul_d3__U304.in1"], - ["self.d.4","mul_d4__U306.in1"], - ["self.d.5","mul_d5__U308.in1"], - ["self.d.6","mul_d6__U310.in1"], - ["self.d.7","mul_d7__U312.in1"] + ["mul_d0__U224.out","add_all__U240.in0"], + ["mul_d1__U226.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U228.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U230.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U232.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["mul_d5__U234.out","add_all__U244.in1"], + ["add_all__U245.in0","add_all__U244.out"], + ["mul_d6__U236.out","add_all__U245.in1"], + ["add_all__U246.in0","add_all__U245.out"], + ["mul_d7__U238.out","add_all__U246.in1"], + ["add_all__U247.in0","add_all__U246.out"], + ["const_term_U239.out","add_all__U247.in1"], + ["self.out","add_all__U247.out"], + ["mul_d0__U224.in0","coeff_0_U223.out"], + ["mul_d1__U226.in0","coeff_1_U225.out"], + ["mul_d2__U228.in0","coeff_2_U227.out"], + ["mul_d3__U230.in0","coeff_3_U229.out"], + ["mul_d4__U232.in0","coeff_4_U231.out"], + ["mul_d5__U234.in0","coeff_5_U233.out"], + ["mul_d6__U236.in0","coeff_6_U235.out"], + ["mul_d7__U238.in0","coeff_7_U237.out"], + ["self.d.0","mul_d0__U224.in1"], + ["self.d.1","mul_d1__U226.in1"], + ["self.d.2","mul_d2__U228.in1"], + ["self.d.3","mul_d3__U230.in1"], + ["self.d.4","mul_d4__U232.in1"], + ["self.d.5","mul_d5__U234.in1"], + ["self.d.6","mul_d6__U236.in1"], + ["self.d.7","mul_d7__U238.in1"] ] }, - "aff__U353":{ + "aff__U279":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U371":{ + "add_all__U297":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U372":{ + "add_all__U298":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U373":{ + "add_all__U299":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U374":{ + "add_all__U300":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U375":{ + "add_all__U301":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U376":{ + "add_all__U302":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U377":{ + "add_all__U303":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U378":{ + "add_all__U304":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U354":{ + "coeff_0_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U356":{ + "coeff_1_U282":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U358":{ + "coeff_2_U284":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_3_U360":{ + "coeff_3_U286":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U362":{ + "coeff_4_U288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U364":{ + "coeff_5_U290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U366":{ + "coeff_6_U292":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U368":{ + "coeff_7_U294":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U370":{ + "const_term_U296":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U355":{ + "mul_d0__U281":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U357":{ + "mul_d1__U283":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U359":{ + "mul_d2__U285":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U361":{ + "mul_d3__U287":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U363":{ + "mul_d4__U289":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U365":{ + "mul_d5__U291":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U367":{ + "mul_d6__U293":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U369":{ + "mul_d7__U295":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U355.out","add_all__U371.in0"], - ["mul_d1__U357.out","add_all__U371.in1"], - ["add_all__U372.in0","add_all__U371.out"], - ["mul_d2__U359.out","add_all__U372.in1"], - ["add_all__U373.in0","add_all__U372.out"], - ["mul_d3__U361.out","add_all__U373.in1"], - ["add_all__U374.in0","add_all__U373.out"], - ["mul_d4__U363.out","add_all__U374.in1"], - ["add_all__U375.in0","add_all__U374.out"], - ["mul_d5__U365.out","add_all__U375.in1"], - ["add_all__U376.in0","add_all__U375.out"], - ["mul_d6__U367.out","add_all__U376.in1"], - ["add_all__U377.in0","add_all__U376.out"], - ["mul_d7__U369.out","add_all__U377.in1"], - ["add_all__U378.in0","add_all__U377.out"], - ["const_term_U370.out","add_all__U378.in1"], - ["self.out","add_all__U378.out"], - ["mul_d0__U355.in0","coeff_0_U354.out"], - ["mul_d1__U357.in0","coeff_1_U356.out"], - ["mul_d2__U359.in0","coeff_2_U358.out"], - ["mul_d3__U361.in0","coeff_3_U360.out"], - ["mul_d4__U363.in0","coeff_4_U362.out"], - ["mul_d5__U365.in0","coeff_5_U364.out"], - ["mul_d6__U367.in0","coeff_6_U366.out"], - ["mul_d7__U369.in0","coeff_7_U368.out"], - ["self.d.0","mul_d0__U355.in1"], - ["self.d.1","mul_d1__U357.in1"], - ["self.d.2","mul_d2__U359.in1"], - ["self.d.3","mul_d3__U361.in1"], - ["self.d.4","mul_d4__U363.in1"], - ["self.d.5","mul_d5__U365.in1"], - ["self.d.6","mul_d6__U367.in1"], - ["self.d.7","mul_d7__U369.in1"] + ["mul_d0__U281.out","add_all__U297.in0"], + ["mul_d1__U283.out","add_all__U297.in1"], + ["add_all__U298.in0","add_all__U297.out"], + ["mul_d2__U285.out","add_all__U298.in1"], + ["add_all__U299.in0","add_all__U298.out"], + ["mul_d3__U287.out","add_all__U299.in1"], + ["add_all__U300.in0","add_all__U299.out"], + ["mul_d4__U289.out","add_all__U300.in1"], + ["add_all__U301.in0","add_all__U300.out"], + ["mul_d5__U291.out","add_all__U301.in1"], + ["add_all__U302.in0","add_all__U301.out"], + ["mul_d6__U293.out","add_all__U302.in1"], + ["add_all__U303.in0","add_all__U302.out"], + ["mul_d7__U295.out","add_all__U303.in1"], + ["add_all__U304.in0","add_all__U303.out"], + ["const_term_U296.out","add_all__U304.in1"], + ["self.out","add_all__U304.out"], + ["mul_d0__U281.in0","coeff_0_U280.out"], + ["mul_d1__U283.in0","coeff_1_U282.out"], + ["mul_d2__U285.in0","coeff_2_U284.out"], + ["mul_d3__U287.in0","coeff_3_U286.out"], + ["mul_d4__U289.in0","coeff_4_U288.out"], + ["mul_d5__U291.in0","coeff_5_U290.out"], + ["mul_d6__U293.in0","coeff_6_U292.out"], + ["mul_d7__U295.in0","coeff_7_U294.out"], + ["self.d.0","mul_d0__U281.in1"], + ["self.d.1","mul_d1__U283.in1"], + ["self.d.2","mul_d2__U285.in1"], + ["self.d.3","mul_d3__U287.in1"], + ["self.d.4","mul_d4__U289.in1"], + ["self.d.5","mul_d5__U291.in1"], + ["self.d.6","mul_d6__U293.in1"], + ["self.d.7","mul_d7__U295.in1"] ] }, - "aff__U399":{ + "aff__U316":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U413":{ + "add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U414":{ + "add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U415":{ + "add_all__U332":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U418":{ + "add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U400":{ + "coeff_0_U317":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U402":{ + "coeff_1_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_2_U404":{ + "coeff_2_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_3_U406":{ + "coeff_3_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_4_U408":{ + "coeff_4_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U410":{ + "coeff_5_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U412":{ + "const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006c00"]} }, - "mul_d0__U401":{ + "mul_d0__U318":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U403":{ + "mul_d1__U320":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U405":{ + "mul_d2__U322":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U407":{ + "mul_d3__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U409":{ + "mul_d4__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U411":{ + "mul_d5__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U401.out","add_all__U413.in0"], - ["mul_d1__U403.out","add_all__U413.in1"], - ["add_all__U414.in0","add_all__U413.out"], - ["mul_d2__U405.out","add_all__U414.in1"], - ["add_all__U415.in0","add_all__U414.out"], - ["mul_d3__U407.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d4__U409.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["mul_d5__U411.out","add_all__U417.in1"], - ["add_all__U418.in0","add_all__U417.out"], - ["const_term_U412.out","add_all__U418.in1"], - ["self.out","add_all__U418.out"], - ["mul_d0__U401.in0","coeff_0_U400.out"], - ["mul_d1__U403.in0","coeff_1_U402.out"], - ["mul_d2__U405.in0","coeff_2_U404.out"], - ["mul_d3__U407.in0","coeff_3_U406.out"], - ["mul_d4__U409.in0","coeff_4_U408.out"], - ["mul_d5__U411.in0","coeff_5_U410.out"], - ["self.d.0","mul_d0__U401.in1"], - ["self.d.1","mul_d1__U403.in1"], - ["self.d.2","mul_d2__U405.in1"], - ["self.d.3","mul_d3__U407.in1"], - ["self.d.4","mul_d4__U409.in1"], - ["self.d.5","mul_d5__U411.in1"] + ["mul_d0__U318.out","add_all__U330.in0"], + ["mul_d1__U320.out","add_all__U330.in1"], + ["add_all__U331.in0","add_all__U330.out"], + ["mul_d2__U322.out","add_all__U331.in1"], + ["add_all__U332.in0","add_all__U331.out"], + ["mul_d3__U324.out","add_all__U332.in1"], + ["add_all__U333.in0","add_all__U332.out"], + ["mul_d4__U326.out","add_all__U333.in1"], + ["add_all__U334.in0","add_all__U333.out"], + ["mul_d5__U328.out","add_all__U334.in1"], + ["add_all__U335.in0","add_all__U334.out"], + ["const_term_U329.out","add_all__U335.in1"], + ["self.out","add_all__U335.out"], + ["mul_d0__U318.in0","coeff_0_U317.out"], + ["mul_d1__U320.in0","coeff_1_U319.out"], + ["mul_d2__U322.in0","coeff_2_U321.out"], + ["mul_d3__U324.in0","coeff_3_U323.out"], + ["mul_d4__U326.in0","coeff_4_U325.out"], + ["mul_d5__U328.in0","coeff_5_U327.out"], + ["self.d.0","mul_d0__U318.in1"], + ["self.d.1","mul_d1__U320.in1"], + ["self.d.2","mul_d2__U322.in1"], + ["self.d.3","mul_d3__U324.in1"], + ["self.d.4","mul_d4__U326.in1"], + ["self.d.5","mul_d5__U328.in1"] ] }, - "aff__U41":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U51":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U52":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U53":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U42":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U44":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U46":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U48":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U50":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U43":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U437":{ + "aff__U354":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U453":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U454":{ + "add_all__U371":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U455":{ + "add_all__U372":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U456":{ + "add_all__U373":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U355":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001880"]} }, - "coeff_2_U442":{ + "coeff_2_U359":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U444":{ + "coeff_3_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000e"]} }, - "coeff_4_U446":{ + "coeff_4_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_5_U448":{ + "coeff_5_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000c4"]} }, - "const_term_U450":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U439":{ + "mul_d0__U356":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U358":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U443":{ + "mul_d2__U360":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U445":{ + "mul_d3__U362":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U447":{ + "mul_d4__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U449":{ + "mul_d5__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U451.in0"], - ["mul_d1__U441.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["mul_d2__U443.out","add_all__U452.in1"], - ["add_all__U453.in0","add_all__U452.out"], - ["mul_d3__U445.out","add_all__U453.in1"], - ["add_all__U454.in0","add_all__U453.out"], - ["mul_d4__U447.out","add_all__U454.in1"], - ["add_all__U455.in0","add_all__U454.out"], - ["mul_d5__U449.out","add_all__U455.in1"], - ["add_all__U456.in0","add_all__U455.out"], - ["const_term_U450.out","add_all__U456.in1"], - ["self.out","add_all__U456.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["mul_d2__U443.in0","coeff_2_U442.out"], - ["mul_d3__U445.in0","coeff_3_U444.out"], - ["mul_d4__U447.in0","coeff_4_U446.out"], - ["mul_d5__U449.in0","coeff_5_U448.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"], - ["self.d.2","mul_d2__U443.in1"], - ["self.d.3","mul_d3__U445.in1"], - ["self.d.4","mul_d4__U447.in1"], - ["self.d.5","mul_d5__U449.in1"] + ["mul_d0__U356.out","add_all__U368.in0"], + ["mul_d1__U358.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["mul_d2__U360.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["mul_d3__U362.out","add_all__U370.in1"], + ["add_all__U371.in0","add_all__U370.out"], + ["mul_d4__U364.out","add_all__U371.in1"], + ["add_all__U372.in0","add_all__U371.out"], + ["mul_d5__U366.out","add_all__U372.in1"], + ["add_all__U373.in0","add_all__U372.out"], + ["const_term_U367.out","add_all__U373.in1"], + ["self.out","add_all__U373.out"], + ["mul_d0__U356.in0","coeff_0_U355.out"], + ["mul_d1__U358.in0","coeff_1_U357.out"], + ["mul_d2__U360.in0","coeff_2_U359.out"], + ["mul_d3__U362.in0","coeff_3_U361.out"], + ["mul_d4__U364.in0","coeff_4_U363.out"], + ["mul_d5__U366.in0","coeff_5_U365.out"], + ["self.d.0","mul_d0__U356.in1"], + ["self.d.1","mul_d1__U358.in1"], + ["self.d.2","mul_d2__U360.in1"], + ["self.d.3","mul_d3__U362.in1"], + ["self.d.4","mul_d4__U364.in1"], + ["self.d.5","mul_d5__U366.in1"] ] }, - "aff__U459":{ + "aff__U376":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U469":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U470":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U471":{ + "add_all__U388":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U472":{ + "add_all__U389":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U460":{ + "coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U462":{ + "coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000e00"]} }, - "coeff_2_U464":{ + "coeff_2_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_3_U466":{ + "coeff_3_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U468":{ + "const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000c37f"]} }, - "mul_d0__U461":{ + "mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U463":{ + "mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U465":{ + "mul_d2__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U467":{ + "mul_d3__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U461.out","add_all__U469.in0"], - ["mul_d1__U463.out","add_all__U469.in1"], - ["add_all__U470.in0","add_all__U469.out"], - ["mul_d2__U465.out","add_all__U470.in1"], - ["add_all__U471.in0","add_all__U470.out"], - ["mul_d3__U467.out","add_all__U471.in1"], - ["add_all__U472.in0","add_all__U471.out"], - ["const_term_U468.out","add_all__U472.in1"], - ["self.out","add_all__U472.out"], - ["mul_d0__U461.in0","coeff_0_U460.out"], - ["mul_d1__U463.in0","coeff_1_U462.out"], - ["mul_d2__U465.in0","coeff_2_U464.out"], - ["mul_d3__U467.in0","coeff_3_U466.out"], - ["self.d.0","mul_d0__U461.in1"], - ["self.d.1","mul_d1__U463.in1"], - ["self.d.2","mul_d2__U465.in1"], - ["self.d.3","mul_d3__U467.in1"] + ["mul_d0__U378.out","add_all__U386.in0"], + ["mul_d1__U380.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["mul_d2__U382.out","add_all__U387.in1"], + ["add_all__U388.in0","add_all__U387.out"], + ["mul_d3__U384.out","add_all__U388.in1"], + ["add_all__U389.in0","add_all__U388.out"], + ["const_term_U385.out","add_all__U389.in1"], + ["self.out","add_all__U389.out"], + ["mul_d0__U378.in0","coeff_0_U377.out"], + ["mul_d1__U380.in0","coeff_1_U379.out"], + ["mul_d2__U382.in0","coeff_2_U381.out"], + ["mul_d3__U384.in0","coeff_3_U383.out"], + ["self.d.0","mul_d0__U378.in1"], + ["self.d.1","mul_d1__U380.in1"], + ["self.d.2","mul_d2__U382.in1"], + ["self.d.3","mul_d3__U384.in1"] ] }, - "aff__U482":{ + "aff__U399":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U492":{ + "add_all__U409":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U493":{ + "add_all__U410":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U494":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U495":{ + "add_all__U412":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U400":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U402":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U487":{ + "coeff_2_U404":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000e"]} }, - "coeff_3_U489":{ + "coeff_3_U406":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000c4"]} }, - "const_term_U491":{ + "const_term_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U484":{ + "mul_d0__U401":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U403":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U488":{ + "mul_d2__U405":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U490":{ + "mul_d3__U407":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U492.in0"], - ["mul_d1__U486.out","add_all__U492.in1"], - ["add_all__U493.in0","add_all__U492.out"], - ["mul_d2__U488.out","add_all__U493.in1"], - ["add_all__U494.in0","add_all__U493.out"], - ["mul_d3__U490.out","add_all__U494.in1"], - ["add_all__U495.in0","add_all__U494.out"], - ["const_term_U491.out","add_all__U495.in1"], - ["self.out","add_all__U495.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["mul_d2__U488.in0","coeff_2_U487.out"], - ["mul_d3__U490.in0","coeff_3_U489.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"], - ["self.d.2","mul_d2__U488.in1"], - ["self.d.3","mul_d3__U490.in1"] + ["mul_d0__U401.out","add_all__U409.in0"], + ["mul_d1__U403.out","add_all__U409.in1"], + ["add_all__U410.in0","add_all__U409.out"], + ["mul_d2__U405.out","add_all__U410.in1"], + ["add_all__U411.in0","add_all__U410.out"], + ["mul_d3__U407.out","add_all__U411.in1"], + ["add_all__U412.in0","add_all__U411.out"], + ["const_term_U408.out","add_all__U412.in1"], + ["self.out","add_all__U412.out"], + ["mul_d0__U401.in0","coeff_0_U400.out"], + ["mul_d1__U403.in0","coeff_1_U402.out"], + ["mul_d2__U405.in0","coeff_2_U404.out"], + ["mul_d3__U407.in0","coeff_3_U406.out"], + ["self.d.0","mul_d0__U401.in1"], + ["self.d.1","mul_d1__U403.in1"], + ["self.d.2","mul_d2__U405.in1"], + ["self.d.3","mul_d3__U407.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U71":{ + "add_all__U62":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U72":{ + "add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U73":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U74":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U70":{ + "const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U71.in0"], - ["mul_d1__U61.out","add_all__U71.in1"], - ["add_all__U72.in0","add_all__U71.out"], - ["mul_d2__U63.out","add_all__U72.in1"], - ["add_all__U73.in0","add_all__U72.out"], - ["mul_d3__U65.out","add_all__U73.in1"], - ["add_all__U74.in0","add_all__U73.out"], - ["mul_d4__U67.out","add_all__U74.in1"], - ["add_all__U75.in0","add_all__U74.out"], - ["mul_d5__U69.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["const_term_U70.out","add_all__U76.in1"], - ["self.out","add_all__U76.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"] + ["mul_d0__U50.out","add_all__U62.in0"], + ["mul_d1__U52.out","add_all__U62.in1"], + ["add_all__U63.in0","add_all__U62.out"], + ["mul_d2__U54.out","add_all__U63.in1"], + ["add_all__U64.in0","add_all__U63.out"], + ["mul_d3__U56.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["mul_d4__U58.out","add_all__U65.in1"], + ["add_all__U66.in0","add_all__U65.out"], + ["mul_d5__U60.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["const_term_U61.out","add_all__U67.in1"], + ["self.out","add_all__U67.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U109":{ + "add_all__U100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U110":{ + "add_all__U101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000800"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U108":{ + "const_term_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U101":{ + "mul_d2__U92":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d3__U94":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d5__U98":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U109.in0"], - ["mul_d1__U99.out","add_all__U109.in1"], - ["add_all__U110.in0","add_all__U109.out"], - ["mul_d2__U101.out","add_all__U110.in1"], - ["add_all__U111.in0","add_all__U110.out"], - ["mul_d3__U103.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d4__U105.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d5__U107.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U108.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"] + ["mul_d0__U88.out","add_all__U100.in0"], + ["mul_d1__U90.out","add_all__U100.in1"], + ["add_all__U101.in0","add_all__U100.out"], + ["mul_d2__U92.out","add_all__U101.in1"], + ["add_all__U102.in0","add_all__U101.out"], + ["mul_d3__U94.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d4__U96.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d5__U98.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["const_term_U99.out","add_all__U105.in1"], + ["self.out","add_all__U105.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"] ] }, - "affine_controller__U17":{ + "aff__U9":{ "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], - ["rst_n","BitIn"] + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "_U32":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U33":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U18" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U34":{ - "modref":"corebit.and" - }, - "d_0_am__U35":{ - "modref":"corebit.and" - }, - "d_0_am__U36":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ + "add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U37":{ - "modref":"corebit.and" - }, - "d_1_am__U38":{ - "modref":"corebit.and" - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ + "add_all__U20":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U39":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ + "add_all__U21":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U32.out"], - ["d_2_inc.in1","_U32.out"], - ["d_3_inc.in1","_U32.out"], - ["cmp_time.in1","_U33.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U34.in0"], - ["d_1_at_max.out","d_0_am__U34.in1"], - ["d_0_am__U35.in0","d_0_am__U34.out"], - ["d_2_at_max.out","d_0_am__U35.in1"], - ["d_0_am__U36.in0","d_0_am__U35.out"], - ["d_3_at_max.out","d_0_am__U36.in1"], - ["d_0_next_value.sel","d_0_am__U36.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U37.in0"], - ["d_2_at_max.out","d_1_am__U37.in1"], - ["d_1_am__U38.in0","d_1_am__U37.out"], - ["d_3_at_max.out","d_1_am__U38.in1"], - ["d_1_next_value.sel","d_1_am__U38.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U39.in0"], - ["d_3_at_max.out","d_2_am__U39.in1"], - ["d_2_next_value.sel","d_2_am__U39.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U13":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U15":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U17":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U246":{ + "affine_controller__U172":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1590,18 +1324,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U264":{ + "_U190":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U265":{ + "_U191":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U247" + "modref":"global.aff__U173" }, "cmp_time":{ "genref":"coreir.eq", @@ -1611,16 +1345,16 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U266":{ + "d_0_am__U192":{ "modref":"corebit.and" }, - "d_0_am__U267":{ + "d_0_am__U193":{ "modref":"corebit.and" }, - "d_0_am__U268":{ + "d_0_am__U194":{ "modref":"corebit.and" }, - "d_0_am__U269":{ + "d_0_am__U195":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1654,13 +1388,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U270":{ + "d_1_am__U196":{ "modref":"corebit.and" }, - "d_1_am__U271":{ + "d_1_am__U197":{ "modref":"corebit.and" }, - "d_1_am__U272":{ + "d_1_am__U198":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1694,10 +1428,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U273":{ + "d_2_am__U199":{ "modref":"corebit.and" }, - "d_2_am__U274":{ + "d_2_am__U200":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -1731,7 +1465,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U275":{ + "d_3_am__U201":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -1806,12 +1540,12 @@ } }, "connections":[ - ["d_0_inc.in1","_U264.out"], - ["d_1_inc.in1","_U264.out"], - ["d_2_inc.in1","_U264.out"], - ["d_3_inc.in1","_U264.out"], - ["d_4_inc.in1","_U264.out"], - ["cmp_time.in1","_U265.out"], + ["d_0_inc.in1","_U190.out"], + ["d_1_inc.in1","_U190.out"], + ["d_2_inc.in1","_U190.out"], + ["d_3_inc.in1","_U190.out"], + ["d_4_inc.in1","_U190.out"], + ["cmp_time.in1","_U191.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -1828,15 +1562,15 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U266.in0"], - ["d_1_at_max.out","d_0_am__U266.in1"], - ["d_0_am__U267.in0","d_0_am__U266.out"], - ["d_2_at_max.out","d_0_am__U267.in1"], - ["d_0_am__U268.in0","d_0_am__U267.out"], - ["d_3_at_max.out","d_0_am__U268.in1"], - ["d_0_am__U269.in0","d_0_am__U268.out"], - ["d_4_at_max.out","d_0_am__U269.in1"], - ["d_0_next_value.sel","d_0_am__U269.out"], + ["true.out","d_0_am__U192.in0"], + ["d_1_at_max.out","d_0_am__U192.in1"], + ["d_0_am__U193.in0","d_0_am__U192.out"], + ["d_2_at_max.out","d_0_am__U193.in1"], + ["d_0_am__U194.in0","d_0_am__U193.out"], + ["d_3_at_max.out","d_0_am__U194.in1"], + ["d_0_am__U195.in0","d_0_am__U194.out"], + ["d_4_at_max.out","d_0_am__U195.in1"], + ["d_0_next_value.sel","d_0_am__U195.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1849,13 +1583,13 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U270.in0"], - ["d_2_at_max.out","d_1_am__U270.in1"], - ["d_1_am__U271.in0","d_1_am__U270.out"], - ["d_3_at_max.out","d_1_am__U271.in1"], - ["d_1_am__U272.in0","d_1_am__U271.out"], - ["d_4_at_max.out","d_1_am__U272.in1"], - ["d_1_next_value.sel","d_1_am__U272.out"], + ["true.out","d_1_am__U196.in0"], + ["d_2_at_max.out","d_1_am__U196.in1"], + ["d_1_am__U197.in0","d_1_am__U196.out"], + ["d_3_at_max.out","d_1_am__U197.in1"], + ["d_1_am__U198.in0","d_1_am__U197.out"], + ["d_4_at_max.out","d_1_am__U198.in1"], + ["d_1_next_value.sel","d_1_am__U198.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1868,11 +1602,11 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U273.in0"], - ["d_3_at_max.out","d_2_am__U273.in1"], - ["d_2_am__U274.in0","d_2_am__U273.out"], - ["d_4_at_max.out","d_2_am__U274.in1"], - ["d_2_next_value.sel","d_2_am__U274.out"], + ["true.out","d_2_am__U199.in0"], + ["d_3_at_max.out","d_2_am__U199.in1"], + ["d_2_am__U200.in0","d_2_am__U199.out"], + ["d_4_at_max.out","d_2_am__U200.in1"], + ["d_2_next_value.sel","d_2_am__U200.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -1885,9 +1619,9 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U275.in0"], - ["d_4_at_max.out","d_3_am__U275.in1"], - ["d_3_next_value.sel","d_3_am__U275.out"], + ["true.out","d_3_am__U201.in0"], + ["d_4_at_max.out","d_3_am__U201.in1"], + ["d_3_next_value.sel","d_3_am__U201.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -1915,7 +1649,7 @@ ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U295":{ + "affine_controller__U221":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1923,18 +1657,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U322":{ + "_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U296" + "modref":"global.aff__U222" }, "cmp_time":{ "genref":"coreir.eq", @@ -1944,25 +1678,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U324":{ + "d_0_am__U250":{ "modref":"corebit.and" }, - "d_0_am__U325":{ + "d_0_am__U251":{ "modref":"corebit.and" }, - "d_0_am__U326":{ + "d_0_am__U252":{ "modref":"corebit.and" }, - "d_0_am__U327":{ + "d_0_am__U253":{ "modref":"corebit.and" }, - "d_0_am__U328":{ + "d_0_am__U254":{ "modref":"corebit.and" }, - "d_0_am__U329":{ + "d_0_am__U255":{ "modref":"corebit.and" }, - "d_0_am__U330":{ + "d_0_am__U256":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1996,22 +1730,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U331":{ + "d_1_am__U257":{ "modref":"corebit.and" }, - "d_1_am__U332":{ + "d_1_am__U258":{ "modref":"corebit.and" }, - "d_1_am__U333":{ + "d_1_am__U259":{ "modref":"corebit.and" }, - "d_1_am__U334":{ + "d_1_am__U260":{ "modref":"corebit.and" }, - "d_1_am__U335":{ + "d_1_am__U261":{ "modref":"corebit.and" }, - "d_1_am__U336":{ + "d_1_am__U262":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2045,19 +1779,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U337":{ + "d_2_am__U263":{ "modref":"corebit.and" }, - "d_2_am__U338":{ + "d_2_am__U264":{ "modref":"corebit.and" }, - "d_2_am__U339":{ + "d_2_am__U265":{ "modref":"corebit.and" }, - "d_2_am__U340":{ + "d_2_am__U266":{ "modref":"corebit.and" }, - "d_2_am__U341":{ + "d_2_am__U267":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2091,16 +1825,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U342":{ + "d_3_am__U268":{ "modref":"corebit.and" }, - "d_3_am__U343":{ + "d_3_am__U269":{ "modref":"corebit.and" }, - "d_3_am__U344":{ + "d_3_am__U270":{ "modref":"corebit.and" }, - "d_3_am__U345":{ + "d_3_am__U271":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2134,13 +1868,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U346":{ + "d_4_am__U272":{ "modref":"corebit.and" }, - "d_4_am__U347":{ + "d_4_am__U273":{ "modref":"corebit.and" }, - "d_4_am__U348":{ + "d_4_am__U274":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2174,10 +1908,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U349":{ + "d_5_am__U275":{ "modref":"corebit.and" }, - "d_5_am__U350":{ + "d_5_am__U276":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -2211,7 +1945,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U351":{ + "d_6_am__U277":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -2286,15 +2020,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U322.out"], - ["d_1_inc.in1","_U322.out"], - ["d_2_inc.in1","_U322.out"], - ["d_3_inc.in1","_U322.out"], - ["d_4_inc.in1","_U322.out"], - ["d_5_inc.in1","_U322.out"], - ["d_6_inc.in1","_U322.out"], - ["d_7_inc.in1","_U322.out"], - ["cmp_time.in1","_U323.out"], + ["d_0_inc.in1","_U248.out"], + ["d_1_inc.in1","_U248.out"], + ["d_2_inc.in1","_U248.out"], + ["d_3_inc.in1","_U248.out"], + ["d_4_inc.in1","_U248.out"], + ["d_5_inc.in1","_U248.out"], + ["d_6_inc.in1","_U248.out"], + ["d_7_inc.in1","_U248.out"], + ["cmp_time.in1","_U249.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2317,21 +2051,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U324.in0"], - ["d_1_at_max.out","d_0_am__U324.in1"], - ["d_0_am__U325.in0","d_0_am__U324.out"], - ["d_2_at_max.out","d_0_am__U325.in1"], - ["d_0_am__U326.in0","d_0_am__U325.out"], - ["d_3_at_max.out","d_0_am__U326.in1"], - ["d_0_am__U327.in0","d_0_am__U326.out"], - ["d_4_at_max.out","d_0_am__U327.in1"], - ["d_0_am__U328.in0","d_0_am__U327.out"], - ["d_5_at_max.out","d_0_am__U328.in1"], - ["d_0_am__U329.in0","d_0_am__U328.out"], - ["d_6_at_max.out","d_0_am__U329.in1"], - ["d_0_am__U330.in0","d_0_am__U329.out"], - ["d_7_at_max.out","d_0_am__U330.in1"], - ["d_0_next_value.sel","d_0_am__U330.out"], + ["true.out","d_0_am__U250.in0"], + ["d_1_at_max.out","d_0_am__U250.in1"], + ["d_0_am__U251.in0","d_0_am__U250.out"], + ["d_2_at_max.out","d_0_am__U251.in1"], + ["d_0_am__U252.in0","d_0_am__U251.out"], + ["d_3_at_max.out","d_0_am__U252.in1"], + ["d_0_am__U253.in0","d_0_am__U252.out"], + ["d_4_at_max.out","d_0_am__U253.in1"], + ["d_0_am__U254.in0","d_0_am__U253.out"], + ["d_5_at_max.out","d_0_am__U254.in1"], + ["d_0_am__U255.in0","d_0_am__U254.out"], + ["d_6_at_max.out","d_0_am__U255.in1"], + ["d_0_am__U256.in0","d_0_am__U255.out"], + ["d_7_at_max.out","d_0_am__U256.in1"], + ["d_0_next_value.sel","d_0_am__U256.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2344,19 +2078,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U331.in0"], - ["d_2_at_max.out","d_1_am__U331.in1"], - ["d_1_am__U332.in0","d_1_am__U331.out"], - ["d_3_at_max.out","d_1_am__U332.in1"], - ["d_1_am__U333.in0","d_1_am__U332.out"], - ["d_4_at_max.out","d_1_am__U333.in1"], - ["d_1_am__U334.in0","d_1_am__U333.out"], - ["d_5_at_max.out","d_1_am__U334.in1"], - ["d_1_am__U335.in0","d_1_am__U334.out"], - ["d_6_at_max.out","d_1_am__U335.in1"], - ["d_1_am__U336.in0","d_1_am__U335.out"], - ["d_7_at_max.out","d_1_am__U336.in1"], - ["d_1_next_value.sel","d_1_am__U336.out"], + ["true.out","d_1_am__U257.in0"], + ["d_2_at_max.out","d_1_am__U257.in1"], + ["d_1_am__U258.in0","d_1_am__U257.out"], + ["d_3_at_max.out","d_1_am__U258.in1"], + ["d_1_am__U259.in0","d_1_am__U258.out"], + ["d_4_at_max.out","d_1_am__U259.in1"], + ["d_1_am__U260.in0","d_1_am__U259.out"], + ["d_5_at_max.out","d_1_am__U260.in1"], + ["d_1_am__U261.in0","d_1_am__U260.out"], + ["d_6_at_max.out","d_1_am__U261.in1"], + ["d_1_am__U262.in0","d_1_am__U261.out"], + ["d_7_at_max.out","d_1_am__U262.in1"], + ["d_1_next_value.sel","d_1_am__U262.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2369,17 +2103,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U337.in0"], - ["d_3_at_max.out","d_2_am__U337.in1"], - ["d_2_am__U338.in0","d_2_am__U337.out"], - ["d_4_at_max.out","d_2_am__U338.in1"], - ["d_2_am__U339.in0","d_2_am__U338.out"], - ["d_5_at_max.out","d_2_am__U339.in1"], - ["d_2_am__U340.in0","d_2_am__U339.out"], - ["d_6_at_max.out","d_2_am__U340.in1"], - ["d_2_am__U341.in0","d_2_am__U340.out"], - ["d_7_at_max.out","d_2_am__U341.in1"], - ["d_2_next_value.sel","d_2_am__U341.out"], + ["true.out","d_2_am__U263.in0"], + ["d_3_at_max.out","d_2_am__U263.in1"], + ["d_2_am__U264.in0","d_2_am__U263.out"], + ["d_4_at_max.out","d_2_am__U264.in1"], + ["d_2_am__U265.in0","d_2_am__U264.out"], + ["d_5_at_max.out","d_2_am__U265.in1"], + ["d_2_am__U266.in0","d_2_am__U265.out"], + ["d_6_at_max.out","d_2_am__U266.in1"], + ["d_2_am__U267.in0","d_2_am__U266.out"], + ["d_7_at_max.out","d_2_am__U267.in1"], + ["d_2_next_value.sel","d_2_am__U267.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2392,15 +2126,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U342.in0"], - ["d_4_at_max.out","d_3_am__U342.in1"], - ["d_3_am__U343.in0","d_3_am__U342.out"], - ["d_5_at_max.out","d_3_am__U343.in1"], - ["d_3_am__U344.in0","d_3_am__U343.out"], - ["d_6_at_max.out","d_3_am__U344.in1"], - ["d_3_am__U345.in0","d_3_am__U344.out"], - ["d_7_at_max.out","d_3_am__U345.in1"], - ["d_3_next_value.sel","d_3_am__U345.out"], + ["true.out","d_3_am__U268.in0"], + ["d_4_at_max.out","d_3_am__U268.in1"], + ["d_3_am__U269.in0","d_3_am__U268.out"], + ["d_5_at_max.out","d_3_am__U269.in1"], + ["d_3_am__U270.in0","d_3_am__U269.out"], + ["d_6_at_max.out","d_3_am__U270.in1"], + ["d_3_am__U271.in0","d_3_am__U270.out"], + ["d_7_at_max.out","d_3_am__U271.in1"], + ["d_3_next_value.sel","d_3_am__U271.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2413,13 +2147,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U346.in0"], - ["d_5_at_max.out","d_4_am__U346.in1"], - ["d_4_am__U347.in0","d_4_am__U346.out"], - ["d_6_at_max.out","d_4_am__U347.in1"], - ["d_4_am__U348.in0","d_4_am__U347.out"], - ["d_7_at_max.out","d_4_am__U348.in1"], - ["d_4_next_value.sel","d_4_am__U348.out"], + ["true.out","d_4_am__U272.in0"], + ["d_5_at_max.out","d_4_am__U272.in1"], + ["d_4_am__U273.in0","d_4_am__U272.out"], + ["d_6_at_max.out","d_4_am__U273.in1"], + ["d_4_am__U274.in0","d_4_am__U273.out"], + ["d_7_at_max.out","d_4_am__U274.in1"], + ["d_4_next_value.sel","d_4_am__U274.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2432,11 +2166,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U349.in0"], - ["d_6_at_max.out","d_5_am__U349.in1"], - ["d_5_am__U350.in0","d_5_am__U349.out"], - ["d_7_at_max.out","d_5_am__U350.in1"], - ["d_5_next_value.sel","d_5_am__U350.out"], + ["true.out","d_5_am__U275.in0"], + ["d_6_at_max.out","d_5_am__U275.in1"], + ["d_5_am__U276.in0","d_5_am__U275.out"], + ["d_7_at_max.out","d_5_am__U276.in1"], + ["d_5_next_value.sel","d_5_am__U276.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -2449,9 +2183,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U351.in0"], - ["d_7_at_max.out","d_6_am__U351.in1"], - ["d_6_next_value.sel","d_6_am__U351.out"], + ["true.out","d_6_am__U277.in0"], + ["d_7_at_max.out","d_6_am__U277.in1"], + ["d_6_next_value.sel","d_6_am__U277.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -2479,7 +2213,7 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U398":{ + "affine_controller__U315":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2487,18 +2221,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U419":{ + "_U336":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U420":{ + "_U337":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U399" + "modref":"global.aff__U316" }, "cmp_time":{ "genref":"coreir.eq", @@ -2508,19 +2242,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U421":{ + "d_0_am__U338":{ "modref":"corebit.and" }, - "d_0_am__U422":{ + "d_0_am__U339":{ "modref":"corebit.and" }, - "d_0_am__U423":{ + "d_0_am__U340":{ "modref":"corebit.and" }, - "d_0_am__U424":{ + "d_0_am__U341":{ "modref":"corebit.and" }, - "d_0_am__U425":{ + "d_0_am__U342":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2554,16 +2288,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U426":{ + "d_1_am__U343":{ "modref":"corebit.and" }, - "d_1_am__U427":{ + "d_1_am__U344":{ "modref":"corebit.and" }, - "d_1_am__U428":{ + "d_1_am__U345":{ "modref":"corebit.and" }, - "d_1_am__U429":{ + "d_1_am__U346":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2597,13 +2331,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U430":{ + "d_2_am__U347":{ "modref":"corebit.and" }, - "d_2_am__U431":{ + "d_2_am__U348":{ "modref":"corebit.and" }, - "d_2_am__U432":{ + "d_2_am__U349":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2637,10 +2371,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U433":{ + "d_3_am__U350":{ "modref":"corebit.and" }, - "d_3_am__U434":{ + "d_3_am__U351":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2674,7 +2408,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U435":{ + "d_4_am__U352":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2749,13 +2483,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U419.out"], - ["d_1_inc.in1","_U419.out"], - ["d_2_inc.in1","_U419.out"], - ["d_3_inc.in1","_U419.out"], - ["d_4_inc.in1","_U419.out"], - ["d_5_inc.in1","_U419.out"], - ["cmp_time.in1","_U420.out"], + ["d_0_inc.in1","_U336.out"], + ["d_1_inc.in1","_U336.out"], + ["d_2_inc.in1","_U336.out"], + ["d_3_inc.in1","_U336.out"], + ["d_4_inc.in1","_U336.out"], + ["d_5_inc.in1","_U336.out"], + ["cmp_time.in1","_U337.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2774,17 +2508,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U421.in0"], - ["d_1_at_max.out","d_0_am__U421.in1"], - ["d_0_am__U422.in0","d_0_am__U421.out"], - ["d_2_at_max.out","d_0_am__U422.in1"], - ["d_0_am__U423.in0","d_0_am__U422.out"], - ["d_3_at_max.out","d_0_am__U423.in1"], - ["d_0_am__U424.in0","d_0_am__U423.out"], - ["d_4_at_max.out","d_0_am__U424.in1"], - ["d_0_am__U425.in0","d_0_am__U424.out"], - ["d_5_at_max.out","d_0_am__U425.in1"], - ["d_0_next_value.sel","d_0_am__U425.out"], + ["true.out","d_0_am__U338.in0"], + ["d_1_at_max.out","d_0_am__U338.in1"], + ["d_0_am__U339.in0","d_0_am__U338.out"], + ["d_2_at_max.out","d_0_am__U339.in1"], + ["d_0_am__U340.in0","d_0_am__U339.out"], + ["d_3_at_max.out","d_0_am__U340.in1"], + ["d_0_am__U341.in0","d_0_am__U340.out"], + ["d_4_at_max.out","d_0_am__U341.in1"], + ["d_0_am__U342.in0","d_0_am__U341.out"], + ["d_5_at_max.out","d_0_am__U342.in1"], + ["d_0_next_value.sel","d_0_am__U342.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2797,15 +2531,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U426.in0"], - ["d_2_at_max.out","d_1_am__U426.in1"], - ["d_1_am__U427.in0","d_1_am__U426.out"], - ["d_3_at_max.out","d_1_am__U427.in1"], - ["d_1_am__U428.in0","d_1_am__U427.out"], - ["d_4_at_max.out","d_1_am__U428.in1"], - ["d_1_am__U429.in0","d_1_am__U428.out"], - ["d_5_at_max.out","d_1_am__U429.in1"], - ["d_1_next_value.sel","d_1_am__U429.out"], + ["true.out","d_1_am__U343.in0"], + ["d_2_at_max.out","d_1_am__U343.in1"], + ["d_1_am__U344.in0","d_1_am__U343.out"], + ["d_3_at_max.out","d_1_am__U344.in1"], + ["d_1_am__U345.in0","d_1_am__U344.out"], + ["d_4_at_max.out","d_1_am__U345.in1"], + ["d_1_am__U346.in0","d_1_am__U345.out"], + ["d_5_at_max.out","d_1_am__U346.in1"], + ["d_1_next_value.sel","d_1_am__U346.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2818,13 +2552,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U430.in0"], - ["d_3_at_max.out","d_2_am__U430.in1"], - ["d_2_am__U431.in0","d_2_am__U430.out"], - ["d_4_at_max.out","d_2_am__U431.in1"], - ["d_2_am__U432.in0","d_2_am__U431.out"], - ["d_5_at_max.out","d_2_am__U432.in1"], - ["d_2_next_value.sel","d_2_am__U432.out"], + ["true.out","d_2_am__U347.in0"], + ["d_3_at_max.out","d_2_am__U347.in1"], + ["d_2_am__U348.in0","d_2_am__U347.out"], + ["d_4_at_max.out","d_2_am__U348.in1"], + ["d_2_am__U349.in0","d_2_am__U348.out"], + ["d_5_at_max.out","d_2_am__U349.in1"], + ["d_2_next_value.sel","d_2_am__U349.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2837,11 +2571,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U433.in0"], - ["d_4_at_max.out","d_3_am__U433.in1"], - ["d_3_am__U434.in0","d_3_am__U433.out"], - ["d_5_at_max.out","d_3_am__U434.in1"], - ["d_3_next_value.sel","d_3_am__U434.out"], + ["true.out","d_3_am__U350.in0"], + ["d_4_at_max.out","d_3_am__U350.in1"], + ["d_3_am__U351.in0","d_3_am__U350.out"], + ["d_5_at_max.out","d_3_am__U351.in1"], + ["d_3_next_value.sel","d_3_am__U351.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2854,9 +2588,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U435.in0"], - ["d_5_at_max.out","d_4_am__U435.in1"], - ["d_4_next_value.sel","d_4_am__U435.out"], + ["true.out","d_4_am__U352.in0"], + ["d_5_at_max.out","d_4_am__U352.in1"], + ["d_4_next_value.sel","d_4_am__U352.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2884,7 +2618,7 @@ ["self.d.5","d_5_reg.out"] ] }, - "affine_controller__U458":{ + "affine_controller__U375":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2892,18 +2626,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U473":{ + "_U390":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U474":{ + "_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U459" + "modref":"global.aff__U376" }, "cmp_time":{ "genref":"coreir.eq", @@ -2913,13 +2647,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U475":{ + "d_0_am__U392":{ "modref":"corebit.and" }, - "d_0_am__U476":{ + "d_0_am__U393":{ "modref":"corebit.and" }, - "d_0_am__U477":{ + "d_0_am__U394":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2953,10 +2687,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U478":{ + "d_1_am__U395":{ "modref":"corebit.and" }, - "d_1_am__U479":{ + "d_1_am__U396":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2990,7 +2724,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U480":{ + "d_2_am__U397":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -3065,11 +2799,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U473.out"], - ["d_1_inc.in1","_U473.out"], - ["d_2_inc.in1","_U473.out"], - ["d_3_inc.in1","_U473.out"], - ["cmp_time.in1","_U474.out"], + ["d_0_inc.in1","_U390.out"], + ["d_1_inc.in1","_U390.out"], + ["d_2_inc.in1","_U390.out"], + ["d_3_inc.in1","_U390.out"], + ["cmp_time.in1","_U391.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3084,13 +2818,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U475.in0"], - ["d_1_at_max.out","d_0_am__U475.in1"], - ["d_0_am__U476.in0","d_0_am__U475.out"], - ["d_2_at_max.out","d_0_am__U476.in1"], - ["d_0_am__U477.in0","d_0_am__U476.out"], - ["d_3_at_max.out","d_0_am__U477.in1"], - ["d_0_next_value.sel","d_0_am__U477.out"], + ["true.out","d_0_am__U392.in0"], + ["d_1_at_max.out","d_0_am__U392.in1"], + ["d_0_am__U393.in0","d_0_am__U392.out"], + ["d_2_at_max.out","d_0_am__U393.in1"], + ["d_0_am__U394.in0","d_0_am__U393.out"], + ["d_3_at_max.out","d_0_am__U394.in1"], + ["d_0_next_value.sel","d_0_am__U394.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3103,11 +2837,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U478.in0"], - ["d_2_at_max.out","d_1_am__U478.in1"], - ["d_1_am__U479.in0","d_1_am__U478.out"], - ["d_3_at_max.out","d_1_am__U479.in1"], - ["d_1_next_value.sel","d_1_am__U479.out"], + ["true.out","d_1_am__U395.in0"], + ["d_2_at_max.out","d_1_am__U395.in1"], + ["d_1_am__U396.in0","d_1_am__U395.out"], + ["d_3_at_max.out","d_1_am__U396.in1"], + ["d_1_next_value.sel","d_1_am__U396.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3120,9 +2854,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U480.in0"], - ["d_3_at_max.out","d_2_am__U480.in1"], - ["d_2_next_value.sel","d_2_am__U480.out"], + ["true.out","d_2_am__U397.in0"], + ["d_3_at_max.out","d_2_am__U397.in1"], + ["d_2_next_value.sel","d_2_am__U397.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3150,7 +2884,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3158,18 +2892,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U77":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U78":{ + "_U69":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U57" + "modref":"global.aff__U48" }, "cmp_time":{ "genref":"coreir.eq", @@ -3179,19 +2913,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U79":{ + "d_0_am__U70":{ "modref":"corebit.and" }, - "d_0_am__U80":{ + "d_0_am__U71":{ "modref":"corebit.and" }, - "d_0_am__U81":{ + "d_0_am__U72":{ "modref":"corebit.and" }, - "d_0_am__U82":{ + "d_0_am__U73":{ "modref":"corebit.and" }, - "d_0_am__U83":{ + "d_0_am__U74":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3225,16 +2959,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U84":{ + "d_1_am__U75":{ "modref":"corebit.and" }, - "d_1_am__U85":{ + "d_1_am__U76":{ "modref":"corebit.and" }, - "d_1_am__U86":{ + "d_1_am__U77":{ "modref":"corebit.and" }, - "d_1_am__U87":{ + "d_1_am__U78":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -3268,13 +3002,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U88":{ + "d_2_am__U79":{ "modref":"corebit.and" }, - "d_2_am__U89":{ + "d_2_am__U80":{ "modref":"corebit.and" }, - "d_2_am__U90":{ + "d_2_am__U81":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -3308,10 +3042,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U91":{ + "d_3_am__U82":{ "modref":"corebit.and" }, - "d_3_am__U92":{ + "d_3_am__U83":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -3345,7 +3079,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U93":{ + "d_4_am__U84":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -3420,13 +3154,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U77.out"], - ["d_1_inc.in1","_U77.out"], - ["d_2_inc.in1","_U77.out"], - ["d_3_inc.in1","_U77.out"], - ["d_4_inc.in1","_U77.out"], - ["d_5_inc.in1","_U77.out"], - ["cmp_time.in1","_U78.out"], + ["d_0_inc.in1","_U68.out"], + ["d_1_inc.in1","_U68.out"], + ["d_2_inc.in1","_U68.out"], + ["d_3_inc.in1","_U68.out"], + ["d_4_inc.in1","_U68.out"], + ["d_5_inc.in1","_U68.out"], + ["cmp_time.in1","_U69.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3445,17 +3179,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U79.in0"], - ["d_1_at_max.out","d_0_am__U79.in1"], - ["d_0_am__U80.in0","d_0_am__U79.out"], - ["d_2_at_max.out","d_0_am__U80.in1"], - ["d_0_am__U81.in0","d_0_am__U80.out"], - ["d_3_at_max.out","d_0_am__U81.in1"], - ["d_0_am__U82.in0","d_0_am__U81.out"], - ["d_4_at_max.out","d_0_am__U82.in1"], - ["d_0_am__U83.in0","d_0_am__U82.out"], - ["d_5_at_max.out","d_0_am__U83.in1"], - ["d_0_next_value.sel","d_0_am__U83.out"], + ["true.out","d_0_am__U70.in0"], + ["d_1_at_max.out","d_0_am__U70.in1"], + ["d_0_am__U71.in0","d_0_am__U70.out"], + ["d_2_at_max.out","d_0_am__U71.in1"], + ["d_0_am__U72.in0","d_0_am__U71.out"], + ["d_3_at_max.out","d_0_am__U72.in1"], + ["d_0_am__U73.in0","d_0_am__U72.out"], + ["d_4_at_max.out","d_0_am__U73.in1"], + ["d_0_am__U74.in0","d_0_am__U73.out"], + ["d_5_at_max.out","d_0_am__U74.in1"], + ["d_0_next_value.sel","d_0_am__U74.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3468,15 +3202,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U84.in0"], - ["d_2_at_max.out","d_1_am__U84.in1"], - ["d_1_am__U85.in0","d_1_am__U84.out"], - ["d_3_at_max.out","d_1_am__U85.in1"], - ["d_1_am__U86.in0","d_1_am__U85.out"], - ["d_4_at_max.out","d_1_am__U86.in1"], - ["d_1_am__U87.in0","d_1_am__U86.out"], - ["d_5_at_max.out","d_1_am__U87.in1"], - ["d_1_next_value.sel","d_1_am__U87.out"], + ["true.out","d_1_am__U75.in0"], + ["d_2_at_max.out","d_1_am__U75.in1"], + ["d_1_am__U76.in0","d_1_am__U75.out"], + ["d_3_at_max.out","d_1_am__U76.in1"], + ["d_1_am__U77.in0","d_1_am__U76.out"], + ["d_4_at_max.out","d_1_am__U77.in1"], + ["d_1_am__U78.in0","d_1_am__U77.out"], + ["d_5_at_max.out","d_1_am__U78.in1"], + ["d_1_next_value.sel","d_1_am__U78.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3489,13 +3223,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U88.in0"], - ["d_3_at_max.out","d_2_am__U88.in1"], - ["d_2_am__U89.in0","d_2_am__U88.out"], - ["d_4_at_max.out","d_2_am__U89.in1"], - ["d_2_am__U90.in0","d_2_am__U89.out"], - ["d_5_at_max.out","d_2_am__U90.in1"], - ["d_2_next_value.sel","d_2_am__U90.out"], + ["true.out","d_2_am__U79.in0"], + ["d_3_at_max.out","d_2_am__U79.in1"], + ["d_2_am__U80.in0","d_2_am__U79.out"], + ["d_4_at_max.out","d_2_am__U80.in1"], + ["d_2_am__U81.in0","d_2_am__U80.out"], + ["d_5_at_max.out","d_2_am__U81.in1"], + ["d_2_next_value.sel","d_2_am__U81.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3508,11 +3242,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U91.in0"], - ["d_4_at_max.out","d_3_am__U91.in1"], - ["d_3_am__U92.in0","d_3_am__U91.out"], - ["d_5_at_max.out","d_3_am__U92.in1"], - ["d_3_next_value.sel","d_3_am__U92.out"], + ["true.out","d_3_am__U82.in0"], + ["d_4_at_max.out","d_3_am__U82.in1"], + ["d_3_am__U83.in0","d_3_am__U82.out"], + ["d_5_at_max.out","d_3_am__U83.in1"], + ["d_3_next_value.sel","d_3_am__U83.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3525,9 +3259,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U93.in0"], - ["d_5_at_max.out","d_4_am__U93.in1"], - ["d_4_next_value.sel","d_4_am__U93.out"], + ["true.out","d_4_am__U84.in0"], + ["d_5_at_max.out","d_4_am__U84.in1"], + ["d_4_next_value.sel","d_4_am__U84.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3555,6 +3289,272 @@ ["self.d.5","d_5_reg.out"] ] }, + "affine_controller__U8":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",4,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U9" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U25":{ + "modref":"corebit.and" + }, + "d_0_am__U26":{ + "modref":"corebit.and" + }, + "d_0_am__U27":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U28":{ + "modref":"corebit.and" + }, + "d_1_am__U29":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_am__U30":{ + "modref":"corebit.and" + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U23.out"], + ["d_2_inc.in1","_U23.out"], + ["d_3_inc.in1","_U23.out"], + ["cmp_time.in1","_U24.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U25.in0"], + ["d_1_at_max.out","d_0_am__U25.in1"], + ["d_0_am__U26.in0","d_0_am__U25.out"], + ["d_2_at_max.out","d_0_am__U26.in1"], + ["d_0_am__U27.in0","d_0_am__U26.out"], + ["d_3_at_max.out","d_0_am__U27.in1"], + ["d_0_next_value.sel","d_0_am__U27.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U28.in0"], + ["d_2_at_max.out","d_1_am__U28.in1"], + ["d_1_am__U29.in0","d_1_am__U28.out"], + ["d_3_at_max.out","d_1_am__U29.in1"], + ["d_1_next_value.sel","d_1_am__U29.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U30.in0"], + ["d_3_at_max.out","d_2_am__U30.in1"], + ["d_2_next_value.sel","d_2_am__U30.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] + ] + }, "cu_op_hcompute_hw_output_stencil":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], @@ -5172,42 +5172,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -5215,8 +5183,8 @@ }, "ub_input_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -5224,8 +5192,8 @@ }, "ub_input_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -5233,8 +5201,8 @@ }, "ub_input_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -5242,8 +5210,8 @@ }, "ub_input_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -5251,8 +5219,8 @@ }, "ub_input_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11517],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11517],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -5260,8 +5228,8 @@ }, "ub_input_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -5269,8 +5237,8 @@ }, "ub_input_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9248],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9248],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -5278,14 +5246,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_input_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U11.out"], - ["ub_input_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U13.out"], - ["ub_input_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U15.out"], - ["ub_input_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_input_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], - ["ub_input_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U7.out"], - ["ub_input_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U9.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_1.clk","self.clk"], ["ub_input_cgra_stencil_BANK_2.clk","self.clk"], @@ -5403,42 +5363,42 @@ ["op_hcompute_input_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U115":{ - "modref":"global.aff__U95" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U106":{ + "modref":"global.aff__U86" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55":{ - "modref":"global.aff__U41" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46":{ + "modref":"global.aff__U32" }, - "chain_en_const_U116":{ + "chain_en_const_U107":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U40":{ - "modref":"global.affine_controller__U17", + "ctrl__U31":{ + "modref":"global.affine_controller__U8", "metadata":{"garnet_remove":true} }, - "ctrl__U94":{ - "modref":"global.affine_controller__U56", + "ctrl__U85":{ + "modref":"global.affine_controller__U47", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,8064,16128],"dimensionality":4,"extent":[8,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,8,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[4096],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U16"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,8064,16128],"dimensionality":4,"extent":[8,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,8,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[4096],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U94.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U115.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U115.out"], - ["ctrl__U40.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U116.out"], - ["self.clk","ctrl__U40.clk"], - ["self.reset","ctrl__U40.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U40.valid"], - ["self.clk","ctrl__U94.clk"], - ["self.reset","ctrl__U94.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U94.valid"], + ["ctrl__U85.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U106.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U106.out"], + ["ctrl__U31.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U107.out"], + ["self.clk","ctrl__U31.clk"], + ["self.reset","ctrl__U31.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U31.valid"], + ["self.clk","ctrl__U85.clk"], + ["self.reset","ctrl__U85.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U85.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_glb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_input_cgra_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -5470,266 +5430,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U118":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U120":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U122":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U124":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U126":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U128":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U130":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U136":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U138":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U140":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U142":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U144":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U146":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U148":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U150":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U152":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U154":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U156":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U158":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U160":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U164":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U166":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U168":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U170":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U172":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U174":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U176":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U178":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U180":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U182":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U184":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U186":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U188":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U190":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U194":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U196":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U198":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U200":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U202":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U204":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U206":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U208":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U210":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U212":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U214":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U216":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U218":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U220":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U222":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U224":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U226":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U228":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U230":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U232":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U234":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U236":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U238":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U240":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U242":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U244":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9409],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U117"} + "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9409],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -5737,13 +5441,13 @@ }, "ub_kernel_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9417],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U119"} + "genargs":{"ID":["String","_U109"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9417],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9426],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U137"} + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9426],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -5751,8 +5455,8 @@ }, "ub_kernel_cgra_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9434],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U139"} + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9434],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -5760,8 +5464,8 @@ }, "ub_kernel_cgra_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9442],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9249],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U141"} + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9442],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9249],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -5769,8 +5473,8 @@ }, "ub_kernel_cgra_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9450],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9257],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U143"} + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9450],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9257],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -5778,8 +5482,8 @@ }, "ub_kernel_cgra_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9458],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9265],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U145"} + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9458],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9265],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -5787,8 +5491,8 @@ }, "ub_kernel_cgra_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9466],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9273],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U147"} + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9466],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9273],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -5796,8 +5500,8 @@ }, "ub_kernel_cgra_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9411],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U149"} + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9411],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -5805,8 +5509,8 @@ }, "ub_kernel_cgra_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9419],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U151"} + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9419],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -5814,8 +5518,8 @@ }, "ub_kernel_cgra_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9427],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U153"} + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9427],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -5823,8 +5527,8 @@ }, "ub_kernel_cgra_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9435],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U155"} + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9435],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -5836,13 +5540,13 @@ }, "ub_kernel_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9425],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U121"} + "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9425],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9443],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9250],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U157"} + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9443],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9250],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -5850,8 +5554,8 @@ }, "ub_kernel_cgra_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9451],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9258],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U159"} + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9451],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9258],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -5859,8 +5563,8 @@ }, "ub_kernel_cgra_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9459],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9266],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U161"} + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9459],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9266],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -5868,8 +5572,8 @@ }, "ub_kernel_cgra_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9467],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9274],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U163"} + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9467],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9274],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -5877,8 +5581,8 @@ }, "ub_kernel_cgra_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9412],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U165"} + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9412],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -5886,8 +5590,8 @@ }, "ub_kernel_cgra_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9420],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U167"} + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9420],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -5895,8 +5599,8 @@ }, "ub_kernel_cgra_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9428],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U169"} + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9428],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -5904,8 +5608,8 @@ }, "ub_kernel_cgra_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9436],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U171"} + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9436],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -5913,8 +5617,8 @@ }, "ub_kernel_cgra_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9444],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9251],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U173"} + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9444],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9251],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -5922,8 +5626,8 @@ }, "ub_kernel_cgra_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9452],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9259],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U175"} + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9452],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9259],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -5935,13 +5639,13 @@ }, "ub_kernel_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9433],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U123"} + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9433],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9460],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9267],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U177"} + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9460],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9267],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -5949,8 +5653,8 @@ }, "ub_kernel_cgra_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9468],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9275],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U179"} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9468],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9275],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -5958,8 +5662,8 @@ }, "ub_kernel_cgra_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9413],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U181"} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9413],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -5967,8 +5671,8 @@ }, "ub_kernel_cgra_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9421],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U183"} + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9421],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -5976,8 +5680,8 @@ }, "ub_kernel_cgra_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9429],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U185"} + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9429],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -5985,8 +5689,8 @@ }, "ub_kernel_cgra_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9437],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U187"} + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9437],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -5994,8 +5698,8 @@ }, "ub_kernel_cgra_stencil_BANK_36":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9445],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9252],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U189"} + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9445],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9252],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const":{ "modref":"corebit.const", @@ -6003,8 +5707,8 @@ }, "ub_kernel_cgra_stencil_BANK_37":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9453],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9260],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U191"} + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9453],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9260],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const":{ "modref":"corebit.const", @@ -6012,8 +5716,8 @@ }, "ub_kernel_cgra_stencil_BANK_38":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9461],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9268],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U193"} + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9461],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9268],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const":{ "modref":"corebit.const", @@ -6021,8 +5725,8 @@ }, "ub_kernel_cgra_stencil_BANK_39":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9469],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9276],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U195"} + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9469],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9276],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const":{ "modref":"corebit.const", @@ -6034,13 +5738,13 @@ }, "ub_kernel_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9441],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9248],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U125"} + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9441],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9248],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U197"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9414],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U197"} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9414],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const":{ "modref":"corebit.const", @@ -6048,8 +5752,8 @@ }, "ub_kernel_cgra_stencil_BANK_41":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U199"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9422],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U199"} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9422],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const":{ "modref":"corebit.const", @@ -6057,8 +5761,8 @@ }, "ub_kernel_cgra_stencil_BANK_42":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U201"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9430],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U201"} + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9430],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const":{ "modref":"corebit.const", @@ -6066,8 +5770,8 @@ }, "ub_kernel_cgra_stencil_BANK_43":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U203"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9438],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U203"} + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9438],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const":{ "modref":"corebit.const", @@ -6075,8 +5779,8 @@ }, "ub_kernel_cgra_stencil_BANK_44":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U205"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9446],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9253],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U205"} + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9446],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9253],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const":{ "modref":"corebit.const", @@ -6084,8 +5788,8 @@ }, "ub_kernel_cgra_stencil_BANK_45":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U207"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9454],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9261],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U207"} + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9454],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9261],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const":{ "modref":"corebit.const", @@ -6093,8 +5797,8 @@ }, "ub_kernel_cgra_stencil_BANK_46":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9462],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9269],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U209"} + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9462],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9269],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const":{ "modref":"corebit.const", @@ -6102,8 +5806,8 @@ }, "ub_kernel_cgra_stencil_BANK_47":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9470],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9277],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U211"} + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9470],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9277],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const":{ "modref":"corebit.const", @@ -6111,8 +5815,8 @@ }, "ub_kernel_cgra_stencil_BANK_48":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9415],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U213"} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9415],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const":{ "modref":"corebit.const", @@ -6120,8 +5824,8 @@ }, "ub_kernel_cgra_stencil_BANK_49":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9423],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U215"} + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9423],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const":{ "modref":"corebit.const", @@ -6133,13 +5837,13 @@ }, "ub_kernel_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9449],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9256],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U127"} + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9449],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9256],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9431],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U217"} + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9431],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const":{ "modref":"corebit.const", @@ -6147,8 +5851,8 @@ }, "ub_kernel_cgra_stencil_BANK_51":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9439],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U219"} + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9439],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const":{ "modref":"corebit.const", @@ -6156,8 +5860,8 @@ }, "ub_kernel_cgra_stencil_BANK_52":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9447],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9254],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U221"} + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9447],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9254],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const":{ "modref":"corebit.const", @@ -6165,8 +5869,8 @@ }, "ub_kernel_cgra_stencil_BANK_53":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9455],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9262],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U223"} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9455],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9262],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const":{ "modref":"corebit.const", @@ -6174,8 +5878,8 @@ }, "ub_kernel_cgra_stencil_BANK_54":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9463],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9270],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U225"} + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9463],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9270],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const":{ "modref":"corebit.const", @@ -6183,8 +5887,8 @@ }, "ub_kernel_cgra_stencil_BANK_55":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9471],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9278],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U227"} + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9471],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9278],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const":{ "modref":"corebit.const", @@ -6192,8 +5896,8 @@ }, "ub_kernel_cgra_stencil_BANK_56":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9416],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U229"} + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9416],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const":{ "modref":"corebit.const", @@ -6201,8 +5905,8 @@ }, "ub_kernel_cgra_stencil_BANK_57":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9424],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U231"} + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9424],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const":{ "modref":"corebit.const", @@ -6210,8 +5914,8 @@ }, "ub_kernel_cgra_stencil_BANK_58":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9432],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U233"} + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9432],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const":{ "modref":"corebit.const", @@ -6219,8 +5923,8 @@ }, "ub_kernel_cgra_stencil_BANK_59":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9440],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U235"} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9440],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const":{ "modref":"corebit.const", @@ -6232,13 +5936,13 @@ }, "ub_kernel_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9457],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9264],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U129"} + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9457],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9264],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9448],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9255],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U237"} + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9448],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9255],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const":{ "modref":"corebit.const", @@ -6246,8 +5950,8 @@ }, "ub_kernel_cgra_stencil_BANK_61":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9456],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9263],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U239"} + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9456],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9263],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const":{ "modref":"corebit.const", @@ -6255,8 +5959,8 @@ }, "ub_kernel_cgra_stencil_BANK_62":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9464],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9271],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U241"} + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9464],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9271],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const":{ "modref":"corebit.const", @@ -6264,8 +5968,8 @@ }, "ub_kernel_cgra_stencil_BANK_63":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9472],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9279],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U243"} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9472],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9279],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const":{ "modref":"corebit.const", @@ -6277,8 +5981,8 @@ }, "ub_kernel_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9465],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9272],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U131"} + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9465],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9272],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -6286,8 +5990,8 @@ }, "ub_kernel_cgra_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9410],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U133"} + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9410],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -6295,8 +5999,8 @@ }, "ub_kernel_cgra_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9418],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U135"} + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9418],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11525],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -6304,70 +6008,6 @@ } }, "connections":[ - ["ub_kernel_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U118.out"], - ["ub_kernel_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U120.out"], - ["ub_kernel_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U122.out"], - ["ub_kernel_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U124.out"], - ["ub_kernel_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U126.out"], - ["ub_kernel_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U128.out"], - ["ub_kernel_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U130.out"], - ["ub_kernel_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U132.out"], - ["ub_kernel_cgra_stencil_BANK_8.chain_chain_en","chain_en_const_U134.out"], - ["ub_kernel_cgra_stencil_BANK_9.chain_chain_en","chain_en_const_U136.out"], - ["ub_kernel_cgra_stencil_BANK_10.chain_chain_en","chain_en_const_U138.out"], - ["ub_kernel_cgra_stencil_BANK_11.chain_chain_en","chain_en_const_U140.out"], - ["ub_kernel_cgra_stencil_BANK_12.chain_chain_en","chain_en_const_U142.out"], - ["ub_kernel_cgra_stencil_BANK_13.chain_chain_en","chain_en_const_U144.out"], - ["ub_kernel_cgra_stencil_BANK_14.chain_chain_en","chain_en_const_U146.out"], - ["ub_kernel_cgra_stencil_BANK_15.chain_chain_en","chain_en_const_U148.out"], - ["ub_kernel_cgra_stencil_BANK_16.chain_chain_en","chain_en_const_U150.out"], - ["ub_kernel_cgra_stencil_BANK_17.chain_chain_en","chain_en_const_U152.out"], - ["ub_kernel_cgra_stencil_BANK_18.chain_chain_en","chain_en_const_U154.out"], - ["ub_kernel_cgra_stencil_BANK_19.chain_chain_en","chain_en_const_U156.out"], - ["ub_kernel_cgra_stencil_BANK_20.chain_chain_en","chain_en_const_U158.out"], - ["ub_kernel_cgra_stencil_BANK_21.chain_chain_en","chain_en_const_U160.out"], - ["ub_kernel_cgra_stencil_BANK_22.chain_chain_en","chain_en_const_U162.out"], - ["ub_kernel_cgra_stencil_BANK_23.chain_chain_en","chain_en_const_U164.out"], - ["ub_kernel_cgra_stencil_BANK_24.chain_chain_en","chain_en_const_U166.out"], - ["ub_kernel_cgra_stencil_BANK_25.chain_chain_en","chain_en_const_U168.out"], - ["ub_kernel_cgra_stencil_BANK_26.chain_chain_en","chain_en_const_U170.out"], - ["ub_kernel_cgra_stencil_BANK_27.chain_chain_en","chain_en_const_U172.out"], - ["ub_kernel_cgra_stencil_BANK_28.chain_chain_en","chain_en_const_U174.out"], - ["ub_kernel_cgra_stencil_BANK_29.chain_chain_en","chain_en_const_U176.out"], - ["ub_kernel_cgra_stencil_BANK_30.chain_chain_en","chain_en_const_U178.out"], - ["ub_kernel_cgra_stencil_BANK_31.chain_chain_en","chain_en_const_U180.out"], - ["ub_kernel_cgra_stencil_BANK_32.chain_chain_en","chain_en_const_U182.out"], - ["ub_kernel_cgra_stencil_BANK_33.chain_chain_en","chain_en_const_U184.out"], - ["ub_kernel_cgra_stencil_BANK_34.chain_chain_en","chain_en_const_U186.out"], - ["ub_kernel_cgra_stencil_BANK_35.chain_chain_en","chain_en_const_U188.out"], - ["ub_kernel_cgra_stencil_BANK_36.chain_chain_en","chain_en_const_U190.out"], - ["ub_kernel_cgra_stencil_BANK_37.chain_chain_en","chain_en_const_U192.out"], - ["ub_kernel_cgra_stencil_BANK_38.chain_chain_en","chain_en_const_U194.out"], - ["ub_kernel_cgra_stencil_BANK_39.chain_chain_en","chain_en_const_U196.out"], - ["ub_kernel_cgra_stencil_BANK_40.chain_chain_en","chain_en_const_U198.out"], - ["ub_kernel_cgra_stencil_BANK_41.chain_chain_en","chain_en_const_U200.out"], - ["ub_kernel_cgra_stencil_BANK_42.chain_chain_en","chain_en_const_U202.out"], - ["ub_kernel_cgra_stencil_BANK_43.chain_chain_en","chain_en_const_U204.out"], - ["ub_kernel_cgra_stencil_BANK_44.chain_chain_en","chain_en_const_U206.out"], - ["ub_kernel_cgra_stencil_BANK_45.chain_chain_en","chain_en_const_U208.out"], - ["ub_kernel_cgra_stencil_BANK_46.chain_chain_en","chain_en_const_U210.out"], - ["ub_kernel_cgra_stencil_BANK_47.chain_chain_en","chain_en_const_U212.out"], - ["ub_kernel_cgra_stencil_BANK_48.chain_chain_en","chain_en_const_U214.out"], - ["ub_kernel_cgra_stencil_BANK_49.chain_chain_en","chain_en_const_U216.out"], - ["ub_kernel_cgra_stencil_BANK_50.chain_chain_en","chain_en_const_U218.out"], - ["ub_kernel_cgra_stencil_BANK_51.chain_chain_en","chain_en_const_U220.out"], - ["ub_kernel_cgra_stencil_BANK_52.chain_chain_en","chain_en_const_U222.out"], - ["ub_kernel_cgra_stencil_BANK_53.chain_chain_en","chain_en_const_U224.out"], - ["ub_kernel_cgra_stencil_BANK_54.chain_chain_en","chain_en_const_U226.out"], - ["ub_kernel_cgra_stencil_BANK_55.chain_chain_en","chain_en_const_U228.out"], - ["ub_kernel_cgra_stencil_BANK_56.chain_chain_en","chain_en_const_U230.out"], - ["ub_kernel_cgra_stencil_BANK_57.chain_chain_en","chain_en_const_U232.out"], - ["ub_kernel_cgra_stencil_BANK_58.chain_chain_en","chain_en_const_U234.out"], - ["ub_kernel_cgra_stencil_BANK_59.chain_chain_en","chain_en_const_U236.out"], - ["ub_kernel_cgra_stencil_BANK_60.chain_chain_en","chain_en_const_U238.out"], - ["ub_kernel_cgra_stencil_BANK_61.chain_chain_en","chain_en_const_U240.out"], - ["ub_kernel_cgra_stencil_BANK_62.chain_chain_en","chain_en_const_U242.out"], - ["ub_kernel_cgra_stencil_BANK_63.chain_chain_en","chain_en_const_U244.out"], ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_1.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_10.clk","self.clk"], @@ -6765,49 +6405,49 @@ ["op_hcompute_kernel_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U379":{ - "modref":"global.aff__U353" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U305":{ + "modref":"global.aff__U279" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U294":{ - "modref":"global.aff__U277" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U220":{ + "modref":"global.aff__U203" }, - "chain_en_const_U380":{ + "chain_en_const_U306":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U276":{ - "modref":"global.affine_controller__U246", + "ctrl__U202":{ + "modref":"global.affine_controller__U172", "metadata":{"garnet_remove":true} }, - "ctrl__U352":{ - "modref":"global.affine_controller__U295", + "ctrl__U278":{ + "modref":"global.affine_controller__U221", "metadata":{"garnet_remove":true} }, "kernel_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,256,8064,16128],"dimensionality":5,"extent":[8,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,1024,8,512]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9216],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U245"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,256,8064,16128],"dimensionality":5,"extent":[8,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,1024,8,512]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9216],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U352.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U379.d"], - ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U379.out"], - ["ctrl__U276.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U294.d"], - ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U294.out"], - ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U380.out"], - ["self.clk","ctrl__U276.clk"], - ["self.reset","ctrl__U276.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U276.valid"], - ["self.clk","ctrl__U352.clk"], - ["self.reset","ctrl__U352.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U352.valid"], + ["ctrl__U278.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U305.d"], + ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U305.out"], + ["ctrl__U202.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U220.d"], + ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U220.out"], + ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U306.out"], + ["self.clk","ctrl__U202.clk"], + ["self.reset","ctrl__U202.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U202.valid"], + ["self.clk","ctrl__U278.clk"], + ["self.reset","ctrl__U278.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U278.valid"], ["self.clk","kernel_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_kernel_glb_stencil_write.0","kernel_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_kernel_cgra_stencil_read.0","kernel_glb_stencil_BANK_0_ubuf.data_out_0"], ["self.reset","kernel_glb_stencil_BANK_0_ubuf.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U500":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U417":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6816,7 +6456,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U499":{ + "op_hcompute_hw_output_stencil_read_start_pt__U416":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6825,7 +6465,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U501":{ + "op_hcompute_hw_output_stencil_write_start_pt__U418":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6834,7 +6474,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U509":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U426":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6843,7 +6483,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U508":{ + "op_hcompute_input_glb_stencil_read_start_pt__U425":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6852,7 +6492,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U510":{ + "op_hcompute_input_glb_stencil_write_start_pt__U427":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6861,7 +6501,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U504":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U421":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6870,7 +6510,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U503":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U420":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6879,7 +6519,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U505":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U422":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6945,42 +6585,10 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U384":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U386":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U388":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U390":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U392":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U394":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U396":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U381"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27645],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27648],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U381"} + "genargs":{"ID":["String","_U307"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27645],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27648],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -6988,8 +6596,8 @@ }, "ub_output_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9220],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[11533],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27647],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27649],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U383"} + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9220],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[11533],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27647],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27649],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -6997,8 +6605,8 @@ }, "ub_output_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U385"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27647],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27650],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U385"} + "genargs":{"ID":["String","_U309"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27647],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27650],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -7006,8 +6614,8 @@ }, "ub_output_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U387"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27649],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27651],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U387"} + "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27649],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27651],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -7015,8 +6623,8 @@ }, "ub_output_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27649],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27652],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U389"} + "genargs":{"ID":["String","_U311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27649],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27652],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -7024,8 +6632,8 @@ }, "ub_output_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U391"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27651],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27653],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U391"} + "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27651],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27653],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -7033,8 +6641,8 @@ }, "ub_output_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U393"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27651],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27654],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U393"} + "genargs":{"ID":["String","_U313"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27651],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27654],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -7042,8 +6650,8 @@ }, "ub_output_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U395"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27653],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27655],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U395"} + "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11532],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[11526],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[27653],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[11528],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[27655],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -7051,14 +6659,6 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U382.out"], - ["ub_output_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U384.out"], - ["ub_output_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U386.out"], - ["ub_output_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U388.out"], - ["ub_output_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U390.out"], - ["ub_output_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U392.out"], - ["ub_output_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U394.out"], - ["ub_output_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U396.out"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], @@ -7136,42 +6736,42 @@ ["op_hcompute_output_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U496":{ - "modref":"global.aff__U482" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U413":{ + "modref":"global.aff__U399" }, - "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U457":{ - "modref":"global.aff__U437" + "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U374":{ + "modref":"global.aff__U354" }, - "chain_en_const_U497":{ + "chain_en_const_U414":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U436":{ - "modref":"global.affine_controller__U398", + "ctrl__U353":{ + "modref":"global.affine_controller__U315", "metadata":{"garnet_remove":true} }, - "ctrl__U481":{ - "modref":"global.affine_controller__U458", + "ctrl__U398":{ + "modref":"global.affine_controller__U375", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[50048],"cycle_stride":[1],"dimensionality":1,"extent":[50176],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[27648],"cycle_stride":[1,32,16128],"dimensionality":3,"extent":[32,196,2],"write_data_starting_addr":[0],"write_data_stride":[1,256,32]}},"mode":"glb","verilog_name":"glb__U397"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[50048],"cycle_stride":[1],"dimensionality":1,"extent":[50176],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[27648],"cycle_stride":[1,32,16128],"dimensionality":3,"extent":[32,196,2],"write_data_starting_addr":[0],"write_data_stride":[1,256,32]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U481.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U496.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U496.out"], - ["ctrl__U436.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U457.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U457.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U497.out"], - ["self.clk","ctrl__U436.clk"], - ["self.reset","ctrl__U436.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U436.valid"], - ["self.clk","ctrl__U481.clk"], - ["self.reset","ctrl__U481.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U481.valid"], + ["ctrl__U398.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U413.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U413.out"], + ["ctrl__U353.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U374.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U374.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U414.out"], + ["self.clk","ctrl__U353.clk"], + ["self.reset","ctrl__U353.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U353.valid"], + ["self.clk","ctrl__U398.clk"], + ["self.reset","ctrl__U398.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U398.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_glb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -7190,12 +6790,12 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U506":{ + "_U423":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U511":{ + "_U428":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -7216,22 +6816,22 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U500" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U417" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U498"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[50048],"cycle_stride":[1,256,3584],"dimensionality":3,"extent":[256,14,14]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U498"} + "genargs":{"ID":["String","_U415"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[50048],"cycle_stride":[1,256,3584],"dimensionality":3,"extent":[256,14,14]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U499" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U416" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U501" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U418" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" @@ -7240,22 +6840,22 @@ "modref":"global.cu_op_hcompute_input_glb_stencil" }, "op_hcompute_input_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U509" + "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U426" }, "op_hcompute_input_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U507"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,256],"dimensionality":3,"extent":[16,16,16]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U507"} + "genargs":{"ID":["String","_U424"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,256],"dimensionality":3,"extent":[16,16,16]}},"mode":"lake"} }, "op_hcompute_input_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_glb_stencil_read_start":{ - "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U508" + "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U425" }, "op_hcompute_input_glb_stencil_write_start":{ - "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U510" + "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U427" }, "op_hcompute_kernel_cgra_stencil":{ "modref":"global.cu_op_hcompute_kernel_cgra_stencil" @@ -7264,22 +6864,22 @@ "modref":"global.cu_op_hcompute_kernel_glb_stencil" }, "op_hcompute_kernel_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U504" + "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U421" }, "op_hcompute_kernel_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U502"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,1024,3072],"dimensionality":4,"extent":[16,64,3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U502"} + "genargs":{"ID":["String","_U419"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,1024,3072],"dimensionality":4,"extent":[16,64,3,3]}},"mode":"lake"} }, "op_hcompute_kernel_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_kernel_glb_stencil_read_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U503" + "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U420" }, "op_hcompute_kernel_glb_stencil_write_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U505" + "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U422" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -7340,10 +6940,10 @@ } }, "connections":[ - ["self.clk","_U506.clk"], - ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U506.in"], - ["self.clk","_U511.clk"], - ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U511.in"], + ["self.clk","_U423.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U423.in"], + ["self.clk","_U428.clk"], + ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U428.in"], ["self.clk","input_cgra_stencil.clk"], ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], ["op_hcompute_output_cgra_stencil_10.input_cgra_stencil_op_hcompute_output_cgra_stencil_10_read","input_cgra_stencil.op_hcompute_output_cgra_stencil_10_read"], diff --git a/aha_garnet_design_new/resnet4_x/resnet4_x_garnet.json b/aha_garnet_design_new/resnet4_x/resnet4_x_garnet.json index b461b0041..237d45360 100644 --- a/aha_garnet_design_new/resnet4_x/resnet4_x_garnet.json +++ b/aha_garnet_design_new/resnet4_x/resnet4_x_garnet.json @@ -232,1407 +232,1425 @@ }, "global":{ "modules":{ - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U247":{ + "aff__U173":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U259":{ + "add_all__U185":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U260":{ + "add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U261":{ + "add_all__U187":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U262":{ + "add_all__U188":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U263":{ + "add_all__U189":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U248":{ + "coeff_0_U174":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U250":{ + "coeff_1_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U252":{ + "coeff_2_U178":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U254":{ + "coeff_3_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U256":{ + "coeff_4_U182":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U258":{ + "const_term_U184":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U249":{ + "mul_d0__U175":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U251":{ + "mul_d1__U177":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U253":{ + "mul_d2__U179":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U255":{ + "mul_d3__U181":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U257":{ + "mul_d4__U183":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U249.out","add_all__U259.in0"], - ["mul_d1__U251.out","add_all__U259.in1"], - ["add_all__U260.in0","add_all__U259.out"], - ["mul_d2__U253.out","add_all__U260.in1"], - ["add_all__U261.in0","add_all__U260.out"], - ["mul_d3__U255.out","add_all__U261.in1"], - ["add_all__U262.in0","add_all__U261.out"], - ["mul_d4__U257.out","add_all__U262.in1"], - ["add_all__U263.in0","add_all__U262.out"], - ["const_term_U258.out","add_all__U263.in1"], - ["self.out","add_all__U263.out"], - ["mul_d0__U249.in0","coeff_0_U248.out"], - ["mul_d1__U251.in0","coeff_1_U250.out"], - ["mul_d2__U253.in0","coeff_2_U252.out"], - ["mul_d3__U255.in0","coeff_3_U254.out"], - ["mul_d4__U257.in0","coeff_4_U256.out"], - ["self.d.0","mul_d0__U249.in1"], - ["self.d.1","mul_d1__U251.in1"], - ["self.d.2","mul_d2__U253.in1"], - ["self.d.3","mul_d3__U255.in1"], - ["self.d.4","mul_d4__U257.in1"] + ["mul_d0__U175.out","add_all__U185.in0"], + ["mul_d1__U177.out","add_all__U185.in1"], + ["add_all__U186.in0","add_all__U185.out"], + ["mul_d2__U179.out","add_all__U186.in1"], + ["add_all__U187.in0","add_all__U186.out"], + ["mul_d3__U181.out","add_all__U187.in1"], + ["add_all__U188.in0","add_all__U187.out"], + ["mul_d4__U183.out","add_all__U188.in1"], + ["add_all__U189.in0","add_all__U188.out"], + ["const_term_U184.out","add_all__U189.in1"], + ["self.out","add_all__U189.out"], + ["mul_d0__U175.in0","coeff_0_U174.out"], + ["mul_d1__U177.in0","coeff_1_U176.out"], + ["mul_d2__U179.in0","coeff_2_U178.out"], + ["mul_d3__U181.in0","coeff_3_U180.out"], + ["mul_d4__U183.in0","coeff_4_U182.out"], + ["self.d.0","mul_d0__U175.in1"], + ["self.d.1","mul_d1__U177.in1"], + ["self.d.2","mul_d2__U179.in1"], + ["self.d.3","mul_d3__U181.in1"], + ["self.d.4","mul_d4__U183.in1"] ] }, - "aff__U277":{ + "aff__U203":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U289":{ + "add_all__U215":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U290":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U291":{ + "add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U292":{ + "add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U293":{ + "add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U278":{ + "coeff_0_U204":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U280":{ + "coeff_1_U206":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U282":{ + "coeff_2_U208":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U284":{ + "coeff_3_U210":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U286":{ + "coeff_4_U212":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U288":{ + "const_term_U214":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U279":{ + "mul_d0__U205":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U281":{ + "mul_d1__U207":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U283":{ + "mul_d2__U209":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U285":{ + "mul_d3__U211":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U287":{ + "mul_d4__U213":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U279.out","add_all__U289.in0"], - ["mul_d1__U281.out","add_all__U289.in1"], - ["add_all__U290.in0","add_all__U289.out"], - ["mul_d2__U283.out","add_all__U290.in1"], - ["add_all__U291.in0","add_all__U290.out"], - ["mul_d3__U285.out","add_all__U291.in1"], - ["add_all__U292.in0","add_all__U291.out"], - ["mul_d4__U287.out","add_all__U292.in1"], - ["add_all__U293.in0","add_all__U292.out"], - ["const_term_U288.out","add_all__U293.in1"], - ["self.out","add_all__U293.out"], - ["mul_d0__U279.in0","coeff_0_U278.out"], - ["mul_d1__U281.in0","coeff_1_U280.out"], - ["mul_d2__U283.in0","coeff_2_U282.out"], - ["mul_d3__U285.in0","coeff_3_U284.out"], - ["mul_d4__U287.in0","coeff_4_U286.out"], - ["self.d.0","mul_d0__U279.in1"], - ["self.d.1","mul_d1__U281.in1"], - ["self.d.2","mul_d2__U283.in1"], - ["self.d.3","mul_d3__U285.in1"], - ["self.d.4","mul_d4__U287.in1"] + ["mul_d0__U205.out","add_all__U215.in0"], + ["mul_d1__U207.out","add_all__U215.in1"], + ["add_all__U216.in0","add_all__U215.out"], + ["mul_d2__U209.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d3__U211.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d4__U213.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["const_term_U214.out","add_all__U219.in1"], + ["self.out","add_all__U219.out"], + ["mul_d0__U205.in0","coeff_0_U204.out"], + ["mul_d1__U207.in0","coeff_1_U206.out"], + ["mul_d2__U209.in0","coeff_2_U208.out"], + ["mul_d3__U211.in0","coeff_3_U210.out"], + ["mul_d4__U213.in0","coeff_4_U212.out"], + ["self.d.0","mul_d0__U205.in1"], + ["self.d.1","mul_d1__U207.in1"], + ["self.d.2","mul_d2__U209.in1"], + ["self.d.3","mul_d3__U211.in1"], + ["self.d.4","mul_d4__U213.in1"] ] }, - "aff__U296":{ + "aff__U222":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U319":{ + "add_all__U245":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U320":{ + "add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U321":{ + "add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U297":{ + "coeff_0_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U299":{ + "coeff_1_U225":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_2_U301":{ + "coeff_2_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_3_U303":{ + "coeff_3_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_4_U305":{ + "coeff_4_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_5_U307":{ + "coeff_5_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_6_U309":{ + "coeff_6_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U311":{ + "coeff_7_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U298":{ + "mul_d0__U224":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U300":{ + "mul_d1__U226":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U302":{ + "mul_d2__U228":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U304":{ + "mul_d3__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U306":{ + "mul_d4__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U308":{ + "mul_d5__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U310":{ + "mul_d6__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U312":{ + "mul_d7__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U298.out","add_all__U314.in0"], - ["mul_d1__U300.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U302.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U304.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U306.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["mul_d5__U308.out","add_all__U318.in1"], - ["add_all__U319.in0","add_all__U318.out"], - ["mul_d6__U310.out","add_all__U319.in1"], - ["add_all__U320.in0","add_all__U319.out"], - ["mul_d7__U312.out","add_all__U320.in1"], - ["add_all__U321.in0","add_all__U320.out"], - ["const_term_U313.out","add_all__U321.in1"], - ["self.out","add_all__U321.out"], - ["mul_d0__U298.in0","coeff_0_U297.out"], - ["mul_d1__U300.in0","coeff_1_U299.out"], - ["mul_d2__U302.in0","coeff_2_U301.out"], - ["mul_d3__U304.in0","coeff_3_U303.out"], - ["mul_d4__U306.in0","coeff_4_U305.out"], - ["mul_d5__U308.in0","coeff_5_U307.out"], - ["mul_d6__U310.in0","coeff_6_U309.out"], - ["mul_d7__U312.in0","coeff_7_U311.out"], - ["self.d.0","mul_d0__U298.in1"], - ["self.d.1","mul_d1__U300.in1"], - ["self.d.2","mul_d2__U302.in1"], - ["self.d.3","mul_d3__U304.in1"], - ["self.d.4","mul_d4__U306.in1"], - ["self.d.5","mul_d5__U308.in1"], - ["self.d.6","mul_d6__U310.in1"], - ["self.d.7","mul_d7__U312.in1"] + ["mul_d0__U224.out","add_all__U240.in0"], + ["mul_d1__U226.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U228.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U230.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U232.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["mul_d5__U234.out","add_all__U244.in1"], + ["add_all__U245.in0","add_all__U244.out"], + ["mul_d6__U236.out","add_all__U245.in1"], + ["add_all__U246.in0","add_all__U245.out"], + ["mul_d7__U238.out","add_all__U246.in1"], + ["add_all__U247.in0","add_all__U246.out"], + ["const_term_U239.out","add_all__U247.in1"], + ["self.out","add_all__U247.out"], + ["mul_d0__U224.in0","coeff_0_U223.out"], + ["mul_d1__U226.in0","coeff_1_U225.out"], + ["mul_d2__U228.in0","coeff_2_U227.out"], + ["mul_d3__U230.in0","coeff_3_U229.out"], + ["mul_d4__U232.in0","coeff_4_U231.out"], + ["mul_d5__U234.in0","coeff_5_U233.out"], + ["mul_d6__U236.in0","coeff_6_U235.out"], + ["mul_d7__U238.in0","coeff_7_U237.out"], + ["self.d.0","mul_d0__U224.in1"], + ["self.d.1","mul_d1__U226.in1"], + ["self.d.2","mul_d2__U228.in1"], + ["self.d.3","mul_d3__U230.in1"], + ["self.d.4","mul_d4__U232.in1"], + ["self.d.5","mul_d5__U234.in1"], + ["self.d.6","mul_d6__U236.in1"], + ["self.d.7","mul_d7__U238.in1"] ] }, - "aff__U353":{ + "aff__U279":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U371":{ + "add_all__U297":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U372":{ + "add_all__U298":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U373":{ + "add_all__U299":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U374":{ + "add_all__U300":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U375":{ + "add_all__U301":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U376":{ + "add_all__U302":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U377":{ + "add_all__U303":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U378":{ + "add_all__U304":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U354":{ + "coeff_0_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U356":{ + "coeff_1_U282":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U358":{ + "coeff_2_U284":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_3_U360":{ + "coeff_3_U286":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U362":{ + "coeff_4_U288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U364":{ + "coeff_5_U290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U366":{ + "coeff_6_U292":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U368":{ + "coeff_7_U294":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U370":{ + "const_term_U296":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U355":{ + "mul_d0__U281":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U357":{ + "mul_d1__U283":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U359":{ + "mul_d2__U285":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U361":{ + "mul_d3__U287":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U363":{ + "mul_d4__U289":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U365":{ + "mul_d5__U291":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U367":{ + "mul_d6__U293":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U369":{ + "mul_d7__U295":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U355.out","add_all__U371.in0"], - ["mul_d1__U357.out","add_all__U371.in1"], - ["add_all__U372.in0","add_all__U371.out"], - ["mul_d2__U359.out","add_all__U372.in1"], - ["add_all__U373.in0","add_all__U372.out"], - ["mul_d3__U361.out","add_all__U373.in1"], - ["add_all__U374.in0","add_all__U373.out"], - ["mul_d4__U363.out","add_all__U374.in1"], - ["add_all__U375.in0","add_all__U374.out"], - ["mul_d5__U365.out","add_all__U375.in1"], - ["add_all__U376.in0","add_all__U375.out"], - ["mul_d6__U367.out","add_all__U376.in1"], - ["add_all__U377.in0","add_all__U376.out"], - ["mul_d7__U369.out","add_all__U377.in1"], - ["add_all__U378.in0","add_all__U377.out"], - ["const_term_U370.out","add_all__U378.in1"], - ["self.out","add_all__U378.out"], - ["mul_d0__U355.in0","coeff_0_U354.out"], - ["mul_d1__U357.in0","coeff_1_U356.out"], - ["mul_d2__U359.in0","coeff_2_U358.out"], - ["mul_d3__U361.in0","coeff_3_U360.out"], - ["mul_d4__U363.in0","coeff_4_U362.out"], - ["mul_d5__U365.in0","coeff_5_U364.out"], - ["mul_d6__U367.in0","coeff_6_U366.out"], - ["mul_d7__U369.in0","coeff_7_U368.out"], - ["self.d.0","mul_d0__U355.in1"], - ["self.d.1","mul_d1__U357.in1"], - ["self.d.2","mul_d2__U359.in1"], - ["self.d.3","mul_d3__U361.in1"], - ["self.d.4","mul_d4__U363.in1"], - ["self.d.5","mul_d5__U365.in1"], - ["self.d.6","mul_d6__U367.in1"], - ["self.d.7","mul_d7__U369.in1"] + ["mul_d0__U281.out","add_all__U297.in0"], + ["mul_d1__U283.out","add_all__U297.in1"], + ["add_all__U298.in0","add_all__U297.out"], + ["mul_d2__U285.out","add_all__U298.in1"], + ["add_all__U299.in0","add_all__U298.out"], + ["mul_d3__U287.out","add_all__U299.in1"], + ["add_all__U300.in0","add_all__U299.out"], + ["mul_d4__U289.out","add_all__U300.in1"], + ["add_all__U301.in0","add_all__U300.out"], + ["mul_d5__U291.out","add_all__U301.in1"], + ["add_all__U302.in0","add_all__U301.out"], + ["mul_d6__U293.out","add_all__U302.in1"], + ["add_all__U303.in0","add_all__U302.out"], + ["mul_d7__U295.out","add_all__U303.in1"], + ["add_all__U304.in0","add_all__U303.out"], + ["const_term_U296.out","add_all__U304.in1"], + ["self.out","add_all__U304.out"], + ["mul_d0__U281.in0","coeff_0_U280.out"], + ["mul_d1__U283.in0","coeff_1_U282.out"], + ["mul_d2__U285.in0","coeff_2_U284.out"], + ["mul_d3__U287.in0","coeff_3_U286.out"], + ["mul_d4__U289.in0","coeff_4_U288.out"], + ["mul_d5__U291.in0","coeff_5_U290.out"], + ["mul_d6__U293.in0","coeff_6_U292.out"], + ["mul_d7__U295.in0","coeff_7_U294.out"], + ["self.d.0","mul_d0__U281.in1"], + ["self.d.1","mul_d1__U283.in1"], + ["self.d.2","mul_d2__U285.in1"], + ["self.d.3","mul_d3__U287.in1"], + ["self.d.4","mul_d4__U289.in1"], + ["self.d.5","mul_d5__U291.in1"], + ["self.d.6","mul_d6__U293.in1"], + ["self.d.7","mul_d7__U295.in1"] ] }, - "aff__U399":{ + "aff__U316":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U413":{ + "add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U414":{ + "add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U415":{ + "add_all__U332":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U418":{ + "add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U400":{ + "coeff_0_U317":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U402":{ + "coeff_1_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_2_U404":{ + "coeff_2_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_3_U406":{ + "coeff_3_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_4_U408":{ + "coeff_4_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U410":{ + "coeff_5_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U412":{ + "const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006c00"]} }, - "mul_d0__U401":{ + "mul_d0__U318":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U403":{ + "mul_d1__U320":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U405":{ + "mul_d2__U322":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U407":{ + "mul_d3__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U409":{ + "mul_d4__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U411":{ + "mul_d5__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U401.out","add_all__U413.in0"], - ["mul_d1__U403.out","add_all__U413.in1"], - ["add_all__U414.in0","add_all__U413.out"], - ["mul_d2__U405.out","add_all__U414.in1"], - ["add_all__U415.in0","add_all__U414.out"], - ["mul_d3__U407.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d4__U409.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["mul_d5__U411.out","add_all__U417.in1"], - ["add_all__U418.in0","add_all__U417.out"], - ["const_term_U412.out","add_all__U418.in1"], - ["self.out","add_all__U418.out"], - ["mul_d0__U401.in0","coeff_0_U400.out"], - ["mul_d1__U403.in0","coeff_1_U402.out"], - ["mul_d2__U405.in0","coeff_2_U404.out"], - ["mul_d3__U407.in0","coeff_3_U406.out"], - ["mul_d4__U409.in0","coeff_4_U408.out"], - ["mul_d5__U411.in0","coeff_5_U410.out"], - ["self.d.0","mul_d0__U401.in1"], - ["self.d.1","mul_d1__U403.in1"], - ["self.d.2","mul_d2__U405.in1"], - ["self.d.3","mul_d3__U407.in1"], - ["self.d.4","mul_d4__U409.in1"], - ["self.d.5","mul_d5__U411.in1"] + ["mul_d0__U318.out","add_all__U330.in0"], + ["mul_d1__U320.out","add_all__U330.in1"], + ["add_all__U331.in0","add_all__U330.out"], + ["mul_d2__U322.out","add_all__U331.in1"], + ["add_all__U332.in0","add_all__U331.out"], + ["mul_d3__U324.out","add_all__U332.in1"], + ["add_all__U333.in0","add_all__U332.out"], + ["mul_d4__U326.out","add_all__U333.in1"], + ["add_all__U334.in0","add_all__U333.out"], + ["mul_d5__U328.out","add_all__U334.in1"], + ["add_all__U335.in0","add_all__U334.out"], + ["const_term_U329.out","add_all__U335.in1"], + ["self.out","add_all__U335.out"], + ["mul_d0__U318.in0","coeff_0_U317.out"], + ["mul_d1__U320.in0","coeff_1_U319.out"], + ["mul_d2__U322.in0","coeff_2_U321.out"], + ["mul_d3__U324.in0","coeff_3_U323.out"], + ["mul_d4__U326.in0","coeff_4_U325.out"], + ["mul_d5__U328.in0","coeff_5_U327.out"], + ["self.d.0","mul_d0__U318.in1"], + ["self.d.1","mul_d1__U320.in1"], + ["self.d.2","mul_d2__U322.in1"], + ["self.d.3","mul_d3__U324.in1"], + ["self.d.4","mul_d4__U326.in1"], + ["self.d.5","mul_d5__U328.in1"] ] }, - "aff__U41":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U51":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U52":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U53":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U42":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U44":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U46":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U48":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U50":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U43":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U437":{ + "aff__U354":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U453":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U454":{ + "add_all__U371":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U455":{ + "add_all__U372":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U456":{ + "add_all__U373":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U355":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001880"]} }, - "coeff_2_U442":{ + "coeff_2_U359":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U444":{ + "coeff_3_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000e"]} }, - "coeff_4_U446":{ + "coeff_4_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_5_U448":{ + "coeff_5_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000c4"]} }, - "const_term_U450":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U439":{ + "mul_d0__U356":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U358":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U443":{ + "mul_d2__U360":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U445":{ + "mul_d3__U362":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U447":{ + "mul_d4__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U449":{ + "mul_d5__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U451.in0"], - ["mul_d1__U441.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["mul_d2__U443.out","add_all__U452.in1"], - ["add_all__U453.in0","add_all__U452.out"], - ["mul_d3__U445.out","add_all__U453.in1"], - ["add_all__U454.in0","add_all__U453.out"], - ["mul_d4__U447.out","add_all__U454.in1"], - ["add_all__U455.in0","add_all__U454.out"], - ["mul_d5__U449.out","add_all__U455.in1"], - ["add_all__U456.in0","add_all__U455.out"], - ["const_term_U450.out","add_all__U456.in1"], - ["self.out","add_all__U456.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["mul_d2__U443.in0","coeff_2_U442.out"], - ["mul_d3__U445.in0","coeff_3_U444.out"], - ["mul_d4__U447.in0","coeff_4_U446.out"], - ["mul_d5__U449.in0","coeff_5_U448.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"], - ["self.d.2","mul_d2__U443.in1"], - ["self.d.3","mul_d3__U445.in1"], - ["self.d.4","mul_d4__U447.in1"], - ["self.d.5","mul_d5__U449.in1"] + ["mul_d0__U356.out","add_all__U368.in0"], + ["mul_d1__U358.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["mul_d2__U360.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["mul_d3__U362.out","add_all__U370.in1"], + ["add_all__U371.in0","add_all__U370.out"], + ["mul_d4__U364.out","add_all__U371.in1"], + ["add_all__U372.in0","add_all__U371.out"], + ["mul_d5__U366.out","add_all__U372.in1"], + ["add_all__U373.in0","add_all__U372.out"], + ["const_term_U367.out","add_all__U373.in1"], + ["self.out","add_all__U373.out"], + ["mul_d0__U356.in0","coeff_0_U355.out"], + ["mul_d1__U358.in0","coeff_1_U357.out"], + ["mul_d2__U360.in0","coeff_2_U359.out"], + ["mul_d3__U362.in0","coeff_3_U361.out"], + ["mul_d4__U364.in0","coeff_4_U363.out"], + ["mul_d5__U366.in0","coeff_5_U365.out"], + ["self.d.0","mul_d0__U356.in1"], + ["self.d.1","mul_d1__U358.in1"], + ["self.d.2","mul_d2__U360.in1"], + ["self.d.3","mul_d3__U362.in1"], + ["self.d.4","mul_d4__U364.in1"], + ["self.d.5","mul_d5__U366.in1"] ] }, - "aff__U459":{ + "aff__U376":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U469":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U470":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U471":{ + "add_all__U388":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U472":{ + "add_all__U389":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U460":{ + "coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U462":{ + "coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000e00"]} }, - "coeff_2_U464":{ + "coeff_2_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_3_U466":{ + "coeff_3_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U468":{ + "const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000c37f"]} }, - "mul_d0__U461":{ + "mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U463":{ + "mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U465":{ + "mul_d2__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U467":{ + "mul_d3__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U461.out","add_all__U469.in0"], - ["mul_d1__U463.out","add_all__U469.in1"], - ["add_all__U470.in0","add_all__U469.out"], - ["mul_d2__U465.out","add_all__U470.in1"], - ["add_all__U471.in0","add_all__U470.out"], - ["mul_d3__U467.out","add_all__U471.in1"], - ["add_all__U472.in0","add_all__U471.out"], - ["const_term_U468.out","add_all__U472.in1"], - ["self.out","add_all__U472.out"], - ["mul_d0__U461.in0","coeff_0_U460.out"], - ["mul_d1__U463.in0","coeff_1_U462.out"], - ["mul_d2__U465.in0","coeff_2_U464.out"], - ["mul_d3__U467.in0","coeff_3_U466.out"], - ["self.d.0","mul_d0__U461.in1"], - ["self.d.1","mul_d1__U463.in1"], - ["self.d.2","mul_d2__U465.in1"], - ["self.d.3","mul_d3__U467.in1"] + ["mul_d0__U378.out","add_all__U386.in0"], + ["mul_d1__U380.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["mul_d2__U382.out","add_all__U387.in1"], + ["add_all__U388.in0","add_all__U387.out"], + ["mul_d3__U384.out","add_all__U388.in1"], + ["add_all__U389.in0","add_all__U388.out"], + ["const_term_U385.out","add_all__U389.in1"], + ["self.out","add_all__U389.out"], + ["mul_d0__U378.in0","coeff_0_U377.out"], + ["mul_d1__U380.in0","coeff_1_U379.out"], + ["mul_d2__U382.in0","coeff_2_U381.out"], + ["mul_d3__U384.in0","coeff_3_U383.out"], + ["self.d.0","mul_d0__U378.in1"], + ["self.d.1","mul_d1__U380.in1"], + ["self.d.2","mul_d2__U382.in1"], + ["self.d.3","mul_d3__U384.in1"] ] }, - "aff__U482":{ + "aff__U399":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U492":{ + "add_all__U409":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U493":{ + "add_all__U410":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U494":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U495":{ + "add_all__U412":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U400":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U402":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U487":{ + "coeff_2_U404":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000e"]} }, - "coeff_3_U489":{ + "coeff_3_U406":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000c4"]} }, - "const_term_U491":{ + "const_term_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U484":{ + "mul_d0__U401":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U403":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U488":{ + "mul_d2__U405":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U490":{ + "mul_d3__U407":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U492.in0"], - ["mul_d1__U486.out","add_all__U492.in1"], - ["add_all__U493.in0","add_all__U492.out"], - ["mul_d2__U488.out","add_all__U493.in1"], - ["add_all__U494.in0","add_all__U493.out"], - ["mul_d3__U490.out","add_all__U494.in1"], - ["add_all__U495.in0","add_all__U494.out"], - ["const_term_U491.out","add_all__U495.in1"], - ["self.out","add_all__U495.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["mul_d2__U488.in0","coeff_2_U487.out"], - ["mul_d3__U490.in0","coeff_3_U489.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"], - ["self.d.2","mul_d2__U488.in1"], - ["self.d.3","mul_d3__U490.in1"] + ["mul_d0__U401.out","add_all__U409.in0"], + ["mul_d1__U403.out","add_all__U409.in1"], + ["add_all__U410.in0","add_all__U409.out"], + ["mul_d2__U405.out","add_all__U410.in1"], + ["add_all__U411.in0","add_all__U410.out"], + ["mul_d3__U407.out","add_all__U411.in1"], + ["add_all__U412.in0","add_all__U411.out"], + ["const_term_U408.out","add_all__U412.in1"], + ["self.out","add_all__U412.out"], + ["mul_d0__U401.in0","coeff_0_U400.out"], + ["mul_d1__U403.in0","coeff_1_U402.out"], + ["mul_d2__U405.in0","coeff_2_U404.out"], + ["mul_d3__U407.in0","coeff_3_U406.out"], + ["self.d.0","mul_d0__U401.in1"], + ["self.d.1","mul_d1__U403.in1"], + ["self.d.2","mul_d2__U405.in1"], + ["self.d.3","mul_d3__U407.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U71":{ + "add_all__U62":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U72":{ + "add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U73":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U74":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U70":{ + "const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U71.in0"], - ["mul_d1__U61.out","add_all__U71.in1"], - ["add_all__U72.in0","add_all__U71.out"], - ["mul_d2__U63.out","add_all__U72.in1"], - ["add_all__U73.in0","add_all__U72.out"], - ["mul_d3__U65.out","add_all__U73.in1"], - ["add_all__U74.in0","add_all__U73.out"], - ["mul_d4__U67.out","add_all__U74.in1"], - ["add_all__U75.in0","add_all__U74.out"], - ["mul_d5__U69.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["const_term_U70.out","add_all__U76.in1"], - ["self.out","add_all__U76.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"] + ["mul_d0__U50.out","add_all__U62.in0"], + ["mul_d1__U52.out","add_all__U62.in1"], + ["add_all__U63.in0","add_all__U62.out"], + ["mul_d2__U54.out","add_all__U63.in1"], + ["add_all__U64.in0","add_all__U63.out"], + ["mul_d3__U56.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["mul_d4__U58.out","add_all__U65.in1"], + ["add_all__U66.in0","add_all__U65.out"], + ["mul_d5__U60.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["const_term_U61.out","add_all__U67.in1"], + ["self.out","add_all__U67.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U109":{ + "add_all__U100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U110":{ + "add_all__U101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000800"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U108":{ + "const_term_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U90":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U92":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U94":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U101":{ + "mul_d5__U98":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U88.out","add_all__U100.in0"], + ["mul_d1__U90.out","add_all__U100.in1"], + ["add_all__U101.in0","add_all__U100.out"], + ["mul_d2__U92.out","add_all__U101.in1"], + ["add_all__U102.in0","add_all__U101.out"], + ["mul_d3__U94.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d4__U96.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d5__U98.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["const_term_U99.out","add_all__U105.in1"], + ["self.out","add_all__U105.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"] + ] + }, + "aff__U9":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U19":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U20":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U21":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U22":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U109.in0"], - ["mul_d1__U99.out","add_all__U109.in1"], - ["add_all__U110.in0","add_all__U109.out"], - ["mul_d2__U101.out","add_all__U110.in1"], - ["add_all__U111.in0","add_all__U110.out"], - ["mul_d3__U103.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d4__U105.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d5__U107.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U108.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U17":{ + "affine_controller__U172":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",5,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U32":{ + "_U190":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U321":{ + "_U1902":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U322":{ + "_U1903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U1904":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U33":{ + "_U191":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U28":{ + "affine_func$add_all__U185":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U29":{ + "affine_func$add_all__U187":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U30":{ + "affine_func$add_all__U188":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U31":{ + "affine_func$add_all__U189":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U19":{ + "affine_func$coeff_0_U174":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U21":{ + "affine_func$coeff_1_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + }, + "affine_func$coeff_2_U178":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "affine_func$coeff_2_U23":{ + "affine_func$coeff_3_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U25":{ + "affine_func$coeff_4_U182":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U27":{ + "affine_func$const_term_U184":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U20":{ + "affine_func$mul_d0__U175":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U177":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U22":{ + "affine_func$mul_d2__U179":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U24":{ + "affine_func$mul_d3__U181":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U26":{ + "affine_func$mul_d4__U183":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -1696,32 +1714,42 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U34$c0_lutcnst":{ + "d_0_am__U192$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U192$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U193$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U34$lut$lut":{ + "d_0_am__U193$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U35$c0_lutcnst":{ + "d_0_am__U194$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U35$lut$lut":{ + "d_0_am__U194$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U36$c0_lutcnst":{ + "d_0_am__U195$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U36$lut$lut":{ + "d_0_am__U195$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1770,22 +1798,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U37$c0_lutcnst":{ + "d_1_am__U196$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U196$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U197$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U37$lut$lut":{ + "d_1_am__U197$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U38$c0_lutcnst":{ + "d_1_am__U198$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U38$lut$lut":{ + "d_1_am__U198$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1801,7 +1839,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -1834,12 +1872,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U39$c0_lutcnst":{ + "d_2_am__U199$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U199$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U200$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U39$lut$lut":{ + "d_2_am__U200$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1855,7 +1903,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -1888,6 +1936,16 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U201$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U201$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -1899,7 +1957,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -1932,6 +1990,50 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -1961,6 +2063,11 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -1968,33 +2075,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U321.out"], - ["d_2_inc.in1","_U322.out"], - ["d_3_inc.in1","_U323.out"], - ["cmp_time.in1","_U33.out"], - ["affine_func$mul_d0__U20.out","affine_func$add_all__U28.in0"], - ["affine_func$mul_d1__U22.out","affine_func$add_all__U28.in1"], - ["affine_func$add_all__U29.in0","affine_func$add_all__U28.out"], - ["affine_func$mul_d2__U24.out","affine_func$add_all__U29.in1"], - ["affine_func$add_all__U30.in0","affine_func$add_all__U29.out"], - ["affine_func$mul_d3__U26.out","affine_func$add_all__U30.in1"], - ["affine_func$add_all__U31.in0","affine_func$add_all__U30.out"], - ["affine_func$const_term_U27.out","affine_func$add_all__U31.in1"], - ["time_diff.in0","affine_func$add_all__U31.out"], - ["affine_func$mul_d0__U20.in0","affine_func$coeff_0_U19.out"], - ["affine_func$mul_d1__U22.in0","affine_func$coeff_1_U21.out"], - ["affine_func$mul_d2__U24.in0","affine_func$coeff_2_U23.out"], - ["affine_func$mul_d3__U26.in0","affine_func$coeff_3_U25.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U20.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U22.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U24.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U26.in1"], + ["d_0_inc.in1","_U190.out"], + ["d_1_inc.in1","_U1901.out"], + ["d_2_inc.in1","_U1902.out"], + ["d_3_inc.in1","_U1903.out"], + ["d_4_inc.in1","_U1904.out"], + ["cmp_time.in1","_U191.out"], + ["affine_func$mul_d0__U175.out","affine_func$add_all__U185.in0"], + ["affine_func$mul_d1__U177.out","affine_func$add_all__U185.in1"], + ["affine_func$add_all__U186.in0","affine_func$add_all__U185.out"], + ["affine_func$mul_d2__U179.out","affine_func$add_all__U186.in1"], + ["affine_func$add_all__U187.in0","affine_func$add_all__U186.out"], + ["affine_func$mul_d3__U181.out","affine_func$add_all__U187.in1"], + ["affine_func$add_all__U188.in0","affine_func$add_all__U187.out"], + ["affine_func$mul_d4__U183.out","affine_func$add_all__U188.in1"], + ["affine_func$add_all__U189.in0","affine_func$add_all__U188.out"], + ["affine_func$const_term_U184.out","affine_func$add_all__U189.in1"], + ["time_diff.in0","affine_func$add_all__U189.out"], + ["affine_func$mul_d0__U175.in0","affine_func$coeff_0_U174.out"], + ["affine_func$mul_d1__U177.in0","affine_func$coeff_1_U176.out"], + ["affine_func$mul_d2__U179.in0","affine_func$coeff_2_U178.out"], + ["affine_func$mul_d3__U181.in0","affine_func$coeff_3_U180.out"], + ["affine_func$mul_d4__U183.in0","affine_func$coeff_4_U182.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U175.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U177.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U179.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U181.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U183.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -2002,28 +2115,31 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U34$lut$lut.bit.in.2","d_0_am__U34$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U34$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U34$lut$lut.bit.in.1"], - ["d_0_am__U35$lut$lut.bit.in.0","d_0_am__U34$lut$lut.bit.out"], - ["d_0_am__U35$lut$lut.bit.in.2","d_0_am__U35$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U35$lut$lut.bit.in.1"], - ["d_0_am__U36$lut$lut.bit.in.0","d_0_am__U35$lut$lut.bit.out"], - ["d_0_am__U36$lut$lut.bit.in.2","d_0_am__U36$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U36$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U36$lut$lut.bit.out"], + ["d_0_am__U192$lut$lut.bit.in.2","d_0_am__U192$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U192$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U192$lut$lut.bit.in.1"], + ["d_0_am__U193$lut$lut.bit.in.0","d_0_am__U192$lut$lut.bit.out"], + ["d_0_am__U193$lut$lut.bit.in.2","d_0_am__U193$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U193$lut$lut.bit.in.1"], + ["d_0_am__U194$lut$lut.bit.in.0","d_0_am__U193$lut$lut.bit.out"], + ["d_0_am__U194$lut$lut.bit.in.2","d_0_am__U194$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U194$lut$lut.bit.in.1"], + ["d_0_am__U195$lut$lut.bit.in.0","d_0_am__U194$lut$lut.bit.out"], + ["d_0_am__U195$lut$lut.bit.in.2","d_0_am__U195$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U195$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U195$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2040,13 +2156,16 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U37$lut$lut.bit.in.2","d_1_am__U37$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U37$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U37$lut$lut.bit.in.1"], - ["d_1_am__U38$lut$lut.bit.in.0","d_1_am__U37$lut$lut.bit.out"], - ["d_1_am__U38$lut$lut.bit.in.2","d_1_am__U38$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U38$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U38$lut$lut.bit.out"], + ["d_1_am__U196$lut$lut.bit.in.2","d_1_am__U196$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U196$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U196$lut$lut.bit.in.1"], + ["d_1_am__U197$lut$lut.bit.in.0","d_1_am__U196$lut$lut.bit.out"], + ["d_1_am__U197$lut$lut.bit.in.2","d_1_am__U197$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U197$lut$lut.bit.in.1"], + ["d_1_am__U198$lut$lut.bit.in.0","d_1_am__U197$lut$lut.bit.out"], + ["d_1_am__U198$lut$lut.bit.in.2","d_1_am__U198$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U198$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U198$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2063,10 +2182,13 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U39$lut$lut.bit.in.2","d_2_am__U39$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U39$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U39$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U39$lut$lut.bit.out"], + ["d_2_am__U199$lut$lut.bit.in.2","d_2_am__U199$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U199$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U199$lut$lut.bit.in.1"], + ["d_2_am__U200$lut$lut.bit.in.0","d_2_am__U199$lut$lut.bit.out"], + ["d_2_am__U200$lut$lut.bit.in.2","d_2_am__U200$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U200$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U200$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2083,6 +2205,10 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U201$lut$lut.bit.in.2","d_3_am__U201$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U201$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U201$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U201$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2092,121 +2218,191 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["true_lutcnst.bit.out","d_4_next_value.sel"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"] ] }, - "affine_controller__U246":{ + "affine_controller__U221":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], + ["d",["Array",8,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U264":{ + "_U248":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2481":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2482":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2641":{ + "_U2483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2642":{ + "_U2484":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2643":{ + "_U2485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2644":{ + "_U2486":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U265":{ + "_U2487":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U259":{ + "affine_func$add_all__U240":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U241":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U242":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U260":{ + "affine_func$add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U261":{ + "affine_func$add_all__U245":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U262":{ + "affine_func$add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U263":{ + "affine_func$add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U248":{ + "affine_func$coeff_0_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U250":{ + "affine_func$coeff_1_U225":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "affine_func$coeff_2_U252":{ + "affine_func$coeff_2_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "affine_func$coeff_3_U254":{ + "affine_func$coeff_3_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00000300"]} + }, + "affine_func$coeff_4_U231":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "affine_func$coeff_5_U233":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_6_U235":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_4_U256":{ + "affine_func$coeff_7_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U258":{ + "affine_func$const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h000023ff"]} + }, + "affine_func$mul_d0__U224":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U226":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U228":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U249":{ + "affine_func$mul_d3__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U251":{ + "affine_func$mul_d4__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U253":{ + "affine_func$mul_d5__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U255":{ + "affine_func$mul_d6__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U257":{ + "affine_func$mul_d7__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2270,42 +2466,72 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U266$c0_lutcnst":{ + "d_0_am__U250$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U250$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U251$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U251$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U252$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U252$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U253$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U266$lut$lut":{ + "d_0_am__U253$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U267$c0_lutcnst":{ + "d_0_am__U254$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U267$lut$lut":{ + "d_0_am__U254$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U268$c0_lutcnst":{ + "d_0_am__U255$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U268$lut$lut":{ + "d_0_am__U255$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U269$c0_lutcnst":{ + "d_0_am__U256$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U269$lut$lut":{ + "d_0_am__U256$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2354,32 +2580,62 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U270$c0_lutcnst":{ + "d_1_am__U257$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U257$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U258$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U258$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U259$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U259$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U260$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U270$lut$lut":{ + "d_1_am__U260$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U271$c0_lutcnst":{ + "d_1_am__U261$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U271$lut$lut":{ + "d_1_am__U261$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U272$c0_lutcnst":{ + "d_1_am__U262$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U272$lut$lut":{ + "d_1_am__U262$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2395,7 +2651,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2428,22 +2684,52 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U273$c0_lutcnst":{ + "d_2_am__U263$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U263$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U264$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U264$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U265$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U265$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U266$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U273$lut$lut":{ + "d_2_am__U266$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U274$c0_lutcnst":{ + "d_2_am__U267$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U274$lut$lut":{ + "d_2_am__U267$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2459,7 +2745,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2492,12 +2778,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U275$c0_lutcnst":{ + "d_3_am__U268$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U268$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U269$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U269$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U270$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U270$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U271$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U275$lut$lut":{ + "d_3_am__U271$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2513,7 +2829,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_3_min":{ "genref":"coreir.const", @@ -2546,6 +2862,36 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_am__U272$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U272$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U273$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U273$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U274$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U274$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -2557,7 +2903,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_4_min":{ "genref":"coreir.const", @@ -2590,112 +2936,316 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ + "d_5_am__U275$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true2_lutcnst":{ + "d_5_am__U275$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true3_lutcnst":{ + "d_5_am__U276$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true4_lutcnst":{ + "d_5_am__U276$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "true_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U264.out"], - ["d_1_inc.in1","_U2641.out"], - ["d_2_inc.in1","_U2642.out"], - ["d_3_inc.in1","_U2643.out"], - ["d_4_inc.in1","_U2644.out"], - ["cmp_time.in1","_U265.out"], - ["affine_func$mul_d0__U249.out","affine_func$add_all__U259.in0"], - ["affine_func$mul_d1__U251.out","affine_func$add_all__U259.in1"], - ["affine_func$add_all__U260.in0","affine_func$add_all__U259.out"], - ["affine_func$mul_d2__U253.out","affine_func$add_all__U260.in1"], - ["affine_func$add_all__U261.in0","affine_func$add_all__U260.out"], - ["affine_func$mul_d3__U255.out","affine_func$add_all__U261.in1"], - ["affine_func$add_all__U262.in0","affine_func$add_all__U261.out"], - ["affine_func$mul_d4__U257.out","affine_func$add_all__U262.in1"], - ["affine_func$add_all__U263.in0","affine_func$add_all__U262.out"], - ["affine_func$const_term_U258.out","affine_func$add_all__U263.in1"], - ["time_diff.in0","affine_func$add_all__U263.out"], - ["affine_func$mul_d0__U249.in0","affine_func$coeff_0_U248.out"], - ["affine_func$mul_d1__U251.in0","affine_func$coeff_1_U250.out"], - ["affine_func$mul_d2__U253.in0","affine_func$coeff_2_U252.out"], - ["affine_func$mul_d3__U255.in0","affine_func$coeff_3_U254.out"], - ["affine_func$mul_d4__U257.in0","affine_func$coeff_4_U256.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U249.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U251.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U253.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U255.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U257.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000003"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_6_am__U277$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_6_am__U277$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_7_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_7_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_7_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_7_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true2_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true3_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true8_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true9_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U248.out"], + ["d_1_inc.in1","_U2481.out"], + ["d_2_inc.in1","_U2482.out"], + ["d_3_inc.in1","_U2483.out"], + ["d_4_inc.in1","_U2484.out"], + ["d_5_inc.in1","_U2485.out"], + ["d_6_inc.in1","_U2486.out"], + ["d_7_inc.in1","_U2487.out"], + ["cmp_time.in1","_U249.out"], + ["affine_func$mul_d0__U224.out","affine_func$add_all__U240.in0"], + ["affine_func$mul_d1__U226.out","affine_func$add_all__U240.in1"], + ["affine_func$add_all__U241.in0","affine_func$add_all__U240.out"], + ["affine_func$mul_d2__U228.out","affine_func$add_all__U241.in1"], + ["affine_func$add_all__U242.in0","affine_func$add_all__U241.out"], + ["affine_func$mul_d3__U230.out","affine_func$add_all__U242.in1"], + ["affine_func$add_all__U243.in0","affine_func$add_all__U242.out"], + ["affine_func$mul_d4__U232.out","affine_func$add_all__U243.in1"], + ["affine_func$add_all__U244.in0","affine_func$add_all__U243.out"], + ["affine_func$mul_d5__U234.out","affine_func$add_all__U244.in1"], + ["affine_func$add_all__U245.in0","affine_func$add_all__U244.out"], + ["affine_func$mul_d6__U236.out","affine_func$add_all__U245.in1"], + ["affine_func$add_all__U246.in0","affine_func$add_all__U245.out"], + ["affine_func$mul_d7__U238.out","affine_func$add_all__U246.in1"], + ["affine_func$add_all__U247.in0","affine_func$add_all__U246.out"], + ["affine_func$const_term_U239.out","affine_func$add_all__U247.in1"], + ["time_diff.in0","affine_func$add_all__U247.out"], + ["affine_func$mul_d0__U224.in0","affine_func$coeff_0_U223.out"], + ["affine_func$mul_d1__U226.in0","affine_func$coeff_1_U225.out"], + ["affine_func$mul_d2__U228.in0","affine_func$coeff_2_U227.out"], + ["affine_func$mul_d3__U230.in0","affine_func$coeff_3_U229.out"], + ["affine_func$mul_d4__U232.in0","affine_func$coeff_4_U231.out"], + ["affine_func$mul_d5__U234.in0","affine_func$coeff_5_U233.out"], + ["affine_func$mul_d6__U236.in0","affine_func$coeff_6_U235.out"], + ["affine_func$mul_d7__U238.in0","affine_func$coeff_7_U237.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U224.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U226.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U228.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U230.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U232.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U234.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U236.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U238.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["d_7_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U266$lut$lut.bit.in.2","d_0_am__U266$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U266$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U266$lut$lut.bit.in.1"], - ["d_0_am__U267$lut$lut.bit.in.0","d_0_am__U266$lut$lut.bit.out"], - ["d_0_am__U267$lut$lut.bit.in.2","d_0_am__U267$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U267$lut$lut.bit.in.1"], - ["d_0_am__U268$lut$lut.bit.in.0","d_0_am__U267$lut$lut.bit.out"], - ["d_0_am__U268$lut$lut.bit.in.2","d_0_am__U268$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U268$lut$lut.bit.in.1"], - ["d_0_am__U269$lut$lut.bit.in.0","d_0_am__U268$lut$lut.bit.out"], - ["d_0_am__U269$lut$lut.bit.in.2","d_0_am__U269$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U269$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U269$lut$lut.bit.out"], + ["d_0_am__U250$lut$lut.bit.in.2","d_0_am__U250$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U250$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U250$lut$lut.bit.in.1"], + ["d_0_am__U251$lut$lut.bit.in.0","d_0_am__U250$lut$lut.bit.out"], + ["d_0_am__U251$lut$lut.bit.in.2","d_0_am__U251$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U251$lut$lut.bit.in.1"], + ["d_0_am__U252$lut$lut.bit.in.0","d_0_am__U251$lut$lut.bit.out"], + ["d_0_am__U252$lut$lut.bit.in.2","d_0_am__U252$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U252$lut$lut.bit.in.1"], + ["d_0_am__U253$lut$lut.bit.in.0","d_0_am__U252$lut$lut.bit.out"], + ["d_0_am__U253$lut$lut.bit.in.2","d_0_am__U253$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U253$lut$lut.bit.in.1"], + ["d_0_am__U254$lut$lut.bit.in.0","d_0_am__U253$lut$lut.bit.out"], + ["d_0_am__U254$lut$lut.bit.in.2","d_0_am__U254$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U254$lut$lut.bit.in.1"], + ["d_0_am__U255$lut$lut.bit.in.0","d_0_am__U254$lut$lut.bit.out"], + ["d_0_am__U255$lut$lut.bit.in.2","d_0_am__U255$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U255$lut$lut.bit.in.1"], + ["d_0_am__U256$lut$lut.bit.in.0","d_0_am__U255$lut$lut.bit.out"], + ["d_0_am__U256$lut$lut.bit.in.2","d_0_am__U256$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U256$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U256$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2712,16 +3262,25 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U270$lut$lut.bit.in.2","d_1_am__U270$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U270$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U270$lut$lut.bit.in.1"], - ["d_1_am__U271$lut$lut.bit.in.0","d_1_am__U270$lut$lut.bit.out"], - ["d_1_am__U271$lut$lut.bit.in.2","d_1_am__U271$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U271$lut$lut.bit.in.1"], - ["d_1_am__U272$lut$lut.bit.in.0","d_1_am__U271$lut$lut.bit.out"], - ["d_1_am__U272$lut$lut.bit.in.2","d_1_am__U272$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U272$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U272$lut$lut.bit.out"], + ["d_1_am__U257$lut$lut.bit.in.2","d_1_am__U257$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U257$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U257$lut$lut.bit.in.1"], + ["d_1_am__U258$lut$lut.bit.in.0","d_1_am__U257$lut$lut.bit.out"], + ["d_1_am__U258$lut$lut.bit.in.2","d_1_am__U258$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U258$lut$lut.bit.in.1"], + ["d_1_am__U259$lut$lut.bit.in.0","d_1_am__U258$lut$lut.bit.out"], + ["d_1_am__U259$lut$lut.bit.in.2","d_1_am__U259$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U259$lut$lut.bit.in.1"], + ["d_1_am__U260$lut$lut.bit.in.0","d_1_am__U259$lut$lut.bit.out"], + ["d_1_am__U260$lut$lut.bit.in.2","d_1_am__U260$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U260$lut$lut.bit.in.1"], + ["d_1_am__U261$lut$lut.bit.in.0","d_1_am__U260$lut$lut.bit.out"], + ["d_1_am__U261$lut$lut.bit.in.2","d_1_am__U261$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U261$lut$lut.bit.in.1"], + ["d_1_am__U262$lut$lut.bit.in.0","d_1_am__U261$lut$lut.bit.out"], + ["d_1_am__U262$lut$lut.bit.in.2","d_1_am__U262$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U262$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U262$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2738,13 +3297,22 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U273$lut$lut.bit.in.2","d_2_am__U273$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U273$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U273$lut$lut.bit.in.1"], - ["d_2_am__U274$lut$lut.bit.in.0","d_2_am__U273$lut$lut.bit.out"], - ["d_2_am__U274$lut$lut.bit.in.2","d_2_am__U274$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U274$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U274$lut$lut.bit.out"], + ["d_2_am__U263$lut$lut.bit.in.2","d_2_am__U263$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U263$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U263$lut$lut.bit.in.1"], + ["d_2_am__U264$lut$lut.bit.in.0","d_2_am__U263$lut$lut.bit.out"], + ["d_2_am__U264$lut$lut.bit.in.2","d_2_am__U264$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U264$lut$lut.bit.in.1"], + ["d_2_am__U265$lut$lut.bit.in.0","d_2_am__U264$lut$lut.bit.out"], + ["d_2_am__U265$lut$lut.bit.in.2","d_2_am__U265$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U265$lut$lut.bit.in.1"], + ["d_2_am__U266$lut$lut.bit.in.0","d_2_am__U265$lut$lut.bit.out"], + ["d_2_am__U266$lut$lut.bit.in.2","d_2_am__U266$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U266$lut$lut.bit.in.1"], + ["d_2_am__U267$lut$lut.bit.in.0","d_2_am__U266$lut$lut.bit.out"], + ["d_2_am__U267$lut$lut.bit.in.2","d_2_am__U267$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U267$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U267$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2761,10 +3329,19 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U275$lut$lut.bit.in.2","d_3_am__U275$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U275$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U275$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U275$lut$lut.bit.out"], + ["d_3_am__U268$lut$lut.bit.in.2","d_3_am__U268$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U268$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U268$lut$lut.bit.in.1"], + ["d_3_am__U269$lut$lut.bit.in.0","d_3_am__U268$lut$lut.bit.out"], + ["d_3_am__U269$lut$lut.bit.in.2","d_3_am__U269$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U269$lut$lut.bit.in.1"], + ["d_3_am__U270$lut$lut.bit.in.0","d_3_am__U269$lut$lut.bit.out"], + ["d_3_am__U270$lut$lut.bit.in.2","d_3_am__U270$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U270$lut$lut.bit.in.1"], + ["d_3_am__U271$lut$lut.bit.in.0","d_3_am__U270$lut$lut.bit.out"], + ["d_3_am__U271$lut$lut.bit.in.2","d_3_am__U271$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U271$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U271$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2781,6 +3358,16 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U272$lut$lut.bit.in.2","d_4_am__U272$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U272$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U272$lut$lut.bit.in.1"], + ["d_4_am__U273$lut$lut.bit.in.0","d_4_am__U272$lut$lut.bit.out"], + ["d_4_am__U273$lut$lut.bit.in.2","d_4_am__U273$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U273$lut$lut.bit.in.1"], + ["d_4_am__U274$lut$lut.bit.in.0","d_4_am__U273$lut$lut.bit.out"], + ["d_4_am__U274$lut$lut.bit.in.2","d_4_am__U274$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U274$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U274$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2790,175 +3377,198 @@ ["d_4_reg$reg0.out","d_4_next_value.in0"], ["d_4_next_value_at_max.out","d_4_next_value.in1"], ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["true_lutcnst.bit.out","d_4_next_value.sel"], ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], ["self.rst_n","d_4_reg$clrMux.sel"], ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"] + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U275$lut$lut.bit.in.2","d_5_am__U275$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U275$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U275$lut$lut.bit.in.1"], + ["d_5_am__U276$lut$lut.bit.in.0","d_5_am__U275$lut$lut.bit.out"], + ["d_5_am__U276$lut$lut.bit.in.2","d_5_am__U276$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U276$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U276$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_am__U277$lut$lut.bit.in.2","d_6_am__U277$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U277$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U277$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U277$lut$lut.bit.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"], + ["d_7_reg$reg0.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg$reg0.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg$reg0.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg$enMux.in1","d_7_next_value.out"], + ["true_lutcnst.bit.out","d_7_next_value.sel"], + ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], + ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], + ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], + ["self.rst_n","d_7_reg$clrMux.sel"], + ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], + ["self.clk","d_7_reg$reg0.clk"], + ["self.d.7","d_7_reg$reg0.out"] ] }, - "affine_controller__U295":{ + "affine_controller__U315":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",8,["Array",32,"Bit"]]], + ["d",["Array",6,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U322":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3221":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3222":{ + "_U336":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3223":{ + "_U3361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3224":{ + "_U3362":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3225":{ + "_U3363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3226":{ + "_U3364":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3227":{ + "_U3365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U337":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U314":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U315":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U316":{ + "affine_func$add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U317":{ + "affine_func$add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U318":{ + "affine_func$add_all__U332":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U319":{ + "affine_func$add_all__U333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U320":{ + "affine_func$add_all__U334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U321":{ + "affine_func$add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U297":{ + "affine_func$coeff_0_U317":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U299":{ + "affine_func$coeff_1_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "affine_func$coeff_2_U301":{ + "affine_func$coeff_2_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001f80"]} - }, - "affine_func$coeff_3_U303":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000300"]} - }, - "affine_func$coeff_4_U305":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "affine_func$coeff_5_U307":{ + "affine_func$coeff_3_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "affine_func$coeff_6_U309":{ + "affine_func$coeff_4_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_7_U311":{ + "affine_func$coeff_5_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U313":{ + "affine_func$const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000023ff"]} - }, - "affine_func$mul_d0__U298":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U300":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00006c00"]} }, - "affine_func$mul_d2__U302":{ + "affine_func$mul_d0__U318":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U304":{ + "affine_func$mul_d1__U320":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U306":{ + "affine_func$mul_d2__U322":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U308":{ + "affine_func$mul_d3__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U310":{ + "affine_func$mul_d4__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d7__U312":{ + "affine_func$mul_d5__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -3022,72 +3632,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U324$c0_lutcnst":{ + "d_0_am__U338$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U324$lut$lut":{ + "d_0_am__U338$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U325$c0_lutcnst":{ + "d_0_am__U339$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U325$lut$lut":{ + "d_0_am__U339$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U326$c0_lutcnst":{ + "d_0_am__U340$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U326$lut$lut":{ + "d_0_am__U340$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U327$c0_lutcnst":{ + "d_0_am__U341$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U327$lut$lut":{ + "d_0_am__U341$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U328$c0_lutcnst":{ + "d_0_am__U342$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U328$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U329$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U329$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U330$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U330$lut$lut":{ + "d_0_am__U342$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3136,62 +3726,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U331$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U331$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U332$c0_lutcnst":{ + "d_1_am__U343$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U332$lut$lut":{ + "d_1_am__U343$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U333$c0_lutcnst":{ + "d_1_am__U344$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U333$lut$lut":{ + "d_1_am__U344$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U334$c0_lutcnst":{ + "d_1_am__U345$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U334$lut$lut":{ + "d_1_am__U345$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U335$c0_lutcnst":{ + "d_1_am__U346$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U335$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U336$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U336$lut$lut":{ + "d_1_am__U346$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3240,52 +3810,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U337$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U337$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U338$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U338$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U339$c0_lutcnst":{ + "d_2_am__U347$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U339$lut$lut":{ + "d_2_am__U347$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U340$c0_lutcnst":{ + "d_2_am__U348$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U340$lut$lut":{ + "d_2_am__U348$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U341$c0_lutcnst":{ + "d_2_am__U349$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U341$lut$lut":{ + "d_2_am__U349$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3301,7 +3851,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h0000000d"]} }, "d_2_min":{ "genref":"coreir.const", @@ -3334,42 +3884,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U342$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U342$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U343$c0_lutcnst":{ + "d_3_am__U350$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U343$lut$lut":{ + "d_3_am__U350$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U344$c0_lutcnst":{ + "d_3_am__U351$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U344$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U345$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U345$lut$lut":{ + "d_3_am__U351$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3385,7 +3915,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h0000000d"]} }, "d_3_min":{ "genref":"coreir.const", @@ -3418,32 +3948,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U346$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U346$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U347$c0_lutcnst":{ + "d_4_am__U352$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U347$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U348$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U348$lut$lut":{ + "d_4_am__U352$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3459,7 +3969,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, "d_4_min":{ "genref":"coreir.const", @@ -3492,26 +4002,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U349$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U349$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U350$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U350$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -3523,7 +4013,7 @@ "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, "d_5_min":{ "genref":"coreir.const", @@ -3547,109 +4037,11 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_6_am__U351$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_6_am__U351$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_6_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_6_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_6_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_6_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_7_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_7_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_7_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_7_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$enMux":{ + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -3693,16 +4085,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -3710,48 +4092,38 @@ } }, "connections":[ - ["d_0_inc.in1","_U322.out"], - ["d_1_inc.in1","_U3221.out"], - ["d_2_inc.in1","_U3222.out"], - ["d_3_inc.in1","_U3223.out"], - ["d_4_inc.in1","_U3224.out"], - ["d_5_inc.in1","_U3225.out"], - ["d_6_inc.in1","_U3226.out"], - ["d_7_inc.in1","_U3227.out"], - ["cmp_time.in1","_U323.out"], - ["affine_func$mul_d0__U298.out","affine_func$add_all__U314.in0"], - ["affine_func$mul_d1__U300.out","affine_func$add_all__U314.in1"], - ["affine_func$add_all__U315.in0","affine_func$add_all__U314.out"], - ["affine_func$mul_d2__U302.out","affine_func$add_all__U315.in1"], - ["affine_func$add_all__U316.in0","affine_func$add_all__U315.out"], - ["affine_func$mul_d3__U304.out","affine_func$add_all__U316.in1"], - ["affine_func$add_all__U317.in0","affine_func$add_all__U316.out"], - ["affine_func$mul_d4__U306.out","affine_func$add_all__U317.in1"], - ["affine_func$add_all__U318.in0","affine_func$add_all__U317.out"], - ["affine_func$mul_d5__U308.out","affine_func$add_all__U318.in1"], - ["affine_func$add_all__U319.in0","affine_func$add_all__U318.out"], - ["affine_func$mul_d6__U310.out","affine_func$add_all__U319.in1"], - ["affine_func$add_all__U320.in0","affine_func$add_all__U319.out"], - ["affine_func$mul_d7__U312.out","affine_func$add_all__U320.in1"], - ["affine_func$add_all__U321.in0","affine_func$add_all__U320.out"], - ["affine_func$const_term_U313.out","affine_func$add_all__U321.in1"], - ["time_diff.in0","affine_func$add_all__U321.out"], - ["affine_func$mul_d0__U298.in0","affine_func$coeff_0_U297.out"], - ["affine_func$mul_d1__U300.in0","affine_func$coeff_1_U299.out"], - ["affine_func$mul_d2__U302.in0","affine_func$coeff_2_U301.out"], - ["affine_func$mul_d3__U304.in0","affine_func$coeff_3_U303.out"], - ["affine_func$mul_d4__U306.in0","affine_func$coeff_4_U305.out"], - ["affine_func$mul_d5__U308.in0","affine_func$coeff_5_U307.out"], - ["affine_func$mul_d6__U310.in0","affine_func$coeff_6_U309.out"], - ["affine_func$mul_d7__U312.in0","affine_func$coeff_7_U311.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U298.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U300.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U302.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U304.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U306.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U308.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U310.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U312.in1"], + ["d_0_inc.in1","_U336.out"], + ["d_1_inc.in1","_U3361.out"], + ["d_2_inc.in1","_U3362.out"], + ["d_3_inc.in1","_U3363.out"], + ["d_4_inc.in1","_U3364.out"], + ["d_5_inc.in1","_U3365.out"], + ["cmp_time.in1","_U337.out"], + ["affine_func$mul_d0__U318.out","affine_func$add_all__U330.in0"], + ["affine_func$mul_d1__U320.out","affine_func$add_all__U330.in1"], + ["affine_func$add_all__U331.in0","affine_func$add_all__U330.out"], + ["affine_func$mul_d2__U322.out","affine_func$add_all__U331.in1"], + ["affine_func$add_all__U332.in0","affine_func$add_all__U331.out"], + ["affine_func$mul_d3__U324.out","affine_func$add_all__U332.in1"], + ["affine_func$add_all__U333.in0","affine_func$add_all__U332.out"], + ["affine_func$mul_d4__U326.out","affine_func$add_all__U333.in1"], + ["affine_func$add_all__U334.in0","affine_func$add_all__U333.out"], + ["affine_func$mul_d5__U328.out","affine_func$add_all__U334.in1"], + ["affine_func$add_all__U335.in0","affine_func$add_all__U334.out"], + ["affine_func$const_term_U329.out","affine_func$add_all__U335.in1"], + ["time_diff.in0","affine_func$add_all__U335.out"], + ["affine_func$mul_d0__U318.in0","affine_func$coeff_0_U317.out"], + ["affine_func$mul_d1__U320.in0","affine_func$coeff_1_U319.out"], + ["affine_func$mul_d2__U322.in0","affine_func$coeff_2_U321.out"], + ["affine_func$mul_d3__U324.in0","affine_func$coeff_3_U323.out"], + ["affine_func$mul_d4__U326.in0","affine_func$coeff_4_U325.out"], + ["affine_func$mul_d5__U328.in0","affine_func$coeff_5_U327.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U318.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U320.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U322.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U324.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U326.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U328.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -3759,8 +4131,6 @@ ["d_3_reg$enMux.sel","cmp_time.out"], ["d_4_reg$enMux.sel","cmp_time.out"], ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], - ["d_7_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -3768,40 +4138,34 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U324$lut$lut.bit.in.2","d_0_am__U324$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U324$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U324$lut$lut.bit.in.1"], - ["d_0_am__U325$lut$lut.bit.in.0","d_0_am__U324$lut$lut.bit.out"], - ["d_0_am__U325$lut$lut.bit.in.2","d_0_am__U325$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U325$lut$lut.bit.in.1"], - ["d_0_am__U326$lut$lut.bit.in.0","d_0_am__U325$lut$lut.bit.out"], - ["d_0_am__U326$lut$lut.bit.in.2","d_0_am__U326$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U326$lut$lut.bit.in.1"], - ["d_0_am__U327$lut$lut.bit.in.0","d_0_am__U326$lut$lut.bit.out"], - ["d_0_am__U327$lut$lut.bit.in.2","d_0_am__U327$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U327$lut$lut.bit.in.1"], - ["d_0_am__U328$lut$lut.bit.in.0","d_0_am__U327$lut$lut.bit.out"], - ["d_0_am__U328$lut$lut.bit.in.2","d_0_am__U328$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U328$lut$lut.bit.in.1"], - ["d_0_am__U329$lut$lut.bit.in.0","d_0_am__U328$lut$lut.bit.out"], - ["d_0_am__U329$lut$lut.bit.in.2","d_0_am__U329$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U329$lut$lut.bit.in.1"], - ["d_0_am__U330$lut$lut.bit.in.0","d_0_am__U329$lut$lut.bit.out"], - ["d_0_am__U330$lut$lut.bit.in.2","d_0_am__U330$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U330$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U330$lut$lut.bit.out"], + ["d_0_am__U338$lut$lut.bit.in.2","d_0_am__U338$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U338$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U338$lut$lut.bit.in.1"], + ["d_0_am__U339$lut$lut.bit.in.0","d_0_am__U338$lut$lut.bit.out"], + ["d_0_am__U339$lut$lut.bit.in.2","d_0_am__U339$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U339$lut$lut.bit.in.1"], + ["d_0_am__U340$lut$lut.bit.in.0","d_0_am__U339$lut$lut.bit.out"], + ["d_0_am__U340$lut$lut.bit.in.2","d_0_am__U340$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U340$lut$lut.bit.in.1"], + ["d_0_am__U341$lut$lut.bit.in.0","d_0_am__U340$lut$lut.bit.out"], + ["d_0_am__U341$lut$lut.bit.in.2","d_0_am__U341$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U341$lut$lut.bit.in.1"], + ["d_0_am__U342$lut$lut.bit.in.0","d_0_am__U341$lut$lut.bit.out"], + ["d_0_am__U342$lut$lut.bit.in.2","d_0_am__U342$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U342$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U342$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3818,25 +4182,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U331$lut$lut.bit.in.2","d_1_am__U331$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U331$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U331$lut$lut.bit.in.1"], - ["d_1_am__U332$lut$lut.bit.in.0","d_1_am__U331$lut$lut.bit.out"], - ["d_1_am__U332$lut$lut.bit.in.2","d_1_am__U332$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U332$lut$lut.bit.in.1"], - ["d_1_am__U333$lut$lut.bit.in.0","d_1_am__U332$lut$lut.bit.out"], - ["d_1_am__U333$lut$lut.bit.in.2","d_1_am__U333$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U333$lut$lut.bit.in.1"], - ["d_1_am__U334$lut$lut.bit.in.0","d_1_am__U333$lut$lut.bit.out"], - ["d_1_am__U334$lut$lut.bit.in.2","d_1_am__U334$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U334$lut$lut.bit.in.1"], - ["d_1_am__U335$lut$lut.bit.in.0","d_1_am__U334$lut$lut.bit.out"], - ["d_1_am__U335$lut$lut.bit.in.2","d_1_am__U335$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U335$lut$lut.bit.in.1"], - ["d_1_am__U336$lut$lut.bit.in.0","d_1_am__U335$lut$lut.bit.out"], - ["d_1_am__U336$lut$lut.bit.in.2","d_1_am__U336$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U336$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U336$lut$lut.bit.out"], + ["d_1_am__U343$lut$lut.bit.in.2","d_1_am__U343$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U343$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U343$lut$lut.bit.in.1"], + ["d_1_am__U344$lut$lut.bit.in.0","d_1_am__U343$lut$lut.bit.out"], + ["d_1_am__U344$lut$lut.bit.in.2","d_1_am__U344$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U344$lut$lut.bit.in.1"], + ["d_1_am__U345$lut$lut.bit.in.0","d_1_am__U344$lut$lut.bit.out"], + ["d_1_am__U345$lut$lut.bit.in.2","d_1_am__U345$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U345$lut$lut.bit.in.1"], + ["d_1_am__U346$lut$lut.bit.in.0","d_1_am__U345$lut$lut.bit.out"], + ["d_1_am__U346$lut$lut.bit.in.2","d_1_am__U346$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U346$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U346$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3853,22 +4211,16 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U337$lut$lut.bit.in.2","d_2_am__U337$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U337$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U337$lut$lut.bit.in.1"], - ["d_2_am__U338$lut$lut.bit.in.0","d_2_am__U337$lut$lut.bit.out"], - ["d_2_am__U338$lut$lut.bit.in.2","d_2_am__U338$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U338$lut$lut.bit.in.1"], - ["d_2_am__U339$lut$lut.bit.in.0","d_2_am__U338$lut$lut.bit.out"], - ["d_2_am__U339$lut$lut.bit.in.2","d_2_am__U339$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U339$lut$lut.bit.in.1"], - ["d_2_am__U340$lut$lut.bit.in.0","d_2_am__U339$lut$lut.bit.out"], - ["d_2_am__U340$lut$lut.bit.in.2","d_2_am__U340$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U340$lut$lut.bit.in.1"], - ["d_2_am__U341$lut$lut.bit.in.0","d_2_am__U340$lut$lut.bit.out"], - ["d_2_am__U341$lut$lut.bit.in.2","d_2_am__U341$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U341$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U341$lut$lut.bit.out"], + ["d_2_am__U347$lut$lut.bit.in.2","d_2_am__U347$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U347$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U347$lut$lut.bit.in.1"], + ["d_2_am__U348$lut$lut.bit.in.0","d_2_am__U347$lut$lut.bit.out"], + ["d_2_am__U348$lut$lut.bit.in.2","d_2_am__U348$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U348$lut$lut.bit.in.1"], + ["d_2_am__U349$lut$lut.bit.in.0","d_2_am__U348$lut$lut.bit.out"], + ["d_2_am__U349$lut$lut.bit.in.2","d_2_am__U349$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U349$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U349$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3885,19 +4237,13 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U342$lut$lut.bit.in.2","d_3_am__U342$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U342$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U342$lut$lut.bit.in.1"], - ["d_3_am__U343$lut$lut.bit.in.0","d_3_am__U342$lut$lut.bit.out"], - ["d_3_am__U343$lut$lut.bit.in.2","d_3_am__U343$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U343$lut$lut.bit.in.1"], - ["d_3_am__U344$lut$lut.bit.in.0","d_3_am__U343$lut$lut.bit.out"], - ["d_3_am__U344$lut$lut.bit.in.2","d_3_am__U344$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U344$lut$lut.bit.in.1"], - ["d_3_am__U345$lut$lut.bit.in.0","d_3_am__U344$lut$lut.bit.out"], - ["d_3_am__U345$lut$lut.bit.in.2","d_3_am__U345$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U345$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U345$lut$lut.bit.out"], + ["d_3_am__U350$lut$lut.bit.in.2","d_3_am__U350$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U350$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U350$lut$lut.bit.in.1"], + ["d_3_am__U351$lut$lut.bit.in.0","d_3_am__U350$lut$lut.bit.out"], + ["d_3_am__U351$lut$lut.bit.in.2","d_3_am__U351$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U351$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U351$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3914,16 +4260,10 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U346$lut$lut.bit.in.2","d_4_am__U346$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U346$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U346$lut$lut.bit.in.1"], - ["d_4_am__U347$lut$lut.bit.in.0","d_4_am__U346$lut$lut.bit.out"], - ["d_4_am__U347$lut$lut.bit.in.2","d_4_am__U347$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U347$lut$lut.bit.in.1"], - ["d_4_am__U348$lut$lut.bit.in.0","d_4_am__U347$lut$lut.bit.out"], - ["d_4_am__U348$lut$lut.bit.in.2","d_4_am__U348$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U348$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U348$lut$lut.bit.out"], + ["d_4_am__U352$lut$lut.bit.in.2","d_4_am__U352$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U352$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U352$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U352$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3940,13 +4280,6 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U349$lut$lut.bit.in.2","d_5_am__U349$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U349$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U349$lut$lut.bit.in.1"], - ["d_5_am__U350$lut$lut.bit.in.0","d_5_am__U349$lut$lut.bit.out"], - ["d_5_am__U350$lut$lut.bit.in.2","d_5_am__U350$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U350$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U350$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -3956,175 +4289,103 @@ ["d_5_reg$reg0.out","d_5_next_value.in0"], ["d_5_next_value_at_max.out","d_5_next_value.in1"], ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["true_lutcnst.bit.out","d_5_next_value.sel"], ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], ["self.rst_n","d_5_reg$clrMux.sel"], ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U351$lut$lut.bit.in.2","d_6_am__U351$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U351$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U351$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U351$lut$lut.bit.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"], - ["d_7_reg$reg0.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg$reg0.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg$reg0.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg$enMux.in1","d_7_next_value.out"], - ["true_lutcnst.bit.out","d_7_next_value.sel"], - ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], - ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], - ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], - ["self.rst_n","d_7_reg$clrMux.sel"], - ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], - ["self.clk","d_7_reg$reg0.clk"], - ["self.d.7","d_7_reg$reg0.out"] + ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U398":{ + "affine_controller__U375":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",6,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U419":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4191":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4192":{ + "_U390":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4193":{ + "_U3901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4194":{ + "_U3902":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4195":{ + "_U3903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U420":{ + "_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U413":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U414":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U415":{ + "affine_func$add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U416":{ + "affine_func$add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U417":{ + "affine_func$add_all__U388":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U418":{ + "affine_func$add_all__U389":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U400":{ + "affine_func$coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U402":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003f00"]} - }, - "affine_func$coeff_2_U404":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000001c0"]} - }, - "affine_func$coeff_3_U406":{ + "affine_func$coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000020"]} + "modargs":{"value":[["BitVector",32],"32'h00000e00"]} }, - "affine_func$coeff_4_U408":{ + "affine_func$coeff_2_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "affine_func$coeff_5_U410":{ + "affine_func$coeff_3_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U412":{ + "affine_func$const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00006c00"]} - }, - "affine_func$mul_d0__U401":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U403":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h0000c37f"]} }, - "affine_func$mul_d2__U405":{ + "affine_func$mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U407":{ + "affine_func$mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U409":{ + "affine_func$mul_d2__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U411":{ + "affine_func$mul_d3__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4188,52 +4449,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U421$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U421$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U422$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U422$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U423$c0_lutcnst":{ + "d_0_am__U392$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U423$lut$lut":{ + "d_0_am__U392$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U424$c0_lutcnst":{ + "d_0_am__U393$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U424$lut$lut":{ + "d_0_am__U393$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U425$c0_lutcnst":{ + "d_0_am__U394$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U425$lut$lut":{ + "d_0_am__U394$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4282,42 +4523,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U426$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U426$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U427$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U427$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U428$c0_lutcnst":{ + "d_1_am__U395$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U428$lut$lut":{ + "d_1_am__U395$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U429$c0_lutcnst":{ + "d_1_am__U396$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U429$lut$lut":{ + "d_1_am__U396$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4333,7 +4554,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h0000000d"]} }, "d_1_min":{ "genref":"coreir.const", @@ -4366,32 +4587,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U430$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U430$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U431$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U431$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U432$c0_lutcnst":{ + "d_2_am__U397$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U432$lut$lut":{ + "d_2_am__U397$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4440,26 +4641,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U433$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U433$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U434$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U434$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -4471,7 +4652,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + "modargs":{"value":[["BitVector",32],"32'h000000ff"]} }, "d_3_min":{ "genref":"coreir.const", @@ -4499,105 +4680,7 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_am__U435$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U435$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_5_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_5_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_5_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_5_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -4631,16 +4714,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4648,45 +4721,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U419.out"], - ["d_1_inc.in1","_U4191.out"], - ["d_2_inc.in1","_U4192.out"], - ["d_3_inc.in1","_U4193.out"], - ["d_4_inc.in1","_U4194.out"], - ["d_5_inc.in1","_U4195.out"], - ["cmp_time.in1","_U420.out"], - ["affine_func$mul_d0__U401.out","affine_func$add_all__U413.in0"], - ["affine_func$mul_d1__U403.out","affine_func$add_all__U413.in1"], - ["affine_func$add_all__U414.in0","affine_func$add_all__U413.out"], - ["affine_func$mul_d2__U405.out","affine_func$add_all__U414.in1"], - ["affine_func$add_all__U415.in0","affine_func$add_all__U414.out"], - ["affine_func$mul_d3__U407.out","affine_func$add_all__U415.in1"], - ["affine_func$add_all__U416.in0","affine_func$add_all__U415.out"], - ["affine_func$mul_d4__U409.out","affine_func$add_all__U416.in1"], - ["affine_func$add_all__U417.in0","affine_func$add_all__U416.out"], - ["affine_func$mul_d5__U411.out","affine_func$add_all__U417.in1"], - ["affine_func$add_all__U418.in0","affine_func$add_all__U417.out"], - ["affine_func$const_term_U412.out","affine_func$add_all__U418.in1"], - ["time_diff.in0","affine_func$add_all__U418.out"], - ["affine_func$mul_d0__U401.in0","affine_func$coeff_0_U400.out"], - ["affine_func$mul_d1__U403.in0","affine_func$coeff_1_U402.out"], - ["affine_func$mul_d2__U405.in0","affine_func$coeff_2_U404.out"], - ["affine_func$mul_d3__U407.in0","affine_func$coeff_3_U406.out"], - ["affine_func$mul_d4__U409.in0","affine_func$coeff_4_U408.out"], - ["affine_func$mul_d5__U411.in0","affine_func$coeff_5_U410.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U401.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U403.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U405.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U407.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U409.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U411.in1"], + ["d_0_inc.in1","_U390.out"], + ["d_1_inc.in1","_U3901.out"], + ["d_2_inc.in1","_U3902.out"], + ["d_3_inc.in1","_U3903.out"], + ["cmp_time.in1","_U391.out"], + ["affine_func$mul_d0__U378.out","affine_func$add_all__U386.in0"], + ["affine_func$mul_d1__U380.out","affine_func$add_all__U386.in1"], + ["affine_func$add_all__U387.in0","affine_func$add_all__U386.out"], + ["affine_func$mul_d2__U382.out","affine_func$add_all__U387.in1"], + ["affine_func$add_all__U388.in0","affine_func$add_all__U387.out"], + ["affine_func$mul_d3__U384.out","affine_func$add_all__U388.in1"], + ["affine_func$add_all__U389.in0","affine_func$add_all__U388.out"], + ["affine_func$const_term_U385.out","affine_func$add_all__U389.in1"], + ["time_diff.in0","affine_func$add_all__U389.out"], + ["affine_func$mul_d0__U378.in0","affine_func$coeff_0_U377.out"], + ["affine_func$mul_d1__U380.in0","affine_func$coeff_1_U379.out"], + ["affine_func$mul_d2__U382.in0","affine_func$coeff_2_U381.out"], + ["affine_func$mul_d3__U384.in0","affine_func$coeff_3_U383.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U378.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U380.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U382.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U384.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -4694,34 +4755,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U421$lut$lut.bit.in.2","d_0_am__U421$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U421$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U421$lut$lut.bit.in.1"], - ["d_0_am__U422$lut$lut.bit.in.0","d_0_am__U421$lut$lut.bit.out"], - ["d_0_am__U422$lut$lut.bit.in.2","d_0_am__U422$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U422$lut$lut.bit.in.1"], - ["d_0_am__U423$lut$lut.bit.in.0","d_0_am__U422$lut$lut.bit.out"], - ["d_0_am__U423$lut$lut.bit.in.2","d_0_am__U423$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U423$lut$lut.bit.in.1"], - ["d_0_am__U424$lut$lut.bit.in.0","d_0_am__U423$lut$lut.bit.out"], - ["d_0_am__U424$lut$lut.bit.in.2","d_0_am__U424$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U424$lut$lut.bit.in.1"], - ["d_0_am__U425$lut$lut.bit.in.0","d_0_am__U424$lut$lut.bit.out"], - ["d_0_am__U425$lut$lut.bit.in.2","d_0_am__U425$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U425$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U425$lut$lut.bit.out"], + ["d_0_am__U392$lut$lut.bit.in.2","d_0_am__U392$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U392$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U392$lut$lut.bit.in.1"], + ["d_0_am__U393$lut$lut.bit.in.0","d_0_am__U392$lut$lut.bit.out"], + ["d_0_am__U393$lut$lut.bit.in.2","d_0_am__U393$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U393$lut$lut.bit.in.1"], + ["d_0_am__U394$lut$lut.bit.in.0","d_0_am__U393$lut$lut.bit.out"], + ["d_0_am__U394$lut$lut.bit.in.2","d_0_am__U394$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U394$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U394$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4738,19 +4793,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U426$lut$lut.bit.in.2","d_1_am__U426$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U426$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U426$lut$lut.bit.in.1"], - ["d_1_am__U427$lut$lut.bit.in.0","d_1_am__U426$lut$lut.bit.out"], - ["d_1_am__U427$lut$lut.bit.in.2","d_1_am__U427$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U427$lut$lut.bit.in.1"], - ["d_1_am__U428$lut$lut.bit.in.0","d_1_am__U427$lut$lut.bit.out"], - ["d_1_am__U428$lut$lut.bit.in.2","d_1_am__U428$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U428$lut$lut.bit.in.1"], - ["d_1_am__U429$lut$lut.bit.in.0","d_1_am__U428$lut$lut.bit.out"], - ["d_1_am__U429$lut$lut.bit.in.2","d_1_am__U429$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U429$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U429$lut$lut.bit.out"], + ["d_1_am__U395$lut$lut.bit.in.2","d_1_am__U395$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U395$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U395$lut$lut.bit.in.1"], + ["d_1_am__U396$lut$lut.bit.in.0","d_1_am__U395$lut$lut.bit.out"], + ["d_1_am__U396$lut$lut.bit.in.2","d_1_am__U396$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U396$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U396$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4767,16 +4816,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U430$lut$lut.bit.in.2","d_2_am__U430$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U430$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U430$lut$lut.bit.in.1"], - ["d_2_am__U431$lut$lut.bit.in.0","d_2_am__U430$lut$lut.bit.out"], - ["d_2_am__U431$lut$lut.bit.in.2","d_2_am__U431$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U431$lut$lut.bit.in.1"], - ["d_2_am__U432$lut$lut.bit.in.0","d_2_am__U431$lut$lut.bit.out"], - ["d_2_am__U432$lut$lut.bit.in.2","d_2_am__U432$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U432$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U432$lut$lut.bit.out"], + ["d_2_am__U397$lut$lut.bit.in.2","d_2_am__U397$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U397$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U397$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U397$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4793,13 +4836,6 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U433$lut$lut.bit.in.2","d_3_am__U433$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U433$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U433$lut$lut.bit.in.1"], - ["d_3_am__U434$lut$lut.bit.in.0","d_3_am__U433$lut$lut.bit.out"], - ["d_3_am__U434$lut$lut.bit.in.2","d_3_am__U434$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U434$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U434$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4809,139 +4845,139 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U435$lut$lut.bit.in.2","d_4_am__U435$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U435$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U435$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U435$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["true_lutcnst.bit.out","d_5_next_value.sel"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U458":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",6,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U473":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4731":{ + "_U681":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4732":{ + "_U682":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4733":{ + "_U683":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U474":{ + "_U684":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U685":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U69":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U469":{ + "affine_func$add_all__U62":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U470":{ + "affine_func$add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U471":{ + "affine_func$add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U472":{ + "affine_func$add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U460":{ + "affine_func$add_all__U67":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U462":{ + "affine_func$coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000e00"]} + "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "affine_func$coeff_2_U464":{ + "affine_func$coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00001f80"]} + }, + "affine_func$coeff_3_U55":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "affine_func$coeff_4_U57":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_3_U466":{ + "affine_func$coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U468":{ + "affine_func$const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000c37f"]} + "modargs":{"value":[["BitVector",32],"32'h000023ff"]} + }, + "affine_func$mul_d0__U50":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U461":{ + "affine_func$mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U463":{ + "affine_func$mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U465":{ + "affine_func$mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U467":{ + "affine_func$mul_d4__U58":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5005,32 +5041,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U475$c0_lutcnst":{ + "d_0_am__U70$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U70$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U71$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U71$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U72$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U475$lut$lut":{ + "d_0_am__U72$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U476$c0_lutcnst":{ + "d_0_am__U73$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U476$lut$lut":{ + "d_0_am__U73$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U477$c0_lutcnst":{ + "d_0_am__U74$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U477$lut$lut":{ + "d_0_am__U74$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5079,22 +5135,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U478$c0_lutcnst":{ + "d_1_am__U75$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U75$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U76$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U76$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U77$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U478$lut$lut":{ + "d_1_am__U77$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U479$c0_lutcnst":{ + "d_1_am__U78$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U479$lut$lut":{ + "d_1_am__U78$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5110,7 +5186,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -5143,12 +5219,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U480$c0_lutcnst":{ + "d_2_am__U79$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U79$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U80$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U80$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U81$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U480$lut$lut":{ + "d_2_am__U81$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5164,7 +5260,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000d"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -5197,6 +5293,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U82$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U82$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U83$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U83$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -5208,7 +5324,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000000ff"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -5232,11 +5348,109 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$enMux":{ + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U84$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U84$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -5270,6 +5484,16 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -5277,33 +5501,45 @@ } }, "connections":[ - ["d_0_inc.in1","_U473.out"], - ["d_1_inc.in1","_U4731.out"], - ["d_2_inc.in1","_U4732.out"], - ["d_3_inc.in1","_U4733.out"], - ["cmp_time.in1","_U474.out"], - ["affine_func$mul_d0__U461.out","affine_func$add_all__U469.in0"], - ["affine_func$mul_d1__U463.out","affine_func$add_all__U469.in1"], - ["affine_func$add_all__U470.in0","affine_func$add_all__U469.out"], - ["affine_func$mul_d2__U465.out","affine_func$add_all__U470.in1"], - ["affine_func$add_all__U471.in0","affine_func$add_all__U470.out"], - ["affine_func$mul_d3__U467.out","affine_func$add_all__U471.in1"], - ["affine_func$add_all__U472.in0","affine_func$add_all__U471.out"], - ["affine_func$const_term_U468.out","affine_func$add_all__U472.in1"], - ["time_diff.in0","affine_func$add_all__U472.out"], - ["affine_func$mul_d0__U461.in0","affine_func$coeff_0_U460.out"], - ["affine_func$mul_d1__U463.in0","affine_func$coeff_1_U462.out"], - ["affine_func$mul_d2__U465.in0","affine_func$coeff_2_U464.out"], - ["affine_func$mul_d3__U467.in0","affine_func$coeff_3_U466.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U461.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U463.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U465.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U467.in1"], + ["d_0_inc.in1","_U68.out"], + ["d_1_inc.in1","_U681.out"], + ["d_2_inc.in1","_U682.out"], + ["d_3_inc.in1","_U683.out"], + ["d_4_inc.in1","_U684.out"], + ["d_5_inc.in1","_U685.out"], + ["cmp_time.in1","_U69.out"], + ["affine_func$mul_d0__U50.out","affine_func$add_all__U62.in0"], + ["affine_func$mul_d1__U52.out","affine_func$add_all__U62.in1"], + ["affine_func$add_all__U63.in0","affine_func$add_all__U62.out"], + ["affine_func$mul_d2__U54.out","affine_func$add_all__U63.in1"], + ["affine_func$add_all__U64.in0","affine_func$add_all__U63.out"], + ["affine_func$mul_d3__U56.out","affine_func$add_all__U64.in1"], + ["affine_func$add_all__U65.in0","affine_func$add_all__U64.out"], + ["affine_func$mul_d4__U58.out","affine_func$add_all__U65.in1"], + ["affine_func$add_all__U66.in0","affine_func$add_all__U65.out"], + ["affine_func$mul_d5__U60.out","affine_func$add_all__U66.in1"], + ["affine_func$add_all__U67.in0","affine_func$add_all__U66.out"], + ["affine_func$const_term_U61.out","affine_func$add_all__U67.in1"], + ["time_diff.in0","affine_func$add_all__U67.out"], + ["affine_func$mul_d0__U50.in0","affine_func$coeff_0_U49.out"], + ["affine_func$mul_d1__U52.in0","affine_func$coeff_1_U51.out"], + ["affine_func$mul_d2__U54.in0","affine_func$coeff_2_U53.out"], + ["affine_func$mul_d3__U56.in0","affine_func$coeff_3_U55.out"], + ["affine_func$mul_d4__U58.in0","affine_func$coeff_4_U57.out"], + ["affine_func$mul_d5__U60.in0","affine_func$coeff_5_U59.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U50.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U52.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U54.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U56.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U58.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U60.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -5311,28 +5547,34 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U475$lut$lut.bit.in.2","d_0_am__U475$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U475$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U475$lut$lut.bit.in.1"], - ["d_0_am__U476$lut$lut.bit.in.0","d_0_am__U475$lut$lut.bit.out"], - ["d_0_am__U476$lut$lut.bit.in.2","d_0_am__U476$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U476$lut$lut.bit.in.1"], - ["d_0_am__U477$lut$lut.bit.in.0","d_0_am__U476$lut$lut.bit.out"], - ["d_0_am__U477$lut$lut.bit.in.2","d_0_am__U477$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U477$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U477$lut$lut.bit.out"], + ["d_0_am__U70$lut$lut.bit.in.2","d_0_am__U70$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U70$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U70$lut$lut.bit.in.1"], + ["d_0_am__U71$lut$lut.bit.in.0","d_0_am__U70$lut$lut.bit.out"], + ["d_0_am__U71$lut$lut.bit.in.2","d_0_am__U71$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U71$lut$lut.bit.in.1"], + ["d_0_am__U72$lut$lut.bit.in.0","d_0_am__U71$lut$lut.bit.out"], + ["d_0_am__U72$lut$lut.bit.in.2","d_0_am__U72$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U72$lut$lut.bit.in.1"], + ["d_0_am__U73$lut$lut.bit.in.0","d_0_am__U72$lut$lut.bit.out"], + ["d_0_am__U73$lut$lut.bit.in.2","d_0_am__U73$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U73$lut$lut.bit.in.1"], + ["d_0_am__U74$lut$lut.bit.in.0","d_0_am__U73$lut$lut.bit.out"], + ["d_0_am__U74$lut$lut.bit.in.2","d_0_am__U74$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U74$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U74$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5349,13 +5591,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U478$lut$lut.bit.in.2","d_1_am__U478$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U478$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U478$lut$lut.bit.in.1"], - ["d_1_am__U479$lut$lut.bit.in.0","d_1_am__U478$lut$lut.bit.out"], - ["d_1_am__U479$lut$lut.bit.in.2","d_1_am__U479$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U479$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U479$lut$lut.bit.out"], + ["d_1_am__U75$lut$lut.bit.in.2","d_1_am__U75$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U75$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U75$lut$lut.bit.in.1"], + ["d_1_am__U76$lut$lut.bit.in.0","d_1_am__U75$lut$lut.bit.out"], + ["d_1_am__U76$lut$lut.bit.in.2","d_1_am__U76$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U76$lut$lut.bit.in.1"], + ["d_1_am__U77$lut$lut.bit.in.0","d_1_am__U76$lut$lut.bit.out"], + ["d_1_am__U77$lut$lut.bit.in.2","d_1_am__U77$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U77$lut$lut.bit.in.1"], + ["d_1_am__U78$lut$lut.bit.in.0","d_1_am__U77$lut$lut.bit.out"], + ["d_1_am__U78$lut$lut.bit.in.2","d_1_am__U78$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U78$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U78$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5372,10 +5620,16 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U480$lut$lut.bit.in.2","d_2_am__U480$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U480$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U480$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U480$lut$lut.bit.out"], + ["d_2_am__U79$lut$lut.bit.in.2","d_2_am__U79$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U79$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U79$lut$lut.bit.in.1"], + ["d_2_am__U80$lut$lut.bit.in.0","d_2_am__U79$lut$lut.bit.out"], + ["d_2_am__U80$lut$lut.bit.in.2","d_2_am__U80$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U80$lut$lut.bit.in.1"], + ["d_2_am__U81$lut$lut.bit.in.0","d_2_am__U80$lut$lut.bit.out"], + ["d_2_am__U81$lut$lut.bit.in.2","d_2_am__U81$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U81$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U81$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5392,6 +5646,13 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U82$lut$lut.bit.in.2","d_3_am__U82$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U82$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U82$lut$lut.bit.in.1"], + ["d_3_am__U83$lut$lut.bit.in.0","d_3_am__U82$lut$lut.bit.out"], + ["d_3_am__U83$lut$lut.bit.in.2","d_3_am__U83$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U83$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U83$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5401,139 +5662,139 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U84$lut$lut.bit.in.2","d_4_am__U84$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U84$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U84$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U84$lut$lut.bit.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["true_lutcnst.bit.out","d_5_next_value.sel"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",6,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U77":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U771":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U772":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U773":{ + "_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U774":{ + "_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U775":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U78":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U71":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U72":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U73":{ + "affine_func$add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U74":{ + "affine_func$add_all__U20":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U75":{ + "affine_func$add_all__U21":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U76":{ + "affine_func$add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U58":{ + "affine_func$coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U60":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003f00"]} - }, - "affine_func$coeff_2_U62":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001f80"]} - }, - "affine_func$coeff_3_U64":{ + "affine_func$coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "affine_func$coeff_4_U66":{ + "affine_func$coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_5_U68":{ + "affine_func$coeff_3_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U70":{ + "affine_func$const_term_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000023ff"]} - }, - "affine_func$mul_d0__U59":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U61":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d2__U63":{ + "affine_func$mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U65":{ + "affine_func$mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U67":{ + "affine_func$mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U69":{ + "affine_func$mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5597,52 +5858,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U79$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U79$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U80$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U80$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U81$c0_lutcnst":{ + "d_0_am__U25$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U81$lut$lut":{ + "d_0_am__U25$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U82$c0_lutcnst":{ + "d_0_am__U26$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U82$lut$lut":{ + "d_0_am__U26$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U83$c0_lutcnst":{ + "d_0_am__U27$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U83$lut$lut":{ + "d_0_am__U27$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5691,42 +5932,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U84$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U84$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U85$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U85$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U86$c0_lutcnst":{ + "d_1_am__U28$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U86$lut$lut":{ + "d_1_am__U28$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U87$c0_lutcnst":{ + "d_1_am__U29$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U87$lut$lut":{ + "d_1_am__U29$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5742,7 +5963,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -5770,243 +5991,105 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U88$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U88$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U89$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U89$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U90$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U90$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U91$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U91$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U92$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U92$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U93$c0_lutcnst":{ + "d_2_am__U30$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U93$lut$lut":{ + "d_2_am__U30$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, - "d_4_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, - "d_5_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -6040,16 +6123,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6057,45 +6130,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U77.out"], - ["d_1_inc.in1","_U771.out"], - ["d_2_inc.in1","_U772.out"], - ["d_3_inc.in1","_U773.out"], - ["d_4_inc.in1","_U774.out"], - ["d_5_inc.in1","_U775.out"], - ["cmp_time.in1","_U78.out"], - ["affine_func$mul_d0__U59.out","affine_func$add_all__U71.in0"], - ["affine_func$mul_d1__U61.out","affine_func$add_all__U71.in1"], - ["affine_func$add_all__U72.in0","affine_func$add_all__U71.out"], - ["affine_func$mul_d2__U63.out","affine_func$add_all__U72.in1"], - ["affine_func$add_all__U73.in0","affine_func$add_all__U72.out"], - ["affine_func$mul_d3__U65.out","affine_func$add_all__U73.in1"], - ["affine_func$add_all__U74.in0","affine_func$add_all__U73.out"], - ["affine_func$mul_d4__U67.out","affine_func$add_all__U74.in1"], - ["affine_func$add_all__U75.in0","affine_func$add_all__U74.out"], - ["affine_func$mul_d5__U69.out","affine_func$add_all__U75.in1"], - ["affine_func$add_all__U76.in0","affine_func$add_all__U75.out"], - ["affine_func$const_term_U70.out","affine_func$add_all__U76.in1"], - ["time_diff.in0","affine_func$add_all__U76.out"], - ["affine_func$mul_d0__U59.in0","affine_func$coeff_0_U58.out"], - ["affine_func$mul_d1__U61.in0","affine_func$coeff_1_U60.out"], - ["affine_func$mul_d2__U63.in0","affine_func$coeff_2_U62.out"], - ["affine_func$mul_d3__U65.in0","affine_func$coeff_3_U64.out"], - ["affine_func$mul_d4__U67.in0","affine_func$coeff_4_U66.out"], - ["affine_func$mul_d5__U69.in0","affine_func$coeff_5_U68.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U59.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U61.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U63.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U65.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U67.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U69.in1"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U231.out"], + ["d_2_inc.in1","_U232.out"], + ["d_3_inc.in1","_U233.out"], + ["cmp_time.in1","_U24.out"], + ["affine_func$mul_d0__U11.out","affine_func$add_all__U19.in0"], + ["affine_func$mul_d1__U13.out","affine_func$add_all__U19.in1"], + ["affine_func$add_all__U20.in0","affine_func$add_all__U19.out"], + ["affine_func$mul_d2__U15.out","affine_func$add_all__U20.in1"], + ["affine_func$add_all__U21.in0","affine_func$add_all__U20.out"], + ["affine_func$mul_d3__U17.out","affine_func$add_all__U21.in1"], + ["affine_func$add_all__U22.in0","affine_func$add_all__U21.out"], + ["affine_func$const_term_U18.out","affine_func$add_all__U22.in1"], + ["time_diff.in0","affine_func$add_all__U22.out"], + ["affine_func$mul_d0__U11.in0","affine_func$coeff_0_U10.out"], + ["affine_func$mul_d1__U13.in0","affine_func$coeff_1_U12.out"], + ["affine_func$mul_d2__U15.in0","affine_func$coeff_2_U14.out"], + ["affine_func$mul_d3__U17.in0","affine_func$coeff_3_U16.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U11.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U13.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U15.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U17.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -6103,34 +6164,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U79$lut$lut.bit.in.2","d_0_am__U79$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U79$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U79$lut$lut.bit.in.1"], - ["d_0_am__U80$lut$lut.bit.in.0","d_0_am__U79$lut$lut.bit.out"], - ["d_0_am__U80$lut$lut.bit.in.2","d_0_am__U80$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U80$lut$lut.bit.in.1"], - ["d_0_am__U81$lut$lut.bit.in.0","d_0_am__U80$lut$lut.bit.out"], - ["d_0_am__U81$lut$lut.bit.in.2","d_0_am__U81$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U81$lut$lut.bit.in.1"], - ["d_0_am__U82$lut$lut.bit.in.0","d_0_am__U81$lut$lut.bit.out"], - ["d_0_am__U82$lut$lut.bit.in.2","d_0_am__U82$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U82$lut$lut.bit.in.1"], - ["d_0_am__U83$lut$lut.bit.in.0","d_0_am__U82$lut$lut.bit.out"], - ["d_0_am__U83$lut$lut.bit.in.2","d_0_am__U83$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U83$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U83$lut$lut.bit.out"], + ["d_0_am__U25$lut$lut.bit.in.2","d_0_am__U25$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U25$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U25$lut$lut.bit.in.1"], + ["d_0_am__U26$lut$lut.bit.in.0","d_0_am__U25$lut$lut.bit.out"], + ["d_0_am__U26$lut$lut.bit.in.2","d_0_am__U26$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U26$lut$lut.bit.in.1"], + ["d_0_am__U27$lut$lut.bit.in.0","d_0_am__U26$lut$lut.bit.out"], + ["d_0_am__U27$lut$lut.bit.in.2","d_0_am__U27$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U27$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U27$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6147,19 +6202,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U84$lut$lut.bit.in.2","d_1_am__U84$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U84$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U84$lut$lut.bit.in.1"], - ["d_1_am__U85$lut$lut.bit.in.0","d_1_am__U84$lut$lut.bit.out"], - ["d_1_am__U85$lut$lut.bit.in.2","d_1_am__U85$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U85$lut$lut.bit.in.1"], - ["d_1_am__U86$lut$lut.bit.in.0","d_1_am__U85$lut$lut.bit.out"], - ["d_1_am__U86$lut$lut.bit.in.2","d_1_am__U86$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U86$lut$lut.bit.in.1"], - ["d_1_am__U87$lut$lut.bit.in.0","d_1_am__U86$lut$lut.bit.out"], - ["d_1_am__U87$lut$lut.bit.in.2","d_1_am__U87$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U87$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U87$lut$lut.bit.out"], + ["d_1_am__U28$lut$lut.bit.in.2","d_1_am__U28$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U28$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U28$lut$lut.bit.in.1"], + ["d_1_am__U29$lut$lut.bit.in.0","d_1_am__U28$lut$lut.bit.out"], + ["d_1_am__U29$lut$lut.bit.in.2","d_1_am__U29$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U29$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U29$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -6176,16 +6225,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U88$lut$lut.bit.in.2","d_2_am__U88$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U88$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U88$lut$lut.bit.in.1"], - ["d_2_am__U89$lut$lut.bit.in.0","d_2_am__U88$lut$lut.bit.out"], - ["d_2_am__U89$lut$lut.bit.in.2","d_2_am__U89$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U89$lut$lut.bit.in.1"], - ["d_2_am__U90$lut$lut.bit.in.0","d_2_am__U89$lut$lut.bit.out"], - ["d_2_am__U90$lut$lut.bit.in.2","d_2_am__U90$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U90$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U90$lut$lut.bit.out"], + ["d_2_am__U30$lut$lut.bit.in.2","d_2_am__U30$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U30$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U30$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U30$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -6202,13 +6245,6 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U91$lut$lut.bit.in.2","d_3_am__U91$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U91$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U91$lut$lut.bit.in.1"], - ["d_3_am__U92$lut$lut.bit.in.0","d_3_am__U91$lut$lut.bit.out"], - ["d_3_am__U92$lut$lut.bit.in.2","d_3_am__U92$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U92$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U92$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -6218,50 +6254,14 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U93$lut$lut.bit.in.2","d_4_am__U93$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U93$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U93$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U93$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["true_lutcnst.bit.out","d_5_next_value.sel"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"] ] }, "cu_op_hcompute_hw_output_stencil":{ @@ -6337,26 +6337,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U514":{ + "PE_init_U431":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U512":{ + "_U429":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U513":{ + "_U430":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U512.out","PE_init_U514.data.in.0"], - ["_U513.out","PE_init_U514.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U514.data.out"], + ["_U429.out","PE_init_U431.data.in.0"], + ["_U430.out","PE_init_U431.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U431.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6368,26 +6368,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U517":{ + "PE_init_U434":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U515":{ + "_U432":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U516":{ + "_U433":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U515.out","PE_init_U517.data.in.0"], - ["_U516.out","PE_init_U517.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U517.data.out"], + ["_U432.out","PE_init_U434.data.in.0"], + ["_U433.out","PE_init_U434.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U434.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7173,26 +7173,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U520":{ + "PE_init_U437":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U518":{ + "_U435":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U519":{ + "_U436":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U518.out","PE_init_U520.data.in.0"], - ["_U519.out","PE_init_U520.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U520.data.out"], + ["_U435.out","PE_init_U437.data.in.0"], + ["_U436.out","PE_init_U437.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U437.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7204,26 +7204,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U523":{ + "PE_init_U440":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U521":{ + "_U438":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U522":{ + "_U439":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U521.out","PE_init_U523.data.in.0"], - ["_U522.out","PE_init_U523.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U523.data.out"], + ["_U438.out","PE_init_U440.data.in.0"], + ["_U439.out","PE_init_U440.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U440.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7235,26 +7235,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U526":{ + "PE_init_U443":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U524":{ + "_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U525":{ + "_U442":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U524.out","PE_init_U526.data.in.0"], - ["_U525.out","PE_init_U526.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U526.data.out"], + ["_U441.out","PE_init_U443.data.in.0"], + ["_U442.out","PE_init_U443.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U443.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7266,26 +7266,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U529":{ + "PE_init_U446":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U527":{ + "_U444":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U528":{ + "_U445":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U527.out","PE_init_U529.data.in.0"], - ["_U528.out","PE_init_U529.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U529.data.out"], + ["_U444.out","PE_init_U446.data.in.0"], + ["_U445.out","PE_init_U446.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U446.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7297,26 +7297,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U532":{ + "PE_init_U449":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U530":{ + "_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U531":{ + "_U448":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U530.out","PE_init_U532.data.in.0"], - ["_U531.out","PE_init_U532.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U532.data.out"], + ["_U447.out","PE_init_U449.data.in.0"], + ["_U448.out","PE_init_U449.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U449.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7328,26 +7328,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U535":{ + "PE_init_U452":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U533":{ + "_U450":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U534":{ + "_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U533.out","PE_init_U535.data.in.0"], - ["_U534.out","PE_init_U535.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U535.data.out"], + ["_U450.out","PE_init_U452.data.in.0"], + ["_U451.out","PE_init_U452.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U452.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7672,26 +7672,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U538":{ + "PE_init_U455":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U536":{ + "_U453":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U537":{ + "_U454":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U536.out","PE_init_U538.data.in.0"], - ["_U537.out","PE_init_U538.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U538.data.out"] + ["_U453.out","PE_init_U455.data.in.0"], + ["_U454.out","PE_init_U455.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U455.data.out"] ] }, "hcompute_output_cgra_stencil_1":{ @@ -7699,26 +7699,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U541":{ + "PE_init_U458":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U539":{ + "_U456":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U540":{ + "_U457":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U539.out","PE_init_U541.data.in.0"], - ["_U540.out","PE_init_U541.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U541.data.out"] + ["_U456.out","PE_init_U458.data.in.0"], + ["_U457.out","PE_init_U458.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U458.data.out"] ] }, "hcompute_output_cgra_stencil_10":{ @@ -8476,26 +8476,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U544":{ + "PE_init_U461":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U542":{ + "_U459":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U543":{ + "_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U542.out","PE_init_U544.data.in.0"], - ["_U543.out","PE_init_U544.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U544.data.out"] + ["_U459.out","PE_init_U461.data.in.0"], + ["_U460.out","PE_init_U461.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U461.data.out"] ] }, "hcompute_output_cgra_stencil_3":{ @@ -8503,26 +8503,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U547":{ + "PE_init_U464":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U545":{ + "_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U546":{ + "_U463":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U545.out","PE_init_U547.data.in.0"], - ["_U546.out","PE_init_U547.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U547.data.out"] + ["_U462.out","PE_init_U464.data.in.0"], + ["_U463.out","PE_init_U464.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U464.data.out"] ] }, "hcompute_output_cgra_stencil_4":{ @@ -8530,26 +8530,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U550":{ + "PE_init_U467":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U548":{ + "_U465":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U549":{ + "_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U548.out","PE_init_U550.data.in.0"], - ["_U549.out","PE_init_U550.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U550.data.out"] + ["_U465.out","PE_init_U467.data.in.0"], + ["_U466.out","PE_init_U467.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U467.data.out"] ] }, "hcompute_output_cgra_stencil_5":{ @@ -8557,26 +8557,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U553":{ + "PE_init_U470":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U551":{ + "_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U552":{ + "_U469":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U551.out","PE_init_U553.data.in.0"], - ["_U552.out","PE_init_U553.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U553.data.out"] + ["_U468.out","PE_init_U470.data.in.0"], + ["_U469.out","PE_init_U470.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U470.data.out"] ] }, "hcompute_output_cgra_stencil_6":{ @@ -8584,26 +8584,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U556":{ + "PE_init_U473":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U554":{ + "_U471":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U555":{ + "_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U554.out","PE_init_U556.data.in.0"], - ["_U555.out","PE_init_U556.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U556.data.out"] + ["_U471.out","PE_init_U473.data.in.0"], + ["_U472.out","PE_init_U473.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U473.data.out"] ] }, "hcompute_output_cgra_stencil_7":{ @@ -8611,26 +8611,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U559":{ + "PE_init_U476":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U557":{ + "_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U558":{ + "_U475":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U557.out","PE_init_U559.data.in.0"], - ["_U558.out","PE_init_U559.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U559.data.out"] + ["_U474.out","PE_init_U476.data.in.0"], + ["_U475.out","PE_init_U476.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U476.data.out"] ] }, "hcompute_output_cgra_stencil_8":{ @@ -8917,38 +8917,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -8956,7 +8924,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -8966,7 +8934,7 @@ }, "ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -8976,7 +8944,7 @@ }, "ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -8986,7 +8954,7 @@ }, "ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -8996,7 +8964,7 @@ }, "ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -9006,7 +8974,7 @@ }, "ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2301],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -9016,7 +8984,7 @@ }, "ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -9026,7 +8994,7 @@ }, "ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -9168,262 +9136,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U118":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U120":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U122":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U124":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U126":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U128":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U130":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U136":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U138":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U140":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U142":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U144":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U146":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U148":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U150":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U152":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U154":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U156":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U158":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U160":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U164":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U166":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U168":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U170":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U172":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U174":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U176":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U178":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U180":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U182":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U184":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U186":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U188":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U190":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U194":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U196":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U198":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U200":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U202":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U204":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U206":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U208":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U210":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U212":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U214":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U216":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U218":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U220":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U222":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U224":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U226":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U228":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U230":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U232":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U234":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U236":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U238":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U240":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U242":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U244":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9431,7 +9143,7 @@ }, "ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -9441,7 +9153,7 @@ }, "ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -9451,7 +9163,7 @@ }, "ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -9461,7 +9173,7 @@ }, "ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -9471,7 +9183,7 @@ }, "ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -9481,7 +9193,7 @@ }, "ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -9491,7 +9203,7 @@ }, "ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -9501,7 +9213,7 @@ }, "ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -9511,7 +9223,7 @@ }, "ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -9521,7 +9233,7 @@ }, "ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -9531,7 +9243,7 @@ }, "ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -9541,7 +9253,7 @@ }, "ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U109"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -9551,7 +9263,7 @@ }, "ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -9561,7 +9273,7 @@ }, "ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -9571,7 +9283,7 @@ }, "ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -9581,7 +9293,7 @@ }, "ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -9591,7 +9303,7 @@ }, "ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -9601,7 +9313,7 @@ }, "ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -9611,7 +9323,7 @@ }, "ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -9621,7 +9333,7 @@ }, "ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -9631,7 +9343,7 @@ }, "ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -9641,7 +9353,7 @@ }, "ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -9651,7 +9363,7 @@ }, "ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -9661,7 +9373,7 @@ }, "ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -9671,7 +9383,7 @@ }, "ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -9681,7 +9393,7 @@ }, "ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -9691,7 +9403,7 @@ }, "ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -9701,7 +9413,7 @@ }, "ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -9711,7 +9423,7 @@ }, "ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -9721,7 +9433,7 @@ }, "ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -9731,7 +9443,7 @@ }, "ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -9741,7 +9453,7 @@ }, "ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -9751,7 +9463,7 @@ }, "ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -9761,7 +9473,7 @@ }, "ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -9771,7 +9483,7 @@ }, "ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U197"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -9781,7 +9493,7 @@ }, "ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U199"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -9791,7 +9503,7 @@ }, "ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U201"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -9801,7 +9513,7 @@ }, "ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U203"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -9811,7 +9523,7 @@ }, "ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U205"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -9821,7 +9533,7 @@ }, "ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U207"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -9831,7 +9543,7 @@ }, "ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -9841,7 +9553,7 @@ }, "ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -9851,7 +9563,7 @@ }, "ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -9861,7 +9573,7 @@ }, "ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -9871,7 +9583,7 @@ }, "ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -9881,7 +9593,7 @@ }, "ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -9891,7 +9603,7 @@ }, "ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -9901,7 +9613,7 @@ }, "ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -9911,7 +9623,7 @@ }, "ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -9921,7 +9633,7 @@ }, "ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -9931,7 +9643,7 @@ }, "ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -9941,7 +9653,7 @@ }, "ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -9951,7 +9663,7 @@ }, "ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -9961,7 +9673,7 @@ }, "ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -9971,7 +9683,7 @@ }, "ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -9981,7 +9693,7 @@ }, "ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -9991,7 +9703,7 @@ }, "ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -10001,7 +9713,7 @@ }, "ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -10011,7 +9723,7 @@ }, "ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -10021,7 +9733,7 @@ }, "ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -10031,7 +9743,7 @@ }, "ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -10041,7 +9753,7 @@ }, "ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -10051,7 +9763,7 @@ }, "ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -10061,7 +9773,7 @@ }, "ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -10402,7 +10114,7 @@ ["self.op_hcompute_kernel_glb_stencil_write.0","self.op_hcompute_kernel_cgra_stencil_read.0"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U500":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U417":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10411,7 +10123,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U499":{ + "op_hcompute_hw_output_stencil_read_start_pt__U416":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10420,7 +10132,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U501":{ + "op_hcompute_hw_output_stencil_write_start_pt__U418":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10429,7 +10141,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U509":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U426":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10438,7 +10150,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U508":{ + "op_hcompute_input_glb_stencil_read_start_pt__U425":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10447,7 +10159,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U510":{ + "op_hcompute_input_glb_stencil_write_start_pt__U427":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10456,7 +10168,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U504":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U421":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10465,7 +10177,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U503":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U420":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10474,7 +10186,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U505":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U422":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10540,38 +10252,6 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U384":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U386":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U388":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U390":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U392":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U394":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U396":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10579,7 +10259,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U381"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U307"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18429],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18432],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -10589,7 +10269,7 @@ }, "ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[2317],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18431],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18433],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -10599,7 +10279,7 @@ }, "ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U385"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U309"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18431],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18434],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -10609,7 +10289,7 @@ }, "ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U387"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18433],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18435],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -10619,7 +10299,7 @@ }, "ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18433],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18436],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -10629,7 +10309,7 @@ }, "ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U391"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18435],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18437],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -10639,7 +10319,7 @@ }, "ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U393"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U313"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18435],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18438],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -10649,7 +10329,7 @@ }, "ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U395"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18437],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18439],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -10738,158 +10418,126 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U562":{ + "PE_init_U479":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U565":{ + "PE_init_U482":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U568":{ + "PE_init_U485":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U571":{ + "PE_init_U488":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U574":{ + "PE_init_U491":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U577":{ + "PE_init_U494":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U580":{ + "PE_init_U497":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U583":{ + "PE_init_U500":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U560":{ + "_U477":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U561":{ + "_U478":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U563":{ + "_U480":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U564":{ + "_U481":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U566":{ + "_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U567":{ + "_U484":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U569":{ + "_U486":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U570":{ + "_U487":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U572":{ + "_U489":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U573":{ + "_U490":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U575":{ + "_U492":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U576":{ + "_U493":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U578":{ + "_U495":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U579":{ + "_U496":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U581":{ + "_U498":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U582":{ + "_U499":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "input_cgra_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10897,7 +10545,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -10907,7 +10555,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -10917,7 +10565,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -10927,7 +10575,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -10937,7 +10585,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -10947,7 +10595,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2301],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -10957,7 +10605,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -10967,7 +10615,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,128,8064],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,128,8064],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[16,64,896,2688,8064],"dimensionality":5,"extent":[4,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -10996,262 +10644,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "kernel_cgra_stencil$chain_en_const_U118":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U120":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U122":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U124":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U126":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U128":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U130":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U136":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U138":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U140":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U142":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U144":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U146":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U148":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U150":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U152":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U154":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U156":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U158":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U160":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U164":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U166":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U168":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U170":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U172":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U174":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U176":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U178":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U180":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U182":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U184":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U186":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U188":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U190":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U194":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U196":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U198":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U200":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U202":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U204":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U206":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U208":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U210":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U212":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U214":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U216":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U218":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U220":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U222":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U224":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U226":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U228":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U230":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U232":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U234":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U236":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U238":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U240":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U242":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U244":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -11259,7 +10651,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -11269,7 +10661,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -11279,7 +10671,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -11289,7 +10681,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -11299,7 +10691,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -11309,7 +10701,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -11319,7 +10711,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -11329,7 +10721,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -11339,7 +10731,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -11349,7 +10741,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -11359,7 +10751,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -11369,7 +10761,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U109"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -11379,7 +10771,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -11389,7 +10781,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -11399,7 +10791,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -11409,7 +10801,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -11419,7 +10811,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -11429,7 +10821,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -11439,7 +10831,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -11449,7 +10841,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -11459,7 +10851,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -11469,7 +10861,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -11479,7 +10871,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -11489,7 +10881,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -11499,7 +10891,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -11509,7 +10901,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -11519,7 +10911,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -11529,7 +10921,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -11539,7 +10931,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -11549,7 +10941,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -11559,7 +10951,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -11569,7 +10961,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -11579,7 +10971,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -11589,7 +10981,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -11599,7 +10991,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U197"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -11609,7 +11001,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U199"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -11619,7 +11011,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U201"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -11629,7 +11021,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U203"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -11639,7 +11031,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U205"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -11649,7 +11041,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U207"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -11659,7 +11051,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -11669,7 +11061,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -11679,7 +11071,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -11689,7 +11081,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -11699,7 +11091,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -11709,7 +11101,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -11719,7 +11111,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -11729,7 +11121,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -11739,7 +11131,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -11749,7 +11141,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -11759,7 +11151,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -11769,7 +11161,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -11779,7 +11171,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -11789,7 +11181,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -11799,7 +11191,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -11809,7 +11201,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -11819,7 +11211,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -11829,7 +11221,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -11839,7 +11231,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -11849,7 +11241,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -11859,7 +11251,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -11869,7 +11261,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -11879,7 +11271,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -11889,7 +11281,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,768,8064],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,256,768,8064],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2309],"cycle_stride":[4,64,896,2688,8064],"dimensionality":5,"extent":[14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,4,64,896,2688,8064],"dimensionality":6,"extent":[4,14,14,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -11899,7 +11291,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U498"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U415"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,16128],"dimensionality":3,"extent":[32,196,2],"write_data_starting_addr":[0],"write_data_stride":[1,256,32]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_output_cgra_stencil_10$inner_compute$add_957_971_972$binop":{ @@ -12542,38 +11934,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "output_cgra_stencil$chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U384":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U386":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U388":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U390":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U392":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U394":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U396":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -12581,7 +11941,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U381"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U307"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18429],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18432],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -12591,7 +11951,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"agg2sram_1":{"cycle_starting_addr":[2317],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"in2agg_1":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18431],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18433],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -12601,7 +11961,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U385"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U309"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18431],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18434],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -12611,7 +11971,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U387"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18433],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18435],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -12621,7 +11981,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18433],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18436],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -12631,7 +11991,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U391"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18435],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18437],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -12641,7 +12001,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U393"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U313"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18435],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18438],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -12651,35 +12011,35 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U395"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2316],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,56,16128],"dimensionality":3,"extent":[14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,14,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,56,16128],"dimensionality":4,"extent":[4,14,14,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,8,0]},"sram2tb_0":{"cycle_starting_addr":[2310],"cycle_stride":[4,64,896,2688,8064,16128],"dimensionality":6,"extent":[14,14,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,14,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[18437],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,14,196],"write_data_starting_addr":[0],"write_data_stride":[0,1,2,0]},"tb2out_0":{"cycle_starting_addr":[2312],"cycle_stride":[1,64,896,16128],"dimensionality":4,"extent":[56,14,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0]},"tb2out_1":{"cycle_starting_addr":[18439],"cycle_stride":[8,32,448,16128],"dimensionality":4,"extent":[4,14,14,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U560.out","PE_init_U562.data.in.0"], - ["_U561.out","PE_init_U562.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U562.data.out"], - ["_U563.out","PE_init_U565.data.in.0"], - ["_U564.out","PE_init_U565.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U565.data.out"], - ["_U566.out","PE_init_U568.data.in.0"], - ["_U567.out","PE_init_U568.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U568.data.out"], - ["_U569.out","PE_init_U571.data.in.0"], - ["_U570.out","PE_init_U571.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U571.data.out"], - ["_U572.out","PE_init_U574.data.in.0"], - ["_U573.out","PE_init_U574.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U574.data.out"], - ["_U575.out","PE_init_U577.data.in.0"], - ["_U576.out","PE_init_U577.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U577.data.out"], - ["_U578.out","PE_init_U580.data.in.0"], - ["_U579.out","PE_init_U580.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U580.data.out"], - ["_U581.out","PE_init_U583.data.in.0"], - ["_U582.out","PE_init_U583.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U583.data.out"], + ["_U477.out","PE_init_U479.data.in.0"], + ["_U478.out","PE_init_U479.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U479.data.out"], + ["_U480.out","PE_init_U482.data.in.0"], + ["_U481.out","PE_init_U482.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U482.data.out"], + ["_U483.out","PE_init_U485.data.in.0"], + ["_U484.out","PE_init_U485.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U485.data.out"], + ["_U486.out","PE_init_U488.data.in.0"], + ["_U487.out","PE_init_U488.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U488.data.out"], + ["_U489.out","PE_init_U491.data.in.0"], + ["_U490.out","PE_init_U491.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U491.data.out"], + ["_U492.out","PE_init_U494.data.in.0"], + ["_U493.out","PE_init_U494.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U494.data.out"], + ["_U495.out","PE_init_U497.data.in.0"], + ["_U496.out","PE_init_U497.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U497.data.out"], + ["_U498.out","PE_init_U500.data.in.0"], + ["_U499.out","PE_init_U500.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U500.data.out"], ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_input_host_stencil_op_hcompute_input_glb_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_output_cgra_stencil_10$inner_compute$mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957$binop.data.in.1","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_new/resnet5_1/resnet5_1.json b/aha_garnet_design_new/resnet5_1/resnet5_1.json index 2bfa631d6..bfc88a827 100644 --- a/aha_garnet_design_new/resnet5_1/resnet5_1.json +++ b/aha_garnet_design_new/resnet5_1/resnet5_1.json @@ -2,1587 +2,1321 @@ "namespaces":{ "global":{ "modules":{ - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U247":{ + "aff__U173":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U259":{ + "add_all__U185":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U260":{ + "add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U261":{ + "add_all__U187":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U262":{ + "add_all__U188":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U263":{ + "add_all__U189":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U248":{ + "coeff_0_U174":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U250":{ + "coeff_1_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U252":{ + "coeff_2_U178":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U254":{ + "coeff_3_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U256":{ + "coeff_4_U182":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U258":{ + "const_term_U184":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U249":{ + "mul_d0__U175":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U251":{ + "mul_d1__U177":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U253":{ + "mul_d2__U179":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U255":{ + "mul_d3__U181":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U257":{ + "mul_d4__U183":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U249.out","add_all__U259.in0"], - ["mul_d1__U251.out","add_all__U259.in1"], - ["add_all__U260.in0","add_all__U259.out"], - ["mul_d2__U253.out","add_all__U260.in1"], - ["add_all__U261.in0","add_all__U260.out"], - ["mul_d3__U255.out","add_all__U261.in1"], - ["add_all__U262.in0","add_all__U261.out"], - ["mul_d4__U257.out","add_all__U262.in1"], - ["add_all__U263.in0","add_all__U262.out"], - ["const_term_U258.out","add_all__U263.in1"], - ["self.out","add_all__U263.out"], - ["mul_d0__U249.in0","coeff_0_U248.out"], - ["mul_d1__U251.in0","coeff_1_U250.out"], - ["mul_d2__U253.in0","coeff_2_U252.out"], - ["mul_d3__U255.in0","coeff_3_U254.out"], - ["mul_d4__U257.in0","coeff_4_U256.out"], - ["self.d.0","mul_d0__U249.in1"], - ["self.d.1","mul_d1__U251.in1"], - ["self.d.2","mul_d2__U253.in1"], - ["self.d.3","mul_d3__U255.in1"], - ["self.d.4","mul_d4__U257.in1"] + ["mul_d0__U175.out","add_all__U185.in0"], + ["mul_d1__U177.out","add_all__U185.in1"], + ["add_all__U186.in0","add_all__U185.out"], + ["mul_d2__U179.out","add_all__U186.in1"], + ["add_all__U187.in0","add_all__U186.out"], + ["mul_d3__U181.out","add_all__U187.in1"], + ["add_all__U188.in0","add_all__U187.out"], + ["mul_d4__U183.out","add_all__U188.in1"], + ["add_all__U189.in0","add_all__U188.out"], + ["const_term_U184.out","add_all__U189.in1"], + ["self.out","add_all__U189.out"], + ["mul_d0__U175.in0","coeff_0_U174.out"], + ["mul_d1__U177.in0","coeff_1_U176.out"], + ["mul_d2__U179.in0","coeff_2_U178.out"], + ["mul_d3__U181.in0","coeff_3_U180.out"], + ["mul_d4__U183.in0","coeff_4_U182.out"], + ["self.d.0","mul_d0__U175.in1"], + ["self.d.1","mul_d1__U177.in1"], + ["self.d.2","mul_d2__U179.in1"], + ["self.d.3","mul_d3__U181.in1"], + ["self.d.4","mul_d4__U183.in1"] ] }, - "aff__U277":{ + "aff__U203":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U289":{ + "add_all__U215":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U290":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U291":{ + "add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U292":{ + "add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U293":{ + "add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U278":{ + "coeff_0_U204":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U280":{ + "coeff_1_U206":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U282":{ + "coeff_2_U208":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U284":{ + "coeff_3_U210":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U286":{ + "coeff_4_U212":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U288":{ + "const_term_U214":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U279":{ + "mul_d0__U205":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U281":{ + "mul_d1__U207":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U283":{ + "mul_d2__U209":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U285":{ + "mul_d3__U211":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U287":{ + "mul_d4__U213":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U279.out","add_all__U289.in0"], - ["mul_d1__U281.out","add_all__U289.in1"], - ["add_all__U290.in0","add_all__U289.out"], - ["mul_d2__U283.out","add_all__U290.in1"], - ["add_all__U291.in0","add_all__U290.out"], - ["mul_d3__U285.out","add_all__U291.in1"], - ["add_all__U292.in0","add_all__U291.out"], - ["mul_d4__U287.out","add_all__U292.in1"], - ["add_all__U293.in0","add_all__U292.out"], - ["const_term_U288.out","add_all__U293.in1"], - ["self.out","add_all__U293.out"], - ["mul_d0__U279.in0","coeff_0_U278.out"], - ["mul_d1__U281.in0","coeff_1_U280.out"], - ["mul_d2__U283.in0","coeff_2_U282.out"], - ["mul_d3__U285.in0","coeff_3_U284.out"], - ["mul_d4__U287.in0","coeff_4_U286.out"], - ["self.d.0","mul_d0__U279.in1"], - ["self.d.1","mul_d1__U281.in1"], - ["self.d.2","mul_d2__U283.in1"], - ["self.d.3","mul_d3__U285.in1"], - ["self.d.4","mul_d4__U287.in1"] + ["mul_d0__U205.out","add_all__U215.in0"], + ["mul_d1__U207.out","add_all__U215.in1"], + ["add_all__U216.in0","add_all__U215.out"], + ["mul_d2__U209.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d3__U211.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d4__U213.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["const_term_U214.out","add_all__U219.in1"], + ["self.out","add_all__U219.out"], + ["mul_d0__U205.in0","coeff_0_U204.out"], + ["mul_d1__U207.in0","coeff_1_U206.out"], + ["mul_d2__U209.in0","coeff_2_U208.out"], + ["mul_d3__U211.in0","coeff_3_U210.out"], + ["mul_d4__U213.in0","coeff_4_U212.out"], + ["self.d.0","mul_d0__U205.in1"], + ["self.d.1","mul_d1__U207.in1"], + ["self.d.2","mul_d2__U209.in1"], + ["self.d.3","mul_d3__U211.in1"], + ["self.d.4","mul_d4__U213.in1"] ] }, - "aff__U296":{ + "aff__U222":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U319":{ + "add_all__U245":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U320":{ + "add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U321":{ + "add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U297":{ + "coeff_0_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U299":{ + "coeff_1_U225":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_2_U301":{ + "coeff_2_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U303":{ + "coeff_3_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_4_U305":{ + "coeff_4_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_5_U307":{ + "coeff_5_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_6_U309":{ + "coeff_6_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U311":{ + "coeff_7_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U298":{ + "mul_d0__U224":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U300":{ + "mul_d1__U226":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U302":{ + "mul_d2__U228":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U304":{ + "mul_d3__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U306":{ + "mul_d4__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U308":{ + "mul_d5__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U310":{ + "mul_d6__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U312":{ + "mul_d7__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U298.out","add_all__U314.in0"], - ["mul_d1__U300.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U302.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U304.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U306.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["mul_d5__U308.out","add_all__U318.in1"], - ["add_all__U319.in0","add_all__U318.out"], - ["mul_d6__U310.out","add_all__U319.in1"], - ["add_all__U320.in0","add_all__U319.out"], - ["mul_d7__U312.out","add_all__U320.in1"], - ["add_all__U321.in0","add_all__U320.out"], - ["const_term_U313.out","add_all__U321.in1"], - ["self.out","add_all__U321.out"], - ["mul_d0__U298.in0","coeff_0_U297.out"], - ["mul_d1__U300.in0","coeff_1_U299.out"], - ["mul_d2__U302.in0","coeff_2_U301.out"], - ["mul_d3__U304.in0","coeff_3_U303.out"], - ["mul_d4__U306.in0","coeff_4_U305.out"], - ["mul_d5__U308.in0","coeff_5_U307.out"], - ["mul_d6__U310.in0","coeff_6_U309.out"], - ["mul_d7__U312.in0","coeff_7_U311.out"], - ["self.d.0","mul_d0__U298.in1"], - ["self.d.1","mul_d1__U300.in1"], - ["self.d.2","mul_d2__U302.in1"], - ["self.d.3","mul_d3__U304.in1"], - ["self.d.4","mul_d4__U306.in1"], - ["self.d.5","mul_d5__U308.in1"], - ["self.d.6","mul_d6__U310.in1"], - ["self.d.7","mul_d7__U312.in1"] + ["mul_d0__U224.out","add_all__U240.in0"], + ["mul_d1__U226.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U228.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U230.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U232.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["mul_d5__U234.out","add_all__U244.in1"], + ["add_all__U245.in0","add_all__U244.out"], + ["mul_d6__U236.out","add_all__U245.in1"], + ["add_all__U246.in0","add_all__U245.out"], + ["mul_d7__U238.out","add_all__U246.in1"], + ["add_all__U247.in0","add_all__U246.out"], + ["const_term_U239.out","add_all__U247.in1"], + ["self.out","add_all__U247.out"], + ["mul_d0__U224.in0","coeff_0_U223.out"], + ["mul_d1__U226.in0","coeff_1_U225.out"], + ["mul_d2__U228.in0","coeff_2_U227.out"], + ["mul_d3__U230.in0","coeff_3_U229.out"], + ["mul_d4__U232.in0","coeff_4_U231.out"], + ["mul_d5__U234.in0","coeff_5_U233.out"], + ["mul_d6__U236.in0","coeff_6_U235.out"], + ["mul_d7__U238.in0","coeff_7_U237.out"], + ["self.d.0","mul_d0__U224.in1"], + ["self.d.1","mul_d1__U226.in1"], + ["self.d.2","mul_d2__U228.in1"], + ["self.d.3","mul_d3__U230.in1"], + ["self.d.4","mul_d4__U232.in1"], + ["self.d.5","mul_d5__U234.in1"], + ["self.d.6","mul_d6__U236.in1"], + ["self.d.7","mul_d7__U238.in1"] ] }, - "aff__U353":{ + "aff__U279":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U371":{ + "add_all__U297":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U372":{ + "add_all__U298":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U373":{ + "add_all__U299":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U374":{ + "add_all__U300":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U375":{ + "add_all__U301":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U376":{ + "add_all__U302":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U377":{ + "add_all__U303":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U378":{ + "add_all__U304":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U354":{ + "coeff_0_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U356":{ + "coeff_1_U282":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U358":{ + "coeff_2_U284":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_3_U360":{ + "coeff_3_U286":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U362":{ + "coeff_4_U288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U364":{ + "coeff_5_U290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U366":{ + "coeff_6_U292":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U368":{ + "coeff_7_U294":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U370":{ + "const_term_U296":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U355":{ + "mul_d0__U281":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U357":{ + "mul_d1__U283":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U359":{ + "mul_d2__U285":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U361":{ + "mul_d3__U287":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U363":{ + "mul_d4__U289":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U365":{ + "mul_d5__U291":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U367":{ + "mul_d6__U293":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U369":{ + "mul_d7__U295":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U355.out","add_all__U371.in0"], - ["mul_d1__U357.out","add_all__U371.in1"], - ["add_all__U372.in0","add_all__U371.out"], - ["mul_d2__U359.out","add_all__U372.in1"], - ["add_all__U373.in0","add_all__U372.out"], - ["mul_d3__U361.out","add_all__U373.in1"], - ["add_all__U374.in0","add_all__U373.out"], - ["mul_d4__U363.out","add_all__U374.in1"], - ["add_all__U375.in0","add_all__U374.out"], - ["mul_d5__U365.out","add_all__U375.in1"], - ["add_all__U376.in0","add_all__U375.out"], - ["mul_d6__U367.out","add_all__U376.in1"], - ["add_all__U377.in0","add_all__U376.out"], - ["mul_d7__U369.out","add_all__U377.in1"], - ["add_all__U378.in0","add_all__U377.out"], - ["const_term_U370.out","add_all__U378.in1"], - ["self.out","add_all__U378.out"], - ["mul_d0__U355.in0","coeff_0_U354.out"], - ["mul_d1__U357.in0","coeff_1_U356.out"], - ["mul_d2__U359.in0","coeff_2_U358.out"], - ["mul_d3__U361.in0","coeff_3_U360.out"], - ["mul_d4__U363.in0","coeff_4_U362.out"], - ["mul_d5__U365.in0","coeff_5_U364.out"], - ["mul_d6__U367.in0","coeff_6_U366.out"], - ["mul_d7__U369.in0","coeff_7_U368.out"], - ["self.d.0","mul_d0__U355.in1"], - ["self.d.1","mul_d1__U357.in1"], - ["self.d.2","mul_d2__U359.in1"], - ["self.d.3","mul_d3__U361.in1"], - ["self.d.4","mul_d4__U363.in1"], - ["self.d.5","mul_d5__U365.in1"], - ["self.d.6","mul_d6__U367.in1"], - ["self.d.7","mul_d7__U369.in1"] + ["mul_d0__U281.out","add_all__U297.in0"], + ["mul_d1__U283.out","add_all__U297.in1"], + ["add_all__U298.in0","add_all__U297.out"], + ["mul_d2__U285.out","add_all__U298.in1"], + ["add_all__U299.in0","add_all__U298.out"], + ["mul_d3__U287.out","add_all__U299.in1"], + ["add_all__U300.in0","add_all__U299.out"], + ["mul_d4__U289.out","add_all__U300.in1"], + ["add_all__U301.in0","add_all__U300.out"], + ["mul_d5__U291.out","add_all__U301.in1"], + ["add_all__U302.in0","add_all__U301.out"], + ["mul_d6__U293.out","add_all__U302.in1"], + ["add_all__U303.in0","add_all__U302.out"], + ["mul_d7__U295.out","add_all__U303.in1"], + ["add_all__U304.in0","add_all__U303.out"], + ["const_term_U296.out","add_all__U304.in1"], + ["self.out","add_all__U304.out"], + ["mul_d0__U281.in0","coeff_0_U280.out"], + ["mul_d1__U283.in0","coeff_1_U282.out"], + ["mul_d2__U285.in0","coeff_2_U284.out"], + ["mul_d3__U287.in0","coeff_3_U286.out"], + ["mul_d4__U289.in0","coeff_4_U288.out"], + ["mul_d5__U291.in0","coeff_5_U290.out"], + ["mul_d6__U293.in0","coeff_6_U292.out"], + ["mul_d7__U295.in0","coeff_7_U294.out"], + ["self.d.0","mul_d0__U281.in1"], + ["self.d.1","mul_d1__U283.in1"], + ["self.d.2","mul_d2__U285.in1"], + ["self.d.3","mul_d3__U287.in1"], + ["self.d.4","mul_d4__U289.in1"], + ["self.d.5","mul_d5__U291.in1"], + ["self.d.6","mul_d6__U293.in1"], + ["self.d.7","mul_d7__U295.in1"] ] }, - "aff__U399":{ + "aff__U316":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U413":{ + "add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U414":{ + "add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U415":{ + "add_all__U332":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U418":{ + "add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U400":{ + "coeff_0_U317":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U402":{ + "coeff_1_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_2_U404":{ + "coeff_2_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "coeff_3_U406":{ + "coeff_3_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_4_U408":{ + "coeff_4_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U410":{ + "coeff_5_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U412":{ + "const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003de0"]} }, - "mul_d0__U401":{ + "mul_d0__U318":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U403":{ + "mul_d1__U320":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U405":{ + "mul_d2__U322":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U407":{ + "mul_d3__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U409":{ + "mul_d4__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U411":{ + "mul_d5__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U401.out","add_all__U413.in0"], - ["mul_d1__U403.out","add_all__U413.in1"], - ["add_all__U414.in0","add_all__U413.out"], - ["mul_d2__U405.out","add_all__U414.in1"], - ["add_all__U415.in0","add_all__U414.out"], - ["mul_d3__U407.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d4__U409.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["mul_d5__U411.out","add_all__U417.in1"], - ["add_all__U418.in0","add_all__U417.out"], - ["const_term_U412.out","add_all__U418.in1"], - ["self.out","add_all__U418.out"], - ["mul_d0__U401.in0","coeff_0_U400.out"], - ["mul_d1__U403.in0","coeff_1_U402.out"], - ["mul_d2__U405.in0","coeff_2_U404.out"], - ["mul_d3__U407.in0","coeff_3_U406.out"], - ["mul_d4__U409.in0","coeff_4_U408.out"], - ["mul_d5__U411.in0","coeff_5_U410.out"], - ["self.d.0","mul_d0__U401.in1"], - ["self.d.1","mul_d1__U403.in1"], - ["self.d.2","mul_d2__U405.in1"], - ["self.d.3","mul_d3__U407.in1"], - ["self.d.4","mul_d4__U409.in1"], - ["self.d.5","mul_d5__U411.in1"] + ["mul_d0__U318.out","add_all__U330.in0"], + ["mul_d1__U320.out","add_all__U330.in1"], + ["add_all__U331.in0","add_all__U330.out"], + ["mul_d2__U322.out","add_all__U331.in1"], + ["add_all__U332.in0","add_all__U331.out"], + ["mul_d3__U324.out","add_all__U332.in1"], + ["add_all__U333.in0","add_all__U332.out"], + ["mul_d4__U326.out","add_all__U333.in1"], + ["add_all__U334.in0","add_all__U333.out"], + ["mul_d5__U328.out","add_all__U334.in1"], + ["add_all__U335.in0","add_all__U334.out"], + ["const_term_U329.out","add_all__U335.in1"], + ["self.out","add_all__U335.out"], + ["mul_d0__U318.in0","coeff_0_U317.out"], + ["mul_d1__U320.in0","coeff_1_U319.out"], + ["mul_d2__U322.in0","coeff_2_U321.out"], + ["mul_d3__U324.in0","coeff_3_U323.out"], + ["mul_d4__U326.in0","coeff_4_U325.out"], + ["mul_d5__U328.in0","coeff_5_U327.out"], + ["self.d.0","mul_d0__U318.in1"], + ["self.d.1","mul_d1__U320.in1"], + ["self.d.2","mul_d2__U322.in1"], + ["self.d.3","mul_d3__U324.in1"], + ["self.d.4","mul_d4__U326.in1"], + ["self.d.5","mul_d5__U328.in1"] ] }, - "aff__U41":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U51":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U52":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U53":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U42":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U44":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U46":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U48":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U50":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U43":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U437":{ + "aff__U354":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U453":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U454":{ + "add_all__U371":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U455":{ + "add_all__U372":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U456":{ + "add_all__U373":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U355":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_2_U442":{ + "coeff_2_U359":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U444":{ + "coeff_3_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_4_U446":{ + "coeff_4_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_5_U448":{ + "coeff_5_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U450":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U439":{ + "mul_d0__U356":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U358":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U443":{ + "mul_d2__U360":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U445":{ + "mul_d3__U362":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U447":{ + "mul_d4__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U449":{ + "mul_d5__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U451.in0"], - ["mul_d1__U441.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["mul_d2__U443.out","add_all__U452.in1"], - ["add_all__U453.in0","add_all__U452.out"], - ["mul_d3__U445.out","add_all__U453.in1"], - ["add_all__U454.in0","add_all__U453.out"], - ["mul_d4__U447.out","add_all__U454.in1"], - ["add_all__U455.in0","add_all__U454.out"], - ["mul_d5__U449.out","add_all__U455.in1"], - ["add_all__U456.in0","add_all__U455.out"], - ["const_term_U450.out","add_all__U456.in1"], - ["self.out","add_all__U456.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["mul_d2__U443.in0","coeff_2_U442.out"], - ["mul_d3__U445.in0","coeff_3_U444.out"], - ["mul_d4__U447.in0","coeff_4_U446.out"], - ["mul_d5__U449.in0","coeff_5_U448.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"], - ["self.d.2","mul_d2__U443.in1"], - ["self.d.3","mul_d3__U445.in1"], - ["self.d.4","mul_d4__U447.in1"], - ["self.d.5","mul_d5__U449.in1"] + ["mul_d0__U356.out","add_all__U368.in0"], + ["mul_d1__U358.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["mul_d2__U360.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["mul_d3__U362.out","add_all__U370.in1"], + ["add_all__U371.in0","add_all__U370.out"], + ["mul_d4__U364.out","add_all__U371.in1"], + ["add_all__U372.in0","add_all__U371.out"], + ["mul_d5__U366.out","add_all__U372.in1"], + ["add_all__U373.in0","add_all__U372.out"], + ["const_term_U367.out","add_all__U373.in1"], + ["self.out","add_all__U373.out"], + ["mul_d0__U356.in0","coeff_0_U355.out"], + ["mul_d1__U358.in0","coeff_1_U357.out"], + ["mul_d2__U360.in0","coeff_2_U359.out"], + ["mul_d3__U362.in0","coeff_3_U361.out"], + ["mul_d4__U364.in0","coeff_4_U363.out"], + ["mul_d5__U366.in0","coeff_5_U365.out"], + ["self.d.0","mul_d0__U356.in1"], + ["self.d.1","mul_d1__U358.in1"], + ["self.d.2","mul_d2__U360.in1"], + ["self.d.3","mul_d3__U362.in1"], + ["self.d.4","mul_d4__U364.in1"], + ["self.d.5","mul_d5__U366.in1"] ] }, - "aff__U459":{ + "aff__U376":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U469":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U470":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U471":{ + "add_all__U388":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U472":{ + "add_all__U389":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U460":{ + "coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U462":{ + "coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_2_U464":{ + "coeff_2_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U466":{ + "coeff_3_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U468":{ + "const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000055ff"]} }, - "mul_d0__U461":{ + "mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U463":{ + "mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U465":{ + "mul_d2__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U467":{ + "mul_d3__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U461.out","add_all__U469.in0"], - ["mul_d1__U463.out","add_all__U469.in1"], - ["add_all__U470.in0","add_all__U469.out"], - ["mul_d2__U465.out","add_all__U470.in1"], - ["add_all__U471.in0","add_all__U470.out"], - ["mul_d3__U467.out","add_all__U471.in1"], - ["add_all__U472.in0","add_all__U471.out"], - ["const_term_U468.out","add_all__U472.in1"], - ["self.out","add_all__U472.out"], - ["mul_d0__U461.in0","coeff_0_U460.out"], - ["mul_d1__U463.in0","coeff_1_U462.out"], - ["mul_d2__U465.in0","coeff_2_U464.out"], - ["mul_d3__U467.in0","coeff_3_U466.out"], - ["self.d.0","mul_d0__U461.in1"], - ["self.d.1","mul_d1__U463.in1"], - ["self.d.2","mul_d2__U465.in1"], - ["self.d.3","mul_d3__U467.in1"] + ["mul_d0__U378.out","add_all__U386.in0"], + ["mul_d1__U380.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["mul_d2__U382.out","add_all__U387.in1"], + ["add_all__U388.in0","add_all__U387.out"], + ["mul_d3__U384.out","add_all__U388.in1"], + ["add_all__U389.in0","add_all__U388.out"], + ["const_term_U385.out","add_all__U389.in1"], + ["self.out","add_all__U389.out"], + ["mul_d0__U378.in0","coeff_0_U377.out"], + ["mul_d1__U380.in0","coeff_1_U379.out"], + ["mul_d2__U382.in0","coeff_2_U381.out"], + ["mul_d3__U384.in0","coeff_3_U383.out"], + ["self.d.0","mul_d0__U378.in1"], + ["self.d.1","mul_d1__U380.in1"], + ["self.d.2","mul_d2__U382.in1"], + ["self.d.3","mul_d3__U384.in1"] ] }, - "aff__U482":{ + "aff__U399":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U492":{ + "add_all__U409":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U493":{ + "add_all__U410":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U494":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U495":{ + "add_all__U412":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U400":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U402":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U487":{ + "coeff_2_U404":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_3_U489":{ + "coeff_3_U406":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U491":{ + "const_term_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U484":{ + "mul_d0__U401":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U403":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U488":{ + "mul_d2__U405":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U490":{ + "mul_d3__U407":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U492.in0"], - ["mul_d1__U486.out","add_all__U492.in1"], - ["add_all__U493.in0","add_all__U492.out"], - ["mul_d2__U488.out","add_all__U493.in1"], - ["add_all__U494.in0","add_all__U493.out"], - ["mul_d3__U490.out","add_all__U494.in1"], - ["add_all__U495.in0","add_all__U494.out"], - ["const_term_U491.out","add_all__U495.in1"], - ["self.out","add_all__U495.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["mul_d2__U488.in0","coeff_2_U487.out"], - ["mul_d3__U490.in0","coeff_3_U489.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"], - ["self.d.2","mul_d2__U488.in1"], - ["self.d.3","mul_d3__U490.in1"] + ["mul_d0__U401.out","add_all__U409.in0"], + ["mul_d1__U403.out","add_all__U409.in1"], + ["add_all__U410.in0","add_all__U409.out"], + ["mul_d2__U405.out","add_all__U410.in1"], + ["add_all__U411.in0","add_all__U410.out"], + ["mul_d3__U407.out","add_all__U411.in1"], + ["add_all__U412.in0","add_all__U411.out"], + ["const_term_U408.out","add_all__U412.in1"], + ["self.out","add_all__U412.out"], + ["mul_d0__U401.in0","coeff_0_U400.out"], + ["mul_d1__U403.in0","coeff_1_U402.out"], + ["mul_d2__U405.in0","coeff_2_U404.out"], + ["mul_d3__U407.in0","coeff_3_U406.out"], + ["self.d.0","mul_d0__U401.in1"], + ["self.d.1","mul_d1__U403.in1"], + ["self.d.2","mul_d2__U405.in1"], + ["self.d.3","mul_d3__U407.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U71":{ + "add_all__U62":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U72":{ + "add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U73":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U74":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U70":{ + "const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U71.in0"], - ["mul_d1__U61.out","add_all__U71.in1"], - ["add_all__U72.in0","add_all__U71.out"], - ["mul_d2__U63.out","add_all__U72.in1"], - ["add_all__U73.in0","add_all__U72.out"], - ["mul_d3__U65.out","add_all__U73.in1"], - ["add_all__U74.in0","add_all__U73.out"], - ["mul_d4__U67.out","add_all__U74.in1"], - ["add_all__U75.in0","add_all__U74.out"], - ["mul_d5__U69.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["const_term_U70.out","add_all__U76.in1"], - ["self.out","add_all__U76.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"] + ["mul_d0__U50.out","add_all__U62.in0"], + ["mul_d1__U52.out","add_all__U62.in1"], + ["add_all__U63.in0","add_all__U62.out"], + ["mul_d2__U54.out","add_all__U63.in1"], + ["add_all__U64.in0","add_all__U63.out"], + ["mul_d3__U56.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["mul_d4__U58.out","add_all__U65.in1"], + ["add_all__U66.in0","add_all__U65.out"], + ["mul_d5__U60.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["const_term_U61.out","add_all__U67.in1"], + ["self.out","add_all__U67.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U109":{ + "add_all__U100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U110":{ + "add_all__U101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000800"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U108":{ + "const_term_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U101":{ + "mul_d2__U92":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d3__U94":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d5__U98":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U109.in0"], - ["mul_d1__U99.out","add_all__U109.in1"], - ["add_all__U110.in0","add_all__U109.out"], - ["mul_d2__U101.out","add_all__U110.in1"], - ["add_all__U111.in0","add_all__U110.out"], - ["mul_d3__U103.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d4__U105.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d5__U107.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U108.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"] + ["mul_d0__U88.out","add_all__U100.in0"], + ["mul_d1__U90.out","add_all__U100.in1"], + ["add_all__U101.in0","add_all__U100.out"], + ["mul_d2__U92.out","add_all__U101.in1"], + ["add_all__U102.in0","add_all__U101.out"], + ["mul_d3__U94.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d4__U96.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d5__U98.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["const_term_U99.out","add_all__U105.in1"], + ["self.out","add_all__U105.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"] ] }, - "affine_controller__U17":{ + "aff__U9":{ "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], - ["rst_n","BitIn"] + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "_U32":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U33":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U18" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U34":{ - "modref":"corebit.and" - }, - "d_0_am__U35":{ - "modref":"corebit.and" - }, - "d_0_am__U36":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ + "add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U37":{ - "modref":"corebit.and" - }, - "d_1_am__U38":{ - "modref":"corebit.and" - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ + "add_all__U20":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U39":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ + "add_all__U21":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U32.out"], - ["d_2_inc.in1","_U32.out"], - ["d_3_inc.in1","_U32.out"], - ["cmp_time.in1","_U33.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U34.in0"], - ["d_1_at_max.out","d_0_am__U34.in1"], - ["d_0_am__U35.in0","d_0_am__U34.out"], - ["d_2_at_max.out","d_0_am__U35.in1"], - ["d_0_am__U36.in0","d_0_am__U35.out"], - ["d_3_at_max.out","d_0_am__U36.in1"], - ["d_0_next_value.sel","d_0_am__U36.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U37.in0"], - ["d_2_at_max.out","d_1_am__U37.in1"], - ["d_1_am__U38.in0","d_1_am__U37.out"], - ["d_3_at_max.out","d_1_am__U38.in1"], - ["d_1_next_value.sel","d_1_am__U38.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U39.in0"], - ["d_3_at_max.out","d_2_am__U39.in1"], - ["d_2_next_value.sel","d_2_am__U39.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U13":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U15":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U17":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U246":{ + "affine_controller__U172":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1590,18 +1324,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U264":{ + "_U190":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U265":{ + "_U191":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U247" + "modref":"global.aff__U173" }, "cmp_time":{ "genref":"coreir.eq", @@ -1611,16 +1345,16 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U266":{ + "d_0_am__U192":{ "modref":"corebit.and" }, - "d_0_am__U267":{ + "d_0_am__U193":{ "modref":"corebit.and" }, - "d_0_am__U268":{ + "d_0_am__U194":{ "modref":"corebit.and" }, - "d_0_am__U269":{ + "d_0_am__U195":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1654,13 +1388,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U270":{ + "d_1_am__U196":{ "modref":"corebit.and" }, - "d_1_am__U271":{ + "d_1_am__U197":{ "modref":"corebit.and" }, - "d_1_am__U272":{ + "d_1_am__U198":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1694,10 +1428,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U273":{ + "d_2_am__U199":{ "modref":"corebit.and" }, - "d_2_am__U274":{ + "d_2_am__U200":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -1731,7 +1465,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U275":{ + "d_3_am__U201":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -1806,12 +1540,12 @@ } }, "connections":[ - ["d_0_inc.in1","_U264.out"], - ["d_1_inc.in1","_U264.out"], - ["d_2_inc.in1","_U264.out"], - ["d_3_inc.in1","_U264.out"], - ["d_4_inc.in1","_U264.out"], - ["cmp_time.in1","_U265.out"], + ["d_0_inc.in1","_U190.out"], + ["d_1_inc.in1","_U190.out"], + ["d_2_inc.in1","_U190.out"], + ["d_3_inc.in1","_U190.out"], + ["d_4_inc.in1","_U190.out"], + ["cmp_time.in1","_U191.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -1828,15 +1562,15 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U266.in0"], - ["d_1_at_max.out","d_0_am__U266.in1"], - ["d_0_am__U267.in0","d_0_am__U266.out"], - ["d_2_at_max.out","d_0_am__U267.in1"], - ["d_0_am__U268.in0","d_0_am__U267.out"], - ["d_3_at_max.out","d_0_am__U268.in1"], - ["d_0_am__U269.in0","d_0_am__U268.out"], - ["d_4_at_max.out","d_0_am__U269.in1"], - ["d_0_next_value.sel","d_0_am__U269.out"], + ["true.out","d_0_am__U192.in0"], + ["d_1_at_max.out","d_0_am__U192.in1"], + ["d_0_am__U193.in0","d_0_am__U192.out"], + ["d_2_at_max.out","d_0_am__U193.in1"], + ["d_0_am__U194.in0","d_0_am__U193.out"], + ["d_3_at_max.out","d_0_am__U194.in1"], + ["d_0_am__U195.in0","d_0_am__U194.out"], + ["d_4_at_max.out","d_0_am__U195.in1"], + ["d_0_next_value.sel","d_0_am__U195.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1849,13 +1583,13 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U270.in0"], - ["d_2_at_max.out","d_1_am__U270.in1"], - ["d_1_am__U271.in0","d_1_am__U270.out"], - ["d_3_at_max.out","d_1_am__U271.in1"], - ["d_1_am__U272.in0","d_1_am__U271.out"], - ["d_4_at_max.out","d_1_am__U272.in1"], - ["d_1_next_value.sel","d_1_am__U272.out"], + ["true.out","d_1_am__U196.in0"], + ["d_2_at_max.out","d_1_am__U196.in1"], + ["d_1_am__U197.in0","d_1_am__U196.out"], + ["d_3_at_max.out","d_1_am__U197.in1"], + ["d_1_am__U198.in0","d_1_am__U197.out"], + ["d_4_at_max.out","d_1_am__U198.in1"], + ["d_1_next_value.sel","d_1_am__U198.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1868,11 +1602,11 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U273.in0"], - ["d_3_at_max.out","d_2_am__U273.in1"], - ["d_2_am__U274.in0","d_2_am__U273.out"], - ["d_4_at_max.out","d_2_am__U274.in1"], - ["d_2_next_value.sel","d_2_am__U274.out"], + ["true.out","d_2_am__U199.in0"], + ["d_3_at_max.out","d_2_am__U199.in1"], + ["d_2_am__U200.in0","d_2_am__U199.out"], + ["d_4_at_max.out","d_2_am__U200.in1"], + ["d_2_next_value.sel","d_2_am__U200.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -1885,9 +1619,9 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U275.in0"], - ["d_4_at_max.out","d_3_am__U275.in1"], - ["d_3_next_value.sel","d_3_am__U275.out"], + ["true.out","d_3_am__U201.in0"], + ["d_4_at_max.out","d_3_am__U201.in1"], + ["d_3_next_value.sel","d_3_am__U201.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -1915,7 +1649,7 @@ ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U295":{ + "affine_controller__U221":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -1923,18 +1657,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U322":{ + "_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U296" + "modref":"global.aff__U222" }, "cmp_time":{ "genref":"coreir.eq", @@ -1944,25 +1678,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U324":{ + "d_0_am__U250":{ "modref":"corebit.and" }, - "d_0_am__U325":{ + "d_0_am__U251":{ "modref":"corebit.and" }, - "d_0_am__U326":{ + "d_0_am__U252":{ "modref":"corebit.and" }, - "d_0_am__U327":{ + "d_0_am__U253":{ "modref":"corebit.and" }, - "d_0_am__U328":{ + "d_0_am__U254":{ "modref":"corebit.and" }, - "d_0_am__U329":{ + "d_0_am__U255":{ "modref":"corebit.and" }, - "d_0_am__U330":{ + "d_0_am__U256":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1996,22 +1730,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U331":{ + "d_1_am__U257":{ "modref":"corebit.and" }, - "d_1_am__U332":{ + "d_1_am__U258":{ "modref":"corebit.and" }, - "d_1_am__U333":{ + "d_1_am__U259":{ "modref":"corebit.and" }, - "d_1_am__U334":{ + "d_1_am__U260":{ "modref":"corebit.and" }, - "d_1_am__U335":{ + "d_1_am__U261":{ "modref":"corebit.and" }, - "d_1_am__U336":{ + "d_1_am__U262":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2045,19 +1779,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U337":{ + "d_2_am__U263":{ "modref":"corebit.and" }, - "d_2_am__U338":{ + "d_2_am__U264":{ "modref":"corebit.and" }, - "d_2_am__U339":{ + "d_2_am__U265":{ "modref":"corebit.and" }, - "d_2_am__U340":{ + "d_2_am__U266":{ "modref":"corebit.and" }, - "d_2_am__U341":{ + "d_2_am__U267":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2091,16 +1825,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U342":{ + "d_3_am__U268":{ "modref":"corebit.and" }, - "d_3_am__U343":{ + "d_3_am__U269":{ "modref":"corebit.and" }, - "d_3_am__U344":{ + "d_3_am__U270":{ "modref":"corebit.and" }, - "d_3_am__U345":{ + "d_3_am__U271":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2134,13 +1868,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U346":{ + "d_4_am__U272":{ "modref":"corebit.and" }, - "d_4_am__U347":{ + "d_4_am__U273":{ "modref":"corebit.and" }, - "d_4_am__U348":{ + "d_4_am__U274":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2174,10 +1908,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U349":{ + "d_5_am__U275":{ "modref":"corebit.and" }, - "d_5_am__U350":{ + "d_5_am__U276":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -2211,7 +1945,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U351":{ + "d_6_am__U277":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -2286,15 +2020,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U322.out"], - ["d_1_inc.in1","_U322.out"], - ["d_2_inc.in1","_U322.out"], - ["d_3_inc.in1","_U322.out"], - ["d_4_inc.in1","_U322.out"], - ["d_5_inc.in1","_U322.out"], - ["d_6_inc.in1","_U322.out"], - ["d_7_inc.in1","_U322.out"], - ["cmp_time.in1","_U323.out"], + ["d_0_inc.in1","_U248.out"], + ["d_1_inc.in1","_U248.out"], + ["d_2_inc.in1","_U248.out"], + ["d_3_inc.in1","_U248.out"], + ["d_4_inc.in1","_U248.out"], + ["d_5_inc.in1","_U248.out"], + ["d_6_inc.in1","_U248.out"], + ["d_7_inc.in1","_U248.out"], + ["cmp_time.in1","_U249.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2317,21 +2051,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U324.in0"], - ["d_1_at_max.out","d_0_am__U324.in1"], - ["d_0_am__U325.in0","d_0_am__U324.out"], - ["d_2_at_max.out","d_0_am__U325.in1"], - ["d_0_am__U326.in0","d_0_am__U325.out"], - ["d_3_at_max.out","d_0_am__U326.in1"], - ["d_0_am__U327.in0","d_0_am__U326.out"], - ["d_4_at_max.out","d_0_am__U327.in1"], - ["d_0_am__U328.in0","d_0_am__U327.out"], - ["d_5_at_max.out","d_0_am__U328.in1"], - ["d_0_am__U329.in0","d_0_am__U328.out"], - ["d_6_at_max.out","d_0_am__U329.in1"], - ["d_0_am__U330.in0","d_0_am__U329.out"], - ["d_7_at_max.out","d_0_am__U330.in1"], - ["d_0_next_value.sel","d_0_am__U330.out"], + ["true.out","d_0_am__U250.in0"], + ["d_1_at_max.out","d_0_am__U250.in1"], + ["d_0_am__U251.in0","d_0_am__U250.out"], + ["d_2_at_max.out","d_0_am__U251.in1"], + ["d_0_am__U252.in0","d_0_am__U251.out"], + ["d_3_at_max.out","d_0_am__U252.in1"], + ["d_0_am__U253.in0","d_0_am__U252.out"], + ["d_4_at_max.out","d_0_am__U253.in1"], + ["d_0_am__U254.in0","d_0_am__U253.out"], + ["d_5_at_max.out","d_0_am__U254.in1"], + ["d_0_am__U255.in0","d_0_am__U254.out"], + ["d_6_at_max.out","d_0_am__U255.in1"], + ["d_0_am__U256.in0","d_0_am__U255.out"], + ["d_7_at_max.out","d_0_am__U256.in1"], + ["d_0_next_value.sel","d_0_am__U256.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2344,19 +2078,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U331.in0"], - ["d_2_at_max.out","d_1_am__U331.in1"], - ["d_1_am__U332.in0","d_1_am__U331.out"], - ["d_3_at_max.out","d_1_am__U332.in1"], - ["d_1_am__U333.in0","d_1_am__U332.out"], - ["d_4_at_max.out","d_1_am__U333.in1"], - ["d_1_am__U334.in0","d_1_am__U333.out"], - ["d_5_at_max.out","d_1_am__U334.in1"], - ["d_1_am__U335.in0","d_1_am__U334.out"], - ["d_6_at_max.out","d_1_am__U335.in1"], - ["d_1_am__U336.in0","d_1_am__U335.out"], - ["d_7_at_max.out","d_1_am__U336.in1"], - ["d_1_next_value.sel","d_1_am__U336.out"], + ["true.out","d_1_am__U257.in0"], + ["d_2_at_max.out","d_1_am__U257.in1"], + ["d_1_am__U258.in0","d_1_am__U257.out"], + ["d_3_at_max.out","d_1_am__U258.in1"], + ["d_1_am__U259.in0","d_1_am__U258.out"], + ["d_4_at_max.out","d_1_am__U259.in1"], + ["d_1_am__U260.in0","d_1_am__U259.out"], + ["d_5_at_max.out","d_1_am__U260.in1"], + ["d_1_am__U261.in0","d_1_am__U260.out"], + ["d_6_at_max.out","d_1_am__U261.in1"], + ["d_1_am__U262.in0","d_1_am__U261.out"], + ["d_7_at_max.out","d_1_am__U262.in1"], + ["d_1_next_value.sel","d_1_am__U262.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2369,17 +2103,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U337.in0"], - ["d_3_at_max.out","d_2_am__U337.in1"], - ["d_2_am__U338.in0","d_2_am__U337.out"], - ["d_4_at_max.out","d_2_am__U338.in1"], - ["d_2_am__U339.in0","d_2_am__U338.out"], - ["d_5_at_max.out","d_2_am__U339.in1"], - ["d_2_am__U340.in0","d_2_am__U339.out"], - ["d_6_at_max.out","d_2_am__U340.in1"], - ["d_2_am__U341.in0","d_2_am__U340.out"], - ["d_7_at_max.out","d_2_am__U341.in1"], - ["d_2_next_value.sel","d_2_am__U341.out"], + ["true.out","d_2_am__U263.in0"], + ["d_3_at_max.out","d_2_am__U263.in1"], + ["d_2_am__U264.in0","d_2_am__U263.out"], + ["d_4_at_max.out","d_2_am__U264.in1"], + ["d_2_am__U265.in0","d_2_am__U264.out"], + ["d_5_at_max.out","d_2_am__U265.in1"], + ["d_2_am__U266.in0","d_2_am__U265.out"], + ["d_6_at_max.out","d_2_am__U266.in1"], + ["d_2_am__U267.in0","d_2_am__U266.out"], + ["d_7_at_max.out","d_2_am__U267.in1"], + ["d_2_next_value.sel","d_2_am__U267.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2392,15 +2126,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U342.in0"], - ["d_4_at_max.out","d_3_am__U342.in1"], - ["d_3_am__U343.in0","d_3_am__U342.out"], - ["d_5_at_max.out","d_3_am__U343.in1"], - ["d_3_am__U344.in0","d_3_am__U343.out"], - ["d_6_at_max.out","d_3_am__U344.in1"], - ["d_3_am__U345.in0","d_3_am__U344.out"], - ["d_7_at_max.out","d_3_am__U345.in1"], - ["d_3_next_value.sel","d_3_am__U345.out"], + ["true.out","d_3_am__U268.in0"], + ["d_4_at_max.out","d_3_am__U268.in1"], + ["d_3_am__U269.in0","d_3_am__U268.out"], + ["d_5_at_max.out","d_3_am__U269.in1"], + ["d_3_am__U270.in0","d_3_am__U269.out"], + ["d_6_at_max.out","d_3_am__U270.in1"], + ["d_3_am__U271.in0","d_3_am__U270.out"], + ["d_7_at_max.out","d_3_am__U271.in1"], + ["d_3_next_value.sel","d_3_am__U271.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2413,13 +2147,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U346.in0"], - ["d_5_at_max.out","d_4_am__U346.in1"], - ["d_4_am__U347.in0","d_4_am__U346.out"], - ["d_6_at_max.out","d_4_am__U347.in1"], - ["d_4_am__U348.in0","d_4_am__U347.out"], - ["d_7_at_max.out","d_4_am__U348.in1"], - ["d_4_next_value.sel","d_4_am__U348.out"], + ["true.out","d_4_am__U272.in0"], + ["d_5_at_max.out","d_4_am__U272.in1"], + ["d_4_am__U273.in0","d_4_am__U272.out"], + ["d_6_at_max.out","d_4_am__U273.in1"], + ["d_4_am__U274.in0","d_4_am__U273.out"], + ["d_7_at_max.out","d_4_am__U274.in1"], + ["d_4_next_value.sel","d_4_am__U274.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2432,11 +2166,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U349.in0"], - ["d_6_at_max.out","d_5_am__U349.in1"], - ["d_5_am__U350.in0","d_5_am__U349.out"], - ["d_7_at_max.out","d_5_am__U350.in1"], - ["d_5_next_value.sel","d_5_am__U350.out"], + ["true.out","d_5_am__U275.in0"], + ["d_6_at_max.out","d_5_am__U275.in1"], + ["d_5_am__U276.in0","d_5_am__U275.out"], + ["d_7_at_max.out","d_5_am__U276.in1"], + ["d_5_next_value.sel","d_5_am__U276.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -2449,9 +2183,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U351.in0"], - ["d_7_at_max.out","d_6_am__U351.in1"], - ["d_6_next_value.sel","d_6_am__U351.out"], + ["true.out","d_6_am__U277.in0"], + ["d_7_at_max.out","d_6_am__U277.in1"], + ["d_6_next_value.sel","d_6_am__U277.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -2479,7 +2213,7 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U398":{ + "affine_controller__U315":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2487,18 +2221,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U419":{ + "_U336":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U420":{ + "_U337":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U399" + "modref":"global.aff__U316" }, "cmp_time":{ "genref":"coreir.eq", @@ -2508,19 +2242,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U421":{ + "d_0_am__U338":{ "modref":"corebit.and" }, - "d_0_am__U422":{ + "d_0_am__U339":{ "modref":"corebit.and" }, - "d_0_am__U423":{ + "d_0_am__U340":{ "modref":"corebit.and" }, - "d_0_am__U424":{ + "d_0_am__U341":{ "modref":"corebit.and" }, - "d_0_am__U425":{ + "d_0_am__U342":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2554,16 +2288,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U426":{ + "d_1_am__U343":{ "modref":"corebit.and" }, - "d_1_am__U427":{ + "d_1_am__U344":{ "modref":"corebit.and" }, - "d_1_am__U428":{ + "d_1_am__U345":{ "modref":"corebit.and" }, - "d_1_am__U429":{ + "d_1_am__U346":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2597,13 +2331,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U430":{ + "d_2_am__U347":{ "modref":"corebit.and" }, - "d_2_am__U431":{ + "d_2_am__U348":{ "modref":"corebit.and" }, - "d_2_am__U432":{ + "d_2_am__U349":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2637,10 +2371,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U433":{ + "d_3_am__U350":{ "modref":"corebit.and" }, - "d_3_am__U434":{ + "d_3_am__U351":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2674,7 +2408,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U435":{ + "d_4_am__U352":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2749,13 +2483,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U419.out"], - ["d_1_inc.in1","_U419.out"], - ["d_2_inc.in1","_U419.out"], - ["d_3_inc.in1","_U419.out"], - ["d_4_inc.in1","_U419.out"], - ["d_5_inc.in1","_U419.out"], - ["cmp_time.in1","_U420.out"], + ["d_0_inc.in1","_U336.out"], + ["d_1_inc.in1","_U336.out"], + ["d_2_inc.in1","_U336.out"], + ["d_3_inc.in1","_U336.out"], + ["d_4_inc.in1","_U336.out"], + ["d_5_inc.in1","_U336.out"], + ["cmp_time.in1","_U337.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2774,17 +2508,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U421.in0"], - ["d_1_at_max.out","d_0_am__U421.in1"], - ["d_0_am__U422.in0","d_0_am__U421.out"], - ["d_2_at_max.out","d_0_am__U422.in1"], - ["d_0_am__U423.in0","d_0_am__U422.out"], - ["d_3_at_max.out","d_0_am__U423.in1"], - ["d_0_am__U424.in0","d_0_am__U423.out"], - ["d_4_at_max.out","d_0_am__U424.in1"], - ["d_0_am__U425.in0","d_0_am__U424.out"], - ["d_5_at_max.out","d_0_am__U425.in1"], - ["d_0_next_value.sel","d_0_am__U425.out"], + ["true.out","d_0_am__U338.in0"], + ["d_1_at_max.out","d_0_am__U338.in1"], + ["d_0_am__U339.in0","d_0_am__U338.out"], + ["d_2_at_max.out","d_0_am__U339.in1"], + ["d_0_am__U340.in0","d_0_am__U339.out"], + ["d_3_at_max.out","d_0_am__U340.in1"], + ["d_0_am__U341.in0","d_0_am__U340.out"], + ["d_4_at_max.out","d_0_am__U341.in1"], + ["d_0_am__U342.in0","d_0_am__U341.out"], + ["d_5_at_max.out","d_0_am__U342.in1"], + ["d_0_next_value.sel","d_0_am__U342.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2797,15 +2531,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U426.in0"], - ["d_2_at_max.out","d_1_am__U426.in1"], - ["d_1_am__U427.in0","d_1_am__U426.out"], - ["d_3_at_max.out","d_1_am__U427.in1"], - ["d_1_am__U428.in0","d_1_am__U427.out"], - ["d_4_at_max.out","d_1_am__U428.in1"], - ["d_1_am__U429.in0","d_1_am__U428.out"], - ["d_5_at_max.out","d_1_am__U429.in1"], - ["d_1_next_value.sel","d_1_am__U429.out"], + ["true.out","d_1_am__U343.in0"], + ["d_2_at_max.out","d_1_am__U343.in1"], + ["d_1_am__U344.in0","d_1_am__U343.out"], + ["d_3_at_max.out","d_1_am__U344.in1"], + ["d_1_am__U345.in0","d_1_am__U344.out"], + ["d_4_at_max.out","d_1_am__U345.in1"], + ["d_1_am__U346.in0","d_1_am__U345.out"], + ["d_5_at_max.out","d_1_am__U346.in1"], + ["d_1_next_value.sel","d_1_am__U346.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2818,13 +2552,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U430.in0"], - ["d_3_at_max.out","d_2_am__U430.in1"], - ["d_2_am__U431.in0","d_2_am__U430.out"], - ["d_4_at_max.out","d_2_am__U431.in1"], - ["d_2_am__U432.in0","d_2_am__U431.out"], - ["d_5_at_max.out","d_2_am__U432.in1"], - ["d_2_next_value.sel","d_2_am__U432.out"], + ["true.out","d_2_am__U347.in0"], + ["d_3_at_max.out","d_2_am__U347.in1"], + ["d_2_am__U348.in0","d_2_am__U347.out"], + ["d_4_at_max.out","d_2_am__U348.in1"], + ["d_2_am__U349.in0","d_2_am__U348.out"], + ["d_5_at_max.out","d_2_am__U349.in1"], + ["d_2_next_value.sel","d_2_am__U349.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2837,11 +2571,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U433.in0"], - ["d_4_at_max.out","d_3_am__U433.in1"], - ["d_3_am__U434.in0","d_3_am__U433.out"], - ["d_5_at_max.out","d_3_am__U434.in1"], - ["d_3_next_value.sel","d_3_am__U434.out"], + ["true.out","d_3_am__U350.in0"], + ["d_4_at_max.out","d_3_am__U350.in1"], + ["d_3_am__U351.in0","d_3_am__U350.out"], + ["d_5_at_max.out","d_3_am__U351.in1"], + ["d_3_next_value.sel","d_3_am__U351.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2854,9 +2588,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U435.in0"], - ["d_5_at_max.out","d_4_am__U435.in1"], - ["d_4_next_value.sel","d_4_am__U435.out"], + ["true.out","d_4_am__U352.in0"], + ["d_5_at_max.out","d_4_am__U352.in1"], + ["d_4_next_value.sel","d_4_am__U352.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2884,7 +2618,7 @@ ["self.d.5","d_5_reg.out"] ] }, - "affine_controller__U458":{ + "affine_controller__U375":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2892,18 +2626,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U473":{ + "_U390":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U474":{ + "_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U459" + "modref":"global.aff__U376" }, "cmp_time":{ "genref":"coreir.eq", @@ -2913,13 +2647,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U475":{ + "d_0_am__U392":{ "modref":"corebit.and" }, - "d_0_am__U476":{ + "d_0_am__U393":{ "modref":"corebit.and" }, - "d_0_am__U477":{ + "d_0_am__U394":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2953,10 +2687,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U478":{ + "d_1_am__U395":{ "modref":"corebit.and" }, - "d_1_am__U479":{ + "d_1_am__U396":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2990,7 +2724,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U480":{ + "d_2_am__U397":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -3065,11 +2799,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U473.out"], - ["d_1_inc.in1","_U473.out"], - ["d_2_inc.in1","_U473.out"], - ["d_3_inc.in1","_U473.out"], - ["cmp_time.in1","_U474.out"], + ["d_0_inc.in1","_U390.out"], + ["d_1_inc.in1","_U390.out"], + ["d_2_inc.in1","_U390.out"], + ["d_3_inc.in1","_U390.out"], + ["cmp_time.in1","_U391.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3084,13 +2818,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U475.in0"], - ["d_1_at_max.out","d_0_am__U475.in1"], - ["d_0_am__U476.in0","d_0_am__U475.out"], - ["d_2_at_max.out","d_0_am__U476.in1"], - ["d_0_am__U477.in0","d_0_am__U476.out"], - ["d_3_at_max.out","d_0_am__U477.in1"], - ["d_0_next_value.sel","d_0_am__U477.out"], + ["true.out","d_0_am__U392.in0"], + ["d_1_at_max.out","d_0_am__U392.in1"], + ["d_0_am__U393.in0","d_0_am__U392.out"], + ["d_2_at_max.out","d_0_am__U393.in1"], + ["d_0_am__U394.in0","d_0_am__U393.out"], + ["d_3_at_max.out","d_0_am__U394.in1"], + ["d_0_next_value.sel","d_0_am__U394.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3103,11 +2837,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U478.in0"], - ["d_2_at_max.out","d_1_am__U478.in1"], - ["d_1_am__U479.in0","d_1_am__U478.out"], - ["d_3_at_max.out","d_1_am__U479.in1"], - ["d_1_next_value.sel","d_1_am__U479.out"], + ["true.out","d_1_am__U395.in0"], + ["d_2_at_max.out","d_1_am__U395.in1"], + ["d_1_am__U396.in0","d_1_am__U395.out"], + ["d_3_at_max.out","d_1_am__U396.in1"], + ["d_1_next_value.sel","d_1_am__U396.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3120,9 +2854,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U480.in0"], - ["d_3_at_max.out","d_2_am__U480.in1"], - ["d_2_next_value.sel","d_2_am__U480.out"], + ["true.out","d_2_am__U397.in0"], + ["d_3_at_max.out","d_2_am__U397.in1"], + ["d_2_next_value.sel","d_2_am__U397.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3150,7 +2884,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3158,18 +2892,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U77":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U78":{ + "_U69":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U57" + "modref":"global.aff__U48" }, "cmp_time":{ "genref":"coreir.eq", @@ -3179,19 +2913,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U79":{ + "d_0_am__U70":{ "modref":"corebit.and" }, - "d_0_am__U80":{ + "d_0_am__U71":{ "modref":"corebit.and" }, - "d_0_am__U81":{ + "d_0_am__U72":{ "modref":"corebit.and" }, - "d_0_am__U82":{ + "d_0_am__U73":{ "modref":"corebit.and" }, - "d_0_am__U83":{ + "d_0_am__U74":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3225,16 +2959,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U84":{ + "d_1_am__U75":{ "modref":"corebit.and" }, - "d_1_am__U85":{ + "d_1_am__U76":{ "modref":"corebit.and" }, - "d_1_am__U86":{ + "d_1_am__U77":{ "modref":"corebit.and" }, - "d_1_am__U87":{ + "d_1_am__U78":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -3268,13 +3002,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U88":{ + "d_2_am__U79":{ "modref":"corebit.and" }, - "d_2_am__U89":{ + "d_2_am__U80":{ "modref":"corebit.and" }, - "d_2_am__U90":{ + "d_2_am__U81":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -3308,10 +3042,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U91":{ + "d_3_am__U82":{ "modref":"corebit.and" }, - "d_3_am__U92":{ + "d_3_am__U83":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -3345,7 +3079,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U93":{ + "d_4_am__U84":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -3420,13 +3154,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U77.out"], - ["d_1_inc.in1","_U77.out"], - ["d_2_inc.in1","_U77.out"], - ["d_3_inc.in1","_U77.out"], - ["d_4_inc.in1","_U77.out"], - ["d_5_inc.in1","_U77.out"], - ["cmp_time.in1","_U78.out"], + ["d_0_inc.in1","_U68.out"], + ["d_1_inc.in1","_U68.out"], + ["d_2_inc.in1","_U68.out"], + ["d_3_inc.in1","_U68.out"], + ["d_4_inc.in1","_U68.out"], + ["d_5_inc.in1","_U68.out"], + ["cmp_time.in1","_U69.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3445,17 +3179,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U79.in0"], - ["d_1_at_max.out","d_0_am__U79.in1"], - ["d_0_am__U80.in0","d_0_am__U79.out"], - ["d_2_at_max.out","d_0_am__U80.in1"], - ["d_0_am__U81.in0","d_0_am__U80.out"], - ["d_3_at_max.out","d_0_am__U81.in1"], - ["d_0_am__U82.in0","d_0_am__U81.out"], - ["d_4_at_max.out","d_0_am__U82.in1"], - ["d_0_am__U83.in0","d_0_am__U82.out"], - ["d_5_at_max.out","d_0_am__U83.in1"], - ["d_0_next_value.sel","d_0_am__U83.out"], + ["true.out","d_0_am__U70.in0"], + ["d_1_at_max.out","d_0_am__U70.in1"], + ["d_0_am__U71.in0","d_0_am__U70.out"], + ["d_2_at_max.out","d_0_am__U71.in1"], + ["d_0_am__U72.in0","d_0_am__U71.out"], + ["d_3_at_max.out","d_0_am__U72.in1"], + ["d_0_am__U73.in0","d_0_am__U72.out"], + ["d_4_at_max.out","d_0_am__U73.in1"], + ["d_0_am__U74.in0","d_0_am__U73.out"], + ["d_5_at_max.out","d_0_am__U74.in1"], + ["d_0_next_value.sel","d_0_am__U74.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3468,15 +3202,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U84.in0"], - ["d_2_at_max.out","d_1_am__U84.in1"], - ["d_1_am__U85.in0","d_1_am__U84.out"], - ["d_3_at_max.out","d_1_am__U85.in1"], - ["d_1_am__U86.in0","d_1_am__U85.out"], - ["d_4_at_max.out","d_1_am__U86.in1"], - ["d_1_am__U87.in0","d_1_am__U86.out"], - ["d_5_at_max.out","d_1_am__U87.in1"], - ["d_1_next_value.sel","d_1_am__U87.out"], + ["true.out","d_1_am__U75.in0"], + ["d_2_at_max.out","d_1_am__U75.in1"], + ["d_1_am__U76.in0","d_1_am__U75.out"], + ["d_3_at_max.out","d_1_am__U76.in1"], + ["d_1_am__U77.in0","d_1_am__U76.out"], + ["d_4_at_max.out","d_1_am__U77.in1"], + ["d_1_am__U78.in0","d_1_am__U77.out"], + ["d_5_at_max.out","d_1_am__U78.in1"], + ["d_1_next_value.sel","d_1_am__U78.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3489,13 +3223,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U88.in0"], - ["d_3_at_max.out","d_2_am__U88.in1"], - ["d_2_am__U89.in0","d_2_am__U88.out"], - ["d_4_at_max.out","d_2_am__U89.in1"], - ["d_2_am__U90.in0","d_2_am__U89.out"], - ["d_5_at_max.out","d_2_am__U90.in1"], - ["d_2_next_value.sel","d_2_am__U90.out"], + ["true.out","d_2_am__U79.in0"], + ["d_3_at_max.out","d_2_am__U79.in1"], + ["d_2_am__U80.in0","d_2_am__U79.out"], + ["d_4_at_max.out","d_2_am__U80.in1"], + ["d_2_am__U81.in0","d_2_am__U80.out"], + ["d_5_at_max.out","d_2_am__U81.in1"], + ["d_2_next_value.sel","d_2_am__U81.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3508,11 +3242,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U91.in0"], - ["d_4_at_max.out","d_3_am__U91.in1"], - ["d_3_am__U92.in0","d_3_am__U91.out"], - ["d_5_at_max.out","d_3_am__U92.in1"], - ["d_3_next_value.sel","d_3_am__U92.out"], + ["true.out","d_3_am__U82.in0"], + ["d_4_at_max.out","d_3_am__U82.in1"], + ["d_3_am__U83.in0","d_3_am__U82.out"], + ["d_5_at_max.out","d_3_am__U83.in1"], + ["d_3_next_value.sel","d_3_am__U83.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3525,9 +3259,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U93.in0"], - ["d_5_at_max.out","d_4_am__U93.in1"], - ["d_4_next_value.sel","d_4_am__U93.out"], + ["true.out","d_4_am__U84.in0"], + ["d_5_at_max.out","d_4_am__U84.in1"], + ["d_4_next_value.sel","d_4_am__U84.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3555,6 +3289,272 @@ ["self.d.5","d_5_reg.out"] ] }, + "affine_controller__U8":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",4,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U9" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U25":{ + "modref":"corebit.and" + }, + "d_0_am__U26":{ + "modref":"corebit.and" + }, + "d_0_am__U27":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U28":{ + "modref":"corebit.and" + }, + "d_1_am__U29":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_am__U30":{ + "modref":"corebit.and" + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U23.out"], + ["d_2_inc.in1","_U23.out"], + ["d_3_inc.in1","_U23.out"], + ["cmp_time.in1","_U24.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U25.in0"], + ["d_1_at_max.out","d_0_am__U25.in1"], + ["d_0_am__U26.in0","d_0_am__U25.out"], + ["d_2_at_max.out","d_0_am__U26.in1"], + ["d_0_am__U27.in0","d_0_am__U26.out"], + ["d_3_at_max.out","d_0_am__U27.in1"], + ["d_0_next_value.sel","d_0_am__U27.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U28.in0"], + ["d_2_at_max.out","d_1_am__U28.in1"], + ["d_1_am__U29.in0","d_1_am__U28.out"], + ["d_3_at_max.out","d_1_am__U29.in1"], + ["d_1_next_value.sel","d_1_am__U29.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U30.in0"], + ["d_3_at_max.out","d_2_am__U30.in1"], + ["d_2_next_value.sel","d_2_am__U30.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] + ] + }, "cu_op_hcompute_hw_output_stencil":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], @@ -5172,42 +5172,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -5215,8 +5183,8 @@ }, "ub_input_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -5224,8 +5192,8 @@ }, "ub_input_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -5233,8 +5201,8 @@ }, "ub_input_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -5242,8 +5210,8 @@ }, "ub_input_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -5251,8 +5219,8 @@ }, "ub_input_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11517],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11517],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -5260,8 +5228,8 @@ }, "ub_input_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -5269,8 +5237,8 @@ }, "ub_input_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9248],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9248],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[11518],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -5278,14 +5246,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_input_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U11.out"], - ["ub_input_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U13.out"], - ["ub_input_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U15.out"], - ["ub_input_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_input_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], - ["ub_input_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U7.out"], - ["ub_input_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U9.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_1.clk","self.clk"], ["ub_input_cgra_stencil_BANK_2.clk","self.clk"], @@ -5403,42 +5363,42 @@ ["op_hcompute_input_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U115":{ - "modref":"global.aff__U95" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U106":{ + "modref":"global.aff__U86" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55":{ - "modref":"global.aff__U41" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46":{ + "modref":"global.aff__U32" }, - "chain_en_const_U116":{ + "chain_en_const_U107":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U40":{ - "modref":"global.affine_controller__U17", + "ctrl__U31":{ + "modref":"global.affine_controller__U8", "metadata":{"garnet_remove":true} }, - "ctrl__U94":{ - "modref":"global.affine_controller__U56", + "ctrl__U85":{ + "modref":"global.affine_controller__U47", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,2304,4608],"dimensionality":4,"extent":[8,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,8,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[4096],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U16"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,2304,4608],"dimensionality":4,"extent":[8,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,8,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[4096],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U94.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U115.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U115.out"], - ["ctrl__U40.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U116.out"], - ["self.clk","ctrl__U40.clk"], - ["self.reset","ctrl__U40.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U40.valid"], - ["self.clk","ctrl__U94.clk"], - ["self.reset","ctrl__U94.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U94.valid"], + ["ctrl__U85.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U106.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U106.out"], + ["ctrl__U31.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U107.out"], + ["self.clk","ctrl__U31.clk"], + ["self.reset","ctrl__U31.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U31.valid"], + ["self.clk","ctrl__U85.clk"], + ["self.reset","ctrl__U85.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U85.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_glb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_input_cgra_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -5470,266 +5430,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U118":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U120":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U122":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U124":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U126":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U128":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U130":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U136":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U138":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U140":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U142":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U144":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U146":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U148":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U150":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U152":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U154":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U156":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U158":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U160":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U164":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U166":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U168":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U170":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U172":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U174":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U176":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U178":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U180":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U182":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U184":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U186":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U188":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U190":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U194":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U196":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U198":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U200":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U202":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U204":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U206":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U208":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U210":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U212":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U214":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U216":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U218":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U220":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U222":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U224":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U226":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U228":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U230":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U232":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U234":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U236":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U238":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U240":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U242":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U244":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9409],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U117"} + "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9409],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -5737,13 +5441,13 @@ }, "ub_kernel_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9417],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U119"} + "genargs":{"ID":["String","_U109"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9417],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9426],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U137"} + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9426],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -5751,8 +5455,8 @@ }, "ub_kernel_cgra_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9434],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U139"} + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9434],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -5760,8 +5464,8 @@ }, "ub_kernel_cgra_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9442],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9249],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U141"} + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9442],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9249],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -5769,8 +5473,8 @@ }, "ub_kernel_cgra_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9450],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9257],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U143"} + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9450],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9257],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -5778,8 +5482,8 @@ }, "ub_kernel_cgra_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9458],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9265],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U145"} + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9458],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9265],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -5787,8 +5491,8 @@ }, "ub_kernel_cgra_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9466],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9273],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U147"} + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9466],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9273],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -5796,8 +5500,8 @@ }, "ub_kernel_cgra_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9411],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U149"} + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9411],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -5805,8 +5509,8 @@ }, "ub_kernel_cgra_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9419],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U151"} + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9419],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -5814,8 +5518,8 @@ }, "ub_kernel_cgra_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9427],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U153"} + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9427],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -5823,8 +5527,8 @@ }, "ub_kernel_cgra_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9435],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U155"} + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9435],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -5836,13 +5540,13 @@ }, "ub_kernel_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9425],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U121"} + "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9425],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9443],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9250],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U157"} + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9443],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9250],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -5850,8 +5554,8 @@ }, "ub_kernel_cgra_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9451],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9258],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U159"} + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9451],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9258],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -5859,8 +5563,8 @@ }, "ub_kernel_cgra_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9459],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9266],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U161"} + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9459],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9266],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -5868,8 +5572,8 @@ }, "ub_kernel_cgra_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9467],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9274],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U163"} + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9467],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9274],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -5877,8 +5581,8 @@ }, "ub_kernel_cgra_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9412],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U165"} + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9412],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -5886,8 +5590,8 @@ }, "ub_kernel_cgra_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9420],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U167"} + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9420],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -5895,8 +5599,8 @@ }, "ub_kernel_cgra_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9428],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U169"} + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9428],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -5904,8 +5608,8 @@ }, "ub_kernel_cgra_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9436],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U171"} + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9436],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -5913,8 +5617,8 @@ }, "ub_kernel_cgra_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9444],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9251],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U173"} + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9444],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9251],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -5922,8 +5626,8 @@ }, "ub_kernel_cgra_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9452],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9259],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U175"} + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9452],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9259],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -5935,13 +5639,13 @@ }, "ub_kernel_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9433],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U123"} + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9433],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9460],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9267],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U177"} + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9460],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9267],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -5949,8 +5653,8 @@ }, "ub_kernel_cgra_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9468],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9275],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U179"} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9468],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9275],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -5958,8 +5662,8 @@ }, "ub_kernel_cgra_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9413],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U181"} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9413],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -5967,8 +5671,8 @@ }, "ub_kernel_cgra_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9421],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U183"} + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9421],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -5976,8 +5680,8 @@ }, "ub_kernel_cgra_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9429],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U185"} + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9429],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -5985,8 +5689,8 @@ }, "ub_kernel_cgra_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9437],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U187"} + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9437],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -5994,8 +5698,8 @@ }, "ub_kernel_cgra_stencil_BANK_36":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9445],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9252],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U189"} + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9445],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9252],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const":{ "modref":"corebit.const", @@ -6003,8 +5707,8 @@ }, "ub_kernel_cgra_stencil_BANK_37":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9453],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9260],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U191"} + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9453],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9260],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const":{ "modref":"corebit.const", @@ -6012,8 +5716,8 @@ }, "ub_kernel_cgra_stencil_BANK_38":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9461],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9268],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U193"} + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9461],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9268],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const":{ "modref":"corebit.const", @@ -6021,8 +5725,8 @@ }, "ub_kernel_cgra_stencil_BANK_39":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9469],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9276],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U195"} + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9469],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9276],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const":{ "modref":"corebit.const", @@ -6034,13 +5738,13 @@ }, "ub_kernel_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9441],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9248],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U125"} + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9441],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9248],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U197"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9414],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U197"} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9414],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const":{ "modref":"corebit.const", @@ -6048,8 +5752,8 @@ }, "ub_kernel_cgra_stencil_BANK_41":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U199"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9422],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U199"} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9422],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const":{ "modref":"corebit.const", @@ -6057,8 +5761,8 @@ }, "ub_kernel_cgra_stencil_BANK_42":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U201"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9430],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U201"} + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9430],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const":{ "modref":"corebit.const", @@ -6066,8 +5770,8 @@ }, "ub_kernel_cgra_stencil_BANK_43":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U203"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9438],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U203"} + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9438],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const":{ "modref":"corebit.const", @@ -6075,8 +5779,8 @@ }, "ub_kernel_cgra_stencil_BANK_44":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U205"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9446],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9253],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U205"} + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9446],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9253],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const":{ "modref":"corebit.const", @@ -6084,8 +5788,8 @@ }, "ub_kernel_cgra_stencil_BANK_45":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U207"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9454],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9261],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U207"} + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9454],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9261],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const":{ "modref":"corebit.const", @@ -6093,8 +5797,8 @@ }, "ub_kernel_cgra_stencil_BANK_46":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9462],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9269],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U209"} + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9462],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9269],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const":{ "modref":"corebit.const", @@ -6102,8 +5806,8 @@ }, "ub_kernel_cgra_stencil_BANK_47":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9470],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9277],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U211"} + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9470],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9277],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const":{ "modref":"corebit.const", @@ -6111,8 +5815,8 @@ }, "ub_kernel_cgra_stencil_BANK_48":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9415],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U213"} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9415],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const":{ "modref":"corebit.const", @@ -6120,8 +5824,8 @@ }, "ub_kernel_cgra_stencil_BANK_49":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9423],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U215"} + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9423],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const":{ "modref":"corebit.const", @@ -6133,13 +5837,13 @@ }, "ub_kernel_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9449],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9256],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U127"} + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9449],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9256],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9431],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U217"} + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9431],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const":{ "modref":"corebit.const", @@ -6147,8 +5851,8 @@ }, "ub_kernel_cgra_stencil_BANK_51":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9439],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U219"} + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9439],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const":{ "modref":"corebit.const", @@ -6156,8 +5860,8 @@ }, "ub_kernel_cgra_stencil_BANK_52":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9447],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9254],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U221"} + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9447],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9254],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const":{ "modref":"corebit.const", @@ -6165,8 +5869,8 @@ }, "ub_kernel_cgra_stencil_BANK_53":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9455],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9262],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U223"} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9455],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9262],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const":{ "modref":"corebit.const", @@ -6174,8 +5878,8 @@ }, "ub_kernel_cgra_stencil_BANK_54":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9463],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9270],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U225"} + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9463],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9270],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const":{ "modref":"corebit.const", @@ -6183,8 +5887,8 @@ }, "ub_kernel_cgra_stencil_BANK_55":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9471],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9278],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U227"} + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9471],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9278],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const":{ "modref":"corebit.const", @@ -6192,8 +5896,8 @@ }, "ub_kernel_cgra_stencil_BANK_56":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9416],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U229"} + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9416],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const":{ "modref":"corebit.const", @@ -6201,8 +5905,8 @@ }, "ub_kernel_cgra_stencil_BANK_57":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9424],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U231"} + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9424],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const":{ "modref":"corebit.const", @@ -6210,8 +5914,8 @@ }, "ub_kernel_cgra_stencil_BANK_58":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9432],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U233"} + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9432],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const":{ "modref":"corebit.const", @@ -6219,8 +5923,8 @@ }, "ub_kernel_cgra_stencil_BANK_59":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9440],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U235"} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9440],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const":{ "modref":"corebit.const", @@ -6232,13 +5936,13 @@ }, "ub_kernel_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9457],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9264],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U129"} + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9457],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9264],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9448],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9255],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U237"} + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9448],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9255],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const":{ "modref":"corebit.const", @@ -6246,8 +5950,8 @@ }, "ub_kernel_cgra_stencil_BANK_61":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9456],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9263],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U239"} + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9456],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9263],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const":{ "modref":"corebit.const", @@ -6255,8 +5959,8 @@ }, "ub_kernel_cgra_stencil_BANK_62":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9464],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9271],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U241"} + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9464],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9271],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const":{ "modref":"corebit.const", @@ -6264,8 +5968,8 @@ }, "ub_kernel_cgra_stencil_BANK_63":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9472],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9279],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U243"} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9472],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9279],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const":{ "modref":"corebit.const", @@ -6277,8 +5981,8 @@ }, "ub_kernel_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9465],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9272],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U131"} + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9465],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9272],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -6286,8 +5990,8 @@ }, "ub_kernel_cgra_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9410],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U133"} + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9410],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -6295,8 +5999,8 @@ }, "ub_kernel_cgra_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9418],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U135"} + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9418],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11521],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -6304,70 +6008,6 @@ } }, "connections":[ - ["ub_kernel_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U118.out"], - ["ub_kernel_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U120.out"], - ["ub_kernel_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U122.out"], - ["ub_kernel_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U124.out"], - ["ub_kernel_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U126.out"], - ["ub_kernel_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U128.out"], - ["ub_kernel_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U130.out"], - ["ub_kernel_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U132.out"], - ["ub_kernel_cgra_stencil_BANK_8.chain_chain_en","chain_en_const_U134.out"], - ["ub_kernel_cgra_stencil_BANK_9.chain_chain_en","chain_en_const_U136.out"], - ["ub_kernel_cgra_stencil_BANK_10.chain_chain_en","chain_en_const_U138.out"], - ["ub_kernel_cgra_stencil_BANK_11.chain_chain_en","chain_en_const_U140.out"], - ["ub_kernel_cgra_stencil_BANK_12.chain_chain_en","chain_en_const_U142.out"], - ["ub_kernel_cgra_stencil_BANK_13.chain_chain_en","chain_en_const_U144.out"], - ["ub_kernel_cgra_stencil_BANK_14.chain_chain_en","chain_en_const_U146.out"], - ["ub_kernel_cgra_stencil_BANK_15.chain_chain_en","chain_en_const_U148.out"], - ["ub_kernel_cgra_stencil_BANK_16.chain_chain_en","chain_en_const_U150.out"], - ["ub_kernel_cgra_stencil_BANK_17.chain_chain_en","chain_en_const_U152.out"], - ["ub_kernel_cgra_stencil_BANK_18.chain_chain_en","chain_en_const_U154.out"], - ["ub_kernel_cgra_stencil_BANK_19.chain_chain_en","chain_en_const_U156.out"], - ["ub_kernel_cgra_stencil_BANK_20.chain_chain_en","chain_en_const_U158.out"], - ["ub_kernel_cgra_stencil_BANK_21.chain_chain_en","chain_en_const_U160.out"], - ["ub_kernel_cgra_stencil_BANK_22.chain_chain_en","chain_en_const_U162.out"], - ["ub_kernel_cgra_stencil_BANK_23.chain_chain_en","chain_en_const_U164.out"], - ["ub_kernel_cgra_stencil_BANK_24.chain_chain_en","chain_en_const_U166.out"], - ["ub_kernel_cgra_stencil_BANK_25.chain_chain_en","chain_en_const_U168.out"], - ["ub_kernel_cgra_stencil_BANK_26.chain_chain_en","chain_en_const_U170.out"], - ["ub_kernel_cgra_stencil_BANK_27.chain_chain_en","chain_en_const_U172.out"], - ["ub_kernel_cgra_stencil_BANK_28.chain_chain_en","chain_en_const_U174.out"], - ["ub_kernel_cgra_stencil_BANK_29.chain_chain_en","chain_en_const_U176.out"], - ["ub_kernel_cgra_stencil_BANK_30.chain_chain_en","chain_en_const_U178.out"], - ["ub_kernel_cgra_stencil_BANK_31.chain_chain_en","chain_en_const_U180.out"], - ["ub_kernel_cgra_stencil_BANK_32.chain_chain_en","chain_en_const_U182.out"], - ["ub_kernel_cgra_stencil_BANK_33.chain_chain_en","chain_en_const_U184.out"], - ["ub_kernel_cgra_stencil_BANK_34.chain_chain_en","chain_en_const_U186.out"], - ["ub_kernel_cgra_stencil_BANK_35.chain_chain_en","chain_en_const_U188.out"], - ["ub_kernel_cgra_stencil_BANK_36.chain_chain_en","chain_en_const_U190.out"], - ["ub_kernel_cgra_stencil_BANK_37.chain_chain_en","chain_en_const_U192.out"], - ["ub_kernel_cgra_stencil_BANK_38.chain_chain_en","chain_en_const_U194.out"], - ["ub_kernel_cgra_stencil_BANK_39.chain_chain_en","chain_en_const_U196.out"], - ["ub_kernel_cgra_stencil_BANK_40.chain_chain_en","chain_en_const_U198.out"], - ["ub_kernel_cgra_stencil_BANK_41.chain_chain_en","chain_en_const_U200.out"], - ["ub_kernel_cgra_stencil_BANK_42.chain_chain_en","chain_en_const_U202.out"], - ["ub_kernel_cgra_stencil_BANK_43.chain_chain_en","chain_en_const_U204.out"], - ["ub_kernel_cgra_stencil_BANK_44.chain_chain_en","chain_en_const_U206.out"], - ["ub_kernel_cgra_stencil_BANK_45.chain_chain_en","chain_en_const_U208.out"], - ["ub_kernel_cgra_stencil_BANK_46.chain_chain_en","chain_en_const_U210.out"], - ["ub_kernel_cgra_stencil_BANK_47.chain_chain_en","chain_en_const_U212.out"], - ["ub_kernel_cgra_stencil_BANK_48.chain_chain_en","chain_en_const_U214.out"], - ["ub_kernel_cgra_stencil_BANK_49.chain_chain_en","chain_en_const_U216.out"], - ["ub_kernel_cgra_stencil_BANK_50.chain_chain_en","chain_en_const_U218.out"], - ["ub_kernel_cgra_stencil_BANK_51.chain_chain_en","chain_en_const_U220.out"], - ["ub_kernel_cgra_stencil_BANK_52.chain_chain_en","chain_en_const_U222.out"], - ["ub_kernel_cgra_stencil_BANK_53.chain_chain_en","chain_en_const_U224.out"], - ["ub_kernel_cgra_stencil_BANK_54.chain_chain_en","chain_en_const_U226.out"], - ["ub_kernel_cgra_stencil_BANK_55.chain_chain_en","chain_en_const_U228.out"], - ["ub_kernel_cgra_stencil_BANK_56.chain_chain_en","chain_en_const_U230.out"], - ["ub_kernel_cgra_stencil_BANK_57.chain_chain_en","chain_en_const_U232.out"], - ["ub_kernel_cgra_stencil_BANK_58.chain_chain_en","chain_en_const_U234.out"], - ["ub_kernel_cgra_stencil_BANK_59.chain_chain_en","chain_en_const_U236.out"], - ["ub_kernel_cgra_stencil_BANK_60.chain_chain_en","chain_en_const_U238.out"], - ["ub_kernel_cgra_stencil_BANK_61.chain_chain_en","chain_en_const_U240.out"], - ["ub_kernel_cgra_stencil_BANK_62.chain_chain_en","chain_en_const_U242.out"], - ["ub_kernel_cgra_stencil_BANK_63.chain_chain_en","chain_en_const_U244.out"], ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_1.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_10.clk","self.clk"], @@ -6765,49 +6405,49 @@ ["op_hcompute_kernel_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U379":{ - "modref":"global.aff__U353" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U305":{ + "modref":"global.aff__U279" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U294":{ - "modref":"global.aff__U277" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U220":{ + "modref":"global.aff__U203" }, - "chain_en_const_U380":{ + "chain_en_const_U306":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U276":{ - "modref":"global.affine_controller__U246", + "ctrl__U202":{ + "modref":"global.affine_controller__U172", "metadata":{"garnet_remove":true} }, - "ctrl__U352":{ - "modref":"global.affine_controller__U295", + "ctrl__U278":{ + "modref":"global.affine_controller__U221", "metadata":{"garnet_remove":true} }, "kernel_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,256,2304,4608],"dimensionality":5,"extent":[8,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,1024,8,512]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9216],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U245"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,8,256,2304,4608],"dimensionality":5,"extent":[8,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,1024,8,512]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9216],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U352.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U379.d"], - ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U379.out"], - ["ctrl__U276.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U294.d"], - ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U294.out"], - ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U380.out"], - ["self.clk","ctrl__U276.clk"], - ["self.reset","ctrl__U276.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U276.valid"], - ["self.clk","ctrl__U352.clk"], - ["self.reset","ctrl__U352.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U352.valid"], + ["ctrl__U278.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U305.d"], + ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U305.out"], + ["ctrl__U202.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U220.d"], + ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U220.out"], + ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U306.out"], + ["self.clk","ctrl__U202.clk"], + ["self.reset","ctrl__U202.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U202.valid"], + ["self.clk","ctrl__U278.clk"], + ["self.reset","ctrl__U278.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U278.valid"], ["self.clk","kernel_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_kernel_glb_stencil_write.0","kernel_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_kernel_cgra_stencil_read.0","kernel_glb_stencil_BANK_0_ubuf.data_out_0"], ["self.reset","kernel_glb_stencil_BANK_0_ubuf.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U500":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U417":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6816,7 +6456,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U499":{ + "op_hcompute_hw_output_stencil_read_start_pt__U416":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6825,7 +6465,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U501":{ + "op_hcompute_hw_output_stencil_write_start_pt__U418":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6834,7 +6474,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U509":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U426":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6843,7 +6483,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U508":{ + "op_hcompute_input_glb_stencil_read_start_pt__U425":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6852,7 +6492,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U510":{ + "op_hcompute_input_glb_stencil_write_start_pt__U427":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6861,7 +6501,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U504":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U421":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6870,7 +6510,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U503":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U420":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6879,7 +6519,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U505":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U422":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -6945,42 +6585,10 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U384":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U386":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U388":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U390":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U392":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U394":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U396":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U381"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15837],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15840],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U381"} + "genargs":{"ID":["String","_U307"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15837],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15840],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -6988,8 +6596,8 @@ }, "ub_output_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9220],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[11529],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15839],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15841],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U383"} + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9220],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[11529],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15839],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15841],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -6997,8 +6605,8 @@ }, "ub_output_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U385"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15839],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15842],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U385"} + "genargs":{"ID":["String","_U309"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15839],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15842],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -7006,8 +6614,8 @@ }, "ub_output_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U387"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15841],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15843],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U387"} + "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15841],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15843],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -7015,8 +6623,8 @@ }, "ub_output_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15841],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15844],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U389"} + "genargs":{"ID":["String","_U311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15841],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15844],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -7024,8 +6632,8 @@ }, "ub_output_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U391"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15843],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15845],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U391"} + "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15843],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15845],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -7033,8 +6641,8 @@ }, "ub_output_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U393"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15843],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15846],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U393"} + "genargs":{"ID":["String","_U313"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15843],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15846],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -7042,8 +6650,8 @@ }, "ub_output_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U395"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15845],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15847],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U395"} + "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[11528],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[11522],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[15845],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[11524],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[15847],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -7051,14 +6659,6 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U382.out"], - ["ub_output_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U384.out"], - ["ub_output_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U386.out"], - ["ub_output_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U388.out"], - ["ub_output_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U390.out"], - ["ub_output_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U392.out"], - ["ub_output_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U394.out"], - ["ub_output_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U396.out"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], @@ -7136,42 +6736,42 @@ ["op_hcompute_output_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U496":{ - "modref":"global.aff__U482" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U413":{ + "modref":"global.aff__U399" }, - "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U457":{ - "modref":"global.aff__U437" + "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U374":{ + "modref":"global.aff__U354" }, - "chain_en_const_U497":{ + "chain_en_const_U414":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U436":{ - "modref":"global.affine_controller__U398", + "ctrl__U353":{ + "modref":"global.affine_controller__U315", "metadata":{"garnet_remove":true} }, - "ctrl__U481":{ - "modref":"global.affine_controller__U458", + "ctrl__U398":{ + "modref":"global.affine_controller__U375", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[22016],"cycle_stride":[1],"dimensionality":1,"extent":[3136],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[15840],"cycle_stride":[1,32,4608],"dimensionality":3,"extent":[32,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,32]}},"mode":"glb","verilog_name":"glb__U397"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[22016],"cycle_stride":[1],"dimensionality":1,"extent":[3136],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[15840],"cycle_stride":[1,32,4608],"dimensionality":3,"extent":[32,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,32]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U481.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U496.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U496.out"], - ["ctrl__U436.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U457.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U457.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U497.out"], - ["self.clk","ctrl__U436.clk"], - ["self.reset","ctrl__U436.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U436.valid"], - ["self.clk","ctrl__U481.clk"], - ["self.reset","ctrl__U481.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U481.valid"], + ["ctrl__U398.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U413.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U413.out"], + ["ctrl__U353.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U374.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U374.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U414.out"], + ["self.clk","ctrl__U353.clk"], + ["self.reset","ctrl__U353.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U353.valid"], + ["self.clk","ctrl__U398.clk"], + ["self.reset","ctrl__U398.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U398.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_glb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -7190,12 +6790,12 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U506":{ + "_U423":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U511":{ + "_U428":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -7216,22 +6816,22 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U500" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U417" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U498"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[22016],"cycle_stride":[1,64,448],"dimensionality":3,"extent":[64,7,7]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U498"} + "genargs":{"ID":["String","_U415"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[22016],"cycle_stride":[1,64,448],"dimensionality":3,"extent":[64,7,7]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U499" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U416" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U501" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U418" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" @@ -7240,22 +6840,22 @@ "modref":"global.cu_op_hcompute_input_glb_stencil" }, "op_hcompute_input_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U509" + "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U426" }, "op_hcompute_input_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U507"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,256],"dimensionality":3,"extent":[16,16,16]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U507"} + "genargs":{"ID":["String","_U424"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,256],"dimensionality":3,"extent":[16,16,16]}},"mode":"lake"} }, "op_hcompute_input_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_glb_stencil_read_start":{ - "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U508" + "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U425" }, "op_hcompute_input_glb_stencil_write_start":{ - "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U510" + "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U427" }, "op_hcompute_kernel_cgra_stencil":{ "modref":"global.cu_op_hcompute_kernel_cgra_stencil" @@ -7264,22 +6864,22 @@ "modref":"global.cu_op_hcompute_kernel_glb_stencil" }, "op_hcompute_kernel_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U504" + "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U421" }, "op_hcompute_kernel_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U502"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,1024,3072],"dimensionality":4,"extent":[16,64,3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U502"} + "genargs":{"ID":["String","_U419"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,1024,3072],"dimensionality":4,"extent":[16,64,3,3]}},"mode":"lake"} }, "op_hcompute_kernel_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_kernel_glb_stencil_read_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U503" + "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U420" }, "op_hcompute_kernel_glb_stencil_write_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U505" + "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U422" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -7340,10 +6940,10 @@ } }, "connections":[ - ["self.clk","_U506.clk"], - ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U506.in"], - ["self.clk","_U511.clk"], - ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U511.in"], + ["self.clk","_U423.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U423.in"], + ["self.clk","_U428.clk"], + ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U428.in"], ["self.clk","input_cgra_stencil.clk"], ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], ["op_hcompute_output_cgra_stencil_10.input_cgra_stencil_op_hcompute_output_cgra_stencil_10_read","input_cgra_stencil.op_hcompute_output_cgra_stencil_10_read"], diff --git a/aha_garnet_design_new/resnet5_1/resnet5_1_garnet.json b/aha_garnet_design_new/resnet5_1/resnet5_1_garnet.json index 170ff436c..a3b77161a 100644 --- a/aha_garnet_design_new/resnet5_1/resnet5_1_garnet.json +++ b/aha_garnet_design_new/resnet5_1/resnet5_1_garnet.json @@ -232,1407 +232,1425 @@ }, "global":{ "modules":{ - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U247":{ + "aff__U173":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U259":{ + "add_all__U185":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U260":{ + "add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U261":{ + "add_all__U187":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U262":{ + "add_all__U188":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U263":{ + "add_all__U189":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U248":{ + "coeff_0_U174":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U250":{ + "coeff_1_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U252":{ + "coeff_2_U178":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U254":{ + "coeff_3_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U256":{ + "coeff_4_U182":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U258":{ + "const_term_U184":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U249":{ + "mul_d0__U175":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U251":{ + "mul_d1__U177":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U253":{ + "mul_d2__U179":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U255":{ + "mul_d3__U181":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U257":{ + "mul_d4__U183":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U249.out","add_all__U259.in0"], - ["mul_d1__U251.out","add_all__U259.in1"], - ["add_all__U260.in0","add_all__U259.out"], - ["mul_d2__U253.out","add_all__U260.in1"], - ["add_all__U261.in0","add_all__U260.out"], - ["mul_d3__U255.out","add_all__U261.in1"], - ["add_all__U262.in0","add_all__U261.out"], - ["mul_d4__U257.out","add_all__U262.in1"], - ["add_all__U263.in0","add_all__U262.out"], - ["const_term_U258.out","add_all__U263.in1"], - ["self.out","add_all__U263.out"], - ["mul_d0__U249.in0","coeff_0_U248.out"], - ["mul_d1__U251.in0","coeff_1_U250.out"], - ["mul_d2__U253.in0","coeff_2_U252.out"], - ["mul_d3__U255.in0","coeff_3_U254.out"], - ["mul_d4__U257.in0","coeff_4_U256.out"], - ["self.d.0","mul_d0__U249.in1"], - ["self.d.1","mul_d1__U251.in1"], - ["self.d.2","mul_d2__U253.in1"], - ["self.d.3","mul_d3__U255.in1"], - ["self.d.4","mul_d4__U257.in1"] + ["mul_d0__U175.out","add_all__U185.in0"], + ["mul_d1__U177.out","add_all__U185.in1"], + ["add_all__U186.in0","add_all__U185.out"], + ["mul_d2__U179.out","add_all__U186.in1"], + ["add_all__U187.in0","add_all__U186.out"], + ["mul_d3__U181.out","add_all__U187.in1"], + ["add_all__U188.in0","add_all__U187.out"], + ["mul_d4__U183.out","add_all__U188.in1"], + ["add_all__U189.in0","add_all__U188.out"], + ["const_term_U184.out","add_all__U189.in1"], + ["self.out","add_all__U189.out"], + ["mul_d0__U175.in0","coeff_0_U174.out"], + ["mul_d1__U177.in0","coeff_1_U176.out"], + ["mul_d2__U179.in0","coeff_2_U178.out"], + ["mul_d3__U181.in0","coeff_3_U180.out"], + ["mul_d4__U183.in0","coeff_4_U182.out"], + ["self.d.0","mul_d0__U175.in1"], + ["self.d.1","mul_d1__U177.in1"], + ["self.d.2","mul_d2__U179.in1"], + ["self.d.3","mul_d3__U181.in1"], + ["self.d.4","mul_d4__U183.in1"] ] }, - "aff__U277":{ + "aff__U203":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U289":{ + "add_all__U215":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U290":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U291":{ + "add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U292":{ + "add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U293":{ + "add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U278":{ + "coeff_0_U204":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U280":{ + "coeff_1_U206":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U282":{ + "coeff_2_U208":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U284":{ + "coeff_3_U210":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U286":{ + "coeff_4_U212":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U288":{ + "const_term_U214":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U279":{ + "mul_d0__U205":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U281":{ + "mul_d1__U207":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U283":{ + "mul_d2__U209":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U285":{ + "mul_d3__U211":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U287":{ + "mul_d4__U213":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U279.out","add_all__U289.in0"], - ["mul_d1__U281.out","add_all__U289.in1"], - ["add_all__U290.in0","add_all__U289.out"], - ["mul_d2__U283.out","add_all__U290.in1"], - ["add_all__U291.in0","add_all__U290.out"], - ["mul_d3__U285.out","add_all__U291.in1"], - ["add_all__U292.in0","add_all__U291.out"], - ["mul_d4__U287.out","add_all__U292.in1"], - ["add_all__U293.in0","add_all__U292.out"], - ["const_term_U288.out","add_all__U293.in1"], - ["self.out","add_all__U293.out"], - ["mul_d0__U279.in0","coeff_0_U278.out"], - ["mul_d1__U281.in0","coeff_1_U280.out"], - ["mul_d2__U283.in0","coeff_2_U282.out"], - ["mul_d3__U285.in0","coeff_3_U284.out"], - ["mul_d4__U287.in0","coeff_4_U286.out"], - ["self.d.0","mul_d0__U279.in1"], - ["self.d.1","mul_d1__U281.in1"], - ["self.d.2","mul_d2__U283.in1"], - ["self.d.3","mul_d3__U285.in1"], - ["self.d.4","mul_d4__U287.in1"] + ["mul_d0__U205.out","add_all__U215.in0"], + ["mul_d1__U207.out","add_all__U215.in1"], + ["add_all__U216.in0","add_all__U215.out"], + ["mul_d2__U209.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d3__U211.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d4__U213.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["const_term_U214.out","add_all__U219.in1"], + ["self.out","add_all__U219.out"], + ["mul_d0__U205.in0","coeff_0_U204.out"], + ["mul_d1__U207.in0","coeff_1_U206.out"], + ["mul_d2__U209.in0","coeff_2_U208.out"], + ["mul_d3__U211.in0","coeff_3_U210.out"], + ["mul_d4__U213.in0","coeff_4_U212.out"], + ["self.d.0","mul_d0__U205.in1"], + ["self.d.1","mul_d1__U207.in1"], + ["self.d.2","mul_d2__U209.in1"], + ["self.d.3","mul_d3__U211.in1"], + ["self.d.4","mul_d4__U213.in1"] ] }, - "aff__U296":{ + "aff__U222":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U319":{ + "add_all__U245":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U320":{ + "add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U321":{ + "add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U297":{ + "coeff_0_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U299":{ + "coeff_1_U225":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_2_U301":{ + "coeff_2_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U303":{ + "coeff_3_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_4_U305":{ + "coeff_4_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_5_U307":{ + "coeff_5_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_6_U309":{ + "coeff_6_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U311":{ + "coeff_7_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U298":{ + "mul_d0__U224":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U300":{ + "mul_d1__U226":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U302":{ + "mul_d2__U228":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U304":{ + "mul_d3__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U306":{ + "mul_d4__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U308":{ + "mul_d5__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U310":{ + "mul_d6__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U312":{ + "mul_d7__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U298.out","add_all__U314.in0"], - ["mul_d1__U300.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U302.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U304.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U306.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["mul_d5__U308.out","add_all__U318.in1"], - ["add_all__U319.in0","add_all__U318.out"], - ["mul_d6__U310.out","add_all__U319.in1"], - ["add_all__U320.in0","add_all__U319.out"], - ["mul_d7__U312.out","add_all__U320.in1"], - ["add_all__U321.in0","add_all__U320.out"], - ["const_term_U313.out","add_all__U321.in1"], - ["self.out","add_all__U321.out"], - ["mul_d0__U298.in0","coeff_0_U297.out"], - ["mul_d1__U300.in0","coeff_1_U299.out"], - ["mul_d2__U302.in0","coeff_2_U301.out"], - ["mul_d3__U304.in0","coeff_3_U303.out"], - ["mul_d4__U306.in0","coeff_4_U305.out"], - ["mul_d5__U308.in0","coeff_5_U307.out"], - ["mul_d6__U310.in0","coeff_6_U309.out"], - ["mul_d7__U312.in0","coeff_7_U311.out"], - ["self.d.0","mul_d0__U298.in1"], - ["self.d.1","mul_d1__U300.in1"], - ["self.d.2","mul_d2__U302.in1"], - ["self.d.3","mul_d3__U304.in1"], - ["self.d.4","mul_d4__U306.in1"], - ["self.d.5","mul_d5__U308.in1"], - ["self.d.6","mul_d6__U310.in1"], - ["self.d.7","mul_d7__U312.in1"] + ["mul_d0__U224.out","add_all__U240.in0"], + ["mul_d1__U226.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U228.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U230.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U232.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["mul_d5__U234.out","add_all__U244.in1"], + ["add_all__U245.in0","add_all__U244.out"], + ["mul_d6__U236.out","add_all__U245.in1"], + ["add_all__U246.in0","add_all__U245.out"], + ["mul_d7__U238.out","add_all__U246.in1"], + ["add_all__U247.in0","add_all__U246.out"], + ["const_term_U239.out","add_all__U247.in1"], + ["self.out","add_all__U247.out"], + ["mul_d0__U224.in0","coeff_0_U223.out"], + ["mul_d1__U226.in0","coeff_1_U225.out"], + ["mul_d2__U228.in0","coeff_2_U227.out"], + ["mul_d3__U230.in0","coeff_3_U229.out"], + ["mul_d4__U232.in0","coeff_4_U231.out"], + ["mul_d5__U234.in0","coeff_5_U233.out"], + ["mul_d6__U236.in0","coeff_6_U235.out"], + ["mul_d7__U238.in0","coeff_7_U237.out"], + ["self.d.0","mul_d0__U224.in1"], + ["self.d.1","mul_d1__U226.in1"], + ["self.d.2","mul_d2__U228.in1"], + ["self.d.3","mul_d3__U230.in1"], + ["self.d.4","mul_d4__U232.in1"], + ["self.d.5","mul_d5__U234.in1"], + ["self.d.6","mul_d6__U236.in1"], + ["self.d.7","mul_d7__U238.in1"] ] }, - "aff__U353":{ + "aff__U279":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U371":{ + "add_all__U297":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U372":{ + "add_all__U298":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U373":{ + "add_all__U299":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U374":{ + "add_all__U300":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U375":{ + "add_all__U301":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U376":{ + "add_all__U302":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U377":{ + "add_all__U303":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U378":{ + "add_all__U304":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U354":{ + "coeff_0_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U356":{ + "coeff_1_U282":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U358":{ + "coeff_2_U284":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_3_U360":{ + "coeff_3_U286":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U362":{ + "coeff_4_U288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U364":{ + "coeff_5_U290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U366":{ + "coeff_6_U292":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U368":{ + "coeff_7_U294":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U370":{ + "const_term_U296":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U355":{ + "mul_d0__U281":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U357":{ + "mul_d1__U283":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U359":{ + "mul_d2__U285":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U361":{ + "mul_d3__U287":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U363":{ + "mul_d4__U289":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U365":{ + "mul_d5__U291":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U367":{ + "mul_d6__U293":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U369":{ + "mul_d7__U295":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U355.out","add_all__U371.in0"], - ["mul_d1__U357.out","add_all__U371.in1"], - ["add_all__U372.in0","add_all__U371.out"], - ["mul_d2__U359.out","add_all__U372.in1"], - ["add_all__U373.in0","add_all__U372.out"], - ["mul_d3__U361.out","add_all__U373.in1"], - ["add_all__U374.in0","add_all__U373.out"], - ["mul_d4__U363.out","add_all__U374.in1"], - ["add_all__U375.in0","add_all__U374.out"], - ["mul_d5__U365.out","add_all__U375.in1"], - ["add_all__U376.in0","add_all__U375.out"], - ["mul_d6__U367.out","add_all__U376.in1"], - ["add_all__U377.in0","add_all__U376.out"], - ["mul_d7__U369.out","add_all__U377.in1"], - ["add_all__U378.in0","add_all__U377.out"], - ["const_term_U370.out","add_all__U378.in1"], - ["self.out","add_all__U378.out"], - ["mul_d0__U355.in0","coeff_0_U354.out"], - ["mul_d1__U357.in0","coeff_1_U356.out"], - ["mul_d2__U359.in0","coeff_2_U358.out"], - ["mul_d3__U361.in0","coeff_3_U360.out"], - ["mul_d4__U363.in0","coeff_4_U362.out"], - ["mul_d5__U365.in0","coeff_5_U364.out"], - ["mul_d6__U367.in0","coeff_6_U366.out"], - ["mul_d7__U369.in0","coeff_7_U368.out"], - ["self.d.0","mul_d0__U355.in1"], - ["self.d.1","mul_d1__U357.in1"], - ["self.d.2","mul_d2__U359.in1"], - ["self.d.3","mul_d3__U361.in1"], - ["self.d.4","mul_d4__U363.in1"], - ["self.d.5","mul_d5__U365.in1"], - ["self.d.6","mul_d6__U367.in1"], - ["self.d.7","mul_d7__U369.in1"] + ["mul_d0__U281.out","add_all__U297.in0"], + ["mul_d1__U283.out","add_all__U297.in1"], + ["add_all__U298.in0","add_all__U297.out"], + ["mul_d2__U285.out","add_all__U298.in1"], + ["add_all__U299.in0","add_all__U298.out"], + ["mul_d3__U287.out","add_all__U299.in1"], + ["add_all__U300.in0","add_all__U299.out"], + ["mul_d4__U289.out","add_all__U300.in1"], + ["add_all__U301.in0","add_all__U300.out"], + ["mul_d5__U291.out","add_all__U301.in1"], + ["add_all__U302.in0","add_all__U301.out"], + ["mul_d6__U293.out","add_all__U302.in1"], + ["add_all__U303.in0","add_all__U302.out"], + ["mul_d7__U295.out","add_all__U303.in1"], + ["add_all__U304.in0","add_all__U303.out"], + ["const_term_U296.out","add_all__U304.in1"], + ["self.out","add_all__U304.out"], + ["mul_d0__U281.in0","coeff_0_U280.out"], + ["mul_d1__U283.in0","coeff_1_U282.out"], + ["mul_d2__U285.in0","coeff_2_U284.out"], + ["mul_d3__U287.in0","coeff_3_U286.out"], + ["mul_d4__U289.in0","coeff_4_U288.out"], + ["mul_d5__U291.in0","coeff_5_U290.out"], + ["mul_d6__U293.in0","coeff_6_U292.out"], + ["mul_d7__U295.in0","coeff_7_U294.out"], + ["self.d.0","mul_d0__U281.in1"], + ["self.d.1","mul_d1__U283.in1"], + ["self.d.2","mul_d2__U285.in1"], + ["self.d.3","mul_d3__U287.in1"], + ["self.d.4","mul_d4__U289.in1"], + ["self.d.5","mul_d5__U291.in1"], + ["self.d.6","mul_d6__U293.in1"], + ["self.d.7","mul_d7__U295.in1"] ] }, - "aff__U399":{ + "aff__U316":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U413":{ + "add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U414":{ + "add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U415":{ + "add_all__U332":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U418":{ + "add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U400":{ + "coeff_0_U317":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U402":{ + "coeff_1_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_2_U404":{ + "coeff_2_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "coeff_3_U406":{ + "coeff_3_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_4_U408":{ + "coeff_4_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U410":{ + "coeff_5_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U412":{ + "const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003de0"]} }, - "mul_d0__U401":{ + "mul_d0__U318":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U403":{ + "mul_d1__U320":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U405":{ + "mul_d2__U322":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U407":{ + "mul_d3__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U409":{ + "mul_d4__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U411":{ + "mul_d5__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U401.out","add_all__U413.in0"], - ["mul_d1__U403.out","add_all__U413.in1"], - ["add_all__U414.in0","add_all__U413.out"], - ["mul_d2__U405.out","add_all__U414.in1"], - ["add_all__U415.in0","add_all__U414.out"], - ["mul_d3__U407.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d4__U409.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["mul_d5__U411.out","add_all__U417.in1"], - ["add_all__U418.in0","add_all__U417.out"], - ["const_term_U412.out","add_all__U418.in1"], - ["self.out","add_all__U418.out"], - ["mul_d0__U401.in0","coeff_0_U400.out"], - ["mul_d1__U403.in0","coeff_1_U402.out"], - ["mul_d2__U405.in0","coeff_2_U404.out"], - ["mul_d3__U407.in0","coeff_3_U406.out"], - ["mul_d4__U409.in0","coeff_4_U408.out"], - ["mul_d5__U411.in0","coeff_5_U410.out"], - ["self.d.0","mul_d0__U401.in1"], - ["self.d.1","mul_d1__U403.in1"], - ["self.d.2","mul_d2__U405.in1"], - ["self.d.3","mul_d3__U407.in1"], - ["self.d.4","mul_d4__U409.in1"], - ["self.d.5","mul_d5__U411.in1"] + ["mul_d0__U318.out","add_all__U330.in0"], + ["mul_d1__U320.out","add_all__U330.in1"], + ["add_all__U331.in0","add_all__U330.out"], + ["mul_d2__U322.out","add_all__U331.in1"], + ["add_all__U332.in0","add_all__U331.out"], + ["mul_d3__U324.out","add_all__U332.in1"], + ["add_all__U333.in0","add_all__U332.out"], + ["mul_d4__U326.out","add_all__U333.in1"], + ["add_all__U334.in0","add_all__U333.out"], + ["mul_d5__U328.out","add_all__U334.in1"], + ["add_all__U335.in0","add_all__U334.out"], + ["const_term_U329.out","add_all__U335.in1"], + ["self.out","add_all__U335.out"], + ["mul_d0__U318.in0","coeff_0_U317.out"], + ["mul_d1__U320.in0","coeff_1_U319.out"], + ["mul_d2__U322.in0","coeff_2_U321.out"], + ["mul_d3__U324.in0","coeff_3_U323.out"], + ["mul_d4__U326.in0","coeff_4_U325.out"], + ["mul_d5__U328.in0","coeff_5_U327.out"], + ["self.d.0","mul_d0__U318.in1"], + ["self.d.1","mul_d1__U320.in1"], + ["self.d.2","mul_d2__U322.in1"], + ["self.d.3","mul_d3__U324.in1"], + ["self.d.4","mul_d4__U326.in1"], + ["self.d.5","mul_d5__U328.in1"] ] }, - "aff__U41":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U51":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U52":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U53":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U42":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U44":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U46":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U48":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U50":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U43":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U437":{ + "aff__U354":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U453":{ + "add_all__U370":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U454":{ + "add_all__U371":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U455":{ + "add_all__U372":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U456":{ + "add_all__U373":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U355":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_2_U442":{ + "coeff_2_U359":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U444":{ + "coeff_3_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_4_U446":{ + "coeff_4_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_5_U448":{ + "coeff_5_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U450":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U439":{ + "mul_d0__U356":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U358":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U443":{ + "mul_d2__U360":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U445":{ + "mul_d3__U362":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U447":{ + "mul_d4__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U449":{ + "mul_d5__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U451.in0"], - ["mul_d1__U441.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["mul_d2__U443.out","add_all__U452.in1"], - ["add_all__U453.in0","add_all__U452.out"], - ["mul_d3__U445.out","add_all__U453.in1"], - ["add_all__U454.in0","add_all__U453.out"], - ["mul_d4__U447.out","add_all__U454.in1"], - ["add_all__U455.in0","add_all__U454.out"], - ["mul_d5__U449.out","add_all__U455.in1"], - ["add_all__U456.in0","add_all__U455.out"], - ["const_term_U450.out","add_all__U456.in1"], - ["self.out","add_all__U456.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["mul_d2__U443.in0","coeff_2_U442.out"], - ["mul_d3__U445.in0","coeff_3_U444.out"], - ["mul_d4__U447.in0","coeff_4_U446.out"], - ["mul_d5__U449.in0","coeff_5_U448.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"], - ["self.d.2","mul_d2__U443.in1"], - ["self.d.3","mul_d3__U445.in1"], - ["self.d.4","mul_d4__U447.in1"], - ["self.d.5","mul_d5__U449.in1"] + ["mul_d0__U356.out","add_all__U368.in0"], + ["mul_d1__U358.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["mul_d2__U360.out","add_all__U369.in1"], + ["add_all__U370.in0","add_all__U369.out"], + ["mul_d3__U362.out","add_all__U370.in1"], + ["add_all__U371.in0","add_all__U370.out"], + ["mul_d4__U364.out","add_all__U371.in1"], + ["add_all__U372.in0","add_all__U371.out"], + ["mul_d5__U366.out","add_all__U372.in1"], + ["add_all__U373.in0","add_all__U372.out"], + ["const_term_U367.out","add_all__U373.in1"], + ["self.out","add_all__U373.out"], + ["mul_d0__U356.in0","coeff_0_U355.out"], + ["mul_d1__U358.in0","coeff_1_U357.out"], + ["mul_d2__U360.in0","coeff_2_U359.out"], + ["mul_d3__U362.in0","coeff_3_U361.out"], + ["mul_d4__U364.in0","coeff_4_U363.out"], + ["mul_d5__U366.in0","coeff_5_U365.out"], + ["self.d.0","mul_d0__U356.in1"], + ["self.d.1","mul_d1__U358.in1"], + ["self.d.2","mul_d2__U360.in1"], + ["self.d.3","mul_d3__U362.in1"], + ["self.d.4","mul_d4__U364.in1"], + ["self.d.5","mul_d5__U366.in1"] ] }, - "aff__U459":{ + "aff__U376":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U469":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U470":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U471":{ + "add_all__U388":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U472":{ + "add_all__U389":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U460":{ + "coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U462":{ + "coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_2_U464":{ + "coeff_2_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U466":{ + "coeff_3_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U468":{ + "const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000055ff"]} }, - "mul_d0__U461":{ + "mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U463":{ + "mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U465":{ + "mul_d2__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U467":{ + "mul_d3__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U461.out","add_all__U469.in0"], - ["mul_d1__U463.out","add_all__U469.in1"], - ["add_all__U470.in0","add_all__U469.out"], - ["mul_d2__U465.out","add_all__U470.in1"], - ["add_all__U471.in0","add_all__U470.out"], - ["mul_d3__U467.out","add_all__U471.in1"], - ["add_all__U472.in0","add_all__U471.out"], - ["const_term_U468.out","add_all__U472.in1"], - ["self.out","add_all__U472.out"], - ["mul_d0__U461.in0","coeff_0_U460.out"], - ["mul_d1__U463.in0","coeff_1_U462.out"], - ["mul_d2__U465.in0","coeff_2_U464.out"], - ["mul_d3__U467.in0","coeff_3_U466.out"], - ["self.d.0","mul_d0__U461.in1"], - ["self.d.1","mul_d1__U463.in1"], - ["self.d.2","mul_d2__U465.in1"], - ["self.d.3","mul_d3__U467.in1"] + ["mul_d0__U378.out","add_all__U386.in0"], + ["mul_d1__U380.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["mul_d2__U382.out","add_all__U387.in1"], + ["add_all__U388.in0","add_all__U387.out"], + ["mul_d3__U384.out","add_all__U388.in1"], + ["add_all__U389.in0","add_all__U388.out"], + ["const_term_U385.out","add_all__U389.in1"], + ["self.out","add_all__U389.out"], + ["mul_d0__U378.in0","coeff_0_U377.out"], + ["mul_d1__U380.in0","coeff_1_U379.out"], + ["mul_d2__U382.in0","coeff_2_U381.out"], + ["mul_d3__U384.in0","coeff_3_U383.out"], + ["self.d.0","mul_d0__U378.in1"], + ["self.d.1","mul_d1__U380.in1"], + ["self.d.2","mul_d2__U382.in1"], + ["self.d.3","mul_d3__U384.in1"] ] }, - "aff__U482":{ + "aff__U399":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U492":{ + "add_all__U409":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U493":{ + "add_all__U410":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U494":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U495":{ + "add_all__U412":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U400":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U402":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U487":{ + "coeff_2_U404":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_3_U489":{ + "coeff_3_U406":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U491":{ + "const_term_U408":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U484":{ + "mul_d0__U401":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U403":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U488":{ + "mul_d2__U405":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U490":{ + "mul_d3__U407":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U492.in0"], - ["mul_d1__U486.out","add_all__U492.in1"], - ["add_all__U493.in0","add_all__U492.out"], - ["mul_d2__U488.out","add_all__U493.in1"], - ["add_all__U494.in0","add_all__U493.out"], - ["mul_d3__U490.out","add_all__U494.in1"], - ["add_all__U495.in0","add_all__U494.out"], - ["const_term_U491.out","add_all__U495.in1"], - ["self.out","add_all__U495.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["mul_d2__U488.in0","coeff_2_U487.out"], - ["mul_d3__U490.in0","coeff_3_U489.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"], - ["self.d.2","mul_d2__U488.in1"], - ["self.d.3","mul_d3__U490.in1"] + ["mul_d0__U401.out","add_all__U409.in0"], + ["mul_d1__U403.out","add_all__U409.in1"], + ["add_all__U410.in0","add_all__U409.out"], + ["mul_d2__U405.out","add_all__U410.in1"], + ["add_all__U411.in0","add_all__U410.out"], + ["mul_d3__U407.out","add_all__U411.in1"], + ["add_all__U412.in0","add_all__U411.out"], + ["const_term_U408.out","add_all__U412.in1"], + ["self.out","add_all__U412.out"], + ["mul_d0__U401.in0","coeff_0_U400.out"], + ["mul_d1__U403.in0","coeff_1_U402.out"], + ["mul_d2__U405.in0","coeff_2_U404.out"], + ["mul_d3__U407.in0","coeff_3_U406.out"], + ["self.d.0","mul_d0__U401.in1"], + ["self.d.1","mul_d1__U403.in1"], + ["self.d.2","mul_d2__U405.in1"], + ["self.d.3","mul_d3__U407.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U71":{ + "add_all__U62":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U72":{ + "add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U73":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U74":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U70":{ + "const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U71.in0"], - ["mul_d1__U61.out","add_all__U71.in1"], - ["add_all__U72.in0","add_all__U71.out"], - ["mul_d2__U63.out","add_all__U72.in1"], - ["add_all__U73.in0","add_all__U72.out"], - ["mul_d3__U65.out","add_all__U73.in1"], - ["add_all__U74.in0","add_all__U73.out"], - ["mul_d4__U67.out","add_all__U74.in1"], - ["add_all__U75.in0","add_all__U74.out"], - ["mul_d5__U69.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["const_term_U70.out","add_all__U76.in1"], - ["self.out","add_all__U76.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"] + ["mul_d0__U50.out","add_all__U62.in0"], + ["mul_d1__U52.out","add_all__U62.in1"], + ["add_all__U63.in0","add_all__U62.out"], + ["mul_d2__U54.out","add_all__U63.in1"], + ["add_all__U64.in0","add_all__U63.out"], + ["mul_d3__U56.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["mul_d4__U58.out","add_all__U65.in1"], + ["add_all__U66.in0","add_all__U65.out"], + ["mul_d5__U60.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["const_term_U61.out","add_all__U67.in1"], + ["self.out","add_all__U67.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U109":{ + "add_all__U100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U110":{ + "add_all__U101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000800"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U108":{ + "const_term_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U90":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U92":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U94":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U101":{ + "mul_d5__U98":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U88.out","add_all__U100.in0"], + ["mul_d1__U90.out","add_all__U100.in1"], + ["add_all__U101.in0","add_all__U100.out"], + ["mul_d2__U92.out","add_all__U101.in1"], + ["add_all__U102.in0","add_all__U101.out"], + ["mul_d3__U94.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d4__U96.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d5__U98.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["const_term_U99.out","add_all__U105.in1"], + ["self.out","add_all__U105.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"] + ] + }, + "aff__U9":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U19":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U20":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U21":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U22":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U109.in0"], - ["mul_d1__U99.out","add_all__U109.in1"], - ["add_all__U110.in0","add_all__U109.out"], - ["mul_d2__U101.out","add_all__U110.in1"], - ["add_all__U111.in0","add_all__U110.out"], - ["mul_d3__U103.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d4__U105.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d5__U107.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U108.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U17":{ + "affine_controller__U172":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",5,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U32":{ + "_U190":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U321":{ + "_U1902":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U322":{ + "_U1903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U1904":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U33":{ + "_U191":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U28":{ + "affine_func$add_all__U185":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U186":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U29":{ + "affine_func$add_all__U187":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U30":{ + "affine_func$add_all__U188":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U31":{ + "affine_func$add_all__U189":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U19":{ + "affine_func$coeff_0_U174":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U21":{ + "affine_func$coeff_1_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + }, + "affine_func$coeff_2_U178":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "affine_func$coeff_2_U23":{ + "affine_func$coeff_3_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U25":{ + "affine_func$coeff_4_U182":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U27":{ + "affine_func$const_term_U184":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U20":{ + "affine_func$mul_d0__U175":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U177":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U22":{ + "affine_func$mul_d2__U179":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U24":{ + "affine_func$mul_d3__U181":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U26":{ + "affine_func$mul_d4__U183":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -1696,32 +1714,42 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U34$c0_lutcnst":{ + "d_0_am__U192$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U192$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U193$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U34$lut$lut":{ + "d_0_am__U193$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U35$c0_lutcnst":{ + "d_0_am__U194$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U35$lut$lut":{ + "d_0_am__U194$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U36$c0_lutcnst":{ + "d_0_am__U195$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U36$lut$lut":{ + "d_0_am__U195$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1770,22 +1798,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U37$c0_lutcnst":{ + "d_1_am__U196$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U196$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U197$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U37$lut$lut":{ + "d_1_am__U197$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U38$c0_lutcnst":{ + "d_1_am__U198$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U38$lut$lut":{ + "d_1_am__U198$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1801,7 +1839,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -1834,12 +1872,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U39$c0_lutcnst":{ + "d_2_am__U199$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U199$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U200$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U39$lut$lut":{ + "d_2_am__U200$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -1855,7 +1903,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -1888,6 +1936,16 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U201$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U201$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -1899,7 +1957,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -1932,6 +1990,50 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -1961,6 +2063,11 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -1968,33 +2075,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U321.out"], - ["d_2_inc.in1","_U322.out"], - ["d_3_inc.in1","_U323.out"], - ["cmp_time.in1","_U33.out"], - ["affine_func$mul_d0__U20.out","affine_func$add_all__U28.in0"], - ["affine_func$mul_d1__U22.out","affine_func$add_all__U28.in1"], - ["affine_func$add_all__U29.in0","affine_func$add_all__U28.out"], - ["affine_func$mul_d2__U24.out","affine_func$add_all__U29.in1"], - ["affine_func$add_all__U30.in0","affine_func$add_all__U29.out"], - ["affine_func$mul_d3__U26.out","affine_func$add_all__U30.in1"], - ["affine_func$add_all__U31.in0","affine_func$add_all__U30.out"], - ["affine_func$const_term_U27.out","affine_func$add_all__U31.in1"], - ["time_diff.in0","affine_func$add_all__U31.out"], - ["affine_func$mul_d0__U20.in0","affine_func$coeff_0_U19.out"], - ["affine_func$mul_d1__U22.in0","affine_func$coeff_1_U21.out"], - ["affine_func$mul_d2__U24.in0","affine_func$coeff_2_U23.out"], - ["affine_func$mul_d3__U26.in0","affine_func$coeff_3_U25.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U20.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U22.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U24.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U26.in1"], + ["d_0_inc.in1","_U190.out"], + ["d_1_inc.in1","_U1901.out"], + ["d_2_inc.in1","_U1902.out"], + ["d_3_inc.in1","_U1903.out"], + ["d_4_inc.in1","_U1904.out"], + ["cmp_time.in1","_U191.out"], + ["affine_func$mul_d0__U175.out","affine_func$add_all__U185.in0"], + ["affine_func$mul_d1__U177.out","affine_func$add_all__U185.in1"], + ["affine_func$add_all__U186.in0","affine_func$add_all__U185.out"], + ["affine_func$mul_d2__U179.out","affine_func$add_all__U186.in1"], + ["affine_func$add_all__U187.in0","affine_func$add_all__U186.out"], + ["affine_func$mul_d3__U181.out","affine_func$add_all__U187.in1"], + ["affine_func$add_all__U188.in0","affine_func$add_all__U187.out"], + ["affine_func$mul_d4__U183.out","affine_func$add_all__U188.in1"], + ["affine_func$add_all__U189.in0","affine_func$add_all__U188.out"], + ["affine_func$const_term_U184.out","affine_func$add_all__U189.in1"], + ["time_diff.in0","affine_func$add_all__U189.out"], + ["affine_func$mul_d0__U175.in0","affine_func$coeff_0_U174.out"], + ["affine_func$mul_d1__U177.in0","affine_func$coeff_1_U176.out"], + ["affine_func$mul_d2__U179.in0","affine_func$coeff_2_U178.out"], + ["affine_func$mul_d3__U181.in0","affine_func$coeff_3_U180.out"], + ["affine_func$mul_d4__U183.in0","affine_func$coeff_4_U182.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U175.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U177.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U179.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U181.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U183.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -2002,28 +2115,31 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U34$lut$lut.bit.in.2","d_0_am__U34$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U34$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U34$lut$lut.bit.in.1"], - ["d_0_am__U35$lut$lut.bit.in.0","d_0_am__U34$lut$lut.bit.out"], - ["d_0_am__U35$lut$lut.bit.in.2","d_0_am__U35$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U35$lut$lut.bit.in.1"], - ["d_0_am__U36$lut$lut.bit.in.0","d_0_am__U35$lut$lut.bit.out"], - ["d_0_am__U36$lut$lut.bit.in.2","d_0_am__U36$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U36$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U36$lut$lut.bit.out"], + ["d_0_am__U192$lut$lut.bit.in.2","d_0_am__U192$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U192$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U192$lut$lut.bit.in.1"], + ["d_0_am__U193$lut$lut.bit.in.0","d_0_am__U192$lut$lut.bit.out"], + ["d_0_am__U193$lut$lut.bit.in.2","d_0_am__U193$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U193$lut$lut.bit.in.1"], + ["d_0_am__U194$lut$lut.bit.in.0","d_0_am__U193$lut$lut.bit.out"], + ["d_0_am__U194$lut$lut.bit.in.2","d_0_am__U194$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U194$lut$lut.bit.in.1"], + ["d_0_am__U195$lut$lut.bit.in.0","d_0_am__U194$lut$lut.bit.out"], + ["d_0_am__U195$lut$lut.bit.in.2","d_0_am__U195$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U195$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U195$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2040,13 +2156,16 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U37$lut$lut.bit.in.2","d_1_am__U37$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U37$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U37$lut$lut.bit.in.1"], - ["d_1_am__U38$lut$lut.bit.in.0","d_1_am__U37$lut$lut.bit.out"], - ["d_1_am__U38$lut$lut.bit.in.2","d_1_am__U38$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U38$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U38$lut$lut.bit.out"], + ["d_1_am__U196$lut$lut.bit.in.2","d_1_am__U196$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U196$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U196$lut$lut.bit.in.1"], + ["d_1_am__U197$lut$lut.bit.in.0","d_1_am__U196$lut$lut.bit.out"], + ["d_1_am__U197$lut$lut.bit.in.2","d_1_am__U197$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U197$lut$lut.bit.in.1"], + ["d_1_am__U198$lut$lut.bit.in.0","d_1_am__U197$lut$lut.bit.out"], + ["d_1_am__U198$lut$lut.bit.in.2","d_1_am__U198$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U198$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U198$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2063,10 +2182,13 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U39$lut$lut.bit.in.2","d_2_am__U39$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U39$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U39$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U39$lut$lut.bit.out"], + ["d_2_am__U199$lut$lut.bit.in.2","d_2_am__U199$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U199$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U199$lut$lut.bit.in.1"], + ["d_2_am__U200$lut$lut.bit.in.0","d_2_am__U199$lut$lut.bit.out"], + ["d_2_am__U200$lut$lut.bit.in.2","d_2_am__U200$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U200$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U200$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2083,6 +2205,10 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U201$lut$lut.bit.in.2","d_3_am__U201$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U201$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U201$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U201$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2092,121 +2218,191 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["true_lutcnst.bit.out","d_4_next_value.sel"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"] ] }, - "affine_controller__U246":{ + "affine_controller__U221":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], + ["d",["Array",8,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U264":{ + "_U248":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2481":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2482":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2641":{ + "_U2483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2642":{ + "_U2484":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2643":{ + "_U2485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2644":{ + "_U2486":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U265":{ + "_U2487":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U259":{ + "affine_func$add_all__U240":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U241":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U242":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U260":{ + "affine_func$add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U261":{ + "affine_func$add_all__U245":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U262":{ + "affine_func$add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U263":{ + "affine_func$add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U248":{ + "affine_func$coeff_0_U223":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U250":{ + "affine_func$coeff_1_U225":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "affine_func$coeff_2_U252":{ + "affine_func$coeff_2_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "affine_func$coeff_3_U254":{ + "affine_func$coeff_3_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00000300"]} + }, + "affine_func$coeff_4_U231":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "affine_func$coeff_5_U233":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_6_U235":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_4_U256":{ + "affine_func$coeff_7_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U258":{ + "affine_func$const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h000023ff"]} + }, + "affine_func$mul_d0__U224":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U226":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U228":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U249":{ + "affine_func$mul_d3__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U251":{ + "affine_func$mul_d4__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U253":{ + "affine_func$mul_d5__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U255":{ + "affine_func$mul_d6__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U257":{ + "affine_func$mul_d7__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2270,42 +2466,72 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U266$c0_lutcnst":{ + "d_0_am__U250$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U250$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U251$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U251$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U252$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U252$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U253$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U266$lut$lut":{ + "d_0_am__U253$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U267$c0_lutcnst":{ + "d_0_am__U254$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U267$lut$lut":{ + "d_0_am__U254$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U268$c0_lutcnst":{ + "d_0_am__U255$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U268$lut$lut":{ + "d_0_am__U255$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U269$c0_lutcnst":{ + "d_0_am__U256$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U269$lut$lut":{ + "d_0_am__U256$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2354,32 +2580,62 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U270$c0_lutcnst":{ + "d_1_am__U257$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U257$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U258$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U258$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U259$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U259$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U260$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U270$lut$lut":{ + "d_1_am__U260$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U271$c0_lutcnst":{ + "d_1_am__U261$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U271$lut$lut":{ + "d_1_am__U261$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U272$c0_lutcnst":{ + "d_1_am__U262$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U272$lut$lut":{ + "d_1_am__U262$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2395,7 +2651,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2428,22 +2684,52 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U273$c0_lutcnst":{ + "d_2_am__U263$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U263$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U264$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U264$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U265$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U265$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U266$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U273$lut$lut":{ + "d_2_am__U266$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U274$c0_lutcnst":{ + "d_2_am__U267$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U274$lut$lut":{ + "d_2_am__U267$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2459,7 +2745,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2492,12 +2778,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U275$c0_lutcnst":{ + "d_3_am__U268$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U268$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U269$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U269$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U270$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U270$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U271$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U275$lut$lut":{ + "d_3_am__U271$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2513,7 +2829,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_3_min":{ "genref":"coreir.const", @@ -2546,6 +2862,36 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_am__U272$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U272$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U273$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U273$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U274$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U274$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -2557,7 +2903,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_4_min":{ "genref":"coreir.const", @@ -2590,112 +2936,316 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ + "d_5_am__U275$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true2_lutcnst":{ + "d_5_am__U275$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true3_lutcnst":{ + "d_5_am__U276$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true4_lutcnst":{ + "d_5_am__U276$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "true_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U264.out"], - ["d_1_inc.in1","_U2641.out"], - ["d_2_inc.in1","_U2642.out"], - ["d_3_inc.in1","_U2643.out"], - ["d_4_inc.in1","_U2644.out"], - ["cmp_time.in1","_U265.out"], - ["affine_func$mul_d0__U249.out","affine_func$add_all__U259.in0"], - ["affine_func$mul_d1__U251.out","affine_func$add_all__U259.in1"], - ["affine_func$add_all__U260.in0","affine_func$add_all__U259.out"], - ["affine_func$mul_d2__U253.out","affine_func$add_all__U260.in1"], - ["affine_func$add_all__U261.in0","affine_func$add_all__U260.out"], - ["affine_func$mul_d3__U255.out","affine_func$add_all__U261.in1"], - ["affine_func$add_all__U262.in0","affine_func$add_all__U261.out"], - ["affine_func$mul_d4__U257.out","affine_func$add_all__U262.in1"], - ["affine_func$add_all__U263.in0","affine_func$add_all__U262.out"], - ["affine_func$const_term_U258.out","affine_func$add_all__U263.in1"], - ["time_diff.in0","affine_func$add_all__U263.out"], - ["affine_func$mul_d0__U249.in0","affine_func$coeff_0_U248.out"], - ["affine_func$mul_d1__U251.in0","affine_func$coeff_1_U250.out"], - ["affine_func$mul_d2__U253.in0","affine_func$coeff_2_U252.out"], - ["affine_func$mul_d3__U255.in0","affine_func$coeff_3_U254.out"], - ["affine_func$mul_d4__U257.in0","affine_func$coeff_4_U256.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U249.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U251.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U253.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U255.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U257.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000003"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_6_am__U277$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_6_am__U277$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_7_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_7_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_7_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_7_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true2_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true3_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true8_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true9_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U248.out"], + ["d_1_inc.in1","_U2481.out"], + ["d_2_inc.in1","_U2482.out"], + ["d_3_inc.in1","_U2483.out"], + ["d_4_inc.in1","_U2484.out"], + ["d_5_inc.in1","_U2485.out"], + ["d_6_inc.in1","_U2486.out"], + ["d_7_inc.in1","_U2487.out"], + ["cmp_time.in1","_U249.out"], + ["affine_func$mul_d0__U224.out","affine_func$add_all__U240.in0"], + ["affine_func$mul_d1__U226.out","affine_func$add_all__U240.in1"], + ["affine_func$add_all__U241.in0","affine_func$add_all__U240.out"], + ["affine_func$mul_d2__U228.out","affine_func$add_all__U241.in1"], + ["affine_func$add_all__U242.in0","affine_func$add_all__U241.out"], + ["affine_func$mul_d3__U230.out","affine_func$add_all__U242.in1"], + ["affine_func$add_all__U243.in0","affine_func$add_all__U242.out"], + ["affine_func$mul_d4__U232.out","affine_func$add_all__U243.in1"], + ["affine_func$add_all__U244.in0","affine_func$add_all__U243.out"], + ["affine_func$mul_d5__U234.out","affine_func$add_all__U244.in1"], + ["affine_func$add_all__U245.in0","affine_func$add_all__U244.out"], + ["affine_func$mul_d6__U236.out","affine_func$add_all__U245.in1"], + ["affine_func$add_all__U246.in0","affine_func$add_all__U245.out"], + ["affine_func$mul_d7__U238.out","affine_func$add_all__U246.in1"], + ["affine_func$add_all__U247.in0","affine_func$add_all__U246.out"], + ["affine_func$const_term_U239.out","affine_func$add_all__U247.in1"], + ["time_diff.in0","affine_func$add_all__U247.out"], + ["affine_func$mul_d0__U224.in0","affine_func$coeff_0_U223.out"], + ["affine_func$mul_d1__U226.in0","affine_func$coeff_1_U225.out"], + ["affine_func$mul_d2__U228.in0","affine_func$coeff_2_U227.out"], + ["affine_func$mul_d3__U230.in0","affine_func$coeff_3_U229.out"], + ["affine_func$mul_d4__U232.in0","affine_func$coeff_4_U231.out"], + ["affine_func$mul_d5__U234.in0","affine_func$coeff_5_U233.out"], + ["affine_func$mul_d6__U236.in0","affine_func$coeff_6_U235.out"], + ["affine_func$mul_d7__U238.in0","affine_func$coeff_7_U237.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U224.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U226.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U228.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U230.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U232.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U234.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U236.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U238.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["d_7_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U266$lut$lut.bit.in.2","d_0_am__U266$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U266$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U266$lut$lut.bit.in.1"], - ["d_0_am__U267$lut$lut.bit.in.0","d_0_am__U266$lut$lut.bit.out"], - ["d_0_am__U267$lut$lut.bit.in.2","d_0_am__U267$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U267$lut$lut.bit.in.1"], - ["d_0_am__U268$lut$lut.bit.in.0","d_0_am__U267$lut$lut.bit.out"], - ["d_0_am__U268$lut$lut.bit.in.2","d_0_am__U268$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U268$lut$lut.bit.in.1"], - ["d_0_am__U269$lut$lut.bit.in.0","d_0_am__U268$lut$lut.bit.out"], - ["d_0_am__U269$lut$lut.bit.in.2","d_0_am__U269$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U269$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U269$lut$lut.bit.out"], + ["d_0_am__U250$lut$lut.bit.in.2","d_0_am__U250$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U250$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U250$lut$lut.bit.in.1"], + ["d_0_am__U251$lut$lut.bit.in.0","d_0_am__U250$lut$lut.bit.out"], + ["d_0_am__U251$lut$lut.bit.in.2","d_0_am__U251$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U251$lut$lut.bit.in.1"], + ["d_0_am__U252$lut$lut.bit.in.0","d_0_am__U251$lut$lut.bit.out"], + ["d_0_am__U252$lut$lut.bit.in.2","d_0_am__U252$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U252$lut$lut.bit.in.1"], + ["d_0_am__U253$lut$lut.bit.in.0","d_0_am__U252$lut$lut.bit.out"], + ["d_0_am__U253$lut$lut.bit.in.2","d_0_am__U253$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U253$lut$lut.bit.in.1"], + ["d_0_am__U254$lut$lut.bit.in.0","d_0_am__U253$lut$lut.bit.out"], + ["d_0_am__U254$lut$lut.bit.in.2","d_0_am__U254$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U254$lut$lut.bit.in.1"], + ["d_0_am__U255$lut$lut.bit.in.0","d_0_am__U254$lut$lut.bit.out"], + ["d_0_am__U255$lut$lut.bit.in.2","d_0_am__U255$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U255$lut$lut.bit.in.1"], + ["d_0_am__U256$lut$lut.bit.in.0","d_0_am__U255$lut$lut.bit.out"], + ["d_0_am__U256$lut$lut.bit.in.2","d_0_am__U256$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U256$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U256$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2712,16 +3262,25 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U270$lut$lut.bit.in.2","d_1_am__U270$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U270$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U270$lut$lut.bit.in.1"], - ["d_1_am__U271$lut$lut.bit.in.0","d_1_am__U270$lut$lut.bit.out"], - ["d_1_am__U271$lut$lut.bit.in.2","d_1_am__U271$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U271$lut$lut.bit.in.1"], - ["d_1_am__U272$lut$lut.bit.in.0","d_1_am__U271$lut$lut.bit.out"], - ["d_1_am__U272$lut$lut.bit.in.2","d_1_am__U272$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U272$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U272$lut$lut.bit.out"], + ["d_1_am__U257$lut$lut.bit.in.2","d_1_am__U257$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U257$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U257$lut$lut.bit.in.1"], + ["d_1_am__U258$lut$lut.bit.in.0","d_1_am__U257$lut$lut.bit.out"], + ["d_1_am__U258$lut$lut.bit.in.2","d_1_am__U258$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U258$lut$lut.bit.in.1"], + ["d_1_am__U259$lut$lut.bit.in.0","d_1_am__U258$lut$lut.bit.out"], + ["d_1_am__U259$lut$lut.bit.in.2","d_1_am__U259$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U259$lut$lut.bit.in.1"], + ["d_1_am__U260$lut$lut.bit.in.0","d_1_am__U259$lut$lut.bit.out"], + ["d_1_am__U260$lut$lut.bit.in.2","d_1_am__U260$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U260$lut$lut.bit.in.1"], + ["d_1_am__U261$lut$lut.bit.in.0","d_1_am__U260$lut$lut.bit.out"], + ["d_1_am__U261$lut$lut.bit.in.2","d_1_am__U261$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U261$lut$lut.bit.in.1"], + ["d_1_am__U262$lut$lut.bit.in.0","d_1_am__U261$lut$lut.bit.out"], + ["d_1_am__U262$lut$lut.bit.in.2","d_1_am__U262$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U262$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U262$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2738,13 +3297,22 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U273$lut$lut.bit.in.2","d_2_am__U273$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U273$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U273$lut$lut.bit.in.1"], - ["d_2_am__U274$lut$lut.bit.in.0","d_2_am__U273$lut$lut.bit.out"], - ["d_2_am__U274$lut$lut.bit.in.2","d_2_am__U274$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U274$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U274$lut$lut.bit.out"], + ["d_2_am__U263$lut$lut.bit.in.2","d_2_am__U263$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U263$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U263$lut$lut.bit.in.1"], + ["d_2_am__U264$lut$lut.bit.in.0","d_2_am__U263$lut$lut.bit.out"], + ["d_2_am__U264$lut$lut.bit.in.2","d_2_am__U264$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U264$lut$lut.bit.in.1"], + ["d_2_am__U265$lut$lut.bit.in.0","d_2_am__U264$lut$lut.bit.out"], + ["d_2_am__U265$lut$lut.bit.in.2","d_2_am__U265$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U265$lut$lut.bit.in.1"], + ["d_2_am__U266$lut$lut.bit.in.0","d_2_am__U265$lut$lut.bit.out"], + ["d_2_am__U266$lut$lut.bit.in.2","d_2_am__U266$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U266$lut$lut.bit.in.1"], + ["d_2_am__U267$lut$lut.bit.in.0","d_2_am__U266$lut$lut.bit.out"], + ["d_2_am__U267$lut$lut.bit.in.2","d_2_am__U267$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U267$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U267$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2761,10 +3329,19 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U275$lut$lut.bit.in.2","d_3_am__U275$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U275$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U275$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U275$lut$lut.bit.out"], + ["d_3_am__U268$lut$lut.bit.in.2","d_3_am__U268$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U268$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U268$lut$lut.bit.in.1"], + ["d_3_am__U269$lut$lut.bit.in.0","d_3_am__U268$lut$lut.bit.out"], + ["d_3_am__U269$lut$lut.bit.in.2","d_3_am__U269$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U269$lut$lut.bit.in.1"], + ["d_3_am__U270$lut$lut.bit.in.0","d_3_am__U269$lut$lut.bit.out"], + ["d_3_am__U270$lut$lut.bit.in.2","d_3_am__U270$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U270$lut$lut.bit.in.1"], + ["d_3_am__U271$lut$lut.bit.in.0","d_3_am__U270$lut$lut.bit.out"], + ["d_3_am__U271$lut$lut.bit.in.2","d_3_am__U271$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U271$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U271$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2781,6 +3358,16 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U272$lut$lut.bit.in.2","d_4_am__U272$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U272$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U272$lut$lut.bit.in.1"], + ["d_4_am__U273$lut$lut.bit.in.0","d_4_am__U272$lut$lut.bit.out"], + ["d_4_am__U273$lut$lut.bit.in.2","d_4_am__U273$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U273$lut$lut.bit.in.1"], + ["d_4_am__U274$lut$lut.bit.in.0","d_4_am__U273$lut$lut.bit.out"], + ["d_4_am__U274$lut$lut.bit.in.2","d_4_am__U274$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U274$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U274$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2790,175 +3377,198 @@ ["d_4_reg$reg0.out","d_4_next_value.in0"], ["d_4_next_value_at_max.out","d_4_next_value.in1"], ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["true_lutcnst.bit.out","d_4_next_value.sel"], ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], ["self.rst_n","d_4_reg$clrMux.sel"], ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"] + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U275$lut$lut.bit.in.2","d_5_am__U275$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U275$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U275$lut$lut.bit.in.1"], + ["d_5_am__U276$lut$lut.bit.in.0","d_5_am__U275$lut$lut.bit.out"], + ["d_5_am__U276$lut$lut.bit.in.2","d_5_am__U276$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U276$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U276$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_am__U277$lut$lut.bit.in.2","d_6_am__U277$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U277$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U277$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U277$lut$lut.bit.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"], + ["d_7_reg$reg0.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg$reg0.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg$reg0.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg$enMux.in1","d_7_next_value.out"], + ["true_lutcnst.bit.out","d_7_next_value.sel"], + ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], + ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], + ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], + ["self.rst_n","d_7_reg$clrMux.sel"], + ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], + ["self.clk","d_7_reg$reg0.clk"], + ["self.d.7","d_7_reg$reg0.out"] ] }, - "affine_controller__U295":{ + "affine_controller__U315":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",8,["Array",32,"Bit"]]], + ["d",["Array",6,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U322":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3221":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3222":{ + "_U336":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3223":{ + "_U3361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3224":{ + "_U3362":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3225":{ + "_U3363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3226":{ + "_U3364":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3227":{ + "_U3365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U337":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U314":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U315":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U316":{ + "affine_func$add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U317":{ + "affine_func$add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U318":{ + "affine_func$add_all__U332":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U319":{ + "affine_func$add_all__U333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U320":{ + "affine_func$add_all__U334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U321":{ + "affine_func$add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U297":{ + "affine_func$coeff_0_U317":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U299":{ + "affine_func$coeff_1_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "affine_func$coeff_2_U301":{ + "affine_func$coeff_2_U321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000900"]} - }, - "affine_func$coeff_3_U303":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000300"]} - }, - "affine_func$coeff_4_U305":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "affine_func$coeff_5_U307":{ + "affine_func$coeff_3_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "affine_func$coeff_6_U309":{ + "affine_func$coeff_4_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_7_U311":{ + "affine_func$coeff_5_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U313":{ + "affine_func$const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000023ff"]} - }, - "affine_func$mul_d0__U298":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U300":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00003de0"]} }, - "affine_func$mul_d2__U302":{ + "affine_func$mul_d0__U318":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U304":{ + "affine_func$mul_d1__U320":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U306":{ + "affine_func$mul_d2__U322":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U308":{ + "affine_func$mul_d3__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U310":{ + "affine_func$mul_d4__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d7__U312":{ + "affine_func$mul_d5__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -3022,72 +3632,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U324$c0_lutcnst":{ + "d_0_am__U338$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U324$lut$lut":{ + "d_0_am__U338$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U325$c0_lutcnst":{ + "d_0_am__U339$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U325$lut$lut":{ + "d_0_am__U339$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U326$c0_lutcnst":{ + "d_0_am__U340$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U326$lut$lut":{ + "d_0_am__U340$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U327$c0_lutcnst":{ + "d_0_am__U341$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U327$lut$lut":{ + "d_0_am__U341$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U328$c0_lutcnst":{ + "d_0_am__U342$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U328$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U329$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U329$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U330$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U330$lut$lut":{ + "d_0_am__U342$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3136,62 +3726,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U331$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U331$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U332$c0_lutcnst":{ + "d_1_am__U343$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U332$lut$lut":{ + "d_1_am__U343$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U333$c0_lutcnst":{ + "d_1_am__U344$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U333$lut$lut":{ + "d_1_am__U344$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U334$c0_lutcnst":{ + "d_1_am__U345$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U334$lut$lut":{ + "d_1_am__U345$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U335$c0_lutcnst":{ + "d_1_am__U346$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U335$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U336$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U336$lut$lut":{ + "d_1_am__U346$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3240,52 +3810,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U337$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U337$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U338$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U338$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U339$c0_lutcnst":{ + "d_2_am__U347$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U339$lut$lut":{ + "d_2_am__U347$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U340$c0_lutcnst":{ + "d_2_am__U348$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U340$lut$lut":{ + "d_2_am__U348$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U341$c0_lutcnst":{ + "d_2_am__U349$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U341$lut$lut":{ + "d_2_am__U349$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3301,7 +3851,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_2_min":{ "genref":"coreir.const", @@ -3334,42 +3884,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U342$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U342$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U343$c0_lutcnst":{ + "d_3_am__U350$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U343$lut$lut":{ + "d_3_am__U350$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U344$c0_lutcnst":{ + "d_3_am__U351$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U344$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U345$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U345$lut$lut":{ + "d_3_am__U351$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3385,7 +3915,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_3_min":{ "genref":"coreir.const", @@ -3418,32 +3948,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U346$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U346$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U347$c0_lutcnst":{ + "d_4_am__U352$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U347$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U348$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U348$lut$lut":{ + "d_4_am__U352$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3459,7 +3969,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, "d_4_min":{ "genref":"coreir.const", @@ -3492,26 +4002,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U349$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U349$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U350$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U350$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -3523,7 +4013,7 @@ "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, "d_5_min":{ "genref":"coreir.const", @@ -3547,109 +4037,11 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_6_am__U351$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_6_am__U351$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_6_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_6_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_6_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_6_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_7_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_7_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_7_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_7_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$enMux":{ + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -3693,16 +4085,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -3710,48 +4092,38 @@ } }, "connections":[ - ["d_0_inc.in1","_U322.out"], - ["d_1_inc.in1","_U3221.out"], - ["d_2_inc.in1","_U3222.out"], - ["d_3_inc.in1","_U3223.out"], - ["d_4_inc.in1","_U3224.out"], - ["d_5_inc.in1","_U3225.out"], - ["d_6_inc.in1","_U3226.out"], - ["d_7_inc.in1","_U3227.out"], - ["cmp_time.in1","_U323.out"], - ["affine_func$mul_d0__U298.out","affine_func$add_all__U314.in0"], - ["affine_func$mul_d1__U300.out","affine_func$add_all__U314.in1"], - ["affine_func$add_all__U315.in0","affine_func$add_all__U314.out"], - ["affine_func$mul_d2__U302.out","affine_func$add_all__U315.in1"], - ["affine_func$add_all__U316.in0","affine_func$add_all__U315.out"], - ["affine_func$mul_d3__U304.out","affine_func$add_all__U316.in1"], - ["affine_func$add_all__U317.in0","affine_func$add_all__U316.out"], - ["affine_func$mul_d4__U306.out","affine_func$add_all__U317.in1"], - ["affine_func$add_all__U318.in0","affine_func$add_all__U317.out"], - ["affine_func$mul_d5__U308.out","affine_func$add_all__U318.in1"], - ["affine_func$add_all__U319.in0","affine_func$add_all__U318.out"], - ["affine_func$mul_d6__U310.out","affine_func$add_all__U319.in1"], - ["affine_func$add_all__U320.in0","affine_func$add_all__U319.out"], - ["affine_func$mul_d7__U312.out","affine_func$add_all__U320.in1"], - ["affine_func$add_all__U321.in0","affine_func$add_all__U320.out"], - ["affine_func$const_term_U313.out","affine_func$add_all__U321.in1"], - ["time_diff.in0","affine_func$add_all__U321.out"], - ["affine_func$mul_d0__U298.in0","affine_func$coeff_0_U297.out"], - ["affine_func$mul_d1__U300.in0","affine_func$coeff_1_U299.out"], - ["affine_func$mul_d2__U302.in0","affine_func$coeff_2_U301.out"], - ["affine_func$mul_d3__U304.in0","affine_func$coeff_3_U303.out"], - ["affine_func$mul_d4__U306.in0","affine_func$coeff_4_U305.out"], - ["affine_func$mul_d5__U308.in0","affine_func$coeff_5_U307.out"], - ["affine_func$mul_d6__U310.in0","affine_func$coeff_6_U309.out"], - ["affine_func$mul_d7__U312.in0","affine_func$coeff_7_U311.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U298.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U300.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U302.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U304.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U306.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U308.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U310.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U312.in1"], + ["d_0_inc.in1","_U336.out"], + ["d_1_inc.in1","_U3361.out"], + ["d_2_inc.in1","_U3362.out"], + ["d_3_inc.in1","_U3363.out"], + ["d_4_inc.in1","_U3364.out"], + ["d_5_inc.in1","_U3365.out"], + ["cmp_time.in1","_U337.out"], + ["affine_func$mul_d0__U318.out","affine_func$add_all__U330.in0"], + ["affine_func$mul_d1__U320.out","affine_func$add_all__U330.in1"], + ["affine_func$add_all__U331.in0","affine_func$add_all__U330.out"], + ["affine_func$mul_d2__U322.out","affine_func$add_all__U331.in1"], + ["affine_func$add_all__U332.in0","affine_func$add_all__U331.out"], + ["affine_func$mul_d3__U324.out","affine_func$add_all__U332.in1"], + ["affine_func$add_all__U333.in0","affine_func$add_all__U332.out"], + ["affine_func$mul_d4__U326.out","affine_func$add_all__U333.in1"], + ["affine_func$add_all__U334.in0","affine_func$add_all__U333.out"], + ["affine_func$mul_d5__U328.out","affine_func$add_all__U334.in1"], + ["affine_func$add_all__U335.in0","affine_func$add_all__U334.out"], + ["affine_func$const_term_U329.out","affine_func$add_all__U335.in1"], + ["time_diff.in0","affine_func$add_all__U335.out"], + ["affine_func$mul_d0__U318.in0","affine_func$coeff_0_U317.out"], + ["affine_func$mul_d1__U320.in0","affine_func$coeff_1_U319.out"], + ["affine_func$mul_d2__U322.in0","affine_func$coeff_2_U321.out"], + ["affine_func$mul_d3__U324.in0","affine_func$coeff_3_U323.out"], + ["affine_func$mul_d4__U326.in0","affine_func$coeff_4_U325.out"], + ["affine_func$mul_d5__U328.in0","affine_func$coeff_5_U327.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U318.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U320.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U322.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U324.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U326.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U328.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -3759,8 +4131,6 @@ ["d_3_reg$enMux.sel","cmp_time.out"], ["d_4_reg$enMux.sel","cmp_time.out"], ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], - ["d_7_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -3768,40 +4138,34 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U324$lut$lut.bit.in.2","d_0_am__U324$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U324$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U324$lut$lut.bit.in.1"], - ["d_0_am__U325$lut$lut.bit.in.0","d_0_am__U324$lut$lut.bit.out"], - ["d_0_am__U325$lut$lut.bit.in.2","d_0_am__U325$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U325$lut$lut.bit.in.1"], - ["d_0_am__U326$lut$lut.bit.in.0","d_0_am__U325$lut$lut.bit.out"], - ["d_0_am__U326$lut$lut.bit.in.2","d_0_am__U326$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U326$lut$lut.bit.in.1"], - ["d_0_am__U327$lut$lut.bit.in.0","d_0_am__U326$lut$lut.bit.out"], - ["d_0_am__U327$lut$lut.bit.in.2","d_0_am__U327$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U327$lut$lut.bit.in.1"], - ["d_0_am__U328$lut$lut.bit.in.0","d_0_am__U327$lut$lut.bit.out"], - ["d_0_am__U328$lut$lut.bit.in.2","d_0_am__U328$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U328$lut$lut.bit.in.1"], - ["d_0_am__U329$lut$lut.bit.in.0","d_0_am__U328$lut$lut.bit.out"], - ["d_0_am__U329$lut$lut.bit.in.2","d_0_am__U329$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U329$lut$lut.bit.in.1"], - ["d_0_am__U330$lut$lut.bit.in.0","d_0_am__U329$lut$lut.bit.out"], - ["d_0_am__U330$lut$lut.bit.in.2","d_0_am__U330$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U330$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U330$lut$lut.bit.out"], + ["d_0_am__U338$lut$lut.bit.in.2","d_0_am__U338$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U338$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U338$lut$lut.bit.in.1"], + ["d_0_am__U339$lut$lut.bit.in.0","d_0_am__U338$lut$lut.bit.out"], + ["d_0_am__U339$lut$lut.bit.in.2","d_0_am__U339$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U339$lut$lut.bit.in.1"], + ["d_0_am__U340$lut$lut.bit.in.0","d_0_am__U339$lut$lut.bit.out"], + ["d_0_am__U340$lut$lut.bit.in.2","d_0_am__U340$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U340$lut$lut.bit.in.1"], + ["d_0_am__U341$lut$lut.bit.in.0","d_0_am__U340$lut$lut.bit.out"], + ["d_0_am__U341$lut$lut.bit.in.2","d_0_am__U341$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U341$lut$lut.bit.in.1"], + ["d_0_am__U342$lut$lut.bit.in.0","d_0_am__U341$lut$lut.bit.out"], + ["d_0_am__U342$lut$lut.bit.in.2","d_0_am__U342$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U342$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U342$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3818,25 +4182,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U331$lut$lut.bit.in.2","d_1_am__U331$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U331$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U331$lut$lut.bit.in.1"], - ["d_1_am__U332$lut$lut.bit.in.0","d_1_am__U331$lut$lut.bit.out"], - ["d_1_am__U332$lut$lut.bit.in.2","d_1_am__U332$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U332$lut$lut.bit.in.1"], - ["d_1_am__U333$lut$lut.bit.in.0","d_1_am__U332$lut$lut.bit.out"], - ["d_1_am__U333$lut$lut.bit.in.2","d_1_am__U333$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U333$lut$lut.bit.in.1"], - ["d_1_am__U334$lut$lut.bit.in.0","d_1_am__U333$lut$lut.bit.out"], - ["d_1_am__U334$lut$lut.bit.in.2","d_1_am__U334$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U334$lut$lut.bit.in.1"], - ["d_1_am__U335$lut$lut.bit.in.0","d_1_am__U334$lut$lut.bit.out"], - ["d_1_am__U335$lut$lut.bit.in.2","d_1_am__U335$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U335$lut$lut.bit.in.1"], - ["d_1_am__U336$lut$lut.bit.in.0","d_1_am__U335$lut$lut.bit.out"], - ["d_1_am__U336$lut$lut.bit.in.2","d_1_am__U336$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U336$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U336$lut$lut.bit.out"], + ["d_1_am__U343$lut$lut.bit.in.2","d_1_am__U343$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U343$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U343$lut$lut.bit.in.1"], + ["d_1_am__U344$lut$lut.bit.in.0","d_1_am__U343$lut$lut.bit.out"], + ["d_1_am__U344$lut$lut.bit.in.2","d_1_am__U344$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U344$lut$lut.bit.in.1"], + ["d_1_am__U345$lut$lut.bit.in.0","d_1_am__U344$lut$lut.bit.out"], + ["d_1_am__U345$lut$lut.bit.in.2","d_1_am__U345$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U345$lut$lut.bit.in.1"], + ["d_1_am__U346$lut$lut.bit.in.0","d_1_am__U345$lut$lut.bit.out"], + ["d_1_am__U346$lut$lut.bit.in.2","d_1_am__U346$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U346$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U346$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3853,22 +4211,16 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U337$lut$lut.bit.in.2","d_2_am__U337$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U337$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U337$lut$lut.bit.in.1"], - ["d_2_am__U338$lut$lut.bit.in.0","d_2_am__U337$lut$lut.bit.out"], - ["d_2_am__U338$lut$lut.bit.in.2","d_2_am__U338$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U338$lut$lut.bit.in.1"], - ["d_2_am__U339$lut$lut.bit.in.0","d_2_am__U338$lut$lut.bit.out"], - ["d_2_am__U339$lut$lut.bit.in.2","d_2_am__U339$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U339$lut$lut.bit.in.1"], - ["d_2_am__U340$lut$lut.bit.in.0","d_2_am__U339$lut$lut.bit.out"], - ["d_2_am__U340$lut$lut.bit.in.2","d_2_am__U340$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U340$lut$lut.bit.in.1"], - ["d_2_am__U341$lut$lut.bit.in.0","d_2_am__U340$lut$lut.bit.out"], - ["d_2_am__U341$lut$lut.bit.in.2","d_2_am__U341$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U341$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U341$lut$lut.bit.out"], + ["d_2_am__U347$lut$lut.bit.in.2","d_2_am__U347$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U347$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U347$lut$lut.bit.in.1"], + ["d_2_am__U348$lut$lut.bit.in.0","d_2_am__U347$lut$lut.bit.out"], + ["d_2_am__U348$lut$lut.bit.in.2","d_2_am__U348$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U348$lut$lut.bit.in.1"], + ["d_2_am__U349$lut$lut.bit.in.0","d_2_am__U348$lut$lut.bit.out"], + ["d_2_am__U349$lut$lut.bit.in.2","d_2_am__U349$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U349$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U349$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3885,19 +4237,13 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U342$lut$lut.bit.in.2","d_3_am__U342$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U342$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U342$lut$lut.bit.in.1"], - ["d_3_am__U343$lut$lut.bit.in.0","d_3_am__U342$lut$lut.bit.out"], - ["d_3_am__U343$lut$lut.bit.in.2","d_3_am__U343$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U343$lut$lut.bit.in.1"], - ["d_3_am__U344$lut$lut.bit.in.0","d_3_am__U343$lut$lut.bit.out"], - ["d_3_am__U344$lut$lut.bit.in.2","d_3_am__U344$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U344$lut$lut.bit.in.1"], - ["d_3_am__U345$lut$lut.bit.in.0","d_3_am__U344$lut$lut.bit.out"], - ["d_3_am__U345$lut$lut.bit.in.2","d_3_am__U345$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U345$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U345$lut$lut.bit.out"], + ["d_3_am__U350$lut$lut.bit.in.2","d_3_am__U350$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U350$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U350$lut$lut.bit.in.1"], + ["d_3_am__U351$lut$lut.bit.in.0","d_3_am__U350$lut$lut.bit.out"], + ["d_3_am__U351$lut$lut.bit.in.2","d_3_am__U351$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U351$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U351$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3914,16 +4260,10 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U346$lut$lut.bit.in.2","d_4_am__U346$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U346$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U346$lut$lut.bit.in.1"], - ["d_4_am__U347$lut$lut.bit.in.0","d_4_am__U346$lut$lut.bit.out"], - ["d_4_am__U347$lut$lut.bit.in.2","d_4_am__U347$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U347$lut$lut.bit.in.1"], - ["d_4_am__U348$lut$lut.bit.in.0","d_4_am__U347$lut$lut.bit.out"], - ["d_4_am__U348$lut$lut.bit.in.2","d_4_am__U348$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U348$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U348$lut$lut.bit.out"], + ["d_4_am__U352$lut$lut.bit.in.2","d_4_am__U352$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U352$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U352$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U352$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3940,13 +4280,6 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U349$lut$lut.bit.in.2","d_5_am__U349$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U349$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U349$lut$lut.bit.in.1"], - ["d_5_am__U350$lut$lut.bit.in.0","d_5_am__U349$lut$lut.bit.out"], - ["d_5_am__U350$lut$lut.bit.in.2","d_5_am__U350$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U350$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U350$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -3956,175 +4289,103 @@ ["d_5_reg$reg0.out","d_5_next_value.in0"], ["d_5_next_value_at_max.out","d_5_next_value.in1"], ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["true_lutcnst.bit.out","d_5_next_value.sel"], ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], ["self.rst_n","d_5_reg$clrMux.sel"], ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U351$lut$lut.bit.in.2","d_6_am__U351$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U351$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U351$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U351$lut$lut.bit.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"], - ["d_7_reg$reg0.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg$reg0.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg$reg0.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg$enMux.in1","d_7_next_value.out"], - ["true_lutcnst.bit.out","d_7_next_value.sel"], - ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], - ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], - ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], - ["self.rst_n","d_7_reg$clrMux.sel"], - ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], - ["self.clk","d_7_reg$reg0.clk"], - ["self.d.7","d_7_reg$reg0.out"] + ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U398":{ + "affine_controller__U375":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",6,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U419":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4191":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4192":{ + "_U390":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4193":{ + "_U3901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4194":{ + "_U3902":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4195":{ + "_U3903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U420":{ + "_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U413":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U414":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U415":{ + "affine_func$add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U416":{ + "affine_func$add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U417":{ + "affine_func$add_all__U388":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U418":{ + "affine_func$add_all__U389":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U400":{ + "affine_func$coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U402":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001200"]} - }, - "affine_func$coeff_2_U404":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000000e0"]} - }, - "affine_func$coeff_3_U406":{ + "affine_func$coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000020"]} + "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "affine_func$coeff_4_U408":{ + "affine_func$coeff_2_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "affine_func$coeff_5_U410":{ + "affine_func$coeff_3_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U412":{ + "affine_func$const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003de0"]} - }, - "affine_func$mul_d0__U401":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U403":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h000055ff"]} }, - "affine_func$mul_d2__U405":{ + "affine_func$mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U407":{ + "affine_func$mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U409":{ + "affine_func$mul_d2__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U411":{ + "affine_func$mul_d3__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4188,52 +4449,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U421$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U421$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U422$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U422$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U423$c0_lutcnst":{ + "d_0_am__U392$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U423$lut$lut":{ + "d_0_am__U392$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U424$c0_lutcnst":{ + "d_0_am__U393$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U424$lut$lut":{ + "d_0_am__U393$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U425$c0_lutcnst":{ + "d_0_am__U394$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U425$lut$lut":{ + "d_0_am__U394$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4282,42 +4523,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U426$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U426$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U427$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U427$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U428$c0_lutcnst":{ + "d_1_am__U395$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U428$lut$lut":{ + "d_1_am__U395$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U429$c0_lutcnst":{ + "d_1_am__U396$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U429$lut$lut":{ + "d_1_am__U396$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4333,7 +4554,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_1_min":{ "genref":"coreir.const", @@ -4366,32 +4587,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U430$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U430$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U431$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U431$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U432$c0_lutcnst":{ + "d_2_am__U397$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U432$lut$lut":{ + "d_2_am__U397$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4440,26 +4641,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U433$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U433$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U434$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U434$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -4471,7 +4652,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -4499,105 +4680,7 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_am__U435$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U435$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_5_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_5_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_5_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_5_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -4631,16 +4714,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4648,45 +4721,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U419.out"], - ["d_1_inc.in1","_U4191.out"], - ["d_2_inc.in1","_U4192.out"], - ["d_3_inc.in1","_U4193.out"], - ["d_4_inc.in1","_U4194.out"], - ["d_5_inc.in1","_U4195.out"], - ["cmp_time.in1","_U420.out"], - ["affine_func$mul_d0__U401.out","affine_func$add_all__U413.in0"], - ["affine_func$mul_d1__U403.out","affine_func$add_all__U413.in1"], - ["affine_func$add_all__U414.in0","affine_func$add_all__U413.out"], - ["affine_func$mul_d2__U405.out","affine_func$add_all__U414.in1"], - ["affine_func$add_all__U415.in0","affine_func$add_all__U414.out"], - ["affine_func$mul_d3__U407.out","affine_func$add_all__U415.in1"], - ["affine_func$add_all__U416.in0","affine_func$add_all__U415.out"], - ["affine_func$mul_d4__U409.out","affine_func$add_all__U416.in1"], - ["affine_func$add_all__U417.in0","affine_func$add_all__U416.out"], - ["affine_func$mul_d5__U411.out","affine_func$add_all__U417.in1"], - ["affine_func$add_all__U418.in0","affine_func$add_all__U417.out"], - ["affine_func$const_term_U412.out","affine_func$add_all__U418.in1"], - ["time_diff.in0","affine_func$add_all__U418.out"], - ["affine_func$mul_d0__U401.in0","affine_func$coeff_0_U400.out"], - ["affine_func$mul_d1__U403.in0","affine_func$coeff_1_U402.out"], - ["affine_func$mul_d2__U405.in0","affine_func$coeff_2_U404.out"], - ["affine_func$mul_d3__U407.in0","affine_func$coeff_3_U406.out"], - ["affine_func$mul_d4__U409.in0","affine_func$coeff_4_U408.out"], - ["affine_func$mul_d5__U411.in0","affine_func$coeff_5_U410.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U401.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U403.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U405.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U407.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U409.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U411.in1"], + ["d_0_inc.in1","_U390.out"], + ["d_1_inc.in1","_U3901.out"], + ["d_2_inc.in1","_U3902.out"], + ["d_3_inc.in1","_U3903.out"], + ["cmp_time.in1","_U391.out"], + ["affine_func$mul_d0__U378.out","affine_func$add_all__U386.in0"], + ["affine_func$mul_d1__U380.out","affine_func$add_all__U386.in1"], + ["affine_func$add_all__U387.in0","affine_func$add_all__U386.out"], + ["affine_func$mul_d2__U382.out","affine_func$add_all__U387.in1"], + ["affine_func$add_all__U388.in0","affine_func$add_all__U387.out"], + ["affine_func$mul_d3__U384.out","affine_func$add_all__U388.in1"], + ["affine_func$add_all__U389.in0","affine_func$add_all__U388.out"], + ["affine_func$const_term_U385.out","affine_func$add_all__U389.in1"], + ["time_diff.in0","affine_func$add_all__U389.out"], + ["affine_func$mul_d0__U378.in0","affine_func$coeff_0_U377.out"], + ["affine_func$mul_d1__U380.in0","affine_func$coeff_1_U379.out"], + ["affine_func$mul_d2__U382.in0","affine_func$coeff_2_U381.out"], + ["affine_func$mul_d3__U384.in0","affine_func$coeff_3_U383.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U378.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U380.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U382.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U384.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -4694,34 +4755,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U421$lut$lut.bit.in.2","d_0_am__U421$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U421$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U421$lut$lut.bit.in.1"], - ["d_0_am__U422$lut$lut.bit.in.0","d_0_am__U421$lut$lut.bit.out"], - ["d_0_am__U422$lut$lut.bit.in.2","d_0_am__U422$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U422$lut$lut.bit.in.1"], - ["d_0_am__U423$lut$lut.bit.in.0","d_0_am__U422$lut$lut.bit.out"], - ["d_0_am__U423$lut$lut.bit.in.2","d_0_am__U423$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U423$lut$lut.bit.in.1"], - ["d_0_am__U424$lut$lut.bit.in.0","d_0_am__U423$lut$lut.bit.out"], - ["d_0_am__U424$lut$lut.bit.in.2","d_0_am__U424$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U424$lut$lut.bit.in.1"], - ["d_0_am__U425$lut$lut.bit.in.0","d_0_am__U424$lut$lut.bit.out"], - ["d_0_am__U425$lut$lut.bit.in.2","d_0_am__U425$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U425$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U425$lut$lut.bit.out"], + ["d_0_am__U392$lut$lut.bit.in.2","d_0_am__U392$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U392$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U392$lut$lut.bit.in.1"], + ["d_0_am__U393$lut$lut.bit.in.0","d_0_am__U392$lut$lut.bit.out"], + ["d_0_am__U393$lut$lut.bit.in.2","d_0_am__U393$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U393$lut$lut.bit.in.1"], + ["d_0_am__U394$lut$lut.bit.in.0","d_0_am__U393$lut$lut.bit.out"], + ["d_0_am__U394$lut$lut.bit.in.2","d_0_am__U394$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U394$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U394$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4738,19 +4793,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U426$lut$lut.bit.in.2","d_1_am__U426$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U426$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U426$lut$lut.bit.in.1"], - ["d_1_am__U427$lut$lut.bit.in.0","d_1_am__U426$lut$lut.bit.out"], - ["d_1_am__U427$lut$lut.bit.in.2","d_1_am__U427$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U427$lut$lut.bit.in.1"], - ["d_1_am__U428$lut$lut.bit.in.0","d_1_am__U427$lut$lut.bit.out"], - ["d_1_am__U428$lut$lut.bit.in.2","d_1_am__U428$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U428$lut$lut.bit.in.1"], - ["d_1_am__U429$lut$lut.bit.in.0","d_1_am__U428$lut$lut.bit.out"], - ["d_1_am__U429$lut$lut.bit.in.2","d_1_am__U429$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U429$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U429$lut$lut.bit.out"], + ["d_1_am__U395$lut$lut.bit.in.2","d_1_am__U395$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U395$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U395$lut$lut.bit.in.1"], + ["d_1_am__U396$lut$lut.bit.in.0","d_1_am__U395$lut$lut.bit.out"], + ["d_1_am__U396$lut$lut.bit.in.2","d_1_am__U396$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U396$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U396$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4767,16 +4816,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U430$lut$lut.bit.in.2","d_2_am__U430$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U430$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U430$lut$lut.bit.in.1"], - ["d_2_am__U431$lut$lut.bit.in.0","d_2_am__U430$lut$lut.bit.out"], - ["d_2_am__U431$lut$lut.bit.in.2","d_2_am__U431$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U431$lut$lut.bit.in.1"], - ["d_2_am__U432$lut$lut.bit.in.0","d_2_am__U431$lut$lut.bit.out"], - ["d_2_am__U432$lut$lut.bit.in.2","d_2_am__U432$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U432$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U432$lut$lut.bit.out"], + ["d_2_am__U397$lut$lut.bit.in.2","d_2_am__U397$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U397$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U397$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U397$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4793,13 +4836,6 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U433$lut$lut.bit.in.2","d_3_am__U433$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U433$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U433$lut$lut.bit.in.1"], - ["d_3_am__U434$lut$lut.bit.in.0","d_3_am__U433$lut$lut.bit.out"], - ["d_3_am__U434$lut$lut.bit.in.2","d_3_am__U434$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U434$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U434$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4809,139 +4845,139 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U435$lut$lut.bit.in.2","d_4_am__U435$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U435$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U435$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U435$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["true_lutcnst.bit.out","d_5_next_value.sel"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U458":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",6,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U473":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4731":{ + "_U681":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4732":{ + "_U682":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4733":{ + "_U683":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U474":{ + "_U684":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U685":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U69":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U469":{ + "affine_func$add_all__U62":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U470":{ + "affine_func$add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U471":{ + "affine_func$add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U472":{ + "affine_func$add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U460":{ + "affine_func$add_all__U67":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U462":{ + "affine_func$coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000001c0"]} + "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "affine_func$coeff_2_U464":{ + "affine_func$coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000900"]} + }, + "affine_func$coeff_3_U55":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "affine_func$coeff_4_U57":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_3_U466":{ + "affine_func$coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U468":{ + "affine_func$const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000055ff"]} + "modargs":{"value":[["BitVector",32],"32'h000023ff"]} + }, + "affine_func$mul_d0__U50":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U461":{ + "affine_func$mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U463":{ + "affine_func$mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U465":{ + "affine_func$mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U467":{ + "affine_func$mul_d4__U58":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5005,32 +5041,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U475$c0_lutcnst":{ + "d_0_am__U70$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U70$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U71$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U71$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U72$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U475$lut$lut":{ + "d_0_am__U72$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U476$c0_lutcnst":{ + "d_0_am__U73$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U476$lut$lut":{ + "d_0_am__U73$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U477$c0_lutcnst":{ + "d_0_am__U74$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U477$lut$lut":{ + "d_0_am__U74$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5079,22 +5135,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U478$c0_lutcnst":{ + "d_1_am__U75$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U75$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U76$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U76$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U77$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U478$lut$lut":{ + "d_1_am__U77$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U479$c0_lutcnst":{ + "d_1_am__U78$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U479$lut$lut":{ + "d_1_am__U78$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5110,7 +5186,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -5143,12 +5219,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U480$c0_lutcnst":{ + "d_2_am__U79$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U79$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U80$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U80$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U81$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U480$lut$lut":{ + "d_2_am__U81$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5164,7 +5260,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -5197,6 +5293,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U82$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U82$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U83$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U83$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -5208,7 +5324,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -5232,11 +5348,109 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$enMux":{ + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U84$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U84$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -5270,6 +5484,16 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -5277,33 +5501,45 @@ } }, "connections":[ - ["d_0_inc.in1","_U473.out"], - ["d_1_inc.in1","_U4731.out"], - ["d_2_inc.in1","_U4732.out"], - ["d_3_inc.in1","_U4733.out"], - ["cmp_time.in1","_U474.out"], - ["affine_func$mul_d0__U461.out","affine_func$add_all__U469.in0"], - ["affine_func$mul_d1__U463.out","affine_func$add_all__U469.in1"], - ["affine_func$add_all__U470.in0","affine_func$add_all__U469.out"], - ["affine_func$mul_d2__U465.out","affine_func$add_all__U470.in1"], - ["affine_func$add_all__U471.in0","affine_func$add_all__U470.out"], - ["affine_func$mul_d3__U467.out","affine_func$add_all__U471.in1"], - ["affine_func$add_all__U472.in0","affine_func$add_all__U471.out"], - ["affine_func$const_term_U468.out","affine_func$add_all__U472.in1"], - ["time_diff.in0","affine_func$add_all__U472.out"], - ["affine_func$mul_d0__U461.in0","affine_func$coeff_0_U460.out"], - ["affine_func$mul_d1__U463.in0","affine_func$coeff_1_U462.out"], - ["affine_func$mul_d2__U465.in0","affine_func$coeff_2_U464.out"], - ["affine_func$mul_d3__U467.in0","affine_func$coeff_3_U466.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U461.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U463.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U465.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U467.in1"], + ["d_0_inc.in1","_U68.out"], + ["d_1_inc.in1","_U681.out"], + ["d_2_inc.in1","_U682.out"], + ["d_3_inc.in1","_U683.out"], + ["d_4_inc.in1","_U684.out"], + ["d_5_inc.in1","_U685.out"], + ["cmp_time.in1","_U69.out"], + ["affine_func$mul_d0__U50.out","affine_func$add_all__U62.in0"], + ["affine_func$mul_d1__U52.out","affine_func$add_all__U62.in1"], + ["affine_func$add_all__U63.in0","affine_func$add_all__U62.out"], + ["affine_func$mul_d2__U54.out","affine_func$add_all__U63.in1"], + ["affine_func$add_all__U64.in0","affine_func$add_all__U63.out"], + ["affine_func$mul_d3__U56.out","affine_func$add_all__U64.in1"], + ["affine_func$add_all__U65.in0","affine_func$add_all__U64.out"], + ["affine_func$mul_d4__U58.out","affine_func$add_all__U65.in1"], + ["affine_func$add_all__U66.in0","affine_func$add_all__U65.out"], + ["affine_func$mul_d5__U60.out","affine_func$add_all__U66.in1"], + ["affine_func$add_all__U67.in0","affine_func$add_all__U66.out"], + ["affine_func$const_term_U61.out","affine_func$add_all__U67.in1"], + ["time_diff.in0","affine_func$add_all__U67.out"], + ["affine_func$mul_d0__U50.in0","affine_func$coeff_0_U49.out"], + ["affine_func$mul_d1__U52.in0","affine_func$coeff_1_U51.out"], + ["affine_func$mul_d2__U54.in0","affine_func$coeff_2_U53.out"], + ["affine_func$mul_d3__U56.in0","affine_func$coeff_3_U55.out"], + ["affine_func$mul_d4__U58.in0","affine_func$coeff_4_U57.out"], + ["affine_func$mul_d5__U60.in0","affine_func$coeff_5_U59.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U50.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U52.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U54.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U56.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U58.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U60.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -5311,28 +5547,34 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U475$lut$lut.bit.in.2","d_0_am__U475$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U475$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U475$lut$lut.bit.in.1"], - ["d_0_am__U476$lut$lut.bit.in.0","d_0_am__U475$lut$lut.bit.out"], - ["d_0_am__U476$lut$lut.bit.in.2","d_0_am__U476$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U476$lut$lut.bit.in.1"], - ["d_0_am__U477$lut$lut.bit.in.0","d_0_am__U476$lut$lut.bit.out"], - ["d_0_am__U477$lut$lut.bit.in.2","d_0_am__U477$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U477$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U477$lut$lut.bit.out"], + ["d_0_am__U70$lut$lut.bit.in.2","d_0_am__U70$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U70$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U70$lut$lut.bit.in.1"], + ["d_0_am__U71$lut$lut.bit.in.0","d_0_am__U70$lut$lut.bit.out"], + ["d_0_am__U71$lut$lut.bit.in.2","d_0_am__U71$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U71$lut$lut.bit.in.1"], + ["d_0_am__U72$lut$lut.bit.in.0","d_0_am__U71$lut$lut.bit.out"], + ["d_0_am__U72$lut$lut.bit.in.2","d_0_am__U72$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U72$lut$lut.bit.in.1"], + ["d_0_am__U73$lut$lut.bit.in.0","d_0_am__U72$lut$lut.bit.out"], + ["d_0_am__U73$lut$lut.bit.in.2","d_0_am__U73$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U73$lut$lut.bit.in.1"], + ["d_0_am__U74$lut$lut.bit.in.0","d_0_am__U73$lut$lut.bit.out"], + ["d_0_am__U74$lut$lut.bit.in.2","d_0_am__U74$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U74$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U74$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5349,13 +5591,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U478$lut$lut.bit.in.2","d_1_am__U478$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U478$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U478$lut$lut.bit.in.1"], - ["d_1_am__U479$lut$lut.bit.in.0","d_1_am__U478$lut$lut.bit.out"], - ["d_1_am__U479$lut$lut.bit.in.2","d_1_am__U479$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U479$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U479$lut$lut.bit.out"], + ["d_1_am__U75$lut$lut.bit.in.2","d_1_am__U75$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U75$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U75$lut$lut.bit.in.1"], + ["d_1_am__U76$lut$lut.bit.in.0","d_1_am__U75$lut$lut.bit.out"], + ["d_1_am__U76$lut$lut.bit.in.2","d_1_am__U76$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U76$lut$lut.bit.in.1"], + ["d_1_am__U77$lut$lut.bit.in.0","d_1_am__U76$lut$lut.bit.out"], + ["d_1_am__U77$lut$lut.bit.in.2","d_1_am__U77$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U77$lut$lut.bit.in.1"], + ["d_1_am__U78$lut$lut.bit.in.0","d_1_am__U77$lut$lut.bit.out"], + ["d_1_am__U78$lut$lut.bit.in.2","d_1_am__U78$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U78$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U78$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5372,10 +5620,16 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U480$lut$lut.bit.in.2","d_2_am__U480$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U480$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U480$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U480$lut$lut.bit.out"], + ["d_2_am__U79$lut$lut.bit.in.2","d_2_am__U79$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U79$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U79$lut$lut.bit.in.1"], + ["d_2_am__U80$lut$lut.bit.in.0","d_2_am__U79$lut$lut.bit.out"], + ["d_2_am__U80$lut$lut.bit.in.2","d_2_am__U80$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U80$lut$lut.bit.in.1"], + ["d_2_am__U81$lut$lut.bit.in.0","d_2_am__U80$lut$lut.bit.out"], + ["d_2_am__U81$lut$lut.bit.in.2","d_2_am__U81$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U81$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U81$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5392,6 +5646,13 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U82$lut$lut.bit.in.2","d_3_am__U82$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U82$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U82$lut$lut.bit.in.1"], + ["d_3_am__U83$lut$lut.bit.in.0","d_3_am__U82$lut$lut.bit.out"], + ["d_3_am__U83$lut$lut.bit.in.2","d_3_am__U83$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U83$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U83$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5401,139 +5662,139 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U84$lut$lut.bit.in.2","d_4_am__U84$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U84$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U84$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U84$lut$lut.bit.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["true_lutcnst.bit.out","d_5_next_value.sel"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",6,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U77":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U771":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U772":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U773":{ + "_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U774":{ + "_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U775":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U78":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U71":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U72":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U73":{ + "affine_func$add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U74":{ + "affine_func$add_all__U20":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U75":{ + "affine_func$add_all__U21":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U76":{ + "affine_func$add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U58":{ + "affine_func$coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U60":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001200"]} - }, - "affine_func$coeff_2_U62":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000900"]} - }, - "affine_func$coeff_3_U64":{ + "affine_func$coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "affine_func$coeff_4_U66":{ + "affine_func$coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_5_U68":{ + "affine_func$coeff_3_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U70":{ + "affine_func$const_term_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000023ff"]} - }, - "affine_func$mul_d0__U59":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U61":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d2__U63":{ + "affine_func$mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U65":{ + "affine_func$mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U67":{ + "affine_func$mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U69":{ + "affine_func$mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5597,52 +5858,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U79$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U79$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U80$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U80$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U81$c0_lutcnst":{ + "d_0_am__U25$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U81$lut$lut":{ + "d_0_am__U25$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U82$c0_lutcnst":{ + "d_0_am__U26$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U82$lut$lut":{ + "d_0_am__U26$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U83$c0_lutcnst":{ + "d_0_am__U27$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U83$lut$lut":{ + "d_0_am__U27$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5691,42 +5932,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U84$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U84$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U85$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U85$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U86$c0_lutcnst":{ + "d_1_am__U28$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U86$lut$lut":{ + "d_1_am__U28$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U87$c0_lutcnst":{ + "d_1_am__U29$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U87$lut$lut":{ + "d_1_am__U29$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5742,7 +5963,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -5770,243 +5991,105 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U88$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U88$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U89$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U89$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U90$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U90$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U91$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U91$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U92$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U92$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U93$c0_lutcnst":{ + "d_2_am__U30$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U93$lut$lut":{ + "d_2_am__U30$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, - "d_4_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, - "d_5_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -6040,16 +6123,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6057,45 +6130,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U77.out"], - ["d_1_inc.in1","_U771.out"], - ["d_2_inc.in1","_U772.out"], - ["d_3_inc.in1","_U773.out"], - ["d_4_inc.in1","_U774.out"], - ["d_5_inc.in1","_U775.out"], - ["cmp_time.in1","_U78.out"], - ["affine_func$mul_d0__U59.out","affine_func$add_all__U71.in0"], - ["affine_func$mul_d1__U61.out","affine_func$add_all__U71.in1"], - ["affine_func$add_all__U72.in0","affine_func$add_all__U71.out"], - ["affine_func$mul_d2__U63.out","affine_func$add_all__U72.in1"], - ["affine_func$add_all__U73.in0","affine_func$add_all__U72.out"], - ["affine_func$mul_d3__U65.out","affine_func$add_all__U73.in1"], - ["affine_func$add_all__U74.in0","affine_func$add_all__U73.out"], - ["affine_func$mul_d4__U67.out","affine_func$add_all__U74.in1"], - ["affine_func$add_all__U75.in0","affine_func$add_all__U74.out"], - ["affine_func$mul_d5__U69.out","affine_func$add_all__U75.in1"], - ["affine_func$add_all__U76.in0","affine_func$add_all__U75.out"], - ["affine_func$const_term_U70.out","affine_func$add_all__U76.in1"], - ["time_diff.in0","affine_func$add_all__U76.out"], - ["affine_func$mul_d0__U59.in0","affine_func$coeff_0_U58.out"], - ["affine_func$mul_d1__U61.in0","affine_func$coeff_1_U60.out"], - ["affine_func$mul_d2__U63.in0","affine_func$coeff_2_U62.out"], - ["affine_func$mul_d3__U65.in0","affine_func$coeff_3_U64.out"], - ["affine_func$mul_d4__U67.in0","affine_func$coeff_4_U66.out"], - ["affine_func$mul_d5__U69.in0","affine_func$coeff_5_U68.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U59.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U61.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U63.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U65.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U67.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U69.in1"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U231.out"], + ["d_2_inc.in1","_U232.out"], + ["d_3_inc.in1","_U233.out"], + ["cmp_time.in1","_U24.out"], + ["affine_func$mul_d0__U11.out","affine_func$add_all__U19.in0"], + ["affine_func$mul_d1__U13.out","affine_func$add_all__U19.in1"], + ["affine_func$add_all__U20.in0","affine_func$add_all__U19.out"], + ["affine_func$mul_d2__U15.out","affine_func$add_all__U20.in1"], + ["affine_func$add_all__U21.in0","affine_func$add_all__U20.out"], + ["affine_func$mul_d3__U17.out","affine_func$add_all__U21.in1"], + ["affine_func$add_all__U22.in0","affine_func$add_all__U21.out"], + ["affine_func$const_term_U18.out","affine_func$add_all__U22.in1"], + ["time_diff.in0","affine_func$add_all__U22.out"], + ["affine_func$mul_d0__U11.in0","affine_func$coeff_0_U10.out"], + ["affine_func$mul_d1__U13.in0","affine_func$coeff_1_U12.out"], + ["affine_func$mul_d2__U15.in0","affine_func$coeff_2_U14.out"], + ["affine_func$mul_d3__U17.in0","affine_func$coeff_3_U16.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U11.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U13.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U15.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U17.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -6103,34 +6164,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U79$lut$lut.bit.in.2","d_0_am__U79$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U79$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U79$lut$lut.bit.in.1"], - ["d_0_am__U80$lut$lut.bit.in.0","d_0_am__U79$lut$lut.bit.out"], - ["d_0_am__U80$lut$lut.bit.in.2","d_0_am__U80$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U80$lut$lut.bit.in.1"], - ["d_0_am__U81$lut$lut.bit.in.0","d_0_am__U80$lut$lut.bit.out"], - ["d_0_am__U81$lut$lut.bit.in.2","d_0_am__U81$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U81$lut$lut.bit.in.1"], - ["d_0_am__U82$lut$lut.bit.in.0","d_0_am__U81$lut$lut.bit.out"], - ["d_0_am__U82$lut$lut.bit.in.2","d_0_am__U82$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U82$lut$lut.bit.in.1"], - ["d_0_am__U83$lut$lut.bit.in.0","d_0_am__U82$lut$lut.bit.out"], - ["d_0_am__U83$lut$lut.bit.in.2","d_0_am__U83$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U83$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U83$lut$lut.bit.out"], + ["d_0_am__U25$lut$lut.bit.in.2","d_0_am__U25$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U25$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U25$lut$lut.bit.in.1"], + ["d_0_am__U26$lut$lut.bit.in.0","d_0_am__U25$lut$lut.bit.out"], + ["d_0_am__U26$lut$lut.bit.in.2","d_0_am__U26$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U26$lut$lut.bit.in.1"], + ["d_0_am__U27$lut$lut.bit.in.0","d_0_am__U26$lut$lut.bit.out"], + ["d_0_am__U27$lut$lut.bit.in.2","d_0_am__U27$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U27$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U27$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6147,19 +6202,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U84$lut$lut.bit.in.2","d_1_am__U84$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U84$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U84$lut$lut.bit.in.1"], - ["d_1_am__U85$lut$lut.bit.in.0","d_1_am__U84$lut$lut.bit.out"], - ["d_1_am__U85$lut$lut.bit.in.2","d_1_am__U85$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U85$lut$lut.bit.in.1"], - ["d_1_am__U86$lut$lut.bit.in.0","d_1_am__U85$lut$lut.bit.out"], - ["d_1_am__U86$lut$lut.bit.in.2","d_1_am__U86$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U86$lut$lut.bit.in.1"], - ["d_1_am__U87$lut$lut.bit.in.0","d_1_am__U86$lut$lut.bit.out"], - ["d_1_am__U87$lut$lut.bit.in.2","d_1_am__U87$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U87$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U87$lut$lut.bit.out"], + ["d_1_am__U28$lut$lut.bit.in.2","d_1_am__U28$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U28$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U28$lut$lut.bit.in.1"], + ["d_1_am__U29$lut$lut.bit.in.0","d_1_am__U28$lut$lut.bit.out"], + ["d_1_am__U29$lut$lut.bit.in.2","d_1_am__U29$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U29$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U29$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -6176,16 +6225,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U88$lut$lut.bit.in.2","d_2_am__U88$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U88$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U88$lut$lut.bit.in.1"], - ["d_2_am__U89$lut$lut.bit.in.0","d_2_am__U88$lut$lut.bit.out"], - ["d_2_am__U89$lut$lut.bit.in.2","d_2_am__U89$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U89$lut$lut.bit.in.1"], - ["d_2_am__U90$lut$lut.bit.in.0","d_2_am__U89$lut$lut.bit.out"], - ["d_2_am__U90$lut$lut.bit.in.2","d_2_am__U90$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U90$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U90$lut$lut.bit.out"], + ["d_2_am__U30$lut$lut.bit.in.2","d_2_am__U30$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U30$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U30$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U30$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -6202,13 +6245,6 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U91$lut$lut.bit.in.2","d_3_am__U91$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U91$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U91$lut$lut.bit.in.1"], - ["d_3_am__U92$lut$lut.bit.in.0","d_3_am__U91$lut$lut.bit.out"], - ["d_3_am__U92$lut$lut.bit.in.2","d_3_am__U92$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U92$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U92$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -6218,50 +6254,14 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U93$lut$lut.bit.in.2","d_4_am__U93$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U93$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U93$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U93$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["true_lutcnst.bit.out","d_5_next_value.sel"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"] ] }, "cu_op_hcompute_hw_output_stencil":{ @@ -6337,26 +6337,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U514":{ + "PE_init_U431":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U512":{ + "_U429":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U513":{ + "_U430":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U512.out","PE_init_U514.data.in.0"], - ["_U513.out","PE_init_U514.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U514.data.out"], + ["_U429.out","PE_init_U431.data.in.0"], + ["_U430.out","PE_init_U431.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U431.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -6368,26 +6368,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U517":{ + "PE_init_U434":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U515":{ + "_U432":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U516":{ + "_U433":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U515.out","PE_init_U517.data.in.0"], - ["_U516.out","PE_init_U517.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U517.data.out"], + ["_U432.out","PE_init_U434.data.in.0"], + ["_U433.out","PE_init_U434.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U434.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7173,26 +7173,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U520":{ + "PE_init_U437":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U518":{ + "_U435":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U519":{ + "_U436":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U518.out","PE_init_U520.data.in.0"], - ["_U519.out","PE_init_U520.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U520.data.out"], + ["_U435.out","PE_init_U437.data.in.0"], + ["_U436.out","PE_init_U437.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U437.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7204,26 +7204,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U523":{ + "PE_init_U440":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U521":{ + "_U438":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U522":{ + "_U439":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U521.out","PE_init_U523.data.in.0"], - ["_U522.out","PE_init_U523.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U523.data.out"], + ["_U438.out","PE_init_U440.data.in.0"], + ["_U439.out","PE_init_U440.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U440.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7235,26 +7235,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U526":{ + "PE_init_U443":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U524":{ + "_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U525":{ + "_U442":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U524.out","PE_init_U526.data.in.0"], - ["_U525.out","PE_init_U526.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U526.data.out"], + ["_U441.out","PE_init_U443.data.in.0"], + ["_U442.out","PE_init_U443.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U443.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7266,26 +7266,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U529":{ + "PE_init_U446":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U527":{ + "_U444":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U528":{ + "_U445":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U527.out","PE_init_U529.data.in.0"], - ["_U528.out","PE_init_U529.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U529.data.out"], + ["_U444.out","PE_init_U446.data.in.0"], + ["_U445.out","PE_init_U446.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U446.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7297,26 +7297,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U532":{ + "PE_init_U449":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U530":{ + "_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U531":{ + "_U448":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U530.out","PE_init_U532.data.in.0"], - ["_U531.out","PE_init_U532.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U532.data.out"], + ["_U447.out","PE_init_U449.data.in.0"], + ["_U448.out","PE_init_U449.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U449.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7328,26 +7328,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U535":{ + "PE_init_U452":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U533":{ + "_U450":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U534":{ + "_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U533.out","PE_init_U535.data.in.0"], - ["_U534.out","PE_init_U535.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U535.data.out"], + ["_U450.out","PE_init_U452.data.in.0"], + ["_U451.out","PE_init_U452.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U452.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -7672,26 +7672,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U538":{ + "PE_init_U455":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U536":{ + "_U453":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U537":{ + "_U454":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U536.out","PE_init_U538.data.in.0"], - ["_U537.out","PE_init_U538.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U538.data.out"] + ["_U453.out","PE_init_U455.data.in.0"], + ["_U454.out","PE_init_U455.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U455.data.out"] ] }, "hcompute_output_cgra_stencil_1":{ @@ -7699,26 +7699,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U541":{ + "PE_init_U458":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U539":{ + "_U456":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U540":{ + "_U457":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U539.out","PE_init_U541.data.in.0"], - ["_U540.out","PE_init_U541.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U541.data.out"] + ["_U456.out","PE_init_U458.data.in.0"], + ["_U457.out","PE_init_U458.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U458.data.out"] ] }, "hcompute_output_cgra_stencil_10":{ @@ -8476,26 +8476,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U544":{ + "PE_init_U461":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U542":{ + "_U459":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U543":{ + "_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U542.out","PE_init_U544.data.in.0"], - ["_U543.out","PE_init_U544.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U544.data.out"] + ["_U459.out","PE_init_U461.data.in.0"], + ["_U460.out","PE_init_U461.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U461.data.out"] ] }, "hcompute_output_cgra_stencil_3":{ @@ -8503,26 +8503,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U547":{ + "PE_init_U464":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U545":{ + "_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U546":{ + "_U463":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U545.out","PE_init_U547.data.in.0"], - ["_U546.out","PE_init_U547.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U547.data.out"] + ["_U462.out","PE_init_U464.data.in.0"], + ["_U463.out","PE_init_U464.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U464.data.out"] ] }, "hcompute_output_cgra_stencil_4":{ @@ -8530,26 +8530,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U550":{ + "PE_init_U467":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U548":{ + "_U465":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U549":{ + "_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U548.out","PE_init_U550.data.in.0"], - ["_U549.out","PE_init_U550.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U550.data.out"] + ["_U465.out","PE_init_U467.data.in.0"], + ["_U466.out","PE_init_U467.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U467.data.out"] ] }, "hcompute_output_cgra_stencil_5":{ @@ -8557,26 +8557,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U553":{ + "PE_init_U470":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U551":{ + "_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U552":{ + "_U469":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U551.out","PE_init_U553.data.in.0"], - ["_U552.out","PE_init_U553.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U553.data.out"] + ["_U468.out","PE_init_U470.data.in.0"], + ["_U469.out","PE_init_U470.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U470.data.out"] ] }, "hcompute_output_cgra_stencil_6":{ @@ -8584,26 +8584,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U556":{ + "PE_init_U473":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U554":{ + "_U471":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U555":{ + "_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U554.out","PE_init_U556.data.in.0"], - ["_U555.out","PE_init_U556.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U556.data.out"] + ["_U471.out","PE_init_U473.data.in.0"], + ["_U472.out","PE_init_U473.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U473.data.out"] ] }, "hcompute_output_cgra_stencil_7":{ @@ -8611,26 +8611,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U559":{ + "PE_init_U476":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U557":{ + "_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U558":{ + "_U475":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U557.out","PE_init_U559.data.in.0"], - ["_U558.out","PE_init_U559.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U559.data.out"] + ["_U474.out","PE_init_U476.data.in.0"], + ["_U475.out","PE_init_U476.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U476.data.out"] ] }, "hcompute_output_cgra_stencil_8":{ @@ -8917,38 +8917,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -8956,7 +8924,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -8966,7 +8934,7 @@ }, "ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -8976,7 +8944,7 @@ }, "ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -8986,7 +8954,7 @@ }, "ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -8996,7 +8964,7 @@ }, "ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -9006,7 +8974,7 @@ }, "ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2301],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -9016,7 +8984,7 @@ }, "ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -9026,7 +8994,7 @@ }, "ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -9168,262 +9136,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U118":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U120":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U122":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U124":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U126":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U128":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U130":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U136":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U138":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U140":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U142":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U144":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U146":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U148":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U150":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U152":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U154":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U156":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U158":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U160":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U164":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U166":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U168":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U170":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U172":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U174":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U176":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U178":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U180":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U182":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U184":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U186":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U188":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U190":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U194":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U196":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U198":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U200":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U202":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U204":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U206":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U208":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U210":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U212":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U214":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U216":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U218":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U220":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U222":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U224":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U226":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U228":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U230":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U232":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U234":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U236":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U238":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U240":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U242":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U244":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9431,7 +9143,7 @@ }, "ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -9441,7 +9153,7 @@ }, "ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -9451,7 +9163,7 @@ }, "ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -9461,7 +9173,7 @@ }, "ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -9471,7 +9183,7 @@ }, "ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -9481,7 +9193,7 @@ }, "ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -9491,7 +9203,7 @@ }, "ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -9501,7 +9213,7 @@ }, "ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -9511,7 +9223,7 @@ }, "ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -9521,7 +9233,7 @@ }, "ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -9531,7 +9243,7 @@ }, "ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -9541,7 +9253,7 @@ }, "ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U109"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -9551,7 +9263,7 @@ }, "ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -9561,7 +9273,7 @@ }, "ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -9571,7 +9283,7 @@ }, "ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -9581,7 +9293,7 @@ }, "ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -9591,7 +9303,7 @@ }, "ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -9601,7 +9313,7 @@ }, "ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -9611,7 +9323,7 @@ }, "ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -9621,7 +9333,7 @@ }, "ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -9631,7 +9343,7 @@ }, "ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -9641,7 +9353,7 @@ }, "ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -9651,7 +9363,7 @@ }, "ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -9661,7 +9373,7 @@ }, "ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -9671,7 +9383,7 @@ }, "ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -9681,7 +9393,7 @@ }, "ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -9691,7 +9403,7 @@ }, "ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -9701,7 +9413,7 @@ }, "ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -9711,7 +9423,7 @@ }, "ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -9721,7 +9433,7 @@ }, "ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -9731,7 +9443,7 @@ }, "ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -9741,7 +9453,7 @@ }, "ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -9751,7 +9463,7 @@ }, "ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -9761,7 +9473,7 @@ }, "ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -9771,7 +9483,7 @@ }, "ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U197"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -9781,7 +9493,7 @@ }, "ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U199"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -9791,7 +9503,7 @@ }, "ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U201"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -9801,7 +9513,7 @@ }, "ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U203"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -9811,7 +9523,7 @@ }, "ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U205"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -9821,7 +9533,7 @@ }, "ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U207"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -9831,7 +9543,7 @@ }, "ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -9841,7 +9553,7 @@ }, "ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -9851,7 +9563,7 @@ }, "ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -9861,7 +9573,7 @@ }, "ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -9871,7 +9583,7 @@ }, "ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -9881,7 +9593,7 @@ }, "ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -9891,7 +9603,7 @@ }, "ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -9901,7 +9613,7 @@ }, "ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -9911,7 +9623,7 @@ }, "ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -9921,7 +9633,7 @@ }, "ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -9931,7 +9643,7 @@ }, "ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -9941,7 +9653,7 @@ }, "ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -9951,7 +9663,7 @@ }, "ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -9961,7 +9673,7 @@ }, "ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -9971,7 +9683,7 @@ }, "ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -9981,7 +9693,7 @@ }, "ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -9991,7 +9703,7 @@ }, "ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -10001,7 +9713,7 @@ }, "ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -10011,7 +9723,7 @@ }, "ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -10021,7 +9733,7 @@ }, "ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -10031,7 +9743,7 @@ }, "ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -10041,7 +9753,7 @@ }, "ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -10051,7 +9763,7 @@ }, "ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -10061,7 +9773,7 @@ }, "ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -10402,7 +10114,7 @@ ["self.op_hcompute_kernel_glb_stencil_write.0","self.op_hcompute_kernel_cgra_stencil_read.0"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U500":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U417":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10411,7 +10123,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U499":{ + "op_hcompute_hw_output_stencil_read_start_pt__U416":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10420,7 +10132,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U501":{ + "op_hcompute_hw_output_stencil_write_start_pt__U418":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10429,7 +10141,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U509":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U426":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10438,7 +10150,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U508":{ + "op_hcompute_input_glb_stencil_read_start_pt__U425":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10447,7 +10159,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U510":{ + "op_hcompute_input_glb_stencil_write_start_pt__U427":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10456,7 +10168,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U504":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U421":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10465,7 +10177,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U503":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U420":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10474,7 +10186,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U505":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U422":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -10540,38 +10252,6 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U384":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U386":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U388":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U390":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U392":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U394":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U396":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10579,7 +10259,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U381"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U307"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6621],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6624],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -10589,7 +10269,7 @@ }, "ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[2313],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6623],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6625],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -10599,7 +10279,7 @@ }, "ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U385"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U309"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6623],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6626],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -10609,7 +10289,7 @@ }, "ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U387"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6625],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6627],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -10619,7 +10299,7 @@ }, "ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6625],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6628],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -10629,7 +10309,7 @@ }, "ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U391"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6627],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6629],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -10639,7 +10319,7 @@ }, "ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U393"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U313"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6627],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6630],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -10649,7 +10329,7 @@ }, "ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U395"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6629],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6631],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -10738,158 +10418,126 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U562":{ + "PE_init_U479":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U565":{ + "PE_init_U482":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U568":{ + "PE_init_U485":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U571":{ + "PE_init_U488":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U574":{ + "PE_init_U491":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U577":{ + "PE_init_U494":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U580":{ + "PE_init_U497":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U583":{ + "PE_init_U500":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U560":{ + "_U477":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U561":{ + "_U478":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U563":{ + "_U480":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U564":{ + "_U481":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U566":{ + "_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U567":{ + "_U484":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U569":{ + "_U486":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U570":{ + "_U487":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U572":{ + "_U489":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U573":{ + "_U490":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U575":{ + "_U492":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U576":{ + "_U493":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U578":{ + "_U495":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U579":{ + "_U496":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U581":{ + "_U498":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U582":{ + "_U499":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "input_cgra_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10897,7 +10545,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -10907,7 +10555,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -10917,7 +10565,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -10927,7 +10575,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -10937,7 +10585,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -10947,7 +10595,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2301],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -10957,7 +10605,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -10967,7 +10615,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,128,2304],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,128,2304],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[2302],"cycle_stride":[8,32,224,672,2304],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -10996,262 +10644,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "kernel_cgra_stencil$chain_en_const_U118":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U120":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U122":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U124":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U126":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U128":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U130":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U134":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U136":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U138":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U140":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U142":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U144":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U146":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U148":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U150":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U152":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U154":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U156":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U158":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U160":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U164":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U166":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U168":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U170":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U172":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U174":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U176":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U178":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U180":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U182":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U184":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U186":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U188":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U190":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U194":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U196":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U198":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U200":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U202":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U204":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U206":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U208":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U210":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U212":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U214":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U216":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U218":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U220":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U222":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U224":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U226":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U228":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U230":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U232":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U234":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U236":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U238":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U240":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U242":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U244":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -11259,7 +10651,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U108"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -11269,7 +10661,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -11279,7 +10671,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -11289,7 +10681,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U120"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -11299,7 +10691,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -11309,7 +10701,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -11319,7 +10711,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -11329,7 +10721,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U124"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -11339,7 +10731,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -11349,7 +10741,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U126"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -11359,7 +10751,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -11369,7 +10761,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U119"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U109"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -11379,7 +10771,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U128"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -11389,7 +10781,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -11399,7 +10791,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -11409,7 +10801,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -11419,7 +10811,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U132"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -11429,7 +10821,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -11439,7 +10831,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -11449,7 +10841,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -11459,7 +10851,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -11469,7 +10861,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -11479,7 +10871,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U110"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -11489,7 +10881,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -11499,7 +10891,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -11509,7 +10901,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -11519,7 +10911,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -11529,7 +10921,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -11539,7 +10931,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -11549,7 +10941,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -11559,7 +10951,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -11569,7 +10961,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -11579,7 +10971,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -11589,7 +10981,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U123"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U111"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -11599,7 +10991,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U197"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -11609,7 +11001,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U199"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -11619,7 +11011,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U201"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -11629,7 +11021,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U203"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -11639,7 +11031,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U205"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -11649,7 +11041,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U207"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -11659,7 +11051,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -11669,7 +11061,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -11679,7 +11071,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -11689,7 +11081,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -11699,7 +11091,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U125"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -11709,7 +11101,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -11719,7 +11111,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -11729,7 +11121,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -11739,7 +11131,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -11749,7 +11141,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -11759,7 +11151,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -11769,7 +11161,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -11779,7 +11171,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -11789,7 +11181,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -11799,7 +11191,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -11809,7 +11201,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U127"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -11819,7 +11211,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -11829,7 +11221,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -11839,7 +11231,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -11849,7 +11241,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -11859,7 +11251,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U129"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U114"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -11869,7 +11261,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U115"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -11879,7 +11271,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U116"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -11889,7 +11281,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U117"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,768,2304],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,256,768,2304],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2305],"cycle_stride":[4,32,224,672,2304],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,4,32,224,672,2304],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -11899,7 +11291,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U498"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U415"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[6624],"cycle_stride":[1,32,4608],"dimensionality":3,"extent":[32,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,32]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_output_cgra_stencil_10$inner_compute$add_957_971_972$binop":{ @@ -12542,38 +11934,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "output_cgra_stencil$chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U384":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U386":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U388":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U390":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U392":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U394":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U396":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -12581,7 +11941,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U381"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U307"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6621],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6624],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -12591,7 +11951,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[2313],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6623],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6625],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -12601,7 +11961,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U385"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U309"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6623],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6626],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -12611,7 +11971,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U387"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6625],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6627],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -12621,7 +11981,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U389"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6625],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6628],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -12631,7 +11991,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U391"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6627],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6629],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -12641,7 +12001,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U393"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U313"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6627],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6630],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -12651,35 +12011,35 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U395"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[2312],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4608],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4608],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[2306],"cycle_stride":[4,32,224,672,2304,4608],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[6629],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[2308],"cycle_stride":[1,32,224,2304,4608],"dimensionality":5,"extent":[28,7,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,4]},"tb2out_1":{"cycle_starting_addr":[6631],"cycle_stride":[8,32,224,4608],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U560.out","PE_init_U562.data.in.0"], - ["_U561.out","PE_init_U562.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U562.data.out"], - ["_U563.out","PE_init_U565.data.in.0"], - ["_U564.out","PE_init_U565.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U565.data.out"], - ["_U566.out","PE_init_U568.data.in.0"], - ["_U567.out","PE_init_U568.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U568.data.out"], - ["_U569.out","PE_init_U571.data.in.0"], - ["_U570.out","PE_init_U571.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U571.data.out"], - ["_U572.out","PE_init_U574.data.in.0"], - ["_U573.out","PE_init_U574.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U574.data.out"], - ["_U575.out","PE_init_U577.data.in.0"], - ["_U576.out","PE_init_U577.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U577.data.out"], - ["_U578.out","PE_init_U580.data.in.0"], - ["_U579.out","PE_init_U580.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U580.data.out"], - ["_U581.out","PE_init_U583.data.in.0"], - ["_U582.out","PE_init_U583.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U583.data.out"], + ["_U477.out","PE_init_U479.data.in.0"], + ["_U478.out","PE_init_U479.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U479.data.out"], + ["_U480.out","PE_init_U482.data.in.0"], + ["_U481.out","PE_init_U482.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U482.data.out"], + ["_U483.out","PE_init_U485.data.in.0"], + ["_U484.out","PE_init_U485.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U485.data.out"], + ["_U486.out","PE_init_U488.data.in.0"], + ["_U487.out","PE_init_U488.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U488.data.out"], + ["_U489.out","PE_init_U491.data.in.0"], + ["_U490.out","PE_init_U491.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U491.data.out"], + ["_U492.out","PE_init_U494.data.in.0"], + ["_U493.out","PE_init_U494.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U494.data.out"], + ["_U495.out","PE_init_U497.data.in.0"], + ["_U496.out","PE_init_U497.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U497.data.out"], + ["_U498.out","PE_init_U500.data.in.0"], + ["_U499.out","PE_init_U500.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U500.data.out"], ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_input_host_stencil_op_hcompute_input_glb_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_output_cgra_stencil_10$inner_compute$mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957$binop.data.in.1","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll.json b/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll.json index b1f11cd62..d6b71a951 100644 --- a/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll.json +++ b/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll.json @@ -2,2231 +2,2231 @@ "namespaces":{ "global":{ "modules":{ - "aff__U119":{ + "aff__U109":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U129":{ + "add_all__U119":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U130":{ + "add_all__U120":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U131":{ + "add_all__U121":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U132":{ + "add_all__U122":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U120":{ + "coeff_0_U110":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U122":{ + "coeff_1_U112":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_2_U124":{ + "coeff_2_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U126":{ + "coeff_3_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "const_term_U128":{ + "const_term_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "mul_d0__U121":{ + "mul_d0__U111":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U123":{ + "mul_d1__U113":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U125":{ + "mul_d2__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U127":{ + "mul_d3__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U121.out","add_all__U129.in0"], - ["mul_d1__U123.out","add_all__U129.in1"], - ["add_all__U130.in0","add_all__U129.out"], - ["mul_d2__U125.out","add_all__U130.in1"], - ["add_all__U131.in0","add_all__U130.out"], - ["mul_d3__U127.out","add_all__U131.in1"], - ["add_all__U132.in0","add_all__U131.out"], - ["const_term_U128.out","add_all__U132.in1"], - ["self.out","add_all__U132.out"], - ["mul_d0__U121.in0","coeff_0_U120.out"], - ["mul_d1__U123.in0","coeff_1_U122.out"], - ["mul_d2__U125.in0","coeff_2_U124.out"], - ["mul_d3__U127.in0","coeff_3_U126.out"], - ["self.d.0","mul_d0__U121.in1"], - ["self.d.1","mul_d1__U123.in1"], - ["self.d.2","mul_d2__U125.in1"], - ["self.d.3","mul_d3__U127.in1"] + ["mul_d0__U111.out","add_all__U119.in0"], + ["mul_d1__U113.out","add_all__U119.in1"], + ["add_all__U120.in0","add_all__U119.out"], + ["mul_d2__U115.out","add_all__U120.in1"], + ["add_all__U121.in0","add_all__U120.out"], + ["mul_d3__U117.out","add_all__U121.in1"], + ["add_all__U122.in0","add_all__U121.out"], + ["const_term_U118.out","add_all__U122.in1"], + ["self.out","add_all__U122.out"], + ["mul_d0__U111.in0","coeff_0_U110.out"], + ["mul_d1__U113.in0","coeff_1_U112.out"], + ["mul_d2__U115.in0","coeff_2_U114.out"], + ["mul_d3__U117.in0","coeff_3_U116.out"], + ["self.d.0","mul_d0__U111.in1"], + ["self.d.1","mul_d1__U113.in1"], + ["self.d.2","mul_d2__U115.in1"], + ["self.d.3","mul_d3__U117.in1"] ] }, - "aff__U142":{ + "aff__U132":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U152":{ + "add_all__U142":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U153":{ + "add_all__U143":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U154":{ + "add_all__U144":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U155":{ + "add_all__U145":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U143":{ + "coeff_0_U133":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U145":{ + "coeff_1_U135":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U147":{ + "coeff_2_U137":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U149":{ + "coeff_3_U139":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U151":{ + "const_term_U141":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U144":{ + "mul_d0__U134":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U146":{ + "mul_d1__U136":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U148":{ + "mul_d2__U138":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U150":{ + "mul_d3__U140":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U144.out","add_all__U152.in0"], - ["mul_d1__U146.out","add_all__U152.in1"], - ["add_all__U153.in0","add_all__U152.out"], - ["mul_d2__U148.out","add_all__U153.in1"], - ["add_all__U154.in0","add_all__U153.out"], - ["mul_d3__U150.out","add_all__U154.in1"], - ["add_all__U155.in0","add_all__U154.out"], - ["const_term_U151.out","add_all__U155.in1"], - ["self.out","add_all__U155.out"], - ["mul_d0__U144.in0","coeff_0_U143.out"], - ["mul_d1__U146.in0","coeff_1_U145.out"], - ["mul_d2__U148.in0","coeff_2_U147.out"], - ["mul_d3__U150.in0","coeff_3_U149.out"], - ["self.d.0","mul_d0__U144.in1"], - ["self.d.1","mul_d1__U146.in1"], - ["self.d.2","mul_d2__U148.in1"], - ["self.d.3","mul_d3__U150.in1"] + ["mul_d0__U134.out","add_all__U142.in0"], + ["mul_d1__U136.out","add_all__U142.in1"], + ["add_all__U143.in0","add_all__U142.out"], + ["mul_d2__U138.out","add_all__U143.in1"], + ["add_all__U144.in0","add_all__U143.out"], + ["mul_d3__U140.out","add_all__U144.in1"], + ["add_all__U145.in0","add_all__U144.out"], + ["const_term_U141.out","add_all__U145.in1"], + ["self.out","add_all__U145.out"], + ["mul_d0__U134.in0","coeff_0_U133.out"], + ["mul_d1__U136.in0","coeff_1_U135.out"], + ["mul_d2__U138.in0","coeff_2_U137.out"], + ["mul_d3__U140.in0","coeff_3_U139.out"], + ["self.d.0","mul_d0__U134.in1"], + ["self.d.1","mul_d1__U136.in1"], + ["self.d.2","mul_d2__U138.in1"], + ["self.d.3","mul_d3__U140.in1"] ] }, - "aff__U158":{ + "aff__U148":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U172":{ + "add_all__U162":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U173":{ + "add_all__U163":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U174":{ + "add_all__U164":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U175":{ + "add_all__U165":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U176":{ + "add_all__U166":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U177":{ + "add_all__U167":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U159":{ + "coeff_0_U149":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U161":{ + "coeff_1_U151":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U163":{ + "coeff_2_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U165":{ + "coeff_3_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U167":{ + "coeff_4_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_5_U169":{ + "coeff_5_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U171":{ + "const_term_U161":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U160":{ + "mul_d0__U150":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U162":{ + "mul_d1__U152":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U164":{ + "mul_d2__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U166":{ + "mul_d3__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U168":{ + "mul_d4__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U170":{ + "mul_d5__U160":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U160.out","add_all__U172.in0"], - ["mul_d1__U162.out","add_all__U172.in1"], - ["add_all__U173.in0","add_all__U172.out"], - ["mul_d2__U164.out","add_all__U173.in1"], - ["add_all__U174.in0","add_all__U173.out"], - ["mul_d3__U166.out","add_all__U174.in1"], - ["add_all__U175.in0","add_all__U174.out"], - ["mul_d4__U168.out","add_all__U175.in1"], - ["add_all__U176.in0","add_all__U175.out"], - ["mul_d5__U170.out","add_all__U176.in1"], - ["add_all__U177.in0","add_all__U176.out"], - ["const_term_U171.out","add_all__U177.in1"], - ["self.out","add_all__U177.out"], - ["mul_d0__U160.in0","coeff_0_U159.out"], - ["mul_d1__U162.in0","coeff_1_U161.out"], - ["mul_d2__U164.in0","coeff_2_U163.out"], - ["mul_d3__U166.in0","coeff_3_U165.out"], - ["mul_d4__U168.in0","coeff_4_U167.out"], - ["mul_d5__U170.in0","coeff_5_U169.out"], - ["self.d.0","mul_d0__U160.in1"], - ["self.d.1","mul_d1__U162.in1"], - ["self.d.2","mul_d2__U164.in1"], - ["self.d.3","mul_d3__U166.in1"], - ["self.d.4","mul_d4__U168.in1"], - ["self.d.5","mul_d5__U170.in1"] + ["mul_d0__U150.out","add_all__U162.in0"], + ["mul_d1__U152.out","add_all__U162.in1"], + ["add_all__U163.in0","add_all__U162.out"], + ["mul_d2__U154.out","add_all__U163.in1"], + ["add_all__U164.in0","add_all__U163.out"], + ["mul_d3__U156.out","add_all__U164.in1"], + ["add_all__U165.in0","add_all__U164.out"], + ["mul_d4__U158.out","add_all__U165.in1"], + ["add_all__U166.in0","add_all__U165.out"], + ["mul_d5__U160.out","add_all__U166.in1"], + ["add_all__U167.in0","add_all__U166.out"], + ["const_term_U161.out","add_all__U167.in1"], + ["self.out","add_all__U167.out"], + ["mul_d0__U150.in0","coeff_0_U149.out"], + ["mul_d1__U152.in0","coeff_1_U151.out"], + ["mul_d2__U154.in0","coeff_2_U153.out"], + ["mul_d3__U156.in0","coeff_3_U155.out"], + ["mul_d4__U158.in0","coeff_4_U157.out"], + ["mul_d5__U160.in0","coeff_5_U159.out"], + ["self.d.0","mul_d0__U150.in1"], + ["self.d.1","mul_d1__U152.in1"], + ["self.d.2","mul_d2__U154.in1"], + ["self.d.3","mul_d3__U156.in1"], + ["self.d.4","mul_d4__U158.in1"], + ["self.d.5","mul_d5__U160.in1"] ] }, - "aff__U18":{ + "aff__U186":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] + ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U28":{ + "add_all__U200":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U201":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U202":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U29":{ + "add_all__U203":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U30":{ + "add_all__U204":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U31":{ + "add_all__U205":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U19":{ + "coeff_0_U187":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U21":{ + "coeff_1_U189":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_2_U191":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_2_U23":{ + "coeff_3_U193":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "coeff_4_U195":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U25":{ + "coeff_5_U197":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U27":{ + "const_term_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U20":{ + "mul_d0__U188":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U22":{ + "mul_d1__U190":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U24":{ + "mul_d2__U192":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U26":{ + "mul_d3__U194":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d4__U196":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d5__U198":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] + ["mul_d0__U188.out","add_all__U200.in0"], + ["mul_d1__U190.out","add_all__U200.in1"], + ["add_all__U201.in0","add_all__U200.out"], + ["mul_d2__U192.out","add_all__U201.in1"], + ["add_all__U202.in0","add_all__U201.out"], + ["mul_d3__U194.out","add_all__U202.in1"], + ["add_all__U203.in0","add_all__U202.out"], + ["mul_d4__U196.out","add_all__U203.in1"], + ["add_all__U204.in0","add_all__U203.out"], + ["mul_d5__U198.out","add_all__U204.in1"], + ["add_all__U205.in0","add_all__U204.out"], + ["const_term_U199.out","add_all__U205.in1"], + ["self.out","add_all__U205.out"], + ["mul_d0__U188.in0","coeff_0_U187.out"], + ["mul_d1__U190.in0","coeff_1_U189.out"], + ["mul_d2__U192.in0","coeff_2_U191.out"], + ["mul_d3__U194.in0","coeff_3_U193.out"], + ["mul_d4__U196.in0","coeff_4_U195.out"], + ["mul_d5__U198.in0","coeff_5_U197.out"], + ["self.d.0","mul_d0__U188.in1"], + ["self.d.1","mul_d1__U190.in1"], + ["self.d.2","mul_d2__U192.in1"], + ["self.d.3","mul_d3__U194.in1"], + ["self.d.4","mul_d4__U196.in1"], + ["self.d.5","mul_d5__U198.in1"] ] }, - "aff__U196":{ + "aff__U273":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",6,["Array",32,"BitIn"]]] + ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U210":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U211":{ + "add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U212":{ + "add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U213":{ + "add_all__U287":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U214":{ + "add_all__U288":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U215":{ + "add_all__U289":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U197":{ + "coeff_0_U274":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U199":{ + "coeff_1_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U201":{ + "coeff_2_U278":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U203":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_4_U205":{ + "coeff_3_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U207":{ + "coeff_4_U282":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "const_term_U209":{ + "const_term_U284":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U198":{ + "mul_d0__U275":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U200":{ + "mul_d1__U277":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U202":{ + "mul_d2__U279":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U204":{ + "mul_d3__U281":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U206":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d5__U208":{ + "mul_d4__U283":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U198.out","add_all__U210.in0"], - ["mul_d1__U200.out","add_all__U210.in1"], - ["add_all__U211.in0","add_all__U210.out"], - ["mul_d2__U202.out","add_all__U211.in1"], - ["add_all__U212.in0","add_all__U211.out"], - ["mul_d3__U204.out","add_all__U212.in1"], - ["add_all__U213.in0","add_all__U212.out"], - ["mul_d4__U206.out","add_all__U213.in1"], - ["add_all__U214.in0","add_all__U213.out"], - ["mul_d5__U208.out","add_all__U214.in1"], - ["add_all__U215.in0","add_all__U214.out"], - ["const_term_U209.out","add_all__U215.in1"], - ["self.out","add_all__U215.out"], - ["mul_d0__U198.in0","coeff_0_U197.out"], - ["mul_d1__U200.in0","coeff_1_U199.out"], - ["mul_d2__U202.in0","coeff_2_U201.out"], - ["mul_d3__U204.in0","coeff_3_U203.out"], - ["mul_d4__U206.in0","coeff_4_U205.out"], - ["mul_d5__U208.in0","coeff_5_U207.out"], - ["self.d.0","mul_d0__U198.in1"], - ["self.d.1","mul_d1__U200.in1"], - ["self.d.2","mul_d2__U202.in1"], - ["self.d.3","mul_d3__U204.in1"], - ["self.d.4","mul_d4__U206.in1"], - ["self.d.5","mul_d5__U208.in1"] + ["mul_d0__U275.out","add_all__U285.in0"], + ["mul_d1__U277.out","add_all__U285.in1"], + ["add_all__U286.in0","add_all__U285.out"], + ["mul_d2__U279.out","add_all__U286.in1"], + ["add_all__U287.in0","add_all__U286.out"], + ["mul_d3__U281.out","add_all__U287.in1"], + ["add_all__U288.in0","add_all__U287.out"], + ["mul_d4__U283.out","add_all__U288.in1"], + ["add_all__U289.in0","add_all__U288.out"], + ["const_term_U284.out","add_all__U289.in1"], + ["self.out","add_all__U289.out"], + ["mul_d0__U275.in0","coeff_0_U274.out"], + ["mul_d1__U277.in0","coeff_1_U276.out"], + ["mul_d2__U279.in0","coeff_2_U278.out"], + ["mul_d3__U281.in0","coeff_3_U280.out"], + ["mul_d4__U283.in0","coeff_4_U282.out"], + ["self.d.0","mul_d0__U275.in1"], + ["self.d.1","mul_d1__U277.in1"], + ["self.d.2","mul_d2__U279.in1"], + ["self.d.3","mul_d3__U281.in1"], + ["self.d.4","mul_d4__U283.in1"] ] }, - "aff__U348":{ + "aff__U303":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U360":{ + "add_all__U315":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U361":{ + "add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U362":{ + "add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U363":{ + "add_all__U318":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U364":{ + "add_all__U319":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U349":{ + "coeff_0_U304":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U351":{ + "coeff_1_U306":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U353":{ + "coeff_2_U308":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U355":{ + "coeff_3_U310":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U357":{ + "coeff_4_U312":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U359":{ + "const_term_U314":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U350":{ + "mul_d0__U305":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U352":{ + "mul_d1__U307":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U354":{ + "mul_d2__U309":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U356":{ + "mul_d3__U311":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U358":{ + "mul_d4__U313":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U350.out","add_all__U360.in0"], - ["mul_d1__U352.out","add_all__U360.in1"], - ["add_all__U361.in0","add_all__U360.out"], - ["mul_d2__U354.out","add_all__U361.in1"], - ["add_all__U362.in0","add_all__U361.out"], - ["mul_d3__U356.out","add_all__U362.in1"], - ["add_all__U363.in0","add_all__U362.out"], - ["mul_d4__U358.out","add_all__U363.in1"], - ["add_all__U364.in0","add_all__U363.out"], - ["const_term_U359.out","add_all__U364.in1"], - ["self.out","add_all__U364.out"], - ["mul_d0__U350.in0","coeff_0_U349.out"], - ["mul_d1__U352.in0","coeff_1_U351.out"], - ["mul_d2__U354.in0","coeff_2_U353.out"], - ["mul_d3__U356.in0","coeff_3_U355.out"], - ["mul_d4__U358.in0","coeff_4_U357.out"], - ["self.d.0","mul_d0__U350.in1"], - ["self.d.1","mul_d1__U352.in1"], - ["self.d.2","mul_d2__U354.in1"], - ["self.d.3","mul_d3__U356.in1"], - ["self.d.4","mul_d4__U358.in1"] + ["mul_d0__U305.out","add_all__U315.in0"], + ["mul_d1__U307.out","add_all__U315.in1"], + ["add_all__U316.in0","add_all__U315.out"], + ["mul_d2__U309.out","add_all__U316.in1"], + ["add_all__U317.in0","add_all__U316.out"], + ["mul_d3__U311.out","add_all__U317.in1"], + ["add_all__U318.in0","add_all__U317.out"], + ["mul_d4__U313.out","add_all__U318.in1"], + ["add_all__U319.in0","add_all__U318.out"], + ["const_term_U314.out","add_all__U319.in1"], + ["self.out","add_all__U319.out"], + ["mul_d0__U305.in0","coeff_0_U304.out"], + ["mul_d1__U307.in0","coeff_1_U306.out"], + ["mul_d2__U309.in0","coeff_2_U308.out"], + ["mul_d3__U311.in0","coeff_3_U310.out"], + ["mul_d4__U313.in0","coeff_4_U312.out"], + ["self.d.0","mul_d0__U305.in1"], + ["self.d.1","mul_d1__U307.in1"], + ["self.d.2","mul_d2__U309.in1"], + ["self.d.3","mul_d3__U311.in1"], + ["self.d.4","mul_d4__U313.in1"] ] }, - "aff__U378":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",5,["Array",32,"BitIn"]]] + ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U390":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U391":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U392":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U393":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U394":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U379":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U381":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U383":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "coeff_3_U385":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000009"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U387":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000240"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U389":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U380":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U382":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U384":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U386":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U388":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U380.out","add_all__U390.in0"], - ["mul_d1__U382.out","add_all__U390.in1"], - ["add_all__U391.in0","add_all__U390.out"], - ["mul_d2__U384.out","add_all__U391.in1"], - ["add_all__U392.in0","add_all__U391.out"], - ["mul_d3__U386.out","add_all__U392.in1"], - ["add_all__U393.in0","add_all__U392.out"], - ["mul_d4__U388.out","add_all__U393.in1"], - ["add_all__U394.in0","add_all__U393.out"], - ["const_term_U389.out","add_all__U394.in1"], - ["self.out","add_all__U394.out"], - ["mul_d0__U380.in0","coeff_0_U379.out"], - ["mul_d1__U382.in0","coeff_1_U381.out"], - ["mul_d2__U384.in0","coeff_2_U383.out"], - ["mul_d3__U386.in0","coeff_3_U385.out"], - ["mul_d4__U388.in0","coeff_4_U387.out"], - ["self.d.0","mul_d0__U380.in1"], - ["self.d.1","mul_d1__U382.in1"], - ["self.d.2","mul_d2__U384.in1"], - ["self.d.3","mul_d3__U386.in1"], - ["self.d.4","mul_d4__U388.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U397":{ + "aff__U322":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U415":{ + "add_all__U340":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U341":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U342":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U418":{ + "add_all__U343":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U419":{ + "add_all__U344":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U420":{ + "add_all__U345":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U421":{ + "add_all__U346":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U422":{ + "add_all__U347":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U398":{ + "coeff_0_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U400":{ + "coeff_1_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U402":{ + "coeff_2_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U404":{ + "coeff_3_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000180"]} }, - "coeff_4_U406":{ + "coeff_4_U331":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_5_U408":{ + "coeff_5_U333":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_6_U410":{ + "coeff_6_U335":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_7_U412":{ + "coeff_7_U337":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U414":{ + "const_term_U339":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U399":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U401":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U403":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U405":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d4__U407":{ + "mul_d0__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U409":{ + "mul_d1__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U411":{ + "mul_d2__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U413":{ + "mul_d3__U330":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U399.out","add_all__U415.in0"], - ["mul_d1__U401.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d2__U403.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["mul_d3__U405.out","add_all__U417.in1"], - ["add_all__U418.in0","add_all__U417.out"], - ["mul_d4__U407.out","add_all__U418.in1"], - ["add_all__U419.in0","add_all__U418.out"], - ["mul_d5__U409.out","add_all__U419.in1"], - ["add_all__U420.in0","add_all__U419.out"], - ["mul_d6__U411.out","add_all__U420.in1"], - ["add_all__U421.in0","add_all__U420.out"], - ["mul_d7__U413.out","add_all__U421.in1"], - ["add_all__U422.in0","add_all__U421.out"], - ["const_term_U414.out","add_all__U422.in1"], - ["self.out","add_all__U422.out"], - ["mul_d0__U399.in0","coeff_0_U398.out"], - ["mul_d1__U401.in0","coeff_1_U400.out"], - ["mul_d2__U403.in0","coeff_2_U402.out"], - ["mul_d3__U405.in0","coeff_3_U404.out"], - ["mul_d4__U407.in0","coeff_4_U406.out"], - ["mul_d5__U409.in0","coeff_5_U408.out"], - ["mul_d6__U411.in0","coeff_6_U410.out"], - ["mul_d7__U413.in0","coeff_7_U412.out"], - ["self.d.0","mul_d0__U399.in1"], - ["self.d.1","mul_d1__U401.in1"], - ["self.d.2","mul_d2__U403.in1"], - ["self.d.3","mul_d3__U405.in1"], - ["self.d.4","mul_d4__U407.in1"], - ["self.d.5","mul_d5__U409.in1"], - ["self.d.6","mul_d6__U411.in1"], - ["self.d.7","mul_d7__U413.in1"] - ] - }, - "aff__U41":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U51":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U52":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U53":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U54":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U42":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U44":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_2_U46":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U48":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} - }, - "const_term_U50":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U43":{ + "mul_d4__U332":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d5__U334":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d6__U336":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d7__U338":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U324.out","add_all__U340.in0"], + ["mul_d1__U326.out","add_all__U340.in1"], + ["add_all__U341.in0","add_all__U340.out"], + ["mul_d2__U328.out","add_all__U341.in1"], + ["add_all__U342.in0","add_all__U341.out"], + ["mul_d3__U330.out","add_all__U342.in1"], + ["add_all__U343.in0","add_all__U342.out"], + ["mul_d4__U332.out","add_all__U343.in1"], + ["add_all__U344.in0","add_all__U343.out"], + ["mul_d5__U334.out","add_all__U344.in1"], + ["add_all__U345.in0","add_all__U344.out"], + ["mul_d6__U336.out","add_all__U345.in1"], + ["add_all__U346.in0","add_all__U345.out"], + ["mul_d7__U338.out","add_all__U346.in1"], + ["add_all__U347.in0","add_all__U346.out"], + ["const_term_U339.out","add_all__U347.in1"], + ["self.out","add_all__U347.out"], + ["mul_d0__U324.in0","coeff_0_U323.out"], + ["mul_d1__U326.in0","coeff_1_U325.out"], + ["mul_d2__U328.in0","coeff_2_U327.out"], + ["mul_d3__U330.in0","coeff_3_U329.out"], + ["mul_d4__U332.in0","coeff_4_U331.out"], + ["mul_d5__U334.in0","coeff_5_U333.out"], + ["mul_d6__U336.in0","coeff_6_U335.out"], + ["mul_d7__U338.in0","coeff_7_U337.out"], + ["self.d.0","mul_d0__U324.in1"], + ["self.d.1","mul_d1__U326.in1"], + ["self.d.2","mul_d2__U328.in1"], + ["self.d.3","mul_d3__U330.in1"], + ["self.d.4","mul_d4__U332.in1"], + ["self.d.5","mul_d5__U334.in1"], + ["self.d.6","mul_d6__U336.in1"], + ["self.d.7","mul_d7__U338.in1"] ] }, - "aff__U454":{ + "aff__U379":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U472":{ + "add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U473":{ + "add_all__U398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U474":{ + "add_all__U399":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U475":{ + "add_all__U400":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U476":{ + "add_all__U401":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U477":{ + "add_all__U402":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U478":{ + "add_all__U403":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U479":{ + "add_all__U404":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U455":{ + "coeff_0_U380":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U457":{ + "coeff_1_U382":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U459":{ + "coeff_2_U384":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U461":{ + "coeff_3_U386":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U463":{ + "coeff_4_U388":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U465":{ + "coeff_5_U390":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U467":{ + "coeff_6_U392":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U469":{ + "coeff_7_U394":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U471":{ + "const_term_U396":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U456":{ + "mul_d0__U381":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U458":{ + "mul_d1__U383":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U460":{ + "mul_d2__U385":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U462":{ + "mul_d3__U387":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U464":{ + "mul_d4__U389":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U466":{ + "mul_d5__U391":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U468":{ + "mul_d6__U393":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U470":{ + "mul_d7__U395":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U456.out","add_all__U472.in0"], - ["mul_d1__U458.out","add_all__U472.in1"], - ["add_all__U473.in0","add_all__U472.out"], - ["mul_d2__U460.out","add_all__U473.in1"], - ["add_all__U474.in0","add_all__U473.out"], - ["mul_d3__U462.out","add_all__U474.in1"], - ["add_all__U475.in0","add_all__U474.out"], - ["mul_d4__U464.out","add_all__U475.in1"], - ["add_all__U476.in0","add_all__U475.out"], - ["mul_d5__U466.out","add_all__U476.in1"], - ["add_all__U477.in0","add_all__U476.out"], - ["mul_d6__U468.out","add_all__U477.in1"], - ["add_all__U478.in0","add_all__U477.out"], - ["mul_d7__U470.out","add_all__U478.in1"], - ["add_all__U479.in0","add_all__U478.out"], - ["const_term_U471.out","add_all__U479.in1"], - ["self.out","add_all__U479.out"], - ["mul_d0__U456.in0","coeff_0_U455.out"], - ["mul_d1__U458.in0","coeff_1_U457.out"], - ["mul_d2__U460.in0","coeff_2_U459.out"], - ["mul_d3__U462.in0","coeff_3_U461.out"], - ["mul_d4__U464.in0","coeff_4_U463.out"], - ["mul_d5__U466.in0","coeff_5_U465.out"], - ["mul_d6__U468.in0","coeff_6_U467.out"], - ["mul_d7__U470.in0","coeff_7_U469.out"], - ["self.d.0","mul_d0__U456.in1"], - ["self.d.1","mul_d1__U458.in1"], - ["self.d.2","mul_d2__U460.in1"], - ["self.d.3","mul_d3__U462.in1"], - ["self.d.4","mul_d4__U464.in1"], - ["self.d.5","mul_d5__U466.in1"], - ["self.d.6","mul_d6__U468.in1"], - ["self.d.7","mul_d7__U470.in1"] + ["mul_d0__U381.out","add_all__U397.in0"], + ["mul_d1__U383.out","add_all__U397.in1"], + ["add_all__U398.in0","add_all__U397.out"], + ["mul_d2__U385.out","add_all__U398.in1"], + ["add_all__U399.in0","add_all__U398.out"], + ["mul_d3__U387.out","add_all__U399.in1"], + ["add_all__U400.in0","add_all__U399.out"], + ["mul_d4__U389.out","add_all__U400.in1"], + ["add_all__U401.in0","add_all__U400.out"], + ["mul_d5__U391.out","add_all__U401.in1"], + ["add_all__U402.in0","add_all__U401.out"], + ["mul_d6__U393.out","add_all__U402.in1"], + ["add_all__U403.in0","add_all__U402.out"], + ["mul_d7__U395.out","add_all__U403.in1"], + ["add_all__U404.in0","add_all__U403.out"], + ["const_term_U396.out","add_all__U404.in1"], + ["self.out","add_all__U404.out"], + ["mul_d0__U381.in0","coeff_0_U380.out"], + ["mul_d1__U383.in0","coeff_1_U382.out"], + ["mul_d2__U385.in0","coeff_2_U384.out"], + ["mul_d3__U387.in0","coeff_3_U386.out"], + ["mul_d4__U389.in0","coeff_4_U388.out"], + ["mul_d5__U391.in0","coeff_5_U390.out"], + ["mul_d6__U393.in0","coeff_6_U392.out"], + ["mul_d7__U395.in0","coeff_7_U394.out"], + ["self.d.0","mul_d0__U381.in1"], + ["self.d.1","mul_d1__U383.in1"], + ["self.d.2","mul_d2__U385.in1"], + ["self.d.3","mul_d3__U387.in1"], + ["self.d.4","mul_d4__U389.in1"], + ["self.d.5","mul_d5__U391.in1"], + ["self.d.6","mul_d6__U393.in1"], + ["self.d.7","mul_d7__U395.in1"] ] }, - "aff__U484":{ + "aff__U408":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U496":{ + "add_all__U420":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U497":{ + "add_all__U421":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U498":{ + "add_all__U422":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U499":{ + "add_all__U423":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U500":{ + "add_all__U424":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U485":{ + "coeff_0_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U487":{ + "coeff_1_U411":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U489":{ + "coeff_2_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U491":{ + "coeff_3_U415":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U493":{ + "coeff_4_U417":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "const_term_U495":{ + "const_term_U419":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "mul_d0__U486":{ + "mul_d0__U410":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U488":{ + "mul_d1__U412":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U490":{ + "mul_d2__U414":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U492":{ + "mul_d3__U416":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U494":{ + "mul_d4__U418":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U486.out","add_all__U496.in0"], - ["mul_d1__U488.out","add_all__U496.in1"], - ["add_all__U497.in0","add_all__U496.out"], - ["mul_d2__U490.out","add_all__U497.in1"], - ["add_all__U498.in0","add_all__U497.out"], - ["mul_d3__U492.out","add_all__U498.in1"], - ["add_all__U499.in0","add_all__U498.out"], - ["mul_d4__U494.out","add_all__U499.in1"], - ["add_all__U500.in0","add_all__U499.out"], - ["const_term_U495.out","add_all__U500.in1"], - ["self.out","add_all__U500.out"], - ["mul_d0__U486.in0","coeff_0_U485.out"], - ["mul_d1__U488.in0","coeff_1_U487.out"], - ["mul_d2__U490.in0","coeff_2_U489.out"], - ["mul_d3__U492.in0","coeff_3_U491.out"], - ["mul_d4__U494.in0","coeff_4_U493.out"], - ["self.d.0","mul_d0__U486.in1"], - ["self.d.1","mul_d1__U488.in1"], - ["self.d.2","mul_d2__U490.in1"], - ["self.d.3","mul_d3__U492.in1"], - ["self.d.4","mul_d4__U494.in1"] + ["mul_d0__U410.out","add_all__U420.in0"], + ["mul_d1__U412.out","add_all__U420.in1"], + ["add_all__U421.in0","add_all__U420.out"], + ["mul_d2__U414.out","add_all__U421.in1"], + ["add_all__U422.in0","add_all__U421.out"], + ["mul_d3__U416.out","add_all__U422.in1"], + ["add_all__U423.in0","add_all__U422.out"], + ["mul_d4__U418.out","add_all__U423.in1"], + ["add_all__U424.in0","add_all__U423.out"], + ["const_term_U419.out","add_all__U424.in1"], + ["self.out","add_all__U424.out"], + ["mul_d0__U410.in0","coeff_0_U409.out"], + ["mul_d1__U412.in0","coeff_1_U411.out"], + ["mul_d2__U414.in0","coeff_2_U413.out"], + ["mul_d3__U416.in0","coeff_3_U415.out"], + ["mul_d4__U418.in0","coeff_4_U417.out"], + ["self.d.0","mul_d0__U410.in1"], + ["self.d.1","mul_d1__U412.in1"], + ["self.d.2","mul_d2__U414.in1"], + ["self.d.3","mul_d3__U416.in1"], + ["self.d.4","mul_d4__U418.in1"] ] }, - "aff__U514":{ + "aff__U438":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U526":{ + "add_all__U450":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U527":{ + "add_all__U451":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U528":{ + "add_all__U452":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U529":{ + "add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U530":{ + "add_all__U454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U515":{ + "coeff_0_U439":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U517":{ + "coeff_1_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U519":{ + "coeff_2_U443":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U521":{ + "coeff_3_U445":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U523":{ + "coeff_4_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U525":{ + "const_term_U449":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U516":{ + "mul_d0__U440":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U518":{ + "mul_d1__U442":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U520":{ + "mul_d2__U444":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U522":{ + "mul_d3__U446":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U524":{ + "mul_d4__U448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U516.out","add_all__U526.in0"], - ["mul_d1__U518.out","add_all__U526.in1"], - ["add_all__U527.in0","add_all__U526.out"], - ["mul_d2__U520.out","add_all__U527.in1"], - ["add_all__U528.in0","add_all__U527.out"], - ["mul_d3__U522.out","add_all__U528.in1"], - ["add_all__U529.in0","add_all__U528.out"], - ["mul_d4__U524.out","add_all__U529.in1"], - ["add_all__U530.in0","add_all__U529.out"], - ["const_term_U525.out","add_all__U530.in1"], - ["self.out","add_all__U530.out"], - ["mul_d0__U516.in0","coeff_0_U515.out"], - ["mul_d1__U518.in0","coeff_1_U517.out"], - ["mul_d2__U520.in0","coeff_2_U519.out"], - ["mul_d3__U522.in0","coeff_3_U521.out"], - ["mul_d4__U524.in0","coeff_4_U523.out"], - ["self.d.0","mul_d0__U516.in1"], - ["self.d.1","mul_d1__U518.in1"], - ["self.d.2","mul_d2__U520.in1"], - ["self.d.3","mul_d3__U522.in1"], - ["self.d.4","mul_d4__U524.in1"] + ["mul_d0__U440.out","add_all__U450.in0"], + ["mul_d1__U442.out","add_all__U450.in1"], + ["add_all__U451.in0","add_all__U450.out"], + ["mul_d2__U444.out","add_all__U451.in1"], + ["add_all__U452.in0","add_all__U451.out"], + ["mul_d3__U446.out","add_all__U452.in1"], + ["add_all__U453.in0","add_all__U452.out"], + ["mul_d4__U448.out","add_all__U453.in1"], + ["add_all__U454.in0","add_all__U453.out"], + ["const_term_U449.out","add_all__U454.in1"], + ["self.out","add_all__U454.out"], + ["mul_d0__U440.in0","coeff_0_U439.out"], + ["mul_d1__U442.in0","coeff_1_U441.out"], + ["mul_d2__U444.in0","coeff_2_U443.out"], + ["mul_d3__U446.in0","coeff_3_U445.out"], + ["mul_d4__U448.in0","coeff_4_U447.out"], + ["self.d.0","mul_d0__U440.in1"], + ["self.d.1","mul_d1__U442.in1"], + ["self.d.2","mul_d2__U444.in1"], + ["self.d.3","mul_d3__U446.in1"], + ["self.d.4","mul_d4__U448.in1"] ] }, - "aff__U533":{ + "aff__U457":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U551":{ + "add_all__U475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U552":{ + "add_all__U476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U553":{ + "add_all__U477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U554":{ + "add_all__U478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U555":{ + "add_all__U479":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U556":{ + "add_all__U480":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U557":{ + "add_all__U481":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U558":{ + "add_all__U482":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U534":{ + "coeff_0_U458":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U536":{ + "coeff_1_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U538":{ + "coeff_2_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U540":{ + "coeff_3_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000180"]} }, - "coeff_4_U542":{ + "coeff_4_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_5_U544":{ + "coeff_5_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_6_U546":{ + "coeff_6_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_7_U548":{ + "coeff_7_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U550":{ + "const_term_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U535":{ + "mul_d0__U459":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U537":{ + "mul_d1__U461":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U539":{ + "mul_d2__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U541":{ + "mul_d3__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U543":{ + "mul_d4__U467":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U545":{ + "mul_d5__U469":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U547":{ + "mul_d6__U471":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U549":{ + "mul_d7__U473":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U535.out","add_all__U551.in0"], - ["mul_d1__U537.out","add_all__U551.in1"], - ["add_all__U552.in0","add_all__U551.out"], - ["mul_d2__U539.out","add_all__U552.in1"], - ["add_all__U553.in0","add_all__U552.out"], - ["mul_d3__U541.out","add_all__U553.in1"], - ["add_all__U554.in0","add_all__U553.out"], - ["mul_d4__U543.out","add_all__U554.in1"], - ["add_all__U555.in0","add_all__U554.out"], - ["mul_d5__U545.out","add_all__U555.in1"], - ["add_all__U556.in0","add_all__U555.out"], - ["mul_d6__U547.out","add_all__U556.in1"], - ["add_all__U557.in0","add_all__U556.out"], - ["mul_d7__U549.out","add_all__U557.in1"], - ["add_all__U558.in0","add_all__U557.out"], - ["const_term_U550.out","add_all__U558.in1"], - ["self.out","add_all__U558.out"], - ["mul_d0__U535.in0","coeff_0_U534.out"], - ["mul_d1__U537.in0","coeff_1_U536.out"], - ["mul_d2__U539.in0","coeff_2_U538.out"], - ["mul_d3__U541.in0","coeff_3_U540.out"], - ["mul_d4__U543.in0","coeff_4_U542.out"], - ["mul_d5__U545.in0","coeff_5_U544.out"], - ["mul_d6__U547.in0","coeff_6_U546.out"], - ["mul_d7__U549.in0","coeff_7_U548.out"], - ["self.d.0","mul_d0__U535.in1"], - ["self.d.1","mul_d1__U537.in1"], - ["self.d.2","mul_d2__U539.in1"], - ["self.d.3","mul_d3__U541.in1"], - ["self.d.4","mul_d4__U543.in1"], - ["self.d.5","mul_d5__U545.in1"], - ["self.d.6","mul_d6__U547.in1"], - ["self.d.7","mul_d7__U549.in1"] + ["mul_d0__U459.out","add_all__U475.in0"], + ["mul_d1__U461.out","add_all__U475.in1"], + ["add_all__U476.in0","add_all__U475.out"], + ["mul_d2__U463.out","add_all__U476.in1"], + ["add_all__U477.in0","add_all__U476.out"], + ["mul_d3__U465.out","add_all__U477.in1"], + ["add_all__U478.in0","add_all__U477.out"], + ["mul_d4__U467.out","add_all__U478.in1"], + ["add_all__U479.in0","add_all__U478.out"], + ["mul_d5__U469.out","add_all__U479.in1"], + ["add_all__U480.in0","add_all__U479.out"], + ["mul_d6__U471.out","add_all__U480.in1"], + ["add_all__U481.in0","add_all__U480.out"], + ["mul_d7__U473.out","add_all__U481.in1"], + ["add_all__U482.in0","add_all__U481.out"], + ["const_term_U474.out","add_all__U482.in1"], + ["self.out","add_all__U482.out"], + ["mul_d0__U459.in0","coeff_0_U458.out"], + ["mul_d1__U461.in0","coeff_1_U460.out"], + ["mul_d2__U463.in0","coeff_2_U462.out"], + ["mul_d3__U465.in0","coeff_3_U464.out"], + ["mul_d4__U467.in0","coeff_4_U466.out"], + ["mul_d5__U469.in0","coeff_5_U468.out"], + ["mul_d6__U471.in0","coeff_6_U470.out"], + ["mul_d7__U473.in0","coeff_7_U472.out"], + ["self.d.0","mul_d0__U459.in1"], + ["self.d.1","mul_d1__U461.in1"], + ["self.d.2","mul_d2__U463.in1"], + ["self.d.3","mul_d3__U465.in1"], + ["self.d.4","mul_d4__U467.in1"], + ["self.d.5","mul_d5__U469.in1"], + ["self.d.6","mul_d6__U471.in1"], + ["self.d.7","mul_d7__U473.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U71":{ + "add_all__U62":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U72":{ + "add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U73":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U74":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U70":{ + "const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U71.in0"], - ["mul_d1__U61.out","add_all__U71.in1"], - ["add_all__U72.in0","add_all__U71.out"], - ["mul_d2__U63.out","add_all__U72.in1"], - ["add_all__U73.in0","add_all__U72.out"], - ["mul_d3__U65.out","add_all__U73.in1"], - ["add_all__U74.in0","add_all__U73.out"], - ["mul_d4__U67.out","add_all__U74.in1"], - ["add_all__U75.in0","add_all__U74.out"], - ["mul_d5__U69.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["const_term_U70.out","add_all__U76.in1"], - ["self.out","add_all__U76.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"] + ["mul_d0__U50.out","add_all__U62.in0"], + ["mul_d1__U52.out","add_all__U62.in1"], + ["add_all__U63.in0","add_all__U62.out"], + ["mul_d2__U54.out","add_all__U63.in1"], + ["add_all__U64.in0","add_all__U63.out"], + ["mul_d3__U56.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["mul_d4__U58.out","add_all__U65.in1"], + ["add_all__U66.in0","add_all__U65.out"], + ["mul_d5__U60.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["const_term_U61.out","add_all__U67.in1"], + ["self.out","add_all__U67.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"] ] }, - "aff__U590":{ + "aff__U514":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U608":{ + "add_all__U532":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U609":{ + "add_all__U533":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U610":{ + "add_all__U534":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U611":{ + "add_all__U535":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U612":{ + "add_all__U536":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U613":{ + "add_all__U537":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U614":{ + "add_all__U538":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U615":{ + "add_all__U539":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U591":{ + "coeff_0_U515":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U593":{ + "coeff_1_U517":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U595":{ + "coeff_2_U519":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U597":{ + "coeff_3_U521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U599":{ + "coeff_4_U523":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U601":{ + "coeff_5_U525":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U603":{ + "coeff_6_U527":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U605":{ + "coeff_7_U529":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U607":{ + "const_term_U531":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U592":{ + "mul_d0__U516":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U594":{ + "mul_d1__U518":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U596":{ + "mul_d2__U520":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U598":{ + "mul_d3__U522":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U600":{ + "mul_d4__U524":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U602":{ + "mul_d5__U526":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U604":{ + "mul_d6__U528":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U606":{ + "mul_d7__U530":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U592.out","add_all__U608.in0"], - ["mul_d1__U594.out","add_all__U608.in1"], - ["add_all__U609.in0","add_all__U608.out"], - ["mul_d2__U596.out","add_all__U609.in1"], - ["add_all__U610.in0","add_all__U609.out"], - ["mul_d3__U598.out","add_all__U610.in1"], - ["add_all__U611.in0","add_all__U610.out"], - ["mul_d4__U600.out","add_all__U611.in1"], - ["add_all__U612.in0","add_all__U611.out"], - ["mul_d5__U602.out","add_all__U612.in1"], - ["add_all__U613.in0","add_all__U612.out"], - ["mul_d6__U604.out","add_all__U613.in1"], - ["add_all__U614.in0","add_all__U613.out"], - ["mul_d7__U606.out","add_all__U614.in1"], - ["add_all__U615.in0","add_all__U614.out"], - ["const_term_U607.out","add_all__U615.in1"], - ["self.out","add_all__U615.out"], - ["mul_d0__U592.in0","coeff_0_U591.out"], - ["mul_d1__U594.in0","coeff_1_U593.out"], - ["mul_d2__U596.in0","coeff_2_U595.out"], - ["mul_d3__U598.in0","coeff_3_U597.out"], - ["mul_d4__U600.in0","coeff_4_U599.out"], - ["mul_d5__U602.in0","coeff_5_U601.out"], - ["mul_d6__U604.in0","coeff_6_U603.out"], - ["mul_d7__U606.in0","coeff_7_U605.out"], - ["self.d.0","mul_d0__U592.in1"], - ["self.d.1","mul_d1__U594.in1"], - ["self.d.2","mul_d2__U596.in1"], - ["self.d.3","mul_d3__U598.in1"], - ["self.d.4","mul_d4__U600.in1"], - ["self.d.5","mul_d5__U602.in1"], - ["self.d.6","mul_d6__U604.in1"], - ["self.d.7","mul_d7__U606.in1"] + ["mul_d0__U516.out","add_all__U532.in0"], + ["mul_d1__U518.out","add_all__U532.in1"], + ["add_all__U533.in0","add_all__U532.out"], + ["mul_d2__U520.out","add_all__U533.in1"], + ["add_all__U534.in0","add_all__U533.out"], + ["mul_d3__U522.out","add_all__U534.in1"], + ["add_all__U535.in0","add_all__U534.out"], + ["mul_d4__U524.out","add_all__U535.in1"], + ["add_all__U536.in0","add_all__U535.out"], + ["mul_d5__U526.out","add_all__U536.in1"], + ["add_all__U537.in0","add_all__U536.out"], + ["mul_d6__U528.out","add_all__U537.in1"], + ["add_all__U538.in0","add_all__U537.out"], + ["mul_d7__U530.out","add_all__U538.in1"], + ["add_all__U539.in0","add_all__U538.out"], + ["const_term_U531.out","add_all__U539.in1"], + ["self.out","add_all__U539.out"], + ["mul_d0__U516.in0","coeff_0_U515.out"], + ["mul_d1__U518.in0","coeff_1_U517.out"], + ["mul_d2__U520.in0","coeff_2_U519.out"], + ["mul_d3__U522.in0","coeff_3_U521.out"], + ["mul_d4__U524.in0","coeff_4_U523.out"], + ["mul_d5__U526.in0","coeff_5_U525.out"], + ["mul_d6__U528.in0","coeff_6_U527.out"], + ["mul_d7__U530.in0","coeff_7_U529.out"], + ["self.d.0","mul_d0__U516.in1"], + ["self.d.1","mul_d1__U518.in1"], + ["self.d.2","mul_d2__U520.in1"], + ["self.d.3","mul_d3__U522.in1"], + ["self.d.4","mul_d4__U524.in1"], + ["self.d.5","mul_d5__U526.in1"], + ["self.d.6","mul_d6__U528.in1"], + ["self.d.7","mul_d7__U530.in1"] ] }, - "aff__U636":{ + "aff__U551":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U650":{ + "add_all__U565":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U651":{ + "add_all__U566":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U652":{ + "add_all__U567":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U653":{ + "add_all__U568":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U654":{ + "add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U655":{ + "add_all__U570":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U637":{ + "coeff_0_U552":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U639":{ + "coeff_1_U554":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U641":{ + "coeff_2_U556":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "coeff_3_U643":{ + "coeff_3_U558":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_4_U645":{ + "coeff_4_U560":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U647":{ + "coeff_5_U562":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U649":{ + "const_term_U564":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003840"]} }, - "mul_d0__U638":{ + "mul_d0__U553":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U640":{ + "mul_d1__U555":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U642":{ + "mul_d2__U557":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U644":{ + "mul_d3__U559":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U646":{ + "mul_d4__U561":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U648":{ + "mul_d5__U563":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U638.out","add_all__U650.in0"], - ["mul_d1__U640.out","add_all__U650.in1"], - ["add_all__U651.in0","add_all__U650.out"], - ["mul_d2__U642.out","add_all__U651.in1"], - ["add_all__U652.in0","add_all__U651.out"], - ["mul_d3__U644.out","add_all__U652.in1"], - ["add_all__U653.in0","add_all__U652.out"], - ["mul_d4__U646.out","add_all__U653.in1"], - ["add_all__U654.in0","add_all__U653.out"], - ["mul_d5__U648.out","add_all__U654.in1"], - ["add_all__U655.in0","add_all__U654.out"], - ["const_term_U649.out","add_all__U655.in1"], - ["self.out","add_all__U655.out"], - ["mul_d0__U638.in0","coeff_0_U637.out"], - ["mul_d1__U640.in0","coeff_1_U639.out"], - ["mul_d2__U642.in0","coeff_2_U641.out"], - ["mul_d3__U644.in0","coeff_3_U643.out"], - ["mul_d4__U646.in0","coeff_4_U645.out"], - ["mul_d5__U648.in0","coeff_5_U647.out"], - ["self.d.0","mul_d0__U638.in1"], - ["self.d.1","mul_d1__U640.in1"], - ["self.d.2","mul_d2__U642.in1"], - ["self.d.3","mul_d3__U644.in1"], - ["self.d.4","mul_d4__U646.in1"], - ["self.d.5","mul_d5__U648.in1"] + ["mul_d0__U553.out","add_all__U565.in0"], + ["mul_d1__U555.out","add_all__U565.in1"], + ["add_all__U566.in0","add_all__U565.out"], + ["mul_d2__U557.out","add_all__U566.in1"], + ["add_all__U567.in0","add_all__U566.out"], + ["mul_d3__U559.out","add_all__U567.in1"], + ["add_all__U568.in0","add_all__U567.out"], + ["mul_d4__U561.out","add_all__U568.in1"], + ["add_all__U569.in0","add_all__U568.out"], + ["mul_d5__U563.out","add_all__U569.in1"], + ["add_all__U570.in0","add_all__U569.out"], + ["const_term_U564.out","add_all__U570.in1"], + ["self.out","add_all__U570.out"], + ["mul_d0__U553.in0","coeff_0_U552.out"], + ["mul_d1__U555.in0","coeff_1_U554.out"], + ["mul_d2__U557.in0","coeff_2_U556.out"], + ["mul_d3__U559.in0","coeff_3_U558.out"], + ["mul_d4__U561.in0","coeff_4_U560.out"], + ["mul_d5__U563.in0","coeff_5_U562.out"], + ["self.d.0","mul_d0__U553.in1"], + ["self.d.1","mul_d1__U555.in1"], + ["self.d.2","mul_d2__U557.in1"], + ["self.d.3","mul_d3__U559.in1"], + ["self.d.4","mul_d4__U561.in1"], + ["self.d.5","mul_d5__U563.in1"] ] }, - "aff__U674":{ + "aff__U589":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U688":{ + "add_all__U603":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U689":{ + "add_all__U604":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U690":{ + "add_all__U605":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U691":{ + "add_all__U606":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U692":{ + "add_all__U607":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U693":{ + "add_all__U608":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U675":{ + "coeff_0_U590":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U677":{ + "coeff_1_U592":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_2_U679":{ + "coeff_2_U594":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U681":{ + "coeff_3_U596":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_4_U683":{ + "coeff_4_U598":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_5_U685":{ + "coeff_5_U600":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U687":{ + "const_term_U602":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U676":{ + "mul_d0__U591":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U678":{ + "mul_d1__U593":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U680":{ + "mul_d2__U595":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U682":{ + "mul_d3__U597":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U684":{ + "mul_d4__U599":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U686":{ + "mul_d5__U601":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U676.out","add_all__U688.in0"], - ["mul_d1__U678.out","add_all__U688.in1"], - ["add_all__U689.in0","add_all__U688.out"], - ["mul_d2__U680.out","add_all__U689.in1"], - ["add_all__U690.in0","add_all__U689.out"], - ["mul_d3__U682.out","add_all__U690.in1"], - ["add_all__U691.in0","add_all__U690.out"], - ["mul_d4__U684.out","add_all__U691.in1"], - ["add_all__U692.in0","add_all__U691.out"], - ["mul_d5__U686.out","add_all__U692.in1"], - ["add_all__U693.in0","add_all__U692.out"], - ["const_term_U687.out","add_all__U693.in1"], - ["self.out","add_all__U693.out"], - ["mul_d0__U676.in0","coeff_0_U675.out"], - ["mul_d1__U678.in0","coeff_1_U677.out"], - ["mul_d2__U680.in0","coeff_2_U679.out"], - ["mul_d3__U682.in0","coeff_3_U681.out"], - ["mul_d4__U684.in0","coeff_4_U683.out"], - ["mul_d5__U686.in0","coeff_5_U685.out"], - ["self.d.0","mul_d0__U676.in1"], - ["self.d.1","mul_d1__U678.in1"], - ["self.d.2","mul_d2__U680.in1"], - ["self.d.3","mul_d3__U682.in1"], - ["self.d.4","mul_d4__U684.in1"], - ["self.d.5","mul_d5__U686.in1"] + ["mul_d0__U591.out","add_all__U603.in0"], + ["mul_d1__U593.out","add_all__U603.in1"], + ["add_all__U604.in0","add_all__U603.out"], + ["mul_d2__U595.out","add_all__U604.in1"], + ["add_all__U605.in0","add_all__U604.out"], + ["mul_d3__U597.out","add_all__U605.in1"], + ["add_all__U606.in0","add_all__U605.out"], + ["mul_d4__U599.out","add_all__U606.in1"], + ["add_all__U607.in0","add_all__U606.out"], + ["mul_d5__U601.out","add_all__U607.in1"], + ["add_all__U608.in0","add_all__U607.out"], + ["const_term_U602.out","add_all__U608.in1"], + ["self.out","add_all__U608.out"], + ["mul_d0__U591.in0","coeff_0_U590.out"], + ["mul_d1__U593.in0","coeff_1_U592.out"], + ["mul_d2__U595.in0","coeff_2_U594.out"], + ["mul_d3__U597.in0","coeff_3_U596.out"], + ["mul_d4__U599.in0","coeff_4_U598.out"], + ["mul_d5__U601.in0","coeff_5_U600.out"], + ["self.d.0","mul_d0__U591.in1"], + ["self.d.1","mul_d1__U593.in1"], + ["self.d.2","mul_d2__U595.in1"], + ["self.d.3","mul_d3__U597.in1"], + ["self.d.4","mul_d4__U599.in1"], + ["self.d.5","mul_d5__U601.in1"] ] }, - "aff__U696":{ + "aff__U611":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U706":{ + "add_all__U621":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U707":{ + "add_all__U622":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U708":{ + "add_all__U623":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U709":{ + "add_all__U624":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U697":{ + "coeff_0_U612":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U699":{ + "coeff_1_U614":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_2_U701":{ + "coeff_2_U616":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U703":{ + "coeff_3_U618":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U705":{ + "const_term_U620":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004e1f"]} }, - "mul_d0__U698":{ + "mul_d0__U613":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U700":{ + "mul_d1__U615":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U702":{ + "mul_d2__U617":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U704":{ + "mul_d3__U619":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U698.out","add_all__U706.in0"], - ["mul_d1__U700.out","add_all__U706.in1"], - ["add_all__U707.in0","add_all__U706.out"], - ["mul_d2__U702.out","add_all__U707.in1"], - ["add_all__U708.in0","add_all__U707.out"], - ["mul_d3__U704.out","add_all__U708.in1"], - ["add_all__U709.in0","add_all__U708.out"], - ["const_term_U705.out","add_all__U709.in1"], - ["self.out","add_all__U709.out"], - ["mul_d0__U698.in0","coeff_0_U697.out"], - ["mul_d1__U700.in0","coeff_1_U699.out"], - ["mul_d2__U702.in0","coeff_2_U701.out"], - ["mul_d3__U704.in0","coeff_3_U703.out"], - ["self.d.0","mul_d0__U698.in1"], - ["self.d.1","mul_d1__U700.in1"], - ["self.d.2","mul_d2__U702.in1"], - ["self.d.3","mul_d3__U704.in1"] + ["mul_d0__U613.out","add_all__U621.in0"], + ["mul_d1__U615.out","add_all__U621.in1"], + ["add_all__U622.in0","add_all__U621.out"], + ["mul_d2__U617.out","add_all__U622.in1"], + ["add_all__U623.in0","add_all__U622.out"], + ["mul_d3__U619.out","add_all__U623.in1"], + ["add_all__U624.in0","add_all__U623.out"], + ["const_term_U620.out","add_all__U624.in1"], + ["self.out","add_all__U624.out"], + ["mul_d0__U613.in0","coeff_0_U612.out"], + ["mul_d1__U615.in0","coeff_1_U614.out"], + ["mul_d2__U617.in0","coeff_2_U616.out"], + ["mul_d3__U619.in0","coeff_3_U618.out"], + ["self.d.0","mul_d0__U613.in1"], + ["self.d.1","mul_d1__U615.in1"], + ["self.d.2","mul_d2__U617.in1"], + ["self.d.3","mul_d3__U619.in1"] ] }, - "aff__U719":{ + "aff__U634":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U729":{ + "add_all__U644":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U730":{ + "add_all__U645":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U731":{ + "add_all__U646":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U732":{ + "add_all__U647":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U720":{ + "coeff_0_U635":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U722":{ + "coeff_1_U637":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U724":{ + "coeff_2_U639":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_3_U726":{ + "coeff_3_U641":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U728":{ + "const_term_U643":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U721":{ + "mul_d0__U636":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U723":{ + "mul_d1__U638":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U725":{ + "mul_d2__U640":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U727":{ + "mul_d3__U642":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U721.out","add_all__U729.in0"], - ["mul_d1__U723.out","add_all__U729.in1"], - ["add_all__U730.in0","add_all__U729.out"], - ["mul_d2__U725.out","add_all__U730.in1"], - ["add_all__U731.in0","add_all__U730.out"], - ["mul_d3__U727.out","add_all__U731.in1"], - ["add_all__U732.in0","add_all__U731.out"], - ["const_term_U728.out","add_all__U732.in1"], - ["self.out","add_all__U732.out"], - ["mul_d0__U721.in0","coeff_0_U720.out"], - ["mul_d1__U723.in0","coeff_1_U722.out"], - ["mul_d2__U725.in0","coeff_2_U724.out"], - ["mul_d3__U727.in0","coeff_3_U726.out"], - ["self.d.0","mul_d0__U721.in1"], - ["self.d.1","mul_d1__U723.in1"], - ["self.d.2","mul_d2__U725.in1"], - ["self.d.3","mul_d3__U727.in1"] + ["mul_d0__U636.out","add_all__U644.in0"], + ["mul_d1__U638.out","add_all__U644.in1"], + ["add_all__U645.in0","add_all__U644.out"], + ["mul_d2__U640.out","add_all__U645.in1"], + ["add_all__U646.in0","add_all__U645.out"], + ["mul_d3__U642.out","add_all__U646.in1"], + ["add_all__U647.in0","add_all__U646.out"], + ["const_term_U643.out","add_all__U647.in1"], + ["self.out","add_all__U647.out"], + ["mul_d0__U636.in0","coeff_0_U635.out"], + ["mul_d1__U638.in0","coeff_1_U637.out"], + ["mul_d2__U640.in0","coeff_2_U639.out"], + ["mul_d3__U642.in0","coeff_3_U641.out"], + ["self.d.0","mul_d0__U636.in1"], + ["self.d.1","mul_d1__U638.in1"], + ["self.d.2","mul_d2__U640.in1"], + ["self.d.3","mul_d3__U642.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U109":{ + "add_all__U100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U110":{ + "add_all__U101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U108":{ + "const_term_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U90":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U92":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U94":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d5__U98":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U88.out","add_all__U100.in0"], + ["mul_d1__U90.out","add_all__U100.in1"], + ["add_all__U101.in0","add_all__U100.out"], + ["mul_d2__U92.out","add_all__U101.in1"], + ["add_all__U102.in0","add_all__U101.out"], + ["mul_d3__U94.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d4__U96.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d5__U98.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["const_term_U99.out","add_all__U105.in1"], + ["self.out","add_all__U105.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"] + ] + }, + "aff__U9":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U19":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U20":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U21":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U22":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000002"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d2__U101":{ + "mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U109.in0"], - ["mul_d1__U99.out","add_all__U109.in1"], - ["add_all__U110.in0","add_all__U109.out"], - ["mul_d2__U101.out","add_all__U110.in1"], - ["add_all__U111.in0","add_all__U110.out"], - ["mul_d3__U103.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d4__U105.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d5__U107.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U108.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U118":{ + "affine_controller__U108":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2234,18 +2234,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U133":{ + "_U123":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U134":{ + "_U124":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U119" + "modref":"global.aff__U109" }, "cmp_time":{ "genref":"coreir.eq", @@ -2255,13 +2255,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U135":{ + "d_0_am__U125":{ "modref":"corebit.and" }, - "d_0_am__U136":{ + "d_0_am__U126":{ "modref":"corebit.and" }, - "d_0_am__U137":{ + "d_0_am__U127":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2295,10 +2295,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U138":{ + "d_1_am__U128":{ "modref":"corebit.and" }, - "d_1_am__U139":{ + "d_1_am__U129":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2332,7 +2332,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U140":{ + "d_2_am__U130":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2407,11 +2407,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U133.out"], - ["d_1_inc.in1","_U133.out"], - ["d_2_inc.in1","_U133.out"], - ["d_3_inc.in1","_U133.out"], - ["cmp_time.in1","_U134.out"], + ["d_0_inc.in1","_U123.out"], + ["d_1_inc.in1","_U123.out"], + ["d_2_inc.in1","_U123.out"], + ["d_3_inc.in1","_U123.out"], + ["cmp_time.in1","_U124.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2426,13 +2426,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U135.in0"], - ["d_1_at_max.out","d_0_am__U135.in1"], - ["d_0_am__U136.in0","d_0_am__U135.out"], - ["d_2_at_max.out","d_0_am__U136.in1"], - ["d_0_am__U137.in0","d_0_am__U136.out"], - ["d_3_at_max.out","d_0_am__U137.in1"], - ["d_0_next_value.sel","d_0_am__U137.out"], + ["true.out","d_0_am__U125.in0"], + ["d_1_at_max.out","d_0_am__U125.in1"], + ["d_0_am__U126.in0","d_0_am__U125.out"], + ["d_2_at_max.out","d_0_am__U126.in1"], + ["d_0_am__U127.in0","d_0_am__U126.out"], + ["d_3_at_max.out","d_0_am__U127.in1"], + ["d_0_next_value.sel","d_0_am__U127.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2445,11 +2445,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U138.in0"], - ["d_2_at_max.out","d_1_am__U138.in1"], - ["d_1_am__U139.in0","d_1_am__U138.out"], - ["d_3_at_max.out","d_1_am__U139.in1"], - ["d_1_next_value.sel","d_1_am__U139.out"], + ["true.out","d_1_am__U128.in0"], + ["d_2_at_max.out","d_1_am__U128.in1"], + ["d_1_am__U129.in0","d_1_am__U128.out"], + ["d_3_at_max.out","d_1_am__U129.in1"], + ["d_1_next_value.sel","d_1_am__U129.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2462,9 +2462,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U140.in0"], - ["d_3_at_max.out","d_2_am__U140.in1"], - ["d_2_next_value.sel","d_2_am__U140.out"], + ["true.out","d_2_am__U130.in0"], + ["d_3_at_max.out","d_2_am__U130.in1"], + ["d_2_next_value.sel","d_2_am__U130.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2492,7 +2492,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U157":{ + "affine_controller__U147":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2500,18 +2500,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U178":{ + "_U168":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U179":{ + "_U169":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U158" + "modref":"global.aff__U148" }, "cmp_time":{ "genref":"coreir.eq", @@ -2521,19 +2521,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U180":{ + "d_0_am__U170":{ "modref":"corebit.and" }, - "d_0_am__U181":{ + "d_0_am__U171":{ "modref":"corebit.and" }, - "d_0_am__U182":{ + "d_0_am__U172":{ "modref":"corebit.and" }, - "d_0_am__U183":{ + "d_0_am__U173":{ "modref":"corebit.and" }, - "d_0_am__U184":{ + "d_0_am__U174":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2567,16 +2567,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U185":{ + "d_1_am__U175":{ "modref":"corebit.and" }, - "d_1_am__U186":{ + "d_1_am__U176":{ "modref":"corebit.and" }, - "d_1_am__U187":{ + "d_1_am__U177":{ "modref":"corebit.and" }, - "d_1_am__U188":{ + "d_1_am__U178":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2610,13 +2610,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U189":{ + "d_2_am__U179":{ "modref":"corebit.and" }, - "d_2_am__U190":{ + "d_2_am__U180":{ "modref":"corebit.and" }, - "d_2_am__U191":{ + "d_2_am__U181":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2650,10 +2650,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U192":{ + "d_3_am__U182":{ "modref":"corebit.and" }, - "d_3_am__U193":{ + "d_3_am__U183":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2687,7 +2687,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U194":{ + "d_4_am__U184":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2762,13 +2762,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U178.out"], - ["d_1_inc.in1","_U178.out"], - ["d_2_inc.in1","_U178.out"], - ["d_3_inc.in1","_U178.out"], - ["d_4_inc.in1","_U178.out"], - ["d_5_inc.in1","_U178.out"], - ["cmp_time.in1","_U179.out"], + ["d_0_inc.in1","_U168.out"], + ["d_1_inc.in1","_U168.out"], + ["d_2_inc.in1","_U168.out"], + ["d_3_inc.in1","_U168.out"], + ["d_4_inc.in1","_U168.out"], + ["d_5_inc.in1","_U168.out"], + ["cmp_time.in1","_U169.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2787,17 +2787,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U180.in0"], - ["d_1_at_max.out","d_0_am__U180.in1"], - ["d_0_am__U181.in0","d_0_am__U180.out"], - ["d_2_at_max.out","d_0_am__U181.in1"], - ["d_0_am__U182.in0","d_0_am__U181.out"], - ["d_3_at_max.out","d_0_am__U182.in1"], - ["d_0_am__U183.in0","d_0_am__U182.out"], - ["d_4_at_max.out","d_0_am__U183.in1"], - ["d_0_am__U184.in0","d_0_am__U183.out"], - ["d_5_at_max.out","d_0_am__U184.in1"], - ["d_0_next_value.sel","d_0_am__U184.out"], + ["true.out","d_0_am__U170.in0"], + ["d_1_at_max.out","d_0_am__U170.in1"], + ["d_0_am__U171.in0","d_0_am__U170.out"], + ["d_2_at_max.out","d_0_am__U171.in1"], + ["d_0_am__U172.in0","d_0_am__U171.out"], + ["d_3_at_max.out","d_0_am__U172.in1"], + ["d_0_am__U173.in0","d_0_am__U172.out"], + ["d_4_at_max.out","d_0_am__U173.in1"], + ["d_0_am__U174.in0","d_0_am__U173.out"], + ["d_5_at_max.out","d_0_am__U174.in1"], + ["d_0_next_value.sel","d_0_am__U174.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2810,15 +2810,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U185.in0"], - ["d_2_at_max.out","d_1_am__U185.in1"], - ["d_1_am__U186.in0","d_1_am__U185.out"], - ["d_3_at_max.out","d_1_am__U186.in1"], - ["d_1_am__U187.in0","d_1_am__U186.out"], - ["d_4_at_max.out","d_1_am__U187.in1"], - ["d_1_am__U188.in0","d_1_am__U187.out"], - ["d_5_at_max.out","d_1_am__U188.in1"], - ["d_1_next_value.sel","d_1_am__U188.out"], + ["true.out","d_1_am__U175.in0"], + ["d_2_at_max.out","d_1_am__U175.in1"], + ["d_1_am__U176.in0","d_1_am__U175.out"], + ["d_3_at_max.out","d_1_am__U176.in1"], + ["d_1_am__U177.in0","d_1_am__U176.out"], + ["d_4_at_max.out","d_1_am__U177.in1"], + ["d_1_am__U178.in0","d_1_am__U177.out"], + ["d_5_at_max.out","d_1_am__U178.in1"], + ["d_1_next_value.sel","d_1_am__U178.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2831,13 +2831,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U189.in0"], - ["d_3_at_max.out","d_2_am__U189.in1"], - ["d_2_am__U190.in0","d_2_am__U189.out"], - ["d_4_at_max.out","d_2_am__U190.in1"], - ["d_2_am__U191.in0","d_2_am__U190.out"], - ["d_5_at_max.out","d_2_am__U191.in1"], - ["d_2_next_value.sel","d_2_am__U191.out"], + ["true.out","d_2_am__U179.in0"], + ["d_3_at_max.out","d_2_am__U179.in1"], + ["d_2_am__U180.in0","d_2_am__U179.out"], + ["d_4_at_max.out","d_2_am__U180.in1"], + ["d_2_am__U181.in0","d_2_am__U180.out"], + ["d_5_at_max.out","d_2_am__U181.in1"], + ["d_2_next_value.sel","d_2_am__U181.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2850,11 +2850,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U192.in0"], - ["d_4_at_max.out","d_3_am__U192.in1"], - ["d_3_am__U193.in0","d_3_am__U192.out"], - ["d_5_at_max.out","d_3_am__U193.in1"], - ["d_3_next_value.sel","d_3_am__U193.out"], + ["true.out","d_3_am__U182.in0"], + ["d_4_at_max.out","d_3_am__U182.in1"], + ["d_3_am__U183.in0","d_3_am__U182.out"], + ["d_5_at_max.out","d_3_am__U183.in1"], + ["d_3_next_value.sel","d_3_am__U183.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2867,9 +2867,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U194.in0"], - ["d_5_at_max.out","d_4_am__U194.in1"], - ["d_4_next_value.sel","d_4_am__U194.out"], + ["true.out","d_4_am__U184.in0"], + ["d_5_at_max.out","d_4_am__U184.in1"], + ["d_4_next_value.sel","d_4_am__U184.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -2889,281 +2889,15 @@ ["d_5_next_value_at_max.in0","d_5_inc.out"], ["d_5_next_value_at_max.in1","d_5_min.out"], ["d_5_reg.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg.in","d_5_next_value.out"], - ["true.out","d_5_next_value.sel"], - ["self.clk","d_5_reg.clk"], - ["self.rst_n","d_5_reg.clr"], - ["self.d.5","d_5_reg.out"] - ] - }, - "affine_controller__U17":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U32":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U33":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U18" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U34":{ - "modref":"corebit.and" - }, - "d_0_am__U35":{ - "modref":"corebit.and" - }, - "d_0_am__U36":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U37":{ - "modref":"corebit.and" - }, - "d_1_am__U38":{ - "modref":"corebit.and" - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U39":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U32.out"], - ["d_2_inc.in1","_U32.out"], - ["d_3_inc.in1","_U32.out"], - ["cmp_time.in1","_U33.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U34.in0"], - ["d_1_at_max.out","d_0_am__U34.in1"], - ["d_0_am__U35.in0","d_0_am__U34.out"], - ["d_2_at_max.out","d_0_am__U35.in1"], - ["d_0_am__U36.in0","d_0_am__U35.out"], - ["d_3_at_max.out","d_0_am__U36.in1"], - ["d_0_next_value.sel","d_0_am__U36.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U37.in0"], - ["d_2_at_max.out","d_1_am__U37.in1"], - ["d_1_am__U38.in0","d_1_am__U37.out"], - ["d_3_at_max.out","d_1_am__U38.in1"], - ["d_1_next_value.sel","d_1_am__U38.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U39.in0"], - ["d_3_at_max.out","d_2_am__U39.in1"], - ["d_2_next_value.sel","d_2_am__U39.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg.in","d_5_next_value.out"], + ["true.out","d_5_next_value.sel"], + ["self.clk","d_5_reg.clk"], + ["self.rst_n","d_5_reg.clr"], + ["self.d.5","d_5_reg.out"] ] }, - "affine_controller__U347":{ + "affine_controller__U272":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3171,18 +2905,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U365":{ + "_U290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U366":{ + "_U291":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U348" + "modref":"global.aff__U273" }, "cmp_time":{ "genref":"coreir.eq", @@ -3192,16 +2926,16 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U367":{ + "d_0_am__U292":{ "modref":"corebit.and" }, - "d_0_am__U368":{ + "d_0_am__U293":{ "modref":"corebit.and" }, - "d_0_am__U369":{ + "d_0_am__U294":{ "modref":"corebit.and" }, - "d_0_am__U370":{ + "d_0_am__U295":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3235,13 +2969,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U371":{ + "d_1_am__U296":{ "modref":"corebit.and" }, - "d_1_am__U372":{ + "d_1_am__U297":{ "modref":"corebit.and" }, - "d_1_am__U373":{ + "d_1_am__U298":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -3275,10 +3009,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U374":{ + "d_2_am__U299":{ "modref":"corebit.and" }, - "d_2_am__U375":{ + "d_2_am__U300":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -3312,7 +3046,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U376":{ + "d_3_am__U301":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -3387,12 +3121,12 @@ } }, "connections":[ - ["d_0_inc.in1","_U365.out"], - ["d_1_inc.in1","_U365.out"], - ["d_2_inc.in1","_U365.out"], - ["d_3_inc.in1","_U365.out"], - ["d_4_inc.in1","_U365.out"], - ["cmp_time.in1","_U366.out"], + ["d_0_inc.in1","_U290.out"], + ["d_1_inc.in1","_U290.out"], + ["d_2_inc.in1","_U290.out"], + ["d_3_inc.in1","_U290.out"], + ["d_4_inc.in1","_U290.out"], + ["cmp_time.in1","_U291.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3409,15 +3143,15 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U367.in0"], - ["d_1_at_max.out","d_0_am__U367.in1"], - ["d_0_am__U368.in0","d_0_am__U367.out"], - ["d_2_at_max.out","d_0_am__U368.in1"], - ["d_0_am__U369.in0","d_0_am__U368.out"], - ["d_3_at_max.out","d_0_am__U369.in1"], - ["d_0_am__U370.in0","d_0_am__U369.out"], - ["d_4_at_max.out","d_0_am__U370.in1"], - ["d_0_next_value.sel","d_0_am__U370.out"], + ["true.out","d_0_am__U292.in0"], + ["d_1_at_max.out","d_0_am__U292.in1"], + ["d_0_am__U293.in0","d_0_am__U292.out"], + ["d_2_at_max.out","d_0_am__U293.in1"], + ["d_0_am__U294.in0","d_0_am__U293.out"], + ["d_3_at_max.out","d_0_am__U294.in1"], + ["d_0_am__U295.in0","d_0_am__U294.out"], + ["d_4_at_max.out","d_0_am__U295.in1"], + ["d_0_next_value.sel","d_0_am__U295.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3430,13 +3164,13 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U371.in0"], - ["d_2_at_max.out","d_1_am__U371.in1"], - ["d_1_am__U372.in0","d_1_am__U371.out"], - ["d_3_at_max.out","d_1_am__U372.in1"], - ["d_1_am__U373.in0","d_1_am__U372.out"], - ["d_4_at_max.out","d_1_am__U373.in1"], - ["d_1_next_value.sel","d_1_am__U373.out"], + ["true.out","d_1_am__U296.in0"], + ["d_2_at_max.out","d_1_am__U296.in1"], + ["d_1_am__U297.in0","d_1_am__U296.out"], + ["d_3_at_max.out","d_1_am__U297.in1"], + ["d_1_am__U298.in0","d_1_am__U297.out"], + ["d_4_at_max.out","d_1_am__U298.in1"], + ["d_1_next_value.sel","d_1_am__U298.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3449,11 +3183,11 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U374.in0"], - ["d_3_at_max.out","d_2_am__U374.in1"], - ["d_2_am__U375.in0","d_2_am__U374.out"], - ["d_4_at_max.out","d_2_am__U375.in1"], - ["d_2_next_value.sel","d_2_am__U375.out"], + ["true.out","d_2_am__U299.in0"], + ["d_3_at_max.out","d_2_am__U299.in1"], + ["d_2_am__U300.in0","d_2_am__U299.out"], + ["d_4_at_max.out","d_2_am__U300.in1"], + ["d_2_next_value.sel","d_2_am__U300.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3466,9 +3200,9 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U376.in0"], - ["d_4_at_max.out","d_3_am__U376.in1"], - ["d_3_next_value.sel","d_3_am__U376.out"], + ["true.out","d_3_am__U301.in0"], + ["d_4_at_max.out","d_3_am__U301.in1"], + ["d_3_next_value.sel","d_3_am__U301.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3496,7 +3230,7 @@ ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U396":{ + "affine_controller__U321":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3504,18 +3238,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U423":{ + "_U348":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U424":{ + "_U349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U397" + "modref":"global.aff__U322" }, "cmp_time":{ "genref":"coreir.eq", @@ -3525,25 +3259,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U425":{ + "d_0_am__U350":{ "modref":"corebit.and" }, - "d_0_am__U426":{ + "d_0_am__U351":{ "modref":"corebit.and" }, - "d_0_am__U427":{ + "d_0_am__U352":{ "modref":"corebit.and" }, - "d_0_am__U428":{ + "d_0_am__U353":{ "modref":"corebit.and" }, - "d_0_am__U429":{ + "d_0_am__U354":{ "modref":"corebit.and" }, - "d_0_am__U430":{ + "d_0_am__U355":{ "modref":"corebit.and" }, - "d_0_am__U431":{ + "d_0_am__U356":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3577,22 +3311,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U432":{ + "d_1_am__U357":{ "modref":"corebit.and" }, - "d_1_am__U433":{ + "d_1_am__U358":{ "modref":"corebit.and" }, - "d_1_am__U434":{ + "d_1_am__U359":{ "modref":"corebit.and" }, - "d_1_am__U435":{ + "d_1_am__U360":{ "modref":"corebit.and" }, - "d_1_am__U436":{ + "d_1_am__U361":{ "modref":"corebit.and" }, - "d_1_am__U437":{ + "d_1_am__U362":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -3626,19 +3360,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U438":{ + "d_2_am__U363":{ "modref":"corebit.and" }, - "d_2_am__U439":{ + "d_2_am__U364":{ "modref":"corebit.and" }, - "d_2_am__U440":{ + "d_2_am__U365":{ "modref":"corebit.and" }, - "d_2_am__U441":{ + "d_2_am__U366":{ "modref":"corebit.and" }, - "d_2_am__U442":{ + "d_2_am__U367":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -3672,16 +3406,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U443":{ + "d_3_am__U368":{ "modref":"corebit.and" }, - "d_3_am__U444":{ + "d_3_am__U369":{ "modref":"corebit.and" }, - "d_3_am__U445":{ + "d_3_am__U370":{ "modref":"corebit.and" }, - "d_3_am__U446":{ + "d_3_am__U371":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -3715,13 +3449,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U447":{ + "d_4_am__U372":{ "modref":"corebit.and" }, - "d_4_am__U448":{ + "d_4_am__U373":{ "modref":"corebit.and" }, - "d_4_am__U449":{ + "d_4_am__U374":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -3755,10 +3489,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U450":{ + "d_5_am__U375":{ "modref":"corebit.and" }, - "d_5_am__U451":{ + "d_5_am__U376":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -3792,7 +3526,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U452":{ + "d_6_am__U377":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -3867,15 +3601,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U423.out"], - ["d_1_inc.in1","_U423.out"], - ["d_2_inc.in1","_U423.out"], - ["d_3_inc.in1","_U423.out"], - ["d_4_inc.in1","_U423.out"], - ["d_5_inc.in1","_U423.out"], - ["d_6_inc.in1","_U423.out"], - ["d_7_inc.in1","_U423.out"], - ["cmp_time.in1","_U424.out"], + ["d_0_inc.in1","_U348.out"], + ["d_1_inc.in1","_U348.out"], + ["d_2_inc.in1","_U348.out"], + ["d_3_inc.in1","_U348.out"], + ["d_4_inc.in1","_U348.out"], + ["d_5_inc.in1","_U348.out"], + ["d_6_inc.in1","_U348.out"], + ["d_7_inc.in1","_U348.out"], + ["cmp_time.in1","_U349.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3898,21 +3632,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U425.in0"], - ["d_1_at_max.out","d_0_am__U425.in1"], - ["d_0_am__U426.in0","d_0_am__U425.out"], - ["d_2_at_max.out","d_0_am__U426.in1"], - ["d_0_am__U427.in0","d_0_am__U426.out"], - ["d_3_at_max.out","d_0_am__U427.in1"], - ["d_0_am__U428.in0","d_0_am__U427.out"], - ["d_4_at_max.out","d_0_am__U428.in1"], - ["d_0_am__U429.in0","d_0_am__U428.out"], - ["d_5_at_max.out","d_0_am__U429.in1"], - ["d_0_am__U430.in0","d_0_am__U429.out"], - ["d_6_at_max.out","d_0_am__U430.in1"], - ["d_0_am__U431.in0","d_0_am__U430.out"], - ["d_7_at_max.out","d_0_am__U431.in1"], - ["d_0_next_value.sel","d_0_am__U431.out"], + ["true.out","d_0_am__U350.in0"], + ["d_1_at_max.out","d_0_am__U350.in1"], + ["d_0_am__U351.in0","d_0_am__U350.out"], + ["d_2_at_max.out","d_0_am__U351.in1"], + ["d_0_am__U352.in0","d_0_am__U351.out"], + ["d_3_at_max.out","d_0_am__U352.in1"], + ["d_0_am__U353.in0","d_0_am__U352.out"], + ["d_4_at_max.out","d_0_am__U353.in1"], + ["d_0_am__U354.in0","d_0_am__U353.out"], + ["d_5_at_max.out","d_0_am__U354.in1"], + ["d_0_am__U355.in0","d_0_am__U354.out"], + ["d_6_at_max.out","d_0_am__U355.in1"], + ["d_0_am__U356.in0","d_0_am__U355.out"], + ["d_7_at_max.out","d_0_am__U356.in1"], + ["d_0_next_value.sel","d_0_am__U356.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3925,19 +3659,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U432.in0"], - ["d_2_at_max.out","d_1_am__U432.in1"], - ["d_1_am__U433.in0","d_1_am__U432.out"], - ["d_3_at_max.out","d_1_am__U433.in1"], - ["d_1_am__U434.in0","d_1_am__U433.out"], - ["d_4_at_max.out","d_1_am__U434.in1"], - ["d_1_am__U435.in0","d_1_am__U434.out"], - ["d_5_at_max.out","d_1_am__U435.in1"], - ["d_1_am__U436.in0","d_1_am__U435.out"], - ["d_6_at_max.out","d_1_am__U436.in1"], - ["d_1_am__U437.in0","d_1_am__U436.out"], - ["d_7_at_max.out","d_1_am__U437.in1"], - ["d_1_next_value.sel","d_1_am__U437.out"], + ["true.out","d_1_am__U357.in0"], + ["d_2_at_max.out","d_1_am__U357.in1"], + ["d_1_am__U358.in0","d_1_am__U357.out"], + ["d_3_at_max.out","d_1_am__U358.in1"], + ["d_1_am__U359.in0","d_1_am__U358.out"], + ["d_4_at_max.out","d_1_am__U359.in1"], + ["d_1_am__U360.in0","d_1_am__U359.out"], + ["d_5_at_max.out","d_1_am__U360.in1"], + ["d_1_am__U361.in0","d_1_am__U360.out"], + ["d_6_at_max.out","d_1_am__U361.in1"], + ["d_1_am__U362.in0","d_1_am__U361.out"], + ["d_7_at_max.out","d_1_am__U362.in1"], + ["d_1_next_value.sel","d_1_am__U362.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3950,17 +3684,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U438.in0"], - ["d_3_at_max.out","d_2_am__U438.in1"], - ["d_2_am__U439.in0","d_2_am__U438.out"], - ["d_4_at_max.out","d_2_am__U439.in1"], - ["d_2_am__U440.in0","d_2_am__U439.out"], - ["d_5_at_max.out","d_2_am__U440.in1"], - ["d_2_am__U441.in0","d_2_am__U440.out"], - ["d_6_at_max.out","d_2_am__U441.in1"], - ["d_2_am__U442.in0","d_2_am__U441.out"], - ["d_7_at_max.out","d_2_am__U442.in1"], - ["d_2_next_value.sel","d_2_am__U442.out"], + ["true.out","d_2_am__U363.in0"], + ["d_3_at_max.out","d_2_am__U363.in1"], + ["d_2_am__U364.in0","d_2_am__U363.out"], + ["d_4_at_max.out","d_2_am__U364.in1"], + ["d_2_am__U365.in0","d_2_am__U364.out"], + ["d_5_at_max.out","d_2_am__U365.in1"], + ["d_2_am__U366.in0","d_2_am__U365.out"], + ["d_6_at_max.out","d_2_am__U366.in1"], + ["d_2_am__U367.in0","d_2_am__U366.out"], + ["d_7_at_max.out","d_2_am__U367.in1"], + ["d_2_next_value.sel","d_2_am__U367.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3973,15 +3707,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U443.in0"], - ["d_4_at_max.out","d_3_am__U443.in1"], - ["d_3_am__U444.in0","d_3_am__U443.out"], - ["d_5_at_max.out","d_3_am__U444.in1"], - ["d_3_am__U445.in0","d_3_am__U444.out"], - ["d_6_at_max.out","d_3_am__U445.in1"], - ["d_3_am__U446.in0","d_3_am__U445.out"], - ["d_7_at_max.out","d_3_am__U446.in1"], - ["d_3_next_value.sel","d_3_am__U446.out"], + ["true.out","d_3_am__U368.in0"], + ["d_4_at_max.out","d_3_am__U368.in1"], + ["d_3_am__U369.in0","d_3_am__U368.out"], + ["d_5_at_max.out","d_3_am__U369.in1"], + ["d_3_am__U370.in0","d_3_am__U369.out"], + ["d_6_at_max.out","d_3_am__U370.in1"], + ["d_3_am__U371.in0","d_3_am__U370.out"], + ["d_7_at_max.out","d_3_am__U371.in1"], + ["d_3_next_value.sel","d_3_am__U371.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3994,13 +3728,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U447.in0"], - ["d_5_at_max.out","d_4_am__U447.in1"], - ["d_4_am__U448.in0","d_4_am__U447.out"], - ["d_6_at_max.out","d_4_am__U448.in1"], - ["d_4_am__U449.in0","d_4_am__U448.out"], - ["d_7_at_max.out","d_4_am__U449.in1"], - ["d_4_next_value.sel","d_4_am__U449.out"], + ["true.out","d_4_am__U372.in0"], + ["d_5_at_max.out","d_4_am__U372.in1"], + ["d_4_am__U373.in0","d_4_am__U372.out"], + ["d_6_at_max.out","d_4_am__U373.in1"], + ["d_4_am__U374.in0","d_4_am__U373.out"], + ["d_7_at_max.out","d_4_am__U374.in1"], + ["d_4_next_value.sel","d_4_am__U374.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -4013,11 +3747,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U450.in0"], - ["d_6_at_max.out","d_5_am__U450.in1"], - ["d_5_am__U451.in0","d_5_am__U450.out"], - ["d_7_at_max.out","d_5_am__U451.in1"], - ["d_5_next_value.sel","d_5_am__U451.out"], + ["true.out","d_5_am__U375.in0"], + ["d_6_at_max.out","d_5_am__U375.in1"], + ["d_5_am__U376.in0","d_5_am__U375.out"], + ["d_7_at_max.out","d_5_am__U376.in1"], + ["d_5_next_value.sel","d_5_am__U376.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -4030,9 +3764,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U452.in0"], - ["d_7_at_max.out","d_6_am__U452.in1"], - ["d_6_next_value.sel","d_6_am__U452.out"], + ["true.out","d_6_am__U377.in0"], + ["d_7_at_max.out","d_6_am__U377.in1"], + ["d_6_next_value.sel","d_6_am__U377.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -4060,7 +3794,7 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U483":{ + "affine_controller__U407":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4068,18 +3802,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U501":{ + "_U425":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U502":{ + "_U426":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U484" + "modref":"global.aff__U408" }, "cmp_time":{ "genref":"coreir.eq", @@ -4089,16 +3823,16 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U503":{ + "d_0_am__U427":{ "modref":"corebit.and" }, - "d_0_am__U504":{ + "d_0_am__U428":{ "modref":"corebit.and" }, - "d_0_am__U505":{ + "d_0_am__U429":{ "modref":"corebit.and" }, - "d_0_am__U506":{ + "d_0_am__U430":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4132,13 +3866,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U507":{ + "d_1_am__U431":{ "modref":"corebit.and" }, - "d_1_am__U508":{ + "d_1_am__U432":{ "modref":"corebit.and" }, - "d_1_am__U509":{ + "d_1_am__U433":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -4172,10 +3906,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U510":{ + "d_2_am__U434":{ "modref":"corebit.and" }, - "d_2_am__U511":{ + "d_2_am__U435":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -4209,7 +3943,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U512":{ + "d_3_am__U436":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -4284,12 +4018,12 @@ } }, "connections":[ - ["d_0_inc.in1","_U501.out"], - ["d_1_inc.in1","_U501.out"], - ["d_2_inc.in1","_U501.out"], - ["d_3_inc.in1","_U501.out"], - ["d_4_inc.in1","_U501.out"], - ["cmp_time.in1","_U502.out"], + ["d_0_inc.in1","_U425.out"], + ["d_1_inc.in1","_U425.out"], + ["d_2_inc.in1","_U425.out"], + ["d_3_inc.in1","_U425.out"], + ["d_4_inc.in1","_U425.out"], + ["cmp_time.in1","_U426.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -4306,15 +4040,15 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U503.in0"], - ["d_1_at_max.out","d_0_am__U503.in1"], - ["d_0_am__U504.in0","d_0_am__U503.out"], - ["d_2_at_max.out","d_0_am__U504.in1"], - ["d_0_am__U505.in0","d_0_am__U504.out"], - ["d_3_at_max.out","d_0_am__U505.in1"], - ["d_0_am__U506.in0","d_0_am__U505.out"], - ["d_4_at_max.out","d_0_am__U506.in1"], - ["d_0_next_value.sel","d_0_am__U506.out"], + ["true.out","d_0_am__U427.in0"], + ["d_1_at_max.out","d_0_am__U427.in1"], + ["d_0_am__U428.in0","d_0_am__U427.out"], + ["d_2_at_max.out","d_0_am__U428.in1"], + ["d_0_am__U429.in0","d_0_am__U428.out"], + ["d_3_at_max.out","d_0_am__U429.in1"], + ["d_0_am__U430.in0","d_0_am__U429.out"], + ["d_4_at_max.out","d_0_am__U430.in1"], + ["d_0_next_value.sel","d_0_am__U430.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4327,13 +4061,13 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U507.in0"], - ["d_2_at_max.out","d_1_am__U507.in1"], - ["d_1_am__U508.in0","d_1_am__U507.out"], - ["d_3_at_max.out","d_1_am__U508.in1"], - ["d_1_am__U509.in0","d_1_am__U508.out"], - ["d_4_at_max.out","d_1_am__U509.in1"], - ["d_1_next_value.sel","d_1_am__U509.out"], + ["true.out","d_1_am__U431.in0"], + ["d_2_at_max.out","d_1_am__U431.in1"], + ["d_1_am__U432.in0","d_1_am__U431.out"], + ["d_3_at_max.out","d_1_am__U432.in1"], + ["d_1_am__U433.in0","d_1_am__U432.out"], + ["d_4_at_max.out","d_1_am__U433.in1"], + ["d_1_next_value.sel","d_1_am__U433.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4346,11 +4080,11 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U510.in0"], - ["d_3_at_max.out","d_2_am__U510.in1"], - ["d_2_am__U511.in0","d_2_am__U510.out"], - ["d_4_at_max.out","d_2_am__U511.in1"], - ["d_2_next_value.sel","d_2_am__U511.out"], + ["true.out","d_2_am__U434.in0"], + ["d_3_at_max.out","d_2_am__U434.in1"], + ["d_2_am__U435.in0","d_2_am__U434.out"], + ["d_4_at_max.out","d_2_am__U435.in1"], + ["d_2_next_value.sel","d_2_am__U435.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4363,9 +4097,9 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U512.in0"], - ["d_4_at_max.out","d_3_am__U512.in1"], - ["d_3_next_value.sel","d_3_am__U512.out"], + ["true.out","d_3_am__U436.in0"], + ["d_4_at_max.out","d_3_am__U436.in1"], + ["d_3_next_value.sel","d_3_am__U436.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4393,7 +4127,7 @@ ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U532":{ + "affine_controller__U456":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4401,18 +4135,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U559":{ + "_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U560":{ + "_U484":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U533" + "modref":"global.aff__U457" }, "cmp_time":{ "genref":"coreir.eq", @@ -4422,25 +4156,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U561":{ + "d_0_am__U485":{ "modref":"corebit.and" }, - "d_0_am__U562":{ + "d_0_am__U486":{ "modref":"corebit.and" }, - "d_0_am__U563":{ + "d_0_am__U487":{ "modref":"corebit.and" }, - "d_0_am__U564":{ + "d_0_am__U488":{ "modref":"corebit.and" }, - "d_0_am__U565":{ + "d_0_am__U489":{ "modref":"corebit.and" }, - "d_0_am__U566":{ + "d_0_am__U490":{ "modref":"corebit.and" }, - "d_0_am__U567":{ + "d_0_am__U491":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4474,22 +4208,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U568":{ + "d_1_am__U492":{ "modref":"corebit.and" }, - "d_1_am__U569":{ + "d_1_am__U493":{ "modref":"corebit.and" }, - "d_1_am__U570":{ + "d_1_am__U494":{ "modref":"corebit.and" }, - "d_1_am__U571":{ + "d_1_am__U495":{ "modref":"corebit.and" }, - "d_1_am__U572":{ + "d_1_am__U496":{ "modref":"corebit.and" }, - "d_1_am__U573":{ + "d_1_am__U497":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -4523,19 +4257,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U574":{ + "d_2_am__U498":{ "modref":"corebit.and" }, - "d_2_am__U575":{ + "d_2_am__U499":{ "modref":"corebit.and" }, - "d_2_am__U576":{ + "d_2_am__U500":{ "modref":"corebit.and" }, - "d_2_am__U577":{ + "d_2_am__U501":{ "modref":"corebit.and" }, - "d_2_am__U578":{ + "d_2_am__U502":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -4569,16 +4303,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U579":{ + "d_3_am__U503":{ "modref":"corebit.and" }, - "d_3_am__U580":{ + "d_3_am__U504":{ "modref":"corebit.and" }, - "d_3_am__U581":{ + "d_3_am__U505":{ "modref":"corebit.and" }, - "d_3_am__U582":{ + "d_3_am__U506":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -4612,13 +4346,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U583":{ + "d_4_am__U507":{ "modref":"corebit.and" }, - "d_4_am__U584":{ + "d_4_am__U508":{ "modref":"corebit.and" }, - "d_4_am__U585":{ + "d_4_am__U509":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -4652,10 +4386,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U586":{ + "d_5_am__U510":{ "modref":"corebit.and" }, - "d_5_am__U587":{ + "d_5_am__U511":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -4689,7 +4423,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U588":{ + "d_6_am__U512":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -4764,15 +4498,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U559.out"], - ["d_1_inc.in1","_U559.out"], - ["d_2_inc.in1","_U559.out"], - ["d_3_inc.in1","_U559.out"], - ["d_4_inc.in1","_U559.out"], - ["d_5_inc.in1","_U559.out"], - ["d_6_inc.in1","_U559.out"], - ["d_7_inc.in1","_U559.out"], - ["cmp_time.in1","_U560.out"], + ["d_0_inc.in1","_U483.out"], + ["d_1_inc.in1","_U483.out"], + ["d_2_inc.in1","_U483.out"], + ["d_3_inc.in1","_U483.out"], + ["d_4_inc.in1","_U483.out"], + ["d_5_inc.in1","_U483.out"], + ["d_6_inc.in1","_U483.out"], + ["d_7_inc.in1","_U483.out"], + ["cmp_time.in1","_U484.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -4795,21 +4529,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U561.in0"], - ["d_1_at_max.out","d_0_am__U561.in1"], - ["d_0_am__U562.in0","d_0_am__U561.out"], - ["d_2_at_max.out","d_0_am__U562.in1"], - ["d_0_am__U563.in0","d_0_am__U562.out"], - ["d_3_at_max.out","d_0_am__U563.in1"], - ["d_0_am__U564.in0","d_0_am__U563.out"], - ["d_4_at_max.out","d_0_am__U564.in1"], - ["d_0_am__U565.in0","d_0_am__U564.out"], - ["d_5_at_max.out","d_0_am__U565.in1"], - ["d_0_am__U566.in0","d_0_am__U565.out"], - ["d_6_at_max.out","d_0_am__U566.in1"], - ["d_0_am__U567.in0","d_0_am__U566.out"], - ["d_7_at_max.out","d_0_am__U567.in1"], - ["d_0_next_value.sel","d_0_am__U567.out"], + ["true.out","d_0_am__U485.in0"], + ["d_1_at_max.out","d_0_am__U485.in1"], + ["d_0_am__U486.in0","d_0_am__U485.out"], + ["d_2_at_max.out","d_0_am__U486.in1"], + ["d_0_am__U487.in0","d_0_am__U486.out"], + ["d_3_at_max.out","d_0_am__U487.in1"], + ["d_0_am__U488.in0","d_0_am__U487.out"], + ["d_4_at_max.out","d_0_am__U488.in1"], + ["d_0_am__U489.in0","d_0_am__U488.out"], + ["d_5_at_max.out","d_0_am__U489.in1"], + ["d_0_am__U490.in0","d_0_am__U489.out"], + ["d_6_at_max.out","d_0_am__U490.in1"], + ["d_0_am__U491.in0","d_0_am__U490.out"], + ["d_7_at_max.out","d_0_am__U491.in1"], + ["d_0_next_value.sel","d_0_am__U491.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4822,19 +4556,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U568.in0"], - ["d_2_at_max.out","d_1_am__U568.in1"], - ["d_1_am__U569.in0","d_1_am__U568.out"], - ["d_3_at_max.out","d_1_am__U569.in1"], - ["d_1_am__U570.in0","d_1_am__U569.out"], - ["d_4_at_max.out","d_1_am__U570.in1"], - ["d_1_am__U571.in0","d_1_am__U570.out"], - ["d_5_at_max.out","d_1_am__U571.in1"], - ["d_1_am__U572.in0","d_1_am__U571.out"], - ["d_6_at_max.out","d_1_am__U572.in1"], - ["d_1_am__U573.in0","d_1_am__U572.out"], - ["d_7_at_max.out","d_1_am__U573.in1"], - ["d_1_next_value.sel","d_1_am__U573.out"], + ["true.out","d_1_am__U492.in0"], + ["d_2_at_max.out","d_1_am__U492.in1"], + ["d_1_am__U493.in0","d_1_am__U492.out"], + ["d_3_at_max.out","d_1_am__U493.in1"], + ["d_1_am__U494.in0","d_1_am__U493.out"], + ["d_4_at_max.out","d_1_am__U494.in1"], + ["d_1_am__U495.in0","d_1_am__U494.out"], + ["d_5_at_max.out","d_1_am__U495.in1"], + ["d_1_am__U496.in0","d_1_am__U495.out"], + ["d_6_at_max.out","d_1_am__U496.in1"], + ["d_1_am__U497.in0","d_1_am__U496.out"], + ["d_7_at_max.out","d_1_am__U497.in1"], + ["d_1_next_value.sel","d_1_am__U497.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4847,17 +4581,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U574.in0"], - ["d_3_at_max.out","d_2_am__U574.in1"], - ["d_2_am__U575.in0","d_2_am__U574.out"], - ["d_4_at_max.out","d_2_am__U575.in1"], - ["d_2_am__U576.in0","d_2_am__U575.out"], - ["d_5_at_max.out","d_2_am__U576.in1"], - ["d_2_am__U577.in0","d_2_am__U576.out"], - ["d_6_at_max.out","d_2_am__U577.in1"], - ["d_2_am__U578.in0","d_2_am__U577.out"], - ["d_7_at_max.out","d_2_am__U578.in1"], - ["d_2_next_value.sel","d_2_am__U578.out"], + ["true.out","d_2_am__U498.in0"], + ["d_3_at_max.out","d_2_am__U498.in1"], + ["d_2_am__U499.in0","d_2_am__U498.out"], + ["d_4_at_max.out","d_2_am__U499.in1"], + ["d_2_am__U500.in0","d_2_am__U499.out"], + ["d_5_at_max.out","d_2_am__U500.in1"], + ["d_2_am__U501.in0","d_2_am__U500.out"], + ["d_6_at_max.out","d_2_am__U501.in1"], + ["d_2_am__U502.in0","d_2_am__U501.out"], + ["d_7_at_max.out","d_2_am__U502.in1"], + ["d_2_next_value.sel","d_2_am__U502.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4870,15 +4604,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U579.in0"], - ["d_4_at_max.out","d_3_am__U579.in1"], - ["d_3_am__U580.in0","d_3_am__U579.out"], - ["d_5_at_max.out","d_3_am__U580.in1"], - ["d_3_am__U581.in0","d_3_am__U580.out"], - ["d_6_at_max.out","d_3_am__U581.in1"], - ["d_3_am__U582.in0","d_3_am__U581.out"], - ["d_7_at_max.out","d_3_am__U582.in1"], - ["d_3_next_value.sel","d_3_am__U582.out"], + ["true.out","d_3_am__U503.in0"], + ["d_4_at_max.out","d_3_am__U503.in1"], + ["d_3_am__U504.in0","d_3_am__U503.out"], + ["d_5_at_max.out","d_3_am__U504.in1"], + ["d_3_am__U505.in0","d_3_am__U504.out"], + ["d_6_at_max.out","d_3_am__U505.in1"], + ["d_3_am__U506.in0","d_3_am__U505.out"], + ["d_7_at_max.out","d_3_am__U506.in1"], + ["d_3_next_value.sel","d_3_am__U506.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4891,13 +4625,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U583.in0"], - ["d_5_at_max.out","d_4_am__U583.in1"], - ["d_4_am__U584.in0","d_4_am__U583.out"], - ["d_6_at_max.out","d_4_am__U584.in1"], - ["d_4_am__U585.in0","d_4_am__U584.out"], - ["d_7_at_max.out","d_4_am__U585.in1"], - ["d_4_next_value.sel","d_4_am__U585.out"], + ["true.out","d_4_am__U507.in0"], + ["d_5_at_max.out","d_4_am__U507.in1"], + ["d_4_am__U508.in0","d_4_am__U507.out"], + ["d_6_at_max.out","d_4_am__U508.in1"], + ["d_4_am__U509.in0","d_4_am__U508.out"], + ["d_7_at_max.out","d_4_am__U509.in1"], + ["d_4_next_value.sel","d_4_am__U509.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -4910,11 +4644,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U586.in0"], - ["d_6_at_max.out","d_5_am__U586.in1"], - ["d_5_am__U587.in0","d_5_am__U586.out"], - ["d_7_at_max.out","d_5_am__U587.in1"], - ["d_5_next_value.sel","d_5_am__U587.out"], + ["true.out","d_5_am__U510.in0"], + ["d_6_at_max.out","d_5_am__U510.in1"], + ["d_5_am__U511.in0","d_5_am__U510.out"], + ["d_7_at_max.out","d_5_am__U511.in1"], + ["d_5_next_value.sel","d_5_am__U511.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -4927,9 +4661,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U588.in0"], - ["d_7_at_max.out","d_6_am__U588.in1"], - ["d_6_next_value.sel","d_6_am__U588.out"], + ["true.out","d_6_am__U512.in0"], + ["d_7_at_max.out","d_6_am__U512.in1"], + ["d_6_next_value.sel","d_6_am__U512.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -4957,7 +4691,7 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4965,18 +4699,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U77":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U78":{ + "_U69":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U57" + "modref":"global.aff__U48" }, "cmp_time":{ "genref":"coreir.eq", @@ -4986,19 +4720,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U79":{ + "d_0_am__U70":{ "modref":"corebit.and" }, - "d_0_am__U80":{ + "d_0_am__U71":{ "modref":"corebit.and" }, - "d_0_am__U81":{ + "d_0_am__U72":{ "modref":"corebit.and" }, - "d_0_am__U82":{ + "d_0_am__U73":{ "modref":"corebit.and" }, - "d_0_am__U83":{ + "d_0_am__U74":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5032,16 +4766,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U84":{ + "d_1_am__U75":{ "modref":"corebit.and" }, - "d_1_am__U85":{ + "d_1_am__U76":{ "modref":"corebit.and" }, - "d_1_am__U86":{ + "d_1_am__U77":{ "modref":"corebit.and" }, - "d_1_am__U87":{ + "d_1_am__U78":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -5075,13 +4809,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U88":{ + "d_2_am__U79":{ "modref":"corebit.and" }, - "d_2_am__U89":{ + "d_2_am__U80":{ "modref":"corebit.and" }, - "d_2_am__U90":{ + "d_2_am__U81":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5115,10 +4849,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U91":{ + "d_3_am__U82":{ "modref":"corebit.and" }, - "d_3_am__U92":{ + "d_3_am__U83":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -5152,7 +4886,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U93":{ + "d_4_am__U84":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -5227,13 +4961,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U77.out"], - ["d_1_inc.in1","_U77.out"], - ["d_2_inc.in1","_U77.out"], - ["d_3_inc.in1","_U77.out"], - ["d_4_inc.in1","_U77.out"], - ["d_5_inc.in1","_U77.out"], - ["cmp_time.in1","_U78.out"], + ["d_0_inc.in1","_U68.out"], + ["d_1_inc.in1","_U68.out"], + ["d_2_inc.in1","_U68.out"], + ["d_3_inc.in1","_U68.out"], + ["d_4_inc.in1","_U68.out"], + ["d_5_inc.in1","_U68.out"], + ["cmp_time.in1","_U69.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5252,17 +4986,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U79.in0"], - ["d_1_at_max.out","d_0_am__U79.in1"], - ["d_0_am__U80.in0","d_0_am__U79.out"], - ["d_2_at_max.out","d_0_am__U80.in1"], - ["d_0_am__U81.in0","d_0_am__U80.out"], - ["d_3_at_max.out","d_0_am__U81.in1"], - ["d_0_am__U82.in0","d_0_am__U81.out"], - ["d_4_at_max.out","d_0_am__U82.in1"], - ["d_0_am__U83.in0","d_0_am__U82.out"], - ["d_5_at_max.out","d_0_am__U83.in1"], - ["d_0_next_value.sel","d_0_am__U83.out"], + ["true.out","d_0_am__U70.in0"], + ["d_1_at_max.out","d_0_am__U70.in1"], + ["d_0_am__U71.in0","d_0_am__U70.out"], + ["d_2_at_max.out","d_0_am__U71.in1"], + ["d_0_am__U72.in0","d_0_am__U71.out"], + ["d_3_at_max.out","d_0_am__U72.in1"], + ["d_0_am__U73.in0","d_0_am__U72.out"], + ["d_4_at_max.out","d_0_am__U73.in1"], + ["d_0_am__U74.in0","d_0_am__U73.out"], + ["d_5_at_max.out","d_0_am__U74.in1"], + ["d_0_next_value.sel","d_0_am__U74.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5275,15 +5009,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U84.in0"], - ["d_2_at_max.out","d_1_am__U84.in1"], - ["d_1_am__U85.in0","d_1_am__U84.out"], - ["d_3_at_max.out","d_1_am__U85.in1"], - ["d_1_am__U86.in0","d_1_am__U85.out"], - ["d_4_at_max.out","d_1_am__U86.in1"], - ["d_1_am__U87.in0","d_1_am__U86.out"], - ["d_5_at_max.out","d_1_am__U87.in1"], - ["d_1_next_value.sel","d_1_am__U87.out"], + ["true.out","d_1_am__U75.in0"], + ["d_2_at_max.out","d_1_am__U75.in1"], + ["d_1_am__U76.in0","d_1_am__U75.out"], + ["d_3_at_max.out","d_1_am__U76.in1"], + ["d_1_am__U77.in0","d_1_am__U76.out"], + ["d_4_at_max.out","d_1_am__U77.in1"], + ["d_1_am__U78.in0","d_1_am__U77.out"], + ["d_5_at_max.out","d_1_am__U78.in1"], + ["d_1_next_value.sel","d_1_am__U78.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5296,13 +5030,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U88.in0"], - ["d_3_at_max.out","d_2_am__U88.in1"], - ["d_2_am__U89.in0","d_2_am__U88.out"], - ["d_4_at_max.out","d_2_am__U89.in1"], - ["d_2_am__U90.in0","d_2_am__U89.out"], - ["d_5_at_max.out","d_2_am__U90.in1"], - ["d_2_next_value.sel","d_2_am__U90.out"], + ["true.out","d_2_am__U79.in0"], + ["d_3_at_max.out","d_2_am__U79.in1"], + ["d_2_am__U80.in0","d_2_am__U79.out"], + ["d_4_at_max.out","d_2_am__U80.in1"], + ["d_2_am__U81.in0","d_2_am__U80.out"], + ["d_5_at_max.out","d_2_am__U81.in1"], + ["d_2_next_value.sel","d_2_am__U81.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5315,11 +5049,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U91.in0"], - ["d_4_at_max.out","d_3_am__U91.in1"], - ["d_3_am__U92.in0","d_3_am__U91.out"], - ["d_5_at_max.out","d_3_am__U92.in1"], - ["d_3_next_value.sel","d_3_am__U92.out"], + ["true.out","d_3_am__U82.in0"], + ["d_4_at_max.out","d_3_am__U82.in1"], + ["d_3_am__U83.in0","d_3_am__U82.out"], + ["d_5_at_max.out","d_3_am__U83.in1"], + ["d_3_next_value.sel","d_3_am__U83.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5332,9 +5066,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U93.in0"], - ["d_5_at_max.out","d_4_am__U93.in1"], - ["d_4_next_value.sel","d_4_am__U93.out"], + ["true.out","d_4_am__U84.in0"], + ["d_5_at_max.out","d_4_am__U84.in1"], + ["d_4_next_value.sel","d_4_am__U84.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -5362,7 +5096,7 @@ ["self.d.5","d_5_reg.out"] ] }, - "affine_controller__U635":{ + "affine_controller__U550":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5370,18 +5104,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U656":{ + "_U571":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U657":{ + "_U572":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U636" + "modref":"global.aff__U551" }, "cmp_time":{ "genref":"coreir.eq", @@ -5391,19 +5125,19 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U658":{ + "d_0_am__U573":{ "modref":"corebit.and" }, - "d_0_am__U659":{ + "d_0_am__U574":{ "modref":"corebit.and" }, - "d_0_am__U660":{ + "d_0_am__U575":{ "modref":"corebit.and" }, - "d_0_am__U661":{ + "d_0_am__U576":{ "modref":"corebit.and" }, - "d_0_am__U662":{ + "d_0_am__U577":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5437,16 +5171,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U663":{ + "d_1_am__U578":{ "modref":"corebit.and" }, - "d_1_am__U664":{ + "d_1_am__U579":{ "modref":"corebit.and" }, - "d_1_am__U665":{ + "d_1_am__U580":{ "modref":"corebit.and" }, - "d_1_am__U666":{ + "d_1_am__U581":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -5480,13 +5214,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U667":{ + "d_2_am__U582":{ "modref":"corebit.and" }, - "d_2_am__U668":{ + "d_2_am__U583":{ "modref":"corebit.and" }, - "d_2_am__U669":{ + "d_2_am__U584":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5520,10 +5254,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U670":{ + "d_3_am__U585":{ "modref":"corebit.and" }, - "d_3_am__U671":{ + "d_3_am__U586":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -5557,7 +5291,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U672":{ + "d_4_am__U587":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -5632,13 +5366,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U656.out"], - ["d_1_inc.in1","_U656.out"], - ["d_2_inc.in1","_U656.out"], - ["d_3_inc.in1","_U656.out"], - ["d_4_inc.in1","_U656.out"], - ["d_5_inc.in1","_U656.out"], - ["cmp_time.in1","_U657.out"], + ["d_0_inc.in1","_U571.out"], + ["d_1_inc.in1","_U571.out"], + ["d_2_inc.in1","_U571.out"], + ["d_3_inc.in1","_U571.out"], + ["d_4_inc.in1","_U571.out"], + ["d_5_inc.in1","_U571.out"], + ["cmp_time.in1","_U572.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5657,17 +5391,17 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U658.in0"], - ["d_1_at_max.out","d_0_am__U658.in1"], - ["d_0_am__U659.in0","d_0_am__U658.out"], - ["d_2_at_max.out","d_0_am__U659.in1"], - ["d_0_am__U660.in0","d_0_am__U659.out"], - ["d_3_at_max.out","d_0_am__U660.in1"], - ["d_0_am__U661.in0","d_0_am__U660.out"], - ["d_4_at_max.out","d_0_am__U661.in1"], - ["d_0_am__U662.in0","d_0_am__U661.out"], - ["d_5_at_max.out","d_0_am__U662.in1"], - ["d_0_next_value.sel","d_0_am__U662.out"], + ["true.out","d_0_am__U573.in0"], + ["d_1_at_max.out","d_0_am__U573.in1"], + ["d_0_am__U574.in0","d_0_am__U573.out"], + ["d_2_at_max.out","d_0_am__U574.in1"], + ["d_0_am__U575.in0","d_0_am__U574.out"], + ["d_3_at_max.out","d_0_am__U575.in1"], + ["d_0_am__U576.in0","d_0_am__U575.out"], + ["d_4_at_max.out","d_0_am__U576.in1"], + ["d_0_am__U577.in0","d_0_am__U576.out"], + ["d_5_at_max.out","d_0_am__U577.in1"], + ["d_0_next_value.sel","d_0_am__U577.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5680,15 +5414,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U663.in0"], - ["d_2_at_max.out","d_1_am__U663.in1"], - ["d_1_am__U664.in0","d_1_am__U663.out"], - ["d_3_at_max.out","d_1_am__U664.in1"], - ["d_1_am__U665.in0","d_1_am__U664.out"], - ["d_4_at_max.out","d_1_am__U665.in1"], - ["d_1_am__U666.in0","d_1_am__U665.out"], - ["d_5_at_max.out","d_1_am__U666.in1"], - ["d_1_next_value.sel","d_1_am__U666.out"], + ["true.out","d_1_am__U578.in0"], + ["d_2_at_max.out","d_1_am__U578.in1"], + ["d_1_am__U579.in0","d_1_am__U578.out"], + ["d_3_at_max.out","d_1_am__U579.in1"], + ["d_1_am__U580.in0","d_1_am__U579.out"], + ["d_4_at_max.out","d_1_am__U580.in1"], + ["d_1_am__U581.in0","d_1_am__U580.out"], + ["d_5_at_max.out","d_1_am__U581.in1"], + ["d_1_next_value.sel","d_1_am__U581.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5701,13 +5435,13 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U667.in0"], - ["d_3_at_max.out","d_2_am__U667.in1"], - ["d_2_am__U668.in0","d_2_am__U667.out"], - ["d_4_at_max.out","d_2_am__U668.in1"], - ["d_2_am__U669.in0","d_2_am__U668.out"], - ["d_5_at_max.out","d_2_am__U669.in1"], - ["d_2_next_value.sel","d_2_am__U669.out"], + ["true.out","d_2_am__U582.in0"], + ["d_3_at_max.out","d_2_am__U582.in1"], + ["d_2_am__U583.in0","d_2_am__U582.out"], + ["d_4_at_max.out","d_2_am__U583.in1"], + ["d_2_am__U584.in0","d_2_am__U583.out"], + ["d_5_at_max.out","d_2_am__U584.in1"], + ["d_2_next_value.sel","d_2_am__U584.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5720,11 +5454,11 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U670.in0"], - ["d_4_at_max.out","d_3_am__U670.in1"], - ["d_3_am__U671.in0","d_3_am__U670.out"], - ["d_5_at_max.out","d_3_am__U671.in1"], - ["d_3_next_value.sel","d_3_am__U671.out"], + ["true.out","d_3_am__U585.in0"], + ["d_4_at_max.out","d_3_am__U585.in1"], + ["d_3_am__U586.in0","d_3_am__U585.out"], + ["d_5_at_max.out","d_3_am__U586.in1"], + ["d_3_next_value.sel","d_3_am__U586.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5737,9 +5471,9 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U672.in0"], - ["d_5_at_max.out","d_4_am__U672.in1"], - ["d_4_next_value.sel","d_4_am__U672.out"], + ["true.out","d_4_am__U587.in0"], + ["d_5_at_max.out","d_4_am__U587.in1"], + ["d_4_next_value.sel","d_4_am__U587.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -5767,7 +5501,273 @@ ["self.d.5","d_5_reg.out"] ] }, - "affine_controller__U695":{ + "affine_controller__U610":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",4,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U625":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U626":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U611" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U627":{ + "modref":"corebit.and" + }, + "d_0_am__U628":{ + "modref":"corebit.and" + }, + "d_0_am__U629":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U630":{ + "modref":"corebit.and" + }, + "d_1_am__U631":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000006"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_am__U632":{ + "modref":"corebit.and" + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000006"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U625.out"], + ["d_1_inc.in1","_U625.out"], + ["d_2_inc.in1","_U625.out"], + ["d_3_inc.in1","_U625.out"], + ["cmp_time.in1","_U626.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U627.in0"], + ["d_1_at_max.out","d_0_am__U627.in1"], + ["d_0_am__U628.in0","d_0_am__U627.out"], + ["d_2_at_max.out","d_0_am__U628.in1"], + ["d_0_am__U629.in0","d_0_am__U628.out"], + ["d_3_at_max.out","d_0_am__U629.in1"], + ["d_0_next_value.sel","d_0_am__U629.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U630.in0"], + ["d_2_at_max.out","d_1_am__U630.in1"], + ["d_1_am__U631.in0","d_1_am__U630.out"], + ["d_3_at_max.out","d_1_am__U631.in1"], + ["d_1_next_value.sel","d_1_am__U631.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U632.in0"], + ["d_3_at_max.out","d_2_am__U632.in1"], + ["d_2_next_value.sel","d_2_am__U632.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] + ] + }, + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5775,18 +5775,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U710":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U711":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U696" + "modref":"global.aff__U9" }, "cmp_time":{ "genref":"coreir.eq", @@ -5796,13 +5796,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U712":{ + "d_0_am__U25":{ "modref":"corebit.and" }, - "d_0_am__U713":{ + "d_0_am__U26":{ "modref":"corebit.and" }, - "d_0_am__U714":{ + "d_0_am__U27":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5836,10 +5836,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U715":{ + "d_1_am__U28":{ "modref":"corebit.and" }, - "d_1_am__U716":{ + "d_1_am__U29":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -5853,7 +5853,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -5873,7 +5873,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U717":{ + "d_2_am__U30":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5887,7 +5887,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_2_min":{ "genref":"coreir.const", @@ -5918,7 +5918,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, "d_3_min":{ "genref":"coreir.const", @@ -5948,11 +5948,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U710.out"], - ["d_1_inc.in1","_U710.out"], - ["d_2_inc.in1","_U710.out"], - ["d_3_inc.in1","_U710.out"], - ["cmp_time.in1","_U711.out"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U23.out"], + ["d_2_inc.in1","_U23.out"], + ["d_3_inc.in1","_U23.out"], + ["cmp_time.in1","_U24.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5967,13 +5967,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U712.in0"], - ["d_1_at_max.out","d_0_am__U712.in1"], - ["d_0_am__U713.in0","d_0_am__U712.out"], - ["d_2_at_max.out","d_0_am__U713.in1"], - ["d_0_am__U714.in0","d_0_am__U713.out"], - ["d_3_at_max.out","d_0_am__U714.in1"], - ["d_0_next_value.sel","d_0_am__U714.out"], + ["true.out","d_0_am__U25.in0"], + ["d_1_at_max.out","d_0_am__U25.in1"], + ["d_0_am__U26.in0","d_0_am__U25.out"], + ["d_2_at_max.out","d_0_am__U26.in1"], + ["d_0_am__U27.in0","d_0_am__U26.out"], + ["d_3_at_max.out","d_0_am__U27.in1"], + ["d_0_next_value.sel","d_0_am__U27.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5986,11 +5986,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U715.in0"], - ["d_2_at_max.out","d_1_am__U715.in1"], - ["d_1_am__U716.in0","d_1_am__U715.out"], - ["d_3_at_max.out","d_1_am__U716.in1"], - ["d_1_next_value.sel","d_1_am__U716.out"], + ["true.out","d_1_am__U28.in0"], + ["d_2_at_max.out","d_1_am__U28.in1"], + ["d_1_am__U29.in0","d_1_am__U28.out"], + ["d_3_at_max.out","d_1_am__U29.in1"], + ["d_1_next_value.sel","d_1_am__U29.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -6003,9 +6003,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U717.in0"], - ["d_3_at_max.out","d_2_am__U717.in1"], - ["d_2_next_value.sel","d_2_am__U717.out"], + ["true.out","d_2_am__U30.in0"], + ["d_3_at_max.out","d_2_am__U30.in1"], + ["d_2_next_value.sel","d_2_am__U30.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -7708,42 +7708,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9229],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9229],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -7751,8 +7719,8 @@ }, "ub_input_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9230],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10365],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9230],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10365],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -7760,8 +7728,8 @@ }, "ub_input_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9231],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9231],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -7769,8 +7737,8 @@ }, "ub_input_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9232],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9232],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -7778,8 +7746,8 @@ }, "ub_input_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9229],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9229],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -7787,8 +7755,8 @@ }, "ub_input_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9230],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10365],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9230],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10365],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -7796,8 +7764,8 @@ }, "ub_input_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9231],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9231],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -7805,8 +7773,8 @@ }, "ub_input_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9232],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9232],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[10366],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -7814,14 +7782,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_input_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U11.out"], - ["ub_input_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U13.out"], - ["ub_input_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U15.out"], - ["ub_input_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_input_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], - ["ub_input_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U7.out"], - ["ub_input_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U9.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_1.clk","self.clk"], ["ub_input_cgra_stencil_BANK_2.clk","self.clk"], @@ -7941,76 +7901,76 @@ ["op_hcompute_input_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_165_U115":{ - "modref":"global.aff__U95" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_165_U106":{ + "modref":"global.aff__U86" }, - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_1_163_U216":{ - "modref":"global.aff__U196" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_1_163_U206":{ + "modref":"global.aff__U186" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U156":{ - "modref":"global.aff__U142" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U146":{ + "modref":"global.aff__U132" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U55":{ - "modref":"global.aff__U41" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U46":{ + "modref":"global.aff__U32" }, - "chain_en_const_U116":{ + "chain_en_const_U107":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "chain_en_const_U217":{ + "chain_en_const_U207":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U141":{ - "modref":"global.affine_controller__U118", + "ctrl__U131":{ + "modref":"global.affine_controller__U108", "metadata":{"garnet_remove":true} }, - "ctrl__U195":{ - "modref":"global.affine_controller__U157", + "ctrl__U185":{ + "modref":"global.affine_controller__U147", "metadata":{"garnet_remove":true} }, - "ctrl__U40":{ - "modref":"global.affine_controller__U17", + "ctrl__U31":{ + "modref":"global.affine_controller__U8", "metadata":{"garnet_remove":true} }, - "ctrl__U94":{ - "modref":"global.affine_controller__U56", + "ctrl__U85":{ + "modref":"global.affine_controller__U47", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,2016,4032],"dimensionality":4,"extent":[4,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,4,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[2],"dimensionality":1,"extent":[2048],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U16"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,2016,4032],"dimensionality":4,"extent":[4,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,4,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[2],"dimensionality":1,"extent":[2048],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} }, "input_glb_stencil_BANK_1_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_1"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,2016,4032],"dimensionality":4,"extent":[4,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,4,0]},"in2glb_0":{"cycle_starting_addr":[1],"cycle_stride":[2],"dimensionality":1,"extent":[2048],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U117"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,2016,4032],"dimensionality":4,"extent":[4,256,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,4,0]},"in2glb_0":{"cycle_starting_addr":[1],"cycle_stride":[2],"dimensionality":1,"extent":[2048],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U94.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_165_U115.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_165_U115.out"], - ["ctrl__U195.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_1_163_U216.d"], - ["input_glb_stencil_BANK_1_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_1_163_U216.out"], - ["ctrl__U141.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U156.d"], - ["input_glb_stencil_BANK_1_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U156.out"], - ["ctrl__U40.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U55.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U55.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U116.out"], - ["input_glb_stencil_BANK_1_ubuf.chain_chain_en","chain_en_const_U217.out"], - ["self.clk","ctrl__U141.clk"], - ["self.reset","ctrl__U141.rst_n"], - ["input_glb_stencil_BANK_1_ubuf.wen_0","ctrl__U141.valid"], - ["self.clk","ctrl__U195.clk"], - ["self.reset","ctrl__U195.rst_n"], - ["input_glb_stencil_BANK_1_ubuf.ren_0","ctrl__U195.valid"], - ["self.clk","ctrl__U40.clk"], - ["self.reset","ctrl__U40.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U40.valid"], - ["self.clk","ctrl__U94.clk"], - ["self.reset","ctrl__U94.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U94.valid"], + ["ctrl__U85.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_165_U106.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_165_U106.out"], + ["ctrl__U185.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_1_163_U206.d"], + ["input_glb_stencil_BANK_1_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_1_163_U206.out"], + ["ctrl__U131.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U146.d"], + ["input_glb_stencil_BANK_1_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U146.out"], + ["ctrl__U31.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U46.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_160_U46.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U107.out"], + ["input_glb_stencil_BANK_1_ubuf.chain_chain_en","chain_en_const_U207.out"], + ["self.clk","ctrl__U131.clk"], + ["self.reset","ctrl__U131.rst_n"], + ["input_glb_stencil_BANK_1_ubuf.wen_0","ctrl__U131.valid"], + ["self.clk","ctrl__U185.clk"], + ["self.reset","ctrl__U185.rst_n"], + ["input_glb_stencil_BANK_1_ubuf.ren_0","ctrl__U185.valid"], + ["self.clk","ctrl__U31.clk"], + ["self.reset","ctrl__U31.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U31.valid"], + ["self.clk","ctrl__U85.clk"], + ["self.reset","ctrl__U85.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U85.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_glb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_input_cgra_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -8048,266 +8008,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U271":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U273":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U275":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U277":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U279":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U281":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U283":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U285":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U287":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U289":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U291":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U293":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U295":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U297":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U299":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U301":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U303":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U305":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U307":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U309":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U311":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U313":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U315":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U317":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U319":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U321":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U323":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U325":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U327":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U329":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U331":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U333":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U335":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U337":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U339":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U341":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U343":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U345":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9313],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U218"} + "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9313],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -8315,13 +8019,13 @@ }, "ub_kernel_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9317],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U220"} + "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9317],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9322],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U238"} + "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9322],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -8329,8 +8033,8 @@ }, "ub_kernel_cgra_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9326],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U240"} + "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9326],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -8338,8 +8042,8 @@ }, "ub_kernel_cgra_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9330],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U242"} + "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9330],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -8347,8 +8051,8 @@ }, "ub_kernel_cgra_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9334],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U244"} + "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9334],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -8356,8 +8060,8 @@ }, "ub_kernel_cgra_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9338],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U246"} + "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9338],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -8365,8 +8069,8 @@ }, "ub_kernel_cgra_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9342],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U248"} + "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9342],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -8374,8 +8078,8 @@ }, "ub_kernel_cgra_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9315],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U250"} + "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9315],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -8383,8 +8087,8 @@ }, "ub_kernel_cgra_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9319],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U252"} + "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9319],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -8392,8 +8096,8 @@ }, "ub_kernel_cgra_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9323],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U254"} + "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9323],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -8401,8 +8105,8 @@ }, "ub_kernel_cgra_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9327],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U256"} + "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9327],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -8414,13 +8118,13 @@ }, "ub_kernel_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9321],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U222"} + "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9321],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9331],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U258"} + "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9331],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -8428,8 +8132,8 @@ }, "ub_kernel_cgra_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9335],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U260"} + "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9335],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -8437,8 +8141,8 @@ }, "ub_kernel_cgra_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9339],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U262"} + "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9339],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -8446,8 +8150,8 @@ }, "ub_kernel_cgra_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9343],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U264"} + "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9343],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -8455,8 +8159,8 @@ }, "ub_kernel_cgra_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9316],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U266"} + "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9316],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -8464,8 +8168,8 @@ }, "ub_kernel_cgra_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9320],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U268"} + "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9320],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -8473,8 +8177,8 @@ }, "ub_kernel_cgra_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U270"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9324],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U270"} + "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9324],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -8482,8 +8186,8 @@ }, "ub_kernel_cgra_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U272"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9328],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U272"} + "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9328],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -8491,8 +8195,8 @@ }, "ub_kernel_cgra_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U274"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9332],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U274"} + "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9332],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -8500,8 +8204,8 @@ }, "ub_kernel_cgra_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U276"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9336],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U276"} + "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9336],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -8513,13 +8217,13 @@ }, "ub_kernel_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9325],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U224"} + "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9325],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U278"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9340],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U278"} + "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9340],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -8527,8 +8231,8 @@ }, "ub_kernel_cgra_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U280"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9344],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U280"} + "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9344],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -8536,8 +8240,8 @@ }, "ub_kernel_cgra_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U282"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9313],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U282"} + "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9313],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -8545,8 +8249,8 @@ }, "ub_kernel_cgra_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U284"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9317],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U284"} + "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9317],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9220],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -8554,8 +8258,8 @@ }, "ub_kernel_cgra_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U286"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9321],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U286"} + "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9321],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9224],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -8563,8 +8267,8 @@ }, "ub_kernel_cgra_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U288"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9325],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U288"} + "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9325],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9228],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -8572,8 +8276,8 @@ }, "ub_kernel_cgra_stencil_BANK_36":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U290"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9329],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U290"} + "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9329],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const":{ "modref":"corebit.const", @@ -8581,8 +8285,8 @@ }, "ub_kernel_cgra_stencil_BANK_37":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U292"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9333],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U292"} + "genargs":{"ID":["String","_U245"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9333],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const":{ "modref":"corebit.const", @@ -8590,8 +8294,8 @@ }, "ub_kernel_cgra_stencil_BANK_38":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9337],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U294"} + "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9337],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const":{ "modref":"corebit.const", @@ -8599,8 +8303,8 @@ }, "ub_kernel_cgra_stencil_BANK_39":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U296"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9341],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U296"} + "genargs":{"ID":["String","_U247"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9341],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const":{ "modref":"corebit.const", @@ -8612,13 +8316,13 @@ }, "ub_kernel_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9329],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U226"} + "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9329],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9232],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U298"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9314],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U298"} + "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9314],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const":{ "modref":"corebit.const", @@ -8626,8 +8330,8 @@ }, "ub_kernel_cgra_stencil_BANK_41":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U300"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9318],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U300"} + "genargs":{"ID":["String","_U249"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9318],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const":{ "modref":"corebit.const", @@ -8635,8 +8339,8 @@ }, "ub_kernel_cgra_stencil_BANK_42":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U302"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9322],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U302"} + "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9322],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9225],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const":{ "modref":"corebit.const", @@ -8644,8 +8348,8 @@ }, "ub_kernel_cgra_stencil_BANK_43":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U304"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9326],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U304"} + "genargs":{"ID":["String","_U251"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9326],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9229],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const":{ "modref":"corebit.const", @@ -8653,8 +8357,8 @@ }, "ub_kernel_cgra_stencil_BANK_44":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U306"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9330],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U306"} + "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9330],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9233],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const":{ "modref":"corebit.const", @@ -8662,8 +8366,8 @@ }, "ub_kernel_cgra_stencil_BANK_45":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9334],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U308"} + "genargs":{"ID":["String","_U253"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9334],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9237],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const":{ "modref":"corebit.const", @@ -8671,8 +8375,8 @@ }, "ub_kernel_cgra_stencil_BANK_46":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9338],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U310"} + "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9338],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9241],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const":{ "modref":"corebit.const", @@ -8680,8 +8384,8 @@ }, "ub_kernel_cgra_stencil_BANK_47":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9342],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U312"} + "genargs":{"ID":["String","_U255"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9342],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9245],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const":{ "modref":"corebit.const", @@ -8689,8 +8393,8 @@ }, "ub_kernel_cgra_stencil_BANK_48":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9315],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U314"} + "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9315],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9218],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const":{ "modref":"corebit.const", @@ -8698,8 +8402,8 @@ }, "ub_kernel_cgra_stencil_BANK_49":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U316"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9319],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U316"} + "genargs":{"ID":["String","_U257"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9319],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9222],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const":{ "modref":"corebit.const", @@ -8711,13 +8415,13 @@ }, "ub_kernel_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9333],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U228"} + "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9333],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9236],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U318"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9323],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U318"} + "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9323],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9226],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const":{ "modref":"corebit.const", @@ -8725,8 +8429,8 @@ }, "ub_kernel_cgra_stencil_BANK_51":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U320"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9327],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U320"} + "genargs":{"ID":["String","_U259"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9327],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9230],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const":{ "modref":"corebit.const", @@ -8734,8 +8438,8 @@ }, "ub_kernel_cgra_stencil_BANK_52":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U322"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9331],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U322"} + "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9331],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9234],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const":{ "modref":"corebit.const", @@ -8743,8 +8447,8 @@ }, "ub_kernel_cgra_stencil_BANK_53":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U324"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9335],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U324"} + "genargs":{"ID":["String","_U261"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9335],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9238],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const":{ "modref":"corebit.const", @@ -8752,8 +8456,8 @@ }, "ub_kernel_cgra_stencil_BANK_54":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U326"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9339],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U326"} + "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9339],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9242],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const":{ "modref":"corebit.const", @@ -8761,8 +8465,8 @@ }, "ub_kernel_cgra_stencil_BANK_55":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U328"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9343],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U328"} + "genargs":{"ID":["String","_U263"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9343],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9246],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const":{ "modref":"corebit.const", @@ -8770,8 +8474,8 @@ }, "ub_kernel_cgra_stencil_BANK_56":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U330"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9316],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U330"} + "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9316],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9219],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const":{ "modref":"corebit.const", @@ -8779,8 +8483,8 @@ }, "ub_kernel_cgra_stencil_BANK_57":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U332"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9320],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U332"} + "genargs":{"ID":["String","_U265"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9320],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9223],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const":{ "modref":"corebit.const", @@ -8788,8 +8492,8 @@ }, "ub_kernel_cgra_stencil_BANK_58":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U334"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9324],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U334"} + "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9324],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9227],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const":{ "modref":"corebit.const", @@ -8797,8 +8501,8 @@ }, "ub_kernel_cgra_stencil_BANK_59":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U336"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9328],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U336"} + "genargs":{"ID":["String","_U267"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9328],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9231],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const":{ "modref":"corebit.const", @@ -8810,13 +8514,13 @@ }, "ub_kernel_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9337],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U230"} + "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9337],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9240],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U338"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9332],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U338"} + "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9332],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9235],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const":{ "modref":"corebit.const", @@ -8824,8 +8528,8 @@ }, "ub_kernel_cgra_stencil_BANK_61":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U340"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9336],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U340"} + "genargs":{"ID":["String","_U269"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9336],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9239],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const":{ "modref":"corebit.const", @@ -8833,8 +8537,8 @@ }, "ub_kernel_cgra_stencil_BANK_62":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U342"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9340],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U342"} + "genargs":{"ID":["String","_U270"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9340],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9243],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const":{ "modref":"corebit.const", @@ -8842,8 +8546,8 @@ }, "ub_kernel_cgra_stencil_BANK_63":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U344"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9344],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U344"} + "genargs":{"ID":["String","_U271"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9344],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9247],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const":{ "modref":"corebit.const", @@ -8855,8 +8559,8 @@ }, "ub_kernel_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9341],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U232"} + "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9341],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9244],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -8864,8 +8568,8 @@ }, "ub_kernel_cgra_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9314],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U234"} + "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9314],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9217],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -8873,8 +8577,8 @@ }, "ub_kernel_cgra_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9318],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake","verilog_name":"lake__U236"} + "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9318],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9221],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10369],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -8882,70 +8586,6 @@ } }, "connections":[ - ["ub_kernel_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U219.out"], - ["ub_kernel_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U221.out"], - ["ub_kernel_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U223.out"], - ["ub_kernel_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U225.out"], - ["ub_kernel_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U227.out"], - ["ub_kernel_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U229.out"], - ["ub_kernel_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U231.out"], - ["ub_kernel_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U233.out"], - ["ub_kernel_cgra_stencil_BANK_8.chain_chain_en","chain_en_const_U235.out"], - ["ub_kernel_cgra_stencil_BANK_9.chain_chain_en","chain_en_const_U237.out"], - ["ub_kernel_cgra_stencil_BANK_10.chain_chain_en","chain_en_const_U239.out"], - ["ub_kernel_cgra_stencil_BANK_11.chain_chain_en","chain_en_const_U241.out"], - ["ub_kernel_cgra_stencil_BANK_12.chain_chain_en","chain_en_const_U243.out"], - ["ub_kernel_cgra_stencil_BANK_13.chain_chain_en","chain_en_const_U245.out"], - ["ub_kernel_cgra_stencil_BANK_14.chain_chain_en","chain_en_const_U247.out"], - ["ub_kernel_cgra_stencil_BANK_15.chain_chain_en","chain_en_const_U249.out"], - ["ub_kernel_cgra_stencil_BANK_16.chain_chain_en","chain_en_const_U251.out"], - ["ub_kernel_cgra_stencil_BANK_17.chain_chain_en","chain_en_const_U253.out"], - ["ub_kernel_cgra_stencil_BANK_18.chain_chain_en","chain_en_const_U255.out"], - ["ub_kernel_cgra_stencil_BANK_19.chain_chain_en","chain_en_const_U257.out"], - ["ub_kernel_cgra_stencil_BANK_20.chain_chain_en","chain_en_const_U259.out"], - ["ub_kernel_cgra_stencil_BANK_21.chain_chain_en","chain_en_const_U261.out"], - ["ub_kernel_cgra_stencil_BANK_22.chain_chain_en","chain_en_const_U263.out"], - ["ub_kernel_cgra_stencil_BANK_23.chain_chain_en","chain_en_const_U265.out"], - ["ub_kernel_cgra_stencil_BANK_24.chain_chain_en","chain_en_const_U267.out"], - ["ub_kernel_cgra_stencil_BANK_25.chain_chain_en","chain_en_const_U269.out"], - ["ub_kernel_cgra_stencil_BANK_26.chain_chain_en","chain_en_const_U271.out"], - ["ub_kernel_cgra_stencil_BANK_27.chain_chain_en","chain_en_const_U273.out"], - ["ub_kernel_cgra_stencil_BANK_28.chain_chain_en","chain_en_const_U275.out"], - ["ub_kernel_cgra_stencil_BANK_29.chain_chain_en","chain_en_const_U277.out"], - ["ub_kernel_cgra_stencil_BANK_30.chain_chain_en","chain_en_const_U279.out"], - ["ub_kernel_cgra_stencil_BANK_31.chain_chain_en","chain_en_const_U281.out"], - ["ub_kernel_cgra_stencil_BANK_32.chain_chain_en","chain_en_const_U283.out"], - ["ub_kernel_cgra_stencil_BANK_33.chain_chain_en","chain_en_const_U285.out"], - ["ub_kernel_cgra_stencil_BANK_34.chain_chain_en","chain_en_const_U287.out"], - ["ub_kernel_cgra_stencil_BANK_35.chain_chain_en","chain_en_const_U289.out"], - ["ub_kernel_cgra_stencil_BANK_36.chain_chain_en","chain_en_const_U291.out"], - ["ub_kernel_cgra_stencil_BANK_37.chain_chain_en","chain_en_const_U293.out"], - ["ub_kernel_cgra_stencil_BANK_38.chain_chain_en","chain_en_const_U295.out"], - ["ub_kernel_cgra_stencil_BANK_39.chain_chain_en","chain_en_const_U297.out"], - ["ub_kernel_cgra_stencil_BANK_40.chain_chain_en","chain_en_const_U299.out"], - ["ub_kernel_cgra_stencil_BANK_41.chain_chain_en","chain_en_const_U301.out"], - ["ub_kernel_cgra_stencil_BANK_42.chain_chain_en","chain_en_const_U303.out"], - ["ub_kernel_cgra_stencil_BANK_43.chain_chain_en","chain_en_const_U305.out"], - ["ub_kernel_cgra_stencil_BANK_44.chain_chain_en","chain_en_const_U307.out"], - ["ub_kernel_cgra_stencil_BANK_45.chain_chain_en","chain_en_const_U309.out"], - ["ub_kernel_cgra_stencil_BANK_46.chain_chain_en","chain_en_const_U311.out"], - ["ub_kernel_cgra_stencil_BANK_47.chain_chain_en","chain_en_const_U313.out"], - ["ub_kernel_cgra_stencil_BANK_48.chain_chain_en","chain_en_const_U315.out"], - ["ub_kernel_cgra_stencil_BANK_49.chain_chain_en","chain_en_const_U317.out"], - ["ub_kernel_cgra_stencil_BANK_50.chain_chain_en","chain_en_const_U319.out"], - ["ub_kernel_cgra_stencil_BANK_51.chain_chain_en","chain_en_const_U321.out"], - ["ub_kernel_cgra_stencil_BANK_52.chain_chain_en","chain_en_const_U323.out"], - ["ub_kernel_cgra_stencil_BANK_53.chain_chain_en","chain_en_const_U325.out"], - ["ub_kernel_cgra_stencil_BANK_54.chain_chain_en","chain_en_const_U327.out"], - ["ub_kernel_cgra_stencil_BANK_55.chain_chain_en","chain_en_const_U329.out"], - ["ub_kernel_cgra_stencil_BANK_56.chain_chain_en","chain_en_const_U331.out"], - ["ub_kernel_cgra_stencil_BANK_57.chain_chain_en","chain_en_const_U333.out"], - ["ub_kernel_cgra_stencil_BANK_58.chain_chain_en","chain_en_const_U335.out"], - ["ub_kernel_cgra_stencil_BANK_59.chain_chain_en","chain_en_const_U337.out"], - ["ub_kernel_cgra_stencil_BANK_60.chain_chain_en","chain_en_const_U339.out"], - ["ub_kernel_cgra_stencil_BANK_61.chain_chain_en","chain_en_const_U341.out"], - ["ub_kernel_cgra_stencil_BANK_62.chain_chain_en","chain_en_const_U343.out"], - ["ub_kernel_cgra_stencil_BANK_63.chain_chain_en","chain_en_const_U345.out"], ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_1.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_10.clk","self.clk"], @@ -9345,76 +8985,76 @@ ["op_hcompute_kernel_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_159_U480":{ - "modref":"global.aff__U454" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_159_U405":{ + "modref":"global.aff__U379" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_1_157_U616":{ - "modref":"global.aff__U590" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_1_157_U540":{ + "modref":"global.aff__U514" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U395":{ - "modref":"global.aff__U378" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U320":{ + "modref":"global.aff__U303" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U531":{ - "modref":"global.aff__U514" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U455":{ + "modref":"global.aff__U438" }, - "chain_en_const_U481":{ + "chain_en_const_U406":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "chain_en_const_U617":{ + "chain_en_const_U541":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U377":{ - "modref":"global.affine_controller__U347", + "ctrl__U302":{ + "modref":"global.affine_controller__U272", "metadata":{"garnet_remove":true} }, - "ctrl__U453":{ - "modref":"global.affine_controller__U396", + "ctrl__U378":{ + "modref":"global.affine_controller__U321", "metadata":{"garnet_remove":true} }, - "ctrl__U513":{ - "modref":"global.affine_controller__U483", + "ctrl__U437":{ + "modref":"global.affine_controller__U407", "metadata":{"garnet_remove":true} }, - "ctrl__U589":{ - "modref":"global.affine_controller__U532", + "ctrl__U513":{ + "modref":"global.affine_controller__U456", "metadata":{"garnet_remove":true} }, "kernel_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,128,2016,4032],"dimensionality":5,"extent":[4,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,512,4,256]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[2],"dimensionality":1,"extent":[4608],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U346"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,128,2016,4032],"dimensionality":5,"extent":[4,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,512,4,256]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[2],"dimensionality":1,"extent":[4608],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} }, "kernel_glb_stencil_BANK_1_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_1"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,128,2016,4032],"dimensionality":5,"extent":[4,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,512,4,256]},"in2glb_0":{"cycle_starting_addr":[1],"cycle_stride":[2],"dimensionality":1,"extent":[4608],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U482"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,128,2016,4032],"dimensionality":5,"extent":[4,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,512,4,256]},"in2glb_0":{"cycle_starting_addr":[1],"cycle_stride":[2],"dimensionality":1,"extent":[4608],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U453.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_159_U480.d"], - ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_159_U480.out"], - ["ctrl__U589.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_1_157_U616.d"], - ["kernel_glb_stencil_BANK_1_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_1_157_U616.out"], - ["ctrl__U377.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U395.d"], - ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U395.out"], - ["ctrl__U513.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U531.d"], - ["kernel_glb_stencil_BANK_1_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U531.out"], - ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U481.out"], - ["kernel_glb_stencil_BANK_1_ubuf.chain_chain_en","chain_en_const_U617.out"], - ["self.clk","ctrl__U377.clk"], - ["self.reset","ctrl__U377.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U377.valid"], - ["self.clk","ctrl__U453.clk"], - ["self.reset","ctrl__U453.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U453.valid"], + ["ctrl__U378.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_159_U405.d"], + ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_159_U405.out"], + ["ctrl__U513.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_1_157_U540.d"], + ["kernel_glb_stencil_BANK_1_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_1_157_U540.out"], + ["ctrl__U302.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U320.d"], + ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U320.out"], + ["ctrl__U437.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U455.d"], + ["kernel_glb_stencil_BANK_1_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U455.out"], + ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U406.out"], + ["kernel_glb_stencil_BANK_1_ubuf.chain_chain_en","chain_en_const_U541.out"], + ["self.clk","ctrl__U302.clk"], + ["self.reset","ctrl__U302.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U302.valid"], + ["self.clk","ctrl__U378.clk"], + ["self.reset","ctrl__U378.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U378.valid"], + ["self.clk","ctrl__U437.clk"], + ["self.reset","ctrl__U437.rst_n"], + ["kernel_glb_stencil_BANK_1_ubuf.wen_0","ctrl__U437.valid"], ["self.clk","ctrl__U513.clk"], ["self.reset","ctrl__U513.rst_n"], - ["kernel_glb_stencil_BANK_1_ubuf.wen_0","ctrl__U513.valid"], - ["self.clk","ctrl__U589.clk"], - ["self.reset","ctrl__U589.rst_n"], - ["kernel_glb_stencil_BANK_1_ubuf.ren_0","ctrl__U589.valid"], + ["kernel_glb_stencil_BANK_1_ubuf.ren_0","ctrl__U513.valid"], ["self.clk","kernel_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_kernel_glb_stencil_write.0","kernel_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_kernel_cgra_stencil_read.0","kernel_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -9425,7 +9065,7 @@ ["self.reset","kernel_glb_stencil_BANK_1_ubuf.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U737":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U652":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9434,7 +9074,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U736":{ + "op_hcompute_hw_output_stencil_read_start_pt__U651":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9443,7 +9083,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U738":{ + "op_hcompute_hw_output_stencil_write_start_pt__U653":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9452,7 +9092,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U746":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U661":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9461,7 +9101,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U745":{ + "op_hcompute_input_glb_stencil_read_start_pt__U660":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9470,7 +9110,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U747":{ + "op_hcompute_input_glb_stencil_write_start_pt__U662":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9479,7 +9119,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U741":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U656":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9488,7 +9128,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U740":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U655":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9497,7 +9137,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U742":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U657":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9563,42 +9203,10 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U619":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U621":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U623":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U625":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U627":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U629":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U631":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U633":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U618"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14397],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14400],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U618"} + "genargs":{"ID":["String","_U542"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14397],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14400],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -9606,8 +9214,8 @@ }, "ub_output_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U620"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9220],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[10377],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14399],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14401],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U620"} + "genargs":{"ID":["String","_U543"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[9220],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[10377],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14399],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14401],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -9615,8 +9223,8 @@ }, "ub_output_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U622"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14399],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14402],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U622"} + "genargs":{"ID":["String","_U544"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14399],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14402],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -9624,8 +9232,8 @@ }, "ub_output_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U624"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14401],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14403],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U624"} + "genargs":{"ID":["String","_U545"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14401],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14403],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -9633,8 +9241,8 @@ }, "ub_output_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U626"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14401],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14404],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U626"} + "genargs":{"ID":["String","_U546"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14401],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14404],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -9642,8 +9250,8 @@ }, "ub_output_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U628"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14403],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14405],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U628"} + "genargs":{"ID":["String","_U547"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14403],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14405],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -9651,8 +9259,8 @@ }, "ub_output_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U630"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14403],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14406],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U630"} + "genargs":{"ID":["String","_U548"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14403],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14406],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -9660,8 +9268,8 @@ }, "ub_output_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U632"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14405],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14407],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake","verilog_name":"lake__U632"} + "genargs":{"ID":["String","_U549"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[10376],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[9221],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[9216],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[10370],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[14405],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[10372],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[14407],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -9669,14 +9277,6 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U619.out"], - ["ub_output_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U621.out"], - ["ub_output_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U623.out"], - ["ub_output_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U625.out"], - ["ub_output_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U627.out"], - ["ub_output_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U629.out"], - ["ub_output_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U631.out"], - ["ub_output_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U633.out"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], @@ -9754,42 +9354,42 @@ ["op_hcompute_output_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_167_U733":{ - "modref":"global.aff__U719" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_167_U648":{ + "modref":"global.aff__U634" }, - "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U694":{ - "modref":"global.aff__U674" + "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U609":{ + "modref":"global.aff__U589" }, - "chain_en_const_U734":{ + "chain_en_const_U649":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U673":{ - "modref":"global.affine_controller__U635", + "ctrl__U588":{ + "modref":"global.affine_controller__U550", "metadata":{"garnet_remove":true} }, - "ctrl__U718":{ - "modref":"global.affine_controller__U695", + "ctrl__U633":{ + "modref":"global.affine_controller__U610", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[20000],"cycle_stride":[1],"dimensionality":1,"extent":[3136],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[14400],"cycle_stride":[1,32,4032],"dimensionality":3,"extent":[32,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,32]}},"mode":"glb","verilog_name":"glb__U634"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[20000],"cycle_stride":[1],"dimensionality":1,"extent":[3136],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[14400],"cycle_stride":[1,32,4032],"dimensionality":3,"extent":[32,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,64,32]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U718.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_167_U733.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_167_U733.out"], - ["ctrl__U673.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U694.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U694.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U734.out"], - ["self.clk","ctrl__U673.clk"], - ["self.reset","ctrl__U673.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U673.valid"], - ["self.clk","ctrl__U718.clk"], - ["self.reset","ctrl__U718.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U718.valid"], + ["ctrl__U633.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_167_U648.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_167_U648.out"], + ["ctrl__U588.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U609.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U609.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U649.out"], + ["self.clk","ctrl__U588.clk"], + ["self.reset","ctrl__U588.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U588.valid"], + ["self.clk","ctrl__U633.clk"], + ["self.reset","ctrl__U633.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U633.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_glb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -9808,12 +9408,12 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U743":{ + "_U658":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U748":{ + "_U663":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -9834,22 +9434,22 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U737" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U652" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U735"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[20000],"cycle_stride":[1,64,448],"dimensionality":3,"extent":[64,7,7]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U735"} + "genargs":{"ID":["String","_U650"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[20000],"cycle_stride":[1,64,448],"dimensionality":3,"extent":[64,7,7]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U736" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U651" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U738" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U653" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" @@ -9861,22 +9461,22 @@ "modref":"global.cu_op_hcompute_input_glb_stencil" }, "op_hcompute_input_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U746" + "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U661" }, "op_hcompute_input_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U744"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,2,16,256],"dimensionality":4,"extent":[2,8,16,16]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U744"} + "genargs":{"ID":["String","_U659"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,2,16,256],"dimensionality":4,"extent":[2,8,16,16]}},"mode":"lake"} }, "op_hcompute_input_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_glb_stencil_read_start":{ - "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U745" + "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U660" }, "op_hcompute_input_glb_stencil_write_start":{ - "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U747" + "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U662" }, "op_hcompute_kernel_cgra_stencil":{ "modref":"global.cu_op_hcompute_kernel_cgra_stencil" @@ -9888,22 +9488,22 @@ "modref":"global.cu_op_hcompute_kernel_glb_stencil" }, "op_hcompute_kernel_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U741" + "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U656" }, "op_hcompute_kernel_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U739"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,2,16,1024,3072],"dimensionality":5,"extent":[2,8,64,3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U739"} + "genargs":{"ID":["String","_U654"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,2,16,1024,3072],"dimensionality":5,"extent":[2,8,64,3,3]}},"mode":"lake"} }, "op_hcompute_kernel_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_kernel_glb_stencil_read_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U740" + "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U655" }, "op_hcompute_kernel_glb_stencil_write_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U742" + "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U657" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -9964,10 +9564,10 @@ } }, "connections":[ - ["self.clk","_U743.clk"], - ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U743.in"], - ["self.clk","_U748.clk"], - ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U748.in"], + ["self.clk","_U658.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U658.in"], + ["self.clk","_U663.clk"], + ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U663.in"], ["self.clk","input_cgra_stencil.clk"], ["op_hcompute_input_cgra_stencil_1.input_cgra_stencil_op_hcompute_input_cgra_stencil_1_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_1_write"], ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], diff --git a/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll_garnet.json b/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll_garnet.json index 3667016ce..11a0fa4d8 100644 --- a/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll_garnet.json +++ b/aha_garnet_design_new/resnet5_1_unroll/resnet5_1_unroll_garnet.json @@ -232,2231 +232,2231 @@ }, "global":{ "modules":{ - "aff__U119":{ + "aff__U109":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U129":{ + "add_all__U119":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U130":{ + "add_all__U120":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U131":{ + "add_all__U121":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U132":{ + "add_all__U122":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U120":{ + "coeff_0_U110":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U122":{ + "coeff_1_U112":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_2_U124":{ + "coeff_2_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U126":{ + "coeff_3_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "const_term_U128":{ + "const_term_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "mul_d0__U121":{ + "mul_d0__U111":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U123":{ + "mul_d1__U113":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U125":{ + "mul_d2__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U127":{ + "mul_d3__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U121.out","add_all__U129.in0"], - ["mul_d1__U123.out","add_all__U129.in1"], - ["add_all__U130.in0","add_all__U129.out"], - ["mul_d2__U125.out","add_all__U130.in1"], - ["add_all__U131.in0","add_all__U130.out"], - ["mul_d3__U127.out","add_all__U131.in1"], - ["add_all__U132.in0","add_all__U131.out"], - ["const_term_U128.out","add_all__U132.in1"], - ["self.out","add_all__U132.out"], - ["mul_d0__U121.in0","coeff_0_U120.out"], - ["mul_d1__U123.in0","coeff_1_U122.out"], - ["mul_d2__U125.in0","coeff_2_U124.out"], - ["mul_d3__U127.in0","coeff_3_U126.out"], - ["self.d.0","mul_d0__U121.in1"], - ["self.d.1","mul_d1__U123.in1"], - ["self.d.2","mul_d2__U125.in1"], - ["self.d.3","mul_d3__U127.in1"] + ["mul_d0__U111.out","add_all__U119.in0"], + ["mul_d1__U113.out","add_all__U119.in1"], + ["add_all__U120.in0","add_all__U119.out"], + ["mul_d2__U115.out","add_all__U120.in1"], + ["add_all__U121.in0","add_all__U120.out"], + ["mul_d3__U117.out","add_all__U121.in1"], + ["add_all__U122.in0","add_all__U121.out"], + ["const_term_U118.out","add_all__U122.in1"], + ["self.out","add_all__U122.out"], + ["mul_d0__U111.in0","coeff_0_U110.out"], + ["mul_d1__U113.in0","coeff_1_U112.out"], + ["mul_d2__U115.in0","coeff_2_U114.out"], + ["mul_d3__U117.in0","coeff_3_U116.out"], + ["self.d.0","mul_d0__U111.in1"], + ["self.d.1","mul_d1__U113.in1"], + ["self.d.2","mul_d2__U115.in1"], + ["self.d.3","mul_d3__U117.in1"] ] }, - "aff__U142":{ + "aff__U132":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U152":{ + "add_all__U142":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U153":{ + "add_all__U143":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U154":{ + "add_all__U144":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U155":{ + "add_all__U145":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U143":{ + "coeff_0_U133":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U145":{ + "coeff_1_U135":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U147":{ + "coeff_2_U137":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U149":{ + "coeff_3_U139":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U151":{ + "const_term_U141":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U144":{ + "mul_d0__U134":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U146":{ + "mul_d1__U136":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U148":{ + "mul_d2__U138":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U150":{ + "mul_d3__U140":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U144.out","add_all__U152.in0"], - ["mul_d1__U146.out","add_all__U152.in1"], - ["add_all__U153.in0","add_all__U152.out"], - ["mul_d2__U148.out","add_all__U153.in1"], - ["add_all__U154.in0","add_all__U153.out"], - ["mul_d3__U150.out","add_all__U154.in1"], - ["add_all__U155.in0","add_all__U154.out"], - ["const_term_U151.out","add_all__U155.in1"], - ["self.out","add_all__U155.out"], - ["mul_d0__U144.in0","coeff_0_U143.out"], - ["mul_d1__U146.in0","coeff_1_U145.out"], - ["mul_d2__U148.in0","coeff_2_U147.out"], - ["mul_d3__U150.in0","coeff_3_U149.out"], - ["self.d.0","mul_d0__U144.in1"], - ["self.d.1","mul_d1__U146.in1"], - ["self.d.2","mul_d2__U148.in1"], - ["self.d.3","mul_d3__U150.in1"] + ["mul_d0__U134.out","add_all__U142.in0"], + ["mul_d1__U136.out","add_all__U142.in1"], + ["add_all__U143.in0","add_all__U142.out"], + ["mul_d2__U138.out","add_all__U143.in1"], + ["add_all__U144.in0","add_all__U143.out"], + ["mul_d3__U140.out","add_all__U144.in1"], + ["add_all__U145.in0","add_all__U144.out"], + ["const_term_U141.out","add_all__U145.in1"], + ["self.out","add_all__U145.out"], + ["mul_d0__U134.in0","coeff_0_U133.out"], + ["mul_d1__U136.in0","coeff_1_U135.out"], + ["mul_d2__U138.in0","coeff_2_U137.out"], + ["mul_d3__U140.in0","coeff_3_U139.out"], + ["self.d.0","mul_d0__U134.in1"], + ["self.d.1","mul_d1__U136.in1"], + ["self.d.2","mul_d2__U138.in1"], + ["self.d.3","mul_d3__U140.in1"] ] }, - "aff__U158":{ + "aff__U148":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U172":{ + "add_all__U162":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U173":{ + "add_all__U163":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U174":{ + "add_all__U164":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U175":{ + "add_all__U165":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U176":{ + "add_all__U166":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U177":{ + "add_all__U167":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U159":{ + "coeff_0_U149":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U161":{ + "coeff_1_U151":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U163":{ + "coeff_2_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U165":{ + "coeff_3_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U167":{ + "coeff_4_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_5_U169":{ + "coeff_5_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U171":{ + "const_term_U161":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U160":{ + "mul_d0__U150":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U162":{ + "mul_d1__U152":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U164":{ + "mul_d2__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U166":{ + "mul_d3__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U168":{ + "mul_d4__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U170":{ + "mul_d5__U160":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U160.out","add_all__U172.in0"], - ["mul_d1__U162.out","add_all__U172.in1"], - ["add_all__U173.in0","add_all__U172.out"], - ["mul_d2__U164.out","add_all__U173.in1"], - ["add_all__U174.in0","add_all__U173.out"], - ["mul_d3__U166.out","add_all__U174.in1"], - ["add_all__U175.in0","add_all__U174.out"], - ["mul_d4__U168.out","add_all__U175.in1"], - ["add_all__U176.in0","add_all__U175.out"], - ["mul_d5__U170.out","add_all__U176.in1"], - ["add_all__U177.in0","add_all__U176.out"], - ["const_term_U171.out","add_all__U177.in1"], - ["self.out","add_all__U177.out"], - ["mul_d0__U160.in0","coeff_0_U159.out"], - ["mul_d1__U162.in0","coeff_1_U161.out"], - ["mul_d2__U164.in0","coeff_2_U163.out"], - ["mul_d3__U166.in0","coeff_3_U165.out"], - ["mul_d4__U168.in0","coeff_4_U167.out"], - ["mul_d5__U170.in0","coeff_5_U169.out"], - ["self.d.0","mul_d0__U160.in1"], - ["self.d.1","mul_d1__U162.in1"], - ["self.d.2","mul_d2__U164.in1"], - ["self.d.3","mul_d3__U166.in1"], - ["self.d.4","mul_d4__U168.in1"], - ["self.d.5","mul_d5__U170.in1"] + ["mul_d0__U150.out","add_all__U162.in0"], + ["mul_d1__U152.out","add_all__U162.in1"], + ["add_all__U163.in0","add_all__U162.out"], + ["mul_d2__U154.out","add_all__U163.in1"], + ["add_all__U164.in0","add_all__U163.out"], + ["mul_d3__U156.out","add_all__U164.in1"], + ["add_all__U165.in0","add_all__U164.out"], + ["mul_d4__U158.out","add_all__U165.in1"], + ["add_all__U166.in0","add_all__U165.out"], + ["mul_d5__U160.out","add_all__U166.in1"], + ["add_all__U167.in0","add_all__U166.out"], + ["const_term_U161.out","add_all__U167.in1"], + ["self.out","add_all__U167.out"], + ["mul_d0__U150.in0","coeff_0_U149.out"], + ["mul_d1__U152.in0","coeff_1_U151.out"], + ["mul_d2__U154.in0","coeff_2_U153.out"], + ["mul_d3__U156.in0","coeff_3_U155.out"], + ["mul_d4__U158.in0","coeff_4_U157.out"], + ["mul_d5__U160.in0","coeff_5_U159.out"], + ["self.d.0","mul_d0__U150.in1"], + ["self.d.1","mul_d1__U152.in1"], + ["self.d.2","mul_d2__U154.in1"], + ["self.d.3","mul_d3__U156.in1"], + ["self.d.4","mul_d4__U158.in1"], + ["self.d.5","mul_d5__U160.in1"] ] }, - "aff__U18":{ + "aff__U186":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] + ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U28":{ + "add_all__U200":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U201":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U202":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U29":{ + "add_all__U203":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U30":{ + "add_all__U204":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U31":{ + "add_all__U205":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U19":{ + "coeff_0_U187":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U21":{ + "coeff_1_U189":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_2_U191":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000400"]} + }, + "coeff_3_U193":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U23":{ + "coeff_4_U195":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U25":{ + "coeff_5_U197":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U27":{ + "const_term_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U20":{ + "mul_d0__U188":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U190":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U192":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U22":{ + "mul_d3__U194":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U24":{ + "mul_d4__U196":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U26":{ + "mul_d5__U198":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] + ["mul_d0__U188.out","add_all__U200.in0"], + ["mul_d1__U190.out","add_all__U200.in1"], + ["add_all__U201.in0","add_all__U200.out"], + ["mul_d2__U192.out","add_all__U201.in1"], + ["add_all__U202.in0","add_all__U201.out"], + ["mul_d3__U194.out","add_all__U202.in1"], + ["add_all__U203.in0","add_all__U202.out"], + ["mul_d4__U196.out","add_all__U203.in1"], + ["add_all__U204.in0","add_all__U203.out"], + ["mul_d5__U198.out","add_all__U204.in1"], + ["add_all__U205.in0","add_all__U204.out"], + ["const_term_U199.out","add_all__U205.in1"], + ["self.out","add_all__U205.out"], + ["mul_d0__U188.in0","coeff_0_U187.out"], + ["mul_d1__U190.in0","coeff_1_U189.out"], + ["mul_d2__U192.in0","coeff_2_U191.out"], + ["mul_d3__U194.in0","coeff_3_U193.out"], + ["mul_d4__U196.in0","coeff_4_U195.out"], + ["mul_d5__U198.in0","coeff_5_U197.out"], + ["self.d.0","mul_d0__U188.in1"], + ["self.d.1","mul_d1__U190.in1"], + ["self.d.2","mul_d2__U192.in1"], + ["self.d.3","mul_d3__U194.in1"], + ["self.d.4","mul_d4__U196.in1"], + ["self.d.5","mul_d5__U198.in1"] ] }, - "aff__U196":{ + "aff__U273":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",6,["Array",32,"BitIn"]]] + ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U210":{ + "add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U211":{ + "add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U212":{ + "add_all__U287":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U213":{ + "add_all__U288":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U214":{ + "add_all__U289":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U215":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U197":{ + "coeff_0_U274":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U199":{ + "coeff_1_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U201":{ + "coeff_2_U278":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U203":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "coeff_4_U205":{ + "coeff_3_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U207":{ + "coeff_4_U282":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "const_term_U209":{ + "const_term_U284":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U198":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U200":{ + "mul_d0__U275":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U202":{ + "mul_d1__U277":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U204":{ + "mul_d2__U279":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U206":{ + "mul_d3__U281":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U208":{ + "mul_d4__U283":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U198.out","add_all__U210.in0"], - ["mul_d1__U200.out","add_all__U210.in1"], - ["add_all__U211.in0","add_all__U210.out"], - ["mul_d2__U202.out","add_all__U211.in1"], - ["add_all__U212.in0","add_all__U211.out"], - ["mul_d3__U204.out","add_all__U212.in1"], - ["add_all__U213.in0","add_all__U212.out"], - ["mul_d4__U206.out","add_all__U213.in1"], - ["add_all__U214.in0","add_all__U213.out"], - ["mul_d5__U208.out","add_all__U214.in1"], - ["add_all__U215.in0","add_all__U214.out"], - ["const_term_U209.out","add_all__U215.in1"], - ["self.out","add_all__U215.out"], - ["mul_d0__U198.in0","coeff_0_U197.out"], - ["mul_d1__U200.in0","coeff_1_U199.out"], - ["mul_d2__U202.in0","coeff_2_U201.out"], - ["mul_d3__U204.in0","coeff_3_U203.out"], - ["mul_d4__U206.in0","coeff_4_U205.out"], - ["mul_d5__U208.in0","coeff_5_U207.out"], - ["self.d.0","mul_d0__U198.in1"], - ["self.d.1","mul_d1__U200.in1"], - ["self.d.2","mul_d2__U202.in1"], - ["self.d.3","mul_d3__U204.in1"], - ["self.d.4","mul_d4__U206.in1"], - ["self.d.5","mul_d5__U208.in1"] + ["mul_d0__U275.out","add_all__U285.in0"], + ["mul_d1__U277.out","add_all__U285.in1"], + ["add_all__U286.in0","add_all__U285.out"], + ["mul_d2__U279.out","add_all__U286.in1"], + ["add_all__U287.in0","add_all__U286.out"], + ["mul_d3__U281.out","add_all__U287.in1"], + ["add_all__U288.in0","add_all__U287.out"], + ["mul_d4__U283.out","add_all__U288.in1"], + ["add_all__U289.in0","add_all__U288.out"], + ["const_term_U284.out","add_all__U289.in1"], + ["self.out","add_all__U289.out"], + ["mul_d0__U275.in0","coeff_0_U274.out"], + ["mul_d1__U277.in0","coeff_1_U276.out"], + ["mul_d2__U279.in0","coeff_2_U278.out"], + ["mul_d3__U281.in0","coeff_3_U280.out"], + ["mul_d4__U283.in0","coeff_4_U282.out"], + ["self.d.0","mul_d0__U275.in1"], + ["self.d.1","mul_d1__U277.in1"], + ["self.d.2","mul_d2__U279.in1"], + ["self.d.3","mul_d3__U281.in1"], + ["self.d.4","mul_d4__U283.in1"] ] }, - "aff__U348":{ + "aff__U303":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U360":{ + "add_all__U315":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U361":{ + "add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U362":{ + "add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U363":{ + "add_all__U318":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U364":{ + "add_all__U319":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U349":{ + "coeff_0_U304":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U351":{ + "coeff_1_U306":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U353":{ + "coeff_2_U308":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U355":{ + "coeff_3_U310":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U357":{ + "coeff_4_U312":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U359":{ + "const_term_U314":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U350":{ + "mul_d0__U305":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U352":{ + "mul_d1__U307":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U354":{ + "mul_d2__U309":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U356":{ + "mul_d3__U311":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U358":{ + "mul_d4__U313":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U350.out","add_all__U360.in0"], - ["mul_d1__U352.out","add_all__U360.in1"], - ["add_all__U361.in0","add_all__U360.out"], - ["mul_d2__U354.out","add_all__U361.in1"], - ["add_all__U362.in0","add_all__U361.out"], - ["mul_d3__U356.out","add_all__U362.in1"], - ["add_all__U363.in0","add_all__U362.out"], - ["mul_d4__U358.out","add_all__U363.in1"], - ["add_all__U364.in0","add_all__U363.out"], - ["const_term_U359.out","add_all__U364.in1"], - ["self.out","add_all__U364.out"], - ["mul_d0__U350.in0","coeff_0_U349.out"], - ["mul_d1__U352.in0","coeff_1_U351.out"], - ["mul_d2__U354.in0","coeff_2_U353.out"], - ["mul_d3__U356.in0","coeff_3_U355.out"], - ["mul_d4__U358.in0","coeff_4_U357.out"], - ["self.d.0","mul_d0__U350.in1"], - ["self.d.1","mul_d1__U352.in1"], - ["self.d.2","mul_d2__U354.in1"], - ["self.d.3","mul_d3__U356.in1"], - ["self.d.4","mul_d4__U358.in1"] + ["mul_d0__U305.out","add_all__U315.in0"], + ["mul_d1__U307.out","add_all__U315.in1"], + ["add_all__U316.in0","add_all__U315.out"], + ["mul_d2__U309.out","add_all__U316.in1"], + ["add_all__U317.in0","add_all__U316.out"], + ["mul_d3__U311.out","add_all__U317.in1"], + ["add_all__U318.in0","add_all__U317.out"], + ["mul_d4__U313.out","add_all__U318.in1"], + ["add_all__U319.in0","add_all__U318.out"], + ["const_term_U314.out","add_all__U319.in1"], + ["self.out","add_all__U319.out"], + ["mul_d0__U305.in0","coeff_0_U304.out"], + ["mul_d1__U307.in0","coeff_1_U306.out"], + ["mul_d2__U309.in0","coeff_2_U308.out"], + ["mul_d3__U311.in0","coeff_3_U310.out"], + ["mul_d4__U313.in0","coeff_4_U312.out"], + ["self.d.0","mul_d0__U305.in1"], + ["self.d.1","mul_d1__U307.in1"], + ["self.d.2","mul_d2__U309.in1"], + ["self.d.3","mul_d3__U311.in1"], + ["self.d.4","mul_d4__U313.in1"] ] }, - "aff__U378":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",5,["Array",32,"BitIn"]]] + ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U390":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U391":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U392":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U393":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U394":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U379":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U381":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U383":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "coeff_3_U385":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000009"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U387":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000240"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U389":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U380":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U382":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U384":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U386":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U388":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U380.out","add_all__U390.in0"], - ["mul_d1__U382.out","add_all__U390.in1"], - ["add_all__U391.in0","add_all__U390.out"], - ["mul_d2__U384.out","add_all__U391.in1"], - ["add_all__U392.in0","add_all__U391.out"], - ["mul_d3__U386.out","add_all__U392.in1"], - ["add_all__U393.in0","add_all__U392.out"], - ["mul_d4__U388.out","add_all__U393.in1"], - ["add_all__U394.in0","add_all__U393.out"], - ["const_term_U389.out","add_all__U394.in1"], - ["self.out","add_all__U394.out"], - ["mul_d0__U380.in0","coeff_0_U379.out"], - ["mul_d1__U382.in0","coeff_1_U381.out"], - ["mul_d2__U384.in0","coeff_2_U383.out"], - ["mul_d3__U386.in0","coeff_3_U385.out"], - ["mul_d4__U388.in0","coeff_4_U387.out"], - ["self.d.0","mul_d0__U380.in1"], - ["self.d.1","mul_d1__U382.in1"], - ["self.d.2","mul_d2__U384.in1"], - ["self.d.3","mul_d3__U386.in1"], - ["self.d.4","mul_d4__U388.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U397":{ + "aff__U322":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U415":{ + "add_all__U340":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U341":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U342":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U418":{ + "add_all__U343":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U419":{ + "add_all__U344":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U420":{ + "add_all__U345":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U421":{ + "add_all__U346":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U422":{ + "add_all__U347":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U398":{ + "coeff_0_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U400":{ + "coeff_1_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U402":{ + "coeff_2_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U404":{ + "coeff_3_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000180"]} }, - "coeff_4_U406":{ + "coeff_4_U331":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_5_U408":{ + "coeff_5_U333":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_6_U410":{ + "coeff_6_U335":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_7_U412":{ + "coeff_7_U337":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U414":{ + "const_term_U339":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U399":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U401":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U403":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U405":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d4__U407":{ + "mul_d0__U324":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U409":{ + "mul_d1__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U411":{ + "mul_d2__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U413":{ + "mul_d3__U330":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U399.out","add_all__U415.in0"], - ["mul_d1__U401.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d2__U403.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["mul_d3__U405.out","add_all__U417.in1"], - ["add_all__U418.in0","add_all__U417.out"], - ["mul_d4__U407.out","add_all__U418.in1"], - ["add_all__U419.in0","add_all__U418.out"], - ["mul_d5__U409.out","add_all__U419.in1"], - ["add_all__U420.in0","add_all__U419.out"], - ["mul_d6__U411.out","add_all__U420.in1"], - ["add_all__U421.in0","add_all__U420.out"], - ["mul_d7__U413.out","add_all__U421.in1"], - ["add_all__U422.in0","add_all__U421.out"], - ["const_term_U414.out","add_all__U422.in1"], - ["self.out","add_all__U422.out"], - ["mul_d0__U399.in0","coeff_0_U398.out"], - ["mul_d1__U401.in0","coeff_1_U400.out"], - ["mul_d2__U403.in0","coeff_2_U402.out"], - ["mul_d3__U405.in0","coeff_3_U404.out"], - ["mul_d4__U407.in0","coeff_4_U406.out"], - ["mul_d5__U409.in0","coeff_5_U408.out"], - ["mul_d6__U411.in0","coeff_6_U410.out"], - ["mul_d7__U413.in0","coeff_7_U412.out"], - ["self.d.0","mul_d0__U399.in1"], - ["self.d.1","mul_d1__U401.in1"], - ["self.d.2","mul_d2__U403.in1"], - ["self.d.3","mul_d3__U405.in1"], - ["self.d.4","mul_d4__U407.in1"], - ["self.d.5","mul_d5__U409.in1"], - ["self.d.6","mul_d6__U411.in1"], - ["self.d.7","mul_d7__U413.in1"] - ] - }, - "aff__U41":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U51":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U52":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U53":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U54":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U42":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U44":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U46":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U48":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} - }, - "const_term_U50":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U43":{ + "mul_d4__U332":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d5__U334":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d6__U336":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d7__U338":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U324.out","add_all__U340.in0"], + ["mul_d1__U326.out","add_all__U340.in1"], + ["add_all__U341.in0","add_all__U340.out"], + ["mul_d2__U328.out","add_all__U341.in1"], + ["add_all__U342.in0","add_all__U341.out"], + ["mul_d3__U330.out","add_all__U342.in1"], + ["add_all__U343.in0","add_all__U342.out"], + ["mul_d4__U332.out","add_all__U343.in1"], + ["add_all__U344.in0","add_all__U343.out"], + ["mul_d5__U334.out","add_all__U344.in1"], + ["add_all__U345.in0","add_all__U344.out"], + ["mul_d6__U336.out","add_all__U345.in1"], + ["add_all__U346.in0","add_all__U345.out"], + ["mul_d7__U338.out","add_all__U346.in1"], + ["add_all__U347.in0","add_all__U346.out"], + ["const_term_U339.out","add_all__U347.in1"], + ["self.out","add_all__U347.out"], + ["mul_d0__U324.in0","coeff_0_U323.out"], + ["mul_d1__U326.in0","coeff_1_U325.out"], + ["mul_d2__U328.in0","coeff_2_U327.out"], + ["mul_d3__U330.in0","coeff_3_U329.out"], + ["mul_d4__U332.in0","coeff_4_U331.out"], + ["mul_d5__U334.in0","coeff_5_U333.out"], + ["mul_d6__U336.in0","coeff_6_U335.out"], + ["mul_d7__U338.in0","coeff_7_U337.out"], + ["self.d.0","mul_d0__U324.in1"], + ["self.d.1","mul_d1__U326.in1"], + ["self.d.2","mul_d2__U328.in1"], + ["self.d.3","mul_d3__U330.in1"], + ["self.d.4","mul_d4__U332.in1"], + ["self.d.5","mul_d5__U334.in1"], + ["self.d.6","mul_d6__U336.in1"], + ["self.d.7","mul_d7__U338.in1"] ] }, - "aff__U454":{ + "aff__U379":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U472":{ + "add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U473":{ + "add_all__U398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U474":{ + "add_all__U399":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U475":{ + "add_all__U400":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U476":{ + "add_all__U401":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U477":{ + "add_all__U402":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U478":{ + "add_all__U403":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U479":{ + "add_all__U404":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U455":{ + "coeff_0_U380":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U457":{ + "coeff_1_U382":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U459":{ + "coeff_2_U384":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U461":{ + "coeff_3_U386":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U463":{ + "coeff_4_U388":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U465":{ + "coeff_5_U390":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U467":{ + "coeff_6_U392":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U469":{ + "coeff_7_U394":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U471":{ + "const_term_U396":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U456":{ + "mul_d0__U381":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U458":{ + "mul_d1__U383":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U460":{ + "mul_d2__U385":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U462":{ + "mul_d3__U387":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U464":{ + "mul_d4__U389":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U466":{ + "mul_d5__U391":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U468":{ + "mul_d6__U393":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U470":{ + "mul_d7__U395":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U456.out","add_all__U472.in0"], - ["mul_d1__U458.out","add_all__U472.in1"], - ["add_all__U473.in0","add_all__U472.out"], - ["mul_d2__U460.out","add_all__U473.in1"], - ["add_all__U474.in0","add_all__U473.out"], - ["mul_d3__U462.out","add_all__U474.in1"], - ["add_all__U475.in0","add_all__U474.out"], - ["mul_d4__U464.out","add_all__U475.in1"], - ["add_all__U476.in0","add_all__U475.out"], - ["mul_d5__U466.out","add_all__U476.in1"], - ["add_all__U477.in0","add_all__U476.out"], - ["mul_d6__U468.out","add_all__U477.in1"], - ["add_all__U478.in0","add_all__U477.out"], - ["mul_d7__U470.out","add_all__U478.in1"], - ["add_all__U479.in0","add_all__U478.out"], - ["const_term_U471.out","add_all__U479.in1"], - ["self.out","add_all__U479.out"], - ["mul_d0__U456.in0","coeff_0_U455.out"], - ["mul_d1__U458.in0","coeff_1_U457.out"], - ["mul_d2__U460.in0","coeff_2_U459.out"], - ["mul_d3__U462.in0","coeff_3_U461.out"], - ["mul_d4__U464.in0","coeff_4_U463.out"], - ["mul_d5__U466.in0","coeff_5_U465.out"], - ["mul_d6__U468.in0","coeff_6_U467.out"], - ["mul_d7__U470.in0","coeff_7_U469.out"], - ["self.d.0","mul_d0__U456.in1"], - ["self.d.1","mul_d1__U458.in1"], - ["self.d.2","mul_d2__U460.in1"], - ["self.d.3","mul_d3__U462.in1"], - ["self.d.4","mul_d4__U464.in1"], - ["self.d.5","mul_d5__U466.in1"], - ["self.d.6","mul_d6__U468.in1"], - ["self.d.7","mul_d7__U470.in1"] + ["mul_d0__U381.out","add_all__U397.in0"], + ["mul_d1__U383.out","add_all__U397.in1"], + ["add_all__U398.in0","add_all__U397.out"], + ["mul_d2__U385.out","add_all__U398.in1"], + ["add_all__U399.in0","add_all__U398.out"], + ["mul_d3__U387.out","add_all__U399.in1"], + ["add_all__U400.in0","add_all__U399.out"], + ["mul_d4__U389.out","add_all__U400.in1"], + ["add_all__U401.in0","add_all__U400.out"], + ["mul_d5__U391.out","add_all__U401.in1"], + ["add_all__U402.in0","add_all__U401.out"], + ["mul_d6__U393.out","add_all__U402.in1"], + ["add_all__U403.in0","add_all__U402.out"], + ["mul_d7__U395.out","add_all__U403.in1"], + ["add_all__U404.in0","add_all__U403.out"], + ["const_term_U396.out","add_all__U404.in1"], + ["self.out","add_all__U404.out"], + ["mul_d0__U381.in0","coeff_0_U380.out"], + ["mul_d1__U383.in0","coeff_1_U382.out"], + ["mul_d2__U385.in0","coeff_2_U384.out"], + ["mul_d3__U387.in0","coeff_3_U386.out"], + ["mul_d4__U389.in0","coeff_4_U388.out"], + ["mul_d5__U391.in0","coeff_5_U390.out"], + ["mul_d6__U393.in0","coeff_6_U392.out"], + ["mul_d7__U395.in0","coeff_7_U394.out"], + ["self.d.0","mul_d0__U381.in1"], + ["self.d.1","mul_d1__U383.in1"], + ["self.d.2","mul_d2__U385.in1"], + ["self.d.3","mul_d3__U387.in1"], + ["self.d.4","mul_d4__U389.in1"], + ["self.d.5","mul_d5__U391.in1"], + ["self.d.6","mul_d6__U393.in1"], + ["self.d.7","mul_d7__U395.in1"] ] }, - "aff__U484":{ + "aff__U408":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U496":{ + "add_all__U420":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U497":{ + "add_all__U421":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U498":{ + "add_all__U422":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U499":{ + "add_all__U423":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U500":{ + "add_all__U424":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U485":{ + "coeff_0_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U487":{ + "coeff_1_U411":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "coeff_2_U489":{ + "coeff_2_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U491":{ + "coeff_3_U415":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U493":{ + "coeff_4_U417":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "const_term_U495":{ + "const_term_U419":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "mul_d0__U486":{ + "mul_d0__U410":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U488":{ + "mul_d1__U412":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U490":{ + "mul_d2__U414":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U492":{ + "mul_d3__U416":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U494":{ + "mul_d4__U418":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U486.out","add_all__U496.in0"], - ["mul_d1__U488.out","add_all__U496.in1"], - ["add_all__U497.in0","add_all__U496.out"], - ["mul_d2__U490.out","add_all__U497.in1"], - ["add_all__U498.in0","add_all__U497.out"], - ["mul_d3__U492.out","add_all__U498.in1"], - ["add_all__U499.in0","add_all__U498.out"], - ["mul_d4__U494.out","add_all__U499.in1"], - ["add_all__U500.in0","add_all__U499.out"], - ["const_term_U495.out","add_all__U500.in1"], - ["self.out","add_all__U500.out"], - ["mul_d0__U486.in0","coeff_0_U485.out"], - ["mul_d1__U488.in0","coeff_1_U487.out"], - ["mul_d2__U490.in0","coeff_2_U489.out"], - ["mul_d3__U492.in0","coeff_3_U491.out"], - ["mul_d4__U494.in0","coeff_4_U493.out"], - ["self.d.0","mul_d0__U486.in1"], - ["self.d.1","mul_d1__U488.in1"], - ["self.d.2","mul_d2__U490.in1"], - ["self.d.3","mul_d3__U492.in1"], - ["self.d.4","mul_d4__U494.in1"] + ["mul_d0__U410.out","add_all__U420.in0"], + ["mul_d1__U412.out","add_all__U420.in1"], + ["add_all__U421.in0","add_all__U420.out"], + ["mul_d2__U414.out","add_all__U421.in1"], + ["add_all__U422.in0","add_all__U421.out"], + ["mul_d3__U416.out","add_all__U422.in1"], + ["add_all__U423.in0","add_all__U422.out"], + ["mul_d4__U418.out","add_all__U423.in1"], + ["add_all__U424.in0","add_all__U423.out"], + ["const_term_U419.out","add_all__U424.in1"], + ["self.out","add_all__U424.out"], + ["mul_d0__U410.in0","coeff_0_U409.out"], + ["mul_d1__U412.in0","coeff_1_U411.out"], + ["mul_d2__U414.in0","coeff_2_U413.out"], + ["mul_d3__U416.in0","coeff_3_U415.out"], + ["mul_d4__U418.in0","coeff_4_U417.out"], + ["self.d.0","mul_d0__U410.in1"], + ["self.d.1","mul_d1__U412.in1"], + ["self.d.2","mul_d2__U414.in1"], + ["self.d.3","mul_d3__U416.in1"], + ["self.d.4","mul_d4__U418.in1"] ] }, - "aff__U514":{ + "aff__U438":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U526":{ + "add_all__U450":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U527":{ + "add_all__U451":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U528":{ + "add_all__U452":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U529":{ + "add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U530":{ + "add_all__U454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U515":{ + "coeff_0_U439":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U517":{ + "coeff_1_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U519":{ + "coeff_2_U443":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U521":{ + "coeff_3_U445":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U523":{ + "coeff_4_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U525":{ + "const_term_U449":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U516":{ + "mul_d0__U440":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U518":{ + "mul_d1__U442":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U520":{ + "mul_d2__U444":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U522":{ + "mul_d3__U446":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U524":{ + "mul_d4__U448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U516.out","add_all__U526.in0"], - ["mul_d1__U518.out","add_all__U526.in1"], - ["add_all__U527.in0","add_all__U526.out"], - ["mul_d2__U520.out","add_all__U527.in1"], - ["add_all__U528.in0","add_all__U527.out"], - ["mul_d3__U522.out","add_all__U528.in1"], - ["add_all__U529.in0","add_all__U528.out"], - ["mul_d4__U524.out","add_all__U529.in1"], - ["add_all__U530.in0","add_all__U529.out"], - ["const_term_U525.out","add_all__U530.in1"], - ["self.out","add_all__U530.out"], - ["mul_d0__U516.in0","coeff_0_U515.out"], - ["mul_d1__U518.in0","coeff_1_U517.out"], - ["mul_d2__U520.in0","coeff_2_U519.out"], - ["mul_d3__U522.in0","coeff_3_U521.out"], - ["mul_d4__U524.in0","coeff_4_U523.out"], - ["self.d.0","mul_d0__U516.in1"], - ["self.d.1","mul_d1__U518.in1"], - ["self.d.2","mul_d2__U520.in1"], - ["self.d.3","mul_d3__U522.in1"], - ["self.d.4","mul_d4__U524.in1"] + ["mul_d0__U440.out","add_all__U450.in0"], + ["mul_d1__U442.out","add_all__U450.in1"], + ["add_all__U451.in0","add_all__U450.out"], + ["mul_d2__U444.out","add_all__U451.in1"], + ["add_all__U452.in0","add_all__U451.out"], + ["mul_d3__U446.out","add_all__U452.in1"], + ["add_all__U453.in0","add_all__U452.out"], + ["mul_d4__U448.out","add_all__U453.in1"], + ["add_all__U454.in0","add_all__U453.out"], + ["const_term_U449.out","add_all__U454.in1"], + ["self.out","add_all__U454.out"], + ["mul_d0__U440.in0","coeff_0_U439.out"], + ["mul_d1__U442.in0","coeff_1_U441.out"], + ["mul_d2__U444.in0","coeff_2_U443.out"], + ["mul_d3__U446.in0","coeff_3_U445.out"], + ["mul_d4__U448.in0","coeff_4_U447.out"], + ["self.d.0","mul_d0__U440.in1"], + ["self.d.1","mul_d1__U442.in1"], + ["self.d.2","mul_d2__U444.in1"], + ["self.d.3","mul_d3__U446.in1"], + ["self.d.4","mul_d4__U448.in1"] ] }, - "aff__U533":{ + "aff__U457":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U551":{ + "add_all__U475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U552":{ + "add_all__U476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U553":{ + "add_all__U477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U554":{ + "add_all__U478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U555":{ + "add_all__U479":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U556":{ + "add_all__U480":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U557":{ + "add_all__U481":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U558":{ + "add_all__U482":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U534":{ + "coeff_0_U458":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U536":{ + "coeff_1_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U538":{ + "coeff_2_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U540":{ + "coeff_3_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000180"]} }, - "coeff_4_U542":{ + "coeff_4_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_5_U544":{ + "coeff_5_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_6_U546":{ + "coeff_6_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_7_U548":{ + "coeff_7_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U550":{ + "const_term_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U535":{ + "mul_d0__U459":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U537":{ + "mul_d1__U461":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U539":{ + "mul_d2__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U541":{ + "mul_d3__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U543":{ + "mul_d4__U467":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U545":{ + "mul_d5__U469":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U547":{ + "mul_d6__U471":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U549":{ + "mul_d7__U473":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U535.out","add_all__U551.in0"], - ["mul_d1__U537.out","add_all__U551.in1"], - ["add_all__U552.in0","add_all__U551.out"], - ["mul_d2__U539.out","add_all__U552.in1"], - ["add_all__U553.in0","add_all__U552.out"], - ["mul_d3__U541.out","add_all__U553.in1"], - ["add_all__U554.in0","add_all__U553.out"], - ["mul_d4__U543.out","add_all__U554.in1"], - ["add_all__U555.in0","add_all__U554.out"], - ["mul_d5__U545.out","add_all__U555.in1"], - ["add_all__U556.in0","add_all__U555.out"], - ["mul_d6__U547.out","add_all__U556.in1"], - ["add_all__U557.in0","add_all__U556.out"], - ["mul_d7__U549.out","add_all__U557.in1"], - ["add_all__U558.in0","add_all__U557.out"], - ["const_term_U550.out","add_all__U558.in1"], - ["self.out","add_all__U558.out"], - ["mul_d0__U535.in0","coeff_0_U534.out"], - ["mul_d1__U537.in0","coeff_1_U536.out"], - ["mul_d2__U539.in0","coeff_2_U538.out"], - ["mul_d3__U541.in0","coeff_3_U540.out"], - ["mul_d4__U543.in0","coeff_4_U542.out"], - ["mul_d5__U545.in0","coeff_5_U544.out"], - ["mul_d6__U547.in0","coeff_6_U546.out"], - ["mul_d7__U549.in0","coeff_7_U548.out"], - ["self.d.0","mul_d0__U535.in1"], - ["self.d.1","mul_d1__U537.in1"], - ["self.d.2","mul_d2__U539.in1"], - ["self.d.3","mul_d3__U541.in1"], - ["self.d.4","mul_d4__U543.in1"], - ["self.d.5","mul_d5__U545.in1"], - ["self.d.6","mul_d6__U547.in1"], - ["self.d.7","mul_d7__U549.in1"] + ["mul_d0__U459.out","add_all__U475.in0"], + ["mul_d1__U461.out","add_all__U475.in1"], + ["add_all__U476.in0","add_all__U475.out"], + ["mul_d2__U463.out","add_all__U476.in1"], + ["add_all__U477.in0","add_all__U476.out"], + ["mul_d3__U465.out","add_all__U477.in1"], + ["add_all__U478.in0","add_all__U477.out"], + ["mul_d4__U467.out","add_all__U478.in1"], + ["add_all__U479.in0","add_all__U478.out"], + ["mul_d5__U469.out","add_all__U479.in1"], + ["add_all__U480.in0","add_all__U479.out"], + ["mul_d6__U471.out","add_all__U480.in1"], + ["add_all__U481.in0","add_all__U480.out"], + ["mul_d7__U473.out","add_all__U481.in1"], + ["add_all__U482.in0","add_all__U481.out"], + ["const_term_U474.out","add_all__U482.in1"], + ["self.out","add_all__U482.out"], + ["mul_d0__U459.in0","coeff_0_U458.out"], + ["mul_d1__U461.in0","coeff_1_U460.out"], + ["mul_d2__U463.in0","coeff_2_U462.out"], + ["mul_d3__U465.in0","coeff_3_U464.out"], + ["mul_d4__U467.in0","coeff_4_U466.out"], + ["mul_d5__U469.in0","coeff_5_U468.out"], + ["mul_d6__U471.in0","coeff_6_U470.out"], + ["mul_d7__U473.in0","coeff_7_U472.out"], + ["self.d.0","mul_d0__U459.in1"], + ["self.d.1","mul_d1__U461.in1"], + ["self.d.2","mul_d2__U463.in1"], + ["self.d.3","mul_d3__U465.in1"], + ["self.d.4","mul_d4__U467.in1"], + ["self.d.5","mul_d5__U469.in1"], + ["self.d.6","mul_d6__U471.in1"], + ["self.d.7","mul_d7__U473.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U71":{ + "add_all__U62":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U72":{ + "add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U73":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U74":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U70":{ + "const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U71.in0"], - ["mul_d1__U61.out","add_all__U71.in1"], - ["add_all__U72.in0","add_all__U71.out"], - ["mul_d2__U63.out","add_all__U72.in1"], - ["add_all__U73.in0","add_all__U72.out"], - ["mul_d3__U65.out","add_all__U73.in1"], - ["add_all__U74.in0","add_all__U73.out"], - ["mul_d4__U67.out","add_all__U74.in1"], - ["add_all__U75.in0","add_all__U74.out"], - ["mul_d5__U69.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["const_term_U70.out","add_all__U76.in1"], - ["self.out","add_all__U76.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"] + ["mul_d0__U50.out","add_all__U62.in0"], + ["mul_d1__U52.out","add_all__U62.in1"], + ["add_all__U63.in0","add_all__U62.out"], + ["mul_d2__U54.out","add_all__U63.in1"], + ["add_all__U64.in0","add_all__U63.out"], + ["mul_d3__U56.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["mul_d4__U58.out","add_all__U65.in1"], + ["add_all__U66.in0","add_all__U65.out"], + ["mul_d5__U60.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["const_term_U61.out","add_all__U67.in1"], + ["self.out","add_all__U67.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"] ] }, - "aff__U590":{ + "aff__U514":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U608":{ + "add_all__U532":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U609":{ + "add_all__U533":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U610":{ + "add_all__U534":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U611":{ + "add_all__U535":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U612":{ + "add_all__U536":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U613":{ + "add_all__U537":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U614":{ + "add_all__U538":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U615":{ + "add_all__U539":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U591":{ + "coeff_0_U515":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U593":{ + "coeff_1_U517":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_2_U595":{ + "coeff_2_U519":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000900"]} }, - "coeff_3_U597":{ + "coeff_3_U521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U599":{ + "coeff_4_U523":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U601":{ + "coeff_5_U525":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U603":{ + "coeff_6_U527":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U605":{ + "coeff_7_U529":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U607":{ + "const_term_U531":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U592":{ + "mul_d0__U516":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U594":{ + "mul_d1__U518":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U596":{ + "mul_d2__U520":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U598":{ + "mul_d3__U522":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U600":{ + "mul_d4__U524":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U602":{ + "mul_d5__U526":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U604":{ + "mul_d6__U528":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U606":{ + "mul_d7__U530":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U592.out","add_all__U608.in0"], - ["mul_d1__U594.out","add_all__U608.in1"], - ["add_all__U609.in0","add_all__U608.out"], - ["mul_d2__U596.out","add_all__U609.in1"], - ["add_all__U610.in0","add_all__U609.out"], - ["mul_d3__U598.out","add_all__U610.in1"], - ["add_all__U611.in0","add_all__U610.out"], - ["mul_d4__U600.out","add_all__U611.in1"], - ["add_all__U612.in0","add_all__U611.out"], - ["mul_d5__U602.out","add_all__U612.in1"], - ["add_all__U613.in0","add_all__U612.out"], - ["mul_d6__U604.out","add_all__U613.in1"], - ["add_all__U614.in0","add_all__U613.out"], - ["mul_d7__U606.out","add_all__U614.in1"], - ["add_all__U615.in0","add_all__U614.out"], - ["const_term_U607.out","add_all__U615.in1"], - ["self.out","add_all__U615.out"], - ["mul_d0__U592.in0","coeff_0_U591.out"], - ["mul_d1__U594.in0","coeff_1_U593.out"], - ["mul_d2__U596.in0","coeff_2_U595.out"], - ["mul_d3__U598.in0","coeff_3_U597.out"], - ["mul_d4__U600.in0","coeff_4_U599.out"], - ["mul_d5__U602.in0","coeff_5_U601.out"], - ["mul_d6__U604.in0","coeff_6_U603.out"], - ["mul_d7__U606.in0","coeff_7_U605.out"], - ["self.d.0","mul_d0__U592.in1"], - ["self.d.1","mul_d1__U594.in1"], - ["self.d.2","mul_d2__U596.in1"], - ["self.d.3","mul_d3__U598.in1"], - ["self.d.4","mul_d4__U600.in1"], - ["self.d.5","mul_d5__U602.in1"], - ["self.d.6","mul_d6__U604.in1"], - ["self.d.7","mul_d7__U606.in1"] + ["mul_d0__U516.out","add_all__U532.in0"], + ["mul_d1__U518.out","add_all__U532.in1"], + ["add_all__U533.in0","add_all__U532.out"], + ["mul_d2__U520.out","add_all__U533.in1"], + ["add_all__U534.in0","add_all__U533.out"], + ["mul_d3__U522.out","add_all__U534.in1"], + ["add_all__U535.in0","add_all__U534.out"], + ["mul_d4__U524.out","add_all__U535.in1"], + ["add_all__U536.in0","add_all__U535.out"], + ["mul_d5__U526.out","add_all__U536.in1"], + ["add_all__U537.in0","add_all__U536.out"], + ["mul_d6__U528.out","add_all__U537.in1"], + ["add_all__U538.in0","add_all__U537.out"], + ["mul_d7__U530.out","add_all__U538.in1"], + ["add_all__U539.in0","add_all__U538.out"], + ["const_term_U531.out","add_all__U539.in1"], + ["self.out","add_all__U539.out"], + ["mul_d0__U516.in0","coeff_0_U515.out"], + ["mul_d1__U518.in0","coeff_1_U517.out"], + ["mul_d2__U520.in0","coeff_2_U519.out"], + ["mul_d3__U522.in0","coeff_3_U521.out"], + ["mul_d4__U524.in0","coeff_4_U523.out"], + ["mul_d5__U526.in0","coeff_5_U525.out"], + ["mul_d6__U528.in0","coeff_6_U527.out"], + ["mul_d7__U530.in0","coeff_7_U529.out"], + ["self.d.0","mul_d0__U516.in1"], + ["self.d.1","mul_d1__U518.in1"], + ["self.d.2","mul_d2__U520.in1"], + ["self.d.3","mul_d3__U522.in1"], + ["self.d.4","mul_d4__U524.in1"], + ["self.d.5","mul_d5__U526.in1"], + ["self.d.6","mul_d6__U528.in1"], + ["self.d.7","mul_d7__U530.in1"] ] }, - "aff__U636":{ + "aff__U551":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U650":{ + "add_all__U565":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U651":{ + "add_all__U566":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U652":{ + "add_all__U567":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U653":{ + "add_all__U568":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U654":{ + "add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U655":{ + "add_all__U570":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U637":{ + "coeff_0_U552":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U639":{ + "coeff_1_U554":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "coeff_2_U641":{ + "coeff_2_U556":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "coeff_3_U643":{ + "coeff_3_U558":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_4_U645":{ + "coeff_4_U560":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U647":{ + "coeff_5_U562":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U649":{ + "const_term_U564":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003840"]} }, - "mul_d0__U638":{ + "mul_d0__U553":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U640":{ + "mul_d1__U555":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U642":{ + "mul_d2__U557":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U644":{ + "mul_d3__U559":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U646":{ + "mul_d4__U561":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U648":{ + "mul_d5__U563":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U638.out","add_all__U650.in0"], - ["mul_d1__U640.out","add_all__U650.in1"], - ["add_all__U651.in0","add_all__U650.out"], - ["mul_d2__U642.out","add_all__U651.in1"], - ["add_all__U652.in0","add_all__U651.out"], - ["mul_d3__U644.out","add_all__U652.in1"], - ["add_all__U653.in0","add_all__U652.out"], - ["mul_d4__U646.out","add_all__U653.in1"], - ["add_all__U654.in0","add_all__U653.out"], - ["mul_d5__U648.out","add_all__U654.in1"], - ["add_all__U655.in0","add_all__U654.out"], - ["const_term_U649.out","add_all__U655.in1"], - ["self.out","add_all__U655.out"], - ["mul_d0__U638.in0","coeff_0_U637.out"], - ["mul_d1__U640.in0","coeff_1_U639.out"], - ["mul_d2__U642.in0","coeff_2_U641.out"], - ["mul_d3__U644.in0","coeff_3_U643.out"], - ["mul_d4__U646.in0","coeff_4_U645.out"], - ["mul_d5__U648.in0","coeff_5_U647.out"], - ["self.d.0","mul_d0__U638.in1"], - ["self.d.1","mul_d1__U640.in1"], - ["self.d.2","mul_d2__U642.in1"], - ["self.d.3","mul_d3__U644.in1"], - ["self.d.4","mul_d4__U646.in1"], - ["self.d.5","mul_d5__U648.in1"] + ["mul_d0__U553.out","add_all__U565.in0"], + ["mul_d1__U555.out","add_all__U565.in1"], + ["add_all__U566.in0","add_all__U565.out"], + ["mul_d2__U557.out","add_all__U566.in1"], + ["add_all__U567.in0","add_all__U566.out"], + ["mul_d3__U559.out","add_all__U567.in1"], + ["add_all__U568.in0","add_all__U567.out"], + ["mul_d4__U561.out","add_all__U568.in1"], + ["add_all__U569.in0","add_all__U568.out"], + ["mul_d5__U563.out","add_all__U569.in1"], + ["add_all__U570.in0","add_all__U569.out"], + ["const_term_U564.out","add_all__U570.in1"], + ["self.out","add_all__U570.out"], + ["mul_d0__U553.in0","coeff_0_U552.out"], + ["mul_d1__U555.in0","coeff_1_U554.out"], + ["mul_d2__U557.in0","coeff_2_U556.out"], + ["mul_d3__U559.in0","coeff_3_U558.out"], + ["mul_d4__U561.in0","coeff_4_U560.out"], + ["mul_d5__U563.in0","coeff_5_U562.out"], + ["self.d.0","mul_d0__U553.in1"], + ["self.d.1","mul_d1__U555.in1"], + ["self.d.2","mul_d2__U557.in1"], + ["self.d.3","mul_d3__U559.in1"], + ["self.d.4","mul_d4__U561.in1"], + ["self.d.5","mul_d5__U563.in1"] ] }, - "aff__U674":{ + "aff__U589":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U688":{ + "add_all__U603":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U689":{ + "add_all__U604":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U690":{ + "add_all__U605":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U691":{ + "add_all__U606":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U692":{ + "add_all__U607":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U693":{ + "add_all__U608":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U675":{ + "coeff_0_U590":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U677":{ + "coeff_1_U592":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_2_U679":{ + "coeff_2_U594":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U681":{ + "coeff_3_U596":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_4_U683":{ + "coeff_4_U598":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_5_U685":{ + "coeff_5_U600":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U687":{ + "const_term_U602":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U676":{ + "mul_d0__U591":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U678":{ + "mul_d1__U593":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U680":{ + "mul_d2__U595":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U682":{ + "mul_d3__U597":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U684":{ + "mul_d4__U599":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U686":{ + "mul_d5__U601":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U676.out","add_all__U688.in0"], - ["mul_d1__U678.out","add_all__U688.in1"], - ["add_all__U689.in0","add_all__U688.out"], - ["mul_d2__U680.out","add_all__U689.in1"], - ["add_all__U690.in0","add_all__U689.out"], - ["mul_d3__U682.out","add_all__U690.in1"], - ["add_all__U691.in0","add_all__U690.out"], - ["mul_d4__U684.out","add_all__U691.in1"], - ["add_all__U692.in0","add_all__U691.out"], - ["mul_d5__U686.out","add_all__U692.in1"], - ["add_all__U693.in0","add_all__U692.out"], - ["const_term_U687.out","add_all__U693.in1"], - ["self.out","add_all__U693.out"], - ["mul_d0__U676.in0","coeff_0_U675.out"], - ["mul_d1__U678.in0","coeff_1_U677.out"], - ["mul_d2__U680.in0","coeff_2_U679.out"], - ["mul_d3__U682.in0","coeff_3_U681.out"], - ["mul_d4__U684.in0","coeff_4_U683.out"], - ["mul_d5__U686.in0","coeff_5_U685.out"], - ["self.d.0","mul_d0__U676.in1"], - ["self.d.1","mul_d1__U678.in1"], - ["self.d.2","mul_d2__U680.in1"], - ["self.d.3","mul_d3__U682.in1"], - ["self.d.4","mul_d4__U684.in1"], - ["self.d.5","mul_d5__U686.in1"] + ["mul_d0__U591.out","add_all__U603.in0"], + ["mul_d1__U593.out","add_all__U603.in1"], + ["add_all__U604.in0","add_all__U603.out"], + ["mul_d2__U595.out","add_all__U604.in1"], + ["add_all__U605.in0","add_all__U604.out"], + ["mul_d3__U597.out","add_all__U605.in1"], + ["add_all__U606.in0","add_all__U605.out"], + ["mul_d4__U599.out","add_all__U606.in1"], + ["add_all__U607.in0","add_all__U606.out"], + ["mul_d5__U601.out","add_all__U607.in1"], + ["add_all__U608.in0","add_all__U607.out"], + ["const_term_U602.out","add_all__U608.in1"], + ["self.out","add_all__U608.out"], + ["mul_d0__U591.in0","coeff_0_U590.out"], + ["mul_d1__U593.in0","coeff_1_U592.out"], + ["mul_d2__U595.in0","coeff_2_U594.out"], + ["mul_d3__U597.in0","coeff_3_U596.out"], + ["mul_d4__U599.in0","coeff_4_U598.out"], + ["mul_d5__U601.in0","coeff_5_U600.out"], + ["self.d.0","mul_d0__U591.in1"], + ["self.d.1","mul_d1__U593.in1"], + ["self.d.2","mul_d2__U595.in1"], + ["self.d.3","mul_d3__U597.in1"], + ["self.d.4","mul_d4__U599.in1"], + ["self.d.5","mul_d5__U601.in1"] ] }, - "aff__U696":{ + "aff__U611":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U706":{ + "add_all__U621":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U707":{ + "add_all__U622":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U708":{ + "add_all__U623":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U709":{ + "add_all__U624":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U697":{ + "coeff_0_U612":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U699":{ + "coeff_1_U614":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_2_U701":{ + "coeff_2_U616":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U703":{ + "coeff_3_U618":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U705":{ + "const_term_U620":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004e1f"]} }, - "mul_d0__U698":{ + "mul_d0__U613":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U700":{ + "mul_d1__U615":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U702":{ + "mul_d2__U617":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U704":{ + "mul_d3__U619":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U698.out","add_all__U706.in0"], - ["mul_d1__U700.out","add_all__U706.in1"], - ["add_all__U707.in0","add_all__U706.out"], - ["mul_d2__U702.out","add_all__U707.in1"], - ["add_all__U708.in0","add_all__U707.out"], - ["mul_d3__U704.out","add_all__U708.in1"], - ["add_all__U709.in0","add_all__U708.out"], - ["const_term_U705.out","add_all__U709.in1"], - ["self.out","add_all__U709.out"], - ["mul_d0__U698.in0","coeff_0_U697.out"], - ["mul_d1__U700.in0","coeff_1_U699.out"], - ["mul_d2__U702.in0","coeff_2_U701.out"], - ["mul_d3__U704.in0","coeff_3_U703.out"], - ["self.d.0","mul_d0__U698.in1"], - ["self.d.1","mul_d1__U700.in1"], - ["self.d.2","mul_d2__U702.in1"], - ["self.d.3","mul_d3__U704.in1"] + ["mul_d0__U613.out","add_all__U621.in0"], + ["mul_d1__U615.out","add_all__U621.in1"], + ["add_all__U622.in0","add_all__U621.out"], + ["mul_d2__U617.out","add_all__U622.in1"], + ["add_all__U623.in0","add_all__U622.out"], + ["mul_d3__U619.out","add_all__U623.in1"], + ["add_all__U624.in0","add_all__U623.out"], + ["const_term_U620.out","add_all__U624.in1"], + ["self.out","add_all__U624.out"], + ["mul_d0__U613.in0","coeff_0_U612.out"], + ["mul_d1__U615.in0","coeff_1_U614.out"], + ["mul_d2__U617.in0","coeff_2_U616.out"], + ["mul_d3__U619.in0","coeff_3_U618.out"], + ["self.d.0","mul_d0__U613.in1"], + ["self.d.1","mul_d1__U615.in1"], + ["self.d.2","mul_d2__U617.in1"], + ["self.d.3","mul_d3__U619.in1"] ] }, - "aff__U719":{ + "aff__U634":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U729":{ + "add_all__U644":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U730":{ + "add_all__U645":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U731":{ + "add_all__U646":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U732":{ + "add_all__U647":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U720":{ + "coeff_0_U635":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U722":{ + "coeff_1_U637":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U724":{ + "coeff_2_U639":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_3_U726":{ + "coeff_3_U641":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U728":{ + "const_term_U643":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U721":{ + "mul_d0__U636":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U723":{ + "mul_d1__U638":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U725":{ + "mul_d2__U640":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U727":{ + "mul_d3__U642":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U721.out","add_all__U729.in0"], - ["mul_d1__U723.out","add_all__U729.in1"], - ["add_all__U730.in0","add_all__U729.out"], - ["mul_d2__U725.out","add_all__U730.in1"], - ["add_all__U731.in0","add_all__U730.out"], - ["mul_d3__U727.out","add_all__U731.in1"], - ["add_all__U732.in0","add_all__U731.out"], - ["const_term_U728.out","add_all__U732.in1"], - ["self.out","add_all__U732.out"], - ["mul_d0__U721.in0","coeff_0_U720.out"], - ["mul_d1__U723.in0","coeff_1_U722.out"], - ["mul_d2__U725.in0","coeff_2_U724.out"], - ["mul_d3__U727.in0","coeff_3_U726.out"], - ["self.d.0","mul_d0__U721.in1"], - ["self.d.1","mul_d1__U723.in1"], - ["self.d.2","mul_d2__U725.in1"], - ["self.d.3","mul_d3__U727.in1"] + ["mul_d0__U636.out","add_all__U644.in0"], + ["mul_d1__U638.out","add_all__U644.in1"], + ["add_all__U645.in0","add_all__U644.out"], + ["mul_d2__U640.out","add_all__U645.in1"], + ["add_all__U646.in0","add_all__U645.out"], + ["mul_d3__U642.out","add_all__U646.in1"], + ["add_all__U647.in0","add_all__U646.out"], + ["const_term_U643.out","add_all__U647.in1"], + ["self.out","add_all__U647.out"], + ["mul_d0__U636.in0","coeff_0_U635.out"], + ["mul_d1__U638.in0","coeff_1_U637.out"], + ["mul_d2__U640.in0","coeff_2_U639.out"], + ["mul_d3__U642.in0","coeff_3_U641.out"], + ["self.d.0","mul_d0__U636.in1"], + ["self.d.1","mul_d1__U638.in1"], + ["self.d.2","mul_d2__U640.in1"], + ["self.d.3","mul_d3__U642.in1"] ] }, - "aff__U95":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U109":{ + "add_all__U100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U110":{ + "add_all__U101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U111":{ + "add_all__U102":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U112":{ + "add_all__U103":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U113":{ + "add_all__U104":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U105":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U96":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U98":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U100":{ + "coeff_2_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "coeff_3_U102":{ + "coeff_3_U93":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U104":{ + "coeff_4_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_5_U106":{ + "coeff_5_U97":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "const_term_U108":{ + "const_term_U99":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U97":{ + "mul_d0__U88":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U99":{ + "mul_d2__U92":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U101":{ + "mul_d3__U94":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U103":{ + "mul_d4__U96":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U105":{ + "mul_d5__U98":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U88.out","add_all__U100.in0"], + ["mul_d1__U90.out","add_all__U100.in1"], + ["add_all__U101.in0","add_all__U100.out"], + ["mul_d2__U92.out","add_all__U101.in1"], + ["add_all__U102.in0","add_all__U101.out"], + ["mul_d3__U94.out","add_all__U102.in1"], + ["add_all__U103.in0","add_all__U102.out"], + ["mul_d4__U96.out","add_all__U103.in1"], + ["add_all__U104.in0","add_all__U103.out"], + ["mul_d5__U98.out","add_all__U104.in1"], + ["add_all__U105.in0","add_all__U104.out"], + ["const_term_U99.out","add_all__U105.in1"], + ["self.out","add_all__U105.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["mul_d2__U92.in0","coeff_2_U91.out"], + ["mul_d3__U94.in0","coeff_3_U93.out"], + ["mul_d4__U96.in0","coeff_4_U95.out"], + ["mul_d5__U98.in0","coeff_5_U97.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"], + ["self.d.2","mul_d2__U92.in1"], + ["self.d.3","mul_d3__U94.in1"], + ["self.d.4","mul_d4__U96.in1"], + ["self.d.5","mul_d5__U98.in1"] + ] + }, + "aff__U9":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U19":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U20":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U21":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U22":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000002"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U13":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U107":{ + "mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U97.out","add_all__U109.in0"], - ["mul_d1__U99.out","add_all__U109.in1"], - ["add_all__U110.in0","add_all__U109.out"], - ["mul_d2__U101.out","add_all__U110.in1"], - ["add_all__U111.in0","add_all__U110.out"], - ["mul_d3__U103.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["mul_d4__U105.out","add_all__U112.in1"], - ["add_all__U113.in0","add_all__U112.out"], - ["mul_d5__U107.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U108.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U97.in0","coeff_0_U96.out"], - ["mul_d1__U99.in0","coeff_1_U98.out"], - ["mul_d2__U101.in0","coeff_2_U100.out"], - ["mul_d3__U103.in0","coeff_3_U102.out"], - ["mul_d4__U105.in0","coeff_4_U104.out"], - ["mul_d5__U107.in0","coeff_5_U106.out"], - ["self.d.0","mul_d0__U97.in1"], - ["self.d.1","mul_d1__U99.in1"], - ["self.d.2","mul_d2__U101.in1"], - ["self.d.3","mul_d3__U103.in1"], - ["self.d.4","mul_d4__U105.in1"], - ["self.d.5","mul_d5__U107.in1"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U118":{ + "affine_controller__U108":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2464,85 +2464,85 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U133":{ + "_U123":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1331":{ + "_U1231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1332":{ + "_U1232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1333":{ + "_U1233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U134":{ + "_U124":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U129":{ + "affine_func$add_all__U119":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U130":{ + "affine_func$add_all__U120":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U131":{ + "affine_func$add_all__U121":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U132":{ + "affine_func$add_all__U122":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U120":{ + "affine_func$coeff_0_U110":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U122":{ + "affine_func$coeff_1_U112":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "affine_func$coeff_2_U124":{ + "affine_func$coeff_2_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U126":{ + "affine_func$coeff_3_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "affine_func$const_term_U128":{ + "affine_func$const_term_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$mul_d0__U121":{ + "affine_func$mul_d0__U111":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U123":{ + "affine_func$mul_d1__U113":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U125":{ + "affine_func$mul_d2__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U127":{ + "affine_func$mul_d3__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2606,32 +2606,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U135$c0_lutcnst":{ + "d_0_am__U125$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U135$lut$lut":{ + "d_0_am__U125$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U136$c0_lutcnst":{ + "d_0_am__U126$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U136$lut$lut":{ + "d_0_am__U126$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U137$c0_lutcnst":{ + "d_0_am__U127$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U137$lut$lut":{ + "d_0_am__U127$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2680,22 +2680,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U138$c0_lutcnst":{ + "d_1_am__U128$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U138$lut$lut":{ + "d_1_am__U128$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U139$c0_lutcnst":{ + "d_1_am__U129$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U139$lut$lut":{ + "d_1_am__U129$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2744,12 +2744,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U140$c0_lutcnst":{ + "d_2_am__U130$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U140$lut$lut":{ + "d_2_am__U130$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2878,28 +2878,28 @@ } }, "connections":[ - ["d_0_inc.in1","_U133.out"], - ["d_1_inc.in1","_U1331.out"], - ["d_2_inc.in1","_U1332.out"], - ["d_3_inc.in1","_U1333.out"], - ["cmp_time.in1","_U134.out"], - ["affine_func$mul_d0__U121.out","affine_func$add_all__U129.in0"], - ["affine_func$mul_d1__U123.out","affine_func$add_all__U129.in1"], - ["affine_func$add_all__U130.in0","affine_func$add_all__U129.out"], - ["affine_func$mul_d2__U125.out","affine_func$add_all__U130.in1"], - ["affine_func$add_all__U131.in0","affine_func$add_all__U130.out"], - ["affine_func$mul_d3__U127.out","affine_func$add_all__U131.in1"], - ["affine_func$add_all__U132.in0","affine_func$add_all__U131.out"], - ["affine_func$const_term_U128.out","affine_func$add_all__U132.in1"], - ["time_diff.in0","affine_func$add_all__U132.out"], - ["affine_func$mul_d0__U121.in0","affine_func$coeff_0_U120.out"], - ["affine_func$mul_d1__U123.in0","affine_func$coeff_1_U122.out"], - ["affine_func$mul_d2__U125.in0","affine_func$coeff_2_U124.out"], - ["affine_func$mul_d3__U127.in0","affine_func$coeff_3_U126.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U121.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U123.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U125.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U127.in1"], + ["d_0_inc.in1","_U123.out"], + ["d_1_inc.in1","_U1231.out"], + ["d_2_inc.in1","_U1232.out"], + ["d_3_inc.in1","_U1233.out"], + ["cmp_time.in1","_U124.out"], + ["affine_func$mul_d0__U111.out","affine_func$add_all__U119.in0"], + ["affine_func$mul_d1__U113.out","affine_func$add_all__U119.in1"], + ["affine_func$add_all__U120.in0","affine_func$add_all__U119.out"], + ["affine_func$mul_d2__U115.out","affine_func$add_all__U120.in1"], + ["affine_func$add_all__U121.in0","affine_func$add_all__U120.out"], + ["affine_func$mul_d3__U117.out","affine_func$add_all__U121.in1"], + ["affine_func$add_all__U122.in0","affine_func$add_all__U121.out"], + ["affine_func$const_term_U118.out","affine_func$add_all__U122.in1"], + ["time_diff.in0","affine_func$add_all__U122.out"], + ["affine_func$mul_d0__U111.in0","affine_func$coeff_0_U110.out"], + ["affine_func$mul_d1__U113.in0","affine_func$coeff_1_U112.out"], + ["affine_func$mul_d2__U115.in0","affine_func$coeff_2_U114.out"], + ["affine_func$mul_d3__U117.in0","affine_func$coeff_3_U116.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U111.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U113.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U115.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U117.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -2924,16 +2924,16 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U135$lut$lut.bit.in.2","d_0_am__U135$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U135$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U135$lut$lut.bit.in.1"], - ["d_0_am__U136$lut$lut.bit.in.0","d_0_am__U135$lut$lut.bit.out"], - ["d_0_am__U136$lut$lut.bit.in.2","d_0_am__U136$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U136$lut$lut.bit.in.1"], - ["d_0_am__U137$lut$lut.bit.in.0","d_0_am__U136$lut$lut.bit.out"], - ["d_0_am__U137$lut$lut.bit.in.2","d_0_am__U137$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U137$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U137$lut$lut.bit.out"], + ["d_0_am__U125$lut$lut.bit.in.2","d_0_am__U125$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U125$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U125$lut$lut.bit.in.1"], + ["d_0_am__U126$lut$lut.bit.in.0","d_0_am__U125$lut$lut.bit.out"], + ["d_0_am__U126$lut$lut.bit.in.2","d_0_am__U126$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U126$lut$lut.bit.in.1"], + ["d_0_am__U127$lut$lut.bit.in.0","d_0_am__U126$lut$lut.bit.out"], + ["d_0_am__U127$lut$lut.bit.in.2","d_0_am__U127$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U127$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U127$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2950,13 +2950,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U138$lut$lut.bit.in.2","d_1_am__U138$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U138$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U138$lut$lut.bit.in.1"], - ["d_1_am__U139$lut$lut.bit.in.0","d_1_am__U138$lut$lut.bit.out"], - ["d_1_am__U139$lut$lut.bit.in.2","d_1_am__U139$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U139$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U139$lut$lut.bit.out"], + ["d_1_am__U128$lut$lut.bit.in.2","d_1_am__U128$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U128$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U128$lut$lut.bit.in.1"], + ["d_1_am__U129$lut$lut.bit.in.0","d_1_am__U128$lut$lut.bit.out"], + ["d_1_am__U129$lut$lut.bit.in.2","d_1_am__U129$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U129$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U129$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2973,10 +2973,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U140$lut$lut.bit.in.2","d_2_am__U140$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U140$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U140$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U140$lut$lut.bit.out"], + ["d_2_am__U130$lut$lut.bit.in.2","d_2_am__U130$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U130$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U130$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U130$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3012,7 +3012,7 @@ ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U157":{ + "affine_controller__U147":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3020,121 +3020,121 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U178":{ + "_U168":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1781":{ + "_U1681":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1782":{ + "_U1682":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1783":{ + "_U1683":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1784":{ + "_U1684":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1785":{ + "_U1685":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U179":{ + "_U169":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U172":{ + "affine_func$add_all__U162":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U173":{ + "affine_func$add_all__U163":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U174":{ + "affine_func$add_all__U164":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U175":{ + "affine_func$add_all__U165":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U176":{ + "affine_func$add_all__U166":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U177":{ + "affine_func$add_all__U167":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U159":{ + "affine_func$coeff_0_U149":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U161":{ + "affine_func$coeff_1_U151":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "affine_func$coeff_2_U163":{ + "affine_func$coeff_2_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "affine_func$coeff_3_U165":{ + "affine_func$coeff_3_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "affine_func$coeff_4_U167":{ + "affine_func$coeff_4_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "affine_func$coeff_5_U169":{ + "affine_func$coeff_5_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U171":{ + "affine_func$const_term_U161":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "affine_func$mul_d0__U160":{ + "affine_func$mul_d0__U150":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U162":{ + "affine_func$mul_d1__U152":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U164":{ + "affine_func$mul_d2__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U166":{ + "affine_func$mul_d3__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U168":{ + "affine_func$mul_d4__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U170":{ + "affine_func$mul_d5__U160":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -3198,52 +3198,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U180$c0_lutcnst":{ + "d_0_am__U170$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U180$lut$lut":{ + "d_0_am__U170$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U181$c0_lutcnst":{ + "d_0_am__U171$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U181$lut$lut":{ + "d_0_am__U171$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U182$c0_lutcnst":{ + "d_0_am__U172$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U182$lut$lut":{ + "d_0_am__U172$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U183$c0_lutcnst":{ + "d_0_am__U173$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U183$lut$lut":{ + "d_0_am__U173$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U184$c0_lutcnst":{ + "d_0_am__U174$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U184$lut$lut":{ + "d_0_am__U174$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3292,42 +3292,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U185$c0_lutcnst":{ + "d_1_am__U175$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U185$lut$lut":{ + "d_1_am__U175$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U186$c0_lutcnst":{ + "d_1_am__U176$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U186$lut$lut":{ + "d_1_am__U176$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U187$c0_lutcnst":{ + "d_1_am__U177$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U187$lut$lut":{ + "d_1_am__U177$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U188$c0_lutcnst":{ + "d_1_am__U178$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U188$lut$lut":{ + "d_1_am__U178$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3376,32 +3376,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U189$c0_lutcnst":{ + "d_2_am__U179$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U189$lut$lut":{ + "d_2_am__U179$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U190$c0_lutcnst":{ + "d_2_am__U180$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U190$lut$lut":{ + "d_2_am__U180$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U191$c0_lutcnst":{ + "d_2_am__U181$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U191$lut$lut":{ + "d_2_am__U181$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3450,22 +3450,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U192$c0_lutcnst":{ + "d_3_am__U182$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U192$lut$lut":{ + "d_3_am__U182$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U193$c0_lutcnst":{ + "d_3_am__U183$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U193$lut$lut":{ + "d_3_am__U183$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3514,12 +3514,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U194$c0_lutcnst":{ + "d_4_am__U184$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U194$lut$lut":{ + "d_4_am__U184$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3658,38 +3658,38 @@ } }, "connections":[ - ["d_0_inc.in1","_U178.out"], - ["d_1_inc.in1","_U1781.out"], - ["d_2_inc.in1","_U1782.out"], - ["d_3_inc.in1","_U1783.out"], - ["d_4_inc.in1","_U1784.out"], - ["d_5_inc.in1","_U1785.out"], - ["cmp_time.in1","_U179.out"], - ["affine_func$mul_d0__U160.out","affine_func$add_all__U172.in0"], - ["affine_func$mul_d1__U162.out","affine_func$add_all__U172.in1"], - ["affine_func$add_all__U173.in0","affine_func$add_all__U172.out"], - ["affine_func$mul_d2__U164.out","affine_func$add_all__U173.in1"], - ["affine_func$add_all__U174.in0","affine_func$add_all__U173.out"], - ["affine_func$mul_d3__U166.out","affine_func$add_all__U174.in1"], - ["affine_func$add_all__U175.in0","affine_func$add_all__U174.out"], - ["affine_func$mul_d4__U168.out","affine_func$add_all__U175.in1"], - ["affine_func$add_all__U176.in0","affine_func$add_all__U175.out"], - ["affine_func$mul_d5__U170.out","affine_func$add_all__U176.in1"], - ["affine_func$add_all__U177.in0","affine_func$add_all__U176.out"], - ["affine_func$const_term_U171.out","affine_func$add_all__U177.in1"], - ["time_diff.in0","affine_func$add_all__U177.out"], - ["affine_func$mul_d0__U160.in0","affine_func$coeff_0_U159.out"], - ["affine_func$mul_d1__U162.in0","affine_func$coeff_1_U161.out"], - ["affine_func$mul_d2__U164.in0","affine_func$coeff_2_U163.out"], - ["affine_func$mul_d3__U166.in0","affine_func$coeff_3_U165.out"], - ["affine_func$mul_d4__U168.in0","affine_func$coeff_4_U167.out"], - ["affine_func$mul_d5__U170.in0","affine_func$coeff_5_U169.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U160.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U162.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U164.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U166.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U168.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U170.in1"], + ["d_0_inc.in1","_U168.out"], + ["d_1_inc.in1","_U1681.out"], + ["d_2_inc.in1","_U1682.out"], + ["d_3_inc.in1","_U1683.out"], + ["d_4_inc.in1","_U1684.out"], + ["d_5_inc.in1","_U1685.out"], + ["cmp_time.in1","_U169.out"], + ["affine_func$mul_d0__U150.out","affine_func$add_all__U162.in0"], + ["affine_func$mul_d1__U152.out","affine_func$add_all__U162.in1"], + ["affine_func$add_all__U163.in0","affine_func$add_all__U162.out"], + ["affine_func$mul_d2__U154.out","affine_func$add_all__U163.in1"], + ["affine_func$add_all__U164.in0","affine_func$add_all__U163.out"], + ["affine_func$mul_d3__U156.out","affine_func$add_all__U164.in1"], + ["affine_func$add_all__U165.in0","affine_func$add_all__U164.out"], + ["affine_func$mul_d4__U158.out","affine_func$add_all__U165.in1"], + ["affine_func$add_all__U166.in0","affine_func$add_all__U165.out"], + ["affine_func$mul_d5__U160.out","affine_func$add_all__U166.in1"], + ["affine_func$add_all__U167.in0","affine_func$add_all__U166.out"], + ["affine_func$const_term_U161.out","affine_func$add_all__U167.in1"], + ["time_diff.in0","affine_func$add_all__U167.out"], + ["affine_func$mul_d0__U150.in0","affine_func$coeff_0_U149.out"], + ["affine_func$mul_d1__U152.in0","affine_func$coeff_1_U151.out"], + ["affine_func$mul_d2__U154.in0","affine_func$coeff_2_U153.out"], + ["affine_func$mul_d3__U156.in0","affine_func$coeff_3_U155.out"], + ["affine_func$mul_d4__U158.in0","affine_func$coeff_4_U157.out"], + ["affine_func$mul_d5__U160.in0","affine_func$coeff_5_U159.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U150.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U152.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U154.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U156.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U158.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U160.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -3716,22 +3716,22 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U180$lut$lut.bit.in.2","d_0_am__U180$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U180$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U180$lut$lut.bit.in.1"], - ["d_0_am__U181$lut$lut.bit.in.0","d_0_am__U180$lut$lut.bit.out"], - ["d_0_am__U181$lut$lut.bit.in.2","d_0_am__U181$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U181$lut$lut.bit.in.1"], - ["d_0_am__U182$lut$lut.bit.in.0","d_0_am__U181$lut$lut.bit.out"], - ["d_0_am__U182$lut$lut.bit.in.2","d_0_am__U182$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U182$lut$lut.bit.in.1"], - ["d_0_am__U183$lut$lut.bit.in.0","d_0_am__U182$lut$lut.bit.out"], - ["d_0_am__U183$lut$lut.bit.in.2","d_0_am__U183$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U183$lut$lut.bit.in.1"], - ["d_0_am__U184$lut$lut.bit.in.0","d_0_am__U183$lut$lut.bit.out"], - ["d_0_am__U184$lut$lut.bit.in.2","d_0_am__U184$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U184$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U184$lut$lut.bit.out"], + ["d_0_am__U170$lut$lut.bit.in.2","d_0_am__U170$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U170$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U170$lut$lut.bit.in.1"], + ["d_0_am__U171$lut$lut.bit.in.0","d_0_am__U170$lut$lut.bit.out"], + ["d_0_am__U171$lut$lut.bit.in.2","d_0_am__U171$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U171$lut$lut.bit.in.1"], + ["d_0_am__U172$lut$lut.bit.in.0","d_0_am__U171$lut$lut.bit.out"], + ["d_0_am__U172$lut$lut.bit.in.2","d_0_am__U172$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U172$lut$lut.bit.in.1"], + ["d_0_am__U173$lut$lut.bit.in.0","d_0_am__U172$lut$lut.bit.out"], + ["d_0_am__U173$lut$lut.bit.in.2","d_0_am__U173$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U173$lut$lut.bit.in.1"], + ["d_0_am__U174$lut$lut.bit.in.0","d_0_am__U173$lut$lut.bit.out"], + ["d_0_am__U174$lut$lut.bit.in.2","d_0_am__U174$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U174$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U174$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3748,19 +3748,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U185$lut$lut.bit.in.2","d_1_am__U185$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U185$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U185$lut$lut.bit.in.1"], - ["d_1_am__U186$lut$lut.bit.in.0","d_1_am__U185$lut$lut.bit.out"], - ["d_1_am__U186$lut$lut.bit.in.2","d_1_am__U186$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U186$lut$lut.bit.in.1"], - ["d_1_am__U187$lut$lut.bit.in.0","d_1_am__U186$lut$lut.bit.out"], - ["d_1_am__U187$lut$lut.bit.in.2","d_1_am__U187$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U187$lut$lut.bit.in.1"], - ["d_1_am__U188$lut$lut.bit.in.0","d_1_am__U187$lut$lut.bit.out"], - ["d_1_am__U188$lut$lut.bit.in.2","d_1_am__U188$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U188$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U188$lut$lut.bit.out"], + ["d_1_am__U175$lut$lut.bit.in.2","d_1_am__U175$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U175$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U175$lut$lut.bit.in.1"], + ["d_1_am__U176$lut$lut.bit.in.0","d_1_am__U175$lut$lut.bit.out"], + ["d_1_am__U176$lut$lut.bit.in.2","d_1_am__U176$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U176$lut$lut.bit.in.1"], + ["d_1_am__U177$lut$lut.bit.in.0","d_1_am__U176$lut$lut.bit.out"], + ["d_1_am__U177$lut$lut.bit.in.2","d_1_am__U177$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U177$lut$lut.bit.in.1"], + ["d_1_am__U178$lut$lut.bit.in.0","d_1_am__U177$lut$lut.bit.out"], + ["d_1_am__U178$lut$lut.bit.in.2","d_1_am__U178$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U178$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U178$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3777,16 +3777,16 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U189$lut$lut.bit.in.2","d_2_am__U189$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U189$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U189$lut$lut.bit.in.1"], - ["d_2_am__U190$lut$lut.bit.in.0","d_2_am__U189$lut$lut.bit.out"], - ["d_2_am__U190$lut$lut.bit.in.2","d_2_am__U190$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U190$lut$lut.bit.in.1"], - ["d_2_am__U191$lut$lut.bit.in.0","d_2_am__U190$lut$lut.bit.out"], - ["d_2_am__U191$lut$lut.bit.in.2","d_2_am__U191$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U191$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U191$lut$lut.bit.out"], + ["d_2_am__U179$lut$lut.bit.in.2","d_2_am__U179$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U179$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U179$lut$lut.bit.in.1"], + ["d_2_am__U180$lut$lut.bit.in.0","d_2_am__U179$lut$lut.bit.out"], + ["d_2_am__U180$lut$lut.bit.in.2","d_2_am__U180$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U180$lut$lut.bit.in.1"], + ["d_2_am__U181$lut$lut.bit.in.0","d_2_am__U180$lut$lut.bit.out"], + ["d_2_am__U181$lut$lut.bit.in.2","d_2_am__U181$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U181$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U181$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3803,13 +3803,13 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U192$lut$lut.bit.in.2","d_3_am__U192$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U192$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U192$lut$lut.bit.in.1"], - ["d_3_am__U193$lut$lut.bit.in.0","d_3_am__U192$lut$lut.bit.out"], - ["d_3_am__U193$lut$lut.bit.in.2","d_3_am__U193$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U193$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U193$lut$lut.bit.out"], + ["d_3_am__U182$lut$lut.bit.in.2","d_3_am__U182$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U182$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U182$lut$lut.bit.in.1"], + ["d_3_am__U183$lut$lut.bit.in.0","d_3_am__U182$lut$lut.bit.out"], + ["d_3_am__U183$lut$lut.bit.in.2","d_3_am__U183$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U183$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U183$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3826,10 +3826,10 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U194$lut$lut.bit.in.2","d_4_am__U194$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U194$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U194$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U194$lut$lut.bit.out"], + ["d_4_am__U184$lut$lut.bit.in.2","d_4_am__U184$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U184$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U184$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U184$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3865,93 +3865,111 @@ ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U17":{ + "affine_controller__U272":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",5,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U32":{ + "_U290":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U321":{ + "_U2902":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U322":{ + "_U2903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U2904":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U33":{ + "_U291":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U28":{ + "affine_func$add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U29":{ + "affine_func$add_all__U286":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U30":{ + "affine_func$add_all__U287":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U31":{ + "affine_func$add_all__U288":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U19":{ + "affine_func$add_all__U289":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U274":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U21":{ + "affine_func$coeff_1_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "affine_func$coeff_2_U23":{ + "affine_func$coeff_2_U278":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "affine_func$coeff_3_U25":{ + "affine_func$coeff_3_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "affine_func$coeff_4_U282":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "affine_func$const_term_U27":{ + "affine_func$const_term_U284":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U20":{ + "affine_func$mul_d0__U275":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U277":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U22":{ + "affine_func$mul_d2__U279":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U24":{ + "affine_func$mul_d3__U281":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U26":{ + "affine_func$mul_d4__U283":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4015,32 +4033,42 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U34$c0_lutcnst":{ + "d_0_am__U292$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U292$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U293$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U34$lut$lut":{ + "d_0_am__U293$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U35$c0_lutcnst":{ + "d_0_am__U294$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U35$lut$lut":{ + "d_0_am__U294$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U36$c0_lutcnst":{ + "d_0_am__U295$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U36$lut$lut":{ + "d_0_am__U295$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4089,22 +4117,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U37$c0_lutcnst":{ + "d_1_am__U296$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U37$lut$lut":{ + "d_1_am__U296$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U38$c0_lutcnst":{ + "d_1_am__U297$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U38$lut$lut":{ + "d_1_am__U297$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U298$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U298$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4120,7 +4158,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -4153,12 +4191,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U39$c0_lutcnst":{ + "d_2_am__U299$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U299$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U300$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U39$lut$lut":{ + "d_2_am__U300$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4174,7 +4222,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -4207,6 +4255,16 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U301$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U301$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -4218,7 +4276,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -4251,6 +4309,50 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -4280,6 +4382,11 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4287,33 +4394,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U321.out"], - ["d_2_inc.in1","_U322.out"], - ["d_3_inc.in1","_U323.out"], - ["cmp_time.in1","_U33.out"], - ["affine_func$mul_d0__U20.out","affine_func$add_all__U28.in0"], - ["affine_func$mul_d1__U22.out","affine_func$add_all__U28.in1"], - ["affine_func$add_all__U29.in0","affine_func$add_all__U28.out"], - ["affine_func$mul_d2__U24.out","affine_func$add_all__U29.in1"], - ["affine_func$add_all__U30.in0","affine_func$add_all__U29.out"], - ["affine_func$mul_d3__U26.out","affine_func$add_all__U30.in1"], - ["affine_func$add_all__U31.in0","affine_func$add_all__U30.out"], - ["affine_func$const_term_U27.out","affine_func$add_all__U31.in1"], - ["time_diff.in0","affine_func$add_all__U31.out"], - ["affine_func$mul_d0__U20.in0","affine_func$coeff_0_U19.out"], - ["affine_func$mul_d1__U22.in0","affine_func$coeff_1_U21.out"], - ["affine_func$mul_d2__U24.in0","affine_func$coeff_2_U23.out"], - ["affine_func$mul_d3__U26.in0","affine_func$coeff_3_U25.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U20.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U22.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U24.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U26.in1"], + ["d_0_inc.in1","_U290.out"], + ["d_1_inc.in1","_U2901.out"], + ["d_2_inc.in1","_U2902.out"], + ["d_3_inc.in1","_U2903.out"], + ["d_4_inc.in1","_U2904.out"], + ["cmp_time.in1","_U291.out"], + ["affine_func$mul_d0__U275.out","affine_func$add_all__U285.in0"], + ["affine_func$mul_d1__U277.out","affine_func$add_all__U285.in1"], + ["affine_func$add_all__U286.in0","affine_func$add_all__U285.out"], + ["affine_func$mul_d2__U279.out","affine_func$add_all__U286.in1"], + ["affine_func$add_all__U287.in0","affine_func$add_all__U286.out"], + ["affine_func$mul_d3__U281.out","affine_func$add_all__U287.in1"], + ["affine_func$add_all__U288.in0","affine_func$add_all__U287.out"], + ["affine_func$mul_d4__U283.out","affine_func$add_all__U288.in1"], + ["affine_func$add_all__U289.in0","affine_func$add_all__U288.out"], + ["affine_func$const_term_U284.out","affine_func$add_all__U289.in1"], + ["time_diff.in0","affine_func$add_all__U289.out"], + ["affine_func$mul_d0__U275.in0","affine_func$coeff_0_U274.out"], + ["affine_func$mul_d1__U277.in0","affine_func$coeff_1_U276.out"], + ["affine_func$mul_d2__U279.in0","affine_func$coeff_2_U278.out"], + ["affine_func$mul_d3__U281.in0","affine_func$coeff_3_U280.out"], + ["affine_func$mul_d4__U283.in0","affine_func$coeff_4_U282.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U275.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U277.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U279.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U281.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U283.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -4321,28 +4434,31 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U34$lut$lut.bit.in.2","d_0_am__U34$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U34$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U34$lut$lut.bit.in.1"], - ["d_0_am__U35$lut$lut.bit.in.0","d_0_am__U34$lut$lut.bit.out"], - ["d_0_am__U35$lut$lut.bit.in.2","d_0_am__U35$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U35$lut$lut.bit.in.1"], - ["d_0_am__U36$lut$lut.bit.in.0","d_0_am__U35$lut$lut.bit.out"], - ["d_0_am__U36$lut$lut.bit.in.2","d_0_am__U36$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U36$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U36$lut$lut.bit.out"], + ["d_0_am__U292$lut$lut.bit.in.2","d_0_am__U292$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U292$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U292$lut$lut.bit.in.1"], + ["d_0_am__U293$lut$lut.bit.in.0","d_0_am__U292$lut$lut.bit.out"], + ["d_0_am__U293$lut$lut.bit.in.2","d_0_am__U293$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U293$lut$lut.bit.in.1"], + ["d_0_am__U294$lut$lut.bit.in.0","d_0_am__U293$lut$lut.bit.out"], + ["d_0_am__U294$lut$lut.bit.in.2","d_0_am__U294$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U294$lut$lut.bit.in.1"], + ["d_0_am__U295$lut$lut.bit.in.0","d_0_am__U294$lut$lut.bit.out"], + ["d_0_am__U295$lut$lut.bit.in.2","d_0_am__U295$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U295$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U295$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4359,13 +4475,16 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U37$lut$lut.bit.in.2","d_1_am__U37$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U37$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U37$lut$lut.bit.in.1"], - ["d_1_am__U38$lut$lut.bit.in.0","d_1_am__U37$lut$lut.bit.out"], - ["d_1_am__U38$lut$lut.bit.in.2","d_1_am__U38$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U38$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U38$lut$lut.bit.out"], + ["d_1_am__U296$lut$lut.bit.in.2","d_1_am__U296$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U296$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U296$lut$lut.bit.in.1"], + ["d_1_am__U297$lut$lut.bit.in.0","d_1_am__U296$lut$lut.bit.out"], + ["d_1_am__U297$lut$lut.bit.in.2","d_1_am__U297$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U297$lut$lut.bit.in.1"], + ["d_1_am__U298$lut$lut.bit.in.0","d_1_am__U297$lut$lut.bit.out"], + ["d_1_am__U298$lut$lut.bit.in.2","d_1_am__U298$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U298$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U298$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4382,10 +4501,13 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U39$lut$lut.bit.in.2","d_2_am__U39$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U39$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U39$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U39$lut$lut.bit.out"], + ["d_2_am__U299$lut$lut.bit.in.2","d_2_am__U299$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U299$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U299$lut$lut.bit.in.1"], + ["d_2_am__U300$lut$lut.bit.in.0","d_2_am__U299$lut$lut.bit.out"], + ["d_2_am__U300$lut$lut.bit.in.2","d_2_am__U300$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U300$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U300$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4402,6 +4524,10 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U301$lut$lut.bit.in.2","d_3_am__U301$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U301$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U301$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U301$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4411,121 +4537,191 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["true_lutcnst.bit.out","d_4_next_value.sel"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"] ] }, - "affine_controller__U347":{ + "affine_controller__U321":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], + ["d",["Array",8,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U365":{ + "_U348":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U3481":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U3482":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U3483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3651":{ + "_U3484":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3652":{ + "_U3485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3653":{ + "_U3486":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3654":{ + "_U3487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U366":{ + "_U349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U360":{ + "affine_func$add_all__U340":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U341":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U342":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U361":{ + "affine_func$add_all__U343":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U362":{ + "affine_func$add_all__U344":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U363":{ + "affine_func$add_all__U345":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U364":{ + "affine_func$add_all__U346":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U349":{ + "affine_func$add_all__U347":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U323":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U351":{ + "affine_func$coeff_1_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "affine_func$coeff_2_U353":{ + "affine_func$coeff_2_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "affine_func$coeff_3_U355":{ + "affine_func$coeff_3_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00000180"]} }, - "affine_func$coeff_4_U357":{ + "affine_func$coeff_4_U331":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "affine_func$const_term_U359":{ + "affine_func$coeff_5_U333":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000020"]} + }, + "affine_func$coeff_6_U335":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000004"]} + }, + "affine_func$coeff_7_U337":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U339":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h000023ff"]} + }, + "affine_func$mul_d0__U324":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U350":{ + "affine_func$mul_d1__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U352":{ + "affine_func$mul_d2__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U354":{ + "affine_func$mul_d3__U330":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U356":{ + "affine_func$mul_d4__U332":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U358":{ + "affine_func$mul_d5__U334":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d6__U336":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d7__U338":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4589,42 +4785,72 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U367$c0_lutcnst":{ + "d_0_am__U350$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U350$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U351$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U351$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U352$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U352$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U353$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U367$lut$lut":{ + "d_0_am__U353$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U368$c0_lutcnst":{ + "d_0_am__U354$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U368$lut$lut":{ + "d_0_am__U354$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U369$c0_lutcnst":{ + "d_0_am__U355$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U369$lut$lut":{ + "d_0_am__U355$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U370$c0_lutcnst":{ + "d_0_am__U356$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U370$lut$lut":{ + "d_0_am__U356$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4673,32 +4899,62 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U371$c0_lutcnst":{ + "d_1_am__U357$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U357$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U358$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U358$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U359$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U359$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U360$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U371$lut$lut":{ + "d_1_am__U360$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U372$c0_lutcnst":{ + "d_1_am__U361$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U372$lut$lut":{ + "d_1_am__U361$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U373$c0_lutcnst":{ + "d_1_am__U362$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U373$lut$lut":{ + "d_1_am__U362$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4714,7 +4970,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -4747,22 +5003,52 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U374$c0_lutcnst":{ + "d_2_am__U363$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U374$lut$lut":{ + "d_2_am__U363$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U375$c0_lutcnst":{ + "d_2_am__U364$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U375$lut$lut":{ + "d_2_am__U364$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U365$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U365$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U366$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U366$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U367$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U367$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4778,7 +5064,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -4811,19 +5097,49 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U376$c0_lutcnst":{ + "d_3_am__U368$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U376$lut$lut":{ + "d_3_am__U368$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_3_am__U369$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U369$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U370$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U370$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U371$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U371$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, "d_3_inc":{ "genref":"coreir.add", @@ -4832,7 +5148,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_3_min":{ "genref":"coreir.const", @@ -4865,6 +5181,36 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_am__U372$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U372$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U373$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U373$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U374$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U374$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -4876,7 +5222,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_4_min":{ "genref":"coreir.const", @@ -4909,6 +5255,168 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_5_am__U375$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_5_am__U375$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_5_am__U376$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_5_am__U376$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000003"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_6_am__U377$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_6_am__U377$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_7_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_7_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_7_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000003"]} + }, + "d_7_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -4943,6 +5451,21 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true8_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true9_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -4950,39 +5473,57 @@ } }, "connections":[ - ["d_0_inc.in1","_U365.out"], - ["d_1_inc.in1","_U3651.out"], - ["d_2_inc.in1","_U3652.out"], - ["d_3_inc.in1","_U3653.out"], - ["d_4_inc.in1","_U3654.out"], - ["cmp_time.in1","_U366.out"], - ["affine_func$mul_d0__U350.out","affine_func$add_all__U360.in0"], - ["affine_func$mul_d1__U352.out","affine_func$add_all__U360.in1"], - ["affine_func$add_all__U361.in0","affine_func$add_all__U360.out"], - ["affine_func$mul_d2__U354.out","affine_func$add_all__U361.in1"], - ["affine_func$add_all__U362.in0","affine_func$add_all__U361.out"], - ["affine_func$mul_d3__U356.out","affine_func$add_all__U362.in1"], - ["affine_func$add_all__U363.in0","affine_func$add_all__U362.out"], - ["affine_func$mul_d4__U358.out","affine_func$add_all__U363.in1"], - ["affine_func$add_all__U364.in0","affine_func$add_all__U363.out"], - ["affine_func$const_term_U359.out","affine_func$add_all__U364.in1"], - ["time_diff.in0","affine_func$add_all__U364.out"], - ["affine_func$mul_d0__U350.in0","affine_func$coeff_0_U349.out"], - ["affine_func$mul_d1__U352.in0","affine_func$coeff_1_U351.out"], - ["affine_func$mul_d2__U354.in0","affine_func$coeff_2_U353.out"], - ["affine_func$mul_d3__U356.in0","affine_func$coeff_3_U355.out"], - ["affine_func$mul_d4__U358.in0","affine_func$coeff_4_U357.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U350.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U352.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U354.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U356.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U358.in1"], + ["d_0_inc.in1","_U348.out"], + ["d_1_inc.in1","_U3481.out"], + ["d_2_inc.in1","_U3482.out"], + ["d_3_inc.in1","_U3483.out"], + ["d_4_inc.in1","_U3484.out"], + ["d_5_inc.in1","_U3485.out"], + ["d_6_inc.in1","_U3486.out"], + ["d_7_inc.in1","_U3487.out"], + ["cmp_time.in1","_U349.out"], + ["affine_func$mul_d0__U324.out","affine_func$add_all__U340.in0"], + ["affine_func$mul_d1__U326.out","affine_func$add_all__U340.in1"], + ["affine_func$add_all__U341.in0","affine_func$add_all__U340.out"], + ["affine_func$mul_d2__U328.out","affine_func$add_all__U341.in1"], + ["affine_func$add_all__U342.in0","affine_func$add_all__U341.out"], + ["affine_func$mul_d3__U330.out","affine_func$add_all__U342.in1"], + ["affine_func$add_all__U343.in0","affine_func$add_all__U342.out"], + ["affine_func$mul_d4__U332.out","affine_func$add_all__U343.in1"], + ["affine_func$add_all__U344.in0","affine_func$add_all__U343.out"], + ["affine_func$mul_d5__U334.out","affine_func$add_all__U344.in1"], + ["affine_func$add_all__U345.in0","affine_func$add_all__U344.out"], + ["affine_func$mul_d6__U336.out","affine_func$add_all__U345.in1"], + ["affine_func$add_all__U346.in0","affine_func$add_all__U345.out"], + ["affine_func$mul_d7__U338.out","affine_func$add_all__U346.in1"], + ["affine_func$add_all__U347.in0","affine_func$add_all__U346.out"], + ["affine_func$const_term_U339.out","affine_func$add_all__U347.in1"], + ["time_diff.in0","affine_func$add_all__U347.out"], + ["affine_func$mul_d0__U324.in0","affine_func$coeff_0_U323.out"], + ["affine_func$mul_d1__U326.in0","affine_func$coeff_1_U325.out"], + ["affine_func$mul_d2__U328.in0","affine_func$coeff_2_U327.out"], + ["affine_func$mul_d3__U330.in0","affine_func$coeff_3_U329.out"], + ["affine_func$mul_d4__U332.in0","affine_func$coeff_4_U331.out"], + ["affine_func$mul_d5__U334.in0","affine_func$coeff_5_U333.out"], + ["affine_func$mul_d6__U336.in0","affine_func$coeff_6_U335.out"], + ["affine_func$mul_d7__U338.in0","affine_func$coeff_7_U337.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U324.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U326.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U328.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U330.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U332.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U334.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U336.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U338.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["d_7_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -4990,31 +5531,40 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U367$lut$lut.bit.in.2","d_0_am__U367$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U367$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U367$lut$lut.bit.in.1"], - ["d_0_am__U368$lut$lut.bit.in.0","d_0_am__U367$lut$lut.bit.out"], - ["d_0_am__U368$lut$lut.bit.in.2","d_0_am__U368$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U368$lut$lut.bit.in.1"], - ["d_0_am__U369$lut$lut.bit.in.0","d_0_am__U368$lut$lut.bit.out"], - ["d_0_am__U369$lut$lut.bit.in.2","d_0_am__U369$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U369$lut$lut.bit.in.1"], - ["d_0_am__U370$lut$lut.bit.in.0","d_0_am__U369$lut$lut.bit.out"], - ["d_0_am__U370$lut$lut.bit.in.2","d_0_am__U370$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U370$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U370$lut$lut.bit.out"], + ["d_0_am__U350$lut$lut.bit.in.2","d_0_am__U350$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U350$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U350$lut$lut.bit.in.1"], + ["d_0_am__U351$lut$lut.bit.in.0","d_0_am__U350$lut$lut.bit.out"], + ["d_0_am__U351$lut$lut.bit.in.2","d_0_am__U351$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U351$lut$lut.bit.in.1"], + ["d_0_am__U352$lut$lut.bit.in.0","d_0_am__U351$lut$lut.bit.out"], + ["d_0_am__U352$lut$lut.bit.in.2","d_0_am__U352$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U352$lut$lut.bit.in.1"], + ["d_0_am__U353$lut$lut.bit.in.0","d_0_am__U352$lut$lut.bit.out"], + ["d_0_am__U353$lut$lut.bit.in.2","d_0_am__U353$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U353$lut$lut.bit.in.1"], + ["d_0_am__U354$lut$lut.bit.in.0","d_0_am__U353$lut$lut.bit.out"], + ["d_0_am__U354$lut$lut.bit.in.2","d_0_am__U354$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U354$lut$lut.bit.in.1"], + ["d_0_am__U355$lut$lut.bit.in.0","d_0_am__U354$lut$lut.bit.out"], + ["d_0_am__U355$lut$lut.bit.in.2","d_0_am__U355$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U355$lut$lut.bit.in.1"], + ["d_0_am__U356$lut$lut.bit.in.0","d_0_am__U355$lut$lut.bit.out"], + ["d_0_am__U356$lut$lut.bit.in.2","d_0_am__U356$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U356$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U356$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5031,16 +5581,25 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U371$lut$lut.bit.in.2","d_1_am__U371$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U371$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U371$lut$lut.bit.in.1"], - ["d_1_am__U372$lut$lut.bit.in.0","d_1_am__U371$lut$lut.bit.out"], - ["d_1_am__U372$lut$lut.bit.in.2","d_1_am__U372$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U372$lut$lut.bit.in.1"], - ["d_1_am__U373$lut$lut.bit.in.0","d_1_am__U372$lut$lut.bit.out"], - ["d_1_am__U373$lut$lut.bit.in.2","d_1_am__U373$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U373$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U373$lut$lut.bit.out"], + ["d_1_am__U357$lut$lut.bit.in.2","d_1_am__U357$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U357$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U357$lut$lut.bit.in.1"], + ["d_1_am__U358$lut$lut.bit.in.0","d_1_am__U357$lut$lut.bit.out"], + ["d_1_am__U358$lut$lut.bit.in.2","d_1_am__U358$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U358$lut$lut.bit.in.1"], + ["d_1_am__U359$lut$lut.bit.in.0","d_1_am__U358$lut$lut.bit.out"], + ["d_1_am__U359$lut$lut.bit.in.2","d_1_am__U359$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U359$lut$lut.bit.in.1"], + ["d_1_am__U360$lut$lut.bit.in.0","d_1_am__U359$lut$lut.bit.out"], + ["d_1_am__U360$lut$lut.bit.in.2","d_1_am__U360$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U360$lut$lut.bit.in.1"], + ["d_1_am__U361$lut$lut.bit.in.0","d_1_am__U360$lut$lut.bit.out"], + ["d_1_am__U361$lut$lut.bit.in.2","d_1_am__U361$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U361$lut$lut.bit.in.1"], + ["d_1_am__U362$lut$lut.bit.in.0","d_1_am__U361$lut$lut.bit.out"], + ["d_1_am__U362$lut$lut.bit.in.2","d_1_am__U362$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U362$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U362$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5057,13 +5616,22 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U374$lut$lut.bit.in.2","d_2_am__U374$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U374$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U374$lut$lut.bit.in.1"], - ["d_2_am__U375$lut$lut.bit.in.0","d_2_am__U374$lut$lut.bit.out"], - ["d_2_am__U375$lut$lut.bit.in.2","d_2_am__U375$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U375$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U375$lut$lut.bit.out"], + ["d_2_am__U363$lut$lut.bit.in.2","d_2_am__U363$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U363$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U363$lut$lut.bit.in.1"], + ["d_2_am__U364$lut$lut.bit.in.0","d_2_am__U363$lut$lut.bit.out"], + ["d_2_am__U364$lut$lut.bit.in.2","d_2_am__U364$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U364$lut$lut.bit.in.1"], + ["d_2_am__U365$lut$lut.bit.in.0","d_2_am__U364$lut$lut.bit.out"], + ["d_2_am__U365$lut$lut.bit.in.2","d_2_am__U365$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U365$lut$lut.bit.in.1"], + ["d_2_am__U366$lut$lut.bit.in.0","d_2_am__U365$lut$lut.bit.out"], + ["d_2_am__U366$lut$lut.bit.in.2","d_2_am__U366$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U366$lut$lut.bit.in.1"], + ["d_2_am__U367$lut$lut.bit.in.0","d_2_am__U366$lut$lut.bit.out"], + ["d_2_am__U367$lut$lut.bit.in.2","d_2_am__U367$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U367$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U367$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5080,10 +5648,19 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U376$lut$lut.bit.in.2","d_3_am__U376$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U376$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U376$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U376$lut$lut.bit.out"], + ["d_3_am__U368$lut$lut.bit.in.2","d_3_am__U368$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U368$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U368$lut$lut.bit.in.1"], + ["d_3_am__U369$lut$lut.bit.in.0","d_3_am__U368$lut$lut.bit.out"], + ["d_3_am__U369$lut$lut.bit.in.2","d_3_am__U369$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U369$lut$lut.bit.in.1"], + ["d_3_am__U370$lut$lut.bit.in.0","d_3_am__U369$lut$lut.bit.out"], + ["d_3_am__U370$lut$lut.bit.in.2","d_3_am__U370$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U370$lut$lut.bit.in.1"], + ["d_3_am__U371$lut$lut.bit.in.0","d_3_am__U370$lut$lut.bit.out"], + ["d_3_am__U371$lut$lut.bit.in.2","d_3_am__U371$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U371$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U371$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5100,6 +5677,16 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U372$lut$lut.bit.in.2","d_4_am__U372$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U372$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U372$lut$lut.bit.in.1"], + ["d_4_am__U373$lut$lut.bit.in.0","d_4_am__U372$lut$lut.bit.out"], + ["d_4_am__U373$lut$lut.bit.in.2","d_4_am__U373$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U373$lut$lut.bit.in.1"], + ["d_4_am__U374$lut$lut.bit.in.0","d_4_am__U373$lut$lut.bit.out"], + ["d_4_am__U374$lut$lut.bit.in.2","d_4_am__U374$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U374$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U374$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -5109,175 +5696,180 @@ ["d_4_reg$reg0.out","d_4_next_value.in0"], ["d_4_next_value_at_max.out","d_4_next_value.in1"], ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["true_lutcnst.bit.out","d_4_next_value.sel"], ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], ["self.rst_n","d_4_reg$clrMux.sel"], ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"] - ] - }, - "affine_controller__U396":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",8,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U423":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4231":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4232":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4233":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U375$lut$lut.bit.in.2","d_5_am__U375$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U375$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U375$lut$lut.bit.in.1"], + ["d_5_am__U376$lut$lut.bit.in.0","d_5_am__U375$lut$lut.bit.out"], + ["d_5_am__U376$lut$lut.bit.in.2","d_5_am__U376$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U376$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U376$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_am__U377$lut$lut.bit.in.2","d_6_am__U377$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U377$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U377$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U377$lut$lut.bit.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"], + ["d_7_reg$reg0.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg$reg0.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg$reg0.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg$enMux.in1","d_7_next_value.out"], + ["true_lutcnst.bit.out","d_7_next_value.sel"], + ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], + ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], + ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], + ["self.rst_n","d_7_reg$clrMux.sel"], + ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], + ["self.clk","d_7_reg$reg0.clk"], + ["self.d.7","d_7_reg$reg0.out"] + ] + }, + "affine_controller__U407":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",5,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U425":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4234":{ + "_U4251":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4235":{ + "_U4252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4236":{ + "_U4253":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4237":{ + "_U4254":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U424":{ + "_U426":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U415":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U416":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U417":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U418":{ + "affine_func$add_all__U420":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U419":{ + "affine_func$add_all__U421":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U420":{ + "affine_func$add_all__U422":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U421":{ + "affine_func$add_all__U423":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U422":{ + "affine_func$add_all__U424":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U398":{ + "affine_func$coeff_0_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U400":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} - }, - "affine_func$coeff_2_U402":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000007e0"]} - }, - "affine_func$coeff_3_U404":{ + "affine_func$coeff_1_U411":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000180"]} + "modargs":{"value":[["BitVector",32],"32'h00000c00"]} }, - "affine_func$coeff_4_U406":{ + "affine_func$coeff_2_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} + "modargs":{"value":[["BitVector",32],"32'h00000400"]} }, - "affine_func$coeff_5_U408":{ + "affine_func$coeff_3_U415":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000020"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_6_U410":{ + "affine_func$coeff_4_U417":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000004"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "affine_func$coeff_7_U412":{ + "affine_func$const_term_U419":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U414":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000023ff"]} - }, - "affine_func$mul_d0__U399":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U401":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d2__U403":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d3__U405":{ + "affine_func$mul_d0__U410":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U407":{ + "affine_func$mul_d1__U412":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U409":{ + "affine_func$mul_d2__U414":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U411":{ + "affine_func$mul_d3__U416":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d7__U413":{ + "affine_func$mul_d4__U418":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5341,26 +5933,6 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U425$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U425$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U426$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U426$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_0_am__U427$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -5401,16 +5973,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U431$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U431$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -5455,62 +6017,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U432$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U432$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U433$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U433$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U434$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U434$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U435$c0_lutcnst":{ + "d_1_am__U431$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U435$lut$lut":{ + "d_1_am__U431$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U436$c0_lutcnst":{ + "d_1_am__U432$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U436$lut$lut":{ + "d_1_am__U432$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U437$c0_lutcnst":{ + "d_1_am__U433$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U437$lut$lut":{ + "d_1_am__U433$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5526,7 +6058,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -5559,52 +6091,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U438$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U438$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U439$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U439$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U440$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U440$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U441$c0_lutcnst":{ + "d_2_am__U434$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U441$lut$lut":{ + "d_2_am__U434$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U442$c0_lutcnst":{ + "d_2_am__U435$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U442$lut$lut":{ + "d_2_am__U435$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5620,7 +6122,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -5653,42 +6155,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U443$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U443$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U444$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U444$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U445$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U445$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U446$c0_lutcnst":{ + "d_3_am__U436$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U446$lut$lut":{ + "d_3_am__U436$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5704,7 +6176,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -5737,36 +6209,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U447$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U447$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U448$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U448$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U449$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U449$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -5778,7 +6220,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, "d_4_min":{ "genref":"coreir.const", @@ -5811,188 +6253,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U450$c0_lutcnst":{ + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_5_am__U450$lut$lut":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_5_am__U451$c0_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_5_am__U451$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_5_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_5_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "d_5_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_6_am__U452$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_6_am__U452$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_6_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_6_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_6_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_6_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_7_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_7_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_7_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "d_7_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true2_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true3_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true4_lutcnst":{ + "true4_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} @@ -6007,21 +6287,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6029,57 +6294,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U423.out"], - ["d_1_inc.in1","_U4231.out"], - ["d_2_inc.in1","_U4232.out"], - ["d_3_inc.in1","_U4233.out"], - ["d_4_inc.in1","_U4234.out"], - ["d_5_inc.in1","_U4235.out"], - ["d_6_inc.in1","_U4236.out"], - ["d_7_inc.in1","_U4237.out"], - ["cmp_time.in1","_U424.out"], - ["affine_func$mul_d0__U399.out","affine_func$add_all__U415.in0"], - ["affine_func$mul_d1__U401.out","affine_func$add_all__U415.in1"], - ["affine_func$add_all__U416.in0","affine_func$add_all__U415.out"], - ["affine_func$mul_d2__U403.out","affine_func$add_all__U416.in1"], - ["affine_func$add_all__U417.in0","affine_func$add_all__U416.out"], - ["affine_func$mul_d3__U405.out","affine_func$add_all__U417.in1"], - ["affine_func$add_all__U418.in0","affine_func$add_all__U417.out"], - ["affine_func$mul_d4__U407.out","affine_func$add_all__U418.in1"], - ["affine_func$add_all__U419.in0","affine_func$add_all__U418.out"], - ["affine_func$mul_d5__U409.out","affine_func$add_all__U419.in1"], - ["affine_func$add_all__U420.in0","affine_func$add_all__U419.out"], - ["affine_func$mul_d6__U411.out","affine_func$add_all__U420.in1"], + ["d_0_inc.in1","_U425.out"], + ["d_1_inc.in1","_U4251.out"], + ["d_2_inc.in1","_U4252.out"], + ["d_3_inc.in1","_U4253.out"], + ["d_4_inc.in1","_U4254.out"], + ["cmp_time.in1","_U426.out"], + ["affine_func$mul_d0__U410.out","affine_func$add_all__U420.in0"], + ["affine_func$mul_d1__U412.out","affine_func$add_all__U420.in1"], ["affine_func$add_all__U421.in0","affine_func$add_all__U420.out"], - ["affine_func$mul_d7__U413.out","affine_func$add_all__U421.in1"], + ["affine_func$mul_d2__U414.out","affine_func$add_all__U421.in1"], ["affine_func$add_all__U422.in0","affine_func$add_all__U421.out"], - ["affine_func$const_term_U414.out","affine_func$add_all__U422.in1"], - ["time_diff.in0","affine_func$add_all__U422.out"], - ["affine_func$mul_d0__U399.in0","affine_func$coeff_0_U398.out"], - ["affine_func$mul_d1__U401.in0","affine_func$coeff_1_U400.out"], - ["affine_func$mul_d2__U403.in0","affine_func$coeff_2_U402.out"], - ["affine_func$mul_d3__U405.in0","affine_func$coeff_3_U404.out"], - ["affine_func$mul_d4__U407.in0","affine_func$coeff_4_U406.out"], - ["affine_func$mul_d5__U409.in0","affine_func$coeff_5_U408.out"], - ["affine_func$mul_d6__U411.in0","affine_func$coeff_6_U410.out"], - ["affine_func$mul_d7__U413.in0","affine_func$coeff_7_U412.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U399.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U401.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U403.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U405.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U407.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U409.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U411.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U413.in1"], + ["affine_func$mul_d3__U416.out","affine_func$add_all__U422.in1"], + ["affine_func$add_all__U423.in0","affine_func$add_all__U422.out"], + ["affine_func$mul_d4__U418.out","affine_func$add_all__U423.in1"], + ["affine_func$add_all__U424.in0","affine_func$add_all__U423.out"], + ["affine_func$const_term_U419.out","affine_func$add_all__U424.in1"], + ["time_diff.in0","affine_func$add_all__U424.out"], + ["affine_func$mul_d0__U410.in0","affine_func$coeff_0_U409.out"], + ["affine_func$mul_d1__U412.in0","affine_func$coeff_1_U411.out"], + ["affine_func$mul_d2__U414.in0","affine_func$coeff_2_U413.out"], + ["affine_func$mul_d3__U416.in0","affine_func$coeff_3_U415.out"], + ["affine_func$mul_d4__U418.in0","affine_func$coeff_4_U417.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U410.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U412.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U414.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U416.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U418.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], - ["d_7_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -6087,40 +6334,31 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U425$lut$lut.bit.in.2","d_0_am__U425$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U425$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U425$lut$lut.bit.in.1"], - ["d_0_am__U426$lut$lut.bit.in.0","d_0_am__U425$lut$lut.bit.out"], - ["d_0_am__U426$lut$lut.bit.in.2","d_0_am__U426$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U426$lut$lut.bit.in.1"], - ["d_0_am__U427$lut$lut.bit.in.0","d_0_am__U426$lut$lut.bit.out"], ["d_0_am__U427$lut$lut.bit.in.2","d_0_am__U427$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U427$lut$lut.bit.in.1"], + ["true1_lutcnst.bit.out","d_0_am__U427$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U427$lut$lut.bit.in.1"], ["d_0_am__U428$lut$lut.bit.in.0","d_0_am__U427$lut$lut.bit.out"], ["d_0_am__U428$lut$lut.bit.in.2","d_0_am__U428$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U428$lut$lut.bit.in.1"], + ["d_2_at_max.out","d_0_am__U428$lut$lut.bit.in.1"], ["d_0_am__U429$lut$lut.bit.in.0","d_0_am__U428$lut$lut.bit.out"], ["d_0_am__U429$lut$lut.bit.in.2","d_0_am__U429$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U429$lut$lut.bit.in.1"], + ["d_3_at_max.out","d_0_am__U429$lut$lut.bit.in.1"], ["d_0_am__U430$lut$lut.bit.in.0","d_0_am__U429$lut$lut.bit.out"], ["d_0_am__U430$lut$lut.bit.in.2","d_0_am__U430$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U430$lut$lut.bit.in.1"], - ["d_0_am__U431$lut$lut.bit.in.0","d_0_am__U430$lut$lut.bit.out"], - ["d_0_am__U431$lut$lut.bit.in.2","d_0_am__U431$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U431$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U431$lut$lut.bit.out"], + ["d_4_at_max.out","d_0_am__U430$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U430$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6137,25 +6375,16 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U431$lut$lut.bit.in.2","d_1_am__U431$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U431$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U431$lut$lut.bit.in.1"], + ["d_1_am__U432$lut$lut.bit.in.0","d_1_am__U431$lut$lut.bit.out"], ["d_1_am__U432$lut$lut.bit.in.2","d_1_am__U432$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U432$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U432$lut$lut.bit.in.1"], + ["d_3_at_max.out","d_1_am__U432$lut$lut.bit.in.1"], ["d_1_am__U433$lut$lut.bit.in.0","d_1_am__U432$lut$lut.bit.out"], ["d_1_am__U433$lut$lut.bit.in.2","d_1_am__U433$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U433$lut$lut.bit.in.1"], - ["d_1_am__U434$lut$lut.bit.in.0","d_1_am__U433$lut$lut.bit.out"], - ["d_1_am__U434$lut$lut.bit.in.2","d_1_am__U434$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U434$lut$lut.bit.in.1"], - ["d_1_am__U435$lut$lut.bit.in.0","d_1_am__U434$lut$lut.bit.out"], - ["d_1_am__U435$lut$lut.bit.in.2","d_1_am__U435$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U435$lut$lut.bit.in.1"], - ["d_1_am__U436$lut$lut.bit.in.0","d_1_am__U435$lut$lut.bit.out"], - ["d_1_am__U436$lut$lut.bit.in.2","d_1_am__U436$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U436$lut$lut.bit.in.1"], - ["d_1_am__U437$lut$lut.bit.in.0","d_1_am__U436$lut$lut.bit.out"], - ["d_1_am__U437$lut$lut.bit.in.2","d_1_am__U437$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U437$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U437$lut$lut.bit.out"], + ["d_4_at_max.out","d_1_am__U433$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U433$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -6172,22 +6401,13 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U438$lut$lut.bit.in.2","d_2_am__U438$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U438$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U438$lut$lut.bit.in.1"], - ["d_2_am__U439$lut$lut.bit.in.0","d_2_am__U438$lut$lut.bit.out"], - ["d_2_am__U439$lut$lut.bit.in.2","d_2_am__U439$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U439$lut$lut.bit.in.1"], - ["d_2_am__U440$lut$lut.bit.in.0","d_2_am__U439$lut$lut.bit.out"], - ["d_2_am__U440$lut$lut.bit.in.2","d_2_am__U440$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U440$lut$lut.bit.in.1"], - ["d_2_am__U441$lut$lut.bit.in.0","d_2_am__U440$lut$lut.bit.out"], - ["d_2_am__U441$lut$lut.bit.in.2","d_2_am__U441$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U441$lut$lut.bit.in.1"], - ["d_2_am__U442$lut$lut.bit.in.0","d_2_am__U441$lut$lut.bit.out"], - ["d_2_am__U442$lut$lut.bit.in.2","d_2_am__U442$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U442$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U442$lut$lut.bit.out"], + ["d_2_am__U434$lut$lut.bit.in.2","d_2_am__U434$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U434$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U434$lut$lut.bit.in.1"], + ["d_2_am__U435$lut$lut.bit.in.0","d_2_am__U434$lut$lut.bit.out"], + ["d_2_am__U435$lut$lut.bit.in.2","d_2_am__U435$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U435$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U435$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -6204,19 +6424,10 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U443$lut$lut.bit.in.2","d_3_am__U443$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U443$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U443$lut$lut.bit.in.1"], - ["d_3_am__U444$lut$lut.bit.in.0","d_3_am__U443$lut$lut.bit.out"], - ["d_3_am__U444$lut$lut.bit.in.2","d_3_am__U444$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U444$lut$lut.bit.in.1"], - ["d_3_am__U445$lut$lut.bit.in.0","d_3_am__U444$lut$lut.bit.out"], - ["d_3_am__U445$lut$lut.bit.in.2","d_3_am__U445$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U445$lut$lut.bit.in.1"], - ["d_3_am__U446$lut$lut.bit.in.0","d_3_am__U445$lut$lut.bit.out"], - ["d_3_am__U446$lut$lut.bit.in.2","d_3_am__U446$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U446$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U446$lut$lut.bit.out"], + ["d_3_am__U436$lut$lut.bit.in.2","d_3_am__U436$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U436$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U436$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U436$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -6233,16 +6444,6 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U447$lut$lut.bit.in.2","d_4_am__U447$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U447$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U447$lut$lut.bit.in.1"], - ["d_4_am__U448$lut$lut.bit.in.0","d_4_am__U447$lut$lut.bit.out"], - ["d_4_am__U448$lut$lut.bit.in.2","d_4_am__U448$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U448$lut$lut.bit.in.1"], - ["d_4_am__U449$lut$lut.bit.in.0","d_4_am__U448$lut$lut.bit.out"], - ["d_4_am__U449$lut$lut.bit.in.2","d_4_am__U449$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U449$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U449$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -6252,559 +6453,866 @@ ["d_4_reg$reg0.out","d_4_next_value.in0"], ["d_4_next_value_at_max.out","d_4_next_value.in1"], ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["true_lutcnst.bit.out","d_4_next_value.sel"], ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], ["self.rst_n","d_4_reg$clrMux.sel"], ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U450$lut$lut.bit.in.2","d_5_am__U450$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U450$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U450$lut$lut.bit.in.1"], - ["d_5_am__U451$lut$lut.bit.in.0","d_5_am__U450$lut$lut.bit.out"], - ["d_5_am__U451$lut$lut.bit.in.2","d_5_am__U451$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U451$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U451$lut$lut.bit.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U452$lut$lut.bit.in.2","d_6_am__U452$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U452$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U452$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U452$lut$lut.bit.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"], - ["d_7_reg$reg0.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg$reg0.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg$reg0.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg$enMux.in1","d_7_next_value.out"], - ["true_lutcnst.bit.out","d_7_next_value.sel"], - ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], - ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], - ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], - ["self.rst_n","d_7_reg$clrMux.sel"], - ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], - ["self.clk","d_7_reg$reg0.clk"], - ["self.d.7","d_7_reg$reg0.out"] + ["self.d.4","d_4_reg$reg0.out"] ] }, - "affine_controller__U483":{ + "affine_controller__U456":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], + ["d",["Array",8,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U501":{ + "_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5011":{ + "_U4831":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5012":{ + "_U4832":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5013":{ + "_U4833":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5014":{ + "_U4834":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U502":{ + "_U4835":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U4836":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U4837":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U484":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U496":{ + "affine_func$add_all__U475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U497":{ + "affine_func$add_all__U476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U498":{ + "affine_func$add_all__U477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U499":{ + "affine_func$add_all__U478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U500":{ + "affine_func$add_all__U479":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U485":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$coeff_1_U487":{ + "affine_func$add_all__U480":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U481":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U482":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U458":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000c00"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_2_U489":{ + "affine_func$coeff_1_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000400"]} + "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "affine_func$coeff_3_U491":{ + "affine_func$coeff_2_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "affine_func$coeff_4_U493":{ + "affine_func$coeff_3_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000180"]} }, - "affine_func$const_term_U495":{ + "affine_func$coeff_4_U466":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "affine_func$coeff_5_U468":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000020"]} + }, + "affine_func$coeff_6_U470":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000004"]} + }, + "affine_func$coeff_7_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$mul_d0__U486":{ + "affine_func$const_term_U474":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h000023ff"]} + }, + "affine_func$mul_d0__U459":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U461":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U488":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "affine_func$mul_d3__U465":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d4__U467":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U469":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d6__U471":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d7__U473":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$count$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} + }, + "d_0_am__U485$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U485$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U486$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U486$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U487$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U487$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U488$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U488$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U489$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U489$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U490$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U490$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U491$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U491$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U492$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U492$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U493$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U493$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U494$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U494$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U495$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U495$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U496$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U496$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U497$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U497$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_am__U498$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U498$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$mul_d2__U490":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_am__U499$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$mul_d3__U492":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_am__U499$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$mul_d4__U494":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_am__U500$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_2_am__U500$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_2_am__U501$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$c0_lutcnst":{ + "d_2_am__U501$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U502$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$lut$lut":{ + "d_2_am__U502$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$c0":{ + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$count$clrMux":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$enMux":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cycle_time$ult":{ - "genref":"coreir.ult", + "d_2_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_am__U503$c0_lutcnst":{ + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_am__U503$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U503$lut$lut":{ + "d_3_am__U503$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U504$c0_lutcnst":{ + "d_3_am__U504$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U504$lut$lut":{ + "d_3_am__U504$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U505$c0_lutcnst":{ + "d_3_am__U505$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U505$lut$lut":{ + "d_3_am__U505$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U506$c0_lutcnst":{ + "d_3_am__U506$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U506$lut$lut":{ + "d_3_am__U506$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "d_0_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U507$c0_lutcnst":{ + "d_4_am__U507$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U507$lut$lut":{ + "d_4_am__U507$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U508$c0_lutcnst":{ + "d_4_am__U508$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U508$lut$lut":{ + "d_4_am__U508$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U509$c0_lutcnst":{ + "d_4_am__U509$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U509$lut$lut":{ + "d_4_am__U509$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_at_max":{ + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "d_1_min":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_4_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_4_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$c0":{ + "d_4_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ + "d_4_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ + "d_4_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ + "d_4_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U510$c0_lutcnst":{ + "d_5_am__U510$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U510$lut$lut":{ + "d_5_am__U510$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U511$c0_lutcnst":{ + "d_5_am__U511$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U511$lut$lut":{ + "d_5_am__U511$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_at_max":{ + "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_2_inc":{ + "d_5_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_max":{ + "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "d_2_min":{ + "d_5_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ + "d_5_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ + "d_5_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$c0":{ + "d_5_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ + "d_5_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$enMux":{ + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U512$c0_lutcnst":{ + "d_6_am__U512$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U512$lut$lut":{ + "d_6_am__U512$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_at_max":{ + "d_6_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_3_inc":{ + "d_6_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ + "d_6_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_3_min":{ + "d_6_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "d_6_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "d_6_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$c0":{ + "d_6_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_reg$clrMux":{ + "d_6_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$enMux":{ + "d_6_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ + "d_6_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_at_max":{ + "d_7_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_7_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_7_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "d_4_min":{ + "d_7_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_7_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_7_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_7_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_7_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_7_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_7_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -6843,6 +7351,21 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true8_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true9_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -6850,39 +7373,57 @@ } }, "connections":[ - ["d_0_inc.in1","_U501.out"], - ["d_1_inc.in1","_U5011.out"], - ["d_2_inc.in1","_U5012.out"], - ["d_3_inc.in1","_U5013.out"], - ["d_4_inc.in1","_U5014.out"], - ["cmp_time.in1","_U502.out"], - ["affine_func$mul_d0__U486.out","affine_func$add_all__U496.in0"], - ["affine_func$mul_d1__U488.out","affine_func$add_all__U496.in1"], - ["affine_func$add_all__U497.in0","affine_func$add_all__U496.out"], - ["affine_func$mul_d2__U490.out","affine_func$add_all__U497.in1"], - ["affine_func$add_all__U498.in0","affine_func$add_all__U497.out"], - ["affine_func$mul_d3__U492.out","affine_func$add_all__U498.in1"], - ["affine_func$add_all__U499.in0","affine_func$add_all__U498.out"], - ["affine_func$mul_d4__U494.out","affine_func$add_all__U499.in1"], - ["affine_func$add_all__U500.in0","affine_func$add_all__U499.out"], - ["affine_func$const_term_U495.out","affine_func$add_all__U500.in1"], - ["time_diff.in0","affine_func$add_all__U500.out"], - ["affine_func$mul_d0__U486.in0","affine_func$coeff_0_U485.out"], - ["affine_func$mul_d1__U488.in0","affine_func$coeff_1_U487.out"], - ["affine_func$mul_d2__U490.in0","affine_func$coeff_2_U489.out"], - ["affine_func$mul_d3__U492.in0","affine_func$coeff_3_U491.out"], - ["affine_func$mul_d4__U494.in0","affine_func$coeff_4_U493.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U486.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U488.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U490.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U492.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U494.in1"], + ["d_0_inc.in1","_U483.out"], + ["d_1_inc.in1","_U4831.out"], + ["d_2_inc.in1","_U4832.out"], + ["d_3_inc.in1","_U4833.out"], + ["d_4_inc.in1","_U4834.out"], + ["d_5_inc.in1","_U4835.out"], + ["d_6_inc.in1","_U4836.out"], + ["d_7_inc.in1","_U4837.out"], + ["cmp_time.in1","_U484.out"], + ["affine_func$mul_d0__U459.out","affine_func$add_all__U475.in0"], + ["affine_func$mul_d1__U461.out","affine_func$add_all__U475.in1"], + ["affine_func$add_all__U476.in0","affine_func$add_all__U475.out"], + ["affine_func$mul_d2__U463.out","affine_func$add_all__U476.in1"], + ["affine_func$add_all__U477.in0","affine_func$add_all__U476.out"], + ["affine_func$mul_d3__U465.out","affine_func$add_all__U477.in1"], + ["affine_func$add_all__U478.in0","affine_func$add_all__U477.out"], + ["affine_func$mul_d4__U467.out","affine_func$add_all__U478.in1"], + ["affine_func$add_all__U479.in0","affine_func$add_all__U478.out"], + ["affine_func$mul_d5__U469.out","affine_func$add_all__U479.in1"], + ["affine_func$add_all__U480.in0","affine_func$add_all__U479.out"], + ["affine_func$mul_d6__U471.out","affine_func$add_all__U480.in1"], + ["affine_func$add_all__U481.in0","affine_func$add_all__U480.out"], + ["affine_func$mul_d7__U473.out","affine_func$add_all__U481.in1"], + ["affine_func$add_all__U482.in0","affine_func$add_all__U481.out"], + ["affine_func$const_term_U474.out","affine_func$add_all__U482.in1"], + ["time_diff.in0","affine_func$add_all__U482.out"], + ["affine_func$mul_d0__U459.in0","affine_func$coeff_0_U458.out"], + ["affine_func$mul_d1__U461.in0","affine_func$coeff_1_U460.out"], + ["affine_func$mul_d2__U463.in0","affine_func$coeff_2_U462.out"], + ["affine_func$mul_d3__U465.in0","affine_func$coeff_3_U464.out"], + ["affine_func$mul_d4__U467.in0","affine_func$coeff_4_U466.out"], + ["affine_func$mul_d5__U469.in0","affine_func$coeff_5_U468.out"], + ["affine_func$mul_d6__U471.in0","affine_func$coeff_6_U470.out"], + ["affine_func$mul_d7__U473.in0","affine_func$coeff_7_U472.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U459.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U461.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U463.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U465.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U467.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U469.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U471.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U473.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["d_7_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -6890,31 +7431,40 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U503$lut$lut.bit.in.2","d_0_am__U503$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U503$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U503$lut$lut.bit.in.1"], - ["d_0_am__U504$lut$lut.bit.in.0","d_0_am__U503$lut$lut.bit.out"], - ["d_0_am__U504$lut$lut.bit.in.2","d_0_am__U504$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U504$lut$lut.bit.in.1"], - ["d_0_am__U505$lut$lut.bit.in.0","d_0_am__U504$lut$lut.bit.out"], - ["d_0_am__U505$lut$lut.bit.in.2","d_0_am__U505$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U505$lut$lut.bit.in.1"], - ["d_0_am__U506$lut$lut.bit.in.0","d_0_am__U505$lut$lut.bit.out"], - ["d_0_am__U506$lut$lut.bit.in.2","d_0_am__U506$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U506$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U506$lut$lut.bit.out"], + ["d_0_am__U485$lut$lut.bit.in.2","d_0_am__U485$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U485$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U485$lut$lut.bit.in.1"], + ["d_0_am__U486$lut$lut.bit.in.0","d_0_am__U485$lut$lut.bit.out"], + ["d_0_am__U486$lut$lut.bit.in.2","d_0_am__U486$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U486$lut$lut.bit.in.1"], + ["d_0_am__U487$lut$lut.bit.in.0","d_0_am__U486$lut$lut.bit.out"], + ["d_0_am__U487$lut$lut.bit.in.2","d_0_am__U487$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U487$lut$lut.bit.in.1"], + ["d_0_am__U488$lut$lut.bit.in.0","d_0_am__U487$lut$lut.bit.out"], + ["d_0_am__U488$lut$lut.bit.in.2","d_0_am__U488$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U488$lut$lut.bit.in.1"], + ["d_0_am__U489$lut$lut.bit.in.0","d_0_am__U488$lut$lut.bit.out"], + ["d_0_am__U489$lut$lut.bit.in.2","d_0_am__U489$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U489$lut$lut.bit.in.1"], + ["d_0_am__U490$lut$lut.bit.in.0","d_0_am__U489$lut$lut.bit.out"], + ["d_0_am__U490$lut$lut.bit.in.2","d_0_am__U490$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U490$lut$lut.bit.in.1"], + ["d_0_am__U491$lut$lut.bit.in.0","d_0_am__U490$lut$lut.bit.out"], + ["d_0_am__U491$lut$lut.bit.in.2","d_0_am__U491$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U491$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U491$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6931,16 +7481,25 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U507$lut$lut.bit.in.2","d_1_am__U507$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U507$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U507$lut$lut.bit.in.1"], - ["d_1_am__U508$lut$lut.bit.in.0","d_1_am__U507$lut$lut.bit.out"], - ["d_1_am__U508$lut$lut.bit.in.2","d_1_am__U508$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U508$lut$lut.bit.in.1"], - ["d_1_am__U509$lut$lut.bit.in.0","d_1_am__U508$lut$lut.bit.out"], - ["d_1_am__U509$lut$lut.bit.in.2","d_1_am__U509$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U509$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U509$lut$lut.bit.out"], + ["d_1_am__U492$lut$lut.bit.in.2","d_1_am__U492$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U492$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U492$lut$lut.bit.in.1"], + ["d_1_am__U493$lut$lut.bit.in.0","d_1_am__U492$lut$lut.bit.out"], + ["d_1_am__U493$lut$lut.bit.in.2","d_1_am__U493$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U493$lut$lut.bit.in.1"], + ["d_1_am__U494$lut$lut.bit.in.0","d_1_am__U493$lut$lut.bit.out"], + ["d_1_am__U494$lut$lut.bit.in.2","d_1_am__U494$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U494$lut$lut.bit.in.1"], + ["d_1_am__U495$lut$lut.bit.in.0","d_1_am__U494$lut$lut.bit.out"], + ["d_1_am__U495$lut$lut.bit.in.2","d_1_am__U495$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U495$lut$lut.bit.in.1"], + ["d_1_am__U496$lut$lut.bit.in.0","d_1_am__U495$lut$lut.bit.out"], + ["d_1_am__U496$lut$lut.bit.in.2","d_1_am__U496$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U496$lut$lut.bit.in.1"], + ["d_1_am__U497$lut$lut.bit.in.0","d_1_am__U496$lut$lut.bit.out"], + ["d_1_am__U497$lut$lut.bit.in.2","d_1_am__U497$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U497$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U497$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -6957,13 +7516,22 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U510$lut$lut.bit.in.2","d_2_am__U510$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U510$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U510$lut$lut.bit.in.1"], - ["d_2_am__U511$lut$lut.bit.in.0","d_2_am__U510$lut$lut.bit.out"], - ["d_2_am__U511$lut$lut.bit.in.2","d_2_am__U511$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U511$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U511$lut$lut.bit.out"], + ["d_2_am__U498$lut$lut.bit.in.2","d_2_am__U498$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U498$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U498$lut$lut.bit.in.1"], + ["d_2_am__U499$lut$lut.bit.in.0","d_2_am__U498$lut$lut.bit.out"], + ["d_2_am__U499$lut$lut.bit.in.2","d_2_am__U499$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U499$lut$lut.bit.in.1"], + ["d_2_am__U500$lut$lut.bit.in.0","d_2_am__U499$lut$lut.bit.out"], + ["d_2_am__U500$lut$lut.bit.in.2","d_2_am__U500$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U500$lut$lut.bit.in.1"], + ["d_2_am__U501$lut$lut.bit.in.0","d_2_am__U500$lut$lut.bit.out"], + ["d_2_am__U501$lut$lut.bit.in.2","d_2_am__U501$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U501$lut$lut.bit.in.1"], + ["d_2_am__U502$lut$lut.bit.in.0","d_2_am__U501$lut$lut.bit.out"], + ["d_2_am__U502$lut$lut.bit.in.2","d_2_am__U502$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U502$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U502$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -6980,10 +7548,19 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U512$lut$lut.bit.in.2","d_3_am__U512$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U512$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U512$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U512$lut$lut.bit.out"], + ["d_3_am__U503$lut$lut.bit.in.2","d_3_am__U503$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U503$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U503$lut$lut.bit.in.1"], + ["d_3_am__U504$lut$lut.bit.in.0","d_3_am__U503$lut$lut.bit.out"], + ["d_3_am__U504$lut$lut.bit.in.2","d_3_am__U504$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U504$lut$lut.bit.in.1"], + ["d_3_am__U505$lut$lut.bit.in.0","d_3_am__U504$lut$lut.bit.out"], + ["d_3_am__U505$lut$lut.bit.in.2","d_3_am__U505$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U505$lut$lut.bit.in.1"], + ["d_3_am__U506$lut$lut.bit.in.0","d_3_am__U505$lut$lut.bit.out"], + ["d_3_am__U506$lut$lut.bit.in.2","d_3_am__U506$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U506$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U506$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -7000,6 +7577,16 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U507$lut$lut.bit.in.2","d_4_am__U507$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U507$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U507$lut$lut.bit.in.1"], + ["d_4_am__U508$lut$lut.bit.in.0","d_4_am__U507$lut$lut.bit.out"], + ["d_4_am__U508$lut$lut.bit.in.2","d_4_am__U508$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U508$lut$lut.bit.in.1"], + ["d_4_am__U509$lut$lut.bit.in.0","d_4_am__U508$lut$lut.bit.out"], + ["d_4_am__U509$lut$lut.bit.in.2","d_4_am__U509$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U509$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U509$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -7009,175 +7596,198 @@ ["d_4_reg$reg0.out","d_4_next_value.in0"], ["d_4_next_value_at_max.out","d_4_next_value.in1"], ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["true_lutcnst.bit.out","d_4_next_value.sel"], ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], ["self.rst_n","d_4_reg$clrMux.sel"], ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"] + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U510$lut$lut.bit.in.2","d_5_am__U510$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U510$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U510$lut$lut.bit.in.1"], + ["d_5_am__U511$lut$lut.bit.in.0","d_5_am__U510$lut$lut.bit.out"], + ["d_5_am__U511$lut$lut.bit.in.2","d_5_am__U511$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U511$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U511$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_am__U512$lut$lut.bit.in.2","d_6_am__U512$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U512$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U512$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U512$lut$lut.bit.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"], + ["d_7_reg$reg0.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg$reg0.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg$reg0.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg$enMux.in1","d_7_next_value.out"], + ["true_lutcnst.bit.out","d_7_next_value.sel"], + ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], + ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], + ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], + ["self.rst_n","d_7_reg$clrMux.sel"], + ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], + ["self.clk","d_7_reg$reg0.clk"], + ["self.d.7","d_7_reg$reg0.out"] ] }, - "affine_controller__U532":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",8,["Array",32,"Bit"]]], + ["d",["Array",6,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U559":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U5591":{ + "_U68":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5592":{ + "_U681":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5593":{ + "_U682":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5594":{ + "_U683":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5595":{ + "_U684":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5596":{ + "_U685":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5597":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U560":{ + "_U69":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U551":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U552":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U553":{ + "affine_func$add_all__U62":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U554":{ + "affine_func$add_all__U63":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U555":{ + "affine_func$add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U556":{ + "affine_func$add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U557":{ + "affine_func$add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U558":{ + "affine_func$add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U534":{ + "affine_func$coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U536":{ + "affine_func$coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "affine_func$coeff_2_U538":{ + "affine_func$coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000007e0"]} }, - "affine_func$coeff_3_U540":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000180"]} - }, - "affine_func$coeff_4_U542":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "affine_func$coeff_5_U544":{ + "affine_func$coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000020"]} + "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "affine_func$coeff_6_U546":{ + "affine_func$coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000004"]} }, - "affine_func$coeff_7_U548":{ + "affine_func$coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U550":{ + "affine_func$const_term_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000023ff"]} }, - "affine_func$mul_d0__U535":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U537":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d2__U539":{ + "affine_func$mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U541":{ + "affine_func$mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U543":{ + "affine_func$mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U545":{ + "affine_func$mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U547":{ + "affine_func$mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d7__U549":{ + "affine_func$mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7241,72 +7851,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U561$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U561$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U562$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U562$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U563$c0_lutcnst":{ + "d_0_am__U70$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U563$lut$lut":{ + "d_0_am__U70$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U564$c0_lutcnst":{ + "d_0_am__U71$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U564$lut$lut":{ + "d_0_am__U71$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U565$c0_lutcnst":{ + "d_0_am__U72$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U565$lut$lut":{ + "d_0_am__U72$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U566$c0_lutcnst":{ + "d_0_am__U73$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U566$lut$lut":{ + "d_0_am__U73$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U567$c0_lutcnst":{ + "d_0_am__U74$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U567$lut$lut":{ + "d_0_am__U74$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7355,62 +7945,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U568$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U568$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U569$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U569$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U570$c0_lutcnst":{ + "d_1_am__U75$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U570$lut$lut":{ + "d_1_am__U75$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U571$c0_lutcnst":{ + "d_1_am__U76$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U571$lut$lut":{ + "d_1_am__U76$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U572$c0_lutcnst":{ + "d_1_am__U77$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U572$lut$lut":{ + "d_1_am__U77$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U573$c0_lutcnst":{ + "d_1_am__U78$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U573$lut$lut":{ + "d_1_am__U78$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7459,52 +8029,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U574$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U574$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U575$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U575$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U576$c0_lutcnst":{ + "d_2_am__U79$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U576$lut$lut":{ + "d_2_am__U79$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U577$c0_lutcnst":{ + "d_2_am__U80$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U577$lut$lut":{ + "d_2_am__U80$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U578$c0_lutcnst":{ + "d_2_am__U81$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U578$lut$lut":{ + "d_2_am__U81$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7553,42 +8103,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U579$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U579$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U580$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U580$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U581$c0_lutcnst":{ + "d_3_am__U82$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U581$lut$lut":{ + "d_3_am__U82$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U582$c0_lutcnst":{ + "d_3_am__U83$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U582$lut$lut":{ + "d_3_am__U83$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7604,7 +8134,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -7637,32 +8167,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U583$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U583$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U584$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U584$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U585$c0_lutcnst":{ + "d_4_am__U84$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U585$lut$lut":{ + "d_4_am__U84$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7678,7 +8188,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_4_min":{ "genref":"coreir.const", @@ -7711,26 +8221,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U586$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U586$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U587$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U587$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -7775,104 +8265,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U588$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_6_am__U588$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_6_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_6_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_6_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_6_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_6_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_6_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_7_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_7_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_7_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "d_7_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_7_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_7_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -7912,16 +8304,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -7929,48 +8311,38 @@ } }, "connections":[ - ["d_0_inc.in1","_U559.out"], - ["d_1_inc.in1","_U5591.out"], - ["d_2_inc.in1","_U5592.out"], - ["d_3_inc.in1","_U5593.out"], - ["d_4_inc.in1","_U5594.out"], - ["d_5_inc.in1","_U5595.out"], - ["d_6_inc.in1","_U5596.out"], - ["d_7_inc.in1","_U5597.out"], - ["cmp_time.in1","_U560.out"], - ["affine_func$mul_d0__U535.out","affine_func$add_all__U551.in0"], - ["affine_func$mul_d1__U537.out","affine_func$add_all__U551.in1"], - ["affine_func$add_all__U552.in0","affine_func$add_all__U551.out"], - ["affine_func$mul_d2__U539.out","affine_func$add_all__U552.in1"], - ["affine_func$add_all__U553.in0","affine_func$add_all__U552.out"], - ["affine_func$mul_d3__U541.out","affine_func$add_all__U553.in1"], - ["affine_func$add_all__U554.in0","affine_func$add_all__U553.out"], - ["affine_func$mul_d4__U543.out","affine_func$add_all__U554.in1"], - ["affine_func$add_all__U555.in0","affine_func$add_all__U554.out"], - ["affine_func$mul_d5__U545.out","affine_func$add_all__U555.in1"], - ["affine_func$add_all__U556.in0","affine_func$add_all__U555.out"], - ["affine_func$mul_d6__U547.out","affine_func$add_all__U556.in1"], - ["affine_func$add_all__U557.in0","affine_func$add_all__U556.out"], - ["affine_func$mul_d7__U549.out","affine_func$add_all__U557.in1"], - ["affine_func$add_all__U558.in0","affine_func$add_all__U557.out"], - ["affine_func$const_term_U550.out","affine_func$add_all__U558.in1"], - ["time_diff.in0","affine_func$add_all__U558.out"], - ["affine_func$mul_d0__U535.in0","affine_func$coeff_0_U534.out"], - ["affine_func$mul_d1__U537.in0","affine_func$coeff_1_U536.out"], - ["affine_func$mul_d2__U539.in0","affine_func$coeff_2_U538.out"], - ["affine_func$mul_d3__U541.in0","affine_func$coeff_3_U540.out"], - ["affine_func$mul_d4__U543.in0","affine_func$coeff_4_U542.out"], - ["affine_func$mul_d5__U545.in0","affine_func$coeff_5_U544.out"], - ["affine_func$mul_d6__U547.in0","affine_func$coeff_6_U546.out"], - ["affine_func$mul_d7__U549.in0","affine_func$coeff_7_U548.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U535.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U537.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U539.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U541.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U543.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U545.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U547.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U549.in1"], + ["d_0_inc.in1","_U68.out"], + ["d_1_inc.in1","_U681.out"], + ["d_2_inc.in1","_U682.out"], + ["d_3_inc.in1","_U683.out"], + ["d_4_inc.in1","_U684.out"], + ["d_5_inc.in1","_U685.out"], + ["cmp_time.in1","_U69.out"], + ["affine_func$mul_d0__U50.out","affine_func$add_all__U62.in0"], + ["affine_func$mul_d1__U52.out","affine_func$add_all__U62.in1"], + ["affine_func$add_all__U63.in0","affine_func$add_all__U62.out"], + ["affine_func$mul_d2__U54.out","affine_func$add_all__U63.in1"], + ["affine_func$add_all__U64.in0","affine_func$add_all__U63.out"], + ["affine_func$mul_d3__U56.out","affine_func$add_all__U64.in1"], + ["affine_func$add_all__U65.in0","affine_func$add_all__U64.out"], + ["affine_func$mul_d4__U58.out","affine_func$add_all__U65.in1"], + ["affine_func$add_all__U66.in0","affine_func$add_all__U65.out"], + ["affine_func$mul_d5__U60.out","affine_func$add_all__U66.in1"], + ["affine_func$add_all__U67.in0","affine_func$add_all__U66.out"], + ["affine_func$const_term_U61.out","affine_func$add_all__U67.in1"], + ["time_diff.in0","affine_func$add_all__U67.out"], + ["affine_func$mul_d0__U50.in0","affine_func$coeff_0_U49.out"], + ["affine_func$mul_d1__U52.in0","affine_func$coeff_1_U51.out"], + ["affine_func$mul_d2__U54.in0","affine_func$coeff_2_U53.out"], + ["affine_func$mul_d3__U56.in0","affine_func$coeff_3_U55.out"], + ["affine_func$mul_d4__U58.in0","affine_func$coeff_4_U57.out"], + ["affine_func$mul_d5__U60.in0","affine_func$coeff_5_U59.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U50.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U52.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U54.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U56.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U58.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U60.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -7978,8 +8350,6 @@ ["d_3_reg$enMux.sel","cmp_time.out"], ["d_4_reg$enMux.sel","cmp_time.out"], ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], - ["d_7_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -7987,40 +8357,34 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U561$lut$lut.bit.in.2","d_0_am__U561$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U561$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U561$lut$lut.bit.in.1"], - ["d_0_am__U562$lut$lut.bit.in.0","d_0_am__U561$lut$lut.bit.out"], - ["d_0_am__U562$lut$lut.bit.in.2","d_0_am__U562$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U562$lut$lut.bit.in.1"], - ["d_0_am__U563$lut$lut.bit.in.0","d_0_am__U562$lut$lut.bit.out"], - ["d_0_am__U563$lut$lut.bit.in.2","d_0_am__U563$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U563$lut$lut.bit.in.1"], - ["d_0_am__U564$lut$lut.bit.in.0","d_0_am__U563$lut$lut.bit.out"], - ["d_0_am__U564$lut$lut.bit.in.2","d_0_am__U564$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U564$lut$lut.bit.in.1"], - ["d_0_am__U565$lut$lut.bit.in.0","d_0_am__U564$lut$lut.bit.out"], - ["d_0_am__U565$lut$lut.bit.in.2","d_0_am__U565$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U565$lut$lut.bit.in.1"], - ["d_0_am__U566$lut$lut.bit.in.0","d_0_am__U565$lut$lut.bit.out"], - ["d_0_am__U566$lut$lut.bit.in.2","d_0_am__U566$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U566$lut$lut.bit.in.1"], - ["d_0_am__U567$lut$lut.bit.in.0","d_0_am__U566$lut$lut.bit.out"], - ["d_0_am__U567$lut$lut.bit.in.2","d_0_am__U567$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U567$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U567$lut$lut.bit.out"], + ["d_0_am__U70$lut$lut.bit.in.2","d_0_am__U70$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U70$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U70$lut$lut.bit.in.1"], + ["d_0_am__U71$lut$lut.bit.in.0","d_0_am__U70$lut$lut.bit.out"], + ["d_0_am__U71$lut$lut.bit.in.2","d_0_am__U71$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U71$lut$lut.bit.in.1"], + ["d_0_am__U72$lut$lut.bit.in.0","d_0_am__U71$lut$lut.bit.out"], + ["d_0_am__U72$lut$lut.bit.in.2","d_0_am__U72$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U72$lut$lut.bit.in.1"], + ["d_0_am__U73$lut$lut.bit.in.0","d_0_am__U72$lut$lut.bit.out"], + ["d_0_am__U73$lut$lut.bit.in.2","d_0_am__U73$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U73$lut$lut.bit.in.1"], + ["d_0_am__U74$lut$lut.bit.in.0","d_0_am__U73$lut$lut.bit.out"], + ["d_0_am__U74$lut$lut.bit.in.2","d_0_am__U74$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U74$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U74$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8037,25 +8401,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U568$lut$lut.bit.in.2","d_1_am__U568$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U568$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U568$lut$lut.bit.in.1"], - ["d_1_am__U569$lut$lut.bit.in.0","d_1_am__U568$lut$lut.bit.out"], - ["d_1_am__U569$lut$lut.bit.in.2","d_1_am__U569$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U569$lut$lut.bit.in.1"], - ["d_1_am__U570$lut$lut.bit.in.0","d_1_am__U569$lut$lut.bit.out"], - ["d_1_am__U570$lut$lut.bit.in.2","d_1_am__U570$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U570$lut$lut.bit.in.1"], - ["d_1_am__U571$lut$lut.bit.in.0","d_1_am__U570$lut$lut.bit.out"], - ["d_1_am__U571$lut$lut.bit.in.2","d_1_am__U571$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U571$lut$lut.bit.in.1"], - ["d_1_am__U572$lut$lut.bit.in.0","d_1_am__U571$lut$lut.bit.out"], - ["d_1_am__U572$lut$lut.bit.in.2","d_1_am__U572$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U572$lut$lut.bit.in.1"], - ["d_1_am__U573$lut$lut.bit.in.0","d_1_am__U572$lut$lut.bit.out"], - ["d_1_am__U573$lut$lut.bit.in.2","d_1_am__U573$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U573$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U573$lut$lut.bit.out"], + ["d_1_am__U75$lut$lut.bit.in.2","d_1_am__U75$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U75$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U75$lut$lut.bit.in.1"], + ["d_1_am__U76$lut$lut.bit.in.0","d_1_am__U75$lut$lut.bit.out"], + ["d_1_am__U76$lut$lut.bit.in.2","d_1_am__U76$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U76$lut$lut.bit.in.1"], + ["d_1_am__U77$lut$lut.bit.in.0","d_1_am__U76$lut$lut.bit.out"], + ["d_1_am__U77$lut$lut.bit.in.2","d_1_am__U77$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U77$lut$lut.bit.in.1"], + ["d_1_am__U78$lut$lut.bit.in.0","d_1_am__U77$lut$lut.bit.out"], + ["d_1_am__U78$lut$lut.bit.in.2","d_1_am__U78$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U78$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U78$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -8072,22 +8430,16 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U574$lut$lut.bit.in.2","d_2_am__U574$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U574$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U574$lut$lut.bit.in.1"], - ["d_2_am__U575$lut$lut.bit.in.0","d_2_am__U574$lut$lut.bit.out"], - ["d_2_am__U575$lut$lut.bit.in.2","d_2_am__U575$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U575$lut$lut.bit.in.1"], - ["d_2_am__U576$lut$lut.bit.in.0","d_2_am__U575$lut$lut.bit.out"], - ["d_2_am__U576$lut$lut.bit.in.2","d_2_am__U576$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U576$lut$lut.bit.in.1"], - ["d_2_am__U577$lut$lut.bit.in.0","d_2_am__U576$lut$lut.bit.out"], - ["d_2_am__U577$lut$lut.bit.in.2","d_2_am__U577$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U577$lut$lut.bit.in.1"], - ["d_2_am__U578$lut$lut.bit.in.0","d_2_am__U577$lut$lut.bit.out"], - ["d_2_am__U578$lut$lut.bit.in.2","d_2_am__U578$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U578$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U578$lut$lut.bit.out"], + ["d_2_am__U79$lut$lut.bit.in.2","d_2_am__U79$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U79$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U79$lut$lut.bit.in.1"], + ["d_2_am__U80$lut$lut.bit.in.0","d_2_am__U79$lut$lut.bit.out"], + ["d_2_am__U80$lut$lut.bit.in.2","d_2_am__U80$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U80$lut$lut.bit.in.1"], + ["d_2_am__U81$lut$lut.bit.in.0","d_2_am__U80$lut$lut.bit.out"], + ["d_2_am__U81$lut$lut.bit.in.2","d_2_am__U81$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U81$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U81$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -8104,19 +8456,13 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U579$lut$lut.bit.in.2","d_3_am__U579$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U579$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U579$lut$lut.bit.in.1"], - ["d_3_am__U580$lut$lut.bit.in.0","d_3_am__U579$lut$lut.bit.out"], - ["d_3_am__U580$lut$lut.bit.in.2","d_3_am__U580$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U580$lut$lut.bit.in.1"], - ["d_3_am__U581$lut$lut.bit.in.0","d_3_am__U580$lut$lut.bit.out"], - ["d_3_am__U581$lut$lut.bit.in.2","d_3_am__U581$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U581$lut$lut.bit.in.1"], - ["d_3_am__U582$lut$lut.bit.in.0","d_3_am__U581$lut$lut.bit.out"], - ["d_3_am__U582$lut$lut.bit.in.2","d_3_am__U582$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U582$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U582$lut$lut.bit.out"], + ["d_3_am__U82$lut$lut.bit.in.2","d_3_am__U82$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U82$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U82$lut$lut.bit.in.1"], + ["d_3_am__U83$lut$lut.bit.in.0","d_3_am__U82$lut$lut.bit.out"], + ["d_3_am__U83$lut$lut.bit.in.2","d_3_am__U83$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U83$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U83$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -8133,16 +8479,10 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U583$lut$lut.bit.in.2","d_4_am__U583$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U583$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U583$lut$lut.bit.in.1"], - ["d_4_am__U584$lut$lut.bit.in.0","d_4_am__U583$lut$lut.bit.out"], - ["d_4_am__U584$lut$lut.bit.in.2","d_4_am__U584$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U584$lut$lut.bit.in.1"], - ["d_4_am__U585$lut$lut.bit.in.0","d_4_am__U584$lut$lut.bit.out"], - ["d_4_am__U585$lut$lut.bit.in.2","d_4_am__U585$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U585$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U585$lut$lut.bit.out"], + ["d_4_am__U84$lut$lut.bit.in.2","d_4_am__U84$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U84$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U84$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U84$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -8159,13 +8499,6 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U586$lut$lut.bit.in.2","d_5_am__U586$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U586$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U586$lut$lut.bit.in.1"], - ["d_5_am__U587$lut$lut.bit.in.0","d_5_am__U586$lut$lut.bit.out"], - ["d_5_am__U587$lut$lut.bit.in.2","d_5_am__U587$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U587$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U587$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -8175,53 +8508,17 @@ ["d_5_reg$reg0.out","d_5_next_value.in0"], ["d_5_next_value_at_max.out","d_5_next_value.in1"], ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["true_lutcnst.bit.out","d_5_next_value.sel"], ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], ["self.rst_n","d_5_reg$clrMux.sel"], ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U588$lut$lut.bit.in.2","d_6_am__U588$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U588$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U588$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U588$lut$lut.bit.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"], - ["d_7_reg$reg0.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg$reg0.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg$reg0.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg$enMux.in1","d_7_next_value.out"], - ["true_lutcnst.bit.out","d_7_next_value.sel"], - ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], - ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], - ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], - ["self.rst_n","d_7_reg$clrMux.sel"], - ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], - ["self.clk","d_7_reg$reg0.clk"], - ["self.d.7","d_7_reg$reg0.out"] + ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U550":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -8229,121 +8526,121 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U77":{ + "_U571":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U771":{ + "_U5711":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U772":{ + "_U5712":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U773":{ + "_U5713":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U774":{ + "_U5714":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U775":{ + "_U5715":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U78":{ + "_U572":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U71":{ + "affine_func$add_all__U565":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U72":{ + "affine_func$add_all__U566":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U73":{ + "affine_func$add_all__U567":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U74":{ + "affine_func$add_all__U568":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U75":{ + "affine_func$add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U76":{ + "affine_func$add_all__U570":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U58":{ + "affine_func$coeff_0_U552":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U60":{ + "affine_func$coeff_1_U554":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} }, - "affine_func$coeff_2_U62":{ + "affine_func$coeff_2_U556":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000007e0"]} + "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "affine_func$coeff_3_U64":{ + "affine_func$coeff_3_U558":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "affine_func$coeff_4_U66":{ + "affine_func$coeff_4_U560":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000004"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_5_U68":{ + "affine_func$coeff_5_U562":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U70":{ + "affine_func$const_term_U564":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000023ff"]} + "modargs":{"value":[["BitVector",32],"32'h00003840"]} }, - "affine_func$mul_d0__U59":{ + "affine_func$mul_d0__U553":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U61":{ + "affine_func$mul_d1__U555":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U63":{ + "affine_func$mul_d2__U557":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U65":{ + "affine_func$mul_d3__U559":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U67":{ + "affine_func$mul_d4__U561":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U69":{ + "affine_func$mul_d5__U563":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -8407,52 +8704,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U79$c0_lutcnst":{ + "d_0_am__U573$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U79$lut$lut":{ + "d_0_am__U573$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U80$c0_lutcnst":{ + "d_0_am__U574$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U80$lut$lut":{ + "d_0_am__U574$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U81$c0_lutcnst":{ + "d_0_am__U575$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U81$lut$lut":{ + "d_0_am__U575$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U82$c0_lutcnst":{ + "d_0_am__U576$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U82$lut$lut":{ + "d_0_am__U576$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U83$c0_lutcnst":{ + "d_0_am__U577$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U83$lut$lut":{ + "d_0_am__U577$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8501,42 +8798,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U84$c0_lutcnst":{ + "d_1_am__U578$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U84$lut$lut":{ + "d_1_am__U578$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U85$c0_lutcnst":{ + "d_1_am__U579$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U85$lut$lut":{ + "d_1_am__U579$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U86$c0_lutcnst":{ + "d_1_am__U580$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U86$lut$lut":{ + "d_1_am__U580$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U87$c0_lutcnst":{ + "d_1_am__U581$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U87$lut$lut":{ + "d_1_am__U581$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8585,32 +8882,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U88$c0_lutcnst":{ + "d_2_am__U582$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U88$lut$lut":{ + "d_2_am__U582$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U89$c0_lutcnst":{ + "d_2_am__U583$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U89$lut$lut":{ + "d_2_am__U583$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U90$c0_lutcnst":{ + "d_2_am__U584$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U90$lut$lut":{ + "d_2_am__U584$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8626,7 +8923,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_2_min":{ "genref":"coreir.const", @@ -8659,22 +8956,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U91$c0_lutcnst":{ + "d_3_am__U585$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U91$lut$lut":{ + "d_3_am__U585$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U92$c0_lutcnst":{ + "d_3_am__U586$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U92$lut$lut":{ + "d_3_am__U586$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8690,7 +8987,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_3_min":{ "genref":"coreir.const", @@ -8723,12 +9020,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U93$c0_lutcnst":{ + "d_4_am__U587$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U93$lut$lut":{ + "d_4_am__U587$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8744,7 +9041,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, "d_4_min":{ "genref":"coreir.const", @@ -8788,7 +9085,7 @@ "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, "d_5_min":{ "genref":"coreir.const", @@ -8867,38 +9164,38 @@ } }, "connections":[ - ["d_0_inc.in1","_U77.out"], - ["d_1_inc.in1","_U771.out"], - ["d_2_inc.in1","_U772.out"], - ["d_3_inc.in1","_U773.out"], - ["d_4_inc.in1","_U774.out"], - ["d_5_inc.in1","_U775.out"], - ["cmp_time.in1","_U78.out"], - ["affine_func$mul_d0__U59.out","affine_func$add_all__U71.in0"], - ["affine_func$mul_d1__U61.out","affine_func$add_all__U71.in1"], - ["affine_func$add_all__U72.in0","affine_func$add_all__U71.out"], - ["affine_func$mul_d2__U63.out","affine_func$add_all__U72.in1"], - ["affine_func$add_all__U73.in0","affine_func$add_all__U72.out"], - ["affine_func$mul_d3__U65.out","affine_func$add_all__U73.in1"], - ["affine_func$add_all__U74.in0","affine_func$add_all__U73.out"], - ["affine_func$mul_d4__U67.out","affine_func$add_all__U74.in1"], - ["affine_func$add_all__U75.in0","affine_func$add_all__U74.out"], - ["affine_func$mul_d5__U69.out","affine_func$add_all__U75.in1"], - ["affine_func$add_all__U76.in0","affine_func$add_all__U75.out"], - ["affine_func$const_term_U70.out","affine_func$add_all__U76.in1"], - ["time_diff.in0","affine_func$add_all__U76.out"], - ["affine_func$mul_d0__U59.in0","affine_func$coeff_0_U58.out"], - ["affine_func$mul_d1__U61.in0","affine_func$coeff_1_U60.out"], - ["affine_func$mul_d2__U63.in0","affine_func$coeff_2_U62.out"], - ["affine_func$mul_d3__U65.in0","affine_func$coeff_3_U64.out"], - ["affine_func$mul_d4__U67.in0","affine_func$coeff_4_U66.out"], - ["affine_func$mul_d5__U69.in0","affine_func$coeff_5_U68.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U59.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U61.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U63.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U65.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U67.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U69.in1"], + ["d_0_inc.in1","_U571.out"], + ["d_1_inc.in1","_U5711.out"], + ["d_2_inc.in1","_U5712.out"], + ["d_3_inc.in1","_U5713.out"], + ["d_4_inc.in1","_U5714.out"], + ["d_5_inc.in1","_U5715.out"], + ["cmp_time.in1","_U572.out"], + ["affine_func$mul_d0__U553.out","affine_func$add_all__U565.in0"], + ["affine_func$mul_d1__U555.out","affine_func$add_all__U565.in1"], + ["affine_func$add_all__U566.in0","affine_func$add_all__U565.out"], + ["affine_func$mul_d2__U557.out","affine_func$add_all__U566.in1"], + ["affine_func$add_all__U567.in0","affine_func$add_all__U566.out"], + ["affine_func$mul_d3__U559.out","affine_func$add_all__U567.in1"], + ["affine_func$add_all__U568.in0","affine_func$add_all__U567.out"], + ["affine_func$mul_d4__U561.out","affine_func$add_all__U568.in1"], + ["affine_func$add_all__U569.in0","affine_func$add_all__U568.out"], + ["affine_func$mul_d5__U563.out","affine_func$add_all__U569.in1"], + ["affine_func$add_all__U570.in0","affine_func$add_all__U569.out"], + ["affine_func$const_term_U564.out","affine_func$add_all__U570.in1"], + ["time_diff.in0","affine_func$add_all__U570.out"], + ["affine_func$mul_d0__U553.in0","affine_func$coeff_0_U552.out"], + ["affine_func$mul_d1__U555.in0","affine_func$coeff_1_U554.out"], + ["affine_func$mul_d2__U557.in0","affine_func$coeff_2_U556.out"], + ["affine_func$mul_d3__U559.in0","affine_func$coeff_3_U558.out"], + ["affine_func$mul_d4__U561.in0","affine_func$coeff_4_U560.out"], + ["affine_func$mul_d5__U563.in0","affine_func$coeff_5_U562.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U553.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U555.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U557.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U559.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U561.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U563.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -8925,22 +9222,22 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U79$lut$lut.bit.in.2","d_0_am__U79$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U79$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U79$lut$lut.bit.in.1"], - ["d_0_am__U80$lut$lut.bit.in.0","d_0_am__U79$lut$lut.bit.out"], - ["d_0_am__U80$lut$lut.bit.in.2","d_0_am__U80$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U80$lut$lut.bit.in.1"], - ["d_0_am__U81$lut$lut.bit.in.0","d_0_am__U80$lut$lut.bit.out"], - ["d_0_am__U81$lut$lut.bit.in.2","d_0_am__U81$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U81$lut$lut.bit.in.1"], - ["d_0_am__U82$lut$lut.bit.in.0","d_0_am__U81$lut$lut.bit.out"], - ["d_0_am__U82$lut$lut.bit.in.2","d_0_am__U82$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U82$lut$lut.bit.in.1"], - ["d_0_am__U83$lut$lut.bit.in.0","d_0_am__U82$lut$lut.bit.out"], - ["d_0_am__U83$lut$lut.bit.in.2","d_0_am__U83$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U83$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U83$lut$lut.bit.out"], + ["d_0_am__U573$lut$lut.bit.in.2","d_0_am__U573$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U573$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U573$lut$lut.bit.in.1"], + ["d_0_am__U574$lut$lut.bit.in.0","d_0_am__U573$lut$lut.bit.out"], + ["d_0_am__U574$lut$lut.bit.in.2","d_0_am__U574$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U574$lut$lut.bit.in.1"], + ["d_0_am__U575$lut$lut.bit.in.0","d_0_am__U574$lut$lut.bit.out"], + ["d_0_am__U575$lut$lut.bit.in.2","d_0_am__U575$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U575$lut$lut.bit.in.1"], + ["d_0_am__U576$lut$lut.bit.in.0","d_0_am__U575$lut$lut.bit.out"], + ["d_0_am__U576$lut$lut.bit.in.2","d_0_am__U576$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U576$lut$lut.bit.in.1"], + ["d_0_am__U577$lut$lut.bit.in.0","d_0_am__U576$lut$lut.bit.out"], + ["d_0_am__U577$lut$lut.bit.in.2","d_0_am__U577$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U577$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U577$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8957,19 +9254,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U84$lut$lut.bit.in.2","d_1_am__U84$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U84$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U84$lut$lut.bit.in.1"], - ["d_1_am__U85$lut$lut.bit.in.0","d_1_am__U84$lut$lut.bit.out"], - ["d_1_am__U85$lut$lut.bit.in.2","d_1_am__U85$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U85$lut$lut.bit.in.1"], - ["d_1_am__U86$lut$lut.bit.in.0","d_1_am__U85$lut$lut.bit.out"], - ["d_1_am__U86$lut$lut.bit.in.2","d_1_am__U86$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U86$lut$lut.bit.in.1"], - ["d_1_am__U87$lut$lut.bit.in.0","d_1_am__U86$lut$lut.bit.out"], - ["d_1_am__U87$lut$lut.bit.in.2","d_1_am__U87$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U87$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U87$lut$lut.bit.out"], + ["d_1_am__U578$lut$lut.bit.in.2","d_1_am__U578$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U578$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U578$lut$lut.bit.in.1"], + ["d_1_am__U579$lut$lut.bit.in.0","d_1_am__U578$lut$lut.bit.out"], + ["d_1_am__U579$lut$lut.bit.in.2","d_1_am__U579$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U579$lut$lut.bit.in.1"], + ["d_1_am__U580$lut$lut.bit.in.0","d_1_am__U579$lut$lut.bit.out"], + ["d_1_am__U580$lut$lut.bit.in.2","d_1_am__U580$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U580$lut$lut.bit.in.1"], + ["d_1_am__U581$lut$lut.bit.in.0","d_1_am__U580$lut$lut.bit.out"], + ["d_1_am__U581$lut$lut.bit.in.2","d_1_am__U581$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U581$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U581$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -8986,16 +9283,16 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U88$lut$lut.bit.in.2","d_2_am__U88$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U88$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U88$lut$lut.bit.in.1"], - ["d_2_am__U89$lut$lut.bit.in.0","d_2_am__U88$lut$lut.bit.out"], - ["d_2_am__U89$lut$lut.bit.in.2","d_2_am__U89$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U89$lut$lut.bit.in.1"], - ["d_2_am__U90$lut$lut.bit.in.0","d_2_am__U89$lut$lut.bit.out"], - ["d_2_am__U90$lut$lut.bit.in.2","d_2_am__U90$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U90$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U90$lut$lut.bit.out"], + ["d_2_am__U582$lut$lut.bit.in.2","d_2_am__U582$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U582$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U582$lut$lut.bit.in.1"], + ["d_2_am__U583$lut$lut.bit.in.0","d_2_am__U582$lut$lut.bit.out"], + ["d_2_am__U583$lut$lut.bit.in.2","d_2_am__U583$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U583$lut$lut.bit.in.1"], + ["d_2_am__U584$lut$lut.bit.in.0","d_2_am__U583$lut$lut.bit.out"], + ["d_2_am__U584$lut$lut.bit.in.2","d_2_am__U584$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U584$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U584$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -9012,13 +9309,13 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U91$lut$lut.bit.in.2","d_3_am__U91$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U91$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U91$lut$lut.bit.in.1"], - ["d_3_am__U92$lut$lut.bit.in.0","d_3_am__U91$lut$lut.bit.out"], - ["d_3_am__U92$lut$lut.bit.in.2","d_3_am__U92$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U92$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U92$lut$lut.bit.out"], + ["d_3_am__U585$lut$lut.bit.in.2","d_3_am__U585$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U585$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U585$lut$lut.bit.in.1"], + ["d_3_am__U586$lut$lut.bit.in.0","d_3_am__U585$lut$lut.bit.out"], + ["d_3_am__U586$lut$lut.bit.in.2","d_3_am__U586$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U586$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U586$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -9035,10 +9332,10 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U93$lut$lut.bit.in.2","d_4_am__U93$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U93$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U93$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U93$lut$lut.bit.out"], + ["d_4_am__U587$lut$lut.bit.in.2","d_4_am__U587$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U587$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U587$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U587$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -9074,129 +9371,93 @@ ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U635":{ + "affine_controller__U610":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",6,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U656":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U6561":{ + "_U625":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6562":{ + "_U6251":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6563":{ + "_U6252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6564":{ + "_U6253":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6565":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U657":{ + "_U626":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U650":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U651":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U652":{ + "affine_func$add_all__U621":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U653":{ + "affine_func$add_all__U622":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U654":{ + "affine_func$add_all__U623":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U655":{ + "affine_func$add_all__U624":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U637":{ + "affine_func$coeff_0_U612":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U639":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000fc0"]} - }, - "affine_func$coeff_2_U641":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000000e0"]} - }, - "affine_func$coeff_3_U643":{ + "affine_func$coeff_1_U614":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000020"]} + "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "affine_func$coeff_4_U645":{ + "affine_func$coeff_2_U616":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "affine_func$coeff_5_U647":{ + "affine_func$coeff_3_U618":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U649":{ + "affine_func$const_term_U620":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003840"]} - }, - "affine_func$mul_d0__U638":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U640":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00004e1f"]} }, - "affine_func$mul_d2__U642":{ + "affine_func$mul_d0__U613":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U644":{ + "affine_func$mul_d1__U615":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U646":{ + "affine_func$mul_d2__U617":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U648":{ + "affine_func$mul_d3__U619":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -9260,52 +9521,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U658$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U658$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U659$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U659$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U660$c0_lutcnst":{ + "d_0_am__U627$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U660$lut$lut":{ + "d_0_am__U627$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U661$c0_lutcnst":{ + "d_0_am__U628$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U661$lut$lut":{ + "d_0_am__U628$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U662$c0_lutcnst":{ + "d_0_am__U629$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U662$lut$lut":{ + "d_0_am__U629$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9354,42 +9595,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U663$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U663$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U664$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U664$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U665$c0_lutcnst":{ + "d_1_am__U630$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U665$lut$lut":{ + "d_1_am__U630$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U666$c0_lutcnst":{ + "d_1_am__U631$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U666$lut$lut":{ + "d_1_am__U631$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9405,7 +9626,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_1_min":{ "genref":"coreir.const", @@ -9438,32 +9659,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U667$c0_lutcnst":{ + "d_2_am__U632$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U667$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U668$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U668$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U669$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U669$lut$lut":{ + "d_2_am__U632$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9499,177 +9700,59 @@ "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U670$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U670$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U671$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U671$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_am__U672$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U672$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, - "d_5_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -9703,16 +9786,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9720,45 +9793,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U656.out"], - ["d_1_inc.in1","_U6561.out"], - ["d_2_inc.in1","_U6562.out"], - ["d_3_inc.in1","_U6563.out"], - ["d_4_inc.in1","_U6564.out"], - ["d_5_inc.in1","_U6565.out"], - ["cmp_time.in1","_U657.out"], - ["affine_func$mul_d0__U638.out","affine_func$add_all__U650.in0"], - ["affine_func$mul_d1__U640.out","affine_func$add_all__U650.in1"], - ["affine_func$add_all__U651.in0","affine_func$add_all__U650.out"], - ["affine_func$mul_d2__U642.out","affine_func$add_all__U651.in1"], - ["affine_func$add_all__U652.in0","affine_func$add_all__U651.out"], - ["affine_func$mul_d3__U644.out","affine_func$add_all__U652.in1"], - ["affine_func$add_all__U653.in0","affine_func$add_all__U652.out"], - ["affine_func$mul_d4__U646.out","affine_func$add_all__U653.in1"], - ["affine_func$add_all__U654.in0","affine_func$add_all__U653.out"], - ["affine_func$mul_d5__U648.out","affine_func$add_all__U654.in1"], - ["affine_func$add_all__U655.in0","affine_func$add_all__U654.out"], - ["affine_func$const_term_U649.out","affine_func$add_all__U655.in1"], - ["time_diff.in0","affine_func$add_all__U655.out"], - ["affine_func$mul_d0__U638.in0","affine_func$coeff_0_U637.out"], - ["affine_func$mul_d1__U640.in0","affine_func$coeff_1_U639.out"], - ["affine_func$mul_d2__U642.in0","affine_func$coeff_2_U641.out"], - ["affine_func$mul_d3__U644.in0","affine_func$coeff_3_U643.out"], - ["affine_func$mul_d4__U646.in0","affine_func$coeff_4_U645.out"], - ["affine_func$mul_d5__U648.in0","affine_func$coeff_5_U647.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U638.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U640.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U642.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U644.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U646.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U648.in1"], + ["d_0_inc.in1","_U625.out"], + ["d_1_inc.in1","_U6251.out"], + ["d_2_inc.in1","_U6252.out"], + ["d_3_inc.in1","_U6253.out"], + ["cmp_time.in1","_U626.out"], + ["affine_func$mul_d0__U613.out","affine_func$add_all__U621.in0"], + ["affine_func$mul_d1__U615.out","affine_func$add_all__U621.in1"], + ["affine_func$add_all__U622.in0","affine_func$add_all__U621.out"], + ["affine_func$mul_d2__U617.out","affine_func$add_all__U622.in1"], + ["affine_func$add_all__U623.in0","affine_func$add_all__U622.out"], + ["affine_func$mul_d3__U619.out","affine_func$add_all__U623.in1"], + ["affine_func$add_all__U624.in0","affine_func$add_all__U623.out"], + ["affine_func$const_term_U620.out","affine_func$add_all__U624.in1"], + ["time_diff.in0","affine_func$add_all__U624.out"], + ["affine_func$mul_d0__U613.in0","affine_func$coeff_0_U612.out"], + ["affine_func$mul_d1__U615.in0","affine_func$coeff_1_U614.out"], + ["affine_func$mul_d2__U617.in0","affine_func$coeff_2_U616.out"], + ["affine_func$mul_d3__U619.in0","affine_func$coeff_3_U618.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U613.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U615.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U617.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U619.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -9766,34 +9827,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U658$lut$lut.bit.in.2","d_0_am__U658$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U658$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U658$lut$lut.bit.in.1"], - ["d_0_am__U659$lut$lut.bit.in.0","d_0_am__U658$lut$lut.bit.out"], - ["d_0_am__U659$lut$lut.bit.in.2","d_0_am__U659$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U659$lut$lut.bit.in.1"], - ["d_0_am__U660$lut$lut.bit.in.0","d_0_am__U659$lut$lut.bit.out"], - ["d_0_am__U660$lut$lut.bit.in.2","d_0_am__U660$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U660$lut$lut.bit.in.1"], - ["d_0_am__U661$lut$lut.bit.in.0","d_0_am__U660$lut$lut.bit.out"], - ["d_0_am__U661$lut$lut.bit.in.2","d_0_am__U661$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U661$lut$lut.bit.in.1"], - ["d_0_am__U662$lut$lut.bit.in.0","d_0_am__U661$lut$lut.bit.out"], - ["d_0_am__U662$lut$lut.bit.in.2","d_0_am__U662$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U662$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U662$lut$lut.bit.out"], + ["d_0_am__U627$lut$lut.bit.in.2","d_0_am__U627$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U627$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U627$lut$lut.bit.in.1"], + ["d_0_am__U628$lut$lut.bit.in.0","d_0_am__U627$lut$lut.bit.out"], + ["d_0_am__U628$lut$lut.bit.in.2","d_0_am__U628$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U628$lut$lut.bit.in.1"], + ["d_0_am__U629$lut$lut.bit.in.0","d_0_am__U628$lut$lut.bit.out"], + ["d_0_am__U629$lut$lut.bit.in.2","d_0_am__U629$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U629$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U629$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9810,19 +9865,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U663$lut$lut.bit.in.2","d_1_am__U663$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U663$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U663$lut$lut.bit.in.1"], - ["d_1_am__U664$lut$lut.bit.in.0","d_1_am__U663$lut$lut.bit.out"], - ["d_1_am__U664$lut$lut.bit.in.2","d_1_am__U664$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U664$lut$lut.bit.in.1"], - ["d_1_am__U665$lut$lut.bit.in.0","d_1_am__U664$lut$lut.bit.out"], - ["d_1_am__U665$lut$lut.bit.in.2","d_1_am__U665$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U665$lut$lut.bit.in.1"], - ["d_1_am__U666$lut$lut.bit.in.0","d_1_am__U665$lut$lut.bit.out"], - ["d_1_am__U666$lut$lut.bit.in.2","d_1_am__U666$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U666$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U666$lut$lut.bit.out"], + ["d_1_am__U630$lut$lut.bit.in.2","d_1_am__U630$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U630$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U630$lut$lut.bit.in.1"], + ["d_1_am__U631$lut$lut.bit.in.0","d_1_am__U630$lut$lut.bit.out"], + ["d_1_am__U631$lut$lut.bit.in.2","d_1_am__U631$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U631$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U631$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -9839,16 +9888,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U667$lut$lut.bit.in.2","d_2_am__U667$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U667$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U667$lut$lut.bit.in.1"], - ["d_2_am__U668$lut$lut.bit.in.0","d_2_am__U667$lut$lut.bit.out"], - ["d_2_am__U668$lut$lut.bit.in.2","d_2_am__U668$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U668$lut$lut.bit.in.1"], - ["d_2_am__U669$lut$lut.bit.in.0","d_2_am__U668$lut$lut.bit.out"], - ["d_2_am__U669$lut$lut.bit.in.2","d_2_am__U669$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U669$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U669$lut$lut.bit.out"], + ["d_2_am__U632$lut$lut.bit.in.2","d_2_am__U632$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U632$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U632$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U632$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -9865,13 +9908,6 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U670$lut$lut.bit.in.2","d_3_am__U670$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U670$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U670$lut$lut.bit.in.1"], - ["d_3_am__U671$lut$lut.bit.in.0","d_3_am__U670$lut$lut.bit.out"], - ["d_3_am__U671$lut$lut.bit.in.2","d_3_am__U671$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U671$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U671$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -9881,53 +9917,17 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U672$lut$lut.bit.in.2","d_4_am__U672$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U672$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U672$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U672$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["true_lutcnst.bit.out","d_5_next_value.sel"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U695":{ + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -9935,85 +9935,85 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U710":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7101":{ + "_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7102":{ + "_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7103":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U711":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U706":{ + "affine_func$add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U707":{ + "affine_func$add_all__U20":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U708":{ + "affine_func$add_all__U21":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U709":{ + "affine_func$add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U697":{ + "affine_func$coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U699":{ + "affine_func$coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000001c0"]} + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "affine_func$coeff_2_U701":{ + "affine_func$coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U703":{ + "affine_func$coeff_3_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "affine_func$const_term_U705":{ + "affine_func$const_term_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00004e1f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U698":{ + "affine_func$mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U700":{ + "affine_func$mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U702":{ + "affine_func$mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U704":{ + "affine_func$mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -10077,32 +10077,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U712$c0_lutcnst":{ + "d_0_am__U25$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U712$lut$lut":{ + "d_0_am__U25$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U713$c0_lutcnst":{ + "d_0_am__U26$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U713$lut$lut":{ + "d_0_am__U26$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U714$c0_lutcnst":{ + "d_0_am__U27$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U714$lut$lut":{ + "d_0_am__U27$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10151,22 +10151,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U715$c0_lutcnst":{ + "d_1_am__U28$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U715$lut$lut":{ + "d_1_am__U28$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U716$c0_lutcnst":{ + "d_1_am__U29$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U716$lut$lut":{ + "d_1_am__U29$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10182,7 +10182,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_1_min":{ "genref":"coreir.const", @@ -10215,12 +10215,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U717$c0_lutcnst":{ + "d_2_am__U30$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U717$lut$lut":{ + "d_2_am__U30$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10236,7 +10236,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, "d_2_min":{ "genref":"coreir.const", @@ -10280,7 +10280,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, "d_3_min":{ "genref":"coreir.const", @@ -10349,28 +10349,28 @@ } }, "connections":[ - ["d_0_inc.in1","_U710.out"], - ["d_1_inc.in1","_U7101.out"], - ["d_2_inc.in1","_U7102.out"], - ["d_3_inc.in1","_U7103.out"], - ["cmp_time.in1","_U711.out"], - ["affine_func$mul_d0__U698.out","affine_func$add_all__U706.in0"], - ["affine_func$mul_d1__U700.out","affine_func$add_all__U706.in1"], - ["affine_func$add_all__U707.in0","affine_func$add_all__U706.out"], - ["affine_func$mul_d2__U702.out","affine_func$add_all__U707.in1"], - ["affine_func$add_all__U708.in0","affine_func$add_all__U707.out"], - ["affine_func$mul_d3__U704.out","affine_func$add_all__U708.in1"], - ["affine_func$add_all__U709.in0","affine_func$add_all__U708.out"], - ["affine_func$const_term_U705.out","affine_func$add_all__U709.in1"], - ["time_diff.in0","affine_func$add_all__U709.out"], - ["affine_func$mul_d0__U698.in0","affine_func$coeff_0_U697.out"], - ["affine_func$mul_d1__U700.in0","affine_func$coeff_1_U699.out"], - ["affine_func$mul_d2__U702.in0","affine_func$coeff_2_U701.out"], - ["affine_func$mul_d3__U704.in0","affine_func$coeff_3_U703.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U698.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U700.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U702.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U704.in1"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U231.out"], + ["d_2_inc.in1","_U232.out"], + ["d_3_inc.in1","_U233.out"], + ["cmp_time.in1","_U24.out"], + ["affine_func$mul_d0__U11.out","affine_func$add_all__U19.in0"], + ["affine_func$mul_d1__U13.out","affine_func$add_all__U19.in1"], + ["affine_func$add_all__U20.in0","affine_func$add_all__U19.out"], + ["affine_func$mul_d2__U15.out","affine_func$add_all__U20.in1"], + ["affine_func$add_all__U21.in0","affine_func$add_all__U20.out"], + ["affine_func$mul_d3__U17.out","affine_func$add_all__U21.in1"], + ["affine_func$add_all__U22.in0","affine_func$add_all__U21.out"], + ["affine_func$const_term_U18.out","affine_func$add_all__U22.in1"], + ["time_diff.in0","affine_func$add_all__U22.out"], + ["affine_func$mul_d0__U11.in0","affine_func$coeff_0_U10.out"], + ["affine_func$mul_d1__U13.in0","affine_func$coeff_1_U12.out"], + ["affine_func$mul_d2__U15.in0","affine_func$coeff_2_U14.out"], + ["affine_func$mul_d3__U17.in0","affine_func$coeff_3_U16.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U11.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U13.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U15.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U17.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -10395,16 +10395,16 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U712$lut$lut.bit.in.2","d_0_am__U712$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U712$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U712$lut$lut.bit.in.1"], - ["d_0_am__U713$lut$lut.bit.in.0","d_0_am__U712$lut$lut.bit.out"], - ["d_0_am__U713$lut$lut.bit.in.2","d_0_am__U713$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U713$lut$lut.bit.in.1"], - ["d_0_am__U714$lut$lut.bit.in.0","d_0_am__U713$lut$lut.bit.out"], - ["d_0_am__U714$lut$lut.bit.in.2","d_0_am__U714$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U714$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U714$lut$lut.bit.out"], + ["d_0_am__U25$lut$lut.bit.in.2","d_0_am__U25$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U25$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U25$lut$lut.bit.in.1"], + ["d_0_am__U26$lut$lut.bit.in.0","d_0_am__U25$lut$lut.bit.out"], + ["d_0_am__U26$lut$lut.bit.in.2","d_0_am__U26$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U26$lut$lut.bit.in.1"], + ["d_0_am__U27$lut$lut.bit.in.0","d_0_am__U26$lut$lut.bit.out"], + ["d_0_am__U27$lut$lut.bit.in.2","d_0_am__U27$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U27$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U27$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10421,13 +10421,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U715$lut$lut.bit.in.2","d_1_am__U715$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U715$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U715$lut$lut.bit.in.1"], - ["d_1_am__U716$lut$lut.bit.in.0","d_1_am__U715$lut$lut.bit.out"], - ["d_1_am__U716$lut$lut.bit.in.2","d_1_am__U716$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U716$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U716$lut$lut.bit.out"], + ["d_1_am__U28$lut$lut.bit.in.2","d_1_am__U28$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U28$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U28$lut$lut.bit.in.1"], + ["d_1_am__U29$lut$lut.bit.in.0","d_1_am__U28$lut$lut.bit.out"], + ["d_1_am__U29$lut$lut.bit.in.2","d_1_am__U29$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U29$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U29$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10444,10 +10444,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U717$lut$lut.bit.in.2","d_2_am__U717$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U717$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U717$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U717$lut$lut.bit.out"], + ["d_2_am__U30$lut$lut.bit.in.2","d_2_am__U30$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U30$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U30$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U30$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -10582,26 +10582,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U751":{ + "PE_init_U666":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U749":{ + "_U664":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U750":{ + "_U665":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U749.out","PE_init_U751.data.in.0"], - ["_U750.out","PE_init_U751.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U751.data.out"], + ["_U664.out","PE_init_U666.data.in.0"], + ["_U665.out","PE_init_U666.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U666.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -10613,26 +10613,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U754":{ + "PE_init_U669":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U752":{ + "_U667":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U753":{ + "_U668":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U752.out","PE_init_U754.data.in.0"], - ["_U753.out","PE_init_U754.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U754.data.out"], + ["_U667.out","PE_init_U669.data.in.0"], + ["_U668.out","PE_init_U669.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U669.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11418,26 +11418,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U757":{ + "PE_init_U672":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U755":{ + "_U670":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U756":{ + "_U671":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U755.out","PE_init_U757.data.in.0"], - ["_U756.out","PE_init_U757.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U757.data.out"], + ["_U670.out","PE_init_U672.data.in.0"], + ["_U671.out","PE_init_U672.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U672.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11449,26 +11449,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U760":{ + "PE_init_U675":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U758":{ + "_U673":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U759":{ + "_U674":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U758.out","PE_init_U760.data.in.0"], - ["_U759.out","PE_init_U760.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U760.data.out"], + ["_U673.out","PE_init_U675.data.in.0"], + ["_U674.out","PE_init_U675.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U675.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11480,26 +11480,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U763":{ + "PE_init_U678":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U761":{ + "_U676":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U762":{ + "_U677":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U761.out","PE_init_U763.data.in.0"], - ["_U762.out","PE_init_U763.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U763.data.out"], + ["_U676.out","PE_init_U678.data.in.0"], + ["_U677.out","PE_init_U678.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U678.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11511,26 +11511,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U766":{ + "PE_init_U681":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U764":{ + "_U679":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U765":{ + "_U680":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U764.out","PE_init_U766.data.in.0"], - ["_U765.out","PE_init_U766.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U766.data.out"], + ["_U679.out","PE_init_U681.data.in.0"], + ["_U680.out","PE_init_U681.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U681.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11542,26 +11542,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U769":{ + "PE_init_U684":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U767":{ + "_U682":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U768":{ + "_U683":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U767.out","PE_init_U769.data.in.0"], - ["_U768.out","PE_init_U769.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U769.data.out"], + ["_U682.out","PE_init_U684.data.in.0"], + ["_U683.out","PE_init_U684.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U684.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11573,26 +11573,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U772":{ + "PE_init_U687":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U770":{ + "_U685":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U771":{ + "_U686":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U770.out","PE_init_U772.data.in.0"], - ["_U771.out","PE_init_U772.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U772.data.out"], + ["_U685.out","PE_init_U687.data.in.0"], + ["_U686.out","PE_init_U687.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U687.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11935,26 +11935,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U775":{ + "PE_init_U690":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U773":{ + "_U688":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U774":{ + "_U689":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U773.out","PE_init_U775.data.in.0"], - ["_U774.out","PE_init_U775.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U775.data.out"] + ["_U688.out","PE_init_U690.data.in.0"], + ["_U689.out","PE_init_U690.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U690.data.out"] ] }, "hcompute_output_cgra_stencil_1":{ @@ -11962,26 +11962,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U778":{ + "PE_init_U693":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U776":{ + "_U691":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U777":{ + "_U692":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U776.out","PE_init_U778.data.in.0"], - ["_U777.out","PE_init_U778.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U778.data.out"] + ["_U691.out","PE_init_U693.data.in.0"], + ["_U692.out","PE_init_U693.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U693.data.out"] ] }, "hcompute_output_cgra_stencil_10":{ @@ -12739,26 +12739,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U781":{ + "PE_init_U696":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U779":{ + "_U694":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U780":{ + "_U695":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U779.out","PE_init_U781.data.in.0"], - ["_U780.out","PE_init_U781.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U781.data.out"] + ["_U694.out","PE_init_U696.data.in.0"], + ["_U695.out","PE_init_U696.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U696.data.out"] ] }, "hcompute_output_cgra_stencil_3":{ @@ -12766,26 +12766,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U784":{ + "PE_init_U699":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U782":{ + "_U697":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U783":{ + "_U698":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U782.out","PE_init_U784.data.in.0"], - ["_U783.out","PE_init_U784.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U784.data.out"] + ["_U697.out","PE_init_U699.data.in.0"], + ["_U698.out","PE_init_U699.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U699.data.out"] ] }, "hcompute_output_cgra_stencil_4":{ @@ -12793,26 +12793,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U787":{ + "PE_init_U702":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U785":{ + "_U700":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U786":{ + "_U701":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U785.out","PE_init_U787.data.in.0"], - ["_U786.out","PE_init_U787.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U787.data.out"] + ["_U700.out","PE_init_U702.data.in.0"], + ["_U701.out","PE_init_U702.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U702.data.out"] ] }, "hcompute_output_cgra_stencil_5":{ @@ -12820,26 +12820,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U790":{ + "PE_init_U705":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U788":{ + "_U703":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U789":{ + "_U704":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U788.out","PE_init_U790.data.in.0"], - ["_U789.out","PE_init_U790.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U790.data.out"] + ["_U703.out","PE_init_U705.data.in.0"], + ["_U704.out","PE_init_U705.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U705.data.out"] ] }, "hcompute_output_cgra_stencil_6":{ @@ -12847,26 +12847,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U793":{ + "PE_init_U708":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U791":{ + "_U706":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U792":{ + "_U707":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U791.out","PE_init_U793.data.in.0"], - ["_U792.out","PE_init_U793.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U793.data.out"] + ["_U706.out","PE_init_U708.data.in.0"], + ["_U707.out","PE_init_U708.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U708.data.out"] ] }, "hcompute_output_cgra_stencil_7":{ @@ -12874,26 +12874,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U796":{ + "PE_init_U711":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U794":{ + "_U709":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U795":{ + "_U710":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U794.out","PE_init_U796.data.in.0"], - ["_U795.out","PE_init_U796.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U796.data.out"] + ["_U709.out","PE_init_U711.data.in.0"], + ["_U710.out","PE_init_U711.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U711.data.out"] ] }, "hcompute_output_cgra_stencil_8":{ @@ -13182,38 +13182,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -13221,7 +13189,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -13231,7 +13199,7 @@ }, "ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1149],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -13241,7 +13209,7 @@ }, "ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -13251,7 +13219,7 @@ }, "ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[16],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -13261,7 +13229,7 @@ }, "ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -13271,7 +13239,7 @@ }, "ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1149],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -13281,7 +13249,7 @@ }, "ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -13291,7 +13259,7 @@ }, "ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[16],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -13438,262 +13406,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U271":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U273":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U275":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U277":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U279":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U281":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U283":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U285":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U287":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U289":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U291":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U293":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U295":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U297":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U299":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U301":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U303":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U305":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U307":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U309":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U311":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U313":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U315":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U317":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U319":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U321":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U323":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U325":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U327":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U329":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U331":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U333":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U335":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U337":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U339":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U341":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U343":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U345":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -13701,7 +13413,7 @@ }, "ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[97],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -13711,7 +13423,7 @@ }, "ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[106],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -13721,7 +13433,7 @@ }, "ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[110],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -13731,7 +13443,7 @@ }, "ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[114],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -13741,7 +13453,7 @@ }, "ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[118],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -13751,7 +13463,7 @@ }, "ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[122],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -13761,7 +13473,7 @@ }, "ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[126],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -13771,7 +13483,7 @@ }, "ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[99],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -13781,7 +13493,7 @@ }, "ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[103],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -13791,7 +13503,7 @@ }, "ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[107],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -13801,7 +13513,7 @@ }, "ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[111],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -13811,7 +13523,7 @@ }, "ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[101],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -13821,7 +13533,7 @@ }, "ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[115],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -13831,7 +13543,7 @@ }, "ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[119],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -13841,7 +13553,7 @@ }, "ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[123],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -13851,7 +13563,7 @@ }, "ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[127],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -13861,7 +13573,7 @@ }, "ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[100],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -13871,7 +13583,7 @@ }, "ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[104],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -13881,7 +13593,7 @@ }, "ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U270"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[108],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -13891,7 +13603,7 @@ }, "ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U272"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[112],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -13901,7 +13613,7 @@ }, "ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U274"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[116],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -13911,7 +13623,7 @@ }, "ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U276"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[120],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -13921,7 +13633,7 @@ }, "ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[105],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -13931,7 +13643,7 @@ }, "ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U278"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[124],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -13941,7 +13653,7 @@ }, "ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U280"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[128],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -13951,7 +13663,7 @@ }, "ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U282"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[97],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -13961,7 +13673,7 @@ }, "ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U284"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[101],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -13971,7 +13683,7 @@ }, "ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U286"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[105],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -13981,7 +13693,7 @@ }, "ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U288"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[109],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -13991,7 +13703,7 @@ }, "ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U290"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[113],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -14001,7 +13713,7 @@ }, "ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U292"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U245"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[117],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -14011,7 +13723,7 @@ }, "ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[121],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -14021,7 +13733,7 @@ }, "ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U296"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U247"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[125],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -14031,7 +13743,7 @@ }, "ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[109],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -14041,7 +13753,7 @@ }, "ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U298"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[98],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -14051,7 +13763,7 @@ }, "ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U300"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U249"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[102],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -14061,7 +13773,7 @@ }, "ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U302"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[106],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -14071,7 +13783,7 @@ }, "ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U304"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U251"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[110],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -14081,7 +13793,7 @@ }, "ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U306"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[114],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -14091,7 +13803,7 @@ }, "ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U253"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[118],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -14101,7 +13813,7 @@ }, "ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[122],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -14111,7 +13823,7 @@ }, "ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U255"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[126],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -14121,7 +13833,7 @@ }, "ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[99],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -14131,7 +13843,7 @@ }, "ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U316"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U257"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[103],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -14141,7 +13853,7 @@ }, "ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[113],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -14151,7 +13863,7 @@ }, "ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U318"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[107],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -14161,7 +13873,7 @@ }, "ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U320"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U259"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[111],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -14171,7 +13883,7 @@ }, "ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U322"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[115],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -14181,7 +13893,7 @@ }, "ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U324"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U261"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[119],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -14191,7 +13903,7 @@ }, "ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U326"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[123],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -14201,7 +13913,7 @@ }, "ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U328"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U263"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[127],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -14211,7 +13923,7 @@ }, "ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U330"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[100],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -14221,7 +13933,7 @@ }, "ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U332"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U265"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[104],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -14231,7 +13943,7 @@ }, "ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U334"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[108],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -14241,7 +13953,7 @@ }, "ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U336"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U267"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[112],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -14251,7 +13963,7 @@ }, "ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[117],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -14261,7 +13973,7 @@ }, "ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U338"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[116],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -14271,7 +13983,7 @@ }, "ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U340"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U269"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[120],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -14281,7 +13993,7 @@ }, "ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U342"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U270"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[124],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -14291,7 +14003,7 @@ }, "ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U344"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U271"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[128],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -14301,7 +14013,7 @@ }, "ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[121],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -14311,7 +14023,7 @@ }, "ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[125],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -14321,7 +14033,7 @@ }, "ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[98],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -14331,7 +14043,7 @@ }, "ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[102],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -14675,7 +14387,7 @@ ["self.op_hcompute_kernel_glb_stencil_write.0","self.op_hcompute_kernel_cgra_stencil_read.0"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U737":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U652":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14684,7 +14396,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U736":{ + "op_hcompute_hw_output_stencil_read_start_pt__U651":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14693,7 +14405,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U738":{ + "op_hcompute_hw_output_stencil_write_start_pt__U653":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14702,7 +14414,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U746":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U661":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14711,7 +14423,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U745":{ + "op_hcompute_input_glb_stencil_read_start_pt__U660":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14720,7 +14432,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U747":{ + "op_hcompute_input_glb_stencil_write_start_pt__U662":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14729,7 +14441,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U741":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U656":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14738,7 +14450,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U740":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U655":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14747,7 +14459,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U742":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U657":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14813,38 +14525,6 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U619":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U621":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U623":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U625":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U627":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U629":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U631":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U633":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -14852,7 +14532,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U618"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U542"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5181],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5184],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -14862,7 +14542,7 @@ }, "ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U620"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U543"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[1161],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5183],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5185],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -14872,7 +14552,7 @@ }, "ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U622"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U544"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5183],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5186],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -14882,7 +14562,7 @@ }, "ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U624"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U545"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5185],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5187],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -14892,7 +14572,7 @@ }, "ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U626"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U546"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5185],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5188],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -14902,7 +14582,7 @@ }, "ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U628"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U547"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5187],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5189],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -14912,7 +14592,7 @@ }, "ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U630"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U548"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5187],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5190],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -14922,7 +14602,7 @@ }, "ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U632"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U549"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5189],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5191],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -15011,158 +14691,126 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U799":{ + "PE_init_U714":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U802":{ + "PE_init_U717":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U805":{ + "PE_init_U720":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U808":{ + "PE_init_U723":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U811":{ + "PE_init_U726":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U814":{ + "PE_init_U729":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U817":{ + "PE_init_U732":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U820":{ + "PE_init_U735":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U797":{ + "_U712":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U798":{ + "_U713":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U800":{ + "_U715":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U801":{ + "_U716":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U803":{ + "_U718":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U804":{ + "_U719":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U806":{ + "_U721":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U807":{ + "_U722":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U809":{ + "_U724":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U810":{ + "_U725":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U812":{ + "_U727":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U813":{ + "_U728":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U815":{ + "_U730":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U816":{ + "_U731":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U818":{ + "_U733":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U819":{ + "_U734":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "input_cgra_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -15170,7 +14818,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -15180,7 +14828,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1149],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -15190,7 +14838,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -15200,7 +14848,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[16],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -15210,7 +14858,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[13],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -15220,7 +14868,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[14],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1149],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -15230,7 +14878,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[15],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -15240,7 +14888,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[16],"cycle_stride":[16,64,2016],"dimensionality":3,"extent":[4,16,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,64]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[4,64,2016],"dimensionality":3,"extent":[16,16,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[8,32,224,672,2016],"dimensionality":5,"extent":[4,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,4,64],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,2,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -15269,262 +14917,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "kernel_cgra_stencil$chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U271":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U273":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U275":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U277":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U279":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U281":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U283":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U285":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U287":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U289":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U291":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U293":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U295":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U297":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U299":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U301":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U303":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U305":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U307":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U309":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U311":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U313":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U315":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U317":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U319":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U321":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U323":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U325":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U327":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U329":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U331":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U333":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U335":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U337":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U339":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U341":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U343":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U345":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -15532,7 +14924,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[97],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -15542,7 +14934,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[106],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -15552,7 +14944,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U219"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[110],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -15562,7 +14954,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[114],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -15572,7 +14964,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U221"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[118],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -15582,7 +14974,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[122],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -15592,7 +14984,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U223"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[126],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -15602,7 +14994,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[99],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -15612,7 +15004,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U225"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[103],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -15622,7 +15014,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[107],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -15632,7 +15024,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U227"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[111],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -15642,7 +15034,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U209"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[101],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -15652,7 +15044,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[115],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -15662,7 +15054,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U229"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[119],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -15672,7 +15064,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[123],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -15682,7 +15074,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U231"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[127],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -15692,7 +15084,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[100],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -15702,7 +15094,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[104],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -15712,7 +15104,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U270"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[108],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -15722,7 +15114,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U272"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U235"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[112],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -15732,7 +15124,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U274"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[116],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -15742,7 +15134,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U276"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U237"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[120],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -15752,7 +15144,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[105],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -15762,7 +15154,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U278"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[124],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -15772,7 +15164,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U280"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U239"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[128],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -15782,7 +15174,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U282"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[97],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -15792,7 +15184,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U284"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U241"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[101],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -15802,7 +15194,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U286"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[105],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -15812,7 +15204,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U288"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U243"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[109],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -15822,7 +15214,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U290"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[113],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -15832,7 +15224,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U292"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U245"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[117],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -15842,7 +15234,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[121],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -15852,7 +15244,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U296"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U247"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[125],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -15862,7 +15254,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U211"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[109],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -15872,7 +15264,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U298"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[98],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -15882,7 +15274,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U300"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U249"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[102],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -15892,7 +15284,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U302"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[106],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -15902,7 +15294,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U304"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U251"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[110],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -15912,7 +15304,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U306"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[114],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -15922,7 +15314,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U253"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[118],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -15932,7 +15324,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U310"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[122],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -15942,7 +15334,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U312"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U255"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[126],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -15952,7 +15344,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U314"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[99],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -15962,7 +15354,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U316"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U257"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[103],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -15972,7 +15364,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[113],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -15982,7 +15374,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U318"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[107],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -15992,7 +15384,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U320"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U259"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[111],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -16002,7 +15394,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U322"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[115],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -16012,7 +15404,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U324"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U261"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[119],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -16022,7 +15414,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U326"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[123],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -16032,7 +15424,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U328"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U263"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[127],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -16042,7 +15434,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U330"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[100],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -16052,7 +15444,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U332"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U265"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[104],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -16062,7 +15454,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U334"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[108],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -16072,7 +15464,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U336"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U267"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[112],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -16082,7 +15474,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U213"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[117],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -16092,7 +15484,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U338"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[116],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -16102,7 +15494,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U340"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U269"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[120],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -16112,7 +15504,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U342"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U270"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[124],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -16122,7 +15514,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U344"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U271"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[128],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -16132,7 +15524,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[121],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -16142,7 +15534,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U215"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[125],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -16152,7 +15544,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[98],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -16162,7 +15554,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U217"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[102],"cycle_stride":[128,384,2016],"dimensionality":3,"extent":[3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,3,9]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[32,128,384,2016],"dimensionality":4,"extent":[4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,32,224,672,2016],"dimensionality":5,"extent":[7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,3,9],"write_data_starting_addr":[0],"write_data_stride":[0,0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,4,32,224,672,2016],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -16172,7 +15564,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U735"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U650"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[-9215],"cycle_stride":[2],"dimensionality":1,"extent":[2048],"write_data_starting_addr":[0],"write_data_stride":[1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_output_cgra_stencil_10$inner_compute$add_899_913_914$binop":{ @@ -16815,38 +16207,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "output_cgra_stencil$chain_en_const_U619":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U621":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U623":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U625":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U627":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U629":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U631":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U633":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -16854,7 +16214,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U618"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U542"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5181],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5184],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -16864,7 +16224,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U620"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U543"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"agg2sram_1":{"cycle_starting_addr":[1161],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"in2agg_1":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5183],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5185],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -16874,7 +16234,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U622"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U544"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5183],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5186],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -16884,7 +16244,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U624"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U545"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5185],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5187],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -16894,7 +16254,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U626"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U546"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5185],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5188],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -16904,7 +16264,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U628"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U547"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5187],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5189],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -16914,7 +16274,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U630"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U548"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5187],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5190],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -16924,35 +16284,35 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U632"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U549"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1160],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,49]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,4032],"dimensionality":3,"extent":[7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,3,1],"write_data_starting_addr":[0],"write_data_stride":[1,7,49]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,4]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,4,28,4032],"dimensionality":4,"extent":[4,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,4,12,4]},"sram2tb_0":{"cycle_starting_addr":[1154],"cycle_stride":[4,32,224,672,2016,4032],"dimensionality":6,"extent":[7,7,3,3,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,49],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,1]},"sram2tb_1":{"cycle_starting_addr":[5189],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[0,1,7,49],"write_data_starting_addr":[0],"write_data_stride":[0,1,3,1]},"tb2out_0":{"cycle_starting_addr":[1156],"cycle_stride":[1,32,224,4032],"dimensionality":4,"extent":[28,7,18,2],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,4]},"tb2out_1":{"cycle_starting_addr":[5191],"cycle_stride":[8,32,224,4032],"dimensionality":4,"extent":[4,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,4,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U797.out","PE_init_U799.data.in.0"], - ["_U798.out","PE_init_U799.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U799.data.out"], - ["_U800.out","PE_init_U802.data.in.0"], - ["_U801.out","PE_init_U802.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U802.data.out"], - ["_U803.out","PE_init_U805.data.in.0"], - ["_U804.out","PE_init_U805.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U805.data.out"], - ["_U806.out","PE_init_U808.data.in.0"], - ["_U807.out","PE_init_U808.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U808.data.out"], - ["_U809.out","PE_init_U811.data.in.0"], - ["_U810.out","PE_init_U811.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U811.data.out"], - ["_U812.out","PE_init_U814.data.in.0"], - ["_U813.out","PE_init_U814.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U814.data.out"], - ["_U815.out","PE_init_U817.data.in.0"], - ["_U816.out","PE_init_U817.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U817.data.out"], - ["_U818.out","PE_init_U820.data.in.0"], - ["_U819.out","PE_init_U820.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U820.data.out"], + ["_U712.out","PE_init_U714.data.in.0"], + ["_U713.out","PE_init_U714.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U714.data.out"], + ["_U715.out","PE_init_U717.data.in.0"], + ["_U716.out","PE_init_U717.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U717.data.out"], + ["_U718.out","PE_init_U720.data.in.0"], + ["_U719.out","PE_init_U720.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U720.data.out"], + ["_U721.out","PE_init_U723.data.in.0"], + ["_U722.out","PE_init_U723.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U723.data.out"], + ["_U724.out","PE_init_U726.data.in.0"], + ["_U725.out","PE_init_U726.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U726.data.out"], + ["_U727.out","PE_init_U729.data.in.0"], + ["_U728.out","PE_init_U729.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U729.data.out"], + ["_U730.out","PE_init_U732.data.in.0"], + ["_U731.out","PE_init_U732.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U732.data.out"], + ["_U733.out","PE_init_U735.data.in.0"], + ["_U734.out","PE_init_U735.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U735.data.out"], ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_input_host_stencil_op_hcompute_input_glb_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_output_cgra_stencil_10$inner_compute$mul_kernel_cgra_stencil_17_input_cgra_stencil_17_899$binop.data.in.1","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_new/resnet5_x/resnet5_x.json b/aha_garnet_design_new/resnet5_x/resnet5_x.json index 9a3df532a..acd6418a1 100644 --- a/aha_garnet_design_new/resnet5_x/resnet5_x.json +++ b/aha_garnet_design_new/resnet5_x/resnet5_x.json @@ -2,2510 +2,2395 @@ "namespaces":{ "global":{ "modules":{ - "aff__U1000":{ + "aff__U100":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1006":{ + "add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1007":{ + "add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1001":{ + "coeff_0_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1003":{ + "coeff_1_U103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1005":{ + "const_term_U105":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1002":{ + "mul_d0__U102":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1004":{ + "mul_d1__U104":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1002.out","add_all__U1006.in0"], - ["mul_d1__U1004.out","add_all__U1006.in1"], - ["add_all__U1007.in0","add_all__U1006.out"], - ["const_term_U1005.out","add_all__U1007.in1"], - ["self.out","add_all__U1007.out"], - ["mul_d0__U1002.in0","coeff_0_U1001.out"], - ["mul_d1__U1004.in0","coeff_1_U1003.out"], - ["self.d.0","mul_d0__U1002.in1"], - ["self.d.1","mul_d1__U1004.in1"] + ["mul_d0__U102.out","add_all__U106.in0"], + ["mul_d1__U104.out","add_all__U106.in1"], + ["add_all__U107.in0","add_all__U106.out"], + ["const_term_U105.out","add_all__U107.in1"], + ["self.out","add_all__U107.out"], + ["mul_d0__U102.in0","coeff_0_U101.out"], + ["mul_d1__U104.in0","coeff_1_U103.out"], + ["self.d.0","mul_d0__U102.in1"], + ["self.d.1","mul_d1__U104.in1"] ] }, - "aff__U1015":{ + "aff__U1010":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1021":{ + "add_all__U1016":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1022":{ + "add_all__U1017":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1016":{ + "coeff_0_U1011":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1018":{ + "coeff_1_U1013":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1020":{ + "const_term_U1015":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1017":{ + "mul_d0__U1012":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1019":{ + "mul_d1__U1014":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1017.out","add_all__U1021.in0"], - ["mul_d1__U1019.out","add_all__U1021.in1"], - ["add_all__U1022.in0","add_all__U1021.out"], - ["const_term_U1020.out","add_all__U1022.in1"], - ["self.out","add_all__U1022.out"], - ["mul_d0__U1017.in0","coeff_0_U1016.out"], - ["mul_d1__U1019.in0","coeff_1_U1018.out"], - ["self.d.0","mul_d0__U1017.in1"], - ["self.d.1","mul_d1__U1019.in1"] + ["mul_d0__U1012.out","add_all__U1016.in0"], + ["mul_d1__U1014.out","add_all__U1016.in1"], + ["add_all__U1017.in0","add_all__U1016.out"], + ["const_term_U1015.out","add_all__U1017.in1"], + ["self.out","add_all__U1017.out"], + ["mul_d0__U1012.in0","coeff_0_U1011.out"], + ["mul_d1__U1014.in0","coeff_1_U1013.out"], + ["self.d.0","mul_d0__U1012.in1"], + ["self.d.1","mul_d1__U1014.in1"] ] }, - "aff__U1030":{ + "aff__U1024":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1036":{ + "add_all__U1030":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1037":{ + "add_all__U1031":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1031":{ + "coeff_0_U1025":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1033":{ + "coeff_1_U1027":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1035":{ + "const_term_U1029":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1032":{ + "mul_d0__U1026":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1034":{ + "mul_d1__U1028":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1032.out","add_all__U1036.in0"], - ["mul_d1__U1034.out","add_all__U1036.in1"], - ["add_all__U1037.in0","add_all__U1036.out"], - ["const_term_U1035.out","add_all__U1037.in1"], - ["self.out","add_all__U1037.out"], - ["mul_d0__U1032.in0","coeff_0_U1031.out"], - ["mul_d1__U1034.in0","coeff_1_U1033.out"], - ["self.d.0","mul_d0__U1032.in1"], - ["self.d.1","mul_d1__U1034.in1"] + ["mul_d0__U1026.out","add_all__U1030.in0"], + ["mul_d1__U1028.out","add_all__U1030.in1"], + ["add_all__U1031.in0","add_all__U1030.out"], + ["const_term_U1029.out","add_all__U1031.in1"], + ["self.out","add_all__U1031.out"], + ["mul_d0__U1026.in0","coeff_0_U1025.out"], + ["mul_d1__U1028.in0","coeff_1_U1027.out"], + ["self.d.0","mul_d0__U1026.in1"], + ["self.d.1","mul_d1__U1028.in1"] ] }, - "aff__U1045":{ + "aff__U1038":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1051":{ + "add_all__U1044":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1052":{ + "add_all__U1045":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1046":{ + "coeff_0_U1039":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1048":{ + "coeff_1_U1041":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1050":{ + "const_term_U1043":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1047":{ + "mul_d0__U1040":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1049":{ + "mul_d1__U1042":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1047.out","add_all__U1051.in0"], - ["mul_d1__U1049.out","add_all__U1051.in1"], - ["add_all__U1052.in0","add_all__U1051.out"], - ["const_term_U1050.out","add_all__U1052.in1"], - ["self.out","add_all__U1052.out"], - ["mul_d0__U1047.in0","coeff_0_U1046.out"], - ["mul_d1__U1049.in0","coeff_1_U1048.out"], - ["self.d.0","mul_d0__U1047.in1"], - ["self.d.1","mul_d1__U1049.in1"] + ["mul_d0__U1040.out","add_all__U1044.in0"], + ["mul_d1__U1042.out","add_all__U1044.in1"], + ["add_all__U1045.in0","add_all__U1044.out"], + ["const_term_U1043.out","add_all__U1045.in1"], + ["self.out","add_all__U1045.out"], + ["mul_d0__U1040.in0","coeff_0_U1039.out"], + ["mul_d1__U1042.in0","coeff_1_U1041.out"], + ["self.d.0","mul_d0__U1040.in1"], + ["self.d.1","mul_d1__U1042.in1"] ] }, - "aff__U1060":{ + "aff__U1052":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1066":{ + "add_all__U1058":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1067":{ + "add_all__U1059":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1061":{ + "coeff_0_U1053":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1063":{ + "coeff_1_U1055":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1065":{ + "const_term_U1057":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1062":{ + "mul_d0__U1054":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1064":{ + "mul_d1__U1056":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1062.out","add_all__U1066.in0"], - ["mul_d1__U1064.out","add_all__U1066.in1"], - ["add_all__U1067.in0","add_all__U1066.out"], - ["const_term_U1065.out","add_all__U1067.in1"], - ["self.out","add_all__U1067.out"], - ["mul_d0__U1062.in0","coeff_0_U1061.out"], - ["mul_d1__U1064.in0","coeff_1_U1063.out"], - ["self.d.0","mul_d0__U1062.in1"], - ["self.d.1","mul_d1__U1064.in1"] + ["mul_d0__U1054.out","add_all__U1058.in0"], + ["mul_d1__U1056.out","add_all__U1058.in1"], + ["add_all__U1059.in0","add_all__U1058.out"], + ["const_term_U1057.out","add_all__U1059.in1"], + ["self.out","add_all__U1059.out"], + ["mul_d0__U1054.in0","coeff_0_U1053.out"], + ["mul_d1__U1056.in0","coeff_1_U1055.out"], + ["self.d.0","mul_d0__U1054.in1"], + ["self.d.1","mul_d1__U1056.in1"] ] }, - "aff__U107":{ + "aff__U1066":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U113":{ + "add_all__U1072":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U1073":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U108":{ + "coeff_0_U1067":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U110":{ + "coeff_1_U1069":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U112":{ + "const_term_U1071":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U109":{ + "mul_d0__U1068":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U111":{ + "mul_d1__U1070":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U109.out","add_all__U113.in0"], - ["mul_d1__U111.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U112.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U109.in0","coeff_0_U108.out"], - ["mul_d1__U111.in0","coeff_1_U110.out"], - ["self.d.0","mul_d0__U109.in1"], - ["self.d.1","mul_d1__U111.in1"] + ["mul_d0__U1068.out","add_all__U1072.in0"], + ["mul_d1__U1070.out","add_all__U1072.in1"], + ["add_all__U1073.in0","add_all__U1072.out"], + ["const_term_U1071.out","add_all__U1073.in1"], + ["self.out","add_all__U1073.out"], + ["mul_d0__U1068.in0","coeff_0_U1067.out"], + ["mul_d1__U1070.in0","coeff_1_U1069.out"], + ["self.d.0","mul_d0__U1068.in1"], + ["self.d.1","mul_d1__U1070.in1"] ] }, - "aff__U1075":{ + "aff__U1080":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1081":{ + "add_all__U1086":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1082":{ + "add_all__U1087":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1076":{ + "coeff_0_U1081":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1078":{ + "coeff_1_U1083":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1080":{ + "const_term_U1085":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1077":{ + "mul_d0__U1082":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1079":{ + "mul_d1__U1084":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1077.out","add_all__U1081.in0"], - ["mul_d1__U1079.out","add_all__U1081.in1"], - ["add_all__U1082.in0","add_all__U1081.out"], - ["const_term_U1080.out","add_all__U1082.in1"], - ["self.out","add_all__U1082.out"], - ["mul_d0__U1077.in0","coeff_0_U1076.out"], - ["mul_d1__U1079.in0","coeff_1_U1078.out"], - ["self.d.0","mul_d0__U1077.in1"], - ["self.d.1","mul_d1__U1079.in1"] + ["mul_d0__U1082.out","add_all__U1086.in0"], + ["mul_d1__U1084.out","add_all__U1086.in1"], + ["add_all__U1087.in0","add_all__U1086.out"], + ["const_term_U1085.out","add_all__U1087.in1"], + ["self.out","add_all__U1087.out"], + ["mul_d0__U1082.in0","coeff_0_U1081.out"], + ["mul_d1__U1084.in0","coeff_1_U1083.out"], + ["self.d.0","mul_d0__U1082.in1"], + ["self.d.1","mul_d1__U1084.in1"] ] }, - "aff__U1090":{ + "aff__U1094":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1096":{ + "add_all__U1100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1097":{ + "add_all__U1101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1091":{ + "coeff_0_U1095":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1093":{ + "coeff_1_U1097":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1095":{ + "const_term_U1099":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1092":{ + "mul_d0__U1096":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1094":{ + "mul_d1__U1098":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1092.out","add_all__U1096.in0"], - ["mul_d1__U1094.out","add_all__U1096.in1"], - ["add_all__U1097.in0","add_all__U1096.out"], - ["const_term_U1095.out","add_all__U1097.in1"], - ["self.out","add_all__U1097.out"], - ["mul_d0__U1092.in0","coeff_0_U1091.out"], - ["mul_d1__U1094.in0","coeff_1_U1093.out"], - ["self.d.0","mul_d0__U1092.in1"], - ["self.d.1","mul_d1__U1094.in1"] + ["mul_d0__U1096.out","add_all__U1100.in0"], + ["mul_d1__U1098.out","add_all__U1100.in1"], + ["add_all__U1101.in0","add_all__U1100.out"], + ["const_term_U1099.out","add_all__U1101.in1"], + ["self.out","add_all__U1101.out"], + ["mul_d0__U1096.in0","coeff_0_U1095.out"], + ["mul_d1__U1098.in0","coeff_1_U1097.out"], + ["self.d.0","mul_d0__U1096.in1"], + ["self.d.1","mul_d1__U1098.in1"] ] }, - "aff__U1105":{ + "aff__U1108":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1111":{ + "add_all__U1114":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1112":{ + "add_all__U1115":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1106":{ + "coeff_0_U1109":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1108":{ + "coeff_1_U1111":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1110":{ + "const_term_U1113":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1107":{ + "mul_d0__U1110":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1109":{ + "mul_d1__U1112":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1107.out","add_all__U1111.in0"], - ["mul_d1__U1109.out","add_all__U1111.in1"], - ["add_all__U1112.in0","add_all__U1111.out"], - ["const_term_U1110.out","add_all__U1112.in1"], - ["self.out","add_all__U1112.out"], - ["mul_d0__U1107.in0","coeff_0_U1106.out"], - ["mul_d1__U1109.in0","coeff_1_U1108.out"], - ["self.d.0","mul_d0__U1107.in1"], - ["self.d.1","mul_d1__U1109.in1"] + ["mul_d0__U1110.out","add_all__U1114.in0"], + ["mul_d1__U1112.out","add_all__U1114.in1"], + ["add_all__U1115.in0","add_all__U1114.out"], + ["const_term_U1113.out","add_all__U1115.in1"], + ["self.out","add_all__U1115.out"], + ["mul_d0__U1110.in0","coeff_0_U1109.out"], + ["mul_d1__U1112.in0","coeff_1_U1111.out"], + ["self.d.0","mul_d0__U1110.in1"], + ["self.d.1","mul_d1__U1112.in1"] ] }, - "aff__U1120":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1126":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1127":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1121":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1123":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1125":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1122":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1124":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1122.out","add_all__U1126.in0"], - ["mul_d1__U1124.out","add_all__U1126.in1"], - ["add_all__U1127.in0","add_all__U1126.out"], - ["const_term_U1125.out","add_all__U1127.in1"], - ["self.out","add_all__U1127.out"], - ["mul_d0__U1122.in0","coeff_0_U1121.out"], - ["mul_d1__U1124.in0","coeff_1_U1123.out"], - ["self.d.0","mul_d0__U1122.in1"], - ["self.d.1","mul_d1__U1124.in1"] - ] - }, - "aff__U1135":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1141":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1142":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1136":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1138":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1140":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1137":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1139":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1137.out","add_all__U1141.in0"], - ["mul_d1__U1139.out","add_all__U1141.in1"], - ["add_all__U1142.in0","add_all__U1141.out"], - ["const_term_U1140.out","add_all__U1142.in1"], - ["self.out","add_all__U1142.out"], - ["mul_d0__U1137.in0","coeff_0_U1136.out"], - ["mul_d1__U1139.in0","coeff_1_U1138.out"], - ["self.d.0","mul_d0__U1137.in1"], - ["self.d.1","mul_d1__U1139.in1"] - ] - }, - "aff__U1150":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1156":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1157":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1151":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1153":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1155":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1152":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1154":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1152.out","add_all__U1156.in0"], - ["mul_d1__U1154.out","add_all__U1156.in1"], - ["add_all__U1157.in0","add_all__U1156.out"], - ["const_term_U1155.out","add_all__U1157.in1"], - ["self.out","add_all__U1157.out"], - ["mul_d0__U1152.in0","coeff_0_U1151.out"], - ["mul_d1__U1154.in0","coeff_1_U1153.out"], - ["self.d.0","mul_d0__U1152.in1"], - ["self.d.1","mul_d1__U1154.in1"] - ] - }, - "aff__U1165":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1171":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1172":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1166":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1168":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1170":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1167":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1169":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1167.out","add_all__U1171.in0"], - ["mul_d1__U1169.out","add_all__U1171.in1"], - ["add_all__U1172.in0","add_all__U1171.out"], - ["const_term_U1170.out","add_all__U1172.in1"], - ["self.out","add_all__U1172.out"], - ["mul_d0__U1167.in0","coeff_0_U1166.out"], - ["mul_d1__U1169.in0","coeff_1_U1168.out"], - ["self.d.0","mul_d0__U1167.in1"], - ["self.d.1","mul_d1__U1169.in1"] - ] - }, - "aff__U1180":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1186":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1187":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1181":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1183":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1185":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1182":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1184":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1182.out","add_all__U1186.in0"], - ["mul_d1__U1184.out","add_all__U1186.in1"], - ["add_all__U1187.in0","add_all__U1186.out"], - ["const_term_U1185.out","add_all__U1187.in1"], - ["self.out","add_all__U1187.out"], - ["mul_d0__U1182.in0","coeff_0_U1181.out"], - ["mul_d1__U1184.in0","coeff_1_U1183.out"], - ["self.d.0","mul_d0__U1182.in1"], - ["self.d.1","mul_d1__U1184.in1"] - ] - }, - "aff__U1195":{ + "aff__U1121":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1207":{ + "add_all__U1133":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1208":{ + "add_all__U1134":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1209":{ + "add_all__U1135":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1210":{ + "add_all__U1136":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1211":{ + "add_all__U1137":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1196":{ + "coeff_0_U1122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1198":{ + "coeff_1_U1124":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006000"]} }, - "coeff_2_U1200":{ + "coeff_2_U1126":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U1202":{ + "coeff_3_U1128":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_4_U1204":{ + "coeff_4_U1130":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1206":{ + "const_term_U1132":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1197":{ + "mul_d0__U1123":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1199":{ + "mul_d1__U1125":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1201":{ + "mul_d2__U1127":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1203":{ + "mul_d3__U1129":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1205":{ + "mul_d4__U1131":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1197.out","add_all__U1207.in0"], - ["mul_d1__U1199.out","add_all__U1207.in1"], - ["add_all__U1208.in0","add_all__U1207.out"], - ["mul_d2__U1201.out","add_all__U1208.in1"], - ["add_all__U1209.in0","add_all__U1208.out"], - ["mul_d3__U1203.out","add_all__U1209.in1"], - ["add_all__U1210.in0","add_all__U1209.out"], - ["mul_d4__U1205.out","add_all__U1210.in1"], - ["add_all__U1211.in0","add_all__U1210.out"], - ["const_term_U1206.out","add_all__U1211.in1"], - ["self.out","add_all__U1211.out"], - ["mul_d0__U1197.in0","coeff_0_U1196.out"], - ["mul_d1__U1199.in0","coeff_1_U1198.out"], - ["mul_d2__U1201.in0","coeff_2_U1200.out"], - ["mul_d3__U1203.in0","coeff_3_U1202.out"], - ["mul_d4__U1205.in0","coeff_4_U1204.out"], - ["self.d.0","mul_d0__U1197.in1"], - ["self.d.1","mul_d1__U1199.in1"], - ["self.d.2","mul_d2__U1201.in1"], - ["self.d.3","mul_d3__U1203.in1"], - ["self.d.4","mul_d4__U1205.in1"] + ["mul_d0__U1123.out","add_all__U1133.in0"], + ["mul_d1__U1125.out","add_all__U1133.in1"], + ["add_all__U1134.in0","add_all__U1133.out"], + ["mul_d2__U1127.out","add_all__U1134.in1"], + ["add_all__U1135.in0","add_all__U1134.out"], + ["mul_d3__U1129.out","add_all__U1135.in1"], + ["add_all__U1136.in0","add_all__U1135.out"], + ["mul_d4__U1131.out","add_all__U1136.in1"], + ["add_all__U1137.in0","add_all__U1136.out"], + ["const_term_U1132.out","add_all__U1137.in1"], + ["self.out","add_all__U1137.out"], + ["mul_d0__U1123.in0","coeff_0_U1122.out"], + ["mul_d1__U1125.in0","coeff_1_U1124.out"], + ["mul_d2__U1127.in0","coeff_2_U1126.out"], + ["mul_d3__U1129.in0","coeff_3_U1128.out"], + ["mul_d4__U1131.in0","coeff_4_U1130.out"], + ["self.d.0","mul_d0__U1123.in1"], + ["self.d.1","mul_d1__U1125.in1"], + ["self.d.2","mul_d2__U1127.in1"], + ["self.d.3","mul_d3__U1129.in1"], + ["self.d.4","mul_d4__U1131.in1"] ] }, - "aff__U122":{ + "aff__U113":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U132":{ + "add_all__U123":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U133":{ + "add_all__U124":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U134":{ + "add_all__U125":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U135":{ + "add_all__U126":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U123":{ + "coeff_0_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U125":{ + "coeff_1_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "coeff_2_U127":{ + "coeff_2_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U129":{ + "coeff_3_U120":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U131":{ + "const_term_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U124":{ + "mul_d0__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U126":{ + "mul_d1__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U128":{ + "mul_d2__U119":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U130":{ + "mul_d3__U121":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U124.out","add_all__U132.in0"], - ["mul_d1__U126.out","add_all__U132.in1"], - ["add_all__U133.in0","add_all__U132.out"], - ["mul_d2__U128.out","add_all__U133.in1"], - ["add_all__U134.in0","add_all__U133.out"], - ["mul_d3__U130.out","add_all__U134.in1"], - ["add_all__U135.in0","add_all__U134.out"], - ["const_term_U131.out","add_all__U135.in1"], - ["self.out","add_all__U135.out"], - ["mul_d0__U124.in0","coeff_0_U123.out"], - ["mul_d1__U126.in0","coeff_1_U125.out"], - ["mul_d2__U128.in0","coeff_2_U127.out"], - ["mul_d3__U130.in0","coeff_3_U129.out"], - ["self.d.0","mul_d0__U124.in1"], - ["self.d.1","mul_d1__U126.in1"], - ["self.d.2","mul_d2__U128.in1"], - ["self.d.3","mul_d3__U130.in1"] + ["mul_d0__U115.out","add_all__U123.in0"], + ["mul_d1__U117.out","add_all__U123.in1"], + ["add_all__U124.in0","add_all__U123.out"], + ["mul_d2__U119.out","add_all__U124.in1"], + ["add_all__U125.in0","add_all__U124.out"], + ["mul_d3__U121.out","add_all__U125.in1"], + ["add_all__U126.in0","add_all__U125.out"], + ["const_term_U122.out","add_all__U126.in1"], + ["self.out","add_all__U126.out"], + ["mul_d0__U115.in0","coeff_0_U114.out"], + ["mul_d1__U117.in0","coeff_1_U116.out"], + ["mul_d2__U119.in0","coeff_2_U118.out"], + ["mul_d3__U121.in0","coeff_3_U120.out"], + ["self.d.0","mul_d0__U115.in1"], + ["self.d.1","mul_d1__U117.in1"], + ["self.d.2","mul_d2__U119.in1"], + ["self.d.3","mul_d3__U121.in1"] ] }, - "aff__U1225":{ + "aff__U1151":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1237":{ + "add_all__U1163":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1238":{ + "add_all__U1164":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1239":{ + "add_all__U1165":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1240":{ + "add_all__U1166":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1241":{ + "add_all__U1167":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1226":{ + "coeff_0_U1152":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1228":{ + "coeff_1_U1154":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U1230":{ + "coeff_2_U1156":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U1232":{ + "coeff_3_U1158":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U1234":{ + "coeff_4_U1160":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U1236":{ + "const_term_U1162":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1227":{ + "mul_d0__U1153":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1229":{ + "mul_d1__U1155":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1231":{ + "mul_d2__U1157":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1233":{ + "mul_d3__U1159":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1235":{ + "mul_d4__U1161":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1227.out","add_all__U1237.in0"], - ["mul_d1__U1229.out","add_all__U1237.in1"], - ["add_all__U1238.in0","add_all__U1237.out"], - ["mul_d2__U1231.out","add_all__U1238.in1"], - ["add_all__U1239.in0","add_all__U1238.out"], - ["mul_d3__U1233.out","add_all__U1239.in1"], - ["add_all__U1240.in0","add_all__U1239.out"], - ["mul_d4__U1235.out","add_all__U1240.in1"], - ["add_all__U1241.in0","add_all__U1240.out"], - ["const_term_U1236.out","add_all__U1241.in1"], - ["self.out","add_all__U1241.out"], - ["mul_d0__U1227.in0","coeff_0_U1226.out"], - ["mul_d1__U1229.in0","coeff_1_U1228.out"], - ["mul_d2__U1231.in0","coeff_2_U1230.out"], - ["mul_d3__U1233.in0","coeff_3_U1232.out"], - ["mul_d4__U1235.in0","coeff_4_U1234.out"], - ["self.d.0","mul_d0__U1227.in1"], - ["self.d.1","mul_d1__U1229.in1"], - ["self.d.2","mul_d2__U1231.in1"], - ["self.d.3","mul_d3__U1233.in1"], - ["self.d.4","mul_d4__U1235.in1"] + ["mul_d0__U1153.out","add_all__U1163.in0"], + ["mul_d1__U1155.out","add_all__U1163.in1"], + ["add_all__U1164.in0","add_all__U1163.out"], + ["mul_d2__U1157.out","add_all__U1164.in1"], + ["add_all__U1165.in0","add_all__U1164.out"], + ["mul_d3__U1159.out","add_all__U1165.in1"], + ["add_all__U1166.in0","add_all__U1165.out"], + ["mul_d4__U1161.out","add_all__U1166.in1"], + ["add_all__U1167.in0","add_all__U1166.out"], + ["const_term_U1162.out","add_all__U1167.in1"], + ["self.out","add_all__U1167.out"], + ["mul_d0__U1153.in0","coeff_0_U1152.out"], + ["mul_d1__U1155.in0","coeff_1_U1154.out"], + ["mul_d2__U1157.in0","coeff_2_U1156.out"], + ["mul_d3__U1159.in0","coeff_3_U1158.out"], + ["mul_d4__U1161.in0","coeff_4_U1160.out"], + ["self.d.0","mul_d0__U1153.in1"], + ["self.d.1","mul_d1__U1155.in1"], + ["self.d.2","mul_d2__U1157.in1"], + ["self.d.3","mul_d3__U1159.in1"], + ["self.d.4","mul_d4__U1161.in1"] ] }, - "aff__U1244":{ + "aff__U1170":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1264":{ + "add_all__U1190":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1265":{ + "add_all__U1191":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1266":{ + "add_all__U1192":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1267":{ + "add_all__U1193":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1268":{ + "add_all__U1194":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1269":{ + "add_all__U1195":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1270":{ + "add_all__U1196":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1271":{ + "add_all__U1197":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1272":{ + "add_all__U1198":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1245":{ + "coeff_0_U1171":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1247":{ + "coeff_1_U1173":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U1249":{ + "coeff_2_U1175":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004800"]} }, - "coeff_3_U1251":{ + "coeff_3_U1177":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001800"]} }, - "coeff_4_U1253":{ + "coeff_4_U1179":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000800"]} }, - "coeff_5_U1255":{ + "coeff_5_U1181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000200"]} }, - "coeff_6_U1257":{ + "coeff_6_U1183":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_7_U1259":{ + "coeff_7_U1185":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_8_U1261":{ + "coeff_8_U1187":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1263":{ + "const_term_U1189":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00011fff"]} }, - "mul_d0__U1246":{ + "mul_d0__U1172":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1248":{ + "mul_d1__U1174":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1250":{ + "mul_d2__U1176":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1252":{ + "mul_d3__U1178":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1254":{ + "mul_d4__U1180":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1256":{ + "mul_d5__U1182":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U1258":{ + "mul_d6__U1184":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U1260":{ + "mul_d7__U1186":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U1262":{ + "mul_d8__U1188":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1246.out","add_all__U1264.in0"], - ["mul_d1__U1248.out","add_all__U1264.in1"], - ["add_all__U1265.in0","add_all__U1264.out"], - ["mul_d2__U1250.out","add_all__U1265.in1"], - ["add_all__U1266.in0","add_all__U1265.out"], - ["mul_d3__U1252.out","add_all__U1266.in1"], - ["add_all__U1267.in0","add_all__U1266.out"], - ["mul_d4__U1254.out","add_all__U1267.in1"], - ["add_all__U1268.in0","add_all__U1267.out"], - ["mul_d5__U1256.out","add_all__U1268.in1"], - ["add_all__U1269.in0","add_all__U1268.out"], - ["mul_d6__U1258.out","add_all__U1269.in1"], - ["add_all__U1270.in0","add_all__U1269.out"], - ["mul_d7__U1260.out","add_all__U1270.in1"], - ["add_all__U1271.in0","add_all__U1270.out"], - ["mul_d8__U1262.out","add_all__U1271.in1"], - ["add_all__U1272.in0","add_all__U1271.out"], - ["const_term_U1263.out","add_all__U1272.in1"], - ["self.out","add_all__U1272.out"], - ["mul_d0__U1246.in0","coeff_0_U1245.out"], - ["mul_d1__U1248.in0","coeff_1_U1247.out"], - ["mul_d2__U1250.in0","coeff_2_U1249.out"], - ["mul_d3__U1252.in0","coeff_3_U1251.out"], - ["mul_d4__U1254.in0","coeff_4_U1253.out"], - ["mul_d5__U1256.in0","coeff_5_U1255.out"], - ["mul_d6__U1258.in0","coeff_6_U1257.out"], - ["mul_d7__U1260.in0","coeff_7_U1259.out"], - ["mul_d8__U1262.in0","coeff_8_U1261.out"], - ["self.d.0","mul_d0__U1246.in1"], - ["self.d.1","mul_d1__U1248.in1"], - ["self.d.2","mul_d2__U1250.in1"], - ["self.d.3","mul_d3__U1252.in1"], - ["self.d.4","mul_d4__U1254.in1"], - ["self.d.5","mul_d5__U1256.in1"], - ["self.d.6","mul_d6__U1258.in1"], - ["self.d.7","mul_d7__U1260.in1"], - ["self.d.8","mul_d8__U1262.in1"] + ["mul_d0__U1172.out","add_all__U1190.in0"], + ["mul_d1__U1174.out","add_all__U1190.in1"], + ["add_all__U1191.in0","add_all__U1190.out"], + ["mul_d2__U1176.out","add_all__U1191.in1"], + ["add_all__U1192.in0","add_all__U1191.out"], + ["mul_d3__U1178.out","add_all__U1192.in1"], + ["add_all__U1193.in0","add_all__U1192.out"], + ["mul_d4__U1180.out","add_all__U1193.in1"], + ["add_all__U1194.in0","add_all__U1193.out"], + ["mul_d5__U1182.out","add_all__U1194.in1"], + ["add_all__U1195.in0","add_all__U1194.out"], + ["mul_d6__U1184.out","add_all__U1195.in1"], + ["add_all__U1196.in0","add_all__U1195.out"], + ["mul_d7__U1186.out","add_all__U1196.in1"], + ["add_all__U1197.in0","add_all__U1196.out"], + ["mul_d8__U1188.out","add_all__U1197.in1"], + ["add_all__U1198.in0","add_all__U1197.out"], + ["const_term_U1189.out","add_all__U1198.in1"], + ["self.out","add_all__U1198.out"], + ["mul_d0__U1172.in0","coeff_0_U1171.out"], + ["mul_d1__U1174.in0","coeff_1_U1173.out"], + ["mul_d2__U1176.in0","coeff_2_U1175.out"], + ["mul_d3__U1178.in0","coeff_3_U1177.out"], + ["mul_d4__U1180.in0","coeff_4_U1179.out"], + ["mul_d5__U1182.in0","coeff_5_U1181.out"], + ["mul_d6__U1184.in0","coeff_6_U1183.out"], + ["mul_d7__U1186.in0","coeff_7_U1185.out"], + ["mul_d8__U1188.in0","coeff_8_U1187.out"], + ["self.d.0","mul_d0__U1172.in1"], + ["self.d.1","mul_d1__U1174.in1"], + ["self.d.2","mul_d2__U1176.in1"], + ["self.d.3","mul_d3__U1178.in1"], + ["self.d.4","mul_d4__U1180.in1"], + ["self.d.5","mul_d5__U1182.in1"], + ["self.d.6","mul_d6__U1184.in1"], + ["self.d.7","mul_d7__U1186.in1"], + ["self.d.8","mul_d8__U1188.in1"] ] }, - "aff__U1312":{ + "aff__U1238":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1332":{ + "add_all__U1258":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1333":{ + "add_all__U1259":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1334":{ + "add_all__U1260":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1335":{ + "add_all__U1261":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1336":{ + "add_all__U1262":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1337":{ + "add_all__U1263":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1338":{ + "add_all__U1264":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1339":{ + "add_all__U1265":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1340":{ + "add_all__U1266":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1313":{ + "coeff_0_U1239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1315":{ + "coeff_1_U1241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U1317":{ + "coeff_2_U1243":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_3_U1319":{ + "coeff_3_U1245":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U1321":{ + "coeff_4_U1247":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U1323":{ + "coeff_5_U1249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U1325":{ + "coeff_6_U1251":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U1327":{ + "coeff_7_U1253":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_8_U1329":{ + "coeff_8_U1255":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U1331":{ + "const_term_U1257":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1314":{ + "mul_d0__U1240":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1316":{ + "mul_d1__U1242":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1318":{ + "mul_d2__U1244":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1320":{ + "mul_d3__U1246":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1322":{ + "mul_d4__U1248":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1324":{ + "mul_d5__U1250":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U1326":{ + "mul_d6__U1252":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U1328":{ + "mul_d7__U1254":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U1330":{ + "mul_d8__U1256":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1314.out","add_all__U1332.in0"], - ["mul_d1__U1316.out","add_all__U1332.in1"], - ["add_all__U1333.in0","add_all__U1332.out"], - ["mul_d2__U1318.out","add_all__U1333.in1"], - ["add_all__U1334.in0","add_all__U1333.out"], - ["mul_d3__U1320.out","add_all__U1334.in1"], - ["add_all__U1335.in0","add_all__U1334.out"], - ["mul_d4__U1322.out","add_all__U1335.in1"], - ["add_all__U1336.in0","add_all__U1335.out"], - ["mul_d5__U1324.out","add_all__U1336.in1"], - ["add_all__U1337.in0","add_all__U1336.out"], - ["mul_d6__U1326.out","add_all__U1337.in1"], - ["add_all__U1338.in0","add_all__U1337.out"], - ["mul_d7__U1328.out","add_all__U1338.in1"], - ["add_all__U1339.in0","add_all__U1338.out"], - ["mul_d8__U1330.out","add_all__U1339.in1"], - ["add_all__U1340.in0","add_all__U1339.out"], - ["const_term_U1331.out","add_all__U1340.in1"], - ["self.out","add_all__U1340.out"], - ["mul_d0__U1314.in0","coeff_0_U1313.out"], - ["mul_d1__U1316.in0","coeff_1_U1315.out"], - ["mul_d2__U1318.in0","coeff_2_U1317.out"], - ["mul_d3__U1320.in0","coeff_3_U1319.out"], - ["mul_d4__U1322.in0","coeff_4_U1321.out"], - ["mul_d5__U1324.in0","coeff_5_U1323.out"], - ["mul_d6__U1326.in0","coeff_6_U1325.out"], - ["mul_d7__U1328.in0","coeff_7_U1327.out"], - ["mul_d8__U1330.in0","coeff_8_U1329.out"], - ["self.d.0","mul_d0__U1314.in1"], - ["self.d.1","mul_d1__U1316.in1"], - ["self.d.2","mul_d2__U1318.in1"], - ["self.d.3","mul_d3__U1320.in1"], - ["self.d.4","mul_d4__U1322.in1"], - ["self.d.5","mul_d5__U1324.in1"], - ["self.d.6","mul_d6__U1326.in1"], - ["self.d.7","mul_d7__U1328.in1"], - ["self.d.8","mul_d8__U1330.in1"] + ["mul_d0__U1240.out","add_all__U1258.in0"], + ["mul_d1__U1242.out","add_all__U1258.in1"], + ["add_all__U1259.in0","add_all__U1258.out"], + ["mul_d2__U1244.out","add_all__U1259.in1"], + ["add_all__U1260.in0","add_all__U1259.out"], + ["mul_d3__U1246.out","add_all__U1260.in1"], + ["add_all__U1261.in0","add_all__U1260.out"], + ["mul_d4__U1248.out","add_all__U1261.in1"], + ["add_all__U1262.in0","add_all__U1261.out"], + ["mul_d5__U1250.out","add_all__U1262.in1"], + ["add_all__U1263.in0","add_all__U1262.out"], + ["mul_d6__U1252.out","add_all__U1263.in1"], + ["add_all__U1264.in0","add_all__U1263.out"], + ["mul_d7__U1254.out","add_all__U1264.in1"], + ["add_all__U1265.in0","add_all__U1264.out"], + ["mul_d8__U1256.out","add_all__U1265.in1"], + ["add_all__U1266.in0","add_all__U1265.out"], + ["const_term_U1257.out","add_all__U1266.in1"], + ["self.out","add_all__U1266.out"], + ["mul_d0__U1240.in0","coeff_0_U1239.out"], + ["mul_d1__U1242.in0","coeff_1_U1241.out"], + ["mul_d2__U1244.in0","coeff_2_U1243.out"], + ["mul_d3__U1246.in0","coeff_3_U1245.out"], + ["mul_d4__U1248.in0","coeff_4_U1247.out"], + ["mul_d5__U1250.in0","coeff_5_U1249.out"], + ["mul_d6__U1252.in0","coeff_6_U1251.out"], + ["mul_d7__U1254.in0","coeff_7_U1253.out"], + ["mul_d8__U1256.in0","coeff_8_U1255.out"], + ["self.d.0","mul_d0__U1240.in1"], + ["self.d.1","mul_d1__U1242.in1"], + ["self.d.2","mul_d2__U1244.in1"], + ["self.d.3","mul_d3__U1246.in1"], + ["self.d.4","mul_d4__U1248.in1"], + ["self.d.5","mul_d5__U1250.in1"], + ["self.d.6","mul_d6__U1252.in1"], + ["self.d.7","mul_d7__U1254.in1"], + ["self.d.8","mul_d8__U1256.in1"] ] }, - "aff__U1345":{ + "aff__U1271":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1351":{ + "add_all__U1277":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1352":{ + "add_all__U1278":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1346":{ + "coeff_0_U1272":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1348":{ + "coeff_1_U1274":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1350":{ + "const_term_U1276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1347":{ + "mul_d0__U1273":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1349":{ + "mul_d1__U1275":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1347.out","add_all__U1351.in0"], - ["mul_d1__U1349.out","add_all__U1351.in1"], - ["add_all__U1352.in0","add_all__U1351.out"], - ["const_term_U1350.out","add_all__U1352.in1"], - ["self.out","add_all__U1352.out"], - ["mul_d0__U1347.in0","coeff_0_U1346.out"], - ["mul_d1__U1349.in0","coeff_1_U1348.out"], - ["self.d.0","mul_d0__U1347.in1"], - ["self.d.1","mul_d1__U1349.in1"] + ["mul_d0__U1273.out","add_all__U1277.in0"], + ["mul_d1__U1275.out","add_all__U1277.in1"], + ["add_all__U1278.in0","add_all__U1277.out"], + ["const_term_U1276.out","add_all__U1278.in1"], + ["self.out","add_all__U1278.out"], + ["mul_d0__U1273.in0","coeff_0_U1272.out"], + ["mul_d1__U1275.in0","coeff_1_U1274.out"], + ["self.d.0","mul_d0__U1273.in1"], + ["self.d.1","mul_d1__U1275.in1"] ] }, - "aff__U1360":{ + "aff__U1285":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1366":{ + "add_all__U1291":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1367":{ + "add_all__U1292":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1361":{ + "coeff_0_U1286":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1363":{ + "coeff_1_U1288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1365":{ + "const_term_U1290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1362":{ + "mul_d0__U1287":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1364":{ + "mul_d1__U1289":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1362.out","add_all__U1366.in0"], - ["mul_d1__U1364.out","add_all__U1366.in1"], - ["add_all__U1367.in0","add_all__U1366.out"], - ["const_term_U1365.out","add_all__U1367.in1"], - ["self.out","add_all__U1367.out"], - ["mul_d0__U1362.in0","coeff_0_U1361.out"], - ["mul_d1__U1364.in0","coeff_1_U1363.out"], - ["self.d.0","mul_d0__U1362.in1"], - ["self.d.1","mul_d1__U1364.in1"] + ["mul_d0__U1287.out","add_all__U1291.in0"], + ["mul_d1__U1289.out","add_all__U1291.in1"], + ["add_all__U1292.in0","add_all__U1291.out"], + ["const_term_U1290.out","add_all__U1292.in1"], + ["self.out","add_all__U1292.out"], + ["mul_d0__U1287.in0","coeff_0_U1286.out"], + ["mul_d1__U1289.in0","coeff_1_U1288.out"], + ["self.d.0","mul_d0__U1287.in1"], + ["self.d.1","mul_d1__U1289.in1"] ] }, - "aff__U1375":{ + "aff__U1299":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1381":{ + "add_all__U1305":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1382":{ + "add_all__U1306":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1376":{ + "coeff_0_U1300":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1378":{ + "coeff_1_U1302":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1380":{ + "const_term_U1304":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1377":{ + "mul_d0__U1301":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1379":{ + "mul_d1__U1303":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1377.out","add_all__U1381.in0"], - ["mul_d1__U1379.out","add_all__U1381.in1"], - ["add_all__U1382.in0","add_all__U1381.out"], - ["const_term_U1380.out","add_all__U1382.in1"], - ["self.out","add_all__U1382.out"], - ["mul_d0__U1377.in0","coeff_0_U1376.out"], - ["mul_d1__U1379.in0","coeff_1_U1378.out"], - ["self.d.0","mul_d0__U1377.in1"], - ["self.d.1","mul_d1__U1379.in1"] + ["mul_d0__U1301.out","add_all__U1305.in0"], + ["mul_d1__U1303.out","add_all__U1305.in1"], + ["add_all__U1306.in0","add_all__U1305.out"], + ["const_term_U1304.out","add_all__U1306.in1"], + ["self.out","add_all__U1306.out"], + ["mul_d0__U1301.in0","coeff_0_U1300.out"], + ["mul_d1__U1303.in0","coeff_1_U1302.out"], + ["self.d.0","mul_d0__U1301.in1"], + ["self.d.1","mul_d1__U1303.in1"] ] }, - "aff__U1390":{ + "aff__U1313":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1396":{ + "add_all__U1319":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1397":{ + "add_all__U1320":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1391":{ + "coeff_0_U1314":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1393":{ + "coeff_1_U1316":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1395":{ + "const_term_U1318":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1392":{ + "mul_d0__U1315":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1394":{ + "mul_d1__U1317":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1392.out","add_all__U1396.in0"], - ["mul_d1__U1394.out","add_all__U1396.in1"], - ["add_all__U1397.in0","add_all__U1396.out"], - ["const_term_U1395.out","add_all__U1397.in1"], - ["self.out","add_all__U1397.out"], - ["mul_d0__U1392.in0","coeff_0_U1391.out"], - ["mul_d1__U1394.in0","coeff_1_U1393.out"], - ["self.d.0","mul_d0__U1392.in1"], - ["self.d.1","mul_d1__U1394.in1"] + ["mul_d0__U1315.out","add_all__U1319.in0"], + ["mul_d1__U1317.out","add_all__U1319.in1"], + ["add_all__U1320.in0","add_all__U1319.out"], + ["const_term_U1318.out","add_all__U1320.in1"], + ["self.out","add_all__U1320.out"], + ["mul_d0__U1315.in0","coeff_0_U1314.out"], + ["mul_d1__U1317.in0","coeff_1_U1316.out"], + ["self.d.0","mul_d0__U1315.in1"], + ["self.d.1","mul_d1__U1317.in1"] ] }, - "aff__U1405":{ + "aff__U1327":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1411":{ + "add_all__U1333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1412":{ + "add_all__U1334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1406":{ + "coeff_0_U1328":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1408":{ + "coeff_1_U1330":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1410":{ + "const_term_U1332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1407":{ + "mul_d0__U1329":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1409":{ + "mul_d1__U1331":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1407.out","add_all__U1411.in0"], - ["mul_d1__U1409.out","add_all__U1411.in1"], - ["add_all__U1412.in0","add_all__U1411.out"], - ["const_term_U1410.out","add_all__U1412.in1"], - ["self.out","add_all__U1412.out"], - ["mul_d0__U1407.in0","coeff_0_U1406.out"], - ["mul_d1__U1409.in0","coeff_1_U1408.out"], - ["self.d.0","mul_d0__U1407.in1"], - ["self.d.1","mul_d1__U1409.in1"] + ["mul_d0__U1329.out","add_all__U1333.in0"], + ["mul_d1__U1331.out","add_all__U1333.in1"], + ["add_all__U1334.in0","add_all__U1333.out"], + ["const_term_U1332.out","add_all__U1334.in1"], + ["self.out","add_all__U1334.out"], + ["mul_d0__U1329.in0","coeff_0_U1328.out"], + ["mul_d1__U1331.in0","coeff_1_U1330.out"], + ["self.d.0","mul_d0__U1329.in1"], + ["self.d.1","mul_d1__U1331.in1"] ] }, - "aff__U1420":{ + "aff__U1341":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1426":{ + "add_all__U1347":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1427":{ + "add_all__U1348":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1421":{ + "coeff_0_U1342":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1423":{ + "coeff_1_U1344":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1425":{ + "const_term_U1346":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1422":{ + "mul_d0__U1343":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1424":{ + "mul_d1__U1345":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1422.out","add_all__U1426.in0"], - ["mul_d1__U1424.out","add_all__U1426.in1"], - ["add_all__U1427.in0","add_all__U1426.out"], - ["const_term_U1425.out","add_all__U1427.in1"], - ["self.out","add_all__U1427.out"], - ["mul_d0__U1422.in0","coeff_0_U1421.out"], - ["mul_d1__U1424.in0","coeff_1_U1423.out"], - ["self.d.0","mul_d0__U1422.in1"], - ["self.d.1","mul_d1__U1424.in1"] + ["mul_d0__U1343.out","add_all__U1347.in0"], + ["mul_d1__U1345.out","add_all__U1347.in1"], + ["add_all__U1348.in0","add_all__U1347.out"], + ["const_term_U1346.out","add_all__U1348.in1"], + ["self.out","add_all__U1348.out"], + ["mul_d0__U1343.in0","coeff_0_U1342.out"], + ["mul_d1__U1345.in0","coeff_1_U1344.out"], + ["self.d.0","mul_d0__U1343.in1"], + ["self.d.1","mul_d1__U1345.in1"] ] }, - "aff__U1435":{ + "aff__U1355":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1441":{ + "add_all__U1361":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1442":{ + "add_all__U1362":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1436":{ + "coeff_0_U1356":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1438":{ + "coeff_1_U1358":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1440":{ + "const_term_U1360":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1437":{ + "mul_d0__U1357":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1439":{ + "mul_d1__U1359":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1437.out","add_all__U1441.in0"], - ["mul_d1__U1439.out","add_all__U1441.in1"], - ["add_all__U1442.in0","add_all__U1441.out"], - ["const_term_U1440.out","add_all__U1442.in1"], - ["self.out","add_all__U1442.out"], - ["mul_d0__U1437.in0","coeff_0_U1436.out"], - ["mul_d1__U1439.in0","coeff_1_U1438.out"], - ["self.d.0","mul_d0__U1437.in1"], - ["self.d.1","mul_d1__U1439.in1"] + ["mul_d0__U1357.out","add_all__U1361.in0"], + ["mul_d1__U1359.out","add_all__U1361.in1"], + ["add_all__U1362.in0","add_all__U1361.out"], + ["const_term_U1360.out","add_all__U1362.in1"], + ["self.out","add_all__U1362.out"], + ["mul_d0__U1357.in0","coeff_0_U1356.out"], + ["mul_d1__U1359.in0","coeff_1_U1358.out"], + ["self.d.0","mul_d0__U1357.in1"], + ["self.d.1","mul_d1__U1359.in1"] ] }, - "aff__U145":{ + "aff__U136":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U155":{ + "add_all__U146":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U156":{ + "add_all__U147":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U157":{ + "add_all__U148":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U158":{ + "add_all__U149":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U146":{ + "coeff_0_U137":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U148":{ + "coeff_1_U139":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U150":{ + "coeff_2_U141":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_3_U152":{ + "coeff_3_U143":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000051"]} }, - "const_term_U154":{ + "const_term_U145":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U147":{ + "mul_d0__U138":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U149":{ + "mul_d1__U140":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U151":{ + "mul_d2__U142":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U153":{ + "mul_d3__U144":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U147.out","add_all__U155.in0"], - ["mul_d1__U149.out","add_all__U155.in1"], - ["add_all__U156.in0","add_all__U155.out"], - ["mul_d2__U151.out","add_all__U156.in1"], - ["add_all__U157.in0","add_all__U156.out"], - ["mul_d3__U153.out","add_all__U157.in1"], - ["add_all__U158.in0","add_all__U157.out"], - ["const_term_U154.out","add_all__U158.in1"], - ["self.out","add_all__U158.out"], - ["mul_d0__U147.in0","coeff_0_U146.out"], - ["mul_d1__U149.in0","coeff_1_U148.out"], - ["mul_d2__U151.in0","coeff_2_U150.out"], - ["mul_d3__U153.in0","coeff_3_U152.out"], - ["self.d.0","mul_d0__U147.in1"], - ["self.d.1","mul_d1__U149.in1"], - ["self.d.2","mul_d2__U151.in1"], - ["self.d.3","mul_d3__U153.in1"] + ["mul_d0__U138.out","add_all__U146.in0"], + ["mul_d1__U140.out","add_all__U146.in1"], + ["add_all__U147.in0","add_all__U146.out"], + ["mul_d2__U142.out","add_all__U147.in1"], + ["add_all__U148.in0","add_all__U147.out"], + ["mul_d3__U144.out","add_all__U148.in1"], + ["add_all__U149.in0","add_all__U148.out"], + ["const_term_U145.out","add_all__U149.in1"], + ["self.out","add_all__U149.out"], + ["mul_d0__U138.in0","coeff_0_U137.out"], + ["mul_d1__U140.in0","coeff_1_U139.out"], + ["mul_d2__U142.in0","coeff_2_U141.out"], + ["mul_d3__U144.in0","coeff_3_U143.out"], + ["self.d.0","mul_d0__U138.in1"], + ["self.d.1","mul_d1__U140.in1"], + ["self.d.2","mul_d2__U142.in1"], + ["self.d.3","mul_d3__U144.in1"] ] }, - "aff__U1450":{ + "aff__U1369":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1456":{ + "add_all__U1375":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1457":{ + "add_all__U1376":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1451":{ + "coeff_0_U1370":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1453":{ + "coeff_1_U1372":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1455":{ + "const_term_U1374":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1452":{ + "mul_d0__U1371":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1454":{ + "mul_d1__U1373":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1452.out","add_all__U1456.in0"], - ["mul_d1__U1454.out","add_all__U1456.in1"], - ["add_all__U1457.in0","add_all__U1456.out"], - ["const_term_U1455.out","add_all__U1457.in1"], - ["self.out","add_all__U1457.out"], - ["mul_d0__U1452.in0","coeff_0_U1451.out"], - ["mul_d1__U1454.in0","coeff_1_U1453.out"], - ["self.d.0","mul_d0__U1452.in1"], - ["self.d.1","mul_d1__U1454.in1"] + ["mul_d0__U1371.out","add_all__U1375.in0"], + ["mul_d1__U1373.out","add_all__U1375.in1"], + ["add_all__U1376.in0","add_all__U1375.out"], + ["const_term_U1374.out","add_all__U1376.in1"], + ["self.out","add_all__U1376.out"], + ["mul_d0__U1371.in0","coeff_0_U1370.out"], + ["mul_d1__U1373.in0","coeff_1_U1372.out"], + ["self.d.0","mul_d0__U1371.in1"], + ["self.d.1","mul_d1__U1373.in1"] ] }, - "aff__U1465":{ + "aff__U1382":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1479":{ + "add_all__U1396":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1480":{ + "add_all__U1397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1481":{ + "add_all__U1398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1482":{ + "add_all__U1399":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1483":{ + "add_all__U1400":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1484":{ + "add_all__U1401":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1466":{ + "coeff_0_U1383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1468":{ + "coeff_1_U1385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U1470":{ + "coeff_2_U1387":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_3_U1472":{ + "coeff_3_U1389":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U1474":{ + "coeff_4_U1391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U1476":{ + "coeff_5_U1393":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1478":{ + "const_term_U1395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0001e720"]} }, - "mul_d0__U1467":{ + "mul_d0__U1384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1469":{ + "mul_d1__U1386":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1471":{ + "mul_d2__U1388":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1473":{ + "mul_d3__U1390":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1475":{ + "mul_d4__U1392":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1477":{ + "mul_d5__U1394":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1467.out","add_all__U1479.in0"], - ["mul_d1__U1469.out","add_all__U1479.in1"], - ["add_all__U1480.in0","add_all__U1479.out"], - ["mul_d2__U1471.out","add_all__U1480.in1"], - ["add_all__U1481.in0","add_all__U1480.out"], - ["mul_d3__U1473.out","add_all__U1481.in1"], - ["add_all__U1482.in0","add_all__U1481.out"], - ["mul_d4__U1475.out","add_all__U1482.in1"], - ["add_all__U1483.in0","add_all__U1482.out"], - ["mul_d5__U1477.out","add_all__U1483.in1"], - ["add_all__U1484.in0","add_all__U1483.out"], - ["const_term_U1478.out","add_all__U1484.in1"], - ["self.out","add_all__U1484.out"], - ["mul_d0__U1467.in0","coeff_0_U1466.out"], - ["mul_d1__U1469.in0","coeff_1_U1468.out"], - ["mul_d2__U1471.in0","coeff_2_U1470.out"], - ["mul_d3__U1473.in0","coeff_3_U1472.out"], - ["mul_d4__U1475.in0","coeff_4_U1474.out"], - ["mul_d5__U1477.in0","coeff_5_U1476.out"], - ["self.d.0","mul_d0__U1467.in1"], - ["self.d.1","mul_d1__U1469.in1"], - ["self.d.2","mul_d2__U1471.in1"], - ["self.d.3","mul_d3__U1473.in1"], - ["self.d.4","mul_d4__U1475.in1"], - ["self.d.5","mul_d5__U1477.in1"] + ["mul_d0__U1384.out","add_all__U1396.in0"], + ["mul_d1__U1386.out","add_all__U1396.in1"], + ["add_all__U1397.in0","add_all__U1396.out"], + ["mul_d2__U1388.out","add_all__U1397.in1"], + ["add_all__U1398.in0","add_all__U1397.out"], + ["mul_d3__U1390.out","add_all__U1398.in1"], + ["add_all__U1399.in0","add_all__U1398.out"], + ["mul_d4__U1392.out","add_all__U1399.in1"], + ["add_all__U1400.in0","add_all__U1399.out"], + ["mul_d5__U1394.out","add_all__U1400.in1"], + ["add_all__U1401.in0","add_all__U1400.out"], + ["const_term_U1395.out","add_all__U1401.in1"], + ["self.out","add_all__U1401.out"], + ["mul_d0__U1384.in0","coeff_0_U1383.out"], + ["mul_d1__U1386.in0","coeff_1_U1385.out"], + ["mul_d2__U1388.in0","coeff_2_U1387.out"], + ["mul_d3__U1390.in0","coeff_3_U1389.out"], + ["mul_d4__U1392.in0","coeff_4_U1391.out"], + ["mul_d5__U1394.in0","coeff_5_U1393.out"], + ["self.d.0","mul_d0__U1384.in1"], + ["self.d.1","mul_d1__U1386.in1"], + ["self.d.2","mul_d2__U1388.in1"], + ["self.d.3","mul_d3__U1390.in1"], + ["self.d.4","mul_d4__U1392.in1"], + ["self.d.5","mul_d5__U1394.in1"] ] }, - "aff__U1503":{ + "aff__U1420":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1517":{ + "add_all__U1434":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1518":{ + "add_all__U1435":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1519":{ + "add_all__U1436":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1520":{ + "add_all__U1437":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1521":{ + "add_all__U1438":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1522":{ + "add_all__U1439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1504":{ + "coeff_0_U1421":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1506":{ + "coeff_1_U1423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c40"]} }, - "coeff_2_U1508":{ + "coeff_2_U1425":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U1510":{ + "coeff_3_U1427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_4_U1512":{ + "coeff_4_U1429":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_5_U1514":{ + "coeff_5_U1431":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U1516":{ + "const_term_U1433":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1505":{ + "mul_d0__U1422":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1507":{ + "mul_d1__U1424":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1509":{ + "mul_d2__U1426":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1511":{ + "mul_d3__U1428":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1513":{ + "mul_d4__U1430":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1515":{ + "mul_d5__U1432":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1505.out","add_all__U1517.in0"], - ["mul_d1__U1507.out","add_all__U1517.in1"], - ["add_all__U1518.in0","add_all__U1517.out"], - ["mul_d2__U1509.out","add_all__U1518.in1"], - ["add_all__U1519.in0","add_all__U1518.out"], - ["mul_d3__U1511.out","add_all__U1519.in1"], - ["add_all__U1520.in0","add_all__U1519.out"], - ["mul_d4__U1513.out","add_all__U1520.in1"], - ["add_all__U1521.in0","add_all__U1520.out"], - ["mul_d5__U1515.out","add_all__U1521.in1"], - ["add_all__U1522.in0","add_all__U1521.out"], - ["const_term_U1516.out","add_all__U1522.in1"], - ["self.out","add_all__U1522.out"], - ["mul_d0__U1505.in0","coeff_0_U1504.out"], - ["mul_d1__U1507.in0","coeff_1_U1506.out"], - ["mul_d2__U1509.in0","coeff_2_U1508.out"], - ["mul_d3__U1511.in0","coeff_3_U1510.out"], - ["mul_d4__U1513.in0","coeff_4_U1512.out"], - ["mul_d5__U1515.in0","coeff_5_U1514.out"], - ["self.d.0","mul_d0__U1505.in1"], - ["self.d.1","mul_d1__U1507.in1"], - ["self.d.2","mul_d2__U1509.in1"], - ["self.d.3","mul_d3__U1511.in1"], - ["self.d.4","mul_d4__U1513.in1"], - ["self.d.5","mul_d5__U1515.in1"] + ["mul_d0__U1422.out","add_all__U1434.in0"], + ["mul_d1__U1424.out","add_all__U1434.in1"], + ["add_all__U1435.in0","add_all__U1434.out"], + ["mul_d2__U1426.out","add_all__U1435.in1"], + ["add_all__U1436.in0","add_all__U1435.out"], + ["mul_d3__U1428.out","add_all__U1436.in1"], + ["add_all__U1437.in0","add_all__U1436.out"], + ["mul_d4__U1430.out","add_all__U1437.in1"], + ["add_all__U1438.in0","add_all__U1437.out"], + ["mul_d5__U1432.out","add_all__U1438.in1"], + ["add_all__U1439.in0","add_all__U1438.out"], + ["const_term_U1433.out","add_all__U1439.in1"], + ["self.out","add_all__U1439.out"], + ["mul_d0__U1422.in0","coeff_0_U1421.out"], + ["mul_d1__U1424.in0","coeff_1_U1423.out"], + ["mul_d2__U1426.in0","coeff_2_U1425.out"], + ["mul_d3__U1428.in0","coeff_3_U1427.out"], + ["mul_d4__U1430.in0","coeff_4_U1429.out"], + ["mul_d5__U1432.in0","coeff_5_U1431.out"], + ["self.d.0","mul_d0__U1422.in1"], + ["self.d.1","mul_d1__U1424.in1"], + ["self.d.2","mul_d2__U1426.in1"], + ["self.d.3","mul_d3__U1428.in1"], + ["self.d.4","mul_d4__U1430.in1"], + ["self.d.5","mul_d5__U1432.in1"] ] }, - "aff__U1525":{ + "aff__U1442":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1535":{ + "add_all__U1452":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1536":{ + "add_all__U1453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1537":{ + "add_all__U1454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1538":{ + "add_all__U1455":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1526":{ + "coeff_0_U1443":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1528":{ + "coeff_1_U1445":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U1530":{ + "coeff_2_U1447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_3_U1532":{ + "coeff_3_U1449":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1534":{ + "const_term_U1451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002835f"]} }, - "mul_d0__U1527":{ + "mul_d0__U1444":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1529":{ + "mul_d1__U1446":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1531":{ + "mul_d2__U1448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1533":{ + "mul_d3__U1450":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1527.out","add_all__U1535.in0"], - ["mul_d1__U1529.out","add_all__U1535.in1"], - ["add_all__U1536.in0","add_all__U1535.out"], - ["mul_d2__U1531.out","add_all__U1536.in1"], - ["add_all__U1537.in0","add_all__U1536.out"], - ["mul_d3__U1533.out","add_all__U1537.in1"], - ["add_all__U1538.in0","add_all__U1537.out"], - ["const_term_U1534.out","add_all__U1538.in1"], - ["self.out","add_all__U1538.out"], - ["mul_d0__U1527.in0","coeff_0_U1526.out"], - ["mul_d1__U1529.in0","coeff_1_U1528.out"], - ["mul_d2__U1531.in0","coeff_2_U1530.out"], - ["mul_d3__U1533.in0","coeff_3_U1532.out"], - ["self.d.0","mul_d0__U1527.in1"], - ["self.d.1","mul_d1__U1529.in1"], - ["self.d.2","mul_d2__U1531.in1"], - ["self.d.3","mul_d3__U1533.in1"] + ["mul_d0__U1444.out","add_all__U1452.in0"], + ["mul_d1__U1446.out","add_all__U1452.in1"], + ["add_all__U1453.in0","add_all__U1452.out"], + ["mul_d2__U1448.out","add_all__U1453.in1"], + ["add_all__U1454.in0","add_all__U1453.out"], + ["mul_d3__U1450.out","add_all__U1454.in1"], + ["add_all__U1455.in0","add_all__U1454.out"], + ["const_term_U1451.out","add_all__U1455.in1"], + ["self.out","add_all__U1455.out"], + ["mul_d0__U1444.in0","coeff_0_U1443.out"], + ["mul_d1__U1446.in0","coeff_1_U1445.out"], + ["mul_d2__U1448.in0","coeff_2_U1447.out"], + ["mul_d3__U1450.in0","coeff_3_U1449.out"], + ["self.d.0","mul_d0__U1444.in1"], + ["self.d.1","mul_d1__U1446.in1"], + ["self.d.2","mul_d2__U1448.in1"], + ["self.d.3","mul_d3__U1450.in1"] ] }, - "aff__U1548":{ + "aff__U1465":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1558":{ + "add_all__U1475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1559":{ + "add_all__U1476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1560":{ + "add_all__U1477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1561":{ + "add_all__U1478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1549":{ + "coeff_0_U1466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1551":{ + "coeff_1_U1468":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U1553":{ + "coeff_2_U1470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_3_U1555":{ + "coeff_3_U1472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U1557":{ + "const_term_U1474":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1550":{ + "mul_d0__U1467":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1552":{ + "mul_d1__U1469":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1554":{ + "mul_d2__U1471":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1556":{ + "mul_d3__U1473":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1550.out","add_all__U1558.in0"], - ["mul_d1__U1552.out","add_all__U1558.in1"], - ["add_all__U1559.in0","add_all__U1558.out"], - ["mul_d2__U1554.out","add_all__U1559.in1"], - ["add_all__U1560.in0","add_all__U1559.out"], - ["mul_d3__U1556.out","add_all__U1560.in1"], - ["add_all__U1561.in0","add_all__U1560.out"], - ["const_term_U1557.out","add_all__U1561.in1"], - ["self.out","add_all__U1561.out"], - ["mul_d0__U1550.in0","coeff_0_U1549.out"], - ["mul_d1__U1552.in0","coeff_1_U1551.out"], - ["mul_d2__U1554.in0","coeff_2_U1553.out"], - ["mul_d3__U1556.in0","coeff_3_U1555.out"], - ["self.d.0","mul_d0__U1550.in1"], - ["self.d.1","mul_d1__U1552.in1"], - ["self.d.2","mul_d2__U1554.in1"], - ["self.d.3","mul_d3__U1556.in1"] + ["mul_d0__U1467.out","add_all__U1475.in0"], + ["mul_d1__U1469.out","add_all__U1475.in1"], + ["add_all__U1476.in0","add_all__U1475.out"], + ["mul_d2__U1471.out","add_all__U1476.in1"], + ["add_all__U1477.in0","add_all__U1476.out"], + ["mul_d3__U1473.out","add_all__U1477.in1"], + ["add_all__U1478.in0","add_all__U1477.out"], + ["const_term_U1474.out","add_all__U1478.in1"], + ["self.out","add_all__U1478.out"], + ["mul_d0__U1467.in0","coeff_0_U1466.out"], + ["mul_d1__U1469.in0","coeff_1_U1468.out"], + ["mul_d2__U1471.in0","coeff_2_U1470.out"], + ["mul_d3__U1473.in0","coeff_3_U1472.out"], + ["self.d.0","mul_d0__U1467.in1"], + ["self.d.1","mul_d1__U1469.in1"], + ["self.d.2","mul_d2__U1471.in1"], + ["self.d.3","mul_d3__U1473.in1"] ] }, - "aff__U1565":{ + "aff__U1482":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1575":{ + "add_all__U1492":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1576":{ + "add_all__U1493":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1577":{ + "add_all__U1494":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1578":{ + "add_all__U1495":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1566":{ + "coeff_0_U1483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1568":{ + "coeff_1_U1485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U1570":{ + "coeff_2_U1487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_3_U1572":{ + "coeff_3_U1489":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1574":{ + "const_term_U1491":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00028360"]} }, - "mul_d0__U1567":{ + "mul_d0__U1484":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1569":{ + "mul_d1__U1486":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1571":{ + "mul_d2__U1488":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1573":{ + "mul_d3__U1490":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1567.out","add_all__U1575.in0"], - ["mul_d1__U1569.out","add_all__U1575.in1"], - ["add_all__U1576.in0","add_all__U1575.out"], - ["mul_d2__U1571.out","add_all__U1576.in1"], - ["add_all__U1577.in0","add_all__U1576.out"], - ["mul_d3__U1573.out","add_all__U1577.in1"], - ["add_all__U1578.in0","add_all__U1577.out"], - ["const_term_U1574.out","add_all__U1578.in1"], - ["self.out","add_all__U1578.out"], - ["mul_d0__U1567.in0","coeff_0_U1566.out"], - ["mul_d1__U1569.in0","coeff_1_U1568.out"], - ["mul_d2__U1571.in0","coeff_2_U1570.out"], - ["mul_d3__U1573.in0","coeff_3_U1572.out"], - ["self.d.0","mul_d0__U1567.in1"], - ["self.d.1","mul_d1__U1569.in1"], - ["self.d.2","mul_d2__U1571.in1"], - ["self.d.3","mul_d3__U1573.in1"] + ["mul_d0__U1484.out","add_all__U1492.in0"], + ["mul_d1__U1486.out","add_all__U1492.in1"], + ["add_all__U1493.in0","add_all__U1492.out"], + ["mul_d2__U1488.out","add_all__U1493.in1"], + ["add_all__U1494.in0","add_all__U1493.out"], + ["mul_d3__U1490.out","add_all__U1494.in1"], + ["add_all__U1495.in0","add_all__U1494.out"], + ["const_term_U1491.out","add_all__U1495.in1"], + ["self.out","add_all__U1495.out"], + ["mul_d0__U1484.in0","coeff_0_U1483.out"], + ["mul_d1__U1486.in0","coeff_1_U1485.out"], + ["mul_d2__U1488.in0","coeff_2_U1487.out"], + ["mul_d3__U1490.in0","coeff_3_U1489.out"], + ["self.d.0","mul_d0__U1484.in1"], + ["self.d.1","mul_d1__U1486.in1"], + ["self.d.2","mul_d2__U1488.in1"], + ["self.d.3","mul_d3__U1490.in1"] ] }, - "aff__U161":{ + "aff__U152":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U177":{ + "add_all__U168":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U178":{ + "add_all__U169":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U179":{ + "add_all__U170":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U180":{ + "add_all__U171":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U181":{ + "add_all__U172":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U182":{ + "add_all__U173":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U183":{ + "add_all__U174":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U162":{ + "coeff_0_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U164":{ + "coeff_1_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U166":{ + "coeff_2_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004800"]} }, - "coeff_3_U168":{ + "coeff_3_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_4_U170":{ + "coeff_4_U161":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_5_U172":{ + "coeff_5_U163":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_6_U174":{ + "coeff_6_U165":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U176":{ + "const_term_U167":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00011fff"]} }, - "mul_d0__U163":{ + "mul_d0__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U165":{ + "mul_d1__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U167":{ + "mul_d2__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U169":{ + "mul_d3__U160":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U171":{ + "mul_d4__U162":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U173":{ + "mul_d5__U164":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U175":{ + "mul_d6__U166":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U163.out","add_all__U177.in0"], - ["mul_d1__U165.out","add_all__U177.in1"], - ["add_all__U178.in0","add_all__U177.out"], - ["mul_d2__U167.out","add_all__U178.in1"], - ["add_all__U179.in0","add_all__U178.out"], - ["mul_d3__U169.out","add_all__U179.in1"], - ["add_all__U180.in0","add_all__U179.out"], - ["mul_d4__U171.out","add_all__U180.in1"], - ["add_all__U181.in0","add_all__U180.out"], - ["mul_d5__U173.out","add_all__U181.in1"], - ["add_all__U182.in0","add_all__U181.out"], - ["mul_d6__U175.out","add_all__U182.in1"], - ["add_all__U183.in0","add_all__U182.out"], - ["const_term_U176.out","add_all__U183.in1"], - ["self.out","add_all__U183.out"], - ["mul_d0__U163.in0","coeff_0_U162.out"], - ["mul_d1__U165.in0","coeff_1_U164.out"], - ["mul_d2__U167.in0","coeff_2_U166.out"], - ["mul_d3__U169.in0","coeff_3_U168.out"], - ["mul_d4__U171.in0","coeff_4_U170.out"], - ["mul_d5__U173.in0","coeff_5_U172.out"], - ["mul_d6__U175.in0","coeff_6_U174.out"], - ["self.d.0","mul_d0__U163.in1"], - ["self.d.1","mul_d1__U165.in1"], - ["self.d.2","mul_d2__U167.in1"], - ["self.d.3","mul_d3__U169.in1"], - ["self.d.4","mul_d4__U171.in1"], - ["self.d.5","mul_d5__U173.in1"], - ["self.d.6","mul_d6__U175.in1"] + ["mul_d0__U154.out","add_all__U168.in0"], + ["mul_d1__U156.out","add_all__U168.in1"], + ["add_all__U169.in0","add_all__U168.out"], + ["mul_d2__U158.out","add_all__U169.in1"], + ["add_all__U170.in0","add_all__U169.out"], + ["mul_d3__U160.out","add_all__U170.in1"], + ["add_all__U171.in0","add_all__U170.out"], + ["mul_d4__U162.out","add_all__U171.in1"], + ["add_all__U172.in0","add_all__U171.out"], + ["mul_d5__U164.out","add_all__U172.in1"], + ["add_all__U173.in0","add_all__U172.out"], + ["mul_d6__U166.out","add_all__U173.in1"], + ["add_all__U174.in0","add_all__U173.out"], + ["const_term_U167.out","add_all__U174.in1"], + ["self.out","add_all__U174.out"], + ["mul_d0__U154.in0","coeff_0_U153.out"], + ["mul_d1__U156.in0","coeff_1_U155.out"], + ["mul_d2__U158.in0","coeff_2_U157.out"], + ["mul_d3__U160.in0","coeff_3_U159.out"], + ["mul_d4__U162.in0","coeff_4_U161.out"], + ["mul_d5__U164.in0","coeff_5_U163.out"], + ["mul_d6__U166.in0","coeff_6_U165.out"], + ["self.d.0","mul_d0__U154.in1"], + ["self.d.1","mul_d1__U156.in1"], + ["self.d.2","mul_d2__U158.in1"], + ["self.d.3","mul_d3__U160.in1"], + ["self.d.4","mul_d4__U162.in1"], + ["self.d.5","mul_d5__U164.in1"], + ["self.d.6","mul_d6__U166.in1"] ] }, - "aff__U17":{ + "aff__U16":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U23":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U24":{ + "add_all__U23":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U18":{ + "coeff_0_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U20":{ + "coeff_1_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U22":{ + "const_term_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U19":{ + "mul_d0__U18":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U21":{ + "mul_d1__U20":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U19.out","add_all__U23.in0"], - ["mul_d1__U21.out","add_all__U23.in1"], - ["add_all__U24.in0","add_all__U23.out"], - ["const_term_U22.out","add_all__U24.in1"], - ["self.out","add_all__U24.out"], - ["mul_d0__U19.in0","coeff_0_U18.out"], - ["mul_d1__U21.in0","coeff_1_U20.out"], - ["self.d.0","mul_d0__U19.in1"], - ["self.d.1","mul_d1__U21.in1"] + ["mul_d0__U18.out","add_all__U22.in0"], + ["mul_d1__U20.out","add_all__U22.in1"], + ["add_all__U23.in0","add_all__U22.out"], + ["const_term_U21.out","add_all__U23.in1"], + ["self.out","add_all__U23.out"], + ["mul_d0__U18.in0","coeff_0_U17.out"], + ["mul_d1__U20.in0","coeff_1_U19.out"], + ["self.d.0","mul_d0__U18.in1"], + ["self.d.1","mul_d1__U20.in1"] ] }, - "aff__U2":{ + "aff__U199":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] + ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U8":{ + "add_all__U215":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U9":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U3":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "add_all__U217":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "coeff_1_U5":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "add_all__U218":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U219":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U220":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U221":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U200":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U202":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_2_U204":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000a20"]} + }, + "coeff_3_U206":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "coeff_4_U208":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000009"]} + }, + "coeff_5_U210":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000288"]} + }, + "coeff_6_U212":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000051"]} + }, + "const_term_U214":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U201":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U203":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U205":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U207":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d4__U209":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d5__U211":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d6__U213":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U201.out","add_all__U215.in0"], + ["mul_d1__U203.out","add_all__U215.in1"], + ["add_all__U216.in0","add_all__U215.out"], + ["mul_d2__U205.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d3__U207.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d4__U209.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["mul_d5__U211.out","add_all__U219.in1"], + ["add_all__U220.in0","add_all__U219.out"], + ["mul_d6__U213.out","add_all__U220.in1"], + ["add_all__U221.in0","add_all__U220.out"], + ["const_term_U214.out","add_all__U221.in1"], + ["self.out","add_all__U221.out"], + ["mul_d0__U201.in0","coeff_0_U200.out"], + ["mul_d1__U203.in0","coeff_1_U202.out"], + ["mul_d2__U205.in0","coeff_2_U204.out"], + ["mul_d3__U207.in0","coeff_3_U206.out"], + ["mul_d4__U209.in0","coeff_4_U208.out"], + ["mul_d5__U211.in0","coeff_5_U210.out"], + ["mul_d6__U213.in0","coeff_6_U212.out"], + ["self.d.0","mul_d0__U201.in1"], + ["self.d.1","mul_d1__U203.in1"], + ["self.d.2","mul_d2__U205.in1"], + ["self.d.3","mul_d3__U207.in1"], + ["self.d.4","mul_d4__U209.in1"], + ["self.d.5","mul_d5__U211.in1"], + ["self.d.6","mul_d6__U213.in1"] + ] + }, + "aff__U2":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U8":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U9":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "const_term_U7":{ "genref":"coreir.const", @@ -2533,389 +2418,354 @@ ["self.d.1","mul_d1__U6.in1"] ] }, - "aff__U208":{ + "aff__U226":{ "type":["Record",[ ["out",["Array",32,"Bit"]], - ["d",["Array",7,["Array",32,"BitIn"]]] + ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U224":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U225":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U226":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U227":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U228":{ + "add_all__U232":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U229":{ + "add_all__U233":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U230":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U209":{ + "coeff_0_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U211":{ + "coeff_1_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U213":{ + "const_term_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000a20"]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "coeff_3_U215":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "mul_d0__U228":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "coeff_4_U217":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000009"]} + "mul_d1__U230":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U228.out","add_all__U232.in0"], + ["mul_d1__U230.out","add_all__U232.in1"], + ["add_all__U233.in0","add_all__U232.out"], + ["const_term_U231.out","add_all__U233.in1"], + ["self.out","add_all__U233.out"], + ["mul_d0__U228.in0","coeff_0_U227.out"], + ["mul_d1__U230.in0","coeff_1_U229.out"], + ["self.d.0","mul_d0__U228.in1"], + ["self.d.1","mul_d1__U230.in1"] + ] + }, + "aff__U240":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U246":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "coeff_5_U219":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000288"]} + "add_all__U247":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "coeff_6_U221":{ + "coeff_0_U241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000051"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U223":{ + "coeff_1_U243":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U210":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U212":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U214":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U216":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d4__U218":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "const_term_U245":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d5__U220":{ + "mul_d0__U242":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U222":{ + "mul_d1__U244":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U210.out","add_all__U224.in0"], - ["mul_d1__U212.out","add_all__U224.in1"], - ["add_all__U225.in0","add_all__U224.out"], - ["mul_d2__U214.out","add_all__U225.in1"], - ["add_all__U226.in0","add_all__U225.out"], - ["mul_d3__U216.out","add_all__U226.in1"], - ["add_all__U227.in0","add_all__U226.out"], - ["mul_d4__U218.out","add_all__U227.in1"], - ["add_all__U228.in0","add_all__U227.out"], - ["mul_d5__U220.out","add_all__U228.in1"], - ["add_all__U229.in0","add_all__U228.out"], - ["mul_d6__U222.out","add_all__U229.in1"], - ["add_all__U230.in0","add_all__U229.out"], - ["const_term_U223.out","add_all__U230.in1"], - ["self.out","add_all__U230.out"], - ["mul_d0__U210.in0","coeff_0_U209.out"], - ["mul_d1__U212.in0","coeff_1_U211.out"], - ["mul_d2__U214.in0","coeff_2_U213.out"], - ["mul_d3__U216.in0","coeff_3_U215.out"], - ["mul_d4__U218.in0","coeff_4_U217.out"], - ["mul_d5__U220.in0","coeff_5_U219.out"], - ["mul_d6__U222.in0","coeff_6_U221.out"], - ["self.d.0","mul_d0__U210.in1"], - ["self.d.1","mul_d1__U212.in1"], - ["self.d.2","mul_d2__U214.in1"], - ["self.d.3","mul_d3__U216.in1"], - ["self.d.4","mul_d4__U218.in1"], - ["self.d.5","mul_d5__U220.in1"], - ["self.d.6","mul_d6__U222.in1"] + ["mul_d0__U242.out","add_all__U246.in0"], + ["mul_d1__U244.out","add_all__U246.in1"], + ["add_all__U247.in0","add_all__U246.out"], + ["const_term_U245.out","add_all__U247.in1"], + ["self.out","add_all__U247.out"], + ["mul_d0__U242.in0","coeff_0_U241.out"], + ["mul_d1__U244.in0","coeff_1_U243.out"], + ["self.d.0","mul_d0__U242.in1"], + ["self.d.1","mul_d1__U244.in1"] ] }, - "aff__U235":{ + "aff__U254":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U241":{ + "add_all__U260":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U242":{ + "add_all__U261":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U236":{ + "coeff_0_U255":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U238":{ + "coeff_1_U257":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U240":{ + "const_term_U259":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U237":{ + "mul_d0__U256":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U239":{ + "mul_d1__U258":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U237.out","add_all__U241.in0"], - ["mul_d1__U239.out","add_all__U241.in1"], - ["add_all__U242.in0","add_all__U241.out"], - ["const_term_U240.out","add_all__U242.in1"], - ["self.out","add_all__U242.out"], - ["mul_d0__U237.in0","coeff_0_U236.out"], - ["mul_d1__U239.in0","coeff_1_U238.out"], - ["self.d.0","mul_d0__U237.in1"], - ["self.d.1","mul_d1__U239.in1"] + ["mul_d0__U256.out","add_all__U260.in0"], + ["mul_d1__U258.out","add_all__U260.in1"], + ["add_all__U261.in0","add_all__U260.out"], + ["const_term_U259.out","add_all__U261.in1"], + ["self.out","add_all__U261.out"], + ["mul_d0__U256.in0","coeff_0_U255.out"], + ["mul_d1__U258.in0","coeff_1_U257.out"], + ["self.d.0","mul_d0__U256.in1"], + ["self.d.1","mul_d1__U258.in1"] ] }, - "aff__U250":{ + "aff__U268":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U256":{ + "add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U257":{ + "add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U251":{ + "coeff_0_U269":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U253":{ + "coeff_1_U271":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U255":{ + "const_term_U273":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U252":{ + "mul_d0__U270":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U254":{ + "mul_d1__U272":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U252.out","add_all__U256.in0"], - ["mul_d1__U254.out","add_all__U256.in1"], - ["add_all__U257.in0","add_all__U256.out"], - ["const_term_U255.out","add_all__U257.in1"], - ["self.out","add_all__U257.out"], - ["mul_d0__U252.in0","coeff_0_U251.out"], - ["mul_d1__U254.in0","coeff_1_U253.out"], - ["self.d.0","mul_d0__U252.in1"], - ["self.d.1","mul_d1__U254.in1"] + ["mul_d0__U270.out","add_all__U274.in0"], + ["mul_d1__U272.out","add_all__U274.in1"], + ["add_all__U275.in0","add_all__U274.out"], + ["const_term_U273.out","add_all__U275.in1"], + ["self.out","add_all__U275.out"], + ["mul_d0__U270.in0","coeff_0_U269.out"], + ["mul_d1__U272.in0","coeff_1_U271.out"], + ["self.d.0","mul_d0__U270.in1"], + ["self.d.1","mul_d1__U272.in1"] ] }, - "aff__U265":{ + "aff__U282":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U271":{ + "add_all__U288":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U272":{ + "add_all__U289":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U266":{ + "coeff_0_U283":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U268":{ + "coeff_1_U285":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U270":{ + "const_term_U287":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U267":{ + "mul_d0__U284":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U269":{ + "mul_d1__U286":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U267.out","add_all__U271.in0"], - ["mul_d1__U269.out","add_all__U271.in1"], - ["add_all__U272.in0","add_all__U271.out"], - ["const_term_U270.out","add_all__U272.in1"], - ["self.out","add_all__U272.out"], - ["mul_d0__U267.in0","coeff_0_U266.out"], - ["mul_d1__U269.in0","coeff_1_U268.out"], - ["self.d.0","mul_d0__U267.in1"], - ["self.d.1","mul_d1__U269.in1"] + ["mul_d0__U284.out","add_all__U288.in0"], + ["mul_d1__U286.out","add_all__U288.in1"], + ["add_all__U289.in0","add_all__U288.out"], + ["const_term_U287.out","add_all__U289.in1"], + ["self.out","add_all__U289.out"], + ["mul_d0__U284.in0","coeff_0_U283.out"], + ["mul_d1__U286.in0","coeff_1_U285.out"], + ["self.d.0","mul_d0__U284.in1"], + ["self.d.1","mul_d1__U286.in1"] ] }, - "aff__U280":{ + "aff__U296":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U286":{ + "add_all__U302":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U287":{ + "add_all__U303":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U281":{ + "coeff_0_U297":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U283":{ + "coeff_1_U299":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U285":{ + "const_term_U301":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U282":{ + "mul_d0__U298":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U284":{ + "mul_d1__U300":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U282.out","add_all__U286.in0"], - ["mul_d1__U284.out","add_all__U286.in1"], - ["add_all__U287.in0","add_all__U286.out"], - ["const_term_U285.out","add_all__U287.in1"], - ["self.out","add_all__U287.out"], - ["mul_d0__U282.in0","coeff_0_U281.out"], - ["mul_d1__U284.in0","coeff_1_U283.out"], - ["self.d.0","mul_d0__U282.in1"], - ["self.d.1","mul_d1__U284.in1"] + ["mul_d0__U298.out","add_all__U302.in0"], + ["mul_d1__U300.out","add_all__U302.in1"], + ["add_all__U303.in0","add_all__U302.out"], + ["const_term_U301.out","add_all__U303.in1"], + ["self.out","add_all__U303.out"], + ["mul_d0__U298.in0","coeff_0_U297.out"], + ["mul_d1__U300.in0","coeff_1_U299.out"], + ["self.d.0","mul_d0__U298.in1"], + ["self.d.1","mul_d1__U300.in1"] ] }, - "aff__U295":{ + "aff__U30":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U301":{ + "add_all__U36":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U302":{ + "add_all__U37":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U296":{ + "coeff_0_U31":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U298":{ + "coeff_1_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U300":{ + "const_term_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U297":{ + "mul_d0__U32":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U299":{ + "mul_d1__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U297.out","add_all__U301.in0"], - ["mul_d1__U299.out","add_all__U301.in1"], - ["add_all__U302.in0","add_all__U301.out"], - ["const_term_U300.out","add_all__U302.in1"], - ["self.out","add_all__U302.out"], - ["mul_d0__U297.in0","coeff_0_U296.out"], - ["mul_d1__U299.in0","coeff_1_U298.out"], - ["self.d.0","mul_d0__U297.in1"], - ["self.d.1","mul_d1__U299.in1"] + ["mul_d0__U32.out","add_all__U36.in0"], + ["mul_d1__U34.out","add_all__U36.in1"], + ["add_all__U37.in0","add_all__U36.out"], + ["const_term_U35.out","add_all__U37.in1"], + ["self.out","add_all__U37.out"], + ["mul_d0__U32.in0","coeff_0_U31.out"], + ["mul_d1__U34.in0","coeff_1_U33.out"], + ["self.d.0","mul_d0__U32.in1"], + ["self.d.1","mul_d1__U34.in1"] ] }, "aff__U310":{ @@ -2968,754 +2818,754 @@ ["self.d.1","mul_d1__U314.in1"] ] }, - "aff__U32":{ + "aff__U324":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U38":{ + "add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U39":{ + "add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U33":{ + "coeff_0_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U35":{ + "coeff_1_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U37":{ + "const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U34":{ + "mul_d0__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U36":{ + "mul_d1__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U34.out","add_all__U38.in0"], - ["mul_d1__U36.out","add_all__U38.in1"], - ["add_all__U39.in0","add_all__U38.out"], - ["const_term_U37.out","add_all__U39.in1"], - ["self.out","add_all__U39.out"], - ["mul_d0__U34.in0","coeff_0_U33.out"], - ["mul_d1__U36.in0","coeff_1_U35.out"], - ["self.d.0","mul_d0__U34.in1"], - ["self.d.1","mul_d1__U36.in1"] + ["mul_d0__U326.out","add_all__U330.in0"], + ["mul_d1__U328.out","add_all__U330.in1"], + ["add_all__U331.in0","add_all__U330.out"], + ["const_term_U329.out","add_all__U331.in1"], + ["self.out","add_all__U331.out"], + ["mul_d0__U326.in0","coeff_0_U325.out"], + ["mul_d1__U328.in0","coeff_1_U327.out"], + ["self.d.0","mul_d0__U326.in1"], + ["self.d.1","mul_d1__U328.in1"] ] }, - "aff__U325":{ + "aff__U338":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U331":{ + "add_all__U344":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U332":{ + "add_all__U345":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U326":{ + "coeff_0_U339":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U328":{ + "coeff_1_U341":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U330":{ + "const_term_U343":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U327":{ + "mul_d0__U340":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U329":{ + "mul_d1__U342":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U327.out","add_all__U331.in0"], - ["mul_d1__U329.out","add_all__U331.in1"], - ["add_all__U332.in0","add_all__U331.out"], - ["const_term_U330.out","add_all__U332.in1"], - ["self.out","add_all__U332.out"], - ["mul_d0__U327.in0","coeff_0_U326.out"], - ["mul_d1__U329.in0","coeff_1_U328.out"], - ["self.d.0","mul_d0__U327.in1"], - ["self.d.1","mul_d1__U329.in1"] + ["mul_d0__U340.out","add_all__U344.in0"], + ["mul_d1__U342.out","add_all__U344.in1"], + ["add_all__U345.in0","add_all__U344.out"], + ["const_term_U343.out","add_all__U345.in1"], + ["self.out","add_all__U345.out"], + ["mul_d0__U340.in0","coeff_0_U339.out"], + ["mul_d1__U342.in0","coeff_1_U341.out"], + ["self.d.0","mul_d0__U340.in1"], + ["self.d.1","mul_d1__U342.in1"] ] }, - "aff__U340":{ + "aff__U352":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U346":{ + "add_all__U358":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U347":{ + "add_all__U359":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U341":{ + "coeff_0_U353":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U343":{ + "coeff_1_U355":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U345":{ + "const_term_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U342":{ + "mul_d0__U354":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U344":{ + "mul_d1__U356":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U342.out","add_all__U346.in0"], - ["mul_d1__U344.out","add_all__U346.in1"], - ["add_all__U347.in0","add_all__U346.out"], - ["const_term_U345.out","add_all__U347.in1"], - ["self.out","add_all__U347.out"], - ["mul_d0__U342.in0","coeff_0_U341.out"], - ["mul_d1__U344.in0","coeff_1_U343.out"], - ["self.d.0","mul_d0__U342.in1"], - ["self.d.1","mul_d1__U344.in1"] + ["mul_d0__U354.out","add_all__U358.in0"], + ["mul_d1__U356.out","add_all__U358.in1"], + ["add_all__U359.in0","add_all__U358.out"], + ["const_term_U357.out","add_all__U359.in1"], + ["self.out","add_all__U359.out"], + ["mul_d0__U354.in0","coeff_0_U353.out"], + ["mul_d1__U356.in0","coeff_1_U355.out"], + ["self.d.0","mul_d0__U354.in1"], + ["self.d.1","mul_d1__U356.in1"] ] }, - "aff__U355":{ + "aff__U366":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U361":{ + "add_all__U372":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U362":{ + "add_all__U373":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U356":{ + "coeff_0_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U358":{ + "coeff_1_U369":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U360":{ + "const_term_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U357":{ + "mul_d0__U368":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U359":{ + "mul_d1__U370":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U357.out","add_all__U361.in0"], - ["mul_d1__U359.out","add_all__U361.in1"], - ["add_all__U362.in0","add_all__U361.out"], - ["const_term_U360.out","add_all__U362.in1"], - ["self.out","add_all__U362.out"], - ["mul_d0__U357.in0","coeff_0_U356.out"], - ["mul_d1__U359.in0","coeff_1_U358.out"], - ["self.d.0","mul_d0__U357.in1"], - ["self.d.1","mul_d1__U359.in1"] + ["mul_d0__U368.out","add_all__U372.in0"], + ["mul_d1__U370.out","add_all__U372.in1"], + ["add_all__U373.in0","add_all__U372.out"], + ["const_term_U371.out","add_all__U373.in1"], + ["self.out","add_all__U373.out"], + ["mul_d0__U368.in0","coeff_0_U367.out"], + ["mul_d1__U370.in0","coeff_1_U369.out"], + ["self.d.0","mul_d0__U368.in1"], + ["self.d.1","mul_d1__U370.in1"] ] }, - "aff__U370":{ + "aff__U380":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U376":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U377":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U371":{ + "coeff_0_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U373":{ + "coeff_1_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U375":{ + "const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U372":{ + "mul_d0__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U374":{ + "mul_d1__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U372.out","add_all__U376.in0"], - ["mul_d1__U374.out","add_all__U376.in1"], - ["add_all__U377.in0","add_all__U376.out"], - ["const_term_U375.out","add_all__U377.in1"], - ["self.out","add_all__U377.out"], - ["mul_d0__U372.in0","coeff_0_U371.out"], - ["mul_d1__U374.in0","coeff_1_U373.out"], - ["self.d.0","mul_d0__U372.in1"], - ["self.d.1","mul_d1__U374.in1"] + ["mul_d0__U382.out","add_all__U386.in0"], + ["mul_d1__U384.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["const_term_U385.out","add_all__U387.in1"], + ["self.out","add_all__U387.out"], + ["mul_d0__U382.in0","coeff_0_U381.out"], + ["mul_d1__U384.in0","coeff_1_U383.out"], + ["self.d.0","mul_d0__U382.in1"], + ["self.d.1","mul_d1__U384.in1"] ] }, - "aff__U385":{ + "aff__U394":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U391":{ + "add_all__U400":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U392":{ + "add_all__U401":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U386":{ + "coeff_0_U395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U388":{ + "coeff_1_U397":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U390":{ + "const_term_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U387":{ + "mul_d0__U396":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U389":{ + "mul_d1__U398":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U387.out","add_all__U391.in0"], - ["mul_d1__U389.out","add_all__U391.in1"], - ["add_all__U392.in0","add_all__U391.out"], - ["const_term_U390.out","add_all__U392.in1"], - ["self.out","add_all__U392.out"], - ["mul_d0__U387.in0","coeff_0_U386.out"], - ["mul_d1__U389.in0","coeff_1_U388.out"], - ["self.d.0","mul_d0__U387.in1"], - ["self.d.1","mul_d1__U389.in1"] + ["mul_d0__U396.out","add_all__U400.in0"], + ["mul_d1__U398.out","add_all__U400.in1"], + ["add_all__U401.in0","add_all__U400.out"], + ["const_term_U399.out","add_all__U401.in1"], + ["self.out","add_all__U401.out"], + ["mul_d0__U396.in0","coeff_0_U395.out"], + ["mul_d1__U398.in0","coeff_1_U397.out"], + ["self.d.0","mul_d0__U396.in1"], + ["self.d.1","mul_d1__U398.in1"] ] }, - "aff__U400":{ + "aff__U408":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U406":{ + "add_all__U414":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U407":{ + "add_all__U415":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U401":{ + "coeff_0_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U403":{ + "coeff_1_U411":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U405":{ + "const_term_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U402":{ + "mul_d0__U410":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U404":{ + "mul_d1__U412":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U402.out","add_all__U406.in0"], - ["mul_d1__U404.out","add_all__U406.in1"], - ["add_all__U407.in0","add_all__U406.out"], - ["const_term_U405.out","add_all__U407.in1"], - ["self.out","add_all__U407.out"], - ["mul_d0__U402.in0","coeff_0_U401.out"], - ["mul_d1__U404.in0","coeff_1_U403.out"], - ["self.d.0","mul_d0__U402.in1"], - ["self.d.1","mul_d1__U404.in1"] + ["mul_d0__U410.out","add_all__U414.in0"], + ["mul_d1__U412.out","add_all__U414.in1"], + ["add_all__U415.in0","add_all__U414.out"], + ["const_term_U413.out","add_all__U415.in1"], + ["self.out","add_all__U415.out"], + ["mul_d0__U410.in0","coeff_0_U409.out"], + ["mul_d1__U412.in0","coeff_1_U411.out"], + ["self.d.0","mul_d0__U410.in1"], + ["self.d.1","mul_d1__U412.in1"] ] }, - "aff__U415":{ + "aff__U422":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U421":{ + "add_all__U428":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U422":{ + "add_all__U429":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U416":{ + "coeff_0_U423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U418":{ + "coeff_1_U425":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U420":{ + "const_term_U427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U417":{ + "mul_d0__U424":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U419":{ + "mul_d1__U426":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U417.out","add_all__U421.in0"], - ["mul_d1__U419.out","add_all__U421.in1"], - ["add_all__U422.in0","add_all__U421.out"], - ["const_term_U420.out","add_all__U422.in1"], - ["self.out","add_all__U422.out"], - ["mul_d0__U417.in0","coeff_0_U416.out"], - ["mul_d1__U419.in0","coeff_1_U418.out"], - ["self.d.0","mul_d0__U417.in1"], - ["self.d.1","mul_d1__U419.in1"] + ["mul_d0__U424.out","add_all__U428.in0"], + ["mul_d1__U426.out","add_all__U428.in1"], + ["add_all__U429.in0","add_all__U428.out"], + ["const_term_U427.out","add_all__U429.in1"], + ["self.out","add_all__U429.out"], + ["mul_d0__U424.in0","coeff_0_U423.out"], + ["mul_d1__U426.in0","coeff_1_U425.out"], + ["self.d.0","mul_d0__U424.in1"], + ["self.d.1","mul_d1__U426.in1"] ] }, - "aff__U430":{ + "aff__U436":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U436":{ + "add_all__U442":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U437":{ + "add_all__U443":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U431":{ + "coeff_0_U437":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U433":{ + "coeff_1_U439":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U435":{ + "const_term_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U432":{ + "mul_d0__U438":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U434":{ + "mul_d1__U440":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U432.out","add_all__U436.in0"], - ["mul_d1__U434.out","add_all__U436.in1"], - ["add_all__U437.in0","add_all__U436.out"], - ["const_term_U435.out","add_all__U437.in1"], - ["self.out","add_all__U437.out"], - ["mul_d0__U432.in0","coeff_0_U431.out"], - ["mul_d1__U434.in0","coeff_1_U433.out"], - ["self.d.0","mul_d0__U432.in1"], - ["self.d.1","mul_d1__U434.in1"] + ["mul_d0__U438.out","add_all__U442.in0"], + ["mul_d1__U440.out","add_all__U442.in1"], + ["add_all__U443.in0","add_all__U442.out"], + ["const_term_U441.out","add_all__U443.in1"], + ["self.out","add_all__U443.out"], + ["mul_d0__U438.in0","coeff_0_U437.out"], + ["mul_d1__U440.in0","coeff_1_U439.out"], + ["self.d.0","mul_d0__U438.in1"], + ["self.d.1","mul_d1__U440.in1"] ] }, - "aff__U445":{ + "aff__U44":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U50":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U51":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U446":{ + "coeff_0_U45":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U448":{ + "coeff_1_U47":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U450":{ + "const_term_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U447":{ + "mul_d0__U46":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U449":{ + "mul_d1__U48":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U447.out","add_all__U451.in0"], - ["mul_d1__U449.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["const_term_U450.out","add_all__U452.in1"], - ["self.out","add_all__U452.out"], - ["mul_d0__U447.in0","coeff_0_U446.out"], - ["mul_d1__U449.in0","coeff_1_U448.out"], - ["self.d.0","mul_d0__U447.in1"], - ["self.d.1","mul_d1__U449.in1"] + ["mul_d0__U46.out","add_all__U50.in0"], + ["mul_d1__U48.out","add_all__U50.in1"], + ["add_all__U51.in0","add_all__U50.out"], + ["const_term_U49.out","add_all__U51.in1"], + ["self.out","add_all__U51.out"], + ["mul_d0__U46.in0","coeff_0_U45.out"], + ["mul_d1__U48.in0","coeff_1_U47.out"], + ["self.d.0","mul_d0__U46.in1"], + ["self.d.1","mul_d1__U48.in1"] ] }, - "aff__U460":{ + "aff__U450":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U466":{ + "add_all__U456":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U467":{ + "add_all__U457":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U461":{ + "coeff_0_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U463":{ + "coeff_1_U453":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U465":{ + "const_term_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U462":{ + "mul_d0__U452":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U464":{ + "mul_d1__U454":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U462.out","add_all__U466.in0"], - ["mul_d1__U464.out","add_all__U466.in1"], - ["add_all__U467.in0","add_all__U466.out"], - ["const_term_U465.out","add_all__U467.in1"], - ["self.out","add_all__U467.out"], - ["mul_d0__U462.in0","coeff_0_U461.out"], - ["mul_d1__U464.in0","coeff_1_U463.out"], - ["self.d.0","mul_d0__U462.in1"], - ["self.d.1","mul_d1__U464.in1"] + ["mul_d0__U452.out","add_all__U456.in0"], + ["mul_d1__U454.out","add_all__U456.in1"], + ["add_all__U457.in0","add_all__U456.out"], + ["const_term_U455.out","add_all__U457.in1"], + ["self.out","add_all__U457.out"], + ["mul_d0__U452.in0","coeff_0_U451.out"], + ["mul_d1__U454.in0","coeff_1_U453.out"], + ["self.d.0","mul_d0__U452.in1"], + ["self.d.1","mul_d1__U454.in1"] ] }, - "aff__U47":{ + "aff__U464":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U53":{ + "add_all__U470":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U471":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U48":{ + "coeff_0_U465":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U50":{ + "coeff_1_U467":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U52":{ + "const_term_U469":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U49":{ + "mul_d0__U466":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U51":{ + "mul_d1__U468":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U49.out","add_all__U53.in0"], - ["mul_d1__U51.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U52.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U49.in0","coeff_0_U48.out"], - ["mul_d1__U51.in0","coeff_1_U50.out"], - ["self.d.0","mul_d0__U49.in1"], - ["self.d.1","mul_d1__U51.in1"] + ["mul_d0__U466.out","add_all__U470.in0"], + ["mul_d1__U468.out","add_all__U470.in1"], + ["add_all__U471.in0","add_all__U470.out"], + ["const_term_U469.out","add_all__U471.in1"], + ["self.out","add_all__U471.out"], + ["mul_d0__U466.in0","coeff_0_U465.out"], + ["mul_d1__U468.in0","coeff_1_U467.out"], + ["self.d.0","mul_d0__U466.in1"], + ["self.d.1","mul_d1__U468.in1"] ] }, - "aff__U475":{ + "aff__U478":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U481":{ + "add_all__U484":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U482":{ + "add_all__U485":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U476":{ + "coeff_0_U479":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U478":{ + "coeff_1_U481":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U480":{ + "const_term_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U477":{ + "mul_d0__U480":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U479":{ + "mul_d1__U482":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U477.out","add_all__U481.in0"], - ["mul_d1__U479.out","add_all__U481.in1"], - ["add_all__U482.in0","add_all__U481.out"], - ["const_term_U480.out","add_all__U482.in1"], - ["self.out","add_all__U482.out"], - ["mul_d0__U477.in0","coeff_0_U476.out"], - ["mul_d1__U479.in0","coeff_1_U478.out"], - ["self.d.0","mul_d0__U477.in1"], - ["self.d.1","mul_d1__U479.in1"] + ["mul_d0__U480.out","add_all__U484.in0"], + ["mul_d1__U482.out","add_all__U484.in1"], + ["add_all__U485.in0","add_all__U484.out"], + ["const_term_U483.out","add_all__U485.in1"], + ["self.out","add_all__U485.out"], + ["mul_d0__U480.in0","coeff_0_U479.out"], + ["mul_d1__U482.in0","coeff_1_U481.out"], + ["self.d.0","mul_d0__U480.in1"], + ["self.d.1","mul_d1__U482.in1"] ] }, - "aff__U490":{ + "aff__U492":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U496":{ + "add_all__U498":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U497":{ + "add_all__U499":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U491":{ + "coeff_0_U493":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U493":{ + "coeff_1_U495":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U495":{ + "const_term_U497":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U492":{ + "mul_d0__U494":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U494":{ + "mul_d1__U496":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U492.out","add_all__U496.in0"], - ["mul_d1__U494.out","add_all__U496.in1"], - ["add_all__U497.in0","add_all__U496.out"], - ["const_term_U495.out","add_all__U497.in1"], - ["self.out","add_all__U497.out"], - ["mul_d0__U492.in0","coeff_0_U491.out"], - ["mul_d1__U494.in0","coeff_1_U493.out"], - ["self.d.0","mul_d0__U492.in1"], - ["self.d.1","mul_d1__U494.in1"] + ["mul_d0__U494.out","add_all__U498.in0"], + ["mul_d1__U496.out","add_all__U498.in1"], + ["add_all__U499.in0","add_all__U498.out"], + ["const_term_U497.out","add_all__U499.in1"], + ["self.out","add_all__U499.out"], + ["mul_d0__U494.in0","coeff_0_U493.out"], + ["mul_d1__U496.in0","coeff_1_U495.out"], + ["self.d.0","mul_d0__U494.in1"], + ["self.d.1","mul_d1__U496.in1"] ] }, - "aff__U505":{ + "aff__U506":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U511":{ + "add_all__U512":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U512":{ + "add_all__U513":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U506":{ + "coeff_0_U507":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U508":{ + "coeff_1_U509":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U510":{ + "const_term_U511":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U507":{ + "mul_d0__U508":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U509":{ + "mul_d1__U510":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U507.out","add_all__U511.in0"], - ["mul_d1__U509.out","add_all__U511.in1"], - ["add_all__U512.in0","add_all__U511.out"], - ["const_term_U510.out","add_all__U512.in1"], - ["self.out","add_all__U512.out"], - ["mul_d0__U507.in0","coeff_0_U506.out"], - ["mul_d1__U509.in0","coeff_1_U508.out"], - ["self.d.0","mul_d0__U507.in1"], - ["self.d.1","mul_d1__U509.in1"] + ["mul_d0__U508.out","add_all__U512.in0"], + ["mul_d1__U510.out","add_all__U512.in1"], + ["add_all__U513.in0","add_all__U512.out"], + ["const_term_U511.out","add_all__U513.in1"], + ["self.out","add_all__U513.out"], + ["mul_d0__U508.in0","coeff_0_U507.out"], + ["mul_d1__U510.in0","coeff_1_U509.out"], + ["self.d.0","mul_d0__U508.in1"], + ["self.d.1","mul_d1__U510.in1"] ] }, "aff__U520":{ @@ -3768,704 +3618,804 @@ ["self.d.1","mul_d1__U524.in1"] ] }, - "aff__U535":{ + "aff__U534":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U541":{ + "add_all__U540":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U542":{ + "add_all__U541":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U536":{ + "coeff_0_U535":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U538":{ + "coeff_1_U537":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U540":{ + "const_term_U539":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U537":{ + "mul_d0__U536":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U539":{ + "mul_d1__U538":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U537.out","add_all__U541.in0"], - ["mul_d1__U539.out","add_all__U541.in1"], - ["add_all__U542.in0","add_all__U541.out"], - ["const_term_U540.out","add_all__U542.in1"], - ["self.out","add_all__U542.out"], - ["mul_d0__U537.in0","coeff_0_U536.out"], - ["mul_d1__U539.in0","coeff_1_U538.out"], - ["self.d.0","mul_d0__U537.in1"], - ["self.d.1","mul_d1__U539.in1"] + ["mul_d0__U536.out","add_all__U540.in0"], + ["mul_d1__U538.out","add_all__U540.in1"], + ["add_all__U541.in0","add_all__U540.out"], + ["const_term_U539.out","add_all__U541.in1"], + ["self.out","add_all__U541.out"], + ["mul_d0__U536.in0","coeff_0_U535.out"], + ["mul_d1__U538.in0","coeff_1_U537.out"], + ["self.d.0","mul_d0__U536.in1"], + ["self.d.1","mul_d1__U538.in1"] ] }, - "aff__U550":{ + "aff__U548":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U556":{ + "add_all__U554":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U557":{ + "add_all__U555":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U551":{ + "coeff_0_U549":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U553":{ + "coeff_1_U551":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U555":{ + "const_term_U553":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U552":{ + "mul_d0__U550":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U554":{ + "mul_d1__U552":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U552.out","add_all__U556.in0"], - ["mul_d1__U554.out","add_all__U556.in1"], - ["add_all__U557.in0","add_all__U556.out"], - ["const_term_U555.out","add_all__U557.in1"], - ["self.out","add_all__U557.out"], - ["mul_d0__U552.in0","coeff_0_U551.out"], - ["mul_d1__U554.in0","coeff_1_U553.out"], - ["self.d.0","mul_d0__U552.in1"], - ["self.d.1","mul_d1__U554.in1"] + ["mul_d0__U550.out","add_all__U554.in0"], + ["mul_d1__U552.out","add_all__U554.in1"], + ["add_all__U555.in0","add_all__U554.out"], + ["const_term_U553.out","add_all__U555.in1"], + ["self.out","add_all__U555.out"], + ["mul_d0__U550.in0","coeff_0_U549.out"], + ["mul_d1__U552.in0","coeff_1_U551.out"], + ["self.d.0","mul_d0__U550.in1"], + ["self.d.1","mul_d1__U552.in1"] ] }, - "aff__U565":{ + "aff__U562":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U571":{ + "add_all__U568":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U572":{ + "add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U566":{ + "coeff_0_U563":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U568":{ + "coeff_1_U565":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U570":{ + "const_term_U567":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U567":{ + "mul_d0__U564":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U569":{ + "mul_d1__U566":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U567.out","add_all__U571.in0"], - ["mul_d1__U569.out","add_all__U571.in1"], - ["add_all__U572.in0","add_all__U571.out"], - ["const_term_U570.out","add_all__U572.in1"], - ["self.out","add_all__U572.out"], - ["mul_d0__U567.in0","coeff_0_U566.out"], - ["mul_d1__U569.in0","coeff_1_U568.out"], - ["self.d.0","mul_d0__U567.in1"], - ["self.d.1","mul_d1__U569.in1"] + ["mul_d0__U564.out","add_all__U568.in0"], + ["mul_d1__U566.out","add_all__U568.in1"], + ["add_all__U569.in0","add_all__U568.out"], + ["const_term_U567.out","add_all__U569.in1"], + ["self.out","add_all__U569.out"], + ["mul_d0__U564.in0","coeff_0_U563.out"], + ["mul_d1__U566.in0","coeff_1_U565.out"], + ["self.d.0","mul_d0__U564.in1"], + ["self.d.1","mul_d1__U566.in1"] ] }, - "aff__U580":{ + "aff__U576":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U586":{ + "add_all__U582":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U587":{ + "add_all__U583":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U581":{ + "coeff_0_U577":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U583":{ + "coeff_1_U579":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U585":{ + "const_term_U581":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U582":{ + "mul_d0__U578":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U584":{ + "mul_d1__U580":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U582.out","add_all__U586.in0"], - ["mul_d1__U584.out","add_all__U586.in1"], - ["add_all__U587.in0","add_all__U586.out"], - ["const_term_U585.out","add_all__U587.in1"], - ["self.out","add_all__U587.out"], - ["mul_d0__U582.in0","coeff_0_U581.out"], - ["mul_d1__U584.in0","coeff_1_U583.out"], - ["self.d.0","mul_d0__U582.in1"], - ["self.d.1","mul_d1__U584.in1"] + ["mul_d0__U578.out","add_all__U582.in0"], + ["mul_d1__U580.out","add_all__U582.in1"], + ["add_all__U583.in0","add_all__U582.out"], + ["const_term_U581.out","add_all__U583.in1"], + ["self.out","add_all__U583.out"], + ["mul_d0__U578.in0","coeff_0_U577.out"], + ["mul_d1__U580.in0","coeff_1_U579.out"], + ["self.d.0","mul_d0__U578.in1"], + ["self.d.1","mul_d1__U580.in1"] ] }, - "aff__U595":{ + "aff__U58":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U601":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U602":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U596":{ + "coeff_0_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U598":{ + "coeff_1_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U600":{ + "const_term_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U597":{ + "mul_d0__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U599":{ + "mul_d1__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U597.out","add_all__U601.in0"], - ["mul_d1__U599.out","add_all__U601.in1"], - ["add_all__U602.in0","add_all__U601.out"], - ["const_term_U600.out","add_all__U602.in1"], - ["self.out","add_all__U602.out"], - ["mul_d0__U597.in0","coeff_0_U596.out"], - ["mul_d1__U599.in0","coeff_1_U598.out"], - ["self.d.0","mul_d0__U597.in1"], - ["self.d.1","mul_d1__U599.in1"] + ["mul_d0__U60.out","add_all__U64.in0"], + ["mul_d1__U62.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["const_term_U63.out","add_all__U65.in1"], + ["self.out","add_all__U65.out"], + ["mul_d0__U60.in0","coeff_0_U59.out"], + ["mul_d1__U62.in0","coeff_1_U61.out"], + ["self.d.0","mul_d0__U60.in1"], + ["self.d.1","mul_d1__U62.in1"] ] }, - "aff__U610":{ + "aff__U590":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U616":{ + "add_all__U596":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U617":{ + "add_all__U597":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U611":{ + "coeff_0_U591":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U613":{ + "coeff_1_U593":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U615":{ + "const_term_U595":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U612":{ + "mul_d0__U592":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U614":{ + "mul_d1__U594":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U612.out","add_all__U616.in0"], - ["mul_d1__U614.out","add_all__U616.in1"], - ["add_all__U617.in0","add_all__U616.out"], - ["const_term_U615.out","add_all__U617.in1"], - ["self.out","add_all__U617.out"], - ["mul_d0__U612.in0","coeff_0_U611.out"], - ["mul_d1__U614.in0","coeff_1_U613.out"], - ["self.d.0","mul_d0__U612.in1"], - ["self.d.1","mul_d1__U614.in1"] + ["mul_d0__U592.out","add_all__U596.in0"], + ["mul_d1__U594.out","add_all__U596.in1"], + ["add_all__U597.in0","add_all__U596.out"], + ["const_term_U595.out","add_all__U597.in1"], + ["self.out","add_all__U597.out"], + ["mul_d0__U592.in0","coeff_0_U591.out"], + ["mul_d1__U594.in0","coeff_1_U593.out"], + ["self.d.0","mul_d0__U592.in1"], + ["self.d.1","mul_d1__U594.in1"] ] }, - "aff__U62":{ + "aff__U604":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U68":{ + "add_all__U610":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U69":{ + "add_all__U611":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U63":{ + "coeff_0_U605":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U65":{ + "coeff_1_U607":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U67":{ + "const_term_U609":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U64":{ + "mul_d0__U606":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U66":{ + "mul_d1__U608":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U64.out","add_all__U68.in0"], - ["mul_d1__U66.out","add_all__U68.in1"], - ["add_all__U69.in0","add_all__U68.out"], - ["const_term_U67.out","add_all__U69.in1"], - ["self.out","add_all__U69.out"], - ["mul_d0__U64.in0","coeff_0_U63.out"], - ["mul_d1__U66.in0","coeff_1_U65.out"], - ["self.d.0","mul_d0__U64.in1"], - ["self.d.1","mul_d1__U66.in1"] + ["mul_d0__U606.out","add_all__U610.in0"], + ["mul_d1__U608.out","add_all__U610.in1"], + ["add_all__U611.in0","add_all__U610.out"], + ["const_term_U609.out","add_all__U611.in1"], + ["self.out","add_all__U611.out"], + ["mul_d0__U606.in0","coeff_0_U605.out"], + ["mul_d1__U608.in0","coeff_1_U607.out"], + ["self.d.0","mul_d0__U606.in1"], + ["self.d.1","mul_d1__U608.in1"] ] }, - "aff__U625":{ + "aff__U618":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U631":{ + "add_all__U624":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U632":{ + "add_all__U625":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U626":{ + "coeff_0_U619":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U628":{ + "coeff_1_U621":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U630":{ + "const_term_U623":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U627":{ + "mul_d0__U620":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U629":{ + "mul_d1__U622":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U627.out","add_all__U631.in0"], - ["mul_d1__U629.out","add_all__U631.in1"], - ["add_all__U632.in0","add_all__U631.out"], - ["const_term_U630.out","add_all__U632.in1"], - ["self.out","add_all__U632.out"], - ["mul_d0__U627.in0","coeff_0_U626.out"], - ["mul_d1__U629.in0","coeff_1_U628.out"], - ["self.d.0","mul_d0__U627.in1"], - ["self.d.1","mul_d1__U629.in1"] + ["mul_d0__U620.out","add_all__U624.in0"], + ["mul_d1__U622.out","add_all__U624.in1"], + ["add_all__U625.in0","add_all__U624.out"], + ["const_term_U623.out","add_all__U625.in1"], + ["self.out","add_all__U625.out"], + ["mul_d0__U620.in0","coeff_0_U619.out"], + ["mul_d1__U622.in0","coeff_1_U621.out"], + ["self.d.0","mul_d0__U620.in1"], + ["self.d.1","mul_d1__U622.in1"] ] }, - "aff__U640":{ + "aff__U632":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U646":{ + "add_all__U638":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U647":{ + "add_all__U639":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U641":{ + "coeff_0_U633":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U643":{ + "coeff_1_U635":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U645":{ + "const_term_U637":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U642":{ + "mul_d0__U634":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U644":{ + "mul_d1__U636":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U642.out","add_all__U646.in0"], - ["mul_d1__U644.out","add_all__U646.in1"], - ["add_all__U647.in0","add_all__U646.out"], - ["const_term_U645.out","add_all__U647.in1"], - ["self.out","add_all__U647.out"], - ["mul_d0__U642.in0","coeff_0_U641.out"], - ["mul_d1__U644.in0","coeff_1_U643.out"], - ["self.d.0","mul_d0__U642.in1"], - ["self.d.1","mul_d1__U644.in1"] + ["mul_d0__U634.out","add_all__U638.in0"], + ["mul_d1__U636.out","add_all__U638.in1"], + ["add_all__U639.in0","add_all__U638.out"], + ["const_term_U637.out","add_all__U639.in1"], + ["self.out","add_all__U639.out"], + ["mul_d0__U634.in0","coeff_0_U633.out"], + ["mul_d1__U636.in0","coeff_1_U635.out"], + ["self.d.0","mul_d0__U634.in1"], + ["self.d.1","mul_d1__U636.in1"] ] }, - "aff__U655":{ + "aff__U646":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U661":{ + "add_all__U652":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U662":{ + "add_all__U653":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U656":{ + "coeff_0_U647":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U658":{ + "coeff_1_U649":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U660":{ + "const_term_U651":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U657":{ + "mul_d0__U648":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U659":{ + "mul_d1__U650":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U657.out","add_all__U661.in0"], - ["mul_d1__U659.out","add_all__U661.in1"], - ["add_all__U662.in0","add_all__U661.out"], - ["const_term_U660.out","add_all__U662.in1"], - ["self.out","add_all__U662.out"], - ["mul_d0__U657.in0","coeff_0_U656.out"], - ["mul_d1__U659.in0","coeff_1_U658.out"], - ["self.d.0","mul_d0__U657.in1"], - ["self.d.1","mul_d1__U659.in1"] + ["mul_d0__U648.out","add_all__U652.in0"], + ["mul_d1__U650.out","add_all__U652.in1"], + ["add_all__U653.in0","add_all__U652.out"], + ["const_term_U651.out","add_all__U653.in1"], + ["self.out","add_all__U653.out"], + ["mul_d0__U648.in0","coeff_0_U647.out"], + ["mul_d1__U650.in0","coeff_1_U649.out"], + ["self.d.0","mul_d0__U648.in1"], + ["self.d.1","mul_d1__U650.in1"] ] }, - "aff__U670":{ + "aff__U660":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U676":{ + "add_all__U666":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U677":{ + "add_all__U667":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U671":{ + "coeff_0_U661":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U673":{ + "coeff_1_U663":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U675":{ + "const_term_U665":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U672":{ + "mul_d0__U662":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U674":{ + "mul_d1__U664":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U672.out","add_all__U676.in0"], - ["mul_d1__U674.out","add_all__U676.in1"], - ["add_all__U677.in0","add_all__U676.out"], - ["const_term_U675.out","add_all__U677.in1"], - ["self.out","add_all__U677.out"], - ["mul_d0__U672.in0","coeff_0_U671.out"], - ["mul_d1__U674.in0","coeff_1_U673.out"], - ["self.d.0","mul_d0__U672.in1"], - ["self.d.1","mul_d1__U674.in1"] + ["mul_d0__U662.out","add_all__U666.in0"], + ["mul_d1__U664.out","add_all__U666.in1"], + ["add_all__U667.in0","add_all__U666.out"], + ["const_term_U665.out","add_all__U667.in1"], + ["self.out","add_all__U667.out"], + ["mul_d0__U662.in0","coeff_0_U661.out"], + ["mul_d1__U664.in0","coeff_1_U663.out"], + ["self.d.0","mul_d0__U662.in1"], + ["self.d.1","mul_d1__U664.in1"] ] }, - "aff__U685":{ + "aff__U674":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U691":{ + "add_all__U680":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U692":{ + "add_all__U681":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U686":{ + "coeff_0_U675":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U688":{ + "coeff_1_U677":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U690":{ + "const_term_U679":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U687":{ + "mul_d0__U676":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U689":{ + "mul_d1__U678":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U687.out","add_all__U691.in0"], - ["mul_d1__U689.out","add_all__U691.in1"], - ["add_all__U692.in0","add_all__U691.out"], - ["const_term_U690.out","add_all__U692.in1"], - ["self.out","add_all__U692.out"], - ["mul_d0__U687.in0","coeff_0_U686.out"], - ["mul_d1__U689.in0","coeff_1_U688.out"], - ["self.d.0","mul_d0__U687.in1"], - ["self.d.1","mul_d1__U689.in1"] + ["mul_d0__U676.out","add_all__U680.in0"], + ["mul_d1__U678.out","add_all__U680.in1"], + ["add_all__U681.in0","add_all__U680.out"], + ["const_term_U679.out","add_all__U681.in1"], + ["self.out","add_all__U681.out"], + ["mul_d0__U676.in0","coeff_0_U675.out"], + ["mul_d1__U678.in0","coeff_1_U677.out"], + ["self.d.0","mul_d0__U676.in1"], + ["self.d.1","mul_d1__U678.in1"] ] }, - "aff__U700":{ + "aff__U688":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U706":{ + "add_all__U694":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U707":{ + "add_all__U695":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U701":{ + "coeff_0_U689":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U703":{ + "coeff_1_U691":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U705":{ + "const_term_U693":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U702":{ + "mul_d0__U690":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U704":{ + "mul_d1__U692":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U702.out","add_all__U706.in0"], - ["mul_d1__U704.out","add_all__U706.in1"], - ["add_all__U707.in0","add_all__U706.out"], - ["const_term_U705.out","add_all__U707.in1"], - ["self.out","add_all__U707.out"], - ["mul_d0__U702.in0","coeff_0_U701.out"], - ["mul_d1__U704.in0","coeff_1_U703.out"], - ["self.d.0","mul_d0__U702.in1"], - ["self.d.1","mul_d1__U704.in1"] + ["mul_d0__U690.out","add_all__U694.in0"], + ["mul_d1__U692.out","add_all__U694.in1"], + ["add_all__U695.in0","add_all__U694.out"], + ["const_term_U693.out","add_all__U695.in1"], + ["self.out","add_all__U695.out"], + ["mul_d0__U690.in0","coeff_0_U689.out"], + ["mul_d1__U692.in0","coeff_1_U691.out"], + ["self.d.0","mul_d0__U690.in1"], + ["self.d.1","mul_d1__U692.in1"] ] }, - "aff__U715":{ + "aff__U702":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U721":{ + "add_all__U708":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U709":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, + "coeff_0_U703":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U705":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U707":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U704":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U706":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U704.out","add_all__U708.in0"], + ["mul_d1__U706.out","add_all__U708.in1"], + ["add_all__U709.in0","add_all__U708.out"], + ["const_term_U707.out","add_all__U709.in1"], + ["self.out","add_all__U709.out"], + ["mul_d0__U704.in0","coeff_0_U703.out"], + ["mul_d1__U706.in0","coeff_1_U705.out"], + ["self.d.0","mul_d0__U704.in1"], + ["self.d.1","mul_d1__U706.in1"] + ] + }, + "aff__U716":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ "add_all__U722":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U716":{ + "add_all__U723":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U717":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U719":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U721":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U718":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U720":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U718.out","add_all__U722.in0"], + ["mul_d1__U720.out","add_all__U722.in1"], + ["add_all__U723.in0","add_all__U722.out"], + ["const_term_U721.out","add_all__U723.in1"], + ["self.out","add_all__U723.out"], + ["mul_d0__U718.in0","coeff_0_U717.out"], + ["mul_d1__U720.in0","coeff_1_U719.out"], + ["self.d.0","mul_d0__U718.in1"], + ["self.d.1","mul_d1__U720.in1"] + ] + }, + "aff__U72":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U78":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U79":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U73":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U718":{ + "coeff_1_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U720":{ + "const_term_U77":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U717":{ + "mul_d0__U74":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U719":{ + "mul_d1__U76":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U717.out","add_all__U721.in0"], - ["mul_d1__U719.out","add_all__U721.in1"], - ["add_all__U722.in0","add_all__U721.out"], - ["const_term_U720.out","add_all__U722.in1"], - ["self.out","add_all__U722.out"], - ["mul_d0__U717.in0","coeff_0_U716.out"], - ["mul_d1__U719.in0","coeff_1_U718.out"], - ["self.d.0","mul_d0__U717.in1"], - ["self.d.1","mul_d1__U719.in1"] + ["mul_d0__U74.out","add_all__U78.in0"], + ["mul_d1__U76.out","add_all__U78.in1"], + ["add_all__U79.in0","add_all__U78.out"], + ["const_term_U77.out","add_all__U79.in1"], + ["self.out","add_all__U79.out"], + ["mul_d0__U74.in0","coeff_0_U73.out"], + ["mul_d1__U76.in0","coeff_1_U75.out"], + ["self.d.0","mul_d0__U74.in1"], + ["self.d.1","mul_d1__U76.in1"] ] }, "aff__U730":{ @@ -4518,754 +4468,754 @@ ["self.d.1","mul_d1__U734.in1"] ] }, - "aff__U745":{ + "aff__U744":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U751":{ + "add_all__U750":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U752":{ + "add_all__U751":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U746":{ + "coeff_0_U745":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U748":{ + "coeff_1_U747":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U750":{ + "const_term_U749":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U747":{ + "mul_d0__U746":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U749":{ + "mul_d1__U748":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U747.out","add_all__U751.in0"], - ["mul_d1__U749.out","add_all__U751.in1"], - ["add_all__U752.in0","add_all__U751.out"], - ["const_term_U750.out","add_all__U752.in1"], - ["self.out","add_all__U752.out"], - ["mul_d0__U747.in0","coeff_0_U746.out"], - ["mul_d1__U749.in0","coeff_1_U748.out"], - ["self.d.0","mul_d0__U747.in1"], - ["self.d.1","mul_d1__U749.in1"] + ["mul_d0__U746.out","add_all__U750.in0"], + ["mul_d1__U748.out","add_all__U750.in1"], + ["add_all__U751.in0","add_all__U750.out"], + ["const_term_U749.out","add_all__U751.in1"], + ["self.out","add_all__U751.out"], + ["mul_d0__U746.in0","coeff_0_U745.out"], + ["mul_d1__U748.in0","coeff_1_U747.out"], + ["self.d.0","mul_d0__U746.in1"], + ["self.d.1","mul_d1__U748.in1"] ] }, - "aff__U760":{ + "aff__U758":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U766":{ + "add_all__U764":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U767":{ + "add_all__U765":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U761":{ + "coeff_0_U759":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U763":{ + "coeff_1_U761":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U765":{ + "const_term_U763":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U762":{ + "mul_d0__U760":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U764":{ + "mul_d1__U762":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U762.out","add_all__U766.in0"], - ["mul_d1__U764.out","add_all__U766.in1"], - ["add_all__U767.in0","add_all__U766.out"], - ["const_term_U765.out","add_all__U767.in1"], - ["self.out","add_all__U767.out"], - ["mul_d0__U762.in0","coeff_0_U761.out"], - ["mul_d1__U764.in0","coeff_1_U763.out"], - ["self.d.0","mul_d0__U762.in1"], - ["self.d.1","mul_d1__U764.in1"] + ["mul_d0__U760.out","add_all__U764.in0"], + ["mul_d1__U762.out","add_all__U764.in1"], + ["add_all__U765.in0","add_all__U764.out"], + ["const_term_U763.out","add_all__U765.in1"], + ["self.out","add_all__U765.out"], + ["mul_d0__U760.in0","coeff_0_U759.out"], + ["mul_d1__U762.in0","coeff_1_U761.out"], + ["self.d.0","mul_d0__U760.in1"], + ["self.d.1","mul_d1__U762.in1"] ] }, - "aff__U77":{ + "aff__U772":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U83":{ + "add_all__U778":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U84":{ + "add_all__U779":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U78":{ + "coeff_0_U773":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U80":{ + "coeff_1_U775":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U82":{ + "const_term_U777":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U79":{ + "mul_d0__U774":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U81":{ + "mul_d1__U776":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U79.out","add_all__U83.in0"], - ["mul_d1__U81.out","add_all__U83.in1"], - ["add_all__U84.in0","add_all__U83.out"], - ["const_term_U82.out","add_all__U84.in1"], - ["self.out","add_all__U84.out"], - ["mul_d0__U79.in0","coeff_0_U78.out"], - ["mul_d1__U81.in0","coeff_1_U80.out"], - ["self.d.0","mul_d0__U79.in1"], - ["self.d.1","mul_d1__U81.in1"] + ["mul_d0__U774.out","add_all__U778.in0"], + ["mul_d1__U776.out","add_all__U778.in1"], + ["add_all__U779.in0","add_all__U778.out"], + ["const_term_U777.out","add_all__U779.in1"], + ["self.out","add_all__U779.out"], + ["mul_d0__U774.in0","coeff_0_U773.out"], + ["mul_d1__U776.in0","coeff_1_U775.out"], + ["self.d.0","mul_d0__U774.in1"], + ["self.d.1","mul_d1__U776.in1"] ] }, - "aff__U775":{ + "aff__U786":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U781":{ + "add_all__U792":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U782":{ + "add_all__U793":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U776":{ + "coeff_0_U787":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U778":{ + "coeff_1_U789":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U780":{ + "const_term_U791":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U777":{ + "mul_d0__U788":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U779":{ + "mul_d1__U790":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U777.out","add_all__U781.in0"], - ["mul_d1__U779.out","add_all__U781.in1"], - ["add_all__U782.in0","add_all__U781.out"], - ["const_term_U780.out","add_all__U782.in1"], - ["self.out","add_all__U782.out"], - ["mul_d0__U777.in0","coeff_0_U776.out"], - ["mul_d1__U779.in0","coeff_1_U778.out"], - ["self.d.0","mul_d0__U777.in1"], - ["self.d.1","mul_d1__U779.in1"] + ["mul_d0__U788.out","add_all__U792.in0"], + ["mul_d1__U790.out","add_all__U792.in1"], + ["add_all__U793.in0","add_all__U792.out"], + ["const_term_U791.out","add_all__U793.in1"], + ["self.out","add_all__U793.out"], + ["mul_d0__U788.in0","coeff_0_U787.out"], + ["mul_d1__U790.in0","coeff_1_U789.out"], + ["self.d.0","mul_d0__U788.in1"], + ["self.d.1","mul_d1__U790.in1"] ] }, - "aff__U790":{ + "aff__U800":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U796":{ + "add_all__U806":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U797":{ + "add_all__U807":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U791":{ + "coeff_0_U801":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U793":{ + "coeff_1_U803":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U795":{ + "const_term_U805":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U792":{ + "mul_d0__U802":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U794":{ + "mul_d1__U804":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U792.out","add_all__U796.in0"], - ["mul_d1__U794.out","add_all__U796.in1"], - ["add_all__U797.in0","add_all__U796.out"], - ["const_term_U795.out","add_all__U797.in1"], - ["self.out","add_all__U797.out"], - ["mul_d0__U792.in0","coeff_0_U791.out"], - ["mul_d1__U794.in0","coeff_1_U793.out"], - ["self.d.0","mul_d0__U792.in1"], - ["self.d.1","mul_d1__U794.in1"] + ["mul_d0__U802.out","add_all__U806.in0"], + ["mul_d1__U804.out","add_all__U806.in1"], + ["add_all__U807.in0","add_all__U806.out"], + ["const_term_U805.out","add_all__U807.in1"], + ["self.out","add_all__U807.out"], + ["mul_d0__U802.in0","coeff_0_U801.out"], + ["mul_d1__U804.in0","coeff_1_U803.out"], + ["self.d.0","mul_d0__U802.in1"], + ["self.d.1","mul_d1__U804.in1"] ] }, - "aff__U805":{ + "aff__U814":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U811":{ + "add_all__U820":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U812":{ + "add_all__U821":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U806":{ + "coeff_0_U815":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U808":{ + "coeff_1_U817":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U810":{ + "const_term_U819":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U807":{ + "mul_d0__U816":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U809":{ + "mul_d1__U818":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U807.out","add_all__U811.in0"], - ["mul_d1__U809.out","add_all__U811.in1"], - ["add_all__U812.in0","add_all__U811.out"], - ["const_term_U810.out","add_all__U812.in1"], - ["self.out","add_all__U812.out"], - ["mul_d0__U807.in0","coeff_0_U806.out"], - ["mul_d1__U809.in0","coeff_1_U808.out"], - ["self.d.0","mul_d0__U807.in1"], - ["self.d.1","mul_d1__U809.in1"] + ["mul_d0__U816.out","add_all__U820.in0"], + ["mul_d1__U818.out","add_all__U820.in1"], + ["add_all__U821.in0","add_all__U820.out"], + ["const_term_U819.out","add_all__U821.in1"], + ["self.out","add_all__U821.out"], + ["mul_d0__U816.in0","coeff_0_U815.out"], + ["mul_d1__U818.in0","coeff_1_U817.out"], + ["self.d.0","mul_d0__U816.in1"], + ["self.d.1","mul_d1__U818.in1"] ] }, - "aff__U820":{ + "aff__U828":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U826":{ + "add_all__U834":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U827":{ + "add_all__U835":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U821":{ + "coeff_0_U829":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U823":{ + "coeff_1_U831":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U825":{ + "const_term_U833":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U822":{ + "mul_d0__U830":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U824":{ + "mul_d1__U832":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U822.out","add_all__U826.in0"], - ["mul_d1__U824.out","add_all__U826.in1"], - ["add_all__U827.in0","add_all__U826.out"], - ["const_term_U825.out","add_all__U827.in1"], - ["self.out","add_all__U827.out"], - ["mul_d0__U822.in0","coeff_0_U821.out"], - ["mul_d1__U824.in0","coeff_1_U823.out"], - ["self.d.0","mul_d0__U822.in1"], - ["self.d.1","mul_d1__U824.in1"] + ["mul_d0__U830.out","add_all__U834.in0"], + ["mul_d1__U832.out","add_all__U834.in1"], + ["add_all__U835.in0","add_all__U834.out"], + ["const_term_U833.out","add_all__U835.in1"], + ["self.out","add_all__U835.out"], + ["mul_d0__U830.in0","coeff_0_U829.out"], + ["mul_d1__U832.in0","coeff_1_U831.out"], + ["self.d.0","mul_d0__U830.in1"], + ["self.d.1","mul_d1__U832.in1"] ] }, - "aff__U835":{ + "aff__U842":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U841":{ + "add_all__U848":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U842":{ + "add_all__U849":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U836":{ + "coeff_0_U843":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U838":{ + "coeff_1_U845":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U840":{ + "const_term_U847":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U837":{ + "mul_d0__U844":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U839":{ + "mul_d1__U846":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U837.out","add_all__U841.in0"], - ["mul_d1__U839.out","add_all__U841.in1"], - ["add_all__U842.in0","add_all__U841.out"], - ["const_term_U840.out","add_all__U842.in1"], - ["self.out","add_all__U842.out"], - ["mul_d0__U837.in0","coeff_0_U836.out"], - ["mul_d1__U839.in0","coeff_1_U838.out"], - ["self.d.0","mul_d0__U837.in1"], - ["self.d.1","mul_d1__U839.in1"] + ["mul_d0__U844.out","add_all__U848.in0"], + ["mul_d1__U846.out","add_all__U848.in1"], + ["add_all__U849.in0","add_all__U848.out"], + ["const_term_U847.out","add_all__U849.in1"], + ["self.out","add_all__U849.out"], + ["mul_d0__U844.in0","coeff_0_U843.out"], + ["mul_d1__U846.in0","coeff_1_U845.out"], + ["self.d.0","mul_d0__U844.in1"], + ["self.d.1","mul_d1__U846.in1"] ] }, - "aff__U850":{ + "aff__U856":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U856":{ + "add_all__U862":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U857":{ + "add_all__U863":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U851":{ + "coeff_0_U857":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U853":{ + "coeff_1_U859":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U855":{ + "const_term_U861":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U852":{ + "mul_d0__U858":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U854":{ + "mul_d1__U860":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U852.out","add_all__U856.in0"], - ["mul_d1__U854.out","add_all__U856.in1"], - ["add_all__U857.in0","add_all__U856.out"], - ["const_term_U855.out","add_all__U857.in1"], - ["self.out","add_all__U857.out"], - ["mul_d0__U852.in0","coeff_0_U851.out"], - ["mul_d1__U854.in0","coeff_1_U853.out"], - ["self.d.0","mul_d0__U852.in1"], - ["self.d.1","mul_d1__U854.in1"] + ["mul_d0__U858.out","add_all__U862.in0"], + ["mul_d1__U860.out","add_all__U862.in1"], + ["add_all__U863.in0","add_all__U862.out"], + ["const_term_U861.out","add_all__U863.in1"], + ["self.out","add_all__U863.out"], + ["mul_d0__U858.in0","coeff_0_U857.out"], + ["mul_d1__U860.in0","coeff_1_U859.out"], + ["self.d.0","mul_d0__U858.in1"], + ["self.d.1","mul_d1__U860.in1"] ] }, - "aff__U865":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U871":{ + "add_all__U92":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U872":{ + "add_all__U93":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U866":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U868":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U870":{ + "const_term_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U867":{ + "mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U869":{ + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U867.out","add_all__U871.in0"], - ["mul_d1__U869.out","add_all__U871.in1"], - ["add_all__U872.in0","add_all__U871.out"], - ["const_term_U870.out","add_all__U872.in1"], - ["self.out","add_all__U872.out"], - ["mul_d0__U867.in0","coeff_0_U866.out"], - ["mul_d1__U869.in0","coeff_1_U868.out"], - ["self.d.0","mul_d0__U867.in1"], - ["self.d.1","mul_d1__U869.in1"] + ["mul_d0__U88.out","add_all__U92.in0"], + ["mul_d1__U90.out","add_all__U92.in1"], + ["add_all__U93.in0","add_all__U92.out"], + ["const_term_U91.out","add_all__U93.in1"], + ["self.out","add_all__U93.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"] ] }, - "aff__U880":{ + "aff__U870":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U886":{ + "add_all__U876":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U887":{ + "add_all__U877":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U881":{ + "coeff_0_U871":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U883":{ + "coeff_1_U873":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U885":{ + "const_term_U875":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U882":{ + "mul_d0__U872":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U884":{ + "mul_d1__U874":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U882.out","add_all__U886.in0"], - ["mul_d1__U884.out","add_all__U886.in1"], - ["add_all__U887.in0","add_all__U886.out"], - ["const_term_U885.out","add_all__U887.in1"], - ["self.out","add_all__U887.out"], - ["mul_d0__U882.in0","coeff_0_U881.out"], - ["mul_d1__U884.in0","coeff_1_U883.out"], - ["self.d.0","mul_d0__U882.in1"], - ["self.d.1","mul_d1__U884.in1"] + ["mul_d0__U872.out","add_all__U876.in0"], + ["mul_d1__U874.out","add_all__U876.in1"], + ["add_all__U877.in0","add_all__U876.out"], + ["const_term_U875.out","add_all__U877.in1"], + ["self.out","add_all__U877.out"], + ["mul_d0__U872.in0","coeff_0_U871.out"], + ["mul_d1__U874.in0","coeff_1_U873.out"], + ["self.d.0","mul_d0__U872.in1"], + ["self.d.1","mul_d1__U874.in1"] ] }, - "aff__U895":{ + "aff__U884":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U901":{ + "add_all__U890":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U902":{ + "add_all__U891":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U896":{ + "coeff_0_U885":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U898":{ + "coeff_1_U887":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U900":{ + "const_term_U889":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U897":{ + "mul_d0__U886":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U899":{ + "mul_d1__U888":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U897.out","add_all__U901.in0"], - ["mul_d1__U899.out","add_all__U901.in1"], - ["add_all__U902.in0","add_all__U901.out"], - ["const_term_U900.out","add_all__U902.in1"], - ["self.out","add_all__U902.out"], - ["mul_d0__U897.in0","coeff_0_U896.out"], - ["mul_d1__U899.in0","coeff_1_U898.out"], - ["self.d.0","mul_d0__U897.in1"], - ["self.d.1","mul_d1__U899.in1"] + ["mul_d0__U886.out","add_all__U890.in0"], + ["mul_d1__U888.out","add_all__U890.in1"], + ["add_all__U891.in0","add_all__U890.out"], + ["const_term_U889.out","add_all__U891.in1"], + ["self.out","add_all__U891.out"], + ["mul_d0__U886.in0","coeff_0_U885.out"], + ["mul_d1__U888.in0","coeff_1_U887.out"], + ["self.d.0","mul_d0__U886.in1"], + ["self.d.1","mul_d1__U888.in1"] ] }, - "aff__U910":{ + "aff__U898":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U916":{ + "add_all__U904":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U917":{ + "add_all__U905":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U911":{ + "coeff_0_U899":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U913":{ + "coeff_1_U901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U915":{ + "const_term_U903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U912":{ + "mul_d0__U900":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U914":{ + "mul_d1__U902":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U912.out","add_all__U916.in0"], - ["mul_d1__U914.out","add_all__U916.in1"], - ["add_all__U917.in0","add_all__U916.out"], - ["const_term_U915.out","add_all__U917.in1"], - ["self.out","add_all__U917.out"], - ["mul_d0__U912.in0","coeff_0_U911.out"], - ["mul_d1__U914.in0","coeff_1_U913.out"], - ["self.d.0","mul_d0__U912.in1"], - ["self.d.1","mul_d1__U914.in1"] + ["mul_d0__U900.out","add_all__U904.in0"], + ["mul_d1__U902.out","add_all__U904.in1"], + ["add_all__U905.in0","add_all__U904.out"], + ["const_term_U903.out","add_all__U905.in1"], + ["self.out","add_all__U905.out"], + ["mul_d0__U900.in0","coeff_0_U899.out"], + ["mul_d1__U902.in0","coeff_1_U901.out"], + ["self.d.0","mul_d0__U900.in1"], + ["self.d.1","mul_d1__U902.in1"] ] }, - "aff__U92":{ + "aff__U912":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U98":{ + "add_all__U918":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U99":{ + "add_all__U919":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U93":{ + "coeff_0_U913":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U95":{ + "coeff_1_U915":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U97":{ + "const_term_U917":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U94":{ + "mul_d0__U914":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U96":{ + "mul_d1__U916":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U94.out","add_all__U98.in0"], - ["mul_d1__U96.out","add_all__U98.in1"], - ["add_all__U99.in0","add_all__U98.out"], - ["const_term_U97.out","add_all__U99.in1"], - ["self.out","add_all__U99.out"], - ["mul_d0__U94.in0","coeff_0_U93.out"], - ["mul_d1__U96.in0","coeff_1_U95.out"], - ["self.d.0","mul_d0__U94.in1"], - ["self.d.1","mul_d1__U96.in1"] + ["mul_d0__U914.out","add_all__U918.in0"], + ["mul_d1__U916.out","add_all__U918.in1"], + ["add_all__U919.in0","add_all__U918.out"], + ["const_term_U917.out","add_all__U919.in1"], + ["self.out","add_all__U919.out"], + ["mul_d0__U914.in0","coeff_0_U913.out"], + ["mul_d1__U916.in0","coeff_1_U915.out"], + ["self.d.0","mul_d0__U914.in1"], + ["self.d.1","mul_d1__U916.in1"] ] }, - "aff__U925":{ + "aff__U926":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U931":{ + "add_all__U932":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U932":{ + "add_all__U933":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U926":{ + "coeff_0_U927":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U928":{ + "coeff_1_U929":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U930":{ + "const_term_U931":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U927":{ + "mul_d0__U928":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U929":{ + "mul_d1__U930":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U927.out","add_all__U931.in0"], - ["mul_d1__U929.out","add_all__U931.in1"], - ["add_all__U932.in0","add_all__U931.out"], - ["const_term_U930.out","add_all__U932.in1"], - ["self.out","add_all__U932.out"], - ["mul_d0__U927.in0","coeff_0_U926.out"], - ["mul_d1__U929.in0","coeff_1_U928.out"], - ["self.d.0","mul_d0__U927.in1"], - ["self.d.1","mul_d1__U929.in1"] + ["mul_d0__U928.out","add_all__U932.in0"], + ["mul_d1__U930.out","add_all__U932.in1"], + ["add_all__U933.in0","add_all__U932.out"], + ["const_term_U931.out","add_all__U933.in1"], + ["self.out","add_all__U933.out"], + ["mul_d0__U928.in0","coeff_0_U927.out"], + ["mul_d1__U930.in0","coeff_1_U929.out"], + ["self.d.0","mul_d0__U928.in1"], + ["self.d.1","mul_d1__U930.in1"] ] }, "aff__U940":{ @@ -5318,178 +5268,228 @@ ["self.d.1","mul_d1__U944.in1"] ] }, - "aff__U955":{ + "aff__U954":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U961":{ + "add_all__U960":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U962":{ + "add_all__U961":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U956":{ + "coeff_0_U955":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U958":{ + "coeff_1_U957":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U960":{ + "const_term_U959":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U957":{ + "mul_d0__U956":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U959":{ + "mul_d1__U958":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U957.out","add_all__U961.in0"], - ["mul_d1__U959.out","add_all__U961.in1"], - ["add_all__U962.in0","add_all__U961.out"], - ["const_term_U960.out","add_all__U962.in1"], - ["self.out","add_all__U962.out"], - ["mul_d0__U957.in0","coeff_0_U956.out"], - ["mul_d1__U959.in0","coeff_1_U958.out"], - ["self.d.0","mul_d0__U957.in1"], - ["self.d.1","mul_d1__U959.in1"] + ["mul_d0__U956.out","add_all__U960.in0"], + ["mul_d1__U958.out","add_all__U960.in1"], + ["add_all__U961.in0","add_all__U960.out"], + ["const_term_U959.out","add_all__U961.in1"], + ["self.out","add_all__U961.out"], + ["mul_d0__U956.in0","coeff_0_U955.out"], + ["mul_d1__U958.in0","coeff_1_U957.out"], + ["self.d.0","mul_d0__U956.in1"], + ["self.d.1","mul_d1__U958.in1"] ] }, - "aff__U970":{ + "aff__U968":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U976":{ + "add_all__U974":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U977":{ + "add_all__U975":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U971":{ + "coeff_0_U969":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U973":{ + "coeff_1_U971":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U975":{ + "const_term_U973":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U972":{ + "mul_d0__U970":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U974":{ + "mul_d1__U972":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U972.out","add_all__U976.in0"], - ["mul_d1__U974.out","add_all__U976.in1"], - ["add_all__U977.in0","add_all__U976.out"], - ["const_term_U975.out","add_all__U977.in1"], - ["self.out","add_all__U977.out"], - ["mul_d0__U972.in0","coeff_0_U971.out"], - ["mul_d1__U974.in0","coeff_1_U973.out"], - ["self.d.0","mul_d0__U972.in1"], - ["self.d.1","mul_d1__U974.in1"] + ["mul_d0__U970.out","add_all__U974.in0"], + ["mul_d1__U972.out","add_all__U974.in1"], + ["add_all__U975.in0","add_all__U974.out"], + ["const_term_U973.out","add_all__U975.in1"], + ["self.out","add_all__U975.out"], + ["mul_d0__U970.in0","coeff_0_U969.out"], + ["mul_d1__U972.in0","coeff_1_U971.out"], + ["self.d.0","mul_d0__U970.in1"], + ["self.d.1","mul_d1__U972.in1"] ] }, - "aff__U985":{ + "aff__U982":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U991":{ + "add_all__U988":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U992":{ + "add_all__U989":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U986":{ + "coeff_0_U983":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U988":{ + "coeff_1_U985":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U990":{ + "const_term_U987":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U987":{ + "mul_d0__U984":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U989":{ + "mul_d1__U986":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U987.out","add_all__U991.in0"], - ["mul_d1__U989.out","add_all__U991.in1"], - ["add_all__U992.in0","add_all__U991.out"], - ["const_term_U990.out","add_all__U992.in1"], - ["self.out","add_all__U992.out"], - ["mul_d0__U987.in0","coeff_0_U986.out"], - ["mul_d1__U989.in0","coeff_1_U988.out"], - ["self.d.0","mul_d0__U987.in1"], - ["self.d.1","mul_d1__U989.in1"] + ["mul_d0__U984.out","add_all__U988.in0"], + ["mul_d1__U986.out","add_all__U988.in1"], + ["add_all__U989.in0","add_all__U988.out"], + ["const_term_U987.out","add_all__U989.in1"], + ["self.out","add_all__U989.out"], + ["mul_d0__U984.in0","coeff_0_U983.out"], + ["mul_d1__U986.in0","coeff_1_U985.out"], + ["self.d.0","mul_d0__U984.in1"], + ["self.d.1","mul_d1__U986.in1"] ] }, - "affine_controller__U1":{ + "aff__U996":{ "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "_U10":{ + "add_all__U1002":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U1003":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U997":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "_U11":{ + "coeff_1_U999":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func":{ - "modref":"global.aff__U2" - }, - "cmp_time":{ + "const_term_U1001":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U998":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U1000":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U998.out","add_all__U1002.in0"], + ["mul_d1__U1000.out","add_all__U1002.in1"], + ["add_all__U1003.in0","add_all__U1002.out"], + ["const_term_U1001.out","add_all__U1003.in1"], + ["self.out","add_all__U1003.out"], + ["mul_d0__U998.in0","coeff_0_U997.out"], + ["mul_d1__U1000.in0","coeff_1_U999.out"], + ["self.d.0","mul_d0__U998.in1"], + ["self.d.1","mul_d1__U1000.in1"] + ] + }, + "affine_controller__U1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U2" + }, + "cmp_time":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, @@ -5615,7 +5615,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1014":{ + "affine_controller__U1009":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5623,18 +5623,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1023":{ + "_U1018":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1024":{ + "_U1019":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1015" + "modref":"global.aff__U1010" }, "cmp_time":{ "genref":"coreir.eq", @@ -5644,7 +5644,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1025":{ + "d_0_am__U1020":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5719,9 +5719,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1023.out"], - ["d_1_inc.in1","_U1023.out"], - ["cmp_time.in1","_U1024.out"], + ["d_0_inc.in1","_U1018.out"], + ["d_1_inc.in1","_U1018.out"], + ["cmp_time.in1","_U1019.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -5732,9 +5732,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1025.in0"], - ["d_1_at_max.out","d_0_am__U1025.in1"], - ["d_0_next_value.sel","d_0_am__U1025.out"], + ["true.out","d_0_am__U1020.in0"], + ["d_1_at_max.out","d_0_am__U1020.in1"], + ["d_0_next_value.sel","d_0_am__U1020.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5762,7 +5762,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1029":{ + "affine_controller__U1023":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5770,18 +5770,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1038":{ + "_U1032":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1039":{ + "_U1033":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1030" + "modref":"global.aff__U1024" }, "cmp_time":{ "genref":"coreir.eq", @@ -5791,7 +5791,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1040":{ + "d_0_am__U1034":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5866,9 +5866,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1038.out"], - ["d_1_inc.in1","_U1038.out"], - ["cmp_time.in1","_U1039.out"], + ["d_0_inc.in1","_U1032.out"], + ["d_1_inc.in1","_U1032.out"], + ["cmp_time.in1","_U1033.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -5879,9 +5879,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1040.in0"], - ["d_1_at_max.out","d_0_am__U1040.in1"], - ["d_0_next_value.sel","d_0_am__U1040.out"], + ["true.out","d_0_am__U1034.in0"], + ["d_1_at_max.out","d_0_am__U1034.in1"], + ["d_0_next_value.sel","d_0_am__U1034.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5909,7 +5909,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1044":{ + "affine_controller__U1037":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5917,18 +5917,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1053":{ + "_U1046":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1054":{ + "_U1047":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1045" + "modref":"global.aff__U1038" }, "cmp_time":{ "genref":"coreir.eq", @@ -5938,7 +5938,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1055":{ + "d_0_am__U1048":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6013,9 +6013,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1053.out"], - ["d_1_inc.in1","_U1053.out"], - ["cmp_time.in1","_U1054.out"], + ["d_0_inc.in1","_U1046.out"], + ["d_1_inc.in1","_U1046.out"], + ["cmp_time.in1","_U1047.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -6026,9 +6026,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1055.in0"], - ["d_1_at_max.out","d_0_am__U1055.in1"], - ["d_0_next_value.sel","d_0_am__U1055.out"], + ["true.out","d_0_am__U1048.in0"], + ["d_1_at_max.out","d_0_am__U1048.in1"], + ["d_0_next_value.sel","d_0_am__U1048.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6056,7 +6056,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1059":{ + "affine_controller__U1051":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6064,18 +6064,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1068":{ + "_U1060":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1069":{ + "_U1061":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1060" + "modref":"global.aff__U1052" }, "cmp_time":{ "genref":"coreir.eq", @@ -6085,7 +6085,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1070":{ + "d_0_am__U1062":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6160,9 +6160,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1068.out"], - ["d_1_inc.in1","_U1068.out"], - ["cmp_time.in1","_U1069.out"], + ["d_0_inc.in1","_U1060.out"], + ["d_1_inc.in1","_U1060.out"], + ["cmp_time.in1","_U1061.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -6173,9 +6173,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1070.in0"], - ["d_1_at_max.out","d_0_am__U1070.in1"], - ["d_0_next_value.sel","d_0_am__U1070.out"], + ["true.out","d_0_am__U1062.in0"], + ["d_1_at_max.out","d_0_am__U1062.in1"], + ["d_0_next_value.sel","d_0_am__U1062.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6203,7 +6203,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U106":{ + "affine_controller__U1065":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6211,18 +6211,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U115":{ + "_U1074":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U116":{ + "_U1075":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U107" + "modref":"global.aff__U1066" }, "cmp_time":{ "genref":"coreir.eq", @@ -6232,7 +6232,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U117":{ + "d_0_am__U1076":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6307,9 +6307,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U115.out"], - ["d_1_inc.in1","_U115.out"], - ["cmp_time.in1","_U116.out"], + ["d_0_inc.in1","_U1074.out"], + ["d_1_inc.in1","_U1074.out"], + ["cmp_time.in1","_U1075.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -6320,9 +6320,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U117.in0"], - ["d_1_at_max.out","d_0_am__U117.in1"], - ["d_0_next_value.sel","d_0_am__U117.out"], + ["true.out","d_0_am__U1076.in0"], + ["d_1_at_max.out","d_0_am__U1076.in1"], + ["d_0_next_value.sel","d_0_am__U1076.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6350,7 +6350,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1074":{ + "affine_controller__U1079":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6358,18 +6358,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1083":{ + "_U1088":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1084":{ + "_U1089":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1075" + "modref":"global.aff__U1080" }, "cmp_time":{ "genref":"coreir.eq", @@ -6379,7 +6379,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1085":{ + "d_0_am__U1090":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6454,9 +6454,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1083.out"], - ["d_1_inc.in1","_U1083.out"], - ["cmp_time.in1","_U1084.out"], + ["d_0_inc.in1","_U1088.out"], + ["d_1_inc.in1","_U1088.out"], + ["cmp_time.in1","_U1089.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -6467,9 +6467,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1085.in0"], - ["d_1_at_max.out","d_0_am__U1085.in1"], - ["d_0_next_value.sel","d_0_am__U1085.out"], + ["true.out","d_0_am__U1090.in0"], + ["d_1_at_max.out","d_0_am__U1090.in1"], + ["d_0_next_value.sel","d_0_am__U1090.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6497,7 +6497,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1089":{ + "affine_controller__U1093":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6505,18 +6505,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1098":{ + "_U1102":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1099":{ + "_U1103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1090" + "modref":"global.aff__U1094" }, "cmp_time":{ "genref":"coreir.eq", @@ -6526,7 +6526,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1100":{ + "d_0_am__U1104":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6601,9 +6601,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1098.out"], - ["d_1_inc.in1","_U1098.out"], - ["cmp_time.in1","_U1099.out"], + ["d_0_inc.in1","_U1102.out"], + ["d_1_inc.in1","_U1102.out"], + ["cmp_time.in1","_U1103.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -6614,9 +6614,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1100.in0"], - ["d_1_at_max.out","d_0_am__U1100.in1"], - ["d_0_next_value.sel","d_0_am__U1100.out"], + ["true.out","d_0_am__U1104.in0"], + ["d_1_at_max.out","d_0_am__U1104.in1"], + ["d_0_next_value.sel","d_0_am__U1104.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6644,7 +6644,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1104":{ + "affine_controller__U1107":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6652,18 +6652,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1113":{ + "_U1116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1114":{ + "_U1117":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1105" + "modref":"global.aff__U1108" }, "cmp_time":{ "genref":"coreir.eq", @@ -6673,7 +6673,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1115":{ + "d_0_am__U1118":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6748,9 +6748,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1113.out"], - ["d_1_inc.in1","_U1113.out"], - ["cmp_time.in1","_U1114.out"], + ["d_0_inc.in1","_U1116.out"], + ["d_1_inc.in1","_U1116.out"], + ["cmp_time.in1","_U1117.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -6761,9 +6761,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1115.in0"], - ["d_1_at_max.out","d_0_am__U1115.in1"], - ["d_0_next_value.sel","d_0_am__U1115.out"], + ["true.out","d_0_am__U1118.in0"], + ["d_1_at_max.out","d_0_am__U1118.in1"], + ["d_0_next_value.sel","d_0_am__U1118.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6791,26 +6791,26 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1119":{ + "affine_controller__U112":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1128":{ + "_U127":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1129":{ + "_U128":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1120" + "modref":"global.aff__U113" }, "cmp_time":{ "genref":"coreir.eq", @@ -6820,7 +6820,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1130":{ + "d_0_am__U129":{ + "modref":"corebit.and" + }, + "d_0_am__U130":{ + "modref":"corebit.and" + }, + "d_0_am__U131":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6854,6 +6860,12 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U132":{ + "modref":"corebit.and" + }, + "d_1_am__U133":{ + "modref":"corebit.and" + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -6865,7 +6877,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, "d_1_min":{ "genref":"coreir.const", @@ -6885,149 +6897,67 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U1128.out"], - ["d_1_inc.in1","_U1128.out"], - ["cmp_time.in1","_U1129.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1130.in0"], - ["d_1_at_max.out","d_0_am__U1130.in1"], - ["d_0_next_value.sel","d_0_am__U1130.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] - ] - }, - "affine_controller__U1134":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1143":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1144":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U1135" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U1145":{ + "d_2_am__U134":{ "modref":"corebit.and" }, - "d_0_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "d_0_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg":{ + "d_2_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, - "d_1_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg":{ + "d_3_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -7042,22 +6972,32 @@ } }, "connections":[ - ["d_0_inc.in1","_U1143.out"], - ["d_1_inc.in1","_U1143.out"], - ["cmp_time.in1","_U1144.out"], + ["d_0_inc.in1","_U127.out"], + ["d_1_inc.in1","_U127.out"], + ["d_2_inc.in1","_U127.out"], + ["d_3_inc.in1","_U127.out"], + ["cmp_time.in1","_U128.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1145.in0"], - ["d_1_at_max.out","d_0_am__U1145.in1"], - ["d_0_next_value.sel","d_0_am__U1145.out"], + ["true.out","d_0_am__U129.in0"], + ["d_1_at_max.out","d_0_am__U129.in1"], + ["d_0_am__U130.in0","d_0_am__U129.out"], + ["d_2_at_max.out","d_0_am__U130.in1"], + ["d_0_am__U131.in0","d_0_am__U130.out"], + ["d_3_at_max.out","d_0_am__U131.in1"], + ["d_0_next_value.sel","d_0_am__U131.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7070,6 +7010,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U132.in0"], + ["d_2_at_max.out","d_1_am__U132.in1"], + ["d_1_am__U133.in0","d_1_am__U132.out"], + ["d_3_at_max.out","d_1_am__U133.in1"], + ["d_1_next_value.sel","d_1_am__U133.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -7079,32 +7024,59 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U134.in0"], + ["d_3_at_max.out","d_2_am__U134.in1"], + ["d_2_next_value.sel","d_2_am__U134.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U1149":{ + "affine_controller__U1120":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",5,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1158":{ + "_U1138":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1159":{ + "_U1139":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1150" + "modref":"global.aff__U1121" }, "cmp_time":{ "genref":"coreir.eq", @@ -7114,7 +7086,16 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1160":{ + "d_0_am__U1140":{ + "modref":"corebit.and" + }, + "d_0_am__U1141":{ + "modref":"corebit.and" + }, + "d_0_am__U1142":{ + "modref":"corebit.and" + }, + "d_0_am__U1143":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -7148,6 +7129,15 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1144":{ + "modref":"corebit.and" + }, + "d_1_am__U1145":{ + "modref":"corebit.and" + }, + "d_1_am__U1146":{ + "modref":"corebit.and" + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -7159,7 +7149,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -7179,149 +7169,104 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", + "d_2_am__U1147":{ + "modref":"corebit.and" + }, + "d_2_am__U1148":{ + "modref":"corebit.and" + }, + "d_2_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U1158.out"], - ["d_1_inc.in1","_U1158.out"], - ["cmp_time.in1","_U1159.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1160.in0"], - ["d_1_at_max.out","d_0_am__U1160.in1"], - ["d_0_next_value.sel","d_0_am__U1160.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] - ] - }, - "affine_controller__U1164":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1173":{ + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "_U1174":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func":{ - "modref":"global.aff__U1165" + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cmp_time":{ - "genref":"coreir.eq", + "d_2_next_value_at_max":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_0_am__U1175":{ + "d_3_am__U1149":{ "modref":"corebit.and" }, - "d_0_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, - "d_0_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg":{ + "d_3_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_1_min":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_4_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_4_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg":{ + "d_4_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -7336,22 +7281,37 @@ } }, "connections":[ - ["d_0_inc.in1","_U1173.out"], - ["d_1_inc.in1","_U1173.out"], - ["cmp_time.in1","_U1174.out"], + ["d_0_inc.in1","_U1138.out"], + ["d_1_inc.in1","_U1138.out"], + ["d_2_inc.in1","_U1138.out"], + ["d_3_inc.in1","_U1138.out"], + ["d_4_inc.in1","_U1138.out"], + ["cmp_time.in1","_U1139.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1175.in0"], - ["d_1_at_max.out","d_0_am__U1175.in1"], - ["d_0_next_value.sel","d_0_am__U1175.out"], + ["true.out","d_0_am__U1140.in0"], + ["d_1_at_max.out","d_0_am__U1140.in1"], + ["d_0_am__U1141.in0","d_0_am__U1140.out"], + ["d_2_at_max.out","d_0_am__U1141.in1"], + ["d_0_am__U1142.in0","d_0_am__U1141.out"], + ["d_3_at_max.out","d_0_am__U1142.in1"], + ["d_0_am__U1143.in0","d_0_am__U1142.out"], + ["d_4_at_max.out","d_0_am__U1143.in1"], + ["d_0_next_value.sel","d_0_am__U1143.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7364,6 +7324,13 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U1144.in0"], + ["d_2_at_max.out","d_1_am__U1144.in1"], + ["d_1_am__U1145.in0","d_1_am__U1144.out"], + ["d_3_at_max.out","d_1_am__U1145.in1"], + ["d_1_am__U1146.in0","d_1_am__U1145.out"], + ["d_4_at_max.out","d_1_am__U1146.in1"], + ["d_1_next_value.sel","d_1_am__U1146.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -7373,32 +7340,76 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U1147.in0"], + ["d_3_at_max.out","d_2_am__U1147.in1"], + ["d_2_am__U1148.in0","d_2_am__U1147.out"], + ["d_4_at_max.out","d_2_am__U1148.in1"], + ["d_2_next_value.sel","d_2_am__U1148.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["true.out","d_3_am__U1149.in0"], + ["d_4_at_max.out","d_3_am__U1149.in1"], + ["d_3_next_value.sel","d_3_am__U1149.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"], + ["d_4_reg.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg.in","d_4_next_value.out"], + ["true.out","d_4_next_value.sel"], + ["self.clk","d_4_reg.clk"], + ["self.rst_n","d_4_reg.clr"], + ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U1179":{ + "affine_controller__U1169":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",9,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1188":{ + "_U1199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1189":{ + "_U1200":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1180" + "modref":"global.aff__U1170" }, "cmp_time":{ "genref":"coreir.eq", @@ -7408,7 +7419,28 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1190":{ + "d_0_am__U1201":{ + "modref":"corebit.and" + }, + "d_0_am__U1202":{ + "modref":"corebit.and" + }, + "d_0_am__U1203":{ + "modref":"corebit.and" + }, + "d_0_am__U1204":{ + "modref":"corebit.and" + }, + "d_0_am__U1205":{ + "modref":"corebit.and" + }, + "d_0_am__U1206":{ + "modref":"corebit.and" + }, + "d_0_am__U1207":{ + "modref":"corebit.and" + }, + "d_0_am__U1208":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -7442,6 +7474,27 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1209":{ + "modref":"corebit.and" + }, + "d_1_am__U1210":{ + "modref":"corebit.and" + }, + "d_1_am__U1211":{ + "modref":"corebit.and" + }, + "d_1_am__U1212":{ + "modref":"corebit.and" + }, + "d_1_am__U1213":{ + "modref":"corebit.and" + }, + "d_1_am__U1214":{ + "modref":"corebit.and" + }, + "d_1_am__U1215":{ + "modref":"corebit.and" + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -7453,7 +7506,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -7473,269 +7526,282 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U1188.out"], - ["d_1_inc.in1","_U1188.out"], - ["cmp_time.in1","_U1189.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1190.in0"], - ["d_1_at_max.out","d_0_am__U1190.in1"], - ["d_0_next_value.sel","d_0_am__U1190.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] - ] - }, - "affine_controller__U1194":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1212":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1213":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U1195" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_2_am__U1216":{ + "modref":"corebit.and" }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + "d_2_am__U1217":{ + "modref":"corebit.and" }, - "d_0_am__U1214":{ + "d_2_am__U1218":{ "modref":"corebit.and" }, - "d_0_am__U1215":{ + "d_2_am__U1219":{ "modref":"corebit.and" }, - "d_0_am__U1216":{ + "d_2_am__U1220":{ "modref":"corebit.and" }, - "d_0_am__U1217":{ + "d_2_am__U1221":{ "modref":"corebit.and" }, - "d_0_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_0_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg":{ + "d_2_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1218":{ + "d_3_am__U1222":{ "modref":"corebit.and" }, - "d_1_am__U1219":{ + "d_3_am__U1223":{ "modref":"corebit.and" }, - "d_1_am__U1220":{ + "d_3_am__U1224":{ "modref":"corebit.and" }, - "d_1_at_max":{ + "d_3_am__U1225":{ + "modref":"corebit.and" + }, + "d_3_am__U1226":{ + "modref":"corebit.and" + }, + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "d_1_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg":{ + "d_3_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1221":{ + "d_4_am__U1227":{ "modref":"corebit.and" }, - "d_2_am__U1222":{ + "d_4_am__U1228":{ "modref":"corebit.and" }, - "d_2_at_max":{ + "d_4_am__U1229":{ + "modref":"corebit.and" + }, + "d_4_am__U1230":{ + "modref":"corebit.and" + }, + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_2_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_max":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "d_2_min":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ + "d_4_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ + "d_4_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg":{ + "d_4_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U1223":{ + "d_5_am__U1231":{ "modref":"corebit.and" }, - "d_3_at_max":{ + "d_5_am__U1232":{ + "modref":"corebit.and" + }, + "d_5_am__U1233":{ + "modref":"corebit.and" + }, + "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_3_inc":{ + "d_5_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ + "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "d_3_min":{ + "d_5_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "d_5_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "d_5_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg":{ + "d_5_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_at_max":{ + "d_6_am__U1234":{ + "modref":"corebit.and" + }, + "d_6_am__U1235":{ + "modref":"corebit.and" + }, + "d_6_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_6_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_6_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_4_min":{ + "d_6_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_6_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_6_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg":{ + "d_6_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_7_am__U1236":{ + "modref":"corebit.and" + }, + "d_7_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_7_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_7_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_7_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_8_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_8_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_8_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_8_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_8_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_8_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_8_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -7750,17 +7816,25 @@ } }, "connections":[ - ["d_0_inc.in1","_U1212.out"], - ["d_1_inc.in1","_U1212.out"], - ["d_2_inc.in1","_U1212.out"], - ["d_3_inc.in1","_U1212.out"], - ["d_4_inc.in1","_U1212.out"], - ["cmp_time.in1","_U1213.out"], + ["d_0_inc.in1","_U1199.out"], + ["d_1_inc.in1","_U1199.out"], + ["d_2_inc.in1","_U1199.out"], + ["d_3_inc.in1","_U1199.out"], + ["d_4_inc.in1","_U1199.out"], + ["d_5_inc.in1","_U1199.out"], + ["d_6_inc.in1","_U1199.out"], + ["d_7_inc.in1","_U1199.out"], + ["d_8_inc.in1","_U1199.out"], + ["cmp_time.in1","_U1200.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], ["d_3_reg.out","affine_func.d.3"], ["d_4_reg.out","affine_func.d.4"], + ["d_5_reg.out","affine_func.d.5"], + ["d_6_reg.out","affine_func.d.6"], + ["d_7_reg.out","affine_func.d.7"], + ["d_8_reg.out","affine_func.d.8"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], @@ -7768,19 +7842,31 @@ ["d_2_reg.en","cmp_time.out"], ["d_3_reg.en","cmp_time.out"], ["d_4_reg.en","cmp_time.out"], + ["d_5_reg.en","cmp_time.out"], + ["d_6_reg.en","cmp_time.out"], + ["d_7_reg.en","cmp_time.out"], + ["d_8_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1214.in0"], - ["d_1_at_max.out","d_0_am__U1214.in1"], - ["d_0_am__U1215.in0","d_0_am__U1214.out"], - ["d_2_at_max.out","d_0_am__U1215.in1"], - ["d_0_am__U1216.in0","d_0_am__U1215.out"], - ["d_3_at_max.out","d_0_am__U1216.in1"], - ["d_0_am__U1217.in0","d_0_am__U1216.out"], - ["d_4_at_max.out","d_0_am__U1217.in1"], - ["d_0_next_value.sel","d_0_am__U1217.out"], + ["true.out","d_0_am__U1201.in0"], + ["d_1_at_max.out","d_0_am__U1201.in1"], + ["d_0_am__U1202.in0","d_0_am__U1201.out"], + ["d_2_at_max.out","d_0_am__U1202.in1"], + ["d_0_am__U1203.in0","d_0_am__U1202.out"], + ["d_3_at_max.out","d_0_am__U1203.in1"], + ["d_0_am__U1204.in0","d_0_am__U1203.out"], + ["d_4_at_max.out","d_0_am__U1204.in1"], + ["d_0_am__U1205.in0","d_0_am__U1204.out"], + ["d_5_at_max.out","d_0_am__U1205.in1"], + ["d_0_am__U1206.in0","d_0_am__U1205.out"], + ["d_6_at_max.out","d_0_am__U1206.in1"], + ["d_0_am__U1207.in0","d_0_am__U1206.out"], + ["d_7_at_max.out","d_0_am__U1207.in1"], + ["d_0_am__U1208.in0","d_0_am__U1207.out"], + ["d_8_at_max.out","d_0_am__U1208.in1"], + ["d_0_next_value.sel","d_0_am__U1208.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7793,13 +7879,21 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U1218.in0"], - ["d_2_at_max.out","d_1_am__U1218.in1"], - ["d_1_am__U1219.in0","d_1_am__U1218.out"], - ["d_3_at_max.out","d_1_am__U1219.in1"], - ["d_1_am__U1220.in0","d_1_am__U1219.out"], - ["d_4_at_max.out","d_1_am__U1220.in1"], - ["d_1_next_value.sel","d_1_am__U1220.out"], + ["true.out","d_1_am__U1209.in0"], + ["d_2_at_max.out","d_1_am__U1209.in1"], + ["d_1_am__U1210.in0","d_1_am__U1209.out"], + ["d_3_at_max.out","d_1_am__U1210.in1"], + ["d_1_am__U1211.in0","d_1_am__U1210.out"], + ["d_4_at_max.out","d_1_am__U1211.in1"], + ["d_1_am__U1212.in0","d_1_am__U1211.out"], + ["d_5_at_max.out","d_1_am__U1212.in1"], + ["d_1_am__U1213.in0","d_1_am__U1212.out"], + ["d_6_at_max.out","d_1_am__U1213.in1"], + ["d_1_am__U1214.in0","d_1_am__U1213.out"], + ["d_7_at_max.out","d_1_am__U1214.in1"], + ["d_1_am__U1215.in0","d_1_am__U1214.out"], + ["d_8_at_max.out","d_1_am__U1215.in1"], + ["d_1_next_value.sel","d_1_am__U1215.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -7812,11 +7906,19 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U1221.in0"], - ["d_3_at_max.out","d_2_am__U1221.in1"], - ["d_2_am__U1222.in0","d_2_am__U1221.out"], - ["d_4_at_max.out","d_2_am__U1222.in1"], - ["d_2_next_value.sel","d_2_am__U1222.out"], + ["true.out","d_2_am__U1216.in0"], + ["d_3_at_max.out","d_2_am__U1216.in1"], + ["d_2_am__U1217.in0","d_2_am__U1216.out"], + ["d_4_at_max.out","d_2_am__U1217.in1"], + ["d_2_am__U1218.in0","d_2_am__U1217.out"], + ["d_5_at_max.out","d_2_am__U1218.in1"], + ["d_2_am__U1219.in0","d_2_am__U1218.out"], + ["d_6_at_max.out","d_2_am__U1219.in1"], + ["d_2_am__U1220.in0","d_2_am__U1219.out"], + ["d_7_at_max.out","d_2_am__U1220.in1"], + ["d_2_am__U1221.in0","d_2_am__U1220.out"], + ["d_8_at_max.out","d_2_am__U1221.in1"], + ["d_2_next_value.sel","d_2_am__U1221.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -7829,9 +7931,17 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U1223.in0"], - ["d_4_at_max.out","d_3_am__U1223.in1"], - ["d_3_next_value.sel","d_3_am__U1223.out"], + ["true.out","d_3_am__U1222.in0"], + ["d_4_at_max.out","d_3_am__U1222.in1"], + ["d_3_am__U1223.in0","d_3_am__U1222.out"], + ["d_5_at_max.out","d_3_am__U1223.in1"], + ["d_3_am__U1224.in0","d_3_am__U1223.out"], + ["d_6_at_max.out","d_3_am__U1224.in1"], + ["d_3_am__U1225.in0","d_3_am__U1224.out"], + ["d_7_at_max.out","d_3_am__U1225.in1"], + ["d_3_am__U1226.in0","d_3_am__U1225.out"], + ["d_8_at_max.out","d_3_am__U1226.in1"], + ["d_3_next_value.sel","d_3_am__U1226.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -7844,6 +7954,15 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], + ["true.out","d_4_am__U1227.in0"], + ["d_5_at_max.out","d_4_am__U1227.in1"], + ["d_4_am__U1228.in0","d_4_am__U1227.out"], + ["d_6_at_max.out","d_4_am__U1228.in1"], + ["d_4_am__U1229.in0","d_4_am__U1228.out"], + ["d_7_at_max.out","d_4_am__U1229.in1"], + ["d_4_am__U1230.in0","d_4_am__U1229.out"], + ["d_8_at_max.out","d_4_am__U1230.in1"], + ["d_4_next_value.sel","d_4_am__U1230.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -7853,32 +7972,95 @@ ["d_4_reg.out","d_4_next_value.in0"], ["d_4_next_value_at_max.out","d_4_next_value.in1"], ["d_4_reg.in","d_4_next_value.out"], - ["true.out","d_4_next_value.sel"], ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], - ["self.d.4","d_4_reg.out"] + ["self.d.4","d_4_reg.out"], + ["true.out","d_5_am__U1231.in0"], + ["d_6_at_max.out","d_5_am__U1231.in1"], + ["d_5_am__U1232.in0","d_5_am__U1231.out"], + ["d_7_at_max.out","d_5_am__U1232.in1"], + ["d_5_am__U1233.in0","d_5_am__U1232.out"], + ["d_8_at_max.out","d_5_am__U1233.in1"], + ["d_5_next_value.sel","d_5_am__U1233.out"], + ["d_5_reg.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg.in","d_5_next_value.out"], + ["self.clk","d_5_reg.clk"], + ["self.rst_n","d_5_reg.clr"], + ["self.d.5","d_5_reg.out"], + ["true.out","d_6_am__U1234.in0"], + ["d_7_at_max.out","d_6_am__U1234.in1"], + ["d_6_am__U1235.in0","d_6_am__U1234.out"], + ["d_8_at_max.out","d_6_am__U1235.in1"], + ["d_6_next_value.sel","d_6_am__U1235.out"], + ["d_6_reg.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg.in","d_6_next_value.out"], + ["self.clk","d_6_reg.clk"], + ["self.rst_n","d_6_reg.clr"], + ["self.d.6","d_6_reg.out"], + ["true.out","d_7_am__U1236.in0"], + ["d_8_at_max.out","d_7_am__U1236.in1"], + ["d_7_next_value.sel","d_7_am__U1236.out"], + ["d_7_reg.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg.in","d_7_next_value.out"], + ["self.clk","d_7_reg.clk"], + ["self.rst_n","d_7_reg.clr"], + ["self.d.7","d_7_reg.out"], + ["d_8_reg.out","d_8_at_max.in0"], + ["d_8_max.out","d_8_at_max.in1"], + ["d_8_next_value_at_max.sel","d_8_at_max.out"], + ["d_8_reg.out","d_8_inc.in0"], + ["d_8_next_value_at_max.in0","d_8_inc.out"], + ["d_8_next_value_at_max.in1","d_8_min.out"], + ["d_8_reg.out","d_8_next_value.in0"], + ["d_8_next_value_at_max.out","d_8_next_value.in1"], + ["d_8_reg.in","d_8_next_value.out"], + ["true.out","d_8_next_value.sel"], + ["self.clk","d_8_reg.clk"], + ["self.rst_n","d_8_reg.clr"], + ["self.d.8","d_8_reg.out"] ] }, - "affine_controller__U121":{ + "affine_controller__U1270":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U136":{ + "_U1279":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U137":{ + "_U1280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U122" + "modref":"global.aff__U1271" }, "cmp_time":{ "genref":"coreir.eq", @@ -7888,13 +8070,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U138":{ - "modref":"corebit.and" - }, - "d_0_am__U139":{ - "modref":"corebit.and" - }, - "d_0_am__U140":{ + "d_0_am__U1281":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -7928,12 +8104,6 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U141":{ - "modref":"corebit.and" - }, - "d_1_am__U142":{ - "modref":"corebit.and" - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -7945,7 +8115,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -7965,71 +8135,6 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U143":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -8040,32 +8145,22 @@ } }, "connections":[ - ["d_0_inc.in1","_U136.out"], - ["d_1_inc.in1","_U136.out"], - ["d_2_inc.in1","_U136.out"], - ["d_3_inc.in1","_U136.out"], - ["cmp_time.in1","_U137.out"], + ["d_0_inc.in1","_U1279.out"], + ["d_1_inc.in1","_U1279.out"], + ["cmp_time.in1","_U1280.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U138.in0"], - ["d_1_at_max.out","d_0_am__U138.in1"], - ["d_0_am__U139.in0","d_0_am__U138.out"], - ["d_2_at_max.out","d_0_am__U139.in1"], - ["d_0_am__U140.in0","d_0_am__U139.out"], - ["d_3_at_max.out","d_0_am__U140.in1"], - ["d_0_next_value.sel","d_0_am__U140.out"], + ["true.out","d_0_am__U1281.in0"], + ["d_1_at_max.out","d_0_am__U1281.in1"], + ["d_0_next_value.sel","d_0_am__U1281.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8078,11 +8173,6 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U141.in0"], - ["d_2_at_max.out","d_1_am__U141.in1"], - ["d_1_am__U142.in0","d_1_am__U141.out"], - ["d_3_at_max.out","d_1_am__U142.in1"], - ["d_1_next_value.sel","d_1_am__U142.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -8092,59 +8182,32 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U143.in0"], - ["d_3_at_max.out","d_2_am__U143.in1"], - ["d_2_next_value.sel","d_2_am__U143.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1243":{ + "affine_controller__U1284":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",9,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1273":{ + "_U1293":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1274":{ + "_U1294":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1244" + "modref":"global.aff__U1285" }, "cmp_time":{ "genref":"coreir.eq", @@ -8154,28 +8217,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1275":{ - "modref":"corebit.and" - }, - "d_0_am__U1276":{ - "modref":"corebit.and" - }, - "d_0_am__U1277":{ - "modref":"corebit.and" - }, - "d_0_am__U1278":{ - "modref":"corebit.and" - }, - "d_0_am__U1279":{ - "modref":"corebit.and" - }, - "d_0_am__U1280":{ - "modref":"corebit.and" - }, - "d_0_am__U1281":{ - "modref":"corebit.and" - }, - "d_0_am__U1282":{ + "d_0_am__U1295":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -8209,27 +8251,6 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1283":{ - "modref":"corebit.and" - }, - "d_1_am__U1284":{ - "modref":"corebit.and" - }, - "d_1_am__U1285":{ - "modref":"corebit.and" - }, - "d_1_am__U1286":{ - "modref":"corebit.and" - }, - "d_1_am__U1287":{ - "modref":"corebit.and" - }, - "d_1_am__U1288":{ - "modref":"corebit.and" - }, - "d_1_am__U1289":{ - "modref":"corebit.and" - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -8241,7 +8262,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -8261,282 +8282,149 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1290":{ - "modref":"corebit.and" - }, - "d_2_am__U1291":{ - "modref":"corebit.and" - }, - "d_2_am__U1292":{ - "modref":"corebit.and" - }, - "d_2_am__U1293":{ - "modref":"corebit.and" - }, - "d_2_am__U1294":{ - "modref":"corebit.and" - }, - "d_2_am__U1295":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", + "time_diff":{ + "genref":"coreir.sub", "genargs":{"width":["Int",32]} }, - "d_2_max":{ + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U1293.out"], + ["d_1_inc.in1","_U1293.out"], + ["cmp_time.in1","_U1294.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U1295.in0"], + ["d_1_at_max.out","d_0_am__U1295.in1"], + ["d_0_next_value.sel","d_0_am__U1295.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"] + ] + }, + "affine_controller__U1298":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U1307":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U1296":{ - "modref":"corebit.and" - }, - "d_3_am__U1297":{ - "modref":"corebit.and" - }, - "d_3_am__U1298":{ - "modref":"corebit.and" - }, - "d_3_am__U1299":{ - "modref":"corebit.and" - }, - "d_3_am__U1300":{ - "modref":"corebit.and" - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_am__U1301":{ - "modref":"corebit.and" - }, - "d_4_am__U1302":{ - "modref":"corebit.and" - }, - "d_4_am__U1303":{ - "modref":"corebit.and" - }, - "d_4_am__U1304":{ - "modref":"corebit.and" - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_5_am__U1305":{ - "modref":"corebit.and" - }, - "d_5_am__U1306":{ - "modref":"corebit.and" - }, - "d_5_am__U1307":{ - "modref":"corebit.and" - }, - "d_5_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_5_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_5_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} - }, - "d_5_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_5_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_5_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_6_am__U1308":{ - "modref":"corebit.and" - }, - "d_6_am__U1309":{ - "modref":"corebit.and" - }, - "d_6_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_6_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_6_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} - }, - "d_6_min":{ + "_U1308":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func":{ + "modref":"global.aff__U1299" }, - "d_6_next_value_at_max":{ - "genref":"coreir.mux", + "cmp_time":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_6_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_7_am__U1310":{ + "d_0_am__U1309":{ "modref":"corebit.and" }, - "d_7_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_7_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_7_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg":{ + "d_0_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_8_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_8_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_8_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_8_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_8_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_8_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_8_reg":{ + "d_1_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -8551,57 +8439,22 @@ } }, "connections":[ - ["d_0_inc.in1","_U1273.out"], - ["d_1_inc.in1","_U1273.out"], - ["d_2_inc.in1","_U1273.out"], - ["d_3_inc.in1","_U1273.out"], - ["d_4_inc.in1","_U1273.out"], - ["d_5_inc.in1","_U1273.out"], - ["d_6_inc.in1","_U1273.out"], - ["d_7_inc.in1","_U1273.out"], - ["d_8_inc.in1","_U1273.out"], - ["cmp_time.in1","_U1274.out"], + ["d_0_inc.in1","_U1307.out"], + ["d_1_inc.in1","_U1307.out"], + ["cmp_time.in1","_U1308.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["d_4_reg.out","affine_func.d.4"], - ["d_5_reg.out","affine_func.d.5"], - ["d_6_reg.out","affine_func.d.6"], - ["d_7_reg.out","affine_func.d.7"], - ["d_8_reg.out","affine_func.d.8"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["d_4_reg.en","cmp_time.out"], - ["d_5_reg.en","cmp_time.out"], - ["d_6_reg.en","cmp_time.out"], - ["d_7_reg.en","cmp_time.out"], - ["d_8_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1275.in0"], - ["d_1_at_max.out","d_0_am__U1275.in1"], - ["d_0_am__U1276.in0","d_0_am__U1275.out"], - ["d_2_at_max.out","d_0_am__U1276.in1"], - ["d_0_am__U1277.in0","d_0_am__U1276.out"], - ["d_3_at_max.out","d_0_am__U1277.in1"], - ["d_0_am__U1278.in0","d_0_am__U1277.out"], - ["d_4_at_max.out","d_0_am__U1278.in1"], - ["d_0_am__U1279.in0","d_0_am__U1278.out"], - ["d_5_at_max.out","d_0_am__U1279.in1"], - ["d_0_am__U1280.in0","d_0_am__U1279.out"], - ["d_6_at_max.out","d_0_am__U1280.in1"], - ["d_0_am__U1281.in0","d_0_am__U1280.out"], - ["d_7_at_max.out","d_0_am__U1281.in1"], - ["d_0_am__U1282.in0","d_0_am__U1281.out"], - ["d_8_at_max.out","d_0_am__U1282.in1"], - ["d_0_next_value.sel","d_0_am__U1282.out"], + ["true.out","d_0_am__U1309.in0"], + ["d_1_at_max.out","d_0_am__U1309.in1"], + ["d_0_next_value.sel","d_0_am__U1309.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8614,21 +8467,6 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U1283.in0"], - ["d_2_at_max.out","d_1_am__U1283.in1"], - ["d_1_am__U1284.in0","d_1_am__U1283.out"], - ["d_3_at_max.out","d_1_am__U1284.in1"], - ["d_1_am__U1285.in0","d_1_am__U1284.out"], - ["d_4_at_max.out","d_1_am__U1285.in1"], - ["d_1_am__U1286.in0","d_1_am__U1285.out"], - ["d_5_at_max.out","d_1_am__U1286.in1"], - ["d_1_am__U1287.in0","d_1_am__U1286.out"], - ["d_6_at_max.out","d_1_am__U1287.in1"], - ["d_1_am__U1288.in0","d_1_am__U1287.out"], - ["d_7_at_max.out","d_1_am__U1288.in1"], - ["d_1_am__U1289.in0","d_1_am__U1288.out"], - ["d_8_at_max.out","d_1_am__U1289.in1"], - ["d_1_next_value.sel","d_1_am__U1289.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -8638,145 +8476,13 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U1290.in0"], - ["d_3_at_max.out","d_2_am__U1290.in1"], - ["d_2_am__U1291.in0","d_2_am__U1290.out"], - ["d_4_at_max.out","d_2_am__U1291.in1"], - ["d_2_am__U1292.in0","d_2_am__U1291.out"], - ["d_5_at_max.out","d_2_am__U1292.in1"], - ["d_2_am__U1293.in0","d_2_am__U1292.out"], - ["d_6_at_max.out","d_2_am__U1293.in1"], - ["d_2_am__U1294.in0","d_2_am__U1293.out"], - ["d_7_at_max.out","d_2_am__U1294.in1"], - ["d_2_am__U1295.in0","d_2_am__U1294.out"], - ["d_8_at_max.out","d_2_am__U1295.in1"], - ["d_2_next_value.sel","d_2_am__U1295.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U1296.in0"], - ["d_4_at_max.out","d_3_am__U1296.in1"], - ["d_3_am__U1297.in0","d_3_am__U1296.out"], - ["d_5_at_max.out","d_3_am__U1297.in1"], - ["d_3_am__U1298.in0","d_3_am__U1297.out"], - ["d_6_at_max.out","d_3_am__U1298.in1"], - ["d_3_am__U1299.in0","d_3_am__U1298.out"], - ["d_7_at_max.out","d_3_am__U1299.in1"], - ["d_3_am__U1300.in0","d_3_am__U1299.out"], - ["d_8_at_max.out","d_3_am__U1300.in1"], - ["d_3_next_value.sel","d_3_am__U1300.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U1301.in0"], - ["d_5_at_max.out","d_4_am__U1301.in1"], - ["d_4_am__U1302.in0","d_4_am__U1301.out"], - ["d_6_at_max.out","d_4_am__U1302.in1"], - ["d_4_am__U1303.in0","d_4_am__U1302.out"], - ["d_7_at_max.out","d_4_am__U1303.in1"], - ["d_4_am__U1304.in0","d_4_am__U1303.out"], - ["d_8_at_max.out","d_4_am__U1304.in1"], - ["d_4_next_value.sel","d_4_am__U1304.out"], - ["d_4_reg.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg.in","d_4_next_value.out"], - ["self.clk","d_4_reg.clk"], - ["self.rst_n","d_4_reg.clr"], - ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U1305.in0"], - ["d_6_at_max.out","d_5_am__U1305.in1"], - ["d_5_am__U1306.in0","d_5_am__U1305.out"], - ["d_7_at_max.out","d_5_am__U1306.in1"], - ["d_5_am__U1307.in0","d_5_am__U1306.out"], - ["d_8_at_max.out","d_5_am__U1307.in1"], - ["d_5_next_value.sel","d_5_am__U1307.out"], - ["d_5_reg.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg.in","d_5_next_value.out"], - ["self.clk","d_5_reg.clk"], - ["self.rst_n","d_5_reg.clr"], - ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U1308.in0"], - ["d_7_at_max.out","d_6_am__U1308.in1"], - ["d_6_am__U1309.in0","d_6_am__U1308.out"], - ["d_8_at_max.out","d_6_am__U1309.in1"], - ["d_6_next_value.sel","d_6_am__U1309.out"], - ["d_6_reg.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg.in","d_6_next_value.out"], - ["self.clk","d_6_reg.clk"], - ["self.rst_n","d_6_reg.clr"], - ["self.d.6","d_6_reg.out"], - ["true.out","d_7_am__U1310.in0"], - ["d_8_at_max.out","d_7_am__U1310.in1"], - ["d_7_next_value.sel","d_7_am__U1310.out"], - ["d_7_reg.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg.in","d_7_next_value.out"], - ["self.clk","d_7_reg.clk"], - ["self.rst_n","d_7_reg.clr"], - ["self.d.7","d_7_reg.out"], - ["d_8_reg.out","d_8_at_max.in0"], - ["d_8_max.out","d_8_at_max.in1"], - ["d_8_next_value_at_max.sel","d_8_at_max.out"], - ["d_8_reg.out","d_8_inc.in0"], - ["d_8_next_value_at_max.in0","d_8_inc.out"], - ["d_8_next_value_at_max.in1","d_8_min.out"], - ["d_8_reg.out","d_8_next_value.in0"], - ["d_8_next_value_at_max.out","d_8_next_value.in1"], - ["d_8_reg.in","d_8_next_value.out"], - ["true.out","d_8_next_value.sel"], - ["self.clk","d_8_reg.clk"], - ["self.rst_n","d_8_reg.clr"], - ["self.d.8","d_8_reg.out"] + ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1344":{ + "affine_controller__U1312":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -8784,18 +8490,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1353":{ + "_U1321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1354":{ + "_U1322":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1345" + "modref":"global.aff__U1313" }, "cmp_time":{ "genref":"coreir.eq", @@ -8805,7 +8511,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1355":{ + "d_0_am__U1323":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -8880,9 +8586,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1353.out"], - ["d_1_inc.in1","_U1353.out"], - ["cmp_time.in1","_U1354.out"], + ["d_0_inc.in1","_U1321.out"], + ["d_1_inc.in1","_U1321.out"], + ["cmp_time.in1","_U1322.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -8893,9 +8599,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1355.in0"], - ["d_1_at_max.out","d_0_am__U1355.in1"], - ["d_0_next_value.sel","d_0_am__U1355.out"], + ["true.out","d_0_am__U1323.in0"], + ["d_1_at_max.out","d_0_am__U1323.in1"], + ["d_0_next_value.sel","d_0_am__U1323.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8923,7 +8629,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1359":{ + "affine_controller__U1326":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -8931,18 +8637,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1368":{ + "_U1335":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1369":{ + "_U1336":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1360" + "modref":"global.aff__U1327" }, "cmp_time":{ "genref":"coreir.eq", @@ -8952,7 +8658,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1370":{ + "d_0_am__U1337":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -9027,9 +8733,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1368.out"], - ["d_1_inc.in1","_U1368.out"], - ["cmp_time.in1","_U1369.out"], + ["d_0_inc.in1","_U1335.out"], + ["d_1_inc.in1","_U1335.out"], + ["cmp_time.in1","_U1336.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -9040,9 +8746,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1370.in0"], - ["d_1_at_max.out","d_0_am__U1370.in1"], - ["d_0_next_value.sel","d_0_am__U1370.out"], + ["true.out","d_0_am__U1337.in0"], + ["d_1_at_max.out","d_0_am__U1337.in1"], + ["d_0_next_value.sel","d_0_am__U1337.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9070,7 +8776,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1374":{ + "affine_controller__U1340":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -9078,18 +8784,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1383":{ + "_U1349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1384":{ + "_U1350":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1375" + "modref":"global.aff__U1341" }, "cmp_time":{ "genref":"coreir.eq", @@ -9099,7 +8805,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1385":{ + "d_0_am__U1351":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -9174,9 +8880,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1383.out"], - ["d_1_inc.in1","_U1383.out"], - ["cmp_time.in1","_U1384.out"], + ["d_0_inc.in1","_U1349.out"], + ["d_1_inc.in1","_U1349.out"], + ["cmp_time.in1","_U1350.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -9187,9 +8893,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1385.in0"], - ["d_1_at_max.out","d_0_am__U1385.in1"], - ["d_0_next_value.sel","d_0_am__U1385.out"], + ["true.out","d_0_am__U1351.in0"], + ["d_1_at_max.out","d_0_am__U1351.in1"], + ["d_0_next_value.sel","d_0_am__U1351.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9217,7 +8923,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1389":{ + "affine_controller__U1354":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -9225,18 +8931,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1398":{ + "_U1363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1399":{ + "_U1364":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1390" + "modref":"global.aff__U1355" }, "cmp_time":{ "genref":"coreir.eq", @@ -9246,7 +8952,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1400":{ + "d_0_am__U1365":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -9321,9 +9027,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1398.out"], - ["d_1_inc.in1","_U1398.out"], - ["cmp_time.in1","_U1399.out"], + ["d_0_inc.in1","_U1363.out"], + ["d_1_inc.in1","_U1363.out"], + ["cmp_time.in1","_U1364.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -9334,9 +9040,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1400.in0"], - ["d_1_at_max.out","d_0_am__U1400.in1"], - ["d_0_next_value.sel","d_0_am__U1400.out"], + ["true.out","d_0_am__U1365.in0"], + ["d_1_at_max.out","d_0_am__U1365.in1"], + ["d_0_next_value.sel","d_0_am__U1365.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9364,7 +9070,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1404":{ + "affine_controller__U1368":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -9372,18 +9078,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1413":{ + "_U1377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1414":{ + "_U1378":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1405" + "modref":"global.aff__U1369" }, "cmp_time":{ "genref":"coreir.eq", @@ -9393,7 +9099,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1415":{ + "d_0_am__U1379":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -9468,9 +9174,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1413.out"], - ["d_1_inc.in1","_U1413.out"], - ["cmp_time.in1","_U1414.out"], + ["d_0_inc.in1","_U1377.out"], + ["d_1_inc.in1","_U1377.out"], + ["cmp_time.in1","_U1378.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -9481,9 +9187,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1415.in0"], - ["d_1_at_max.out","d_0_am__U1415.in1"], - ["d_0_next_value.sel","d_0_am__U1415.out"], + ["true.out","d_0_am__U1379.in0"], + ["d_1_at_max.out","d_0_am__U1379.in1"], + ["d_0_next_value.sel","d_0_am__U1379.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9511,96 +9217,262 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1419":{ + "affine_controller__U1381":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",6,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1428":{ + "_U1402":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1403":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U1382" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U1404":{ + "modref":"corebit.and" + }, + "d_0_am__U1405":{ + "modref":"corebit.and" + }, + "d_0_am__U1406":{ + "modref":"corebit.and" + }, + "d_0_am__U1407":{ + "modref":"corebit.and" + }, + "d_0_am__U1408":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U1409":{ + "modref":"corebit.and" + }, + "d_1_am__U1410":{ + "modref":"corebit.and" + }, + "d_1_am__U1411":{ + "modref":"corebit.and" + }, + "d_1_am__U1412":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_am__U1413":{ + "modref":"corebit.and" + }, + "d_2_am__U1414":{ + "modref":"corebit.and" + }, + "d_2_am__U1415":{ + "modref":"corebit.and" + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, - "_U1429":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func":{ - "modref":"global.aff__U1420" + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cmp_time":{ - "genref":"coreir.eq", + "d_2_next_value_at_max":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_0_am__U1430":{ + "d_3_am__U1416":{ "modref":"corebit.and" }, - "d_0_at_max":{ + "d_3_am__U1417":{ + "modref":"corebit.and" + }, + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, - "d_0_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg":{ + "d_3_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_4_am__U1418":{ + "modref":"corebit.and" + }, + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_min":{ + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_5_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_5_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_5_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg":{ + "d_5_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -9615,22 +9487,42 @@ } }, "connections":[ - ["d_0_inc.in1","_U1428.out"], - ["d_1_inc.in1","_U1428.out"], - ["cmp_time.in1","_U1429.out"], + ["d_0_inc.in1","_U1402.out"], + ["d_1_inc.in1","_U1402.out"], + ["d_2_inc.in1","_U1402.out"], + ["d_3_inc.in1","_U1402.out"], + ["d_4_inc.in1","_U1402.out"], + ["d_5_inc.in1","_U1402.out"], + ["cmp_time.in1","_U1403.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["d_4_reg.out","affine_func.d.4"], + ["d_5_reg.out","affine_func.d.5"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["d_4_reg.en","cmp_time.out"], + ["d_5_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1430.in0"], - ["d_1_at_max.out","d_0_am__U1430.in1"], - ["d_0_next_value.sel","d_0_am__U1430.out"], + ["true.out","d_0_am__U1404.in0"], + ["d_1_at_max.out","d_0_am__U1404.in1"], + ["d_0_am__U1405.in0","d_0_am__U1404.out"], + ["d_2_at_max.out","d_0_am__U1405.in1"], + ["d_0_am__U1406.in0","d_0_am__U1405.out"], + ["d_3_at_max.out","d_0_am__U1406.in1"], + ["d_0_am__U1407.in0","d_0_am__U1406.out"], + ["d_4_at_max.out","d_0_am__U1407.in1"], + ["d_0_am__U1408.in0","d_0_am__U1407.out"], + ["d_5_at_max.out","d_0_am__U1408.in1"], + ["d_0_next_value.sel","d_0_am__U1408.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9643,6 +9535,15 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U1409.in0"], + ["d_2_at_max.out","d_1_am__U1409.in1"], + ["d_1_am__U1410.in0","d_1_am__U1409.out"], + ["d_3_at_max.out","d_1_am__U1410.in1"], + ["d_1_am__U1411.in0","d_1_am__U1410.out"], + ["d_4_at_max.out","d_1_am__U1411.in1"], + ["d_1_am__U1412.in0","d_1_am__U1411.out"], + ["d_5_at_max.out","d_1_am__U1412.in1"], + ["d_1_next_value.sel","d_1_am__U1412.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -9652,32 +9553,95 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U1413.in0"], + ["d_3_at_max.out","d_2_am__U1413.in1"], + ["d_2_am__U1414.in0","d_2_am__U1413.out"], + ["d_4_at_max.out","d_2_am__U1414.in1"], + ["d_2_am__U1415.in0","d_2_am__U1414.out"], + ["d_5_at_max.out","d_2_am__U1415.in1"], + ["d_2_next_value.sel","d_2_am__U1415.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["true.out","d_3_am__U1416.in0"], + ["d_4_at_max.out","d_3_am__U1416.in1"], + ["d_3_am__U1417.in0","d_3_am__U1416.out"], + ["d_5_at_max.out","d_3_am__U1417.in1"], + ["d_3_next_value.sel","d_3_am__U1417.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"], + ["true.out","d_4_am__U1418.in0"], + ["d_5_at_max.out","d_4_am__U1418.in1"], + ["d_4_next_value.sel","d_4_am__U1418.out"], + ["d_4_reg.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg.in","d_4_next_value.out"], + ["self.clk","d_4_reg.clk"], + ["self.rst_n","d_4_reg.clr"], + ["self.d.4","d_4_reg.out"], + ["d_5_reg.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg.in","d_5_next_value.out"], + ["true.out","d_5_next_value.sel"], + ["self.clk","d_5_reg.clk"], + ["self.rst_n","d_5_reg.clr"], + ["self.d.5","d_5_reg.out"] ] }, - "affine_controller__U1434":{ + "affine_controller__U1441":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1443":{ + "_U1456":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1444":{ + "_U1457":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1435" + "modref":"global.aff__U1442" }, "cmp_time":{ "genref":"coreir.eq", @@ -9687,7 +9651,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1445":{ + "d_0_am__U1458":{ + "modref":"corebit.and" + }, + "d_0_am__U1459":{ + "modref":"corebit.and" + }, + "d_0_am__U1460":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -9721,6 +9691,12 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1461":{ + "modref":"corebit.and" + }, + "d_1_am__U1462":{ + "modref":"corebit.and" + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -9732,7 +9708,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_1_min":{ "genref":"coreir.const", @@ -9752,149 +9728,67 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U1443.out"], - ["d_1_inc.in1","_U1443.out"], - ["cmp_time.in1","_U1444.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1445.in0"], - ["d_1_at_max.out","d_0_am__U1445.in1"], - ["d_0_next_value.sel","d_0_am__U1445.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] - ] - }, - "affine_controller__U1449":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1458":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1459":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U1450" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U1460":{ + "d_2_am__U1463":{ "modref":"corebit.and" }, - "d_0_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, - "d_0_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg":{ + "d_2_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_1_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg":{ + "d_3_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -9909,21 +9803,31 @@ } }, "connections":[ - ["d_0_inc.in1","_U1458.out"], - ["d_1_inc.in1","_U1458.out"], - ["cmp_time.in1","_U1459.out"], + ["d_0_inc.in1","_U1456.out"], + ["d_1_inc.in1","_U1456.out"], + ["d_2_inc.in1","_U1456.out"], + ["d_3_inc.in1","_U1456.out"], + ["cmp_time.in1","_U1457.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1460.in0"], - ["d_1_at_max.out","d_0_am__U1460.in1"], + ["true.out","d_0_am__U1458.in0"], + ["d_1_at_max.out","d_0_am__U1458.in1"], + ["d_0_am__U1459.in0","d_0_am__U1458.out"], + ["d_2_at_max.out","d_0_am__U1459.in1"], + ["d_0_am__U1460.in0","d_0_am__U1459.out"], + ["d_3_at_max.out","d_0_am__U1460.in1"], ["d_0_next_value.sel","d_0_am__U1460.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], @@ -9937,6 +9841,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U1461.in0"], + ["d_2_at_max.out","d_1_am__U1461.in1"], + ["d_1_am__U1462.in0","d_1_am__U1461.out"], + ["d_3_at_max.out","d_1_am__U1462.in1"], + ["d_1_next_value.sel","d_1_am__U1462.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -9946,32 +9855,59 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], - ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"] + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U1463.in0"], + ["d_3_at_max.out","d_2_am__U1463.in1"], + ["d_2_next_value.sel","d_2_am__U1463.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U1464":{ + "affine_controller__U1481":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",6,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1485":{ + "_U1496":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1486":{ + "_U1497":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1465" + "modref":"global.aff__U1482" }, "cmp_time":{ "genref":"coreir.eq", @@ -9981,19 +9917,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1487":{ - "modref":"corebit.and" - }, - "d_0_am__U1488":{ + "d_0_am__U1498":{ "modref":"corebit.and" }, - "d_0_am__U1489":{ + "d_0_am__U1499":{ "modref":"corebit.and" }, - "d_0_am__U1490":{ - "modref":"corebit.and" - }, - "d_0_am__U1491":{ + "d_0_am__U1500":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -10027,16 +9957,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1492":{ - "modref":"corebit.and" - }, - "d_1_am__U1493":{ + "d_1_am__U1501":{ "modref":"corebit.and" }, - "d_1_am__U1494":{ - "modref":"corebit.and" - }, - "d_1_am__U1495":{ + "d_1_am__U1502":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -10050,7 +9974,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_1_min":{ "genref":"coreir.const", @@ -10070,13 +9994,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1496":{ - "modref":"corebit.and" - }, - "d_2_am__U1497":{ - "modref":"corebit.and" - }, - "d_2_am__U1498":{ + "d_2_am__U1503":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -10110,12 +10028,6 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U1499":{ - "modref":"corebit.and" - }, - "d_3_am__U1500":{ - "modref":"corebit.and" - }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -10127,7 +10039,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, "d_3_min":{ "genref":"coreir.const", @@ -10147,67 +10059,191 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U1501":{ + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U1496.out"], + ["d_1_inc.in1","_U1496.out"], + ["d_2_inc.in1","_U1496.out"], + ["d_3_inc.in1","_U1496.out"], + ["cmp_time.in1","_U1497.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U1498.in0"], + ["d_1_at_max.out","d_0_am__U1498.in1"], + ["d_0_am__U1499.in0","d_0_am__U1498.out"], + ["d_2_at_max.out","d_0_am__U1499.in1"], + ["d_0_am__U1500.in0","d_0_am__U1499.out"], + ["d_3_at_max.out","d_0_am__U1500.in1"], + ["d_0_next_value.sel","d_0_am__U1500.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U1501.in0"], + ["d_2_at_max.out","d_1_am__U1501.in1"], + ["d_1_am__U1502.in0","d_1_am__U1501.out"], + ["d_3_at_max.out","d_1_am__U1502.in1"], + ["d_1_next_value.sel","d_1_am__U1502.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U1503.in0"], + ["d_3_at_max.out","d_2_am__U1503.in1"], + ["d_2_next_value.sel","d_2_am__U1503.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] + ] + }, + "affine_controller__U15":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U16" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U26":{ "modref":"corebit.and" }, - "d_4_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg":{ + "d_0_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg":{ + "d_1_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -10222,42 +10258,22 @@ } }, "connections":[ - ["d_0_inc.in1","_U1485.out"], - ["d_1_inc.in1","_U1485.out"], - ["d_2_inc.in1","_U1485.out"], - ["d_3_inc.in1","_U1485.out"], - ["d_4_inc.in1","_U1485.out"], - ["d_5_inc.in1","_U1485.out"], - ["cmp_time.in1","_U1486.out"], + ["d_0_inc.in1","_U24.out"], + ["d_1_inc.in1","_U24.out"], + ["cmp_time.in1","_U25.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["d_4_reg.out","affine_func.d.4"], - ["d_5_reg.out","affine_func.d.5"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["d_4_reg.en","cmp_time.out"], - ["d_5_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1487.in0"], - ["d_1_at_max.out","d_0_am__U1487.in1"], - ["d_0_am__U1488.in0","d_0_am__U1487.out"], - ["d_2_at_max.out","d_0_am__U1488.in1"], - ["d_0_am__U1489.in0","d_0_am__U1488.out"], - ["d_3_at_max.out","d_0_am__U1489.in1"], - ["d_0_am__U1490.in0","d_0_am__U1489.out"], - ["d_4_at_max.out","d_0_am__U1490.in1"], - ["d_0_am__U1491.in0","d_0_am__U1490.out"], - ["d_5_at_max.out","d_0_am__U1491.in1"], - ["d_0_next_value.sel","d_0_am__U1491.out"], + ["true.out","d_0_am__U26.in0"], + ["d_1_at_max.out","d_0_am__U26.in1"], + ["d_0_next_value.sel","d_0_am__U26.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10270,15 +10286,6 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U1492.in0"], - ["d_2_at_max.out","d_1_am__U1492.in1"], - ["d_1_am__U1493.in0","d_1_am__U1492.out"], - ["d_3_at_max.out","d_1_am__U1493.in1"], - ["d_1_am__U1494.in0","d_1_am__U1493.out"], - ["d_4_at_max.out","d_1_am__U1494.in1"], - ["d_1_am__U1495.in0","d_1_am__U1494.out"], - ["d_5_at_max.out","d_1_am__U1495.in1"], - ["d_1_next_value.sel","d_1_am__U1495.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10288,95 +10295,32 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U1496.in0"], - ["d_3_at_max.out","d_2_am__U1496.in1"], - ["d_2_am__U1497.in0","d_2_am__U1496.out"], - ["d_4_at_max.out","d_2_am__U1497.in1"], - ["d_2_am__U1498.in0","d_2_am__U1497.out"], - ["d_5_at_max.out","d_2_am__U1498.in1"], - ["d_2_next_value.sel","d_2_am__U1498.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U1499.in0"], - ["d_4_at_max.out","d_3_am__U1499.in1"], - ["d_3_am__U1500.in0","d_3_am__U1499.out"], - ["d_5_at_max.out","d_3_am__U1500.in1"], - ["d_3_next_value.sel","d_3_am__U1500.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U1501.in0"], - ["d_5_at_max.out","d_4_am__U1501.in1"], - ["d_4_next_value.sel","d_4_am__U1501.out"], - ["d_4_reg.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg.in","d_4_next_value.out"], - ["self.clk","d_4_reg.clk"], - ["self.rst_n","d_4_reg.clr"], - ["self.d.4","d_4_reg.out"], - ["d_5_reg.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg.in","d_5_next_value.out"], - ["true.out","d_5_next_value.sel"], - ["self.clk","d_5_reg.clk"], - ["self.rst_n","d_5_reg.clr"], - ["self.d.5","d_5_reg.out"] + ["true.out","d_1_next_value.sel"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U1524":{ + "affine_controller__U151":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",7,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1539":{ + "_U175":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1540":{ + "_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1525" + "modref":"global.aff__U152" }, "cmp_time":{ "genref":"coreir.eq", @@ -10386,13 +10330,22 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1541":{ + "d_0_am__U177":{ + "modref":"corebit.and" + }, + "d_0_am__U178":{ + "modref":"corebit.and" + }, + "d_0_am__U179":{ + "modref":"corebit.and" + }, + "d_0_am__U180":{ "modref":"corebit.and" }, - "d_0_am__U1542":{ + "d_0_am__U181":{ "modref":"corebit.and" }, - "d_0_am__U1543":{ + "d_0_am__U182":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -10426,10 +10379,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1544":{ + "d_1_am__U183":{ + "modref":"corebit.and" + }, + "d_1_am__U184":{ + "modref":"corebit.and" + }, + "d_1_am__U185":{ + "modref":"corebit.and" + }, + "d_1_am__U186":{ "modref":"corebit.and" }, - "d_1_am__U1545":{ + "d_1_am__U187":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -10443,7 +10405,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -10463,7 +10425,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1546":{ + "d_2_am__U188":{ + "modref":"corebit.and" + }, + "d_2_am__U189":{ + "modref":"corebit.and" + }, + "d_2_am__U190":{ + "modref":"corebit.and" + }, + "d_2_am__U191":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -10477,7 +10448,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -10497,6 +10468,15 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U192":{ + "modref":"corebit.and" + }, + "d_3_am__U193":{ + "modref":"corebit.and" + }, + "d_3_am__U194":{ + "modref":"corebit.and" + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -10508,7 +10488,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, "d_3_min":{ "genref":"coreir.const", @@ -10528,6 +10508,108 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, + "d_4_am__U195":{ + "modref":"corebit.and" + }, + "d_4_am__U196":{ + "modref":"corebit.and" + }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_5_am__U197":{ + "modref":"corebit.and" + }, + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000003"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -10538,32 +10620,47 @@ } }, "connections":[ - ["d_0_inc.in1","_U1539.out"], - ["d_1_inc.in1","_U1539.out"], - ["d_2_inc.in1","_U1539.out"], - ["d_3_inc.in1","_U1539.out"], - ["cmp_time.in1","_U1540.out"], + ["d_0_inc.in1","_U175.out"], + ["d_1_inc.in1","_U175.out"], + ["d_2_inc.in1","_U175.out"], + ["d_3_inc.in1","_U175.out"], + ["d_4_inc.in1","_U175.out"], + ["d_5_inc.in1","_U175.out"], + ["d_6_inc.in1","_U175.out"], + ["cmp_time.in1","_U176.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], ["d_3_reg.out","affine_func.d.3"], + ["d_4_reg.out","affine_func.d.4"], + ["d_5_reg.out","affine_func.d.5"], + ["d_6_reg.out","affine_func.d.6"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], ["d_3_reg.en","cmp_time.out"], + ["d_4_reg.en","cmp_time.out"], + ["d_5_reg.en","cmp_time.out"], + ["d_6_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1541.in0"], - ["d_1_at_max.out","d_0_am__U1541.in1"], - ["d_0_am__U1542.in0","d_0_am__U1541.out"], - ["d_2_at_max.out","d_0_am__U1542.in1"], - ["d_0_am__U1543.in0","d_0_am__U1542.out"], - ["d_3_at_max.out","d_0_am__U1543.in1"], - ["d_0_next_value.sel","d_0_am__U1543.out"], + ["true.out","d_0_am__U177.in0"], + ["d_1_at_max.out","d_0_am__U177.in1"], + ["d_0_am__U178.in0","d_0_am__U177.out"], + ["d_2_at_max.out","d_0_am__U178.in1"], + ["d_0_am__U179.in0","d_0_am__U178.out"], + ["d_3_at_max.out","d_0_am__U179.in1"], + ["d_0_am__U180.in0","d_0_am__U179.out"], + ["d_4_at_max.out","d_0_am__U180.in1"], + ["d_0_am__U181.in0","d_0_am__U180.out"], + ["d_5_at_max.out","d_0_am__U181.in1"], + ["d_0_am__U182.in0","d_0_am__U181.out"], + ["d_6_at_max.out","d_0_am__U182.in1"], + ["d_0_next_value.sel","d_0_am__U182.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10576,11 +10673,17 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U1544.in0"], - ["d_2_at_max.out","d_1_am__U1544.in1"], - ["d_1_am__U1545.in0","d_1_am__U1544.out"], - ["d_3_at_max.out","d_1_am__U1545.in1"], - ["d_1_next_value.sel","d_1_am__U1545.out"], + ["true.out","d_1_am__U183.in0"], + ["d_2_at_max.out","d_1_am__U183.in1"], + ["d_1_am__U184.in0","d_1_am__U183.out"], + ["d_3_at_max.out","d_1_am__U184.in1"], + ["d_1_am__U185.in0","d_1_am__U184.out"], + ["d_4_at_max.out","d_1_am__U185.in1"], + ["d_1_am__U186.in0","d_1_am__U185.out"], + ["d_5_at_max.out","d_1_am__U186.in1"], + ["d_1_am__U187.in0","d_1_am__U186.out"], + ["d_6_at_max.out","d_1_am__U187.in1"], + ["d_1_next_value.sel","d_1_am__U187.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10593,9 +10696,15 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U1546.in0"], - ["d_3_at_max.out","d_2_am__U1546.in1"], - ["d_2_next_value.sel","d_2_am__U1546.out"], + ["true.out","d_2_am__U188.in0"], + ["d_3_at_max.out","d_2_am__U188.in1"], + ["d_2_am__U189.in0","d_2_am__U188.out"], + ["d_4_at_max.out","d_2_am__U189.in1"], + ["d_2_am__U190.in0","d_2_am__U189.out"], + ["d_5_at_max.out","d_2_am__U190.in1"], + ["d_2_am__U191.in0","d_2_am__U190.out"], + ["d_6_at_max.out","d_2_am__U191.in1"], + ["d_2_next_value.sel","d_2_am__U191.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -10608,6 +10717,13 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], + ["true.out","d_3_am__U192.in0"], + ["d_4_at_max.out","d_3_am__U192.in1"], + ["d_3_am__U193.in0","d_3_am__U192.out"], + ["d_5_at_max.out","d_3_am__U193.in1"], + ["d_3_am__U194.in0","d_3_am__U193.out"], + ["d_6_at_max.out","d_3_am__U194.in1"], + ["d_3_next_value.sel","d_3_am__U194.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -10617,32 +10733,76 @@ ["d_3_reg.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + ["self.d.3","d_3_reg.out"], + ["true.out","d_4_am__U195.in0"], + ["d_5_at_max.out","d_4_am__U195.in1"], + ["d_4_am__U196.in0","d_4_am__U195.out"], + ["d_6_at_max.out","d_4_am__U196.in1"], + ["d_4_next_value.sel","d_4_am__U196.out"], + ["d_4_reg.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg.in","d_4_next_value.out"], + ["self.clk","d_4_reg.clk"], + ["self.rst_n","d_4_reg.clr"], + ["self.d.4","d_4_reg.out"], + ["true.out","d_5_am__U197.in0"], + ["d_6_at_max.out","d_5_am__U197.in1"], + ["d_5_next_value.sel","d_5_am__U197.out"], + ["d_5_reg.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg.in","d_5_next_value.out"], + ["self.clk","d_5_reg.clk"], + ["self.rst_n","d_5_reg.clr"], + ["self.d.5","d_5_reg.out"], + ["d_6_reg.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg.in","d_6_next_value.out"], + ["true.out","d_6_next_value.sel"], + ["self.clk","d_6_reg.clk"], + ["self.rst_n","d_6_reg.clr"], + ["self.d.6","d_6_reg.out"] ] }, - "affine_controller__U1564":{ + "affine_controller__U225":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1579":{ + "_U234":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1580":{ + "_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1565" + "modref":"global.aff__U226" }, "cmp_time":{ "genref":"coreir.eq", @@ -10652,13 +10812,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1581":{ - "modref":"corebit.and" - }, - "d_0_am__U1582":{ - "modref":"corebit.and" - }, - "d_0_am__U1583":{ + "d_0_am__U236":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -10692,12 +10846,6 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1584":{ - "modref":"corebit.and" - }, - "d_1_am__U1585":{ - "modref":"corebit.and" - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -10709,7 +10857,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -10720,76 +10868,11 @@ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U1586":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg":{ + "d_1_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -10804,32 +10887,22 @@ } }, "connections":[ - ["d_0_inc.in1","_U1579.out"], - ["d_1_inc.in1","_U1579.out"], - ["d_2_inc.in1","_U1579.out"], - ["d_3_inc.in1","_U1579.out"], - ["cmp_time.in1","_U1580.out"], + ["d_0_inc.in1","_U234.out"], + ["d_1_inc.in1","_U234.out"], + ["cmp_time.in1","_U235.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1581.in0"], - ["d_1_at_max.out","d_0_am__U1581.in1"], - ["d_0_am__U1582.in0","d_0_am__U1581.out"], - ["d_2_at_max.out","d_0_am__U1582.in1"], - ["d_0_am__U1583.in0","d_0_am__U1582.out"], - ["d_3_at_max.out","d_0_am__U1583.in1"], - ["d_0_next_value.sel","d_0_am__U1583.out"], + ["true.out","d_0_am__U236.in0"], + ["d_1_at_max.out","d_0_am__U236.in1"], + ["d_0_next_value.sel","d_0_am__U236.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10842,11 +10915,6 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U1584.in0"], - ["d_2_at_max.out","d_1_am__U1584.in1"], - ["d_1_am__U1585.in0","d_1_am__U1584.out"], - ["d_3_at_max.out","d_1_am__U1585.in1"], - ["d_1_next_value.sel","d_1_am__U1585.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10856,40 +10924,13 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U1586.in0"], - ["d_3_at_max.out","d_2_am__U1586.in1"], - ["d_2_next_value.sel","d_2_am__U1586.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U16":{ + "affine_controller__U239":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -10897,18 +10938,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U25":{ + "_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U26":{ + "_U249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U17" + "modref":"global.aff__U240" }, "cmp_time":{ "genref":"coreir.eq", @@ -10918,7 +10959,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U27":{ + "d_0_am__U250":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -10993,9 +11034,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U25.out"], - ["d_1_inc.in1","_U25.out"], - ["cmp_time.in1","_U26.out"], + ["d_0_inc.in1","_U248.out"], + ["d_1_inc.in1","_U248.out"], + ["cmp_time.in1","_U249.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -11006,9 +11047,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U27.in0"], - ["d_1_at_max.out","d_0_am__U27.in1"], - ["d_0_next_value.sel","d_0_am__U27.out"], + ["true.out","d_0_am__U250.in0"], + ["d_1_at_max.out","d_0_am__U250.in1"], + ["d_0_next_value.sel","d_0_am__U250.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11036,26 +11077,26 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U160":{ + "affine_controller__U253":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",7,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U184":{ + "_U262":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U185":{ + "_U263":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U161" + "modref":"global.aff__U254" }, "cmp_time":{ "genref":"coreir.eq", @@ -11065,22 +11106,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U186":{ - "modref":"corebit.and" - }, - "d_0_am__U187":{ - "modref":"corebit.and" - }, - "d_0_am__U188":{ - "modref":"corebit.and" - }, - "d_0_am__U189":{ - "modref":"corebit.and" - }, - "d_0_am__U190":{ - "modref":"corebit.and" - }, - "d_0_am__U191":{ + "d_0_am__U264":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -11114,21 +11140,6 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U192":{ - "modref":"corebit.and" - }, - "d_1_am__U193":{ - "modref":"corebit.and" - }, - "d_1_am__U194":{ - "modref":"corebit.and" - }, - "d_1_am__U195":{ - "modref":"corebit.and" - }, - "d_1_am__U196":{ - "modref":"corebit.and" - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -11140,7 +11151,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -11160,187 +11171,296 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U197":{ - "modref":"corebit.and" + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} }, - "d_2_am__U198":{ - "modref":"corebit.and" + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U262.out"], + ["d_1_inc.in1","_U262.out"], + ["cmp_time.in1","_U263.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U264.in0"], + ["d_1_at_max.out","d_0_am__U264.in1"], + ["d_0_next_value.sel","d_0_am__U264.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"] + ] + }, + "affine_controller__U267":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U276":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_am__U199":{ - "modref":"corebit.and" + "_U277":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U268" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_2_am__U200":{ + "d_0_am__U278":{ "modref":"corebit.and" }, - "d_2_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_2_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg":{ + "d_0_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U201":{ - "modref":"corebit.and" - }, - "d_3_am__U202":{ - "modref":"corebit.and" - }, - "d_3_am__U203":{ - "modref":"corebit.and" - }, - "d_3_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_3_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg":{ + "d_1_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U204":{ - "modref":"corebit.and" - }, - "d_4_am__U205":{ - "modref":"corebit.and" - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", + "time_diff":{ + "genref":"coreir.sub", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U276.out"], + ["d_1_inc.in1","_U276.out"], + ["cmp_time.in1","_U277.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U278.in0"], + ["d_1_at_max.out","d_0_am__U278.in1"], + ["d_0_next_value.sel","d_0_am__U278.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"] + ] + }, + "affine_controller__U281":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_4_min":{ + "_U291":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func":{ + "modref":"global.aff__U282" }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", + "cmp_time":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_5_am__U206":{ + "d_0_am__U292":{ "modref":"corebit.and" }, - "d_5_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg":{ + "d_0_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_6_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_6_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg":{ + "d_1_reg":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} @@ -11355,47 +11475,22 @@ } }, "connections":[ - ["d_0_inc.in1","_U184.out"], - ["d_1_inc.in1","_U184.out"], - ["d_2_inc.in1","_U184.out"], - ["d_3_inc.in1","_U184.out"], - ["d_4_inc.in1","_U184.out"], - ["d_5_inc.in1","_U184.out"], - ["d_6_inc.in1","_U184.out"], - ["cmp_time.in1","_U185.out"], + ["d_0_inc.in1","_U290.out"], + ["d_1_inc.in1","_U290.out"], + ["cmp_time.in1","_U291.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["d_4_reg.out","affine_func.d.4"], - ["d_5_reg.out","affine_func.d.5"], - ["d_6_reg.out","affine_func.d.6"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["d_4_reg.en","cmp_time.out"], - ["d_5_reg.en","cmp_time.out"], - ["d_6_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U186.in0"], - ["d_1_at_max.out","d_0_am__U186.in1"], - ["d_0_am__U187.in0","d_0_am__U186.out"], - ["d_2_at_max.out","d_0_am__U187.in1"], - ["d_0_am__U188.in0","d_0_am__U187.out"], - ["d_3_at_max.out","d_0_am__U188.in1"], - ["d_0_am__U189.in0","d_0_am__U188.out"], - ["d_4_at_max.out","d_0_am__U189.in1"], - ["d_0_am__U190.in0","d_0_am__U189.out"], - ["d_5_at_max.out","d_0_am__U190.in1"], - ["d_0_am__U191.in0","d_0_am__U190.out"], - ["d_6_at_max.out","d_0_am__U191.in1"], - ["d_0_next_value.sel","d_0_am__U191.out"], + ["true.out","d_0_am__U292.in0"], + ["d_1_at_max.out","d_0_am__U292.in1"], + ["d_0_next_value.sel","d_0_am__U292.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11408,17 +11503,6 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U192.in0"], - ["d_2_at_max.out","d_1_am__U192.in1"], - ["d_1_am__U193.in0","d_1_am__U192.out"], - ["d_3_at_max.out","d_1_am__U193.in1"], - ["d_1_am__U194.in0","d_1_am__U193.out"], - ["d_4_at_max.out","d_1_am__U194.in1"], - ["d_1_am__U195.in0","d_1_am__U194.out"], - ["d_5_at_max.out","d_1_am__U195.in1"], - ["d_1_am__U196.in0","d_1_am__U195.out"], - ["d_6_at_max.out","d_1_am__U196.in1"], - ["d_1_next_value.sel","d_1_am__U196.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -11428,97 +11512,13 @@ ["d_1_reg.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg.in","d_1_next_value.out"], + ["true.out","d_1_next_value.sel"], ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U197.in0"], - ["d_3_at_max.out","d_2_am__U197.in1"], - ["d_2_am__U198.in0","d_2_am__U197.out"], - ["d_4_at_max.out","d_2_am__U198.in1"], - ["d_2_am__U199.in0","d_2_am__U198.out"], - ["d_5_at_max.out","d_2_am__U199.in1"], - ["d_2_am__U200.in0","d_2_am__U199.out"], - ["d_6_at_max.out","d_2_am__U200.in1"], - ["d_2_next_value.sel","d_2_am__U200.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U201.in0"], - ["d_4_at_max.out","d_3_am__U201.in1"], - ["d_3_am__U202.in0","d_3_am__U201.out"], - ["d_5_at_max.out","d_3_am__U202.in1"], - ["d_3_am__U203.in0","d_3_am__U202.out"], - ["d_6_at_max.out","d_3_am__U203.in1"], - ["d_3_next_value.sel","d_3_am__U203.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U204.in0"], - ["d_5_at_max.out","d_4_am__U204.in1"], - ["d_4_am__U205.in0","d_4_am__U204.out"], - ["d_6_at_max.out","d_4_am__U205.in1"], - ["d_4_next_value.sel","d_4_am__U205.out"], - ["d_4_reg.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg.in","d_4_next_value.out"], - ["self.clk","d_4_reg.clk"], - ["self.rst_n","d_4_reg.clr"], - ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U206.in0"], - ["d_6_at_max.out","d_5_am__U206.in1"], - ["d_5_next_value.sel","d_5_am__U206.out"], - ["d_5_reg.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg.in","d_5_next_value.out"], - ["self.clk","d_5_reg.clk"], - ["self.rst_n","d_5_reg.clr"], - ["self.d.5","d_5_reg.out"], - ["d_6_reg.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg.in","d_6_next_value.out"], - ["true.out","d_6_next_value.sel"], - ["self.clk","d_6_reg.clk"], - ["self.rst_n","d_6_reg.clr"], - ["self.d.6","d_6_reg.out"] + ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U234":{ + "affine_controller__U29":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -11526,18 +11526,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U243":{ + "_U38":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U244":{ + "_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U235" + "modref":"global.aff__U30" }, "cmp_time":{ "genref":"coreir.eq", @@ -11547,7 +11547,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U245":{ + "d_0_am__U40":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -11622,9 +11622,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U243.out"], - ["d_1_inc.in1","_U243.out"], - ["cmp_time.in1","_U244.out"], + ["d_0_inc.in1","_U38.out"], + ["d_1_inc.in1","_U38.out"], + ["cmp_time.in1","_U39.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -11635,9 +11635,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U245.in0"], - ["d_1_at_max.out","d_0_am__U245.in1"], - ["d_0_next_value.sel","d_0_am__U245.out"], + ["true.out","d_0_am__U40.in0"], + ["d_1_at_max.out","d_0_am__U40.in1"], + ["d_0_next_value.sel","d_0_am__U40.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11665,7 +11665,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U249":{ + "affine_controller__U295":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -11673,18 +11673,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U258":{ + "_U304":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U259":{ + "_U305":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U250" + "modref":"global.aff__U296" }, "cmp_time":{ "genref":"coreir.eq", @@ -11694,7 +11694,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U260":{ + "d_0_am__U306":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -11769,9 +11769,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U258.out"], - ["d_1_inc.in1","_U258.out"], - ["cmp_time.in1","_U259.out"], + ["d_0_inc.in1","_U304.out"], + ["d_1_inc.in1","_U304.out"], + ["cmp_time.in1","_U305.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -11782,9 +11782,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U260.in0"], - ["d_1_at_max.out","d_0_am__U260.in1"], - ["d_0_next_value.sel","d_0_am__U260.out"], + ["true.out","d_0_am__U306.in0"], + ["d_1_at_max.out","d_0_am__U306.in1"], + ["d_0_next_value.sel","d_0_am__U306.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11812,7 +11812,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U264":{ + "affine_controller__U309":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -11820,18 +11820,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U273":{ + "_U318":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U274":{ + "_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U265" + "modref":"global.aff__U310" }, "cmp_time":{ "genref":"coreir.eq", @@ -11841,7 +11841,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U275":{ + "d_0_am__U320":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -11916,9 +11916,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U273.out"], - ["d_1_inc.in1","_U273.out"], - ["cmp_time.in1","_U274.out"], + ["d_0_inc.in1","_U318.out"], + ["d_1_inc.in1","_U318.out"], + ["cmp_time.in1","_U319.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -11929,9 +11929,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U275.in0"], - ["d_1_at_max.out","d_0_am__U275.in1"], - ["d_0_next_value.sel","d_0_am__U275.out"], + ["true.out","d_0_am__U320.in0"], + ["d_1_at_max.out","d_0_am__U320.in1"], + ["d_0_next_value.sel","d_0_am__U320.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11959,7 +11959,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U279":{ + "affine_controller__U323":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -11967,18 +11967,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U288":{ + "_U332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U289":{ + "_U333":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U280" + "modref":"global.aff__U324" }, "cmp_time":{ "genref":"coreir.eq", @@ -11988,7 +11988,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U290":{ + "d_0_am__U334":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -12063,9 +12063,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U288.out"], - ["d_1_inc.in1","_U288.out"], - ["cmp_time.in1","_U289.out"], + ["d_0_inc.in1","_U332.out"], + ["d_1_inc.in1","_U332.out"], + ["cmp_time.in1","_U333.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -12076,9 +12076,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U290.in0"], - ["d_1_at_max.out","d_0_am__U290.in1"], - ["d_0_next_value.sel","d_0_am__U290.out"], + ["true.out","d_0_am__U334.in0"], + ["d_1_at_max.out","d_0_am__U334.in1"], + ["d_0_next_value.sel","d_0_am__U334.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12106,7 +12106,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U294":{ + "affine_controller__U337":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12114,18 +12114,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U303":{ + "_U346":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U304":{ + "_U347":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U295" + "modref":"global.aff__U338" }, "cmp_time":{ "genref":"coreir.eq", @@ -12135,7 +12135,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U305":{ + "d_0_am__U348":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -12210,9 +12210,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U303.out"], - ["d_1_inc.in1","_U303.out"], - ["cmp_time.in1","_U304.out"], + ["d_0_inc.in1","_U346.out"], + ["d_1_inc.in1","_U346.out"], + ["cmp_time.in1","_U347.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -12223,9 +12223,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U305.in0"], - ["d_1_at_max.out","d_0_am__U305.in1"], - ["d_0_next_value.sel","d_0_am__U305.out"], + ["true.out","d_0_am__U348.in0"], + ["d_1_at_max.out","d_0_am__U348.in1"], + ["d_0_next_value.sel","d_0_am__U348.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12253,7 +12253,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U309":{ + "affine_controller__U351":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12261,18 +12261,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U318":{ + "_U360":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U319":{ + "_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U310" + "modref":"global.aff__U352" }, "cmp_time":{ "genref":"coreir.eq", @@ -12282,7 +12282,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U320":{ + "d_0_am__U362":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -12357,9 +12357,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U318.out"], - ["d_1_inc.in1","_U318.out"], - ["cmp_time.in1","_U319.out"], + ["d_0_inc.in1","_U360.out"], + ["d_1_inc.in1","_U360.out"], + ["cmp_time.in1","_U361.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -12370,9 +12370,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U320.in0"], - ["d_1_at_max.out","d_0_am__U320.in1"], - ["d_0_next_value.sel","d_0_am__U320.out"], + ["true.out","d_0_am__U362.in0"], + ["d_1_at_max.out","d_0_am__U362.in1"], + ["d_0_next_value.sel","d_0_am__U362.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12400,7 +12400,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U31":{ + "affine_controller__U365":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12408,18 +12408,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U40":{ + "_U374":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U41":{ + "_U375":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U32" + "modref":"global.aff__U366" }, "cmp_time":{ "genref":"coreir.eq", @@ -12429,7 +12429,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U42":{ + "d_0_am__U376":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -12504,9 +12504,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U40.out"], - ["d_1_inc.in1","_U40.out"], - ["cmp_time.in1","_U41.out"], + ["d_0_inc.in1","_U374.out"], + ["d_1_inc.in1","_U374.out"], + ["cmp_time.in1","_U375.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -12517,9 +12517,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U42.in0"], - ["d_1_at_max.out","d_0_am__U42.in1"], - ["d_0_next_value.sel","d_0_am__U42.out"], + ["true.out","d_0_am__U376.in0"], + ["d_1_at_max.out","d_0_am__U376.in1"], + ["d_0_next_value.sel","d_0_am__U376.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12547,7 +12547,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U324":{ + "affine_controller__U379":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12555,18 +12555,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U333":{ + "_U388":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U334":{ + "_U389":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U325" + "modref":"global.aff__U380" }, "cmp_time":{ "genref":"coreir.eq", @@ -12576,7 +12576,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U335":{ + "d_0_am__U390":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -12651,9 +12651,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U333.out"], - ["d_1_inc.in1","_U333.out"], - ["cmp_time.in1","_U334.out"], + ["d_0_inc.in1","_U388.out"], + ["d_1_inc.in1","_U388.out"], + ["cmp_time.in1","_U389.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -12664,9 +12664,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U335.in0"], - ["d_1_at_max.out","d_0_am__U335.in1"], - ["d_0_next_value.sel","d_0_am__U335.out"], + ["true.out","d_0_am__U390.in0"], + ["d_1_at_max.out","d_0_am__U390.in1"], + ["d_0_next_value.sel","d_0_am__U390.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12694,7 +12694,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U339":{ + "affine_controller__U393":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12702,18 +12702,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U348":{ + "_U402":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U349":{ + "_U403":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U340" + "modref":"global.aff__U394" }, "cmp_time":{ "genref":"coreir.eq", @@ -12723,7 +12723,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U350":{ + "d_0_am__U404":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -12798,9 +12798,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U348.out"], - ["d_1_inc.in1","_U348.out"], - ["cmp_time.in1","_U349.out"], + ["d_0_inc.in1","_U402.out"], + ["d_1_inc.in1","_U402.out"], + ["cmp_time.in1","_U403.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -12811,9 +12811,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U350.in0"], - ["d_1_at_max.out","d_0_am__U350.in1"], - ["d_0_next_value.sel","d_0_am__U350.out"], + ["true.out","d_0_am__U404.in0"], + ["d_1_at_max.out","d_0_am__U404.in1"], + ["d_0_next_value.sel","d_0_am__U404.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12841,7 +12841,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U354":{ + "affine_controller__U407":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12849,18 +12849,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U363":{ + "_U416":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U364":{ + "_U417":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U355" + "modref":"global.aff__U408" }, "cmp_time":{ "genref":"coreir.eq", @@ -12870,7 +12870,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U365":{ + "d_0_am__U418":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -12945,9 +12945,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U363.out"], - ["d_1_inc.in1","_U363.out"], - ["cmp_time.in1","_U364.out"], + ["d_0_inc.in1","_U416.out"], + ["d_1_inc.in1","_U416.out"], + ["cmp_time.in1","_U417.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -12958,9 +12958,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U365.in0"], - ["d_1_at_max.out","d_0_am__U365.in1"], - ["d_0_next_value.sel","d_0_am__U365.out"], + ["true.out","d_0_am__U418.in0"], + ["d_1_at_max.out","d_0_am__U418.in1"], + ["d_0_next_value.sel","d_0_am__U418.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12988,7 +12988,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U369":{ + "affine_controller__U421":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12996,18 +12996,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U378":{ + "_U430":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U379":{ + "_U431":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U370" + "modref":"global.aff__U422" }, "cmp_time":{ "genref":"coreir.eq", @@ -13017,7 +13017,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U380":{ + "d_0_am__U432":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -13092,9 +13092,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U378.out"], - ["d_1_inc.in1","_U378.out"], - ["cmp_time.in1","_U379.out"], + ["d_0_inc.in1","_U430.out"], + ["d_1_inc.in1","_U430.out"], + ["cmp_time.in1","_U431.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -13105,9 +13105,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U380.in0"], - ["d_1_at_max.out","d_0_am__U380.in1"], - ["d_0_next_value.sel","d_0_am__U380.out"], + ["true.out","d_0_am__U432.in0"], + ["d_1_at_max.out","d_0_am__U432.in1"], + ["d_0_next_value.sel","d_0_am__U432.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13135,7 +13135,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U384":{ + "affine_controller__U43":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -13143,18 +13143,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U393":{ + "_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U394":{ + "_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U385" + "modref":"global.aff__U44" }, "cmp_time":{ "genref":"coreir.eq", @@ -13164,7 +13164,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U395":{ + "d_0_am__U54":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -13239,9 +13239,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U393.out"], - ["d_1_inc.in1","_U393.out"], - ["cmp_time.in1","_U394.out"], + ["d_0_inc.in1","_U52.out"], + ["d_1_inc.in1","_U52.out"], + ["cmp_time.in1","_U53.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -13252,9 +13252,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U395.in0"], - ["d_1_at_max.out","d_0_am__U395.in1"], - ["d_0_next_value.sel","d_0_am__U395.out"], + ["true.out","d_0_am__U54.in0"], + ["d_1_at_max.out","d_0_am__U54.in1"], + ["d_0_next_value.sel","d_0_am__U54.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13282,7 +13282,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U399":{ + "affine_controller__U435":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -13290,18 +13290,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U408":{ + "_U444":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U409":{ + "_U445":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U400" + "modref":"global.aff__U436" }, "cmp_time":{ "genref":"coreir.eq", @@ -13311,7 +13311,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U410":{ + "d_0_am__U446":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -13386,9 +13386,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U408.out"], - ["d_1_inc.in1","_U408.out"], - ["cmp_time.in1","_U409.out"], + ["d_0_inc.in1","_U444.out"], + ["d_1_inc.in1","_U444.out"], + ["cmp_time.in1","_U445.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -13399,9 +13399,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U410.in0"], - ["d_1_at_max.out","d_0_am__U410.in1"], - ["d_0_next_value.sel","d_0_am__U410.out"], + ["true.out","d_0_am__U446.in0"], + ["d_1_at_max.out","d_0_am__U446.in1"], + ["d_0_next_value.sel","d_0_am__U446.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13429,7 +13429,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U414":{ + "affine_controller__U449":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -13437,18 +13437,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U423":{ + "_U458":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U424":{ + "_U459":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U415" + "modref":"global.aff__U450" }, "cmp_time":{ "genref":"coreir.eq", @@ -13458,7 +13458,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U425":{ + "d_0_am__U460":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -13533,9 +13533,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U423.out"], - ["d_1_inc.in1","_U423.out"], - ["cmp_time.in1","_U424.out"], + ["d_0_inc.in1","_U458.out"], + ["d_1_inc.in1","_U458.out"], + ["cmp_time.in1","_U459.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -13546,9 +13546,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U425.in0"], - ["d_1_at_max.out","d_0_am__U425.in1"], - ["d_0_next_value.sel","d_0_am__U425.out"], + ["true.out","d_0_am__U460.in0"], + ["d_1_at_max.out","d_0_am__U460.in1"], + ["d_0_next_value.sel","d_0_am__U460.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13576,7 +13576,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U429":{ + "affine_controller__U463":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -13584,18 +13584,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U438":{ + "_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U439":{ + "_U473":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U430" + "modref":"global.aff__U464" }, "cmp_time":{ "genref":"coreir.eq", @@ -13605,7 +13605,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U440":{ + "d_0_am__U474":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -13680,9 +13680,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U438.out"], - ["d_1_inc.in1","_U438.out"], - ["cmp_time.in1","_U439.out"], + ["d_0_inc.in1","_U472.out"], + ["d_1_inc.in1","_U472.out"], + ["cmp_time.in1","_U473.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -13693,9 +13693,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U440.in0"], - ["d_1_at_max.out","d_0_am__U440.in1"], - ["d_0_next_value.sel","d_0_am__U440.out"], + ["true.out","d_0_am__U474.in0"], + ["d_1_at_max.out","d_0_am__U474.in1"], + ["d_0_next_value.sel","d_0_am__U474.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13723,7 +13723,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U444":{ + "affine_controller__U477":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -13731,18 +13731,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U453":{ + "_U486":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U454":{ + "_U487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U445" + "modref":"global.aff__U478" }, "cmp_time":{ "genref":"coreir.eq", @@ -13752,7 +13752,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U455":{ + "d_0_am__U488":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -13827,9 +13827,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U453.out"], - ["d_1_inc.in1","_U453.out"], - ["cmp_time.in1","_U454.out"], + ["d_0_inc.in1","_U486.out"], + ["d_1_inc.in1","_U486.out"], + ["cmp_time.in1","_U487.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -13840,9 +13840,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U455.in0"], - ["d_1_at_max.out","d_0_am__U455.in1"], - ["d_0_next_value.sel","d_0_am__U455.out"], + ["true.out","d_0_am__U488.in0"], + ["d_1_at_max.out","d_0_am__U488.in1"], + ["d_0_next_value.sel","d_0_am__U488.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13870,7 +13870,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U459":{ + "affine_controller__U491":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -13878,18 +13878,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U468":{ + "_U500":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U469":{ + "_U501":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U460" + "modref":"global.aff__U492" }, "cmp_time":{ "genref":"coreir.eq", @@ -13899,7 +13899,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U470":{ + "d_0_am__U502":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -13974,9 +13974,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U468.out"], - ["d_1_inc.in1","_U468.out"], - ["cmp_time.in1","_U469.out"], + ["d_0_inc.in1","_U500.out"], + ["d_1_inc.in1","_U500.out"], + ["cmp_time.in1","_U501.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -13987,9 +13987,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U470.in0"], - ["d_1_at_max.out","d_0_am__U470.in1"], - ["d_0_next_value.sel","d_0_am__U470.out"], + ["true.out","d_0_am__U502.in0"], + ["d_1_at_max.out","d_0_am__U502.in1"], + ["d_0_next_value.sel","d_0_am__U502.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14017,7 +14017,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U46":{ + "affine_controller__U505":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14025,18 +14025,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U55":{ + "_U514":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U56":{ + "_U515":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U47" + "modref":"global.aff__U506" }, "cmp_time":{ "genref":"coreir.eq", @@ -14046,7 +14046,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U57":{ + "d_0_am__U516":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -14121,9 +14121,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U55.out"], - ["d_1_inc.in1","_U55.out"], - ["cmp_time.in1","_U56.out"], + ["d_0_inc.in1","_U514.out"], + ["d_1_inc.in1","_U514.out"], + ["cmp_time.in1","_U515.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -14134,9 +14134,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U57.in0"], - ["d_1_at_max.out","d_0_am__U57.in1"], - ["d_0_next_value.sel","d_0_am__U57.out"], + ["true.out","d_0_am__U516.in0"], + ["d_1_at_max.out","d_0_am__U516.in1"], + ["d_0_next_value.sel","d_0_am__U516.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14164,7 +14164,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U474":{ + "affine_controller__U519":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14172,18 +14172,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U483":{ + "_U528":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U484":{ + "_U529":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U475" + "modref":"global.aff__U520" }, "cmp_time":{ "genref":"coreir.eq", @@ -14193,7 +14193,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U485":{ + "d_0_am__U530":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -14268,9 +14268,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U483.out"], - ["d_1_inc.in1","_U483.out"], - ["cmp_time.in1","_U484.out"], + ["d_0_inc.in1","_U528.out"], + ["d_1_inc.in1","_U528.out"], + ["cmp_time.in1","_U529.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -14281,9 +14281,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U485.in0"], - ["d_1_at_max.out","d_0_am__U485.in1"], - ["d_0_next_value.sel","d_0_am__U485.out"], + ["true.out","d_0_am__U530.in0"], + ["d_1_at_max.out","d_0_am__U530.in1"], + ["d_0_next_value.sel","d_0_am__U530.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14311,7 +14311,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U489":{ + "affine_controller__U533":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14319,18 +14319,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U498":{ + "_U542":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U499":{ + "_U543":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U490" + "modref":"global.aff__U534" }, "cmp_time":{ "genref":"coreir.eq", @@ -14340,7 +14340,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U500":{ + "d_0_am__U544":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -14415,9 +14415,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U498.out"], - ["d_1_inc.in1","_U498.out"], - ["cmp_time.in1","_U499.out"], + ["d_0_inc.in1","_U542.out"], + ["d_1_inc.in1","_U542.out"], + ["cmp_time.in1","_U543.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -14428,9 +14428,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U500.in0"], - ["d_1_at_max.out","d_0_am__U500.in1"], - ["d_0_next_value.sel","d_0_am__U500.out"], + ["true.out","d_0_am__U544.in0"], + ["d_1_at_max.out","d_0_am__U544.in1"], + ["d_0_next_value.sel","d_0_am__U544.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14458,7 +14458,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U504":{ + "affine_controller__U547":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14466,18 +14466,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U513":{ + "_U556":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U514":{ + "_U557":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U505" + "modref":"global.aff__U548" }, "cmp_time":{ "genref":"coreir.eq", @@ -14487,7 +14487,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U515":{ + "d_0_am__U558":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -14562,9 +14562,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U513.out"], - ["d_1_inc.in1","_U513.out"], - ["cmp_time.in1","_U514.out"], + ["d_0_inc.in1","_U556.out"], + ["d_1_inc.in1","_U556.out"], + ["cmp_time.in1","_U557.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -14575,9 +14575,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U515.in0"], - ["d_1_at_max.out","d_0_am__U515.in1"], - ["d_0_next_value.sel","d_0_am__U515.out"], + ["true.out","d_0_am__U558.in0"], + ["d_1_at_max.out","d_0_am__U558.in1"], + ["d_0_next_value.sel","d_0_am__U558.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14605,7 +14605,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U519":{ + "affine_controller__U561":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14613,18 +14613,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U528":{ + "_U570":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U529":{ + "_U571":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U520" + "modref":"global.aff__U562" }, "cmp_time":{ "genref":"coreir.eq", @@ -14634,7 +14634,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U530":{ + "d_0_am__U572":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -14709,9 +14709,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U528.out"], - ["d_1_inc.in1","_U528.out"], - ["cmp_time.in1","_U529.out"], + ["d_0_inc.in1","_U570.out"], + ["d_1_inc.in1","_U570.out"], + ["cmp_time.in1","_U571.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -14722,9 +14722,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U530.in0"], - ["d_1_at_max.out","d_0_am__U530.in1"], - ["d_0_next_value.sel","d_0_am__U530.out"], + ["true.out","d_0_am__U572.in0"], + ["d_1_at_max.out","d_0_am__U572.in1"], + ["d_0_next_value.sel","d_0_am__U572.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14752,7 +14752,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U534":{ + "affine_controller__U57":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14760,18 +14760,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U543":{ + "_U66":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U544":{ + "_U67":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U535" + "modref":"global.aff__U58" }, "cmp_time":{ "genref":"coreir.eq", @@ -14781,7 +14781,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U545":{ + "d_0_am__U68":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -14856,9 +14856,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U543.out"], - ["d_1_inc.in1","_U543.out"], - ["cmp_time.in1","_U544.out"], + ["d_0_inc.in1","_U66.out"], + ["d_1_inc.in1","_U66.out"], + ["cmp_time.in1","_U67.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -14869,9 +14869,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U545.in0"], - ["d_1_at_max.out","d_0_am__U545.in1"], - ["d_0_next_value.sel","d_0_am__U545.out"], + ["true.out","d_0_am__U68.in0"], + ["d_1_at_max.out","d_0_am__U68.in1"], + ["d_0_next_value.sel","d_0_am__U68.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14899,7 +14899,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U549":{ + "affine_controller__U575":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14907,18 +14907,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U558":{ + "_U584":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U559":{ + "_U585":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U550" + "modref":"global.aff__U576" }, "cmp_time":{ "genref":"coreir.eq", @@ -14928,7 +14928,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U560":{ + "d_0_am__U586":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -15003,9 +15003,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U558.out"], - ["d_1_inc.in1","_U558.out"], - ["cmp_time.in1","_U559.out"], + ["d_0_inc.in1","_U584.out"], + ["d_1_inc.in1","_U584.out"], + ["cmp_time.in1","_U585.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -15016,9 +15016,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U560.in0"], - ["d_1_at_max.out","d_0_am__U560.in1"], - ["d_0_next_value.sel","d_0_am__U560.out"], + ["true.out","d_0_am__U586.in0"], + ["d_1_at_max.out","d_0_am__U586.in1"], + ["d_0_next_value.sel","d_0_am__U586.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15046,7 +15046,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U564":{ + "affine_controller__U589":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -15054,18 +15054,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U573":{ + "_U598":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U574":{ + "_U599":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U565" + "modref":"global.aff__U590" }, "cmp_time":{ "genref":"coreir.eq", @@ -15075,7 +15075,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U575":{ + "d_0_am__U600":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -15150,9 +15150,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U573.out"], - ["d_1_inc.in1","_U573.out"], - ["cmp_time.in1","_U574.out"], + ["d_0_inc.in1","_U598.out"], + ["d_1_inc.in1","_U598.out"], + ["cmp_time.in1","_U599.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -15163,9 +15163,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U575.in0"], - ["d_1_at_max.out","d_0_am__U575.in1"], - ["d_0_next_value.sel","d_0_am__U575.out"], + ["true.out","d_0_am__U600.in0"], + ["d_1_at_max.out","d_0_am__U600.in1"], + ["d_0_next_value.sel","d_0_am__U600.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15193,7 +15193,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U579":{ + "affine_controller__U603":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -15201,18 +15201,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U588":{ + "_U612":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U589":{ + "_U613":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U580" + "modref":"global.aff__U604" }, "cmp_time":{ "genref":"coreir.eq", @@ -15222,7 +15222,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U590":{ + "d_0_am__U614":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -15297,9 +15297,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U588.out"], - ["d_1_inc.in1","_U588.out"], - ["cmp_time.in1","_U589.out"], + ["d_0_inc.in1","_U612.out"], + ["d_1_inc.in1","_U612.out"], + ["cmp_time.in1","_U613.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -15310,9 +15310,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U590.in0"], - ["d_1_at_max.out","d_0_am__U590.in1"], - ["d_0_next_value.sel","d_0_am__U590.out"], + ["true.out","d_0_am__U614.in0"], + ["d_1_at_max.out","d_0_am__U614.in1"], + ["d_0_next_value.sel","d_0_am__U614.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15340,7 +15340,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U594":{ + "affine_controller__U617":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -15348,18 +15348,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U603":{ + "_U626":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U604":{ + "_U627":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U595" + "modref":"global.aff__U618" }, "cmp_time":{ "genref":"coreir.eq", @@ -15369,7 +15369,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U605":{ + "d_0_am__U628":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -15444,9 +15444,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U603.out"], - ["d_1_inc.in1","_U603.out"], - ["cmp_time.in1","_U604.out"], + ["d_0_inc.in1","_U626.out"], + ["d_1_inc.in1","_U626.out"], + ["cmp_time.in1","_U627.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -15457,9 +15457,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U605.in0"], - ["d_1_at_max.out","d_0_am__U605.in1"], - ["d_0_next_value.sel","d_0_am__U605.out"], + ["true.out","d_0_am__U628.in0"], + ["d_1_at_max.out","d_0_am__U628.in1"], + ["d_0_next_value.sel","d_0_am__U628.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15487,7 +15487,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U609":{ + "affine_controller__U631":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -15495,18 +15495,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U618":{ + "_U640":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U619":{ + "_U641":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U610" + "modref":"global.aff__U632" }, "cmp_time":{ "genref":"coreir.eq", @@ -15516,7 +15516,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U620":{ + "d_0_am__U642":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -15591,9 +15591,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U618.out"], - ["d_1_inc.in1","_U618.out"], - ["cmp_time.in1","_U619.out"], + ["d_0_inc.in1","_U640.out"], + ["d_1_inc.in1","_U640.out"], + ["cmp_time.in1","_U641.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -15604,9 +15604,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U620.in0"], - ["d_1_at_max.out","d_0_am__U620.in1"], - ["d_0_next_value.sel","d_0_am__U620.out"], + ["true.out","d_0_am__U642.in0"], + ["d_1_at_max.out","d_0_am__U642.in1"], + ["d_0_next_value.sel","d_0_am__U642.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15634,7 +15634,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U61":{ + "affine_controller__U645":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -15642,18 +15642,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U70":{ + "_U654":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U71":{ + "_U655":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U62" + "modref":"global.aff__U646" }, "cmp_time":{ "genref":"coreir.eq", @@ -15663,7 +15663,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U72":{ + "d_0_am__U656":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -15738,9 +15738,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U70.out"], - ["d_1_inc.in1","_U70.out"], - ["cmp_time.in1","_U71.out"], + ["d_0_inc.in1","_U654.out"], + ["d_1_inc.in1","_U654.out"], + ["cmp_time.in1","_U655.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -15751,9 +15751,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U72.in0"], - ["d_1_at_max.out","d_0_am__U72.in1"], - ["d_0_next_value.sel","d_0_am__U72.out"], + ["true.out","d_0_am__U656.in0"], + ["d_1_at_max.out","d_0_am__U656.in1"], + ["d_0_next_value.sel","d_0_am__U656.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15781,7 +15781,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U624":{ + "affine_controller__U659":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -15789,18 +15789,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U633":{ + "_U668":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U634":{ + "_U669":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U625" + "modref":"global.aff__U660" }, "cmp_time":{ "genref":"coreir.eq", @@ -15810,7 +15810,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U635":{ + "d_0_am__U670":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -15885,9 +15885,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U633.out"], - ["d_1_inc.in1","_U633.out"], - ["cmp_time.in1","_U634.out"], + ["d_0_inc.in1","_U668.out"], + ["d_1_inc.in1","_U668.out"], + ["cmp_time.in1","_U669.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -15898,9 +15898,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U635.in0"], - ["d_1_at_max.out","d_0_am__U635.in1"], - ["d_0_next_value.sel","d_0_am__U635.out"], + ["true.out","d_0_am__U670.in0"], + ["d_1_at_max.out","d_0_am__U670.in1"], + ["d_0_next_value.sel","d_0_am__U670.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15928,7 +15928,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U639":{ + "affine_controller__U673":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -15936,18 +15936,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U648":{ + "_U682":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U649":{ + "_U683":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U640" + "modref":"global.aff__U674" }, "cmp_time":{ "genref":"coreir.eq", @@ -15957,7 +15957,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U650":{ + "d_0_am__U684":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -16032,9 +16032,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U648.out"], - ["d_1_inc.in1","_U648.out"], - ["cmp_time.in1","_U649.out"], + ["d_0_inc.in1","_U682.out"], + ["d_1_inc.in1","_U682.out"], + ["cmp_time.in1","_U683.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -16045,9 +16045,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U650.in0"], - ["d_1_at_max.out","d_0_am__U650.in1"], - ["d_0_next_value.sel","d_0_am__U650.out"], + ["true.out","d_0_am__U684.in0"], + ["d_1_at_max.out","d_0_am__U684.in1"], + ["d_0_next_value.sel","d_0_am__U684.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16075,7 +16075,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U654":{ + "affine_controller__U687":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -16083,18 +16083,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U663":{ + "_U696":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U664":{ + "_U697":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U655" + "modref":"global.aff__U688" }, "cmp_time":{ "genref":"coreir.eq", @@ -16104,7 +16104,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U665":{ + "d_0_am__U698":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -16179,9 +16179,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U663.out"], - ["d_1_inc.in1","_U663.out"], - ["cmp_time.in1","_U664.out"], + ["d_0_inc.in1","_U696.out"], + ["d_1_inc.in1","_U696.out"], + ["cmp_time.in1","_U697.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -16192,9 +16192,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U665.in0"], - ["d_1_at_max.out","d_0_am__U665.in1"], - ["d_0_next_value.sel","d_0_am__U665.out"], + ["true.out","d_0_am__U698.in0"], + ["d_1_at_max.out","d_0_am__U698.in1"], + ["d_0_next_value.sel","d_0_am__U698.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16222,7 +16222,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U669":{ + "affine_controller__U701":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -16230,18 +16230,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U678":{ + "_U710":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U679":{ + "_U711":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U670" + "modref":"global.aff__U702" }, "cmp_time":{ "genref":"coreir.eq", @@ -16251,7 +16251,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U680":{ + "d_0_am__U712":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -16326,9 +16326,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U678.out"], - ["d_1_inc.in1","_U678.out"], - ["cmp_time.in1","_U679.out"], + ["d_0_inc.in1","_U710.out"], + ["d_1_inc.in1","_U710.out"], + ["cmp_time.in1","_U711.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -16339,9 +16339,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U680.in0"], - ["d_1_at_max.out","d_0_am__U680.in1"], - ["d_0_next_value.sel","d_0_am__U680.out"], + ["true.out","d_0_am__U712.in0"], + ["d_1_at_max.out","d_0_am__U712.in1"], + ["d_0_next_value.sel","d_0_am__U712.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16369,7 +16369,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U684":{ + "affine_controller__U71":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -16377,18 +16377,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U693":{ + "_U80":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U694":{ + "_U81":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U685" + "modref":"global.aff__U72" }, "cmp_time":{ "genref":"coreir.eq", @@ -16398,7 +16398,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U695":{ + "d_0_am__U82":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -16473,9 +16473,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U693.out"], - ["d_1_inc.in1","_U693.out"], - ["cmp_time.in1","_U694.out"], + ["d_0_inc.in1","_U80.out"], + ["d_1_inc.in1","_U80.out"], + ["cmp_time.in1","_U81.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -16486,9 +16486,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U695.in0"], - ["d_1_at_max.out","d_0_am__U695.in1"], - ["d_0_next_value.sel","d_0_am__U695.out"], + ["true.out","d_0_am__U82.in0"], + ["d_1_at_max.out","d_0_am__U82.in1"], + ["d_0_next_value.sel","d_0_am__U82.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16516,7 +16516,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U699":{ + "affine_controller__U715":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -16524,18 +16524,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U708":{ + "_U724":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U709":{ + "_U725":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U700" + "modref":"global.aff__U716" }, "cmp_time":{ "genref":"coreir.eq", @@ -16545,7 +16545,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U710":{ + "d_0_am__U726":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -16620,9 +16620,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U708.out"], - ["d_1_inc.in1","_U708.out"], - ["cmp_time.in1","_U709.out"], + ["d_0_inc.in1","_U724.out"], + ["d_1_inc.in1","_U724.out"], + ["cmp_time.in1","_U725.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -16633,9 +16633,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U710.in0"], - ["d_1_at_max.out","d_0_am__U710.in1"], - ["d_0_next_value.sel","d_0_am__U710.out"], + ["true.out","d_0_am__U726.in0"], + ["d_1_at_max.out","d_0_am__U726.in1"], + ["d_0_next_value.sel","d_0_am__U726.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16663,7 +16663,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U714":{ + "affine_controller__U729":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -16671,18 +16671,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U723":{ + "_U738":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U724":{ + "_U739":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U715" + "modref":"global.aff__U730" }, "cmp_time":{ "genref":"coreir.eq", @@ -16692,7 +16692,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U725":{ + "d_0_am__U740":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -16767,9 +16767,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U723.out"], - ["d_1_inc.in1","_U723.out"], - ["cmp_time.in1","_U724.out"], + ["d_0_inc.in1","_U738.out"], + ["d_1_inc.in1","_U738.out"], + ["cmp_time.in1","_U739.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -16780,9 +16780,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U725.in0"], - ["d_1_at_max.out","d_0_am__U725.in1"], - ["d_0_next_value.sel","d_0_am__U725.out"], + ["true.out","d_0_am__U740.in0"], + ["d_1_at_max.out","d_0_am__U740.in1"], + ["d_0_next_value.sel","d_0_am__U740.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16810,7 +16810,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U729":{ + "affine_controller__U743":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -16818,18 +16818,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U738":{ + "_U752":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U739":{ + "_U753":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U730" + "modref":"global.aff__U744" }, "cmp_time":{ "genref":"coreir.eq", @@ -16839,7 +16839,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U740":{ + "d_0_am__U754":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -16914,9 +16914,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U738.out"], - ["d_1_inc.in1","_U738.out"], - ["cmp_time.in1","_U739.out"], + ["d_0_inc.in1","_U752.out"], + ["d_1_inc.in1","_U752.out"], + ["cmp_time.in1","_U753.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -16927,9 +16927,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U740.in0"], - ["d_1_at_max.out","d_0_am__U740.in1"], - ["d_0_next_value.sel","d_0_am__U740.out"], + ["true.out","d_0_am__U754.in0"], + ["d_1_at_max.out","d_0_am__U754.in1"], + ["d_0_next_value.sel","d_0_am__U754.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16957,7 +16957,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U744":{ + "affine_controller__U757":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -16965,18 +16965,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U753":{ + "_U766":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U754":{ + "_U767":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U745" + "modref":"global.aff__U758" }, "cmp_time":{ "genref":"coreir.eq", @@ -16986,7 +16986,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U755":{ + "d_0_am__U768":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -17061,9 +17061,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U753.out"], - ["d_1_inc.in1","_U753.out"], - ["cmp_time.in1","_U754.out"], + ["d_0_inc.in1","_U766.out"], + ["d_1_inc.in1","_U766.out"], + ["cmp_time.in1","_U767.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -17074,9 +17074,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U755.in0"], - ["d_1_at_max.out","d_0_am__U755.in1"], - ["d_0_next_value.sel","d_0_am__U755.out"], + ["true.out","d_0_am__U768.in0"], + ["d_1_at_max.out","d_0_am__U768.in1"], + ["d_0_next_value.sel","d_0_am__U768.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17104,7 +17104,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U759":{ + "affine_controller__U771":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17112,18 +17112,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U768":{ + "_U780":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U769":{ + "_U781":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U760" + "modref":"global.aff__U772" }, "cmp_time":{ "genref":"coreir.eq", @@ -17133,7 +17133,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U770":{ + "d_0_am__U782":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -17208,9 +17208,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U768.out"], - ["d_1_inc.in1","_U768.out"], - ["cmp_time.in1","_U769.out"], + ["d_0_inc.in1","_U780.out"], + ["d_1_inc.in1","_U780.out"], + ["cmp_time.in1","_U781.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -17221,9 +17221,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U770.in0"], - ["d_1_at_max.out","d_0_am__U770.in1"], - ["d_0_next_value.sel","d_0_am__U770.out"], + ["true.out","d_0_am__U782.in0"], + ["d_1_at_max.out","d_0_am__U782.in1"], + ["d_0_next_value.sel","d_0_am__U782.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17251,7 +17251,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U76":{ + "affine_controller__U785":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17259,18 +17259,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U85":{ + "_U794":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U86":{ + "_U795":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U77" + "modref":"global.aff__U786" }, "cmp_time":{ "genref":"coreir.eq", @@ -17280,7 +17280,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U87":{ + "d_0_am__U796":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -17355,9 +17355,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U85.out"], - ["d_1_inc.in1","_U85.out"], - ["cmp_time.in1","_U86.out"], + ["d_0_inc.in1","_U794.out"], + ["d_1_inc.in1","_U794.out"], + ["cmp_time.in1","_U795.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -17368,9 +17368,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U87.in0"], - ["d_1_at_max.out","d_0_am__U87.in1"], - ["d_0_next_value.sel","d_0_am__U87.out"], + ["true.out","d_0_am__U796.in0"], + ["d_1_at_max.out","d_0_am__U796.in1"], + ["d_0_next_value.sel","d_0_am__U796.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17398,7 +17398,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U774":{ + "affine_controller__U799":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17406,18 +17406,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U783":{ + "_U808":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U784":{ + "_U809":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U775" + "modref":"global.aff__U800" }, "cmp_time":{ "genref":"coreir.eq", @@ -17427,7 +17427,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U785":{ + "d_0_am__U810":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -17502,9 +17502,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U783.out"], - ["d_1_inc.in1","_U783.out"], - ["cmp_time.in1","_U784.out"], + ["d_0_inc.in1","_U808.out"], + ["d_1_inc.in1","_U808.out"], + ["cmp_time.in1","_U809.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -17515,9 +17515,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U785.in0"], - ["d_1_at_max.out","d_0_am__U785.in1"], - ["d_0_next_value.sel","d_0_am__U785.out"], + ["true.out","d_0_am__U810.in0"], + ["d_1_at_max.out","d_0_am__U810.in1"], + ["d_0_next_value.sel","d_0_am__U810.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17545,7 +17545,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U789":{ + "affine_controller__U813":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17553,18 +17553,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U798":{ + "_U822":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U799":{ + "_U823":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U790" + "modref":"global.aff__U814" }, "cmp_time":{ "genref":"coreir.eq", @@ -17574,7 +17574,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U800":{ + "d_0_am__U824":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -17649,9 +17649,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U798.out"], - ["d_1_inc.in1","_U798.out"], - ["cmp_time.in1","_U799.out"], + ["d_0_inc.in1","_U822.out"], + ["d_1_inc.in1","_U822.out"], + ["cmp_time.in1","_U823.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -17662,9 +17662,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U800.in0"], - ["d_1_at_max.out","d_0_am__U800.in1"], - ["d_0_next_value.sel","d_0_am__U800.out"], + ["true.out","d_0_am__U824.in0"], + ["d_1_at_max.out","d_0_am__U824.in1"], + ["d_0_next_value.sel","d_0_am__U824.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17692,7 +17692,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U804":{ + "affine_controller__U827":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17700,18 +17700,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U813":{ + "_U836":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U814":{ + "_U837":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U805" + "modref":"global.aff__U828" }, "cmp_time":{ "genref":"coreir.eq", @@ -17721,7 +17721,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U815":{ + "d_0_am__U838":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -17796,9 +17796,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U813.out"], - ["d_1_inc.in1","_U813.out"], - ["cmp_time.in1","_U814.out"], + ["d_0_inc.in1","_U836.out"], + ["d_1_inc.in1","_U836.out"], + ["cmp_time.in1","_U837.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -17809,9 +17809,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U815.in0"], - ["d_1_at_max.out","d_0_am__U815.in1"], - ["d_0_next_value.sel","d_0_am__U815.out"], + ["true.out","d_0_am__U838.in0"], + ["d_1_at_max.out","d_0_am__U838.in1"], + ["d_0_next_value.sel","d_0_am__U838.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17839,7 +17839,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U819":{ + "affine_controller__U841":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17847,18 +17847,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U828":{ + "_U850":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U829":{ + "_U851":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U820" + "modref":"global.aff__U842" }, "cmp_time":{ "genref":"coreir.eq", @@ -17868,7 +17868,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U830":{ + "d_0_am__U852":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -17943,9 +17943,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U828.out"], - ["d_1_inc.in1","_U828.out"], - ["cmp_time.in1","_U829.out"], + ["d_0_inc.in1","_U850.out"], + ["d_1_inc.in1","_U850.out"], + ["cmp_time.in1","_U851.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -17956,9 +17956,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U830.in0"], - ["d_1_at_max.out","d_0_am__U830.in1"], - ["d_0_next_value.sel","d_0_am__U830.out"], + ["true.out","d_0_am__U852.in0"], + ["d_1_at_max.out","d_0_am__U852.in1"], + ["d_0_next_value.sel","d_0_am__U852.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17986,7 +17986,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U834":{ + "affine_controller__U85":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17994,18 +17994,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U843":{ + "_U94":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U844":{ + "_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U835" + "modref":"global.aff__U86" }, "cmp_time":{ "genref":"coreir.eq", @@ -18015,7 +18015,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U845":{ + "d_0_am__U96":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -18090,9 +18090,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U843.out"], - ["d_1_inc.in1","_U843.out"], - ["cmp_time.in1","_U844.out"], + ["d_0_inc.in1","_U94.out"], + ["d_1_inc.in1","_U94.out"], + ["cmp_time.in1","_U95.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -18103,9 +18103,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U845.in0"], - ["d_1_at_max.out","d_0_am__U845.in1"], - ["d_0_next_value.sel","d_0_am__U845.out"], + ["true.out","d_0_am__U96.in0"], + ["d_1_at_max.out","d_0_am__U96.in1"], + ["d_0_next_value.sel","d_0_am__U96.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18133,7 +18133,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U849":{ + "affine_controller__U855":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18141,18 +18141,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U858":{ + "_U864":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U859":{ + "_U865":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U850" + "modref":"global.aff__U856" }, "cmp_time":{ "genref":"coreir.eq", @@ -18162,7 +18162,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U860":{ + "d_0_am__U866":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -18237,9 +18237,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U858.out"], - ["d_1_inc.in1","_U858.out"], - ["cmp_time.in1","_U859.out"], + ["d_0_inc.in1","_U864.out"], + ["d_1_inc.in1","_U864.out"], + ["cmp_time.in1","_U865.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -18250,9 +18250,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U860.in0"], - ["d_1_at_max.out","d_0_am__U860.in1"], - ["d_0_next_value.sel","d_0_am__U860.out"], + ["true.out","d_0_am__U866.in0"], + ["d_1_at_max.out","d_0_am__U866.in1"], + ["d_0_next_value.sel","d_0_am__U866.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18280,7 +18280,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U864":{ + "affine_controller__U869":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18288,18 +18288,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U873":{ + "_U878":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U874":{ + "_U879":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U865" + "modref":"global.aff__U870" }, "cmp_time":{ "genref":"coreir.eq", @@ -18309,7 +18309,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U875":{ + "d_0_am__U880":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -18384,9 +18384,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U873.out"], - ["d_1_inc.in1","_U873.out"], - ["cmp_time.in1","_U874.out"], + ["d_0_inc.in1","_U878.out"], + ["d_1_inc.in1","_U878.out"], + ["cmp_time.in1","_U879.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -18397,9 +18397,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U875.in0"], - ["d_1_at_max.out","d_0_am__U875.in1"], - ["d_0_next_value.sel","d_0_am__U875.out"], + ["true.out","d_0_am__U880.in0"], + ["d_1_at_max.out","d_0_am__U880.in1"], + ["d_0_next_value.sel","d_0_am__U880.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18427,7 +18427,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U879":{ + "affine_controller__U883":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18435,18 +18435,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U888":{ + "_U892":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U889":{ + "_U893":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U880" + "modref":"global.aff__U884" }, "cmp_time":{ "genref":"coreir.eq", @@ -18456,7 +18456,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U890":{ + "d_0_am__U894":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -18531,9 +18531,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U888.out"], - ["d_1_inc.in1","_U888.out"], - ["cmp_time.in1","_U889.out"], + ["d_0_inc.in1","_U892.out"], + ["d_1_inc.in1","_U892.out"], + ["cmp_time.in1","_U893.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -18544,9 +18544,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U890.in0"], - ["d_1_at_max.out","d_0_am__U890.in1"], - ["d_0_next_value.sel","d_0_am__U890.out"], + ["true.out","d_0_am__U894.in0"], + ["d_1_at_max.out","d_0_am__U894.in1"], + ["d_0_next_value.sel","d_0_am__U894.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18574,7 +18574,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U894":{ + "affine_controller__U897":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18582,18 +18582,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U903":{ + "_U906":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U904":{ + "_U907":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U895" + "modref":"global.aff__U898" }, "cmp_time":{ "genref":"coreir.eq", @@ -18603,7 +18603,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U905":{ + "d_0_am__U908":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -18678,9 +18678,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U903.out"], - ["d_1_inc.in1","_U903.out"], - ["cmp_time.in1","_U904.out"], + ["d_0_inc.in1","_U906.out"], + ["d_1_inc.in1","_U906.out"], + ["cmp_time.in1","_U907.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -18691,9 +18691,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U905.in0"], - ["d_1_at_max.out","d_0_am__U905.in1"], - ["d_0_next_value.sel","d_0_am__U905.out"], + ["true.out","d_0_am__U908.in0"], + ["d_1_at_max.out","d_0_am__U908.in1"], + ["d_0_next_value.sel","d_0_am__U908.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18721,7 +18721,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U909":{ + "affine_controller__U911":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18729,18 +18729,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U918":{ + "_U920":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U919":{ + "_U921":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U910" + "modref":"global.aff__U912" }, "cmp_time":{ "genref":"coreir.eq", @@ -18750,7 +18750,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U920":{ + "d_0_am__U922":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -18825,9 +18825,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U918.out"], - ["d_1_inc.in1","_U918.out"], - ["cmp_time.in1","_U919.out"], + ["d_0_inc.in1","_U920.out"], + ["d_1_inc.in1","_U920.out"], + ["cmp_time.in1","_U921.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -18838,9 +18838,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U920.in0"], - ["d_1_at_max.out","d_0_am__U920.in1"], - ["d_0_next_value.sel","d_0_am__U920.out"], + ["true.out","d_0_am__U922.in0"], + ["d_1_at_max.out","d_0_am__U922.in1"], + ["d_0_next_value.sel","d_0_am__U922.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18868,7 +18868,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U91":{ + "affine_controller__U925":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18876,18 +18876,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U100":{ + "_U934":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U101":{ + "_U935":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U92" + "modref":"global.aff__U926" }, "cmp_time":{ "genref":"coreir.eq", @@ -18897,7 +18897,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U102":{ + "d_0_am__U936":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -18972,9 +18972,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U100.out"], - ["d_1_inc.in1","_U100.out"], - ["cmp_time.in1","_U101.out"], + ["d_0_inc.in1","_U934.out"], + ["d_1_inc.in1","_U934.out"], + ["cmp_time.in1","_U935.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -18985,9 +18985,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U102.in0"], - ["d_1_at_max.out","d_0_am__U102.in1"], - ["d_0_next_value.sel","d_0_am__U102.out"], + ["true.out","d_0_am__U936.in0"], + ["d_1_at_max.out","d_0_am__U936.in1"], + ["d_0_next_value.sel","d_0_am__U936.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19015,7 +19015,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U924":{ + "affine_controller__U939":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19023,18 +19023,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U933":{ + "_U948":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U934":{ + "_U949":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U925" + "modref":"global.aff__U940" }, "cmp_time":{ "genref":"coreir.eq", @@ -19044,7 +19044,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U935":{ + "d_0_am__U950":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -19119,9 +19119,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U933.out"], - ["d_1_inc.in1","_U933.out"], - ["cmp_time.in1","_U934.out"], + ["d_0_inc.in1","_U948.out"], + ["d_1_inc.in1","_U948.out"], + ["cmp_time.in1","_U949.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -19132,9 +19132,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U935.in0"], - ["d_1_at_max.out","d_0_am__U935.in1"], - ["d_0_next_value.sel","d_0_am__U935.out"], + ["true.out","d_0_am__U950.in0"], + ["d_1_at_max.out","d_0_am__U950.in1"], + ["d_0_next_value.sel","d_0_am__U950.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19162,7 +19162,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U939":{ + "affine_controller__U953":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19170,18 +19170,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U948":{ + "_U962":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U949":{ + "_U963":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U940" + "modref":"global.aff__U954" }, "cmp_time":{ "genref":"coreir.eq", @@ -19191,7 +19191,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U950":{ + "d_0_am__U964":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -19266,9 +19266,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U948.out"], - ["d_1_inc.in1","_U948.out"], - ["cmp_time.in1","_U949.out"], + ["d_0_inc.in1","_U962.out"], + ["d_1_inc.in1","_U962.out"], + ["cmp_time.in1","_U963.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -19279,9 +19279,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U950.in0"], - ["d_1_at_max.out","d_0_am__U950.in1"], - ["d_0_next_value.sel","d_0_am__U950.out"], + ["true.out","d_0_am__U964.in0"], + ["d_1_at_max.out","d_0_am__U964.in1"], + ["d_0_next_value.sel","d_0_am__U964.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19309,7 +19309,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U954":{ + "affine_controller__U967":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19317,18 +19317,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U963":{ + "_U976":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U964":{ + "_U977":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U955" + "modref":"global.aff__U968" }, "cmp_time":{ "genref":"coreir.eq", @@ -19338,7 +19338,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U965":{ + "d_0_am__U978":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -19413,9 +19413,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U963.out"], - ["d_1_inc.in1","_U963.out"], - ["cmp_time.in1","_U964.out"], + ["d_0_inc.in1","_U976.out"], + ["d_1_inc.in1","_U976.out"], + ["cmp_time.in1","_U977.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -19426,9 +19426,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U965.in0"], - ["d_1_at_max.out","d_0_am__U965.in1"], - ["d_0_next_value.sel","d_0_am__U965.out"], + ["true.out","d_0_am__U978.in0"], + ["d_1_at_max.out","d_0_am__U978.in1"], + ["d_0_next_value.sel","d_0_am__U978.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19456,7 +19456,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U969":{ + "affine_controller__U981":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19464,18 +19464,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U978":{ + "_U990":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U979":{ + "_U991":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U970" + "modref":"global.aff__U982" }, "cmp_time":{ "genref":"coreir.eq", @@ -19485,7 +19485,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U980":{ + "d_0_am__U992":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -19560,9 +19560,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U978.out"], - ["d_1_inc.in1","_U978.out"], - ["cmp_time.in1","_U979.out"], + ["d_0_inc.in1","_U990.out"], + ["d_1_inc.in1","_U990.out"], + ["cmp_time.in1","_U991.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -19573,9 +19573,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U980.in0"], - ["d_1_at_max.out","d_0_am__U980.in1"], - ["d_0_next_value.sel","d_0_am__U980.out"], + ["true.out","d_0_am__U992.in0"], + ["d_1_at_max.out","d_0_am__U992.in1"], + ["d_0_next_value.sel","d_0_am__U992.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19603,7 +19603,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U984":{ + "affine_controller__U99":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19611,18 +19611,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U993":{ + "_U108":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U994":{ + "_U109":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U985" + "modref":"global.aff__U100" }, "cmp_time":{ "genref":"coreir.eq", @@ -19632,7 +19632,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U995":{ + "d_0_am__U110":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -19707,9 +19707,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U993.out"], - ["d_1_inc.in1","_U993.out"], - ["cmp_time.in1","_U994.out"], + ["d_0_inc.in1","_U108.out"], + ["d_1_inc.in1","_U108.out"], + ["cmp_time.in1","_U109.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -19720,9 +19720,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U995.in0"], - ["d_1_at_max.out","d_0_am__U995.in1"], - ["d_0_next_value.sel","d_0_am__U995.out"], + ["true.out","d_0_am__U110.in0"], + ["d_1_at_max.out","d_0_am__U110.in1"], + ["d_0_next_value.sel","d_0_am__U110.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19750,7 +19750,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U999":{ + "affine_controller__U995":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19758,18 +19758,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1008":{ + "_U1004":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1009":{ + "_U1005":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U1000" + "modref":"global.aff__U996" }, "cmp_time":{ "genref":"coreir.eq", @@ -19779,7 +19779,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U1010":{ + "d_0_am__U1006":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -19854,9 +19854,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U1008.out"], - ["d_1_inc.in1","_U1008.out"], - ["cmp_time.in1","_U1009.out"], + ["d_0_inc.in1","_U1004.out"], + ["d_1_inc.in1","_U1004.out"], + ["cmp_time.in1","_U1005.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -19867,9 +19867,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U1010.in0"], - ["d_1_at_max.out","d_0_am__U1010.in1"], - ["d_0_next_value.sel","d_0_am__U1010.out"], + ["true.out","d_0_am__U1006.in0"], + ["d_1_at_max.out","d_0_am__U1006.in1"], + ["d_0_next_value.sel","d_0_am__U1006.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -21490,98 +21490,66 @@ ] }, "input_cgra_stencil_ub":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["flush","BitIn"], - ["reset","BitIn"], - ["op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], - ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"], - ["op_hcompute_output_cgra_stencil_10_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_10_read_extra_ctrl","Bit"], - ["op_hcompute_output_cgra_stencil_11_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_11_read_extra_ctrl","Bit"], - ["op_hcompute_output_cgra_stencil_12_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_12_read_extra_ctrl","Bit"], - ["op_hcompute_output_cgra_stencil_13_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_13_read_extra_ctrl","Bit"], - ["op_hcompute_output_cgra_stencil_14_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_14_read_extra_ctrl","Bit"], - ["op_hcompute_output_cgra_stencil_15_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_15_read_extra_ctrl","Bit"], - ["op_hcompute_output_cgra_stencil_8_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_8_read_extra_ctrl","Bit"], - ["op_hcompute_output_cgra_stencil_9_read",["Array",8,["Array",16,"Bit"]]], - ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] - ]], - "instances":{ - "chain_en_const_U104":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U14":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U44":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U74":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "ctrl__U103":{ - "modref":"global.affine_controller__U91", - "metadata":{"garnet_rewire_flush":true} - }, - "ctrl__U118":{ - "modref":"global.affine_controller__U106", + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_cgra_stencil_10_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_10_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_11_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_11_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_12_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_12_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_13_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_13_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_14_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_14_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_15_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_15_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_8_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_8_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_9_read",["Array",8,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ctrl__U111":{ + "modref":"global.affine_controller__U99", "metadata":{"garnet_rewire_flush":true} }, "ctrl__U13":{ "modref":"global.affine_controller__U1", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U28":{ - "modref":"global.affine_controller__U16", + "ctrl__U27":{ + "modref":"global.affine_controller__U15", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U43":{ - "modref":"global.affine_controller__U31", + "ctrl__U41":{ + "modref":"global.affine_controller__U29", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U58":{ - "modref":"global.affine_controller__U46", + "ctrl__U55":{ + "modref":"global.affine_controller__U43", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U73":{ - "modref":"global.affine_controller__U61", + "ctrl__U69":{ + "modref":"global.affine_controller__U57", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U88":{ - "modref":"global.affine_controller__U76", + "ctrl__U83":{ + "modref":"global.affine_controller__U71", + "metadata":{"garnet_rewire_flush":true} + }, + "ctrl__U97":{ + "modref":"global.affine_controller__U85", "metadata":{"garnet_rewire_flush":true} }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -21589,8 +21557,8 @@ }, "ub_input_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U15"} + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -21598,8 +21566,8 @@ }, "ub_input_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U30"} + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -21607,8 +21575,8 @@ }, "ub_input_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U45"} + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -21616,8 +21584,8 @@ }, "ub_input_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U60"} + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -21625,8 +21593,8 @@ }, "ub_input_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U75"} + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -21634,8 +21602,8 @@ }, "ub_input_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U90"} + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -21643,8 +21611,8 @@ }, "ub_input_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U105"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U105"} + "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_input_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -21652,30 +21620,22 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U104.out"], - ["ub_input_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U119.out"], - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U14.out"], - ["ub_input_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U29.out"], - ["ub_input_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U44.out"], - ["ub_input_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U59.out"], - ["ub_input_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U74.out"], - ["ub_input_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U89.out"], - ["self.clk","ctrl__U103.clk"], - ["ub_input_cgra_stencil_BANK_6.flush","ctrl__U103.valid"], - ["self.clk","ctrl__U118.clk"], - ["ub_input_cgra_stencil_BANK_7.flush","ctrl__U118.valid"], + ["self.clk","ctrl__U111.clk"], + ["ub_input_cgra_stencil_BANK_7.flush","ctrl__U111.valid"], ["self.clk","ctrl__U13.clk"], ["ub_input_cgra_stencil_BANK_0.flush","ctrl__U13.valid"], - ["self.clk","ctrl__U28.clk"], - ["ub_input_cgra_stencil_BANK_1.flush","ctrl__U28.valid"], - ["self.clk","ctrl__U43.clk"], - ["ub_input_cgra_stencil_BANK_2.flush","ctrl__U43.valid"], - ["self.clk","ctrl__U58.clk"], - ["ub_input_cgra_stencil_BANK_3.flush","ctrl__U58.valid"], - ["self.clk","ctrl__U73.clk"], - ["ub_input_cgra_stencil_BANK_4.flush","ctrl__U73.valid"], - ["self.clk","ctrl__U88.clk"], - ["ub_input_cgra_stencil_BANK_5.flush","ctrl__U88.valid"], + ["self.clk","ctrl__U27.clk"], + ["ub_input_cgra_stencil_BANK_1.flush","ctrl__U27.valid"], + ["self.clk","ctrl__U41.clk"], + ["ub_input_cgra_stencil_BANK_2.flush","ctrl__U41.valid"], + ["self.clk","ctrl__U55.clk"], + ["ub_input_cgra_stencil_BANK_3.flush","ctrl__U55.valid"], + ["self.clk","ctrl__U69.clk"], + ["ub_input_cgra_stencil_BANK_4.flush","ctrl__U69.valid"], + ["self.clk","ctrl__U83.clk"], + ["ub_input_cgra_stencil_BANK_5.flush","ctrl__U83.valid"], + ["self.clk","ctrl__U97.clk"], + ["ub_input_cgra_stencil_BANK_6.flush","ctrl__U97.valid"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_1.clk","self.clk"], ["ub_input_cgra_stencil_BANK_2.clk","self.clk"], @@ -21785,42 +21745,42 @@ ["op_hcompute_input_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U231":{ - "modref":"global.aff__U208" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U222":{ + "modref":"global.aff__U199" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U159":{ - "modref":"global.aff__U145" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U150":{ + "modref":"global.aff__U136" }, - "chain_en_const_U232":{ + "chain_en_const_U223":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U144":{ - "modref":"global.affine_controller__U121", + "ctrl__U135":{ + "modref":"global.affine_controller__U112", "metadata":{"garnet_remove":true} }, - "ctrl__U207":{ - "modref":"global.affine_controller__U160", + "ctrl__U198":{ + "modref":"global.affine_controller__U151", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[73728],"cycle_stride":[1,32,18432,36864],"dimensionality":4,"extent":[32,81,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,64,32,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[5184],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U120"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[73728],"cycle_stride":[1,32,18432,36864],"dimensionality":4,"extent":[32,81,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,64,32,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[5184],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U207.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U231.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U231.out"], - ["ctrl__U144.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U159.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U159.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U232.out"], - ["self.clk","ctrl__U144.clk"], - ["self.reset","ctrl__U144.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U144.valid"], - ["self.clk","ctrl__U207.clk"], - ["self.reset","ctrl__U207.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U207.valid"], + ["ctrl__U198.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U222.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U222.out"], + ["ctrl__U135.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U150.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U150.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U223.out"], + ["self.clk","ctrl__U135.clk"], + ["self.reset","ctrl__U135.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U135.valid"], + ["self.clk","ctrl__U198.clk"], + ["self.reset","ctrl__U198.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U198.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_glb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_input_cgra_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -21852,522 +21812,266 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1012":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1027":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1042":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1057":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1072":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1087":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1102":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1117":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U262":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U277":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U292":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U307":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U322":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U337":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U352":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U367":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U397":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U412":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U427":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U442":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U457":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U472":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U487":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U502":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U517":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U532":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U547":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U562":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U577":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U592":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U607":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U622":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U637":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U652":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U667":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U682":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U697":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U712":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U727":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U742":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U757":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U772":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U787":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U802":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U817":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U832":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U847":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U862":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U877":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U892":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U907":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U922":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U937":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U952":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U967":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U982":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U997":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "ctrl__U1011":{ - "modref":"global.affine_controller__U999", - "metadata":{"garnet_rewire_flush":true} - }, - "ctrl__U1026":{ - "modref":"global.affine_controller__U1014", - "metadata":{"garnet_rewire_flush":true} - }, - "ctrl__U1041":{ - "modref":"global.affine_controller__U1029", - "metadata":{"garnet_rewire_flush":true} - }, - "ctrl__U1056":{ - "modref":"global.affine_controller__U1044", + "ctrl__U1007":{ + "modref":"global.affine_controller__U995", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1071":{ - "modref":"global.affine_controller__U1059", + "ctrl__U1021":{ + "modref":"global.affine_controller__U1009", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1086":{ - "modref":"global.affine_controller__U1074", + "ctrl__U1035":{ + "modref":"global.affine_controller__U1023", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1101":{ - "modref":"global.affine_controller__U1089", + "ctrl__U1049":{ + "modref":"global.affine_controller__U1037", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1116":{ - "modref":"global.affine_controller__U1104", + "ctrl__U1063":{ + "modref":"global.affine_controller__U1051", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1131":{ - "modref":"global.affine_controller__U1119", + "ctrl__U1077":{ + "modref":"global.affine_controller__U1065", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1146":{ - "modref":"global.affine_controller__U1134", + "ctrl__U1091":{ + "modref":"global.affine_controller__U1079", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1161":{ - "modref":"global.affine_controller__U1149", + "ctrl__U1105":{ + "modref":"global.affine_controller__U1093", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1176":{ - "modref":"global.affine_controller__U1164", + "ctrl__U1119":{ + "modref":"global.affine_controller__U1107", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1191":{ - "modref":"global.affine_controller__U1179", + "ctrl__U237":{ + "modref":"global.affine_controller__U225", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U246":{ - "modref":"global.affine_controller__U234", + "ctrl__U251":{ + "modref":"global.affine_controller__U239", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U261":{ - "modref":"global.affine_controller__U249", + "ctrl__U265":{ + "modref":"global.affine_controller__U253", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U276":{ - "modref":"global.affine_controller__U264", + "ctrl__U279":{ + "modref":"global.affine_controller__U267", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U291":{ - "modref":"global.affine_controller__U279", + "ctrl__U293":{ + "modref":"global.affine_controller__U281", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U306":{ - "modref":"global.affine_controller__U294", + "ctrl__U307":{ + "modref":"global.affine_controller__U295", "metadata":{"garnet_rewire_flush":true} }, "ctrl__U321":{ "modref":"global.affine_controller__U309", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U336":{ - "modref":"global.affine_controller__U324", + "ctrl__U335":{ + "modref":"global.affine_controller__U323", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U351":{ - "modref":"global.affine_controller__U339", + "ctrl__U349":{ + "modref":"global.affine_controller__U337", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U366":{ - "modref":"global.affine_controller__U354", + "ctrl__U363":{ + "modref":"global.affine_controller__U351", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U381":{ - "modref":"global.affine_controller__U369", + "ctrl__U377":{ + "modref":"global.affine_controller__U365", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U396":{ - "modref":"global.affine_controller__U384", + "ctrl__U391":{ + "modref":"global.affine_controller__U379", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U411":{ - "modref":"global.affine_controller__U399", + "ctrl__U405":{ + "modref":"global.affine_controller__U393", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U426":{ - "modref":"global.affine_controller__U414", + "ctrl__U419":{ + "modref":"global.affine_controller__U407", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U441":{ - "modref":"global.affine_controller__U429", + "ctrl__U433":{ + "modref":"global.affine_controller__U421", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U456":{ - "modref":"global.affine_controller__U444", + "ctrl__U447":{ + "modref":"global.affine_controller__U435", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U471":{ - "modref":"global.affine_controller__U459", + "ctrl__U461":{ + "modref":"global.affine_controller__U449", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U486":{ - "modref":"global.affine_controller__U474", + "ctrl__U475":{ + "modref":"global.affine_controller__U463", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U501":{ - "modref":"global.affine_controller__U489", + "ctrl__U489":{ + "modref":"global.affine_controller__U477", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U516":{ - "modref":"global.affine_controller__U504", + "ctrl__U503":{ + "modref":"global.affine_controller__U491", + "metadata":{"garnet_rewire_flush":true} + }, + "ctrl__U517":{ + "modref":"global.affine_controller__U505", "metadata":{"garnet_rewire_flush":true} }, "ctrl__U531":{ "modref":"global.affine_controller__U519", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U546":{ - "modref":"global.affine_controller__U534", + "ctrl__U545":{ + "modref":"global.affine_controller__U533", + "metadata":{"garnet_rewire_flush":true} + }, + "ctrl__U559":{ + "modref":"global.affine_controller__U547", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U561":{ - "modref":"global.affine_controller__U549", + "ctrl__U573":{ + "modref":"global.affine_controller__U561", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U576":{ - "modref":"global.affine_controller__U564", + "ctrl__U587":{ + "modref":"global.affine_controller__U575", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U591":{ - "modref":"global.affine_controller__U579", + "ctrl__U601":{ + "modref":"global.affine_controller__U589", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U606":{ - "modref":"global.affine_controller__U594", + "ctrl__U615":{ + "modref":"global.affine_controller__U603", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U621":{ - "modref":"global.affine_controller__U609", + "ctrl__U629":{ + "modref":"global.affine_controller__U617", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U636":{ - "modref":"global.affine_controller__U624", + "ctrl__U643":{ + "modref":"global.affine_controller__U631", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U651":{ - "modref":"global.affine_controller__U639", + "ctrl__U657":{ + "modref":"global.affine_controller__U645", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U666":{ - "modref":"global.affine_controller__U654", + "ctrl__U671":{ + "modref":"global.affine_controller__U659", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U681":{ - "modref":"global.affine_controller__U669", + "ctrl__U685":{ + "modref":"global.affine_controller__U673", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U696":{ - "modref":"global.affine_controller__U684", + "ctrl__U699":{ + "modref":"global.affine_controller__U687", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U711":{ - "modref":"global.affine_controller__U699", + "ctrl__U713":{ + "modref":"global.affine_controller__U701", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U726":{ - "modref":"global.affine_controller__U714", + "ctrl__U727":{ + "modref":"global.affine_controller__U715", "metadata":{"garnet_rewire_flush":true} }, "ctrl__U741":{ "modref":"global.affine_controller__U729", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U756":{ - "modref":"global.affine_controller__U744", + "ctrl__U755":{ + "modref":"global.affine_controller__U743", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U771":{ - "modref":"global.affine_controller__U759", + "ctrl__U769":{ + "modref":"global.affine_controller__U757", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U786":{ - "modref":"global.affine_controller__U774", + "ctrl__U783":{ + "modref":"global.affine_controller__U771", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U801":{ - "modref":"global.affine_controller__U789", + "ctrl__U797":{ + "modref":"global.affine_controller__U785", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U816":{ - "modref":"global.affine_controller__U804", + "ctrl__U811":{ + "modref":"global.affine_controller__U799", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U831":{ - "modref":"global.affine_controller__U819", + "ctrl__U825":{ + "modref":"global.affine_controller__U813", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U846":{ - "modref":"global.affine_controller__U834", + "ctrl__U839":{ + "modref":"global.affine_controller__U827", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U861":{ - "modref":"global.affine_controller__U849", + "ctrl__U853":{ + "modref":"global.affine_controller__U841", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U876":{ - "modref":"global.affine_controller__U864", + "ctrl__U867":{ + "modref":"global.affine_controller__U855", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U891":{ - "modref":"global.affine_controller__U879", + "ctrl__U881":{ + "modref":"global.affine_controller__U869", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U906":{ - "modref":"global.affine_controller__U894", + "ctrl__U895":{ + "modref":"global.affine_controller__U883", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U921":{ - "modref":"global.affine_controller__U909", + "ctrl__U909":{ + "modref":"global.affine_controller__U897", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U936":{ - "modref":"global.affine_controller__U924", + "ctrl__U923":{ + "modref":"global.affine_controller__U911", + "metadata":{"garnet_rewire_flush":true} + }, + "ctrl__U937":{ + "modref":"global.affine_controller__U925", "metadata":{"garnet_rewire_flush":true} }, "ctrl__U951":{ "modref":"global.affine_controller__U939", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U966":{ - "modref":"global.affine_controller__U954", + "ctrl__U965":{ + "modref":"global.affine_controller__U953", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U981":{ - "modref":"global.affine_controller__U969", + "ctrl__U979":{ + "modref":"global.affine_controller__U967", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U996":{ - "modref":"global.affine_controller__U984", + "ctrl__U993":{ + "modref":"global.affine_controller__U981", "metadata":{"garnet_rewire_flush":true} }, "ub_kernel_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U233"} + "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -22375,13 +22079,13 @@ }, "ub_kernel_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[64],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U248"} + "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[64],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[154],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[129],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U383"} + "genargs":{"ID":["String","_U364"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[154],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[129],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -22389,8 +22093,8 @@ }, "ub_kernel_cgra_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U398"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[193],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U398"} + "genargs":{"ID":["String","_U378"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[193],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -22398,8 +22102,8 @@ }, "ub_kernel_cgra_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U413"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[282],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[257],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U413"} + "genargs":{"ID":["String","_U392"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[282],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[257],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -22407,8 +22111,8 @@ }, "ub_kernel_cgra_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U428"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[346],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[321],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U428"} + "genargs":{"ID":["String","_U406"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[346],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[321],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -22416,8 +22120,8 @@ }, "ub_kernel_cgra_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U443"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[410],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[385],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U443"} + "genargs":{"ID":["String","_U420"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[410],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[385],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -22425,8 +22129,8 @@ }, "ub_kernel_cgra_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U458"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[474],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[449],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U458"} + "genargs":{"ID":["String","_U434"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[474],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[449],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -22434,8 +22138,8 @@ }, "ub_kernel_cgra_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U473"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U473"} + "genargs":{"ID":["String","_U448"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -22443,8 +22147,8 @@ }, "ub_kernel_cgra_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U488"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[66],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U488"} + "genargs":{"ID":["String","_U462"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[66],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -22452,8 +22156,8 @@ }, "ub_kernel_cgra_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U503"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[155],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U503"} + "genargs":{"ID":["String","_U476"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[155],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -22461,8 +22165,8 @@ }, "ub_kernel_cgra_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U518"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[194],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U518"} + "genargs":{"ID":["String","_U490"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[194],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -22474,13 +22178,13 @@ }, "ub_kernel_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U263"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[153],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[128],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U263"} + "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[153],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[128],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U533"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[283],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[258],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U533"} + "genargs":{"ID":["String","_U504"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[283],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[258],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -22488,8 +22192,8 @@ }, "ub_kernel_cgra_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U548"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[347],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[322],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U548"} + "genargs":{"ID":["String","_U518"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[347],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[322],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -22497,8 +22201,8 @@ }, "ub_kernel_cgra_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U563"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[411],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[386],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U563"} + "genargs":{"ID":["String","_U532"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[411],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[386],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -22506,8 +22210,8 @@ }, "ub_kernel_cgra_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U578"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[475],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[450],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U578"} + "genargs":{"ID":["String","_U546"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[475],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[450],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -22515,8 +22219,8 @@ }, "ub_kernel_cgra_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U593"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U593"} + "genargs":{"ID":["String","_U560"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -22524,8 +22228,8 @@ }, "ub_kernel_cgra_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U608"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[67],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U608"} + "genargs":{"ID":["String","_U574"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[67],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -22533,8 +22237,8 @@ }, "ub_kernel_cgra_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U623"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[156],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[131],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U623"} + "genargs":{"ID":["String","_U588"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[156],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[131],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -22542,8 +22246,8 @@ }, "ub_kernel_cgra_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U638"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[195],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U638"} + "genargs":{"ID":["String","_U602"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[195],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -22551,8 +22255,8 @@ }, "ub_kernel_cgra_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U653"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[284],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[259],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U653"} + "genargs":{"ID":["String","_U616"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[284],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[259],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -22560,8 +22264,8 @@ }, "ub_kernel_cgra_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U668"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[348],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[323],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U668"} + "genargs":{"ID":["String","_U630"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[348],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[323],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -22573,13 +22277,13 @@ }, "ub_kernel_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U278"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[192],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U278"} + "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[192],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U683"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[412],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[387],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U683"} + "genargs":{"ID":["String","_U644"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[412],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[387],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -22587,8 +22291,8 @@ }, "ub_kernel_cgra_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U698"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[476],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[451],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U698"} + "genargs":{"ID":["String","_U658"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[476],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[451],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -22596,8 +22300,8 @@ }, "ub_kernel_cgra_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U713"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U713"} + "genargs":{"ID":["String","_U672"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -22605,8 +22309,8 @@ }, "ub_kernel_cgra_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U728"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[68],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U728"} + "genargs":{"ID":["String","_U686"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[68],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -22614,8 +22318,8 @@ }, "ub_kernel_cgra_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U743"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[157],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[132],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U743"} + "genargs":{"ID":["String","_U700"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[157],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[132],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -22623,8 +22327,8 @@ }, "ub_kernel_cgra_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U758"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[196],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U758"} + "genargs":{"ID":["String","_U714"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[196],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -22632,8 +22336,8 @@ }, "ub_kernel_cgra_stencil_BANK_36":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U773"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[285],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U773"} + "genargs":{"ID":["String","_U728"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[285],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const":{ "modref":"corebit.const", @@ -22641,8 +22345,8 @@ }, "ub_kernel_cgra_stencil_BANK_37":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U788"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[349],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[324],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U788"} + "genargs":{"ID":["String","_U742"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[349],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[324],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const":{ "modref":"corebit.const", @@ -22650,8 +22354,8 @@ }, "ub_kernel_cgra_stencil_BANK_38":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U803"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[413],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[388],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U803"} + "genargs":{"ID":["String","_U756"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[413],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[388],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const":{ "modref":"corebit.const", @@ -22659,8 +22363,8 @@ }, "ub_kernel_cgra_stencil_BANK_39":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U818"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[477],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[452],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U818"} + "genargs":{"ID":["String","_U770"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[477],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[452],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const":{ "modref":"corebit.const", @@ -22672,13 +22376,13 @@ }, "ub_kernel_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U293"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[281],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[256],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U293"} + "genargs":{"ID":["String","_U280"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[281],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[256],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U833"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U833"} + "genargs":{"ID":["String","_U784"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const":{ "modref":"corebit.const", @@ -22686,8 +22390,8 @@ }, "ub_kernel_cgra_stencil_BANK_41":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U848"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[69],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U848"} + "genargs":{"ID":["String","_U798"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[69],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const":{ "modref":"corebit.const", @@ -22695,8 +22399,8 @@ }, "ub_kernel_cgra_stencil_BANK_42":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U863"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[158],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[133],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U863"} + "genargs":{"ID":["String","_U812"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[158],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[133],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const":{ "modref":"corebit.const", @@ -22704,8 +22408,8 @@ }, "ub_kernel_cgra_stencil_BANK_43":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U878"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[197],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U878"} + "genargs":{"ID":["String","_U826"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[197],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const":{ "modref":"corebit.const", @@ -22713,8 +22417,8 @@ }, "ub_kernel_cgra_stencil_BANK_44":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U893"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[286],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[261],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U893"} + "genargs":{"ID":["String","_U840"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[286],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[261],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const":{ "modref":"corebit.const", @@ -22722,8 +22426,8 @@ }, "ub_kernel_cgra_stencil_BANK_45":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U908"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[350],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[325],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U908"} + "genargs":{"ID":["String","_U854"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[350],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[325],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const":{ "modref":"corebit.const", @@ -22731,8 +22435,8 @@ }, "ub_kernel_cgra_stencil_BANK_46":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U923"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[414],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[389],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U923"} + "genargs":{"ID":["String","_U868"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[414],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[389],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const":{ "modref":"corebit.const", @@ -22740,8 +22444,8 @@ }, "ub_kernel_cgra_stencil_BANK_47":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U938"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[478],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[453],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U938"} + "genargs":{"ID":["String","_U882"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[478],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[453],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const":{ "modref":"corebit.const", @@ -22749,8 +22453,8 @@ }, "ub_kernel_cgra_stencil_BANK_48":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U953"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U953"} + "genargs":{"ID":["String","_U896"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const":{ "modref":"corebit.const", @@ -22758,8 +22462,8 @@ }, "ub_kernel_cgra_stencil_BANK_49":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U968"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[70],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U968"} + "genargs":{"ID":["String","_U910"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[70],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const":{ "modref":"corebit.const", @@ -22771,13 +22475,13 @@ }, "ub_kernel_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[345],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[320],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U308"} + "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[345],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[320],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U983"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[159],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[134],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U983"} + "genargs":{"ID":["String","_U924"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[159],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[134],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const":{ "modref":"corebit.const", @@ -22785,8 +22489,8 @@ }, "ub_kernel_cgra_stencil_BANK_51":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U998"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[198],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U998"} + "genargs":{"ID":["String","_U938"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[198],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const":{ "modref":"corebit.const", @@ -22794,8 +22498,8 @@ }, "ub_kernel_cgra_stencil_BANK_52":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1013"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[287],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[262],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1013"} + "genargs":{"ID":["String","_U952"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[287],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[262],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const":{ "modref":"corebit.const", @@ -22803,8 +22507,8 @@ }, "ub_kernel_cgra_stencil_BANK_53":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1028"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[351],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[326],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1028"} + "genargs":{"ID":["String","_U966"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[351],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[326],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const":{ "modref":"corebit.const", @@ -22812,8 +22516,8 @@ }, "ub_kernel_cgra_stencil_BANK_54":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1043"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[415],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[390],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1043"} + "genargs":{"ID":["String","_U980"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[415],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[390],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const":{ "modref":"corebit.const", @@ -22821,8 +22525,8 @@ }, "ub_kernel_cgra_stencil_BANK_55":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1058"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[479],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[454],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1058"} + "genargs":{"ID":["String","_U994"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[479],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[454],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const":{ "modref":"corebit.const", @@ -22830,8 +22534,8 @@ }, "ub_kernel_cgra_stencil_BANK_56":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1073"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1073"} + "genargs":{"ID":["String","_U1008"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const":{ "modref":"corebit.const", @@ -22839,8 +22543,8 @@ }, "ub_kernel_cgra_stencil_BANK_57":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1088"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[71],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1088"} + "genargs":{"ID":["String","_U1022"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[71],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const":{ "modref":"corebit.const", @@ -22848,8 +22552,8 @@ }, "ub_kernel_cgra_stencil_BANK_58":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[160],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[135],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1103"} + "genargs":{"ID":["String","_U1036"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[160],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[135],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const":{ "modref":"corebit.const", @@ -22857,8 +22561,8 @@ }, "ub_kernel_cgra_stencil_BANK_59":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[199],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1118"} + "genargs":{"ID":["String","_U1050"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[199],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const":{ "modref":"corebit.const", @@ -22870,13 +22574,13 @@ }, "ub_kernel_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U323"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[409],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[384],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U323"} + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[409],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[384],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[288],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[263],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1133"} + "genargs":{"ID":["String","_U1064"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[288],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[263],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const":{ "modref":"corebit.const", @@ -22884,8 +22588,8 @@ }, "ub_kernel_cgra_stencil_BANK_61":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[352],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[327],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1148"} + "genargs":{"ID":["String","_U1078"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[352],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[327],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const":{ "modref":"corebit.const", @@ -22893,8 +22597,8 @@ }, "ub_kernel_cgra_stencil_BANK_62":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[416],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[391],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1163"} + "genargs":{"ID":["String","_U1092"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[416],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[391],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const":{ "modref":"corebit.const", @@ -22902,8 +22606,8 @@ }, "ub_kernel_cgra_stencil_BANK_63":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[480],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[455],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1178"} + "genargs":{"ID":["String","_U1106"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[480],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[455],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const":{ "modref":"corebit.const", @@ -22915,8 +22619,8 @@ }, "ub_kernel_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U338"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[473],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[448],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U338"} + "genargs":{"ID":["String","_U322"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[473],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[448],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -22924,8 +22628,8 @@ }, "ub_kernel_cgra_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U353"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U353"} + "genargs":{"ID":["String","_U336"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -22933,8 +22637,8 @@ }, "ub_kernel_cgra_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U368"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[65],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U368"} + "genargs":{"ID":["String","_U350"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[65],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -22942,198 +22646,134 @@ } }, "connections":[ - ["ub_kernel_cgra_stencil_BANK_51.chain_chain_en","chain_en_const_U1012.out"], - ["ub_kernel_cgra_stencil_BANK_52.chain_chain_en","chain_en_const_U1027.out"], - ["ub_kernel_cgra_stencil_BANK_53.chain_chain_en","chain_en_const_U1042.out"], - ["ub_kernel_cgra_stencil_BANK_54.chain_chain_en","chain_en_const_U1057.out"], - ["ub_kernel_cgra_stencil_BANK_55.chain_chain_en","chain_en_const_U1072.out"], - ["ub_kernel_cgra_stencil_BANK_56.chain_chain_en","chain_en_const_U1087.out"], - ["ub_kernel_cgra_stencil_BANK_57.chain_chain_en","chain_en_const_U1102.out"], - ["ub_kernel_cgra_stencil_BANK_58.chain_chain_en","chain_en_const_U1117.out"], - ["ub_kernel_cgra_stencil_BANK_59.chain_chain_en","chain_en_const_U1132.out"], - ["ub_kernel_cgra_stencil_BANK_60.chain_chain_en","chain_en_const_U1147.out"], - ["ub_kernel_cgra_stencil_BANK_61.chain_chain_en","chain_en_const_U1162.out"], - ["ub_kernel_cgra_stencil_BANK_62.chain_chain_en","chain_en_const_U1177.out"], - ["ub_kernel_cgra_stencil_BANK_63.chain_chain_en","chain_en_const_U1192.out"], - ["ub_kernel_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U247.out"], - ["ub_kernel_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U262.out"], - ["ub_kernel_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U277.out"], - ["ub_kernel_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U292.out"], - ["ub_kernel_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U307.out"], - ["ub_kernel_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U322.out"], - ["ub_kernel_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U337.out"], - ["ub_kernel_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U352.out"], - ["ub_kernel_cgra_stencil_BANK_8.chain_chain_en","chain_en_const_U367.out"], - ["ub_kernel_cgra_stencil_BANK_9.chain_chain_en","chain_en_const_U382.out"], - ["ub_kernel_cgra_stencil_BANK_10.chain_chain_en","chain_en_const_U397.out"], - ["ub_kernel_cgra_stencil_BANK_11.chain_chain_en","chain_en_const_U412.out"], - ["ub_kernel_cgra_stencil_BANK_12.chain_chain_en","chain_en_const_U427.out"], - ["ub_kernel_cgra_stencil_BANK_13.chain_chain_en","chain_en_const_U442.out"], - ["ub_kernel_cgra_stencil_BANK_14.chain_chain_en","chain_en_const_U457.out"], - ["ub_kernel_cgra_stencil_BANK_15.chain_chain_en","chain_en_const_U472.out"], - ["ub_kernel_cgra_stencil_BANK_16.chain_chain_en","chain_en_const_U487.out"], - ["ub_kernel_cgra_stencil_BANK_17.chain_chain_en","chain_en_const_U502.out"], - ["ub_kernel_cgra_stencil_BANK_18.chain_chain_en","chain_en_const_U517.out"], - ["ub_kernel_cgra_stencil_BANK_19.chain_chain_en","chain_en_const_U532.out"], - ["ub_kernel_cgra_stencil_BANK_20.chain_chain_en","chain_en_const_U547.out"], - ["ub_kernel_cgra_stencil_BANK_21.chain_chain_en","chain_en_const_U562.out"], - ["ub_kernel_cgra_stencil_BANK_22.chain_chain_en","chain_en_const_U577.out"], - ["ub_kernel_cgra_stencil_BANK_23.chain_chain_en","chain_en_const_U592.out"], - ["ub_kernel_cgra_stencil_BANK_24.chain_chain_en","chain_en_const_U607.out"], - ["ub_kernel_cgra_stencil_BANK_25.chain_chain_en","chain_en_const_U622.out"], - ["ub_kernel_cgra_stencil_BANK_26.chain_chain_en","chain_en_const_U637.out"], - ["ub_kernel_cgra_stencil_BANK_27.chain_chain_en","chain_en_const_U652.out"], - ["ub_kernel_cgra_stencil_BANK_28.chain_chain_en","chain_en_const_U667.out"], - ["ub_kernel_cgra_stencil_BANK_29.chain_chain_en","chain_en_const_U682.out"], - ["ub_kernel_cgra_stencil_BANK_30.chain_chain_en","chain_en_const_U697.out"], - ["ub_kernel_cgra_stencil_BANK_31.chain_chain_en","chain_en_const_U712.out"], - ["ub_kernel_cgra_stencil_BANK_32.chain_chain_en","chain_en_const_U727.out"], - ["ub_kernel_cgra_stencil_BANK_33.chain_chain_en","chain_en_const_U742.out"], - ["ub_kernel_cgra_stencil_BANK_34.chain_chain_en","chain_en_const_U757.out"], - ["ub_kernel_cgra_stencil_BANK_35.chain_chain_en","chain_en_const_U772.out"], - ["ub_kernel_cgra_stencil_BANK_36.chain_chain_en","chain_en_const_U787.out"], - ["ub_kernel_cgra_stencil_BANK_37.chain_chain_en","chain_en_const_U802.out"], - ["ub_kernel_cgra_stencil_BANK_38.chain_chain_en","chain_en_const_U817.out"], - ["ub_kernel_cgra_stencil_BANK_39.chain_chain_en","chain_en_const_U832.out"], - ["ub_kernel_cgra_stencil_BANK_40.chain_chain_en","chain_en_const_U847.out"], - ["ub_kernel_cgra_stencil_BANK_41.chain_chain_en","chain_en_const_U862.out"], - ["ub_kernel_cgra_stencil_BANK_42.chain_chain_en","chain_en_const_U877.out"], - ["ub_kernel_cgra_stencil_BANK_43.chain_chain_en","chain_en_const_U892.out"], - ["ub_kernel_cgra_stencil_BANK_44.chain_chain_en","chain_en_const_U907.out"], - ["ub_kernel_cgra_stencil_BANK_45.chain_chain_en","chain_en_const_U922.out"], - ["ub_kernel_cgra_stencil_BANK_46.chain_chain_en","chain_en_const_U937.out"], - ["ub_kernel_cgra_stencil_BANK_47.chain_chain_en","chain_en_const_U952.out"], - ["ub_kernel_cgra_stencil_BANK_48.chain_chain_en","chain_en_const_U967.out"], - ["ub_kernel_cgra_stencil_BANK_49.chain_chain_en","chain_en_const_U982.out"], - ["ub_kernel_cgra_stencil_BANK_50.chain_chain_en","chain_en_const_U997.out"], - ["self.clk","ctrl__U1011.clk"], - ["ub_kernel_cgra_stencil_BANK_51.flush","ctrl__U1011.valid"], - ["self.clk","ctrl__U1026.clk"], - ["ub_kernel_cgra_stencil_BANK_52.flush","ctrl__U1026.valid"], - ["self.clk","ctrl__U1041.clk"], - ["ub_kernel_cgra_stencil_BANK_53.flush","ctrl__U1041.valid"], - ["self.clk","ctrl__U1056.clk"], - ["ub_kernel_cgra_stencil_BANK_54.flush","ctrl__U1056.valid"], - ["self.clk","ctrl__U1071.clk"], - ["ub_kernel_cgra_stencil_BANK_55.flush","ctrl__U1071.valid"], - ["self.clk","ctrl__U1086.clk"], - ["ub_kernel_cgra_stencil_BANK_56.flush","ctrl__U1086.valid"], - ["self.clk","ctrl__U1101.clk"], - ["ub_kernel_cgra_stencil_BANK_57.flush","ctrl__U1101.valid"], - ["self.clk","ctrl__U1116.clk"], - ["ub_kernel_cgra_stencil_BANK_58.flush","ctrl__U1116.valid"], - ["self.clk","ctrl__U1131.clk"], - ["ub_kernel_cgra_stencil_BANK_59.flush","ctrl__U1131.valid"], - ["self.clk","ctrl__U1146.clk"], - ["ub_kernel_cgra_stencil_BANK_60.flush","ctrl__U1146.valid"], - ["self.clk","ctrl__U1161.clk"], - ["ub_kernel_cgra_stencil_BANK_61.flush","ctrl__U1161.valid"], - ["self.clk","ctrl__U1176.clk"], - ["ub_kernel_cgra_stencil_BANK_62.flush","ctrl__U1176.valid"], - ["self.clk","ctrl__U1191.clk"], - ["ub_kernel_cgra_stencil_BANK_63.flush","ctrl__U1191.valid"], - ["self.clk","ctrl__U246.clk"], - ["ub_kernel_cgra_stencil_BANK_0.flush","ctrl__U246.valid"], - ["self.clk","ctrl__U261.clk"], - ["ub_kernel_cgra_stencil_BANK_1.flush","ctrl__U261.valid"], - ["self.clk","ctrl__U276.clk"], - ["ub_kernel_cgra_stencil_BANK_2.flush","ctrl__U276.valid"], - ["self.clk","ctrl__U291.clk"], - ["ub_kernel_cgra_stencil_BANK_3.flush","ctrl__U291.valid"], - ["self.clk","ctrl__U306.clk"], - ["ub_kernel_cgra_stencil_BANK_4.flush","ctrl__U306.valid"], + ["self.clk","ctrl__U1007.clk"], + ["ub_kernel_cgra_stencil_BANK_55.flush","ctrl__U1007.valid"], + ["self.clk","ctrl__U1021.clk"], + ["ub_kernel_cgra_stencil_BANK_56.flush","ctrl__U1021.valid"], + ["self.clk","ctrl__U1035.clk"], + ["ub_kernel_cgra_stencil_BANK_57.flush","ctrl__U1035.valid"], + ["self.clk","ctrl__U1049.clk"], + ["ub_kernel_cgra_stencil_BANK_58.flush","ctrl__U1049.valid"], + ["self.clk","ctrl__U1063.clk"], + ["ub_kernel_cgra_stencil_BANK_59.flush","ctrl__U1063.valid"], + ["self.clk","ctrl__U1077.clk"], + ["ub_kernel_cgra_stencil_BANK_60.flush","ctrl__U1077.valid"], + ["self.clk","ctrl__U1091.clk"], + ["ub_kernel_cgra_stencil_BANK_61.flush","ctrl__U1091.valid"], + ["self.clk","ctrl__U1105.clk"], + ["ub_kernel_cgra_stencil_BANK_62.flush","ctrl__U1105.valid"], + ["self.clk","ctrl__U1119.clk"], + ["ub_kernel_cgra_stencil_BANK_63.flush","ctrl__U1119.valid"], + ["self.clk","ctrl__U237.clk"], + ["ub_kernel_cgra_stencil_BANK_0.flush","ctrl__U237.valid"], + ["self.clk","ctrl__U251.clk"], + ["ub_kernel_cgra_stencil_BANK_1.flush","ctrl__U251.valid"], + ["self.clk","ctrl__U265.clk"], + ["ub_kernel_cgra_stencil_BANK_2.flush","ctrl__U265.valid"], + ["self.clk","ctrl__U279.clk"], + ["ub_kernel_cgra_stencil_BANK_3.flush","ctrl__U279.valid"], + ["self.clk","ctrl__U293.clk"], + ["ub_kernel_cgra_stencil_BANK_4.flush","ctrl__U293.valid"], + ["self.clk","ctrl__U307.clk"], + ["ub_kernel_cgra_stencil_BANK_5.flush","ctrl__U307.valid"], ["self.clk","ctrl__U321.clk"], - ["ub_kernel_cgra_stencil_BANK_5.flush","ctrl__U321.valid"], - ["self.clk","ctrl__U336.clk"], - ["ub_kernel_cgra_stencil_BANK_6.flush","ctrl__U336.valid"], - ["self.clk","ctrl__U351.clk"], - ["ub_kernel_cgra_stencil_BANK_7.flush","ctrl__U351.valid"], - ["self.clk","ctrl__U366.clk"], - ["ub_kernel_cgra_stencil_BANK_8.flush","ctrl__U366.valid"], - ["self.clk","ctrl__U381.clk"], - ["ub_kernel_cgra_stencil_BANK_9.flush","ctrl__U381.valid"], - ["self.clk","ctrl__U396.clk"], - ["ub_kernel_cgra_stencil_BANK_10.flush","ctrl__U396.valid"], - ["self.clk","ctrl__U411.clk"], - ["ub_kernel_cgra_stencil_BANK_11.flush","ctrl__U411.valid"], - ["self.clk","ctrl__U426.clk"], - ["ub_kernel_cgra_stencil_BANK_12.flush","ctrl__U426.valid"], - ["self.clk","ctrl__U441.clk"], - ["ub_kernel_cgra_stencil_BANK_13.flush","ctrl__U441.valid"], - ["self.clk","ctrl__U456.clk"], - ["ub_kernel_cgra_stencil_BANK_14.flush","ctrl__U456.valid"], - ["self.clk","ctrl__U471.clk"], - ["ub_kernel_cgra_stencil_BANK_15.flush","ctrl__U471.valid"], - ["self.clk","ctrl__U486.clk"], - ["ub_kernel_cgra_stencil_BANK_16.flush","ctrl__U486.valid"], - ["self.clk","ctrl__U501.clk"], - ["ub_kernel_cgra_stencil_BANK_17.flush","ctrl__U501.valid"], - ["self.clk","ctrl__U516.clk"], - ["ub_kernel_cgra_stencil_BANK_18.flush","ctrl__U516.valid"], + ["ub_kernel_cgra_stencil_BANK_6.flush","ctrl__U321.valid"], + ["self.clk","ctrl__U335.clk"], + ["ub_kernel_cgra_stencil_BANK_7.flush","ctrl__U335.valid"], + ["self.clk","ctrl__U349.clk"], + ["ub_kernel_cgra_stencil_BANK_8.flush","ctrl__U349.valid"], + ["self.clk","ctrl__U363.clk"], + ["ub_kernel_cgra_stencil_BANK_9.flush","ctrl__U363.valid"], + ["self.clk","ctrl__U377.clk"], + ["ub_kernel_cgra_stencil_BANK_10.flush","ctrl__U377.valid"], + ["self.clk","ctrl__U391.clk"], + ["ub_kernel_cgra_stencil_BANK_11.flush","ctrl__U391.valid"], + ["self.clk","ctrl__U405.clk"], + ["ub_kernel_cgra_stencil_BANK_12.flush","ctrl__U405.valid"], + ["self.clk","ctrl__U419.clk"], + ["ub_kernel_cgra_stencil_BANK_13.flush","ctrl__U419.valid"], + ["self.clk","ctrl__U433.clk"], + ["ub_kernel_cgra_stencil_BANK_14.flush","ctrl__U433.valid"], + ["self.clk","ctrl__U447.clk"], + ["ub_kernel_cgra_stencil_BANK_15.flush","ctrl__U447.valid"], + ["self.clk","ctrl__U461.clk"], + ["ub_kernel_cgra_stencil_BANK_16.flush","ctrl__U461.valid"], + ["self.clk","ctrl__U475.clk"], + ["ub_kernel_cgra_stencil_BANK_17.flush","ctrl__U475.valid"], + ["self.clk","ctrl__U489.clk"], + ["ub_kernel_cgra_stencil_BANK_18.flush","ctrl__U489.valid"], + ["self.clk","ctrl__U503.clk"], + ["ub_kernel_cgra_stencil_BANK_19.flush","ctrl__U503.valid"], + ["self.clk","ctrl__U517.clk"], + ["ub_kernel_cgra_stencil_BANK_20.flush","ctrl__U517.valid"], ["self.clk","ctrl__U531.clk"], - ["ub_kernel_cgra_stencil_BANK_19.flush","ctrl__U531.valid"], - ["self.clk","ctrl__U546.clk"], - ["ub_kernel_cgra_stencil_BANK_20.flush","ctrl__U546.valid"], - ["self.clk","ctrl__U561.clk"], - ["ub_kernel_cgra_stencil_BANK_21.flush","ctrl__U561.valid"], - ["self.clk","ctrl__U576.clk"], - ["ub_kernel_cgra_stencil_BANK_22.flush","ctrl__U576.valid"], - ["self.clk","ctrl__U591.clk"], - ["ub_kernel_cgra_stencil_BANK_23.flush","ctrl__U591.valid"], - ["self.clk","ctrl__U606.clk"], - ["ub_kernel_cgra_stencil_BANK_24.flush","ctrl__U606.valid"], - ["self.clk","ctrl__U621.clk"], - ["ub_kernel_cgra_stencil_BANK_25.flush","ctrl__U621.valid"], - ["self.clk","ctrl__U636.clk"], - ["ub_kernel_cgra_stencil_BANK_26.flush","ctrl__U636.valid"], - ["self.clk","ctrl__U651.clk"], - ["ub_kernel_cgra_stencil_BANK_27.flush","ctrl__U651.valid"], - ["self.clk","ctrl__U666.clk"], - ["ub_kernel_cgra_stencil_BANK_28.flush","ctrl__U666.valid"], - ["self.clk","ctrl__U681.clk"], - ["ub_kernel_cgra_stencil_BANK_29.flush","ctrl__U681.valid"], - ["self.clk","ctrl__U696.clk"], - ["ub_kernel_cgra_stencil_BANK_30.flush","ctrl__U696.valid"], - ["self.clk","ctrl__U711.clk"], - ["ub_kernel_cgra_stencil_BANK_31.flush","ctrl__U711.valid"], - ["self.clk","ctrl__U726.clk"], - ["ub_kernel_cgra_stencil_BANK_32.flush","ctrl__U726.valid"], + ["ub_kernel_cgra_stencil_BANK_21.flush","ctrl__U531.valid"], + ["self.clk","ctrl__U545.clk"], + ["ub_kernel_cgra_stencil_BANK_22.flush","ctrl__U545.valid"], + ["self.clk","ctrl__U559.clk"], + ["ub_kernel_cgra_stencil_BANK_23.flush","ctrl__U559.valid"], + ["self.clk","ctrl__U573.clk"], + ["ub_kernel_cgra_stencil_BANK_24.flush","ctrl__U573.valid"], + ["self.clk","ctrl__U587.clk"], + ["ub_kernel_cgra_stencil_BANK_25.flush","ctrl__U587.valid"], + ["self.clk","ctrl__U601.clk"], + ["ub_kernel_cgra_stencil_BANK_26.flush","ctrl__U601.valid"], + ["self.clk","ctrl__U615.clk"], + ["ub_kernel_cgra_stencil_BANK_27.flush","ctrl__U615.valid"], + ["self.clk","ctrl__U629.clk"], + ["ub_kernel_cgra_stencil_BANK_28.flush","ctrl__U629.valid"], + ["self.clk","ctrl__U643.clk"], + ["ub_kernel_cgra_stencil_BANK_29.flush","ctrl__U643.valid"], + ["self.clk","ctrl__U657.clk"], + ["ub_kernel_cgra_stencil_BANK_30.flush","ctrl__U657.valid"], + ["self.clk","ctrl__U671.clk"], + ["ub_kernel_cgra_stencil_BANK_31.flush","ctrl__U671.valid"], + ["self.clk","ctrl__U685.clk"], + ["ub_kernel_cgra_stencil_BANK_32.flush","ctrl__U685.valid"], + ["self.clk","ctrl__U699.clk"], + ["ub_kernel_cgra_stencil_BANK_33.flush","ctrl__U699.valid"], + ["self.clk","ctrl__U713.clk"], + ["ub_kernel_cgra_stencil_BANK_34.flush","ctrl__U713.valid"], + ["self.clk","ctrl__U727.clk"], + ["ub_kernel_cgra_stencil_BANK_35.flush","ctrl__U727.valid"], ["self.clk","ctrl__U741.clk"], - ["ub_kernel_cgra_stencil_BANK_33.flush","ctrl__U741.valid"], - ["self.clk","ctrl__U756.clk"], - ["ub_kernel_cgra_stencil_BANK_34.flush","ctrl__U756.valid"], - ["self.clk","ctrl__U771.clk"], - ["ub_kernel_cgra_stencil_BANK_35.flush","ctrl__U771.valid"], - ["self.clk","ctrl__U786.clk"], - ["ub_kernel_cgra_stencil_BANK_36.flush","ctrl__U786.valid"], - ["self.clk","ctrl__U801.clk"], - ["ub_kernel_cgra_stencil_BANK_37.flush","ctrl__U801.valid"], - ["self.clk","ctrl__U816.clk"], - ["ub_kernel_cgra_stencil_BANK_38.flush","ctrl__U816.valid"], - ["self.clk","ctrl__U831.clk"], - ["ub_kernel_cgra_stencil_BANK_39.flush","ctrl__U831.valid"], - ["self.clk","ctrl__U846.clk"], - ["ub_kernel_cgra_stencil_BANK_40.flush","ctrl__U846.valid"], - ["self.clk","ctrl__U861.clk"], - ["ub_kernel_cgra_stencil_BANK_41.flush","ctrl__U861.valid"], - ["self.clk","ctrl__U876.clk"], - ["ub_kernel_cgra_stencil_BANK_42.flush","ctrl__U876.valid"], - ["self.clk","ctrl__U891.clk"], - ["ub_kernel_cgra_stencil_BANK_43.flush","ctrl__U891.valid"], - ["self.clk","ctrl__U906.clk"], - ["ub_kernel_cgra_stencil_BANK_44.flush","ctrl__U906.valid"], - ["self.clk","ctrl__U921.clk"], - ["ub_kernel_cgra_stencil_BANK_45.flush","ctrl__U921.valid"], - ["self.clk","ctrl__U936.clk"], - ["ub_kernel_cgra_stencil_BANK_46.flush","ctrl__U936.valid"], + ["ub_kernel_cgra_stencil_BANK_36.flush","ctrl__U741.valid"], + ["self.clk","ctrl__U755.clk"], + ["ub_kernel_cgra_stencil_BANK_37.flush","ctrl__U755.valid"], + ["self.clk","ctrl__U769.clk"], + ["ub_kernel_cgra_stencil_BANK_38.flush","ctrl__U769.valid"], + ["self.clk","ctrl__U783.clk"], + ["ub_kernel_cgra_stencil_BANK_39.flush","ctrl__U783.valid"], + ["self.clk","ctrl__U797.clk"], + ["ub_kernel_cgra_stencil_BANK_40.flush","ctrl__U797.valid"], + ["self.clk","ctrl__U811.clk"], + ["ub_kernel_cgra_stencil_BANK_41.flush","ctrl__U811.valid"], + ["self.clk","ctrl__U825.clk"], + ["ub_kernel_cgra_stencil_BANK_42.flush","ctrl__U825.valid"], + ["self.clk","ctrl__U839.clk"], + ["ub_kernel_cgra_stencil_BANK_43.flush","ctrl__U839.valid"], + ["self.clk","ctrl__U853.clk"], + ["ub_kernel_cgra_stencil_BANK_44.flush","ctrl__U853.valid"], + ["self.clk","ctrl__U867.clk"], + ["ub_kernel_cgra_stencil_BANK_45.flush","ctrl__U867.valid"], + ["self.clk","ctrl__U881.clk"], + ["ub_kernel_cgra_stencil_BANK_46.flush","ctrl__U881.valid"], + ["self.clk","ctrl__U895.clk"], + ["ub_kernel_cgra_stencil_BANK_47.flush","ctrl__U895.valid"], + ["self.clk","ctrl__U909.clk"], + ["ub_kernel_cgra_stencil_BANK_48.flush","ctrl__U909.valid"], + ["self.clk","ctrl__U923.clk"], + ["ub_kernel_cgra_stencil_BANK_49.flush","ctrl__U923.valid"], + ["self.clk","ctrl__U937.clk"], + ["ub_kernel_cgra_stencil_BANK_50.flush","ctrl__U937.valid"], ["self.clk","ctrl__U951.clk"], - ["ub_kernel_cgra_stencil_BANK_47.flush","ctrl__U951.valid"], - ["self.clk","ctrl__U966.clk"], - ["ub_kernel_cgra_stencil_BANK_48.flush","ctrl__U966.valid"], - ["self.clk","ctrl__U981.clk"], - ["ub_kernel_cgra_stencil_BANK_49.flush","ctrl__U981.valid"], - ["self.clk","ctrl__U996.clk"], - ["ub_kernel_cgra_stencil_BANK_50.flush","ctrl__U996.valid"], + ["ub_kernel_cgra_stencil_BANK_51.flush","ctrl__U951.valid"], + ["self.clk","ctrl__U965.clk"], + ["ub_kernel_cgra_stencil_BANK_52.flush","ctrl__U965.valid"], + ["self.clk","ctrl__U979.clk"], + ["ub_kernel_cgra_stencil_BANK_53.flush","ctrl__U979.valid"], + ["self.clk","ctrl__U993.clk"], + ["ub_kernel_cgra_stencil_BANK_54.flush","ctrl__U993.valid"], ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_1.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_10.clk","self.clk"], @@ -23467,49 +23107,49 @@ ["op_hcompute_kernel_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U1341":{ - "modref":"global.aff__U1312" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U1267":{ + "modref":"global.aff__U1238" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U1242":{ - "modref":"global.aff__U1225" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U1168":{ + "modref":"global.aff__U1151" }, - "chain_en_const_U1342":{ + "chain_en_const_U1268":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U1224":{ - "modref":"global.affine_controller__U1194", + "ctrl__U1150":{ + "modref":"global.affine_controller__U1120", "metadata":{"garnet_remove":true} }, - "ctrl__U1311":{ - "modref":"global.affine_controller__U1243", + "ctrl__U1237":{ + "modref":"global.affine_controller__U1169", "metadata":{"garnet_remove":true} }, "kernel_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[73728],"cycle_stride":[1,64,2048,18432,36864],"dimensionality":5,"extent":[64,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,128,8192,4096,64]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[73728],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U1193"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[73728],"cycle_stride":[1,64,2048,18432,36864],"dimensionality":5,"extent":[64,32,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,128,8192,4096,64]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[73728],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U1311.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U1341.d"], - ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U1341.out"], - ["ctrl__U1224.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U1242.d"], - ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U1242.out"], - ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U1342.out"], - ["self.clk","ctrl__U1224.clk"], - ["self.reset","ctrl__U1224.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U1224.valid"], - ["self.clk","ctrl__U1311.clk"], - ["self.reset","ctrl__U1311.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U1311.valid"], + ["ctrl__U1237.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U1267.d"], + ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U1267.out"], + ["ctrl__U1150.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U1168.d"], + ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U1168.out"], + ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U1268.out"], + ["self.clk","ctrl__U1150.clk"], + ["self.reset","ctrl__U1150.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U1150.valid"], + ["self.clk","ctrl__U1237.clk"], + ["self.reset","ctrl__U1237.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U1237.valid"], ["self.clk","kernel_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_kernel_glb_stencil_write.0","kernel_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_kernel_cgra_stencil_read.0","kernel_glb_stencil_BANK_0_ubuf.data_out_0"], ["self.reset","kernel_glb_stencil_BANK_0_ubuf.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U1590":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U1507":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -23518,7 +23158,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U1589":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U1506":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23527,7 +23167,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U1588":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U1505":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -23536,7 +23176,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U1587":{ + "op_hcompute_hw_output_stencil_read_start_pt__U1504":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23545,7 +23185,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U1592":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U1509":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -23554,7 +23194,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U1591":{ + "op_hcompute_hw_output_stencil_write_start_pt__U1508":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23563,7 +23203,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U1600":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U1517":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23572,7 +23212,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U1599":{ + "op_hcompute_input_glb_stencil_read_start_pt__U1516":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23581,7 +23221,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U1601":{ + "op_hcompute_input_glb_stencil_write_start_pt__U1518":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23590,7 +23230,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U1595":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U1512":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23599,7 +23239,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U1594":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U1511":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23608,7 +23248,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U1596":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U1513":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -23674,74 +23314,42 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1357":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1372":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1387":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1402":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1417":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1432":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1447":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1462":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ctrl__U1356":{ - "modref":"global.affine_controller__U1344", + "ctrl__U1282":{ + "modref":"global.affine_controller__U1270", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1371":{ - "modref":"global.affine_controller__U1359", + "ctrl__U1296":{ + "modref":"global.affine_controller__U1284", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1386":{ - "modref":"global.affine_controller__U1374", + "ctrl__U1310":{ + "modref":"global.affine_controller__U1298", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1401":{ - "modref":"global.affine_controller__U1389", + "ctrl__U1324":{ + "modref":"global.affine_controller__U1312", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1416":{ - "modref":"global.affine_controller__U1404", + "ctrl__U1338":{ + "modref":"global.affine_controller__U1326", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1431":{ - "modref":"global.affine_controller__U1419", + "ctrl__U1352":{ + "modref":"global.affine_controller__U1340", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1446":{ - "modref":"global.affine_controller__U1434", + "ctrl__U1366":{ + "modref":"global.affine_controller__U1354", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U1461":{ - "modref":"global.affine_controller__U1449", + "ctrl__U1380":{ + "modref":"global.affine_controller__U1368", "metadata":{"garnet_rewire_flush":true} }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1343"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50974],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50976],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1343"} + "genargs":{"ID":["String","_U1269"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50974],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50976],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -23749,8 +23357,8 @@ }, "ub_output_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1358"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"agg2sram_1":{"cycle_starting_addr":[18437],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"in2agg_1":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50977],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1358"} + "genargs":{"ID":["String","_U1283"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"agg2sram_1":{"cycle_starting_addr":[18437],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"in2agg_1":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50977],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -23758,8 +23366,8 @@ }, "ub_output_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1373"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50978],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1373"} + "genargs":{"ID":["String","_U1297"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50978],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -23767,8 +23375,8 @@ }, "ub_output_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1388"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50977],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50979],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1388"} + "genargs":{"ID":["String","_U1311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50977],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50979],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -23776,8 +23384,8 @@ }, "ub_output_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1403"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50978],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50980],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1403"} + "genargs":{"ID":["String","_U1325"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50978],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50980],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -23785,8 +23393,8 @@ }, "ub_output_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1418"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50979],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50981],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1418"} + "genargs":{"ID":["String","_U1339"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50979],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50981],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -23794,8 +23402,8 @@ }, "ub_output_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1433"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50980],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50982],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1433"} + "genargs":{"ID":["String","_U1353"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50980],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50982],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -23803,8 +23411,8 @@ }, "ub_output_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1448"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50981],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50983],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U1448"} + "genargs":{"ID":["String","_U1367"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50981],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50983],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -23812,30 +23420,22 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U1357.out"], - ["ub_output_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U1372.out"], - ["ub_output_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U1387.out"], - ["ub_output_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U1402.out"], - ["ub_output_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U1417.out"], - ["ub_output_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U1432.out"], - ["ub_output_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U1447.out"], - ["ub_output_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U1462.out"], - ["self.clk","ctrl__U1356.clk"], - ["ub_output_cgra_stencil_BANK_0.flush","ctrl__U1356.valid"], - ["self.clk","ctrl__U1371.clk"], - ["ub_output_cgra_stencil_BANK_1.flush","ctrl__U1371.valid"], - ["self.clk","ctrl__U1386.clk"], - ["ub_output_cgra_stencil_BANK_2.flush","ctrl__U1386.valid"], - ["self.clk","ctrl__U1401.clk"], - ["ub_output_cgra_stencil_BANK_3.flush","ctrl__U1401.valid"], - ["self.clk","ctrl__U1416.clk"], - ["ub_output_cgra_stencil_BANK_4.flush","ctrl__U1416.valid"], - ["self.clk","ctrl__U1431.clk"], - ["ub_output_cgra_stencil_BANK_5.flush","ctrl__U1431.valid"], - ["self.clk","ctrl__U1446.clk"], - ["ub_output_cgra_stencil_BANK_6.flush","ctrl__U1446.valid"], - ["self.clk","ctrl__U1461.clk"], - ["ub_output_cgra_stencil_BANK_7.flush","ctrl__U1461.valid"], + ["self.clk","ctrl__U1282.clk"], + ["ub_output_cgra_stencil_BANK_0.flush","ctrl__U1282.valid"], + ["self.clk","ctrl__U1296.clk"], + ["ub_output_cgra_stencil_BANK_1.flush","ctrl__U1296.valid"], + ["self.clk","ctrl__U1310.clk"], + ["ub_output_cgra_stencil_BANK_2.flush","ctrl__U1310.valid"], + ["self.clk","ctrl__U1324.clk"], + ["ub_output_cgra_stencil_BANK_3.flush","ctrl__U1324.valid"], + ["self.clk","ctrl__U1338.clk"], + ["ub_output_cgra_stencil_BANK_4.flush","ctrl__U1338.valid"], + ["self.clk","ctrl__U1352.clk"], + ["ub_output_cgra_stencil_BANK_5.flush","ctrl__U1352.valid"], + ["self.clk","ctrl__U1366.clk"], + ["ub_output_cgra_stencil_BANK_6.flush","ctrl__U1366.valid"], + ["self.clk","ctrl__U1380.clk"], + ["ub_output_cgra_stencil_BANK_7.flush","ctrl__U1380.valid"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], @@ -23905,42 +23505,42 @@ ["op_hcompute_output_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U1562":{ - "modref":"global.aff__U1548" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U1479":{ + "modref":"global.aff__U1465" }, - "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U1523":{ - "modref":"global.aff__U1503" + "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U1440":{ + "modref":"global.aff__U1420" }, - "chain_en_const_U1563":{ + "chain_en_const_U1480":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U1502":{ - "modref":"global.affine_controller__U1464", + "ctrl__U1419":{ + "modref":"global.affine_controller__U1381", "metadata":{"garnet_remove":true} }, - "ctrl__U1547":{ - "modref":"global.affine_controller__U1524", + "ctrl__U1464":{ + "modref":"global.affine_controller__U1441", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[164704],"cycle_stride":[1],"dimensionality":1,"extent":[6272],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[124704],"cycle_stride":[1,64,36864],"dimensionality":3,"extent":[64,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,128,64]}},"mode":"glb","verilog_name":"glb__U1463"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[164704],"cycle_stride":[1],"dimensionality":1,"extent":[6272],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[124704],"cycle_stride":[1,64,36864],"dimensionality":3,"extent":[64,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,128,64]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U1547.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U1562.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U1562.out"], - ["ctrl__U1502.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U1523.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U1523.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U1563.out"], - ["self.clk","ctrl__U1502.clk"], - ["self.reset","ctrl__U1502.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U1502.valid"], - ["self.clk","ctrl__U1547.clk"], - ["self.reset","ctrl__U1547.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U1547.valid"], + ["ctrl__U1464.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U1479.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U1479.out"], + ["ctrl__U1419.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U1440.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U1440.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U1480.out"], + ["self.clk","ctrl__U1419.clk"], + ["self.reset","ctrl__U1419.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U1419.valid"], + ["self.clk","ctrl__U1464.clk"], + ["self.reset","ctrl__U1464.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U1464.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_glb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -23959,12 +23559,12 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U1597":{ + "_U1514":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1602":{ + "_U1519":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -23985,26 +23585,26 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U1589" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U1506" }, "op_hcompute_hw_output_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U1590" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U1507" }, "op_hcompute_hw_output_stencil_port_controller":{ - "modref":"global.affine_controller__U1564", + "modref":"global.affine_controller__U1481", "metadata":{"lake_config":{"stencil_valid":{"cycle_starting_addr":[164704],"cycle_stride":[1,128,896],"dimensionality":3,"extent":[128,7,7]}}} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U1587" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U1504" }, "op_hcompute_hw_output_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U1588" + "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U1505" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U1591" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U1508" }, "op_hcompute_hw_output_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U1592" + "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U1509" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" @@ -24013,22 +23613,22 @@ "modref":"global.cu_op_hcompute_input_glb_stencil" }, "op_hcompute_input_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U1600" + "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U1517" }, "op_hcompute_input_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1598"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64,576],"dimensionality":3,"extent":[64,9,9]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U1598"} + "genargs":{"ID":["String","_U1515"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64,576],"dimensionality":3,"extent":[64,9,9]}},"mode":"lake"} }, "op_hcompute_input_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_glb_stencil_read_start":{ - "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U1599" + "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U1516" }, "op_hcompute_input_glb_stencil_write_start":{ - "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U1601" + "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U1518" }, "op_hcompute_kernel_cgra_stencil":{ "modref":"global.cu_op_hcompute_kernel_cgra_stencil" @@ -24037,22 +23637,22 @@ "modref":"global.cu_op_hcompute_kernel_glb_stencil" }, "op_hcompute_kernel_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U1595" + "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U1512" }, "op_hcompute_kernel_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U1593"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128,8192,24576],"dimensionality":4,"extent":[128,64,3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U1593"} + "genargs":{"ID":["String","_U1510"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128,8192,24576],"dimensionality":4,"extent":[128,64,3,3]}},"mode":"lake"} }, "op_hcompute_kernel_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_kernel_glb_stencil_read_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U1594" + "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U1511" }, "op_hcompute_kernel_glb_stencil_write_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U1596" + "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U1513" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -24113,10 +23713,10 @@ } }, "connections":[ - ["self.clk","_U1597.clk"], - ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U1597.in"], - ["self.clk","_U1602.clk"], - ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U1602.in"], + ["self.clk","_U1514.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U1514.in"], + ["self.clk","_U1519.clk"], + ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U1519.in"], ["self.clk","input_cgra_stencil.clk"], ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], ["op_hcompute_output_cgra_stencil_10.input_cgra_stencil_op_hcompute_output_cgra_stencil_10_read","input_cgra_stencil.op_hcompute_output_cgra_stencil_10_read"], diff --git a/aha_garnet_design_new/resnet5_x/resnet5_x_garnet.json b/aha_garnet_design_new/resnet5_x/resnet5_x_garnet.json index 3d670ccf1..0302e8e89 100644 --- a/aha_garnet_design_new/resnet5_x/resnet5_x_garnet.json +++ b/aha_garnet_design_new/resnet5_x/resnet5_x_garnet.json @@ -232,3720 +232,3570 @@ }, "global":{ "modules":{ - "aff__U1000":{ + "aff__U100":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1006":{ + "add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1007":{ + "add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1001":{ + "coeff_0_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1003":{ + "coeff_1_U103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1005":{ + "const_term_U105":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1002":{ + "mul_d0__U102":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1004":{ + "mul_d1__U104":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1002.out","add_all__U1006.in0"], - ["mul_d1__U1004.out","add_all__U1006.in1"], - ["add_all__U1007.in0","add_all__U1006.out"], - ["const_term_U1005.out","add_all__U1007.in1"], - ["self.out","add_all__U1007.out"], - ["mul_d0__U1002.in0","coeff_0_U1001.out"], - ["mul_d1__U1004.in0","coeff_1_U1003.out"], - ["self.d.0","mul_d0__U1002.in1"], - ["self.d.1","mul_d1__U1004.in1"] + ["mul_d0__U102.out","add_all__U106.in0"], + ["mul_d1__U104.out","add_all__U106.in1"], + ["add_all__U107.in0","add_all__U106.out"], + ["const_term_U105.out","add_all__U107.in1"], + ["self.out","add_all__U107.out"], + ["mul_d0__U102.in0","coeff_0_U101.out"], + ["mul_d1__U104.in0","coeff_1_U103.out"], + ["self.d.0","mul_d0__U102.in1"], + ["self.d.1","mul_d1__U104.in1"] ] }, - "aff__U1015":{ + "aff__U1010":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1021":{ + "add_all__U1016":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1022":{ + "add_all__U1017":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1016":{ + "coeff_0_U1011":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1018":{ + "coeff_1_U1013":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1020":{ + "const_term_U1015":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1017":{ + "mul_d0__U1012":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1019":{ + "mul_d1__U1014":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1017.out","add_all__U1021.in0"], - ["mul_d1__U1019.out","add_all__U1021.in1"], - ["add_all__U1022.in0","add_all__U1021.out"], - ["const_term_U1020.out","add_all__U1022.in1"], - ["self.out","add_all__U1022.out"], - ["mul_d0__U1017.in0","coeff_0_U1016.out"], - ["mul_d1__U1019.in0","coeff_1_U1018.out"], - ["self.d.0","mul_d0__U1017.in1"], - ["self.d.1","mul_d1__U1019.in1"] + ["mul_d0__U1012.out","add_all__U1016.in0"], + ["mul_d1__U1014.out","add_all__U1016.in1"], + ["add_all__U1017.in0","add_all__U1016.out"], + ["const_term_U1015.out","add_all__U1017.in1"], + ["self.out","add_all__U1017.out"], + ["mul_d0__U1012.in0","coeff_0_U1011.out"], + ["mul_d1__U1014.in0","coeff_1_U1013.out"], + ["self.d.0","mul_d0__U1012.in1"], + ["self.d.1","mul_d1__U1014.in1"] ] }, - "aff__U1030":{ + "aff__U1024":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1036":{ + "add_all__U1030":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1037":{ + "add_all__U1031":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1031":{ + "coeff_0_U1025":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1033":{ + "coeff_1_U1027":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1035":{ + "const_term_U1029":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1032":{ + "mul_d0__U1026":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1034":{ + "mul_d1__U1028":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1032.out","add_all__U1036.in0"], - ["mul_d1__U1034.out","add_all__U1036.in1"], - ["add_all__U1037.in0","add_all__U1036.out"], - ["const_term_U1035.out","add_all__U1037.in1"], - ["self.out","add_all__U1037.out"], - ["mul_d0__U1032.in0","coeff_0_U1031.out"], - ["mul_d1__U1034.in0","coeff_1_U1033.out"], - ["self.d.0","mul_d0__U1032.in1"], - ["self.d.1","mul_d1__U1034.in1"] + ["mul_d0__U1026.out","add_all__U1030.in0"], + ["mul_d1__U1028.out","add_all__U1030.in1"], + ["add_all__U1031.in0","add_all__U1030.out"], + ["const_term_U1029.out","add_all__U1031.in1"], + ["self.out","add_all__U1031.out"], + ["mul_d0__U1026.in0","coeff_0_U1025.out"], + ["mul_d1__U1028.in0","coeff_1_U1027.out"], + ["self.d.0","mul_d0__U1026.in1"], + ["self.d.1","mul_d1__U1028.in1"] ] }, - "aff__U1045":{ + "aff__U1038":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1051":{ + "add_all__U1044":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1052":{ + "add_all__U1045":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1046":{ + "coeff_0_U1039":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1048":{ + "coeff_1_U1041":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1050":{ + "const_term_U1043":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1047":{ + "mul_d0__U1040":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1049":{ + "mul_d1__U1042":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1047.out","add_all__U1051.in0"], - ["mul_d1__U1049.out","add_all__U1051.in1"], - ["add_all__U1052.in0","add_all__U1051.out"], - ["const_term_U1050.out","add_all__U1052.in1"], - ["self.out","add_all__U1052.out"], - ["mul_d0__U1047.in0","coeff_0_U1046.out"], - ["mul_d1__U1049.in0","coeff_1_U1048.out"], - ["self.d.0","mul_d0__U1047.in1"], - ["self.d.1","mul_d1__U1049.in1"] + ["mul_d0__U1040.out","add_all__U1044.in0"], + ["mul_d1__U1042.out","add_all__U1044.in1"], + ["add_all__U1045.in0","add_all__U1044.out"], + ["const_term_U1043.out","add_all__U1045.in1"], + ["self.out","add_all__U1045.out"], + ["mul_d0__U1040.in0","coeff_0_U1039.out"], + ["mul_d1__U1042.in0","coeff_1_U1041.out"], + ["self.d.0","mul_d0__U1040.in1"], + ["self.d.1","mul_d1__U1042.in1"] ] }, - "aff__U1060":{ + "aff__U1052":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1066":{ + "add_all__U1058":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1067":{ + "add_all__U1059":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1061":{ + "coeff_0_U1053":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1063":{ + "coeff_1_U1055":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1065":{ + "const_term_U1057":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1062":{ + "mul_d0__U1054":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1064":{ + "mul_d1__U1056":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1062.out","add_all__U1066.in0"], - ["mul_d1__U1064.out","add_all__U1066.in1"], - ["add_all__U1067.in0","add_all__U1066.out"], - ["const_term_U1065.out","add_all__U1067.in1"], - ["self.out","add_all__U1067.out"], - ["mul_d0__U1062.in0","coeff_0_U1061.out"], - ["mul_d1__U1064.in0","coeff_1_U1063.out"], - ["self.d.0","mul_d0__U1062.in1"], - ["self.d.1","mul_d1__U1064.in1"] + ["mul_d0__U1054.out","add_all__U1058.in0"], + ["mul_d1__U1056.out","add_all__U1058.in1"], + ["add_all__U1059.in0","add_all__U1058.out"], + ["const_term_U1057.out","add_all__U1059.in1"], + ["self.out","add_all__U1059.out"], + ["mul_d0__U1054.in0","coeff_0_U1053.out"], + ["mul_d1__U1056.in0","coeff_1_U1055.out"], + ["self.d.0","mul_d0__U1054.in1"], + ["self.d.1","mul_d1__U1056.in1"] ] }, - "aff__U107":{ + "aff__U1066":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U113":{ + "add_all__U1072":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U114":{ + "add_all__U1073":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U108":{ + "coeff_0_U1067":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U110":{ + "coeff_1_U1069":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U112":{ + "const_term_U1071":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U109":{ + "mul_d0__U1068":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U111":{ + "mul_d1__U1070":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U109.out","add_all__U113.in0"], - ["mul_d1__U111.out","add_all__U113.in1"], - ["add_all__U114.in0","add_all__U113.out"], - ["const_term_U112.out","add_all__U114.in1"], - ["self.out","add_all__U114.out"], - ["mul_d0__U109.in0","coeff_0_U108.out"], - ["mul_d1__U111.in0","coeff_1_U110.out"], - ["self.d.0","mul_d0__U109.in1"], - ["self.d.1","mul_d1__U111.in1"] + ["mul_d0__U1068.out","add_all__U1072.in0"], + ["mul_d1__U1070.out","add_all__U1072.in1"], + ["add_all__U1073.in0","add_all__U1072.out"], + ["const_term_U1071.out","add_all__U1073.in1"], + ["self.out","add_all__U1073.out"], + ["mul_d0__U1068.in0","coeff_0_U1067.out"], + ["mul_d1__U1070.in0","coeff_1_U1069.out"], + ["self.d.0","mul_d0__U1068.in1"], + ["self.d.1","mul_d1__U1070.in1"] ] }, - "aff__U1075":{ + "aff__U1080":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1081":{ + "add_all__U1086":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1082":{ + "add_all__U1087":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1076":{ + "coeff_0_U1081":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1078":{ + "coeff_1_U1083":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1080":{ + "const_term_U1085":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1077":{ + "mul_d0__U1082":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1079":{ + "mul_d1__U1084":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1077.out","add_all__U1081.in0"], - ["mul_d1__U1079.out","add_all__U1081.in1"], - ["add_all__U1082.in0","add_all__U1081.out"], - ["const_term_U1080.out","add_all__U1082.in1"], - ["self.out","add_all__U1082.out"], - ["mul_d0__U1077.in0","coeff_0_U1076.out"], - ["mul_d1__U1079.in0","coeff_1_U1078.out"], - ["self.d.0","mul_d0__U1077.in1"], - ["self.d.1","mul_d1__U1079.in1"] + ["mul_d0__U1082.out","add_all__U1086.in0"], + ["mul_d1__U1084.out","add_all__U1086.in1"], + ["add_all__U1087.in0","add_all__U1086.out"], + ["const_term_U1085.out","add_all__U1087.in1"], + ["self.out","add_all__U1087.out"], + ["mul_d0__U1082.in0","coeff_0_U1081.out"], + ["mul_d1__U1084.in0","coeff_1_U1083.out"], + ["self.d.0","mul_d0__U1082.in1"], + ["self.d.1","mul_d1__U1084.in1"] ] }, - "aff__U1090":{ + "aff__U1094":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1096":{ + "add_all__U1100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1097":{ + "add_all__U1101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1091":{ + "coeff_0_U1095":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1093":{ + "coeff_1_U1097":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1095":{ + "const_term_U1099":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1092":{ + "mul_d0__U1096":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1094":{ + "mul_d1__U1098":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1092.out","add_all__U1096.in0"], - ["mul_d1__U1094.out","add_all__U1096.in1"], - ["add_all__U1097.in0","add_all__U1096.out"], - ["const_term_U1095.out","add_all__U1097.in1"], - ["self.out","add_all__U1097.out"], - ["mul_d0__U1092.in0","coeff_0_U1091.out"], - ["mul_d1__U1094.in0","coeff_1_U1093.out"], - ["self.d.0","mul_d0__U1092.in1"], - ["self.d.1","mul_d1__U1094.in1"] + ["mul_d0__U1096.out","add_all__U1100.in0"], + ["mul_d1__U1098.out","add_all__U1100.in1"], + ["add_all__U1101.in0","add_all__U1100.out"], + ["const_term_U1099.out","add_all__U1101.in1"], + ["self.out","add_all__U1101.out"], + ["mul_d0__U1096.in0","coeff_0_U1095.out"], + ["mul_d1__U1098.in0","coeff_1_U1097.out"], + ["self.d.0","mul_d0__U1096.in1"], + ["self.d.1","mul_d1__U1098.in1"] ] }, - "aff__U1105":{ + "aff__U1108":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1111":{ + "add_all__U1114":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1112":{ + "add_all__U1115":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1106":{ + "coeff_0_U1109":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1108":{ + "coeff_1_U1111":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1110":{ + "const_term_U1113":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1107":{ + "mul_d0__U1110":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1109":{ + "mul_d1__U1112":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1107.out","add_all__U1111.in0"], - ["mul_d1__U1109.out","add_all__U1111.in1"], - ["add_all__U1112.in0","add_all__U1111.out"], - ["const_term_U1110.out","add_all__U1112.in1"], - ["self.out","add_all__U1112.out"], - ["mul_d0__U1107.in0","coeff_0_U1106.out"], - ["mul_d1__U1109.in0","coeff_1_U1108.out"], - ["self.d.0","mul_d0__U1107.in1"], - ["self.d.1","mul_d1__U1109.in1"] + ["mul_d0__U1110.out","add_all__U1114.in0"], + ["mul_d1__U1112.out","add_all__U1114.in1"], + ["add_all__U1115.in0","add_all__U1114.out"], + ["const_term_U1113.out","add_all__U1115.in1"], + ["self.out","add_all__U1115.out"], + ["mul_d0__U1110.in0","coeff_0_U1109.out"], + ["mul_d1__U1112.in0","coeff_1_U1111.out"], + ["self.d.0","mul_d0__U1110.in1"], + ["self.d.1","mul_d1__U1112.in1"] ] }, - "aff__U1120":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1126":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1127":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1121":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1123":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1125":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1122":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1124":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1122.out","add_all__U1126.in0"], - ["mul_d1__U1124.out","add_all__U1126.in1"], - ["add_all__U1127.in0","add_all__U1126.out"], - ["const_term_U1125.out","add_all__U1127.in1"], - ["self.out","add_all__U1127.out"], - ["mul_d0__U1122.in0","coeff_0_U1121.out"], - ["mul_d1__U1124.in0","coeff_1_U1123.out"], - ["self.d.0","mul_d0__U1122.in1"], - ["self.d.1","mul_d1__U1124.in1"] - ] - }, - "aff__U1135":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1141":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1142":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1136":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1138":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1140":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1137":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1139":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1137.out","add_all__U1141.in0"], - ["mul_d1__U1139.out","add_all__U1141.in1"], - ["add_all__U1142.in0","add_all__U1141.out"], - ["const_term_U1140.out","add_all__U1142.in1"], - ["self.out","add_all__U1142.out"], - ["mul_d0__U1137.in0","coeff_0_U1136.out"], - ["mul_d1__U1139.in0","coeff_1_U1138.out"], - ["self.d.0","mul_d0__U1137.in1"], - ["self.d.1","mul_d1__U1139.in1"] - ] - }, - "aff__U1150":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1156":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1157":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1151":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1153":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1155":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1152":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1154":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1152.out","add_all__U1156.in0"], - ["mul_d1__U1154.out","add_all__U1156.in1"], - ["add_all__U1157.in0","add_all__U1156.out"], - ["const_term_U1155.out","add_all__U1157.in1"], - ["self.out","add_all__U1157.out"], - ["mul_d0__U1152.in0","coeff_0_U1151.out"], - ["mul_d1__U1154.in0","coeff_1_U1153.out"], - ["self.d.0","mul_d0__U1152.in1"], - ["self.d.1","mul_d1__U1154.in1"] - ] - }, - "aff__U1165":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1171":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1172":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1166":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1168":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1170":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1167":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1169":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1167.out","add_all__U1171.in0"], - ["mul_d1__U1169.out","add_all__U1171.in1"], - ["add_all__U1172.in0","add_all__U1171.out"], - ["const_term_U1170.out","add_all__U1172.in1"], - ["self.out","add_all__U1172.out"], - ["mul_d0__U1167.in0","coeff_0_U1166.out"], - ["mul_d1__U1169.in0","coeff_1_U1168.out"], - ["self.d.0","mul_d0__U1167.in1"], - ["self.d.1","mul_d1__U1169.in1"] - ] - }, - "aff__U1180":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1186":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1187":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1181":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1183":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1185":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1182":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1184":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1182.out","add_all__U1186.in0"], - ["mul_d1__U1184.out","add_all__U1186.in1"], - ["add_all__U1187.in0","add_all__U1186.out"], - ["const_term_U1185.out","add_all__U1187.in1"], - ["self.out","add_all__U1187.out"], - ["mul_d0__U1182.in0","coeff_0_U1181.out"], - ["mul_d1__U1184.in0","coeff_1_U1183.out"], - ["self.d.0","mul_d0__U1182.in1"], - ["self.d.1","mul_d1__U1184.in1"] - ] - }, - "aff__U1195":{ + "aff__U1121":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1207":{ + "add_all__U1133":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1208":{ + "add_all__U1134":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1209":{ + "add_all__U1135":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1210":{ + "add_all__U1136":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1211":{ + "add_all__U1137":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1196":{ + "coeff_0_U1122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1198":{ + "coeff_1_U1124":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006000"]} }, - "coeff_2_U1200":{ + "coeff_2_U1126":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00002000"]} }, - "coeff_3_U1202":{ + "coeff_3_U1128":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_4_U1204":{ + "coeff_4_U1130":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1206":{ + "const_term_U1132":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1197":{ + "mul_d0__U1123":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1199":{ + "mul_d1__U1125":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1201":{ + "mul_d2__U1127":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1203":{ + "mul_d3__U1129":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1205":{ + "mul_d4__U1131":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1197.out","add_all__U1207.in0"], - ["mul_d1__U1199.out","add_all__U1207.in1"], - ["add_all__U1208.in0","add_all__U1207.out"], - ["mul_d2__U1201.out","add_all__U1208.in1"], - ["add_all__U1209.in0","add_all__U1208.out"], - ["mul_d3__U1203.out","add_all__U1209.in1"], - ["add_all__U1210.in0","add_all__U1209.out"], - ["mul_d4__U1205.out","add_all__U1210.in1"], - ["add_all__U1211.in0","add_all__U1210.out"], - ["const_term_U1206.out","add_all__U1211.in1"], - ["self.out","add_all__U1211.out"], - ["mul_d0__U1197.in0","coeff_0_U1196.out"], - ["mul_d1__U1199.in0","coeff_1_U1198.out"], - ["mul_d2__U1201.in0","coeff_2_U1200.out"], - ["mul_d3__U1203.in0","coeff_3_U1202.out"], - ["mul_d4__U1205.in0","coeff_4_U1204.out"], - ["self.d.0","mul_d0__U1197.in1"], - ["self.d.1","mul_d1__U1199.in1"], - ["self.d.2","mul_d2__U1201.in1"], - ["self.d.3","mul_d3__U1203.in1"], - ["self.d.4","mul_d4__U1205.in1"] + ["mul_d0__U1123.out","add_all__U1133.in0"], + ["mul_d1__U1125.out","add_all__U1133.in1"], + ["add_all__U1134.in0","add_all__U1133.out"], + ["mul_d2__U1127.out","add_all__U1134.in1"], + ["add_all__U1135.in0","add_all__U1134.out"], + ["mul_d3__U1129.out","add_all__U1135.in1"], + ["add_all__U1136.in0","add_all__U1135.out"], + ["mul_d4__U1131.out","add_all__U1136.in1"], + ["add_all__U1137.in0","add_all__U1136.out"], + ["const_term_U1132.out","add_all__U1137.in1"], + ["self.out","add_all__U1137.out"], + ["mul_d0__U1123.in0","coeff_0_U1122.out"], + ["mul_d1__U1125.in0","coeff_1_U1124.out"], + ["mul_d2__U1127.in0","coeff_2_U1126.out"], + ["mul_d3__U1129.in0","coeff_3_U1128.out"], + ["mul_d4__U1131.in0","coeff_4_U1130.out"], + ["self.d.0","mul_d0__U1123.in1"], + ["self.d.1","mul_d1__U1125.in1"], + ["self.d.2","mul_d2__U1127.in1"], + ["self.d.3","mul_d3__U1129.in1"], + ["self.d.4","mul_d4__U1131.in1"] ] }, - "aff__U122":{ + "aff__U113":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U132":{ + "add_all__U123":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U133":{ + "add_all__U124":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U134":{ + "add_all__U125":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U135":{ + "add_all__U126":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U123":{ + "coeff_0_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U125":{ + "coeff_1_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "coeff_2_U127":{ + "coeff_2_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_3_U129":{ + "coeff_3_U120":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U131":{ + "const_term_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U124":{ + "mul_d0__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U126":{ + "mul_d1__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U128":{ + "mul_d2__U119":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U130":{ + "mul_d3__U121":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U124.out","add_all__U132.in0"], - ["mul_d1__U126.out","add_all__U132.in1"], - ["add_all__U133.in0","add_all__U132.out"], - ["mul_d2__U128.out","add_all__U133.in1"], - ["add_all__U134.in0","add_all__U133.out"], - ["mul_d3__U130.out","add_all__U134.in1"], - ["add_all__U135.in0","add_all__U134.out"], - ["const_term_U131.out","add_all__U135.in1"], - ["self.out","add_all__U135.out"], - ["mul_d0__U124.in0","coeff_0_U123.out"], - ["mul_d1__U126.in0","coeff_1_U125.out"], - ["mul_d2__U128.in0","coeff_2_U127.out"], - ["mul_d3__U130.in0","coeff_3_U129.out"], - ["self.d.0","mul_d0__U124.in1"], - ["self.d.1","mul_d1__U126.in1"], - ["self.d.2","mul_d2__U128.in1"], - ["self.d.3","mul_d3__U130.in1"] + ["mul_d0__U115.out","add_all__U123.in0"], + ["mul_d1__U117.out","add_all__U123.in1"], + ["add_all__U124.in0","add_all__U123.out"], + ["mul_d2__U119.out","add_all__U124.in1"], + ["add_all__U125.in0","add_all__U124.out"], + ["mul_d3__U121.out","add_all__U125.in1"], + ["add_all__U126.in0","add_all__U125.out"], + ["const_term_U122.out","add_all__U126.in1"], + ["self.out","add_all__U126.out"], + ["mul_d0__U115.in0","coeff_0_U114.out"], + ["mul_d1__U117.in0","coeff_1_U116.out"], + ["mul_d2__U119.in0","coeff_2_U118.out"], + ["mul_d3__U121.in0","coeff_3_U120.out"], + ["self.d.0","mul_d0__U115.in1"], + ["self.d.1","mul_d1__U117.in1"], + ["self.d.2","mul_d2__U119.in1"], + ["self.d.3","mul_d3__U121.in1"] ] }, - "aff__U1225":{ + "aff__U1151":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1237":{ + "add_all__U1163":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1238":{ + "add_all__U1164":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1239":{ + "add_all__U1165":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1240":{ + "add_all__U1166":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1241":{ + "add_all__U1167":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1226":{ + "coeff_0_U1152":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1228":{ + "coeff_1_U1154":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U1230":{ + "coeff_2_U1156":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U1232":{ + "coeff_3_U1158":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U1234":{ + "coeff_4_U1160":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U1236":{ + "const_term_U1162":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1227":{ + "mul_d0__U1153":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1229":{ + "mul_d1__U1155":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1231":{ + "mul_d2__U1157":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1233":{ + "mul_d3__U1159":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1235":{ + "mul_d4__U1161":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1227.out","add_all__U1237.in0"], - ["mul_d1__U1229.out","add_all__U1237.in1"], - ["add_all__U1238.in0","add_all__U1237.out"], - ["mul_d2__U1231.out","add_all__U1238.in1"], - ["add_all__U1239.in0","add_all__U1238.out"], - ["mul_d3__U1233.out","add_all__U1239.in1"], - ["add_all__U1240.in0","add_all__U1239.out"], - ["mul_d4__U1235.out","add_all__U1240.in1"], - ["add_all__U1241.in0","add_all__U1240.out"], - ["const_term_U1236.out","add_all__U1241.in1"], - ["self.out","add_all__U1241.out"], - ["mul_d0__U1227.in0","coeff_0_U1226.out"], - ["mul_d1__U1229.in0","coeff_1_U1228.out"], - ["mul_d2__U1231.in0","coeff_2_U1230.out"], - ["mul_d3__U1233.in0","coeff_3_U1232.out"], - ["mul_d4__U1235.in0","coeff_4_U1234.out"], - ["self.d.0","mul_d0__U1227.in1"], - ["self.d.1","mul_d1__U1229.in1"], - ["self.d.2","mul_d2__U1231.in1"], - ["self.d.3","mul_d3__U1233.in1"], - ["self.d.4","mul_d4__U1235.in1"] + ["mul_d0__U1153.out","add_all__U1163.in0"], + ["mul_d1__U1155.out","add_all__U1163.in1"], + ["add_all__U1164.in0","add_all__U1163.out"], + ["mul_d2__U1157.out","add_all__U1164.in1"], + ["add_all__U1165.in0","add_all__U1164.out"], + ["mul_d3__U1159.out","add_all__U1165.in1"], + ["add_all__U1166.in0","add_all__U1165.out"], + ["mul_d4__U1161.out","add_all__U1166.in1"], + ["add_all__U1167.in0","add_all__U1166.out"], + ["const_term_U1162.out","add_all__U1167.in1"], + ["self.out","add_all__U1167.out"], + ["mul_d0__U1153.in0","coeff_0_U1152.out"], + ["mul_d1__U1155.in0","coeff_1_U1154.out"], + ["mul_d2__U1157.in0","coeff_2_U1156.out"], + ["mul_d3__U1159.in0","coeff_3_U1158.out"], + ["mul_d4__U1161.in0","coeff_4_U1160.out"], + ["self.d.0","mul_d0__U1153.in1"], + ["self.d.1","mul_d1__U1155.in1"], + ["self.d.2","mul_d2__U1157.in1"], + ["self.d.3","mul_d3__U1159.in1"], + ["self.d.4","mul_d4__U1161.in1"] ] }, - "aff__U1244":{ + "aff__U1170":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1264":{ + "add_all__U1190":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1265":{ + "add_all__U1191":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1266":{ + "add_all__U1192":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1267":{ + "add_all__U1193":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1268":{ + "add_all__U1194":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1269":{ + "add_all__U1195":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1270":{ + "add_all__U1196":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1271":{ + "add_all__U1197":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1272":{ + "add_all__U1198":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1245":{ + "coeff_0_U1171":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1247":{ + "coeff_1_U1173":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U1249":{ + "coeff_2_U1175":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004800"]} }, - "coeff_3_U1251":{ + "coeff_3_U1177":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001800"]} }, - "coeff_4_U1253":{ + "coeff_4_U1179":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000800"]} }, - "coeff_5_U1255":{ + "coeff_5_U1181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000200"]} }, - "coeff_6_U1257":{ + "coeff_6_U1183":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_7_U1259":{ + "coeff_7_U1185":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_8_U1261":{ + "coeff_8_U1187":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1263":{ + "const_term_U1189":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00011fff"]} }, - "mul_d0__U1246":{ + "mul_d0__U1172":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1248":{ + "mul_d1__U1174":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1250":{ + "mul_d2__U1176":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1252":{ + "mul_d3__U1178":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1254":{ + "mul_d4__U1180":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1256":{ + "mul_d5__U1182":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U1258":{ + "mul_d6__U1184":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U1260":{ + "mul_d7__U1186":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U1262":{ + "mul_d8__U1188":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1246.out","add_all__U1264.in0"], - ["mul_d1__U1248.out","add_all__U1264.in1"], - ["add_all__U1265.in0","add_all__U1264.out"], - ["mul_d2__U1250.out","add_all__U1265.in1"], - ["add_all__U1266.in0","add_all__U1265.out"], - ["mul_d3__U1252.out","add_all__U1266.in1"], - ["add_all__U1267.in0","add_all__U1266.out"], - ["mul_d4__U1254.out","add_all__U1267.in1"], - ["add_all__U1268.in0","add_all__U1267.out"], - ["mul_d5__U1256.out","add_all__U1268.in1"], - ["add_all__U1269.in0","add_all__U1268.out"], - ["mul_d6__U1258.out","add_all__U1269.in1"], - ["add_all__U1270.in0","add_all__U1269.out"], - ["mul_d7__U1260.out","add_all__U1270.in1"], - ["add_all__U1271.in0","add_all__U1270.out"], - ["mul_d8__U1262.out","add_all__U1271.in1"], - ["add_all__U1272.in0","add_all__U1271.out"], - ["const_term_U1263.out","add_all__U1272.in1"], - ["self.out","add_all__U1272.out"], - ["mul_d0__U1246.in0","coeff_0_U1245.out"], - ["mul_d1__U1248.in0","coeff_1_U1247.out"], - ["mul_d2__U1250.in0","coeff_2_U1249.out"], - ["mul_d3__U1252.in0","coeff_3_U1251.out"], - ["mul_d4__U1254.in0","coeff_4_U1253.out"], - ["mul_d5__U1256.in0","coeff_5_U1255.out"], - ["mul_d6__U1258.in0","coeff_6_U1257.out"], - ["mul_d7__U1260.in0","coeff_7_U1259.out"], - ["mul_d8__U1262.in0","coeff_8_U1261.out"], - ["self.d.0","mul_d0__U1246.in1"], - ["self.d.1","mul_d1__U1248.in1"], - ["self.d.2","mul_d2__U1250.in1"], - ["self.d.3","mul_d3__U1252.in1"], - ["self.d.4","mul_d4__U1254.in1"], - ["self.d.5","mul_d5__U1256.in1"], - ["self.d.6","mul_d6__U1258.in1"], - ["self.d.7","mul_d7__U1260.in1"], - ["self.d.8","mul_d8__U1262.in1"] + ["mul_d0__U1172.out","add_all__U1190.in0"], + ["mul_d1__U1174.out","add_all__U1190.in1"], + ["add_all__U1191.in0","add_all__U1190.out"], + ["mul_d2__U1176.out","add_all__U1191.in1"], + ["add_all__U1192.in0","add_all__U1191.out"], + ["mul_d3__U1178.out","add_all__U1192.in1"], + ["add_all__U1193.in0","add_all__U1192.out"], + ["mul_d4__U1180.out","add_all__U1193.in1"], + ["add_all__U1194.in0","add_all__U1193.out"], + ["mul_d5__U1182.out","add_all__U1194.in1"], + ["add_all__U1195.in0","add_all__U1194.out"], + ["mul_d6__U1184.out","add_all__U1195.in1"], + ["add_all__U1196.in0","add_all__U1195.out"], + ["mul_d7__U1186.out","add_all__U1196.in1"], + ["add_all__U1197.in0","add_all__U1196.out"], + ["mul_d8__U1188.out","add_all__U1197.in1"], + ["add_all__U1198.in0","add_all__U1197.out"], + ["const_term_U1189.out","add_all__U1198.in1"], + ["self.out","add_all__U1198.out"], + ["mul_d0__U1172.in0","coeff_0_U1171.out"], + ["mul_d1__U1174.in0","coeff_1_U1173.out"], + ["mul_d2__U1176.in0","coeff_2_U1175.out"], + ["mul_d3__U1178.in0","coeff_3_U1177.out"], + ["mul_d4__U1180.in0","coeff_4_U1179.out"], + ["mul_d5__U1182.in0","coeff_5_U1181.out"], + ["mul_d6__U1184.in0","coeff_6_U1183.out"], + ["mul_d7__U1186.in0","coeff_7_U1185.out"], + ["mul_d8__U1188.in0","coeff_8_U1187.out"], + ["self.d.0","mul_d0__U1172.in1"], + ["self.d.1","mul_d1__U1174.in1"], + ["self.d.2","mul_d2__U1176.in1"], + ["self.d.3","mul_d3__U1178.in1"], + ["self.d.4","mul_d4__U1180.in1"], + ["self.d.5","mul_d5__U1182.in1"], + ["self.d.6","mul_d6__U1184.in1"], + ["self.d.7","mul_d7__U1186.in1"], + ["self.d.8","mul_d8__U1188.in1"] ] }, - "aff__U1312":{ + "aff__U1238":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1332":{ + "add_all__U1258":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1333":{ + "add_all__U1259":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1334":{ + "add_all__U1260":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1335":{ + "add_all__U1261":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1336":{ + "add_all__U1262":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1337":{ + "add_all__U1263":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1338":{ + "add_all__U1264":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1339":{ + "add_all__U1265":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1340":{ + "add_all__U1266":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1313":{ + "coeff_0_U1239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1315":{ + "coeff_1_U1241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U1317":{ + "coeff_2_U1243":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_3_U1319":{ + "coeff_3_U1245":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U1321":{ + "coeff_4_U1247":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_5_U1323":{ + "coeff_5_U1249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_6_U1325":{ + "coeff_6_U1251":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_7_U1327":{ + "coeff_7_U1253":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001200"]} }, - "coeff_8_U1329":{ + "coeff_8_U1255":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "const_term_U1331":{ + "const_term_U1257":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1314":{ + "mul_d0__U1240":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1316":{ + "mul_d1__U1242":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1318":{ + "mul_d2__U1244":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1320":{ + "mul_d3__U1246":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1322":{ + "mul_d4__U1248":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1324":{ + "mul_d5__U1250":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U1326":{ + "mul_d6__U1252":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U1328":{ + "mul_d7__U1254":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U1330":{ + "mul_d8__U1256":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1314.out","add_all__U1332.in0"], - ["mul_d1__U1316.out","add_all__U1332.in1"], - ["add_all__U1333.in0","add_all__U1332.out"], - ["mul_d2__U1318.out","add_all__U1333.in1"], - ["add_all__U1334.in0","add_all__U1333.out"], - ["mul_d3__U1320.out","add_all__U1334.in1"], - ["add_all__U1335.in0","add_all__U1334.out"], - ["mul_d4__U1322.out","add_all__U1335.in1"], - ["add_all__U1336.in0","add_all__U1335.out"], - ["mul_d5__U1324.out","add_all__U1336.in1"], - ["add_all__U1337.in0","add_all__U1336.out"], - ["mul_d6__U1326.out","add_all__U1337.in1"], - ["add_all__U1338.in0","add_all__U1337.out"], - ["mul_d7__U1328.out","add_all__U1338.in1"], - ["add_all__U1339.in0","add_all__U1338.out"], - ["mul_d8__U1330.out","add_all__U1339.in1"], - ["add_all__U1340.in0","add_all__U1339.out"], - ["const_term_U1331.out","add_all__U1340.in1"], - ["self.out","add_all__U1340.out"], - ["mul_d0__U1314.in0","coeff_0_U1313.out"], - ["mul_d1__U1316.in0","coeff_1_U1315.out"], - ["mul_d2__U1318.in0","coeff_2_U1317.out"], - ["mul_d3__U1320.in0","coeff_3_U1319.out"], - ["mul_d4__U1322.in0","coeff_4_U1321.out"], - ["mul_d5__U1324.in0","coeff_5_U1323.out"], - ["mul_d6__U1326.in0","coeff_6_U1325.out"], - ["mul_d7__U1328.in0","coeff_7_U1327.out"], - ["mul_d8__U1330.in0","coeff_8_U1329.out"], - ["self.d.0","mul_d0__U1314.in1"], - ["self.d.1","mul_d1__U1316.in1"], - ["self.d.2","mul_d2__U1318.in1"], - ["self.d.3","mul_d3__U1320.in1"], - ["self.d.4","mul_d4__U1322.in1"], - ["self.d.5","mul_d5__U1324.in1"], - ["self.d.6","mul_d6__U1326.in1"], - ["self.d.7","mul_d7__U1328.in1"], - ["self.d.8","mul_d8__U1330.in1"] + ["mul_d0__U1240.out","add_all__U1258.in0"], + ["mul_d1__U1242.out","add_all__U1258.in1"], + ["add_all__U1259.in0","add_all__U1258.out"], + ["mul_d2__U1244.out","add_all__U1259.in1"], + ["add_all__U1260.in0","add_all__U1259.out"], + ["mul_d3__U1246.out","add_all__U1260.in1"], + ["add_all__U1261.in0","add_all__U1260.out"], + ["mul_d4__U1248.out","add_all__U1261.in1"], + ["add_all__U1262.in0","add_all__U1261.out"], + ["mul_d5__U1250.out","add_all__U1262.in1"], + ["add_all__U1263.in0","add_all__U1262.out"], + ["mul_d6__U1252.out","add_all__U1263.in1"], + ["add_all__U1264.in0","add_all__U1263.out"], + ["mul_d7__U1254.out","add_all__U1264.in1"], + ["add_all__U1265.in0","add_all__U1264.out"], + ["mul_d8__U1256.out","add_all__U1265.in1"], + ["add_all__U1266.in0","add_all__U1265.out"], + ["const_term_U1257.out","add_all__U1266.in1"], + ["self.out","add_all__U1266.out"], + ["mul_d0__U1240.in0","coeff_0_U1239.out"], + ["mul_d1__U1242.in0","coeff_1_U1241.out"], + ["mul_d2__U1244.in0","coeff_2_U1243.out"], + ["mul_d3__U1246.in0","coeff_3_U1245.out"], + ["mul_d4__U1248.in0","coeff_4_U1247.out"], + ["mul_d5__U1250.in0","coeff_5_U1249.out"], + ["mul_d6__U1252.in0","coeff_6_U1251.out"], + ["mul_d7__U1254.in0","coeff_7_U1253.out"], + ["mul_d8__U1256.in0","coeff_8_U1255.out"], + ["self.d.0","mul_d0__U1240.in1"], + ["self.d.1","mul_d1__U1242.in1"], + ["self.d.2","mul_d2__U1244.in1"], + ["self.d.3","mul_d3__U1246.in1"], + ["self.d.4","mul_d4__U1248.in1"], + ["self.d.5","mul_d5__U1250.in1"], + ["self.d.6","mul_d6__U1252.in1"], + ["self.d.7","mul_d7__U1254.in1"], + ["self.d.8","mul_d8__U1256.in1"] + ] + }, + "aff__U1271":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U1277":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U1278":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U1272":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U1274":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U1276":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U1273":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U1275":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U1273.out","add_all__U1277.in0"], + ["mul_d1__U1275.out","add_all__U1277.in1"], + ["add_all__U1278.in0","add_all__U1277.out"], + ["const_term_U1276.out","add_all__U1278.in1"], + ["self.out","add_all__U1278.out"], + ["mul_d0__U1273.in0","coeff_0_U1272.out"], + ["mul_d1__U1275.in0","coeff_1_U1274.out"], + ["self.d.0","mul_d0__U1273.in1"], + ["self.d.1","mul_d1__U1275.in1"] + ] + }, + "aff__U1285":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U1291":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U1292":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U1286":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U1288":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U1290":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U1287":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U1289":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U1287.out","add_all__U1291.in0"], + ["mul_d1__U1289.out","add_all__U1291.in1"], + ["add_all__U1292.in0","add_all__U1291.out"], + ["const_term_U1290.out","add_all__U1292.in1"], + ["self.out","add_all__U1292.out"], + ["mul_d0__U1287.in0","coeff_0_U1286.out"], + ["mul_d1__U1289.in0","coeff_1_U1288.out"], + ["self.d.0","mul_d0__U1287.in1"], + ["self.d.1","mul_d1__U1289.in1"] + ] + }, + "aff__U1299":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U1305":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U1306":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U1300":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U1302":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U1304":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U1301":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U1303":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U1301.out","add_all__U1305.in0"], + ["mul_d1__U1303.out","add_all__U1305.in1"], + ["add_all__U1306.in0","add_all__U1305.out"], + ["const_term_U1304.out","add_all__U1306.in1"], + ["self.out","add_all__U1306.out"], + ["mul_d0__U1301.in0","coeff_0_U1300.out"], + ["mul_d1__U1303.in0","coeff_1_U1302.out"], + ["self.d.0","mul_d0__U1301.in1"], + ["self.d.1","mul_d1__U1303.in1"] ] }, - "aff__U1345":{ + "aff__U1313":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1351":{ + "add_all__U1319":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1352":{ + "add_all__U1320":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1346":{ + "coeff_0_U1314":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1348":{ + "coeff_1_U1316":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1350":{ + "const_term_U1318":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1347":{ + "mul_d0__U1315":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1349":{ + "mul_d1__U1317":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1347.out","add_all__U1351.in0"], - ["mul_d1__U1349.out","add_all__U1351.in1"], - ["add_all__U1352.in0","add_all__U1351.out"], - ["const_term_U1350.out","add_all__U1352.in1"], - ["self.out","add_all__U1352.out"], - ["mul_d0__U1347.in0","coeff_0_U1346.out"], - ["mul_d1__U1349.in0","coeff_1_U1348.out"], - ["self.d.0","mul_d0__U1347.in1"], - ["self.d.1","mul_d1__U1349.in1"] + ["mul_d0__U1315.out","add_all__U1319.in0"], + ["mul_d1__U1317.out","add_all__U1319.in1"], + ["add_all__U1320.in0","add_all__U1319.out"], + ["const_term_U1318.out","add_all__U1320.in1"], + ["self.out","add_all__U1320.out"], + ["mul_d0__U1315.in0","coeff_0_U1314.out"], + ["mul_d1__U1317.in0","coeff_1_U1316.out"], + ["self.d.0","mul_d0__U1315.in1"], + ["self.d.1","mul_d1__U1317.in1"] ] }, - "aff__U1360":{ + "aff__U1327":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1366":{ + "add_all__U1333":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1367":{ + "add_all__U1334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1361":{ + "coeff_0_U1328":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1363":{ + "coeff_1_U1330":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1365":{ + "const_term_U1332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1362":{ + "mul_d0__U1329":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1364":{ + "mul_d1__U1331":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1362.out","add_all__U1366.in0"], - ["mul_d1__U1364.out","add_all__U1366.in1"], - ["add_all__U1367.in0","add_all__U1366.out"], - ["const_term_U1365.out","add_all__U1367.in1"], - ["self.out","add_all__U1367.out"], - ["mul_d0__U1362.in0","coeff_0_U1361.out"], - ["mul_d1__U1364.in0","coeff_1_U1363.out"], - ["self.d.0","mul_d0__U1362.in1"], - ["self.d.1","mul_d1__U1364.in1"] + ["mul_d0__U1329.out","add_all__U1333.in0"], + ["mul_d1__U1331.out","add_all__U1333.in1"], + ["add_all__U1334.in0","add_all__U1333.out"], + ["const_term_U1332.out","add_all__U1334.in1"], + ["self.out","add_all__U1334.out"], + ["mul_d0__U1329.in0","coeff_0_U1328.out"], + ["mul_d1__U1331.in0","coeff_1_U1330.out"], + ["self.d.0","mul_d0__U1329.in1"], + ["self.d.1","mul_d1__U1331.in1"] ] }, - "aff__U1375":{ + "aff__U1341":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1381":{ + "add_all__U1347":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1382":{ + "add_all__U1348":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1376":{ + "coeff_0_U1342":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1378":{ + "coeff_1_U1344":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1380":{ + "const_term_U1346":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1377":{ + "mul_d0__U1343":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1379":{ + "mul_d1__U1345":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1377.out","add_all__U1381.in0"], - ["mul_d1__U1379.out","add_all__U1381.in1"], - ["add_all__U1382.in0","add_all__U1381.out"], - ["const_term_U1380.out","add_all__U1382.in1"], - ["self.out","add_all__U1382.out"], - ["mul_d0__U1377.in0","coeff_0_U1376.out"], - ["mul_d1__U1379.in0","coeff_1_U1378.out"], - ["self.d.0","mul_d0__U1377.in1"], - ["self.d.1","mul_d1__U1379.in1"] + ["mul_d0__U1343.out","add_all__U1347.in0"], + ["mul_d1__U1345.out","add_all__U1347.in1"], + ["add_all__U1348.in0","add_all__U1347.out"], + ["const_term_U1346.out","add_all__U1348.in1"], + ["self.out","add_all__U1348.out"], + ["mul_d0__U1343.in0","coeff_0_U1342.out"], + ["mul_d1__U1345.in0","coeff_1_U1344.out"], + ["self.d.0","mul_d0__U1343.in1"], + ["self.d.1","mul_d1__U1345.in1"] ] }, - "aff__U1390":{ + "aff__U1355":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1396":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1397":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1391":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1393":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1395":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1392":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1394":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1392.out","add_all__U1396.in0"], - ["mul_d1__U1394.out","add_all__U1396.in1"], - ["add_all__U1397.in0","add_all__U1396.out"], - ["const_term_U1395.out","add_all__U1397.in1"], - ["self.out","add_all__U1397.out"], - ["mul_d0__U1392.in0","coeff_0_U1391.out"], - ["mul_d1__U1394.in0","coeff_1_U1393.out"], - ["self.d.0","mul_d0__U1392.in1"], - ["self.d.1","mul_d1__U1394.in1"] - ] - }, - "aff__U1405":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1411":{ + "add_all__U1361":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1412":{ + "add_all__U1362":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1406":{ + "coeff_0_U1356":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1408":{ + "coeff_1_U1358":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1410":{ + "const_term_U1360":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1407":{ + "mul_d0__U1357":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1409":{ + "mul_d1__U1359":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1407.out","add_all__U1411.in0"], - ["mul_d1__U1409.out","add_all__U1411.in1"], - ["add_all__U1412.in0","add_all__U1411.out"], - ["const_term_U1410.out","add_all__U1412.in1"], - ["self.out","add_all__U1412.out"], - ["mul_d0__U1407.in0","coeff_0_U1406.out"], - ["mul_d1__U1409.in0","coeff_1_U1408.out"], - ["self.d.0","mul_d0__U1407.in1"], - ["self.d.1","mul_d1__U1409.in1"] + ["mul_d0__U1357.out","add_all__U1361.in0"], + ["mul_d1__U1359.out","add_all__U1361.in1"], + ["add_all__U1362.in0","add_all__U1361.out"], + ["const_term_U1360.out","add_all__U1362.in1"], + ["self.out","add_all__U1362.out"], + ["mul_d0__U1357.in0","coeff_0_U1356.out"], + ["mul_d1__U1359.in0","coeff_1_U1358.out"], + ["self.d.0","mul_d0__U1357.in1"], + ["self.d.1","mul_d1__U1359.in1"] ] }, - "aff__U1420":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1426":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1427":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1421":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1423":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1425":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1422":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1424":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1422.out","add_all__U1426.in0"], - ["mul_d1__U1424.out","add_all__U1426.in1"], - ["add_all__U1427.in0","add_all__U1426.out"], - ["const_term_U1425.out","add_all__U1427.in1"], - ["self.out","add_all__U1427.out"], - ["mul_d0__U1422.in0","coeff_0_U1421.out"], - ["mul_d1__U1424.in0","coeff_1_U1423.out"], - ["self.d.0","mul_d0__U1422.in1"], - ["self.d.1","mul_d1__U1424.in1"] - ] - }, - "aff__U1435":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U1441":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U1442":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U1436":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U1438":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U1440":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U1437":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U1439":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U1437.out","add_all__U1441.in0"], - ["mul_d1__U1439.out","add_all__U1441.in1"], - ["add_all__U1442.in0","add_all__U1441.out"], - ["const_term_U1440.out","add_all__U1442.in1"], - ["self.out","add_all__U1442.out"], - ["mul_d0__U1437.in0","coeff_0_U1436.out"], - ["mul_d1__U1439.in0","coeff_1_U1438.out"], - ["self.d.0","mul_d0__U1437.in1"], - ["self.d.1","mul_d1__U1439.in1"] - ] - }, - "aff__U145":{ + "aff__U136":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U155":{ + "add_all__U146":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U156":{ + "add_all__U147":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U157":{ + "add_all__U148":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U158":{ + "add_all__U149":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U146":{ + "coeff_0_U137":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U148":{ + "coeff_1_U139":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U150":{ + "coeff_2_U141":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_3_U152":{ + "coeff_3_U143":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000051"]} }, - "const_term_U154":{ + "const_term_U145":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U147":{ + "mul_d0__U138":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U149":{ + "mul_d1__U140":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U151":{ + "mul_d2__U142":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U153":{ + "mul_d3__U144":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U147.out","add_all__U155.in0"], - ["mul_d1__U149.out","add_all__U155.in1"], - ["add_all__U156.in0","add_all__U155.out"], - ["mul_d2__U151.out","add_all__U156.in1"], - ["add_all__U157.in0","add_all__U156.out"], - ["mul_d3__U153.out","add_all__U157.in1"], - ["add_all__U158.in0","add_all__U157.out"], - ["const_term_U154.out","add_all__U158.in1"], - ["self.out","add_all__U158.out"], - ["mul_d0__U147.in0","coeff_0_U146.out"], - ["mul_d1__U149.in0","coeff_1_U148.out"], - ["mul_d2__U151.in0","coeff_2_U150.out"], - ["mul_d3__U153.in0","coeff_3_U152.out"], - ["self.d.0","mul_d0__U147.in1"], - ["self.d.1","mul_d1__U149.in1"], - ["self.d.2","mul_d2__U151.in1"], - ["self.d.3","mul_d3__U153.in1"] + ["mul_d0__U138.out","add_all__U146.in0"], + ["mul_d1__U140.out","add_all__U146.in1"], + ["add_all__U147.in0","add_all__U146.out"], + ["mul_d2__U142.out","add_all__U147.in1"], + ["add_all__U148.in0","add_all__U147.out"], + ["mul_d3__U144.out","add_all__U148.in1"], + ["add_all__U149.in0","add_all__U148.out"], + ["const_term_U145.out","add_all__U149.in1"], + ["self.out","add_all__U149.out"], + ["mul_d0__U138.in0","coeff_0_U137.out"], + ["mul_d1__U140.in0","coeff_1_U139.out"], + ["mul_d2__U142.in0","coeff_2_U141.out"], + ["mul_d3__U144.in0","coeff_3_U143.out"], + ["self.d.0","mul_d0__U138.in1"], + ["self.d.1","mul_d1__U140.in1"], + ["self.d.2","mul_d2__U142.in1"], + ["self.d.3","mul_d3__U144.in1"] ] }, - "aff__U1450":{ + "aff__U1369":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1456":{ + "add_all__U1375":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1457":{ + "add_all__U1376":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1451":{ + "coeff_0_U1370":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1453":{ + "coeff_1_U1372":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U1455":{ + "const_term_U1374":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U1452":{ + "mul_d0__U1371":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1454":{ + "mul_d1__U1373":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1452.out","add_all__U1456.in0"], - ["mul_d1__U1454.out","add_all__U1456.in1"], - ["add_all__U1457.in0","add_all__U1456.out"], - ["const_term_U1455.out","add_all__U1457.in1"], - ["self.out","add_all__U1457.out"], - ["mul_d0__U1452.in0","coeff_0_U1451.out"], - ["mul_d1__U1454.in0","coeff_1_U1453.out"], - ["self.d.0","mul_d0__U1452.in1"], - ["self.d.1","mul_d1__U1454.in1"] + ["mul_d0__U1371.out","add_all__U1375.in0"], + ["mul_d1__U1373.out","add_all__U1375.in1"], + ["add_all__U1376.in0","add_all__U1375.out"], + ["const_term_U1374.out","add_all__U1376.in1"], + ["self.out","add_all__U1376.out"], + ["mul_d0__U1371.in0","coeff_0_U1370.out"], + ["mul_d1__U1373.in0","coeff_1_U1372.out"], + ["self.d.0","mul_d0__U1371.in1"], + ["self.d.1","mul_d1__U1373.in1"] ] }, - "aff__U1465":{ + "aff__U1382":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1479":{ + "add_all__U1396":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1480":{ + "add_all__U1397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1481":{ + "add_all__U1398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1482":{ + "add_all__U1399":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1483":{ + "add_all__U1400":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1484":{ + "add_all__U1401":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1466":{ + "coeff_0_U1383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1468":{ + "coeff_1_U1385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U1470":{ + "coeff_2_U1387":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000001c0"]} }, - "coeff_3_U1472":{ + "coeff_3_U1389":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_4_U1474":{ + "coeff_4_U1391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_5_U1476":{ + "coeff_5_U1393":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1478":{ + "const_term_U1395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0001e720"]} }, - "mul_d0__U1467":{ + "mul_d0__U1384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1469":{ + "mul_d1__U1386":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1471":{ + "mul_d2__U1388":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1473":{ + "mul_d3__U1390":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1475":{ + "mul_d4__U1392":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1477":{ + "mul_d5__U1394":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1467.out","add_all__U1479.in0"], - ["mul_d1__U1469.out","add_all__U1479.in1"], - ["add_all__U1480.in0","add_all__U1479.out"], - ["mul_d2__U1471.out","add_all__U1480.in1"], - ["add_all__U1481.in0","add_all__U1480.out"], - ["mul_d3__U1473.out","add_all__U1481.in1"], - ["add_all__U1482.in0","add_all__U1481.out"], - ["mul_d4__U1475.out","add_all__U1482.in1"], - ["add_all__U1483.in0","add_all__U1482.out"], - ["mul_d5__U1477.out","add_all__U1483.in1"], - ["add_all__U1484.in0","add_all__U1483.out"], - ["const_term_U1478.out","add_all__U1484.in1"], - ["self.out","add_all__U1484.out"], - ["mul_d0__U1467.in0","coeff_0_U1466.out"], - ["mul_d1__U1469.in0","coeff_1_U1468.out"], - ["mul_d2__U1471.in0","coeff_2_U1470.out"], - ["mul_d3__U1473.in0","coeff_3_U1472.out"], - ["mul_d4__U1475.in0","coeff_4_U1474.out"], - ["mul_d5__U1477.in0","coeff_5_U1476.out"], - ["self.d.0","mul_d0__U1467.in1"], - ["self.d.1","mul_d1__U1469.in1"], - ["self.d.2","mul_d2__U1471.in1"], - ["self.d.3","mul_d3__U1473.in1"], - ["self.d.4","mul_d4__U1475.in1"], - ["self.d.5","mul_d5__U1477.in1"] + ["mul_d0__U1384.out","add_all__U1396.in0"], + ["mul_d1__U1386.out","add_all__U1396.in1"], + ["add_all__U1397.in0","add_all__U1396.out"], + ["mul_d2__U1388.out","add_all__U1397.in1"], + ["add_all__U1398.in0","add_all__U1397.out"], + ["mul_d3__U1390.out","add_all__U1398.in1"], + ["add_all__U1399.in0","add_all__U1398.out"], + ["mul_d4__U1392.out","add_all__U1399.in1"], + ["add_all__U1400.in0","add_all__U1399.out"], + ["mul_d5__U1394.out","add_all__U1400.in1"], + ["add_all__U1401.in0","add_all__U1400.out"], + ["const_term_U1395.out","add_all__U1401.in1"], + ["self.out","add_all__U1401.out"], + ["mul_d0__U1384.in0","coeff_0_U1383.out"], + ["mul_d1__U1386.in0","coeff_1_U1385.out"], + ["mul_d2__U1388.in0","coeff_2_U1387.out"], + ["mul_d3__U1390.in0","coeff_3_U1389.out"], + ["mul_d4__U1392.in0","coeff_4_U1391.out"], + ["mul_d5__U1394.in0","coeff_5_U1393.out"], + ["self.d.0","mul_d0__U1384.in1"], + ["self.d.1","mul_d1__U1386.in1"], + ["self.d.2","mul_d2__U1388.in1"], + ["self.d.3","mul_d3__U1390.in1"], + ["self.d.4","mul_d4__U1392.in1"], + ["self.d.5","mul_d5__U1394.in1"] ] }, - "aff__U1503":{ + "aff__U1420":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",6,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1517":{ + "add_all__U1434":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1518":{ + "add_all__U1435":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1519":{ + "add_all__U1436":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1520":{ + "add_all__U1437":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1521":{ + "add_all__U1438":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1522":{ + "add_all__U1439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1504":{ + "coeff_0_U1421":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1506":{ + "coeff_1_U1423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c40"]} }, - "coeff_2_U1508":{ + "coeff_2_U1425":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_3_U1510":{ + "coeff_3_U1427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_4_U1512":{ + "coeff_4_U1429":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000188"]} }, - "coeff_5_U1514":{ + "coeff_5_U1431":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U1516":{ + "const_term_U1433":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1505":{ + "mul_d0__U1422":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1507":{ + "mul_d1__U1424":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1509":{ + "mul_d2__U1426":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1511":{ + "mul_d3__U1428":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U1513":{ + "mul_d4__U1430":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U1515":{ + "mul_d5__U1432":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1505.out","add_all__U1517.in0"], - ["mul_d1__U1507.out","add_all__U1517.in1"], - ["add_all__U1518.in0","add_all__U1517.out"], - ["mul_d2__U1509.out","add_all__U1518.in1"], - ["add_all__U1519.in0","add_all__U1518.out"], - ["mul_d3__U1511.out","add_all__U1519.in1"], - ["add_all__U1520.in0","add_all__U1519.out"], - ["mul_d4__U1513.out","add_all__U1520.in1"], - ["add_all__U1521.in0","add_all__U1520.out"], - ["mul_d5__U1515.out","add_all__U1521.in1"], - ["add_all__U1522.in0","add_all__U1521.out"], - ["const_term_U1516.out","add_all__U1522.in1"], - ["self.out","add_all__U1522.out"], - ["mul_d0__U1505.in0","coeff_0_U1504.out"], - ["mul_d1__U1507.in0","coeff_1_U1506.out"], - ["mul_d2__U1509.in0","coeff_2_U1508.out"], - ["mul_d3__U1511.in0","coeff_3_U1510.out"], - ["mul_d4__U1513.in0","coeff_4_U1512.out"], - ["mul_d5__U1515.in0","coeff_5_U1514.out"], - ["self.d.0","mul_d0__U1505.in1"], - ["self.d.1","mul_d1__U1507.in1"], - ["self.d.2","mul_d2__U1509.in1"], - ["self.d.3","mul_d3__U1511.in1"], - ["self.d.4","mul_d4__U1513.in1"], - ["self.d.5","mul_d5__U1515.in1"] + ["mul_d0__U1422.out","add_all__U1434.in0"], + ["mul_d1__U1424.out","add_all__U1434.in1"], + ["add_all__U1435.in0","add_all__U1434.out"], + ["mul_d2__U1426.out","add_all__U1435.in1"], + ["add_all__U1436.in0","add_all__U1435.out"], + ["mul_d3__U1428.out","add_all__U1436.in1"], + ["add_all__U1437.in0","add_all__U1436.out"], + ["mul_d4__U1430.out","add_all__U1437.in1"], + ["add_all__U1438.in0","add_all__U1437.out"], + ["mul_d5__U1432.out","add_all__U1438.in1"], + ["add_all__U1439.in0","add_all__U1438.out"], + ["const_term_U1433.out","add_all__U1439.in1"], + ["self.out","add_all__U1439.out"], + ["mul_d0__U1422.in0","coeff_0_U1421.out"], + ["mul_d1__U1424.in0","coeff_1_U1423.out"], + ["mul_d2__U1426.in0","coeff_2_U1425.out"], + ["mul_d3__U1428.in0","coeff_3_U1427.out"], + ["mul_d4__U1430.in0","coeff_4_U1429.out"], + ["mul_d5__U1432.in0","coeff_5_U1431.out"], + ["self.d.0","mul_d0__U1422.in1"], + ["self.d.1","mul_d1__U1424.in1"], + ["self.d.2","mul_d2__U1426.in1"], + ["self.d.3","mul_d3__U1428.in1"], + ["self.d.4","mul_d4__U1430.in1"], + ["self.d.5","mul_d5__U1432.in1"] ] }, - "aff__U1525":{ + "aff__U1442":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1535":{ + "add_all__U1452":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1536":{ + "add_all__U1453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1537":{ + "add_all__U1454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1538":{ + "add_all__U1455":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1526":{ + "coeff_0_U1443":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1528":{ + "coeff_1_U1445":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U1530":{ + "coeff_2_U1447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_3_U1532":{ + "coeff_3_U1449":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1534":{ + "const_term_U1451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002835f"]} }, - "mul_d0__U1527":{ + "mul_d0__U1444":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1529":{ + "mul_d1__U1446":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1531":{ + "mul_d2__U1448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1533":{ + "mul_d3__U1450":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1527.out","add_all__U1535.in0"], - ["mul_d1__U1529.out","add_all__U1535.in1"], - ["add_all__U1536.in0","add_all__U1535.out"], - ["mul_d2__U1531.out","add_all__U1536.in1"], - ["add_all__U1537.in0","add_all__U1536.out"], - ["mul_d3__U1533.out","add_all__U1537.in1"], - ["add_all__U1538.in0","add_all__U1537.out"], - ["const_term_U1534.out","add_all__U1538.in1"], - ["self.out","add_all__U1538.out"], - ["mul_d0__U1527.in0","coeff_0_U1526.out"], - ["mul_d1__U1529.in0","coeff_1_U1528.out"], - ["mul_d2__U1531.in0","coeff_2_U1530.out"], - ["mul_d3__U1533.in0","coeff_3_U1532.out"], - ["self.d.0","mul_d0__U1527.in1"], - ["self.d.1","mul_d1__U1529.in1"], - ["self.d.2","mul_d2__U1531.in1"], - ["self.d.3","mul_d3__U1533.in1"] + ["mul_d0__U1444.out","add_all__U1452.in0"], + ["mul_d1__U1446.out","add_all__U1452.in1"], + ["add_all__U1453.in0","add_all__U1452.out"], + ["mul_d2__U1448.out","add_all__U1453.in1"], + ["add_all__U1454.in0","add_all__U1453.out"], + ["mul_d3__U1450.out","add_all__U1454.in1"], + ["add_all__U1455.in0","add_all__U1454.out"], + ["const_term_U1451.out","add_all__U1455.in1"], + ["self.out","add_all__U1455.out"], + ["mul_d0__U1444.in0","coeff_0_U1443.out"], + ["mul_d1__U1446.in0","coeff_1_U1445.out"], + ["mul_d2__U1448.in0","coeff_2_U1447.out"], + ["mul_d3__U1450.in0","coeff_3_U1449.out"], + ["self.d.0","mul_d0__U1444.in1"], + ["self.d.1","mul_d1__U1446.in1"], + ["self.d.2","mul_d2__U1448.in1"], + ["self.d.3","mul_d3__U1450.in1"] ] }, - "aff__U1548":{ + "aff__U1465":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1558":{ + "add_all__U1475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1559":{ + "add_all__U1476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1560":{ + "add_all__U1477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1561":{ + "add_all__U1478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1549":{ + "coeff_0_U1466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1551":{ + "coeff_1_U1468":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U1553":{ + "coeff_2_U1470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "coeff_3_U1555":{ + "coeff_3_U1472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000031"]} }, - "const_term_U1557":{ + "const_term_U1474":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U1550":{ + "mul_d0__U1467":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1552":{ + "mul_d1__U1469":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1554":{ + "mul_d2__U1471":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1556":{ + "mul_d3__U1473":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1550.out","add_all__U1558.in0"], - ["mul_d1__U1552.out","add_all__U1558.in1"], - ["add_all__U1559.in0","add_all__U1558.out"], - ["mul_d2__U1554.out","add_all__U1559.in1"], - ["add_all__U1560.in0","add_all__U1559.out"], - ["mul_d3__U1556.out","add_all__U1560.in1"], - ["add_all__U1561.in0","add_all__U1560.out"], - ["const_term_U1557.out","add_all__U1561.in1"], - ["self.out","add_all__U1561.out"], - ["mul_d0__U1550.in0","coeff_0_U1549.out"], - ["mul_d1__U1552.in0","coeff_1_U1551.out"], - ["mul_d2__U1554.in0","coeff_2_U1553.out"], - ["mul_d3__U1556.in0","coeff_3_U1555.out"], - ["self.d.0","mul_d0__U1550.in1"], - ["self.d.1","mul_d1__U1552.in1"], - ["self.d.2","mul_d2__U1554.in1"], - ["self.d.3","mul_d3__U1556.in1"] + ["mul_d0__U1467.out","add_all__U1475.in0"], + ["mul_d1__U1469.out","add_all__U1475.in1"], + ["add_all__U1476.in0","add_all__U1475.out"], + ["mul_d2__U1471.out","add_all__U1476.in1"], + ["add_all__U1477.in0","add_all__U1476.out"], + ["mul_d3__U1473.out","add_all__U1477.in1"], + ["add_all__U1478.in0","add_all__U1477.out"], + ["const_term_U1474.out","add_all__U1478.in1"], + ["self.out","add_all__U1478.out"], + ["mul_d0__U1467.in0","coeff_0_U1466.out"], + ["mul_d1__U1469.in0","coeff_1_U1468.out"], + ["mul_d2__U1471.in0","coeff_2_U1470.out"], + ["mul_d3__U1473.in0","coeff_3_U1472.out"], + ["self.d.0","mul_d0__U1467.in1"], + ["self.d.1","mul_d1__U1469.in1"], + ["self.d.2","mul_d2__U1471.in1"], + ["self.d.3","mul_d3__U1473.in1"] ] }, - "aff__U1565":{ + "aff__U1482":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U1575":{ + "add_all__U1492":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1576":{ + "add_all__U1493":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1577":{ + "add_all__U1494":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U1578":{ + "add_all__U1495":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U1566":{ + "coeff_0_U1483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U1568":{ + "coeff_1_U1485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U1570":{ + "coeff_2_U1487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "coeff_3_U1572":{ + "coeff_3_U1489":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U1574":{ + "const_term_U1491":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00028360"]} }, - "mul_d0__U1567":{ + "mul_d0__U1484":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U1569":{ + "mul_d1__U1486":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U1571":{ + "mul_d2__U1488":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U1573":{ + "mul_d3__U1490":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U1567.out","add_all__U1575.in0"], - ["mul_d1__U1569.out","add_all__U1575.in1"], - ["add_all__U1576.in0","add_all__U1575.out"], - ["mul_d2__U1571.out","add_all__U1576.in1"], - ["add_all__U1577.in0","add_all__U1576.out"], - ["mul_d3__U1573.out","add_all__U1577.in1"], - ["add_all__U1578.in0","add_all__U1577.out"], - ["const_term_U1574.out","add_all__U1578.in1"], - ["self.out","add_all__U1578.out"], - ["mul_d0__U1567.in0","coeff_0_U1566.out"], - ["mul_d1__U1569.in0","coeff_1_U1568.out"], - ["mul_d2__U1571.in0","coeff_2_U1570.out"], - ["mul_d3__U1573.in0","coeff_3_U1572.out"], - ["self.d.0","mul_d0__U1567.in1"], - ["self.d.1","mul_d1__U1569.in1"], - ["self.d.2","mul_d2__U1571.in1"], - ["self.d.3","mul_d3__U1573.in1"] + ["mul_d0__U1484.out","add_all__U1492.in0"], + ["mul_d1__U1486.out","add_all__U1492.in1"], + ["add_all__U1493.in0","add_all__U1492.out"], + ["mul_d2__U1488.out","add_all__U1493.in1"], + ["add_all__U1494.in0","add_all__U1493.out"], + ["mul_d3__U1490.out","add_all__U1494.in1"], + ["add_all__U1495.in0","add_all__U1494.out"], + ["const_term_U1491.out","add_all__U1495.in1"], + ["self.out","add_all__U1495.out"], + ["mul_d0__U1484.in0","coeff_0_U1483.out"], + ["mul_d1__U1486.in0","coeff_1_U1485.out"], + ["mul_d2__U1488.in0","coeff_2_U1487.out"], + ["mul_d3__U1490.in0","coeff_3_U1489.out"], + ["self.d.0","mul_d0__U1484.in1"], + ["self.d.1","mul_d1__U1486.in1"], + ["self.d.2","mul_d2__U1488.in1"], + ["self.d.3","mul_d3__U1490.in1"] ] }, - "aff__U161":{ + "aff__U152":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U177":{ + "add_all__U168":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U178":{ + "add_all__U169":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U179":{ + "add_all__U170":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U180":{ + "add_all__U171":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U181":{ + "add_all__U172":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U182":{ + "add_all__U173":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U183":{ + "add_all__U174":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U162":{ + "coeff_0_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U164":{ + "coeff_1_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "coeff_2_U166":{ + "coeff_2_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00004800"]} }, - "coeff_3_U168":{ + "coeff_3_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "coeff_4_U170":{ + "coeff_4_U161":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000020"]} }, - "coeff_5_U172":{ + "coeff_5_U163":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_6_U174":{ + "coeff_6_U165":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U176":{ + "const_term_U167":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00011fff"]} }, - "mul_d0__U163":{ + "mul_d0__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U165":{ + "mul_d1__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U167":{ + "mul_d2__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U169":{ + "mul_d3__U160":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U171":{ + "mul_d4__U162":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U173":{ + "mul_d5__U164":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U175":{ + "mul_d6__U166":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U163.out","add_all__U177.in0"], - ["mul_d1__U165.out","add_all__U177.in1"], - ["add_all__U178.in0","add_all__U177.out"], - ["mul_d2__U167.out","add_all__U178.in1"], - ["add_all__U179.in0","add_all__U178.out"], - ["mul_d3__U169.out","add_all__U179.in1"], - ["add_all__U180.in0","add_all__U179.out"], - ["mul_d4__U171.out","add_all__U180.in1"], - ["add_all__U181.in0","add_all__U180.out"], - ["mul_d5__U173.out","add_all__U181.in1"], - ["add_all__U182.in0","add_all__U181.out"], - ["mul_d6__U175.out","add_all__U182.in1"], - ["add_all__U183.in0","add_all__U182.out"], - ["const_term_U176.out","add_all__U183.in1"], - ["self.out","add_all__U183.out"], - ["mul_d0__U163.in0","coeff_0_U162.out"], - ["mul_d1__U165.in0","coeff_1_U164.out"], - ["mul_d2__U167.in0","coeff_2_U166.out"], - ["mul_d3__U169.in0","coeff_3_U168.out"], - ["mul_d4__U171.in0","coeff_4_U170.out"], - ["mul_d5__U173.in0","coeff_5_U172.out"], - ["mul_d6__U175.in0","coeff_6_U174.out"], - ["self.d.0","mul_d0__U163.in1"], - ["self.d.1","mul_d1__U165.in1"], - ["self.d.2","mul_d2__U167.in1"], - ["self.d.3","mul_d3__U169.in1"], - ["self.d.4","mul_d4__U171.in1"], - ["self.d.5","mul_d5__U173.in1"], - ["self.d.6","mul_d6__U175.in1"] + ["mul_d0__U154.out","add_all__U168.in0"], + ["mul_d1__U156.out","add_all__U168.in1"], + ["add_all__U169.in0","add_all__U168.out"], + ["mul_d2__U158.out","add_all__U169.in1"], + ["add_all__U170.in0","add_all__U169.out"], + ["mul_d3__U160.out","add_all__U170.in1"], + ["add_all__U171.in0","add_all__U170.out"], + ["mul_d4__U162.out","add_all__U171.in1"], + ["add_all__U172.in0","add_all__U171.out"], + ["mul_d5__U164.out","add_all__U172.in1"], + ["add_all__U173.in0","add_all__U172.out"], + ["mul_d6__U166.out","add_all__U173.in1"], + ["add_all__U174.in0","add_all__U173.out"], + ["const_term_U167.out","add_all__U174.in1"], + ["self.out","add_all__U174.out"], + ["mul_d0__U154.in0","coeff_0_U153.out"], + ["mul_d1__U156.in0","coeff_1_U155.out"], + ["mul_d2__U158.in0","coeff_2_U157.out"], + ["mul_d3__U160.in0","coeff_3_U159.out"], + ["mul_d4__U162.in0","coeff_4_U161.out"], + ["mul_d5__U164.in0","coeff_5_U163.out"], + ["mul_d6__U166.in0","coeff_6_U165.out"], + ["self.d.0","mul_d0__U154.in1"], + ["self.d.1","mul_d1__U156.in1"], + ["self.d.2","mul_d2__U158.in1"], + ["self.d.3","mul_d3__U160.in1"], + ["self.d.4","mul_d4__U162.in1"], + ["self.d.5","mul_d5__U164.in1"], + ["self.d.6","mul_d6__U166.in1"] ] }, - "aff__U17":{ + "aff__U16":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U23":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U24":{ + "add_all__U23":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U18":{ + "coeff_0_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U20":{ + "coeff_1_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U22":{ + "const_term_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U19":{ + "mul_d0__U18":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U21":{ + "mul_d1__U20":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U19.out","add_all__U23.in0"], - ["mul_d1__U21.out","add_all__U23.in1"], - ["add_all__U24.in0","add_all__U23.out"], - ["const_term_U22.out","add_all__U24.in1"], - ["self.out","add_all__U24.out"], - ["mul_d0__U19.in0","coeff_0_U18.out"], - ["mul_d1__U21.in0","coeff_1_U20.out"], - ["self.d.0","mul_d0__U19.in1"], - ["self.d.1","mul_d1__U21.in1"] + ["mul_d0__U18.out","add_all__U22.in0"], + ["mul_d1__U20.out","add_all__U22.in1"], + ["add_all__U23.in0","add_all__U22.out"], + ["const_term_U21.out","add_all__U23.in1"], + ["self.out","add_all__U23.out"], + ["mul_d0__U18.in0","coeff_0_U17.out"], + ["mul_d1__U20.in0","coeff_1_U19.out"], + ["self.d.0","mul_d0__U18.in1"], + ["self.d.1","mul_d1__U20.in1"] ] }, - "aff__U2":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",2,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U8":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U9":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U3":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U5":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "const_term_U7":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "mul_d0__U4":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U6":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U4.out","add_all__U8.in0"], - ["mul_d1__U6.out","add_all__U8.in1"], - ["add_all__U9.in0","add_all__U8.out"], - ["const_term_U7.out","add_all__U9.in1"], - ["self.out","add_all__U9.out"], - ["mul_d0__U4.in0","coeff_0_U3.out"], - ["mul_d1__U6.in0","coeff_1_U5.out"], - ["self.d.0","mul_d0__U4.in1"], - ["self.d.1","mul_d1__U6.in1"] - ] - }, - "aff__U208":{ + "aff__U199":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U224":{ + "add_all__U215":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U225":{ + "add_all__U216":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U226":{ + "add_all__U217":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U227":{ + "add_all__U218":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U228":{ + "add_all__U219":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U229":{ + "add_all__U220":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U230":{ + "add_all__U221":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U209":{ + "coeff_0_U200":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U211":{ + "coeff_1_U202":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U213":{ + "coeff_2_U204":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000a20"]} }, - "coeff_3_U215":{ + "coeff_3_U206":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_4_U217":{ + "coeff_4_U208":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_5_U219":{ + "coeff_5_U210":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000288"]} }, - "coeff_6_U221":{ + "coeff_6_U212":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000051"]} }, - "const_term_U223":{ + "const_term_U214":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U210":{ + "mul_d0__U201":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U212":{ + "mul_d1__U203":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U214":{ + "mul_d2__U205":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U216":{ + "mul_d3__U207":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U218":{ + "mul_d4__U209":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U220":{ + "mul_d5__U211":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U222":{ + "mul_d6__U213":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U210.out","add_all__U224.in0"], - ["mul_d1__U212.out","add_all__U224.in1"], - ["add_all__U225.in0","add_all__U224.out"], - ["mul_d2__U214.out","add_all__U225.in1"], - ["add_all__U226.in0","add_all__U225.out"], - ["mul_d3__U216.out","add_all__U226.in1"], - ["add_all__U227.in0","add_all__U226.out"], - ["mul_d4__U218.out","add_all__U227.in1"], - ["add_all__U228.in0","add_all__U227.out"], - ["mul_d5__U220.out","add_all__U228.in1"], - ["add_all__U229.in0","add_all__U228.out"], - ["mul_d6__U222.out","add_all__U229.in1"], - ["add_all__U230.in0","add_all__U229.out"], - ["const_term_U223.out","add_all__U230.in1"], - ["self.out","add_all__U230.out"], - ["mul_d0__U210.in0","coeff_0_U209.out"], - ["mul_d1__U212.in0","coeff_1_U211.out"], - ["mul_d2__U214.in0","coeff_2_U213.out"], - ["mul_d3__U216.in0","coeff_3_U215.out"], - ["mul_d4__U218.in0","coeff_4_U217.out"], - ["mul_d5__U220.in0","coeff_5_U219.out"], - ["mul_d6__U222.in0","coeff_6_U221.out"], - ["self.d.0","mul_d0__U210.in1"], - ["self.d.1","mul_d1__U212.in1"], - ["self.d.2","mul_d2__U214.in1"], - ["self.d.3","mul_d3__U216.in1"], - ["self.d.4","mul_d4__U218.in1"], - ["self.d.5","mul_d5__U220.in1"], - ["self.d.6","mul_d6__U222.in1"] + ["mul_d0__U201.out","add_all__U215.in0"], + ["mul_d1__U203.out","add_all__U215.in1"], + ["add_all__U216.in0","add_all__U215.out"], + ["mul_d2__U205.out","add_all__U216.in1"], + ["add_all__U217.in0","add_all__U216.out"], + ["mul_d3__U207.out","add_all__U217.in1"], + ["add_all__U218.in0","add_all__U217.out"], + ["mul_d4__U209.out","add_all__U218.in1"], + ["add_all__U219.in0","add_all__U218.out"], + ["mul_d5__U211.out","add_all__U219.in1"], + ["add_all__U220.in0","add_all__U219.out"], + ["mul_d6__U213.out","add_all__U220.in1"], + ["add_all__U221.in0","add_all__U220.out"], + ["const_term_U214.out","add_all__U221.in1"], + ["self.out","add_all__U221.out"], + ["mul_d0__U201.in0","coeff_0_U200.out"], + ["mul_d1__U203.in0","coeff_1_U202.out"], + ["mul_d2__U205.in0","coeff_2_U204.out"], + ["mul_d3__U207.in0","coeff_3_U206.out"], + ["mul_d4__U209.in0","coeff_4_U208.out"], + ["mul_d5__U211.in0","coeff_5_U210.out"], + ["mul_d6__U213.in0","coeff_6_U212.out"], + ["self.d.0","mul_d0__U201.in1"], + ["self.d.1","mul_d1__U203.in1"], + ["self.d.2","mul_d2__U205.in1"], + ["self.d.3","mul_d3__U207.in1"], + ["self.d.4","mul_d4__U209.in1"], + ["self.d.5","mul_d5__U211.in1"], + ["self.d.6","mul_d6__U213.in1"] ] }, - "aff__U235":{ + "aff__U2":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U241":{ + "add_all__U8":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U242":{ + "add_all__U9":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U236":{ + "coeff_0_U3":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U238":{ + "coeff_1_U5":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U240":{ + "const_term_U7":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U237":{ + "mul_d0__U4":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U239":{ + "mul_d1__U6":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U237.out","add_all__U241.in0"], - ["mul_d1__U239.out","add_all__U241.in1"], - ["add_all__U242.in0","add_all__U241.out"], - ["const_term_U240.out","add_all__U242.in1"], - ["self.out","add_all__U242.out"], - ["mul_d0__U237.in0","coeff_0_U236.out"], - ["mul_d1__U239.in0","coeff_1_U238.out"], - ["self.d.0","mul_d0__U237.in1"], - ["self.d.1","mul_d1__U239.in1"] + ["mul_d0__U4.out","add_all__U8.in0"], + ["mul_d1__U6.out","add_all__U8.in1"], + ["add_all__U9.in0","add_all__U8.out"], + ["const_term_U7.out","add_all__U9.in1"], + ["self.out","add_all__U9.out"], + ["mul_d0__U4.in0","coeff_0_U3.out"], + ["mul_d1__U6.in0","coeff_1_U5.out"], + ["self.d.0","mul_d0__U4.in1"], + ["self.d.1","mul_d1__U6.in1"] ] }, - "aff__U250":{ + "aff__U226":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U256":{ + "add_all__U232":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U257":{ + "add_all__U233":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U251":{ + "coeff_0_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U253":{ + "coeff_1_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U255":{ + "const_term_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U252":{ + "mul_d0__U228":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U254":{ + "mul_d1__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U252.out","add_all__U256.in0"], - ["mul_d1__U254.out","add_all__U256.in1"], - ["add_all__U257.in0","add_all__U256.out"], - ["const_term_U255.out","add_all__U257.in1"], - ["self.out","add_all__U257.out"], - ["mul_d0__U252.in0","coeff_0_U251.out"], - ["mul_d1__U254.in0","coeff_1_U253.out"], - ["self.d.0","mul_d0__U252.in1"], - ["self.d.1","mul_d1__U254.in1"] + ["mul_d0__U228.out","add_all__U232.in0"], + ["mul_d1__U230.out","add_all__U232.in1"], + ["add_all__U233.in0","add_all__U232.out"], + ["const_term_U231.out","add_all__U233.in1"], + ["self.out","add_all__U233.out"], + ["mul_d0__U228.in0","coeff_0_U227.out"], + ["mul_d1__U230.in0","coeff_1_U229.out"], + ["self.d.0","mul_d0__U228.in1"], + ["self.d.1","mul_d1__U230.in1"] ] }, - "aff__U265":{ + "aff__U240":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U271":{ + "add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U272":{ + "add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U266":{ + "coeff_0_U241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U268":{ + "coeff_1_U243":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U270":{ + "const_term_U245":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U267":{ + "mul_d0__U242":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U269":{ + "mul_d1__U244":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U267.out","add_all__U271.in0"], - ["mul_d1__U269.out","add_all__U271.in1"], - ["add_all__U272.in0","add_all__U271.out"], - ["const_term_U270.out","add_all__U272.in1"], - ["self.out","add_all__U272.out"], - ["mul_d0__U267.in0","coeff_0_U266.out"], - ["mul_d1__U269.in0","coeff_1_U268.out"], - ["self.d.0","mul_d0__U267.in1"], - ["self.d.1","mul_d1__U269.in1"] + ["mul_d0__U242.out","add_all__U246.in0"], + ["mul_d1__U244.out","add_all__U246.in1"], + ["add_all__U247.in0","add_all__U246.out"], + ["const_term_U245.out","add_all__U247.in1"], + ["self.out","add_all__U247.out"], + ["mul_d0__U242.in0","coeff_0_U241.out"], + ["mul_d1__U244.in0","coeff_1_U243.out"], + ["self.d.0","mul_d0__U242.in1"], + ["self.d.1","mul_d1__U244.in1"] ] }, - "aff__U280":{ + "aff__U254":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U286":{ + "add_all__U260":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U287":{ + "add_all__U261":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U281":{ + "coeff_0_U255":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U283":{ + "coeff_1_U257":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U285":{ + "const_term_U259":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U282":{ + "mul_d0__U256":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U284":{ + "mul_d1__U258":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U282.out","add_all__U286.in0"], - ["mul_d1__U284.out","add_all__U286.in1"], - ["add_all__U287.in0","add_all__U286.out"], - ["const_term_U285.out","add_all__U287.in1"], - ["self.out","add_all__U287.out"], - ["mul_d0__U282.in0","coeff_0_U281.out"], - ["mul_d1__U284.in0","coeff_1_U283.out"], - ["self.d.0","mul_d0__U282.in1"], - ["self.d.1","mul_d1__U284.in1"] + ["mul_d0__U256.out","add_all__U260.in0"], + ["mul_d1__U258.out","add_all__U260.in1"], + ["add_all__U261.in0","add_all__U260.out"], + ["const_term_U259.out","add_all__U261.in1"], + ["self.out","add_all__U261.out"], + ["mul_d0__U256.in0","coeff_0_U255.out"], + ["mul_d1__U258.in0","coeff_1_U257.out"], + ["self.d.0","mul_d0__U256.in1"], + ["self.d.1","mul_d1__U258.in1"] ] }, - "aff__U295":{ + "aff__U268":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U301":{ + "add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U302":{ + "add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U296":{ + "coeff_0_U269":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U298":{ + "coeff_1_U271":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U300":{ + "const_term_U273":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U297":{ + "mul_d0__U270":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U299":{ + "mul_d1__U272":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U297.out","add_all__U301.in0"], - ["mul_d1__U299.out","add_all__U301.in1"], - ["add_all__U302.in0","add_all__U301.out"], - ["const_term_U300.out","add_all__U302.in1"], - ["self.out","add_all__U302.out"], - ["mul_d0__U297.in0","coeff_0_U296.out"], - ["mul_d1__U299.in0","coeff_1_U298.out"], - ["self.d.0","mul_d0__U297.in1"], - ["self.d.1","mul_d1__U299.in1"] + ["mul_d0__U270.out","add_all__U274.in0"], + ["mul_d1__U272.out","add_all__U274.in1"], + ["add_all__U275.in0","add_all__U274.out"], + ["const_term_U273.out","add_all__U275.in1"], + ["self.out","add_all__U275.out"], + ["mul_d0__U270.in0","coeff_0_U269.out"], + ["mul_d1__U272.in0","coeff_1_U271.out"], + ["self.d.0","mul_d0__U270.in1"], + ["self.d.1","mul_d1__U272.in1"] ] }, - "aff__U310":{ + "aff__U282":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U316":{ + "add_all__U288":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U289":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U311":{ + "coeff_0_U283":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U313":{ + "coeff_1_U285":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U315":{ + "const_term_U287":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U312":{ + "mul_d0__U284":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U314":{ + "mul_d1__U286":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U312.out","add_all__U316.in0"], - ["mul_d1__U314.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["const_term_U315.out","add_all__U317.in1"], - ["self.out","add_all__U317.out"], - ["mul_d0__U312.in0","coeff_0_U311.out"], - ["mul_d1__U314.in0","coeff_1_U313.out"], - ["self.d.0","mul_d0__U312.in1"], - ["self.d.1","mul_d1__U314.in1"] + ["mul_d0__U284.out","add_all__U288.in0"], + ["mul_d1__U286.out","add_all__U288.in1"], + ["add_all__U289.in0","add_all__U288.out"], + ["const_term_U287.out","add_all__U289.in1"], + ["self.out","add_all__U289.out"], + ["mul_d0__U284.in0","coeff_0_U283.out"], + ["mul_d1__U286.in0","coeff_1_U285.out"], + ["self.d.0","mul_d0__U284.in1"], + ["self.d.1","mul_d1__U286.in1"] ] }, - "aff__U32":{ + "aff__U296":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U38":{ + "add_all__U302":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U39":{ + "add_all__U303":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U33":{ + "coeff_0_U297":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U35":{ + "coeff_1_U299":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U37":{ + "const_term_U301":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U34":{ + "mul_d0__U298":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U36":{ + "mul_d1__U300":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U34.out","add_all__U38.in0"], - ["mul_d1__U36.out","add_all__U38.in1"], - ["add_all__U39.in0","add_all__U38.out"], - ["const_term_U37.out","add_all__U39.in1"], - ["self.out","add_all__U39.out"], - ["mul_d0__U34.in0","coeff_0_U33.out"], - ["mul_d1__U36.in0","coeff_1_U35.out"], - ["self.d.0","mul_d0__U34.in1"], - ["self.d.1","mul_d1__U36.in1"] + ["mul_d0__U298.out","add_all__U302.in0"], + ["mul_d1__U300.out","add_all__U302.in1"], + ["add_all__U303.in0","add_all__U302.out"], + ["const_term_U301.out","add_all__U303.in1"], + ["self.out","add_all__U303.out"], + ["mul_d0__U298.in0","coeff_0_U297.out"], + ["mul_d1__U300.in0","coeff_1_U299.out"], + ["self.d.0","mul_d0__U298.in1"], + ["self.d.1","mul_d1__U300.in1"] ] }, - "aff__U325":{ + "aff__U30":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U331":{ + "add_all__U36":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U332":{ + "add_all__U37":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U326":{ + "coeff_0_U31":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U328":{ + "coeff_1_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U330":{ + "const_term_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U327":{ + "mul_d0__U32":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U329":{ + "mul_d1__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U327.out","add_all__U331.in0"], - ["mul_d1__U329.out","add_all__U331.in1"], - ["add_all__U332.in0","add_all__U331.out"], - ["const_term_U330.out","add_all__U332.in1"], - ["self.out","add_all__U332.out"], - ["mul_d0__U327.in0","coeff_0_U326.out"], - ["mul_d1__U329.in0","coeff_1_U328.out"], - ["self.d.0","mul_d0__U327.in1"], - ["self.d.1","mul_d1__U329.in1"] + ["mul_d0__U32.out","add_all__U36.in0"], + ["mul_d1__U34.out","add_all__U36.in1"], + ["add_all__U37.in0","add_all__U36.out"], + ["const_term_U35.out","add_all__U37.in1"], + ["self.out","add_all__U37.out"], + ["mul_d0__U32.in0","coeff_0_U31.out"], + ["mul_d1__U34.in0","coeff_1_U33.out"], + ["self.d.0","mul_d0__U32.in1"], + ["self.d.1","mul_d1__U34.in1"] ] }, - "aff__U340":{ + "aff__U310":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U346":{ + "add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U347":{ + "add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U341":{ + "coeff_0_U311":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U343":{ + "coeff_1_U313":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U345":{ + "const_term_U315":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U342":{ + "mul_d0__U312":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U344":{ + "mul_d1__U314":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U342.out","add_all__U346.in0"], - ["mul_d1__U344.out","add_all__U346.in1"], - ["add_all__U347.in0","add_all__U346.out"], - ["const_term_U345.out","add_all__U347.in1"], - ["self.out","add_all__U347.out"], - ["mul_d0__U342.in0","coeff_0_U341.out"], - ["mul_d1__U344.in0","coeff_1_U343.out"], - ["self.d.0","mul_d0__U342.in1"], - ["self.d.1","mul_d1__U344.in1"] + ["mul_d0__U312.out","add_all__U316.in0"], + ["mul_d1__U314.out","add_all__U316.in1"], + ["add_all__U317.in0","add_all__U316.out"], + ["const_term_U315.out","add_all__U317.in1"], + ["self.out","add_all__U317.out"], + ["mul_d0__U312.in0","coeff_0_U311.out"], + ["mul_d1__U314.in0","coeff_1_U313.out"], + ["self.d.0","mul_d0__U312.in1"], + ["self.d.1","mul_d1__U314.in1"] ] }, - "aff__U355":{ + "aff__U324":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U361":{ + "add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U362":{ + "add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U356":{ + "coeff_0_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U358":{ + "coeff_1_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U360":{ + "const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U357":{ + "mul_d0__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U359":{ + "mul_d1__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U357.out","add_all__U361.in0"], - ["mul_d1__U359.out","add_all__U361.in1"], - ["add_all__U362.in0","add_all__U361.out"], - ["const_term_U360.out","add_all__U362.in1"], - ["self.out","add_all__U362.out"], - ["mul_d0__U357.in0","coeff_0_U356.out"], - ["mul_d1__U359.in0","coeff_1_U358.out"], - ["self.d.0","mul_d0__U357.in1"], - ["self.d.1","mul_d1__U359.in1"] + ["mul_d0__U326.out","add_all__U330.in0"], + ["mul_d1__U328.out","add_all__U330.in1"], + ["add_all__U331.in0","add_all__U330.out"], + ["const_term_U329.out","add_all__U331.in1"], + ["self.out","add_all__U331.out"], + ["mul_d0__U326.in0","coeff_0_U325.out"], + ["mul_d1__U328.in0","coeff_1_U327.out"], + ["self.d.0","mul_d0__U326.in1"], + ["self.d.1","mul_d1__U328.in1"] ] }, - "aff__U370":{ + "aff__U338":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U376":{ + "add_all__U344":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U377":{ + "add_all__U345":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U371":{ + "coeff_0_U339":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U373":{ + "coeff_1_U341":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U375":{ + "const_term_U343":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U372":{ + "mul_d0__U340":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U374":{ + "mul_d1__U342":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U372.out","add_all__U376.in0"], - ["mul_d1__U374.out","add_all__U376.in1"], - ["add_all__U377.in0","add_all__U376.out"], - ["const_term_U375.out","add_all__U377.in1"], - ["self.out","add_all__U377.out"], - ["mul_d0__U372.in0","coeff_0_U371.out"], - ["mul_d1__U374.in0","coeff_1_U373.out"], - ["self.d.0","mul_d0__U372.in1"], - ["self.d.1","mul_d1__U374.in1"] + ["mul_d0__U340.out","add_all__U344.in0"], + ["mul_d1__U342.out","add_all__U344.in1"], + ["add_all__U345.in0","add_all__U344.out"], + ["const_term_U343.out","add_all__U345.in1"], + ["self.out","add_all__U345.out"], + ["mul_d0__U340.in0","coeff_0_U339.out"], + ["mul_d1__U342.in0","coeff_1_U341.out"], + ["self.d.0","mul_d0__U340.in1"], + ["self.d.1","mul_d1__U342.in1"] ] }, - "aff__U385":{ + "aff__U352":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U391":{ + "add_all__U358":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U392":{ + "add_all__U359":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U386":{ + "coeff_0_U353":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U388":{ + "coeff_1_U355":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U390":{ + "const_term_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U387":{ + "mul_d0__U354":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U389":{ + "mul_d1__U356":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U387.out","add_all__U391.in0"], - ["mul_d1__U389.out","add_all__U391.in1"], - ["add_all__U392.in0","add_all__U391.out"], - ["const_term_U390.out","add_all__U392.in1"], - ["self.out","add_all__U392.out"], - ["mul_d0__U387.in0","coeff_0_U386.out"], - ["mul_d1__U389.in0","coeff_1_U388.out"], - ["self.d.0","mul_d0__U387.in1"], - ["self.d.1","mul_d1__U389.in1"] + ["mul_d0__U354.out","add_all__U358.in0"], + ["mul_d1__U356.out","add_all__U358.in1"], + ["add_all__U359.in0","add_all__U358.out"], + ["const_term_U357.out","add_all__U359.in1"], + ["self.out","add_all__U359.out"], + ["mul_d0__U354.in0","coeff_0_U353.out"], + ["mul_d1__U356.in0","coeff_1_U355.out"], + ["self.d.0","mul_d0__U354.in1"], + ["self.d.1","mul_d1__U356.in1"] ] }, - "aff__U400":{ + "aff__U366":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U406":{ + "add_all__U372":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U407":{ + "add_all__U373":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U401":{ + "coeff_0_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U403":{ + "coeff_1_U369":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U405":{ + "const_term_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U402":{ + "mul_d0__U368":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U404":{ + "mul_d1__U370":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U402.out","add_all__U406.in0"], - ["mul_d1__U404.out","add_all__U406.in1"], - ["add_all__U407.in0","add_all__U406.out"], - ["const_term_U405.out","add_all__U407.in1"], - ["self.out","add_all__U407.out"], - ["mul_d0__U402.in0","coeff_0_U401.out"], - ["mul_d1__U404.in0","coeff_1_U403.out"], - ["self.d.0","mul_d0__U402.in1"], - ["self.d.1","mul_d1__U404.in1"] + ["mul_d0__U368.out","add_all__U372.in0"], + ["mul_d1__U370.out","add_all__U372.in1"], + ["add_all__U373.in0","add_all__U372.out"], + ["const_term_U371.out","add_all__U373.in1"], + ["self.out","add_all__U373.out"], + ["mul_d0__U368.in0","coeff_0_U367.out"], + ["mul_d1__U370.in0","coeff_1_U369.out"], + ["self.d.0","mul_d0__U368.in1"], + ["self.d.1","mul_d1__U370.in1"] ] }, - "aff__U415":{ + "aff__U380":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U421":{ + "add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U422":{ + "add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U416":{ + "coeff_0_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U418":{ + "coeff_1_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U420":{ + "const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U417":{ + "mul_d0__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U419":{ + "mul_d1__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U417.out","add_all__U421.in0"], - ["mul_d1__U419.out","add_all__U421.in1"], - ["add_all__U422.in0","add_all__U421.out"], - ["const_term_U420.out","add_all__U422.in1"], - ["self.out","add_all__U422.out"], - ["mul_d0__U417.in0","coeff_0_U416.out"], - ["mul_d1__U419.in0","coeff_1_U418.out"], - ["self.d.0","mul_d0__U417.in1"], - ["self.d.1","mul_d1__U419.in1"] + ["mul_d0__U382.out","add_all__U386.in0"], + ["mul_d1__U384.out","add_all__U386.in1"], + ["add_all__U387.in0","add_all__U386.out"], + ["const_term_U385.out","add_all__U387.in1"], + ["self.out","add_all__U387.out"], + ["mul_d0__U382.in0","coeff_0_U381.out"], + ["mul_d1__U384.in0","coeff_1_U383.out"], + ["self.d.0","mul_d0__U382.in1"], + ["self.d.1","mul_d1__U384.in1"] ] }, - "aff__U430":{ + "aff__U394":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U436":{ + "add_all__U400":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U437":{ + "add_all__U401":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U431":{ + "coeff_0_U395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U433":{ + "coeff_1_U397":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U435":{ + "const_term_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U432":{ + "mul_d0__U396":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U434":{ + "mul_d1__U398":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U432.out","add_all__U436.in0"], - ["mul_d1__U434.out","add_all__U436.in1"], - ["add_all__U437.in0","add_all__U436.out"], - ["const_term_U435.out","add_all__U437.in1"], - ["self.out","add_all__U437.out"], - ["mul_d0__U432.in0","coeff_0_U431.out"], - ["mul_d1__U434.in0","coeff_1_U433.out"], - ["self.d.0","mul_d0__U432.in1"], - ["self.d.1","mul_d1__U434.in1"] + ["mul_d0__U396.out","add_all__U400.in0"], + ["mul_d1__U398.out","add_all__U400.in1"], + ["add_all__U401.in0","add_all__U400.out"], + ["const_term_U399.out","add_all__U401.in1"], + ["self.out","add_all__U401.out"], + ["mul_d0__U396.in0","coeff_0_U395.out"], + ["mul_d1__U398.in0","coeff_1_U397.out"], + ["self.d.0","mul_d0__U396.in1"], + ["self.d.1","mul_d1__U398.in1"] ] }, - "aff__U445":{ + "aff__U408":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U451":{ + "add_all__U414":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U452":{ + "add_all__U415":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U446":{ + "coeff_0_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U448":{ + "coeff_1_U411":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U450":{ + "const_term_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U447":{ + "mul_d0__U410":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U449":{ + "mul_d1__U412":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U447.out","add_all__U451.in0"], - ["mul_d1__U449.out","add_all__U451.in1"], - ["add_all__U452.in0","add_all__U451.out"], - ["const_term_U450.out","add_all__U452.in1"], - ["self.out","add_all__U452.out"], - ["mul_d0__U447.in0","coeff_0_U446.out"], - ["mul_d1__U449.in0","coeff_1_U448.out"], - ["self.d.0","mul_d0__U447.in1"], - ["self.d.1","mul_d1__U449.in1"] + ["mul_d0__U410.out","add_all__U414.in0"], + ["mul_d1__U412.out","add_all__U414.in1"], + ["add_all__U415.in0","add_all__U414.out"], + ["const_term_U413.out","add_all__U415.in1"], + ["self.out","add_all__U415.out"], + ["mul_d0__U410.in0","coeff_0_U409.out"], + ["mul_d1__U412.in0","coeff_1_U411.out"], + ["self.d.0","mul_d0__U410.in1"], + ["self.d.1","mul_d1__U412.in1"] ] }, - "aff__U460":{ + "aff__U422":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U466":{ + "add_all__U428":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U467":{ + "add_all__U429":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U461":{ + "coeff_0_U423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U463":{ + "coeff_1_U425":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U465":{ + "const_term_U427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U462":{ + "mul_d0__U424":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U464":{ + "mul_d1__U426":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U462.out","add_all__U466.in0"], - ["mul_d1__U464.out","add_all__U466.in1"], - ["add_all__U467.in0","add_all__U466.out"], - ["const_term_U465.out","add_all__U467.in1"], - ["self.out","add_all__U467.out"], - ["mul_d0__U462.in0","coeff_0_U461.out"], - ["mul_d1__U464.in0","coeff_1_U463.out"], - ["self.d.0","mul_d0__U462.in1"], - ["self.d.1","mul_d1__U464.in1"] + ["mul_d0__U424.out","add_all__U428.in0"], + ["mul_d1__U426.out","add_all__U428.in1"], + ["add_all__U429.in0","add_all__U428.out"], + ["const_term_U427.out","add_all__U429.in1"], + ["self.out","add_all__U429.out"], + ["mul_d0__U424.in0","coeff_0_U423.out"], + ["mul_d1__U426.in0","coeff_1_U425.out"], + ["self.d.0","mul_d0__U424.in1"], + ["self.d.1","mul_d1__U426.in1"] ] }, - "aff__U47":{ + "aff__U436":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U53":{ + "add_all__U442":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U443":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U48":{ + "coeff_0_U437":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U50":{ + "coeff_1_U439":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U52":{ + "const_term_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U49":{ + "mul_d0__U438":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U51":{ + "mul_d1__U440":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U49.out","add_all__U53.in0"], - ["mul_d1__U51.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U52.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U49.in0","coeff_0_U48.out"], - ["mul_d1__U51.in0","coeff_1_U50.out"], - ["self.d.0","mul_d0__U49.in1"], - ["self.d.1","mul_d1__U51.in1"] + ["mul_d0__U438.out","add_all__U442.in0"], + ["mul_d1__U440.out","add_all__U442.in1"], + ["add_all__U443.in0","add_all__U442.out"], + ["const_term_U441.out","add_all__U443.in1"], + ["self.out","add_all__U443.out"], + ["mul_d0__U438.in0","coeff_0_U437.out"], + ["mul_d1__U440.in0","coeff_1_U439.out"], + ["self.d.0","mul_d0__U438.in1"], + ["self.d.1","mul_d1__U440.in1"] ] }, - "aff__U475":{ + "aff__U44":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U481":{ + "add_all__U50":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U482":{ + "add_all__U51":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U476":{ + "coeff_0_U45":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U478":{ + "coeff_1_U47":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U480":{ + "const_term_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U477":{ + "mul_d0__U46":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U479":{ + "mul_d1__U48":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U477.out","add_all__U481.in0"], - ["mul_d1__U479.out","add_all__U481.in1"], - ["add_all__U482.in0","add_all__U481.out"], - ["const_term_U480.out","add_all__U482.in1"], - ["self.out","add_all__U482.out"], - ["mul_d0__U477.in0","coeff_0_U476.out"], - ["mul_d1__U479.in0","coeff_1_U478.out"], - ["self.d.0","mul_d0__U477.in1"], - ["self.d.1","mul_d1__U479.in1"] + ["mul_d0__U46.out","add_all__U50.in0"], + ["mul_d1__U48.out","add_all__U50.in1"], + ["add_all__U51.in0","add_all__U50.out"], + ["const_term_U49.out","add_all__U51.in1"], + ["self.out","add_all__U51.out"], + ["mul_d0__U46.in0","coeff_0_U45.out"], + ["mul_d1__U48.in0","coeff_1_U47.out"], + ["self.d.0","mul_d0__U46.in1"], + ["self.d.1","mul_d1__U48.in1"] ] }, - "aff__U490":{ + "aff__U450":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U496":{ + "add_all__U456":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U497":{ + "add_all__U457":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U491":{ + "coeff_0_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U493":{ + "coeff_1_U453":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U495":{ + "const_term_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U492":{ + "mul_d0__U452":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U494":{ + "mul_d1__U454":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U492.out","add_all__U496.in0"], - ["mul_d1__U494.out","add_all__U496.in1"], - ["add_all__U497.in0","add_all__U496.out"], - ["const_term_U495.out","add_all__U497.in1"], - ["self.out","add_all__U497.out"], - ["mul_d0__U492.in0","coeff_0_U491.out"], - ["mul_d1__U494.in0","coeff_1_U493.out"], - ["self.d.0","mul_d0__U492.in1"], - ["self.d.1","mul_d1__U494.in1"] + ["mul_d0__U452.out","add_all__U456.in0"], + ["mul_d1__U454.out","add_all__U456.in1"], + ["add_all__U457.in0","add_all__U456.out"], + ["const_term_U455.out","add_all__U457.in1"], + ["self.out","add_all__U457.out"], + ["mul_d0__U452.in0","coeff_0_U451.out"], + ["mul_d1__U454.in0","coeff_1_U453.out"], + ["self.d.0","mul_d0__U452.in1"], + ["self.d.1","mul_d1__U454.in1"] ] }, - "aff__U505":{ + "aff__U464":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U511":{ + "add_all__U470":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, + "add_all__U471":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U465":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U467":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U469":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U466":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U468":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U466.out","add_all__U470.in0"], + ["mul_d1__U468.out","add_all__U470.in1"], + ["add_all__U471.in0","add_all__U470.out"], + ["const_term_U469.out","add_all__U471.in1"], + ["self.out","add_all__U471.out"], + ["mul_d0__U466.in0","coeff_0_U465.out"], + ["mul_d1__U468.in0","coeff_1_U467.out"], + ["self.d.0","mul_d0__U466.in1"], + ["self.d.1","mul_d1__U468.in1"] + ] + }, + "aff__U478":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U484":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U485":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U479":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U481":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U483":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U480":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U482":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U480.out","add_all__U484.in0"], + ["mul_d1__U482.out","add_all__U484.in1"], + ["add_all__U485.in0","add_all__U484.out"], + ["const_term_U483.out","add_all__U485.in1"], + ["self.out","add_all__U485.out"], + ["mul_d0__U480.in0","coeff_0_U479.out"], + ["mul_d1__U482.in0","coeff_1_U481.out"], + ["self.d.0","mul_d0__U480.in1"], + ["self.d.1","mul_d1__U482.in1"] + ] + }, + "aff__U492":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U498":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U499":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U493":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U495":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U497":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U494":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U496":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U494.out","add_all__U498.in0"], + ["mul_d1__U496.out","add_all__U498.in1"], + ["add_all__U499.in0","add_all__U498.out"], + ["const_term_U497.out","add_all__U499.in1"], + ["self.out","add_all__U499.out"], + ["mul_d0__U494.in0","coeff_0_U493.out"], + ["mul_d1__U496.in0","coeff_1_U495.out"], + ["self.d.0","mul_d0__U494.in1"], + ["self.d.1","mul_d1__U496.in1"] + ] + }, + "aff__U506":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ "add_all__U512":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U506":{ + "add_all__U513":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U507":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U508":{ + "coeff_1_U509":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U510":{ + "const_term_U511":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U507":{ + "mul_d0__U508":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U509":{ + "mul_d1__U510":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U507.out","add_all__U511.in0"], - ["mul_d1__U509.out","add_all__U511.in1"], - ["add_all__U512.in0","add_all__U511.out"], - ["const_term_U510.out","add_all__U512.in1"], - ["self.out","add_all__U512.out"], - ["mul_d0__U507.in0","coeff_0_U506.out"], - ["mul_d1__U509.in0","coeff_1_U508.out"], - ["self.d.0","mul_d0__U507.in1"], - ["self.d.1","mul_d1__U509.in1"] + ["mul_d0__U508.out","add_all__U512.in0"], + ["mul_d1__U510.out","add_all__U512.in1"], + ["add_all__U513.in0","add_all__U512.out"], + ["const_term_U511.out","add_all__U513.in1"], + ["self.out","add_all__U513.out"], + ["mul_d0__U508.in0","coeff_0_U507.out"], + ["mul_d1__U510.in0","coeff_1_U509.out"], + ["self.d.0","mul_d0__U508.in1"], + ["self.d.1","mul_d1__U510.in1"] ] }, "aff__U520":{ @@ -3998,704 +3848,804 @@ ["self.d.1","mul_d1__U524.in1"] ] }, - "aff__U535":{ + "aff__U534":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U541":{ + "add_all__U540":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U542":{ + "add_all__U541":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U536":{ + "coeff_0_U535":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U538":{ + "coeff_1_U537":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U540":{ + "const_term_U539":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U537":{ + "mul_d0__U536":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U539":{ + "mul_d1__U538":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U537.out","add_all__U541.in0"], - ["mul_d1__U539.out","add_all__U541.in1"], - ["add_all__U542.in0","add_all__U541.out"], - ["const_term_U540.out","add_all__U542.in1"], - ["self.out","add_all__U542.out"], - ["mul_d0__U537.in0","coeff_0_U536.out"], - ["mul_d1__U539.in0","coeff_1_U538.out"], - ["self.d.0","mul_d0__U537.in1"], - ["self.d.1","mul_d1__U539.in1"] + ["mul_d0__U536.out","add_all__U540.in0"], + ["mul_d1__U538.out","add_all__U540.in1"], + ["add_all__U541.in0","add_all__U540.out"], + ["const_term_U539.out","add_all__U541.in1"], + ["self.out","add_all__U541.out"], + ["mul_d0__U536.in0","coeff_0_U535.out"], + ["mul_d1__U538.in0","coeff_1_U537.out"], + ["self.d.0","mul_d0__U536.in1"], + ["self.d.1","mul_d1__U538.in1"] ] }, - "aff__U550":{ + "aff__U548":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U556":{ + "add_all__U554":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U557":{ + "add_all__U555":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U551":{ + "coeff_0_U549":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U553":{ + "coeff_1_U551":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U555":{ + "const_term_U553":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U552":{ + "mul_d0__U550":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U554":{ + "mul_d1__U552":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U552.out","add_all__U556.in0"], - ["mul_d1__U554.out","add_all__U556.in1"], - ["add_all__U557.in0","add_all__U556.out"], - ["const_term_U555.out","add_all__U557.in1"], - ["self.out","add_all__U557.out"], - ["mul_d0__U552.in0","coeff_0_U551.out"], - ["mul_d1__U554.in0","coeff_1_U553.out"], - ["self.d.0","mul_d0__U552.in1"], - ["self.d.1","mul_d1__U554.in1"] + ["mul_d0__U550.out","add_all__U554.in0"], + ["mul_d1__U552.out","add_all__U554.in1"], + ["add_all__U555.in0","add_all__U554.out"], + ["const_term_U553.out","add_all__U555.in1"], + ["self.out","add_all__U555.out"], + ["mul_d0__U550.in0","coeff_0_U549.out"], + ["mul_d1__U552.in0","coeff_1_U551.out"], + ["self.d.0","mul_d0__U550.in1"], + ["self.d.1","mul_d1__U552.in1"] ] }, - "aff__U565":{ + "aff__U562":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U571":{ + "add_all__U568":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U572":{ + "add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U566":{ + "coeff_0_U563":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U568":{ + "coeff_1_U565":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U570":{ + "const_term_U567":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U567":{ + "mul_d0__U564":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U569":{ + "mul_d1__U566":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U567.out","add_all__U571.in0"], - ["mul_d1__U569.out","add_all__U571.in1"], - ["add_all__U572.in0","add_all__U571.out"], - ["const_term_U570.out","add_all__U572.in1"], - ["self.out","add_all__U572.out"], - ["mul_d0__U567.in0","coeff_0_U566.out"], - ["mul_d1__U569.in0","coeff_1_U568.out"], - ["self.d.0","mul_d0__U567.in1"], - ["self.d.1","mul_d1__U569.in1"] + ["mul_d0__U564.out","add_all__U568.in0"], + ["mul_d1__U566.out","add_all__U568.in1"], + ["add_all__U569.in0","add_all__U568.out"], + ["const_term_U567.out","add_all__U569.in1"], + ["self.out","add_all__U569.out"], + ["mul_d0__U564.in0","coeff_0_U563.out"], + ["mul_d1__U566.in0","coeff_1_U565.out"], + ["self.d.0","mul_d0__U564.in1"], + ["self.d.1","mul_d1__U566.in1"] ] }, - "aff__U580":{ + "aff__U576":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U586":{ + "add_all__U582":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U587":{ + "add_all__U583":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U581":{ + "coeff_0_U577":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U583":{ + "coeff_1_U579":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U585":{ + "const_term_U581":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U582":{ + "mul_d0__U578":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U584":{ + "mul_d1__U580":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U582.out","add_all__U586.in0"], - ["mul_d1__U584.out","add_all__U586.in1"], - ["add_all__U587.in0","add_all__U586.out"], - ["const_term_U585.out","add_all__U587.in1"], - ["self.out","add_all__U587.out"], - ["mul_d0__U582.in0","coeff_0_U581.out"], - ["mul_d1__U584.in0","coeff_1_U583.out"], - ["self.d.0","mul_d0__U582.in1"], - ["self.d.1","mul_d1__U584.in1"] + ["mul_d0__U578.out","add_all__U582.in0"], + ["mul_d1__U580.out","add_all__U582.in1"], + ["add_all__U583.in0","add_all__U582.out"], + ["const_term_U581.out","add_all__U583.in1"], + ["self.out","add_all__U583.out"], + ["mul_d0__U578.in0","coeff_0_U577.out"], + ["mul_d1__U580.in0","coeff_1_U579.out"], + ["self.d.0","mul_d0__U578.in1"], + ["self.d.1","mul_d1__U580.in1"] ] }, - "aff__U595":{ + "aff__U58":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U601":{ + "add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U602":{ + "add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U596":{ + "coeff_0_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U598":{ + "coeff_1_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U600":{ + "const_term_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U597":{ + "mul_d0__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U599":{ + "mul_d1__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U597.out","add_all__U601.in0"], - ["mul_d1__U599.out","add_all__U601.in1"], - ["add_all__U602.in0","add_all__U601.out"], - ["const_term_U600.out","add_all__U602.in1"], - ["self.out","add_all__U602.out"], - ["mul_d0__U597.in0","coeff_0_U596.out"], - ["mul_d1__U599.in0","coeff_1_U598.out"], - ["self.d.0","mul_d0__U597.in1"], - ["self.d.1","mul_d1__U599.in1"] + ["mul_d0__U60.out","add_all__U64.in0"], + ["mul_d1__U62.out","add_all__U64.in1"], + ["add_all__U65.in0","add_all__U64.out"], + ["const_term_U63.out","add_all__U65.in1"], + ["self.out","add_all__U65.out"], + ["mul_d0__U60.in0","coeff_0_U59.out"], + ["mul_d1__U62.in0","coeff_1_U61.out"], + ["self.d.0","mul_d0__U60.in1"], + ["self.d.1","mul_d1__U62.in1"] ] }, - "aff__U610":{ + "aff__U590":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U616":{ + "add_all__U596":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U617":{ + "add_all__U597":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U611":{ + "coeff_0_U591":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U613":{ + "coeff_1_U593":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U615":{ + "const_term_U595":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U612":{ + "mul_d0__U592":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U614":{ + "mul_d1__U594":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U612.out","add_all__U616.in0"], - ["mul_d1__U614.out","add_all__U616.in1"], - ["add_all__U617.in0","add_all__U616.out"], - ["const_term_U615.out","add_all__U617.in1"], - ["self.out","add_all__U617.out"], - ["mul_d0__U612.in0","coeff_0_U611.out"], - ["mul_d1__U614.in0","coeff_1_U613.out"], - ["self.d.0","mul_d0__U612.in1"], - ["self.d.1","mul_d1__U614.in1"] + ["mul_d0__U592.out","add_all__U596.in0"], + ["mul_d1__U594.out","add_all__U596.in1"], + ["add_all__U597.in0","add_all__U596.out"], + ["const_term_U595.out","add_all__U597.in1"], + ["self.out","add_all__U597.out"], + ["mul_d0__U592.in0","coeff_0_U591.out"], + ["mul_d1__U594.in0","coeff_1_U593.out"], + ["self.d.0","mul_d0__U592.in1"], + ["self.d.1","mul_d1__U594.in1"] ] }, - "aff__U62":{ + "aff__U604":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U68":{ + "add_all__U610":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U69":{ + "add_all__U611":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U63":{ + "coeff_0_U605":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U65":{ + "coeff_1_U607":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U67":{ + "const_term_U609":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U64":{ + "mul_d0__U606":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U66":{ + "mul_d1__U608":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U64.out","add_all__U68.in0"], - ["mul_d1__U66.out","add_all__U68.in1"], - ["add_all__U69.in0","add_all__U68.out"], - ["const_term_U67.out","add_all__U69.in1"], - ["self.out","add_all__U69.out"], - ["mul_d0__U64.in0","coeff_0_U63.out"], - ["mul_d1__U66.in0","coeff_1_U65.out"], - ["self.d.0","mul_d0__U64.in1"], - ["self.d.1","mul_d1__U66.in1"] + ["mul_d0__U606.out","add_all__U610.in0"], + ["mul_d1__U608.out","add_all__U610.in1"], + ["add_all__U611.in0","add_all__U610.out"], + ["const_term_U609.out","add_all__U611.in1"], + ["self.out","add_all__U611.out"], + ["mul_d0__U606.in0","coeff_0_U605.out"], + ["mul_d1__U608.in0","coeff_1_U607.out"], + ["self.d.0","mul_d0__U606.in1"], + ["self.d.1","mul_d1__U608.in1"] ] }, - "aff__U625":{ + "aff__U618":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U631":{ + "add_all__U624":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U632":{ + "add_all__U625":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U626":{ + "coeff_0_U619":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U628":{ + "coeff_1_U621":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U630":{ + "const_term_U623":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U627":{ + "mul_d0__U620":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U629":{ + "mul_d1__U622":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U627.out","add_all__U631.in0"], - ["mul_d1__U629.out","add_all__U631.in1"], - ["add_all__U632.in0","add_all__U631.out"], - ["const_term_U630.out","add_all__U632.in1"], - ["self.out","add_all__U632.out"], - ["mul_d0__U627.in0","coeff_0_U626.out"], - ["mul_d1__U629.in0","coeff_1_U628.out"], - ["self.d.0","mul_d0__U627.in1"], - ["self.d.1","mul_d1__U629.in1"] + ["mul_d0__U620.out","add_all__U624.in0"], + ["mul_d1__U622.out","add_all__U624.in1"], + ["add_all__U625.in0","add_all__U624.out"], + ["const_term_U623.out","add_all__U625.in1"], + ["self.out","add_all__U625.out"], + ["mul_d0__U620.in0","coeff_0_U619.out"], + ["mul_d1__U622.in0","coeff_1_U621.out"], + ["self.d.0","mul_d0__U620.in1"], + ["self.d.1","mul_d1__U622.in1"] ] }, - "aff__U640":{ + "aff__U632":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U646":{ + "add_all__U638":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U647":{ + "add_all__U639":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U641":{ + "coeff_0_U633":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U643":{ + "coeff_1_U635":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U645":{ + "const_term_U637":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U642":{ + "mul_d0__U634":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U644":{ + "mul_d1__U636":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U642.out","add_all__U646.in0"], - ["mul_d1__U644.out","add_all__U646.in1"], - ["add_all__U647.in0","add_all__U646.out"], - ["const_term_U645.out","add_all__U647.in1"], - ["self.out","add_all__U647.out"], - ["mul_d0__U642.in0","coeff_0_U641.out"], - ["mul_d1__U644.in0","coeff_1_U643.out"], - ["self.d.0","mul_d0__U642.in1"], - ["self.d.1","mul_d1__U644.in1"] + ["mul_d0__U634.out","add_all__U638.in0"], + ["mul_d1__U636.out","add_all__U638.in1"], + ["add_all__U639.in0","add_all__U638.out"], + ["const_term_U637.out","add_all__U639.in1"], + ["self.out","add_all__U639.out"], + ["mul_d0__U634.in0","coeff_0_U633.out"], + ["mul_d1__U636.in0","coeff_1_U635.out"], + ["self.d.0","mul_d0__U634.in1"], + ["self.d.1","mul_d1__U636.in1"] ] }, - "aff__U655":{ + "aff__U646":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U661":{ + "add_all__U652":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U662":{ + "add_all__U653":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U656":{ + "coeff_0_U647":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U658":{ + "coeff_1_U649":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U660":{ + "const_term_U651":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U657":{ + "mul_d0__U648":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U659":{ + "mul_d1__U650":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U657.out","add_all__U661.in0"], - ["mul_d1__U659.out","add_all__U661.in1"], - ["add_all__U662.in0","add_all__U661.out"], - ["const_term_U660.out","add_all__U662.in1"], - ["self.out","add_all__U662.out"], - ["mul_d0__U657.in0","coeff_0_U656.out"], - ["mul_d1__U659.in0","coeff_1_U658.out"], - ["self.d.0","mul_d0__U657.in1"], - ["self.d.1","mul_d1__U659.in1"] + ["mul_d0__U648.out","add_all__U652.in0"], + ["mul_d1__U650.out","add_all__U652.in1"], + ["add_all__U653.in0","add_all__U652.out"], + ["const_term_U651.out","add_all__U653.in1"], + ["self.out","add_all__U653.out"], + ["mul_d0__U648.in0","coeff_0_U647.out"], + ["mul_d1__U650.in0","coeff_1_U649.out"], + ["self.d.0","mul_d0__U648.in1"], + ["self.d.1","mul_d1__U650.in1"] ] }, - "aff__U670":{ + "aff__U660":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U676":{ + "add_all__U666":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U677":{ + "add_all__U667":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U671":{ + "coeff_0_U661":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U673":{ + "coeff_1_U663":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U675":{ + "const_term_U665":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U672":{ + "mul_d0__U662":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U674":{ + "mul_d1__U664":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U672.out","add_all__U676.in0"], - ["mul_d1__U674.out","add_all__U676.in1"], - ["add_all__U677.in0","add_all__U676.out"], - ["const_term_U675.out","add_all__U677.in1"], - ["self.out","add_all__U677.out"], - ["mul_d0__U672.in0","coeff_0_U671.out"], - ["mul_d1__U674.in0","coeff_1_U673.out"], - ["self.d.0","mul_d0__U672.in1"], - ["self.d.1","mul_d1__U674.in1"] + ["mul_d0__U662.out","add_all__U666.in0"], + ["mul_d1__U664.out","add_all__U666.in1"], + ["add_all__U667.in0","add_all__U666.out"], + ["const_term_U665.out","add_all__U667.in1"], + ["self.out","add_all__U667.out"], + ["mul_d0__U662.in0","coeff_0_U661.out"], + ["mul_d1__U664.in0","coeff_1_U663.out"], + ["self.d.0","mul_d0__U662.in1"], + ["self.d.1","mul_d1__U664.in1"] ] }, - "aff__U685":{ + "aff__U674":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U691":{ + "add_all__U680":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U692":{ + "add_all__U681":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U686":{ + "coeff_0_U675":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U688":{ + "coeff_1_U677":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U690":{ + "const_term_U679":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U687":{ + "mul_d0__U676":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U689":{ + "mul_d1__U678":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U687.out","add_all__U691.in0"], - ["mul_d1__U689.out","add_all__U691.in1"], - ["add_all__U692.in0","add_all__U691.out"], - ["const_term_U690.out","add_all__U692.in1"], - ["self.out","add_all__U692.out"], - ["mul_d0__U687.in0","coeff_0_U686.out"], - ["mul_d1__U689.in0","coeff_1_U688.out"], - ["self.d.0","mul_d0__U687.in1"], - ["self.d.1","mul_d1__U689.in1"] + ["mul_d0__U676.out","add_all__U680.in0"], + ["mul_d1__U678.out","add_all__U680.in1"], + ["add_all__U681.in0","add_all__U680.out"], + ["const_term_U679.out","add_all__U681.in1"], + ["self.out","add_all__U681.out"], + ["mul_d0__U676.in0","coeff_0_U675.out"], + ["mul_d1__U678.in0","coeff_1_U677.out"], + ["self.d.0","mul_d0__U676.in1"], + ["self.d.1","mul_d1__U678.in1"] ] }, - "aff__U700":{ + "aff__U688":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U706":{ + "add_all__U694":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U707":{ + "add_all__U695":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U701":{ + "coeff_0_U689":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U703":{ + "coeff_1_U691":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U705":{ + "const_term_U693":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U702":{ + "mul_d0__U690":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U704":{ + "mul_d1__U692":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U702.out","add_all__U706.in0"], - ["mul_d1__U704.out","add_all__U706.in1"], - ["add_all__U707.in0","add_all__U706.out"], - ["const_term_U705.out","add_all__U707.in1"], - ["self.out","add_all__U707.out"], - ["mul_d0__U702.in0","coeff_0_U701.out"], - ["mul_d1__U704.in0","coeff_1_U703.out"], - ["self.d.0","mul_d0__U702.in1"], - ["self.d.1","mul_d1__U704.in1"] + ["mul_d0__U690.out","add_all__U694.in0"], + ["mul_d1__U692.out","add_all__U694.in1"], + ["add_all__U695.in0","add_all__U694.out"], + ["const_term_U693.out","add_all__U695.in1"], + ["self.out","add_all__U695.out"], + ["mul_d0__U690.in0","coeff_0_U689.out"], + ["mul_d1__U692.in0","coeff_1_U691.out"], + ["self.d.0","mul_d0__U690.in1"], + ["self.d.1","mul_d1__U692.in1"] ] }, - "aff__U715":{ + "aff__U702":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U721":{ + "add_all__U708":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U709":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, + "coeff_0_U703":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U705":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U707":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U704":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U706":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U704.out","add_all__U708.in0"], + ["mul_d1__U706.out","add_all__U708.in1"], + ["add_all__U709.in0","add_all__U708.out"], + ["const_term_U707.out","add_all__U709.in1"], + ["self.out","add_all__U709.out"], + ["mul_d0__U704.in0","coeff_0_U703.out"], + ["mul_d1__U706.in0","coeff_1_U705.out"], + ["self.d.0","mul_d0__U704.in1"], + ["self.d.1","mul_d1__U706.in1"] + ] + }, + "aff__U716":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ "add_all__U722":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U716":{ + "add_all__U723":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U717":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U718":{ + "coeff_1_U719":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U720":{ + "const_term_U721":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U717":{ + "mul_d0__U718":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U719":{ + "mul_d1__U720":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U717.out","add_all__U721.in0"], - ["mul_d1__U719.out","add_all__U721.in1"], - ["add_all__U722.in0","add_all__U721.out"], - ["const_term_U720.out","add_all__U722.in1"], - ["self.out","add_all__U722.out"], - ["mul_d0__U717.in0","coeff_0_U716.out"], - ["mul_d1__U719.in0","coeff_1_U718.out"], - ["self.d.0","mul_d0__U717.in1"], - ["self.d.1","mul_d1__U719.in1"] + ["mul_d0__U718.out","add_all__U722.in0"], + ["mul_d1__U720.out","add_all__U722.in1"], + ["add_all__U723.in0","add_all__U722.out"], + ["const_term_U721.out","add_all__U723.in1"], + ["self.out","add_all__U723.out"], + ["mul_d0__U718.in0","coeff_0_U717.out"], + ["mul_d1__U720.in0","coeff_1_U719.out"], + ["self.d.0","mul_d0__U718.in1"], + ["self.d.1","mul_d1__U720.in1"] + ] + }, + "aff__U72":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U78":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U79":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U73":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U75":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U77":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U74":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U76":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U74.out","add_all__U78.in0"], + ["mul_d1__U76.out","add_all__U78.in1"], + ["add_all__U79.in0","add_all__U78.out"], + ["const_term_U77.out","add_all__U79.in1"], + ["self.out","add_all__U79.out"], + ["mul_d0__U74.in0","coeff_0_U73.out"], + ["mul_d1__U76.in0","coeff_1_U75.out"], + ["self.d.0","mul_d0__U74.in1"], + ["self.d.1","mul_d1__U76.in1"] ] }, "aff__U730":{ @@ -4748,754 +4698,754 @@ ["self.d.1","mul_d1__U734.in1"] ] }, - "aff__U745":{ + "aff__U744":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U751":{ + "add_all__U750":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U752":{ + "add_all__U751":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U746":{ + "coeff_0_U745":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U748":{ + "coeff_1_U747":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U750":{ + "const_term_U749":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U747":{ + "mul_d0__U746":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U749":{ + "mul_d1__U748":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U747.out","add_all__U751.in0"], - ["mul_d1__U749.out","add_all__U751.in1"], - ["add_all__U752.in0","add_all__U751.out"], - ["const_term_U750.out","add_all__U752.in1"], - ["self.out","add_all__U752.out"], - ["mul_d0__U747.in0","coeff_0_U746.out"], - ["mul_d1__U749.in0","coeff_1_U748.out"], - ["self.d.0","mul_d0__U747.in1"], - ["self.d.1","mul_d1__U749.in1"] + ["mul_d0__U746.out","add_all__U750.in0"], + ["mul_d1__U748.out","add_all__U750.in1"], + ["add_all__U751.in0","add_all__U750.out"], + ["const_term_U749.out","add_all__U751.in1"], + ["self.out","add_all__U751.out"], + ["mul_d0__U746.in0","coeff_0_U745.out"], + ["mul_d1__U748.in0","coeff_1_U747.out"], + ["self.d.0","mul_d0__U746.in1"], + ["self.d.1","mul_d1__U748.in1"] ] }, - "aff__U760":{ + "aff__U758":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U766":{ + "add_all__U764":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U767":{ + "add_all__U765":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U761":{ + "coeff_0_U759":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U763":{ + "coeff_1_U761":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U765":{ + "const_term_U763":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U762":{ + "mul_d0__U760":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U764":{ + "mul_d1__U762":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U762.out","add_all__U766.in0"], - ["mul_d1__U764.out","add_all__U766.in1"], - ["add_all__U767.in0","add_all__U766.out"], - ["const_term_U765.out","add_all__U767.in1"], - ["self.out","add_all__U767.out"], - ["mul_d0__U762.in0","coeff_0_U761.out"], - ["mul_d1__U764.in0","coeff_1_U763.out"], - ["self.d.0","mul_d0__U762.in1"], - ["self.d.1","mul_d1__U764.in1"] + ["mul_d0__U760.out","add_all__U764.in0"], + ["mul_d1__U762.out","add_all__U764.in1"], + ["add_all__U765.in0","add_all__U764.out"], + ["const_term_U763.out","add_all__U765.in1"], + ["self.out","add_all__U765.out"], + ["mul_d0__U760.in0","coeff_0_U759.out"], + ["mul_d1__U762.in0","coeff_1_U761.out"], + ["self.d.0","mul_d0__U760.in1"], + ["self.d.1","mul_d1__U762.in1"] ] }, - "aff__U77":{ + "aff__U772":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U83":{ + "add_all__U778":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U84":{ + "add_all__U779":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U78":{ + "coeff_0_U773":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U80":{ + "coeff_1_U775":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U82":{ + "const_term_U777":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U79":{ + "mul_d0__U774":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U81":{ + "mul_d1__U776":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U79.out","add_all__U83.in0"], - ["mul_d1__U81.out","add_all__U83.in1"], - ["add_all__U84.in0","add_all__U83.out"], - ["const_term_U82.out","add_all__U84.in1"], - ["self.out","add_all__U84.out"], - ["mul_d0__U79.in0","coeff_0_U78.out"], - ["mul_d1__U81.in0","coeff_1_U80.out"], - ["self.d.0","mul_d0__U79.in1"], - ["self.d.1","mul_d1__U81.in1"] + ["mul_d0__U774.out","add_all__U778.in0"], + ["mul_d1__U776.out","add_all__U778.in1"], + ["add_all__U779.in0","add_all__U778.out"], + ["const_term_U777.out","add_all__U779.in1"], + ["self.out","add_all__U779.out"], + ["mul_d0__U774.in0","coeff_0_U773.out"], + ["mul_d1__U776.in0","coeff_1_U775.out"], + ["self.d.0","mul_d0__U774.in1"], + ["self.d.1","mul_d1__U776.in1"] ] }, - "aff__U775":{ + "aff__U786":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U781":{ + "add_all__U792":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U782":{ + "add_all__U793":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U776":{ + "coeff_0_U787":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U778":{ + "coeff_1_U789":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U780":{ + "const_term_U791":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U777":{ + "mul_d0__U788":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U779":{ + "mul_d1__U790":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U777.out","add_all__U781.in0"], - ["mul_d1__U779.out","add_all__U781.in1"], - ["add_all__U782.in0","add_all__U781.out"], - ["const_term_U780.out","add_all__U782.in1"], - ["self.out","add_all__U782.out"], - ["mul_d0__U777.in0","coeff_0_U776.out"], - ["mul_d1__U779.in0","coeff_1_U778.out"], - ["self.d.0","mul_d0__U777.in1"], - ["self.d.1","mul_d1__U779.in1"] + ["mul_d0__U788.out","add_all__U792.in0"], + ["mul_d1__U790.out","add_all__U792.in1"], + ["add_all__U793.in0","add_all__U792.out"], + ["const_term_U791.out","add_all__U793.in1"], + ["self.out","add_all__U793.out"], + ["mul_d0__U788.in0","coeff_0_U787.out"], + ["mul_d1__U790.in0","coeff_1_U789.out"], + ["self.d.0","mul_d0__U788.in1"], + ["self.d.1","mul_d1__U790.in1"] ] }, - "aff__U790":{ + "aff__U800":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U796":{ + "add_all__U806":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U797":{ + "add_all__U807":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U791":{ + "coeff_0_U801":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U793":{ + "coeff_1_U803":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U795":{ + "const_term_U805":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U792":{ + "mul_d0__U802":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U794":{ + "mul_d1__U804":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U792.out","add_all__U796.in0"], - ["mul_d1__U794.out","add_all__U796.in1"], - ["add_all__U797.in0","add_all__U796.out"], - ["const_term_U795.out","add_all__U797.in1"], - ["self.out","add_all__U797.out"], - ["mul_d0__U792.in0","coeff_0_U791.out"], - ["mul_d1__U794.in0","coeff_1_U793.out"], - ["self.d.0","mul_d0__U792.in1"], - ["self.d.1","mul_d1__U794.in1"] + ["mul_d0__U802.out","add_all__U806.in0"], + ["mul_d1__U804.out","add_all__U806.in1"], + ["add_all__U807.in0","add_all__U806.out"], + ["const_term_U805.out","add_all__U807.in1"], + ["self.out","add_all__U807.out"], + ["mul_d0__U802.in0","coeff_0_U801.out"], + ["mul_d1__U804.in0","coeff_1_U803.out"], + ["self.d.0","mul_d0__U802.in1"], + ["self.d.1","mul_d1__U804.in1"] ] }, - "aff__U805":{ + "aff__U814":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U811":{ + "add_all__U820":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U812":{ + "add_all__U821":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U806":{ + "coeff_0_U815":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U808":{ + "coeff_1_U817":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U810":{ + "const_term_U819":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U807":{ + "mul_d0__U816":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U809":{ + "mul_d1__U818":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U807.out","add_all__U811.in0"], - ["mul_d1__U809.out","add_all__U811.in1"], - ["add_all__U812.in0","add_all__U811.out"], - ["const_term_U810.out","add_all__U812.in1"], - ["self.out","add_all__U812.out"], - ["mul_d0__U807.in0","coeff_0_U806.out"], - ["mul_d1__U809.in0","coeff_1_U808.out"], - ["self.d.0","mul_d0__U807.in1"], - ["self.d.1","mul_d1__U809.in1"] + ["mul_d0__U816.out","add_all__U820.in0"], + ["mul_d1__U818.out","add_all__U820.in1"], + ["add_all__U821.in0","add_all__U820.out"], + ["const_term_U819.out","add_all__U821.in1"], + ["self.out","add_all__U821.out"], + ["mul_d0__U816.in0","coeff_0_U815.out"], + ["mul_d1__U818.in0","coeff_1_U817.out"], + ["self.d.0","mul_d0__U816.in1"], + ["self.d.1","mul_d1__U818.in1"] ] }, - "aff__U820":{ + "aff__U828":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U826":{ + "add_all__U834":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U827":{ + "add_all__U835":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U821":{ + "coeff_0_U829":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U823":{ + "coeff_1_U831":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U825":{ + "const_term_U833":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U822":{ + "mul_d0__U830":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U824":{ + "mul_d1__U832":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U822.out","add_all__U826.in0"], - ["mul_d1__U824.out","add_all__U826.in1"], - ["add_all__U827.in0","add_all__U826.out"], - ["const_term_U825.out","add_all__U827.in1"], - ["self.out","add_all__U827.out"], - ["mul_d0__U822.in0","coeff_0_U821.out"], - ["mul_d1__U824.in0","coeff_1_U823.out"], - ["self.d.0","mul_d0__U822.in1"], - ["self.d.1","mul_d1__U824.in1"] + ["mul_d0__U830.out","add_all__U834.in0"], + ["mul_d1__U832.out","add_all__U834.in1"], + ["add_all__U835.in0","add_all__U834.out"], + ["const_term_U833.out","add_all__U835.in1"], + ["self.out","add_all__U835.out"], + ["mul_d0__U830.in0","coeff_0_U829.out"], + ["mul_d1__U832.in0","coeff_1_U831.out"], + ["self.d.0","mul_d0__U830.in1"], + ["self.d.1","mul_d1__U832.in1"] ] }, - "aff__U835":{ + "aff__U842":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U841":{ + "add_all__U848":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U842":{ + "add_all__U849":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U836":{ + "coeff_0_U843":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U838":{ + "coeff_1_U845":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U840":{ + "const_term_U847":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U837":{ + "mul_d0__U844":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U839":{ + "mul_d1__U846":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U837.out","add_all__U841.in0"], - ["mul_d1__U839.out","add_all__U841.in1"], - ["add_all__U842.in0","add_all__U841.out"], - ["const_term_U840.out","add_all__U842.in1"], - ["self.out","add_all__U842.out"], - ["mul_d0__U837.in0","coeff_0_U836.out"], - ["mul_d1__U839.in0","coeff_1_U838.out"], - ["self.d.0","mul_d0__U837.in1"], - ["self.d.1","mul_d1__U839.in1"] + ["mul_d0__U844.out","add_all__U848.in0"], + ["mul_d1__U846.out","add_all__U848.in1"], + ["add_all__U849.in0","add_all__U848.out"], + ["const_term_U847.out","add_all__U849.in1"], + ["self.out","add_all__U849.out"], + ["mul_d0__U844.in0","coeff_0_U843.out"], + ["mul_d1__U846.in0","coeff_1_U845.out"], + ["self.d.0","mul_d0__U844.in1"], + ["self.d.1","mul_d1__U846.in1"] ] }, - "aff__U850":{ + "aff__U856":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U856":{ + "add_all__U862":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U857":{ + "add_all__U863":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U851":{ + "coeff_0_U857":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U853":{ + "coeff_1_U859":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U855":{ + "const_term_U861":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U852":{ + "mul_d0__U858":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U854":{ + "mul_d1__U860":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U852.out","add_all__U856.in0"], - ["mul_d1__U854.out","add_all__U856.in1"], - ["add_all__U857.in0","add_all__U856.out"], - ["const_term_U855.out","add_all__U857.in1"], - ["self.out","add_all__U857.out"], - ["mul_d0__U852.in0","coeff_0_U851.out"], - ["mul_d1__U854.in0","coeff_1_U853.out"], - ["self.d.0","mul_d0__U852.in1"], - ["self.d.1","mul_d1__U854.in1"] + ["mul_d0__U858.out","add_all__U862.in0"], + ["mul_d1__U860.out","add_all__U862.in1"], + ["add_all__U863.in0","add_all__U862.out"], + ["const_term_U861.out","add_all__U863.in1"], + ["self.out","add_all__U863.out"], + ["mul_d0__U858.in0","coeff_0_U857.out"], + ["mul_d1__U860.in0","coeff_1_U859.out"], + ["self.d.0","mul_d0__U858.in1"], + ["self.d.1","mul_d1__U860.in1"] ] }, - "aff__U865":{ + "aff__U86":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U871":{ + "add_all__U92":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U872":{ + "add_all__U93":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U866":{ + "coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U868":{ + "coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U870":{ + "const_term_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U867":{ + "mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U869":{ + "mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U867.out","add_all__U871.in0"], - ["mul_d1__U869.out","add_all__U871.in1"], - ["add_all__U872.in0","add_all__U871.out"], - ["const_term_U870.out","add_all__U872.in1"], - ["self.out","add_all__U872.out"], - ["mul_d0__U867.in0","coeff_0_U866.out"], - ["mul_d1__U869.in0","coeff_1_U868.out"], - ["self.d.0","mul_d0__U867.in1"], - ["self.d.1","mul_d1__U869.in1"] + ["mul_d0__U88.out","add_all__U92.in0"], + ["mul_d1__U90.out","add_all__U92.in1"], + ["add_all__U93.in0","add_all__U92.out"], + ["const_term_U91.out","add_all__U93.in1"], + ["self.out","add_all__U93.out"], + ["mul_d0__U88.in0","coeff_0_U87.out"], + ["mul_d1__U90.in0","coeff_1_U89.out"], + ["self.d.0","mul_d0__U88.in1"], + ["self.d.1","mul_d1__U90.in1"] ] }, - "aff__U880":{ + "aff__U870":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U886":{ + "add_all__U876":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U887":{ + "add_all__U877":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U881":{ + "coeff_0_U871":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U883":{ + "coeff_1_U873":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U885":{ + "const_term_U875":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U882":{ + "mul_d0__U872":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U884":{ + "mul_d1__U874":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U882.out","add_all__U886.in0"], - ["mul_d1__U884.out","add_all__U886.in1"], - ["add_all__U887.in0","add_all__U886.out"], - ["const_term_U885.out","add_all__U887.in1"], - ["self.out","add_all__U887.out"], - ["mul_d0__U882.in0","coeff_0_U881.out"], - ["mul_d1__U884.in0","coeff_1_U883.out"], - ["self.d.0","mul_d0__U882.in1"], - ["self.d.1","mul_d1__U884.in1"] + ["mul_d0__U872.out","add_all__U876.in0"], + ["mul_d1__U874.out","add_all__U876.in1"], + ["add_all__U877.in0","add_all__U876.out"], + ["const_term_U875.out","add_all__U877.in1"], + ["self.out","add_all__U877.out"], + ["mul_d0__U872.in0","coeff_0_U871.out"], + ["mul_d1__U874.in0","coeff_1_U873.out"], + ["self.d.0","mul_d0__U872.in1"], + ["self.d.1","mul_d1__U874.in1"] ] }, - "aff__U895":{ + "aff__U884":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U901":{ + "add_all__U890":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U902":{ + "add_all__U891":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U896":{ + "coeff_0_U885":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U898":{ + "coeff_1_U887":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U900":{ + "const_term_U889":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U897":{ + "mul_d0__U886":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U899":{ + "mul_d1__U888":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U897.out","add_all__U901.in0"], - ["mul_d1__U899.out","add_all__U901.in1"], - ["add_all__U902.in0","add_all__U901.out"], - ["const_term_U900.out","add_all__U902.in1"], - ["self.out","add_all__U902.out"], - ["mul_d0__U897.in0","coeff_0_U896.out"], - ["mul_d1__U899.in0","coeff_1_U898.out"], - ["self.d.0","mul_d0__U897.in1"], - ["self.d.1","mul_d1__U899.in1"] + ["mul_d0__U886.out","add_all__U890.in0"], + ["mul_d1__U888.out","add_all__U890.in1"], + ["add_all__U891.in0","add_all__U890.out"], + ["const_term_U889.out","add_all__U891.in1"], + ["self.out","add_all__U891.out"], + ["mul_d0__U886.in0","coeff_0_U885.out"], + ["mul_d1__U888.in0","coeff_1_U887.out"], + ["self.d.0","mul_d0__U886.in1"], + ["self.d.1","mul_d1__U888.in1"] ] }, - "aff__U910":{ + "aff__U898":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U916":{ + "add_all__U904":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U917":{ + "add_all__U905":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U911":{ + "coeff_0_U899":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U913":{ + "coeff_1_U901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U915":{ + "const_term_U903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U912":{ + "mul_d0__U900":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U914":{ + "mul_d1__U902":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U912.out","add_all__U916.in0"], - ["mul_d1__U914.out","add_all__U916.in1"], - ["add_all__U917.in0","add_all__U916.out"], - ["const_term_U915.out","add_all__U917.in1"], - ["self.out","add_all__U917.out"], - ["mul_d0__U912.in0","coeff_0_U911.out"], - ["mul_d1__U914.in0","coeff_1_U913.out"], - ["self.d.0","mul_d0__U912.in1"], - ["self.d.1","mul_d1__U914.in1"] + ["mul_d0__U900.out","add_all__U904.in0"], + ["mul_d1__U902.out","add_all__U904.in1"], + ["add_all__U905.in0","add_all__U904.out"], + ["const_term_U903.out","add_all__U905.in1"], + ["self.out","add_all__U905.out"], + ["mul_d0__U900.in0","coeff_0_U899.out"], + ["mul_d1__U902.in0","coeff_1_U901.out"], + ["self.d.0","mul_d0__U900.in1"], + ["self.d.1","mul_d1__U902.in1"] ] }, - "aff__U92":{ + "aff__U912":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U98":{ + "add_all__U918":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U99":{ + "add_all__U919":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U93":{ + "coeff_0_U913":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U95":{ + "coeff_1_U915":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U97":{ + "const_term_U917":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U94":{ + "mul_d0__U914":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U96":{ + "mul_d1__U916":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U94.out","add_all__U98.in0"], - ["mul_d1__U96.out","add_all__U98.in1"], - ["add_all__U99.in0","add_all__U98.out"], - ["const_term_U97.out","add_all__U99.in1"], - ["self.out","add_all__U99.out"], - ["mul_d0__U94.in0","coeff_0_U93.out"], - ["mul_d1__U96.in0","coeff_1_U95.out"], - ["self.d.0","mul_d0__U94.in1"], - ["self.d.1","mul_d1__U96.in1"] + ["mul_d0__U914.out","add_all__U918.in0"], + ["mul_d1__U916.out","add_all__U918.in1"], + ["add_all__U919.in0","add_all__U918.out"], + ["const_term_U917.out","add_all__U919.in1"], + ["self.out","add_all__U919.out"], + ["mul_d0__U914.in0","coeff_0_U913.out"], + ["mul_d1__U916.in0","coeff_1_U915.out"], + ["self.d.0","mul_d0__U914.in1"], + ["self.d.1","mul_d1__U916.in1"] ] }, - "aff__U925":{ + "aff__U926":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U931":{ + "add_all__U932":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U932":{ + "add_all__U933":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U926":{ + "coeff_0_U927":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U928":{ + "coeff_1_U929":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U930":{ + "const_term_U931":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U927":{ + "mul_d0__U928":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U929":{ + "mul_d1__U930":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U927.out","add_all__U931.in0"], - ["mul_d1__U929.out","add_all__U931.in1"], - ["add_all__U932.in0","add_all__U931.out"], - ["const_term_U930.out","add_all__U932.in1"], - ["self.out","add_all__U932.out"], - ["mul_d0__U927.in0","coeff_0_U926.out"], - ["mul_d1__U929.in0","coeff_1_U928.out"], - ["self.d.0","mul_d0__U927.in1"], - ["self.d.1","mul_d1__U929.in1"] + ["mul_d0__U928.out","add_all__U932.in0"], + ["mul_d1__U930.out","add_all__U932.in1"], + ["add_all__U933.in0","add_all__U932.out"], + ["const_term_U931.out","add_all__U933.in1"], + ["self.out","add_all__U933.out"], + ["mul_d0__U928.in0","coeff_0_U927.out"], + ["mul_d1__U930.in0","coeff_1_U929.out"], + ["self.d.0","mul_d0__U928.in1"], + ["self.d.1","mul_d1__U930.in1"] ] }, "aff__U940":{ @@ -5548,154 +5498,204 @@ ["self.d.1","mul_d1__U944.in1"] ] }, - "aff__U955":{ + "aff__U954":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ + "add_all__U960":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, "add_all__U961":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U962":{ + "coeff_0_U955":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U957":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "const_term_U959":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "mul_d0__U956":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U958":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U956.out","add_all__U960.in0"], + ["mul_d1__U958.out","add_all__U960.in1"], + ["add_all__U961.in0","add_all__U960.out"], + ["const_term_U959.out","add_all__U961.in1"], + ["self.out","add_all__U961.out"], + ["mul_d0__U956.in0","coeff_0_U955.out"], + ["mul_d1__U958.in0","coeff_1_U957.out"], + ["self.d.0","mul_d0__U956.in1"], + ["self.d.1","mul_d1__U958.in1"] + ] + }, + "aff__U968":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",2,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U974":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U975":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U956":{ + "coeff_0_U969":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U958":{ + "coeff_1_U971":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U960":{ + "const_term_U973":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U957":{ + "mul_d0__U970":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U959":{ + "mul_d1__U972":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U957.out","add_all__U961.in0"], - ["mul_d1__U959.out","add_all__U961.in1"], - ["add_all__U962.in0","add_all__U961.out"], - ["const_term_U960.out","add_all__U962.in1"], - ["self.out","add_all__U962.out"], - ["mul_d0__U957.in0","coeff_0_U956.out"], - ["mul_d1__U959.in0","coeff_1_U958.out"], - ["self.d.0","mul_d0__U957.in1"], - ["self.d.1","mul_d1__U959.in1"] + ["mul_d0__U970.out","add_all__U974.in0"], + ["mul_d1__U972.out","add_all__U974.in1"], + ["add_all__U975.in0","add_all__U974.out"], + ["const_term_U973.out","add_all__U975.in1"], + ["self.out","add_all__U975.out"], + ["mul_d0__U970.in0","coeff_0_U969.out"], + ["mul_d1__U972.in0","coeff_1_U971.out"], + ["self.d.0","mul_d0__U970.in1"], + ["self.d.1","mul_d1__U972.in1"] ] }, - "aff__U970":{ + "aff__U982":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U976":{ + "add_all__U988":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U977":{ + "add_all__U989":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U971":{ + "coeff_0_U983":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U973":{ + "coeff_1_U985":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U975":{ + "const_term_U987":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U972":{ + "mul_d0__U984":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U974":{ + "mul_d1__U986":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U972.out","add_all__U976.in0"], - ["mul_d1__U974.out","add_all__U976.in1"], - ["add_all__U977.in0","add_all__U976.out"], - ["const_term_U975.out","add_all__U977.in1"], - ["self.out","add_all__U977.out"], - ["mul_d0__U972.in0","coeff_0_U971.out"], - ["mul_d1__U974.in0","coeff_1_U973.out"], - ["self.d.0","mul_d0__U972.in1"], - ["self.d.1","mul_d1__U974.in1"] + ["mul_d0__U984.out","add_all__U988.in0"], + ["mul_d1__U986.out","add_all__U988.in1"], + ["add_all__U989.in0","add_all__U988.out"], + ["const_term_U987.out","add_all__U989.in1"], + ["self.out","add_all__U989.out"], + ["mul_d0__U984.in0","coeff_0_U983.out"], + ["mul_d1__U986.in0","coeff_1_U985.out"], + ["self.d.0","mul_d0__U984.in1"], + ["self.d.1","mul_d1__U986.in1"] ] }, - "aff__U985":{ + "aff__U996":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U991":{ + "add_all__U1002":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U992":{ + "add_all__U1003":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U986":{ + "coeff_0_U997":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U988":{ + "coeff_1_U999":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U990":{ + "const_term_U1001":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "mul_d0__U987":{ + "mul_d0__U998":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U989":{ + "mul_d1__U1000":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U987.out","add_all__U991.in0"], - ["mul_d1__U989.out","add_all__U991.in1"], - ["add_all__U992.in0","add_all__U991.out"], - ["const_term_U990.out","add_all__U992.in1"], - ["self.out","add_all__U992.out"], - ["mul_d0__U987.in0","coeff_0_U986.out"], - ["mul_d1__U989.in0","coeff_1_U988.out"], - ["self.d.0","mul_d0__U987.in1"], - ["self.d.1","mul_d1__U989.in1"] + ["mul_d0__U998.out","add_all__U1002.in0"], + ["mul_d1__U1000.out","add_all__U1002.in1"], + ["add_all__U1003.in0","add_all__U1002.out"], + ["const_term_U1001.out","add_all__U1003.in1"], + ["self.out","add_all__U1003.out"], + ["mul_d0__U998.in0","coeff_0_U997.out"], + ["mul_d1__U1000.in0","coeff_1_U999.out"], + ["self.d.0","mul_d0__U998.in1"], + ["self.d.1","mul_d1__U1000.in1"] ] }, "affine_controller__U1":{ @@ -6009,7 +6009,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1014":{ + "affine_controller__U1009":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6017,49 +6017,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1023":{ + "_U1018":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U10231":{ + "_U10181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1024":{ + "_U1019":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1021":{ + "affine_func$add_all__U1016":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1022":{ + "affine_func$add_all__U1017":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1016":{ + "affine_func$coeff_0_U1011":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1018":{ + "affine_func$coeff_1_U1013":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1020":{ + "affine_func$const_term_U1015":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1017":{ + "affine_func$mul_d0__U1012":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1019":{ + "affine_func$mul_d1__U1014":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6123,12 +6123,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1025$c0_lutcnst":{ + "d_0_am__U1020$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1025$lut$lut":{ + "d_0_am__U1020$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6247,18 +6247,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1023.out"], - ["d_1_inc.in1","_U10231.out"], - ["cmp_time.in1","_U1024.out"], - ["affine_func$mul_d0__U1017.out","affine_func$add_all__U1021.in0"], - ["affine_func$mul_d1__U1019.out","affine_func$add_all__U1021.in1"], - ["affine_func$add_all__U1022.in0","affine_func$add_all__U1021.out"], - ["affine_func$const_term_U1020.out","affine_func$add_all__U1022.in1"], - ["time_diff.in0","affine_func$add_all__U1022.out"], - ["affine_func$mul_d0__U1017.in0","affine_func$coeff_0_U1016.out"], - ["affine_func$mul_d1__U1019.in0","affine_func$coeff_1_U1018.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1017.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1019.in1"], + ["d_0_inc.in1","_U1018.out"], + ["d_1_inc.in1","_U10181.out"], + ["cmp_time.in1","_U1019.out"], + ["affine_func$mul_d0__U1012.out","affine_func$add_all__U1016.in0"], + ["affine_func$mul_d1__U1014.out","affine_func$add_all__U1016.in1"], + ["affine_func$add_all__U1017.in0","affine_func$add_all__U1016.out"], + ["affine_func$const_term_U1015.out","affine_func$add_all__U1017.in1"], + ["time_diff.in0","affine_func$add_all__U1017.out"], + ["affine_func$mul_d0__U1012.in0","affine_func$coeff_0_U1011.out"], + ["affine_func$mul_d1__U1014.in0","affine_func$coeff_1_U1013.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1012.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1014.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6281,10 +6281,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1025$lut$lut.bit.in.2","d_0_am__U1025$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1025$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1025$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1025$lut$lut.bit.out"], + ["d_0_am__U1020$lut$lut.bit.in.2","d_0_am__U1020$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1020$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1020$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1020$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6320,7 +6320,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1029":{ + "affine_controller__U1023":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6328,49 +6328,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1038":{ + "_U1032":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U10381":{ + "_U10321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1039":{ + "_U1033":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1036":{ + "affine_func$add_all__U1030":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1037":{ + "affine_func$add_all__U1031":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1031":{ + "affine_func$coeff_0_U1025":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1033":{ + "affine_func$coeff_1_U1027":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1035":{ + "affine_func$const_term_U1029":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1032":{ + "affine_func$mul_d0__U1026":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1034":{ + "affine_func$mul_d1__U1028":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6434,12 +6434,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1040$c0_lutcnst":{ + "d_0_am__U1034$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1040$lut$lut":{ + "d_0_am__U1034$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6558,18 +6558,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1038.out"], - ["d_1_inc.in1","_U10381.out"], - ["cmp_time.in1","_U1039.out"], - ["affine_func$mul_d0__U1032.out","affine_func$add_all__U1036.in0"], - ["affine_func$mul_d1__U1034.out","affine_func$add_all__U1036.in1"], - ["affine_func$add_all__U1037.in0","affine_func$add_all__U1036.out"], - ["affine_func$const_term_U1035.out","affine_func$add_all__U1037.in1"], - ["time_diff.in0","affine_func$add_all__U1037.out"], - ["affine_func$mul_d0__U1032.in0","affine_func$coeff_0_U1031.out"], - ["affine_func$mul_d1__U1034.in0","affine_func$coeff_1_U1033.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1032.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1034.in1"], + ["d_0_inc.in1","_U1032.out"], + ["d_1_inc.in1","_U10321.out"], + ["cmp_time.in1","_U1033.out"], + ["affine_func$mul_d0__U1026.out","affine_func$add_all__U1030.in0"], + ["affine_func$mul_d1__U1028.out","affine_func$add_all__U1030.in1"], + ["affine_func$add_all__U1031.in0","affine_func$add_all__U1030.out"], + ["affine_func$const_term_U1029.out","affine_func$add_all__U1031.in1"], + ["time_diff.in0","affine_func$add_all__U1031.out"], + ["affine_func$mul_d0__U1026.in0","affine_func$coeff_0_U1025.out"], + ["affine_func$mul_d1__U1028.in0","affine_func$coeff_1_U1027.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1026.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1028.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6592,10 +6592,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1040$lut$lut.bit.in.2","d_0_am__U1040$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1040$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1040$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1040$lut$lut.bit.out"], + ["d_0_am__U1034$lut$lut.bit.in.2","d_0_am__U1034$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1034$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1034$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1034$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6631,7 +6631,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1044":{ + "affine_controller__U1037":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6639,49 +6639,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1053":{ + "_U1046":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U10531":{ + "_U10461":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1054":{ + "_U1047":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1051":{ + "affine_func$add_all__U1044":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1052":{ + "affine_func$add_all__U1045":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1046":{ + "affine_func$coeff_0_U1039":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1048":{ + "affine_func$coeff_1_U1041":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1050":{ + "affine_func$const_term_U1043":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1047":{ + "affine_func$mul_d0__U1040":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1049":{ + "affine_func$mul_d1__U1042":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6745,12 +6745,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1055$c0_lutcnst":{ + "d_0_am__U1048$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1055$lut$lut":{ + "d_0_am__U1048$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6869,18 +6869,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1053.out"], - ["d_1_inc.in1","_U10531.out"], - ["cmp_time.in1","_U1054.out"], - ["affine_func$mul_d0__U1047.out","affine_func$add_all__U1051.in0"], - ["affine_func$mul_d1__U1049.out","affine_func$add_all__U1051.in1"], - ["affine_func$add_all__U1052.in0","affine_func$add_all__U1051.out"], - ["affine_func$const_term_U1050.out","affine_func$add_all__U1052.in1"], - ["time_diff.in0","affine_func$add_all__U1052.out"], - ["affine_func$mul_d0__U1047.in0","affine_func$coeff_0_U1046.out"], - ["affine_func$mul_d1__U1049.in0","affine_func$coeff_1_U1048.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1047.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1049.in1"], + ["d_0_inc.in1","_U1046.out"], + ["d_1_inc.in1","_U10461.out"], + ["cmp_time.in1","_U1047.out"], + ["affine_func$mul_d0__U1040.out","affine_func$add_all__U1044.in0"], + ["affine_func$mul_d1__U1042.out","affine_func$add_all__U1044.in1"], + ["affine_func$add_all__U1045.in0","affine_func$add_all__U1044.out"], + ["affine_func$const_term_U1043.out","affine_func$add_all__U1045.in1"], + ["time_diff.in0","affine_func$add_all__U1045.out"], + ["affine_func$mul_d0__U1040.in0","affine_func$coeff_0_U1039.out"], + ["affine_func$mul_d1__U1042.in0","affine_func$coeff_1_U1041.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1040.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1042.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6903,10 +6903,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1055$lut$lut.bit.in.2","d_0_am__U1055$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1055$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1055$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1055$lut$lut.bit.out"], + ["d_0_am__U1048$lut$lut.bit.in.2","d_0_am__U1048$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1048$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1048$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1048$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6942,7 +6942,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1059":{ + "affine_controller__U1051":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6950,49 +6950,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1068":{ + "_U1060":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U10681":{ + "_U10601":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1069":{ + "_U1061":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1066":{ + "affine_func$add_all__U1058":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1067":{ + "affine_func$add_all__U1059":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1061":{ + "affine_func$coeff_0_U1053":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1063":{ + "affine_func$coeff_1_U1055":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1065":{ + "affine_func$const_term_U1057":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1062":{ + "affine_func$mul_d0__U1054":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1064":{ + "affine_func$mul_d1__U1056":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7056,12 +7056,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1070$c0_lutcnst":{ + "d_0_am__U1062$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1070$lut$lut":{ + "d_0_am__U1062$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7180,18 +7180,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1068.out"], - ["d_1_inc.in1","_U10681.out"], - ["cmp_time.in1","_U1069.out"], - ["affine_func$mul_d0__U1062.out","affine_func$add_all__U1066.in0"], - ["affine_func$mul_d1__U1064.out","affine_func$add_all__U1066.in1"], - ["affine_func$add_all__U1067.in0","affine_func$add_all__U1066.out"], - ["affine_func$const_term_U1065.out","affine_func$add_all__U1067.in1"], - ["time_diff.in0","affine_func$add_all__U1067.out"], - ["affine_func$mul_d0__U1062.in0","affine_func$coeff_0_U1061.out"], - ["affine_func$mul_d1__U1064.in0","affine_func$coeff_1_U1063.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1062.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1064.in1"], + ["d_0_inc.in1","_U1060.out"], + ["d_1_inc.in1","_U10601.out"], + ["cmp_time.in1","_U1061.out"], + ["affine_func$mul_d0__U1054.out","affine_func$add_all__U1058.in0"], + ["affine_func$mul_d1__U1056.out","affine_func$add_all__U1058.in1"], + ["affine_func$add_all__U1059.in0","affine_func$add_all__U1058.out"], + ["affine_func$const_term_U1057.out","affine_func$add_all__U1059.in1"], + ["time_diff.in0","affine_func$add_all__U1059.out"], + ["affine_func$mul_d0__U1054.in0","affine_func$coeff_0_U1053.out"], + ["affine_func$mul_d1__U1056.in0","affine_func$coeff_1_U1055.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1054.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1056.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -7214,10 +7214,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1070$lut$lut.bit.in.2","d_0_am__U1070$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1070$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1070$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1070$lut$lut.bit.out"], + ["d_0_am__U1062$lut$lut.bit.in.2","d_0_am__U1062$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1062$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1062$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1062$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7253,7 +7253,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U106":{ + "affine_controller__U1065":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -7261,49 +7261,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U115":{ + "_U1074":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1151":{ + "_U10741":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U116":{ + "_U1075":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U113":{ + "affine_func$add_all__U1072":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U114":{ + "affine_func$add_all__U1073":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U108":{ + "affine_func$coeff_0_U1067":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U110":{ + "affine_func$coeff_1_U1069":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U112":{ + "affine_func$const_term_U1071":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U109":{ + "affine_func$mul_d0__U1068":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U111":{ + "affine_func$mul_d1__U1070":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7367,12 +7367,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U117$c0_lutcnst":{ + "d_0_am__U1076$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U117$lut$lut":{ + "d_0_am__U1076$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7491,18 +7491,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U115.out"], - ["d_1_inc.in1","_U1151.out"], - ["cmp_time.in1","_U116.out"], - ["affine_func$mul_d0__U109.out","affine_func$add_all__U113.in0"], - ["affine_func$mul_d1__U111.out","affine_func$add_all__U113.in1"], - ["affine_func$add_all__U114.in0","affine_func$add_all__U113.out"], - ["affine_func$const_term_U112.out","affine_func$add_all__U114.in1"], - ["time_diff.in0","affine_func$add_all__U114.out"], - ["affine_func$mul_d0__U109.in0","affine_func$coeff_0_U108.out"], - ["affine_func$mul_d1__U111.in0","affine_func$coeff_1_U110.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U109.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U111.in1"], + ["d_0_inc.in1","_U1074.out"], + ["d_1_inc.in1","_U10741.out"], + ["cmp_time.in1","_U1075.out"], + ["affine_func$mul_d0__U1068.out","affine_func$add_all__U1072.in0"], + ["affine_func$mul_d1__U1070.out","affine_func$add_all__U1072.in1"], + ["affine_func$add_all__U1073.in0","affine_func$add_all__U1072.out"], + ["affine_func$const_term_U1071.out","affine_func$add_all__U1073.in1"], + ["time_diff.in0","affine_func$add_all__U1073.out"], + ["affine_func$mul_d0__U1068.in0","affine_func$coeff_0_U1067.out"], + ["affine_func$mul_d1__U1070.in0","affine_func$coeff_1_U1069.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1068.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1070.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -7525,10 +7525,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U117$lut$lut.bit.in.2","d_0_am__U117$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U117$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U117$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U117$lut$lut.bit.out"], + ["d_0_am__U1076$lut$lut.bit.in.2","d_0_am__U1076$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1076$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1076$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1076$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7564,7 +7564,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1074":{ + "affine_controller__U1079":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -7572,49 +7572,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1083":{ + "_U1088":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U10831":{ + "_U10881":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1084":{ + "_U1089":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1081":{ + "affine_func$add_all__U1086":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1082":{ + "affine_func$add_all__U1087":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1076":{ + "affine_func$coeff_0_U1081":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1078":{ + "affine_func$coeff_1_U1083":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1080":{ + "affine_func$const_term_U1085":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1077":{ + "affine_func$mul_d0__U1082":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1079":{ + "affine_func$mul_d1__U1084":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7678,12 +7678,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1085$c0_lutcnst":{ + "d_0_am__U1090$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1085$lut$lut":{ + "d_0_am__U1090$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7802,18 +7802,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1083.out"], - ["d_1_inc.in1","_U10831.out"], - ["cmp_time.in1","_U1084.out"], - ["affine_func$mul_d0__U1077.out","affine_func$add_all__U1081.in0"], - ["affine_func$mul_d1__U1079.out","affine_func$add_all__U1081.in1"], - ["affine_func$add_all__U1082.in0","affine_func$add_all__U1081.out"], - ["affine_func$const_term_U1080.out","affine_func$add_all__U1082.in1"], - ["time_diff.in0","affine_func$add_all__U1082.out"], - ["affine_func$mul_d0__U1077.in0","affine_func$coeff_0_U1076.out"], - ["affine_func$mul_d1__U1079.in0","affine_func$coeff_1_U1078.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1077.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1079.in1"], + ["d_0_inc.in1","_U1088.out"], + ["d_1_inc.in1","_U10881.out"], + ["cmp_time.in1","_U1089.out"], + ["affine_func$mul_d0__U1082.out","affine_func$add_all__U1086.in0"], + ["affine_func$mul_d1__U1084.out","affine_func$add_all__U1086.in1"], + ["affine_func$add_all__U1087.in0","affine_func$add_all__U1086.out"], + ["affine_func$const_term_U1085.out","affine_func$add_all__U1087.in1"], + ["time_diff.in0","affine_func$add_all__U1087.out"], + ["affine_func$mul_d0__U1082.in0","affine_func$coeff_0_U1081.out"], + ["affine_func$mul_d1__U1084.in0","affine_func$coeff_1_U1083.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1082.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1084.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -7836,10 +7836,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1085$lut$lut.bit.in.2","d_0_am__U1085$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1085$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1085$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1085$lut$lut.bit.out"], + ["d_0_am__U1090$lut$lut.bit.in.2","d_0_am__U1090$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1090$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1090$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1090$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7875,7 +7875,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1089":{ + "affine_controller__U1093":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -7883,49 +7883,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1098":{ + "_U1102":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U10981":{ + "_U11021":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1099":{ + "_U1103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1096":{ + "affine_func$add_all__U1100":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1097":{ + "affine_func$add_all__U1101":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1091":{ + "affine_func$coeff_0_U1095":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1093":{ + "affine_func$coeff_1_U1097":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1095":{ + "affine_func$const_term_U1099":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1092":{ + "affine_func$mul_d0__U1096":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1094":{ + "affine_func$mul_d1__U1098":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7989,12 +7989,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1100$c0_lutcnst":{ + "d_0_am__U1104$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1100$lut$lut":{ + "d_0_am__U1104$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8113,18 +8113,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1098.out"], - ["d_1_inc.in1","_U10981.out"], - ["cmp_time.in1","_U1099.out"], - ["affine_func$mul_d0__U1092.out","affine_func$add_all__U1096.in0"], - ["affine_func$mul_d1__U1094.out","affine_func$add_all__U1096.in1"], - ["affine_func$add_all__U1097.in0","affine_func$add_all__U1096.out"], - ["affine_func$const_term_U1095.out","affine_func$add_all__U1097.in1"], - ["time_diff.in0","affine_func$add_all__U1097.out"], - ["affine_func$mul_d0__U1092.in0","affine_func$coeff_0_U1091.out"], - ["affine_func$mul_d1__U1094.in0","affine_func$coeff_1_U1093.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1092.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1094.in1"], + ["d_0_inc.in1","_U1102.out"], + ["d_1_inc.in1","_U11021.out"], + ["cmp_time.in1","_U1103.out"], + ["affine_func$mul_d0__U1096.out","affine_func$add_all__U1100.in0"], + ["affine_func$mul_d1__U1098.out","affine_func$add_all__U1100.in1"], + ["affine_func$add_all__U1101.in0","affine_func$add_all__U1100.out"], + ["affine_func$const_term_U1099.out","affine_func$add_all__U1101.in1"], + ["time_diff.in0","affine_func$add_all__U1101.out"], + ["affine_func$mul_d0__U1096.in0","affine_func$coeff_0_U1095.out"], + ["affine_func$mul_d1__U1098.in0","affine_func$coeff_1_U1097.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1096.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1098.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -8147,10 +8147,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1100$lut$lut.bit.in.2","d_0_am__U1100$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1100$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1100$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1100$lut$lut.bit.out"], + ["d_0_am__U1104$lut$lut.bit.in.2","d_0_am__U1104$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1104$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1104$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1104$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8186,7 +8186,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1104":{ + "affine_controller__U1107":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -8194,49 +8194,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1113":{ + "_U1116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U11131":{ + "_U11161":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1114":{ + "_U1117":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1111":{ + "affine_func$add_all__U1114":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1112":{ + "affine_func$add_all__U1115":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1106":{ + "affine_func$coeff_0_U1109":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1108":{ + "affine_func$coeff_1_U1111":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1110":{ + "affine_func$const_term_U1113":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1107":{ + "affine_func$mul_d0__U1110":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1109":{ + "affine_func$mul_d1__U1112":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -8300,12 +8300,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1115$c0_lutcnst":{ + "d_0_am__U1118$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1115$lut$lut":{ + "d_0_am__U1118$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8424,18 +8424,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1113.out"], - ["d_1_inc.in1","_U11131.out"], - ["cmp_time.in1","_U1114.out"], - ["affine_func$mul_d0__U1107.out","affine_func$add_all__U1111.in0"], - ["affine_func$mul_d1__U1109.out","affine_func$add_all__U1111.in1"], - ["affine_func$add_all__U1112.in0","affine_func$add_all__U1111.out"], - ["affine_func$const_term_U1110.out","affine_func$add_all__U1112.in1"], - ["time_diff.in0","affine_func$add_all__U1112.out"], - ["affine_func$mul_d0__U1107.in0","affine_func$coeff_0_U1106.out"], - ["affine_func$mul_d1__U1109.in0","affine_func$coeff_1_U1108.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1107.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1109.in1"], + ["d_0_inc.in1","_U1116.out"], + ["d_1_inc.in1","_U11161.out"], + ["cmp_time.in1","_U1117.out"], + ["affine_func$mul_d0__U1110.out","affine_func$add_all__U1114.in0"], + ["affine_func$mul_d1__U1112.out","affine_func$add_all__U1114.in1"], + ["affine_func$add_all__U1115.in0","affine_func$add_all__U1114.out"], + ["affine_func$const_term_U1113.out","affine_func$add_all__U1115.in1"], + ["time_diff.in0","affine_func$add_all__U1115.out"], + ["affine_func$mul_d0__U1110.in0","affine_func$coeff_0_U1109.out"], + ["affine_func$mul_d1__U1112.in0","affine_func$coeff_1_U1111.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1110.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1112.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -8458,10 +8458,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1115$lut$lut.bit.in.2","d_0_am__U1115$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1115$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1115$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1115$lut$lut.bit.out"], + ["d_0_am__U1118$lut$lut.bit.in.2","d_0_am__U1118$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1118$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1118$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1118$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8497,57 +8497,93 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1119":{ + "affine_controller__U112":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1128":{ + "_U127":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U11281":{ + "_U1271":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1129":{ + "_U1272":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1273":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U128":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1126":{ + "affine_func$add_all__U123":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U124":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1127":{ + "affine_func$add_all__U125":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1121":{ + "affine_func$add_all__U126":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1123":{ + "affine_func$coeff_1_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000240"]} }, - "affine_func$const_term_U1125":{ + "affine_func$coeff_2_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_3_U120":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U122":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$mul_d0__U115":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U117":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U1122":{ + "affine_func$mul_d2__U119":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1124":{ + "affine_func$mul_d3__U121":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -8611,12 +8647,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1130$c0_lutcnst":{ + "d_0_am__U129$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1130$lut$lut":{ + "d_0_am__U129$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U130$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U130$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U131$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U131$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8665,6 +8721,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U132$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U132$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U133$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U133$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -8676,7 +8752,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, "d_1_min":{ "genref":"coreir.const", @@ -8709,6 +8785,104 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_2_am__U134$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U134$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -8728,6 +8902,16 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -8735,21 +8919,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U1128.out"], - ["d_1_inc.in1","_U11281.out"], - ["cmp_time.in1","_U1129.out"], - ["affine_func$mul_d0__U1122.out","affine_func$add_all__U1126.in0"], - ["affine_func$mul_d1__U1124.out","affine_func$add_all__U1126.in1"], - ["affine_func$add_all__U1127.in0","affine_func$add_all__U1126.out"], - ["affine_func$const_term_U1125.out","affine_func$add_all__U1127.in1"], - ["time_diff.in0","affine_func$add_all__U1127.out"], - ["affine_func$mul_d0__U1122.in0","affine_func$coeff_0_U1121.out"], - ["affine_func$mul_d1__U1124.in0","affine_func$coeff_1_U1123.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1122.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1124.in1"], + ["d_0_inc.in1","_U127.out"], + ["d_1_inc.in1","_U1271.out"], + ["d_2_inc.in1","_U1272.out"], + ["d_3_inc.in1","_U1273.out"], + ["cmp_time.in1","_U128.out"], + ["affine_func$mul_d0__U115.out","affine_func$add_all__U123.in0"], + ["affine_func$mul_d1__U117.out","affine_func$add_all__U123.in1"], + ["affine_func$add_all__U124.in0","affine_func$add_all__U123.out"], + ["affine_func$mul_d2__U119.out","affine_func$add_all__U124.in1"], + ["affine_func$add_all__U125.in0","affine_func$add_all__U124.out"], + ["affine_func$mul_d3__U121.out","affine_func$add_all__U125.in1"], + ["affine_func$add_all__U126.in0","affine_func$add_all__U125.out"], + ["affine_func$const_term_U122.out","affine_func$add_all__U126.in1"], + ["time_diff.in0","affine_func$add_all__U126.out"], + ["affine_func$mul_d0__U115.in0","affine_func$coeff_0_U114.out"], + ["affine_func$mul_d1__U117.in0","affine_func$coeff_1_U116.out"], + ["affine_func$mul_d2__U119.in0","affine_func$coeff_2_U118.out"], + ["affine_func$mul_d3__U121.in0","affine_func$coeff_3_U120.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U115.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U117.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U119.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U121.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -8757,22 +8953,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1130$lut$lut.bit.in.2","d_0_am__U1130$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1130$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1130$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1130$lut$lut.bit.out"], + ["d_0_am__U129$lut$lut.bit.in.2","d_0_am__U129$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U129$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U129$lut$lut.bit.in.1"], + ["d_0_am__U130$lut$lut.bit.in.0","d_0_am__U129$lut$lut.bit.out"], + ["d_0_am__U130$lut$lut.bit.in.2","d_0_am__U130$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U130$lut$lut.bit.in.1"], + ["d_0_am__U131$lut$lut.bit.in.0","d_0_am__U130$lut$lut.bit.out"], + ["d_0_am__U131$lut$lut.bit.in.2","d_0_am__U131$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U131$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U131$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8789,6 +8991,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U132$lut$lut.bit.in.2","d_1_am__U132$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U132$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U132$lut$lut.bit.in.1"], + ["d_1_am__U133$lut$lut.bit.in.0","d_1_am__U132$lut$lut.bit.out"], + ["d_1_am__U133$lut$lut.bit.in.2","d_1_am__U133$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U133$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U133$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -8798,67 +9007,157 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U134$lut$lut.bit.in.2","d_2_am__U134$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U134$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U134$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U134$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U1134":{ + "affine_controller__U1120":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",5,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1143":{ + "_U1138":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11381":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11382":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U11431":{ + "_U11384":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1144":{ + "_U1139":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1141":{ + "affine_func$add_all__U1133":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1134":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1135":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1142":{ + "affine_func$add_all__U1136":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1136":{ + "affine_func$add_all__U1137":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U1122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1138":{ + "affine_func$coeff_1_U1124":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00006000"]} }, - "affine_func$const_term_U1140":{ + "affine_func$coeff_2_U1126":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} + "modargs":{"value":[["BitVector",32],"32'h00002000"]} + }, + "affine_func$coeff_3_U1128":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "affine_func$coeff_4_U1130":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U1132":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$mul_d0__U1123":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U1125":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U1127":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U1137":{ + "affine_func$mul_d3__U1129":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1139":{ + "affine_func$mul_d4__U1131":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -8922,12 +9221,42 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1145$c0_lutcnst":{ + "d_0_am__U1140$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1140$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1141$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1141$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1142$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1142$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1143$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1145$lut$lut":{ + "d_0_am__U1143$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8976,6 +9305,36 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1144$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1144$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1145$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1145$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1146$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1146$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -8987,7 +9346,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -9020,313 +9379,164 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ + "d_2_am__U1147$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true2_lutcnst":{ + "d_2_am__U1147$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true3_lutcnst":{ + "d_2_am__U1148$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true_lutcnst":{ + "d_2_am__U1148$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U1143.out"], - ["d_1_inc.in1","_U11431.out"], - ["cmp_time.in1","_U1144.out"], - ["affine_func$mul_d0__U1137.out","affine_func$add_all__U1141.in0"], - ["affine_func$mul_d1__U1139.out","affine_func$add_all__U1141.in1"], - ["affine_func$add_all__U1142.in0","affine_func$add_all__U1141.out"], - ["affine_func$const_term_U1140.out","affine_func$add_all__U1142.in1"], - ["time_diff.in0","affine_func$add_all__U1142.out"], - ["affine_func$mul_d0__U1137.in0","affine_func$coeff_0_U1136.out"], - ["affine_func$mul_d1__U1139.in0","affine_func$coeff_1_U1138.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1137.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1139.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1145$lut$lut.bit.in.2","d_0_am__U1145$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1145$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1145$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1145$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] - ] - }, - "affine_controller__U1149":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1158":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U11581":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1159":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$add_all__U1156":{ - "genref":"coreir.add", + "d_2_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1157":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1151":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, - "affine_func$coeff_1_U1153":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1155":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "affine_func$mul_d0__U1152":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U1154":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "cmp_time":{ - "genref":"coreir.eq", + "d_2_next_value":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$add":{ - "genref":"coreir.add", + "d_2_next_value_at_max":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$and$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$and$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "cycle_time$count$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$count$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} - }, - "cycle_time$ult":{ - "genref":"coreir.ult", - "genargs":{"width":["Int",32]} - }, - "d_0_am__U1160$c0_lutcnst":{ + "d_3_am__U1149$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1160$lut$lut":{ + "d_3_am__U1149$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000003f"]} }, - "d_0_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_1_min":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_4_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_4_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$c0":{ + "d_4_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ + "d_4_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ + "d_4_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ + "d_4_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -9350,6 +9560,21 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9357,21 +9582,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U1158.out"], - ["d_1_inc.in1","_U11581.out"], - ["cmp_time.in1","_U1159.out"], - ["affine_func$mul_d0__U1152.out","affine_func$add_all__U1156.in0"], - ["affine_func$mul_d1__U1154.out","affine_func$add_all__U1156.in1"], - ["affine_func$add_all__U1157.in0","affine_func$add_all__U1156.out"], - ["affine_func$const_term_U1155.out","affine_func$add_all__U1157.in1"], - ["time_diff.in0","affine_func$add_all__U1157.out"], - ["affine_func$mul_d0__U1152.in0","affine_func$coeff_0_U1151.out"], - ["affine_func$mul_d1__U1154.in0","affine_func$coeff_1_U1153.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1152.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1154.in1"], + ["d_0_inc.in1","_U1138.out"], + ["d_1_inc.in1","_U11381.out"], + ["d_2_inc.in1","_U11382.out"], + ["d_3_inc.in1","_U11383.out"], + ["d_4_inc.in1","_U11384.out"], + ["cmp_time.in1","_U1139.out"], + ["affine_func$mul_d0__U1123.out","affine_func$add_all__U1133.in0"], + ["affine_func$mul_d1__U1125.out","affine_func$add_all__U1133.in1"], + ["affine_func$add_all__U1134.in0","affine_func$add_all__U1133.out"], + ["affine_func$mul_d2__U1127.out","affine_func$add_all__U1134.in1"], + ["affine_func$add_all__U1135.in0","affine_func$add_all__U1134.out"], + ["affine_func$mul_d3__U1129.out","affine_func$add_all__U1135.in1"], + ["affine_func$add_all__U1136.in0","affine_func$add_all__U1135.out"], + ["affine_func$mul_d4__U1131.out","affine_func$add_all__U1136.in1"], + ["affine_func$add_all__U1137.in0","affine_func$add_all__U1136.out"], + ["affine_func$const_term_U1132.out","affine_func$add_all__U1137.in1"], + ["time_diff.in0","affine_func$add_all__U1137.out"], + ["affine_func$mul_d0__U1123.in0","affine_func$coeff_0_U1122.out"], + ["affine_func$mul_d1__U1125.in0","affine_func$coeff_1_U1124.out"], + ["affine_func$mul_d2__U1127.in0","affine_func$coeff_2_U1126.out"], + ["affine_func$mul_d3__U1129.in0","affine_func$coeff_3_U1128.out"], + ["affine_func$mul_d4__U1131.in0","affine_func$coeff_4_U1130.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1123.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1125.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U1127.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U1129.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U1131.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -9379,22 +9622,31 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1160$lut$lut.bit.in.2","d_0_am__U1160$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1160$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1160$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1160$lut$lut.bit.out"], + ["d_0_am__U1140$lut$lut.bit.in.2","d_0_am__U1140$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1140$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1140$lut$lut.bit.in.1"], + ["d_0_am__U1141$lut$lut.bit.in.0","d_0_am__U1140$lut$lut.bit.out"], + ["d_0_am__U1141$lut$lut.bit.in.2","d_0_am__U1141$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U1141$lut$lut.bit.in.1"], + ["d_0_am__U1142$lut$lut.bit.in.0","d_0_am__U1141$lut$lut.bit.out"], + ["d_0_am__U1142$lut$lut.bit.in.2","d_0_am__U1142$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U1142$lut$lut.bit.in.1"], + ["d_0_am__U1143$lut$lut.bit.in.0","d_0_am__U1142$lut$lut.bit.out"], + ["d_0_am__U1143$lut$lut.bit.in.2","d_0_am__U1143$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U1143$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1143$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9411,6 +9663,16 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U1144$lut$lut.bit.in.2","d_1_am__U1144$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U1144$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U1144$lut$lut.bit.in.1"], + ["d_1_am__U1145$lut$lut.bit.in.0","d_1_am__U1144$lut$lut.bit.out"], + ["d_1_am__U1145$lut$lut.bit.in.2","d_1_am__U1145$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U1145$lut$lut.bit.in.1"], + ["d_1_am__U1146$lut$lut.bit.in.0","d_1_am__U1145$lut$lut.bit.out"], + ["d_1_am__U1146$lut$lut.bit.in.2","d_1_am__U1146$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U1146$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U1146$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -9420,67 +9682,252 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] - ] - }, - "affine_controller__U1164":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1173":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U11731":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1174":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$add_all__U1171":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1172":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U1166":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$coeff_1_U1168":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$const_term_U1170":{ - "genref":"coreir.const", + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U1147$lut$lut.bit.in.2","d_2_am__U1147$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U1147$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U1147$lut$lut.bit.in.1"], + ["d_2_am__U1148$lut$lut.bit.in.0","d_2_am__U1147$lut$lut.bit.out"], + ["d_2_am__U1148$lut$lut.bit.in.2","d_2_am__U1148$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U1148$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U1148$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U1149$lut$lut.bit.in.2","d_3_am__U1149$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U1149$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U1149$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U1149$lut$lut.bit.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["true_lutcnst.bit.out","d_4_next_value.sel"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"] + ] + }, + "affine_controller__U1169":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",9,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U1199":{ + "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11991":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11992":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11993":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11994":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11995":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11996":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11997":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U11998":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1200":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$add_all__U1190":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1191":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1192":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1193":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1194":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1195":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U1167":{ + "affine_func$add_all__U1196":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1197":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1198":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U1171":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$coeff_1_U1173":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00009000"]} + }, + "affine_func$coeff_2_U1175":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00004800"]} + }, + "affine_func$coeff_3_U1177":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00001800"]} + }, + "affine_func$coeff_4_U1179":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000800"]} + }, + "affine_func$coeff_5_U1181":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000200"]} + }, + "affine_func$coeff_6_U1183":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_7_U1185":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} + }, + "affine_func$coeff_8_U1187":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U1189":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00011fff"]} + }, + "affine_func$mul_d0__U1172":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U1174":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U1176":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U1178":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1169":{ + "affine_func$mul_d4__U1180":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U1182":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d6__U1184":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d7__U1186":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d8__U1188":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -9544,12 +9991,82 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1175$c0_lutcnst":{ + "d_0_am__U1201$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1201$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1202$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1202$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1203$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1203$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1204$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1204$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1205$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1205$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1206$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1206$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1207$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1175$lut$lut":{ + "d_0_am__U1207$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1208$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1208$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9598,6 +10115,76 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1209$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1209$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1210$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1210$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1211$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1211$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1212$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1212$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1213$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1213$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1214$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1214$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1215$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1215$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -9609,7 +10196,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -9642,10 +10229,533 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_2_am__U1216$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U1216$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U1217$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U1217$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U1218$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U1218$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U1219$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U1219$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U1220$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U1220$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U1221$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U1221$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_am__U1222$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U1222$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U1223$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U1223$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U1224$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U1224$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U1225$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U1225$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U1226$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U1226$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000002"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U1227$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U1227$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U1228$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U1228$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U1229$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U1229$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U1230$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U1230$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000002"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_5_am__U1231$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_5_am__U1231$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_5_am__U1232$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_5_am__U1232$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_5_am__U1233$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_5_am__U1233$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000003"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_6_am__U1234$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_6_am__U1234$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_6_am__U1235$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_6_am__U1235$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_7_am__U1236$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_7_am__U1236$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_7_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_7_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_7_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_7_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_7_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_7_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_8_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_8_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_8_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_8_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_8_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_8_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_8_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_8_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_8_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_8_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} }, + "true10_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9661,6 +10771,36 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true8_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true9_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9668,21 +10808,63 @@ } }, "connections":[ - ["d_0_inc.in1","_U1173.out"], - ["d_1_inc.in1","_U11731.out"], - ["cmp_time.in1","_U1174.out"], - ["affine_func$mul_d0__U1167.out","affine_func$add_all__U1171.in0"], - ["affine_func$mul_d1__U1169.out","affine_func$add_all__U1171.in1"], - ["affine_func$add_all__U1172.in0","affine_func$add_all__U1171.out"], - ["affine_func$const_term_U1170.out","affine_func$add_all__U1172.in1"], - ["time_diff.in0","affine_func$add_all__U1172.out"], - ["affine_func$mul_d0__U1167.in0","affine_func$coeff_0_U1166.out"], - ["affine_func$mul_d1__U1169.in0","affine_func$coeff_1_U1168.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1167.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1169.in1"], + ["d_0_inc.in1","_U1199.out"], + ["d_1_inc.in1","_U11991.out"], + ["d_2_inc.in1","_U11992.out"], + ["d_3_inc.in1","_U11993.out"], + ["d_4_inc.in1","_U11994.out"], + ["d_5_inc.in1","_U11995.out"], + ["d_6_inc.in1","_U11996.out"], + ["d_7_inc.in1","_U11997.out"], + ["d_8_inc.in1","_U11998.out"], + ["cmp_time.in1","_U1200.out"], + ["affine_func$mul_d0__U1172.out","affine_func$add_all__U1190.in0"], + ["affine_func$mul_d1__U1174.out","affine_func$add_all__U1190.in1"], + ["affine_func$add_all__U1191.in0","affine_func$add_all__U1190.out"], + ["affine_func$mul_d2__U1176.out","affine_func$add_all__U1191.in1"], + ["affine_func$add_all__U1192.in0","affine_func$add_all__U1191.out"], + ["affine_func$mul_d3__U1178.out","affine_func$add_all__U1192.in1"], + ["affine_func$add_all__U1193.in0","affine_func$add_all__U1192.out"], + ["affine_func$mul_d4__U1180.out","affine_func$add_all__U1193.in1"], + ["affine_func$add_all__U1194.in0","affine_func$add_all__U1193.out"], + ["affine_func$mul_d5__U1182.out","affine_func$add_all__U1194.in1"], + ["affine_func$add_all__U1195.in0","affine_func$add_all__U1194.out"], + ["affine_func$mul_d6__U1184.out","affine_func$add_all__U1195.in1"], + ["affine_func$add_all__U1196.in0","affine_func$add_all__U1195.out"], + ["affine_func$mul_d7__U1186.out","affine_func$add_all__U1196.in1"], + ["affine_func$add_all__U1197.in0","affine_func$add_all__U1196.out"], + ["affine_func$mul_d8__U1188.out","affine_func$add_all__U1197.in1"], + ["affine_func$add_all__U1198.in0","affine_func$add_all__U1197.out"], + ["affine_func$const_term_U1189.out","affine_func$add_all__U1198.in1"], + ["time_diff.in0","affine_func$add_all__U1198.out"], + ["affine_func$mul_d0__U1172.in0","affine_func$coeff_0_U1171.out"], + ["affine_func$mul_d1__U1174.in0","affine_func$coeff_1_U1173.out"], + ["affine_func$mul_d2__U1176.in0","affine_func$coeff_2_U1175.out"], + ["affine_func$mul_d3__U1178.in0","affine_func$coeff_3_U1177.out"], + ["affine_func$mul_d4__U1180.in0","affine_func$coeff_4_U1179.out"], + ["affine_func$mul_d5__U1182.in0","affine_func$coeff_5_U1181.out"], + ["affine_func$mul_d6__U1184.in0","affine_func$coeff_6_U1183.out"], + ["affine_func$mul_d7__U1186.in0","affine_func$coeff_7_U1185.out"], + ["affine_func$mul_d8__U1188.in0","affine_func$coeff_8_U1187.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1172.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1174.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U1176.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U1178.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U1180.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U1182.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U1184.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U1186.in1"], + ["d_8_reg$reg0.out","affine_func$mul_d8__U1188.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["d_7_reg$enMux.sel","cmp_time.out"], + ["d_8_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -9690,22 +10872,43 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true10_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true9_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1175$lut$lut.bit.in.2","d_0_am__U1175$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1175$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1175$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1175$lut$lut.bit.out"], + ["d_0_am__U1201$lut$lut.bit.in.2","d_0_am__U1201$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1201$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1201$lut$lut.bit.in.1"], + ["d_0_am__U1202$lut$lut.bit.in.0","d_0_am__U1201$lut$lut.bit.out"], + ["d_0_am__U1202$lut$lut.bit.in.2","d_0_am__U1202$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U1202$lut$lut.bit.in.1"], + ["d_0_am__U1203$lut$lut.bit.in.0","d_0_am__U1202$lut$lut.bit.out"], + ["d_0_am__U1203$lut$lut.bit.in.2","d_0_am__U1203$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U1203$lut$lut.bit.in.1"], + ["d_0_am__U1204$lut$lut.bit.in.0","d_0_am__U1203$lut$lut.bit.out"], + ["d_0_am__U1204$lut$lut.bit.in.2","d_0_am__U1204$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U1204$lut$lut.bit.in.1"], + ["d_0_am__U1205$lut$lut.bit.in.0","d_0_am__U1204$lut$lut.bit.out"], + ["d_0_am__U1205$lut$lut.bit.in.2","d_0_am__U1205$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U1205$lut$lut.bit.in.1"], + ["d_0_am__U1206$lut$lut.bit.in.0","d_0_am__U1205$lut$lut.bit.out"], + ["d_0_am__U1206$lut$lut.bit.in.2","d_0_am__U1206$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U1206$lut$lut.bit.in.1"], + ["d_0_am__U1207$lut$lut.bit.in.0","d_0_am__U1206$lut$lut.bit.out"], + ["d_0_am__U1207$lut$lut.bit.in.2","d_0_am__U1207$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U1207$lut$lut.bit.in.1"], + ["d_0_am__U1208$lut$lut.bit.in.0","d_0_am__U1207$lut$lut.bit.out"], + ["d_0_am__U1208$lut$lut.bit.in.2","d_0_am__U1208$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_0_am__U1208$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1208$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9722,6 +10925,28 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U1209$lut$lut.bit.in.2","d_1_am__U1209$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U1209$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U1209$lut$lut.bit.in.1"], + ["d_1_am__U1210$lut$lut.bit.in.0","d_1_am__U1209$lut$lut.bit.out"], + ["d_1_am__U1210$lut$lut.bit.in.2","d_1_am__U1210$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U1210$lut$lut.bit.in.1"], + ["d_1_am__U1211$lut$lut.bit.in.0","d_1_am__U1210$lut$lut.bit.out"], + ["d_1_am__U1211$lut$lut.bit.in.2","d_1_am__U1211$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U1211$lut$lut.bit.in.1"], + ["d_1_am__U1212$lut$lut.bit.in.0","d_1_am__U1211$lut$lut.bit.out"], + ["d_1_am__U1212$lut$lut.bit.in.2","d_1_am__U1212$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U1212$lut$lut.bit.in.1"], + ["d_1_am__U1213$lut$lut.bit.in.0","d_1_am__U1212$lut$lut.bit.out"], + ["d_1_am__U1213$lut$lut.bit.in.2","d_1_am__U1213$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U1213$lut$lut.bit.in.1"], + ["d_1_am__U1214$lut$lut.bit.in.0","d_1_am__U1213$lut$lut.bit.out"], + ["d_1_am__U1214$lut$lut.bit.in.2","d_1_am__U1214$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U1214$lut$lut.bit.in.1"], + ["d_1_am__U1215$lut$lut.bit.in.0","d_1_am__U1214$lut$lut.bit.out"], + ["d_1_am__U1215$lut$lut.bit.in.2","d_1_am__U1215$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_1_am__U1215$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U1215$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -9731,17 +10956,198 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U1216$lut$lut.bit.in.2","d_2_am__U1216$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U1216$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U1216$lut$lut.bit.in.1"], + ["d_2_am__U1217$lut$lut.bit.in.0","d_2_am__U1216$lut$lut.bit.out"], + ["d_2_am__U1217$lut$lut.bit.in.2","d_2_am__U1217$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U1217$lut$lut.bit.in.1"], + ["d_2_am__U1218$lut$lut.bit.in.0","d_2_am__U1217$lut$lut.bit.out"], + ["d_2_am__U1218$lut$lut.bit.in.2","d_2_am__U1218$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U1218$lut$lut.bit.in.1"], + ["d_2_am__U1219$lut$lut.bit.in.0","d_2_am__U1218$lut$lut.bit.out"], + ["d_2_am__U1219$lut$lut.bit.in.2","d_2_am__U1219$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U1219$lut$lut.bit.in.1"], + ["d_2_am__U1220$lut$lut.bit.in.0","d_2_am__U1219$lut$lut.bit.out"], + ["d_2_am__U1220$lut$lut.bit.in.2","d_2_am__U1220$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U1220$lut$lut.bit.in.1"], + ["d_2_am__U1221$lut$lut.bit.in.0","d_2_am__U1220$lut$lut.bit.out"], + ["d_2_am__U1221$lut$lut.bit.in.2","d_2_am__U1221$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_2_am__U1221$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U1221$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U1222$lut$lut.bit.in.2","d_3_am__U1222$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U1222$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U1222$lut$lut.bit.in.1"], + ["d_3_am__U1223$lut$lut.bit.in.0","d_3_am__U1222$lut$lut.bit.out"], + ["d_3_am__U1223$lut$lut.bit.in.2","d_3_am__U1223$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U1223$lut$lut.bit.in.1"], + ["d_3_am__U1224$lut$lut.bit.in.0","d_3_am__U1223$lut$lut.bit.out"], + ["d_3_am__U1224$lut$lut.bit.in.2","d_3_am__U1224$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U1224$lut$lut.bit.in.1"], + ["d_3_am__U1225$lut$lut.bit.in.0","d_3_am__U1224$lut$lut.bit.out"], + ["d_3_am__U1225$lut$lut.bit.in.2","d_3_am__U1225$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U1225$lut$lut.bit.in.1"], + ["d_3_am__U1226$lut$lut.bit.in.0","d_3_am__U1225$lut$lut.bit.out"], + ["d_3_am__U1226$lut$lut.bit.in.2","d_3_am__U1226$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_3_am__U1226$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U1226$lut$lut.bit.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U1227$lut$lut.bit.in.2","d_4_am__U1227$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U1227$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U1227$lut$lut.bit.in.1"], + ["d_4_am__U1228$lut$lut.bit.in.0","d_4_am__U1227$lut$lut.bit.out"], + ["d_4_am__U1228$lut$lut.bit.in.2","d_4_am__U1228$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U1228$lut$lut.bit.in.1"], + ["d_4_am__U1229$lut$lut.bit.in.0","d_4_am__U1228$lut$lut.bit.out"], + ["d_4_am__U1229$lut$lut.bit.in.2","d_4_am__U1229$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U1229$lut$lut.bit.in.1"], + ["d_4_am__U1230$lut$lut.bit.in.0","d_4_am__U1229$lut$lut.bit.out"], + ["d_4_am__U1230$lut$lut.bit.in.2","d_4_am__U1230$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_4_am__U1230$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U1230$lut$lut.bit.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U1231$lut$lut.bit.in.2","d_5_am__U1231$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U1231$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U1231$lut$lut.bit.in.1"], + ["d_5_am__U1232$lut$lut.bit.in.0","d_5_am__U1231$lut$lut.bit.out"], + ["d_5_am__U1232$lut$lut.bit.in.2","d_5_am__U1232$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U1232$lut$lut.bit.in.1"], + ["d_5_am__U1233$lut$lut.bit.in.0","d_5_am__U1232$lut$lut.bit.out"], + ["d_5_am__U1233$lut$lut.bit.in.2","d_5_am__U1233$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_5_am__U1233$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U1233$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_am__U1234$lut$lut.bit.in.2","d_6_am__U1234$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U1234$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U1234$lut$lut.bit.in.1"], + ["d_6_am__U1235$lut$lut.bit.in.0","d_6_am__U1234$lut$lut.bit.out"], + ["d_6_am__U1235$lut$lut.bit.in.2","d_6_am__U1235$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_6_am__U1235$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U1235$lut$lut.bit.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"], + ["d_7_am__U1236$lut$lut.bit.in.2","d_7_am__U1236$c0_lutcnst.bit.out"], + ["true8_lutcnst.bit.out","d_7_am__U1236$lut$lut.bit.in.0"], + ["d_8_at_max.out","d_7_am__U1236$lut$lut.bit.in.1"], + ["d_7_next_value.sel","d_7_am__U1236$lut$lut.bit.out"], + ["d_7_reg$reg0.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg$reg0.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg$reg0.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg$enMux.in1","d_7_next_value.out"], + ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], + ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], + ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], + ["self.rst_n","d_7_reg$clrMux.sel"], + ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], + ["self.clk","d_7_reg$reg0.clk"], + ["self.d.7","d_7_reg$reg0.out"], + ["d_8_reg$reg0.out","d_8_at_max.in0"], + ["d_8_max.out","d_8_at_max.in1"], + ["d_8_next_value_at_max.sel","d_8_at_max.out"], + ["d_8_reg$reg0.out","d_8_inc.in0"], + ["d_8_next_value_at_max.in0","d_8_inc.out"], + ["d_8_next_value_at_max.in1","d_8_min.out"], + ["d_8_reg$reg0.out","d_8_next_value.in0"], + ["d_8_next_value_at_max.out","d_8_next_value.in1"], + ["d_8_reg$enMux.in1","d_8_next_value.out"], + ["true_lutcnst.bit.out","d_8_next_value.sel"], + ["d_8_reg$clrMux.in1","d_8_reg$c0.out"], + ["d_8_reg$enMux.out","d_8_reg$clrMux.in0"], + ["d_8_reg$reg0.in","d_8_reg$clrMux.out"], + ["self.rst_n","d_8_reg$clrMux.sel"], + ["d_8_reg$reg0.out","d_8_reg$enMux.in0"], + ["self.clk","d_8_reg$reg0.clk"], + ["self.d.8","d_8_reg$reg0.out"] ] }, - "affine_controller__U1179":{ + "affine_controller__U1270":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -9749,49 +11155,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1188":{ + "_U1279":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U11881":{ + "_U12791":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1189":{ + "_U1280":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1186":{ + "affine_func$add_all__U1277":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1187":{ + "affine_func$add_all__U1278":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1181":{ + "affine_func$coeff_0_U1272":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1183":{ + "affine_func$coeff_1_U1274":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1185":{ + "affine_func$const_term_U1276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1182":{ + "affine_func$mul_d0__U1273":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1184":{ + "affine_func$mul_d1__U1275":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -9855,12 +11261,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1190$c0_lutcnst":{ + "d_0_am__U1281$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1190$lut$lut":{ + "d_0_am__U1281$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9979,18 +11385,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1188.out"], - ["d_1_inc.in1","_U11881.out"], - ["cmp_time.in1","_U1189.out"], - ["affine_func$mul_d0__U1182.out","affine_func$add_all__U1186.in0"], - ["affine_func$mul_d1__U1184.out","affine_func$add_all__U1186.in1"], - ["affine_func$add_all__U1187.in0","affine_func$add_all__U1186.out"], - ["affine_func$const_term_U1185.out","affine_func$add_all__U1187.in1"], - ["time_diff.in0","affine_func$add_all__U1187.out"], - ["affine_func$mul_d0__U1182.in0","affine_func$coeff_0_U1181.out"], - ["affine_func$mul_d1__U1184.in0","affine_func$coeff_1_U1183.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1182.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1184.in1"], + ["d_0_inc.in1","_U1279.out"], + ["d_1_inc.in1","_U12791.out"], + ["cmp_time.in1","_U1280.out"], + ["affine_func$mul_d0__U1273.out","affine_func$add_all__U1277.in0"], + ["affine_func$mul_d1__U1275.out","affine_func$add_all__U1277.in1"], + ["affine_func$add_all__U1278.in0","affine_func$add_all__U1277.out"], + ["affine_func$const_term_U1276.out","affine_func$add_all__U1278.in1"], + ["time_diff.in0","affine_func$add_all__U1278.out"], + ["affine_func$mul_d0__U1273.in0","affine_func$coeff_0_U1272.out"], + ["affine_func$mul_d1__U1275.in0","affine_func$coeff_1_U1274.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1273.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1275.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -10013,10 +11419,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1190$lut$lut.bit.in.2","d_0_am__U1190$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1190$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1190$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1190$lut$lut.bit.out"], + ["d_0_am__U1281$lut$lut.bit.in.2","d_0_am__U1281$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1281$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1281$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1281$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10052,111 +11458,57 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1194":{ + "affine_controller__U1284":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1212":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12121":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12122":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12123":{ + "_U1293":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U12124":{ + "_U12931":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1213":{ + "_U1294":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1207":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1208":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1209":{ + "affine_func$add_all__U1291":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1210":{ + "affine_func$add_all__U1292":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1211":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U1196":{ + "affine_func$coeff_0_U1286":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1198":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00006000"]} - }, - "affine_func$coeff_2_U1200":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00002000"]} - }, - "affine_func$coeff_3_U1202":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "affine_func$coeff_4_U1204":{ + "affine_func$coeff_1_U1288":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1206":{ + "affine_func$const_term_U1290":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$mul_d0__U1197":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U1199":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d2__U1201":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d3__U1203":{ + "affine_func$mul_d0__U1287":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U1205":{ + "affine_func$mul_d1__U1289":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -10220,42 +11572,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1214$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1214$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1215$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1215$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1216$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1216$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1217$c0_lutcnst":{ + "d_0_am__U1295$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1217$lut$lut":{ + "d_0_am__U1295$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10304,36 +11626,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1218$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1218$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1219$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1219$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1220$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1220$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -10345,7 +11637,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -10378,168 +11670,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1221$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1221$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U1222$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1222$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U1223$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U1223$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -10559,21 +11689,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -10581,39 +11696,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U1212.out"], - ["d_1_inc.in1","_U12121.out"], - ["d_2_inc.in1","_U12122.out"], - ["d_3_inc.in1","_U12123.out"], - ["d_4_inc.in1","_U12124.out"], - ["cmp_time.in1","_U1213.out"], - ["affine_func$mul_d0__U1197.out","affine_func$add_all__U1207.in0"], - ["affine_func$mul_d1__U1199.out","affine_func$add_all__U1207.in1"], - ["affine_func$add_all__U1208.in0","affine_func$add_all__U1207.out"], - ["affine_func$mul_d2__U1201.out","affine_func$add_all__U1208.in1"], - ["affine_func$add_all__U1209.in0","affine_func$add_all__U1208.out"], - ["affine_func$mul_d3__U1203.out","affine_func$add_all__U1209.in1"], - ["affine_func$add_all__U1210.in0","affine_func$add_all__U1209.out"], - ["affine_func$mul_d4__U1205.out","affine_func$add_all__U1210.in1"], - ["affine_func$add_all__U1211.in0","affine_func$add_all__U1210.out"], - ["affine_func$const_term_U1206.out","affine_func$add_all__U1211.in1"], - ["time_diff.in0","affine_func$add_all__U1211.out"], - ["affine_func$mul_d0__U1197.in0","affine_func$coeff_0_U1196.out"], - ["affine_func$mul_d1__U1199.in0","affine_func$coeff_1_U1198.out"], - ["affine_func$mul_d2__U1201.in0","affine_func$coeff_2_U1200.out"], - ["affine_func$mul_d3__U1203.in0","affine_func$coeff_3_U1202.out"], - ["affine_func$mul_d4__U1205.in0","affine_func$coeff_4_U1204.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1197.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1199.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U1201.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U1203.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U1205.in1"], + ["d_0_inc.in1","_U1293.out"], + ["d_1_inc.in1","_U12931.out"], + ["cmp_time.in1","_U1294.out"], + ["affine_func$mul_d0__U1287.out","affine_func$add_all__U1291.in0"], + ["affine_func$mul_d1__U1289.out","affine_func$add_all__U1291.in1"], + ["affine_func$add_all__U1292.in0","affine_func$add_all__U1291.out"], + ["affine_func$const_term_U1290.out","affine_func$add_all__U1292.in1"], + ["time_diff.in0","affine_func$add_all__U1292.out"], + ["affine_func$mul_d0__U1287.in0","affine_func$coeff_0_U1286.out"], + ["affine_func$mul_d1__U1289.in0","affine_func$coeff_1_U1288.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1287.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1289.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -10621,31 +11718,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1214$lut$lut.bit.in.2","d_0_am__U1214$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1214$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1214$lut$lut.bit.in.1"], - ["d_0_am__U1215$lut$lut.bit.in.0","d_0_am__U1214$lut$lut.bit.out"], - ["d_0_am__U1215$lut$lut.bit.in.2","d_0_am__U1215$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U1215$lut$lut.bit.in.1"], - ["d_0_am__U1216$lut$lut.bit.in.0","d_0_am__U1215$lut$lut.bit.out"], - ["d_0_am__U1216$lut$lut.bit.in.2","d_0_am__U1216$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U1216$lut$lut.bit.in.1"], - ["d_0_am__U1217$lut$lut.bit.in.0","d_0_am__U1216$lut$lut.bit.out"], - ["d_0_am__U1217$lut$lut.bit.in.2","d_0_am__U1217$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U1217$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1217$lut$lut.bit.out"], + ["d_0_am__U1295$lut$lut.bit.in.2","d_0_am__U1295$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1295$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1295$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1295$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10662,16 +11750,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U1218$lut$lut.bit.in.2","d_1_am__U1218$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U1218$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U1218$lut$lut.bit.in.1"], - ["d_1_am__U1219$lut$lut.bit.in.0","d_1_am__U1218$lut$lut.bit.out"], - ["d_1_am__U1219$lut$lut.bit.in.2","d_1_am__U1219$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U1219$lut$lut.bit.in.1"], - ["d_1_am__U1220$lut$lut.bit.in.0","d_1_am__U1219$lut$lut.bit.out"], - ["d_1_am__U1220$lut$lut.bit.in.2","d_1_am__U1220$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U1220$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U1220$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10681,162 +11759,67 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U1221$lut$lut.bit.in.2","d_2_am__U1221$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U1221$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U1221$lut$lut.bit.in.1"], - ["d_2_am__U1222$lut$lut.bit.in.0","d_2_am__U1221$lut$lut.bit.out"], - ["d_2_am__U1222$lut$lut.bit.in.2","d_2_am__U1222$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U1222$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U1222$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U1223$lut$lut.bit.in.2","d_3_am__U1223$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U1223$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U1223$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U1223$lut$lut.bit.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["true_lutcnst.bit.out","d_4_next_value.sel"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U121":{ + "affine_controller__U1298":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U136":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1361":{ + "_U1307":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1362":{ + "_U13071":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1363":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U137":{ + "_U1308":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U132":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U133":{ + "affine_func$add_all__U1305":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U134":{ + "affine_func$add_all__U1306":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U135":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U123":{ + "affine_func$coeff_0_U1300":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U125":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000240"]} - }, - "affine_func$coeff_2_U127":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} - }, - "affine_func$coeff_3_U129":{ + "affine_func$coeff_1_U1302":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U131":{ + "affine_func$const_term_U1304":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$mul_d0__U124":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U126":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d2__U128":{ + "affine_func$mul_d0__U1301":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U130":{ + "affine_func$mul_d1__U1303":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -10900,238 +11883,100 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U138$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U138$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U139$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U139$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U140$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U140$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U141$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U141$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U142$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U142$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U143$c0_lutcnst":{ + "d_0_am__U1309$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U143$lut$lut":{ + "d_0_am__U1309$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_2_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_2_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_3_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000003f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -11155,16 +12000,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -11172,33 +12007,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U136.out"], - ["d_1_inc.in1","_U1361.out"], - ["d_2_inc.in1","_U1362.out"], - ["d_3_inc.in1","_U1363.out"], - ["cmp_time.in1","_U137.out"], - ["affine_func$mul_d0__U124.out","affine_func$add_all__U132.in0"], - ["affine_func$mul_d1__U126.out","affine_func$add_all__U132.in1"], - ["affine_func$add_all__U133.in0","affine_func$add_all__U132.out"], - ["affine_func$mul_d2__U128.out","affine_func$add_all__U133.in1"], - ["affine_func$add_all__U134.in0","affine_func$add_all__U133.out"], - ["affine_func$mul_d3__U130.out","affine_func$add_all__U134.in1"], - ["affine_func$add_all__U135.in0","affine_func$add_all__U134.out"], - ["affine_func$const_term_U131.out","affine_func$add_all__U135.in1"], - ["time_diff.in0","affine_func$add_all__U135.out"], - ["affine_func$mul_d0__U124.in0","affine_func$coeff_0_U123.out"], - ["affine_func$mul_d1__U126.in0","affine_func$coeff_1_U125.out"], - ["affine_func$mul_d2__U128.in0","affine_func$coeff_2_U127.out"], - ["affine_func$mul_d3__U130.in0","affine_func$coeff_3_U129.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U124.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U126.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U128.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U130.in1"], + ["d_0_inc.in1","_U1307.out"], + ["d_1_inc.in1","_U13071.out"], + ["cmp_time.in1","_U1308.out"], + ["affine_func$mul_d0__U1301.out","affine_func$add_all__U1305.in0"], + ["affine_func$mul_d1__U1303.out","affine_func$add_all__U1305.in1"], + ["affine_func$add_all__U1306.in0","affine_func$add_all__U1305.out"], + ["affine_func$const_term_U1304.out","affine_func$add_all__U1306.in1"], + ["time_diff.in0","affine_func$add_all__U1306.out"], + ["affine_func$mul_d0__U1301.in0","affine_func$coeff_0_U1300.out"], + ["affine_func$mul_d1__U1303.in0","affine_func$coeff_1_U1302.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1301.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1303.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -11206,28 +12029,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U138$lut$lut.bit.in.2","d_0_am__U138$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U138$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U138$lut$lut.bit.in.1"], - ["d_0_am__U139$lut$lut.bit.in.0","d_0_am__U138$lut$lut.bit.out"], - ["d_0_am__U139$lut$lut.bit.in.2","d_0_am__U139$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U139$lut$lut.bit.in.1"], - ["d_0_am__U140$lut$lut.bit.in.0","d_0_am__U139$lut$lut.bit.out"], - ["d_0_am__U140$lut$lut.bit.in.2","d_0_am__U140$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U140$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U140$lut$lut.bit.out"], + ["d_0_am__U1309$lut$lut.bit.in.2","d_0_am__U1309$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1309$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1309$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1309$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11244,13 +12061,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U141$lut$lut.bit.in.2","d_1_am__U141$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U141$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U141$lut$lut.bit.in.1"], - ["d_1_am__U142$lut$lut.bit.in.0","d_1_am__U141$lut$lut.bit.out"], - ["d_1_am__U142$lut$lut.bit.in.2","d_1_am__U142$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U142$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U142$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -11260,229 +12070,67 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U143$lut$lut.bit.in.2","d_2_am__U143$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U143$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U143$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U143$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1243":{ + "affine_controller__U1312":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",9,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1273":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12731":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12732":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12733":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12734":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12735":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U12736":{ + "_U1321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U12737":{ + "_U13211":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U12738":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1274":{ + "_U1322":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1264":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1265":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1266":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1267":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1268":{ + "affine_func$add_all__U1319":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1269":{ + "affine_func$add_all__U1320":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1270":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1271":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1272":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U1245":{ + "affine_func$coeff_0_U1314":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1247":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00009000"]} - }, - "affine_func$coeff_2_U1249":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00004800"]} - }, - "affine_func$coeff_3_U1251":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001800"]} - }, - "affine_func$coeff_4_U1253":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000800"]} - }, - "affine_func$coeff_5_U1255":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000200"]} - }, - "affine_func$coeff_6_U1257":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} - }, - "affine_func$coeff_7_U1259":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "affine_func$coeff_8_U1261":{ + "affine_func$coeff_1_U1316":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1263":{ + "affine_func$const_term_U1318":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00011fff"]} - }, - "affine_func$mul_d0__U1246":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U1248":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d2__U1250":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d3__U1252":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d4__U1254":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d5__U1256":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d6__U1258":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d7__U1260":{ + "affine_func$mul_d0__U1315":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d8__U1262":{ + "affine_func$mul_d1__U1317":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -11546,82 +12194,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1275$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1275$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1276$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1276$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1277$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1277$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1278$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1278$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1279$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1279$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1280$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1280$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1281$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1281$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1282$c0_lutcnst":{ + "d_0_am__U1323$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1282$lut$lut":{ + "d_0_am__U1323$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -11670,76 +12248,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1283$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1283$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1284$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1284$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1285$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1285$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1286$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1286$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1287$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1287$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1288$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1288$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1289$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1289$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -11751,7 +12259,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -11784,520 +12292,624 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1290$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1290$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U1291$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1291$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U1292$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1292$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U1293$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1293$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} }, - "d_2_am__U1294$c0_lutcnst":{ + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U1294$lut$lut":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U1295$c0_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U1295$lut$lut":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U1321.out"], + ["d_1_inc.in1","_U13211.out"], + ["cmp_time.in1","_U1322.out"], + ["affine_func$mul_d0__U1315.out","affine_func$add_all__U1319.in0"], + ["affine_func$mul_d1__U1317.out","affine_func$add_all__U1319.in1"], + ["affine_func$add_all__U1320.in0","affine_func$add_all__U1319.out"], + ["affine_func$const_term_U1318.out","affine_func$add_all__U1320.in1"], + ["time_diff.in0","affine_func$add_all__U1320.out"], + ["affine_func$mul_d0__U1315.in0","affine_func$coeff_0_U1314.out"], + ["affine_func$mul_d1__U1317.in0","affine_func$coeff_1_U1316.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1315.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1317.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true2_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U1323$lut$lut.bit.in.2","d_0_am__U1323$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1323$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1323$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1323$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"] + ] + }, + "affine_controller__U1326":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U1335":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_min":{ + "_U13351":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_reg$c0":{ + "_U1336":{ "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U1296$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U1296$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U1297$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U1297$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U1298$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U1298$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U1299$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U1299$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U1300$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U1300$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", + "affine_func$add_all__U1333":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_inc":{ + "affine_func$add_all__U1334":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_3_max":{ + "affine_func$coeff_0_U1328":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_min":{ + "affine_func$coeff_1_U1330":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ - "genref":"coreir.mux", + "affine_func$const_term_U1332":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "affine_func$mul_d0__U1329":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", + "affine_func$mul_d1__U1331":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_3_reg$c0":{ + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_reg$clrMux":{ + "cycle_time$count$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$enMux":{ + "cycle_time$count$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ + "cycle_time$count$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U1301$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_4_am__U1301$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} }, - "d_4_am__U1302$c0_lutcnst":{ + "cycle_time$resetOr$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U1302$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U1303$c0_lutcnst":{ + "cycle_time$resetOr$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} }, - "d_4_am__U1303$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} }, - "d_4_am__U1304$c0_lutcnst":{ + "d_0_am__U1337$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U1304$lut$lut":{ + "d_0_am__U1337$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U1305$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U1305$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U1306$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U1306$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U1307$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U1307$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U1308$c0_lutcnst":{ + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_6_am__U1308$lut$lut":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_6_am__U1309$c0_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_6_am__U1309$lut$lut":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U1335.out"], + ["d_1_inc.in1","_U13351.out"], + ["cmp_time.in1","_U1336.out"], + ["affine_func$mul_d0__U1329.out","affine_func$add_all__U1333.in0"], + ["affine_func$mul_d1__U1331.out","affine_func$add_all__U1333.in1"], + ["affine_func$add_all__U1334.in0","affine_func$add_all__U1333.out"], + ["affine_func$const_term_U1332.out","affine_func$add_all__U1334.in1"], + ["time_diff.in0","affine_func$add_all__U1334.out"], + ["affine_func$mul_d0__U1329.in0","affine_func$coeff_0_U1328.out"], + ["affine_func$mul_d1__U1331.in0","affine_func$coeff_1_U1330.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1329.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1331.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U1337$lut$lut.bit.in.2","d_0_am__U1337$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1337$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1337$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1337$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"] + ] + }, + "affine_controller__U1340":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U1349":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_6_at_max":{ - "genref":"coreir.eq", + "_U13491":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1350":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$add_all__U1347":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_6_inc":{ + "affine_func$add_all__U1348":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_6_max":{ + "affine_func$coeff_0_U1342":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_min":{ + "affine_func$coeff_1_U1344":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_next_value":{ - "genref":"coreir.mux", + "affine_func$const_term_U1346":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "affine_func$mul_d0__U1343":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_6_next_value_at_max":{ - "genref":"coreir.mux", + "affine_func$mul_d1__U1345":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_6_reg$c0":{ + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_reg$clrMux":{ + "cycle_time$count$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$enMux":{ + "cycle_time$count$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$reg0":{ + "cycle_time$count$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_7_am__U1310$c0_lutcnst":{ + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} + }, + "d_0_am__U1351$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_7_am__U1310$lut$lut":{ + "d_0_am__U1351$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_7_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_7_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_7_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_8_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_8_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_8_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_8_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_8_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_8_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_8_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_8_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_8_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_8_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -12306,11 +12918,6 @@ "genref":"coreir.sub", "genargs":{"width":["Int",32]} }, - "true10_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -12326,36 +12933,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -12363,63 +12940,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U1273.out"], - ["d_1_inc.in1","_U12731.out"], - ["d_2_inc.in1","_U12732.out"], - ["d_3_inc.in1","_U12733.out"], - ["d_4_inc.in1","_U12734.out"], - ["d_5_inc.in1","_U12735.out"], - ["d_6_inc.in1","_U12736.out"], - ["d_7_inc.in1","_U12737.out"], - ["d_8_inc.in1","_U12738.out"], - ["cmp_time.in1","_U1274.out"], - ["affine_func$mul_d0__U1246.out","affine_func$add_all__U1264.in0"], - ["affine_func$mul_d1__U1248.out","affine_func$add_all__U1264.in1"], - ["affine_func$add_all__U1265.in0","affine_func$add_all__U1264.out"], - ["affine_func$mul_d2__U1250.out","affine_func$add_all__U1265.in1"], - ["affine_func$add_all__U1266.in0","affine_func$add_all__U1265.out"], - ["affine_func$mul_d3__U1252.out","affine_func$add_all__U1266.in1"], - ["affine_func$add_all__U1267.in0","affine_func$add_all__U1266.out"], - ["affine_func$mul_d4__U1254.out","affine_func$add_all__U1267.in1"], - ["affine_func$add_all__U1268.in0","affine_func$add_all__U1267.out"], - ["affine_func$mul_d5__U1256.out","affine_func$add_all__U1268.in1"], - ["affine_func$add_all__U1269.in0","affine_func$add_all__U1268.out"], - ["affine_func$mul_d6__U1258.out","affine_func$add_all__U1269.in1"], - ["affine_func$add_all__U1270.in0","affine_func$add_all__U1269.out"], - ["affine_func$mul_d7__U1260.out","affine_func$add_all__U1270.in1"], - ["affine_func$add_all__U1271.in0","affine_func$add_all__U1270.out"], - ["affine_func$mul_d8__U1262.out","affine_func$add_all__U1271.in1"], - ["affine_func$add_all__U1272.in0","affine_func$add_all__U1271.out"], - ["affine_func$const_term_U1263.out","affine_func$add_all__U1272.in1"], - ["time_diff.in0","affine_func$add_all__U1272.out"], - ["affine_func$mul_d0__U1246.in0","affine_func$coeff_0_U1245.out"], - ["affine_func$mul_d1__U1248.in0","affine_func$coeff_1_U1247.out"], - ["affine_func$mul_d2__U1250.in0","affine_func$coeff_2_U1249.out"], - ["affine_func$mul_d3__U1252.in0","affine_func$coeff_3_U1251.out"], - ["affine_func$mul_d4__U1254.in0","affine_func$coeff_4_U1253.out"], - ["affine_func$mul_d5__U1256.in0","affine_func$coeff_5_U1255.out"], - ["affine_func$mul_d6__U1258.in0","affine_func$coeff_6_U1257.out"], - ["affine_func$mul_d7__U1260.in0","affine_func$coeff_7_U1259.out"], - ["affine_func$mul_d8__U1262.in0","affine_func$coeff_8_U1261.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1246.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1248.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U1250.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U1252.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U1254.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U1256.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U1258.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U1260.in1"], - ["d_8_reg$reg0.out","affine_func$mul_d8__U1262.in1"], + ["d_0_inc.in1","_U1349.out"], + ["d_1_inc.in1","_U13491.out"], + ["cmp_time.in1","_U1350.out"], + ["affine_func$mul_d0__U1343.out","affine_func$add_all__U1347.in0"], + ["affine_func$mul_d1__U1345.out","affine_func$add_all__U1347.in1"], + ["affine_func$add_all__U1348.in0","affine_func$add_all__U1347.out"], + ["affine_func$const_term_U1346.out","affine_func$add_all__U1348.in1"], + ["time_diff.in0","affine_func$add_all__U1348.out"], + ["affine_func$mul_d0__U1343.in0","affine_func$coeff_0_U1342.out"], + ["affine_func$mul_d1__U1345.in0","affine_func$coeff_1_U1344.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1343.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1345.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], - ["d_7_reg$enMux.sel","cmp_time.out"], - ["d_8_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -12427,43 +12962,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true10_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true9_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1275$lut$lut.bit.in.2","d_0_am__U1275$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1275$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1275$lut$lut.bit.in.1"], - ["d_0_am__U1276$lut$lut.bit.in.0","d_0_am__U1275$lut$lut.bit.out"], - ["d_0_am__U1276$lut$lut.bit.in.2","d_0_am__U1276$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U1276$lut$lut.bit.in.1"], - ["d_0_am__U1277$lut$lut.bit.in.0","d_0_am__U1276$lut$lut.bit.out"], - ["d_0_am__U1277$lut$lut.bit.in.2","d_0_am__U1277$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U1277$lut$lut.bit.in.1"], - ["d_0_am__U1278$lut$lut.bit.in.0","d_0_am__U1277$lut$lut.bit.out"], - ["d_0_am__U1278$lut$lut.bit.in.2","d_0_am__U1278$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U1278$lut$lut.bit.in.1"], - ["d_0_am__U1279$lut$lut.bit.in.0","d_0_am__U1278$lut$lut.bit.out"], - ["d_0_am__U1279$lut$lut.bit.in.2","d_0_am__U1279$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U1279$lut$lut.bit.in.1"], - ["d_0_am__U1280$lut$lut.bit.in.0","d_0_am__U1279$lut$lut.bit.out"], - ["d_0_am__U1280$lut$lut.bit.in.2","d_0_am__U1280$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U1280$lut$lut.bit.in.1"], - ["d_0_am__U1281$lut$lut.bit.in.0","d_0_am__U1280$lut$lut.bit.out"], - ["d_0_am__U1281$lut$lut.bit.in.2","d_0_am__U1281$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U1281$lut$lut.bit.in.1"], - ["d_0_am__U1282$lut$lut.bit.in.0","d_0_am__U1281$lut$lut.bit.out"], - ["d_0_am__U1282$lut$lut.bit.in.2","d_0_am__U1282$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_0_am__U1282$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1282$lut$lut.bit.out"], + ["d_0_am__U1351$lut$lut.bit.in.2","d_0_am__U1351$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1351$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1351$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1351$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -12480,28 +12994,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U1283$lut$lut.bit.in.2","d_1_am__U1283$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U1283$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U1283$lut$lut.bit.in.1"], - ["d_1_am__U1284$lut$lut.bit.in.0","d_1_am__U1283$lut$lut.bit.out"], - ["d_1_am__U1284$lut$lut.bit.in.2","d_1_am__U1284$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U1284$lut$lut.bit.in.1"], - ["d_1_am__U1285$lut$lut.bit.in.0","d_1_am__U1284$lut$lut.bit.out"], - ["d_1_am__U1285$lut$lut.bit.in.2","d_1_am__U1285$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U1285$lut$lut.bit.in.1"], - ["d_1_am__U1286$lut$lut.bit.in.0","d_1_am__U1285$lut$lut.bit.out"], - ["d_1_am__U1286$lut$lut.bit.in.2","d_1_am__U1286$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U1286$lut$lut.bit.in.1"], - ["d_1_am__U1287$lut$lut.bit.in.0","d_1_am__U1286$lut$lut.bit.out"], - ["d_1_am__U1287$lut$lut.bit.in.2","d_1_am__U1287$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U1287$lut$lut.bit.in.1"], - ["d_1_am__U1288$lut$lut.bit.in.0","d_1_am__U1287$lut$lut.bit.out"], - ["d_1_am__U1288$lut$lut.bit.in.2","d_1_am__U1288$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U1288$lut$lut.bit.in.1"], - ["d_1_am__U1289$lut$lut.bit.in.0","d_1_am__U1288$lut$lut.bit.out"], - ["d_1_am__U1289$lut$lut.bit.in.2","d_1_am__U1289$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_1_am__U1289$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U1289$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -12511,198 +13003,17 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U1290$lut$lut.bit.in.2","d_2_am__U1290$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U1290$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U1290$lut$lut.bit.in.1"], - ["d_2_am__U1291$lut$lut.bit.in.0","d_2_am__U1290$lut$lut.bit.out"], - ["d_2_am__U1291$lut$lut.bit.in.2","d_2_am__U1291$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U1291$lut$lut.bit.in.1"], - ["d_2_am__U1292$lut$lut.bit.in.0","d_2_am__U1291$lut$lut.bit.out"], - ["d_2_am__U1292$lut$lut.bit.in.2","d_2_am__U1292$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U1292$lut$lut.bit.in.1"], - ["d_2_am__U1293$lut$lut.bit.in.0","d_2_am__U1292$lut$lut.bit.out"], - ["d_2_am__U1293$lut$lut.bit.in.2","d_2_am__U1293$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U1293$lut$lut.bit.in.1"], - ["d_2_am__U1294$lut$lut.bit.in.0","d_2_am__U1293$lut$lut.bit.out"], - ["d_2_am__U1294$lut$lut.bit.in.2","d_2_am__U1294$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U1294$lut$lut.bit.in.1"], - ["d_2_am__U1295$lut$lut.bit.in.0","d_2_am__U1294$lut$lut.bit.out"], - ["d_2_am__U1295$lut$lut.bit.in.2","d_2_am__U1295$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_2_am__U1295$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U1295$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U1296$lut$lut.bit.in.2","d_3_am__U1296$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U1296$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U1296$lut$lut.bit.in.1"], - ["d_3_am__U1297$lut$lut.bit.in.0","d_3_am__U1296$lut$lut.bit.out"], - ["d_3_am__U1297$lut$lut.bit.in.2","d_3_am__U1297$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U1297$lut$lut.bit.in.1"], - ["d_3_am__U1298$lut$lut.bit.in.0","d_3_am__U1297$lut$lut.bit.out"], - ["d_3_am__U1298$lut$lut.bit.in.2","d_3_am__U1298$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U1298$lut$lut.bit.in.1"], - ["d_3_am__U1299$lut$lut.bit.in.0","d_3_am__U1298$lut$lut.bit.out"], - ["d_3_am__U1299$lut$lut.bit.in.2","d_3_am__U1299$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U1299$lut$lut.bit.in.1"], - ["d_3_am__U1300$lut$lut.bit.in.0","d_3_am__U1299$lut$lut.bit.out"], - ["d_3_am__U1300$lut$lut.bit.in.2","d_3_am__U1300$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_3_am__U1300$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U1300$lut$lut.bit.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U1301$lut$lut.bit.in.2","d_4_am__U1301$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U1301$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U1301$lut$lut.bit.in.1"], - ["d_4_am__U1302$lut$lut.bit.in.0","d_4_am__U1301$lut$lut.bit.out"], - ["d_4_am__U1302$lut$lut.bit.in.2","d_4_am__U1302$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U1302$lut$lut.bit.in.1"], - ["d_4_am__U1303$lut$lut.bit.in.0","d_4_am__U1302$lut$lut.bit.out"], - ["d_4_am__U1303$lut$lut.bit.in.2","d_4_am__U1303$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U1303$lut$lut.bit.in.1"], - ["d_4_am__U1304$lut$lut.bit.in.0","d_4_am__U1303$lut$lut.bit.out"], - ["d_4_am__U1304$lut$lut.bit.in.2","d_4_am__U1304$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_4_am__U1304$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U1304$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U1305$lut$lut.bit.in.2","d_5_am__U1305$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U1305$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U1305$lut$lut.bit.in.1"], - ["d_5_am__U1306$lut$lut.bit.in.0","d_5_am__U1305$lut$lut.bit.out"], - ["d_5_am__U1306$lut$lut.bit.in.2","d_5_am__U1306$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U1306$lut$lut.bit.in.1"], - ["d_5_am__U1307$lut$lut.bit.in.0","d_5_am__U1306$lut$lut.bit.out"], - ["d_5_am__U1307$lut$lut.bit.in.2","d_5_am__U1307$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_5_am__U1307$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U1307$lut$lut.bit.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U1308$lut$lut.bit.in.2","d_6_am__U1308$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U1308$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U1308$lut$lut.bit.in.1"], - ["d_6_am__U1309$lut$lut.bit.in.0","d_6_am__U1308$lut$lut.bit.out"], - ["d_6_am__U1309$lut$lut.bit.in.2","d_6_am__U1309$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_6_am__U1309$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U1309$lut$lut.bit.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"], - ["d_7_am__U1310$lut$lut.bit.in.2","d_7_am__U1310$c0_lutcnst.bit.out"], - ["true8_lutcnst.bit.out","d_7_am__U1310$lut$lut.bit.in.0"], - ["d_8_at_max.out","d_7_am__U1310$lut$lut.bit.in.1"], - ["d_7_next_value.sel","d_7_am__U1310$lut$lut.bit.out"], - ["d_7_reg$reg0.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg$reg0.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg$reg0.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg$enMux.in1","d_7_next_value.out"], - ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], - ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], - ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], - ["self.rst_n","d_7_reg$clrMux.sel"], - ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], - ["self.clk","d_7_reg$reg0.clk"], - ["self.d.7","d_7_reg$reg0.out"], - ["d_8_reg$reg0.out","d_8_at_max.in0"], - ["d_8_max.out","d_8_at_max.in1"], - ["d_8_next_value_at_max.sel","d_8_at_max.out"], - ["d_8_reg$reg0.out","d_8_inc.in0"], - ["d_8_next_value_at_max.in0","d_8_inc.out"], - ["d_8_next_value_at_max.in1","d_8_min.out"], - ["d_8_reg$reg0.out","d_8_next_value.in0"], - ["d_8_next_value_at_max.out","d_8_next_value.in1"], - ["d_8_reg$enMux.in1","d_8_next_value.out"], - ["true_lutcnst.bit.out","d_8_next_value.sel"], - ["d_8_reg$clrMux.in1","d_8_reg$c0.out"], - ["d_8_reg$enMux.out","d_8_reg$clrMux.in0"], - ["d_8_reg$reg0.in","d_8_reg$clrMux.out"], - ["self.rst_n","d_8_reg$clrMux.sel"], - ["d_8_reg$reg0.out","d_8_reg$enMux.in0"], - ["self.clk","d_8_reg$reg0.clk"], - ["self.d.8","d_8_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1344":{ + "affine_controller__U1354":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -12710,49 +13021,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1353":{ + "_U1363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U13531":{ + "_U13631":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1354":{ + "_U1364":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1351":{ + "affine_func$add_all__U1361":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1352":{ + "affine_func$add_all__U1362":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1346":{ + "affine_func$coeff_0_U1356":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1348":{ + "affine_func$coeff_1_U1358":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1350":{ + "affine_func$const_term_U1360":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1347":{ + "affine_func$mul_d0__U1357":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1349":{ + "affine_func$mul_d1__U1359":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -12816,12 +13127,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1355$c0_lutcnst":{ + "d_0_am__U1365$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1355$lut$lut":{ + "d_0_am__U1365$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -12940,18 +13251,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1353.out"], - ["d_1_inc.in1","_U13531.out"], - ["cmp_time.in1","_U1354.out"], - ["affine_func$mul_d0__U1347.out","affine_func$add_all__U1351.in0"], - ["affine_func$mul_d1__U1349.out","affine_func$add_all__U1351.in1"], - ["affine_func$add_all__U1352.in0","affine_func$add_all__U1351.out"], - ["affine_func$const_term_U1350.out","affine_func$add_all__U1352.in1"], - ["time_diff.in0","affine_func$add_all__U1352.out"], - ["affine_func$mul_d0__U1347.in0","affine_func$coeff_0_U1346.out"], - ["affine_func$mul_d1__U1349.in0","affine_func$coeff_1_U1348.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1347.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1349.in1"], + ["d_0_inc.in1","_U1363.out"], + ["d_1_inc.in1","_U13631.out"], + ["cmp_time.in1","_U1364.out"], + ["affine_func$mul_d0__U1357.out","affine_func$add_all__U1361.in0"], + ["affine_func$mul_d1__U1359.out","affine_func$add_all__U1361.in1"], + ["affine_func$add_all__U1362.in0","affine_func$add_all__U1361.out"], + ["affine_func$const_term_U1360.out","affine_func$add_all__U1362.in1"], + ["time_diff.in0","affine_func$add_all__U1362.out"], + ["affine_func$mul_d0__U1357.in0","affine_func$coeff_0_U1356.out"], + ["affine_func$mul_d1__U1359.in0","affine_func$coeff_1_U1358.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1357.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1359.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -12974,10 +13285,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1355$lut$lut.bit.in.2","d_0_am__U1355$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1355$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1355$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1355$lut$lut.bit.out"], + ["d_0_am__U1365$lut$lut.bit.in.2","d_0_am__U1365$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1365$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1365$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1365$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13013,7 +13324,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1359":{ + "affine_controller__U1368":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -13021,49 +13332,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1368":{ + "_U1377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U13681":{ + "_U13771":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1369":{ + "_U1378":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1366":{ + "affine_func$add_all__U1375":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1367":{ + "affine_func$add_all__U1376":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1361":{ + "affine_func$coeff_0_U1370":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1363":{ + "affine_func$coeff_1_U1372":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1365":{ + "affine_func$const_term_U1374":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1362":{ + "affine_func$mul_d0__U1371":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1364":{ + "affine_func$mul_d1__U1373":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -13127,12 +13438,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1370$c0_lutcnst":{ + "d_0_am__U1379$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1370$lut$lut":{ + "d_0_am__U1379$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -13251,18 +13562,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1368.out"], - ["d_1_inc.in1","_U13681.out"], - ["cmp_time.in1","_U1369.out"], - ["affine_func$mul_d0__U1362.out","affine_func$add_all__U1366.in0"], - ["affine_func$mul_d1__U1364.out","affine_func$add_all__U1366.in1"], - ["affine_func$add_all__U1367.in0","affine_func$add_all__U1366.out"], - ["affine_func$const_term_U1365.out","affine_func$add_all__U1367.in1"], - ["time_diff.in0","affine_func$add_all__U1367.out"], - ["affine_func$mul_d0__U1362.in0","affine_func$coeff_0_U1361.out"], - ["affine_func$mul_d1__U1364.in0","affine_func$coeff_1_U1363.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1362.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1364.in1"], + ["d_0_inc.in1","_U1377.out"], + ["d_1_inc.in1","_U13771.out"], + ["cmp_time.in1","_U1378.out"], + ["affine_func$mul_d0__U1371.out","affine_func$add_all__U1375.in0"], + ["affine_func$mul_d1__U1373.out","affine_func$add_all__U1375.in1"], + ["affine_func$add_all__U1376.in0","affine_func$add_all__U1375.out"], + ["affine_func$const_term_U1374.out","affine_func$add_all__U1376.in1"], + ["time_diff.in0","affine_func$add_all__U1376.out"], + ["affine_func$mul_d0__U1371.in0","affine_func$coeff_0_U1370.out"], + ["affine_func$mul_d1__U1373.in0","affine_func$coeff_1_U1372.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1371.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1373.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -13285,10 +13596,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1370$lut$lut.bit.in.2","d_0_am__U1370$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1370$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1370$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1370$lut$lut.bit.out"], + ["d_0_am__U1379$lut$lut.bit.in.2","d_0_am__U1379$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1379$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1379$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1379$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13324,57 +13635,129 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1374":{ + "affine_controller__U1381":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",6,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1383":{ + "_U1402":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U14021":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U14022":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U14023":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U14024":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U13831":{ + "_U14025":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1384":{ + "_U1403":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1381":{ + "affine_func$add_all__U1396":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1382":{ + "affine_func$add_all__U1398":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1376":{ + "affine_func$add_all__U1399":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1400":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1401":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U1383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1378":{ + "affine_func$coeff_1_U1385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "affine_func$const_term_U1380":{ + "affine_func$coeff_2_U1387":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} + "modargs":{"value":[["BitVector",32],"32'h000001c0"]} + }, + "affine_func$coeff_3_U1389":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_4_U1391":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} + }, + "affine_func$coeff_5_U1393":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U1395":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0001e720"]} }, - "affine_func$mul_d0__U1377":{ + "affine_func$mul_d0__U1384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1379":{ + "affine_func$mul_d1__U1386":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U1388":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U1390":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d4__U1392":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U1394":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -13438,12 +13821,52 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1385$c0_lutcnst":{ + "d_0_am__U1404$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1404$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1405$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1405$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1406$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1385$lut$lut":{ + "d_0_am__U1406$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1407$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1407$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1408$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1408$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -13492,6 +13915,46 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1409$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1409$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1410$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1410$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1411$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1411$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1412$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1412$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -13503,7 +13966,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -13536,313 +13999,238 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ + "d_2_am__U1413$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true2_lutcnst":{ + "d_2_am__U1413$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true3_lutcnst":{ + "d_2_am__U1414$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true_lutcnst":{ + "d_2_am__U1414$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U1383.out"], - ["d_1_inc.in1","_U13831.out"], - ["cmp_time.in1","_U1384.out"], - ["affine_func$mul_d0__U1377.out","affine_func$add_all__U1381.in0"], - ["affine_func$mul_d1__U1379.out","affine_func$add_all__U1381.in1"], - ["affine_func$add_all__U1382.in0","affine_func$add_all__U1381.out"], - ["affine_func$const_term_U1380.out","affine_func$add_all__U1382.in1"], - ["time_diff.in0","affine_func$add_all__U1382.out"], - ["affine_func$mul_d0__U1377.in0","affine_func$coeff_0_U1376.out"], - ["affine_func$mul_d1__U1379.in0","affine_func$coeff_1_U1378.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1377.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1379.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1385$lut$lut.bit.in.2","d_0_am__U1385$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1385$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1385$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1385$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] - ] - }, - "affine_controller__U1389":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1398":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "_U13981":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "d_2_am__U1415$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "_U1399":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "d_2_am__U1415$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "affine_func$add_all__U1396":{ - "genref":"coreir.add", + "d_2_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1397":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1391":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, - "affine_func$coeff_1_U1393":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1395":{ + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U1392":{ - "genref":"coreir.mul", + "d_2_reg$clrMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1394":{ - "genref":"coreir.mul", + "d_2_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_3_am__U1416$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$c0_lutcnst":{ + "d_3_am__U1416$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U1417$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$lut$lut":{ + "d_3_am__U1417$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$c0":{ + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000006"]} + }, + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$count$clrMux":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$enMux":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cycle_time$ult":{ - "genref":"coreir.ult", + "d_3_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_am__U1400$c0_lutcnst":{ + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U1418$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1400$lut$lut":{ + "d_4_am__U1418$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_0_min":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_4_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_4_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_4_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_4_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_4_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_4_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_5_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_1_min":{ + "d_5_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_5_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_5_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$c0":{ + "d_5_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ + "d_5_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ + "d_5_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ + "d_5_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -13866,6 +14254,26 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true7_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -13873,21 +14281,45 @@ } }, "connections":[ - ["d_0_inc.in1","_U1398.out"], - ["d_1_inc.in1","_U13981.out"], - ["cmp_time.in1","_U1399.out"], - ["affine_func$mul_d0__U1392.out","affine_func$add_all__U1396.in0"], - ["affine_func$mul_d1__U1394.out","affine_func$add_all__U1396.in1"], + ["d_0_inc.in1","_U1402.out"], + ["d_1_inc.in1","_U14021.out"], + ["d_2_inc.in1","_U14022.out"], + ["d_3_inc.in1","_U14023.out"], + ["d_4_inc.in1","_U14024.out"], + ["d_5_inc.in1","_U14025.out"], + ["cmp_time.in1","_U1403.out"], + ["affine_func$mul_d0__U1384.out","affine_func$add_all__U1396.in0"], + ["affine_func$mul_d1__U1386.out","affine_func$add_all__U1396.in1"], ["affine_func$add_all__U1397.in0","affine_func$add_all__U1396.out"], - ["affine_func$const_term_U1395.out","affine_func$add_all__U1397.in1"], - ["time_diff.in0","affine_func$add_all__U1397.out"], - ["affine_func$mul_d0__U1392.in0","affine_func$coeff_0_U1391.out"], - ["affine_func$mul_d1__U1394.in0","affine_func$coeff_1_U1393.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1392.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1394.in1"], + ["affine_func$mul_d2__U1388.out","affine_func$add_all__U1397.in1"], + ["affine_func$add_all__U1398.in0","affine_func$add_all__U1397.out"], + ["affine_func$mul_d3__U1390.out","affine_func$add_all__U1398.in1"], + ["affine_func$add_all__U1399.in0","affine_func$add_all__U1398.out"], + ["affine_func$mul_d4__U1392.out","affine_func$add_all__U1399.in1"], + ["affine_func$add_all__U1400.in0","affine_func$add_all__U1399.out"], + ["affine_func$mul_d5__U1394.out","affine_func$add_all__U1400.in1"], + ["affine_func$add_all__U1401.in0","affine_func$add_all__U1400.out"], + ["affine_func$const_term_U1395.out","affine_func$add_all__U1401.in1"], + ["time_diff.in0","affine_func$add_all__U1401.out"], + ["affine_func$mul_d0__U1384.in0","affine_func$coeff_0_U1383.out"], + ["affine_func$mul_d1__U1386.in0","affine_func$coeff_1_U1385.out"], + ["affine_func$mul_d2__U1388.in0","affine_func$coeff_2_U1387.out"], + ["affine_func$mul_d3__U1390.in0","affine_func$coeff_3_U1389.out"], + ["affine_func$mul_d4__U1392.in0","affine_func$coeff_4_U1391.out"], + ["affine_func$mul_d5__U1394.in0","affine_func$coeff_5_U1393.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1384.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1386.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U1388.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U1390.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U1392.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U1394.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -13895,22 +14327,34 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1400$lut$lut.bit.in.2","d_0_am__U1400$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1400$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1400$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1400$lut$lut.bit.out"], + ["d_0_am__U1404$lut$lut.bit.in.2","d_0_am__U1404$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1404$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1404$lut$lut.bit.in.1"], + ["d_0_am__U1405$lut$lut.bit.in.0","d_0_am__U1404$lut$lut.bit.out"], + ["d_0_am__U1405$lut$lut.bit.in.2","d_0_am__U1405$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U1405$lut$lut.bit.in.1"], + ["d_0_am__U1406$lut$lut.bit.in.0","d_0_am__U1405$lut$lut.bit.out"], + ["d_0_am__U1406$lut$lut.bit.in.2","d_0_am__U1406$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U1406$lut$lut.bit.in.1"], + ["d_0_am__U1407$lut$lut.bit.in.0","d_0_am__U1406$lut$lut.bit.out"], + ["d_0_am__U1407$lut$lut.bit.in.2","d_0_am__U1407$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U1407$lut$lut.bit.in.1"], + ["d_0_am__U1408$lut$lut.bit.in.0","d_0_am__U1407$lut$lut.bit.out"], + ["d_0_am__U1408$lut$lut.bit.in.2","d_0_am__U1408$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U1408$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1408$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -13927,6 +14371,19 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U1409$lut$lut.bit.in.2","d_1_am__U1409$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U1409$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U1409$lut$lut.bit.in.1"], + ["d_1_am__U1410$lut$lut.bit.in.0","d_1_am__U1409$lut$lut.bit.out"], + ["d_1_am__U1410$lut$lut.bit.in.2","d_1_am__U1410$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U1410$lut$lut.bit.in.1"], + ["d_1_am__U1411$lut$lut.bit.in.0","d_1_am__U1410$lut$lut.bit.out"], + ["d_1_am__U1411$lut$lut.bit.in.2","d_1_am__U1411$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U1411$lut$lut.bit.in.1"], + ["d_1_am__U1412$lut$lut.bit.in.0","d_1_am__U1411$lut$lut.bit.out"], + ["d_1_am__U1412$lut$lut.bit.in.2","d_1_am__U1412$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U1412$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U1412$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -13936,67 +14393,188 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U1413$lut$lut.bit.in.2","d_2_am__U1413$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U1413$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U1413$lut$lut.bit.in.1"], + ["d_2_am__U1414$lut$lut.bit.in.0","d_2_am__U1413$lut$lut.bit.out"], + ["d_2_am__U1414$lut$lut.bit.in.2","d_2_am__U1414$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U1414$lut$lut.bit.in.1"], + ["d_2_am__U1415$lut$lut.bit.in.0","d_2_am__U1414$lut$lut.bit.out"], + ["d_2_am__U1415$lut$lut.bit.in.2","d_2_am__U1415$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U1415$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U1415$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U1416$lut$lut.bit.in.2","d_3_am__U1416$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U1416$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U1416$lut$lut.bit.in.1"], + ["d_3_am__U1417$lut$lut.bit.in.0","d_3_am__U1416$lut$lut.bit.out"], + ["d_3_am__U1417$lut$lut.bit.in.2","d_3_am__U1417$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U1417$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U1417$lut$lut.bit.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U1418$lut$lut.bit.in.2","d_4_am__U1418$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U1418$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U1418$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U1418$lut$lut.bit.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["true_lutcnst.bit.out","d_5_next_value.sel"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"] ] }, - "affine_controller__U1404":{ + "affine_controller__U1441":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1413":{ + "_U1456":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U14561":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14131":{ + "_U14562":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1414":{ + "_U14563":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1457":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1411":{ + "affine_func$add_all__U1452":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1453":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1454":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1412":{ + "affine_func$add_all__U1455":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1406":{ + "affine_func$coeff_0_U1443":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1408":{ + "affine_func$coeff_1_U1445":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "affine_func$const_term_U1410":{ + "affine_func$coeff_2_U1447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} + "modargs":{"value":[["BitVector",32],"32'h00000080"]} + }, + "affine_func$coeff_3_U1449":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U1451":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0002835f"]} + }, + "affine_func$mul_d0__U1444":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U1446":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U1407":{ + "affine_func$mul_d2__U1448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1409":{ + "affine_func$mul_d3__U1450":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -14060,12 +14638,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1415$c0_lutcnst":{ + "d_0_am__U1458$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1458$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1459$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1459$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1460$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1415$lut$lut":{ + "d_0_am__U1460$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -14114,6 +14712,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1461$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1461$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1462$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1462$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -14125,7 +14743,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_1_min":{ "genref":"coreir.const", @@ -14158,313 +14776,100 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true2_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true3_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U1413.out"], - ["d_1_inc.in1","_U14131.out"], - ["cmp_time.in1","_U1414.out"], - ["affine_func$mul_d0__U1407.out","affine_func$add_all__U1411.in0"], - ["affine_func$mul_d1__U1409.out","affine_func$add_all__U1411.in1"], - ["affine_func$add_all__U1412.in0","affine_func$add_all__U1411.out"], - ["affine_func$const_term_U1410.out","affine_func$add_all__U1412.in1"], - ["time_diff.in0","affine_func$add_all__U1412.out"], - ["affine_func$mul_d0__U1407.in0","affine_func$coeff_0_U1406.out"], - ["affine_func$mul_d1__U1409.in0","affine_func$coeff_1_U1408.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1407.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1409.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1415$lut$lut.bit.in.2","d_0_am__U1415$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1415$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1415$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1415$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] - ] - }, - "affine_controller__U1419":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U1428":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U14281":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1429":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$add_all__U1426":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1427":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U1421":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$coeff_1_U1423":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$const_term_U1425":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "affine_func$mul_d0__U1422":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U1424":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "cycle_time$and$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$and$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "cycle_time$count$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$count$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} - }, - "cycle_time$ult":{ - "genref":"coreir.ult", - "genargs":{"width":["Int",32]} - }, - "d_0_am__U1430$c0_lutcnst":{ + "d_2_am__U1463$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1430$lut$lut":{ + "d_2_am__U1463$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, - "d_0_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} }, - "d_1_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -14488,6 +14893,16 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -14495,21 +14910,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U1428.out"], - ["d_1_inc.in1","_U14281.out"], - ["cmp_time.in1","_U1429.out"], - ["affine_func$mul_d0__U1422.out","affine_func$add_all__U1426.in0"], - ["affine_func$mul_d1__U1424.out","affine_func$add_all__U1426.in1"], - ["affine_func$add_all__U1427.in0","affine_func$add_all__U1426.out"], - ["affine_func$const_term_U1425.out","affine_func$add_all__U1427.in1"], - ["time_diff.in0","affine_func$add_all__U1427.out"], - ["affine_func$mul_d0__U1422.in0","affine_func$coeff_0_U1421.out"], - ["affine_func$mul_d1__U1424.in0","affine_func$coeff_1_U1423.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1422.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1424.in1"], + ["d_0_inc.in1","_U1456.out"], + ["d_1_inc.in1","_U14561.out"], + ["d_2_inc.in1","_U14562.out"], + ["d_3_inc.in1","_U14563.out"], + ["cmp_time.in1","_U1457.out"], + ["affine_func$mul_d0__U1444.out","affine_func$add_all__U1452.in0"], + ["affine_func$mul_d1__U1446.out","affine_func$add_all__U1452.in1"], + ["affine_func$add_all__U1453.in0","affine_func$add_all__U1452.out"], + ["affine_func$mul_d2__U1448.out","affine_func$add_all__U1453.in1"], + ["affine_func$add_all__U1454.in0","affine_func$add_all__U1453.out"], + ["affine_func$mul_d3__U1450.out","affine_func$add_all__U1454.in1"], + ["affine_func$add_all__U1455.in0","affine_func$add_all__U1454.out"], + ["affine_func$const_term_U1451.out","affine_func$add_all__U1455.in1"], + ["time_diff.in0","affine_func$add_all__U1455.out"], + ["affine_func$mul_d0__U1444.in0","affine_func$coeff_0_U1443.out"], + ["affine_func$mul_d1__U1446.in0","affine_func$coeff_1_U1445.out"], + ["affine_func$mul_d2__U1448.in0","affine_func$coeff_2_U1447.out"], + ["affine_func$mul_d3__U1450.in0","affine_func$coeff_3_U1449.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1444.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1446.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U1448.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U1450.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -14517,22 +14944,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1430$lut$lut.bit.in.2","d_0_am__U1430$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1430$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1430$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1430$lut$lut.bit.out"], + ["d_0_am__U1458$lut$lut.bit.in.2","d_0_am__U1458$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1458$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1458$lut$lut.bit.in.1"], + ["d_0_am__U1459$lut$lut.bit.in.0","d_0_am__U1458$lut$lut.bit.out"], + ["d_0_am__U1459$lut$lut.bit.in.2","d_0_am__U1459$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U1459$lut$lut.bit.in.1"], + ["d_0_am__U1460$lut$lut.bit.in.0","d_0_am__U1459$lut$lut.bit.out"], + ["d_0_am__U1460$lut$lut.bit.in.2","d_0_am__U1460$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U1460$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1460$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14549,6 +14982,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U1461$lut$lut.bit.in.2","d_1_am__U1461$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U1461$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U1461$lut$lut.bit.in.1"], + ["d_1_am__U1462$lut$lut.bit.in.0","d_1_am__U1461$lut$lut.bit.out"], + ["d_1_am__U1462$lut$lut.bit.in.2","d_1_am__U1462$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U1462$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U1462$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -14558,67 +14998,139 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U1463$lut$lut.bit.in.2","d_2_am__U1463$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U1463$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U1463$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U1463$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U1434":{ + "affine_controller__U1481":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], + ["d",["Array",4,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1443":{ + "_U1496":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U14961":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14431":{ + "_U14962":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1444":{ + "_U14963":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1497":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1441":{ + "affine_func$add_all__U1492":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1442":{ + "affine_func$add_all__U1493":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1436":{ + "affine_func$add_all__U1494":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U1495":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U1483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1438":{ + "affine_func$coeff_1_U1485":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "affine_func$const_term_U1440":{ + "affine_func$coeff_2_U1487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} + "modargs":{"value":[["BitVector",32],"32'h00000080"]} }, - "affine_func$mul_d0__U1437":{ + "affine_func$coeff_3_U1489":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U1491":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00028360"]} + }, + "affine_func$mul_d0__U1484":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U1486":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U1488":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1439":{ + "affine_func$mul_d3__U1490":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -14682,12 +15194,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1445$c0_lutcnst":{ + "d_0_am__U1498$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1498$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1499$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1445$lut$lut":{ + "d_0_am__U1499$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U1500$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U1500$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -14736,6 +15268,26 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_1_am__U1501$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1501$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U1502$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U1502$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -14747,7 +15299,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000006"]} }, "d_1_min":{ "genref":"coreir.const", @@ -14780,6 +15332,104 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_2_am__U1503$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U1503$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000006"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000007f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -14799,6 +15449,16 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true4_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "true5_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -14806,21 +15466,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U1443.out"], - ["d_1_inc.in1","_U14431.out"], - ["cmp_time.in1","_U1444.out"], - ["affine_func$mul_d0__U1437.out","affine_func$add_all__U1441.in0"], - ["affine_func$mul_d1__U1439.out","affine_func$add_all__U1441.in1"], - ["affine_func$add_all__U1442.in0","affine_func$add_all__U1441.out"], - ["affine_func$const_term_U1440.out","affine_func$add_all__U1442.in1"], - ["time_diff.in0","affine_func$add_all__U1442.out"], - ["affine_func$mul_d0__U1437.in0","affine_func$coeff_0_U1436.out"], - ["affine_func$mul_d1__U1439.in0","affine_func$coeff_1_U1438.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1437.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1439.in1"], + ["d_0_inc.in1","_U1496.out"], + ["d_1_inc.in1","_U14961.out"], + ["d_2_inc.in1","_U14962.out"], + ["d_3_inc.in1","_U14963.out"], + ["cmp_time.in1","_U1497.out"], + ["affine_func$mul_d0__U1484.out","affine_func$add_all__U1492.in0"], + ["affine_func$mul_d1__U1486.out","affine_func$add_all__U1492.in1"], + ["affine_func$add_all__U1493.in0","affine_func$add_all__U1492.out"], + ["affine_func$mul_d2__U1488.out","affine_func$add_all__U1493.in1"], + ["affine_func$add_all__U1494.in0","affine_func$add_all__U1493.out"], + ["affine_func$mul_d3__U1490.out","affine_func$add_all__U1494.in1"], + ["affine_func$add_all__U1495.in0","affine_func$add_all__U1494.out"], + ["affine_func$const_term_U1491.out","affine_func$add_all__U1495.in1"], + ["time_diff.in0","affine_func$add_all__U1495.out"], + ["affine_func$mul_d0__U1484.in0","affine_func$coeff_0_U1483.out"], + ["affine_func$mul_d1__U1486.in0","affine_func$coeff_1_U1485.out"], + ["affine_func$mul_d2__U1488.in0","affine_func$coeff_2_U1487.out"], + ["affine_func$mul_d3__U1490.in0","affine_func$coeff_3_U1489.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U1484.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1486.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U1488.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U1490.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -14828,22 +15500,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1445$lut$lut.bit.in.2","d_0_am__U1445$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1445$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1445$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1445$lut$lut.bit.out"], + ["d_0_am__U1498$lut$lut.bit.in.2","d_0_am__U1498$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1498$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1498$lut$lut.bit.in.1"], + ["d_0_am__U1499$lut$lut.bit.in.0","d_0_am__U1498$lut$lut.bit.out"], + ["d_0_am__U1499$lut$lut.bit.in.2","d_0_am__U1499$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U1499$lut$lut.bit.in.1"], + ["d_0_am__U1500$lut$lut.bit.in.0","d_0_am__U1499$lut$lut.bit.out"], + ["d_0_am__U1500$lut$lut.bit.in.2","d_0_am__U1500$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U1500$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1500$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -14860,6 +15538,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U1501$lut$lut.bit.in.2","d_1_am__U1501$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U1501$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U1501$lut$lut.bit.in.1"], + ["d_1_am__U1502$lut$lut.bit.in.0","d_1_am__U1501$lut$lut.bit.out"], + ["d_1_am__U1502$lut$lut.bit.in.2","d_1_am__U1502$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U1502$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U1502$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -14869,17 +15554,53 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U1503$lut$lut.bit.in.2","d_2_am__U1503$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U1503$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U1503$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U1503$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U1449":{ + "affine_controller__U15":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -14887,49 +15608,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1458":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14581":{ + "_U241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1459":{ + "_U25":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1456":{ + "affine_func$add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1457":{ + "affine_func$add_all__U23":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1451":{ + "affine_func$coeff_0_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1453":{ + "affine_func$coeff_1_U19":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1455":{ + "affine_func$const_term_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1452":{ + "affine_func$mul_d0__U18":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1454":{ + "affine_func$mul_d1__U20":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -14993,12 +15714,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1460$c0_lutcnst":{ + "d_0_am__U26$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1460$lut$lut":{ + "d_0_am__U26$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -15117,18 +15838,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1458.out"], - ["d_1_inc.in1","_U14581.out"], - ["cmp_time.in1","_U1459.out"], - ["affine_func$mul_d0__U1452.out","affine_func$add_all__U1456.in0"], - ["affine_func$mul_d1__U1454.out","affine_func$add_all__U1456.in1"], - ["affine_func$add_all__U1457.in0","affine_func$add_all__U1456.out"], - ["affine_func$const_term_U1455.out","affine_func$add_all__U1457.in1"], - ["time_diff.in0","affine_func$add_all__U1457.out"], - ["affine_func$mul_d0__U1452.in0","affine_func$coeff_0_U1451.out"], - ["affine_func$mul_d1__U1454.in0","affine_func$coeff_1_U1453.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1452.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1454.in1"], + ["d_0_inc.in1","_U24.out"], + ["d_1_inc.in1","_U241.out"], + ["cmp_time.in1","_U25.out"], + ["affine_func$mul_d0__U18.out","affine_func$add_all__U22.in0"], + ["affine_func$mul_d1__U20.out","affine_func$add_all__U22.in1"], + ["affine_func$add_all__U23.in0","affine_func$add_all__U22.out"], + ["affine_func$const_term_U21.out","affine_func$add_all__U23.in1"], + ["time_diff.in0","affine_func$add_all__U23.out"], + ["affine_func$mul_d0__U18.in0","affine_func$coeff_0_U17.out"], + ["affine_func$mul_d1__U20.in0","affine_func$coeff_1_U19.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U18.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U20.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -15151,10 +15872,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1460$lut$lut.bit.in.2","d_0_am__U1460$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1460$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1460$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1460$lut$lut.bit.out"], + ["d_0_am__U26$lut$lut.bit.in.2","d_0_am__U26$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U26$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U26$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U26$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15190,129 +15911,147 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1464":{ + "affine_controller__U151":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",6,["Array",32,"Bit"]]], + ["d",["Array",7,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1485":{ + "_U175":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U1751":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14851":{ + "_U1752":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14852":{ + "_U1753":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14853":{ + "_U1754":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14854":{ + "_U1755":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U14855":{ + "_U1756":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1486":{ + "_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1479":{ + "affine_func$add_all__U168":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1480":{ + "affine_func$add_all__U169":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1481":{ + "affine_func$add_all__U170":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1482":{ + "affine_func$add_all__U171":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1483":{ + "affine_func$add_all__U172":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1484":{ + "affine_func$add_all__U173":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1466":{ + "affine_func$add_all__U174":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1468":{ + "affine_func$coeff_1_U155":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00009000"]} }, - "affine_func$coeff_2_U1470":{ + "affine_func$coeff_2_U157":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000001c0"]} + "modargs":{"value":[["BitVector",32],"32'h00004800"]} }, - "affine_func$coeff_3_U1472":{ + "affine_func$coeff_3_U159":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} + "modargs":{"value":[["BitVector",32],"32'h00000120"]} }, - "affine_func$coeff_4_U1474":{ + "affine_func$coeff_4_U161":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000020"]} + }, + "affine_func$coeff_5_U163":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_5_U1476":{ + "affine_func$coeff_6_U165":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U1478":{ + "affine_func$const_term_U167":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0001e720"]} + "modargs":{"value":[["BitVector",32],"32'h00011fff"]} }, - "affine_func$mul_d0__U1467":{ + "affine_func$mul_d0__U154":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1469":{ + "affine_func$mul_d1__U156":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U1471":{ + "affine_func$mul_d2__U158":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U1473":{ + "affine_func$mul_d3__U160":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U1475":{ + "affine_func$mul_d4__U162":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U1477":{ + "affine_func$mul_d5__U164":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d6__U166":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -15376,52 +16115,62 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1487$c0_lutcnst":{ + "d_0_am__U177$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U177$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U178$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1487$lut$lut":{ + "d_0_am__U178$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U1488$c0_lutcnst":{ + "d_0_am__U179$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1488$lut$lut":{ + "d_0_am__U179$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U1489$c0_lutcnst":{ + "d_0_am__U180$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1489$lut$lut":{ + "d_0_am__U180$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U1490$c0_lutcnst":{ + "d_0_am__U181$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1490$lut$lut":{ + "d_0_am__U181$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U1491$c0_lutcnst":{ + "d_0_am__U182$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1491$lut$lut":{ + "d_0_am__U182$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -15470,42 +16219,52 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1492$c0_lutcnst":{ + "d_1_am__U183$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U183$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U184$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U1492$lut$lut":{ + "d_1_am__U184$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U1493$c0_lutcnst":{ + "d_1_am__U185$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U1493$lut$lut":{ + "d_1_am__U185$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U1494$c0_lutcnst":{ + "d_1_am__U186$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U1494$lut$lut":{ + "d_1_am__U186$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U1495$c0_lutcnst":{ + "d_1_am__U187$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U1495$lut$lut":{ + "d_1_am__U187$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -15554,32 +16313,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1496$c0_lutcnst":{ + "d_2_am__U188$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U1496$lut$lut":{ + "d_2_am__U188$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U1497$c0_lutcnst":{ + "d_2_am__U189$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U1497$lut$lut":{ + "d_2_am__U189$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U1498$c0_lutcnst":{ + "d_2_am__U190$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U1498$lut$lut":{ + "d_2_am__U190$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U191$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U191$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -15595,7 +16364,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -15628,22 +16397,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U1499$c0_lutcnst":{ + "d_3_am__U192$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U192$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U193$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U1499$lut$lut":{ + "d_3_am__U193$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U1500$c0_lutcnst":{ + "d_3_am__U194$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U1500$lut$lut":{ + "d_3_am__U194$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -15659,7 +16438,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, "d_3_min":{ "genref":"coreir.const", @@ -15692,12 +16471,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U1501$c0_lutcnst":{ + "d_4_am__U195$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U195$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U196$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U1501$lut$lut":{ + "d_4_am__U196$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -15713,7 +16502,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, "d_4_min":{ "genref":"coreir.const", @@ -15746,6 +16535,16 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_5_am__U197$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_5_am__U197$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_5_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -15757,7 +16556,7 @@ "d_5_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, "d_5_min":{ "genref":"coreir.const", @@ -15790,6 +16589,50 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000007"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_6_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -15829,6 +16672,11 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true8_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -15836,38 +16684,43 @@ } }, "connections":[ - ["d_0_inc.in1","_U1485.out"], - ["d_1_inc.in1","_U14851.out"], - ["d_2_inc.in1","_U14852.out"], - ["d_3_inc.in1","_U14853.out"], - ["d_4_inc.in1","_U14854.out"], - ["d_5_inc.in1","_U14855.out"], - ["cmp_time.in1","_U1486.out"], - ["affine_func$mul_d0__U1467.out","affine_func$add_all__U1479.in0"], - ["affine_func$mul_d1__U1469.out","affine_func$add_all__U1479.in1"], - ["affine_func$add_all__U1480.in0","affine_func$add_all__U1479.out"], - ["affine_func$mul_d2__U1471.out","affine_func$add_all__U1480.in1"], - ["affine_func$add_all__U1481.in0","affine_func$add_all__U1480.out"], - ["affine_func$mul_d3__U1473.out","affine_func$add_all__U1481.in1"], - ["affine_func$add_all__U1482.in0","affine_func$add_all__U1481.out"], - ["affine_func$mul_d4__U1475.out","affine_func$add_all__U1482.in1"], - ["affine_func$add_all__U1483.in0","affine_func$add_all__U1482.out"], - ["affine_func$mul_d5__U1477.out","affine_func$add_all__U1483.in1"], - ["affine_func$add_all__U1484.in0","affine_func$add_all__U1483.out"], - ["affine_func$const_term_U1478.out","affine_func$add_all__U1484.in1"], - ["time_diff.in0","affine_func$add_all__U1484.out"], - ["affine_func$mul_d0__U1467.in0","affine_func$coeff_0_U1466.out"], - ["affine_func$mul_d1__U1469.in0","affine_func$coeff_1_U1468.out"], - ["affine_func$mul_d2__U1471.in0","affine_func$coeff_2_U1470.out"], - ["affine_func$mul_d3__U1473.in0","affine_func$coeff_3_U1472.out"], - ["affine_func$mul_d4__U1475.in0","affine_func$coeff_4_U1474.out"], - ["affine_func$mul_d5__U1477.in0","affine_func$coeff_5_U1476.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1467.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1469.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U1471.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U1473.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U1475.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U1477.in1"], + ["d_0_inc.in1","_U175.out"], + ["d_1_inc.in1","_U1751.out"], + ["d_2_inc.in1","_U1752.out"], + ["d_3_inc.in1","_U1753.out"], + ["d_4_inc.in1","_U1754.out"], + ["d_5_inc.in1","_U1755.out"], + ["d_6_inc.in1","_U1756.out"], + ["cmp_time.in1","_U176.out"], + ["affine_func$mul_d0__U154.out","affine_func$add_all__U168.in0"], + ["affine_func$mul_d1__U156.out","affine_func$add_all__U168.in1"], + ["affine_func$add_all__U169.in0","affine_func$add_all__U168.out"], + ["affine_func$mul_d2__U158.out","affine_func$add_all__U169.in1"], + ["affine_func$add_all__U170.in0","affine_func$add_all__U169.out"], + ["affine_func$mul_d3__U160.out","affine_func$add_all__U170.in1"], + ["affine_func$add_all__U171.in0","affine_func$add_all__U170.out"], + ["affine_func$mul_d4__U162.out","affine_func$add_all__U171.in1"], + ["affine_func$add_all__U172.in0","affine_func$add_all__U171.out"], + ["affine_func$mul_d5__U164.out","affine_func$add_all__U172.in1"], + ["affine_func$add_all__U173.in0","affine_func$add_all__U172.out"], + ["affine_func$mul_d6__U166.out","affine_func$add_all__U173.in1"], + ["affine_func$add_all__U174.in0","affine_func$add_all__U173.out"], + ["affine_func$const_term_U167.out","affine_func$add_all__U174.in1"], + ["time_diff.in0","affine_func$add_all__U174.out"], + ["affine_func$mul_d0__U154.in0","affine_func$coeff_0_U153.out"], + ["affine_func$mul_d1__U156.in0","affine_func$coeff_1_U155.out"], + ["affine_func$mul_d2__U158.in0","affine_func$coeff_2_U157.out"], + ["affine_func$mul_d3__U160.in0","affine_func$coeff_3_U159.out"], + ["affine_func$mul_d4__U162.in0","affine_func$coeff_4_U161.out"], + ["affine_func$mul_d5__U164.in0","affine_func$coeff_5_U163.out"], + ["affine_func$mul_d6__U166.in0","affine_func$coeff_6_U165.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U154.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U156.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U158.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U160.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U162.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U164.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U166.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -15875,6 +16728,7 @@ ["d_3_reg$enMux.sel","cmp_time.out"], ["d_4_reg$enMux.sel","cmp_time.out"], ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -15882,34 +16736,37 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true7_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true8_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true6_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true7_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1487$lut$lut.bit.in.2","d_0_am__U1487$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1487$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1487$lut$lut.bit.in.1"], - ["d_0_am__U1488$lut$lut.bit.in.0","d_0_am__U1487$lut$lut.bit.out"], - ["d_0_am__U1488$lut$lut.bit.in.2","d_0_am__U1488$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U1488$lut$lut.bit.in.1"], - ["d_0_am__U1489$lut$lut.bit.in.0","d_0_am__U1488$lut$lut.bit.out"], - ["d_0_am__U1489$lut$lut.bit.in.2","d_0_am__U1489$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U1489$lut$lut.bit.in.1"], - ["d_0_am__U1490$lut$lut.bit.in.0","d_0_am__U1489$lut$lut.bit.out"], - ["d_0_am__U1490$lut$lut.bit.in.2","d_0_am__U1490$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U1490$lut$lut.bit.in.1"], - ["d_0_am__U1491$lut$lut.bit.in.0","d_0_am__U1490$lut$lut.bit.out"], - ["d_0_am__U1491$lut$lut.bit.in.2","d_0_am__U1491$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U1491$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1491$lut$lut.bit.out"], + ["d_0_am__U177$lut$lut.bit.in.2","d_0_am__U177$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U177$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U177$lut$lut.bit.in.1"], + ["d_0_am__U178$lut$lut.bit.in.0","d_0_am__U177$lut$lut.bit.out"], + ["d_0_am__U178$lut$lut.bit.in.2","d_0_am__U178$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U178$lut$lut.bit.in.1"], + ["d_0_am__U179$lut$lut.bit.in.0","d_0_am__U178$lut$lut.bit.out"], + ["d_0_am__U179$lut$lut.bit.in.2","d_0_am__U179$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U179$lut$lut.bit.in.1"], + ["d_0_am__U180$lut$lut.bit.in.0","d_0_am__U179$lut$lut.bit.out"], + ["d_0_am__U180$lut$lut.bit.in.2","d_0_am__U180$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U180$lut$lut.bit.in.1"], + ["d_0_am__U181$lut$lut.bit.in.0","d_0_am__U180$lut$lut.bit.out"], + ["d_0_am__U181$lut$lut.bit.in.2","d_0_am__U181$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U181$lut$lut.bit.in.1"], + ["d_0_am__U182$lut$lut.bit.in.0","d_0_am__U181$lut$lut.bit.out"], + ["d_0_am__U182$lut$lut.bit.in.2","d_0_am__U182$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U182$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U182$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -15926,19 +16783,22 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U1492$lut$lut.bit.in.2","d_1_am__U1492$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U1492$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U1492$lut$lut.bit.in.1"], - ["d_1_am__U1493$lut$lut.bit.in.0","d_1_am__U1492$lut$lut.bit.out"], - ["d_1_am__U1493$lut$lut.bit.in.2","d_1_am__U1493$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U1493$lut$lut.bit.in.1"], - ["d_1_am__U1494$lut$lut.bit.in.0","d_1_am__U1493$lut$lut.bit.out"], - ["d_1_am__U1494$lut$lut.bit.in.2","d_1_am__U1494$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U1494$lut$lut.bit.in.1"], - ["d_1_am__U1495$lut$lut.bit.in.0","d_1_am__U1494$lut$lut.bit.out"], - ["d_1_am__U1495$lut$lut.bit.in.2","d_1_am__U1495$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U1495$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U1495$lut$lut.bit.out"], + ["d_1_am__U183$lut$lut.bit.in.2","d_1_am__U183$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U183$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U183$lut$lut.bit.in.1"], + ["d_1_am__U184$lut$lut.bit.in.0","d_1_am__U183$lut$lut.bit.out"], + ["d_1_am__U184$lut$lut.bit.in.2","d_1_am__U184$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U184$lut$lut.bit.in.1"], + ["d_1_am__U185$lut$lut.bit.in.0","d_1_am__U184$lut$lut.bit.out"], + ["d_1_am__U185$lut$lut.bit.in.2","d_1_am__U185$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U185$lut$lut.bit.in.1"], + ["d_1_am__U186$lut$lut.bit.in.0","d_1_am__U185$lut$lut.bit.out"], + ["d_1_am__U186$lut$lut.bit.in.2","d_1_am__U186$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U186$lut$lut.bit.in.1"], + ["d_1_am__U187$lut$lut.bit.in.0","d_1_am__U186$lut$lut.bit.out"], + ["d_1_am__U187$lut$lut.bit.in.2","d_1_am__U187$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U187$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U187$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -15955,16 +16815,19 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U1496$lut$lut.bit.in.2","d_2_am__U1496$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U1496$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U1496$lut$lut.bit.in.1"], - ["d_2_am__U1497$lut$lut.bit.in.0","d_2_am__U1496$lut$lut.bit.out"], - ["d_2_am__U1497$lut$lut.bit.in.2","d_2_am__U1497$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U1497$lut$lut.bit.in.1"], - ["d_2_am__U1498$lut$lut.bit.in.0","d_2_am__U1497$lut$lut.bit.out"], - ["d_2_am__U1498$lut$lut.bit.in.2","d_2_am__U1498$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U1498$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U1498$lut$lut.bit.out"], + ["d_2_am__U188$lut$lut.bit.in.2","d_2_am__U188$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U188$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U188$lut$lut.bit.in.1"], + ["d_2_am__U189$lut$lut.bit.in.0","d_2_am__U188$lut$lut.bit.out"], + ["d_2_am__U189$lut$lut.bit.in.2","d_2_am__U189$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U189$lut$lut.bit.in.1"], + ["d_2_am__U190$lut$lut.bit.in.0","d_2_am__U189$lut$lut.bit.out"], + ["d_2_am__U190$lut$lut.bit.in.2","d_2_am__U190$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U190$lut$lut.bit.in.1"], + ["d_2_am__U191$lut$lut.bit.in.0","d_2_am__U190$lut$lut.bit.out"], + ["d_2_am__U191$lut$lut.bit.in.2","d_2_am__U191$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U191$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U191$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -15981,13 +16844,16 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U1499$lut$lut.bit.in.2","d_3_am__U1499$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U1499$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U1499$lut$lut.bit.in.1"], - ["d_3_am__U1500$lut$lut.bit.in.0","d_3_am__U1499$lut$lut.bit.out"], - ["d_3_am__U1500$lut$lut.bit.in.2","d_3_am__U1500$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U1500$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U1500$lut$lut.bit.out"], + ["d_3_am__U192$lut$lut.bit.in.2","d_3_am__U192$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U192$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U192$lut$lut.bit.in.1"], + ["d_3_am__U193$lut$lut.bit.in.0","d_3_am__U192$lut$lut.bit.out"], + ["d_3_am__U193$lut$lut.bit.in.2","d_3_am__U193$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U193$lut$lut.bit.in.1"], + ["d_3_am__U194$lut$lut.bit.in.0","d_3_am__U193$lut$lut.bit.out"], + ["d_3_am__U194$lut$lut.bit.in.2","d_3_am__U194$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U194$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U194$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -16004,10 +16870,13 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U1501$lut$lut.bit.in.2","d_4_am__U1501$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U1501$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U1501$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U1501$lut$lut.bit.out"], + ["d_4_am__U195$lut$lut.bit.in.2","d_4_am__U195$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U195$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U195$lut$lut.bit.in.1"], + ["d_4_am__U196$lut$lut.bit.in.0","d_4_am__U195$lut$lut.bit.out"], + ["d_4_am__U196$lut$lut.bit.in.2","d_4_am__U196$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U196$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U196$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -16024,6 +16893,10 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U197$lut$lut.bit.in.2","d_5_am__U197$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U197$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U197$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U197$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -16033,103 +16906,83 @@ ["d_5_reg$reg0.out","d_5_next_value.in0"], ["d_5_next_value_at_max.out","d_5_next_value.in1"], ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["true_lutcnst.bit.out","d_5_next_value.sel"], ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], ["self.rst_n","d_5_reg$clrMux.sel"], ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"] + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["true_lutcnst.bit.out","d_6_next_value.sel"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"] ] }, - "affine_controller__U1524":{ + "affine_controller__U225":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1539":{ + "_U234":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U15391":{ + "_U2341":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U15392":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U15393":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1540":{ + "_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1535":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1536":{ + "affine_func$add_all__U232":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1537":{ + "affine_func$add_all__U233":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1538":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U1526":{ + "affine_func$coeff_0_U227":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1528":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000380"]} - }, - "affine_func$coeff_2_U1530":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "affine_func$coeff_3_U1532":{ + "affine_func$coeff_1_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1534":{ + "affine_func$const_term_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0002835f"]} - }, - "affine_func$mul_d0__U1527":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U1529":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d2__U1531":{ + "affine_func$mul_d0__U228":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U1533":{ + "affine_func$mul_d1__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -16193,32 +17046,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1541$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1541$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1542$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1542$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1543$c0_lutcnst":{ + "d_0_am__U236$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1543$lut$lut":{ + "d_0_am__U236$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -16267,26 +17100,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1544$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1544$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1545$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1545$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -16298,7 +17111,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -16331,104 +17144,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1546$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1546$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -16448,16 +17163,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -16465,33 +17170,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U1539.out"], - ["d_1_inc.in1","_U15391.out"], - ["d_2_inc.in1","_U15392.out"], - ["d_3_inc.in1","_U15393.out"], - ["cmp_time.in1","_U1540.out"], - ["affine_func$mul_d0__U1527.out","affine_func$add_all__U1535.in0"], - ["affine_func$mul_d1__U1529.out","affine_func$add_all__U1535.in1"], - ["affine_func$add_all__U1536.in0","affine_func$add_all__U1535.out"], - ["affine_func$mul_d2__U1531.out","affine_func$add_all__U1536.in1"], - ["affine_func$add_all__U1537.in0","affine_func$add_all__U1536.out"], - ["affine_func$mul_d3__U1533.out","affine_func$add_all__U1537.in1"], - ["affine_func$add_all__U1538.in0","affine_func$add_all__U1537.out"], - ["affine_func$const_term_U1534.out","affine_func$add_all__U1538.in1"], - ["time_diff.in0","affine_func$add_all__U1538.out"], - ["affine_func$mul_d0__U1527.in0","affine_func$coeff_0_U1526.out"], - ["affine_func$mul_d1__U1529.in0","affine_func$coeff_1_U1528.out"], - ["affine_func$mul_d2__U1531.in0","affine_func$coeff_2_U1530.out"], - ["affine_func$mul_d3__U1533.in0","affine_func$coeff_3_U1532.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1527.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1529.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U1531.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U1533.in1"], + ["d_0_inc.in1","_U234.out"], + ["d_1_inc.in1","_U2341.out"], + ["cmp_time.in1","_U235.out"], + ["affine_func$mul_d0__U228.out","affine_func$add_all__U232.in0"], + ["affine_func$mul_d1__U230.out","affine_func$add_all__U232.in1"], + ["affine_func$add_all__U233.in0","affine_func$add_all__U232.out"], + ["affine_func$const_term_U231.out","affine_func$add_all__U233.in1"], + ["time_diff.in0","affine_func$add_all__U233.out"], + ["affine_func$mul_d0__U228.in0","affine_func$coeff_0_U227.out"], + ["affine_func$mul_d1__U230.in0","affine_func$coeff_1_U229.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U228.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U230.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -16499,28 +17192,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1541$lut$lut.bit.in.2","d_0_am__U1541$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1541$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1541$lut$lut.bit.in.1"], - ["d_0_am__U1542$lut$lut.bit.in.0","d_0_am__U1541$lut$lut.bit.out"], - ["d_0_am__U1542$lut$lut.bit.in.2","d_0_am__U1542$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U1542$lut$lut.bit.in.1"], - ["d_0_am__U1543$lut$lut.bit.in.0","d_0_am__U1542$lut$lut.bit.out"], - ["d_0_am__U1543$lut$lut.bit.in.2","d_0_am__U1543$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U1543$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1543$lut$lut.bit.out"], + ["d_0_am__U236$lut$lut.bit.in.2","d_0_am__U236$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U236$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U236$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U236$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -16537,13 +17224,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U1544$lut$lut.bit.in.2","d_1_am__U1544$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U1544$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U1544$lut$lut.bit.in.1"], - ["d_1_am__U1545$lut$lut.bit.in.0","d_1_am__U1544$lut$lut.bit.out"], - ["d_1_am__U1545$lut$lut.bit.in.2","d_1_am__U1545$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U1545$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U1545$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -16553,139 +17233,67 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U1546$lut$lut.bit.in.2","d_2_am__U1546$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U1546$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U1546$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U1546$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U1564":{ + "affine_controller__U239":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U1579":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U15791":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U15792":{ + "_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U15793":{ + "_U2481":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1580":{ + "_U249":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1575":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U1576":{ + "affine_func$add_all__U246":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1577":{ + "affine_func$add_all__U247":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1578":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U1566":{ + "affine_func$coeff_0_U241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1568":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000380"]} - }, - "affine_func$coeff_2_U1570":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000080"]} - }, - "affine_func$coeff_3_U1572":{ + "affine_func$coeff_1_U243":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1574":{ + "affine_func$const_term_U245":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00028360"]} - }, - "affine_func$mul_d0__U1567":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U1569":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d2__U1571":{ + "affine_func$mul_d0__U242":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U1573":{ + "affine_func$mul_d1__U244":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -16749,32 +17357,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1581$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1581$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1582$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U1582$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U1583$c0_lutcnst":{ + "d_0_am__U250$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1583$lut$lut":{ + "d_0_am__U250$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -16823,26 +17411,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U1584$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1584$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U1585$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U1585$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -16854,7 +17422,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -16887,104 +17455,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U1586$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U1586$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000006"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000007f"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -17004,16 +17474,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true5_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -17021,33 +17481,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U1579.out"], - ["d_1_inc.in1","_U15791.out"], - ["d_2_inc.in1","_U15792.out"], - ["d_3_inc.in1","_U15793.out"], - ["cmp_time.in1","_U1580.out"], - ["affine_func$mul_d0__U1567.out","affine_func$add_all__U1575.in0"], - ["affine_func$mul_d1__U1569.out","affine_func$add_all__U1575.in1"], - ["affine_func$add_all__U1576.in0","affine_func$add_all__U1575.out"], - ["affine_func$mul_d2__U1571.out","affine_func$add_all__U1576.in1"], - ["affine_func$add_all__U1577.in0","affine_func$add_all__U1576.out"], - ["affine_func$mul_d3__U1573.out","affine_func$add_all__U1577.in1"], - ["affine_func$add_all__U1578.in0","affine_func$add_all__U1577.out"], - ["affine_func$const_term_U1574.out","affine_func$add_all__U1578.in1"], - ["time_diff.in0","affine_func$add_all__U1578.out"], - ["affine_func$mul_d0__U1567.in0","affine_func$coeff_0_U1566.out"], - ["affine_func$mul_d1__U1569.in0","affine_func$coeff_1_U1568.out"], - ["affine_func$mul_d2__U1571.in0","affine_func$coeff_2_U1570.out"], - ["affine_func$mul_d3__U1573.in0","affine_func$coeff_3_U1572.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1567.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1569.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U1571.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U1573.in1"], + ["d_0_inc.in1","_U248.out"], + ["d_1_inc.in1","_U2481.out"], + ["cmp_time.in1","_U249.out"], + ["affine_func$mul_d0__U242.out","affine_func$add_all__U246.in0"], + ["affine_func$mul_d1__U244.out","affine_func$add_all__U246.in1"], + ["affine_func$add_all__U247.in0","affine_func$add_all__U246.out"], + ["affine_func$const_term_U245.out","affine_func$add_all__U247.in1"], + ["time_diff.in0","affine_func$add_all__U247.out"], + ["affine_func$mul_d0__U242.in0","affine_func$coeff_0_U241.out"], + ["affine_func$mul_d1__U244.in0","affine_func$coeff_1_U243.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U242.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U244.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -17055,28 +17503,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1581$lut$lut.bit.in.2","d_0_am__U1581$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1581$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1581$lut$lut.bit.in.1"], - ["d_0_am__U1582$lut$lut.bit.in.0","d_0_am__U1581$lut$lut.bit.out"], - ["d_0_am__U1582$lut$lut.bit.in.2","d_0_am__U1582$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U1582$lut$lut.bit.in.1"], - ["d_0_am__U1583$lut$lut.bit.in.0","d_0_am__U1582$lut$lut.bit.out"], - ["d_0_am__U1583$lut$lut.bit.in.2","d_0_am__U1583$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U1583$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1583$lut$lut.bit.out"], + ["d_0_am__U250$lut$lut.bit.in.2","d_0_am__U250$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U250$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U250$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U250$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17093,13 +17535,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U1584$lut$lut.bit.in.2","d_1_am__U1584$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U1584$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U1584$lut$lut.bit.in.1"], - ["d_1_am__U1585$lut$lut.bit.in.0","d_1_am__U1584$lut$lut.bit.out"], - ["d_1_am__U1585$lut$lut.bit.in.2","d_1_am__U1585$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U1585$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U1585$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -17109,53 +17544,17 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U1586$lut$lut.bit.in.2","d_2_am__U1586$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U1586$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U1586$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U1586$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U16":{ + "affine_controller__U253":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -17163,49 +17562,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U25":{ + "_U262":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U251":{ + "_U2621":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U26":{ + "_U263":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U23":{ + "affine_func$add_all__U260":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U24":{ + "affine_func$add_all__U261":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U18":{ + "affine_func$coeff_0_U255":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U20":{ + "affine_func$coeff_1_U257":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U22":{ + "affine_func$const_term_U259":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U19":{ + "affine_func$mul_d0__U256":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U21":{ + "affine_func$mul_d1__U258":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -17269,12 +17668,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U27$c0_lutcnst":{ + "d_0_am__U264$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U27$lut$lut":{ + "d_0_am__U264$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -17393,18 +17792,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U25.out"], - ["d_1_inc.in1","_U251.out"], - ["cmp_time.in1","_U26.out"], - ["affine_func$mul_d0__U19.out","affine_func$add_all__U23.in0"], - ["affine_func$mul_d1__U21.out","affine_func$add_all__U23.in1"], - ["affine_func$add_all__U24.in0","affine_func$add_all__U23.out"], - ["affine_func$const_term_U22.out","affine_func$add_all__U24.in1"], - ["time_diff.in0","affine_func$add_all__U24.out"], - ["affine_func$mul_d0__U19.in0","affine_func$coeff_0_U18.out"], - ["affine_func$mul_d1__U21.in0","affine_func$coeff_1_U20.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U19.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U21.in1"], + ["d_0_inc.in1","_U262.out"], + ["d_1_inc.in1","_U2621.out"], + ["cmp_time.in1","_U263.out"], + ["affine_func$mul_d0__U256.out","affine_func$add_all__U260.in0"], + ["affine_func$mul_d1__U258.out","affine_func$add_all__U260.in1"], + ["affine_func$add_all__U261.in0","affine_func$add_all__U260.out"], + ["affine_func$const_term_U259.out","affine_func$add_all__U261.in1"], + ["time_diff.in0","affine_func$add_all__U261.out"], + ["affine_func$mul_d0__U256.in0","affine_func$coeff_0_U255.out"], + ["affine_func$mul_d1__U258.in0","affine_func$coeff_1_U257.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U256.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U258.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -17415,22 +17814,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true2_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true3_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U27$lut$lut.bit.in.2","d_0_am__U27$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U27$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U27$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U27$lut$lut.bit.out"], + ["d_0_am__U264$lut$lut.bit.in.2","d_0_am__U264$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U264$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U264$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U264$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -17466,147 +17865,57 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U160":{ + "affine_controller__U267":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",7,["Array",32,"Bit"]]], + ["d",["Array",2,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U184":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1841":{ + "_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1842":{ + "_U2761":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1843":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1844":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1845":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U1846":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U185":{ + "_U277":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U177":{ + "affine_func$add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U178":{ + "affine_func$add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U179":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U180":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U181":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U182":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U183":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U162":{ + "affine_func$coeff_0_U269":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U164":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00009000"]} - }, - "affine_func$coeff_2_U166":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00004800"]} - }, - "affine_func$coeff_3_U168":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000120"]} - }, - "affine_func$coeff_4_U170":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000020"]} - }, - "affine_func$coeff_5_U172":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "affine_func$coeff_6_U174":{ + "affine_func$coeff_1_U271":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U176":{ + "affine_func$const_term_U273":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00011fff"]} - }, - "affine_func$mul_d0__U163":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U165":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d2__U167":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d3__U169":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d4__U171":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d5__U173":{ + "affine_func$mul_d0__U270":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U175":{ + "affine_func$mul_d1__U272":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -17670,62 +17979,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U186$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U186$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U187$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U187$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U188$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U188$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U189$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U189$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U190$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U190$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U191$c0_lutcnst":{ + "d_0_am__U278$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U191$lut$lut":{ + "d_0_am__U278$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -17774,56 +18033,6 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U192$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U192$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U193$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U193$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U194$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U194$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U195$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U195$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U196$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U196$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -17835,7 +18044,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "d_1_min":{ "genref":"coreir.const", @@ -17868,322 +18077,313 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U197$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U197$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U198$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U198$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} }, - "d_2_am__U199$c0_lutcnst":{ + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U199$lut$lut":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U200$c0_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U200$lut$lut":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U276.out"], + ["d_1_inc.in1","_U2761.out"], + ["cmp_time.in1","_U277.out"], + ["affine_func$mul_d0__U270.out","affine_func$add_all__U274.in0"], + ["affine_func$mul_d1__U272.out","affine_func$add_all__U274.in1"], + ["affine_func$add_all__U275.in0","affine_func$add_all__U274.out"], + ["affine_func$const_term_U273.out","affine_func$add_all__U275.in1"], + ["time_diff.in0","affine_func$add_all__U275.out"], + ["affine_func$mul_d0__U270.in0","affine_func$coeff_0_U269.out"], + ["affine_func$mul_d1__U272.in0","affine_func$coeff_1_U271.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U270.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U272.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U278$lut$lut.bit.in.2","d_0_am__U278$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U278$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U278$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U278$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"] + ] + }, + "affine_controller__U281":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U290":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_max":{ + "_U2901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_min":{ + "_U291":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ - "genref":"coreir.mux", + "affine_func$add_all__U288":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", + "affine_func$add_all__U289":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_reg$c0":{ + "affine_func$coeff_0_U283":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func$coeff_1_U285":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", + "affine_func$const_term_U287":{ + "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "d_3_am__U201$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$mul_d0__U284":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U201$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "affine_func$mul_d1__U286":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U202$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} }, - "d_3_am__U202$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "d_3_am__U203$c0_lutcnst":{ + "cycle_time$and$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U203$lut$lut":{ + "cycle_time$and$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ + "cycle_time$count$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_reg$clrMux":{ + "cycle_time$count$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$enMux":{ + "cycle_time$count$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$reg0":{ + "cycle_time$count$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U204$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_4_am__U204$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} }, - "d_4_am__U205$c0_lutcnst":{ + "cycle_time$resetOr$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U205$lut$lut":{ + "cycle_time$resetOr$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} }, - "d_4_reg$enMux":{ - "genref":"coreir.mux", + "cycle_time$ult":{ + "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_5_am__U206$c0_lutcnst":{ + "d_0_am__U292$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U206$lut$lut":{ + "d_0_am__U292$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_5_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000003"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_6_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_6_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -18207,27 +18407,313 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true4_lutcnst":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U290.out"], + ["d_1_inc.in1","_U2901.out"], + ["cmp_time.in1","_U291.out"], + ["affine_func$mul_d0__U284.out","affine_func$add_all__U288.in0"], + ["affine_func$mul_d1__U286.out","affine_func$add_all__U288.in1"], + ["affine_func$add_all__U289.in0","affine_func$add_all__U288.out"], + ["affine_func$const_term_U287.out","affine_func$add_all__U289.in1"], + ["time_diff.in0","affine_func$add_all__U289.out"], + ["affine_func$mul_d0__U284.in0","affine_func$coeff_0_U283.out"], + ["affine_func$mul_d1__U286.in0","affine_func$coeff_1_U285.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U284.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U286.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U292$lut$lut.bit.in.2","d_0_am__U292$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U292$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U292$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U292$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"] + ] + }, + "affine_controller__U29":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",2,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "true5_lutcnst":{ + "_U381":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$add_all__U36":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U37":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$coeff_1_U33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$const_term_U35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00012000"]} + }, + "affine_func$mul_d0__U32":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U34":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true6_lutcnst":{ + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$count$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} + }, + "d_0_am__U40$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U40$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true7_lutcnst":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true8_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} @@ -18239,51 +18725,21 @@ } }, "connections":[ - ["d_0_inc.in1","_U184.out"], - ["d_1_inc.in1","_U1841.out"], - ["d_2_inc.in1","_U1842.out"], - ["d_3_inc.in1","_U1843.out"], - ["d_4_inc.in1","_U1844.out"], - ["d_5_inc.in1","_U1845.out"], - ["d_6_inc.in1","_U1846.out"], - ["cmp_time.in1","_U185.out"], - ["affine_func$mul_d0__U163.out","affine_func$add_all__U177.in0"], - ["affine_func$mul_d1__U165.out","affine_func$add_all__U177.in1"], - ["affine_func$add_all__U178.in0","affine_func$add_all__U177.out"], - ["affine_func$mul_d2__U167.out","affine_func$add_all__U178.in1"], - ["affine_func$add_all__U179.in0","affine_func$add_all__U178.out"], - ["affine_func$mul_d3__U169.out","affine_func$add_all__U179.in1"], - ["affine_func$add_all__U180.in0","affine_func$add_all__U179.out"], - ["affine_func$mul_d4__U171.out","affine_func$add_all__U180.in1"], - ["affine_func$add_all__U181.in0","affine_func$add_all__U180.out"], - ["affine_func$mul_d5__U173.out","affine_func$add_all__U181.in1"], - ["affine_func$add_all__U182.in0","affine_func$add_all__U181.out"], - ["affine_func$mul_d6__U175.out","affine_func$add_all__U182.in1"], - ["affine_func$add_all__U183.in0","affine_func$add_all__U182.out"], - ["affine_func$const_term_U176.out","affine_func$add_all__U183.in1"], - ["time_diff.in0","affine_func$add_all__U183.out"], - ["affine_func$mul_d0__U163.in0","affine_func$coeff_0_U162.out"], - ["affine_func$mul_d1__U165.in0","affine_func$coeff_1_U164.out"], - ["affine_func$mul_d2__U167.in0","affine_func$coeff_2_U166.out"], - ["affine_func$mul_d3__U169.in0","affine_func$coeff_3_U168.out"], - ["affine_func$mul_d4__U171.in0","affine_func$coeff_4_U170.out"], - ["affine_func$mul_d5__U173.in0","affine_func$coeff_5_U172.out"], - ["affine_func$mul_d6__U175.in0","affine_func$coeff_6_U174.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U163.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U165.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U167.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U169.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U171.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U173.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U175.in1"], + ["d_0_inc.in1","_U38.out"], + ["d_1_inc.in1","_U381.out"], + ["cmp_time.in1","_U39.out"], + ["affine_func$mul_d0__U32.out","affine_func$add_all__U36.in0"], + ["affine_func$mul_d1__U34.out","affine_func$add_all__U36.in1"], + ["affine_func$add_all__U37.in0","affine_func$add_all__U36.out"], + ["affine_func$const_term_U35.out","affine_func$add_all__U37.in1"], + ["time_diff.in0","affine_func$add_all__U37.out"], + ["affine_func$mul_d0__U32.in0","affine_func$coeff_0_U31.out"], + ["affine_func$mul_d1__U34.in0","affine_func$coeff_1_U33.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U32.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U34.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -18291,37 +18747,22 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true8_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true7_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U186$lut$lut.bit.in.2","d_0_am__U186$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U186$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U186$lut$lut.bit.in.1"], - ["d_0_am__U187$lut$lut.bit.in.0","d_0_am__U186$lut$lut.bit.out"], - ["d_0_am__U187$lut$lut.bit.in.2","d_0_am__U187$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U187$lut$lut.bit.in.1"], - ["d_0_am__U188$lut$lut.bit.in.0","d_0_am__U187$lut$lut.bit.out"], - ["d_0_am__U188$lut$lut.bit.in.2","d_0_am__U188$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U188$lut$lut.bit.in.1"], - ["d_0_am__U189$lut$lut.bit.in.0","d_0_am__U188$lut$lut.bit.out"], - ["d_0_am__U189$lut$lut.bit.in.2","d_0_am__U189$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U189$lut$lut.bit.in.1"], - ["d_0_am__U190$lut$lut.bit.in.0","d_0_am__U189$lut$lut.bit.out"], - ["d_0_am__U190$lut$lut.bit.in.2","d_0_am__U190$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U190$lut$lut.bit.in.1"], - ["d_0_am__U191$lut$lut.bit.in.0","d_0_am__U190$lut$lut.bit.out"], - ["d_0_am__U191$lut$lut.bit.in.2","d_0_am__U191$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U191$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U191$lut$lut.bit.out"], + ["d_0_am__U40$lut$lut.bit.in.2","d_0_am__U40$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U40$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U40$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U40$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18338,22 +18779,6 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U192$lut$lut.bit.in.2","d_1_am__U192$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U192$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U192$lut$lut.bit.in.1"], - ["d_1_am__U193$lut$lut.bit.in.0","d_1_am__U192$lut$lut.bit.out"], - ["d_1_am__U193$lut$lut.bit.in.2","d_1_am__U193$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U193$lut$lut.bit.in.1"], - ["d_1_am__U194$lut$lut.bit.in.0","d_1_am__U193$lut$lut.bit.out"], - ["d_1_am__U194$lut$lut.bit.in.2","d_1_am__U194$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U194$lut$lut.bit.in.1"], - ["d_1_am__U195$lut$lut.bit.in.0","d_1_am__U194$lut$lut.bit.out"], - ["d_1_am__U195$lut$lut.bit.in.2","d_1_am__U195$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U195$lut$lut.bit.in.1"], - ["d_1_am__U196$lut$lut.bit.in.0","d_1_am__U195$lut$lut.bit.out"], - ["d_1_am__U196$lut$lut.bit.in.2","d_1_am__U196$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U196$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U196$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -18363,131 +18788,17 @@ ["d_1_reg$reg0.out","d_1_next_value.in0"], ["d_1_next_value_at_max.out","d_1_next_value.in1"], ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["true_lutcnst.bit.out","d_1_next_value.sel"], ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], ["self.rst_n","d_1_reg$clrMux.sel"], ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U197$lut$lut.bit.in.2","d_2_am__U197$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U197$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U197$lut$lut.bit.in.1"], - ["d_2_am__U198$lut$lut.bit.in.0","d_2_am__U197$lut$lut.bit.out"], - ["d_2_am__U198$lut$lut.bit.in.2","d_2_am__U198$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U198$lut$lut.bit.in.1"], - ["d_2_am__U199$lut$lut.bit.in.0","d_2_am__U198$lut$lut.bit.out"], - ["d_2_am__U199$lut$lut.bit.in.2","d_2_am__U199$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U199$lut$lut.bit.in.1"], - ["d_2_am__U200$lut$lut.bit.in.0","d_2_am__U199$lut$lut.bit.out"], - ["d_2_am__U200$lut$lut.bit.in.2","d_2_am__U200$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U200$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U200$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U201$lut$lut.bit.in.2","d_3_am__U201$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U201$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U201$lut$lut.bit.in.1"], - ["d_3_am__U202$lut$lut.bit.in.0","d_3_am__U201$lut$lut.bit.out"], - ["d_3_am__U202$lut$lut.bit.in.2","d_3_am__U202$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U202$lut$lut.bit.in.1"], - ["d_3_am__U203$lut$lut.bit.in.0","d_3_am__U202$lut$lut.bit.out"], - ["d_3_am__U203$lut$lut.bit.in.2","d_3_am__U203$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U203$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U203$lut$lut.bit.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U204$lut$lut.bit.in.2","d_4_am__U204$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U204$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U204$lut$lut.bit.in.1"], - ["d_4_am__U205$lut$lut.bit.in.0","d_4_am__U204$lut$lut.bit.out"], - ["d_4_am__U205$lut$lut.bit.in.2","d_4_am__U205$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U205$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U205$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U206$lut$lut.bit.in.2","d_5_am__U206$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U206$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U206$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U206$lut$lut.bit.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["true_lutcnst.bit.out","d_6_next_value.sel"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"] + ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U234":{ + "affine_controller__U295":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18495,49 +18806,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U243":{ + "_U304":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2431":{ + "_U3041":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U244":{ + "_U305":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U241":{ + "affine_func$add_all__U302":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U242":{ + "affine_func$add_all__U303":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U236":{ + "affine_func$coeff_0_U297":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U238":{ + "affine_func$coeff_1_U299":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U240":{ + "affine_func$const_term_U301":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U237":{ + "affine_func$mul_d0__U298":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U239":{ + "affine_func$mul_d1__U300":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -18601,12 +18912,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U245$c0_lutcnst":{ + "d_0_am__U306$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U245$lut$lut":{ + "d_0_am__U306$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -18725,18 +19036,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U243.out"], - ["d_1_inc.in1","_U2431.out"], - ["cmp_time.in1","_U244.out"], - ["affine_func$mul_d0__U237.out","affine_func$add_all__U241.in0"], - ["affine_func$mul_d1__U239.out","affine_func$add_all__U241.in1"], - ["affine_func$add_all__U242.in0","affine_func$add_all__U241.out"], - ["affine_func$const_term_U240.out","affine_func$add_all__U242.in1"], - ["time_diff.in0","affine_func$add_all__U242.out"], - ["affine_func$mul_d0__U237.in0","affine_func$coeff_0_U236.out"], - ["affine_func$mul_d1__U239.in0","affine_func$coeff_1_U238.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U237.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U239.in1"], + ["d_0_inc.in1","_U304.out"], + ["d_1_inc.in1","_U3041.out"], + ["cmp_time.in1","_U305.out"], + ["affine_func$mul_d0__U298.out","affine_func$add_all__U302.in0"], + ["affine_func$mul_d1__U300.out","affine_func$add_all__U302.in1"], + ["affine_func$add_all__U303.in0","affine_func$add_all__U302.out"], + ["affine_func$const_term_U301.out","affine_func$add_all__U303.in1"], + ["time_diff.in0","affine_func$add_all__U303.out"], + ["affine_func$mul_d0__U298.in0","affine_func$coeff_0_U297.out"], + ["affine_func$mul_d1__U300.in0","affine_func$coeff_1_U299.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U298.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U300.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -18759,10 +19070,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U245$lut$lut.bit.in.2","d_0_am__U245$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U245$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U245$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U245$lut$lut.bit.out"], + ["d_0_am__U306$lut$lut.bit.in.2","d_0_am__U306$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U306$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U306$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U306$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -18798,7 +19109,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U249":{ + "affine_controller__U309":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -18806,49 +19117,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U258":{ + "_U318":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2581":{ + "_U3181":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U259":{ + "_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U256":{ + "affine_func$add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U257":{ + "affine_func$add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U251":{ + "affine_func$coeff_0_U311":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U253":{ + "affine_func$coeff_1_U313":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U255":{ + "affine_func$const_term_U315":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U252":{ + "affine_func$mul_d0__U312":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U254":{ + "affine_func$mul_d1__U314":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -18912,12 +19223,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U260$c0_lutcnst":{ + "d_0_am__U320$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U260$lut$lut":{ + "d_0_am__U320$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -19036,18 +19347,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U258.out"], - ["d_1_inc.in1","_U2581.out"], - ["cmp_time.in1","_U259.out"], - ["affine_func$mul_d0__U252.out","affine_func$add_all__U256.in0"], - ["affine_func$mul_d1__U254.out","affine_func$add_all__U256.in1"], - ["affine_func$add_all__U257.in0","affine_func$add_all__U256.out"], - ["affine_func$const_term_U255.out","affine_func$add_all__U257.in1"], - ["time_diff.in0","affine_func$add_all__U257.out"], - ["affine_func$mul_d0__U252.in0","affine_func$coeff_0_U251.out"], - ["affine_func$mul_d1__U254.in0","affine_func$coeff_1_U253.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U252.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U254.in1"], + ["d_0_inc.in1","_U318.out"], + ["d_1_inc.in1","_U3181.out"], + ["cmp_time.in1","_U319.out"], + ["affine_func$mul_d0__U312.out","affine_func$add_all__U316.in0"], + ["affine_func$mul_d1__U314.out","affine_func$add_all__U316.in1"], + ["affine_func$add_all__U317.in0","affine_func$add_all__U316.out"], + ["affine_func$const_term_U315.out","affine_func$add_all__U317.in1"], + ["time_diff.in0","affine_func$add_all__U317.out"], + ["affine_func$mul_d0__U312.in0","affine_func$coeff_0_U311.out"], + ["affine_func$mul_d1__U314.in0","affine_func$coeff_1_U313.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U312.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U314.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -19070,10 +19381,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U260$lut$lut.bit.in.2","d_0_am__U260$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U260$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U260$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U260$lut$lut.bit.out"], + ["d_0_am__U320$lut$lut.bit.in.2","d_0_am__U320$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U320$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U320$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U320$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19109,7 +19420,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U264":{ + "affine_controller__U323":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19117,49 +19428,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U273":{ + "_U332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2731":{ + "_U3321":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U274":{ + "_U333":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U271":{ + "affine_func$add_all__U330":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U272":{ + "affine_func$add_all__U331":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U266":{ + "affine_func$coeff_0_U325":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U268":{ + "affine_func$coeff_1_U327":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U270":{ + "affine_func$const_term_U329":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U267":{ + "affine_func$mul_d0__U326":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U269":{ + "affine_func$mul_d1__U328":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -19223,12 +19534,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U275$c0_lutcnst":{ + "d_0_am__U334$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U275$lut$lut":{ + "d_0_am__U334$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -19347,18 +19658,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U273.out"], - ["d_1_inc.in1","_U2731.out"], - ["cmp_time.in1","_U274.out"], - ["affine_func$mul_d0__U267.out","affine_func$add_all__U271.in0"], - ["affine_func$mul_d1__U269.out","affine_func$add_all__U271.in1"], - ["affine_func$add_all__U272.in0","affine_func$add_all__U271.out"], - ["affine_func$const_term_U270.out","affine_func$add_all__U272.in1"], - ["time_diff.in0","affine_func$add_all__U272.out"], - ["affine_func$mul_d0__U267.in0","affine_func$coeff_0_U266.out"], - ["affine_func$mul_d1__U269.in0","affine_func$coeff_1_U268.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U267.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U269.in1"], + ["d_0_inc.in1","_U332.out"], + ["d_1_inc.in1","_U3321.out"], + ["cmp_time.in1","_U333.out"], + ["affine_func$mul_d0__U326.out","affine_func$add_all__U330.in0"], + ["affine_func$mul_d1__U328.out","affine_func$add_all__U330.in1"], + ["affine_func$add_all__U331.in0","affine_func$add_all__U330.out"], + ["affine_func$const_term_U329.out","affine_func$add_all__U331.in1"], + ["time_diff.in0","affine_func$add_all__U331.out"], + ["affine_func$mul_d0__U326.in0","affine_func$coeff_0_U325.out"], + ["affine_func$mul_d1__U328.in0","affine_func$coeff_1_U327.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U326.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U328.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -19381,10 +19692,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U275$lut$lut.bit.in.2","d_0_am__U275$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U275$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U275$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U275$lut$lut.bit.out"], + ["d_0_am__U334$lut$lut.bit.in.2","d_0_am__U334$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U334$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U334$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U334$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19420,7 +19731,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U279":{ + "affine_controller__U337":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19428,49 +19739,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U288":{ + "_U346":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2881":{ + "_U3461":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U289":{ + "_U347":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U286":{ + "affine_func$add_all__U344":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U287":{ + "affine_func$add_all__U345":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U281":{ + "affine_func$coeff_0_U339":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U283":{ + "affine_func$coeff_1_U341":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U285":{ + "affine_func$const_term_U343":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U282":{ + "affine_func$mul_d0__U340":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U284":{ + "affine_func$mul_d1__U342":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -19534,12 +19845,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U290$c0_lutcnst":{ + "d_0_am__U348$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U290$lut$lut":{ + "d_0_am__U348$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -19658,18 +19969,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U288.out"], - ["d_1_inc.in1","_U2881.out"], - ["cmp_time.in1","_U289.out"], - ["affine_func$mul_d0__U282.out","affine_func$add_all__U286.in0"], - ["affine_func$mul_d1__U284.out","affine_func$add_all__U286.in1"], - ["affine_func$add_all__U287.in0","affine_func$add_all__U286.out"], - ["affine_func$const_term_U285.out","affine_func$add_all__U287.in1"], - ["time_diff.in0","affine_func$add_all__U287.out"], - ["affine_func$mul_d0__U282.in0","affine_func$coeff_0_U281.out"], - ["affine_func$mul_d1__U284.in0","affine_func$coeff_1_U283.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U282.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U284.in1"], + ["d_0_inc.in1","_U346.out"], + ["d_1_inc.in1","_U3461.out"], + ["cmp_time.in1","_U347.out"], + ["affine_func$mul_d0__U340.out","affine_func$add_all__U344.in0"], + ["affine_func$mul_d1__U342.out","affine_func$add_all__U344.in1"], + ["affine_func$add_all__U345.in0","affine_func$add_all__U344.out"], + ["affine_func$const_term_U343.out","affine_func$add_all__U345.in1"], + ["time_diff.in0","affine_func$add_all__U345.out"], + ["affine_func$mul_d0__U340.in0","affine_func$coeff_0_U339.out"], + ["affine_func$mul_d1__U342.in0","affine_func$coeff_1_U341.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U340.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U342.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -19692,10 +20003,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U290$lut$lut.bit.in.2","d_0_am__U290$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U290$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U290$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U290$lut$lut.bit.out"], + ["d_0_am__U348$lut$lut.bit.in.2","d_0_am__U348$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U348$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U348$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U348$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -19731,7 +20042,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U294":{ + "affine_controller__U351":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -19739,49 +20050,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U303":{ + "_U360":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3031":{ + "_U3601":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U304":{ + "_U361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U301":{ + "affine_func$add_all__U358":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U302":{ + "affine_func$add_all__U359":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U296":{ + "affine_func$coeff_0_U353":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U298":{ + "affine_func$coeff_1_U355":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U300":{ + "affine_func$const_term_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U297":{ + "affine_func$mul_d0__U354":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U299":{ + "affine_func$mul_d1__U356":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -19845,12 +20156,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U305$c0_lutcnst":{ + "d_0_am__U362$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U305$lut$lut":{ + "d_0_am__U362$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -19969,18 +20280,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U303.out"], - ["d_1_inc.in1","_U3031.out"], - ["cmp_time.in1","_U304.out"], - ["affine_func$mul_d0__U297.out","affine_func$add_all__U301.in0"], - ["affine_func$mul_d1__U299.out","affine_func$add_all__U301.in1"], - ["affine_func$add_all__U302.in0","affine_func$add_all__U301.out"], - ["affine_func$const_term_U300.out","affine_func$add_all__U302.in1"], - ["time_diff.in0","affine_func$add_all__U302.out"], - ["affine_func$mul_d0__U297.in0","affine_func$coeff_0_U296.out"], - ["affine_func$mul_d1__U299.in0","affine_func$coeff_1_U298.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U297.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U299.in1"], + ["d_0_inc.in1","_U360.out"], + ["d_1_inc.in1","_U3601.out"], + ["cmp_time.in1","_U361.out"], + ["affine_func$mul_d0__U354.out","affine_func$add_all__U358.in0"], + ["affine_func$mul_d1__U356.out","affine_func$add_all__U358.in1"], + ["affine_func$add_all__U359.in0","affine_func$add_all__U358.out"], + ["affine_func$const_term_U357.out","affine_func$add_all__U359.in1"], + ["time_diff.in0","affine_func$add_all__U359.out"], + ["affine_func$mul_d0__U354.in0","affine_func$coeff_0_U353.out"], + ["affine_func$mul_d1__U356.in0","affine_func$coeff_1_U355.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U354.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U356.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -20003,10 +20314,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U305$lut$lut.bit.in.2","d_0_am__U305$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U305$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U305$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U305$lut$lut.bit.out"], + ["d_0_am__U362$lut$lut.bit.in.2","d_0_am__U362$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U362$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U362$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U362$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -20042,7 +20353,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U309":{ + "affine_controller__U365":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -20050,49 +20361,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U318":{ + "_U374":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3181":{ + "_U3741":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U319":{ + "_U375":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U316":{ + "affine_func$add_all__U372":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U317":{ + "affine_func$add_all__U373":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U311":{ + "affine_func$coeff_0_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U313":{ + "affine_func$coeff_1_U369":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U315":{ + "affine_func$const_term_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U312":{ + "affine_func$mul_d0__U368":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U314":{ + "affine_func$mul_d1__U370":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -20156,12 +20467,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U320$c0_lutcnst":{ + "d_0_am__U376$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U320$lut$lut":{ + "d_0_am__U376$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -20280,18 +20591,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U318.out"], - ["d_1_inc.in1","_U3181.out"], - ["cmp_time.in1","_U319.out"], - ["affine_func$mul_d0__U312.out","affine_func$add_all__U316.in0"], - ["affine_func$mul_d1__U314.out","affine_func$add_all__U316.in1"], - ["affine_func$add_all__U317.in0","affine_func$add_all__U316.out"], - ["affine_func$const_term_U315.out","affine_func$add_all__U317.in1"], - ["time_diff.in0","affine_func$add_all__U317.out"], - ["affine_func$mul_d0__U312.in0","affine_func$coeff_0_U311.out"], - ["affine_func$mul_d1__U314.in0","affine_func$coeff_1_U313.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U312.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U314.in1"], + ["d_0_inc.in1","_U374.out"], + ["d_1_inc.in1","_U3741.out"], + ["cmp_time.in1","_U375.out"], + ["affine_func$mul_d0__U368.out","affine_func$add_all__U372.in0"], + ["affine_func$mul_d1__U370.out","affine_func$add_all__U372.in1"], + ["affine_func$add_all__U373.in0","affine_func$add_all__U372.out"], + ["affine_func$const_term_U371.out","affine_func$add_all__U373.in1"], + ["time_diff.in0","affine_func$add_all__U373.out"], + ["affine_func$mul_d0__U368.in0","affine_func$coeff_0_U367.out"], + ["affine_func$mul_d1__U370.in0","affine_func$coeff_1_U369.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U368.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U370.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -20314,10 +20625,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U320$lut$lut.bit.in.2","d_0_am__U320$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U320$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U320$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U320$lut$lut.bit.out"], + ["d_0_am__U376$lut$lut.bit.in.2","d_0_am__U376$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U376$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U376$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U376$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -20353,7 +20664,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U31":{ + "affine_controller__U379":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -20361,49 +20672,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U40":{ + "_U388":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U401":{ + "_U3881":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U41":{ + "_U389":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U38":{ + "affine_func$add_all__U386":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U39":{ + "affine_func$add_all__U387":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U33":{ + "affine_func$coeff_0_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U35":{ + "affine_func$coeff_1_U383":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U37":{ + "affine_func$const_term_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U34":{ + "affine_func$mul_d0__U382":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U36":{ + "affine_func$mul_d1__U384":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -20467,12 +20778,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U42$c0_lutcnst":{ + "d_0_am__U390$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U42$lut$lut":{ + "d_0_am__U390$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -20591,18 +20902,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U40.out"], - ["d_1_inc.in1","_U401.out"], - ["cmp_time.in1","_U41.out"], - ["affine_func$mul_d0__U34.out","affine_func$add_all__U38.in0"], - ["affine_func$mul_d1__U36.out","affine_func$add_all__U38.in1"], - ["affine_func$add_all__U39.in0","affine_func$add_all__U38.out"], - ["affine_func$const_term_U37.out","affine_func$add_all__U39.in1"], - ["time_diff.in0","affine_func$add_all__U39.out"], - ["affine_func$mul_d0__U34.in0","affine_func$coeff_0_U33.out"], - ["affine_func$mul_d1__U36.in0","affine_func$coeff_1_U35.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U34.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U36.in1"], + ["d_0_inc.in1","_U388.out"], + ["d_1_inc.in1","_U3881.out"], + ["cmp_time.in1","_U389.out"], + ["affine_func$mul_d0__U382.out","affine_func$add_all__U386.in0"], + ["affine_func$mul_d1__U384.out","affine_func$add_all__U386.in1"], + ["affine_func$add_all__U387.in0","affine_func$add_all__U386.out"], + ["affine_func$const_term_U385.out","affine_func$add_all__U387.in1"], + ["time_diff.in0","affine_func$add_all__U387.out"], + ["affine_func$mul_d0__U382.in0","affine_func$coeff_0_U381.out"], + ["affine_func$mul_d1__U384.in0","affine_func$coeff_1_U383.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U382.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U384.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -20625,10 +20936,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U42$lut$lut.bit.in.2","d_0_am__U42$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U42$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U42$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U42$lut$lut.bit.out"], + ["d_0_am__U390$lut$lut.bit.in.2","d_0_am__U390$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U390$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U390$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U390$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -20664,7 +20975,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U324":{ + "affine_controller__U393":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -20672,49 +20983,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U333":{ + "_U402":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3331":{ + "_U4021":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U334":{ + "_U403":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U331":{ + "affine_func$add_all__U400":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U332":{ + "affine_func$add_all__U401":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U326":{ + "affine_func$coeff_0_U395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U328":{ + "affine_func$coeff_1_U397":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U330":{ + "affine_func$const_term_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U327":{ + "affine_func$mul_d0__U396":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U329":{ + "affine_func$mul_d1__U398":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -20778,12 +21089,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U335$c0_lutcnst":{ + "d_0_am__U404$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U335$lut$lut":{ + "d_0_am__U404$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -20902,18 +21213,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U333.out"], - ["d_1_inc.in1","_U3331.out"], - ["cmp_time.in1","_U334.out"], - ["affine_func$mul_d0__U327.out","affine_func$add_all__U331.in0"], - ["affine_func$mul_d1__U329.out","affine_func$add_all__U331.in1"], - ["affine_func$add_all__U332.in0","affine_func$add_all__U331.out"], - ["affine_func$const_term_U330.out","affine_func$add_all__U332.in1"], - ["time_diff.in0","affine_func$add_all__U332.out"], - ["affine_func$mul_d0__U327.in0","affine_func$coeff_0_U326.out"], - ["affine_func$mul_d1__U329.in0","affine_func$coeff_1_U328.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U327.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U329.in1"], + ["d_0_inc.in1","_U402.out"], + ["d_1_inc.in1","_U4021.out"], + ["cmp_time.in1","_U403.out"], + ["affine_func$mul_d0__U396.out","affine_func$add_all__U400.in0"], + ["affine_func$mul_d1__U398.out","affine_func$add_all__U400.in1"], + ["affine_func$add_all__U401.in0","affine_func$add_all__U400.out"], + ["affine_func$const_term_U399.out","affine_func$add_all__U401.in1"], + ["time_diff.in0","affine_func$add_all__U401.out"], + ["affine_func$mul_d0__U396.in0","affine_func$coeff_0_U395.out"], + ["affine_func$mul_d1__U398.in0","affine_func$coeff_1_U397.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U396.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U398.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -20936,10 +21247,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U335$lut$lut.bit.in.2","d_0_am__U335$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U335$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U335$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U335$lut$lut.bit.out"], + ["d_0_am__U404$lut$lut.bit.in.2","d_0_am__U404$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U404$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U404$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U404$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -20975,7 +21286,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U339":{ + "affine_controller__U407":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -20983,49 +21294,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U348":{ + "_U416":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3481":{ + "_U4161":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U349":{ + "_U417":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U346":{ + "affine_func$add_all__U414":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U347":{ + "affine_func$add_all__U415":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U341":{ + "affine_func$coeff_0_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U343":{ + "affine_func$coeff_1_U411":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U345":{ + "affine_func$const_term_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U342":{ + "affine_func$mul_d0__U410":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U344":{ + "affine_func$mul_d1__U412":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -21089,12 +21400,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U350$c0_lutcnst":{ + "d_0_am__U418$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U350$lut$lut":{ + "d_0_am__U418$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -21213,18 +21524,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U348.out"], - ["d_1_inc.in1","_U3481.out"], - ["cmp_time.in1","_U349.out"], - ["affine_func$mul_d0__U342.out","affine_func$add_all__U346.in0"], - ["affine_func$mul_d1__U344.out","affine_func$add_all__U346.in1"], - ["affine_func$add_all__U347.in0","affine_func$add_all__U346.out"], - ["affine_func$const_term_U345.out","affine_func$add_all__U347.in1"], - ["time_diff.in0","affine_func$add_all__U347.out"], - ["affine_func$mul_d0__U342.in0","affine_func$coeff_0_U341.out"], - ["affine_func$mul_d1__U344.in0","affine_func$coeff_1_U343.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U342.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U344.in1"], + ["d_0_inc.in1","_U416.out"], + ["d_1_inc.in1","_U4161.out"], + ["cmp_time.in1","_U417.out"], + ["affine_func$mul_d0__U410.out","affine_func$add_all__U414.in0"], + ["affine_func$mul_d1__U412.out","affine_func$add_all__U414.in1"], + ["affine_func$add_all__U415.in0","affine_func$add_all__U414.out"], + ["affine_func$const_term_U413.out","affine_func$add_all__U415.in1"], + ["time_diff.in0","affine_func$add_all__U415.out"], + ["affine_func$mul_d0__U410.in0","affine_func$coeff_0_U409.out"], + ["affine_func$mul_d1__U412.in0","affine_func$coeff_1_U411.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U410.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U412.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -21247,10 +21558,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U350$lut$lut.bit.in.2","d_0_am__U350$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U350$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U350$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U350$lut$lut.bit.out"], + ["d_0_am__U418$lut$lut.bit.in.2","d_0_am__U418$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U418$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U418$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U418$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -21286,7 +21597,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U354":{ + "affine_controller__U421":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -21294,49 +21605,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U363":{ + "_U430":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3631":{ + "_U4301":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U364":{ + "_U431":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U361":{ + "affine_func$add_all__U428":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U362":{ + "affine_func$add_all__U429":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U356":{ + "affine_func$coeff_0_U423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U358":{ + "affine_func$coeff_1_U425":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U360":{ + "affine_func$const_term_U427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U357":{ + "affine_func$mul_d0__U424":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U359":{ + "affine_func$mul_d1__U426":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -21400,12 +21711,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U365$c0_lutcnst":{ + "d_0_am__U432$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U365$lut$lut":{ + "d_0_am__U432$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -21524,18 +21835,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U363.out"], - ["d_1_inc.in1","_U3631.out"], - ["cmp_time.in1","_U364.out"], - ["affine_func$mul_d0__U357.out","affine_func$add_all__U361.in0"], - ["affine_func$mul_d1__U359.out","affine_func$add_all__U361.in1"], - ["affine_func$add_all__U362.in0","affine_func$add_all__U361.out"], - ["affine_func$const_term_U360.out","affine_func$add_all__U362.in1"], - ["time_diff.in0","affine_func$add_all__U362.out"], - ["affine_func$mul_d0__U357.in0","affine_func$coeff_0_U356.out"], - ["affine_func$mul_d1__U359.in0","affine_func$coeff_1_U358.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U357.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U359.in1"], + ["d_0_inc.in1","_U430.out"], + ["d_1_inc.in1","_U4301.out"], + ["cmp_time.in1","_U431.out"], + ["affine_func$mul_d0__U424.out","affine_func$add_all__U428.in0"], + ["affine_func$mul_d1__U426.out","affine_func$add_all__U428.in1"], + ["affine_func$add_all__U429.in0","affine_func$add_all__U428.out"], + ["affine_func$const_term_U427.out","affine_func$add_all__U429.in1"], + ["time_diff.in0","affine_func$add_all__U429.out"], + ["affine_func$mul_d0__U424.in0","affine_func$coeff_0_U423.out"], + ["affine_func$mul_d1__U426.in0","affine_func$coeff_1_U425.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U424.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U426.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -21558,10 +21869,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U365$lut$lut.bit.in.2","d_0_am__U365$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U365$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U365$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U365$lut$lut.bit.out"], + ["d_0_am__U432$lut$lut.bit.in.2","d_0_am__U432$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U432$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U432$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U432$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -21597,7 +21908,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U369":{ + "affine_controller__U43":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -21605,49 +21916,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U378":{ + "_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3781":{ + "_U521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U379":{ + "_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U376":{ + "affine_func$add_all__U50":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U377":{ + "affine_func$add_all__U51":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U371":{ + "affine_func$coeff_0_U45":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U373":{ + "affine_func$coeff_1_U47":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U375":{ + "affine_func$const_term_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U372":{ + "affine_func$mul_d0__U46":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U374":{ + "affine_func$mul_d1__U48":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -21711,12 +22022,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U380$c0_lutcnst":{ + "d_0_am__U54$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U380$lut$lut":{ + "d_0_am__U54$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -21835,18 +22146,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U378.out"], - ["d_1_inc.in1","_U3781.out"], - ["cmp_time.in1","_U379.out"], - ["affine_func$mul_d0__U372.out","affine_func$add_all__U376.in0"], - ["affine_func$mul_d1__U374.out","affine_func$add_all__U376.in1"], - ["affine_func$add_all__U377.in0","affine_func$add_all__U376.out"], - ["affine_func$const_term_U375.out","affine_func$add_all__U377.in1"], - ["time_diff.in0","affine_func$add_all__U377.out"], - ["affine_func$mul_d0__U372.in0","affine_func$coeff_0_U371.out"], - ["affine_func$mul_d1__U374.in0","affine_func$coeff_1_U373.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U372.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U374.in1"], + ["d_0_inc.in1","_U52.out"], + ["d_1_inc.in1","_U521.out"], + ["cmp_time.in1","_U53.out"], + ["affine_func$mul_d0__U46.out","affine_func$add_all__U50.in0"], + ["affine_func$mul_d1__U48.out","affine_func$add_all__U50.in1"], + ["affine_func$add_all__U51.in0","affine_func$add_all__U50.out"], + ["affine_func$const_term_U49.out","affine_func$add_all__U51.in1"], + ["time_diff.in0","affine_func$add_all__U51.out"], + ["affine_func$mul_d0__U46.in0","affine_func$coeff_0_U45.out"], + ["affine_func$mul_d1__U48.in0","affine_func$coeff_1_U47.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U46.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U48.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -21869,10 +22180,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U380$lut$lut.bit.in.2","d_0_am__U380$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U380$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U380$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U380$lut$lut.bit.out"], + ["d_0_am__U54$lut$lut.bit.in.2","d_0_am__U54$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U54$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U54$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U54$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -21908,7 +22219,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U384":{ + "affine_controller__U435":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -21916,49 +22227,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U393":{ + "_U444":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U3931":{ + "_U4441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U394":{ + "_U445":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U391":{ + "affine_func$add_all__U442":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U392":{ + "affine_func$add_all__U443":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U386":{ + "affine_func$coeff_0_U437":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U388":{ + "affine_func$coeff_1_U439":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U390":{ + "affine_func$const_term_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U387":{ + "affine_func$mul_d0__U438":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U389":{ + "affine_func$mul_d1__U440":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -22022,12 +22333,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U395$c0_lutcnst":{ + "d_0_am__U446$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U395$lut$lut":{ + "d_0_am__U446$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -22146,18 +22457,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U393.out"], - ["d_1_inc.in1","_U3931.out"], - ["cmp_time.in1","_U394.out"], - ["affine_func$mul_d0__U387.out","affine_func$add_all__U391.in0"], - ["affine_func$mul_d1__U389.out","affine_func$add_all__U391.in1"], - ["affine_func$add_all__U392.in0","affine_func$add_all__U391.out"], - ["affine_func$const_term_U390.out","affine_func$add_all__U392.in1"], - ["time_diff.in0","affine_func$add_all__U392.out"], - ["affine_func$mul_d0__U387.in0","affine_func$coeff_0_U386.out"], - ["affine_func$mul_d1__U389.in0","affine_func$coeff_1_U388.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U387.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U389.in1"], + ["d_0_inc.in1","_U444.out"], + ["d_1_inc.in1","_U4441.out"], + ["cmp_time.in1","_U445.out"], + ["affine_func$mul_d0__U438.out","affine_func$add_all__U442.in0"], + ["affine_func$mul_d1__U440.out","affine_func$add_all__U442.in1"], + ["affine_func$add_all__U443.in0","affine_func$add_all__U442.out"], + ["affine_func$const_term_U441.out","affine_func$add_all__U443.in1"], + ["time_diff.in0","affine_func$add_all__U443.out"], + ["affine_func$mul_d0__U438.in0","affine_func$coeff_0_U437.out"], + ["affine_func$mul_d1__U440.in0","affine_func$coeff_1_U439.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U438.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U440.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -22180,10 +22491,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U395$lut$lut.bit.in.2","d_0_am__U395$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U395$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U395$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U395$lut$lut.bit.out"], + ["d_0_am__U446$lut$lut.bit.in.2","d_0_am__U446$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U446$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U446$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U446$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -22219,7 +22530,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U399":{ + "affine_controller__U449":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -22227,49 +22538,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U408":{ + "_U458":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4081":{ + "_U4581":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U409":{ + "_U459":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U406":{ + "affine_func$add_all__U456":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U407":{ + "affine_func$add_all__U457":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U401":{ + "affine_func$coeff_0_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U403":{ + "affine_func$coeff_1_U453":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U405":{ + "affine_func$const_term_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U402":{ + "affine_func$mul_d0__U452":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U404":{ + "affine_func$mul_d1__U454":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -22333,12 +22644,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U410$c0_lutcnst":{ + "d_0_am__U460$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U410$lut$lut":{ + "d_0_am__U460$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -22457,18 +22768,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U408.out"], - ["d_1_inc.in1","_U4081.out"], - ["cmp_time.in1","_U409.out"], - ["affine_func$mul_d0__U402.out","affine_func$add_all__U406.in0"], - ["affine_func$mul_d1__U404.out","affine_func$add_all__U406.in1"], - ["affine_func$add_all__U407.in0","affine_func$add_all__U406.out"], - ["affine_func$const_term_U405.out","affine_func$add_all__U407.in1"], - ["time_diff.in0","affine_func$add_all__U407.out"], - ["affine_func$mul_d0__U402.in0","affine_func$coeff_0_U401.out"], - ["affine_func$mul_d1__U404.in0","affine_func$coeff_1_U403.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U402.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U404.in1"], + ["d_0_inc.in1","_U458.out"], + ["d_1_inc.in1","_U4581.out"], + ["cmp_time.in1","_U459.out"], + ["affine_func$mul_d0__U452.out","affine_func$add_all__U456.in0"], + ["affine_func$mul_d1__U454.out","affine_func$add_all__U456.in1"], + ["affine_func$add_all__U457.in0","affine_func$add_all__U456.out"], + ["affine_func$const_term_U455.out","affine_func$add_all__U457.in1"], + ["time_diff.in0","affine_func$add_all__U457.out"], + ["affine_func$mul_d0__U452.in0","affine_func$coeff_0_U451.out"], + ["affine_func$mul_d1__U454.in0","affine_func$coeff_1_U453.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U452.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U454.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -22491,10 +22802,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U410$lut$lut.bit.in.2","d_0_am__U410$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U410$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U410$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U410$lut$lut.bit.out"], + ["d_0_am__U460$lut$lut.bit.in.2","d_0_am__U460$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U460$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U460$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U460$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -22530,7 +22841,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U414":{ + "affine_controller__U463":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -22538,49 +22849,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U423":{ + "_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4231":{ + "_U4721":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U424":{ + "_U473":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U421":{ + "affine_func$add_all__U470":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U422":{ + "affine_func$add_all__U471":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U416":{ + "affine_func$coeff_0_U465":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U418":{ + "affine_func$coeff_1_U467":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U420":{ + "affine_func$const_term_U469":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U417":{ + "affine_func$mul_d0__U466":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U419":{ + "affine_func$mul_d1__U468":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -22644,12 +22955,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U425$c0_lutcnst":{ + "d_0_am__U474$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U425$lut$lut":{ + "d_0_am__U474$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -22768,18 +23079,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U423.out"], - ["d_1_inc.in1","_U4231.out"], - ["cmp_time.in1","_U424.out"], - ["affine_func$mul_d0__U417.out","affine_func$add_all__U421.in0"], - ["affine_func$mul_d1__U419.out","affine_func$add_all__U421.in1"], - ["affine_func$add_all__U422.in0","affine_func$add_all__U421.out"], - ["affine_func$const_term_U420.out","affine_func$add_all__U422.in1"], - ["time_diff.in0","affine_func$add_all__U422.out"], - ["affine_func$mul_d0__U417.in0","affine_func$coeff_0_U416.out"], - ["affine_func$mul_d1__U419.in0","affine_func$coeff_1_U418.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U417.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U419.in1"], + ["d_0_inc.in1","_U472.out"], + ["d_1_inc.in1","_U4721.out"], + ["cmp_time.in1","_U473.out"], + ["affine_func$mul_d0__U466.out","affine_func$add_all__U470.in0"], + ["affine_func$mul_d1__U468.out","affine_func$add_all__U470.in1"], + ["affine_func$add_all__U471.in0","affine_func$add_all__U470.out"], + ["affine_func$const_term_U469.out","affine_func$add_all__U471.in1"], + ["time_diff.in0","affine_func$add_all__U471.out"], + ["affine_func$mul_d0__U466.in0","affine_func$coeff_0_U465.out"], + ["affine_func$mul_d1__U468.in0","affine_func$coeff_1_U467.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U466.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U468.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -22802,10 +23113,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U425$lut$lut.bit.in.2","d_0_am__U425$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U425$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U425$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U425$lut$lut.bit.out"], + ["d_0_am__U474$lut$lut.bit.in.2","d_0_am__U474$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U474$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U474$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U474$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -22841,7 +23152,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U429":{ + "affine_controller__U477":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -22849,49 +23160,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U438":{ + "_U486":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4381":{ + "_U4861":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U439":{ + "_U487":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U436":{ + "affine_func$add_all__U484":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U437":{ + "affine_func$add_all__U485":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U431":{ + "affine_func$coeff_0_U479":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U433":{ + "affine_func$coeff_1_U481":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U435":{ + "affine_func$const_term_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U432":{ + "affine_func$mul_d0__U480":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U434":{ + "affine_func$mul_d1__U482":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -22955,12 +23266,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U440$c0_lutcnst":{ + "d_0_am__U488$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U440$lut$lut":{ + "d_0_am__U488$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -23079,18 +23390,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U438.out"], - ["d_1_inc.in1","_U4381.out"], - ["cmp_time.in1","_U439.out"], - ["affine_func$mul_d0__U432.out","affine_func$add_all__U436.in0"], - ["affine_func$mul_d1__U434.out","affine_func$add_all__U436.in1"], - ["affine_func$add_all__U437.in0","affine_func$add_all__U436.out"], - ["affine_func$const_term_U435.out","affine_func$add_all__U437.in1"], - ["time_diff.in0","affine_func$add_all__U437.out"], - ["affine_func$mul_d0__U432.in0","affine_func$coeff_0_U431.out"], - ["affine_func$mul_d1__U434.in0","affine_func$coeff_1_U433.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U432.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U434.in1"], + ["d_0_inc.in1","_U486.out"], + ["d_1_inc.in1","_U4861.out"], + ["cmp_time.in1","_U487.out"], + ["affine_func$mul_d0__U480.out","affine_func$add_all__U484.in0"], + ["affine_func$mul_d1__U482.out","affine_func$add_all__U484.in1"], + ["affine_func$add_all__U485.in0","affine_func$add_all__U484.out"], + ["affine_func$const_term_U483.out","affine_func$add_all__U485.in1"], + ["time_diff.in0","affine_func$add_all__U485.out"], + ["affine_func$mul_d0__U480.in0","affine_func$coeff_0_U479.out"], + ["affine_func$mul_d1__U482.in0","affine_func$coeff_1_U481.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U480.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U482.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -23113,10 +23424,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U440$lut$lut.bit.in.2","d_0_am__U440$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U440$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U440$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U440$lut$lut.bit.out"], + ["d_0_am__U488$lut$lut.bit.in.2","d_0_am__U488$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U488$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U488$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U488$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -23152,7 +23463,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U444":{ + "affine_controller__U491":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -23160,49 +23471,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U453":{ + "_U500":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4531":{ + "_U5001":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U454":{ + "_U501":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U451":{ + "affine_func$add_all__U498":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U452":{ + "affine_func$add_all__U499":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U446":{ + "affine_func$coeff_0_U493":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U448":{ + "affine_func$coeff_1_U495":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U450":{ + "affine_func$const_term_U497":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U447":{ + "affine_func$mul_d0__U494":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U449":{ + "affine_func$mul_d1__U496":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -23266,12 +23577,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U455$c0_lutcnst":{ + "d_0_am__U502$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U455$lut$lut":{ + "d_0_am__U502$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -23390,18 +23701,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U453.out"], - ["d_1_inc.in1","_U4531.out"], - ["cmp_time.in1","_U454.out"], - ["affine_func$mul_d0__U447.out","affine_func$add_all__U451.in0"], - ["affine_func$mul_d1__U449.out","affine_func$add_all__U451.in1"], - ["affine_func$add_all__U452.in0","affine_func$add_all__U451.out"], - ["affine_func$const_term_U450.out","affine_func$add_all__U452.in1"], - ["time_diff.in0","affine_func$add_all__U452.out"], - ["affine_func$mul_d0__U447.in0","affine_func$coeff_0_U446.out"], - ["affine_func$mul_d1__U449.in0","affine_func$coeff_1_U448.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U447.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U449.in1"], + ["d_0_inc.in1","_U500.out"], + ["d_1_inc.in1","_U5001.out"], + ["cmp_time.in1","_U501.out"], + ["affine_func$mul_d0__U494.out","affine_func$add_all__U498.in0"], + ["affine_func$mul_d1__U496.out","affine_func$add_all__U498.in1"], + ["affine_func$add_all__U499.in0","affine_func$add_all__U498.out"], + ["affine_func$const_term_U497.out","affine_func$add_all__U499.in1"], + ["time_diff.in0","affine_func$add_all__U499.out"], + ["affine_func$mul_d0__U494.in0","affine_func$coeff_0_U493.out"], + ["affine_func$mul_d1__U496.in0","affine_func$coeff_1_U495.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U494.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U496.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -23424,10 +23735,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U455$lut$lut.bit.in.2","d_0_am__U455$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U455$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U455$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U455$lut$lut.bit.out"], + ["d_0_am__U502$lut$lut.bit.in.2","d_0_am__U502$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U502$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U502$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U502$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -23463,7 +23774,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U459":{ + "affine_controller__U505":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -23471,49 +23782,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U468":{ + "_U514":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4681":{ + "_U5141":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U469":{ + "_U515":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U466":{ + "affine_func$add_all__U512":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U467":{ + "affine_func$add_all__U513":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U461":{ + "affine_func$coeff_0_U507":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U463":{ + "affine_func$coeff_1_U509":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U465":{ + "affine_func$const_term_U511":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U462":{ + "affine_func$mul_d0__U508":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U464":{ + "affine_func$mul_d1__U510":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -23577,12 +23888,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U470$c0_lutcnst":{ + "d_0_am__U516$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U470$lut$lut":{ + "d_0_am__U516$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -23701,18 +24012,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U468.out"], - ["d_1_inc.in1","_U4681.out"], - ["cmp_time.in1","_U469.out"], - ["affine_func$mul_d0__U462.out","affine_func$add_all__U466.in0"], - ["affine_func$mul_d1__U464.out","affine_func$add_all__U466.in1"], - ["affine_func$add_all__U467.in0","affine_func$add_all__U466.out"], - ["affine_func$const_term_U465.out","affine_func$add_all__U467.in1"], - ["time_diff.in0","affine_func$add_all__U467.out"], - ["affine_func$mul_d0__U462.in0","affine_func$coeff_0_U461.out"], - ["affine_func$mul_d1__U464.in0","affine_func$coeff_1_U463.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U462.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U464.in1"], + ["d_0_inc.in1","_U514.out"], + ["d_1_inc.in1","_U5141.out"], + ["cmp_time.in1","_U515.out"], + ["affine_func$mul_d0__U508.out","affine_func$add_all__U512.in0"], + ["affine_func$mul_d1__U510.out","affine_func$add_all__U512.in1"], + ["affine_func$add_all__U513.in0","affine_func$add_all__U512.out"], + ["affine_func$const_term_U511.out","affine_func$add_all__U513.in1"], + ["time_diff.in0","affine_func$add_all__U513.out"], + ["affine_func$mul_d0__U508.in0","affine_func$coeff_0_U507.out"], + ["affine_func$mul_d1__U510.in0","affine_func$coeff_1_U509.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U508.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U510.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -23735,10 +24046,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U470$lut$lut.bit.in.2","d_0_am__U470$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U470$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U470$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U470$lut$lut.bit.out"], + ["d_0_am__U516$lut$lut.bit.in.2","d_0_am__U516$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U516$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U516$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U516$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -23774,7 +24085,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U46":{ + "affine_controller__U519":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -23782,49 +24093,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U55":{ + "_U528":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U551":{ + "_U5281":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U56":{ + "_U529":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U53":{ + "affine_func$add_all__U526":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U54":{ + "affine_func$add_all__U527":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U48":{ + "affine_func$coeff_0_U521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U50":{ + "affine_func$coeff_1_U523":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U52":{ + "affine_func$const_term_U525":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U49":{ + "affine_func$mul_d0__U522":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U51":{ + "affine_func$mul_d1__U524":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -23888,12 +24199,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U57$c0_lutcnst":{ + "d_0_am__U530$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U57$lut$lut":{ + "d_0_am__U530$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -24012,18 +24323,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U55.out"], - ["d_1_inc.in1","_U551.out"], - ["cmp_time.in1","_U56.out"], - ["affine_func$mul_d0__U49.out","affine_func$add_all__U53.in0"], - ["affine_func$mul_d1__U51.out","affine_func$add_all__U53.in1"], - ["affine_func$add_all__U54.in0","affine_func$add_all__U53.out"], - ["affine_func$const_term_U52.out","affine_func$add_all__U54.in1"], - ["time_diff.in0","affine_func$add_all__U54.out"], - ["affine_func$mul_d0__U49.in0","affine_func$coeff_0_U48.out"], - ["affine_func$mul_d1__U51.in0","affine_func$coeff_1_U50.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U49.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U51.in1"], + ["d_0_inc.in1","_U528.out"], + ["d_1_inc.in1","_U5281.out"], + ["cmp_time.in1","_U529.out"], + ["affine_func$mul_d0__U522.out","affine_func$add_all__U526.in0"], + ["affine_func$mul_d1__U524.out","affine_func$add_all__U526.in1"], + ["affine_func$add_all__U527.in0","affine_func$add_all__U526.out"], + ["affine_func$const_term_U525.out","affine_func$add_all__U527.in1"], + ["time_diff.in0","affine_func$add_all__U527.out"], + ["affine_func$mul_d0__U522.in0","affine_func$coeff_0_U521.out"], + ["affine_func$mul_d1__U524.in0","affine_func$coeff_1_U523.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U522.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U524.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -24046,321 +24357,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U57$lut$lut.bit.in.2","d_0_am__U57$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U57$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U57$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U57$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["true_lutcnst.bit.out","d_1_next_value.sel"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"] - ] - }, - "affine_controller__U474":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",2,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U483":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U4831":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U484":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$add_all__U481":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U482":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U476":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$coeff_1_U478":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$const_term_U480":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00012000"]} - }, - "affine_func$mul_d0__U477":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U479":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "cycle_time$and$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$and$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "cycle_time$count$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$count$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} - }, - "cycle_time$ult":{ - "genref":"coreir.ult", - "genargs":{"width":["Int",32]} - }, - "d_0_am__U485$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U485$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true2_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true3_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U483.out"], - ["d_1_inc.in1","_U4831.out"], - ["cmp_time.in1","_U484.out"], - ["affine_func$mul_d0__U477.out","affine_func$add_all__U481.in0"], - ["affine_func$mul_d1__U479.out","affine_func$add_all__U481.in1"], - ["affine_func$add_all__U482.in0","affine_func$add_all__U481.out"], - ["affine_func$const_term_U480.out","affine_func$add_all__U482.in1"], - ["time_diff.in0","affine_func$add_all__U482.out"], - ["affine_func$mul_d0__U477.in0","affine_func$coeff_0_U476.out"], - ["affine_func$mul_d1__U479.in0","affine_func$coeff_1_U478.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U477.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U479.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true3_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true2_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U485$lut$lut.bit.in.2","d_0_am__U485$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U485$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U485$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U485$lut$lut.bit.out"], + ["d_0_am__U530$lut$lut.bit.in.2","d_0_am__U530$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U530$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U530$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U530$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -24396,7 +24396,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U489":{ + "affine_controller__U533":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -24404,49 +24404,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U498":{ + "_U542":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4981":{ + "_U5421":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U499":{ + "_U543":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U496":{ + "affine_func$add_all__U540":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U497":{ + "affine_func$add_all__U541":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U491":{ + "affine_func$coeff_0_U535":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U493":{ + "affine_func$coeff_1_U537":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U495":{ + "affine_func$const_term_U539":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U492":{ + "affine_func$mul_d0__U536":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U494":{ + "affine_func$mul_d1__U538":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -24510,12 +24510,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U500$c0_lutcnst":{ + "d_0_am__U544$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U500$lut$lut":{ + "d_0_am__U544$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -24634,18 +24634,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U498.out"], - ["d_1_inc.in1","_U4981.out"], - ["cmp_time.in1","_U499.out"], - ["affine_func$mul_d0__U492.out","affine_func$add_all__U496.in0"], - ["affine_func$mul_d1__U494.out","affine_func$add_all__U496.in1"], - ["affine_func$add_all__U497.in0","affine_func$add_all__U496.out"], - ["affine_func$const_term_U495.out","affine_func$add_all__U497.in1"], - ["time_diff.in0","affine_func$add_all__U497.out"], - ["affine_func$mul_d0__U492.in0","affine_func$coeff_0_U491.out"], - ["affine_func$mul_d1__U494.in0","affine_func$coeff_1_U493.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U492.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U494.in1"], + ["d_0_inc.in1","_U542.out"], + ["d_1_inc.in1","_U5421.out"], + ["cmp_time.in1","_U543.out"], + ["affine_func$mul_d0__U536.out","affine_func$add_all__U540.in0"], + ["affine_func$mul_d1__U538.out","affine_func$add_all__U540.in1"], + ["affine_func$add_all__U541.in0","affine_func$add_all__U540.out"], + ["affine_func$const_term_U539.out","affine_func$add_all__U541.in1"], + ["time_diff.in0","affine_func$add_all__U541.out"], + ["affine_func$mul_d0__U536.in0","affine_func$coeff_0_U535.out"], + ["affine_func$mul_d1__U538.in0","affine_func$coeff_1_U537.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U536.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U538.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -24668,10 +24668,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U500$lut$lut.bit.in.2","d_0_am__U500$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U500$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U500$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U500$lut$lut.bit.out"], + ["d_0_am__U544$lut$lut.bit.in.2","d_0_am__U544$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U544$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U544$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U544$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -24707,7 +24707,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U504":{ + "affine_controller__U547":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -24715,49 +24715,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U513":{ + "_U556":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5131":{ + "_U5561":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U514":{ + "_U557":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U511":{ + "affine_func$add_all__U554":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U512":{ + "affine_func$add_all__U555":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U506":{ + "affine_func$coeff_0_U549":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U508":{ + "affine_func$coeff_1_U551":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U510":{ + "affine_func$const_term_U553":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U507":{ + "affine_func$mul_d0__U550":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U509":{ + "affine_func$mul_d1__U552":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -24821,12 +24821,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U515$c0_lutcnst":{ + "d_0_am__U558$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U515$lut$lut":{ + "d_0_am__U558$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -24945,18 +24945,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U513.out"], - ["d_1_inc.in1","_U5131.out"], - ["cmp_time.in1","_U514.out"], - ["affine_func$mul_d0__U507.out","affine_func$add_all__U511.in0"], - ["affine_func$mul_d1__U509.out","affine_func$add_all__U511.in1"], - ["affine_func$add_all__U512.in0","affine_func$add_all__U511.out"], - ["affine_func$const_term_U510.out","affine_func$add_all__U512.in1"], - ["time_diff.in0","affine_func$add_all__U512.out"], - ["affine_func$mul_d0__U507.in0","affine_func$coeff_0_U506.out"], - ["affine_func$mul_d1__U509.in0","affine_func$coeff_1_U508.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U507.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U509.in1"], + ["d_0_inc.in1","_U556.out"], + ["d_1_inc.in1","_U5561.out"], + ["cmp_time.in1","_U557.out"], + ["affine_func$mul_d0__U550.out","affine_func$add_all__U554.in0"], + ["affine_func$mul_d1__U552.out","affine_func$add_all__U554.in1"], + ["affine_func$add_all__U555.in0","affine_func$add_all__U554.out"], + ["affine_func$const_term_U553.out","affine_func$add_all__U555.in1"], + ["time_diff.in0","affine_func$add_all__U555.out"], + ["affine_func$mul_d0__U550.in0","affine_func$coeff_0_U549.out"], + ["affine_func$mul_d1__U552.in0","affine_func$coeff_1_U551.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U550.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U552.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -24979,10 +24979,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U515$lut$lut.bit.in.2","d_0_am__U515$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U515$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U515$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U515$lut$lut.bit.out"], + ["d_0_am__U558$lut$lut.bit.in.2","d_0_am__U558$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U558$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U558$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U558$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -25018,7 +25018,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U519":{ + "affine_controller__U561":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -25026,49 +25026,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U528":{ + "_U570":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5281":{ + "_U5701":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U529":{ + "_U571":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U526":{ + "affine_func$add_all__U568":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U527":{ + "affine_func$add_all__U569":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U521":{ + "affine_func$coeff_0_U563":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U523":{ + "affine_func$coeff_1_U565":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U525":{ + "affine_func$const_term_U567":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U522":{ + "affine_func$mul_d0__U564":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U524":{ + "affine_func$mul_d1__U566":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -25132,12 +25132,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U530$c0_lutcnst":{ + "d_0_am__U572$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U530$lut$lut":{ + "d_0_am__U572$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -25256,18 +25256,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U528.out"], - ["d_1_inc.in1","_U5281.out"], - ["cmp_time.in1","_U529.out"], - ["affine_func$mul_d0__U522.out","affine_func$add_all__U526.in0"], - ["affine_func$mul_d1__U524.out","affine_func$add_all__U526.in1"], - ["affine_func$add_all__U527.in0","affine_func$add_all__U526.out"], - ["affine_func$const_term_U525.out","affine_func$add_all__U527.in1"], - ["time_diff.in0","affine_func$add_all__U527.out"], - ["affine_func$mul_d0__U522.in0","affine_func$coeff_0_U521.out"], - ["affine_func$mul_d1__U524.in0","affine_func$coeff_1_U523.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U522.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U524.in1"], + ["d_0_inc.in1","_U570.out"], + ["d_1_inc.in1","_U5701.out"], + ["cmp_time.in1","_U571.out"], + ["affine_func$mul_d0__U564.out","affine_func$add_all__U568.in0"], + ["affine_func$mul_d1__U566.out","affine_func$add_all__U568.in1"], + ["affine_func$add_all__U569.in0","affine_func$add_all__U568.out"], + ["affine_func$const_term_U567.out","affine_func$add_all__U569.in1"], + ["time_diff.in0","affine_func$add_all__U569.out"], + ["affine_func$mul_d0__U564.in0","affine_func$coeff_0_U563.out"], + ["affine_func$mul_d1__U566.in0","affine_func$coeff_1_U565.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U564.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U566.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -25290,10 +25290,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U530$lut$lut.bit.in.2","d_0_am__U530$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U530$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U530$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U530$lut$lut.bit.out"], + ["d_0_am__U572$lut$lut.bit.in.2","d_0_am__U572$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U572$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U572$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U572$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -25329,7 +25329,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U534":{ + "affine_controller__U57":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -25337,49 +25337,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U543":{ + "_U66":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5431":{ + "_U661":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U544":{ + "_U67":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U541":{ + "affine_func$add_all__U64":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U542":{ + "affine_func$add_all__U65":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U536":{ + "affine_func$coeff_0_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U538":{ + "affine_func$coeff_1_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U540":{ + "affine_func$const_term_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U537":{ + "affine_func$mul_d0__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U539":{ + "affine_func$mul_d1__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -25443,12 +25443,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U545$c0_lutcnst":{ + "d_0_am__U68$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U545$lut$lut":{ + "d_0_am__U68$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -25567,18 +25567,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U543.out"], - ["d_1_inc.in1","_U5431.out"], - ["cmp_time.in1","_U544.out"], - ["affine_func$mul_d0__U537.out","affine_func$add_all__U541.in0"], - ["affine_func$mul_d1__U539.out","affine_func$add_all__U541.in1"], - ["affine_func$add_all__U542.in0","affine_func$add_all__U541.out"], - ["affine_func$const_term_U540.out","affine_func$add_all__U542.in1"], - ["time_diff.in0","affine_func$add_all__U542.out"], - ["affine_func$mul_d0__U537.in0","affine_func$coeff_0_U536.out"], - ["affine_func$mul_d1__U539.in0","affine_func$coeff_1_U538.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U537.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U539.in1"], + ["d_0_inc.in1","_U66.out"], + ["d_1_inc.in1","_U661.out"], + ["cmp_time.in1","_U67.out"], + ["affine_func$mul_d0__U60.out","affine_func$add_all__U64.in0"], + ["affine_func$mul_d1__U62.out","affine_func$add_all__U64.in1"], + ["affine_func$add_all__U65.in0","affine_func$add_all__U64.out"], + ["affine_func$const_term_U63.out","affine_func$add_all__U65.in1"], + ["time_diff.in0","affine_func$add_all__U65.out"], + ["affine_func$mul_d0__U60.in0","affine_func$coeff_0_U59.out"], + ["affine_func$mul_d1__U62.in0","affine_func$coeff_1_U61.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U60.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U62.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -25601,10 +25601,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U545$lut$lut.bit.in.2","d_0_am__U545$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U545$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U545$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U545$lut$lut.bit.out"], + ["d_0_am__U68$lut$lut.bit.in.2","d_0_am__U68$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U68$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U68$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U68$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -25640,7 +25640,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U549":{ + "affine_controller__U575":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -25648,49 +25648,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U558":{ + "_U584":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5581":{ + "_U5841":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U559":{ + "_U585":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U556":{ + "affine_func$add_all__U582":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U557":{ + "affine_func$add_all__U583":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U551":{ + "affine_func$coeff_0_U577":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U553":{ + "affine_func$coeff_1_U579":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U555":{ + "affine_func$const_term_U581":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U552":{ + "affine_func$mul_d0__U578":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U554":{ + "affine_func$mul_d1__U580":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -25754,12 +25754,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U560$c0_lutcnst":{ + "d_0_am__U586$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U560$lut$lut":{ + "d_0_am__U586$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -25878,18 +25878,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U558.out"], - ["d_1_inc.in1","_U5581.out"], - ["cmp_time.in1","_U559.out"], - ["affine_func$mul_d0__U552.out","affine_func$add_all__U556.in0"], - ["affine_func$mul_d1__U554.out","affine_func$add_all__U556.in1"], - ["affine_func$add_all__U557.in0","affine_func$add_all__U556.out"], - ["affine_func$const_term_U555.out","affine_func$add_all__U557.in1"], - ["time_diff.in0","affine_func$add_all__U557.out"], - ["affine_func$mul_d0__U552.in0","affine_func$coeff_0_U551.out"], - ["affine_func$mul_d1__U554.in0","affine_func$coeff_1_U553.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U552.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U554.in1"], + ["d_0_inc.in1","_U584.out"], + ["d_1_inc.in1","_U5841.out"], + ["cmp_time.in1","_U585.out"], + ["affine_func$mul_d0__U578.out","affine_func$add_all__U582.in0"], + ["affine_func$mul_d1__U580.out","affine_func$add_all__U582.in1"], + ["affine_func$add_all__U583.in0","affine_func$add_all__U582.out"], + ["affine_func$const_term_U581.out","affine_func$add_all__U583.in1"], + ["time_diff.in0","affine_func$add_all__U583.out"], + ["affine_func$mul_d0__U578.in0","affine_func$coeff_0_U577.out"], + ["affine_func$mul_d1__U580.in0","affine_func$coeff_1_U579.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U578.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U580.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -25912,10 +25912,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U560$lut$lut.bit.in.2","d_0_am__U560$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U560$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U560$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U560$lut$lut.bit.out"], + ["d_0_am__U586$lut$lut.bit.in.2","d_0_am__U586$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U586$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U586$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U586$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -25951,7 +25951,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U564":{ + "affine_controller__U589":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -25959,49 +25959,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U573":{ + "_U598":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5731":{ + "_U5981":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U574":{ + "_U599":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U571":{ + "affine_func$add_all__U596":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U572":{ + "affine_func$add_all__U597":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U566":{ + "affine_func$coeff_0_U591":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U568":{ + "affine_func$coeff_1_U593":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U570":{ + "affine_func$const_term_U595":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U567":{ + "affine_func$mul_d0__U592":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U569":{ + "affine_func$mul_d1__U594":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -26065,12 +26065,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U575$c0_lutcnst":{ + "d_0_am__U600$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U575$lut$lut":{ + "d_0_am__U600$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -26189,18 +26189,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U573.out"], - ["d_1_inc.in1","_U5731.out"], - ["cmp_time.in1","_U574.out"], - ["affine_func$mul_d0__U567.out","affine_func$add_all__U571.in0"], - ["affine_func$mul_d1__U569.out","affine_func$add_all__U571.in1"], - ["affine_func$add_all__U572.in0","affine_func$add_all__U571.out"], - ["affine_func$const_term_U570.out","affine_func$add_all__U572.in1"], - ["time_diff.in0","affine_func$add_all__U572.out"], - ["affine_func$mul_d0__U567.in0","affine_func$coeff_0_U566.out"], - ["affine_func$mul_d1__U569.in0","affine_func$coeff_1_U568.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U567.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U569.in1"], + ["d_0_inc.in1","_U598.out"], + ["d_1_inc.in1","_U5981.out"], + ["cmp_time.in1","_U599.out"], + ["affine_func$mul_d0__U592.out","affine_func$add_all__U596.in0"], + ["affine_func$mul_d1__U594.out","affine_func$add_all__U596.in1"], + ["affine_func$add_all__U597.in0","affine_func$add_all__U596.out"], + ["affine_func$const_term_U595.out","affine_func$add_all__U597.in1"], + ["time_diff.in0","affine_func$add_all__U597.out"], + ["affine_func$mul_d0__U592.in0","affine_func$coeff_0_U591.out"], + ["affine_func$mul_d1__U594.in0","affine_func$coeff_1_U593.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U592.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U594.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -26223,10 +26223,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U575$lut$lut.bit.in.2","d_0_am__U575$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U575$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U575$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U575$lut$lut.bit.out"], + ["d_0_am__U600$lut$lut.bit.in.2","d_0_am__U600$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U600$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U600$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U600$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -26262,7 +26262,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U579":{ + "affine_controller__U603":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -26270,49 +26270,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U588":{ + "_U612":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5881":{ + "_U6121":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U589":{ + "_U613":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U586":{ + "affine_func$add_all__U610":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U587":{ + "affine_func$add_all__U611":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U581":{ + "affine_func$coeff_0_U605":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U583":{ + "affine_func$coeff_1_U607":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U585":{ + "affine_func$const_term_U609":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U582":{ + "affine_func$mul_d0__U606":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U584":{ + "affine_func$mul_d1__U608":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -26376,12 +26376,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U590$c0_lutcnst":{ + "d_0_am__U614$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U590$lut$lut":{ + "d_0_am__U614$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -26500,18 +26500,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U588.out"], - ["d_1_inc.in1","_U5881.out"], - ["cmp_time.in1","_U589.out"], - ["affine_func$mul_d0__U582.out","affine_func$add_all__U586.in0"], - ["affine_func$mul_d1__U584.out","affine_func$add_all__U586.in1"], - ["affine_func$add_all__U587.in0","affine_func$add_all__U586.out"], - ["affine_func$const_term_U585.out","affine_func$add_all__U587.in1"], - ["time_diff.in0","affine_func$add_all__U587.out"], - ["affine_func$mul_d0__U582.in0","affine_func$coeff_0_U581.out"], - ["affine_func$mul_d1__U584.in0","affine_func$coeff_1_U583.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U582.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U584.in1"], + ["d_0_inc.in1","_U612.out"], + ["d_1_inc.in1","_U6121.out"], + ["cmp_time.in1","_U613.out"], + ["affine_func$mul_d0__U606.out","affine_func$add_all__U610.in0"], + ["affine_func$mul_d1__U608.out","affine_func$add_all__U610.in1"], + ["affine_func$add_all__U611.in0","affine_func$add_all__U610.out"], + ["affine_func$const_term_U609.out","affine_func$add_all__U611.in1"], + ["time_diff.in0","affine_func$add_all__U611.out"], + ["affine_func$mul_d0__U606.in0","affine_func$coeff_0_U605.out"], + ["affine_func$mul_d1__U608.in0","affine_func$coeff_1_U607.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U606.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U608.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -26534,10 +26534,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U590$lut$lut.bit.in.2","d_0_am__U590$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U590$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U590$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U590$lut$lut.bit.out"], + ["d_0_am__U614$lut$lut.bit.in.2","d_0_am__U614$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U614$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U614$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U614$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -26573,7 +26573,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U594":{ + "affine_controller__U617":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -26581,49 +26581,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U603":{ + "_U626":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6031":{ + "_U6261":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U604":{ + "_U627":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U601":{ + "affine_func$add_all__U624":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U602":{ + "affine_func$add_all__U625":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U596":{ + "affine_func$coeff_0_U619":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U598":{ + "affine_func$coeff_1_U621":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U600":{ + "affine_func$const_term_U623":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U597":{ + "affine_func$mul_d0__U620":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U599":{ + "affine_func$mul_d1__U622":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -26687,12 +26687,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U605$c0_lutcnst":{ + "d_0_am__U628$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U605$lut$lut":{ + "d_0_am__U628$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -26811,18 +26811,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U603.out"], - ["d_1_inc.in1","_U6031.out"], - ["cmp_time.in1","_U604.out"], - ["affine_func$mul_d0__U597.out","affine_func$add_all__U601.in0"], - ["affine_func$mul_d1__U599.out","affine_func$add_all__U601.in1"], - ["affine_func$add_all__U602.in0","affine_func$add_all__U601.out"], - ["affine_func$const_term_U600.out","affine_func$add_all__U602.in1"], - ["time_diff.in0","affine_func$add_all__U602.out"], - ["affine_func$mul_d0__U597.in0","affine_func$coeff_0_U596.out"], - ["affine_func$mul_d1__U599.in0","affine_func$coeff_1_U598.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U597.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U599.in1"], + ["d_0_inc.in1","_U626.out"], + ["d_1_inc.in1","_U6261.out"], + ["cmp_time.in1","_U627.out"], + ["affine_func$mul_d0__U620.out","affine_func$add_all__U624.in0"], + ["affine_func$mul_d1__U622.out","affine_func$add_all__U624.in1"], + ["affine_func$add_all__U625.in0","affine_func$add_all__U624.out"], + ["affine_func$const_term_U623.out","affine_func$add_all__U625.in1"], + ["time_diff.in0","affine_func$add_all__U625.out"], + ["affine_func$mul_d0__U620.in0","affine_func$coeff_0_U619.out"], + ["affine_func$mul_d1__U622.in0","affine_func$coeff_1_U621.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U620.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U622.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -26845,10 +26845,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U605$lut$lut.bit.in.2","d_0_am__U605$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U605$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U605$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U605$lut$lut.bit.out"], + ["d_0_am__U628$lut$lut.bit.in.2","d_0_am__U628$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U628$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U628$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U628$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -26884,7 +26884,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U609":{ + "affine_controller__U631":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -26892,49 +26892,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U618":{ + "_U640":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6181":{ + "_U6401":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U619":{ + "_U641":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U616":{ + "affine_func$add_all__U638":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U617":{ + "affine_func$add_all__U639":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U611":{ + "affine_func$coeff_0_U633":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U613":{ + "affine_func$coeff_1_U635":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U615":{ + "affine_func$const_term_U637":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U612":{ + "affine_func$mul_d0__U634":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U614":{ + "affine_func$mul_d1__U636":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -26998,12 +26998,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U620$c0_lutcnst":{ + "d_0_am__U642$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U620$lut$lut":{ + "d_0_am__U642$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -27122,18 +27122,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U618.out"], - ["d_1_inc.in1","_U6181.out"], - ["cmp_time.in1","_U619.out"], - ["affine_func$mul_d0__U612.out","affine_func$add_all__U616.in0"], - ["affine_func$mul_d1__U614.out","affine_func$add_all__U616.in1"], - ["affine_func$add_all__U617.in0","affine_func$add_all__U616.out"], - ["affine_func$const_term_U615.out","affine_func$add_all__U617.in1"], - ["time_diff.in0","affine_func$add_all__U617.out"], - ["affine_func$mul_d0__U612.in0","affine_func$coeff_0_U611.out"], - ["affine_func$mul_d1__U614.in0","affine_func$coeff_1_U613.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U612.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U614.in1"], + ["d_0_inc.in1","_U640.out"], + ["d_1_inc.in1","_U6401.out"], + ["cmp_time.in1","_U641.out"], + ["affine_func$mul_d0__U634.out","affine_func$add_all__U638.in0"], + ["affine_func$mul_d1__U636.out","affine_func$add_all__U638.in1"], + ["affine_func$add_all__U639.in0","affine_func$add_all__U638.out"], + ["affine_func$const_term_U637.out","affine_func$add_all__U639.in1"], + ["time_diff.in0","affine_func$add_all__U639.out"], + ["affine_func$mul_d0__U634.in0","affine_func$coeff_0_U633.out"], + ["affine_func$mul_d1__U636.in0","affine_func$coeff_1_U635.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U634.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U636.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -27156,10 +27156,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U620$lut$lut.bit.in.2","d_0_am__U620$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U620$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U620$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U620$lut$lut.bit.out"], + ["d_0_am__U642$lut$lut.bit.in.2","d_0_am__U642$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U642$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U642$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U642$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -27195,7 +27195,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U61":{ + "affine_controller__U645":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -27203,49 +27203,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U70":{ + "_U654":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U701":{ + "_U6541":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U71":{ + "_U655":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U68":{ + "affine_func$add_all__U652":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U69":{ + "affine_func$add_all__U653":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U63":{ + "affine_func$coeff_0_U647":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U65":{ + "affine_func$coeff_1_U649":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U67":{ + "affine_func$const_term_U651":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U64":{ + "affine_func$mul_d0__U648":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U66":{ + "affine_func$mul_d1__U650":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -27309,12 +27309,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U72$c0_lutcnst":{ + "d_0_am__U656$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U72$lut$lut":{ + "d_0_am__U656$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -27433,18 +27433,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U70.out"], - ["d_1_inc.in1","_U701.out"], - ["cmp_time.in1","_U71.out"], - ["affine_func$mul_d0__U64.out","affine_func$add_all__U68.in0"], - ["affine_func$mul_d1__U66.out","affine_func$add_all__U68.in1"], - ["affine_func$add_all__U69.in0","affine_func$add_all__U68.out"], - ["affine_func$const_term_U67.out","affine_func$add_all__U69.in1"], - ["time_diff.in0","affine_func$add_all__U69.out"], - ["affine_func$mul_d0__U64.in0","affine_func$coeff_0_U63.out"], - ["affine_func$mul_d1__U66.in0","affine_func$coeff_1_U65.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U64.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U66.in1"], + ["d_0_inc.in1","_U654.out"], + ["d_1_inc.in1","_U6541.out"], + ["cmp_time.in1","_U655.out"], + ["affine_func$mul_d0__U648.out","affine_func$add_all__U652.in0"], + ["affine_func$mul_d1__U650.out","affine_func$add_all__U652.in1"], + ["affine_func$add_all__U653.in0","affine_func$add_all__U652.out"], + ["affine_func$const_term_U651.out","affine_func$add_all__U653.in1"], + ["time_diff.in0","affine_func$add_all__U653.out"], + ["affine_func$mul_d0__U648.in0","affine_func$coeff_0_U647.out"], + ["affine_func$mul_d1__U650.in0","affine_func$coeff_1_U649.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U648.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U650.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -27467,10 +27467,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U72$lut$lut.bit.in.2","d_0_am__U72$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U72$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U72$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U72$lut$lut.bit.out"], + ["d_0_am__U656$lut$lut.bit.in.2","d_0_am__U656$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U656$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U656$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U656$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -27506,7 +27506,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U624":{ + "affine_controller__U659":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -27514,49 +27514,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U633":{ + "_U668":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6331":{ + "_U6681":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U634":{ + "_U669":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U631":{ + "affine_func$add_all__U666":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U632":{ + "affine_func$add_all__U667":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U626":{ + "affine_func$coeff_0_U661":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U628":{ + "affine_func$coeff_1_U663":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U630":{ + "affine_func$const_term_U665":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U627":{ + "affine_func$mul_d0__U662":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U629":{ + "affine_func$mul_d1__U664":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -27620,12 +27620,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U635$c0_lutcnst":{ + "d_0_am__U670$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U635$lut$lut":{ + "d_0_am__U670$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -27744,18 +27744,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U633.out"], - ["d_1_inc.in1","_U6331.out"], - ["cmp_time.in1","_U634.out"], - ["affine_func$mul_d0__U627.out","affine_func$add_all__U631.in0"], - ["affine_func$mul_d1__U629.out","affine_func$add_all__U631.in1"], - ["affine_func$add_all__U632.in0","affine_func$add_all__U631.out"], - ["affine_func$const_term_U630.out","affine_func$add_all__U632.in1"], - ["time_diff.in0","affine_func$add_all__U632.out"], - ["affine_func$mul_d0__U627.in0","affine_func$coeff_0_U626.out"], - ["affine_func$mul_d1__U629.in0","affine_func$coeff_1_U628.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U627.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U629.in1"], + ["d_0_inc.in1","_U668.out"], + ["d_1_inc.in1","_U6681.out"], + ["cmp_time.in1","_U669.out"], + ["affine_func$mul_d0__U662.out","affine_func$add_all__U666.in0"], + ["affine_func$mul_d1__U664.out","affine_func$add_all__U666.in1"], + ["affine_func$add_all__U667.in0","affine_func$add_all__U666.out"], + ["affine_func$const_term_U665.out","affine_func$add_all__U667.in1"], + ["time_diff.in0","affine_func$add_all__U667.out"], + ["affine_func$mul_d0__U662.in0","affine_func$coeff_0_U661.out"], + ["affine_func$mul_d1__U664.in0","affine_func$coeff_1_U663.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U662.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U664.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -27778,10 +27778,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U635$lut$lut.bit.in.2","d_0_am__U635$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U635$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U635$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U635$lut$lut.bit.out"], + ["d_0_am__U670$lut$lut.bit.in.2","d_0_am__U670$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U670$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U670$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U670$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -27817,7 +27817,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U639":{ + "affine_controller__U673":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -27825,49 +27825,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U648":{ + "_U682":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6481":{ + "_U6821":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U649":{ + "_U683":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U646":{ + "affine_func$add_all__U680":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U647":{ + "affine_func$add_all__U681":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U641":{ + "affine_func$coeff_0_U675":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U643":{ + "affine_func$coeff_1_U677":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U645":{ + "affine_func$const_term_U679":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U642":{ + "affine_func$mul_d0__U676":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U644":{ + "affine_func$mul_d1__U678":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -27931,12 +27931,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U650$c0_lutcnst":{ + "d_0_am__U684$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U650$lut$lut":{ + "d_0_am__U684$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -28055,18 +28055,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U648.out"], - ["d_1_inc.in1","_U6481.out"], - ["cmp_time.in1","_U649.out"], - ["affine_func$mul_d0__U642.out","affine_func$add_all__U646.in0"], - ["affine_func$mul_d1__U644.out","affine_func$add_all__U646.in1"], - ["affine_func$add_all__U647.in0","affine_func$add_all__U646.out"], - ["affine_func$const_term_U645.out","affine_func$add_all__U647.in1"], - ["time_diff.in0","affine_func$add_all__U647.out"], - ["affine_func$mul_d0__U642.in0","affine_func$coeff_0_U641.out"], - ["affine_func$mul_d1__U644.in0","affine_func$coeff_1_U643.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U642.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U644.in1"], + ["d_0_inc.in1","_U682.out"], + ["d_1_inc.in1","_U6821.out"], + ["cmp_time.in1","_U683.out"], + ["affine_func$mul_d0__U676.out","affine_func$add_all__U680.in0"], + ["affine_func$mul_d1__U678.out","affine_func$add_all__U680.in1"], + ["affine_func$add_all__U681.in0","affine_func$add_all__U680.out"], + ["affine_func$const_term_U679.out","affine_func$add_all__U681.in1"], + ["time_diff.in0","affine_func$add_all__U681.out"], + ["affine_func$mul_d0__U676.in0","affine_func$coeff_0_U675.out"], + ["affine_func$mul_d1__U678.in0","affine_func$coeff_1_U677.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U676.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U678.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -28089,10 +28089,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U650$lut$lut.bit.in.2","d_0_am__U650$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U650$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U650$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U650$lut$lut.bit.out"], + ["d_0_am__U684$lut$lut.bit.in.2","d_0_am__U684$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U684$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U684$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U684$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -28128,7 +28128,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U654":{ + "affine_controller__U687":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -28136,49 +28136,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U663":{ + "_U696":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6631":{ + "_U6961":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U664":{ + "_U697":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U661":{ + "affine_func$add_all__U694":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U662":{ + "affine_func$add_all__U695":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U656":{ + "affine_func$coeff_0_U689":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U658":{ + "affine_func$coeff_1_U691":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U660":{ + "affine_func$const_term_U693":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U657":{ + "affine_func$mul_d0__U690":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U659":{ + "affine_func$mul_d1__U692":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -28242,12 +28242,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U665$c0_lutcnst":{ + "d_0_am__U698$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U665$lut$lut":{ + "d_0_am__U698$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -28366,18 +28366,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U663.out"], - ["d_1_inc.in1","_U6631.out"], - ["cmp_time.in1","_U664.out"], - ["affine_func$mul_d0__U657.out","affine_func$add_all__U661.in0"], - ["affine_func$mul_d1__U659.out","affine_func$add_all__U661.in1"], - ["affine_func$add_all__U662.in0","affine_func$add_all__U661.out"], - ["affine_func$const_term_U660.out","affine_func$add_all__U662.in1"], - ["time_diff.in0","affine_func$add_all__U662.out"], - ["affine_func$mul_d0__U657.in0","affine_func$coeff_0_U656.out"], - ["affine_func$mul_d1__U659.in0","affine_func$coeff_1_U658.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U657.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U659.in1"], + ["d_0_inc.in1","_U696.out"], + ["d_1_inc.in1","_U6961.out"], + ["cmp_time.in1","_U697.out"], + ["affine_func$mul_d0__U690.out","affine_func$add_all__U694.in0"], + ["affine_func$mul_d1__U692.out","affine_func$add_all__U694.in1"], + ["affine_func$add_all__U695.in0","affine_func$add_all__U694.out"], + ["affine_func$const_term_U693.out","affine_func$add_all__U695.in1"], + ["time_diff.in0","affine_func$add_all__U695.out"], + ["affine_func$mul_d0__U690.in0","affine_func$coeff_0_U689.out"], + ["affine_func$mul_d1__U692.in0","affine_func$coeff_1_U691.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U690.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U692.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -28400,10 +28400,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U665$lut$lut.bit.in.2","d_0_am__U665$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U665$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U665$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U665$lut$lut.bit.out"], + ["d_0_am__U698$lut$lut.bit.in.2","d_0_am__U698$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U698$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U698$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U698$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -28439,7 +28439,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U669":{ + "affine_controller__U701":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -28447,49 +28447,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U678":{ + "_U710":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6781":{ + "_U7101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U679":{ + "_U711":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U676":{ + "affine_func$add_all__U708":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U677":{ + "affine_func$add_all__U709":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U671":{ + "affine_func$coeff_0_U703":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U673":{ + "affine_func$coeff_1_U705":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U675":{ + "affine_func$const_term_U707":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U672":{ + "affine_func$mul_d0__U704":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U674":{ + "affine_func$mul_d1__U706":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -28553,12 +28553,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U680$c0_lutcnst":{ + "d_0_am__U712$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U680$lut$lut":{ + "d_0_am__U712$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -28677,18 +28677,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U678.out"], - ["d_1_inc.in1","_U6781.out"], - ["cmp_time.in1","_U679.out"], - ["affine_func$mul_d0__U672.out","affine_func$add_all__U676.in0"], - ["affine_func$mul_d1__U674.out","affine_func$add_all__U676.in1"], - ["affine_func$add_all__U677.in0","affine_func$add_all__U676.out"], - ["affine_func$const_term_U675.out","affine_func$add_all__U677.in1"], - ["time_diff.in0","affine_func$add_all__U677.out"], - ["affine_func$mul_d0__U672.in0","affine_func$coeff_0_U671.out"], - ["affine_func$mul_d1__U674.in0","affine_func$coeff_1_U673.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U672.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U674.in1"], + ["d_0_inc.in1","_U710.out"], + ["d_1_inc.in1","_U7101.out"], + ["cmp_time.in1","_U711.out"], + ["affine_func$mul_d0__U704.out","affine_func$add_all__U708.in0"], + ["affine_func$mul_d1__U706.out","affine_func$add_all__U708.in1"], + ["affine_func$add_all__U709.in0","affine_func$add_all__U708.out"], + ["affine_func$const_term_U707.out","affine_func$add_all__U709.in1"], + ["time_diff.in0","affine_func$add_all__U709.out"], + ["affine_func$mul_d0__U704.in0","affine_func$coeff_0_U703.out"], + ["affine_func$mul_d1__U706.in0","affine_func$coeff_1_U705.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U704.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U706.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -28711,10 +28711,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U680$lut$lut.bit.in.2","d_0_am__U680$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U680$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U680$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U680$lut$lut.bit.out"], + ["d_0_am__U712$lut$lut.bit.in.2","d_0_am__U712$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U712$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U712$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U712$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -28750,7 +28750,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U684":{ + "affine_controller__U71":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -28758,49 +28758,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U693":{ + "_U80":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6931":{ + "_U801":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U694":{ + "_U81":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U691":{ + "affine_func$add_all__U78":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U692":{ + "affine_func$add_all__U79":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U686":{ + "affine_func$coeff_0_U73":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U688":{ + "affine_func$coeff_1_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U690":{ + "affine_func$const_term_U77":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U687":{ + "affine_func$mul_d0__U74":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U689":{ + "affine_func$mul_d1__U76":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -28864,12 +28864,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U695$c0_lutcnst":{ + "d_0_am__U82$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U695$lut$lut":{ + "d_0_am__U82$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -28988,18 +28988,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U693.out"], - ["d_1_inc.in1","_U6931.out"], - ["cmp_time.in1","_U694.out"], - ["affine_func$mul_d0__U687.out","affine_func$add_all__U691.in0"], - ["affine_func$mul_d1__U689.out","affine_func$add_all__U691.in1"], - ["affine_func$add_all__U692.in0","affine_func$add_all__U691.out"], - ["affine_func$const_term_U690.out","affine_func$add_all__U692.in1"], - ["time_diff.in0","affine_func$add_all__U692.out"], - ["affine_func$mul_d0__U687.in0","affine_func$coeff_0_U686.out"], - ["affine_func$mul_d1__U689.in0","affine_func$coeff_1_U688.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U687.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U689.in1"], + ["d_0_inc.in1","_U80.out"], + ["d_1_inc.in1","_U801.out"], + ["cmp_time.in1","_U81.out"], + ["affine_func$mul_d0__U74.out","affine_func$add_all__U78.in0"], + ["affine_func$mul_d1__U76.out","affine_func$add_all__U78.in1"], + ["affine_func$add_all__U79.in0","affine_func$add_all__U78.out"], + ["affine_func$const_term_U77.out","affine_func$add_all__U79.in1"], + ["time_diff.in0","affine_func$add_all__U79.out"], + ["affine_func$mul_d0__U74.in0","affine_func$coeff_0_U73.out"], + ["affine_func$mul_d1__U76.in0","affine_func$coeff_1_U75.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U74.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U76.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -29022,10 +29022,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U695$lut$lut.bit.in.2","d_0_am__U695$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U695$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U695$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U695$lut$lut.bit.out"], + ["d_0_am__U82$lut$lut.bit.in.2","d_0_am__U82$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U82$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U82$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U82$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -29061,7 +29061,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U699":{ + "affine_controller__U715":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -29069,49 +29069,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U708":{ + "_U724":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7081":{ + "_U7241":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U709":{ + "_U725":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U706":{ + "affine_func$add_all__U722":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U707":{ + "affine_func$add_all__U723":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U701":{ + "affine_func$coeff_0_U717":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U703":{ + "affine_func$coeff_1_U719":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U705":{ + "affine_func$const_term_U721":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U702":{ + "affine_func$mul_d0__U718":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U704":{ + "affine_func$mul_d1__U720":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -29175,12 +29175,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U710$c0_lutcnst":{ + "d_0_am__U726$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U710$lut$lut":{ + "d_0_am__U726$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -29299,18 +29299,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U708.out"], - ["d_1_inc.in1","_U7081.out"], - ["cmp_time.in1","_U709.out"], - ["affine_func$mul_d0__U702.out","affine_func$add_all__U706.in0"], - ["affine_func$mul_d1__U704.out","affine_func$add_all__U706.in1"], - ["affine_func$add_all__U707.in0","affine_func$add_all__U706.out"], - ["affine_func$const_term_U705.out","affine_func$add_all__U707.in1"], - ["time_diff.in0","affine_func$add_all__U707.out"], - ["affine_func$mul_d0__U702.in0","affine_func$coeff_0_U701.out"], - ["affine_func$mul_d1__U704.in0","affine_func$coeff_1_U703.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U702.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U704.in1"], + ["d_0_inc.in1","_U724.out"], + ["d_1_inc.in1","_U7241.out"], + ["cmp_time.in1","_U725.out"], + ["affine_func$mul_d0__U718.out","affine_func$add_all__U722.in0"], + ["affine_func$mul_d1__U720.out","affine_func$add_all__U722.in1"], + ["affine_func$add_all__U723.in0","affine_func$add_all__U722.out"], + ["affine_func$const_term_U721.out","affine_func$add_all__U723.in1"], + ["time_diff.in0","affine_func$add_all__U723.out"], + ["affine_func$mul_d0__U718.in0","affine_func$coeff_0_U717.out"], + ["affine_func$mul_d1__U720.in0","affine_func$coeff_1_U719.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U718.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U720.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -29333,10 +29333,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U710$lut$lut.bit.in.2","d_0_am__U710$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U710$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U710$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U710$lut$lut.bit.out"], + ["d_0_am__U726$lut$lut.bit.in.2","d_0_am__U726$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U726$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U726$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U726$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -29372,7 +29372,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U714":{ + "affine_controller__U729":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -29380,49 +29380,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U723":{ + "_U738":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7231":{ + "_U7381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U724":{ + "_U739":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U721":{ + "affine_func$add_all__U736":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U722":{ + "affine_func$add_all__U737":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U716":{ + "affine_func$coeff_0_U731":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U718":{ + "affine_func$coeff_1_U733":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U720":{ + "affine_func$const_term_U735":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U717":{ + "affine_func$mul_d0__U732":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U719":{ + "affine_func$mul_d1__U734":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -29486,12 +29486,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U725$c0_lutcnst":{ + "d_0_am__U740$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U725$lut$lut":{ + "d_0_am__U740$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -29610,18 +29610,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U723.out"], - ["d_1_inc.in1","_U7231.out"], - ["cmp_time.in1","_U724.out"], - ["affine_func$mul_d0__U717.out","affine_func$add_all__U721.in0"], - ["affine_func$mul_d1__U719.out","affine_func$add_all__U721.in1"], - ["affine_func$add_all__U722.in0","affine_func$add_all__U721.out"], - ["affine_func$const_term_U720.out","affine_func$add_all__U722.in1"], - ["time_diff.in0","affine_func$add_all__U722.out"], - ["affine_func$mul_d0__U717.in0","affine_func$coeff_0_U716.out"], - ["affine_func$mul_d1__U719.in0","affine_func$coeff_1_U718.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U717.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U719.in1"], + ["d_0_inc.in1","_U738.out"], + ["d_1_inc.in1","_U7381.out"], + ["cmp_time.in1","_U739.out"], + ["affine_func$mul_d0__U732.out","affine_func$add_all__U736.in0"], + ["affine_func$mul_d1__U734.out","affine_func$add_all__U736.in1"], + ["affine_func$add_all__U737.in0","affine_func$add_all__U736.out"], + ["affine_func$const_term_U735.out","affine_func$add_all__U737.in1"], + ["time_diff.in0","affine_func$add_all__U737.out"], + ["affine_func$mul_d0__U732.in0","affine_func$coeff_0_U731.out"], + ["affine_func$mul_d1__U734.in0","affine_func$coeff_1_U733.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U732.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U734.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -29644,10 +29644,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U725$lut$lut.bit.in.2","d_0_am__U725$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U725$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U725$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U725$lut$lut.bit.out"], + ["d_0_am__U740$lut$lut.bit.in.2","d_0_am__U740$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U740$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U740$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U740$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -29683,7 +29683,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U729":{ + "affine_controller__U743":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -29691,49 +29691,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U738":{ + "_U752":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7381":{ + "_U7521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U739":{ + "_U753":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U736":{ + "affine_func$add_all__U750":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U737":{ + "affine_func$add_all__U751":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U731":{ + "affine_func$coeff_0_U745":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U733":{ + "affine_func$coeff_1_U747":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U735":{ + "affine_func$const_term_U749":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U732":{ + "affine_func$mul_d0__U746":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U734":{ + "affine_func$mul_d1__U748":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -29797,12 +29797,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U740$c0_lutcnst":{ + "d_0_am__U754$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U740$lut$lut":{ + "d_0_am__U754$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -29921,18 +29921,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U738.out"], - ["d_1_inc.in1","_U7381.out"], - ["cmp_time.in1","_U739.out"], - ["affine_func$mul_d0__U732.out","affine_func$add_all__U736.in0"], - ["affine_func$mul_d1__U734.out","affine_func$add_all__U736.in1"], - ["affine_func$add_all__U737.in0","affine_func$add_all__U736.out"], - ["affine_func$const_term_U735.out","affine_func$add_all__U737.in1"], - ["time_diff.in0","affine_func$add_all__U737.out"], - ["affine_func$mul_d0__U732.in0","affine_func$coeff_0_U731.out"], - ["affine_func$mul_d1__U734.in0","affine_func$coeff_1_U733.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U732.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U734.in1"], + ["d_0_inc.in1","_U752.out"], + ["d_1_inc.in1","_U7521.out"], + ["cmp_time.in1","_U753.out"], + ["affine_func$mul_d0__U746.out","affine_func$add_all__U750.in0"], + ["affine_func$mul_d1__U748.out","affine_func$add_all__U750.in1"], + ["affine_func$add_all__U751.in0","affine_func$add_all__U750.out"], + ["affine_func$const_term_U749.out","affine_func$add_all__U751.in1"], + ["time_diff.in0","affine_func$add_all__U751.out"], + ["affine_func$mul_d0__U746.in0","affine_func$coeff_0_U745.out"], + ["affine_func$mul_d1__U748.in0","affine_func$coeff_1_U747.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U746.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U748.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -29955,10 +29955,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U740$lut$lut.bit.in.2","d_0_am__U740$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U740$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U740$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U740$lut$lut.bit.out"], + ["d_0_am__U754$lut$lut.bit.in.2","d_0_am__U754$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U754$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U754$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U754$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -29994,7 +29994,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U744":{ + "affine_controller__U757":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -30002,49 +30002,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U753":{ + "_U766":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7531":{ + "_U7661":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U754":{ + "_U767":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U751":{ + "affine_func$add_all__U764":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U752":{ + "affine_func$add_all__U765":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U746":{ + "affine_func$coeff_0_U759":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U748":{ + "affine_func$coeff_1_U761":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U750":{ + "affine_func$const_term_U763":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U747":{ + "affine_func$mul_d0__U760":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U749":{ + "affine_func$mul_d1__U762":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -30108,12 +30108,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U755$c0_lutcnst":{ + "d_0_am__U768$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U755$lut$lut":{ + "d_0_am__U768$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -30232,18 +30232,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U753.out"], - ["d_1_inc.in1","_U7531.out"], - ["cmp_time.in1","_U754.out"], - ["affine_func$mul_d0__U747.out","affine_func$add_all__U751.in0"], - ["affine_func$mul_d1__U749.out","affine_func$add_all__U751.in1"], - ["affine_func$add_all__U752.in0","affine_func$add_all__U751.out"], - ["affine_func$const_term_U750.out","affine_func$add_all__U752.in1"], - ["time_diff.in0","affine_func$add_all__U752.out"], - ["affine_func$mul_d0__U747.in0","affine_func$coeff_0_U746.out"], - ["affine_func$mul_d1__U749.in0","affine_func$coeff_1_U748.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U747.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U749.in1"], + ["d_0_inc.in1","_U766.out"], + ["d_1_inc.in1","_U7661.out"], + ["cmp_time.in1","_U767.out"], + ["affine_func$mul_d0__U760.out","affine_func$add_all__U764.in0"], + ["affine_func$mul_d1__U762.out","affine_func$add_all__U764.in1"], + ["affine_func$add_all__U765.in0","affine_func$add_all__U764.out"], + ["affine_func$const_term_U763.out","affine_func$add_all__U765.in1"], + ["time_diff.in0","affine_func$add_all__U765.out"], + ["affine_func$mul_d0__U760.in0","affine_func$coeff_0_U759.out"], + ["affine_func$mul_d1__U762.in0","affine_func$coeff_1_U761.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U760.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U762.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -30266,10 +30266,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U755$lut$lut.bit.in.2","d_0_am__U755$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U755$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U755$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U755$lut$lut.bit.out"], + ["d_0_am__U768$lut$lut.bit.in.2","d_0_am__U768$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U768$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U768$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U768$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -30305,7 +30305,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U759":{ + "affine_controller__U771":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -30313,49 +30313,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U768":{ + "_U780":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7681":{ + "_U7801":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U769":{ + "_U781":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U766":{ + "affine_func$add_all__U778":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U767":{ + "affine_func$add_all__U779":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U761":{ + "affine_func$coeff_0_U773":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U763":{ + "affine_func$coeff_1_U775":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U765":{ + "affine_func$const_term_U777":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U762":{ + "affine_func$mul_d0__U774":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U764":{ + "affine_func$mul_d1__U776":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -30419,12 +30419,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U770$c0_lutcnst":{ + "d_0_am__U782$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U770$lut$lut":{ + "d_0_am__U782$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -30543,18 +30543,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U768.out"], - ["d_1_inc.in1","_U7681.out"], - ["cmp_time.in1","_U769.out"], - ["affine_func$mul_d0__U762.out","affine_func$add_all__U766.in0"], - ["affine_func$mul_d1__U764.out","affine_func$add_all__U766.in1"], - ["affine_func$add_all__U767.in0","affine_func$add_all__U766.out"], - ["affine_func$const_term_U765.out","affine_func$add_all__U767.in1"], - ["time_diff.in0","affine_func$add_all__U767.out"], - ["affine_func$mul_d0__U762.in0","affine_func$coeff_0_U761.out"], - ["affine_func$mul_d1__U764.in0","affine_func$coeff_1_U763.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U762.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U764.in1"], + ["d_0_inc.in1","_U780.out"], + ["d_1_inc.in1","_U7801.out"], + ["cmp_time.in1","_U781.out"], + ["affine_func$mul_d0__U774.out","affine_func$add_all__U778.in0"], + ["affine_func$mul_d1__U776.out","affine_func$add_all__U778.in1"], + ["affine_func$add_all__U779.in0","affine_func$add_all__U778.out"], + ["affine_func$const_term_U777.out","affine_func$add_all__U779.in1"], + ["time_diff.in0","affine_func$add_all__U779.out"], + ["affine_func$mul_d0__U774.in0","affine_func$coeff_0_U773.out"], + ["affine_func$mul_d1__U776.in0","affine_func$coeff_1_U775.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U774.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U776.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -30577,10 +30577,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U770$lut$lut.bit.in.2","d_0_am__U770$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U770$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U770$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U770$lut$lut.bit.out"], + ["d_0_am__U782$lut$lut.bit.in.2","d_0_am__U782$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U782$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U782$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U782$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -30616,7 +30616,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U76":{ + "affine_controller__U785":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -30624,49 +30624,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U85":{ + "_U794":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U851":{ + "_U7941":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U86":{ + "_U795":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U83":{ + "affine_func$add_all__U792":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U84":{ + "affine_func$add_all__U793":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U78":{ + "affine_func$coeff_0_U787":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U80":{ + "affine_func$coeff_1_U789":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U82":{ + "affine_func$const_term_U791":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U79":{ + "affine_func$mul_d0__U788":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U81":{ + "affine_func$mul_d1__U790":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -30730,12 +30730,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U87$c0_lutcnst":{ + "d_0_am__U796$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U87$lut$lut":{ + "d_0_am__U796$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -30854,18 +30854,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U85.out"], - ["d_1_inc.in1","_U851.out"], - ["cmp_time.in1","_U86.out"], - ["affine_func$mul_d0__U79.out","affine_func$add_all__U83.in0"], - ["affine_func$mul_d1__U81.out","affine_func$add_all__U83.in1"], - ["affine_func$add_all__U84.in0","affine_func$add_all__U83.out"], - ["affine_func$const_term_U82.out","affine_func$add_all__U84.in1"], - ["time_diff.in0","affine_func$add_all__U84.out"], - ["affine_func$mul_d0__U79.in0","affine_func$coeff_0_U78.out"], - ["affine_func$mul_d1__U81.in0","affine_func$coeff_1_U80.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U79.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U81.in1"], + ["d_0_inc.in1","_U794.out"], + ["d_1_inc.in1","_U7941.out"], + ["cmp_time.in1","_U795.out"], + ["affine_func$mul_d0__U788.out","affine_func$add_all__U792.in0"], + ["affine_func$mul_d1__U790.out","affine_func$add_all__U792.in1"], + ["affine_func$add_all__U793.in0","affine_func$add_all__U792.out"], + ["affine_func$const_term_U791.out","affine_func$add_all__U793.in1"], + ["time_diff.in0","affine_func$add_all__U793.out"], + ["affine_func$mul_d0__U788.in0","affine_func$coeff_0_U787.out"], + ["affine_func$mul_d1__U790.in0","affine_func$coeff_1_U789.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U788.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U790.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -30888,10 +30888,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U87$lut$lut.bit.in.2","d_0_am__U87$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U87$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U87$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U87$lut$lut.bit.out"], + ["d_0_am__U796$lut$lut.bit.in.2","d_0_am__U796$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U796$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U796$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U796$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -30927,7 +30927,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U774":{ + "affine_controller__U799":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -30935,49 +30935,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U783":{ + "_U808":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7831":{ + "_U8081":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U784":{ + "_U809":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U781":{ + "affine_func$add_all__U806":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U782":{ + "affine_func$add_all__U807":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U776":{ + "affine_func$coeff_0_U801":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U778":{ + "affine_func$coeff_1_U803":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U780":{ + "affine_func$const_term_U805":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U777":{ + "affine_func$mul_d0__U802":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U779":{ + "affine_func$mul_d1__U804":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -31041,12 +31041,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U785$c0_lutcnst":{ + "d_0_am__U810$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U785$lut$lut":{ + "d_0_am__U810$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -31165,18 +31165,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U783.out"], - ["d_1_inc.in1","_U7831.out"], - ["cmp_time.in1","_U784.out"], - ["affine_func$mul_d0__U777.out","affine_func$add_all__U781.in0"], - ["affine_func$mul_d1__U779.out","affine_func$add_all__U781.in1"], - ["affine_func$add_all__U782.in0","affine_func$add_all__U781.out"], - ["affine_func$const_term_U780.out","affine_func$add_all__U782.in1"], - ["time_diff.in0","affine_func$add_all__U782.out"], - ["affine_func$mul_d0__U777.in0","affine_func$coeff_0_U776.out"], - ["affine_func$mul_d1__U779.in0","affine_func$coeff_1_U778.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U777.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U779.in1"], + ["d_0_inc.in1","_U808.out"], + ["d_1_inc.in1","_U8081.out"], + ["cmp_time.in1","_U809.out"], + ["affine_func$mul_d0__U802.out","affine_func$add_all__U806.in0"], + ["affine_func$mul_d1__U804.out","affine_func$add_all__U806.in1"], + ["affine_func$add_all__U807.in0","affine_func$add_all__U806.out"], + ["affine_func$const_term_U805.out","affine_func$add_all__U807.in1"], + ["time_diff.in0","affine_func$add_all__U807.out"], + ["affine_func$mul_d0__U802.in0","affine_func$coeff_0_U801.out"], + ["affine_func$mul_d1__U804.in0","affine_func$coeff_1_U803.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U802.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U804.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -31199,10 +31199,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U785$lut$lut.bit.in.2","d_0_am__U785$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U785$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U785$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U785$lut$lut.bit.out"], + ["d_0_am__U810$lut$lut.bit.in.2","d_0_am__U810$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U810$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U810$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U810$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -31238,7 +31238,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U789":{ + "affine_controller__U813":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -31246,49 +31246,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U798":{ + "_U822":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U7981":{ + "_U8221":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U799":{ + "_U823":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U796":{ + "affine_func$add_all__U820":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U797":{ + "affine_func$add_all__U821":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U791":{ + "affine_func$coeff_0_U815":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U793":{ + "affine_func$coeff_1_U817":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U795":{ + "affine_func$const_term_U819":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U792":{ + "affine_func$mul_d0__U816":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U794":{ + "affine_func$mul_d1__U818":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -31352,12 +31352,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U800$c0_lutcnst":{ + "d_0_am__U824$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U800$lut$lut":{ + "d_0_am__U824$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -31476,18 +31476,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U798.out"], - ["d_1_inc.in1","_U7981.out"], - ["cmp_time.in1","_U799.out"], - ["affine_func$mul_d0__U792.out","affine_func$add_all__U796.in0"], - ["affine_func$mul_d1__U794.out","affine_func$add_all__U796.in1"], - ["affine_func$add_all__U797.in0","affine_func$add_all__U796.out"], - ["affine_func$const_term_U795.out","affine_func$add_all__U797.in1"], - ["time_diff.in0","affine_func$add_all__U797.out"], - ["affine_func$mul_d0__U792.in0","affine_func$coeff_0_U791.out"], - ["affine_func$mul_d1__U794.in0","affine_func$coeff_1_U793.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U792.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U794.in1"], + ["d_0_inc.in1","_U822.out"], + ["d_1_inc.in1","_U8221.out"], + ["cmp_time.in1","_U823.out"], + ["affine_func$mul_d0__U816.out","affine_func$add_all__U820.in0"], + ["affine_func$mul_d1__U818.out","affine_func$add_all__U820.in1"], + ["affine_func$add_all__U821.in0","affine_func$add_all__U820.out"], + ["affine_func$const_term_U819.out","affine_func$add_all__U821.in1"], + ["time_diff.in0","affine_func$add_all__U821.out"], + ["affine_func$mul_d0__U816.in0","affine_func$coeff_0_U815.out"], + ["affine_func$mul_d1__U818.in0","affine_func$coeff_1_U817.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U816.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U818.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -31510,10 +31510,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U800$lut$lut.bit.in.2","d_0_am__U800$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U800$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U800$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U800$lut$lut.bit.out"], + ["d_0_am__U824$lut$lut.bit.in.2","d_0_am__U824$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U824$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U824$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U824$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -31549,7 +31549,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U804":{ + "affine_controller__U827":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -31557,49 +31557,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U813":{ + "_U836":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U8131":{ + "_U8361":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U814":{ + "_U837":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U811":{ + "affine_func$add_all__U834":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U812":{ + "affine_func$add_all__U835":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U806":{ + "affine_func$coeff_0_U829":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U808":{ + "affine_func$coeff_1_U831":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U810":{ + "affine_func$const_term_U833":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U807":{ + "affine_func$mul_d0__U830":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U809":{ + "affine_func$mul_d1__U832":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -31663,12 +31663,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U815$c0_lutcnst":{ + "d_0_am__U838$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U815$lut$lut":{ + "d_0_am__U838$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -31787,18 +31787,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U813.out"], - ["d_1_inc.in1","_U8131.out"], - ["cmp_time.in1","_U814.out"], - ["affine_func$mul_d0__U807.out","affine_func$add_all__U811.in0"], - ["affine_func$mul_d1__U809.out","affine_func$add_all__U811.in1"], - ["affine_func$add_all__U812.in0","affine_func$add_all__U811.out"], - ["affine_func$const_term_U810.out","affine_func$add_all__U812.in1"], - ["time_diff.in0","affine_func$add_all__U812.out"], - ["affine_func$mul_d0__U807.in0","affine_func$coeff_0_U806.out"], - ["affine_func$mul_d1__U809.in0","affine_func$coeff_1_U808.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U807.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U809.in1"], + ["d_0_inc.in1","_U836.out"], + ["d_1_inc.in1","_U8361.out"], + ["cmp_time.in1","_U837.out"], + ["affine_func$mul_d0__U830.out","affine_func$add_all__U834.in0"], + ["affine_func$mul_d1__U832.out","affine_func$add_all__U834.in1"], + ["affine_func$add_all__U835.in0","affine_func$add_all__U834.out"], + ["affine_func$const_term_U833.out","affine_func$add_all__U835.in1"], + ["time_diff.in0","affine_func$add_all__U835.out"], + ["affine_func$mul_d0__U830.in0","affine_func$coeff_0_U829.out"], + ["affine_func$mul_d1__U832.in0","affine_func$coeff_1_U831.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U830.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U832.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -31821,10 +31821,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U815$lut$lut.bit.in.2","d_0_am__U815$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U815$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U815$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U815$lut$lut.bit.out"], + ["d_0_am__U838$lut$lut.bit.in.2","d_0_am__U838$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U838$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U838$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U838$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -31860,7 +31860,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U819":{ + "affine_controller__U841":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -31868,49 +31868,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U828":{ + "_U850":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U8281":{ + "_U8501":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U829":{ + "_U851":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U826":{ + "affine_func$add_all__U848":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U827":{ + "affine_func$add_all__U849":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U821":{ + "affine_func$coeff_0_U843":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U823":{ + "affine_func$coeff_1_U845":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U825":{ + "affine_func$const_term_U847":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U822":{ + "affine_func$mul_d0__U844":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U824":{ + "affine_func$mul_d1__U846":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -31974,12 +31974,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U830$c0_lutcnst":{ + "d_0_am__U852$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U830$lut$lut":{ + "d_0_am__U852$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -32098,18 +32098,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U828.out"], - ["d_1_inc.in1","_U8281.out"], - ["cmp_time.in1","_U829.out"], - ["affine_func$mul_d0__U822.out","affine_func$add_all__U826.in0"], - ["affine_func$mul_d1__U824.out","affine_func$add_all__U826.in1"], - ["affine_func$add_all__U827.in0","affine_func$add_all__U826.out"], - ["affine_func$const_term_U825.out","affine_func$add_all__U827.in1"], - ["time_diff.in0","affine_func$add_all__U827.out"], - ["affine_func$mul_d0__U822.in0","affine_func$coeff_0_U821.out"], - ["affine_func$mul_d1__U824.in0","affine_func$coeff_1_U823.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U822.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U824.in1"], + ["d_0_inc.in1","_U850.out"], + ["d_1_inc.in1","_U8501.out"], + ["cmp_time.in1","_U851.out"], + ["affine_func$mul_d0__U844.out","affine_func$add_all__U848.in0"], + ["affine_func$mul_d1__U846.out","affine_func$add_all__U848.in1"], + ["affine_func$add_all__U849.in0","affine_func$add_all__U848.out"], + ["affine_func$const_term_U847.out","affine_func$add_all__U849.in1"], + ["time_diff.in0","affine_func$add_all__U849.out"], + ["affine_func$mul_d0__U844.in0","affine_func$coeff_0_U843.out"], + ["affine_func$mul_d1__U846.in0","affine_func$coeff_1_U845.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U844.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U846.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -32132,10 +32132,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U830$lut$lut.bit.in.2","d_0_am__U830$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U830$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U830$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U830$lut$lut.bit.out"], + ["d_0_am__U852$lut$lut.bit.in.2","d_0_am__U852$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U852$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U852$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U852$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -32171,7 +32171,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U834":{ + "affine_controller__U85":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -32179,49 +32179,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U843":{ + "_U94":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U8431":{ + "_U941":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U844":{ + "_U95":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U841":{ + "affine_func$add_all__U92":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U842":{ + "affine_func$add_all__U93":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U836":{ + "affine_func$coeff_0_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U838":{ + "affine_func$coeff_1_U89":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U840":{ + "affine_func$const_term_U91":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U837":{ + "affine_func$mul_d0__U88":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U839":{ + "affine_func$mul_d1__U90":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -32285,12 +32285,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U845$c0_lutcnst":{ + "d_0_am__U96$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U845$lut$lut":{ + "d_0_am__U96$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -32409,18 +32409,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U843.out"], - ["d_1_inc.in1","_U8431.out"], - ["cmp_time.in1","_U844.out"], - ["affine_func$mul_d0__U837.out","affine_func$add_all__U841.in0"], - ["affine_func$mul_d1__U839.out","affine_func$add_all__U841.in1"], - ["affine_func$add_all__U842.in0","affine_func$add_all__U841.out"], - ["affine_func$const_term_U840.out","affine_func$add_all__U842.in1"], - ["time_diff.in0","affine_func$add_all__U842.out"], - ["affine_func$mul_d0__U837.in0","affine_func$coeff_0_U836.out"], - ["affine_func$mul_d1__U839.in0","affine_func$coeff_1_U838.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U837.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U839.in1"], + ["d_0_inc.in1","_U94.out"], + ["d_1_inc.in1","_U941.out"], + ["cmp_time.in1","_U95.out"], + ["affine_func$mul_d0__U88.out","affine_func$add_all__U92.in0"], + ["affine_func$mul_d1__U90.out","affine_func$add_all__U92.in1"], + ["affine_func$add_all__U93.in0","affine_func$add_all__U92.out"], + ["affine_func$const_term_U91.out","affine_func$add_all__U93.in1"], + ["time_diff.in0","affine_func$add_all__U93.out"], + ["affine_func$mul_d0__U88.in0","affine_func$coeff_0_U87.out"], + ["affine_func$mul_d1__U90.in0","affine_func$coeff_1_U89.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U88.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U90.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -32443,10 +32443,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U845$lut$lut.bit.in.2","d_0_am__U845$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U845$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U845$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U845$lut$lut.bit.out"], + ["d_0_am__U96$lut$lut.bit.in.2","d_0_am__U96$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U96$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U96$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U96$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -32482,7 +32482,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U849":{ + "affine_controller__U855":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -32490,49 +32490,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U858":{ + "_U864":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U8581":{ + "_U8641":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U859":{ + "_U865":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U856":{ + "affine_func$add_all__U862":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U857":{ + "affine_func$add_all__U863":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U851":{ + "affine_func$coeff_0_U857":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U853":{ + "affine_func$coeff_1_U859":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U855":{ + "affine_func$const_term_U861":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U852":{ + "affine_func$mul_d0__U858":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U854":{ + "affine_func$mul_d1__U860":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -32596,12 +32596,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U860$c0_lutcnst":{ + "d_0_am__U866$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U860$lut$lut":{ + "d_0_am__U866$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -32720,18 +32720,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U858.out"], - ["d_1_inc.in1","_U8581.out"], - ["cmp_time.in1","_U859.out"], - ["affine_func$mul_d0__U852.out","affine_func$add_all__U856.in0"], - ["affine_func$mul_d1__U854.out","affine_func$add_all__U856.in1"], - ["affine_func$add_all__U857.in0","affine_func$add_all__U856.out"], - ["affine_func$const_term_U855.out","affine_func$add_all__U857.in1"], - ["time_diff.in0","affine_func$add_all__U857.out"], - ["affine_func$mul_d0__U852.in0","affine_func$coeff_0_U851.out"], - ["affine_func$mul_d1__U854.in0","affine_func$coeff_1_U853.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U852.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U854.in1"], + ["d_0_inc.in1","_U864.out"], + ["d_1_inc.in1","_U8641.out"], + ["cmp_time.in1","_U865.out"], + ["affine_func$mul_d0__U858.out","affine_func$add_all__U862.in0"], + ["affine_func$mul_d1__U860.out","affine_func$add_all__U862.in1"], + ["affine_func$add_all__U863.in0","affine_func$add_all__U862.out"], + ["affine_func$const_term_U861.out","affine_func$add_all__U863.in1"], + ["time_diff.in0","affine_func$add_all__U863.out"], + ["affine_func$mul_d0__U858.in0","affine_func$coeff_0_U857.out"], + ["affine_func$mul_d1__U860.in0","affine_func$coeff_1_U859.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U858.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U860.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -32754,10 +32754,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U860$lut$lut.bit.in.2","d_0_am__U860$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U860$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U860$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U860$lut$lut.bit.out"], + ["d_0_am__U866$lut$lut.bit.in.2","d_0_am__U866$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U866$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U866$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U866$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -32793,7 +32793,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U864":{ + "affine_controller__U869":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -32801,49 +32801,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U873":{ + "_U878":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U8731":{ + "_U8781":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U874":{ + "_U879":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U871":{ + "affine_func$add_all__U876":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U872":{ + "affine_func$add_all__U877":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U866":{ + "affine_func$coeff_0_U871":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U868":{ + "affine_func$coeff_1_U873":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U870":{ + "affine_func$const_term_U875":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U867":{ + "affine_func$mul_d0__U872":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U869":{ + "affine_func$mul_d1__U874":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -32907,12 +32907,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U875$c0_lutcnst":{ + "d_0_am__U880$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U875$lut$lut":{ + "d_0_am__U880$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -33031,18 +33031,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U873.out"], - ["d_1_inc.in1","_U8731.out"], - ["cmp_time.in1","_U874.out"], - ["affine_func$mul_d0__U867.out","affine_func$add_all__U871.in0"], - ["affine_func$mul_d1__U869.out","affine_func$add_all__U871.in1"], - ["affine_func$add_all__U872.in0","affine_func$add_all__U871.out"], - ["affine_func$const_term_U870.out","affine_func$add_all__U872.in1"], - ["time_diff.in0","affine_func$add_all__U872.out"], - ["affine_func$mul_d0__U867.in0","affine_func$coeff_0_U866.out"], - ["affine_func$mul_d1__U869.in0","affine_func$coeff_1_U868.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U867.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U869.in1"], + ["d_0_inc.in1","_U878.out"], + ["d_1_inc.in1","_U8781.out"], + ["cmp_time.in1","_U879.out"], + ["affine_func$mul_d0__U872.out","affine_func$add_all__U876.in0"], + ["affine_func$mul_d1__U874.out","affine_func$add_all__U876.in1"], + ["affine_func$add_all__U877.in0","affine_func$add_all__U876.out"], + ["affine_func$const_term_U875.out","affine_func$add_all__U877.in1"], + ["time_diff.in0","affine_func$add_all__U877.out"], + ["affine_func$mul_d0__U872.in0","affine_func$coeff_0_U871.out"], + ["affine_func$mul_d1__U874.in0","affine_func$coeff_1_U873.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U872.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U874.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -33065,10 +33065,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U875$lut$lut.bit.in.2","d_0_am__U875$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U875$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U875$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U875$lut$lut.bit.out"], + ["d_0_am__U880$lut$lut.bit.in.2","d_0_am__U880$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U880$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U880$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U880$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -33104,7 +33104,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U879":{ + "affine_controller__U883":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -33112,49 +33112,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U888":{ + "_U892":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U8881":{ + "_U8921":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U889":{ + "_U893":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U886":{ + "affine_func$add_all__U890":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U887":{ + "affine_func$add_all__U891":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U881":{ + "affine_func$coeff_0_U885":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U883":{ + "affine_func$coeff_1_U887":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U885":{ + "affine_func$const_term_U889":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U882":{ + "affine_func$mul_d0__U886":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U884":{ + "affine_func$mul_d1__U888":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -33218,12 +33218,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U890$c0_lutcnst":{ + "d_0_am__U894$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U890$lut$lut":{ + "d_0_am__U894$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -33342,18 +33342,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U888.out"], - ["d_1_inc.in1","_U8881.out"], - ["cmp_time.in1","_U889.out"], - ["affine_func$mul_d0__U882.out","affine_func$add_all__U886.in0"], - ["affine_func$mul_d1__U884.out","affine_func$add_all__U886.in1"], - ["affine_func$add_all__U887.in0","affine_func$add_all__U886.out"], - ["affine_func$const_term_U885.out","affine_func$add_all__U887.in1"], - ["time_diff.in0","affine_func$add_all__U887.out"], - ["affine_func$mul_d0__U882.in0","affine_func$coeff_0_U881.out"], - ["affine_func$mul_d1__U884.in0","affine_func$coeff_1_U883.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U882.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U884.in1"], + ["d_0_inc.in1","_U892.out"], + ["d_1_inc.in1","_U8921.out"], + ["cmp_time.in1","_U893.out"], + ["affine_func$mul_d0__U886.out","affine_func$add_all__U890.in0"], + ["affine_func$mul_d1__U888.out","affine_func$add_all__U890.in1"], + ["affine_func$add_all__U891.in0","affine_func$add_all__U890.out"], + ["affine_func$const_term_U889.out","affine_func$add_all__U891.in1"], + ["time_diff.in0","affine_func$add_all__U891.out"], + ["affine_func$mul_d0__U886.in0","affine_func$coeff_0_U885.out"], + ["affine_func$mul_d1__U888.in0","affine_func$coeff_1_U887.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U886.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U888.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -33376,10 +33376,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U890$lut$lut.bit.in.2","d_0_am__U890$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U890$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U890$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U890$lut$lut.bit.out"], + ["d_0_am__U894$lut$lut.bit.in.2","d_0_am__U894$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U894$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U894$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U894$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -33415,7 +33415,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U894":{ + "affine_controller__U897":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -33423,49 +33423,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U903":{ + "_U906":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U9031":{ + "_U9061":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U904":{ + "_U907":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U901":{ + "affine_func$add_all__U904":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U902":{ + "affine_func$add_all__U905":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U896":{ + "affine_func$coeff_0_U899":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U898":{ + "affine_func$coeff_1_U901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U900":{ + "affine_func$const_term_U903":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U897":{ + "affine_func$mul_d0__U900":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U899":{ + "affine_func$mul_d1__U902":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -33529,12 +33529,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U905$c0_lutcnst":{ + "d_0_am__U908$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U905$lut$lut":{ + "d_0_am__U908$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -33653,18 +33653,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U903.out"], - ["d_1_inc.in1","_U9031.out"], - ["cmp_time.in1","_U904.out"], - ["affine_func$mul_d0__U897.out","affine_func$add_all__U901.in0"], - ["affine_func$mul_d1__U899.out","affine_func$add_all__U901.in1"], - ["affine_func$add_all__U902.in0","affine_func$add_all__U901.out"], - ["affine_func$const_term_U900.out","affine_func$add_all__U902.in1"], - ["time_diff.in0","affine_func$add_all__U902.out"], - ["affine_func$mul_d0__U897.in0","affine_func$coeff_0_U896.out"], - ["affine_func$mul_d1__U899.in0","affine_func$coeff_1_U898.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U897.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U899.in1"], + ["d_0_inc.in1","_U906.out"], + ["d_1_inc.in1","_U9061.out"], + ["cmp_time.in1","_U907.out"], + ["affine_func$mul_d0__U900.out","affine_func$add_all__U904.in0"], + ["affine_func$mul_d1__U902.out","affine_func$add_all__U904.in1"], + ["affine_func$add_all__U905.in0","affine_func$add_all__U904.out"], + ["affine_func$const_term_U903.out","affine_func$add_all__U905.in1"], + ["time_diff.in0","affine_func$add_all__U905.out"], + ["affine_func$mul_d0__U900.in0","affine_func$coeff_0_U899.out"], + ["affine_func$mul_d1__U902.in0","affine_func$coeff_1_U901.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U900.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U902.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -33687,10 +33687,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U905$lut$lut.bit.in.2","d_0_am__U905$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U905$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U905$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U905$lut$lut.bit.out"], + ["d_0_am__U908$lut$lut.bit.in.2","d_0_am__U908$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U908$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U908$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U908$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -33726,7 +33726,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U909":{ + "affine_controller__U911":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -33734,49 +33734,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U918":{ + "_U920":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U9181":{ + "_U9201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U919":{ + "_U921":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U916":{ + "affine_func$add_all__U918":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U917":{ + "affine_func$add_all__U919":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U911":{ + "affine_func$coeff_0_U913":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U913":{ + "affine_func$coeff_1_U915":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U915":{ + "affine_func$const_term_U917":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U912":{ + "affine_func$mul_d0__U914":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U914":{ + "affine_func$mul_d1__U916":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -33840,12 +33840,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U920$c0_lutcnst":{ + "d_0_am__U922$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U920$lut$lut":{ + "d_0_am__U922$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -33964,18 +33964,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U918.out"], - ["d_1_inc.in1","_U9181.out"], - ["cmp_time.in1","_U919.out"], - ["affine_func$mul_d0__U912.out","affine_func$add_all__U916.in0"], - ["affine_func$mul_d1__U914.out","affine_func$add_all__U916.in1"], - ["affine_func$add_all__U917.in0","affine_func$add_all__U916.out"], - ["affine_func$const_term_U915.out","affine_func$add_all__U917.in1"], - ["time_diff.in0","affine_func$add_all__U917.out"], - ["affine_func$mul_d0__U912.in0","affine_func$coeff_0_U911.out"], - ["affine_func$mul_d1__U914.in0","affine_func$coeff_1_U913.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U912.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U914.in1"], + ["d_0_inc.in1","_U920.out"], + ["d_1_inc.in1","_U9201.out"], + ["cmp_time.in1","_U921.out"], + ["affine_func$mul_d0__U914.out","affine_func$add_all__U918.in0"], + ["affine_func$mul_d1__U916.out","affine_func$add_all__U918.in1"], + ["affine_func$add_all__U919.in0","affine_func$add_all__U918.out"], + ["affine_func$const_term_U917.out","affine_func$add_all__U919.in1"], + ["time_diff.in0","affine_func$add_all__U919.out"], + ["affine_func$mul_d0__U914.in0","affine_func$coeff_0_U913.out"], + ["affine_func$mul_d1__U916.in0","affine_func$coeff_1_U915.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U914.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U916.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -33998,10 +33998,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U920$lut$lut.bit.in.2","d_0_am__U920$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U920$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U920$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U920$lut$lut.bit.out"], + ["d_0_am__U922$lut$lut.bit.in.2","d_0_am__U922$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U922$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U922$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U922$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -34037,7 +34037,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U91":{ + "affine_controller__U925":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -34045,49 +34045,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U100":{ + "_U934":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1001":{ + "_U9341":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U101":{ + "_U935":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U98":{ + "affine_func$add_all__U932":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U99":{ + "affine_func$add_all__U933":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U93":{ + "affine_func$coeff_0_U927":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U95":{ + "affine_func$coeff_1_U929":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U97":{ + "affine_func$const_term_U931":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U94":{ + "affine_func$mul_d0__U928":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U96":{ + "affine_func$mul_d1__U930":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -34151,12 +34151,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U102$c0_lutcnst":{ + "d_0_am__U936$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U102$lut$lut":{ + "d_0_am__U936$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -34275,18 +34275,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U100.out"], - ["d_1_inc.in1","_U1001.out"], - ["cmp_time.in1","_U101.out"], - ["affine_func$mul_d0__U94.out","affine_func$add_all__U98.in0"], - ["affine_func$mul_d1__U96.out","affine_func$add_all__U98.in1"], - ["affine_func$add_all__U99.in0","affine_func$add_all__U98.out"], - ["affine_func$const_term_U97.out","affine_func$add_all__U99.in1"], - ["time_diff.in0","affine_func$add_all__U99.out"], - ["affine_func$mul_d0__U94.in0","affine_func$coeff_0_U93.out"], - ["affine_func$mul_d1__U96.in0","affine_func$coeff_1_U95.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U94.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U96.in1"], + ["d_0_inc.in1","_U934.out"], + ["d_1_inc.in1","_U9341.out"], + ["cmp_time.in1","_U935.out"], + ["affine_func$mul_d0__U928.out","affine_func$add_all__U932.in0"], + ["affine_func$mul_d1__U930.out","affine_func$add_all__U932.in1"], + ["affine_func$add_all__U933.in0","affine_func$add_all__U932.out"], + ["affine_func$const_term_U931.out","affine_func$add_all__U933.in1"], + ["time_diff.in0","affine_func$add_all__U933.out"], + ["affine_func$mul_d0__U928.in0","affine_func$coeff_0_U927.out"], + ["affine_func$mul_d1__U930.in0","affine_func$coeff_1_U929.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U928.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U930.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -34309,10 +34309,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U102$lut$lut.bit.in.2","d_0_am__U102$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U102$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U102$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U102$lut$lut.bit.out"], + ["d_0_am__U936$lut$lut.bit.in.2","d_0_am__U936$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U936$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U936$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U936$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -34348,7 +34348,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U924":{ + "affine_controller__U939":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -34356,49 +34356,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U933":{ + "_U948":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U9331":{ + "_U9481":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U934":{ + "_U949":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U931":{ + "affine_func$add_all__U946":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U932":{ + "affine_func$add_all__U947":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U926":{ + "affine_func$coeff_0_U941":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U928":{ + "affine_func$coeff_1_U943":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U930":{ + "affine_func$const_term_U945":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U927":{ + "affine_func$mul_d0__U942":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U929":{ + "affine_func$mul_d1__U944":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -34462,12 +34462,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U935$c0_lutcnst":{ + "d_0_am__U950$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U935$lut$lut":{ + "d_0_am__U950$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -34586,18 +34586,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U933.out"], - ["d_1_inc.in1","_U9331.out"], - ["cmp_time.in1","_U934.out"], - ["affine_func$mul_d0__U927.out","affine_func$add_all__U931.in0"], - ["affine_func$mul_d1__U929.out","affine_func$add_all__U931.in1"], - ["affine_func$add_all__U932.in0","affine_func$add_all__U931.out"], - ["affine_func$const_term_U930.out","affine_func$add_all__U932.in1"], - ["time_diff.in0","affine_func$add_all__U932.out"], - ["affine_func$mul_d0__U927.in0","affine_func$coeff_0_U926.out"], - ["affine_func$mul_d1__U929.in0","affine_func$coeff_1_U928.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U927.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U929.in1"], + ["d_0_inc.in1","_U948.out"], + ["d_1_inc.in1","_U9481.out"], + ["cmp_time.in1","_U949.out"], + ["affine_func$mul_d0__U942.out","affine_func$add_all__U946.in0"], + ["affine_func$mul_d1__U944.out","affine_func$add_all__U946.in1"], + ["affine_func$add_all__U947.in0","affine_func$add_all__U946.out"], + ["affine_func$const_term_U945.out","affine_func$add_all__U947.in1"], + ["time_diff.in0","affine_func$add_all__U947.out"], + ["affine_func$mul_d0__U942.in0","affine_func$coeff_0_U941.out"], + ["affine_func$mul_d1__U944.in0","affine_func$coeff_1_U943.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U942.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U944.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -34620,10 +34620,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U935$lut$lut.bit.in.2","d_0_am__U935$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U935$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U935$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U935$lut$lut.bit.out"], + ["d_0_am__U950$lut$lut.bit.in.2","d_0_am__U950$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U950$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U950$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U950$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -34659,7 +34659,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U939":{ + "affine_controller__U953":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -34667,49 +34667,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U948":{ + "_U962":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U9481":{ + "_U9621":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U949":{ + "_U963":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U946":{ + "affine_func$add_all__U960":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U947":{ + "affine_func$add_all__U961":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U941":{ + "affine_func$coeff_0_U955":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U943":{ + "affine_func$coeff_1_U957":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U945":{ + "affine_func$const_term_U959":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U942":{ + "affine_func$mul_d0__U956":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U944":{ + "affine_func$mul_d1__U958":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -34773,12 +34773,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U950$c0_lutcnst":{ + "d_0_am__U964$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U950$lut$lut":{ + "d_0_am__U964$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -34897,18 +34897,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U948.out"], - ["d_1_inc.in1","_U9481.out"], - ["cmp_time.in1","_U949.out"], - ["affine_func$mul_d0__U942.out","affine_func$add_all__U946.in0"], - ["affine_func$mul_d1__U944.out","affine_func$add_all__U946.in1"], - ["affine_func$add_all__U947.in0","affine_func$add_all__U946.out"], - ["affine_func$const_term_U945.out","affine_func$add_all__U947.in1"], - ["time_diff.in0","affine_func$add_all__U947.out"], - ["affine_func$mul_d0__U942.in0","affine_func$coeff_0_U941.out"], - ["affine_func$mul_d1__U944.in0","affine_func$coeff_1_U943.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U942.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U944.in1"], + ["d_0_inc.in1","_U962.out"], + ["d_1_inc.in1","_U9621.out"], + ["cmp_time.in1","_U963.out"], + ["affine_func$mul_d0__U956.out","affine_func$add_all__U960.in0"], + ["affine_func$mul_d1__U958.out","affine_func$add_all__U960.in1"], + ["affine_func$add_all__U961.in0","affine_func$add_all__U960.out"], + ["affine_func$const_term_U959.out","affine_func$add_all__U961.in1"], + ["time_diff.in0","affine_func$add_all__U961.out"], + ["affine_func$mul_d0__U956.in0","affine_func$coeff_0_U955.out"], + ["affine_func$mul_d1__U958.in0","affine_func$coeff_1_U957.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U956.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U958.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -34931,10 +34931,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U950$lut$lut.bit.in.2","d_0_am__U950$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U950$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U950$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U950$lut$lut.bit.out"], + ["d_0_am__U964$lut$lut.bit.in.2","d_0_am__U964$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U964$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U964$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U964$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -34970,7 +34970,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U954":{ + "affine_controller__U967":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -34978,49 +34978,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U963":{ + "_U976":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U9631":{ + "_U9761":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U964":{ + "_U977":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U961":{ + "affine_func$add_all__U974":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U962":{ + "affine_func$add_all__U975":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U956":{ + "affine_func$coeff_0_U969":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U958":{ + "affine_func$coeff_1_U971":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U960":{ + "affine_func$const_term_U973":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U957":{ + "affine_func$mul_d0__U970":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U959":{ + "affine_func$mul_d1__U972":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -35084,12 +35084,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U965$c0_lutcnst":{ + "d_0_am__U978$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U965$lut$lut":{ + "d_0_am__U978$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -35208,18 +35208,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U963.out"], - ["d_1_inc.in1","_U9631.out"], - ["cmp_time.in1","_U964.out"], - ["affine_func$mul_d0__U957.out","affine_func$add_all__U961.in0"], - ["affine_func$mul_d1__U959.out","affine_func$add_all__U961.in1"], - ["affine_func$add_all__U962.in0","affine_func$add_all__U961.out"], - ["affine_func$const_term_U960.out","affine_func$add_all__U962.in1"], - ["time_diff.in0","affine_func$add_all__U962.out"], - ["affine_func$mul_d0__U957.in0","affine_func$coeff_0_U956.out"], - ["affine_func$mul_d1__U959.in0","affine_func$coeff_1_U958.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U957.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U959.in1"], + ["d_0_inc.in1","_U976.out"], + ["d_1_inc.in1","_U9761.out"], + ["cmp_time.in1","_U977.out"], + ["affine_func$mul_d0__U970.out","affine_func$add_all__U974.in0"], + ["affine_func$mul_d1__U972.out","affine_func$add_all__U974.in1"], + ["affine_func$add_all__U975.in0","affine_func$add_all__U974.out"], + ["affine_func$const_term_U973.out","affine_func$add_all__U975.in1"], + ["time_diff.in0","affine_func$add_all__U975.out"], + ["affine_func$mul_d0__U970.in0","affine_func$coeff_0_U969.out"], + ["affine_func$mul_d1__U972.in0","affine_func$coeff_1_U971.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U970.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U972.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -35242,10 +35242,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U965$lut$lut.bit.in.2","d_0_am__U965$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U965$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U965$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U965$lut$lut.bit.out"], + ["d_0_am__U978$lut$lut.bit.in.2","d_0_am__U978$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U978$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U978$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U978$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -35281,7 +35281,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U969":{ + "affine_controller__U981":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -35289,49 +35289,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U978":{ + "_U990":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U9781":{ + "_U9901":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U979":{ + "_U991":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U976":{ + "affine_func$add_all__U988":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U977":{ + "affine_func$add_all__U989":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U971":{ + "affine_func$coeff_0_U983":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U973":{ + "affine_func$coeff_1_U985":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U975":{ + "affine_func$const_term_U987":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U972":{ + "affine_func$mul_d0__U984":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U974":{ + "affine_func$mul_d1__U986":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -35395,12 +35395,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U980$c0_lutcnst":{ + "d_0_am__U992$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U980$lut$lut":{ + "d_0_am__U992$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -35519,18 +35519,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U978.out"], - ["d_1_inc.in1","_U9781.out"], - ["cmp_time.in1","_U979.out"], - ["affine_func$mul_d0__U972.out","affine_func$add_all__U976.in0"], - ["affine_func$mul_d1__U974.out","affine_func$add_all__U976.in1"], - ["affine_func$add_all__U977.in0","affine_func$add_all__U976.out"], - ["affine_func$const_term_U975.out","affine_func$add_all__U977.in1"], - ["time_diff.in0","affine_func$add_all__U977.out"], - ["affine_func$mul_d0__U972.in0","affine_func$coeff_0_U971.out"], - ["affine_func$mul_d1__U974.in0","affine_func$coeff_1_U973.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U972.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U974.in1"], + ["d_0_inc.in1","_U990.out"], + ["d_1_inc.in1","_U9901.out"], + ["cmp_time.in1","_U991.out"], + ["affine_func$mul_d0__U984.out","affine_func$add_all__U988.in0"], + ["affine_func$mul_d1__U986.out","affine_func$add_all__U988.in1"], + ["affine_func$add_all__U989.in0","affine_func$add_all__U988.out"], + ["affine_func$const_term_U987.out","affine_func$add_all__U989.in1"], + ["time_diff.in0","affine_func$add_all__U989.out"], + ["affine_func$mul_d0__U984.in0","affine_func$coeff_0_U983.out"], + ["affine_func$mul_d1__U986.in0","affine_func$coeff_1_U985.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U984.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U986.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -35553,10 +35553,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U980$lut$lut.bit.in.2","d_0_am__U980$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U980$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U980$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U980$lut$lut.bit.out"], + ["d_0_am__U992$lut$lut.bit.in.2","d_0_am__U992$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U992$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U992$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U992$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -35592,7 +35592,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U984":{ + "affine_controller__U99":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -35600,49 +35600,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U993":{ + "_U108":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U9931":{ + "_U1081":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U994":{ + "_U109":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U991":{ + "affine_func$add_all__U106":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U992":{ + "affine_func$add_all__U107":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U986":{ + "affine_func$coeff_0_U101":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U988":{ + "affine_func$coeff_1_U103":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U990":{ + "affine_func$const_term_U105":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U987":{ + "affine_func$mul_d0__U102":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U989":{ + "affine_func$mul_d1__U104":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -35706,12 +35706,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U995$c0_lutcnst":{ + "d_0_am__U110$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U995$lut$lut":{ + "d_0_am__U110$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -35830,18 +35830,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U993.out"], - ["d_1_inc.in1","_U9931.out"], - ["cmp_time.in1","_U994.out"], - ["affine_func$mul_d0__U987.out","affine_func$add_all__U991.in0"], - ["affine_func$mul_d1__U989.out","affine_func$add_all__U991.in1"], - ["affine_func$add_all__U992.in0","affine_func$add_all__U991.out"], - ["affine_func$const_term_U990.out","affine_func$add_all__U992.in1"], - ["time_diff.in0","affine_func$add_all__U992.out"], - ["affine_func$mul_d0__U987.in0","affine_func$coeff_0_U986.out"], - ["affine_func$mul_d1__U989.in0","affine_func$coeff_1_U988.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U987.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U989.in1"], + ["d_0_inc.in1","_U108.out"], + ["d_1_inc.in1","_U1081.out"], + ["cmp_time.in1","_U109.out"], + ["affine_func$mul_d0__U102.out","affine_func$add_all__U106.in0"], + ["affine_func$mul_d1__U104.out","affine_func$add_all__U106.in1"], + ["affine_func$add_all__U107.in0","affine_func$add_all__U106.out"], + ["affine_func$const_term_U105.out","affine_func$add_all__U107.in1"], + ["time_diff.in0","affine_func$add_all__U107.out"], + ["affine_func$mul_d0__U102.in0","affine_func$coeff_0_U101.out"], + ["affine_func$mul_d1__U104.in0","affine_func$coeff_1_U103.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U102.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U104.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -35864,10 +35864,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U995$lut$lut.bit.in.2","d_0_am__U995$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U995$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U995$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U995$lut$lut.bit.out"], + ["d_0_am__U110$lut$lut.bit.in.2","d_0_am__U110$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U110$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U110$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U110$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -35903,7 +35903,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U999":{ + "affine_controller__U995":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -35911,49 +35911,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U1008":{ + "_U1004":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U10081":{ + "_U10041":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U1009":{ + "_U1005":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U1006":{ + "affine_func$add_all__U1002":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U1007":{ + "affine_func$add_all__U1003":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U1001":{ + "affine_func$coeff_0_U997":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U1003":{ + "affine_func$coeff_1_U999":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U1005":{ + "affine_func$const_term_U1001":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012000"]} }, - "affine_func$mul_d0__U1002":{ + "affine_func$mul_d0__U998":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U1004":{ + "affine_func$mul_d1__U1000":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -36017,12 +36017,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U1010$c0_lutcnst":{ + "d_0_am__U1006$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U1010$lut$lut":{ + "d_0_am__U1006$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -36141,18 +36141,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U1008.out"], - ["d_1_inc.in1","_U10081.out"], - ["cmp_time.in1","_U1009.out"], - ["affine_func$mul_d0__U1002.out","affine_func$add_all__U1006.in0"], - ["affine_func$mul_d1__U1004.out","affine_func$add_all__U1006.in1"], - ["affine_func$add_all__U1007.in0","affine_func$add_all__U1006.out"], - ["affine_func$const_term_U1005.out","affine_func$add_all__U1007.in1"], - ["time_diff.in0","affine_func$add_all__U1007.out"], - ["affine_func$mul_d0__U1002.in0","affine_func$coeff_0_U1001.out"], - ["affine_func$mul_d1__U1004.in0","affine_func$coeff_1_U1003.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U1002.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U1004.in1"], + ["d_0_inc.in1","_U1004.out"], + ["d_1_inc.in1","_U10041.out"], + ["cmp_time.in1","_U1005.out"], + ["affine_func$mul_d0__U998.out","affine_func$add_all__U1002.in0"], + ["affine_func$mul_d1__U1000.out","affine_func$add_all__U1002.in1"], + ["affine_func$add_all__U1003.in0","affine_func$add_all__U1002.out"], + ["affine_func$const_term_U1001.out","affine_func$add_all__U1003.in1"], + ["time_diff.in0","affine_func$add_all__U1003.out"], + ["affine_func$mul_d0__U998.in0","affine_func$coeff_0_U997.out"], + ["affine_func$mul_d1__U1000.in0","affine_func$coeff_1_U999.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U998.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U1000.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -36175,10 +36175,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U1010$lut$lut.bit.in.2","d_0_am__U1010$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U1010$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U1010$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U1010$lut$lut.bit.out"], + ["d_0_am__U1006$lut$lut.bit.in.2","d_0_am__U1006$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U1006$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U1006$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U1006$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -36287,26 +36287,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1606":{ + "PE_init_U1523":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1604":{ + "_U1521":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1605":{ + "_U1522":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1604.out","PE_init_U1606.data.in.0"], - ["_U1605.out","PE_init_U1606.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U1606.data.out"], + ["_U1521.out","PE_init_U1523.data.in.0"], + ["_U1522.out","PE_init_U1523.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U1523.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -36318,26 +36318,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1609":{ + "PE_init_U1526":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1607":{ + "_U1524":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1608":{ + "_U1525":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1607.out","PE_init_U1609.data.in.0"], - ["_U1608.out","PE_init_U1609.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U1609.data.out"], + ["_U1524.out","PE_init_U1526.data.in.0"], + ["_U1525.out","PE_init_U1526.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U1526.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -37123,26 +37123,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1612":{ + "PE_init_U1529":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1610":{ + "_U1527":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1611":{ + "_U1528":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1610.out","PE_init_U1612.data.in.0"], - ["_U1611.out","PE_init_U1612.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U1612.data.out"], + ["_U1527.out","PE_init_U1529.data.in.0"], + ["_U1528.out","PE_init_U1529.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U1529.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -37154,26 +37154,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1615":{ + "PE_init_U1532":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1613":{ + "_U1530":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1614":{ + "_U1531":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1613.out","PE_init_U1615.data.in.0"], - ["_U1614.out","PE_init_U1615.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U1615.data.out"], + ["_U1530.out","PE_init_U1532.data.in.0"], + ["_U1531.out","PE_init_U1532.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U1532.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -37185,26 +37185,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1618":{ + "PE_init_U1535":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1616":{ + "_U1533":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1617":{ + "_U1534":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1616.out","PE_init_U1618.data.in.0"], - ["_U1617.out","PE_init_U1618.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U1618.data.out"], + ["_U1533.out","PE_init_U1535.data.in.0"], + ["_U1534.out","PE_init_U1535.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U1535.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -37216,26 +37216,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1621":{ + "PE_init_U1538":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1619":{ + "_U1536":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1620":{ + "_U1537":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1619.out","PE_init_U1621.data.in.0"], - ["_U1620.out","PE_init_U1621.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U1621.data.out"], + ["_U1536.out","PE_init_U1538.data.in.0"], + ["_U1537.out","PE_init_U1538.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U1538.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -37247,26 +37247,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1624":{ + "PE_init_U1541":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1622":{ + "_U1539":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1623":{ + "_U1540":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1622.out","PE_init_U1624.data.in.0"], - ["_U1623.out","PE_init_U1624.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U1624.data.out"], + ["_U1539.out","PE_init_U1541.data.in.0"], + ["_U1540.out","PE_init_U1541.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U1541.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -37278,26 +37278,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U1627":{ + "PE_init_U1544":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1625":{ + "_U1542":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1626":{ + "_U1543":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1625.out","PE_init_U1627.data.in.0"], - ["_U1626.out","PE_init_U1627.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U1627.data.out"], + ["_U1542.out","PE_init_U1544.data.in.0"], + ["_U1543.out","PE_init_U1544.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U1544.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -37622,26 +37622,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1630":{ + "PE_init_U1547":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1628":{ + "_U1545":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1629":{ + "_U1546":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1628.out","PE_init_U1630.data.in.0"], - ["_U1629.out","PE_init_U1630.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1630.data.out"] + ["_U1545.out","PE_init_U1547.data.in.0"], + ["_U1546.out","PE_init_U1547.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1547.data.out"] ] }, "hcompute_output_cgra_stencil_1":{ @@ -37649,26 +37649,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1633":{ + "PE_init_U1550":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1631":{ + "_U1548":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1632":{ + "_U1549":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1631.out","PE_init_U1633.data.in.0"], - ["_U1632.out","PE_init_U1633.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1633.data.out"] + ["_U1548.out","PE_init_U1550.data.in.0"], + ["_U1549.out","PE_init_U1550.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1550.data.out"] ] }, "hcompute_output_cgra_stencil_10":{ @@ -38426,26 +38426,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1636":{ + "PE_init_U1553":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1634":{ + "_U1551":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1635":{ + "_U1552":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1634.out","PE_init_U1636.data.in.0"], - ["_U1635.out","PE_init_U1636.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1636.data.out"] + ["_U1551.out","PE_init_U1553.data.in.0"], + ["_U1552.out","PE_init_U1553.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1553.data.out"] ] }, "hcompute_output_cgra_stencil_3":{ @@ -38453,26 +38453,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1639":{ + "PE_init_U1556":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1637":{ + "_U1554":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1638":{ + "_U1555":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1637.out","PE_init_U1639.data.in.0"], - ["_U1638.out","PE_init_U1639.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1639.data.out"] + ["_U1554.out","PE_init_U1556.data.in.0"], + ["_U1555.out","PE_init_U1556.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1556.data.out"] ] }, "hcompute_output_cgra_stencil_4":{ @@ -38480,26 +38480,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1642":{ + "PE_init_U1559":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1640":{ + "_U1557":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1641":{ + "_U1558":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1640.out","PE_init_U1642.data.in.0"], - ["_U1641.out","PE_init_U1642.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1642.data.out"] + ["_U1557.out","PE_init_U1559.data.in.0"], + ["_U1558.out","PE_init_U1559.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1559.data.out"] ] }, "hcompute_output_cgra_stencil_5":{ @@ -38507,26 +38507,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1645":{ + "PE_init_U1562":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1643":{ + "_U1560":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1644":{ + "_U1561":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1643.out","PE_init_U1645.data.in.0"], - ["_U1644.out","PE_init_U1645.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1645.data.out"] + ["_U1560.out","PE_init_U1562.data.in.0"], + ["_U1561.out","PE_init_U1562.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1562.data.out"] ] }, "hcompute_output_cgra_stencil_6":{ @@ -38534,26 +38534,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1648":{ + "PE_init_U1565":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1646":{ + "_U1563":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1647":{ + "_U1564":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1646.out","PE_init_U1648.data.in.0"], - ["_U1647.out","PE_init_U1648.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1648.data.out"] + ["_U1563.out","PE_init_U1565.data.in.0"], + ["_U1564.out","PE_init_U1565.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1565.data.out"] ] }, "hcompute_output_cgra_stencil_7":{ @@ -38561,26 +38561,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U1651":{ + "PE_init_U1568":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1649":{ + "_U1566":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1650":{ + "_U1567":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U1649.out","PE_init_U1651.data.in.0"], - ["_U1650.out","PE_init_U1651.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U1651.data.out"] + ["_U1566.out","PE_init_U1568.data.in.0"], + ["_U1567.out","PE_init_U1568.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U1568.data.out"] ] }, "hcompute_output_cgra_stencil_8":{ @@ -38867,38 +38867,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U104":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U14":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U44":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U74":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -38906,7 +38874,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -38916,7 +38884,7 @@ }, "ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -38926,7 +38894,7 @@ }, "ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -38936,7 +38904,7 @@ }, "ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -38946,7 +38914,7 @@ }, "ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -38956,7 +38924,7 @@ }, "ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -38966,7 +38934,7 @@ }, "ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -38976,7 +38944,7 @@ }, "ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U105"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -39118,262 +39086,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1012":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1027":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1042":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1057":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1072":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1087":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1102":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1117":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U1192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U262":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U277":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U292":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U307":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U322":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U337":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U352":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U367":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U397":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U412":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U427":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U442":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U457":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U472":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U487":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U502":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U517":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U532":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U547":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U562":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U577":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U592":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U607":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U622":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U637":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U652":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U667":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U682":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U697":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U712":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U727":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U742":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U757":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U772":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U787":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U802":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U817":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U832":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U847":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U862":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U877":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U892":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U907":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U922":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U937":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U952":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U967":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U982":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U997":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -39381,7 +39093,7 @@ }, "ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -39391,7 +39103,7 @@ }, "ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U364"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[154],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[129],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -39401,7 +39113,7 @@ }, "ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U398"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U378"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[193],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -39411,7 +39123,7 @@ }, "ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U413"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U392"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[282],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[257],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -39421,7 +39133,7 @@ }, "ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U428"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U406"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[346],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[321],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -39431,7 +39143,7 @@ }, "ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U443"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U420"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[410],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[385],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -39441,7 +39153,7 @@ }, "ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U458"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U434"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[474],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[449],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -39451,7 +39163,7 @@ }, "ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U473"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U448"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -39461,7 +39173,7 @@ }, "ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U488"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U462"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[66],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -39471,7 +39183,7 @@ }, "ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U503"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U476"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[155],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -39481,7 +39193,7 @@ }, "ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U518"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U490"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[194],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -39491,7 +39203,7 @@ }, "ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[64],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -39501,7 +39213,7 @@ }, "ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U533"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U504"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[283],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[258],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -39511,7 +39223,7 @@ }, "ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U548"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U518"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[347],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[322],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -39521,7 +39233,7 @@ }, "ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U563"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U532"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[411],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[386],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -39531,7 +39243,7 @@ }, "ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U578"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U546"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[475],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[450],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -39541,7 +39253,7 @@ }, "ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U593"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U560"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -39551,7 +39263,7 @@ }, "ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U608"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U574"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[67],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -39561,7 +39273,7 @@ }, "ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U623"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U588"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[156],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[131],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -39571,7 +39283,7 @@ }, "ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U638"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U602"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[195],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -39581,7 +39293,7 @@ }, "ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U653"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U616"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[284],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[259],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -39591,7 +39303,7 @@ }, "ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U668"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U630"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[348],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[323],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -39601,7 +39313,7 @@ }, "ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U263"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[153],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[128],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -39611,7 +39323,7 @@ }, "ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U683"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U644"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[412],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[387],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -39621,7 +39333,7 @@ }, "ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U698"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U658"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[476],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[451],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -39631,7 +39343,7 @@ }, "ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U713"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U672"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -39641,7 +39353,7 @@ }, "ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U728"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U686"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[68],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -39651,7 +39363,7 @@ }, "ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U743"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U700"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[157],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[132],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -39661,7 +39373,7 @@ }, "ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U758"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U714"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[196],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -39671,7 +39383,7 @@ }, "ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U773"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U728"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[285],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -39681,7 +39393,7 @@ }, "ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U788"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U742"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[349],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[324],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -39691,7 +39403,7 @@ }, "ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U803"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U756"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[413],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[388],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -39701,7 +39413,7 @@ }, "ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U818"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U770"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[477],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[452],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -39711,7 +39423,7 @@ }, "ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U278"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[192],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -39721,7 +39433,7 @@ }, "ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U833"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U784"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -39731,7 +39443,7 @@ }, "ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U848"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U798"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[69],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -39741,7 +39453,7 @@ }, "ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U863"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U812"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[158],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[133],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -39751,7 +39463,7 @@ }, "ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U878"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U826"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[197],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -39761,7 +39473,7 @@ }, "ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U893"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U840"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[286],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[261],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -39771,7 +39483,7 @@ }, "ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U908"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U854"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[350],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[325],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -39781,7 +39493,7 @@ }, "ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U923"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U868"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[414],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[389],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -39791,7 +39503,7 @@ }, "ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U938"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U882"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[478],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[453],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -39801,7 +39513,7 @@ }, "ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U953"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U896"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -39811,7 +39523,7 @@ }, "ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U968"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U910"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[70],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -39821,7 +39533,7 @@ }, "ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U293"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U280"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[281],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[256],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -39831,7 +39543,7 @@ }, "ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U983"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U924"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[159],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[134],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -39841,7 +39553,7 @@ }, "ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U998"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U938"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[198],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -39851,7 +39563,7 @@ }, "ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1013"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U952"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[287],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[262],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -39861,7 +39573,7 @@ }, "ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1028"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U966"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[351],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[326],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -39871,7 +39583,7 @@ }, "ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1043"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U980"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[415],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[390],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -39881,7 +39593,7 @@ }, "ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1058"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U994"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[479],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[454],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -39891,7 +39603,7 @@ }, "ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1073"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1008"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -39901,7 +39613,7 @@ }, "ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1088"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1022"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[71],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -39911,7 +39623,7 @@ }, "ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1036"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[160],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[135],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -39921,7 +39633,7 @@ }, "ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1050"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[199],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -39931,7 +39643,7 @@ }, "ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[345],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[320],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -39941,7 +39653,7 @@ }, "ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1064"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[288],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[263],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -39951,7 +39663,7 @@ }, "ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1078"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[352],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[327],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -39961,7 +39673,7 @@ }, "ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1092"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[416],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[391],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -39971,7 +39683,7 @@ }, "ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1106"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[480],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[455],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -39981,7 +39693,7 @@ }, "ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U323"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[409],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[384],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -39991,7 +39703,7 @@ }, "ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U338"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U322"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[473],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[448],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -40001,7 +39713,7 @@ }, "ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U353"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U336"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -40011,7 +39723,7 @@ }, "ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U368"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U350"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[65],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -40352,7 +40064,7 @@ ["self.op_hcompute_kernel_glb_stencil_write.0","self.op_hcompute_kernel_cgra_stencil_read.0"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U1590":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U1507":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -40361,7 +40073,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U1589":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U1506":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40370,7 +40082,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U1588":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U1505":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -40379,7 +40091,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U1587":{ + "op_hcompute_hw_output_stencil_read_start_pt__U1504":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40388,7 +40100,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U1592":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U1509":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -40397,7 +40109,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U1591":{ + "op_hcompute_hw_output_stencil_write_start_pt__U1508":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40406,7 +40118,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U1600":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U1517":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40415,7 +40127,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U1599":{ + "op_hcompute_input_glb_stencil_read_start_pt__U1516":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40424,7 +40136,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U1601":{ + "op_hcompute_input_glb_stencil_write_start_pt__U1518":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40433,7 +40145,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U1595":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U1512":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40442,7 +40154,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U1594":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U1511":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40451,7 +40163,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U1596":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U1513":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -40517,38 +40229,6 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1357":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1372":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1387":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1402":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1417":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1432":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1447":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U1462":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -40556,7 +40236,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1343"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1269"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50974],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50976],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -40566,7 +40246,7 @@ }, "ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1358"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1283"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"agg2sram_1":{"cycle_starting_addr":[18437],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"in2agg_1":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50977],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -40576,7 +40256,7 @@ }, "ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1373"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1297"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50978],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -40586,7 +40266,7 @@ }, "ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1388"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50977],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50979],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -40596,7 +40276,7 @@ }, "ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1403"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1325"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50978],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50980],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -40606,7 +40286,7 @@ }, "ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1418"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1339"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50979],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50981],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -40616,7 +40296,7 @@ }, "ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1433"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1353"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50980],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50982],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -40626,7 +40306,7 @@ }, "ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1448"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1367"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50981],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50983],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -40715,158 +40395,126 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U1654":{ + "PE_init_U1571":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U1657":{ + "PE_init_U1574":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U1660":{ + "PE_init_U1577":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U1663":{ + "PE_init_U1580":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U1666":{ + "PE_init_U1583":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U1669":{ + "PE_init_U1586":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U1672":{ + "PE_init_U1589":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U1675":{ + "PE_init_U1592":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U1652":{ + "_U1569":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1653":{ + "_U1570":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1655":{ + "_U1572":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1656":{ + "_U1573":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1658":{ + "_U1575":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1659":{ + "_U1576":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1661":{ + "_U1578":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1662":{ + "_U1579":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1664":{ + "_U1581":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1665":{ + "_U1582":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1667":{ + "_U1584":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1668":{ + "_U1585":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1670":{ + "_U1587":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1671":{ + "_U1588":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1673":{ + "_U1590":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U1674":{ + "_U1591":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "input_cgra_stencil$chain_en_const_U104":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U119":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U14":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U44":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U59":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U74":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U89":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -40874,7 +40522,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -40884,7 +40532,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -40894,7 +40542,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -40904,7 +40552,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U45"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -40914,7 +40562,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U60"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -40924,7 +40572,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U75"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -40934,7 +40582,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U84"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -40944,7 +40592,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U105"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U98"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,288,18432],"dimensionality":3,"extent":[9,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9,81]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,32,288,18432],"dimensionality":4,"extent":[4,9,9,4],"write_data_starting_addr":[0],"write_data_stride":[1,4,4,4]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[8,32,224,1568,4704,18432],"dimensionality":6,"extent":[4,7,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,9,1,9,81],"write_data_starting_addr":[0],"write_data_stride":[0,1,1,3,3,1]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,224,1568,4704,18432],"dimensionality":6,"extent":[8,28,7,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[0,1,4,12,12,4]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -40973,262 +40621,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "kernel_cgra_stencil$chain_en_const_U1012":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1027":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1042":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1057":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1072":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1087":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1102":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1117":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1132":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1162":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U1192":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U262":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U277":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U292":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U307":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U322":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U337":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U352":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U367":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U382":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U397":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U412":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U427":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U442":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U457":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U472":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U487":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U502":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U517":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U532":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U547":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U562":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U577":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U592":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U607":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U622":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U637":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U652":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U667":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U682":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U697":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U712":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U727":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U742":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U757":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U772":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U787":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U802":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U817":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U832":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U847":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U862":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U877":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U892":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U907":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U922":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U937":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U952":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U967":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U982":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U997":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -41236,7 +40628,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U233"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ @@ -41246,7 +40638,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U383"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U364"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[154],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[129],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ @@ -41256,7 +40648,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U398"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U378"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[193],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ @@ -41266,7 +40658,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U413"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U392"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[282],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[257],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ @@ -41276,7 +40668,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U428"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U406"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[346],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[321],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ @@ -41286,7 +40678,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U443"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U420"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[410],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[385],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ @@ -41296,7 +40688,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U458"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U434"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[474],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[449],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ @@ -41306,7 +40698,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U473"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U448"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ @@ -41316,7 +40708,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U488"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U462"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[91],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[66],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ @@ -41326,7 +40718,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U503"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U476"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[155],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[130],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ @@ -41336,7 +40728,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U518"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U490"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[194],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -41346,7 +40738,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[89],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[64],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ @@ -41356,7 +40748,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U533"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U504"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[283],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[258],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ @@ -41366,7 +40758,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U548"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U518"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[347],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[322],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ @@ -41376,7 +40768,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U563"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U532"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[411],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[386],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ @@ -41386,7 +40778,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U578"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U546"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[475],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[450],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ @@ -41396,7 +40788,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U593"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U560"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ @@ -41406,7 +40798,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U608"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U574"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[92],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[67],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ @@ -41416,7 +40808,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U623"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U588"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[156],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[131],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ @@ -41426,7 +40818,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U638"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U602"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[195],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ @@ -41436,7 +40828,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U653"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U616"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[284],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[259],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ @@ -41446,7 +40838,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U668"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U630"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[348],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[323],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -41456,7 +40848,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U263"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[153],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[128],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ @@ -41466,7 +40858,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U683"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U644"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[412],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[387],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ @@ -41476,7 +40868,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U698"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U658"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[476],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[451],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ @@ -41486,7 +40878,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U713"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U672"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ @@ -41496,7 +40888,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U728"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U686"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[93],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[68],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ @@ -41506,7 +40898,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U743"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U700"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[157],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[132],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ @@ -41516,7 +40908,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U758"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U714"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[196],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ @@ -41526,7 +40918,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U773"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U728"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[285],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[260],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ @@ -41536,7 +40928,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U788"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U742"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[349],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[324],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ @@ -41546,7 +40938,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U803"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U756"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[413],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[388],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ @@ -41556,7 +40948,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U818"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U770"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[477],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[452],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -41566,7 +40958,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U278"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[192],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ @@ -41576,7 +40968,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U833"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U784"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ @@ -41586,7 +40978,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U848"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U798"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[94],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[69],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ @@ -41596,7 +40988,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U863"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U812"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[158],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[133],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ @@ -41606,7 +40998,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U878"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U826"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[197],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ @@ -41616,7 +41008,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U893"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U840"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[286],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[261],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ @@ -41626,7 +41018,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U908"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U854"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[350],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[325],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ @@ -41636,7 +41028,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U923"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U868"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[414],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[389],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ @@ -41646,7 +41038,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U938"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U882"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[478],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[453],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ @@ -41656,7 +41048,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U953"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U896"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ @@ -41666,7 +41058,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U968"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U910"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[95],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[70],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -41676,7 +41068,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U293"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U280"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[281],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[256],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ @@ -41686,7 +41078,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U983"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U924"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[159],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[134],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ @@ -41696,7 +41088,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U998"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U938"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[198],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ @@ -41706,7 +41098,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1013"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U952"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[287],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[262],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ @@ -41716,7 +41108,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1028"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U966"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[351],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[326],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ @@ -41726,7 +41118,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1043"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U980"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[415],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[390],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ @@ -41736,7 +41128,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1058"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U994"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[479],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[454],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ @@ -41746,7 +41138,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1073"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1008"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ @@ -41756,7 +41148,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1088"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1022"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[96],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[71],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ @@ -41766,7 +41158,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1036"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[160],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[135],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ @@ -41776,7 +41168,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1118"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1050"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[199],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -41786,7 +41178,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U294"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[345],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[320],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ @@ -41796,7 +41188,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1064"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[288],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[263],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ @@ -41806,7 +41198,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1078"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[352],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[327],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ @@ -41816,7 +41208,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1092"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[416],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[391],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ @@ -41826,7 +41218,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1106"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[480],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[455],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -41836,7 +41228,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U323"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U308"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[409],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[384],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -41846,7 +41238,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U338"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U322"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[473],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[448],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ @@ -41856,7 +41248,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U353"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U336"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ @@ -41866,7 +41258,7 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U368"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U350"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[90],"cycle_stride":[32,512,2048,6144,18432],"dimensionality":5,"extent":[2,4,3,3,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[65],"cycle_stride":[8,512,2048,6144,18432],"dimensionality":5,"extent":[8,4,3,3,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[18429],"cycle_stride":[4,32,1568,18432],"dimensionality":4,"extent":[8,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,72],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,32,1568,18432],"dimensionality":4,"extent":[32,49,9,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -41876,7 +41268,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_lake_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1603"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1520"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[50976],"cycle_stride":[1,64,36864],"dimensionality":3,"extent":[64,49,2],"write_data_starting_addr":[0],"write_data_stride":[1,128,64]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_output_cgra_stencil_10$inner_compute$add_957_971_972$binop":{ @@ -42519,38 +41911,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "output_cgra_stencil$chain_en_const_U1357":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U1372":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U1387":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U1402":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U1417":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U1432":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U1447":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U1462":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -42558,7 +41918,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1343"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1269"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50974],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50976],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -42568,7 +41928,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1358"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1283"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"agg2sram_1":{"cycle_starting_addr":[18437],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"in2agg_1":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50977],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -42578,7 +41938,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1373"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1297"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50975],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50978],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -42588,7 +41948,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1388"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1311"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50977],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50979],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -42598,7 +41958,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1403"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1325"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50978],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50980],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -42608,7 +41968,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1418"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1339"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50979],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50981],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -42618,7 +41978,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1433"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1353"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50980],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50982],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -42628,35 +41988,35 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U1448"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1367"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[18436],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,98]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,8,56,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,14,98]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0,0,8]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,8,56,36864],"dimensionality":4,"extent":[8,7,7,2],"write_data_starting_addr":[0],"write_data_stride":[1,8,8,8]},"sram2tb_0":{"cycle_starting_addr":[18430],"cycle_stride":[4,8,32,1568,18432,36864],"dimensionality":6,"extent":[2,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0,0,98],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0,0,2]},"sram2tb_1":{"cycle_starting_addr":[50981],"cycle_stride":[32,64,448,36864],"dimensionality":4,"extent":[2,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,2,14,98],"write_data_starting_addr":[0],"write_data_stride":[1,2,2,2]},"tb2out_0":{"cycle_starting_addr":[18432],"cycle_stride":[1,8,32,1568,18432,36864],"dimensionality":6,"extent":[8,4,49,9,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0,0,8]},"tb2out_1":{"cycle_starting_addr":[50983],"cycle_stride":[8,64,448,36864],"dimensionality":4,"extent":[8,7,7,2],"read_data_starting_addr":[0],"read_data_stride":[1,8,8,8]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U1652.out","PE_init_U1654.data.in.0"], - ["_U1653.out","PE_init_U1654.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U1654.data.out"], - ["_U1655.out","PE_init_U1657.data.in.0"], - ["_U1656.out","PE_init_U1657.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U1657.data.out"], - ["_U1658.out","PE_init_U1660.data.in.0"], - ["_U1659.out","PE_init_U1660.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U1660.data.out"], - ["_U1661.out","PE_init_U1663.data.in.0"], - ["_U1662.out","PE_init_U1663.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U1663.data.out"], - ["_U1664.out","PE_init_U1666.data.in.0"], - ["_U1665.out","PE_init_U1666.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U1666.data.out"], - ["_U1667.out","PE_init_U1669.data.in.0"], - ["_U1668.out","PE_init_U1669.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U1669.data.out"], - ["_U1670.out","PE_init_U1672.data.in.0"], - ["_U1671.out","PE_init_U1672.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U1672.data.out"], - ["_U1673.out","PE_init_U1675.data.in.0"], - ["_U1674.out","PE_init_U1675.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U1675.data.out"], + ["_U1569.out","PE_init_U1571.data.in.0"], + ["_U1570.out","PE_init_U1571.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U1571.data.out"], + ["_U1572.out","PE_init_U1574.data.in.0"], + ["_U1573.out","PE_init_U1574.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U1574.data.out"], + ["_U1575.out","PE_init_U1577.data.in.0"], + ["_U1576.out","PE_init_U1577.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U1577.data.out"], + ["_U1578.out","PE_init_U1580.data.in.0"], + ["_U1579.out","PE_init_U1580.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U1580.data.out"], + ["_U1581.out","PE_init_U1583.data.in.0"], + ["_U1582.out","PE_init_U1583.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U1583.data.out"], + ["_U1584.out","PE_init_U1586.data.in.0"], + ["_U1585.out","PE_init_U1586.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U1586.data.out"], + ["_U1587.out","PE_init_U1589.data.in.0"], + ["_U1588.out","PE_init_U1589.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U1589.data.out"], + ["_U1590.out","PE_init_U1592.data.in.0"], + ["_U1591.out","PE_init_U1592.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U1592.data.out"], ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_input_host_stencil_op_hcompute_input_glb_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_output_cgra_stencil_10$inner_compute$mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957$binop.data.in.1","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile.json b/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile.json index 7f0b5f0f4..983b609bf 100644 --- a/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile.json +++ b/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile.json @@ -2,2207 +2,1941 @@ "namespaces":{ "global":{ "modules":{ - "aff__U114":{ + "aff__U105":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U132":{ + "add_all__U123":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U133":{ + "add_all__U124":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U134":{ + "add_all__U125":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U135":{ + "add_all__U126":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U136":{ + "add_all__U127":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U137":{ + "add_all__U128":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U138":{ + "add_all__U129":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U139":{ + "add_all__U130":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U115":{ + "coeff_0_U106":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U117":{ + "coeff_1_U108":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_2_U119":{ + "coeff_2_U110":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000658"]} }, - "coeff_3_U121":{ + "coeff_3_U112":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_4_U123":{ + "coeff_4_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006920"]} }, - "coeff_5_U125":{ + "coeff_5_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U127":{ + "coeff_6_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000003a"]} }, - "coeff_7_U129":{ + "coeff_7_U120":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000d24"]} }, - "const_term_U131":{ + "const_term_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U116":{ + "mul_d0__U107":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U118":{ + "mul_d1__U109":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U120":{ + "mul_d2__U111":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U122":{ + "mul_d3__U113":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U124":{ + "mul_d4__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U126":{ + "mul_d5__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U128":{ + "mul_d6__U119":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U130":{ + "mul_d7__U121":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U116.out","add_all__U132.in0"], - ["mul_d1__U118.out","add_all__U132.in1"], - ["add_all__U133.in0","add_all__U132.out"], - ["mul_d2__U120.out","add_all__U133.in1"], - ["add_all__U134.in0","add_all__U133.out"], - ["mul_d3__U122.out","add_all__U134.in1"], - ["add_all__U135.in0","add_all__U134.out"], - ["mul_d4__U124.out","add_all__U135.in1"], - ["add_all__U136.in0","add_all__U135.out"], - ["mul_d5__U126.out","add_all__U136.in1"], - ["add_all__U137.in0","add_all__U136.out"], - ["mul_d6__U128.out","add_all__U137.in1"], - ["add_all__U138.in0","add_all__U137.out"], - ["mul_d7__U130.out","add_all__U138.in1"], - ["add_all__U139.in0","add_all__U138.out"], - ["const_term_U131.out","add_all__U139.in1"], - ["self.out","add_all__U139.out"], - ["mul_d0__U116.in0","coeff_0_U115.out"], - ["mul_d1__U118.in0","coeff_1_U117.out"], - ["mul_d2__U120.in0","coeff_2_U119.out"], - ["mul_d3__U122.in0","coeff_3_U121.out"], - ["mul_d4__U124.in0","coeff_4_U123.out"], - ["mul_d5__U126.in0","coeff_5_U125.out"], - ["mul_d6__U128.in0","coeff_6_U127.out"], - ["mul_d7__U130.in0","coeff_7_U129.out"], - ["self.d.0","mul_d0__U116.in1"], - ["self.d.1","mul_d1__U118.in1"], - ["self.d.2","mul_d2__U120.in1"], - ["self.d.3","mul_d3__U122.in1"], - ["self.d.4","mul_d4__U124.in1"], - ["self.d.5","mul_d5__U126.in1"], - ["self.d.6","mul_d6__U128.in1"], - ["self.d.7","mul_d7__U130.in1"] + ["mul_d0__U107.out","add_all__U123.in0"], + ["mul_d1__U109.out","add_all__U123.in1"], + ["add_all__U124.in0","add_all__U123.out"], + ["mul_d2__U111.out","add_all__U124.in1"], + ["add_all__U125.in0","add_all__U124.out"], + ["mul_d3__U113.out","add_all__U125.in1"], + ["add_all__U126.in0","add_all__U125.out"], + ["mul_d4__U115.out","add_all__U126.in1"], + ["add_all__U127.in0","add_all__U126.out"], + ["mul_d5__U117.out","add_all__U127.in1"], + ["add_all__U128.in0","add_all__U127.out"], + ["mul_d6__U119.out","add_all__U128.in1"], + ["add_all__U129.in0","add_all__U128.out"], + ["mul_d7__U121.out","add_all__U129.in1"], + ["add_all__U130.in0","add_all__U129.out"], + ["const_term_U122.out","add_all__U130.in1"], + ["self.out","add_all__U130.out"], + ["mul_d0__U107.in0","coeff_0_U106.out"], + ["mul_d1__U109.in0","coeff_1_U108.out"], + ["mul_d2__U111.in0","coeff_2_U110.out"], + ["mul_d3__U113.in0","coeff_3_U112.out"], + ["mul_d4__U115.in0","coeff_4_U114.out"], + ["mul_d5__U117.in0","coeff_5_U116.out"], + ["mul_d6__U119.in0","coeff_6_U118.out"], + ["mul_d7__U121.in0","coeff_7_U120.out"], + ["self.d.0","mul_d0__U107.in1"], + ["self.d.1","mul_d1__U109.in1"], + ["self.d.2","mul_d2__U111.in1"], + ["self.d.3","mul_d3__U113.in1"], + ["self.d.4","mul_d4__U115.in1"], + ["self.d.5","mul_d5__U117.in1"], + ["self.d.6","mul_d6__U119.in1"], + ["self.d.7","mul_d7__U121.in1"] ] }, - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000003a0"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U272":{ + "aff__U198":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U284":{ + "add_all__U210":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U285":{ + "add_all__U211":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U286":{ + "add_all__U212":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U287":{ + "add_all__U213":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U288":{ + "add_all__U214":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U273":{ + "coeff_0_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U275":{ + "coeff_1_U201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_2_U277":{ + "coeff_2_U203":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_3_U279":{ + "coeff_3_U205":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U281":{ + "coeff_4_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U283":{ + "const_term_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U274":{ + "mul_d0__U200":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U276":{ + "mul_d1__U202":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U278":{ + "mul_d2__U204":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U280":{ + "mul_d3__U206":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U282":{ + "mul_d4__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U274.out","add_all__U284.in0"], - ["mul_d1__U276.out","add_all__U284.in1"], - ["add_all__U285.in0","add_all__U284.out"], - ["mul_d2__U278.out","add_all__U285.in1"], - ["add_all__U286.in0","add_all__U285.out"], - ["mul_d3__U280.out","add_all__U286.in1"], - ["add_all__U287.in0","add_all__U286.out"], - ["mul_d4__U282.out","add_all__U287.in1"], - ["add_all__U288.in0","add_all__U287.out"], - ["const_term_U283.out","add_all__U288.in1"], - ["self.out","add_all__U288.out"], - ["mul_d0__U274.in0","coeff_0_U273.out"], - ["mul_d1__U276.in0","coeff_1_U275.out"], - ["mul_d2__U278.in0","coeff_2_U277.out"], - ["mul_d3__U280.in0","coeff_3_U279.out"], - ["mul_d4__U282.in0","coeff_4_U281.out"], - ["self.d.0","mul_d0__U274.in1"], - ["self.d.1","mul_d1__U276.in1"], - ["self.d.2","mul_d2__U278.in1"], - ["self.d.3","mul_d3__U280.in1"], - ["self.d.4","mul_d4__U282.in1"] + ["mul_d0__U200.out","add_all__U210.in0"], + ["mul_d1__U202.out","add_all__U210.in1"], + ["add_all__U211.in0","add_all__U210.out"], + ["mul_d2__U204.out","add_all__U211.in1"], + ["add_all__U212.in0","add_all__U211.out"], + ["mul_d3__U206.out","add_all__U212.in1"], + ["add_all__U213.in0","add_all__U212.out"], + ["mul_d4__U208.out","add_all__U213.in1"], + ["add_all__U214.in0","add_all__U213.out"], + ["const_term_U209.out","add_all__U214.in1"], + ["self.out","add_all__U214.out"], + ["mul_d0__U200.in0","coeff_0_U199.out"], + ["mul_d1__U202.in0","coeff_1_U201.out"], + ["mul_d2__U204.in0","coeff_2_U203.out"], + ["mul_d3__U206.in0","coeff_3_U205.out"], + ["mul_d4__U208.in0","coeff_4_U207.out"], + ["self.d.0","mul_d0__U200.in1"], + ["self.d.1","mul_d1__U202.in1"], + ["self.d.2","mul_d2__U204.in1"], + ["self.d.3","mul_d3__U206.in1"], + ["self.d.4","mul_d4__U208.in1"] ] }, - "aff__U302":{ + "aff__U228":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U303":{ + "coeff_0_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U305":{ + "coeff_1_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U307":{ + "coeff_2_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U309":{ + "coeff_3_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U311":{ + "coeff_4_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000090"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U304":{ + "mul_d0__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U306":{ + "mul_d1__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U308":{ + "mul_d2__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U310":{ + "mul_d3__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U312":{ + "mul_d4__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U304.out","add_all__U314.in0"], - ["mul_d1__U306.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U308.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U310.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U312.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["const_term_U313.out","add_all__U318.in1"], - ["self.out","add_all__U318.out"], - ["mul_d0__U304.in0","coeff_0_U303.out"], - ["mul_d1__U306.in0","coeff_1_U305.out"], - ["mul_d2__U308.in0","coeff_2_U307.out"], - ["mul_d3__U310.in0","coeff_3_U309.out"], - ["mul_d4__U312.in0","coeff_4_U311.out"], - ["self.d.0","mul_d0__U304.in1"], - ["self.d.1","mul_d1__U306.in1"], - ["self.d.2","mul_d2__U308.in1"], - ["self.d.3","mul_d3__U310.in1"], - ["self.d.4","mul_d4__U312.in1"] + ["mul_d0__U230.out","add_all__U240.in0"], + ["mul_d1__U232.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U234.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U236.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U238.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["const_term_U239.out","add_all__U244.in1"], + ["self.out","add_all__U244.out"], + ["mul_d0__U230.in0","coeff_0_U229.out"], + ["mul_d1__U232.in0","coeff_1_U231.out"], + ["mul_d2__U234.in0","coeff_2_U233.out"], + ["mul_d3__U236.in0","coeff_3_U235.out"], + ["mul_d4__U238.in0","coeff_4_U237.out"], + ["self.d.0","mul_d0__U230.in1"], + ["self.d.1","mul_d1__U232.in1"], + ["self.d.2","mul_d2__U234.in1"], + ["self.d.3","mul_d3__U236.in1"], + ["self.d.4","mul_d4__U238.in1"] ] }, - "aff__U321":{ + "aff__U247":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U341":{ + "add_all__U267":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U342":{ + "add_all__U268":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U343":{ + "add_all__U269":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U344":{ + "add_all__U270":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U345":{ + "add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U346":{ + "add_all__U272":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U347":{ + "add_all__U273":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U348":{ + "add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U349":{ + "add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U322":{ + "coeff_0_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U324":{ + "coeff_1_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U326":{ + "coeff_2_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U328":{ + "coeff_3_U254":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U330":{ + "coeff_4_U256":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U332":{ + "coeff_5_U258":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000c0"]} }, - "coeff_6_U334":{ + "coeff_6_U260":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_7_U336":{ + "coeff_7_U262":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_8_U338":{ + "coeff_8_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U340":{ + "const_term_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U323":{ + "mul_d0__U249":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U325":{ + "mul_d1__U251":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U327":{ + "mul_d2__U253":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U329":{ + "mul_d3__U255":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U331":{ + "mul_d4__U257":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U333":{ + "mul_d5__U259":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U335":{ + "mul_d6__U261":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U337":{ + "mul_d7__U263":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U339":{ + "mul_d8__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U323.out","add_all__U341.in0"], - ["mul_d1__U325.out","add_all__U341.in1"], - ["add_all__U342.in0","add_all__U341.out"], - ["mul_d2__U327.out","add_all__U342.in1"], - ["add_all__U343.in0","add_all__U342.out"], - ["mul_d3__U329.out","add_all__U343.in1"], - ["add_all__U344.in0","add_all__U343.out"], - ["mul_d4__U331.out","add_all__U344.in1"], - ["add_all__U345.in0","add_all__U344.out"], - ["mul_d5__U333.out","add_all__U345.in1"], - ["add_all__U346.in0","add_all__U345.out"], - ["mul_d6__U335.out","add_all__U346.in1"], - ["add_all__U347.in0","add_all__U346.out"], - ["mul_d7__U337.out","add_all__U347.in1"], - ["add_all__U348.in0","add_all__U347.out"], - ["mul_d8__U339.out","add_all__U348.in1"], - ["add_all__U349.in0","add_all__U348.out"], - ["const_term_U340.out","add_all__U349.in1"], - ["self.out","add_all__U349.out"], - ["mul_d0__U323.in0","coeff_0_U322.out"], - ["mul_d1__U325.in0","coeff_1_U324.out"], - ["mul_d2__U327.in0","coeff_2_U326.out"], - ["mul_d3__U329.in0","coeff_3_U328.out"], - ["mul_d4__U331.in0","coeff_4_U330.out"], - ["mul_d5__U333.in0","coeff_5_U332.out"], - ["mul_d6__U335.in0","coeff_6_U334.out"], - ["mul_d7__U337.in0","coeff_7_U336.out"], - ["mul_d8__U339.in0","coeff_8_U338.out"], - ["self.d.0","mul_d0__U323.in1"], - ["self.d.1","mul_d1__U325.in1"], - ["self.d.2","mul_d2__U327.in1"], - ["self.d.3","mul_d3__U329.in1"], - ["self.d.4","mul_d4__U331.in1"], - ["self.d.5","mul_d5__U333.in1"], - ["self.d.6","mul_d6__U335.in1"], - ["self.d.7","mul_d7__U337.in1"], - ["self.d.8","mul_d8__U339.in1"] + ["mul_d0__U249.out","add_all__U267.in0"], + ["mul_d1__U251.out","add_all__U267.in1"], + ["add_all__U268.in0","add_all__U267.out"], + ["mul_d2__U253.out","add_all__U268.in1"], + ["add_all__U269.in0","add_all__U268.out"], + ["mul_d3__U255.out","add_all__U269.in1"], + ["add_all__U270.in0","add_all__U269.out"], + ["mul_d4__U257.out","add_all__U270.in1"], + ["add_all__U271.in0","add_all__U270.out"], + ["mul_d5__U259.out","add_all__U271.in1"], + ["add_all__U272.in0","add_all__U271.out"], + ["mul_d6__U261.out","add_all__U272.in1"], + ["add_all__U273.in0","add_all__U272.out"], + ["mul_d7__U263.out","add_all__U273.in1"], + ["add_all__U274.in0","add_all__U273.out"], + ["mul_d8__U265.out","add_all__U274.in1"], + ["add_all__U275.in0","add_all__U274.out"], + ["const_term_U266.out","add_all__U275.in1"], + ["self.out","add_all__U275.out"], + ["mul_d0__U249.in0","coeff_0_U248.out"], + ["mul_d1__U251.in0","coeff_1_U250.out"], + ["mul_d2__U253.in0","coeff_2_U252.out"], + ["mul_d3__U255.in0","coeff_3_U254.out"], + ["mul_d4__U257.in0","coeff_4_U256.out"], + ["mul_d5__U259.in0","coeff_5_U258.out"], + ["mul_d6__U261.in0","coeff_6_U260.out"], + ["mul_d7__U263.in0","coeff_7_U262.out"], + ["mul_d8__U265.in0","coeff_8_U264.out"], + ["self.d.0","mul_d0__U249.in1"], + ["self.d.1","mul_d1__U251.in1"], + ["self.d.2","mul_d2__U253.in1"], + ["self.d.3","mul_d3__U255.in1"], + ["self.d.4","mul_d4__U257.in1"], + ["self.d.5","mul_d5__U259.in1"], + ["self.d.6","mul_d6__U261.in1"], + ["self.d.7","mul_d7__U263.in1"], + ["self.d.8","mul_d8__U265.in1"] ] }, - "aff__U389":{ + "aff__U315":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U409":{ + "add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U410":{ + "add_all__U336":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U411":{ + "add_all__U337":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U412":{ + "add_all__U338":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U413":{ + "add_all__U339":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U414":{ + "add_all__U340":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U415":{ + "add_all__U341":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U342":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U343":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U390":{ + "coeff_0_U316":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U392":{ + "coeff_1_U318":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U394":{ + "coeff_2_U320":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_3_U396":{ + "coeff_3_U322":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_4_U398":{ + "coeff_4_U324":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000480"]} }, - "coeff_5_U400":{ + "coeff_5_U326":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U402":{ + "coeff_6_U328":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_7_U404":{ + "coeff_7_U330":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_8_U406":{ + "coeff_8_U332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000090"]} }, - "const_term_U408":{ + "const_term_U334":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U391":{ + "mul_d0__U317":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U393":{ + "mul_d1__U319":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U395":{ + "mul_d2__U321":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U397":{ + "mul_d3__U323":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U399":{ + "mul_d4__U325":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U401":{ + "mul_d5__U327":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U403":{ + "mul_d6__U329":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U405":{ + "mul_d7__U331":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U407":{ + "mul_d8__U333":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U391.out","add_all__U409.in0"], - ["mul_d1__U393.out","add_all__U409.in1"], - ["add_all__U410.in0","add_all__U409.out"], - ["mul_d2__U395.out","add_all__U410.in1"], - ["add_all__U411.in0","add_all__U410.out"], - ["mul_d3__U397.out","add_all__U411.in1"], - ["add_all__U412.in0","add_all__U411.out"], - ["mul_d4__U399.out","add_all__U412.in1"], - ["add_all__U413.in0","add_all__U412.out"], - ["mul_d5__U401.out","add_all__U413.in1"], - ["add_all__U414.in0","add_all__U413.out"], - ["mul_d6__U403.out","add_all__U414.in1"], - ["add_all__U415.in0","add_all__U414.out"], - ["mul_d7__U405.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d8__U407.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["const_term_U408.out","add_all__U417.in1"], - ["self.out","add_all__U417.out"], - ["mul_d0__U391.in0","coeff_0_U390.out"], - ["mul_d1__U393.in0","coeff_1_U392.out"], - ["mul_d2__U395.in0","coeff_2_U394.out"], - ["mul_d3__U397.in0","coeff_3_U396.out"], - ["mul_d4__U399.in0","coeff_4_U398.out"], - ["mul_d5__U401.in0","coeff_5_U400.out"], - ["mul_d6__U403.in0","coeff_6_U402.out"], - ["mul_d7__U405.in0","coeff_7_U404.out"], - ["mul_d8__U407.in0","coeff_8_U406.out"], - ["self.d.0","mul_d0__U391.in1"], - ["self.d.1","mul_d1__U393.in1"], - ["self.d.2","mul_d2__U395.in1"], - ["self.d.3","mul_d3__U397.in1"], - ["self.d.4","mul_d4__U399.in1"], - ["self.d.5","mul_d5__U401.in1"], - ["self.d.6","mul_d6__U403.in1"], - ["self.d.7","mul_d7__U405.in1"], - ["self.d.8","mul_d8__U407.in1"] + ["mul_d0__U317.out","add_all__U335.in0"], + ["mul_d1__U319.out","add_all__U335.in1"], + ["add_all__U336.in0","add_all__U335.out"], + ["mul_d2__U321.out","add_all__U336.in1"], + ["add_all__U337.in0","add_all__U336.out"], + ["mul_d3__U323.out","add_all__U337.in1"], + ["add_all__U338.in0","add_all__U337.out"], + ["mul_d4__U325.out","add_all__U338.in1"], + ["add_all__U339.in0","add_all__U338.out"], + ["mul_d5__U327.out","add_all__U339.in1"], + ["add_all__U340.in0","add_all__U339.out"], + ["mul_d6__U329.out","add_all__U340.in1"], + ["add_all__U341.in0","add_all__U340.out"], + ["mul_d7__U331.out","add_all__U341.in1"], + ["add_all__U342.in0","add_all__U341.out"], + ["mul_d8__U333.out","add_all__U342.in1"], + ["add_all__U343.in0","add_all__U342.out"], + ["const_term_U334.out","add_all__U343.in1"], + ["self.out","add_all__U343.out"], + ["mul_d0__U317.in0","coeff_0_U316.out"], + ["mul_d1__U319.in0","coeff_1_U318.out"], + ["mul_d2__U321.in0","coeff_2_U320.out"], + ["mul_d3__U323.in0","coeff_3_U322.out"], + ["mul_d4__U325.in0","coeff_4_U324.out"], + ["mul_d5__U327.in0","coeff_5_U326.out"], + ["mul_d6__U329.in0","coeff_6_U328.out"], + ["mul_d7__U331.in0","coeff_7_U330.out"], + ["mul_d8__U333.in0","coeff_8_U332.out"], + ["self.d.0","mul_d0__U317.in1"], + ["self.d.1","mul_d1__U319.in1"], + ["self.d.2","mul_d2__U321.in1"], + ["self.d.3","mul_d3__U323.in1"], + ["self.d.4","mul_d4__U325.in1"], + ["self.d.5","mul_d5__U327.in1"], + ["self.d.6","mul_d6__U329.in1"], + ["self.d.7","mul_d7__U331.in1"], + ["self.d.8","mul_d8__U333.in1"] ] }, - "aff__U41":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U51":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U52":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U53":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U42":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U44":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U46":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000003a"]} }, - "coeff_3_U48":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000d24"]} }, - "const_term_U50":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U43":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U422":{ + "aff__U348":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U428":{ + "add_all__U354":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U429":{ + "add_all__U355":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U423":{ + "coeff_0_U349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U425":{ + "coeff_1_U351":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U427":{ + "const_term_U353":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U424":{ + "mul_d0__U350":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U426":{ + "mul_d1__U352":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U424.out","add_all__U428.in0"], - ["mul_d1__U426.out","add_all__U428.in1"], - ["add_all__U429.in0","add_all__U428.out"], - ["const_term_U427.out","add_all__U429.in1"], - ["self.out","add_all__U429.out"], - ["mul_d0__U424.in0","coeff_0_U423.out"], - ["mul_d1__U426.in0","coeff_1_U425.out"], - ["self.d.0","mul_d0__U424.in1"], - ["self.d.1","mul_d1__U426.in1"] + ["mul_d0__U350.out","add_all__U354.in0"], + ["mul_d1__U352.out","add_all__U354.in1"], + ["add_all__U355.in0","add_all__U354.out"], + ["const_term_U353.out","add_all__U355.in1"], + ["self.out","add_all__U355.out"], + ["mul_d0__U350.in0","coeff_0_U349.out"], + ["mul_d1__U352.in0","coeff_1_U351.out"], + ["self.d.0","mul_d0__U350.in1"], + ["self.d.1","mul_d1__U352.in1"] ] }, - "aff__U437":{ + "aff__U362":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U443":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U444":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U442":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U439":{ + "mul_d0__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U443.in0"], - ["mul_d1__U441.out","add_all__U443.in1"], - ["add_all__U444.in0","add_all__U443.out"], - ["const_term_U442.out","add_all__U444.in1"], - ["self.out","add_all__U444.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"] + ["mul_d0__U364.out","add_all__U368.in0"], + ["mul_d1__U366.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["const_term_U367.out","add_all__U369.in1"], + ["self.out","add_all__U369.out"], + ["mul_d0__U364.in0","coeff_0_U363.out"], + ["mul_d1__U366.in0","coeff_1_U365.out"], + ["self.d.0","mul_d0__U364.in1"], + ["self.d.1","mul_d1__U366.in1"] ] }, - "aff__U452":{ + "aff__U376":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U458":{ + "add_all__U382":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U459":{ + "add_all__U383":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U453":{ + "coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U455":{ + "coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U457":{ + "const_term_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U454":{ + "mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U456":{ + "mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U454.out","add_all__U458.in0"], - ["mul_d1__U456.out","add_all__U458.in1"], - ["add_all__U459.in0","add_all__U458.out"], - ["const_term_U457.out","add_all__U459.in1"], - ["self.out","add_all__U459.out"], - ["mul_d0__U454.in0","coeff_0_U453.out"], - ["mul_d1__U456.in0","coeff_1_U455.out"], - ["self.d.0","mul_d0__U454.in1"], - ["self.d.1","mul_d1__U456.in1"] + ["mul_d0__U378.out","add_all__U382.in0"], + ["mul_d1__U380.out","add_all__U382.in1"], + ["add_all__U383.in0","add_all__U382.out"], + ["const_term_U381.out","add_all__U383.in1"], + ["self.out","add_all__U383.out"], + ["mul_d0__U378.in0","coeff_0_U377.out"], + ["mul_d1__U380.in0","coeff_1_U379.out"], + ["self.d.0","mul_d0__U378.in1"], + ["self.d.1","mul_d1__U380.in1"] ] }, - "aff__U467":{ + "aff__U390":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U473":{ + "add_all__U396":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U474":{ + "add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U468":{ + "coeff_0_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U470":{ + "coeff_1_U393":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U472":{ + "const_term_U395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U469":{ + "mul_d0__U392":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U471":{ + "mul_d1__U394":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U469.out","add_all__U473.in0"], - ["mul_d1__U471.out","add_all__U473.in1"], - ["add_all__U474.in0","add_all__U473.out"], - ["const_term_U472.out","add_all__U474.in1"], - ["self.out","add_all__U474.out"], - ["mul_d0__U469.in0","coeff_0_U468.out"], - ["mul_d1__U471.in0","coeff_1_U470.out"], - ["self.d.0","mul_d0__U469.in1"], - ["self.d.1","mul_d1__U471.in1"] + ["mul_d0__U392.out","add_all__U396.in0"], + ["mul_d1__U394.out","add_all__U396.in1"], + ["add_all__U397.in0","add_all__U396.out"], + ["const_term_U395.out","add_all__U397.in1"], + ["self.out","add_all__U397.out"], + ["mul_d0__U392.in0","coeff_0_U391.out"], + ["mul_d1__U394.in0","coeff_1_U393.out"], + ["self.d.0","mul_d0__U392.in1"], + ["self.d.1","mul_d1__U394.in1"] ] }, - "aff__U482":{ + "aff__U404":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U488":{ + "add_all__U410":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U489":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U405":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U407":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U487":{ + "const_term_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U484":{ + "mul_d0__U406":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U408":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U488.in0"], - ["mul_d1__U486.out","add_all__U488.in1"], - ["add_all__U489.in0","add_all__U488.out"], - ["const_term_U487.out","add_all__U489.in1"], - ["self.out","add_all__U489.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"] + ["mul_d0__U406.out","add_all__U410.in0"], + ["mul_d1__U408.out","add_all__U410.in1"], + ["add_all__U411.in0","add_all__U410.out"], + ["const_term_U409.out","add_all__U411.in1"], + ["self.out","add_all__U411.out"], + ["mul_d0__U406.in0","coeff_0_U405.out"], + ["mul_d1__U408.in0","coeff_1_U407.out"], + ["self.d.0","mul_d0__U406.in1"], + ["self.d.1","mul_d1__U408.in1"] ] }, - "aff__U497":{ + "aff__U418":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U503":{ + "add_all__U424":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U504":{ + "add_all__U425":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U498":{ + "coeff_0_U419":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U500":{ + "coeff_1_U421":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U502":{ + "const_term_U423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U499":{ + "mul_d0__U420":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U501":{ + "mul_d1__U422":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U499.out","add_all__U503.in0"], - ["mul_d1__U501.out","add_all__U503.in1"], - ["add_all__U504.in0","add_all__U503.out"], - ["const_term_U502.out","add_all__U504.in1"], - ["self.out","add_all__U504.out"], - ["mul_d0__U499.in0","coeff_0_U498.out"], - ["mul_d1__U501.in0","coeff_1_U500.out"], - ["self.d.0","mul_d0__U499.in1"], - ["self.d.1","mul_d1__U501.in1"] + ["mul_d0__U420.out","add_all__U424.in0"], + ["mul_d1__U422.out","add_all__U424.in1"], + ["add_all__U425.in0","add_all__U424.out"], + ["const_term_U423.out","add_all__U425.in1"], + ["self.out","add_all__U425.out"], + ["mul_d0__U420.in0","coeff_0_U419.out"], + ["mul_d1__U422.in0","coeff_1_U421.out"], + ["self.d.0","mul_d0__U420.in1"], + ["self.d.1","mul_d1__U422.in1"] ] }, - "aff__U512":{ + "aff__U432":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U518":{ + "add_all__U438":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U519":{ + "add_all__U439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U513":{ + "coeff_0_U433":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U515":{ + "coeff_1_U435":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U517":{ + "const_term_U437":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U514":{ + "mul_d0__U434":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U516":{ + "mul_d1__U436":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U514.out","add_all__U518.in0"], - ["mul_d1__U516.out","add_all__U518.in1"], - ["add_all__U519.in0","add_all__U518.out"], - ["const_term_U517.out","add_all__U519.in1"], - ["self.out","add_all__U519.out"], - ["mul_d0__U514.in0","coeff_0_U513.out"], - ["mul_d1__U516.in0","coeff_1_U515.out"], - ["self.d.0","mul_d0__U514.in1"], - ["self.d.1","mul_d1__U516.in1"] + ["mul_d0__U434.out","add_all__U438.in0"], + ["mul_d1__U436.out","add_all__U438.in1"], + ["add_all__U439.in0","add_all__U438.out"], + ["const_term_U437.out","add_all__U439.in1"], + ["self.out","add_all__U439.out"], + ["mul_d0__U434.in0","coeff_0_U433.out"], + ["mul_d1__U436.in0","coeff_1_U435.out"], + ["self.d.0","mul_d0__U434.in1"], + ["self.d.1","mul_d1__U436.in1"] ] }, - "aff__U527":{ + "aff__U446":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U533":{ + "add_all__U452":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U534":{ + "add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U528":{ + "coeff_0_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U530":{ + "coeff_1_U449":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U532":{ + "const_term_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U529":{ + "mul_d0__U448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U531":{ + "mul_d1__U450":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U529.out","add_all__U533.in0"], - ["mul_d1__U531.out","add_all__U533.in1"], - ["add_all__U534.in0","add_all__U533.out"], - ["const_term_U532.out","add_all__U534.in1"], - ["self.out","add_all__U534.out"], - ["mul_d0__U529.in0","coeff_0_U528.out"], - ["mul_d1__U531.in0","coeff_1_U530.out"], - ["self.d.0","mul_d0__U529.in1"], - ["self.d.1","mul_d1__U531.in1"] + ["mul_d0__U448.out","add_all__U452.in0"], + ["mul_d1__U450.out","add_all__U452.in1"], + ["add_all__U453.in0","add_all__U452.out"], + ["const_term_U451.out","add_all__U453.in1"], + ["self.out","add_all__U453.out"], + ["mul_d0__U448.in0","coeff_0_U447.out"], + ["mul_d1__U450.in0","coeff_1_U449.out"], + ["self.d.0","mul_d0__U448.in1"], + ["self.d.1","mul_d1__U450.in1"] ] }, - "aff__U542":{ + "aff__U459":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U558":{ + "add_all__U475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U559":{ + "add_all__U476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U560":{ + "add_all__U477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U561":{ + "add_all__U478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U562":{ + "add_all__U479":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U563":{ + "add_all__U480":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U564":{ + "add_all__U481":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U543":{ + "coeff_0_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U545":{ + "coeff_1_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U547":{ + "coeff_2_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U549":{ + "coeff_3_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U551":{ + "coeff_4_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "coeff_5_U553":{ + "coeff_5_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_6_U555":{ + "coeff_6_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U557":{ + "const_term_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012d60"]} }, - "mul_d0__U544":{ + "mul_d0__U461":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U546":{ + "mul_d1__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U548":{ + "mul_d2__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U550":{ + "mul_d3__U467":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U552":{ + "mul_d4__U469":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U554":{ + "mul_d5__U471":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U556":{ + "mul_d6__U473":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U544.out","add_all__U558.in0"], - ["mul_d1__U546.out","add_all__U558.in1"], - ["add_all__U559.in0","add_all__U558.out"], - ["mul_d2__U548.out","add_all__U559.in1"], - ["add_all__U560.in0","add_all__U559.out"], - ["mul_d3__U550.out","add_all__U560.in1"], - ["add_all__U561.in0","add_all__U560.out"], - ["mul_d4__U552.out","add_all__U561.in1"], - ["add_all__U562.in0","add_all__U561.out"], - ["mul_d5__U554.out","add_all__U562.in1"], - ["add_all__U563.in0","add_all__U562.out"], - ["mul_d6__U556.out","add_all__U563.in1"], - ["add_all__U564.in0","add_all__U563.out"], - ["const_term_U557.out","add_all__U564.in1"], - ["self.out","add_all__U564.out"], - ["mul_d0__U544.in0","coeff_0_U543.out"], - ["mul_d1__U546.in0","coeff_1_U545.out"], - ["mul_d2__U548.in0","coeff_2_U547.out"], - ["mul_d3__U550.in0","coeff_3_U549.out"], - ["mul_d4__U552.in0","coeff_4_U551.out"], - ["mul_d5__U554.in0","coeff_5_U553.out"], - ["mul_d6__U556.in0","coeff_6_U555.out"], - ["self.d.0","mul_d0__U544.in1"], - ["self.d.1","mul_d1__U546.in1"], - ["self.d.2","mul_d2__U548.in1"], - ["self.d.3","mul_d3__U550.in1"], - ["self.d.4","mul_d4__U552.in1"], - ["self.d.5","mul_d5__U554.in1"], - ["self.d.6","mul_d6__U556.in1"] + ["mul_d0__U461.out","add_all__U475.in0"], + ["mul_d1__U463.out","add_all__U475.in1"], + ["add_all__U476.in0","add_all__U475.out"], + ["mul_d2__U465.out","add_all__U476.in1"], + ["add_all__U477.in0","add_all__U476.out"], + ["mul_d3__U467.out","add_all__U477.in1"], + ["add_all__U478.in0","add_all__U477.out"], + ["mul_d4__U469.out","add_all__U478.in1"], + ["add_all__U479.in0","add_all__U478.out"], + ["mul_d5__U471.out","add_all__U479.in1"], + ["add_all__U480.in0","add_all__U479.out"], + ["mul_d6__U473.out","add_all__U480.in1"], + ["add_all__U481.in0","add_all__U480.out"], + ["const_term_U474.out","add_all__U481.in1"], + ["self.out","add_all__U481.out"], + ["mul_d0__U461.in0","coeff_0_U460.out"], + ["mul_d1__U463.in0","coeff_1_U462.out"], + ["mul_d2__U465.in0","coeff_2_U464.out"], + ["mul_d3__U467.in0","coeff_3_U466.out"], + ["mul_d4__U469.in0","coeff_4_U468.out"], + ["mul_d5__U471.in0","coeff_5_U470.out"], + ["mul_d6__U473.in0","coeff_6_U472.out"], + ["self.d.0","mul_d0__U461.in1"], + ["self.d.1","mul_d1__U463.in1"], + ["self.d.2","mul_d2__U465.in1"], + ["self.d.3","mul_d3__U467.in1"], + ["self.d.4","mul_d4__U469.in1"], + ["self.d.5","mul_d5__U471.in1"], + ["self.d.6","mul_d6__U473.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U77":{ + "add_all__U68":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U78":{ + "add_all__U69":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U79":{ + "add_all__U70":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U80":{ + "add_all__U71":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U81":{ + "add_all__U72":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U82":{ + "add_all__U73":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000f0"]} }, - "coeff_6_U70":{ + "coeff_6_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U72":{ + "coeff_7_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U74":{ + "const_term_U65":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U71":{ + "mul_d6__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U73":{ + "mul_d7__U64":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U75.in0"], - ["mul_d1__U61.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["mul_d2__U63.out","add_all__U76.in1"], - ["add_all__U77.in0","add_all__U76.out"], - ["mul_d3__U65.out","add_all__U77.in1"], - ["add_all__U78.in0","add_all__U77.out"], - ["mul_d4__U67.out","add_all__U78.in1"], - ["add_all__U79.in0","add_all__U78.out"], - ["mul_d5__U69.out","add_all__U79.in1"], - ["add_all__U80.in0","add_all__U79.out"], - ["mul_d6__U71.out","add_all__U80.in1"], - ["add_all__U81.in0","add_all__U80.out"], - ["mul_d7__U73.out","add_all__U81.in1"], - ["add_all__U82.in0","add_all__U81.out"], - ["const_term_U74.out","add_all__U82.in1"], - ["self.out","add_all__U82.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["mul_d6__U71.in0","coeff_6_U70.out"], - ["mul_d7__U73.in0","coeff_7_U72.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"], - ["self.d.6","mul_d6__U71.in1"], - ["self.d.7","mul_d7__U73.in1"] + ["mul_d0__U50.out","add_all__U66.in0"], + ["mul_d1__U52.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["mul_d2__U54.out","add_all__U67.in1"], + ["add_all__U68.in0","add_all__U67.out"], + ["mul_d3__U56.out","add_all__U68.in1"], + ["add_all__U69.in0","add_all__U68.out"], + ["mul_d4__U58.out","add_all__U69.in1"], + ["add_all__U70.in0","add_all__U69.out"], + ["mul_d5__U60.out","add_all__U70.in1"], + ["add_all__U71.in0","add_all__U70.out"], + ["mul_d6__U62.out","add_all__U71.in1"], + ["add_all__U72.in0","add_all__U71.out"], + ["mul_d7__U64.out","add_all__U72.in1"], + ["add_all__U73.in0","add_all__U72.out"], + ["const_term_U65.out","add_all__U73.in1"], + ["self.out","add_all__U73.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["mul_d6__U62.in0","coeff_6_U61.out"], + ["mul_d7__U64.in0","coeff_7_U63.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"], + ["self.d.6","mul_d6__U62.in1"], + ["self.d.7","mul_d7__U64.in1"] ] }, - "aff__U589":{ + "aff__U506":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U605":{ + "add_all__U522":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U606":{ + "add_all__U523":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U607":{ + "add_all__U524":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U608":{ + "add_all__U525":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U609":{ + "add_all__U526":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U610":{ + "add_all__U527":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U611":{ + "add_all__U528":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U590":{ + "coeff_0_U507":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U592":{ + "coeff_1_U509":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_2_U594":{ + "coeff_2_U511":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_3_U596":{ + "coeff_3_U513":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006200"]} }, - "coeff_4_U598":{ + "coeff_4_U515":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_5_U600":{ + "coeff_5_U517":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000038"]} }, - "coeff_6_U602":{ + "coeff_6_U519":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c40"]} }, - "const_term_U604":{ + "const_term_U521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U591":{ + "mul_d0__U508":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U593":{ + "mul_d1__U510":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U595":{ + "mul_d2__U512":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U597":{ + "mul_d3__U514":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U599":{ + "mul_d4__U516":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U601":{ + "mul_d5__U518":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U603":{ + "mul_d6__U520":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U591.out","add_all__U605.in0"], - ["mul_d1__U593.out","add_all__U605.in1"], - ["add_all__U606.in0","add_all__U605.out"], - ["mul_d2__U595.out","add_all__U606.in1"], - ["add_all__U607.in0","add_all__U606.out"], - ["mul_d3__U597.out","add_all__U607.in1"], - ["add_all__U608.in0","add_all__U607.out"], - ["mul_d4__U599.out","add_all__U608.in1"], - ["add_all__U609.in0","add_all__U608.out"], - ["mul_d5__U601.out","add_all__U609.in1"], - ["add_all__U610.in0","add_all__U609.out"], - ["mul_d6__U603.out","add_all__U610.in1"], - ["add_all__U611.in0","add_all__U610.out"], - ["const_term_U604.out","add_all__U611.in1"], - ["self.out","add_all__U611.out"], - ["mul_d0__U591.in0","coeff_0_U590.out"], - ["mul_d1__U593.in0","coeff_1_U592.out"], - ["mul_d2__U595.in0","coeff_2_U594.out"], - ["mul_d3__U597.in0","coeff_3_U596.out"], - ["mul_d4__U599.in0","coeff_4_U598.out"], - ["mul_d5__U601.in0","coeff_5_U600.out"], - ["mul_d6__U603.in0","coeff_6_U602.out"], - ["self.d.0","mul_d0__U591.in1"], - ["self.d.1","mul_d1__U593.in1"], - ["self.d.2","mul_d2__U595.in1"], - ["self.d.3","mul_d3__U597.in1"], - ["self.d.4","mul_d4__U599.in1"], - ["self.d.5","mul_d5__U601.in1"], - ["self.d.6","mul_d6__U603.in1"] + ["mul_d0__U508.out","add_all__U522.in0"], + ["mul_d1__U510.out","add_all__U522.in1"], + ["add_all__U523.in0","add_all__U522.out"], + ["mul_d2__U512.out","add_all__U523.in1"], + ["add_all__U524.in0","add_all__U523.out"], + ["mul_d3__U514.out","add_all__U524.in1"], + ["add_all__U525.in0","add_all__U524.out"], + ["mul_d4__U516.out","add_all__U525.in1"], + ["add_all__U526.in0","add_all__U525.out"], + ["mul_d5__U518.out","add_all__U526.in1"], + ["add_all__U527.in0","add_all__U526.out"], + ["mul_d6__U520.out","add_all__U527.in1"], + ["add_all__U528.in0","add_all__U527.out"], + ["const_term_U521.out","add_all__U528.in1"], + ["self.out","add_all__U528.out"], + ["mul_d0__U508.in0","coeff_0_U507.out"], + ["mul_d1__U510.in0","coeff_1_U509.out"], + ["mul_d2__U512.in0","coeff_2_U511.out"], + ["mul_d3__U514.in0","coeff_3_U513.out"], + ["mul_d4__U516.in0","coeff_4_U515.out"], + ["mul_d5__U518.in0","coeff_5_U517.out"], + ["mul_d6__U520.in0","coeff_6_U519.out"], + ["self.d.0","mul_d0__U508.in1"], + ["self.d.1","mul_d1__U510.in1"], + ["self.d.2","mul_d2__U512.in1"], + ["self.d.3","mul_d3__U514.in1"], + ["self.d.4","mul_d4__U516.in1"], + ["self.d.5","mul_d5__U518.in1"], + ["self.d.6","mul_d6__U520.in1"] ] }, - "aff__U614":{ + "aff__U531":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U624":{ + "add_all__U541":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U625":{ + "add_all__U542":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U626":{ + "add_all__U543":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U627":{ + "add_all__U544":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U615":{ + "coeff_0_U532":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U617":{ + "coeff_1_U534":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U619":{ + "coeff_2_U536":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U621":{ + "coeff_3_U538":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U623":{ + "const_term_U540":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} }, - "mul_d0__U616":{ + "mul_d0__U533":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U618":{ + "mul_d1__U535":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U620":{ + "mul_d2__U537":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U622":{ + "mul_d3__U539":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U616.out","add_all__U624.in0"], - ["mul_d1__U618.out","add_all__U624.in1"], - ["add_all__U625.in0","add_all__U624.out"], - ["mul_d2__U620.out","add_all__U625.in1"], - ["add_all__U626.in0","add_all__U625.out"], - ["mul_d3__U622.out","add_all__U626.in1"], - ["add_all__U627.in0","add_all__U626.out"], - ["const_term_U623.out","add_all__U627.in1"], - ["self.out","add_all__U627.out"], - ["mul_d0__U616.in0","coeff_0_U615.out"], - ["mul_d1__U618.in0","coeff_1_U617.out"], - ["mul_d2__U620.in0","coeff_2_U619.out"], - ["mul_d3__U622.in0","coeff_3_U621.out"], - ["self.d.0","mul_d0__U616.in1"], - ["self.d.1","mul_d1__U618.in1"], - ["self.d.2","mul_d2__U620.in1"], - ["self.d.3","mul_d3__U622.in1"] + ["mul_d0__U533.out","add_all__U541.in0"], + ["mul_d1__U535.out","add_all__U541.in1"], + ["add_all__U542.in0","add_all__U541.out"], + ["mul_d2__U537.out","add_all__U542.in1"], + ["add_all__U543.in0","add_all__U542.out"], + ["mul_d3__U539.out","add_all__U543.in1"], + ["add_all__U544.in0","add_all__U543.out"], + ["const_term_U540.out","add_all__U544.in1"], + ["self.out","add_all__U544.out"], + ["mul_d0__U533.in0","coeff_0_U532.out"], + ["mul_d1__U535.in0","coeff_1_U534.out"], + ["mul_d2__U537.in0","coeff_2_U536.out"], + ["mul_d3__U539.in0","coeff_3_U538.out"], + ["self.d.0","mul_d0__U533.in1"], + ["self.d.1","mul_d1__U535.in1"], + ["self.d.2","mul_d2__U537.in1"], + ["self.d.3","mul_d3__U539.in1"] ] }, - "aff__U637":{ + "aff__U554":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U647":{ + "add_all__U564":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U648":{ + "add_all__U565":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U649":{ + "add_all__U566":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U650":{ + "add_all__U567":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U638":{ + "coeff_0_U555":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U640":{ + "coeff_1_U557":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U642":{ + "coeff_2_U559":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000038"]} }, - "coeff_3_U644":{ + "coeff_3_U561":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c40"]} }, - "const_term_U646":{ + "const_term_U563":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U639":{ + "mul_d0__U556":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U641":{ + "mul_d1__U558":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U643":{ + "mul_d2__U560":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U645":{ + "mul_d3__U562":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U639.out","add_all__U647.in0"], - ["mul_d1__U641.out","add_all__U647.in1"], - ["add_all__U648.in0","add_all__U647.out"], - ["mul_d2__U643.out","add_all__U648.in1"], - ["add_all__U649.in0","add_all__U648.out"], - ["mul_d3__U645.out","add_all__U649.in1"], - ["add_all__U650.in0","add_all__U649.out"], - ["const_term_U646.out","add_all__U650.in1"], - ["self.out","add_all__U650.out"], - ["mul_d0__U639.in0","coeff_0_U638.out"], - ["mul_d1__U641.in0","coeff_1_U640.out"], - ["mul_d2__U643.in0","coeff_2_U642.out"], - ["mul_d3__U645.in0","coeff_3_U644.out"], - ["self.d.0","mul_d0__U639.in1"], - ["self.d.1","mul_d1__U641.in1"], - ["self.d.2","mul_d2__U643.in1"], - ["self.d.3","mul_d3__U645.in1"] + ["mul_d0__U556.out","add_all__U564.in0"], + ["mul_d1__U558.out","add_all__U564.in1"], + ["add_all__U565.in0","add_all__U564.out"], + ["mul_d2__U560.out","add_all__U565.in1"], + ["add_all__U566.in0","add_all__U565.out"], + ["mul_d3__U562.out","add_all__U566.in1"], + ["add_all__U567.in0","add_all__U566.out"], + ["const_term_U563.out","add_all__U567.in1"], + ["self.out","add_all__U567.out"], + ["mul_d0__U556.in0","coeff_0_U555.out"], + ["mul_d1__U558.in0","coeff_1_U557.out"], + ["mul_d2__U560.in0","coeff_2_U559.out"], + ["mul_d3__U562.in0","coeff_3_U561.out"], + ["self.d.0","mul_d0__U556.in1"], + ["self.d.1","mul_d1__U558.in1"], + ["self.d.2","mul_d2__U560.in1"], + ["self.d.3","mul_d3__U562.in1"] ] }, - "aff__U654":{ + "aff__U571":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U664":{ + "add_all__U581":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U665":{ + "add_all__U582":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U666":{ + "add_all__U583":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U667":{ + "add_all__U584":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U655":{ + "coeff_0_U572":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U657":{ + "coeff_1_U574":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U659":{ + "coeff_2_U576":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U661":{ + "coeff_3_U578":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U663":{ + "const_term_U580":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} }, - "mul_d0__U656":{ + "mul_d0__U573":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U658":{ + "mul_d1__U575":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U660":{ + "mul_d2__U577":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U662":{ + "mul_d3__U579":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U656.out","add_all__U664.in0"], - ["mul_d1__U658.out","add_all__U664.in1"], - ["add_all__U665.in0","add_all__U664.out"], - ["mul_d2__U660.out","add_all__U665.in1"], - ["add_all__U666.in0","add_all__U665.out"], - ["mul_d3__U662.out","add_all__U666.in1"], - ["add_all__U667.in0","add_all__U666.out"], - ["const_term_U663.out","add_all__U667.in1"], - ["self.out","add_all__U667.out"], - ["mul_d0__U656.in0","coeff_0_U655.out"], - ["mul_d1__U658.in0","coeff_1_U657.out"], - ["mul_d2__U660.in0","coeff_2_U659.out"], - ["mul_d3__U662.in0","coeff_3_U661.out"], - ["self.d.0","mul_d0__U656.in1"], - ["self.d.1","mul_d1__U658.in1"], - ["self.d.2","mul_d2__U660.in1"], - ["self.d.3","mul_d3__U662.in1"] + ["mul_d0__U573.out","add_all__U581.in0"], + ["mul_d1__U575.out","add_all__U581.in1"], + ["add_all__U582.in0","add_all__U581.out"], + ["mul_d2__U577.out","add_all__U582.in1"], + ["add_all__U583.in0","add_all__U582.out"], + ["mul_d3__U579.out","add_all__U583.in1"], + ["add_all__U584.in0","add_all__U583.out"], + ["const_term_U580.out","add_all__U584.in1"], + ["self.out","add_all__U584.out"], + ["mul_d0__U573.in0","coeff_0_U572.out"], + ["mul_d1__U575.in0","coeff_1_U574.out"], + ["mul_d2__U577.in0","coeff_2_U576.out"], + ["mul_d3__U579.in0","coeff_3_U578.out"], + ["self.d.0","mul_d0__U573.in1"], + ["self.d.1","mul_d1__U575.in1"], + ["self.d.2","mul_d2__U577.in1"], + ["self.d.3","mul_d3__U579.in1"] ] }, - "affine_controller__U17":{ + "aff__U9":{ "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], - ["rst_n","BitIn"] + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "_U32":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U33":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func":{ - "modref":"global.aff__U18" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time":{ - "genref":"commonlib.counter", - "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} - }, - "d_0_am__U34":{ - "modref":"corebit.and" - }, - "d_0_am__U35":{ - "modref":"corebit.and" - }, - "d_0_am__U36":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ + "add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", + "add_all__U20":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U37":{ - "modref":"corebit.and" - }, - "d_1_am__U38":{ - "modref":"corebit.and" - }, - "d_1_at_max":{ - "genref":"coreir.eq", + "add_all__U21":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} - }, - "d_1_min":{ + "coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U39":{ - "modref":"corebit.and" - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ + "coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} + "modargs":{"value":[["BitVector",32],"32'h000003a0"]} }, - "d_2_min":{ + "coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "d_3_max":{ + "coeff_3_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_3_min":{ + "const_term_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ - "genref":"coreir.mux", + "mul_d0__U11":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", + "mul_d1__U13":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, - "modargs":{"init":[["BitVector",32],"32'h00000000"]} - }, - "time_diff":{ - "genref":"coreir.sub", + "mul_d2__U15":{ + "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} + "mul_d3__U17":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} } }, "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U32.out"], - ["d_2_inc.in1","_U32.out"], - ["d_3_inc.in1","_U32.out"], - ["cmp_time.in1","_U33.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["true.out","cycle_time.en"], - ["time_diff.in1","cycle_time.out"], - ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U34.in0"], - ["d_1_at_max.out","d_0_am__U34.in1"], - ["d_0_am__U35.in0","d_0_am__U34.out"], - ["d_2_at_max.out","d_0_am__U35.in1"], - ["d_0_am__U36.in0","d_0_am__U35.out"], - ["d_3_at_max.out","d_0_am__U36.in1"], - ["d_0_next_value.sel","d_0_am__U36.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.rst_n","d_0_reg.clr"], - ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U37.in0"], - ["d_2_at_max.out","d_1_am__U37.in1"], - ["d_1_am__U38.in0","d_1_am__U37.out"], - ["d_3_at_max.out","d_1_am__U38.in1"], - ["d_1_next_value.sel","d_1_am__U38.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.rst_n","d_1_reg.clr"], - ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U39.in0"], - ["d_3_at_max.out","d_2_am__U39.in1"], - ["d_2_next_value.sel","d_2_am__U39.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["self.clk","d_2_reg.clk"], - ["self.rst_n","d_2_reg.clr"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.rst_n","d_3_reg.clr"], - ["self.d.3","d_3_reg.out"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U271":{ + "affine_controller__U197":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2210,18 +1944,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U289":{ + "_U215":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U290":{ + "_U216":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U272" + "modref":"global.aff__U198" }, "cmp_time":{ "genref":"coreir.eq", @@ -2231,16 +1965,16 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U291":{ + "d_0_am__U217":{ "modref":"corebit.and" }, - "d_0_am__U292":{ + "d_0_am__U218":{ "modref":"corebit.and" }, - "d_0_am__U293":{ + "d_0_am__U219":{ "modref":"corebit.and" }, - "d_0_am__U294":{ + "d_0_am__U220":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2274,13 +2008,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U295":{ + "d_1_am__U221":{ "modref":"corebit.and" }, - "d_1_am__U296":{ + "d_1_am__U222":{ "modref":"corebit.and" }, - "d_1_am__U297":{ + "d_1_am__U223":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2314,10 +2048,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U298":{ + "d_2_am__U224":{ "modref":"corebit.and" }, - "d_2_am__U299":{ + "d_2_am__U225":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2351,7 +2085,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U300":{ + "d_3_am__U226":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2426,12 +2160,12 @@ } }, "connections":[ - ["d_0_inc.in1","_U289.out"], - ["d_1_inc.in1","_U289.out"], - ["d_2_inc.in1","_U289.out"], - ["d_3_inc.in1","_U289.out"], - ["d_4_inc.in1","_U289.out"], - ["cmp_time.in1","_U290.out"], + ["d_0_inc.in1","_U215.out"], + ["d_1_inc.in1","_U215.out"], + ["d_2_inc.in1","_U215.out"], + ["d_3_inc.in1","_U215.out"], + ["d_4_inc.in1","_U215.out"], + ["cmp_time.in1","_U216.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2448,15 +2182,15 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U291.in0"], - ["d_1_at_max.out","d_0_am__U291.in1"], - ["d_0_am__U292.in0","d_0_am__U291.out"], - ["d_2_at_max.out","d_0_am__U292.in1"], - ["d_0_am__U293.in0","d_0_am__U292.out"], - ["d_3_at_max.out","d_0_am__U293.in1"], - ["d_0_am__U294.in0","d_0_am__U293.out"], - ["d_4_at_max.out","d_0_am__U294.in1"], - ["d_0_next_value.sel","d_0_am__U294.out"], + ["true.out","d_0_am__U217.in0"], + ["d_1_at_max.out","d_0_am__U217.in1"], + ["d_0_am__U218.in0","d_0_am__U217.out"], + ["d_2_at_max.out","d_0_am__U218.in1"], + ["d_0_am__U219.in0","d_0_am__U218.out"], + ["d_3_at_max.out","d_0_am__U219.in1"], + ["d_0_am__U220.in0","d_0_am__U219.out"], + ["d_4_at_max.out","d_0_am__U220.in1"], + ["d_0_next_value.sel","d_0_am__U220.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2469,13 +2203,13 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U295.in0"], - ["d_2_at_max.out","d_1_am__U295.in1"], - ["d_1_am__U296.in0","d_1_am__U295.out"], - ["d_3_at_max.out","d_1_am__U296.in1"], - ["d_1_am__U297.in0","d_1_am__U296.out"], - ["d_4_at_max.out","d_1_am__U297.in1"], - ["d_1_next_value.sel","d_1_am__U297.out"], + ["true.out","d_1_am__U221.in0"], + ["d_2_at_max.out","d_1_am__U221.in1"], + ["d_1_am__U222.in0","d_1_am__U221.out"], + ["d_3_at_max.out","d_1_am__U222.in1"], + ["d_1_am__U223.in0","d_1_am__U222.out"], + ["d_4_at_max.out","d_1_am__U223.in1"], + ["d_1_next_value.sel","d_1_am__U223.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2488,11 +2222,11 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U298.in0"], - ["d_3_at_max.out","d_2_am__U298.in1"], - ["d_2_am__U299.in0","d_2_am__U298.out"], - ["d_4_at_max.out","d_2_am__U299.in1"], - ["d_2_next_value.sel","d_2_am__U299.out"], + ["true.out","d_2_am__U224.in0"], + ["d_3_at_max.out","d_2_am__U224.in1"], + ["d_2_am__U225.in0","d_2_am__U224.out"], + ["d_4_at_max.out","d_2_am__U225.in1"], + ["d_2_next_value.sel","d_2_am__U225.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2505,9 +2239,9 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U300.in0"], - ["d_4_at_max.out","d_3_am__U300.in1"], - ["d_3_next_value.sel","d_3_am__U300.out"], + ["true.out","d_3_am__U226.in0"], + ["d_4_at_max.out","d_3_am__U226.in1"], + ["d_3_next_value.sel","d_3_am__U226.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2535,7 +2269,7 @@ ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U320":{ + "affine_controller__U246":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -2543,18 +2277,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U350":{ + "_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U351":{ + "_U277":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U321" + "modref":"global.aff__U247" }, "cmp_time":{ "genref":"coreir.eq", @@ -2564,28 +2298,28 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U352":{ + "d_0_am__U278":{ "modref":"corebit.and" }, - "d_0_am__U353":{ + "d_0_am__U279":{ "modref":"corebit.and" }, - "d_0_am__U354":{ + "d_0_am__U280":{ "modref":"corebit.and" }, - "d_0_am__U355":{ + "d_0_am__U281":{ "modref":"corebit.and" }, - "d_0_am__U356":{ + "d_0_am__U282":{ "modref":"corebit.and" }, - "d_0_am__U357":{ + "d_0_am__U283":{ "modref":"corebit.and" }, - "d_0_am__U358":{ + "d_0_am__U284":{ "modref":"corebit.and" }, - "d_0_am__U359":{ + "d_0_am__U285":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2619,25 +2353,25 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U360":{ + "d_1_am__U286":{ "modref":"corebit.and" }, - "d_1_am__U361":{ + "d_1_am__U287":{ "modref":"corebit.and" }, - "d_1_am__U362":{ + "d_1_am__U288":{ "modref":"corebit.and" }, - "d_1_am__U363":{ + "d_1_am__U289":{ "modref":"corebit.and" }, - "d_1_am__U364":{ + "d_1_am__U290":{ "modref":"corebit.and" }, - "d_1_am__U365":{ + "d_1_am__U291":{ "modref":"corebit.and" }, - "d_1_am__U366":{ + "d_1_am__U292":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2671,22 +2405,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U367":{ + "d_2_am__U293":{ "modref":"corebit.and" }, - "d_2_am__U368":{ + "d_2_am__U294":{ "modref":"corebit.and" }, - "d_2_am__U369":{ + "d_2_am__U295":{ "modref":"corebit.and" }, - "d_2_am__U370":{ + "d_2_am__U296":{ "modref":"corebit.and" }, - "d_2_am__U371":{ + "d_2_am__U297":{ "modref":"corebit.and" }, - "d_2_am__U372":{ + "d_2_am__U298":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2720,19 +2454,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U373":{ + "d_3_am__U299":{ "modref":"corebit.and" }, - "d_3_am__U374":{ + "d_3_am__U300":{ "modref":"corebit.and" }, - "d_3_am__U375":{ + "d_3_am__U301":{ "modref":"corebit.and" }, - "d_3_am__U376":{ + "d_3_am__U302":{ "modref":"corebit.and" }, - "d_3_am__U377":{ + "d_3_am__U303":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -2766,16 +2500,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U378":{ + "d_4_am__U304":{ "modref":"corebit.and" }, - "d_4_am__U379":{ + "d_4_am__U305":{ "modref":"corebit.and" }, - "d_4_am__U380":{ + "d_4_am__U306":{ "modref":"corebit.and" }, - "d_4_am__U381":{ + "d_4_am__U307":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -2809,13 +2543,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U382":{ + "d_5_am__U308":{ "modref":"corebit.and" }, - "d_5_am__U383":{ + "d_5_am__U309":{ "modref":"corebit.and" }, - "d_5_am__U384":{ + "d_5_am__U310":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -2849,10 +2583,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U385":{ + "d_6_am__U311":{ "modref":"corebit.and" }, - "d_6_am__U386":{ + "d_6_am__U312":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -2886,7 +2620,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_7_am__U387":{ + "d_7_am__U313":{ "modref":"corebit.and" }, "d_7_at_max":{ @@ -2961,16 +2695,16 @@ } }, "connections":[ - ["d_0_inc.in1","_U350.out"], - ["d_1_inc.in1","_U350.out"], - ["d_2_inc.in1","_U350.out"], - ["d_3_inc.in1","_U350.out"], - ["d_4_inc.in1","_U350.out"], - ["d_5_inc.in1","_U350.out"], - ["d_6_inc.in1","_U350.out"], - ["d_7_inc.in1","_U350.out"], - ["d_8_inc.in1","_U350.out"], - ["cmp_time.in1","_U351.out"], + ["d_0_inc.in1","_U276.out"], + ["d_1_inc.in1","_U276.out"], + ["d_2_inc.in1","_U276.out"], + ["d_3_inc.in1","_U276.out"], + ["d_4_inc.in1","_U276.out"], + ["d_5_inc.in1","_U276.out"], + ["d_6_inc.in1","_U276.out"], + ["d_7_inc.in1","_U276.out"], + ["d_8_inc.in1","_U276.out"], + ["cmp_time.in1","_U277.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -2995,23 +2729,23 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U352.in0"], - ["d_1_at_max.out","d_0_am__U352.in1"], - ["d_0_am__U353.in0","d_0_am__U352.out"], - ["d_2_at_max.out","d_0_am__U353.in1"], - ["d_0_am__U354.in0","d_0_am__U353.out"], - ["d_3_at_max.out","d_0_am__U354.in1"], - ["d_0_am__U355.in0","d_0_am__U354.out"], - ["d_4_at_max.out","d_0_am__U355.in1"], - ["d_0_am__U356.in0","d_0_am__U355.out"], - ["d_5_at_max.out","d_0_am__U356.in1"], - ["d_0_am__U357.in0","d_0_am__U356.out"], - ["d_6_at_max.out","d_0_am__U357.in1"], - ["d_0_am__U358.in0","d_0_am__U357.out"], - ["d_7_at_max.out","d_0_am__U358.in1"], - ["d_0_am__U359.in0","d_0_am__U358.out"], - ["d_8_at_max.out","d_0_am__U359.in1"], - ["d_0_next_value.sel","d_0_am__U359.out"], + ["true.out","d_0_am__U278.in0"], + ["d_1_at_max.out","d_0_am__U278.in1"], + ["d_0_am__U279.in0","d_0_am__U278.out"], + ["d_2_at_max.out","d_0_am__U279.in1"], + ["d_0_am__U280.in0","d_0_am__U279.out"], + ["d_3_at_max.out","d_0_am__U280.in1"], + ["d_0_am__U281.in0","d_0_am__U280.out"], + ["d_4_at_max.out","d_0_am__U281.in1"], + ["d_0_am__U282.in0","d_0_am__U281.out"], + ["d_5_at_max.out","d_0_am__U282.in1"], + ["d_0_am__U283.in0","d_0_am__U282.out"], + ["d_6_at_max.out","d_0_am__U283.in1"], + ["d_0_am__U284.in0","d_0_am__U283.out"], + ["d_7_at_max.out","d_0_am__U284.in1"], + ["d_0_am__U285.in0","d_0_am__U284.out"], + ["d_8_at_max.out","d_0_am__U285.in1"], + ["d_0_next_value.sel","d_0_am__U285.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3024,21 +2758,21 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U360.in0"], - ["d_2_at_max.out","d_1_am__U360.in1"], - ["d_1_am__U361.in0","d_1_am__U360.out"], - ["d_3_at_max.out","d_1_am__U361.in1"], - ["d_1_am__U362.in0","d_1_am__U361.out"], - ["d_4_at_max.out","d_1_am__U362.in1"], - ["d_1_am__U363.in0","d_1_am__U362.out"], - ["d_5_at_max.out","d_1_am__U363.in1"], - ["d_1_am__U364.in0","d_1_am__U363.out"], - ["d_6_at_max.out","d_1_am__U364.in1"], - ["d_1_am__U365.in0","d_1_am__U364.out"], - ["d_7_at_max.out","d_1_am__U365.in1"], - ["d_1_am__U366.in0","d_1_am__U365.out"], - ["d_8_at_max.out","d_1_am__U366.in1"], - ["d_1_next_value.sel","d_1_am__U366.out"], + ["true.out","d_1_am__U286.in0"], + ["d_2_at_max.out","d_1_am__U286.in1"], + ["d_1_am__U287.in0","d_1_am__U286.out"], + ["d_3_at_max.out","d_1_am__U287.in1"], + ["d_1_am__U288.in0","d_1_am__U287.out"], + ["d_4_at_max.out","d_1_am__U288.in1"], + ["d_1_am__U289.in0","d_1_am__U288.out"], + ["d_5_at_max.out","d_1_am__U289.in1"], + ["d_1_am__U290.in0","d_1_am__U289.out"], + ["d_6_at_max.out","d_1_am__U290.in1"], + ["d_1_am__U291.in0","d_1_am__U290.out"], + ["d_7_at_max.out","d_1_am__U291.in1"], + ["d_1_am__U292.in0","d_1_am__U291.out"], + ["d_8_at_max.out","d_1_am__U292.in1"], + ["d_1_next_value.sel","d_1_am__U292.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3051,19 +2785,19 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U367.in0"], - ["d_3_at_max.out","d_2_am__U367.in1"], - ["d_2_am__U368.in0","d_2_am__U367.out"], - ["d_4_at_max.out","d_2_am__U368.in1"], - ["d_2_am__U369.in0","d_2_am__U368.out"], - ["d_5_at_max.out","d_2_am__U369.in1"], - ["d_2_am__U370.in0","d_2_am__U369.out"], - ["d_6_at_max.out","d_2_am__U370.in1"], - ["d_2_am__U371.in0","d_2_am__U370.out"], - ["d_7_at_max.out","d_2_am__U371.in1"], - ["d_2_am__U372.in0","d_2_am__U371.out"], - ["d_8_at_max.out","d_2_am__U372.in1"], - ["d_2_next_value.sel","d_2_am__U372.out"], + ["true.out","d_2_am__U293.in0"], + ["d_3_at_max.out","d_2_am__U293.in1"], + ["d_2_am__U294.in0","d_2_am__U293.out"], + ["d_4_at_max.out","d_2_am__U294.in1"], + ["d_2_am__U295.in0","d_2_am__U294.out"], + ["d_5_at_max.out","d_2_am__U295.in1"], + ["d_2_am__U296.in0","d_2_am__U295.out"], + ["d_6_at_max.out","d_2_am__U296.in1"], + ["d_2_am__U297.in0","d_2_am__U296.out"], + ["d_7_at_max.out","d_2_am__U297.in1"], + ["d_2_am__U298.in0","d_2_am__U297.out"], + ["d_8_at_max.out","d_2_am__U298.in1"], + ["d_2_next_value.sel","d_2_am__U298.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3076,17 +2810,17 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U373.in0"], - ["d_4_at_max.out","d_3_am__U373.in1"], - ["d_3_am__U374.in0","d_3_am__U373.out"], - ["d_5_at_max.out","d_3_am__U374.in1"], - ["d_3_am__U375.in0","d_3_am__U374.out"], - ["d_6_at_max.out","d_3_am__U375.in1"], - ["d_3_am__U376.in0","d_3_am__U375.out"], - ["d_7_at_max.out","d_3_am__U376.in1"], - ["d_3_am__U377.in0","d_3_am__U376.out"], - ["d_8_at_max.out","d_3_am__U377.in1"], - ["d_3_next_value.sel","d_3_am__U377.out"], + ["true.out","d_3_am__U299.in0"], + ["d_4_at_max.out","d_3_am__U299.in1"], + ["d_3_am__U300.in0","d_3_am__U299.out"], + ["d_5_at_max.out","d_3_am__U300.in1"], + ["d_3_am__U301.in0","d_3_am__U300.out"], + ["d_6_at_max.out","d_3_am__U301.in1"], + ["d_3_am__U302.in0","d_3_am__U301.out"], + ["d_7_at_max.out","d_3_am__U302.in1"], + ["d_3_am__U303.in0","d_3_am__U302.out"], + ["d_8_at_max.out","d_3_am__U303.in1"], + ["d_3_next_value.sel","d_3_am__U303.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3099,15 +2833,15 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U378.in0"], - ["d_5_at_max.out","d_4_am__U378.in1"], - ["d_4_am__U379.in0","d_4_am__U378.out"], - ["d_6_at_max.out","d_4_am__U379.in1"], - ["d_4_am__U380.in0","d_4_am__U379.out"], - ["d_7_at_max.out","d_4_am__U380.in1"], - ["d_4_am__U381.in0","d_4_am__U380.out"], - ["d_8_at_max.out","d_4_am__U381.in1"], - ["d_4_next_value.sel","d_4_am__U381.out"], + ["true.out","d_4_am__U304.in0"], + ["d_5_at_max.out","d_4_am__U304.in1"], + ["d_4_am__U305.in0","d_4_am__U304.out"], + ["d_6_at_max.out","d_4_am__U305.in1"], + ["d_4_am__U306.in0","d_4_am__U305.out"], + ["d_7_at_max.out","d_4_am__U306.in1"], + ["d_4_am__U307.in0","d_4_am__U306.out"], + ["d_8_at_max.out","d_4_am__U307.in1"], + ["d_4_next_value.sel","d_4_am__U307.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -3120,13 +2854,13 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U382.in0"], - ["d_6_at_max.out","d_5_am__U382.in1"], - ["d_5_am__U383.in0","d_5_am__U382.out"], - ["d_7_at_max.out","d_5_am__U383.in1"], - ["d_5_am__U384.in0","d_5_am__U383.out"], - ["d_8_at_max.out","d_5_am__U384.in1"], - ["d_5_next_value.sel","d_5_am__U384.out"], + ["true.out","d_5_am__U308.in0"], + ["d_6_at_max.out","d_5_am__U308.in1"], + ["d_5_am__U309.in0","d_5_am__U308.out"], + ["d_7_at_max.out","d_5_am__U309.in1"], + ["d_5_am__U310.in0","d_5_am__U309.out"], + ["d_8_at_max.out","d_5_am__U310.in1"], + ["d_5_next_value.sel","d_5_am__U310.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -3139,11 +2873,11 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U385.in0"], - ["d_7_at_max.out","d_6_am__U385.in1"], - ["d_6_am__U386.in0","d_6_am__U385.out"], - ["d_8_at_max.out","d_6_am__U386.in1"], - ["d_6_next_value.sel","d_6_am__U386.out"], + ["true.out","d_6_am__U311.in0"], + ["d_7_at_max.out","d_6_am__U311.in1"], + ["d_6_am__U312.in0","d_6_am__U311.out"], + ["d_8_at_max.out","d_6_am__U312.in1"], + ["d_6_next_value.sel","d_6_am__U312.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -3156,9 +2890,9 @@ ["self.clk","d_6_reg.clk"], ["self.rst_n","d_6_reg.clr"], ["self.d.6","d_6_reg.out"], - ["true.out","d_7_am__U387.in0"], - ["d_8_at_max.out","d_7_am__U387.in1"], - ["d_7_next_value.sel","d_7_am__U387.out"], + ["true.out","d_7_am__U313.in0"], + ["d_8_at_max.out","d_7_am__U313.in1"], + ["d_7_next_value.sel","d_7_am__U313.out"], ["d_7_reg.out","d_7_at_max.in0"], ["d_7_max.out","d_7_at_max.in1"], ["d_7_next_value_at_max.sel","d_7_at_max.out"], @@ -3186,7 +2920,7 @@ ["self.d.8","d_8_reg.out"] ] }, - "affine_controller__U421":{ + "affine_controller__U347":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3194,18 +2928,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U430":{ + "_U356":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U431":{ + "_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U422" + "modref":"global.aff__U348" }, "cmp_time":{ "genref":"coreir.eq", @@ -3215,7 +2949,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U432":{ + "d_0_am__U358":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3290,9 +3024,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U430.out"], - ["d_1_inc.in1","_U430.out"], - ["cmp_time.in1","_U431.out"], + ["d_0_inc.in1","_U356.out"], + ["d_1_inc.in1","_U356.out"], + ["cmp_time.in1","_U357.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3303,9 +3037,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U432.in0"], - ["d_1_at_max.out","d_0_am__U432.in1"], - ["d_0_next_value.sel","d_0_am__U432.out"], + ["true.out","d_0_am__U358.in0"], + ["d_1_at_max.out","d_0_am__U358.in1"], + ["d_0_next_value.sel","d_0_am__U358.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3333,7 +3067,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U436":{ + "affine_controller__U361":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3341,18 +3075,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U445":{ + "_U370":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U446":{ + "_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U437" + "modref":"global.aff__U362" }, "cmp_time":{ "genref":"coreir.eq", @@ -3362,7 +3096,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U447":{ + "d_0_am__U372":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3437,9 +3171,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U445.out"], - ["d_1_inc.in1","_U445.out"], - ["cmp_time.in1","_U446.out"], + ["d_0_inc.in1","_U370.out"], + ["d_1_inc.in1","_U370.out"], + ["cmp_time.in1","_U371.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3450,9 +3184,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U447.in0"], - ["d_1_at_max.out","d_0_am__U447.in1"], - ["d_0_next_value.sel","d_0_am__U447.out"], + ["true.out","d_0_am__U372.in0"], + ["d_1_at_max.out","d_0_am__U372.in1"], + ["d_0_next_value.sel","d_0_am__U372.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3480,7 +3214,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U451":{ + "affine_controller__U375":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3488,18 +3222,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U460":{ + "_U384":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U461":{ + "_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U452" + "modref":"global.aff__U376" }, "cmp_time":{ "genref":"coreir.eq", @@ -3509,7 +3243,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U462":{ + "d_0_am__U386":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3584,9 +3318,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U460.out"], - ["d_1_inc.in1","_U460.out"], - ["cmp_time.in1","_U461.out"], + ["d_0_inc.in1","_U384.out"], + ["d_1_inc.in1","_U384.out"], + ["cmp_time.in1","_U385.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3597,9 +3331,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U462.in0"], - ["d_1_at_max.out","d_0_am__U462.in1"], - ["d_0_next_value.sel","d_0_am__U462.out"], + ["true.out","d_0_am__U386.in0"], + ["d_1_at_max.out","d_0_am__U386.in1"], + ["d_0_next_value.sel","d_0_am__U386.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3627,7 +3361,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U466":{ + "affine_controller__U389":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3635,18 +3369,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U475":{ + "_U398":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U476":{ + "_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U467" + "modref":"global.aff__U390" }, "cmp_time":{ "genref":"coreir.eq", @@ -3656,7 +3390,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U477":{ + "d_0_am__U400":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3731,9 +3465,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U475.out"], - ["d_1_inc.in1","_U475.out"], - ["cmp_time.in1","_U476.out"], + ["d_0_inc.in1","_U398.out"], + ["d_1_inc.in1","_U398.out"], + ["cmp_time.in1","_U399.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3744,9 +3478,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U477.in0"], - ["d_1_at_max.out","d_0_am__U477.in1"], - ["d_0_next_value.sel","d_0_am__U477.out"], + ["true.out","d_0_am__U400.in0"], + ["d_1_at_max.out","d_0_am__U400.in1"], + ["d_0_next_value.sel","d_0_am__U400.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3774,7 +3508,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U481":{ + "affine_controller__U403":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3782,18 +3516,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U490":{ + "_U412":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U491":{ + "_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U482" + "modref":"global.aff__U404" }, "cmp_time":{ "genref":"coreir.eq", @@ -3803,7 +3537,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U492":{ + "d_0_am__U414":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3878,9 +3612,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U490.out"], - ["d_1_inc.in1","_U490.out"], - ["cmp_time.in1","_U491.out"], + ["d_0_inc.in1","_U412.out"], + ["d_1_inc.in1","_U412.out"], + ["cmp_time.in1","_U413.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -3891,9 +3625,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U492.in0"], - ["d_1_at_max.out","d_0_am__U492.in1"], - ["d_0_next_value.sel","d_0_am__U492.out"], + ["true.out","d_0_am__U414.in0"], + ["d_1_at_max.out","d_0_am__U414.in1"], + ["d_0_next_value.sel","d_0_am__U414.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3921,7 +3655,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U496":{ + "affine_controller__U417":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -3929,18 +3663,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U505":{ + "_U426":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U506":{ + "_U427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U497" + "modref":"global.aff__U418" }, "cmp_time":{ "genref":"coreir.eq", @@ -3950,7 +3684,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U507":{ + "d_0_am__U428":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4025,9 +3759,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U505.out"], - ["d_1_inc.in1","_U505.out"], - ["cmp_time.in1","_U506.out"], + ["d_0_inc.in1","_U426.out"], + ["d_1_inc.in1","_U426.out"], + ["cmp_time.in1","_U427.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -4038,9 +3772,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U507.in0"], - ["d_1_at_max.out","d_0_am__U507.in1"], - ["d_0_next_value.sel","d_0_am__U507.out"], + ["true.out","d_0_am__U428.in0"], + ["d_1_at_max.out","d_0_am__U428.in1"], + ["d_0_next_value.sel","d_0_am__U428.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4068,7 +3802,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U511":{ + "affine_controller__U431":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4076,18 +3810,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U520":{ + "_U440":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U521":{ + "_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U512" + "modref":"global.aff__U432" }, "cmp_time":{ "genref":"coreir.eq", @@ -4097,7 +3831,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U522":{ + "d_0_am__U442":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4172,9 +3906,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U520.out"], - ["d_1_inc.in1","_U520.out"], - ["cmp_time.in1","_U521.out"], + ["d_0_inc.in1","_U440.out"], + ["d_1_inc.in1","_U440.out"], + ["cmp_time.in1","_U441.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -4185,9 +3919,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U522.in0"], - ["d_1_at_max.out","d_0_am__U522.in1"], - ["d_0_next_value.sel","d_0_am__U522.out"], + ["true.out","d_0_am__U442.in0"], + ["d_1_at_max.out","d_0_am__U442.in1"], + ["d_0_next_value.sel","d_0_am__U442.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4215,7 +3949,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U526":{ + "affine_controller__U445":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4223,18 +3957,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U535":{ + "_U454":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U536":{ + "_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U527" + "modref":"global.aff__U446" }, "cmp_time":{ "genref":"coreir.eq", @@ -4244,7 +3978,7 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U537":{ + "d_0_am__U456":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4319,9 +4053,9 @@ } }, "connections":[ - ["d_0_inc.in1","_U535.out"], - ["d_1_inc.in1","_U535.out"], - ["cmp_time.in1","_U536.out"], + ["d_0_inc.in1","_U454.out"], + ["d_1_inc.in1","_U454.out"], + ["cmp_time.in1","_U455.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["time_diff.in0","affine_func.out"], @@ -4332,9 +4066,9 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U537.in0"], - ["d_1_at_max.out","d_0_am__U537.in1"], - ["d_0_next_value.sel","d_0_am__U537.out"], + ["true.out","d_0_am__U456.in0"], + ["d_1_at_max.out","d_0_am__U456.in1"], + ["d_0_next_value.sel","d_0_am__U456.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4362,7 +4096,7 @@ ["self.d.1","d_1_reg.out"] ] }, - "affine_controller__U541":{ + "affine_controller__U458":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4370,18 +4104,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U565":{ + "_U482":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U566":{ + "_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U542" + "modref":"global.aff__U459" }, "cmp_time":{ "genref":"coreir.eq", @@ -4391,22 +4125,22 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U567":{ + "d_0_am__U484":{ "modref":"corebit.and" }, - "d_0_am__U568":{ + "d_0_am__U485":{ "modref":"corebit.and" }, - "d_0_am__U569":{ + "d_0_am__U486":{ "modref":"corebit.and" }, - "d_0_am__U570":{ + "d_0_am__U487":{ "modref":"corebit.and" }, - "d_0_am__U571":{ + "d_0_am__U488":{ "modref":"corebit.and" }, - "d_0_am__U572":{ + "d_0_am__U489":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4440,19 +4174,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U573":{ + "d_1_am__U490":{ "modref":"corebit.and" }, - "d_1_am__U574":{ + "d_1_am__U491":{ "modref":"corebit.and" }, - "d_1_am__U575":{ + "d_1_am__U492":{ "modref":"corebit.and" }, - "d_1_am__U576":{ + "d_1_am__U493":{ "modref":"corebit.and" }, - "d_1_am__U577":{ + "d_1_am__U494":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -4486,16 +4220,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U578":{ + "d_2_am__U495":{ "modref":"corebit.and" }, - "d_2_am__U579":{ + "d_2_am__U496":{ "modref":"corebit.and" }, - "d_2_am__U580":{ + "d_2_am__U497":{ "modref":"corebit.and" }, - "d_2_am__U581":{ + "d_2_am__U498":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -4529,13 +4263,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U582":{ + "d_3_am__U499":{ "modref":"corebit.and" }, - "d_3_am__U583":{ + "d_3_am__U500":{ "modref":"corebit.and" }, - "d_3_am__U584":{ + "d_3_am__U501":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -4569,10 +4303,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U585":{ + "d_4_am__U502":{ "modref":"corebit.and" }, - "d_4_am__U586":{ + "d_4_am__U503":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -4606,7 +4340,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U587":{ + "d_5_am__U504":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -4681,14 +4415,14 @@ } }, "connections":[ - ["d_0_inc.in1","_U565.out"], - ["d_1_inc.in1","_U565.out"], - ["d_2_inc.in1","_U565.out"], - ["d_3_inc.in1","_U565.out"], - ["d_4_inc.in1","_U565.out"], - ["d_5_inc.in1","_U565.out"], - ["d_6_inc.in1","_U565.out"], - ["cmp_time.in1","_U566.out"], + ["d_0_inc.in1","_U482.out"], + ["d_1_inc.in1","_U482.out"], + ["d_2_inc.in1","_U482.out"], + ["d_3_inc.in1","_U482.out"], + ["d_4_inc.in1","_U482.out"], + ["d_5_inc.in1","_U482.out"], + ["d_6_inc.in1","_U482.out"], + ["cmp_time.in1","_U483.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -4709,19 +4443,19 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U567.in0"], - ["d_1_at_max.out","d_0_am__U567.in1"], - ["d_0_am__U568.in0","d_0_am__U567.out"], - ["d_2_at_max.out","d_0_am__U568.in1"], - ["d_0_am__U569.in0","d_0_am__U568.out"], - ["d_3_at_max.out","d_0_am__U569.in1"], - ["d_0_am__U570.in0","d_0_am__U569.out"], - ["d_4_at_max.out","d_0_am__U570.in1"], - ["d_0_am__U571.in0","d_0_am__U570.out"], - ["d_5_at_max.out","d_0_am__U571.in1"], - ["d_0_am__U572.in0","d_0_am__U571.out"], - ["d_6_at_max.out","d_0_am__U572.in1"], - ["d_0_next_value.sel","d_0_am__U572.out"], + ["true.out","d_0_am__U484.in0"], + ["d_1_at_max.out","d_0_am__U484.in1"], + ["d_0_am__U485.in0","d_0_am__U484.out"], + ["d_2_at_max.out","d_0_am__U485.in1"], + ["d_0_am__U486.in0","d_0_am__U485.out"], + ["d_3_at_max.out","d_0_am__U486.in1"], + ["d_0_am__U487.in0","d_0_am__U486.out"], + ["d_4_at_max.out","d_0_am__U487.in1"], + ["d_0_am__U488.in0","d_0_am__U487.out"], + ["d_5_at_max.out","d_0_am__U488.in1"], + ["d_0_am__U489.in0","d_0_am__U488.out"], + ["d_6_at_max.out","d_0_am__U489.in1"], + ["d_0_next_value.sel","d_0_am__U489.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4734,17 +4468,17 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U573.in0"], - ["d_2_at_max.out","d_1_am__U573.in1"], - ["d_1_am__U574.in0","d_1_am__U573.out"], - ["d_3_at_max.out","d_1_am__U574.in1"], - ["d_1_am__U575.in0","d_1_am__U574.out"], - ["d_4_at_max.out","d_1_am__U575.in1"], - ["d_1_am__U576.in0","d_1_am__U575.out"], - ["d_5_at_max.out","d_1_am__U576.in1"], - ["d_1_am__U577.in0","d_1_am__U576.out"], - ["d_6_at_max.out","d_1_am__U577.in1"], - ["d_1_next_value.sel","d_1_am__U577.out"], + ["true.out","d_1_am__U490.in0"], + ["d_2_at_max.out","d_1_am__U490.in1"], + ["d_1_am__U491.in0","d_1_am__U490.out"], + ["d_3_at_max.out","d_1_am__U491.in1"], + ["d_1_am__U492.in0","d_1_am__U491.out"], + ["d_4_at_max.out","d_1_am__U492.in1"], + ["d_1_am__U493.in0","d_1_am__U492.out"], + ["d_5_at_max.out","d_1_am__U493.in1"], + ["d_1_am__U494.in0","d_1_am__U493.out"], + ["d_6_at_max.out","d_1_am__U494.in1"], + ["d_1_next_value.sel","d_1_am__U494.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4757,15 +4491,15 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U578.in0"], - ["d_3_at_max.out","d_2_am__U578.in1"], - ["d_2_am__U579.in0","d_2_am__U578.out"], - ["d_4_at_max.out","d_2_am__U579.in1"], - ["d_2_am__U580.in0","d_2_am__U579.out"], - ["d_5_at_max.out","d_2_am__U580.in1"], - ["d_2_am__U581.in0","d_2_am__U580.out"], - ["d_6_at_max.out","d_2_am__U581.in1"], - ["d_2_next_value.sel","d_2_am__U581.out"], + ["true.out","d_2_am__U495.in0"], + ["d_3_at_max.out","d_2_am__U495.in1"], + ["d_2_am__U496.in0","d_2_am__U495.out"], + ["d_4_at_max.out","d_2_am__U496.in1"], + ["d_2_am__U497.in0","d_2_am__U496.out"], + ["d_5_at_max.out","d_2_am__U497.in1"], + ["d_2_am__U498.in0","d_2_am__U497.out"], + ["d_6_at_max.out","d_2_am__U498.in1"], + ["d_2_next_value.sel","d_2_am__U498.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4778,13 +4512,13 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U582.in0"], - ["d_4_at_max.out","d_3_am__U582.in1"], - ["d_3_am__U583.in0","d_3_am__U582.out"], - ["d_5_at_max.out","d_3_am__U583.in1"], - ["d_3_am__U584.in0","d_3_am__U583.out"], - ["d_6_at_max.out","d_3_am__U584.in1"], - ["d_3_next_value.sel","d_3_am__U584.out"], + ["true.out","d_3_am__U499.in0"], + ["d_4_at_max.out","d_3_am__U499.in1"], + ["d_3_am__U500.in0","d_3_am__U499.out"], + ["d_5_at_max.out","d_3_am__U500.in1"], + ["d_3_am__U501.in0","d_3_am__U500.out"], + ["d_6_at_max.out","d_3_am__U501.in1"], + ["d_3_next_value.sel","d_3_am__U501.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4797,11 +4531,11 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U585.in0"], - ["d_5_at_max.out","d_4_am__U585.in1"], - ["d_4_am__U586.in0","d_4_am__U585.out"], - ["d_6_at_max.out","d_4_am__U586.in1"], - ["d_4_next_value.sel","d_4_am__U586.out"], + ["true.out","d_4_am__U502.in0"], + ["d_5_at_max.out","d_4_am__U502.in1"], + ["d_4_am__U503.in0","d_4_am__U502.out"], + ["d_6_at_max.out","d_4_am__U503.in1"], + ["d_4_next_value.sel","d_4_am__U503.out"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -4814,9 +4548,9 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U587.in0"], - ["d_6_at_max.out","d_5_am__U587.in1"], - ["d_5_next_value.sel","d_5_am__U587.out"], + ["true.out","d_5_am__U504.in0"], + ["d_6_at_max.out","d_5_am__U504.in1"], + ["d_5_next_value.sel","d_5_am__U504.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -4844,7 +4578,7 @@ ["self.d.6","d_6_reg.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4852,18 +4586,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U83":{ + "_U74":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U84":{ + "_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U57" + "modref":"global.aff__U48" }, "cmp_time":{ "genref":"coreir.eq", @@ -4873,25 +4607,25 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U85":{ + "d_0_am__U76":{ "modref":"corebit.and" }, - "d_0_am__U86":{ + "d_0_am__U77":{ "modref":"corebit.and" }, - "d_0_am__U87":{ + "d_0_am__U78":{ "modref":"corebit.and" }, - "d_0_am__U88":{ + "d_0_am__U79":{ "modref":"corebit.and" }, - "d_0_am__U89":{ + "d_0_am__U80":{ "modref":"corebit.and" }, - "d_0_am__U90":{ + "d_0_am__U81":{ "modref":"corebit.and" }, - "d_0_am__U91":{ + "d_0_am__U82":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -4925,22 +4659,22 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U92":{ + "d_1_am__U83":{ "modref":"corebit.and" }, - "d_1_am__U93":{ + "d_1_am__U84":{ "modref":"corebit.and" }, - "d_1_am__U94":{ + "d_1_am__U85":{ "modref":"corebit.and" }, - "d_1_am__U95":{ + "d_1_am__U86":{ "modref":"corebit.and" }, - "d_1_am__U96":{ + "d_1_am__U87":{ "modref":"corebit.and" }, - "d_1_am__U97":{ + "d_1_am__U88":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -4974,19 +4708,19 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U100":{ + "d_2_am__U89":{ "modref":"corebit.and" }, - "d_2_am__U101":{ + "d_2_am__U90":{ "modref":"corebit.and" }, - "d_2_am__U102":{ + "d_2_am__U91":{ "modref":"corebit.and" }, - "d_2_am__U98":{ + "d_2_am__U92":{ "modref":"corebit.and" }, - "d_2_am__U99":{ + "d_2_am__U93":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5020,16 +4754,16 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U103":{ + "d_3_am__U94":{ "modref":"corebit.and" }, - "d_3_am__U104":{ + "d_3_am__U95":{ "modref":"corebit.and" }, - "d_3_am__U105":{ + "d_3_am__U96":{ "modref":"corebit.and" }, - "d_3_am__U106":{ + "d_3_am__U97":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -5063,13 +4797,13 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U107":{ + "d_4_am__U100":{ "modref":"corebit.and" }, - "d_4_am__U108":{ + "d_4_am__U98":{ "modref":"corebit.and" }, - "d_4_am__U109":{ + "d_4_am__U99":{ "modref":"corebit.and" }, "d_4_at_max":{ @@ -5103,10 +4837,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U110":{ + "d_5_am__U101":{ "modref":"corebit.and" }, - "d_5_am__U111":{ + "d_5_am__U102":{ "modref":"corebit.and" }, "d_5_at_max":{ @@ -5140,7 +4874,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U112":{ + "d_6_am__U103":{ "modref":"corebit.and" }, "d_6_at_max":{ @@ -5215,15 +4949,15 @@ } }, "connections":[ - ["d_0_inc.in1","_U83.out"], - ["d_1_inc.in1","_U83.out"], - ["d_2_inc.in1","_U83.out"], - ["d_3_inc.in1","_U83.out"], - ["d_4_inc.in1","_U83.out"], - ["d_5_inc.in1","_U83.out"], - ["d_6_inc.in1","_U83.out"], - ["d_7_inc.in1","_U83.out"], - ["cmp_time.in1","_U84.out"], + ["d_0_inc.in1","_U74.out"], + ["d_1_inc.in1","_U74.out"], + ["d_2_inc.in1","_U74.out"], + ["d_3_inc.in1","_U74.out"], + ["d_4_inc.in1","_U74.out"], + ["d_5_inc.in1","_U74.out"], + ["d_6_inc.in1","_U74.out"], + ["d_7_inc.in1","_U74.out"], + ["cmp_time.in1","_U75.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5246,21 +4980,21 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U85.in0"], - ["d_1_at_max.out","d_0_am__U85.in1"], - ["d_0_am__U86.in0","d_0_am__U85.out"], - ["d_2_at_max.out","d_0_am__U86.in1"], - ["d_0_am__U87.in0","d_0_am__U86.out"], - ["d_3_at_max.out","d_0_am__U87.in1"], - ["d_0_am__U88.in0","d_0_am__U87.out"], - ["d_4_at_max.out","d_0_am__U88.in1"], - ["d_0_am__U89.in0","d_0_am__U88.out"], - ["d_5_at_max.out","d_0_am__U89.in1"], - ["d_0_am__U90.in0","d_0_am__U89.out"], - ["d_6_at_max.out","d_0_am__U90.in1"], - ["d_0_am__U91.in0","d_0_am__U90.out"], - ["d_7_at_max.out","d_0_am__U91.in1"], - ["d_0_next_value.sel","d_0_am__U91.out"], + ["true.out","d_0_am__U76.in0"], + ["d_1_at_max.out","d_0_am__U76.in1"], + ["d_0_am__U77.in0","d_0_am__U76.out"], + ["d_2_at_max.out","d_0_am__U77.in1"], + ["d_0_am__U78.in0","d_0_am__U77.out"], + ["d_3_at_max.out","d_0_am__U78.in1"], + ["d_0_am__U79.in0","d_0_am__U78.out"], + ["d_4_at_max.out","d_0_am__U79.in1"], + ["d_0_am__U80.in0","d_0_am__U79.out"], + ["d_5_at_max.out","d_0_am__U80.in1"], + ["d_0_am__U81.in0","d_0_am__U80.out"], + ["d_6_at_max.out","d_0_am__U81.in1"], + ["d_0_am__U82.in0","d_0_am__U81.out"], + ["d_7_at_max.out","d_0_am__U82.in1"], + ["d_0_next_value.sel","d_0_am__U82.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5273,19 +5007,19 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U92.in0"], - ["d_2_at_max.out","d_1_am__U92.in1"], - ["d_1_am__U93.in0","d_1_am__U92.out"], - ["d_3_at_max.out","d_1_am__U93.in1"], - ["d_1_am__U94.in0","d_1_am__U93.out"], - ["d_4_at_max.out","d_1_am__U94.in1"], - ["d_1_am__U95.in0","d_1_am__U94.out"], - ["d_5_at_max.out","d_1_am__U95.in1"], - ["d_1_am__U96.in0","d_1_am__U95.out"], - ["d_6_at_max.out","d_1_am__U96.in1"], - ["d_1_am__U97.in0","d_1_am__U96.out"], - ["d_7_at_max.out","d_1_am__U97.in1"], - ["d_1_next_value.sel","d_1_am__U97.out"], + ["true.out","d_1_am__U83.in0"], + ["d_2_at_max.out","d_1_am__U83.in1"], + ["d_1_am__U84.in0","d_1_am__U83.out"], + ["d_3_at_max.out","d_1_am__U84.in1"], + ["d_1_am__U85.in0","d_1_am__U84.out"], + ["d_4_at_max.out","d_1_am__U85.in1"], + ["d_1_am__U86.in0","d_1_am__U85.out"], + ["d_5_at_max.out","d_1_am__U86.in1"], + ["d_1_am__U87.in0","d_1_am__U86.out"], + ["d_6_at_max.out","d_1_am__U87.in1"], + ["d_1_am__U88.in0","d_1_am__U87.out"], + ["d_7_at_max.out","d_1_am__U88.in1"], + ["d_1_next_value.sel","d_1_am__U88.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5298,17 +5032,17 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["d_2_am__U99.out","d_2_am__U100.in0"], - ["d_5_at_max.out","d_2_am__U100.in1"], - ["d_2_am__U101.in0","d_2_am__U100.out"], - ["d_6_at_max.out","d_2_am__U101.in1"], - ["d_2_am__U102.in0","d_2_am__U101.out"], - ["d_7_at_max.out","d_2_am__U102.in1"], - ["d_2_next_value.sel","d_2_am__U102.out"], - ["true.out","d_2_am__U98.in0"], - ["d_3_at_max.out","d_2_am__U98.in1"], - ["d_2_am__U99.in0","d_2_am__U98.out"], - ["d_4_at_max.out","d_2_am__U99.in1"], + ["true.out","d_2_am__U89.in0"], + ["d_3_at_max.out","d_2_am__U89.in1"], + ["d_2_am__U90.in0","d_2_am__U89.out"], + ["d_4_at_max.out","d_2_am__U90.in1"], + ["d_2_am__U91.in0","d_2_am__U90.out"], + ["d_5_at_max.out","d_2_am__U91.in1"], + ["d_2_am__U92.in0","d_2_am__U91.out"], + ["d_6_at_max.out","d_2_am__U92.in1"], + ["d_2_am__U93.in0","d_2_am__U92.out"], + ["d_7_at_max.out","d_2_am__U93.in1"], + ["d_2_next_value.sel","d_2_am__U93.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5321,15 +5055,15 @@ ["self.clk","d_2_reg.clk"], ["self.rst_n","d_2_reg.clr"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U103.in0"], - ["d_4_at_max.out","d_3_am__U103.in1"], - ["d_3_am__U104.in0","d_3_am__U103.out"], - ["d_5_at_max.out","d_3_am__U104.in1"], - ["d_3_am__U105.in0","d_3_am__U104.out"], - ["d_6_at_max.out","d_3_am__U105.in1"], - ["d_3_am__U106.in0","d_3_am__U105.out"], - ["d_7_at_max.out","d_3_am__U106.in1"], - ["d_3_next_value.sel","d_3_am__U106.out"], + ["true.out","d_3_am__U94.in0"], + ["d_4_at_max.out","d_3_am__U94.in1"], + ["d_3_am__U95.in0","d_3_am__U94.out"], + ["d_5_at_max.out","d_3_am__U95.in1"], + ["d_3_am__U96.in0","d_3_am__U95.out"], + ["d_6_at_max.out","d_3_am__U96.in1"], + ["d_3_am__U97.in0","d_3_am__U96.out"], + ["d_7_at_max.out","d_3_am__U97.in1"], + ["d_3_next_value.sel","d_3_am__U97.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -5342,13 +5076,13 @@ ["self.clk","d_3_reg.clk"], ["self.rst_n","d_3_reg.clr"], ["self.d.3","d_3_reg.out"], - ["true.out","d_4_am__U107.in0"], - ["d_5_at_max.out","d_4_am__U107.in1"], - ["d_4_am__U108.in0","d_4_am__U107.out"], - ["d_6_at_max.out","d_4_am__U108.in1"], - ["d_4_am__U109.in0","d_4_am__U108.out"], - ["d_7_at_max.out","d_4_am__U109.in1"], - ["d_4_next_value.sel","d_4_am__U109.out"], + ["d_4_am__U99.out","d_4_am__U100.in0"], + ["d_7_at_max.out","d_4_am__U100.in1"], + ["d_4_next_value.sel","d_4_am__U100.out"], + ["true.out","d_4_am__U98.in0"], + ["d_5_at_max.out","d_4_am__U98.in1"], + ["d_4_am__U99.in0","d_4_am__U98.out"], + ["d_6_at_max.out","d_4_am__U99.in1"], ["d_4_reg.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -5361,11 +5095,11 @@ ["self.clk","d_4_reg.clk"], ["self.rst_n","d_4_reg.clr"], ["self.d.4","d_4_reg.out"], - ["true.out","d_5_am__U110.in0"], - ["d_6_at_max.out","d_5_am__U110.in1"], - ["d_5_am__U111.in0","d_5_am__U110.out"], - ["d_7_at_max.out","d_5_am__U111.in1"], - ["d_5_next_value.sel","d_5_am__U111.out"], + ["true.out","d_5_am__U101.in0"], + ["d_6_at_max.out","d_5_am__U101.in1"], + ["d_5_am__U102.in0","d_5_am__U101.out"], + ["d_7_at_max.out","d_5_am__U102.in1"], + ["d_5_next_value.sel","d_5_am__U102.out"], ["d_5_reg.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -5378,9 +5112,9 @@ ["self.clk","d_5_reg.clk"], ["self.rst_n","d_5_reg.clr"], ["self.d.5","d_5_reg.out"], - ["true.out","d_6_am__U112.in0"], - ["d_7_at_max.out","d_6_am__U112.in1"], - ["d_6_next_value.sel","d_6_am__U112.out"], + ["true.out","d_6_am__U103.in0"], + ["d_7_at_max.out","d_6_am__U103.in1"], + ["d_6_next_value.sel","d_6_am__U103.out"], ["d_6_reg.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -5408,7 +5142,273 @@ ["self.d.7","d_7_reg.out"] ] }, - "affine_controller__U613":{ + "affine_controller__U530":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",4,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U545":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U546":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func":{ + "modref":"global.aff__U531" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time":{ + "genref":"commonlib.counter", + "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} + }, + "d_0_am__U547":{ + "modref":"corebit.and" + }, + "d_0_am__U548":{ + "modref":"corebit.and" + }, + "d_0_am__U549":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U550":{ + "modref":"corebit.and" + }, + "d_1_am__U551":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000037"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_2_am__U552":{ + "modref":"corebit.and" + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000037"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, + "modargs":{"init":[["BitVector",32],"32'h00000000"]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U545.out"], + ["d_1_inc.in1","_U545.out"], + ["d_2_inc.in1","_U545.out"], + ["d_3_inc.in1","_U545.out"], + ["cmp_time.in1","_U546.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["true.out","cycle_time.en"], + ["time_diff.in1","cycle_time.out"], + ["self.rst_n","cycle_time.reset"], + ["true.out","d_0_am__U547.in0"], + ["d_1_at_max.out","d_0_am__U547.in1"], + ["d_0_am__U548.in0","d_0_am__U547.out"], + ["d_2_at_max.out","d_0_am__U548.in1"], + ["d_0_am__U549.in0","d_0_am__U548.out"], + ["d_3_at_max.out","d_0_am__U549.in1"], + ["d_0_next_value.sel","d_0_am__U549.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.rst_n","d_0_reg.clr"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U550.in0"], + ["d_2_at_max.out","d_1_am__U550.in1"], + ["d_1_am__U551.in0","d_1_am__U550.out"], + ["d_3_at_max.out","d_1_am__U551.in1"], + ["d_1_next_value.sel","d_1_am__U551.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.rst_n","d_1_reg.clr"], + ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U552.in0"], + ["d_3_at_max.out","d_2_am__U552.in1"], + ["d_2_next_value.sel","d_2_am__U552.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["self.clk","d_2_reg.clk"], + ["self.rst_n","d_2_reg.clr"], + ["self.d.2","d_2_reg.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], + ["self.clk","d_3_reg.clk"], + ["self.rst_n","d_3_reg.clr"], + ["self.d.3","d_3_reg.out"] + ] + }, + "affine_controller__U570":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5416,18 +5416,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U628":{ + "_U585":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U629":{ + "_U586":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U614" + "modref":"global.aff__U571" }, "cmp_time":{ "genref":"coreir.eq", @@ -5437,13 +5437,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U630":{ + "d_0_am__U587":{ "modref":"corebit.and" }, - "d_0_am__U631":{ + "d_0_am__U588":{ "modref":"corebit.and" }, - "d_0_am__U632":{ + "d_0_am__U589":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5477,10 +5477,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U633":{ + "d_1_am__U590":{ "modref":"corebit.and" }, - "d_1_am__U634":{ + "d_1_am__U591":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -5514,7 +5514,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U635":{ + "d_2_am__U592":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5589,11 +5589,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U628.out"], - ["d_1_inc.in1","_U628.out"], - ["d_2_inc.in1","_U628.out"], - ["d_3_inc.in1","_U628.out"], - ["cmp_time.in1","_U629.out"], + ["d_0_inc.in1","_U585.out"], + ["d_1_inc.in1","_U585.out"], + ["d_2_inc.in1","_U585.out"], + ["d_3_inc.in1","_U585.out"], + ["cmp_time.in1","_U586.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5608,13 +5608,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U630.in0"], - ["d_1_at_max.out","d_0_am__U630.in1"], - ["d_0_am__U631.in0","d_0_am__U630.out"], - ["d_2_at_max.out","d_0_am__U631.in1"], - ["d_0_am__U632.in0","d_0_am__U631.out"], - ["d_3_at_max.out","d_0_am__U632.in1"], - ["d_0_next_value.sel","d_0_am__U632.out"], + ["true.out","d_0_am__U587.in0"], + ["d_1_at_max.out","d_0_am__U587.in1"], + ["d_0_am__U588.in0","d_0_am__U587.out"], + ["d_2_at_max.out","d_0_am__U588.in1"], + ["d_0_am__U589.in0","d_0_am__U588.out"], + ["d_3_at_max.out","d_0_am__U589.in1"], + ["d_0_next_value.sel","d_0_am__U589.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5627,11 +5627,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U633.in0"], - ["d_2_at_max.out","d_1_am__U633.in1"], - ["d_1_am__U634.in0","d_1_am__U633.out"], - ["d_3_at_max.out","d_1_am__U634.in1"], - ["d_1_next_value.sel","d_1_am__U634.out"], + ["true.out","d_1_am__U590.in0"], + ["d_2_at_max.out","d_1_am__U590.in1"], + ["d_1_am__U591.in0","d_1_am__U590.out"], + ["d_3_at_max.out","d_1_am__U591.in1"], + ["d_1_next_value.sel","d_1_am__U591.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5644,9 +5644,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U635.in0"], - ["d_3_at_max.out","d_2_am__U635.in1"], - ["d_2_next_value.sel","d_2_am__U635.out"], + ["true.out","d_2_am__U592.in0"], + ["d_3_at_max.out","d_2_am__U592.in1"], + ["d_2_next_value.sel","d_2_am__U592.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -5674,7 +5674,7 @@ ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U653":{ + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5682,18 +5682,18 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U668":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U669":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, "affine_func":{ - "modref":"global.aff__U654" + "modref":"global.aff__U9" }, "cmp_time":{ "genref":"coreir.eq", @@ -5703,13 +5703,13 @@ "genref":"commonlib.counter", "genargs":{"inc":["Int",1], "max":["Int",2147483647], "min":["Int",0], "width":["Int",32]} }, - "d_0_am__U670":{ + "d_0_am__U25":{ "modref":"corebit.and" }, - "d_0_am__U671":{ + "d_0_am__U26":{ "modref":"corebit.and" }, - "d_0_am__U672":{ + "d_0_am__U27":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -5743,10 +5743,10 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U673":{ + "d_1_am__U28":{ "modref":"corebit.and" }, - "d_1_am__U674":{ + "d_1_am__U29":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -5760,7 +5760,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000037"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_1_min":{ "genref":"coreir.const", @@ -5780,7 +5780,7 @@ "genargs":{"has_clr":["Bool",true], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",32]}, "modargs":{"init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U675":{ + "d_2_am__U30":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -5794,7 +5794,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000037"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_2_min":{ "genref":"coreir.const", @@ -5855,11 +5855,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U668.out"], - ["d_1_inc.in1","_U668.out"], - ["d_2_inc.in1","_U668.out"], - ["d_3_inc.in1","_U668.out"], - ["cmp_time.in1","_U669.out"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U23.out"], + ["d_2_inc.in1","_U23.out"], + ["d_3_inc.in1","_U23.out"], + ["cmp_time.in1","_U24.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -5874,13 +5874,13 @@ ["true.out","cycle_time.en"], ["time_diff.in1","cycle_time.out"], ["self.rst_n","cycle_time.reset"], - ["true.out","d_0_am__U670.in0"], - ["d_1_at_max.out","d_0_am__U670.in1"], - ["d_0_am__U671.in0","d_0_am__U670.out"], - ["d_2_at_max.out","d_0_am__U671.in1"], - ["d_0_am__U672.in0","d_0_am__U671.out"], - ["d_3_at_max.out","d_0_am__U672.in1"], - ["d_0_next_value.sel","d_0_am__U672.out"], + ["true.out","d_0_am__U25.in0"], + ["d_1_at_max.out","d_0_am__U25.in1"], + ["d_0_am__U26.in0","d_0_am__U25.out"], + ["d_2_at_max.out","d_0_am__U26.in1"], + ["d_0_am__U27.in0","d_0_am__U26.out"], + ["d_3_at_max.out","d_0_am__U27.in1"], + ["d_0_next_value.sel","d_0_am__U27.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5893,11 +5893,11 @@ ["self.clk","d_0_reg.clk"], ["self.rst_n","d_0_reg.clr"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U673.in0"], - ["d_2_at_max.out","d_1_am__U673.in1"], - ["d_1_am__U674.in0","d_1_am__U673.out"], - ["d_3_at_max.out","d_1_am__U674.in1"], - ["d_1_next_value.sel","d_1_am__U674.out"], + ["true.out","d_1_am__U28.in0"], + ["d_2_at_max.out","d_1_am__U28.in1"], + ["d_1_am__U29.in0","d_1_am__U28.out"], + ["d_3_at_max.out","d_1_am__U29.in1"], + ["d_1_next_value.sel","d_1_am__U29.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -5910,9 +5910,9 @@ ["self.clk","d_1_reg.clk"], ["self.rst_n","d_1_reg.clr"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U675.in0"], - ["d_3_at_max.out","d_2_am__U675.in1"], - ["d_2_next_value.sel","d_2_am__U675.out"], + ["true.out","d_2_am__U30.in0"], + ["d_3_at_max.out","d_2_am__U30.in1"], + ["d_2_next_value.sel","d_2_am__U30.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -7557,42 +7557,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53849],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53849],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -7600,8 +7568,8 @@ }, "ub_input_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53850],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53850],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -7609,8 +7577,8 @@ }, "ub_input_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53851],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53851],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -7618,8 +7586,8 @@ }, "ub_input_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53852],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61023],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53852],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61023],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -7627,8 +7595,8 @@ }, "ub_input_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53853],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53853],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -7636,8 +7604,8 @@ }, "ub_input_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53854],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U10"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53854],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -7645,8 +7613,8 @@ }, "ub_input_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53855],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U12"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53855],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61024],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -7654,8 +7622,8 @@ }, "ub_input_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53856],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61023],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake","verilog_name":"lake__U14"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[53856],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[61023],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -7663,14 +7631,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_input_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U11.out"], - ["ub_input_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U13.out"], - ["ub_input_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U15.out"], - ["ub_input_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_input_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], - ["ub_input_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U7.out"], - ["ub_input_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U9.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_1.clk","self.clk"], ["ub_input_cgra_stencil_BANK_2.clk","self.clk"], @@ -7788,42 +7748,42 @@ ["op_hcompute_input_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U140":{ - "modref":"global.aff__U114" + "addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U131":{ + "modref":"global.aff__U105" }, - "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55":{ - "modref":"global.aff__U41" + "addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46":{ + "modref":"global.aff__U32" }, - "chain_en_const_U141":{ + "chain_en_const_U132":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U113":{ - "modref":"global.affine_controller__U56", + "ctrl__U104":{ + "modref":"global.affine_controller__U47", "metadata":{"garnet_remove":true} }, - "ctrl__U40":{ - "modref":"global.affine_controller__U17", + "ctrl__U31":{ + "modref":"global.affine_controller__U8", "metadata":{"garnet_remove":true} }, "input_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","input_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,240,8064,16128,32256,64512],"dimensionality":7,"extent":[8,30,30,2,2,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,928,8,0,448,25984]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[53824],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U16"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,240,8064,16128,32256,64512],"dimensionality":7,"extent":[8,30,30,2,2,2,2],"read_data_starting_addr":[0],"read_data_stride":[1,16,928,8,0,448,25984]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[53824],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U113.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U140.d"], - ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U140.out"], - ["ctrl__U40.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.d"], - ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U55.out"], - ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U141.out"], - ["self.clk","ctrl__U113.clk"], - ["self.reset","ctrl__U113.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U113.valid"], - ["self.clk","ctrl__U40.clk"], - ["self.reset","ctrl__U40.rst_n"], - ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U40.valid"], + ["ctrl__U104.d","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U131.d"], + ["input_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_input_glb_stencil_op_hcompute_input_cgra_stencil_161_U131.out"], + ["ctrl__U31.d","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.d"], + ["input_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_input_glb_stencil_op_hcompute_input_glb_stencil_158_U46.out"], + ["input_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U132.out"], + ["self.clk","ctrl__U104.clk"], + ["self.reset","ctrl__U104.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U104.valid"], + ["self.clk","ctrl__U31.clk"], + ["self.reset","ctrl__U31.rst_n"], + ["input_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U31.valid"], ["self.clk","input_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_input_glb_stencil_write.0","input_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_input_cgra_stencil_read.0","input_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -7855,266 +7815,10 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54017],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U142"} + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54017],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53824],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -8122,13 +7826,13 @@ }, "ub_kernel_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54025],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53832],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U144"} + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54025],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53832],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54034],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53841],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U162"} + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54034],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53841],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -8136,8 +7840,8 @@ }, "ub_kernel_cgra_stencil_BANK_11":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54042],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53849],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U164"} + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54042],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53849],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -8145,8 +7849,8 @@ }, "ub_kernel_cgra_stencil_BANK_12":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54050],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53857],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U166"} + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54050],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53857],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -8154,8 +7858,8 @@ }, "ub_kernel_cgra_stencil_BANK_13":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54058],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53865],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U168"} + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54058],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53865],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -8163,8 +7867,8 @@ }, "ub_kernel_cgra_stencil_BANK_14":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54066],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53873],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U170"} + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54066],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53873],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -8172,8 +7876,8 @@ }, "ub_kernel_cgra_stencil_BANK_15":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54074],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53881],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U172"} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54074],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53881],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -8181,8 +7885,8 @@ }, "ub_kernel_cgra_stencil_BANK_16":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54019],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U174"} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54019],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53826],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -8190,8 +7894,8 @@ }, "ub_kernel_cgra_stencil_BANK_17":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54027],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53834],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U176"} + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54027],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53834],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -8199,8 +7903,8 @@ }, "ub_kernel_cgra_stencil_BANK_18":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54035],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53842],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U178"} + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54035],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53842],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -8208,8 +7912,8 @@ }, "ub_kernel_cgra_stencil_BANK_19":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54043],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53850],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U180"} + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54043],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53850],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -8221,13 +7925,13 @@ }, "ub_kernel_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54033],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53840],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U146"} + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54033],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53840],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54051],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53858],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U182"} + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54051],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53858],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -8235,8 +7939,8 @@ }, "ub_kernel_cgra_stencil_BANK_21":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54059],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53866],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U184"} + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54059],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53866],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -8244,8 +7948,8 @@ }, "ub_kernel_cgra_stencil_BANK_22":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54067],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53874],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U186"} + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54067],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53874],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -8253,8 +7957,8 @@ }, "ub_kernel_cgra_stencil_BANK_23":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54075],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53882],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U188"} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54075],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53882],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -8262,8 +7966,8 @@ }, "ub_kernel_cgra_stencil_BANK_24":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54020],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U190"} + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54020],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53827],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const":{ "modref":"corebit.const", @@ -8271,8 +7975,8 @@ }, "ub_kernel_cgra_stencil_BANK_25":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54028],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53835],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U192"} + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54028],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53835],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const":{ "modref":"corebit.const", @@ -8280,8 +7984,8 @@ }, "ub_kernel_cgra_stencil_BANK_26":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54036],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53843],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U194"} + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54036],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53843],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const":{ "modref":"corebit.const", @@ -8289,8 +7993,8 @@ }, "ub_kernel_cgra_stencil_BANK_27":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54044],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53851],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U196"} + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54044],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53851],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const":{ "modref":"corebit.const", @@ -8298,8 +8002,8 @@ }, "ub_kernel_cgra_stencil_BANK_28":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54052],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53859],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U198"} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54052],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53859],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const":{ "modref":"corebit.const", @@ -8307,8 +8011,8 @@ }, "ub_kernel_cgra_stencil_BANK_29":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54060],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53867],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U200"} + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54060],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53867],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const":{ "modref":"corebit.const", @@ -8320,13 +8024,13 @@ }, "ub_kernel_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54041],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53848],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U148"} + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54041],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53848],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54068],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53875],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U202"} + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54068],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53875],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const":{ "modref":"corebit.const", @@ -8334,8 +8038,8 @@ }, "ub_kernel_cgra_stencil_BANK_31":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54076],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53883],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U204"} + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54076],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53883],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const":{ "modref":"corebit.const", @@ -8343,8 +8047,8 @@ }, "ub_kernel_cgra_stencil_BANK_32":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54021],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U206"} + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54021],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53828],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const":{ "modref":"corebit.const", @@ -8352,8 +8056,8 @@ }, "ub_kernel_cgra_stencil_BANK_33":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54029],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53836],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U208"} + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54029],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53836],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const":{ "modref":"corebit.const", @@ -8361,8 +8065,8 @@ }, "ub_kernel_cgra_stencil_BANK_34":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54037],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53844],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U210"} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54037],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53844],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const":{ "modref":"corebit.const", @@ -8370,8 +8074,8 @@ }, "ub_kernel_cgra_stencil_BANK_35":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54045],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53852],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U212"} + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54045],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53852],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const":{ "modref":"corebit.const", @@ -8379,8 +8083,8 @@ }, "ub_kernel_cgra_stencil_BANK_36":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54053],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53860],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U214"} + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54053],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53860],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const":{ "modref":"corebit.const", @@ -8388,8 +8092,8 @@ }, "ub_kernel_cgra_stencil_BANK_37":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54061],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53868],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U216"} + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54061],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53868],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const":{ "modref":"corebit.const", @@ -8397,8 +8101,8 @@ }, "ub_kernel_cgra_stencil_BANK_38":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54069],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53876],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U218"} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54069],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53876],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const":{ "modref":"corebit.const", @@ -8406,8 +8110,8 @@ }, "ub_kernel_cgra_stencil_BANK_39":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54077],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53884],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U220"} + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54077],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53884],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const":{ "modref":"corebit.const", @@ -8419,13 +8123,13 @@ }, "ub_kernel_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54049],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53856],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U150"} + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54049],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53856],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54022],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U222"} + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54022],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53829],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const":{ "modref":"corebit.const", @@ -8433,8 +8137,8 @@ }, "ub_kernel_cgra_stencil_BANK_41":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54030],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53837],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U224"} + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54030],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53837],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const":{ "modref":"corebit.const", @@ -8442,8 +8146,8 @@ }, "ub_kernel_cgra_stencil_BANK_42":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54038],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53845],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U226"} + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54038],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53845],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const":{ "modref":"corebit.const", @@ -8451,8 +8155,8 @@ }, "ub_kernel_cgra_stencil_BANK_43":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54046],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53853],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U228"} + "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54046],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53853],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const":{ "modref":"corebit.const", @@ -8460,8 +8164,8 @@ }, "ub_kernel_cgra_stencil_BANK_44":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54054],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53861],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U230"} + "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54054],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53861],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const":{ "modref":"corebit.const", @@ -8469,8 +8173,8 @@ }, "ub_kernel_cgra_stencil_BANK_45":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54062],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53869],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U232"} + "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54062],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53869],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const":{ "modref":"corebit.const", @@ -8478,8 +8182,8 @@ }, "ub_kernel_cgra_stencil_BANK_46":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54070],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53877],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U234"} + "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54070],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53877],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const":{ "modref":"corebit.const", @@ -8487,8 +8191,8 @@ }, "ub_kernel_cgra_stencil_BANK_47":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54078],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53885],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U236"} + "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54078],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53885],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const":{ "modref":"corebit.const", @@ -8496,8 +8200,8 @@ }, "ub_kernel_cgra_stencil_BANK_48":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54023],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U238"} + "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54023],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53830],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const":{ "modref":"corebit.const", @@ -8505,8 +8209,8 @@ }, "ub_kernel_cgra_stencil_BANK_49":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54031],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53838],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U240"} + "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54031],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53838],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const":{ "modref":"corebit.const", @@ -8518,13 +8222,13 @@ }, "ub_kernel_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54057],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53864],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U152"} + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54057],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53864],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54039],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53846],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U242"} + "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54039],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53846],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const":{ "modref":"corebit.const", @@ -8532,8 +8236,8 @@ }, "ub_kernel_cgra_stencil_BANK_51":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54047],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53854],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U244"} + "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54047],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53854],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const":{ "modref":"corebit.const", @@ -8541,8 +8245,8 @@ }, "ub_kernel_cgra_stencil_BANK_52":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54055],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53862],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U246"} + "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54055],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53862],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const":{ "modref":"corebit.const", @@ -8550,8 +8254,8 @@ }, "ub_kernel_cgra_stencil_BANK_53":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54063],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53870],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U248"} + "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54063],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53870],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const":{ "modref":"corebit.const", @@ -8559,8 +8263,8 @@ }, "ub_kernel_cgra_stencil_BANK_54":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54071],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53878],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U250"} + "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54071],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53878],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const":{ "modref":"corebit.const", @@ -8568,8 +8272,8 @@ }, "ub_kernel_cgra_stencil_BANK_55":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54079],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53886],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U252"} + "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54079],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53886],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const":{ "modref":"corebit.const", @@ -8577,8 +8281,8 @@ }, "ub_kernel_cgra_stencil_BANK_56":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54024],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U254"} + "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54024],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53831],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const":{ "modref":"corebit.const", @@ -8586,8 +8290,8 @@ }, "ub_kernel_cgra_stencil_BANK_57":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54032],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53839],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U256"} + "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54032],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53839],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const":{ "modref":"corebit.const", @@ -8595,8 +8299,8 @@ }, "ub_kernel_cgra_stencil_BANK_58":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54040],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53847],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U258"} + "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54040],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53847],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const":{ "modref":"corebit.const", @@ -8604,8 +8308,8 @@ }, "ub_kernel_cgra_stencil_BANK_59":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54048],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53855],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U260"} + "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54048],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53855],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const":{ "modref":"corebit.const", @@ -8617,13 +8321,13 @@ }, "ub_kernel_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54065],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53872],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U154"} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54065],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53872],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54056],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53863],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U262"} + "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54056],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53863],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const":{ "modref":"corebit.const", @@ -8631,8 +8335,8 @@ }, "ub_kernel_cgra_stencil_BANK_61":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54064],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53871],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U264"} + "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54064],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53871],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const":{ "modref":"corebit.const", @@ -8640,8 +8344,8 @@ }, "ub_kernel_cgra_stencil_BANK_62":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54072],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53879],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U266"} + "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54072],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53879],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const":{ "modref":"corebit.const", @@ -8649,8 +8353,8 @@ }, "ub_kernel_cgra_stencil_BANK_63":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54080],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53887],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U268"} + "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54080],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53887],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const":{ "modref":"corebit.const", @@ -8662,8 +8366,8 @@ }, "ub_kernel_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54073],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53880],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U156"} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54073],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53880],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -8671,8 +8375,8 @@ }, "ub_kernel_cgra_stencil_BANK_8":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54018],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U158"} + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54018],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53825],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -8680,8 +8384,8 @@ }, "ub_kernel_cgra_stencil_BANK_9":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54026],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53833],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake","verilog_name":"lake__U160"} + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[54026],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53833],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[61026],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[61028],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}},"mode":"lake"} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", @@ -8689,70 +8393,6 @@ } }, "connections":[ - ["ub_kernel_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U143.out"], - ["ub_kernel_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U145.out"], - ["ub_kernel_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U147.out"], - ["ub_kernel_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U149.out"], - ["ub_kernel_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U151.out"], - ["ub_kernel_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U153.out"], - ["ub_kernel_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U155.out"], - ["ub_kernel_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U157.out"], - ["ub_kernel_cgra_stencil_BANK_8.chain_chain_en","chain_en_const_U159.out"], - ["ub_kernel_cgra_stencil_BANK_9.chain_chain_en","chain_en_const_U161.out"], - ["ub_kernel_cgra_stencil_BANK_10.chain_chain_en","chain_en_const_U163.out"], - ["ub_kernel_cgra_stencil_BANK_11.chain_chain_en","chain_en_const_U165.out"], - ["ub_kernel_cgra_stencil_BANK_12.chain_chain_en","chain_en_const_U167.out"], - ["ub_kernel_cgra_stencil_BANK_13.chain_chain_en","chain_en_const_U169.out"], - ["ub_kernel_cgra_stencil_BANK_14.chain_chain_en","chain_en_const_U171.out"], - ["ub_kernel_cgra_stencil_BANK_15.chain_chain_en","chain_en_const_U173.out"], - ["ub_kernel_cgra_stencil_BANK_16.chain_chain_en","chain_en_const_U175.out"], - ["ub_kernel_cgra_stencil_BANK_17.chain_chain_en","chain_en_const_U177.out"], - ["ub_kernel_cgra_stencil_BANK_18.chain_chain_en","chain_en_const_U179.out"], - ["ub_kernel_cgra_stencil_BANK_19.chain_chain_en","chain_en_const_U181.out"], - ["ub_kernel_cgra_stencil_BANK_20.chain_chain_en","chain_en_const_U183.out"], - ["ub_kernel_cgra_stencil_BANK_21.chain_chain_en","chain_en_const_U185.out"], - ["ub_kernel_cgra_stencil_BANK_22.chain_chain_en","chain_en_const_U187.out"], - ["ub_kernel_cgra_stencil_BANK_23.chain_chain_en","chain_en_const_U189.out"], - ["ub_kernel_cgra_stencil_BANK_24.chain_chain_en","chain_en_const_U191.out"], - ["ub_kernel_cgra_stencil_BANK_25.chain_chain_en","chain_en_const_U193.out"], - ["ub_kernel_cgra_stencil_BANK_26.chain_chain_en","chain_en_const_U195.out"], - ["ub_kernel_cgra_stencil_BANK_27.chain_chain_en","chain_en_const_U197.out"], - ["ub_kernel_cgra_stencil_BANK_28.chain_chain_en","chain_en_const_U199.out"], - ["ub_kernel_cgra_stencil_BANK_29.chain_chain_en","chain_en_const_U201.out"], - ["ub_kernel_cgra_stencil_BANK_30.chain_chain_en","chain_en_const_U203.out"], - ["ub_kernel_cgra_stencil_BANK_31.chain_chain_en","chain_en_const_U205.out"], - ["ub_kernel_cgra_stencil_BANK_32.chain_chain_en","chain_en_const_U207.out"], - ["ub_kernel_cgra_stencil_BANK_33.chain_chain_en","chain_en_const_U209.out"], - ["ub_kernel_cgra_stencil_BANK_34.chain_chain_en","chain_en_const_U211.out"], - ["ub_kernel_cgra_stencil_BANK_35.chain_chain_en","chain_en_const_U213.out"], - ["ub_kernel_cgra_stencil_BANK_36.chain_chain_en","chain_en_const_U215.out"], - ["ub_kernel_cgra_stencil_BANK_37.chain_chain_en","chain_en_const_U217.out"], - ["ub_kernel_cgra_stencil_BANK_38.chain_chain_en","chain_en_const_U219.out"], - ["ub_kernel_cgra_stencil_BANK_39.chain_chain_en","chain_en_const_U221.out"], - ["ub_kernel_cgra_stencil_BANK_40.chain_chain_en","chain_en_const_U223.out"], - ["ub_kernel_cgra_stencil_BANK_41.chain_chain_en","chain_en_const_U225.out"], - ["ub_kernel_cgra_stencil_BANK_42.chain_chain_en","chain_en_const_U227.out"], - ["ub_kernel_cgra_stencil_BANK_43.chain_chain_en","chain_en_const_U229.out"], - ["ub_kernel_cgra_stencil_BANK_44.chain_chain_en","chain_en_const_U231.out"], - ["ub_kernel_cgra_stencil_BANK_45.chain_chain_en","chain_en_const_U233.out"], - ["ub_kernel_cgra_stencil_BANK_46.chain_chain_en","chain_en_const_U235.out"], - ["ub_kernel_cgra_stencil_BANK_47.chain_chain_en","chain_en_const_U237.out"], - ["ub_kernel_cgra_stencil_BANK_48.chain_chain_en","chain_en_const_U239.out"], - ["ub_kernel_cgra_stencil_BANK_49.chain_chain_en","chain_en_const_U241.out"], - ["ub_kernel_cgra_stencil_BANK_50.chain_chain_en","chain_en_const_U243.out"], - ["ub_kernel_cgra_stencil_BANK_51.chain_chain_en","chain_en_const_U245.out"], - ["ub_kernel_cgra_stencil_BANK_52.chain_chain_en","chain_en_const_U247.out"], - ["ub_kernel_cgra_stencil_BANK_53.chain_chain_en","chain_en_const_U249.out"], - ["ub_kernel_cgra_stencil_BANK_54.chain_chain_en","chain_en_const_U251.out"], - ["ub_kernel_cgra_stencil_BANK_55.chain_chain_en","chain_en_const_U253.out"], - ["ub_kernel_cgra_stencil_BANK_56.chain_chain_en","chain_en_const_U255.out"], - ["ub_kernel_cgra_stencil_BANK_57.chain_chain_en","chain_en_const_U257.out"], - ["ub_kernel_cgra_stencil_BANK_58.chain_chain_en","chain_en_const_U259.out"], - ["ub_kernel_cgra_stencil_BANK_59.chain_chain_en","chain_en_const_U261.out"], - ["ub_kernel_cgra_stencil_BANK_60.chain_chain_en","chain_en_const_U263.out"], - ["ub_kernel_cgra_stencil_BANK_61.chain_chain_en","chain_en_const_U265.out"], - ["ub_kernel_cgra_stencil_BANK_62.chain_chain_en","chain_en_const_U267.out"], - ["ub_kernel_cgra_stencil_BANK_63.chain_chain_en","chain_en_const_U269.out"], ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_1.clk","self.clk"], ["ub_kernel_cgra_stencil_BANK_10.clk","self.clk"], @@ -9150,49 +8790,49 @@ ["op_hcompute_kernel_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U418":{ - "modref":"global.aff__U389" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U344":{ + "modref":"global.aff__U315" }, - "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U319":{ - "modref":"global.aff__U302" + "addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U245":{ + "modref":"global.aff__U228" }, - "chain_en_const_U419":{ + "chain_en_const_U345":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U301":{ - "modref":"global.affine_controller__U271", + "ctrl__U227":{ + "modref":"global.affine_controller__U197", "metadata":{"garnet_remove":true} }, - "ctrl__U388":{ - "modref":"global.affine_controller__U320", + "ctrl__U314":{ + "modref":"global.affine_controller__U246", "metadata":{"garnet_remove":true} }, "kernel_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","kernel_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,64,8064,16128,32256],"dimensionality":6,"extent":[8,8,9,2,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,16,256,8,128,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[2304],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb","verilog_name":"glb__U270"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[53824],"cycle_stride":[1,8,64,8064,16128,32256],"dimensionality":6,"extent":[8,8,9,2,2,4],"read_data_starting_addr":[0],"read_data_stride":[1,16,256,8,128,0]},"in2glb_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[2304],"write_data_starting_addr":[0],"write_data_stride":[1]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U388.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U418.d"], - ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U418.out"], - ["ctrl__U301.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U319.d"], - ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U319.out"], - ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U419.out"], - ["self.clk","ctrl__U301.clk"], - ["self.reset","ctrl__U301.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U301.valid"], - ["self.clk","ctrl__U388.clk"], - ["self.reset","ctrl__U388.rst_n"], - ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U388.valid"], + ["ctrl__U314.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U344.d"], + ["kernel_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_cgra_stencil_157_U344.out"], + ["ctrl__U227.d","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U245.d"], + ["kernel_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_kernel_glb_stencil_op_hcompute_kernel_glb_stencil_154_U245.out"], + ["kernel_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U345.out"], + ["self.clk","ctrl__U227.clk"], + ["self.reset","ctrl__U227.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U227.valid"], + ["self.clk","ctrl__U314.clk"], + ["self.reset","ctrl__U314.rst_n"], + ["kernel_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U314.valid"], ["self.clk","kernel_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_kernel_glb_stencil_write.0","kernel_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_kernel_cgra_stencil_read.0","kernel_glb_stencil_BANK_0_ubuf.data_out_0"], ["self.reset","kernel_glb_stencil_BANK_0_ubuf.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U679":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U596":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -9201,7 +8841,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U678":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U595":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9210,7 +8850,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U677":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U594":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -9219,7 +8859,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U676":{ + "op_hcompute_hw_output_stencil_read_start_pt__U593":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9228,7 +8868,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U681":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U598":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -9237,7 +8877,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U680":{ + "op_hcompute_hw_output_stencil_write_start_pt__U597":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9246,7 +8886,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U689":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U606":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9255,7 +8895,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U688":{ + "op_hcompute_input_glb_stencil_read_start_pt__U605":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9264,7 +8904,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U690":{ + "op_hcompute_input_glb_stencil_write_start_pt__U607":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9273,7 +8913,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U684":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U601":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9282,7 +8922,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U683":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U600":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9291,7 +8931,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U685":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U602":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -9357,74 +8997,42 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U434":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U449":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U464":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U479":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U494":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U509":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U524":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U539":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "ctrl__U433":{ - "modref":"global.affine_controller__U421", + "ctrl__U359":{ + "modref":"global.affine_controller__U347", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U448":{ - "modref":"global.affine_controller__U436", + "ctrl__U373":{ + "modref":"global.affine_controller__U361", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U463":{ - "modref":"global.affine_controller__U451", + "ctrl__U387":{ + "modref":"global.affine_controller__U375", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U478":{ - "modref":"global.affine_controller__U466", + "ctrl__U401":{ + "modref":"global.affine_controller__U389", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U493":{ - "modref":"global.affine_controller__U481", + "ctrl__U415":{ + "modref":"global.affine_controller__U403", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U508":{ - "modref":"global.affine_controller__U496", + "ctrl__U429":{ + "modref":"global.affine_controller__U417", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U523":{ - "modref":"global.affine_controller__U511", + "ctrl__U443":{ + "modref":"global.affine_controller__U431", "metadata":{"garnet_rewire_flush":true} }, - "ctrl__U538":{ - "modref":"global.affine_controller__U526", + "ctrl__U457":{ + "modref":"global.affine_controller__U445", "metadata":{"garnet_rewire_flush":true} }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U420"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23326],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U420"} + "genargs":{"ID":["String","_U346"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23326],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -9432,8 +9040,8 @@ }, "ub_output_cgra_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U435"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"agg2sram_1":{"cycle_starting_addr":[7209],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U435"} + "genargs":{"ID":["String","_U360"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"agg2sram_1":{"cycle_starting_addr":[7209],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -9441,8 +9049,8 @@ }, "ub_output_cgra_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U450"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U450"} + "genargs":{"ID":["String","_U374"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -9450,8 +9058,8 @@ }, "ub_output_cgra_stencil_BANK_3":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U465"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U465"} + "genargs":{"ID":["String","_U388"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -9459,8 +9067,8 @@ }, "ub_output_cgra_stencil_BANK_4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U480"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U480"} + "genargs":{"ID":["String","_U402"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -9468,8 +9076,8 @@ }, "ub_output_cgra_stencil_BANK_5":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U495"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U495"} + "genargs":{"ID":["String","_U416"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -9477,8 +9085,8 @@ }, "ub_output_cgra_stencil_BANK_6":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U510"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23332],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U510"} + "genargs":{"ID":["String","_U430"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23332],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -9486,8 +9094,8 @@ }, "ub_output_cgra_stencil_BANK_7":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U525"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake","verilog_name":"lake__U525"} + "genargs":{"ID":["String","_U444"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} }, "ub_output_cgra_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -9495,30 +9103,22 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U434.out"], - ["ub_output_cgra_stencil_BANK_1.chain_chain_en","chain_en_const_U449.out"], - ["ub_output_cgra_stencil_BANK_2.chain_chain_en","chain_en_const_U464.out"], - ["ub_output_cgra_stencil_BANK_3.chain_chain_en","chain_en_const_U479.out"], - ["ub_output_cgra_stencil_BANK_4.chain_chain_en","chain_en_const_U494.out"], - ["ub_output_cgra_stencil_BANK_5.chain_chain_en","chain_en_const_U509.out"], - ["ub_output_cgra_stencil_BANK_6.chain_chain_en","chain_en_const_U524.out"], - ["ub_output_cgra_stencil_BANK_7.chain_chain_en","chain_en_const_U539.out"], - ["self.clk","ctrl__U433.clk"], - ["ub_output_cgra_stencil_BANK_0.flush","ctrl__U433.valid"], - ["self.clk","ctrl__U448.clk"], - ["ub_output_cgra_stencil_BANK_1.flush","ctrl__U448.valid"], - ["self.clk","ctrl__U463.clk"], - ["ub_output_cgra_stencil_BANK_2.flush","ctrl__U463.valid"], - ["self.clk","ctrl__U478.clk"], - ["ub_output_cgra_stencil_BANK_3.flush","ctrl__U478.valid"], - ["self.clk","ctrl__U493.clk"], - ["ub_output_cgra_stencil_BANK_4.flush","ctrl__U493.valid"], - ["self.clk","ctrl__U508.clk"], - ["ub_output_cgra_stencil_BANK_5.flush","ctrl__U508.valid"], - ["self.clk","ctrl__U523.clk"], - ["ub_output_cgra_stencil_BANK_6.flush","ctrl__U523.valid"], - ["self.clk","ctrl__U538.clk"], - ["ub_output_cgra_stencil_BANK_7.flush","ctrl__U538.valid"], + ["self.clk","ctrl__U359.clk"], + ["ub_output_cgra_stencil_BANK_0.flush","ctrl__U359.valid"], + ["self.clk","ctrl__U373.clk"], + ["ub_output_cgra_stencil_BANK_1.flush","ctrl__U373.valid"], + ["self.clk","ctrl__U387.clk"], + ["ub_output_cgra_stencil_BANK_2.flush","ctrl__U387.valid"], + ["self.clk","ctrl__U401.clk"], + ["ub_output_cgra_stencil_BANK_3.flush","ctrl__U401.valid"], + ["self.clk","ctrl__U415.clk"], + ["ub_output_cgra_stencil_BANK_4.flush","ctrl__U415.valid"], + ["self.clk","ctrl__U429.clk"], + ["ub_output_cgra_stencil_BANK_5.flush","ctrl__U429.valid"], + ["self.clk","ctrl__U443.clk"], + ["ub_output_cgra_stencil_BANK_6.flush","ctrl__U443.valid"], + ["self.clk","ctrl__U457.clk"], + ["ub_output_cgra_stencil_BANK_7.flush","ctrl__U457.valid"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], @@ -9588,42 +9188,42 @@ ["op_hcompute_output_glb_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U651":{ - "modref":"global.aff__U637" + "addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U568":{ + "modref":"global.aff__U554" }, - "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U612":{ - "modref":"global.aff__U589" + "addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U529":{ + "modref":"global.aff__U506" }, - "chain_en_const_U652":{ + "chain_en_const_U569":{ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "ctrl__U588":{ - "modref":"global.affine_controller__U541", + "ctrl__U505":{ + "modref":"global.affine_controller__U458", "metadata":{"garnet_remove":true} }, - "ctrl__U636":{ - "modref":"global.affine_controller__U613", + "ctrl__U553":{ + "modref":"global.affine_controller__U530", "metadata":{"garnet_remove":true} }, "output_glb_stencil_BANK_0_ubuf":{ "genref":"cgralib.Mem_amber", "genargs":{"ID":["String","output_glb_stencil_BANK_0"], "ctrl_width":["Int",32], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",true], "has_flush":["Bool",false], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",false], "width":["Int",16]}, - "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[196320],"cycle_stride":[1],"dimensionality":1,"extent":[50176],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[77152],"cycle_stride":[1,8,224,16128,32256,64512],"dimensionality":6,"extent":[8,28,28,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,16,896,8,448,25088]}},"mode":"glb","verilog_name":"glb__U540"} + "metadata":{"config":{"glb2out_0":{"cycle_starting_addr":[196320],"cycle_stride":[1],"dimensionality":1,"extent":[50176],"read_data_starting_addr":[0],"read_data_stride":[1]},"in2glb_0":{"cycle_starting_addr":[77152],"cycle_stride":[1,8,224,16128,32256,64512],"dimensionality":6,"extent":[8,28,28,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,16,896,8,448,25088]}},"mode":"glb"} } }, "connections":[ - ["ctrl__U636.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U651.d"], - ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U651.out"], - ["ctrl__U588.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U612.d"], - ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U612.out"], - ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U652.out"], - ["self.clk","ctrl__U588.clk"], - ["self.reset","ctrl__U588.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U588.valid"], - ["self.clk","ctrl__U636.clk"], - ["self.reset","ctrl__U636.rst_n"], - ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U636.valid"], + ["ctrl__U553.d","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U568.d"], + ["output_glb_stencil_BANK_0_ubuf.read_addr_0","addrgen_output_glb_stencil_op_hcompute_hw_output_stencil_163_U568.out"], + ["ctrl__U505.d","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U529.d"], + ["output_glb_stencil_BANK_0_ubuf.write_addr_0","addrgen_output_glb_stencil_op_hcompute_output_glb_stencil_0_U529.out"], + ["output_glb_stencil_BANK_0_ubuf.chain_chain_en","chain_en_const_U569.out"], + ["self.clk","ctrl__U505.clk"], + ["self.reset","ctrl__U505.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.wen_0","ctrl__U505.valid"], + ["self.clk","ctrl__U553.clk"], + ["self.reset","ctrl__U553.rst_n"], + ["output_glb_stencil_BANK_0_ubuf.ren_0","ctrl__U553.valid"], ["self.clk","output_glb_stencil_BANK_0_ubuf.clk"], ["self.op_hcompute_output_glb_stencil_write.0","output_glb_stencil_BANK_0_ubuf.data_in_0"], ["self.op_hcompute_hw_output_stencil_read.0","output_glb_stencil_BANK_0_ubuf.data_out_0"], @@ -9642,12 +9242,12 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U686":{ + "_U603":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U691":{ + "_U608":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -9668,26 +9268,26 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U678" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U595" }, "op_hcompute_hw_output_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U679" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U596" }, "op_hcompute_hw_output_stencil_port_controller":{ - "modref":"global.affine_controller__U653", + "modref":"global.affine_controller__U570", "metadata":{"lake_config":{"stencil_valid":{"cycle_starting_addr":[196320],"cycle_stride":[1,16,896],"dimensionality":3,"extent":[16,56,56]}}} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U676" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U593" }, "op_hcompute_hw_output_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U677" + "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U594" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U680" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U597" }, "op_hcompute_hw_output_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U681" + "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U598" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" @@ -9696,22 +9296,22 @@ "modref":"global.cu_op_hcompute_input_glb_stencil" }, "op_hcompute_input_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U689" + "modref":"global.op_hcompute_input_glb_stencil_exe_start_pt__U606" }, "op_hcompute_input_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U687"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,928],"dimensionality":3,"extent":[16,58,58]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U687"} + "genargs":{"ID":["String","_U604"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,928],"dimensionality":3,"extent":[16,58,58]}},"mode":"lake"} }, "op_hcompute_input_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_glb_stencil_read_start":{ - "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U688" + "modref":"global.op_hcompute_input_glb_stencil_read_start_pt__U605" }, "op_hcompute_input_glb_stencil_write_start":{ - "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U690" + "modref":"global.op_hcompute_input_glb_stencil_write_start_pt__U607" }, "op_hcompute_kernel_cgra_stencil":{ "modref":"global.cu_op_hcompute_kernel_cgra_stencil" @@ -9720,22 +9320,22 @@ "modref":"global.cu_op_hcompute_kernel_glb_stencil" }, "op_hcompute_kernel_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U684" + "modref":"global.op_hcompute_kernel_glb_stencil_exe_start_pt__U601" }, "op_hcompute_kernel_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U682"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,256,768],"dimensionality":4,"extent":[16,16,3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U682"} + "genargs":{"ID":["String","_U599"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16,256,768],"dimensionality":4,"extent":[16,16,3,3]}},"mode":"lake"} }, "op_hcompute_kernel_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_kernel_glb_stencil_read_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U683" + "modref":"global.op_hcompute_kernel_glb_stencil_read_start_pt__U600" }, "op_hcompute_kernel_glb_stencil_write_start":{ - "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U685" + "modref":"global.op_hcompute_kernel_glb_stencil_write_start_pt__U602" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -9796,10 +9396,10 @@ } }, "connections":[ - ["self.clk","_U686.clk"], - ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U686.in"], - ["self.clk","_U691.clk"], - ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U691.in"], + ["self.clk","_U603.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_glb_stencil_read.0","_U603.in"], + ["self.clk","_U608.clk"], + ["self.input_host_stencil_op_hcompute_input_glb_stencil_read.0","_U608.in"], ["self.clk","input_cgra_stencil.clk"], ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], ["op_hcompute_output_cgra_stencil_10.input_cgra_stencil_op_hcompute_output_cgra_stencil_10_read","input_cgra_stencil.op_hcompute_output_cgra_stencil_10_read"], diff --git a/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile_garnet.json b/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile_garnet.json index 974754a33..17b1c94a5 100644 --- a/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile_garnet.json +++ b/aha_garnet_design_new/resnet_init_unroll_tile/resnet_init_unroll_tile_garnet.json @@ -232,2027 +232,2045 @@ }, "global":{ "modules":{ - "aff__U114":{ + "aff__U105":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U132":{ + "add_all__U123":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U133":{ + "add_all__U124":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U134":{ + "add_all__U125":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U135":{ + "add_all__U126":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U136":{ + "add_all__U127":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U137":{ + "add_all__U128":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U138":{ + "add_all__U129":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U139":{ + "add_all__U130":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U115":{ + "coeff_0_U106":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U117":{ + "coeff_1_U108":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_2_U119":{ + "coeff_2_U110":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000658"]} }, - "coeff_3_U121":{ + "coeff_3_U112":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_4_U123":{ + "coeff_4_U114":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006920"]} }, - "coeff_5_U125":{ + "coeff_5_U116":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U127":{ + "coeff_6_U118":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000003a"]} }, - "coeff_7_U129":{ + "coeff_7_U120":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000d24"]} }, - "const_term_U131":{ + "const_term_U122":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U116":{ + "mul_d0__U107":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U118":{ + "mul_d1__U109":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U120":{ + "mul_d2__U111":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U122":{ + "mul_d3__U113":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U124":{ + "mul_d4__U115":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U126":{ + "mul_d5__U117":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U128":{ + "mul_d6__U119":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U130":{ + "mul_d7__U121":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U116.out","add_all__U132.in0"], - ["mul_d1__U118.out","add_all__U132.in1"], - ["add_all__U133.in0","add_all__U132.out"], - ["mul_d2__U120.out","add_all__U133.in1"], - ["add_all__U134.in0","add_all__U133.out"], - ["mul_d3__U122.out","add_all__U134.in1"], - ["add_all__U135.in0","add_all__U134.out"], - ["mul_d4__U124.out","add_all__U135.in1"], - ["add_all__U136.in0","add_all__U135.out"], - ["mul_d5__U126.out","add_all__U136.in1"], - ["add_all__U137.in0","add_all__U136.out"], - ["mul_d6__U128.out","add_all__U137.in1"], - ["add_all__U138.in0","add_all__U137.out"], - ["mul_d7__U130.out","add_all__U138.in1"], - ["add_all__U139.in0","add_all__U138.out"], - ["const_term_U131.out","add_all__U139.in1"], - ["self.out","add_all__U139.out"], - ["mul_d0__U116.in0","coeff_0_U115.out"], - ["mul_d1__U118.in0","coeff_1_U117.out"], - ["mul_d2__U120.in0","coeff_2_U119.out"], - ["mul_d3__U122.in0","coeff_3_U121.out"], - ["mul_d4__U124.in0","coeff_4_U123.out"], - ["mul_d5__U126.in0","coeff_5_U125.out"], - ["mul_d6__U128.in0","coeff_6_U127.out"], - ["mul_d7__U130.in0","coeff_7_U129.out"], - ["self.d.0","mul_d0__U116.in1"], - ["self.d.1","mul_d1__U118.in1"], - ["self.d.2","mul_d2__U120.in1"], - ["self.d.3","mul_d3__U122.in1"], - ["self.d.4","mul_d4__U124.in1"], - ["self.d.5","mul_d5__U126.in1"], - ["self.d.6","mul_d6__U128.in1"], - ["self.d.7","mul_d7__U130.in1"] + ["mul_d0__U107.out","add_all__U123.in0"], + ["mul_d1__U109.out","add_all__U123.in1"], + ["add_all__U124.in0","add_all__U123.out"], + ["mul_d2__U111.out","add_all__U124.in1"], + ["add_all__U125.in0","add_all__U124.out"], + ["mul_d3__U113.out","add_all__U125.in1"], + ["add_all__U126.in0","add_all__U125.out"], + ["mul_d4__U115.out","add_all__U126.in1"], + ["add_all__U127.in0","add_all__U126.out"], + ["mul_d5__U117.out","add_all__U127.in1"], + ["add_all__U128.in0","add_all__U127.out"], + ["mul_d6__U119.out","add_all__U128.in1"], + ["add_all__U129.in0","add_all__U128.out"], + ["mul_d7__U121.out","add_all__U129.in1"], + ["add_all__U130.in0","add_all__U129.out"], + ["const_term_U122.out","add_all__U130.in1"], + ["self.out","add_all__U130.out"], + ["mul_d0__U107.in0","coeff_0_U106.out"], + ["mul_d1__U109.in0","coeff_1_U108.out"], + ["mul_d2__U111.in0","coeff_2_U110.out"], + ["mul_d3__U113.in0","coeff_3_U112.out"], + ["mul_d4__U115.in0","coeff_4_U114.out"], + ["mul_d5__U117.in0","coeff_5_U116.out"], + ["mul_d6__U119.in0","coeff_6_U118.out"], + ["mul_d7__U121.in0","coeff_7_U120.out"], + ["self.d.0","mul_d0__U107.in1"], + ["self.d.1","mul_d1__U109.in1"], + ["self.d.2","mul_d2__U111.in1"], + ["self.d.3","mul_d3__U113.in1"], + ["self.d.4","mul_d4__U115.in1"], + ["self.d.5","mul_d5__U117.in1"], + ["self.d.6","mul_d6__U119.in1"], + ["self.d.7","mul_d7__U121.in1"] ] }, - "aff__U18":{ - "type":["Record",[ - ["out",["Array",32,"Bit"]], - ["d",["Array",4,["Array",32,"BitIn"]]] - ]], - "instances":{ - "add_all__U28":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U29":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U30":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "add_all__U31":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "coeff_0_U19":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "coeff_1_U21":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000003a0"]} - }, - "coeff_2_U23":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} - }, - "coeff_3_U25":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "const_term_U27":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "mul_d0__U20":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d1__U22":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d2__U24":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "mul_d3__U26":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - } - }, - "connections":[ - ["mul_d0__U20.out","add_all__U28.in0"], - ["mul_d1__U22.out","add_all__U28.in1"], - ["add_all__U29.in0","add_all__U28.out"], - ["mul_d2__U24.out","add_all__U29.in1"], - ["add_all__U30.in0","add_all__U29.out"], - ["mul_d3__U26.out","add_all__U30.in1"], - ["add_all__U31.in0","add_all__U30.out"], - ["const_term_U27.out","add_all__U31.in1"], - ["self.out","add_all__U31.out"], - ["mul_d0__U20.in0","coeff_0_U19.out"], - ["mul_d1__U22.in0","coeff_1_U21.out"], - ["mul_d2__U24.in0","coeff_2_U23.out"], - ["mul_d3__U26.in0","coeff_3_U25.out"], - ["self.d.0","mul_d0__U20.in1"], - ["self.d.1","mul_d1__U22.in1"], - ["self.d.2","mul_d2__U24.in1"], - ["self.d.3","mul_d3__U26.in1"] - ] - }, - "aff__U272":{ + "aff__U198":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U284":{ + "add_all__U210":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U285":{ + "add_all__U211":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U286":{ + "add_all__U212":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U287":{ + "add_all__U213":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U288":{ + "add_all__U214":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U273":{ + "coeff_0_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U275":{ + "coeff_1_U201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000300"]} }, - "coeff_2_U277":{ + "coeff_2_U203":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "coeff_3_U279":{ + "coeff_3_U205":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_4_U281":{ + "coeff_4_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U283":{ + "const_term_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U274":{ + "mul_d0__U200":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U276":{ + "mul_d1__U202":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U278":{ + "mul_d2__U204":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U280":{ + "mul_d3__U206":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U282":{ + "mul_d4__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U274.out","add_all__U284.in0"], - ["mul_d1__U276.out","add_all__U284.in1"], - ["add_all__U285.in0","add_all__U284.out"], - ["mul_d2__U278.out","add_all__U285.in1"], - ["add_all__U286.in0","add_all__U285.out"], - ["mul_d3__U280.out","add_all__U286.in1"], - ["add_all__U287.in0","add_all__U286.out"], - ["mul_d4__U282.out","add_all__U287.in1"], - ["add_all__U288.in0","add_all__U287.out"], - ["const_term_U283.out","add_all__U288.in1"], - ["self.out","add_all__U288.out"], - ["mul_d0__U274.in0","coeff_0_U273.out"], - ["mul_d1__U276.in0","coeff_1_U275.out"], - ["mul_d2__U278.in0","coeff_2_U277.out"], - ["mul_d3__U280.in0","coeff_3_U279.out"], - ["mul_d4__U282.in0","coeff_4_U281.out"], - ["self.d.0","mul_d0__U274.in1"], - ["self.d.1","mul_d1__U276.in1"], - ["self.d.2","mul_d2__U278.in1"], - ["self.d.3","mul_d3__U280.in1"], - ["self.d.4","mul_d4__U282.in1"] + ["mul_d0__U200.out","add_all__U210.in0"], + ["mul_d1__U202.out","add_all__U210.in1"], + ["add_all__U211.in0","add_all__U210.out"], + ["mul_d2__U204.out","add_all__U211.in1"], + ["add_all__U212.in0","add_all__U211.out"], + ["mul_d3__U206.out","add_all__U212.in1"], + ["add_all__U213.in0","add_all__U212.out"], + ["mul_d4__U208.out","add_all__U213.in1"], + ["add_all__U214.in0","add_all__U213.out"], + ["const_term_U209.out","add_all__U214.in1"], + ["self.out","add_all__U214.out"], + ["mul_d0__U200.in0","coeff_0_U199.out"], + ["mul_d1__U202.in0","coeff_1_U201.out"], + ["mul_d2__U204.in0","coeff_2_U203.out"], + ["mul_d3__U206.in0","coeff_3_U205.out"], + ["mul_d4__U208.in0","coeff_4_U207.out"], + ["self.d.0","mul_d0__U200.in1"], + ["self.d.1","mul_d1__U202.in1"], + ["self.d.2","mul_d2__U204.in1"], + ["self.d.3","mul_d3__U206.in1"], + ["self.d.4","mul_d4__U208.in1"] ] }, - "aff__U302":{ + "aff__U228":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",5,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U314":{ + "add_all__U240":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U315":{ + "add_all__U241":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U316":{ + "add_all__U242":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U317":{ + "add_all__U243":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U318":{ + "add_all__U244":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U303":{ + "coeff_0_U229":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U305":{ + "coeff_1_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U307":{ + "coeff_2_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_3_U309":{ + "coeff_3_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_4_U311":{ + "coeff_4_U237":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000090"]} }, - "const_term_U313":{ + "const_term_U239":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U304":{ + "mul_d0__U230":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U306":{ + "mul_d1__U232":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U308":{ + "mul_d2__U234":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U310":{ + "mul_d3__U236":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U312":{ + "mul_d4__U238":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U304.out","add_all__U314.in0"], - ["mul_d1__U306.out","add_all__U314.in1"], - ["add_all__U315.in0","add_all__U314.out"], - ["mul_d2__U308.out","add_all__U315.in1"], - ["add_all__U316.in0","add_all__U315.out"], - ["mul_d3__U310.out","add_all__U316.in1"], - ["add_all__U317.in0","add_all__U316.out"], - ["mul_d4__U312.out","add_all__U317.in1"], - ["add_all__U318.in0","add_all__U317.out"], - ["const_term_U313.out","add_all__U318.in1"], - ["self.out","add_all__U318.out"], - ["mul_d0__U304.in0","coeff_0_U303.out"], - ["mul_d1__U306.in0","coeff_1_U305.out"], - ["mul_d2__U308.in0","coeff_2_U307.out"], - ["mul_d3__U310.in0","coeff_3_U309.out"], - ["mul_d4__U312.in0","coeff_4_U311.out"], - ["self.d.0","mul_d0__U304.in1"], - ["self.d.1","mul_d1__U306.in1"], - ["self.d.2","mul_d2__U308.in1"], - ["self.d.3","mul_d3__U310.in1"], - ["self.d.4","mul_d4__U312.in1"] + ["mul_d0__U230.out","add_all__U240.in0"], + ["mul_d1__U232.out","add_all__U240.in1"], + ["add_all__U241.in0","add_all__U240.out"], + ["mul_d2__U234.out","add_all__U241.in1"], + ["add_all__U242.in0","add_all__U241.out"], + ["mul_d3__U236.out","add_all__U242.in1"], + ["add_all__U243.in0","add_all__U242.out"], + ["mul_d4__U238.out","add_all__U243.in1"], + ["add_all__U244.in0","add_all__U243.out"], + ["const_term_U239.out","add_all__U244.in1"], + ["self.out","add_all__U244.out"], + ["mul_d0__U230.in0","coeff_0_U229.out"], + ["mul_d1__U232.in0","coeff_1_U231.out"], + ["mul_d2__U234.in0","coeff_2_U233.out"], + ["mul_d3__U236.in0","coeff_3_U235.out"], + ["mul_d4__U238.in0","coeff_4_U237.out"], + ["self.d.0","mul_d0__U230.in1"], + ["self.d.1","mul_d1__U232.in1"], + ["self.d.2","mul_d2__U234.in1"], + ["self.d.3","mul_d3__U236.in1"], + ["self.d.4","mul_d4__U238.in1"] ] }, - "aff__U321":{ + "aff__U247":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U341":{ + "add_all__U267":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U342":{ + "add_all__U268":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U343":{ + "add_all__U269":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U344":{ + "add_all__U270":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U345":{ + "add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U346":{ + "add_all__U272":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U347":{ + "add_all__U273":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U348":{ + "add_all__U274":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U349":{ + "add_all__U275":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U322":{ + "coeff_0_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U324":{ + "coeff_1_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U326":{ + "coeff_2_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U328":{ + "coeff_3_U254":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U330":{ + "coeff_4_U256":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U332":{ + "coeff_5_U258":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000c0"]} }, - "coeff_6_U334":{ + "coeff_6_U260":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000040"]} }, - "coeff_7_U336":{ + "coeff_7_U262":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_8_U338":{ + "coeff_8_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U340":{ + "const_term_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U323":{ + "mul_d0__U249":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U325":{ + "mul_d1__U251":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U327":{ + "mul_d2__U253":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U329":{ + "mul_d3__U255":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U331":{ + "mul_d4__U257":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U333":{ + "mul_d5__U259":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U335":{ + "mul_d6__U261":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U337":{ + "mul_d7__U263":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U339":{ + "mul_d8__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U323.out","add_all__U341.in0"], - ["mul_d1__U325.out","add_all__U341.in1"], - ["add_all__U342.in0","add_all__U341.out"], - ["mul_d2__U327.out","add_all__U342.in1"], - ["add_all__U343.in0","add_all__U342.out"], - ["mul_d3__U329.out","add_all__U343.in1"], - ["add_all__U344.in0","add_all__U343.out"], - ["mul_d4__U331.out","add_all__U344.in1"], - ["add_all__U345.in0","add_all__U344.out"], - ["mul_d5__U333.out","add_all__U345.in1"], - ["add_all__U346.in0","add_all__U345.out"], - ["mul_d6__U335.out","add_all__U346.in1"], - ["add_all__U347.in0","add_all__U346.out"], - ["mul_d7__U337.out","add_all__U347.in1"], - ["add_all__U348.in0","add_all__U347.out"], - ["mul_d8__U339.out","add_all__U348.in1"], - ["add_all__U349.in0","add_all__U348.out"], - ["const_term_U340.out","add_all__U349.in1"], - ["self.out","add_all__U349.out"], - ["mul_d0__U323.in0","coeff_0_U322.out"], - ["mul_d1__U325.in0","coeff_1_U324.out"], - ["mul_d2__U327.in0","coeff_2_U326.out"], - ["mul_d3__U329.in0","coeff_3_U328.out"], - ["mul_d4__U331.in0","coeff_4_U330.out"], - ["mul_d5__U333.in0","coeff_5_U332.out"], - ["mul_d6__U335.in0","coeff_6_U334.out"], - ["mul_d7__U337.in0","coeff_7_U336.out"], - ["mul_d8__U339.in0","coeff_8_U338.out"], - ["self.d.0","mul_d0__U323.in1"], - ["self.d.1","mul_d1__U325.in1"], - ["self.d.2","mul_d2__U327.in1"], - ["self.d.3","mul_d3__U329.in1"], - ["self.d.4","mul_d4__U331.in1"], - ["self.d.5","mul_d5__U333.in1"], - ["self.d.6","mul_d6__U335.in1"], - ["self.d.7","mul_d7__U337.in1"], - ["self.d.8","mul_d8__U339.in1"] + ["mul_d0__U249.out","add_all__U267.in0"], + ["mul_d1__U251.out","add_all__U267.in1"], + ["add_all__U268.in0","add_all__U267.out"], + ["mul_d2__U253.out","add_all__U268.in1"], + ["add_all__U269.in0","add_all__U268.out"], + ["mul_d3__U255.out","add_all__U269.in1"], + ["add_all__U270.in0","add_all__U269.out"], + ["mul_d4__U257.out","add_all__U270.in1"], + ["add_all__U271.in0","add_all__U270.out"], + ["mul_d5__U259.out","add_all__U271.in1"], + ["add_all__U272.in0","add_all__U271.out"], + ["mul_d6__U261.out","add_all__U272.in1"], + ["add_all__U273.in0","add_all__U272.out"], + ["mul_d7__U263.out","add_all__U273.in1"], + ["add_all__U274.in0","add_all__U273.out"], + ["mul_d8__U265.out","add_all__U274.in1"], + ["add_all__U275.in0","add_all__U274.out"], + ["const_term_U266.out","add_all__U275.in1"], + ["self.out","add_all__U275.out"], + ["mul_d0__U249.in0","coeff_0_U248.out"], + ["mul_d1__U251.in0","coeff_1_U250.out"], + ["mul_d2__U253.in0","coeff_2_U252.out"], + ["mul_d3__U255.in0","coeff_3_U254.out"], + ["mul_d4__U257.in0","coeff_4_U256.out"], + ["mul_d5__U259.in0","coeff_5_U258.out"], + ["mul_d6__U261.in0","coeff_6_U260.out"], + ["mul_d7__U263.in0","coeff_7_U262.out"], + ["mul_d8__U265.in0","coeff_8_U264.out"], + ["self.d.0","mul_d0__U249.in1"], + ["self.d.1","mul_d1__U251.in1"], + ["self.d.2","mul_d2__U253.in1"], + ["self.d.3","mul_d3__U255.in1"], + ["self.d.4","mul_d4__U257.in1"], + ["self.d.5","mul_d5__U259.in1"], + ["self.d.6","mul_d6__U261.in1"], + ["self.d.7","mul_d7__U263.in1"], + ["self.d.8","mul_d8__U265.in1"] ] }, - "aff__U389":{ + "aff__U315":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",9,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U409":{ + "add_all__U335":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U410":{ + "add_all__U336":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U411":{ + "add_all__U337":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U412":{ + "add_all__U338":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U413":{ + "add_all__U339":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U414":{ + "add_all__U340":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U415":{ + "add_all__U341":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U416":{ + "add_all__U342":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U417":{ + "add_all__U343":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U390":{ + "coeff_0_U316":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U392":{ + "coeff_1_U318":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_2_U394":{ + "coeff_2_U320":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_3_U396":{ + "coeff_3_U322":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000048"]} }, - "coeff_4_U398":{ + "coeff_4_U324":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000480"]} }, - "coeff_5_U400":{ + "coeff_5_U326":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_6_U402":{ + "coeff_6_U328":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000003"]} }, - "coeff_7_U404":{ + "coeff_7_U330":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000009"]} }, - "coeff_8_U406":{ + "coeff_8_U332":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000090"]} }, - "const_term_U408":{ + "const_term_U334":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U391":{ + "mul_d0__U317":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U393":{ + "mul_d1__U319":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U395":{ + "mul_d2__U321":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U397":{ + "mul_d3__U323":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U399":{ + "mul_d4__U325":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U401":{ + "mul_d5__U327":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U403":{ + "mul_d6__U329":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U405":{ + "mul_d7__U331":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d8__U407":{ + "mul_d8__U333":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U391.out","add_all__U409.in0"], - ["mul_d1__U393.out","add_all__U409.in1"], - ["add_all__U410.in0","add_all__U409.out"], - ["mul_d2__U395.out","add_all__U410.in1"], - ["add_all__U411.in0","add_all__U410.out"], - ["mul_d3__U397.out","add_all__U411.in1"], - ["add_all__U412.in0","add_all__U411.out"], - ["mul_d4__U399.out","add_all__U412.in1"], - ["add_all__U413.in0","add_all__U412.out"], - ["mul_d5__U401.out","add_all__U413.in1"], - ["add_all__U414.in0","add_all__U413.out"], - ["mul_d6__U403.out","add_all__U414.in1"], - ["add_all__U415.in0","add_all__U414.out"], - ["mul_d7__U405.out","add_all__U415.in1"], - ["add_all__U416.in0","add_all__U415.out"], - ["mul_d8__U407.out","add_all__U416.in1"], - ["add_all__U417.in0","add_all__U416.out"], - ["const_term_U408.out","add_all__U417.in1"], - ["self.out","add_all__U417.out"], - ["mul_d0__U391.in0","coeff_0_U390.out"], - ["mul_d1__U393.in0","coeff_1_U392.out"], - ["mul_d2__U395.in0","coeff_2_U394.out"], - ["mul_d3__U397.in0","coeff_3_U396.out"], - ["mul_d4__U399.in0","coeff_4_U398.out"], - ["mul_d5__U401.in0","coeff_5_U400.out"], - ["mul_d6__U403.in0","coeff_6_U402.out"], - ["mul_d7__U405.in0","coeff_7_U404.out"], - ["mul_d8__U407.in0","coeff_8_U406.out"], - ["self.d.0","mul_d0__U391.in1"], - ["self.d.1","mul_d1__U393.in1"], - ["self.d.2","mul_d2__U395.in1"], - ["self.d.3","mul_d3__U397.in1"], - ["self.d.4","mul_d4__U399.in1"], - ["self.d.5","mul_d5__U401.in1"], - ["self.d.6","mul_d6__U403.in1"], - ["self.d.7","mul_d7__U405.in1"], - ["self.d.8","mul_d8__U407.in1"] + ["mul_d0__U317.out","add_all__U335.in0"], + ["mul_d1__U319.out","add_all__U335.in1"], + ["add_all__U336.in0","add_all__U335.out"], + ["mul_d2__U321.out","add_all__U336.in1"], + ["add_all__U337.in0","add_all__U336.out"], + ["mul_d3__U323.out","add_all__U337.in1"], + ["add_all__U338.in0","add_all__U337.out"], + ["mul_d4__U325.out","add_all__U338.in1"], + ["add_all__U339.in0","add_all__U338.out"], + ["mul_d5__U327.out","add_all__U339.in1"], + ["add_all__U340.in0","add_all__U339.out"], + ["mul_d6__U329.out","add_all__U340.in1"], + ["add_all__U341.in0","add_all__U340.out"], + ["mul_d7__U331.out","add_all__U341.in1"], + ["add_all__U342.in0","add_all__U341.out"], + ["mul_d8__U333.out","add_all__U342.in1"], + ["add_all__U343.in0","add_all__U342.out"], + ["const_term_U334.out","add_all__U343.in1"], + ["self.out","add_all__U343.out"], + ["mul_d0__U317.in0","coeff_0_U316.out"], + ["mul_d1__U319.in0","coeff_1_U318.out"], + ["mul_d2__U321.in0","coeff_2_U320.out"], + ["mul_d3__U323.in0","coeff_3_U322.out"], + ["mul_d4__U325.in0","coeff_4_U324.out"], + ["mul_d5__U327.in0","coeff_5_U326.out"], + ["mul_d6__U329.in0","coeff_6_U328.out"], + ["mul_d7__U331.in0","coeff_7_U330.out"], + ["mul_d8__U333.in0","coeff_8_U332.out"], + ["self.d.0","mul_d0__U317.in1"], + ["self.d.1","mul_d1__U319.in1"], + ["self.d.2","mul_d2__U321.in1"], + ["self.d.3","mul_d3__U323.in1"], + ["self.d.4","mul_d4__U325.in1"], + ["self.d.5","mul_d5__U327.in1"], + ["self.d.6","mul_d6__U329.in1"], + ["self.d.7","mul_d7__U331.in1"], + ["self.d.8","mul_d8__U333.in1"] ] }, - "aff__U41":{ + "aff__U32":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U51":{ + "add_all__U42":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U52":{ + "add_all__U43":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U53":{ + "add_all__U44":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U54":{ + "add_all__U45":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U42":{ + "coeff_0_U33":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U44":{ + "coeff_1_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U46":{ + "coeff_2_U37":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000003a"]} }, - "coeff_3_U48":{ + "coeff_3_U39":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000d24"]} }, - "const_term_U50":{ + "const_term_U41":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U43":{ + "mul_d0__U34":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U45":{ + "mul_d1__U36":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U47":{ + "mul_d2__U38":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U49":{ + "mul_d3__U40":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U43.out","add_all__U51.in0"], - ["mul_d1__U45.out","add_all__U51.in1"], - ["add_all__U52.in0","add_all__U51.out"], - ["mul_d2__U47.out","add_all__U52.in1"], - ["add_all__U53.in0","add_all__U52.out"], - ["mul_d3__U49.out","add_all__U53.in1"], - ["add_all__U54.in0","add_all__U53.out"], - ["const_term_U50.out","add_all__U54.in1"], - ["self.out","add_all__U54.out"], - ["mul_d0__U43.in0","coeff_0_U42.out"], - ["mul_d1__U45.in0","coeff_1_U44.out"], - ["mul_d2__U47.in0","coeff_2_U46.out"], - ["mul_d3__U49.in0","coeff_3_U48.out"], - ["self.d.0","mul_d0__U43.in1"], - ["self.d.1","mul_d1__U45.in1"], - ["self.d.2","mul_d2__U47.in1"], - ["self.d.3","mul_d3__U49.in1"] + ["mul_d0__U34.out","add_all__U42.in0"], + ["mul_d1__U36.out","add_all__U42.in1"], + ["add_all__U43.in0","add_all__U42.out"], + ["mul_d2__U38.out","add_all__U43.in1"], + ["add_all__U44.in0","add_all__U43.out"], + ["mul_d3__U40.out","add_all__U44.in1"], + ["add_all__U45.in0","add_all__U44.out"], + ["const_term_U41.out","add_all__U45.in1"], + ["self.out","add_all__U45.out"], + ["mul_d0__U34.in0","coeff_0_U33.out"], + ["mul_d1__U36.in0","coeff_1_U35.out"], + ["mul_d2__U38.in0","coeff_2_U37.out"], + ["mul_d3__U40.in0","coeff_3_U39.out"], + ["self.d.0","mul_d0__U34.in1"], + ["self.d.1","mul_d1__U36.in1"], + ["self.d.2","mul_d2__U38.in1"], + ["self.d.3","mul_d3__U40.in1"] ] }, - "aff__U422":{ + "aff__U348":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U428":{ + "add_all__U354":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U429":{ + "add_all__U355":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U423":{ + "coeff_0_U349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U425":{ + "coeff_1_U351":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U427":{ + "const_term_U353":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U424":{ + "mul_d0__U350":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U426":{ + "mul_d1__U352":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U424.out","add_all__U428.in0"], - ["mul_d1__U426.out","add_all__U428.in1"], - ["add_all__U429.in0","add_all__U428.out"], - ["const_term_U427.out","add_all__U429.in1"], - ["self.out","add_all__U429.out"], - ["mul_d0__U424.in0","coeff_0_U423.out"], - ["mul_d1__U426.in0","coeff_1_U425.out"], - ["self.d.0","mul_d0__U424.in1"], - ["self.d.1","mul_d1__U426.in1"] + ["mul_d0__U350.out","add_all__U354.in0"], + ["mul_d1__U352.out","add_all__U354.in1"], + ["add_all__U355.in0","add_all__U354.out"], + ["const_term_U353.out","add_all__U355.in1"], + ["self.out","add_all__U355.out"], + ["mul_d0__U350.in0","coeff_0_U349.out"], + ["mul_d1__U352.in0","coeff_1_U351.out"], + ["self.d.0","mul_d0__U350.in1"], + ["self.d.1","mul_d1__U352.in1"] ] }, - "aff__U437":{ + "aff__U362":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U443":{ + "add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U444":{ + "add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U438":{ + "coeff_0_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U440":{ + "coeff_1_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U442":{ + "const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U439":{ + "mul_d0__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U441":{ + "mul_d1__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U439.out","add_all__U443.in0"], - ["mul_d1__U441.out","add_all__U443.in1"], - ["add_all__U444.in0","add_all__U443.out"], - ["const_term_U442.out","add_all__U444.in1"], - ["self.out","add_all__U444.out"], - ["mul_d0__U439.in0","coeff_0_U438.out"], - ["mul_d1__U441.in0","coeff_1_U440.out"], - ["self.d.0","mul_d0__U439.in1"], - ["self.d.1","mul_d1__U441.in1"] + ["mul_d0__U364.out","add_all__U368.in0"], + ["mul_d1__U366.out","add_all__U368.in1"], + ["add_all__U369.in0","add_all__U368.out"], + ["const_term_U367.out","add_all__U369.in1"], + ["self.out","add_all__U369.out"], + ["mul_d0__U364.in0","coeff_0_U363.out"], + ["mul_d1__U366.in0","coeff_1_U365.out"], + ["self.d.0","mul_d0__U364.in1"], + ["self.d.1","mul_d1__U366.in1"] ] }, - "aff__U452":{ + "aff__U376":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U458":{ + "add_all__U382":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U459":{ + "add_all__U383":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U453":{ + "coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U455":{ + "coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U457":{ + "const_term_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U454":{ + "mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U456":{ + "mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U454.out","add_all__U458.in0"], - ["mul_d1__U456.out","add_all__U458.in1"], - ["add_all__U459.in0","add_all__U458.out"], - ["const_term_U457.out","add_all__U459.in1"], - ["self.out","add_all__U459.out"], - ["mul_d0__U454.in0","coeff_0_U453.out"], - ["mul_d1__U456.in0","coeff_1_U455.out"], - ["self.d.0","mul_d0__U454.in1"], - ["self.d.1","mul_d1__U456.in1"] + ["mul_d0__U378.out","add_all__U382.in0"], + ["mul_d1__U380.out","add_all__U382.in1"], + ["add_all__U383.in0","add_all__U382.out"], + ["const_term_U381.out","add_all__U383.in1"], + ["self.out","add_all__U383.out"], + ["mul_d0__U378.in0","coeff_0_U377.out"], + ["mul_d1__U380.in0","coeff_1_U379.out"], + ["self.d.0","mul_d0__U378.in1"], + ["self.d.1","mul_d1__U380.in1"] ] }, - "aff__U467":{ + "aff__U390":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U473":{ + "add_all__U396":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U474":{ + "add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U468":{ + "coeff_0_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U470":{ + "coeff_1_U393":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U472":{ + "const_term_U395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U469":{ + "mul_d0__U392":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U471":{ + "mul_d1__U394":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U469.out","add_all__U473.in0"], - ["mul_d1__U471.out","add_all__U473.in1"], - ["add_all__U474.in0","add_all__U473.out"], - ["const_term_U472.out","add_all__U474.in1"], - ["self.out","add_all__U474.out"], - ["mul_d0__U469.in0","coeff_0_U468.out"], - ["mul_d1__U471.in0","coeff_1_U470.out"], - ["self.d.0","mul_d0__U469.in1"], - ["self.d.1","mul_d1__U471.in1"] + ["mul_d0__U392.out","add_all__U396.in0"], + ["mul_d1__U394.out","add_all__U396.in1"], + ["add_all__U397.in0","add_all__U396.out"], + ["const_term_U395.out","add_all__U397.in1"], + ["self.out","add_all__U397.out"], + ["mul_d0__U392.in0","coeff_0_U391.out"], + ["mul_d1__U394.in0","coeff_1_U393.out"], + ["self.d.0","mul_d0__U392.in1"], + ["self.d.1","mul_d1__U394.in1"] ] }, - "aff__U482":{ + "aff__U404":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U488":{ + "add_all__U410":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U489":{ + "add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U483":{ + "coeff_0_U405":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U485":{ + "coeff_1_U407":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U487":{ + "const_term_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U484":{ + "mul_d0__U406":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U486":{ + "mul_d1__U408":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U484.out","add_all__U488.in0"], - ["mul_d1__U486.out","add_all__U488.in1"], - ["add_all__U489.in0","add_all__U488.out"], - ["const_term_U487.out","add_all__U489.in1"], - ["self.out","add_all__U489.out"], - ["mul_d0__U484.in0","coeff_0_U483.out"], - ["mul_d1__U486.in0","coeff_1_U485.out"], - ["self.d.0","mul_d0__U484.in1"], - ["self.d.1","mul_d1__U486.in1"] + ["mul_d0__U406.out","add_all__U410.in0"], + ["mul_d1__U408.out","add_all__U410.in1"], + ["add_all__U411.in0","add_all__U410.out"], + ["const_term_U409.out","add_all__U411.in1"], + ["self.out","add_all__U411.out"], + ["mul_d0__U406.in0","coeff_0_U405.out"], + ["mul_d1__U408.in0","coeff_1_U407.out"], + ["self.d.0","mul_d0__U406.in1"], + ["self.d.1","mul_d1__U408.in1"] ] }, - "aff__U497":{ + "aff__U418":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U503":{ + "add_all__U424":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U504":{ + "add_all__U425":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U498":{ + "coeff_0_U419":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U500":{ + "coeff_1_U421":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U502":{ + "const_term_U423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U499":{ + "mul_d0__U420":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U501":{ + "mul_d1__U422":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U499.out","add_all__U503.in0"], - ["mul_d1__U501.out","add_all__U503.in1"], - ["add_all__U504.in0","add_all__U503.out"], - ["const_term_U502.out","add_all__U504.in1"], - ["self.out","add_all__U504.out"], - ["mul_d0__U499.in0","coeff_0_U498.out"], - ["mul_d1__U501.in0","coeff_1_U500.out"], - ["self.d.0","mul_d0__U499.in1"], - ["self.d.1","mul_d1__U501.in1"] + ["mul_d0__U420.out","add_all__U424.in0"], + ["mul_d1__U422.out","add_all__U424.in1"], + ["add_all__U425.in0","add_all__U424.out"], + ["const_term_U423.out","add_all__U425.in1"], + ["self.out","add_all__U425.out"], + ["mul_d0__U420.in0","coeff_0_U419.out"], + ["mul_d1__U422.in0","coeff_1_U421.out"], + ["self.d.0","mul_d0__U420.in1"], + ["self.d.1","mul_d1__U422.in1"] ] }, - "aff__U512":{ + "aff__U432":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U518":{ + "add_all__U438":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U519":{ + "add_all__U439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U513":{ + "coeff_0_U433":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U515":{ + "coeff_1_U435":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U517":{ + "const_term_U437":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U514":{ + "mul_d0__U434":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U516":{ + "mul_d1__U436":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U514.out","add_all__U518.in0"], - ["mul_d1__U516.out","add_all__U518.in1"], - ["add_all__U519.in0","add_all__U518.out"], - ["const_term_U517.out","add_all__U519.in1"], - ["self.out","add_all__U519.out"], - ["mul_d0__U514.in0","coeff_0_U513.out"], - ["mul_d1__U516.in0","coeff_1_U515.out"], - ["self.d.0","mul_d0__U514.in1"], - ["self.d.1","mul_d1__U516.in1"] + ["mul_d0__U434.out","add_all__U438.in0"], + ["mul_d1__U436.out","add_all__U438.in1"], + ["add_all__U439.in0","add_all__U438.out"], + ["const_term_U437.out","add_all__U439.in1"], + ["self.out","add_all__U439.out"], + ["mul_d0__U434.in0","coeff_0_U433.out"], + ["mul_d1__U436.in0","coeff_1_U435.out"], + ["self.d.0","mul_d0__U434.in1"], + ["self.d.1","mul_d1__U436.in1"] ] }, - "aff__U527":{ + "aff__U446":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",2,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U533":{ + "add_all__U452":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U534":{ + "add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U528":{ + "coeff_0_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U530":{ + "coeff_1_U449":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "const_term_U532":{ + "const_term_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "mul_d0__U529":{ + "mul_d0__U448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U531":{ + "mul_d1__U450":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U529.out","add_all__U533.in0"], - ["mul_d1__U531.out","add_all__U533.in1"], - ["add_all__U534.in0","add_all__U533.out"], - ["const_term_U532.out","add_all__U534.in1"], - ["self.out","add_all__U534.out"], - ["mul_d0__U529.in0","coeff_0_U528.out"], - ["mul_d1__U531.in0","coeff_1_U530.out"], - ["self.d.0","mul_d0__U529.in1"], - ["self.d.1","mul_d1__U531.in1"] + ["mul_d0__U448.out","add_all__U452.in0"], + ["mul_d1__U450.out","add_all__U452.in1"], + ["add_all__U453.in0","add_all__U452.out"], + ["const_term_U451.out","add_all__U453.in1"], + ["self.out","add_all__U453.out"], + ["mul_d0__U448.in0","coeff_0_U447.out"], + ["mul_d1__U450.in0","coeff_1_U449.out"], + ["self.d.0","mul_d0__U448.in1"], + ["self.d.1","mul_d1__U450.in1"] ] }, - "aff__U542":{ + "aff__U459":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U558":{ + "add_all__U475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U559":{ + "add_all__U476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U560":{ + "add_all__U477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U561":{ + "add_all__U478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U562":{ + "add_all__U479":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U563":{ + "add_all__U480":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U564":{ + "add_all__U481":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U543":{ + "coeff_0_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U545":{ + "coeff_1_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U547":{ + "coeff_2_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U549":{ + "coeff_3_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U551":{ + "coeff_4_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "coeff_5_U553":{ + "coeff_5_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_6_U555":{ + "coeff_6_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U557":{ + "const_term_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012d60"]} }, - "mul_d0__U544":{ + "mul_d0__U461":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U546":{ + "mul_d1__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U548":{ + "mul_d2__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U550":{ + "mul_d3__U467":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U552":{ + "mul_d4__U469":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U554":{ + "mul_d5__U471":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U556":{ + "mul_d6__U473":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U544.out","add_all__U558.in0"], - ["mul_d1__U546.out","add_all__U558.in1"], - ["add_all__U559.in0","add_all__U558.out"], - ["mul_d2__U548.out","add_all__U559.in1"], - ["add_all__U560.in0","add_all__U559.out"], - ["mul_d3__U550.out","add_all__U560.in1"], - ["add_all__U561.in0","add_all__U560.out"], - ["mul_d4__U552.out","add_all__U561.in1"], - ["add_all__U562.in0","add_all__U561.out"], - ["mul_d5__U554.out","add_all__U562.in1"], - ["add_all__U563.in0","add_all__U562.out"], - ["mul_d6__U556.out","add_all__U563.in1"], - ["add_all__U564.in0","add_all__U563.out"], - ["const_term_U557.out","add_all__U564.in1"], - ["self.out","add_all__U564.out"], - ["mul_d0__U544.in0","coeff_0_U543.out"], - ["mul_d1__U546.in0","coeff_1_U545.out"], - ["mul_d2__U548.in0","coeff_2_U547.out"], - ["mul_d3__U550.in0","coeff_3_U549.out"], - ["mul_d4__U552.in0","coeff_4_U551.out"], - ["mul_d5__U554.in0","coeff_5_U553.out"], - ["mul_d6__U556.in0","coeff_6_U555.out"], - ["self.d.0","mul_d0__U544.in1"], - ["self.d.1","mul_d1__U546.in1"], - ["self.d.2","mul_d2__U548.in1"], - ["self.d.3","mul_d3__U550.in1"], - ["self.d.4","mul_d4__U552.in1"], - ["self.d.5","mul_d5__U554.in1"], - ["self.d.6","mul_d6__U556.in1"] + ["mul_d0__U461.out","add_all__U475.in0"], + ["mul_d1__U463.out","add_all__U475.in1"], + ["add_all__U476.in0","add_all__U475.out"], + ["mul_d2__U465.out","add_all__U476.in1"], + ["add_all__U477.in0","add_all__U476.out"], + ["mul_d3__U467.out","add_all__U477.in1"], + ["add_all__U478.in0","add_all__U477.out"], + ["mul_d4__U469.out","add_all__U478.in1"], + ["add_all__U479.in0","add_all__U478.out"], + ["mul_d5__U471.out","add_all__U479.in1"], + ["add_all__U480.in0","add_all__U479.out"], + ["mul_d6__U473.out","add_all__U480.in1"], + ["add_all__U481.in0","add_all__U480.out"], + ["const_term_U474.out","add_all__U481.in1"], + ["self.out","add_all__U481.out"], + ["mul_d0__U461.in0","coeff_0_U460.out"], + ["mul_d1__U463.in0","coeff_1_U462.out"], + ["mul_d2__U465.in0","coeff_2_U464.out"], + ["mul_d3__U467.in0","coeff_3_U466.out"], + ["mul_d4__U469.in0","coeff_4_U468.out"], + ["mul_d5__U471.in0","coeff_5_U470.out"], + ["mul_d6__U473.in0","coeff_6_U472.out"], + ["self.d.0","mul_d0__U461.in1"], + ["self.d.1","mul_d1__U463.in1"], + ["self.d.2","mul_d2__U465.in1"], + ["self.d.3","mul_d3__U467.in1"], + ["self.d.4","mul_d4__U469.in1"], + ["self.d.5","mul_d5__U471.in1"], + ["self.d.6","mul_d6__U473.in1"] ] }, - "aff__U57":{ + "aff__U48":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",8,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U75":{ + "add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U76":{ + "add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U77":{ + "add_all__U68":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U78":{ + "add_all__U69":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U79":{ + "add_all__U70":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U80":{ + "add_all__U71":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U81":{ + "add_all__U72":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U82":{ + "add_all__U73":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U58":{ + "coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U60":{ + "coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "coeff_2_U62":{ + "coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "coeff_3_U64":{ + "coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "coeff_4_U66":{ + "coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "coeff_5_U68":{ + "coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000f0"]} }, - "coeff_6_U70":{ + "coeff_6_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "coeff_7_U72":{ + "coeff_7_U63":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U74":{ + "const_term_U65":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} }, - "mul_d0__U59":{ + "mul_d0__U50":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U61":{ + "mul_d1__U52":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U63":{ + "mul_d2__U54":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U65":{ + "mul_d3__U56":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U67":{ + "mul_d4__U58":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U69":{ + "mul_d5__U60":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U71":{ + "mul_d6__U62":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d7__U73":{ + "mul_d7__U64":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U59.out","add_all__U75.in0"], - ["mul_d1__U61.out","add_all__U75.in1"], - ["add_all__U76.in0","add_all__U75.out"], - ["mul_d2__U63.out","add_all__U76.in1"], - ["add_all__U77.in0","add_all__U76.out"], - ["mul_d3__U65.out","add_all__U77.in1"], - ["add_all__U78.in0","add_all__U77.out"], - ["mul_d4__U67.out","add_all__U78.in1"], - ["add_all__U79.in0","add_all__U78.out"], - ["mul_d5__U69.out","add_all__U79.in1"], - ["add_all__U80.in0","add_all__U79.out"], - ["mul_d6__U71.out","add_all__U80.in1"], - ["add_all__U81.in0","add_all__U80.out"], - ["mul_d7__U73.out","add_all__U81.in1"], - ["add_all__U82.in0","add_all__U81.out"], - ["const_term_U74.out","add_all__U82.in1"], - ["self.out","add_all__U82.out"], - ["mul_d0__U59.in0","coeff_0_U58.out"], - ["mul_d1__U61.in0","coeff_1_U60.out"], - ["mul_d2__U63.in0","coeff_2_U62.out"], - ["mul_d3__U65.in0","coeff_3_U64.out"], - ["mul_d4__U67.in0","coeff_4_U66.out"], - ["mul_d5__U69.in0","coeff_5_U68.out"], - ["mul_d6__U71.in0","coeff_6_U70.out"], - ["mul_d7__U73.in0","coeff_7_U72.out"], - ["self.d.0","mul_d0__U59.in1"], - ["self.d.1","mul_d1__U61.in1"], - ["self.d.2","mul_d2__U63.in1"], - ["self.d.3","mul_d3__U65.in1"], - ["self.d.4","mul_d4__U67.in1"], - ["self.d.5","mul_d5__U69.in1"], - ["self.d.6","mul_d6__U71.in1"], - ["self.d.7","mul_d7__U73.in1"] + ["mul_d0__U50.out","add_all__U66.in0"], + ["mul_d1__U52.out","add_all__U66.in1"], + ["add_all__U67.in0","add_all__U66.out"], + ["mul_d2__U54.out","add_all__U67.in1"], + ["add_all__U68.in0","add_all__U67.out"], + ["mul_d3__U56.out","add_all__U68.in1"], + ["add_all__U69.in0","add_all__U68.out"], + ["mul_d4__U58.out","add_all__U69.in1"], + ["add_all__U70.in0","add_all__U69.out"], + ["mul_d5__U60.out","add_all__U70.in1"], + ["add_all__U71.in0","add_all__U70.out"], + ["mul_d6__U62.out","add_all__U71.in1"], + ["add_all__U72.in0","add_all__U71.out"], + ["mul_d7__U64.out","add_all__U72.in1"], + ["add_all__U73.in0","add_all__U72.out"], + ["const_term_U65.out","add_all__U73.in1"], + ["self.out","add_all__U73.out"], + ["mul_d0__U50.in0","coeff_0_U49.out"], + ["mul_d1__U52.in0","coeff_1_U51.out"], + ["mul_d2__U54.in0","coeff_2_U53.out"], + ["mul_d3__U56.in0","coeff_3_U55.out"], + ["mul_d4__U58.in0","coeff_4_U57.out"], + ["mul_d5__U60.in0","coeff_5_U59.out"], + ["mul_d6__U62.in0","coeff_6_U61.out"], + ["mul_d7__U64.in0","coeff_7_U63.out"], + ["self.d.0","mul_d0__U50.in1"], + ["self.d.1","mul_d1__U52.in1"], + ["self.d.2","mul_d2__U54.in1"], + ["self.d.3","mul_d3__U56.in1"], + ["self.d.4","mul_d4__U58.in1"], + ["self.d.5","mul_d5__U60.in1"], + ["self.d.6","mul_d6__U62.in1"], + ["self.d.7","mul_d7__U64.in1"] ] }, - "aff__U589":{ + "aff__U506":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",7,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U605":{ + "add_all__U522":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U606":{ + "add_all__U523":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U607":{ + "add_all__U524":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U608":{ + "add_all__U525":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U609":{ + "add_all__U526":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U610":{ + "add_all__U527":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U611":{ + "add_all__U528":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U590":{ + "coeff_0_U507":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U592":{ + "coeff_1_U509":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000001c"]} }, - "coeff_2_U594":{ + "coeff_2_U511":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000620"]} }, - "coeff_3_U596":{ + "coeff_3_U513":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00006200"]} }, - "coeff_4_U598":{ + "coeff_4_U515":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_5_U600":{ + "coeff_5_U517":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000038"]} }, - "coeff_6_U602":{ + "coeff_6_U519":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c40"]} }, - "const_term_U604":{ + "const_term_U521":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U591":{ + "mul_d0__U508":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U593":{ + "mul_d1__U510":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U595":{ + "mul_d2__U512":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U597":{ + "mul_d3__U514":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d4__U599":{ + "mul_d4__U516":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d5__U601":{ + "mul_d5__U518":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d6__U603":{ + "mul_d6__U520":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U591.out","add_all__U605.in0"], - ["mul_d1__U593.out","add_all__U605.in1"], - ["add_all__U606.in0","add_all__U605.out"], - ["mul_d2__U595.out","add_all__U606.in1"], - ["add_all__U607.in0","add_all__U606.out"], - ["mul_d3__U597.out","add_all__U607.in1"], - ["add_all__U608.in0","add_all__U607.out"], - ["mul_d4__U599.out","add_all__U608.in1"], - ["add_all__U609.in0","add_all__U608.out"], - ["mul_d5__U601.out","add_all__U609.in1"], - ["add_all__U610.in0","add_all__U609.out"], - ["mul_d6__U603.out","add_all__U610.in1"], - ["add_all__U611.in0","add_all__U610.out"], - ["const_term_U604.out","add_all__U611.in1"], - ["self.out","add_all__U611.out"], - ["mul_d0__U591.in0","coeff_0_U590.out"], - ["mul_d1__U593.in0","coeff_1_U592.out"], - ["mul_d2__U595.in0","coeff_2_U594.out"], - ["mul_d3__U597.in0","coeff_3_U596.out"], - ["mul_d4__U599.in0","coeff_4_U598.out"], - ["mul_d5__U601.in0","coeff_5_U600.out"], - ["mul_d6__U603.in0","coeff_6_U602.out"], - ["self.d.0","mul_d0__U591.in1"], - ["self.d.1","mul_d1__U593.in1"], - ["self.d.2","mul_d2__U595.in1"], - ["self.d.3","mul_d3__U597.in1"], - ["self.d.4","mul_d4__U599.in1"], - ["self.d.5","mul_d5__U601.in1"], - ["self.d.6","mul_d6__U603.in1"] + ["mul_d0__U508.out","add_all__U522.in0"], + ["mul_d1__U510.out","add_all__U522.in1"], + ["add_all__U523.in0","add_all__U522.out"], + ["mul_d2__U512.out","add_all__U523.in1"], + ["add_all__U524.in0","add_all__U523.out"], + ["mul_d3__U514.out","add_all__U524.in1"], + ["add_all__U525.in0","add_all__U524.out"], + ["mul_d4__U516.out","add_all__U525.in1"], + ["add_all__U526.in0","add_all__U525.out"], + ["mul_d5__U518.out","add_all__U526.in1"], + ["add_all__U527.in0","add_all__U526.out"], + ["mul_d6__U520.out","add_all__U527.in1"], + ["add_all__U528.in0","add_all__U527.out"], + ["const_term_U521.out","add_all__U528.in1"], + ["self.out","add_all__U528.out"], + ["mul_d0__U508.in0","coeff_0_U507.out"], + ["mul_d1__U510.in0","coeff_1_U509.out"], + ["mul_d2__U512.in0","coeff_2_U511.out"], + ["mul_d3__U514.in0","coeff_3_U513.out"], + ["mul_d4__U516.in0","coeff_4_U515.out"], + ["mul_d5__U518.in0","coeff_5_U517.out"], + ["mul_d6__U520.in0","coeff_6_U519.out"], + ["self.d.0","mul_d0__U508.in1"], + ["self.d.1","mul_d1__U510.in1"], + ["self.d.2","mul_d2__U512.in1"], + ["self.d.3","mul_d3__U514.in1"], + ["self.d.4","mul_d4__U516.in1"], + ["self.d.5","mul_d5__U518.in1"], + ["self.d.6","mul_d6__U520.in1"] ] }, - "aff__U614":{ + "aff__U531":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U624":{ + "add_all__U541":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U625":{ + "add_all__U542":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U626":{ + "add_all__U543":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U627":{ + "add_all__U544":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U615":{ + "coeff_0_U532":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U617":{ + "coeff_1_U534":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U619":{ + "coeff_2_U536":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U621":{ + "coeff_3_U538":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U623":{ + "const_term_U540":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} }, - "mul_d0__U616":{ + "mul_d0__U533":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U618":{ + "mul_d1__U535":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U620":{ + "mul_d2__U537":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U622":{ + "mul_d3__U539":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U616.out","add_all__U624.in0"], - ["mul_d1__U618.out","add_all__U624.in1"], - ["add_all__U625.in0","add_all__U624.out"], - ["mul_d2__U620.out","add_all__U625.in1"], - ["add_all__U626.in0","add_all__U625.out"], - ["mul_d3__U622.out","add_all__U626.in1"], - ["add_all__U627.in0","add_all__U626.out"], - ["const_term_U623.out","add_all__U627.in1"], - ["self.out","add_all__U627.out"], - ["mul_d0__U616.in0","coeff_0_U615.out"], - ["mul_d1__U618.in0","coeff_1_U617.out"], - ["mul_d2__U620.in0","coeff_2_U619.out"], - ["mul_d3__U622.in0","coeff_3_U621.out"], - ["self.d.0","mul_d0__U616.in1"], - ["self.d.1","mul_d1__U618.in1"], - ["self.d.2","mul_d2__U620.in1"], - ["self.d.3","mul_d3__U622.in1"] + ["mul_d0__U533.out","add_all__U541.in0"], + ["mul_d1__U535.out","add_all__U541.in1"], + ["add_all__U542.in0","add_all__U541.out"], + ["mul_d2__U537.out","add_all__U542.in1"], + ["add_all__U543.in0","add_all__U542.out"], + ["mul_d3__U539.out","add_all__U543.in1"], + ["add_all__U544.in0","add_all__U543.out"], + ["const_term_U540.out","add_all__U544.in1"], + ["self.out","add_all__U544.out"], + ["mul_d0__U533.in0","coeff_0_U532.out"], + ["mul_d1__U535.in0","coeff_1_U534.out"], + ["mul_d2__U537.in0","coeff_2_U536.out"], + ["mul_d3__U539.in0","coeff_3_U538.out"], + ["self.d.0","mul_d0__U533.in1"], + ["self.d.1","mul_d1__U535.in1"], + ["self.d.2","mul_d2__U537.in1"], + ["self.d.3","mul_d3__U539.in1"] ] }, - "aff__U637":{ + "aff__U554":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U647":{ + "add_all__U564":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U648":{ + "add_all__U565":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U649":{ + "add_all__U566":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U650":{ + "add_all__U567":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U638":{ + "coeff_0_U555":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U640":{ + "coeff_1_U557":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "coeff_2_U642":{ + "coeff_2_U559":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000038"]} }, - "coeff_3_U644":{ + "coeff_3_U561":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000c40"]} }, - "const_term_U646":{ + "const_term_U563":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "mul_d0__U639":{ + "mul_d0__U556":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U641":{ + "mul_d1__U558":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U643":{ + "mul_d2__U560":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U645":{ + "mul_d3__U562":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U639.out","add_all__U647.in0"], - ["mul_d1__U641.out","add_all__U647.in1"], - ["add_all__U648.in0","add_all__U647.out"], - ["mul_d2__U643.out","add_all__U648.in1"], - ["add_all__U649.in0","add_all__U648.out"], - ["mul_d3__U645.out","add_all__U649.in1"], - ["add_all__U650.in0","add_all__U649.out"], - ["const_term_U646.out","add_all__U650.in1"], - ["self.out","add_all__U650.out"], - ["mul_d0__U639.in0","coeff_0_U638.out"], - ["mul_d1__U641.in0","coeff_1_U640.out"], - ["mul_d2__U643.in0","coeff_2_U642.out"], - ["mul_d3__U645.in0","coeff_3_U644.out"], - ["self.d.0","mul_d0__U639.in1"], - ["self.d.1","mul_d1__U641.in1"], - ["self.d.2","mul_d2__U643.in1"], - ["self.d.3","mul_d3__U645.in1"] + ["mul_d0__U556.out","add_all__U564.in0"], + ["mul_d1__U558.out","add_all__U564.in1"], + ["add_all__U565.in0","add_all__U564.out"], + ["mul_d2__U560.out","add_all__U565.in1"], + ["add_all__U566.in0","add_all__U565.out"], + ["mul_d3__U562.out","add_all__U566.in1"], + ["add_all__U567.in0","add_all__U566.out"], + ["const_term_U563.out","add_all__U567.in1"], + ["self.out","add_all__U567.out"], + ["mul_d0__U556.in0","coeff_0_U555.out"], + ["mul_d1__U558.in0","coeff_1_U557.out"], + ["mul_d2__U560.in0","coeff_2_U559.out"], + ["mul_d3__U562.in0","coeff_3_U561.out"], + ["self.d.0","mul_d0__U556.in1"], + ["self.d.1","mul_d1__U558.in1"], + ["self.d.2","mul_d2__U560.in1"], + ["self.d.3","mul_d3__U562.in1"] ] }, - "aff__U654":{ + "aff__U571":{ "type":["Record",[ ["out",["Array",32,"Bit"]], ["d",["Array",4,["Array",32,"BitIn"]]] ]], "instances":{ - "add_all__U664":{ + "add_all__U581":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U665":{ + "add_all__U582":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U666":{ + "add_all__U583":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "add_all__U667":{ + "add_all__U584":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "coeff_0_U655":{ + "coeff_0_U572":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "coeff_1_U657":{ + "coeff_1_U574":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "coeff_2_U659":{ + "coeff_2_U576":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "coeff_3_U661":{ + "coeff_3_U578":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "const_term_U663":{ + "const_term_U580":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} }, - "mul_d0__U656":{ + "mul_d0__U573":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d1__U575":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d2__U577":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "mul_d3__U579":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + } + }, + "connections":[ + ["mul_d0__U573.out","add_all__U581.in0"], + ["mul_d1__U575.out","add_all__U581.in1"], + ["add_all__U582.in0","add_all__U581.out"], + ["mul_d2__U577.out","add_all__U582.in1"], + ["add_all__U583.in0","add_all__U582.out"], + ["mul_d3__U579.out","add_all__U583.in1"], + ["add_all__U584.in0","add_all__U583.out"], + ["const_term_U580.out","add_all__U584.in1"], + ["self.out","add_all__U584.out"], + ["mul_d0__U573.in0","coeff_0_U572.out"], + ["mul_d1__U575.in0","coeff_1_U574.out"], + ["mul_d2__U577.in0","coeff_2_U576.out"], + ["mul_d3__U579.in0","coeff_3_U578.out"], + ["self.d.0","mul_d0__U573.in1"], + ["self.d.1","mul_d1__U575.in1"], + ["self.d.2","mul_d2__U577.in1"], + ["self.d.3","mul_d3__U579.in1"] + ] + }, + "aff__U9":{ + "type":["Record",[ + ["out",["Array",32,"Bit"]], + ["d",["Array",4,["Array",32,"BitIn"]]] + ]], + "instances":{ + "add_all__U19":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U20":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U21":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "add_all__U22":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "coeff_0_U10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "coeff_1_U12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h000003a0"]} + }, + "coeff_2_U14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} + }, + "coeff_3_U16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "const_term_U18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d1__U658":{ + "mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d2__U660":{ + "mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "mul_d3__U662":{ + "mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} } }, "connections":[ - ["mul_d0__U656.out","add_all__U664.in0"], - ["mul_d1__U658.out","add_all__U664.in1"], - ["add_all__U665.in0","add_all__U664.out"], - ["mul_d2__U660.out","add_all__U665.in1"], - ["add_all__U666.in0","add_all__U665.out"], - ["mul_d3__U662.out","add_all__U666.in1"], - ["add_all__U667.in0","add_all__U666.out"], - ["const_term_U663.out","add_all__U667.in1"], - ["self.out","add_all__U667.out"], - ["mul_d0__U656.in0","coeff_0_U655.out"], - ["mul_d1__U658.in0","coeff_1_U657.out"], - ["mul_d2__U660.in0","coeff_2_U659.out"], - ["mul_d3__U662.in0","coeff_3_U661.out"], - ["self.d.0","mul_d0__U656.in1"], - ["self.d.1","mul_d1__U658.in1"], - ["self.d.2","mul_d2__U660.in1"], - ["self.d.3","mul_d3__U662.in1"] + ["mul_d0__U11.out","add_all__U19.in0"], + ["mul_d1__U13.out","add_all__U19.in1"], + ["add_all__U20.in0","add_all__U19.out"], + ["mul_d2__U15.out","add_all__U20.in1"], + ["add_all__U21.in0","add_all__U20.out"], + ["mul_d3__U17.out","add_all__U21.in1"], + ["add_all__U22.in0","add_all__U21.out"], + ["const_term_U18.out","add_all__U22.in1"], + ["self.out","add_all__U22.out"], + ["mul_d0__U11.in0","coeff_0_U10.out"], + ["mul_d1__U13.in0","coeff_1_U12.out"], + ["mul_d2__U15.in0","coeff_2_U14.out"], + ["mul_d3__U17.in0","coeff_3_U16.out"], + ["self.d.0","mul_d0__U11.in1"], + ["self.d.1","mul_d1__U13.in1"], + ["self.d.2","mul_d2__U15.in1"], + ["self.d.3","mul_d3__U17.in1"] ] }, - "affine_controller__U17":{ + "affine_controller__U197":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",32,"Bit"]]], + ["d",["Array",5,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U32":{ + "_U215":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2151":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U321":{ + "_U2152":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U322":{ + "_U2153":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U323":{ + "_U2154":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U33":{ + "_U216":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U28":{ + "affine_func$add_all__U210":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U211":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U29":{ + "affine_func$add_all__U212":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U30":{ + "affine_func$add_all__U213":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U31":{ + "affine_func$add_all__U214":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U19":{ + "affine_func$coeff_0_U199":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U21":{ + "affine_func$coeff_1_U201":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000003a0"]} + "modargs":{"value":[["BitVector",32],"32'h00000300"]} + }, + "affine_func$coeff_2_U203":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000100"]} }, - "affine_func$coeff_2_U23":{ + "affine_func$coeff_3_U205":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U25":{ + "affine_func$coeff_4_U207":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U27":{ + "affine_func$const_term_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U20":{ + "affine_func$mul_d0__U200":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U202":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U22":{ + "affine_func$mul_d2__U204":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U24":{ + "affine_func$mul_d3__U206":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U26":{ + "affine_func$mul_d4__U208":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2316,32 +2334,42 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U34$c0_lutcnst":{ + "d_0_am__U217$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U217$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U218$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U34$lut$lut":{ + "d_0_am__U218$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U35$c0_lutcnst":{ + "d_0_am__U219$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U35$lut$lut":{ + "d_0_am__U219$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U36$c0_lutcnst":{ + "d_0_am__U220$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U36$lut$lut":{ + "d_0_am__U220$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2390,22 +2418,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U37$c0_lutcnst":{ + "d_1_am__U221$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U221$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U222$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U37$lut$lut":{ + "d_1_am__U222$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U38$c0_lutcnst":{ + "d_1_am__U223$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U38$lut$lut":{ + "d_1_am__U223$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2421,7 +2459,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2454,12 +2492,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U39$c0_lutcnst":{ + "d_2_am__U224$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U39$lut$lut":{ + "d_2_am__U224$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U225$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U225$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2475,7 +2523,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000039"]} + "modargs":{"value":[["BitVector",32],"32'h00000002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2508,6 +2556,16 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U226$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U226$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -2552,6 +2610,50 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_4_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_4_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, "time_diff":{ "genref":"coreir.sub", "genargs":{"width":["Int",32]} @@ -2581,6 +2683,11 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, + "true6_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2588,33 +2695,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U32.out"], - ["d_1_inc.in1","_U321.out"], - ["d_2_inc.in1","_U322.out"], - ["d_3_inc.in1","_U323.out"], - ["cmp_time.in1","_U33.out"], - ["affine_func$mul_d0__U20.out","affine_func$add_all__U28.in0"], - ["affine_func$mul_d1__U22.out","affine_func$add_all__U28.in1"], - ["affine_func$add_all__U29.in0","affine_func$add_all__U28.out"], - ["affine_func$mul_d2__U24.out","affine_func$add_all__U29.in1"], - ["affine_func$add_all__U30.in0","affine_func$add_all__U29.out"], - ["affine_func$mul_d3__U26.out","affine_func$add_all__U30.in1"], - ["affine_func$add_all__U31.in0","affine_func$add_all__U30.out"], - ["affine_func$const_term_U27.out","affine_func$add_all__U31.in1"], - ["time_diff.in0","affine_func$add_all__U31.out"], - ["affine_func$mul_d0__U20.in0","affine_func$coeff_0_U19.out"], - ["affine_func$mul_d1__U22.in0","affine_func$coeff_1_U21.out"], - ["affine_func$mul_d2__U24.in0","affine_func$coeff_2_U23.out"], - ["affine_func$mul_d3__U26.in0","affine_func$coeff_3_U25.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U20.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U22.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U24.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U26.in1"], + ["d_0_inc.in1","_U215.out"], + ["d_1_inc.in1","_U2151.out"], + ["d_2_inc.in1","_U2152.out"], + ["d_3_inc.in1","_U2153.out"], + ["d_4_inc.in1","_U2154.out"], + ["cmp_time.in1","_U216.out"], + ["affine_func$mul_d0__U200.out","affine_func$add_all__U210.in0"], + ["affine_func$mul_d1__U202.out","affine_func$add_all__U210.in1"], + ["affine_func$add_all__U211.in0","affine_func$add_all__U210.out"], + ["affine_func$mul_d2__U204.out","affine_func$add_all__U211.in1"], + ["affine_func$add_all__U212.in0","affine_func$add_all__U211.out"], + ["affine_func$mul_d3__U206.out","affine_func$add_all__U212.in1"], + ["affine_func$add_all__U213.in0","affine_func$add_all__U212.out"], + ["affine_func$mul_d4__U208.out","affine_func$add_all__U213.in1"], + ["affine_func$add_all__U214.in0","affine_func$add_all__U213.out"], + ["affine_func$const_term_U209.out","affine_func$add_all__U214.in1"], + ["time_diff.in0","affine_func$add_all__U214.out"], + ["affine_func$mul_d0__U200.in0","affine_func$coeff_0_U199.out"], + ["affine_func$mul_d1__U202.in0","affine_func$coeff_1_U201.out"], + ["affine_func$mul_d2__U204.in0","affine_func$coeff_2_U203.out"], + ["affine_func$mul_d3__U206.in0","affine_func$coeff_3_U205.out"], + ["affine_func$mul_d4__U208.in0","affine_func$coeff_4_U207.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U200.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U202.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U204.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U206.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U208.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], ["d_2_reg$enMux.sel","cmp_time.out"], ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -2622,28 +2735,31 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U34$lut$lut.bit.in.2","d_0_am__U34$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U34$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U34$lut$lut.bit.in.1"], - ["d_0_am__U35$lut$lut.bit.in.0","d_0_am__U34$lut$lut.bit.out"], - ["d_0_am__U35$lut$lut.bit.in.2","d_0_am__U35$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U35$lut$lut.bit.in.1"], - ["d_0_am__U36$lut$lut.bit.in.0","d_0_am__U35$lut$lut.bit.out"], - ["d_0_am__U36$lut$lut.bit.in.2","d_0_am__U36$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U36$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U36$lut$lut.bit.out"], + ["d_0_am__U217$lut$lut.bit.in.2","d_0_am__U217$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U217$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U217$lut$lut.bit.in.1"], + ["d_0_am__U218$lut$lut.bit.in.0","d_0_am__U217$lut$lut.bit.out"], + ["d_0_am__U218$lut$lut.bit.in.2","d_0_am__U218$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U218$lut$lut.bit.in.1"], + ["d_0_am__U219$lut$lut.bit.in.0","d_0_am__U218$lut$lut.bit.out"], + ["d_0_am__U219$lut$lut.bit.in.2","d_0_am__U219$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U219$lut$lut.bit.in.1"], + ["d_0_am__U220$lut$lut.bit.in.0","d_0_am__U219$lut$lut.bit.out"], + ["d_0_am__U220$lut$lut.bit.in.2","d_0_am__U220$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U220$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U220$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2660,13 +2776,16 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U37$lut$lut.bit.in.2","d_1_am__U37$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U37$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U37$lut$lut.bit.in.1"], - ["d_1_am__U38$lut$lut.bit.in.0","d_1_am__U37$lut$lut.bit.out"], - ["d_1_am__U38$lut$lut.bit.in.2","d_1_am__U38$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U38$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U38$lut$lut.bit.out"], + ["d_1_am__U221$lut$lut.bit.in.2","d_1_am__U221$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U221$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U221$lut$lut.bit.in.1"], + ["d_1_am__U222$lut$lut.bit.in.0","d_1_am__U221$lut$lut.bit.out"], + ["d_1_am__U222$lut$lut.bit.in.2","d_1_am__U222$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U222$lut$lut.bit.in.1"], + ["d_1_am__U223$lut$lut.bit.in.0","d_1_am__U222$lut$lut.bit.out"], + ["d_1_am__U223$lut$lut.bit.in.2","d_1_am__U223$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U223$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U223$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2683,10 +2802,13 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U39$lut$lut.bit.in.2","d_2_am__U39$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U39$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U39$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U39$lut$lut.bit.out"], + ["d_2_am__U224$lut$lut.bit.in.2","d_2_am__U224$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U224$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U224$lut$lut.bit.in.1"], + ["d_2_am__U225$lut$lut.bit.in.0","d_2_am__U224$lut$lut.bit.out"], + ["d_2_am__U225$lut$lut.bit.in.2","d_2_am__U225$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U225$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U225$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2703,6 +2825,10 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U226$lut$lut.bit.in.2","d_3_am__U226$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U226$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U226$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U226$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2712,121 +2838,209 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["true_lutcnst.bit.out","d_4_next_value.sel"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"] ] }, - "affine_controller__U271":{ + "affine_controller__U246":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",32,"Bit"]]], + ["d",["Array",9,["Array",32,"Bit"]]], ["rst_n","BitIn"] ]], "instances":{ - "_U289":{ + "_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2891":{ + "_U2761":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2892":{ + "_U2762":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2893":{ + "_U2763":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U2894":{ + "_U2764":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U290":{ + "_U2765":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$add_all__U284":{ + "_U2766":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2767":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U2768":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "_U277":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "affine_func$add_all__U267":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U285":{ + "affine_func$add_all__U268":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U286":{ + "affine_func$add_all__U269":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U287":{ + "affine_func$add_all__U270":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U288":{ + "affine_func$add_all__U271":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U273":{ + "affine_func$add_all__U272":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U273":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U274":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U275":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U248":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U275":{ + "affine_func$coeff_1_U250":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000300"]} + "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "affine_func$coeff_2_U277":{ + "affine_func$coeff_2_U252":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000100"]} + "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "affine_func$coeff_3_U279":{ + "affine_func$coeff_3_U254":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000010"]} + "modargs":{"value":[["BitVector",32],"32'h00003f00"]} + }, + "affine_func$coeff_4_U256":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00001f80"]} + }, + "affine_func$coeff_5_U258":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h000000c0"]} + }, + "affine_func$coeff_6_U260":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000040"]} + }, + "affine_func$coeff_7_U262":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_4_U281":{ + "affine_func$coeff_8_U264":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U283":{ + "affine_func$const_term_U266":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} + }, + "affine_func$mul_d0__U249":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U251":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U253":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U255":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "affine_func$mul_d0__U274":{ + "affine_func$mul_d4__U257":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U276":{ + "affine_func$mul_d5__U259":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U278":{ + "affine_func$mul_d6__U261":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U280":{ + "affine_func$mul_d7__U263":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U282":{ + "affine_func$mul_d8__U265":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -2890,42 +3104,82 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U291$c0_lutcnst":{ + "d_0_am__U278$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U291$lut$lut":{ + "d_0_am__U278$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U292$c0_lutcnst":{ + "d_0_am__U279$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U292$lut$lut":{ + "d_0_am__U279$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U293$c0_lutcnst":{ + "d_0_am__U280$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U293$lut$lut":{ + "d_0_am__U280$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U294$c0_lutcnst":{ + "d_0_am__U281$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U294$lut$lut":{ + "d_0_am__U281$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U282$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U282$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U283$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U283$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U284$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U284$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U285$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U285$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -2974,32 +3228,72 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U295$c0_lutcnst":{ + "d_1_am__U286$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U286$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U287$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U287$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U288$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U288$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U289$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U289$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U290$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U295$lut$lut":{ + "d_1_am__U290$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U296$c0_lutcnst":{ + "d_1_am__U291$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U296$lut$lut":{ + "d_1_am__U291$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U297$c0_lutcnst":{ + "d_1_am__U292$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U297$lut$lut":{ + "d_1_am__U292$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3015,7 +3309,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_1_min":{ "genref":"coreir.const", @@ -3048,22 +3342,62 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U298$c0_lutcnst":{ + "d_2_am__U293$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U298$lut$lut":{ + "d_2_am__U293$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U294$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U294$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U295$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U295$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U296$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U296$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_am__U297$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U297$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U299$c0_lutcnst":{ + "d_2_am__U298$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U299$lut$lut":{ + "d_2_am__U298$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -3079,7 +3413,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000002"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_2_min":{ "genref":"coreir.const", @@ -3112,6 +3446,16 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_3_am__U299$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U299$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_am__U300$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -3122,6 +3466,36 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, + "d_3_am__U301$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U301$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U302$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U302$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_3_am__U303$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_3_am__U303$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -3133,7 +3507,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_3_min":{ "genref":"coreir.const", @@ -3166,6 +3540,46 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, + "d_4_am__U304$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U304$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U305$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U305$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U306$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U306$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_4_am__U307$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_4_am__U307$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} @@ -3177,7 +3591,7 @@ "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000000f"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, "d_4_min":{ "genref":"coreir.const", @@ -3210,1002 +3624,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",32]} - }, - "true1_lutcnst":{ + "d_5_am__U308$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true2_lutcnst":{ + "d_5_am__U308$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true3_lutcnst":{ + "d_5_am__U309$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true4_lutcnst":{ + "d_5_am__U309$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "true5_lutcnst":{ + "d_5_am__U310$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - } - }, - "connections":[ - ["d_0_inc.in1","_U289.out"], - ["d_1_inc.in1","_U2891.out"], - ["d_2_inc.in1","_U2892.out"], - ["d_3_inc.in1","_U2893.out"], - ["d_4_inc.in1","_U2894.out"], - ["cmp_time.in1","_U290.out"], - ["affine_func$mul_d0__U274.out","affine_func$add_all__U284.in0"], - ["affine_func$mul_d1__U276.out","affine_func$add_all__U284.in1"], - ["affine_func$add_all__U285.in0","affine_func$add_all__U284.out"], - ["affine_func$mul_d2__U278.out","affine_func$add_all__U285.in1"], - ["affine_func$add_all__U286.in0","affine_func$add_all__U285.out"], - ["affine_func$mul_d3__U280.out","affine_func$add_all__U286.in1"], - ["affine_func$add_all__U287.in0","affine_func$add_all__U286.out"], - ["affine_func$mul_d4__U282.out","affine_func$add_all__U287.in1"], - ["affine_func$add_all__U288.in0","affine_func$add_all__U287.out"], - ["affine_func$const_term_U283.out","affine_func$add_all__U288.in1"], - ["time_diff.in0","affine_func$add_all__U288.out"], - ["affine_func$mul_d0__U274.in0","affine_func$coeff_0_U273.out"], - ["affine_func$mul_d1__U276.in0","affine_func$coeff_1_U275.out"], - ["affine_func$mul_d2__U278.in0","affine_func$coeff_2_U277.out"], - ["affine_func$mul_d3__U280.in0","affine_func$coeff_3_U279.out"], - ["affine_func$mul_d4__U282.in0","affine_func$coeff_4_U281.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U274.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U276.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U278.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U280.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U282.in1"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["cycle_time$count$reg0.out","cycle_time$add.in0"], - ["cycle_time$inc.out","cycle_time$add.in1"], - ["cycle_time$count$enMux.in1","cycle_time$add.out"], - ["cycle_time$ult.in1","cycle_time$add.out"], - ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], - ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true6_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], - ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], - ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], - ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], - ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], - ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], - ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true5_lutcnst.bit.out","cycle_time$count$enMux.sel"], - ["time_diff.in1","cycle_time$count$reg0.out"], - ["cycle_time$ult.in0","cycle_time$max.out"], - ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], - ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U291$lut$lut.bit.in.2","d_0_am__U291$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U291$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U291$lut$lut.bit.in.1"], - ["d_0_am__U292$lut$lut.bit.in.0","d_0_am__U291$lut$lut.bit.out"], - ["d_0_am__U292$lut$lut.bit.in.2","d_0_am__U292$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U292$lut$lut.bit.in.1"], - ["d_0_am__U293$lut$lut.bit.in.0","d_0_am__U292$lut$lut.bit.out"], - ["d_0_am__U293$lut$lut.bit.in.2","d_0_am__U293$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U293$lut$lut.bit.in.1"], - ["d_0_am__U294$lut$lut.bit.in.0","d_0_am__U293$lut$lut.bit.out"], - ["d_0_am__U294$lut$lut.bit.in.2","d_0_am__U294$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U294$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U294$lut$lut.bit.out"], - ["d_0_reg$reg0.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg$reg0.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg$reg0.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg$enMux.in1","d_0_next_value.out"], - ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], - ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], - ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], - ["self.rst_n","d_0_reg$clrMux.sel"], - ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], - ["self.clk","d_0_reg$reg0.clk"], - ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U295$lut$lut.bit.in.2","d_1_am__U295$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U295$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U295$lut$lut.bit.in.1"], - ["d_1_am__U296$lut$lut.bit.in.0","d_1_am__U295$lut$lut.bit.out"], - ["d_1_am__U296$lut$lut.bit.in.2","d_1_am__U296$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U296$lut$lut.bit.in.1"], - ["d_1_am__U297$lut$lut.bit.in.0","d_1_am__U296$lut$lut.bit.out"], - ["d_1_am__U297$lut$lut.bit.in.2","d_1_am__U297$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U297$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U297$lut$lut.bit.out"], - ["d_1_reg$reg0.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg$reg0.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg$reg0.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg$enMux.in1","d_1_next_value.out"], - ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], - ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], - ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], - ["self.rst_n","d_1_reg$clrMux.sel"], - ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], - ["self.clk","d_1_reg$reg0.clk"], - ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U298$lut$lut.bit.in.2","d_2_am__U298$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U298$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U298$lut$lut.bit.in.1"], - ["d_2_am__U299$lut$lut.bit.in.0","d_2_am__U298$lut$lut.bit.out"], - ["d_2_am__U299$lut$lut.bit.in.2","d_2_am__U299$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U299$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U299$lut$lut.bit.out"], - ["d_2_reg$reg0.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg$reg0.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg$reg0.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg$enMux.in1","d_2_next_value.out"], - ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], - ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], - ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], - ["self.rst_n","d_2_reg$clrMux.sel"], - ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], - ["self.clk","d_2_reg$reg0.clk"], - ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U300$lut$lut.bit.in.2","d_3_am__U300$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U300$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U300$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U300$lut$lut.bit.out"], - ["d_3_reg$reg0.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg$reg0.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg$reg0.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg$enMux.in1","d_3_next_value.out"], - ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], - ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], - ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], - ["self.rst_n","d_3_reg$clrMux.sel"], - ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], - ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["true_lutcnst.bit.out","d_4_next_value.sel"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"] - ] - }, - "affine_controller__U320":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",9,["Array",32,"Bit"]]], - ["rst_n","BitIn"] - ]], - "instances":{ - "_U350":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3501":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3502":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3503":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3504":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3505":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3506":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3507":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U3508":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "_U351":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$add_all__U341":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U342":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U343":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U344":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U345":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U346":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U347":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U348":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$add_all__U349":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "affine_func$coeff_0_U322":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "affine_func$coeff_1_U324":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} - }, - "affine_func$coeff_2_U326":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00007e00"]} - }, - "affine_func$coeff_3_U328":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00003f00"]} - }, - "affine_func$coeff_4_U330":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00001f80"]} - }, - "affine_func$coeff_5_U332":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h000000c0"]} - }, - "affine_func$coeff_6_U334":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000040"]} - }, - "affine_func$coeff_7_U336":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000008"]} - }, - "affine_func$coeff_8_U338":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "affine_func$const_term_U340":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} - }, - "affine_func$mul_d0__U323":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d1__U325":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d2__U327":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d3__U329":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d4__U331":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d5__U333":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d6__U335":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d7__U337":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "affine_func$mul_d8__U339":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "cycle_time$and$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$and$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "cycle_time$count$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$count$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "cycle_time$inc":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "cycle_time$max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} - }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} - }, - "cycle_time$ult":{ - "genref":"coreir.ult", - "genargs":{"width":["Int",32]} - }, - "d_0_am__U352$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U352$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U353$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U353$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U354$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U354$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U355$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U355$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U356$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U356$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U357$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U357$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U358$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U358$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_am__U359$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_0_am__U359$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_0_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_0_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_0_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_1_am__U360$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U360$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U361$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U361$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U362$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U362$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U363$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U363$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U364$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U364$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U365$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U365$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_am__U366$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_1_am__U366$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_1_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_1_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_2_am__U367$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U367$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U368$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U368$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U369$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U369$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U370$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U370$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U371$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U371$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_am__U372$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_2_am__U372$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_3_am__U373$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U373$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U374$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U374$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U375$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U375$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U376$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U376$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_am__U377$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_3_am__U377$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_4_am__U378$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U378$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U379$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U379$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U380$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U380$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_am__U381$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_4_am__U381$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} - }, - "d_4_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} - }, - "d_4_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} - }, - "d_5_am__U382$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U382$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U383$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U383$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} - }, - "d_5_am__U384$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} - }, - "d_5_am__U384$lut$lut":{ + "d_5_am__U310$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4254,22 +3698,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U385$c0_lutcnst":{ + "d_6_am__U311$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U385$lut$lut":{ + "d_6_am__U311$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_6_am__U386$c0_lutcnst":{ + "d_6_am__U312$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U386$lut$lut":{ + "d_6_am__U312$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4318,12 +3762,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_7_am__U387$c0_lutcnst":{ + "d_7_am__U313$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_7_am__U387$lut$lut":{ + "d_7_am__U313$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -4477,53 +3921,53 @@ } }, "connections":[ - ["d_0_inc.in1","_U350.out"], - ["d_1_inc.in1","_U3501.out"], - ["d_2_inc.in1","_U3502.out"], - ["d_3_inc.in1","_U3503.out"], - ["d_4_inc.in1","_U3504.out"], - ["d_5_inc.in1","_U3505.out"], - ["d_6_inc.in1","_U3506.out"], - ["d_7_inc.in1","_U3507.out"], - ["d_8_inc.in1","_U3508.out"], - ["cmp_time.in1","_U351.out"], - ["affine_func$mul_d0__U323.out","affine_func$add_all__U341.in0"], - ["affine_func$mul_d1__U325.out","affine_func$add_all__U341.in1"], - ["affine_func$add_all__U342.in0","affine_func$add_all__U341.out"], - ["affine_func$mul_d2__U327.out","affine_func$add_all__U342.in1"], - ["affine_func$add_all__U343.in0","affine_func$add_all__U342.out"], - ["affine_func$mul_d3__U329.out","affine_func$add_all__U343.in1"], - ["affine_func$add_all__U344.in0","affine_func$add_all__U343.out"], - ["affine_func$mul_d4__U331.out","affine_func$add_all__U344.in1"], - ["affine_func$add_all__U345.in0","affine_func$add_all__U344.out"], - ["affine_func$mul_d5__U333.out","affine_func$add_all__U345.in1"], - ["affine_func$add_all__U346.in0","affine_func$add_all__U345.out"], - ["affine_func$mul_d6__U335.out","affine_func$add_all__U346.in1"], - ["affine_func$add_all__U347.in0","affine_func$add_all__U346.out"], - ["affine_func$mul_d7__U337.out","affine_func$add_all__U347.in1"], - ["affine_func$add_all__U348.in0","affine_func$add_all__U347.out"], - ["affine_func$mul_d8__U339.out","affine_func$add_all__U348.in1"], - ["affine_func$add_all__U349.in0","affine_func$add_all__U348.out"], - ["affine_func$const_term_U340.out","affine_func$add_all__U349.in1"], - ["time_diff.in0","affine_func$add_all__U349.out"], - ["affine_func$mul_d0__U323.in0","affine_func$coeff_0_U322.out"], - ["affine_func$mul_d1__U325.in0","affine_func$coeff_1_U324.out"], - ["affine_func$mul_d2__U327.in0","affine_func$coeff_2_U326.out"], - ["affine_func$mul_d3__U329.in0","affine_func$coeff_3_U328.out"], - ["affine_func$mul_d4__U331.in0","affine_func$coeff_4_U330.out"], - ["affine_func$mul_d5__U333.in0","affine_func$coeff_5_U332.out"], - ["affine_func$mul_d6__U335.in0","affine_func$coeff_6_U334.out"], - ["affine_func$mul_d7__U337.in0","affine_func$coeff_7_U336.out"], - ["affine_func$mul_d8__U339.in0","affine_func$coeff_8_U338.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U323.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U325.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U327.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U329.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U331.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U333.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U335.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U337.in1"], - ["d_8_reg$reg0.out","affine_func$mul_d8__U339.in1"], + ["d_0_inc.in1","_U276.out"], + ["d_1_inc.in1","_U2761.out"], + ["d_2_inc.in1","_U2762.out"], + ["d_3_inc.in1","_U2763.out"], + ["d_4_inc.in1","_U2764.out"], + ["d_5_inc.in1","_U2765.out"], + ["d_6_inc.in1","_U2766.out"], + ["d_7_inc.in1","_U2767.out"], + ["d_8_inc.in1","_U2768.out"], + ["cmp_time.in1","_U277.out"], + ["affine_func$mul_d0__U249.out","affine_func$add_all__U267.in0"], + ["affine_func$mul_d1__U251.out","affine_func$add_all__U267.in1"], + ["affine_func$add_all__U268.in0","affine_func$add_all__U267.out"], + ["affine_func$mul_d2__U253.out","affine_func$add_all__U268.in1"], + ["affine_func$add_all__U269.in0","affine_func$add_all__U268.out"], + ["affine_func$mul_d3__U255.out","affine_func$add_all__U269.in1"], + ["affine_func$add_all__U270.in0","affine_func$add_all__U269.out"], + ["affine_func$mul_d4__U257.out","affine_func$add_all__U270.in1"], + ["affine_func$add_all__U271.in0","affine_func$add_all__U270.out"], + ["affine_func$mul_d5__U259.out","affine_func$add_all__U271.in1"], + ["affine_func$add_all__U272.in0","affine_func$add_all__U271.out"], + ["affine_func$mul_d6__U261.out","affine_func$add_all__U272.in1"], + ["affine_func$add_all__U273.in0","affine_func$add_all__U272.out"], + ["affine_func$mul_d7__U263.out","affine_func$add_all__U273.in1"], + ["affine_func$add_all__U274.in0","affine_func$add_all__U273.out"], + ["affine_func$mul_d8__U265.out","affine_func$add_all__U274.in1"], + ["affine_func$add_all__U275.in0","affine_func$add_all__U274.out"], + ["affine_func$const_term_U266.out","affine_func$add_all__U275.in1"], + ["time_diff.in0","affine_func$add_all__U275.out"], + ["affine_func$mul_d0__U249.in0","affine_func$coeff_0_U248.out"], + ["affine_func$mul_d1__U251.in0","affine_func$coeff_1_U250.out"], + ["affine_func$mul_d2__U253.in0","affine_func$coeff_2_U252.out"], + ["affine_func$mul_d3__U255.in0","affine_func$coeff_3_U254.out"], + ["affine_func$mul_d4__U257.in0","affine_func$coeff_4_U256.out"], + ["affine_func$mul_d5__U259.in0","affine_func$coeff_5_U258.out"], + ["affine_func$mul_d6__U261.in0","affine_func$coeff_6_U260.out"], + ["affine_func$mul_d7__U263.in0","affine_func$coeff_7_U262.out"], + ["affine_func$mul_d8__U265.in0","affine_func$coeff_8_U264.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U249.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U251.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U253.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U255.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U257.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U259.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U261.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U263.in1"], + ["d_8_reg$reg0.out","affine_func$mul_d8__U265.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -4553,31 +3997,31 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U352$lut$lut.bit.in.2","d_0_am__U352$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U352$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U352$lut$lut.bit.in.1"], - ["d_0_am__U353$lut$lut.bit.in.0","d_0_am__U352$lut$lut.bit.out"], - ["d_0_am__U353$lut$lut.bit.in.2","d_0_am__U353$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U353$lut$lut.bit.in.1"], - ["d_0_am__U354$lut$lut.bit.in.0","d_0_am__U353$lut$lut.bit.out"], - ["d_0_am__U354$lut$lut.bit.in.2","d_0_am__U354$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U354$lut$lut.bit.in.1"], - ["d_0_am__U355$lut$lut.bit.in.0","d_0_am__U354$lut$lut.bit.out"], - ["d_0_am__U355$lut$lut.bit.in.2","d_0_am__U355$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U355$lut$lut.bit.in.1"], - ["d_0_am__U356$lut$lut.bit.in.0","d_0_am__U355$lut$lut.bit.out"], - ["d_0_am__U356$lut$lut.bit.in.2","d_0_am__U356$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U356$lut$lut.bit.in.1"], - ["d_0_am__U357$lut$lut.bit.in.0","d_0_am__U356$lut$lut.bit.out"], - ["d_0_am__U357$lut$lut.bit.in.2","d_0_am__U357$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U357$lut$lut.bit.in.1"], - ["d_0_am__U358$lut$lut.bit.in.0","d_0_am__U357$lut$lut.bit.out"], - ["d_0_am__U358$lut$lut.bit.in.2","d_0_am__U358$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U358$lut$lut.bit.in.1"], - ["d_0_am__U359$lut$lut.bit.in.0","d_0_am__U358$lut$lut.bit.out"], - ["d_0_am__U359$lut$lut.bit.in.2","d_0_am__U359$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_0_am__U359$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U359$lut$lut.bit.out"], + ["d_0_am__U278$lut$lut.bit.in.2","d_0_am__U278$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U278$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U278$lut$lut.bit.in.1"], + ["d_0_am__U279$lut$lut.bit.in.0","d_0_am__U278$lut$lut.bit.out"], + ["d_0_am__U279$lut$lut.bit.in.2","d_0_am__U279$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U279$lut$lut.bit.in.1"], + ["d_0_am__U280$lut$lut.bit.in.0","d_0_am__U279$lut$lut.bit.out"], + ["d_0_am__U280$lut$lut.bit.in.2","d_0_am__U280$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U280$lut$lut.bit.in.1"], + ["d_0_am__U281$lut$lut.bit.in.0","d_0_am__U280$lut$lut.bit.out"], + ["d_0_am__U281$lut$lut.bit.in.2","d_0_am__U281$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U281$lut$lut.bit.in.1"], + ["d_0_am__U282$lut$lut.bit.in.0","d_0_am__U281$lut$lut.bit.out"], + ["d_0_am__U282$lut$lut.bit.in.2","d_0_am__U282$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U282$lut$lut.bit.in.1"], + ["d_0_am__U283$lut$lut.bit.in.0","d_0_am__U282$lut$lut.bit.out"], + ["d_0_am__U283$lut$lut.bit.in.2","d_0_am__U283$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U283$lut$lut.bit.in.1"], + ["d_0_am__U284$lut$lut.bit.in.0","d_0_am__U283$lut$lut.bit.out"], + ["d_0_am__U284$lut$lut.bit.in.2","d_0_am__U284$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U284$lut$lut.bit.in.1"], + ["d_0_am__U285$lut$lut.bit.in.0","d_0_am__U284$lut$lut.bit.out"], + ["d_0_am__U285$lut$lut.bit.in.2","d_0_am__U285$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_0_am__U285$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U285$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -4594,28 +4038,28 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U360$lut$lut.bit.in.2","d_1_am__U360$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U360$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U360$lut$lut.bit.in.1"], - ["d_1_am__U361$lut$lut.bit.in.0","d_1_am__U360$lut$lut.bit.out"], - ["d_1_am__U361$lut$lut.bit.in.2","d_1_am__U361$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U361$lut$lut.bit.in.1"], - ["d_1_am__U362$lut$lut.bit.in.0","d_1_am__U361$lut$lut.bit.out"], - ["d_1_am__U362$lut$lut.bit.in.2","d_1_am__U362$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U362$lut$lut.bit.in.1"], - ["d_1_am__U363$lut$lut.bit.in.0","d_1_am__U362$lut$lut.bit.out"], - ["d_1_am__U363$lut$lut.bit.in.2","d_1_am__U363$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U363$lut$lut.bit.in.1"], - ["d_1_am__U364$lut$lut.bit.in.0","d_1_am__U363$lut$lut.bit.out"], - ["d_1_am__U364$lut$lut.bit.in.2","d_1_am__U364$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U364$lut$lut.bit.in.1"], - ["d_1_am__U365$lut$lut.bit.in.0","d_1_am__U364$lut$lut.bit.out"], - ["d_1_am__U365$lut$lut.bit.in.2","d_1_am__U365$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U365$lut$lut.bit.in.1"], - ["d_1_am__U366$lut$lut.bit.in.0","d_1_am__U365$lut$lut.bit.out"], - ["d_1_am__U366$lut$lut.bit.in.2","d_1_am__U366$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_1_am__U366$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U366$lut$lut.bit.out"], + ["d_1_am__U286$lut$lut.bit.in.2","d_1_am__U286$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U286$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U286$lut$lut.bit.in.1"], + ["d_1_am__U287$lut$lut.bit.in.0","d_1_am__U286$lut$lut.bit.out"], + ["d_1_am__U287$lut$lut.bit.in.2","d_1_am__U287$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U287$lut$lut.bit.in.1"], + ["d_1_am__U288$lut$lut.bit.in.0","d_1_am__U287$lut$lut.bit.out"], + ["d_1_am__U288$lut$lut.bit.in.2","d_1_am__U288$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U288$lut$lut.bit.in.1"], + ["d_1_am__U289$lut$lut.bit.in.0","d_1_am__U288$lut$lut.bit.out"], + ["d_1_am__U289$lut$lut.bit.in.2","d_1_am__U289$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U289$lut$lut.bit.in.1"], + ["d_1_am__U290$lut$lut.bit.in.0","d_1_am__U289$lut$lut.bit.out"], + ["d_1_am__U290$lut$lut.bit.in.2","d_1_am__U290$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U290$lut$lut.bit.in.1"], + ["d_1_am__U291$lut$lut.bit.in.0","d_1_am__U290$lut$lut.bit.out"], + ["d_1_am__U291$lut$lut.bit.in.2","d_1_am__U291$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U291$lut$lut.bit.in.1"], + ["d_1_am__U292$lut$lut.bit.in.0","d_1_am__U291$lut$lut.bit.out"], + ["d_1_am__U292$lut$lut.bit.in.2","d_1_am__U292$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_1_am__U292$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U292$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -4632,25 +4076,25 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U367$lut$lut.bit.in.2","d_2_am__U367$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U367$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U367$lut$lut.bit.in.1"], - ["d_2_am__U368$lut$lut.bit.in.0","d_2_am__U367$lut$lut.bit.out"], - ["d_2_am__U368$lut$lut.bit.in.2","d_2_am__U368$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U368$lut$lut.bit.in.1"], - ["d_2_am__U369$lut$lut.bit.in.0","d_2_am__U368$lut$lut.bit.out"], - ["d_2_am__U369$lut$lut.bit.in.2","d_2_am__U369$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U369$lut$lut.bit.in.1"], - ["d_2_am__U370$lut$lut.bit.in.0","d_2_am__U369$lut$lut.bit.out"], - ["d_2_am__U370$lut$lut.bit.in.2","d_2_am__U370$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U370$lut$lut.bit.in.1"], - ["d_2_am__U371$lut$lut.bit.in.0","d_2_am__U370$lut$lut.bit.out"], - ["d_2_am__U371$lut$lut.bit.in.2","d_2_am__U371$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U371$lut$lut.bit.in.1"], - ["d_2_am__U372$lut$lut.bit.in.0","d_2_am__U371$lut$lut.bit.out"], - ["d_2_am__U372$lut$lut.bit.in.2","d_2_am__U372$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_2_am__U372$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U372$lut$lut.bit.out"], + ["d_2_am__U293$lut$lut.bit.in.2","d_2_am__U293$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U293$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U293$lut$lut.bit.in.1"], + ["d_2_am__U294$lut$lut.bit.in.0","d_2_am__U293$lut$lut.bit.out"], + ["d_2_am__U294$lut$lut.bit.in.2","d_2_am__U294$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U294$lut$lut.bit.in.1"], + ["d_2_am__U295$lut$lut.bit.in.0","d_2_am__U294$lut$lut.bit.out"], + ["d_2_am__U295$lut$lut.bit.in.2","d_2_am__U295$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U295$lut$lut.bit.in.1"], + ["d_2_am__U296$lut$lut.bit.in.0","d_2_am__U295$lut$lut.bit.out"], + ["d_2_am__U296$lut$lut.bit.in.2","d_2_am__U296$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U296$lut$lut.bit.in.1"], + ["d_2_am__U297$lut$lut.bit.in.0","d_2_am__U296$lut$lut.bit.out"], + ["d_2_am__U297$lut$lut.bit.in.2","d_2_am__U297$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U297$lut$lut.bit.in.1"], + ["d_2_am__U298$lut$lut.bit.in.0","d_2_am__U297$lut$lut.bit.out"], + ["d_2_am__U298$lut$lut.bit.in.2","d_2_am__U298$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_2_am__U298$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U298$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -4667,22 +4111,22 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U373$lut$lut.bit.in.2","d_3_am__U373$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U373$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U373$lut$lut.bit.in.1"], - ["d_3_am__U374$lut$lut.bit.in.0","d_3_am__U373$lut$lut.bit.out"], - ["d_3_am__U374$lut$lut.bit.in.2","d_3_am__U374$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U374$lut$lut.bit.in.1"], - ["d_3_am__U375$lut$lut.bit.in.0","d_3_am__U374$lut$lut.bit.out"], - ["d_3_am__U375$lut$lut.bit.in.2","d_3_am__U375$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U375$lut$lut.bit.in.1"], - ["d_3_am__U376$lut$lut.bit.in.0","d_3_am__U375$lut$lut.bit.out"], - ["d_3_am__U376$lut$lut.bit.in.2","d_3_am__U376$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U376$lut$lut.bit.in.1"], - ["d_3_am__U377$lut$lut.bit.in.0","d_3_am__U376$lut$lut.bit.out"], - ["d_3_am__U377$lut$lut.bit.in.2","d_3_am__U377$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_3_am__U377$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U377$lut$lut.bit.out"], + ["d_3_am__U299$lut$lut.bit.in.2","d_3_am__U299$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U299$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U299$lut$lut.bit.in.1"], + ["d_3_am__U300$lut$lut.bit.in.0","d_3_am__U299$lut$lut.bit.out"], + ["d_3_am__U300$lut$lut.bit.in.2","d_3_am__U300$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U300$lut$lut.bit.in.1"], + ["d_3_am__U301$lut$lut.bit.in.0","d_3_am__U300$lut$lut.bit.out"], + ["d_3_am__U301$lut$lut.bit.in.2","d_3_am__U301$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U301$lut$lut.bit.in.1"], + ["d_3_am__U302$lut$lut.bit.in.0","d_3_am__U301$lut$lut.bit.out"], + ["d_3_am__U302$lut$lut.bit.in.2","d_3_am__U302$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U302$lut$lut.bit.in.1"], + ["d_3_am__U303$lut$lut.bit.in.0","d_3_am__U302$lut$lut.bit.out"], + ["d_3_am__U303$lut$lut.bit.in.2","d_3_am__U303$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_3_am__U303$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U303$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -4699,19 +4143,19 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U378$lut$lut.bit.in.2","d_4_am__U378$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U378$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U378$lut$lut.bit.in.1"], - ["d_4_am__U379$lut$lut.bit.in.0","d_4_am__U378$lut$lut.bit.out"], - ["d_4_am__U379$lut$lut.bit.in.2","d_4_am__U379$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U379$lut$lut.bit.in.1"], - ["d_4_am__U380$lut$lut.bit.in.0","d_4_am__U379$lut$lut.bit.out"], - ["d_4_am__U380$lut$lut.bit.in.2","d_4_am__U380$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U380$lut$lut.bit.in.1"], - ["d_4_am__U381$lut$lut.bit.in.0","d_4_am__U380$lut$lut.bit.out"], - ["d_4_am__U381$lut$lut.bit.in.2","d_4_am__U381$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_4_am__U381$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U381$lut$lut.bit.out"], + ["d_4_am__U304$lut$lut.bit.in.2","d_4_am__U304$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U304$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U304$lut$lut.bit.in.1"], + ["d_4_am__U305$lut$lut.bit.in.0","d_4_am__U304$lut$lut.bit.out"], + ["d_4_am__U305$lut$lut.bit.in.2","d_4_am__U305$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U305$lut$lut.bit.in.1"], + ["d_4_am__U306$lut$lut.bit.in.0","d_4_am__U305$lut$lut.bit.out"], + ["d_4_am__U306$lut$lut.bit.in.2","d_4_am__U306$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_4_am__U306$lut$lut.bit.in.1"], + ["d_4_am__U307$lut$lut.bit.in.0","d_4_am__U306$lut$lut.bit.out"], + ["d_4_am__U307$lut$lut.bit.in.2","d_4_am__U307$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_4_am__U307$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U307$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -4728,16 +4172,16 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U382$lut$lut.bit.in.2","d_5_am__U382$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U382$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U382$lut$lut.bit.in.1"], - ["d_5_am__U383$lut$lut.bit.in.0","d_5_am__U382$lut$lut.bit.out"], - ["d_5_am__U383$lut$lut.bit.in.2","d_5_am__U383$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U383$lut$lut.bit.in.1"], - ["d_5_am__U384$lut$lut.bit.in.0","d_5_am__U383$lut$lut.bit.out"], - ["d_5_am__U384$lut$lut.bit.in.2","d_5_am__U384$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_5_am__U384$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U384$lut$lut.bit.out"], + ["d_5_am__U308$lut$lut.bit.in.2","d_5_am__U308$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U308$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U308$lut$lut.bit.in.1"], + ["d_5_am__U309$lut$lut.bit.in.0","d_5_am__U308$lut$lut.bit.out"], + ["d_5_am__U309$lut$lut.bit.in.2","d_5_am__U309$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U309$lut$lut.bit.in.1"], + ["d_5_am__U310$lut$lut.bit.in.0","d_5_am__U309$lut$lut.bit.out"], + ["d_5_am__U310$lut$lut.bit.in.2","d_5_am__U310$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_5_am__U310$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U310$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -4754,13 +4198,13 @@ ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], ["self.clk","d_5_reg$reg0.clk"], ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U385$lut$lut.bit.in.2","d_6_am__U385$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U385$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U385$lut$lut.bit.in.1"], - ["d_6_am__U386$lut$lut.bit.in.0","d_6_am__U385$lut$lut.bit.out"], - ["d_6_am__U386$lut$lut.bit.in.2","d_6_am__U386$c0_lutcnst.bit.out"], - ["d_8_at_max.out","d_6_am__U386$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U386$lut$lut.bit.out"], + ["d_6_am__U311$lut$lut.bit.in.2","d_6_am__U311$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U311$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U311$lut$lut.bit.in.1"], + ["d_6_am__U312$lut$lut.bit.in.0","d_6_am__U311$lut$lut.bit.out"], + ["d_6_am__U312$lut$lut.bit.in.2","d_6_am__U312$c0_lutcnst.bit.out"], + ["d_8_at_max.out","d_6_am__U312$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U312$lut$lut.bit.out"], ["d_6_reg$reg0.out","d_6_at_max.in0"], ["d_6_max.out","d_6_at_max.in1"], ["d_6_next_value_at_max.sel","d_6_at_max.out"], @@ -4777,10 +4221,10 @@ ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], ["self.clk","d_6_reg$reg0.clk"], ["self.d.6","d_6_reg$reg0.out"], - ["d_7_am__U387$lut$lut.bit.in.2","d_7_am__U387$c0_lutcnst.bit.out"], - ["true8_lutcnst.bit.out","d_7_am__U387$lut$lut.bit.in.0"], - ["d_8_at_max.out","d_7_am__U387$lut$lut.bit.in.1"], - ["d_7_next_value.sel","d_7_am__U387$lut$lut.bit.out"], + ["d_7_am__U313$lut$lut.bit.in.2","d_7_am__U313$c0_lutcnst.bit.out"], + ["true8_lutcnst.bit.out","d_7_am__U313$lut$lut.bit.in.0"], + ["d_8_at_max.out","d_7_am__U313$lut$lut.bit.in.1"], + ["d_7_next_value.sel","d_7_am__U313$lut$lut.bit.out"], ["d_7_reg$reg0.out","d_7_at_max.in0"], ["d_7_max.out","d_7_at_max.in1"], ["d_7_next_value_at_max.sel","d_7_at_max.out"], @@ -4816,7 +4260,7 @@ ["self.d.8","d_8_reg$reg0.out"] ] }, - "affine_controller__U421":{ + "affine_controller__U347":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -4824,49 +4268,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U430":{ + "_U356":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4301":{ + "_U3561":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U431":{ + "_U357":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U428":{ + "affine_func$add_all__U354":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U429":{ + "affine_func$add_all__U355":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U423":{ + "affine_func$coeff_0_U349":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U425":{ + "affine_func$coeff_1_U351":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U427":{ + "affine_func$const_term_U353":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U424":{ + "affine_func$mul_d0__U350":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U426":{ + "affine_func$mul_d1__U352":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -4930,12 +4374,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U432$c0_lutcnst":{ + "d_0_am__U358$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U432$lut$lut":{ + "d_0_am__U358$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5054,18 +4498,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U430.out"], - ["d_1_inc.in1","_U4301.out"], - ["cmp_time.in1","_U431.out"], - ["affine_func$mul_d0__U424.out","affine_func$add_all__U428.in0"], - ["affine_func$mul_d1__U426.out","affine_func$add_all__U428.in1"], - ["affine_func$add_all__U429.in0","affine_func$add_all__U428.out"], - ["affine_func$const_term_U427.out","affine_func$add_all__U429.in1"], - ["time_diff.in0","affine_func$add_all__U429.out"], - ["affine_func$mul_d0__U424.in0","affine_func$coeff_0_U423.out"], - ["affine_func$mul_d1__U426.in0","affine_func$coeff_1_U425.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U424.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U426.in1"], + ["d_0_inc.in1","_U356.out"], + ["d_1_inc.in1","_U3561.out"], + ["cmp_time.in1","_U357.out"], + ["affine_func$mul_d0__U350.out","affine_func$add_all__U354.in0"], + ["affine_func$mul_d1__U352.out","affine_func$add_all__U354.in1"], + ["affine_func$add_all__U355.in0","affine_func$add_all__U354.out"], + ["affine_func$const_term_U353.out","affine_func$add_all__U355.in1"], + ["time_diff.in0","affine_func$add_all__U355.out"], + ["affine_func$mul_d0__U350.in0","affine_func$coeff_0_U349.out"], + ["affine_func$mul_d1__U352.in0","affine_func$coeff_1_U351.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U350.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U352.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5088,10 +4532,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U432$lut$lut.bit.in.2","d_0_am__U432$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U432$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U432$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U432$lut$lut.bit.out"], + ["d_0_am__U358$lut$lut.bit.in.2","d_0_am__U358$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U358$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U358$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U358$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5127,7 +4571,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U436":{ + "affine_controller__U361":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5135,49 +4579,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U445":{ + "_U370":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4451":{ + "_U3701":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U446":{ + "_U371":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U443":{ + "affine_func$add_all__U368":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U444":{ + "affine_func$add_all__U369":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U438":{ + "affine_func$coeff_0_U363":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U440":{ + "affine_func$coeff_1_U365":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U442":{ + "affine_func$const_term_U367":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U439":{ + "affine_func$mul_d0__U364":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U441":{ + "affine_func$mul_d1__U366":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5241,12 +4685,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U447$c0_lutcnst":{ + "d_0_am__U372$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U447$lut$lut":{ + "d_0_am__U372$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5365,18 +4809,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U445.out"], - ["d_1_inc.in1","_U4451.out"], - ["cmp_time.in1","_U446.out"], - ["affine_func$mul_d0__U439.out","affine_func$add_all__U443.in0"], - ["affine_func$mul_d1__U441.out","affine_func$add_all__U443.in1"], - ["affine_func$add_all__U444.in0","affine_func$add_all__U443.out"], - ["affine_func$const_term_U442.out","affine_func$add_all__U444.in1"], - ["time_diff.in0","affine_func$add_all__U444.out"], - ["affine_func$mul_d0__U439.in0","affine_func$coeff_0_U438.out"], - ["affine_func$mul_d1__U441.in0","affine_func$coeff_1_U440.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U439.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U441.in1"], + ["d_0_inc.in1","_U370.out"], + ["d_1_inc.in1","_U3701.out"], + ["cmp_time.in1","_U371.out"], + ["affine_func$mul_d0__U364.out","affine_func$add_all__U368.in0"], + ["affine_func$mul_d1__U366.out","affine_func$add_all__U368.in1"], + ["affine_func$add_all__U369.in0","affine_func$add_all__U368.out"], + ["affine_func$const_term_U367.out","affine_func$add_all__U369.in1"], + ["time_diff.in0","affine_func$add_all__U369.out"], + ["affine_func$mul_d0__U364.in0","affine_func$coeff_0_U363.out"], + ["affine_func$mul_d1__U366.in0","affine_func$coeff_1_U365.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U364.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U366.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5399,10 +4843,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U447$lut$lut.bit.in.2","d_0_am__U447$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U447$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U447$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U447$lut$lut.bit.out"], + ["d_0_am__U372$lut$lut.bit.in.2","d_0_am__U372$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U372$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U372$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U372$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5438,7 +4882,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U451":{ + "affine_controller__U375":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5446,49 +4890,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U460":{ + "_U384":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4601":{ + "_U3841":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U461":{ + "_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U458":{ + "affine_func$add_all__U382":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U459":{ + "affine_func$add_all__U383":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U453":{ + "affine_func$coeff_0_U377":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U455":{ + "affine_func$coeff_1_U379":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U457":{ + "affine_func$const_term_U381":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U454":{ + "affine_func$mul_d0__U378":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U456":{ + "affine_func$mul_d1__U380":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5552,12 +4996,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U462$c0_lutcnst":{ + "d_0_am__U386$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U462$lut$lut":{ + "d_0_am__U386$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5676,18 +5120,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U460.out"], - ["d_1_inc.in1","_U4601.out"], - ["cmp_time.in1","_U461.out"], - ["affine_func$mul_d0__U454.out","affine_func$add_all__U458.in0"], - ["affine_func$mul_d1__U456.out","affine_func$add_all__U458.in1"], - ["affine_func$add_all__U459.in0","affine_func$add_all__U458.out"], - ["affine_func$const_term_U457.out","affine_func$add_all__U459.in1"], - ["time_diff.in0","affine_func$add_all__U459.out"], - ["affine_func$mul_d0__U454.in0","affine_func$coeff_0_U453.out"], - ["affine_func$mul_d1__U456.in0","affine_func$coeff_1_U455.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U454.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U456.in1"], + ["d_0_inc.in1","_U384.out"], + ["d_1_inc.in1","_U3841.out"], + ["cmp_time.in1","_U385.out"], + ["affine_func$mul_d0__U378.out","affine_func$add_all__U382.in0"], + ["affine_func$mul_d1__U380.out","affine_func$add_all__U382.in1"], + ["affine_func$add_all__U383.in0","affine_func$add_all__U382.out"], + ["affine_func$const_term_U381.out","affine_func$add_all__U383.in1"], + ["time_diff.in0","affine_func$add_all__U383.out"], + ["affine_func$mul_d0__U378.in0","affine_func$coeff_0_U377.out"], + ["affine_func$mul_d1__U380.in0","affine_func$coeff_1_U379.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U378.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U380.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -5710,10 +5154,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U462$lut$lut.bit.in.2","d_0_am__U462$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U462$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U462$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U462$lut$lut.bit.out"], + ["d_0_am__U386$lut$lut.bit.in.2","d_0_am__U386$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U386$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U386$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U386$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -5749,7 +5193,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U466":{ + "affine_controller__U389":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -5757,49 +5201,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U475":{ + "_U398":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4751":{ + "_U3981":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U476":{ + "_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U473":{ + "affine_func$add_all__U396":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U474":{ + "affine_func$add_all__U397":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U468":{ + "affine_func$coeff_0_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U470":{ + "affine_func$coeff_1_U393":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U472":{ + "affine_func$const_term_U395":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U469":{ + "affine_func$mul_d0__U392":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U471":{ + "affine_func$mul_d1__U394":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -5863,12 +5307,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U477$c0_lutcnst":{ + "d_0_am__U400$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U477$lut$lut":{ + "d_0_am__U400$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -5987,18 +5431,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U475.out"], - ["d_1_inc.in1","_U4751.out"], - ["cmp_time.in1","_U476.out"], - ["affine_func$mul_d0__U469.out","affine_func$add_all__U473.in0"], - ["affine_func$mul_d1__U471.out","affine_func$add_all__U473.in1"], - ["affine_func$add_all__U474.in0","affine_func$add_all__U473.out"], - ["affine_func$const_term_U472.out","affine_func$add_all__U474.in1"], - ["time_diff.in0","affine_func$add_all__U474.out"], - ["affine_func$mul_d0__U469.in0","affine_func$coeff_0_U468.out"], - ["affine_func$mul_d1__U471.in0","affine_func$coeff_1_U470.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U469.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U471.in1"], + ["d_0_inc.in1","_U398.out"], + ["d_1_inc.in1","_U3981.out"], + ["cmp_time.in1","_U399.out"], + ["affine_func$mul_d0__U392.out","affine_func$add_all__U396.in0"], + ["affine_func$mul_d1__U394.out","affine_func$add_all__U396.in1"], + ["affine_func$add_all__U397.in0","affine_func$add_all__U396.out"], + ["affine_func$const_term_U395.out","affine_func$add_all__U397.in1"], + ["time_diff.in0","affine_func$add_all__U397.out"], + ["affine_func$mul_d0__U392.in0","affine_func$coeff_0_U391.out"], + ["affine_func$mul_d1__U394.in0","affine_func$coeff_1_U393.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U392.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U394.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6021,10 +5465,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U477$lut$lut.bit.in.2","d_0_am__U477$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U477$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U477$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U477$lut$lut.bit.out"], + ["d_0_am__U400$lut$lut.bit.in.2","d_0_am__U400$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U400$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U400$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U400$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6060,7 +5504,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U481":{ + "affine_controller__U403":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6068,49 +5512,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U490":{ + "_U412":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U4901":{ + "_U4121":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U491":{ + "_U413":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U488":{ + "affine_func$add_all__U410":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U489":{ + "affine_func$add_all__U411":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U483":{ + "affine_func$coeff_0_U405":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U485":{ + "affine_func$coeff_1_U407":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U487":{ + "affine_func$const_term_U409":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U484":{ + "affine_func$mul_d0__U406":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U486":{ + "affine_func$mul_d1__U408":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6174,12 +5618,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U492$c0_lutcnst":{ + "d_0_am__U414$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U492$lut$lut":{ + "d_0_am__U414$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6298,18 +5742,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U490.out"], - ["d_1_inc.in1","_U4901.out"], - ["cmp_time.in1","_U491.out"], - ["affine_func$mul_d0__U484.out","affine_func$add_all__U488.in0"], - ["affine_func$mul_d1__U486.out","affine_func$add_all__U488.in1"], - ["affine_func$add_all__U489.in0","affine_func$add_all__U488.out"], - ["affine_func$const_term_U487.out","affine_func$add_all__U489.in1"], - ["time_diff.in0","affine_func$add_all__U489.out"], - ["affine_func$mul_d0__U484.in0","affine_func$coeff_0_U483.out"], - ["affine_func$mul_d1__U486.in0","affine_func$coeff_1_U485.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U484.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U486.in1"], + ["d_0_inc.in1","_U412.out"], + ["d_1_inc.in1","_U4121.out"], + ["cmp_time.in1","_U413.out"], + ["affine_func$mul_d0__U406.out","affine_func$add_all__U410.in0"], + ["affine_func$mul_d1__U408.out","affine_func$add_all__U410.in1"], + ["affine_func$add_all__U411.in0","affine_func$add_all__U410.out"], + ["affine_func$const_term_U409.out","affine_func$add_all__U411.in1"], + ["time_diff.in0","affine_func$add_all__U411.out"], + ["affine_func$mul_d0__U406.in0","affine_func$coeff_0_U405.out"], + ["affine_func$mul_d1__U408.in0","affine_func$coeff_1_U407.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U406.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U408.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6332,10 +5776,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U492$lut$lut.bit.in.2","d_0_am__U492$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U492$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U492$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U492$lut$lut.bit.out"], + ["d_0_am__U414$lut$lut.bit.in.2","d_0_am__U414$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U414$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U414$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U414$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6371,7 +5815,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U496":{ + "affine_controller__U417":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6379,49 +5823,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U505":{ + "_U426":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5051":{ + "_U4261":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U506":{ + "_U427":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U503":{ + "affine_func$add_all__U424":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U504":{ + "affine_func$add_all__U425":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U498":{ + "affine_func$coeff_0_U419":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U500":{ + "affine_func$coeff_1_U421":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U502":{ + "affine_func$const_term_U423":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U499":{ + "affine_func$mul_d0__U420":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U501":{ + "affine_func$mul_d1__U422":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6485,12 +5929,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U507$c0_lutcnst":{ + "d_0_am__U428$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U507$lut$lut":{ + "d_0_am__U428$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6609,18 +6053,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U505.out"], - ["d_1_inc.in1","_U5051.out"], - ["cmp_time.in1","_U506.out"], - ["affine_func$mul_d0__U499.out","affine_func$add_all__U503.in0"], - ["affine_func$mul_d1__U501.out","affine_func$add_all__U503.in1"], - ["affine_func$add_all__U504.in0","affine_func$add_all__U503.out"], - ["affine_func$const_term_U502.out","affine_func$add_all__U504.in1"], - ["time_diff.in0","affine_func$add_all__U504.out"], - ["affine_func$mul_d0__U499.in0","affine_func$coeff_0_U498.out"], - ["affine_func$mul_d1__U501.in0","affine_func$coeff_1_U500.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U499.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U501.in1"], + ["d_1_inc.in1","_U426.out"], + ["d_0_inc.in1","_U4261.out"], + ["cmp_time.in1","_U427.out"], + ["affine_func$mul_d0__U420.out","affine_func$add_all__U424.in0"], + ["affine_func$mul_d1__U422.out","affine_func$add_all__U424.in1"], + ["affine_func$add_all__U425.in0","affine_func$add_all__U424.out"], + ["affine_func$const_term_U423.out","affine_func$add_all__U425.in1"], + ["time_diff.in0","affine_func$add_all__U425.out"], + ["affine_func$mul_d0__U420.in0","affine_func$coeff_0_U419.out"], + ["affine_func$mul_d1__U422.in0","affine_func$coeff_1_U421.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U420.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U422.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6643,10 +6087,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U507$lut$lut.bit.in.2","d_0_am__U507$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U507$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U507$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U507$lut$lut.bit.out"], + ["d_0_am__U428$lut$lut.bit.in.2","d_0_am__U428$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U428$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U428$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U428$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6682,7 +6126,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U511":{ + "affine_controller__U431":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -6690,49 +6134,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U520":{ + "_U440":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5201":{ + "_U4401":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U521":{ + "_U441":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U518":{ + "affine_func$add_all__U438":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U519":{ + "affine_func$add_all__U439":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U513":{ + "affine_func$coeff_0_U433":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U515":{ + "affine_func$coeff_1_U435":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U517":{ + "affine_func$const_term_U437":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U514":{ + "affine_func$mul_d0__U434":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U516":{ + "affine_func$mul_d1__U436":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -6796,12 +6240,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U522$c0_lutcnst":{ + "d_0_am__U442$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U522$lut$lut":{ + "d_0_am__U442$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -6920,18 +6364,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U520.out"], - ["d_1_inc.in1","_U5201.out"], - ["cmp_time.in1","_U521.out"], - ["affine_func$mul_d0__U514.out","affine_func$add_all__U518.in0"], - ["affine_func$mul_d1__U516.out","affine_func$add_all__U518.in1"], - ["affine_func$add_all__U519.in0","affine_func$add_all__U518.out"], - ["affine_func$const_term_U517.out","affine_func$add_all__U519.in1"], - ["time_diff.in0","affine_func$add_all__U519.out"], - ["affine_func$mul_d0__U514.in0","affine_func$coeff_0_U513.out"], - ["affine_func$mul_d1__U516.in0","affine_func$coeff_1_U515.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U514.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U516.in1"], + ["d_0_inc.in1","_U440.out"], + ["d_1_inc.in1","_U4401.out"], + ["cmp_time.in1","_U441.out"], + ["affine_func$mul_d0__U434.out","affine_func$add_all__U438.in0"], + ["affine_func$mul_d1__U436.out","affine_func$add_all__U438.in1"], + ["affine_func$add_all__U439.in0","affine_func$add_all__U438.out"], + ["affine_func$const_term_U437.out","affine_func$add_all__U439.in1"], + ["time_diff.in0","affine_func$add_all__U439.out"], + ["affine_func$mul_d0__U434.in0","affine_func$coeff_0_U433.out"], + ["affine_func$mul_d1__U436.in0","affine_func$coeff_1_U435.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U434.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U436.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -6954,10 +6398,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U522$lut$lut.bit.in.2","d_0_am__U522$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U522$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U522$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U522$lut$lut.bit.out"], + ["d_0_am__U442$lut$lut.bit.in.2","d_0_am__U442$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U442$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U442$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U442$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6993,7 +6437,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U526":{ + "affine_controller__U445":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -7001,49 +6445,49 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U535":{ + "_U454":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5351":{ + "_U4541":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U536":{ + "_U455":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U533":{ + "affine_func$add_all__U452":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U534":{ + "affine_func$add_all__U453":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U528":{ + "affine_func$coeff_0_U447":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U530":{ + "affine_func$coeff_1_U449":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$const_term_U532":{ + "affine_func$const_term_U451":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000d240"]} }, - "affine_func$mul_d0__U529":{ + "affine_func$mul_d0__U448":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U531":{ + "affine_func$mul_d1__U450":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7107,12 +6551,12 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U537$c0_lutcnst":{ + "d_0_am__U456$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U537$lut$lut":{ + "d_0_am__U456$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7231,18 +6675,18 @@ } }, "connections":[ - ["d_0_inc.in1","_U535.out"], - ["d_1_inc.in1","_U5351.out"], - ["cmp_time.in1","_U536.out"], - ["affine_func$mul_d0__U529.out","affine_func$add_all__U533.in0"], - ["affine_func$mul_d1__U531.out","affine_func$add_all__U533.in1"], - ["affine_func$add_all__U534.in0","affine_func$add_all__U533.out"], - ["affine_func$const_term_U532.out","affine_func$add_all__U534.in1"], - ["time_diff.in0","affine_func$add_all__U534.out"], - ["affine_func$mul_d0__U529.in0","affine_func$coeff_0_U528.out"], - ["affine_func$mul_d1__U531.in0","affine_func$coeff_1_U530.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U529.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U531.in1"], + ["d_0_inc.in1","_U454.out"], + ["d_1_inc.in1","_U4541.out"], + ["cmp_time.in1","_U455.out"], + ["affine_func$mul_d0__U448.out","affine_func$add_all__U452.in0"], + ["affine_func$mul_d1__U450.out","affine_func$add_all__U452.in1"], + ["affine_func$add_all__U453.in0","affine_func$add_all__U452.out"], + ["affine_func$const_term_U451.out","affine_func$add_all__U453.in1"], + ["time_diff.in0","affine_func$add_all__U453.out"], + ["affine_func$mul_d0__U448.in0","affine_func$coeff_0_U447.out"], + ["affine_func$mul_d1__U450.in0","affine_func$coeff_1_U449.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U448.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U450.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -7265,10 +6709,10 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U537$lut$lut.bit.in.2","d_0_am__U537$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U537$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U537$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U537$lut$lut.bit.out"], + ["d_0_am__U456$lut$lut.bit.in.2","d_0_am__U456$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U456$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U456$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U456$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7304,7 +6748,7 @@ ["self.d.1","d_1_reg$reg0.out"] ] }, - "affine_controller__U541":{ + "affine_controller__U458":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -7312,139 +6756,139 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U565":{ + "_U482":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5651":{ + "_U4821":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5652":{ + "_U4822":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5653":{ + "_U4823":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5654":{ + "_U4824":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5655":{ + "_U4825":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U5656":{ + "_U4826":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U566":{ + "_U483":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U558":{ + "affine_func$add_all__U475":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U559":{ + "affine_func$add_all__U476":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U560":{ + "affine_func$add_all__U477":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U561":{ + "affine_func$add_all__U478":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U562":{ + "affine_func$add_all__U479":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U563":{ + "affine_func$add_all__U480":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U564":{ + "affine_func$add_all__U481":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U543":{ + "affine_func$coeff_0_U460":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U545":{ + "affine_func$coeff_1_U462":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "affine_func$coeff_2_U547":{ + "affine_func$coeff_2_U464":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "affine_func$coeff_3_U549":{ + "affine_func$coeff_3_U466":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "affine_func$coeff_4_U551":{ + "affine_func$coeff_4_U468":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000e0"]} }, - "affine_func$coeff_5_U553":{ + "affine_func$coeff_5_U470":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_6_U555":{ + "affine_func$coeff_6_U472":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U557":{ + "affine_func$const_term_U474":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00012d60"]} }, - "affine_func$mul_d0__U544":{ + "affine_func$mul_d0__U461":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U546":{ + "affine_func$mul_d1__U463":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U548":{ + "affine_func$mul_d2__U465":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U550":{ + "affine_func$mul_d3__U467":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U552":{ + "affine_func$mul_d4__U469":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U554":{ + "affine_func$mul_d5__U471":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d6__U556":{ + "affine_func$mul_d6__U473":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -7508,62 +6952,62 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U567$c0_lutcnst":{ + "d_0_am__U484$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U567$lut$lut":{ + "d_0_am__U484$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U568$c0_lutcnst":{ + "d_0_am__U485$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U568$lut$lut":{ + "d_0_am__U485$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U569$c0_lutcnst":{ + "d_0_am__U486$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U569$lut$lut":{ + "d_0_am__U486$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U570$c0_lutcnst":{ + "d_0_am__U487$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U570$lut$lut":{ + "d_0_am__U487$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U571$c0_lutcnst":{ + "d_0_am__U488$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U571$lut$lut":{ + "d_0_am__U488$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U572$c0_lutcnst":{ + "d_0_am__U489$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U572$lut$lut":{ + "d_0_am__U489$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7612,52 +7056,52 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U573$c0_lutcnst":{ + "d_1_am__U490$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U573$lut$lut":{ + "d_1_am__U490$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U574$c0_lutcnst":{ + "d_1_am__U491$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U574$lut$lut":{ + "d_1_am__U491$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U575$c0_lutcnst":{ + "d_1_am__U492$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U575$lut$lut":{ + "d_1_am__U492$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U576$c0_lutcnst":{ + "d_1_am__U493$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U576$lut$lut":{ + "d_1_am__U493$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U577$c0_lutcnst":{ + "d_1_am__U494$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U577$lut$lut":{ + "d_1_am__U494$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7706,42 +7150,42 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U578$c0_lutcnst":{ + "d_2_am__U495$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U578$lut$lut":{ + "d_2_am__U495$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U579$c0_lutcnst":{ + "d_2_am__U496$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U579$lut$lut":{ + "d_2_am__U496$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U580$c0_lutcnst":{ + "d_2_am__U497$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U580$lut$lut":{ + "d_2_am__U497$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_2_am__U581$c0_lutcnst":{ + "d_2_am__U498$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U581$lut$lut":{ + "d_2_am__U498$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7790,32 +7234,32 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_3_am__U582$c0_lutcnst":{ + "d_3_am__U499$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U582$lut$lut":{ + "d_3_am__U499$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U583$c0_lutcnst":{ + "d_3_am__U500$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U583$lut$lut":{ + "d_3_am__U500$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_am__U584$c0_lutcnst":{ + "d_3_am__U501$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U584$lut$lut":{ + "d_3_am__U501$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7864,22 +7308,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_4_am__U585$c0_lutcnst":{ + "d_4_am__U502$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U585$lut$lut":{ + "d_4_am__U502$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U586$c0_lutcnst":{ + "d_4_am__U503$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U586$lut$lut":{ + "d_4_am__U503$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -7928,12 +7372,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U587$c0_lutcnst":{ + "d_5_am__U504$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U587$lut$lut":{ + "d_5_am__U504$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -8077,43 +7521,43 @@ } }, "connections":[ - ["d_0_inc.in1","_U565.out"], - ["d_1_inc.in1","_U5651.out"], - ["d_2_inc.in1","_U5652.out"], - ["d_3_inc.in1","_U5653.out"], - ["d_4_inc.in1","_U5654.out"], - ["d_5_inc.in1","_U5655.out"], - ["d_6_inc.in1","_U5656.out"], - ["cmp_time.in1","_U566.out"], - ["affine_func$mul_d0__U544.out","affine_func$add_all__U558.in0"], - ["affine_func$mul_d1__U546.out","affine_func$add_all__U558.in1"], - ["affine_func$add_all__U559.in0","affine_func$add_all__U558.out"], - ["affine_func$mul_d2__U548.out","affine_func$add_all__U559.in1"], - ["affine_func$add_all__U560.in0","affine_func$add_all__U559.out"], - ["affine_func$mul_d3__U550.out","affine_func$add_all__U560.in1"], - ["affine_func$add_all__U561.in0","affine_func$add_all__U560.out"], - ["affine_func$mul_d4__U552.out","affine_func$add_all__U561.in1"], - ["affine_func$add_all__U562.in0","affine_func$add_all__U561.out"], - ["affine_func$mul_d5__U554.out","affine_func$add_all__U562.in1"], - ["affine_func$add_all__U563.in0","affine_func$add_all__U562.out"], - ["affine_func$mul_d6__U556.out","affine_func$add_all__U563.in1"], - ["affine_func$add_all__U564.in0","affine_func$add_all__U563.out"], - ["affine_func$const_term_U557.out","affine_func$add_all__U564.in1"], - ["time_diff.in0","affine_func$add_all__U564.out"], - ["affine_func$mul_d0__U544.in0","affine_func$coeff_0_U543.out"], - ["affine_func$mul_d1__U546.in0","affine_func$coeff_1_U545.out"], - ["affine_func$mul_d2__U548.in0","affine_func$coeff_2_U547.out"], - ["affine_func$mul_d3__U550.in0","affine_func$coeff_3_U549.out"], - ["affine_func$mul_d4__U552.in0","affine_func$coeff_4_U551.out"], - ["affine_func$mul_d5__U554.in0","affine_func$coeff_5_U553.out"], - ["affine_func$mul_d6__U556.in0","affine_func$coeff_6_U555.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U544.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U546.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U548.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U550.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U552.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U554.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U556.in1"], + ["d_0_inc.in1","_U482.out"], + ["d_1_inc.in1","_U4821.out"], + ["d_2_inc.in1","_U4822.out"], + ["d_3_inc.in1","_U4823.out"], + ["d_4_inc.in1","_U4824.out"], + ["d_5_inc.in1","_U4825.out"], + ["d_6_inc.in1","_U4826.out"], + ["cmp_time.in1","_U483.out"], + ["affine_func$mul_d0__U461.out","affine_func$add_all__U475.in0"], + ["affine_func$mul_d1__U463.out","affine_func$add_all__U475.in1"], + ["affine_func$add_all__U476.in0","affine_func$add_all__U475.out"], + ["affine_func$mul_d2__U465.out","affine_func$add_all__U476.in1"], + ["affine_func$add_all__U477.in0","affine_func$add_all__U476.out"], + ["affine_func$mul_d3__U467.out","affine_func$add_all__U477.in1"], + ["affine_func$add_all__U478.in0","affine_func$add_all__U477.out"], + ["affine_func$mul_d4__U469.out","affine_func$add_all__U478.in1"], + ["affine_func$add_all__U479.in0","affine_func$add_all__U478.out"], + ["affine_func$mul_d5__U471.out","affine_func$add_all__U479.in1"], + ["affine_func$add_all__U480.in0","affine_func$add_all__U479.out"], + ["affine_func$mul_d6__U473.out","affine_func$add_all__U480.in1"], + ["affine_func$add_all__U481.in0","affine_func$add_all__U480.out"], + ["affine_func$const_term_U474.out","affine_func$add_all__U481.in1"], + ["time_diff.in0","affine_func$add_all__U481.out"], + ["affine_func$mul_d0__U461.in0","affine_func$coeff_0_U460.out"], + ["affine_func$mul_d1__U463.in0","affine_func$coeff_1_U462.out"], + ["affine_func$mul_d2__U465.in0","affine_func$coeff_2_U464.out"], + ["affine_func$mul_d3__U467.in0","affine_func$coeff_3_U466.out"], + ["affine_func$mul_d4__U469.in0","affine_func$coeff_4_U468.out"], + ["affine_func$mul_d5__U471.in0","affine_func$coeff_5_U470.out"], + ["affine_func$mul_d6__U473.in0","affine_func$coeff_6_U472.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U461.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U463.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U465.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U467.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U469.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U471.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U473.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -8141,25 +7585,25 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U567$lut$lut.bit.in.2","d_0_am__U567$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U567$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U567$lut$lut.bit.in.1"], - ["d_0_am__U568$lut$lut.bit.in.0","d_0_am__U567$lut$lut.bit.out"], - ["d_0_am__U568$lut$lut.bit.in.2","d_0_am__U568$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U568$lut$lut.bit.in.1"], - ["d_0_am__U569$lut$lut.bit.in.0","d_0_am__U568$lut$lut.bit.out"], - ["d_0_am__U569$lut$lut.bit.in.2","d_0_am__U569$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U569$lut$lut.bit.in.1"], - ["d_0_am__U570$lut$lut.bit.in.0","d_0_am__U569$lut$lut.bit.out"], - ["d_0_am__U570$lut$lut.bit.in.2","d_0_am__U570$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U570$lut$lut.bit.in.1"], - ["d_0_am__U571$lut$lut.bit.in.0","d_0_am__U570$lut$lut.bit.out"], - ["d_0_am__U571$lut$lut.bit.in.2","d_0_am__U571$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U571$lut$lut.bit.in.1"], - ["d_0_am__U572$lut$lut.bit.in.0","d_0_am__U571$lut$lut.bit.out"], - ["d_0_am__U572$lut$lut.bit.in.2","d_0_am__U572$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U572$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U572$lut$lut.bit.out"], + ["d_0_am__U484$lut$lut.bit.in.2","d_0_am__U484$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U484$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U484$lut$lut.bit.in.1"], + ["d_0_am__U485$lut$lut.bit.in.0","d_0_am__U484$lut$lut.bit.out"], + ["d_0_am__U485$lut$lut.bit.in.2","d_0_am__U485$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U485$lut$lut.bit.in.1"], + ["d_0_am__U486$lut$lut.bit.in.0","d_0_am__U485$lut$lut.bit.out"], + ["d_0_am__U486$lut$lut.bit.in.2","d_0_am__U486$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U486$lut$lut.bit.in.1"], + ["d_0_am__U487$lut$lut.bit.in.0","d_0_am__U486$lut$lut.bit.out"], + ["d_0_am__U487$lut$lut.bit.in.2","d_0_am__U487$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U487$lut$lut.bit.in.1"], + ["d_0_am__U488$lut$lut.bit.in.0","d_0_am__U487$lut$lut.bit.out"], + ["d_0_am__U488$lut$lut.bit.in.2","d_0_am__U488$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U488$lut$lut.bit.in.1"], + ["d_0_am__U489$lut$lut.bit.in.0","d_0_am__U488$lut$lut.bit.out"], + ["d_0_am__U489$lut$lut.bit.in.2","d_0_am__U489$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U489$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U489$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8176,22 +7620,22 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U573$lut$lut.bit.in.2","d_1_am__U573$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U573$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U573$lut$lut.bit.in.1"], - ["d_1_am__U574$lut$lut.bit.in.0","d_1_am__U573$lut$lut.bit.out"], - ["d_1_am__U574$lut$lut.bit.in.2","d_1_am__U574$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U574$lut$lut.bit.in.1"], - ["d_1_am__U575$lut$lut.bit.in.0","d_1_am__U574$lut$lut.bit.out"], - ["d_1_am__U575$lut$lut.bit.in.2","d_1_am__U575$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U575$lut$lut.bit.in.1"], - ["d_1_am__U576$lut$lut.bit.in.0","d_1_am__U575$lut$lut.bit.out"], - ["d_1_am__U576$lut$lut.bit.in.2","d_1_am__U576$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U576$lut$lut.bit.in.1"], - ["d_1_am__U577$lut$lut.bit.in.0","d_1_am__U576$lut$lut.bit.out"], - ["d_1_am__U577$lut$lut.bit.in.2","d_1_am__U577$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U577$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U577$lut$lut.bit.out"], + ["d_1_am__U490$lut$lut.bit.in.2","d_1_am__U490$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U490$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U490$lut$lut.bit.in.1"], + ["d_1_am__U491$lut$lut.bit.in.0","d_1_am__U490$lut$lut.bit.out"], + ["d_1_am__U491$lut$lut.bit.in.2","d_1_am__U491$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U491$lut$lut.bit.in.1"], + ["d_1_am__U492$lut$lut.bit.in.0","d_1_am__U491$lut$lut.bit.out"], + ["d_1_am__U492$lut$lut.bit.in.2","d_1_am__U492$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U492$lut$lut.bit.in.1"], + ["d_1_am__U493$lut$lut.bit.in.0","d_1_am__U492$lut$lut.bit.out"], + ["d_1_am__U493$lut$lut.bit.in.2","d_1_am__U493$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U493$lut$lut.bit.in.1"], + ["d_1_am__U494$lut$lut.bit.in.0","d_1_am__U493$lut$lut.bit.out"], + ["d_1_am__U494$lut$lut.bit.in.2","d_1_am__U494$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U494$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U494$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -8208,19 +7652,19 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U578$lut$lut.bit.in.2","d_2_am__U578$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U578$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U578$lut$lut.bit.in.1"], - ["d_2_am__U579$lut$lut.bit.in.0","d_2_am__U578$lut$lut.bit.out"], - ["d_2_am__U579$lut$lut.bit.in.2","d_2_am__U579$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U579$lut$lut.bit.in.1"], - ["d_2_am__U580$lut$lut.bit.in.0","d_2_am__U579$lut$lut.bit.out"], - ["d_2_am__U580$lut$lut.bit.in.2","d_2_am__U580$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_2_am__U580$lut$lut.bit.in.1"], - ["d_2_am__U581$lut$lut.bit.in.0","d_2_am__U580$lut$lut.bit.out"], - ["d_2_am__U581$lut$lut.bit.in.2","d_2_am__U581$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U581$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U581$lut$lut.bit.out"], + ["d_2_am__U495$lut$lut.bit.in.2","d_2_am__U495$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U495$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U495$lut$lut.bit.in.1"], + ["d_2_am__U496$lut$lut.bit.in.0","d_2_am__U495$lut$lut.bit.out"], + ["d_2_am__U496$lut$lut.bit.in.2","d_2_am__U496$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U496$lut$lut.bit.in.1"], + ["d_2_am__U497$lut$lut.bit.in.0","d_2_am__U496$lut$lut.bit.out"], + ["d_2_am__U497$lut$lut.bit.in.2","d_2_am__U497$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U497$lut$lut.bit.in.1"], + ["d_2_am__U498$lut$lut.bit.in.0","d_2_am__U497$lut$lut.bit.out"], + ["d_2_am__U498$lut$lut.bit.in.2","d_2_am__U498$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U498$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U498$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -8237,16 +7681,16 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U582$lut$lut.bit.in.2","d_3_am__U582$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U582$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U582$lut$lut.bit.in.1"], - ["d_3_am__U583$lut$lut.bit.in.0","d_3_am__U582$lut$lut.bit.out"], - ["d_3_am__U583$lut$lut.bit.in.2","d_3_am__U583$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U583$lut$lut.bit.in.1"], - ["d_3_am__U584$lut$lut.bit.in.0","d_3_am__U583$lut$lut.bit.out"], - ["d_3_am__U584$lut$lut.bit.in.2","d_3_am__U584$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U584$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U584$lut$lut.bit.out"], + ["d_3_am__U499$lut$lut.bit.in.2","d_3_am__U499$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U499$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U499$lut$lut.bit.in.1"], + ["d_3_am__U500$lut$lut.bit.in.0","d_3_am__U499$lut$lut.bit.out"], + ["d_3_am__U500$lut$lut.bit.in.2","d_3_am__U500$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U500$lut$lut.bit.in.1"], + ["d_3_am__U501$lut$lut.bit.in.0","d_3_am__U500$lut$lut.bit.out"], + ["d_3_am__U501$lut$lut.bit.in.2","d_3_am__U501$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U501$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U501$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -8263,13 +7707,13 @@ ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U585$lut$lut.bit.in.2","d_4_am__U585$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U585$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U585$lut$lut.bit.in.1"], - ["d_4_am__U586$lut$lut.bit.in.0","d_4_am__U585$lut$lut.bit.out"], - ["d_4_am__U586$lut$lut.bit.in.2","d_4_am__U586$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U586$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U586$lut$lut.bit.out"], + ["d_4_am__U502$lut$lut.bit.in.2","d_4_am__U502$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U502$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U502$lut$lut.bit.in.1"], + ["d_4_am__U503$lut$lut.bit.in.0","d_4_am__U502$lut$lut.bit.out"], + ["d_4_am__U503$lut$lut.bit.in.2","d_4_am__U503$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U503$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U503$lut$lut.bit.out"], ["d_4_reg$reg0.out","d_4_at_max.in0"], ["d_4_max.out","d_4_at_max.in1"], ["d_4_next_value_at_max.sel","d_4_at_max.out"], @@ -8286,10 +7730,10 @@ ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], ["self.clk","d_4_reg$reg0.clk"], ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U587$lut$lut.bit.in.2","d_5_am__U587$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U587$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U587$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U587$lut$lut.bit.out"], + ["d_5_am__U504$lut$lut.bit.in.2","d_5_am__U504$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U504$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U504$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U504$lut$lut.bit.out"], ["d_5_reg$reg0.out","d_5_at_max.in0"], ["d_5_max.out","d_5_at_max.in1"], ["d_5_next_value_at_max.sel","d_5_at_max.out"], @@ -8325,7 +7769,7 @@ ["self.d.6","d_6_reg$reg0.out"] ] }, - "affine_controller__U56":{ + "affine_controller__U47":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -8333,848 +7777,1582 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U83":{ + "_U74":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U831":{ + "_U741":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U832":{ + "_U742":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U833":{ + "_U743":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U834":{ + "_U744":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U835":{ + "_U745":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U836":{ + "_U746":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U837":{ + "_U747":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U84":{ + "_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U75":{ + "affine_func$add_all__U66":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U76":{ + "affine_func$add_all__U67":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U77":{ + "affine_func$add_all__U68":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U78":{ + "affine_func$add_all__U69":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U79":{ + "affine_func$add_all__U70":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U80":{ + "affine_func$add_all__U71":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U81":{ + "affine_func$add_all__U72":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U82":{ + "affine_func$add_all__U73":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U58":{ + "affine_func$coeff_0_U49":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U60":{ + "affine_func$coeff_1_U51":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h0000fc00"]} }, - "affine_func$coeff_2_U62":{ + "affine_func$coeff_2_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00007e00"]} }, - "affine_func$coeff_3_U64":{ + "affine_func$coeff_3_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00003f00"]} }, - "affine_func$coeff_4_U66":{ + "affine_func$coeff_4_U57":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00001f80"]} }, - "affine_func$coeff_5_U68":{ + "affine_func$coeff_5_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h000000f0"]} }, - "affine_func$coeff_6_U70":{ + "affine_func$coeff_6_U61":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000008"]} }, - "affine_func$coeff_7_U72":{ + "affine_func$coeff_7_U63":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "affine_func$const_term_U65":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} + }, + "affine_func$mul_d0__U50":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d1__U52":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d2__U54":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d3__U56":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d4__U58":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d5__U60":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d6__U62":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "affine_func$mul_d7__U64":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "cycle_time$and$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$and$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "cycle_time$count$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$count$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + }, + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} + }, + "d_0_am__U76$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U76$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U77$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U77$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U78$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U78$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U79$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U79$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U80$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U80$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U81$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U81$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_am__U82$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_0_am__U82$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_0_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_0_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_1_am__U83$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U83$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U84$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U84$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U85$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U85$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U86$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U86$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U87$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U87$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_am__U88$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_1_am__U88$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U74":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000d23f"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U59":{ - "genref":"coreir.mul", + "d_1_next_value":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U61":{ - "genref":"coreir.mul", + "d_1_next_value_at_max":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U63":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_1_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d3__U65":{ - "genref":"coreir.mul", + "d_1_reg$clrMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d4__U67":{ - "genref":"coreir.mul", + "d_1_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d5__U69":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_1_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d6__U71":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_am__U89$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "affine_func$mul_d7__U73":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",32]} + "d_2_am__U89$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "d_2_am__U90$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$add":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "d_2_am__U90$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$and$c0_lutcnst":{ + "d_2_am__U91$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$and$lut$lut":{ + "d_2_am__U91$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$c0":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "d_2_am__U92$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "cycle_time$count$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "d_2_am__U92$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "cycle_time$count$enMux":{ - "genref":"coreir.mux", + "d_2_am__U93$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + }, + "d_2_am__U93$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "cycle_time$count$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "cycle_time$inc":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "cycle_time$max":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "cycle_time$resetOr$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cycle_time$resetOr$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "cycle_time$ult":{ - "genref":"coreir.ult", + "d_2_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_2_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_2_reg$enMux":{ + "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_am__U85$c0_lutcnst":{ + "d_2_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_3_am__U94$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U85$lut$lut":{ + "d_3_am__U94$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U86$c0_lutcnst":{ + "d_3_am__U95$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U86$lut$lut":{ + "d_3_am__U95$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U87$c0_lutcnst":{ + "d_3_am__U96$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U87$lut$lut":{ + "d_3_am__U96$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U88$c0_lutcnst":{ + "d_3_am__U97$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U88$lut$lut":{ + "d_3_am__U97$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U89$c0_lutcnst":{ + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_3_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_3_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_4_am__U100$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U89$lut$lut":{ + "d_4_am__U100$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U90$c0_lutcnst":{ + "d_4_am__U98$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U90$lut$lut":{ + "d_4_am__U98$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U91$c0_lutcnst":{ + "d_4_am__U99$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U91$lut$lut":{ + "d_4_am__U99$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_at_max":{ + "d_4_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_0_inc":{ + "d_4_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_0_max":{ + "d_4_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_0_min":{ + "d_4_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_next_value":{ + "d_4_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_next_value_at_max":{ + "d_4_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$c0":{ + "d_4_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_0_reg$clrMux":{ + "d_4_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$enMux":{ + "d_4_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_0_reg$reg0":{ + "d_4_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U92$c0_lutcnst":{ + "d_5_am__U101$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U92$lut$lut":{ + "d_5_am__U101$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U93$c0_lutcnst":{ + "d_5_am__U102$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U93$lut$lut":{ + "d_5_am__U102$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U94$c0_lutcnst":{ + "d_5_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_5_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_5_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + }, + "d_5_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_5_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} + }, + "d_5_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "d_6_am__U103$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U94$lut$lut":{ + "d_6_am__U103$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U95$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_6_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "d_6_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "d_6_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + }, + "d_6_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} + }, + "d_6_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U95$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_6_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U96$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_6_reg$c0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U96$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_6_reg$clrMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U97$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "d_6_reg$enMux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",32]} }, - "d_1_am__U97$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "d_6_reg$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_at_max":{ + "d_7_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_1_inc":{ + "d_7_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_1_max":{ + "d_7_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000007"]} }, - "d_1_min":{ + "d_7_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_next_value":{ + "d_7_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_next_value_at_max":{ + "d_7_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$c0":{ + "d_7_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_1_reg$clrMux":{ + "d_7_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$enMux":{ + "d_7_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_1_reg$reg0":{ + "d_7_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U100$c0_lutcnst":{ + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",32]} + }, + "true1_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U100$lut$lut":{ + "true2_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U101$c0_lutcnst":{ + "true3_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U101$lut$lut":{ + "true4_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U102$c0_lutcnst":{ + "true5_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U102$lut$lut":{ + "true6_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U98$c0_lutcnst":{ + "true7_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U98$lut$lut":{ + "true8_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U99$c0_lutcnst":{ + "true9_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "d_2_am__U99$lut$lut":{ + "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + } + }, + "connections":[ + ["d_0_inc.in1","_U74.out"], + ["d_1_inc.in1","_U741.out"], + ["d_2_inc.in1","_U742.out"], + ["d_3_inc.in1","_U743.out"], + ["d_4_inc.in1","_U744.out"], + ["d_5_inc.in1","_U745.out"], + ["d_6_inc.in1","_U746.out"], + ["d_7_inc.in1","_U747.out"], + ["cmp_time.in1","_U75.out"], + ["affine_func$mul_d0__U50.out","affine_func$add_all__U66.in0"], + ["affine_func$mul_d1__U52.out","affine_func$add_all__U66.in1"], + ["affine_func$add_all__U67.in0","affine_func$add_all__U66.out"], + ["affine_func$mul_d2__U54.out","affine_func$add_all__U67.in1"], + ["affine_func$add_all__U68.in0","affine_func$add_all__U67.out"], + ["affine_func$mul_d3__U56.out","affine_func$add_all__U68.in1"], + ["affine_func$add_all__U69.in0","affine_func$add_all__U68.out"], + ["affine_func$mul_d4__U58.out","affine_func$add_all__U69.in1"], + ["affine_func$add_all__U70.in0","affine_func$add_all__U69.out"], + ["affine_func$mul_d5__U60.out","affine_func$add_all__U70.in1"], + ["affine_func$add_all__U71.in0","affine_func$add_all__U70.out"], + ["affine_func$mul_d6__U62.out","affine_func$add_all__U71.in1"], + ["affine_func$add_all__U72.in0","affine_func$add_all__U71.out"], + ["affine_func$mul_d7__U64.out","affine_func$add_all__U72.in1"], + ["affine_func$add_all__U73.in0","affine_func$add_all__U72.out"], + ["affine_func$const_term_U65.out","affine_func$add_all__U73.in1"], + ["time_diff.in0","affine_func$add_all__U73.out"], + ["affine_func$mul_d0__U50.in0","affine_func$coeff_0_U49.out"], + ["affine_func$mul_d1__U52.in0","affine_func$coeff_1_U51.out"], + ["affine_func$mul_d2__U54.in0","affine_func$coeff_2_U53.out"], + ["affine_func$mul_d3__U56.in0","affine_func$coeff_3_U55.out"], + ["affine_func$mul_d4__U58.in0","affine_func$coeff_4_U57.out"], + ["affine_func$mul_d5__U60.in0","affine_func$coeff_5_U59.out"], + ["affine_func$mul_d6__U62.in0","affine_func$coeff_6_U61.out"], + ["affine_func$mul_d7__U64.in0","affine_func$coeff_7_U63.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U50.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U52.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U54.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U56.in1"], + ["d_4_reg$reg0.out","affine_func$mul_d4__U58.in1"], + ["d_5_reg$reg0.out","affine_func$mul_d5__U60.in1"], + ["d_6_reg$reg0.out","affine_func$mul_d6__U62.in1"], + ["d_7_reg$reg0.out","affine_func$mul_d7__U64.in1"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], + ["d_4_reg$enMux.sel","cmp_time.out"], + ["d_5_reg$enMux.sel","cmp_time.out"], + ["d_6_reg$enMux.sel","cmp_time.out"], + ["d_7_reg$enMux.sel","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["cycle_time$count$reg0.out","cycle_time$add.in0"], + ["cycle_time$inc.out","cycle_time$add.in1"], + ["cycle_time$count$enMux.in1","cycle_time$add.out"], + ["cycle_time$ult.in1","cycle_time$add.out"], + ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], + ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], + ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], + ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], + ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], + ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], + ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], + ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], + ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["time_diff.in1","cycle_time$count$reg0.out"], + ["cycle_time$ult.in0","cycle_time$max.out"], + ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], + ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], + ["d_0_am__U76$lut$lut.bit.in.2","d_0_am__U76$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U76$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U76$lut$lut.bit.in.1"], + ["d_0_am__U77$lut$lut.bit.in.0","d_0_am__U76$lut$lut.bit.out"], + ["d_0_am__U77$lut$lut.bit.in.2","d_0_am__U77$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U77$lut$lut.bit.in.1"], + ["d_0_am__U78$lut$lut.bit.in.0","d_0_am__U77$lut$lut.bit.out"], + ["d_0_am__U78$lut$lut.bit.in.2","d_0_am__U78$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U78$lut$lut.bit.in.1"], + ["d_0_am__U79$lut$lut.bit.in.0","d_0_am__U78$lut$lut.bit.out"], + ["d_0_am__U79$lut$lut.bit.in.2","d_0_am__U79$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_0_am__U79$lut$lut.bit.in.1"], + ["d_0_am__U80$lut$lut.bit.in.0","d_0_am__U79$lut$lut.bit.out"], + ["d_0_am__U80$lut$lut.bit.in.2","d_0_am__U80$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_0_am__U80$lut$lut.bit.in.1"], + ["d_0_am__U81$lut$lut.bit.in.0","d_0_am__U80$lut$lut.bit.out"], + ["d_0_am__U81$lut$lut.bit.in.2","d_0_am__U81$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_0_am__U81$lut$lut.bit.in.1"], + ["d_0_am__U82$lut$lut.bit.in.0","d_0_am__U81$lut$lut.bit.out"], + ["d_0_am__U82$lut$lut.bit.in.2","d_0_am__U82$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_0_am__U82$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U82$lut$lut.bit.out"], + ["d_0_reg$reg0.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg$reg0.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg$reg0.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg$enMux.in1","d_0_next_value.out"], + ["d_0_reg$clrMux.in1","d_0_reg$c0.out"], + ["d_0_reg$enMux.out","d_0_reg$clrMux.in0"], + ["d_0_reg$reg0.in","d_0_reg$clrMux.out"], + ["self.rst_n","d_0_reg$clrMux.sel"], + ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], + ["self.clk","d_0_reg$reg0.clk"], + ["self.d.0","d_0_reg$reg0.out"], + ["d_1_am__U83$lut$lut.bit.in.2","d_1_am__U83$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U83$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U83$lut$lut.bit.in.1"], + ["d_1_am__U84$lut$lut.bit.in.0","d_1_am__U83$lut$lut.bit.out"], + ["d_1_am__U84$lut$lut.bit.in.2","d_1_am__U84$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U84$lut$lut.bit.in.1"], + ["d_1_am__U85$lut$lut.bit.in.0","d_1_am__U84$lut$lut.bit.out"], + ["d_1_am__U85$lut$lut.bit.in.2","d_1_am__U85$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_1_am__U85$lut$lut.bit.in.1"], + ["d_1_am__U86$lut$lut.bit.in.0","d_1_am__U85$lut$lut.bit.out"], + ["d_1_am__U86$lut$lut.bit.in.2","d_1_am__U86$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_1_am__U86$lut$lut.bit.in.1"], + ["d_1_am__U87$lut$lut.bit.in.0","d_1_am__U86$lut$lut.bit.out"], + ["d_1_am__U87$lut$lut.bit.in.2","d_1_am__U87$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_1_am__U87$lut$lut.bit.in.1"], + ["d_1_am__U88$lut$lut.bit.in.0","d_1_am__U87$lut$lut.bit.out"], + ["d_1_am__U88$lut$lut.bit.in.2","d_1_am__U88$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_1_am__U88$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U88$lut$lut.bit.out"], + ["d_1_reg$reg0.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg$reg0.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg$reg0.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg$enMux.in1","d_1_next_value.out"], + ["d_1_reg$clrMux.in1","d_1_reg$c0.out"], + ["d_1_reg$enMux.out","d_1_reg$clrMux.in0"], + ["d_1_reg$reg0.in","d_1_reg$clrMux.out"], + ["self.rst_n","d_1_reg$clrMux.sel"], + ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], + ["self.clk","d_1_reg$reg0.clk"], + ["self.d.1","d_1_reg$reg0.out"], + ["d_2_am__U89$lut$lut.bit.in.2","d_2_am__U89$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U89$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U89$lut$lut.bit.in.1"], + ["d_2_am__U90$lut$lut.bit.in.0","d_2_am__U89$lut$lut.bit.out"], + ["d_2_am__U90$lut$lut.bit.in.2","d_2_am__U90$c0_lutcnst.bit.out"], + ["d_4_at_max.out","d_2_am__U90$lut$lut.bit.in.1"], + ["d_2_am__U91$lut$lut.bit.in.0","d_2_am__U90$lut$lut.bit.out"], + ["d_2_am__U91$lut$lut.bit.in.2","d_2_am__U91$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_2_am__U91$lut$lut.bit.in.1"], + ["d_2_am__U92$lut$lut.bit.in.0","d_2_am__U91$lut$lut.bit.out"], + ["d_2_am__U92$lut$lut.bit.in.2","d_2_am__U92$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_2_am__U92$lut$lut.bit.in.1"], + ["d_2_am__U93$lut$lut.bit.in.0","d_2_am__U92$lut$lut.bit.out"], + ["d_2_am__U93$lut$lut.bit.in.2","d_2_am__U93$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_2_am__U93$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U93$lut$lut.bit.out"], + ["d_2_reg$reg0.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg$reg0.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg$reg0.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg$enMux.in1","d_2_next_value.out"], + ["d_2_reg$clrMux.in1","d_2_reg$c0.out"], + ["d_2_reg$enMux.out","d_2_reg$clrMux.in0"], + ["d_2_reg$reg0.in","d_2_reg$clrMux.out"], + ["self.rst_n","d_2_reg$clrMux.sel"], + ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], + ["self.clk","d_2_reg$reg0.clk"], + ["self.d.2","d_2_reg$reg0.out"], + ["d_3_am__U94$lut$lut.bit.in.2","d_3_am__U94$c0_lutcnst.bit.out"], + ["true4_lutcnst.bit.out","d_3_am__U94$lut$lut.bit.in.0"], + ["d_4_at_max.out","d_3_am__U94$lut$lut.bit.in.1"], + ["d_3_am__U95$lut$lut.bit.in.0","d_3_am__U94$lut$lut.bit.out"], + ["d_3_am__U95$lut$lut.bit.in.2","d_3_am__U95$c0_lutcnst.bit.out"], + ["d_5_at_max.out","d_3_am__U95$lut$lut.bit.in.1"], + ["d_3_am__U96$lut$lut.bit.in.0","d_3_am__U95$lut$lut.bit.out"], + ["d_3_am__U96$lut$lut.bit.in.2","d_3_am__U96$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_3_am__U96$lut$lut.bit.in.1"], + ["d_3_am__U97$lut$lut.bit.in.0","d_3_am__U96$lut$lut.bit.out"], + ["d_3_am__U97$lut$lut.bit.in.2","d_3_am__U97$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_3_am__U97$lut$lut.bit.in.1"], + ["d_3_next_value.sel","d_3_am__U97$lut$lut.bit.out"], + ["d_3_reg$reg0.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg$reg0.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg$reg0.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], + ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], + ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], + ["self.rst_n","d_3_reg$clrMux.sel"], + ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], + ["self.clk","d_3_reg$reg0.clk"], + ["self.d.3","d_3_reg$reg0.out"], + ["d_4_am__U100$lut$lut.bit.in.2","d_4_am__U100$c0_lutcnst.bit.out"], + ["d_4_am__U99$lut$lut.bit.out","d_4_am__U100$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_4_am__U100$lut$lut.bit.in.1"], + ["d_4_next_value.sel","d_4_am__U100$lut$lut.bit.out"], + ["d_4_am__U98$lut$lut.bit.in.2","d_4_am__U98$c0_lutcnst.bit.out"], + ["true5_lutcnst.bit.out","d_4_am__U98$lut$lut.bit.in.0"], + ["d_5_at_max.out","d_4_am__U98$lut$lut.bit.in.1"], + ["d_4_am__U99$lut$lut.bit.in.0","d_4_am__U98$lut$lut.bit.out"], + ["d_4_am__U99$lut$lut.bit.in.2","d_4_am__U99$c0_lutcnst.bit.out"], + ["d_6_at_max.out","d_4_am__U99$lut$lut.bit.in.1"], + ["d_4_reg$reg0.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg$reg0.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg$reg0.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg$enMux.in1","d_4_next_value.out"], + ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], + ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], + ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], + ["self.rst_n","d_4_reg$clrMux.sel"], + ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], + ["self.clk","d_4_reg$reg0.clk"], + ["self.d.4","d_4_reg$reg0.out"], + ["d_5_am__U101$lut$lut.bit.in.2","d_5_am__U101$c0_lutcnst.bit.out"], + ["true6_lutcnst.bit.out","d_5_am__U101$lut$lut.bit.in.0"], + ["d_6_at_max.out","d_5_am__U101$lut$lut.bit.in.1"], + ["d_5_am__U102$lut$lut.bit.in.0","d_5_am__U101$lut$lut.bit.out"], + ["d_5_am__U102$lut$lut.bit.in.2","d_5_am__U102$c0_lutcnst.bit.out"], + ["d_7_at_max.out","d_5_am__U102$lut$lut.bit.in.1"], + ["d_5_next_value.sel","d_5_am__U102$lut$lut.bit.out"], + ["d_5_reg$reg0.out","d_5_at_max.in0"], + ["d_5_max.out","d_5_at_max.in1"], + ["d_5_next_value_at_max.sel","d_5_at_max.out"], + ["d_5_reg$reg0.out","d_5_inc.in0"], + ["d_5_next_value_at_max.in0","d_5_inc.out"], + ["d_5_next_value_at_max.in1","d_5_min.out"], + ["d_5_reg$reg0.out","d_5_next_value.in0"], + ["d_5_next_value_at_max.out","d_5_next_value.in1"], + ["d_5_reg$enMux.in1","d_5_next_value.out"], + ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], + ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], + ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], + ["self.rst_n","d_5_reg$clrMux.sel"], + ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], + ["self.clk","d_5_reg$reg0.clk"], + ["self.d.5","d_5_reg$reg0.out"], + ["d_6_am__U103$lut$lut.bit.in.2","d_6_am__U103$c0_lutcnst.bit.out"], + ["true7_lutcnst.bit.out","d_6_am__U103$lut$lut.bit.in.0"], + ["d_7_at_max.out","d_6_am__U103$lut$lut.bit.in.1"], + ["d_6_next_value.sel","d_6_am__U103$lut$lut.bit.out"], + ["d_6_reg$reg0.out","d_6_at_max.in0"], + ["d_6_max.out","d_6_at_max.in1"], + ["d_6_next_value_at_max.sel","d_6_at_max.out"], + ["d_6_reg$reg0.out","d_6_inc.in0"], + ["d_6_next_value_at_max.in0","d_6_inc.out"], + ["d_6_next_value_at_max.in1","d_6_min.out"], + ["d_6_reg$reg0.out","d_6_next_value.in0"], + ["d_6_next_value_at_max.out","d_6_next_value.in1"], + ["d_6_reg$enMux.in1","d_6_next_value.out"], + ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], + ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], + ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], + ["self.rst_n","d_6_reg$clrMux.sel"], + ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], + ["self.clk","d_6_reg$reg0.clk"], + ["self.d.6","d_6_reg$reg0.out"], + ["d_7_reg$reg0.out","d_7_at_max.in0"], + ["d_7_max.out","d_7_at_max.in1"], + ["d_7_next_value_at_max.sel","d_7_at_max.out"], + ["d_7_reg$reg0.out","d_7_inc.in0"], + ["d_7_next_value_at_max.in0","d_7_inc.out"], + ["d_7_next_value_at_max.in1","d_7_min.out"], + ["d_7_reg$reg0.out","d_7_next_value.in0"], + ["d_7_next_value_at_max.out","d_7_next_value.in1"], + ["d_7_reg$enMux.in1","d_7_next_value.out"], + ["true_lutcnst.bit.out","d_7_next_value.sel"], + ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], + ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], + ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], + ["self.rst_n","d_7_reg$clrMux.sel"], + ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], + ["self.clk","d_7_reg$reg0.clk"], + ["self.d.7","d_7_reg$reg0.out"] + ] + }, + "affine_controller__U530":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",4,["Array",32,"Bit"]]], + ["rst_n","BitIn"] + ]], + "instances":{ + "_U545":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} + "_U5451":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} + "_U5452":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_max":{ + "_U5453":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_2_min":{ + "_U546":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_next_value":{ - "genref":"coreir.mux", + "affine_func$add_all__U541":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", + "affine_func$add_all__U542":{ + "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_2_reg$c0":{ + "affine_func$add_all__U543":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$add_all__U544":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} + }, + "affine_func$coeff_0_U532":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_2_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func$coeff_1_U534":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "d_2_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "affine_func$coeff_2_U536":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "d_2_reg$reg0":{ - "genref":"coreir.reg", + "affine_func$coeff_3_U538":{ + "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_3_am__U103$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$const_term_U540":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} }, - "d_3_am__U103$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "affine_func$mul_d0__U533":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U104$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$mul_d1__U535":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U104$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "affine_func$mul_d2__U537":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U105$c0_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} + "affine_func$mul_d3__U539":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",32]} }, - "d_3_am__U105$lut$lut":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",32]} + }, + "cycle_time$add":{ + "genref":"coreir.add", + "genargs":{"width":["Int",32]} }, - "d_3_am__U106$c0_lutcnst":{ + "cycle_time$and$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_am__U106$lut$lut":{ + "cycle_time$and$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",32]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",32]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} - }, - "d_3_min":{ + "cycle_time$count$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_3_next_value":{ + "cycle_time$count$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_next_value_at_max":{ + "cycle_time$count$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_3_reg$c0":{ + "cycle_time$count$reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",32]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + }, + "cycle_time$inc":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000000"]} + "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "d_3_reg$clrMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "cycle_time$max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",32]}, + "modargs":{"value":[["BitVector",32],"32'h7fffffff"]} }, - "d_3_reg$enMux":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",32]} + "cycle_time$resetOr$c0_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_3_reg$reg0":{ - "genref":"coreir.reg", - "genargs":{"width":["Int",32]}, - "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} + "cycle_time$resetOr$lut$lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'hee"]} + }, + "cycle_time$ult":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",32]} }, - "d_4_am__U107$c0_lutcnst":{ + "d_0_am__U547$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U107$lut$lut":{ + "d_0_am__U547$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U108$c0_lutcnst":{ + "d_0_am__U548$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U108$lut$lut":{ + "d_0_am__U548$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_am__U109$c0_lutcnst":{ + "d_0_am__U549$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_4_am__U109$lut$lut":{ + "d_0_am__U549$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_4_at_max":{ + "d_0_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_4_inc":{ + "d_0_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_4_max":{ + "d_0_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000001"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_min":{ + "d_0_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_next_value":{ + "d_0_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_next_value_at_max":{ + "d_0_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$c0":{ + "d_0_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_4_reg$clrMux":{ + "d_0_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$enMux":{ + "d_0_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_4_reg$reg0":{ + "d_0_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_5_am__U110$c0_lutcnst":{ + "d_1_am__U550$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U110$lut$lut":{ + "d_1_am__U550$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_5_am__U111$c0_lutcnst":{ + "d_1_am__U551$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_5_am__U111$lut$lut":{ + "d_1_am__U551$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_5_at_max":{ + "d_1_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_5_inc":{ + "d_1_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_5_max":{ + "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + "modargs":{"value":[["BitVector",32],"32'h00000037"]} }, - "d_5_min":{ + "d_1_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_next_value":{ + "d_1_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_next_value_at_max":{ + "d_1_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$c0":{ + "d_1_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_5_reg$clrMux":{ + "d_1_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$enMux":{ + "d_1_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_5_reg$reg0":{ + "d_1_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_6_am__U112$c0_lutcnst":{ + "d_2_am__U552$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_6_am__U112$lut$lut":{ + "d_2_am__U552$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_6_at_max":{ + "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_6_inc":{ + "d_2_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_6_max":{ + "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0000001d"]} + "modargs":{"value":[["BitVector",32],"32'h00000037"]} }, - "d_6_min":{ + "d_2_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_next_value":{ + "d_2_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_next_value_at_max":{ + "d_2_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$c0":{ + "d_2_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_6_reg$clrMux":{ + "d_2_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$enMux":{ + "d_2_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_6_reg$reg0":{ + "d_2_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_7_at_max":{ + "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",32]} }, - "d_7_inc":{ + "d_3_inc":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "d_7_max":{ + "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000007"]} + "modargs":{"value":[["BitVector",32],"32'h0000000f"]} }, - "d_7_min":{ + "d_3_min":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_next_value":{ + "d_3_next_value":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_next_value_at_max":{ + "d_3_next_value_at_max":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$c0":{ + "d_3_reg$c0":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "d_7_reg$clrMux":{ + "d_3_reg$clrMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$enMux":{ + "d_3_reg$enMux":{ "genref":"coreir.mux", "genargs":{"width":["Int",32]} }, - "d_7_reg$reg0":{ + "d_3_reg$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} @@ -9208,26 +9386,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} }, - "true6_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true7_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true8_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, - "true9_lutcnst":{ - "genref":"cgralib.PE", - "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, - "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} - }, "true_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -9235,57 +9393,33 @@ } }, "connections":[ - ["d_0_inc.in1","_U83.out"], - ["d_1_inc.in1","_U831.out"], - ["d_2_inc.in1","_U832.out"], - ["d_3_inc.in1","_U833.out"], - ["d_4_inc.in1","_U834.out"], - ["d_5_inc.in1","_U835.out"], - ["d_6_inc.in1","_U836.out"], - ["d_7_inc.in1","_U837.out"], - ["cmp_time.in1","_U84.out"], - ["affine_func$mul_d0__U59.out","affine_func$add_all__U75.in0"], - ["affine_func$mul_d1__U61.out","affine_func$add_all__U75.in1"], - ["affine_func$add_all__U76.in0","affine_func$add_all__U75.out"], - ["affine_func$mul_d2__U63.out","affine_func$add_all__U76.in1"], - ["affine_func$add_all__U77.in0","affine_func$add_all__U76.out"], - ["affine_func$mul_d3__U65.out","affine_func$add_all__U77.in1"], - ["affine_func$add_all__U78.in0","affine_func$add_all__U77.out"], - ["affine_func$mul_d4__U67.out","affine_func$add_all__U78.in1"], - ["affine_func$add_all__U79.in0","affine_func$add_all__U78.out"], - ["affine_func$mul_d5__U69.out","affine_func$add_all__U79.in1"], - ["affine_func$add_all__U80.in0","affine_func$add_all__U79.out"], - ["affine_func$mul_d6__U71.out","affine_func$add_all__U80.in1"], - ["affine_func$add_all__U81.in0","affine_func$add_all__U80.out"], - ["affine_func$mul_d7__U73.out","affine_func$add_all__U81.in1"], - ["affine_func$add_all__U82.in0","affine_func$add_all__U81.out"], - ["affine_func$const_term_U74.out","affine_func$add_all__U82.in1"], - ["time_diff.in0","affine_func$add_all__U82.out"], - ["affine_func$mul_d0__U59.in0","affine_func$coeff_0_U58.out"], - ["affine_func$mul_d1__U61.in0","affine_func$coeff_1_U60.out"], - ["affine_func$mul_d2__U63.in0","affine_func$coeff_2_U62.out"], - ["affine_func$mul_d3__U65.in0","affine_func$coeff_3_U64.out"], - ["affine_func$mul_d4__U67.in0","affine_func$coeff_4_U66.out"], - ["affine_func$mul_d5__U69.in0","affine_func$coeff_5_U68.out"], - ["affine_func$mul_d6__U71.in0","affine_func$coeff_6_U70.out"], - ["affine_func$mul_d7__U73.in0","affine_func$coeff_7_U72.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U59.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U61.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U63.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U65.in1"], - ["d_4_reg$reg0.out","affine_func$mul_d4__U67.in1"], - ["d_5_reg$reg0.out","affine_func$mul_d5__U69.in1"], - ["d_6_reg$reg0.out","affine_func$mul_d6__U71.in1"], - ["d_7_reg$reg0.out","affine_func$mul_d7__U73.in1"], + ["d_0_inc.in1","_U545.out"], + ["d_1_inc.in1","_U5451.out"], + ["d_2_inc.in1","_U5452.out"], + ["d_3_inc.in1","_U5453.out"], + ["cmp_time.in1","_U546.out"], + ["affine_func$mul_d0__U533.out","affine_func$add_all__U541.in0"], + ["affine_func$mul_d1__U535.out","affine_func$add_all__U541.in1"], + ["affine_func$add_all__U542.in0","affine_func$add_all__U541.out"], + ["affine_func$mul_d2__U537.out","affine_func$add_all__U542.in1"], + ["affine_func$add_all__U543.in0","affine_func$add_all__U542.out"], + ["affine_func$mul_d3__U539.out","affine_func$add_all__U543.in1"], + ["affine_func$add_all__U544.in0","affine_func$add_all__U543.out"], + ["affine_func$const_term_U540.out","affine_func$add_all__U544.in1"], + ["time_diff.in0","affine_func$add_all__U544.out"], + ["affine_func$mul_d0__U533.in0","affine_func$coeff_0_U532.out"], + ["affine_func$mul_d1__U535.in0","affine_func$coeff_1_U534.out"], + ["affine_func$mul_d2__U537.in0","affine_func$coeff_2_U536.out"], + ["affine_func$mul_d3__U539.in0","affine_func$coeff_3_U538.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U533.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U535.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U537.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U539.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], - ["d_1_reg$enMux.sel","cmp_time.out"], - ["d_2_reg$enMux.sel","cmp_time.out"], - ["d_3_reg$enMux.sel","cmp_time.out"], - ["d_4_reg$enMux.sel","cmp_time.out"], - ["d_5_reg$enMux.sel","cmp_time.out"], - ["d_6_reg$enMux.sel","cmp_time.out"], - ["d_7_reg$enMux.sel","cmp_time.out"], + ["d_1_reg$enMux.sel","cmp_time.out"], + ["d_2_reg$enMux.sel","cmp_time.out"], + ["d_3_reg$enMux.sel","cmp_time.out"], ["self.valid","cmp_time.out"], ["cycle_time$count$reg0.out","cycle_time$add.in0"], ["cycle_time$inc.out","cycle_time$add.in1"], @@ -9293,40 +9427,28 @@ ["cycle_time$ult.in1","cycle_time$add.out"], ["cycle_time$and$lut$lut.bit.in.2","cycle_time$and$c0_lutcnst.bit.out"], ["cycle_time$ult.out","cycle_time$and$lut$lut.bit.in.0"], - ["true9_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], + ["true5_lutcnst.bit.out","cycle_time$and$lut$lut.bit.in.1"], ["cycle_time$resetOr$lut$lut.bit.in.0","cycle_time$and$lut$lut.bit.out"], ["cycle_time$count$clrMux.in1","cycle_time$count$c0.out"], ["cycle_time$count$enMux.out","cycle_time$count$clrMux.in0"], ["cycle_time$count$reg0.in","cycle_time$count$clrMux.out"], ["cycle_time$resetOr$lut$lut.bit.out","cycle_time$count$clrMux.sel"], ["cycle_time$count$reg0.out","cycle_time$count$enMux.in0"], - ["true8_lutcnst.bit.out","cycle_time$count$enMux.sel"], + ["true4_lutcnst.bit.out","cycle_time$count$enMux.sel"], ["time_diff.in1","cycle_time$count$reg0.out"], ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U85$lut$lut.bit.in.2","d_0_am__U85$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U85$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U85$lut$lut.bit.in.1"], - ["d_0_am__U86$lut$lut.bit.in.0","d_0_am__U85$lut$lut.bit.out"], - ["d_0_am__U86$lut$lut.bit.in.2","d_0_am__U86$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U86$lut$lut.bit.in.1"], - ["d_0_am__U87$lut$lut.bit.in.0","d_0_am__U86$lut$lut.bit.out"], - ["d_0_am__U87$lut$lut.bit.in.2","d_0_am__U87$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U87$lut$lut.bit.in.1"], - ["d_0_am__U88$lut$lut.bit.in.0","d_0_am__U87$lut$lut.bit.out"], - ["d_0_am__U88$lut$lut.bit.in.2","d_0_am__U88$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_0_am__U88$lut$lut.bit.in.1"], - ["d_0_am__U89$lut$lut.bit.in.0","d_0_am__U88$lut$lut.bit.out"], - ["d_0_am__U89$lut$lut.bit.in.2","d_0_am__U89$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_0_am__U89$lut$lut.bit.in.1"], - ["d_0_am__U90$lut$lut.bit.in.0","d_0_am__U89$lut$lut.bit.out"], - ["d_0_am__U90$lut$lut.bit.in.2","d_0_am__U90$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_0_am__U90$lut$lut.bit.in.1"], - ["d_0_am__U91$lut$lut.bit.in.0","d_0_am__U90$lut$lut.bit.out"], - ["d_0_am__U91$lut$lut.bit.in.2","d_0_am__U91$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_0_am__U91$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U91$lut$lut.bit.out"], + ["d_0_am__U547$lut$lut.bit.in.2","d_0_am__U547$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U547$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U547$lut$lut.bit.in.1"], + ["d_0_am__U548$lut$lut.bit.in.0","d_0_am__U547$lut$lut.bit.out"], + ["d_0_am__U548$lut$lut.bit.in.2","d_0_am__U548$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U548$lut$lut.bit.in.1"], + ["d_0_am__U549$lut$lut.bit.in.0","d_0_am__U548$lut$lut.bit.out"], + ["d_0_am__U549$lut$lut.bit.in.2","d_0_am__U549$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U549$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U549$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -9343,25 +9465,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U92$lut$lut.bit.in.2","d_1_am__U92$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U92$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U92$lut$lut.bit.in.1"], - ["d_1_am__U93$lut$lut.bit.in.0","d_1_am__U92$lut$lut.bit.out"], - ["d_1_am__U93$lut$lut.bit.in.2","d_1_am__U93$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U93$lut$lut.bit.in.1"], - ["d_1_am__U94$lut$lut.bit.in.0","d_1_am__U93$lut$lut.bit.out"], - ["d_1_am__U94$lut$lut.bit.in.2","d_1_am__U94$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_1_am__U94$lut$lut.bit.in.1"], - ["d_1_am__U95$lut$lut.bit.in.0","d_1_am__U94$lut$lut.bit.out"], - ["d_1_am__U95$lut$lut.bit.in.2","d_1_am__U95$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_1_am__U95$lut$lut.bit.in.1"], - ["d_1_am__U96$lut$lut.bit.in.0","d_1_am__U95$lut$lut.bit.out"], - ["d_1_am__U96$lut$lut.bit.in.2","d_1_am__U96$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_1_am__U96$lut$lut.bit.in.1"], - ["d_1_am__U97$lut$lut.bit.in.0","d_1_am__U96$lut$lut.bit.out"], - ["d_1_am__U97$lut$lut.bit.in.2","d_1_am__U97$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_1_am__U97$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U97$lut$lut.bit.out"], + ["d_1_am__U550$lut$lut.bit.in.2","d_1_am__U550$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U550$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U550$lut$lut.bit.in.1"], + ["d_1_am__U551$lut$lut.bit.in.0","d_1_am__U550$lut$lut.bit.out"], + ["d_1_am__U551$lut$lut.bit.in.2","d_1_am__U551$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U551$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U551$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -9378,22 +9488,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U100$lut$lut.bit.in.2","d_2_am__U100$c0_lutcnst.bit.out"], - ["d_2_am__U99$lut$lut.bit.out","d_2_am__U100$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_2_am__U100$lut$lut.bit.in.1"], - ["d_2_am__U101$lut$lut.bit.in.0","d_2_am__U100$lut$lut.bit.out"], - ["d_2_am__U101$lut$lut.bit.in.2","d_2_am__U101$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_2_am__U101$lut$lut.bit.in.1"], - ["d_2_am__U102$lut$lut.bit.in.0","d_2_am__U101$lut$lut.bit.out"], - ["d_2_am__U102$lut$lut.bit.in.2","d_2_am__U102$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_2_am__U102$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U102$lut$lut.bit.out"], - ["d_2_am__U98$lut$lut.bit.in.2","d_2_am__U98$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U98$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U98$lut$lut.bit.in.1"], - ["d_2_am__U99$lut$lut.bit.in.0","d_2_am__U98$lut$lut.bit.out"], - ["d_2_am__U99$lut$lut.bit.in.2","d_2_am__U99$c0_lutcnst.bit.out"], - ["d_4_at_max.out","d_2_am__U99$lut$lut.bit.in.1"], + ["d_2_am__U552$lut$lut.bit.in.2","d_2_am__U552$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U552$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U552$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U552$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -9410,19 +9508,6 @@ ["d_2_reg$reg0.out","d_2_reg$enMux.in0"], ["self.clk","d_2_reg$reg0.clk"], ["self.d.2","d_2_reg$reg0.out"], - ["d_3_am__U103$lut$lut.bit.in.2","d_3_am__U103$c0_lutcnst.bit.out"], - ["true4_lutcnst.bit.out","d_3_am__U103$lut$lut.bit.in.0"], - ["d_4_at_max.out","d_3_am__U103$lut$lut.bit.in.1"], - ["d_3_am__U104$lut$lut.bit.in.0","d_3_am__U103$lut$lut.bit.out"], - ["d_3_am__U104$lut$lut.bit.in.2","d_3_am__U104$c0_lutcnst.bit.out"], - ["d_5_at_max.out","d_3_am__U104$lut$lut.bit.in.1"], - ["d_3_am__U105$lut$lut.bit.in.0","d_3_am__U104$lut$lut.bit.out"], - ["d_3_am__U105$lut$lut.bit.in.2","d_3_am__U105$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_3_am__U105$lut$lut.bit.in.1"], - ["d_3_am__U106$lut$lut.bit.in.0","d_3_am__U105$lut$lut.bit.out"], - ["d_3_am__U106$lut$lut.bit.in.2","d_3_am__U106$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_3_am__U106$lut$lut.bit.in.1"], - ["d_3_next_value.sel","d_3_am__U106$lut$lut.bit.out"], ["d_3_reg$reg0.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -9432,102 +9517,17 @@ ["d_3_reg$reg0.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg$enMux.in1","d_3_next_value.out"], + ["true_lutcnst.bit.out","d_3_next_value.sel"], ["d_3_reg$clrMux.in1","d_3_reg$c0.out"], ["d_3_reg$enMux.out","d_3_reg$clrMux.in0"], ["d_3_reg$reg0.in","d_3_reg$clrMux.out"], ["self.rst_n","d_3_reg$clrMux.sel"], ["d_3_reg$reg0.out","d_3_reg$enMux.in0"], ["self.clk","d_3_reg$reg0.clk"], - ["self.d.3","d_3_reg$reg0.out"], - ["d_4_am__U107$lut$lut.bit.in.2","d_4_am__U107$c0_lutcnst.bit.out"], - ["true5_lutcnst.bit.out","d_4_am__U107$lut$lut.bit.in.0"], - ["d_5_at_max.out","d_4_am__U107$lut$lut.bit.in.1"], - ["d_4_am__U108$lut$lut.bit.in.0","d_4_am__U107$lut$lut.bit.out"], - ["d_4_am__U108$lut$lut.bit.in.2","d_4_am__U108$c0_lutcnst.bit.out"], - ["d_6_at_max.out","d_4_am__U108$lut$lut.bit.in.1"], - ["d_4_am__U109$lut$lut.bit.in.0","d_4_am__U108$lut$lut.bit.out"], - ["d_4_am__U109$lut$lut.bit.in.2","d_4_am__U109$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_4_am__U109$lut$lut.bit.in.1"], - ["d_4_next_value.sel","d_4_am__U109$lut$lut.bit.out"], - ["d_4_reg$reg0.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg$reg0.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg$reg0.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg$enMux.in1","d_4_next_value.out"], - ["d_4_reg$clrMux.in1","d_4_reg$c0.out"], - ["d_4_reg$enMux.out","d_4_reg$clrMux.in0"], - ["d_4_reg$reg0.in","d_4_reg$clrMux.out"], - ["self.rst_n","d_4_reg$clrMux.sel"], - ["d_4_reg$reg0.out","d_4_reg$enMux.in0"], - ["self.clk","d_4_reg$reg0.clk"], - ["self.d.4","d_4_reg$reg0.out"], - ["d_5_am__U110$lut$lut.bit.in.2","d_5_am__U110$c0_lutcnst.bit.out"], - ["true6_lutcnst.bit.out","d_5_am__U110$lut$lut.bit.in.0"], - ["d_6_at_max.out","d_5_am__U110$lut$lut.bit.in.1"], - ["d_5_am__U111$lut$lut.bit.in.0","d_5_am__U110$lut$lut.bit.out"], - ["d_5_am__U111$lut$lut.bit.in.2","d_5_am__U111$c0_lutcnst.bit.out"], - ["d_7_at_max.out","d_5_am__U111$lut$lut.bit.in.1"], - ["d_5_next_value.sel","d_5_am__U111$lut$lut.bit.out"], - ["d_5_reg$reg0.out","d_5_at_max.in0"], - ["d_5_max.out","d_5_at_max.in1"], - ["d_5_next_value_at_max.sel","d_5_at_max.out"], - ["d_5_reg$reg0.out","d_5_inc.in0"], - ["d_5_next_value_at_max.in0","d_5_inc.out"], - ["d_5_next_value_at_max.in1","d_5_min.out"], - ["d_5_reg$reg0.out","d_5_next_value.in0"], - ["d_5_next_value_at_max.out","d_5_next_value.in1"], - ["d_5_reg$enMux.in1","d_5_next_value.out"], - ["d_5_reg$clrMux.in1","d_5_reg$c0.out"], - ["d_5_reg$enMux.out","d_5_reg$clrMux.in0"], - ["d_5_reg$reg0.in","d_5_reg$clrMux.out"], - ["self.rst_n","d_5_reg$clrMux.sel"], - ["d_5_reg$reg0.out","d_5_reg$enMux.in0"], - ["self.clk","d_5_reg$reg0.clk"], - ["self.d.5","d_5_reg$reg0.out"], - ["d_6_am__U112$lut$lut.bit.in.2","d_6_am__U112$c0_lutcnst.bit.out"], - ["true7_lutcnst.bit.out","d_6_am__U112$lut$lut.bit.in.0"], - ["d_7_at_max.out","d_6_am__U112$lut$lut.bit.in.1"], - ["d_6_next_value.sel","d_6_am__U112$lut$lut.bit.out"], - ["d_6_reg$reg0.out","d_6_at_max.in0"], - ["d_6_max.out","d_6_at_max.in1"], - ["d_6_next_value_at_max.sel","d_6_at_max.out"], - ["d_6_reg$reg0.out","d_6_inc.in0"], - ["d_6_next_value_at_max.in0","d_6_inc.out"], - ["d_6_next_value_at_max.in1","d_6_min.out"], - ["d_6_reg$reg0.out","d_6_next_value.in0"], - ["d_6_next_value_at_max.out","d_6_next_value.in1"], - ["d_6_reg$enMux.in1","d_6_next_value.out"], - ["d_6_reg$clrMux.in1","d_6_reg$c0.out"], - ["d_6_reg$enMux.out","d_6_reg$clrMux.in0"], - ["d_6_reg$reg0.in","d_6_reg$clrMux.out"], - ["self.rst_n","d_6_reg$clrMux.sel"], - ["d_6_reg$reg0.out","d_6_reg$enMux.in0"], - ["self.clk","d_6_reg$reg0.clk"], - ["self.d.6","d_6_reg$reg0.out"], - ["d_7_reg$reg0.out","d_7_at_max.in0"], - ["d_7_max.out","d_7_at_max.in1"], - ["d_7_next_value_at_max.sel","d_7_at_max.out"], - ["d_7_reg$reg0.out","d_7_inc.in0"], - ["d_7_next_value_at_max.in0","d_7_inc.out"], - ["d_7_next_value_at_max.in1","d_7_min.out"], - ["d_7_reg$reg0.out","d_7_next_value.in0"], - ["d_7_next_value_at_max.out","d_7_next_value.in1"], - ["d_7_reg$enMux.in1","d_7_next_value.out"], - ["true_lutcnst.bit.out","d_7_next_value.sel"], - ["d_7_reg$clrMux.in1","d_7_reg$c0.out"], - ["d_7_reg$enMux.out","d_7_reg$clrMux.in0"], - ["d_7_reg$reg0.in","d_7_reg$clrMux.out"], - ["self.rst_n","d_7_reg$clrMux.sel"], - ["d_7_reg$reg0.out","d_7_reg$enMux.in0"], - ["self.clk","d_7_reg$reg0.clk"], - ["self.d.7","d_7_reg$reg0.out"] + ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U613":{ + "affine_controller__U570":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -9535,85 +9535,85 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U628":{ + "_U585":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6281":{ + "_U5851":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6282":{ + "_U5852":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6283":{ + "_U5853":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U629":{ + "_U586":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U624":{ + "affine_func$add_all__U581":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U625":{ + "affine_func$add_all__U582":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U626":{ + "affine_func$add_all__U583":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U627":{ + "affine_func$add_all__U584":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U615":{ + "affine_func$coeff_0_U572":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U617":{ + "affine_func$coeff_1_U574":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000380"]} }, - "affine_func$coeff_2_U619":{ + "affine_func$coeff_2_U576":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U621":{ + "affine_func$coeff_3_U578":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U623":{ + "affine_func$const_term_U580":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0002fedf"]} + "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} }, - "affine_func$mul_d0__U616":{ + "affine_func$mul_d0__U573":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U618":{ + "affine_func$mul_d1__U575":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U620":{ + "affine_func$mul_d2__U577":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U622":{ + "affine_func$mul_d3__U579":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -9677,32 +9677,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U630$c0_lutcnst":{ + "d_0_am__U587$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U630$lut$lut":{ + "d_0_am__U587$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U631$c0_lutcnst":{ + "d_0_am__U588$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U631$lut$lut":{ + "d_0_am__U588$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U632$c0_lutcnst":{ + "d_0_am__U589$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U632$lut$lut":{ + "d_0_am__U589$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9751,22 +9751,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U633$c0_lutcnst":{ + "d_1_am__U590$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U633$lut$lut":{ + "d_1_am__U590$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U634$c0_lutcnst":{ + "d_1_am__U591$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U634$lut$lut":{ + "d_1_am__U591$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9815,12 +9815,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U635$c0_lutcnst":{ + "d_2_am__U592$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U635$lut$lut":{ + "d_2_am__U592$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -9949,28 +9949,28 @@ } }, "connections":[ - ["d_0_inc.in1","_U628.out"], - ["d_1_inc.in1","_U6281.out"], - ["d_2_inc.in1","_U6282.out"], - ["d_3_inc.in1","_U6283.out"], - ["cmp_time.in1","_U629.out"], - ["affine_func$mul_d0__U616.out","affine_func$add_all__U624.in0"], - ["affine_func$mul_d1__U618.out","affine_func$add_all__U624.in1"], - ["affine_func$add_all__U625.in0","affine_func$add_all__U624.out"], - ["affine_func$mul_d2__U620.out","affine_func$add_all__U625.in1"], - ["affine_func$add_all__U626.in0","affine_func$add_all__U625.out"], - ["affine_func$mul_d3__U622.out","affine_func$add_all__U626.in1"], - ["affine_func$add_all__U627.in0","affine_func$add_all__U626.out"], - ["affine_func$const_term_U623.out","affine_func$add_all__U627.in1"], - ["time_diff.in0","affine_func$add_all__U627.out"], - ["affine_func$mul_d0__U616.in0","affine_func$coeff_0_U615.out"], - ["affine_func$mul_d1__U618.in0","affine_func$coeff_1_U617.out"], - ["affine_func$mul_d2__U620.in0","affine_func$coeff_2_U619.out"], - ["affine_func$mul_d3__U622.in0","affine_func$coeff_3_U621.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U616.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U618.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U620.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U622.in1"], + ["d_0_inc.in1","_U585.out"], + ["d_1_inc.in1","_U5851.out"], + ["d_2_inc.in1","_U5852.out"], + ["d_3_inc.in1","_U5853.out"], + ["cmp_time.in1","_U586.out"], + ["affine_func$mul_d0__U573.out","affine_func$add_all__U581.in0"], + ["affine_func$mul_d1__U575.out","affine_func$add_all__U581.in1"], + ["affine_func$add_all__U582.in0","affine_func$add_all__U581.out"], + ["affine_func$mul_d2__U577.out","affine_func$add_all__U582.in1"], + ["affine_func$add_all__U583.in0","affine_func$add_all__U582.out"], + ["affine_func$mul_d3__U579.out","affine_func$add_all__U583.in1"], + ["affine_func$add_all__U584.in0","affine_func$add_all__U583.out"], + ["affine_func$const_term_U580.out","affine_func$add_all__U584.in1"], + ["time_diff.in0","affine_func$add_all__U584.out"], + ["affine_func$mul_d0__U573.in0","affine_func$coeff_0_U572.out"], + ["affine_func$mul_d1__U575.in0","affine_func$coeff_1_U574.out"], + ["affine_func$mul_d2__U577.in0","affine_func$coeff_2_U576.out"], + ["affine_func$mul_d3__U579.in0","affine_func$coeff_3_U578.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U573.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U575.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U577.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U579.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -9995,16 +9995,16 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U630$lut$lut.bit.in.2","d_0_am__U630$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U630$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U630$lut$lut.bit.in.1"], - ["d_0_am__U631$lut$lut.bit.in.0","d_0_am__U630$lut$lut.bit.out"], - ["d_0_am__U631$lut$lut.bit.in.2","d_0_am__U631$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U631$lut$lut.bit.in.1"], - ["d_0_am__U632$lut$lut.bit.in.0","d_0_am__U631$lut$lut.bit.out"], - ["d_0_am__U632$lut$lut.bit.in.2","d_0_am__U632$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U632$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U632$lut$lut.bit.out"], + ["d_0_am__U587$lut$lut.bit.in.2","d_0_am__U587$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U587$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U587$lut$lut.bit.in.1"], + ["d_0_am__U588$lut$lut.bit.in.0","d_0_am__U587$lut$lut.bit.out"], + ["d_0_am__U588$lut$lut.bit.in.2","d_0_am__U588$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U588$lut$lut.bit.in.1"], + ["d_0_am__U589$lut$lut.bit.in.0","d_0_am__U588$lut$lut.bit.out"], + ["d_0_am__U589$lut$lut.bit.in.2","d_0_am__U589$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U589$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U589$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10021,13 +10021,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U633$lut$lut.bit.in.2","d_1_am__U633$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U633$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U633$lut$lut.bit.in.1"], - ["d_1_am__U634$lut$lut.bit.in.0","d_1_am__U633$lut$lut.bit.out"], - ["d_1_am__U634$lut$lut.bit.in.2","d_1_am__U634$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U634$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U634$lut$lut.bit.out"], + ["d_1_am__U590$lut$lut.bit.in.2","d_1_am__U590$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U590$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U590$lut$lut.bit.in.1"], + ["d_1_am__U591$lut$lut.bit.in.0","d_1_am__U590$lut$lut.bit.out"], + ["d_1_am__U591$lut$lut.bit.in.2","d_1_am__U591$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U591$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U591$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10044,10 +10044,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U635$lut$lut.bit.in.2","d_2_am__U635$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U635$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U635$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U635$lut$lut.bit.out"], + ["d_2_am__U592$lut$lut.bit.in.2","d_2_am__U592$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U592$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U592$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U592$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -10083,7 +10083,7 @@ ["self.d.3","d_3_reg$reg0.out"] ] }, - "affine_controller__U653":{ + "affine_controller__U8":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], @@ -10091,85 +10091,85 @@ ["rst_n","BitIn"] ]], "instances":{ - "_U668":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6681":{ + "_U231":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6682":{ + "_U232":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U6683":{ + "_U233":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "_U669":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$add_all__U664":{ + "affine_func$add_all__U19":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U665":{ + "affine_func$add_all__U20":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U666":{ + "affine_func$add_all__U21":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$add_all__U667":{ + "affine_func$add_all__U22":{ "genref":"coreir.add", "genargs":{"width":["Int",32]} }, - "affine_func$coeff_0_U655":{ + "affine_func$coeff_0_U10":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$coeff_1_U657":{ + "affine_func$coeff_1_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000380"]} + "modargs":{"value":[["BitVector",32],"32'h000003a0"]} }, - "affine_func$coeff_2_U659":{ + "affine_func$coeff_2_U14":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000010"]} }, - "affine_func$coeff_3_U661":{ + "affine_func$coeff_3_U16":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, "modargs":{"value":[["BitVector",32],"32'h00000001"]} }, - "affine_func$const_term_U663":{ + "affine_func$const_term_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h0002fee0"]} + "modargs":{"value":[["BitVector",32],"32'h00000000"]} }, - "affine_func$mul_d0__U656":{ + "affine_func$mul_d0__U11":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d1__U658":{ + "affine_func$mul_d1__U13":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d2__U660":{ + "affine_func$mul_d2__U15":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, - "affine_func$mul_d3__U662":{ + "affine_func$mul_d3__U17":{ "genref":"coreir.mul", "genargs":{"width":["Int",32]} }, @@ -10233,32 +10233,32 @@ "genref":"coreir.ult", "genargs":{"width":["Int",32]} }, - "d_0_am__U670$c0_lutcnst":{ + "d_0_am__U25$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U670$lut$lut":{ + "d_0_am__U25$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U671$c0_lutcnst":{ + "d_0_am__U26$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U671$lut$lut":{ + "d_0_am__U26$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_0_am__U672$c0_lutcnst":{ + "d_0_am__U27$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_0_am__U672$lut$lut":{ + "d_0_am__U27$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10307,22 +10307,22 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_1_am__U673$c0_lutcnst":{ + "d_1_am__U28$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U673$lut$lut":{ + "d_1_am__U28$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} }, - "d_1_am__U674$c0_lutcnst":{ + "d_1_am__U29$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_1_am__U674$lut$lut":{ + "d_1_am__U29$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10338,7 +10338,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000037"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_1_min":{ "genref":"coreir.const", @@ -10371,12 +10371,12 @@ "genargs":{"width":["Int",32]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",32],"32'h00000000"]} }, - "d_2_am__U675$c0_lutcnst":{ + "d_2_am__U30$c0_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h00"]} }, - "d_2_am__U675$lut$lut":{ + "d_2_am__U30$lut$lut":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h88"]} @@ -10392,7 +10392,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",32]}, - "modargs":{"value":[["BitVector",32],"32'h00000037"]} + "modargs":{"value":[["BitVector",32],"32'h00000039"]} }, "d_2_min":{ "genref":"coreir.const", @@ -10505,28 +10505,28 @@ } }, "connections":[ - ["d_0_inc.in1","_U668.out"], - ["d_1_inc.in1","_U6681.out"], - ["d_2_inc.in1","_U6682.out"], - ["d_3_inc.in1","_U6683.out"], - ["cmp_time.in1","_U669.out"], - ["affine_func$mul_d0__U656.out","affine_func$add_all__U664.in0"], - ["affine_func$mul_d1__U658.out","affine_func$add_all__U664.in1"], - ["affine_func$add_all__U665.in0","affine_func$add_all__U664.out"], - ["affine_func$mul_d2__U660.out","affine_func$add_all__U665.in1"], - ["affine_func$add_all__U666.in0","affine_func$add_all__U665.out"], - ["affine_func$mul_d3__U662.out","affine_func$add_all__U666.in1"], - ["affine_func$add_all__U667.in0","affine_func$add_all__U666.out"], - ["affine_func$const_term_U663.out","affine_func$add_all__U667.in1"], - ["time_diff.in0","affine_func$add_all__U667.out"], - ["affine_func$mul_d0__U656.in0","affine_func$coeff_0_U655.out"], - ["affine_func$mul_d1__U658.in0","affine_func$coeff_1_U657.out"], - ["affine_func$mul_d2__U660.in0","affine_func$coeff_2_U659.out"], - ["affine_func$mul_d3__U662.in0","affine_func$coeff_3_U661.out"], - ["d_0_reg$reg0.out","affine_func$mul_d0__U656.in1"], - ["d_1_reg$reg0.out","affine_func$mul_d1__U658.in1"], - ["d_2_reg$reg0.out","affine_func$mul_d2__U660.in1"], - ["d_3_reg$reg0.out","affine_func$mul_d3__U662.in1"], + ["d_0_inc.in1","_U23.out"], + ["d_1_inc.in1","_U231.out"], + ["d_2_inc.in1","_U232.out"], + ["d_3_inc.in1","_U233.out"], + ["cmp_time.in1","_U24.out"], + ["affine_func$mul_d0__U11.out","affine_func$add_all__U19.in0"], + ["affine_func$mul_d1__U13.out","affine_func$add_all__U19.in1"], + ["affine_func$add_all__U20.in0","affine_func$add_all__U19.out"], + ["affine_func$mul_d2__U15.out","affine_func$add_all__U20.in1"], + ["affine_func$add_all__U21.in0","affine_func$add_all__U20.out"], + ["affine_func$mul_d3__U17.out","affine_func$add_all__U21.in1"], + ["affine_func$add_all__U22.in0","affine_func$add_all__U21.out"], + ["affine_func$const_term_U18.out","affine_func$add_all__U22.in1"], + ["time_diff.in0","affine_func$add_all__U22.out"], + ["affine_func$mul_d0__U11.in0","affine_func$coeff_0_U10.out"], + ["affine_func$mul_d1__U13.in0","affine_func$coeff_1_U12.out"], + ["affine_func$mul_d2__U15.in0","affine_func$coeff_2_U14.out"], + ["affine_func$mul_d3__U17.in0","affine_func$coeff_3_U16.out"], + ["d_0_reg$reg0.out","affine_func$mul_d0__U11.in1"], + ["d_1_reg$reg0.out","affine_func$mul_d1__U13.in1"], + ["d_2_reg$reg0.out","affine_func$mul_d2__U15.in1"], + ["d_3_reg$reg0.out","affine_func$mul_d3__U17.in1"], ["time_diff.out","cmp_time.in0"], ["d_0_reg$enMux.sel","cmp_time.out"], ["d_1_reg$enMux.sel","cmp_time.out"], @@ -10551,16 +10551,16 @@ ["cycle_time$ult.in0","cycle_time$max.out"], ["cycle_time$resetOr$lut$lut.bit.in.2","cycle_time$resetOr$c0_lutcnst.bit.out"], ["self.rst_n","cycle_time$resetOr$lut$lut.bit.in.1"], - ["d_0_am__U670$lut$lut.bit.in.2","d_0_am__U670$c0_lutcnst.bit.out"], - ["true1_lutcnst.bit.out","d_0_am__U670$lut$lut.bit.in.0"], - ["d_1_at_max.out","d_0_am__U670$lut$lut.bit.in.1"], - ["d_0_am__U671$lut$lut.bit.in.0","d_0_am__U670$lut$lut.bit.out"], - ["d_0_am__U671$lut$lut.bit.in.2","d_0_am__U671$c0_lutcnst.bit.out"], - ["d_2_at_max.out","d_0_am__U671$lut$lut.bit.in.1"], - ["d_0_am__U672$lut$lut.bit.in.0","d_0_am__U671$lut$lut.bit.out"], - ["d_0_am__U672$lut$lut.bit.in.2","d_0_am__U672$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_0_am__U672$lut$lut.bit.in.1"], - ["d_0_next_value.sel","d_0_am__U672$lut$lut.bit.out"], + ["d_0_am__U25$lut$lut.bit.in.2","d_0_am__U25$c0_lutcnst.bit.out"], + ["true1_lutcnst.bit.out","d_0_am__U25$lut$lut.bit.in.0"], + ["d_1_at_max.out","d_0_am__U25$lut$lut.bit.in.1"], + ["d_0_am__U26$lut$lut.bit.in.0","d_0_am__U25$lut$lut.bit.out"], + ["d_0_am__U26$lut$lut.bit.in.2","d_0_am__U26$c0_lutcnst.bit.out"], + ["d_2_at_max.out","d_0_am__U26$lut$lut.bit.in.1"], + ["d_0_am__U27$lut$lut.bit.in.0","d_0_am__U26$lut$lut.bit.out"], + ["d_0_am__U27$lut$lut.bit.in.2","d_0_am__U27$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_0_am__U27$lut$lut.bit.in.1"], + ["d_0_next_value.sel","d_0_am__U27$lut$lut.bit.out"], ["d_0_reg$reg0.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -10577,13 +10577,13 @@ ["d_0_reg$reg0.out","d_0_reg$enMux.in0"], ["self.clk","d_0_reg$reg0.clk"], ["self.d.0","d_0_reg$reg0.out"], - ["d_1_am__U673$lut$lut.bit.in.2","d_1_am__U673$c0_lutcnst.bit.out"], - ["true2_lutcnst.bit.out","d_1_am__U673$lut$lut.bit.in.0"], - ["d_2_at_max.out","d_1_am__U673$lut$lut.bit.in.1"], - ["d_1_am__U674$lut$lut.bit.in.0","d_1_am__U673$lut$lut.bit.out"], - ["d_1_am__U674$lut$lut.bit.in.2","d_1_am__U674$c0_lutcnst.bit.out"], - ["d_3_at_max.out","d_1_am__U674$lut$lut.bit.in.1"], - ["d_1_next_value.sel","d_1_am__U674$lut$lut.bit.out"], + ["d_1_am__U28$lut$lut.bit.in.2","d_1_am__U28$c0_lutcnst.bit.out"], + ["true2_lutcnst.bit.out","d_1_am__U28$lut$lut.bit.in.0"], + ["d_2_at_max.out","d_1_am__U28$lut$lut.bit.in.1"], + ["d_1_am__U29$lut$lut.bit.in.0","d_1_am__U28$lut$lut.bit.out"], + ["d_1_am__U29$lut$lut.bit.in.2","d_1_am__U29$c0_lutcnst.bit.out"], + ["d_3_at_max.out","d_1_am__U29$lut$lut.bit.in.1"], + ["d_1_next_value.sel","d_1_am__U29$lut$lut.bit.out"], ["d_1_reg$reg0.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10600,10 +10600,10 @@ ["d_1_reg$reg0.out","d_1_reg$enMux.in0"], ["self.clk","d_1_reg$reg0.clk"], ["self.d.1","d_1_reg$reg0.out"], - ["d_2_am__U675$lut$lut.bit.in.2","d_2_am__U675$c0_lutcnst.bit.out"], - ["true3_lutcnst.bit.out","d_2_am__U675$lut$lut.bit.in.0"], - ["d_3_at_max.out","d_2_am__U675$lut$lut.bit.in.1"], - ["d_2_next_value.sel","d_2_am__U675$lut$lut.bit.out"], + ["d_2_am__U30$lut$lut.bit.in.2","d_2_am__U30$c0_lutcnst.bit.out"], + ["true3_lutcnst.bit.out","d_2_am__U30$lut$lut.bit.in.0"], + ["d_3_at_max.out","d_2_am__U30$lut$lut.bit.in.1"], + ["d_2_next_value.sel","d_2_am__U30$lut$lut.bit.out"], ["d_2_reg$reg0.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -10712,26 +10712,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U695":{ + "PE_init_U612":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U693":{ + "_U610":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U694":{ + "_U611":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U693.out","PE_init_U695.data.in.0"], - ["_U694.out","PE_init_U695.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U695.data.out"], + ["_U610.out","PE_init_U612.data.in.0"], + ["_U611.out","PE_init_U612.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","PE_init_U612.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -10743,26 +10743,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U698":{ + "PE_init_U615":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U696":{ + "_U613":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U697":{ + "_U614":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U696.out","PE_init_U698.data.in.0"], - ["_U697.out","PE_init_U698.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U698.data.out"], + ["_U613.out","PE_init_U615.data.in.0"], + ["_U614.out","PE_init_U615.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","PE_init_U615.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11548,26 +11548,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U701":{ + "PE_init_U618":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U699":{ + "_U616":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U700":{ + "_U617":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U699.out","PE_init_U701.data.in.0"], - ["_U700.out","PE_init_U701.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U701.data.out"], + ["_U616.out","PE_init_U618.data.in.0"], + ["_U617.out","PE_init_U618.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","PE_init_U618.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11579,26 +11579,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U704":{ + "PE_init_U621":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U702":{ + "_U619":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U703":{ + "_U620":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U702.out","PE_init_U704.data.in.0"], - ["_U703.out","PE_init_U704.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U704.data.out"], + ["_U619.out","PE_init_U621.data.in.0"], + ["_U620.out","PE_init_U621.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_3_write.0","PE_init_U621.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11610,26 +11610,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U707":{ + "PE_init_U624":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U705":{ + "_U622":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U706":{ + "_U623":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U705.out","PE_init_U707.data.in.0"], - ["_U706.out","PE_init_U707.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U707.data.out"], + ["_U622.out","PE_init_U624.data.in.0"], + ["_U623.out","PE_init_U624.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_4_write.0","PE_init_U624.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11641,26 +11641,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U710":{ + "PE_init_U627":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U708":{ + "_U625":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U709":{ + "_U626":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U708.out","PE_init_U710.data.in.0"], - ["_U709.out","PE_init_U710.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U710.data.out"], + ["_U625.out","PE_init_U627.data.in.0"], + ["_U626.out","PE_init_U627.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_5_write.0","PE_init_U627.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11672,26 +11672,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U713":{ + "PE_init_U630":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U711":{ + "_U628":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U712":{ + "_U629":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U711.out","PE_init_U713.data.in.0"], - ["_U712.out","PE_init_U713.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U713.data.out"], + ["_U628.out","PE_init_U630.data.in.0"], + ["_U629.out","PE_init_U630.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_6_write.0","PE_init_U630.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -11703,26 +11703,26 @@ ["output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U716":{ + "PE_init_U633":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U714":{ + "_U631":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U715":{ + "_U632":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U714.out","PE_init_U716.data.in.0"], - ["_U715.out","PE_init_U716.data.in.1"], - ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U716.data.out"], + ["_U631.out","PE_init_U633.data.in.0"], + ["_U632.out","PE_init_U633.data.in.1"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_7_write.0","PE_init_U633.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -12047,26 +12047,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U719":{ + "PE_init_U636":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U717":{ + "_U634":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U718":{ + "_U635":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U717.out","PE_init_U719.data.in.0"], - ["_U718.out","PE_init_U719.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U719.data.out"] + ["_U634.out","PE_init_U636.data.in.0"], + ["_U635.out","PE_init_U636.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U636.data.out"] ] }, "hcompute_output_cgra_stencil_1":{ @@ -12074,26 +12074,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U722":{ + "PE_init_U639":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U720":{ + "_U637":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U721":{ + "_U638":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U720.out","PE_init_U722.data.in.0"], - ["_U721.out","PE_init_U722.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U722.data.out"] + ["_U637.out","PE_init_U639.data.in.0"], + ["_U638.out","PE_init_U639.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U639.data.out"] ] }, "hcompute_output_cgra_stencil_10":{ @@ -12851,26 +12851,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U725":{ + "PE_init_U642":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U723":{ + "_U640":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U724":{ + "_U641":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U723.out","PE_init_U725.data.in.0"], - ["_U724.out","PE_init_U725.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U725.data.out"] + ["_U640.out","PE_init_U642.data.in.0"], + ["_U641.out","PE_init_U642.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U642.data.out"] ] }, "hcompute_output_cgra_stencil_3":{ @@ -12878,26 +12878,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U728":{ + "PE_init_U645":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U726":{ + "_U643":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U727":{ + "_U644":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U726.out","PE_init_U728.data.in.0"], - ["_U727.out","PE_init_U728.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U728.data.out"] + ["_U643.out","PE_init_U645.data.in.0"], + ["_U644.out","PE_init_U645.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U645.data.out"] ] }, "hcompute_output_cgra_stencil_4":{ @@ -12905,26 +12905,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U731":{ + "PE_init_U648":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U729":{ + "_U646":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U730":{ + "_U647":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U729.out","PE_init_U731.data.in.0"], - ["_U730.out","PE_init_U731.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U731.data.out"] + ["_U646.out","PE_init_U648.data.in.0"], + ["_U647.out","PE_init_U648.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U648.data.out"] ] }, "hcompute_output_cgra_stencil_5":{ @@ -12932,26 +12932,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U734":{ + "PE_init_U651":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U732":{ + "_U649":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U733":{ + "_U650":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U732.out","PE_init_U734.data.in.0"], - ["_U733.out","PE_init_U734.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U734.data.out"] + ["_U649.out","PE_init_U651.data.in.0"], + ["_U650.out","PE_init_U651.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U651.data.out"] ] }, "hcompute_output_cgra_stencil_6":{ @@ -12959,26 +12959,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U737":{ + "PE_init_U654":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U735":{ + "_U652":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U736":{ + "_U653":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U735.out","PE_init_U737.data.in.0"], - ["_U736.out","PE_init_U737.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U737.data.out"] + ["_U652.out","PE_init_U654.data.in.0"], + ["_U653.out","PE_init_U654.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U654.data.out"] ] }, "hcompute_output_cgra_stencil_7":{ @@ -12986,26 +12986,26 @@ ["out_output_cgra_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U740":{ + "PE_init_U657":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U738":{ + "_U655":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U739":{ + "_U656":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U738.out","PE_init_U740.data.in.0"], - ["_U739.out","PE_init_U740.data.in.1"], - ["self.out_output_cgra_stencil","PE_init_U740.data.out"] + ["_U655.out","PE_init_U657.data.in.0"], + ["_U656.out","PE_init_U657.data.in.1"], + ["self.out_output_cgra_stencil","PE_init_U657.data.out"] ] }, "hcompute_output_cgra_stencil_8":{ @@ -13292,38 +13292,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -13331,7 +13299,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -13341,7 +13309,7 @@ }, "ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -13351,7 +13319,7 @@ }, "ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -13361,7 +13329,7 @@ }, "ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -13371,7 +13339,7 @@ }, "ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -13381,7 +13349,7 @@ }, "ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -13391,7 +13359,7 @@ }, "ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -13401,7 +13369,7 @@ }, "ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -13543,262 +13511,6 @@ ["op_hcompute_output_cgra_stencil_9_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -13806,8 +13518,8 @@ }, "ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13816,8 +13528,8 @@ }, "ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13826,8 +13538,8 @@ }, "ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13836,8 +13548,8 @@ }, "ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13846,8 +13558,8 @@ }, "ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13856,8 +13568,8 @@ }, "ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13866,8 +13578,8 @@ }, "ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13876,8 +13588,8 @@ }, "ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13886,8 +13598,8 @@ }, "ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13896,8 +13608,8 @@ }, "ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13906,8 +13618,8 @@ }, "ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13916,8 +13628,8 @@ }, "ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13926,8 +13638,8 @@ }, "ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13936,8 +13648,8 @@ }, "ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13946,8 +13658,8 @@ }, "ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13956,8 +13668,8 @@ }, "ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13966,8 +13678,8 @@ }, "ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13976,8 +13688,8 @@ }, "ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13986,8 +13698,8 @@ }, "ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -13996,8 +13708,8 @@ }, "ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14006,8 +13718,8 @@ }, "ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14016,8 +13728,8 @@ }, "ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14026,8 +13738,8 @@ }, "ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14036,8 +13748,8 @@ }, "ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14046,8 +13758,8 @@ }, "ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14056,8 +13768,8 @@ }, "ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14066,8 +13778,8 @@ }, "ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14076,8 +13788,8 @@ }, "ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14086,8 +13798,8 @@ }, "ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14096,8 +13808,8 @@ }, "ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14106,8 +13818,8 @@ }, "ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14116,8 +13828,8 @@ }, "ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14126,8 +13838,8 @@ }, "ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14136,8 +13848,8 @@ }, "ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14146,8 +13858,8 @@ }, "ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14156,8 +13868,8 @@ }, "ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14166,8 +13878,8 @@ }, "ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14176,8 +13888,8 @@ }, "ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14186,8 +13898,8 @@ }, "ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14196,8 +13908,8 @@ }, "ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14206,8 +13918,8 @@ }, "ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14216,8 +13928,8 @@ }, "ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14226,8 +13938,8 @@ }, "ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14236,8 +13948,8 @@ }, "ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14246,8 +13958,8 @@ }, "ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14256,8 +13968,8 @@ }, "ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14266,8 +13978,8 @@ }, "ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14276,8 +13988,8 @@ }, "ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14286,8 +13998,8 @@ }, "ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14296,8 +14008,8 @@ }, "ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14306,8 +14018,8 @@ }, "ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14316,8 +14028,8 @@ }, "ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14326,8 +14038,8 @@ }, "ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14336,8 +14048,8 @@ }, "ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14346,8 +14058,8 @@ }, "ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14356,8 +14068,8 @@ }, "ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14366,8 +14078,8 @@ }, "ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14376,8 +14088,8 @@ }, "ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14386,8 +14098,8 @@ }, "ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14396,8 +14108,8 @@ }, "ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14406,8 +14118,8 @@ }, "ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14416,8 +14128,8 @@ }, "ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14426,8 +14138,8 @@ }, "ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -14436,8 +14148,8 @@ }, "ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -14777,7 +14489,7 @@ ["self.op_hcompute_kernel_glb_stencil_write.0","self.op_hcompute_kernel_cgra_stencil_read.0"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U679":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U596":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -14786,7 +14498,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U678":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U595":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14795,7 +14507,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U677":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U594":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -14804,7 +14516,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U676":{ + "op_hcompute_hw_output_stencil_read_start_pt__U593":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14813,7 +14525,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U681":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U598":{ "type":["Record",[ ["in",["Array",4,["Array",32,"BitIn"]]], ["out",["Array",4,["Array",32,"Bit"]]] @@ -14822,7 +14534,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U680":{ + "op_hcompute_hw_output_stencil_write_start_pt__U597":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14831,7 +14543,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_exe_start_pt__U689":{ + "op_hcompute_input_glb_stencil_exe_start_pt__U606":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14840,7 +14552,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_read_start_pt__U688":{ + "op_hcompute_input_glb_stencil_read_start_pt__U605":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14849,7 +14561,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_glb_stencil_write_start_pt__U690":{ + "op_hcompute_input_glb_stencil_write_start_pt__U607":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14858,7 +14570,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_exe_start_pt__U684":{ + "op_hcompute_kernel_glb_stencil_exe_start_pt__U601":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14867,7 +14579,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_read_start_pt__U683":{ + "op_hcompute_kernel_glb_stencil_read_start_pt__U600":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14876,7 +14588,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_kernel_glb_stencil_write_start_pt__U685":{ + "op_hcompute_kernel_glb_stencil_write_start_pt__U602":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -14942,38 +14654,6 @@ ["op_hcompute_output_glb_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U434":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U449":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U464":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U479":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U494":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U509":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U524":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "chain_en_const_U539":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -14981,7 +14661,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U420"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U346"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23326],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -14991,7 +14671,7 @@ }, "ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U435"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U360"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"agg2sram_1":{"cycle_starting_addr":[7209],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -15001,7 +14681,7 @@ }, "ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U450"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U374"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -15011,7 +14691,7 @@ }, "ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U465"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U388"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -15021,7 +14701,7 @@ }, "ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U480"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U402"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -15031,7 +14711,7 @@ }, "ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U495"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U416"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -15041,7 +14721,7 @@ }, "ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U510"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U430"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23332],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -15051,7 +14731,7 @@ }, "ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U525"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U444"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -15140,158 +14820,126 @@ ["kernel_host_stencil_op_hcompute_kernel_glb_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "PE_init_U743":{ + "PE_init_U660":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U746":{ + "PE_init_U663":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U749":{ + "PE_init_U666":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U752":{ + "PE_init_U669":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U755":{ + "PE_init_U672":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U758":{ + "PE_init_U675":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U761":{ + "PE_init_U678":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "PE_init_U764":{ + "PE_init_U681":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U741":{ + "_U658":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U742":{ + "_U659":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U744":{ + "_U661":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U745":{ + "_U662":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U747":{ + "_U664":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U748":{ + "_U665":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U750":{ + "_U667":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U751":{ + "_U668":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U753":{ + "_U670":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U754":{ + "_U671":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U756":{ + "_U673":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U757":{ + "_U674":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U759":{ + "_U676":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U760":{ + "_U677":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U762":{ + "_U679":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U763":{ + "_U680":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "input_cgra_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U11":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U13":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U15":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "input_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -15299,7 +14947,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[25],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -15309,7 +14957,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[26],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -15319,7 +14967,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[27],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -15329,7 +14977,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[28],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -15339,7 +14987,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[29],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -15349,7 +14997,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[30],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -15359,7 +15007,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[31],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7200],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -15369,7 +15017,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[32],"cycle_stride":[32,240,8064],"dimensionality":3,"extent":[8,30,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,240]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[8,240,8064],"dimensionality":3,"extent":[30,30,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[7199],"cycle_stride":[4,32,896,2688,8064],"dimensionality":5,"extent":[8,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8,240],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064],"dimensionality":5,"extent":[28,28,3,3,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -15398,262 +15046,6 @@ "modref":"cgralib.BitIO", "modargs":{"mode":["String","in"]} }, - "kernel_cgra_stencil$chain_en_const_U143":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U145":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U147":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U149":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U151":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U153":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U155":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U157":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U159":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U161":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U163":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U165":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U167":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U169":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U171":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U173":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U175":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U177":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U179":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U181":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U183":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U185":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U187":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U189":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U191":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U193":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U195":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U197":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U199":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U201":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U203":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U205":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U207":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U209":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U211":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U213":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U215":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U217":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U219":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U221":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U223":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U225":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U227":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U229":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U231":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U233":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U235":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U237":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U239":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U241":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U243":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U245":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U247":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U249":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U251":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U253":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U255":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U257":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U259":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U261":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U263":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U265":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U267":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "kernel_cgra_stencil$chain_en_const_U269":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -15661,8 +15053,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U133"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[193],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15671,8 +15063,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_10_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U143"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[210],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[17],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15681,8 +15073,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_11_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[218],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[25],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15691,8 +15083,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_12_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U145"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[226],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[33],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15701,8 +15093,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_13_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[234],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[41],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15711,8 +15103,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_14_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U147"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[242],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[49],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15721,8 +15113,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_15_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[250],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[57],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15731,8 +15123,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_16_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[195],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15741,8 +15133,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_17_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[203],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[10],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15751,8 +15143,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_18_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U151"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[211],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[18],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15761,8 +15153,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_19_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[219],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[26],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15771,8 +15163,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U144"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U134"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[201],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[8],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15781,8 +15173,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_20_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U153"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[227],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[34],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15791,8 +15183,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_21_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[235],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[42],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15801,8 +15193,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_22_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U155"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[243],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[50],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15811,8 +15203,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_23_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[251],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[58],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15821,8 +15213,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_24_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U157"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[196],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[3],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15831,8 +15223,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_25_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[204],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[11],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15841,8 +15233,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_26_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U159"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[212],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[19],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15851,8 +15243,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_27_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[220],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[27],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15861,8 +15253,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_28_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U198"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[228],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[35],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15871,8 +15263,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_29_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U200"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U162"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[236],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[43],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15881,8 +15273,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U146"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U135"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[209],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[16],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15891,8 +15283,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_30_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U202"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U163"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[244],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[51],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15901,8 +15293,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_31_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U204"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U164"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[252],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[59],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15911,8 +15303,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_32_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U206"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U165"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[197],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[4],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15921,8 +15313,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_33_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U208"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U166"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[205],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[12],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15931,8 +15323,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_34_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U210"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U167"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[213],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[20],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15941,8 +15333,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_35_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U212"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U168"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[221],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[28],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15951,8 +15343,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_36_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U214"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U169"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[229],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[36],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15961,8 +15353,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_37_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U216"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U170"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[237],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[44],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15971,8 +15363,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_38_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U218"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U171"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[245],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[52],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15981,8 +15373,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_39_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U220"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U172"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[253],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[60],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -15991,8 +15383,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U136"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[217],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[24],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16001,8 +15393,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_40_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U222"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U173"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[198],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[5],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16011,8 +15403,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_41_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U224"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U174"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[206],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[13],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16021,8 +15413,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_42_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U226"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U175"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[214],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[21],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16031,8 +15423,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_43_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U228"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U176"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[222],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[29],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16041,8 +15433,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_44_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U230"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U177"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[230],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[37],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16051,8 +15443,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_45_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U232"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U178"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[238],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[45],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16061,8 +15453,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_46_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U234"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U179"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[246],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[53],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16071,8 +15463,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_47_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U236"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U180"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[254],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[61],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16081,8 +15473,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_48_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U238"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U181"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[199],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[6],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16091,8 +15483,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_49_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U240"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U182"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[207],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[14],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16101,8 +15493,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U150"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U137"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[225],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[32],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16111,8 +15503,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_50_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U242"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U183"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[215],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[22],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16121,8 +15513,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_51_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U244"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U184"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[223],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[30],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16131,8 +15523,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_52_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U246"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U185"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[231],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[38],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16141,8 +15533,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_53_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U248"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U186"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[239],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[46],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16151,8 +15543,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_54_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U250"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U187"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[247],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[54],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16161,8 +15553,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_55_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U252"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U188"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[255],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[62],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16171,8 +15563,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_56_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U254"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U189"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[200],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[7],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16181,8 +15573,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_57_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U256"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U190"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[208],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[15],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16191,8 +15583,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_58_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U258"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U191"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[216],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[23],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16201,8 +15593,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_59_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U260"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U192"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[224],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[31],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16211,8 +15603,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U152"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U138"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[233],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[40],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16221,8 +15613,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_60_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U262"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U193"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[232],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[39],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16231,8 +15623,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_61_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U264"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U194"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[240],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[47],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16241,8 +15633,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_62_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U266"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U195"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[248],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[55],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16251,8 +15643,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_63_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U268"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U196"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[256],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[63],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16261,8 +15653,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U154"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[241],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[48],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16271,8 +15663,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[249],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[56],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16281,8 +15673,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_8_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U158"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U141"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[194],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[1],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16291,8 +15683,8 @@ }, "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_9_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U160"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,8064],"dimensionality":2,"extent":[12,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U142"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[202],"cycle_stride":[256,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"in2agg_0":{"cycle_starting_addr":[9],"cycle_stride":[64,8064],"dimensionality":2,"extent":[9,16],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[3584,8064],"dimensionality":2,"extent":[3,16],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,8064],"dimensionality":4,"extent":[28,28,9,16],"read_data_starting_addr":[0],"read_data_stride":[0,0,1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -16301,7 +15693,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_lake_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U692"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U609"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[23328],"cycle_stride":[1,8,224,16128,32256,64512],"dimensionality":6,"extent":[8,28,28,2,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,16,896,8,448,25088]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_output_cgra_stencil_10$inner_compute$add_957_971_972$binop":{ @@ -16944,38 +16336,6 @@ "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "output_cgra_stencil$chain_en_const_U434":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U449":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U464":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U479":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U494":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U509":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U524":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, - "output_cgra_stencil$chain_en_const_U539":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -16983,7 +16343,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U420"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U346"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23326],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23328],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -16993,7 +16353,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U435"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U360"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"agg2sram_1":{"cycle_starting_addr":[7209],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"in2agg_1":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23329],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -17003,7 +16363,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U450"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U374"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23327],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23330],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_clk_en_const_lutcnst":{ @@ -17013,7 +16373,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U465"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U388"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23331],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_clk_en_const_lutcnst":{ @@ -17023,7 +16383,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U480"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U402"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23329],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23332],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_clk_en_const_lutcnst":{ @@ -17033,7 +16393,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U495"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U416"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23331],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23333],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_clk_en_const_lutcnst":{ @@ -17043,7 +16403,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U510"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U430"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23332],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23334],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_clk_en_const_lutcnst":{ @@ -17053,35 +16413,35 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U525"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U444"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7208],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0,0,196]},"agg2sram_1":{"cycle_starting_addr":[5],"cycle_stride":[4,28,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,3,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,196]},"chain_en":1,"in2agg_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28,16128],"dimensionality":3,"extent":[28,28,8],"write_data_starting_addr":[0],"write_data_stride":[1,12,0]},"sram2tb_0":{"cycle_starting_addr":[7202],"cycle_stride":[4,32,896,2688,8064,16128],"dimensionality":6,"extent":[7,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0,0,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[23333],"cycle_stride":[32,224,16128],"dimensionality":3,"extent":[7,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,7,196],"write_data_starting_addr":[0],"write_data_stride":[1,3,0]},"tb2out_0":{"cycle_starting_addr":[7204],"cycle_stride":[1,32,896,2688,8064,16128],"dimensionality":6,"extent":[28,28,3,3,2,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0,0,0]},"tb2out_1":{"cycle_starting_addr":[23335],"cycle_stride":[8,224,16128],"dimensionality":3,"extent":[28,28,8],"read_data_starting_addr":[0],"read_data_stride":[1,12,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U741.out","PE_init_U743.data.in.0"], - ["_U742.out","PE_init_U743.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U743.data.out"], - ["_U744.out","PE_init_U746.data.in.0"], - ["_U745.out","PE_init_U746.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U746.data.out"], - ["_U747.out","PE_init_U749.data.in.0"], - ["_U748.out","PE_init_U749.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U749.data.out"], - ["_U750.out","PE_init_U752.data.in.0"], - ["_U751.out","PE_init_U752.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U752.data.out"], - ["_U753.out","PE_init_U755.data.in.0"], - ["_U754.out","PE_init_U755.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U755.data.out"], - ["_U756.out","PE_init_U758.data.in.0"], - ["_U757.out","PE_init_U758.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U758.data.out"], - ["_U759.out","PE_init_U761.data.in.0"], - ["_U760.out","PE_init_U761.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U761.data.out"], - ["_U762.out","PE_init_U764.data.in.0"], - ["_U763.out","PE_init_U764.data.in.1"], - ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U764.data.out"], + ["_U658.out","PE_init_U660.data.in.0"], + ["_U659.out","PE_init_U660.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_1","PE_init_U660.data.out"], + ["_U661.out","PE_init_U663.data.in.0"], + ["_U662.out","PE_init_U663.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_0","PE_init_U663.data.out"], + ["_U664.out","PE_init_U666.data.in.0"], + ["_U665.out","PE_init_U666.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_1","PE_init_U666.data.out"], + ["_U667.out","PE_init_U669.data.in.0"], + ["_U668.out","PE_init_U669.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_3_garnet.data_in_1","PE_init_U669.data.out"], + ["_U670.out","PE_init_U672.data.in.0"], + ["_U671.out","PE_init_U672.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_4_garnet.data_in_1","PE_init_U672.data.out"], + ["_U673.out","PE_init_U675.data.in.0"], + ["_U674.out","PE_init_U675.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_5_garnet.data_in_1","PE_init_U675.data.out"], + ["_U676.out","PE_init_U678.data.in.0"], + ["_U677.out","PE_init_U678.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_6_garnet.data_in_1","PE_init_U678.data.out"], + ["_U679.out","PE_init_U681.data.in.0"], + ["_U680.out","PE_init_U681.data.in.1"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_7_garnet.data_in_1","PE_init_U681.data.out"], ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_input_host_stencil_op_hcompute_input_glb_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_output_cgra_stencil_10$inner_compute$mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957$binop.data.in.1","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_input_global_wrapper_stencil_port_controller/stencil_valid.csv b/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_input_global_wrapper_stencil_port_controller/stencil_valid.csv index b4af0d23f..b88d95a55 100644 --- a/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_input_global_wrapper_stencil_port_controller/stencil_valid.csv +++ b/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_input_global_wrapper_stencil_port_controller/stencil_valid.csv @@ -1,6 +1,6 @@ -"cycle_starting_addr",0,0 +"cycle_starting_addr",2,0 "cycle_stride_0",1,0 -"cycle_stride_1",30,0 +"cycle_stride_1",32,0 "dimensionality",2,0 "extent_0",30,0 "extent_1",30,0 diff --git a/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_output_stencil_port_controller/stencil_valid.csv b/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_output_stencil_port_controller/stencil_valid.csv index e06bcc781..7a9ef23fa 100644 --- a/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_output_stencil_port_controller/stencil_valid.csv +++ b/aha_garnet_design_new/resnet_simple/lake_collateral/op_hcompute_hw_output_stencil_port_controller/stencil_valid.csv @@ -1,4 +1,4 @@ -"cycle_starting_addr",8964,0 +"cycle_starting_addr",9024,0 "cycle_stride_0",1,0 "cycle_stride_1",28,0 "dimensionality",2,0 diff --git a/aha_garnet_design_new/resnet_simple/resnet_simple.json b/aha_garnet_design_new/resnet_simple/resnet_simple.json index b29410e17..974a83786 100644 --- a/aha_garnet_design_new/resnet_simple/resnet_simple.json +++ b/aha_garnet_design_new/resnet_simple/resnet_simple.json @@ -17,14 +17,10 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_conv_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[908],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[8962],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[968],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[9022],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake"} }, "ub_conv_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -32,7 +28,6 @@ } }, "connections":[ - ["ub_conv_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], ["ub_conv_stencil_BANK_0.clk","self.clk"], ["ub_conv_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], ["ub_conv_stencil_BANK_0.data_in_0","self.op_hcompute_conv_stencil_1_write.0"], @@ -231,14 +226,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,30],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[900],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[960],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -246,7 +237,6 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U3.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], @@ -266,14 +256,10 @@ ["op_hcompute_hw_kernel_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_kernel_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -281,7 +267,6 @@ } }, "connections":[ - ["ub_hw_kernel_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U5.out"], ["ub_hw_kernel_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_kernel_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], ["ub_hw_kernel_global_wrapper_stencil_BANK_0.data_in_0","self.op_hcompute_hw_kernel_global_wrapper_stencil_write.0"], @@ -290,7 +275,7 @@ ["ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_kernel_global_wrapper_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U17":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -299,7 +284,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U16":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -308,7 +293,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U18":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -317,7 +302,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U12":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -326,7 +311,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U11":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -335,7 +320,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U13":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -344,7 +329,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U8":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U5":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -353,7 +338,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U7":{ + "op_hcompute_hw_output_stencil_read_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -362,7 +347,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U9":{ + "op_hcompute_hw_output_stencil_write_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -383,12 +368,12 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U14":{ + "_U11":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U19":{ + "_U16":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -412,71 +397,71 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U17" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U15"} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U16" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U18" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15" }, "op_hcompute_hw_kernel_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_kernel_global_wrapper_stencil" }, "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U12" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9" }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,3],"dimensionality":2,"extent":[3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U10"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,3],"dimensionality":2,"extent":[3,3]}},"mode":"lake"} }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_kernel_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U11" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8" }, "op_hcompute_hw_kernel_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U13" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U8" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U5" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U7" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U4" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U9" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U6" } }, "connections":[ - ["self.clk","_U14.clk"], - ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","_U14.in"], - ["self.clk","_U19.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U19.in"], + ["self.clk","_U11.clk"], + ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","_U11.in"], + ["self.clk","_U16.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U16.in"], ["self.clk","conv_stencil.clk"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_read","conv_stencil.op_hcompute_conv_stencil_1_read"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], diff --git a/aha_garnet_design_new/resnet_simple/resnet_simple_garnet.json b/aha_garnet_design_new/resnet_simple/resnet_simple_garnet.json index 6929b720d..1d7b3b305 100644 --- a/aha_garnet_design_new/resnet_simple/resnet_simple_garnet.json +++ b/aha_garnet_design_new/resnet_simple/resnet_simple_garnet.json @@ -179,10 +179,6 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -190,8 +186,8 @@ }, "ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[908],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[8962],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[968],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[9022],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -212,26 +208,26 @@ ["conv_stencil_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U22":{ + "PE_init_U19":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U20":{ + "_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U21":{ + "_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U20.out","PE_init_U22.data.in.0"], - ["_U21.out","PE_init_U22.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U22.data.out"], + ["_U17.out","PE_init_U19.data.in.0"], + ["_U18.out","PE_init_U19.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U19.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -324,26 +320,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U25":{ + "PE_init_U22":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U23":{ + "_U20":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U24":{ + "_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U23.out","PE_init_U25.data.in.0"], - ["_U24.out","PE_init_U25.data.in.1"], - ["self.out_conv_stencil","PE_init_U25.data.out"] + ["_U20.out","PE_init_U22.data.in.0"], + ["_U21.out","PE_init_U22.data.in.1"], + ["self.out_conv_stencil","PE_init_U22.data.out"] ] }, "hcompute_conv_stencil_1":{ @@ -425,10 +421,6 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -436,8 +428,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,30],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[900],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[960],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -459,10 +451,6 @@ ["op_hcompute_hw_kernel_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -470,8 +458,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -482,7 +470,7 @@ ["ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet.clk_en","ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U17":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -491,7 +479,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U16":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -500,7 +488,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U18":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -509,7 +497,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U12":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -518,7 +506,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U11":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -527,7 +515,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U13":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -536,7 +524,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U8":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U5":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -545,7 +533,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U7":{ + "op_hcompute_hw_output_stencil_read_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -554,7 +542,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U9":{ + "op_hcompute_hw_output_stencil_write_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -575,25 +563,21 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U28":{ + "PE_init_U25":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U26":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U27":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "conv_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -601,12 +585,8 @@ }, "conv_stencil$ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[908],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[8962],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[968],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[9022],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -615,12 +595,8 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,30],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[900],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "hw_kernel_global_wrapper_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[960],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -629,20 +605,20 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[12],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[3584],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, - "metadata":{"in2glb_0":{"cycle_starting_addr":[8964],"cycle_stride":[1],"dimensionality":1,"extent":[784],"write_data_starting_addr":[0],"write_data_stride":[1]}} + "metadata":{"in2glb_0":{"cycle_starting_addr":[9024],"cycle_stride":[1],"dimensionality":1,"extent":[784],"write_data_starting_addr":[0],"write_data_stride":[1]}} }, "io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, - "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[900],"read_data_starting_addr":[0],"read_data_stride":[1]}} + "metadata":{"glb2out_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[1,30]}} }, "io16in_hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_0":{ "genref":"cgralib.IO", @@ -685,14 +661,14 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U26.out","PE_init_U28.data.in.0"], - ["_U27.out","PE_init_U28.data.in.1"], - ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U28.data.out"], + ["_U23.out","PE_init_U25.data.in.0"], + ["_U24.out","PE_init_U25.data.in.1"], + ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U25.data.out"], ["conv_stencil$ub_conv_stencil_BANK_0_garnet.clk_en","conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_conv_stencil_1$inner_compute$add_conv_stencil_1_666_667$binop.data.out","conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_conv_stencil_1$inner_compute$add_conv_stencil_1_666_667$binop.data.in.0","conv_stencil$ub_conv_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_new/resnet_tiny/resnet_tiny.json b/aha_garnet_design_new/resnet_tiny/resnet_tiny.json new file mode 100644 index 000000000..b18b84728 --- /dev/null +++ b/aha_garnet_design_new/resnet_tiny/resnet_tiny.json @@ -0,0 +1,540 @@ +{"top":"global.resnet_tiny", +"namespaces":{ + "global":{ + "modules":{ + "conv_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_conv_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_conv_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_conv_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_conv_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_conv_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_conv_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_conv_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[4,16],"dimensionality":2,"extent":[4,14],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"agg2sram_1":{"cycle_starting_addr":[262],"cycle_stride":[4,16,224,672],"dimensionality":4,"extent":[4,14,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,0,0]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[1,16],"dimensionality":2,"extent":[14,14],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2agg_1":{"cycle_starting_addr":[258],"cycle_stride":[1,16,224,672],"dimensionality":4,"extent":[14,14,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[4,16,224,672],"dimensionality":4,"extent":[4,14,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"sram2tb_1":{"cycle_starting_addr":[2272],"cycle_stride":[4,16],"dimensionality":2,"extent":[4,14],"read_data_starting_addr":[0],"read_data_stride":[1,4],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,16,224,672],"dimensionality":4,"extent":[14,14,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,0]},"tb2out_1":{"cycle_starting_addr":[2274],"cycle_stride":[1,16],"dimensionality":2,"extent":[14,14],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} + }, + "ub_conv_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_conv_stencil_BANK_0.clk","self.clk"], + ["ub_conv_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], + ["ub_conv_stencil_BANK_0.data_in_1","self.op_hcompute_conv_stencil_1_write.0"], + ["ub_conv_stencil_BANK_0.data_in_0","self.op_hcompute_conv_stencil_write.0"], + ["ub_conv_stencil_BANK_0.data_out_1","self.op_hcompute_hw_output_stencil_read.0"], + ["ub_conv_stencil_BANK_0.flush","self.reset"], + ["ub_conv_stencil_BANK_0_clk_en_const.out","ub_conv_stencil_BANK_0.clk_en"], + ["ub_conv_stencil_BANK_0_clk_en_const.out","ub_conv_stencil_BANK_0.rst_n"] + ] + }, + "cu_op_hcompute_conv_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["conv_stencil_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_conv_stencil" + } + }, + "connections":[ + ["self.conv_stencil_op_hcompute_conv_stencil_write.0","inner_compute.out_conv_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_conv_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["conv_stencil_op_hcompute_conv_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["conv_stencil_op_hcompute_conv_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_conv_stencil_1" + } + }, + "connections":[ + ["self.conv_stencil_op_hcompute_conv_stencil_1_read.0","inner_compute.in0_conv_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_1_read.0","inner_compute.in1_hw_input_global_wrapper_stencil.0"], + ["self.hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_1_read.0","inner_compute.in2_hw_kernel_global_wrapper_stencil.0"], + ["self.conv_stencil_op_hcompute_conv_stencil_1_write.0","inner_compute.out_conv_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_input_global_wrapper_stencil" + } + }, + "connections":[ + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_kernel_global_wrapper_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_kernel_global_wrapper_stencil" + } + }, + "connections":[ + ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","inner_compute.in0_hw_kernel_stencil.0"], + ["self.hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write.0","inner_compute.out_hw_kernel_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_output_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["conv_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_output_stencil" + } + }, + "connections":[ + ["self.conv_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in0_conv_stencil.0"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "hcompute_conv_stencil":{ + "type":["Record",[ + ["out_conv_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__662":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_conv_stencil","const_p0__662.out"] + ] + }, + "hcompute_conv_stencil_1":{ + "type":["Record",[ + ["out_conv_stencil",["Array",16,"Bit"]], + ["in0_conv_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_hw_kernel_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_conv_stencil_1_666_667":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_conv_stencil.0","add_conv_stencil_1_666_667.in0"], + ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666.out","add_conv_stencil_1_666_667.in1"], + ["self.out_conv_stencil","add_conv_stencil_1_666_667.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666.in0"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_kernel_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_kernel_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_kernel_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_kernel_global_wrapper_stencil","self.in0_hw_kernel_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_conv_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "smax_conv_stencil_2_677_678":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_conv_stencil_2_677_678.in1","const_p0__677.out"], + ["smax_conv_stencil_2_677_678.in0","self.in0_conv_stencil.0"], + ["smax_conv_stencil_2_677_678.out","self.out_hw_output_stencil"] + ] + }, + "hw_input_global_wrapper_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_conv_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_conv_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_hw_input_global_wrapper_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,16],"dimensionality":2,"extent":[4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,16],"dimensionality":2,"extent":[16,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[254],"cycle_stride":[4,16,224,672],"dimensionality":4,"extent":[4,14,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,4],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,16,224,672],"dimensionality":4,"extent":[14,14,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"] + ] + }, + "hw_kernel_global_wrapper_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_conv_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_conv_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_hw_kernel_global_wrapper_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_kernel_global_wrapper_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_hw_kernel_global_wrapper_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"sram2tb_0":{"cycle_starting_addr":[256],"cycle_stride":[896],"dimensionality":1,"extent":[3],"read_data_starting_addr":[0],"read_data_stride":[1],"write_data_starting_addr":[0],"write_data_stride":[1]},"tb2out_0":{"cycle_starting_addr":[258],"cycle_stride":[1,16,224],"dimensionality":3,"extent":[14,14,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"lake"} + }, + "ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_hw_kernel_global_wrapper_stencil_BANK_0.clk","self.clk"], + ["ub_hw_kernel_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], + ["ub_hw_kernel_global_wrapper_stencil_BANK_0.data_in_0","self.op_hcompute_hw_kernel_global_wrapper_stencil_write.0"], + ["ub_hw_kernel_global_wrapper_stencil_BANK_0.flush","self.reset"], + ["ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_kernel_global_wrapper_stencil_BANK_0.clk_en"], + ["ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_kernel_global_wrapper_stencil_BANK_0.rst_n"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_exe_start_pt__U5":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_read_start_pt__U4":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_write_start_pt__U6":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "resnet_tiny":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["reset","BitIn"], + ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], + ["hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en","Bit"], + ["hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "_U11":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U16":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "conv_stencil":{ + "modref":"global.conv_stencil_ub" + }, + "hw_input_global_wrapper_stencil":{ + "modref":"global.hw_input_global_wrapper_stencil_ub" + }, + "hw_kernel_global_wrapper_stencil":{ + "modref":"global.hw_kernel_global_wrapper_stencil_ub" + }, + "op_hcompute_conv_stencil":{ + "modref":"global.cu_op_hcompute_conv_stencil" + }, + "op_hcompute_conv_stencil_1":{ + "modref":"global.cu_op_hcompute_conv_stencil_1" + }, + "op_hcompute_hw_input_global_wrapper_stencil":{ + "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" + }, + "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14" + }, + "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,16],"dimensionality":2,"extent":[16,16]}},"mode":"lake"} + }, + "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13" + }, + "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15" + }, + "op_hcompute_hw_kernel_global_wrapper_stencil":{ + "modref":"global.cu_op_hcompute_hw_kernel_global_wrapper_stencil" + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9" + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,3],"dimensionality":2,"extent":[3,3]}},"mode":"lake"} + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start":{ + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8" + }, + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start":{ + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10" + }, + "op_hcompute_hw_output_stencil":{ + "modref":"global.cu_op_hcompute_hw_output_stencil" + }, + "op_hcompute_hw_output_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U5" + }, + "op_hcompute_hw_output_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[2274],"cycle_stride":[1,16],"dimensionality":2,"extent":[14,14]}},"mode":"lake"} + }, + "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_output_stencil_read_start":{ + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U4" + }, + "op_hcompute_hw_output_stencil_write_start":{ + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U6" + } + }, + "connections":[ + ["self.clk","_U11.clk"], + ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","_U11.in"], + ["self.clk","_U16.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U16.in"], + ["self.clk","conv_stencil.clk"], + ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_read","conv_stencil.op_hcompute_conv_stencil_1_read"], + ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], + ["op_hcompute_conv_stencil.conv_stencil_op_hcompute_conv_stencil_write","conv_stencil.op_hcompute_conv_stencil_write"], + ["op_hcompute_hw_output_stencil.conv_stencil_op_hcompute_hw_output_stencil_read","conv_stencil.op_hcompute_hw_output_stencil_read"], + ["self.reset","conv_stencil.reset"], + ["self.clk","hw_input_global_wrapper_stencil.clk"], + ["op_hcompute_conv_stencil_1.hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_1_read","hw_input_global_wrapper_stencil.op_hcompute_conv_stencil_1_read"], + ["op_hcompute_hw_input_global_wrapper_stencil.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write","hw_input_global_wrapper_stencil.op_hcompute_hw_input_global_wrapper_stencil_write"], + ["self.reset","hw_input_global_wrapper_stencil.reset"], + ["self.clk","hw_kernel_global_wrapper_stencil.clk"], + ["op_hcompute_conv_stencil_1.hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_1_read","hw_kernel_global_wrapper_stencil.op_hcompute_conv_stencil_1_read"], + ["op_hcompute_hw_kernel_global_wrapper_stencil.hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write","hw_kernel_global_wrapper_stencil.op_hcompute_hw_kernel_global_wrapper_stencil_write"], + ["self.reset","hw_kernel_global_wrapper_stencil.reset"], + ["self.clk","op_hcompute_conv_stencil.clk"], + ["self.clk","op_hcompute_conv_stencil_1.clk"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read","op_hcompute_hw_input_global_wrapper_stencil.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_input_global_wrapper_stencil_port_controller.flush"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.rst_n"], + ["op_hcompute_hw_input_global_wrapper_stencil_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], + ["self.clk","op_hcompute_hw_kernel_global_wrapper_stencil.clk"], + ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read","op_hcompute_hw_kernel_global_wrapper_stencil.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read"], + ["op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.stencil_valid","op_hcompute_hw_kernel_global_wrapper_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.clk"], + ["op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.flush"], + ["op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.rst_n"], + ["op_hcompute_hw_kernel_global_wrapper_stencil_read_start.in","op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_kernel_global_wrapper_stencil_write_start.in","op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.stencil_valid"], + ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en","op_hcompute_hw_kernel_global_wrapper_stencil_read_start.out"], + ["self.clk","op_hcompute_hw_output_stencil.clk"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_op_hcompute_hw_output_stencil_write"], + ["op_hcompute_hw_output_stencil_port_controller.stencil_valid","op_hcompute_hw_output_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_output_stencil_port_controller.clk"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_output_stencil_port_controller.flush"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.rst_n"], + ["op_hcompute_hw_output_stencil_read_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_output_stencil_write_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"] + ] + } + }, + "generators":{ + "delay_tile":{ + "typegen":"global.delay_tile_TG", + "genparams":{"delay":"Int"} + }, + "raw_dual_port_sram_tile":{ + "typegen":"global.raw_dual_port_sram_TG", + "genparams":{"depth":"Int"} + }, + "raw_quad_port_memtile":{ + "typegen":"global.raw_quad_port_memtile_TG", + "genparams":{"depth":"Int"} + }, + "tahoe":{ + "typegen":"global.tahoe_TG", + "genparams":{"depth":"Int"} + } + }, + "typegens":{ + "delay_tile_TG":[{"delay":"Int"},"implicit"], + "raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"], + "raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"], + "tahoe_TG":[{"depth":"Int"},"implicit"] + } + } +} +} diff --git a/aha_garnet_design_new/rom/rom.json b/aha_garnet_design_new/rom/rom.json index d9948cca3..790dce18a 100644 --- a/aha_garnet_design_new/rom/rom.json +++ b/aha_garnet_design_new/rom/rom.json @@ -202,8 +202,8 @@ }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U4"} + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -223,8 +223,8 @@ }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", diff --git a/aha_garnet_design_new/rom/rom_garnet.json b/aha_garnet_design_new/rom/rom_garnet.json index 9f8f95125..069a8dbe9 100644 --- a/aha_garnet_design_new/rom/rom_garnet.json +++ b/aha_garnet_design_new/rom/rom_garnet.json @@ -258,8 +258,8 @@ }, "connections":[ ["inner_compute$smax_776_777_778$cgramax.data.in.1","inner_compute$const_p0__777.out"], - ["inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$scomp$compop.data.in.1","inner_compute$const_p1023__775.out"], - ["inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$min_mux$mux.data.in.1","inner_compute$const_p1023__7751.out"], + ["inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$min_mux$mux.data.in.1","inner_compute$const_p1023__775.out"], + ["inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$scomp$compop.data.in.1","inner_compute$const_p1023__7751.out"], ["inner_compute$rom_curvea0$1_rom.ren_in_0","inner_compute$rom_curvea0$1_ren_lutcnst.bit.out"], ["inner_compute$smax_776_777_778$cgramax.data.out","inner_compute$rom_curvea0$1_rom.addr_in_0"], ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write.0","inner_compute$rom_curvea0$1_rom.data_out_0"], @@ -329,8 +329,8 @@ }, "connections":[ ["smax_776_777_778$cgramax.data.in.1","const_p0__777.out"], - ["smin_hw_input_global_wrapper_stencil_1_775_776$scomp$compop.data.in.1","const_p1023__775.out"], - ["smin_hw_input_global_wrapper_stencil_1_775_776$min_mux$mux.data.in.1","const_p1023__7751.out"], + ["smin_hw_input_global_wrapper_stencil_1_775_776$min_mux$mux.data.in.1","const_p1023__775.out"], + ["smin_hw_input_global_wrapper_stencil_1_775_776$scomp$compop.data.in.1","const_p1023__7751.out"], ["rom_curvea0$1_rom.ren_in_0","rom_curvea0$1_ren_lutcnst.bit.out"], ["smax_776_777_778$cgramax.data.out","rom_curvea0$1_rom.addr_in_0"], ["self.out_hw_output_stencil","rom_curvea0$1_rom.data_out_0"], @@ -485,7 +485,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -496,8 +496,8 @@ ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_op_hcompute_hw_output_stencil_write_valid.in"], ["op_hcompute_hw_output_stencil_port_controller_garnet.flush","io1in_reset.out"], ["op_hcompute_hw_output_stencil$inner_compute$smax_776_777_778$cgramax.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p0__777.out"], - ["op_hcompute_hw_output_stencil$inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$scomp$compop.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p1023__775.out"], - ["op_hcompute_hw_output_stencil$inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$min_mux$mux.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p1023__7751.out"], + ["op_hcompute_hw_output_stencil$inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$min_mux$mux.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p1023__775.out"], + ["op_hcompute_hw_output_stencil$inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$scomp$compop.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p1023__7751.out"], ["op_hcompute_hw_output_stencil$inner_compute$rom_curvea0$1_rom.ren_in_0","op_hcompute_hw_output_stencil$inner_compute$rom_curvea0$1_ren_lutcnst.bit.out"], ["op_hcompute_hw_output_stencil$inner_compute$smax_776_777_778$cgramax.data.out","op_hcompute_hw_output_stencil$inner_compute$rom_curvea0$1_rom.addr_in_0"], ["op_hcompute_hw_output_stencil$inner_compute$smin_hw_input_global_wrapper_stencil_1_775_776$min_mux$mux.data.out","op_hcompute_hw_output_stencil$inner_compute$smax_776_777_778$cgramax.data.in.0"], diff --git a/aha_garnet_design_new/unsharp/unsharp.json b/aha_garnet_design_new/unsharp/unsharp.json index 58c0cda35..ffc5981ca 100644 --- a/aha_garnet_design_new/unsharp/unsharp.json +++ b/aha_garnet_design_new/unsharp/unsharp.json @@ -177,7 +177,7 @@ ["valid_pass_out","Bit"], ["hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["ratio_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -187,7 +187,7 @@ "connections":[ ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in0_hw_input_global_wrapper_stencil.0"], ["self.ratio_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in1_ratio_stencil.0"], - ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -198,7 +198,7 @@ ["valid_pass_out","Bit"], ["hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["ratio_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -208,7 +208,7 @@ "connections":[ ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute.in0_hw_input_global_wrapper_stencil.0"], ["self.ratio_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute.in1_ratio_stencil.0"], - ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -219,7 +219,7 @@ ["valid_pass_out","Bit"], ["hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], ["ratio_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute":{ @@ -229,7 +229,7 @@ "connections":[ ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_2_read.0","inner_compute.in0_hw_input_global_wrapper_stencil.0"], ["self.ratio_stencil_op_hcompute_hw_output_stencil_2_read.0","inner_compute.in1_ratio_stencil.0"], - ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write.0","inner_compute.out_hw_output_stencil"], + ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write.0","inner_compute.out_hw_output_stencil"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -267,14 +267,6 @@ ["op_hcompute_ratio_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "d_reg__U10":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -325,22 +317,22 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U20":{ + "d_reg__U2":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U21":{ + "d_reg__U20":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U22":{ + "d_reg__U21":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U23":{ + "d_reg__U3":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -377,8 +369,8 @@ }, "ub_gray_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[190],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[253],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[192],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[256],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[190],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[253],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[192],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[256],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_gray_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -386,8 +378,8 @@ }, "ub_gray_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_gray_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -395,69 +387,67 @@ } }, "connections":[ - ["ub_gray_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_gray_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], ["self.clk","d_reg__U10.clk"], - ["d_reg__U9.out","d_reg__U10.in"], + ["ub_gray_stencil_BANK_1.data_out_0","d_reg__U10.in"], ["d_reg__U11.in","d_reg__U10.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U10.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.5","d_reg__U10.out"], ["self.clk","d_reg__U11.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.7","d_reg__U11.out"], + ["d_reg__U12.in","d_reg__U11.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U11.out"], + ["self.op_hcompute_ratio_stencil_read.0","d_reg__U11.out"], ["self.clk","d_reg__U12.clk"], - ["ub_gray_stencil_BANK_1.data_out_0","d_reg__U12.in"], ["d_reg__U13.in","d_reg__U12.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.5","d_reg__U12.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U12.out"], ["self.clk","d_reg__U13.clk"], - ["d_reg__U14.in","d_reg__U13.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U13.out"], - ["self.op_hcompute_ratio_stencil_read.0","d_reg__U13.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.2","d_reg__U13.out"], ["self.clk","d_reg__U14.clk"], + ["ub_gray_stencil_BANK_0.data_out_0","d_reg__U14.in"], ["d_reg__U15.in","d_reg__U14.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U14.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.24","d_reg__U14.out"], ["self.clk","d_reg__U15.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.2","d_reg__U15.out"], + ["d_reg__U16.in","d_reg__U15.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.23","d_reg__U15.out"], ["self.clk","d_reg__U16.clk"], - ["ub_gray_stencil_BANK_0.data_out_0","d_reg__U16.in"], ["d_reg__U17.in","d_reg__U16.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.24","d_reg__U16.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.22","d_reg__U16.out"], ["self.clk","d_reg__U17.clk"], - ["d_reg__U18.in","d_reg__U17.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.23","d_reg__U17.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.21","d_reg__U17.out"], ["self.clk","d_reg__U18.clk"], + ["ub_gray_stencil_BANK_0.data_out_1","d_reg__U18.in"], ["d_reg__U19.in","d_reg__U18.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.22","d_reg__U18.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.19","d_reg__U18.out"], ["self.clk","d_reg__U19.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.21","d_reg__U19.out"], + ["d_reg__U20.in","d_reg__U19.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.18","d_reg__U19.out"], + ["self.clk","d_reg__U2.clk"], + ["self.op_hcompute_gray_stencil_write.0","d_reg__U2.in"], + ["d_reg__U3.in","d_reg__U2.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.16","d_reg__U2.out"], ["self.clk","d_reg__U20.clk"], - ["ub_gray_stencil_BANK_0.data_out_1","d_reg__U20.in"], ["d_reg__U21.in","d_reg__U20.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.19","d_reg__U20.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.11","d_reg__U20.out"], ["self.clk","d_reg__U21.clk"], - ["d_reg__U22.in","d_reg__U21.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.18","d_reg__U21.out"], - ["self.clk","d_reg__U22.clk"], - ["d_reg__U23.in","d_reg__U22.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.11","d_reg__U22.out"], - ["self.clk","d_reg__U23.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U23.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U21.out"], + ["self.clk","d_reg__U3.clk"], + ["d_reg__U4.in","d_reg__U3.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.15","d_reg__U3.out"], ["self.clk","d_reg__U4.clk"], - ["self.op_hcompute_gray_stencil_write.0","d_reg__U4.in"], ["d_reg__U5.in","d_reg__U4.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.16","d_reg__U4.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.14","d_reg__U4.out"], ["self.clk","d_reg__U5.clk"], - ["d_reg__U6.in","d_reg__U5.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.15","d_reg__U5.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.13","d_reg__U5.out"], ["self.clk","d_reg__U6.clk"], + ["ub_gray_stencil_BANK_1.data_out_1","d_reg__U6.in"], ["d_reg__U7.in","d_reg__U6.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.14","d_reg__U6.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.10","d_reg__U6.out"], ["self.clk","d_reg__U7.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.13","d_reg__U7.out"], + ["d_reg__U8.in","d_reg__U7.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.9","d_reg__U7.out"], ["self.clk","d_reg__U8.clk"], - ["ub_gray_stencil_BANK_1.data_out_1","d_reg__U8.in"], ["d_reg__U9.in","d_reg__U8.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.10","d_reg__U8.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U8.out"], ["self.clk","d_reg__U9.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.9","d_reg__U9.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.7","d_reg__U9.out"], ["ub_gray_stencil_BANK_0.clk","self.clk"], ["ub_gray_stencil_BANK_1.clk","self.clk"], ["ub_gray_stencil_BANK_1.data_out_1","self.op_hcompute_blur_unnormalized_stencil_1_read.12"], @@ -1263,22 +1253,10 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U24"} + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1286,8 +1264,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U26"} + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -1295,8 +1273,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U28"} + "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -1304,9 +1282,6 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U25.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_1.chain_chain_en","chain_en_const_U27.out"], - ["ub_hw_input_global_wrapper_stencil_BANK_2.chain_chain_en","chain_en_const_U29.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_1.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_2.clk","self.clk"], @@ -1330,7 +1305,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_2.rst_n"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U49":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U44":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1339,7 +1314,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U48":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U43":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1348,7 +1323,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U50":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U45":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1357,7 +1332,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U44":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U39":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1366,7 +1341,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U43":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1375,7 +1350,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U45":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1384,7 +1359,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U54":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U49":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1393,7 +1368,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U53":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U48":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1402,7 +1377,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U55":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U50":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1411,7 +1386,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U36":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U31":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1420,7 +1395,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U35":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U30":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1429,7 +1404,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U37":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U32":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1438,7 +1413,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U32":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U27":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1447,7 +1422,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U31":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1456,7 +1431,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U33":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U28":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1465,7 +1440,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U40":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U35":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1474,7 +1449,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U39":{ + "op_hcompute_hw_output_stencil_read_start_pt__U34":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1483,7 +1458,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U41":{ + "op_hcompute_hw_output_stencil_write_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1522,25 +1497,25 @@ ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write_valid","Bit"], - ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write_valid","Bit"], - ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write_valid","Bit"], - ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_valid","Bit"], + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_valid","Bit"], + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U46":{ + "_U41":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U51":{ + "_U46":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U56":{ + "_U51":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -1573,61 +1548,61 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_1" }, "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U49" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U44" }, "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U47"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U47"} + "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U48" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U43" }, "op_hcompute_hw_input_global_wrapper_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U50" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U45" }, "op_hcompute_hw_input_global_wrapper_stencil_2":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_2" }, "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U44" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U39" }, "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U42"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U42"} + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U43" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U38" }, "op_hcompute_hw_input_global_wrapper_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U45" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U40" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U54" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U49" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U52"} + "genargs":{"ID":["String","_U47"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U53" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U48" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U55" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U50" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" @@ -1636,61 +1611,61 @@ "modref":"global.cu_op_hcompute_hw_output_stencil_1" }, "op_hcompute_hw_output_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U36" + "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U31" }, "op_hcompute_hw_output_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U34"} + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U35" + "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U30" }, "op_hcompute_hw_output_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U37" + "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U32" }, "op_hcompute_hw_output_stencil_2":{ "modref":"global.cu_op_hcompute_hw_output_stencil_2" }, "op_hcompute_hw_output_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U32" + "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U27" }, "op_hcompute_hw_output_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U30"} + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U31" + "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U26" }, "op_hcompute_hw_output_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U33" + "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U28" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U40" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U35" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U38"} + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U39" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U34" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U41" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U36" }, "op_hcompute_ratio_stencil":{ "modref":"global.cu_op_hcompute_ratio_stencil" @@ -1700,12 +1675,12 @@ } }, "connections":[ + ["self.clk","_U41.clk"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","_U41.in"], ["self.clk","_U46.clk"], - ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","_U46.in"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","_U46.in"], ["self.clk","_U51.clk"], - ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","_U51.in"], - ["self.clk","_U56.clk"], - ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U56.in"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U51.in"], ["self.clk","blur_unnormalized_stencil.clk"], ["op_hcompute_blur_unnormalized_stencil_1.blur_unnormalized_stencil_op_hcompute_blur_unnormalized_stencil_1_write","blur_unnormalized_stencil.op_hcompute_blur_unnormalized_stencil_1_write"], ["op_hcompute_ratio_stencil.blur_unnormalized_stencil_op_hcompute_ratio_stencil_read","blur_unnormalized_stencil.op_hcompute_ratio_stencil_read"], @@ -1762,10 +1737,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], ["self.clk","op_hcompute_hw_output_stencil.clk"], - ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write"], + ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write"], ["ratio_stencil.op_hcompute_hw_output_stencil_read","op_hcompute_hw_output_stencil.ratio_stencil_op_hcompute_hw_output_stencil_read"], ["self.clk","op_hcompute_hw_output_stencil_1.clk"], - ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write","op_hcompute_hw_output_stencil_1.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write"], + ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write","op_hcompute_hw_output_stencil_1.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write"], ["ratio_stencil.op_hcompute_hw_output_stencil_1_read","op_hcompute_hw_output_stencil_1.ratio_stencil_op_hcompute_hw_output_stencil_1_read"], ["op_hcompute_hw_output_stencil_1_port_controller.stencil_valid","op_hcompute_hw_output_stencil_1_exe_start.in"], ["self.clk","op_hcompute_hw_output_stencil_1_port_controller.clk"], @@ -1774,9 +1749,9 @@ ["op_hcompute_hw_output_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_1_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_1_read_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_1_write_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write_valid","op_hcompute_hw_output_stencil_1_write_start.out"], + ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_valid","op_hcompute_hw_output_stencil_1_write_start.out"], ["self.clk","op_hcompute_hw_output_stencil_2.clk"], - ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write","op_hcompute_hw_output_stencil_2.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write"], + ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write","op_hcompute_hw_output_stencil_2.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write"], ["ratio_stencil.op_hcompute_hw_output_stencil_2_read","op_hcompute_hw_output_stencil_2.ratio_stencil_op_hcompute_hw_output_stencil_2_read"], ["op_hcompute_hw_output_stencil_2_port_controller.stencil_valid","op_hcompute_hw_output_stencil_2_exe_start.in"], ["self.clk","op_hcompute_hw_output_stencil_2_port_controller.clk"], @@ -1785,7 +1760,7 @@ ["op_hcompute_hw_output_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_2_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_2_read_start.in","op_hcompute_hw_output_stencil_2_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_2_write_start.in","op_hcompute_hw_output_stencil_2_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write_valid","op_hcompute_hw_output_stencil_2_write_start.out"], + ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_valid","op_hcompute_hw_output_stencil_2_write_start.out"], ["op_hcompute_hw_output_stencil_port_controller.stencil_valid","op_hcompute_hw_output_stencil_exe_start.in"], ["self.clk","op_hcompute_hw_output_stencil_port_controller.clk"], ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.clk_en"], @@ -1793,7 +1768,7 @@ ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.rst_n"], ["op_hcompute_hw_output_stencil_read_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], ["op_hcompute_hw_output_stencil_write_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], - ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"], + ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"], ["self.clk","op_hcompute_ratio_stencil.clk"], ["ratio_stencil.op_hcompute_ratio_stencil_write","op_hcompute_ratio_stencil.ratio_stencil_op_hcompute_ratio_stencil_write"], ["self.clk","ratio_stencil.clk"], diff --git a/aha_garnet_design_new/unsharp/unsharp_garnet.json b/aha_garnet_design_new/unsharp/unsharp_garnet.json index f69a90944..d353ae89d 100644 --- a/aha_garnet_design_new/unsharp/unsharp_garnet.json +++ b/aha_garnet_design_new/unsharp/unsharp_garnet.json @@ -279,26 +279,26 @@ ["blur_unnormalized_stencil_clkwrk_dsa6_op_hcompute_blur_unnormalized_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U59":{ + "PE_init_U54":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U57":{ + "_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U58":{ + "_U53":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U57.out","PE_init_U59.data.in.0"], - ["_U58.out","PE_init_U59.data.in.1"], - ["self.blur_unnormalized_stencil_clkwrk_dsa6_op_hcompute_blur_unnormalized_stencil_write.0","PE_init_U59.data.out"], + ["_U52.out","PE_init_U54.data.in.0"], + ["_U53.out","PE_init_U54.data.in.1"], + ["self.blur_unnormalized_stencil_clkwrk_dsa6_op_hcompute_blur_unnormalized_stencil_write.0","PE_init_U54.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -916,7 +916,7 @@ ["valid_pass_out","Bit"], ["hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["ratio_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute$const_p255__776":{ @@ -956,8 +956,8 @@ } }, "connections":[ - ["inner_compute$umin_775_776_777$ucomp$compop.data.in.1","inner_compute$const_p255__776.out"], - ["inner_compute$umin_775_776_777$min_mux$mux.data.in.1","inner_compute$const_p255__7761.out"], + ["inner_compute$umin_775_776_777$min_mux$mux.data.in.1","inner_compute$const_p255__776.out"], + ["inner_compute$umin_775_776_777$ucomp$compop.data.in.1","inner_compute$const_p255__7761.out"], ["inner_compute$lshr_773_774_775$binop.data.in.1","inner_compute$const_p5__774.out"], ["inner_compute$mul_ratio_stencil_1_hw_input_global_wrapper_stencil_4_773$binop.data.out","inner_compute$lshr_773_774_775$binop.data.in.0"], ["inner_compute$umin_775_776_777$min_mux$mux.data.in.0","inner_compute$lshr_773_774_775$binop.data.out"], @@ -965,7 +965,7 @@ ["self.ratio_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute$mul_ratio_stencil_1_hw_input_global_wrapper_stencil_4_773$binop.data.in.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute$mul_ratio_stencil_1_hw_input_global_wrapper_stencil_4_773$binop.data.in.1"], ["inner_compute$umin_775_776_777$ucomp$compop.bit.out","inner_compute$umin_775_776_777$min_mux$mux.bit.in.0"], - ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write.0","inner_compute$umin_775_776_777$min_mux$mux.data.out"], + ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write.0","inner_compute$umin_775_776_777$min_mux$mux.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -976,7 +976,7 @@ ["valid_pass_out","Bit"], ["hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["ratio_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute$const_p255__793":{ @@ -1016,8 +1016,8 @@ } }, "connections":[ - ["inner_compute$umin_792_793_794$ucomp$compop.data.in.1","inner_compute$const_p255__793.out"], - ["inner_compute$umin_792_793_794$min_mux$mux.data.in.1","inner_compute$const_p255__7931.out"], + ["inner_compute$umin_792_793_794$min_mux$mux.data.in.1","inner_compute$const_p255__793.out"], + ["inner_compute$umin_792_793_794$ucomp$compop.data.in.1","inner_compute$const_p255__7931.out"], ["inner_compute$lshr_790_791_792$binop.data.in.1","inner_compute$const_p5__791.out"], ["inner_compute$mul_ratio_stencil_2_hw_input_global_wrapper_stencil_5_790$binop.data.out","inner_compute$lshr_790_791_792$binop.data.in.0"], ["inner_compute$umin_792_793_794$min_mux$mux.data.in.0","inner_compute$lshr_790_791_792$binop.data.out"], @@ -1025,7 +1025,7 @@ ["self.ratio_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute$mul_ratio_stencil_2_hw_input_global_wrapper_stencil_5_790$binop.data.in.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute$mul_ratio_stencil_2_hw_input_global_wrapper_stencil_5_790$binop.data.in.1"], ["inner_compute$umin_792_793_794$ucomp$compop.bit.out","inner_compute$umin_792_793_794$min_mux$mux.bit.in.0"], - ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write.0","inner_compute$umin_792_793_794$min_mux$mux.data.out"], + ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write.0","inner_compute$umin_792_793_794$min_mux$mux.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1036,7 +1036,7 @@ ["valid_pass_out","Bit"], ["hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], ["ratio_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ "inner_compute$const_p255__810":{ @@ -1085,7 +1085,7 @@ ["self.ratio_stencil_op_hcompute_hw_output_stencil_2_read.0","inner_compute$mul_ratio_stencil_3_hw_input_global_wrapper_stencil_6_807$binop.data.in.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_output_stencil_2_read.0","inner_compute$mul_ratio_stencil_3_hw_input_global_wrapper_stencil_6_807$binop.data.in.1"], ["inner_compute$umin_809_810_811$ucomp$compop.bit.out","inner_compute$umin_809_810_811$min_mux$mux.bit.in.0"], - ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write.0","inner_compute$umin_809_810_811$min_mux$mux.data.out"], + ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write.0","inner_compute$umin_809_810_811$min_mux$mux.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -1241,14 +1241,6 @@ ["op_hcompute_ratio_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "d_reg__U10$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, @@ -1299,22 +1291,22 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U20$reg0":{ + "d_reg__U2$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U21$reg0":{ + "d_reg__U20$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U22$reg0":{ + "d_reg__U21$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "d_reg__U23$reg0":{ + "d_reg__U3$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -1356,7 +1348,7 @@ }, "ub_gray_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[190],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[253],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[192],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[256],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_gray_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -1366,72 +1358,72 @@ }, "ub_gray_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ ["self.clk","d_reg__U10$reg0.clk"], - ["d_reg__U9$reg0.out","d_reg__U10$reg0.in"], + ["ub_gray_stencil_BANK_1_garnet.data_out_0","d_reg__U10$reg0.in"], ["d_reg__U11$reg0.in","d_reg__U10$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U10$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.5","d_reg__U10$reg0.out"], ["self.clk","d_reg__U11$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.7","d_reg__U11$reg0.out"], + ["d_reg__U12$reg0.in","d_reg__U11$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U11$reg0.out"], + ["self.op_hcompute_ratio_stencil_read.0","d_reg__U11$reg0.out"], ["self.clk","d_reg__U12$reg0.clk"], - ["ub_gray_stencil_BANK_1_garnet.data_out_0","d_reg__U12$reg0.in"], ["d_reg__U13$reg0.in","d_reg__U12$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.5","d_reg__U12$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U12$reg0.out"], ["self.clk","d_reg__U13$reg0.clk"], - ["d_reg__U14$reg0.in","d_reg__U13$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.4","d_reg__U13$reg0.out"], - ["self.op_hcompute_ratio_stencil_read.0","d_reg__U13$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.2","d_reg__U13$reg0.out"], ["self.clk","d_reg__U14$reg0.clk"], + ["ub_gray_stencil_BANK_0_garnet.data_out_0","d_reg__U14$reg0.in"], ["d_reg__U15$reg0.in","d_reg__U14$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.3","d_reg__U14$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.24","d_reg__U14$reg0.out"], ["self.clk","d_reg__U15$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.2","d_reg__U15$reg0.out"], + ["d_reg__U16$reg0.in","d_reg__U15$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.23","d_reg__U15$reg0.out"], ["self.clk","d_reg__U16$reg0.clk"], - ["ub_gray_stencil_BANK_0_garnet.data_out_0","d_reg__U16$reg0.in"], ["d_reg__U17$reg0.in","d_reg__U16$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.24","d_reg__U16$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.22","d_reg__U16$reg0.out"], ["self.clk","d_reg__U17$reg0.clk"], - ["d_reg__U18$reg0.in","d_reg__U17$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.23","d_reg__U17$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.21","d_reg__U17$reg0.out"], ["self.clk","d_reg__U18$reg0.clk"], + ["ub_gray_stencil_BANK_0_garnet.data_out_1","d_reg__U18$reg0.in"], ["d_reg__U19$reg0.in","d_reg__U18$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.22","d_reg__U18$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.19","d_reg__U18$reg0.out"], ["self.clk","d_reg__U19$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.21","d_reg__U19$reg0.out"], + ["d_reg__U20$reg0.in","d_reg__U19$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.18","d_reg__U19$reg0.out"], + ["self.clk","d_reg__U2$reg0.clk"], + ["self.op_hcompute_gray_stencil_write.0","d_reg__U2$reg0.in"], + ["d_reg__U3$reg0.in","d_reg__U2$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.16","d_reg__U2$reg0.out"], ["self.clk","d_reg__U20$reg0.clk"], - ["ub_gray_stencil_BANK_0_garnet.data_out_1","d_reg__U20$reg0.in"], ["d_reg__U21$reg0.in","d_reg__U20$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.19","d_reg__U20$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.11","d_reg__U20$reg0.out"], ["self.clk","d_reg__U21$reg0.clk"], - ["d_reg__U22$reg0.in","d_reg__U21$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.18","d_reg__U21$reg0.out"], - ["self.clk","d_reg__U22$reg0.clk"], - ["d_reg__U23$reg0.in","d_reg__U22$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.11","d_reg__U22$reg0.out"], - ["self.clk","d_reg__U23$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U23$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.0","d_reg__U21$reg0.out"], + ["self.clk","d_reg__U3$reg0.clk"], + ["d_reg__U4$reg0.in","d_reg__U3$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.15","d_reg__U3$reg0.out"], ["self.clk","d_reg__U4$reg0.clk"], - ["self.op_hcompute_gray_stencil_write.0","d_reg__U4$reg0.in"], ["d_reg__U5$reg0.in","d_reg__U4$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.16","d_reg__U4$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.14","d_reg__U4$reg0.out"], ["self.clk","d_reg__U5$reg0.clk"], - ["d_reg__U6$reg0.in","d_reg__U5$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.15","d_reg__U5$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.13","d_reg__U5$reg0.out"], ["self.clk","d_reg__U6$reg0.clk"], + ["ub_gray_stencil_BANK_1_garnet.data_out_1","d_reg__U6$reg0.in"], ["d_reg__U7$reg0.in","d_reg__U6$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.14","d_reg__U6$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.10","d_reg__U6$reg0.out"], ["self.clk","d_reg__U7$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.13","d_reg__U7$reg0.out"], + ["d_reg__U8$reg0.in","d_reg__U7$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.9","d_reg__U7$reg0.out"], ["self.clk","d_reg__U8$reg0.clk"], - ["ub_gray_stencil_BANK_1_garnet.data_out_1","d_reg__U8$reg0.in"], ["d_reg__U9$reg0.in","d_reg__U8$reg0.out"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.10","d_reg__U8$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.8","d_reg__U8$reg0.out"], ["self.clk","d_reg__U9$reg0.clk"], - ["self.op_hcompute_blur_unnormalized_stencil_1_read.9","d_reg__U9$reg0.out"], + ["self.op_hcompute_blur_unnormalized_stencil_1_read.7","d_reg__U9$reg0.out"], ["ub_gray_stencil_BANK_0_garnet.clk","self.clk"], ["ub_gray_stencil_BANK_1_garnet.clk","self.clk"], ["ub_gray_stencil_BANK_1_garnet.data_out_1","self.op_hcompute_blur_unnormalized_stencil_1_read.12"], @@ -1452,26 +1444,26 @@ ["out_blur_unnormalized_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U62":{ + "PE_init_U57":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U60":{ + "_U55":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U61":{ + "_U56":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U60.out","PE_init_U62.data.in.0"], - ["_U61.out","PE_init_U62.data.in.1"], - ["self.out_blur_unnormalized_stencil","PE_init_U62.data.out"] + ["_U55.out","PE_init_U57.data.in.0"], + ["_U56.out","PE_init_U57.data.in.1"], + ["self.out_blur_unnormalized_stencil","PE_init_U57.data.out"] ] }, "hcompute_blur_unnormalized_stencil_1":{ @@ -2385,18 +2377,6 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2404,7 +2384,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -2414,7 +2394,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -2424,7 +2404,7 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -2449,7 +2429,7 @@ ["ub_hw_input_global_wrapper_stencil_BANK_2_garnet.clk_en","ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U49":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U44":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2458,7 +2438,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U48":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U43":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2467,7 +2447,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U50":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U45":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2476,7 +2456,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U44":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U39":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2485,7 +2465,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U43":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2494,7 +2474,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U45":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2503,7 +2483,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U54":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U49":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2512,7 +2492,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U53":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U48":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2521,7 +2501,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U55":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U50":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2530,7 +2510,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_exe_start_pt__U36":{ + "op_hcompute_hw_output_stencil_1_exe_start_pt__U31":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2539,7 +2519,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_read_start_pt__U35":{ + "op_hcompute_hw_output_stencil_1_read_start_pt__U30":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2548,7 +2528,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_1_write_start_pt__U37":{ + "op_hcompute_hw_output_stencil_1_write_start_pt__U32":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2557,7 +2537,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_exe_start_pt__U32":{ + "op_hcompute_hw_output_stencil_2_exe_start_pt__U27":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2566,7 +2546,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_read_start_pt__U31":{ + "op_hcompute_hw_output_stencil_2_read_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2575,7 +2555,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_2_write_start_pt__U33":{ + "op_hcompute_hw_output_stencil_2_write_start_pt__U28":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2584,7 +2564,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U40":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U35":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2593,7 +2573,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U39":{ + "op_hcompute_hw_output_stencil_read_start_pt__U34":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2602,7 +2582,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U41":{ + "op_hcompute_hw_output_stencil_write_start_pt__U36":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -2641,22 +2621,14 @@ ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write_valid","Bit"], - ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write_valid","Bit"], - ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], - ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write_valid","Bit"], - ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_valid","Bit"], + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_valid","Bit"], + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "gray_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "gray_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "gray_stencil$d_reg__U10$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, @@ -2707,22 +2679,22 @@ "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "gray_stencil$d_reg__U20$reg0":{ + "gray_stencil$d_reg__U2$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "gray_stencil$d_reg__U21$reg0":{ + "gray_stencil$d_reg__U20$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "gray_stencil$d_reg__U22$reg0":{ + "gray_stencil$d_reg__U21$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} }, - "gray_stencil$d_reg__U23$reg0":{ + "gray_stencil$d_reg__U3$reg0":{ "genref":"coreir.reg", "genargs":{"width":["Int",16]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"16'h0000"]} @@ -2764,7 +2736,7 @@ }, "gray_stencil$ub_gray_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[190],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[253],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[192],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[256],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "gray_stencil$ub_gray_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -2774,21 +2746,9 @@ }, "gray_stencil$ub_gray_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[126],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[61],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[128],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]},"tb2out_1":{"cycle_starting_addr":[64],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "hw_input_global_wrapper_stencil$chain_en_const_U25":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U27":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U29":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -2796,7 +2756,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ @@ -2806,7 +2766,7 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ @@ -2816,22 +2776,22 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U24"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[127],"cycle_stride":[4,64],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,16],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[130],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,64],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, - "io16_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write_0":{ + "io16_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, "metadata":{"in2glb_0":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,60]}} }, - "io16_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write_0":{ + "io16_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, "metadata":{"in2glb_0":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60],"write_data_starting_addr":[0],"write_data_stride":[1,60]}} }, - "io16_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write_0":{ + "io16_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, @@ -2855,15 +2815,15 @@ "modargs":{"mode":["String","in"]}, "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[4096],"read_data_starting_addr":[0],"read_data_stride":[1]}} }, - "io1_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write_valid":{ + "io1_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, - "io1_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write_valid":{ + "io1_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, - "io1_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write_valid":{ + "io1_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_valid":{ "modref":"cgralib.BitIO", "modargs":{"mode":["String","out"]} }, @@ -3378,7 +3338,7 @@ }, "op_hcompute_hw_output_stencil_1_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U29"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_2$inner_compute$const_p255__810":{ @@ -3423,7 +3383,7 @@ }, "op_hcompute_hw_output_stencil_2_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ @@ -3433,7 +3393,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U38"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U33"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[260],"cycle_stride":[1,64],"dimensionality":2,"extent":[60,60]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_ratio_stencil$inner_compute$ashr_blur_unnormalized_stencil_2_729_730$binop":{ @@ -3537,48 +3497,48 @@ } }, "connections":[ - ["gray_stencil$d_reg__U9$reg0.out","gray_stencil$d_reg__U10$reg0.in"], + ["gray_stencil$ub_gray_stencil_BANK_1_garnet.data_out_0","gray_stencil$d_reg__U10$reg0.in"], ["gray_stencil$d_reg__U11$reg0.in","gray_stencil$d_reg__U10$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_17_531_564$binop.data.in.0","gray_stencil$d_reg__U10$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_16_514_561$binop.data.in.0","gray_stencil$d_reg__U11$reg0.out"], - ["gray_stencil$ub_gray_stencil_BANK_1_garnet.data_out_0","gray_stencil$d_reg__U12$reg0.in"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_14_535_555$binop.data.in.0","gray_stencil$d_reg__U10$reg0.out"], + ["gray_stencil$d_reg__U12$reg0.in","gray_stencil$d_reg__U11$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_13_551_552$binop.data.in.0","gray_stencil$d_reg__U11$reg0.out"], + ["op_hcompute_ratio_stencil$inner_compute$mul_726_727_728$binop.data.in.0","gray_stencil$d_reg__U11$reg0.out"], + ["op_hcompute_ratio_stencil$inner_compute$umax_gray_stencil_26_741_742$cgramax.data.in.0","gray_stencil$d_reg__U11$reg0.out"], ["gray_stencil$d_reg__U13$reg0.in","gray_stencil$d_reg__U12$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_14_535_555$binop.data.in.0","gray_stencil$d_reg__U12$reg0.out"], - ["gray_stencil$d_reg__U14$reg0.in","gray_stencil$d_reg__U13$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_13_551_552$binop.data.in.0","gray_stencil$d_reg__U13$reg0.out"], - ["op_hcompute_ratio_stencil$inner_compute$mul_726_727_728$binop.data.in.0","gray_stencil$d_reg__U13$reg0.out"], - ["op_hcompute_ratio_stencil$inner_compute$umax_gray_stencil_26_741_742$cgramax.data.in.0","gray_stencil$d_reg__U13$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_12_535_548$binop.data.in.0","gray_stencil$d_reg__U12$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_11_518_545$binop.data.in.0","gray_stencil$d_reg__U13$reg0.out"], + ["gray_stencil$ub_gray_stencil_BANK_0_garnet.data_out_0","gray_stencil$d_reg__U14$reg0.in"], ["gray_stencil$d_reg__U15$reg0.in","gray_stencil$d_reg__U14$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_12_535_548$binop.data.in.0","gray_stencil$d_reg__U14$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_11_518_545$binop.data.in.0","gray_stencil$d_reg__U15$reg0.out"], - ["gray_stencil$ub_gray_stencil_BANK_0_garnet.data_out_0","gray_stencil$d_reg__U16$reg0.in"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_9_531_539$binop.data.in.0","gray_stencil$d_reg__U14$reg0.out"], + ["gray_stencil$d_reg__U16$reg0.in","gray_stencil$d_reg__U15$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_8_535_536$binop.data.in.0","gray_stencil$d_reg__U15$reg0.out"], ["gray_stencil$d_reg__U17$reg0.in","gray_stencil$d_reg__U16$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_9_531_539$binop.data.in.0","gray_stencil$d_reg__U16$reg0.out"], - ["gray_stencil$d_reg__U18$reg0.in","gray_stencil$d_reg__U17$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_8_535_536$binop.data.in.0","gray_stencil$d_reg__U17$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_7_531_532$binop.data.in.0","gray_stencil$d_reg__U16$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_6_514_528$binop.data.in.0","gray_stencil$d_reg__U17$reg0.out"], + ["gray_stencil$ub_gray_stencil_BANK_0_garnet.data_out_1","gray_stencil$d_reg__U18$reg0.in"], ["gray_stencil$d_reg__U19$reg0.in","gray_stencil$d_reg__U18$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_7_531_532$binop.data.in.0","gray_stencil$d_reg__U18$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_6_514_528$binop.data.in.0","gray_stencil$d_reg__U19$reg0.out"], - ["gray_stencil$ub_gray_stencil_BANK_0_garnet.data_out_1","gray_stencil$d_reg__U20$reg0.in"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_4_514_522$binop.data.in.0","gray_stencil$d_reg__U18$reg0.out"], + ["gray_stencil$d_reg__U20$reg0.in","gray_stencil$d_reg__U19$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_3_518_519$binop.data.in.0","gray_stencil$d_reg__U19$reg0.out"], + ["op_hcompute_gray_stencil$inner_compute$lshr_410_411_412$binop.data.out","gray_stencil$d_reg__U2$reg0.in"], + ["gray_stencil$d_reg__U3$reg0.in","gray_stencil$d_reg__U2$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_24_514_585$binop.data.in.0","gray_stencil$d_reg__U2$reg0.out"], ["gray_stencil$d_reg__U21$reg0.in","gray_stencil$d_reg__U20$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_4_514_522$binop.data.in.0","gray_stencil$d_reg__U20$reg0.out"], - ["gray_stencil$d_reg__U22$reg0.in","gray_stencil$d_reg__U21$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_3_518_519$binop.data.in.0","gray_stencil$d_reg__U21$reg0.out"], - ["gray_stencil$d_reg__U23$reg0.in","gray_stencil$d_reg__U22$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_2_514_515$binop.data.in.0","gray_stencil$d_reg__U22$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_1_510_511$binop.data.in.0","gray_stencil$d_reg__U23$reg0.out"], - ["op_hcompute_gray_stencil$inner_compute$lshr_410_411_412$binop.data.out","gray_stencil$d_reg__U4$reg0.in"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_2_514_515$binop.data.in.0","gray_stencil$d_reg__U20$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_1_510_511$binop.data.in.0","gray_stencil$d_reg__U21$reg0.out"], + ["gray_stencil$d_reg__U4$reg0.in","gray_stencil$d_reg__U3$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_23_518_582$binop.data.in.0","gray_stencil$d_reg__U3$reg0.out"], ["gray_stencil$d_reg__U5$reg0.in","gray_stencil$d_reg__U4$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_24_514_585$binop.data.in.0","gray_stencil$d_reg__U4$reg0.out"], - ["gray_stencil$d_reg__U6$reg0.in","gray_stencil$d_reg__U5$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_23_518_582$binop.data.in.0","gray_stencil$d_reg__U5$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_22_514_579$binop.data.in.0","gray_stencil$d_reg__U4$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_21_510_576$binop.data.in.0","gray_stencil$d_reg__U5$reg0.out"], + ["gray_stencil$ub_gray_stencil_BANK_1_garnet.data_out_1","gray_stencil$d_reg__U6$reg0.in"], ["gray_stencil$d_reg__U7$reg0.in","gray_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_22_514_579$binop.data.in.0","gray_stencil$d_reg__U6$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_21_510_576$binop.data.in.0","gray_stencil$d_reg__U7$reg0.out"], - ["gray_stencil$ub_gray_stencil_BANK_1_garnet.data_out_1","gray_stencil$d_reg__U8$reg0.in"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_19_531_570$binop.data.in.0","gray_stencil$d_reg__U6$reg0.out"], + ["gray_stencil$d_reg__U8$reg0.in","gray_stencil$d_reg__U7$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_18_535_567$binop.data.in.0","gray_stencil$d_reg__U7$reg0.out"], ["gray_stencil$d_reg__U9$reg0.in","gray_stencil$d_reg__U8$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_19_531_570$binop.data.in.0","gray_stencil$d_reg__U8$reg0.out"], - ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_18_535_567$binop.data.in.0","gray_stencil$d_reg__U9$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_17_531_564$binop.data.in.0","gray_stencil$d_reg__U8$reg0.out"], + ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_16_514_561$binop.data.in.0","gray_stencil$d_reg__U9$reg0.out"], ["gray_stencil$ub_gray_stencil_BANK_0_garnet.clk_en","gray_stencil$ub_gray_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_gray_stencil$inner_compute$lshr_410_411_412$binop.data.out","gray_stencil$ub_gray_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_blur_unnormalized_stencil_1$inner_compute$mul_gray_stencil_10_514_542$binop.data.in.0","gray_stencil$ub_gray_stencil_BANK_0_garnet.data_out_0"], @@ -3601,15 +3561,15 @@ ["io16in_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_in_0"], ["op_hcompute_hw_output_stencil_2$inner_compute$mul_ratio_stencil_3_hw_input_global_wrapper_stencil_6_807$binop.data.in.1","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_2_garnet.flush"], - ["op_hcompute_hw_output_stencil_2$inner_compute$umin_809_810_811$min_mux$mux.data.out","io16_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write_0.in"], - ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$min_mux$mux.data.out","io16_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write_0.in"], - ["op_hcompute_hw_output_stencil_1$inner_compute$umin_792_793_794$min_mux$mux.data.out","io16_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write_0.in"], + ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$min_mux$mux.data.out","io16_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_0.in"], + ["op_hcompute_hw_output_stencil_1$inner_compute$umin_792_793_794$min_mux$mux.data.out","io16_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_0.in"], + ["op_hcompute_hw_output_stencil_2$inner_compute$umin_809_810_811$min_mux$mux.data.out","io16_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_0.in"], ["op_hcompute_gray_stencil$inner_compute$mul_hw_input_global_wrapper_stencil_3_407_408$binop.data.in.0","io16in_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_0.out"], ["op_hcompute_gray_stencil$inner_compute$mul_hw_input_global_wrapper_stencil_1_403_404$binop.data.in.0","io16in_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_0.out"], ["op_hcompute_gray_stencil$inner_compute$mul_hw_input_global_wrapper_stencil_2_405_406$binop.data.in.0","io16in_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_0.out"], - ["op_hcompute_hw_output_stencil_2_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_2_write_valid.in"], - ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_write_valid.in"], - ["op_hcompute_hw_output_stencil_1_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_1_write_valid.in"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_valid.in"], + ["op_hcompute_hw_output_stencil_1_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_valid.in"], + ["op_hcompute_hw_output_stencil_2_port_controller_garnet.stencil_valid","io1_hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_valid.in"], ["op_hcompute_hw_output_stencil_1_port_controller_garnet.flush","io1in_reset.out"], ["op_hcompute_hw_output_stencil_2_port_controller_garnet.flush","io1in_reset.out"], ["op_hcompute_hw_output_stencil_port_controller_garnet.flush","io1in_reset.out"], @@ -3699,16 +3659,16 @@ ["op_hcompute_gray_stencil$inner_compute$mul_hw_input_global_wrapper_stencil_2_405_406$binop.data.in.1","op_hcompute_gray_stencil$inner_compute$const_p29__405.out"], ["op_hcompute_gray_stencil$inner_compute$mul_hw_input_global_wrapper_stencil_3_407_408$binop.data.in.1","op_hcompute_gray_stencil$inner_compute$const_p77__407.out"], ["op_hcompute_gray_stencil$inner_compute$lshr_410_411_412$binop.data.in.1","op_hcompute_gray_stencil$inner_compute$const_p8__411.out"], - ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$ucomp$compop.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p255__776.out"], - ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$min_mux$mux.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p255__7761.out"], + ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$min_mux$mux.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p255__776.out"], + ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$ucomp$compop.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p255__7761.out"], ["op_hcompute_hw_output_stencil$inner_compute$lshr_773_774_775$binop.data.in.1","op_hcompute_hw_output_stencil$inner_compute$const_p5__774.out"], ["op_hcompute_hw_output_stencil$inner_compute$mul_ratio_stencil_1_hw_input_global_wrapper_stencil_4_773$binop.data.out","op_hcompute_hw_output_stencil$inner_compute$lshr_773_774_775$binop.data.in.0"], ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$min_mux$mux.data.in.0","op_hcompute_hw_output_stencil$inner_compute$lshr_773_774_775$binop.data.out"], ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$ucomp$compop.data.in.0","op_hcompute_hw_output_stencil$inner_compute$lshr_773_774_775$binop.data.out"], ["op_hcompute_ratio_stencil$inner_compute$umin_743_744_745$min_mux$mux.data.out","op_hcompute_hw_output_stencil$inner_compute$mul_ratio_stencil_1_hw_input_global_wrapper_stencil_4_773$binop.data.in.0"], ["op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$ucomp$compop.bit.out","op_hcompute_hw_output_stencil$inner_compute$umin_775_776_777$min_mux$mux.bit.in.0"], - ["op_hcompute_hw_output_stencil_1$inner_compute$umin_792_793_794$ucomp$compop.data.in.1","op_hcompute_hw_output_stencil_1$inner_compute$const_p255__793.out"], - ["op_hcompute_hw_output_stencil_1$inner_compute$umin_792_793_794$min_mux$mux.data.in.1","op_hcompute_hw_output_stencil_1$inner_compute$const_p255__7931.out"], + ["op_hcompute_hw_output_stencil_1$inner_compute$umin_792_793_794$min_mux$mux.data.in.1","op_hcompute_hw_output_stencil_1$inner_compute$const_p255__793.out"], + ["op_hcompute_hw_output_stencil_1$inner_compute$umin_792_793_794$ucomp$compop.data.in.1","op_hcompute_hw_output_stencil_1$inner_compute$const_p255__7931.out"], ["op_hcompute_hw_output_stencil_1$inner_compute$lshr_790_791_792$binop.data.in.1","op_hcompute_hw_output_stencil_1$inner_compute$const_p5__791.out"], ["op_hcompute_hw_output_stencil_1$inner_compute$mul_ratio_stencil_2_hw_input_global_wrapper_stencil_5_790$binop.data.out","op_hcompute_hw_output_stencil_1$inner_compute$lshr_790_791_792$binop.data.in.0"], ["op_hcompute_hw_output_stencil_1$inner_compute$umin_792_793_794$min_mux$mux.data.in.0","op_hcompute_hw_output_stencil_1$inner_compute$lshr_790_791_792$binop.data.out"], diff --git a/aha_garnet_design_new/up_sample/up_sample.json b/aha_garnet_design_new/up_sample/up_sample.json index e04830d65..111efd2d0 100644 --- a/aha_garnet_design_new/up_sample/up_sample.json +++ b/aha_garnet_design_new/up_sample/up_sample.json @@ -97,14 +97,10 @@ ["op_hcompute_nearest_neighbor_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[8,256],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[2,256],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[8,128,256],"dimensionality":3,"extent":[16,2,64],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[16],"cycle_stride":[1,2,128,256],"dimensionality":4,"extent":[2,64,2,64],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[8,256],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[2,256],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[8,128,256],"dimensionality":3,"extent":[16,2,64],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[16],"cycle_stride":[1,2,128,256],"dimensionality":4,"extent":[2,64,2,64],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,0]}},"mode":"lake"} }, "ub_hw_input_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -112,7 +108,6 @@ } }, "connections":[ - ["ub_hw_input_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], ["ub_hw_input_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_stencil_BANK_0.data_in_0","self.op_hcompute_hw_input_stencil_write.0"], ["ub_hw_input_stencil_BANK_0.data_out_0","self.op_hcompute_nearest_neighbor_stencil_read.0"], @@ -135,7 +130,7 @@ ["self.op_hcompute_nearest_neighbor_stencil_write.0","self.op_hcompute_hw_output_stencil_read.0"] ] }, - "op_hcompute_hw_input_stencil_exe_start_pt__U8":{ + "op_hcompute_hw_input_stencil_exe_start_pt__U7":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -144,7 +139,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_stencil_read_start_pt__U7":{ + "op_hcompute_hw_input_stencil_read_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -153,7 +148,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_stencil_write_start_pt__U9":{ + "op_hcompute_hw_input_stencil_write_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -162,7 +157,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U4":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U3":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -171,7 +166,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U3":{ + "op_hcompute_hw_output_stencil_read_start_pt__U2":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -180,7 +175,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U5":{ + "op_hcompute_hw_output_stencil_write_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -199,7 +194,7 @@ ["input_copy_stencil_op_hcompute_hw_input_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U10":{ + "_U9":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -214,51 +209,51 @@ "modref":"global.cu_op_hcompute_hw_input_stencil" }, "op_hcompute_hw_input_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_stencil_exe_start_pt__U8" + "modref":"global.op_hcompute_hw_input_stencil_exe_start_pt__U7" }, "op_hcompute_hw_input_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[2,256],"dimensionality":2,"extent":[64,64]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U6"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[2,256],"dimensionality":2,"extent":[64,64]}},"mode":"lake"} }, "op_hcompute_hw_input_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_stencil_read_start_pt__U7" + "modref":"global.op_hcompute_hw_input_stencil_read_start_pt__U6" }, "op_hcompute_hw_input_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_stencil_write_start_pt__U9" + "modref":"global.op_hcompute_hw_input_stencil_write_start_pt__U8" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U4" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U3" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[16],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[16],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U3" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U2" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U5" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U4" }, "op_hcompute_nearest_neighbor_stencil":{ "modref":"global.cu_op_hcompute_nearest_neighbor_stencil" } }, "connections":[ - ["self.clk","_U10.clk"], - ["self.input_copy_stencil_op_hcompute_hw_input_stencil_read.0","_U10.in"], + ["self.clk","_U9.clk"], + ["self.input_copy_stencil_op_hcompute_hw_input_stencil_read.0","_U9.in"], ["self.clk","hw_input_stencil.clk"], ["op_hcompute_hw_input_stencil.hw_input_stencil_op_hcompute_hw_input_stencil_write","hw_input_stencil.op_hcompute_hw_input_stencil_write"], ["op_hcompute_nearest_neighbor_stencil.hw_input_stencil_op_hcompute_nearest_neighbor_stencil_read","hw_input_stencil.op_hcompute_nearest_neighbor_stencil_read"], diff --git a/aha_garnet_design_new/up_sample/up_sample_garnet.json b/aha_garnet_design_new/up_sample/up_sample_garnet.json index dec409577..d16a99ec0 100644 --- a/aha_garnet_design_new/up_sample/up_sample_garnet.json +++ b/aha_garnet_design_new/up_sample/up_sample_garnet.json @@ -220,10 +220,6 @@ ["op_hcompute_nearest_neighbor_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -231,7 +227,7 @@ }, "ub_hw_input_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[8,256],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[2,256],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[8,128,256],"dimensionality":3,"extent":[16,2,64],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[16],"cycle_stride":[1,2,128,256],"dimensionality":4,"extent":[2,64,2,64],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -257,7 +253,7 @@ ["self.op_hcompute_nearest_neighbor_stencil_write.0","self.op_hcompute_hw_output_stencil_read.0"] ] }, - "op_hcompute_hw_input_stencil_exe_start_pt__U8":{ + "op_hcompute_hw_input_stencil_exe_start_pt__U7":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -266,7 +262,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_stencil_read_start_pt__U7":{ + "op_hcompute_hw_input_stencil_read_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -275,7 +271,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_stencil_write_start_pt__U9":{ + "op_hcompute_hw_input_stencil_write_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -284,7 +280,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U4":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U3":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -293,7 +289,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U3":{ + "op_hcompute_hw_output_stencil_read_start_pt__U2":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -302,7 +298,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U5":{ + "op_hcompute_hw_output_stencil_write_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -321,10 +317,6 @@ ["input_copy_stencil_op_hcompute_hw_input_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "hw_input_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_input_stencil$ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -332,7 +324,7 @@ }, "hw_input_stencil$ub_hw_input_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[7],"cycle_stride":[8,256],"dimensionality":2,"extent":[16,64],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[2,256],"dimensionality":2,"extent":[64,64],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[14],"cycle_stride":[8,128,256],"dimensionality":3,"extent":[16,2,64],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[16],"cycle_stride":[1,2,128,256],"dimensionality":4,"extent":[2,64,2,64],"read_data_starting_addr":[0],"read_data_stride":[0,1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -362,7 +354,7 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[16],"cycle_stride":[1,128],"dimensionality":2,"extent":[128,128]}}], "init":["Json",null], "mode":["String","lake"]} } }, diff --git a/aha_garnet_design_new/up_sample_glb/up_sample_glb.json b/aha_garnet_design_new/up_sample_glb/up_sample_glb.json index 39f61a7e2..003f1dcca 100644 --- a/aha_garnet_design_new/up_sample_glb/up_sample_glb.json +++ b/aha_garnet_design_new/up_sample_glb/up_sample_glb.json @@ -723,22 +723,10 @@ ["op_hcompute_nearest_neighbor_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -746,8 +734,8 @@ }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -755,8 +743,8 @@ }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake","verilog_name":"lake__U4"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -764,9 +752,6 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1.chain_chain_en","chain_en_const_U3.out"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2.chain_chain_en","chain_en_const_U5.out"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1.clk","self.clk"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2.clk","self.clk"], @@ -776,9 +761,9 @@ ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1.data_out_0","self.op_hcompute_nearest_neighbor_stencil_1_read.0"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2.data_out_0","self.op_hcompute_nearest_neighbor_stencil_2_read.0"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_nearest_neighbor_stencil_3_read.0"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1.data_out_1","self.op_hcompute_nearest_neighbor_stencil_4_read.0"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2.data_out_1","self.op_hcompute_nearest_neighbor_stencil_5_read.0"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0.data_out_1","self.op_hcompute_nearest_neighbor_stencil_read.0"], + ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1.data_out_0","self.op_hcompute_nearest_neighbor_stencil_4_read.0"], + ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2.data_out_0","self.op_hcompute_nearest_neighbor_stencil_5_read.0"], + ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_nearest_neighbor_stencil_read.0"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0.flush","self.reset"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1.flush","self.reset"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2.flush","self.reset"], @@ -868,7 +853,7 @@ ["self.op_hcompute_nearest_neighbor_stencil_write.0","self.op_hcompute_hw_output_glb_stencil_read.0"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_1_exe_start_pt__U37":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_1_exe_start_pt__U34":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -877,7 +862,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_start_pt__U36":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_start_pt__U33":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -886,7 +871,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_1_write_start_pt__U38":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_1_write_start_pt__U35":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -895,7 +880,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_2_exe_start_pt__U32":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_2_exe_start_pt__U29":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -904,7 +889,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_start_pt__U31":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_start_pt__U28":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -913,7 +898,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_2_write_start_pt__U33":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_2_write_start_pt__U30":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -922,7 +907,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_exe_start_pt__U42":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_exe_start_pt__U39":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -931,7 +916,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_read_start_pt__U41":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_read_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -940,7 +925,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_write_start_pt__U43":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_write_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -949,7 +934,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_1_exe_start_pt__U24":{ + "op_hcompute_hw_output_global_wrapper_stencil_1_exe_start_pt__U21":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -958,7 +943,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_1_read_start_pt__U23":{ + "op_hcompute_hw_output_global_wrapper_stencil_1_read_start_pt__U20":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -967,7 +952,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_1_write_start_pt__U25":{ + "op_hcompute_hw_output_global_wrapper_stencil_1_write_start_pt__U22":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -976,7 +961,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_2_exe_start_pt__U20":{ + "op_hcompute_hw_output_global_wrapper_stencil_2_exe_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -985,7 +970,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_2_read_start_pt__U19":{ + "op_hcompute_hw_output_global_wrapper_stencil_2_read_start_pt__U16":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -994,7 +979,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_2_write_start_pt__U21":{ + "op_hcompute_hw_output_global_wrapper_stencil_2_write_start_pt__U18":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1003,7 +988,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_3_exe_start_pt__U16":{ + "op_hcompute_hw_output_global_wrapper_stencil_3_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1012,7 +997,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_3_read_start_pt__U15":{ + "op_hcompute_hw_output_global_wrapper_stencil_3_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1021,7 +1006,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_3_write_start_pt__U17":{ + "op_hcompute_hw_output_global_wrapper_stencil_3_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1030,7 +1015,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_4_exe_start_pt__U12":{ + "op_hcompute_hw_output_global_wrapper_stencil_4_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1039,7 +1024,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_4_read_start_pt__U11":{ + "op_hcompute_hw_output_global_wrapper_stencil_4_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1048,7 +1033,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_4_write_start_pt__U13":{ + "op_hcompute_hw_output_global_wrapper_stencil_4_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1057,7 +1042,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_5_exe_start_pt__U8":{ + "op_hcompute_hw_output_global_wrapper_stencil_5_exe_start_pt__U5":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1066,7 +1051,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_5_read_start_pt__U7":{ + "op_hcompute_hw_output_global_wrapper_stencil_5_read_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1075,7 +1060,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_5_write_start_pt__U9":{ + "op_hcompute_hw_output_global_wrapper_stencil_5_write_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1084,7 +1069,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_exe_start_pt__U28":{ + "op_hcompute_hw_output_global_wrapper_stencil_exe_start_pt__U25":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1093,7 +1078,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_read_start_pt__U27":{ + "op_hcompute_hw_output_global_wrapper_stencil_read_start_pt__U24":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1102,7 +1087,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_write_start_pt__U29":{ + "op_hcompute_hw_output_global_wrapper_stencil_write_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1135,17 +1120,17 @@ ["hw_output_global_wrapper_stencil_clkwrk_8_op_hcompute_hw_output_global_wrapper_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U34":{ + "_U31":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U39":{ + "_U36":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U44":{ + "_U41":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -1169,61 +1154,61 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_glb_stencil_1" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_1_exe_start_pt__U37" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_1_exe_start_pt__U34" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U35"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U35"} + "genargs":{"ID":["String","_U32"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_glb_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_start_pt__U36" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_start_pt__U33" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_1_write_start_pt__U38" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_1_write_start_pt__U35" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_2":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_glb_stencil_2" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_2_exe_start_pt__U32" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_2_exe_start_pt__U29" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U30"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U30"} + "genargs":{"ID":["String","_U27"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_glb_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_start_pt__U31" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_start_pt__U28" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_2_write_start_pt__U33" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_2_write_start_pt__U30" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_exe_start_pt__U42" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_exe_start_pt__U39" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U40"} + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_glb_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_glb_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_read_start_pt__U41" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_read_start_pt__U38" }, "op_hcompute_hw_input_global_wrapper_glb_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_write_start_pt__U43" + "modref":"global.op_hcompute_hw_input_global_wrapper_glb_stencil_write_start_pt__U40" }, "op_hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_global_wrapper_stencil" @@ -1259,124 +1244,124 @@ "modref":"global.cu_op_hcompute_hw_output_global_wrapper_stencil_1" }, "op_hcompute_hw_output_global_wrapper_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_1_exe_start_pt__U24" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_1_exe_start_pt__U21" }, "op_hcompute_hw_output_global_wrapper_stencil_1_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U22"} + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake"} }, "op_hcompute_hw_output_global_wrapper_stencil_1_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_global_wrapper_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_1_read_start_pt__U23" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_1_read_start_pt__U20" }, "op_hcompute_hw_output_global_wrapper_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_1_write_start_pt__U25" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_1_write_start_pt__U22" }, "op_hcompute_hw_output_global_wrapper_stencil_2":{ "modref":"global.cu_op_hcompute_hw_output_global_wrapper_stencil_2" }, "op_hcompute_hw_output_global_wrapper_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_2_exe_start_pt__U20" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_2_exe_start_pt__U17" }, "op_hcompute_hw_output_global_wrapper_stencil_2_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U18"} + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake"} }, "op_hcompute_hw_output_global_wrapper_stencil_2_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_global_wrapper_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_2_read_start_pt__U19" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_2_read_start_pt__U16" }, "op_hcompute_hw_output_global_wrapper_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_2_write_start_pt__U21" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_2_write_start_pt__U18" }, "op_hcompute_hw_output_global_wrapper_stencil_3":{ "modref":"global.cu_op_hcompute_hw_output_global_wrapper_stencil_3" }, "op_hcompute_hw_output_global_wrapper_stencil_3_exe_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_3_exe_start_pt__U16" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_3_exe_start_pt__U13" }, "op_hcompute_hw_output_global_wrapper_stencil_3_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U14"} + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake"} }, "op_hcompute_hw_output_global_wrapper_stencil_3_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_global_wrapper_stencil_3_read_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_3_read_start_pt__U15" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_3_read_start_pt__U12" }, "op_hcompute_hw_output_global_wrapper_stencil_3_write_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_3_write_start_pt__U17" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_3_write_start_pt__U14" }, "op_hcompute_hw_output_global_wrapper_stencil_4":{ "modref":"global.cu_op_hcompute_hw_output_global_wrapper_stencil_4" }, "op_hcompute_hw_output_global_wrapper_stencil_4_exe_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_4_exe_start_pt__U12" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_4_exe_start_pt__U9" }, "op_hcompute_hw_output_global_wrapper_stencil_4_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U10"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake"} }, "op_hcompute_hw_output_global_wrapper_stencil_4_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_global_wrapper_stencil_4_read_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_4_read_start_pt__U11" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_4_read_start_pt__U8" }, "op_hcompute_hw_output_global_wrapper_stencil_4_write_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_4_write_start_pt__U13" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_4_write_start_pt__U10" }, "op_hcompute_hw_output_global_wrapper_stencil_5":{ "modref":"global.cu_op_hcompute_hw_output_global_wrapper_stencil_5" }, "op_hcompute_hw_output_global_wrapper_stencil_5_exe_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_5_exe_start_pt__U8" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_5_exe_start_pt__U5" }, "op_hcompute_hw_output_global_wrapper_stencil_5_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U6"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake"} }, "op_hcompute_hw_output_global_wrapper_stencil_5_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_global_wrapper_stencil_5_read_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_5_read_start_pt__U7" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_5_read_start_pt__U4" }, "op_hcompute_hw_output_global_wrapper_stencil_5_write_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_5_write_start_pt__U9" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_5_write_start_pt__U6" }, "op_hcompute_hw_output_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_exe_start_pt__U28" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_exe_start_pt__U25" }, "op_hcompute_hw_output_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U26"} + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}},"mode":"lake"} }, "op_hcompute_hw_output_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_read_start_pt__U27" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_read_start_pt__U24" }, "op_hcompute_hw_output_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_write_start_pt__U29" + "modref":"global.op_hcompute_hw_output_global_wrapper_stencil_write_start_pt__U26" }, "op_hcompute_nearest_neighbor_stencil":{ "modref":"global.cu_op_hcompute_nearest_neighbor_stencil" @@ -1398,12 +1383,12 @@ } }, "connections":[ - ["self.clk","_U34.clk"], - ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_glb_stencil_2_read.0","_U34.in"], - ["self.clk","_U39.clk"], - ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_glb_stencil_1_read.0","_U39.in"], - ["self.clk","_U44.clk"], - ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_glb_stencil_read.0","_U44.in"], + ["self.clk","_U31.clk"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_glb_stencil_2_read.0","_U31.in"], + ["self.clk","_U36.clk"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_glb_stencil_1_read.0","_U36.in"], + ["self.clk","_U41.clk"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_glb_stencil_read.0","_U41.in"], ["self.clk","hw_input_global_wrapper_glb_stencil.clk"], ["op_hcompute_hw_input_global_wrapper_glb_stencil_1.hw_input_global_wrapper_glb_stencil_op_hcompute_hw_input_global_wrapper_glb_stencil_1_write","hw_input_global_wrapper_glb_stencil.op_hcompute_hw_input_global_wrapper_glb_stencil_1_write"], ["op_hcompute_hw_input_global_wrapper_glb_stencil_2.hw_input_global_wrapper_glb_stencil_op_hcompute_hw_input_global_wrapper_glb_stencil_2_write","hw_input_global_wrapper_glb_stencil.op_hcompute_hw_input_global_wrapper_glb_stencil_2_write"], diff --git a/aha_garnet_design_new/up_sample_glb/up_sample_glb_garnet.json b/aha_garnet_design_new/up_sample_glb/up_sample_glb_garnet.json index 66b01c94c..bed393a38 100644 --- a/aha_garnet_design_new/up_sample_glb/up_sample_glb_garnet.json +++ b/aha_garnet_design_new/up_sample_glb/up_sample_glb_garnet.json @@ -720,18 +720,6 @@ ["op_hcompute_nearest_neighbor_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -739,8 +727,8 @@ }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -749,8 +737,8 @@ }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -759,8 +747,8 @@ }, "ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -773,9 +761,9 @@ ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.data_out_0","self.op_hcompute_nearest_neighbor_stencil_1_read.0"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_nearest_neighbor_stencil_2_read.0"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_nearest_neighbor_stencil_3_read.0"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.data_out_1","self.op_hcompute_nearest_neighbor_stencil_4_read.0"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.data_out_1","self.op_hcompute_nearest_neighbor_stencil_5_read.0"], - ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.data_out_1","self.op_hcompute_nearest_neighbor_stencil_read.0"], + ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.data_out_0","self.op_hcompute_nearest_neighbor_stencil_4_read.0"], + ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.data_out_0","self.op_hcompute_nearest_neighbor_stencil_5_read.0"], + ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_nearest_neighbor_stencil_read.0"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.flush","self.reset"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.flush","self.reset"], ["ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.flush","self.reset"], @@ -862,7 +850,7 @@ ["self.op_hcompute_nearest_neighbor_stencil_write.0","self.op_hcompute_hw_output_glb_stencil_read.0"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_1_exe_start_pt__U37":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_1_exe_start_pt__U34":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -871,7 +859,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_start_pt__U36":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_start_pt__U33":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -880,7 +868,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_1_write_start_pt__U38":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_1_write_start_pt__U35":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -889,7 +877,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_2_exe_start_pt__U32":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_2_exe_start_pt__U29":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -898,7 +886,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_start_pt__U31":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_start_pt__U28":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -907,7 +895,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_2_write_start_pt__U33":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_2_write_start_pt__U30":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -916,7 +904,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_exe_start_pt__U42":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_exe_start_pt__U39":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -925,7 +913,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_read_start_pt__U41":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_read_start_pt__U38":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -934,7 +922,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_glb_stencil_write_start_pt__U43":{ + "op_hcompute_hw_input_global_wrapper_glb_stencil_write_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -943,7 +931,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_1_exe_start_pt__U24":{ + "op_hcompute_hw_output_global_wrapper_stencil_1_exe_start_pt__U21":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -952,7 +940,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_1_read_start_pt__U23":{ + "op_hcompute_hw_output_global_wrapper_stencil_1_read_start_pt__U20":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -961,7 +949,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_1_write_start_pt__U25":{ + "op_hcompute_hw_output_global_wrapper_stencil_1_write_start_pt__U22":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -970,7 +958,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_2_exe_start_pt__U20":{ + "op_hcompute_hw_output_global_wrapper_stencil_2_exe_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -979,7 +967,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_2_read_start_pt__U19":{ + "op_hcompute_hw_output_global_wrapper_stencil_2_read_start_pt__U16":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -988,7 +976,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_2_write_start_pt__U21":{ + "op_hcompute_hw_output_global_wrapper_stencil_2_write_start_pt__U18":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -997,7 +985,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_3_exe_start_pt__U16":{ + "op_hcompute_hw_output_global_wrapper_stencil_3_exe_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1006,7 +994,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_3_read_start_pt__U15":{ + "op_hcompute_hw_output_global_wrapper_stencil_3_read_start_pt__U12":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1015,7 +1003,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_3_write_start_pt__U17":{ + "op_hcompute_hw_output_global_wrapper_stencil_3_write_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1024,7 +1012,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_4_exe_start_pt__U12":{ + "op_hcompute_hw_output_global_wrapper_stencil_4_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1033,7 +1021,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_4_read_start_pt__U11":{ + "op_hcompute_hw_output_global_wrapper_stencil_4_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1042,7 +1030,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_4_write_start_pt__U13":{ + "op_hcompute_hw_output_global_wrapper_stencil_4_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1051,7 +1039,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_5_exe_start_pt__U8":{ + "op_hcompute_hw_output_global_wrapper_stencil_5_exe_start_pt__U5":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1060,7 +1048,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_5_read_start_pt__U7":{ + "op_hcompute_hw_output_global_wrapper_stencil_5_read_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1069,7 +1057,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_5_write_start_pt__U9":{ + "op_hcompute_hw_output_global_wrapper_stencil_5_write_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1078,7 +1066,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_exe_start_pt__U28":{ + "op_hcompute_hw_output_global_wrapper_stencil_exe_start_pt__U25":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1087,7 +1075,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_read_start_pt__U27":{ + "op_hcompute_hw_output_global_wrapper_stencil_read_start_pt__U24":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1096,7 +1084,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_global_wrapper_stencil_write_start_pt__U29":{ + "op_hcompute_hw_output_global_wrapper_stencil_write_start_pt__U26":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -1129,18 +1117,6 @@ ["hw_output_global_wrapper_stencil_clkwrk_8_op_hcompute_hw_output_global_wrapper_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "hw_input_global_wrapper_global_wrapper_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_global_wrapper_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, - "hw_input_global_wrapper_global_wrapper_stencil$chain_en_const_U5":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -1148,8 +1124,8 @@ }, "hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1158,8 +1134,8 @@ }, "hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -1168,8 +1144,8 @@ }, "hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_1":{"cycle_starting_addr":[5],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]},"tb2out_1":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,128],"dimensionality":2,"extent":[16,128],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,16]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,128],"dimensionality":2,"extent":[64,128],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[6],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[16,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[8],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[64,2,128],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_global_wrapper_stencil_clkwrk_3_op_hcompute_hw_output_global_wrapper_stencil_write_0":{ "genref":"cgralib.IO", @@ -1260,7 +1236,7 @@ }, "op_hcompute_hw_output_global_wrapper_stencil_1_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_global_wrapper_stencil_2_port_controller_clk_en_const_lutcnst":{ @@ -1270,7 +1246,7 @@ }, "op_hcompute_hw_output_global_wrapper_stencil_2_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U18"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U15"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_global_wrapper_stencil_3_port_controller_clk_en_const_lutcnst":{ @@ -1280,7 +1256,7 @@ }, "op_hcompute_hw_output_global_wrapper_stencil_3_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_global_wrapper_stencil_4_port_controller_clk_en_const_lutcnst":{ @@ -1290,7 +1266,7 @@ }, "op_hcompute_hw_output_global_wrapper_stencil_4_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_global_wrapper_stencil_5_port_controller_clk_en_const_lutcnst":{ @@ -1300,7 +1276,7 @@ }, "op_hcompute_hw_output_global_wrapper_stencil_5_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_global_wrapper_stencil_port_controller_clk_en_const_lutcnst":{ @@ -1310,25 +1286,25 @@ }, "op_hcompute_hw_output_global_wrapper_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U26"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U23"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8],"cycle_stride":[1,64],"dimensionality":2,"extent":[64,256]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ ["hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.clk_en","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_glb_stencil_read_0.out","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.data_in_0"], + ["io16_hw_output_global_wrapper_stencil_clkwrk_3_op_hcompute_hw_output_global_wrapper_stencil_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.data_out_0"], ["io16_hw_output_global_wrapper_stencil_clkwrk_6_op_hcompute_hw_output_global_wrapper_stencil_3_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.data_out_0"], - ["io16_hw_output_global_wrapper_stencil_clkwrk_3_op_hcompute_hw_output_global_wrapper_stencil_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.data_out_1"], ["io1in_reset.out","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_0_garnet.flush"], ["hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.clk_en","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_glb_stencil_1_read_0.out","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.data_in_0"], ["io16_hw_output_global_wrapper_stencil_clkwrk_4_op_hcompute_hw_output_global_wrapper_stencil_1_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.data_out_0"], - ["io16_hw_output_global_wrapper_stencil_clkwrk_7_op_hcompute_hw_output_global_wrapper_stencil_4_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.data_out_1"], + ["io16_hw_output_global_wrapper_stencil_clkwrk_7_op_hcompute_hw_output_global_wrapper_stencil_4_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_1_garnet.flush"], ["hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.clk_en","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], ["io16in_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_glb_stencil_2_read_0.out","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.data_in_0"], ["io16_hw_output_global_wrapper_stencil_clkwrk_5_op_hcompute_hw_output_global_wrapper_stencil_2_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.data_out_0"], - ["io16_hw_output_global_wrapper_stencil_clkwrk_8_op_hcompute_hw_output_global_wrapper_stencil_5_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.data_out_1"], + ["io16_hw_output_global_wrapper_stencil_clkwrk_8_op_hcompute_hw_output_global_wrapper_stencil_5_write_0.in","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.data_out_0"], ["io1in_reset.out","hw_input_global_wrapper_global_wrapper_stencil$ub_hw_input_global_wrapper_global_wrapper_stencil_BANK_2_garnet.flush"], ["op_hcompute_hw_output_global_wrapper_stencil_port_controller_garnet.stencil_valid","io1_hw_output_global_wrapper_stencil_clkwrk_3_op_hcompute_hw_output_global_wrapper_stencil_write_valid.in"], ["op_hcompute_hw_output_global_wrapper_stencil_1_port_controller_garnet.stencil_valid","io1_hw_output_global_wrapper_stencil_clkwrk_4_op_hcompute_hw_output_global_wrapper_stencil_1_write_valid.in"], diff --git a/aha_garnet_design_pond/complex_mem_pond/complex_mem_pond.json b/aha_garnet_design_pond/complex_mem_pond/complex_mem_pond.json new file mode 100644 index 000000000..80285e7d7 --- /dev/null +++ b/aha_garnet_design_pond/complex_mem_pond/complex_mem_pond.json @@ -0,0 +1,1631 @@ +{"top":"global.complex_mem_pond", +"namespaces":{ + "global":{ + "modules":{ + "complex_mem_pond":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["reset","BitIn"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read_en","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_en","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "_U78":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U83":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "input_cgra_stencil":{ + "modref":"global.input_cgra_stencil_ub" + }, + "input_pond_stencil":{ + "modref":"global.input_pond_stencil_ub" + }, + "kernel_cgra_stencil":{ + "modref":"global.kernel_cgra_stencil_ub" + }, + "kernel_pond_stencil":{ + "modref":"global.kernel_pond_stencil_ub" + }, + "op_hcompute_hw_output_stencil":{ + "modref":"global.cu_op_hcompute_hw_output_stencil" + }, + "op_hcompute_hw_output_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U72" + }, + "op_hcompute_hw_output_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[20816],"cycle_stride":[1,4,16],"dimensionality":3,"extent":[4,4,3]}},"mode":"lake"} + }, + "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_output_stencil_read_start":{ + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U71" + }, + "op_hcompute_hw_output_stencil_write_start":{ + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U73" + }, + "op_hcompute_input_cgra_stencil":{ + "modref":"global.cu_op_hcompute_input_cgra_stencil" + }, + "op_hcompute_input_cgra_stencil_exe_start":{ + "modref":"global.op_hcompute_input_cgra_stencil_exe_start_pt__U81" + }, + "op_hcompute_input_cgra_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U79"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,192],"dimensionality":4,"extent":[8,4,6,6]}},"mode":"lake"} + }, + "op_hcompute_input_cgra_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_input_cgra_stencil_read_start":{ + "modref":"global.op_hcompute_input_cgra_stencil_read_start_pt__U80" + }, + "op_hcompute_input_cgra_stencil_write_start":{ + "modref":"global.op_hcompute_input_cgra_stencil_write_start_pt__U82" + }, + "op_hcompute_input_pond_stencil":{ + "modref":"global.cu_op_hcompute_input_pond_stencil" + }, + "op_hcompute_kernel_cgra_stencil":{ + "modref":"global.cu_op_hcompute_kernel_cgra_stencil" + }, + "op_hcompute_kernel_cgra_stencil_exe_start":{ + "modref":"global.op_hcompute_kernel_cgra_stencil_exe_start_pt__U76" + }, + "op_hcompute_kernel_cgra_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U74"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,96,288],"dimensionality":5,"extent":[8,4,3,3,3]}},"mode":"lake"} + }, + "op_hcompute_kernel_cgra_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_kernel_cgra_stencil_read_start":{ + "modref":"global.op_hcompute_kernel_cgra_stencil_read_start_pt__U75" + }, + "op_hcompute_kernel_cgra_stencil_write_start":{ + "modref":"global.op_hcompute_kernel_cgra_stencil_write_start_pt__U77" + }, + "op_hcompute_kernel_pond_stencil":{ + "modref":"global.cu_op_hcompute_kernel_pond_stencil" + }, + "op_hcompute_output_cgra_stencil":{ + "modref":"global.cu_op_hcompute_output_cgra_stencil" + }, + "op_hcompute_output_cgra_stencil_1":{ + "modref":"global.cu_op_hcompute_output_cgra_stencil_1" + }, + "op_hcompute_output_cgra_stencil_2":{ + "modref":"global.cu_op_hcompute_output_cgra_stencil_2" + }, + "op_hcompute_output_pond_stencil":{ + "modref":"global.cu_op_hcompute_output_pond_stencil" + }, + "op_hcompute_output_pond_stencil_1":{ + "modref":"global.cu_op_hcompute_output_pond_stencil_1" + }, + "op_hcompute_output_pond_stencil_2":{ + "modref":"global.cu_op_hcompute_output_pond_stencil_2" + }, + "op_hcompute_output_pond_stencil_3":{ + "modref":"global.cu_op_hcompute_output_pond_stencil_3" + }, + "output_cgra_stencil":{ + "modref":"global.output_cgra_stencil_ub" + }, + "output_pond_stencil":{ + "modref":"global.output_pond_stencil_ub" + } + }, + "connections":[ + ["self.clk","_U78.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read.0","_U78.in"], + ["self.clk","_U83.clk"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","_U83.in"], + ["self.clk","input_cgra_stencil.clk"], + ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], + ["op_hcompute_input_pond_stencil.input_cgra_stencil_op_hcompute_input_pond_stencil_read","input_cgra_stencil.op_hcompute_input_pond_stencil_read"], + ["self.reset","input_cgra_stencil.reset"], + ["self.clk","input_pond_stencil.clk"], + ["op_hcompute_input_pond_stencil.input_pond_stencil_op_hcompute_input_pond_stencil_write","input_pond_stencil.op_hcompute_input_pond_stencil_write"], + ["op_hcompute_output_pond_stencil_1.input_pond_stencil_op_hcompute_output_pond_stencil_1_read","input_pond_stencil.op_hcompute_output_pond_stencil_1_read"], + ["op_hcompute_output_pond_stencil_2.input_pond_stencil_op_hcompute_output_pond_stencil_2_read","input_pond_stencil.op_hcompute_output_pond_stencil_2_read"], + ["op_hcompute_output_pond_stencil_3.input_pond_stencil_op_hcompute_output_pond_stencil_3_read","input_pond_stencil.op_hcompute_output_pond_stencil_3_read"], + ["self.reset","input_pond_stencil.reset"], + ["self.clk","kernel_cgra_stencil.clk"], + ["op_hcompute_kernel_cgra_stencil.kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write","kernel_cgra_stencil.op_hcompute_kernel_cgra_stencil_write"], + ["op_hcompute_kernel_pond_stencil.kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read","kernel_cgra_stencil.op_hcompute_kernel_pond_stencil_read"], + ["self.reset","kernel_cgra_stencil.reset"], + ["self.clk","kernel_pond_stencil.clk"], + ["op_hcompute_kernel_pond_stencil.kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write","kernel_pond_stencil.op_hcompute_kernel_pond_stencil_write"], + ["op_hcompute_output_pond_stencil_1.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read","kernel_pond_stencil.op_hcompute_output_pond_stencil_1_read"], + ["op_hcompute_output_pond_stencil_2.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read","kernel_pond_stencil.op_hcompute_output_pond_stencil_2_read"], + ["op_hcompute_output_pond_stencil_3.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read","kernel_pond_stencil.op_hcompute_output_pond_stencil_3_read"], + ["self.reset","kernel_pond_stencil.reset"], + ["self.clk","op_hcompute_hw_output_stencil.clk"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_op_hcompute_hw_output_stencil_write"], + ["output_cgra_stencil.op_hcompute_hw_output_stencil_read","op_hcompute_hw_output_stencil.output_cgra_stencil_op_hcompute_hw_output_stencil_read"], + ["op_hcompute_hw_output_stencil_port_controller.stencil_valid","op_hcompute_hw_output_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_output_stencil_port_controller.clk"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_output_stencil_port_controller.flush"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.rst_n"], + ["op_hcompute_hw_output_stencil_read_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_output_stencil_write_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"], + ["self.clk","op_hcompute_input_cgra_stencil.clk"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read","op_hcompute_input_cgra_stencil.input_host_stencil_op_hcompute_input_cgra_stencil_read"], + ["op_hcompute_input_cgra_stencil_port_controller.stencil_valid","op_hcompute_input_cgra_stencil_exe_start.in"], + ["self.clk","op_hcompute_input_cgra_stencil_port_controller.clk"], + ["op_hcompute_input_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_input_cgra_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_input_cgra_stencil_port_controller.flush"], + ["op_hcompute_input_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_input_cgra_stencil_port_controller.rst_n"], + ["op_hcompute_input_cgra_stencil_read_start.in","op_hcompute_input_cgra_stencil_port_controller.stencil_valid"], + ["op_hcompute_input_cgra_stencil_write_start.in","op_hcompute_input_cgra_stencil_port_controller.stencil_valid"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read_en","op_hcompute_input_cgra_stencil_read_start.out"], + ["self.clk","op_hcompute_input_pond_stencil.clk"], + ["self.clk","op_hcompute_kernel_cgra_stencil.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read","op_hcompute_kernel_cgra_stencil.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read"], + ["op_hcompute_kernel_cgra_stencil_port_controller.stencil_valid","op_hcompute_kernel_cgra_stencil_exe_start.in"], + ["self.clk","op_hcompute_kernel_cgra_stencil_port_controller.clk"], + ["op_hcompute_kernel_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_kernel_cgra_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_kernel_cgra_stencil_port_controller.flush"], + ["op_hcompute_kernel_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_kernel_cgra_stencil_port_controller.rst_n"], + ["op_hcompute_kernel_cgra_stencil_read_start.in","op_hcompute_kernel_cgra_stencil_port_controller.stencil_valid"], + ["op_hcompute_kernel_cgra_stencil_write_start.in","op_hcompute_kernel_cgra_stencil_port_controller.stencil_valid"], + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_en","op_hcompute_kernel_cgra_stencil_read_start.out"], + ["self.clk","op_hcompute_kernel_pond_stencil.clk"], + ["self.clk","op_hcompute_output_cgra_stencil.clk"], + ["output_cgra_stencil.op_hcompute_output_cgra_stencil_write","op_hcompute_output_cgra_stencil.output_cgra_stencil_op_hcompute_output_cgra_stencil_write"], + ["output_pond_stencil.op_hcompute_output_cgra_stencil_read","op_hcompute_output_cgra_stencil.output_pond_stencil_op_hcompute_output_cgra_stencil_read"], + ["self.clk","op_hcompute_output_cgra_stencil_1.clk"], + ["output_cgra_stencil.op_hcompute_output_cgra_stencil_1_write","op_hcompute_output_cgra_stencil_1.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write"], + ["output_pond_stencil.op_hcompute_output_cgra_stencil_1_read","op_hcompute_output_cgra_stencil_1.output_pond_stencil_op_hcompute_output_cgra_stencil_1_read"], + ["self.clk","op_hcompute_output_cgra_stencil_2.clk"], + ["output_cgra_stencil.op_hcompute_output_cgra_stencil_2_write","op_hcompute_output_cgra_stencil_2.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write"], + ["output_pond_stencil.op_hcompute_output_cgra_stencil_2_read","op_hcompute_output_cgra_stencil_2.output_pond_stencil_op_hcompute_output_cgra_stencil_2_read"], + ["self.clk","op_hcompute_output_pond_stencil.clk"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_write","op_hcompute_output_pond_stencil.output_pond_stencil_op_hcompute_output_pond_stencil_write"], + ["self.clk","op_hcompute_output_pond_stencil_1.clk"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_1_read","op_hcompute_output_pond_stencil_1.output_pond_stencil_op_hcompute_output_pond_stencil_1_read"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_1_write","op_hcompute_output_pond_stencil_1.output_pond_stencil_op_hcompute_output_pond_stencil_1_write"], + ["self.clk","op_hcompute_output_pond_stencil_2.clk"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_2_read","op_hcompute_output_pond_stencil_2.output_pond_stencil_op_hcompute_output_pond_stencil_2_read"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_2_write","op_hcompute_output_pond_stencil_2.output_pond_stencil_op_hcompute_output_pond_stencil_2_write"], + ["self.clk","op_hcompute_output_pond_stencil_3.clk"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_3_read","op_hcompute_output_pond_stencil_3.output_pond_stencil_op_hcompute_output_pond_stencil_3_read"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_3_write","op_hcompute_output_pond_stencil_3.output_pond_stencil_op_hcompute_output_pond_stencil_3_write"], + ["self.clk","output_cgra_stencil.clk"], + ["self.reset","output_cgra_stencil.reset"], + ["self.clk","output_pond_stencil.clk"], + ["self.reset","output_pond_stencil.reset"] + ] + }, + "cu_op_hcompute_hw_output_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_cgra_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_output_stencil" + } + }, + "connections":[ + ["self.output_cgra_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in0_output_cgra_stencil.0"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_cgra_stencil_op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_input_cgra_stencil" + } + }, + "connections":[ + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","inner_compute.in0_input_host_stencil.0"], + ["self.input_cgra_stencil_op_hcompute_input_cgra_stencil_write.0","inner_compute.out_input_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_cgra_stencil_op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_pond_stencil_op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_input_pond_stencil" + } + }, + "connections":[ + ["self.input_cgra_stencil_op_hcompute_input_pond_stencil_read.0","inner_compute.in0_input_cgra_stencil.0"], + ["self.input_pond_stencil_op_hcompute_input_pond_stencil_write.0","inner_compute.out_input_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_kernel_cgra_stencil" + } + }, + "connections":[ + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read.0","inner_compute.in0_kernel_host_stencil.0"], + ["self.kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write.0","inner_compute.out_kernel_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_kernel_pond_stencil" + } + }, + "connections":[ + ["self.kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read.0","inner_compute.in0_kernel_cgra_stencil.0"], + ["self.kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write.0","inner_compute.out_kernel_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_cgra_stencil" + } + }, + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_read.0","inner_compute.in0_output_pond_stencil.0"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","inner_compute.out_output_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_cgra_stencil_1" + } + }, + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_1_read.0","inner_compute.in0_output_pond_stencil.0"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0","inner_compute.out_output_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_cgra_stencil_2" + } + }, + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_2_read.0","inner_compute.in0_output_pond_stencil.0"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0","inner_compute.out_output_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_pond_stencil" + } + }, + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_write.0","inner_compute.out_output_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_pond_stencil_1" + } + }, + "connections":[ + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute.in0_input_pond_stencil.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.1","inner_compute.in0_input_pond_stencil.1"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.2","inner_compute.in0_input_pond_stencil.2"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.3","inner_compute.in0_input_pond_stencil.3"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute.in1_kernel_pond_stencil.0"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.1","inner_compute.in1_kernel_pond_stencil.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.2","inner_compute.in1_kernel_pond_stencil.2"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.3","inner_compute.in1_kernel_pond_stencil.3"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute.in2_output_pond_stencil.0"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_write.0","inner_compute.out_output_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_pond_stencil_2" + } + }, + "connections":[ + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.0","inner_compute.in0_input_pond_stencil.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.1","inner_compute.in0_input_pond_stencil.1"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.2","inner_compute.in0_input_pond_stencil.2"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.3","inner_compute.in0_input_pond_stencil.3"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.0","inner_compute.in1_kernel_pond_stencil.0"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.1","inner_compute.in1_kernel_pond_stencil.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.2","inner_compute.in1_kernel_pond_stencil.2"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.3","inner_compute.in1_kernel_pond_stencil.3"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_2_read.0","inner_compute.in2_output_pond_stencil.0"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_2_write.0","inner_compute.out_output_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_3":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_3_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_pond_stencil_3" + } + }, + "connections":[ + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.0","inner_compute.in0_input_pond_stencil.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.1","inner_compute.in0_input_pond_stencil.1"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.2","inner_compute.in0_input_pond_stencil.2"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.3","inner_compute.in0_input_pond_stencil.3"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.0","inner_compute.in1_kernel_pond_stencil.0"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.1","inner_compute.in1_kernel_pond_stencil.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.2","inner_compute.in1_kernel_pond_stencil.2"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.3","inner_compute.in1_kernel_pond_stencil.3"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_3_read.0","inner_compute.in2_output_pond_stencil.0"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_3_write.0","inner_compute.out_output_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_cgra_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_pond_stencil":{ + "type":["Record",[ + ["out_input_pond_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_pond_stencil","self.in0_input_cgra_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["out_kernel_pond_stencil",["Array",16,"Bit"]], + ["in0_kernel_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_pond_stencil","self.in0_kernel_cgra_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_pond_stencil":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_pond_stencil","const_p0__677.out"] + ] + }, + "hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_698_704_705":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_699_703_704":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_700_702_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_pond_stencil_1_701_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_1_input_pond_stencil_1_698":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_2_input_pond_stencil_2_699":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_3_input_pond_stencil_3_700":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_4_input_pond_stencil_4_701":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_pond_stencil_1_input_pond_stencil_1_698.out","add_698_704_705.in0"], + ["add_699_703_704.out","add_698_704_705.in1"], + ["self.out_output_pond_stencil","add_698_704_705.out"], + ["mul_kernel_pond_stencil_2_input_pond_stencil_2_699.out","add_699_703_704.in0"], + ["add_700_702_703.out","add_699_703_704.in1"], + ["mul_kernel_pond_stencil_3_input_pond_stencil_3_700.out","add_700_702_703.in0"], + ["add_output_pond_stencil_1_701_702.out","add_700_702_703.in1"], + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_1_701_702.in0"], + ["mul_kernel_pond_stencil_4_input_pond_stencil_4_701.out","add_output_pond_stencil_1_701_702.in1"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_698.in0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_698.in1"], + ["self.in1_kernel_pond_stencil.1","mul_kernel_pond_stencil_2_input_pond_stencil_2_699.in0"], + ["self.in0_input_pond_stencil.1","mul_kernel_pond_stencil_2_input_pond_stencil_2_699.in1"], + ["self.in1_kernel_pond_stencil.2","mul_kernel_pond_stencil_3_input_pond_stencil_3_700.in0"], + ["self.in0_input_pond_stencil.2","mul_kernel_pond_stencil_3_input_pond_stencil_3_700.in1"], + ["self.in1_kernel_pond_stencil.3","mul_kernel_pond_stencil_4_input_pond_stencil_4_701.in0"], + ["self.in0_input_pond_stencil.3","mul_kernel_pond_stencil_4_input_pond_stencil_4_701.in1"] + ] + }, + "hcompute_output_pond_stencil_2":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_731_737_738":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_732_736_737":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_733_735_736":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_pond_stencil_2_734_735":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_5_input_pond_stencil_5_731":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_6_input_pond_stencil_6_732":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_7_input_pond_stencil_7_733":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_8_input_pond_stencil_8_734":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_pond_stencil_5_input_pond_stencil_5_731.out","add_731_737_738.in0"], + ["add_732_736_737.out","add_731_737_738.in1"], + ["self.out_output_pond_stencil","add_731_737_738.out"], + ["mul_kernel_pond_stencil_6_input_pond_stencil_6_732.out","add_732_736_737.in0"], + ["add_733_735_736.out","add_732_736_737.in1"], + ["mul_kernel_pond_stencil_7_input_pond_stencil_7_733.out","add_733_735_736.in0"], + ["add_output_pond_stencil_2_734_735.out","add_733_735_736.in1"], + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_2_734_735.in0"], + ["mul_kernel_pond_stencil_8_input_pond_stencil_8_734.out","add_output_pond_stencil_2_734_735.in1"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_5_input_pond_stencil_5_731.in0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_5_input_pond_stencil_5_731.in1"], + ["self.in1_kernel_pond_stencil.1","mul_kernel_pond_stencil_6_input_pond_stencil_6_732.in0"], + ["self.in0_input_pond_stencil.1","mul_kernel_pond_stencil_6_input_pond_stencil_6_732.in1"], + ["self.in1_kernel_pond_stencil.2","mul_kernel_pond_stencil_7_input_pond_stencil_7_733.in0"], + ["self.in0_input_pond_stencil.2","mul_kernel_pond_stencil_7_input_pond_stencil_7_733.in1"], + ["self.in1_kernel_pond_stencil.3","mul_kernel_pond_stencil_8_input_pond_stencil_8_734.in0"], + ["self.in0_input_pond_stencil.3","mul_kernel_pond_stencil_8_input_pond_stencil_8_734.in1"] + ] + }, + "hcompute_output_pond_stencil_3":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_764_770_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_765_769_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_766_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_pond_stencil_3_767_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_10_input_pond_stencil_10_765":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_11_input_pond_stencil_11_766":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_12_input_pond_stencil_12_767":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_9_input_pond_stencil_9_764":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_pond_stencil_9_input_pond_stencil_9_764.out","add_764_770_771.in0"], + ["add_765_769_770.out","add_764_770_771.in1"], + ["self.out_output_pond_stencil","add_764_770_771.out"], + ["mul_kernel_pond_stencil_10_input_pond_stencil_10_765.out","add_765_769_770.in0"], + ["add_766_768_769.out","add_765_769_770.in1"], + ["mul_kernel_pond_stencil_11_input_pond_stencil_11_766.out","add_766_768_769.in0"], + ["add_output_pond_stencil_3_767_768.out","add_766_768_769.in1"], + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_3_767_768.in0"], + ["mul_kernel_pond_stencil_12_input_pond_stencil_12_767.out","add_output_pond_stencil_3_767_768.in1"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_10_input_pond_stencil_10_765.in0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_10_input_pond_stencil_10_765.in1"], + ["self.in1_kernel_pond_stencil.1","mul_kernel_pond_stencil_11_input_pond_stencil_11_766.in0"], + ["self.in0_input_pond_stencil.1","mul_kernel_pond_stencil_11_input_pond_stencil_11_766.in1"], + ["self.in1_kernel_pond_stencil.2","mul_kernel_pond_stencil_12_input_pond_stencil_12_767.in0"], + ["self.in0_input_pond_stencil.2","mul_kernel_pond_stencil_12_input_pond_stencil_12_767.in1"], + ["self.in1_kernel_pond_stencil.3","mul_kernel_pond_stencil_9_input_pond_stencil_9_764.in0"], + ["self.in0_input_pond_stencil.3","mul_kernel_pond_stencil_9_input_pond_stencil_9_764.in1"] + ] + }, + "input_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_input_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_input_cgra_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,32,192],"dimensionality":4,"extent":[2,4,6,6],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,48]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,192],"dimensionality":4,"extent":[8,4,6,6],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,8,24,72,1229,4916],"dimensionality":6,"extent":[2,3,3,4,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,48,2,8,48],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,2,0,0]},"tb2out_0":{"cycle_starting_addr":[1155],"cycle_stride":[1,8,24,72,1229,4916],"dimensionality":6,"extent":[8,3,3,4,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,8,0,0]}},"mode":"lake"} + }, + "ub_input_cgra_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], + ["ub_input_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_input_cgra_stencil_write.0"], + ["ub_input_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_input_pond_stencil_read.0"], + ["ub_input_cgra_stencil_BANK_0.flush","self.reset"], + ["ub_input_cgra_stencil_BANK_0_clk_en_const.out","ub_input_cgra_stencil_BANK_0.clk_en"], + ["ub_input_cgra_stencil_BANK_0_clk_en_const.out","ub_input_cgra_stencil_BANK_0.rst_n"] + ] + }, + "input_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_3_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U11":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1370],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U11_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U2":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1154],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U5":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1226],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U5_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U8":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1298],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U8_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_input_pond_stencil_BANK_0":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U1"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1152],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_input_pond_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_input_pond_stencil_BANK_1":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U4"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1080],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_input_pond_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_input_pond_stencil_BANK_2":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U7"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1008],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_input_pond_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_input_pond_stencil_BANK_3":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U10"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[936],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_input_pond_stencil_BANK_3_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["self.clk","cgpl_ctrl_U11.clk"], + ["cgpl_ctrl_U11_clk_en_const.out","cgpl_ctrl_U11.clk_en"], + ["self.reset","cgpl_ctrl_U11.flush"], + ["cgpl_ctrl_U11_clk_en_const.out","cgpl_ctrl_U11.rst_n"], + ["ub_input_pond_stencil_BANK_3.flush","cgpl_ctrl_U11.stencil_valid"], + ["self.clk","cgpl_ctrl_U2.clk"], + ["cgpl_ctrl_U2_clk_en_const.out","cgpl_ctrl_U2.clk_en"], + ["self.reset","cgpl_ctrl_U2.flush"], + ["cgpl_ctrl_U2_clk_en_const.out","cgpl_ctrl_U2.rst_n"], + ["ub_input_pond_stencil_BANK_0.flush","cgpl_ctrl_U2.stencil_valid"], + ["self.clk","cgpl_ctrl_U5.clk"], + ["cgpl_ctrl_U5_clk_en_const.out","cgpl_ctrl_U5.clk_en"], + ["self.reset","cgpl_ctrl_U5.flush"], + ["cgpl_ctrl_U5_clk_en_const.out","cgpl_ctrl_U5.rst_n"], + ["ub_input_pond_stencil_BANK_1.flush","cgpl_ctrl_U5.stencil_valid"], + ["self.clk","cgpl_ctrl_U8.clk"], + ["cgpl_ctrl_U8_clk_en_const.out","cgpl_ctrl_U8.clk_en"], + ["self.reset","cgpl_ctrl_U8.flush"], + ["cgpl_ctrl_U8_clk_en_const.out","cgpl_ctrl_U8.rst_n"], + ["ub_input_pond_stencil_BANK_2.flush","cgpl_ctrl_U8.stencil_valid"], + ["ub_input_pond_stencil_BANK_0.clk","self.clk"], + ["ub_input_pond_stencil_BANK_1.clk","self.clk"], + ["ub_input_pond_stencil_BANK_2.clk","self.clk"], + ["ub_input_pond_stencil_BANK_3.clk","self.clk"], + ["ub_input_pond_stencil_BANK_0.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_1.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_2.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_3.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_0.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_input_pond_stencil_BANK_1.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.1"], + ["ub_input_pond_stencil_BANK_2.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.2"], + ["ub_input_pond_stencil_BANK_3.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.3"], + ["ub_input_pond_stencil_BANK_0.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.0"], + ["ub_input_pond_stencil_BANK_1.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.1"], + ["ub_input_pond_stencil_BANK_2.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.2"], + ["ub_input_pond_stencil_BANK_3.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.3"], + ["ub_input_pond_stencil_BANK_1.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.0"], + ["ub_input_pond_stencil_BANK_2.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.1"], + ["ub_input_pond_stencil_BANK_3.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.2"], + ["ub_input_pond_stencil_BANK_0.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.3"], + ["ub_input_pond_stencil_BANK_0_clk_en_const.out","ub_input_pond_stencil_BANK_0.clk_en"], + ["ub_input_pond_stencil_BANK_0_clk_en_const.out","ub_input_pond_stencil_BANK_0.rst_n"], + ["ub_input_pond_stencil_BANK_1_clk_en_const.out","ub_input_pond_stencil_BANK_1.clk_en"], + ["ub_input_pond_stencil_BANK_1_clk_en_const.out","ub_input_pond_stencil_BANK_1.rst_n"], + ["ub_input_pond_stencil_BANK_2_clk_en_const.out","ub_input_pond_stencil_BANK_2.clk_en"], + ["ub_input_pond_stencil_BANK_2_clk_en_const.out","ub_input_pond_stencil_BANK_2.rst_n"], + ["ub_input_pond_stencil_BANK_3_clk_en_const.out","ub_input_pond_stencil_BANK_3.clk_en"], + ["ub_input_pond_stencil_BANK_3_clk_en_const.out","ub_input_pond_stencil_BANK_3.rst_n"] + ] + }, + "kernel_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_kernel_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_kernel_cgra_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U13"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,32,96,288],"dimensionality":5,"extent":[2,4,3,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,96,288],"dimensionality":5,"extent":[8,4,3,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[1441],"cycle_stride":[4,8,216,1229],"dimensionality":4,"extent":[2,27,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0]},"tb2out_0":{"cycle_starting_addr":[1443],"cycle_stride":[1,8,216,1229],"dimensionality":4,"extent":[8,27,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0]}},"mode":"lake"} + }, + "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], + ["ub_kernel_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_kernel_cgra_stencil_write.0"], + ["ub_kernel_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_kernel_pond_stencil_read.0"], + ["ub_kernel_cgra_stencil_BANK_0.flush","self.reset"], + ["ub_kernel_cgra_stencil_BANK_0_clk_en_const.out","ub_kernel_cgra_stencil_BANK_0.clk_en"], + ["ub_kernel_cgra_stencil_BANK_0_clk_en_const.out","ub_kernel_cgra_stencil_BANK_0.rst_n"] + ] + }, + "kernel_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_3_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U15":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1442],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U15_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U18":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1450],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U18_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U21":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1458],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U21_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U24":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1658],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U24_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U27":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1666],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U27_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U30":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1674],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U30_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U33":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1874],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U33_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U36":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1882],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U36_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U39":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1890],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U39_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U42":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[2090],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U42_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U45":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[2098],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U45_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U48":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U49"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[2106],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U48_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_0":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U14"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[864],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_1":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U17"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[856],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_10":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U44"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[208],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_10_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_11":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U47"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[200],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_11_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_2":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U20"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[848],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_3":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U23"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[648],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_3_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_4":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U26"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[640],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_4_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_5":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U29"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[632],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_5_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_6":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U32"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[432],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_6_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_7":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U35"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[424],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_7_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_8":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U38"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[416],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_8_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_9":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U41"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[216],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_kernel_pond_stencil_BANK_9_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["self.clk","cgpl_ctrl_U15.clk"], + ["cgpl_ctrl_U15_clk_en_const.out","cgpl_ctrl_U15.clk_en"], + ["self.reset","cgpl_ctrl_U15.flush"], + ["cgpl_ctrl_U15_clk_en_const.out","cgpl_ctrl_U15.rst_n"], + ["ub_kernel_pond_stencil_BANK_0.flush","cgpl_ctrl_U15.stencil_valid"], + ["self.clk","cgpl_ctrl_U18.clk"], + ["cgpl_ctrl_U18_clk_en_const.out","cgpl_ctrl_U18.clk_en"], + ["self.reset","cgpl_ctrl_U18.flush"], + ["cgpl_ctrl_U18_clk_en_const.out","cgpl_ctrl_U18.rst_n"], + ["ub_kernel_pond_stencil_BANK_1.flush","cgpl_ctrl_U18.stencil_valid"], + ["self.clk","cgpl_ctrl_U21.clk"], + ["cgpl_ctrl_U21_clk_en_const.out","cgpl_ctrl_U21.clk_en"], + ["self.reset","cgpl_ctrl_U21.flush"], + ["cgpl_ctrl_U21_clk_en_const.out","cgpl_ctrl_U21.rst_n"], + ["ub_kernel_pond_stencil_BANK_2.flush","cgpl_ctrl_U21.stencil_valid"], + ["self.clk","cgpl_ctrl_U24.clk"], + ["cgpl_ctrl_U24_clk_en_const.out","cgpl_ctrl_U24.clk_en"], + ["self.reset","cgpl_ctrl_U24.flush"], + ["cgpl_ctrl_U24_clk_en_const.out","cgpl_ctrl_U24.rst_n"], + ["ub_kernel_pond_stencil_BANK_3.flush","cgpl_ctrl_U24.stencil_valid"], + ["self.clk","cgpl_ctrl_U27.clk"], + ["cgpl_ctrl_U27_clk_en_const.out","cgpl_ctrl_U27.clk_en"], + ["self.reset","cgpl_ctrl_U27.flush"], + ["cgpl_ctrl_U27_clk_en_const.out","cgpl_ctrl_U27.rst_n"], + ["ub_kernel_pond_stencil_BANK_4.flush","cgpl_ctrl_U27.stencil_valid"], + ["self.clk","cgpl_ctrl_U30.clk"], + ["cgpl_ctrl_U30_clk_en_const.out","cgpl_ctrl_U30.clk_en"], + ["self.reset","cgpl_ctrl_U30.flush"], + ["cgpl_ctrl_U30_clk_en_const.out","cgpl_ctrl_U30.rst_n"], + ["ub_kernel_pond_stencil_BANK_5.flush","cgpl_ctrl_U30.stencil_valid"], + ["self.clk","cgpl_ctrl_U33.clk"], + ["cgpl_ctrl_U33_clk_en_const.out","cgpl_ctrl_U33.clk_en"], + ["self.reset","cgpl_ctrl_U33.flush"], + ["cgpl_ctrl_U33_clk_en_const.out","cgpl_ctrl_U33.rst_n"], + ["ub_kernel_pond_stencil_BANK_6.flush","cgpl_ctrl_U33.stencil_valid"], + ["self.clk","cgpl_ctrl_U36.clk"], + ["cgpl_ctrl_U36_clk_en_const.out","cgpl_ctrl_U36.clk_en"], + ["self.reset","cgpl_ctrl_U36.flush"], + ["cgpl_ctrl_U36_clk_en_const.out","cgpl_ctrl_U36.rst_n"], + ["ub_kernel_pond_stencil_BANK_7.flush","cgpl_ctrl_U36.stencil_valid"], + ["self.clk","cgpl_ctrl_U39.clk"], + ["cgpl_ctrl_U39_clk_en_const.out","cgpl_ctrl_U39.clk_en"], + ["self.reset","cgpl_ctrl_U39.flush"], + ["cgpl_ctrl_U39_clk_en_const.out","cgpl_ctrl_U39.rst_n"], + ["ub_kernel_pond_stencil_BANK_8.flush","cgpl_ctrl_U39.stencil_valid"], + ["self.clk","cgpl_ctrl_U42.clk"], + ["cgpl_ctrl_U42_clk_en_const.out","cgpl_ctrl_U42.clk_en"], + ["self.reset","cgpl_ctrl_U42.flush"], + ["cgpl_ctrl_U42_clk_en_const.out","cgpl_ctrl_U42.rst_n"], + ["ub_kernel_pond_stencil_BANK_9.flush","cgpl_ctrl_U42.stencil_valid"], + ["self.clk","cgpl_ctrl_U45.clk"], + ["cgpl_ctrl_U45_clk_en_const.out","cgpl_ctrl_U45.clk_en"], + ["self.reset","cgpl_ctrl_U45.flush"], + ["cgpl_ctrl_U45_clk_en_const.out","cgpl_ctrl_U45.rst_n"], + ["ub_kernel_pond_stencil_BANK_10.flush","cgpl_ctrl_U45.stencil_valid"], + ["self.clk","cgpl_ctrl_U48.clk"], + ["cgpl_ctrl_U48_clk_en_const.out","cgpl_ctrl_U48.clk_en"], + ["self.reset","cgpl_ctrl_U48.flush"], + ["cgpl_ctrl_U48_clk_en_const.out","cgpl_ctrl_U48.rst_n"], + ["ub_kernel_pond_stencil_BANK_11.flush","cgpl_ctrl_U48.stencil_valid"], + ["ub_kernel_pond_stencil_BANK_0.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_1.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_10.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_11.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_2.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_3.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_4.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_5.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_6.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_7.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_8.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_9.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_0.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_1.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_10.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_11.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_2.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_3.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_4.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_5.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_6.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_7.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_8.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_9.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_0.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_kernel_pond_stencil_BANK_3.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.1"], + ["ub_kernel_pond_stencil_BANK_6.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.2"], + ["ub_kernel_pond_stencil_BANK_9.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.3"], + ["ub_kernel_pond_stencil_BANK_1.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.0"], + ["ub_kernel_pond_stencil_BANK_4.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.1"], + ["ub_kernel_pond_stencil_BANK_7.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.2"], + ["ub_kernel_pond_stencil_BANK_10.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.3"], + ["ub_kernel_pond_stencil_BANK_5.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.0"], + ["ub_kernel_pond_stencil_BANK_8.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.1"], + ["ub_kernel_pond_stencil_BANK_11.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.2"], + ["ub_kernel_pond_stencil_BANK_2.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.3"], + ["ub_kernel_pond_stencil_BANK_0_clk_en_const.out","ub_kernel_pond_stencil_BANK_0.clk_en"], + ["ub_kernel_pond_stencil_BANK_0_clk_en_const.out","ub_kernel_pond_stencil_BANK_0.rst_n"], + ["ub_kernel_pond_stencil_BANK_1_clk_en_const.out","ub_kernel_pond_stencil_BANK_1.clk_en"], + ["ub_kernel_pond_stencil_BANK_1_clk_en_const.out","ub_kernel_pond_stencil_BANK_1.rst_n"], + ["ub_kernel_pond_stencil_BANK_10_clk_en_const.out","ub_kernel_pond_stencil_BANK_10.clk_en"], + ["ub_kernel_pond_stencil_BANK_10_clk_en_const.out","ub_kernel_pond_stencil_BANK_10.rst_n"], + ["ub_kernel_pond_stencil_BANK_11_clk_en_const.out","ub_kernel_pond_stencil_BANK_11.clk_en"], + ["ub_kernel_pond_stencil_BANK_11_clk_en_const.out","ub_kernel_pond_stencil_BANK_11.rst_n"], + ["ub_kernel_pond_stencil_BANK_2_clk_en_const.out","ub_kernel_pond_stencil_BANK_2.clk_en"], + ["ub_kernel_pond_stencil_BANK_2_clk_en_const.out","ub_kernel_pond_stencil_BANK_2.rst_n"], + ["ub_kernel_pond_stencil_BANK_3_clk_en_const.out","ub_kernel_pond_stencil_BANK_3.clk_en"], + ["ub_kernel_pond_stencil_BANK_3_clk_en_const.out","ub_kernel_pond_stencil_BANK_3.rst_n"], + ["ub_kernel_pond_stencil_BANK_4_clk_en_const.out","ub_kernel_pond_stencil_BANK_4.clk_en"], + ["ub_kernel_pond_stencil_BANK_4_clk_en_const.out","ub_kernel_pond_stencil_BANK_4.rst_n"], + ["ub_kernel_pond_stencil_BANK_5_clk_en_const.out","ub_kernel_pond_stencil_BANK_5.clk_en"], + ["ub_kernel_pond_stencil_BANK_5_clk_en_const.out","ub_kernel_pond_stencil_BANK_5.rst_n"], + ["ub_kernel_pond_stencil_BANK_6_clk_en_const.out","ub_kernel_pond_stencil_BANK_6.clk_en"], + ["ub_kernel_pond_stencil_BANK_6_clk_en_const.out","ub_kernel_pond_stencil_BANK_6.rst_n"], + ["ub_kernel_pond_stencil_BANK_7_clk_en_const.out","ub_kernel_pond_stencil_BANK_7.clk_en"], + ["ub_kernel_pond_stencil_BANK_7_clk_en_const.out","ub_kernel_pond_stencil_BANK_7.rst_n"], + ["ub_kernel_pond_stencil_BANK_8_clk_en_const.out","ub_kernel_pond_stencil_BANK_8.clk_en"], + ["ub_kernel_pond_stencil_BANK_8_clk_en_const.out","ub_kernel_pond_stencil_BANK_8.rst_n"], + ["ub_kernel_pond_stencil_BANK_9_clk_en_const.out","ub_kernel_pond_stencil_BANK_9.clk_en"], + ["ub_kernel_pond_stencil_BANK_9_clk_en_const.out","ub_kernel_pond_stencil_BANK_9.rst_n"] + ] + }, + "op_hcompute_hw_output_stencil_exe_start_pt__U72":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_read_start_pt__U71":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_write_start_pt__U73":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_exe_start_pt__U81":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_read_start_pt__U80":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_write_start_pt__U82":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_exe_start_pt__U76":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_read_start_pt__U75":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_write_start_pt__U77":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "output_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_2_write_extra_ctrl","BitIn"], + ["op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "_U54_mux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "_U59_mux":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "dataout_pt_mux_ctrl__U52":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[20816],"cycle_stride":[1,4],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "dataout_pt_mux_ctrl__U52_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "dataout_pt_mux_ctrl__U57":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[20832],"cycle_stride":[1,4],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "dataout_pt_mux_ctrl__U57_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_output_cgra_stencil_BANK_0":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U50"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[2379],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20816],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"mode":"pond"} + }, + "ub_output_cgra_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_output_cgra_stencil_BANK_1":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U55"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[2380],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20832],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"mode":"pond"} + }, + "ub_output_cgra_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_output_cgra_stencil_BANK_2":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U60"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[2381],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20848],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"mode":"pond"} + }, + "ub_output_cgra_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["_U59_mux.out","_U54_mux.in0"], + ["ub_output_cgra_stencil_BANK_0.data_out_pond_0","_U54_mux.in1"], + ["self.op_hcompute_hw_output_stencil_read.0","_U54_mux.out"], + ["dataout_pt_mux_ctrl__U52.stencil_valid","_U54_mux.sel"], + ["ub_output_cgra_stencil_BANK_2.data_out_pond_0","_U59_mux.in0"], + ["ub_output_cgra_stencil_BANK_1.data_out_pond_0","_U59_mux.in1"], + ["dataout_pt_mux_ctrl__U57.stencil_valid","_U59_mux.sel"], + ["self.clk","dataout_pt_mux_ctrl__U52.clk"], + ["dataout_pt_mux_ctrl__U52_clk_en_const.out","dataout_pt_mux_ctrl__U52.clk_en"], + ["self.reset","dataout_pt_mux_ctrl__U52.flush"], + ["dataout_pt_mux_ctrl__U52_clk_en_const.out","dataout_pt_mux_ctrl__U52.rst_n"], + ["self.clk","dataout_pt_mux_ctrl__U57.clk"], + ["dataout_pt_mux_ctrl__U57_clk_en_const.out","dataout_pt_mux_ctrl__U57.clk_en"], + ["self.reset","dataout_pt_mux_ctrl__U57.flush"], + ["dataout_pt_mux_ctrl__U57_clk_en_const.out","dataout_pt_mux_ctrl__U57.rst_n"], + ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_1.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_2.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_1.data_in_pond_0","self.op_hcompute_output_cgra_stencil_1_write.0"], + ["ub_output_cgra_stencil_BANK_2.data_in_pond_0","self.op_hcompute_output_cgra_stencil_2_write.0"], + ["ub_output_cgra_stencil_BANK_0.data_in_pond_0","self.op_hcompute_output_cgra_stencil_write.0"], + ["ub_output_cgra_stencil_BANK_0.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_1.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_2.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_0_clk_en_const.out","ub_output_cgra_stencil_BANK_0.clk_en"], + ["ub_output_cgra_stencil_BANK_0_clk_en_const.out","ub_output_cgra_stencil_BANK_0.rst_n"], + ["ub_output_cgra_stencil_BANK_1_clk_en_const.out","ub_output_cgra_stencil_BANK_1.clk_en"], + ["ub_output_cgra_stencil_BANK_1_clk_en_const.out","ub_output_cgra_stencil_BANK_1.rst_n"], + ["ub_output_cgra_stencil_BANK_2_clk_en_const.out","ub_output_cgra_stencil_BANK_2.clk_en"], + ["ub_output_cgra_stencil_BANK_2_clk_en_const.out","ub_output_cgra_stencil_BANK_2.rst_n"] + ] + }, + "output_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_output_cgra_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_2_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_2_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_2_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_2_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_3_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_3_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_3_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_3_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "cgpl_ctrl_U62":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U63"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1151],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U62_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U65":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1152],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U65_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "cgpl_ctrl_U68":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U69"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1153],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U68_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_output_pond_stencil_BANK_0":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U61"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[1155],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1155],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[0],"read_data_stride":[0]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_output_pond_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_output_pond_stencil_BANK_1":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U64"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[1154],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[1],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[1],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1154],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[1],"read_data_stride":[0]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_output_pond_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_output_pond_stencil_BANK_2":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U67"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[1153],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[2],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[2],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1153],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[2],"read_data_stride":[0]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_output_pond_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["self.clk","cgpl_ctrl_U62.clk"], + ["cgpl_ctrl_U62_clk_en_const.out","cgpl_ctrl_U62.clk_en"], + ["self.reset","cgpl_ctrl_U62.flush"], + ["cgpl_ctrl_U62_clk_en_const.out","cgpl_ctrl_U62.rst_n"], + ["ub_output_pond_stencil_BANK_0.flush","cgpl_ctrl_U62.stencil_valid"], + ["self.clk","cgpl_ctrl_U65.clk"], + ["cgpl_ctrl_U65_clk_en_const.out","cgpl_ctrl_U65.clk_en"], + ["self.reset","cgpl_ctrl_U65.flush"], + ["cgpl_ctrl_U65_clk_en_const.out","cgpl_ctrl_U65.rst_n"], + ["ub_output_pond_stencil_BANK_1.flush","cgpl_ctrl_U65.stencil_valid"], + ["self.clk","cgpl_ctrl_U68.clk"], + ["cgpl_ctrl_U68_clk_en_const.out","cgpl_ctrl_U68.clk_en"], + ["self.reset","cgpl_ctrl_U68.flush"], + ["cgpl_ctrl_U68_clk_en_const.out","cgpl_ctrl_U68.rst_n"], + ["ub_output_pond_stencil_BANK_2.flush","cgpl_ctrl_U68.stencil_valid"], + ["ub_output_pond_stencil_BANK_0.clk","self.clk"], + ["ub_output_pond_stencil_BANK_1.clk","self.clk"], + ["ub_output_pond_stencil_BANK_2.clk","self.clk"], + ["ub_output_pond_stencil_BANK_1.data_out_pond_0","self.op_hcompute_output_cgra_stencil_1_read.0"], + ["ub_output_pond_stencil_BANK_2.data_out_pond_0","self.op_hcompute_output_cgra_stencil_2_read.0"], + ["ub_output_pond_stencil_BANK_0.data_out_pond_0","self.op_hcompute_output_cgra_stencil_read.0"], + ["ub_output_pond_stencil_BANK_0.data_out_pond_1","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_output_pond_stencil_BANK_0.data_in_pond_0","self.op_hcompute_output_pond_stencil_1_write.0"], + ["ub_output_pond_stencil_BANK_1.data_out_pond_1","self.op_hcompute_output_pond_stencil_2_read.0"], + ["ub_output_pond_stencil_BANK_1.data_in_pond_0","self.op_hcompute_output_pond_stencil_2_write.0"], + ["ub_output_pond_stencil_BANK_2.data_out_pond_1","self.op_hcompute_output_pond_stencil_3_read.0"], + ["ub_output_pond_stencil_BANK_2.data_in_pond_1","self.op_hcompute_output_pond_stencil_3_write.0"], + ["ub_output_pond_stencil_BANK_0.data_in_pond_1","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_1.data_in_pond_1","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_2.data_in_pond_0","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_0_clk_en_const.out","ub_output_pond_stencil_BANK_0.clk_en"], + ["ub_output_pond_stencil_BANK_0_clk_en_const.out","ub_output_pond_stencil_BANK_0.rst_n"], + ["ub_output_pond_stencil_BANK_1_clk_en_const.out","ub_output_pond_stencil_BANK_1.clk_en"], + ["ub_output_pond_stencil_BANK_1_clk_en_const.out","ub_output_pond_stencil_BANK_1.rst_n"], + ["ub_output_pond_stencil_BANK_2_clk_en_const.out","ub_output_pond_stencil_BANK_2.clk_en"], + ["ub_output_pond_stencil_BANK_2_clk_en_const.out","ub_output_pond_stencil_BANK_2.rst_n"] + ] + } + }, + "generators":{ + "delay_tile":{ + "typegen":"global.delay_tile_TG", + "genparams":{"delay":"Int"} + }, + "raw_dual_port_sram_tile":{ + "typegen":"global.raw_dual_port_sram_TG", + "genparams":{"depth":"Int"} + }, + "raw_quad_port_memtile":{ + "typegen":"global.raw_quad_port_memtile_TG", + "genparams":{"depth":"Int"} + }, + "tahoe":{ + "typegen":"global.tahoe_TG", + "genparams":{"depth":"Int"} + } + }, + "typegens":{ + "delay_tile_TG":[{"delay":"Int"},"implicit"], + "raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"], + "raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"], + "tahoe_TG":[{"depth":"Int"},"implicit"] + } + } +} +} diff --git a/aha_garnet_design_pond/complex_mem_pond/complex_mem_pond_garnet.json b/aha_garnet_design_pond/complex_mem_pond/complex_mem_pond_garnet.json new file mode 100644 index 000000000..e3f0b657c --- /dev/null +++ b/aha_garnet_design_pond/complex_mem_pond/complex_mem_pond_garnet.json @@ -0,0 +1,2586 @@ +{"top":"global.complex_mem_pond", +"namespaces":{ + "commonlib":{ + "generators":{ + "MAD":{ + "typegen":"coreir.ternary", + "genparams":{"width":"Int"} + }, + "abs":{ + "typegen":"coreir.unary", + "genparams":{"width":"Int"} + }, + "absd":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "accumulation_register":{ + "typegen":"commonlib.accumulation_register_type", + "genparams":{"iterations":"Int", "width":"Int"} + }, + "bitopn":{ + "typegen":"commonlib.bitopN_type", + "genparams":{"N":"Int", "operator":"String"} + }, + "const_array":{ + "typegen":"coreir.constArrayTG", + "genparams":{"type":"CoreIRType", "value":"Int"}, + "defaultgenargs":{"value":["Int",0]} + }, + "counter":{ + "typegen":"commonlib.counter_type", + "genparams":{"inc":"Int", "max":"Int", "min":"Int", "width":"Int"} + }, + "deserializer":{ + "typegen":"commonlib.deserializer_type", + "genparams":{"rate":"Int", "width":"Int"} + }, + "div":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "lutN":{ + "typegen":"commonlib.lutNType", + "genparams":{"N":"Int"}, + "modules":[ + [{"N":["Int",3]},{ + "type":["Record",[ + ["in",["Array",3,"BitIn"]], + ["out","Bit"] + ]], + "modparams":{"init":["BitVector",8]}, + "instances":{ + "lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"Arg","init"]} + } + }, + "connections":[ + ["self.in","lut.bit.in"], + ["self.out","lut.bit.out"] + ] + }] + ], + "metadata":{"verilog":{"definition":" assign out = init[in];","interface":["input [N-1:0] in","output out"],"parameters":["init"]}} + }, + "mult_high":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "mult_middle":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "muxn":{ + "typegen":"commonlib.muxN_type", + "genparams":{"N":"Int", "width":"Int"} + }, + "opn":{ + "typegen":"commonlib.opN_type", + "genparams":{"N":"Int", "operator":"String", "width":"Int"} + }, + "reg_array":{ + "typegen":"coreir.regArrayTG", + "genparams":{"has_clr":"Bool", "has_en":"Bool", "has_rst":"Bool", "init":"Int", "type":"CoreIRType"}, + "defaultgenargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "init":["Int",0]} + }, + "reshape":{ + "typegen":"commonlib.reshape_type", + "genparams":{"input_type":"CoreIRType", "output_type":"CoreIRType"} + }, + "sclamp":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "serializer":{ + "typegen":"commonlib.serializer_type", + "genparams":{"rate":"Int", "width":"Int"} + }, + "smax":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "smin":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "transpose":{ + "typegen":"commonlib.transpose_type", + "genparams":{"input_type":"CoreIRType"} + }, + "transpose_reshape":{ + "typegen":"commonlib.reshape_type", + "genparams":{"input_type":"CoreIRType", "output_type":"CoreIRType"} + }, + "uclamp":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "umax":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "umin":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + } + }, + "typegens":{ + "accumulation_register_type":[{"iterations":"Int", "width":"Int"},"implicit"], + "bitopN_type":[{"N":"Int", "operator":"String"},"implicit"], + "counter_type":[{"inc":"Int", "max":"Int", "min":"Int", "width":"Int"},"implicit"], + "deserializer_type":[{"rate":"Int", "width":"Int"},"implicit"], + "lutNType":[{"N":"Int"},"sparse",[ + [{"N":["Int",3]},["Record",[["in",["Array",3,"BitIn"]],["out","Bit"]]]] + ]], + "muxN_type":[{"N":"Int", "width":"Int"},"implicit"], + "opN_type":[{"N":"Int", "operator":"String", "width":"Int"},"implicit"], + "reshape_type":[{"input_type":"CoreIRType", "output_type":"CoreIRType"},"implicit"], + "serializer_type":[{"rate":"Int", "width":"Int"},"implicit"], + "transpose_type":[{"input_type":"CoreIRType"},"implicit"] + } + }, + "global":{ + "modules":{ + "complex_mem_pond":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["reset","BitIn"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read_en","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_en","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,32,192],"dimensionality":4,"extent":[2,4,6,6],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,48]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,192],"dimensionality":4,"extent":[8,4,6,6],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,8,24,72,1229,4916],"dimensionality":6,"extent":[2,3,3,4,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,48,2,8,48],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,2,0,0]},"tb2out_0":{"cycle_starting_addr":[1155],"cycle_stride":[1,8,24,72,1229,4916],"dimensionality":6,"extent":[8,3,3,4,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "input_pond_stencil$cgpl_ctrl_U11_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$cgpl_ctrl_U11_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1370],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "input_pond_stencil$cgpl_ctrl_U2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$cgpl_ctrl_U2_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1154],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "input_pond_stencil$cgpl_ctrl_U5_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$cgpl_ctrl_U5_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1226],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "input_pond_stencil$cgpl_ctrl_U8_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$cgpl_ctrl_U8_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1298],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U1"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1152],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U4"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1080],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U7"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1008],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_3_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_3_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U10"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[936],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ + "genref":"cgralib.IO", + "genargs":{"width":["Int",16]}, + "modargs":{"mode":["String","out"]}, + "metadata":{"in2glb_0":{"cycle_starting_addr":[20816],"cycle_stride":[1],"dimensionality":1,"extent":[48],"write_data_starting_addr":[0],"write_data_stride":[1]}} + }, + "io16in_input_host_stencil_op_hcompute_input_cgra_stencil_read_0":{ + "genref":"cgralib.IO", + "genargs":{"width":["Int",16]}, + "modargs":{"mode":["String","in"]}, + "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[1152],"read_data_starting_addr":[0],"read_data_stride":[1]}} + }, + "io16in_kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_0":{ + "genref":"cgralib.IO", + "genargs":{"width":["Int",16]}, + "modargs":{"mode":["String","in"]}, + "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[864],"read_data_starting_addr":[0],"read_data_stride":[1]}} + }, + "io1_hw_output_stencil_op_hcompute_hw_output_stencil_write_valid":{ + "modref":"cgralib.BitIO", + "modargs":{"mode":["String","out"]} + }, + "io1in_reset":{ + "modref":"cgralib.BitIO", + "modargs":{"mode":["String","in"]} + }, + "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U13"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,32,96,288],"dimensionality":5,"extent":[2,4,3,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,96,288],"dimensionality":5,"extent":[8,4,3,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[1441],"cycle_stride":[4,8,216,1229],"dimensionality":4,"extent":[2,27,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0]},"tb2out_0":{"cycle_starting_addr":[1443],"cycle_stride":[1,8,216,1229],"dimensionality":4,"extent":[8,27,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U15_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U15_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1442],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U18_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U18_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1450],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U21_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U21_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1458],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U24_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U24_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1658],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U27_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U27_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1666],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U30_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U30_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1674],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U33_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U33_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1874],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U36_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U36_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1882],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U39_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U39_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1890],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U42_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U42_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[2090],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U45_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U45_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[2098],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U48_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U48_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U49"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[2106],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U14"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[864],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_10_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_10_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U44"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[208],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_11_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_11_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U47"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[200],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U17"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[856],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U20"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[848],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_3_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_3_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U23"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[648],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_4_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_4_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U26"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[640],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_5_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_5_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U29"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[632],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_6_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_6_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U32"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[432],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_7_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_7_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U35"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[424],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_8_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_8_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U38"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[416],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_9_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_9_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U41"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[216],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "op_hcompute_hw_output_stencil_port_controller_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U70"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[20816],"cycle_stride":[1,4,16],"dimensionality":3,"extent":[4,4,3]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "op_hcompute_output_pond_stencil$inner_compute$const_p0__677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "op_hcompute_output_pond_stencil$inner_compute$const_p0__6771":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "op_hcompute_output_pond_stencil$inner_compute$const_p0__6772":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$add_698_704_705$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$add_699_703_704$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$add_700_702_703$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_701_702$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$add_731_737_738$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$add_732_736_737$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$add_733_735_736$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$add_output_pond_stencil_2_734_735$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$add_764_770_771$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$add_765_769_770$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$add_766_768_769$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$add_output_pond_stencil_3_767_768$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "output_cgra_stencil$_U54_mux$mux":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","combined"], "width":["Int",16]}, + "modargs":{"alu_op":["String","sel"], "bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "flag_sel":["String","pe"], "lut_value":[["BitVector",8],"8'h00"], "signed":["Bool",false]} + }, + "output_cgra_stencil$_U59_mux$mux":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","combined"], "width":["Int",16]}, + "modargs":{"alu_op":["String","sel"], "bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "flag_sel":["String","pe"], "lut_value":[["BitVector",8],"8'h00"], "signed":["Bool",false]} + }, + "output_cgra_stencil$dataout_pt_mux_ctrl__U52_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_cgra_stencil$dataout_pt_mux_ctrl__U52_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[20816],"cycle_stride":[1,4],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "output_cgra_stencil$dataout_pt_mux_ctrl__U57_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_cgra_stencil$dataout_pt_mux_ctrl__U57_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[20832],"cycle_stride":[1,4],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U50"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[2379],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20816],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}}], "mode":["String","pond"]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U55"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[2380],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20832],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}}], "mode":["String","pond"]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U60"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[2381],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20848],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}}], "mode":["String","pond"]} + }, + "output_pond_stencil$cgpl_ctrl_U62_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$cgpl_ctrl_U62_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U63"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1151],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "output_pond_stencil$cgpl_ctrl_U65_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$cgpl_ctrl_U65_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1152],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "output_pond_stencil$cgpl_ctrl_U68_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$cgpl_ctrl_U68_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U69"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1153],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U61"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[1155],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1155],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[0],"read_data_stride":[0]}}], "mode":["String","pond"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U64"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[1154],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[1],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[1],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1154],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[1],"read_data_stride":[0]}}], "mode":["String","pond"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U67"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[1153],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[2],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[2],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1153],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[2],"read_data_stride":[0]}}], "mode":["String","pond"]} + } + }, + "connections":[ + ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["io16in_input_host_stencil_op_hcompute_input_cgra_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.data_in_pond_0","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_1_garnet.data_in_pond_0","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_2_garnet.data_in_pond_0","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_3_garnet.data_in_pond_0","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], + ["io1in_reset.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.flush"], + ["input_pond_stencil$cgpl_ctrl_U11_garnet.clk_en","input_pond_stencil$cgpl_ctrl_U11_clk_en_const_lutcnst.bit.out"], + ["io1in_reset.out","input_pond_stencil$cgpl_ctrl_U11_garnet.flush"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_3_garnet.flush","input_pond_stencil$cgpl_ctrl_U11_garnet.stencil_valid"], + ["input_pond_stencil$cgpl_ctrl_U2_garnet.clk_en","input_pond_stencil$cgpl_ctrl_U2_clk_en_const_lutcnst.bit.out"], + ["io1in_reset.out","input_pond_stencil$cgpl_ctrl_U2_garnet.flush"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.flush","input_pond_stencil$cgpl_ctrl_U2_garnet.stencil_valid"], + ["input_pond_stencil$cgpl_ctrl_U5_garnet.clk_en","input_pond_stencil$cgpl_ctrl_U5_clk_en_const_lutcnst.bit.out"], + ["io1in_reset.out","input_pond_stencil$cgpl_ctrl_U5_garnet.flush"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_1_garnet.flush","input_pond_stencil$cgpl_ctrl_U5_garnet.stencil_valid"], + ["input_pond_stencil$cgpl_ctrl_U8_garnet.clk_en","input_pond_stencil$cgpl_ctrl_U8_clk_en_const_lutcnst.bit.out"], + ["io1in_reset.out","input_pond_stencil$cgpl_ctrl_U8_garnet.flush"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_2_garnet.flush","input_pond_stencil$cgpl_ctrl_U8_garnet.stencil_valid"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.clk_en","input_pond_stencil$ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.data_out_pond_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_1_garnet.clk_en","input_pond_stencil$ub_input_pond_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_1_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_1_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_1_garnet.data_out_pond_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_2_garnet.clk_en","input_pond_stencil$ub_input_pond_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_2_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_2_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_2_garnet.data_out_pond_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_3_garnet.clk_en","input_pond_stencil$ub_input_pond_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_3_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_3_garnet.data_out_pond_0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_3_garnet.data_out_pond_0"], + ["output_cgra_stencil$_U54_mux$mux.data.out","io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0.in"], + ["kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_in_0","io16in_kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_0.out"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_op_hcompute_hw_output_stencil_write_valid.in"], + ["kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U15_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U18_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U21_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U24_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U27_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U30_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U33_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U36_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U39_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U42_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U45_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U48_garnet.flush","io1in_reset.out"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.flush","io1in_reset.out"], + ["output_cgra_stencil$dataout_pt_mux_ctrl__U52_garnet.flush","io1in_reset.out"], + ["output_cgra_stencil$dataout_pt_mux_ctrl__U57_garnet.flush","io1in_reset.out"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.flush","io1in_reset.out"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.flush","io1in_reset.out"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.flush","io1in_reset.out"], + ["output_pond_stencil$cgpl_ctrl_U62_garnet.flush","io1in_reset.out"], + ["output_pond_stencil$cgpl_ctrl_U65_garnet.flush","io1in_reset.out"], + ["output_pond_stencil$cgpl_ctrl_U68_garnet.flush","io1in_reset.out"], + ["kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.clk_en","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_10_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_11_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_1_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_2_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_3_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_4_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_5_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_6_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_7_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_8_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_9_garnet.data_in_pond_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$cgpl_ctrl_U15_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U15_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U15_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U18_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U18_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_1_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U18_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U21_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U21_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_2_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U21_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U24_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U24_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_3_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U24_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U27_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U27_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_4_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U27_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U30_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U30_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_5_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U30_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U33_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U33_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_6_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U33_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U36_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U36_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_7_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U36_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U39_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U39_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_8_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U39_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U42_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U42_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_9_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U42_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U45_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U45_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_10_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U45_garnet.stencil_valid"], + ["kernel_pond_stencil$cgpl_ctrl_U48_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U48_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_11_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U48_garnet.stencil_valid"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_10_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_10_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_10_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_11_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_11_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_11_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_1_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_1_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_2_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_2_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_3_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_3_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_4_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_4_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_5_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_5_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_6_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_6_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_7_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_7_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_7_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_8_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_8_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_8_garnet.data_out_pond_0"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_9_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_9_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_9_garnet.data_out_pond_0"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.clk_en","op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_1_garnet.data_in_pond_1","op_hcompute_output_pond_stencil$inner_compute$const_p0__677.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_in_pond_1","op_hcompute_output_pond_stencil$inner_compute$const_p0__6771.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_2_garnet.data_in_pond_0","op_hcompute_output_pond_stencil$inner_compute$const_p0__6772.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_698_704_705$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_1$inner_compute$add_699_703_704$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_698_704_705$binop.data.in.1"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_in_pond_0","op_hcompute_output_pond_stencil_1$inner_compute$add_698_704_705$binop.data.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_699_703_704$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_1$inner_compute$add_700_702_703$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_699_703_704$binop.data.in.1"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_700_702_703$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_701_702$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_700_702_703$binop.data.in.1"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_out_pond_1","op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_701_702$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_701_702$binop.data.in.1"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.out","op_hcompute_output_pond_stencil_2$inner_compute$add_731_737_738$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$add_732_736_737$binop.data.out","op_hcompute_output_pond_stencil_2$inner_compute$add_731_737_738$binop.data.in.1"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_1_garnet.data_in_pond_0","op_hcompute_output_pond_stencil_2$inner_compute$add_731_737_738$binop.data.out"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.out","op_hcompute_output_pond_stencil_2$inner_compute$add_732_736_737$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$add_733_735_736$binop.data.out","op_hcompute_output_pond_stencil_2$inner_compute$add_732_736_737$binop.data.in.1"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.out","op_hcompute_output_pond_stencil_2$inner_compute$add_733_735_736$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$add_output_pond_stencil_2_734_735$binop.data.out","op_hcompute_output_pond_stencil_2$inner_compute$add_733_735_736$binop.data.in.1"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_1_garnet.data_out_pond_1","op_hcompute_output_pond_stencil_2$inner_compute$add_output_pond_stencil_2_734_735$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_2$inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.out","op_hcompute_output_pond_stencil_2$inner_compute$add_output_pond_stencil_2_734_735$binop.data.in.1"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.out","op_hcompute_output_pond_stencil_3$inner_compute$add_764_770_771$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$add_765_769_770$binop.data.out","op_hcompute_output_pond_stencil_3$inner_compute$add_764_770_771$binop.data.in.1"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_2_garnet.data_in_pond_1","op_hcompute_output_pond_stencil_3$inner_compute$add_764_770_771$binop.data.out"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.out","op_hcompute_output_pond_stencil_3$inner_compute$add_765_769_770$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$add_766_768_769$binop.data.out","op_hcompute_output_pond_stencil_3$inner_compute$add_765_769_770$binop.data.in.1"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.out","op_hcompute_output_pond_stencil_3$inner_compute$add_766_768_769$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$add_output_pond_stencil_3_767_768$binop.data.out","op_hcompute_output_pond_stencil_3$inner_compute$add_766_768_769$binop.data.in.1"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_2_garnet.data_out_pond_1","op_hcompute_output_pond_stencil_3$inner_compute$add_output_pond_stencil_3_767_768$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_3$inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.out","op_hcompute_output_pond_stencil_3$inner_compute$add_output_pond_stencil_3_767_768$binop.data.in.1"], + ["output_cgra_stencil$dataout_pt_mux_ctrl__U52_garnet.stencil_valid","output_cgra_stencil$_U54_mux$mux.bit.in.0"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_out_pond_0","output_cgra_stencil$_U54_mux$mux.data.in.0"], + ["output_cgra_stencil$_U59_mux$mux.data.out","output_cgra_stencil$_U54_mux$mux.data.in.1"], + ["output_cgra_stencil$dataout_pt_mux_ctrl__U57_garnet.stencil_valid","output_cgra_stencil$_U59_mux$mux.bit.in.0"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_out_pond_0","output_cgra_stencil$_U59_mux$mux.data.in.0"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_out_pond_0","output_cgra_stencil$_U59_mux$mux.data.in.1"], + ["output_cgra_stencil$dataout_pt_mux_ctrl__U52_garnet.clk_en","output_cgra_stencil$dataout_pt_mux_ctrl__U52_clk_en_const_lutcnst.bit.out"], + ["output_cgra_stencil$dataout_pt_mux_ctrl__U57_garnet.clk_en","output_cgra_stencil$dataout_pt_mux_ctrl__U57_clk_en_const_lutcnst.bit.out"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.clk_en","output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_out_pond_0","output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_pond_0"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.clk_en","output_cgra_stencil$ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_1_garnet.data_out_pond_0","output_cgra_stencil$ub_output_cgra_stencil_BANK_1_garnet.data_in_pond_0"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.clk_en","output_cgra_stencil$ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_2_garnet.data_out_pond_0","output_cgra_stencil$ub_output_cgra_stencil_BANK_2_garnet.data_in_pond_0"], + ["output_pond_stencil$cgpl_ctrl_U62_garnet.clk_en","output_pond_stencil$cgpl_ctrl_U62_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.flush","output_pond_stencil$cgpl_ctrl_U62_garnet.stencil_valid"], + ["output_pond_stencil$cgpl_ctrl_U65_garnet.clk_en","output_pond_stencil$cgpl_ctrl_U65_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_1_garnet.flush","output_pond_stencil$cgpl_ctrl_U65_garnet.stencil_valid"], + ["output_pond_stencil$cgpl_ctrl_U68_garnet.clk_en","output_pond_stencil$cgpl_ctrl_U68_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_2_garnet.flush","output_pond_stencil$cgpl_ctrl_U68_garnet.stencil_valid"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.clk_en","output_pond_stencil$ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_1_garnet.clk_en","output_pond_stencil$ub_output_pond_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_2_garnet.clk_en","output_pond_stencil$ub_output_pond_stencil_BANK_2_clk_en_const_lutcnst.bit.out"] + ] + }, + "cu_op_hcompute_hw_output_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_cgra_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.output_cgra_stencil_op_hcompute_hw_output_stencil_read.0","self.hw_output_stencil_op_hcompute_hw_output_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_cgra_stencil_op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","self.input_cgra_stencil_op_hcompute_input_cgra_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_cgra_stencil_op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_pond_stencil_op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.input_pond_stencil_op_hcompute_input_pond_stencil_write.0","self.input_cgra_stencil_op_hcompute_input_pond_stencil_read.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read.0","self.kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write.0","self.kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_read.0","self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_1_read.0","self.output_cgra_stencil_op_hcompute_output_cgra_stencil_1_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_2_read.0","self.output_cgra_stencil_op_hcompute_output_cgra_stencil_2_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "PE_init_U86":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "_U84":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "_U85":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["_U84.out","PE_init_U86.data.in.0"], + ["_U85.out","PE_init_U86.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_write.0","PE_init_U86.data.out"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute$add_698_704_705$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_699_703_704$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_700_702_703$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_output_pond_stencil_1_701_702$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.out","inner_compute$add_698_704_705$binop.data.in.0"], + ["inner_compute$add_699_703_704$binop.data.out","inner_compute$add_698_704_705$binop.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_write.0","inner_compute$add_698_704_705$binop.data.out"], + ["inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.out","inner_compute$add_699_703_704$binop.data.in.0"], + ["inner_compute$add_700_702_703$binop.data.out","inner_compute$add_699_703_704$binop.data.in.1"], + ["inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.out","inner_compute$add_700_702_703$binop.data.in.0"], + ["inner_compute$add_output_pond_stencil_1_701_702$binop.data.out","inner_compute$add_700_702_703$binop.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute$add_output_pond_stencil_1_701_702$binop.data.in.0"], + ["inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.out","inner_compute$add_output_pond_stencil_1_701_702$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.1","inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.1","inner_compute$mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.2","inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.2","inner_compute$mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.3","inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.3","inner_compute$mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.in.1"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute$add_731_737_738$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_732_736_737$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_733_735_736$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_output_pond_stencil_2_734_735$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.out","inner_compute$add_731_737_738$binop.data.in.0"], + ["inner_compute$add_732_736_737$binop.data.out","inner_compute$add_731_737_738$binop.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_2_write.0","inner_compute$add_731_737_738$binop.data.out"], + ["inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.out","inner_compute$add_732_736_737$binop.data.in.0"], + ["inner_compute$add_733_735_736$binop.data.out","inner_compute$add_732_736_737$binop.data.in.1"], + ["inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.out","inner_compute$add_733_735_736$binop.data.in.0"], + ["inner_compute$add_output_pond_stencil_2_734_735$binop.data.out","inner_compute$add_733_735_736$binop.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_2_read.0","inner_compute$add_output_pond_stencil_2_734_735$binop.data.in.0"], + ["inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.out","inner_compute$add_output_pond_stencil_2_734_735$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.0","inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.0","inner_compute$mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.1","inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.1","inner_compute$mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.2","inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.2","inner_compute$mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_2_read.3","inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_2_read.3","inner_compute$mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.in.1"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_3":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_3_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute$add_764_770_771$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_765_769_770$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_766_768_769$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$add_output_pond_stencil_3_767_768$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.out","inner_compute$add_764_770_771$binop.data.in.0"], + ["inner_compute$add_765_769_770$binop.data.out","inner_compute$add_764_770_771$binop.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_3_write.0","inner_compute$add_764_770_771$binop.data.out"], + ["inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.out","inner_compute$add_765_769_770$binop.data.in.0"], + ["inner_compute$add_766_768_769$binop.data.out","inner_compute$add_765_769_770$binop.data.in.1"], + ["inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.out","inner_compute$add_766_768_769$binop.data.in.0"], + ["inner_compute$add_output_pond_stencil_3_767_768$binop.data.out","inner_compute$add_766_768_769$binop.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_3_read.0","inner_compute$add_output_pond_stencil_3_767_768$binop.data.in.0"], + ["inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.out","inner_compute$add_output_pond_stencil_3_767_768$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.0","inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.0","inner_compute$mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.1","inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.1","inner_compute$mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.2","inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.2","inner_compute$mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.in.1"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_3_read.3","inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_3_read.3","inner_compute$mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.in.1"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_cgra_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_pond_stencil":{ + "type":["Record",[ + ["out_input_pond_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_pond_stencil","self.in0_input_cgra_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["out_kernel_pond_stencil",["Array",16,"Bit"]], + ["in0_kernel_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_pond_stencil","self.in0_kernel_cgra_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_pond_stencil":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "PE_init_U89":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "_U87":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "_U88":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["_U87.out","PE_init_U89.data.in.0"], + ["_U88.out","PE_init_U89.data.in.1"], + ["self.out_output_pond_stencil","PE_init_U89.data.out"] + ] + }, + "hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_698_704_705$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_699_703_704$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_700_702_703$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_output_pond_stencil_1_701_702$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.out","add_698_704_705$binop.data.in.0"], + ["add_699_703_704$binop.data.out","add_698_704_705$binop.data.in.1"], + ["self.out_output_pond_stencil","add_698_704_705$binop.data.out"], + ["mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.out","add_699_703_704$binop.data.in.0"], + ["add_700_702_703$binop.data.out","add_699_703_704$binop.data.in.1"], + ["mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.out","add_700_702_703$binop.data.in.0"], + ["add_output_pond_stencil_1_701_702$binop.data.out","add_700_702_703$binop.data.in.1"], + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_1_701_702$binop.data.in.0"], + ["mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.out","add_output_pond_stencil_1_701_702$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.in.0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_698$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.1","mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.in.0"], + ["self.in0_input_pond_stencil.1","mul_kernel_pond_stencil_2_input_pond_stencil_2_699$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.2","mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.in.0"], + ["self.in0_input_pond_stencil.2","mul_kernel_pond_stencil_3_input_pond_stencil_3_700$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.3","mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.in.0"], + ["self.in0_input_pond_stencil.3","mul_kernel_pond_stencil_4_input_pond_stencil_4_701$binop.data.in.1"] + ] + }, + "hcompute_output_pond_stencil_2":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_731_737_738$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_732_736_737$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_733_735_736$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_output_pond_stencil_2_734_735$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.out","add_731_737_738$binop.data.in.0"], + ["add_732_736_737$binop.data.out","add_731_737_738$binop.data.in.1"], + ["self.out_output_pond_stencil","add_731_737_738$binop.data.out"], + ["mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.out","add_732_736_737$binop.data.in.0"], + ["add_733_735_736$binop.data.out","add_732_736_737$binop.data.in.1"], + ["mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.out","add_733_735_736$binop.data.in.0"], + ["add_output_pond_stencil_2_734_735$binop.data.out","add_733_735_736$binop.data.in.1"], + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_2_734_735$binop.data.in.0"], + ["mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.out","add_output_pond_stencil_2_734_735$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.in.0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_5_input_pond_stencil_5_731$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.1","mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.in.0"], + ["self.in0_input_pond_stencil.1","mul_kernel_pond_stencil_6_input_pond_stencil_6_732$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.2","mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.in.0"], + ["self.in0_input_pond_stencil.2","mul_kernel_pond_stencil_7_input_pond_stencil_7_733$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.3","mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.in.0"], + ["self.in0_input_pond_stencil.3","mul_kernel_pond_stencil_8_input_pond_stencil_8_734$binop.data.in.1"] + ] + }, + "hcompute_output_pond_stencil_3":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_764_770_771$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_765_769_770$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_766_768_769$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "add_output_pond_stencil_3_767_768$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.out","add_764_770_771$binop.data.in.0"], + ["add_765_769_770$binop.data.out","add_764_770_771$binop.data.in.1"], + ["self.out_output_pond_stencil","add_764_770_771$binop.data.out"], + ["mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.out","add_765_769_770$binop.data.in.0"], + ["add_766_768_769$binop.data.out","add_765_769_770$binop.data.in.1"], + ["mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.out","add_766_768_769$binop.data.in.0"], + ["add_output_pond_stencil_3_767_768$binop.data.out","add_766_768_769$binop.data.in.1"], + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_3_767_768$binop.data.in.0"], + ["mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.out","add_output_pond_stencil_3_767_768$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.in.0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_10_input_pond_stencil_10_765$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.1","mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.in.0"], + ["self.in0_input_pond_stencil.1","mul_kernel_pond_stencil_11_input_pond_stencil_11_766$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.2","mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.in.0"], + ["self.in0_input_pond_stencil.2","mul_kernel_pond_stencil_12_input_pond_stencil_12_767$binop.data.in.1"], + ["self.in1_kernel_pond_stencil.3","mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.in.0"], + ["self.in0_input_pond_stencil.3","mul_kernel_pond_stencil_9_input_pond_stencil_9_764$binop.data.in.1"] + ] + }, + "input_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_input_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_input_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,32,192],"dimensionality":4,"extent":[2,4,6,6],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,48]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,192],"dimensionality":4,"extent":[8,4,6,6],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[1153],"cycle_stride":[4,8,24,72,1229,4916],"dimensionality":6,"extent":[2,3,3,4,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,48,2,8,48],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,2,0,0]},"tb2out_0":{"cycle_starting_addr":[1155],"cycle_stride":[1,8,24,72,1229,4916],"dimensionality":6,"extent":[8,3,3,4,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + } + }, + "connections":[ + ["ub_input_cgra_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_input_cgra_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_input_cgra_stencil_write.0"], + ["ub_input_cgra_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_input_pond_stencil_read.0"], + ["ub_input_cgra_stencil_BANK_0_garnet.flush","self.reset"], + ["ub_input_cgra_stencil_BANK_0_garnet.clk_en","ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "input_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_3_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U11_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U11_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1370],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U2_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1154],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U5_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U5_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1226],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U8_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U8_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1298],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_input_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U1"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1152],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_input_pond_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_input_pond_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U4"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1080],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_input_pond_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_input_pond_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U7"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[1008],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_input_pond_stencil_BANK_3_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_input_pond_stencil_BANK_3_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U10"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[936],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + } + }, + "connections":[ + ["cgpl_ctrl_U11_garnet.clk_en","cgpl_ctrl_U11_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U11_garnet.clk"], + ["self.reset","cgpl_ctrl_U11_garnet.flush"], + ["ub_input_pond_stencil_BANK_3_garnet.flush","cgpl_ctrl_U11_garnet.stencil_valid"], + ["cgpl_ctrl_U2_garnet.clk_en","cgpl_ctrl_U2_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U2_garnet.clk"], + ["self.reset","cgpl_ctrl_U2_garnet.flush"], + ["ub_input_pond_stencil_BANK_0_garnet.flush","cgpl_ctrl_U2_garnet.stencil_valid"], + ["cgpl_ctrl_U5_garnet.clk_en","cgpl_ctrl_U5_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U5_garnet.clk"], + ["self.reset","cgpl_ctrl_U5_garnet.flush"], + ["ub_input_pond_stencil_BANK_1_garnet.flush","cgpl_ctrl_U5_garnet.stencil_valid"], + ["cgpl_ctrl_U8_garnet.clk_en","cgpl_ctrl_U8_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U8_garnet.clk"], + ["self.reset","cgpl_ctrl_U8_garnet.flush"], + ["ub_input_pond_stencil_BANK_2_garnet.flush","cgpl_ctrl_U8_garnet.stencil_valid"], + ["ub_input_pond_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_input_pond_stencil_BANK_1_garnet.clk","self.clk"], + ["ub_input_pond_stencil_BANK_2_garnet.clk","self.clk"], + ["ub_input_pond_stencil_BANK_3_garnet.clk","self.clk"], + ["ub_input_pond_stencil_BANK_0_garnet.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_1_garnet.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_2_garnet.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_3_garnet.data_in_pond_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_0_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_input_pond_stencil_BANK_1_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.1"], + ["ub_input_pond_stencil_BANK_2_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.2"], + ["ub_input_pond_stencil_BANK_3_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.3"], + ["ub_input_pond_stencil_BANK_0_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.0"], + ["ub_input_pond_stencil_BANK_1_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.1"], + ["ub_input_pond_stencil_BANK_2_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.2"], + ["ub_input_pond_stencil_BANK_3_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.3"], + ["ub_input_pond_stencil_BANK_1_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.0"], + ["ub_input_pond_stencil_BANK_2_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.1"], + ["ub_input_pond_stencil_BANK_3_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.2"], + ["ub_input_pond_stencil_BANK_0_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.3"], + ["ub_input_pond_stencil_BANK_0_garnet.clk_en","ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["ub_input_pond_stencil_BANK_1_garnet.clk_en","ub_input_pond_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["ub_input_pond_stencil_BANK_2_garnet.clk_en","ub_input_pond_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], + ["ub_input_pond_stencil_BANK_3_garnet.clk_en","ub_input_pond_stencil_BANK_3_clk_en_const_lutcnst.bit.out"] + ] + }, + "kernel_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_kernel_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U13"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,32,96,288],"dimensionality":5,"extent":[2,4,3,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8,24,72]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,32,96,288],"dimensionality":5,"extent":[8,4,3,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0,0]},"sram2tb_0":{"cycle_starting_addr":[1441],"cycle_stride":[4,8,216,1229],"dimensionality":4,"extent":[2,27,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,8,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,2,0]},"tb2out_0":{"cycle_starting_addr":[1443],"cycle_stride":[1,8,216,1229],"dimensionality":4,"extent":[8,27,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,8,0]}}], "init":["Json",null], "mode":["String","lake"]} + } + }, + "connections":[ + ["ub_kernel_cgra_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_kernel_cgra_stencil_write.0"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_kernel_pond_stencil_read.0"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.flush","self.reset"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.clk_en","ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "kernel_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_2_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_3_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_3_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U15_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U15_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1442],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U18_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U18_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U19"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1450],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U21_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U21_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U22"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1458],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U24_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U24_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U25"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1658],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U27_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U27_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U28"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1666],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U30_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U30_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U31"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1674],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U33_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U33_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U34"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1874],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U36_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U36_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U37"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1882],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U39_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U39_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U40"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1890],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U42_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U42_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U43"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[2090],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U45_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U45_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U46"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[2098],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U48_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U48_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U49"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[2106],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U14"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[864],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_10_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_10_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U44"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[208],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_11_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_11_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U47"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[200],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U17"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[856],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U20"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[848],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_3_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_3_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U23"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[648],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_4_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_4_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U26"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[640],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_5_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_5_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U29"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[632],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_6_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_6_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U32"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[432],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_7_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_7_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U35"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[424],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_8_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_8_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U38"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[416],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + }, + "ub_kernel_pond_stencil_BANK_9_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_9_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U41"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1,24],"dimensionality":2,"extent":[8,9],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"regfile2out_0":{"cycle_starting_addr":[216],"cycle_stride":[1,9],"dimensionality":2,"extent":[9,8],"read_data_starting_addr":[0],"read_data_stride":[8,1]}}], "mode":["String","pond"]} + } + }, + "connections":[ + ["cgpl_ctrl_U15_garnet.clk_en","cgpl_ctrl_U15_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U15_garnet.clk"], + ["self.reset","cgpl_ctrl_U15_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_0_garnet.flush","cgpl_ctrl_U15_garnet.stencil_valid"], + ["cgpl_ctrl_U18_garnet.clk_en","cgpl_ctrl_U18_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U18_garnet.clk"], + ["self.reset","cgpl_ctrl_U18_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_1_garnet.flush","cgpl_ctrl_U18_garnet.stencil_valid"], + ["cgpl_ctrl_U21_garnet.clk_en","cgpl_ctrl_U21_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U21_garnet.clk"], + ["self.reset","cgpl_ctrl_U21_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_2_garnet.flush","cgpl_ctrl_U21_garnet.stencil_valid"], + ["cgpl_ctrl_U24_garnet.clk_en","cgpl_ctrl_U24_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U24_garnet.clk"], + ["self.reset","cgpl_ctrl_U24_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_3_garnet.flush","cgpl_ctrl_U24_garnet.stencil_valid"], + ["cgpl_ctrl_U27_garnet.clk_en","cgpl_ctrl_U27_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U27_garnet.clk"], + ["self.reset","cgpl_ctrl_U27_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_4_garnet.flush","cgpl_ctrl_U27_garnet.stencil_valid"], + ["cgpl_ctrl_U30_garnet.clk_en","cgpl_ctrl_U30_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U30_garnet.clk"], + ["self.reset","cgpl_ctrl_U30_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_5_garnet.flush","cgpl_ctrl_U30_garnet.stencil_valid"], + ["cgpl_ctrl_U33_garnet.clk_en","cgpl_ctrl_U33_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U33_garnet.clk"], + ["self.reset","cgpl_ctrl_U33_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_6_garnet.flush","cgpl_ctrl_U33_garnet.stencil_valid"], + ["cgpl_ctrl_U36_garnet.clk_en","cgpl_ctrl_U36_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U36_garnet.clk"], + ["self.reset","cgpl_ctrl_U36_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_7_garnet.flush","cgpl_ctrl_U36_garnet.stencil_valid"], + ["cgpl_ctrl_U39_garnet.clk_en","cgpl_ctrl_U39_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U39_garnet.clk"], + ["self.reset","cgpl_ctrl_U39_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_8_garnet.flush","cgpl_ctrl_U39_garnet.stencil_valid"], + ["cgpl_ctrl_U42_garnet.clk_en","cgpl_ctrl_U42_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U42_garnet.clk"], + ["self.reset","cgpl_ctrl_U42_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_9_garnet.flush","cgpl_ctrl_U42_garnet.stencil_valid"], + ["cgpl_ctrl_U45_garnet.clk_en","cgpl_ctrl_U45_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U45_garnet.clk"], + ["self.reset","cgpl_ctrl_U45_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_10_garnet.flush","cgpl_ctrl_U45_garnet.stencil_valid"], + ["cgpl_ctrl_U48_garnet.clk_en","cgpl_ctrl_U48_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U48_garnet.clk"], + ["self.reset","cgpl_ctrl_U48_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_11_garnet.flush","cgpl_ctrl_U48_garnet.stencil_valid"], + ["ub_kernel_pond_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_10_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_11_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_1_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_2_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_3_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_4_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_5_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_6_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_7_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_8_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_9_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_0_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_10_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_11_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_1_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_2_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_3_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_4_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_5_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_6_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_7_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_8_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_9_garnet.data_in_pond_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_0_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_kernel_pond_stencil_BANK_3_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.1"], + ["ub_kernel_pond_stencil_BANK_6_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.2"], + ["ub_kernel_pond_stencil_BANK_9_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_1_read.3"], + ["ub_kernel_pond_stencil_BANK_1_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.0"], + ["ub_kernel_pond_stencil_BANK_4_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.1"], + ["ub_kernel_pond_stencil_BANK_7_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.2"], + ["ub_kernel_pond_stencil_BANK_10_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_2_read.3"], + ["ub_kernel_pond_stencil_BANK_5_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.0"], + ["ub_kernel_pond_stencil_BANK_8_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.1"], + ["ub_kernel_pond_stencil_BANK_11_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.2"], + ["ub_kernel_pond_stencil_BANK_2_garnet.data_out_pond_0","self.op_hcompute_output_pond_stencil_3_read.3"], + ["ub_kernel_pond_stencil_BANK_0_garnet.clk_en","ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_10_garnet.clk_en","ub_kernel_pond_stencil_BANK_10_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_11_garnet.clk_en","ub_kernel_pond_stencil_BANK_11_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_1_garnet.clk_en","ub_kernel_pond_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_2_garnet.clk_en","ub_kernel_pond_stencil_BANK_2_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_3_garnet.clk_en","ub_kernel_pond_stencil_BANK_3_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_4_garnet.clk_en","ub_kernel_pond_stencil_BANK_4_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_5_garnet.clk_en","ub_kernel_pond_stencil_BANK_5_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_6_garnet.clk_en","ub_kernel_pond_stencil_BANK_6_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_7_garnet.clk_en","ub_kernel_pond_stencil_BANK_7_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_8_garnet.clk_en","ub_kernel_pond_stencil_BANK_8_clk_en_const_lutcnst.bit.out"], + ["ub_kernel_pond_stencil_BANK_9_garnet.clk_en","ub_kernel_pond_stencil_BANK_9_clk_en_const_lutcnst.bit.out"] + ] + }, + "op_hcompute_hw_output_stencil_exe_start_pt__U72":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_read_start_pt__U71":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_write_start_pt__U73":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_exe_start_pt__U81":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_read_start_pt__U80":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_write_start_pt__U82":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_exe_start_pt__U76":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_read_start_pt__U75":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_write_start_pt__U77":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "output_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_output_cgra_stencil_2_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_2_write_extra_ctrl","BitIn"], + ["op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "_U54_mux$mux":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","combined"], "width":["Int",16]}, + "modargs":{"alu_op":["String","sel"], "bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "flag_sel":["String","pe"], "lut_value":[["BitVector",8],"8'h00"], "signed":["Bool",false]} + }, + "_U59_mux$mux":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","combined"], "width":["Int",16]}, + "modargs":{"alu_op":["String","sel"], "bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "flag_sel":["String","pe"], "lut_value":[["BitVector",8],"8'h00"], "signed":["Bool",false]} + }, + "dataout_pt_mux_ctrl__U52_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "dataout_pt_mux_ctrl__U52_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[20816],"cycle_stride":[1,4],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "dataout_pt_mux_ctrl__U57_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "dataout_pt_mux_ctrl__U57_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[20832],"cycle_stride":[1,4],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U50"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[2379],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20816],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}}], "mode":["String","pond"]} + }, + "ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_cgra_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U55"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[2380],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20832],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}}], "mode":["String","pond"]} + }, + "ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_cgra_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U60"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[2381],"cycle_stride":[1229],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20848],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}}], "mode":["String","pond"]} + } + }, + "connections":[ + ["dataout_pt_mux_ctrl__U52_garnet.stencil_valid","_U54_mux$mux.bit.in.0"], + ["ub_output_cgra_stencil_BANK_0_garnet.data_out_pond_0","_U54_mux$mux.data.in.0"], + ["_U59_mux$mux.data.out","_U54_mux$mux.data.in.1"], + ["self.op_hcompute_hw_output_stencil_read.0","_U54_mux$mux.data.out"], + ["dataout_pt_mux_ctrl__U57_garnet.stencil_valid","_U59_mux$mux.bit.in.0"], + ["ub_output_cgra_stencil_BANK_1_garnet.data_out_pond_0","_U59_mux$mux.data.in.0"], + ["ub_output_cgra_stencil_BANK_2_garnet.data_out_pond_0","_U59_mux$mux.data.in.1"], + ["dataout_pt_mux_ctrl__U52_garnet.clk_en","dataout_pt_mux_ctrl__U52_clk_en_const_lutcnst.bit.out"], + ["self.clk","dataout_pt_mux_ctrl__U52_garnet.clk"], + ["self.reset","dataout_pt_mux_ctrl__U52_garnet.flush"], + ["dataout_pt_mux_ctrl__U57_garnet.clk_en","dataout_pt_mux_ctrl__U57_clk_en_const_lutcnst.bit.out"], + ["self.clk","dataout_pt_mux_ctrl__U57_garnet.clk"], + ["self.reset","dataout_pt_mux_ctrl__U57_garnet.flush"], + ["ub_output_cgra_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_1_garnet.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_2_garnet.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_1_garnet.data_in_pond_0","self.op_hcompute_output_cgra_stencil_1_write.0"], + ["ub_output_cgra_stencil_BANK_2_garnet.data_in_pond_0","self.op_hcompute_output_cgra_stencil_2_write.0"], + ["ub_output_cgra_stencil_BANK_0_garnet.data_in_pond_0","self.op_hcompute_output_cgra_stencil_write.0"], + ["ub_output_cgra_stencil_BANK_0_garnet.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_1_garnet.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_2_garnet.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_0_garnet.clk_en","ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["ub_output_cgra_stencil_BANK_1_garnet.clk_en","ub_output_cgra_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["ub_output_cgra_stencil_BANK_2_garnet.clk_en","ub_output_cgra_stencil_BANK_2_clk_en_const_lutcnst.bit.out"] + ] + }, + "output_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_output_cgra_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_2_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_2_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_2_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_2_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_3_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_3_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_3_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_3_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "cgpl_ctrl_U62_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U62_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U63"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1151],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U65_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U65_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U66"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1152],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "cgpl_ctrl_U68_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U68_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U69"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1153],"cycle_stride":[1229,4916],"dimensionality":2,"extent":[4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U61"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[1155],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1155],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[0],"read_data_stride":[0]}}], "mode":["String","pond"]} + }, + "ub_output_pond_stencil_BANK_1_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_pond_stencil_BANK_1_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U64"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[1154],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[1],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[1],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[1],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1154],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[1],"read_data_stride":[0]}}], "mode":["String","pond"]} + }, + "ub_output_pond_stencil_BANK_2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_pond_stencil_BANK_2_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U67"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[2],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[1153],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[2],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[1227],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[2],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1153],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[2],"read_data_stride":[0]}}], "mode":["String","pond"]} + } + }, + "connections":[ + ["cgpl_ctrl_U62_garnet.clk_en","cgpl_ctrl_U62_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U62_garnet.clk"], + ["self.reset","cgpl_ctrl_U62_garnet.flush"], + ["ub_output_pond_stencil_BANK_0_garnet.flush","cgpl_ctrl_U62_garnet.stencil_valid"], + ["cgpl_ctrl_U65_garnet.clk_en","cgpl_ctrl_U65_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U65_garnet.clk"], + ["self.reset","cgpl_ctrl_U65_garnet.flush"], + ["ub_output_pond_stencil_BANK_1_garnet.flush","cgpl_ctrl_U65_garnet.stencil_valid"], + ["cgpl_ctrl_U68_garnet.clk_en","cgpl_ctrl_U68_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U68_garnet.clk"], + ["self.reset","cgpl_ctrl_U68_garnet.flush"], + ["ub_output_pond_stencil_BANK_2_garnet.flush","cgpl_ctrl_U68_garnet.stencil_valid"], + ["ub_output_pond_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_output_pond_stencil_BANK_1_garnet.clk","self.clk"], + ["ub_output_pond_stencil_BANK_2_garnet.clk","self.clk"], + ["ub_output_pond_stencil_BANK_1_garnet.data_out_pond_0","self.op_hcompute_output_cgra_stencil_1_read.0"], + ["ub_output_pond_stencil_BANK_2_garnet.data_out_pond_0","self.op_hcompute_output_cgra_stencil_2_read.0"], + ["ub_output_pond_stencil_BANK_0_garnet.data_out_pond_0","self.op_hcompute_output_cgra_stencil_read.0"], + ["ub_output_pond_stencil_BANK_0_garnet.data_out_pond_1","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_output_pond_stencil_BANK_0_garnet.data_in_pond_0","self.op_hcompute_output_pond_stencil_1_write.0"], + ["ub_output_pond_stencil_BANK_1_garnet.data_out_pond_1","self.op_hcompute_output_pond_stencil_2_read.0"], + ["ub_output_pond_stencil_BANK_1_garnet.data_in_pond_0","self.op_hcompute_output_pond_stencil_2_write.0"], + ["ub_output_pond_stencil_BANK_2_garnet.data_out_pond_1","self.op_hcompute_output_pond_stencil_3_read.0"], + ["ub_output_pond_stencil_BANK_2_garnet.data_in_pond_1","self.op_hcompute_output_pond_stencil_3_write.0"], + ["ub_output_pond_stencil_BANK_0_garnet.data_in_pond_1","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_1_garnet.data_in_pond_1","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_2_garnet.data_in_pond_0","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_0_garnet.clk_en","ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["ub_output_pond_stencil_BANK_1_garnet.clk_en","ub_output_pond_stencil_BANK_1_clk_en_const_lutcnst.bit.out"], + ["ub_output_pond_stencil_BANK_2_garnet.clk_en","ub_output_pond_stencil_BANK_2_clk_en_const_lutcnst.bit.out"] + ] + } + }, + "generators":{ + "delay_tile":{ + "typegen":"global.delay_tile_TG", + "genparams":{"delay":"Int"} + }, + "raw_dual_port_sram_tile":{ + "typegen":"global.raw_dual_port_sram_TG", + "genparams":{"depth":"Int"} + }, + "raw_quad_port_memtile":{ + "typegen":"global.raw_quad_port_memtile_TG", + "genparams":{"depth":"Int"} + }, + "tahoe":{ + "typegen":"global.tahoe_TG", + "genparams":{"depth":"Int"} + } + }, + "typegens":{ + "delay_tile_TG":[{"delay":"Int"},"implicit"], + "raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"], + "raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"], + "tahoe_TG":[{"depth":"Int"},"implicit"] + } + }, + "mantle":{ + "generators":{ + "add":{ + "typegen":"mantle.addType", + "genparams":{"has_cin":"Bool", "has_cout":"Bool", "width":"Int"}, + "defaultgenargs":{"has_cin":["Bool",false], "has_cout":["Bool",false]} + }, + "counter":{ + "typegen":"mantle.counter_type", + "genparams":{"has_en":"Bool", "has_max":"Bool", "has_srst":"Bool", "width":"Int"}, + "defaultgenargs":{"has_en":["Bool",false], "has_max":["Bool",false], "has_srst":["Bool",false]} + }, + "reg":{ + "typegen":"mantle.regType", + "genparams":{"has_clr":"Bool", "has_en":"Bool", "has_rst":"Bool", "width":"Int"}, + "modules":[ + [{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["clk",["Named","coreir.clkIn"]], + ["out",["Array",16,"Bit"]] + ]], + "modparams":{"init":["BitVector",16]}, + "defaultmodargs":{"init":[["BitVector",16],"16'h0000"]}, + "instances":{ + "reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"Arg","init"]} + } + }, + "connections":[ + ["self.clk","reg0.clk"], + ["self.in","reg0.in"], + ["self.out","reg0.out"] + ] + }] + ], + "defaultgenargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false]} + }, + "regCE":{ + "typegen":"mantle.regCEType", + "genparams":{"width":"Int"}, + "metadata":{"verilog":{"definition":" reg [width-1:0] value;\n always @(posedge clk) begin\n if (ce) begin\n value <= in;\n end\n end\n assign out = value;","interface":["input [width-1:0] in","input ce","output [width-1:0] out","input clk"]}} + }, + "regCE_arst":{ + "typegen":"mantle.regCEArstType", + "genparams":{"width":"Int"}, + "metadata":{"verilog":{"definition":" reg [width-1:0] value;\n always @(posedge clk, posedge arst) begin\n if (arst) begin\n value <= init;\n end\n else if (ce) begin\n value <= in;\n end\n end\n assign out = value;","interface":["input [width-1:0] in","input ce","output [width-1:0] out","input clk","input arst"],"parameters":["init"]}} + }, + "sub":{ + "typegen":"mantle.addType", + "genparams":{"has_cin":"Bool", "has_cout":"Bool", "width":"Int"}, + "defaultgenargs":{"has_cin":["Bool",false], "has_cout":["Bool",false]} + }, + "wire":{ + "typegen":"mantle.wire", + "genparams":{"type":"CoreIRType"} + } + }, + "typegens":{ + "addType":[{"has_cin":"Bool", "has_cout":"Bool", "width":"Int"},"implicit"], + "counter_type":[{"has_en":"Bool", "has_max":"Bool", "has_srst":"Bool", "width":"Int"},"implicit"], + "regCEArstType":[{"width":"Int"},"implicit"], + "regCEType":[{"width":"Int"},"implicit"], + "regType":[{"has_clr":"Bool", "has_en":"Bool", "has_rst":"Bool", "width":"Int"},"sparse",[ + [{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},["Record",[["in",["Array",16,"BitIn"]],["clk",["Named","coreir.clkIn"]],["out",["Array",16,"Bit"]]]]] + ]], + "wire":[{"type":"CoreIRType"},"implicit"] + } + } +} +} diff --git a/aha_garnet_design_pond/complex_mem_pond_rolled/complex_mem_pond_rolled.json b/aha_garnet_design_pond/complex_mem_pond_rolled/complex_mem_pond_rolled.json new file mode 100644 index 000000000..e81b0de21 --- /dev/null +++ b/aha_garnet_design_pond/complex_mem_pond_rolled/complex_mem_pond_rolled.json @@ -0,0 +1,773 @@ +{"top":"global.complex_mem_pond_rolled", +"namespaces":{ + "global":{ + "modules":{ + "complex_mem_pond_rolled":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["reset","BitIn"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read_en","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_en","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "_U20":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U25":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "input_cgra_stencil":{ + "modref":"global.input_cgra_stencil_ub" + }, + "input_pond_stencil":{ + "modref":"global.input_pond_stencil_ub" + }, + "kernel_cgra_stencil":{ + "modref":"global.kernel_cgra_stencil_ub" + }, + "kernel_pond_stencil":{ + "modref":"global.kernel_pond_stencil_ub" + }, + "op_hcompute_hw_output_stencil":{ + "modref":"global.cu_op_hcompute_hw_output_stencil" + }, + "op_hcompute_hw_output_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U14" + }, + "op_hcompute_hw_output_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[28352],"cycle_stride":[1,8,32],"dimensionality":3,"extent":[8,4,4]}},"mode":"lake"} + }, + "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_output_stencil_read_start":{ + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U13" + }, + "op_hcompute_hw_output_stencil_write_start":{ + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U15" + }, + "op_hcompute_input_cgra_stencil":{ + "modref":"global.cu_op_hcompute_input_cgra_stencil" + }, + "op_hcompute_input_cgra_stencil_exe_start":{ + "modref":"global.op_hcompute_input_cgra_stencil_exe_start_pt__U23" + }, + "op_hcompute_input_cgra_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U21"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,48],"dimensionality":3,"extent":[8,6,6]}},"mode":"lake"} + }, + "op_hcompute_input_cgra_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_input_cgra_stencil_read_start":{ + "modref":"global.op_hcompute_input_cgra_stencil_read_start_pt__U22" + }, + "op_hcompute_input_cgra_stencil_write_start":{ + "modref":"global.op_hcompute_input_cgra_stencil_write_start_pt__U24" + }, + "op_hcompute_input_pond_stencil":{ + "modref":"global.cu_op_hcompute_input_pond_stencil" + }, + "op_hcompute_kernel_cgra_stencil":{ + "modref":"global.cu_op_hcompute_kernel_cgra_stencil" + }, + "op_hcompute_kernel_cgra_stencil_exe_start":{ + "modref":"global.op_hcompute_kernel_cgra_stencil_exe_start_pt__U18" + }, + "op_hcompute_kernel_cgra_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U16"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,64,192],"dimensionality":4,"extent":[8,8,3,3]}},"mode":"lake"} + }, + "op_hcompute_kernel_cgra_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_kernel_cgra_stencil_read_start":{ + "modref":"global.op_hcompute_kernel_cgra_stencil_read_start_pt__U17" + }, + "op_hcompute_kernel_cgra_stencil_write_start":{ + "modref":"global.op_hcompute_kernel_cgra_stencil_write_start_pt__U19" + }, + "op_hcompute_kernel_pond_stencil":{ + "modref":"global.cu_op_hcompute_kernel_pond_stencil" + }, + "op_hcompute_output_cgra_stencil":{ + "modref":"global.cu_op_hcompute_output_cgra_stencil" + }, + "op_hcompute_output_pond_stencil":{ + "modref":"global.cu_op_hcompute_output_pond_stencil" + }, + "op_hcompute_output_pond_stencil_1":{ + "modref":"global.cu_op_hcompute_output_pond_stencil_1" + }, + "output_cgra_stencil":{ + "modref":"global.output_cgra_stencil_ub" + }, + "output_pond_stencil":{ + "modref":"global.output_pond_stencil_ub" + } + }, + "connections":[ + ["self.clk","_U20.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read.0","_U20.in"], + ["self.clk","_U25.clk"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","_U25.in"], + ["self.clk","input_cgra_stencil.clk"], + ["op_hcompute_input_cgra_stencil.input_cgra_stencil_op_hcompute_input_cgra_stencil_write","input_cgra_stencil.op_hcompute_input_cgra_stencil_write"], + ["op_hcompute_input_pond_stencil.input_cgra_stencil_op_hcompute_input_pond_stencil_read","input_cgra_stencil.op_hcompute_input_pond_stencil_read"], + ["self.reset","input_cgra_stencil.reset"], + ["self.clk","input_pond_stencil.clk"], + ["op_hcompute_input_pond_stencil.input_pond_stencil_op_hcompute_input_pond_stencil_write","input_pond_stencil.op_hcompute_input_pond_stencil_write"], + ["op_hcompute_output_pond_stencil_1.input_pond_stencil_op_hcompute_output_pond_stencil_1_read","input_pond_stencil.op_hcompute_output_pond_stencil_1_read"], + ["self.reset","input_pond_stencil.reset"], + ["self.clk","kernel_cgra_stencil.clk"], + ["op_hcompute_kernel_cgra_stencil.kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write","kernel_cgra_stencil.op_hcompute_kernel_cgra_stencil_write"], + ["op_hcompute_kernel_pond_stencil.kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read","kernel_cgra_stencil.op_hcompute_kernel_pond_stencil_read"], + ["self.reset","kernel_cgra_stencil.reset"], + ["self.clk","kernel_pond_stencil.clk"], + ["op_hcompute_kernel_pond_stencil.kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write","kernel_pond_stencil.op_hcompute_kernel_pond_stencil_write"], + ["op_hcompute_output_pond_stencil_1.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read","kernel_pond_stencil.op_hcompute_output_pond_stencil_1_read"], + ["self.reset","kernel_pond_stencil.reset"], + ["self.clk","op_hcompute_hw_output_stencil.clk"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_op_hcompute_hw_output_stencil_write"], + ["output_cgra_stencil.op_hcompute_hw_output_stencil_read","op_hcompute_hw_output_stencil.output_cgra_stencil_op_hcompute_hw_output_stencil_read"], + ["op_hcompute_hw_output_stencil_port_controller.stencil_valid","op_hcompute_hw_output_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_output_stencil_port_controller.clk"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_output_stencil_port_controller.flush"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.rst_n"], + ["op_hcompute_hw_output_stencil_read_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_output_stencil_write_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"], + ["self.clk","op_hcompute_input_cgra_stencil.clk"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read","op_hcompute_input_cgra_stencil.input_host_stencil_op_hcompute_input_cgra_stencil_read"], + ["op_hcompute_input_cgra_stencil_port_controller.stencil_valid","op_hcompute_input_cgra_stencil_exe_start.in"], + ["self.clk","op_hcompute_input_cgra_stencil_port_controller.clk"], + ["op_hcompute_input_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_input_cgra_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_input_cgra_stencil_port_controller.flush"], + ["op_hcompute_input_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_input_cgra_stencil_port_controller.rst_n"], + ["op_hcompute_input_cgra_stencil_read_start.in","op_hcompute_input_cgra_stencil_port_controller.stencil_valid"], + ["op_hcompute_input_cgra_stencil_write_start.in","op_hcompute_input_cgra_stencil_port_controller.stencil_valid"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read_en","op_hcompute_input_cgra_stencil_read_start.out"], + ["self.clk","op_hcompute_input_pond_stencil.clk"], + ["self.clk","op_hcompute_kernel_cgra_stencil.clk"], + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read","op_hcompute_kernel_cgra_stencil.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read"], + ["op_hcompute_kernel_cgra_stencil_port_controller.stencil_valid","op_hcompute_kernel_cgra_stencil_exe_start.in"], + ["self.clk","op_hcompute_kernel_cgra_stencil_port_controller.clk"], + ["op_hcompute_kernel_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_kernel_cgra_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_kernel_cgra_stencil_port_controller.flush"], + ["op_hcompute_kernel_cgra_stencil_port_controller_clk_en_const.out","op_hcompute_kernel_cgra_stencil_port_controller.rst_n"], + ["op_hcompute_kernel_cgra_stencil_read_start.in","op_hcompute_kernel_cgra_stencil_port_controller.stencil_valid"], + ["op_hcompute_kernel_cgra_stencil_write_start.in","op_hcompute_kernel_cgra_stencil_port_controller.stencil_valid"], + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_en","op_hcompute_kernel_cgra_stencil_read_start.out"], + ["self.clk","op_hcompute_kernel_pond_stencil.clk"], + ["self.clk","op_hcompute_output_cgra_stencil.clk"], + ["output_cgra_stencil.op_hcompute_output_cgra_stencil_write","op_hcompute_output_cgra_stencil.output_cgra_stencil_op_hcompute_output_cgra_stencil_write"], + ["output_pond_stencil.op_hcompute_output_cgra_stencil_read","op_hcompute_output_cgra_stencil.output_pond_stencil_op_hcompute_output_cgra_stencil_read"], + ["self.clk","op_hcompute_output_pond_stencil.clk"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_write","op_hcompute_output_pond_stencil.output_pond_stencil_op_hcompute_output_pond_stencil_write"], + ["self.clk","op_hcompute_output_pond_stencil_1.clk"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_1_read","op_hcompute_output_pond_stencil_1.output_pond_stencil_op_hcompute_output_pond_stencil_1_read"], + ["output_pond_stencil.op_hcompute_output_pond_stencil_1_write","op_hcompute_output_pond_stencil_1.output_pond_stencil_op_hcompute_output_pond_stencil_1_write"], + ["self.clk","output_cgra_stencil.clk"], + ["self.reset","output_cgra_stencil.reset"], + ["self.clk","output_pond_stencil.clk"], + ["self.reset","output_pond_stencil.reset"] + ] + }, + "cu_op_hcompute_hw_output_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_cgra_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_output_stencil" + } + }, + "connections":[ + ["self.output_cgra_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in0_output_cgra_stencil.0"], + ["self.hw_output_stencil_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_cgra_stencil_op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_input_cgra_stencil" + } + }, + "connections":[ + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","inner_compute.in0_input_host_stencil.0"], + ["self.input_cgra_stencil_op_hcompute_input_cgra_stencil_write.0","inner_compute.out_input_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_cgra_stencil_op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_pond_stencil_op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_input_pond_stencil" + } + }, + "connections":[ + ["self.input_cgra_stencil_op_hcompute_input_pond_stencil_read.0","inner_compute.in0_input_cgra_stencil.0"], + ["self.input_pond_stencil_op_hcompute_input_pond_stencil_write.0","inner_compute.out_input_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_kernel_cgra_stencil" + } + }, + "connections":[ + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read.0","inner_compute.in0_kernel_host_stencil.0"], + ["self.kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write.0","inner_compute.out_kernel_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_kernel_pond_stencil" + } + }, + "connections":[ + ["self.kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read.0","inner_compute.in0_kernel_cgra_stencil.0"], + ["self.kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write.0","inner_compute.out_kernel_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_cgra_stencil" + } + }, + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_read.0","inner_compute.in0_output_pond_stencil.0"], + ["self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0","inner_compute.out_output_cgra_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_pond_stencil" + } + }, + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_write.0","inner_compute.out_output_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_output_pond_stencil_1" + } + }, + "connections":[ + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute.in0_input_pond_stencil.0"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute.in1_kernel_pond_stencil.0"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute.in2_output_pond_stencil.0"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_write.0","inner_compute.out_output_pond_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_cgra_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_pond_stencil":{ + "type":["Record",[ + ["out_input_pond_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_pond_stencil","self.in0_input_cgra_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["out_kernel_pond_stencil",["Array",16,"Bit"]], + ["in0_kernel_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_pond_stencil","self.in0_kernel_cgra_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_pond_stencil":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_pond_stencil","const_p0__677.out"] + ] + }, + "hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_output_pond_stencil_1_690_691":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_pond_stencil_1_input_pond_stencil_1_690":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_1_690_691.in0"], + ["mul_kernel_pond_stencil_1_input_pond_stencil_1_690.out","add_output_pond_stencil_1_690_691.in1"], + ["self.out_output_pond_stencil","add_output_pond_stencil_1_690_691.out"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_690.in0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_690.in1"] + ] + }, + "input_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_input_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_input_cgra_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,48],"dimensionality":3,"extent":[2,6,6],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,12]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,48],"dimensionality":3,"extent":[8,6,6],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[574],"cycle_stride":[4,8,24,217,1736,6944],"dimensionality":6,"extent":[2,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,12,0,2,12],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,2,0]},"tb2out_0":{"cycle_starting_addr":[576],"cycle_stride":[1,8,24,217,1736,6944],"dimensionality":6,"extent":[8,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0,8,0]}},"mode":"lake"} + }, + "ub_input_cgra_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], + ["ub_input_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_input_cgra_stencil_write.0"], + ["ub_input_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_input_pond_stencil_read.0"], + ["ub_input_cgra_stencil_BANK_0.flush","self.reset"], + ["ub_input_cgra_stencil_BANK_0_clk_en_const.out","ub_input_cgra_stencil_BANK_0.clk_en"], + ["ub_input_cgra_stencil_BANK_0_clk_en_const.out","ub_input_cgra_stencil_BANK_0.rst_n"] + ] + }, + "input_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U2":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[575],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_input_pond_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,6]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,8]},"sram2tb_0":{"cycle_starting_addr":[143],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,6],"write_data_starting_addr":[0],"write_data_stride":[1,2,2]},"tb2out_0":{"cycle_starting_addr":[145],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} + }, + "ub_input_pond_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["self.clk","cgpl_ctrl_U2.clk"], + ["cgpl_ctrl_U2_clk_en_const.out","cgpl_ctrl_U2.clk_en"], + ["self.reset","cgpl_ctrl_U2.flush"], + ["cgpl_ctrl_U2_clk_en_const.out","cgpl_ctrl_U2.rst_n"], + ["ub_input_pond_stencil_BANK_0.flush","cgpl_ctrl_U2.stencil_valid"], + ["ub_input_pond_stencil_BANK_0.clk","self.clk"], + ["ub_input_pond_stencil_BANK_0.data_in_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_0.data_out_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_input_pond_stencil_BANK_0_clk_en_const.out","ub_input_pond_stencil_BANK_0.clk_en"], + ["ub_input_pond_stencil_BANK_0_clk_en_const.out","ub_input_pond_stencil_BANK_0.rst_n"] + ] + }, + "kernel_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_kernel_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_kernel_cgra_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,64,192],"dimensionality":4,"extent":[2,8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16,48]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,64,192],"dimensionality":4,"extent":[8,8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[646],"cycle_stride":[4,8,24,217,1736,6944],"dimensionality":6,"extent":[2,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,16,48,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,2,0,0]},"tb2out_0":{"cycle_starting_addr":[648],"cycle_stride":[1,8,24,217,1736,6944],"dimensionality":6,"extent":[8,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,8,0,0]}},"mode":"lake"} + }, + "ub_kernel_cgra_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_kernel_cgra_stencil_BANK_0.clk","self.clk"], + ["ub_kernel_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_kernel_cgra_stencil_write.0"], + ["ub_kernel_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_kernel_pond_stencil_read.0"], + ["ub_kernel_cgra_stencil_BANK_0.flush","self.reset"], + ["ub_kernel_cgra_stencil_BANK_0_clk_en_const.out","ub_kernel_cgra_stencil_BANK_0.clk_en"], + ["ub_kernel_cgra_stencil_BANK_0_clk_en_const.out","ub_kernel_cgra_stencil_BANK_0.rst_n"] + ] + }, + "kernel_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U6":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[647],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U6_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_kernel_pond_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,6]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,8]},"sram2tb_0":{"cycle_starting_addr":[71],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,6],"write_data_starting_addr":[0],"write_data_stride":[1,2,2]},"tb2out_0":{"cycle_starting_addr":[73],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,8]}},"drive_by_cgpl_ctrl":true,"mode":"lake"} + }, + "ub_kernel_pond_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["self.clk","cgpl_ctrl_U6.clk"], + ["cgpl_ctrl_U6_clk_en_const.out","cgpl_ctrl_U6.clk_en"], + ["self.reset","cgpl_ctrl_U6.flush"], + ["cgpl_ctrl_U6_clk_en_const.out","cgpl_ctrl_U6.rst_n"], + ["ub_kernel_pond_stencil_BANK_0.flush","cgpl_ctrl_U6.stencil_valid"], + ["ub_kernel_pond_stencil_BANK_0.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_0.data_in_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_0.data_out_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_kernel_pond_stencil_BANK_0_clk_en_const.out","ub_kernel_pond_stencil_BANK_0.clk_en"], + ["ub_kernel_pond_stencil_BANK_0_clk_en_const.out","ub_kernel_pond_stencil_BANK_0.rst_n"] + ] + }, + "op_hcompute_hw_output_stencil_exe_start_pt__U14":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_read_start_pt__U13":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_write_start_pt__U15":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_exe_start_pt__U23":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_read_start_pt__U22":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_write_start_pt__U24":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_exe_start_pt__U18":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_read_start_pt__U17":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_write_start_pt__U19":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "output_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_output_cgra_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1445],"cycle_stride":[868,1736,6944],"dimensionality":3,"extent":[2,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8]},"in2agg_0":{"cycle_starting_addr":[793],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[28350],"cycle_stride":[4,8,32],"dimensionality":3,"extent":[2,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[28352],"cycle_stride":[1,8,32],"dimensionality":3,"extent":[8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}},"mode":"lake"} + }, + "ub_output_cgra_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_hw_output_stencil_read.0"], + ["ub_output_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_output_cgra_stencil_write.0"], + ["ub_output_cgra_stencil_BANK_0.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_0_clk_en_const.out","ub_output_cgra_stencil_BANK_0.clk_en"], + ["ub_output_cgra_stencil_BANK_0_clk_en_const.out","ub_output_cgra_stencil_BANK_0.rst_n"] + ] + }, + "output_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "cgpl_ctrl_U10":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[719],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}},"mode":"lake"} + }, + "cgpl_ctrl_U10_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_output_pond_stencil_BANK_0":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U9"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[1],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[73],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[0],"read_data_stride":[0]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} + }, + "ub_output_pond_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["self.clk","cgpl_ctrl_U10.clk"], + ["cgpl_ctrl_U10_clk_en_const.out","cgpl_ctrl_U10.clk_en"], + ["self.reset","cgpl_ctrl_U10.flush"], + ["cgpl_ctrl_U10_clk_en_const.out","cgpl_ctrl_U10.rst_n"], + ["ub_output_pond_stencil_BANK_0.flush","cgpl_ctrl_U10.stencil_valid"], + ["ub_output_pond_stencil_BANK_0.clk","self.clk"], + ["ub_output_pond_stencil_BANK_0.data_out_pond_0","self.op_hcompute_output_cgra_stencil_read.0"], + ["ub_output_pond_stencil_BANK_0.data_out_pond_1","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_output_pond_stencil_BANK_0.data_in_pond_0","self.op_hcompute_output_pond_stencil_1_write.0"], + ["ub_output_pond_stencil_BANK_0.data_in_pond_1","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_0_clk_en_const.out","ub_output_pond_stencil_BANK_0.clk_en"], + ["ub_output_pond_stencil_BANK_0_clk_en_const.out","ub_output_pond_stencil_BANK_0.rst_n"] + ] + } + }, + "generators":{ + "delay_tile":{ + "typegen":"global.delay_tile_TG", + "genparams":{"delay":"Int"} + }, + "raw_dual_port_sram_tile":{ + "typegen":"global.raw_dual_port_sram_TG", + "genparams":{"depth":"Int"} + }, + "raw_quad_port_memtile":{ + "typegen":"global.raw_quad_port_memtile_TG", + "genparams":{"depth":"Int"} + }, + "tahoe":{ + "typegen":"global.tahoe_TG", + "genparams":{"depth":"Int"} + } + }, + "typegens":{ + "delay_tile_TG":[{"delay":"Int"},"implicit"], + "raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"], + "raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"], + "tahoe_TG":[{"depth":"Int"},"implicit"] + } + } +} +} diff --git a/aha_garnet_design_pond/complex_mem_pond_rolled/complex_mem_pond_rolled_garnet.json b/aha_garnet_design_pond/complex_mem_pond_rolled/complex_mem_pond_rolled_garnet.json new file mode 100644 index 000000000..5ed22853a --- /dev/null +++ b/aha_garnet_design_pond/complex_mem_pond_rolled/complex_mem_pond_rolled_garnet.json @@ -0,0 +1,988 @@ +{"top":"global.complex_mem_pond_rolled", +"namespaces":{ + "commonlib":{ + "generators":{ + "MAD":{ + "typegen":"coreir.ternary", + "genparams":{"width":"Int"} + }, + "abs":{ + "typegen":"coreir.unary", + "genparams":{"width":"Int"} + }, + "absd":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "accumulation_register":{ + "typegen":"commonlib.accumulation_register_type", + "genparams":{"iterations":"Int", "width":"Int"} + }, + "bitopn":{ + "typegen":"commonlib.bitopN_type", + "genparams":{"N":"Int", "operator":"String"} + }, + "const_array":{ + "typegen":"coreir.constArrayTG", + "genparams":{"type":"CoreIRType", "value":"Int"}, + "defaultgenargs":{"value":["Int",0]} + }, + "counter":{ + "typegen":"commonlib.counter_type", + "genparams":{"inc":"Int", "max":"Int", "min":"Int", "width":"Int"} + }, + "deserializer":{ + "typegen":"commonlib.deserializer_type", + "genparams":{"rate":"Int", "width":"Int"} + }, + "div":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "lutN":{ + "typegen":"commonlib.lutNType", + "genparams":{"N":"Int"}, + "modules":[ + [{"N":["Int",3]},{ + "type":["Record",[ + ["in",["Array",3,"BitIn"]], + ["out","Bit"] + ]], + "modparams":{"init":["BitVector",8]}, + "instances":{ + "lut":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"Arg","init"]} + } + }, + "connections":[ + ["self.in","lut.bit.in"], + ["self.out","lut.bit.out"] + ] + }] + ], + "metadata":{"verilog":{"definition":" assign out = init[in];","interface":["input [N-1:0] in","output out"],"parameters":["init"]}} + }, + "mult_high":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "mult_middle":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "muxn":{ + "typegen":"commonlib.muxN_type", + "genparams":{"N":"Int", "width":"Int"} + }, + "opn":{ + "typegen":"commonlib.opN_type", + "genparams":{"N":"Int", "operator":"String", "width":"Int"} + }, + "reg_array":{ + "typegen":"coreir.regArrayTG", + "genparams":{"has_clr":"Bool", "has_en":"Bool", "has_rst":"Bool", "init":"Int", "type":"CoreIRType"}, + "defaultgenargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "init":["Int",0]} + }, + "reshape":{ + "typegen":"commonlib.reshape_type", + "genparams":{"input_type":"CoreIRType", "output_type":"CoreIRType"} + }, + "sclamp":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "serializer":{ + "typegen":"commonlib.serializer_type", + "genparams":{"rate":"Int", "width":"Int"} + }, + "smax":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "smin":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "transpose":{ + "typegen":"commonlib.transpose_type", + "genparams":{"input_type":"CoreIRType"} + }, + "transpose_reshape":{ + "typegen":"commonlib.reshape_type", + "genparams":{"input_type":"CoreIRType", "output_type":"CoreIRType"} + }, + "uclamp":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "umax":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + }, + "umin":{ + "typegen":"coreir.binary", + "genparams":{"width":"Int"} + } + }, + "typegens":{ + "accumulation_register_type":[{"iterations":"Int", "width":"Int"},"implicit"], + "bitopN_type":[{"N":"Int", "operator":"String"},"implicit"], + "counter_type":[{"inc":"Int", "max":"Int", "min":"Int", "width":"Int"},"implicit"], + "deserializer_type":[{"rate":"Int", "width":"Int"},"implicit"], + "lutNType":[{"N":"Int"},"sparse",[ + [{"N":["Int",3]},["Record",[["in",["Array",3,"BitIn"]],["out","Bit"]]]] + ]], + "muxN_type":[{"N":"Int", "width":"Int"},"implicit"], + "opN_type":[{"N":"Int", "operator":"String", "width":"Int"},"implicit"], + "reshape_type":[{"input_type":"CoreIRType", "output_type":"CoreIRType"},"implicit"], + "serializer_type":[{"rate":"Int", "width":"Int"},"implicit"], + "transpose_type":[{"input_type":"CoreIRType"},"implicit"] + } + }, + "global":{ + "modules":{ + "complex_mem_pond_rolled":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["reset","BitIn"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read_en","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_en","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,48],"dimensionality":3,"extent":[2,6,6],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,12]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,48],"dimensionality":3,"extent":[8,6,6],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[574],"cycle_stride":[4,8,24,217,1736,6944],"dimensionality":6,"extent":[2,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,12,0,2,12],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,2,0]},"tb2out_0":{"cycle_starting_addr":[576],"cycle_stride":[1,8,24,217,1736,6944],"dimensionality":6,"extent":[8,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0,8,0]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "input_pond_stencil$cgpl_ctrl_U2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$cgpl_ctrl_U2_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[575],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,6]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,8]},"sram2tb_0":{"cycle_starting_addr":[143],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,6],"write_data_starting_addr":[0],"write_data_stride":[1,2,2]},"tb2out_0":{"cycle_starting_addr":[145],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,8]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ + "genref":"cgralib.IO", + "genargs":{"width":["Int",16]}, + "modargs":{"mode":["String","out"]}, + "metadata":{"in2glb_0":{"cycle_starting_addr":[28352],"cycle_stride":[1],"dimensionality":1,"extent":[128],"write_data_starting_addr":[0],"write_data_stride":[1]}} + }, + "io16in_input_host_stencil_op_hcompute_input_cgra_stencil_read_0":{ + "genref":"cgralib.IO", + "genargs":{"width":["Int",16]}, + "modargs":{"mode":["String","in"]}, + "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[288],"read_data_starting_addr":[0],"read_data_stride":[1]}} + }, + "io16in_kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_0":{ + "genref":"cgralib.IO", + "genargs":{"width":["Int",16]}, + "modargs":{"mode":["String","in"]}, + "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[576],"read_data_starting_addr":[0],"read_data_stride":[1]}} + }, + "io1_hw_output_stencil_op_hcompute_hw_output_stencil_write_valid":{ + "modref":"cgralib.BitIO", + "modargs":{"mode":["String","out"]} + }, + "io1in_reset":{ + "modref":"cgralib.BitIO", + "modargs":{"mode":["String","in"]} + }, + "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,64,192],"dimensionality":4,"extent":[2,8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16,48]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,64,192],"dimensionality":4,"extent":[8,8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[646],"cycle_stride":[4,8,24,217,1736,6944],"dimensionality":6,"extent":[2,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,16,48,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,2,0,0]},"tb2out_0":{"cycle_starting_addr":[648],"cycle_stride":[1,8,24,217,1736,6944],"dimensionality":6,"extent":[8,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U6_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$cgpl_ctrl_U6_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[647],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,6]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,8]},"sram2tb_0":{"cycle_starting_addr":[71],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,6],"write_data_starting_addr":[0],"write_data_stride":[1,2,2]},"tb2out_0":{"cycle_starting_addr":[73],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,8]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "op_hcompute_hw_output_stencil_port_controller_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[28352],"cycle_stride":[1,8,32],"dimensionality":3,"extent":[8,4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "op_hcompute_output_pond_stencil$inner_compute$const_p0__677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_690_691$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1445],"cycle_stride":[868,1736,6944],"dimensionality":3,"extent":[2,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8]},"in2agg_0":{"cycle_starting_addr":[793],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[28350],"cycle_stride":[4,8,32],"dimensionality":3,"extent":[2,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[28352],"cycle_stride":[1,8,32],"dimensionality":3,"extent":[8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "output_pond_stencil$cgpl_ctrl_U10_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$cgpl_ctrl_U10_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[719],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U9"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[1],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[73],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[0],"read_data_stride":[0]}}], "mode":["String","pond"]} + } + }, + "connections":[ + ["input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.clk_en","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["io16in_input_host_stencil_op_hcompute_input_cgra_stencil_read_0.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_in_0"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.data_in_0","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.data_out_0"], + ["io1in_reset.out","input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet.flush"], + ["input_pond_stencil$cgpl_ctrl_U2_garnet.clk_en","input_pond_stencil$cgpl_ctrl_U2_clk_en_const_lutcnst.bit.out"], + ["io1in_reset.out","input_pond_stencil$cgpl_ctrl_U2_garnet.flush"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.flush","input_pond_stencil$cgpl_ctrl_U2_garnet.stencil_valid"], + ["input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.clk_en","input_pond_stencil$ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.in.1","input_pond_stencil$ub_input_pond_stencil_BANK_0_garnet.data_out_0"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_out_0","io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0.in"], + ["kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_in_0","io16in_kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read_0.out"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.stencil_valid","io1_hw_output_stencil_op_hcompute_hw_output_stencil_write_valid.in"], + ["kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.flush","io1in_reset.out"], + ["kernel_pond_stencil$cgpl_ctrl_U6_garnet.flush","io1in_reset.out"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.flush","io1in_reset.out"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.flush","io1in_reset.out"], + ["output_pond_stencil$cgpl_ctrl_U10_garnet.flush","io1in_reset.out"], + ["kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.clk_en","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.data_in_0","kernel_cgra_stencil$ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0"], + ["kernel_pond_stencil$cgpl_ctrl_U6_garnet.clk_en","kernel_pond_stencil$cgpl_ctrl_U6_clk_en_const_lutcnst.bit.out"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.flush","kernel_pond_stencil$cgpl_ctrl_U6_garnet.stencil_valid"], + ["kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.clk_en","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.in.0","kernel_pond_stencil$ub_kernel_pond_stencil_BANK_0_garnet.data_out_0"], + ["op_hcompute_hw_output_stencil_port_controller_garnet.clk_en","op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_in_pond_1","op_hcompute_output_pond_stencil$inner_compute$const_p0__677.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_out_pond_1","op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_690_691$binop.data.in.0"], + ["op_hcompute_output_pond_stencil_1$inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.out","op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_690_691$binop.data.in.1"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_in_pond_0","op_hcompute_output_pond_stencil_1$inner_compute$add_output_pond_stencil_1_690_691$binop.data.out"], + ["output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.clk_en","output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.data_out_pond_0","output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet.data_in_0"], + ["output_pond_stencil$cgpl_ctrl_U10_garnet.clk_en","output_pond_stencil$cgpl_ctrl_U10_clk_en_const_lutcnst.bit.out"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.flush","output_pond_stencil$cgpl_ctrl_U10_garnet.stencil_valid"], + ["output_pond_stencil$ub_output_pond_stencil_BANK_0_garnet.clk_en","output_pond_stencil$ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "cu_op_hcompute_hw_output_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_cgra_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.output_cgra_stencil_op_hcompute_hw_output_stencil_read.0","self.hw_output_stencil_op_hcompute_hw_output_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_cgra_stencil_op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","self.input_cgra_stencil_op_hcompute_input_cgra_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_input_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_cgra_stencil_op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["input_pond_stencil_op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.input_pond_stencil_op_hcompute_input_pond_stencil_write.0","self.input_cgra_stencil_op_hcompute_input_pond_stencil_read.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.kernel_host_stencil_op_hcompute_kernel_cgra_stencil_read.0","self.kernel_cgra_stencil_op_hcompute_kernel_cgra_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.kernel_pond_stencil_op_hcompute_kernel_pond_stencil_write.0","self.kernel_cgra_stencil_op_hcompute_kernel_pond_stencil_read.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["output_cgra_stencil_op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_cgra_stencil_read.0","self.output_cgra_stencil_op_hcompute_output_cgra_stencil_write.0"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["output_pond_stencil_op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "PE_init_U28":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "_U26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "_U27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["_U26.out","PE_init_U28.data.in.0"], + ["_U27.out","PE_init_U28.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_write.0","PE_init_U28.data.out"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["input_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["output_pond_stencil_op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute$add_output_pond_stencil_1_690_691$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute$add_output_pond_stencil_1_690_691$binop.data.in.0"], + ["inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.out","inner_compute$add_output_pond_stencil_1_690_691$binop.data.in.1"], + ["self.output_pond_stencil_op_hcompute_output_pond_stencil_1_write.0","inner_compute$add_output_pond_stencil_1_690_691$binop.data.out"], + ["self.kernel_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.in.0"], + ["self.input_pond_stencil_op_hcompute_output_pond_stencil_1_read.0","inner_compute$mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.in.1"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_cgra_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_pond_stencil":{ + "type":["Record",[ + ["out_input_pond_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_pond_stencil","self.in0_input_cgra_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_kernel_pond_stencil":{ + "type":["Record",[ + ["out_kernel_pond_stencil",["Array",16,"Bit"]], + ["in0_kernel_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_pond_stencil","self.in0_kernel_cgra_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_cgra_stencil","self.in0_output_pond_stencil.0"] + ] + }, + "hcompute_output_pond_stencil":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "PE_init_U31":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "_U29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "_U30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["_U29.out","PE_init_U31.data.in.0"], + ["_U30.out","PE_init_U31.data.in.1"], + ["self.out_output_pond_stencil","PE_init_U31.data.out"] + ] + }, + "hcompute_output_pond_stencil_1":{ + "type":["Record",[ + ["out_output_pond_stencil",["Array",16,"Bit"]], + ["in0_input_pond_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_kernel_pond_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_output_pond_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_output_pond_stencil_1_690_691$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + }, + "mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, + "modargs":{"alu_op":["String","mult_0"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} + } + }, + "connections":[ + ["self.in2_output_pond_stencil.0","add_output_pond_stencil_1_690_691$binop.data.in.0"], + ["mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.out","add_output_pond_stencil_1_690_691$binop.data.in.1"], + ["self.out_output_pond_stencil","add_output_pond_stencil_1_690_691$binop.data.out"], + ["self.in1_kernel_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.in.0"], + ["self.in0_input_pond_stencil.0","mul_kernel_pond_stencil_1_input_pond_stencil_1_690$binop.data.in.1"] + ] + }, + "input_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_input_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_input_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_input_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,48],"dimensionality":3,"extent":[2,6,6],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,12]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,48],"dimensionality":3,"extent":[8,6,6],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[574],"cycle_stride":[4,8,24,217,1736,6944],"dimensionality":6,"extent":[2,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,12,0,2,12],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,2,0]},"tb2out_0":{"cycle_starting_addr":[576],"cycle_stride":[1,8,24,217,1736,6944],"dimensionality":6,"extent":[8,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,0,8,0]}}], "init":["Json",null], "mode":["String","lake"]} + } + }, + "connections":[ + ["ub_input_cgra_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_input_cgra_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_input_cgra_stencil_write.0"], + ["ub_input_cgra_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_input_pond_stencil_read.0"], + ["ub_input_cgra_stencil_BANK_0_garnet.flush","self.reset"], + ["ub_input_cgra_stencil_BANK_0_garnet.clk_en","ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "input_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_input_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_input_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U2_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U2_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[575],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_input_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,6]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,8]},"sram2tb_0":{"cycle_starting_addr":[143],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,6],"write_data_starting_addr":[0],"write_data_stride":[1,2,2]},"tb2out_0":{"cycle_starting_addr":[145],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,8]}}], "init":["Json",null], "mode":["String","lake"]} + } + }, + "connections":[ + ["cgpl_ctrl_U2_garnet.clk_en","cgpl_ctrl_U2_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U2_garnet.clk"], + ["self.reset","cgpl_ctrl_U2_garnet.flush"], + ["ub_input_pond_stencil_BANK_0_garnet.flush","cgpl_ctrl_U2_garnet.stencil_valid"], + ["ub_input_pond_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_input_pond_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_input_pond_stencil_write.0"], + ["ub_input_pond_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_input_pond_stencil_BANK_0_garnet.clk_en","ub_input_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "kernel_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_cgra_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_kernel_pond_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_kernel_pond_stencil_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U4"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,64,192],"dimensionality":4,"extent":[2,8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,16,48]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,64,192],"dimensionality":4,"extent":[8,8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,0,0]},"sram2tb_0":{"cycle_starting_addr":[646],"cycle_stride":[4,8,24,217,1736,6944],"dimensionality":6,"extent":[2,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,16,48,2,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,2,0,0]},"tb2out_0":{"cycle_starting_addr":[648],"cycle_stride":[1,8,24,217,1736,6944],"dimensionality":6,"extent":[8,3,3,8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,0,0,8,0,0]}}], "init":["Json",null], "mode":["String","lake"]} + } + }, + "connections":[ + ["ub_kernel_cgra_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_kernel_cgra_stencil_write.0"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_kernel_pond_stencil_read.0"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.flush","self.reset"], + ["ub_kernel_cgra_stencil_BANK_0_garnet.clk_en","ub_kernel_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "kernel_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_kernel_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_kernel_pond_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"] + ]], + "instances":{ + "cgpl_ctrl_U6_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U6_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[647],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_kernel_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,2],"write_data_starting_addr":[0],"write_data_stride":[1,2,6]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,8,8]},"sram2tb_0":{"cycle_starting_addr":[71],"cycle_stride":[4,8,24],"dimensionality":3,"extent":[2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,2,6],"write_data_starting_addr":[0],"write_data_stride":[1,2,2]},"tb2out_0":{"cycle_starting_addr":[73],"cycle_stride":[1,8,24],"dimensionality":3,"extent":[8,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,8]}}], "init":["Json",null], "mode":["String","lake"]} + } + }, + "connections":[ + ["cgpl_ctrl_U6_garnet.clk_en","cgpl_ctrl_U6_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U6_garnet.clk"], + ["self.reset","cgpl_ctrl_U6_garnet.flush"], + ["ub_kernel_pond_stencil_BANK_0_garnet.flush","cgpl_ctrl_U6_garnet.stencil_valid"], + ["ub_kernel_pond_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_kernel_pond_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_kernel_pond_stencil_write.0"], + ["ub_kernel_pond_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_kernel_pond_stencil_BANK_0_garnet.clk_en","ub_kernel_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "op_hcompute_hw_output_stencil_exe_start_pt__U14":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_read_start_pt__U13":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_write_start_pt__U15":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_exe_start_pt__U23":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_read_start_pt__U22":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_input_cgra_stencil_write_start_pt__U24":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_exe_start_pt__U18":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_read_start_pt__U17":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_kernel_cgra_stencil_write_start_pt__U19":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "output_cgra_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_cgra_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_cgra_stencil_BANK_0_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1445],"cycle_stride":[868,1736,6944],"dimensionality":3,"extent":[2,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,2,8]},"in2agg_0":{"cycle_starting_addr":[793],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"sram2tb_0":{"cycle_starting_addr":[28350],"cycle_stride":[4,8,32],"dimensionality":3,"extent":[2,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,2,8],"write_data_starting_addr":[0],"write_data_stride":[1,2,0]},"tb2out_0":{"cycle_starting_addr":[28352],"cycle_stride":[1,8,32],"dimensionality":3,"extent":[8,4,4],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]}}], "init":["Json",null], "mode":["String","lake"]} + } + }, + "connections":[ + ["ub_output_cgra_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_output_cgra_stencil_BANK_0_garnet.data_out_0","self.op_hcompute_hw_output_stencil_read.0"], + ["ub_output_cgra_stencil_BANK_0_garnet.data_in_0","self.op_hcompute_output_cgra_stencil_write.0"], + ["ub_output_cgra_stencil_BANK_0_garnet.flush","self.reset"], + ["ub_output_cgra_stencil_BANK_0_garnet.clk_en","ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + }, + "output_pond_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_output_cgra_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_cgra_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_output_pond_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_output_pond_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_output_pond_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_output_pond_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "cgpl_ctrl_U10_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "cgpl_ctrl_U10_garnet":{ + "genref":"cgralib.Mem", + "genargs":{"ID":["String","_U11"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[719],"cycle_stride":[217,1736,6944],"dimensionality":3,"extent":[8,4,4]}}], "init":["Json",null], "mode":["String","lake"]} + }, + "ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst":{ + "genref":"cgralib.PE", + "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, + "modargs":{"bit0_mode":["String","BYPASS"], "bit0_value":["Bool",false], "bit1_mode":["String","BYPASS"], "bit1_value":["Bool",false], "bit2_mode":["String","BYPASS"], "bit2_value":["Bool",false], "flag_sel":["String","lut"], "lut_value":[["BitVector",8],"8'h3f"]} + }, + "ub_output_pond_stencil_BANK_0_garnet":{ + "genref":"cgralib.Pond", + "genargs":{"ID":["String","_U9"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[1],"cycle_stride":[1],"dimensionality":1,"extent":[72],"write_data_starting_addr":[0],"write_data_stride":[0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[0],"dimensionality":1,"extent":[1],"write_data_starting_addr":[0],"write_data_stride":[0]},"regfile2out_0":{"cycle_starting_addr":[73],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0]},"regfile2out_1":{"cycle_starting_addr":[1],"cycle_stride":[1],"dimensionality":1,"extent":[72],"read_data_starting_addr":[0],"read_data_stride":[0]}}], "mode":["String","pond"]} + } + }, + "connections":[ + ["cgpl_ctrl_U10_garnet.clk_en","cgpl_ctrl_U10_clk_en_const_lutcnst.bit.out"], + ["self.clk","cgpl_ctrl_U10_garnet.clk"], + ["self.reset","cgpl_ctrl_U10_garnet.flush"], + ["ub_output_pond_stencil_BANK_0_garnet.flush","cgpl_ctrl_U10_garnet.stencil_valid"], + ["ub_output_pond_stencil_BANK_0_garnet.clk","self.clk"], + ["ub_output_pond_stencil_BANK_0_garnet.data_out_pond_0","self.op_hcompute_output_cgra_stencil_read.0"], + ["ub_output_pond_stencil_BANK_0_garnet.data_out_pond_1","self.op_hcompute_output_pond_stencil_1_read.0"], + ["ub_output_pond_stencil_BANK_0_garnet.data_in_pond_0","self.op_hcompute_output_pond_stencil_1_write.0"], + ["ub_output_pond_stencil_BANK_0_garnet.data_in_pond_1","self.op_hcompute_output_pond_stencil_write.0"], + ["ub_output_pond_stencil_BANK_0_garnet.clk_en","ub_output_pond_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] + ] + } + }, + "generators":{ + "delay_tile":{ + "typegen":"global.delay_tile_TG", + "genparams":{"delay":"Int"} + }, + "raw_dual_port_sram_tile":{ + "typegen":"global.raw_dual_port_sram_TG", + "genparams":{"depth":"Int"} + }, + "raw_quad_port_memtile":{ + "typegen":"global.raw_quad_port_memtile_TG", + "genparams":{"depth":"Int"} + }, + "tahoe":{ + "typegen":"global.tahoe_TG", + "genparams":{"depth":"Int"} + } + }, + "typegens":{ + "delay_tile_TG":[{"delay":"Int"},"implicit"], + "raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"], + "raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"], + "tahoe_TG":[{"depth":"Int"},"implicit"] + } + }, + "mantle":{ + "generators":{ + "add":{ + "typegen":"mantle.addType", + "genparams":{"has_cin":"Bool", "has_cout":"Bool", "width":"Int"}, + "defaultgenargs":{"has_cin":["Bool",false], "has_cout":["Bool",false]} + }, + "counter":{ + "typegen":"mantle.counter_type", + "genparams":{"has_en":"Bool", "has_max":"Bool", "has_srst":"Bool", "width":"Int"}, + "defaultgenargs":{"has_en":["Bool",false], "has_max":["Bool",false], "has_srst":["Bool",false]} + }, + "reg":{ + "typegen":"mantle.regType", + "genparams":{"has_clr":"Bool", "has_en":"Bool", "has_rst":"Bool", "width":"Int"}, + "modules":[ + [{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["clk",["Named","coreir.clkIn"]], + ["out",["Array",16,"Bit"]] + ]], + "modparams":{"init":["BitVector",16]}, + "defaultmodargs":{"init":[["BitVector",16],"16'h0000"]}, + "instances":{ + "reg0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",16]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",16],"Arg","init"]} + } + }, + "connections":[ + ["self.clk","reg0.clk"], + ["self.in","reg0.in"], + ["self.out","reg0.out"] + ] + }] + ], + "defaultgenargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false]} + }, + "regCE":{ + "typegen":"mantle.regCEType", + "genparams":{"width":"Int"}, + "metadata":{"verilog":{"definition":" reg [width-1:0] value;\n always @(posedge clk) begin\n if (ce) begin\n value <= in;\n end\n end\n assign out = value;","interface":["input [width-1:0] in","input ce","output [width-1:0] out","input clk"]}} + }, + "regCE_arst":{ + "typegen":"mantle.regCEArstType", + "genparams":{"width":"Int"}, + "metadata":{"verilog":{"definition":" reg [width-1:0] value;\n always @(posedge clk, posedge arst) begin\n if (arst) begin\n value <= init;\n end\n else if (ce) begin\n value <= in;\n end\n end\n assign out = value;","interface":["input [width-1:0] in","input ce","output [width-1:0] out","input clk","input arst"],"parameters":["init"]}} + }, + "sub":{ + "typegen":"mantle.addType", + "genparams":{"has_cin":"Bool", "has_cout":"Bool", "width":"Int"}, + "defaultgenargs":{"has_cin":["Bool",false], "has_cout":["Bool",false]} + }, + "wire":{ + "typegen":"mantle.wire", + "genparams":{"type":"CoreIRType"} + } + }, + "typegens":{ + "addType":[{"has_cin":"Bool", "has_cout":"Bool", "width":"Int"},"implicit"], + "counter_type":[{"has_en":"Bool", "has_max":"Bool", "has_srst":"Bool", "width":"Int"},"implicit"], + "regCEArstType":[{"width":"Int"},"implicit"], + "regCEType":[{"width":"Int"},"implicit"], + "regType":[{"has_clr":"Bool", "has_en":"Bool", "has_rst":"Bool", "width":"Int"},"sparse",[ + [{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},["Record",[["in",["Array",16,"BitIn"]],["clk",["Named","coreir.clkIn"]],["out",["Array",16,"Bit"]]]]] + ]], + "wire":[{"type":"CoreIRType"},"implicit"] + } + } +} +} diff --git a/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split.json b/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split.json index 3eabbedd6..5031cff47 100644 --- a/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split.json +++ b/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split.json @@ -17,13 +17,13 @@ }, "op_hcompute_f5_1_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U103"} + "genargs":{"ID":["String","_U103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_f5_1_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U104"} + "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_f5_1_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -60,13 +60,13 @@ }, "op_hcompute_f5_0_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U112"} + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_f5_0_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U113"} + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_f5_0_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -103,13 +103,13 @@ }, "op_hcompute_f4_1_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U121"} + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_f4_1_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U122"} + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_f4_1_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -146,13 +146,13 @@ }, "op_hcompute_f4_0_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U130"} + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_f4_0_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U131"} + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_f4_0_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -189,13 +189,13 @@ }, "op_hcompute_f3_1_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U139"} + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_f3_1_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U140"} + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_f3_1_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -232,13 +232,13 @@ }, "op_hcompute_f3_0_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U148"} + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_f3_0_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U149"} + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_f3_0_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -275,13 +275,13 @@ }, "op_hcompute_hw_output_stencil_port_controller_Counter_1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake","verilog_name":"aff_ctrl__U94"} + "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_Counter_2":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U95"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"init":[0,1,2,3,4,5,6,7],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[4,8],"dimensionality":2,"extent":[2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"aff_ctrl__U95"} + "genargs":{"ID":["String","_U95"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"init":[0,1,2,3,4,5,6,7],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[4,8],"dimensionality":2,"extent":[2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -726,7 +726,7 @@ "ub_f3_0_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U43"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U43"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f3_0_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -735,7 +735,7 @@ "ub_f3_0_stencil_BANK_1":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U44"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U44"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f3_0_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -744,7 +744,7 @@ "ub_f3_0_stencil_BANK_2":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U45"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U45"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f3_0_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -753,7 +753,7 @@ "ub_f3_0_stencil_BANK_3":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U46"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U46"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f3_0_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -803,7 +803,7 @@ "ub_f3_1_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U47"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U47"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f3_1_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -812,7 +812,7 @@ "ub_f3_1_stencil_BANK_1":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U48"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U48"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f3_1_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -821,7 +821,7 @@ "ub_f3_1_stencil_BANK_2":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U49"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U49"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f3_1_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -830,7 +830,7 @@ "ub_f3_1_stencil_BANK_3":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U50"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U50"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f3_1_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -880,7 +880,7 @@ "ub_f4_0_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U51"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U51"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f4_0_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -889,7 +889,7 @@ "ub_f4_0_stencil_BANK_1":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U52"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U52"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f4_0_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -898,7 +898,7 @@ "ub_f4_0_stencil_BANK_2":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U53"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U53"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f4_0_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -907,7 +907,7 @@ "ub_f4_0_stencil_BANK_3":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U54"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U54"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f4_0_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -957,7 +957,7 @@ "ub_f4_1_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U55"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U55"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f4_1_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -966,7 +966,7 @@ "ub_f4_1_stencil_BANK_1":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U56"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U56"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f4_1_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -975,7 +975,7 @@ "ub_f4_1_stencil_BANK_2":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U57"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U57"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_f4_1_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -984,7 +984,7 @@ "ub_f4_1_stencil_BANK_3":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U58"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U58"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_f4_1_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -1032,7 +1032,7 @@ "ub_f5_0_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U59"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"pond","verilog_name":"pond__U59"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"pond"} }, "ub_f5_0_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1062,7 +1062,7 @@ "ub_f5_1_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U60"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"pond","verilog_name":"pond__U60"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"regfile2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"pond"} }, "ub_f5_1_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1276,8 +1276,8 @@ }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[48],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U156"} + "genargs":{"ID":["String","_U156"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[48],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -1321,8 +1321,8 @@ }, "op_hcompute_hw_twi_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,16],"dimensionality":3,"extent":[8,2,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U161"} + "genargs":{"ID":["String","_U161"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,8,16],"dimensionality":3,"extent":[8,2,3]}},"mode":"lake"} }, "op_hcompute_hw_twi_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", @@ -1564,7 +1564,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U61"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U61"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1573,7 +1573,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U62"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U62"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const":{ "modref":"corebit.const", @@ -1582,7 +1582,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U63"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U63"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const":{ "modref":"corebit.const", @@ -1591,7 +1591,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_3":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U64"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U64"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[56],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -1600,7 +1600,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_4":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U65"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U65"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -1609,7 +1609,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_5":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U66"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U66"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -1618,7 +1618,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_6":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U67"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U67"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -1627,7 +1627,7 @@ "ub_hw_input_global_wrapper_stencil_BANK_7":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U68"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U68"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[48],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_input_global_wrapper_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -1709,7 +1709,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U69"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U69"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -1718,12 +1718,12 @@ "ub_hw_twi_global_wrapper_stencil_BANK_1":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U70"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U70"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_10":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U79"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U79"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_10_clk_en_const":{ "modref":"corebit.const", @@ -1732,7 +1732,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_11":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U80"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U80"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_11_clk_en_const":{ "modref":"corebit.const", @@ -1741,7 +1741,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_12":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U81"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U81"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_12_clk_en_const":{ "modref":"corebit.const", @@ -1750,7 +1750,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_13":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U82"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U82"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_13_clk_en_const":{ "modref":"corebit.const", @@ -1759,7 +1759,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_14":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U83"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U83"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_14_clk_en_const":{ "modref":"corebit.const", @@ -1768,7 +1768,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_15":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U84"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U84"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[24],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_15_clk_en_const":{ "modref":"corebit.const", @@ -1777,7 +1777,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_16":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U85"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U85"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_16_clk_en_const":{ "modref":"corebit.const", @@ -1786,7 +1786,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_17":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U86"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U86"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_17_clk_en_const":{ "modref":"corebit.const", @@ -1795,7 +1795,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_18":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U87"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U87"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_18_clk_en_const":{ "modref":"corebit.const", @@ -1804,7 +1804,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_19":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U88"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U88"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[40],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_19_clk_en_const":{ "modref":"corebit.const", @@ -1817,12 +1817,12 @@ "ub_hw_twi_global_wrapper_stencil_BANK_2":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U71"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U71"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_20":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U89"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U89"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_20_clk_en_const":{ "modref":"corebit.const", @@ -1831,7 +1831,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_21":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U90"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U90"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_21_clk_en_const":{ "modref":"corebit.const", @@ -1840,7 +1840,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_22":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U91"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U91"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_22_clk_en_const":{ "modref":"corebit.const", @@ -1849,7 +1849,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_23":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U92"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U92"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_23_clk_en_const":{ "modref":"corebit.const", @@ -1862,7 +1862,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_3":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U72"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U72"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_3_clk_en_const":{ "modref":"corebit.const", @@ -1871,7 +1871,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_4":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U73"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U73"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_4_clk_en_const":{ "modref":"corebit.const", @@ -1880,7 +1880,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_5":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U74"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U74"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_5_clk_en_const":{ "modref":"corebit.const", @@ -1889,7 +1889,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_6":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U75"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U75"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_6_clk_en_const":{ "modref":"corebit.const", @@ -1898,7 +1898,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_7":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U76"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U76"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_7_clk_en_const":{ "modref":"corebit.const", @@ -1907,7 +1907,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_8":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U77"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond","verilog_name":"pond__U77"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[2,1]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_8_clk_en_const":{ "modref":"corebit.const", @@ -1916,7 +1916,7 @@ "ub_hw_twi_global_wrapper_stencil_BANK_9":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U78"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond","verilog_name":"pond__U78"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[8],"cycle_stride":[1],"dimensionality":1,"extent":[8],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[1],"read_data_stride":[2,31]}},"mode":"pond"} }, "ub_hw_twi_global_wrapper_stencil_BANK_9_clk_en_const":{ "modref":"corebit.const", diff --git a/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split_garnet.json b/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split_garnet.json index 41e07429d..06a0ad62b 100644 --- a/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split_garnet.json +++ b/aha_garnet_design_pond/fft8_unroll8_split/fft8_unroll8_split_garnet.json @@ -168,12 +168,12 @@ }, "op_hcompute_f5_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -227,12 +227,12 @@ }, "op_hcompute_f5_0_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_0_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_0_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -286,12 +286,12 @@ }, "op_hcompute_f4_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -345,12 +345,12 @@ }, "op_hcompute_f4_0_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_0_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_0_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -404,12 +404,12 @@ }, "op_hcompute_f3_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -463,12 +463,12 @@ }, "op_hcompute_f3_0_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_0_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_0_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -522,12 +522,12 @@ }, "op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U95"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U95"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[4,8],"dimensionality":2,"extent":[2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -1954,12 +1954,12 @@ }, "op_hcompute_f3_0_stencil_port_controller$op_hcompute_f3_0_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U148"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_0_stencil_port_controller$op_hcompute_f3_0_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U149"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[61],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[64],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_0_stencil_port_controller$op_hcompute_f3_0_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -2014,12 +2014,12 @@ }, "op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U139"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U140"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[62],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[65],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -2074,12 +2074,12 @@ }, "op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U130"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U131"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[75],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[78],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -2134,12 +2134,12 @@ }, "op_hcompute_f4_1_stencil_port_controller$op_hcompute_f4_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U121"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_1_stencil_port_controller$op_hcompute_f4_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U122"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[76],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[79],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f4_1_stencil_port_controller$op_hcompute_f4_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -2194,12 +2194,12 @@ }, "op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U112"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U113"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[89],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[92],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -2254,12 +2254,12 @@ }, "op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U103"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U104"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[90],"cycle_stride":[7],"dimensionality":1,"extent":[2],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"tb2out_0":{"cycle_starting_addr":[93],"cycle_stride":[2,7],"dimensionality":2,"extent":[4,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -2284,12 +2284,12 @@ }, "op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U94"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[0],"dimensionality":1,"extent":[1],"read_data_starting_addr":[0],"read_data_stride":[0],"write_data_starting_addr":[0],"write_data_stride":[0]},"stencil_valid":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[0,1]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U95"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U95"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"init":[0,1,2,3,4,5,6,7],"sram2tb_0":{"cycle_starting_addr":[103],"cycle_stride":[4,8],"dimensionality":2,"extent":[2,2],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[106],"cycle_stride":[1,8],"dimensionality":2,"extent":[8,2],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst":{ @@ -2534,16 +2534,16 @@ ["op_hcompute_f3_1_stencil$add_all__U13$binop.data.in.0","op_hcompute_f3_1_stencil$add_all__U12$binop.data.out"], ["op_hcompute_f3_1_stencil$add_all__U8$binop.data.in.0","op_hcompute_f3_1_stencil$add_all__U7$binop.data.out"], ["op_hcompute_f3_1_stencil$add_all__U9$binop.data.in.0","op_hcompute_f3_1_stencil$add_all__U8$binop.data.out"], - ["op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f3_1_stencil_port_controller$op_hcompute_f3_1_stencil_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_f4_0_stencil$add_all__U15$binop.data.in.0","op_hcompute_f4_0_stencil$add_all__U14$binop.data.out"], ["op_hcompute_f4_0_stencil$add_all__U16$binop.data.in.0","op_hcompute_f4_0_stencil$add_all__U15$binop.data.out"], ["op_hcompute_f4_0_stencil$add_all__U17$binop.data.in.0","op_hcompute_f4_0_stencil$add_all__U16$binop.data.out"], ["op_hcompute_f4_0_stencil$add_all__U18$binop.data.in.0","op_hcompute_f4_0_stencil$add_all__U17$binop.data.out"], ["op_hcompute_f4_0_stencil$add_all__U19$binop.data.in.0","op_hcompute_f4_0_stencil$add_all__U18$binop.data.out"], ["op_hcompute_f4_0_stencil$add_all__U20$binop.data.in.0","op_hcompute_f4_0_stencil$add_all__U19$binop.data.out"], - ["op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f4_0_stencil_port_controller$op_hcompute_f4_0_stencil_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_f4_1_stencil$add_all__U22$binop.data.in.0","op_hcompute_f4_1_stencil$add_all__U21$binop.data.out"], ["op_hcompute_f4_1_stencil$add_all__U23$binop.data.in.0","op_hcompute_f4_1_stencil$add_all__U22$binop.data.out"], ["op_hcompute_f4_1_stencil$add_all__U24$binop.data.in.0","op_hcompute_f4_1_stencil$add_all__U23$binop.data.out"], @@ -2558,18 +2558,18 @@ ["op_hcompute_f5_0_stencil$add_all__U32$binop.data.in.0","op_hcompute_f5_0_stencil$add_all__U31$binop.data.out"], ["op_hcompute_f5_0_stencil$add_all__U33$binop.data.in.0","op_hcompute_f5_0_stencil$add_all__U32$binop.data.out"], ["op_hcompute_f5_0_stencil$add_all__U34$binop.data.in.0","op_hcompute_f5_0_stencil$add_all__U33$binop.data.out"], - ["op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f5_0_stencil_port_controller$op_hcompute_f5_0_stencil_port_controller_Counter_2_garnet.clk_en"], ["op_hcompute_f5_1_stencil$add_all__U36$binop.data.in.0","op_hcompute_f5_1_stencil$add_all__U35$binop.data.out"], ["op_hcompute_f5_1_stencil$add_all__U37$binop.data.in.0","op_hcompute_f5_1_stencil$add_all__U36$binop.data.out"], ["op_hcompute_f5_1_stencil$add_all__U38$binop.data.in.0","op_hcompute_f5_1_stencil$add_all__U37$binop.data.out"], ["op_hcompute_f5_1_stencil$add_all__U39$binop.data.in.0","op_hcompute_f5_1_stencil$add_all__U38$binop.data.out"], ["op_hcompute_f5_1_stencil$add_all__U40$binop.data.in.0","op_hcompute_f5_1_stencil$add_all__U39$binop.data.out"], ["op_hcompute_f5_1_stencil$add_all__U41$binop.data.in.0","op_hcompute_f5_1_stencil$add_all__U40$binop.data.out"], - ["op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_Counter_2_garnet.clk_en"], - ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet.clk_en"], - ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet.clk_en"] + ["op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_f5_1_stencil_port_controller$op_hcompute_f5_1_stencil_port_controller_Counter_2_garnet.clk_en"], + ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const1_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_1_garnet.clk_en"], + ["op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_clk_en_const_lutcnst.bit.out","op_hcompute_hw_output_stencil_port_controller$op_hcompute_hw_output_stencil_port_controller_Counter_2_garnet.clk_en"] ] }, "hcompute_f3_0_stencil":{ diff --git a/aha_garnet_design_pond/nlmeans_simple/nlmeans_simple.json b/aha_garnet_design_pond/nlmeans_simple/nlmeans_simple.json new file mode 100644 index 000000000..7c5ffd779 --- /dev/null +++ b/aha_garnet_design_pond/nlmeans_simple/nlmeans_simple.json @@ -0,0 +1,2323 @@ +{"top":"global.nlmeans_simple", +"namespaces":{ + "global":{ + "modules":{ + "blur_d_stencil_clkwrk_dsa6_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_blur_d_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_blur_d_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_blur_d_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_blur_d_stencil_write_extra_ctrl","BitIn"] + ]], + "connections":[ + ["self.op_hcompute_blur_d_stencil_write.0","self.op_hcompute_blur_d_stencil_1_read.0"] + ] + }, + "blur_d_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_blur_d_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_blur_d_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_div_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_div_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_3_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_3_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_4_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_4_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_5_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_5_read_extra_ctrl","Bit"] + ]], + "connections":[ + ["self.op_hcompute_non_local_means_div_stencil_1_read.0","self.op_hcompute_blur_d_stencil_1_write.0"], + ["self.op_hcompute_non_local_means_sum_stencil_3_read.0","self.op_hcompute_blur_d_stencil_1_write.0"], + ["self.op_hcompute_non_local_means_sum_stencil_4_read.0","self.op_hcompute_blur_d_stencil_1_write.0"], + ["self.op_hcompute_non_local_means_sum_stencil_5_read.0","self.op_hcompute_blur_d_stencil_1_write.0"] + ] + }, + "blur_d_y_stencil_clkwrk_dsa7_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_blur_d_y_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_blur_d_y_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_blur_d_y_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_blur_d_y_stencil_write_extra_ctrl","BitIn"] + ]], + "connections":[ + ["self.op_hcompute_blur_d_y_stencil_write.0","self.op_hcompute_blur_d_y_stencil_1_read.0"] + ] + }, + "blur_d_y_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_blur_d_stencil_1_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_blur_d_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_blur_d_y_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_blur_d_y_stencil_1_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "d_reg__U0":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U1":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U10":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U11":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U12":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U13":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U14":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U15":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U16":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U17":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U18":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U19":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U2":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U20":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U21":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U22":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U23":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U24":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U25":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U26":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U27":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U28":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U29":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U3":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U30":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U31":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U32":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U33":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U34":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U35":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U36":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U37":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U38":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U39":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U4":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U40":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U41":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U42":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U43":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U44":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U45":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U46":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U47":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U5":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U6":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U7":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U8":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_reg__U9":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.clk","d_reg__U0.clk"], + ["self.op_hcompute_blur_d_y_stencil_1_write.0","d_reg__U0.in"], + ["d_reg__U1.in","d_reg__U0.out"], + ["self.clk","d_reg__U1.clk"], + ["d_reg__U2.in","d_reg__U1.out"], + ["self.clk","d_reg__U10.clk"], + ["d_reg__U9.out","d_reg__U10.in"], + ["d_reg__U11.in","d_reg__U10.out"], + ["self.clk","d_reg__U11.clk"], + ["d_reg__U12.in","d_reg__U11.out"], + ["self.clk","d_reg__U12.clk"], + ["d_reg__U13.in","d_reg__U12.out"], + ["self.clk","d_reg__U13.clk"], + ["d_reg__U14.in","d_reg__U13.out"], + ["self.clk","d_reg__U14.clk"], + ["d_reg__U15.in","d_reg__U14.out"], + ["self.clk","d_reg__U15.clk"], + ["d_reg__U16.in","d_reg__U15.out"], + ["self.op_hcompute_blur_d_stencil_1_read.3","d_reg__U15.out"], + ["self.clk","d_reg__U16.clk"], + ["d_reg__U17.in","d_reg__U16.out"], + ["self.clk","d_reg__U17.clk"], + ["d_reg__U18.in","d_reg__U17.out"], + ["self.clk","d_reg__U18.clk"], + ["d_reg__U19.in","d_reg__U18.out"], + ["self.clk","d_reg__U19.clk"], + ["d_reg__U20.in","d_reg__U19.out"], + ["self.clk","d_reg__U2.clk"], + ["d_reg__U3.in","d_reg__U2.out"], + ["self.clk","d_reg__U20.clk"], + ["d_reg__U21.in","d_reg__U20.out"], + ["self.clk","d_reg__U21.clk"], + ["d_reg__U22.in","d_reg__U21.out"], + ["self.clk","d_reg__U22.clk"], + ["d_reg__U23.in","d_reg__U22.out"], + ["self.clk","d_reg__U23.clk"], + ["d_reg__U24.in","d_reg__U23.out"], + ["self.clk","d_reg__U24.clk"], + ["d_reg__U25.in","d_reg__U24.out"], + ["self.clk","d_reg__U25.clk"], + ["d_reg__U26.in","d_reg__U25.out"], + ["self.clk","d_reg__U26.clk"], + ["d_reg__U27.in","d_reg__U26.out"], + ["self.clk","d_reg__U27.clk"], + ["d_reg__U28.in","d_reg__U27.out"], + ["self.clk","d_reg__U28.clk"], + ["d_reg__U29.in","d_reg__U28.out"], + ["self.clk","d_reg__U29.clk"], + ["d_reg__U30.in","d_reg__U29.out"], + ["self.clk","d_reg__U3.clk"], + ["d_reg__U4.in","d_reg__U3.out"], + ["self.clk","d_reg__U30.clk"], + ["d_reg__U31.in","d_reg__U30.out"], + ["self.clk","d_reg__U31.clk"], + ["d_reg__U32.in","d_reg__U31.out"], + ["self.op_hcompute_blur_d_stencil_1_read.1","d_reg__U31.out"], + ["self.clk","d_reg__U32.clk"], + ["d_reg__U33.in","d_reg__U32.out"], + ["self.clk","d_reg__U33.clk"], + ["d_reg__U34.in","d_reg__U33.out"], + ["self.clk","d_reg__U34.clk"], + ["d_reg__U35.in","d_reg__U34.out"], + ["self.clk","d_reg__U35.clk"], + ["d_reg__U36.in","d_reg__U35.out"], + ["self.clk","d_reg__U36.clk"], + ["d_reg__U37.in","d_reg__U36.out"], + ["self.clk","d_reg__U37.clk"], + ["d_reg__U38.in","d_reg__U37.out"], + ["self.clk","d_reg__U38.clk"], + ["d_reg__U39.in","d_reg__U38.out"], + ["self.clk","d_reg__U39.clk"], + ["d_reg__U40.in","d_reg__U39.out"], + ["self.clk","d_reg__U4.clk"], + ["d_reg__U5.in","d_reg__U4.out"], + ["self.clk","d_reg__U40.clk"], + ["d_reg__U41.in","d_reg__U40.out"], + ["self.clk","d_reg__U41.clk"], + ["d_reg__U42.in","d_reg__U41.out"], + ["self.clk","d_reg__U42.clk"], + ["d_reg__U43.in","d_reg__U42.out"], + ["self.clk","d_reg__U43.clk"], + ["d_reg__U44.in","d_reg__U43.out"], + ["self.clk","d_reg__U44.clk"], + ["d_reg__U45.in","d_reg__U44.out"], + ["self.clk","d_reg__U45.clk"], + ["d_reg__U46.in","d_reg__U45.out"], + ["self.clk","d_reg__U46.clk"], + ["d_reg__U47.in","d_reg__U46.out"], + ["self.clk","d_reg__U47.clk"], + ["self.op_hcompute_blur_d_stencil_1_read.0","d_reg__U47.out"], + ["self.clk","d_reg__U5.clk"], + ["d_reg__U6.in","d_reg__U5.out"], + ["self.clk","d_reg__U6.clk"], + ["d_reg__U7.in","d_reg__U6.out"], + ["self.clk","d_reg__U7.clk"], + ["d_reg__U8.in","d_reg__U7.out"], + ["self.clk","d_reg__U8.clk"], + ["d_reg__U9.in","d_reg__U8.out"], + ["self.clk","d_reg__U9.clk"], + ["self.op_hcompute_blur_d_y_stencil_1_write.0","self.op_hcompute_blur_d_stencil_1_read.2"] + ] + }, + "cu_op_hcompute_blur_d_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_stencil_clkwrk_dsa6_op_hcompute_blur_d_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_blur_d_stencil" + } + }, + "connections":[ + ["self.blur_d_stencil_clkwrk_dsa6_op_hcompute_blur_d_stencil_write.0","inner_compute.out_blur_d_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_stencil_clkwrk_dsa6_op_hcompute_blur_d_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["blur_d_y_stencil_op_hcompute_blur_d_stencil_1_read",["Array",4,["Array",16,"BitIn"]]], + ["blur_d_stencil_op_hcompute_blur_d_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_blur_d_stencil_1" + } + }, + "connections":[ + ["self.blur_d_stencil_clkwrk_dsa6_op_hcompute_blur_d_stencil_1_read.0","inner_compute.in0_blur_d_stencil.0"], + ["self.blur_d_y_stencil_op_hcompute_blur_d_stencil_1_read.0","inner_compute.in1_blur_d_y_stencil.0"], + ["self.blur_d_y_stencil_op_hcompute_blur_d_stencil_1_read.1","inner_compute.in1_blur_d_y_stencil.1"], + ["self.blur_d_y_stencil_op_hcompute_blur_d_stencil_1_read.2","inner_compute.in1_blur_d_y_stencil.2"], + ["self.blur_d_y_stencil_op_hcompute_blur_d_stencil_1_read.3","inner_compute.in1_blur_d_y_stencil.3"], + ["self.blur_d_stencil_op_hcompute_blur_d_stencil_1_write.0","inner_compute.out_blur_d_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_y_stencil_clkwrk_dsa7_op_hcompute_blur_d_y_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_blur_d_y_stencil" + } + }, + "connections":[ + ["self.blur_d_y_stencil_clkwrk_dsa7_op_hcompute_blur_d_y_stencil_write.0","inner_compute.out_blur_d_y_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_y_stencil_clkwrk_dsa7_op_hcompute_blur_d_y_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["d_stencil_op_hcompute_blur_d_y_stencil_1_read",["Array",4,["Array",16,"BitIn"]]], + ["blur_d_y_stencil_op_hcompute_blur_d_y_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_blur_d_y_stencil_1" + } + }, + "connections":[ + ["self.blur_d_y_stencil_clkwrk_dsa7_op_hcompute_blur_d_y_stencil_1_read.0","inner_compute.in0_blur_d_y_stencil.0"], + ["self.d_stencil_op_hcompute_blur_d_y_stencil_1_read.0","inner_compute.in1_d_stencil.0"], + ["self.d_stencil_op_hcompute_blur_d_y_stencil_1_read.1","inner_compute.in1_d_stencil.1"], + ["self.d_stencil_op_hcompute_blur_d_y_stencil_1_read.2","inner_compute.in1_d_stencil.2"], + ["self.d_stencil_op_hcompute_blur_d_y_stencil_1_read.3","inner_compute.in1_d_stencil.3"], + ["self.blur_d_y_stencil_op_hcompute_blur_d_y_stencil_1_write.0","inner_compute.out_blur_d_y_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_d_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["d_stencil_clkwrk_dsa8_op_hcompute_d_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_d_stencil" + } + }, + "connections":[ + ["self.d_stencil_clkwrk_dsa8_op_hcompute_d_stencil_write.0","inner_compute.out_d_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_d_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["d_stencil_clkwrk_dsa8_op_hcompute_d_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read",["Array",6,["Array",16,"BitIn"]]], + ["d_stencil_op_hcompute_d_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_d_stencil_1" + } + }, + "connections":[ + ["self.d_stencil_clkwrk_dsa8_op_hcompute_d_stencil_1_read.0","inner_compute.in0_d_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.0","inner_compute.in1_hw_input_global_wrapper_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.1","inner_compute.in1_hw_input_global_wrapper_stencil.1"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.2","inner_compute.in1_hw_input_global_wrapper_stencil.2"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.3","inner_compute.in1_hw_input_global_wrapper_stencil.3"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.4","inner_compute.in1_hw_input_global_wrapper_stencil.4"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read.5","inner_compute.in1_hw_input_global_wrapper_stencil.5"], + ["self.d_stencil_op_hcompute_d_stencil_1_write.0","inner_compute.out_d_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_input_global_wrapper_stencil" + } + }, + "connections":[ + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_input_global_wrapper_stencil_1" + } + }, + "connections":[ + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_input_global_wrapper_stencil_2" + } + }, + "connections":[ + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write.0","inner_compute.out_hw_input_global_wrapper_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_output_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["non_local_means_div_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_output_stencil" + } + }, + "connections":[ + ["self.non_local_means_div_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in0_non_local_means_div_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_hw_output_stencil_read.0","inner_compute.in1_non_local_means_sum_stencil.0"], + ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write.0","inner_compute.out_hw_output_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["non_local_means_div_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_output_stencil_1" + } + }, + "connections":[ + ["self.non_local_means_div_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute.in0_non_local_means_div_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_hw_output_stencil_1_read.0","inner_compute.in1_non_local_means_sum_stencil.0"], + ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write.0","inner_compute.out_hw_output_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["non_local_means_div_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_hw_output_stencil_2" + } + }, + "connections":[ + ["self.non_local_means_div_stencil_op_hcompute_hw_output_stencil_2_read.0","inner_compute.in0_non_local_means_div_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_hw_output_stencil_2_read.0","inner_compute.in1_non_local_means_sum_stencil.0"], + ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write.0","inner_compute.out_hw_output_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_div_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_div_stencil" + } + }, + "connections":[ + ["self.non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_write.0","inner_compute.out_non_local_means_div_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_div_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_stencil_op_hcompute_non_local_means_div_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_div_stencil_1" + } + }, + "connections":[ + ["self.blur_d_stencil_op_hcompute_non_local_means_div_stencil_1_read.0","inner_compute.in0_blur_d_stencil.0"], + ["self.non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_1_read.0","inner_compute.in1_non_local_means_div_stencil.0"], + ["self.non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_1_write.0","inner_compute.out_non_local_means_div_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_sum_stencil" + } + }, + "connections":[ + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_write.0","inner_compute.out_non_local_means_sum_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_1_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_sum_stencil_1" + } + }, + "connections":[ + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_1_write.0","inner_compute.out_non_local_means_sum_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_sum_stencil_2" + } + }, + "connections":[ + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_2_write.0","inner_compute.out_non_local_means_sum_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_stencil_op_hcompute_non_local_means_sum_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_3_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_sum_stencil_3" + } + }, + "connections":[ + ["self.blur_d_stencil_op_hcompute_non_local_means_sum_stencil_3_read.0","inner_compute.in0_blur_d_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_3_read.0","inner_compute.in1_hw_input_global_wrapper_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_3_read.0","inner_compute.in2_non_local_means_sum_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_3_write.0","inner_compute.out_non_local_means_sum_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_stencil_op_hcompute_non_local_means_sum_stencil_4_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_4_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_4_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_4_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_sum_stencil_4" + } + }, + "connections":[ + ["self.blur_d_stencil_op_hcompute_non_local_means_sum_stencil_4_read.0","inner_compute.in0_blur_d_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_4_read.0","inner_compute.in1_hw_input_global_wrapper_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_4_read.0","inner_compute.in2_non_local_means_sum_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_4_write.0","inner_compute.out_non_local_means_sum_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "cu_op_hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid_pass_in","BitIn"], + ["valid_pass_out","Bit"], + ["blur_d_stencil_op_hcompute_non_local_means_sum_stencil_5_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_5_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_5_read",["Array",1,["Array",16,"BitIn"]]], + ["non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_5_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "inner_compute":{ + "modref":"global.hcompute_non_local_means_sum_stencil_5" + } + }, + "connections":[ + ["self.blur_d_stencil_op_hcompute_non_local_means_sum_stencil_5_read.0","inner_compute.in0_blur_d_stencil.0"], + ["self.hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_5_read.0","inner_compute.in1_hw_input_global_wrapper_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_5_read.0","inner_compute.in2_non_local_means_sum_stencil.0"], + ["self.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_5_write.0","inner_compute.out_non_local_means_sum_stencil"], + ["self.valid_pass_out","self.valid_pass_in"] + ] + }, + "d_stencil_clkwrk_dsa8_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_d_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_d_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_d_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_d_stencil_write_extra_ctrl","BitIn"] + ]], + "connections":[ + ["self.op_hcompute_d_stencil_write.0","self.op_hcompute_d_stencil_1_read.0"] + ] + }, + "d_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_blur_d_y_stencil_1_read",["Array",4,["Array",16,"Bit"]]], + ["op_hcompute_blur_d_y_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_d_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_d_stencil_1_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_d_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U48"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2100],"cycle_stride":[4,16,640],"dimensionality":3,"extent":[4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,144]},"in2agg_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,640],"dimensionality":4,"extent":[4,4,36,35],"write_data_starting_addr":[0],"write_data_stride":[1,4,0,0]},"sram2tb_0":{"cycle_starting_addr":[2734],"cycle_stride":[4,16,640],"dimensionality":3,"extent":[4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,4,144],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[2736],"cycle_stride":[1,4,16,640],"dimensionality":4,"extent":[4,4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,0]}},"mode":"lake"} + }, + "ub_d_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_d_stencil_BANK_1":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U49"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2100],"cycle_stride":[4,16,640],"dimensionality":3,"extent":[4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,144]},"in2agg_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,640],"dimensionality":4,"extent":[4,4,36,35],"write_data_starting_addr":[0],"write_data_stride":[1,4,0,0]},"sram2tb_0":{"cycle_starting_addr":[3374],"cycle_stride":[4,16,640],"dimensionality":3,"extent":[4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,4,144],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[3376],"cycle_stride":[1,4,16,640],"dimensionality":4,"extent":[4,4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,0]}},"mode":"lake"} + }, + "ub_d_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_d_stencil_BANK_2":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U50"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[2100],"cycle_stride":[4,16,640],"dimensionality":3,"extent":[4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,144]},"in2agg_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,640],"dimensionality":4,"extent":[4,4,36,35],"write_data_starting_addr":[0],"write_data_stride":[1,4,0,0]},"sram2tb_0":{"cycle_starting_addr":[4014],"cycle_stride":[4,16,640],"dimensionality":3,"extent":[4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,4,144],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[4016],"cycle_stride":[1,4,16,640],"dimensionality":4,"extent":[4,4,36,35],"read_data_starting_addr":[0],"read_data_stride":[1,4,0,0]}},"mode":"lake"} + }, + "ub_d_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_d_stencil_BANK_0.clk","self.clk"], + ["ub_d_stencil_BANK_1.clk","self.clk"], + ["ub_d_stencil_BANK_2.clk","self.clk"], + ["ub_d_stencil_BANK_2.data_out_0","self.op_hcompute_blur_d_y_stencil_1_read.0"], + ["ub_d_stencil_BANK_1.data_out_0","self.op_hcompute_blur_d_y_stencil_1_read.1"], + ["self.op_hcompute_d_stencil_1_write.0","self.op_hcompute_blur_d_y_stencil_1_read.2"], + ["ub_d_stencil_BANK_0.data_out_0","self.op_hcompute_blur_d_y_stencil_1_read.3"], + ["ub_d_stencil_BANK_0.data_in_0","self.op_hcompute_d_stencil_1_write.0"], + ["ub_d_stencil_BANK_1.data_in_0","self.op_hcompute_d_stencil_1_write.0"], + ["ub_d_stencil_BANK_2.data_in_0","self.op_hcompute_d_stencil_1_write.0"], + ["ub_d_stencil_BANK_0.flush","self.reset"], + ["ub_d_stencil_BANK_1.flush","self.reset"], + ["ub_d_stencil_BANK_2.flush","self.reset"], + ["ub_d_stencil_BANK_0_clk_en_const.out","ub_d_stencil_BANK_0.clk_en"], + ["ub_d_stencil_BANK_0_clk_en_const.out","ub_d_stencil_BANK_0.rst_n"], + ["ub_d_stencil_BANK_1_clk_en_const.out","ub_d_stencil_BANK_1.clk_en"], + ["ub_d_stencil_BANK_1_clk_en_const.out","ub_d_stencil_BANK_1.rst_n"], + ["ub_d_stencil_BANK_2_clk_en_const.out","ub_d_stencil_BANK_2.clk_en"], + ["ub_d_stencil_BANK_2_clk_en_const.out","ub_d_stencil_BANK_2.rst_n"] + ] + }, + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__760":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_stencil","const_p0__760.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_stencil_1_769_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_2_770_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_3_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_4_blur_d_y_stencil_5_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","add_blur_d_stencil_1_769_770.in0"], + ["add_blur_d_y_stencil_3_768_769.out","add_blur_d_stencil_1_769_770.in1"], + ["add_blur_d_y_stencil_2_770_771.in1","add_blur_d_stencil_1_769_770.out"], + ["self.in1_blur_d_y_stencil.0","add_blur_d_y_stencil_2_770_771.in0"], + ["self.out_blur_d_stencil","add_blur_d_y_stencil_2_770_771.out"], + ["self.in1_blur_d_y_stencil.1","add_blur_d_y_stencil_3_768_769.in0"], + ["add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.out","add_blur_d_y_stencil_3_768_769.in1"], + ["self.in1_blur_d_y_stencil.2","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in0"], + ["self.in1_blur_d_y_stencil.3","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in1"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__731":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","const_p0__731.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_y_stencil_1_741_742":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_2_742_743":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_3_740_741":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_4_d_stencil_5_740":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","add_blur_d_y_stencil_1_741_742.in0"], + ["add_d_stencil_3_740_741.out","add_blur_d_y_stencil_1_741_742.in1"], + ["add_d_stencil_2_742_743.in1","add_blur_d_y_stencil_1_741_742.out"], + ["self.in1_d_stencil.0","add_d_stencil_2_742_743.in0"], + ["self.out_blur_d_y_stencil","add_d_stencil_2_742_743.out"], + ["self.in1_d_stencil.1","add_d_stencil_3_740_741.in0"], + ["add_d_stencil_4_d_stencil_5_740.out","add_d_stencil_3_740_741.in1"], + ["self.in1_d_stencil.2","add_d_stencil_4_d_stencil_5_740.in0"], + ["self.in1_d_stencil.3","add_d_stencil_4_d_stencil_5_740.in1"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__680":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_d_stencil","const_p0__680.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_696_702_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_698_700_701":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_1_701_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_695_695_696":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_697_697_698":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_699_699_700":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_695_695_696.out","add_696_702_703.in0"], + ["add_d_stencil_1_701_702.out","add_696_702_703.in1"], + ["self.out_d_stencil","add_696_702_703.out"], + ["mul_697_697_698.out","add_698_700_701.in0"], + ["mul_699_699_700.out","add_698_700_701.in1"], + ["add_d_stencil_1_701_702.in1","add_698_700_701.out"], + ["self.in0_d_stencil.0","add_d_stencil_1_701_702.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in0"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in1"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in0"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in1"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in0","self.in1_hw_input_global_wrapper_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in1","self.in1_hw_input_global_wrapper_stencil.1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in0","self.in1_hw_input_global_wrapper_stencil.2"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in1","self.in1_hw_input_global_wrapper_stencil.3"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in0","self.in1_hw_input_global_wrapper_stencil.4"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in1","self.in1_hw_input_global_wrapper_stencil.5"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__882":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__880":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_881_882_883":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_879_880_881":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_881_882_883.in1","const_p0__882.out"], + ["smin_879_880_881.in1","const_p255__880.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in1"], + ["smin_879_880_881.in0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.out"], + ["smax_881_882_883.out","self.out_hw_output_stencil"], + ["smin_879_880_881.out","smax_881_882_883.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__899":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__897":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_898_899_900":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_896_897_898":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_898_899_900.in1","const_p0__899.out"], + ["smin_896_897_898.in1","const_p255__897.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in1"], + ["smin_896_897_898.in0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.out"], + ["smax_898_899_900.out","self.out_hw_output_stencil"], + ["smin_896_897_898.out","smax_898_899_900.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__916":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__914":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_915_916_917":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_913_914_915":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_915_916_917.in1","const_p0__916.out"], + ["smin_913_914_915.in1","const_p255__914.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in1"], + ["smin_913_914_915.in0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.out"], + ["smax_915_916_917.out","self.out_hw_output_stencil"], + ["smin_913_914_915.out","smax_915_916_917.in0"] + ] + }, + "hcompute_non_local_means_div_stencil":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__787":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_div_stencil","const_p0__787.out"] + ] + }, + "hcompute_non_local_means_div_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_div_stencil_1_793_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_2_792_793":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__792":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + } + }, + "connections":[ + ["self.in1_non_local_means_div_stencil.0","add_non_local_means_div_stencil_1_793_794.in0"], + ["ashr_blur_d_stencil_2_792_793.out","add_non_local_means_div_stencil_1_793_794.in1"], + ["self.out_non_local_means_div_stencil","add_non_local_means_div_stencil_1_793_794.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_2_792_793.in0"], + ["const_p4__792.out","ashr_blur_d_stencil_2_792_793.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__803":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__803.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__806":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__806.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__809":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__809.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_1_817_818":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_3_815_816":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__815":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_7_816_817":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_1_817_818.in0"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.out","add_non_local_means_sum_stencil_1_817_818.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_1_817_818.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_3_815_816.in0"], + ["const_p4__815.out","ashr_blur_d_stencil_3_815_816.in1"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.in1","ashr_blur_d_stencil_3_815_816.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_7_816_817.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_2_838_839":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_4_836_837":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__836":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_8_837_838":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_2_838_839.in0"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.out","add_non_local_means_sum_stencil_2_838_839.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_2_838_839.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_4_836_837.in0"], + ["const_p4__836.out","ashr_blur_d_stencil_4_836_837.in1"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.in1","ashr_blur_d_stencil_4_836_837.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_8_837_838.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_3_859_860":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_5_857_858":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__857":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_9_858_859":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_3_859_860.in0"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.out","add_non_local_means_sum_stencil_3_859_860.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_3_859_860.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_5_857_858.in0"], + ["const_p4__857.out","ashr_blur_d_stencil_5_857_858.in1"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.in1","ashr_blur_d_stencil_5_857_858.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_9_858_859.in0"] + ] + }, + "hw_input_global_wrapper_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_d_stencil_1_read",["Array",6,["Array",16,"Bit"]]], + ["op_hcompute_d_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_input_global_wrapper_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_input_global_wrapper_stencil_2_write_extra_ctrl","BitIn"], + ["op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_sum_stencil_3_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_3_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_4_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_4_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_5_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_5_read_extra_ctrl","Bit"] + ]], + "instances":{ + "ub_hw_input_global_wrapper_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U51"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2062],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,35],"read_data_starting_addr":[20],"read_data_stride":[1,10],"write_data_starting_addr":[20],"write_data_stride":[1,2]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[82],"read_data_stride":[0,0,1,4,8]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_1":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U52"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2092],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_2":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U53"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2062],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,35],"read_data_starting_addr":[20],"read_data_stride":[1,10],"write_data_starting_addr":[20],"write_data_stride":[1,2]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[82],"read_data_stride":[0,0,1,4,8]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_3":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U54"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2092],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_4":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U55"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2062],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,35],"read_data_starting_addr":[20],"read_data_stride":[1,10],"write_data_starting_addr":[20],"write_data_stride":[1,2]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[82],"read_data_stride":[0,0,1,4,8]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_5":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U56"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[2092],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[0],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[2096],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,9,35],"read_data_starting_addr":[0],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_6":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U57"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[4060],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,8,32],"read_data_starting_addr":[20],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[116],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[4064],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,8,32],"read_data_starting_addr":[464],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_7":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U58"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[4060],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,8,32],"read_data_starting_addr":[20],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[116],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[4064],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,8,32],"read_data_starting_addr":[464],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_7_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_hw_input_global_wrapper_stencil_BANK_8":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U59"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[49],"cycle_stride":[64,640],"dimensionality":2,"extent":[10,40],"read_data_starting_addr":[0],"read_data_stride":[1,2],"write_data_starting_addr":[0],"write_data_stride":[1,10]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"sram2tb_0":{"cycle_starting_addr":[4060],"cycle_stride":[2,4,16,64,640],"dimensionality":5,"extent":[2,4,4,8,32],"read_data_starting_addr":[20],"read_data_stride":[1,10,0,1,10],"write_data_starting_addr":[116],"write_data_stride":[1,2,0,0,0]},"tb2out_0":{"cycle_starting_addr":[4064],"cycle_stride":[1,4,16,64,640],"dimensionality":5,"extent":[4,4,4,8,32],"read_data_starting_addr":[464],"read_data_stride":[1,8,1,0,0]}},"mode":"lake"} + }, + "ub_hw_input_global_wrapper_stencil_BANK_8_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_6.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_7.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_8.clk","self.clk"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_d_stencil_1_read.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.data_out_0","self.op_hcompute_d_stencil_1_read.1"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.data_out_0","self.op_hcompute_d_stencil_1_read.2"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.data_out_0","self.op_hcompute_d_stencil_1_read.3"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.data_out_0","self.op_hcompute_d_stencil_1_read.4"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.data_out_0","self.op_hcompute_d_stencil_1_read.5"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_7.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_1_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_8.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_2_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_6.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_6.data_out_0","self.op_hcompute_non_local_means_sum_stencil_3_read.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_7.data_out_0","self.op_hcompute_non_local_means_sum_stencil_4_read.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_8.data_out_0","self.op_hcompute_non_local_means_sum_stencil_5_read.0"], + ["ub_hw_input_global_wrapper_stencil_BANK_0.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_1.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_2.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_3.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_4.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_5.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_6.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_7.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_8.flush","self.reset"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_0.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_1.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_1_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_1.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_2.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_2_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_2.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_3.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_3_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_3.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_4.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_4_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_4.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_5.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_5_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_5.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_6.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_6_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_6.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_7_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_7.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_7_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_7.rst_n"], + ["ub_hw_input_global_wrapper_stencil_BANK_8_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_8.clk_en"], + ["ub_hw_input_global_wrapper_stencil_BANK_8_clk_en_const.out","ub_hw_input_global_wrapper_stencil_BANK_8.rst_n"] + ] + }, + "nlmeans_simple":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["reset","BitIn"], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_valid","Bit"], + ["hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_valid","Bit"], + ["hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write",["Array",1,["Array",16,"Bit"]]], + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_valid","Bit"], + ["hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write",["Array",1,["Array",16,"Bit"]]] + ]], + "instances":{ + "_U84":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U89":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U94":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "blur_d_stencil":{ + "modref":"global.blur_d_stencil_ub" + }, + "blur_d_stencil_clkwrk_dsa6":{ + "modref":"global.blur_d_stencil_clkwrk_dsa6_ub" + }, + "blur_d_y_stencil":{ + "modref":"global.blur_d_y_stencil_ub" + }, + "blur_d_y_stencil_clkwrk_dsa7":{ + "modref":"global.blur_d_y_stencil_clkwrk_dsa7_ub" + }, + "d_stencil":{ + "modref":"global.d_stencil_ub" + }, + "d_stencil_clkwrk_dsa8":{ + "modref":"global.d_stencil_clkwrk_dsa8_ub" + }, + "hw_input_global_wrapper_stencil":{ + "modref":"global.hw_input_global_wrapper_stencil_ub" + }, + "non_local_means_div_stencil":{ + "modref":"global.non_local_means_div_stencil_ub" + }, + "non_local_means_sum_stencil":{ + "modref":"global.non_local_means_sum_stencil_ub" + }, + "op_hcompute_blur_d_stencil":{ + "modref":"global.cu_op_hcompute_blur_d_stencil" + }, + "op_hcompute_blur_d_stencil_1":{ + "modref":"global.cu_op_hcompute_blur_d_stencil_1" + }, + "op_hcompute_blur_d_y_stencil":{ + "modref":"global.cu_op_hcompute_blur_d_y_stencil" + }, + "op_hcompute_blur_d_y_stencil_1":{ + "modref":"global.cu_op_hcompute_blur_d_y_stencil_1" + }, + "op_hcompute_d_stencil":{ + "modref":"global.cu_op_hcompute_d_stencil" + }, + "op_hcompute_d_stencil_1":{ + "modref":"global.cu_op_hcompute_d_stencil_1" + }, + "op_hcompute_hw_input_global_wrapper_stencil":{ + "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1":{ + "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_1" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U87" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U85"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40]}},"mode":"lake"} + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U86" + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U88" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2":{ + "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_2" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U82" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U80"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40]}},"mode":"lake"} + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U81" + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U83" + }, + "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U92" + }, + "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U90"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[16,640],"dimensionality":2,"extent":[40,40]}},"mode":"lake"} + }, + "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U91" + }, + "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U93" + }, + "op_hcompute_hw_output_stencil":{ + "modref":"global.cu_op_hcompute_hw_output_stencil" + }, + "op_hcompute_hw_output_stencil_1":{ + "modref":"global.cu_op_hcompute_hw_output_stencil_1" + }, + "op_hcompute_hw_output_stencil_1_exe_start":{ + "modref":"global.op_hcompute_hw_output_stencil_1_exe_start_pt__U74" + }, + "op_hcompute_hw_output_stencil_1_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U72"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[4207],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} + }, + "op_hcompute_hw_output_stencil_1_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_output_stencil_1_read_start":{ + "modref":"global.op_hcompute_hw_output_stencil_1_read_start_pt__U73" + }, + "op_hcompute_hw_output_stencil_1_write_start":{ + "modref":"global.op_hcompute_hw_output_stencil_1_write_start_pt__U75" + }, + "op_hcompute_hw_output_stencil_2":{ + "modref":"global.cu_op_hcompute_hw_output_stencil_2" + }, + "op_hcompute_hw_output_stencil_2_exe_start":{ + "modref":"global.op_hcompute_hw_output_stencil_2_exe_start_pt__U70" + }, + "op_hcompute_hw_output_stencil_2_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U68"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[4207],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} + }, + "op_hcompute_hw_output_stencil_2_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_output_stencil_2_read_start":{ + "modref":"global.op_hcompute_hw_output_stencil_2_read_start_pt__U69" + }, + "op_hcompute_hw_output_stencil_2_write_start":{ + "modref":"global.op_hcompute_hw_output_stencil_2_write_start_pt__U71" + }, + "op_hcompute_hw_output_stencil_exe_start":{ + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U78" + }, + "op_hcompute_hw_output_stencil_port_controller":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U76"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[4207],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} + }, + "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "op_hcompute_hw_output_stencil_read_start":{ + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U77" + }, + "op_hcompute_hw_output_stencil_write_start":{ + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U79" + }, + "op_hcompute_non_local_means_div_stencil":{ + "modref":"global.cu_op_hcompute_non_local_means_div_stencil" + }, + "op_hcompute_non_local_means_div_stencil_1":{ + "modref":"global.cu_op_hcompute_non_local_means_div_stencil_1" + }, + "op_hcompute_non_local_means_sum_stencil":{ + "modref":"global.cu_op_hcompute_non_local_means_sum_stencil" + }, + "op_hcompute_non_local_means_sum_stencil_1":{ + "modref":"global.cu_op_hcompute_non_local_means_sum_stencil_1" + }, + "op_hcompute_non_local_means_sum_stencil_2":{ + "modref":"global.cu_op_hcompute_non_local_means_sum_stencil_2" + }, + "op_hcompute_non_local_means_sum_stencil_3":{ + "modref":"global.cu_op_hcompute_non_local_means_sum_stencil_3" + }, + "op_hcompute_non_local_means_sum_stencil_4":{ + "modref":"global.cu_op_hcompute_non_local_means_sum_stencil_4" + }, + "op_hcompute_non_local_means_sum_stencil_5":{ + "modref":"global.cu_op_hcompute_non_local_means_sum_stencil_5" + } + }, + "connections":[ + ["self.clk","_U84.clk"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","_U84.in"], + ["self.clk","_U89.clk"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","_U89.in"], + ["self.clk","_U94.clk"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U94.in"], + ["self.clk","blur_d_stencil.clk"], + ["op_hcompute_blur_d_stencil_1.blur_d_stencil_op_hcompute_blur_d_stencil_1_write","blur_d_stencil.op_hcompute_blur_d_stencil_1_write"], + ["op_hcompute_non_local_means_div_stencil_1.blur_d_stencil_op_hcompute_non_local_means_div_stencil_1_read","blur_d_stencil.op_hcompute_non_local_means_div_stencil_1_read"], + ["op_hcompute_non_local_means_sum_stencil_3.blur_d_stencil_op_hcompute_non_local_means_sum_stencil_3_read","blur_d_stencil.op_hcompute_non_local_means_sum_stencil_3_read"], + ["op_hcompute_non_local_means_sum_stencil_4.blur_d_stencil_op_hcompute_non_local_means_sum_stencil_4_read","blur_d_stencil.op_hcompute_non_local_means_sum_stencil_4_read"], + ["op_hcompute_non_local_means_sum_stencil_5.blur_d_stencil_op_hcompute_non_local_means_sum_stencil_5_read","blur_d_stencil.op_hcompute_non_local_means_sum_stencil_5_read"], + ["self.reset","blur_d_stencil.reset"], + ["self.clk","blur_d_stencil_clkwrk_dsa6.clk"], + ["op_hcompute_blur_d_stencil_1.blur_d_stencil_clkwrk_dsa6_op_hcompute_blur_d_stencil_1_read","blur_d_stencil_clkwrk_dsa6.op_hcompute_blur_d_stencil_1_read"], + ["op_hcompute_blur_d_stencil.blur_d_stencil_clkwrk_dsa6_op_hcompute_blur_d_stencil_write","blur_d_stencil_clkwrk_dsa6.op_hcompute_blur_d_stencil_write"], + ["self.reset","blur_d_stencil_clkwrk_dsa6.reset"], + ["self.clk","blur_d_y_stencil.clk"], + ["op_hcompute_blur_d_stencil_1.blur_d_y_stencil_op_hcompute_blur_d_stencil_1_read","blur_d_y_stencil.op_hcompute_blur_d_stencil_1_read"], + ["op_hcompute_blur_d_y_stencil_1.blur_d_y_stencil_op_hcompute_blur_d_y_stencil_1_write","blur_d_y_stencil.op_hcompute_blur_d_y_stencil_1_write"], + ["self.reset","blur_d_y_stencil.reset"], + ["self.clk","blur_d_y_stencil_clkwrk_dsa7.clk"], + ["op_hcompute_blur_d_y_stencil_1.blur_d_y_stencil_clkwrk_dsa7_op_hcompute_blur_d_y_stencil_1_read","blur_d_y_stencil_clkwrk_dsa7.op_hcompute_blur_d_y_stencil_1_read"], + ["op_hcompute_blur_d_y_stencil.blur_d_y_stencil_clkwrk_dsa7_op_hcompute_blur_d_y_stencil_write","blur_d_y_stencil_clkwrk_dsa7.op_hcompute_blur_d_y_stencil_write"], + ["self.reset","blur_d_y_stencil_clkwrk_dsa7.reset"], + ["self.clk","d_stencil.clk"], + ["op_hcompute_blur_d_y_stencil_1.d_stencil_op_hcompute_blur_d_y_stencil_1_read","d_stencil.op_hcompute_blur_d_y_stencil_1_read"], + ["op_hcompute_d_stencil_1.d_stencil_op_hcompute_d_stencil_1_write","d_stencil.op_hcompute_d_stencil_1_write"], + ["self.reset","d_stencil.reset"], + ["self.clk","d_stencil_clkwrk_dsa8.clk"], + ["op_hcompute_d_stencil_1.d_stencil_clkwrk_dsa8_op_hcompute_d_stencil_1_read","d_stencil_clkwrk_dsa8.op_hcompute_d_stencil_1_read"], + ["op_hcompute_d_stencil.d_stencil_clkwrk_dsa8_op_hcompute_d_stencil_write","d_stencil_clkwrk_dsa8.op_hcompute_d_stencil_write"], + ["self.reset","d_stencil_clkwrk_dsa8.reset"], + ["self.clk","hw_input_global_wrapper_stencil.clk"], + ["op_hcompute_d_stencil_1.hw_input_global_wrapper_stencil_op_hcompute_d_stencil_1_read","hw_input_global_wrapper_stencil.op_hcompute_d_stencil_1_read"], + ["op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write","hw_input_global_wrapper_stencil.op_hcompute_hw_input_global_wrapper_stencil_1_write"], + ["op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write","hw_input_global_wrapper_stencil.op_hcompute_hw_input_global_wrapper_stencil_2_write"], + ["op_hcompute_hw_input_global_wrapper_stencil.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write","hw_input_global_wrapper_stencil.op_hcompute_hw_input_global_wrapper_stencil_write"], + ["op_hcompute_non_local_means_sum_stencil_3.hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_3_read","hw_input_global_wrapper_stencil.op_hcompute_non_local_means_sum_stencil_3_read"], + ["op_hcompute_non_local_means_sum_stencil_4.hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_4_read","hw_input_global_wrapper_stencil.op_hcompute_non_local_means_sum_stencil_4_read"], + ["op_hcompute_non_local_means_sum_stencil_5.hw_input_global_wrapper_stencil_op_hcompute_non_local_means_sum_stencil_5_read","hw_input_global_wrapper_stencil.op_hcompute_non_local_means_sum_stencil_5_read"], + ["self.reset","hw_input_global_wrapper_stencil.reset"], + ["self.clk","non_local_means_div_stencil.clk"], + ["op_hcompute_hw_output_stencil_1.non_local_means_div_stencil_op_hcompute_hw_output_stencil_1_read","non_local_means_div_stencil.op_hcompute_hw_output_stencil_1_read"], + ["op_hcompute_hw_output_stencil_2.non_local_means_div_stencil_op_hcompute_hw_output_stencil_2_read","non_local_means_div_stencil.op_hcompute_hw_output_stencil_2_read"], + ["op_hcompute_hw_output_stencil.non_local_means_div_stencil_op_hcompute_hw_output_stencil_read","non_local_means_div_stencil.op_hcompute_hw_output_stencil_read"], + ["op_hcompute_non_local_means_div_stencil_1.non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_1_read","non_local_means_div_stencil.op_hcompute_non_local_means_div_stencil_1_read"], + ["op_hcompute_non_local_means_div_stencil_1.non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_1_write","non_local_means_div_stencil.op_hcompute_non_local_means_div_stencil_1_write"], + ["op_hcompute_non_local_means_div_stencil.non_local_means_div_stencil_op_hcompute_non_local_means_div_stencil_write","non_local_means_div_stencil.op_hcompute_non_local_means_div_stencil_write"], + ["self.reset","non_local_means_div_stencil.reset"], + ["self.clk","non_local_means_sum_stencil.clk"], + ["op_hcompute_hw_output_stencil_1.non_local_means_sum_stencil_op_hcompute_hw_output_stencil_1_read","non_local_means_sum_stencil.op_hcompute_hw_output_stencil_1_read"], + ["op_hcompute_hw_output_stencil_2.non_local_means_sum_stencil_op_hcompute_hw_output_stencil_2_read","non_local_means_sum_stencil.op_hcompute_hw_output_stencil_2_read"], + ["op_hcompute_hw_output_stencil.non_local_means_sum_stencil_op_hcompute_hw_output_stencil_read","non_local_means_sum_stencil.op_hcompute_hw_output_stencil_read"], + ["op_hcompute_non_local_means_sum_stencil_1.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_1_write","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_1_write"], + ["op_hcompute_non_local_means_sum_stencil_2.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_2_write","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_2_write"], + ["op_hcompute_non_local_means_sum_stencil_3.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_3_read","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_3_read"], + ["op_hcompute_non_local_means_sum_stencil_3.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_3_write","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_3_write"], + ["op_hcompute_non_local_means_sum_stencil_4.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_4_read","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_4_read"], + ["op_hcompute_non_local_means_sum_stencil_4.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_4_write","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_4_write"], + ["op_hcompute_non_local_means_sum_stencil_5.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_5_read","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_5_read"], + ["op_hcompute_non_local_means_sum_stencil_5.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_5_write","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_5_write"], + ["op_hcompute_non_local_means_sum_stencil.non_local_means_sum_stencil_op_hcompute_non_local_means_sum_stencil_write","non_local_means_sum_stencil.op_hcompute_non_local_means_sum_stencil_write"], + ["self.reset","non_local_means_sum_stencil.reset"], + ["self.clk","op_hcompute_blur_d_stencil.clk"], + ["self.clk","op_hcompute_blur_d_stencil_1.clk"], + ["self.clk","op_hcompute_blur_d_y_stencil.clk"], + ["self.clk","op_hcompute_blur_d_y_stencil_1.clk"], + ["self.clk","op_hcompute_d_stencil.clk"], + ["self.clk","op_hcompute_d_stencil_1.clk"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil.clk"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read","op_hcompute_hw_input_global_wrapper_stencil.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1.clk"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read","op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_1_exe_start.in"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.clk"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.flush"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.rst_n"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid"], + ["op_hcompute_hw_input_global_wrapper_stencil_1_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.stencil_valid"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","op_hcompute_hw_input_global_wrapper_stencil_1_read_start.out"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2.clk"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read","op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_2_exe_start.in"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.clk"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.flush"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.rst_n"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid"], + ["op_hcompute_hw_input_global_wrapper_stencil_2_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.stencil_valid"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","op_hcompute_hw_input_global_wrapper_stencil_2_read_start.out"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid","op_hcompute_hw_input_global_wrapper_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_input_global_wrapper_stencil_port_controller.flush"], + ["op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const.out","op_hcompute_hw_input_global_wrapper_stencil_port_controller.rst_n"], + ["op_hcompute_hw_input_global_wrapper_stencil_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.stencil_valid"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], + ["self.clk","op_hcompute_hw_output_stencil.clk"], + ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write","op_hcompute_hw_output_stencil.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write"], + ["self.clk","op_hcompute_hw_output_stencil_1.clk"], + ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write","op_hcompute_hw_output_stencil_1.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write"], + ["op_hcompute_hw_output_stencil_1_port_controller.stencil_valid","op_hcompute_hw_output_stencil_1_exe_start.in"], + ["self.clk","op_hcompute_hw_output_stencil_1_port_controller.clk"], + ["op_hcompute_hw_output_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_1_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_output_stencil_1_port_controller.flush"], + ["op_hcompute_hw_output_stencil_1_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_1_port_controller.rst_n"], + ["op_hcompute_hw_output_stencil_1_read_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], + ["op_hcompute_hw_output_stencil_1_write_start.in","op_hcompute_hw_output_stencil_1_port_controller.stencil_valid"], + ["self.hw_output_stencil_clkwrk_4_op_hcompute_hw_output_stencil_1_write_valid","op_hcompute_hw_output_stencil_1_write_start.out"], + ["self.clk","op_hcompute_hw_output_stencil_2.clk"], + ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write","op_hcompute_hw_output_stencil_2.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write"], + ["op_hcompute_hw_output_stencil_2_port_controller.stencil_valid","op_hcompute_hw_output_stencil_2_exe_start.in"], + ["self.clk","op_hcompute_hw_output_stencil_2_port_controller.clk"], + ["op_hcompute_hw_output_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_2_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_output_stencil_2_port_controller.flush"], + ["op_hcompute_hw_output_stencil_2_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_2_port_controller.rst_n"], + ["op_hcompute_hw_output_stencil_2_read_start.in","op_hcompute_hw_output_stencil_2_port_controller.stencil_valid"], + ["op_hcompute_hw_output_stencil_2_write_start.in","op_hcompute_hw_output_stencil_2_port_controller.stencil_valid"], + ["self.hw_output_stencil_clkwrk_5_op_hcompute_hw_output_stencil_2_write_valid","op_hcompute_hw_output_stencil_2_write_start.out"], + ["op_hcompute_hw_output_stencil_port_controller.stencil_valid","op_hcompute_hw_output_stencil_exe_start.in"], + ["self.clk","op_hcompute_hw_output_stencil_port_controller.clk"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.clk_en"], + ["self.reset","op_hcompute_hw_output_stencil_port_controller.flush"], + ["op_hcompute_hw_output_stencil_port_controller_clk_en_const.out","op_hcompute_hw_output_stencil_port_controller.rst_n"], + ["op_hcompute_hw_output_stencil_read_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["op_hcompute_hw_output_stencil_write_start.in","op_hcompute_hw_output_stencil_port_controller.stencil_valid"], + ["self.hw_output_stencil_clkwrk_3_op_hcompute_hw_output_stencil_write_valid","op_hcompute_hw_output_stencil_write_start.out"], + ["self.clk","op_hcompute_non_local_means_div_stencil.clk"], + ["self.clk","op_hcompute_non_local_means_div_stencil_1.clk"], + ["self.clk","op_hcompute_non_local_means_sum_stencil.clk"], + ["self.clk","op_hcompute_non_local_means_sum_stencil_1.clk"], + ["self.clk","op_hcompute_non_local_means_sum_stencil_2.clk"], + ["self.clk","op_hcompute_non_local_means_sum_stencil_3.clk"], + ["self.clk","op_hcompute_non_local_means_sum_stencil_4.clk"], + ["self.clk","op_hcompute_non_local_means_sum_stencil_5.clk"] + ] + }, + "non_local_means_div_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_div_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_div_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_div_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_div_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_div_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_div_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_non_local_means_div_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U61"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3985],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"agg2sram_1":{"cycle_starting_addr":[4128],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3936],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2agg_1":{"cycle_starting_addr":[4079],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[4205],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[4061],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[4207],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]},"tb2out_1":{"cycle_starting_addr":[4063],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]}},"mode":"lake"} + }, + "ub_non_local_means_div_stencil_BANK_0_accum_reg":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U60"], "num_inputs":["Int",2], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[4063],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2regfile_1":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"write_data_starting_addr":[0],"write_data_stride":[0,1,0]},"regfile2out_0":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"read_data_starting_addr":[0],"read_data_stride":[0,1,0]}},"mode":"pond"} + }, + "ub_non_local_means_div_stencil_BANK_0_accum_reg_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_non_local_means_div_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_non_local_means_div_stencil_BANK_0.clk","self.clk"], + ["ub_non_local_means_div_stencil_BANK_0_accum_reg.clk","self.clk"], + ["ub_non_local_means_div_stencil_BANK_0.data_out_0","self.op_hcompute_hw_output_stencil_1_read.0"], + ["ub_non_local_means_div_stencil_BANK_0.data_out_0","self.op_hcompute_hw_output_stencil_2_read.0"], + ["ub_non_local_means_div_stencil_BANK_0.data_out_0","self.op_hcompute_hw_output_stencil_read.0"], + ["ub_non_local_means_div_stencil_BANK_0_accum_reg.data_out_pond_0","self.op_hcompute_non_local_means_div_stencil_1_read.0"], + ["ub_non_local_means_div_stencil_BANK_0.data_in_1","self.op_hcompute_non_local_means_div_stencil_1_write.0"], + ["ub_non_local_means_div_stencil_BANK_0_accum_reg.data_in_pond_1","self.op_hcompute_non_local_means_div_stencil_1_write.0"], + ["ub_non_local_means_div_stencil_BANK_0.data_in_0","self.op_hcompute_non_local_means_div_stencil_write.0"], + ["ub_non_local_means_div_stencil_BANK_0.flush","self.reset"], + ["ub_non_local_means_div_stencil_BANK_0_accum_reg.flush","self.reset"], + ["ub_non_local_means_div_stencil_BANK_0_clk_en_const.out","ub_non_local_means_div_stencil_BANK_0.clk_en"], + ["ub_non_local_means_div_stencil_BANK_0_accum_reg.data_in_pond_0","ub_non_local_means_div_stencil_BANK_0.data_out_1"], + ["ub_non_local_means_div_stencil_BANK_0_clk_en_const.out","ub_non_local_means_div_stencil_BANK_0.rst_n"], + ["ub_non_local_means_div_stencil_BANK_0_accum_reg_clk_en_const.out","ub_non_local_means_div_stencil_BANK_0_accum_reg.clk_en"], + ["ub_non_local_means_div_stencil_BANK_0_accum_reg_clk_en_const.out","ub_non_local_means_div_stencil_BANK_0_accum_reg.rst_n"] + ] + }, + "non_local_means_sum_stencil_ub":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["flush","BitIn"], + ["reset","BitIn"], + ["op_hcompute_hw_output_stencil_1_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_1_read_extra_ctrl","Bit"], + ["op_hcompute_hw_output_stencil_2_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_2_read_extra_ctrl","Bit"], + ["op_hcompute_hw_output_stencil_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_1_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_sum_stencil_1_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_sum_stencil_2_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_sum_stencil_2_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_sum_stencil_3_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_3_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_3_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_sum_stencil_3_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_sum_stencil_4_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_4_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_4_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_sum_stencil_4_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_sum_stencil_5_read",["Array",1,["Array",16,"Bit"]]], + ["op_hcompute_non_local_means_sum_stencil_5_read_extra_ctrl","Bit"], + ["op_hcompute_non_local_means_sum_stencil_5_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_sum_stencil_5_write_extra_ctrl","BitIn"], + ["op_hcompute_non_local_means_sum_stencil_write",["Array",1,["Array",16,"BitIn"]]], + ["op_hcompute_non_local_means_sum_stencil_write_extra_ctrl","BitIn"] + ]], + "instances":{ + "ub_non_local_means_sum_stencil_BANK_0":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U63"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3985],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"agg2sram_1":{"cycle_starting_addr":[4128],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3936],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2agg_1":{"cycle_starting_addr":[4079],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[4205],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[4061],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[4207],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]},"tb2out_1":{"cycle_starting_addr":[4063],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]}},"mode":"lake"} + }, + "ub_non_local_means_sum_stencil_BANK_0_accum_reg":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U62"], "num_inputs":["Int",2], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[4063],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2regfile_1":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"write_data_starting_addr":[0],"write_data_stride":[0,1,0]},"regfile2out_0":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"read_data_starting_addr":[0],"read_data_stride":[0,1,0]}},"mode":"pond"} + }, + "ub_non_local_means_sum_stencil_BANK_0_accum_reg_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_non_local_means_sum_stencil_BANK_0_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_non_local_means_sum_stencil_BANK_1":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U65"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3985],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"agg2sram_1":{"cycle_starting_addr":[4128],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3936],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2agg_1":{"cycle_starting_addr":[4079],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[4205],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[4061],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[4207],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]},"tb2out_1":{"cycle_starting_addr":[4063],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]}},"mode":"lake"} + }, + "ub_non_local_means_sum_stencil_BANK_1_accum_reg":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U64"], "num_inputs":["Int",2], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[4063],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2regfile_1":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"write_data_starting_addr":[0],"write_data_stride":[0,1,0]},"regfile2out_0":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"read_data_starting_addr":[0],"read_data_stride":[0,1,0]}},"mode":"pond"} + }, + "ub_non_local_means_sum_stencil_BANK_1_accum_reg_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_non_local_means_sum_stencil_BANK_1_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_non_local_means_sum_stencil_BANK_2":{ + "genref":"cgralib.Mem_amber", + "genargs":{"ID":["String","_U67"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[3985],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"agg2sram_1":{"cycle_starting_addr":[4128],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[3936],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2agg_1":{"cycle_starting_addr":[4079],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[4205],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_1":{"cycle_starting_addr":[4061],"cycle_stride":[64,640],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[4207],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]},"tb2out_1":{"cycle_starting_addr":[4063],"cycle_stride":[16,64,640],"dimensionality":3,"extent":[4,8,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,0]}},"mode":"lake"} + }, + "ub_non_local_means_sum_stencil_BANK_2_accum_reg":{ + "genref":"cgralib.Pond_amber", + "genargs":{"ID":["String","_U66"], "num_inputs":["Int",2], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[4063],"cycle_stride":[16,640],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"in2regfile_1":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"write_data_starting_addr":[0],"write_data_stride":[0,1,0]},"regfile2out_0":{"cycle_starting_addr":[4064],"cycle_stride":[1,16,640],"dimensionality":3,"extent":[16,32,32],"read_data_starting_addr":[0],"read_data_stride":[0,1,0]}},"mode":"pond"} + }, + "ub_non_local_means_sum_stencil_BANK_2_accum_reg_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "ub_non_local_means_sum_stencil_BANK_2_clk_en_const":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["ub_non_local_means_sum_stencil_BANK_0.clk","self.clk"], + ["ub_non_local_means_sum_stencil_BANK_0_accum_reg.clk","self.clk"], + ["ub_non_local_means_sum_stencil_BANK_1.clk","self.clk"], + ["ub_non_local_means_sum_stencil_BANK_1_accum_reg.clk","self.clk"], + ["ub_non_local_means_sum_stencil_BANK_2.clk","self.clk"], + ["ub_non_local_means_sum_stencil_BANK_2_accum_reg.clk","self.clk"], + ["ub_non_local_means_sum_stencil_BANK_1.data_out_0","self.op_hcompute_hw_output_stencil_1_read.0"], + ["ub_non_local_means_sum_stencil_BANK_2.data_out_0","self.op_hcompute_hw_output_stencil_2_read.0"], + ["ub_non_local_means_sum_stencil_BANK_0.data_out_0","self.op_hcompute_hw_output_stencil_read.0"], + ["ub_non_local_means_sum_stencil_BANK_1.data_in_0","self.op_hcompute_non_local_means_sum_stencil_1_write.0"], + ["ub_non_local_means_sum_stencil_BANK_2.data_in_0","self.op_hcompute_non_local_means_sum_stencil_2_write.0"], + ["ub_non_local_means_sum_stencil_BANK_0_accum_reg.data_out_pond_0","self.op_hcompute_non_local_means_sum_stencil_3_read.0"], + ["ub_non_local_means_sum_stencil_BANK_0.data_in_1","self.op_hcompute_non_local_means_sum_stencil_3_write.0"], + ["ub_non_local_means_sum_stencil_BANK_0_accum_reg.data_in_pond_1","self.op_hcompute_non_local_means_sum_stencil_3_write.0"], + ["ub_non_local_means_sum_stencil_BANK_1_accum_reg.data_out_pond_0","self.op_hcompute_non_local_means_sum_stencil_4_read.0"], + ["ub_non_local_means_sum_stencil_BANK_1.data_in_1","self.op_hcompute_non_local_means_sum_stencil_4_write.0"], + ["ub_non_local_means_sum_stencil_BANK_1_accum_reg.data_in_pond_1","self.op_hcompute_non_local_means_sum_stencil_4_write.0"], + ["ub_non_local_means_sum_stencil_BANK_2_accum_reg.data_out_pond_0","self.op_hcompute_non_local_means_sum_stencil_5_read.0"], + ["ub_non_local_means_sum_stencil_BANK_2.data_in_1","self.op_hcompute_non_local_means_sum_stencil_5_write.0"], + ["ub_non_local_means_sum_stencil_BANK_2_accum_reg.data_in_pond_1","self.op_hcompute_non_local_means_sum_stencil_5_write.0"], + ["ub_non_local_means_sum_stencil_BANK_0.data_in_0","self.op_hcompute_non_local_means_sum_stencil_write.0"], + ["ub_non_local_means_sum_stencil_BANK_0.flush","self.reset"], + ["ub_non_local_means_sum_stencil_BANK_0_accum_reg.flush","self.reset"], + ["ub_non_local_means_sum_stencil_BANK_1.flush","self.reset"], + ["ub_non_local_means_sum_stencil_BANK_1_accum_reg.flush","self.reset"], + ["ub_non_local_means_sum_stencil_BANK_2.flush","self.reset"], + ["ub_non_local_means_sum_stencil_BANK_2_accum_reg.flush","self.reset"], + ["ub_non_local_means_sum_stencil_BANK_0_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_0.clk_en"], + ["ub_non_local_means_sum_stencil_BANK_0_accum_reg.data_in_pond_0","ub_non_local_means_sum_stencil_BANK_0.data_out_1"], + ["ub_non_local_means_sum_stencil_BANK_0_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_0.rst_n"], + ["ub_non_local_means_sum_stencil_BANK_0_accum_reg_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_0_accum_reg.clk_en"], + ["ub_non_local_means_sum_stencil_BANK_0_accum_reg_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_0_accum_reg.rst_n"], + ["ub_non_local_means_sum_stencil_BANK_1_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_1.clk_en"], + ["ub_non_local_means_sum_stencil_BANK_1_accum_reg.data_in_pond_0","ub_non_local_means_sum_stencil_BANK_1.data_out_1"], + ["ub_non_local_means_sum_stencil_BANK_1_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_1.rst_n"], + ["ub_non_local_means_sum_stencil_BANK_1_accum_reg_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_1_accum_reg.clk_en"], + ["ub_non_local_means_sum_stencil_BANK_1_accum_reg_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_1_accum_reg.rst_n"], + ["ub_non_local_means_sum_stencil_BANK_2_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_2.clk_en"], + ["ub_non_local_means_sum_stencil_BANK_2_accum_reg.data_in_pond_0","ub_non_local_means_sum_stencil_BANK_2.data_out_1"], + ["ub_non_local_means_sum_stencil_BANK_2_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_2.rst_n"], + ["ub_non_local_means_sum_stencil_BANK_2_accum_reg_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_2_accum_reg.clk_en"], + ["ub_non_local_means_sum_stencil_BANK_2_accum_reg_clk_en_const.out","ub_non_local_means_sum_stencil_BANK_2_accum_reg.rst_n"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U87":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U86":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U88":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U82":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U81":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U83":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U92":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U91":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U93":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_1_exe_start_pt__U74":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_1_read_start_pt__U73":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_1_write_start_pt__U75":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_2_exe_start_pt__U70":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_2_read_start_pt__U69":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_2_write_start_pt__U71":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_exe_start_pt__U78":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_read_start_pt__U77":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "op_hcompute_hw_output_stencil_write_start_pt__U79":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "connections":[ + ["self.out","self.in"] + ] + } + }, + "generators":{ + "delay_tile":{ + "typegen":"global.delay_tile_TG", + "genparams":{"delay":"Int"} + }, + "raw_dual_port_sram_tile":{ + "typegen":"global.raw_dual_port_sram_TG", + "genparams":{"depth":"Int"} + }, + "raw_quad_port_memtile":{ + "typegen":"global.raw_quad_port_memtile_TG", + "genparams":{"depth":"Int"} + }, + "tahoe":{ + "typegen":"global.tahoe_TG", + "genparams":{"depth":"Int"} + } + }, + "typegens":{ + "delay_tile_TG":[{"delay":"Int"},"implicit"], + "raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"], + "raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"], + "tahoe_TG":[{"depth":"Int"},"implicit"] + } + } +} +} diff --git a/aha_garnet_design_pond/resnet_simple/resnet_simple.json b/aha_garnet_design_pond/resnet_simple/resnet_simple.json index 6ae533449..f915baca8 100644 --- a/aha_garnet_design_pond/resnet_simple/resnet_simple.json +++ b/aha_garnet_design_pond/resnet_simple/resnet_simple.json @@ -17,14 +17,10 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_conv_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[908],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[8962],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake","verilog_name":"lake__U0"} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[968],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[9022],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}},"mode":"lake"} }, "ub_conv_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -32,7 +28,6 @@ } }, "connections":[ - ["ub_conv_stencil_BANK_0.chain_chain_en","chain_en_const_U1.out"], ["ub_conv_stencil_BANK_0.clk","self.clk"], ["ub_conv_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], ["ub_conv_stencil_BANK_0.data_in_0","self.op_hcompute_conv_stencil_1_write.0"], @@ -231,14 +226,10 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,30],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[900],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake","verilog_name":"lake__U2"} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[960],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}},"mode":"lake"} }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -246,7 +237,6 @@ } }, "connections":[ - ["ub_hw_input_global_wrapper_stencil_BANK_0.chain_chain_en","chain_en_const_U3.out"], ["ub_hw_input_global_wrapper_stencil_BANK_0.clk","self.clk"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_out_0","self.op_hcompute_conv_stencil_1_read.0"], ["ub_hw_input_global_wrapper_stencil_BANK_0.data_in_0","self.op_hcompute_hw_input_global_wrapper_stencil_write.0"], @@ -268,8 +258,8 @@ "instances":{ "ub_hw_kernel_global_wrapper_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", - "genargs":{"ID":["String","_U4"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"pond","verilog_name":"pond__U4"} + "genargs":{"ID":["String","_U2"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}},"mode":"pond"} }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -285,7 +275,7 @@ ["ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const.out","ub_hw_kernel_global_wrapper_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U16":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -294,7 +284,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U15":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -303,7 +293,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U17":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -312,7 +302,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U11":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -321,7 +311,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U10":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -330,7 +320,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U12":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -339,7 +329,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U7":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U5":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -348,7 +338,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U6":{ + "op_hcompute_hw_output_stencil_read_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -357,7 +347,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U8":{ + "op_hcompute_hw_output_stencil_write_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -378,12 +368,12 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "_U13":{ + "_U11":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U18":{ + "_U16":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -407,71 +397,71 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U16" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U14"} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30]}},"mode":"lake"} }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U15" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U17" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15" }, "op_hcompute_hw_kernel_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_kernel_global_wrapper_stencil" }, "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U11" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9" }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U9"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,3],"dimensionality":2,"extent":[3,3]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U9"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,3],"dimensionality":2,"extent":[3,3]}},"mode":"lake"} }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_kernel_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U10" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8" }, "op_hcompute_hw_kernel_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U12" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U7" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U5" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U5"} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U6" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U4" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U8" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U6" } }, "connections":[ - ["self.clk","_U13.clk"], - ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","_U13.in"], - ["self.clk","_U18.clk"], - ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U18.in"], + ["self.clk","_U11.clk"], + ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read.0","_U11.in"], + ["self.clk","_U16.clk"], + ["self.hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read.0","_U16.in"], ["self.clk","conv_stencil.clk"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_read","conv_stencil.op_hcompute_conv_stencil_1_read"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], diff --git a/aha_garnet_design_pond/resnet_simple/resnet_simple_garnet.json b/aha_garnet_design_pond/resnet_simple/resnet_simple_garnet.json index 6d70a9c52..81e54d182 100644 --- a/aha_garnet_design_pond/resnet_simple/resnet_simple_garnet.json +++ b/aha_garnet_design_pond/resnet_simple/resnet_simple_garnet.json @@ -179,10 +179,6 @@ ["op_hcompute_hw_output_stencil_read_extra_ctrl","Bit"] ]], "instances":{ - "chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -190,8 +186,8 @@ }, "ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[908],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[8962],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[968],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[9022],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -212,26 +208,26 @@ ["conv_stencil_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U21":{ + "PE_init_U19":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U19":{ + "_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U20":{ + "_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U19.out","PE_init_U21.data.in.0"], - ["_U20.out","PE_init_U21.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U21.data.out"], + ["_U17.out","PE_init_U19.data.in.0"], + ["_U18.out","PE_init_U19.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U19.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -324,26 +320,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U24":{ + "PE_init_U22":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U22":{ + "_U20":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U23":{ + "_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U22.out","PE_init_U24.data.in.0"], - ["_U23.out","PE_init_U24.data.in.1"], - ["self.out_conv_stencil","PE_init_U24.data.out"] + ["_U20.out","PE_init_U22.data.in.0"], + ["_U21.out","PE_init_U22.data.in.1"], + ["self.out_conv_stencil","PE_init_U22.data.out"] ] }, "hcompute_conv_stencil_1":{ @@ -425,10 +421,6 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -436,8 +428,8 @@ }, "ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,30],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[900],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[960],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ @@ -466,8 +458,8 @@ }, "ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Pond", - "genargs":{"ID":["String","_U4"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "mode":["String","pond"]} + "genargs":{"ID":["String","_U2"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "mode":["String","pond"]} } }, "connections":[ @@ -478,7 +470,7 @@ ["ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet.clk_en","ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U16":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -487,7 +479,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U15":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -496,7 +488,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U17":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -505,7 +497,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U11":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -514,7 +506,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U10":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U8":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -523,7 +515,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U12":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -532,7 +524,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U7":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U5":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -541,7 +533,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U6":{ + "op_hcompute_hw_output_stencil_read_start_pt__U4":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -550,7 +542,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U8":{ + "op_hcompute_hw_output_stencil_write_start_pt__U6":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -571,25 +563,21 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U27":{ + "PE_init_U25":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U25":{ + "_U23":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U26":{ + "_U24":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "conv_stencil$chain_en_const_U1":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -597,12 +585,8 @@ }, "conv_stencil$ub_conv_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[908],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[902],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[8962],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} - }, - "hw_input_global_wrapper_stencil$chain_en_const_U3":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} + "genargs":{"ID":["String","_U0"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",2], "num_outputs":["Int",2], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[968],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,3,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,7,0,0]},"agg2sram_1":{"cycle_starting_addr":[4],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,3],"write_data_starting_addr":[0],"write_data_stride":[1,7]},"in2agg_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"write_data_starting_addr":[0],"write_data_stride":[1,12,0,0]},"in2agg_1":{"cycle_starting_addr":[0],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"write_data_starting_addr":[0],"write_data_stride":[1,12]},"sram2tb_0":{"cycle_starting_addr":[962],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[7,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,7,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,3,0,0]},"sram2tb_1":{"cycle_starting_addr":[9022],"cycle_stride":[4,28],"dimensionality":2,"extent":[7,28],"read_data_starting_addr":[0],"read_data_stride":[1,7],"write_data_starting_addr":[0],"write_data_stride":[1,3]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,0,0]},"tb2out_1":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28],"read_data_starting_addr":[0],"read_data_stride":[1,12]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -611,8 +595,8 @@ }, "hw_input_global_wrapper_stencil$ub_hw_input_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,30],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,30],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[900],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U1"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[6],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,30],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[960],"cycle_stride":[4,32,896,2688],"dimensionality":4,"extent":[8,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,8,0,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0,0]},"tb2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896,2688],"dimensionality":4,"extent":[28,28,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,0,1,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", @@ -621,20 +605,20 @@ }, "hw_kernel_global_wrapper_stencil$ub_hw_kernel_global_wrapper_stencil_BANK_0_garnet":{ "genref":"cgralib.Pond", - "genargs":{"ID":["String","_U4"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[904],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "mode":["String","pond"]} + "genargs":{"ID":["String","_U2"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, + "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[9],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[964],"cycle_stride":[1,32,896],"dimensionality":3,"extent":[28,28,9],"read_data_starting_addr":[0],"read_data_stride":[0,0,1]}}], "mode":["String","pond"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","out"]}, - "metadata":{"in2glb_0":{"cycle_starting_addr":[8964],"cycle_stride":[1],"dimensionality":1,"extent":[784],"write_data_starting_addr":[0],"write_data_stride":[1]}} + "metadata":{"in2glb_0":{"cycle_starting_addr":[9024],"cycle_stride":[1],"dimensionality":1,"extent":[784],"write_data_starting_addr":[0],"write_data_stride":[1]}} }, "io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0":{ "genref":"cgralib.IO", "genargs":{"width":["Int",16]}, "modargs":{"mode":["String","in"]}, - "metadata":{"glb2out_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[900],"read_data_starting_addr":[0],"read_data_stride":[1]}} + "metadata":{"glb2out_0":{"cycle_starting_addr":[2],"cycle_stride":[1,32],"dimensionality":2,"extent":[30,30],"read_data_starting_addr":[0],"read_data_stride":[1,30]}} }, "io16in_hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_0":{ "genref":"cgralib.IO", @@ -677,14 +661,14 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[8964],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}}], "init":["Json",null], "mode":["String","lake"]} + "genargs":{"ID":["String","_U3"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[9024],"cycle_stride":[1,28],"dimensionality":2,"extent":[28,28]}}], "init":["Json",null], "mode":["String","lake"]} } }, "connections":[ - ["_U25.out","PE_init_U27.data.in.0"], - ["_U26.out","PE_init_U27.data.in.1"], - ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U27.data.out"], + ["_U23.out","PE_init_U25.data.in.0"], + ["_U24.out","PE_init_U25.data.in.1"], + ["conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_1","PE_init_U25.data.out"], ["conv_stencil$ub_conv_stencil_BANK_0_garnet.clk_en","conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst.bit.out"], ["op_hcompute_conv_stencil_1$inner_compute$add_conv_stencil_1_666_667$binop.data.out","conv_stencil$ub_conv_stencil_BANK_0_garnet.data_in_0"], ["op_hcompute_conv_stencil_1$inner_compute$add_conv_stencil_1_666_667$binop.data.in.0","conv_stencil$ub_conv_stencil_BANK_0_garnet.data_out_0"], diff --git a/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy.json b/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy.json index 35632c03a..e5cd1375c 100644 --- a/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy.json +++ b/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy.json @@ -19,8 +19,8 @@ "instances":{ "cgpl_ctrl_U1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1039],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U2"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1039],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}},"mode":"lake"} }, "cgpl_ctrl_U1_clk_en_const":{ "modref":"corebit.const", @@ -29,7 +29,7 @@ "ub_conv_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U0"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]},"regfile2out_1":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"drive_by_cgpl_ctrl":true,"mode":"pond","verilog_name":"pond__U0"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[16],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]},"regfile2out_1":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} }, "ub_conv_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -247,8 +247,8 @@ "instances":{ "cgpl_ctrl_U4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1023],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U5"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1023],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}},"mode":"lake"} }, "cgpl_ctrl_U4_clk_en_const":{ "modref":"corebit.const", @@ -257,7 +257,7 @@ "ub_hw_input_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U3"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"drive_by_cgpl_ctrl":true,"mode":"pond","verilog_name":"pond__U3"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} }, "ub_hw_input_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -288,14 +288,10 @@ ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[1022],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[1024],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[1022],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[1024],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -303,7 +299,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U7.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_hw_input_stencil_read.0"], ["ub_input_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_input_cgra_stencil_write.0"], @@ -312,7 +307,7 @@ ["ub_input_cgra_stencil_BANK_0_clk_en_const.out","ub_input_cgra_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U12":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -321,7 +316,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U11":{ + "op_hcompute_hw_output_stencil_read_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -330,7 +325,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U13":{ + "op_hcompute_hw_output_stencil_write_start_pt__U11":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -339,7 +334,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_exe_start_pt__U16":{ + "op_hcompute_input_cgra_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -348,7 +343,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_read_start_pt__U15":{ + "op_hcompute_input_cgra_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -357,7 +352,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_write_start_pt__U17":{ + "op_hcompute_input_cgra_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -377,14 +372,10 @@ ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1076],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,8]},"in2agg_0":{"cycle_starting_addr":[1072],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[5118],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[5120],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1076],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,8]},"in2agg_0":{"cycle_starting_addr":[1072],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[5118],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[5120],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -392,7 +383,6 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U9.out"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_hw_output_stencil_read.0"], ["ub_output_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_output_cgra_stencil_write.0"], @@ -411,7 +401,7 @@ ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U18":{ + "_U16":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -438,43 +428,43 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U12" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U10" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[5120],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U10"} + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[5120],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U11" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U9" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U13" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U11" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" }, "op_hcompute_input_cgra_stencil_exe_start":{ - "modref":"global.op_hcompute_input_cgra_stencil_exe_start_pt__U16" + "modref":"global.op_hcompute_input_cgra_stencil_exe_start_pt__U14" }, "op_hcompute_input_cgra_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U14"} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} }, "op_hcompute_input_cgra_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_cgra_stencil_read_start":{ - "modref":"global.op_hcompute_input_cgra_stencil_read_start_pt__U15" + "modref":"global.op_hcompute_input_cgra_stencil_read_start_pt__U13" }, "op_hcompute_input_cgra_stencil_write_start":{ - "modref":"global.op_hcompute_input_cgra_stencil_write_start_pt__U17" + "modref":"global.op_hcompute_input_cgra_stencil_write_start_pt__U15" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -484,8 +474,8 @@ } }, "connections":[ - ["self.clk","_U18.clk"], - ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","_U18.in"], + ["self.clk","_U16.clk"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","_U16.in"], ["self.clk","conv_stencil.clk"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_read","conv_stencil.op_hcompute_conv_stencil_1_read"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], diff --git a/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy_garnet.json b/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy_garnet.json index bb3a64c20..604b88d97 100644 --- a/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy_garnet.json +++ b/aha_garnet_design_pond/three_level_pond_copy/three_level_pond_copy_garnet.json @@ -165,7 +165,7 @@ }, "cgpl_ctrl_U1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1039],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -200,26 +200,26 @@ ["conv_stencil_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U21":{ + "PE_init_U19":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U19":{ + "_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U20":{ + "_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U19.out","PE_init_U21.data.in.0"], - ["_U20.out","PE_init_U21.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U21.data.out"], + ["_U17.out","PE_init_U19.data.in.0"], + ["_U18.out","PE_init_U19.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U19.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -303,26 +303,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U24":{ + "PE_init_U22":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U22":{ + "_U20":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U23":{ + "_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U22.out","PE_init_U24.data.in.0"], - ["_U23.out","PE_init_U24.data.in.1"], - ["self.out_conv_stencil","PE_init_U24.data.out"] + ["_U20.out","PE_init_U22.data.in.0"], + ["_U21.out","PE_init_U22.data.in.1"], + ["self.out_conv_stencil","PE_init_U22.data.out"] ] }, "hcompute_conv_stencil_1":{ @@ -398,7 +398,7 @@ }, "cgpl_ctrl_U4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1023],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -434,10 +434,6 @@ ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -445,7 +441,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[1022],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[1024],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -457,7 +453,7 @@ ["ub_input_cgra_stencil_BANK_0_garnet.clk_en","ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U12":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -466,7 +462,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U11":{ + "op_hcompute_hw_output_stencil_read_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -475,7 +471,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U13":{ + "op_hcompute_hw_output_stencil_write_start_pt__U11":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -484,7 +480,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_exe_start_pt__U16":{ + "op_hcompute_input_cgra_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -493,7 +489,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_read_start_pt__U15":{ + "op_hcompute_input_cgra_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -502,7 +498,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_write_start_pt__U17":{ + "op_hcompute_input_cgra_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -522,10 +518,6 @@ ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -533,7 +525,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1076],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,8]},"in2agg_0":{"cycle_starting_addr":[1072],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[5118],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[5120],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -562,7 +554,7 @@ }, "conv_stencil$cgpl_ctrl_U1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1039],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}}], "init":["Json",null], "mode":["String","lake"]} }, "conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -582,7 +574,7 @@ }, "hw_input_stencil$cgpl_ctrl_U4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1023],"cycle_stride":[64,128],"dimensionality":2,"extent":[2,32]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -595,10 +587,6 @@ "genargs":{"ID":["String","_U3"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[32],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}}], "mode":["String","pond"]} }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -606,7 +594,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,0],"write_data_starting_addr":[0],"write_data_stride":[1,8]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"sram2tb_0":{"cycle_starting_addr":[1022],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,4,8],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"tb2out_0":{"cycle_starting_addr":[1024],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -646,13 +634,9 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[5120],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}}], "init":["Json",null], "mode":["String","lake"]} }, - "output_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -660,7 +644,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1076],"cycle_stride":[4,64,128],"dimensionality":3,"extent":[4,2,32],"read_data_starting_addr":[0],"read_data_stride":[1,0,0],"write_data_starting_addr":[0],"write_data_stride":[1,4,8]},"in2agg_0":{"cycle_starting_addr":[1072],"cycle_stride":[1,64,128],"dimensionality":3,"extent":[16,2,32],"write_data_starting_addr":[0],"write_data_stride":[1,0,0]},"sram2tb_0":{"cycle_starting_addr":[5118],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[5120],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, diff --git a/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled.json b/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled.json index f553bdc70..7fc60fe7e 100644 --- a/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled.json +++ b/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled.json @@ -19,8 +19,8 @@ "instances":{ "cgpl_ctrl_U1":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1175],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U2"} + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1175],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}},"mode":"lake"} }, "cgpl_ctrl_U1_clk_en_const":{ "modref":"corebit.const", @@ -29,7 +29,7 @@ "ub_conv_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U0"], "num_inputs":["Int",2], "num_outputs":["Int",2], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[20],"cycle_stride":[1,12,24],"dimensionality":3,"extent":[8,2,9],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20],"cycle_stride":[1,12,24],"dimensionality":3,"extent":[8,2,9],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]},"regfile2out_1":{"cycle_starting_addr":[232],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"drive_by_cgpl_ctrl":true,"mode":"pond","verilog_name":"pond__U0"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[20],"cycle_stride":[1,12,24],"dimensionality":3,"extent":[8,2,9],"write_data_starting_addr":[0],"write_data_stride":[1,8,0]},"in2regfile_1":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[16],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[20],"cycle_stride":[1,12,24],"dimensionality":3,"extent":[8,2,9],"read_data_starting_addr":[0],"read_data_stride":[1,8,0]},"regfile2out_1":{"cycle_starting_addr":[232],"cycle_stride":[1],"dimensionality":1,"extent":[16],"read_data_starting_addr":[0],"read_data_stride":[1]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} }, "ub_conv_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -247,8 +247,8 @@ "instances":{ "cgpl_ctrl_U4":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1151],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U5"} + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[1151],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}},"mode":"lake"} }, "cgpl_ctrl_U4_clk_en_const":{ "modref":"corebit.const", @@ -257,7 +257,7 @@ "ub_hw_input_stencil_BANK_0":{ "genref":"cgralib.Pond_amber", "genargs":{"ID":["String","_U3"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, - "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[24],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[44],"cycle_stride":[1,12,24,72],"dimensionality":4,"extent":[8,2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,1,0]}},"drive_by_cgpl_ctrl":true,"mode":"pond","verilog_name":"pond__U3"} + "metadata":{"config":{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[24],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[44],"cycle_stride":[1,12,24,72],"dimensionality":4,"extent":[8,2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,1,0]}},"drive_by_cgpl_ctrl":true,"mode":"pond"} }, "ub_hw_input_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -288,14 +288,10 @@ ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,36],"dimensionality":2,"extent":[9,32],"read_data_starting_addr":[0],"read_data_stride":[1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,36],"dimensionality":2,"extent":[36,32],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[4,12,272,1088],"dimensionality":4,"extent":[3,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,9,2,18],"write_data_starting_addr":[0],"write_data_stride":[1,1,2,0]},"tb2out_0":{"cycle_starting_addr":[1152],"cycle_stride":[1,12,272,1088],"dimensionality":4,"extent":[12,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake","verilog_name":"lake__U6"} + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,36],"dimensionality":2,"extent":[9,32],"read_data_starting_addr":[0],"read_data_stride":[1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,36],"dimensionality":2,"extent":[36,32],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[4,12,272,1088],"dimensionality":4,"extent":[3,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,9,2,18],"write_data_starting_addr":[0],"write_data_stride":[1,1,2,0]},"tb2out_0":{"cycle_starting_addr":[1152],"cycle_stride":[1,12,272,1088],"dimensionality":4,"extent":[12,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}},"mode":"lake"} }, "ub_input_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -303,7 +299,6 @@ } }, "connections":[ - ["ub_input_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U7.out"], ["ub_input_cgra_stencil_BANK_0.clk","self.clk"], ["ub_input_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_hw_input_stencil_read.0"], ["ub_input_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_input_cgra_stencil_write.0"], @@ -312,7 +307,7 @@ ["ub_input_cgra_stencil_BANK_0_clk_en_const.out","ub_input_cgra_stencil_BANK_0.rst_n"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U12":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -321,7 +316,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U11":{ + "op_hcompute_hw_output_stencil_read_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -330,7 +325,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U13":{ + "op_hcompute_hw_output_stencil_write_start_pt__U11":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -339,7 +334,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_exe_start_pt__U16":{ + "op_hcompute_input_cgra_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -348,7 +343,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_read_start_pt__U15":{ + "op_hcompute_input_cgra_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -357,7 +352,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_write_start_pt__U17":{ + "op_hcompute_input_cgra_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -377,14 +372,10 @@ ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_output_cgra_stencil_BANK_0":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1412],"cycle_stride":[4,8,272,1088],"dimensionality":4,"extent":[2,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,2,16]},"in2agg_0":{"cycle_starting_addr":[1408],"cycle_stride":[1,8,272,1088],"dimensionality":4,"extent":[8,2,4,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0]},"sram2tb_0":{"cycle_starting_addr":[18558],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[18560],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake","verilog_name":"lake__U8"} + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"agg2sram_0":{"cycle_starting_addr":[1412],"cycle_stride":[4,8,272,1088],"dimensionality":4,"extent":[2,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,2,16]},"in2agg_0":{"cycle_starting_addr":[1408],"cycle_stride":[1,8,272,1088],"dimensionality":4,"extent":[8,2,4,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0]},"sram2tb_0":{"cycle_starting_addr":[18558],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[18560],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}},"mode":"lake"} }, "ub_output_cgra_stencil_BANK_0_clk_en_const":{ "modref":"corebit.const", @@ -392,7 +383,6 @@ } }, "connections":[ - ["ub_output_cgra_stencil_BANK_0.chain_chain_en","chain_en_const_U9.out"], ["ub_output_cgra_stencil_BANK_0.clk","self.clk"], ["ub_output_cgra_stencil_BANK_0.data_out_0","self.op_hcompute_hw_output_stencil_read.0"], ["ub_output_cgra_stencil_BANK_0.data_in_0","self.op_hcompute_output_cgra_stencil_write.0"], @@ -411,7 +401,7 @@ ["input_host_stencil_op_hcompute_input_cgra_stencil_read",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U18":{ + "_U16":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} @@ -438,43 +428,43 @@ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U12" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U10" }, "op_hcompute_hw_output_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[18560],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U10"} + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[18560],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}},"mode":"lake"} }, "op_hcompute_hw_output_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U11" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U9" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U13" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U11" }, "op_hcompute_input_cgra_stencil":{ "modref":"global.cu_op_hcompute_input_cgra_stencil" }, "op_hcompute_input_cgra_stencil_exe_start":{ - "modref":"global.op_hcompute_input_cgra_stencil_exe_start_pt__U16" + "modref":"global.op_hcompute_input_cgra_stencil_exe_start_pt__U14" }, "op_hcompute_input_cgra_stencil_port_controller":{ "genref":"cgralib.Mem_amber", - "genargs":{"ID":["String","_U14"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, - "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,36],"dimensionality":2,"extent":[36,32]}},"mode":"lake","verilog_name":"aff_ctrl_counter__U14"} + "genargs":{"ID":["String","_U12"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "metadata":{"config":{"stencil_valid":{"cycle_starting_addr":[0],"cycle_stride":[1,36],"dimensionality":2,"extent":[36,32]}},"mode":"lake"} }, "op_hcompute_input_cgra_stencil_port_controller_clk_en_const":{ "modref":"corebit.const", "modargs":{"value":["Bool",true]} }, "op_hcompute_input_cgra_stencil_read_start":{ - "modref":"global.op_hcompute_input_cgra_stencil_read_start_pt__U15" + "modref":"global.op_hcompute_input_cgra_stencil_read_start_pt__U13" }, "op_hcompute_input_cgra_stencil_write_start":{ - "modref":"global.op_hcompute_input_cgra_stencil_write_start_pt__U17" + "modref":"global.op_hcompute_input_cgra_stencil_write_start_pt__U15" }, "op_hcompute_output_cgra_stencil":{ "modref":"global.cu_op_hcompute_output_cgra_stencil" @@ -484,8 +474,8 @@ } }, "connections":[ - ["self.clk","_U18.clk"], - ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","_U18.in"], + ["self.clk","_U16.clk"], + ["self.input_host_stencil_op_hcompute_input_cgra_stencil_read.0","_U16.in"], ["self.clk","conv_stencil.clk"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_read","conv_stencil.op_hcompute_conv_stencil_1_read"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], diff --git a/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled_garnet.json b/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled_garnet.json index b9d86b9e1..155ccce29 100644 --- a/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled_garnet.json +++ b/aha_garnet_design_pond/three_level_pond_rolled/three_level_pond_rolled_garnet.json @@ -165,7 +165,7 @@ }, "cgpl_ctrl_U1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1175],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -200,26 +200,26 @@ ["conv_stencil_op_hcompute_conv_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "PE_init_U21":{ + "PE_init_U19":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U19":{ + "_U17":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U20":{ + "_U18":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U19.out","PE_init_U21.data.in.0"], - ["_U20.out","PE_init_U21.data.in.1"], - ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U21.data.out"], + ["_U17.out","PE_init_U19.data.in.0"], + ["_U18.out","PE_init_U19.data.in.1"], + ["self.conv_stencil_op_hcompute_conv_stencil_write.0","PE_init_U19.data.out"], ["self.valid_pass_out","self.valid_pass_in"] ] }, @@ -303,26 +303,26 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "PE_init_U24":{ + "PE_init_U22":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","alu"], "width":["Int",16]}, "modargs":{"alu_op":["String","add"], "data0_mode":["String","BYPASS"], "data0_value":[["BitVector",16],"16'h0000"], "data1_mode":["String","BYPASS"], "data1_value":[["BitVector",16],"16'h0000"], "signed":["Bool",false]} }, - "_U22":{ + "_U20":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "_U23":{ + "_U21":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["_U22.out","PE_init_U24.data.in.0"], - ["_U23.out","PE_init_U24.data.in.1"], - ["self.out_conv_stencil","PE_init_U24.data.out"] + ["_U20.out","PE_init_U22.data.in.0"], + ["_U21.out","PE_init_U22.data.in.1"], + ["self.out_conv_stencil","PE_init_U22.data.out"] ] }, "hcompute_conv_stencil_1":{ @@ -398,7 +398,7 @@ }, "cgpl_ctrl_U4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1151],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}}], "init":["Json",null], "mode":["String","lake"]} }, "ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -434,10 +434,6 @@ ["op_hcompute_input_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -445,7 +441,7 @@ }, "ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,36],"dimensionality":2,"extent":[9,32],"read_data_starting_addr":[0],"read_data_stride":[1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,36],"dimensionality":2,"extent":[36,32],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[4,12,272,1088],"dimensionality":4,"extent":[3,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,9,2,18],"write_data_starting_addr":[0],"write_data_stride":[1,1,2,0]},"tb2out_0":{"cycle_starting_addr":[1152],"cycle_stride":[1,12,272,1088],"dimensionality":4,"extent":[12,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -457,7 +453,7 @@ ["ub_input_cgra_stencil_BANK_0_garnet.clk_en","ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst.bit.out"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U12":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U10":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -466,7 +462,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U11":{ + "op_hcompute_hw_output_stencil_read_start_pt__U9":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -475,7 +471,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U13":{ + "op_hcompute_hw_output_stencil_write_start_pt__U11":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -484,7 +480,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_exe_start_pt__U16":{ + "op_hcompute_input_cgra_stencil_exe_start_pt__U14":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -493,7 +489,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_read_start_pt__U15":{ + "op_hcompute_input_cgra_stencil_read_start_pt__U13":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -502,7 +498,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_input_cgra_stencil_write_start_pt__U17":{ + "op_hcompute_input_cgra_stencil_write_start_pt__U15":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -522,10 +518,6 @@ ["op_hcompute_output_cgra_stencil_write_extra_ctrl","BitIn"] ]], "instances":{ - "chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -533,7 +525,7 @@ }, "ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1412],"cycle_stride":[4,8,272,1088],"dimensionality":4,"extent":[2,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,2,16]},"in2agg_0":{"cycle_starting_addr":[1408],"cycle_stride":[1,8,272,1088],"dimensionality":4,"extent":[8,2,4,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0]},"sram2tb_0":{"cycle_starting_addr":[18558],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[18560],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, @@ -562,7 +554,7 @@ }, "conv_stencil$cgpl_ctrl_U1_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U2"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1175],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}}], "init":["Json",null], "mode":["String","lake"]} }, "conv_stencil$ub_conv_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -582,7 +574,7 @@ }, "hw_input_stencil$cgpl_ctrl_U4_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U5"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[1151],"cycle_stride":[272,1088],"dimensionality":2,"extent":[4,16]}}], "init":["Json",null], "mode":["String","lake"]} }, "hw_input_stencil$ub_hw_input_stencil_BANK_0_clk_en_const_lutcnst":{ @@ -595,10 +587,6 @@ "genargs":{"ID":["String","_U3"], "num_inputs":["Int",1], "num_outputs":["Int",1], "width":["Int",16]}, "modargs":{"config":["Json",{"in2regfile_0":{"cycle_starting_addr":[0],"cycle_stride":[1],"dimensionality":1,"extent":[24],"write_data_starting_addr":[0],"write_data_stride":[1]},"regfile2out_0":{"cycle_starting_addr":[44],"cycle_stride":[1,12,24,72],"dimensionality":4,"extent":[8,2,3,3],"read_data_starting_addr":[0],"read_data_stride":[1,12,1,0]}}], "mode":["String","pond"]} }, - "input_cgra_stencil$chain_en_const_U7":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -606,7 +594,7 @@ }, "input_cgra_stencil$ub_input_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U6"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[4],"cycle_stride":[4,36],"dimensionality":2,"extent":[9,32],"read_data_starting_addr":[0],"read_data_stride":[1,1],"write_data_starting_addr":[0],"write_data_stride":[1,9]},"in2agg_0":{"cycle_starting_addr":[0],"cycle_stride":[1,36],"dimensionality":2,"extent":[36,32],"write_data_starting_addr":[0],"write_data_stride":[1,4]},"sram2tb_0":{"cycle_starting_addr":[1150],"cycle_stride":[4,12,272,1088],"dimensionality":4,"extent":[3,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,9,2,18],"write_data_starting_addr":[0],"write_data_stride":[1,1,2,0]},"tb2out_0":{"cycle_starting_addr":[1152],"cycle_stride":[1,12,272,1088],"dimensionality":4,"extent":[12,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,4,8,0]}}], "init":["Json",null], "mode":["String","lake"]} }, "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0":{ @@ -646,13 +634,9 @@ }, "op_hcompute_hw_output_stencil_port_controller_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U10"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",0], "num_outputs":["Int",0], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",true], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"stencil_valid":{"cycle_starting_addr":[18560],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32]}}], "init":["Json",null], "mode":["String","lake"]} }, - "output_cgra_stencil$chain_en_const_U9":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",false]} - }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_clk_en_const_lutcnst":{ "genref":"cgralib.PE", "genargs":{"numbitports":["Int",3], "numdataports":["Int",2], "op_kind":["String","bit"], "width":["Int",16]}, @@ -660,7 +644,7 @@ }, "output_cgra_stencil$ub_output_cgra_stencil_BANK_0_garnet":{ "genref":"cgralib.Mem", - "genargs":{"ID":["String","_U8"], "ctrl_width":["Int",16], "has_chain_en":["Bool",true], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, + "genargs":{"ID":["String","_U7"], "ctrl_width":["Int",16], "has_chain_en":["Bool",false], "has_external_addrgen":["Bool",false], "has_flush":["Bool",true], "has_read_valid":["Bool",false], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "is_rom":["Bool",false], "num_inputs":["Int",1], "num_outputs":["Int",1], "use_prebuilt_mem":["Bool",true], "width":["Int",16]}, "modargs":{"config":["Json",{"agg2sram_0":{"cycle_starting_addr":[1412],"cycle_stride":[4,8,272,1088],"dimensionality":4,"extent":[2,2,4,16],"read_data_starting_addr":[0],"read_data_stride":[1,0,2,0],"write_data_starting_addr":[0],"write_data_stride":[1,8,2,16]},"in2agg_0":{"cycle_starting_addr":[1408],"cycle_stride":[1,8,272,1088],"dimensionality":4,"extent":[8,2,4,16],"write_data_starting_addr":[0],"write_data_stride":[1,0,8,0]},"sram2tb_0":{"cycle_starting_addr":[18558],"cycle_stride":[4,32],"dimensionality":2,"extent":[8,32],"read_data_starting_addr":[0],"read_data_stride":[1,8],"write_data_starting_addr":[0],"write_data_stride":[1,0]},"tb2out_0":{"cycle_starting_addr":[18560],"cycle_stride":[1,32],"dimensionality":2,"extent":[32,32],"read_data_starting_addr":[0],"read_data_stride":[1,0]}}], "init":["Json",null], "mode":["String","lake"]} } }, diff --git a/app.cpp b/app.cpp index 4db0b5d3d..97e095259 100644 --- a/app.cpp +++ b/app.cpp @@ -760,88 +760,6 @@ umap* opt_schedule_dimension(vector deps) { return nullptr; } -pair -extract_div_free_linear_rational_approximation(isl_aff* aff_bound) { - int in_dims = num_in_dims(aff_bound); - int out_dims = num_out_dims(aff_bound); - int div_dims = num_div_dims(aff_bound); - - //cout << "in_dims = " << in_dims << endl; - //cout << "out_dims = " << out_dims << endl; - //cout << "div_dims = " << div_dims << endl; - - assert(in_dims == 1); - assert(out_dims == 1); - //assert(div_dims == 0); - - for (int i = 0; i < div_dims; i++) { - auto dc = isl_aff_get_coefficient_val(aff_bound, isl_dim_div, i); - assert(isl_val_is_zero(dc)); - } - - isl_val* b = isl_aff_get_constant_val(aff_bound); - isl_val* k = isl_aff_get_coefficient_val(aff_bound, isl_dim_in, 0); - //cout << "b = " << str(b) << endl; - //cout << "k = " << str(k) << endl; - - return {k, b}; -} - -pair -extract_linear_rational_approximation(isl_aff* aff_bound) { - cout << "Extracting linear rational approximation: " << str(aff_bound) << endl; - - int in_dims = num_in_dims(aff_bound); - int out_dims = num_out_dims(aff_bound); - int div_dims = num_div_dims(aff_bound); - - //cout << "in_dims = " << in_dims << endl; - //cout << "out_dims = " << out_dims << endl; - //cout << "div_dims = " << div_dims << endl; - - assert(in_dims == 1); - assert(out_dims == 1); - //cout << "div dims = " << div_dims << endl; - - if (div_dims == 0) { - auto dkb = extract_div_free_linear_rational_approximation(aff_bound); - auto k = dkb.first; - auto b = dkb.second; - //cout << "b = " << str(b) << endl; - //cout << "k = " << str(k) << endl; - - return {k, b}; - } else { - //cout << "Getting div bound for: " << str(aff_bound) << endl; - //cout << "Div exprs..." << endl; - for (int i = 0; i < div_dims; i++) { - auto dexpr = isl_aff_get_div(aff_bound, i); - //cout << tab(1) << str(dexpr) << endl; - } - assert(div_dims == 1); - - isl_val* k = isl_aff_get_coefficient_val(aff_bound, isl_dim_in, 0); - isl_val* b = isl_aff_get_constant_val(aff_bound); - - isl_aff* div_expr = isl_aff_get_div(aff_bound, 0); - //cout << "Div: " << str(div_expr) << endl; - auto dkb = extract_div_free_linear_rational_approximation(div_expr); - //cout << "div k = " << str(dkb.first) << endl; - //cout << "div b = " << str(dkb.second) << endl; - - //assert(isl_val_is_zero(dkb.second)); - assert(isl_val_is_zero(k)); - - isl_val* final_b = add(dkb.second, b); - //cout << "final k = " << str(dkb.first) << endl; - //cout << "final b = " << str(final_b) << endl; - - //assert(false); - - return {dkb.first, final_b}; - } -} - map simplify(const vector >& terms) { map > simplified; for (auto t : terms) { diff --git a/bit_io_header.json b/bit_io_header.json new file mode 100644 index 000000000..fc3647cd4 --- /dev/null +++ b/bit_io_header.json @@ -0,0 +1,14 @@ +{"namespaces":{ + "global":{ + "modules":{ + "BitIO":{ + "type":["Record",[ + ["in","BitIn"], + ["out","Bit"] + ]], + "modparams":{"mode":"String"} + } + } + } +} +} diff --git a/build_set_test.cpp b/build_set_test.cpp index 3470ddc0c..d0f4d1ae7 100644 --- a/build_set_test.cpp +++ b/build_set_test.cpp @@ -1193,6 +1193,7 @@ void upsample_vectorization_test() { generate_hls_code(buf); + buf.simplify_floor_div_expr(); map buffers; buffers.insert({"ups", buf}); buffer_vectorization({1}, {"ups"}, 4, buffers); @@ -1235,6 +1236,7 @@ void upsample_pad_test() { generate_hls_code(buf); + buf.simplify_floor_div_expr(); map buffers; buffers.insert({"ups", buf}); buffer_vectorization({1}, {"ups"}, 4, buffers); @@ -1272,7 +1274,7 @@ void rolled_conv_reorder_test() { buf.access_map["read"] = rdmap(ctx, "{ read[root = 0, i, j] -> conv_rolled[i + j] : 0 <= i <= 2 and 0 <= j < 12}"); buf.schedule["read"] = - isl_union_map_read_from_str(ctx, "{ read[root = 0, i, j] -> [j + 3*i + 16] : 0 <= i <= 2 and 0 <= j < 12}"); + isl_union_map_read_from_str(ctx, "{ read[root = 0, i, j] -> [j + 16*i + 16] : 0 <= i <= 2 and 0 <= j < 12}"); buf.isIn["read"] = false; generate_hls_code(buf); @@ -1377,6 +1379,159 @@ void stride_conv_test() { } +void rolled_conv2D_test() { + struct isl_ctx *ctx; + ctx = isl_ctx_alloc(); + + UBuffer buf; + buf.name = "conv2D_rolled"; + buf.ctx = ctx; + + buf.domain["write"] = + isl_set_read_from_str(ctx, "{ write[root = 0, i, j] : 0 <= i < 16 and 0<=j<16}"); + buf.access_map["write"] = + rdmap(ctx, "{ write[root = 0, i, j] -> conv2D_rolled[i, j] : 0 <= i < 16 and 0<=j<16}}"); + buf.schedule["write"] = + isl_union_map_read_from_str(ctx, "{ write[root = 0, i, j] -> [16*i + j] : 0 <= i < 16 and 0<=j<16}}"); + buf.isIn["write"] = true; + map_insert(buf.port_bundles, string("write"), string("write")); + + // Read 0 through 7 + buf.domain["read"] = + isl_set_read_from_str(ctx, "{ read[root = 0, i, j, ii, jj] : 0 <= i < 12 and 0 <= j < 12 and 0 <= ii < 4 and 0 <= jj < 4}"); + buf.access_map["read"] = + rdmap(ctx, "{ read[root = 0, i, j, ii, jj] -> conv2D_rolled[i + ii, j + jj] : 0 <= i < 12 and 0 <= j < 12 and 0 <= ii < 4 and 0 <= jj < 4}"); + buf.schedule["read"] = + isl_union_map_read_from_str(ctx, "{ read[root = 0, i, j, ii, jj] -> [jj + 4*ii + 16*j + 256*i + 256] : 0 <= i < 12 and 0 <= j < 12 and 0 <= ii < 4 and 0 <= jj < 4}"); + buf.isIn["read"] = false; + map_insert(buf.port_bundles, string("read"), string("read")); + + generate_hls_code(buf); + + map buffers; + buffers.insert({"conv2D_rolled", buf}); + buffer_vectorization({1}, {"conv2D_rolled"}, 4, buffers); + + + for (auto& it: buffers) { + auto & buf = it.second; + buf.simplify_address_space(); + buf.linear_address_space(to_set(buf.global_range()), 4); + } + + generate_hls_code_unit_test(buffers, buf.name); + + generate_vectorization_unit_testbench(buf); + + int res = cmd("clang++ -std=c++11 unit_tb_conv2D_rolled.cpp conv2D_rolled.cpp conv2D_rolled_vec.cpp" ); + assert(res == 0); + + res = system("./a.out"); + assert(res == 0); +} + +void outer_rolled_conv2D_test() { + struct isl_ctx *ctx; + ctx = isl_ctx_alloc(); + + UBuffer buf; + buf.name = "conv2D_outer_rolled"; + buf.ctx = ctx; + + buf.domain["write"] = + isl_set_read_from_str(ctx, "{ write[root = 0, i, j] : 0 <= i < 16 and 0<=j<16}"); + buf.access_map["write"] = + rdmap(ctx, "{ write[root = 0, i, j] -> conv2D_outer_rolled[i, j] : 0 <= i < 16 and 0<=j<16}}"); + buf.schedule["write"] = + isl_union_map_read_from_str(ctx, "{ write[root = 0, i, j] -> [16*i + j] : 0 <= i < 16 and 0<=j<16}}"); + buf.isIn["write"] = true; + map_insert(buf.port_bundles, string("write"), string("write")); + + // Read 0 through 7 + buf.domain["read"] = + isl_set_read_from_str(ctx, "{ read[root = 0, i, j, ii, jj] : 0 <= i < 7 and 0 <= j < 7 and 0 <= ii < 8 and 0 <= jj < 8}"); + buf.access_map["read"] = + rdmap(ctx, "{ read[root = 0, i, j, ii, jj] -> conv2D_outer_rolled[i + ii, j + jj] : 0 <= i < 7 and 0 <= j < 7 and 0 <= ii < 8 and 0 <= jj < 8}"); + buf.schedule["read"] = + isl_union_map_read_from_str(ctx, "{ read[root = 0, i, j, ii, jj] -> [jj + 12*ii + 96*j + 768*i + 256] : 0 <= i < 7 and 0 <= j < 7 and 0 <= ii < 8 and 0 <= jj < 8}"); + buf.isIn["read"] = false; + map_insert(buf.port_bundles, string("read"), string("read")); + + generate_hls_code(buf); + + map buffers; + buffers.insert({"conv2D_outer_rolled", buf}); + buffer_vectorization({1}, {"conv2D_outer_rolled"}, 4, buffers); + + for (auto& it: buffers) { + auto & buf = it.second; + buf.simplify_address_space(); + buf.linear_address_space(to_set(buf.global_range()), 4); + } + + generate_hls_code_unit_test(buffers, buf.name); + + generate_vectorization_unit_testbench(buf); + + int res = cmd("clang++ -std=c++11 unit_tb_conv2D_outer_rolled.cpp conv2D_outer_rolled.cpp conv2D_outer_rolled_vec.cpp" ); + assert(res == 0); + + res = system("./a.out"); + assert(res == 0); +} + +void upsample_2d_unit_test() { + struct isl_ctx *ctx; + ctx = isl_ctx_alloc(); + + UBuffer buf; + buf.name = "up2D"; + buf.ctx = ctx; + + buf.domain["write"] = + isl_set_read_from_str(ctx, "{ write[root = 0, i, j] : 0 <= i < 16 and 0<=j<16}"); + buf.access_map["write"] = + rdmap(ctx, "{ write[root = 0, i, j] -> up2D[i, j] : 0 <= i < 16 and 0<=j<16}}"); + buf.schedule["write"] = + isl_union_map_read_from_str(ctx, "{ write[root = 0, i, j] -> [64*i + 2*j] : 0 <= i < 16 and 0<=j<16}}"); + buf.isIn["write"] = true; + map_insert(buf.port_bundles, string("write"), string("write")); + + // Read 0 through 7 + buf.domain["read"] = + isl_set_read_from_str(ctx, "{ read[root = 0, i, j] : 0 <= i < 32 and 0 <= j < 32}"); + buf.access_map["read"] = + rdmap(ctx, "{ read[root = 0, i, j] -> up2D[floor(i/2) , floor(j/2) ] : 0 <= i < 32 and 0 <= j < 32 }"); + buf.schedule["read"] = + isl_union_map_read_from_str(ctx, "{ read[root = 0, i, j] -> [j + 32*i + 16] : 0 <= i < 32 and 0 <= j < 32}"); + buf.isIn["read"] = false; + map_insert(buf.port_bundles, string("read"), string("read")); + + generate_hls_code(buf); + buf.simplify_floor_div_expr(); + + map buffers; + buffers.insert({"up2D", buf}); + buffer_vectorization({1}, {"up2D"}, 4, buffers); + + for (auto& it: buffers) { + auto & buf = it.second; + buf.simplify_address_space(); + buf.linear_address_space(to_set(buf.global_range()), 4); + } + + generate_hls_code_unit_test(buffers, buf.name); + + generate_vectorization_unit_testbench(buf); + + int res = cmd("clang++ -std=c++11 unit_tb_up2D.cpp up2D.cpp up2D_vec.cpp" ); + assert(res == 0); + + res = system("./a.out"); + assert(res == 0); +} + + void rolled_conv_test() { struct isl_ctx *ctx; ctx = isl_ctx_alloc(); @@ -11694,42 +11849,147 @@ void blur_and_downsample_test() { void test_if_complex(); void test_loop_perfection(); + + + + /* + * l is the long sequence, s is the short sequence, + * This function will return a array with length of s, + * each item of the array is the align position in the long sequence + * it will also return the min diff + */ +pair > find_best_alignment(vector & l, vector & s) { + if (s.size() == 1) { + int val = pick(s); + int min_diff = INT_MAX; + int target_idx = -1; + for (int i = 0; i < l.size(); i ++) { + int diff = abs(val - l.at(i)); + if (diff < min_diff) { + target_idx = i; + min_diff = diff; + } + } + assert(target_idx >= 0); + return {min_diff, {target_idx}}; + } else { + int range = l.size() - s.size() + 1; + int min_diff = INT_MAX; + vector align_idx; + for (int i = 0; i < range; i ++) { + vector s_tail(s.begin() + 1, s.end()); + vector l_tail(l.begin() + i + 1, l.end()); + auto ret = find_best_alignment(l_tail, s_tail); + int cur_diff = ret.first + abs(l.at(i) - s.at(0)); + if (cur_diff < min_diff) { + min_diff = cur_diff; + + //update the align idx array + align_idx.clear(); + align_idx.push_back(i); + for (auto idx: ret.second) { + align_idx.push_back(idx + i + 1); + } + } + } + return {min_diff, align_idx}; + } +} + +void print_alignment(vector & a, vector & b) { + + auto val_alignment_pair = find_best_alignment(a, b); + cout << "min diff : " << val_alignment_pair.first << endl; + cout << "alignment array: " << val_alignment_pair.second << endl << endl;; +} + +vector get_alignment_array(vector& a, vector& b) { + auto val_alignment_pair = find_best_alignment(a, b); + auto val_alignment = val_alignment_pair.second; + auto it = val_alignment.begin(); + vector alignment_arr({0}); + for (int i = 0; i < a.size(); i ++) { + if(*it == i) { + alignment_arr.push_back((int) (it - val_alignment.begin() + 1)); + it ++; + } else { + alignment_arr.push_back(-1); + } + } + assert(alignment_arr.size() == a.size() + 1); + return alignment_arr; +} + + void playground() { - test_loop_perfection(); + { + prog app = camera_pipeline_2x2_unroll(); + app.pretty_print(); + loop_split(app); + app.pretty_print(); + assert(false); + } + + { + vector a = {3, 40, 3, 40}; + vector b = {44, 44}; + print_alignment(a, b); + cout << get_alignment_array(a, b) << endl; + + a = {39, 40, 5, 90}; + b = {44, 44}; + print_alignment(a, b); + cout << get_alignment_array(a, b) << endl; + + assert(false); + + } { isl_ctx* ctx = isl_ctx_alloc(); - auto acc_0 = isl_map_read_from_str(ctx,"{ [i0]-> [3*i0]: 0<=i0<8}"); - auto delta_set = isl_map_deltas(acc_0); - cout << "Delta: " << str(delta_set) << endl; + auto sched_wr = isl_map_read_from_str(ctx,"{ wr[root=0, i0, i1]-> [8*i0 + i1, 0]: 0<=i0<8 and 0<=i1<8}"); + auto sched_rd = isl_map_read_from_str(ctx,"{ rd[root=0, i0, i1]-> [8*i0 + i1 + 9, 1]: 0<=i0<7 and 0<=i1<7}"); + auto lexm = simplify(lex_gt(sched_rd, sched_wr)); + cout << "read deps" << str(lexmax(lexm)) << endl; + //for (auto pt: get_points(domain(sched_rd))) { + // auto m = lexmax(its(lexm, to_set(pt))); + // cout << "\t pt: " << str(pt) << "\n\t\t" << str(m) << endl; + //} + auto lexm_wr = simplify(lex_gt(sched_wr, sched_rd)); + cout << "wr deps" << str(lexmax(lexm_wr)) << endl; + for (auto pt: get_points(domain(sched_wr))) { + auto m = lexmax(its(lexm_wr, to_set(pt))); + cout << "\t pt: " << str(pt) << "\n\t\t" << str(m) << endl; + } assert(false); } { isl_ctx* ctx = isl_ctx_alloc(); - auto acc_0 = isl_map_read_from_str(ctx,"{ op[i0, i1]-> [4000 + i1]: i0=0 and i1=0}"); - auto aff = get_aff(acc_0); + auto acc_0 = isl_map_read_from_str(ctx,"{ a[root=0, i0, i1]-> [0]: 0<=i0<8 and 0<=i1<8}"); + auto sched_0 = isl_map_read_from_str(ctx,"{ s[root = 0, i0, i1]-> [10*i0+i1]: 0<=i0<8 and 0<=i1<8}"); + map dim2pad = get_all_domain_pad_dims(sched_0, acc_0); + cout << "Dim2pad: " << dim2pad << endl; assert(false); } + { + auto sp_mem = create_single_port_wide_fetch_memory(4, 512, 2); + sp_mem.print_points(); + + auto dp_mem = create_dual_port_memory(512); + dp_mem.print_points(); + assert(false); + } + test_loop_perfection(); { isl_ctx* ctx = isl_ctx_alloc(); - auto acc_0 = isl_map_read_from_str(ctx,"{ op[i0, i1]-> data[i0 + i1]: 0<=i0<3 and 0 <= i1 <= 7}"); - auto sched = isl_map_read_from_str(ctx,"{ op[i0, i1]-> [10 + i0*10 + i1]: 0<=i0<3and 0 <= i1 <= 7 }"); - auto read_ir = get_vectorized_read_simplified(acc_0, sched, {}, 2, 0); - auto acc_vec = read_ir.first; - auto sched_vec = read_ir.second; - cout << "After vec read access map: " << str(simplify_expr(acc_vec)) << endl; - cout << "After vec read sched: " << str(sched_vec) << endl; + auto acc_0 = isl_map_read_from_str(ctx,"{ [i0]-> [3*i0]: 0<=i0<8}"); + auto delta_set = isl_map_deltas(acc_0); + cout << "Delta: " << str(delta_set) << endl; assert(false); } { isl_ctx* ctx = isl_ctx_alloc(); - auto acc_0 = isl_map_read_from_str(ctx,"{ op[i0, i1]-> data[i0 + i1]: 0<=i0<8 and 0 <= i1 <= 2}"); - auto sched = isl_map_read_from_str(ctx,"{ op[i0, i1]-> [14 + i0*3 + i1]: 0<=i0<8and 0 <= i1 <= 2 }"); - get_vectorized_read_simplified(acc_0, sched, {}, 0, 0, false); - auto read_ir = get_vectorized_read(acc_0, sched, {}, 4, 0); - auto acc_vec = read_ir.first; - auto sched_vec = read_ir.second; - cout << "After vec read access map: " << str(simplify_expr(acc_vec)) << endl; - cout << "After vec read sched: " << str(sched_vec) << endl; + auto acc_0 = isl_map_read_from_str(ctx,"{ op[i0, i1]-> [4000 + i1]: i0=0 and i1=0}"); + auto aff = get_aff(acc_0); assert(false); } { @@ -12932,12 +13192,14 @@ int run_verilator_on(const std::string& top_module, if (extra_flag) { #ifdef CGRAFLOW cmd("echo $CLKWRK_PATH"); - verilator_build = cmd("verilator -Wall --cc " + sep_list(verilog_files, "", "", " ") + " --exe --build --trace " + tb_file + " -CFLAGS -I$CLKWRK_PATH --top-module " + top_module + " -Wno-UNUSED -Wno-PINMISSING -Wno-DECLFILENAME -Wno-WIDTH -Wno-UNDRIVEN -Wno-CASEINCOMPLETE -Wno-MODDUP -Wno-UNOPTFLAT -Wno-CMPCONST"); + cmd("echo $FP_COMPT_PATH"); + verilator_build = cmd("verilator -Wall --cc " + sep_list(verilog_files, "", "", " ") + " --exe --build --trace " + tb_file + " -CFLAGS -I$CLKWRK_PATH -I$FP_COMP_PATH --top-module " + top_module + " -Wno-UNUSED -Wno-PINMISSING -Wno-DECLFILENAME -Wno-WIDTH -Wno-UNDRIVEN -Wno-CASEINCOMPLETE -Wno-MODDUP -Wno-UNOPTFLAT -Wno-CMPCONST -Wno-LATCH -Wno-VARHIDDEN"); #else - verilator_build = cmd("verilator -Wall --cc " + sep_list(verilog_files, "", "", " ") + " --exe --build --trace " + tb_file + " --top-module " + top_module + " -Wno-UNUSED -Wno-PINMISSING -Wno-DECLFILENAME -Wno-WIDTH -Wno-UNDRIVEN -Wno-CASEINCOMPLETE -Wno-MODDUP -Wno-UNOPTFLAT -Wno-CMPCONST"); + //verilator_build = cmd("verilator -Wall --cc " + sep_list(verilog_files, "", "", " ") + " --exe --build --trace " + tb_file + " --top-module " + top_module + " -Wno-UNUSED -Wno-PINMISSING -Wno-DECLFILENAME -Wno-WIDTH -Wno-UNDRIVEN -Wno-CASEINCOMPLETE -Wno-MODDUP -Wno-UNOPTFLAT -Wno-CMPCONST"); + verilator_build = cmd("verilator -Wall --cc " + sep_list(verilog_files, "", "", " ") + " -exe --build --trace " + tb_file + " --top-module " + top_module + " -I$FP_COMP_PATH -Wno-UNUSED -Wno-PINMISSING -Wno-DECLFILENAME -Wno-WIDTH -Wno-UNDRIVEN -Wno-CASEINCOMPLETE -Wno-MODDUP -Wno-UNOPTFLAT -Wno-CMPCONST -Wno-VARHIDDEN"); #endif } else { - verilator_build = cmd("verilator -Wall --cc " + sep_list(verilog_files, "", "", " ") + " --exe --build " + tb_file + " --top-module " + top_module + " -Wno-UNUSED -Wno-WIDTH -Wno-PINMISSING -Wno-DECLFILENAME"); + verilator_build = cmd("verilator -Wall --cc " + sep_list(verilog_files, "", "", " ") + " --exe --build --trace " + tb_file + " --top-module " + top_module + " -Wno-UNUSED -Wno-WIDTH -Wno-PINMISSING -Wno-DECLFILENAME"); } assert(verilator_build == 0); @@ -12983,7 +13245,7 @@ void run_verilator_tb(const std::string& name) { void generate_verilog_tb(const std::string& name) { cmd("echo $LD_LIBRARY_PATH"); - int to_verilog_res = cmd("${COREIR_PATH}/bin/coreir --inline --load_libs commonlib,cwlib --input " + name + ".json --output " + name + ".v -p \"rungenerators; wireclocks-clk; deletedeadinstances; add-dummy-inputs\""); + int to_verilog_res = cmd("${COREIR_PATH}/bin/coreir --inline --load_libs commonlib,cwlib --input " + name + ".json --output " + name + ".v -p \"rungenerators; wireclocks-clk; wireclocks-arst; deletedeadinstances; add-dummy-inputs\""); assert(to_verilog_res == 0); } @@ -12991,7 +13253,7 @@ void generate_verilog_tb(const std::string& name) { void generate_garnet_verilog_top(CodegenOptions& options, const std::string& name) { cmd("echo $LD_LIBRARY_PATH"); - int to_verilog_res = cmd("${COREIR_PATH}/bin/coreir --inline --load_libs commonlib,cwlib,cgralib --input " + options.dir + "/"+name +".json --output " + name + ".v -p \"rungenerators; wireclocks-clk; deletedeadinstances; add-dummy-inputs\""); + int to_verilog_res = cmd("${COREIR_PATH}/bin/coreir --inline --load_libs float,float_DW,commonlib,cwlib,cgralib --input " + options.dir + "/"+name +".json --output " + name + ".v -p \"rungenerators; wireclocks-clk; wireclocks-arst; deletedeadinstances; add-dummy-inputs\""); assert(to_verilog_res == 0); //run verilator on all the generated verilog @@ -13008,7 +13270,7 @@ void generate_cgra_tb(std::map buffers_opt, prog prg, CodegenOp CoreIRLoadLibrary_commonlib(context); CoreIRLoadLibrary_cwlib(context); schedule_info hwinfo; - hwinfo.use_dse_compute = false; + hwinfo.use_metamapper = false; opt.rtl_options.use_prebuilt_memory = true; opt.rtl_options.use_external_controllers = false; auto sched = global_schedule_from_buffers(buffers_opt); @@ -13016,18 +13278,21 @@ void generate_cgra_tb(std::map buffers_opt, prog prg, CodegenOp generate_verilog_tb(prg.name); } -void generate_garnet_coreir(std::map buffers_opt, prog prg, CodegenOptions& opt, schedule_info& hwinfo, bool use_dse_compute=false) { +void generate_garnet_coreir(std::map buffers_opt, prog prg, CodegenOptions& opt, schedule_info& hwinfo, bool use_metamapper, string dse_compute_filename) { CoreIR::Context* context = CoreIR::newContext(); CoreIRLoadLibrary_commonlib(context); CoreIRLoadLibrary_cwlib(context); //schedule_info hwinfo; - hwinfo.use_dse_compute = use_dse_compute; + hwinfo.use_metamapper = use_metamapper; //TODO: add lake memory tile configuration here - auto sched = global_schedule_from_buffers(buffers_opt); - generate_coreir(opt, buffers_opt, prg, sched, hwinfo); - + umap* sched = global_schedule_from_buffers(buffers_opt); + if (use_metamapper) { + generate_coreir_without_ctrl(opt, buffers_opt, prg, sched, hwinfo, dse_compute_filename); + } else { + generate_coreir(opt, buffers_opt, prg, sched, hwinfo); + } //cmd("mv " + prg.name + ".v " + opt.dir + "verilog"); } #endif @@ -14860,28 +15125,76 @@ void Init_PE_energy_cost(power_analysis_params& power_params) { } -void compile_for_garnet_single_port_mem(prog & prg, string dir, bool gen_smt_stream, bool gen_config_only, bool multi_level_mem, bool use_dse_compute, bool energy_model = false); -void compile_for_garnet_fetch2_mem(prog & prg, string dir, bool gen_smt_stream, bool gen_config_only, bool multi_level_mem, bool use_dse_compute, bool energy_model = false); +void compile_for_garnet_single_port_mem(prog & prg, string dir, bool gen_smt_stream, bool gen_config_only,bool multi_level_mem, bool use_metamapper, string dse_compute_filename, bool energy_model = false); +void compile_for_garnet_fetch2_mem(prog & prg, string dir, bool gen_smt_stream, bool gen_config_only, bool multi_level_mem, bool use_metampper, bool energy_model = false); +void compile_for_garnet_dual_port_mem(prog& prg, + string dir, + bool gen_smt_stream, + bool config_gen_only, + bool multi_level_mem, + bool use_metamapper, + string dse_compute_filename, + bool energy_model =false); void cpy_app_to_folder(const std::string& app_type, const std::string& prg_name); void generate_resnet_latency_experiment(prog& prg, ofstream& profiling_file, string dir, - bool use_dse_compute = false); + bool use_metamapper = false); + +void verilator_regression_test(prog& prg, vector& collateral_files, string app_type) { + + string name = prg.name; + auto cpu = unoptimized_result(prg); + vector verilog_files;// = get_files("./" + dir + "/"+name+"/verilog/"); + verilog_files.push_back(name + ".v"); + for (auto file: collateral_files) { + verilog_files.push_back(file); + } + //verilog_files.push_back("laketop_new.sv"); + //verilog_files.push_back("LakeTop_flat.v"); + //verilog_files.push_back("lake_module_wrappers.v"); + //cmd("mv laketop_new.sv laketop.sv"); + bool extra_flag_for_lake = true; + int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); + assert(res == 0); + //cmd("rm LakeTop_W_new.v"); + //cmd("rm LakeWrapper.v"); + //cmd("rm lake_module_wrappers.v"); + //cmd("rm laketop_new.sv"); + //cmd("rm LakeTop_flat.v"); + for (auto file: collateral_files) { + cmd("rm " + file); + } + + auto verilator_res = verilator_results(prg.name); + compare("cgra_" + prg.name + "_cpu_vs_verilog_comparison", verilator_res, cpu); + //string app_type = "dualwithaddr"; + //string app_type = "single_port_buffer"; + cpy_app_to_folder(app_type, prg.name); +} void test_pond(string dir, bool run_verilator=true) { vector test_apps; //Need to change the schedule for vectorization //test_apps.push_back(complex_mem_pond_input()); - test_apps.push_back(complex_mem_pond()); - test_apps.push_back(complex_mem_pond_rolled()); - test_apps.push_back(conv_rolled()); - test_apps.push_back(conv_1_3()); + //fp app need pond for accumulation buffer + //test_apps.push_back(nlmeans_rolled_7x7()); + + //test_apps.push_back(nlmeans_simple_blur()); + test_apps.push_back(nlmeans_simple()); test_apps.push_back(resnet_simple()); test_apps.push_back(resnet()); test_apps.push_back(three_level_pond_copy()); test_apps.push_back(three_level_pond_rolled()); - test_apps.push_back(fft8_unroll8_split()); + test_apps.push_back(conv_1_3()); + test_apps.push_back(conv_rolled()); + test_apps.push_back(complex_mem_pond_rolled()); + test_apps.push_back(complex_mem_pond()); + test_apps.push_back(resnet_init_unroll_tile()); + + //TODO:Currently not work because of floating point, also need to check the cyclic banking condition + //test_apps.push_back(fft8_unroll8_split()); //TODO: tobe tested with new pond //test_apps.push_back(three_level_pond()); @@ -14893,7 +15206,7 @@ void test_pond(string dir, bool run_verilator=true) { break_up_multi_channel_inputs(prg); break_up_multi_channel_outputs(prg); - dsa_writers(prg); + dsa_writers_new(prg); prg.pretty_print(); bool gen_config_only = !run_verilator; @@ -14902,7 +15215,9 @@ void test_pond(string dir, bool run_verilator=true) { false, /*generate smt stream*/ gen_config_only,/*gen_config_only*/ true, /*multi level hierarchy*/ - false/*use dse compute*/); + false, /*for metamapper*/ + "", + false); //generate_regression_testbench(prg); cout << "Output name: " << prg.name << endl; @@ -14910,26 +15225,15 @@ void test_pond(string dir, bool run_verilator=true) { //TODO: move to a function //run verilator on all the generated verilog if (!gen_config_only) { - auto cpu = unoptimized_result(prg); - string name = prg.name; - auto verilog_files = get_files("./" + dir + "/"+name+"/verilog/"); - verilog_files.push_back(name + ".v"); - verilog_files.push_back("Pond_W.v"); - verilog_files.push_back("LakeTop_W_new.v"); - add_default_initial_block(); - bool extra_flag_for_lake = true; - int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); - assert(res == 0); - cmd("rm LakeWrapper.v"); - cmd("rm Pond_W.v"); - cmd("rm LakeTop_W_new.v"); - cmd("rm -rf ./" + dir + "/" + name + "/verilog/"); - - auto verilator_res = verilator_results(prg.name); - compare("cgra_" + prg.name + "_cpu_vs_verilog_comparison", verilator_res, cpu); - //string app_type = "dualwithaddr"; - string app_type = "single_port_buffer"; - cpy_app_to_folder(app_type, prg.name); + vector verilog_files; + verilog_files.push_back("LakeTop_flat.v"); + verilog_files.push_back("laketop_new.sv"); + verilog_files.push_back("PondTop_flat.v"); + verilog_files.push_back("pondtop.sv"); + verilog_files.push_back("pond_module_wrappers.v"); + verilog_files.push_back("lake_module_wrappers.v"); + add_default_initial_block("laketop", "endmodule // sram_sp__0"); + verilator_regression_test(prg, verilog_files, "single_port_buffer"); } #endif @@ -14956,7 +15260,7 @@ void test_energy_model(string dir) { auto cpu = unoptimized_result(prg); //compile_for_garnet_platonic_mem(prg); - compile_for_garnet_single_port_mem(prg, dir, false, gen_config_only, false, false, true); + compile_for_garnet_single_port_mem(prg, dir, false, gen_config_only, false, false, "", true); generate_regression_testbench(prg); cout << "Output name: " << prg.name << endl; @@ -15075,8 +15379,18 @@ void resnet_profiling() { void test_glb(bool gen_config_only, bool multi_accessor=false, string dir="aha_garnet_design") { vector test_apps; + + //camera pipeline variant tests + test_apps.push_back(camera_pipeline_2x2_unroll()); + //Still not work need to add a fanin pass support delay row buffer + //test_apps.push_back(camera_pipeline_extra_buf_glb()); + test_apps.push_back(camera_pipeline_extra_buf()); + test_apps.push_back(camera_pipeline_unrolly()); + test_apps.push_back(camera_pipeline_2x2()); + //ISSCC application without unroll test_apps.push_back(harris_color()); + test_apps.push_back(harris_color_unroll4()); test_apps.push_back(gaussian_isscc()); test_apps.push_back(camera_pipeline_isscc()); test_apps.push_back(unsharp_isscc()); @@ -15100,8 +15414,13 @@ void test_glb(bool gen_config_only, bool multi_accessor=false, string dir="aha_g //test_apps.push_back(resnet5_1_full()); //test_apps.push_back(resnet2_x_full()); - ////Sample DNN Layers + //For debug the 7x7 layer + test_apps.push_back(resnet_last()); + + //Sample DNN Layers + //test_apps.push_back(resnet1_docker()); test_apps.push_back(resnet1()); + test_apps.push_back(resnet_1x1()); test_apps.push_back(resnet3_1()); test_apps.push_back(resnet4_x()); test_apps.push_back(resnet5_1()); @@ -15109,11 +15428,17 @@ void test_glb(bool gen_config_only, bool multi_accessor=false, string dir="aha_g test_apps.push_back(resnet5_x_new()); test_apps.push_back(resnet5_1_new()); test_apps.push_back(resnet5_1_unroll()); - test_apps.push_back(resnet_multi_channel()); + test_apps.push_back(resnet5_1_unroll_cyclic()); + test_apps.push_back(resnet5_glb_unroll()); + //test_apps.push_back(resnet_multi_channel()); + + //two different resnet5x tests + test_apps.push_back(resnet5_x_unroll()); + test_apps.push_back(resnet5_x_unroll_mic()); - ////Test with non double buffer, not tested with db - //test_apps.push_back(resnet_output_stationary_small()); - //test_apps.push_back(resnet_output_stationary_tiny()); + //Test with non double buffer, not tested with db + test_apps.push_back(resnet_output_stationary_small()); + test_apps.push_back(resnet_output_stationary_tiny()); for ( auto prg: test_apps) { prg.sanity_check(); @@ -15125,28 +15450,17 @@ void test_glb(bool gen_config_only, bool multi_accessor=false, string dir="aha_g #ifdef COREIR //compile_for_garnet_platonic_mem(prg); - compile_for_garnet_single_port_mem(prg, dir, false, gen_config_only, false, false); + compile_for_garnet_single_port_mem(prg, dir, false, gen_config_only, false, false, "", false); cout << "Output name: " << prg.name << endl; //TODO: move to a function //run verilator on all the generated verilog if (!gen_config_only) { - string name = prg.name; - auto verilog_files = get_files("./" + dir + "/"+name+"/verilog/"); - verilog_files.push_back(name + ".v"); - verilog_files.push_back("LakeTop_W_new.v"); - add_default_initial_block(); - bool extra_flag_for_lake = true; - auto cpu = unoptimized_result(prg); - int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); - assert(res == 0); - cmd("rm LakeTop_W_new.v"); - cmd("rm LakeWrapper.v"); - - auto verilator_res = verilator_results(prg.name); - compare("cgra_" + prg.name + "_cpu_vs_verilog_comparison", verilator_res, cpu); - //string app_typssive "dualwithaddr"; - string app_type = "single_port_buffer"; - cpy_app_to_folder(app_type, prg.name); + vector verilog_files;// = get_files("./" + dir + "/"+name+"/verilog/"); + verilog_files.push_back("laketop_new.sv"); + verilog_files.push_back("LakeTop_flat.v"); + verilog_files.push_back("lake_module_wrappers.v"); + add_default_initial_block("laketop", "endmodule // sram_sp__0"); + verilator_regression_test(prg, verilog_files, "single_port_buffer"); } #endif } @@ -15157,29 +15471,39 @@ void test_single_port_mem(bool gen_config_only, bool multi_accessor=false, strin //TODO:has issue with multiple input //test_apps.push_back(demosaic_complex()); //test_apps.push_back(fft8_unroll8()); - //test_apps.push_back(camera_pipeline_trunc()); + // + ////fp apps + //test_apps.push_back(nlmeans_unroll_reorder()); + //test_apps.push_back(nlmeans_simple_trunc()); + //test_apps.push_back(fp_pointwise()); + //test_apps.push_back(fp_arith()); + //test_apps.push_back(camera_pipeline_2x2_unroll()); //CGRA tests + test_apps.push_back(nlmeans_simple_trunc()); test_apps.push_back(conv_3_3()); - test_apps.push_back(matmul_single()); test_apps.push_back(counter()); - test_apps.push_back(camera_pipeline_new()); test_apps.push_back(rom()); + test_apps.push_back(camera_pipeline_new()); test_apps.push_back(unsharp_new()); - test_apps.push_back(laplacian_pyramid()); - test_apps.push_back(laplacian_pyramid_docker()); + test_apps.push_back(unsharp_large()); + test_apps.push_back(unsharp()); test_apps.push_back(gaussian()); - test_apps.push_back(down_sample()); test_apps.push_back(cascade()); test_apps.push_back(harris()); test_apps.push_back(conv_1_2()); test_apps.push_back(demosaic_unrolled()); + test_apps.push_back(down_sample()); test_apps.push_back(up_sample()); - test_apps.push_back(unsharp()); + test_apps.push_back(laplacian_pyramid()); + test_apps.push_back(laplacian_pyramid_docker()); //DNN apps test_apps.push_back(resnet_tiny()); test_apps.push_back(resnet_simple()); + test_apps.push_back(matmul_single()); + test_apps.push_back(matmul_unroll2()); + test_apps.push_back(resnet_size_test()); test_apps.push_back(resnet()); //Big applications @@ -15202,55 +15526,115 @@ void test_single_port_mem(bool gen_config_only, bool multi_accessor=false, strin break_up_multi_channel_inputs(prg); break_up_multi_channel_outputs(prg); - dsa_writers(prg); + dsa_writers_new(prg); prg.pretty_print(); #ifdef COREIR //compile_for_garnet_platonic_mem(prg); - compile_for_garnet_single_port_mem(prg, dir, false, gen_config_only, false, false); + compile_for_garnet_single_port_mem(prg, dir, false, gen_config_only, false, false, "", false); cout << "Output name: " << prg.name << endl; - //TODO: move to a function //run verilator on all the generated verilog if (!gen_config_only) { - string name = prg.name; - auto verilog_files = get_files("./" + dir + "/"+name+"/verilog/"); - verilog_files.push_back(name + ".v"); - verilog_files.push_back("LakeTop_W_new.v"); - add_default_initial_block(); - bool extra_flag_for_lake = true; - auto cpu = unoptimized_result(prg); - int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); - assert(res == 0); - cmd("rm LakeTop_W_new.v"); - cmd("rm LakeWrapper.v"); - - auto verilator_res = verilator_results(prg.name); - compare("cgra_" + prg.name + "_cpu_vs_verilog_comparison", verilator_res, cpu); - //string app_type = "dualwithaddr"; - string app_type = "single_port_buffer"; - cpy_app_to_folder(app_type, prg.name); + vector verilog_files;; + verilog_files.push_back("laketop_new.sv"); + verilog_files.push_back("LakeTop_flat.v"); + verilog_files.push_back("lake_module_wrappers.v"); + add_default_initial_block("laketop", "endmodule // sram_sp__0"); + verilator_regression_test(prg, verilog_files, "single_port_buffer"); } #endif } } -void generate_smt_stream_for_garnet_single_port_mem(prog& prg); -void test_single_port_mem_smt_stream() { +void test_dual_port_mem(bool gen_config_only, bool multi_accessor=false, string dir="aha_garnet_dp") { vector test_apps; - //test_apps.push_back(conv_3_3(28, 28, "_SMT_28_28")); - //test_apps.push_back(cascade(28, 28, "_SMT_28_28")); - test_apps.push_back(harris(14, 14, "_SMT_16_16")); - - for ( auto prg: test_apps) { - cout << "====== Running CGRA Single Port test for " << prg.name << endl; - prg.pretty_print(); - prg.sanity_check(); - - dsa_writers(prg); - prg.pretty_print(); - - generate_smt_stream_for_garnet_single_port_mem(prg); - cout << "Output name: " << prg.name << endl; + //CGRA tests that pass dual port test + //test_apps.push_back(matmul()); + test_apps.push_back(camera_pipeline_2x2()); + test_apps.push_back(unsharp_large()); + test_apps.push_back(harris_color()); + test_apps.push_back(conv_3_3()); + test_apps.push_back(gaussian()); + test_apps.push_back(cascade()); + test_apps.push_back(harris()); + test_apps.push_back(down_sample()); + test_apps.push_back(unsharp()); + test_apps.push_back(unsharp_new()); + test_apps.push_back(counter()); + test_apps.push_back(rom()); + test_apps.push_back(conv_1_2()); + test_apps.push_back(demosaic_unrolled()); + test_apps.push_back(up_sample()); + test_apps.push_back(camera_pipeline_new()); + test_apps.push_back(resnet88()); + test_apps.push_back(laplacian_pyramid_docker()); + test_apps.push_back(laplacian_pyramid()); + + //////DNN apps + ////Not working + ////test_apps.push_back(matmul_single()); + + //test_apps.push_back(resnet_tiny()); + //test_apps.push_back(resnet_simple()); + //test_apps.push_back(resnet()); + + //////Big applications + //test_apps.push_back(mobilenet_unrolled()); + //test_apps.push_back(resnet_one_input()); + //test_apps.push_back(resnet88()); + //test_apps.push_back(resnet88_chain()); + + //test_apps.push_back(resnet_coarse_pipeline_loop()); + + //coarse grained pipeline + //test_apps.push_back(resnet_coarse_pipeline_loop()); + + //test_apps.push_back(conv_3_3_wide()); + //TODO: break in the middle of vectorization + //test_apps.push_back(down_sample()); + + for ( auto prg: test_apps) { + prg.sanity_check(); + + break_up_multi_channel_inputs(prg); + break_up_multi_channel_outputs(prg); + dsa_writers(prg); + prg.pretty_print(); +#ifdef COREIR + //compile_for_garnet_platonic_mem(prg); + compile_for_garnet_dual_port_mem(prg, dir, false, gen_config_only, false, false, "", false); + cout << "Output name: " << prg.name << endl; + //run verilator on all the generated verilog + if (!gen_config_only) { + vector verilog_files;; + verilog_files.push_back("PondTop_flat.v"); + verilog_files.push_back("pondtop_new.sv"); + verilog_files.push_back("pond_module_wrappers.v"); + add_default_initial_block("pondtop", "endmodule // sram_dp__0"); + verilator_regression_test(prg, verilog_files, "dual_port_buffer"); + } +#endif + } +} + +void generate_smt_stream_for_garnet_single_port_mem(prog& prg); +void test_single_port_mem_smt_stream() { + vector test_apps; + //test_apps.push_back(conv_3_3(28, 28, "_SMT_28_28")); + //test_apps.push_back(cascade(28, 28, "_SMT_28_28")); + test_apps.push_back(harris(14, 14, "_SMT_16_16")); + + for ( auto prg: test_apps) { + cout << "====== Running CGRA Single Port test for " << prg.name << endl; + prg.pretty_print(); + prg.sanity_check(); + + dsa_writers(prg); + prg.pretty_print(); + + generate_smt_stream_for_garnet_single_port_mem(prg); + + cout << "Output name: " << prg.name << endl; } } @@ -17151,11 +17535,12 @@ void lake_smt_tests() { void access_pattern_read_unit_tests() { isl_ctx* ctx = isl_ctx_alloc(); + int dummy_dim; auto acc_0 = isl_map_read_from_str(ctx,"{ op[i0]-> data[i0]: 0<=i0<=61}"); auto sched = isl_map_read_from_str(ctx,"{ op[i0]-> [i0]: 0<=i0<=61 }"); //auto read_ir = get_vectorized_read(acc_0, sched, {}, 4, 0); - auto read_ir = get_vectorized_read_simplified(acc_0, sched, {}, 4, 0); + auto read_ir = get_vectorized_read_simplified(acc_0, sched, {}, 4, 0, dummy_dim); auto acc_vec = read_ir.first; auto sched_vec = read_ir.second; cout << "After vec read access map: " << str(simplify_expr(acc_vec)) << endl; @@ -17169,7 +17554,7 @@ void access_pattern_read_unit_tests() { auto sched_write = isl_map_read_from_str(ctx,"{ op_write[i0]-> [4 + 4*i0]: 0<=i0<=15 }"); //read_ir = get_vectorized_read(acc_0, sched, read_ir = get_vectorized_read_simplified(acc_0, sched, - {{"sram2tb_0", sched_read}, {"agg2sram_0", sched_write}}, 4, 0); + {{"sram2tb_0", sched_read}, {"agg2sram_0", sched_write}}, 4, 0, dummy_dim); acc_vec = read_ir.first; sched_vec = read_ir.second; cout << "After vec read access map: " << str(acc_vec) << endl; @@ -17183,7 +17568,7 @@ void access_pattern_read_unit_tests() { sched_write = isl_map_read_from_str(ctx,"{ op_write[i0]-> [4 + 4*i0]: 0<=i0<=15 }"); //read_ir = get_vectorized_read(acc_0, sched, read_ir = get_vectorized_read_simplified(acc_0, sched, - {{"sram2tb_0", sched_read}, {"agg2sram_0", sched_write}}, 4, 0); + {{"sram2tb_0", sched_read}, {"agg2sram_0", sched_write}}, 4, 0, dummy_dim); acc_vec = read_ir.first; sched_vec = read_ir.second; cout << "After vec read access map: " << str(acc_vec) << endl; @@ -17195,7 +17580,7 @@ void access_pattern_read_unit_tests() { sched_write = isl_map_read_from_str(ctx,"{ op_write[i0]-> [8 + 8*i0]: 0<=i0<=7 }"); //read_ir = get_vectorized_read(acc_0, sched, read_ir = get_vectorized_read_simplified(acc_0, sched, - {{"agg2sram_0", sched_write}}, 4, 0); + {{"agg2sram_0", sched_write}}, 4, 0, dummy_dim); acc_vec = read_ir.first; sched_vec = read_ir.second; cout << "After vec read access map: " << str(acc_vec) << endl; @@ -17217,7 +17602,7 @@ void access_pattern_read_unit_tests() { acc_0 = isl_map_read_from_str(ctx,"{ sram2tb[root = 0, i0, i2, i1]-> data[i0, i1+i2]: 0<=i0<=61 and 0<=i1<=61 and 0<=i2<=7}"); sched = isl_map_read_from_str(ctx,"{ sram2tb[root = 0, i0, i2, i1]-> [560*i0+ 70*i2+i1]: 0<=i0<=61 and 0<=i1<=61 and 0<=i2<=7}"); - read_ir = get_vectorized_read_simplified(acc_0, sched, {}, 4, 1); + read_ir = get_vectorized_read_simplified(acc_0, sched, {}, 4, 1, dummy_dim); //read_ir = get_vectorized_read(acc_0, sched, {}, 4, 1); acc_vec = read_ir.first; sched_vec = read_ir.second; @@ -17229,7 +17614,7 @@ void access_pattern_read_unit_tests() { acc_0 = isl_map_read_from_str(ctx,"{ op[i0, i1]-> data[i0 + i1]: 0<=i0<8 and 0 <= i1 <= 2}"); sched = isl_map_read_from_str(ctx,"{ op[i0, i1]-> [14 + i0*3 + i1]: 0<=i0<8and 0 <= i1 <= 2 }"); //read_ir = get_vectorized_read(acc_0, sched, {}, 4, 0); - read_ir = get_vectorized_read_simplified(acc_0, sched, {}, 4, 0); + read_ir = get_vectorized_read_simplified(acc_0, sched, {}, 4, 0, dummy_dim); acc_vec = read_ir.first; sched_vec = read_ir.second; cout << "After vec read access map: " << str(simplify_expr(acc_vec)) << endl; @@ -17372,9 +17757,12 @@ void vectorization_unit_tests() { upsample_pad_test(); stride_id_test(); stride_conv_test(); + upsample_2d_unit_test(); + outer_rolled_conv2D_test(); + rolled_conv2D_test(); //FIXME: Did not work need to test after ASPLOS - sw_fetch2_test(); + //sw_fetch2_test(); } void lake_tests() { @@ -17498,6 +17886,48 @@ int get_vectorization_dim(isl_map* m, int fetch_width) { return -1; //need merge or use single pixel vectorization } +void relax_write(schedule_info& sched, op* loop, prog& prg, int fetch_width) { + //only look at loop op + if (!loop->is_loop()) + return; + cout << "op name: " << loop->name << endl; + auto write_map = written_at(loop->name, prg); + auto levels = get_variable_levels(prg); + cout << "op level: " << levels.at(loop->name) << endl; + if(write_map == nullptr) + return; + //Do not pad glb loop + if (contains(loop->name, "glb")) + return; + for (auto wr_map: get_maps(write_map)) { + cout << tab(4) << "write map: \n\t" << str(wr_map) << endl; + auto b_map = to_map(pick(get_basic_maps(wr_map))); + auto write_addr_involve_dim = out_involve_dim(b_map, levels.at(loop->name)); + cout << tab(4) << "addr involve dim: " << write_addr_involve_dim << endl; + + //Chances are that this dimension is fully unrolled + //Involve the vectorization dimension + int vec_dim = get_vectorization_dim(b_map, fetch_width); + if (write_addr_involve_dim.size() > 0 + && (elem(vec_dim, write_addr_involve_dim))) { + assert(write_addr_involve_dim.size() == 1); + int packed_addr_dim = pick(write_addr_involve_dim); + auto in_involve_d = in_involve_dim(b_map, packed_addr_dim); + cout << "\tInvolve in dim: " << in_involve_d << endl; + + //Do not pad if this dimension will be merged + if (loop->trip_count() < fetch_width) { + continue; + } else { + sched.op_offset_within_parent[loop] += (fetch_width - (loop->trip_count() * sched.II(loop)) % fetch_width) % fetch_width; + cout << "\t change loop : " << loop->name << "'s offset to " << sched.op_offset_within_parent.at(loop) << endl; + } + } + //Should only go over one time + return; + } +} + bool need_relax(schedule_info& sched, op* loop, prog& prg, int fetch_width) { //only look at loop op if (!loop->is_loop()) @@ -17556,9 +17986,11 @@ bool need_relax(schedule_info& sched, op* loop, prog& prg, int fetch_width) { //cout << tab(4) << "Original offset within parent: " << sched.offset_in_parent(child) << endl; cout << tab(4) << "Original offset within parent: " << sched.offset_in_parent(loop) << endl; cout << tab(4) << "loop trip count: " << loop->trip_count() << endl; - if (is_inner_loop(loop)) - sched.op_offset_within_parent.at(loop) = (loop->trip_count()) % fetch_width + fetch_width * (loop->trip_count()%fetch_width== 0); - else { + + //This loop is the innermost loop that access the vectorized dimension + if (levels.at(loop->name) == in_involve_d.back()) { + sched.op_offset_within_parent.at(loop) = sched.II(loop) * ((loop->trip_count()) % fetch_width + fetch_width * (loop->trip_count()%fetch_width== 0)); + } else { //int range_span = get_dim_extent(range(b_map), packed_addr_dim); //if (range_span % fetch_width) //TODO: also check the logic here, this is conservative @@ -17606,9 +18038,13 @@ void asap_inner_loops_schedule(schedule_info& sched, op* op, prog& prg, int fetc // //TODO: currently only need to pad read op // relax_inner_delay_for_vec_read(sched, other, prg, fetch_width); //} + relax_write(sched, other, prg, fetch_width); if (need_relax(sched, other, prg, fetch_width)) { cout << tab(4) << other->name << "--> Enter relax condition loop!" << endl; } + //if (other->is_loop()) + // sched.op_offset_within_parent[other] += (fetch_width - + // (other->trip_count() * sched.II(other) % fetch_width)) % fetch_width; latency = sched.total_latency(other) + sched.offset_in_parent(other); //TODO: this offset by 1 is trying to pipeline instead of braodacsting if (old_latency == latency) { @@ -17724,6 +18160,17 @@ void rate_matched_schedule(schedule_info& sched, op* root, prog& prg, const int //adjust_outer_delays(sched, prg); } +//Just test if add delay work +void add_delay_to_op(string op_name, prog& prg, schedule_info& sched) { + for (auto kernel: topologically_sort_kernels(prg)) { + auto lp = prg.find_non_op(kernel); + cout << "\t kernel name: " << lp<< ", delay: " << sched.op_offset_within_parent[lp]<< endl; + if (!contains(kernel, "hw_input")) { + sched.op_offset_within_parent[lp] += 64; + } + } +} + void tighten_iis(schedule_info& sched, prog& prg) { bool tightened = true; while (tightened) { @@ -17772,13 +18219,14 @@ void tighten_coarse_grained_iis(schedule_info& sched, prog& prg) { auto lower_ops = loop->descendants(); bool outside_cgpl = false; for(op* lp: cgpl_lps){ - if(elem(lp, lower_ops)) { + if(elem(lp, lower_ops) && (lp!=loop)) { outside_cgpl = true; break; } } if (!outside_cgpl) continue; + cout << "\tOP: " << loop->name << "is a loop outside cgpl " << endl; int ii = sched.II(loop); if (ii != 1) { int L = sched.doublebuffer_update_delay(loop); @@ -17923,6 +18371,7 @@ void relax_iis_for_vectorization(schedule_info& sched, prog& prg) { } } + void adjust_coarse_grained_loop_delays_sequentially_without_opt(schedule_info& sched, prog& prg) { int d = 0; map coarse_pipeline_II; @@ -17978,6 +18427,40 @@ void adjust_coarse_grained_loop_delays_sequentially_without_opt(schedule_info& s } } +void align_glb_load_start_cycle(schedule_info& sched, prog& prg) { + vector cgpl_lps; + find_coarse_grained_pipeline_loops(prg.root, cgpl_lps, prg); + for (op* coarse_pipeline_loop: cgpl_lps) { + cout << "adjust delay under coarse loop: " + << coarse_pipeline_loop->name << endl; + vector sorted_kernels = topologically_sort_kernels(coarse_pipeline_loop, prg); + vector kernels_to_be_aligned; + for (auto name : sorted_kernels) { + //cout << tab(2) << "II: " << sched.II(lp) << endl; + //cout << tab(2) << "TP: " << (lp)->trip_count() << endl; + auto producers = get_producers(name, coarse_pipeline_loop, prg); + + if (producers.size() == 0) { + kernels_to_be_aligned.push_back(name); + cout << tab(1) << "Push kernel <" << name << "> into GLB alignment list." << endl; + } + } + + + int max_delay = 0; + map delay_map; + for (auto name : kernels_to_be_aligned) { + auto lp = prg.find_non_op(name); + delay_map[name] = sched.starting_delay_to_leaf(lp); + max_delay = max(delay_map.at(name), max_delay); + } + for (auto name : kernels_to_be_aligned) { + auto lp = prg.find_non_op(name); + sched.op_offset_within_parent.at(lp) = - delay_map.at(name); + } + } +} + void adjust_coarse_grained_loop_delays_sequentially(schedule_info& sched, prog& prg) { int d = 0; map coarse_pipeline_II; @@ -18069,10 +18552,87 @@ void dump_DNN_delays(schedule_info& sched, prog& prg, ofstream& out) { out << end-start; } -void adjust_outer_delays_sequentially(schedule_info& sched, prog& prg) { +void adjust_outer_delays_sequentially_with_glb_guard(schedule_info& sched, prog& prg) { + cout << "Adjusting delays of " << prg.name << "After vectorization" << endl; + int d = 0; + int glb_load_latency = 0; + for (auto name : topologically_sort_kernels(prg)) { + auto lp = prg.find_loop(name); + auto prods = get_producers(name, prg); + if (prods.size() == 0 && contains(name, "glb")) { + cout << "\tkernel <" << lp->name << "> is the glb loading kernel." << endl; + cout << "\tname<" << name << endl; + glb_load_latency = std::max(sched.total_latency(lp), glb_load_latency); + } + } + cout << "Find GLB load latency = " << glb_load_latency << endl; + map coarse_pipeline_II; + for (auto name : topologically_sort_kernels(prg)) { + auto lp = prg.find_loop(name); + cout << "Push kernel <" << lp->name << "> into delay adjusting queue." << endl; + cout << "II: " << sched.II(lp) << endl; + cout << "TP: " << (lp)->trip_count() << endl; + for (auto prod: get_producers(name, prg)) + cout << "\tprod: " << prod << endl; + //This only works for the schedule without pipeline should change into total latency + //coarse_pipeline_II[name] = sched.II(lp) * lp->trip_count(); + coarse_pipeline_II[name] = sched.total_latency(lp); + sched.op_offset_within_parent[lp] = 0; + } + for (auto name : topologically_sort_kernels(prg)) { + auto lp = prg.find_loop(name); + cout << "Adjusting delay of " << lp->name << endl; + cout << "II: " << sched.II(lp) << endl; + int max_delay = 0; + for (string prod: get_producers(name, prg)){ + op* prod_op = prg.find_loop(prod); + max_delay = max(coarse_pipeline_II.at(prod) + + sched.op_offset_within_parent.at(prod_op), max_delay); + } + //FIXME: Hack for glb latency sync nothing can start before glb transfer + if (!contains(name, "glb")) { + max_delay = max(glb_load_latency, max_delay); + } + + sched.op_offset_within_parent.at(lp) = max_delay; + cout << "final delay of " << lp->name << + ": \n\t"<< max_delay << endl; + } +} + +int find_glb_load_latency(schedule_info& sched, prog& prg) { + int glb_load_latency = 0; + for (auto name : topologically_sort_kernels(prg)) { + auto lp = prg.find_loop(name); + auto prods = get_producers(name, prg); + if (prods.size() == 0 && contains(name, "glb")) { + cout << "\tkernel <" << lp->name << "> is the glb loading kernel." << endl; + cout << "\tname<" << name << endl; + glb_load_latency = std::max(sched.total_latency(lp), glb_load_latency); + } + } + cout << "Find GLB load latency = " << glb_load_latency << endl; + return glb_load_latency; +} + + +void adjust_outer_delays_sequentially(schedule_info& sched, prog& prg, bool glb_sync = true) { cout << "Adjusting delays of " << prg.name << "After vectorization" << endl; int d = 0; map coarse_pipeline_II; + int glb_load_latency = 0; + if (glb_sync) { + for (auto name : topologically_sort_kernels(prg)) { + auto lp = prg.find_loop(name); + auto prods = get_producers(name, prg); + if (prods.size() == 0 && contains(name, "glb")) { + cout << "\tkernel <" << lp->name << "> is the glb loading kernel." << endl; + cout << "\tname<" << name << endl; + glb_load_latency = std::max(sched.total_latency(lp), glb_load_latency); + } + } + cout << "Find GLB load latency = " << glb_load_latency << endl; + } for (auto name : topologically_sort_kernels(prg)) { auto lp = prg.find_loop(name); cout << "Push kernel <" << lp->name << "> into delay adjusting queue." << endl; @@ -18095,6 +18655,12 @@ void adjust_outer_delays_sequentially(schedule_info& sched, prog& prg) { max_delay = max(coarse_pipeline_II.at(prod) + sched.op_offset_within_parent.at(prod_op), max_delay); } + //FIXME: Hack for glb latency sync nothing can start before glb transfer + if (glb_sync) { + if (!contains(name, "glb")) { + max_delay = max(glb_load_latency, max_delay); + } + } sched.op_offset_within_parent.at(lp) = max_delay; cout << "final delay of " << lp->name << @@ -18154,6 +18720,8 @@ void relax_delays_rate_matched(CodegenOptions& options, schedule_info& sched, pr cout << "Adjusting delays of " << prg.name << endl; map delay_relaxation; int fetch_width = options.mem_hierarchy.at("mem").fetch_width; + if (fetch_width == 1) + return; auto start_times = its(op_times_map(sched, prg), prg.whole_iteration_domain()); auto start_times_map = get_maps_in_map(start_times); auto domains = prg.domains(); @@ -18169,6 +18737,7 @@ void relax_delays_rate_matched(CodegenOptions& options, schedule_info& sched, pr continue; } cout << "read map: " << str(kernel_read_map) << endl; + string dsa_writer; for (auto cons_op: cons_op_vec) { for(auto prod: get_producers(name, prg)){ auto prod_loop = prg.find_loop(prod); @@ -18204,6 +18773,9 @@ void relax_delays_rate_matched(CodegenOptions& options, schedule_info& sched, pr need_relax = true; } } + if (contains(pick(prod_op->buffers_written()), "clkwrk_dsa")) { + dsa_writer = prod; + } cout << tab(2) << "Producers: " << prod_op_name << endl; cout << tab(2) << "sched: " << str(prod_sched) << endl; @@ -18218,18 +18790,29 @@ void relax_delays_rate_matched(CodegenOptions& options, schedule_info& sched, pr bool prod_need_index = pick(cons_op_vec)->index_variables_needed_by_compute.size(); int offset = 0; if (need_relax) { + //change into current op ii int prod_ii = sched.II(prod_op->parent); + int cons_ii = sched.II(cons_op->parent); //Relaxation recipe input/output - offset = prod_ii * fetch_width * 2; + offset = std::max(cons_ii, prod_ii) * fetch_width * 2; } else if (equal_start_time && prod_need_index && (cons_start_time < 3)) { offset = 3 - cons_start_time; } - //get the max delay relaxation from all producer - delay_max = max(delay_max, delay_relaxation.at(prod) + offset); + //get the max delay relaxation from all producer, + //topographical sort can have close area, AKA all connected + if (delay_relaxation.count(prod)) + delay_max = max(delay_max, delay_relaxation.at(prod) + offset); } // for each producer op } //for each producer kernel } //for each consumer op delay_relaxation.at(name) = delay_max; + + //For dsa writer kernel add the delay + //Since topological sort may put the init kernel in beginning + if (!dsa_writer.empty()) { + sched.op_offset_within_parent[prg.find_loop(dsa_writer)] += delay_max; + } + sched.op_offset_within_parent[lp] += delay_max; cout << "Kernel <" << name << "> has Delay slack: " << delay_max << endl; cout << "Offset with in parent: " << sched.op_offset_within_parent.at(lp) << endl; @@ -18627,9 +19210,11 @@ void dump_resnet_latency(CodegenOptions& options, schedule_info& sched, op* root } else if(options.fallback_schedule == ISCA_SCHEDULE) { coarse_grained_pipeline_optimization(sched, prg); adjust_coarse_grained_loop_delays_sequentially_without_opt(sched, prg); + align_glb_load_start_cycle(sched, prg); tighten_coarse_grained_iis(sched, prg); adjust_outer_delays_sequentially(sched, prg); + } else if (options.fallback_schedule == SEQUENTIAL_SCHEDULE){ //adjust_outer_delays(sched, prg); adjust_outer_delays_sequentially(sched, prg); @@ -18641,7 +19226,7 @@ void dump_resnet_latency(CodegenOptions& options, schedule_info& sched, op* root cout << "\tFinal schedule : " << str(op_sched) << endl; adjust_schedule_forward(sched, prg, 0); - sanity_check_hw_schedule(sched, prg); + sanity_check_hw_schedule(sched, prg);; return; } @@ -18652,9 +19237,11 @@ void garnet_single_port_ram_schedule(CodegenOptions& options, schedule_info& sch //An hack on the fft schedule sequential_schedule(sched, root, prg); return; - } else if (is_rate_matchable(prg)) { + } else if (is_rate_matchable(prg) || contains(prg.name, "nlmeans")) { prg.pretty_print(); - + halide_check_rate_mismatch("", {16, 16}, 4, prg); + loop_split(prg); + prg.sanity_check(); //TODO: need another function to choose between pad bottom level or top level //pad_bottom_level_ops_with_loops(prg); pad_to_single_depth(sched, root, prg); @@ -18740,7 +19327,7 @@ void garnet_single_port_ram_schedule(CodegenOptions& options, schedule_info& sch // //total_latency += op_latency(op, sched) + 2; // total_latency += op_latency(op, sched); //} - int total_latency = 0; + vector scheduled; for (auto op : inner_ops(prg)) { cout << "inner ops: " << op->name << endl; @@ -18767,23 +19354,27 @@ void garnet_single_port_ram_schedule(CodegenOptions& options, schedule_info& sch //total_latency += op_latency(op, sched); scheduled.push_back(op); } + //auto init_op_sched = op_start_times_map(sched, prg); + //cout << "init sched: " << str(init_op_sched) << endl; + //for (auto it: sched.op_offset_within_parent) { + // cout << "\t" << it.first->name << ": " << it.second << endl; + //} + //assert(false); - //Hack for rom, Rom need to be conservative - //because the affine controller output on cycle of flush is undeterministic - //if (prg.name == "rom" ) { - //adjust_schedule_forward(sched, prg, 1); - //} else { + auto op_sched = op_start_times_map(sched, prg); + cout << "orginal schedule before relax: " << str(op_sched) << endl; adjust_schedule_forward(sched, prg, 0); - //} + //Add delay for identity stream relax_delays_rate_matched(options, sched, prg); //Make input as fast as possible asap_input_iis(sched, prg); - auto op_sched = op_start_times_map(sched, prg); + op_sched = op_start_times_map(sched, prg); cout << "Final schedule after relax: " << str(op_sched) << endl; op_sched = op_end_times_map(sched, prg); cout << "Final end schedule after relax: " << str(op_sched) << endl; + sanity_check_hw_schedule(sched, prg); return; } else if (contains(prg.name, "split")) { sequential_schedule(sched, root, prg); @@ -18802,48 +19393,59 @@ void garnet_single_port_ram_schedule(CodegenOptions& options, schedule_info& sch //} //assert(false); - /* - * old method for ISCA deadline*/ - asap_inner_loops_schedule(sched, root, prg, - options.mem_hierarchy.at("mem").fetch_width); - //sequential_schedule(sched, root, prg); - - adjust_inner_iis(sched, prg); - tighten_iis(sched, prg); - - //only adjust coarse grained ii while optimize double buffer - if (options.fallback_schedule == ASPLOS_SCHEDULE) { - adjust_coarse_grained_loop_iis(sched, prg); - adjust_coarse_grained_loop_delays_sequentially(sched, prg); - tighten_coarse_grained_iis(sched, prg); - //adjust_outer_delays_sequentially_cgpl(sched, prg); - adjust_outer_delays_sequentially(sched, prg); - } else if(options.fallback_schedule == VANILLA_DB_SCHEDULE) { - coarse_grained_pipeline_optimization(sched, prg); - adjust_coarse_grained_loop_delays_sequentially_without_opt(sched, prg); - adjust_outer_delays_sequentially(sched, prg); - - } else if(options.fallback_schedule == ISCA_SCHEDULE) { - coarse_grained_pipeline_optimization(sched, prg); - adjust_coarse_grained_loop_delays_sequentially_without_opt(sched, prg); - tighten_coarse_grained_iis(sched, prg); - adjust_outer_delays_sequentially(sched, prg); - - } else if (options.fallback_schedule == SEQUENTIAL_SCHEDULE){ - //adjust_outer_delays(sched, prg); - adjust_outer_delays_sequentially(sched, prg); - } + do { + options.rtl_options.double_buffer_optimization = options.fallback_schedule < 3; + /* + * old method for ISCA deadline*/ + asap_inner_loops_schedule(sched, root, prg, + options.mem_hierarchy.at("mem").fetch_width); + //sequential_schedule(sched, root, prg); + + adjust_inner_iis(sched, prg); + tighten_iis(sched, prg); + + //only adjust coarse grained ii while optimize double buffer + if (options.fallback_schedule == ASPLOS_SCHEDULE) { + adjust_coarse_grained_loop_iis(sched, prg); + adjust_coarse_grained_loop_delays_sequentially(sched, prg); + tighten_coarse_grained_iis(sched, prg); + //adjust_outer_delays_sequentially_cgpl(sched, prg); + adjust_outer_delays_sequentially(sched, prg); + } else if(options.fallback_schedule == VANILLA_DB_SCHEDULE) { + coarse_grained_pipeline_optimization(sched, prg); + adjust_coarse_grained_loop_delays_sequentially_without_opt(sched, prg); + adjust_outer_delays_sequentially(sched, prg); + + } else if(options.fallback_schedule == ISCA_SCHEDULE) { + coarse_grained_pipeline_optimization(sched, prg); + adjust_coarse_grained_loop_delays_sequentially_without_opt(sched, prg); + align_glb_load_start_cycle(sched, prg); + tighten_coarse_grained_iis(sched, prg); + adjust_outer_delays_sequentially(sched, prg); + //int glb_load_latency = find_glb_load_latency(sched, prg); + //adjust_outer_delays_exhaustively(sched, prg, glb_load_latency); + + } else if (options.fallback_schedule == SEQUENTIAL_SCHEDULE){ + //adjust_outer_delays(sched, prg); + adjust_outer_delays_sequentially(sched, prg); + } else { + cout << "No schedule works..." << endl; + assert(false); + } + //change to the fallback schedule + options.fallback_schedule = DNNScheduleAlgorithm(options.fallback_schedule + 1); + cout << " Fall back schedule No. " << options.fallback_schedule << endl; + } while (!no_violated_buf_write_port_assignments(options, sched, prg)); //dump_DNN_delays(sched, prg); auto op_sched = op_start_times_map(sched, prg); cout << "\tFinal schedule : " << str(op_sched) << endl; + assert(no_violated_buf_write_port_assignments(options, sched, prg)); adjust_schedule_forward(sched, prg, 0); sanity_check_hw_schedule(sched, prg); return; } - - void pad_to_single_depth(schedule_info& sched, op* root, prog& prg) { bool single_depth = all_loop_nests_same_depth(prg); int max_depth = max_loop_depth(prg); @@ -18868,21 +19470,53 @@ void pad_to_single_depth(schedule_info& sched, op* root, prog& prg) { //prg.pretty_print(); //assert(false); - map > pad_indexes; + //First pass to collect all the deepest loops loop bound + vector depth_record(max_depth - 1, 0); + int div_factor = 0; for (auto k : get_kernels(prg)) { auto lp = prg.find_loop(k); for (auto rep : lp->descendant_ops()) { int depth_m = loop_depth(prg.find_loop(k)); - vector inds; - inds.push_back(0); - for (int p = 0; p < max_depth - depth_m; p++) { - inds.push_back(-1); + if (depth_m == max_depth - 1) { + auto vec = loop_depth_vector(lp); + for (int i = 0; i < max_depth - 1; i++ ) { + depth_record.at(i) += vec.at(i); + } + div_factor ++; + cout << " op: " << rep->name << endl; + cout << tab(2) << loop_depth_vector(lp) << endl; } - for (int d = 1; d < depth_m + 1; d++) { - inds.push_back(d); + } + } + for (auto & it: depth_record) { + it /= div_factor; + } + cout << "Final depth vec: " << depth_record << endl; + + //next pass to get all the other loops' pad level + map > pad_indexes; + for (auto k : get_kernels(prg)) { + auto lp = prg.find_loop(k); + for (auto rep : lp->descendant_ops()) { + int depth_m = loop_depth(prg.find_loop(k)); + if (depth_m < max_depth - 1) { + auto vec = loop_depth_vector(lp); + vector inds = get_alignment_array(depth_record, vec); + pad_indexes[rep->name] = inds; + } else { + vector inds; + inds.push_back(0); + for (int d = 1; d < depth_m + 1; d++) { + inds.push_back(d); + } + pad_indexes[rep->name] = inds; } - pad_indexes[rep->name] = inds; + //Pad the inner loop + //for (int p = 0; p < max_depth - depth_m - 1; p++) { + // inds.push_back(-1); + //} + } } cout << "Pad inds..." << endl; @@ -19086,6 +19720,7 @@ void garnet_dual_port_ram_schedule(schedule_info& sched, op* root, prog& prg) { buffer_dims.insert(logical_dimension(b, prg)); } + //TODO fix this scheduler if (buffer_dims.size() > 1) { coarse_pipeline_schedule(sched, root, prg); } else { @@ -19099,9 +19734,54 @@ void garnet_dual_port_ram_schedule(schedule_info& sched, op* root, prog& prg) { sanity_check_iis(sched); } -schedule_info garnet_schedule_info(CodegenOptions& options, prog& prg, bool use_dse_compute=false) { +schedule_info garnet_schedule_info(CodegenOptions& options, prog& prg, bool use_metamapper=false, string dse_compute_filename="") { schedule_info sched; - sched.use_dse_compute = use_dse_compute; + sched.use_metamapper = use_metamapper; + sched.dse_compute_filename = dse_compute_filename; + + if (use_metamapper) { + json kernel_latencies; + std::ifstream kernel_latencies_file(prg.name + "_compute_kernel_latencies.json", std::ifstream::binary); + kernel_latencies_file >> kernel_latencies; + + for (auto op : prg.all_ops()) { + if (op->func != "") { + sched.resource_requirements[op] = op->func; + } + cout << op->func << endl; + if (kernel_latencies[op->func] == NULL || kernel_latencies[op->func] == "null") { + sched.compute_unit_latencies[op->func] = 0; + } else { + sched.compute_unit_latencies[op->func] = kernel_latencies[op->func]; + cout << "KERNEL LATENCY " << op->func << " : " << kernel_latencies[op->func] << endl; + } + + + for (auto b: op->buffers_written()) { + //assign a write + sched.assign_memory_write_resource(options, op, b); + } + + + for (auto b : op->buffers_referenced()) { + if (!prg.is_boundary(b)) { + sched.buffer_load_latencies[b] = buffer_load_latency(options); + sched.buffer_store_latencies[b] = buffer_store_latency(options); + } else { + sched.buffer_load_latencies[b] = 0; + sched.buffer_store_latencies[b] = 0; + } + auto pmap = prg.producer_map(b); + cout << "\tBuffer <" << b << "> \n\tproducer map: "<< str(pmap) + << "\n\tcapacity: " << logical_capacity(b, prg) << endl << + "\thierarchy level: " << options.get_hierarchy_level(logical_capacity(b, prg)) << endl; + sched.buf2level[b] = options.get_hierarchy_level(logical_capacity(b, prg)); + + } + } + cout << sched.compute_unit_latencies << endl; + } else { + for (auto op : prg.all_ops()) { if (op->func != "") { sched.resource_requirements[op] = op->func; @@ -19114,6 +19794,11 @@ schedule_info garnet_schedule_info(CodegenOptions& options, prog& prg, bool use_ //sched.op_compute_unit_latencies[op->name] = 0; } + for (auto b: op->buffers_written()) { + //assign a write + sched.assign_memory_write_resource(options, op, b); + } + for (auto b : op->buffers_referenced()) { if (!prg.is_boundary(b)) { sched.buffer_load_latencies[b] = buffer_load_latency(options); @@ -19122,8 +19807,14 @@ schedule_info garnet_schedule_info(CodegenOptions& options, prog& prg, bool use_ sched.buffer_load_latencies[b] = 0; sched.buffer_store_latencies[b] = 0; } + auto pmap = prg.producer_map(b); + cout << "\tBuffer <" << b << "> \n\tproducer map: "<< str(pmap) + << "\n\tcapacity: " << logical_capacity(b, prg) << endl << + "\thierarchy level: " << options.get_hierarchy_level(logical_capacity(b, prg)) << endl; + sched.buf2level[b] = options.get_hierarchy_level(logical_capacity(b, prg)); } } + } cout << sched.compute_unit_latencies << endl; for (auto op : prg.all_ops()) { @@ -19142,6 +19833,7 @@ schedule_info garnet_schedule_info(CodegenOptions& options, prog& prg, bool use_ return sched; } + CodegenOptions garnet_codegen_single_port_with_addrgen_options(prog& prg, string dir) { CodegenOptions options; options.rtl_options.target_tile = TARGET_TILE_WIDE_FETCH_WITH_ADDRGEN; @@ -19169,11 +19861,38 @@ CodegenOptions garnet_codegen_single_port_with_addrgen_options(prog& prg, string return options; } +CodegenOptions garnet_codegen_dual_port_with_addrgen_options(prog& prg, string dir) { + CodegenOptions options; + options.rtl_options.target_tile = TARGET_TILE_WIDE_FETCH_WITH_ADDRGEN; + options.conditional_merge = true; + options.fallback_schedule = ISCA_SCHEDULE; + options.merge_threshold = 10; + options.iis = {1}; + options.rtl_options.max_inpt = 2; + options.rtl_options.max_outpt = 2; + //all_unbanked(prg, options); + + //coreIR codegen options + options.rtl_options.use_prebuilt_memory = true; + options.rtl_options.use_external_controllers = false; + options.rtl_options.double_buffer_optimization = true; + options.inline_vectorization = true; + options.pass_through_valid= true; + options.dir = dir + "/" + prg.name + "/"; + + if (!is_rate_matchable(prg)) { + options.inner_bank_offset_mode = + INNER_BANK_OFFSET_LINEAR; + } + + return options; +} + CodegenOptions garnet_baseline_codegen_options(prog& prg) { CodegenOptions options; options.rtl_options.use_external_controllers = true; options.rtl_options.target_tile = - TARGET_TILE_DUAL_SRAM_WITH_ADDRGEN; + TARGET_TILE_WIDE_FETCH_WITH_ADDRGEN; if (is_rate_matchable(prg)) { options.inner_bank_offset_mode = @@ -19246,7 +19965,9 @@ CodegenOptions CGRA_M1_codegen_options(prog& prg) { options.rtl_options.use_external_controllers = true; options.rtl_options.target_tile = TARGET_TILE_M1; - all_unbanked(prg, options); + options.debug_options.traceWave = true; + //all_unbanked(prg, options); + all_exhaustive_banked(prg, options); return options; } @@ -19312,6 +20033,7 @@ void compile_cycle_accurate_hw(CodegenOptions& options, schedule_info& sched, pr auto hw_sched = its(op_times_map(sched, prg), prg.whole_iteration_domain()); + cout << "final schedule: " << str(hw_sched) << endl; sanity_check_hw_schedule(sched, prg); auto buffers = build_buffers(prg, hw_sched); @@ -19479,7 +20201,7 @@ void compile_for_garnet_fetch2_mem(prog& prg, bool gen_smt_stream, bool config_gen_only, bool multi_level_mem, - bool use_dse_compute, + bool use_metamapper, bool energy_model) { //make sure the loop bound and address is positive @@ -19504,7 +20226,7 @@ void compile_for_garnet_fetch2_mem(prog& prg, options.config_gen_only = config_gen_only; //if (multi_sram) // options.mem_tile.multi_sram_accessor = true; - schedule_info sched = garnet_schedule_info(options, prg, use_dse_compute); + schedule_info sched = garnet_schedule_info(options, prg, use_metamapper); garnet_single_port_ram_schedule(options, sched, prg.root, prg); auto sched_map = op_times_map(sched, prg); auto hw_sched = its(sched_map, @@ -19534,7 +20256,7 @@ void compile_for_garnet_fetch2_mem(prog& prg, #ifdef COREIR - generate_garnet_coreir(buffers_opt, prg, options, sched, use_dse_compute); + generate_garnet_coreir(buffers_opt, prg, options, sched, use_metamapper, ""); if (!options.config_gen_only) { generate_garnet_verilog_top(options, prg.name); generate_garnet_verilator_tb(options, prg, hw_sched, buffers_opt); @@ -19545,7 +20267,7 @@ void compile_for_garnet_fetch2_mem(prog& prg, void generate_resnet_latency_experiment(prog& prg, ofstream& profiling_file, string dir, - bool use_dse_compute) { + bool use_metamapper) { //make sure the loop bound and address is positive normalize_bounds(prg); @@ -19566,11 +20288,11 @@ void generate_resnet_latency_experiment(prog& prg, options.add_memory_hierarchy("glb"); profiling_file << prg.name << ", "; - schedule_info sched = garnet_schedule_info(options, prg, use_dse_compute); + schedule_info sched = garnet_schedule_info(options, prg, use_metamapper); dump_resnet_latency(options, sched, prg.root, prg, profiling_file, false); profiling_file << ", "; - schedule_info sched_db_vanilla = garnet_schedule_info(options, prg, use_dse_compute); + schedule_info sched_db_vanilla = garnet_schedule_info(options, prg, use_metamapper); options.fallback_schedule = VANILLA_DB_SCHEDULE; dump_resnet_latency(options, sched_db_vanilla, prg.root, prg, profiling_file, false); profiling_file << ", "; @@ -19581,17 +20303,19 @@ void generate_resnet_latency_experiment(prog& prg, //profiling_file << ", "; options.fallback_schedule = ISCA_SCHEDULE; - schedule_info sched_db_loop_perfect = garnet_schedule_info(options, prg, use_dse_compute); + schedule_info sched_db_loop_perfect = garnet_schedule_info(options, prg, use_metamapper); dump_resnet_latency(options, sched_db_loop_perfect, prg.root, prg, profiling_file, true); profiling_file << endl; } -void compile_for_garnet_single_port_mem(prog& prg, + +void compile_for_garnet_dual_port_mem(prog& prg, string dir, bool gen_smt_stream, bool config_gen_only, bool multi_level_mem, - bool use_dse_compute, + bool use_metamapper, + string dse_compute_filename, bool energy_model) { //make sure the loop bound and address is positive @@ -19607,11 +20331,11 @@ void compile_for_garnet_single_port_mem(prog& prg, //auto iis = garnet_fuse_ii_level(prg); //auto buffers_opt = build_buffers(prg, clockwork_schedule(prg)); - - CodegenOptions options = garnet_codegen_single_port_with_addrgen_options(prg, dir); + CodegenOptions options = garnet_codegen_dual_port_with_addrgen_options(prg, dir); options.debug_options.traceWave = true; options.add_memory_hierarchy("mem"); options.add_memory_hierarchy("glb"); + options.mem_hierarchy.at("mem").set_config_dp(); if (multi_level_mem) { options.add_memory_hierarchy("regfile"); options.rtl_options.double_buffer_optimization = false; @@ -19628,7 +20352,7 @@ void compile_for_garnet_single_port_mem(prog& prg, prg.pretty_print(); } - schedule_info sched = garnet_schedule_info(options, prg, use_dse_compute); + schedule_info sched = garnet_schedule_info(options, prg, use_metamapper); garnet_single_port_ram_schedule(options, sched, prg.root, prg); auto sched_map = op_times_map(sched, prg); auto hw_sched = its(sched_map, @@ -19657,7 +20381,87 @@ void compile_for_garnet_single_port_mem(prog& prg, } #ifdef COREIR - generate_garnet_coreir(buffers_opt, prg, options, sched, use_dse_compute); + generate_garnet_coreir(buffers_opt, prg, options, sched, use_metamapper, dse_compute_filename); + if (!options.config_gen_only) { + generate_garnet_verilog_top(options, prg.name); + generate_garnet_verilator_tb(options, prg, hw_sched, buffers_opt); + } +#endif +} + +void compile_for_garnet_single_port_mem(prog& prg, + string dir, + bool gen_smt_stream, + bool config_gen_only, + bool multi_level_mem, + bool use_metamapper, + string dse_compute_filename, + bool energy_model) { + + //make sure the loop bound and address is positive + normalize_bounds(prg); + normalize_address_offsets(prg); + //remove_div(prg); + prg.sanity_check(); + prg.pretty_print(); + + + //optimized schedule + cmd("mkdir -p " + dir + "/" + prg.name); + + //auto iis = garnet_fuse_ii_level(prg); + //auto buffers_opt = build_buffers(prg, clockwork_schedule(prg)); + CodegenOptions options = garnet_codegen_single_port_with_addrgen_options(prg, dir); + options.debug_options.traceWave = true; + options.add_memory_hierarchy("mem"); + options.add_memory_hierarchy("glb"); + if (multi_level_mem) { + options.add_memory_hierarchy("regfile"); + //options.rtl_options.double_buffer_optimization = false; + //options.fallback_schedule = SEQUENTIAL_SCHEDULE; + } + options.rtl_options.double_buffer_optimization = true; + options.emit_smt_stream = gen_smt_stream; + options.config_gen_only = config_gen_only; + //if (multi_sram) + // options.mem_tile.multi_sram_accessor = true; + + if(options.fallback_schedule == ISCA_SCHEDULE) { + loop_perfection(prg); + cout << "After Loop Perfection" << endl; + prg.pretty_print(); + } + + schedule_info sched = garnet_schedule_info(options, prg, use_metamapper); + garnet_single_port_ram_schedule(options, sched, prg.root, prg); + auto sched_map = op_times_map(sched, prg); + auto hw_sched = its(sched_map, + prg.whole_iteration_domain()); + cout << "result schedule: " << str(hw_sched) << endl; + auto buffers_opt = build_buffers(prg, hw_sched); + auto sched_max = lexmaxpt(range(hw_sched)); + cout << "Latency of application is: " << str((sched_max)) << endl; + + tag_coarse_grained_loop_to_ubuf(buffers_opt, prg); + //FIXME: put into separate pass for power analysis + if (energy_model) { + mem_access_cnt mem_access; + Mem_access_count(options, buffers_opt, mem_access, prg); + emit_mem_access_count_to_csv(dir + "/MemCount/" + prg.name, options, mem_access); + + power_analysis_params power_params; + power_analysis_info power_stats; + Init_PE_energy_cost(power_params); + +#ifdef COREIR + PE_energy_cost_instance_model(power_params, power_stats, prg); + PE_energy_cost(power_params, power_stats, prg); +#endif + + } + +#ifdef COREIR + generate_garnet_coreir(buffers_opt, prg, options, sched, use_metamapper, dse_compute_filename); if (!options.config_gen_only) { generate_garnet_verilog_top(options, prg.name); generate_garnet_verilator_tb(options, prg, hw_sched, buffers_opt); @@ -19694,6 +20498,35 @@ bool schedule_bounds_fit_controller_bitwidth(const int bitwidth, schedule_info& return true; } +void test_schedules_single_port(vector& test_programs) { + + for (auto& prg : test_programs) { + CodegenOptions options = garnet_codegen_single_port_with_addrgen_options(prg, ""); + options.add_memory_hierarchy("mem"); + options.mem_hierarchy.at("mem").fetch_width = 1; + options.fallback_schedule = ISCA_SCHEDULE; + schedule_info sched = + garnet_schedule_info(options, prg); + + garnet_single_port_ram_schedule(options, sched, prg.root, prg); + cout << "Checking " << prg.name << " schedule" << endl; + prg.pretty_print(); + + assert(no_violated_cycle_accurate_dependencies(sched, prg)); + auto ss = op_start_times_map(sched, prg); + for (auto m : get_maps(ss)) { + //cout << tab(1) << str(m) << endl; + } + auto hw_sched = its(op_times_map(sched, prg), prg.whole_iteration_domain()); + auto sched_max = lexmaxpt(range(hw_sched)); + cout << "APP: " << prg.name << endl; + cout << "\tLatency of application is: " << str((sched_max)) << endl; + } + + //assert(false); +} + + void test_schedules(vector& test_programs) { for (auto& prg : test_programs) { @@ -19707,7 +20540,7 @@ void test_schedules(vector& test_programs) { assert(no_violated_cycle_accurate_dependencies(sched, prg)); auto ss = op_start_times_map(sched, prg); for (auto m : get_maps(ss)) { - cout << tab(1) << str(m) << endl; + //cout << tab(1) << str(m) << endl; } } @@ -19769,25 +20602,59 @@ vector harris_variants() { return test_programs; } -vector isca_programs() { +vector isca_programs_m3() { vector test_programs; //test_programs.push_back(harris_sch5_1ppc()); - //test_programs.push_back(harris()); //test_programs.push_back(harris_sch6_2ppc()); //test_programs.push_back(harris_sch7_bigtile()); //test_programs.push_back(harris_sch8_endcim()); //test_programs.back().pretty_print(); //FIXME: not work for M1 and M3 - //test_programs.push_back(up_sample()); + //test_programs.push_back(three_level_pond_rolled()); + + test_programs.push_back(gaussian()); + //test_programs.push_back(cascade()); + //test_programs.push_back(down_sample()); + //test_programs.push_back(harris()); + //test_programs.push_back(camera_pipeline()); //test_programs.push_back(unsharp()); + //test_programs.push_back(unsharp_new()); + //test_programs.push_back(mobilenet_unrolled()); + //test_programs.push_back(resnet()); + + + return test_programs; +} + +vector isca_programs() { + vector test_programs; + //test_programs.push_back(harris_sch5_1ppc()); + //test_programs.push_back(harris_sch6_2ppc()); + //test_programs.push_back(harris_sch7_bigtile()); + //test_programs.push_back(harris_sch8_endcim()); + //test_programs.back().pretty_print(); + + //FIXME: not work for M1 and M3 //test_programs.push_back(three_level_pond_rolled()); - test_programs.push_back(camera_pipeline()); + + test_programs.push_back(camera_pipeline_new()); + test_programs.push_back(matmul_single()); + test_programs.push_back(camera_pipeline_2x2()); + test_programs.push_back(unsharp_large()); + test_programs.push_back(harris_color()); test_programs.push_back(gaussian()); + //test_programs.push_back(cascade()); + //test_programs.push_back(down_sample()); + //test_programs.push_back(harris()); + //test_programs.push_back(camera_pipeline()); + test_programs.push_back(up_sample()); + //test_programs.push_back(unsharp()); + //test_programs.push_back(unsharp_new()); + //test_programs.push_back(resnet()); + test_programs.push_back(resnet88_chain()); test_programs.push_back(mobilenet_unrolled()); - test_programs.push_back(resnet()); - test_programs.push_back(cascade()); - test_programs.push_back(down_sample()); + return test_programs; } @@ -19830,6 +20697,7 @@ void cpy_app_to_folder(const std::string& app_type, const std::string& prg_name) cmd("mkdir -p ./coreir_apps/" + app_type + "/" + prg_name); //cmd("mv LakeWrapper.v ./coreir_apps/coreir_apps/" + app_type +"/" + prg_name + "/"); cmd("mv " + prg_name + ".json ./coreir_apps/" + app_type + "/" + prg_name + "/"); + cmd("mv cgra_resource_estimation.csv ./coreir_apps/" + app_type + "/" + prg_name + "/"); cmd("mv " + prg_name + "_post_mapping.json ./coreir_apps/" + app_type + "/" + prg_name + "/"); cmd("mv " + prg_name + ".v ./coreir_apps/" + app_type + "/" + prg_name + "/"); cmd("mv " + prg_name + "_verilog_collateral.sv ./coreir_apps/" + app_type + "/" + prg_name + "/"); @@ -20137,33 +21005,29 @@ void fpga_asplos_tests() { void cgra_flow_tests() { - vector M3_test_programs = isca_programs(); //vector bram_test_programs{pointwise(), gaussian(), harris(), resnet()}; - vector bram_test_programs{resnet88()}; + //vector bram_test_programs{resnet88()}; //vector bram_test_programs{pointwise()}; - test_codegen(bram_test_programs, compile_for_FPGA_BRAM_mem); + //test_codegen(bram_test_programs, compile_for_FPGA_BRAM_mem); //vector M3_test_programs = harris_variants(); //vector M3_test_programs{up_sample(), resnet()}; //vector M3_test_programs{resnet()}; //vector M3_test_programs{gaussian()}; - test_codegen(M3_test_programs, compile_for_CGRA_M3_mem); + //vector M3_test_programs = isca_programs_m3(); + //test_codegen(M3_test_programs, compile_for_CGRA_M3_mem); //assert(false); + //vector M1_test_programs{resnet88_chain()}; vector M1_test_programs = isca_programs(); - //vector M1_test_programs{gaussian()}; test_codegen(M1_test_programs, compile_for_CGRA_M1_mem); - auto test_programs = - all_cgra_programs(); - test_platonic_codegen(test_programs); - - + //auto test_programs = all_cgra_programs(); + //test_platonic_codegen(test_programs); - - vector sram_test_programs{pointwise(), camera_pipeline(), resnet()}; - test_codegen(sram_test_programs, compile_for_generic_SRAM_mem); + //vector sram_test_programs{pointwise(), camera_pipeline(), resnet()}; + //test_codegen(sram_test_programs, compile_for_generic_SRAM_mem); } @@ -20207,6 +21071,22 @@ void dual_port_lake_test() { } +void test_dual_port_latency() { + + vector test_programs; + test_programs.push_back(gaussian()); + test_programs.push_back(harris()); + test_programs.push_back(unsharp_large()); + test_programs.push_back(camera_pipeline_2x2()); + test_programs.push_back(up_sample()); + test_programs.push_back(resnet88()); + test_programs.push_back(mobilenet_unrolled()); + test_programs.push_back(matmul_single()); + + + test_schedules_single_port(test_programs); +} + void full_cgra_flow_tests() { #ifdef COREIR @@ -27646,14 +28526,17 @@ void unoptimized_mem_baseline() { isscc_programs.push_back(gaussian_isscc()); isscc_programs.push_back(unsharp_isscc()); isscc_programs.push_back(harris_color()); - isscc_programs.push_back(camera_pipeline_isscc()); + isscc_programs.push_back(camera_pipeline_2x2()); for (auto prg : isscc_programs) { + normalize_bounds(prg); + dsa_writers(prg); auto options = garnet_baseline_codegen_options(prg); schedule_info sched = garnet_schedule_info(options, prg); + options.add_memory_hierarchy("mem"); //compile_cycle_accurate_hw(options, sched, prg); - normalize_bounds(prg); - sequential_schedule(sched, prg.root, prg); + //sequential_schedule(sched, prg.root, prg); + garnet_single_port_ram_schedule(options, sched, prg.root, prg); auto hw_sched = its(op_times_map(sched, prg), prg.whole_iteration_domain()); auto sched_max = lexmaxpt(range(hw_sched)); @@ -27674,7 +28557,8 @@ void unoptimized_mem_baseline() { int mem_tile_num_by_bank = b.second.get_banks().size(); cout << tab(4) << "naive capacity tile number: " << mem_tile_num_by_capacity << endl; cout << tab(4) << "naive banking number: " << mem_tile_num_by_bank << endl; - total_tile += max(mem_tile_num_by_capacity, mem_tile_num_by_bank); + //total_tile += max(mem_tile_num_by_capacity, mem_tile_num_by_bank); + total_tile += mem_tile_num_by_bank; } } cout << tab(1) << "=== SRAM bytes for " << prg.name << ": " << total_capacity << endl; @@ -27999,6 +28883,7 @@ int main(int argc, char** argv) { return 0; } + if (cmd == "dse-flow") { dse_flow_tests(); return 0; @@ -28069,6 +28954,18 @@ int main(int argc, char** argv) { return 0; } + if (cmd == "dp-tests") { + bool gen_config_only = false; + bool use_multi_accessor_tile = true; + test_dual_port_mem(gen_config_only, use_multi_accessor_tile, "aha_garnet_design_dp"); + return 0; + } + + if (cmd == "dp-latency") { + test_dual_port_latency(); + return 0; + } + if (cmd == "pond-exp") { bool run_verilator = false; test_pond("aha_garnet_design_pond", run_verilator); diff --git a/build_set_test.h b/build_set_test.h index 40cb09b42..2115aab3b 100755 --- a/build_set_test.h +++ b/build_set_test.h @@ -4,7 +4,7 @@ void break_up_multi_channel_outputs(prog& prg); void break_up_multi_channel_inputs(prog& prg); void asap_inner_loops_schedule(schedule_info& hwinfo, op* op, prog& prg); void garnet_single_port_ram_schedule(schedule_info& sched, op* root, prog& prg); -void compile_for_garnet_single_port_mem(prog& prg, string dir, bool gen_smt_stream, bool config_gen_only, bool multi_sram, bool use_dse_compute, bool energy_model=false); +void compile_for_garnet_single_port_mem(prog& prg, string dir, bool gen_smt_stream, bool config_gen_only, bool multi_level_mem, bool use_metamapper, string dse_compute_filename, bool energy_model=false); int run_verilator_on(const std::string& top_module, const std::string& tb_file, const std::vector& verilog_files, diff --git a/camera_pipeline_2x2_compute.h b/camera_pipeline_2x2_compute.h new file mode 100644 index 000000000..b253484e2 --- /dev/null +++ b/camera_pipeline_2x2_compute.h @@ -0,0 +1,25749 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_1(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_2 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_2(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_3 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_3(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_4 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_4; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_1 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_1; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_1(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_2 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_2; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_2(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_3 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_3; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_3(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_4 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_4; +} + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 2)))))) +hw_uint<16> hcompute_denoised_1_stencil(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_1 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_2 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_3 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_4 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_5 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _372 = max(_hw_input_global_wrapper_global_wrapper_stencil_4, _hw_input_global_wrapper_global_wrapper_stencil_5); + uint16_t _373 = max(_hw_input_global_wrapper_global_wrapper_stencil_3, _372); + uint16_t _374 = max(_hw_input_global_wrapper_global_wrapper_stencil_2, _373); + uint16_t _375 = min(_hw_input_global_wrapper_global_wrapper_stencil_1, _374); + return _375; +} + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 3)))))) +hw_uint<16> hcompute_denoised_1_stencil_1(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_10 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_6 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_7 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_8 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_9 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _395 = max(_hw_input_global_wrapper_global_wrapper_stencil_9, _hw_input_global_wrapper_global_wrapper_stencil_10); + uint16_t _396 = max(_hw_input_global_wrapper_global_wrapper_stencil_8, _395); + uint16_t _397 = max(_hw_input_global_wrapper_global_wrapper_stencil_7, _396); + uint16_t _398 = min(_hw_input_global_wrapper_global_wrapper_stencil_6, _397); + return _398; +} + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 2)))))) +hw_uint<16> hcompute_denoised_1_stencil_2(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_11 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_12 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_13 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_14 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_15 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _419 = max(_hw_input_global_wrapper_global_wrapper_stencil_14, _hw_input_global_wrapper_global_wrapper_stencil_15); + uint16_t _420 = max(_hw_input_global_wrapper_global_wrapper_stencil_13, _419); + uint16_t _421 = max(_hw_input_global_wrapper_global_wrapper_stencil_12, _420); + uint16_t _422 = min(_hw_input_global_wrapper_global_wrapper_stencil_11, _421); + return _422; +} + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 3)))))) +hw_uint<16> hcompute_denoised_1_stencil_3(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_16 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_17 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_18 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_19 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_20 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _443 = max(_hw_input_global_wrapper_global_wrapper_stencil_19, _hw_input_global_wrapper_global_wrapper_stencil_20); + uint16_t _444 = max(_hw_input_global_wrapper_global_wrapper_stencil_18, _443); + uint16_t _445 = max(_hw_input_global_wrapper_global_wrapper_stencil_17, _444); + uint16_t _446 = min(_hw_input_global_wrapper_global_wrapper_stencil_16, _445); + return _446; +} + +//store is: b_b.stencil(b_b_s0_x, (b_b_s0_y + 1)) = denoised$1.stencil(((b_b_s0_x*2) + 2), ((b_b_s0_y*2) + 3)) +hw_uint<16> hcompute_b_b_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_1 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_1; +} + +//store is: g_gb.stencil((g_gb_s0_x + 1), (g_gb_s0_y + 1)) = denoised$1.stencil(((g_gb_s0_x*2) + 3), ((g_gb_s0_y*2) + 3)) +hw_uint<16> hcompute_g_gb_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_2 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_2; +} + +//store is: g_gr.stencil((g_gr_s0_x + 1), (g_gr_s0_y + 1)) = denoised$1.stencil(((g_gr_s0_x*2) + 2), ((g_gr_s0_y*2) + 2)) +hw_uint<16> hcompute_g_gr_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_3 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_3; +} + +//store is: g_b.stencil(g_b_s0_x, (g_b_s0_y + 1)) = select((absd(g_gb.stencil(g_b_s0_x, (g_b_s0_y + 1)), g_gb.stencil((g_b_s0_x + 1), (g_b_s0_y + 1))) < absd(g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 2)), g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))), ((g_gb.stencil(g_b_s0_x, (g_b_s0_y + 1)) + g_gb.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))/(uint16)2), ((g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 2)) + g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_1 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_2 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_1 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_2 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _488 = _g_gb_stencil_1 + _g_gb_stencil_2; + uint16_t _489 = (uint16_t)(1); + uint16_t _490 = _488 >> _489; + uint16_t _491 = _g_gr_stencil_1 + _g_gr_stencil_2; + uint16_t _492 = _491 >> _489; + uint16_t _493 = _g_gb_stencil_2 - _g_gb_stencil_1; + uint16_t _494 = _g_gb_stencil_1 - _g_gb_stencil_2; + bool _495 = _g_gb_stencil_1 < _g_gb_stencil_2; + uint16_t _496 = (uint16_t)(_495 ? _493 : _494); + uint16_t _497 = _496; + uint16_t _498 = _g_gr_stencil_2 - _g_gr_stencil_1; + uint16_t _499 = _g_gr_stencil_1 - _g_gr_stencil_2; + bool _500 = _g_gr_stencil_1 < _g_gr_stencil_2; + uint16_t _501 = (uint16_t)(_500 ? _498 : _499); + uint16_t _502 = _501; + bool _503 = _497 < _502; + uint16_t _504 = (uint16_t)(_503 ? _490 : _492); + return _504; +} + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + ((b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) - ((g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_1 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_2 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_1 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_2 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gb_stencil_3 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _538 = _b_b_stencil_1 + _b_b_stencil_2; + uint16_t _539 = (uint16_t)(1); + uint16_t _540 = _538 >> _539; + uint16_t _541 = _g_gb_stencil_3 + _540; + uint16_t _542 = _g_b_stencil_1 + _g_b_stencil_2; + uint16_t _543 = _542 >> _539; + uint16_t _544 = _541 - _543; + return _544; +} + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + ((b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + b_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) - ((g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + g_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_3 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_4 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_3 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_4 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_3 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _566 = _b_b_stencil_3 + _b_b_stencil_4; + uint16_t _567 = (uint16_t)(1); + uint16_t _568 = _566 >> _567; + uint16_t _569 = _g_gr_stencil_3 + _568; + uint16_t _570 = _g_b_stencil_3 + _g_b_stencil_4; + uint16_t _571 = _570 >> _567; + uint16_t _572 = _569 - _571; + return _572; +} + +//store is: g_r.stencil((g_r_s0_x + 1), g_r_s0_y) = select((absd(g_gr.stencil((g_r_s0_x + 2), (g_r_s0_y + 1)), g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1))) < absd(g_gb.stencil((g_r_s0_x + 1), g_r_s0_y), g_gb.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))), ((g_gr.stencil((g_r_s0_x + 2), (g_r_s0_y + 1)) + g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))/(uint16)2), ((g_gb.stencil((g_r_s0_x + 1), g_r_s0_y) + g_gb.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_4 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_5 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_4 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_5 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _594 = _g_gr_stencil_4 + _g_gr_stencil_5; + uint16_t _595 = (uint16_t)(1); + uint16_t _596 = _594 >> _595; + uint16_t _597 = _g_gb_stencil_4 + _g_gb_stencil_5; + uint16_t _598 = _597 >> _595; + uint16_t _599 = _g_gr_stencil_5 - _g_gr_stencil_4; + uint16_t _600 = _g_gr_stencil_4 - _g_gr_stencil_5; + bool _601 = _g_gr_stencil_4 < _g_gr_stencil_5; + uint16_t _602 = (uint16_t)(_601 ? _599 : _600); + uint16_t _603 = _602; + uint16_t _604 = _g_gb_stencil_5 - _g_gb_stencil_4; + uint16_t _605 = _g_gb_stencil_4 - _g_gb_stencil_5; + bool _606 = _g_gb_stencil_4 < _g_gb_stencil_5; + uint16_t _607 = (uint16_t)(_606 ? _604 : _605); + uint16_t _608 = _607; + bool _609 = _603 < _608; + uint16_t _610 = (uint16_t)(_609 ? _596 : _598); + return _610; +} + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + b_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)) - ((g_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + g_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + b_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2)) - ((g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + g_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_5 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_6 = (uint16_t) (b_b_stencil.extract<16, 31>()); + uint16_t _b_b_stencil_7 = (uint16_t) (b_b_stencil.extract<32, 47>()); + uint16_t _b_b_stencil_8 = (uint16_t) (b_b_stencil.extract<48, 63>()); + + uint16_t _g_b_stencil_5 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_6 = (uint16_t) (g_b_stencil.extract<16, 31>()); + uint16_t _g_b_stencil_7 = (uint16_t) (g_b_stencil.extract<32, 47>()); + uint16_t _g_b_stencil_8 = (uint16_t) (g_b_stencil.extract<48, 63>()); + + uint16_t _g_r_stencil_1 = (uint16_t) (g_r_stencil.extract<0, 15>()); + + uint16_t _644 = _b_b_stencil_5 + _b_b_stencil_6; + uint16_t _645 = (uint16_t)(1); + uint16_t _646 = _644 >> _645; + uint16_t _647 = _g_r_stencil_1 + _646; + uint16_t _648 = _g_b_stencil_5 + _g_b_stencil_6; + uint16_t _649 = _648 >> _645; + uint16_t _650 = _647 - _649; + uint16_t _651 = _b_b_stencil_7 + _b_b_stencil_8; + uint16_t _652 = _651 >> _645; + uint16_t _653 = _g_r_stencil_1 + _652; + uint16_t _654 = _g_b_stencil_7 + _g_b_stencil_8; + uint16_t _655 = _654 >> _645; + uint16_t _656 = _653 - _655; + uint16_t _657 = _b_b_stencil_6 - _b_b_stencil_5; + uint16_t _658 = _b_b_stencil_5 - _b_b_stencil_6; + bool _659 = _b_b_stencil_5 < _b_b_stencil_6; + uint16_t _660 = (uint16_t)(_659 ? _657 : _658); + uint16_t _661 = _660; + uint16_t _662 = _b_b_stencil_8 - _b_b_stencil_7; + uint16_t _663 = _b_b_stencil_7 - _b_b_stencil_8; + bool _664 = _b_b_stencil_7 < _b_b_stencil_8; + uint16_t _665 = (uint16_t)(_664 ? _662 : _663); + uint16_t _666 = _665; + bool _667 = _661 < _666; + uint16_t _668 = (uint16_t)(_667 ? _650 : _656); + return _668; +} + +//store is: r_r.stencil((r_r_s0_x + 1), r_r_s0_y) = denoised$1.stencil(((r_r_s0_x*2) + 3), ((r_r_s0_y*2) + 2)) +hw_uint<16> hcompute_r_r_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_4 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_4; +} + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil((r_b_s0_x + 1), r_b_s0_y) + r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x + 1), r_b_s0_y) + g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil(r_b_s0_x, r_b_s0_y) + r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil(r_b_s0_x, r_b_s0_y) + g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_9 = (uint16_t) (g_b_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_2 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_3 = (uint16_t) (g_r_stencil.extract<16, 31>()); + uint16_t _g_r_stencil_4 = (uint16_t) (g_r_stencil.extract<32, 47>()); + uint16_t _g_r_stencil_5 = (uint16_t) (g_r_stencil.extract<48, 63>()); + + uint16_t _r_r_stencil_1 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_2 = (uint16_t) (r_r_stencil.extract<16, 31>()); + uint16_t _r_r_stencil_3 = (uint16_t) (r_r_stencil.extract<32, 47>()); + uint16_t _r_r_stencil_4 = (uint16_t) (r_r_stencil.extract<48, 63>()); + + uint16_t _728 = _r_r_stencil_1 + _r_r_stencil_2; + uint16_t _729 = (uint16_t)(1); + uint16_t _730 = _728 >> _729; + uint16_t _731 = _g_b_stencil_9 + _730; + uint16_t _732 = _g_r_stencil_2 + _g_r_stencil_3; + uint16_t _733 = _732 >> _729; + uint16_t _734 = _731 - _733; + uint16_t _735 = _r_r_stencil_3 + _r_r_stencil_4; + uint16_t _736 = _735 >> _729; + uint16_t _737 = _g_b_stencil_9 + _736; + uint16_t _738 = _g_r_stencil_4 + _g_r_stencil_5; + uint16_t _739 = _738 >> _729; + uint16_t _740 = _737 - _739; + uint16_t _741 = _r_r_stencil_2 - _r_r_stencil_1; + uint16_t _742 = _r_r_stencil_1 - _r_r_stencil_2; + bool _743 = _r_r_stencil_1 < _r_r_stencil_2; + uint16_t _744 = (uint16_t)(_743 ? _741 : _742); + uint16_t _745 = _744; + uint16_t _746 = _r_r_stencil_4 - _r_r_stencil_3; + uint16_t _747 = _r_r_stencil_3 - _r_r_stencil_4; + bool _748 = _r_r_stencil_3 < _r_r_stencil_4; + uint16_t _749 = (uint16_t)(_748 ? _746 : _747); + uint16_t _750 = _749; + bool _751 = _745 < _750; + uint16_t _752 = (uint16_t)(_751 ? _734 : _740); + return _752; +} + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + ((r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_6 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_6 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_7 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_5 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_6 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _806 = _r_r_stencil_5 + _r_r_stencil_6; + uint16_t _807 = (uint16_t)(1); + uint16_t _808 = _806 >> _807; + uint16_t _809 = _g_gb_stencil_6 + _808; + uint16_t _810 = _g_r_stencil_6 + _g_r_stencil_7; + uint16_t _811 = _810 >> _807; + uint16_t _812 = _809 - _811; + return _812; +} + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + ((r_r.stencil(r_gr_s0_x, r_gr_s0_y) + r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y))/(uint16)2)) - ((g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + g_r.stencil(r_gr_s0_x, r_gr_s0_y))/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_6 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_8 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_9 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_7 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_8 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _834 = _r_r_stencil_7 + _r_r_stencil_8; + uint16_t _835 = (uint16_t)(1); + uint16_t _836 = _834 >> _835; + uint16_t _837 = _g_gr_stencil_6 + _836; + uint16_t _838 = _g_r_stencil_8 + _g_r_stencil_9; + uint16_t _839 = _838 >> _835; + uint16_t _840 = _837 - _839; + return _840; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 0) = r_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil(hw_uint<16>& r_gr_stencil) { + uint16_t _r_gr_stencil_1 = (uint16_t) (r_gr_stencil.extract<0, 15>()); + + return _r_gr_stencil_1; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 1) = g_gr.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_1(hw_uint<16>& g_gr_stencil) { + uint16_t _g_gr_stencil_7 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + return _g_gr_stencil_7; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 2) = b_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_2(hw_uint<16>& b_gr_stencil) { + uint16_t _b_gr_stencil_1 = (uint16_t) (b_gr_stencil.extract<0, 15>()); + + return _b_gr_stencil_1; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_b.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_3(hw_uint<16>& r_b_stencil) { + uint16_t _r_b_stencil_1 = (uint16_t) (r_b_stencil.extract<0, 15>()); + + return _r_b_stencil_1; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_4(hw_uint<16>& g_b_stencil) { + uint16_t _g_b_stencil_10 = (uint16_t) (g_b_stencil.extract<0, 15>()); + + return _g_b_stencil_10; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_5(hw_uint<16>& b_b_stencil) { + uint16_t _b_b_stencil_9 = (uint16_t) (b_b_stencil.extract<0, 15>()); + + return _b_b_stencil_9; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 0) = r_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_6(hw_uint<16>& r_r_stencil) { + uint16_t _r_r_stencil_9 = (uint16_t) (r_r_stencil.extract<0, 15>()); + + return _r_r_stencil_9; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 1) = g_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_7(hw_uint<16>& g_r_stencil) { + uint16_t _g_r_stencil_10 = (uint16_t) (g_r_stencil.extract<0, 15>()); + + return _g_r_stencil_10; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 2) = b_r.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_8(hw_uint<16>& b_r_stencil) { + uint16_t _b_r_stencil_1 = (uint16_t) (b_r_stencil.extract<0, 15>()); + + return _b_r_stencil_1; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_9(hw_uint<16>& r_gb_stencil) { + uint16_t _r_gb_stencil_1 = (uint16_t) (r_gb_stencil.extract<0, 15>()); + + return _r_gb_stencil_1; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_gb.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_10(hw_uint<16>& g_gb_stencil) { + uint16_t _g_gb_stencil_7 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + return _g_gb_stencil_7; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_11(hw_uint<16>& b_gb_stencil) { + uint16_t _b_gb_stencil_1 = (uint16_t) (b_gb_stencil.extract<0, 15>()); + + return _b_gb_stencil_1; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_1 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_2 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_3 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _918 = (uint16_t)(10000); + uint16_t _919 = min(_demosaicked_1_stencil_1, _918); + int32_t _920 = (int32_t)(_919); + int32_t _921 = _920 * 549; + int32_t _922 = _921 >> 8; + int16_t _923 = (int16_t)(_922); + uint16_t _924 = min(_demosaicked_1_stencil_2, _918); + int32_t _925 = (int32_t)(_924); + int32_t _926 = _925 * -103; + int32_t _927 = _926 >> 8; + int16_t _928 = (int16_t)(_927); + int16_t _929 = _923 + _928; + uint16_t _930 = min(_demosaicked_1_stencil_3, _918); + int32_t _931 = (int32_t)(_930); + int32_t _932 = _931 * 7; + int32_t _933 = _932 >> 8; + int16_t _934 = (int16_t)(_933); + int16_t _935 = _929 + _934; + int16_t _936 = (int16_t)(-40); + int16_t _937 = _935 + _936; + return _937; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_1(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_4 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_5 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_6 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _977 = (uint16_t)(10000); + uint16_t _978 = min(_demosaicked_1_stencil_4, _977); + int32_t _979 = (int32_t)(_978); + int32_t _980 = _979 * -96; + int32_t _981 = _980 >> 8; + int16_t _982 = (int16_t)(_981); + uint16_t _983 = min(_demosaicked_1_stencil_5, _977); + int32_t _984 = (int32_t)(_983); + int32_t _985 = _984 * 373; + int32_t _986 = _985 >> 8; + int16_t _987 = (int16_t)(_986); + int16_t _988 = _982 + _987; + uint16_t _989 = min(_demosaicked_1_stencil_6, _977); + int32_t _990 = (int32_t)(_989); + int32_t _991 = _990 * 62; + int32_t _992 = _991 >> 8; + int16_t _993 = (int16_t)(_992); + int16_t _994 = _988 + _993; + int16_t _995 = (int16_t)(-29); + int16_t _996 = _994 + _995; + return _996; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_2(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_7 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_8 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_9 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1036 = (uint16_t)(10000); + uint16_t _1037 = min(_demosaicked_1_stencil_7, _1036); + int32_t _1038 = (int32_t)(_1037); + int32_t _1039 = _1038 * -31; + int32_t _1040 = _1039 >> 8; + int16_t _1041 = (int16_t)(_1040); + uint16_t _1042 = min(_demosaicked_1_stencil_8, _1036); + int32_t _1043 = (int32_t)(_1042); + int32_t _1044 = _1043 * -261; + int32_t _1045 = _1044 >> 8; + int16_t _1046 = (int16_t)(_1045); + int16_t _1047 = _1041 + _1046; + uint16_t _1048 = min(_demosaicked_1_stencil_9, _1036); + int32_t _1049 = (int32_t)(_1048); + int32_t _1050 = _1049 * 883; + int32_t _1051 = _1050 >> 8; + int16_t _1052 = (int16_t)(_1051); + int16_t _1053 = _1047 + _1052; + int16_t _1054 = (int16_t)(-22); + int16_t _1055 = _1053 + _1054; + return _1055; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_3(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_10 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_11 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_12 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1095 = (uint16_t)(10000); + uint16_t _1096 = min(_demosaicked_1_stencil_10, _1095); + int32_t _1097 = (int32_t)(_1096); + int32_t _1098 = _1097 * 549; + int32_t _1099 = _1098 >> 8; + int16_t _1100 = (int16_t)(_1099); + uint16_t _1101 = min(_demosaicked_1_stencil_11, _1095); + int32_t _1102 = (int32_t)(_1101); + int32_t _1103 = _1102 * -103; + int32_t _1104 = _1103 >> 8; + int16_t _1105 = (int16_t)(_1104); + int16_t _1106 = _1100 + _1105; + uint16_t _1107 = min(_demosaicked_1_stencil_12, _1095); + int32_t _1108 = (int32_t)(_1107); + int32_t _1109 = _1108 * 7; + int32_t _1110 = _1109 >> 8; + int16_t _1111 = (int16_t)(_1110); + int16_t _1112 = _1106 + _1111; + int16_t _1113 = (int16_t)(-40); + int16_t _1114 = _1112 + _1113; + return _1114; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_4(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_13 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_14 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_15 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1155 = (uint16_t)(10000); + uint16_t _1156 = min(_demosaicked_1_stencil_13, _1155); + int32_t _1157 = (int32_t)(_1156); + int32_t _1158 = _1157 * -96; + int32_t _1159 = _1158 >> 8; + int16_t _1160 = (int16_t)(_1159); + uint16_t _1161 = min(_demosaicked_1_stencil_14, _1155); + int32_t _1162 = (int32_t)(_1161); + int32_t _1163 = _1162 * 373; + int32_t _1164 = _1163 >> 8; + int16_t _1165 = (int16_t)(_1164); + int16_t _1166 = _1160 + _1165; + uint16_t _1167 = min(_demosaicked_1_stencil_15, _1155); + int32_t _1168 = (int32_t)(_1167); + int32_t _1169 = _1168 * 62; + int32_t _1170 = _1169 >> 8; + int16_t _1171 = (int16_t)(_1170); + int16_t _1172 = _1166 + _1171; + int16_t _1173 = (int16_t)(-29); + int16_t _1174 = _1172 + _1173; + return _1174; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_5(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_16 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_17 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_18 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1215 = (uint16_t)(10000); + uint16_t _1216 = min(_demosaicked_1_stencil_16, _1215); + int32_t _1217 = (int32_t)(_1216); + int32_t _1218 = _1217 * -31; + int32_t _1219 = _1218 >> 8; + int16_t _1220 = (int16_t)(_1219); + uint16_t _1221 = min(_demosaicked_1_stencil_17, _1215); + int32_t _1222 = (int32_t)(_1221); + int32_t _1223 = _1222 * -261; + int32_t _1224 = _1223 >> 8; + int16_t _1225 = (int16_t)(_1224); + int16_t _1226 = _1220 + _1225; + uint16_t _1227 = min(_demosaicked_1_stencil_18, _1215); + int32_t _1228 = (int32_t)(_1227); + int32_t _1229 = _1228 * 883; + int32_t _1230 = _1229 >> 8; + int16_t _1231 = (int16_t)(_1230); + int16_t _1232 = _1226 + _1231; + int16_t _1233 = (int16_t)(-22); + int16_t _1234 = _1232 + _1233; + return _1234; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_6(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_19 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_20 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_21 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1275 = (uint16_t)(10000); + uint16_t _1276 = min(_demosaicked_1_stencil_19, _1275); + int32_t _1277 = (int32_t)(_1276); + int32_t _1278 = _1277 * 549; + int32_t _1279 = _1278 >> 8; + int16_t _1280 = (int16_t)(_1279); + uint16_t _1281 = min(_demosaicked_1_stencil_20, _1275); + int32_t _1282 = (int32_t)(_1281); + int32_t _1283 = _1282 * -103; + int32_t _1284 = _1283 >> 8; + int16_t _1285 = (int16_t)(_1284); + int16_t _1286 = _1280 + _1285; + uint16_t _1287 = min(_demosaicked_1_stencil_21, _1275); + int32_t _1288 = (int32_t)(_1287); + int32_t _1289 = _1288 * 7; + int32_t _1290 = _1289 >> 8; + int16_t _1291 = (int16_t)(_1290); + int16_t _1292 = _1286 + _1291; + int16_t _1293 = (int16_t)(-40); + int16_t _1294 = _1292 + _1293; + return _1294; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_7(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_22 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_23 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_24 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1335 = (uint16_t)(10000); + uint16_t _1336 = min(_demosaicked_1_stencil_22, _1335); + int32_t _1337 = (int32_t)(_1336); + int32_t _1338 = _1337 * -96; + int32_t _1339 = _1338 >> 8; + int16_t _1340 = (int16_t)(_1339); + uint16_t _1341 = min(_demosaicked_1_stencil_23, _1335); + int32_t _1342 = (int32_t)(_1341); + int32_t _1343 = _1342 * 373; + int32_t _1344 = _1343 >> 8; + int16_t _1345 = (int16_t)(_1344); + int16_t _1346 = _1340 + _1345; + uint16_t _1347 = min(_demosaicked_1_stencil_24, _1335); + int32_t _1348 = (int32_t)(_1347); + int32_t _1349 = _1348 * 62; + int32_t _1350 = _1349 >> 8; + int16_t _1351 = (int16_t)(_1350); + int16_t _1352 = _1346 + _1351; + int16_t _1353 = (int16_t)(-29); + int16_t _1354 = _1352 + _1353; + return _1354; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_8(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_25 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_26 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_27 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1395 = (uint16_t)(10000); + uint16_t _1396 = min(_demosaicked_1_stencil_25, _1395); + int32_t _1397 = (int32_t)(_1396); + int32_t _1398 = _1397 * -31; + int32_t _1399 = _1398 >> 8; + int16_t _1400 = (int16_t)(_1399); + uint16_t _1401 = min(_demosaicked_1_stencil_26, _1395); + int32_t _1402 = (int32_t)(_1401); + int32_t _1403 = _1402 * -261; + int32_t _1404 = _1403 >> 8; + int16_t _1405 = (int16_t)(_1404); + int16_t _1406 = _1400 + _1405; + uint16_t _1407 = min(_demosaicked_1_stencil_27, _1395); + int32_t _1408 = (int32_t)(_1407); + int32_t _1409 = _1408 * 883; + int32_t _1410 = _1409 >> 8; + int16_t _1411 = (int16_t)(_1410); + int16_t _1412 = _1406 + _1411; + int16_t _1413 = (int16_t)(-22); + int16_t _1414 = _1412 + _1413; + return _1414; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_9(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_28 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_29 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_30 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1455 = (uint16_t)(10000); + uint16_t _1456 = min(_demosaicked_1_stencil_28, _1455); + int32_t _1457 = (int32_t)(_1456); + int32_t _1458 = _1457 * 549; + int32_t _1459 = _1458 >> 8; + int16_t _1460 = (int16_t)(_1459); + uint16_t _1461 = min(_demosaicked_1_stencil_29, _1455); + int32_t _1462 = (int32_t)(_1461); + int32_t _1463 = _1462 * -103; + int32_t _1464 = _1463 >> 8; + int16_t _1465 = (int16_t)(_1464); + int16_t _1466 = _1460 + _1465; + uint16_t _1467 = min(_demosaicked_1_stencil_30, _1455); + int32_t _1468 = (int32_t)(_1467); + int32_t _1469 = _1468 * 7; + int32_t _1470 = _1469 >> 8; + int16_t _1471 = (int16_t)(_1470); + int16_t _1472 = _1466 + _1471; + int16_t _1473 = (int16_t)(-40); + int16_t _1474 = _1472 + _1473; + return _1474; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_10(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_31 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_32 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_33 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1516 = (uint16_t)(10000); + uint16_t _1517 = min(_demosaicked_1_stencil_31, _1516); + int32_t _1518 = (int32_t)(_1517); + int32_t _1519 = _1518 * -96; + int32_t _1520 = _1519 >> 8; + int16_t _1521 = (int16_t)(_1520); + uint16_t _1522 = min(_demosaicked_1_stencil_32, _1516); + int32_t _1523 = (int32_t)(_1522); + int32_t _1524 = _1523 * 373; + int32_t _1525 = _1524 >> 8; + int16_t _1526 = (int16_t)(_1525); + int16_t _1527 = _1521 + _1526; + uint16_t _1528 = min(_demosaicked_1_stencil_33, _1516); + int32_t _1529 = (int32_t)(_1528); + int32_t _1530 = _1529 * 62; + int32_t _1531 = _1530 >> 8; + int16_t _1532 = (int16_t)(_1531); + int16_t _1533 = _1527 + _1532; + int16_t _1534 = (int16_t)(-29); + int16_t _1535 = _1533 + _1534; + return _1535; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_11(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_34 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_35 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_36 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _1577 = (uint16_t)(10000); + uint16_t _1578 = min(_demosaicked_1_stencil_34, _1577); + int32_t _1579 = (int32_t)(_1578); + int32_t _1580 = _1579 * -31; + int32_t _1581 = _1580 >> 8; + int16_t _1582 = (int16_t)(_1581); + uint16_t _1583 = min(_demosaicked_1_stencil_35, _1577); + int32_t _1584 = (int32_t)(_1583); + int32_t _1585 = _1584 * -261; + int32_t _1586 = _1585 >> 8; + int16_t _1587 = (int16_t)(_1586); + int16_t _1588 = _1582 + _1587; + uint16_t _1589 = min(_demosaicked_1_stencil_36, _1577); + int32_t _1590 = (int32_t)(_1589); + int32_t _1591 = _1590 * 883; + int32_t _1592 = _1591 >> 8; + int16_t _1593 = (int16_t)(_1592); + int16_t _1594 = _1588 + _1593; + int16_t _1595 = (int16_t)(-22); + int16_t _1596 = _1594 + _1595; + return _1596; +} + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_1 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _2662 = (uint16_t)(0); + _curvea0[0] = _2662; + uint16_t _2663 = (uint16_t)(4); + _curvea0[1] = _2663; + uint16_t _2664 = (uint16_t)(7); + _curvea0[2] = _2664; + uint16_t _2665 = (uint16_t)(8); + _curvea0[3] = _2665; + uint16_t _2666 = (uint16_t)(10); + _curvea0[4] = _2666; + uint16_t _2667 = (uint16_t)(11); + _curvea0[5] = _2667; + uint16_t _2668 = (uint16_t)(12); + _curvea0[6] = _2668; + uint16_t _2669 = (uint16_t)(13); + _curvea0[7] = _2669; + uint16_t _2670 = (uint16_t)(14); + _curvea0[8] = _2670; + uint16_t _2671 = (uint16_t)(15); + _curvea0[9] = _2671; + uint16_t _2672 = (uint16_t)(16); + _curvea0[10] = _2672; + uint16_t _2673 = (uint16_t)(17); + _curvea0[11] = _2673; + uint16_t _2674 = (uint16_t)(18); + _curvea0[12] = _2674; + uint16_t _2675 = (uint16_t)(19); + _curvea0[13] = _2675; + uint16_t _2676 = (uint16_t)(20); + _curvea0[14] = _2676; + uint16_t _2677 = (uint16_t)(21); + _curvea0[15] = _2677; + uint16_t _2678 = (uint16_t)(22); + _curvea0[16] = _2678; + uint16_t _2679 = (uint16_t)(22); + _curvea0[17] = _2679; + uint16_t _2680 = (uint16_t)(23); + _curvea0[18] = _2680; + uint16_t _2681 = (uint16_t)(24); + _curvea0[19] = _2681; + uint16_t _2682 = (uint16_t)(25); + _curvea0[20] = _2682; + uint16_t _2683 = (uint16_t)(25); + _curvea0[21] = _2683; + uint16_t _2684 = (uint16_t)(26); + _curvea0[22] = _2684; + uint16_t _2685 = (uint16_t)(27); + _curvea0[23] = _2685; + uint16_t _2686 = (uint16_t)(27); + _curvea0[24] = _2686; + uint16_t _2687 = (uint16_t)(28); + _curvea0[25] = _2687; + uint16_t _2688 = (uint16_t)(29); + _curvea0[26] = _2688; + uint16_t _2689 = (uint16_t)(29); + _curvea0[27] = _2689; + uint16_t _2690 = (uint16_t)(30); + _curvea0[28] = _2690; + uint16_t _2691 = (uint16_t)(31); + _curvea0[29] = _2691; + uint16_t _2692 = (uint16_t)(31); + _curvea0[30] = _2692; + uint16_t _2693 = (uint16_t)(32); + _curvea0[31] = _2693; + uint16_t _2694 = (uint16_t)(33); + _curvea0[32] = _2694; + uint16_t _2695 = (uint16_t)(33); + _curvea0[33] = _2695; + uint16_t _2696 = (uint16_t)(34); + _curvea0[34] = _2696; + uint16_t _2697 = (uint16_t)(34); + _curvea0[35] = _2697; + uint16_t _2698 = (uint16_t)(35); + _curvea0[36] = _2698; + uint16_t _2699 = (uint16_t)(36); + _curvea0[37] = _2699; + uint16_t _2700 = (uint16_t)(36); + _curvea0[38] = _2700; + uint16_t _2701 = (uint16_t)(37); + _curvea0[39] = _2701; + uint16_t _2702 = (uint16_t)(37); + _curvea0[40] = _2702; + uint16_t _2703 = (uint16_t)(38); + _curvea0[41] = _2703; + uint16_t _2704 = (uint16_t)(39); + _curvea0[42] = _2704; + uint16_t _2705 = (uint16_t)(39); + _curvea0[43] = _2705; + uint16_t _2706 = (uint16_t)(40); + _curvea0[44] = _2706; + uint16_t _2707 = (uint16_t)(40); + _curvea0[45] = _2707; + uint16_t _2708 = (uint16_t)(41); + _curvea0[46] = _2708; + uint16_t _2709 = (uint16_t)(41); + _curvea0[47] = _2709; + uint16_t _2710 = (uint16_t)(42); + _curvea0[48] = _2710; + uint16_t _2711 = (uint16_t)(42); + _curvea0[49] = _2711; + uint16_t _2712 = (uint16_t)(43); + _curvea0[50] = _2712; + uint16_t _2713 = (uint16_t)(44); + _curvea0[51] = _2713; + uint16_t _2714 = (uint16_t)(44); + _curvea0[52] = _2714; + uint16_t _2715 = (uint16_t)(45); + _curvea0[53] = _2715; + uint16_t _2716 = (uint16_t)(45); + _curvea0[54] = _2716; + uint16_t _2717 = (uint16_t)(46); + _curvea0[55] = _2717; + uint16_t _2718 = (uint16_t)(46); + _curvea0[56] = _2718; + uint16_t _2719 = (uint16_t)(47); + _curvea0[57] = _2719; + uint16_t _2720 = (uint16_t)(47); + _curvea0[58] = _2720; + uint16_t _2721 = (uint16_t)(48); + _curvea0[59] = _2721; + uint16_t _2722 = (uint16_t)(48); + _curvea0[60] = _2722; + uint16_t _2723 = (uint16_t)(49); + _curvea0[61] = _2723; + uint16_t _2724 = (uint16_t)(49); + _curvea0[62] = _2724; + uint16_t _2725 = (uint16_t)(50); + _curvea0[63] = _2725; + uint16_t _2726 = (uint16_t)(50); + _curvea0[64] = _2726; + uint16_t _2727 = (uint16_t)(51); + _curvea0[65] = _2727; + uint16_t _2728 = (uint16_t)(51); + _curvea0[66] = _2728; + uint16_t _2729 = (uint16_t)(52); + _curvea0[67] = _2729; + uint16_t _2730 = (uint16_t)(52); + _curvea0[68] = _2730; + uint16_t _2731 = (uint16_t)(53); + _curvea0[69] = _2731; + uint16_t _2732 = (uint16_t)(53); + _curvea0[70] = _2732; + uint16_t _2733 = (uint16_t)(54); + _curvea0[71] = _2733; + uint16_t _2734 = (uint16_t)(54); + _curvea0[72] = _2734; + uint16_t _2735 = (uint16_t)(55); + _curvea0[73] = _2735; + uint16_t _2736 = (uint16_t)(55); + _curvea0[74] = _2736; + uint16_t _2737 = (uint16_t)(56); + _curvea0[75] = _2737; + uint16_t _2738 = (uint16_t)(56); + _curvea0[76] = _2738; + uint16_t _2739 = (uint16_t)(57); + _curvea0[77] = _2739; + uint16_t _2740 = (uint16_t)(57); + _curvea0[78] = _2740; + uint16_t _2741 = (uint16_t)(58); + _curvea0[79] = _2741; + uint16_t _2742 = (uint16_t)(58); + _curvea0[80] = _2742; + uint16_t _2743 = (uint16_t)(58); + _curvea0[81] = _2743; + uint16_t _2744 = (uint16_t)(59); + _curvea0[82] = _2744; + uint16_t _2745 = (uint16_t)(59); + _curvea0[83] = _2745; + uint16_t _2746 = (uint16_t)(60); + _curvea0[84] = _2746; + uint16_t _2747 = (uint16_t)(60); + _curvea0[85] = _2747; + uint16_t _2748 = (uint16_t)(61); + _curvea0[86] = _2748; + uint16_t _2749 = (uint16_t)(61); + _curvea0[87] = _2749; + uint16_t _2750 = (uint16_t)(62); + _curvea0[88] = _2750; + uint16_t _2751 = (uint16_t)(62); + _curvea0[89] = _2751; + uint16_t _2752 = (uint16_t)(63); + _curvea0[90] = _2752; + uint16_t _2753 = (uint16_t)(63); + _curvea0[91] = _2753; + uint16_t _2754 = (uint16_t)(64); + _curvea0[92] = _2754; + uint16_t _2755 = (uint16_t)(64); + _curvea0[93] = _2755; + uint16_t _2756 = (uint16_t)(64); + _curvea0[94] = _2756; + uint16_t _2757 = (uint16_t)(65); + _curvea0[95] = _2757; + uint16_t _2758 = (uint16_t)(65); + _curvea0[96] = _2758; + uint16_t _2759 = (uint16_t)(66); + _curvea0[97] = _2759; + uint16_t _2760 = (uint16_t)(66); + _curvea0[98] = _2760; + uint16_t _2761 = (uint16_t)(67); + _curvea0[99] = _2761; + uint16_t _2762 = (uint16_t)(67); + _curvea0[100] = _2762; + uint16_t _2763 = (uint16_t)(68); + _curvea0[101] = _2763; + uint16_t _2764 = (uint16_t)(68); + _curvea0[102] = _2764; + uint16_t _2765 = (uint16_t)(68); + _curvea0[103] = _2765; + uint16_t _2766 = (uint16_t)(69); + _curvea0[104] = _2766; + uint16_t _2767 = (uint16_t)(69); + _curvea0[105] = _2767; + uint16_t _2768 = (uint16_t)(70); + _curvea0[106] = _2768; + uint16_t _2769 = (uint16_t)(70); + _curvea0[107] = _2769; + uint16_t _2770 = (uint16_t)(71); + _curvea0[108] = _2770; + uint16_t _2771 = (uint16_t)(71); + _curvea0[109] = _2771; + uint16_t _2772 = (uint16_t)(71); + _curvea0[110] = _2772; + uint16_t _2773 = (uint16_t)(72); + _curvea0[111] = _2773; + uint16_t _2774 = (uint16_t)(72); + _curvea0[112] = _2774; + uint16_t _2775 = (uint16_t)(73); + _curvea0[113] = _2775; + uint16_t _2776 = (uint16_t)(73); + _curvea0[114] = _2776; + uint16_t _2777 = (uint16_t)(74); + _curvea0[115] = _2777; + uint16_t _2778 = (uint16_t)(74); + _curvea0[116] = _2778; + uint16_t _2779 = (uint16_t)(74); + _curvea0[117] = _2779; + uint16_t _2780 = (uint16_t)(75); + _curvea0[118] = _2780; + uint16_t _2781 = (uint16_t)(75); + _curvea0[119] = _2781; + uint16_t _2782 = (uint16_t)(76); + _curvea0[120] = _2782; + uint16_t _2783 = (uint16_t)(76); + _curvea0[121] = _2783; + uint16_t _2784 = (uint16_t)(77); + _curvea0[122] = _2784; + uint16_t _2785 = (uint16_t)(77); + _curvea0[123] = _2785; + uint16_t _2786 = (uint16_t)(77); + _curvea0[124] = _2786; + uint16_t _2787 = (uint16_t)(78); + _curvea0[125] = _2787; + uint16_t _2788 = (uint16_t)(78); + _curvea0[126] = _2788; + uint16_t _2789 = (uint16_t)(79); + _curvea0[127] = _2789; + uint16_t _2790 = (uint16_t)(79); + _curvea0[128] = _2790; + uint16_t _2791 = (uint16_t)(79); + _curvea0[129] = _2791; + uint16_t _2792 = (uint16_t)(80); + _curvea0[130] = _2792; + uint16_t _2793 = (uint16_t)(80); + _curvea0[131] = _2793; + uint16_t _2794 = (uint16_t)(81); + _curvea0[132] = _2794; + uint16_t _2795 = (uint16_t)(81); + _curvea0[133] = _2795; + uint16_t _2796 = (uint16_t)(82); + _curvea0[134] = _2796; + uint16_t _2797 = (uint16_t)(82); + _curvea0[135] = _2797; + uint16_t _2798 = (uint16_t)(82); + _curvea0[136] = _2798; + uint16_t _2799 = (uint16_t)(83); + _curvea0[137] = _2799; + uint16_t _2800 = (uint16_t)(83); + _curvea0[138] = _2800; + uint16_t _2801 = (uint16_t)(84); + _curvea0[139] = _2801; + uint16_t _2802 = (uint16_t)(84); + _curvea0[140] = _2802; + uint16_t _2803 = (uint16_t)(84); + _curvea0[141] = _2803; + uint16_t _2804 = (uint16_t)(85); + _curvea0[142] = _2804; + uint16_t _2805 = (uint16_t)(85); + _curvea0[143] = _2805; + uint16_t _2806 = (uint16_t)(86); + _curvea0[144] = _2806; + uint16_t _2807 = (uint16_t)(86); + _curvea0[145] = _2807; + uint16_t _2808 = (uint16_t)(86); + _curvea0[146] = _2808; + uint16_t _2809 = (uint16_t)(87); + _curvea0[147] = _2809; + uint16_t _2810 = (uint16_t)(87); + _curvea0[148] = _2810; + uint16_t _2811 = (uint16_t)(88); + _curvea0[149] = _2811; + uint16_t _2812 = (uint16_t)(88); + _curvea0[150] = _2812; + uint16_t _2813 = (uint16_t)(88); + _curvea0[151] = _2813; + uint16_t _2814 = (uint16_t)(89); + _curvea0[152] = _2814; + uint16_t _2815 = (uint16_t)(89); + _curvea0[153] = _2815; + uint16_t _2816 = (uint16_t)(90); + _curvea0[154] = _2816; + uint16_t _2817 = (uint16_t)(90); + _curvea0[155] = _2817; + uint16_t _2818 = (uint16_t)(90); + _curvea0[156] = _2818; + uint16_t _2819 = (uint16_t)(91); + _curvea0[157] = _2819; + uint16_t _2820 = (uint16_t)(91); + _curvea0[158] = _2820; + uint16_t _2821 = (uint16_t)(92); + _curvea0[159] = _2821; + uint16_t _2822 = (uint16_t)(92); + _curvea0[160] = _2822; + uint16_t _2823 = (uint16_t)(92); + _curvea0[161] = _2823; + uint16_t _2824 = (uint16_t)(93); + _curvea0[162] = _2824; + uint16_t _2825 = (uint16_t)(93); + _curvea0[163] = _2825; + uint16_t _2826 = (uint16_t)(93); + _curvea0[164] = _2826; + uint16_t _2827 = (uint16_t)(94); + _curvea0[165] = _2827; + uint16_t _2828 = (uint16_t)(94); + _curvea0[166] = _2828; + uint16_t _2829 = (uint16_t)(95); + _curvea0[167] = _2829; + uint16_t _2830 = (uint16_t)(95); + _curvea0[168] = _2830; + uint16_t _2831 = (uint16_t)(95); + _curvea0[169] = _2831; + uint16_t _2832 = (uint16_t)(96); + _curvea0[170] = _2832; + uint16_t _2833 = (uint16_t)(96); + _curvea0[171] = _2833; + uint16_t _2834 = (uint16_t)(97); + _curvea0[172] = _2834; + uint16_t _2835 = (uint16_t)(97); + _curvea0[173] = _2835; + uint16_t _2836 = (uint16_t)(97); + _curvea0[174] = _2836; + uint16_t _2837 = (uint16_t)(98); + _curvea0[175] = _2837; + uint16_t _2838 = (uint16_t)(98); + _curvea0[176] = _2838; + uint16_t _2839 = (uint16_t)(99); + _curvea0[177] = _2839; + uint16_t _2840 = (uint16_t)(99); + _curvea0[178] = _2840; + uint16_t _2841 = (uint16_t)(99); + _curvea0[179] = _2841; + uint16_t _2842 = (uint16_t)(100); + _curvea0[180] = _2842; + uint16_t _2843 = (uint16_t)(100); + _curvea0[181] = _2843; + uint16_t _2844 = (uint16_t)(100); + _curvea0[182] = _2844; + uint16_t _2845 = (uint16_t)(101); + _curvea0[183] = _2845; + uint16_t _2846 = (uint16_t)(101); + _curvea0[184] = _2846; + uint16_t _2847 = (uint16_t)(102); + _curvea0[185] = _2847; + uint16_t _2848 = (uint16_t)(102); + _curvea0[186] = _2848; + uint16_t _2849 = (uint16_t)(102); + _curvea0[187] = _2849; + uint16_t _2850 = (uint16_t)(103); + _curvea0[188] = _2850; + uint16_t _2851 = (uint16_t)(103); + _curvea0[189] = _2851; + uint16_t _2852 = (uint16_t)(103); + _curvea0[190] = _2852; + uint16_t _2853 = (uint16_t)(104); + _curvea0[191] = _2853; + uint16_t _2854 = (uint16_t)(104); + _curvea0[192] = _2854; + uint16_t _2855 = (uint16_t)(105); + _curvea0[193] = _2855; + uint16_t _2856 = (uint16_t)(105); + _curvea0[194] = _2856; + uint16_t _2857 = (uint16_t)(105); + _curvea0[195] = _2857; + uint16_t _2858 = (uint16_t)(106); + _curvea0[196] = _2858; + uint16_t _2859 = (uint16_t)(106); + _curvea0[197] = _2859; + uint16_t _2860 = (uint16_t)(106); + _curvea0[198] = _2860; + uint16_t _2861 = (uint16_t)(107); + _curvea0[199] = _2861; + uint16_t _2862 = (uint16_t)(107); + _curvea0[200] = _2862; + uint16_t _2863 = (uint16_t)(108); + _curvea0[201] = _2863; + uint16_t _2864 = (uint16_t)(108); + _curvea0[202] = _2864; + uint16_t _2865 = (uint16_t)(108); + _curvea0[203] = _2865; + uint16_t _2866 = (uint16_t)(109); + _curvea0[204] = _2866; + uint16_t _2867 = (uint16_t)(109); + _curvea0[205] = _2867; + uint16_t _2868 = (uint16_t)(109); + _curvea0[206] = _2868; + uint16_t _2869 = (uint16_t)(110); + _curvea0[207] = _2869; + uint16_t _2870 = (uint16_t)(110); + _curvea0[208] = _2870; + uint16_t _2871 = (uint16_t)(111); + _curvea0[209] = _2871; + uint16_t _2872 = (uint16_t)(111); + _curvea0[210] = _2872; + uint16_t _2873 = (uint16_t)(111); + _curvea0[211] = _2873; + uint16_t _2874 = (uint16_t)(112); + _curvea0[212] = _2874; + uint16_t _2875 = (uint16_t)(112); + _curvea0[213] = _2875; + uint16_t _2876 = (uint16_t)(112); + _curvea0[214] = _2876; + uint16_t _2877 = (uint16_t)(113); + _curvea0[215] = _2877; + uint16_t _2878 = (uint16_t)(113); + _curvea0[216] = _2878; + uint16_t _2879 = (uint16_t)(113); + _curvea0[217] = _2879; + uint16_t _2880 = (uint16_t)(114); + _curvea0[218] = _2880; + uint16_t _2881 = (uint16_t)(114); + _curvea0[219] = _2881; + uint16_t _2882 = (uint16_t)(115); + _curvea0[220] = _2882; + uint16_t _2883 = (uint16_t)(115); + _curvea0[221] = _2883; + uint16_t _2884 = (uint16_t)(115); + _curvea0[222] = _2884; + uint16_t _2885 = (uint16_t)(116); + _curvea0[223] = _2885; + uint16_t _2886 = (uint16_t)(116); + _curvea0[224] = _2886; + uint16_t _2887 = (uint16_t)(116); + _curvea0[225] = _2887; + uint16_t _2888 = (uint16_t)(117); + _curvea0[226] = _2888; + uint16_t _2889 = (uint16_t)(117); + _curvea0[227] = _2889; + uint16_t _2890 = (uint16_t)(117); + _curvea0[228] = _2890; + uint16_t _2891 = (uint16_t)(118); + _curvea0[229] = _2891; + uint16_t _2892 = (uint16_t)(118); + _curvea0[230] = _2892; + uint16_t _2893 = (uint16_t)(119); + _curvea0[231] = _2893; + uint16_t _2894 = (uint16_t)(119); + _curvea0[232] = _2894; + uint16_t _2895 = (uint16_t)(119); + _curvea0[233] = _2895; + uint16_t _2896 = (uint16_t)(120); + _curvea0[234] = _2896; + uint16_t _2897 = (uint16_t)(120); + _curvea0[235] = _2897; + uint16_t _2898 = (uint16_t)(120); + _curvea0[236] = _2898; + uint16_t _2899 = (uint16_t)(121); + _curvea0[237] = _2899; + uint16_t _2900 = (uint16_t)(121); + _curvea0[238] = _2900; + uint16_t _2901 = (uint16_t)(121); + _curvea0[239] = _2901; + uint16_t _2902 = (uint16_t)(122); + _curvea0[240] = _2902; + uint16_t _2903 = (uint16_t)(122); + _curvea0[241] = _2903; + uint16_t _2904 = (uint16_t)(123); + _curvea0[242] = _2904; + uint16_t _2905 = (uint16_t)(123); + _curvea0[243] = _2905; + uint16_t _2906 = (uint16_t)(123); + _curvea0[244] = _2906; + uint16_t _2907 = (uint16_t)(124); + _curvea0[245] = _2907; + uint16_t _2908 = (uint16_t)(124); + _curvea0[246] = _2908; + uint16_t _2909 = (uint16_t)(124); + _curvea0[247] = _2909; + uint16_t _2910 = (uint16_t)(125); + _curvea0[248] = _2910; + uint16_t _2911 = (uint16_t)(125); + _curvea0[249] = _2911; + uint16_t _2912 = (uint16_t)(125); + _curvea0[250] = _2912; + uint16_t _2913 = (uint16_t)(126); + _curvea0[251] = _2913; + uint16_t _2914 = (uint16_t)(126); + _curvea0[252] = _2914; + uint16_t _2915 = (uint16_t)(126); + _curvea0[253] = _2915; + uint16_t _2916 = (uint16_t)(127); + _curvea0[254] = _2916; + uint16_t _2917 = (uint16_t)(127); + _curvea0[255] = _2917; + uint16_t _2918 = (uint16_t)(128); + _curvea0[256] = _2918; + uint16_t _2919 = (uint16_t)(128); + _curvea0[257] = _2919; + uint16_t _2920 = (uint16_t)(128); + _curvea0[258] = _2920; + uint16_t _2921 = (uint16_t)(129); + _curvea0[259] = _2921; + uint16_t _2922 = (uint16_t)(129); + _curvea0[260] = _2922; + uint16_t _2923 = (uint16_t)(129); + _curvea0[261] = _2923; + uint16_t _2924 = (uint16_t)(130); + _curvea0[262] = _2924; + uint16_t _2925 = (uint16_t)(130); + _curvea0[263] = _2925; + uint16_t _2926 = (uint16_t)(130); + _curvea0[264] = _2926; + uint16_t _2927 = (uint16_t)(131); + _curvea0[265] = _2927; + uint16_t _2928 = (uint16_t)(131); + _curvea0[266] = _2928; + uint16_t _2929 = (uint16_t)(131); + _curvea0[267] = _2929; + uint16_t _2930 = (uint16_t)(132); + _curvea0[268] = _2930; + uint16_t _2931 = (uint16_t)(132); + _curvea0[269] = _2931; + uint16_t _2932 = (uint16_t)(132); + _curvea0[270] = _2932; + uint16_t _2933 = (uint16_t)(133); + _curvea0[271] = _2933; + uint16_t _2934 = (uint16_t)(133); + _curvea0[272] = _2934; + uint16_t _2935 = (uint16_t)(133); + _curvea0[273] = _2935; + uint16_t _2936 = (uint16_t)(134); + _curvea0[274] = _2936; + uint16_t _2937 = (uint16_t)(134); + _curvea0[275] = _2937; + uint16_t _2938 = (uint16_t)(134); + _curvea0[276] = _2938; + uint16_t _2939 = (uint16_t)(135); + _curvea0[277] = _2939; + uint16_t _2940 = (uint16_t)(135); + _curvea0[278] = _2940; + uint16_t _2941 = (uint16_t)(135); + _curvea0[279] = _2941; + uint16_t _2942 = (uint16_t)(136); + _curvea0[280] = _2942; + uint16_t _2943 = (uint16_t)(136); + _curvea0[281] = _2943; + uint16_t _2944 = (uint16_t)(136); + _curvea0[282] = _2944; + uint16_t _2945 = (uint16_t)(137); + _curvea0[283] = _2945; + uint16_t _2946 = (uint16_t)(137); + _curvea0[284] = _2946; + uint16_t _2947 = (uint16_t)(137); + _curvea0[285] = _2947; + uint16_t _2948 = (uint16_t)(138); + _curvea0[286] = _2948; + uint16_t _2949 = (uint16_t)(138); + _curvea0[287] = _2949; + uint16_t _2950 = (uint16_t)(138); + _curvea0[288] = _2950; + uint16_t _2951 = (uint16_t)(139); + _curvea0[289] = _2951; + uint16_t _2952 = (uint16_t)(139); + _curvea0[290] = _2952; + uint16_t _2953 = (uint16_t)(139); + _curvea0[291] = _2953; + uint16_t _2954 = (uint16_t)(140); + _curvea0[292] = _2954; + uint16_t _2955 = (uint16_t)(140); + _curvea0[293] = _2955; + uint16_t _2956 = (uint16_t)(140); + _curvea0[294] = _2956; + uint16_t _2957 = (uint16_t)(141); + _curvea0[295] = _2957; + uint16_t _2958 = (uint16_t)(141); + _curvea0[296] = _2958; + uint16_t _2959 = (uint16_t)(141); + _curvea0[297] = _2959; + uint16_t _2960 = (uint16_t)(141); + _curvea0[298] = _2960; + uint16_t _2961 = (uint16_t)(142); + _curvea0[299] = _2961; + uint16_t _2962 = (uint16_t)(142); + _curvea0[300] = _2962; + uint16_t _2963 = (uint16_t)(142); + _curvea0[301] = _2963; + uint16_t _2964 = (uint16_t)(143); + _curvea0[302] = _2964; + uint16_t _2965 = (uint16_t)(143); + _curvea0[303] = _2965; + uint16_t _2966 = (uint16_t)(143); + _curvea0[304] = _2966; + uint16_t _2967 = (uint16_t)(144); + _curvea0[305] = _2967; + uint16_t _2968 = (uint16_t)(144); + _curvea0[306] = _2968; + uint16_t _2969 = (uint16_t)(144); + _curvea0[307] = _2969; + uint16_t _2970 = (uint16_t)(145); + _curvea0[308] = _2970; + uint16_t _2971 = (uint16_t)(145); + _curvea0[309] = _2971; + uint16_t _2972 = (uint16_t)(145); + _curvea0[310] = _2972; + uint16_t _2973 = (uint16_t)(145); + _curvea0[311] = _2973; + uint16_t _2974 = (uint16_t)(146); + _curvea0[312] = _2974; + uint16_t _2975 = (uint16_t)(146); + _curvea0[313] = _2975; + uint16_t _2976 = (uint16_t)(146); + _curvea0[314] = _2976; + uint16_t _2977 = (uint16_t)(147); + _curvea0[315] = _2977; + uint16_t _2978 = (uint16_t)(147); + _curvea0[316] = _2978; + uint16_t _2979 = (uint16_t)(147); + _curvea0[317] = _2979; + uint16_t _2980 = (uint16_t)(148); + _curvea0[318] = _2980; + uint16_t _2981 = (uint16_t)(148); + _curvea0[319] = _2981; + uint16_t _2982 = (uint16_t)(148); + _curvea0[320] = _2982; + uint16_t _2983 = (uint16_t)(148); + _curvea0[321] = _2983; + uint16_t _2984 = (uint16_t)(149); + _curvea0[322] = _2984; + uint16_t _2985 = (uint16_t)(149); + _curvea0[323] = _2985; + uint16_t _2986 = (uint16_t)(149); + _curvea0[324] = _2986; + uint16_t _2987 = (uint16_t)(150); + _curvea0[325] = _2987; + uint16_t _2988 = (uint16_t)(150); + _curvea0[326] = _2988; + uint16_t _2989 = (uint16_t)(150); + _curvea0[327] = _2989; + uint16_t _2990 = (uint16_t)(150); + _curvea0[328] = _2990; + uint16_t _2991 = (uint16_t)(151); + _curvea0[329] = _2991; + uint16_t _2992 = (uint16_t)(151); + _curvea0[330] = _2992; + uint16_t _2993 = (uint16_t)(151); + _curvea0[331] = _2993; + uint16_t _2994 = (uint16_t)(152); + _curvea0[332] = _2994; + uint16_t _2995 = (uint16_t)(152); + _curvea0[333] = _2995; + uint16_t _2996 = (uint16_t)(152); + _curvea0[334] = _2996; + uint16_t _2997 = (uint16_t)(152); + _curvea0[335] = _2997; + uint16_t _2998 = (uint16_t)(153); + _curvea0[336] = _2998; + uint16_t _2999 = (uint16_t)(153); + _curvea0[337] = _2999; + uint16_t _3000 = (uint16_t)(153); + _curvea0[338] = _3000; + uint16_t _3001 = (uint16_t)(154); + _curvea0[339] = _3001; + uint16_t _3002 = (uint16_t)(154); + _curvea0[340] = _3002; + uint16_t _3003 = (uint16_t)(154); + _curvea0[341] = _3003; + uint16_t _3004 = (uint16_t)(154); + _curvea0[342] = _3004; + uint16_t _3005 = (uint16_t)(155); + _curvea0[343] = _3005; + uint16_t _3006 = (uint16_t)(155); + _curvea0[344] = _3006; + uint16_t _3007 = (uint16_t)(155); + _curvea0[345] = _3007; + uint16_t _3008 = (uint16_t)(156); + _curvea0[346] = _3008; + uint16_t _3009 = (uint16_t)(156); + _curvea0[347] = _3009; + uint16_t _3010 = (uint16_t)(156); + _curvea0[348] = _3010; + uint16_t _3011 = (uint16_t)(156); + _curvea0[349] = _3011; + uint16_t _3012 = (uint16_t)(157); + _curvea0[350] = _3012; + uint16_t _3013 = (uint16_t)(157); + _curvea0[351] = _3013; + uint16_t _3014 = (uint16_t)(157); + _curvea0[352] = _3014; + uint16_t _3015 = (uint16_t)(157); + _curvea0[353] = _3015; + uint16_t _3016 = (uint16_t)(158); + _curvea0[354] = _3016; + uint16_t _3017 = (uint16_t)(158); + _curvea0[355] = _3017; + uint16_t _3018 = (uint16_t)(158); + _curvea0[356] = _3018; + uint16_t _3019 = (uint16_t)(159); + _curvea0[357] = _3019; + uint16_t _3020 = (uint16_t)(159); + _curvea0[358] = _3020; + uint16_t _3021 = (uint16_t)(159); + _curvea0[359] = _3021; + uint16_t _3022 = (uint16_t)(159); + _curvea0[360] = _3022; + uint16_t _3023 = (uint16_t)(160); + _curvea0[361] = _3023; + uint16_t _3024 = (uint16_t)(160); + _curvea0[362] = _3024; + uint16_t _3025 = (uint16_t)(160); + _curvea0[363] = _3025; + uint16_t _3026 = (uint16_t)(160); + _curvea0[364] = _3026; + uint16_t _3027 = (uint16_t)(161); + _curvea0[365] = _3027; + uint16_t _3028 = (uint16_t)(161); + _curvea0[366] = _3028; + uint16_t _3029 = (uint16_t)(161); + _curvea0[367] = _3029; + uint16_t _3030 = (uint16_t)(161); + _curvea0[368] = _3030; + uint16_t _3031 = (uint16_t)(162); + _curvea0[369] = _3031; + uint16_t _3032 = (uint16_t)(162); + _curvea0[370] = _3032; + uint16_t _3033 = (uint16_t)(162); + _curvea0[371] = _3033; + uint16_t _3034 = (uint16_t)(162); + _curvea0[372] = _3034; + uint16_t _3035 = (uint16_t)(163); + _curvea0[373] = _3035; + uint16_t _3036 = (uint16_t)(163); + _curvea0[374] = _3036; + uint16_t _3037 = (uint16_t)(163); + _curvea0[375] = _3037; + uint16_t _3038 = (uint16_t)(163); + _curvea0[376] = _3038; + uint16_t _3039 = (uint16_t)(164); + _curvea0[377] = _3039; + uint16_t _3040 = (uint16_t)(164); + _curvea0[378] = _3040; + uint16_t _3041 = (uint16_t)(164); + _curvea0[379] = _3041; + uint16_t _3042 = (uint16_t)(164); + _curvea0[380] = _3042; + uint16_t _3043 = (uint16_t)(165); + _curvea0[381] = _3043; + uint16_t _3044 = (uint16_t)(165); + _curvea0[382] = _3044; + uint16_t _3045 = (uint16_t)(165); + _curvea0[383] = _3045; + uint16_t _3046 = (uint16_t)(166); + _curvea0[384] = _3046; + uint16_t _3047 = (uint16_t)(166); + _curvea0[385] = _3047; + uint16_t _3048 = (uint16_t)(166); + _curvea0[386] = _3048; + uint16_t _3049 = (uint16_t)(166); + _curvea0[387] = _3049; + uint16_t _3050 = (uint16_t)(167); + _curvea0[388] = _3050; + uint16_t _3051 = (uint16_t)(167); + _curvea0[389] = _3051; + uint16_t _3052 = (uint16_t)(167); + _curvea0[390] = _3052; + uint16_t _3053 = (uint16_t)(167); + _curvea0[391] = _3053; + uint16_t _3054 = (uint16_t)(167); + _curvea0[392] = _3054; + uint16_t _3055 = (uint16_t)(168); + _curvea0[393] = _3055; + uint16_t _3056 = (uint16_t)(168); + _curvea0[394] = _3056; + uint16_t _3057 = (uint16_t)(168); + _curvea0[395] = _3057; + uint16_t _3058 = (uint16_t)(168); + _curvea0[396] = _3058; + uint16_t _3059 = (uint16_t)(169); + _curvea0[397] = _3059; + uint16_t _3060 = (uint16_t)(169); + _curvea0[398] = _3060; + uint16_t _3061 = (uint16_t)(169); + _curvea0[399] = _3061; + uint16_t _3062 = (uint16_t)(169); + _curvea0[400] = _3062; + uint16_t _3063 = (uint16_t)(170); + _curvea0[401] = _3063; + uint16_t _3064 = (uint16_t)(170); + _curvea0[402] = _3064; + uint16_t _3065 = (uint16_t)(170); + _curvea0[403] = _3065; + uint16_t _3066 = (uint16_t)(170); + _curvea0[404] = _3066; + uint16_t _3067 = (uint16_t)(171); + _curvea0[405] = _3067; + uint16_t _3068 = (uint16_t)(171); + _curvea0[406] = _3068; + uint16_t _3069 = (uint16_t)(171); + _curvea0[407] = _3069; + uint16_t _3070 = (uint16_t)(171); + _curvea0[408] = _3070; + uint16_t _3071 = (uint16_t)(172); + _curvea0[409] = _3071; + uint16_t _3072 = (uint16_t)(172); + _curvea0[410] = _3072; + uint16_t _3073 = (uint16_t)(172); + _curvea0[411] = _3073; + uint16_t _3074 = (uint16_t)(172); + _curvea0[412] = _3074; + uint16_t _3075 = (uint16_t)(173); + _curvea0[413] = _3075; + uint16_t _3076 = (uint16_t)(173); + _curvea0[414] = _3076; + uint16_t _3077 = (uint16_t)(173); + _curvea0[415] = _3077; + uint16_t _3078 = (uint16_t)(173); + _curvea0[416] = _3078; + uint16_t _3079 = (uint16_t)(173); + _curvea0[417] = _3079; + uint16_t _3080 = (uint16_t)(174); + _curvea0[418] = _3080; + uint16_t _3081 = (uint16_t)(174); + _curvea0[419] = _3081; + uint16_t _3082 = (uint16_t)(174); + _curvea0[420] = _3082; + uint16_t _3083 = (uint16_t)(174); + _curvea0[421] = _3083; + uint16_t _3084 = (uint16_t)(175); + _curvea0[422] = _3084; + uint16_t _3085 = (uint16_t)(175); + _curvea0[423] = _3085; + uint16_t _3086 = (uint16_t)(175); + _curvea0[424] = _3086; + uint16_t _3087 = (uint16_t)(175); + _curvea0[425] = _3087; + uint16_t _3088 = (uint16_t)(176); + _curvea0[426] = _3088; + uint16_t _3089 = (uint16_t)(176); + _curvea0[427] = _3089; + uint16_t _3090 = (uint16_t)(176); + _curvea0[428] = _3090; + uint16_t _3091 = (uint16_t)(176); + _curvea0[429] = _3091; + uint16_t _3092 = (uint16_t)(176); + _curvea0[430] = _3092; + uint16_t _3093 = (uint16_t)(177); + _curvea0[431] = _3093; + uint16_t _3094 = (uint16_t)(177); + _curvea0[432] = _3094; + uint16_t _3095 = (uint16_t)(177); + _curvea0[433] = _3095; + uint16_t _3096 = (uint16_t)(177); + _curvea0[434] = _3096; + uint16_t _3097 = (uint16_t)(178); + _curvea0[435] = _3097; + uint16_t _3098 = (uint16_t)(178); + _curvea0[436] = _3098; + uint16_t _3099 = (uint16_t)(178); + _curvea0[437] = _3099; + uint16_t _3100 = (uint16_t)(178); + _curvea0[438] = _3100; + uint16_t _3101 = (uint16_t)(178); + _curvea0[439] = _3101; + uint16_t _3102 = (uint16_t)(179); + _curvea0[440] = _3102; + uint16_t _3103 = (uint16_t)(179); + _curvea0[441] = _3103; + uint16_t _3104 = (uint16_t)(179); + _curvea0[442] = _3104; + uint16_t _3105 = (uint16_t)(179); + _curvea0[443] = _3105; + uint16_t _3106 = (uint16_t)(180); + _curvea0[444] = _3106; + uint16_t _3107 = (uint16_t)(180); + _curvea0[445] = _3107; + uint16_t _3108 = (uint16_t)(180); + _curvea0[446] = _3108; + uint16_t _3109 = (uint16_t)(180); + _curvea0[447] = _3109; + uint16_t _3110 = (uint16_t)(180); + _curvea0[448] = _3110; + uint16_t _3111 = (uint16_t)(181); + _curvea0[449] = _3111; + uint16_t _3112 = (uint16_t)(181); + _curvea0[450] = _3112; + uint16_t _3113 = (uint16_t)(181); + _curvea0[451] = _3113; + uint16_t _3114 = (uint16_t)(181); + _curvea0[452] = _3114; + uint16_t _3115 = (uint16_t)(181); + _curvea0[453] = _3115; + uint16_t _3116 = (uint16_t)(182); + _curvea0[454] = _3116; + uint16_t _3117 = (uint16_t)(182); + _curvea0[455] = _3117; + uint16_t _3118 = (uint16_t)(182); + _curvea0[456] = _3118; + uint16_t _3119 = (uint16_t)(182); + _curvea0[457] = _3119; + uint16_t _3120 = (uint16_t)(183); + _curvea0[458] = _3120; + uint16_t _3121 = (uint16_t)(183); + _curvea0[459] = _3121; + uint16_t _3122 = (uint16_t)(183); + _curvea0[460] = _3122; + uint16_t _3123 = (uint16_t)(183); + _curvea0[461] = _3123; + uint16_t _3124 = (uint16_t)(183); + _curvea0[462] = _3124; + uint16_t _3125 = (uint16_t)(184); + _curvea0[463] = _3125; + uint16_t _3126 = (uint16_t)(184); + _curvea0[464] = _3126; + uint16_t _3127 = (uint16_t)(184); + _curvea0[465] = _3127; + uint16_t _3128 = (uint16_t)(184); + _curvea0[466] = _3128; + uint16_t _3129 = (uint16_t)(184); + _curvea0[467] = _3129; + uint16_t _3130 = (uint16_t)(185); + _curvea0[468] = _3130; + uint16_t _3131 = (uint16_t)(185); + _curvea0[469] = _3131; + uint16_t _3132 = (uint16_t)(185); + _curvea0[470] = _3132; + uint16_t _3133 = (uint16_t)(185); + _curvea0[471] = _3133; + uint16_t _3134 = (uint16_t)(185); + _curvea0[472] = _3134; + uint16_t _3135 = (uint16_t)(186); + _curvea0[473] = _3135; + uint16_t _3136 = (uint16_t)(186); + _curvea0[474] = _3136; + uint16_t _3137 = (uint16_t)(186); + _curvea0[475] = _3137; + uint16_t _3138 = (uint16_t)(186); + _curvea0[476] = _3138; + uint16_t _3139 = (uint16_t)(187); + _curvea0[477] = _3139; + uint16_t _3140 = (uint16_t)(187); + _curvea0[478] = _3140; + uint16_t _3141 = (uint16_t)(187); + _curvea0[479] = _3141; + uint16_t _3142 = (uint16_t)(187); + _curvea0[480] = _3142; + uint16_t _3143 = (uint16_t)(187); + _curvea0[481] = _3143; + uint16_t _3144 = (uint16_t)(188); + _curvea0[482] = _3144; + uint16_t _3145 = (uint16_t)(188); + _curvea0[483] = _3145; + uint16_t _3146 = (uint16_t)(188); + _curvea0[484] = _3146; + uint16_t _3147 = (uint16_t)(188); + _curvea0[485] = _3147; + uint16_t _3148 = (uint16_t)(188); + _curvea0[486] = _3148; + uint16_t _3149 = (uint16_t)(189); + _curvea0[487] = _3149; + uint16_t _3150 = (uint16_t)(189); + _curvea0[488] = _3150; + uint16_t _3151 = (uint16_t)(189); + _curvea0[489] = _3151; + uint16_t _3152 = (uint16_t)(189); + _curvea0[490] = _3152; + uint16_t _3153 = (uint16_t)(189); + _curvea0[491] = _3153; + uint16_t _3154 = (uint16_t)(190); + _curvea0[492] = _3154; + uint16_t _3155 = (uint16_t)(190); + _curvea0[493] = _3155; + uint16_t _3156 = (uint16_t)(190); + _curvea0[494] = _3156; + uint16_t _3157 = (uint16_t)(190); + _curvea0[495] = _3157; + uint16_t _3158 = (uint16_t)(190); + _curvea0[496] = _3158; + uint16_t _3159 = (uint16_t)(190); + _curvea0[497] = _3159; + uint16_t _3160 = (uint16_t)(191); + _curvea0[498] = _3160; + uint16_t _3161 = (uint16_t)(191); + _curvea0[499] = _3161; + uint16_t _3162 = (uint16_t)(191); + _curvea0[500] = _3162; + uint16_t _3163 = (uint16_t)(191); + _curvea0[501] = _3163; + uint16_t _3164 = (uint16_t)(191); + _curvea0[502] = _3164; + uint16_t _3165 = (uint16_t)(192); + _curvea0[503] = _3165; + uint16_t _3166 = (uint16_t)(192); + _curvea0[504] = _3166; + uint16_t _3167 = (uint16_t)(192); + _curvea0[505] = _3167; + uint16_t _3168 = (uint16_t)(192); + _curvea0[506] = _3168; + uint16_t _3169 = (uint16_t)(192); + _curvea0[507] = _3169; + uint16_t _3170 = (uint16_t)(193); + _curvea0[508] = _3170; + uint16_t _3171 = (uint16_t)(193); + _curvea0[509] = _3171; + uint16_t _3172 = (uint16_t)(193); + _curvea0[510] = _3172; + uint16_t _3173 = (uint16_t)(193); + _curvea0[511] = _3173; + uint16_t _3174 = (uint16_t)(193); + _curvea0[512] = _3174; + uint16_t _3175 = (uint16_t)(194); + _curvea0[513] = _3175; + uint16_t _3176 = (uint16_t)(194); + _curvea0[514] = _3176; + uint16_t _3177 = (uint16_t)(194); + _curvea0[515] = _3177; + uint16_t _3178 = (uint16_t)(194); + _curvea0[516] = _3178; + uint16_t _3179 = (uint16_t)(194); + _curvea0[517] = _3179; + uint16_t _3180 = (uint16_t)(195); + _curvea0[518] = _3180; + uint16_t _3181 = (uint16_t)(195); + _curvea0[519] = _3181; + uint16_t _3182 = (uint16_t)(195); + _curvea0[520] = _3182; + uint16_t _3183 = (uint16_t)(195); + _curvea0[521] = _3183; + uint16_t _3184 = (uint16_t)(195); + _curvea0[522] = _3184; + uint16_t _3185 = (uint16_t)(195); + _curvea0[523] = _3185; + uint16_t _3186 = (uint16_t)(196); + _curvea0[524] = _3186; + uint16_t _3187 = (uint16_t)(196); + _curvea0[525] = _3187; + uint16_t _3188 = (uint16_t)(196); + _curvea0[526] = _3188; + uint16_t _3189 = (uint16_t)(196); + _curvea0[527] = _3189; + uint16_t _3190 = (uint16_t)(196); + _curvea0[528] = _3190; + uint16_t _3191 = (uint16_t)(197); + _curvea0[529] = _3191; + uint16_t _3192 = (uint16_t)(197); + _curvea0[530] = _3192; + uint16_t _3193 = (uint16_t)(197); + _curvea0[531] = _3193; + uint16_t _3194 = (uint16_t)(197); + _curvea0[532] = _3194; + uint16_t _3195 = (uint16_t)(197); + _curvea0[533] = _3195; + uint16_t _3196 = (uint16_t)(197); + _curvea0[534] = _3196; + uint16_t _3197 = (uint16_t)(198); + _curvea0[535] = _3197; + uint16_t _3198 = (uint16_t)(198); + _curvea0[536] = _3198; + uint16_t _3199 = (uint16_t)(198); + _curvea0[537] = _3199; + uint16_t _3200 = (uint16_t)(198); + _curvea0[538] = _3200; + uint16_t _3201 = (uint16_t)(198); + _curvea0[539] = _3201; + uint16_t _3202 = (uint16_t)(199); + _curvea0[540] = _3202; + uint16_t _3203 = (uint16_t)(199); + _curvea0[541] = _3203; + uint16_t _3204 = (uint16_t)(199); + _curvea0[542] = _3204; + uint16_t _3205 = (uint16_t)(199); + _curvea0[543] = _3205; + uint16_t _3206 = (uint16_t)(199); + _curvea0[544] = _3206; + uint16_t _3207 = (uint16_t)(199); + _curvea0[545] = _3207; + uint16_t _3208 = (uint16_t)(200); + _curvea0[546] = _3208; + uint16_t _3209 = (uint16_t)(200); + _curvea0[547] = _3209; + uint16_t _3210 = (uint16_t)(200); + _curvea0[548] = _3210; + uint16_t _3211 = (uint16_t)(200); + _curvea0[549] = _3211; + uint16_t _3212 = (uint16_t)(200); + _curvea0[550] = _3212; + uint16_t _3213 = (uint16_t)(200); + _curvea0[551] = _3213; + uint16_t _3214 = (uint16_t)(201); + _curvea0[552] = _3214; + uint16_t _3215 = (uint16_t)(201); + _curvea0[553] = _3215; + uint16_t _3216 = (uint16_t)(201); + _curvea0[554] = _3216; + uint16_t _3217 = (uint16_t)(201); + _curvea0[555] = _3217; + uint16_t _3218 = (uint16_t)(201); + _curvea0[556] = _3218; + uint16_t _3219 = (uint16_t)(202); + _curvea0[557] = _3219; + uint16_t _3220 = (uint16_t)(202); + _curvea0[558] = _3220; + uint16_t _3221 = (uint16_t)(202); + _curvea0[559] = _3221; + uint16_t _3222 = (uint16_t)(202); + _curvea0[560] = _3222; + uint16_t _3223 = (uint16_t)(202); + _curvea0[561] = _3223; + uint16_t _3224 = (uint16_t)(202); + _curvea0[562] = _3224; + uint16_t _3225 = (uint16_t)(203); + _curvea0[563] = _3225; + uint16_t _3226 = (uint16_t)(203); + _curvea0[564] = _3226; + uint16_t _3227 = (uint16_t)(203); + _curvea0[565] = _3227; + uint16_t _3228 = (uint16_t)(203); + _curvea0[566] = _3228; + uint16_t _3229 = (uint16_t)(203); + _curvea0[567] = _3229; + uint16_t _3230 = (uint16_t)(203); + _curvea0[568] = _3230; + uint16_t _3231 = (uint16_t)(204); + _curvea0[569] = _3231; + uint16_t _3232 = (uint16_t)(204); + _curvea0[570] = _3232; + uint16_t _3233 = (uint16_t)(204); + _curvea0[571] = _3233; + uint16_t _3234 = (uint16_t)(204); + _curvea0[572] = _3234; + uint16_t _3235 = (uint16_t)(204); + _curvea0[573] = _3235; + uint16_t _3236 = (uint16_t)(204); + _curvea0[574] = _3236; + uint16_t _3237 = (uint16_t)(205); + _curvea0[575] = _3237; + uint16_t _3238 = (uint16_t)(205); + _curvea0[576] = _3238; + uint16_t _3239 = (uint16_t)(205); + _curvea0[577] = _3239; + uint16_t _3240 = (uint16_t)(205); + _curvea0[578] = _3240; + uint16_t _3241 = (uint16_t)(205); + _curvea0[579] = _3241; + uint16_t _3242 = (uint16_t)(205); + _curvea0[580] = _3242; + uint16_t _3243 = (uint16_t)(206); + _curvea0[581] = _3243; + uint16_t _3244 = (uint16_t)(206); + _curvea0[582] = _3244; + uint16_t _3245 = (uint16_t)(206); + _curvea0[583] = _3245; + uint16_t _3246 = (uint16_t)(206); + _curvea0[584] = _3246; + uint16_t _3247 = (uint16_t)(206); + _curvea0[585] = _3247; + uint16_t _3248 = (uint16_t)(206); + _curvea0[586] = _3248; + uint16_t _3249 = (uint16_t)(207); + _curvea0[587] = _3249; + uint16_t _3250 = (uint16_t)(207); + _curvea0[588] = _3250; + uint16_t _3251 = (uint16_t)(207); + _curvea0[589] = _3251; + uint16_t _3252 = (uint16_t)(207); + _curvea0[590] = _3252; + uint16_t _3253 = (uint16_t)(207); + _curvea0[591] = _3253; + uint16_t _3254 = (uint16_t)(207); + _curvea0[592] = _3254; + uint16_t _3255 = (uint16_t)(208); + _curvea0[593] = _3255; + uint16_t _3256 = (uint16_t)(208); + _curvea0[594] = _3256; + uint16_t _3257 = (uint16_t)(208); + _curvea0[595] = _3257; + uint16_t _3258 = (uint16_t)(208); + _curvea0[596] = _3258; + uint16_t _3259 = (uint16_t)(208); + _curvea0[597] = _3259; + uint16_t _3260 = (uint16_t)(208); + _curvea0[598] = _3260; + uint16_t _3261 = (uint16_t)(209); + _curvea0[599] = _3261; + uint16_t _3262 = (uint16_t)(209); + _curvea0[600] = _3262; + uint16_t _3263 = (uint16_t)(209); + _curvea0[601] = _3263; + uint16_t _3264 = (uint16_t)(209); + _curvea0[602] = _3264; + uint16_t _3265 = (uint16_t)(209); + _curvea0[603] = _3265; + uint16_t _3266 = (uint16_t)(209); + _curvea0[604] = _3266; + uint16_t _3267 = (uint16_t)(209); + _curvea0[605] = _3267; + uint16_t _3268 = (uint16_t)(210); + _curvea0[606] = _3268; + uint16_t _3269 = (uint16_t)(210); + _curvea0[607] = _3269; + uint16_t _3270 = (uint16_t)(210); + _curvea0[608] = _3270; + uint16_t _3271 = (uint16_t)(210); + _curvea0[609] = _3271; + uint16_t _3272 = (uint16_t)(210); + _curvea0[610] = _3272; + uint16_t _3273 = (uint16_t)(210); + _curvea0[611] = _3273; + uint16_t _3274 = (uint16_t)(211); + _curvea0[612] = _3274; + uint16_t _3275 = (uint16_t)(211); + _curvea0[613] = _3275; + uint16_t _3276 = (uint16_t)(211); + _curvea0[614] = _3276; + uint16_t _3277 = (uint16_t)(211); + _curvea0[615] = _3277; + uint16_t _3278 = (uint16_t)(211); + _curvea0[616] = _3278; + uint16_t _3279 = (uint16_t)(211); + _curvea0[617] = _3279; + uint16_t _3280 = (uint16_t)(211); + _curvea0[618] = _3280; + uint16_t _3281 = (uint16_t)(212); + _curvea0[619] = _3281; + uint16_t _3282 = (uint16_t)(212); + _curvea0[620] = _3282; + uint16_t _3283 = (uint16_t)(212); + _curvea0[621] = _3283; + uint16_t _3284 = (uint16_t)(212); + _curvea0[622] = _3284; + uint16_t _3285 = (uint16_t)(212); + _curvea0[623] = _3285; + uint16_t _3286 = (uint16_t)(212); + _curvea0[624] = _3286; + uint16_t _3287 = (uint16_t)(213); + _curvea0[625] = _3287; + uint16_t _3288 = (uint16_t)(213); + _curvea0[626] = _3288; + uint16_t _3289 = (uint16_t)(213); + _curvea0[627] = _3289; + uint16_t _3290 = (uint16_t)(213); + _curvea0[628] = _3290; + uint16_t _3291 = (uint16_t)(213); + _curvea0[629] = _3291; + uint16_t _3292 = (uint16_t)(213); + _curvea0[630] = _3292; + uint16_t _3293 = (uint16_t)(213); + _curvea0[631] = _3293; + uint16_t _3294 = (uint16_t)(214); + _curvea0[632] = _3294; + uint16_t _3295 = (uint16_t)(214); + _curvea0[633] = _3295; + uint16_t _3296 = (uint16_t)(214); + _curvea0[634] = _3296; + uint16_t _3297 = (uint16_t)(214); + _curvea0[635] = _3297; + uint16_t _3298 = (uint16_t)(214); + _curvea0[636] = _3298; + uint16_t _3299 = (uint16_t)(214); + _curvea0[637] = _3299; + uint16_t _3300 = (uint16_t)(214); + _curvea0[638] = _3300; + uint16_t _3301 = (uint16_t)(215); + _curvea0[639] = _3301; + uint16_t _3302 = (uint16_t)(215); + _curvea0[640] = _3302; + uint16_t _3303 = (uint16_t)(215); + _curvea0[641] = _3303; + uint16_t _3304 = (uint16_t)(215); + _curvea0[642] = _3304; + uint16_t _3305 = (uint16_t)(215); + _curvea0[643] = _3305; + uint16_t _3306 = (uint16_t)(215); + _curvea0[644] = _3306; + uint16_t _3307 = (uint16_t)(216); + _curvea0[645] = _3307; + uint16_t _3308 = (uint16_t)(216); + _curvea0[646] = _3308; + uint16_t _3309 = (uint16_t)(216); + _curvea0[647] = _3309; + uint16_t _3310 = (uint16_t)(216); + _curvea0[648] = _3310; + uint16_t _3311 = (uint16_t)(216); + _curvea0[649] = _3311; + uint16_t _3312 = (uint16_t)(216); + _curvea0[650] = _3312; + uint16_t _3313 = (uint16_t)(216); + _curvea0[651] = _3313; + uint16_t _3314 = (uint16_t)(217); + _curvea0[652] = _3314; + uint16_t _3315 = (uint16_t)(217); + _curvea0[653] = _3315; + uint16_t _3316 = (uint16_t)(217); + _curvea0[654] = _3316; + uint16_t _3317 = (uint16_t)(217); + _curvea0[655] = _3317; + uint16_t _3318 = (uint16_t)(217); + _curvea0[656] = _3318; + uint16_t _3319 = (uint16_t)(217); + _curvea0[657] = _3319; + uint16_t _3320 = (uint16_t)(217); + _curvea0[658] = _3320; + uint16_t _3321 = (uint16_t)(218); + _curvea0[659] = _3321; + uint16_t _3322 = (uint16_t)(218); + _curvea0[660] = _3322; + uint16_t _3323 = (uint16_t)(218); + _curvea0[661] = _3323; + uint16_t _3324 = (uint16_t)(218); + _curvea0[662] = _3324; + uint16_t _3325 = (uint16_t)(218); + _curvea0[663] = _3325; + uint16_t _3326 = (uint16_t)(218); + _curvea0[664] = _3326; + uint16_t _3327 = (uint16_t)(218); + _curvea0[665] = _3327; + uint16_t _3328 = (uint16_t)(219); + _curvea0[666] = _3328; + uint16_t _3329 = (uint16_t)(219); + _curvea0[667] = _3329; + uint16_t _3330 = (uint16_t)(219); + _curvea0[668] = _3330; + uint16_t _3331 = (uint16_t)(219); + _curvea0[669] = _3331; + uint16_t _3332 = (uint16_t)(219); + _curvea0[670] = _3332; + uint16_t _3333 = (uint16_t)(219); + _curvea0[671] = _3333; + uint16_t _3334 = (uint16_t)(219); + _curvea0[672] = _3334; + uint16_t _3335 = (uint16_t)(220); + _curvea0[673] = _3335; + uint16_t _3336 = (uint16_t)(220); + _curvea0[674] = _3336; + uint16_t _3337 = (uint16_t)(220); + _curvea0[675] = _3337; + uint16_t _3338 = (uint16_t)(220); + _curvea0[676] = _3338; + uint16_t _3339 = (uint16_t)(220); + _curvea0[677] = _3339; + uint16_t _3340 = (uint16_t)(220); + _curvea0[678] = _3340; + uint16_t _3341 = (uint16_t)(220); + _curvea0[679] = _3341; + uint16_t _3342 = (uint16_t)(220); + _curvea0[680] = _3342; + uint16_t _3343 = (uint16_t)(221); + _curvea0[681] = _3343; + uint16_t _3344 = (uint16_t)(221); + _curvea0[682] = _3344; + uint16_t _3345 = (uint16_t)(221); + _curvea0[683] = _3345; + uint16_t _3346 = (uint16_t)(221); + _curvea0[684] = _3346; + uint16_t _3347 = (uint16_t)(221); + _curvea0[685] = _3347; + uint16_t _3348 = (uint16_t)(221); + _curvea0[686] = _3348; + uint16_t _3349 = (uint16_t)(221); + _curvea0[687] = _3349; + uint16_t _3350 = (uint16_t)(222); + _curvea0[688] = _3350; + uint16_t _3351 = (uint16_t)(222); + _curvea0[689] = _3351; + uint16_t _3352 = (uint16_t)(222); + _curvea0[690] = _3352; + uint16_t _3353 = (uint16_t)(222); + _curvea0[691] = _3353; + uint16_t _3354 = (uint16_t)(222); + _curvea0[692] = _3354; + uint16_t _3355 = (uint16_t)(222); + _curvea0[693] = _3355; + uint16_t _3356 = (uint16_t)(222); + _curvea0[694] = _3356; + uint16_t _3357 = (uint16_t)(223); + _curvea0[695] = _3357; + uint16_t _3358 = (uint16_t)(223); + _curvea0[696] = _3358; + uint16_t _3359 = (uint16_t)(223); + _curvea0[697] = _3359; + uint16_t _3360 = (uint16_t)(223); + _curvea0[698] = _3360; + uint16_t _3361 = (uint16_t)(223); + _curvea0[699] = _3361; + uint16_t _3362 = (uint16_t)(223); + _curvea0[700] = _3362; + uint16_t _3363 = (uint16_t)(223); + _curvea0[701] = _3363; + uint16_t _3364 = (uint16_t)(223); + _curvea0[702] = _3364; + uint16_t _3365 = (uint16_t)(224); + _curvea0[703] = _3365; + uint16_t _3366 = (uint16_t)(224); + _curvea0[704] = _3366; + uint16_t _3367 = (uint16_t)(224); + _curvea0[705] = _3367; + uint16_t _3368 = (uint16_t)(224); + _curvea0[706] = _3368; + uint16_t _3369 = (uint16_t)(224); + _curvea0[707] = _3369; + uint16_t _3370 = (uint16_t)(224); + _curvea0[708] = _3370; + uint16_t _3371 = (uint16_t)(224); + _curvea0[709] = _3371; + uint16_t _3372 = (uint16_t)(224); + _curvea0[710] = _3372; + uint16_t _3373 = (uint16_t)(225); + _curvea0[711] = _3373; + uint16_t _3374 = (uint16_t)(225); + _curvea0[712] = _3374; + uint16_t _3375 = (uint16_t)(225); + _curvea0[713] = _3375; + uint16_t _3376 = (uint16_t)(225); + _curvea0[714] = _3376; + uint16_t _3377 = (uint16_t)(225); + _curvea0[715] = _3377; + uint16_t _3378 = (uint16_t)(225); + _curvea0[716] = _3378; + uint16_t _3379 = (uint16_t)(225); + _curvea0[717] = _3379; + uint16_t _3380 = (uint16_t)(226); + _curvea0[718] = _3380; + uint16_t _3381 = (uint16_t)(226); + _curvea0[719] = _3381; + uint16_t _3382 = (uint16_t)(226); + _curvea0[720] = _3382; + uint16_t _3383 = (uint16_t)(226); + _curvea0[721] = _3383; + uint16_t _3384 = (uint16_t)(226); + _curvea0[722] = _3384; + uint16_t _3385 = (uint16_t)(226); + _curvea0[723] = _3385; + uint16_t _3386 = (uint16_t)(226); + _curvea0[724] = _3386; + uint16_t _3387 = (uint16_t)(226); + _curvea0[725] = _3387; + uint16_t _3388 = (uint16_t)(227); + _curvea0[726] = _3388; + uint16_t _3389 = (uint16_t)(227); + _curvea0[727] = _3389; + uint16_t _3390 = (uint16_t)(227); + _curvea0[728] = _3390; + uint16_t _3391 = (uint16_t)(227); + _curvea0[729] = _3391; + uint16_t _3392 = (uint16_t)(227); + _curvea0[730] = _3392; + uint16_t _3393 = (uint16_t)(227); + _curvea0[731] = _3393; + uint16_t _3394 = (uint16_t)(227); + _curvea0[732] = _3394; + uint16_t _3395 = (uint16_t)(227); + _curvea0[733] = _3395; + uint16_t _3396 = (uint16_t)(228); + _curvea0[734] = _3396; + uint16_t _3397 = (uint16_t)(228); + _curvea0[735] = _3397; + uint16_t _3398 = (uint16_t)(228); + _curvea0[736] = _3398; + uint16_t _3399 = (uint16_t)(228); + _curvea0[737] = _3399; + uint16_t _3400 = (uint16_t)(228); + _curvea0[738] = _3400; + uint16_t _3401 = (uint16_t)(228); + _curvea0[739] = _3401; + uint16_t _3402 = (uint16_t)(228); + _curvea0[740] = _3402; + uint16_t _3403 = (uint16_t)(228); + _curvea0[741] = _3403; + uint16_t _3404 = (uint16_t)(228); + _curvea0[742] = _3404; + uint16_t _3405 = (uint16_t)(229); + _curvea0[743] = _3405; + uint16_t _3406 = (uint16_t)(229); + _curvea0[744] = _3406; + uint16_t _3407 = (uint16_t)(229); + _curvea0[745] = _3407; + uint16_t _3408 = (uint16_t)(229); + _curvea0[746] = _3408; + uint16_t _3409 = (uint16_t)(229); + _curvea0[747] = _3409; + uint16_t _3410 = (uint16_t)(229); + _curvea0[748] = _3410; + uint16_t _3411 = (uint16_t)(229); + _curvea0[749] = _3411; + uint16_t _3412 = (uint16_t)(229); + _curvea0[750] = _3412; + uint16_t _3413 = (uint16_t)(230); + _curvea0[751] = _3413; + uint16_t _3414 = (uint16_t)(230); + _curvea0[752] = _3414; + uint16_t _3415 = (uint16_t)(230); + _curvea0[753] = _3415; + uint16_t _3416 = (uint16_t)(230); + _curvea0[754] = _3416; + uint16_t _3417 = (uint16_t)(230); + _curvea0[755] = _3417; + uint16_t _3418 = (uint16_t)(230); + _curvea0[756] = _3418; + uint16_t _3419 = (uint16_t)(230); + _curvea0[757] = _3419; + uint16_t _3420 = (uint16_t)(230); + _curvea0[758] = _3420; + uint16_t _3421 = (uint16_t)(231); + _curvea0[759] = _3421; + uint16_t _3422 = (uint16_t)(231); + _curvea0[760] = _3422; + uint16_t _3423 = (uint16_t)(231); + _curvea0[761] = _3423; + uint16_t _3424 = (uint16_t)(231); + _curvea0[762] = _3424; + uint16_t _3425 = (uint16_t)(231); + _curvea0[763] = _3425; + uint16_t _3426 = (uint16_t)(231); + _curvea0[764] = _3426; + uint16_t _3427 = (uint16_t)(231); + _curvea0[765] = _3427; + uint16_t _3428 = (uint16_t)(231); + _curvea0[766] = _3428; + uint16_t _3429 = (uint16_t)(231); + _curvea0[767] = _3429; + uint16_t _3430 = (uint16_t)(232); + _curvea0[768] = _3430; + uint16_t _3431 = (uint16_t)(232); + _curvea0[769] = _3431; + uint16_t _3432 = (uint16_t)(232); + _curvea0[770] = _3432; + uint16_t _3433 = (uint16_t)(232); + _curvea0[771] = _3433; + uint16_t _3434 = (uint16_t)(232); + _curvea0[772] = _3434; + uint16_t _3435 = (uint16_t)(232); + _curvea0[773] = _3435; + uint16_t _3436 = (uint16_t)(232); + _curvea0[774] = _3436; + uint16_t _3437 = (uint16_t)(232); + _curvea0[775] = _3437; + uint16_t _3438 = (uint16_t)(233); + _curvea0[776] = _3438; + uint16_t _3439 = (uint16_t)(233); + _curvea0[777] = _3439; + uint16_t _3440 = (uint16_t)(233); + _curvea0[778] = _3440; + uint16_t _3441 = (uint16_t)(233); + _curvea0[779] = _3441; + uint16_t _3442 = (uint16_t)(233); + _curvea0[780] = _3442; + uint16_t _3443 = (uint16_t)(233); + _curvea0[781] = _3443; + uint16_t _3444 = (uint16_t)(233); + _curvea0[782] = _3444; + uint16_t _3445 = (uint16_t)(233); + _curvea0[783] = _3445; + uint16_t _3446 = (uint16_t)(233); + _curvea0[784] = _3446; + uint16_t _3447 = (uint16_t)(234); + _curvea0[785] = _3447; + uint16_t _3448 = (uint16_t)(234); + _curvea0[786] = _3448; + uint16_t _3449 = (uint16_t)(234); + _curvea0[787] = _3449; + uint16_t _3450 = (uint16_t)(234); + _curvea0[788] = _3450; + uint16_t _3451 = (uint16_t)(234); + _curvea0[789] = _3451; + uint16_t _3452 = (uint16_t)(234); + _curvea0[790] = _3452; + uint16_t _3453 = (uint16_t)(234); + _curvea0[791] = _3453; + uint16_t _3454 = (uint16_t)(234); + _curvea0[792] = _3454; + uint16_t _3455 = (uint16_t)(234); + _curvea0[793] = _3455; + uint16_t _3456 = (uint16_t)(235); + _curvea0[794] = _3456; + uint16_t _3457 = (uint16_t)(235); + _curvea0[795] = _3457; + uint16_t _3458 = (uint16_t)(235); + _curvea0[796] = _3458; + uint16_t _3459 = (uint16_t)(235); + _curvea0[797] = _3459; + uint16_t _3460 = (uint16_t)(235); + _curvea0[798] = _3460; + uint16_t _3461 = (uint16_t)(235); + _curvea0[799] = _3461; + uint16_t _3462 = (uint16_t)(235); + _curvea0[800] = _3462; + uint16_t _3463 = (uint16_t)(235); + _curvea0[801] = _3463; + uint16_t _3464 = (uint16_t)(235); + _curvea0[802] = _3464; + uint16_t _3465 = (uint16_t)(236); + _curvea0[803] = _3465; + uint16_t _3466 = (uint16_t)(236); + _curvea0[804] = _3466; + uint16_t _3467 = (uint16_t)(236); + _curvea0[805] = _3467; + uint16_t _3468 = (uint16_t)(236); + _curvea0[806] = _3468; + uint16_t _3469 = (uint16_t)(236); + _curvea0[807] = _3469; + uint16_t _3470 = (uint16_t)(236); + _curvea0[808] = _3470; + uint16_t _3471 = (uint16_t)(236); + _curvea0[809] = _3471; + uint16_t _3472 = (uint16_t)(236); + _curvea0[810] = _3472; + uint16_t _3473 = (uint16_t)(236); + _curvea0[811] = _3473; + uint16_t _3474 = (uint16_t)(237); + _curvea0[812] = _3474; + uint16_t _3475 = (uint16_t)(237); + _curvea0[813] = _3475; + uint16_t _3476 = (uint16_t)(237); + _curvea0[814] = _3476; + uint16_t _3477 = (uint16_t)(237); + _curvea0[815] = _3477; + uint16_t _3478 = (uint16_t)(237); + _curvea0[816] = _3478; + uint16_t _3479 = (uint16_t)(237); + _curvea0[817] = _3479; + uint16_t _3480 = (uint16_t)(237); + _curvea0[818] = _3480; + uint16_t _3481 = (uint16_t)(237); + _curvea0[819] = _3481; + uint16_t _3482 = (uint16_t)(237); + _curvea0[820] = _3482; + uint16_t _3483 = (uint16_t)(237); + _curvea0[821] = _3483; + uint16_t _3484 = (uint16_t)(238); + _curvea0[822] = _3484; + uint16_t _3485 = (uint16_t)(238); + _curvea0[823] = _3485; + uint16_t _3486 = (uint16_t)(238); + _curvea0[824] = _3486; + uint16_t _3487 = (uint16_t)(238); + _curvea0[825] = _3487; + uint16_t _3488 = (uint16_t)(238); + _curvea0[826] = _3488; + uint16_t _3489 = (uint16_t)(238); + _curvea0[827] = _3489; + uint16_t _3490 = (uint16_t)(238); + _curvea0[828] = _3490; + uint16_t _3491 = (uint16_t)(238); + _curvea0[829] = _3491; + uint16_t _3492 = (uint16_t)(238); + _curvea0[830] = _3492; + uint16_t _3493 = (uint16_t)(239); + _curvea0[831] = _3493; + uint16_t _3494 = (uint16_t)(239); + _curvea0[832] = _3494; + uint16_t _3495 = (uint16_t)(239); + _curvea0[833] = _3495; + uint16_t _3496 = (uint16_t)(239); + _curvea0[834] = _3496; + uint16_t _3497 = (uint16_t)(239); + _curvea0[835] = _3497; + uint16_t _3498 = (uint16_t)(239); + _curvea0[836] = _3498; + uint16_t _3499 = (uint16_t)(239); + _curvea0[837] = _3499; + uint16_t _3500 = (uint16_t)(239); + _curvea0[838] = _3500; + uint16_t _3501 = (uint16_t)(239); + _curvea0[839] = _3501; + uint16_t _3502 = (uint16_t)(239); + _curvea0[840] = _3502; + uint16_t _3503 = (uint16_t)(240); + _curvea0[841] = _3503; + uint16_t _3504 = (uint16_t)(240); + _curvea0[842] = _3504; + uint16_t _3505 = (uint16_t)(240); + _curvea0[843] = _3505; + uint16_t _3506 = (uint16_t)(240); + _curvea0[844] = _3506; + uint16_t _3507 = (uint16_t)(240); + _curvea0[845] = _3507; + uint16_t _3508 = (uint16_t)(240); + _curvea0[846] = _3508; + uint16_t _3509 = (uint16_t)(240); + _curvea0[847] = _3509; + uint16_t _3510 = (uint16_t)(240); + _curvea0[848] = _3510; + uint16_t _3511 = (uint16_t)(240); + _curvea0[849] = _3511; + uint16_t _3512 = (uint16_t)(240); + _curvea0[850] = _3512; + uint16_t _3513 = (uint16_t)(241); + _curvea0[851] = _3513; + uint16_t _3514 = (uint16_t)(241); + _curvea0[852] = _3514; + uint16_t _3515 = (uint16_t)(241); + _curvea0[853] = _3515; + uint16_t _3516 = (uint16_t)(241); + _curvea0[854] = _3516; + uint16_t _3517 = (uint16_t)(241); + _curvea0[855] = _3517; + uint16_t _3518 = (uint16_t)(241); + _curvea0[856] = _3518; + uint16_t _3519 = (uint16_t)(241); + _curvea0[857] = _3519; + uint16_t _3520 = (uint16_t)(241); + _curvea0[858] = _3520; + uint16_t _3521 = (uint16_t)(241); + _curvea0[859] = _3521; + uint16_t _3522 = (uint16_t)(241); + _curvea0[860] = _3522; + uint16_t _3523 = (uint16_t)(242); + _curvea0[861] = _3523; + uint16_t _3524 = (uint16_t)(242); + _curvea0[862] = _3524; + uint16_t _3525 = (uint16_t)(242); + _curvea0[863] = _3525; + uint16_t _3526 = (uint16_t)(242); + _curvea0[864] = _3526; + uint16_t _3527 = (uint16_t)(242); + _curvea0[865] = _3527; + uint16_t _3528 = (uint16_t)(242); + _curvea0[866] = _3528; + uint16_t _3529 = (uint16_t)(242); + _curvea0[867] = _3529; + uint16_t _3530 = (uint16_t)(242); + _curvea0[868] = _3530; + uint16_t _3531 = (uint16_t)(242); + _curvea0[869] = _3531; + uint16_t _3532 = (uint16_t)(242); + _curvea0[870] = _3532; + uint16_t _3533 = (uint16_t)(243); + _curvea0[871] = _3533; + uint16_t _3534 = (uint16_t)(243); + _curvea0[872] = _3534; + uint16_t _3535 = (uint16_t)(243); + _curvea0[873] = _3535; + uint16_t _3536 = (uint16_t)(243); + _curvea0[874] = _3536; + uint16_t _3537 = (uint16_t)(243); + _curvea0[875] = _3537; + uint16_t _3538 = (uint16_t)(243); + _curvea0[876] = _3538; + uint16_t _3539 = (uint16_t)(243); + _curvea0[877] = _3539; + uint16_t _3540 = (uint16_t)(243); + _curvea0[878] = _3540; + uint16_t _3541 = (uint16_t)(243); + _curvea0[879] = _3541; + uint16_t _3542 = (uint16_t)(243); + _curvea0[880] = _3542; + uint16_t _3543 = (uint16_t)(244); + _curvea0[881] = _3543; + uint16_t _3544 = (uint16_t)(244); + _curvea0[882] = _3544; + uint16_t _3545 = (uint16_t)(244); + _curvea0[883] = _3545; + uint16_t _3546 = (uint16_t)(244); + _curvea0[884] = _3546; + uint16_t _3547 = (uint16_t)(244); + _curvea0[885] = _3547; + uint16_t _3548 = (uint16_t)(244); + _curvea0[886] = _3548; + uint16_t _3549 = (uint16_t)(244); + _curvea0[887] = _3549; + uint16_t _3550 = (uint16_t)(244); + _curvea0[888] = _3550; + uint16_t _3551 = (uint16_t)(244); + _curvea0[889] = _3551; + uint16_t _3552 = (uint16_t)(244); + _curvea0[890] = _3552; + uint16_t _3553 = (uint16_t)(244); + _curvea0[891] = _3553; + uint16_t _3554 = (uint16_t)(245); + _curvea0[892] = _3554; + uint16_t _3555 = (uint16_t)(245); + _curvea0[893] = _3555; + uint16_t _3556 = (uint16_t)(245); + _curvea0[894] = _3556; + uint16_t _3557 = (uint16_t)(245); + _curvea0[895] = _3557; + uint16_t _3558 = (uint16_t)(245); + _curvea0[896] = _3558; + uint16_t _3559 = (uint16_t)(245); + _curvea0[897] = _3559; + uint16_t _3560 = (uint16_t)(245); + _curvea0[898] = _3560; + uint16_t _3561 = (uint16_t)(245); + _curvea0[899] = _3561; + uint16_t _3562 = (uint16_t)(245); + _curvea0[900] = _3562; + uint16_t _3563 = (uint16_t)(245); + _curvea0[901] = _3563; + uint16_t _3564 = (uint16_t)(245); + _curvea0[902] = _3564; + uint16_t _3565 = (uint16_t)(246); + _curvea0[903] = _3565; + uint16_t _3566 = (uint16_t)(246); + _curvea0[904] = _3566; + uint16_t _3567 = (uint16_t)(246); + _curvea0[905] = _3567; + uint16_t _3568 = (uint16_t)(246); + _curvea0[906] = _3568; + uint16_t _3569 = (uint16_t)(246); + _curvea0[907] = _3569; + uint16_t _3570 = (uint16_t)(246); + _curvea0[908] = _3570; + uint16_t _3571 = (uint16_t)(246); + _curvea0[909] = _3571; + uint16_t _3572 = (uint16_t)(246); + _curvea0[910] = _3572; + uint16_t _3573 = (uint16_t)(246); + _curvea0[911] = _3573; + uint16_t _3574 = (uint16_t)(246); + _curvea0[912] = _3574; + uint16_t _3575 = (uint16_t)(246); + _curvea0[913] = _3575; + uint16_t _3576 = (uint16_t)(247); + _curvea0[914] = _3576; + uint16_t _3577 = (uint16_t)(247); + _curvea0[915] = _3577; + uint16_t _3578 = (uint16_t)(247); + _curvea0[916] = _3578; + uint16_t _3579 = (uint16_t)(247); + _curvea0[917] = _3579; + uint16_t _3580 = (uint16_t)(247); + _curvea0[918] = _3580; + uint16_t _3581 = (uint16_t)(247); + _curvea0[919] = _3581; + uint16_t _3582 = (uint16_t)(247); + _curvea0[920] = _3582; + uint16_t _3583 = (uint16_t)(247); + _curvea0[921] = _3583; + uint16_t _3584 = (uint16_t)(247); + _curvea0[922] = _3584; + uint16_t _3585 = (uint16_t)(247); + _curvea0[923] = _3585; + uint16_t _3586 = (uint16_t)(247); + _curvea0[924] = _3586; + uint16_t _3587 = (uint16_t)(248); + _curvea0[925] = _3587; + uint16_t _3588 = (uint16_t)(248); + _curvea0[926] = _3588; + uint16_t _3589 = (uint16_t)(248); + _curvea0[927] = _3589; + uint16_t _3590 = (uint16_t)(248); + _curvea0[928] = _3590; + uint16_t _3591 = (uint16_t)(248); + _curvea0[929] = _3591; + uint16_t _3592 = (uint16_t)(248); + _curvea0[930] = _3592; + uint16_t _3593 = (uint16_t)(248); + _curvea0[931] = _3593; + uint16_t _3594 = (uint16_t)(248); + _curvea0[932] = _3594; + uint16_t _3595 = (uint16_t)(248); + _curvea0[933] = _3595; + uint16_t _3596 = (uint16_t)(248); + _curvea0[934] = _3596; + uint16_t _3597 = (uint16_t)(248); + _curvea0[935] = _3597; + uint16_t _3598 = (uint16_t)(249); + _curvea0[936] = _3598; + uint16_t _3599 = (uint16_t)(249); + _curvea0[937] = _3599; + uint16_t _3600 = (uint16_t)(249); + _curvea0[938] = _3600; + uint16_t _3601 = (uint16_t)(249); + _curvea0[939] = _3601; + uint16_t _3602 = (uint16_t)(249); + _curvea0[940] = _3602; + uint16_t _3603 = (uint16_t)(249); + _curvea0[941] = _3603; + uint16_t _3604 = (uint16_t)(249); + _curvea0[942] = _3604; + uint16_t _3605 = (uint16_t)(249); + _curvea0[943] = _3605; + uint16_t _3606 = (uint16_t)(249); + _curvea0[944] = _3606; + uint16_t _3607 = (uint16_t)(249); + _curvea0[945] = _3607; + uint16_t _3608 = (uint16_t)(249); + _curvea0[946] = _3608; + uint16_t _3609 = (uint16_t)(249); + _curvea0[947] = _3609; + uint16_t _3610 = (uint16_t)(250); + _curvea0[948] = _3610; + uint16_t _3611 = (uint16_t)(250); + _curvea0[949] = _3611; + uint16_t _3612 = (uint16_t)(250); + _curvea0[950] = _3612; + uint16_t _3613 = (uint16_t)(250); + _curvea0[951] = _3613; + uint16_t _3614 = (uint16_t)(250); + _curvea0[952] = _3614; + uint16_t _3615 = (uint16_t)(250); + _curvea0[953] = _3615; + uint16_t _3616 = (uint16_t)(250); + _curvea0[954] = _3616; + uint16_t _3617 = (uint16_t)(250); + _curvea0[955] = _3617; + uint16_t _3618 = (uint16_t)(250); + _curvea0[956] = _3618; + uint16_t _3619 = (uint16_t)(250); + _curvea0[957] = _3619; + uint16_t _3620 = (uint16_t)(250); + _curvea0[958] = _3620; + uint16_t _3621 = (uint16_t)(250); + _curvea0[959] = _3621; + uint16_t _3622 = (uint16_t)(251); + _curvea0[960] = _3622; + uint16_t _3623 = (uint16_t)(251); + _curvea0[961] = _3623; + uint16_t _3624 = (uint16_t)(251); + _curvea0[962] = _3624; + uint16_t _3625 = (uint16_t)(251); + _curvea0[963] = _3625; + uint16_t _3626 = (uint16_t)(251); + _curvea0[964] = _3626; + uint16_t _3627 = (uint16_t)(251); + _curvea0[965] = _3627; + uint16_t _3628 = (uint16_t)(251); + _curvea0[966] = _3628; + uint16_t _3629 = (uint16_t)(251); + _curvea0[967] = _3629; + uint16_t _3630 = (uint16_t)(251); + _curvea0[968] = _3630; + uint16_t _3631 = (uint16_t)(251); + _curvea0[969] = _3631; + uint16_t _3632 = (uint16_t)(251); + _curvea0[970] = _3632; + uint16_t _3633 = (uint16_t)(251); + _curvea0[971] = _3633; + uint16_t _3634 = (uint16_t)(252); + _curvea0[972] = _3634; + uint16_t _3635 = (uint16_t)(252); + _curvea0[973] = _3635; + uint16_t _3636 = (uint16_t)(252); + _curvea0[974] = _3636; + uint16_t _3637 = (uint16_t)(252); + _curvea0[975] = _3637; + uint16_t _3638 = (uint16_t)(252); + _curvea0[976] = _3638; + uint16_t _3639 = (uint16_t)(252); + _curvea0[977] = _3639; + uint16_t _3640 = (uint16_t)(252); + _curvea0[978] = _3640; + uint16_t _3641 = (uint16_t)(252); + _curvea0[979] = _3641; + uint16_t _3642 = (uint16_t)(252); + _curvea0[980] = _3642; + uint16_t _3643 = (uint16_t)(252); + _curvea0[981] = _3643; + uint16_t _3644 = (uint16_t)(252); + _curvea0[982] = _3644; + uint16_t _3645 = (uint16_t)(252); + _curvea0[983] = _3645; + uint16_t _3646 = (uint16_t)(252); + _curvea0[984] = _3646; + uint16_t _3647 = (uint16_t)(253); + _curvea0[985] = _3647; + uint16_t _3648 = (uint16_t)(253); + _curvea0[986] = _3648; + uint16_t _3649 = (uint16_t)(253); + _curvea0[987] = _3649; + uint16_t _3650 = (uint16_t)(253); + _curvea0[988] = _3650; + uint16_t _3651 = (uint16_t)(253); + _curvea0[989] = _3651; + uint16_t _3652 = (uint16_t)(253); + _curvea0[990] = _3652; + uint16_t _3653 = (uint16_t)(253); + _curvea0[991] = _3653; + uint16_t _3654 = (uint16_t)(253); + _curvea0[992] = _3654; + uint16_t _3655 = (uint16_t)(253); + _curvea0[993] = _3655; + uint16_t _3656 = (uint16_t)(253); + _curvea0[994] = _3656; + uint16_t _3657 = (uint16_t)(253); + _curvea0[995] = _3657; + uint16_t _3658 = (uint16_t)(253); + _curvea0[996] = _3658; + uint16_t _3659 = (uint16_t)(253); + _curvea0[997] = _3659; + uint16_t _3660 = (uint16_t)(254); + _curvea0[998] = _3660; + uint16_t _3661 = (uint16_t)(254); + _curvea0[999] = _3661; + uint16_t _3662 = (uint16_t)(254); + _curvea0[1000] = _3662; + uint16_t _3663 = (uint16_t)(254); + _curvea0[1001] = _3663; + uint16_t _3664 = (uint16_t)(254); + _curvea0[1002] = _3664; + uint16_t _3665 = (uint16_t)(254); + _curvea0[1003] = _3665; + uint16_t _3666 = (uint16_t)(254); + _curvea0[1004] = _3666; + uint16_t _3667 = (uint16_t)(254); + _curvea0[1005] = _3667; + uint16_t _3668 = (uint16_t)(254); + _curvea0[1006] = _3668; + uint16_t _3669 = (uint16_t)(254); + _curvea0[1007] = _3669; + uint16_t _3670 = (uint16_t)(254); + _curvea0[1008] = _3670; + uint16_t _3671 = (uint16_t)(254); + _curvea0[1009] = _3671; + uint16_t _3672 = (uint16_t)(254); + _curvea0[1010] = _3672; + uint16_t _3673 = (uint16_t)(255); + _curvea0[1011] = _3673; + uint16_t _3674 = (uint16_t)(255); + _curvea0[1012] = _3674; + uint16_t _3675 = (uint16_t)(255); + _curvea0[1013] = _3675; + uint16_t _3676 = (uint16_t)(255); + _curvea0[1014] = _3676; + uint16_t _3677 = (uint16_t)(255); + _curvea0[1015] = _3677; + uint16_t _3678 = (uint16_t)(255); + _curvea0[1016] = _3678; + uint16_t _3679 = (uint16_t)(255); + _curvea0[1017] = _3679; + uint16_t _3680 = (uint16_t)(255); + _curvea0[1018] = _3680; + uint16_t _3681 = (uint16_t)(255); + _curvea0[1019] = _3681; + uint16_t _3682 = (uint16_t)(255); + _curvea0[1020] = _3682; + uint16_t _3683 = (uint16_t)(255); + _curvea0[1021] = _3683; + uint16_t _3684 = (uint16_t)(255); + _curvea0[1022] = _3684; + uint16_t _3685 = (uint16_t)(255); + _curvea0[1023] = _3685; + + int16_t _3686 = (int16_t)(1023); + int16_t _3687 = min(_corrected_stencil_1, _3686); + int16_t _3688 = (int16_t)(0); + int16_t _3689 = max(_3687, _3688); + uint16_t _3690 = (uint16_t)(_3689); + int32_t _3691 = (int32_t)(_3690); + uint16_t _3692 = ((const uint16_t *)_curvea0)[_3691]; + return _3692; +} + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_1(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_2 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _3709 = (uint16_t)(0); + _curvea0[0] = _3709; + uint16_t _3710 = (uint16_t)(4); + _curvea0[1] = _3710; + uint16_t _3711 = (uint16_t)(7); + _curvea0[2] = _3711; + uint16_t _3712 = (uint16_t)(8); + _curvea0[3] = _3712; + uint16_t _3713 = (uint16_t)(10); + _curvea0[4] = _3713; + uint16_t _3714 = (uint16_t)(11); + _curvea0[5] = _3714; + uint16_t _3715 = (uint16_t)(12); + _curvea0[6] = _3715; + uint16_t _3716 = (uint16_t)(13); + _curvea0[7] = _3716; + uint16_t _3717 = (uint16_t)(14); + _curvea0[8] = _3717; + uint16_t _3718 = (uint16_t)(15); + _curvea0[9] = _3718; + uint16_t _3719 = (uint16_t)(16); + _curvea0[10] = _3719; + uint16_t _3720 = (uint16_t)(17); + _curvea0[11] = _3720; + uint16_t _3721 = (uint16_t)(18); + _curvea0[12] = _3721; + uint16_t _3722 = (uint16_t)(19); + _curvea0[13] = _3722; + uint16_t _3723 = (uint16_t)(20); + _curvea0[14] = _3723; + uint16_t _3724 = (uint16_t)(21); + _curvea0[15] = _3724; + uint16_t _3725 = (uint16_t)(22); + _curvea0[16] = _3725; + uint16_t _3726 = (uint16_t)(22); + _curvea0[17] = _3726; + uint16_t _3727 = (uint16_t)(23); + _curvea0[18] = _3727; + uint16_t _3728 = (uint16_t)(24); + _curvea0[19] = _3728; + uint16_t _3729 = (uint16_t)(25); + _curvea0[20] = _3729; + uint16_t _3730 = (uint16_t)(25); + _curvea0[21] = _3730; + uint16_t _3731 = (uint16_t)(26); + _curvea0[22] = _3731; + uint16_t _3732 = (uint16_t)(27); + _curvea0[23] = _3732; + uint16_t _3733 = (uint16_t)(27); + _curvea0[24] = _3733; + uint16_t _3734 = (uint16_t)(28); + _curvea0[25] = _3734; + uint16_t _3735 = (uint16_t)(29); + _curvea0[26] = _3735; + uint16_t _3736 = (uint16_t)(29); + _curvea0[27] = _3736; + uint16_t _3737 = (uint16_t)(30); + _curvea0[28] = _3737; + uint16_t _3738 = (uint16_t)(31); + _curvea0[29] = _3738; + uint16_t _3739 = (uint16_t)(31); + _curvea0[30] = _3739; + uint16_t _3740 = (uint16_t)(32); + _curvea0[31] = _3740; + uint16_t _3741 = (uint16_t)(33); + _curvea0[32] = _3741; + uint16_t _3742 = (uint16_t)(33); + _curvea0[33] = _3742; + uint16_t _3743 = (uint16_t)(34); + _curvea0[34] = _3743; + uint16_t _3744 = (uint16_t)(34); + _curvea0[35] = _3744; + uint16_t _3745 = (uint16_t)(35); + _curvea0[36] = _3745; + uint16_t _3746 = (uint16_t)(36); + _curvea0[37] = _3746; + uint16_t _3747 = (uint16_t)(36); + _curvea0[38] = _3747; + uint16_t _3748 = (uint16_t)(37); + _curvea0[39] = _3748; + uint16_t _3749 = (uint16_t)(37); + _curvea0[40] = _3749; + uint16_t _3750 = (uint16_t)(38); + _curvea0[41] = _3750; + uint16_t _3751 = (uint16_t)(39); + _curvea0[42] = _3751; + uint16_t _3752 = (uint16_t)(39); + _curvea0[43] = _3752; + uint16_t _3753 = (uint16_t)(40); + _curvea0[44] = _3753; + uint16_t _3754 = (uint16_t)(40); + _curvea0[45] = _3754; + uint16_t _3755 = (uint16_t)(41); + _curvea0[46] = _3755; + uint16_t _3756 = (uint16_t)(41); + _curvea0[47] = _3756; + uint16_t _3757 = (uint16_t)(42); + _curvea0[48] = _3757; + uint16_t _3758 = (uint16_t)(42); + _curvea0[49] = _3758; + uint16_t _3759 = (uint16_t)(43); + _curvea0[50] = _3759; + uint16_t _3760 = (uint16_t)(44); + _curvea0[51] = _3760; + uint16_t _3761 = (uint16_t)(44); + _curvea0[52] = _3761; + uint16_t _3762 = (uint16_t)(45); + _curvea0[53] = _3762; + uint16_t _3763 = (uint16_t)(45); + _curvea0[54] = _3763; + uint16_t _3764 = (uint16_t)(46); + _curvea0[55] = _3764; + uint16_t _3765 = (uint16_t)(46); + _curvea0[56] = _3765; + uint16_t _3766 = (uint16_t)(47); + _curvea0[57] = _3766; + uint16_t _3767 = (uint16_t)(47); + _curvea0[58] = _3767; + uint16_t _3768 = (uint16_t)(48); + _curvea0[59] = _3768; + uint16_t _3769 = (uint16_t)(48); + _curvea0[60] = _3769; + uint16_t _3770 = (uint16_t)(49); + _curvea0[61] = _3770; + uint16_t _3771 = (uint16_t)(49); + _curvea0[62] = _3771; + uint16_t _3772 = (uint16_t)(50); + _curvea0[63] = _3772; + uint16_t _3773 = (uint16_t)(50); + _curvea0[64] = _3773; + uint16_t _3774 = (uint16_t)(51); + _curvea0[65] = _3774; + uint16_t _3775 = (uint16_t)(51); + _curvea0[66] = _3775; + uint16_t _3776 = (uint16_t)(52); + _curvea0[67] = _3776; + uint16_t _3777 = (uint16_t)(52); + _curvea0[68] = _3777; + uint16_t _3778 = (uint16_t)(53); + _curvea0[69] = _3778; + uint16_t _3779 = (uint16_t)(53); + _curvea0[70] = _3779; + uint16_t _3780 = (uint16_t)(54); + _curvea0[71] = _3780; + uint16_t _3781 = (uint16_t)(54); + _curvea0[72] = _3781; + uint16_t _3782 = (uint16_t)(55); + _curvea0[73] = _3782; + uint16_t _3783 = (uint16_t)(55); + _curvea0[74] = _3783; + uint16_t _3784 = (uint16_t)(56); + _curvea0[75] = _3784; + uint16_t _3785 = (uint16_t)(56); + _curvea0[76] = _3785; + uint16_t _3786 = (uint16_t)(57); + _curvea0[77] = _3786; + uint16_t _3787 = (uint16_t)(57); + _curvea0[78] = _3787; + uint16_t _3788 = (uint16_t)(58); + _curvea0[79] = _3788; + uint16_t _3789 = (uint16_t)(58); + _curvea0[80] = _3789; + uint16_t _3790 = (uint16_t)(58); + _curvea0[81] = _3790; + uint16_t _3791 = (uint16_t)(59); + _curvea0[82] = _3791; + uint16_t _3792 = (uint16_t)(59); + _curvea0[83] = _3792; + uint16_t _3793 = (uint16_t)(60); + _curvea0[84] = _3793; + uint16_t _3794 = (uint16_t)(60); + _curvea0[85] = _3794; + uint16_t _3795 = (uint16_t)(61); + _curvea0[86] = _3795; + uint16_t _3796 = (uint16_t)(61); + _curvea0[87] = _3796; + uint16_t _3797 = (uint16_t)(62); + _curvea0[88] = _3797; + uint16_t _3798 = (uint16_t)(62); + _curvea0[89] = _3798; + uint16_t _3799 = (uint16_t)(63); + _curvea0[90] = _3799; + uint16_t _3800 = (uint16_t)(63); + _curvea0[91] = _3800; + uint16_t _3801 = (uint16_t)(64); + _curvea0[92] = _3801; + uint16_t _3802 = (uint16_t)(64); + _curvea0[93] = _3802; + uint16_t _3803 = (uint16_t)(64); + _curvea0[94] = _3803; + uint16_t _3804 = (uint16_t)(65); + _curvea0[95] = _3804; + uint16_t _3805 = (uint16_t)(65); + _curvea0[96] = _3805; + uint16_t _3806 = (uint16_t)(66); + _curvea0[97] = _3806; + uint16_t _3807 = (uint16_t)(66); + _curvea0[98] = _3807; + uint16_t _3808 = (uint16_t)(67); + _curvea0[99] = _3808; + uint16_t _3809 = (uint16_t)(67); + _curvea0[100] = _3809; + uint16_t _3810 = (uint16_t)(68); + _curvea0[101] = _3810; + uint16_t _3811 = (uint16_t)(68); + _curvea0[102] = _3811; + uint16_t _3812 = (uint16_t)(68); + _curvea0[103] = _3812; + uint16_t _3813 = (uint16_t)(69); + _curvea0[104] = _3813; + uint16_t _3814 = (uint16_t)(69); + _curvea0[105] = _3814; + uint16_t _3815 = (uint16_t)(70); + _curvea0[106] = _3815; + uint16_t _3816 = (uint16_t)(70); + _curvea0[107] = _3816; + uint16_t _3817 = (uint16_t)(71); + _curvea0[108] = _3817; + uint16_t _3818 = (uint16_t)(71); + _curvea0[109] = _3818; + uint16_t _3819 = (uint16_t)(71); + _curvea0[110] = _3819; + uint16_t _3820 = (uint16_t)(72); + _curvea0[111] = _3820; + uint16_t _3821 = (uint16_t)(72); + _curvea0[112] = _3821; + uint16_t _3822 = (uint16_t)(73); + _curvea0[113] = _3822; + uint16_t _3823 = (uint16_t)(73); + _curvea0[114] = _3823; + uint16_t _3824 = (uint16_t)(74); + _curvea0[115] = _3824; + uint16_t _3825 = (uint16_t)(74); + _curvea0[116] = _3825; + uint16_t _3826 = (uint16_t)(74); + _curvea0[117] = _3826; + uint16_t _3827 = (uint16_t)(75); + _curvea0[118] = _3827; + uint16_t _3828 = (uint16_t)(75); + _curvea0[119] = _3828; + uint16_t _3829 = (uint16_t)(76); + _curvea0[120] = _3829; + uint16_t _3830 = (uint16_t)(76); + _curvea0[121] = _3830; + uint16_t _3831 = (uint16_t)(77); + _curvea0[122] = _3831; + uint16_t _3832 = (uint16_t)(77); + _curvea0[123] = _3832; + uint16_t _3833 = (uint16_t)(77); + _curvea0[124] = _3833; + uint16_t _3834 = (uint16_t)(78); + _curvea0[125] = _3834; + uint16_t _3835 = (uint16_t)(78); + _curvea0[126] = _3835; + uint16_t _3836 = (uint16_t)(79); + _curvea0[127] = _3836; + uint16_t _3837 = (uint16_t)(79); + _curvea0[128] = _3837; + uint16_t _3838 = (uint16_t)(79); + _curvea0[129] = _3838; + uint16_t _3839 = (uint16_t)(80); + _curvea0[130] = _3839; + uint16_t _3840 = (uint16_t)(80); + _curvea0[131] = _3840; + uint16_t _3841 = (uint16_t)(81); + _curvea0[132] = _3841; + uint16_t _3842 = (uint16_t)(81); + _curvea0[133] = _3842; + uint16_t _3843 = (uint16_t)(82); + _curvea0[134] = _3843; + uint16_t _3844 = (uint16_t)(82); + _curvea0[135] = _3844; + uint16_t _3845 = (uint16_t)(82); + _curvea0[136] = _3845; + uint16_t _3846 = (uint16_t)(83); + _curvea0[137] = _3846; + uint16_t _3847 = (uint16_t)(83); + _curvea0[138] = _3847; + uint16_t _3848 = (uint16_t)(84); + _curvea0[139] = _3848; + uint16_t _3849 = (uint16_t)(84); + _curvea0[140] = _3849; + uint16_t _3850 = (uint16_t)(84); + _curvea0[141] = _3850; + uint16_t _3851 = (uint16_t)(85); + _curvea0[142] = _3851; + uint16_t _3852 = (uint16_t)(85); + _curvea0[143] = _3852; + uint16_t _3853 = (uint16_t)(86); + _curvea0[144] = _3853; + uint16_t _3854 = (uint16_t)(86); + _curvea0[145] = _3854; + uint16_t _3855 = (uint16_t)(86); + _curvea0[146] = _3855; + uint16_t _3856 = (uint16_t)(87); + _curvea0[147] = _3856; + uint16_t _3857 = (uint16_t)(87); + _curvea0[148] = _3857; + uint16_t _3858 = (uint16_t)(88); + _curvea0[149] = _3858; + uint16_t _3859 = (uint16_t)(88); + _curvea0[150] = _3859; + uint16_t _3860 = (uint16_t)(88); + _curvea0[151] = _3860; + uint16_t _3861 = (uint16_t)(89); + _curvea0[152] = _3861; + uint16_t _3862 = (uint16_t)(89); + _curvea0[153] = _3862; + uint16_t _3863 = (uint16_t)(90); + _curvea0[154] = _3863; + uint16_t _3864 = (uint16_t)(90); + _curvea0[155] = _3864; + uint16_t _3865 = (uint16_t)(90); + _curvea0[156] = _3865; + uint16_t _3866 = (uint16_t)(91); + _curvea0[157] = _3866; + uint16_t _3867 = (uint16_t)(91); + _curvea0[158] = _3867; + uint16_t _3868 = (uint16_t)(92); + _curvea0[159] = _3868; + uint16_t _3869 = (uint16_t)(92); + _curvea0[160] = _3869; + uint16_t _3870 = (uint16_t)(92); + _curvea0[161] = _3870; + uint16_t _3871 = (uint16_t)(93); + _curvea0[162] = _3871; + uint16_t _3872 = (uint16_t)(93); + _curvea0[163] = _3872; + uint16_t _3873 = (uint16_t)(93); + _curvea0[164] = _3873; + uint16_t _3874 = (uint16_t)(94); + _curvea0[165] = _3874; + uint16_t _3875 = (uint16_t)(94); + _curvea0[166] = _3875; + uint16_t _3876 = (uint16_t)(95); + _curvea0[167] = _3876; + uint16_t _3877 = (uint16_t)(95); + _curvea0[168] = _3877; + uint16_t _3878 = (uint16_t)(95); + _curvea0[169] = _3878; + uint16_t _3879 = (uint16_t)(96); + _curvea0[170] = _3879; + uint16_t _3880 = (uint16_t)(96); + _curvea0[171] = _3880; + uint16_t _3881 = (uint16_t)(97); + _curvea0[172] = _3881; + uint16_t _3882 = (uint16_t)(97); + _curvea0[173] = _3882; + uint16_t _3883 = (uint16_t)(97); + _curvea0[174] = _3883; + uint16_t _3884 = (uint16_t)(98); + _curvea0[175] = _3884; + uint16_t _3885 = (uint16_t)(98); + _curvea0[176] = _3885; + uint16_t _3886 = (uint16_t)(99); + _curvea0[177] = _3886; + uint16_t _3887 = (uint16_t)(99); + _curvea0[178] = _3887; + uint16_t _3888 = (uint16_t)(99); + _curvea0[179] = _3888; + uint16_t _3889 = (uint16_t)(100); + _curvea0[180] = _3889; + uint16_t _3890 = (uint16_t)(100); + _curvea0[181] = _3890; + uint16_t _3891 = (uint16_t)(100); + _curvea0[182] = _3891; + uint16_t _3892 = (uint16_t)(101); + _curvea0[183] = _3892; + uint16_t _3893 = (uint16_t)(101); + _curvea0[184] = _3893; + uint16_t _3894 = (uint16_t)(102); + _curvea0[185] = _3894; + uint16_t _3895 = (uint16_t)(102); + _curvea0[186] = _3895; + uint16_t _3896 = (uint16_t)(102); + _curvea0[187] = _3896; + uint16_t _3897 = (uint16_t)(103); + _curvea0[188] = _3897; + uint16_t _3898 = (uint16_t)(103); + _curvea0[189] = _3898; + uint16_t _3899 = (uint16_t)(103); + _curvea0[190] = _3899; + uint16_t _3900 = (uint16_t)(104); + _curvea0[191] = _3900; + uint16_t _3901 = (uint16_t)(104); + _curvea0[192] = _3901; + uint16_t _3902 = (uint16_t)(105); + _curvea0[193] = _3902; + uint16_t _3903 = (uint16_t)(105); + _curvea0[194] = _3903; + uint16_t _3904 = (uint16_t)(105); + _curvea0[195] = _3904; + uint16_t _3905 = (uint16_t)(106); + _curvea0[196] = _3905; + uint16_t _3906 = (uint16_t)(106); + _curvea0[197] = _3906; + uint16_t _3907 = (uint16_t)(106); + _curvea0[198] = _3907; + uint16_t _3908 = (uint16_t)(107); + _curvea0[199] = _3908; + uint16_t _3909 = (uint16_t)(107); + _curvea0[200] = _3909; + uint16_t _3910 = (uint16_t)(108); + _curvea0[201] = _3910; + uint16_t _3911 = (uint16_t)(108); + _curvea0[202] = _3911; + uint16_t _3912 = (uint16_t)(108); + _curvea0[203] = _3912; + uint16_t _3913 = (uint16_t)(109); + _curvea0[204] = _3913; + uint16_t _3914 = (uint16_t)(109); + _curvea0[205] = _3914; + uint16_t _3915 = (uint16_t)(109); + _curvea0[206] = _3915; + uint16_t _3916 = (uint16_t)(110); + _curvea0[207] = _3916; + uint16_t _3917 = (uint16_t)(110); + _curvea0[208] = _3917; + uint16_t _3918 = (uint16_t)(111); + _curvea0[209] = _3918; + uint16_t _3919 = (uint16_t)(111); + _curvea0[210] = _3919; + uint16_t _3920 = (uint16_t)(111); + _curvea0[211] = _3920; + uint16_t _3921 = (uint16_t)(112); + _curvea0[212] = _3921; + uint16_t _3922 = (uint16_t)(112); + _curvea0[213] = _3922; + uint16_t _3923 = (uint16_t)(112); + _curvea0[214] = _3923; + uint16_t _3924 = (uint16_t)(113); + _curvea0[215] = _3924; + uint16_t _3925 = (uint16_t)(113); + _curvea0[216] = _3925; + uint16_t _3926 = (uint16_t)(113); + _curvea0[217] = _3926; + uint16_t _3927 = (uint16_t)(114); + _curvea0[218] = _3927; + uint16_t _3928 = (uint16_t)(114); + _curvea0[219] = _3928; + uint16_t _3929 = (uint16_t)(115); + _curvea0[220] = _3929; + uint16_t _3930 = (uint16_t)(115); + _curvea0[221] = _3930; + uint16_t _3931 = (uint16_t)(115); + _curvea0[222] = _3931; + uint16_t _3932 = (uint16_t)(116); + _curvea0[223] = _3932; + uint16_t _3933 = (uint16_t)(116); + _curvea0[224] = _3933; + uint16_t _3934 = (uint16_t)(116); + _curvea0[225] = _3934; + uint16_t _3935 = (uint16_t)(117); + _curvea0[226] = _3935; + uint16_t _3936 = (uint16_t)(117); + _curvea0[227] = _3936; + uint16_t _3937 = (uint16_t)(117); + _curvea0[228] = _3937; + uint16_t _3938 = (uint16_t)(118); + _curvea0[229] = _3938; + uint16_t _3939 = (uint16_t)(118); + _curvea0[230] = _3939; + uint16_t _3940 = (uint16_t)(119); + _curvea0[231] = _3940; + uint16_t _3941 = (uint16_t)(119); + _curvea0[232] = _3941; + uint16_t _3942 = (uint16_t)(119); + _curvea0[233] = _3942; + uint16_t _3943 = (uint16_t)(120); + _curvea0[234] = _3943; + uint16_t _3944 = (uint16_t)(120); + _curvea0[235] = _3944; + uint16_t _3945 = (uint16_t)(120); + _curvea0[236] = _3945; + uint16_t _3946 = (uint16_t)(121); + _curvea0[237] = _3946; + uint16_t _3947 = (uint16_t)(121); + _curvea0[238] = _3947; + uint16_t _3948 = (uint16_t)(121); + _curvea0[239] = _3948; + uint16_t _3949 = (uint16_t)(122); + _curvea0[240] = _3949; + uint16_t _3950 = (uint16_t)(122); + _curvea0[241] = _3950; + uint16_t _3951 = (uint16_t)(123); + _curvea0[242] = _3951; + uint16_t _3952 = (uint16_t)(123); + _curvea0[243] = _3952; + uint16_t _3953 = (uint16_t)(123); + _curvea0[244] = _3953; + uint16_t _3954 = (uint16_t)(124); + _curvea0[245] = _3954; + uint16_t _3955 = (uint16_t)(124); + _curvea0[246] = _3955; + uint16_t _3956 = (uint16_t)(124); + _curvea0[247] = _3956; + uint16_t _3957 = (uint16_t)(125); + _curvea0[248] = _3957; + uint16_t _3958 = (uint16_t)(125); + _curvea0[249] = _3958; + uint16_t _3959 = (uint16_t)(125); + _curvea0[250] = _3959; + uint16_t _3960 = (uint16_t)(126); + _curvea0[251] = _3960; + uint16_t _3961 = (uint16_t)(126); + _curvea0[252] = _3961; + uint16_t _3962 = (uint16_t)(126); + _curvea0[253] = _3962; + uint16_t _3963 = (uint16_t)(127); + _curvea0[254] = _3963; + uint16_t _3964 = (uint16_t)(127); + _curvea0[255] = _3964; + uint16_t _3965 = (uint16_t)(128); + _curvea0[256] = _3965; + uint16_t _3966 = (uint16_t)(128); + _curvea0[257] = _3966; + uint16_t _3967 = (uint16_t)(128); + _curvea0[258] = _3967; + uint16_t _3968 = (uint16_t)(129); + _curvea0[259] = _3968; + uint16_t _3969 = (uint16_t)(129); + _curvea0[260] = _3969; + uint16_t _3970 = (uint16_t)(129); + _curvea0[261] = _3970; + uint16_t _3971 = (uint16_t)(130); + _curvea0[262] = _3971; + uint16_t _3972 = (uint16_t)(130); + _curvea0[263] = _3972; + uint16_t _3973 = (uint16_t)(130); + _curvea0[264] = _3973; + uint16_t _3974 = (uint16_t)(131); + _curvea0[265] = _3974; + uint16_t _3975 = (uint16_t)(131); + _curvea0[266] = _3975; + uint16_t _3976 = (uint16_t)(131); + _curvea0[267] = _3976; + uint16_t _3977 = (uint16_t)(132); + _curvea0[268] = _3977; + uint16_t _3978 = (uint16_t)(132); + _curvea0[269] = _3978; + uint16_t _3979 = (uint16_t)(132); + _curvea0[270] = _3979; + uint16_t _3980 = (uint16_t)(133); + _curvea0[271] = _3980; + uint16_t _3981 = (uint16_t)(133); + _curvea0[272] = _3981; + uint16_t _3982 = (uint16_t)(133); + _curvea0[273] = _3982; + uint16_t _3983 = (uint16_t)(134); + _curvea0[274] = _3983; + uint16_t _3984 = (uint16_t)(134); + _curvea0[275] = _3984; + uint16_t _3985 = (uint16_t)(134); + _curvea0[276] = _3985; + uint16_t _3986 = (uint16_t)(135); + _curvea0[277] = _3986; + uint16_t _3987 = (uint16_t)(135); + _curvea0[278] = _3987; + uint16_t _3988 = (uint16_t)(135); + _curvea0[279] = _3988; + uint16_t _3989 = (uint16_t)(136); + _curvea0[280] = _3989; + uint16_t _3990 = (uint16_t)(136); + _curvea0[281] = _3990; + uint16_t _3991 = (uint16_t)(136); + _curvea0[282] = _3991; + uint16_t _3992 = (uint16_t)(137); + _curvea0[283] = _3992; + uint16_t _3993 = (uint16_t)(137); + _curvea0[284] = _3993; + uint16_t _3994 = (uint16_t)(137); + _curvea0[285] = _3994; + uint16_t _3995 = (uint16_t)(138); + _curvea0[286] = _3995; + uint16_t _3996 = (uint16_t)(138); + _curvea0[287] = _3996; + uint16_t _3997 = (uint16_t)(138); + _curvea0[288] = _3997; + uint16_t _3998 = (uint16_t)(139); + _curvea0[289] = _3998; + uint16_t _3999 = (uint16_t)(139); + _curvea0[290] = _3999; + uint16_t _4000 = (uint16_t)(139); + _curvea0[291] = _4000; + uint16_t _4001 = (uint16_t)(140); + _curvea0[292] = _4001; + uint16_t _4002 = (uint16_t)(140); + _curvea0[293] = _4002; + uint16_t _4003 = (uint16_t)(140); + _curvea0[294] = _4003; + uint16_t _4004 = (uint16_t)(141); + _curvea0[295] = _4004; + uint16_t _4005 = (uint16_t)(141); + _curvea0[296] = _4005; + uint16_t _4006 = (uint16_t)(141); + _curvea0[297] = _4006; + uint16_t _4007 = (uint16_t)(141); + _curvea0[298] = _4007; + uint16_t _4008 = (uint16_t)(142); + _curvea0[299] = _4008; + uint16_t _4009 = (uint16_t)(142); + _curvea0[300] = _4009; + uint16_t _4010 = (uint16_t)(142); + _curvea0[301] = _4010; + uint16_t _4011 = (uint16_t)(143); + _curvea0[302] = _4011; + uint16_t _4012 = (uint16_t)(143); + _curvea0[303] = _4012; + uint16_t _4013 = (uint16_t)(143); + _curvea0[304] = _4013; + uint16_t _4014 = (uint16_t)(144); + _curvea0[305] = _4014; + uint16_t _4015 = (uint16_t)(144); + _curvea0[306] = _4015; + uint16_t _4016 = (uint16_t)(144); + _curvea0[307] = _4016; + uint16_t _4017 = (uint16_t)(145); + _curvea0[308] = _4017; + uint16_t _4018 = (uint16_t)(145); + _curvea0[309] = _4018; + uint16_t _4019 = (uint16_t)(145); + _curvea0[310] = _4019; + uint16_t _4020 = (uint16_t)(145); + _curvea0[311] = _4020; + uint16_t _4021 = (uint16_t)(146); + _curvea0[312] = _4021; + uint16_t _4022 = (uint16_t)(146); + _curvea0[313] = _4022; + uint16_t _4023 = (uint16_t)(146); + _curvea0[314] = _4023; + uint16_t _4024 = (uint16_t)(147); + _curvea0[315] = _4024; + uint16_t _4025 = (uint16_t)(147); + _curvea0[316] = _4025; + uint16_t _4026 = (uint16_t)(147); + _curvea0[317] = _4026; + uint16_t _4027 = (uint16_t)(148); + _curvea0[318] = _4027; + uint16_t _4028 = (uint16_t)(148); + _curvea0[319] = _4028; + uint16_t _4029 = (uint16_t)(148); + _curvea0[320] = _4029; + uint16_t _4030 = (uint16_t)(148); + _curvea0[321] = _4030; + uint16_t _4031 = (uint16_t)(149); + _curvea0[322] = _4031; + uint16_t _4032 = (uint16_t)(149); + _curvea0[323] = _4032; + uint16_t _4033 = (uint16_t)(149); + _curvea0[324] = _4033; + uint16_t _4034 = (uint16_t)(150); + _curvea0[325] = _4034; + uint16_t _4035 = (uint16_t)(150); + _curvea0[326] = _4035; + uint16_t _4036 = (uint16_t)(150); + _curvea0[327] = _4036; + uint16_t _4037 = (uint16_t)(150); + _curvea0[328] = _4037; + uint16_t _4038 = (uint16_t)(151); + _curvea0[329] = _4038; + uint16_t _4039 = (uint16_t)(151); + _curvea0[330] = _4039; + uint16_t _4040 = (uint16_t)(151); + _curvea0[331] = _4040; + uint16_t _4041 = (uint16_t)(152); + _curvea0[332] = _4041; + uint16_t _4042 = (uint16_t)(152); + _curvea0[333] = _4042; + uint16_t _4043 = (uint16_t)(152); + _curvea0[334] = _4043; + uint16_t _4044 = (uint16_t)(152); + _curvea0[335] = _4044; + uint16_t _4045 = (uint16_t)(153); + _curvea0[336] = _4045; + uint16_t _4046 = (uint16_t)(153); + _curvea0[337] = _4046; + uint16_t _4047 = (uint16_t)(153); + _curvea0[338] = _4047; + uint16_t _4048 = (uint16_t)(154); + _curvea0[339] = _4048; + uint16_t _4049 = (uint16_t)(154); + _curvea0[340] = _4049; + uint16_t _4050 = (uint16_t)(154); + _curvea0[341] = _4050; + uint16_t _4051 = (uint16_t)(154); + _curvea0[342] = _4051; + uint16_t _4052 = (uint16_t)(155); + _curvea0[343] = _4052; + uint16_t _4053 = (uint16_t)(155); + _curvea0[344] = _4053; + uint16_t _4054 = (uint16_t)(155); + _curvea0[345] = _4054; + uint16_t _4055 = (uint16_t)(156); + _curvea0[346] = _4055; + uint16_t _4056 = (uint16_t)(156); + _curvea0[347] = _4056; + uint16_t _4057 = (uint16_t)(156); + _curvea0[348] = _4057; + uint16_t _4058 = (uint16_t)(156); + _curvea0[349] = _4058; + uint16_t _4059 = (uint16_t)(157); + _curvea0[350] = _4059; + uint16_t _4060 = (uint16_t)(157); + _curvea0[351] = _4060; + uint16_t _4061 = (uint16_t)(157); + _curvea0[352] = _4061; + uint16_t _4062 = (uint16_t)(157); + _curvea0[353] = _4062; + uint16_t _4063 = (uint16_t)(158); + _curvea0[354] = _4063; + uint16_t _4064 = (uint16_t)(158); + _curvea0[355] = _4064; + uint16_t _4065 = (uint16_t)(158); + _curvea0[356] = _4065; + uint16_t _4066 = (uint16_t)(159); + _curvea0[357] = _4066; + uint16_t _4067 = (uint16_t)(159); + _curvea0[358] = _4067; + uint16_t _4068 = (uint16_t)(159); + _curvea0[359] = _4068; + uint16_t _4069 = (uint16_t)(159); + _curvea0[360] = _4069; + uint16_t _4070 = (uint16_t)(160); + _curvea0[361] = _4070; + uint16_t _4071 = (uint16_t)(160); + _curvea0[362] = _4071; + uint16_t _4072 = (uint16_t)(160); + _curvea0[363] = _4072; + uint16_t _4073 = (uint16_t)(160); + _curvea0[364] = _4073; + uint16_t _4074 = (uint16_t)(161); + _curvea0[365] = _4074; + uint16_t _4075 = (uint16_t)(161); + _curvea0[366] = _4075; + uint16_t _4076 = (uint16_t)(161); + _curvea0[367] = _4076; + uint16_t _4077 = (uint16_t)(161); + _curvea0[368] = _4077; + uint16_t _4078 = (uint16_t)(162); + _curvea0[369] = _4078; + uint16_t _4079 = (uint16_t)(162); + _curvea0[370] = _4079; + uint16_t _4080 = (uint16_t)(162); + _curvea0[371] = _4080; + uint16_t _4081 = (uint16_t)(162); + _curvea0[372] = _4081; + uint16_t _4082 = (uint16_t)(163); + _curvea0[373] = _4082; + uint16_t _4083 = (uint16_t)(163); + _curvea0[374] = _4083; + uint16_t _4084 = (uint16_t)(163); + _curvea0[375] = _4084; + uint16_t _4085 = (uint16_t)(163); + _curvea0[376] = _4085; + uint16_t _4086 = (uint16_t)(164); + _curvea0[377] = _4086; + uint16_t _4087 = (uint16_t)(164); + _curvea0[378] = _4087; + uint16_t _4088 = (uint16_t)(164); + _curvea0[379] = _4088; + uint16_t _4089 = (uint16_t)(164); + _curvea0[380] = _4089; + uint16_t _4090 = (uint16_t)(165); + _curvea0[381] = _4090; + uint16_t _4091 = (uint16_t)(165); + _curvea0[382] = _4091; + uint16_t _4092 = (uint16_t)(165); + _curvea0[383] = _4092; + uint16_t _4093 = (uint16_t)(166); + _curvea0[384] = _4093; + uint16_t _4094 = (uint16_t)(166); + _curvea0[385] = _4094; + uint16_t _4095 = (uint16_t)(166); + _curvea0[386] = _4095; + uint16_t _4096 = (uint16_t)(166); + _curvea0[387] = _4096; + uint16_t _4097 = (uint16_t)(167); + _curvea0[388] = _4097; + uint16_t _4098 = (uint16_t)(167); + _curvea0[389] = _4098; + uint16_t _4099 = (uint16_t)(167); + _curvea0[390] = _4099; + uint16_t _4100 = (uint16_t)(167); + _curvea0[391] = _4100; + uint16_t _4101 = (uint16_t)(167); + _curvea0[392] = _4101; + uint16_t _4102 = (uint16_t)(168); + _curvea0[393] = _4102; + uint16_t _4103 = (uint16_t)(168); + _curvea0[394] = _4103; + uint16_t _4104 = (uint16_t)(168); + _curvea0[395] = _4104; + uint16_t _4105 = (uint16_t)(168); + _curvea0[396] = _4105; + uint16_t _4106 = (uint16_t)(169); + _curvea0[397] = _4106; + uint16_t _4107 = (uint16_t)(169); + _curvea0[398] = _4107; + uint16_t _4108 = (uint16_t)(169); + _curvea0[399] = _4108; + uint16_t _4109 = (uint16_t)(169); + _curvea0[400] = _4109; + uint16_t _4110 = (uint16_t)(170); + _curvea0[401] = _4110; + uint16_t _4111 = (uint16_t)(170); + _curvea0[402] = _4111; + uint16_t _4112 = (uint16_t)(170); + _curvea0[403] = _4112; + uint16_t _4113 = (uint16_t)(170); + _curvea0[404] = _4113; + uint16_t _4114 = (uint16_t)(171); + _curvea0[405] = _4114; + uint16_t _4115 = (uint16_t)(171); + _curvea0[406] = _4115; + uint16_t _4116 = (uint16_t)(171); + _curvea0[407] = _4116; + uint16_t _4117 = (uint16_t)(171); + _curvea0[408] = _4117; + uint16_t _4118 = (uint16_t)(172); + _curvea0[409] = _4118; + uint16_t _4119 = (uint16_t)(172); + _curvea0[410] = _4119; + uint16_t _4120 = (uint16_t)(172); + _curvea0[411] = _4120; + uint16_t _4121 = (uint16_t)(172); + _curvea0[412] = _4121; + uint16_t _4122 = (uint16_t)(173); + _curvea0[413] = _4122; + uint16_t _4123 = (uint16_t)(173); + _curvea0[414] = _4123; + uint16_t _4124 = (uint16_t)(173); + _curvea0[415] = _4124; + uint16_t _4125 = (uint16_t)(173); + _curvea0[416] = _4125; + uint16_t _4126 = (uint16_t)(173); + _curvea0[417] = _4126; + uint16_t _4127 = (uint16_t)(174); + _curvea0[418] = _4127; + uint16_t _4128 = (uint16_t)(174); + _curvea0[419] = _4128; + uint16_t _4129 = (uint16_t)(174); + _curvea0[420] = _4129; + uint16_t _4130 = (uint16_t)(174); + _curvea0[421] = _4130; + uint16_t _4131 = (uint16_t)(175); + _curvea0[422] = _4131; + uint16_t _4132 = (uint16_t)(175); + _curvea0[423] = _4132; + uint16_t _4133 = (uint16_t)(175); + _curvea0[424] = _4133; + uint16_t _4134 = (uint16_t)(175); + _curvea0[425] = _4134; + uint16_t _4135 = (uint16_t)(176); + _curvea0[426] = _4135; + uint16_t _4136 = (uint16_t)(176); + _curvea0[427] = _4136; + uint16_t _4137 = (uint16_t)(176); + _curvea0[428] = _4137; + uint16_t _4138 = (uint16_t)(176); + _curvea0[429] = _4138; + uint16_t _4139 = (uint16_t)(176); + _curvea0[430] = _4139; + uint16_t _4140 = (uint16_t)(177); + _curvea0[431] = _4140; + uint16_t _4141 = (uint16_t)(177); + _curvea0[432] = _4141; + uint16_t _4142 = (uint16_t)(177); + _curvea0[433] = _4142; + uint16_t _4143 = (uint16_t)(177); + _curvea0[434] = _4143; + uint16_t _4144 = (uint16_t)(178); + _curvea0[435] = _4144; + uint16_t _4145 = (uint16_t)(178); + _curvea0[436] = _4145; + uint16_t _4146 = (uint16_t)(178); + _curvea0[437] = _4146; + uint16_t _4147 = (uint16_t)(178); + _curvea0[438] = _4147; + uint16_t _4148 = (uint16_t)(178); + _curvea0[439] = _4148; + uint16_t _4149 = (uint16_t)(179); + _curvea0[440] = _4149; + uint16_t _4150 = (uint16_t)(179); + _curvea0[441] = _4150; + uint16_t _4151 = (uint16_t)(179); + _curvea0[442] = _4151; + uint16_t _4152 = (uint16_t)(179); + _curvea0[443] = _4152; + uint16_t _4153 = (uint16_t)(180); + _curvea0[444] = _4153; + uint16_t _4154 = (uint16_t)(180); + _curvea0[445] = _4154; + uint16_t _4155 = (uint16_t)(180); + _curvea0[446] = _4155; + uint16_t _4156 = (uint16_t)(180); + _curvea0[447] = _4156; + uint16_t _4157 = (uint16_t)(180); + _curvea0[448] = _4157; + uint16_t _4158 = (uint16_t)(181); + _curvea0[449] = _4158; + uint16_t _4159 = (uint16_t)(181); + _curvea0[450] = _4159; + uint16_t _4160 = (uint16_t)(181); + _curvea0[451] = _4160; + uint16_t _4161 = (uint16_t)(181); + _curvea0[452] = _4161; + uint16_t _4162 = (uint16_t)(181); + _curvea0[453] = _4162; + uint16_t _4163 = (uint16_t)(182); + _curvea0[454] = _4163; + uint16_t _4164 = (uint16_t)(182); + _curvea0[455] = _4164; + uint16_t _4165 = (uint16_t)(182); + _curvea0[456] = _4165; + uint16_t _4166 = (uint16_t)(182); + _curvea0[457] = _4166; + uint16_t _4167 = (uint16_t)(183); + _curvea0[458] = _4167; + uint16_t _4168 = (uint16_t)(183); + _curvea0[459] = _4168; + uint16_t _4169 = (uint16_t)(183); + _curvea0[460] = _4169; + uint16_t _4170 = (uint16_t)(183); + _curvea0[461] = _4170; + uint16_t _4171 = (uint16_t)(183); + _curvea0[462] = _4171; + uint16_t _4172 = (uint16_t)(184); + _curvea0[463] = _4172; + uint16_t _4173 = (uint16_t)(184); + _curvea0[464] = _4173; + uint16_t _4174 = (uint16_t)(184); + _curvea0[465] = _4174; + uint16_t _4175 = (uint16_t)(184); + _curvea0[466] = _4175; + uint16_t _4176 = (uint16_t)(184); + _curvea0[467] = _4176; + uint16_t _4177 = (uint16_t)(185); + _curvea0[468] = _4177; + uint16_t _4178 = (uint16_t)(185); + _curvea0[469] = _4178; + uint16_t _4179 = (uint16_t)(185); + _curvea0[470] = _4179; + uint16_t _4180 = (uint16_t)(185); + _curvea0[471] = _4180; + uint16_t _4181 = (uint16_t)(185); + _curvea0[472] = _4181; + uint16_t _4182 = (uint16_t)(186); + _curvea0[473] = _4182; + uint16_t _4183 = (uint16_t)(186); + _curvea0[474] = _4183; + uint16_t _4184 = (uint16_t)(186); + _curvea0[475] = _4184; + uint16_t _4185 = (uint16_t)(186); + _curvea0[476] = _4185; + uint16_t _4186 = (uint16_t)(187); + _curvea0[477] = _4186; + uint16_t _4187 = (uint16_t)(187); + _curvea0[478] = _4187; + uint16_t _4188 = (uint16_t)(187); + _curvea0[479] = _4188; + uint16_t _4189 = (uint16_t)(187); + _curvea0[480] = _4189; + uint16_t _4190 = (uint16_t)(187); + _curvea0[481] = _4190; + uint16_t _4191 = (uint16_t)(188); + _curvea0[482] = _4191; + uint16_t _4192 = (uint16_t)(188); + _curvea0[483] = _4192; + uint16_t _4193 = (uint16_t)(188); + _curvea0[484] = _4193; + uint16_t _4194 = (uint16_t)(188); + _curvea0[485] = _4194; + uint16_t _4195 = (uint16_t)(188); + _curvea0[486] = _4195; + uint16_t _4196 = (uint16_t)(189); + _curvea0[487] = _4196; + uint16_t _4197 = (uint16_t)(189); + _curvea0[488] = _4197; + uint16_t _4198 = (uint16_t)(189); + _curvea0[489] = _4198; + uint16_t _4199 = (uint16_t)(189); + _curvea0[490] = _4199; + uint16_t _4200 = (uint16_t)(189); + _curvea0[491] = _4200; + uint16_t _4201 = (uint16_t)(190); + _curvea0[492] = _4201; + uint16_t _4202 = (uint16_t)(190); + _curvea0[493] = _4202; + uint16_t _4203 = (uint16_t)(190); + _curvea0[494] = _4203; + uint16_t _4204 = (uint16_t)(190); + _curvea0[495] = _4204; + uint16_t _4205 = (uint16_t)(190); + _curvea0[496] = _4205; + uint16_t _4206 = (uint16_t)(190); + _curvea0[497] = _4206; + uint16_t _4207 = (uint16_t)(191); + _curvea0[498] = _4207; + uint16_t _4208 = (uint16_t)(191); + _curvea0[499] = _4208; + uint16_t _4209 = (uint16_t)(191); + _curvea0[500] = _4209; + uint16_t _4210 = (uint16_t)(191); + _curvea0[501] = _4210; + uint16_t _4211 = (uint16_t)(191); + _curvea0[502] = _4211; + uint16_t _4212 = (uint16_t)(192); + _curvea0[503] = _4212; + uint16_t _4213 = (uint16_t)(192); + _curvea0[504] = _4213; + uint16_t _4214 = (uint16_t)(192); + _curvea0[505] = _4214; + uint16_t _4215 = (uint16_t)(192); + _curvea0[506] = _4215; + uint16_t _4216 = (uint16_t)(192); + _curvea0[507] = _4216; + uint16_t _4217 = (uint16_t)(193); + _curvea0[508] = _4217; + uint16_t _4218 = (uint16_t)(193); + _curvea0[509] = _4218; + uint16_t _4219 = (uint16_t)(193); + _curvea0[510] = _4219; + uint16_t _4220 = (uint16_t)(193); + _curvea0[511] = _4220; + uint16_t _4221 = (uint16_t)(193); + _curvea0[512] = _4221; + uint16_t _4222 = (uint16_t)(194); + _curvea0[513] = _4222; + uint16_t _4223 = (uint16_t)(194); + _curvea0[514] = _4223; + uint16_t _4224 = (uint16_t)(194); + _curvea0[515] = _4224; + uint16_t _4225 = (uint16_t)(194); + _curvea0[516] = _4225; + uint16_t _4226 = (uint16_t)(194); + _curvea0[517] = _4226; + uint16_t _4227 = (uint16_t)(195); + _curvea0[518] = _4227; + uint16_t _4228 = (uint16_t)(195); + _curvea0[519] = _4228; + uint16_t _4229 = (uint16_t)(195); + _curvea0[520] = _4229; + uint16_t _4230 = (uint16_t)(195); + _curvea0[521] = _4230; + uint16_t _4231 = (uint16_t)(195); + _curvea0[522] = _4231; + uint16_t _4232 = (uint16_t)(195); + _curvea0[523] = _4232; + uint16_t _4233 = (uint16_t)(196); + _curvea0[524] = _4233; + uint16_t _4234 = (uint16_t)(196); + _curvea0[525] = _4234; + uint16_t _4235 = (uint16_t)(196); + _curvea0[526] = _4235; + uint16_t _4236 = (uint16_t)(196); + _curvea0[527] = _4236; + uint16_t _4237 = (uint16_t)(196); + _curvea0[528] = _4237; + uint16_t _4238 = (uint16_t)(197); + _curvea0[529] = _4238; + uint16_t _4239 = (uint16_t)(197); + _curvea0[530] = _4239; + uint16_t _4240 = (uint16_t)(197); + _curvea0[531] = _4240; + uint16_t _4241 = (uint16_t)(197); + _curvea0[532] = _4241; + uint16_t _4242 = (uint16_t)(197); + _curvea0[533] = _4242; + uint16_t _4243 = (uint16_t)(197); + _curvea0[534] = _4243; + uint16_t _4244 = (uint16_t)(198); + _curvea0[535] = _4244; + uint16_t _4245 = (uint16_t)(198); + _curvea0[536] = _4245; + uint16_t _4246 = (uint16_t)(198); + _curvea0[537] = _4246; + uint16_t _4247 = (uint16_t)(198); + _curvea0[538] = _4247; + uint16_t _4248 = (uint16_t)(198); + _curvea0[539] = _4248; + uint16_t _4249 = (uint16_t)(199); + _curvea0[540] = _4249; + uint16_t _4250 = (uint16_t)(199); + _curvea0[541] = _4250; + uint16_t _4251 = (uint16_t)(199); + _curvea0[542] = _4251; + uint16_t _4252 = (uint16_t)(199); + _curvea0[543] = _4252; + uint16_t _4253 = (uint16_t)(199); + _curvea0[544] = _4253; + uint16_t _4254 = (uint16_t)(199); + _curvea0[545] = _4254; + uint16_t _4255 = (uint16_t)(200); + _curvea0[546] = _4255; + uint16_t _4256 = (uint16_t)(200); + _curvea0[547] = _4256; + uint16_t _4257 = (uint16_t)(200); + _curvea0[548] = _4257; + uint16_t _4258 = (uint16_t)(200); + _curvea0[549] = _4258; + uint16_t _4259 = (uint16_t)(200); + _curvea0[550] = _4259; + uint16_t _4260 = (uint16_t)(200); + _curvea0[551] = _4260; + uint16_t _4261 = (uint16_t)(201); + _curvea0[552] = _4261; + uint16_t _4262 = (uint16_t)(201); + _curvea0[553] = _4262; + uint16_t _4263 = (uint16_t)(201); + _curvea0[554] = _4263; + uint16_t _4264 = (uint16_t)(201); + _curvea0[555] = _4264; + uint16_t _4265 = (uint16_t)(201); + _curvea0[556] = _4265; + uint16_t _4266 = (uint16_t)(202); + _curvea0[557] = _4266; + uint16_t _4267 = (uint16_t)(202); + _curvea0[558] = _4267; + uint16_t _4268 = (uint16_t)(202); + _curvea0[559] = _4268; + uint16_t _4269 = (uint16_t)(202); + _curvea0[560] = _4269; + uint16_t _4270 = (uint16_t)(202); + _curvea0[561] = _4270; + uint16_t _4271 = (uint16_t)(202); + _curvea0[562] = _4271; + uint16_t _4272 = (uint16_t)(203); + _curvea0[563] = _4272; + uint16_t _4273 = (uint16_t)(203); + _curvea0[564] = _4273; + uint16_t _4274 = (uint16_t)(203); + _curvea0[565] = _4274; + uint16_t _4275 = (uint16_t)(203); + _curvea0[566] = _4275; + uint16_t _4276 = (uint16_t)(203); + _curvea0[567] = _4276; + uint16_t _4277 = (uint16_t)(203); + _curvea0[568] = _4277; + uint16_t _4278 = (uint16_t)(204); + _curvea0[569] = _4278; + uint16_t _4279 = (uint16_t)(204); + _curvea0[570] = _4279; + uint16_t _4280 = (uint16_t)(204); + _curvea0[571] = _4280; + uint16_t _4281 = (uint16_t)(204); + _curvea0[572] = _4281; + uint16_t _4282 = (uint16_t)(204); + _curvea0[573] = _4282; + uint16_t _4283 = (uint16_t)(204); + _curvea0[574] = _4283; + uint16_t _4284 = (uint16_t)(205); + _curvea0[575] = _4284; + uint16_t _4285 = (uint16_t)(205); + _curvea0[576] = _4285; + uint16_t _4286 = (uint16_t)(205); + _curvea0[577] = _4286; + uint16_t _4287 = (uint16_t)(205); + _curvea0[578] = _4287; + uint16_t _4288 = (uint16_t)(205); + _curvea0[579] = _4288; + uint16_t _4289 = (uint16_t)(205); + _curvea0[580] = _4289; + uint16_t _4290 = (uint16_t)(206); + _curvea0[581] = _4290; + uint16_t _4291 = (uint16_t)(206); + _curvea0[582] = _4291; + uint16_t _4292 = (uint16_t)(206); + _curvea0[583] = _4292; + uint16_t _4293 = (uint16_t)(206); + _curvea0[584] = _4293; + uint16_t _4294 = (uint16_t)(206); + _curvea0[585] = _4294; + uint16_t _4295 = (uint16_t)(206); + _curvea0[586] = _4295; + uint16_t _4296 = (uint16_t)(207); + _curvea0[587] = _4296; + uint16_t _4297 = (uint16_t)(207); + _curvea0[588] = _4297; + uint16_t _4298 = (uint16_t)(207); + _curvea0[589] = _4298; + uint16_t _4299 = (uint16_t)(207); + _curvea0[590] = _4299; + uint16_t _4300 = (uint16_t)(207); + _curvea0[591] = _4300; + uint16_t _4301 = (uint16_t)(207); + _curvea0[592] = _4301; + uint16_t _4302 = (uint16_t)(208); + _curvea0[593] = _4302; + uint16_t _4303 = (uint16_t)(208); + _curvea0[594] = _4303; + uint16_t _4304 = (uint16_t)(208); + _curvea0[595] = _4304; + uint16_t _4305 = (uint16_t)(208); + _curvea0[596] = _4305; + uint16_t _4306 = (uint16_t)(208); + _curvea0[597] = _4306; + uint16_t _4307 = (uint16_t)(208); + _curvea0[598] = _4307; + uint16_t _4308 = (uint16_t)(209); + _curvea0[599] = _4308; + uint16_t _4309 = (uint16_t)(209); + _curvea0[600] = _4309; + uint16_t _4310 = (uint16_t)(209); + _curvea0[601] = _4310; + uint16_t _4311 = (uint16_t)(209); + _curvea0[602] = _4311; + uint16_t _4312 = (uint16_t)(209); + _curvea0[603] = _4312; + uint16_t _4313 = (uint16_t)(209); + _curvea0[604] = _4313; + uint16_t _4314 = (uint16_t)(209); + _curvea0[605] = _4314; + uint16_t _4315 = (uint16_t)(210); + _curvea0[606] = _4315; + uint16_t _4316 = (uint16_t)(210); + _curvea0[607] = _4316; + uint16_t _4317 = (uint16_t)(210); + _curvea0[608] = _4317; + uint16_t _4318 = (uint16_t)(210); + _curvea0[609] = _4318; + uint16_t _4319 = (uint16_t)(210); + _curvea0[610] = _4319; + uint16_t _4320 = (uint16_t)(210); + _curvea0[611] = _4320; + uint16_t _4321 = (uint16_t)(211); + _curvea0[612] = _4321; + uint16_t _4322 = (uint16_t)(211); + _curvea0[613] = _4322; + uint16_t _4323 = (uint16_t)(211); + _curvea0[614] = _4323; + uint16_t _4324 = (uint16_t)(211); + _curvea0[615] = _4324; + uint16_t _4325 = (uint16_t)(211); + _curvea0[616] = _4325; + uint16_t _4326 = (uint16_t)(211); + _curvea0[617] = _4326; + uint16_t _4327 = (uint16_t)(211); + _curvea0[618] = _4327; + uint16_t _4328 = (uint16_t)(212); + _curvea0[619] = _4328; + uint16_t _4329 = (uint16_t)(212); + _curvea0[620] = _4329; + uint16_t _4330 = (uint16_t)(212); + _curvea0[621] = _4330; + uint16_t _4331 = (uint16_t)(212); + _curvea0[622] = _4331; + uint16_t _4332 = (uint16_t)(212); + _curvea0[623] = _4332; + uint16_t _4333 = (uint16_t)(212); + _curvea0[624] = _4333; + uint16_t _4334 = (uint16_t)(213); + _curvea0[625] = _4334; + uint16_t _4335 = (uint16_t)(213); + _curvea0[626] = _4335; + uint16_t _4336 = (uint16_t)(213); + _curvea0[627] = _4336; + uint16_t _4337 = (uint16_t)(213); + _curvea0[628] = _4337; + uint16_t _4338 = (uint16_t)(213); + _curvea0[629] = _4338; + uint16_t _4339 = (uint16_t)(213); + _curvea0[630] = _4339; + uint16_t _4340 = (uint16_t)(213); + _curvea0[631] = _4340; + uint16_t _4341 = (uint16_t)(214); + _curvea0[632] = _4341; + uint16_t _4342 = (uint16_t)(214); + _curvea0[633] = _4342; + uint16_t _4343 = (uint16_t)(214); + _curvea0[634] = _4343; + uint16_t _4344 = (uint16_t)(214); + _curvea0[635] = _4344; + uint16_t _4345 = (uint16_t)(214); + _curvea0[636] = _4345; + uint16_t _4346 = (uint16_t)(214); + _curvea0[637] = _4346; + uint16_t _4347 = (uint16_t)(214); + _curvea0[638] = _4347; + uint16_t _4348 = (uint16_t)(215); + _curvea0[639] = _4348; + uint16_t _4349 = (uint16_t)(215); + _curvea0[640] = _4349; + uint16_t _4350 = (uint16_t)(215); + _curvea0[641] = _4350; + uint16_t _4351 = (uint16_t)(215); + _curvea0[642] = _4351; + uint16_t _4352 = (uint16_t)(215); + _curvea0[643] = _4352; + uint16_t _4353 = (uint16_t)(215); + _curvea0[644] = _4353; + uint16_t _4354 = (uint16_t)(216); + _curvea0[645] = _4354; + uint16_t _4355 = (uint16_t)(216); + _curvea0[646] = _4355; + uint16_t _4356 = (uint16_t)(216); + _curvea0[647] = _4356; + uint16_t _4357 = (uint16_t)(216); + _curvea0[648] = _4357; + uint16_t _4358 = (uint16_t)(216); + _curvea0[649] = _4358; + uint16_t _4359 = (uint16_t)(216); + _curvea0[650] = _4359; + uint16_t _4360 = (uint16_t)(216); + _curvea0[651] = _4360; + uint16_t _4361 = (uint16_t)(217); + _curvea0[652] = _4361; + uint16_t _4362 = (uint16_t)(217); + _curvea0[653] = _4362; + uint16_t _4363 = (uint16_t)(217); + _curvea0[654] = _4363; + uint16_t _4364 = (uint16_t)(217); + _curvea0[655] = _4364; + uint16_t _4365 = (uint16_t)(217); + _curvea0[656] = _4365; + uint16_t _4366 = (uint16_t)(217); + _curvea0[657] = _4366; + uint16_t _4367 = (uint16_t)(217); + _curvea0[658] = _4367; + uint16_t _4368 = (uint16_t)(218); + _curvea0[659] = _4368; + uint16_t _4369 = (uint16_t)(218); + _curvea0[660] = _4369; + uint16_t _4370 = (uint16_t)(218); + _curvea0[661] = _4370; + uint16_t _4371 = (uint16_t)(218); + _curvea0[662] = _4371; + uint16_t _4372 = (uint16_t)(218); + _curvea0[663] = _4372; + uint16_t _4373 = (uint16_t)(218); + _curvea0[664] = _4373; + uint16_t _4374 = (uint16_t)(218); + _curvea0[665] = _4374; + uint16_t _4375 = (uint16_t)(219); + _curvea0[666] = _4375; + uint16_t _4376 = (uint16_t)(219); + _curvea0[667] = _4376; + uint16_t _4377 = (uint16_t)(219); + _curvea0[668] = _4377; + uint16_t _4378 = (uint16_t)(219); + _curvea0[669] = _4378; + uint16_t _4379 = (uint16_t)(219); + _curvea0[670] = _4379; + uint16_t _4380 = (uint16_t)(219); + _curvea0[671] = _4380; + uint16_t _4381 = (uint16_t)(219); + _curvea0[672] = _4381; + uint16_t _4382 = (uint16_t)(220); + _curvea0[673] = _4382; + uint16_t _4383 = (uint16_t)(220); + _curvea0[674] = _4383; + uint16_t _4384 = (uint16_t)(220); + _curvea0[675] = _4384; + uint16_t _4385 = (uint16_t)(220); + _curvea0[676] = _4385; + uint16_t _4386 = (uint16_t)(220); + _curvea0[677] = _4386; + uint16_t _4387 = (uint16_t)(220); + _curvea0[678] = _4387; + uint16_t _4388 = (uint16_t)(220); + _curvea0[679] = _4388; + uint16_t _4389 = (uint16_t)(220); + _curvea0[680] = _4389; + uint16_t _4390 = (uint16_t)(221); + _curvea0[681] = _4390; + uint16_t _4391 = (uint16_t)(221); + _curvea0[682] = _4391; + uint16_t _4392 = (uint16_t)(221); + _curvea0[683] = _4392; + uint16_t _4393 = (uint16_t)(221); + _curvea0[684] = _4393; + uint16_t _4394 = (uint16_t)(221); + _curvea0[685] = _4394; + uint16_t _4395 = (uint16_t)(221); + _curvea0[686] = _4395; + uint16_t _4396 = (uint16_t)(221); + _curvea0[687] = _4396; + uint16_t _4397 = (uint16_t)(222); + _curvea0[688] = _4397; + uint16_t _4398 = (uint16_t)(222); + _curvea0[689] = _4398; + uint16_t _4399 = (uint16_t)(222); + _curvea0[690] = _4399; + uint16_t _4400 = (uint16_t)(222); + _curvea0[691] = _4400; + uint16_t _4401 = (uint16_t)(222); + _curvea0[692] = _4401; + uint16_t _4402 = (uint16_t)(222); + _curvea0[693] = _4402; + uint16_t _4403 = (uint16_t)(222); + _curvea0[694] = _4403; + uint16_t _4404 = (uint16_t)(223); + _curvea0[695] = _4404; + uint16_t _4405 = (uint16_t)(223); + _curvea0[696] = _4405; + uint16_t _4406 = (uint16_t)(223); + _curvea0[697] = _4406; + uint16_t _4407 = (uint16_t)(223); + _curvea0[698] = _4407; + uint16_t _4408 = (uint16_t)(223); + _curvea0[699] = _4408; + uint16_t _4409 = (uint16_t)(223); + _curvea0[700] = _4409; + uint16_t _4410 = (uint16_t)(223); + _curvea0[701] = _4410; + uint16_t _4411 = (uint16_t)(223); + _curvea0[702] = _4411; + uint16_t _4412 = (uint16_t)(224); + _curvea0[703] = _4412; + uint16_t _4413 = (uint16_t)(224); + _curvea0[704] = _4413; + uint16_t _4414 = (uint16_t)(224); + _curvea0[705] = _4414; + uint16_t _4415 = (uint16_t)(224); + _curvea0[706] = _4415; + uint16_t _4416 = (uint16_t)(224); + _curvea0[707] = _4416; + uint16_t _4417 = (uint16_t)(224); + _curvea0[708] = _4417; + uint16_t _4418 = (uint16_t)(224); + _curvea0[709] = _4418; + uint16_t _4419 = (uint16_t)(224); + _curvea0[710] = _4419; + uint16_t _4420 = (uint16_t)(225); + _curvea0[711] = _4420; + uint16_t _4421 = (uint16_t)(225); + _curvea0[712] = _4421; + uint16_t _4422 = (uint16_t)(225); + _curvea0[713] = _4422; + uint16_t _4423 = (uint16_t)(225); + _curvea0[714] = _4423; + uint16_t _4424 = (uint16_t)(225); + _curvea0[715] = _4424; + uint16_t _4425 = (uint16_t)(225); + _curvea0[716] = _4425; + uint16_t _4426 = (uint16_t)(225); + _curvea0[717] = _4426; + uint16_t _4427 = (uint16_t)(226); + _curvea0[718] = _4427; + uint16_t _4428 = (uint16_t)(226); + _curvea0[719] = _4428; + uint16_t _4429 = (uint16_t)(226); + _curvea0[720] = _4429; + uint16_t _4430 = (uint16_t)(226); + _curvea0[721] = _4430; + uint16_t _4431 = (uint16_t)(226); + _curvea0[722] = _4431; + uint16_t _4432 = (uint16_t)(226); + _curvea0[723] = _4432; + uint16_t _4433 = (uint16_t)(226); + _curvea0[724] = _4433; + uint16_t _4434 = (uint16_t)(226); + _curvea0[725] = _4434; + uint16_t _4435 = (uint16_t)(227); + _curvea0[726] = _4435; + uint16_t _4436 = (uint16_t)(227); + _curvea0[727] = _4436; + uint16_t _4437 = (uint16_t)(227); + _curvea0[728] = _4437; + uint16_t _4438 = (uint16_t)(227); + _curvea0[729] = _4438; + uint16_t _4439 = (uint16_t)(227); + _curvea0[730] = _4439; + uint16_t _4440 = (uint16_t)(227); + _curvea0[731] = _4440; + uint16_t _4441 = (uint16_t)(227); + _curvea0[732] = _4441; + uint16_t _4442 = (uint16_t)(227); + _curvea0[733] = _4442; + uint16_t _4443 = (uint16_t)(228); + _curvea0[734] = _4443; + uint16_t _4444 = (uint16_t)(228); + _curvea0[735] = _4444; + uint16_t _4445 = (uint16_t)(228); + _curvea0[736] = _4445; + uint16_t _4446 = (uint16_t)(228); + _curvea0[737] = _4446; + uint16_t _4447 = (uint16_t)(228); + _curvea0[738] = _4447; + uint16_t _4448 = (uint16_t)(228); + _curvea0[739] = _4448; + uint16_t _4449 = (uint16_t)(228); + _curvea0[740] = _4449; + uint16_t _4450 = (uint16_t)(228); + _curvea0[741] = _4450; + uint16_t _4451 = (uint16_t)(228); + _curvea0[742] = _4451; + uint16_t _4452 = (uint16_t)(229); + _curvea0[743] = _4452; + uint16_t _4453 = (uint16_t)(229); + _curvea0[744] = _4453; + uint16_t _4454 = (uint16_t)(229); + _curvea0[745] = _4454; + uint16_t _4455 = (uint16_t)(229); + _curvea0[746] = _4455; + uint16_t _4456 = (uint16_t)(229); + _curvea0[747] = _4456; + uint16_t _4457 = (uint16_t)(229); + _curvea0[748] = _4457; + uint16_t _4458 = (uint16_t)(229); + _curvea0[749] = _4458; + uint16_t _4459 = (uint16_t)(229); + _curvea0[750] = _4459; + uint16_t _4460 = (uint16_t)(230); + _curvea0[751] = _4460; + uint16_t _4461 = (uint16_t)(230); + _curvea0[752] = _4461; + uint16_t _4462 = (uint16_t)(230); + _curvea0[753] = _4462; + uint16_t _4463 = (uint16_t)(230); + _curvea0[754] = _4463; + uint16_t _4464 = (uint16_t)(230); + _curvea0[755] = _4464; + uint16_t _4465 = (uint16_t)(230); + _curvea0[756] = _4465; + uint16_t _4466 = (uint16_t)(230); + _curvea0[757] = _4466; + uint16_t _4467 = (uint16_t)(230); + _curvea0[758] = _4467; + uint16_t _4468 = (uint16_t)(231); + _curvea0[759] = _4468; + uint16_t _4469 = (uint16_t)(231); + _curvea0[760] = _4469; + uint16_t _4470 = (uint16_t)(231); + _curvea0[761] = _4470; + uint16_t _4471 = (uint16_t)(231); + _curvea0[762] = _4471; + uint16_t _4472 = (uint16_t)(231); + _curvea0[763] = _4472; + uint16_t _4473 = (uint16_t)(231); + _curvea0[764] = _4473; + uint16_t _4474 = (uint16_t)(231); + _curvea0[765] = _4474; + uint16_t _4475 = (uint16_t)(231); + _curvea0[766] = _4475; + uint16_t _4476 = (uint16_t)(231); + _curvea0[767] = _4476; + uint16_t _4477 = (uint16_t)(232); + _curvea0[768] = _4477; + uint16_t _4478 = (uint16_t)(232); + _curvea0[769] = _4478; + uint16_t _4479 = (uint16_t)(232); + _curvea0[770] = _4479; + uint16_t _4480 = (uint16_t)(232); + _curvea0[771] = _4480; + uint16_t _4481 = (uint16_t)(232); + _curvea0[772] = _4481; + uint16_t _4482 = (uint16_t)(232); + _curvea0[773] = _4482; + uint16_t _4483 = (uint16_t)(232); + _curvea0[774] = _4483; + uint16_t _4484 = (uint16_t)(232); + _curvea0[775] = _4484; + uint16_t _4485 = (uint16_t)(233); + _curvea0[776] = _4485; + uint16_t _4486 = (uint16_t)(233); + _curvea0[777] = _4486; + uint16_t _4487 = (uint16_t)(233); + _curvea0[778] = _4487; + uint16_t _4488 = (uint16_t)(233); + _curvea0[779] = _4488; + uint16_t _4489 = (uint16_t)(233); + _curvea0[780] = _4489; + uint16_t _4490 = (uint16_t)(233); + _curvea0[781] = _4490; + uint16_t _4491 = (uint16_t)(233); + _curvea0[782] = _4491; + uint16_t _4492 = (uint16_t)(233); + _curvea0[783] = _4492; + uint16_t _4493 = (uint16_t)(233); + _curvea0[784] = _4493; + uint16_t _4494 = (uint16_t)(234); + _curvea0[785] = _4494; + uint16_t _4495 = (uint16_t)(234); + _curvea0[786] = _4495; + uint16_t _4496 = (uint16_t)(234); + _curvea0[787] = _4496; + uint16_t _4497 = (uint16_t)(234); + _curvea0[788] = _4497; + uint16_t _4498 = (uint16_t)(234); + _curvea0[789] = _4498; + uint16_t _4499 = (uint16_t)(234); + _curvea0[790] = _4499; + uint16_t _4500 = (uint16_t)(234); + _curvea0[791] = _4500; + uint16_t _4501 = (uint16_t)(234); + _curvea0[792] = _4501; + uint16_t _4502 = (uint16_t)(234); + _curvea0[793] = _4502; + uint16_t _4503 = (uint16_t)(235); + _curvea0[794] = _4503; + uint16_t _4504 = (uint16_t)(235); + _curvea0[795] = _4504; + uint16_t _4505 = (uint16_t)(235); + _curvea0[796] = _4505; + uint16_t _4506 = (uint16_t)(235); + _curvea0[797] = _4506; + uint16_t _4507 = (uint16_t)(235); + _curvea0[798] = _4507; + uint16_t _4508 = (uint16_t)(235); + _curvea0[799] = _4508; + uint16_t _4509 = (uint16_t)(235); + _curvea0[800] = _4509; + uint16_t _4510 = (uint16_t)(235); + _curvea0[801] = _4510; + uint16_t _4511 = (uint16_t)(235); + _curvea0[802] = _4511; + uint16_t _4512 = (uint16_t)(236); + _curvea0[803] = _4512; + uint16_t _4513 = (uint16_t)(236); + _curvea0[804] = _4513; + uint16_t _4514 = (uint16_t)(236); + _curvea0[805] = _4514; + uint16_t _4515 = (uint16_t)(236); + _curvea0[806] = _4515; + uint16_t _4516 = (uint16_t)(236); + _curvea0[807] = _4516; + uint16_t _4517 = (uint16_t)(236); + _curvea0[808] = _4517; + uint16_t _4518 = (uint16_t)(236); + _curvea0[809] = _4518; + uint16_t _4519 = (uint16_t)(236); + _curvea0[810] = _4519; + uint16_t _4520 = (uint16_t)(236); + _curvea0[811] = _4520; + uint16_t _4521 = (uint16_t)(237); + _curvea0[812] = _4521; + uint16_t _4522 = (uint16_t)(237); + _curvea0[813] = _4522; + uint16_t _4523 = (uint16_t)(237); + _curvea0[814] = _4523; + uint16_t _4524 = (uint16_t)(237); + _curvea0[815] = _4524; + uint16_t _4525 = (uint16_t)(237); + _curvea0[816] = _4525; + uint16_t _4526 = (uint16_t)(237); + _curvea0[817] = _4526; + uint16_t _4527 = (uint16_t)(237); + _curvea0[818] = _4527; + uint16_t _4528 = (uint16_t)(237); + _curvea0[819] = _4528; + uint16_t _4529 = (uint16_t)(237); + _curvea0[820] = _4529; + uint16_t _4530 = (uint16_t)(237); + _curvea0[821] = _4530; + uint16_t _4531 = (uint16_t)(238); + _curvea0[822] = _4531; + uint16_t _4532 = (uint16_t)(238); + _curvea0[823] = _4532; + uint16_t _4533 = (uint16_t)(238); + _curvea0[824] = _4533; + uint16_t _4534 = (uint16_t)(238); + _curvea0[825] = _4534; + uint16_t _4535 = (uint16_t)(238); + _curvea0[826] = _4535; + uint16_t _4536 = (uint16_t)(238); + _curvea0[827] = _4536; + uint16_t _4537 = (uint16_t)(238); + _curvea0[828] = _4537; + uint16_t _4538 = (uint16_t)(238); + _curvea0[829] = _4538; + uint16_t _4539 = (uint16_t)(238); + _curvea0[830] = _4539; + uint16_t _4540 = (uint16_t)(239); + _curvea0[831] = _4540; + uint16_t _4541 = (uint16_t)(239); + _curvea0[832] = _4541; + uint16_t _4542 = (uint16_t)(239); + _curvea0[833] = _4542; + uint16_t _4543 = (uint16_t)(239); + _curvea0[834] = _4543; + uint16_t _4544 = (uint16_t)(239); + _curvea0[835] = _4544; + uint16_t _4545 = (uint16_t)(239); + _curvea0[836] = _4545; + uint16_t _4546 = (uint16_t)(239); + _curvea0[837] = _4546; + uint16_t _4547 = (uint16_t)(239); + _curvea0[838] = _4547; + uint16_t _4548 = (uint16_t)(239); + _curvea0[839] = _4548; + uint16_t _4549 = (uint16_t)(239); + _curvea0[840] = _4549; + uint16_t _4550 = (uint16_t)(240); + _curvea0[841] = _4550; + uint16_t _4551 = (uint16_t)(240); + _curvea0[842] = _4551; + uint16_t _4552 = (uint16_t)(240); + _curvea0[843] = _4552; + uint16_t _4553 = (uint16_t)(240); + _curvea0[844] = _4553; + uint16_t _4554 = (uint16_t)(240); + _curvea0[845] = _4554; + uint16_t _4555 = (uint16_t)(240); + _curvea0[846] = _4555; + uint16_t _4556 = (uint16_t)(240); + _curvea0[847] = _4556; + uint16_t _4557 = (uint16_t)(240); + _curvea0[848] = _4557; + uint16_t _4558 = (uint16_t)(240); + _curvea0[849] = _4558; + uint16_t _4559 = (uint16_t)(240); + _curvea0[850] = _4559; + uint16_t _4560 = (uint16_t)(241); + _curvea0[851] = _4560; + uint16_t _4561 = (uint16_t)(241); + _curvea0[852] = _4561; + uint16_t _4562 = (uint16_t)(241); + _curvea0[853] = _4562; + uint16_t _4563 = (uint16_t)(241); + _curvea0[854] = _4563; + uint16_t _4564 = (uint16_t)(241); + _curvea0[855] = _4564; + uint16_t _4565 = (uint16_t)(241); + _curvea0[856] = _4565; + uint16_t _4566 = (uint16_t)(241); + _curvea0[857] = _4566; + uint16_t _4567 = (uint16_t)(241); + _curvea0[858] = _4567; + uint16_t _4568 = (uint16_t)(241); + _curvea0[859] = _4568; + uint16_t _4569 = (uint16_t)(241); + _curvea0[860] = _4569; + uint16_t _4570 = (uint16_t)(242); + _curvea0[861] = _4570; + uint16_t _4571 = (uint16_t)(242); + _curvea0[862] = _4571; + uint16_t _4572 = (uint16_t)(242); + _curvea0[863] = _4572; + uint16_t _4573 = (uint16_t)(242); + _curvea0[864] = _4573; + uint16_t _4574 = (uint16_t)(242); + _curvea0[865] = _4574; + uint16_t _4575 = (uint16_t)(242); + _curvea0[866] = _4575; + uint16_t _4576 = (uint16_t)(242); + _curvea0[867] = _4576; + uint16_t _4577 = (uint16_t)(242); + _curvea0[868] = _4577; + uint16_t _4578 = (uint16_t)(242); + _curvea0[869] = _4578; + uint16_t _4579 = (uint16_t)(242); + _curvea0[870] = _4579; + uint16_t _4580 = (uint16_t)(243); + _curvea0[871] = _4580; + uint16_t _4581 = (uint16_t)(243); + _curvea0[872] = _4581; + uint16_t _4582 = (uint16_t)(243); + _curvea0[873] = _4582; + uint16_t _4583 = (uint16_t)(243); + _curvea0[874] = _4583; + uint16_t _4584 = (uint16_t)(243); + _curvea0[875] = _4584; + uint16_t _4585 = (uint16_t)(243); + _curvea0[876] = _4585; + uint16_t _4586 = (uint16_t)(243); + _curvea0[877] = _4586; + uint16_t _4587 = (uint16_t)(243); + _curvea0[878] = _4587; + uint16_t _4588 = (uint16_t)(243); + _curvea0[879] = _4588; + uint16_t _4589 = (uint16_t)(243); + _curvea0[880] = _4589; + uint16_t _4590 = (uint16_t)(244); + _curvea0[881] = _4590; + uint16_t _4591 = (uint16_t)(244); + _curvea0[882] = _4591; + uint16_t _4592 = (uint16_t)(244); + _curvea0[883] = _4592; + uint16_t _4593 = (uint16_t)(244); + _curvea0[884] = _4593; + uint16_t _4594 = (uint16_t)(244); + _curvea0[885] = _4594; + uint16_t _4595 = (uint16_t)(244); + _curvea0[886] = _4595; + uint16_t _4596 = (uint16_t)(244); + _curvea0[887] = _4596; + uint16_t _4597 = (uint16_t)(244); + _curvea0[888] = _4597; + uint16_t _4598 = (uint16_t)(244); + _curvea0[889] = _4598; + uint16_t _4599 = (uint16_t)(244); + _curvea0[890] = _4599; + uint16_t _4600 = (uint16_t)(244); + _curvea0[891] = _4600; + uint16_t _4601 = (uint16_t)(245); + _curvea0[892] = _4601; + uint16_t _4602 = (uint16_t)(245); + _curvea0[893] = _4602; + uint16_t _4603 = (uint16_t)(245); + _curvea0[894] = _4603; + uint16_t _4604 = (uint16_t)(245); + _curvea0[895] = _4604; + uint16_t _4605 = (uint16_t)(245); + _curvea0[896] = _4605; + uint16_t _4606 = (uint16_t)(245); + _curvea0[897] = _4606; + uint16_t _4607 = (uint16_t)(245); + _curvea0[898] = _4607; + uint16_t _4608 = (uint16_t)(245); + _curvea0[899] = _4608; + uint16_t _4609 = (uint16_t)(245); + _curvea0[900] = _4609; + uint16_t _4610 = (uint16_t)(245); + _curvea0[901] = _4610; + uint16_t _4611 = (uint16_t)(245); + _curvea0[902] = _4611; + uint16_t _4612 = (uint16_t)(246); + _curvea0[903] = _4612; + uint16_t _4613 = (uint16_t)(246); + _curvea0[904] = _4613; + uint16_t _4614 = (uint16_t)(246); + _curvea0[905] = _4614; + uint16_t _4615 = (uint16_t)(246); + _curvea0[906] = _4615; + uint16_t _4616 = (uint16_t)(246); + _curvea0[907] = _4616; + uint16_t _4617 = (uint16_t)(246); + _curvea0[908] = _4617; + uint16_t _4618 = (uint16_t)(246); + _curvea0[909] = _4618; + uint16_t _4619 = (uint16_t)(246); + _curvea0[910] = _4619; + uint16_t _4620 = (uint16_t)(246); + _curvea0[911] = _4620; + uint16_t _4621 = (uint16_t)(246); + _curvea0[912] = _4621; + uint16_t _4622 = (uint16_t)(246); + _curvea0[913] = _4622; + uint16_t _4623 = (uint16_t)(247); + _curvea0[914] = _4623; + uint16_t _4624 = (uint16_t)(247); + _curvea0[915] = _4624; + uint16_t _4625 = (uint16_t)(247); + _curvea0[916] = _4625; + uint16_t _4626 = (uint16_t)(247); + _curvea0[917] = _4626; + uint16_t _4627 = (uint16_t)(247); + _curvea0[918] = _4627; + uint16_t _4628 = (uint16_t)(247); + _curvea0[919] = _4628; + uint16_t _4629 = (uint16_t)(247); + _curvea0[920] = _4629; + uint16_t _4630 = (uint16_t)(247); + _curvea0[921] = _4630; + uint16_t _4631 = (uint16_t)(247); + _curvea0[922] = _4631; + uint16_t _4632 = (uint16_t)(247); + _curvea0[923] = _4632; + uint16_t _4633 = (uint16_t)(247); + _curvea0[924] = _4633; + uint16_t _4634 = (uint16_t)(248); + _curvea0[925] = _4634; + uint16_t _4635 = (uint16_t)(248); + _curvea0[926] = _4635; + uint16_t _4636 = (uint16_t)(248); + _curvea0[927] = _4636; + uint16_t _4637 = (uint16_t)(248); + _curvea0[928] = _4637; + uint16_t _4638 = (uint16_t)(248); + _curvea0[929] = _4638; + uint16_t _4639 = (uint16_t)(248); + _curvea0[930] = _4639; + uint16_t _4640 = (uint16_t)(248); + _curvea0[931] = _4640; + uint16_t _4641 = (uint16_t)(248); + _curvea0[932] = _4641; + uint16_t _4642 = (uint16_t)(248); + _curvea0[933] = _4642; + uint16_t _4643 = (uint16_t)(248); + _curvea0[934] = _4643; + uint16_t _4644 = (uint16_t)(248); + _curvea0[935] = _4644; + uint16_t _4645 = (uint16_t)(249); + _curvea0[936] = _4645; + uint16_t _4646 = (uint16_t)(249); + _curvea0[937] = _4646; + uint16_t _4647 = (uint16_t)(249); + _curvea0[938] = _4647; + uint16_t _4648 = (uint16_t)(249); + _curvea0[939] = _4648; + uint16_t _4649 = (uint16_t)(249); + _curvea0[940] = _4649; + uint16_t _4650 = (uint16_t)(249); + _curvea0[941] = _4650; + uint16_t _4651 = (uint16_t)(249); + _curvea0[942] = _4651; + uint16_t _4652 = (uint16_t)(249); + _curvea0[943] = _4652; + uint16_t _4653 = (uint16_t)(249); + _curvea0[944] = _4653; + uint16_t _4654 = (uint16_t)(249); + _curvea0[945] = _4654; + uint16_t _4655 = (uint16_t)(249); + _curvea0[946] = _4655; + uint16_t _4656 = (uint16_t)(249); + _curvea0[947] = _4656; + uint16_t _4657 = (uint16_t)(250); + _curvea0[948] = _4657; + uint16_t _4658 = (uint16_t)(250); + _curvea0[949] = _4658; + uint16_t _4659 = (uint16_t)(250); + _curvea0[950] = _4659; + uint16_t _4660 = (uint16_t)(250); + _curvea0[951] = _4660; + uint16_t _4661 = (uint16_t)(250); + _curvea0[952] = _4661; + uint16_t _4662 = (uint16_t)(250); + _curvea0[953] = _4662; + uint16_t _4663 = (uint16_t)(250); + _curvea0[954] = _4663; + uint16_t _4664 = (uint16_t)(250); + _curvea0[955] = _4664; + uint16_t _4665 = (uint16_t)(250); + _curvea0[956] = _4665; + uint16_t _4666 = (uint16_t)(250); + _curvea0[957] = _4666; + uint16_t _4667 = (uint16_t)(250); + _curvea0[958] = _4667; + uint16_t _4668 = (uint16_t)(250); + _curvea0[959] = _4668; + uint16_t _4669 = (uint16_t)(251); + _curvea0[960] = _4669; + uint16_t _4670 = (uint16_t)(251); + _curvea0[961] = _4670; + uint16_t _4671 = (uint16_t)(251); + _curvea0[962] = _4671; + uint16_t _4672 = (uint16_t)(251); + _curvea0[963] = _4672; + uint16_t _4673 = (uint16_t)(251); + _curvea0[964] = _4673; + uint16_t _4674 = (uint16_t)(251); + _curvea0[965] = _4674; + uint16_t _4675 = (uint16_t)(251); + _curvea0[966] = _4675; + uint16_t _4676 = (uint16_t)(251); + _curvea0[967] = _4676; + uint16_t _4677 = (uint16_t)(251); + _curvea0[968] = _4677; + uint16_t _4678 = (uint16_t)(251); + _curvea0[969] = _4678; + uint16_t _4679 = (uint16_t)(251); + _curvea0[970] = _4679; + uint16_t _4680 = (uint16_t)(251); + _curvea0[971] = _4680; + uint16_t _4681 = (uint16_t)(252); + _curvea0[972] = _4681; + uint16_t _4682 = (uint16_t)(252); + _curvea0[973] = _4682; + uint16_t _4683 = (uint16_t)(252); + _curvea0[974] = _4683; + uint16_t _4684 = (uint16_t)(252); + _curvea0[975] = _4684; + uint16_t _4685 = (uint16_t)(252); + _curvea0[976] = _4685; + uint16_t _4686 = (uint16_t)(252); + _curvea0[977] = _4686; + uint16_t _4687 = (uint16_t)(252); + _curvea0[978] = _4687; + uint16_t _4688 = (uint16_t)(252); + _curvea0[979] = _4688; + uint16_t _4689 = (uint16_t)(252); + _curvea0[980] = _4689; + uint16_t _4690 = (uint16_t)(252); + _curvea0[981] = _4690; + uint16_t _4691 = (uint16_t)(252); + _curvea0[982] = _4691; + uint16_t _4692 = (uint16_t)(252); + _curvea0[983] = _4692; + uint16_t _4693 = (uint16_t)(252); + _curvea0[984] = _4693; + uint16_t _4694 = (uint16_t)(253); + _curvea0[985] = _4694; + uint16_t _4695 = (uint16_t)(253); + _curvea0[986] = _4695; + uint16_t _4696 = (uint16_t)(253); + _curvea0[987] = _4696; + uint16_t _4697 = (uint16_t)(253); + _curvea0[988] = _4697; + uint16_t _4698 = (uint16_t)(253); + _curvea0[989] = _4698; + uint16_t _4699 = (uint16_t)(253); + _curvea0[990] = _4699; + uint16_t _4700 = (uint16_t)(253); + _curvea0[991] = _4700; + uint16_t _4701 = (uint16_t)(253); + _curvea0[992] = _4701; + uint16_t _4702 = (uint16_t)(253); + _curvea0[993] = _4702; + uint16_t _4703 = (uint16_t)(253); + _curvea0[994] = _4703; + uint16_t _4704 = (uint16_t)(253); + _curvea0[995] = _4704; + uint16_t _4705 = (uint16_t)(253); + _curvea0[996] = _4705; + uint16_t _4706 = (uint16_t)(253); + _curvea0[997] = _4706; + uint16_t _4707 = (uint16_t)(254); + _curvea0[998] = _4707; + uint16_t _4708 = (uint16_t)(254); + _curvea0[999] = _4708; + uint16_t _4709 = (uint16_t)(254); + _curvea0[1000] = _4709; + uint16_t _4710 = (uint16_t)(254); + _curvea0[1001] = _4710; + uint16_t _4711 = (uint16_t)(254); + _curvea0[1002] = _4711; + uint16_t _4712 = (uint16_t)(254); + _curvea0[1003] = _4712; + uint16_t _4713 = (uint16_t)(254); + _curvea0[1004] = _4713; + uint16_t _4714 = (uint16_t)(254); + _curvea0[1005] = _4714; + uint16_t _4715 = (uint16_t)(254); + _curvea0[1006] = _4715; + uint16_t _4716 = (uint16_t)(254); + _curvea0[1007] = _4716; + uint16_t _4717 = (uint16_t)(254); + _curvea0[1008] = _4717; + uint16_t _4718 = (uint16_t)(254); + _curvea0[1009] = _4718; + uint16_t _4719 = (uint16_t)(254); + _curvea0[1010] = _4719; + uint16_t _4720 = (uint16_t)(255); + _curvea0[1011] = _4720; + uint16_t _4721 = (uint16_t)(255); + _curvea0[1012] = _4721; + uint16_t _4722 = (uint16_t)(255); + _curvea0[1013] = _4722; + uint16_t _4723 = (uint16_t)(255); + _curvea0[1014] = _4723; + uint16_t _4724 = (uint16_t)(255); + _curvea0[1015] = _4724; + uint16_t _4725 = (uint16_t)(255); + _curvea0[1016] = _4725; + uint16_t _4726 = (uint16_t)(255); + _curvea0[1017] = _4726; + uint16_t _4727 = (uint16_t)(255); + _curvea0[1018] = _4727; + uint16_t _4728 = (uint16_t)(255); + _curvea0[1019] = _4728; + uint16_t _4729 = (uint16_t)(255); + _curvea0[1020] = _4729; + uint16_t _4730 = (uint16_t)(255); + _curvea0[1021] = _4730; + uint16_t _4731 = (uint16_t)(255); + _curvea0[1022] = _4731; + uint16_t _4732 = (uint16_t)(255); + _curvea0[1023] = _4732; + + int16_t _4733 = (int16_t)(1023); + int16_t _4734 = min(_corrected_stencil_2, _4733); + int16_t _4735 = (int16_t)(0); + int16_t _4736 = max(_4734, _4735); + uint16_t _4737 = (uint16_t)(_4736); + int32_t _4738 = (int32_t)(_4737); + uint16_t _4739 = ((const uint16_t *)_curvea0)[_4738]; + return _4739; +} + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_2(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_3 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _4756 = (uint16_t)(0); + _curvea0[0] = _4756; + uint16_t _4757 = (uint16_t)(4); + _curvea0[1] = _4757; + uint16_t _4758 = (uint16_t)(7); + _curvea0[2] = _4758; + uint16_t _4759 = (uint16_t)(8); + _curvea0[3] = _4759; + uint16_t _4760 = (uint16_t)(10); + _curvea0[4] = _4760; + uint16_t _4761 = (uint16_t)(11); + _curvea0[5] = _4761; + uint16_t _4762 = (uint16_t)(12); + _curvea0[6] = _4762; + uint16_t _4763 = (uint16_t)(13); + _curvea0[7] = _4763; + uint16_t _4764 = (uint16_t)(14); + _curvea0[8] = _4764; + uint16_t _4765 = (uint16_t)(15); + _curvea0[9] = _4765; + uint16_t _4766 = (uint16_t)(16); + _curvea0[10] = _4766; + uint16_t _4767 = (uint16_t)(17); + _curvea0[11] = _4767; + uint16_t _4768 = (uint16_t)(18); + _curvea0[12] = _4768; + uint16_t _4769 = (uint16_t)(19); + _curvea0[13] = _4769; + uint16_t _4770 = (uint16_t)(20); + _curvea0[14] = _4770; + uint16_t _4771 = (uint16_t)(21); + _curvea0[15] = _4771; + uint16_t _4772 = (uint16_t)(22); + _curvea0[16] = _4772; + uint16_t _4773 = (uint16_t)(22); + _curvea0[17] = _4773; + uint16_t _4774 = (uint16_t)(23); + _curvea0[18] = _4774; + uint16_t _4775 = (uint16_t)(24); + _curvea0[19] = _4775; + uint16_t _4776 = (uint16_t)(25); + _curvea0[20] = _4776; + uint16_t _4777 = (uint16_t)(25); + _curvea0[21] = _4777; + uint16_t _4778 = (uint16_t)(26); + _curvea0[22] = _4778; + uint16_t _4779 = (uint16_t)(27); + _curvea0[23] = _4779; + uint16_t _4780 = (uint16_t)(27); + _curvea0[24] = _4780; + uint16_t _4781 = (uint16_t)(28); + _curvea0[25] = _4781; + uint16_t _4782 = (uint16_t)(29); + _curvea0[26] = _4782; + uint16_t _4783 = (uint16_t)(29); + _curvea0[27] = _4783; + uint16_t _4784 = (uint16_t)(30); + _curvea0[28] = _4784; + uint16_t _4785 = (uint16_t)(31); + _curvea0[29] = _4785; + uint16_t _4786 = (uint16_t)(31); + _curvea0[30] = _4786; + uint16_t _4787 = (uint16_t)(32); + _curvea0[31] = _4787; + uint16_t _4788 = (uint16_t)(33); + _curvea0[32] = _4788; + uint16_t _4789 = (uint16_t)(33); + _curvea0[33] = _4789; + uint16_t _4790 = (uint16_t)(34); + _curvea0[34] = _4790; + uint16_t _4791 = (uint16_t)(34); + _curvea0[35] = _4791; + uint16_t _4792 = (uint16_t)(35); + _curvea0[36] = _4792; + uint16_t _4793 = (uint16_t)(36); + _curvea0[37] = _4793; + uint16_t _4794 = (uint16_t)(36); + _curvea0[38] = _4794; + uint16_t _4795 = (uint16_t)(37); + _curvea0[39] = _4795; + uint16_t _4796 = (uint16_t)(37); + _curvea0[40] = _4796; + uint16_t _4797 = (uint16_t)(38); + _curvea0[41] = _4797; + uint16_t _4798 = (uint16_t)(39); + _curvea0[42] = _4798; + uint16_t _4799 = (uint16_t)(39); + _curvea0[43] = _4799; + uint16_t _4800 = (uint16_t)(40); + _curvea0[44] = _4800; + uint16_t _4801 = (uint16_t)(40); + _curvea0[45] = _4801; + uint16_t _4802 = (uint16_t)(41); + _curvea0[46] = _4802; + uint16_t _4803 = (uint16_t)(41); + _curvea0[47] = _4803; + uint16_t _4804 = (uint16_t)(42); + _curvea0[48] = _4804; + uint16_t _4805 = (uint16_t)(42); + _curvea0[49] = _4805; + uint16_t _4806 = (uint16_t)(43); + _curvea0[50] = _4806; + uint16_t _4807 = (uint16_t)(44); + _curvea0[51] = _4807; + uint16_t _4808 = (uint16_t)(44); + _curvea0[52] = _4808; + uint16_t _4809 = (uint16_t)(45); + _curvea0[53] = _4809; + uint16_t _4810 = (uint16_t)(45); + _curvea0[54] = _4810; + uint16_t _4811 = (uint16_t)(46); + _curvea0[55] = _4811; + uint16_t _4812 = (uint16_t)(46); + _curvea0[56] = _4812; + uint16_t _4813 = (uint16_t)(47); + _curvea0[57] = _4813; + uint16_t _4814 = (uint16_t)(47); + _curvea0[58] = _4814; + uint16_t _4815 = (uint16_t)(48); + _curvea0[59] = _4815; + uint16_t _4816 = (uint16_t)(48); + _curvea0[60] = _4816; + uint16_t _4817 = (uint16_t)(49); + _curvea0[61] = _4817; + uint16_t _4818 = (uint16_t)(49); + _curvea0[62] = _4818; + uint16_t _4819 = (uint16_t)(50); + _curvea0[63] = _4819; + uint16_t _4820 = (uint16_t)(50); + _curvea0[64] = _4820; + uint16_t _4821 = (uint16_t)(51); + _curvea0[65] = _4821; + uint16_t _4822 = (uint16_t)(51); + _curvea0[66] = _4822; + uint16_t _4823 = (uint16_t)(52); + _curvea0[67] = _4823; + uint16_t _4824 = (uint16_t)(52); + _curvea0[68] = _4824; + uint16_t _4825 = (uint16_t)(53); + _curvea0[69] = _4825; + uint16_t _4826 = (uint16_t)(53); + _curvea0[70] = _4826; + uint16_t _4827 = (uint16_t)(54); + _curvea0[71] = _4827; + uint16_t _4828 = (uint16_t)(54); + _curvea0[72] = _4828; + uint16_t _4829 = (uint16_t)(55); + _curvea0[73] = _4829; + uint16_t _4830 = (uint16_t)(55); + _curvea0[74] = _4830; + uint16_t _4831 = (uint16_t)(56); + _curvea0[75] = _4831; + uint16_t _4832 = (uint16_t)(56); + _curvea0[76] = _4832; + uint16_t _4833 = (uint16_t)(57); + _curvea0[77] = _4833; + uint16_t _4834 = (uint16_t)(57); + _curvea0[78] = _4834; + uint16_t _4835 = (uint16_t)(58); + _curvea0[79] = _4835; + uint16_t _4836 = (uint16_t)(58); + _curvea0[80] = _4836; + uint16_t _4837 = (uint16_t)(58); + _curvea0[81] = _4837; + uint16_t _4838 = (uint16_t)(59); + _curvea0[82] = _4838; + uint16_t _4839 = (uint16_t)(59); + _curvea0[83] = _4839; + uint16_t _4840 = (uint16_t)(60); + _curvea0[84] = _4840; + uint16_t _4841 = (uint16_t)(60); + _curvea0[85] = _4841; + uint16_t _4842 = (uint16_t)(61); + _curvea0[86] = _4842; + uint16_t _4843 = (uint16_t)(61); + _curvea0[87] = _4843; + uint16_t _4844 = (uint16_t)(62); + _curvea0[88] = _4844; + uint16_t _4845 = (uint16_t)(62); + _curvea0[89] = _4845; + uint16_t _4846 = (uint16_t)(63); + _curvea0[90] = _4846; + uint16_t _4847 = (uint16_t)(63); + _curvea0[91] = _4847; + uint16_t _4848 = (uint16_t)(64); + _curvea0[92] = _4848; + uint16_t _4849 = (uint16_t)(64); + _curvea0[93] = _4849; + uint16_t _4850 = (uint16_t)(64); + _curvea0[94] = _4850; + uint16_t _4851 = (uint16_t)(65); + _curvea0[95] = _4851; + uint16_t _4852 = (uint16_t)(65); + _curvea0[96] = _4852; + uint16_t _4853 = (uint16_t)(66); + _curvea0[97] = _4853; + uint16_t _4854 = (uint16_t)(66); + _curvea0[98] = _4854; + uint16_t _4855 = (uint16_t)(67); + _curvea0[99] = _4855; + uint16_t _4856 = (uint16_t)(67); + _curvea0[100] = _4856; + uint16_t _4857 = (uint16_t)(68); + _curvea0[101] = _4857; + uint16_t _4858 = (uint16_t)(68); + _curvea0[102] = _4858; + uint16_t _4859 = (uint16_t)(68); + _curvea0[103] = _4859; + uint16_t _4860 = (uint16_t)(69); + _curvea0[104] = _4860; + uint16_t _4861 = (uint16_t)(69); + _curvea0[105] = _4861; + uint16_t _4862 = (uint16_t)(70); + _curvea0[106] = _4862; + uint16_t _4863 = (uint16_t)(70); + _curvea0[107] = _4863; + uint16_t _4864 = (uint16_t)(71); + _curvea0[108] = _4864; + uint16_t _4865 = (uint16_t)(71); + _curvea0[109] = _4865; + uint16_t _4866 = (uint16_t)(71); + _curvea0[110] = _4866; + uint16_t _4867 = (uint16_t)(72); + _curvea0[111] = _4867; + uint16_t _4868 = (uint16_t)(72); + _curvea0[112] = _4868; + uint16_t _4869 = (uint16_t)(73); + _curvea0[113] = _4869; + uint16_t _4870 = (uint16_t)(73); + _curvea0[114] = _4870; + uint16_t _4871 = (uint16_t)(74); + _curvea0[115] = _4871; + uint16_t _4872 = (uint16_t)(74); + _curvea0[116] = _4872; + uint16_t _4873 = (uint16_t)(74); + _curvea0[117] = _4873; + uint16_t _4874 = (uint16_t)(75); + _curvea0[118] = _4874; + uint16_t _4875 = (uint16_t)(75); + _curvea0[119] = _4875; + uint16_t _4876 = (uint16_t)(76); + _curvea0[120] = _4876; + uint16_t _4877 = (uint16_t)(76); + _curvea0[121] = _4877; + uint16_t _4878 = (uint16_t)(77); + _curvea0[122] = _4878; + uint16_t _4879 = (uint16_t)(77); + _curvea0[123] = _4879; + uint16_t _4880 = (uint16_t)(77); + _curvea0[124] = _4880; + uint16_t _4881 = (uint16_t)(78); + _curvea0[125] = _4881; + uint16_t _4882 = (uint16_t)(78); + _curvea0[126] = _4882; + uint16_t _4883 = (uint16_t)(79); + _curvea0[127] = _4883; + uint16_t _4884 = (uint16_t)(79); + _curvea0[128] = _4884; + uint16_t _4885 = (uint16_t)(79); + _curvea0[129] = _4885; + uint16_t _4886 = (uint16_t)(80); + _curvea0[130] = _4886; + uint16_t _4887 = (uint16_t)(80); + _curvea0[131] = _4887; + uint16_t _4888 = (uint16_t)(81); + _curvea0[132] = _4888; + uint16_t _4889 = (uint16_t)(81); + _curvea0[133] = _4889; + uint16_t _4890 = (uint16_t)(82); + _curvea0[134] = _4890; + uint16_t _4891 = (uint16_t)(82); + _curvea0[135] = _4891; + uint16_t _4892 = (uint16_t)(82); + _curvea0[136] = _4892; + uint16_t _4893 = (uint16_t)(83); + _curvea0[137] = _4893; + uint16_t _4894 = (uint16_t)(83); + _curvea0[138] = _4894; + uint16_t _4895 = (uint16_t)(84); + _curvea0[139] = _4895; + uint16_t _4896 = (uint16_t)(84); + _curvea0[140] = _4896; + uint16_t _4897 = (uint16_t)(84); + _curvea0[141] = _4897; + uint16_t _4898 = (uint16_t)(85); + _curvea0[142] = _4898; + uint16_t _4899 = (uint16_t)(85); + _curvea0[143] = _4899; + uint16_t _4900 = (uint16_t)(86); + _curvea0[144] = _4900; + uint16_t _4901 = (uint16_t)(86); + _curvea0[145] = _4901; + uint16_t _4902 = (uint16_t)(86); + _curvea0[146] = _4902; + uint16_t _4903 = (uint16_t)(87); + _curvea0[147] = _4903; + uint16_t _4904 = (uint16_t)(87); + _curvea0[148] = _4904; + uint16_t _4905 = (uint16_t)(88); + _curvea0[149] = _4905; + uint16_t _4906 = (uint16_t)(88); + _curvea0[150] = _4906; + uint16_t _4907 = (uint16_t)(88); + _curvea0[151] = _4907; + uint16_t _4908 = (uint16_t)(89); + _curvea0[152] = _4908; + uint16_t _4909 = (uint16_t)(89); + _curvea0[153] = _4909; + uint16_t _4910 = (uint16_t)(90); + _curvea0[154] = _4910; + uint16_t _4911 = (uint16_t)(90); + _curvea0[155] = _4911; + uint16_t _4912 = (uint16_t)(90); + _curvea0[156] = _4912; + uint16_t _4913 = (uint16_t)(91); + _curvea0[157] = _4913; + uint16_t _4914 = (uint16_t)(91); + _curvea0[158] = _4914; + uint16_t _4915 = (uint16_t)(92); + _curvea0[159] = _4915; + uint16_t _4916 = (uint16_t)(92); + _curvea0[160] = _4916; + uint16_t _4917 = (uint16_t)(92); + _curvea0[161] = _4917; + uint16_t _4918 = (uint16_t)(93); + _curvea0[162] = _4918; + uint16_t _4919 = (uint16_t)(93); + _curvea0[163] = _4919; + uint16_t _4920 = (uint16_t)(93); + _curvea0[164] = _4920; + uint16_t _4921 = (uint16_t)(94); + _curvea0[165] = _4921; + uint16_t _4922 = (uint16_t)(94); + _curvea0[166] = _4922; + uint16_t _4923 = (uint16_t)(95); + _curvea0[167] = _4923; + uint16_t _4924 = (uint16_t)(95); + _curvea0[168] = _4924; + uint16_t _4925 = (uint16_t)(95); + _curvea0[169] = _4925; + uint16_t _4926 = (uint16_t)(96); + _curvea0[170] = _4926; + uint16_t _4927 = (uint16_t)(96); + _curvea0[171] = _4927; + uint16_t _4928 = (uint16_t)(97); + _curvea0[172] = _4928; + uint16_t _4929 = (uint16_t)(97); + _curvea0[173] = _4929; + uint16_t _4930 = (uint16_t)(97); + _curvea0[174] = _4930; + uint16_t _4931 = (uint16_t)(98); + _curvea0[175] = _4931; + uint16_t _4932 = (uint16_t)(98); + _curvea0[176] = _4932; + uint16_t _4933 = (uint16_t)(99); + _curvea0[177] = _4933; + uint16_t _4934 = (uint16_t)(99); + _curvea0[178] = _4934; + uint16_t _4935 = (uint16_t)(99); + _curvea0[179] = _4935; + uint16_t _4936 = (uint16_t)(100); + _curvea0[180] = _4936; + uint16_t _4937 = (uint16_t)(100); + _curvea0[181] = _4937; + uint16_t _4938 = (uint16_t)(100); + _curvea0[182] = _4938; + uint16_t _4939 = (uint16_t)(101); + _curvea0[183] = _4939; + uint16_t _4940 = (uint16_t)(101); + _curvea0[184] = _4940; + uint16_t _4941 = (uint16_t)(102); + _curvea0[185] = _4941; + uint16_t _4942 = (uint16_t)(102); + _curvea0[186] = _4942; + uint16_t _4943 = (uint16_t)(102); + _curvea0[187] = _4943; + uint16_t _4944 = (uint16_t)(103); + _curvea0[188] = _4944; + uint16_t _4945 = (uint16_t)(103); + _curvea0[189] = _4945; + uint16_t _4946 = (uint16_t)(103); + _curvea0[190] = _4946; + uint16_t _4947 = (uint16_t)(104); + _curvea0[191] = _4947; + uint16_t _4948 = (uint16_t)(104); + _curvea0[192] = _4948; + uint16_t _4949 = (uint16_t)(105); + _curvea0[193] = _4949; + uint16_t _4950 = (uint16_t)(105); + _curvea0[194] = _4950; + uint16_t _4951 = (uint16_t)(105); + _curvea0[195] = _4951; + uint16_t _4952 = (uint16_t)(106); + _curvea0[196] = _4952; + uint16_t _4953 = (uint16_t)(106); + _curvea0[197] = _4953; + uint16_t _4954 = (uint16_t)(106); + _curvea0[198] = _4954; + uint16_t _4955 = (uint16_t)(107); + _curvea0[199] = _4955; + uint16_t _4956 = (uint16_t)(107); + _curvea0[200] = _4956; + uint16_t _4957 = (uint16_t)(108); + _curvea0[201] = _4957; + uint16_t _4958 = (uint16_t)(108); + _curvea0[202] = _4958; + uint16_t _4959 = (uint16_t)(108); + _curvea0[203] = _4959; + uint16_t _4960 = (uint16_t)(109); + _curvea0[204] = _4960; + uint16_t _4961 = (uint16_t)(109); + _curvea0[205] = _4961; + uint16_t _4962 = (uint16_t)(109); + _curvea0[206] = _4962; + uint16_t _4963 = (uint16_t)(110); + _curvea0[207] = _4963; + uint16_t _4964 = (uint16_t)(110); + _curvea0[208] = _4964; + uint16_t _4965 = (uint16_t)(111); + _curvea0[209] = _4965; + uint16_t _4966 = (uint16_t)(111); + _curvea0[210] = _4966; + uint16_t _4967 = (uint16_t)(111); + _curvea0[211] = _4967; + uint16_t _4968 = (uint16_t)(112); + _curvea0[212] = _4968; + uint16_t _4969 = (uint16_t)(112); + _curvea0[213] = _4969; + uint16_t _4970 = (uint16_t)(112); + _curvea0[214] = _4970; + uint16_t _4971 = (uint16_t)(113); + _curvea0[215] = _4971; + uint16_t _4972 = (uint16_t)(113); + _curvea0[216] = _4972; + uint16_t _4973 = (uint16_t)(113); + _curvea0[217] = _4973; + uint16_t _4974 = (uint16_t)(114); + _curvea0[218] = _4974; + uint16_t _4975 = (uint16_t)(114); + _curvea0[219] = _4975; + uint16_t _4976 = (uint16_t)(115); + _curvea0[220] = _4976; + uint16_t _4977 = (uint16_t)(115); + _curvea0[221] = _4977; + uint16_t _4978 = (uint16_t)(115); + _curvea0[222] = _4978; + uint16_t _4979 = (uint16_t)(116); + _curvea0[223] = _4979; + uint16_t _4980 = (uint16_t)(116); + _curvea0[224] = _4980; + uint16_t _4981 = (uint16_t)(116); + _curvea0[225] = _4981; + uint16_t _4982 = (uint16_t)(117); + _curvea0[226] = _4982; + uint16_t _4983 = (uint16_t)(117); + _curvea0[227] = _4983; + uint16_t _4984 = (uint16_t)(117); + _curvea0[228] = _4984; + uint16_t _4985 = (uint16_t)(118); + _curvea0[229] = _4985; + uint16_t _4986 = (uint16_t)(118); + _curvea0[230] = _4986; + uint16_t _4987 = (uint16_t)(119); + _curvea0[231] = _4987; + uint16_t _4988 = (uint16_t)(119); + _curvea0[232] = _4988; + uint16_t _4989 = (uint16_t)(119); + _curvea0[233] = _4989; + uint16_t _4990 = (uint16_t)(120); + _curvea0[234] = _4990; + uint16_t _4991 = (uint16_t)(120); + _curvea0[235] = _4991; + uint16_t _4992 = (uint16_t)(120); + _curvea0[236] = _4992; + uint16_t _4993 = (uint16_t)(121); + _curvea0[237] = _4993; + uint16_t _4994 = (uint16_t)(121); + _curvea0[238] = _4994; + uint16_t _4995 = (uint16_t)(121); + _curvea0[239] = _4995; + uint16_t _4996 = (uint16_t)(122); + _curvea0[240] = _4996; + uint16_t _4997 = (uint16_t)(122); + _curvea0[241] = _4997; + uint16_t _4998 = (uint16_t)(123); + _curvea0[242] = _4998; + uint16_t _4999 = (uint16_t)(123); + _curvea0[243] = _4999; + uint16_t _5000 = (uint16_t)(123); + _curvea0[244] = _5000; + uint16_t _5001 = (uint16_t)(124); + _curvea0[245] = _5001; + uint16_t _5002 = (uint16_t)(124); + _curvea0[246] = _5002; + uint16_t _5003 = (uint16_t)(124); + _curvea0[247] = _5003; + uint16_t _5004 = (uint16_t)(125); + _curvea0[248] = _5004; + uint16_t _5005 = (uint16_t)(125); + _curvea0[249] = _5005; + uint16_t _5006 = (uint16_t)(125); + _curvea0[250] = _5006; + uint16_t _5007 = (uint16_t)(126); + _curvea0[251] = _5007; + uint16_t _5008 = (uint16_t)(126); + _curvea0[252] = _5008; + uint16_t _5009 = (uint16_t)(126); + _curvea0[253] = _5009; + uint16_t _5010 = (uint16_t)(127); + _curvea0[254] = _5010; + uint16_t _5011 = (uint16_t)(127); + _curvea0[255] = _5011; + uint16_t _5012 = (uint16_t)(128); + _curvea0[256] = _5012; + uint16_t _5013 = (uint16_t)(128); + _curvea0[257] = _5013; + uint16_t _5014 = (uint16_t)(128); + _curvea0[258] = _5014; + uint16_t _5015 = (uint16_t)(129); + _curvea0[259] = _5015; + uint16_t _5016 = (uint16_t)(129); + _curvea0[260] = _5016; + uint16_t _5017 = (uint16_t)(129); + _curvea0[261] = _5017; + uint16_t _5018 = (uint16_t)(130); + _curvea0[262] = _5018; + uint16_t _5019 = (uint16_t)(130); + _curvea0[263] = _5019; + uint16_t _5020 = (uint16_t)(130); + _curvea0[264] = _5020; + uint16_t _5021 = (uint16_t)(131); + _curvea0[265] = _5021; + uint16_t _5022 = (uint16_t)(131); + _curvea0[266] = _5022; + uint16_t _5023 = (uint16_t)(131); + _curvea0[267] = _5023; + uint16_t _5024 = (uint16_t)(132); + _curvea0[268] = _5024; + uint16_t _5025 = (uint16_t)(132); + _curvea0[269] = _5025; + uint16_t _5026 = (uint16_t)(132); + _curvea0[270] = _5026; + uint16_t _5027 = (uint16_t)(133); + _curvea0[271] = _5027; + uint16_t _5028 = (uint16_t)(133); + _curvea0[272] = _5028; + uint16_t _5029 = (uint16_t)(133); + _curvea0[273] = _5029; + uint16_t _5030 = (uint16_t)(134); + _curvea0[274] = _5030; + uint16_t _5031 = (uint16_t)(134); + _curvea0[275] = _5031; + uint16_t _5032 = (uint16_t)(134); + _curvea0[276] = _5032; + uint16_t _5033 = (uint16_t)(135); + _curvea0[277] = _5033; + uint16_t _5034 = (uint16_t)(135); + _curvea0[278] = _5034; + uint16_t _5035 = (uint16_t)(135); + _curvea0[279] = _5035; + uint16_t _5036 = (uint16_t)(136); + _curvea0[280] = _5036; + uint16_t _5037 = (uint16_t)(136); + _curvea0[281] = _5037; + uint16_t _5038 = (uint16_t)(136); + _curvea0[282] = _5038; + uint16_t _5039 = (uint16_t)(137); + _curvea0[283] = _5039; + uint16_t _5040 = (uint16_t)(137); + _curvea0[284] = _5040; + uint16_t _5041 = (uint16_t)(137); + _curvea0[285] = _5041; + uint16_t _5042 = (uint16_t)(138); + _curvea0[286] = _5042; + uint16_t _5043 = (uint16_t)(138); + _curvea0[287] = _5043; + uint16_t _5044 = (uint16_t)(138); + _curvea0[288] = _5044; + uint16_t _5045 = (uint16_t)(139); + _curvea0[289] = _5045; + uint16_t _5046 = (uint16_t)(139); + _curvea0[290] = _5046; + uint16_t _5047 = (uint16_t)(139); + _curvea0[291] = _5047; + uint16_t _5048 = (uint16_t)(140); + _curvea0[292] = _5048; + uint16_t _5049 = (uint16_t)(140); + _curvea0[293] = _5049; + uint16_t _5050 = (uint16_t)(140); + _curvea0[294] = _5050; + uint16_t _5051 = (uint16_t)(141); + _curvea0[295] = _5051; + uint16_t _5052 = (uint16_t)(141); + _curvea0[296] = _5052; + uint16_t _5053 = (uint16_t)(141); + _curvea0[297] = _5053; + uint16_t _5054 = (uint16_t)(141); + _curvea0[298] = _5054; + uint16_t _5055 = (uint16_t)(142); + _curvea0[299] = _5055; + uint16_t _5056 = (uint16_t)(142); + _curvea0[300] = _5056; + uint16_t _5057 = (uint16_t)(142); + _curvea0[301] = _5057; + uint16_t _5058 = (uint16_t)(143); + _curvea0[302] = _5058; + uint16_t _5059 = (uint16_t)(143); + _curvea0[303] = _5059; + uint16_t _5060 = (uint16_t)(143); + _curvea0[304] = _5060; + uint16_t _5061 = (uint16_t)(144); + _curvea0[305] = _5061; + uint16_t _5062 = (uint16_t)(144); + _curvea0[306] = _5062; + uint16_t _5063 = (uint16_t)(144); + _curvea0[307] = _5063; + uint16_t _5064 = (uint16_t)(145); + _curvea0[308] = _5064; + uint16_t _5065 = (uint16_t)(145); + _curvea0[309] = _5065; + uint16_t _5066 = (uint16_t)(145); + _curvea0[310] = _5066; + uint16_t _5067 = (uint16_t)(145); + _curvea0[311] = _5067; + uint16_t _5068 = (uint16_t)(146); + _curvea0[312] = _5068; + uint16_t _5069 = (uint16_t)(146); + _curvea0[313] = _5069; + uint16_t _5070 = (uint16_t)(146); + _curvea0[314] = _5070; + uint16_t _5071 = (uint16_t)(147); + _curvea0[315] = _5071; + uint16_t _5072 = (uint16_t)(147); + _curvea0[316] = _5072; + uint16_t _5073 = (uint16_t)(147); + _curvea0[317] = _5073; + uint16_t _5074 = (uint16_t)(148); + _curvea0[318] = _5074; + uint16_t _5075 = (uint16_t)(148); + _curvea0[319] = _5075; + uint16_t _5076 = (uint16_t)(148); + _curvea0[320] = _5076; + uint16_t _5077 = (uint16_t)(148); + _curvea0[321] = _5077; + uint16_t _5078 = (uint16_t)(149); + _curvea0[322] = _5078; + uint16_t _5079 = (uint16_t)(149); + _curvea0[323] = _5079; + uint16_t _5080 = (uint16_t)(149); + _curvea0[324] = _5080; + uint16_t _5081 = (uint16_t)(150); + _curvea0[325] = _5081; + uint16_t _5082 = (uint16_t)(150); + _curvea0[326] = _5082; + uint16_t _5083 = (uint16_t)(150); + _curvea0[327] = _5083; + uint16_t _5084 = (uint16_t)(150); + _curvea0[328] = _5084; + uint16_t _5085 = (uint16_t)(151); + _curvea0[329] = _5085; + uint16_t _5086 = (uint16_t)(151); + _curvea0[330] = _5086; + uint16_t _5087 = (uint16_t)(151); + _curvea0[331] = _5087; + uint16_t _5088 = (uint16_t)(152); + _curvea0[332] = _5088; + uint16_t _5089 = (uint16_t)(152); + _curvea0[333] = _5089; + uint16_t _5090 = (uint16_t)(152); + _curvea0[334] = _5090; + uint16_t _5091 = (uint16_t)(152); + _curvea0[335] = _5091; + uint16_t _5092 = (uint16_t)(153); + _curvea0[336] = _5092; + uint16_t _5093 = (uint16_t)(153); + _curvea0[337] = _5093; + uint16_t _5094 = (uint16_t)(153); + _curvea0[338] = _5094; + uint16_t _5095 = (uint16_t)(154); + _curvea0[339] = _5095; + uint16_t _5096 = (uint16_t)(154); + _curvea0[340] = _5096; + uint16_t _5097 = (uint16_t)(154); + _curvea0[341] = _5097; + uint16_t _5098 = (uint16_t)(154); + _curvea0[342] = _5098; + uint16_t _5099 = (uint16_t)(155); + _curvea0[343] = _5099; + uint16_t _5100 = (uint16_t)(155); + _curvea0[344] = _5100; + uint16_t _5101 = (uint16_t)(155); + _curvea0[345] = _5101; + uint16_t _5102 = (uint16_t)(156); + _curvea0[346] = _5102; + uint16_t _5103 = (uint16_t)(156); + _curvea0[347] = _5103; + uint16_t _5104 = (uint16_t)(156); + _curvea0[348] = _5104; + uint16_t _5105 = (uint16_t)(156); + _curvea0[349] = _5105; + uint16_t _5106 = (uint16_t)(157); + _curvea0[350] = _5106; + uint16_t _5107 = (uint16_t)(157); + _curvea0[351] = _5107; + uint16_t _5108 = (uint16_t)(157); + _curvea0[352] = _5108; + uint16_t _5109 = (uint16_t)(157); + _curvea0[353] = _5109; + uint16_t _5110 = (uint16_t)(158); + _curvea0[354] = _5110; + uint16_t _5111 = (uint16_t)(158); + _curvea0[355] = _5111; + uint16_t _5112 = (uint16_t)(158); + _curvea0[356] = _5112; + uint16_t _5113 = (uint16_t)(159); + _curvea0[357] = _5113; + uint16_t _5114 = (uint16_t)(159); + _curvea0[358] = _5114; + uint16_t _5115 = (uint16_t)(159); + _curvea0[359] = _5115; + uint16_t _5116 = (uint16_t)(159); + _curvea0[360] = _5116; + uint16_t _5117 = (uint16_t)(160); + _curvea0[361] = _5117; + uint16_t _5118 = (uint16_t)(160); + _curvea0[362] = _5118; + uint16_t _5119 = (uint16_t)(160); + _curvea0[363] = _5119; + uint16_t _5120 = (uint16_t)(160); + _curvea0[364] = _5120; + uint16_t _5121 = (uint16_t)(161); + _curvea0[365] = _5121; + uint16_t _5122 = (uint16_t)(161); + _curvea0[366] = _5122; + uint16_t _5123 = (uint16_t)(161); + _curvea0[367] = _5123; + uint16_t _5124 = (uint16_t)(161); + _curvea0[368] = _5124; + uint16_t _5125 = (uint16_t)(162); + _curvea0[369] = _5125; + uint16_t _5126 = (uint16_t)(162); + _curvea0[370] = _5126; + uint16_t _5127 = (uint16_t)(162); + _curvea0[371] = _5127; + uint16_t _5128 = (uint16_t)(162); + _curvea0[372] = _5128; + uint16_t _5129 = (uint16_t)(163); + _curvea0[373] = _5129; + uint16_t _5130 = (uint16_t)(163); + _curvea0[374] = _5130; + uint16_t _5131 = (uint16_t)(163); + _curvea0[375] = _5131; + uint16_t _5132 = (uint16_t)(163); + _curvea0[376] = _5132; + uint16_t _5133 = (uint16_t)(164); + _curvea0[377] = _5133; + uint16_t _5134 = (uint16_t)(164); + _curvea0[378] = _5134; + uint16_t _5135 = (uint16_t)(164); + _curvea0[379] = _5135; + uint16_t _5136 = (uint16_t)(164); + _curvea0[380] = _5136; + uint16_t _5137 = (uint16_t)(165); + _curvea0[381] = _5137; + uint16_t _5138 = (uint16_t)(165); + _curvea0[382] = _5138; + uint16_t _5139 = (uint16_t)(165); + _curvea0[383] = _5139; + uint16_t _5140 = (uint16_t)(166); + _curvea0[384] = _5140; + uint16_t _5141 = (uint16_t)(166); + _curvea0[385] = _5141; + uint16_t _5142 = (uint16_t)(166); + _curvea0[386] = _5142; + uint16_t _5143 = (uint16_t)(166); + _curvea0[387] = _5143; + uint16_t _5144 = (uint16_t)(167); + _curvea0[388] = _5144; + uint16_t _5145 = (uint16_t)(167); + _curvea0[389] = _5145; + uint16_t _5146 = (uint16_t)(167); + _curvea0[390] = _5146; + uint16_t _5147 = (uint16_t)(167); + _curvea0[391] = _5147; + uint16_t _5148 = (uint16_t)(167); + _curvea0[392] = _5148; + uint16_t _5149 = (uint16_t)(168); + _curvea0[393] = _5149; + uint16_t _5150 = (uint16_t)(168); + _curvea0[394] = _5150; + uint16_t _5151 = (uint16_t)(168); + _curvea0[395] = _5151; + uint16_t _5152 = (uint16_t)(168); + _curvea0[396] = _5152; + uint16_t _5153 = (uint16_t)(169); + _curvea0[397] = _5153; + uint16_t _5154 = (uint16_t)(169); + _curvea0[398] = _5154; + uint16_t _5155 = (uint16_t)(169); + _curvea0[399] = _5155; + uint16_t _5156 = (uint16_t)(169); + _curvea0[400] = _5156; + uint16_t _5157 = (uint16_t)(170); + _curvea0[401] = _5157; + uint16_t _5158 = (uint16_t)(170); + _curvea0[402] = _5158; + uint16_t _5159 = (uint16_t)(170); + _curvea0[403] = _5159; + uint16_t _5160 = (uint16_t)(170); + _curvea0[404] = _5160; + uint16_t _5161 = (uint16_t)(171); + _curvea0[405] = _5161; + uint16_t _5162 = (uint16_t)(171); + _curvea0[406] = _5162; + uint16_t _5163 = (uint16_t)(171); + _curvea0[407] = _5163; + uint16_t _5164 = (uint16_t)(171); + _curvea0[408] = _5164; + uint16_t _5165 = (uint16_t)(172); + _curvea0[409] = _5165; + uint16_t _5166 = (uint16_t)(172); + _curvea0[410] = _5166; + uint16_t _5167 = (uint16_t)(172); + _curvea0[411] = _5167; + uint16_t _5168 = (uint16_t)(172); + _curvea0[412] = _5168; + uint16_t _5169 = (uint16_t)(173); + _curvea0[413] = _5169; + uint16_t _5170 = (uint16_t)(173); + _curvea0[414] = _5170; + uint16_t _5171 = (uint16_t)(173); + _curvea0[415] = _5171; + uint16_t _5172 = (uint16_t)(173); + _curvea0[416] = _5172; + uint16_t _5173 = (uint16_t)(173); + _curvea0[417] = _5173; + uint16_t _5174 = (uint16_t)(174); + _curvea0[418] = _5174; + uint16_t _5175 = (uint16_t)(174); + _curvea0[419] = _5175; + uint16_t _5176 = (uint16_t)(174); + _curvea0[420] = _5176; + uint16_t _5177 = (uint16_t)(174); + _curvea0[421] = _5177; + uint16_t _5178 = (uint16_t)(175); + _curvea0[422] = _5178; + uint16_t _5179 = (uint16_t)(175); + _curvea0[423] = _5179; + uint16_t _5180 = (uint16_t)(175); + _curvea0[424] = _5180; + uint16_t _5181 = (uint16_t)(175); + _curvea0[425] = _5181; + uint16_t _5182 = (uint16_t)(176); + _curvea0[426] = _5182; + uint16_t _5183 = (uint16_t)(176); + _curvea0[427] = _5183; + uint16_t _5184 = (uint16_t)(176); + _curvea0[428] = _5184; + uint16_t _5185 = (uint16_t)(176); + _curvea0[429] = _5185; + uint16_t _5186 = (uint16_t)(176); + _curvea0[430] = _5186; + uint16_t _5187 = (uint16_t)(177); + _curvea0[431] = _5187; + uint16_t _5188 = (uint16_t)(177); + _curvea0[432] = _5188; + uint16_t _5189 = (uint16_t)(177); + _curvea0[433] = _5189; + uint16_t _5190 = (uint16_t)(177); + _curvea0[434] = _5190; + uint16_t _5191 = (uint16_t)(178); + _curvea0[435] = _5191; + uint16_t _5192 = (uint16_t)(178); + _curvea0[436] = _5192; + uint16_t _5193 = (uint16_t)(178); + _curvea0[437] = _5193; + uint16_t _5194 = (uint16_t)(178); + _curvea0[438] = _5194; + uint16_t _5195 = (uint16_t)(178); + _curvea0[439] = _5195; + uint16_t _5196 = (uint16_t)(179); + _curvea0[440] = _5196; + uint16_t _5197 = (uint16_t)(179); + _curvea0[441] = _5197; + uint16_t _5198 = (uint16_t)(179); + _curvea0[442] = _5198; + uint16_t _5199 = (uint16_t)(179); + _curvea0[443] = _5199; + uint16_t _5200 = (uint16_t)(180); + _curvea0[444] = _5200; + uint16_t _5201 = (uint16_t)(180); + _curvea0[445] = _5201; + uint16_t _5202 = (uint16_t)(180); + _curvea0[446] = _5202; + uint16_t _5203 = (uint16_t)(180); + _curvea0[447] = _5203; + uint16_t _5204 = (uint16_t)(180); + _curvea0[448] = _5204; + uint16_t _5205 = (uint16_t)(181); + _curvea0[449] = _5205; + uint16_t _5206 = (uint16_t)(181); + _curvea0[450] = _5206; + uint16_t _5207 = (uint16_t)(181); + _curvea0[451] = _5207; + uint16_t _5208 = (uint16_t)(181); + _curvea0[452] = _5208; + uint16_t _5209 = (uint16_t)(181); + _curvea0[453] = _5209; + uint16_t _5210 = (uint16_t)(182); + _curvea0[454] = _5210; + uint16_t _5211 = (uint16_t)(182); + _curvea0[455] = _5211; + uint16_t _5212 = (uint16_t)(182); + _curvea0[456] = _5212; + uint16_t _5213 = (uint16_t)(182); + _curvea0[457] = _5213; + uint16_t _5214 = (uint16_t)(183); + _curvea0[458] = _5214; + uint16_t _5215 = (uint16_t)(183); + _curvea0[459] = _5215; + uint16_t _5216 = (uint16_t)(183); + _curvea0[460] = _5216; + uint16_t _5217 = (uint16_t)(183); + _curvea0[461] = _5217; + uint16_t _5218 = (uint16_t)(183); + _curvea0[462] = _5218; + uint16_t _5219 = (uint16_t)(184); + _curvea0[463] = _5219; + uint16_t _5220 = (uint16_t)(184); + _curvea0[464] = _5220; + uint16_t _5221 = (uint16_t)(184); + _curvea0[465] = _5221; + uint16_t _5222 = (uint16_t)(184); + _curvea0[466] = _5222; + uint16_t _5223 = (uint16_t)(184); + _curvea0[467] = _5223; + uint16_t _5224 = (uint16_t)(185); + _curvea0[468] = _5224; + uint16_t _5225 = (uint16_t)(185); + _curvea0[469] = _5225; + uint16_t _5226 = (uint16_t)(185); + _curvea0[470] = _5226; + uint16_t _5227 = (uint16_t)(185); + _curvea0[471] = _5227; + uint16_t _5228 = (uint16_t)(185); + _curvea0[472] = _5228; + uint16_t _5229 = (uint16_t)(186); + _curvea0[473] = _5229; + uint16_t _5230 = (uint16_t)(186); + _curvea0[474] = _5230; + uint16_t _5231 = (uint16_t)(186); + _curvea0[475] = _5231; + uint16_t _5232 = (uint16_t)(186); + _curvea0[476] = _5232; + uint16_t _5233 = (uint16_t)(187); + _curvea0[477] = _5233; + uint16_t _5234 = (uint16_t)(187); + _curvea0[478] = _5234; + uint16_t _5235 = (uint16_t)(187); + _curvea0[479] = _5235; + uint16_t _5236 = (uint16_t)(187); + _curvea0[480] = _5236; + uint16_t _5237 = (uint16_t)(187); + _curvea0[481] = _5237; + uint16_t _5238 = (uint16_t)(188); + _curvea0[482] = _5238; + uint16_t _5239 = (uint16_t)(188); + _curvea0[483] = _5239; + uint16_t _5240 = (uint16_t)(188); + _curvea0[484] = _5240; + uint16_t _5241 = (uint16_t)(188); + _curvea0[485] = _5241; + uint16_t _5242 = (uint16_t)(188); + _curvea0[486] = _5242; + uint16_t _5243 = (uint16_t)(189); + _curvea0[487] = _5243; + uint16_t _5244 = (uint16_t)(189); + _curvea0[488] = _5244; + uint16_t _5245 = (uint16_t)(189); + _curvea0[489] = _5245; + uint16_t _5246 = (uint16_t)(189); + _curvea0[490] = _5246; + uint16_t _5247 = (uint16_t)(189); + _curvea0[491] = _5247; + uint16_t _5248 = (uint16_t)(190); + _curvea0[492] = _5248; + uint16_t _5249 = (uint16_t)(190); + _curvea0[493] = _5249; + uint16_t _5250 = (uint16_t)(190); + _curvea0[494] = _5250; + uint16_t _5251 = (uint16_t)(190); + _curvea0[495] = _5251; + uint16_t _5252 = (uint16_t)(190); + _curvea0[496] = _5252; + uint16_t _5253 = (uint16_t)(190); + _curvea0[497] = _5253; + uint16_t _5254 = (uint16_t)(191); + _curvea0[498] = _5254; + uint16_t _5255 = (uint16_t)(191); + _curvea0[499] = _5255; + uint16_t _5256 = (uint16_t)(191); + _curvea0[500] = _5256; + uint16_t _5257 = (uint16_t)(191); + _curvea0[501] = _5257; + uint16_t _5258 = (uint16_t)(191); + _curvea0[502] = _5258; + uint16_t _5259 = (uint16_t)(192); + _curvea0[503] = _5259; + uint16_t _5260 = (uint16_t)(192); + _curvea0[504] = _5260; + uint16_t _5261 = (uint16_t)(192); + _curvea0[505] = _5261; + uint16_t _5262 = (uint16_t)(192); + _curvea0[506] = _5262; + uint16_t _5263 = (uint16_t)(192); + _curvea0[507] = _5263; + uint16_t _5264 = (uint16_t)(193); + _curvea0[508] = _5264; + uint16_t _5265 = (uint16_t)(193); + _curvea0[509] = _5265; + uint16_t _5266 = (uint16_t)(193); + _curvea0[510] = _5266; + uint16_t _5267 = (uint16_t)(193); + _curvea0[511] = _5267; + uint16_t _5268 = (uint16_t)(193); + _curvea0[512] = _5268; + uint16_t _5269 = (uint16_t)(194); + _curvea0[513] = _5269; + uint16_t _5270 = (uint16_t)(194); + _curvea0[514] = _5270; + uint16_t _5271 = (uint16_t)(194); + _curvea0[515] = _5271; + uint16_t _5272 = (uint16_t)(194); + _curvea0[516] = _5272; + uint16_t _5273 = (uint16_t)(194); + _curvea0[517] = _5273; + uint16_t _5274 = (uint16_t)(195); + _curvea0[518] = _5274; + uint16_t _5275 = (uint16_t)(195); + _curvea0[519] = _5275; + uint16_t _5276 = (uint16_t)(195); + _curvea0[520] = _5276; + uint16_t _5277 = (uint16_t)(195); + _curvea0[521] = _5277; + uint16_t _5278 = (uint16_t)(195); + _curvea0[522] = _5278; + uint16_t _5279 = (uint16_t)(195); + _curvea0[523] = _5279; + uint16_t _5280 = (uint16_t)(196); + _curvea0[524] = _5280; + uint16_t _5281 = (uint16_t)(196); + _curvea0[525] = _5281; + uint16_t _5282 = (uint16_t)(196); + _curvea0[526] = _5282; + uint16_t _5283 = (uint16_t)(196); + _curvea0[527] = _5283; + uint16_t _5284 = (uint16_t)(196); + _curvea0[528] = _5284; + uint16_t _5285 = (uint16_t)(197); + _curvea0[529] = _5285; + uint16_t _5286 = (uint16_t)(197); + _curvea0[530] = _5286; + uint16_t _5287 = (uint16_t)(197); + _curvea0[531] = _5287; + uint16_t _5288 = (uint16_t)(197); + _curvea0[532] = _5288; + uint16_t _5289 = (uint16_t)(197); + _curvea0[533] = _5289; + uint16_t _5290 = (uint16_t)(197); + _curvea0[534] = _5290; + uint16_t _5291 = (uint16_t)(198); + _curvea0[535] = _5291; + uint16_t _5292 = (uint16_t)(198); + _curvea0[536] = _5292; + uint16_t _5293 = (uint16_t)(198); + _curvea0[537] = _5293; + uint16_t _5294 = (uint16_t)(198); + _curvea0[538] = _5294; + uint16_t _5295 = (uint16_t)(198); + _curvea0[539] = _5295; + uint16_t _5296 = (uint16_t)(199); + _curvea0[540] = _5296; + uint16_t _5297 = (uint16_t)(199); + _curvea0[541] = _5297; + uint16_t _5298 = (uint16_t)(199); + _curvea0[542] = _5298; + uint16_t _5299 = (uint16_t)(199); + _curvea0[543] = _5299; + uint16_t _5300 = (uint16_t)(199); + _curvea0[544] = _5300; + uint16_t _5301 = (uint16_t)(199); + _curvea0[545] = _5301; + uint16_t _5302 = (uint16_t)(200); + _curvea0[546] = _5302; + uint16_t _5303 = (uint16_t)(200); + _curvea0[547] = _5303; + uint16_t _5304 = (uint16_t)(200); + _curvea0[548] = _5304; + uint16_t _5305 = (uint16_t)(200); + _curvea0[549] = _5305; + uint16_t _5306 = (uint16_t)(200); + _curvea0[550] = _5306; + uint16_t _5307 = (uint16_t)(200); + _curvea0[551] = _5307; + uint16_t _5308 = (uint16_t)(201); + _curvea0[552] = _5308; + uint16_t _5309 = (uint16_t)(201); + _curvea0[553] = _5309; + uint16_t _5310 = (uint16_t)(201); + _curvea0[554] = _5310; + uint16_t _5311 = (uint16_t)(201); + _curvea0[555] = _5311; + uint16_t _5312 = (uint16_t)(201); + _curvea0[556] = _5312; + uint16_t _5313 = (uint16_t)(202); + _curvea0[557] = _5313; + uint16_t _5314 = (uint16_t)(202); + _curvea0[558] = _5314; + uint16_t _5315 = (uint16_t)(202); + _curvea0[559] = _5315; + uint16_t _5316 = (uint16_t)(202); + _curvea0[560] = _5316; + uint16_t _5317 = (uint16_t)(202); + _curvea0[561] = _5317; + uint16_t _5318 = (uint16_t)(202); + _curvea0[562] = _5318; + uint16_t _5319 = (uint16_t)(203); + _curvea0[563] = _5319; + uint16_t _5320 = (uint16_t)(203); + _curvea0[564] = _5320; + uint16_t _5321 = (uint16_t)(203); + _curvea0[565] = _5321; + uint16_t _5322 = (uint16_t)(203); + _curvea0[566] = _5322; + uint16_t _5323 = (uint16_t)(203); + _curvea0[567] = _5323; + uint16_t _5324 = (uint16_t)(203); + _curvea0[568] = _5324; + uint16_t _5325 = (uint16_t)(204); + _curvea0[569] = _5325; + uint16_t _5326 = (uint16_t)(204); + _curvea0[570] = _5326; + uint16_t _5327 = (uint16_t)(204); + _curvea0[571] = _5327; + uint16_t _5328 = (uint16_t)(204); + _curvea0[572] = _5328; + uint16_t _5329 = (uint16_t)(204); + _curvea0[573] = _5329; + uint16_t _5330 = (uint16_t)(204); + _curvea0[574] = _5330; + uint16_t _5331 = (uint16_t)(205); + _curvea0[575] = _5331; + uint16_t _5332 = (uint16_t)(205); + _curvea0[576] = _5332; + uint16_t _5333 = (uint16_t)(205); + _curvea0[577] = _5333; + uint16_t _5334 = (uint16_t)(205); + _curvea0[578] = _5334; + uint16_t _5335 = (uint16_t)(205); + _curvea0[579] = _5335; + uint16_t _5336 = (uint16_t)(205); + _curvea0[580] = _5336; + uint16_t _5337 = (uint16_t)(206); + _curvea0[581] = _5337; + uint16_t _5338 = (uint16_t)(206); + _curvea0[582] = _5338; + uint16_t _5339 = (uint16_t)(206); + _curvea0[583] = _5339; + uint16_t _5340 = (uint16_t)(206); + _curvea0[584] = _5340; + uint16_t _5341 = (uint16_t)(206); + _curvea0[585] = _5341; + uint16_t _5342 = (uint16_t)(206); + _curvea0[586] = _5342; + uint16_t _5343 = (uint16_t)(207); + _curvea0[587] = _5343; + uint16_t _5344 = (uint16_t)(207); + _curvea0[588] = _5344; + uint16_t _5345 = (uint16_t)(207); + _curvea0[589] = _5345; + uint16_t _5346 = (uint16_t)(207); + _curvea0[590] = _5346; + uint16_t _5347 = (uint16_t)(207); + _curvea0[591] = _5347; + uint16_t _5348 = (uint16_t)(207); + _curvea0[592] = _5348; + uint16_t _5349 = (uint16_t)(208); + _curvea0[593] = _5349; + uint16_t _5350 = (uint16_t)(208); + _curvea0[594] = _5350; + uint16_t _5351 = (uint16_t)(208); + _curvea0[595] = _5351; + uint16_t _5352 = (uint16_t)(208); + _curvea0[596] = _5352; + uint16_t _5353 = (uint16_t)(208); + _curvea0[597] = _5353; + uint16_t _5354 = (uint16_t)(208); + _curvea0[598] = _5354; + uint16_t _5355 = (uint16_t)(209); + _curvea0[599] = _5355; + uint16_t _5356 = (uint16_t)(209); + _curvea0[600] = _5356; + uint16_t _5357 = (uint16_t)(209); + _curvea0[601] = _5357; + uint16_t _5358 = (uint16_t)(209); + _curvea0[602] = _5358; + uint16_t _5359 = (uint16_t)(209); + _curvea0[603] = _5359; + uint16_t _5360 = (uint16_t)(209); + _curvea0[604] = _5360; + uint16_t _5361 = (uint16_t)(209); + _curvea0[605] = _5361; + uint16_t _5362 = (uint16_t)(210); + _curvea0[606] = _5362; + uint16_t _5363 = (uint16_t)(210); + _curvea0[607] = _5363; + uint16_t _5364 = (uint16_t)(210); + _curvea0[608] = _5364; + uint16_t _5365 = (uint16_t)(210); + _curvea0[609] = _5365; + uint16_t _5366 = (uint16_t)(210); + _curvea0[610] = _5366; + uint16_t _5367 = (uint16_t)(210); + _curvea0[611] = _5367; + uint16_t _5368 = (uint16_t)(211); + _curvea0[612] = _5368; + uint16_t _5369 = (uint16_t)(211); + _curvea0[613] = _5369; + uint16_t _5370 = (uint16_t)(211); + _curvea0[614] = _5370; + uint16_t _5371 = (uint16_t)(211); + _curvea0[615] = _5371; + uint16_t _5372 = (uint16_t)(211); + _curvea0[616] = _5372; + uint16_t _5373 = (uint16_t)(211); + _curvea0[617] = _5373; + uint16_t _5374 = (uint16_t)(211); + _curvea0[618] = _5374; + uint16_t _5375 = (uint16_t)(212); + _curvea0[619] = _5375; + uint16_t _5376 = (uint16_t)(212); + _curvea0[620] = _5376; + uint16_t _5377 = (uint16_t)(212); + _curvea0[621] = _5377; + uint16_t _5378 = (uint16_t)(212); + _curvea0[622] = _5378; + uint16_t _5379 = (uint16_t)(212); + _curvea0[623] = _5379; + uint16_t _5380 = (uint16_t)(212); + _curvea0[624] = _5380; + uint16_t _5381 = (uint16_t)(213); + _curvea0[625] = _5381; + uint16_t _5382 = (uint16_t)(213); + _curvea0[626] = _5382; + uint16_t _5383 = (uint16_t)(213); + _curvea0[627] = _5383; + uint16_t _5384 = (uint16_t)(213); + _curvea0[628] = _5384; + uint16_t _5385 = (uint16_t)(213); + _curvea0[629] = _5385; + uint16_t _5386 = (uint16_t)(213); + _curvea0[630] = _5386; + uint16_t _5387 = (uint16_t)(213); + _curvea0[631] = _5387; + uint16_t _5388 = (uint16_t)(214); + _curvea0[632] = _5388; + uint16_t _5389 = (uint16_t)(214); + _curvea0[633] = _5389; + uint16_t _5390 = (uint16_t)(214); + _curvea0[634] = _5390; + uint16_t _5391 = (uint16_t)(214); + _curvea0[635] = _5391; + uint16_t _5392 = (uint16_t)(214); + _curvea0[636] = _5392; + uint16_t _5393 = (uint16_t)(214); + _curvea0[637] = _5393; + uint16_t _5394 = (uint16_t)(214); + _curvea0[638] = _5394; + uint16_t _5395 = (uint16_t)(215); + _curvea0[639] = _5395; + uint16_t _5396 = (uint16_t)(215); + _curvea0[640] = _5396; + uint16_t _5397 = (uint16_t)(215); + _curvea0[641] = _5397; + uint16_t _5398 = (uint16_t)(215); + _curvea0[642] = _5398; + uint16_t _5399 = (uint16_t)(215); + _curvea0[643] = _5399; + uint16_t _5400 = (uint16_t)(215); + _curvea0[644] = _5400; + uint16_t _5401 = (uint16_t)(216); + _curvea0[645] = _5401; + uint16_t _5402 = (uint16_t)(216); + _curvea0[646] = _5402; + uint16_t _5403 = (uint16_t)(216); + _curvea0[647] = _5403; + uint16_t _5404 = (uint16_t)(216); + _curvea0[648] = _5404; + uint16_t _5405 = (uint16_t)(216); + _curvea0[649] = _5405; + uint16_t _5406 = (uint16_t)(216); + _curvea0[650] = _5406; + uint16_t _5407 = (uint16_t)(216); + _curvea0[651] = _5407; + uint16_t _5408 = (uint16_t)(217); + _curvea0[652] = _5408; + uint16_t _5409 = (uint16_t)(217); + _curvea0[653] = _5409; + uint16_t _5410 = (uint16_t)(217); + _curvea0[654] = _5410; + uint16_t _5411 = (uint16_t)(217); + _curvea0[655] = _5411; + uint16_t _5412 = (uint16_t)(217); + _curvea0[656] = _5412; + uint16_t _5413 = (uint16_t)(217); + _curvea0[657] = _5413; + uint16_t _5414 = (uint16_t)(217); + _curvea0[658] = _5414; + uint16_t _5415 = (uint16_t)(218); + _curvea0[659] = _5415; + uint16_t _5416 = (uint16_t)(218); + _curvea0[660] = _5416; + uint16_t _5417 = (uint16_t)(218); + _curvea0[661] = _5417; + uint16_t _5418 = (uint16_t)(218); + _curvea0[662] = _5418; + uint16_t _5419 = (uint16_t)(218); + _curvea0[663] = _5419; + uint16_t _5420 = (uint16_t)(218); + _curvea0[664] = _5420; + uint16_t _5421 = (uint16_t)(218); + _curvea0[665] = _5421; + uint16_t _5422 = (uint16_t)(219); + _curvea0[666] = _5422; + uint16_t _5423 = (uint16_t)(219); + _curvea0[667] = _5423; + uint16_t _5424 = (uint16_t)(219); + _curvea0[668] = _5424; + uint16_t _5425 = (uint16_t)(219); + _curvea0[669] = _5425; + uint16_t _5426 = (uint16_t)(219); + _curvea0[670] = _5426; + uint16_t _5427 = (uint16_t)(219); + _curvea0[671] = _5427; + uint16_t _5428 = (uint16_t)(219); + _curvea0[672] = _5428; + uint16_t _5429 = (uint16_t)(220); + _curvea0[673] = _5429; + uint16_t _5430 = (uint16_t)(220); + _curvea0[674] = _5430; + uint16_t _5431 = (uint16_t)(220); + _curvea0[675] = _5431; + uint16_t _5432 = (uint16_t)(220); + _curvea0[676] = _5432; + uint16_t _5433 = (uint16_t)(220); + _curvea0[677] = _5433; + uint16_t _5434 = (uint16_t)(220); + _curvea0[678] = _5434; + uint16_t _5435 = (uint16_t)(220); + _curvea0[679] = _5435; + uint16_t _5436 = (uint16_t)(220); + _curvea0[680] = _5436; + uint16_t _5437 = (uint16_t)(221); + _curvea0[681] = _5437; + uint16_t _5438 = (uint16_t)(221); + _curvea0[682] = _5438; + uint16_t _5439 = (uint16_t)(221); + _curvea0[683] = _5439; + uint16_t _5440 = (uint16_t)(221); + _curvea0[684] = _5440; + uint16_t _5441 = (uint16_t)(221); + _curvea0[685] = _5441; + uint16_t _5442 = (uint16_t)(221); + _curvea0[686] = _5442; + uint16_t _5443 = (uint16_t)(221); + _curvea0[687] = _5443; + uint16_t _5444 = (uint16_t)(222); + _curvea0[688] = _5444; + uint16_t _5445 = (uint16_t)(222); + _curvea0[689] = _5445; + uint16_t _5446 = (uint16_t)(222); + _curvea0[690] = _5446; + uint16_t _5447 = (uint16_t)(222); + _curvea0[691] = _5447; + uint16_t _5448 = (uint16_t)(222); + _curvea0[692] = _5448; + uint16_t _5449 = (uint16_t)(222); + _curvea0[693] = _5449; + uint16_t _5450 = (uint16_t)(222); + _curvea0[694] = _5450; + uint16_t _5451 = (uint16_t)(223); + _curvea0[695] = _5451; + uint16_t _5452 = (uint16_t)(223); + _curvea0[696] = _5452; + uint16_t _5453 = (uint16_t)(223); + _curvea0[697] = _5453; + uint16_t _5454 = (uint16_t)(223); + _curvea0[698] = _5454; + uint16_t _5455 = (uint16_t)(223); + _curvea0[699] = _5455; + uint16_t _5456 = (uint16_t)(223); + _curvea0[700] = _5456; + uint16_t _5457 = (uint16_t)(223); + _curvea0[701] = _5457; + uint16_t _5458 = (uint16_t)(223); + _curvea0[702] = _5458; + uint16_t _5459 = (uint16_t)(224); + _curvea0[703] = _5459; + uint16_t _5460 = (uint16_t)(224); + _curvea0[704] = _5460; + uint16_t _5461 = (uint16_t)(224); + _curvea0[705] = _5461; + uint16_t _5462 = (uint16_t)(224); + _curvea0[706] = _5462; + uint16_t _5463 = (uint16_t)(224); + _curvea0[707] = _5463; + uint16_t _5464 = (uint16_t)(224); + _curvea0[708] = _5464; + uint16_t _5465 = (uint16_t)(224); + _curvea0[709] = _5465; + uint16_t _5466 = (uint16_t)(224); + _curvea0[710] = _5466; + uint16_t _5467 = (uint16_t)(225); + _curvea0[711] = _5467; + uint16_t _5468 = (uint16_t)(225); + _curvea0[712] = _5468; + uint16_t _5469 = (uint16_t)(225); + _curvea0[713] = _5469; + uint16_t _5470 = (uint16_t)(225); + _curvea0[714] = _5470; + uint16_t _5471 = (uint16_t)(225); + _curvea0[715] = _5471; + uint16_t _5472 = (uint16_t)(225); + _curvea0[716] = _5472; + uint16_t _5473 = (uint16_t)(225); + _curvea0[717] = _5473; + uint16_t _5474 = (uint16_t)(226); + _curvea0[718] = _5474; + uint16_t _5475 = (uint16_t)(226); + _curvea0[719] = _5475; + uint16_t _5476 = (uint16_t)(226); + _curvea0[720] = _5476; + uint16_t _5477 = (uint16_t)(226); + _curvea0[721] = _5477; + uint16_t _5478 = (uint16_t)(226); + _curvea0[722] = _5478; + uint16_t _5479 = (uint16_t)(226); + _curvea0[723] = _5479; + uint16_t _5480 = (uint16_t)(226); + _curvea0[724] = _5480; + uint16_t _5481 = (uint16_t)(226); + _curvea0[725] = _5481; + uint16_t _5482 = (uint16_t)(227); + _curvea0[726] = _5482; + uint16_t _5483 = (uint16_t)(227); + _curvea0[727] = _5483; + uint16_t _5484 = (uint16_t)(227); + _curvea0[728] = _5484; + uint16_t _5485 = (uint16_t)(227); + _curvea0[729] = _5485; + uint16_t _5486 = (uint16_t)(227); + _curvea0[730] = _5486; + uint16_t _5487 = (uint16_t)(227); + _curvea0[731] = _5487; + uint16_t _5488 = (uint16_t)(227); + _curvea0[732] = _5488; + uint16_t _5489 = (uint16_t)(227); + _curvea0[733] = _5489; + uint16_t _5490 = (uint16_t)(228); + _curvea0[734] = _5490; + uint16_t _5491 = (uint16_t)(228); + _curvea0[735] = _5491; + uint16_t _5492 = (uint16_t)(228); + _curvea0[736] = _5492; + uint16_t _5493 = (uint16_t)(228); + _curvea0[737] = _5493; + uint16_t _5494 = (uint16_t)(228); + _curvea0[738] = _5494; + uint16_t _5495 = (uint16_t)(228); + _curvea0[739] = _5495; + uint16_t _5496 = (uint16_t)(228); + _curvea0[740] = _5496; + uint16_t _5497 = (uint16_t)(228); + _curvea0[741] = _5497; + uint16_t _5498 = (uint16_t)(228); + _curvea0[742] = _5498; + uint16_t _5499 = (uint16_t)(229); + _curvea0[743] = _5499; + uint16_t _5500 = (uint16_t)(229); + _curvea0[744] = _5500; + uint16_t _5501 = (uint16_t)(229); + _curvea0[745] = _5501; + uint16_t _5502 = (uint16_t)(229); + _curvea0[746] = _5502; + uint16_t _5503 = (uint16_t)(229); + _curvea0[747] = _5503; + uint16_t _5504 = (uint16_t)(229); + _curvea0[748] = _5504; + uint16_t _5505 = (uint16_t)(229); + _curvea0[749] = _5505; + uint16_t _5506 = (uint16_t)(229); + _curvea0[750] = _5506; + uint16_t _5507 = (uint16_t)(230); + _curvea0[751] = _5507; + uint16_t _5508 = (uint16_t)(230); + _curvea0[752] = _5508; + uint16_t _5509 = (uint16_t)(230); + _curvea0[753] = _5509; + uint16_t _5510 = (uint16_t)(230); + _curvea0[754] = _5510; + uint16_t _5511 = (uint16_t)(230); + _curvea0[755] = _5511; + uint16_t _5512 = (uint16_t)(230); + _curvea0[756] = _5512; + uint16_t _5513 = (uint16_t)(230); + _curvea0[757] = _5513; + uint16_t _5514 = (uint16_t)(230); + _curvea0[758] = _5514; + uint16_t _5515 = (uint16_t)(231); + _curvea0[759] = _5515; + uint16_t _5516 = (uint16_t)(231); + _curvea0[760] = _5516; + uint16_t _5517 = (uint16_t)(231); + _curvea0[761] = _5517; + uint16_t _5518 = (uint16_t)(231); + _curvea0[762] = _5518; + uint16_t _5519 = (uint16_t)(231); + _curvea0[763] = _5519; + uint16_t _5520 = (uint16_t)(231); + _curvea0[764] = _5520; + uint16_t _5521 = (uint16_t)(231); + _curvea0[765] = _5521; + uint16_t _5522 = (uint16_t)(231); + _curvea0[766] = _5522; + uint16_t _5523 = (uint16_t)(231); + _curvea0[767] = _5523; + uint16_t _5524 = (uint16_t)(232); + _curvea0[768] = _5524; + uint16_t _5525 = (uint16_t)(232); + _curvea0[769] = _5525; + uint16_t _5526 = (uint16_t)(232); + _curvea0[770] = _5526; + uint16_t _5527 = (uint16_t)(232); + _curvea0[771] = _5527; + uint16_t _5528 = (uint16_t)(232); + _curvea0[772] = _5528; + uint16_t _5529 = (uint16_t)(232); + _curvea0[773] = _5529; + uint16_t _5530 = (uint16_t)(232); + _curvea0[774] = _5530; + uint16_t _5531 = (uint16_t)(232); + _curvea0[775] = _5531; + uint16_t _5532 = (uint16_t)(233); + _curvea0[776] = _5532; + uint16_t _5533 = (uint16_t)(233); + _curvea0[777] = _5533; + uint16_t _5534 = (uint16_t)(233); + _curvea0[778] = _5534; + uint16_t _5535 = (uint16_t)(233); + _curvea0[779] = _5535; + uint16_t _5536 = (uint16_t)(233); + _curvea0[780] = _5536; + uint16_t _5537 = (uint16_t)(233); + _curvea0[781] = _5537; + uint16_t _5538 = (uint16_t)(233); + _curvea0[782] = _5538; + uint16_t _5539 = (uint16_t)(233); + _curvea0[783] = _5539; + uint16_t _5540 = (uint16_t)(233); + _curvea0[784] = _5540; + uint16_t _5541 = (uint16_t)(234); + _curvea0[785] = _5541; + uint16_t _5542 = (uint16_t)(234); + _curvea0[786] = _5542; + uint16_t _5543 = (uint16_t)(234); + _curvea0[787] = _5543; + uint16_t _5544 = (uint16_t)(234); + _curvea0[788] = _5544; + uint16_t _5545 = (uint16_t)(234); + _curvea0[789] = _5545; + uint16_t _5546 = (uint16_t)(234); + _curvea0[790] = _5546; + uint16_t _5547 = (uint16_t)(234); + _curvea0[791] = _5547; + uint16_t _5548 = (uint16_t)(234); + _curvea0[792] = _5548; + uint16_t _5549 = (uint16_t)(234); + _curvea0[793] = _5549; + uint16_t _5550 = (uint16_t)(235); + _curvea0[794] = _5550; + uint16_t _5551 = (uint16_t)(235); + _curvea0[795] = _5551; + uint16_t _5552 = (uint16_t)(235); + _curvea0[796] = _5552; + uint16_t _5553 = (uint16_t)(235); + _curvea0[797] = _5553; + uint16_t _5554 = (uint16_t)(235); + _curvea0[798] = _5554; + uint16_t _5555 = (uint16_t)(235); + _curvea0[799] = _5555; + uint16_t _5556 = (uint16_t)(235); + _curvea0[800] = _5556; + uint16_t _5557 = (uint16_t)(235); + _curvea0[801] = _5557; + uint16_t _5558 = (uint16_t)(235); + _curvea0[802] = _5558; + uint16_t _5559 = (uint16_t)(236); + _curvea0[803] = _5559; + uint16_t _5560 = (uint16_t)(236); + _curvea0[804] = _5560; + uint16_t _5561 = (uint16_t)(236); + _curvea0[805] = _5561; + uint16_t _5562 = (uint16_t)(236); + _curvea0[806] = _5562; + uint16_t _5563 = (uint16_t)(236); + _curvea0[807] = _5563; + uint16_t _5564 = (uint16_t)(236); + _curvea0[808] = _5564; + uint16_t _5565 = (uint16_t)(236); + _curvea0[809] = _5565; + uint16_t _5566 = (uint16_t)(236); + _curvea0[810] = _5566; + uint16_t _5567 = (uint16_t)(236); + _curvea0[811] = _5567; + uint16_t _5568 = (uint16_t)(237); + _curvea0[812] = _5568; + uint16_t _5569 = (uint16_t)(237); + _curvea0[813] = _5569; + uint16_t _5570 = (uint16_t)(237); + _curvea0[814] = _5570; + uint16_t _5571 = (uint16_t)(237); + _curvea0[815] = _5571; + uint16_t _5572 = (uint16_t)(237); + _curvea0[816] = _5572; + uint16_t _5573 = (uint16_t)(237); + _curvea0[817] = _5573; + uint16_t _5574 = (uint16_t)(237); + _curvea0[818] = _5574; + uint16_t _5575 = (uint16_t)(237); + _curvea0[819] = _5575; + uint16_t _5576 = (uint16_t)(237); + _curvea0[820] = _5576; + uint16_t _5577 = (uint16_t)(237); + _curvea0[821] = _5577; + uint16_t _5578 = (uint16_t)(238); + _curvea0[822] = _5578; + uint16_t _5579 = (uint16_t)(238); + _curvea0[823] = _5579; + uint16_t _5580 = (uint16_t)(238); + _curvea0[824] = _5580; + uint16_t _5581 = (uint16_t)(238); + _curvea0[825] = _5581; + uint16_t _5582 = (uint16_t)(238); + _curvea0[826] = _5582; + uint16_t _5583 = (uint16_t)(238); + _curvea0[827] = _5583; + uint16_t _5584 = (uint16_t)(238); + _curvea0[828] = _5584; + uint16_t _5585 = (uint16_t)(238); + _curvea0[829] = _5585; + uint16_t _5586 = (uint16_t)(238); + _curvea0[830] = _5586; + uint16_t _5587 = (uint16_t)(239); + _curvea0[831] = _5587; + uint16_t _5588 = (uint16_t)(239); + _curvea0[832] = _5588; + uint16_t _5589 = (uint16_t)(239); + _curvea0[833] = _5589; + uint16_t _5590 = (uint16_t)(239); + _curvea0[834] = _5590; + uint16_t _5591 = (uint16_t)(239); + _curvea0[835] = _5591; + uint16_t _5592 = (uint16_t)(239); + _curvea0[836] = _5592; + uint16_t _5593 = (uint16_t)(239); + _curvea0[837] = _5593; + uint16_t _5594 = (uint16_t)(239); + _curvea0[838] = _5594; + uint16_t _5595 = (uint16_t)(239); + _curvea0[839] = _5595; + uint16_t _5596 = (uint16_t)(239); + _curvea0[840] = _5596; + uint16_t _5597 = (uint16_t)(240); + _curvea0[841] = _5597; + uint16_t _5598 = (uint16_t)(240); + _curvea0[842] = _5598; + uint16_t _5599 = (uint16_t)(240); + _curvea0[843] = _5599; + uint16_t _5600 = (uint16_t)(240); + _curvea0[844] = _5600; + uint16_t _5601 = (uint16_t)(240); + _curvea0[845] = _5601; + uint16_t _5602 = (uint16_t)(240); + _curvea0[846] = _5602; + uint16_t _5603 = (uint16_t)(240); + _curvea0[847] = _5603; + uint16_t _5604 = (uint16_t)(240); + _curvea0[848] = _5604; + uint16_t _5605 = (uint16_t)(240); + _curvea0[849] = _5605; + uint16_t _5606 = (uint16_t)(240); + _curvea0[850] = _5606; + uint16_t _5607 = (uint16_t)(241); + _curvea0[851] = _5607; + uint16_t _5608 = (uint16_t)(241); + _curvea0[852] = _5608; + uint16_t _5609 = (uint16_t)(241); + _curvea0[853] = _5609; + uint16_t _5610 = (uint16_t)(241); + _curvea0[854] = _5610; + uint16_t _5611 = (uint16_t)(241); + _curvea0[855] = _5611; + uint16_t _5612 = (uint16_t)(241); + _curvea0[856] = _5612; + uint16_t _5613 = (uint16_t)(241); + _curvea0[857] = _5613; + uint16_t _5614 = (uint16_t)(241); + _curvea0[858] = _5614; + uint16_t _5615 = (uint16_t)(241); + _curvea0[859] = _5615; + uint16_t _5616 = (uint16_t)(241); + _curvea0[860] = _5616; + uint16_t _5617 = (uint16_t)(242); + _curvea0[861] = _5617; + uint16_t _5618 = (uint16_t)(242); + _curvea0[862] = _5618; + uint16_t _5619 = (uint16_t)(242); + _curvea0[863] = _5619; + uint16_t _5620 = (uint16_t)(242); + _curvea0[864] = _5620; + uint16_t _5621 = (uint16_t)(242); + _curvea0[865] = _5621; + uint16_t _5622 = (uint16_t)(242); + _curvea0[866] = _5622; + uint16_t _5623 = (uint16_t)(242); + _curvea0[867] = _5623; + uint16_t _5624 = (uint16_t)(242); + _curvea0[868] = _5624; + uint16_t _5625 = (uint16_t)(242); + _curvea0[869] = _5625; + uint16_t _5626 = (uint16_t)(242); + _curvea0[870] = _5626; + uint16_t _5627 = (uint16_t)(243); + _curvea0[871] = _5627; + uint16_t _5628 = (uint16_t)(243); + _curvea0[872] = _5628; + uint16_t _5629 = (uint16_t)(243); + _curvea0[873] = _5629; + uint16_t _5630 = (uint16_t)(243); + _curvea0[874] = _5630; + uint16_t _5631 = (uint16_t)(243); + _curvea0[875] = _5631; + uint16_t _5632 = (uint16_t)(243); + _curvea0[876] = _5632; + uint16_t _5633 = (uint16_t)(243); + _curvea0[877] = _5633; + uint16_t _5634 = (uint16_t)(243); + _curvea0[878] = _5634; + uint16_t _5635 = (uint16_t)(243); + _curvea0[879] = _5635; + uint16_t _5636 = (uint16_t)(243); + _curvea0[880] = _5636; + uint16_t _5637 = (uint16_t)(244); + _curvea0[881] = _5637; + uint16_t _5638 = (uint16_t)(244); + _curvea0[882] = _5638; + uint16_t _5639 = (uint16_t)(244); + _curvea0[883] = _5639; + uint16_t _5640 = (uint16_t)(244); + _curvea0[884] = _5640; + uint16_t _5641 = (uint16_t)(244); + _curvea0[885] = _5641; + uint16_t _5642 = (uint16_t)(244); + _curvea0[886] = _5642; + uint16_t _5643 = (uint16_t)(244); + _curvea0[887] = _5643; + uint16_t _5644 = (uint16_t)(244); + _curvea0[888] = _5644; + uint16_t _5645 = (uint16_t)(244); + _curvea0[889] = _5645; + uint16_t _5646 = (uint16_t)(244); + _curvea0[890] = _5646; + uint16_t _5647 = (uint16_t)(244); + _curvea0[891] = _5647; + uint16_t _5648 = (uint16_t)(245); + _curvea0[892] = _5648; + uint16_t _5649 = (uint16_t)(245); + _curvea0[893] = _5649; + uint16_t _5650 = (uint16_t)(245); + _curvea0[894] = _5650; + uint16_t _5651 = (uint16_t)(245); + _curvea0[895] = _5651; + uint16_t _5652 = (uint16_t)(245); + _curvea0[896] = _5652; + uint16_t _5653 = (uint16_t)(245); + _curvea0[897] = _5653; + uint16_t _5654 = (uint16_t)(245); + _curvea0[898] = _5654; + uint16_t _5655 = (uint16_t)(245); + _curvea0[899] = _5655; + uint16_t _5656 = (uint16_t)(245); + _curvea0[900] = _5656; + uint16_t _5657 = (uint16_t)(245); + _curvea0[901] = _5657; + uint16_t _5658 = (uint16_t)(245); + _curvea0[902] = _5658; + uint16_t _5659 = (uint16_t)(246); + _curvea0[903] = _5659; + uint16_t _5660 = (uint16_t)(246); + _curvea0[904] = _5660; + uint16_t _5661 = (uint16_t)(246); + _curvea0[905] = _5661; + uint16_t _5662 = (uint16_t)(246); + _curvea0[906] = _5662; + uint16_t _5663 = (uint16_t)(246); + _curvea0[907] = _5663; + uint16_t _5664 = (uint16_t)(246); + _curvea0[908] = _5664; + uint16_t _5665 = (uint16_t)(246); + _curvea0[909] = _5665; + uint16_t _5666 = (uint16_t)(246); + _curvea0[910] = _5666; + uint16_t _5667 = (uint16_t)(246); + _curvea0[911] = _5667; + uint16_t _5668 = (uint16_t)(246); + _curvea0[912] = _5668; + uint16_t _5669 = (uint16_t)(246); + _curvea0[913] = _5669; + uint16_t _5670 = (uint16_t)(247); + _curvea0[914] = _5670; + uint16_t _5671 = (uint16_t)(247); + _curvea0[915] = _5671; + uint16_t _5672 = (uint16_t)(247); + _curvea0[916] = _5672; + uint16_t _5673 = (uint16_t)(247); + _curvea0[917] = _5673; + uint16_t _5674 = (uint16_t)(247); + _curvea0[918] = _5674; + uint16_t _5675 = (uint16_t)(247); + _curvea0[919] = _5675; + uint16_t _5676 = (uint16_t)(247); + _curvea0[920] = _5676; + uint16_t _5677 = (uint16_t)(247); + _curvea0[921] = _5677; + uint16_t _5678 = (uint16_t)(247); + _curvea0[922] = _5678; + uint16_t _5679 = (uint16_t)(247); + _curvea0[923] = _5679; + uint16_t _5680 = (uint16_t)(247); + _curvea0[924] = _5680; + uint16_t _5681 = (uint16_t)(248); + _curvea0[925] = _5681; + uint16_t _5682 = (uint16_t)(248); + _curvea0[926] = _5682; + uint16_t _5683 = (uint16_t)(248); + _curvea0[927] = _5683; + uint16_t _5684 = (uint16_t)(248); + _curvea0[928] = _5684; + uint16_t _5685 = (uint16_t)(248); + _curvea0[929] = _5685; + uint16_t _5686 = (uint16_t)(248); + _curvea0[930] = _5686; + uint16_t _5687 = (uint16_t)(248); + _curvea0[931] = _5687; + uint16_t _5688 = (uint16_t)(248); + _curvea0[932] = _5688; + uint16_t _5689 = (uint16_t)(248); + _curvea0[933] = _5689; + uint16_t _5690 = (uint16_t)(248); + _curvea0[934] = _5690; + uint16_t _5691 = (uint16_t)(248); + _curvea0[935] = _5691; + uint16_t _5692 = (uint16_t)(249); + _curvea0[936] = _5692; + uint16_t _5693 = (uint16_t)(249); + _curvea0[937] = _5693; + uint16_t _5694 = (uint16_t)(249); + _curvea0[938] = _5694; + uint16_t _5695 = (uint16_t)(249); + _curvea0[939] = _5695; + uint16_t _5696 = (uint16_t)(249); + _curvea0[940] = _5696; + uint16_t _5697 = (uint16_t)(249); + _curvea0[941] = _5697; + uint16_t _5698 = (uint16_t)(249); + _curvea0[942] = _5698; + uint16_t _5699 = (uint16_t)(249); + _curvea0[943] = _5699; + uint16_t _5700 = (uint16_t)(249); + _curvea0[944] = _5700; + uint16_t _5701 = (uint16_t)(249); + _curvea0[945] = _5701; + uint16_t _5702 = (uint16_t)(249); + _curvea0[946] = _5702; + uint16_t _5703 = (uint16_t)(249); + _curvea0[947] = _5703; + uint16_t _5704 = (uint16_t)(250); + _curvea0[948] = _5704; + uint16_t _5705 = (uint16_t)(250); + _curvea0[949] = _5705; + uint16_t _5706 = (uint16_t)(250); + _curvea0[950] = _5706; + uint16_t _5707 = (uint16_t)(250); + _curvea0[951] = _5707; + uint16_t _5708 = (uint16_t)(250); + _curvea0[952] = _5708; + uint16_t _5709 = (uint16_t)(250); + _curvea0[953] = _5709; + uint16_t _5710 = (uint16_t)(250); + _curvea0[954] = _5710; + uint16_t _5711 = (uint16_t)(250); + _curvea0[955] = _5711; + uint16_t _5712 = (uint16_t)(250); + _curvea0[956] = _5712; + uint16_t _5713 = (uint16_t)(250); + _curvea0[957] = _5713; + uint16_t _5714 = (uint16_t)(250); + _curvea0[958] = _5714; + uint16_t _5715 = (uint16_t)(250); + _curvea0[959] = _5715; + uint16_t _5716 = (uint16_t)(251); + _curvea0[960] = _5716; + uint16_t _5717 = (uint16_t)(251); + _curvea0[961] = _5717; + uint16_t _5718 = (uint16_t)(251); + _curvea0[962] = _5718; + uint16_t _5719 = (uint16_t)(251); + _curvea0[963] = _5719; + uint16_t _5720 = (uint16_t)(251); + _curvea0[964] = _5720; + uint16_t _5721 = (uint16_t)(251); + _curvea0[965] = _5721; + uint16_t _5722 = (uint16_t)(251); + _curvea0[966] = _5722; + uint16_t _5723 = (uint16_t)(251); + _curvea0[967] = _5723; + uint16_t _5724 = (uint16_t)(251); + _curvea0[968] = _5724; + uint16_t _5725 = (uint16_t)(251); + _curvea0[969] = _5725; + uint16_t _5726 = (uint16_t)(251); + _curvea0[970] = _5726; + uint16_t _5727 = (uint16_t)(251); + _curvea0[971] = _5727; + uint16_t _5728 = (uint16_t)(252); + _curvea0[972] = _5728; + uint16_t _5729 = (uint16_t)(252); + _curvea0[973] = _5729; + uint16_t _5730 = (uint16_t)(252); + _curvea0[974] = _5730; + uint16_t _5731 = (uint16_t)(252); + _curvea0[975] = _5731; + uint16_t _5732 = (uint16_t)(252); + _curvea0[976] = _5732; + uint16_t _5733 = (uint16_t)(252); + _curvea0[977] = _5733; + uint16_t _5734 = (uint16_t)(252); + _curvea0[978] = _5734; + uint16_t _5735 = (uint16_t)(252); + _curvea0[979] = _5735; + uint16_t _5736 = (uint16_t)(252); + _curvea0[980] = _5736; + uint16_t _5737 = (uint16_t)(252); + _curvea0[981] = _5737; + uint16_t _5738 = (uint16_t)(252); + _curvea0[982] = _5738; + uint16_t _5739 = (uint16_t)(252); + _curvea0[983] = _5739; + uint16_t _5740 = (uint16_t)(252); + _curvea0[984] = _5740; + uint16_t _5741 = (uint16_t)(253); + _curvea0[985] = _5741; + uint16_t _5742 = (uint16_t)(253); + _curvea0[986] = _5742; + uint16_t _5743 = (uint16_t)(253); + _curvea0[987] = _5743; + uint16_t _5744 = (uint16_t)(253); + _curvea0[988] = _5744; + uint16_t _5745 = (uint16_t)(253); + _curvea0[989] = _5745; + uint16_t _5746 = (uint16_t)(253); + _curvea0[990] = _5746; + uint16_t _5747 = (uint16_t)(253); + _curvea0[991] = _5747; + uint16_t _5748 = (uint16_t)(253); + _curvea0[992] = _5748; + uint16_t _5749 = (uint16_t)(253); + _curvea0[993] = _5749; + uint16_t _5750 = (uint16_t)(253); + _curvea0[994] = _5750; + uint16_t _5751 = (uint16_t)(253); + _curvea0[995] = _5751; + uint16_t _5752 = (uint16_t)(253); + _curvea0[996] = _5752; + uint16_t _5753 = (uint16_t)(253); + _curvea0[997] = _5753; + uint16_t _5754 = (uint16_t)(254); + _curvea0[998] = _5754; + uint16_t _5755 = (uint16_t)(254); + _curvea0[999] = _5755; + uint16_t _5756 = (uint16_t)(254); + _curvea0[1000] = _5756; + uint16_t _5757 = (uint16_t)(254); + _curvea0[1001] = _5757; + uint16_t _5758 = (uint16_t)(254); + _curvea0[1002] = _5758; + uint16_t _5759 = (uint16_t)(254); + _curvea0[1003] = _5759; + uint16_t _5760 = (uint16_t)(254); + _curvea0[1004] = _5760; + uint16_t _5761 = (uint16_t)(254); + _curvea0[1005] = _5761; + uint16_t _5762 = (uint16_t)(254); + _curvea0[1006] = _5762; + uint16_t _5763 = (uint16_t)(254); + _curvea0[1007] = _5763; + uint16_t _5764 = (uint16_t)(254); + _curvea0[1008] = _5764; + uint16_t _5765 = (uint16_t)(254); + _curvea0[1009] = _5765; + uint16_t _5766 = (uint16_t)(254); + _curvea0[1010] = _5766; + uint16_t _5767 = (uint16_t)(255); + _curvea0[1011] = _5767; + uint16_t _5768 = (uint16_t)(255); + _curvea0[1012] = _5768; + uint16_t _5769 = (uint16_t)(255); + _curvea0[1013] = _5769; + uint16_t _5770 = (uint16_t)(255); + _curvea0[1014] = _5770; + uint16_t _5771 = (uint16_t)(255); + _curvea0[1015] = _5771; + uint16_t _5772 = (uint16_t)(255); + _curvea0[1016] = _5772; + uint16_t _5773 = (uint16_t)(255); + _curvea0[1017] = _5773; + uint16_t _5774 = (uint16_t)(255); + _curvea0[1018] = _5774; + uint16_t _5775 = (uint16_t)(255); + _curvea0[1019] = _5775; + uint16_t _5776 = (uint16_t)(255); + _curvea0[1020] = _5776; + uint16_t _5777 = (uint16_t)(255); + _curvea0[1021] = _5777; + uint16_t _5778 = (uint16_t)(255); + _curvea0[1022] = _5778; + uint16_t _5779 = (uint16_t)(255); + _curvea0[1023] = _5779; + + int16_t _5780 = (int16_t)(1023); + int16_t _5781 = min(_corrected_stencil_3, _5780); + int16_t _5782 = (int16_t)(0); + int16_t _5783 = max(_5781, _5782); + uint16_t _5784 = (uint16_t)(_5783); + int32_t _5785 = (int32_t)(_5784); + uint16_t _5786 = ((const uint16_t *)_curvea0)[_5785]; + return _5786; +} + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_3(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_4 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _5803 = (uint16_t)(0); + _curvea0[0] = _5803; + uint16_t _5804 = (uint16_t)(4); + _curvea0[1] = _5804; + uint16_t _5805 = (uint16_t)(7); + _curvea0[2] = _5805; + uint16_t _5806 = (uint16_t)(8); + _curvea0[3] = _5806; + uint16_t _5807 = (uint16_t)(10); + _curvea0[4] = _5807; + uint16_t _5808 = (uint16_t)(11); + _curvea0[5] = _5808; + uint16_t _5809 = (uint16_t)(12); + _curvea0[6] = _5809; + uint16_t _5810 = (uint16_t)(13); + _curvea0[7] = _5810; + uint16_t _5811 = (uint16_t)(14); + _curvea0[8] = _5811; + uint16_t _5812 = (uint16_t)(15); + _curvea0[9] = _5812; + uint16_t _5813 = (uint16_t)(16); + _curvea0[10] = _5813; + uint16_t _5814 = (uint16_t)(17); + _curvea0[11] = _5814; + uint16_t _5815 = (uint16_t)(18); + _curvea0[12] = _5815; + uint16_t _5816 = (uint16_t)(19); + _curvea0[13] = _5816; + uint16_t _5817 = (uint16_t)(20); + _curvea0[14] = _5817; + uint16_t _5818 = (uint16_t)(21); + _curvea0[15] = _5818; + uint16_t _5819 = (uint16_t)(22); + _curvea0[16] = _5819; + uint16_t _5820 = (uint16_t)(22); + _curvea0[17] = _5820; + uint16_t _5821 = (uint16_t)(23); + _curvea0[18] = _5821; + uint16_t _5822 = (uint16_t)(24); + _curvea0[19] = _5822; + uint16_t _5823 = (uint16_t)(25); + _curvea0[20] = _5823; + uint16_t _5824 = (uint16_t)(25); + _curvea0[21] = _5824; + uint16_t _5825 = (uint16_t)(26); + _curvea0[22] = _5825; + uint16_t _5826 = (uint16_t)(27); + _curvea0[23] = _5826; + uint16_t _5827 = (uint16_t)(27); + _curvea0[24] = _5827; + uint16_t _5828 = (uint16_t)(28); + _curvea0[25] = _5828; + uint16_t _5829 = (uint16_t)(29); + _curvea0[26] = _5829; + uint16_t _5830 = (uint16_t)(29); + _curvea0[27] = _5830; + uint16_t _5831 = (uint16_t)(30); + _curvea0[28] = _5831; + uint16_t _5832 = (uint16_t)(31); + _curvea0[29] = _5832; + uint16_t _5833 = (uint16_t)(31); + _curvea0[30] = _5833; + uint16_t _5834 = (uint16_t)(32); + _curvea0[31] = _5834; + uint16_t _5835 = (uint16_t)(33); + _curvea0[32] = _5835; + uint16_t _5836 = (uint16_t)(33); + _curvea0[33] = _5836; + uint16_t _5837 = (uint16_t)(34); + _curvea0[34] = _5837; + uint16_t _5838 = (uint16_t)(34); + _curvea0[35] = _5838; + uint16_t _5839 = (uint16_t)(35); + _curvea0[36] = _5839; + uint16_t _5840 = (uint16_t)(36); + _curvea0[37] = _5840; + uint16_t _5841 = (uint16_t)(36); + _curvea0[38] = _5841; + uint16_t _5842 = (uint16_t)(37); + _curvea0[39] = _5842; + uint16_t _5843 = (uint16_t)(37); + _curvea0[40] = _5843; + uint16_t _5844 = (uint16_t)(38); + _curvea0[41] = _5844; + uint16_t _5845 = (uint16_t)(39); + _curvea0[42] = _5845; + uint16_t _5846 = (uint16_t)(39); + _curvea0[43] = _5846; + uint16_t _5847 = (uint16_t)(40); + _curvea0[44] = _5847; + uint16_t _5848 = (uint16_t)(40); + _curvea0[45] = _5848; + uint16_t _5849 = (uint16_t)(41); + _curvea0[46] = _5849; + uint16_t _5850 = (uint16_t)(41); + _curvea0[47] = _5850; + uint16_t _5851 = (uint16_t)(42); + _curvea0[48] = _5851; + uint16_t _5852 = (uint16_t)(42); + _curvea0[49] = _5852; + uint16_t _5853 = (uint16_t)(43); + _curvea0[50] = _5853; + uint16_t _5854 = (uint16_t)(44); + _curvea0[51] = _5854; + uint16_t _5855 = (uint16_t)(44); + _curvea0[52] = _5855; + uint16_t _5856 = (uint16_t)(45); + _curvea0[53] = _5856; + uint16_t _5857 = (uint16_t)(45); + _curvea0[54] = _5857; + uint16_t _5858 = (uint16_t)(46); + _curvea0[55] = _5858; + uint16_t _5859 = (uint16_t)(46); + _curvea0[56] = _5859; + uint16_t _5860 = (uint16_t)(47); + _curvea0[57] = _5860; + uint16_t _5861 = (uint16_t)(47); + _curvea0[58] = _5861; + uint16_t _5862 = (uint16_t)(48); + _curvea0[59] = _5862; + uint16_t _5863 = (uint16_t)(48); + _curvea0[60] = _5863; + uint16_t _5864 = (uint16_t)(49); + _curvea0[61] = _5864; + uint16_t _5865 = (uint16_t)(49); + _curvea0[62] = _5865; + uint16_t _5866 = (uint16_t)(50); + _curvea0[63] = _5866; + uint16_t _5867 = (uint16_t)(50); + _curvea0[64] = _5867; + uint16_t _5868 = (uint16_t)(51); + _curvea0[65] = _5868; + uint16_t _5869 = (uint16_t)(51); + _curvea0[66] = _5869; + uint16_t _5870 = (uint16_t)(52); + _curvea0[67] = _5870; + uint16_t _5871 = (uint16_t)(52); + _curvea0[68] = _5871; + uint16_t _5872 = (uint16_t)(53); + _curvea0[69] = _5872; + uint16_t _5873 = (uint16_t)(53); + _curvea0[70] = _5873; + uint16_t _5874 = (uint16_t)(54); + _curvea0[71] = _5874; + uint16_t _5875 = (uint16_t)(54); + _curvea0[72] = _5875; + uint16_t _5876 = (uint16_t)(55); + _curvea0[73] = _5876; + uint16_t _5877 = (uint16_t)(55); + _curvea0[74] = _5877; + uint16_t _5878 = (uint16_t)(56); + _curvea0[75] = _5878; + uint16_t _5879 = (uint16_t)(56); + _curvea0[76] = _5879; + uint16_t _5880 = (uint16_t)(57); + _curvea0[77] = _5880; + uint16_t _5881 = (uint16_t)(57); + _curvea0[78] = _5881; + uint16_t _5882 = (uint16_t)(58); + _curvea0[79] = _5882; + uint16_t _5883 = (uint16_t)(58); + _curvea0[80] = _5883; + uint16_t _5884 = (uint16_t)(58); + _curvea0[81] = _5884; + uint16_t _5885 = (uint16_t)(59); + _curvea0[82] = _5885; + uint16_t _5886 = (uint16_t)(59); + _curvea0[83] = _5886; + uint16_t _5887 = (uint16_t)(60); + _curvea0[84] = _5887; + uint16_t _5888 = (uint16_t)(60); + _curvea0[85] = _5888; + uint16_t _5889 = (uint16_t)(61); + _curvea0[86] = _5889; + uint16_t _5890 = (uint16_t)(61); + _curvea0[87] = _5890; + uint16_t _5891 = (uint16_t)(62); + _curvea0[88] = _5891; + uint16_t _5892 = (uint16_t)(62); + _curvea0[89] = _5892; + uint16_t _5893 = (uint16_t)(63); + _curvea0[90] = _5893; + uint16_t _5894 = (uint16_t)(63); + _curvea0[91] = _5894; + uint16_t _5895 = (uint16_t)(64); + _curvea0[92] = _5895; + uint16_t _5896 = (uint16_t)(64); + _curvea0[93] = _5896; + uint16_t _5897 = (uint16_t)(64); + _curvea0[94] = _5897; + uint16_t _5898 = (uint16_t)(65); + _curvea0[95] = _5898; + uint16_t _5899 = (uint16_t)(65); + _curvea0[96] = _5899; + uint16_t _5900 = (uint16_t)(66); + _curvea0[97] = _5900; + uint16_t _5901 = (uint16_t)(66); + _curvea0[98] = _5901; + uint16_t _5902 = (uint16_t)(67); + _curvea0[99] = _5902; + uint16_t _5903 = (uint16_t)(67); + _curvea0[100] = _5903; + uint16_t _5904 = (uint16_t)(68); + _curvea0[101] = _5904; + uint16_t _5905 = (uint16_t)(68); + _curvea0[102] = _5905; + uint16_t _5906 = (uint16_t)(68); + _curvea0[103] = _5906; + uint16_t _5907 = (uint16_t)(69); + _curvea0[104] = _5907; + uint16_t _5908 = (uint16_t)(69); + _curvea0[105] = _5908; + uint16_t _5909 = (uint16_t)(70); + _curvea0[106] = _5909; + uint16_t _5910 = (uint16_t)(70); + _curvea0[107] = _5910; + uint16_t _5911 = (uint16_t)(71); + _curvea0[108] = _5911; + uint16_t _5912 = (uint16_t)(71); + _curvea0[109] = _5912; + uint16_t _5913 = (uint16_t)(71); + _curvea0[110] = _5913; + uint16_t _5914 = (uint16_t)(72); + _curvea0[111] = _5914; + uint16_t _5915 = (uint16_t)(72); + _curvea0[112] = _5915; + uint16_t _5916 = (uint16_t)(73); + _curvea0[113] = _5916; + uint16_t _5917 = (uint16_t)(73); + _curvea0[114] = _5917; + uint16_t _5918 = (uint16_t)(74); + _curvea0[115] = _5918; + uint16_t _5919 = (uint16_t)(74); + _curvea0[116] = _5919; + uint16_t _5920 = (uint16_t)(74); + _curvea0[117] = _5920; + uint16_t _5921 = (uint16_t)(75); + _curvea0[118] = _5921; + uint16_t _5922 = (uint16_t)(75); + _curvea0[119] = _5922; + uint16_t _5923 = (uint16_t)(76); + _curvea0[120] = _5923; + uint16_t _5924 = (uint16_t)(76); + _curvea0[121] = _5924; + uint16_t _5925 = (uint16_t)(77); + _curvea0[122] = _5925; + uint16_t _5926 = (uint16_t)(77); + _curvea0[123] = _5926; + uint16_t _5927 = (uint16_t)(77); + _curvea0[124] = _5927; + uint16_t _5928 = (uint16_t)(78); + _curvea0[125] = _5928; + uint16_t _5929 = (uint16_t)(78); + _curvea0[126] = _5929; + uint16_t _5930 = (uint16_t)(79); + _curvea0[127] = _5930; + uint16_t _5931 = (uint16_t)(79); + _curvea0[128] = _5931; + uint16_t _5932 = (uint16_t)(79); + _curvea0[129] = _5932; + uint16_t _5933 = (uint16_t)(80); + _curvea0[130] = _5933; + uint16_t _5934 = (uint16_t)(80); + _curvea0[131] = _5934; + uint16_t _5935 = (uint16_t)(81); + _curvea0[132] = _5935; + uint16_t _5936 = (uint16_t)(81); + _curvea0[133] = _5936; + uint16_t _5937 = (uint16_t)(82); + _curvea0[134] = _5937; + uint16_t _5938 = (uint16_t)(82); + _curvea0[135] = _5938; + uint16_t _5939 = (uint16_t)(82); + _curvea0[136] = _5939; + uint16_t _5940 = (uint16_t)(83); + _curvea0[137] = _5940; + uint16_t _5941 = (uint16_t)(83); + _curvea0[138] = _5941; + uint16_t _5942 = (uint16_t)(84); + _curvea0[139] = _5942; + uint16_t _5943 = (uint16_t)(84); + _curvea0[140] = _5943; + uint16_t _5944 = (uint16_t)(84); + _curvea0[141] = _5944; + uint16_t _5945 = (uint16_t)(85); + _curvea0[142] = _5945; + uint16_t _5946 = (uint16_t)(85); + _curvea0[143] = _5946; + uint16_t _5947 = (uint16_t)(86); + _curvea0[144] = _5947; + uint16_t _5948 = (uint16_t)(86); + _curvea0[145] = _5948; + uint16_t _5949 = (uint16_t)(86); + _curvea0[146] = _5949; + uint16_t _5950 = (uint16_t)(87); + _curvea0[147] = _5950; + uint16_t _5951 = (uint16_t)(87); + _curvea0[148] = _5951; + uint16_t _5952 = (uint16_t)(88); + _curvea0[149] = _5952; + uint16_t _5953 = (uint16_t)(88); + _curvea0[150] = _5953; + uint16_t _5954 = (uint16_t)(88); + _curvea0[151] = _5954; + uint16_t _5955 = (uint16_t)(89); + _curvea0[152] = _5955; + uint16_t _5956 = (uint16_t)(89); + _curvea0[153] = _5956; + uint16_t _5957 = (uint16_t)(90); + _curvea0[154] = _5957; + uint16_t _5958 = (uint16_t)(90); + _curvea0[155] = _5958; + uint16_t _5959 = (uint16_t)(90); + _curvea0[156] = _5959; + uint16_t _5960 = (uint16_t)(91); + _curvea0[157] = _5960; + uint16_t _5961 = (uint16_t)(91); + _curvea0[158] = _5961; + uint16_t _5962 = (uint16_t)(92); + _curvea0[159] = _5962; + uint16_t _5963 = (uint16_t)(92); + _curvea0[160] = _5963; + uint16_t _5964 = (uint16_t)(92); + _curvea0[161] = _5964; + uint16_t _5965 = (uint16_t)(93); + _curvea0[162] = _5965; + uint16_t _5966 = (uint16_t)(93); + _curvea0[163] = _5966; + uint16_t _5967 = (uint16_t)(93); + _curvea0[164] = _5967; + uint16_t _5968 = (uint16_t)(94); + _curvea0[165] = _5968; + uint16_t _5969 = (uint16_t)(94); + _curvea0[166] = _5969; + uint16_t _5970 = (uint16_t)(95); + _curvea0[167] = _5970; + uint16_t _5971 = (uint16_t)(95); + _curvea0[168] = _5971; + uint16_t _5972 = (uint16_t)(95); + _curvea0[169] = _5972; + uint16_t _5973 = (uint16_t)(96); + _curvea0[170] = _5973; + uint16_t _5974 = (uint16_t)(96); + _curvea0[171] = _5974; + uint16_t _5975 = (uint16_t)(97); + _curvea0[172] = _5975; + uint16_t _5976 = (uint16_t)(97); + _curvea0[173] = _5976; + uint16_t _5977 = (uint16_t)(97); + _curvea0[174] = _5977; + uint16_t _5978 = (uint16_t)(98); + _curvea0[175] = _5978; + uint16_t _5979 = (uint16_t)(98); + _curvea0[176] = _5979; + uint16_t _5980 = (uint16_t)(99); + _curvea0[177] = _5980; + uint16_t _5981 = (uint16_t)(99); + _curvea0[178] = _5981; + uint16_t _5982 = (uint16_t)(99); + _curvea0[179] = _5982; + uint16_t _5983 = (uint16_t)(100); + _curvea0[180] = _5983; + uint16_t _5984 = (uint16_t)(100); + _curvea0[181] = _5984; + uint16_t _5985 = (uint16_t)(100); + _curvea0[182] = _5985; + uint16_t _5986 = (uint16_t)(101); + _curvea0[183] = _5986; + uint16_t _5987 = (uint16_t)(101); + _curvea0[184] = _5987; + uint16_t _5988 = (uint16_t)(102); + _curvea0[185] = _5988; + uint16_t _5989 = (uint16_t)(102); + _curvea0[186] = _5989; + uint16_t _5990 = (uint16_t)(102); + _curvea0[187] = _5990; + uint16_t _5991 = (uint16_t)(103); + _curvea0[188] = _5991; + uint16_t _5992 = (uint16_t)(103); + _curvea0[189] = _5992; + uint16_t _5993 = (uint16_t)(103); + _curvea0[190] = _5993; + uint16_t _5994 = (uint16_t)(104); + _curvea0[191] = _5994; + uint16_t _5995 = (uint16_t)(104); + _curvea0[192] = _5995; + uint16_t _5996 = (uint16_t)(105); + _curvea0[193] = _5996; + uint16_t _5997 = (uint16_t)(105); + _curvea0[194] = _5997; + uint16_t _5998 = (uint16_t)(105); + _curvea0[195] = _5998; + uint16_t _5999 = (uint16_t)(106); + _curvea0[196] = _5999; + uint16_t _6000 = (uint16_t)(106); + _curvea0[197] = _6000; + uint16_t _6001 = (uint16_t)(106); + _curvea0[198] = _6001; + uint16_t _6002 = (uint16_t)(107); + _curvea0[199] = _6002; + uint16_t _6003 = (uint16_t)(107); + _curvea0[200] = _6003; + uint16_t _6004 = (uint16_t)(108); + _curvea0[201] = _6004; + uint16_t _6005 = (uint16_t)(108); + _curvea0[202] = _6005; + uint16_t _6006 = (uint16_t)(108); + _curvea0[203] = _6006; + uint16_t _6007 = (uint16_t)(109); + _curvea0[204] = _6007; + uint16_t _6008 = (uint16_t)(109); + _curvea0[205] = _6008; + uint16_t _6009 = (uint16_t)(109); + _curvea0[206] = _6009; + uint16_t _6010 = (uint16_t)(110); + _curvea0[207] = _6010; + uint16_t _6011 = (uint16_t)(110); + _curvea0[208] = _6011; + uint16_t _6012 = (uint16_t)(111); + _curvea0[209] = _6012; + uint16_t _6013 = (uint16_t)(111); + _curvea0[210] = _6013; + uint16_t _6014 = (uint16_t)(111); + _curvea0[211] = _6014; + uint16_t _6015 = (uint16_t)(112); + _curvea0[212] = _6015; + uint16_t _6016 = (uint16_t)(112); + _curvea0[213] = _6016; + uint16_t _6017 = (uint16_t)(112); + _curvea0[214] = _6017; + uint16_t _6018 = (uint16_t)(113); + _curvea0[215] = _6018; + uint16_t _6019 = (uint16_t)(113); + _curvea0[216] = _6019; + uint16_t _6020 = (uint16_t)(113); + _curvea0[217] = _6020; + uint16_t _6021 = (uint16_t)(114); + _curvea0[218] = _6021; + uint16_t _6022 = (uint16_t)(114); + _curvea0[219] = _6022; + uint16_t _6023 = (uint16_t)(115); + _curvea0[220] = _6023; + uint16_t _6024 = (uint16_t)(115); + _curvea0[221] = _6024; + uint16_t _6025 = (uint16_t)(115); + _curvea0[222] = _6025; + uint16_t _6026 = (uint16_t)(116); + _curvea0[223] = _6026; + uint16_t _6027 = (uint16_t)(116); + _curvea0[224] = _6027; + uint16_t _6028 = (uint16_t)(116); + _curvea0[225] = _6028; + uint16_t _6029 = (uint16_t)(117); + _curvea0[226] = _6029; + uint16_t _6030 = (uint16_t)(117); + _curvea0[227] = _6030; + uint16_t _6031 = (uint16_t)(117); + _curvea0[228] = _6031; + uint16_t _6032 = (uint16_t)(118); + _curvea0[229] = _6032; + uint16_t _6033 = (uint16_t)(118); + _curvea0[230] = _6033; + uint16_t _6034 = (uint16_t)(119); + _curvea0[231] = _6034; + uint16_t _6035 = (uint16_t)(119); + _curvea0[232] = _6035; + uint16_t _6036 = (uint16_t)(119); + _curvea0[233] = _6036; + uint16_t _6037 = (uint16_t)(120); + _curvea0[234] = _6037; + uint16_t _6038 = (uint16_t)(120); + _curvea0[235] = _6038; + uint16_t _6039 = (uint16_t)(120); + _curvea0[236] = _6039; + uint16_t _6040 = (uint16_t)(121); + _curvea0[237] = _6040; + uint16_t _6041 = (uint16_t)(121); + _curvea0[238] = _6041; + uint16_t _6042 = (uint16_t)(121); + _curvea0[239] = _6042; + uint16_t _6043 = (uint16_t)(122); + _curvea0[240] = _6043; + uint16_t _6044 = (uint16_t)(122); + _curvea0[241] = _6044; + uint16_t _6045 = (uint16_t)(123); + _curvea0[242] = _6045; + uint16_t _6046 = (uint16_t)(123); + _curvea0[243] = _6046; + uint16_t _6047 = (uint16_t)(123); + _curvea0[244] = _6047; + uint16_t _6048 = (uint16_t)(124); + _curvea0[245] = _6048; + uint16_t _6049 = (uint16_t)(124); + _curvea0[246] = _6049; + uint16_t _6050 = (uint16_t)(124); + _curvea0[247] = _6050; + uint16_t _6051 = (uint16_t)(125); + _curvea0[248] = _6051; + uint16_t _6052 = (uint16_t)(125); + _curvea0[249] = _6052; + uint16_t _6053 = (uint16_t)(125); + _curvea0[250] = _6053; + uint16_t _6054 = (uint16_t)(126); + _curvea0[251] = _6054; + uint16_t _6055 = (uint16_t)(126); + _curvea0[252] = _6055; + uint16_t _6056 = (uint16_t)(126); + _curvea0[253] = _6056; + uint16_t _6057 = (uint16_t)(127); + _curvea0[254] = _6057; + uint16_t _6058 = (uint16_t)(127); + _curvea0[255] = _6058; + uint16_t _6059 = (uint16_t)(128); + _curvea0[256] = _6059; + uint16_t _6060 = (uint16_t)(128); + _curvea0[257] = _6060; + uint16_t _6061 = (uint16_t)(128); + _curvea0[258] = _6061; + uint16_t _6062 = (uint16_t)(129); + _curvea0[259] = _6062; + uint16_t _6063 = (uint16_t)(129); + _curvea0[260] = _6063; + uint16_t _6064 = (uint16_t)(129); + _curvea0[261] = _6064; + uint16_t _6065 = (uint16_t)(130); + _curvea0[262] = _6065; + uint16_t _6066 = (uint16_t)(130); + _curvea0[263] = _6066; + uint16_t _6067 = (uint16_t)(130); + _curvea0[264] = _6067; + uint16_t _6068 = (uint16_t)(131); + _curvea0[265] = _6068; + uint16_t _6069 = (uint16_t)(131); + _curvea0[266] = _6069; + uint16_t _6070 = (uint16_t)(131); + _curvea0[267] = _6070; + uint16_t _6071 = (uint16_t)(132); + _curvea0[268] = _6071; + uint16_t _6072 = (uint16_t)(132); + _curvea0[269] = _6072; + uint16_t _6073 = (uint16_t)(132); + _curvea0[270] = _6073; + uint16_t _6074 = (uint16_t)(133); + _curvea0[271] = _6074; + uint16_t _6075 = (uint16_t)(133); + _curvea0[272] = _6075; + uint16_t _6076 = (uint16_t)(133); + _curvea0[273] = _6076; + uint16_t _6077 = (uint16_t)(134); + _curvea0[274] = _6077; + uint16_t _6078 = (uint16_t)(134); + _curvea0[275] = _6078; + uint16_t _6079 = (uint16_t)(134); + _curvea0[276] = _6079; + uint16_t _6080 = (uint16_t)(135); + _curvea0[277] = _6080; + uint16_t _6081 = (uint16_t)(135); + _curvea0[278] = _6081; + uint16_t _6082 = (uint16_t)(135); + _curvea0[279] = _6082; + uint16_t _6083 = (uint16_t)(136); + _curvea0[280] = _6083; + uint16_t _6084 = (uint16_t)(136); + _curvea0[281] = _6084; + uint16_t _6085 = (uint16_t)(136); + _curvea0[282] = _6085; + uint16_t _6086 = (uint16_t)(137); + _curvea0[283] = _6086; + uint16_t _6087 = (uint16_t)(137); + _curvea0[284] = _6087; + uint16_t _6088 = (uint16_t)(137); + _curvea0[285] = _6088; + uint16_t _6089 = (uint16_t)(138); + _curvea0[286] = _6089; + uint16_t _6090 = (uint16_t)(138); + _curvea0[287] = _6090; + uint16_t _6091 = (uint16_t)(138); + _curvea0[288] = _6091; + uint16_t _6092 = (uint16_t)(139); + _curvea0[289] = _6092; + uint16_t _6093 = (uint16_t)(139); + _curvea0[290] = _6093; + uint16_t _6094 = (uint16_t)(139); + _curvea0[291] = _6094; + uint16_t _6095 = (uint16_t)(140); + _curvea0[292] = _6095; + uint16_t _6096 = (uint16_t)(140); + _curvea0[293] = _6096; + uint16_t _6097 = (uint16_t)(140); + _curvea0[294] = _6097; + uint16_t _6098 = (uint16_t)(141); + _curvea0[295] = _6098; + uint16_t _6099 = (uint16_t)(141); + _curvea0[296] = _6099; + uint16_t _6100 = (uint16_t)(141); + _curvea0[297] = _6100; + uint16_t _6101 = (uint16_t)(141); + _curvea0[298] = _6101; + uint16_t _6102 = (uint16_t)(142); + _curvea0[299] = _6102; + uint16_t _6103 = (uint16_t)(142); + _curvea0[300] = _6103; + uint16_t _6104 = (uint16_t)(142); + _curvea0[301] = _6104; + uint16_t _6105 = (uint16_t)(143); + _curvea0[302] = _6105; + uint16_t _6106 = (uint16_t)(143); + _curvea0[303] = _6106; + uint16_t _6107 = (uint16_t)(143); + _curvea0[304] = _6107; + uint16_t _6108 = (uint16_t)(144); + _curvea0[305] = _6108; + uint16_t _6109 = (uint16_t)(144); + _curvea0[306] = _6109; + uint16_t _6110 = (uint16_t)(144); + _curvea0[307] = _6110; + uint16_t _6111 = (uint16_t)(145); + _curvea0[308] = _6111; + uint16_t _6112 = (uint16_t)(145); + _curvea0[309] = _6112; + uint16_t _6113 = (uint16_t)(145); + _curvea0[310] = _6113; + uint16_t _6114 = (uint16_t)(145); + _curvea0[311] = _6114; + uint16_t _6115 = (uint16_t)(146); + _curvea0[312] = _6115; + uint16_t _6116 = (uint16_t)(146); + _curvea0[313] = _6116; + uint16_t _6117 = (uint16_t)(146); + _curvea0[314] = _6117; + uint16_t _6118 = (uint16_t)(147); + _curvea0[315] = _6118; + uint16_t _6119 = (uint16_t)(147); + _curvea0[316] = _6119; + uint16_t _6120 = (uint16_t)(147); + _curvea0[317] = _6120; + uint16_t _6121 = (uint16_t)(148); + _curvea0[318] = _6121; + uint16_t _6122 = (uint16_t)(148); + _curvea0[319] = _6122; + uint16_t _6123 = (uint16_t)(148); + _curvea0[320] = _6123; + uint16_t _6124 = (uint16_t)(148); + _curvea0[321] = _6124; + uint16_t _6125 = (uint16_t)(149); + _curvea0[322] = _6125; + uint16_t _6126 = (uint16_t)(149); + _curvea0[323] = _6126; + uint16_t _6127 = (uint16_t)(149); + _curvea0[324] = _6127; + uint16_t _6128 = (uint16_t)(150); + _curvea0[325] = _6128; + uint16_t _6129 = (uint16_t)(150); + _curvea0[326] = _6129; + uint16_t _6130 = (uint16_t)(150); + _curvea0[327] = _6130; + uint16_t _6131 = (uint16_t)(150); + _curvea0[328] = _6131; + uint16_t _6132 = (uint16_t)(151); + _curvea0[329] = _6132; + uint16_t _6133 = (uint16_t)(151); + _curvea0[330] = _6133; + uint16_t _6134 = (uint16_t)(151); + _curvea0[331] = _6134; + uint16_t _6135 = (uint16_t)(152); + _curvea0[332] = _6135; + uint16_t _6136 = (uint16_t)(152); + _curvea0[333] = _6136; + uint16_t _6137 = (uint16_t)(152); + _curvea0[334] = _6137; + uint16_t _6138 = (uint16_t)(152); + _curvea0[335] = _6138; + uint16_t _6139 = (uint16_t)(153); + _curvea0[336] = _6139; + uint16_t _6140 = (uint16_t)(153); + _curvea0[337] = _6140; + uint16_t _6141 = (uint16_t)(153); + _curvea0[338] = _6141; + uint16_t _6142 = (uint16_t)(154); + _curvea0[339] = _6142; + uint16_t _6143 = (uint16_t)(154); + _curvea0[340] = _6143; + uint16_t _6144 = (uint16_t)(154); + _curvea0[341] = _6144; + uint16_t _6145 = (uint16_t)(154); + _curvea0[342] = _6145; + uint16_t _6146 = (uint16_t)(155); + _curvea0[343] = _6146; + uint16_t _6147 = (uint16_t)(155); + _curvea0[344] = _6147; + uint16_t _6148 = (uint16_t)(155); + _curvea0[345] = _6148; + uint16_t _6149 = (uint16_t)(156); + _curvea0[346] = _6149; + uint16_t _6150 = (uint16_t)(156); + _curvea0[347] = _6150; + uint16_t _6151 = (uint16_t)(156); + _curvea0[348] = _6151; + uint16_t _6152 = (uint16_t)(156); + _curvea0[349] = _6152; + uint16_t _6153 = (uint16_t)(157); + _curvea0[350] = _6153; + uint16_t _6154 = (uint16_t)(157); + _curvea0[351] = _6154; + uint16_t _6155 = (uint16_t)(157); + _curvea0[352] = _6155; + uint16_t _6156 = (uint16_t)(157); + _curvea0[353] = _6156; + uint16_t _6157 = (uint16_t)(158); + _curvea0[354] = _6157; + uint16_t _6158 = (uint16_t)(158); + _curvea0[355] = _6158; + uint16_t _6159 = (uint16_t)(158); + _curvea0[356] = _6159; + uint16_t _6160 = (uint16_t)(159); + _curvea0[357] = _6160; + uint16_t _6161 = (uint16_t)(159); + _curvea0[358] = _6161; + uint16_t _6162 = (uint16_t)(159); + _curvea0[359] = _6162; + uint16_t _6163 = (uint16_t)(159); + _curvea0[360] = _6163; + uint16_t _6164 = (uint16_t)(160); + _curvea0[361] = _6164; + uint16_t _6165 = (uint16_t)(160); + _curvea0[362] = _6165; + uint16_t _6166 = (uint16_t)(160); + _curvea0[363] = _6166; + uint16_t _6167 = (uint16_t)(160); + _curvea0[364] = _6167; + uint16_t _6168 = (uint16_t)(161); + _curvea0[365] = _6168; + uint16_t _6169 = (uint16_t)(161); + _curvea0[366] = _6169; + uint16_t _6170 = (uint16_t)(161); + _curvea0[367] = _6170; + uint16_t _6171 = (uint16_t)(161); + _curvea0[368] = _6171; + uint16_t _6172 = (uint16_t)(162); + _curvea0[369] = _6172; + uint16_t _6173 = (uint16_t)(162); + _curvea0[370] = _6173; + uint16_t _6174 = (uint16_t)(162); + _curvea0[371] = _6174; + uint16_t _6175 = (uint16_t)(162); + _curvea0[372] = _6175; + uint16_t _6176 = (uint16_t)(163); + _curvea0[373] = _6176; + uint16_t _6177 = (uint16_t)(163); + _curvea0[374] = _6177; + uint16_t _6178 = (uint16_t)(163); + _curvea0[375] = _6178; + uint16_t _6179 = (uint16_t)(163); + _curvea0[376] = _6179; + uint16_t _6180 = (uint16_t)(164); + _curvea0[377] = _6180; + uint16_t _6181 = (uint16_t)(164); + _curvea0[378] = _6181; + uint16_t _6182 = (uint16_t)(164); + _curvea0[379] = _6182; + uint16_t _6183 = (uint16_t)(164); + _curvea0[380] = _6183; + uint16_t _6184 = (uint16_t)(165); + _curvea0[381] = _6184; + uint16_t _6185 = (uint16_t)(165); + _curvea0[382] = _6185; + uint16_t _6186 = (uint16_t)(165); + _curvea0[383] = _6186; + uint16_t _6187 = (uint16_t)(166); + _curvea0[384] = _6187; + uint16_t _6188 = (uint16_t)(166); + _curvea0[385] = _6188; + uint16_t _6189 = (uint16_t)(166); + _curvea0[386] = _6189; + uint16_t _6190 = (uint16_t)(166); + _curvea0[387] = _6190; + uint16_t _6191 = (uint16_t)(167); + _curvea0[388] = _6191; + uint16_t _6192 = (uint16_t)(167); + _curvea0[389] = _6192; + uint16_t _6193 = (uint16_t)(167); + _curvea0[390] = _6193; + uint16_t _6194 = (uint16_t)(167); + _curvea0[391] = _6194; + uint16_t _6195 = (uint16_t)(167); + _curvea0[392] = _6195; + uint16_t _6196 = (uint16_t)(168); + _curvea0[393] = _6196; + uint16_t _6197 = (uint16_t)(168); + _curvea0[394] = _6197; + uint16_t _6198 = (uint16_t)(168); + _curvea0[395] = _6198; + uint16_t _6199 = (uint16_t)(168); + _curvea0[396] = _6199; + uint16_t _6200 = (uint16_t)(169); + _curvea0[397] = _6200; + uint16_t _6201 = (uint16_t)(169); + _curvea0[398] = _6201; + uint16_t _6202 = (uint16_t)(169); + _curvea0[399] = _6202; + uint16_t _6203 = (uint16_t)(169); + _curvea0[400] = _6203; + uint16_t _6204 = (uint16_t)(170); + _curvea0[401] = _6204; + uint16_t _6205 = (uint16_t)(170); + _curvea0[402] = _6205; + uint16_t _6206 = (uint16_t)(170); + _curvea0[403] = _6206; + uint16_t _6207 = (uint16_t)(170); + _curvea0[404] = _6207; + uint16_t _6208 = (uint16_t)(171); + _curvea0[405] = _6208; + uint16_t _6209 = (uint16_t)(171); + _curvea0[406] = _6209; + uint16_t _6210 = (uint16_t)(171); + _curvea0[407] = _6210; + uint16_t _6211 = (uint16_t)(171); + _curvea0[408] = _6211; + uint16_t _6212 = (uint16_t)(172); + _curvea0[409] = _6212; + uint16_t _6213 = (uint16_t)(172); + _curvea0[410] = _6213; + uint16_t _6214 = (uint16_t)(172); + _curvea0[411] = _6214; + uint16_t _6215 = (uint16_t)(172); + _curvea0[412] = _6215; + uint16_t _6216 = (uint16_t)(173); + _curvea0[413] = _6216; + uint16_t _6217 = (uint16_t)(173); + _curvea0[414] = _6217; + uint16_t _6218 = (uint16_t)(173); + _curvea0[415] = _6218; + uint16_t _6219 = (uint16_t)(173); + _curvea0[416] = _6219; + uint16_t _6220 = (uint16_t)(173); + _curvea0[417] = _6220; + uint16_t _6221 = (uint16_t)(174); + _curvea0[418] = _6221; + uint16_t _6222 = (uint16_t)(174); + _curvea0[419] = _6222; + uint16_t _6223 = (uint16_t)(174); + _curvea0[420] = _6223; + uint16_t _6224 = (uint16_t)(174); + _curvea0[421] = _6224; + uint16_t _6225 = (uint16_t)(175); + _curvea0[422] = _6225; + uint16_t _6226 = (uint16_t)(175); + _curvea0[423] = _6226; + uint16_t _6227 = (uint16_t)(175); + _curvea0[424] = _6227; + uint16_t _6228 = (uint16_t)(175); + _curvea0[425] = _6228; + uint16_t _6229 = (uint16_t)(176); + _curvea0[426] = _6229; + uint16_t _6230 = (uint16_t)(176); + _curvea0[427] = _6230; + uint16_t _6231 = (uint16_t)(176); + _curvea0[428] = _6231; + uint16_t _6232 = (uint16_t)(176); + _curvea0[429] = _6232; + uint16_t _6233 = (uint16_t)(176); + _curvea0[430] = _6233; + uint16_t _6234 = (uint16_t)(177); + _curvea0[431] = _6234; + uint16_t _6235 = (uint16_t)(177); + _curvea0[432] = _6235; + uint16_t _6236 = (uint16_t)(177); + _curvea0[433] = _6236; + uint16_t _6237 = (uint16_t)(177); + _curvea0[434] = _6237; + uint16_t _6238 = (uint16_t)(178); + _curvea0[435] = _6238; + uint16_t _6239 = (uint16_t)(178); + _curvea0[436] = _6239; + uint16_t _6240 = (uint16_t)(178); + _curvea0[437] = _6240; + uint16_t _6241 = (uint16_t)(178); + _curvea0[438] = _6241; + uint16_t _6242 = (uint16_t)(178); + _curvea0[439] = _6242; + uint16_t _6243 = (uint16_t)(179); + _curvea0[440] = _6243; + uint16_t _6244 = (uint16_t)(179); + _curvea0[441] = _6244; + uint16_t _6245 = (uint16_t)(179); + _curvea0[442] = _6245; + uint16_t _6246 = (uint16_t)(179); + _curvea0[443] = _6246; + uint16_t _6247 = (uint16_t)(180); + _curvea0[444] = _6247; + uint16_t _6248 = (uint16_t)(180); + _curvea0[445] = _6248; + uint16_t _6249 = (uint16_t)(180); + _curvea0[446] = _6249; + uint16_t _6250 = (uint16_t)(180); + _curvea0[447] = _6250; + uint16_t _6251 = (uint16_t)(180); + _curvea0[448] = _6251; + uint16_t _6252 = (uint16_t)(181); + _curvea0[449] = _6252; + uint16_t _6253 = (uint16_t)(181); + _curvea0[450] = _6253; + uint16_t _6254 = (uint16_t)(181); + _curvea0[451] = _6254; + uint16_t _6255 = (uint16_t)(181); + _curvea0[452] = _6255; + uint16_t _6256 = (uint16_t)(181); + _curvea0[453] = _6256; + uint16_t _6257 = (uint16_t)(182); + _curvea0[454] = _6257; + uint16_t _6258 = (uint16_t)(182); + _curvea0[455] = _6258; + uint16_t _6259 = (uint16_t)(182); + _curvea0[456] = _6259; + uint16_t _6260 = (uint16_t)(182); + _curvea0[457] = _6260; + uint16_t _6261 = (uint16_t)(183); + _curvea0[458] = _6261; + uint16_t _6262 = (uint16_t)(183); + _curvea0[459] = _6262; + uint16_t _6263 = (uint16_t)(183); + _curvea0[460] = _6263; + uint16_t _6264 = (uint16_t)(183); + _curvea0[461] = _6264; + uint16_t _6265 = (uint16_t)(183); + _curvea0[462] = _6265; + uint16_t _6266 = (uint16_t)(184); + _curvea0[463] = _6266; + uint16_t _6267 = (uint16_t)(184); + _curvea0[464] = _6267; + uint16_t _6268 = (uint16_t)(184); + _curvea0[465] = _6268; + uint16_t _6269 = (uint16_t)(184); + _curvea0[466] = _6269; + uint16_t _6270 = (uint16_t)(184); + _curvea0[467] = _6270; + uint16_t _6271 = (uint16_t)(185); + _curvea0[468] = _6271; + uint16_t _6272 = (uint16_t)(185); + _curvea0[469] = _6272; + uint16_t _6273 = (uint16_t)(185); + _curvea0[470] = _6273; + uint16_t _6274 = (uint16_t)(185); + _curvea0[471] = _6274; + uint16_t _6275 = (uint16_t)(185); + _curvea0[472] = _6275; + uint16_t _6276 = (uint16_t)(186); + _curvea0[473] = _6276; + uint16_t _6277 = (uint16_t)(186); + _curvea0[474] = _6277; + uint16_t _6278 = (uint16_t)(186); + _curvea0[475] = _6278; + uint16_t _6279 = (uint16_t)(186); + _curvea0[476] = _6279; + uint16_t _6280 = (uint16_t)(187); + _curvea0[477] = _6280; + uint16_t _6281 = (uint16_t)(187); + _curvea0[478] = _6281; + uint16_t _6282 = (uint16_t)(187); + _curvea0[479] = _6282; + uint16_t _6283 = (uint16_t)(187); + _curvea0[480] = _6283; + uint16_t _6284 = (uint16_t)(187); + _curvea0[481] = _6284; + uint16_t _6285 = (uint16_t)(188); + _curvea0[482] = _6285; + uint16_t _6286 = (uint16_t)(188); + _curvea0[483] = _6286; + uint16_t _6287 = (uint16_t)(188); + _curvea0[484] = _6287; + uint16_t _6288 = (uint16_t)(188); + _curvea0[485] = _6288; + uint16_t _6289 = (uint16_t)(188); + _curvea0[486] = _6289; + uint16_t _6290 = (uint16_t)(189); + _curvea0[487] = _6290; + uint16_t _6291 = (uint16_t)(189); + _curvea0[488] = _6291; + uint16_t _6292 = (uint16_t)(189); + _curvea0[489] = _6292; + uint16_t _6293 = (uint16_t)(189); + _curvea0[490] = _6293; + uint16_t _6294 = (uint16_t)(189); + _curvea0[491] = _6294; + uint16_t _6295 = (uint16_t)(190); + _curvea0[492] = _6295; + uint16_t _6296 = (uint16_t)(190); + _curvea0[493] = _6296; + uint16_t _6297 = (uint16_t)(190); + _curvea0[494] = _6297; + uint16_t _6298 = (uint16_t)(190); + _curvea0[495] = _6298; + uint16_t _6299 = (uint16_t)(190); + _curvea0[496] = _6299; + uint16_t _6300 = (uint16_t)(190); + _curvea0[497] = _6300; + uint16_t _6301 = (uint16_t)(191); + _curvea0[498] = _6301; + uint16_t _6302 = (uint16_t)(191); + _curvea0[499] = _6302; + uint16_t _6303 = (uint16_t)(191); + _curvea0[500] = _6303; + uint16_t _6304 = (uint16_t)(191); + _curvea0[501] = _6304; + uint16_t _6305 = (uint16_t)(191); + _curvea0[502] = _6305; + uint16_t _6306 = (uint16_t)(192); + _curvea0[503] = _6306; + uint16_t _6307 = (uint16_t)(192); + _curvea0[504] = _6307; + uint16_t _6308 = (uint16_t)(192); + _curvea0[505] = _6308; + uint16_t _6309 = (uint16_t)(192); + _curvea0[506] = _6309; + uint16_t _6310 = (uint16_t)(192); + _curvea0[507] = _6310; + uint16_t _6311 = (uint16_t)(193); + _curvea0[508] = _6311; + uint16_t _6312 = (uint16_t)(193); + _curvea0[509] = _6312; + uint16_t _6313 = (uint16_t)(193); + _curvea0[510] = _6313; + uint16_t _6314 = (uint16_t)(193); + _curvea0[511] = _6314; + uint16_t _6315 = (uint16_t)(193); + _curvea0[512] = _6315; + uint16_t _6316 = (uint16_t)(194); + _curvea0[513] = _6316; + uint16_t _6317 = (uint16_t)(194); + _curvea0[514] = _6317; + uint16_t _6318 = (uint16_t)(194); + _curvea0[515] = _6318; + uint16_t _6319 = (uint16_t)(194); + _curvea0[516] = _6319; + uint16_t _6320 = (uint16_t)(194); + _curvea0[517] = _6320; + uint16_t _6321 = (uint16_t)(195); + _curvea0[518] = _6321; + uint16_t _6322 = (uint16_t)(195); + _curvea0[519] = _6322; + uint16_t _6323 = (uint16_t)(195); + _curvea0[520] = _6323; + uint16_t _6324 = (uint16_t)(195); + _curvea0[521] = _6324; + uint16_t _6325 = (uint16_t)(195); + _curvea0[522] = _6325; + uint16_t _6326 = (uint16_t)(195); + _curvea0[523] = _6326; + uint16_t _6327 = (uint16_t)(196); + _curvea0[524] = _6327; + uint16_t _6328 = (uint16_t)(196); + _curvea0[525] = _6328; + uint16_t _6329 = (uint16_t)(196); + _curvea0[526] = _6329; + uint16_t _6330 = (uint16_t)(196); + _curvea0[527] = _6330; + uint16_t _6331 = (uint16_t)(196); + _curvea0[528] = _6331; + uint16_t _6332 = (uint16_t)(197); + _curvea0[529] = _6332; + uint16_t _6333 = (uint16_t)(197); + _curvea0[530] = _6333; + uint16_t _6334 = (uint16_t)(197); + _curvea0[531] = _6334; + uint16_t _6335 = (uint16_t)(197); + _curvea0[532] = _6335; + uint16_t _6336 = (uint16_t)(197); + _curvea0[533] = _6336; + uint16_t _6337 = (uint16_t)(197); + _curvea0[534] = _6337; + uint16_t _6338 = (uint16_t)(198); + _curvea0[535] = _6338; + uint16_t _6339 = (uint16_t)(198); + _curvea0[536] = _6339; + uint16_t _6340 = (uint16_t)(198); + _curvea0[537] = _6340; + uint16_t _6341 = (uint16_t)(198); + _curvea0[538] = _6341; + uint16_t _6342 = (uint16_t)(198); + _curvea0[539] = _6342; + uint16_t _6343 = (uint16_t)(199); + _curvea0[540] = _6343; + uint16_t _6344 = (uint16_t)(199); + _curvea0[541] = _6344; + uint16_t _6345 = (uint16_t)(199); + _curvea0[542] = _6345; + uint16_t _6346 = (uint16_t)(199); + _curvea0[543] = _6346; + uint16_t _6347 = (uint16_t)(199); + _curvea0[544] = _6347; + uint16_t _6348 = (uint16_t)(199); + _curvea0[545] = _6348; + uint16_t _6349 = (uint16_t)(200); + _curvea0[546] = _6349; + uint16_t _6350 = (uint16_t)(200); + _curvea0[547] = _6350; + uint16_t _6351 = (uint16_t)(200); + _curvea0[548] = _6351; + uint16_t _6352 = (uint16_t)(200); + _curvea0[549] = _6352; + uint16_t _6353 = (uint16_t)(200); + _curvea0[550] = _6353; + uint16_t _6354 = (uint16_t)(200); + _curvea0[551] = _6354; + uint16_t _6355 = (uint16_t)(201); + _curvea0[552] = _6355; + uint16_t _6356 = (uint16_t)(201); + _curvea0[553] = _6356; + uint16_t _6357 = (uint16_t)(201); + _curvea0[554] = _6357; + uint16_t _6358 = (uint16_t)(201); + _curvea0[555] = _6358; + uint16_t _6359 = (uint16_t)(201); + _curvea0[556] = _6359; + uint16_t _6360 = (uint16_t)(202); + _curvea0[557] = _6360; + uint16_t _6361 = (uint16_t)(202); + _curvea0[558] = _6361; + uint16_t _6362 = (uint16_t)(202); + _curvea0[559] = _6362; + uint16_t _6363 = (uint16_t)(202); + _curvea0[560] = _6363; + uint16_t _6364 = (uint16_t)(202); + _curvea0[561] = _6364; + uint16_t _6365 = (uint16_t)(202); + _curvea0[562] = _6365; + uint16_t _6366 = (uint16_t)(203); + _curvea0[563] = _6366; + uint16_t _6367 = (uint16_t)(203); + _curvea0[564] = _6367; + uint16_t _6368 = (uint16_t)(203); + _curvea0[565] = _6368; + uint16_t _6369 = (uint16_t)(203); + _curvea0[566] = _6369; + uint16_t _6370 = (uint16_t)(203); + _curvea0[567] = _6370; + uint16_t _6371 = (uint16_t)(203); + _curvea0[568] = _6371; + uint16_t _6372 = (uint16_t)(204); + _curvea0[569] = _6372; + uint16_t _6373 = (uint16_t)(204); + _curvea0[570] = _6373; + uint16_t _6374 = (uint16_t)(204); + _curvea0[571] = _6374; + uint16_t _6375 = (uint16_t)(204); + _curvea0[572] = _6375; + uint16_t _6376 = (uint16_t)(204); + _curvea0[573] = _6376; + uint16_t _6377 = (uint16_t)(204); + _curvea0[574] = _6377; + uint16_t _6378 = (uint16_t)(205); + _curvea0[575] = _6378; + uint16_t _6379 = (uint16_t)(205); + _curvea0[576] = _6379; + uint16_t _6380 = (uint16_t)(205); + _curvea0[577] = _6380; + uint16_t _6381 = (uint16_t)(205); + _curvea0[578] = _6381; + uint16_t _6382 = (uint16_t)(205); + _curvea0[579] = _6382; + uint16_t _6383 = (uint16_t)(205); + _curvea0[580] = _6383; + uint16_t _6384 = (uint16_t)(206); + _curvea0[581] = _6384; + uint16_t _6385 = (uint16_t)(206); + _curvea0[582] = _6385; + uint16_t _6386 = (uint16_t)(206); + _curvea0[583] = _6386; + uint16_t _6387 = (uint16_t)(206); + _curvea0[584] = _6387; + uint16_t _6388 = (uint16_t)(206); + _curvea0[585] = _6388; + uint16_t _6389 = (uint16_t)(206); + _curvea0[586] = _6389; + uint16_t _6390 = (uint16_t)(207); + _curvea0[587] = _6390; + uint16_t _6391 = (uint16_t)(207); + _curvea0[588] = _6391; + uint16_t _6392 = (uint16_t)(207); + _curvea0[589] = _6392; + uint16_t _6393 = (uint16_t)(207); + _curvea0[590] = _6393; + uint16_t _6394 = (uint16_t)(207); + _curvea0[591] = _6394; + uint16_t _6395 = (uint16_t)(207); + _curvea0[592] = _6395; + uint16_t _6396 = (uint16_t)(208); + _curvea0[593] = _6396; + uint16_t _6397 = (uint16_t)(208); + _curvea0[594] = _6397; + uint16_t _6398 = (uint16_t)(208); + _curvea0[595] = _6398; + uint16_t _6399 = (uint16_t)(208); + _curvea0[596] = _6399; + uint16_t _6400 = (uint16_t)(208); + _curvea0[597] = _6400; + uint16_t _6401 = (uint16_t)(208); + _curvea0[598] = _6401; + uint16_t _6402 = (uint16_t)(209); + _curvea0[599] = _6402; + uint16_t _6403 = (uint16_t)(209); + _curvea0[600] = _6403; + uint16_t _6404 = (uint16_t)(209); + _curvea0[601] = _6404; + uint16_t _6405 = (uint16_t)(209); + _curvea0[602] = _6405; + uint16_t _6406 = (uint16_t)(209); + _curvea0[603] = _6406; + uint16_t _6407 = (uint16_t)(209); + _curvea0[604] = _6407; + uint16_t _6408 = (uint16_t)(209); + _curvea0[605] = _6408; + uint16_t _6409 = (uint16_t)(210); + _curvea0[606] = _6409; + uint16_t _6410 = (uint16_t)(210); + _curvea0[607] = _6410; + uint16_t _6411 = (uint16_t)(210); + _curvea0[608] = _6411; + uint16_t _6412 = (uint16_t)(210); + _curvea0[609] = _6412; + uint16_t _6413 = (uint16_t)(210); + _curvea0[610] = _6413; + uint16_t _6414 = (uint16_t)(210); + _curvea0[611] = _6414; + uint16_t _6415 = (uint16_t)(211); + _curvea0[612] = _6415; + uint16_t _6416 = (uint16_t)(211); + _curvea0[613] = _6416; + uint16_t _6417 = (uint16_t)(211); + _curvea0[614] = _6417; + uint16_t _6418 = (uint16_t)(211); + _curvea0[615] = _6418; + uint16_t _6419 = (uint16_t)(211); + _curvea0[616] = _6419; + uint16_t _6420 = (uint16_t)(211); + _curvea0[617] = _6420; + uint16_t _6421 = (uint16_t)(211); + _curvea0[618] = _6421; + uint16_t _6422 = (uint16_t)(212); + _curvea0[619] = _6422; + uint16_t _6423 = (uint16_t)(212); + _curvea0[620] = _6423; + uint16_t _6424 = (uint16_t)(212); + _curvea0[621] = _6424; + uint16_t _6425 = (uint16_t)(212); + _curvea0[622] = _6425; + uint16_t _6426 = (uint16_t)(212); + _curvea0[623] = _6426; + uint16_t _6427 = (uint16_t)(212); + _curvea0[624] = _6427; + uint16_t _6428 = (uint16_t)(213); + _curvea0[625] = _6428; + uint16_t _6429 = (uint16_t)(213); + _curvea0[626] = _6429; + uint16_t _6430 = (uint16_t)(213); + _curvea0[627] = _6430; + uint16_t _6431 = (uint16_t)(213); + _curvea0[628] = _6431; + uint16_t _6432 = (uint16_t)(213); + _curvea0[629] = _6432; + uint16_t _6433 = (uint16_t)(213); + _curvea0[630] = _6433; + uint16_t _6434 = (uint16_t)(213); + _curvea0[631] = _6434; + uint16_t _6435 = (uint16_t)(214); + _curvea0[632] = _6435; + uint16_t _6436 = (uint16_t)(214); + _curvea0[633] = _6436; + uint16_t _6437 = (uint16_t)(214); + _curvea0[634] = _6437; + uint16_t _6438 = (uint16_t)(214); + _curvea0[635] = _6438; + uint16_t _6439 = (uint16_t)(214); + _curvea0[636] = _6439; + uint16_t _6440 = (uint16_t)(214); + _curvea0[637] = _6440; + uint16_t _6441 = (uint16_t)(214); + _curvea0[638] = _6441; + uint16_t _6442 = (uint16_t)(215); + _curvea0[639] = _6442; + uint16_t _6443 = (uint16_t)(215); + _curvea0[640] = _6443; + uint16_t _6444 = (uint16_t)(215); + _curvea0[641] = _6444; + uint16_t _6445 = (uint16_t)(215); + _curvea0[642] = _6445; + uint16_t _6446 = (uint16_t)(215); + _curvea0[643] = _6446; + uint16_t _6447 = (uint16_t)(215); + _curvea0[644] = _6447; + uint16_t _6448 = (uint16_t)(216); + _curvea0[645] = _6448; + uint16_t _6449 = (uint16_t)(216); + _curvea0[646] = _6449; + uint16_t _6450 = (uint16_t)(216); + _curvea0[647] = _6450; + uint16_t _6451 = (uint16_t)(216); + _curvea0[648] = _6451; + uint16_t _6452 = (uint16_t)(216); + _curvea0[649] = _6452; + uint16_t _6453 = (uint16_t)(216); + _curvea0[650] = _6453; + uint16_t _6454 = (uint16_t)(216); + _curvea0[651] = _6454; + uint16_t _6455 = (uint16_t)(217); + _curvea0[652] = _6455; + uint16_t _6456 = (uint16_t)(217); + _curvea0[653] = _6456; + uint16_t _6457 = (uint16_t)(217); + _curvea0[654] = _6457; + uint16_t _6458 = (uint16_t)(217); + _curvea0[655] = _6458; + uint16_t _6459 = (uint16_t)(217); + _curvea0[656] = _6459; + uint16_t _6460 = (uint16_t)(217); + _curvea0[657] = _6460; + uint16_t _6461 = (uint16_t)(217); + _curvea0[658] = _6461; + uint16_t _6462 = (uint16_t)(218); + _curvea0[659] = _6462; + uint16_t _6463 = (uint16_t)(218); + _curvea0[660] = _6463; + uint16_t _6464 = (uint16_t)(218); + _curvea0[661] = _6464; + uint16_t _6465 = (uint16_t)(218); + _curvea0[662] = _6465; + uint16_t _6466 = (uint16_t)(218); + _curvea0[663] = _6466; + uint16_t _6467 = (uint16_t)(218); + _curvea0[664] = _6467; + uint16_t _6468 = (uint16_t)(218); + _curvea0[665] = _6468; + uint16_t _6469 = (uint16_t)(219); + _curvea0[666] = _6469; + uint16_t _6470 = (uint16_t)(219); + _curvea0[667] = _6470; + uint16_t _6471 = (uint16_t)(219); + _curvea0[668] = _6471; + uint16_t _6472 = (uint16_t)(219); + _curvea0[669] = _6472; + uint16_t _6473 = (uint16_t)(219); + _curvea0[670] = _6473; + uint16_t _6474 = (uint16_t)(219); + _curvea0[671] = _6474; + uint16_t _6475 = (uint16_t)(219); + _curvea0[672] = _6475; + uint16_t _6476 = (uint16_t)(220); + _curvea0[673] = _6476; + uint16_t _6477 = (uint16_t)(220); + _curvea0[674] = _6477; + uint16_t _6478 = (uint16_t)(220); + _curvea0[675] = _6478; + uint16_t _6479 = (uint16_t)(220); + _curvea0[676] = _6479; + uint16_t _6480 = (uint16_t)(220); + _curvea0[677] = _6480; + uint16_t _6481 = (uint16_t)(220); + _curvea0[678] = _6481; + uint16_t _6482 = (uint16_t)(220); + _curvea0[679] = _6482; + uint16_t _6483 = (uint16_t)(220); + _curvea0[680] = _6483; + uint16_t _6484 = (uint16_t)(221); + _curvea0[681] = _6484; + uint16_t _6485 = (uint16_t)(221); + _curvea0[682] = _6485; + uint16_t _6486 = (uint16_t)(221); + _curvea0[683] = _6486; + uint16_t _6487 = (uint16_t)(221); + _curvea0[684] = _6487; + uint16_t _6488 = (uint16_t)(221); + _curvea0[685] = _6488; + uint16_t _6489 = (uint16_t)(221); + _curvea0[686] = _6489; + uint16_t _6490 = (uint16_t)(221); + _curvea0[687] = _6490; + uint16_t _6491 = (uint16_t)(222); + _curvea0[688] = _6491; + uint16_t _6492 = (uint16_t)(222); + _curvea0[689] = _6492; + uint16_t _6493 = (uint16_t)(222); + _curvea0[690] = _6493; + uint16_t _6494 = (uint16_t)(222); + _curvea0[691] = _6494; + uint16_t _6495 = (uint16_t)(222); + _curvea0[692] = _6495; + uint16_t _6496 = (uint16_t)(222); + _curvea0[693] = _6496; + uint16_t _6497 = (uint16_t)(222); + _curvea0[694] = _6497; + uint16_t _6498 = (uint16_t)(223); + _curvea0[695] = _6498; + uint16_t _6499 = (uint16_t)(223); + _curvea0[696] = _6499; + uint16_t _6500 = (uint16_t)(223); + _curvea0[697] = _6500; + uint16_t _6501 = (uint16_t)(223); + _curvea0[698] = _6501; + uint16_t _6502 = (uint16_t)(223); + _curvea0[699] = _6502; + uint16_t _6503 = (uint16_t)(223); + _curvea0[700] = _6503; + uint16_t _6504 = (uint16_t)(223); + _curvea0[701] = _6504; + uint16_t _6505 = (uint16_t)(223); + _curvea0[702] = _6505; + uint16_t _6506 = (uint16_t)(224); + _curvea0[703] = _6506; + uint16_t _6507 = (uint16_t)(224); + _curvea0[704] = _6507; + uint16_t _6508 = (uint16_t)(224); + _curvea0[705] = _6508; + uint16_t _6509 = (uint16_t)(224); + _curvea0[706] = _6509; + uint16_t _6510 = (uint16_t)(224); + _curvea0[707] = _6510; + uint16_t _6511 = (uint16_t)(224); + _curvea0[708] = _6511; + uint16_t _6512 = (uint16_t)(224); + _curvea0[709] = _6512; + uint16_t _6513 = (uint16_t)(224); + _curvea0[710] = _6513; + uint16_t _6514 = (uint16_t)(225); + _curvea0[711] = _6514; + uint16_t _6515 = (uint16_t)(225); + _curvea0[712] = _6515; + uint16_t _6516 = (uint16_t)(225); + _curvea0[713] = _6516; + uint16_t _6517 = (uint16_t)(225); + _curvea0[714] = _6517; + uint16_t _6518 = (uint16_t)(225); + _curvea0[715] = _6518; + uint16_t _6519 = (uint16_t)(225); + _curvea0[716] = _6519; + uint16_t _6520 = (uint16_t)(225); + _curvea0[717] = _6520; + uint16_t _6521 = (uint16_t)(226); + _curvea0[718] = _6521; + uint16_t _6522 = (uint16_t)(226); + _curvea0[719] = _6522; + uint16_t _6523 = (uint16_t)(226); + _curvea0[720] = _6523; + uint16_t _6524 = (uint16_t)(226); + _curvea0[721] = _6524; + uint16_t _6525 = (uint16_t)(226); + _curvea0[722] = _6525; + uint16_t _6526 = (uint16_t)(226); + _curvea0[723] = _6526; + uint16_t _6527 = (uint16_t)(226); + _curvea0[724] = _6527; + uint16_t _6528 = (uint16_t)(226); + _curvea0[725] = _6528; + uint16_t _6529 = (uint16_t)(227); + _curvea0[726] = _6529; + uint16_t _6530 = (uint16_t)(227); + _curvea0[727] = _6530; + uint16_t _6531 = (uint16_t)(227); + _curvea0[728] = _6531; + uint16_t _6532 = (uint16_t)(227); + _curvea0[729] = _6532; + uint16_t _6533 = (uint16_t)(227); + _curvea0[730] = _6533; + uint16_t _6534 = (uint16_t)(227); + _curvea0[731] = _6534; + uint16_t _6535 = (uint16_t)(227); + _curvea0[732] = _6535; + uint16_t _6536 = (uint16_t)(227); + _curvea0[733] = _6536; + uint16_t _6537 = (uint16_t)(228); + _curvea0[734] = _6537; + uint16_t _6538 = (uint16_t)(228); + _curvea0[735] = _6538; + uint16_t _6539 = (uint16_t)(228); + _curvea0[736] = _6539; + uint16_t _6540 = (uint16_t)(228); + _curvea0[737] = _6540; + uint16_t _6541 = (uint16_t)(228); + _curvea0[738] = _6541; + uint16_t _6542 = (uint16_t)(228); + _curvea0[739] = _6542; + uint16_t _6543 = (uint16_t)(228); + _curvea0[740] = _6543; + uint16_t _6544 = (uint16_t)(228); + _curvea0[741] = _6544; + uint16_t _6545 = (uint16_t)(228); + _curvea0[742] = _6545; + uint16_t _6546 = (uint16_t)(229); + _curvea0[743] = _6546; + uint16_t _6547 = (uint16_t)(229); + _curvea0[744] = _6547; + uint16_t _6548 = (uint16_t)(229); + _curvea0[745] = _6548; + uint16_t _6549 = (uint16_t)(229); + _curvea0[746] = _6549; + uint16_t _6550 = (uint16_t)(229); + _curvea0[747] = _6550; + uint16_t _6551 = (uint16_t)(229); + _curvea0[748] = _6551; + uint16_t _6552 = (uint16_t)(229); + _curvea0[749] = _6552; + uint16_t _6553 = (uint16_t)(229); + _curvea0[750] = _6553; + uint16_t _6554 = (uint16_t)(230); + _curvea0[751] = _6554; + uint16_t _6555 = (uint16_t)(230); + _curvea0[752] = _6555; + uint16_t _6556 = (uint16_t)(230); + _curvea0[753] = _6556; + uint16_t _6557 = (uint16_t)(230); + _curvea0[754] = _6557; + uint16_t _6558 = (uint16_t)(230); + _curvea0[755] = _6558; + uint16_t _6559 = (uint16_t)(230); + _curvea0[756] = _6559; + uint16_t _6560 = (uint16_t)(230); + _curvea0[757] = _6560; + uint16_t _6561 = (uint16_t)(230); + _curvea0[758] = _6561; + uint16_t _6562 = (uint16_t)(231); + _curvea0[759] = _6562; + uint16_t _6563 = (uint16_t)(231); + _curvea0[760] = _6563; + uint16_t _6564 = (uint16_t)(231); + _curvea0[761] = _6564; + uint16_t _6565 = (uint16_t)(231); + _curvea0[762] = _6565; + uint16_t _6566 = (uint16_t)(231); + _curvea0[763] = _6566; + uint16_t _6567 = (uint16_t)(231); + _curvea0[764] = _6567; + uint16_t _6568 = (uint16_t)(231); + _curvea0[765] = _6568; + uint16_t _6569 = (uint16_t)(231); + _curvea0[766] = _6569; + uint16_t _6570 = (uint16_t)(231); + _curvea0[767] = _6570; + uint16_t _6571 = (uint16_t)(232); + _curvea0[768] = _6571; + uint16_t _6572 = (uint16_t)(232); + _curvea0[769] = _6572; + uint16_t _6573 = (uint16_t)(232); + _curvea0[770] = _6573; + uint16_t _6574 = (uint16_t)(232); + _curvea0[771] = _6574; + uint16_t _6575 = (uint16_t)(232); + _curvea0[772] = _6575; + uint16_t _6576 = (uint16_t)(232); + _curvea0[773] = _6576; + uint16_t _6577 = (uint16_t)(232); + _curvea0[774] = _6577; + uint16_t _6578 = (uint16_t)(232); + _curvea0[775] = _6578; + uint16_t _6579 = (uint16_t)(233); + _curvea0[776] = _6579; + uint16_t _6580 = (uint16_t)(233); + _curvea0[777] = _6580; + uint16_t _6581 = (uint16_t)(233); + _curvea0[778] = _6581; + uint16_t _6582 = (uint16_t)(233); + _curvea0[779] = _6582; + uint16_t _6583 = (uint16_t)(233); + _curvea0[780] = _6583; + uint16_t _6584 = (uint16_t)(233); + _curvea0[781] = _6584; + uint16_t _6585 = (uint16_t)(233); + _curvea0[782] = _6585; + uint16_t _6586 = (uint16_t)(233); + _curvea0[783] = _6586; + uint16_t _6587 = (uint16_t)(233); + _curvea0[784] = _6587; + uint16_t _6588 = (uint16_t)(234); + _curvea0[785] = _6588; + uint16_t _6589 = (uint16_t)(234); + _curvea0[786] = _6589; + uint16_t _6590 = (uint16_t)(234); + _curvea0[787] = _6590; + uint16_t _6591 = (uint16_t)(234); + _curvea0[788] = _6591; + uint16_t _6592 = (uint16_t)(234); + _curvea0[789] = _6592; + uint16_t _6593 = (uint16_t)(234); + _curvea0[790] = _6593; + uint16_t _6594 = (uint16_t)(234); + _curvea0[791] = _6594; + uint16_t _6595 = (uint16_t)(234); + _curvea0[792] = _6595; + uint16_t _6596 = (uint16_t)(234); + _curvea0[793] = _6596; + uint16_t _6597 = (uint16_t)(235); + _curvea0[794] = _6597; + uint16_t _6598 = (uint16_t)(235); + _curvea0[795] = _6598; + uint16_t _6599 = (uint16_t)(235); + _curvea0[796] = _6599; + uint16_t _6600 = (uint16_t)(235); + _curvea0[797] = _6600; + uint16_t _6601 = (uint16_t)(235); + _curvea0[798] = _6601; + uint16_t _6602 = (uint16_t)(235); + _curvea0[799] = _6602; + uint16_t _6603 = (uint16_t)(235); + _curvea0[800] = _6603; + uint16_t _6604 = (uint16_t)(235); + _curvea0[801] = _6604; + uint16_t _6605 = (uint16_t)(235); + _curvea0[802] = _6605; + uint16_t _6606 = (uint16_t)(236); + _curvea0[803] = _6606; + uint16_t _6607 = (uint16_t)(236); + _curvea0[804] = _6607; + uint16_t _6608 = (uint16_t)(236); + _curvea0[805] = _6608; + uint16_t _6609 = (uint16_t)(236); + _curvea0[806] = _6609; + uint16_t _6610 = (uint16_t)(236); + _curvea0[807] = _6610; + uint16_t _6611 = (uint16_t)(236); + _curvea0[808] = _6611; + uint16_t _6612 = (uint16_t)(236); + _curvea0[809] = _6612; + uint16_t _6613 = (uint16_t)(236); + _curvea0[810] = _6613; + uint16_t _6614 = (uint16_t)(236); + _curvea0[811] = _6614; + uint16_t _6615 = (uint16_t)(237); + _curvea0[812] = _6615; + uint16_t _6616 = (uint16_t)(237); + _curvea0[813] = _6616; + uint16_t _6617 = (uint16_t)(237); + _curvea0[814] = _6617; + uint16_t _6618 = (uint16_t)(237); + _curvea0[815] = _6618; + uint16_t _6619 = (uint16_t)(237); + _curvea0[816] = _6619; + uint16_t _6620 = (uint16_t)(237); + _curvea0[817] = _6620; + uint16_t _6621 = (uint16_t)(237); + _curvea0[818] = _6621; + uint16_t _6622 = (uint16_t)(237); + _curvea0[819] = _6622; + uint16_t _6623 = (uint16_t)(237); + _curvea0[820] = _6623; + uint16_t _6624 = (uint16_t)(237); + _curvea0[821] = _6624; + uint16_t _6625 = (uint16_t)(238); + _curvea0[822] = _6625; + uint16_t _6626 = (uint16_t)(238); + _curvea0[823] = _6626; + uint16_t _6627 = (uint16_t)(238); + _curvea0[824] = _6627; + uint16_t _6628 = (uint16_t)(238); + _curvea0[825] = _6628; + uint16_t _6629 = (uint16_t)(238); + _curvea0[826] = _6629; + uint16_t _6630 = (uint16_t)(238); + _curvea0[827] = _6630; + uint16_t _6631 = (uint16_t)(238); + _curvea0[828] = _6631; + uint16_t _6632 = (uint16_t)(238); + _curvea0[829] = _6632; + uint16_t _6633 = (uint16_t)(238); + _curvea0[830] = _6633; + uint16_t _6634 = (uint16_t)(239); + _curvea0[831] = _6634; + uint16_t _6635 = (uint16_t)(239); + _curvea0[832] = _6635; + uint16_t _6636 = (uint16_t)(239); + _curvea0[833] = _6636; + uint16_t _6637 = (uint16_t)(239); + _curvea0[834] = _6637; + uint16_t _6638 = (uint16_t)(239); + _curvea0[835] = _6638; + uint16_t _6639 = (uint16_t)(239); + _curvea0[836] = _6639; + uint16_t _6640 = (uint16_t)(239); + _curvea0[837] = _6640; + uint16_t _6641 = (uint16_t)(239); + _curvea0[838] = _6641; + uint16_t _6642 = (uint16_t)(239); + _curvea0[839] = _6642; + uint16_t _6643 = (uint16_t)(239); + _curvea0[840] = _6643; + uint16_t _6644 = (uint16_t)(240); + _curvea0[841] = _6644; + uint16_t _6645 = (uint16_t)(240); + _curvea0[842] = _6645; + uint16_t _6646 = (uint16_t)(240); + _curvea0[843] = _6646; + uint16_t _6647 = (uint16_t)(240); + _curvea0[844] = _6647; + uint16_t _6648 = (uint16_t)(240); + _curvea0[845] = _6648; + uint16_t _6649 = (uint16_t)(240); + _curvea0[846] = _6649; + uint16_t _6650 = (uint16_t)(240); + _curvea0[847] = _6650; + uint16_t _6651 = (uint16_t)(240); + _curvea0[848] = _6651; + uint16_t _6652 = (uint16_t)(240); + _curvea0[849] = _6652; + uint16_t _6653 = (uint16_t)(240); + _curvea0[850] = _6653; + uint16_t _6654 = (uint16_t)(241); + _curvea0[851] = _6654; + uint16_t _6655 = (uint16_t)(241); + _curvea0[852] = _6655; + uint16_t _6656 = (uint16_t)(241); + _curvea0[853] = _6656; + uint16_t _6657 = (uint16_t)(241); + _curvea0[854] = _6657; + uint16_t _6658 = (uint16_t)(241); + _curvea0[855] = _6658; + uint16_t _6659 = (uint16_t)(241); + _curvea0[856] = _6659; + uint16_t _6660 = (uint16_t)(241); + _curvea0[857] = _6660; + uint16_t _6661 = (uint16_t)(241); + _curvea0[858] = _6661; + uint16_t _6662 = (uint16_t)(241); + _curvea0[859] = _6662; + uint16_t _6663 = (uint16_t)(241); + _curvea0[860] = _6663; + uint16_t _6664 = (uint16_t)(242); + _curvea0[861] = _6664; + uint16_t _6665 = (uint16_t)(242); + _curvea0[862] = _6665; + uint16_t _6666 = (uint16_t)(242); + _curvea0[863] = _6666; + uint16_t _6667 = (uint16_t)(242); + _curvea0[864] = _6667; + uint16_t _6668 = (uint16_t)(242); + _curvea0[865] = _6668; + uint16_t _6669 = (uint16_t)(242); + _curvea0[866] = _6669; + uint16_t _6670 = (uint16_t)(242); + _curvea0[867] = _6670; + uint16_t _6671 = (uint16_t)(242); + _curvea0[868] = _6671; + uint16_t _6672 = (uint16_t)(242); + _curvea0[869] = _6672; + uint16_t _6673 = (uint16_t)(242); + _curvea0[870] = _6673; + uint16_t _6674 = (uint16_t)(243); + _curvea0[871] = _6674; + uint16_t _6675 = (uint16_t)(243); + _curvea0[872] = _6675; + uint16_t _6676 = (uint16_t)(243); + _curvea0[873] = _6676; + uint16_t _6677 = (uint16_t)(243); + _curvea0[874] = _6677; + uint16_t _6678 = (uint16_t)(243); + _curvea0[875] = _6678; + uint16_t _6679 = (uint16_t)(243); + _curvea0[876] = _6679; + uint16_t _6680 = (uint16_t)(243); + _curvea0[877] = _6680; + uint16_t _6681 = (uint16_t)(243); + _curvea0[878] = _6681; + uint16_t _6682 = (uint16_t)(243); + _curvea0[879] = _6682; + uint16_t _6683 = (uint16_t)(243); + _curvea0[880] = _6683; + uint16_t _6684 = (uint16_t)(244); + _curvea0[881] = _6684; + uint16_t _6685 = (uint16_t)(244); + _curvea0[882] = _6685; + uint16_t _6686 = (uint16_t)(244); + _curvea0[883] = _6686; + uint16_t _6687 = (uint16_t)(244); + _curvea0[884] = _6687; + uint16_t _6688 = (uint16_t)(244); + _curvea0[885] = _6688; + uint16_t _6689 = (uint16_t)(244); + _curvea0[886] = _6689; + uint16_t _6690 = (uint16_t)(244); + _curvea0[887] = _6690; + uint16_t _6691 = (uint16_t)(244); + _curvea0[888] = _6691; + uint16_t _6692 = (uint16_t)(244); + _curvea0[889] = _6692; + uint16_t _6693 = (uint16_t)(244); + _curvea0[890] = _6693; + uint16_t _6694 = (uint16_t)(244); + _curvea0[891] = _6694; + uint16_t _6695 = (uint16_t)(245); + _curvea0[892] = _6695; + uint16_t _6696 = (uint16_t)(245); + _curvea0[893] = _6696; + uint16_t _6697 = (uint16_t)(245); + _curvea0[894] = _6697; + uint16_t _6698 = (uint16_t)(245); + _curvea0[895] = _6698; + uint16_t _6699 = (uint16_t)(245); + _curvea0[896] = _6699; + uint16_t _6700 = (uint16_t)(245); + _curvea0[897] = _6700; + uint16_t _6701 = (uint16_t)(245); + _curvea0[898] = _6701; + uint16_t _6702 = (uint16_t)(245); + _curvea0[899] = _6702; + uint16_t _6703 = (uint16_t)(245); + _curvea0[900] = _6703; + uint16_t _6704 = (uint16_t)(245); + _curvea0[901] = _6704; + uint16_t _6705 = (uint16_t)(245); + _curvea0[902] = _6705; + uint16_t _6706 = (uint16_t)(246); + _curvea0[903] = _6706; + uint16_t _6707 = (uint16_t)(246); + _curvea0[904] = _6707; + uint16_t _6708 = (uint16_t)(246); + _curvea0[905] = _6708; + uint16_t _6709 = (uint16_t)(246); + _curvea0[906] = _6709; + uint16_t _6710 = (uint16_t)(246); + _curvea0[907] = _6710; + uint16_t _6711 = (uint16_t)(246); + _curvea0[908] = _6711; + uint16_t _6712 = (uint16_t)(246); + _curvea0[909] = _6712; + uint16_t _6713 = (uint16_t)(246); + _curvea0[910] = _6713; + uint16_t _6714 = (uint16_t)(246); + _curvea0[911] = _6714; + uint16_t _6715 = (uint16_t)(246); + _curvea0[912] = _6715; + uint16_t _6716 = (uint16_t)(246); + _curvea0[913] = _6716; + uint16_t _6717 = (uint16_t)(247); + _curvea0[914] = _6717; + uint16_t _6718 = (uint16_t)(247); + _curvea0[915] = _6718; + uint16_t _6719 = (uint16_t)(247); + _curvea0[916] = _6719; + uint16_t _6720 = (uint16_t)(247); + _curvea0[917] = _6720; + uint16_t _6721 = (uint16_t)(247); + _curvea0[918] = _6721; + uint16_t _6722 = (uint16_t)(247); + _curvea0[919] = _6722; + uint16_t _6723 = (uint16_t)(247); + _curvea0[920] = _6723; + uint16_t _6724 = (uint16_t)(247); + _curvea0[921] = _6724; + uint16_t _6725 = (uint16_t)(247); + _curvea0[922] = _6725; + uint16_t _6726 = (uint16_t)(247); + _curvea0[923] = _6726; + uint16_t _6727 = (uint16_t)(247); + _curvea0[924] = _6727; + uint16_t _6728 = (uint16_t)(248); + _curvea0[925] = _6728; + uint16_t _6729 = (uint16_t)(248); + _curvea0[926] = _6729; + uint16_t _6730 = (uint16_t)(248); + _curvea0[927] = _6730; + uint16_t _6731 = (uint16_t)(248); + _curvea0[928] = _6731; + uint16_t _6732 = (uint16_t)(248); + _curvea0[929] = _6732; + uint16_t _6733 = (uint16_t)(248); + _curvea0[930] = _6733; + uint16_t _6734 = (uint16_t)(248); + _curvea0[931] = _6734; + uint16_t _6735 = (uint16_t)(248); + _curvea0[932] = _6735; + uint16_t _6736 = (uint16_t)(248); + _curvea0[933] = _6736; + uint16_t _6737 = (uint16_t)(248); + _curvea0[934] = _6737; + uint16_t _6738 = (uint16_t)(248); + _curvea0[935] = _6738; + uint16_t _6739 = (uint16_t)(249); + _curvea0[936] = _6739; + uint16_t _6740 = (uint16_t)(249); + _curvea0[937] = _6740; + uint16_t _6741 = (uint16_t)(249); + _curvea0[938] = _6741; + uint16_t _6742 = (uint16_t)(249); + _curvea0[939] = _6742; + uint16_t _6743 = (uint16_t)(249); + _curvea0[940] = _6743; + uint16_t _6744 = (uint16_t)(249); + _curvea0[941] = _6744; + uint16_t _6745 = (uint16_t)(249); + _curvea0[942] = _6745; + uint16_t _6746 = (uint16_t)(249); + _curvea0[943] = _6746; + uint16_t _6747 = (uint16_t)(249); + _curvea0[944] = _6747; + uint16_t _6748 = (uint16_t)(249); + _curvea0[945] = _6748; + uint16_t _6749 = (uint16_t)(249); + _curvea0[946] = _6749; + uint16_t _6750 = (uint16_t)(249); + _curvea0[947] = _6750; + uint16_t _6751 = (uint16_t)(250); + _curvea0[948] = _6751; + uint16_t _6752 = (uint16_t)(250); + _curvea0[949] = _6752; + uint16_t _6753 = (uint16_t)(250); + _curvea0[950] = _6753; + uint16_t _6754 = (uint16_t)(250); + _curvea0[951] = _6754; + uint16_t _6755 = (uint16_t)(250); + _curvea0[952] = _6755; + uint16_t _6756 = (uint16_t)(250); + _curvea0[953] = _6756; + uint16_t _6757 = (uint16_t)(250); + _curvea0[954] = _6757; + uint16_t _6758 = (uint16_t)(250); + _curvea0[955] = _6758; + uint16_t _6759 = (uint16_t)(250); + _curvea0[956] = _6759; + uint16_t _6760 = (uint16_t)(250); + _curvea0[957] = _6760; + uint16_t _6761 = (uint16_t)(250); + _curvea0[958] = _6761; + uint16_t _6762 = (uint16_t)(250); + _curvea0[959] = _6762; + uint16_t _6763 = (uint16_t)(251); + _curvea0[960] = _6763; + uint16_t _6764 = (uint16_t)(251); + _curvea0[961] = _6764; + uint16_t _6765 = (uint16_t)(251); + _curvea0[962] = _6765; + uint16_t _6766 = (uint16_t)(251); + _curvea0[963] = _6766; + uint16_t _6767 = (uint16_t)(251); + _curvea0[964] = _6767; + uint16_t _6768 = (uint16_t)(251); + _curvea0[965] = _6768; + uint16_t _6769 = (uint16_t)(251); + _curvea0[966] = _6769; + uint16_t _6770 = (uint16_t)(251); + _curvea0[967] = _6770; + uint16_t _6771 = (uint16_t)(251); + _curvea0[968] = _6771; + uint16_t _6772 = (uint16_t)(251); + _curvea0[969] = _6772; + uint16_t _6773 = (uint16_t)(251); + _curvea0[970] = _6773; + uint16_t _6774 = (uint16_t)(251); + _curvea0[971] = _6774; + uint16_t _6775 = (uint16_t)(252); + _curvea0[972] = _6775; + uint16_t _6776 = (uint16_t)(252); + _curvea0[973] = _6776; + uint16_t _6777 = (uint16_t)(252); + _curvea0[974] = _6777; + uint16_t _6778 = (uint16_t)(252); + _curvea0[975] = _6778; + uint16_t _6779 = (uint16_t)(252); + _curvea0[976] = _6779; + uint16_t _6780 = (uint16_t)(252); + _curvea0[977] = _6780; + uint16_t _6781 = (uint16_t)(252); + _curvea0[978] = _6781; + uint16_t _6782 = (uint16_t)(252); + _curvea0[979] = _6782; + uint16_t _6783 = (uint16_t)(252); + _curvea0[980] = _6783; + uint16_t _6784 = (uint16_t)(252); + _curvea0[981] = _6784; + uint16_t _6785 = (uint16_t)(252); + _curvea0[982] = _6785; + uint16_t _6786 = (uint16_t)(252); + _curvea0[983] = _6786; + uint16_t _6787 = (uint16_t)(252); + _curvea0[984] = _6787; + uint16_t _6788 = (uint16_t)(253); + _curvea0[985] = _6788; + uint16_t _6789 = (uint16_t)(253); + _curvea0[986] = _6789; + uint16_t _6790 = (uint16_t)(253); + _curvea0[987] = _6790; + uint16_t _6791 = (uint16_t)(253); + _curvea0[988] = _6791; + uint16_t _6792 = (uint16_t)(253); + _curvea0[989] = _6792; + uint16_t _6793 = (uint16_t)(253); + _curvea0[990] = _6793; + uint16_t _6794 = (uint16_t)(253); + _curvea0[991] = _6794; + uint16_t _6795 = (uint16_t)(253); + _curvea0[992] = _6795; + uint16_t _6796 = (uint16_t)(253); + _curvea0[993] = _6796; + uint16_t _6797 = (uint16_t)(253); + _curvea0[994] = _6797; + uint16_t _6798 = (uint16_t)(253); + _curvea0[995] = _6798; + uint16_t _6799 = (uint16_t)(253); + _curvea0[996] = _6799; + uint16_t _6800 = (uint16_t)(253); + _curvea0[997] = _6800; + uint16_t _6801 = (uint16_t)(254); + _curvea0[998] = _6801; + uint16_t _6802 = (uint16_t)(254); + _curvea0[999] = _6802; + uint16_t _6803 = (uint16_t)(254); + _curvea0[1000] = _6803; + uint16_t _6804 = (uint16_t)(254); + _curvea0[1001] = _6804; + uint16_t _6805 = (uint16_t)(254); + _curvea0[1002] = _6805; + uint16_t _6806 = (uint16_t)(254); + _curvea0[1003] = _6806; + uint16_t _6807 = (uint16_t)(254); + _curvea0[1004] = _6807; + uint16_t _6808 = (uint16_t)(254); + _curvea0[1005] = _6808; + uint16_t _6809 = (uint16_t)(254); + _curvea0[1006] = _6809; + uint16_t _6810 = (uint16_t)(254); + _curvea0[1007] = _6810; + uint16_t _6811 = (uint16_t)(254); + _curvea0[1008] = _6811; + uint16_t _6812 = (uint16_t)(254); + _curvea0[1009] = _6812; + uint16_t _6813 = (uint16_t)(254); + _curvea0[1010] = _6813; + uint16_t _6814 = (uint16_t)(255); + _curvea0[1011] = _6814; + uint16_t _6815 = (uint16_t)(255); + _curvea0[1012] = _6815; + uint16_t _6816 = (uint16_t)(255); + _curvea0[1013] = _6816; + uint16_t _6817 = (uint16_t)(255); + _curvea0[1014] = _6817; + uint16_t _6818 = (uint16_t)(255); + _curvea0[1015] = _6818; + uint16_t _6819 = (uint16_t)(255); + _curvea0[1016] = _6819; + uint16_t _6820 = (uint16_t)(255); + _curvea0[1017] = _6820; + uint16_t _6821 = (uint16_t)(255); + _curvea0[1018] = _6821; + uint16_t _6822 = (uint16_t)(255); + _curvea0[1019] = _6822; + uint16_t _6823 = (uint16_t)(255); + _curvea0[1020] = _6823; + uint16_t _6824 = (uint16_t)(255); + _curvea0[1021] = _6824; + uint16_t _6825 = (uint16_t)(255); + _curvea0[1022] = _6825; + uint16_t _6826 = (uint16_t)(255); + _curvea0[1023] = _6826; + + int16_t _6827 = (int16_t)(1023); + int16_t _6828 = min(_corrected_stencil_4, _6827); + int16_t _6829 = (int16_t)(0); + int16_t _6830 = max(_6828, _6829); + uint16_t _6831 = (uint16_t)(_6830); + int32_t _6832 = (int32_t)(_6831); + uint16_t _6833 = ((const uint16_t *)_curvea0)[_6832]; + return _6833; +} + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_4(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_5 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _6851 = (uint16_t)(0); + _curvea0[0] = _6851; + uint16_t _6852 = (uint16_t)(4); + _curvea0[1] = _6852; + uint16_t _6853 = (uint16_t)(7); + _curvea0[2] = _6853; + uint16_t _6854 = (uint16_t)(8); + _curvea0[3] = _6854; + uint16_t _6855 = (uint16_t)(10); + _curvea0[4] = _6855; + uint16_t _6856 = (uint16_t)(11); + _curvea0[5] = _6856; + uint16_t _6857 = (uint16_t)(12); + _curvea0[6] = _6857; + uint16_t _6858 = (uint16_t)(13); + _curvea0[7] = _6858; + uint16_t _6859 = (uint16_t)(14); + _curvea0[8] = _6859; + uint16_t _6860 = (uint16_t)(15); + _curvea0[9] = _6860; + uint16_t _6861 = (uint16_t)(16); + _curvea0[10] = _6861; + uint16_t _6862 = (uint16_t)(17); + _curvea0[11] = _6862; + uint16_t _6863 = (uint16_t)(18); + _curvea0[12] = _6863; + uint16_t _6864 = (uint16_t)(19); + _curvea0[13] = _6864; + uint16_t _6865 = (uint16_t)(20); + _curvea0[14] = _6865; + uint16_t _6866 = (uint16_t)(21); + _curvea0[15] = _6866; + uint16_t _6867 = (uint16_t)(22); + _curvea0[16] = _6867; + uint16_t _6868 = (uint16_t)(22); + _curvea0[17] = _6868; + uint16_t _6869 = (uint16_t)(23); + _curvea0[18] = _6869; + uint16_t _6870 = (uint16_t)(24); + _curvea0[19] = _6870; + uint16_t _6871 = (uint16_t)(25); + _curvea0[20] = _6871; + uint16_t _6872 = (uint16_t)(25); + _curvea0[21] = _6872; + uint16_t _6873 = (uint16_t)(26); + _curvea0[22] = _6873; + uint16_t _6874 = (uint16_t)(27); + _curvea0[23] = _6874; + uint16_t _6875 = (uint16_t)(27); + _curvea0[24] = _6875; + uint16_t _6876 = (uint16_t)(28); + _curvea0[25] = _6876; + uint16_t _6877 = (uint16_t)(29); + _curvea0[26] = _6877; + uint16_t _6878 = (uint16_t)(29); + _curvea0[27] = _6878; + uint16_t _6879 = (uint16_t)(30); + _curvea0[28] = _6879; + uint16_t _6880 = (uint16_t)(31); + _curvea0[29] = _6880; + uint16_t _6881 = (uint16_t)(31); + _curvea0[30] = _6881; + uint16_t _6882 = (uint16_t)(32); + _curvea0[31] = _6882; + uint16_t _6883 = (uint16_t)(33); + _curvea0[32] = _6883; + uint16_t _6884 = (uint16_t)(33); + _curvea0[33] = _6884; + uint16_t _6885 = (uint16_t)(34); + _curvea0[34] = _6885; + uint16_t _6886 = (uint16_t)(34); + _curvea0[35] = _6886; + uint16_t _6887 = (uint16_t)(35); + _curvea0[36] = _6887; + uint16_t _6888 = (uint16_t)(36); + _curvea0[37] = _6888; + uint16_t _6889 = (uint16_t)(36); + _curvea0[38] = _6889; + uint16_t _6890 = (uint16_t)(37); + _curvea0[39] = _6890; + uint16_t _6891 = (uint16_t)(37); + _curvea0[40] = _6891; + uint16_t _6892 = (uint16_t)(38); + _curvea0[41] = _6892; + uint16_t _6893 = (uint16_t)(39); + _curvea0[42] = _6893; + uint16_t _6894 = (uint16_t)(39); + _curvea0[43] = _6894; + uint16_t _6895 = (uint16_t)(40); + _curvea0[44] = _6895; + uint16_t _6896 = (uint16_t)(40); + _curvea0[45] = _6896; + uint16_t _6897 = (uint16_t)(41); + _curvea0[46] = _6897; + uint16_t _6898 = (uint16_t)(41); + _curvea0[47] = _6898; + uint16_t _6899 = (uint16_t)(42); + _curvea0[48] = _6899; + uint16_t _6900 = (uint16_t)(42); + _curvea0[49] = _6900; + uint16_t _6901 = (uint16_t)(43); + _curvea0[50] = _6901; + uint16_t _6902 = (uint16_t)(44); + _curvea0[51] = _6902; + uint16_t _6903 = (uint16_t)(44); + _curvea0[52] = _6903; + uint16_t _6904 = (uint16_t)(45); + _curvea0[53] = _6904; + uint16_t _6905 = (uint16_t)(45); + _curvea0[54] = _6905; + uint16_t _6906 = (uint16_t)(46); + _curvea0[55] = _6906; + uint16_t _6907 = (uint16_t)(46); + _curvea0[56] = _6907; + uint16_t _6908 = (uint16_t)(47); + _curvea0[57] = _6908; + uint16_t _6909 = (uint16_t)(47); + _curvea0[58] = _6909; + uint16_t _6910 = (uint16_t)(48); + _curvea0[59] = _6910; + uint16_t _6911 = (uint16_t)(48); + _curvea0[60] = _6911; + uint16_t _6912 = (uint16_t)(49); + _curvea0[61] = _6912; + uint16_t _6913 = (uint16_t)(49); + _curvea0[62] = _6913; + uint16_t _6914 = (uint16_t)(50); + _curvea0[63] = _6914; + uint16_t _6915 = (uint16_t)(50); + _curvea0[64] = _6915; + uint16_t _6916 = (uint16_t)(51); + _curvea0[65] = _6916; + uint16_t _6917 = (uint16_t)(51); + _curvea0[66] = _6917; + uint16_t _6918 = (uint16_t)(52); + _curvea0[67] = _6918; + uint16_t _6919 = (uint16_t)(52); + _curvea0[68] = _6919; + uint16_t _6920 = (uint16_t)(53); + _curvea0[69] = _6920; + uint16_t _6921 = (uint16_t)(53); + _curvea0[70] = _6921; + uint16_t _6922 = (uint16_t)(54); + _curvea0[71] = _6922; + uint16_t _6923 = (uint16_t)(54); + _curvea0[72] = _6923; + uint16_t _6924 = (uint16_t)(55); + _curvea0[73] = _6924; + uint16_t _6925 = (uint16_t)(55); + _curvea0[74] = _6925; + uint16_t _6926 = (uint16_t)(56); + _curvea0[75] = _6926; + uint16_t _6927 = (uint16_t)(56); + _curvea0[76] = _6927; + uint16_t _6928 = (uint16_t)(57); + _curvea0[77] = _6928; + uint16_t _6929 = (uint16_t)(57); + _curvea0[78] = _6929; + uint16_t _6930 = (uint16_t)(58); + _curvea0[79] = _6930; + uint16_t _6931 = (uint16_t)(58); + _curvea0[80] = _6931; + uint16_t _6932 = (uint16_t)(58); + _curvea0[81] = _6932; + uint16_t _6933 = (uint16_t)(59); + _curvea0[82] = _6933; + uint16_t _6934 = (uint16_t)(59); + _curvea0[83] = _6934; + uint16_t _6935 = (uint16_t)(60); + _curvea0[84] = _6935; + uint16_t _6936 = (uint16_t)(60); + _curvea0[85] = _6936; + uint16_t _6937 = (uint16_t)(61); + _curvea0[86] = _6937; + uint16_t _6938 = (uint16_t)(61); + _curvea0[87] = _6938; + uint16_t _6939 = (uint16_t)(62); + _curvea0[88] = _6939; + uint16_t _6940 = (uint16_t)(62); + _curvea0[89] = _6940; + uint16_t _6941 = (uint16_t)(63); + _curvea0[90] = _6941; + uint16_t _6942 = (uint16_t)(63); + _curvea0[91] = _6942; + uint16_t _6943 = (uint16_t)(64); + _curvea0[92] = _6943; + uint16_t _6944 = (uint16_t)(64); + _curvea0[93] = _6944; + uint16_t _6945 = (uint16_t)(64); + _curvea0[94] = _6945; + uint16_t _6946 = (uint16_t)(65); + _curvea0[95] = _6946; + uint16_t _6947 = (uint16_t)(65); + _curvea0[96] = _6947; + uint16_t _6948 = (uint16_t)(66); + _curvea0[97] = _6948; + uint16_t _6949 = (uint16_t)(66); + _curvea0[98] = _6949; + uint16_t _6950 = (uint16_t)(67); + _curvea0[99] = _6950; + uint16_t _6951 = (uint16_t)(67); + _curvea0[100] = _6951; + uint16_t _6952 = (uint16_t)(68); + _curvea0[101] = _6952; + uint16_t _6953 = (uint16_t)(68); + _curvea0[102] = _6953; + uint16_t _6954 = (uint16_t)(68); + _curvea0[103] = _6954; + uint16_t _6955 = (uint16_t)(69); + _curvea0[104] = _6955; + uint16_t _6956 = (uint16_t)(69); + _curvea0[105] = _6956; + uint16_t _6957 = (uint16_t)(70); + _curvea0[106] = _6957; + uint16_t _6958 = (uint16_t)(70); + _curvea0[107] = _6958; + uint16_t _6959 = (uint16_t)(71); + _curvea0[108] = _6959; + uint16_t _6960 = (uint16_t)(71); + _curvea0[109] = _6960; + uint16_t _6961 = (uint16_t)(71); + _curvea0[110] = _6961; + uint16_t _6962 = (uint16_t)(72); + _curvea0[111] = _6962; + uint16_t _6963 = (uint16_t)(72); + _curvea0[112] = _6963; + uint16_t _6964 = (uint16_t)(73); + _curvea0[113] = _6964; + uint16_t _6965 = (uint16_t)(73); + _curvea0[114] = _6965; + uint16_t _6966 = (uint16_t)(74); + _curvea0[115] = _6966; + uint16_t _6967 = (uint16_t)(74); + _curvea0[116] = _6967; + uint16_t _6968 = (uint16_t)(74); + _curvea0[117] = _6968; + uint16_t _6969 = (uint16_t)(75); + _curvea0[118] = _6969; + uint16_t _6970 = (uint16_t)(75); + _curvea0[119] = _6970; + uint16_t _6971 = (uint16_t)(76); + _curvea0[120] = _6971; + uint16_t _6972 = (uint16_t)(76); + _curvea0[121] = _6972; + uint16_t _6973 = (uint16_t)(77); + _curvea0[122] = _6973; + uint16_t _6974 = (uint16_t)(77); + _curvea0[123] = _6974; + uint16_t _6975 = (uint16_t)(77); + _curvea0[124] = _6975; + uint16_t _6976 = (uint16_t)(78); + _curvea0[125] = _6976; + uint16_t _6977 = (uint16_t)(78); + _curvea0[126] = _6977; + uint16_t _6978 = (uint16_t)(79); + _curvea0[127] = _6978; + uint16_t _6979 = (uint16_t)(79); + _curvea0[128] = _6979; + uint16_t _6980 = (uint16_t)(79); + _curvea0[129] = _6980; + uint16_t _6981 = (uint16_t)(80); + _curvea0[130] = _6981; + uint16_t _6982 = (uint16_t)(80); + _curvea0[131] = _6982; + uint16_t _6983 = (uint16_t)(81); + _curvea0[132] = _6983; + uint16_t _6984 = (uint16_t)(81); + _curvea0[133] = _6984; + uint16_t _6985 = (uint16_t)(82); + _curvea0[134] = _6985; + uint16_t _6986 = (uint16_t)(82); + _curvea0[135] = _6986; + uint16_t _6987 = (uint16_t)(82); + _curvea0[136] = _6987; + uint16_t _6988 = (uint16_t)(83); + _curvea0[137] = _6988; + uint16_t _6989 = (uint16_t)(83); + _curvea0[138] = _6989; + uint16_t _6990 = (uint16_t)(84); + _curvea0[139] = _6990; + uint16_t _6991 = (uint16_t)(84); + _curvea0[140] = _6991; + uint16_t _6992 = (uint16_t)(84); + _curvea0[141] = _6992; + uint16_t _6993 = (uint16_t)(85); + _curvea0[142] = _6993; + uint16_t _6994 = (uint16_t)(85); + _curvea0[143] = _6994; + uint16_t _6995 = (uint16_t)(86); + _curvea0[144] = _6995; + uint16_t _6996 = (uint16_t)(86); + _curvea0[145] = _6996; + uint16_t _6997 = (uint16_t)(86); + _curvea0[146] = _6997; + uint16_t _6998 = (uint16_t)(87); + _curvea0[147] = _6998; + uint16_t _6999 = (uint16_t)(87); + _curvea0[148] = _6999; + uint16_t _7000 = (uint16_t)(88); + _curvea0[149] = _7000; + uint16_t _7001 = (uint16_t)(88); + _curvea0[150] = _7001; + uint16_t _7002 = (uint16_t)(88); + _curvea0[151] = _7002; + uint16_t _7003 = (uint16_t)(89); + _curvea0[152] = _7003; + uint16_t _7004 = (uint16_t)(89); + _curvea0[153] = _7004; + uint16_t _7005 = (uint16_t)(90); + _curvea0[154] = _7005; + uint16_t _7006 = (uint16_t)(90); + _curvea0[155] = _7006; + uint16_t _7007 = (uint16_t)(90); + _curvea0[156] = _7007; + uint16_t _7008 = (uint16_t)(91); + _curvea0[157] = _7008; + uint16_t _7009 = (uint16_t)(91); + _curvea0[158] = _7009; + uint16_t _7010 = (uint16_t)(92); + _curvea0[159] = _7010; + uint16_t _7011 = (uint16_t)(92); + _curvea0[160] = _7011; + uint16_t _7012 = (uint16_t)(92); + _curvea0[161] = _7012; + uint16_t _7013 = (uint16_t)(93); + _curvea0[162] = _7013; + uint16_t _7014 = (uint16_t)(93); + _curvea0[163] = _7014; + uint16_t _7015 = (uint16_t)(93); + _curvea0[164] = _7015; + uint16_t _7016 = (uint16_t)(94); + _curvea0[165] = _7016; + uint16_t _7017 = (uint16_t)(94); + _curvea0[166] = _7017; + uint16_t _7018 = (uint16_t)(95); + _curvea0[167] = _7018; + uint16_t _7019 = (uint16_t)(95); + _curvea0[168] = _7019; + uint16_t _7020 = (uint16_t)(95); + _curvea0[169] = _7020; + uint16_t _7021 = (uint16_t)(96); + _curvea0[170] = _7021; + uint16_t _7022 = (uint16_t)(96); + _curvea0[171] = _7022; + uint16_t _7023 = (uint16_t)(97); + _curvea0[172] = _7023; + uint16_t _7024 = (uint16_t)(97); + _curvea0[173] = _7024; + uint16_t _7025 = (uint16_t)(97); + _curvea0[174] = _7025; + uint16_t _7026 = (uint16_t)(98); + _curvea0[175] = _7026; + uint16_t _7027 = (uint16_t)(98); + _curvea0[176] = _7027; + uint16_t _7028 = (uint16_t)(99); + _curvea0[177] = _7028; + uint16_t _7029 = (uint16_t)(99); + _curvea0[178] = _7029; + uint16_t _7030 = (uint16_t)(99); + _curvea0[179] = _7030; + uint16_t _7031 = (uint16_t)(100); + _curvea0[180] = _7031; + uint16_t _7032 = (uint16_t)(100); + _curvea0[181] = _7032; + uint16_t _7033 = (uint16_t)(100); + _curvea0[182] = _7033; + uint16_t _7034 = (uint16_t)(101); + _curvea0[183] = _7034; + uint16_t _7035 = (uint16_t)(101); + _curvea0[184] = _7035; + uint16_t _7036 = (uint16_t)(102); + _curvea0[185] = _7036; + uint16_t _7037 = (uint16_t)(102); + _curvea0[186] = _7037; + uint16_t _7038 = (uint16_t)(102); + _curvea0[187] = _7038; + uint16_t _7039 = (uint16_t)(103); + _curvea0[188] = _7039; + uint16_t _7040 = (uint16_t)(103); + _curvea0[189] = _7040; + uint16_t _7041 = (uint16_t)(103); + _curvea0[190] = _7041; + uint16_t _7042 = (uint16_t)(104); + _curvea0[191] = _7042; + uint16_t _7043 = (uint16_t)(104); + _curvea0[192] = _7043; + uint16_t _7044 = (uint16_t)(105); + _curvea0[193] = _7044; + uint16_t _7045 = (uint16_t)(105); + _curvea0[194] = _7045; + uint16_t _7046 = (uint16_t)(105); + _curvea0[195] = _7046; + uint16_t _7047 = (uint16_t)(106); + _curvea0[196] = _7047; + uint16_t _7048 = (uint16_t)(106); + _curvea0[197] = _7048; + uint16_t _7049 = (uint16_t)(106); + _curvea0[198] = _7049; + uint16_t _7050 = (uint16_t)(107); + _curvea0[199] = _7050; + uint16_t _7051 = (uint16_t)(107); + _curvea0[200] = _7051; + uint16_t _7052 = (uint16_t)(108); + _curvea0[201] = _7052; + uint16_t _7053 = (uint16_t)(108); + _curvea0[202] = _7053; + uint16_t _7054 = (uint16_t)(108); + _curvea0[203] = _7054; + uint16_t _7055 = (uint16_t)(109); + _curvea0[204] = _7055; + uint16_t _7056 = (uint16_t)(109); + _curvea0[205] = _7056; + uint16_t _7057 = (uint16_t)(109); + _curvea0[206] = _7057; + uint16_t _7058 = (uint16_t)(110); + _curvea0[207] = _7058; + uint16_t _7059 = (uint16_t)(110); + _curvea0[208] = _7059; + uint16_t _7060 = (uint16_t)(111); + _curvea0[209] = _7060; + uint16_t _7061 = (uint16_t)(111); + _curvea0[210] = _7061; + uint16_t _7062 = (uint16_t)(111); + _curvea0[211] = _7062; + uint16_t _7063 = (uint16_t)(112); + _curvea0[212] = _7063; + uint16_t _7064 = (uint16_t)(112); + _curvea0[213] = _7064; + uint16_t _7065 = (uint16_t)(112); + _curvea0[214] = _7065; + uint16_t _7066 = (uint16_t)(113); + _curvea0[215] = _7066; + uint16_t _7067 = (uint16_t)(113); + _curvea0[216] = _7067; + uint16_t _7068 = (uint16_t)(113); + _curvea0[217] = _7068; + uint16_t _7069 = (uint16_t)(114); + _curvea0[218] = _7069; + uint16_t _7070 = (uint16_t)(114); + _curvea0[219] = _7070; + uint16_t _7071 = (uint16_t)(115); + _curvea0[220] = _7071; + uint16_t _7072 = (uint16_t)(115); + _curvea0[221] = _7072; + uint16_t _7073 = (uint16_t)(115); + _curvea0[222] = _7073; + uint16_t _7074 = (uint16_t)(116); + _curvea0[223] = _7074; + uint16_t _7075 = (uint16_t)(116); + _curvea0[224] = _7075; + uint16_t _7076 = (uint16_t)(116); + _curvea0[225] = _7076; + uint16_t _7077 = (uint16_t)(117); + _curvea0[226] = _7077; + uint16_t _7078 = (uint16_t)(117); + _curvea0[227] = _7078; + uint16_t _7079 = (uint16_t)(117); + _curvea0[228] = _7079; + uint16_t _7080 = (uint16_t)(118); + _curvea0[229] = _7080; + uint16_t _7081 = (uint16_t)(118); + _curvea0[230] = _7081; + uint16_t _7082 = (uint16_t)(119); + _curvea0[231] = _7082; + uint16_t _7083 = (uint16_t)(119); + _curvea0[232] = _7083; + uint16_t _7084 = (uint16_t)(119); + _curvea0[233] = _7084; + uint16_t _7085 = (uint16_t)(120); + _curvea0[234] = _7085; + uint16_t _7086 = (uint16_t)(120); + _curvea0[235] = _7086; + uint16_t _7087 = (uint16_t)(120); + _curvea0[236] = _7087; + uint16_t _7088 = (uint16_t)(121); + _curvea0[237] = _7088; + uint16_t _7089 = (uint16_t)(121); + _curvea0[238] = _7089; + uint16_t _7090 = (uint16_t)(121); + _curvea0[239] = _7090; + uint16_t _7091 = (uint16_t)(122); + _curvea0[240] = _7091; + uint16_t _7092 = (uint16_t)(122); + _curvea0[241] = _7092; + uint16_t _7093 = (uint16_t)(123); + _curvea0[242] = _7093; + uint16_t _7094 = (uint16_t)(123); + _curvea0[243] = _7094; + uint16_t _7095 = (uint16_t)(123); + _curvea0[244] = _7095; + uint16_t _7096 = (uint16_t)(124); + _curvea0[245] = _7096; + uint16_t _7097 = (uint16_t)(124); + _curvea0[246] = _7097; + uint16_t _7098 = (uint16_t)(124); + _curvea0[247] = _7098; + uint16_t _7099 = (uint16_t)(125); + _curvea0[248] = _7099; + uint16_t _7100 = (uint16_t)(125); + _curvea0[249] = _7100; + uint16_t _7101 = (uint16_t)(125); + _curvea0[250] = _7101; + uint16_t _7102 = (uint16_t)(126); + _curvea0[251] = _7102; + uint16_t _7103 = (uint16_t)(126); + _curvea0[252] = _7103; + uint16_t _7104 = (uint16_t)(126); + _curvea0[253] = _7104; + uint16_t _7105 = (uint16_t)(127); + _curvea0[254] = _7105; + uint16_t _7106 = (uint16_t)(127); + _curvea0[255] = _7106; + uint16_t _7107 = (uint16_t)(128); + _curvea0[256] = _7107; + uint16_t _7108 = (uint16_t)(128); + _curvea0[257] = _7108; + uint16_t _7109 = (uint16_t)(128); + _curvea0[258] = _7109; + uint16_t _7110 = (uint16_t)(129); + _curvea0[259] = _7110; + uint16_t _7111 = (uint16_t)(129); + _curvea0[260] = _7111; + uint16_t _7112 = (uint16_t)(129); + _curvea0[261] = _7112; + uint16_t _7113 = (uint16_t)(130); + _curvea0[262] = _7113; + uint16_t _7114 = (uint16_t)(130); + _curvea0[263] = _7114; + uint16_t _7115 = (uint16_t)(130); + _curvea0[264] = _7115; + uint16_t _7116 = (uint16_t)(131); + _curvea0[265] = _7116; + uint16_t _7117 = (uint16_t)(131); + _curvea0[266] = _7117; + uint16_t _7118 = (uint16_t)(131); + _curvea0[267] = _7118; + uint16_t _7119 = (uint16_t)(132); + _curvea0[268] = _7119; + uint16_t _7120 = (uint16_t)(132); + _curvea0[269] = _7120; + uint16_t _7121 = (uint16_t)(132); + _curvea0[270] = _7121; + uint16_t _7122 = (uint16_t)(133); + _curvea0[271] = _7122; + uint16_t _7123 = (uint16_t)(133); + _curvea0[272] = _7123; + uint16_t _7124 = (uint16_t)(133); + _curvea0[273] = _7124; + uint16_t _7125 = (uint16_t)(134); + _curvea0[274] = _7125; + uint16_t _7126 = (uint16_t)(134); + _curvea0[275] = _7126; + uint16_t _7127 = (uint16_t)(134); + _curvea0[276] = _7127; + uint16_t _7128 = (uint16_t)(135); + _curvea0[277] = _7128; + uint16_t _7129 = (uint16_t)(135); + _curvea0[278] = _7129; + uint16_t _7130 = (uint16_t)(135); + _curvea0[279] = _7130; + uint16_t _7131 = (uint16_t)(136); + _curvea0[280] = _7131; + uint16_t _7132 = (uint16_t)(136); + _curvea0[281] = _7132; + uint16_t _7133 = (uint16_t)(136); + _curvea0[282] = _7133; + uint16_t _7134 = (uint16_t)(137); + _curvea0[283] = _7134; + uint16_t _7135 = (uint16_t)(137); + _curvea0[284] = _7135; + uint16_t _7136 = (uint16_t)(137); + _curvea0[285] = _7136; + uint16_t _7137 = (uint16_t)(138); + _curvea0[286] = _7137; + uint16_t _7138 = (uint16_t)(138); + _curvea0[287] = _7138; + uint16_t _7139 = (uint16_t)(138); + _curvea0[288] = _7139; + uint16_t _7140 = (uint16_t)(139); + _curvea0[289] = _7140; + uint16_t _7141 = (uint16_t)(139); + _curvea0[290] = _7141; + uint16_t _7142 = (uint16_t)(139); + _curvea0[291] = _7142; + uint16_t _7143 = (uint16_t)(140); + _curvea0[292] = _7143; + uint16_t _7144 = (uint16_t)(140); + _curvea0[293] = _7144; + uint16_t _7145 = (uint16_t)(140); + _curvea0[294] = _7145; + uint16_t _7146 = (uint16_t)(141); + _curvea0[295] = _7146; + uint16_t _7147 = (uint16_t)(141); + _curvea0[296] = _7147; + uint16_t _7148 = (uint16_t)(141); + _curvea0[297] = _7148; + uint16_t _7149 = (uint16_t)(141); + _curvea0[298] = _7149; + uint16_t _7150 = (uint16_t)(142); + _curvea0[299] = _7150; + uint16_t _7151 = (uint16_t)(142); + _curvea0[300] = _7151; + uint16_t _7152 = (uint16_t)(142); + _curvea0[301] = _7152; + uint16_t _7153 = (uint16_t)(143); + _curvea0[302] = _7153; + uint16_t _7154 = (uint16_t)(143); + _curvea0[303] = _7154; + uint16_t _7155 = (uint16_t)(143); + _curvea0[304] = _7155; + uint16_t _7156 = (uint16_t)(144); + _curvea0[305] = _7156; + uint16_t _7157 = (uint16_t)(144); + _curvea0[306] = _7157; + uint16_t _7158 = (uint16_t)(144); + _curvea0[307] = _7158; + uint16_t _7159 = (uint16_t)(145); + _curvea0[308] = _7159; + uint16_t _7160 = (uint16_t)(145); + _curvea0[309] = _7160; + uint16_t _7161 = (uint16_t)(145); + _curvea0[310] = _7161; + uint16_t _7162 = (uint16_t)(145); + _curvea0[311] = _7162; + uint16_t _7163 = (uint16_t)(146); + _curvea0[312] = _7163; + uint16_t _7164 = (uint16_t)(146); + _curvea0[313] = _7164; + uint16_t _7165 = (uint16_t)(146); + _curvea0[314] = _7165; + uint16_t _7166 = (uint16_t)(147); + _curvea0[315] = _7166; + uint16_t _7167 = (uint16_t)(147); + _curvea0[316] = _7167; + uint16_t _7168 = (uint16_t)(147); + _curvea0[317] = _7168; + uint16_t _7169 = (uint16_t)(148); + _curvea0[318] = _7169; + uint16_t _7170 = (uint16_t)(148); + _curvea0[319] = _7170; + uint16_t _7171 = (uint16_t)(148); + _curvea0[320] = _7171; + uint16_t _7172 = (uint16_t)(148); + _curvea0[321] = _7172; + uint16_t _7173 = (uint16_t)(149); + _curvea0[322] = _7173; + uint16_t _7174 = (uint16_t)(149); + _curvea0[323] = _7174; + uint16_t _7175 = (uint16_t)(149); + _curvea0[324] = _7175; + uint16_t _7176 = (uint16_t)(150); + _curvea0[325] = _7176; + uint16_t _7177 = (uint16_t)(150); + _curvea0[326] = _7177; + uint16_t _7178 = (uint16_t)(150); + _curvea0[327] = _7178; + uint16_t _7179 = (uint16_t)(150); + _curvea0[328] = _7179; + uint16_t _7180 = (uint16_t)(151); + _curvea0[329] = _7180; + uint16_t _7181 = (uint16_t)(151); + _curvea0[330] = _7181; + uint16_t _7182 = (uint16_t)(151); + _curvea0[331] = _7182; + uint16_t _7183 = (uint16_t)(152); + _curvea0[332] = _7183; + uint16_t _7184 = (uint16_t)(152); + _curvea0[333] = _7184; + uint16_t _7185 = (uint16_t)(152); + _curvea0[334] = _7185; + uint16_t _7186 = (uint16_t)(152); + _curvea0[335] = _7186; + uint16_t _7187 = (uint16_t)(153); + _curvea0[336] = _7187; + uint16_t _7188 = (uint16_t)(153); + _curvea0[337] = _7188; + uint16_t _7189 = (uint16_t)(153); + _curvea0[338] = _7189; + uint16_t _7190 = (uint16_t)(154); + _curvea0[339] = _7190; + uint16_t _7191 = (uint16_t)(154); + _curvea0[340] = _7191; + uint16_t _7192 = (uint16_t)(154); + _curvea0[341] = _7192; + uint16_t _7193 = (uint16_t)(154); + _curvea0[342] = _7193; + uint16_t _7194 = (uint16_t)(155); + _curvea0[343] = _7194; + uint16_t _7195 = (uint16_t)(155); + _curvea0[344] = _7195; + uint16_t _7196 = (uint16_t)(155); + _curvea0[345] = _7196; + uint16_t _7197 = (uint16_t)(156); + _curvea0[346] = _7197; + uint16_t _7198 = (uint16_t)(156); + _curvea0[347] = _7198; + uint16_t _7199 = (uint16_t)(156); + _curvea0[348] = _7199; + uint16_t _7200 = (uint16_t)(156); + _curvea0[349] = _7200; + uint16_t _7201 = (uint16_t)(157); + _curvea0[350] = _7201; + uint16_t _7202 = (uint16_t)(157); + _curvea0[351] = _7202; + uint16_t _7203 = (uint16_t)(157); + _curvea0[352] = _7203; + uint16_t _7204 = (uint16_t)(157); + _curvea0[353] = _7204; + uint16_t _7205 = (uint16_t)(158); + _curvea0[354] = _7205; + uint16_t _7206 = (uint16_t)(158); + _curvea0[355] = _7206; + uint16_t _7207 = (uint16_t)(158); + _curvea0[356] = _7207; + uint16_t _7208 = (uint16_t)(159); + _curvea0[357] = _7208; + uint16_t _7209 = (uint16_t)(159); + _curvea0[358] = _7209; + uint16_t _7210 = (uint16_t)(159); + _curvea0[359] = _7210; + uint16_t _7211 = (uint16_t)(159); + _curvea0[360] = _7211; + uint16_t _7212 = (uint16_t)(160); + _curvea0[361] = _7212; + uint16_t _7213 = (uint16_t)(160); + _curvea0[362] = _7213; + uint16_t _7214 = (uint16_t)(160); + _curvea0[363] = _7214; + uint16_t _7215 = (uint16_t)(160); + _curvea0[364] = _7215; + uint16_t _7216 = (uint16_t)(161); + _curvea0[365] = _7216; + uint16_t _7217 = (uint16_t)(161); + _curvea0[366] = _7217; + uint16_t _7218 = (uint16_t)(161); + _curvea0[367] = _7218; + uint16_t _7219 = (uint16_t)(161); + _curvea0[368] = _7219; + uint16_t _7220 = (uint16_t)(162); + _curvea0[369] = _7220; + uint16_t _7221 = (uint16_t)(162); + _curvea0[370] = _7221; + uint16_t _7222 = (uint16_t)(162); + _curvea0[371] = _7222; + uint16_t _7223 = (uint16_t)(162); + _curvea0[372] = _7223; + uint16_t _7224 = (uint16_t)(163); + _curvea0[373] = _7224; + uint16_t _7225 = (uint16_t)(163); + _curvea0[374] = _7225; + uint16_t _7226 = (uint16_t)(163); + _curvea0[375] = _7226; + uint16_t _7227 = (uint16_t)(163); + _curvea0[376] = _7227; + uint16_t _7228 = (uint16_t)(164); + _curvea0[377] = _7228; + uint16_t _7229 = (uint16_t)(164); + _curvea0[378] = _7229; + uint16_t _7230 = (uint16_t)(164); + _curvea0[379] = _7230; + uint16_t _7231 = (uint16_t)(164); + _curvea0[380] = _7231; + uint16_t _7232 = (uint16_t)(165); + _curvea0[381] = _7232; + uint16_t _7233 = (uint16_t)(165); + _curvea0[382] = _7233; + uint16_t _7234 = (uint16_t)(165); + _curvea0[383] = _7234; + uint16_t _7235 = (uint16_t)(166); + _curvea0[384] = _7235; + uint16_t _7236 = (uint16_t)(166); + _curvea0[385] = _7236; + uint16_t _7237 = (uint16_t)(166); + _curvea0[386] = _7237; + uint16_t _7238 = (uint16_t)(166); + _curvea0[387] = _7238; + uint16_t _7239 = (uint16_t)(167); + _curvea0[388] = _7239; + uint16_t _7240 = (uint16_t)(167); + _curvea0[389] = _7240; + uint16_t _7241 = (uint16_t)(167); + _curvea0[390] = _7241; + uint16_t _7242 = (uint16_t)(167); + _curvea0[391] = _7242; + uint16_t _7243 = (uint16_t)(167); + _curvea0[392] = _7243; + uint16_t _7244 = (uint16_t)(168); + _curvea0[393] = _7244; + uint16_t _7245 = (uint16_t)(168); + _curvea0[394] = _7245; + uint16_t _7246 = (uint16_t)(168); + _curvea0[395] = _7246; + uint16_t _7247 = (uint16_t)(168); + _curvea0[396] = _7247; + uint16_t _7248 = (uint16_t)(169); + _curvea0[397] = _7248; + uint16_t _7249 = (uint16_t)(169); + _curvea0[398] = _7249; + uint16_t _7250 = (uint16_t)(169); + _curvea0[399] = _7250; + uint16_t _7251 = (uint16_t)(169); + _curvea0[400] = _7251; + uint16_t _7252 = (uint16_t)(170); + _curvea0[401] = _7252; + uint16_t _7253 = (uint16_t)(170); + _curvea0[402] = _7253; + uint16_t _7254 = (uint16_t)(170); + _curvea0[403] = _7254; + uint16_t _7255 = (uint16_t)(170); + _curvea0[404] = _7255; + uint16_t _7256 = (uint16_t)(171); + _curvea0[405] = _7256; + uint16_t _7257 = (uint16_t)(171); + _curvea0[406] = _7257; + uint16_t _7258 = (uint16_t)(171); + _curvea0[407] = _7258; + uint16_t _7259 = (uint16_t)(171); + _curvea0[408] = _7259; + uint16_t _7260 = (uint16_t)(172); + _curvea0[409] = _7260; + uint16_t _7261 = (uint16_t)(172); + _curvea0[410] = _7261; + uint16_t _7262 = (uint16_t)(172); + _curvea0[411] = _7262; + uint16_t _7263 = (uint16_t)(172); + _curvea0[412] = _7263; + uint16_t _7264 = (uint16_t)(173); + _curvea0[413] = _7264; + uint16_t _7265 = (uint16_t)(173); + _curvea0[414] = _7265; + uint16_t _7266 = (uint16_t)(173); + _curvea0[415] = _7266; + uint16_t _7267 = (uint16_t)(173); + _curvea0[416] = _7267; + uint16_t _7268 = (uint16_t)(173); + _curvea0[417] = _7268; + uint16_t _7269 = (uint16_t)(174); + _curvea0[418] = _7269; + uint16_t _7270 = (uint16_t)(174); + _curvea0[419] = _7270; + uint16_t _7271 = (uint16_t)(174); + _curvea0[420] = _7271; + uint16_t _7272 = (uint16_t)(174); + _curvea0[421] = _7272; + uint16_t _7273 = (uint16_t)(175); + _curvea0[422] = _7273; + uint16_t _7274 = (uint16_t)(175); + _curvea0[423] = _7274; + uint16_t _7275 = (uint16_t)(175); + _curvea0[424] = _7275; + uint16_t _7276 = (uint16_t)(175); + _curvea0[425] = _7276; + uint16_t _7277 = (uint16_t)(176); + _curvea0[426] = _7277; + uint16_t _7278 = (uint16_t)(176); + _curvea0[427] = _7278; + uint16_t _7279 = (uint16_t)(176); + _curvea0[428] = _7279; + uint16_t _7280 = (uint16_t)(176); + _curvea0[429] = _7280; + uint16_t _7281 = (uint16_t)(176); + _curvea0[430] = _7281; + uint16_t _7282 = (uint16_t)(177); + _curvea0[431] = _7282; + uint16_t _7283 = (uint16_t)(177); + _curvea0[432] = _7283; + uint16_t _7284 = (uint16_t)(177); + _curvea0[433] = _7284; + uint16_t _7285 = (uint16_t)(177); + _curvea0[434] = _7285; + uint16_t _7286 = (uint16_t)(178); + _curvea0[435] = _7286; + uint16_t _7287 = (uint16_t)(178); + _curvea0[436] = _7287; + uint16_t _7288 = (uint16_t)(178); + _curvea0[437] = _7288; + uint16_t _7289 = (uint16_t)(178); + _curvea0[438] = _7289; + uint16_t _7290 = (uint16_t)(178); + _curvea0[439] = _7290; + uint16_t _7291 = (uint16_t)(179); + _curvea0[440] = _7291; + uint16_t _7292 = (uint16_t)(179); + _curvea0[441] = _7292; + uint16_t _7293 = (uint16_t)(179); + _curvea0[442] = _7293; + uint16_t _7294 = (uint16_t)(179); + _curvea0[443] = _7294; + uint16_t _7295 = (uint16_t)(180); + _curvea0[444] = _7295; + uint16_t _7296 = (uint16_t)(180); + _curvea0[445] = _7296; + uint16_t _7297 = (uint16_t)(180); + _curvea0[446] = _7297; + uint16_t _7298 = (uint16_t)(180); + _curvea0[447] = _7298; + uint16_t _7299 = (uint16_t)(180); + _curvea0[448] = _7299; + uint16_t _7300 = (uint16_t)(181); + _curvea0[449] = _7300; + uint16_t _7301 = (uint16_t)(181); + _curvea0[450] = _7301; + uint16_t _7302 = (uint16_t)(181); + _curvea0[451] = _7302; + uint16_t _7303 = (uint16_t)(181); + _curvea0[452] = _7303; + uint16_t _7304 = (uint16_t)(181); + _curvea0[453] = _7304; + uint16_t _7305 = (uint16_t)(182); + _curvea0[454] = _7305; + uint16_t _7306 = (uint16_t)(182); + _curvea0[455] = _7306; + uint16_t _7307 = (uint16_t)(182); + _curvea0[456] = _7307; + uint16_t _7308 = (uint16_t)(182); + _curvea0[457] = _7308; + uint16_t _7309 = (uint16_t)(183); + _curvea0[458] = _7309; + uint16_t _7310 = (uint16_t)(183); + _curvea0[459] = _7310; + uint16_t _7311 = (uint16_t)(183); + _curvea0[460] = _7311; + uint16_t _7312 = (uint16_t)(183); + _curvea0[461] = _7312; + uint16_t _7313 = (uint16_t)(183); + _curvea0[462] = _7313; + uint16_t _7314 = (uint16_t)(184); + _curvea0[463] = _7314; + uint16_t _7315 = (uint16_t)(184); + _curvea0[464] = _7315; + uint16_t _7316 = (uint16_t)(184); + _curvea0[465] = _7316; + uint16_t _7317 = (uint16_t)(184); + _curvea0[466] = _7317; + uint16_t _7318 = (uint16_t)(184); + _curvea0[467] = _7318; + uint16_t _7319 = (uint16_t)(185); + _curvea0[468] = _7319; + uint16_t _7320 = (uint16_t)(185); + _curvea0[469] = _7320; + uint16_t _7321 = (uint16_t)(185); + _curvea0[470] = _7321; + uint16_t _7322 = (uint16_t)(185); + _curvea0[471] = _7322; + uint16_t _7323 = (uint16_t)(185); + _curvea0[472] = _7323; + uint16_t _7324 = (uint16_t)(186); + _curvea0[473] = _7324; + uint16_t _7325 = (uint16_t)(186); + _curvea0[474] = _7325; + uint16_t _7326 = (uint16_t)(186); + _curvea0[475] = _7326; + uint16_t _7327 = (uint16_t)(186); + _curvea0[476] = _7327; + uint16_t _7328 = (uint16_t)(187); + _curvea0[477] = _7328; + uint16_t _7329 = (uint16_t)(187); + _curvea0[478] = _7329; + uint16_t _7330 = (uint16_t)(187); + _curvea0[479] = _7330; + uint16_t _7331 = (uint16_t)(187); + _curvea0[480] = _7331; + uint16_t _7332 = (uint16_t)(187); + _curvea0[481] = _7332; + uint16_t _7333 = (uint16_t)(188); + _curvea0[482] = _7333; + uint16_t _7334 = (uint16_t)(188); + _curvea0[483] = _7334; + uint16_t _7335 = (uint16_t)(188); + _curvea0[484] = _7335; + uint16_t _7336 = (uint16_t)(188); + _curvea0[485] = _7336; + uint16_t _7337 = (uint16_t)(188); + _curvea0[486] = _7337; + uint16_t _7338 = (uint16_t)(189); + _curvea0[487] = _7338; + uint16_t _7339 = (uint16_t)(189); + _curvea0[488] = _7339; + uint16_t _7340 = (uint16_t)(189); + _curvea0[489] = _7340; + uint16_t _7341 = (uint16_t)(189); + _curvea0[490] = _7341; + uint16_t _7342 = (uint16_t)(189); + _curvea0[491] = _7342; + uint16_t _7343 = (uint16_t)(190); + _curvea0[492] = _7343; + uint16_t _7344 = (uint16_t)(190); + _curvea0[493] = _7344; + uint16_t _7345 = (uint16_t)(190); + _curvea0[494] = _7345; + uint16_t _7346 = (uint16_t)(190); + _curvea0[495] = _7346; + uint16_t _7347 = (uint16_t)(190); + _curvea0[496] = _7347; + uint16_t _7348 = (uint16_t)(190); + _curvea0[497] = _7348; + uint16_t _7349 = (uint16_t)(191); + _curvea0[498] = _7349; + uint16_t _7350 = (uint16_t)(191); + _curvea0[499] = _7350; + uint16_t _7351 = (uint16_t)(191); + _curvea0[500] = _7351; + uint16_t _7352 = (uint16_t)(191); + _curvea0[501] = _7352; + uint16_t _7353 = (uint16_t)(191); + _curvea0[502] = _7353; + uint16_t _7354 = (uint16_t)(192); + _curvea0[503] = _7354; + uint16_t _7355 = (uint16_t)(192); + _curvea0[504] = _7355; + uint16_t _7356 = (uint16_t)(192); + _curvea0[505] = _7356; + uint16_t _7357 = (uint16_t)(192); + _curvea0[506] = _7357; + uint16_t _7358 = (uint16_t)(192); + _curvea0[507] = _7358; + uint16_t _7359 = (uint16_t)(193); + _curvea0[508] = _7359; + uint16_t _7360 = (uint16_t)(193); + _curvea0[509] = _7360; + uint16_t _7361 = (uint16_t)(193); + _curvea0[510] = _7361; + uint16_t _7362 = (uint16_t)(193); + _curvea0[511] = _7362; + uint16_t _7363 = (uint16_t)(193); + _curvea0[512] = _7363; + uint16_t _7364 = (uint16_t)(194); + _curvea0[513] = _7364; + uint16_t _7365 = (uint16_t)(194); + _curvea0[514] = _7365; + uint16_t _7366 = (uint16_t)(194); + _curvea0[515] = _7366; + uint16_t _7367 = (uint16_t)(194); + _curvea0[516] = _7367; + uint16_t _7368 = (uint16_t)(194); + _curvea0[517] = _7368; + uint16_t _7369 = (uint16_t)(195); + _curvea0[518] = _7369; + uint16_t _7370 = (uint16_t)(195); + _curvea0[519] = _7370; + uint16_t _7371 = (uint16_t)(195); + _curvea0[520] = _7371; + uint16_t _7372 = (uint16_t)(195); + _curvea0[521] = _7372; + uint16_t _7373 = (uint16_t)(195); + _curvea0[522] = _7373; + uint16_t _7374 = (uint16_t)(195); + _curvea0[523] = _7374; + uint16_t _7375 = (uint16_t)(196); + _curvea0[524] = _7375; + uint16_t _7376 = (uint16_t)(196); + _curvea0[525] = _7376; + uint16_t _7377 = (uint16_t)(196); + _curvea0[526] = _7377; + uint16_t _7378 = (uint16_t)(196); + _curvea0[527] = _7378; + uint16_t _7379 = (uint16_t)(196); + _curvea0[528] = _7379; + uint16_t _7380 = (uint16_t)(197); + _curvea0[529] = _7380; + uint16_t _7381 = (uint16_t)(197); + _curvea0[530] = _7381; + uint16_t _7382 = (uint16_t)(197); + _curvea0[531] = _7382; + uint16_t _7383 = (uint16_t)(197); + _curvea0[532] = _7383; + uint16_t _7384 = (uint16_t)(197); + _curvea0[533] = _7384; + uint16_t _7385 = (uint16_t)(197); + _curvea0[534] = _7385; + uint16_t _7386 = (uint16_t)(198); + _curvea0[535] = _7386; + uint16_t _7387 = (uint16_t)(198); + _curvea0[536] = _7387; + uint16_t _7388 = (uint16_t)(198); + _curvea0[537] = _7388; + uint16_t _7389 = (uint16_t)(198); + _curvea0[538] = _7389; + uint16_t _7390 = (uint16_t)(198); + _curvea0[539] = _7390; + uint16_t _7391 = (uint16_t)(199); + _curvea0[540] = _7391; + uint16_t _7392 = (uint16_t)(199); + _curvea0[541] = _7392; + uint16_t _7393 = (uint16_t)(199); + _curvea0[542] = _7393; + uint16_t _7394 = (uint16_t)(199); + _curvea0[543] = _7394; + uint16_t _7395 = (uint16_t)(199); + _curvea0[544] = _7395; + uint16_t _7396 = (uint16_t)(199); + _curvea0[545] = _7396; + uint16_t _7397 = (uint16_t)(200); + _curvea0[546] = _7397; + uint16_t _7398 = (uint16_t)(200); + _curvea0[547] = _7398; + uint16_t _7399 = (uint16_t)(200); + _curvea0[548] = _7399; + uint16_t _7400 = (uint16_t)(200); + _curvea0[549] = _7400; + uint16_t _7401 = (uint16_t)(200); + _curvea0[550] = _7401; + uint16_t _7402 = (uint16_t)(200); + _curvea0[551] = _7402; + uint16_t _7403 = (uint16_t)(201); + _curvea0[552] = _7403; + uint16_t _7404 = (uint16_t)(201); + _curvea0[553] = _7404; + uint16_t _7405 = (uint16_t)(201); + _curvea0[554] = _7405; + uint16_t _7406 = (uint16_t)(201); + _curvea0[555] = _7406; + uint16_t _7407 = (uint16_t)(201); + _curvea0[556] = _7407; + uint16_t _7408 = (uint16_t)(202); + _curvea0[557] = _7408; + uint16_t _7409 = (uint16_t)(202); + _curvea0[558] = _7409; + uint16_t _7410 = (uint16_t)(202); + _curvea0[559] = _7410; + uint16_t _7411 = (uint16_t)(202); + _curvea0[560] = _7411; + uint16_t _7412 = (uint16_t)(202); + _curvea0[561] = _7412; + uint16_t _7413 = (uint16_t)(202); + _curvea0[562] = _7413; + uint16_t _7414 = (uint16_t)(203); + _curvea0[563] = _7414; + uint16_t _7415 = (uint16_t)(203); + _curvea0[564] = _7415; + uint16_t _7416 = (uint16_t)(203); + _curvea0[565] = _7416; + uint16_t _7417 = (uint16_t)(203); + _curvea0[566] = _7417; + uint16_t _7418 = (uint16_t)(203); + _curvea0[567] = _7418; + uint16_t _7419 = (uint16_t)(203); + _curvea0[568] = _7419; + uint16_t _7420 = (uint16_t)(204); + _curvea0[569] = _7420; + uint16_t _7421 = (uint16_t)(204); + _curvea0[570] = _7421; + uint16_t _7422 = (uint16_t)(204); + _curvea0[571] = _7422; + uint16_t _7423 = (uint16_t)(204); + _curvea0[572] = _7423; + uint16_t _7424 = (uint16_t)(204); + _curvea0[573] = _7424; + uint16_t _7425 = (uint16_t)(204); + _curvea0[574] = _7425; + uint16_t _7426 = (uint16_t)(205); + _curvea0[575] = _7426; + uint16_t _7427 = (uint16_t)(205); + _curvea0[576] = _7427; + uint16_t _7428 = (uint16_t)(205); + _curvea0[577] = _7428; + uint16_t _7429 = (uint16_t)(205); + _curvea0[578] = _7429; + uint16_t _7430 = (uint16_t)(205); + _curvea0[579] = _7430; + uint16_t _7431 = (uint16_t)(205); + _curvea0[580] = _7431; + uint16_t _7432 = (uint16_t)(206); + _curvea0[581] = _7432; + uint16_t _7433 = (uint16_t)(206); + _curvea0[582] = _7433; + uint16_t _7434 = (uint16_t)(206); + _curvea0[583] = _7434; + uint16_t _7435 = (uint16_t)(206); + _curvea0[584] = _7435; + uint16_t _7436 = (uint16_t)(206); + _curvea0[585] = _7436; + uint16_t _7437 = (uint16_t)(206); + _curvea0[586] = _7437; + uint16_t _7438 = (uint16_t)(207); + _curvea0[587] = _7438; + uint16_t _7439 = (uint16_t)(207); + _curvea0[588] = _7439; + uint16_t _7440 = (uint16_t)(207); + _curvea0[589] = _7440; + uint16_t _7441 = (uint16_t)(207); + _curvea0[590] = _7441; + uint16_t _7442 = (uint16_t)(207); + _curvea0[591] = _7442; + uint16_t _7443 = (uint16_t)(207); + _curvea0[592] = _7443; + uint16_t _7444 = (uint16_t)(208); + _curvea0[593] = _7444; + uint16_t _7445 = (uint16_t)(208); + _curvea0[594] = _7445; + uint16_t _7446 = (uint16_t)(208); + _curvea0[595] = _7446; + uint16_t _7447 = (uint16_t)(208); + _curvea0[596] = _7447; + uint16_t _7448 = (uint16_t)(208); + _curvea0[597] = _7448; + uint16_t _7449 = (uint16_t)(208); + _curvea0[598] = _7449; + uint16_t _7450 = (uint16_t)(209); + _curvea0[599] = _7450; + uint16_t _7451 = (uint16_t)(209); + _curvea0[600] = _7451; + uint16_t _7452 = (uint16_t)(209); + _curvea0[601] = _7452; + uint16_t _7453 = (uint16_t)(209); + _curvea0[602] = _7453; + uint16_t _7454 = (uint16_t)(209); + _curvea0[603] = _7454; + uint16_t _7455 = (uint16_t)(209); + _curvea0[604] = _7455; + uint16_t _7456 = (uint16_t)(209); + _curvea0[605] = _7456; + uint16_t _7457 = (uint16_t)(210); + _curvea0[606] = _7457; + uint16_t _7458 = (uint16_t)(210); + _curvea0[607] = _7458; + uint16_t _7459 = (uint16_t)(210); + _curvea0[608] = _7459; + uint16_t _7460 = (uint16_t)(210); + _curvea0[609] = _7460; + uint16_t _7461 = (uint16_t)(210); + _curvea0[610] = _7461; + uint16_t _7462 = (uint16_t)(210); + _curvea0[611] = _7462; + uint16_t _7463 = (uint16_t)(211); + _curvea0[612] = _7463; + uint16_t _7464 = (uint16_t)(211); + _curvea0[613] = _7464; + uint16_t _7465 = (uint16_t)(211); + _curvea0[614] = _7465; + uint16_t _7466 = (uint16_t)(211); + _curvea0[615] = _7466; + uint16_t _7467 = (uint16_t)(211); + _curvea0[616] = _7467; + uint16_t _7468 = (uint16_t)(211); + _curvea0[617] = _7468; + uint16_t _7469 = (uint16_t)(211); + _curvea0[618] = _7469; + uint16_t _7470 = (uint16_t)(212); + _curvea0[619] = _7470; + uint16_t _7471 = (uint16_t)(212); + _curvea0[620] = _7471; + uint16_t _7472 = (uint16_t)(212); + _curvea0[621] = _7472; + uint16_t _7473 = (uint16_t)(212); + _curvea0[622] = _7473; + uint16_t _7474 = (uint16_t)(212); + _curvea0[623] = _7474; + uint16_t _7475 = (uint16_t)(212); + _curvea0[624] = _7475; + uint16_t _7476 = (uint16_t)(213); + _curvea0[625] = _7476; + uint16_t _7477 = (uint16_t)(213); + _curvea0[626] = _7477; + uint16_t _7478 = (uint16_t)(213); + _curvea0[627] = _7478; + uint16_t _7479 = (uint16_t)(213); + _curvea0[628] = _7479; + uint16_t _7480 = (uint16_t)(213); + _curvea0[629] = _7480; + uint16_t _7481 = (uint16_t)(213); + _curvea0[630] = _7481; + uint16_t _7482 = (uint16_t)(213); + _curvea0[631] = _7482; + uint16_t _7483 = (uint16_t)(214); + _curvea0[632] = _7483; + uint16_t _7484 = (uint16_t)(214); + _curvea0[633] = _7484; + uint16_t _7485 = (uint16_t)(214); + _curvea0[634] = _7485; + uint16_t _7486 = (uint16_t)(214); + _curvea0[635] = _7486; + uint16_t _7487 = (uint16_t)(214); + _curvea0[636] = _7487; + uint16_t _7488 = (uint16_t)(214); + _curvea0[637] = _7488; + uint16_t _7489 = (uint16_t)(214); + _curvea0[638] = _7489; + uint16_t _7490 = (uint16_t)(215); + _curvea0[639] = _7490; + uint16_t _7491 = (uint16_t)(215); + _curvea0[640] = _7491; + uint16_t _7492 = (uint16_t)(215); + _curvea0[641] = _7492; + uint16_t _7493 = (uint16_t)(215); + _curvea0[642] = _7493; + uint16_t _7494 = (uint16_t)(215); + _curvea0[643] = _7494; + uint16_t _7495 = (uint16_t)(215); + _curvea0[644] = _7495; + uint16_t _7496 = (uint16_t)(216); + _curvea0[645] = _7496; + uint16_t _7497 = (uint16_t)(216); + _curvea0[646] = _7497; + uint16_t _7498 = (uint16_t)(216); + _curvea0[647] = _7498; + uint16_t _7499 = (uint16_t)(216); + _curvea0[648] = _7499; + uint16_t _7500 = (uint16_t)(216); + _curvea0[649] = _7500; + uint16_t _7501 = (uint16_t)(216); + _curvea0[650] = _7501; + uint16_t _7502 = (uint16_t)(216); + _curvea0[651] = _7502; + uint16_t _7503 = (uint16_t)(217); + _curvea0[652] = _7503; + uint16_t _7504 = (uint16_t)(217); + _curvea0[653] = _7504; + uint16_t _7505 = (uint16_t)(217); + _curvea0[654] = _7505; + uint16_t _7506 = (uint16_t)(217); + _curvea0[655] = _7506; + uint16_t _7507 = (uint16_t)(217); + _curvea0[656] = _7507; + uint16_t _7508 = (uint16_t)(217); + _curvea0[657] = _7508; + uint16_t _7509 = (uint16_t)(217); + _curvea0[658] = _7509; + uint16_t _7510 = (uint16_t)(218); + _curvea0[659] = _7510; + uint16_t _7511 = (uint16_t)(218); + _curvea0[660] = _7511; + uint16_t _7512 = (uint16_t)(218); + _curvea0[661] = _7512; + uint16_t _7513 = (uint16_t)(218); + _curvea0[662] = _7513; + uint16_t _7514 = (uint16_t)(218); + _curvea0[663] = _7514; + uint16_t _7515 = (uint16_t)(218); + _curvea0[664] = _7515; + uint16_t _7516 = (uint16_t)(218); + _curvea0[665] = _7516; + uint16_t _7517 = (uint16_t)(219); + _curvea0[666] = _7517; + uint16_t _7518 = (uint16_t)(219); + _curvea0[667] = _7518; + uint16_t _7519 = (uint16_t)(219); + _curvea0[668] = _7519; + uint16_t _7520 = (uint16_t)(219); + _curvea0[669] = _7520; + uint16_t _7521 = (uint16_t)(219); + _curvea0[670] = _7521; + uint16_t _7522 = (uint16_t)(219); + _curvea0[671] = _7522; + uint16_t _7523 = (uint16_t)(219); + _curvea0[672] = _7523; + uint16_t _7524 = (uint16_t)(220); + _curvea0[673] = _7524; + uint16_t _7525 = (uint16_t)(220); + _curvea0[674] = _7525; + uint16_t _7526 = (uint16_t)(220); + _curvea0[675] = _7526; + uint16_t _7527 = (uint16_t)(220); + _curvea0[676] = _7527; + uint16_t _7528 = (uint16_t)(220); + _curvea0[677] = _7528; + uint16_t _7529 = (uint16_t)(220); + _curvea0[678] = _7529; + uint16_t _7530 = (uint16_t)(220); + _curvea0[679] = _7530; + uint16_t _7531 = (uint16_t)(220); + _curvea0[680] = _7531; + uint16_t _7532 = (uint16_t)(221); + _curvea0[681] = _7532; + uint16_t _7533 = (uint16_t)(221); + _curvea0[682] = _7533; + uint16_t _7534 = (uint16_t)(221); + _curvea0[683] = _7534; + uint16_t _7535 = (uint16_t)(221); + _curvea0[684] = _7535; + uint16_t _7536 = (uint16_t)(221); + _curvea0[685] = _7536; + uint16_t _7537 = (uint16_t)(221); + _curvea0[686] = _7537; + uint16_t _7538 = (uint16_t)(221); + _curvea0[687] = _7538; + uint16_t _7539 = (uint16_t)(222); + _curvea0[688] = _7539; + uint16_t _7540 = (uint16_t)(222); + _curvea0[689] = _7540; + uint16_t _7541 = (uint16_t)(222); + _curvea0[690] = _7541; + uint16_t _7542 = (uint16_t)(222); + _curvea0[691] = _7542; + uint16_t _7543 = (uint16_t)(222); + _curvea0[692] = _7543; + uint16_t _7544 = (uint16_t)(222); + _curvea0[693] = _7544; + uint16_t _7545 = (uint16_t)(222); + _curvea0[694] = _7545; + uint16_t _7546 = (uint16_t)(223); + _curvea0[695] = _7546; + uint16_t _7547 = (uint16_t)(223); + _curvea0[696] = _7547; + uint16_t _7548 = (uint16_t)(223); + _curvea0[697] = _7548; + uint16_t _7549 = (uint16_t)(223); + _curvea0[698] = _7549; + uint16_t _7550 = (uint16_t)(223); + _curvea0[699] = _7550; + uint16_t _7551 = (uint16_t)(223); + _curvea0[700] = _7551; + uint16_t _7552 = (uint16_t)(223); + _curvea0[701] = _7552; + uint16_t _7553 = (uint16_t)(223); + _curvea0[702] = _7553; + uint16_t _7554 = (uint16_t)(224); + _curvea0[703] = _7554; + uint16_t _7555 = (uint16_t)(224); + _curvea0[704] = _7555; + uint16_t _7556 = (uint16_t)(224); + _curvea0[705] = _7556; + uint16_t _7557 = (uint16_t)(224); + _curvea0[706] = _7557; + uint16_t _7558 = (uint16_t)(224); + _curvea0[707] = _7558; + uint16_t _7559 = (uint16_t)(224); + _curvea0[708] = _7559; + uint16_t _7560 = (uint16_t)(224); + _curvea0[709] = _7560; + uint16_t _7561 = (uint16_t)(224); + _curvea0[710] = _7561; + uint16_t _7562 = (uint16_t)(225); + _curvea0[711] = _7562; + uint16_t _7563 = (uint16_t)(225); + _curvea0[712] = _7563; + uint16_t _7564 = (uint16_t)(225); + _curvea0[713] = _7564; + uint16_t _7565 = (uint16_t)(225); + _curvea0[714] = _7565; + uint16_t _7566 = (uint16_t)(225); + _curvea0[715] = _7566; + uint16_t _7567 = (uint16_t)(225); + _curvea0[716] = _7567; + uint16_t _7568 = (uint16_t)(225); + _curvea0[717] = _7568; + uint16_t _7569 = (uint16_t)(226); + _curvea0[718] = _7569; + uint16_t _7570 = (uint16_t)(226); + _curvea0[719] = _7570; + uint16_t _7571 = (uint16_t)(226); + _curvea0[720] = _7571; + uint16_t _7572 = (uint16_t)(226); + _curvea0[721] = _7572; + uint16_t _7573 = (uint16_t)(226); + _curvea0[722] = _7573; + uint16_t _7574 = (uint16_t)(226); + _curvea0[723] = _7574; + uint16_t _7575 = (uint16_t)(226); + _curvea0[724] = _7575; + uint16_t _7576 = (uint16_t)(226); + _curvea0[725] = _7576; + uint16_t _7577 = (uint16_t)(227); + _curvea0[726] = _7577; + uint16_t _7578 = (uint16_t)(227); + _curvea0[727] = _7578; + uint16_t _7579 = (uint16_t)(227); + _curvea0[728] = _7579; + uint16_t _7580 = (uint16_t)(227); + _curvea0[729] = _7580; + uint16_t _7581 = (uint16_t)(227); + _curvea0[730] = _7581; + uint16_t _7582 = (uint16_t)(227); + _curvea0[731] = _7582; + uint16_t _7583 = (uint16_t)(227); + _curvea0[732] = _7583; + uint16_t _7584 = (uint16_t)(227); + _curvea0[733] = _7584; + uint16_t _7585 = (uint16_t)(228); + _curvea0[734] = _7585; + uint16_t _7586 = (uint16_t)(228); + _curvea0[735] = _7586; + uint16_t _7587 = (uint16_t)(228); + _curvea0[736] = _7587; + uint16_t _7588 = (uint16_t)(228); + _curvea0[737] = _7588; + uint16_t _7589 = (uint16_t)(228); + _curvea0[738] = _7589; + uint16_t _7590 = (uint16_t)(228); + _curvea0[739] = _7590; + uint16_t _7591 = (uint16_t)(228); + _curvea0[740] = _7591; + uint16_t _7592 = (uint16_t)(228); + _curvea0[741] = _7592; + uint16_t _7593 = (uint16_t)(228); + _curvea0[742] = _7593; + uint16_t _7594 = (uint16_t)(229); + _curvea0[743] = _7594; + uint16_t _7595 = (uint16_t)(229); + _curvea0[744] = _7595; + uint16_t _7596 = (uint16_t)(229); + _curvea0[745] = _7596; + uint16_t _7597 = (uint16_t)(229); + _curvea0[746] = _7597; + uint16_t _7598 = (uint16_t)(229); + _curvea0[747] = _7598; + uint16_t _7599 = (uint16_t)(229); + _curvea0[748] = _7599; + uint16_t _7600 = (uint16_t)(229); + _curvea0[749] = _7600; + uint16_t _7601 = (uint16_t)(229); + _curvea0[750] = _7601; + uint16_t _7602 = (uint16_t)(230); + _curvea0[751] = _7602; + uint16_t _7603 = (uint16_t)(230); + _curvea0[752] = _7603; + uint16_t _7604 = (uint16_t)(230); + _curvea0[753] = _7604; + uint16_t _7605 = (uint16_t)(230); + _curvea0[754] = _7605; + uint16_t _7606 = (uint16_t)(230); + _curvea0[755] = _7606; + uint16_t _7607 = (uint16_t)(230); + _curvea0[756] = _7607; + uint16_t _7608 = (uint16_t)(230); + _curvea0[757] = _7608; + uint16_t _7609 = (uint16_t)(230); + _curvea0[758] = _7609; + uint16_t _7610 = (uint16_t)(231); + _curvea0[759] = _7610; + uint16_t _7611 = (uint16_t)(231); + _curvea0[760] = _7611; + uint16_t _7612 = (uint16_t)(231); + _curvea0[761] = _7612; + uint16_t _7613 = (uint16_t)(231); + _curvea0[762] = _7613; + uint16_t _7614 = (uint16_t)(231); + _curvea0[763] = _7614; + uint16_t _7615 = (uint16_t)(231); + _curvea0[764] = _7615; + uint16_t _7616 = (uint16_t)(231); + _curvea0[765] = _7616; + uint16_t _7617 = (uint16_t)(231); + _curvea0[766] = _7617; + uint16_t _7618 = (uint16_t)(231); + _curvea0[767] = _7618; + uint16_t _7619 = (uint16_t)(232); + _curvea0[768] = _7619; + uint16_t _7620 = (uint16_t)(232); + _curvea0[769] = _7620; + uint16_t _7621 = (uint16_t)(232); + _curvea0[770] = _7621; + uint16_t _7622 = (uint16_t)(232); + _curvea0[771] = _7622; + uint16_t _7623 = (uint16_t)(232); + _curvea0[772] = _7623; + uint16_t _7624 = (uint16_t)(232); + _curvea0[773] = _7624; + uint16_t _7625 = (uint16_t)(232); + _curvea0[774] = _7625; + uint16_t _7626 = (uint16_t)(232); + _curvea0[775] = _7626; + uint16_t _7627 = (uint16_t)(233); + _curvea0[776] = _7627; + uint16_t _7628 = (uint16_t)(233); + _curvea0[777] = _7628; + uint16_t _7629 = (uint16_t)(233); + _curvea0[778] = _7629; + uint16_t _7630 = (uint16_t)(233); + _curvea0[779] = _7630; + uint16_t _7631 = (uint16_t)(233); + _curvea0[780] = _7631; + uint16_t _7632 = (uint16_t)(233); + _curvea0[781] = _7632; + uint16_t _7633 = (uint16_t)(233); + _curvea0[782] = _7633; + uint16_t _7634 = (uint16_t)(233); + _curvea0[783] = _7634; + uint16_t _7635 = (uint16_t)(233); + _curvea0[784] = _7635; + uint16_t _7636 = (uint16_t)(234); + _curvea0[785] = _7636; + uint16_t _7637 = (uint16_t)(234); + _curvea0[786] = _7637; + uint16_t _7638 = (uint16_t)(234); + _curvea0[787] = _7638; + uint16_t _7639 = (uint16_t)(234); + _curvea0[788] = _7639; + uint16_t _7640 = (uint16_t)(234); + _curvea0[789] = _7640; + uint16_t _7641 = (uint16_t)(234); + _curvea0[790] = _7641; + uint16_t _7642 = (uint16_t)(234); + _curvea0[791] = _7642; + uint16_t _7643 = (uint16_t)(234); + _curvea0[792] = _7643; + uint16_t _7644 = (uint16_t)(234); + _curvea0[793] = _7644; + uint16_t _7645 = (uint16_t)(235); + _curvea0[794] = _7645; + uint16_t _7646 = (uint16_t)(235); + _curvea0[795] = _7646; + uint16_t _7647 = (uint16_t)(235); + _curvea0[796] = _7647; + uint16_t _7648 = (uint16_t)(235); + _curvea0[797] = _7648; + uint16_t _7649 = (uint16_t)(235); + _curvea0[798] = _7649; + uint16_t _7650 = (uint16_t)(235); + _curvea0[799] = _7650; + uint16_t _7651 = (uint16_t)(235); + _curvea0[800] = _7651; + uint16_t _7652 = (uint16_t)(235); + _curvea0[801] = _7652; + uint16_t _7653 = (uint16_t)(235); + _curvea0[802] = _7653; + uint16_t _7654 = (uint16_t)(236); + _curvea0[803] = _7654; + uint16_t _7655 = (uint16_t)(236); + _curvea0[804] = _7655; + uint16_t _7656 = (uint16_t)(236); + _curvea0[805] = _7656; + uint16_t _7657 = (uint16_t)(236); + _curvea0[806] = _7657; + uint16_t _7658 = (uint16_t)(236); + _curvea0[807] = _7658; + uint16_t _7659 = (uint16_t)(236); + _curvea0[808] = _7659; + uint16_t _7660 = (uint16_t)(236); + _curvea0[809] = _7660; + uint16_t _7661 = (uint16_t)(236); + _curvea0[810] = _7661; + uint16_t _7662 = (uint16_t)(236); + _curvea0[811] = _7662; + uint16_t _7663 = (uint16_t)(237); + _curvea0[812] = _7663; + uint16_t _7664 = (uint16_t)(237); + _curvea0[813] = _7664; + uint16_t _7665 = (uint16_t)(237); + _curvea0[814] = _7665; + uint16_t _7666 = (uint16_t)(237); + _curvea0[815] = _7666; + uint16_t _7667 = (uint16_t)(237); + _curvea0[816] = _7667; + uint16_t _7668 = (uint16_t)(237); + _curvea0[817] = _7668; + uint16_t _7669 = (uint16_t)(237); + _curvea0[818] = _7669; + uint16_t _7670 = (uint16_t)(237); + _curvea0[819] = _7670; + uint16_t _7671 = (uint16_t)(237); + _curvea0[820] = _7671; + uint16_t _7672 = (uint16_t)(237); + _curvea0[821] = _7672; + uint16_t _7673 = (uint16_t)(238); + _curvea0[822] = _7673; + uint16_t _7674 = (uint16_t)(238); + _curvea0[823] = _7674; + uint16_t _7675 = (uint16_t)(238); + _curvea0[824] = _7675; + uint16_t _7676 = (uint16_t)(238); + _curvea0[825] = _7676; + uint16_t _7677 = (uint16_t)(238); + _curvea0[826] = _7677; + uint16_t _7678 = (uint16_t)(238); + _curvea0[827] = _7678; + uint16_t _7679 = (uint16_t)(238); + _curvea0[828] = _7679; + uint16_t _7680 = (uint16_t)(238); + _curvea0[829] = _7680; + uint16_t _7681 = (uint16_t)(238); + _curvea0[830] = _7681; + uint16_t _7682 = (uint16_t)(239); + _curvea0[831] = _7682; + uint16_t _7683 = (uint16_t)(239); + _curvea0[832] = _7683; + uint16_t _7684 = (uint16_t)(239); + _curvea0[833] = _7684; + uint16_t _7685 = (uint16_t)(239); + _curvea0[834] = _7685; + uint16_t _7686 = (uint16_t)(239); + _curvea0[835] = _7686; + uint16_t _7687 = (uint16_t)(239); + _curvea0[836] = _7687; + uint16_t _7688 = (uint16_t)(239); + _curvea0[837] = _7688; + uint16_t _7689 = (uint16_t)(239); + _curvea0[838] = _7689; + uint16_t _7690 = (uint16_t)(239); + _curvea0[839] = _7690; + uint16_t _7691 = (uint16_t)(239); + _curvea0[840] = _7691; + uint16_t _7692 = (uint16_t)(240); + _curvea0[841] = _7692; + uint16_t _7693 = (uint16_t)(240); + _curvea0[842] = _7693; + uint16_t _7694 = (uint16_t)(240); + _curvea0[843] = _7694; + uint16_t _7695 = (uint16_t)(240); + _curvea0[844] = _7695; + uint16_t _7696 = (uint16_t)(240); + _curvea0[845] = _7696; + uint16_t _7697 = (uint16_t)(240); + _curvea0[846] = _7697; + uint16_t _7698 = (uint16_t)(240); + _curvea0[847] = _7698; + uint16_t _7699 = (uint16_t)(240); + _curvea0[848] = _7699; + uint16_t _7700 = (uint16_t)(240); + _curvea0[849] = _7700; + uint16_t _7701 = (uint16_t)(240); + _curvea0[850] = _7701; + uint16_t _7702 = (uint16_t)(241); + _curvea0[851] = _7702; + uint16_t _7703 = (uint16_t)(241); + _curvea0[852] = _7703; + uint16_t _7704 = (uint16_t)(241); + _curvea0[853] = _7704; + uint16_t _7705 = (uint16_t)(241); + _curvea0[854] = _7705; + uint16_t _7706 = (uint16_t)(241); + _curvea0[855] = _7706; + uint16_t _7707 = (uint16_t)(241); + _curvea0[856] = _7707; + uint16_t _7708 = (uint16_t)(241); + _curvea0[857] = _7708; + uint16_t _7709 = (uint16_t)(241); + _curvea0[858] = _7709; + uint16_t _7710 = (uint16_t)(241); + _curvea0[859] = _7710; + uint16_t _7711 = (uint16_t)(241); + _curvea0[860] = _7711; + uint16_t _7712 = (uint16_t)(242); + _curvea0[861] = _7712; + uint16_t _7713 = (uint16_t)(242); + _curvea0[862] = _7713; + uint16_t _7714 = (uint16_t)(242); + _curvea0[863] = _7714; + uint16_t _7715 = (uint16_t)(242); + _curvea0[864] = _7715; + uint16_t _7716 = (uint16_t)(242); + _curvea0[865] = _7716; + uint16_t _7717 = (uint16_t)(242); + _curvea0[866] = _7717; + uint16_t _7718 = (uint16_t)(242); + _curvea0[867] = _7718; + uint16_t _7719 = (uint16_t)(242); + _curvea0[868] = _7719; + uint16_t _7720 = (uint16_t)(242); + _curvea0[869] = _7720; + uint16_t _7721 = (uint16_t)(242); + _curvea0[870] = _7721; + uint16_t _7722 = (uint16_t)(243); + _curvea0[871] = _7722; + uint16_t _7723 = (uint16_t)(243); + _curvea0[872] = _7723; + uint16_t _7724 = (uint16_t)(243); + _curvea0[873] = _7724; + uint16_t _7725 = (uint16_t)(243); + _curvea0[874] = _7725; + uint16_t _7726 = (uint16_t)(243); + _curvea0[875] = _7726; + uint16_t _7727 = (uint16_t)(243); + _curvea0[876] = _7727; + uint16_t _7728 = (uint16_t)(243); + _curvea0[877] = _7728; + uint16_t _7729 = (uint16_t)(243); + _curvea0[878] = _7729; + uint16_t _7730 = (uint16_t)(243); + _curvea0[879] = _7730; + uint16_t _7731 = (uint16_t)(243); + _curvea0[880] = _7731; + uint16_t _7732 = (uint16_t)(244); + _curvea0[881] = _7732; + uint16_t _7733 = (uint16_t)(244); + _curvea0[882] = _7733; + uint16_t _7734 = (uint16_t)(244); + _curvea0[883] = _7734; + uint16_t _7735 = (uint16_t)(244); + _curvea0[884] = _7735; + uint16_t _7736 = (uint16_t)(244); + _curvea0[885] = _7736; + uint16_t _7737 = (uint16_t)(244); + _curvea0[886] = _7737; + uint16_t _7738 = (uint16_t)(244); + _curvea0[887] = _7738; + uint16_t _7739 = (uint16_t)(244); + _curvea0[888] = _7739; + uint16_t _7740 = (uint16_t)(244); + _curvea0[889] = _7740; + uint16_t _7741 = (uint16_t)(244); + _curvea0[890] = _7741; + uint16_t _7742 = (uint16_t)(244); + _curvea0[891] = _7742; + uint16_t _7743 = (uint16_t)(245); + _curvea0[892] = _7743; + uint16_t _7744 = (uint16_t)(245); + _curvea0[893] = _7744; + uint16_t _7745 = (uint16_t)(245); + _curvea0[894] = _7745; + uint16_t _7746 = (uint16_t)(245); + _curvea0[895] = _7746; + uint16_t _7747 = (uint16_t)(245); + _curvea0[896] = _7747; + uint16_t _7748 = (uint16_t)(245); + _curvea0[897] = _7748; + uint16_t _7749 = (uint16_t)(245); + _curvea0[898] = _7749; + uint16_t _7750 = (uint16_t)(245); + _curvea0[899] = _7750; + uint16_t _7751 = (uint16_t)(245); + _curvea0[900] = _7751; + uint16_t _7752 = (uint16_t)(245); + _curvea0[901] = _7752; + uint16_t _7753 = (uint16_t)(245); + _curvea0[902] = _7753; + uint16_t _7754 = (uint16_t)(246); + _curvea0[903] = _7754; + uint16_t _7755 = (uint16_t)(246); + _curvea0[904] = _7755; + uint16_t _7756 = (uint16_t)(246); + _curvea0[905] = _7756; + uint16_t _7757 = (uint16_t)(246); + _curvea0[906] = _7757; + uint16_t _7758 = (uint16_t)(246); + _curvea0[907] = _7758; + uint16_t _7759 = (uint16_t)(246); + _curvea0[908] = _7759; + uint16_t _7760 = (uint16_t)(246); + _curvea0[909] = _7760; + uint16_t _7761 = (uint16_t)(246); + _curvea0[910] = _7761; + uint16_t _7762 = (uint16_t)(246); + _curvea0[911] = _7762; + uint16_t _7763 = (uint16_t)(246); + _curvea0[912] = _7763; + uint16_t _7764 = (uint16_t)(246); + _curvea0[913] = _7764; + uint16_t _7765 = (uint16_t)(247); + _curvea0[914] = _7765; + uint16_t _7766 = (uint16_t)(247); + _curvea0[915] = _7766; + uint16_t _7767 = (uint16_t)(247); + _curvea0[916] = _7767; + uint16_t _7768 = (uint16_t)(247); + _curvea0[917] = _7768; + uint16_t _7769 = (uint16_t)(247); + _curvea0[918] = _7769; + uint16_t _7770 = (uint16_t)(247); + _curvea0[919] = _7770; + uint16_t _7771 = (uint16_t)(247); + _curvea0[920] = _7771; + uint16_t _7772 = (uint16_t)(247); + _curvea0[921] = _7772; + uint16_t _7773 = (uint16_t)(247); + _curvea0[922] = _7773; + uint16_t _7774 = (uint16_t)(247); + _curvea0[923] = _7774; + uint16_t _7775 = (uint16_t)(247); + _curvea0[924] = _7775; + uint16_t _7776 = (uint16_t)(248); + _curvea0[925] = _7776; + uint16_t _7777 = (uint16_t)(248); + _curvea0[926] = _7777; + uint16_t _7778 = (uint16_t)(248); + _curvea0[927] = _7778; + uint16_t _7779 = (uint16_t)(248); + _curvea0[928] = _7779; + uint16_t _7780 = (uint16_t)(248); + _curvea0[929] = _7780; + uint16_t _7781 = (uint16_t)(248); + _curvea0[930] = _7781; + uint16_t _7782 = (uint16_t)(248); + _curvea0[931] = _7782; + uint16_t _7783 = (uint16_t)(248); + _curvea0[932] = _7783; + uint16_t _7784 = (uint16_t)(248); + _curvea0[933] = _7784; + uint16_t _7785 = (uint16_t)(248); + _curvea0[934] = _7785; + uint16_t _7786 = (uint16_t)(248); + _curvea0[935] = _7786; + uint16_t _7787 = (uint16_t)(249); + _curvea0[936] = _7787; + uint16_t _7788 = (uint16_t)(249); + _curvea0[937] = _7788; + uint16_t _7789 = (uint16_t)(249); + _curvea0[938] = _7789; + uint16_t _7790 = (uint16_t)(249); + _curvea0[939] = _7790; + uint16_t _7791 = (uint16_t)(249); + _curvea0[940] = _7791; + uint16_t _7792 = (uint16_t)(249); + _curvea0[941] = _7792; + uint16_t _7793 = (uint16_t)(249); + _curvea0[942] = _7793; + uint16_t _7794 = (uint16_t)(249); + _curvea0[943] = _7794; + uint16_t _7795 = (uint16_t)(249); + _curvea0[944] = _7795; + uint16_t _7796 = (uint16_t)(249); + _curvea0[945] = _7796; + uint16_t _7797 = (uint16_t)(249); + _curvea0[946] = _7797; + uint16_t _7798 = (uint16_t)(249); + _curvea0[947] = _7798; + uint16_t _7799 = (uint16_t)(250); + _curvea0[948] = _7799; + uint16_t _7800 = (uint16_t)(250); + _curvea0[949] = _7800; + uint16_t _7801 = (uint16_t)(250); + _curvea0[950] = _7801; + uint16_t _7802 = (uint16_t)(250); + _curvea0[951] = _7802; + uint16_t _7803 = (uint16_t)(250); + _curvea0[952] = _7803; + uint16_t _7804 = (uint16_t)(250); + _curvea0[953] = _7804; + uint16_t _7805 = (uint16_t)(250); + _curvea0[954] = _7805; + uint16_t _7806 = (uint16_t)(250); + _curvea0[955] = _7806; + uint16_t _7807 = (uint16_t)(250); + _curvea0[956] = _7807; + uint16_t _7808 = (uint16_t)(250); + _curvea0[957] = _7808; + uint16_t _7809 = (uint16_t)(250); + _curvea0[958] = _7809; + uint16_t _7810 = (uint16_t)(250); + _curvea0[959] = _7810; + uint16_t _7811 = (uint16_t)(251); + _curvea0[960] = _7811; + uint16_t _7812 = (uint16_t)(251); + _curvea0[961] = _7812; + uint16_t _7813 = (uint16_t)(251); + _curvea0[962] = _7813; + uint16_t _7814 = (uint16_t)(251); + _curvea0[963] = _7814; + uint16_t _7815 = (uint16_t)(251); + _curvea0[964] = _7815; + uint16_t _7816 = (uint16_t)(251); + _curvea0[965] = _7816; + uint16_t _7817 = (uint16_t)(251); + _curvea0[966] = _7817; + uint16_t _7818 = (uint16_t)(251); + _curvea0[967] = _7818; + uint16_t _7819 = (uint16_t)(251); + _curvea0[968] = _7819; + uint16_t _7820 = (uint16_t)(251); + _curvea0[969] = _7820; + uint16_t _7821 = (uint16_t)(251); + _curvea0[970] = _7821; + uint16_t _7822 = (uint16_t)(251); + _curvea0[971] = _7822; + uint16_t _7823 = (uint16_t)(252); + _curvea0[972] = _7823; + uint16_t _7824 = (uint16_t)(252); + _curvea0[973] = _7824; + uint16_t _7825 = (uint16_t)(252); + _curvea0[974] = _7825; + uint16_t _7826 = (uint16_t)(252); + _curvea0[975] = _7826; + uint16_t _7827 = (uint16_t)(252); + _curvea0[976] = _7827; + uint16_t _7828 = (uint16_t)(252); + _curvea0[977] = _7828; + uint16_t _7829 = (uint16_t)(252); + _curvea0[978] = _7829; + uint16_t _7830 = (uint16_t)(252); + _curvea0[979] = _7830; + uint16_t _7831 = (uint16_t)(252); + _curvea0[980] = _7831; + uint16_t _7832 = (uint16_t)(252); + _curvea0[981] = _7832; + uint16_t _7833 = (uint16_t)(252); + _curvea0[982] = _7833; + uint16_t _7834 = (uint16_t)(252); + _curvea0[983] = _7834; + uint16_t _7835 = (uint16_t)(252); + _curvea0[984] = _7835; + uint16_t _7836 = (uint16_t)(253); + _curvea0[985] = _7836; + uint16_t _7837 = (uint16_t)(253); + _curvea0[986] = _7837; + uint16_t _7838 = (uint16_t)(253); + _curvea0[987] = _7838; + uint16_t _7839 = (uint16_t)(253); + _curvea0[988] = _7839; + uint16_t _7840 = (uint16_t)(253); + _curvea0[989] = _7840; + uint16_t _7841 = (uint16_t)(253); + _curvea0[990] = _7841; + uint16_t _7842 = (uint16_t)(253); + _curvea0[991] = _7842; + uint16_t _7843 = (uint16_t)(253); + _curvea0[992] = _7843; + uint16_t _7844 = (uint16_t)(253); + _curvea0[993] = _7844; + uint16_t _7845 = (uint16_t)(253); + _curvea0[994] = _7845; + uint16_t _7846 = (uint16_t)(253); + _curvea0[995] = _7846; + uint16_t _7847 = (uint16_t)(253); + _curvea0[996] = _7847; + uint16_t _7848 = (uint16_t)(253); + _curvea0[997] = _7848; + uint16_t _7849 = (uint16_t)(254); + _curvea0[998] = _7849; + uint16_t _7850 = (uint16_t)(254); + _curvea0[999] = _7850; + uint16_t _7851 = (uint16_t)(254); + _curvea0[1000] = _7851; + uint16_t _7852 = (uint16_t)(254); + _curvea0[1001] = _7852; + uint16_t _7853 = (uint16_t)(254); + _curvea0[1002] = _7853; + uint16_t _7854 = (uint16_t)(254); + _curvea0[1003] = _7854; + uint16_t _7855 = (uint16_t)(254); + _curvea0[1004] = _7855; + uint16_t _7856 = (uint16_t)(254); + _curvea0[1005] = _7856; + uint16_t _7857 = (uint16_t)(254); + _curvea0[1006] = _7857; + uint16_t _7858 = (uint16_t)(254); + _curvea0[1007] = _7858; + uint16_t _7859 = (uint16_t)(254); + _curvea0[1008] = _7859; + uint16_t _7860 = (uint16_t)(254); + _curvea0[1009] = _7860; + uint16_t _7861 = (uint16_t)(254); + _curvea0[1010] = _7861; + uint16_t _7862 = (uint16_t)(255); + _curvea0[1011] = _7862; + uint16_t _7863 = (uint16_t)(255); + _curvea0[1012] = _7863; + uint16_t _7864 = (uint16_t)(255); + _curvea0[1013] = _7864; + uint16_t _7865 = (uint16_t)(255); + _curvea0[1014] = _7865; + uint16_t _7866 = (uint16_t)(255); + _curvea0[1015] = _7866; + uint16_t _7867 = (uint16_t)(255); + _curvea0[1016] = _7867; + uint16_t _7868 = (uint16_t)(255); + _curvea0[1017] = _7868; + uint16_t _7869 = (uint16_t)(255); + _curvea0[1018] = _7869; + uint16_t _7870 = (uint16_t)(255); + _curvea0[1019] = _7870; + uint16_t _7871 = (uint16_t)(255); + _curvea0[1020] = _7871; + uint16_t _7872 = (uint16_t)(255); + _curvea0[1021] = _7872; + uint16_t _7873 = (uint16_t)(255); + _curvea0[1022] = _7873; + uint16_t _7874 = (uint16_t)(255); + _curvea0[1023] = _7874; + + int16_t _7875 = (int16_t)(1023); + int16_t _7876 = min(_corrected_stencil_5, _7875); + int16_t _7877 = (int16_t)(0); + int16_t _7878 = max(_7876, _7877); + uint16_t _7879 = (uint16_t)(_7878); + int32_t _7880 = (int32_t)(_7879); + uint16_t _7881 = ((const uint16_t *)_curvea0)[_7880]; + return _7881; +} + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_5(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_6 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _7899 = (uint16_t)(0); + _curvea0[0] = _7899; + uint16_t _7900 = (uint16_t)(4); + _curvea0[1] = _7900; + uint16_t _7901 = (uint16_t)(7); + _curvea0[2] = _7901; + uint16_t _7902 = (uint16_t)(8); + _curvea0[3] = _7902; + uint16_t _7903 = (uint16_t)(10); + _curvea0[4] = _7903; + uint16_t _7904 = (uint16_t)(11); + _curvea0[5] = _7904; + uint16_t _7905 = (uint16_t)(12); + _curvea0[6] = _7905; + uint16_t _7906 = (uint16_t)(13); + _curvea0[7] = _7906; + uint16_t _7907 = (uint16_t)(14); + _curvea0[8] = _7907; + uint16_t _7908 = (uint16_t)(15); + _curvea0[9] = _7908; + uint16_t _7909 = (uint16_t)(16); + _curvea0[10] = _7909; + uint16_t _7910 = (uint16_t)(17); + _curvea0[11] = _7910; + uint16_t _7911 = (uint16_t)(18); + _curvea0[12] = _7911; + uint16_t _7912 = (uint16_t)(19); + _curvea0[13] = _7912; + uint16_t _7913 = (uint16_t)(20); + _curvea0[14] = _7913; + uint16_t _7914 = (uint16_t)(21); + _curvea0[15] = _7914; + uint16_t _7915 = (uint16_t)(22); + _curvea0[16] = _7915; + uint16_t _7916 = (uint16_t)(22); + _curvea0[17] = _7916; + uint16_t _7917 = (uint16_t)(23); + _curvea0[18] = _7917; + uint16_t _7918 = (uint16_t)(24); + _curvea0[19] = _7918; + uint16_t _7919 = (uint16_t)(25); + _curvea0[20] = _7919; + uint16_t _7920 = (uint16_t)(25); + _curvea0[21] = _7920; + uint16_t _7921 = (uint16_t)(26); + _curvea0[22] = _7921; + uint16_t _7922 = (uint16_t)(27); + _curvea0[23] = _7922; + uint16_t _7923 = (uint16_t)(27); + _curvea0[24] = _7923; + uint16_t _7924 = (uint16_t)(28); + _curvea0[25] = _7924; + uint16_t _7925 = (uint16_t)(29); + _curvea0[26] = _7925; + uint16_t _7926 = (uint16_t)(29); + _curvea0[27] = _7926; + uint16_t _7927 = (uint16_t)(30); + _curvea0[28] = _7927; + uint16_t _7928 = (uint16_t)(31); + _curvea0[29] = _7928; + uint16_t _7929 = (uint16_t)(31); + _curvea0[30] = _7929; + uint16_t _7930 = (uint16_t)(32); + _curvea0[31] = _7930; + uint16_t _7931 = (uint16_t)(33); + _curvea0[32] = _7931; + uint16_t _7932 = (uint16_t)(33); + _curvea0[33] = _7932; + uint16_t _7933 = (uint16_t)(34); + _curvea0[34] = _7933; + uint16_t _7934 = (uint16_t)(34); + _curvea0[35] = _7934; + uint16_t _7935 = (uint16_t)(35); + _curvea0[36] = _7935; + uint16_t _7936 = (uint16_t)(36); + _curvea0[37] = _7936; + uint16_t _7937 = (uint16_t)(36); + _curvea0[38] = _7937; + uint16_t _7938 = (uint16_t)(37); + _curvea0[39] = _7938; + uint16_t _7939 = (uint16_t)(37); + _curvea0[40] = _7939; + uint16_t _7940 = (uint16_t)(38); + _curvea0[41] = _7940; + uint16_t _7941 = (uint16_t)(39); + _curvea0[42] = _7941; + uint16_t _7942 = (uint16_t)(39); + _curvea0[43] = _7942; + uint16_t _7943 = (uint16_t)(40); + _curvea0[44] = _7943; + uint16_t _7944 = (uint16_t)(40); + _curvea0[45] = _7944; + uint16_t _7945 = (uint16_t)(41); + _curvea0[46] = _7945; + uint16_t _7946 = (uint16_t)(41); + _curvea0[47] = _7946; + uint16_t _7947 = (uint16_t)(42); + _curvea0[48] = _7947; + uint16_t _7948 = (uint16_t)(42); + _curvea0[49] = _7948; + uint16_t _7949 = (uint16_t)(43); + _curvea0[50] = _7949; + uint16_t _7950 = (uint16_t)(44); + _curvea0[51] = _7950; + uint16_t _7951 = (uint16_t)(44); + _curvea0[52] = _7951; + uint16_t _7952 = (uint16_t)(45); + _curvea0[53] = _7952; + uint16_t _7953 = (uint16_t)(45); + _curvea0[54] = _7953; + uint16_t _7954 = (uint16_t)(46); + _curvea0[55] = _7954; + uint16_t _7955 = (uint16_t)(46); + _curvea0[56] = _7955; + uint16_t _7956 = (uint16_t)(47); + _curvea0[57] = _7956; + uint16_t _7957 = (uint16_t)(47); + _curvea0[58] = _7957; + uint16_t _7958 = (uint16_t)(48); + _curvea0[59] = _7958; + uint16_t _7959 = (uint16_t)(48); + _curvea0[60] = _7959; + uint16_t _7960 = (uint16_t)(49); + _curvea0[61] = _7960; + uint16_t _7961 = (uint16_t)(49); + _curvea0[62] = _7961; + uint16_t _7962 = (uint16_t)(50); + _curvea0[63] = _7962; + uint16_t _7963 = (uint16_t)(50); + _curvea0[64] = _7963; + uint16_t _7964 = (uint16_t)(51); + _curvea0[65] = _7964; + uint16_t _7965 = (uint16_t)(51); + _curvea0[66] = _7965; + uint16_t _7966 = (uint16_t)(52); + _curvea0[67] = _7966; + uint16_t _7967 = (uint16_t)(52); + _curvea0[68] = _7967; + uint16_t _7968 = (uint16_t)(53); + _curvea0[69] = _7968; + uint16_t _7969 = (uint16_t)(53); + _curvea0[70] = _7969; + uint16_t _7970 = (uint16_t)(54); + _curvea0[71] = _7970; + uint16_t _7971 = (uint16_t)(54); + _curvea0[72] = _7971; + uint16_t _7972 = (uint16_t)(55); + _curvea0[73] = _7972; + uint16_t _7973 = (uint16_t)(55); + _curvea0[74] = _7973; + uint16_t _7974 = (uint16_t)(56); + _curvea0[75] = _7974; + uint16_t _7975 = (uint16_t)(56); + _curvea0[76] = _7975; + uint16_t _7976 = (uint16_t)(57); + _curvea0[77] = _7976; + uint16_t _7977 = (uint16_t)(57); + _curvea0[78] = _7977; + uint16_t _7978 = (uint16_t)(58); + _curvea0[79] = _7978; + uint16_t _7979 = (uint16_t)(58); + _curvea0[80] = _7979; + uint16_t _7980 = (uint16_t)(58); + _curvea0[81] = _7980; + uint16_t _7981 = (uint16_t)(59); + _curvea0[82] = _7981; + uint16_t _7982 = (uint16_t)(59); + _curvea0[83] = _7982; + uint16_t _7983 = (uint16_t)(60); + _curvea0[84] = _7983; + uint16_t _7984 = (uint16_t)(60); + _curvea0[85] = _7984; + uint16_t _7985 = (uint16_t)(61); + _curvea0[86] = _7985; + uint16_t _7986 = (uint16_t)(61); + _curvea0[87] = _7986; + uint16_t _7987 = (uint16_t)(62); + _curvea0[88] = _7987; + uint16_t _7988 = (uint16_t)(62); + _curvea0[89] = _7988; + uint16_t _7989 = (uint16_t)(63); + _curvea0[90] = _7989; + uint16_t _7990 = (uint16_t)(63); + _curvea0[91] = _7990; + uint16_t _7991 = (uint16_t)(64); + _curvea0[92] = _7991; + uint16_t _7992 = (uint16_t)(64); + _curvea0[93] = _7992; + uint16_t _7993 = (uint16_t)(64); + _curvea0[94] = _7993; + uint16_t _7994 = (uint16_t)(65); + _curvea0[95] = _7994; + uint16_t _7995 = (uint16_t)(65); + _curvea0[96] = _7995; + uint16_t _7996 = (uint16_t)(66); + _curvea0[97] = _7996; + uint16_t _7997 = (uint16_t)(66); + _curvea0[98] = _7997; + uint16_t _7998 = (uint16_t)(67); + _curvea0[99] = _7998; + uint16_t _7999 = (uint16_t)(67); + _curvea0[100] = _7999; + uint16_t _8000 = (uint16_t)(68); + _curvea0[101] = _8000; + uint16_t _8001 = (uint16_t)(68); + _curvea0[102] = _8001; + uint16_t _8002 = (uint16_t)(68); + _curvea0[103] = _8002; + uint16_t _8003 = (uint16_t)(69); + _curvea0[104] = _8003; + uint16_t _8004 = (uint16_t)(69); + _curvea0[105] = _8004; + uint16_t _8005 = (uint16_t)(70); + _curvea0[106] = _8005; + uint16_t _8006 = (uint16_t)(70); + _curvea0[107] = _8006; + uint16_t _8007 = (uint16_t)(71); + _curvea0[108] = _8007; + uint16_t _8008 = (uint16_t)(71); + _curvea0[109] = _8008; + uint16_t _8009 = (uint16_t)(71); + _curvea0[110] = _8009; + uint16_t _8010 = (uint16_t)(72); + _curvea0[111] = _8010; + uint16_t _8011 = (uint16_t)(72); + _curvea0[112] = _8011; + uint16_t _8012 = (uint16_t)(73); + _curvea0[113] = _8012; + uint16_t _8013 = (uint16_t)(73); + _curvea0[114] = _8013; + uint16_t _8014 = (uint16_t)(74); + _curvea0[115] = _8014; + uint16_t _8015 = (uint16_t)(74); + _curvea0[116] = _8015; + uint16_t _8016 = (uint16_t)(74); + _curvea0[117] = _8016; + uint16_t _8017 = (uint16_t)(75); + _curvea0[118] = _8017; + uint16_t _8018 = (uint16_t)(75); + _curvea0[119] = _8018; + uint16_t _8019 = (uint16_t)(76); + _curvea0[120] = _8019; + uint16_t _8020 = (uint16_t)(76); + _curvea0[121] = _8020; + uint16_t _8021 = (uint16_t)(77); + _curvea0[122] = _8021; + uint16_t _8022 = (uint16_t)(77); + _curvea0[123] = _8022; + uint16_t _8023 = (uint16_t)(77); + _curvea0[124] = _8023; + uint16_t _8024 = (uint16_t)(78); + _curvea0[125] = _8024; + uint16_t _8025 = (uint16_t)(78); + _curvea0[126] = _8025; + uint16_t _8026 = (uint16_t)(79); + _curvea0[127] = _8026; + uint16_t _8027 = (uint16_t)(79); + _curvea0[128] = _8027; + uint16_t _8028 = (uint16_t)(79); + _curvea0[129] = _8028; + uint16_t _8029 = (uint16_t)(80); + _curvea0[130] = _8029; + uint16_t _8030 = (uint16_t)(80); + _curvea0[131] = _8030; + uint16_t _8031 = (uint16_t)(81); + _curvea0[132] = _8031; + uint16_t _8032 = (uint16_t)(81); + _curvea0[133] = _8032; + uint16_t _8033 = (uint16_t)(82); + _curvea0[134] = _8033; + uint16_t _8034 = (uint16_t)(82); + _curvea0[135] = _8034; + uint16_t _8035 = (uint16_t)(82); + _curvea0[136] = _8035; + uint16_t _8036 = (uint16_t)(83); + _curvea0[137] = _8036; + uint16_t _8037 = (uint16_t)(83); + _curvea0[138] = _8037; + uint16_t _8038 = (uint16_t)(84); + _curvea0[139] = _8038; + uint16_t _8039 = (uint16_t)(84); + _curvea0[140] = _8039; + uint16_t _8040 = (uint16_t)(84); + _curvea0[141] = _8040; + uint16_t _8041 = (uint16_t)(85); + _curvea0[142] = _8041; + uint16_t _8042 = (uint16_t)(85); + _curvea0[143] = _8042; + uint16_t _8043 = (uint16_t)(86); + _curvea0[144] = _8043; + uint16_t _8044 = (uint16_t)(86); + _curvea0[145] = _8044; + uint16_t _8045 = (uint16_t)(86); + _curvea0[146] = _8045; + uint16_t _8046 = (uint16_t)(87); + _curvea0[147] = _8046; + uint16_t _8047 = (uint16_t)(87); + _curvea0[148] = _8047; + uint16_t _8048 = (uint16_t)(88); + _curvea0[149] = _8048; + uint16_t _8049 = (uint16_t)(88); + _curvea0[150] = _8049; + uint16_t _8050 = (uint16_t)(88); + _curvea0[151] = _8050; + uint16_t _8051 = (uint16_t)(89); + _curvea0[152] = _8051; + uint16_t _8052 = (uint16_t)(89); + _curvea0[153] = _8052; + uint16_t _8053 = (uint16_t)(90); + _curvea0[154] = _8053; + uint16_t _8054 = (uint16_t)(90); + _curvea0[155] = _8054; + uint16_t _8055 = (uint16_t)(90); + _curvea0[156] = _8055; + uint16_t _8056 = (uint16_t)(91); + _curvea0[157] = _8056; + uint16_t _8057 = (uint16_t)(91); + _curvea0[158] = _8057; + uint16_t _8058 = (uint16_t)(92); + _curvea0[159] = _8058; + uint16_t _8059 = (uint16_t)(92); + _curvea0[160] = _8059; + uint16_t _8060 = (uint16_t)(92); + _curvea0[161] = _8060; + uint16_t _8061 = (uint16_t)(93); + _curvea0[162] = _8061; + uint16_t _8062 = (uint16_t)(93); + _curvea0[163] = _8062; + uint16_t _8063 = (uint16_t)(93); + _curvea0[164] = _8063; + uint16_t _8064 = (uint16_t)(94); + _curvea0[165] = _8064; + uint16_t _8065 = (uint16_t)(94); + _curvea0[166] = _8065; + uint16_t _8066 = (uint16_t)(95); + _curvea0[167] = _8066; + uint16_t _8067 = (uint16_t)(95); + _curvea0[168] = _8067; + uint16_t _8068 = (uint16_t)(95); + _curvea0[169] = _8068; + uint16_t _8069 = (uint16_t)(96); + _curvea0[170] = _8069; + uint16_t _8070 = (uint16_t)(96); + _curvea0[171] = _8070; + uint16_t _8071 = (uint16_t)(97); + _curvea0[172] = _8071; + uint16_t _8072 = (uint16_t)(97); + _curvea0[173] = _8072; + uint16_t _8073 = (uint16_t)(97); + _curvea0[174] = _8073; + uint16_t _8074 = (uint16_t)(98); + _curvea0[175] = _8074; + uint16_t _8075 = (uint16_t)(98); + _curvea0[176] = _8075; + uint16_t _8076 = (uint16_t)(99); + _curvea0[177] = _8076; + uint16_t _8077 = (uint16_t)(99); + _curvea0[178] = _8077; + uint16_t _8078 = (uint16_t)(99); + _curvea0[179] = _8078; + uint16_t _8079 = (uint16_t)(100); + _curvea0[180] = _8079; + uint16_t _8080 = (uint16_t)(100); + _curvea0[181] = _8080; + uint16_t _8081 = (uint16_t)(100); + _curvea0[182] = _8081; + uint16_t _8082 = (uint16_t)(101); + _curvea0[183] = _8082; + uint16_t _8083 = (uint16_t)(101); + _curvea0[184] = _8083; + uint16_t _8084 = (uint16_t)(102); + _curvea0[185] = _8084; + uint16_t _8085 = (uint16_t)(102); + _curvea0[186] = _8085; + uint16_t _8086 = (uint16_t)(102); + _curvea0[187] = _8086; + uint16_t _8087 = (uint16_t)(103); + _curvea0[188] = _8087; + uint16_t _8088 = (uint16_t)(103); + _curvea0[189] = _8088; + uint16_t _8089 = (uint16_t)(103); + _curvea0[190] = _8089; + uint16_t _8090 = (uint16_t)(104); + _curvea0[191] = _8090; + uint16_t _8091 = (uint16_t)(104); + _curvea0[192] = _8091; + uint16_t _8092 = (uint16_t)(105); + _curvea0[193] = _8092; + uint16_t _8093 = (uint16_t)(105); + _curvea0[194] = _8093; + uint16_t _8094 = (uint16_t)(105); + _curvea0[195] = _8094; + uint16_t _8095 = (uint16_t)(106); + _curvea0[196] = _8095; + uint16_t _8096 = (uint16_t)(106); + _curvea0[197] = _8096; + uint16_t _8097 = (uint16_t)(106); + _curvea0[198] = _8097; + uint16_t _8098 = (uint16_t)(107); + _curvea0[199] = _8098; + uint16_t _8099 = (uint16_t)(107); + _curvea0[200] = _8099; + uint16_t _8100 = (uint16_t)(108); + _curvea0[201] = _8100; + uint16_t _8101 = (uint16_t)(108); + _curvea0[202] = _8101; + uint16_t _8102 = (uint16_t)(108); + _curvea0[203] = _8102; + uint16_t _8103 = (uint16_t)(109); + _curvea0[204] = _8103; + uint16_t _8104 = (uint16_t)(109); + _curvea0[205] = _8104; + uint16_t _8105 = (uint16_t)(109); + _curvea0[206] = _8105; + uint16_t _8106 = (uint16_t)(110); + _curvea0[207] = _8106; + uint16_t _8107 = (uint16_t)(110); + _curvea0[208] = _8107; + uint16_t _8108 = (uint16_t)(111); + _curvea0[209] = _8108; + uint16_t _8109 = (uint16_t)(111); + _curvea0[210] = _8109; + uint16_t _8110 = (uint16_t)(111); + _curvea0[211] = _8110; + uint16_t _8111 = (uint16_t)(112); + _curvea0[212] = _8111; + uint16_t _8112 = (uint16_t)(112); + _curvea0[213] = _8112; + uint16_t _8113 = (uint16_t)(112); + _curvea0[214] = _8113; + uint16_t _8114 = (uint16_t)(113); + _curvea0[215] = _8114; + uint16_t _8115 = (uint16_t)(113); + _curvea0[216] = _8115; + uint16_t _8116 = (uint16_t)(113); + _curvea0[217] = _8116; + uint16_t _8117 = (uint16_t)(114); + _curvea0[218] = _8117; + uint16_t _8118 = (uint16_t)(114); + _curvea0[219] = _8118; + uint16_t _8119 = (uint16_t)(115); + _curvea0[220] = _8119; + uint16_t _8120 = (uint16_t)(115); + _curvea0[221] = _8120; + uint16_t _8121 = (uint16_t)(115); + _curvea0[222] = _8121; + uint16_t _8122 = (uint16_t)(116); + _curvea0[223] = _8122; + uint16_t _8123 = (uint16_t)(116); + _curvea0[224] = _8123; + uint16_t _8124 = (uint16_t)(116); + _curvea0[225] = _8124; + uint16_t _8125 = (uint16_t)(117); + _curvea0[226] = _8125; + uint16_t _8126 = (uint16_t)(117); + _curvea0[227] = _8126; + uint16_t _8127 = (uint16_t)(117); + _curvea0[228] = _8127; + uint16_t _8128 = (uint16_t)(118); + _curvea0[229] = _8128; + uint16_t _8129 = (uint16_t)(118); + _curvea0[230] = _8129; + uint16_t _8130 = (uint16_t)(119); + _curvea0[231] = _8130; + uint16_t _8131 = (uint16_t)(119); + _curvea0[232] = _8131; + uint16_t _8132 = (uint16_t)(119); + _curvea0[233] = _8132; + uint16_t _8133 = (uint16_t)(120); + _curvea0[234] = _8133; + uint16_t _8134 = (uint16_t)(120); + _curvea0[235] = _8134; + uint16_t _8135 = (uint16_t)(120); + _curvea0[236] = _8135; + uint16_t _8136 = (uint16_t)(121); + _curvea0[237] = _8136; + uint16_t _8137 = (uint16_t)(121); + _curvea0[238] = _8137; + uint16_t _8138 = (uint16_t)(121); + _curvea0[239] = _8138; + uint16_t _8139 = (uint16_t)(122); + _curvea0[240] = _8139; + uint16_t _8140 = (uint16_t)(122); + _curvea0[241] = _8140; + uint16_t _8141 = (uint16_t)(123); + _curvea0[242] = _8141; + uint16_t _8142 = (uint16_t)(123); + _curvea0[243] = _8142; + uint16_t _8143 = (uint16_t)(123); + _curvea0[244] = _8143; + uint16_t _8144 = (uint16_t)(124); + _curvea0[245] = _8144; + uint16_t _8145 = (uint16_t)(124); + _curvea0[246] = _8145; + uint16_t _8146 = (uint16_t)(124); + _curvea0[247] = _8146; + uint16_t _8147 = (uint16_t)(125); + _curvea0[248] = _8147; + uint16_t _8148 = (uint16_t)(125); + _curvea0[249] = _8148; + uint16_t _8149 = (uint16_t)(125); + _curvea0[250] = _8149; + uint16_t _8150 = (uint16_t)(126); + _curvea0[251] = _8150; + uint16_t _8151 = (uint16_t)(126); + _curvea0[252] = _8151; + uint16_t _8152 = (uint16_t)(126); + _curvea0[253] = _8152; + uint16_t _8153 = (uint16_t)(127); + _curvea0[254] = _8153; + uint16_t _8154 = (uint16_t)(127); + _curvea0[255] = _8154; + uint16_t _8155 = (uint16_t)(128); + _curvea0[256] = _8155; + uint16_t _8156 = (uint16_t)(128); + _curvea0[257] = _8156; + uint16_t _8157 = (uint16_t)(128); + _curvea0[258] = _8157; + uint16_t _8158 = (uint16_t)(129); + _curvea0[259] = _8158; + uint16_t _8159 = (uint16_t)(129); + _curvea0[260] = _8159; + uint16_t _8160 = (uint16_t)(129); + _curvea0[261] = _8160; + uint16_t _8161 = (uint16_t)(130); + _curvea0[262] = _8161; + uint16_t _8162 = (uint16_t)(130); + _curvea0[263] = _8162; + uint16_t _8163 = (uint16_t)(130); + _curvea0[264] = _8163; + uint16_t _8164 = (uint16_t)(131); + _curvea0[265] = _8164; + uint16_t _8165 = (uint16_t)(131); + _curvea0[266] = _8165; + uint16_t _8166 = (uint16_t)(131); + _curvea0[267] = _8166; + uint16_t _8167 = (uint16_t)(132); + _curvea0[268] = _8167; + uint16_t _8168 = (uint16_t)(132); + _curvea0[269] = _8168; + uint16_t _8169 = (uint16_t)(132); + _curvea0[270] = _8169; + uint16_t _8170 = (uint16_t)(133); + _curvea0[271] = _8170; + uint16_t _8171 = (uint16_t)(133); + _curvea0[272] = _8171; + uint16_t _8172 = (uint16_t)(133); + _curvea0[273] = _8172; + uint16_t _8173 = (uint16_t)(134); + _curvea0[274] = _8173; + uint16_t _8174 = (uint16_t)(134); + _curvea0[275] = _8174; + uint16_t _8175 = (uint16_t)(134); + _curvea0[276] = _8175; + uint16_t _8176 = (uint16_t)(135); + _curvea0[277] = _8176; + uint16_t _8177 = (uint16_t)(135); + _curvea0[278] = _8177; + uint16_t _8178 = (uint16_t)(135); + _curvea0[279] = _8178; + uint16_t _8179 = (uint16_t)(136); + _curvea0[280] = _8179; + uint16_t _8180 = (uint16_t)(136); + _curvea0[281] = _8180; + uint16_t _8181 = (uint16_t)(136); + _curvea0[282] = _8181; + uint16_t _8182 = (uint16_t)(137); + _curvea0[283] = _8182; + uint16_t _8183 = (uint16_t)(137); + _curvea0[284] = _8183; + uint16_t _8184 = (uint16_t)(137); + _curvea0[285] = _8184; + uint16_t _8185 = (uint16_t)(138); + _curvea0[286] = _8185; + uint16_t _8186 = (uint16_t)(138); + _curvea0[287] = _8186; + uint16_t _8187 = (uint16_t)(138); + _curvea0[288] = _8187; + uint16_t _8188 = (uint16_t)(139); + _curvea0[289] = _8188; + uint16_t _8189 = (uint16_t)(139); + _curvea0[290] = _8189; + uint16_t _8190 = (uint16_t)(139); + _curvea0[291] = _8190; + uint16_t _8191 = (uint16_t)(140); + _curvea0[292] = _8191; + uint16_t _8192 = (uint16_t)(140); + _curvea0[293] = _8192; + uint16_t _8193 = (uint16_t)(140); + _curvea0[294] = _8193; + uint16_t _8194 = (uint16_t)(141); + _curvea0[295] = _8194; + uint16_t _8195 = (uint16_t)(141); + _curvea0[296] = _8195; + uint16_t _8196 = (uint16_t)(141); + _curvea0[297] = _8196; + uint16_t _8197 = (uint16_t)(141); + _curvea0[298] = _8197; + uint16_t _8198 = (uint16_t)(142); + _curvea0[299] = _8198; + uint16_t _8199 = (uint16_t)(142); + _curvea0[300] = _8199; + uint16_t _8200 = (uint16_t)(142); + _curvea0[301] = _8200; + uint16_t _8201 = (uint16_t)(143); + _curvea0[302] = _8201; + uint16_t _8202 = (uint16_t)(143); + _curvea0[303] = _8202; + uint16_t _8203 = (uint16_t)(143); + _curvea0[304] = _8203; + uint16_t _8204 = (uint16_t)(144); + _curvea0[305] = _8204; + uint16_t _8205 = (uint16_t)(144); + _curvea0[306] = _8205; + uint16_t _8206 = (uint16_t)(144); + _curvea0[307] = _8206; + uint16_t _8207 = (uint16_t)(145); + _curvea0[308] = _8207; + uint16_t _8208 = (uint16_t)(145); + _curvea0[309] = _8208; + uint16_t _8209 = (uint16_t)(145); + _curvea0[310] = _8209; + uint16_t _8210 = (uint16_t)(145); + _curvea0[311] = _8210; + uint16_t _8211 = (uint16_t)(146); + _curvea0[312] = _8211; + uint16_t _8212 = (uint16_t)(146); + _curvea0[313] = _8212; + uint16_t _8213 = (uint16_t)(146); + _curvea0[314] = _8213; + uint16_t _8214 = (uint16_t)(147); + _curvea0[315] = _8214; + uint16_t _8215 = (uint16_t)(147); + _curvea0[316] = _8215; + uint16_t _8216 = (uint16_t)(147); + _curvea0[317] = _8216; + uint16_t _8217 = (uint16_t)(148); + _curvea0[318] = _8217; + uint16_t _8218 = (uint16_t)(148); + _curvea0[319] = _8218; + uint16_t _8219 = (uint16_t)(148); + _curvea0[320] = _8219; + uint16_t _8220 = (uint16_t)(148); + _curvea0[321] = _8220; + uint16_t _8221 = (uint16_t)(149); + _curvea0[322] = _8221; + uint16_t _8222 = (uint16_t)(149); + _curvea0[323] = _8222; + uint16_t _8223 = (uint16_t)(149); + _curvea0[324] = _8223; + uint16_t _8224 = (uint16_t)(150); + _curvea0[325] = _8224; + uint16_t _8225 = (uint16_t)(150); + _curvea0[326] = _8225; + uint16_t _8226 = (uint16_t)(150); + _curvea0[327] = _8226; + uint16_t _8227 = (uint16_t)(150); + _curvea0[328] = _8227; + uint16_t _8228 = (uint16_t)(151); + _curvea0[329] = _8228; + uint16_t _8229 = (uint16_t)(151); + _curvea0[330] = _8229; + uint16_t _8230 = (uint16_t)(151); + _curvea0[331] = _8230; + uint16_t _8231 = (uint16_t)(152); + _curvea0[332] = _8231; + uint16_t _8232 = (uint16_t)(152); + _curvea0[333] = _8232; + uint16_t _8233 = (uint16_t)(152); + _curvea0[334] = _8233; + uint16_t _8234 = (uint16_t)(152); + _curvea0[335] = _8234; + uint16_t _8235 = (uint16_t)(153); + _curvea0[336] = _8235; + uint16_t _8236 = (uint16_t)(153); + _curvea0[337] = _8236; + uint16_t _8237 = (uint16_t)(153); + _curvea0[338] = _8237; + uint16_t _8238 = (uint16_t)(154); + _curvea0[339] = _8238; + uint16_t _8239 = (uint16_t)(154); + _curvea0[340] = _8239; + uint16_t _8240 = (uint16_t)(154); + _curvea0[341] = _8240; + uint16_t _8241 = (uint16_t)(154); + _curvea0[342] = _8241; + uint16_t _8242 = (uint16_t)(155); + _curvea0[343] = _8242; + uint16_t _8243 = (uint16_t)(155); + _curvea0[344] = _8243; + uint16_t _8244 = (uint16_t)(155); + _curvea0[345] = _8244; + uint16_t _8245 = (uint16_t)(156); + _curvea0[346] = _8245; + uint16_t _8246 = (uint16_t)(156); + _curvea0[347] = _8246; + uint16_t _8247 = (uint16_t)(156); + _curvea0[348] = _8247; + uint16_t _8248 = (uint16_t)(156); + _curvea0[349] = _8248; + uint16_t _8249 = (uint16_t)(157); + _curvea0[350] = _8249; + uint16_t _8250 = (uint16_t)(157); + _curvea0[351] = _8250; + uint16_t _8251 = (uint16_t)(157); + _curvea0[352] = _8251; + uint16_t _8252 = (uint16_t)(157); + _curvea0[353] = _8252; + uint16_t _8253 = (uint16_t)(158); + _curvea0[354] = _8253; + uint16_t _8254 = (uint16_t)(158); + _curvea0[355] = _8254; + uint16_t _8255 = (uint16_t)(158); + _curvea0[356] = _8255; + uint16_t _8256 = (uint16_t)(159); + _curvea0[357] = _8256; + uint16_t _8257 = (uint16_t)(159); + _curvea0[358] = _8257; + uint16_t _8258 = (uint16_t)(159); + _curvea0[359] = _8258; + uint16_t _8259 = (uint16_t)(159); + _curvea0[360] = _8259; + uint16_t _8260 = (uint16_t)(160); + _curvea0[361] = _8260; + uint16_t _8261 = (uint16_t)(160); + _curvea0[362] = _8261; + uint16_t _8262 = (uint16_t)(160); + _curvea0[363] = _8262; + uint16_t _8263 = (uint16_t)(160); + _curvea0[364] = _8263; + uint16_t _8264 = (uint16_t)(161); + _curvea0[365] = _8264; + uint16_t _8265 = (uint16_t)(161); + _curvea0[366] = _8265; + uint16_t _8266 = (uint16_t)(161); + _curvea0[367] = _8266; + uint16_t _8267 = (uint16_t)(161); + _curvea0[368] = _8267; + uint16_t _8268 = (uint16_t)(162); + _curvea0[369] = _8268; + uint16_t _8269 = (uint16_t)(162); + _curvea0[370] = _8269; + uint16_t _8270 = (uint16_t)(162); + _curvea0[371] = _8270; + uint16_t _8271 = (uint16_t)(162); + _curvea0[372] = _8271; + uint16_t _8272 = (uint16_t)(163); + _curvea0[373] = _8272; + uint16_t _8273 = (uint16_t)(163); + _curvea0[374] = _8273; + uint16_t _8274 = (uint16_t)(163); + _curvea0[375] = _8274; + uint16_t _8275 = (uint16_t)(163); + _curvea0[376] = _8275; + uint16_t _8276 = (uint16_t)(164); + _curvea0[377] = _8276; + uint16_t _8277 = (uint16_t)(164); + _curvea0[378] = _8277; + uint16_t _8278 = (uint16_t)(164); + _curvea0[379] = _8278; + uint16_t _8279 = (uint16_t)(164); + _curvea0[380] = _8279; + uint16_t _8280 = (uint16_t)(165); + _curvea0[381] = _8280; + uint16_t _8281 = (uint16_t)(165); + _curvea0[382] = _8281; + uint16_t _8282 = (uint16_t)(165); + _curvea0[383] = _8282; + uint16_t _8283 = (uint16_t)(166); + _curvea0[384] = _8283; + uint16_t _8284 = (uint16_t)(166); + _curvea0[385] = _8284; + uint16_t _8285 = (uint16_t)(166); + _curvea0[386] = _8285; + uint16_t _8286 = (uint16_t)(166); + _curvea0[387] = _8286; + uint16_t _8287 = (uint16_t)(167); + _curvea0[388] = _8287; + uint16_t _8288 = (uint16_t)(167); + _curvea0[389] = _8288; + uint16_t _8289 = (uint16_t)(167); + _curvea0[390] = _8289; + uint16_t _8290 = (uint16_t)(167); + _curvea0[391] = _8290; + uint16_t _8291 = (uint16_t)(167); + _curvea0[392] = _8291; + uint16_t _8292 = (uint16_t)(168); + _curvea0[393] = _8292; + uint16_t _8293 = (uint16_t)(168); + _curvea0[394] = _8293; + uint16_t _8294 = (uint16_t)(168); + _curvea0[395] = _8294; + uint16_t _8295 = (uint16_t)(168); + _curvea0[396] = _8295; + uint16_t _8296 = (uint16_t)(169); + _curvea0[397] = _8296; + uint16_t _8297 = (uint16_t)(169); + _curvea0[398] = _8297; + uint16_t _8298 = (uint16_t)(169); + _curvea0[399] = _8298; + uint16_t _8299 = (uint16_t)(169); + _curvea0[400] = _8299; + uint16_t _8300 = (uint16_t)(170); + _curvea0[401] = _8300; + uint16_t _8301 = (uint16_t)(170); + _curvea0[402] = _8301; + uint16_t _8302 = (uint16_t)(170); + _curvea0[403] = _8302; + uint16_t _8303 = (uint16_t)(170); + _curvea0[404] = _8303; + uint16_t _8304 = (uint16_t)(171); + _curvea0[405] = _8304; + uint16_t _8305 = (uint16_t)(171); + _curvea0[406] = _8305; + uint16_t _8306 = (uint16_t)(171); + _curvea0[407] = _8306; + uint16_t _8307 = (uint16_t)(171); + _curvea0[408] = _8307; + uint16_t _8308 = (uint16_t)(172); + _curvea0[409] = _8308; + uint16_t _8309 = (uint16_t)(172); + _curvea0[410] = _8309; + uint16_t _8310 = (uint16_t)(172); + _curvea0[411] = _8310; + uint16_t _8311 = (uint16_t)(172); + _curvea0[412] = _8311; + uint16_t _8312 = (uint16_t)(173); + _curvea0[413] = _8312; + uint16_t _8313 = (uint16_t)(173); + _curvea0[414] = _8313; + uint16_t _8314 = (uint16_t)(173); + _curvea0[415] = _8314; + uint16_t _8315 = (uint16_t)(173); + _curvea0[416] = _8315; + uint16_t _8316 = (uint16_t)(173); + _curvea0[417] = _8316; + uint16_t _8317 = (uint16_t)(174); + _curvea0[418] = _8317; + uint16_t _8318 = (uint16_t)(174); + _curvea0[419] = _8318; + uint16_t _8319 = (uint16_t)(174); + _curvea0[420] = _8319; + uint16_t _8320 = (uint16_t)(174); + _curvea0[421] = _8320; + uint16_t _8321 = (uint16_t)(175); + _curvea0[422] = _8321; + uint16_t _8322 = (uint16_t)(175); + _curvea0[423] = _8322; + uint16_t _8323 = (uint16_t)(175); + _curvea0[424] = _8323; + uint16_t _8324 = (uint16_t)(175); + _curvea0[425] = _8324; + uint16_t _8325 = (uint16_t)(176); + _curvea0[426] = _8325; + uint16_t _8326 = (uint16_t)(176); + _curvea0[427] = _8326; + uint16_t _8327 = (uint16_t)(176); + _curvea0[428] = _8327; + uint16_t _8328 = (uint16_t)(176); + _curvea0[429] = _8328; + uint16_t _8329 = (uint16_t)(176); + _curvea0[430] = _8329; + uint16_t _8330 = (uint16_t)(177); + _curvea0[431] = _8330; + uint16_t _8331 = (uint16_t)(177); + _curvea0[432] = _8331; + uint16_t _8332 = (uint16_t)(177); + _curvea0[433] = _8332; + uint16_t _8333 = (uint16_t)(177); + _curvea0[434] = _8333; + uint16_t _8334 = (uint16_t)(178); + _curvea0[435] = _8334; + uint16_t _8335 = (uint16_t)(178); + _curvea0[436] = _8335; + uint16_t _8336 = (uint16_t)(178); + _curvea0[437] = _8336; + uint16_t _8337 = (uint16_t)(178); + _curvea0[438] = _8337; + uint16_t _8338 = (uint16_t)(178); + _curvea0[439] = _8338; + uint16_t _8339 = (uint16_t)(179); + _curvea0[440] = _8339; + uint16_t _8340 = (uint16_t)(179); + _curvea0[441] = _8340; + uint16_t _8341 = (uint16_t)(179); + _curvea0[442] = _8341; + uint16_t _8342 = (uint16_t)(179); + _curvea0[443] = _8342; + uint16_t _8343 = (uint16_t)(180); + _curvea0[444] = _8343; + uint16_t _8344 = (uint16_t)(180); + _curvea0[445] = _8344; + uint16_t _8345 = (uint16_t)(180); + _curvea0[446] = _8345; + uint16_t _8346 = (uint16_t)(180); + _curvea0[447] = _8346; + uint16_t _8347 = (uint16_t)(180); + _curvea0[448] = _8347; + uint16_t _8348 = (uint16_t)(181); + _curvea0[449] = _8348; + uint16_t _8349 = (uint16_t)(181); + _curvea0[450] = _8349; + uint16_t _8350 = (uint16_t)(181); + _curvea0[451] = _8350; + uint16_t _8351 = (uint16_t)(181); + _curvea0[452] = _8351; + uint16_t _8352 = (uint16_t)(181); + _curvea0[453] = _8352; + uint16_t _8353 = (uint16_t)(182); + _curvea0[454] = _8353; + uint16_t _8354 = (uint16_t)(182); + _curvea0[455] = _8354; + uint16_t _8355 = (uint16_t)(182); + _curvea0[456] = _8355; + uint16_t _8356 = (uint16_t)(182); + _curvea0[457] = _8356; + uint16_t _8357 = (uint16_t)(183); + _curvea0[458] = _8357; + uint16_t _8358 = (uint16_t)(183); + _curvea0[459] = _8358; + uint16_t _8359 = (uint16_t)(183); + _curvea0[460] = _8359; + uint16_t _8360 = (uint16_t)(183); + _curvea0[461] = _8360; + uint16_t _8361 = (uint16_t)(183); + _curvea0[462] = _8361; + uint16_t _8362 = (uint16_t)(184); + _curvea0[463] = _8362; + uint16_t _8363 = (uint16_t)(184); + _curvea0[464] = _8363; + uint16_t _8364 = (uint16_t)(184); + _curvea0[465] = _8364; + uint16_t _8365 = (uint16_t)(184); + _curvea0[466] = _8365; + uint16_t _8366 = (uint16_t)(184); + _curvea0[467] = _8366; + uint16_t _8367 = (uint16_t)(185); + _curvea0[468] = _8367; + uint16_t _8368 = (uint16_t)(185); + _curvea0[469] = _8368; + uint16_t _8369 = (uint16_t)(185); + _curvea0[470] = _8369; + uint16_t _8370 = (uint16_t)(185); + _curvea0[471] = _8370; + uint16_t _8371 = (uint16_t)(185); + _curvea0[472] = _8371; + uint16_t _8372 = (uint16_t)(186); + _curvea0[473] = _8372; + uint16_t _8373 = (uint16_t)(186); + _curvea0[474] = _8373; + uint16_t _8374 = (uint16_t)(186); + _curvea0[475] = _8374; + uint16_t _8375 = (uint16_t)(186); + _curvea0[476] = _8375; + uint16_t _8376 = (uint16_t)(187); + _curvea0[477] = _8376; + uint16_t _8377 = (uint16_t)(187); + _curvea0[478] = _8377; + uint16_t _8378 = (uint16_t)(187); + _curvea0[479] = _8378; + uint16_t _8379 = (uint16_t)(187); + _curvea0[480] = _8379; + uint16_t _8380 = (uint16_t)(187); + _curvea0[481] = _8380; + uint16_t _8381 = (uint16_t)(188); + _curvea0[482] = _8381; + uint16_t _8382 = (uint16_t)(188); + _curvea0[483] = _8382; + uint16_t _8383 = (uint16_t)(188); + _curvea0[484] = _8383; + uint16_t _8384 = (uint16_t)(188); + _curvea0[485] = _8384; + uint16_t _8385 = (uint16_t)(188); + _curvea0[486] = _8385; + uint16_t _8386 = (uint16_t)(189); + _curvea0[487] = _8386; + uint16_t _8387 = (uint16_t)(189); + _curvea0[488] = _8387; + uint16_t _8388 = (uint16_t)(189); + _curvea0[489] = _8388; + uint16_t _8389 = (uint16_t)(189); + _curvea0[490] = _8389; + uint16_t _8390 = (uint16_t)(189); + _curvea0[491] = _8390; + uint16_t _8391 = (uint16_t)(190); + _curvea0[492] = _8391; + uint16_t _8392 = (uint16_t)(190); + _curvea0[493] = _8392; + uint16_t _8393 = (uint16_t)(190); + _curvea0[494] = _8393; + uint16_t _8394 = (uint16_t)(190); + _curvea0[495] = _8394; + uint16_t _8395 = (uint16_t)(190); + _curvea0[496] = _8395; + uint16_t _8396 = (uint16_t)(190); + _curvea0[497] = _8396; + uint16_t _8397 = (uint16_t)(191); + _curvea0[498] = _8397; + uint16_t _8398 = (uint16_t)(191); + _curvea0[499] = _8398; + uint16_t _8399 = (uint16_t)(191); + _curvea0[500] = _8399; + uint16_t _8400 = (uint16_t)(191); + _curvea0[501] = _8400; + uint16_t _8401 = (uint16_t)(191); + _curvea0[502] = _8401; + uint16_t _8402 = (uint16_t)(192); + _curvea0[503] = _8402; + uint16_t _8403 = (uint16_t)(192); + _curvea0[504] = _8403; + uint16_t _8404 = (uint16_t)(192); + _curvea0[505] = _8404; + uint16_t _8405 = (uint16_t)(192); + _curvea0[506] = _8405; + uint16_t _8406 = (uint16_t)(192); + _curvea0[507] = _8406; + uint16_t _8407 = (uint16_t)(193); + _curvea0[508] = _8407; + uint16_t _8408 = (uint16_t)(193); + _curvea0[509] = _8408; + uint16_t _8409 = (uint16_t)(193); + _curvea0[510] = _8409; + uint16_t _8410 = (uint16_t)(193); + _curvea0[511] = _8410; + uint16_t _8411 = (uint16_t)(193); + _curvea0[512] = _8411; + uint16_t _8412 = (uint16_t)(194); + _curvea0[513] = _8412; + uint16_t _8413 = (uint16_t)(194); + _curvea0[514] = _8413; + uint16_t _8414 = (uint16_t)(194); + _curvea0[515] = _8414; + uint16_t _8415 = (uint16_t)(194); + _curvea0[516] = _8415; + uint16_t _8416 = (uint16_t)(194); + _curvea0[517] = _8416; + uint16_t _8417 = (uint16_t)(195); + _curvea0[518] = _8417; + uint16_t _8418 = (uint16_t)(195); + _curvea0[519] = _8418; + uint16_t _8419 = (uint16_t)(195); + _curvea0[520] = _8419; + uint16_t _8420 = (uint16_t)(195); + _curvea0[521] = _8420; + uint16_t _8421 = (uint16_t)(195); + _curvea0[522] = _8421; + uint16_t _8422 = (uint16_t)(195); + _curvea0[523] = _8422; + uint16_t _8423 = (uint16_t)(196); + _curvea0[524] = _8423; + uint16_t _8424 = (uint16_t)(196); + _curvea0[525] = _8424; + uint16_t _8425 = (uint16_t)(196); + _curvea0[526] = _8425; + uint16_t _8426 = (uint16_t)(196); + _curvea0[527] = _8426; + uint16_t _8427 = (uint16_t)(196); + _curvea0[528] = _8427; + uint16_t _8428 = (uint16_t)(197); + _curvea0[529] = _8428; + uint16_t _8429 = (uint16_t)(197); + _curvea0[530] = _8429; + uint16_t _8430 = (uint16_t)(197); + _curvea0[531] = _8430; + uint16_t _8431 = (uint16_t)(197); + _curvea0[532] = _8431; + uint16_t _8432 = (uint16_t)(197); + _curvea0[533] = _8432; + uint16_t _8433 = (uint16_t)(197); + _curvea0[534] = _8433; + uint16_t _8434 = (uint16_t)(198); + _curvea0[535] = _8434; + uint16_t _8435 = (uint16_t)(198); + _curvea0[536] = _8435; + uint16_t _8436 = (uint16_t)(198); + _curvea0[537] = _8436; + uint16_t _8437 = (uint16_t)(198); + _curvea0[538] = _8437; + uint16_t _8438 = (uint16_t)(198); + _curvea0[539] = _8438; + uint16_t _8439 = (uint16_t)(199); + _curvea0[540] = _8439; + uint16_t _8440 = (uint16_t)(199); + _curvea0[541] = _8440; + uint16_t _8441 = (uint16_t)(199); + _curvea0[542] = _8441; + uint16_t _8442 = (uint16_t)(199); + _curvea0[543] = _8442; + uint16_t _8443 = (uint16_t)(199); + _curvea0[544] = _8443; + uint16_t _8444 = (uint16_t)(199); + _curvea0[545] = _8444; + uint16_t _8445 = (uint16_t)(200); + _curvea0[546] = _8445; + uint16_t _8446 = (uint16_t)(200); + _curvea0[547] = _8446; + uint16_t _8447 = (uint16_t)(200); + _curvea0[548] = _8447; + uint16_t _8448 = (uint16_t)(200); + _curvea0[549] = _8448; + uint16_t _8449 = (uint16_t)(200); + _curvea0[550] = _8449; + uint16_t _8450 = (uint16_t)(200); + _curvea0[551] = _8450; + uint16_t _8451 = (uint16_t)(201); + _curvea0[552] = _8451; + uint16_t _8452 = (uint16_t)(201); + _curvea0[553] = _8452; + uint16_t _8453 = (uint16_t)(201); + _curvea0[554] = _8453; + uint16_t _8454 = (uint16_t)(201); + _curvea0[555] = _8454; + uint16_t _8455 = (uint16_t)(201); + _curvea0[556] = _8455; + uint16_t _8456 = (uint16_t)(202); + _curvea0[557] = _8456; + uint16_t _8457 = (uint16_t)(202); + _curvea0[558] = _8457; + uint16_t _8458 = (uint16_t)(202); + _curvea0[559] = _8458; + uint16_t _8459 = (uint16_t)(202); + _curvea0[560] = _8459; + uint16_t _8460 = (uint16_t)(202); + _curvea0[561] = _8460; + uint16_t _8461 = (uint16_t)(202); + _curvea0[562] = _8461; + uint16_t _8462 = (uint16_t)(203); + _curvea0[563] = _8462; + uint16_t _8463 = (uint16_t)(203); + _curvea0[564] = _8463; + uint16_t _8464 = (uint16_t)(203); + _curvea0[565] = _8464; + uint16_t _8465 = (uint16_t)(203); + _curvea0[566] = _8465; + uint16_t _8466 = (uint16_t)(203); + _curvea0[567] = _8466; + uint16_t _8467 = (uint16_t)(203); + _curvea0[568] = _8467; + uint16_t _8468 = (uint16_t)(204); + _curvea0[569] = _8468; + uint16_t _8469 = (uint16_t)(204); + _curvea0[570] = _8469; + uint16_t _8470 = (uint16_t)(204); + _curvea0[571] = _8470; + uint16_t _8471 = (uint16_t)(204); + _curvea0[572] = _8471; + uint16_t _8472 = (uint16_t)(204); + _curvea0[573] = _8472; + uint16_t _8473 = (uint16_t)(204); + _curvea0[574] = _8473; + uint16_t _8474 = (uint16_t)(205); + _curvea0[575] = _8474; + uint16_t _8475 = (uint16_t)(205); + _curvea0[576] = _8475; + uint16_t _8476 = (uint16_t)(205); + _curvea0[577] = _8476; + uint16_t _8477 = (uint16_t)(205); + _curvea0[578] = _8477; + uint16_t _8478 = (uint16_t)(205); + _curvea0[579] = _8478; + uint16_t _8479 = (uint16_t)(205); + _curvea0[580] = _8479; + uint16_t _8480 = (uint16_t)(206); + _curvea0[581] = _8480; + uint16_t _8481 = (uint16_t)(206); + _curvea0[582] = _8481; + uint16_t _8482 = (uint16_t)(206); + _curvea0[583] = _8482; + uint16_t _8483 = (uint16_t)(206); + _curvea0[584] = _8483; + uint16_t _8484 = (uint16_t)(206); + _curvea0[585] = _8484; + uint16_t _8485 = (uint16_t)(206); + _curvea0[586] = _8485; + uint16_t _8486 = (uint16_t)(207); + _curvea0[587] = _8486; + uint16_t _8487 = (uint16_t)(207); + _curvea0[588] = _8487; + uint16_t _8488 = (uint16_t)(207); + _curvea0[589] = _8488; + uint16_t _8489 = (uint16_t)(207); + _curvea0[590] = _8489; + uint16_t _8490 = (uint16_t)(207); + _curvea0[591] = _8490; + uint16_t _8491 = (uint16_t)(207); + _curvea0[592] = _8491; + uint16_t _8492 = (uint16_t)(208); + _curvea0[593] = _8492; + uint16_t _8493 = (uint16_t)(208); + _curvea0[594] = _8493; + uint16_t _8494 = (uint16_t)(208); + _curvea0[595] = _8494; + uint16_t _8495 = (uint16_t)(208); + _curvea0[596] = _8495; + uint16_t _8496 = (uint16_t)(208); + _curvea0[597] = _8496; + uint16_t _8497 = (uint16_t)(208); + _curvea0[598] = _8497; + uint16_t _8498 = (uint16_t)(209); + _curvea0[599] = _8498; + uint16_t _8499 = (uint16_t)(209); + _curvea0[600] = _8499; + uint16_t _8500 = (uint16_t)(209); + _curvea0[601] = _8500; + uint16_t _8501 = (uint16_t)(209); + _curvea0[602] = _8501; + uint16_t _8502 = (uint16_t)(209); + _curvea0[603] = _8502; + uint16_t _8503 = (uint16_t)(209); + _curvea0[604] = _8503; + uint16_t _8504 = (uint16_t)(209); + _curvea0[605] = _8504; + uint16_t _8505 = (uint16_t)(210); + _curvea0[606] = _8505; + uint16_t _8506 = (uint16_t)(210); + _curvea0[607] = _8506; + uint16_t _8507 = (uint16_t)(210); + _curvea0[608] = _8507; + uint16_t _8508 = (uint16_t)(210); + _curvea0[609] = _8508; + uint16_t _8509 = (uint16_t)(210); + _curvea0[610] = _8509; + uint16_t _8510 = (uint16_t)(210); + _curvea0[611] = _8510; + uint16_t _8511 = (uint16_t)(211); + _curvea0[612] = _8511; + uint16_t _8512 = (uint16_t)(211); + _curvea0[613] = _8512; + uint16_t _8513 = (uint16_t)(211); + _curvea0[614] = _8513; + uint16_t _8514 = (uint16_t)(211); + _curvea0[615] = _8514; + uint16_t _8515 = (uint16_t)(211); + _curvea0[616] = _8515; + uint16_t _8516 = (uint16_t)(211); + _curvea0[617] = _8516; + uint16_t _8517 = (uint16_t)(211); + _curvea0[618] = _8517; + uint16_t _8518 = (uint16_t)(212); + _curvea0[619] = _8518; + uint16_t _8519 = (uint16_t)(212); + _curvea0[620] = _8519; + uint16_t _8520 = (uint16_t)(212); + _curvea0[621] = _8520; + uint16_t _8521 = (uint16_t)(212); + _curvea0[622] = _8521; + uint16_t _8522 = (uint16_t)(212); + _curvea0[623] = _8522; + uint16_t _8523 = (uint16_t)(212); + _curvea0[624] = _8523; + uint16_t _8524 = (uint16_t)(213); + _curvea0[625] = _8524; + uint16_t _8525 = (uint16_t)(213); + _curvea0[626] = _8525; + uint16_t _8526 = (uint16_t)(213); + _curvea0[627] = _8526; + uint16_t _8527 = (uint16_t)(213); + _curvea0[628] = _8527; + uint16_t _8528 = (uint16_t)(213); + _curvea0[629] = _8528; + uint16_t _8529 = (uint16_t)(213); + _curvea0[630] = _8529; + uint16_t _8530 = (uint16_t)(213); + _curvea0[631] = _8530; + uint16_t _8531 = (uint16_t)(214); + _curvea0[632] = _8531; + uint16_t _8532 = (uint16_t)(214); + _curvea0[633] = _8532; + uint16_t _8533 = (uint16_t)(214); + _curvea0[634] = _8533; + uint16_t _8534 = (uint16_t)(214); + _curvea0[635] = _8534; + uint16_t _8535 = (uint16_t)(214); + _curvea0[636] = _8535; + uint16_t _8536 = (uint16_t)(214); + _curvea0[637] = _8536; + uint16_t _8537 = (uint16_t)(214); + _curvea0[638] = _8537; + uint16_t _8538 = (uint16_t)(215); + _curvea0[639] = _8538; + uint16_t _8539 = (uint16_t)(215); + _curvea0[640] = _8539; + uint16_t _8540 = (uint16_t)(215); + _curvea0[641] = _8540; + uint16_t _8541 = (uint16_t)(215); + _curvea0[642] = _8541; + uint16_t _8542 = (uint16_t)(215); + _curvea0[643] = _8542; + uint16_t _8543 = (uint16_t)(215); + _curvea0[644] = _8543; + uint16_t _8544 = (uint16_t)(216); + _curvea0[645] = _8544; + uint16_t _8545 = (uint16_t)(216); + _curvea0[646] = _8545; + uint16_t _8546 = (uint16_t)(216); + _curvea0[647] = _8546; + uint16_t _8547 = (uint16_t)(216); + _curvea0[648] = _8547; + uint16_t _8548 = (uint16_t)(216); + _curvea0[649] = _8548; + uint16_t _8549 = (uint16_t)(216); + _curvea0[650] = _8549; + uint16_t _8550 = (uint16_t)(216); + _curvea0[651] = _8550; + uint16_t _8551 = (uint16_t)(217); + _curvea0[652] = _8551; + uint16_t _8552 = (uint16_t)(217); + _curvea0[653] = _8552; + uint16_t _8553 = (uint16_t)(217); + _curvea0[654] = _8553; + uint16_t _8554 = (uint16_t)(217); + _curvea0[655] = _8554; + uint16_t _8555 = (uint16_t)(217); + _curvea0[656] = _8555; + uint16_t _8556 = (uint16_t)(217); + _curvea0[657] = _8556; + uint16_t _8557 = (uint16_t)(217); + _curvea0[658] = _8557; + uint16_t _8558 = (uint16_t)(218); + _curvea0[659] = _8558; + uint16_t _8559 = (uint16_t)(218); + _curvea0[660] = _8559; + uint16_t _8560 = (uint16_t)(218); + _curvea0[661] = _8560; + uint16_t _8561 = (uint16_t)(218); + _curvea0[662] = _8561; + uint16_t _8562 = (uint16_t)(218); + _curvea0[663] = _8562; + uint16_t _8563 = (uint16_t)(218); + _curvea0[664] = _8563; + uint16_t _8564 = (uint16_t)(218); + _curvea0[665] = _8564; + uint16_t _8565 = (uint16_t)(219); + _curvea0[666] = _8565; + uint16_t _8566 = (uint16_t)(219); + _curvea0[667] = _8566; + uint16_t _8567 = (uint16_t)(219); + _curvea0[668] = _8567; + uint16_t _8568 = (uint16_t)(219); + _curvea0[669] = _8568; + uint16_t _8569 = (uint16_t)(219); + _curvea0[670] = _8569; + uint16_t _8570 = (uint16_t)(219); + _curvea0[671] = _8570; + uint16_t _8571 = (uint16_t)(219); + _curvea0[672] = _8571; + uint16_t _8572 = (uint16_t)(220); + _curvea0[673] = _8572; + uint16_t _8573 = (uint16_t)(220); + _curvea0[674] = _8573; + uint16_t _8574 = (uint16_t)(220); + _curvea0[675] = _8574; + uint16_t _8575 = (uint16_t)(220); + _curvea0[676] = _8575; + uint16_t _8576 = (uint16_t)(220); + _curvea0[677] = _8576; + uint16_t _8577 = (uint16_t)(220); + _curvea0[678] = _8577; + uint16_t _8578 = (uint16_t)(220); + _curvea0[679] = _8578; + uint16_t _8579 = (uint16_t)(220); + _curvea0[680] = _8579; + uint16_t _8580 = (uint16_t)(221); + _curvea0[681] = _8580; + uint16_t _8581 = (uint16_t)(221); + _curvea0[682] = _8581; + uint16_t _8582 = (uint16_t)(221); + _curvea0[683] = _8582; + uint16_t _8583 = (uint16_t)(221); + _curvea0[684] = _8583; + uint16_t _8584 = (uint16_t)(221); + _curvea0[685] = _8584; + uint16_t _8585 = (uint16_t)(221); + _curvea0[686] = _8585; + uint16_t _8586 = (uint16_t)(221); + _curvea0[687] = _8586; + uint16_t _8587 = (uint16_t)(222); + _curvea0[688] = _8587; + uint16_t _8588 = (uint16_t)(222); + _curvea0[689] = _8588; + uint16_t _8589 = (uint16_t)(222); + _curvea0[690] = _8589; + uint16_t _8590 = (uint16_t)(222); + _curvea0[691] = _8590; + uint16_t _8591 = (uint16_t)(222); + _curvea0[692] = _8591; + uint16_t _8592 = (uint16_t)(222); + _curvea0[693] = _8592; + uint16_t _8593 = (uint16_t)(222); + _curvea0[694] = _8593; + uint16_t _8594 = (uint16_t)(223); + _curvea0[695] = _8594; + uint16_t _8595 = (uint16_t)(223); + _curvea0[696] = _8595; + uint16_t _8596 = (uint16_t)(223); + _curvea0[697] = _8596; + uint16_t _8597 = (uint16_t)(223); + _curvea0[698] = _8597; + uint16_t _8598 = (uint16_t)(223); + _curvea0[699] = _8598; + uint16_t _8599 = (uint16_t)(223); + _curvea0[700] = _8599; + uint16_t _8600 = (uint16_t)(223); + _curvea0[701] = _8600; + uint16_t _8601 = (uint16_t)(223); + _curvea0[702] = _8601; + uint16_t _8602 = (uint16_t)(224); + _curvea0[703] = _8602; + uint16_t _8603 = (uint16_t)(224); + _curvea0[704] = _8603; + uint16_t _8604 = (uint16_t)(224); + _curvea0[705] = _8604; + uint16_t _8605 = (uint16_t)(224); + _curvea0[706] = _8605; + uint16_t _8606 = (uint16_t)(224); + _curvea0[707] = _8606; + uint16_t _8607 = (uint16_t)(224); + _curvea0[708] = _8607; + uint16_t _8608 = (uint16_t)(224); + _curvea0[709] = _8608; + uint16_t _8609 = (uint16_t)(224); + _curvea0[710] = _8609; + uint16_t _8610 = (uint16_t)(225); + _curvea0[711] = _8610; + uint16_t _8611 = (uint16_t)(225); + _curvea0[712] = _8611; + uint16_t _8612 = (uint16_t)(225); + _curvea0[713] = _8612; + uint16_t _8613 = (uint16_t)(225); + _curvea0[714] = _8613; + uint16_t _8614 = (uint16_t)(225); + _curvea0[715] = _8614; + uint16_t _8615 = (uint16_t)(225); + _curvea0[716] = _8615; + uint16_t _8616 = (uint16_t)(225); + _curvea0[717] = _8616; + uint16_t _8617 = (uint16_t)(226); + _curvea0[718] = _8617; + uint16_t _8618 = (uint16_t)(226); + _curvea0[719] = _8618; + uint16_t _8619 = (uint16_t)(226); + _curvea0[720] = _8619; + uint16_t _8620 = (uint16_t)(226); + _curvea0[721] = _8620; + uint16_t _8621 = (uint16_t)(226); + _curvea0[722] = _8621; + uint16_t _8622 = (uint16_t)(226); + _curvea0[723] = _8622; + uint16_t _8623 = (uint16_t)(226); + _curvea0[724] = _8623; + uint16_t _8624 = (uint16_t)(226); + _curvea0[725] = _8624; + uint16_t _8625 = (uint16_t)(227); + _curvea0[726] = _8625; + uint16_t _8626 = (uint16_t)(227); + _curvea0[727] = _8626; + uint16_t _8627 = (uint16_t)(227); + _curvea0[728] = _8627; + uint16_t _8628 = (uint16_t)(227); + _curvea0[729] = _8628; + uint16_t _8629 = (uint16_t)(227); + _curvea0[730] = _8629; + uint16_t _8630 = (uint16_t)(227); + _curvea0[731] = _8630; + uint16_t _8631 = (uint16_t)(227); + _curvea0[732] = _8631; + uint16_t _8632 = (uint16_t)(227); + _curvea0[733] = _8632; + uint16_t _8633 = (uint16_t)(228); + _curvea0[734] = _8633; + uint16_t _8634 = (uint16_t)(228); + _curvea0[735] = _8634; + uint16_t _8635 = (uint16_t)(228); + _curvea0[736] = _8635; + uint16_t _8636 = (uint16_t)(228); + _curvea0[737] = _8636; + uint16_t _8637 = (uint16_t)(228); + _curvea0[738] = _8637; + uint16_t _8638 = (uint16_t)(228); + _curvea0[739] = _8638; + uint16_t _8639 = (uint16_t)(228); + _curvea0[740] = _8639; + uint16_t _8640 = (uint16_t)(228); + _curvea0[741] = _8640; + uint16_t _8641 = (uint16_t)(228); + _curvea0[742] = _8641; + uint16_t _8642 = (uint16_t)(229); + _curvea0[743] = _8642; + uint16_t _8643 = (uint16_t)(229); + _curvea0[744] = _8643; + uint16_t _8644 = (uint16_t)(229); + _curvea0[745] = _8644; + uint16_t _8645 = (uint16_t)(229); + _curvea0[746] = _8645; + uint16_t _8646 = (uint16_t)(229); + _curvea0[747] = _8646; + uint16_t _8647 = (uint16_t)(229); + _curvea0[748] = _8647; + uint16_t _8648 = (uint16_t)(229); + _curvea0[749] = _8648; + uint16_t _8649 = (uint16_t)(229); + _curvea0[750] = _8649; + uint16_t _8650 = (uint16_t)(230); + _curvea0[751] = _8650; + uint16_t _8651 = (uint16_t)(230); + _curvea0[752] = _8651; + uint16_t _8652 = (uint16_t)(230); + _curvea0[753] = _8652; + uint16_t _8653 = (uint16_t)(230); + _curvea0[754] = _8653; + uint16_t _8654 = (uint16_t)(230); + _curvea0[755] = _8654; + uint16_t _8655 = (uint16_t)(230); + _curvea0[756] = _8655; + uint16_t _8656 = (uint16_t)(230); + _curvea0[757] = _8656; + uint16_t _8657 = (uint16_t)(230); + _curvea0[758] = _8657; + uint16_t _8658 = (uint16_t)(231); + _curvea0[759] = _8658; + uint16_t _8659 = (uint16_t)(231); + _curvea0[760] = _8659; + uint16_t _8660 = (uint16_t)(231); + _curvea0[761] = _8660; + uint16_t _8661 = (uint16_t)(231); + _curvea0[762] = _8661; + uint16_t _8662 = (uint16_t)(231); + _curvea0[763] = _8662; + uint16_t _8663 = (uint16_t)(231); + _curvea0[764] = _8663; + uint16_t _8664 = (uint16_t)(231); + _curvea0[765] = _8664; + uint16_t _8665 = (uint16_t)(231); + _curvea0[766] = _8665; + uint16_t _8666 = (uint16_t)(231); + _curvea0[767] = _8666; + uint16_t _8667 = (uint16_t)(232); + _curvea0[768] = _8667; + uint16_t _8668 = (uint16_t)(232); + _curvea0[769] = _8668; + uint16_t _8669 = (uint16_t)(232); + _curvea0[770] = _8669; + uint16_t _8670 = (uint16_t)(232); + _curvea0[771] = _8670; + uint16_t _8671 = (uint16_t)(232); + _curvea0[772] = _8671; + uint16_t _8672 = (uint16_t)(232); + _curvea0[773] = _8672; + uint16_t _8673 = (uint16_t)(232); + _curvea0[774] = _8673; + uint16_t _8674 = (uint16_t)(232); + _curvea0[775] = _8674; + uint16_t _8675 = (uint16_t)(233); + _curvea0[776] = _8675; + uint16_t _8676 = (uint16_t)(233); + _curvea0[777] = _8676; + uint16_t _8677 = (uint16_t)(233); + _curvea0[778] = _8677; + uint16_t _8678 = (uint16_t)(233); + _curvea0[779] = _8678; + uint16_t _8679 = (uint16_t)(233); + _curvea0[780] = _8679; + uint16_t _8680 = (uint16_t)(233); + _curvea0[781] = _8680; + uint16_t _8681 = (uint16_t)(233); + _curvea0[782] = _8681; + uint16_t _8682 = (uint16_t)(233); + _curvea0[783] = _8682; + uint16_t _8683 = (uint16_t)(233); + _curvea0[784] = _8683; + uint16_t _8684 = (uint16_t)(234); + _curvea0[785] = _8684; + uint16_t _8685 = (uint16_t)(234); + _curvea0[786] = _8685; + uint16_t _8686 = (uint16_t)(234); + _curvea0[787] = _8686; + uint16_t _8687 = (uint16_t)(234); + _curvea0[788] = _8687; + uint16_t _8688 = (uint16_t)(234); + _curvea0[789] = _8688; + uint16_t _8689 = (uint16_t)(234); + _curvea0[790] = _8689; + uint16_t _8690 = (uint16_t)(234); + _curvea0[791] = _8690; + uint16_t _8691 = (uint16_t)(234); + _curvea0[792] = _8691; + uint16_t _8692 = (uint16_t)(234); + _curvea0[793] = _8692; + uint16_t _8693 = (uint16_t)(235); + _curvea0[794] = _8693; + uint16_t _8694 = (uint16_t)(235); + _curvea0[795] = _8694; + uint16_t _8695 = (uint16_t)(235); + _curvea0[796] = _8695; + uint16_t _8696 = (uint16_t)(235); + _curvea0[797] = _8696; + uint16_t _8697 = (uint16_t)(235); + _curvea0[798] = _8697; + uint16_t _8698 = (uint16_t)(235); + _curvea0[799] = _8698; + uint16_t _8699 = (uint16_t)(235); + _curvea0[800] = _8699; + uint16_t _8700 = (uint16_t)(235); + _curvea0[801] = _8700; + uint16_t _8701 = (uint16_t)(235); + _curvea0[802] = _8701; + uint16_t _8702 = (uint16_t)(236); + _curvea0[803] = _8702; + uint16_t _8703 = (uint16_t)(236); + _curvea0[804] = _8703; + uint16_t _8704 = (uint16_t)(236); + _curvea0[805] = _8704; + uint16_t _8705 = (uint16_t)(236); + _curvea0[806] = _8705; + uint16_t _8706 = (uint16_t)(236); + _curvea0[807] = _8706; + uint16_t _8707 = (uint16_t)(236); + _curvea0[808] = _8707; + uint16_t _8708 = (uint16_t)(236); + _curvea0[809] = _8708; + uint16_t _8709 = (uint16_t)(236); + _curvea0[810] = _8709; + uint16_t _8710 = (uint16_t)(236); + _curvea0[811] = _8710; + uint16_t _8711 = (uint16_t)(237); + _curvea0[812] = _8711; + uint16_t _8712 = (uint16_t)(237); + _curvea0[813] = _8712; + uint16_t _8713 = (uint16_t)(237); + _curvea0[814] = _8713; + uint16_t _8714 = (uint16_t)(237); + _curvea0[815] = _8714; + uint16_t _8715 = (uint16_t)(237); + _curvea0[816] = _8715; + uint16_t _8716 = (uint16_t)(237); + _curvea0[817] = _8716; + uint16_t _8717 = (uint16_t)(237); + _curvea0[818] = _8717; + uint16_t _8718 = (uint16_t)(237); + _curvea0[819] = _8718; + uint16_t _8719 = (uint16_t)(237); + _curvea0[820] = _8719; + uint16_t _8720 = (uint16_t)(237); + _curvea0[821] = _8720; + uint16_t _8721 = (uint16_t)(238); + _curvea0[822] = _8721; + uint16_t _8722 = (uint16_t)(238); + _curvea0[823] = _8722; + uint16_t _8723 = (uint16_t)(238); + _curvea0[824] = _8723; + uint16_t _8724 = (uint16_t)(238); + _curvea0[825] = _8724; + uint16_t _8725 = (uint16_t)(238); + _curvea0[826] = _8725; + uint16_t _8726 = (uint16_t)(238); + _curvea0[827] = _8726; + uint16_t _8727 = (uint16_t)(238); + _curvea0[828] = _8727; + uint16_t _8728 = (uint16_t)(238); + _curvea0[829] = _8728; + uint16_t _8729 = (uint16_t)(238); + _curvea0[830] = _8729; + uint16_t _8730 = (uint16_t)(239); + _curvea0[831] = _8730; + uint16_t _8731 = (uint16_t)(239); + _curvea0[832] = _8731; + uint16_t _8732 = (uint16_t)(239); + _curvea0[833] = _8732; + uint16_t _8733 = (uint16_t)(239); + _curvea0[834] = _8733; + uint16_t _8734 = (uint16_t)(239); + _curvea0[835] = _8734; + uint16_t _8735 = (uint16_t)(239); + _curvea0[836] = _8735; + uint16_t _8736 = (uint16_t)(239); + _curvea0[837] = _8736; + uint16_t _8737 = (uint16_t)(239); + _curvea0[838] = _8737; + uint16_t _8738 = (uint16_t)(239); + _curvea0[839] = _8738; + uint16_t _8739 = (uint16_t)(239); + _curvea0[840] = _8739; + uint16_t _8740 = (uint16_t)(240); + _curvea0[841] = _8740; + uint16_t _8741 = (uint16_t)(240); + _curvea0[842] = _8741; + uint16_t _8742 = (uint16_t)(240); + _curvea0[843] = _8742; + uint16_t _8743 = (uint16_t)(240); + _curvea0[844] = _8743; + uint16_t _8744 = (uint16_t)(240); + _curvea0[845] = _8744; + uint16_t _8745 = (uint16_t)(240); + _curvea0[846] = _8745; + uint16_t _8746 = (uint16_t)(240); + _curvea0[847] = _8746; + uint16_t _8747 = (uint16_t)(240); + _curvea0[848] = _8747; + uint16_t _8748 = (uint16_t)(240); + _curvea0[849] = _8748; + uint16_t _8749 = (uint16_t)(240); + _curvea0[850] = _8749; + uint16_t _8750 = (uint16_t)(241); + _curvea0[851] = _8750; + uint16_t _8751 = (uint16_t)(241); + _curvea0[852] = _8751; + uint16_t _8752 = (uint16_t)(241); + _curvea0[853] = _8752; + uint16_t _8753 = (uint16_t)(241); + _curvea0[854] = _8753; + uint16_t _8754 = (uint16_t)(241); + _curvea0[855] = _8754; + uint16_t _8755 = (uint16_t)(241); + _curvea0[856] = _8755; + uint16_t _8756 = (uint16_t)(241); + _curvea0[857] = _8756; + uint16_t _8757 = (uint16_t)(241); + _curvea0[858] = _8757; + uint16_t _8758 = (uint16_t)(241); + _curvea0[859] = _8758; + uint16_t _8759 = (uint16_t)(241); + _curvea0[860] = _8759; + uint16_t _8760 = (uint16_t)(242); + _curvea0[861] = _8760; + uint16_t _8761 = (uint16_t)(242); + _curvea0[862] = _8761; + uint16_t _8762 = (uint16_t)(242); + _curvea0[863] = _8762; + uint16_t _8763 = (uint16_t)(242); + _curvea0[864] = _8763; + uint16_t _8764 = (uint16_t)(242); + _curvea0[865] = _8764; + uint16_t _8765 = (uint16_t)(242); + _curvea0[866] = _8765; + uint16_t _8766 = (uint16_t)(242); + _curvea0[867] = _8766; + uint16_t _8767 = (uint16_t)(242); + _curvea0[868] = _8767; + uint16_t _8768 = (uint16_t)(242); + _curvea0[869] = _8768; + uint16_t _8769 = (uint16_t)(242); + _curvea0[870] = _8769; + uint16_t _8770 = (uint16_t)(243); + _curvea0[871] = _8770; + uint16_t _8771 = (uint16_t)(243); + _curvea0[872] = _8771; + uint16_t _8772 = (uint16_t)(243); + _curvea0[873] = _8772; + uint16_t _8773 = (uint16_t)(243); + _curvea0[874] = _8773; + uint16_t _8774 = (uint16_t)(243); + _curvea0[875] = _8774; + uint16_t _8775 = (uint16_t)(243); + _curvea0[876] = _8775; + uint16_t _8776 = (uint16_t)(243); + _curvea0[877] = _8776; + uint16_t _8777 = (uint16_t)(243); + _curvea0[878] = _8777; + uint16_t _8778 = (uint16_t)(243); + _curvea0[879] = _8778; + uint16_t _8779 = (uint16_t)(243); + _curvea0[880] = _8779; + uint16_t _8780 = (uint16_t)(244); + _curvea0[881] = _8780; + uint16_t _8781 = (uint16_t)(244); + _curvea0[882] = _8781; + uint16_t _8782 = (uint16_t)(244); + _curvea0[883] = _8782; + uint16_t _8783 = (uint16_t)(244); + _curvea0[884] = _8783; + uint16_t _8784 = (uint16_t)(244); + _curvea0[885] = _8784; + uint16_t _8785 = (uint16_t)(244); + _curvea0[886] = _8785; + uint16_t _8786 = (uint16_t)(244); + _curvea0[887] = _8786; + uint16_t _8787 = (uint16_t)(244); + _curvea0[888] = _8787; + uint16_t _8788 = (uint16_t)(244); + _curvea0[889] = _8788; + uint16_t _8789 = (uint16_t)(244); + _curvea0[890] = _8789; + uint16_t _8790 = (uint16_t)(244); + _curvea0[891] = _8790; + uint16_t _8791 = (uint16_t)(245); + _curvea0[892] = _8791; + uint16_t _8792 = (uint16_t)(245); + _curvea0[893] = _8792; + uint16_t _8793 = (uint16_t)(245); + _curvea0[894] = _8793; + uint16_t _8794 = (uint16_t)(245); + _curvea0[895] = _8794; + uint16_t _8795 = (uint16_t)(245); + _curvea0[896] = _8795; + uint16_t _8796 = (uint16_t)(245); + _curvea0[897] = _8796; + uint16_t _8797 = (uint16_t)(245); + _curvea0[898] = _8797; + uint16_t _8798 = (uint16_t)(245); + _curvea0[899] = _8798; + uint16_t _8799 = (uint16_t)(245); + _curvea0[900] = _8799; + uint16_t _8800 = (uint16_t)(245); + _curvea0[901] = _8800; + uint16_t _8801 = (uint16_t)(245); + _curvea0[902] = _8801; + uint16_t _8802 = (uint16_t)(246); + _curvea0[903] = _8802; + uint16_t _8803 = (uint16_t)(246); + _curvea0[904] = _8803; + uint16_t _8804 = (uint16_t)(246); + _curvea0[905] = _8804; + uint16_t _8805 = (uint16_t)(246); + _curvea0[906] = _8805; + uint16_t _8806 = (uint16_t)(246); + _curvea0[907] = _8806; + uint16_t _8807 = (uint16_t)(246); + _curvea0[908] = _8807; + uint16_t _8808 = (uint16_t)(246); + _curvea0[909] = _8808; + uint16_t _8809 = (uint16_t)(246); + _curvea0[910] = _8809; + uint16_t _8810 = (uint16_t)(246); + _curvea0[911] = _8810; + uint16_t _8811 = (uint16_t)(246); + _curvea0[912] = _8811; + uint16_t _8812 = (uint16_t)(246); + _curvea0[913] = _8812; + uint16_t _8813 = (uint16_t)(247); + _curvea0[914] = _8813; + uint16_t _8814 = (uint16_t)(247); + _curvea0[915] = _8814; + uint16_t _8815 = (uint16_t)(247); + _curvea0[916] = _8815; + uint16_t _8816 = (uint16_t)(247); + _curvea0[917] = _8816; + uint16_t _8817 = (uint16_t)(247); + _curvea0[918] = _8817; + uint16_t _8818 = (uint16_t)(247); + _curvea0[919] = _8818; + uint16_t _8819 = (uint16_t)(247); + _curvea0[920] = _8819; + uint16_t _8820 = (uint16_t)(247); + _curvea0[921] = _8820; + uint16_t _8821 = (uint16_t)(247); + _curvea0[922] = _8821; + uint16_t _8822 = (uint16_t)(247); + _curvea0[923] = _8822; + uint16_t _8823 = (uint16_t)(247); + _curvea0[924] = _8823; + uint16_t _8824 = (uint16_t)(248); + _curvea0[925] = _8824; + uint16_t _8825 = (uint16_t)(248); + _curvea0[926] = _8825; + uint16_t _8826 = (uint16_t)(248); + _curvea0[927] = _8826; + uint16_t _8827 = (uint16_t)(248); + _curvea0[928] = _8827; + uint16_t _8828 = (uint16_t)(248); + _curvea0[929] = _8828; + uint16_t _8829 = (uint16_t)(248); + _curvea0[930] = _8829; + uint16_t _8830 = (uint16_t)(248); + _curvea0[931] = _8830; + uint16_t _8831 = (uint16_t)(248); + _curvea0[932] = _8831; + uint16_t _8832 = (uint16_t)(248); + _curvea0[933] = _8832; + uint16_t _8833 = (uint16_t)(248); + _curvea0[934] = _8833; + uint16_t _8834 = (uint16_t)(248); + _curvea0[935] = _8834; + uint16_t _8835 = (uint16_t)(249); + _curvea0[936] = _8835; + uint16_t _8836 = (uint16_t)(249); + _curvea0[937] = _8836; + uint16_t _8837 = (uint16_t)(249); + _curvea0[938] = _8837; + uint16_t _8838 = (uint16_t)(249); + _curvea0[939] = _8838; + uint16_t _8839 = (uint16_t)(249); + _curvea0[940] = _8839; + uint16_t _8840 = (uint16_t)(249); + _curvea0[941] = _8840; + uint16_t _8841 = (uint16_t)(249); + _curvea0[942] = _8841; + uint16_t _8842 = (uint16_t)(249); + _curvea0[943] = _8842; + uint16_t _8843 = (uint16_t)(249); + _curvea0[944] = _8843; + uint16_t _8844 = (uint16_t)(249); + _curvea0[945] = _8844; + uint16_t _8845 = (uint16_t)(249); + _curvea0[946] = _8845; + uint16_t _8846 = (uint16_t)(249); + _curvea0[947] = _8846; + uint16_t _8847 = (uint16_t)(250); + _curvea0[948] = _8847; + uint16_t _8848 = (uint16_t)(250); + _curvea0[949] = _8848; + uint16_t _8849 = (uint16_t)(250); + _curvea0[950] = _8849; + uint16_t _8850 = (uint16_t)(250); + _curvea0[951] = _8850; + uint16_t _8851 = (uint16_t)(250); + _curvea0[952] = _8851; + uint16_t _8852 = (uint16_t)(250); + _curvea0[953] = _8852; + uint16_t _8853 = (uint16_t)(250); + _curvea0[954] = _8853; + uint16_t _8854 = (uint16_t)(250); + _curvea0[955] = _8854; + uint16_t _8855 = (uint16_t)(250); + _curvea0[956] = _8855; + uint16_t _8856 = (uint16_t)(250); + _curvea0[957] = _8856; + uint16_t _8857 = (uint16_t)(250); + _curvea0[958] = _8857; + uint16_t _8858 = (uint16_t)(250); + _curvea0[959] = _8858; + uint16_t _8859 = (uint16_t)(251); + _curvea0[960] = _8859; + uint16_t _8860 = (uint16_t)(251); + _curvea0[961] = _8860; + uint16_t _8861 = (uint16_t)(251); + _curvea0[962] = _8861; + uint16_t _8862 = (uint16_t)(251); + _curvea0[963] = _8862; + uint16_t _8863 = (uint16_t)(251); + _curvea0[964] = _8863; + uint16_t _8864 = (uint16_t)(251); + _curvea0[965] = _8864; + uint16_t _8865 = (uint16_t)(251); + _curvea0[966] = _8865; + uint16_t _8866 = (uint16_t)(251); + _curvea0[967] = _8866; + uint16_t _8867 = (uint16_t)(251); + _curvea0[968] = _8867; + uint16_t _8868 = (uint16_t)(251); + _curvea0[969] = _8868; + uint16_t _8869 = (uint16_t)(251); + _curvea0[970] = _8869; + uint16_t _8870 = (uint16_t)(251); + _curvea0[971] = _8870; + uint16_t _8871 = (uint16_t)(252); + _curvea0[972] = _8871; + uint16_t _8872 = (uint16_t)(252); + _curvea0[973] = _8872; + uint16_t _8873 = (uint16_t)(252); + _curvea0[974] = _8873; + uint16_t _8874 = (uint16_t)(252); + _curvea0[975] = _8874; + uint16_t _8875 = (uint16_t)(252); + _curvea0[976] = _8875; + uint16_t _8876 = (uint16_t)(252); + _curvea0[977] = _8876; + uint16_t _8877 = (uint16_t)(252); + _curvea0[978] = _8877; + uint16_t _8878 = (uint16_t)(252); + _curvea0[979] = _8878; + uint16_t _8879 = (uint16_t)(252); + _curvea0[980] = _8879; + uint16_t _8880 = (uint16_t)(252); + _curvea0[981] = _8880; + uint16_t _8881 = (uint16_t)(252); + _curvea0[982] = _8881; + uint16_t _8882 = (uint16_t)(252); + _curvea0[983] = _8882; + uint16_t _8883 = (uint16_t)(252); + _curvea0[984] = _8883; + uint16_t _8884 = (uint16_t)(253); + _curvea0[985] = _8884; + uint16_t _8885 = (uint16_t)(253); + _curvea0[986] = _8885; + uint16_t _8886 = (uint16_t)(253); + _curvea0[987] = _8886; + uint16_t _8887 = (uint16_t)(253); + _curvea0[988] = _8887; + uint16_t _8888 = (uint16_t)(253); + _curvea0[989] = _8888; + uint16_t _8889 = (uint16_t)(253); + _curvea0[990] = _8889; + uint16_t _8890 = (uint16_t)(253); + _curvea0[991] = _8890; + uint16_t _8891 = (uint16_t)(253); + _curvea0[992] = _8891; + uint16_t _8892 = (uint16_t)(253); + _curvea0[993] = _8892; + uint16_t _8893 = (uint16_t)(253); + _curvea0[994] = _8893; + uint16_t _8894 = (uint16_t)(253); + _curvea0[995] = _8894; + uint16_t _8895 = (uint16_t)(253); + _curvea0[996] = _8895; + uint16_t _8896 = (uint16_t)(253); + _curvea0[997] = _8896; + uint16_t _8897 = (uint16_t)(254); + _curvea0[998] = _8897; + uint16_t _8898 = (uint16_t)(254); + _curvea0[999] = _8898; + uint16_t _8899 = (uint16_t)(254); + _curvea0[1000] = _8899; + uint16_t _8900 = (uint16_t)(254); + _curvea0[1001] = _8900; + uint16_t _8901 = (uint16_t)(254); + _curvea0[1002] = _8901; + uint16_t _8902 = (uint16_t)(254); + _curvea0[1003] = _8902; + uint16_t _8903 = (uint16_t)(254); + _curvea0[1004] = _8903; + uint16_t _8904 = (uint16_t)(254); + _curvea0[1005] = _8904; + uint16_t _8905 = (uint16_t)(254); + _curvea0[1006] = _8905; + uint16_t _8906 = (uint16_t)(254); + _curvea0[1007] = _8906; + uint16_t _8907 = (uint16_t)(254); + _curvea0[1008] = _8907; + uint16_t _8908 = (uint16_t)(254); + _curvea0[1009] = _8908; + uint16_t _8909 = (uint16_t)(254); + _curvea0[1010] = _8909; + uint16_t _8910 = (uint16_t)(255); + _curvea0[1011] = _8910; + uint16_t _8911 = (uint16_t)(255); + _curvea0[1012] = _8911; + uint16_t _8912 = (uint16_t)(255); + _curvea0[1013] = _8912; + uint16_t _8913 = (uint16_t)(255); + _curvea0[1014] = _8913; + uint16_t _8914 = (uint16_t)(255); + _curvea0[1015] = _8914; + uint16_t _8915 = (uint16_t)(255); + _curvea0[1016] = _8915; + uint16_t _8916 = (uint16_t)(255); + _curvea0[1017] = _8916; + uint16_t _8917 = (uint16_t)(255); + _curvea0[1018] = _8917; + uint16_t _8918 = (uint16_t)(255); + _curvea0[1019] = _8918; + uint16_t _8919 = (uint16_t)(255); + _curvea0[1020] = _8919; + uint16_t _8920 = (uint16_t)(255); + _curvea0[1021] = _8920; + uint16_t _8921 = (uint16_t)(255); + _curvea0[1022] = _8921; + uint16_t _8922 = (uint16_t)(255); + _curvea0[1023] = _8922; + + int16_t _8923 = (int16_t)(1023); + int16_t _8924 = min(_corrected_stencil_6, _8923); + int16_t _8925 = (int16_t)(0); + int16_t _8926 = max(_8924, _8925); + uint16_t _8927 = (uint16_t)(_8926); + int32_t _8928 = (int32_t)(_8927); + uint16_t _8929 = ((const uint16_t *)_curvea0)[_8928]; + return _8929; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_6(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_7 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _8947 = (uint16_t)(0); + _curvea0[0] = _8947; + uint16_t _8948 = (uint16_t)(4); + _curvea0[1] = _8948; + uint16_t _8949 = (uint16_t)(7); + _curvea0[2] = _8949; + uint16_t _8950 = (uint16_t)(8); + _curvea0[3] = _8950; + uint16_t _8951 = (uint16_t)(10); + _curvea0[4] = _8951; + uint16_t _8952 = (uint16_t)(11); + _curvea0[5] = _8952; + uint16_t _8953 = (uint16_t)(12); + _curvea0[6] = _8953; + uint16_t _8954 = (uint16_t)(13); + _curvea0[7] = _8954; + uint16_t _8955 = (uint16_t)(14); + _curvea0[8] = _8955; + uint16_t _8956 = (uint16_t)(15); + _curvea0[9] = _8956; + uint16_t _8957 = (uint16_t)(16); + _curvea0[10] = _8957; + uint16_t _8958 = (uint16_t)(17); + _curvea0[11] = _8958; + uint16_t _8959 = (uint16_t)(18); + _curvea0[12] = _8959; + uint16_t _8960 = (uint16_t)(19); + _curvea0[13] = _8960; + uint16_t _8961 = (uint16_t)(20); + _curvea0[14] = _8961; + uint16_t _8962 = (uint16_t)(21); + _curvea0[15] = _8962; + uint16_t _8963 = (uint16_t)(22); + _curvea0[16] = _8963; + uint16_t _8964 = (uint16_t)(22); + _curvea0[17] = _8964; + uint16_t _8965 = (uint16_t)(23); + _curvea0[18] = _8965; + uint16_t _8966 = (uint16_t)(24); + _curvea0[19] = _8966; + uint16_t _8967 = (uint16_t)(25); + _curvea0[20] = _8967; + uint16_t _8968 = (uint16_t)(25); + _curvea0[21] = _8968; + uint16_t _8969 = (uint16_t)(26); + _curvea0[22] = _8969; + uint16_t _8970 = (uint16_t)(27); + _curvea0[23] = _8970; + uint16_t _8971 = (uint16_t)(27); + _curvea0[24] = _8971; + uint16_t _8972 = (uint16_t)(28); + _curvea0[25] = _8972; + uint16_t _8973 = (uint16_t)(29); + _curvea0[26] = _8973; + uint16_t _8974 = (uint16_t)(29); + _curvea0[27] = _8974; + uint16_t _8975 = (uint16_t)(30); + _curvea0[28] = _8975; + uint16_t _8976 = (uint16_t)(31); + _curvea0[29] = _8976; + uint16_t _8977 = (uint16_t)(31); + _curvea0[30] = _8977; + uint16_t _8978 = (uint16_t)(32); + _curvea0[31] = _8978; + uint16_t _8979 = (uint16_t)(33); + _curvea0[32] = _8979; + uint16_t _8980 = (uint16_t)(33); + _curvea0[33] = _8980; + uint16_t _8981 = (uint16_t)(34); + _curvea0[34] = _8981; + uint16_t _8982 = (uint16_t)(34); + _curvea0[35] = _8982; + uint16_t _8983 = (uint16_t)(35); + _curvea0[36] = _8983; + uint16_t _8984 = (uint16_t)(36); + _curvea0[37] = _8984; + uint16_t _8985 = (uint16_t)(36); + _curvea0[38] = _8985; + uint16_t _8986 = (uint16_t)(37); + _curvea0[39] = _8986; + uint16_t _8987 = (uint16_t)(37); + _curvea0[40] = _8987; + uint16_t _8988 = (uint16_t)(38); + _curvea0[41] = _8988; + uint16_t _8989 = (uint16_t)(39); + _curvea0[42] = _8989; + uint16_t _8990 = (uint16_t)(39); + _curvea0[43] = _8990; + uint16_t _8991 = (uint16_t)(40); + _curvea0[44] = _8991; + uint16_t _8992 = (uint16_t)(40); + _curvea0[45] = _8992; + uint16_t _8993 = (uint16_t)(41); + _curvea0[46] = _8993; + uint16_t _8994 = (uint16_t)(41); + _curvea0[47] = _8994; + uint16_t _8995 = (uint16_t)(42); + _curvea0[48] = _8995; + uint16_t _8996 = (uint16_t)(42); + _curvea0[49] = _8996; + uint16_t _8997 = (uint16_t)(43); + _curvea0[50] = _8997; + uint16_t _8998 = (uint16_t)(44); + _curvea0[51] = _8998; + uint16_t _8999 = (uint16_t)(44); + _curvea0[52] = _8999; + uint16_t _9000 = (uint16_t)(45); + _curvea0[53] = _9000; + uint16_t _9001 = (uint16_t)(45); + _curvea0[54] = _9001; + uint16_t _9002 = (uint16_t)(46); + _curvea0[55] = _9002; + uint16_t _9003 = (uint16_t)(46); + _curvea0[56] = _9003; + uint16_t _9004 = (uint16_t)(47); + _curvea0[57] = _9004; + uint16_t _9005 = (uint16_t)(47); + _curvea0[58] = _9005; + uint16_t _9006 = (uint16_t)(48); + _curvea0[59] = _9006; + uint16_t _9007 = (uint16_t)(48); + _curvea0[60] = _9007; + uint16_t _9008 = (uint16_t)(49); + _curvea0[61] = _9008; + uint16_t _9009 = (uint16_t)(49); + _curvea0[62] = _9009; + uint16_t _9010 = (uint16_t)(50); + _curvea0[63] = _9010; + uint16_t _9011 = (uint16_t)(50); + _curvea0[64] = _9011; + uint16_t _9012 = (uint16_t)(51); + _curvea0[65] = _9012; + uint16_t _9013 = (uint16_t)(51); + _curvea0[66] = _9013; + uint16_t _9014 = (uint16_t)(52); + _curvea0[67] = _9014; + uint16_t _9015 = (uint16_t)(52); + _curvea0[68] = _9015; + uint16_t _9016 = (uint16_t)(53); + _curvea0[69] = _9016; + uint16_t _9017 = (uint16_t)(53); + _curvea0[70] = _9017; + uint16_t _9018 = (uint16_t)(54); + _curvea0[71] = _9018; + uint16_t _9019 = (uint16_t)(54); + _curvea0[72] = _9019; + uint16_t _9020 = (uint16_t)(55); + _curvea0[73] = _9020; + uint16_t _9021 = (uint16_t)(55); + _curvea0[74] = _9021; + uint16_t _9022 = (uint16_t)(56); + _curvea0[75] = _9022; + uint16_t _9023 = (uint16_t)(56); + _curvea0[76] = _9023; + uint16_t _9024 = (uint16_t)(57); + _curvea0[77] = _9024; + uint16_t _9025 = (uint16_t)(57); + _curvea0[78] = _9025; + uint16_t _9026 = (uint16_t)(58); + _curvea0[79] = _9026; + uint16_t _9027 = (uint16_t)(58); + _curvea0[80] = _9027; + uint16_t _9028 = (uint16_t)(58); + _curvea0[81] = _9028; + uint16_t _9029 = (uint16_t)(59); + _curvea0[82] = _9029; + uint16_t _9030 = (uint16_t)(59); + _curvea0[83] = _9030; + uint16_t _9031 = (uint16_t)(60); + _curvea0[84] = _9031; + uint16_t _9032 = (uint16_t)(60); + _curvea0[85] = _9032; + uint16_t _9033 = (uint16_t)(61); + _curvea0[86] = _9033; + uint16_t _9034 = (uint16_t)(61); + _curvea0[87] = _9034; + uint16_t _9035 = (uint16_t)(62); + _curvea0[88] = _9035; + uint16_t _9036 = (uint16_t)(62); + _curvea0[89] = _9036; + uint16_t _9037 = (uint16_t)(63); + _curvea0[90] = _9037; + uint16_t _9038 = (uint16_t)(63); + _curvea0[91] = _9038; + uint16_t _9039 = (uint16_t)(64); + _curvea0[92] = _9039; + uint16_t _9040 = (uint16_t)(64); + _curvea0[93] = _9040; + uint16_t _9041 = (uint16_t)(64); + _curvea0[94] = _9041; + uint16_t _9042 = (uint16_t)(65); + _curvea0[95] = _9042; + uint16_t _9043 = (uint16_t)(65); + _curvea0[96] = _9043; + uint16_t _9044 = (uint16_t)(66); + _curvea0[97] = _9044; + uint16_t _9045 = (uint16_t)(66); + _curvea0[98] = _9045; + uint16_t _9046 = (uint16_t)(67); + _curvea0[99] = _9046; + uint16_t _9047 = (uint16_t)(67); + _curvea0[100] = _9047; + uint16_t _9048 = (uint16_t)(68); + _curvea0[101] = _9048; + uint16_t _9049 = (uint16_t)(68); + _curvea0[102] = _9049; + uint16_t _9050 = (uint16_t)(68); + _curvea0[103] = _9050; + uint16_t _9051 = (uint16_t)(69); + _curvea0[104] = _9051; + uint16_t _9052 = (uint16_t)(69); + _curvea0[105] = _9052; + uint16_t _9053 = (uint16_t)(70); + _curvea0[106] = _9053; + uint16_t _9054 = (uint16_t)(70); + _curvea0[107] = _9054; + uint16_t _9055 = (uint16_t)(71); + _curvea0[108] = _9055; + uint16_t _9056 = (uint16_t)(71); + _curvea0[109] = _9056; + uint16_t _9057 = (uint16_t)(71); + _curvea0[110] = _9057; + uint16_t _9058 = (uint16_t)(72); + _curvea0[111] = _9058; + uint16_t _9059 = (uint16_t)(72); + _curvea0[112] = _9059; + uint16_t _9060 = (uint16_t)(73); + _curvea0[113] = _9060; + uint16_t _9061 = (uint16_t)(73); + _curvea0[114] = _9061; + uint16_t _9062 = (uint16_t)(74); + _curvea0[115] = _9062; + uint16_t _9063 = (uint16_t)(74); + _curvea0[116] = _9063; + uint16_t _9064 = (uint16_t)(74); + _curvea0[117] = _9064; + uint16_t _9065 = (uint16_t)(75); + _curvea0[118] = _9065; + uint16_t _9066 = (uint16_t)(75); + _curvea0[119] = _9066; + uint16_t _9067 = (uint16_t)(76); + _curvea0[120] = _9067; + uint16_t _9068 = (uint16_t)(76); + _curvea0[121] = _9068; + uint16_t _9069 = (uint16_t)(77); + _curvea0[122] = _9069; + uint16_t _9070 = (uint16_t)(77); + _curvea0[123] = _9070; + uint16_t _9071 = (uint16_t)(77); + _curvea0[124] = _9071; + uint16_t _9072 = (uint16_t)(78); + _curvea0[125] = _9072; + uint16_t _9073 = (uint16_t)(78); + _curvea0[126] = _9073; + uint16_t _9074 = (uint16_t)(79); + _curvea0[127] = _9074; + uint16_t _9075 = (uint16_t)(79); + _curvea0[128] = _9075; + uint16_t _9076 = (uint16_t)(79); + _curvea0[129] = _9076; + uint16_t _9077 = (uint16_t)(80); + _curvea0[130] = _9077; + uint16_t _9078 = (uint16_t)(80); + _curvea0[131] = _9078; + uint16_t _9079 = (uint16_t)(81); + _curvea0[132] = _9079; + uint16_t _9080 = (uint16_t)(81); + _curvea0[133] = _9080; + uint16_t _9081 = (uint16_t)(82); + _curvea0[134] = _9081; + uint16_t _9082 = (uint16_t)(82); + _curvea0[135] = _9082; + uint16_t _9083 = (uint16_t)(82); + _curvea0[136] = _9083; + uint16_t _9084 = (uint16_t)(83); + _curvea0[137] = _9084; + uint16_t _9085 = (uint16_t)(83); + _curvea0[138] = _9085; + uint16_t _9086 = (uint16_t)(84); + _curvea0[139] = _9086; + uint16_t _9087 = (uint16_t)(84); + _curvea0[140] = _9087; + uint16_t _9088 = (uint16_t)(84); + _curvea0[141] = _9088; + uint16_t _9089 = (uint16_t)(85); + _curvea0[142] = _9089; + uint16_t _9090 = (uint16_t)(85); + _curvea0[143] = _9090; + uint16_t _9091 = (uint16_t)(86); + _curvea0[144] = _9091; + uint16_t _9092 = (uint16_t)(86); + _curvea0[145] = _9092; + uint16_t _9093 = (uint16_t)(86); + _curvea0[146] = _9093; + uint16_t _9094 = (uint16_t)(87); + _curvea0[147] = _9094; + uint16_t _9095 = (uint16_t)(87); + _curvea0[148] = _9095; + uint16_t _9096 = (uint16_t)(88); + _curvea0[149] = _9096; + uint16_t _9097 = (uint16_t)(88); + _curvea0[150] = _9097; + uint16_t _9098 = (uint16_t)(88); + _curvea0[151] = _9098; + uint16_t _9099 = (uint16_t)(89); + _curvea0[152] = _9099; + uint16_t _9100 = (uint16_t)(89); + _curvea0[153] = _9100; + uint16_t _9101 = (uint16_t)(90); + _curvea0[154] = _9101; + uint16_t _9102 = (uint16_t)(90); + _curvea0[155] = _9102; + uint16_t _9103 = (uint16_t)(90); + _curvea0[156] = _9103; + uint16_t _9104 = (uint16_t)(91); + _curvea0[157] = _9104; + uint16_t _9105 = (uint16_t)(91); + _curvea0[158] = _9105; + uint16_t _9106 = (uint16_t)(92); + _curvea0[159] = _9106; + uint16_t _9107 = (uint16_t)(92); + _curvea0[160] = _9107; + uint16_t _9108 = (uint16_t)(92); + _curvea0[161] = _9108; + uint16_t _9109 = (uint16_t)(93); + _curvea0[162] = _9109; + uint16_t _9110 = (uint16_t)(93); + _curvea0[163] = _9110; + uint16_t _9111 = (uint16_t)(93); + _curvea0[164] = _9111; + uint16_t _9112 = (uint16_t)(94); + _curvea0[165] = _9112; + uint16_t _9113 = (uint16_t)(94); + _curvea0[166] = _9113; + uint16_t _9114 = (uint16_t)(95); + _curvea0[167] = _9114; + uint16_t _9115 = (uint16_t)(95); + _curvea0[168] = _9115; + uint16_t _9116 = (uint16_t)(95); + _curvea0[169] = _9116; + uint16_t _9117 = (uint16_t)(96); + _curvea0[170] = _9117; + uint16_t _9118 = (uint16_t)(96); + _curvea0[171] = _9118; + uint16_t _9119 = (uint16_t)(97); + _curvea0[172] = _9119; + uint16_t _9120 = (uint16_t)(97); + _curvea0[173] = _9120; + uint16_t _9121 = (uint16_t)(97); + _curvea0[174] = _9121; + uint16_t _9122 = (uint16_t)(98); + _curvea0[175] = _9122; + uint16_t _9123 = (uint16_t)(98); + _curvea0[176] = _9123; + uint16_t _9124 = (uint16_t)(99); + _curvea0[177] = _9124; + uint16_t _9125 = (uint16_t)(99); + _curvea0[178] = _9125; + uint16_t _9126 = (uint16_t)(99); + _curvea0[179] = _9126; + uint16_t _9127 = (uint16_t)(100); + _curvea0[180] = _9127; + uint16_t _9128 = (uint16_t)(100); + _curvea0[181] = _9128; + uint16_t _9129 = (uint16_t)(100); + _curvea0[182] = _9129; + uint16_t _9130 = (uint16_t)(101); + _curvea0[183] = _9130; + uint16_t _9131 = (uint16_t)(101); + _curvea0[184] = _9131; + uint16_t _9132 = (uint16_t)(102); + _curvea0[185] = _9132; + uint16_t _9133 = (uint16_t)(102); + _curvea0[186] = _9133; + uint16_t _9134 = (uint16_t)(102); + _curvea0[187] = _9134; + uint16_t _9135 = (uint16_t)(103); + _curvea0[188] = _9135; + uint16_t _9136 = (uint16_t)(103); + _curvea0[189] = _9136; + uint16_t _9137 = (uint16_t)(103); + _curvea0[190] = _9137; + uint16_t _9138 = (uint16_t)(104); + _curvea0[191] = _9138; + uint16_t _9139 = (uint16_t)(104); + _curvea0[192] = _9139; + uint16_t _9140 = (uint16_t)(105); + _curvea0[193] = _9140; + uint16_t _9141 = (uint16_t)(105); + _curvea0[194] = _9141; + uint16_t _9142 = (uint16_t)(105); + _curvea0[195] = _9142; + uint16_t _9143 = (uint16_t)(106); + _curvea0[196] = _9143; + uint16_t _9144 = (uint16_t)(106); + _curvea0[197] = _9144; + uint16_t _9145 = (uint16_t)(106); + _curvea0[198] = _9145; + uint16_t _9146 = (uint16_t)(107); + _curvea0[199] = _9146; + uint16_t _9147 = (uint16_t)(107); + _curvea0[200] = _9147; + uint16_t _9148 = (uint16_t)(108); + _curvea0[201] = _9148; + uint16_t _9149 = (uint16_t)(108); + _curvea0[202] = _9149; + uint16_t _9150 = (uint16_t)(108); + _curvea0[203] = _9150; + uint16_t _9151 = (uint16_t)(109); + _curvea0[204] = _9151; + uint16_t _9152 = (uint16_t)(109); + _curvea0[205] = _9152; + uint16_t _9153 = (uint16_t)(109); + _curvea0[206] = _9153; + uint16_t _9154 = (uint16_t)(110); + _curvea0[207] = _9154; + uint16_t _9155 = (uint16_t)(110); + _curvea0[208] = _9155; + uint16_t _9156 = (uint16_t)(111); + _curvea0[209] = _9156; + uint16_t _9157 = (uint16_t)(111); + _curvea0[210] = _9157; + uint16_t _9158 = (uint16_t)(111); + _curvea0[211] = _9158; + uint16_t _9159 = (uint16_t)(112); + _curvea0[212] = _9159; + uint16_t _9160 = (uint16_t)(112); + _curvea0[213] = _9160; + uint16_t _9161 = (uint16_t)(112); + _curvea0[214] = _9161; + uint16_t _9162 = (uint16_t)(113); + _curvea0[215] = _9162; + uint16_t _9163 = (uint16_t)(113); + _curvea0[216] = _9163; + uint16_t _9164 = (uint16_t)(113); + _curvea0[217] = _9164; + uint16_t _9165 = (uint16_t)(114); + _curvea0[218] = _9165; + uint16_t _9166 = (uint16_t)(114); + _curvea0[219] = _9166; + uint16_t _9167 = (uint16_t)(115); + _curvea0[220] = _9167; + uint16_t _9168 = (uint16_t)(115); + _curvea0[221] = _9168; + uint16_t _9169 = (uint16_t)(115); + _curvea0[222] = _9169; + uint16_t _9170 = (uint16_t)(116); + _curvea0[223] = _9170; + uint16_t _9171 = (uint16_t)(116); + _curvea0[224] = _9171; + uint16_t _9172 = (uint16_t)(116); + _curvea0[225] = _9172; + uint16_t _9173 = (uint16_t)(117); + _curvea0[226] = _9173; + uint16_t _9174 = (uint16_t)(117); + _curvea0[227] = _9174; + uint16_t _9175 = (uint16_t)(117); + _curvea0[228] = _9175; + uint16_t _9176 = (uint16_t)(118); + _curvea0[229] = _9176; + uint16_t _9177 = (uint16_t)(118); + _curvea0[230] = _9177; + uint16_t _9178 = (uint16_t)(119); + _curvea0[231] = _9178; + uint16_t _9179 = (uint16_t)(119); + _curvea0[232] = _9179; + uint16_t _9180 = (uint16_t)(119); + _curvea0[233] = _9180; + uint16_t _9181 = (uint16_t)(120); + _curvea0[234] = _9181; + uint16_t _9182 = (uint16_t)(120); + _curvea0[235] = _9182; + uint16_t _9183 = (uint16_t)(120); + _curvea0[236] = _9183; + uint16_t _9184 = (uint16_t)(121); + _curvea0[237] = _9184; + uint16_t _9185 = (uint16_t)(121); + _curvea0[238] = _9185; + uint16_t _9186 = (uint16_t)(121); + _curvea0[239] = _9186; + uint16_t _9187 = (uint16_t)(122); + _curvea0[240] = _9187; + uint16_t _9188 = (uint16_t)(122); + _curvea0[241] = _9188; + uint16_t _9189 = (uint16_t)(123); + _curvea0[242] = _9189; + uint16_t _9190 = (uint16_t)(123); + _curvea0[243] = _9190; + uint16_t _9191 = (uint16_t)(123); + _curvea0[244] = _9191; + uint16_t _9192 = (uint16_t)(124); + _curvea0[245] = _9192; + uint16_t _9193 = (uint16_t)(124); + _curvea0[246] = _9193; + uint16_t _9194 = (uint16_t)(124); + _curvea0[247] = _9194; + uint16_t _9195 = (uint16_t)(125); + _curvea0[248] = _9195; + uint16_t _9196 = (uint16_t)(125); + _curvea0[249] = _9196; + uint16_t _9197 = (uint16_t)(125); + _curvea0[250] = _9197; + uint16_t _9198 = (uint16_t)(126); + _curvea0[251] = _9198; + uint16_t _9199 = (uint16_t)(126); + _curvea0[252] = _9199; + uint16_t _9200 = (uint16_t)(126); + _curvea0[253] = _9200; + uint16_t _9201 = (uint16_t)(127); + _curvea0[254] = _9201; + uint16_t _9202 = (uint16_t)(127); + _curvea0[255] = _9202; + uint16_t _9203 = (uint16_t)(128); + _curvea0[256] = _9203; + uint16_t _9204 = (uint16_t)(128); + _curvea0[257] = _9204; + uint16_t _9205 = (uint16_t)(128); + _curvea0[258] = _9205; + uint16_t _9206 = (uint16_t)(129); + _curvea0[259] = _9206; + uint16_t _9207 = (uint16_t)(129); + _curvea0[260] = _9207; + uint16_t _9208 = (uint16_t)(129); + _curvea0[261] = _9208; + uint16_t _9209 = (uint16_t)(130); + _curvea0[262] = _9209; + uint16_t _9210 = (uint16_t)(130); + _curvea0[263] = _9210; + uint16_t _9211 = (uint16_t)(130); + _curvea0[264] = _9211; + uint16_t _9212 = (uint16_t)(131); + _curvea0[265] = _9212; + uint16_t _9213 = (uint16_t)(131); + _curvea0[266] = _9213; + uint16_t _9214 = (uint16_t)(131); + _curvea0[267] = _9214; + uint16_t _9215 = (uint16_t)(132); + _curvea0[268] = _9215; + uint16_t _9216 = (uint16_t)(132); + _curvea0[269] = _9216; + uint16_t _9217 = (uint16_t)(132); + _curvea0[270] = _9217; + uint16_t _9218 = (uint16_t)(133); + _curvea0[271] = _9218; + uint16_t _9219 = (uint16_t)(133); + _curvea0[272] = _9219; + uint16_t _9220 = (uint16_t)(133); + _curvea0[273] = _9220; + uint16_t _9221 = (uint16_t)(134); + _curvea0[274] = _9221; + uint16_t _9222 = (uint16_t)(134); + _curvea0[275] = _9222; + uint16_t _9223 = (uint16_t)(134); + _curvea0[276] = _9223; + uint16_t _9224 = (uint16_t)(135); + _curvea0[277] = _9224; + uint16_t _9225 = (uint16_t)(135); + _curvea0[278] = _9225; + uint16_t _9226 = (uint16_t)(135); + _curvea0[279] = _9226; + uint16_t _9227 = (uint16_t)(136); + _curvea0[280] = _9227; + uint16_t _9228 = (uint16_t)(136); + _curvea0[281] = _9228; + uint16_t _9229 = (uint16_t)(136); + _curvea0[282] = _9229; + uint16_t _9230 = (uint16_t)(137); + _curvea0[283] = _9230; + uint16_t _9231 = (uint16_t)(137); + _curvea0[284] = _9231; + uint16_t _9232 = (uint16_t)(137); + _curvea0[285] = _9232; + uint16_t _9233 = (uint16_t)(138); + _curvea0[286] = _9233; + uint16_t _9234 = (uint16_t)(138); + _curvea0[287] = _9234; + uint16_t _9235 = (uint16_t)(138); + _curvea0[288] = _9235; + uint16_t _9236 = (uint16_t)(139); + _curvea0[289] = _9236; + uint16_t _9237 = (uint16_t)(139); + _curvea0[290] = _9237; + uint16_t _9238 = (uint16_t)(139); + _curvea0[291] = _9238; + uint16_t _9239 = (uint16_t)(140); + _curvea0[292] = _9239; + uint16_t _9240 = (uint16_t)(140); + _curvea0[293] = _9240; + uint16_t _9241 = (uint16_t)(140); + _curvea0[294] = _9241; + uint16_t _9242 = (uint16_t)(141); + _curvea0[295] = _9242; + uint16_t _9243 = (uint16_t)(141); + _curvea0[296] = _9243; + uint16_t _9244 = (uint16_t)(141); + _curvea0[297] = _9244; + uint16_t _9245 = (uint16_t)(141); + _curvea0[298] = _9245; + uint16_t _9246 = (uint16_t)(142); + _curvea0[299] = _9246; + uint16_t _9247 = (uint16_t)(142); + _curvea0[300] = _9247; + uint16_t _9248 = (uint16_t)(142); + _curvea0[301] = _9248; + uint16_t _9249 = (uint16_t)(143); + _curvea0[302] = _9249; + uint16_t _9250 = (uint16_t)(143); + _curvea0[303] = _9250; + uint16_t _9251 = (uint16_t)(143); + _curvea0[304] = _9251; + uint16_t _9252 = (uint16_t)(144); + _curvea0[305] = _9252; + uint16_t _9253 = (uint16_t)(144); + _curvea0[306] = _9253; + uint16_t _9254 = (uint16_t)(144); + _curvea0[307] = _9254; + uint16_t _9255 = (uint16_t)(145); + _curvea0[308] = _9255; + uint16_t _9256 = (uint16_t)(145); + _curvea0[309] = _9256; + uint16_t _9257 = (uint16_t)(145); + _curvea0[310] = _9257; + uint16_t _9258 = (uint16_t)(145); + _curvea0[311] = _9258; + uint16_t _9259 = (uint16_t)(146); + _curvea0[312] = _9259; + uint16_t _9260 = (uint16_t)(146); + _curvea0[313] = _9260; + uint16_t _9261 = (uint16_t)(146); + _curvea0[314] = _9261; + uint16_t _9262 = (uint16_t)(147); + _curvea0[315] = _9262; + uint16_t _9263 = (uint16_t)(147); + _curvea0[316] = _9263; + uint16_t _9264 = (uint16_t)(147); + _curvea0[317] = _9264; + uint16_t _9265 = (uint16_t)(148); + _curvea0[318] = _9265; + uint16_t _9266 = (uint16_t)(148); + _curvea0[319] = _9266; + uint16_t _9267 = (uint16_t)(148); + _curvea0[320] = _9267; + uint16_t _9268 = (uint16_t)(148); + _curvea0[321] = _9268; + uint16_t _9269 = (uint16_t)(149); + _curvea0[322] = _9269; + uint16_t _9270 = (uint16_t)(149); + _curvea0[323] = _9270; + uint16_t _9271 = (uint16_t)(149); + _curvea0[324] = _9271; + uint16_t _9272 = (uint16_t)(150); + _curvea0[325] = _9272; + uint16_t _9273 = (uint16_t)(150); + _curvea0[326] = _9273; + uint16_t _9274 = (uint16_t)(150); + _curvea0[327] = _9274; + uint16_t _9275 = (uint16_t)(150); + _curvea0[328] = _9275; + uint16_t _9276 = (uint16_t)(151); + _curvea0[329] = _9276; + uint16_t _9277 = (uint16_t)(151); + _curvea0[330] = _9277; + uint16_t _9278 = (uint16_t)(151); + _curvea0[331] = _9278; + uint16_t _9279 = (uint16_t)(152); + _curvea0[332] = _9279; + uint16_t _9280 = (uint16_t)(152); + _curvea0[333] = _9280; + uint16_t _9281 = (uint16_t)(152); + _curvea0[334] = _9281; + uint16_t _9282 = (uint16_t)(152); + _curvea0[335] = _9282; + uint16_t _9283 = (uint16_t)(153); + _curvea0[336] = _9283; + uint16_t _9284 = (uint16_t)(153); + _curvea0[337] = _9284; + uint16_t _9285 = (uint16_t)(153); + _curvea0[338] = _9285; + uint16_t _9286 = (uint16_t)(154); + _curvea0[339] = _9286; + uint16_t _9287 = (uint16_t)(154); + _curvea0[340] = _9287; + uint16_t _9288 = (uint16_t)(154); + _curvea0[341] = _9288; + uint16_t _9289 = (uint16_t)(154); + _curvea0[342] = _9289; + uint16_t _9290 = (uint16_t)(155); + _curvea0[343] = _9290; + uint16_t _9291 = (uint16_t)(155); + _curvea0[344] = _9291; + uint16_t _9292 = (uint16_t)(155); + _curvea0[345] = _9292; + uint16_t _9293 = (uint16_t)(156); + _curvea0[346] = _9293; + uint16_t _9294 = (uint16_t)(156); + _curvea0[347] = _9294; + uint16_t _9295 = (uint16_t)(156); + _curvea0[348] = _9295; + uint16_t _9296 = (uint16_t)(156); + _curvea0[349] = _9296; + uint16_t _9297 = (uint16_t)(157); + _curvea0[350] = _9297; + uint16_t _9298 = (uint16_t)(157); + _curvea0[351] = _9298; + uint16_t _9299 = (uint16_t)(157); + _curvea0[352] = _9299; + uint16_t _9300 = (uint16_t)(157); + _curvea0[353] = _9300; + uint16_t _9301 = (uint16_t)(158); + _curvea0[354] = _9301; + uint16_t _9302 = (uint16_t)(158); + _curvea0[355] = _9302; + uint16_t _9303 = (uint16_t)(158); + _curvea0[356] = _9303; + uint16_t _9304 = (uint16_t)(159); + _curvea0[357] = _9304; + uint16_t _9305 = (uint16_t)(159); + _curvea0[358] = _9305; + uint16_t _9306 = (uint16_t)(159); + _curvea0[359] = _9306; + uint16_t _9307 = (uint16_t)(159); + _curvea0[360] = _9307; + uint16_t _9308 = (uint16_t)(160); + _curvea0[361] = _9308; + uint16_t _9309 = (uint16_t)(160); + _curvea0[362] = _9309; + uint16_t _9310 = (uint16_t)(160); + _curvea0[363] = _9310; + uint16_t _9311 = (uint16_t)(160); + _curvea0[364] = _9311; + uint16_t _9312 = (uint16_t)(161); + _curvea0[365] = _9312; + uint16_t _9313 = (uint16_t)(161); + _curvea0[366] = _9313; + uint16_t _9314 = (uint16_t)(161); + _curvea0[367] = _9314; + uint16_t _9315 = (uint16_t)(161); + _curvea0[368] = _9315; + uint16_t _9316 = (uint16_t)(162); + _curvea0[369] = _9316; + uint16_t _9317 = (uint16_t)(162); + _curvea0[370] = _9317; + uint16_t _9318 = (uint16_t)(162); + _curvea0[371] = _9318; + uint16_t _9319 = (uint16_t)(162); + _curvea0[372] = _9319; + uint16_t _9320 = (uint16_t)(163); + _curvea0[373] = _9320; + uint16_t _9321 = (uint16_t)(163); + _curvea0[374] = _9321; + uint16_t _9322 = (uint16_t)(163); + _curvea0[375] = _9322; + uint16_t _9323 = (uint16_t)(163); + _curvea0[376] = _9323; + uint16_t _9324 = (uint16_t)(164); + _curvea0[377] = _9324; + uint16_t _9325 = (uint16_t)(164); + _curvea0[378] = _9325; + uint16_t _9326 = (uint16_t)(164); + _curvea0[379] = _9326; + uint16_t _9327 = (uint16_t)(164); + _curvea0[380] = _9327; + uint16_t _9328 = (uint16_t)(165); + _curvea0[381] = _9328; + uint16_t _9329 = (uint16_t)(165); + _curvea0[382] = _9329; + uint16_t _9330 = (uint16_t)(165); + _curvea0[383] = _9330; + uint16_t _9331 = (uint16_t)(166); + _curvea0[384] = _9331; + uint16_t _9332 = (uint16_t)(166); + _curvea0[385] = _9332; + uint16_t _9333 = (uint16_t)(166); + _curvea0[386] = _9333; + uint16_t _9334 = (uint16_t)(166); + _curvea0[387] = _9334; + uint16_t _9335 = (uint16_t)(167); + _curvea0[388] = _9335; + uint16_t _9336 = (uint16_t)(167); + _curvea0[389] = _9336; + uint16_t _9337 = (uint16_t)(167); + _curvea0[390] = _9337; + uint16_t _9338 = (uint16_t)(167); + _curvea0[391] = _9338; + uint16_t _9339 = (uint16_t)(167); + _curvea0[392] = _9339; + uint16_t _9340 = (uint16_t)(168); + _curvea0[393] = _9340; + uint16_t _9341 = (uint16_t)(168); + _curvea0[394] = _9341; + uint16_t _9342 = (uint16_t)(168); + _curvea0[395] = _9342; + uint16_t _9343 = (uint16_t)(168); + _curvea0[396] = _9343; + uint16_t _9344 = (uint16_t)(169); + _curvea0[397] = _9344; + uint16_t _9345 = (uint16_t)(169); + _curvea0[398] = _9345; + uint16_t _9346 = (uint16_t)(169); + _curvea0[399] = _9346; + uint16_t _9347 = (uint16_t)(169); + _curvea0[400] = _9347; + uint16_t _9348 = (uint16_t)(170); + _curvea0[401] = _9348; + uint16_t _9349 = (uint16_t)(170); + _curvea0[402] = _9349; + uint16_t _9350 = (uint16_t)(170); + _curvea0[403] = _9350; + uint16_t _9351 = (uint16_t)(170); + _curvea0[404] = _9351; + uint16_t _9352 = (uint16_t)(171); + _curvea0[405] = _9352; + uint16_t _9353 = (uint16_t)(171); + _curvea0[406] = _9353; + uint16_t _9354 = (uint16_t)(171); + _curvea0[407] = _9354; + uint16_t _9355 = (uint16_t)(171); + _curvea0[408] = _9355; + uint16_t _9356 = (uint16_t)(172); + _curvea0[409] = _9356; + uint16_t _9357 = (uint16_t)(172); + _curvea0[410] = _9357; + uint16_t _9358 = (uint16_t)(172); + _curvea0[411] = _9358; + uint16_t _9359 = (uint16_t)(172); + _curvea0[412] = _9359; + uint16_t _9360 = (uint16_t)(173); + _curvea0[413] = _9360; + uint16_t _9361 = (uint16_t)(173); + _curvea0[414] = _9361; + uint16_t _9362 = (uint16_t)(173); + _curvea0[415] = _9362; + uint16_t _9363 = (uint16_t)(173); + _curvea0[416] = _9363; + uint16_t _9364 = (uint16_t)(173); + _curvea0[417] = _9364; + uint16_t _9365 = (uint16_t)(174); + _curvea0[418] = _9365; + uint16_t _9366 = (uint16_t)(174); + _curvea0[419] = _9366; + uint16_t _9367 = (uint16_t)(174); + _curvea0[420] = _9367; + uint16_t _9368 = (uint16_t)(174); + _curvea0[421] = _9368; + uint16_t _9369 = (uint16_t)(175); + _curvea0[422] = _9369; + uint16_t _9370 = (uint16_t)(175); + _curvea0[423] = _9370; + uint16_t _9371 = (uint16_t)(175); + _curvea0[424] = _9371; + uint16_t _9372 = (uint16_t)(175); + _curvea0[425] = _9372; + uint16_t _9373 = (uint16_t)(176); + _curvea0[426] = _9373; + uint16_t _9374 = (uint16_t)(176); + _curvea0[427] = _9374; + uint16_t _9375 = (uint16_t)(176); + _curvea0[428] = _9375; + uint16_t _9376 = (uint16_t)(176); + _curvea0[429] = _9376; + uint16_t _9377 = (uint16_t)(176); + _curvea0[430] = _9377; + uint16_t _9378 = (uint16_t)(177); + _curvea0[431] = _9378; + uint16_t _9379 = (uint16_t)(177); + _curvea0[432] = _9379; + uint16_t _9380 = (uint16_t)(177); + _curvea0[433] = _9380; + uint16_t _9381 = (uint16_t)(177); + _curvea0[434] = _9381; + uint16_t _9382 = (uint16_t)(178); + _curvea0[435] = _9382; + uint16_t _9383 = (uint16_t)(178); + _curvea0[436] = _9383; + uint16_t _9384 = (uint16_t)(178); + _curvea0[437] = _9384; + uint16_t _9385 = (uint16_t)(178); + _curvea0[438] = _9385; + uint16_t _9386 = (uint16_t)(178); + _curvea0[439] = _9386; + uint16_t _9387 = (uint16_t)(179); + _curvea0[440] = _9387; + uint16_t _9388 = (uint16_t)(179); + _curvea0[441] = _9388; + uint16_t _9389 = (uint16_t)(179); + _curvea0[442] = _9389; + uint16_t _9390 = (uint16_t)(179); + _curvea0[443] = _9390; + uint16_t _9391 = (uint16_t)(180); + _curvea0[444] = _9391; + uint16_t _9392 = (uint16_t)(180); + _curvea0[445] = _9392; + uint16_t _9393 = (uint16_t)(180); + _curvea0[446] = _9393; + uint16_t _9394 = (uint16_t)(180); + _curvea0[447] = _9394; + uint16_t _9395 = (uint16_t)(180); + _curvea0[448] = _9395; + uint16_t _9396 = (uint16_t)(181); + _curvea0[449] = _9396; + uint16_t _9397 = (uint16_t)(181); + _curvea0[450] = _9397; + uint16_t _9398 = (uint16_t)(181); + _curvea0[451] = _9398; + uint16_t _9399 = (uint16_t)(181); + _curvea0[452] = _9399; + uint16_t _9400 = (uint16_t)(181); + _curvea0[453] = _9400; + uint16_t _9401 = (uint16_t)(182); + _curvea0[454] = _9401; + uint16_t _9402 = (uint16_t)(182); + _curvea0[455] = _9402; + uint16_t _9403 = (uint16_t)(182); + _curvea0[456] = _9403; + uint16_t _9404 = (uint16_t)(182); + _curvea0[457] = _9404; + uint16_t _9405 = (uint16_t)(183); + _curvea0[458] = _9405; + uint16_t _9406 = (uint16_t)(183); + _curvea0[459] = _9406; + uint16_t _9407 = (uint16_t)(183); + _curvea0[460] = _9407; + uint16_t _9408 = (uint16_t)(183); + _curvea0[461] = _9408; + uint16_t _9409 = (uint16_t)(183); + _curvea0[462] = _9409; + uint16_t _9410 = (uint16_t)(184); + _curvea0[463] = _9410; + uint16_t _9411 = (uint16_t)(184); + _curvea0[464] = _9411; + uint16_t _9412 = (uint16_t)(184); + _curvea0[465] = _9412; + uint16_t _9413 = (uint16_t)(184); + _curvea0[466] = _9413; + uint16_t _9414 = (uint16_t)(184); + _curvea0[467] = _9414; + uint16_t _9415 = (uint16_t)(185); + _curvea0[468] = _9415; + uint16_t _9416 = (uint16_t)(185); + _curvea0[469] = _9416; + uint16_t _9417 = (uint16_t)(185); + _curvea0[470] = _9417; + uint16_t _9418 = (uint16_t)(185); + _curvea0[471] = _9418; + uint16_t _9419 = (uint16_t)(185); + _curvea0[472] = _9419; + uint16_t _9420 = (uint16_t)(186); + _curvea0[473] = _9420; + uint16_t _9421 = (uint16_t)(186); + _curvea0[474] = _9421; + uint16_t _9422 = (uint16_t)(186); + _curvea0[475] = _9422; + uint16_t _9423 = (uint16_t)(186); + _curvea0[476] = _9423; + uint16_t _9424 = (uint16_t)(187); + _curvea0[477] = _9424; + uint16_t _9425 = (uint16_t)(187); + _curvea0[478] = _9425; + uint16_t _9426 = (uint16_t)(187); + _curvea0[479] = _9426; + uint16_t _9427 = (uint16_t)(187); + _curvea0[480] = _9427; + uint16_t _9428 = (uint16_t)(187); + _curvea0[481] = _9428; + uint16_t _9429 = (uint16_t)(188); + _curvea0[482] = _9429; + uint16_t _9430 = (uint16_t)(188); + _curvea0[483] = _9430; + uint16_t _9431 = (uint16_t)(188); + _curvea0[484] = _9431; + uint16_t _9432 = (uint16_t)(188); + _curvea0[485] = _9432; + uint16_t _9433 = (uint16_t)(188); + _curvea0[486] = _9433; + uint16_t _9434 = (uint16_t)(189); + _curvea0[487] = _9434; + uint16_t _9435 = (uint16_t)(189); + _curvea0[488] = _9435; + uint16_t _9436 = (uint16_t)(189); + _curvea0[489] = _9436; + uint16_t _9437 = (uint16_t)(189); + _curvea0[490] = _9437; + uint16_t _9438 = (uint16_t)(189); + _curvea0[491] = _9438; + uint16_t _9439 = (uint16_t)(190); + _curvea0[492] = _9439; + uint16_t _9440 = (uint16_t)(190); + _curvea0[493] = _9440; + uint16_t _9441 = (uint16_t)(190); + _curvea0[494] = _9441; + uint16_t _9442 = (uint16_t)(190); + _curvea0[495] = _9442; + uint16_t _9443 = (uint16_t)(190); + _curvea0[496] = _9443; + uint16_t _9444 = (uint16_t)(190); + _curvea0[497] = _9444; + uint16_t _9445 = (uint16_t)(191); + _curvea0[498] = _9445; + uint16_t _9446 = (uint16_t)(191); + _curvea0[499] = _9446; + uint16_t _9447 = (uint16_t)(191); + _curvea0[500] = _9447; + uint16_t _9448 = (uint16_t)(191); + _curvea0[501] = _9448; + uint16_t _9449 = (uint16_t)(191); + _curvea0[502] = _9449; + uint16_t _9450 = (uint16_t)(192); + _curvea0[503] = _9450; + uint16_t _9451 = (uint16_t)(192); + _curvea0[504] = _9451; + uint16_t _9452 = (uint16_t)(192); + _curvea0[505] = _9452; + uint16_t _9453 = (uint16_t)(192); + _curvea0[506] = _9453; + uint16_t _9454 = (uint16_t)(192); + _curvea0[507] = _9454; + uint16_t _9455 = (uint16_t)(193); + _curvea0[508] = _9455; + uint16_t _9456 = (uint16_t)(193); + _curvea0[509] = _9456; + uint16_t _9457 = (uint16_t)(193); + _curvea0[510] = _9457; + uint16_t _9458 = (uint16_t)(193); + _curvea0[511] = _9458; + uint16_t _9459 = (uint16_t)(193); + _curvea0[512] = _9459; + uint16_t _9460 = (uint16_t)(194); + _curvea0[513] = _9460; + uint16_t _9461 = (uint16_t)(194); + _curvea0[514] = _9461; + uint16_t _9462 = (uint16_t)(194); + _curvea0[515] = _9462; + uint16_t _9463 = (uint16_t)(194); + _curvea0[516] = _9463; + uint16_t _9464 = (uint16_t)(194); + _curvea0[517] = _9464; + uint16_t _9465 = (uint16_t)(195); + _curvea0[518] = _9465; + uint16_t _9466 = (uint16_t)(195); + _curvea0[519] = _9466; + uint16_t _9467 = (uint16_t)(195); + _curvea0[520] = _9467; + uint16_t _9468 = (uint16_t)(195); + _curvea0[521] = _9468; + uint16_t _9469 = (uint16_t)(195); + _curvea0[522] = _9469; + uint16_t _9470 = (uint16_t)(195); + _curvea0[523] = _9470; + uint16_t _9471 = (uint16_t)(196); + _curvea0[524] = _9471; + uint16_t _9472 = (uint16_t)(196); + _curvea0[525] = _9472; + uint16_t _9473 = (uint16_t)(196); + _curvea0[526] = _9473; + uint16_t _9474 = (uint16_t)(196); + _curvea0[527] = _9474; + uint16_t _9475 = (uint16_t)(196); + _curvea0[528] = _9475; + uint16_t _9476 = (uint16_t)(197); + _curvea0[529] = _9476; + uint16_t _9477 = (uint16_t)(197); + _curvea0[530] = _9477; + uint16_t _9478 = (uint16_t)(197); + _curvea0[531] = _9478; + uint16_t _9479 = (uint16_t)(197); + _curvea0[532] = _9479; + uint16_t _9480 = (uint16_t)(197); + _curvea0[533] = _9480; + uint16_t _9481 = (uint16_t)(197); + _curvea0[534] = _9481; + uint16_t _9482 = (uint16_t)(198); + _curvea0[535] = _9482; + uint16_t _9483 = (uint16_t)(198); + _curvea0[536] = _9483; + uint16_t _9484 = (uint16_t)(198); + _curvea0[537] = _9484; + uint16_t _9485 = (uint16_t)(198); + _curvea0[538] = _9485; + uint16_t _9486 = (uint16_t)(198); + _curvea0[539] = _9486; + uint16_t _9487 = (uint16_t)(199); + _curvea0[540] = _9487; + uint16_t _9488 = (uint16_t)(199); + _curvea0[541] = _9488; + uint16_t _9489 = (uint16_t)(199); + _curvea0[542] = _9489; + uint16_t _9490 = (uint16_t)(199); + _curvea0[543] = _9490; + uint16_t _9491 = (uint16_t)(199); + _curvea0[544] = _9491; + uint16_t _9492 = (uint16_t)(199); + _curvea0[545] = _9492; + uint16_t _9493 = (uint16_t)(200); + _curvea0[546] = _9493; + uint16_t _9494 = (uint16_t)(200); + _curvea0[547] = _9494; + uint16_t _9495 = (uint16_t)(200); + _curvea0[548] = _9495; + uint16_t _9496 = (uint16_t)(200); + _curvea0[549] = _9496; + uint16_t _9497 = (uint16_t)(200); + _curvea0[550] = _9497; + uint16_t _9498 = (uint16_t)(200); + _curvea0[551] = _9498; + uint16_t _9499 = (uint16_t)(201); + _curvea0[552] = _9499; + uint16_t _9500 = (uint16_t)(201); + _curvea0[553] = _9500; + uint16_t _9501 = (uint16_t)(201); + _curvea0[554] = _9501; + uint16_t _9502 = (uint16_t)(201); + _curvea0[555] = _9502; + uint16_t _9503 = (uint16_t)(201); + _curvea0[556] = _9503; + uint16_t _9504 = (uint16_t)(202); + _curvea0[557] = _9504; + uint16_t _9505 = (uint16_t)(202); + _curvea0[558] = _9505; + uint16_t _9506 = (uint16_t)(202); + _curvea0[559] = _9506; + uint16_t _9507 = (uint16_t)(202); + _curvea0[560] = _9507; + uint16_t _9508 = (uint16_t)(202); + _curvea0[561] = _9508; + uint16_t _9509 = (uint16_t)(202); + _curvea0[562] = _9509; + uint16_t _9510 = (uint16_t)(203); + _curvea0[563] = _9510; + uint16_t _9511 = (uint16_t)(203); + _curvea0[564] = _9511; + uint16_t _9512 = (uint16_t)(203); + _curvea0[565] = _9512; + uint16_t _9513 = (uint16_t)(203); + _curvea0[566] = _9513; + uint16_t _9514 = (uint16_t)(203); + _curvea0[567] = _9514; + uint16_t _9515 = (uint16_t)(203); + _curvea0[568] = _9515; + uint16_t _9516 = (uint16_t)(204); + _curvea0[569] = _9516; + uint16_t _9517 = (uint16_t)(204); + _curvea0[570] = _9517; + uint16_t _9518 = (uint16_t)(204); + _curvea0[571] = _9518; + uint16_t _9519 = (uint16_t)(204); + _curvea0[572] = _9519; + uint16_t _9520 = (uint16_t)(204); + _curvea0[573] = _9520; + uint16_t _9521 = (uint16_t)(204); + _curvea0[574] = _9521; + uint16_t _9522 = (uint16_t)(205); + _curvea0[575] = _9522; + uint16_t _9523 = (uint16_t)(205); + _curvea0[576] = _9523; + uint16_t _9524 = (uint16_t)(205); + _curvea0[577] = _9524; + uint16_t _9525 = (uint16_t)(205); + _curvea0[578] = _9525; + uint16_t _9526 = (uint16_t)(205); + _curvea0[579] = _9526; + uint16_t _9527 = (uint16_t)(205); + _curvea0[580] = _9527; + uint16_t _9528 = (uint16_t)(206); + _curvea0[581] = _9528; + uint16_t _9529 = (uint16_t)(206); + _curvea0[582] = _9529; + uint16_t _9530 = (uint16_t)(206); + _curvea0[583] = _9530; + uint16_t _9531 = (uint16_t)(206); + _curvea0[584] = _9531; + uint16_t _9532 = (uint16_t)(206); + _curvea0[585] = _9532; + uint16_t _9533 = (uint16_t)(206); + _curvea0[586] = _9533; + uint16_t _9534 = (uint16_t)(207); + _curvea0[587] = _9534; + uint16_t _9535 = (uint16_t)(207); + _curvea0[588] = _9535; + uint16_t _9536 = (uint16_t)(207); + _curvea0[589] = _9536; + uint16_t _9537 = (uint16_t)(207); + _curvea0[590] = _9537; + uint16_t _9538 = (uint16_t)(207); + _curvea0[591] = _9538; + uint16_t _9539 = (uint16_t)(207); + _curvea0[592] = _9539; + uint16_t _9540 = (uint16_t)(208); + _curvea0[593] = _9540; + uint16_t _9541 = (uint16_t)(208); + _curvea0[594] = _9541; + uint16_t _9542 = (uint16_t)(208); + _curvea0[595] = _9542; + uint16_t _9543 = (uint16_t)(208); + _curvea0[596] = _9543; + uint16_t _9544 = (uint16_t)(208); + _curvea0[597] = _9544; + uint16_t _9545 = (uint16_t)(208); + _curvea0[598] = _9545; + uint16_t _9546 = (uint16_t)(209); + _curvea0[599] = _9546; + uint16_t _9547 = (uint16_t)(209); + _curvea0[600] = _9547; + uint16_t _9548 = (uint16_t)(209); + _curvea0[601] = _9548; + uint16_t _9549 = (uint16_t)(209); + _curvea0[602] = _9549; + uint16_t _9550 = (uint16_t)(209); + _curvea0[603] = _9550; + uint16_t _9551 = (uint16_t)(209); + _curvea0[604] = _9551; + uint16_t _9552 = (uint16_t)(209); + _curvea0[605] = _9552; + uint16_t _9553 = (uint16_t)(210); + _curvea0[606] = _9553; + uint16_t _9554 = (uint16_t)(210); + _curvea0[607] = _9554; + uint16_t _9555 = (uint16_t)(210); + _curvea0[608] = _9555; + uint16_t _9556 = (uint16_t)(210); + _curvea0[609] = _9556; + uint16_t _9557 = (uint16_t)(210); + _curvea0[610] = _9557; + uint16_t _9558 = (uint16_t)(210); + _curvea0[611] = _9558; + uint16_t _9559 = (uint16_t)(211); + _curvea0[612] = _9559; + uint16_t _9560 = (uint16_t)(211); + _curvea0[613] = _9560; + uint16_t _9561 = (uint16_t)(211); + _curvea0[614] = _9561; + uint16_t _9562 = (uint16_t)(211); + _curvea0[615] = _9562; + uint16_t _9563 = (uint16_t)(211); + _curvea0[616] = _9563; + uint16_t _9564 = (uint16_t)(211); + _curvea0[617] = _9564; + uint16_t _9565 = (uint16_t)(211); + _curvea0[618] = _9565; + uint16_t _9566 = (uint16_t)(212); + _curvea0[619] = _9566; + uint16_t _9567 = (uint16_t)(212); + _curvea0[620] = _9567; + uint16_t _9568 = (uint16_t)(212); + _curvea0[621] = _9568; + uint16_t _9569 = (uint16_t)(212); + _curvea0[622] = _9569; + uint16_t _9570 = (uint16_t)(212); + _curvea0[623] = _9570; + uint16_t _9571 = (uint16_t)(212); + _curvea0[624] = _9571; + uint16_t _9572 = (uint16_t)(213); + _curvea0[625] = _9572; + uint16_t _9573 = (uint16_t)(213); + _curvea0[626] = _9573; + uint16_t _9574 = (uint16_t)(213); + _curvea0[627] = _9574; + uint16_t _9575 = (uint16_t)(213); + _curvea0[628] = _9575; + uint16_t _9576 = (uint16_t)(213); + _curvea0[629] = _9576; + uint16_t _9577 = (uint16_t)(213); + _curvea0[630] = _9577; + uint16_t _9578 = (uint16_t)(213); + _curvea0[631] = _9578; + uint16_t _9579 = (uint16_t)(214); + _curvea0[632] = _9579; + uint16_t _9580 = (uint16_t)(214); + _curvea0[633] = _9580; + uint16_t _9581 = (uint16_t)(214); + _curvea0[634] = _9581; + uint16_t _9582 = (uint16_t)(214); + _curvea0[635] = _9582; + uint16_t _9583 = (uint16_t)(214); + _curvea0[636] = _9583; + uint16_t _9584 = (uint16_t)(214); + _curvea0[637] = _9584; + uint16_t _9585 = (uint16_t)(214); + _curvea0[638] = _9585; + uint16_t _9586 = (uint16_t)(215); + _curvea0[639] = _9586; + uint16_t _9587 = (uint16_t)(215); + _curvea0[640] = _9587; + uint16_t _9588 = (uint16_t)(215); + _curvea0[641] = _9588; + uint16_t _9589 = (uint16_t)(215); + _curvea0[642] = _9589; + uint16_t _9590 = (uint16_t)(215); + _curvea0[643] = _9590; + uint16_t _9591 = (uint16_t)(215); + _curvea0[644] = _9591; + uint16_t _9592 = (uint16_t)(216); + _curvea0[645] = _9592; + uint16_t _9593 = (uint16_t)(216); + _curvea0[646] = _9593; + uint16_t _9594 = (uint16_t)(216); + _curvea0[647] = _9594; + uint16_t _9595 = (uint16_t)(216); + _curvea0[648] = _9595; + uint16_t _9596 = (uint16_t)(216); + _curvea0[649] = _9596; + uint16_t _9597 = (uint16_t)(216); + _curvea0[650] = _9597; + uint16_t _9598 = (uint16_t)(216); + _curvea0[651] = _9598; + uint16_t _9599 = (uint16_t)(217); + _curvea0[652] = _9599; + uint16_t _9600 = (uint16_t)(217); + _curvea0[653] = _9600; + uint16_t _9601 = (uint16_t)(217); + _curvea0[654] = _9601; + uint16_t _9602 = (uint16_t)(217); + _curvea0[655] = _9602; + uint16_t _9603 = (uint16_t)(217); + _curvea0[656] = _9603; + uint16_t _9604 = (uint16_t)(217); + _curvea0[657] = _9604; + uint16_t _9605 = (uint16_t)(217); + _curvea0[658] = _9605; + uint16_t _9606 = (uint16_t)(218); + _curvea0[659] = _9606; + uint16_t _9607 = (uint16_t)(218); + _curvea0[660] = _9607; + uint16_t _9608 = (uint16_t)(218); + _curvea0[661] = _9608; + uint16_t _9609 = (uint16_t)(218); + _curvea0[662] = _9609; + uint16_t _9610 = (uint16_t)(218); + _curvea0[663] = _9610; + uint16_t _9611 = (uint16_t)(218); + _curvea0[664] = _9611; + uint16_t _9612 = (uint16_t)(218); + _curvea0[665] = _9612; + uint16_t _9613 = (uint16_t)(219); + _curvea0[666] = _9613; + uint16_t _9614 = (uint16_t)(219); + _curvea0[667] = _9614; + uint16_t _9615 = (uint16_t)(219); + _curvea0[668] = _9615; + uint16_t _9616 = (uint16_t)(219); + _curvea0[669] = _9616; + uint16_t _9617 = (uint16_t)(219); + _curvea0[670] = _9617; + uint16_t _9618 = (uint16_t)(219); + _curvea0[671] = _9618; + uint16_t _9619 = (uint16_t)(219); + _curvea0[672] = _9619; + uint16_t _9620 = (uint16_t)(220); + _curvea0[673] = _9620; + uint16_t _9621 = (uint16_t)(220); + _curvea0[674] = _9621; + uint16_t _9622 = (uint16_t)(220); + _curvea0[675] = _9622; + uint16_t _9623 = (uint16_t)(220); + _curvea0[676] = _9623; + uint16_t _9624 = (uint16_t)(220); + _curvea0[677] = _9624; + uint16_t _9625 = (uint16_t)(220); + _curvea0[678] = _9625; + uint16_t _9626 = (uint16_t)(220); + _curvea0[679] = _9626; + uint16_t _9627 = (uint16_t)(220); + _curvea0[680] = _9627; + uint16_t _9628 = (uint16_t)(221); + _curvea0[681] = _9628; + uint16_t _9629 = (uint16_t)(221); + _curvea0[682] = _9629; + uint16_t _9630 = (uint16_t)(221); + _curvea0[683] = _9630; + uint16_t _9631 = (uint16_t)(221); + _curvea0[684] = _9631; + uint16_t _9632 = (uint16_t)(221); + _curvea0[685] = _9632; + uint16_t _9633 = (uint16_t)(221); + _curvea0[686] = _9633; + uint16_t _9634 = (uint16_t)(221); + _curvea0[687] = _9634; + uint16_t _9635 = (uint16_t)(222); + _curvea0[688] = _9635; + uint16_t _9636 = (uint16_t)(222); + _curvea0[689] = _9636; + uint16_t _9637 = (uint16_t)(222); + _curvea0[690] = _9637; + uint16_t _9638 = (uint16_t)(222); + _curvea0[691] = _9638; + uint16_t _9639 = (uint16_t)(222); + _curvea0[692] = _9639; + uint16_t _9640 = (uint16_t)(222); + _curvea0[693] = _9640; + uint16_t _9641 = (uint16_t)(222); + _curvea0[694] = _9641; + uint16_t _9642 = (uint16_t)(223); + _curvea0[695] = _9642; + uint16_t _9643 = (uint16_t)(223); + _curvea0[696] = _9643; + uint16_t _9644 = (uint16_t)(223); + _curvea0[697] = _9644; + uint16_t _9645 = (uint16_t)(223); + _curvea0[698] = _9645; + uint16_t _9646 = (uint16_t)(223); + _curvea0[699] = _9646; + uint16_t _9647 = (uint16_t)(223); + _curvea0[700] = _9647; + uint16_t _9648 = (uint16_t)(223); + _curvea0[701] = _9648; + uint16_t _9649 = (uint16_t)(223); + _curvea0[702] = _9649; + uint16_t _9650 = (uint16_t)(224); + _curvea0[703] = _9650; + uint16_t _9651 = (uint16_t)(224); + _curvea0[704] = _9651; + uint16_t _9652 = (uint16_t)(224); + _curvea0[705] = _9652; + uint16_t _9653 = (uint16_t)(224); + _curvea0[706] = _9653; + uint16_t _9654 = (uint16_t)(224); + _curvea0[707] = _9654; + uint16_t _9655 = (uint16_t)(224); + _curvea0[708] = _9655; + uint16_t _9656 = (uint16_t)(224); + _curvea0[709] = _9656; + uint16_t _9657 = (uint16_t)(224); + _curvea0[710] = _9657; + uint16_t _9658 = (uint16_t)(225); + _curvea0[711] = _9658; + uint16_t _9659 = (uint16_t)(225); + _curvea0[712] = _9659; + uint16_t _9660 = (uint16_t)(225); + _curvea0[713] = _9660; + uint16_t _9661 = (uint16_t)(225); + _curvea0[714] = _9661; + uint16_t _9662 = (uint16_t)(225); + _curvea0[715] = _9662; + uint16_t _9663 = (uint16_t)(225); + _curvea0[716] = _9663; + uint16_t _9664 = (uint16_t)(225); + _curvea0[717] = _9664; + uint16_t _9665 = (uint16_t)(226); + _curvea0[718] = _9665; + uint16_t _9666 = (uint16_t)(226); + _curvea0[719] = _9666; + uint16_t _9667 = (uint16_t)(226); + _curvea0[720] = _9667; + uint16_t _9668 = (uint16_t)(226); + _curvea0[721] = _9668; + uint16_t _9669 = (uint16_t)(226); + _curvea0[722] = _9669; + uint16_t _9670 = (uint16_t)(226); + _curvea0[723] = _9670; + uint16_t _9671 = (uint16_t)(226); + _curvea0[724] = _9671; + uint16_t _9672 = (uint16_t)(226); + _curvea0[725] = _9672; + uint16_t _9673 = (uint16_t)(227); + _curvea0[726] = _9673; + uint16_t _9674 = (uint16_t)(227); + _curvea0[727] = _9674; + uint16_t _9675 = (uint16_t)(227); + _curvea0[728] = _9675; + uint16_t _9676 = (uint16_t)(227); + _curvea0[729] = _9676; + uint16_t _9677 = (uint16_t)(227); + _curvea0[730] = _9677; + uint16_t _9678 = (uint16_t)(227); + _curvea0[731] = _9678; + uint16_t _9679 = (uint16_t)(227); + _curvea0[732] = _9679; + uint16_t _9680 = (uint16_t)(227); + _curvea0[733] = _9680; + uint16_t _9681 = (uint16_t)(228); + _curvea0[734] = _9681; + uint16_t _9682 = (uint16_t)(228); + _curvea0[735] = _9682; + uint16_t _9683 = (uint16_t)(228); + _curvea0[736] = _9683; + uint16_t _9684 = (uint16_t)(228); + _curvea0[737] = _9684; + uint16_t _9685 = (uint16_t)(228); + _curvea0[738] = _9685; + uint16_t _9686 = (uint16_t)(228); + _curvea0[739] = _9686; + uint16_t _9687 = (uint16_t)(228); + _curvea0[740] = _9687; + uint16_t _9688 = (uint16_t)(228); + _curvea0[741] = _9688; + uint16_t _9689 = (uint16_t)(228); + _curvea0[742] = _9689; + uint16_t _9690 = (uint16_t)(229); + _curvea0[743] = _9690; + uint16_t _9691 = (uint16_t)(229); + _curvea0[744] = _9691; + uint16_t _9692 = (uint16_t)(229); + _curvea0[745] = _9692; + uint16_t _9693 = (uint16_t)(229); + _curvea0[746] = _9693; + uint16_t _9694 = (uint16_t)(229); + _curvea0[747] = _9694; + uint16_t _9695 = (uint16_t)(229); + _curvea0[748] = _9695; + uint16_t _9696 = (uint16_t)(229); + _curvea0[749] = _9696; + uint16_t _9697 = (uint16_t)(229); + _curvea0[750] = _9697; + uint16_t _9698 = (uint16_t)(230); + _curvea0[751] = _9698; + uint16_t _9699 = (uint16_t)(230); + _curvea0[752] = _9699; + uint16_t _9700 = (uint16_t)(230); + _curvea0[753] = _9700; + uint16_t _9701 = (uint16_t)(230); + _curvea0[754] = _9701; + uint16_t _9702 = (uint16_t)(230); + _curvea0[755] = _9702; + uint16_t _9703 = (uint16_t)(230); + _curvea0[756] = _9703; + uint16_t _9704 = (uint16_t)(230); + _curvea0[757] = _9704; + uint16_t _9705 = (uint16_t)(230); + _curvea0[758] = _9705; + uint16_t _9706 = (uint16_t)(231); + _curvea0[759] = _9706; + uint16_t _9707 = (uint16_t)(231); + _curvea0[760] = _9707; + uint16_t _9708 = (uint16_t)(231); + _curvea0[761] = _9708; + uint16_t _9709 = (uint16_t)(231); + _curvea0[762] = _9709; + uint16_t _9710 = (uint16_t)(231); + _curvea0[763] = _9710; + uint16_t _9711 = (uint16_t)(231); + _curvea0[764] = _9711; + uint16_t _9712 = (uint16_t)(231); + _curvea0[765] = _9712; + uint16_t _9713 = (uint16_t)(231); + _curvea0[766] = _9713; + uint16_t _9714 = (uint16_t)(231); + _curvea0[767] = _9714; + uint16_t _9715 = (uint16_t)(232); + _curvea0[768] = _9715; + uint16_t _9716 = (uint16_t)(232); + _curvea0[769] = _9716; + uint16_t _9717 = (uint16_t)(232); + _curvea0[770] = _9717; + uint16_t _9718 = (uint16_t)(232); + _curvea0[771] = _9718; + uint16_t _9719 = (uint16_t)(232); + _curvea0[772] = _9719; + uint16_t _9720 = (uint16_t)(232); + _curvea0[773] = _9720; + uint16_t _9721 = (uint16_t)(232); + _curvea0[774] = _9721; + uint16_t _9722 = (uint16_t)(232); + _curvea0[775] = _9722; + uint16_t _9723 = (uint16_t)(233); + _curvea0[776] = _9723; + uint16_t _9724 = (uint16_t)(233); + _curvea0[777] = _9724; + uint16_t _9725 = (uint16_t)(233); + _curvea0[778] = _9725; + uint16_t _9726 = (uint16_t)(233); + _curvea0[779] = _9726; + uint16_t _9727 = (uint16_t)(233); + _curvea0[780] = _9727; + uint16_t _9728 = (uint16_t)(233); + _curvea0[781] = _9728; + uint16_t _9729 = (uint16_t)(233); + _curvea0[782] = _9729; + uint16_t _9730 = (uint16_t)(233); + _curvea0[783] = _9730; + uint16_t _9731 = (uint16_t)(233); + _curvea0[784] = _9731; + uint16_t _9732 = (uint16_t)(234); + _curvea0[785] = _9732; + uint16_t _9733 = (uint16_t)(234); + _curvea0[786] = _9733; + uint16_t _9734 = (uint16_t)(234); + _curvea0[787] = _9734; + uint16_t _9735 = (uint16_t)(234); + _curvea0[788] = _9735; + uint16_t _9736 = (uint16_t)(234); + _curvea0[789] = _9736; + uint16_t _9737 = (uint16_t)(234); + _curvea0[790] = _9737; + uint16_t _9738 = (uint16_t)(234); + _curvea0[791] = _9738; + uint16_t _9739 = (uint16_t)(234); + _curvea0[792] = _9739; + uint16_t _9740 = (uint16_t)(234); + _curvea0[793] = _9740; + uint16_t _9741 = (uint16_t)(235); + _curvea0[794] = _9741; + uint16_t _9742 = (uint16_t)(235); + _curvea0[795] = _9742; + uint16_t _9743 = (uint16_t)(235); + _curvea0[796] = _9743; + uint16_t _9744 = (uint16_t)(235); + _curvea0[797] = _9744; + uint16_t _9745 = (uint16_t)(235); + _curvea0[798] = _9745; + uint16_t _9746 = (uint16_t)(235); + _curvea0[799] = _9746; + uint16_t _9747 = (uint16_t)(235); + _curvea0[800] = _9747; + uint16_t _9748 = (uint16_t)(235); + _curvea0[801] = _9748; + uint16_t _9749 = (uint16_t)(235); + _curvea0[802] = _9749; + uint16_t _9750 = (uint16_t)(236); + _curvea0[803] = _9750; + uint16_t _9751 = (uint16_t)(236); + _curvea0[804] = _9751; + uint16_t _9752 = (uint16_t)(236); + _curvea0[805] = _9752; + uint16_t _9753 = (uint16_t)(236); + _curvea0[806] = _9753; + uint16_t _9754 = (uint16_t)(236); + _curvea0[807] = _9754; + uint16_t _9755 = (uint16_t)(236); + _curvea0[808] = _9755; + uint16_t _9756 = (uint16_t)(236); + _curvea0[809] = _9756; + uint16_t _9757 = (uint16_t)(236); + _curvea0[810] = _9757; + uint16_t _9758 = (uint16_t)(236); + _curvea0[811] = _9758; + uint16_t _9759 = (uint16_t)(237); + _curvea0[812] = _9759; + uint16_t _9760 = (uint16_t)(237); + _curvea0[813] = _9760; + uint16_t _9761 = (uint16_t)(237); + _curvea0[814] = _9761; + uint16_t _9762 = (uint16_t)(237); + _curvea0[815] = _9762; + uint16_t _9763 = (uint16_t)(237); + _curvea0[816] = _9763; + uint16_t _9764 = (uint16_t)(237); + _curvea0[817] = _9764; + uint16_t _9765 = (uint16_t)(237); + _curvea0[818] = _9765; + uint16_t _9766 = (uint16_t)(237); + _curvea0[819] = _9766; + uint16_t _9767 = (uint16_t)(237); + _curvea0[820] = _9767; + uint16_t _9768 = (uint16_t)(237); + _curvea0[821] = _9768; + uint16_t _9769 = (uint16_t)(238); + _curvea0[822] = _9769; + uint16_t _9770 = (uint16_t)(238); + _curvea0[823] = _9770; + uint16_t _9771 = (uint16_t)(238); + _curvea0[824] = _9771; + uint16_t _9772 = (uint16_t)(238); + _curvea0[825] = _9772; + uint16_t _9773 = (uint16_t)(238); + _curvea0[826] = _9773; + uint16_t _9774 = (uint16_t)(238); + _curvea0[827] = _9774; + uint16_t _9775 = (uint16_t)(238); + _curvea0[828] = _9775; + uint16_t _9776 = (uint16_t)(238); + _curvea0[829] = _9776; + uint16_t _9777 = (uint16_t)(238); + _curvea0[830] = _9777; + uint16_t _9778 = (uint16_t)(239); + _curvea0[831] = _9778; + uint16_t _9779 = (uint16_t)(239); + _curvea0[832] = _9779; + uint16_t _9780 = (uint16_t)(239); + _curvea0[833] = _9780; + uint16_t _9781 = (uint16_t)(239); + _curvea0[834] = _9781; + uint16_t _9782 = (uint16_t)(239); + _curvea0[835] = _9782; + uint16_t _9783 = (uint16_t)(239); + _curvea0[836] = _9783; + uint16_t _9784 = (uint16_t)(239); + _curvea0[837] = _9784; + uint16_t _9785 = (uint16_t)(239); + _curvea0[838] = _9785; + uint16_t _9786 = (uint16_t)(239); + _curvea0[839] = _9786; + uint16_t _9787 = (uint16_t)(239); + _curvea0[840] = _9787; + uint16_t _9788 = (uint16_t)(240); + _curvea0[841] = _9788; + uint16_t _9789 = (uint16_t)(240); + _curvea0[842] = _9789; + uint16_t _9790 = (uint16_t)(240); + _curvea0[843] = _9790; + uint16_t _9791 = (uint16_t)(240); + _curvea0[844] = _9791; + uint16_t _9792 = (uint16_t)(240); + _curvea0[845] = _9792; + uint16_t _9793 = (uint16_t)(240); + _curvea0[846] = _9793; + uint16_t _9794 = (uint16_t)(240); + _curvea0[847] = _9794; + uint16_t _9795 = (uint16_t)(240); + _curvea0[848] = _9795; + uint16_t _9796 = (uint16_t)(240); + _curvea0[849] = _9796; + uint16_t _9797 = (uint16_t)(240); + _curvea0[850] = _9797; + uint16_t _9798 = (uint16_t)(241); + _curvea0[851] = _9798; + uint16_t _9799 = (uint16_t)(241); + _curvea0[852] = _9799; + uint16_t _9800 = (uint16_t)(241); + _curvea0[853] = _9800; + uint16_t _9801 = (uint16_t)(241); + _curvea0[854] = _9801; + uint16_t _9802 = (uint16_t)(241); + _curvea0[855] = _9802; + uint16_t _9803 = (uint16_t)(241); + _curvea0[856] = _9803; + uint16_t _9804 = (uint16_t)(241); + _curvea0[857] = _9804; + uint16_t _9805 = (uint16_t)(241); + _curvea0[858] = _9805; + uint16_t _9806 = (uint16_t)(241); + _curvea0[859] = _9806; + uint16_t _9807 = (uint16_t)(241); + _curvea0[860] = _9807; + uint16_t _9808 = (uint16_t)(242); + _curvea0[861] = _9808; + uint16_t _9809 = (uint16_t)(242); + _curvea0[862] = _9809; + uint16_t _9810 = (uint16_t)(242); + _curvea0[863] = _9810; + uint16_t _9811 = (uint16_t)(242); + _curvea0[864] = _9811; + uint16_t _9812 = (uint16_t)(242); + _curvea0[865] = _9812; + uint16_t _9813 = (uint16_t)(242); + _curvea0[866] = _9813; + uint16_t _9814 = (uint16_t)(242); + _curvea0[867] = _9814; + uint16_t _9815 = (uint16_t)(242); + _curvea0[868] = _9815; + uint16_t _9816 = (uint16_t)(242); + _curvea0[869] = _9816; + uint16_t _9817 = (uint16_t)(242); + _curvea0[870] = _9817; + uint16_t _9818 = (uint16_t)(243); + _curvea0[871] = _9818; + uint16_t _9819 = (uint16_t)(243); + _curvea0[872] = _9819; + uint16_t _9820 = (uint16_t)(243); + _curvea0[873] = _9820; + uint16_t _9821 = (uint16_t)(243); + _curvea0[874] = _9821; + uint16_t _9822 = (uint16_t)(243); + _curvea0[875] = _9822; + uint16_t _9823 = (uint16_t)(243); + _curvea0[876] = _9823; + uint16_t _9824 = (uint16_t)(243); + _curvea0[877] = _9824; + uint16_t _9825 = (uint16_t)(243); + _curvea0[878] = _9825; + uint16_t _9826 = (uint16_t)(243); + _curvea0[879] = _9826; + uint16_t _9827 = (uint16_t)(243); + _curvea0[880] = _9827; + uint16_t _9828 = (uint16_t)(244); + _curvea0[881] = _9828; + uint16_t _9829 = (uint16_t)(244); + _curvea0[882] = _9829; + uint16_t _9830 = (uint16_t)(244); + _curvea0[883] = _9830; + uint16_t _9831 = (uint16_t)(244); + _curvea0[884] = _9831; + uint16_t _9832 = (uint16_t)(244); + _curvea0[885] = _9832; + uint16_t _9833 = (uint16_t)(244); + _curvea0[886] = _9833; + uint16_t _9834 = (uint16_t)(244); + _curvea0[887] = _9834; + uint16_t _9835 = (uint16_t)(244); + _curvea0[888] = _9835; + uint16_t _9836 = (uint16_t)(244); + _curvea0[889] = _9836; + uint16_t _9837 = (uint16_t)(244); + _curvea0[890] = _9837; + uint16_t _9838 = (uint16_t)(244); + _curvea0[891] = _9838; + uint16_t _9839 = (uint16_t)(245); + _curvea0[892] = _9839; + uint16_t _9840 = (uint16_t)(245); + _curvea0[893] = _9840; + uint16_t _9841 = (uint16_t)(245); + _curvea0[894] = _9841; + uint16_t _9842 = (uint16_t)(245); + _curvea0[895] = _9842; + uint16_t _9843 = (uint16_t)(245); + _curvea0[896] = _9843; + uint16_t _9844 = (uint16_t)(245); + _curvea0[897] = _9844; + uint16_t _9845 = (uint16_t)(245); + _curvea0[898] = _9845; + uint16_t _9846 = (uint16_t)(245); + _curvea0[899] = _9846; + uint16_t _9847 = (uint16_t)(245); + _curvea0[900] = _9847; + uint16_t _9848 = (uint16_t)(245); + _curvea0[901] = _9848; + uint16_t _9849 = (uint16_t)(245); + _curvea0[902] = _9849; + uint16_t _9850 = (uint16_t)(246); + _curvea0[903] = _9850; + uint16_t _9851 = (uint16_t)(246); + _curvea0[904] = _9851; + uint16_t _9852 = (uint16_t)(246); + _curvea0[905] = _9852; + uint16_t _9853 = (uint16_t)(246); + _curvea0[906] = _9853; + uint16_t _9854 = (uint16_t)(246); + _curvea0[907] = _9854; + uint16_t _9855 = (uint16_t)(246); + _curvea0[908] = _9855; + uint16_t _9856 = (uint16_t)(246); + _curvea0[909] = _9856; + uint16_t _9857 = (uint16_t)(246); + _curvea0[910] = _9857; + uint16_t _9858 = (uint16_t)(246); + _curvea0[911] = _9858; + uint16_t _9859 = (uint16_t)(246); + _curvea0[912] = _9859; + uint16_t _9860 = (uint16_t)(246); + _curvea0[913] = _9860; + uint16_t _9861 = (uint16_t)(247); + _curvea0[914] = _9861; + uint16_t _9862 = (uint16_t)(247); + _curvea0[915] = _9862; + uint16_t _9863 = (uint16_t)(247); + _curvea0[916] = _9863; + uint16_t _9864 = (uint16_t)(247); + _curvea0[917] = _9864; + uint16_t _9865 = (uint16_t)(247); + _curvea0[918] = _9865; + uint16_t _9866 = (uint16_t)(247); + _curvea0[919] = _9866; + uint16_t _9867 = (uint16_t)(247); + _curvea0[920] = _9867; + uint16_t _9868 = (uint16_t)(247); + _curvea0[921] = _9868; + uint16_t _9869 = (uint16_t)(247); + _curvea0[922] = _9869; + uint16_t _9870 = (uint16_t)(247); + _curvea0[923] = _9870; + uint16_t _9871 = (uint16_t)(247); + _curvea0[924] = _9871; + uint16_t _9872 = (uint16_t)(248); + _curvea0[925] = _9872; + uint16_t _9873 = (uint16_t)(248); + _curvea0[926] = _9873; + uint16_t _9874 = (uint16_t)(248); + _curvea0[927] = _9874; + uint16_t _9875 = (uint16_t)(248); + _curvea0[928] = _9875; + uint16_t _9876 = (uint16_t)(248); + _curvea0[929] = _9876; + uint16_t _9877 = (uint16_t)(248); + _curvea0[930] = _9877; + uint16_t _9878 = (uint16_t)(248); + _curvea0[931] = _9878; + uint16_t _9879 = (uint16_t)(248); + _curvea0[932] = _9879; + uint16_t _9880 = (uint16_t)(248); + _curvea0[933] = _9880; + uint16_t _9881 = (uint16_t)(248); + _curvea0[934] = _9881; + uint16_t _9882 = (uint16_t)(248); + _curvea0[935] = _9882; + uint16_t _9883 = (uint16_t)(249); + _curvea0[936] = _9883; + uint16_t _9884 = (uint16_t)(249); + _curvea0[937] = _9884; + uint16_t _9885 = (uint16_t)(249); + _curvea0[938] = _9885; + uint16_t _9886 = (uint16_t)(249); + _curvea0[939] = _9886; + uint16_t _9887 = (uint16_t)(249); + _curvea0[940] = _9887; + uint16_t _9888 = (uint16_t)(249); + _curvea0[941] = _9888; + uint16_t _9889 = (uint16_t)(249); + _curvea0[942] = _9889; + uint16_t _9890 = (uint16_t)(249); + _curvea0[943] = _9890; + uint16_t _9891 = (uint16_t)(249); + _curvea0[944] = _9891; + uint16_t _9892 = (uint16_t)(249); + _curvea0[945] = _9892; + uint16_t _9893 = (uint16_t)(249); + _curvea0[946] = _9893; + uint16_t _9894 = (uint16_t)(249); + _curvea0[947] = _9894; + uint16_t _9895 = (uint16_t)(250); + _curvea0[948] = _9895; + uint16_t _9896 = (uint16_t)(250); + _curvea0[949] = _9896; + uint16_t _9897 = (uint16_t)(250); + _curvea0[950] = _9897; + uint16_t _9898 = (uint16_t)(250); + _curvea0[951] = _9898; + uint16_t _9899 = (uint16_t)(250); + _curvea0[952] = _9899; + uint16_t _9900 = (uint16_t)(250); + _curvea0[953] = _9900; + uint16_t _9901 = (uint16_t)(250); + _curvea0[954] = _9901; + uint16_t _9902 = (uint16_t)(250); + _curvea0[955] = _9902; + uint16_t _9903 = (uint16_t)(250); + _curvea0[956] = _9903; + uint16_t _9904 = (uint16_t)(250); + _curvea0[957] = _9904; + uint16_t _9905 = (uint16_t)(250); + _curvea0[958] = _9905; + uint16_t _9906 = (uint16_t)(250); + _curvea0[959] = _9906; + uint16_t _9907 = (uint16_t)(251); + _curvea0[960] = _9907; + uint16_t _9908 = (uint16_t)(251); + _curvea0[961] = _9908; + uint16_t _9909 = (uint16_t)(251); + _curvea0[962] = _9909; + uint16_t _9910 = (uint16_t)(251); + _curvea0[963] = _9910; + uint16_t _9911 = (uint16_t)(251); + _curvea0[964] = _9911; + uint16_t _9912 = (uint16_t)(251); + _curvea0[965] = _9912; + uint16_t _9913 = (uint16_t)(251); + _curvea0[966] = _9913; + uint16_t _9914 = (uint16_t)(251); + _curvea0[967] = _9914; + uint16_t _9915 = (uint16_t)(251); + _curvea0[968] = _9915; + uint16_t _9916 = (uint16_t)(251); + _curvea0[969] = _9916; + uint16_t _9917 = (uint16_t)(251); + _curvea0[970] = _9917; + uint16_t _9918 = (uint16_t)(251); + _curvea0[971] = _9918; + uint16_t _9919 = (uint16_t)(252); + _curvea0[972] = _9919; + uint16_t _9920 = (uint16_t)(252); + _curvea0[973] = _9920; + uint16_t _9921 = (uint16_t)(252); + _curvea0[974] = _9921; + uint16_t _9922 = (uint16_t)(252); + _curvea0[975] = _9922; + uint16_t _9923 = (uint16_t)(252); + _curvea0[976] = _9923; + uint16_t _9924 = (uint16_t)(252); + _curvea0[977] = _9924; + uint16_t _9925 = (uint16_t)(252); + _curvea0[978] = _9925; + uint16_t _9926 = (uint16_t)(252); + _curvea0[979] = _9926; + uint16_t _9927 = (uint16_t)(252); + _curvea0[980] = _9927; + uint16_t _9928 = (uint16_t)(252); + _curvea0[981] = _9928; + uint16_t _9929 = (uint16_t)(252); + _curvea0[982] = _9929; + uint16_t _9930 = (uint16_t)(252); + _curvea0[983] = _9930; + uint16_t _9931 = (uint16_t)(252); + _curvea0[984] = _9931; + uint16_t _9932 = (uint16_t)(253); + _curvea0[985] = _9932; + uint16_t _9933 = (uint16_t)(253); + _curvea0[986] = _9933; + uint16_t _9934 = (uint16_t)(253); + _curvea0[987] = _9934; + uint16_t _9935 = (uint16_t)(253); + _curvea0[988] = _9935; + uint16_t _9936 = (uint16_t)(253); + _curvea0[989] = _9936; + uint16_t _9937 = (uint16_t)(253); + _curvea0[990] = _9937; + uint16_t _9938 = (uint16_t)(253); + _curvea0[991] = _9938; + uint16_t _9939 = (uint16_t)(253); + _curvea0[992] = _9939; + uint16_t _9940 = (uint16_t)(253); + _curvea0[993] = _9940; + uint16_t _9941 = (uint16_t)(253); + _curvea0[994] = _9941; + uint16_t _9942 = (uint16_t)(253); + _curvea0[995] = _9942; + uint16_t _9943 = (uint16_t)(253); + _curvea0[996] = _9943; + uint16_t _9944 = (uint16_t)(253); + _curvea0[997] = _9944; + uint16_t _9945 = (uint16_t)(254); + _curvea0[998] = _9945; + uint16_t _9946 = (uint16_t)(254); + _curvea0[999] = _9946; + uint16_t _9947 = (uint16_t)(254); + _curvea0[1000] = _9947; + uint16_t _9948 = (uint16_t)(254); + _curvea0[1001] = _9948; + uint16_t _9949 = (uint16_t)(254); + _curvea0[1002] = _9949; + uint16_t _9950 = (uint16_t)(254); + _curvea0[1003] = _9950; + uint16_t _9951 = (uint16_t)(254); + _curvea0[1004] = _9951; + uint16_t _9952 = (uint16_t)(254); + _curvea0[1005] = _9952; + uint16_t _9953 = (uint16_t)(254); + _curvea0[1006] = _9953; + uint16_t _9954 = (uint16_t)(254); + _curvea0[1007] = _9954; + uint16_t _9955 = (uint16_t)(254); + _curvea0[1008] = _9955; + uint16_t _9956 = (uint16_t)(254); + _curvea0[1009] = _9956; + uint16_t _9957 = (uint16_t)(254); + _curvea0[1010] = _9957; + uint16_t _9958 = (uint16_t)(255); + _curvea0[1011] = _9958; + uint16_t _9959 = (uint16_t)(255); + _curvea0[1012] = _9959; + uint16_t _9960 = (uint16_t)(255); + _curvea0[1013] = _9960; + uint16_t _9961 = (uint16_t)(255); + _curvea0[1014] = _9961; + uint16_t _9962 = (uint16_t)(255); + _curvea0[1015] = _9962; + uint16_t _9963 = (uint16_t)(255); + _curvea0[1016] = _9963; + uint16_t _9964 = (uint16_t)(255); + _curvea0[1017] = _9964; + uint16_t _9965 = (uint16_t)(255); + _curvea0[1018] = _9965; + uint16_t _9966 = (uint16_t)(255); + _curvea0[1019] = _9966; + uint16_t _9967 = (uint16_t)(255); + _curvea0[1020] = _9967; + uint16_t _9968 = (uint16_t)(255); + _curvea0[1021] = _9968; + uint16_t _9969 = (uint16_t)(255); + _curvea0[1022] = _9969; + uint16_t _9970 = (uint16_t)(255); + _curvea0[1023] = _9970; + + int16_t _9971 = (int16_t)(1023); + int16_t _9972 = min(_corrected_stencil_7, _9971); + int16_t _9973 = (int16_t)(0); + int16_t _9974 = max(_9972, _9973); + uint16_t _9975 = (uint16_t)(_9974); + int32_t _9976 = (int32_t)(_9975); + uint16_t _9977 = ((const uint16_t *)_curvea0)[_9976]; + return _9977; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_7(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_8 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _9995 = (uint16_t)(0); + _curvea0[0] = _9995; + uint16_t _9996 = (uint16_t)(4); + _curvea0[1] = _9996; + uint16_t _9997 = (uint16_t)(7); + _curvea0[2] = _9997; + uint16_t _9998 = (uint16_t)(8); + _curvea0[3] = _9998; + uint16_t _9999 = (uint16_t)(10); + _curvea0[4] = _9999; + uint16_t _10000 = (uint16_t)(11); + _curvea0[5] = _10000; + uint16_t _10001 = (uint16_t)(12); + _curvea0[6] = _10001; + uint16_t _10002 = (uint16_t)(13); + _curvea0[7] = _10002; + uint16_t _10003 = (uint16_t)(14); + _curvea0[8] = _10003; + uint16_t _10004 = (uint16_t)(15); + _curvea0[9] = _10004; + uint16_t _10005 = (uint16_t)(16); + _curvea0[10] = _10005; + uint16_t _10006 = (uint16_t)(17); + _curvea0[11] = _10006; + uint16_t _10007 = (uint16_t)(18); + _curvea0[12] = _10007; + uint16_t _10008 = (uint16_t)(19); + _curvea0[13] = _10008; + uint16_t _10009 = (uint16_t)(20); + _curvea0[14] = _10009; + uint16_t _10010 = (uint16_t)(21); + _curvea0[15] = _10010; + uint16_t _10011 = (uint16_t)(22); + _curvea0[16] = _10011; + uint16_t _10012 = (uint16_t)(22); + _curvea0[17] = _10012; + uint16_t _10013 = (uint16_t)(23); + _curvea0[18] = _10013; + uint16_t _10014 = (uint16_t)(24); + _curvea0[19] = _10014; + uint16_t _10015 = (uint16_t)(25); + _curvea0[20] = _10015; + uint16_t _10016 = (uint16_t)(25); + _curvea0[21] = _10016; + uint16_t _10017 = (uint16_t)(26); + _curvea0[22] = _10017; + uint16_t _10018 = (uint16_t)(27); + _curvea0[23] = _10018; + uint16_t _10019 = (uint16_t)(27); + _curvea0[24] = _10019; + uint16_t _10020 = (uint16_t)(28); + _curvea0[25] = _10020; + uint16_t _10021 = (uint16_t)(29); + _curvea0[26] = _10021; + uint16_t _10022 = (uint16_t)(29); + _curvea0[27] = _10022; + uint16_t _10023 = (uint16_t)(30); + _curvea0[28] = _10023; + uint16_t _10024 = (uint16_t)(31); + _curvea0[29] = _10024; + uint16_t _10025 = (uint16_t)(31); + _curvea0[30] = _10025; + uint16_t _10026 = (uint16_t)(32); + _curvea0[31] = _10026; + uint16_t _10027 = (uint16_t)(33); + _curvea0[32] = _10027; + uint16_t _10028 = (uint16_t)(33); + _curvea0[33] = _10028; + uint16_t _10029 = (uint16_t)(34); + _curvea0[34] = _10029; + uint16_t _10030 = (uint16_t)(34); + _curvea0[35] = _10030; + uint16_t _10031 = (uint16_t)(35); + _curvea0[36] = _10031; + uint16_t _10032 = (uint16_t)(36); + _curvea0[37] = _10032; + uint16_t _10033 = (uint16_t)(36); + _curvea0[38] = _10033; + uint16_t _10034 = (uint16_t)(37); + _curvea0[39] = _10034; + uint16_t _10035 = (uint16_t)(37); + _curvea0[40] = _10035; + uint16_t _10036 = (uint16_t)(38); + _curvea0[41] = _10036; + uint16_t _10037 = (uint16_t)(39); + _curvea0[42] = _10037; + uint16_t _10038 = (uint16_t)(39); + _curvea0[43] = _10038; + uint16_t _10039 = (uint16_t)(40); + _curvea0[44] = _10039; + uint16_t _10040 = (uint16_t)(40); + _curvea0[45] = _10040; + uint16_t _10041 = (uint16_t)(41); + _curvea0[46] = _10041; + uint16_t _10042 = (uint16_t)(41); + _curvea0[47] = _10042; + uint16_t _10043 = (uint16_t)(42); + _curvea0[48] = _10043; + uint16_t _10044 = (uint16_t)(42); + _curvea0[49] = _10044; + uint16_t _10045 = (uint16_t)(43); + _curvea0[50] = _10045; + uint16_t _10046 = (uint16_t)(44); + _curvea0[51] = _10046; + uint16_t _10047 = (uint16_t)(44); + _curvea0[52] = _10047; + uint16_t _10048 = (uint16_t)(45); + _curvea0[53] = _10048; + uint16_t _10049 = (uint16_t)(45); + _curvea0[54] = _10049; + uint16_t _10050 = (uint16_t)(46); + _curvea0[55] = _10050; + uint16_t _10051 = (uint16_t)(46); + _curvea0[56] = _10051; + uint16_t _10052 = (uint16_t)(47); + _curvea0[57] = _10052; + uint16_t _10053 = (uint16_t)(47); + _curvea0[58] = _10053; + uint16_t _10054 = (uint16_t)(48); + _curvea0[59] = _10054; + uint16_t _10055 = (uint16_t)(48); + _curvea0[60] = _10055; + uint16_t _10056 = (uint16_t)(49); + _curvea0[61] = _10056; + uint16_t _10057 = (uint16_t)(49); + _curvea0[62] = _10057; + uint16_t _10058 = (uint16_t)(50); + _curvea0[63] = _10058; + uint16_t _10059 = (uint16_t)(50); + _curvea0[64] = _10059; + uint16_t _10060 = (uint16_t)(51); + _curvea0[65] = _10060; + uint16_t _10061 = (uint16_t)(51); + _curvea0[66] = _10061; + uint16_t _10062 = (uint16_t)(52); + _curvea0[67] = _10062; + uint16_t _10063 = (uint16_t)(52); + _curvea0[68] = _10063; + uint16_t _10064 = (uint16_t)(53); + _curvea0[69] = _10064; + uint16_t _10065 = (uint16_t)(53); + _curvea0[70] = _10065; + uint16_t _10066 = (uint16_t)(54); + _curvea0[71] = _10066; + uint16_t _10067 = (uint16_t)(54); + _curvea0[72] = _10067; + uint16_t _10068 = (uint16_t)(55); + _curvea0[73] = _10068; + uint16_t _10069 = (uint16_t)(55); + _curvea0[74] = _10069; + uint16_t _10070 = (uint16_t)(56); + _curvea0[75] = _10070; + uint16_t _10071 = (uint16_t)(56); + _curvea0[76] = _10071; + uint16_t _10072 = (uint16_t)(57); + _curvea0[77] = _10072; + uint16_t _10073 = (uint16_t)(57); + _curvea0[78] = _10073; + uint16_t _10074 = (uint16_t)(58); + _curvea0[79] = _10074; + uint16_t _10075 = (uint16_t)(58); + _curvea0[80] = _10075; + uint16_t _10076 = (uint16_t)(58); + _curvea0[81] = _10076; + uint16_t _10077 = (uint16_t)(59); + _curvea0[82] = _10077; + uint16_t _10078 = (uint16_t)(59); + _curvea0[83] = _10078; + uint16_t _10079 = (uint16_t)(60); + _curvea0[84] = _10079; + uint16_t _10080 = (uint16_t)(60); + _curvea0[85] = _10080; + uint16_t _10081 = (uint16_t)(61); + _curvea0[86] = _10081; + uint16_t _10082 = (uint16_t)(61); + _curvea0[87] = _10082; + uint16_t _10083 = (uint16_t)(62); + _curvea0[88] = _10083; + uint16_t _10084 = (uint16_t)(62); + _curvea0[89] = _10084; + uint16_t _10085 = (uint16_t)(63); + _curvea0[90] = _10085; + uint16_t _10086 = (uint16_t)(63); + _curvea0[91] = _10086; + uint16_t _10087 = (uint16_t)(64); + _curvea0[92] = _10087; + uint16_t _10088 = (uint16_t)(64); + _curvea0[93] = _10088; + uint16_t _10089 = (uint16_t)(64); + _curvea0[94] = _10089; + uint16_t _10090 = (uint16_t)(65); + _curvea0[95] = _10090; + uint16_t _10091 = (uint16_t)(65); + _curvea0[96] = _10091; + uint16_t _10092 = (uint16_t)(66); + _curvea0[97] = _10092; + uint16_t _10093 = (uint16_t)(66); + _curvea0[98] = _10093; + uint16_t _10094 = (uint16_t)(67); + _curvea0[99] = _10094; + uint16_t _10095 = (uint16_t)(67); + _curvea0[100] = _10095; + uint16_t _10096 = (uint16_t)(68); + _curvea0[101] = _10096; + uint16_t _10097 = (uint16_t)(68); + _curvea0[102] = _10097; + uint16_t _10098 = (uint16_t)(68); + _curvea0[103] = _10098; + uint16_t _10099 = (uint16_t)(69); + _curvea0[104] = _10099; + uint16_t _10100 = (uint16_t)(69); + _curvea0[105] = _10100; + uint16_t _10101 = (uint16_t)(70); + _curvea0[106] = _10101; + uint16_t _10102 = (uint16_t)(70); + _curvea0[107] = _10102; + uint16_t _10103 = (uint16_t)(71); + _curvea0[108] = _10103; + uint16_t _10104 = (uint16_t)(71); + _curvea0[109] = _10104; + uint16_t _10105 = (uint16_t)(71); + _curvea0[110] = _10105; + uint16_t _10106 = (uint16_t)(72); + _curvea0[111] = _10106; + uint16_t _10107 = (uint16_t)(72); + _curvea0[112] = _10107; + uint16_t _10108 = (uint16_t)(73); + _curvea0[113] = _10108; + uint16_t _10109 = (uint16_t)(73); + _curvea0[114] = _10109; + uint16_t _10110 = (uint16_t)(74); + _curvea0[115] = _10110; + uint16_t _10111 = (uint16_t)(74); + _curvea0[116] = _10111; + uint16_t _10112 = (uint16_t)(74); + _curvea0[117] = _10112; + uint16_t _10113 = (uint16_t)(75); + _curvea0[118] = _10113; + uint16_t _10114 = (uint16_t)(75); + _curvea0[119] = _10114; + uint16_t _10115 = (uint16_t)(76); + _curvea0[120] = _10115; + uint16_t _10116 = (uint16_t)(76); + _curvea0[121] = _10116; + uint16_t _10117 = (uint16_t)(77); + _curvea0[122] = _10117; + uint16_t _10118 = (uint16_t)(77); + _curvea0[123] = _10118; + uint16_t _10119 = (uint16_t)(77); + _curvea0[124] = _10119; + uint16_t _10120 = (uint16_t)(78); + _curvea0[125] = _10120; + uint16_t _10121 = (uint16_t)(78); + _curvea0[126] = _10121; + uint16_t _10122 = (uint16_t)(79); + _curvea0[127] = _10122; + uint16_t _10123 = (uint16_t)(79); + _curvea0[128] = _10123; + uint16_t _10124 = (uint16_t)(79); + _curvea0[129] = _10124; + uint16_t _10125 = (uint16_t)(80); + _curvea0[130] = _10125; + uint16_t _10126 = (uint16_t)(80); + _curvea0[131] = _10126; + uint16_t _10127 = (uint16_t)(81); + _curvea0[132] = _10127; + uint16_t _10128 = (uint16_t)(81); + _curvea0[133] = _10128; + uint16_t _10129 = (uint16_t)(82); + _curvea0[134] = _10129; + uint16_t _10130 = (uint16_t)(82); + _curvea0[135] = _10130; + uint16_t _10131 = (uint16_t)(82); + _curvea0[136] = _10131; + uint16_t _10132 = (uint16_t)(83); + _curvea0[137] = _10132; + uint16_t _10133 = (uint16_t)(83); + _curvea0[138] = _10133; + uint16_t _10134 = (uint16_t)(84); + _curvea0[139] = _10134; + uint16_t _10135 = (uint16_t)(84); + _curvea0[140] = _10135; + uint16_t _10136 = (uint16_t)(84); + _curvea0[141] = _10136; + uint16_t _10137 = (uint16_t)(85); + _curvea0[142] = _10137; + uint16_t _10138 = (uint16_t)(85); + _curvea0[143] = _10138; + uint16_t _10139 = (uint16_t)(86); + _curvea0[144] = _10139; + uint16_t _10140 = (uint16_t)(86); + _curvea0[145] = _10140; + uint16_t _10141 = (uint16_t)(86); + _curvea0[146] = _10141; + uint16_t _10142 = (uint16_t)(87); + _curvea0[147] = _10142; + uint16_t _10143 = (uint16_t)(87); + _curvea0[148] = _10143; + uint16_t _10144 = (uint16_t)(88); + _curvea0[149] = _10144; + uint16_t _10145 = (uint16_t)(88); + _curvea0[150] = _10145; + uint16_t _10146 = (uint16_t)(88); + _curvea0[151] = _10146; + uint16_t _10147 = (uint16_t)(89); + _curvea0[152] = _10147; + uint16_t _10148 = (uint16_t)(89); + _curvea0[153] = _10148; + uint16_t _10149 = (uint16_t)(90); + _curvea0[154] = _10149; + uint16_t _10150 = (uint16_t)(90); + _curvea0[155] = _10150; + uint16_t _10151 = (uint16_t)(90); + _curvea0[156] = _10151; + uint16_t _10152 = (uint16_t)(91); + _curvea0[157] = _10152; + uint16_t _10153 = (uint16_t)(91); + _curvea0[158] = _10153; + uint16_t _10154 = (uint16_t)(92); + _curvea0[159] = _10154; + uint16_t _10155 = (uint16_t)(92); + _curvea0[160] = _10155; + uint16_t _10156 = (uint16_t)(92); + _curvea0[161] = _10156; + uint16_t _10157 = (uint16_t)(93); + _curvea0[162] = _10157; + uint16_t _10158 = (uint16_t)(93); + _curvea0[163] = _10158; + uint16_t _10159 = (uint16_t)(93); + _curvea0[164] = _10159; + uint16_t _10160 = (uint16_t)(94); + _curvea0[165] = _10160; + uint16_t _10161 = (uint16_t)(94); + _curvea0[166] = _10161; + uint16_t _10162 = (uint16_t)(95); + _curvea0[167] = _10162; + uint16_t _10163 = (uint16_t)(95); + _curvea0[168] = _10163; + uint16_t _10164 = (uint16_t)(95); + _curvea0[169] = _10164; + uint16_t _10165 = (uint16_t)(96); + _curvea0[170] = _10165; + uint16_t _10166 = (uint16_t)(96); + _curvea0[171] = _10166; + uint16_t _10167 = (uint16_t)(97); + _curvea0[172] = _10167; + uint16_t _10168 = (uint16_t)(97); + _curvea0[173] = _10168; + uint16_t _10169 = (uint16_t)(97); + _curvea0[174] = _10169; + uint16_t _10170 = (uint16_t)(98); + _curvea0[175] = _10170; + uint16_t _10171 = (uint16_t)(98); + _curvea0[176] = _10171; + uint16_t _10172 = (uint16_t)(99); + _curvea0[177] = _10172; + uint16_t _10173 = (uint16_t)(99); + _curvea0[178] = _10173; + uint16_t _10174 = (uint16_t)(99); + _curvea0[179] = _10174; + uint16_t _10175 = (uint16_t)(100); + _curvea0[180] = _10175; + uint16_t _10176 = (uint16_t)(100); + _curvea0[181] = _10176; + uint16_t _10177 = (uint16_t)(100); + _curvea0[182] = _10177; + uint16_t _10178 = (uint16_t)(101); + _curvea0[183] = _10178; + uint16_t _10179 = (uint16_t)(101); + _curvea0[184] = _10179; + uint16_t _10180 = (uint16_t)(102); + _curvea0[185] = _10180; + uint16_t _10181 = (uint16_t)(102); + _curvea0[186] = _10181; + uint16_t _10182 = (uint16_t)(102); + _curvea0[187] = _10182; + uint16_t _10183 = (uint16_t)(103); + _curvea0[188] = _10183; + uint16_t _10184 = (uint16_t)(103); + _curvea0[189] = _10184; + uint16_t _10185 = (uint16_t)(103); + _curvea0[190] = _10185; + uint16_t _10186 = (uint16_t)(104); + _curvea0[191] = _10186; + uint16_t _10187 = (uint16_t)(104); + _curvea0[192] = _10187; + uint16_t _10188 = (uint16_t)(105); + _curvea0[193] = _10188; + uint16_t _10189 = (uint16_t)(105); + _curvea0[194] = _10189; + uint16_t _10190 = (uint16_t)(105); + _curvea0[195] = _10190; + uint16_t _10191 = (uint16_t)(106); + _curvea0[196] = _10191; + uint16_t _10192 = (uint16_t)(106); + _curvea0[197] = _10192; + uint16_t _10193 = (uint16_t)(106); + _curvea0[198] = _10193; + uint16_t _10194 = (uint16_t)(107); + _curvea0[199] = _10194; + uint16_t _10195 = (uint16_t)(107); + _curvea0[200] = _10195; + uint16_t _10196 = (uint16_t)(108); + _curvea0[201] = _10196; + uint16_t _10197 = (uint16_t)(108); + _curvea0[202] = _10197; + uint16_t _10198 = (uint16_t)(108); + _curvea0[203] = _10198; + uint16_t _10199 = (uint16_t)(109); + _curvea0[204] = _10199; + uint16_t _10200 = (uint16_t)(109); + _curvea0[205] = _10200; + uint16_t _10201 = (uint16_t)(109); + _curvea0[206] = _10201; + uint16_t _10202 = (uint16_t)(110); + _curvea0[207] = _10202; + uint16_t _10203 = (uint16_t)(110); + _curvea0[208] = _10203; + uint16_t _10204 = (uint16_t)(111); + _curvea0[209] = _10204; + uint16_t _10205 = (uint16_t)(111); + _curvea0[210] = _10205; + uint16_t _10206 = (uint16_t)(111); + _curvea0[211] = _10206; + uint16_t _10207 = (uint16_t)(112); + _curvea0[212] = _10207; + uint16_t _10208 = (uint16_t)(112); + _curvea0[213] = _10208; + uint16_t _10209 = (uint16_t)(112); + _curvea0[214] = _10209; + uint16_t _10210 = (uint16_t)(113); + _curvea0[215] = _10210; + uint16_t _10211 = (uint16_t)(113); + _curvea0[216] = _10211; + uint16_t _10212 = (uint16_t)(113); + _curvea0[217] = _10212; + uint16_t _10213 = (uint16_t)(114); + _curvea0[218] = _10213; + uint16_t _10214 = (uint16_t)(114); + _curvea0[219] = _10214; + uint16_t _10215 = (uint16_t)(115); + _curvea0[220] = _10215; + uint16_t _10216 = (uint16_t)(115); + _curvea0[221] = _10216; + uint16_t _10217 = (uint16_t)(115); + _curvea0[222] = _10217; + uint16_t _10218 = (uint16_t)(116); + _curvea0[223] = _10218; + uint16_t _10219 = (uint16_t)(116); + _curvea0[224] = _10219; + uint16_t _10220 = (uint16_t)(116); + _curvea0[225] = _10220; + uint16_t _10221 = (uint16_t)(117); + _curvea0[226] = _10221; + uint16_t _10222 = (uint16_t)(117); + _curvea0[227] = _10222; + uint16_t _10223 = (uint16_t)(117); + _curvea0[228] = _10223; + uint16_t _10224 = (uint16_t)(118); + _curvea0[229] = _10224; + uint16_t _10225 = (uint16_t)(118); + _curvea0[230] = _10225; + uint16_t _10226 = (uint16_t)(119); + _curvea0[231] = _10226; + uint16_t _10227 = (uint16_t)(119); + _curvea0[232] = _10227; + uint16_t _10228 = (uint16_t)(119); + _curvea0[233] = _10228; + uint16_t _10229 = (uint16_t)(120); + _curvea0[234] = _10229; + uint16_t _10230 = (uint16_t)(120); + _curvea0[235] = _10230; + uint16_t _10231 = (uint16_t)(120); + _curvea0[236] = _10231; + uint16_t _10232 = (uint16_t)(121); + _curvea0[237] = _10232; + uint16_t _10233 = (uint16_t)(121); + _curvea0[238] = _10233; + uint16_t _10234 = (uint16_t)(121); + _curvea0[239] = _10234; + uint16_t _10235 = (uint16_t)(122); + _curvea0[240] = _10235; + uint16_t _10236 = (uint16_t)(122); + _curvea0[241] = _10236; + uint16_t _10237 = (uint16_t)(123); + _curvea0[242] = _10237; + uint16_t _10238 = (uint16_t)(123); + _curvea0[243] = _10238; + uint16_t _10239 = (uint16_t)(123); + _curvea0[244] = _10239; + uint16_t _10240 = (uint16_t)(124); + _curvea0[245] = _10240; + uint16_t _10241 = (uint16_t)(124); + _curvea0[246] = _10241; + uint16_t _10242 = (uint16_t)(124); + _curvea0[247] = _10242; + uint16_t _10243 = (uint16_t)(125); + _curvea0[248] = _10243; + uint16_t _10244 = (uint16_t)(125); + _curvea0[249] = _10244; + uint16_t _10245 = (uint16_t)(125); + _curvea0[250] = _10245; + uint16_t _10246 = (uint16_t)(126); + _curvea0[251] = _10246; + uint16_t _10247 = (uint16_t)(126); + _curvea0[252] = _10247; + uint16_t _10248 = (uint16_t)(126); + _curvea0[253] = _10248; + uint16_t _10249 = (uint16_t)(127); + _curvea0[254] = _10249; + uint16_t _10250 = (uint16_t)(127); + _curvea0[255] = _10250; + uint16_t _10251 = (uint16_t)(128); + _curvea0[256] = _10251; + uint16_t _10252 = (uint16_t)(128); + _curvea0[257] = _10252; + uint16_t _10253 = (uint16_t)(128); + _curvea0[258] = _10253; + uint16_t _10254 = (uint16_t)(129); + _curvea0[259] = _10254; + uint16_t _10255 = (uint16_t)(129); + _curvea0[260] = _10255; + uint16_t _10256 = (uint16_t)(129); + _curvea0[261] = _10256; + uint16_t _10257 = (uint16_t)(130); + _curvea0[262] = _10257; + uint16_t _10258 = (uint16_t)(130); + _curvea0[263] = _10258; + uint16_t _10259 = (uint16_t)(130); + _curvea0[264] = _10259; + uint16_t _10260 = (uint16_t)(131); + _curvea0[265] = _10260; + uint16_t _10261 = (uint16_t)(131); + _curvea0[266] = _10261; + uint16_t _10262 = (uint16_t)(131); + _curvea0[267] = _10262; + uint16_t _10263 = (uint16_t)(132); + _curvea0[268] = _10263; + uint16_t _10264 = (uint16_t)(132); + _curvea0[269] = _10264; + uint16_t _10265 = (uint16_t)(132); + _curvea0[270] = _10265; + uint16_t _10266 = (uint16_t)(133); + _curvea0[271] = _10266; + uint16_t _10267 = (uint16_t)(133); + _curvea0[272] = _10267; + uint16_t _10268 = (uint16_t)(133); + _curvea0[273] = _10268; + uint16_t _10269 = (uint16_t)(134); + _curvea0[274] = _10269; + uint16_t _10270 = (uint16_t)(134); + _curvea0[275] = _10270; + uint16_t _10271 = (uint16_t)(134); + _curvea0[276] = _10271; + uint16_t _10272 = (uint16_t)(135); + _curvea0[277] = _10272; + uint16_t _10273 = (uint16_t)(135); + _curvea0[278] = _10273; + uint16_t _10274 = (uint16_t)(135); + _curvea0[279] = _10274; + uint16_t _10275 = (uint16_t)(136); + _curvea0[280] = _10275; + uint16_t _10276 = (uint16_t)(136); + _curvea0[281] = _10276; + uint16_t _10277 = (uint16_t)(136); + _curvea0[282] = _10277; + uint16_t _10278 = (uint16_t)(137); + _curvea0[283] = _10278; + uint16_t _10279 = (uint16_t)(137); + _curvea0[284] = _10279; + uint16_t _10280 = (uint16_t)(137); + _curvea0[285] = _10280; + uint16_t _10281 = (uint16_t)(138); + _curvea0[286] = _10281; + uint16_t _10282 = (uint16_t)(138); + _curvea0[287] = _10282; + uint16_t _10283 = (uint16_t)(138); + _curvea0[288] = _10283; + uint16_t _10284 = (uint16_t)(139); + _curvea0[289] = _10284; + uint16_t _10285 = (uint16_t)(139); + _curvea0[290] = _10285; + uint16_t _10286 = (uint16_t)(139); + _curvea0[291] = _10286; + uint16_t _10287 = (uint16_t)(140); + _curvea0[292] = _10287; + uint16_t _10288 = (uint16_t)(140); + _curvea0[293] = _10288; + uint16_t _10289 = (uint16_t)(140); + _curvea0[294] = _10289; + uint16_t _10290 = (uint16_t)(141); + _curvea0[295] = _10290; + uint16_t _10291 = (uint16_t)(141); + _curvea0[296] = _10291; + uint16_t _10292 = (uint16_t)(141); + _curvea0[297] = _10292; + uint16_t _10293 = (uint16_t)(141); + _curvea0[298] = _10293; + uint16_t _10294 = (uint16_t)(142); + _curvea0[299] = _10294; + uint16_t _10295 = (uint16_t)(142); + _curvea0[300] = _10295; + uint16_t _10296 = (uint16_t)(142); + _curvea0[301] = _10296; + uint16_t _10297 = (uint16_t)(143); + _curvea0[302] = _10297; + uint16_t _10298 = (uint16_t)(143); + _curvea0[303] = _10298; + uint16_t _10299 = (uint16_t)(143); + _curvea0[304] = _10299; + uint16_t _10300 = (uint16_t)(144); + _curvea0[305] = _10300; + uint16_t _10301 = (uint16_t)(144); + _curvea0[306] = _10301; + uint16_t _10302 = (uint16_t)(144); + _curvea0[307] = _10302; + uint16_t _10303 = (uint16_t)(145); + _curvea0[308] = _10303; + uint16_t _10304 = (uint16_t)(145); + _curvea0[309] = _10304; + uint16_t _10305 = (uint16_t)(145); + _curvea0[310] = _10305; + uint16_t _10306 = (uint16_t)(145); + _curvea0[311] = _10306; + uint16_t _10307 = (uint16_t)(146); + _curvea0[312] = _10307; + uint16_t _10308 = (uint16_t)(146); + _curvea0[313] = _10308; + uint16_t _10309 = (uint16_t)(146); + _curvea0[314] = _10309; + uint16_t _10310 = (uint16_t)(147); + _curvea0[315] = _10310; + uint16_t _10311 = (uint16_t)(147); + _curvea0[316] = _10311; + uint16_t _10312 = (uint16_t)(147); + _curvea0[317] = _10312; + uint16_t _10313 = (uint16_t)(148); + _curvea0[318] = _10313; + uint16_t _10314 = (uint16_t)(148); + _curvea0[319] = _10314; + uint16_t _10315 = (uint16_t)(148); + _curvea0[320] = _10315; + uint16_t _10316 = (uint16_t)(148); + _curvea0[321] = _10316; + uint16_t _10317 = (uint16_t)(149); + _curvea0[322] = _10317; + uint16_t _10318 = (uint16_t)(149); + _curvea0[323] = _10318; + uint16_t _10319 = (uint16_t)(149); + _curvea0[324] = _10319; + uint16_t _10320 = (uint16_t)(150); + _curvea0[325] = _10320; + uint16_t _10321 = (uint16_t)(150); + _curvea0[326] = _10321; + uint16_t _10322 = (uint16_t)(150); + _curvea0[327] = _10322; + uint16_t _10323 = (uint16_t)(150); + _curvea0[328] = _10323; + uint16_t _10324 = (uint16_t)(151); + _curvea0[329] = _10324; + uint16_t _10325 = (uint16_t)(151); + _curvea0[330] = _10325; + uint16_t _10326 = (uint16_t)(151); + _curvea0[331] = _10326; + uint16_t _10327 = (uint16_t)(152); + _curvea0[332] = _10327; + uint16_t _10328 = (uint16_t)(152); + _curvea0[333] = _10328; + uint16_t _10329 = (uint16_t)(152); + _curvea0[334] = _10329; + uint16_t _10330 = (uint16_t)(152); + _curvea0[335] = _10330; + uint16_t _10331 = (uint16_t)(153); + _curvea0[336] = _10331; + uint16_t _10332 = (uint16_t)(153); + _curvea0[337] = _10332; + uint16_t _10333 = (uint16_t)(153); + _curvea0[338] = _10333; + uint16_t _10334 = (uint16_t)(154); + _curvea0[339] = _10334; + uint16_t _10335 = (uint16_t)(154); + _curvea0[340] = _10335; + uint16_t _10336 = (uint16_t)(154); + _curvea0[341] = _10336; + uint16_t _10337 = (uint16_t)(154); + _curvea0[342] = _10337; + uint16_t _10338 = (uint16_t)(155); + _curvea0[343] = _10338; + uint16_t _10339 = (uint16_t)(155); + _curvea0[344] = _10339; + uint16_t _10340 = (uint16_t)(155); + _curvea0[345] = _10340; + uint16_t _10341 = (uint16_t)(156); + _curvea0[346] = _10341; + uint16_t _10342 = (uint16_t)(156); + _curvea0[347] = _10342; + uint16_t _10343 = (uint16_t)(156); + _curvea0[348] = _10343; + uint16_t _10344 = (uint16_t)(156); + _curvea0[349] = _10344; + uint16_t _10345 = (uint16_t)(157); + _curvea0[350] = _10345; + uint16_t _10346 = (uint16_t)(157); + _curvea0[351] = _10346; + uint16_t _10347 = (uint16_t)(157); + _curvea0[352] = _10347; + uint16_t _10348 = (uint16_t)(157); + _curvea0[353] = _10348; + uint16_t _10349 = (uint16_t)(158); + _curvea0[354] = _10349; + uint16_t _10350 = (uint16_t)(158); + _curvea0[355] = _10350; + uint16_t _10351 = (uint16_t)(158); + _curvea0[356] = _10351; + uint16_t _10352 = (uint16_t)(159); + _curvea0[357] = _10352; + uint16_t _10353 = (uint16_t)(159); + _curvea0[358] = _10353; + uint16_t _10354 = (uint16_t)(159); + _curvea0[359] = _10354; + uint16_t _10355 = (uint16_t)(159); + _curvea0[360] = _10355; + uint16_t _10356 = (uint16_t)(160); + _curvea0[361] = _10356; + uint16_t _10357 = (uint16_t)(160); + _curvea0[362] = _10357; + uint16_t _10358 = (uint16_t)(160); + _curvea0[363] = _10358; + uint16_t _10359 = (uint16_t)(160); + _curvea0[364] = _10359; + uint16_t _10360 = (uint16_t)(161); + _curvea0[365] = _10360; + uint16_t _10361 = (uint16_t)(161); + _curvea0[366] = _10361; + uint16_t _10362 = (uint16_t)(161); + _curvea0[367] = _10362; + uint16_t _10363 = (uint16_t)(161); + _curvea0[368] = _10363; + uint16_t _10364 = (uint16_t)(162); + _curvea0[369] = _10364; + uint16_t _10365 = (uint16_t)(162); + _curvea0[370] = _10365; + uint16_t _10366 = (uint16_t)(162); + _curvea0[371] = _10366; + uint16_t _10367 = (uint16_t)(162); + _curvea0[372] = _10367; + uint16_t _10368 = (uint16_t)(163); + _curvea0[373] = _10368; + uint16_t _10369 = (uint16_t)(163); + _curvea0[374] = _10369; + uint16_t _10370 = (uint16_t)(163); + _curvea0[375] = _10370; + uint16_t _10371 = (uint16_t)(163); + _curvea0[376] = _10371; + uint16_t _10372 = (uint16_t)(164); + _curvea0[377] = _10372; + uint16_t _10373 = (uint16_t)(164); + _curvea0[378] = _10373; + uint16_t _10374 = (uint16_t)(164); + _curvea0[379] = _10374; + uint16_t _10375 = (uint16_t)(164); + _curvea0[380] = _10375; + uint16_t _10376 = (uint16_t)(165); + _curvea0[381] = _10376; + uint16_t _10377 = (uint16_t)(165); + _curvea0[382] = _10377; + uint16_t _10378 = (uint16_t)(165); + _curvea0[383] = _10378; + uint16_t _10379 = (uint16_t)(166); + _curvea0[384] = _10379; + uint16_t _10380 = (uint16_t)(166); + _curvea0[385] = _10380; + uint16_t _10381 = (uint16_t)(166); + _curvea0[386] = _10381; + uint16_t _10382 = (uint16_t)(166); + _curvea0[387] = _10382; + uint16_t _10383 = (uint16_t)(167); + _curvea0[388] = _10383; + uint16_t _10384 = (uint16_t)(167); + _curvea0[389] = _10384; + uint16_t _10385 = (uint16_t)(167); + _curvea0[390] = _10385; + uint16_t _10386 = (uint16_t)(167); + _curvea0[391] = _10386; + uint16_t _10387 = (uint16_t)(167); + _curvea0[392] = _10387; + uint16_t _10388 = (uint16_t)(168); + _curvea0[393] = _10388; + uint16_t _10389 = (uint16_t)(168); + _curvea0[394] = _10389; + uint16_t _10390 = (uint16_t)(168); + _curvea0[395] = _10390; + uint16_t _10391 = (uint16_t)(168); + _curvea0[396] = _10391; + uint16_t _10392 = (uint16_t)(169); + _curvea0[397] = _10392; + uint16_t _10393 = (uint16_t)(169); + _curvea0[398] = _10393; + uint16_t _10394 = (uint16_t)(169); + _curvea0[399] = _10394; + uint16_t _10395 = (uint16_t)(169); + _curvea0[400] = _10395; + uint16_t _10396 = (uint16_t)(170); + _curvea0[401] = _10396; + uint16_t _10397 = (uint16_t)(170); + _curvea0[402] = _10397; + uint16_t _10398 = (uint16_t)(170); + _curvea0[403] = _10398; + uint16_t _10399 = (uint16_t)(170); + _curvea0[404] = _10399; + uint16_t _10400 = (uint16_t)(171); + _curvea0[405] = _10400; + uint16_t _10401 = (uint16_t)(171); + _curvea0[406] = _10401; + uint16_t _10402 = (uint16_t)(171); + _curvea0[407] = _10402; + uint16_t _10403 = (uint16_t)(171); + _curvea0[408] = _10403; + uint16_t _10404 = (uint16_t)(172); + _curvea0[409] = _10404; + uint16_t _10405 = (uint16_t)(172); + _curvea0[410] = _10405; + uint16_t _10406 = (uint16_t)(172); + _curvea0[411] = _10406; + uint16_t _10407 = (uint16_t)(172); + _curvea0[412] = _10407; + uint16_t _10408 = (uint16_t)(173); + _curvea0[413] = _10408; + uint16_t _10409 = (uint16_t)(173); + _curvea0[414] = _10409; + uint16_t _10410 = (uint16_t)(173); + _curvea0[415] = _10410; + uint16_t _10411 = (uint16_t)(173); + _curvea0[416] = _10411; + uint16_t _10412 = (uint16_t)(173); + _curvea0[417] = _10412; + uint16_t _10413 = (uint16_t)(174); + _curvea0[418] = _10413; + uint16_t _10414 = (uint16_t)(174); + _curvea0[419] = _10414; + uint16_t _10415 = (uint16_t)(174); + _curvea0[420] = _10415; + uint16_t _10416 = (uint16_t)(174); + _curvea0[421] = _10416; + uint16_t _10417 = (uint16_t)(175); + _curvea0[422] = _10417; + uint16_t _10418 = (uint16_t)(175); + _curvea0[423] = _10418; + uint16_t _10419 = (uint16_t)(175); + _curvea0[424] = _10419; + uint16_t _10420 = (uint16_t)(175); + _curvea0[425] = _10420; + uint16_t _10421 = (uint16_t)(176); + _curvea0[426] = _10421; + uint16_t _10422 = (uint16_t)(176); + _curvea0[427] = _10422; + uint16_t _10423 = (uint16_t)(176); + _curvea0[428] = _10423; + uint16_t _10424 = (uint16_t)(176); + _curvea0[429] = _10424; + uint16_t _10425 = (uint16_t)(176); + _curvea0[430] = _10425; + uint16_t _10426 = (uint16_t)(177); + _curvea0[431] = _10426; + uint16_t _10427 = (uint16_t)(177); + _curvea0[432] = _10427; + uint16_t _10428 = (uint16_t)(177); + _curvea0[433] = _10428; + uint16_t _10429 = (uint16_t)(177); + _curvea0[434] = _10429; + uint16_t _10430 = (uint16_t)(178); + _curvea0[435] = _10430; + uint16_t _10431 = (uint16_t)(178); + _curvea0[436] = _10431; + uint16_t _10432 = (uint16_t)(178); + _curvea0[437] = _10432; + uint16_t _10433 = (uint16_t)(178); + _curvea0[438] = _10433; + uint16_t _10434 = (uint16_t)(178); + _curvea0[439] = _10434; + uint16_t _10435 = (uint16_t)(179); + _curvea0[440] = _10435; + uint16_t _10436 = (uint16_t)(179); + _curvea0[441] = _10436; + uint16_t _10437 = (uint16_t)(179); + _curvea0[442] = _10437; + uint16_t _10438 = (uint16_t)(179); + _curvea0[443] = _10438; + uint16_t _10439 = (uint16_t)(180); + _curvea0[444] = _10439; + uint16_t _10440 = (uint16_t)(180); + _curvea0[445] = _10440; + uint16_t _10441 = (uint16_t)(180); + _curvea0[446] = _10441; + uint16_t _10442 = (uint16_t)(180); + _curvea0[447] = _10442; + uint16_t _10443 = (uint16_t)(180); + _curvea0[448] = _10443; + uint16_t _10444 = (uint16_t)(181); + _curvea0[449] = _10444; + uint16_t _10445 = (uint16_t)(181); + _curvea0[450] = _10445; + uint16_t _10446 = (uint16_t)(181); + _curvea0[451] = _10446; + uint16_t _10447 = (uint16_t)(181); + _curvea0[452] = _10447; + uint16_t _10448 = (uint16_t)(181); + _curvea0[453] = _10448; + uint16_t _10449 = (uint16_t)(182); + _curvea0[454] = _10449; + uint16_t _10450 = (uint16_t)(182); + _curvea0[455] = _10450; + uint16_t _10451 = (uint16_t)(182); + _curvea0[456] = _10451; + uint16_t _10452 = (uint16_t)(182); + _curvea0[457] = _10452; + uint16_t _10453 = (uint16_t)(183); + _curvea0[458] = _10453; + uint16_t _10454 = (uint16_t)(183); + _curvea0[459] = _10454; + uint16_t _10455 = (uint16_t)(183); + _curvea0[460] = _10455; + uint16_t _10456 = (uint16_t)(183); + _curvea0[461] = _10456; + uint16_t _10457 = (uint16_t)(183); + _curvea0[462] = _10457; + uint16_t _10458 = (uint16_t)(184); + _curvea0[463] = _10458; + uint16_t _10459 = (uint16_t)(184); + _curvea0[464] = _10459; + uint16_t _10460 = (uint16_t)(184); + _curvea0[465] = _10460; + uint16_t _10461 = (uint16_t)(184); + _curvea0[466] = _10461; + uint16_t _10462 = (uint16_t)(184); + _curvea0[467] = _10462; + uint16_t _10463 = (uint16_t)(185); + _curvea0[468] = _10463; + uint16_t _10464 = (uint16_t)(185); + _curvea0[469] = _10464; + uint16_t _10465 = (uint16_t)(185); + _curvea0[470] = _10465; + uint16_t _10466 = (uint16_t)(185); + _curvea0[471] = _10466; + uint16_t _10467 = (uint16_t)(185); + _curvea0[472] = _10467; + uint16_t _10468 = (uint16_t)(186); + _curvea0[473] = _10468; + uint16_t _10469 = (uint16_t)(186); + _curvea0[474] = _10469; + uint16_t _10470 = (uint16_t)(186); + _curvea0[475] = _10470; + uint16_t _10471 = (uint16_t)(186); + _curvea0[476] = _10471; + uint16_t _10472 = (uint16_t)(187); + _curvea0[477] = _10472; + uint16_t _10473 = (uint16_t)(187); + _curvea0[478] = _10473; + uint16_t _10474 = (uint16_t)(187); + _curvea0[479] = _10474; + uint16_t _10475 = (uint16_t)(187); + _curvea0[480] = _10475; + uint16_t _10476 = (uint16_t)(187); + _curvea0[481] = _10476; + uint16_t _10477 = (uint16_t)(188); + _curvea0[482] = _10477; + uint16_t _10478 = (uint16_t)(188); + _curvea0[483] = _10478; + uint16_t _10479 = (uint16_t)(188); + _curvea0[484] = _10479; + uint16_t _10480 = (uint16_t)(188); + _curvea0[485] = _10480; + uint16_t _10481 = (uint16_t)(188); + _curvea0[486] = _10481; + uint16_t _10482 = (uint16_t)(189); + _curvea0[487] = _10482; + uint16_t _10483 = (uint16_t)(189); + _curvea0[488] = _10483; + uint16_t _10484 = (uint16_t)(189); + _curvea0[489] = _10484; + uint16_t _10485 = (uint16_t)(189); + _curvea0[490] = _10485; + uint16_t _10486 = (uint16_t)(189); + _curvea0[491] = _10486; + uint16_t _10487 = (uint16_t)(190); + _curvea0[492] = _10487; + uint16_t _10488 = (uint16_t)(190); + _curvea0[493] = _10488; + uint16_t _10489 = (uint16_t)(190); + _curvea0[494] = _10489; + uint16_t _10490 = (uint16_t)(190); + _curvea0[495] = _10490; + uint16_t _10491 = (uint16_t)(190); + _curvea0[496] = _10491; + uint16_t _10492 = (uint16_t)(190); + _curvea0[497] = _10492; + uint16_t _10493 = (uint16_t)(191); + _curvea0[498] = _10493; + uint16_t _10494 = (uint16_t)(191); + _curvea0[499] = _10494; + uint16_t _10495 = (uint16_t)(191); + _curvea0[500] = _10495; + uint16_t _10496 = (uint16_t)(191); + _curvea0[501] = _10496; + uint16_t _10497 = (uint16_t)(191); + _curvea0[502] = _10497; + uint16_t _10498 = (uint16_t)(192); + _curvea0[503] = _10498; + uint16_t _10499 = (uint16_t)(192); + _curvea0[504] = _10499; + uint16_t _10500 = (uint16_t)(192); + _curvea0[505] = _10500; + uint16_t _10501 = (uint16_t)(192); + _curvea0[506] = _10501; + uint16_t _10502 = (uint16_t)(192); + _curvea0[507] = _10502; + uint16_t _10503 = (uint16_t)(193); + _curvea0[508] = _10503; + uint16_t _10504 = (uint16_t)(193); + _curvea0[509] = _10504; + uint16_t _10505 = (uint16_t)(193); + _curvea0[510] = _10505; + uint16_t _10506 = (uint16_t)(193); + _curvea0[511] = _10506; + uint16_t _10507 = (uint16_t)(193); + _curvea0[512] = _10507; + uint16_t _10508 = (uint16_t)(194); + _curvea0[513] = _10508; + uint16_t _10509 = (uint16_t)(194); + _curvea0[514] = _10509; + uint16_t _10510 = (uint16_t)(194); + _curvea0[515] = _10510; + uint16_t _10511 = (uint16_t)(194); + _curvea0[516] = _10511; + uint16_t _10512 = (uint16_t)(194); + _curvea0[517] = _10512; + uint16_t _10513 = (uint16_t)(195); + _curvea0[518] = _10513; + uint16_t _10514 = (uint16_t)(195); + _curvea0[519] = _10514; + uint16_t _10515 = (uint16_t)(195); + _curvea0[520] = _10515; + uint16_t _10516 = (uint16_t)(195); + _curvea0[521] = _10516; + uint16_t _10517 = (uint16_t)(195); + _curvea0[522] = _10517; + uint16_t _10518 = (uint16_t)(195); + _curvea0[523] = _10518; + uint16_t _10519 = (uint16_t)(196); + _curvea0[524] = _10519; + uint16_t _10520 = (uint16_t)(196); + _curvea0[525] = _10520; + uint16_t _10521 = (uint16_t)(196); + _curvea0[526] = _10521; + uint16_t _10522 = (uint16_t)(196); + _curvea0[527] = _10522; + uint16_t _10523 = (uint16_t)(196); + _curvea0[528] = _10523; + uint16_t _10524 = (uint16_t)(197); + _curvea0[529] = _10524; + uint16_t _10525 = (uint16_t)(197); + _curvea0[530] = _10525; + uint16_t _10526 = (uint16_t)(197); + _curvea0[531] = _10526; + uint16_t _10527 = (uint16_t)(197); + _curvea0[532] = _10527; + uint16_t _10528 = (uint16_t)(197); + _curvea0[533] = _10528; + uint16_t _10529 = (uint16_t)(197); + _curvea0[534] = _10529; + uint16_t _10530 = (uint16_t)(198); + _curvea0[535] = _10530; + uint16_t _10531 = (uint16_t)(198); + _curvea0[536] = _10531; + uint16_t _10532 = (uint16_t)(198); + _curvea0[537] = _10532; + uint16_t _10533 = (uint16_t)(198); + _curvea0[538] = _10533; + uint16_t _10534 = (uint16_t)(198); + _curvea0[539] = _10534; + uint16_t _10535 = (uint16_t)(199); + _curvea0[540] = _10535; + uint16_t _10536 = (uint16_t)(199); + _curvea0[541] = _10536; + uint16_t _10537 = (uint16_t)(199); + _curvea0[542] = _10537; + uint16_t _10538 = (uint16_t)(199); + _curvea0[543] = _10538; + uint16_t _10539 = (uint16_t)(199); + _curvea0[544] = _10539; + uint16_t _10540 = (uint16_t)(199); + _curvea0[545] = _10540; + uint16_t _10541 = (uint16_t)(200); + _curvea0[546] = _10541; + uint16_t _10542 = (uint16_t)(200); + _curvea0[547] = _10542; + uint16_t _10543 = (uint16_t)(200); + _curvea0[548] = _10543; + uint16_t _10544 = (uint16_t)(200); + _curvea0[549] = _10544; + uint16_t _10545 = (uint16_t)(200); + _curvea0[550] = _10545; + uint16_t _10546 = (uint16_t)(200); + _curvea0[551] = _10546; + uint16_t _10547 = (uint16_t)(201); + _curvea0[552] = _10547; + uint16_t _10548 = (uint16_t)(201); + _curvea0[553] = _10548; + uint16_t _10549 = (uint16_t)(201); + _curvea0[554] = _10549; + uint16_t _10550 = (uint16_t)(201); + _curvea0[555] = _10550; + uint16_t _10551 = (uint16_t)(201); + _curvea0[556] = _10551; + uint16_t _10552 = (uint16_t)(202); + _curvea0[557] = _10552; + uint16_t _10553 = (uint16_t)(202); + _curvea0[558] = _10553; + uint16_t _10554 = (uint16_t)(202); + _curvea0[559] = _10554; + uint16_t _10555 = (uint16_t)(202); + _curvea0[560] = _10555; + uint16_t _10556 = (uint16_t)(202); + _curvea0[561] = _10556; + uint16_t _10557 = (uint16_t)(202); + _curvea0[562] = _10557; + uint16_t _10558 = (uint16_t)(203); + _curvea0[563] = _10558; + uint16_t _10559 = (uint16_t)(203); + _curvea0[564] = _10559; + uint16_t _10560 = (uint16_t)(203); + _curvea0[565] = _10560; + uint16_t _10561 = (uint16_t)(203); + _curvea0[566] = _10561; + uint16_t _10562 = (uint16_t)(203); + _curvea0[567] = _10562; + uint16_t _10563 = (uint16_t)(203); + _curvea0[568] = _10563; + uint16_t _10564 = (uint16_t)(204); + _curvea0[569] = _10564; + uint16_t _10565 = (uint16_t)(204); + _curvea0[570] = _10565; + uint16_t _10566 = (uint16_t)(204); + _curvea0[571] = _10566; + uint16_t _10567 = (uint16_t)(204); + _curvea0[572] = _10567; + uint16_t _10568 = (uint16_t)(204); + _curvea0[573] = _10568; + uint16_t _10569 = (uint16_t)(204); + _curvea0[574] = _10569; + uint16_t _10570 = (uint16_t)(205); + _curvea0[575] = _10570; + uint16_t _10571 = (uint16_t)(205); + _curvea0[576] = _10571; + uint16_t _10572 = (uint16_t)(205); + _curvea0[577] = _10572; + uint16_t _10573 = (uint16_t)(205); + _curvea0[578] = _10573; + uint16_t _10574 = (uint16_t)(205); + _curvea0[579] = _10574; + uint16_t _10575 = (uint16_t)(205); + _curvea0[580] = _10575; + uint16_t _10576 = (uint16_t)(206); + _curvea0[581] = _10576; + uint16_t _10577 = (uint16_t)(206); + _curvea0[582] = _10577; + uint16_t _10578 = (uint16_t)(206); + _curvea0[583] = _10578; + uint16_t _10579 = (uint16_t)(206); + _curvea0[584] = _10579; + uint16_t _10580 = (uint16_t)(206); + _curvea0[585] = _10580; + uint16_t _10581 = (uint16_t)(206); + _curvea0[586] = _10581; + uint16_t _10582 = (uint16_t)(207); + _curvea0[587] = _10582; + uint16_t _10583 = (uint16_t)(207); + _curvea0[588] = _10583; + uint16_t _10584 = (uint16_t)(207); + _curvea0[589] = _10584; + uint16_t _10585 = (uint16_t)(207); + _curvea0[590] = _10585; + uint16_t _10586 = (uint16_t)(207); + _curvea0[591] = _10586; + uint16_t _10587 = (uint16_t)(207); + _curvea0[592] = _10587; + uint16_t _10588 = (uint16_t)(208); + _curvea0[593] = _10588; + uint16_t _10589 = (uint16_t)(208); + _curvea0[594] = _10589; + uint16_t _10590 = (uint16_t)(208); + _curvea0[595] = _10590; + uint16_t _10591 = (uint16_t)(208); + _curvea0[596] = _10591; + uint16_t _10592 = (uint16_t)(208); + _curvea0[597] = _10592; + uint16_t _10593 = (uint16_t)(208); + _curvea0[598] = _10593; + uint16_t _10594 = (uint16_t)(209); + _curvea0[599] = _10594; + uint16_t _10595 = (uint16_t)(209); + _curvea0[600] = _10595; + uint16_t _10596 = (uint16_t)(209); + _curvea0[601] = _10596; + uint16_t _10597 = (uint16_t)(209); + _curvea0[602] = _10597; + uint16_t _10598 = (uint16_t)(209); + _curvea0[603] = _10598; + uint16_t _10599 = (uint16_t)(209); + _curvea0[604] = _10599; + uint16_t _10600 = (uint16_t)(209); + _curvea0[605] = _10600; + uint16_t _10601 = (uint16_t)(210); + _curvea0[606] = _10601; + uint16_t _10602 = (uint16_t)(210); + _curvea0[607] = _10602; + uint16_t _10603 = (uint16_t)(210); + _curvea0[608] = _10603; + uint16_t _10604 = (uint16_t)(210); + _curvea0[609] = _10604; + uint16_t _10605 = (uint16_t)(210); + _curvea0[610] = _10605; + uint16_t _10606 = (uint16_t)(210); + _curvea0[611] = _10606; + uint16_t _10607 = (uint16_t)(211); + _curvea0[612] = _10607; + uint16_t _10608 = (uint16_t)(211); + _curvea0[613] = _10608; + uint16_t _10609 = (uint16_t)(211); + _curvea0[614] = _10609; + uint16_t _10610 = (uint16_t)(211); + _curvea0[615] = _10610; + uint16_t _10611 = (uint16_t)(211); + _curvea0[616] = _10611; + uint16_t _10612 = (uint16_t)(211); + _curvea0[617] = _10612; + uint16_t _10613 = (uint16_t)(211); + _curvea0[618] = _10613; + uint16_t _10614 = (uint16_t)(212); + _curvea0[619] = _10614; + uint16_t _10615 = (uint16_t)(212); + _curvea0[620] = _10615; + uint16_t _10616 = (uint16_t)(212); + _curvea0[621] = _10616; + uint16_t _10617 = (uint16_t)(212); + _curvea0[622] = _10617; + uint16_t _10618 = (uint16_t)(212); + _curvea0[623] = _10618; + uint16_t _10619 = (uint16_t)(212); + _curvea0[624] = _10619; + uint16_t _10620 = (uint16_t)(213); + _curvea0[625] = _10620; + uint16_t _10621 = (uint16_t)(213); + _curvea0[626] = _10621; + uint16_t _10622 = (uint16_t)(213); + _curvea0[627] = _10622; + uint16_t _10623 = (uint16_t)(213); + _curvea0[628] = _10623; + uint16_t _10624 = (uint16_t)(213); + _curvea0[629] = _10624; + uint16_t _10625 = (uint16_t)(213); + _curvea0[630] = _10625; + uint16_t _10626 = (uint16_t)(213); + _curvea0[631] = _10626; + uint16_t _10627 = (uint16_t)(214); + _curvea0[632] = _10627; + uint16_t _10628 = (uint16_t)(214); + _curvea0[633] = _10628; + uint16_t _10629 = (uint16_t)(214); + _curvea0[634] = _10629; + uint16_t _10630 = (uint16_t)(214); + _curvea0[635] = _10630; + uint16_t _10631 = (uint16_t)(214); + _curvea0[636] = _10631; + uint16_t _10632 = (uint16_t)(214); + _curvea0[637] = _10632; + uint16_t _10633 = (uint16_t)(214); + _curvea0[638] = _10633; + uint16_t _10634 = (uint16_t)(215); + _curvea0[639] = _10634; + uint16_t _10635 = (uint16_t)(215); + _curvea0[640] = _10635; + uint16_t _10636 = (uint16_t)(215); + _curvea0[641] = _10636; + uint16_t _10637 = (uint16_t)(215); + _curvea0[642] = _10637; + uint16_t _10638 = (uint16_t)(215); + _curvea0[643] = _10638; + uint16_t _10639 = (uint16_t)(215); + _curvea0[644] = _10639; + uint16_t _10640 = (uint16_t)(216); + _curvea0[645] = _10640; + uint16_t _10641 = (uint16_t)(216); + _curvea0[646] = _10641; + uint16_t _10642 = (uint16_t)(216); + _curvea0[647] = _10642; + uint16_t _10643 = (uint16_t)(216); + _curvea0[648] = _10643; + uint16_t _10644 = (uint16_t)(216); + _curvea0[649] = _10644; + uint16_t _10645 = (uint16_t)(216); + _curvea0[650] = _10645; + uint16_t _10646 = (uint16_t)(216); + _curvea0[651] = _10646; + uint16_t _10647 = (uint16_t)(217); + _curvea0[652] = _10647; + uint16_t _10648 = (uint16_t)(217); + _curvea0[653] = _10648; + uint16_t _10649 = (uint16_t)(217); + _curvea0[654] = _10649; + uint16_t _10650 = (uint16_t)(217); + _curvea0[655] = _10650; + uint16_t _10651 = (uint16_t)(217); + _curvea0[656] = _10651; + uint16_t _10652 = (uint16_t)(217); + _curvea0[657] = _10652; + uint16_t _10653 = (uint16_t)(217); + _curvea0[658] = _10653; + uint16_t _10654 = (uint16_t)(218); + _curvea0[659] = _10654; + uint16_t _10655 = (uint16_t)(218); + _curvea0[660] = _10655; + uint16_t _10656 = (uint16_t)(218); + _curvea0[661] = _10656; + uint16_t _10657 = (uint16_t)(218); + _curvea0[662] = _10657; + uint16_t _10658 = (uint16_t)(218); + _curvea0[663] = _10658; + uint16_t _10659 = (uint16_t)(218); + _curvea0[664] = _10659; + uint16_t _10660 = (uint16_t)(218); + _curvea0[665] = _10660; + uint16_t _10661 = (uint16_t)(219); + _curvea0[666] = _10661; + uint16_t _10662 = (uint16_t)(219); + _curvea0[667] = _10662; + uint16_t _10663 = (uint16_t)(219); + _curvea0[668] = _10663; + uint16_t _10664 = (uint16_t)(219); + _curvea0[669] = _10664; + uint16_t _10665 = (uint16_t)(219); + _curvea0[670] = _10665; + uint16_t _10666 = (uint16_t)(219); + _curvea0[671] = _10666; + uint16_t _10667 = (uint16_t)(219); + _curvea0[672] = _10667; + uint16_t _10668 = (uint16_t)(220); + _curvea0[673] = _10668; + uint16_t _10669 = (uint16_t)(220); + _curvea0[674] = _10669; + uint16_t _10670 = (uint16_t)(220); + _curvea0[675] = _10670; + uint16_t _10671 = (uint16_t)(220); + _curvea0[676] = _10671; + uint16_t _10672 = (uint16_t)(220); + _curvea0[677] = _10672; + uint16_t _10673 = (uint16_t)(220); + _curvea0[678] = _10673; + uint16_t _10674 = (uint16_t)(220); + _curvea0[679] = _10674; + uint16_t _10675 = (uint16_t)(220); + _curvea0[680] = _10675; + uint16_t _10676 = (uint16_t)(221); + _curvea0[681] = _10676; + uint16_t _10677 = (uint16_t)(221); + _curvea0[682] = _10677; + uint16_t _10678 = (uint16_t)(221); + _curvea0[683] = _10678; + uint16_t _10679 = (uint16_t)(221); + _curvea0[684] = _10679; + uint16_t _10680 = (uint16_t)(221); + _curvea0[685] = _10680; + uint16_t _10681 = (uint16_t)(221); + _curvea0[686] = _10681; + uint16_t _10682 = (uint16_t)(221); + _curvea0[687] = _10682; + uint16_t _10683 = (uint16_t)(222); + _curvea0[688] = _10683; + uint16_t _10684 = (uint16_t)(222); + _curvea0[689] = _10684; + uint16_t _10685 = (uint16_t)(222); + _curvea0[690] = _10685; + uint16_t _10686 = (uint16_t)(222); + _curvea0[691] = _10686; + uint16_t _10687 = (uint16_t)(222); + _curvea0[692] = _10687; + uint16_t _10688 = (uint16_t)(222); + _curvea0[693] = _10688; + uint16_t _10689 = (uint16_t)(222); + _curvea0[694] = _10689; + uint16_t _10690 = (uint16_t)(223); + _curvea0[695] = _10690; + uint16_t _10691 = (uint16_t)(223); + _curvea0[696] = _10691; + uint16_t _10692 = (uint16_t)(223); + _curvea0[697] = _10692; + uint16_t _10693 = (uint16_t)(223); + _curvea0[698] = _10693; + uint16_t _10694 = (uint16_t)(223); + _curvea0[699] = _10694; + uint16_t _10695 = (uint16_t)(223); + _curvea0[700] = _10695; + uint16_t _10696 = (uint16_t)(223); + _curvea0[701] = _10696; + uint16_t _10697 = (uint16_t)(223); + _curvea0[702] = _10697; + uint16_t _10698 = (uint16_t)(224); + _curvea0[703] = _10698; + uint16_t _10699 = (uint16_t)(224); + _curvea0[704] = _10699; + uint16_t _10700 = (uint16_t)(224); + _curvea0[705] = _10700; + uint16_t _10701 = (uint16_t)(224); + _curvea0[706] = _10701; + uint16_t _10702 = (uint16_t)(224); + _curvea0[707] = _10702; + uint16_t _10703 = (uint16_t)(224); + _curvea0[708] = _10703; + uint16_t _10704 = (uint16_t)(224); + _curvea0[709] = _10704; + uint16_t _10705 = (uint16_t)(224); + _curvea0[710] = _10705; + uint16_t _10706 = (uint16_t)(225); + _curvea0[711] = _10706; + uint16_t _10707 = (uint16_t)(225); + _curvea0[712] = _10707; + uint16_t _10708 = (uint16_t)(225); + _curvea0[713] = _10708; + uint16_t _10709 = (uint16_t)(225); + _curvea0[714] = _10709; + uint16_t _10710 = (uint16_t)(225); + _curvea0[715] = _10710; + uint16_t _10711 = (uint16_t)(225); + _curvea0[716] = _10711; + uint16_t _10712 = (uint16_t)(225); + _curvea0[717] = _10712; + uint16_t _10713 = (uint16_t)(226); + _curvea0[718] = _10713; + uint16_t _10714 = (uint16_t)(226); + _curvea0[719] = _10714; + uint16_t _10715 = (uint16_t)(226); + _curvea0[720] = _10715; + uint16_t _10716 = (uint16_t)(226); + _curvea0[721] = _10716; + uint16_t _10717 = (uint16_t)(226); + _curvea0[722] = _10717; + uint16_t _10718 = (uint16_t)(226); + _curvea0[723] = _10718; + uint16_t _10719 = (uint16_t)(226); + _curvea0[724] = _10719; + uint16_t _10720 = (uint16_t)(226); + _curvea0[725] = _10720; + uint16_t _10721 = (uint16_t)(227); + _curvea0[726] = _10721; + uint16_t _10722 = (uint16_t)(227); + _curvea0[727] = _10722; + uint16_t _10723 = (uint16_t)(227); + _curvea0[728] = _10723; + uint16_t _10724 = (uint16_t)(227); + _curvea0[729] = _10724; + uint16_t _10725 = (uint16_t)(227); + _curvea0[730] = _10725; + uint16_t _10726 = (uint16_t)(227); + _curvea0[731] = _10726; + uint16_t _10727 = (uint16_t)(227); + _curvea0[732] = _10727; + uint16_t _10728 = (uint16_t)(227); + _curvea0[733] = _10728; + uint16_t _10729 = (uint16_t)(228); + _curvea0[734] = _10729; + uint16_t _10730 = (uint16_t)(228); + _curvea0[735] = _10730; + uint16_t _10731 = (uint16_t)(228); + _curvea0[736] = _10731; + uint16_t _10732 = (uint16_t)(228); + _curvea0[737] = _10732; + uint16_t _10733 = (uint16_t)(228); + _curvea0[738] = _10733; + uint16_t _10734 = (uint16_t)(228); + _curvea0[739] = _10734; + uint16_t _10735 = (uint16_t)(228); + _curvea0[740] = _10735; + uint16_t _10736 = (uint16_t)(228); + _curvea0[741] = _10736; + uint16_t _10737 = (uint16_t)(228); + _curvea0[742] = _10737; + uint16_t _10738 = (uint16_t)(229); + _curvea0[743] = _10738; + uint16_t _10739 = (uint16_t)(229); + _curvea0[744] = _10739; + uint16_t _10740 = (uint16_t)(229); + _curvea0[745] = _10740; + uint16_t _10741 = (uint16_t)(229); + _curvea0[746] = _10741; + uint16_t _10742 = (uint16_t)(229); + _curvea0[747] = _10742; + uint16_t _10743 = (uint16_t)(229); + _curvea0[748] = _10743; + uint16_t _10744 = (uint16_t)(229); + _curvea0[749] = _10744; + uint16_t _10745 = (uint16_t)(229); + _curvea0[750] = _10745; + uint16_t _10746 = (uint16_t)(230); + _curvea0[751] = _10746; + uint16_t _10747 = (uint16_t)(230); + _curvea0[752] = _10747; + uint16_t _10748 = (uint16_t)(230); + _curvea0[753] = _10748; + uint16_t _10749 = (uint16_t)(230); + _curvea0[754] = _10749; + uint16_t _10750 = (uint16_t)(230); + _curvea0[755] = _10750; + uint16_t _10751 = (uint16_t)(230); + _curvea0[756] = _10751; + uint16_t _10752 = (uint16_t)(230); + _curvea0[757] = _10752; + uint16_t _10753 = (uint16_t)(230); + _curvea0[758] = _10753; + uint16_t _10754 = (uint16_t)(231); + _curvea0[759] = _10754; + uint16_t _10755 = (uint16_t)(231); + _curvea0[760] = _10755; + uint16_t _10756 = (uint16_t)(231); + _curvea0[761] = _10756; + uint16_t _10757 = (uint16_t)(231); + _curvea0[762] = _10757; + uint16_t _10758 = (uint16_t)(231); + _curvea0[763] = _10758; + uint16_t _10759 = (uint16_t)(231); + _curvea0[764] = _10759; + uint16_t _10760 = (uint16_t)(231); + _curvea0[765] = _10760; + uint16_t _10761 = (uint16_t)(231); + _curvea0[766] = _10761; + uint16_t _10762 = (uint16_t)(231); + _curvea0[767] = _10762; + uint16_t _10763 = (uint16_t)(232); + _curvea0[768] = _10763; + uint16_t _10764 = (uint16_t)(232); + _curvea0[769] = _10764; + uint16_t _10765 = (uint16_t)(232); + _curvea0[770] = _10765; + uint16_t _10766 = (uint16_t)(232); + _curvea0[771] = _10766; + uint16_t _10767 = (uint16_t)(232); + _curvea0[772] = _10767; + uint16_t _10768 = (uint16_t)(232); + _curvea0[773] = _10768; + uint16_t _10769 = (uint16_t)(232); + _curvea0[774] = _10769; + uint16_t _10770 = (uint16_t)(232); + _curvea0[775] = _10770; + uint16_t _10771 = (uint16_t)(233); + _curvea0[776] = _10771; + uint16_t _10772 = (uint16_t)(233); + _curvea0[777] = _10772; + uint16_t _10773 = (uint16_t)(233); + _curvea0[778] = _10773; + uint16_t _10774 = (uint16_t)(233); + _curvea0[779] = _10774; + uint16_t _10775 = (uint16_t)(233); + _curvea0[780] = _10775; + uint16_t _10776 = (uint16_t)(233); + _curvea0[781] = _10776; + uint16_t _10777 = (uint16_t)(233); + _curvea0[782] = _10777; + uint16_t _10778 = (uint16_t)(233); + _curvea0[783] = _10778; + uint16_t _10779 = (uint16_t)(233); + _curvea0[784] = _10779; + uint16_t _10780 = (uint16_t)(234); + _curvea0[785] = _10780; + uint16_t _10781 = (uint16_t)(234); + _curvea0[786] = _10781; + uint16_t _10782 = (uint16_t)(234); + _curvea0[787] = _10782; + uint16_t _10783 = (uint16_t)(234); + _curvea0[788] = _10783; + uint16_t _10784 = (uint16_t)(234); + _curvea0[789] = _10784; + uint16_t _10785 = (uint16_t)(234); + _curvea0[790] = _10785; + uint16_t _10786 = (uint16_t)(234); + _curvea0[791] = _10786; + uint16_t _10787 = (uint16_t)(234); + _curvea0[792] = _10787; + uint16_t _10788 = (uint16_t)(234); + _curvea0[793] = _10788; + uint16_t _10789 = (uint16_t)(235); + _curvea0[794] = _10789; + uint16_t _10790 = (uint16_t)(235); + _curvea0[795] = _10790; + uint16_t _10791 = (uint16_t)(235); + _curvea0[796] = _10791; + uint16_t _10792 = (uint16_t)(235); + _curvea0[797] = _10792; + uint16_t _10793 = (uint16_t)(235); + _curvea0[798] = _10793; + uint16_t _10794 = (uint16_t)(235); + _curvea0[799] = _10794; + uint16_t _10795 = (uint16_t)(235); + _curvea0[800] = _10795; + uint16_t _10796 = (uint16_t)(235); + _curvea0[801] = _10796; + uint16_t _10797 = (uint16_t)(235); + _curvea0[802] = _10797; + uint16_t _10798 = (uint16_t)(236); + _curvea0[803] = _10798; + uint16_t _10799 = (uint16_t)(236); + _curvea0[804] = _10799; + uint16_t _10800 = (uint16_t)(236); + _curvea0[805] = _10800; + uint16_t _10801 = (uint16_t)(236); + _curvea0[806] = _10801; + uint16_t _10802 = (uint16_t)(236); + _curvea0[807] = _10802; + uint16_t _10803 = (uint16_t)(236); + _curvea0[808] = _10803; + uint16_t _10804 = (uint16_t)(236); + _curvea0[809] = _10804; + uint16_t _10805 = (uint16_t)(236); + _curvea0[810] = _10805; + uint16_t _10806 = (uint16_t)(236); + _curvea0[811] = _10806; + uint16_t _10807 = (uint16_t)(237); + _curvea0[812] = _10807; + uint16_t _10808 = (uint16_t)(237); + _curvea0[813] = _10808; + uint16_t _10809 = (uint16_t)(237); + _curvea0[814] = _10809; + uint16_t _10810 = (uint16_t)(237); + _curvea0[815] = _10810; + uint16_t _10811 = (uint16_t)(237); + _curvea0[816] = _10811; + uint16_t _10812 = (uint16_t)(237); + _curvea0[817] = _10812; + uint16_t _10813 = (uint16_t)(237); + _curvea0[818] = _10813; + uint16_t _10814 = (uint16_t)(237); + _curvea0[819] = _10814; + uint16_t _10815 = (uint16_t)(237); + _curvea0[820] = _10815; + uint16_t _10816 = (uint16_t)(237); + _curvea0[821] = _10816; + uint16_t _10817 = (uint16_t)(238); + _curvea0[822] = _10817; + uint16_t _10818 = (uint16_t)(238); + _curvea0[823] = _10818; + uint16_t _10819 = (uint16_t)(238); + _curvea0[824] = _10819; + uint16_t _10820 = (uint16_t)(238); + _curvea0[825] = _10820; + uint16_t _10821 = (uint16_t)(238); + _curvea0[826] = _10821; + uint16_t _10822 = (uint16_t)(238); + _curvea0[827] = _10822; + uint16_t _10823 = (uint16_t)(238); + _curvea0[828] = _10823; + uint16_t _10824 = (uint16_t)(238); + _curvea0[829] = _10824; + uint16_t _10825 = (uint16_t)(238); + _curvea0[830] = _10825; + uint16_t _10826 = (uint16_t)(239); + _curvea0[831] = _10826; + uint16_t _10827 = (uint16_t)(239); + _curvea0[832] = _10827; + uint16_t _10828 = (uint16_t)(239); + _curvea0[833] = _10828; + uint16_t _10829 = (uint16_t)(239); + _curvea0[834] = _10829; + uint16_t _10830 = (uint16_t)(239); + _curvea0[835] = _10830; + uint16_t _10831 = (uint16_t)(239); + _curvea0[836] = _10831; + uint16_t _10832 = (uint16_t)(239); + _curvea0[837] = _10832; + uint16_t _10833 = (uint16_t)(239); + _curvea0[838] = _10833; + uint16_t _10834 = (uint16_t)(239); + _curvea0[839] = _10834; + uint16_t _10835 = (uint16_t)(239); + _curvea0[840] = _10835; + uint16_t _10836 = (uint16_t)(240); + _curvea0[841] = _10836; + uint16_t _10837 = (uint16_t)(240); + _curvea0[842] = _10837; + uint16_t _10838 = (uint16_t)(240); + _curvea0[843] = _10838; + uint16_t _10839 = (uint16_t)(240); + _curvea0[844] = _10839; + uint16_t _10840 = (uint16_t)(240); + _curvea0[845] = _10840; + uint16_t _10841 = (uint16_t)(240); + _curvea0[846] = _10841; + uint16_t _10842 = (uint16_t)(240); + _curvea0[847] = _10842; + uint16_t _10843 = (uint16_t)(240); + _curvea0[848] = _10843; + uint16_t _10844 = (uint16_t)(240); + _curvea0[849] = _10844; + uint16_t _10845 = (uint16_t)(240); + _curvea0[850] = _10845; + uint16_t _10846 = (uint16_t)(241); + _curvea0[851] = _10846; + uint16_t _10847 = (uint16_t)(241); + _curvea0[852] = _10847; + uint16_t _10848 = (uint16_t)(241); + _curvea0[853] = _10848; + uint16_t _10849 = (uint16_t)(241); + _curvea0[854] = _10849; + uint16_t _10850 = (uint16_t)(241); + _curvea0[855] = _10850; + uint16_t _10851 = (uint16_t)(241); + _curvea0[856] = _10851; + uint16_t _10852 = (uint16_t)(241); + _curvea0[857] = _10852; + uint16_t _10853 = (uint16_t)(241); + _curvea0[858] = _10853; + uint16_t _10854 = (uint16_t)(241); + _curvea0[859] = _10854; + uint16_t _10855 = (uint16_t)(241); + _curvea0[860] = _10855; + uint16_t _10856 = (uint16_t)(242); + _curvea0[861] = _10856; + uint16_t _10857 = (uint16_t)(242); + _curvea0[862] = _10857; + uint16_t _10858 = (uint16_t)(242); + _curvea0[863] = _10858; + uint16_t _10859 = (uint16_t)(242); + _curvea0[864] = _10859; + uint16_t _10860 = (uint16_t)(242); + _curvea0[865] = _10860; + uint16_t _10861 = (uint16_t)(242); + _curvea0[866] = _10861; + uint16_t _10862 = (uint16_t)(242); + _curvea0[867] = _10862; + uint16_t _10863 = (uint16_t)(242); + _curvea0[868] = _10863; + uint16_t _10864 = (uint16_t)(242); + _curvea0[869] = _10864; + uint16_t _10865 = (uint16_t)(242); + _curvea0[870] = _10865; + uint16_t _10866 = (uint16_t)(243); + _curvea0[871] = _10866; + uint16_t _10867 = (uint16_t)(243); + _curvea0[872] = _10867; + uint16_t _10868 = (uint16_t)(243); + _curvea0[873] = _10868; + uint16_t _10869 = (uint16_t)(243); + _curvea0[874] = _10869; + uint16_t _10870 = (uint16_t)(243); + _curvea0[875] = _10870; + uint16_t _10871 = (uint16_t)(243); + _curvea0[876] = _10871; + uint16_t _10872 = (uint16_t)(243); + _curvea0[877] = _10872; + uint16_t _10873 = (uint16_t)(243); + _curvea0[878] = _10873; + uint16_t _10874 = (uint16_t)(243); + _curvea0[879] = _10874; + uint16_t _10875 = (uint16_t)(243); + _curvea0[880] = _10875; + uint16_t _10876 = (uint16_t)(244); + _curvea0[881] = _10876; + uint16_t _10877 = (uint16_t)(244); + _curvea0[882] = _10877; + uint16_t _10878 = (uint16_t)(244); + _curvea0[883] = _10878; + uint16_t _10879 = (uint16_t)(244); + _curvea0[884] = _10879; + uint16_t _10880 = (uint16_t)(244); + _curvea0[885] = _10880; + uint16_t _10881 = (uint16_t)(244); + _curvea0[886] = _10881; + uint16_t _10882 = (uint16_t)(244); + _curvea0[887] = _10882; + uint16_t _10883 = (uint16_t)(244); + _curvea0[888] = _10883; + uint16_t _10884 = (uint16_t)(244); + _curvea0[889] = _10884; + uint16_t _10885 = (uint16_t)(244); + _curvea0[890] = _10885; + uint16_t _10886 = (uint16_t)(244); + _curvea0[891] = _10886; + uint16_t _10887 = (uint16_t)(245); + _curvea0[892] = _10887; + uint16_t _10888 = (uint16_t)(245); + _curvea0[893] = _10888; + uint16_t _10889 = (uint16_t)(245); + _curvea0[894] = _10889; + uint16_t _10890 = (uint16_t)(245); + _curvea0[895] = _10890; + uint16_t _10891 = (uint16_t)(245); + _curvea0[896] = _10891; + uint16_t _10892 = (uint16_t)(245); + _curvea0[897] = _10892; + uint16_t _10893 = (uint16_t)(245); + _curvea0[898] = _10893; + uint16_t _10894 = (uint16_t)(245); + _curvea0[899] = _10894; + uint16_t _10895 = (uint16_t)(245); + _curvea0[900] = _10895; + uint16_t _10896 = (uint16_t)(245); + _curvea0[901] = _10896; + uint16_t _10897 = (uint16_t)(245); + _curvea0[902] = _10897; + uint16_t _10898 = (uint16_t)(246); + _curvea0[903] = _10898; + uint16_t _10899 = (uint16_t)(246); + _curvea0[904] = _10899; + uint16_t _10900 = (uint16_t)(246); + _curvea0[905] = _10900; + uint16_t _10901 = (uint16_t)(246); + _curvea0[906] = _10901; + uint16_t _10902 = (uint16_t)(246); + _curvea0[907] = _10902; + uint16_t _10903 = (uint16_t)(246); + _curvea0[908] = _10903; + uint16_t _10904 = (uint16_t)(246); + _curvea0[909] = _10904; + uint16_t _10905 = (uint16_t)(246); + _curvea0[910] = _10905; + uint16_t _10906 = (uint16_t)(246); + _curvea0[911] = _10906; + uint16_t _10907 = (uint16_t)(246); + _curvea0[912] = _10907; + uint16_t _10908 = (uint16_t)(246); + _curvea0[913] = _10908; + uint16_t _10909 = (uint16_t)(247); + _curvea0[914] = _10909; + uint16_t _10910 = (uint16_t)(247); + _curvea0[915] = _10910; + uint16_t _10911 = (uint16_t)(247); + _curvea0[916] = _10911; + uint16_t _10912 = (uint16_t)(247); + _curvea0[917] = _10912; + uint16_t _10913 = (uint16_t)(247); + _curvea0[918] = _10913; + uint16_t _10914 = (uint16_t)(247); + _curvea0[919] = _10914; + uint16_t _10915 = (uint16_t)(247); + _curvea0[920] = _10915; + uint16_t _10916 = (uint16_t)(247); + _curvea0[921] = _10916; + uint16_t _10917 = (uint16_t)(247); + _curvea0[922] = _10917; + uint16_t _10918 = (uint16_t)(247); + _curvea0[923] = _10918; + uint16_t _10919 = (uint16_t)(247); + _curvea0[924] = _10919; + uint16_t _10920 = (uint16_t)(248); + _curvea0[925] = _10920; + uint16_t _10921 = (uint16_t)(248); + _curvea0[926] = _10921; + uint16_t _10922 = (uint16_t)(248); + _curvea0[927] = _10922; + uint16_t _10923 = (uint16_t)(248); + _curvea0[928] = _10923; + uint16_t _10924 = (uint16_t)(248); + _curvea0[929] = _10924; + uint16_t _10925 = (uint16_t)(248); + _curvea0[930] = _10925; + uint16_t _10926 = (uint16_t)(248); + _curvea0[931] = _10926; + uint16_t _10927 = (uint16_t)(248); + _curvea0[932] = _10927; + uint16_t _10928 = (uint16_t)(248); + _curvea0[933] = _10928; + uint16_t _10929 = (uint16_t)(248); + _curvea0[934] = _10929; + uint16_t _10930 = (uint16_t)(248); + _curvea0[935] = _10930; + uint16_t _10931 = (uint16_t)(249); + _curvea0[936] = _10931; + uint16_t _10932 = (uint16_t)(249); + _curvea0[937] = _10932; + uint16_t _10933 = (uint16_t)(249); + _curvea0[938] = _10933; + uint16_t _10934 = (uint16_t)(249); + _curvea0[939] = _10934; + uint16_t _10935 = (uint16_t)(249); + _curvea0[940] = _10935; + uint16_t _10936 = (uint16_t)(249); + _curvea0[941] = _10936; + uint16_t _10937 = (uint16_t)(249); + _curvea0[942] = _10937; + uint16_t _10938 = (uint16_t)(249); + _curvea0[943] = _10938; + uint16_t _10939 = (uint16_t)(249); + _curvea0[944] = _10939; + uint16_t _10940 = (uint16_t)(249); + _curvea0[945] = _10940; + uint16_t _10941 = (uint16_t)(249); + _curvea0[946] = _10941; + uint16_t _10942 = (uint16_t)(249); + _curvea0[947] = _10942; + uint16_t _10943 = (uint16_t)(250); + _curvea0[948] = _10943; + uint16_t _10944 = (uint16_t)(250); + _curvea0[949] = _10944; + uint16_t _10945 = (uint16_t)(250); + _curvea0[950] = _10945; + uint16_t _10946 = (uint16_t)(250); + _curvea0[951] = _10946; + uint16_t _10947 = (uint16_t)(250); + _curvea0[952] = _10947; + uint16_t _10948 = (uint16_t)(250); + _curvea0[953] = _10948; + uint16_t _10949 = (uint16_t)(250); + _curvea0[954] = _10949; + uint16_t _10950 = (uint16_t)(250); + _curvea0[955] = _10950; + uint16_t _10951 = (uint16_t)(250); + _curvea0[956] = _10951; + uint16_t _10952 = (uint16_t)(250); + _curvea0[957] = _10952; + uint16_t _10953 = (uint16_t)(250); + _curvea0[958] = _10953; + uint16_t _10954 = (uint16_t)(250); + _curvea0[959] = _10954; + uint16_t _10955 = (uint16_t)(251); + _curvea0[960] = _10955; + uint16_t _10956 = (uint16_t)(251); + _curvea0[961] = _10956; + uint16_t _10957 = (uint16_t)(251); + _curvea0[962] = _10957; + uint16_t _10958 = (uint16_t)(251); + _curvea0[963] = _10958; + uint16_t _10959 = (uint16_t)(251); + _curvea0[964] = _10959; + uint16_t _10960 = (uint16_t)(251); + _curvea0[965] = _10960; + uint16_t _10961 = (uint16_t)(251); + _curvea0[966] = _10961; + uint16_t _10962 = (uint16_t)(251); + _curvea0[967] = _10962; + uint16_t _10963 = (uint16_t)(251); + _curvea0[968] = _10963; + uint16_t _10964 = (uint16_t)(251); + _curvea0[969] = _10964; + uint16_t _10965 = (uint16_t)(251); + _curvea0[970] = _10965; + uint16_t _10966 = (uint16_t)(251); + _curvea0[971] = _10966; + uint16_t _10967 = (uint16_t)(252); + _curvea0[972] = _10967; + uint16_t _10968 = (uint16_t)(252); + _curvea0[973] = _10968; + uint16_t _10969 = (uint16_t)(252); + _curvea0[974] = _10969; + uint16_t _10970 = (uint16_t)(252); + _curvea0[975] = _10970; + uint16_t _10971 = (uint16_t)(252); + _curvea0[976] = _10971; + uint16_t _10972 = (uint16_t)(252); + _curvea0[977] = _10972; + uint16_t _10973 = (uint16_t)(252); + _curvea0[978] = _10973; + uint16_t _10974 = (uint16_t)(252); + _curvea0[979] = _10974; + uint16_t _10975 = (uint16_t)(252); + _curvea0[980] = _10975; + uint16_t _10976 = (uint16_t)(252); + _curvea0[981] = _10976; + uint16_t _10977 = (uint16_t)(252); + _curvea0[982] = _10977; + uint16_t _10978 = (uint16_t)(252); + _curvea0[983] = _10978; + uint16_t _10979 = (uint16_t)(252); + _curvea0[984] = _10979; + uint16_t _10980 = (uint16_t)(253); + _curvea0[985] = _10980; + uint16_t _10981 = (uint16_t)(253); + _curvea0[986] = _10981; + uint16_t _10982 = (uint16_t)(253); + _curvea0[987] = _10982; + uint16_t _10983 = (uint16_t)(253); + _curvea0[988] = _10983; + uint16_t _10984 = (uint16_t)(253); + _curvea0[989] = _10984; + uint16_t _10985 = (uint16_t)(253); + _curvea0[990] = _10985; + uint16_t _10986 = (uint16_t)(253); + _curvea0[991] = _10986; + uint16_t _10987 = (uint16_t)(253); + _curvea0[992] = _10987; + uint16_t _10988 = (uint16_t)(253); + _curvea0[993] = _10988; + uint16_t _10989 = (uint16_t)(253); + _curvea0[994] = _10989; + uint16_t _10990 = (uint16_t)(253); + _curvea0[995] = _10990; + uint16_t _10991 = (uint16_t)(253); + _curvea0[996] = _10991; + uint16_t _10992 = (uint16_t)(253); + _curvea0[997] = _10992; + uint16_t _10993 = (uint16_t)(254); + _curvea0[998] = _10993; + uint16_t _10994 = (uint16_t)(254); + _curvea0[999] = _10994; + uint16_t _10995 = (uint16_t)(254); + _curvea0[1000] = _10995; + uint16_t _10996 = (uint16_t)(254); + _curvea0[1001] = _10996; + uint16_t _10997 = (uint16_t)(254); + _curvea0[1002] = _10997; + uint16_t _10998 = (uint16_t)(254); + _curvea0[1003] = _10998; + uint16_t _10999 = (uint16_t)(254); + _curvea0[1004] = _10999; + uint16_t _11000 = (uint16_t)(254); + _curvea0[1005] = _11000; + uint16_t _11001 = (uint16_t)(254); + _curvea0[1006] = _11001; + uint16_t _11002 = (uint16_t)(254); + _curvea0[1007] = _11002; + uint16_t _11003 = (uint16_t)(254); + _curvea0[1008] = _11003; + uint16_t _11004 = (uint16_t)(254); + _curvea0[1009] = _11004; + uint16_t _11005 = (uint16_t)(254); + _curvea0[1010] = _11005; + uint16_t _11006 = (uint16_t)(255); + _curvea0[1011] = _11006; + uint16_t _11007 = (uint16_t)(255); + _curvea0[1012] = _11007; + uint16_t _11008 = (uint16_t)(255); + _curvea0[1013] = _11008; + uint16_t _11009 = (uint16_t)(255); + _curvea0[1014] = _11009; + uint16_t _11010 = (uint16_t)(255); + _curvea0[1015] = _11010; + uint16_t _11011 = (uint16_t)(255); + _curvea0[1016] = _11011; + uint16_t _11012 = (uint16_t)(255); + _curvea0[1017] = _11012; + uint16_t _11013 = (uint16_t)(255); + _curvea0[1018] = _11013; + uint16_t _11014 = (uint16_t)(255); + _curvea0[1019] = _11014; + uint16_t _11015 = (uint16_t)(255); + _curvea0[1020] = _11015; + uint16_t _11016 = (uint16_t)(255); + _curvea0[1021] = _11016; + uint16_t _11017 = (uint16_t)(255); + _curvea0[1022] = _11017; + uint16_t _11018 = (uint16_t)(255); + _curvea0[1023] = _11018; + + int16_t _11019 = (int16_t)(1023); + int16_t _11020 = min(_corrected_stencil_8, _11019); + int16_t _11021 = (int16_t)(0); + int16_t _11022 = max(_11020, _11021); + uint16_t _11023 = (uint16_t)(_11022); + int32_t _11024 = (int32_t)(_11023); + uint16_t _11025 = ((const uint16_t *)_curvea0)[_11024]; + return _11025; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_8(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_9 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _11043 = (uint16_t)(0); + _curvea0[0] = _11043; + uint16_t _11044 = (uint16_t)(4); + _curvea0[1] = _11044; + uint16_t _11045 = (uint16_t)(7); + _curvea0[2] = _11045; + uint16_t _11046 = (uint16_t)(8); + _curvea0[3] = _11046; + uint16_t _11047 = (uint16_t)(10); + _curvea0[4] = _11047; + uint16_t _11048 = (uint16_t)(11); + _curvea0[5] = _11048; + uint16_t _11049 = (uint16_t)(12); + _curvea0[6] = _11049; + uint16_t _11050 = (uint16_t)(13); + _curvea0[7] = _11050; + uint16_t _11051 = (uint16_t)(14); + _curvea0[8] = _11051; + uint16_t _11052 = (uint16_t)(15); + _curvea0[9] = _11052; + uint16_t _11053 = (uint16_t)(16); + _curvea0[10] = _11053; + uint16_t _11054 = (uint16_t)(17); + _curvea0[11] = _11054; + uint16_t _11055 = (uint16_t)(18); + _curvea0[12] = _11055; + uint16_t _11056 = (uint16_t)(19); + _curvea0[13] = _11056; + uint16_t _11057 = (uint16_t)(20); + _curvea0[14] = _11057; + uint16_t _11058 = (uint16_t)(21); + _curvea0[15] = _11058; + uint16_t _11059 = (uint16_t)(22); + _curvea0[16] = _11059; + uint16_t _11060 = (uint16_t)(22); + _curvea0[17] = _11060; + uint16_t _11061 = (uint16_t)(23); + _curvea0[18] = _11061; + uint16_t _11062 = (uint16_t)(24); + _curvea0[19] = _11062; + uint16_t _11063 = (uint16_t)(25); + _curvea0[20] = _11063; + uint16_t _11064 = (uint16_t)(25); + _curvea0[21] = _11064; + uint16_t _11065 = (uint16_t)(26); + _curvea0[22] = _11065; + uint16_t _11066 = (uint16_t)(27); + _curvea0[23] = _11066; + uint16_t _11067 = (uint16_t)(27); + _curvea0[24] = _11067; + uint16_t _11068 = (uint16_t)(28); + _curvea0[25] = _11068; + uint16_t _11069 = (uint16_t)(29); + _curvea0[26] = _11069; + uint16_t _11070 = (uint16_t)(29); + _curvea0[27] = _11070; + uint16_t _11071 = (uint16_t)(30); + _curvea0[28] = _11071; + uint16_t _11072 = (uint16_t)(31); + _curvea0[29] = _11072; + uint16_t _11073 = (uint16_t)(31); + _curvea0[30] = _11073; + uint16_t _11074 = (uint16_t)(32); + _curvea0[31] = _11074; + uint16_t _11075 = (uint16_t)(33); + _curvea0[32] = _11075; + uint16_t _11076 = (uint16_t)(33); + _curvea0[33] = _11076; + uint16_t _11077 = (uint16_t)(34); + _curvea0[34] = _11077; + uint16_t _11078 = (uint16_t)(34); + _curvea0[35] = _11078; + uint16_t _11079 = (uint16_t)(35); + _curvea0[36] = _11079; + uint16_t _11080 = (uint16_t)(36); + _curvea0[37] = _11080; + uint16_t _11081 = (uint16_t)(36); + _curvea0[38] = _11081; + uint16_t _11082 = (uint16_t)(37); + _curvea0[39] = _11082; + uint16_t _11083 = (uint16_t)(37); + _curvea0[40] = _11083; + uint16_t _11084 = (uint16_t)(38); + _curvea0[41] = _11084; + uint16_t _11085 = (uint16_t)(39); + _curvea0[42] = _11085; + uint16_t _11086 = (uint16_t)(39); + _curvea0[43] = _11086; + uint16_t _11087 = (uint16_t)(40); + _curvea0[44] = _11087; + uint16_t _11088 = (uint16_t)(40); + _curvea0[45] = _11088; + uint16_t _11089 = (uint16_t)(41); + _curvea0[46] = _11089; + uint16_t _11090 = (uint16_t)(41); + _curvea0[47] = _11090; + uint16_t _11091 = (uint16_t)(42); + _curvea0[48] = _11091; + uint16_t _11092 = (uint16_t)(42); + _curvea0[49] = _11092; + uint16_t _11093 = (uint16_t)(43); + _curvea0[50] = _11093; + uint16_t _11094 = (uint16_t)(44); + _curvea0[51] = _11094; + uint16_t _11095 = (uint16_t)(44); + _curvea0[52] = _11095; + uint16_t _11096 = (uint16_t)(45); + _curvea0[53] = _11096; + uint16_t _11097 = (uint16_t)(45); + _curvea0[54] = _11097; + uint16_t _11098 = (uint16_t)(46); + _curvea0[55] = _11098; + uint16_t _11099 = (uint16_t)(46); + _curvea0[56] = _11099; + uint16_t _11100 = (uint16_t)(47); + _curvea0[57] = _11100; + uint16_t _11101 = (uint16_t)(47); + _curvea0[58] = _11101; + uint16_t _11102 = (uint16_t)(48); + _curvea0[59] = _11102; + uint16_t _11103 = (uint16_t)(48); + _curvea0[60] = _11103; + uint16_t _11104 = (uint16_t)(49); + _curvea0[61] = _11104; + uint16_t _11105 = (uint16_t)(49); + _curvea0[62] = _11105; + uint16_t _11106 = (uint16_t)(50); + _curvea0[63] = _11106; + uint16_t _11107 = (uint16_t)(50); + _curvea0[64] = _11107; + uint16_t _11108 = (uint16_t)(51); + _curvea0[65] = _11108; + uint16_t _11109 = (uint16_t)(51); + _curvea0[66] = _11109; + uint16_t _11110 = (uint16_t)(52); + _curvea0[67] = _11110; + uint16_t _11111 = (uint16_t)(52); + _curvea0[68] = _11111; + uint16_t _11112 = (uint16_t)(53); + _curvea0[69] = _11112; + uint16_t _11113 = (uint16_t)(53); + _curvea0[70] = _11113; + uint16_t _11114 = (uint16_t)(54); + _curvea0[71] = _11114; + uint16_t _11115 = (uint16_t)(54); + _curvea0[72] = _11115; + uint16_t _11116 = (uint16_t)(55); + _curvea0[73] = _11116; + uint16_t _11117 = (uint16_t)(55); + _curvea0[74] = _11117; + uint16_t _11118 = (uint16_t)(56); + _curvea0[75] = _11118; + uint16_t _11119 = (uint16_t)(56); + _curvea0[76] = _11119; + uint16_t _11120 = (uint16_t)(57); + _curvea0[77] = _11120; + uint16_t _11121 = (uint16_t)(57); + _curvea0[78] = _11121; + uint16_t _11122 = (uint16_t)(58); + _curvea0[79] = _11122; + uint16_t _11123 = (uint16_t)(58); + _curvea0[80] = _11123; + uint16_t _11124 = (uint16_t)(58); + _curvea0[81] = _11124; + uint16_t _11125 = (uint16_t)(59); + _curvea0[82] = _11125; + uint16_t _11126 = (uint16_t)(59); + _curvea0[83] = _11126; + uint16_t _11127 = (uint16_t)(60); + _curvea0[84] = _11127; + uint16_t _11128 = (uint16_t)(60); + _curvea0[85] = _11128; + uint16_t _11129 = (uint16_t)(61); + _curvea0[86] = _11129; + uint16_t _11130 = (uint16_t)(61); + _curvea0[87] = _11130; + uint16_t _11131 = (uint16_t)(62); + _curvea0[88] = _11131; + uint16_t _11132 = (uint16_t)(62); + _curvea0[89] = _11132; + uint16_t _11133 = (uint16_t)(63); + _curvea0[90] = _11133; + uint16_t _11134 = (uint16_t)(63); + _curvea0[91] = _11134; + uint16_t _11135 = (uint16_t)(64); + _curvea0[92] = _11135; + uint16_t _11136 = (uint16_t)(64); + _curvea0[93] = _11136; + uint16_t _11137 = (uint16_t)(64); + _curvea0[94] = _11137; + uint16_t _11138 = (uint16_t)(65); + _curvea0[95] = _11138; + uint16_t _11139 = (uint16_t)(65); + _curvea0[96] = _11139; + uint16_t _11140 = (uint16_t)(66); + _curvea0[97] = _11140; + uint16_t _11141 = (uint16_t)(66); + _curvea0[98] = _11141; + uint16_t _11142 = (uint16_t)(67); + _curvea0[99] = _11142; + uint16_t _11143 = (uint16_t)(67); + _curvea0[100] = _11143; + uint16_t _11144 = (uint16_t)(68); + _curvea0[101] = _11144; + uint16_t _11145 = (uint16_t)(68); + _curvea0[102] = _11145; + uint16_t _11146 = (uint16_t)(68); + _curvea0[103] = _11146; + uint16_t _11147 = (uint16_t)(69); + _curvea0[104] = _11147; + uint16_t _11148 = (uint16_t)(69); + _curvea0[105] = _11148; + uint16_t _11149 = (uint16_t)(70); + _curvea0[106] = _11149; + uint16_t _11150 = (uint16_t)(70); + _curvea0[107] = _11150; + uint16_t _11151 = (uint16_t)(71); + _curvea0[108] = _11151; + uint16_t _11152 = (uint16_t)(71); + _curvea0[109] = _11152; + uint16_t _11153 = (uint16_t)(71); + _curvea0[110] = _11153; + uint16_t _11154 = (uint16_t)(72); + _curvea0[111] = _11154; + uint16_t _11155 = (uint16_t)(72); + _curvea0[112] = _11155; + uint16_t _11156 = (uint16_t)(73); + _curvea0[113] = _11156; + uint16_t _11157 = (uint16_t)(73); + _curvea0[114] = _11157; + uint16_t _11158 = (uint16_t)(74); + _curvea0[115] = _11158; + uint16_t _11159 = (uint16_t)(74); + _curvea0[116] = _11159; + uint16_t _11160 = (uint16_t)(74); + _curvea0[117] = _11160; + uint16_t _11161 = (uint16_t)(75); + _curvea0[118] = _11161; + uint16_t _11162 = (uint16_t)(75); + _curvea0[119] = _11162; + uint16_t _11163 = (uint16_t)(76); + _curvea0[120] = _11163; + uint16_t _11164 = (uint16_t)(76); + _curvea0[121] = _11164; + uint16_t _11165 = (uint16_t)(77); + _curvea0[122] = _11165; + uint16_t _11166 = (uint16_t)(77); + _curvea0[123] = _11166; + uint16_t _11167 = (uint16_t)(77); + _curvea0[124] = _11167; + uint16_t _11168 = (uint16_t)(78); + _curvea0[125] = _11168; + uint16_t _11169 = (uint16_t)(78); + _curvea0[126] = _11169; + uint16_t _11170 = (uint16_t)(79); + _curvea0[127] = _11170; + uint16_t _11171 = (uint16_t)(79); + _curvea0[128] = _11171; + uint16_t _11172 = (uint16_t)(79); + _curvea0[129] = _11172; + uint16_t _11173 = (uint16_t)(80); + _curvea0[130] = _11173; + uint16_t _11174 = (uint16_t)(80); + _curvea0[131] = _11174; + uint16_t _11175 = (uint16_t)(81); + _curvea0[132] = _11175; + uint16_t _11176 = (uint16_t)(81); + _curvea0[133] = _11176; + uint16_t _11177 = (uint16_t)(82); + _curvea0[134] = _11177; + uint16_t _11178 = (uint16_t)(82); + _curvea0[135] = _11178; + uint16_t _11179 = (uint16_t)(82); + _curvea0[136] = _11179; + uint16_t _11180 = (uint16_t)(83); + _curvea0[137] = _11180; + uint16_t _11181 = (uint16_t)(83); + _curvea0[138] = _11181; + uint16_t _11182 = (uint16_t)(84); + _curvea0[139] = _11182; + uint16_t _11183 = (uint16_t)(84); + _curvea0[140] = _11183; + uint16_t _11184 = (uint16_t)(84); + _curvea0[141] = _11184; + uint16_t _11185 = (uint16_t)(85); + _curvea0[142] = _11185; + uint16_t _11186 = (uint16_t)(85); + _curvea0[143] = _11186; + uint16_t _11187 = (uint16_t)(86); + _curvea0[144] = _11187; + uint16_t _11188 = (uint16_t)(86); + _curvea0[145] = _11188; + uint16_t _11189 = (uint16_t)(86); + _curvea0[146] = _11189; + uint16_t _11190 = (uint16_t)(87); + _curvea0[147] = _11190; + uint16_t _11191 = (uint16_t)(87); + _curvea0[148] = _11191; + uint16_t _11192 = (uint16_t)(88); + _curvea0[149] = _11192; + uint16_t _11193 = (uint16_t)(88); + _curvea0[150] = _11193; + uint16_t _11194 = (uint16_t)(88); + _curvea0[151] = _11194; + uint16_t _11195 = (uint16_t)(89); + _curvea0[152] = _11195; + uint16_t _11196 = (uint16_t)(89); + _curvea0[153] = _11196; + uint16_t _11197 = (uint16_t)(90); + _curvea0[154] = _11197; + uint16_t _11198 = (uint16_t)(90); + _curvea0[155] = _11198; + uint16_t _11199 = (uint16_t)(90); + _curvea0[156] = _11199; + uint16_t _11200 = (uint16_t)(91); + _curvea0[157] = _11200; + uint16_t _11201 = (uint16_t)(91); + _curvea0[158] = _11201; + uint16_t _11202 = (uint16_t)(92); + _curvea0[159] = _11202; + uint16_t _11203 = (uint16_t)(92); + _curvea0[160] = _11203; + uint16_t _11204 = (uint16_t)(92); + _curvea0[161] = _11204; + uint16_t _11205 = (uint16_t)(93); + _curvea0[162] = _11205; + uint16_t _11206 = (uint16_t)(93); + _curvea0[163] = _11206; + uint16_t _11207 = (uint16_t)(93); + _curvea0[164] = _11207; + uint16_t _11208 = (uint16_t)(94); + _curvea0[165] = _11208; + uint16_t _11209 = (uint16_t)(94); + _curvea0[166] = _11209; + uint16_t _11210 = (uint16_t)(95); + _curvea0[167] = _11210; + uint16_t _11211 = (uint16_t)(95); + _curvea0[168] = _11211; + uint16_t _11212 = (uint16_t)(95); + _curvea0[169] = _11212; + uint16_t _11213 = (uint16_t)(96); + _curvea0[170] = _11213; + uint16_t _11214 = (uint16_t)(96); + _curvea0[171] = _11214; + uint16_t _11215 = (uint16_t)(97); + _curvea0[172] = _11215; + uint16_t _11216 = (uint16_t)(97); + _curvea0[173] = _11216; + uint16_t _11217 = (uint16_t)(97); + _curvea0[174] = _11217; + uint16_t _11218 = (uint16_t)(98); + _curvea0[175] = _11218; + uint16_t _11219 = (uint16_t)(98); + _curvea0[176] = _11219; + uint16_t _11220 = (uint16_t)(99); + _curvea0[177] = _11220; + uint16_t _11221 = (uint16_t)(99); + _curvea0[178] = _11221; + uint16_t _11222 = (uint16_t)(99); + _curvea0[179] = _11222; + uint16_t _11223 = (uint16_t)(100); + _curvea0[180] = _11223; + uint16_t _11224 = (uint16_t)(100); + _curvea0[181] = _11224; + uint16_t _11225 = (uint16_t)(100); + _curvea0[182] = _11225; + uint16_t _11226 = (uint16_t)(101); + _curvea0[183] = _11226; + uint16_t _11227 = (uint16_t)(101); + _curvea0[184] = _11227; + uint16_t _11228 = (uint16_t)(102); + _curvea0[185] = _11228; + uint16_t _11229 = (uint16_t)(102); + _curvea0[186] = _11229; + uint16_t _11230 = (uint16_t)(102); + _curvea0[187] = _11230; + uint16_t _11231 = (uint16_t)(103); + _curvea0[188] = _11231; + uint16_t _11232 = (uint16_t)(103); + _curvea0[189] = _11232; + uint16_t _11233 = (uint16_t)(103); + _curvea0[190] = _11233; + uint16_t _11234 = (uint16_t)(104); + _curvea0[191] = _11234; + uint16_t _11235 = (uint16_t)(104); + _curvea0[192] = _11235; + uint16_t _11236 = (uint16_t)(105); + _curvea0[193] = _11236; + uint16_t _11237 = (uint16_t)(105); + _curvea0[194] = _11237; + uint16_t _11238 = (uint16_t)(105); + _curvea0[195] = _11238; + uint16_t _11239 = (uint16_t)(106); + _curvea0[196] = _11239; + uint16_t _11240 = (uint16_t)(106); + _curvea0[197] = _11240; + uint16_t _11241 = (uint16_t)(106); + _curvea0[198] = _11241; + uint16_t _11242 = (uint16_t)(107); + _curvea0[199] = _11242; + uint16_t _11243 = (uint16_t)(107); + _curvea0[200] = _11243; + uint16_t _11244 = (uint16_t)(108); + _curvea0[201] = _11244; + uint16_t _11245 = (uint16_t)(108); + _curvea0[202] = _11245; + uint16_t _11246 = (uint16_t)(108); + _curvea0[203] = _11246; + uint16_t _11247 = (uint16_t)(109); + _curvea0[204] = _11247; + uint16_t _11248 = (uint16_t)(109); + _curvea0[205] = _11248; + uint16_t _11249 = (uint16_t)(109); + _curvea0[206] = _11249; + uint16_t _11250 = (uint16_t)(110); + _curvea0[207] = _11250; + uint16_t _11251 = (uint16_t)(110); + _curvea0[208] = _11251; + uint16_t _11252 = (uint16_t)(111); + _curvea0[209] = _11252; + uint16_t _11253 = (uint16_t)(111); + _curvea0[210] = _11253; + uint16_t _11254 = (uint16_t)(111); + _curvea0[211] = _11254; + uint16_t _11255 = (uint16_t)(112); + _curvea0[212] = _11255; + uint16_t _11256 = (uint16_t)(112); + _curvea0[213] = _11256; + uint16_t _11257 = (uint16_t)(112); + _curvea0[214] = _11257; + uint16_t _11258 = (uint16_t)(113); + _curvea0[215] = _11258; + uint16_t _11259 = (uint16_t)(113); + _curvea0[216] = _11259; + uint16_t _11260 = (uint16_t)(113); + _curvea0[217] = _11260; + uint16_t _11261 = (uint16_t)(114); + _curvea0[218] = _11261; + uint16_t _11262 = (uint16_t)(114); + _curvea0[219] = _11262; + uint16_t _11263 = (uint16_t)(115); + _curvea0[220] = _11263; + uint16_t _11264 = (uint16_t)(115); + _curvea0[221] = _11264; + uint16_t _11265 = (uint16_t)(115); + _curvea0[222] = _11265; + uint16_t _11266 = (uint16_t)(116); + _curvea0[223] = _11266; + uint16_t _11267 = (uint16_t)(116); + _curvea0[224] = _11267; + uint16_t _11268 = (uint16_t)(116); + _curvea0[225] = _11268; + uint16_t _11269 = (uint16_t)(117); + _curvea0[226] = _11269; + uint16_t _11270 = (uint16_t)(117); + _curvea0[227] = _11270; + uint16_t _11271 = (uint16_t)(117); + _curvea0[228] = _11271; + uint16_t _11272 = (uint16_t)(118); + _curvea0[229] = _11272; + uint16_t _11273 = (uint16_t)(118); + _curvea0[230] = _11273; + uint16_t _11274 = (uint16_t)(119); + _curvea0[231] = _11274; + uint16_t _11275 = (uint16_t)(119); + _curvea0[232] = _11275; + uint16_t _11276 = (uint16_t)(119); + _curvea0[233] = _11276; + uint16_t _11277 = (uint16_t)(120); + _curvea0[234] = _11277; + uint16_t _11278 = (uint16_t)(120); + _curvea0[235] = _11278; + uint16_t _11279 = (uint16_t)(120); + _curvea0[236] = _11279; + uint16_t _11280 = (uint16_t)(121); + _curvea0[237] = _11280; + uint16_t _11281 = (uint16_t)(121); + _curvea0[238] = _11281; + uint16_t _11282 = (uint16_t)(121); + _curvea0[239] = _11282; + uint16_t _11283 = (uint16_t)(122); + _curvea0[240] = _11283; + uint16_t _11284 = (uint16_t)(122); + _curvea0[241] = _11284; + uint16_t _11285 = (uint16_t)(123); + _curvea0[242] = _11285; + uint16_t _11286 = (uint16_t)(123); + _curvea0[243] = _11286; + uint16_t _11287 = (uint16_t)(123); + _curvea0[244] = _11287; + uint16_t _11288 = (uint16_t)(124); + _curvea0[245] = _11288; + uint16_t _11289 = (uint16_t)(124); + _curvea0[246] = _11289; + uint16_t _11290 = (uint16_t)(124); + _curvea0[247] = _11290; + uint16_t _11291 = (uint16_t)(125); + _curvea0[248] = _11291; + uint16_t _11292 = (uint16_t)(125); + _curvea0[249] = _11292; + uint16_t _11293 = (uint16_t)(125); + _curvea0[250] = _11293; + uint16_t _11294 = (uint16_t)(126); + _curvea0[251] = _11294; + uint16_t _11295 = (uint16_t)(126); + _curvea0[252] = _11295; + uint16_t _11296 = (uint16_t)(126); + _curvea0[253] = _11296; + uint16_t _11297 = (uint16_t)(127); + _curvea0[254] = _11297; + uint16_t _11298 = (uint16_t)(127); + _curvea0[255] = _11298; + uint16_t _11299 = (uint16_t)(128); + _curvea0[256] = _11299; + uint16_t _11300 = (uint16_t)(128); + _curvea0[257] = _11300; + uint16_t _11301 = (uint16_t)(128); + _curvea0[258] = _11301; + uint16_t _11302 = (uint16_t)(129); + _curvea0[259] = _11302; + uint16_t _11303 = (uint16_t)(129); + _curvea0[260] = _11303; + uint16_t _11304 = (uint16_t)(129); + _curvea0[261] = _11304; + uint16_t _11305 = (uint16_t)(130); + _curvea0[262] = _11305; + uint16_t _11306 = (uint16_t)(130); + _curvea0[263] = _11306; + uint16_t _11307 = (uint16_t)(130); + _curvea0[264] = _11307; + uint16_t _11308 = (uint16_t)(131); + _curvea0[265] = _11308; + uint16_t _11309 = (uint16_t)(131); + _curvea0[266] = _11309; + uint16_t _11310 = (uint16_t)(131); + _curvea0[267] = _11310; + uint16_t _11311 = (uint16_t)(132); + _curvea0[268] = _11311; + uint16_t _11312 = (uint16_t)(132); + _curvea0[269] = _11312; + uint16_t _11313 = (uint16_t)(132); + _curvea0[270] = _11313; + uint16_t _11314 = (uint16_t)(133); + _curvea0[271] = _11314; + uint16_t _11315 = (uint16_t)(133); + _curvea0[272] = _11315; + uint16_t _11316 = (uint16_t)(133); + _curvea0[273] = _11316; + uint16_t _11317 = (uint16_t)(134); + _curvea0[274] = _11317; + uint16_t _11318 = (uint16_t)(134); + _curvea0[275] = _11318; + uint16_t _11319 = (uint16_t)(134); + _curvea0[276] = _11319; + uint16_t _11320 = (uint16_t)(135); + _curvea0[277] = _11320; + uint16_t _11321 = (uint16_t)(135); + _curvea0[278] = _11321; + uint16_t _11322 = (uint16_t)(135); + _curvea0[279] = _11322; + uint16_t _11323 = (uint16_t)(136); + _curvea0[280] = _11323; + uint16_t _11324 = (uint16_t)(136); + _curvea0[281] = _11324; + uint16_t _11325 = (uint16_t)(136); + _curvea0[282] = _11325; + uint16_t _11326 = (uint16_t)(137); + _curvea0[283] = _11326; + uint16_t _11327 = (uint16_t)(137); + _curvea0[284] = _11327; + uint16_t _11328 = (uint16_t)(137); + _curvea0[285] = _11328; + uint16_t _11329 = (uint16_t)(138); + _curvea0[286] = _11329; + uint16_t _11330 = (uint16_t)(138); + _curvea0[287] = _11330; + uint16_t _11331 = (uint16_t)(138); + _curvea0[288] = _11331; + uint16_t _11332 = (uint16_t)(139); + _curvea0[289] = _11332; + uint16_t _11333 = (uint16_t)(139); + _curvea0[290] = _11333; + uint16_t _11334 = (uint16_t)(139); + _curvea0[291] = _11334; + uint16_t _11335 = (uint16_t)(140); + _curvea0[292] = _11335; + uint16_t _11336 = (uint16_t)(140); + _curvea0[293] = _11336; + uint16_t _11337 = (uint16_t)(140); + _curvea0[294] = _11337; + uint16_t _11338 = (uint16_t)(141); + _curvea0[295] = _11338; + uint16_t _11339 = (uint16_t)(141); + _curvea0[296] = _11339; + uint16_t _11340 = (uint16_t)(141); + _curvea0[297] = _11340; + uint16_t _11341 = (uint16_t)(141); + _curvea0[298] = _11341; + uint16_t _11342 = (uint16_t)(142); + _curvea0[299] = _11342; + uint16_t _11343 = (uint16_t)(142); + _curvea0[300] = _11343; + uint16_t _11344 = (uint16_t)(142); + _curvea0[301] = _11344; + uint16_t _11345 = (uint16_t)(143); + _curvea0[302] = _11345; + uint16_t _11346 = (uint16_t)(143); + _curvea0[303] = _11346; + uint16_t _11347 = (uint16_t)(143); + _curvea0[304] = _11347; + uint16_t _11348 = (uint16_t)(144); + _curvea0[305] = _11348; + uint16_t _11349 = (uint16_t)(144); + _curvea0[306] = _11349; + uint16_t _11350 = (uint16_t)(144); + _curvea0[307] = _11350; + uint16_t _11351 = (uint16_t)(145); + _curvea0[308] = _11351; + uint16_t _11352 = (uint16_t)(145); + _curvea0[309] = _11352; + uint16_t _11353 = (uint16_t)(145); + _curvea0[310] = _11353; + uint16_t _11354 = (uint16_t)(145); + _curvea0[311] = _11354; + uint16_t _11355 = (uint16_t)(146); + _curvea0[312] = _11355; + uint16_t _11356 = (uint16_t)(146); + _curvea0[313] = _11356; + uint16_t _11357 = (uint16_t)(146); + _curvea0[314] = _11357; + uint16_t _11358 = (uint16_t)(147); + _curvea0[315] = _11358; + uint16_t _11359 = (uint16_t)(147); + _curvea0[316] = _11359; + uint16_t _11360 = (uint16_t)(147); + _curvea0[317] = _11360; + uint16_t _11361 = (uint16_t)(148); + _curvea0[318] = _11361; + uint16_t _11362 = (uint16_t)(148); + _curvea0[319] = _11362; + uint16_t _11363 = (uint16_t)(148); + _curvea0[320] = _11363; + uint16_t _11364 = (uint16_t)(148); + _curvea0[321] = _11364; + uint16_t _11365 = (uint16_t)(149); + _curvea0[322] = _11365; + uint16_t _11366 = (uint16_t)(149); + _curvea0[323] = _11366; + uint16_t _11367 = (uint16_t)(149); + _curvea0[324] = _11367; + uint16_t _11368 = (uint16_t)(150); + _curvea0[325] = _11368; + uint16_t _11369 = (uint16_t)(150); + _curvea0[326] = _11369; + uint16_t _11370 = (uint16_t)(150); + _curvea0[327] = _11370; + uint16_t _11371 = (uint16_t)(150); + _curvea0[328] = _11371; + uint16_t _11372 = (uint16_t)(151); + _curvea0[329] = _11372; + uint16_t _11373 = (uint16_t)(151); + _curvea0[330] = _11373; + uint16_t _11374 = (uint16_t)(151); + _curvea0[331] = _11374; + uint16_t _11375 = (uint16_t)(152); + _curvea0[332] = _11375; + uint16_t _11376 = (uint16_t)(152); + _curvea0[333] = _11376; + uint16_t _11377 = (uint16_t)(152); + _curvea0[334] = _11377; + uint16_t _11378 = (uint16_t)(152); + _curvea0[335] = _11378; + uint16_t _11379 = (uint16_t)(153); + _curvea0[336] = _11379; + uint16_t _11380 = (uint16_t)(153); + _curvea0[337] = _11380; + uint16_t _11381 = (uint16_t)(153); + _curvea0[338] = _11381; + uint16_t _11382 = (uint16_t)(154); + _curvea0[339] = _11382; + uint16_t _11383 = (uint16_t)(154); + _curvea0[340] = _11383; + uint16_t _11384 = (uint16_t)(154); + _curvea0[341] = _11384; + uint16_t _11385 = (uint16_t)(154); + _curvea0[342] = _11385; + uint16_t _11386 = (uint16_t)(155); + _curvea0[343] = _11386; + uint16_t _11387 = (uint16_t)(155); + _curvea0[344] = _11387; + uint16_t _11388 = (uint16_t)(155); + _curvea0[345] = _11388; + uint16_t _11389 = (uint16_t)(156); + _curvea0[346] = _11389; + uint16_t _11390 = (uint16_t)(156); + _curvea0[347] = _11390; + uint16_t _11391 = (uint16_t)(156); + _curvea0[348] = _11391; + uint16_t _11392 = (uint16_t)(156); + _curvea0[349] = _11392; + uint16_t _11393 = (uint16_t)(157); + _curvea0[350] = _11393; + uint16_t _11394 = (uint16_t)(157); + _curvea0[351] = _11394; + uint16_t _11395 = (uint16_t)(157); + _curvea0[352] = _11395; + uint16_t _11396 = (uint16_t)(157); + _curvea0[353] = _11396; + uint16_t _11397 = (uint16_t)(158); + _curvea0[354] = _11397; + uint16_t _11398 = (uint16_t)(158); + _curvea0[355] = _11398; + uint16_t _11399 = (uint16_t)(158); + _curvea0[356] = _11399; + uint16_t _11400 = (uint16_t)(159); + _curvea0[357] = _11400; + uint16_t _11401 = (uint16_t)(159); + _curvea0[358] = _11401; + uint16_t _11402 = (uint16_t)(159); + _curvea0[359] = _11402; + uint16_t _11403 = (uint16_t)(159); + _curvea0[360] = _11403; + uint16_t _11404 = (uint16_t)(160); + _curvea0[361] = _11404; + uint16_t _11405 = (uint16_t)(160); + _curvea0[362] = _11405; + uint16_t _11406 = (uint16_t)(160); + _curvea0[363] = _11406; + uint16_t _11407 = (uint16_t)(160); + _curvea0[364] = _11407; + uint16_t _11408 = (uint16_t)(161); + _curvea0[365] = _11408; + uint16_t _11409 = (uint16_t)(161); + _curvea0[366] = _11409; + uint16_t _11410 = (uint16_t)(161); + _curvea0[367] = _11410; + uint16_t _11411 = (uint16_t)(161); + _curvea0[368] = _11411; + uint16_t _11412 = (uint16_t)(162); + _curvea0[369] = _11412; + uint16_t _11413 = (uint16_t)(162); + _curvea0[370] = _11413; + uint16_t _11414 = (uint16_t)(162); + _curvea0[371] = _11414; + uint16_t _11415 = (uint16_t)(162); + _curvea0[372] = _11415; + uint16_t _11416 = (uint16_t)(163); + _curvea0[373] = _11416; + uint16_t _11417 = (uint16_t)(163); + _curvea0[374] = _11417; + uint16_t _11418 = (uint16_t)(163); + _curvea0[375] = _11418; + uint16_t _11419 = (uint16_t)(163); + _curvea0[376] = _11419; + uint16_t _11420 = (uint16_t)(164); + _curvea0[377] = _11420; + uint16_t _11421 = (uint16_t)(164); + _curvea0[378] = _11421; + uint16_t _11422 = (uint16_t)(164); + _curvea0[379] = _11422; + uint16_t _11423 = (uint16_t)(164); + _curvea0[380] = _11423; + uint16_t _11424 = (uint16_t)(165); + _curvea0[381] = _11424; + uint16_t _11425 = (uint16_t)(165); + _curvea0[382] = _11425; + uint16_t _11426 = (uint16_t)(165); + _curvea0[383] = _11426; + uint16_t _11427 = (uint16_t)(166); + _curvea0[384] = _11427; + uint16_t _11428 = (uint16_t)(166); + _curvea0[385] = _11428; + uint16_t _11429 = (uint16_t)(166); + _curvea0[386] = _11429; + uint16_t _11430 = (uint16_t)(166); + _curvea0[387] = _11430; + uint16_t _11431 = (uint16_t)(167); + _curvea0[388] = _11431; + uint16_t _11432 = (uint16_t)(167); + _curvea0[389] = _11432; + uint16_t _11433 = (uint16_t)(167); + _curvea0[390] = _11433; + uint16_t _11434 = (uint16_t)(167); + _curvea0[391] = _11434; + uint16_t _11435 = (uint16_t)(167); + _curvea0[392] = _11435; + uint16_t _11436 = (uint16_t)(168); + _curvea0[393] = _11436; + uint16_t _11437 = (uint16_t)(168); + _curvea0[394] = _11437; + uint16_t _11438 = (uint16_t)(168); + _curvea0[395] = _11438; + uint16_t _11439 = (uint16_t)(168); + _curvea0[396] = _11439; + uint16_t _11440 = (uint16_t)(169); + _curvea0[397] = _11440; + uint16_t _11441 = (uint16_t)(169); + _curvea0[398] = _11441; + uint16_t _11442 = (uint16_t)(169); + _curvea0[399] = _11442; + uint16_t _11443 = (uint16_t)(169); + _curvea0[400] = _11443; + uint16_t _11444 = (uint16_t)(170); + _curvea0[401] = _11444; + uint16_t _11445 = (uint16_t)(170); + _curvea0[402] = _11445; + uint16_t _11446 = (uint16_t)(170); + _curvea0[403] = _11446; + uint16_t _11447 = (uint16_t)(170); + _curvea0[404] = _11447; + uint16_t _11448 = (uint16_t)(171); + _curvea0[405] = _11448; + uint16_t _11449 = (uint16_t)(171); + _curvea0[406] = _11449; + uint16_t _11450 = (uint16_t)(171); + _curvea0[407] = _11450; + uint16_t _11451 = (uint16_t)(171); + _curvea0[408] = _11451; + uint16_t _11452 = (uint16_t)(172); + _curvea0[409] = _11452; + uint16_t _11453 = (uint16_t)(172); + _curvea0[410] = _11453; + uint16_t _11454 = (uint16_t)(172); + _curvea0[411] = _11454; + uint16_t _11455 = (uint16_t)(172); + _curvea0[412] = _11455; + uint16_t _11456 = (uint16_t)(173); + _curvea0[413] = _11456; + uint16_t _11457 = (uint16_t)(173); + _curvea0[414] = _11457; + uint16_t _11458 = (uint16_t)(173); + _curvea0[415] = _11458; + uint16_t _11459 = (uint16_t)(173); + _curvea0[416] = _11459; + uint16_t _11460 = (uint16_t)(173); + _curvea0[417] = _11460; + uint16_t _11461 = (uint16_t)(174); + _curvea0[418] = _11461; + uint16_t _11462 = (uint16_t)(174); + _curvea0[419] = _11462; + uint16_t _11463 = (uint16_t)(174); + _curvea0[420] = _11463; + uint16_t _11464 = (uint16_t)(174); + _curvea0[421] = _11464; + uint16_t _11465 = (uint16_t)(175); + _curvea0[422] = _11465; + uint16_t _11466 = (uint16_t)(175); + _curvea0[423] = _11466; + uint16_t _11467 = (uint16_t)(175); + _curvea0[424] = _11467; + uint16_t _11468 = (uint16_t)(175); + _curvea0[425] = _11468; + uint16_t _11469 = (uint16_t)(176); + _curvea0[426] = _11469; + uint16_t _11470 = (uint16_t)(176); + _curvea0[427] = _11470; + uint16_t _11471 = (uint16_t)(176); + _curvea0[428] = _11471; + uint16_t _11472 = (uint16_t)(176); + _curvea0[429] = _11472; + uint16_t _11473 = (uint16_t)(176); + _curvea0[430] = _11473; + uint16_t _11474 = (uint16_t)(177); + _curvea0[431] = _11474; + uint16_t _11475 = (uint16_t)(177); + _curvea0[432] = _11475; + uint16_t _11476 = (uint16_t)(177); + _curvea0[433] = _11476; + uint16_t _11477 = (uint16_t)(177); + _curvea0[434] = _11477; + uint16_t _11478 = (uint16_t)(178); + _curvea0[435] = _11478; + uint16_t _11479 = (uint16_t)(178); + _curvea0[436] = _11479; + uint16_t _11480 = (uint16_t)(178); + _curvea0[437] = _11480; + uint16_t _11481 = (uint16_t)(178); + _curvea0[438] = _11481; + uint16_t _11482 = (uint16_t)(178); + _curvea0[439] = _11482; + uint16_t _11483 = (uint16_t)(179); + _curvea0[440] = _11483; + uint16_t _11484 = (uint16_t)(179); + _curvea0[441] = _11484; + uint16_t _11485 = (uint16_t)(179); + _curvea0[442] = _11485; + uint16_t _11486 = (uint16_t)(179); + _curvea0[443] = _11486; + uint16_t _11487 = (uint16_t)(180); + _curvea0[444] = _11487; + uint16_t _11488 = (uint16_t)(180); + _curvea0[445] = _11488; + uint16_t _11489 = (uint16_t)(180); + _curvea0[446] = _11489; + uint16_t _11490 = (uint16_t)(180); + _curvea0[447] = _11490; + uint16_t _11491 = (uint16_t)(180); + _curvea0[448] = _11491; + uint16_t _11492 = (uint16_t)(181); + _curvea0[449] = _11492; + uint16_t _11493 = (uint16_t)(181); + _curvea0[450] = _11493; + uint16_t _11494 = (uint16_t)(181); + _curvea0[451] = _11494; + uint16_t _11495 = (uint16_t)(181); + _curvea0[452] = _11495; + uint16_t _11496 = (uint16_t)(181); + _curvea0[453] = _11496; + uint16_t _11497 = (uint16_t)(182); + _curvea0[454] = _11497; + uint16_t _11498 = (uint16_t)(182); + _curvea0[455] = _11498; + uint16_t _11499 = (uint16_t)(182); + _curvea0[456] = _11499; + uint16_t _11500 = (uint16_t)(182); + _curvea0[457] = _11500; + uint16_t _11501 = (uint16_t)(183); + _curvea0[458] = _11501; + uint16_t _11502 = (uint16_t)(183); + _curvea0[459] = _11502; + uint16_t _11503 = (uint16_t)(183); + _curvea0[460] = _11503; + uint16_t _11504 = (uint16_t)(183); + _curvea0[461] = _11504; + uint16_t _11505 = (uint16_t)(183); + _curvea0[462] = _11505; + uint16_t _11506 = (uint16_t)(184); + _curvea0[463] = _11506; + uint16_t _11507 = (uint16_t)(184); + _curvea0[464] = _11507; + uint16_t _11508 = (uint16_t)(184); + _curvea0[465] = _11508; + uint16_t _11509 = (uint16_t)(184); + _curvea0[466] = _11509; + uint16_t _11510 = (uint16_t)(184); + _curvea0[467] = _11510; + uint16_t _11511 = (uint16_t)(185); + _curvea0[468] = _11511; + uint16_t _11512 = (uint16_t)(185); + _curvea0[469] = _11512; + uint16_t _11513 = (uint16_t)(185); + _curvea0[470] = _11513; + uint16_t _11514 = (uint16_t)(185); + _curvea0[471] = _11514; + uint16_t _11515 = (uint16_t)(185); + _curvea0[472] = _11515; + uint16_t _11516 = (uint16_t)(186); + _curvea0[473] = _11516; + uint16_t _11517 = (uint16_t)(186); + _curvea0[474] = _11517; + uint16_t _11518 = (uint16_t)(186); + _curvea0[475] = _11518; + uint16_t _11519 = (uint16_t)(186); + _curvea0[476] = _11519; + uint16_t _11520 = (uint16_t)(187); + _curvea0[477] = _11520; + uint16_t _11521 = (uint16_t)(187); + _curvea0[478] = _11521; + uint16_t _11522 = (uint16_t)(187); + _curvea0[479] = _11522; + uint16_t _11523 = (uint16_t)(187); + _curvea0[480] = _11523; + uint16_t _11524 = (uint16_t)(187); + _curvea0[481] = _11524; + uint16_t _11525 = (uint16_t)(188); + _curvea0[482] = _11525; + uint16_t _11526 = (uint16_t)(188); + _curvea0[483] = _11526; + uint16_t _11527 = (uint16_t)(188); + _curvea0[484] = _11527; + uint16_t _11528 = (uint16_t)(188); + _curvea0[485] = _11528; + uint16_t _11529 = (uint16_t)(188); + _curvea0[486] = _11529; + uint16_t _11530 = (uint16_t)(189); + _curvea0[487] = _11530; + uint16_t _11531 = (uint16_t)(189); + _curvea0[488] = _11531; + uint16_t _11532 = (uint16_t)(189); + _curvea0[489] = _11532; + uint16_t _11533 = (uint16_t)(189); + _curvea0[490] = _11533; + uint16_t _11534 = (uint16_t)(189); + _curvea0[491] = _11534; + uint16_t _11535 = (uint16_t)(190); + _curvea0[492] = _11535; + uint16_t _11536 = (uint16_t)(190); + _curvea0[493] = _11536; + uint16_t _11537 = (uint16_t)(190); + _curvea0[494] = _11537; + uint16_t _11538 = (uint16_t)(190); + _curvea0[495] = _11538; + uint16_t _11539 = (uint16_t)(190); + _curvea0[496] = _11539; + uint16_t _11540 = (uint16_t)(190); + _curvea0[497] = _11540; + uint16_t _11541 = (uint16_t)(191); + _curvea0[498] = _11541; + uint16_t _11542 = (uint16_t)(191); + _curvea0[499] = _11542; + uint16_t _11543 = (uint16_t)(191); + _curvea0[500] = _11543; + uint16_t _11544 = (uint16_t)(191); + _curvea0[501] = _11544; + uint16_t _11545 = (uint16_t)(191); + _curvea0[502] = _11545; + uint16_t _11546 = (uint16_t)(192); + _curvea0[503] = _11546; + uint16_t _11547 = (uint16_t)(192); + _curvea0[504] = _11547; + uint16_t _11548 = (uint16_t)(192); + _curvea0[505] = _11548; + uint16_t _11549 = (uint16_t)(192); + _curvea0[506] = _11549; + uint16_t _11550 = (uint16_t)(192); + _curvea0[507] = _11550; + uint16_t _11551 = (uint16_t)(193); + _curvea0[508] = _11551; + uint16_t _11552 = (uint16_t)(193); + _curvea0[509] = _11552; + uint16_t _11553 = (uint16_t)(193); + _curvea0[510] = _11553; + uint16_t _11554 = (uint16_t)(193); + _curvea0[511] = _11554; + uint16_t _11555 = (uint16_t)(193); + _curvea0[512] = _11555; + uint16_t _11556 = (uint16_t)(194); + _curvea0[513] = _11556; + uint16_t _11557 = (uint16_t)(194); + _curvea0[514] = _11557; + uint16_t _11558 = (uint16_t)(194); + _curvea0[515] = _11558; + uint16_t _11559 = (uint16_t)(194); + _curvea0[516] = _11559; + uint16_t _11560 = (uint16_t)(194); + _curvea0[517] = _11560; + uint16_t _11561 = (uint16_t)(195); + _curvea0[518] = _11561; + uint16_t _11562 = (uint16_t)(195); + _curvea0[519] = _11562; + uint16_t _11563 = (uint16_t)(195); + _curvea0[520] = _11563; + uint16_t _11564 = (uint16_t)(195); + _curvea0[521] = _11564; + uint16_t _11565 = (uint16_t)(195); + _curvea0[522] = _11565; + uint16_t _11566 = (uint16_t)(195); + _curvea0[523] = _11566; + uint16_t _11567 = (uint16_t)(196); + _curvea0[524] = _11567; + uint16_t _11568 = (uint16_t)(196); + _curvea0[525] = _11568; + uint16_t _11569 = (uint16_t)(196); + _curvea0[526] = _11569; + uint16_t _11570 = (uint16_t)(196); + _curvea0[527] = _11570; + uint16_t _11571 = (uint16_t)(196); + _curvea0[528] = _11571; + uint16_t _11572 = (uint16_t)(197); + _curvea0[529] = _11572; + uint16_t _11573 = (uint16_t)(197); + _curvea0[530] = _11573; + uint16_t _11574 = (uint16_t)(197); + _curvea0[531] = _11574; + uint16_t _11575 = (uint16_t)(197); + _curvea0[532] = _11575; + uint16_t _11576 = (uint16_t)(197); + _curvea0[533] = _11576; + uint16_t _11577 = (uint16_t)(197); + _curvea0[534] = _11577; + uint16_t _11578 = (uint16_t)(198); + _curvea0[535] = _11578; + uint16_t _11579 = (uint16_t)(198); + _curvea0[536] = _11579; + uint16_t _11580 = (uint16_t)(198); + _curvea0[537] = _11580; + uint16_t _11581 = (uint16_t)(198); + _curvea0[538] = _11581; + uint16_t _11582 = (uint16_t)(198); + _curvea0[539] = _11582; + uint16_t _11583 = (uint16_t)(199); + _curvea0[540] = _11583; + uint16_t _11584 = (uint16_t)(199); + _curvea0[541] = _11584; + uint16_t _11585 = (uint16_t)(199); + _curvea0[542] = _11585; + uint16_t _11586 = (uint16_t)(199); + _curvea0[543] = _11586; + uint16_t _11587 = (uint16_t)(199); + _curvea0[544] = _11587; + uint16_t _11588 = (uint16_t)(199); + _curvea0[545] = _11588; + uint16_t _11589 = (uint16_t)(200); + _curvea0[546] = _11589; + uint16_t _11590 = (uint16_t)(200); + _curvea0[547] = _11590; + uint16_t _11591 = (uint16_t)(200); + _curvea0[548] = _11591; + uint16_t _11592 = (uint16_t)(200); + _curvea0[549] = _11592; + uint16_t _11593 = (uint16_t)(200); + _curvea0[550] = _11593; + uint16_t _11594 = (uint16_t)(200); + _curvea0[551] = _11594; + uint16_t _11595 = (uint16_t)(201); + _curvea0[552] = _11595; + uint16_t _11596 = (uint16_t)(201); + _curvea0[553] = _11596; + uint16_t _11597 = (uint16_t)(201); + _curvea0[554] = _11597; + uint16_t _11598 = (uint16_t)(201); + _curvea0[555] = _11598; + uint16_t _11599 = (uint16_t)(201); + _curvea0[556] = _11599; + uint16_t _11600 = (uint16_t)(202); + _curvea0[557] = _11600; + uint16_t _11601 = (uint16_t)(202); + _curvea0[558] = _11601; + uint16_t _11602 = (uint16_t)(202); + _curvea0[559] = _11602; + uint16_t _11603 = (uint16_t)(202); + _curvea0[560] = _11603; + uint16_t _11604 = (uint16_t)(202); + _curvea0[561] = _11604; + uint16_t _11605 = (uint16_t)(202); + _curvea0[562] = _11605; + uint16_t _11606 = (uint16_t)(203); + _curvea0[563] = _11606; + uint16_t _11607 = (uint16_t)(203); + _curvea0[564] = _11607; + uint16_t _11608 = (uint16_t)(203); + _curvea0[565] = _11608; + uint16_t _11609 = (uint16_t)(203); + _curvea0[566] = _11609; + uint16_t _11610 = (uint16_t)(203); + _curvea0[567] = _11610; + uint16_t _11611 = (uint16_t)(203); + _curvea0[568] = _11611; + uint16_t _11612 = (uint16_t)(204); + _curvea0[569] = _11612; + uint16_t _11613 = (uint16_t)(204); + _curvea0[570] = _11613; + uint16_t _11614 = (uint16_t)(204); + _curvea0[571] = _11614; + uint16_t _11615 = (uint16_t)(204); + _curvea0[572] = _11615; + uint16_t _11616 = (uint16_t)(204); + _curvea0[573] = _11616; + uint16_t _11617 = (uint16_t)(204); + _curvea0[574] = _11617; + uint16_t _11618 = (uint16_t)(205); + _curvea0[575] = _11618; + uint16_t _11619 = (uint16_t)(205); + _curvea0[576] = _11619; + uint16_t _11620 = (uint16_t)(205); + _curvea0[577] = _11620; + uint16_t _11621 = (uint16_t)(205); + _curvea0[578] = _11621; + uint16_t _11622 = (uint16_t)(205); + _curvea0[579] = _11622; + uint16_t _11623 = (uint16_t)(205); + _curvea0[580] = _11623; + uint16_t _11624 = (uint16_t)(206); + _curvea0[581] = _11624; + uint16_t _11625 = (uint16_t)(206); + _curvea0[582] = _11625; + uint16_t _11626 = (uint16_t)(206); + _curvea0[583] = _11626; + uint16_t _11627 = (uint16_t)(206); + _curvea0[584] = _11627; + uint16_t _11628 = (uint16_t)(206); + _curvea0[585] = _11628; + uint16_t _11629 = (uint16_t)(206); + _curvea0[586] = _11629; + uint16_t _11630 = (uint16_t)(207); + _curvea0[587] = _11630; + uint16_t _11631 = (uint16_t)(207); + _curvea0[588] = _11631; + uint16_t _11632 = (uint16_t)(207); + _curvea0[589] = _11632; + uint16_t _11633 = (uint16_t)(207); + _curvea0[590] = _11633; + uint16_t _11634 = (uint16_t)(207); + _curvea0[591] = _11634; + uint16_t _11635 = (uint16_t)(207); + _curvea0[592] = _11635; + uint16_t _11636 = (uint16_t)(208); + _curvea0[593] = _11636; + uint16_t _11637 = (uint16_t)(208); + _curvea0[594] = _11637; + uint16_t _11638 = (uint16_t)(208); + _curvea0[595] = _11638; + uint16_t _11639 = (uint16_t)(208); + _curvea0[596] = _11639; + uint16_t _11640 = (uint16_t)(208); + _curvea0[597] = _11640; + uint16_t _11641 = (uint16_t)(208); + _curvea0[598] = _11641; + uint16_t _11642 = (uint16_t)(209); + _curvea0[599] = _11642; + uint16_t _11643 = (uint16_t)(209); + _curvea0[600] = _11643; + uint16_t _11644 = (uint16_t)(209); + _curvea0[601] = _11644; + uint16_t _11645 = (uint16_t)(209); + _curvea0[602] = _11645; + uint16_t _11646 = (uint16_t)(209); + _curvea0[603] = _11646; + uint16_t _11647 = (uint16_t)(209); + _curvea0[604] = _11647; + uint16_t _11648 = (uint16_t)(209); + _curvea0[605] = _11648; + uint16_t _11649 = (uint16_t)(210); + _curvea0[606] = _11649; + uint16_t _11650 = (uint16_t)(210); + _curvea0[607] = _11650; + uint16_t _11651 = (uint16_t)(210); + _curvea0[608] = _11651; + uint16_t _11652 = (uint16_t)(210); + _curvea0[609] = _11652; + uint16_t _11653 = (uint16_t)(210); + _curvea0[610] = _11653; + uint16_t _11654 = (uint16_t)(210); + _curvea0[611] = _11654; + uint16_t _11655 = (uint16_t)(211); + _curvea0[612] = _11655; + uint16_t _11656 = (uint16_t)(211); + _curvea0[613] = _11656; + uint16_t _11657 = (uint16_t)(211); + _curvea0[614] = _11657; + uint16_t _11658 = (uint16_t)(211); + _curvea0[615] = _11658; + uint16_t _11659 = (uint16_t)(211); + _curvea0[616] = _11659; + uint16_t _11660 = (uint16_t)(211); + _curvea0[617] = _11660; + uint16_t _11661 = (uint16_t)(211); + _curvea0[618] = _11661; + uint16_t _11662 = (uint16_t)(212); + _curvea0[619] = _11662; + uint16_t _11663 = (uint16_t)(212); + _curvea0[620] = _11663; + uint16_t _11664 = (uint16_t)(212); + _curvea0[621] = _11664; + uint16_t _11665 = (uint16_t)(212); + _curvea0[622] = _11665; + uint16_t _11666 = (uint16_t)(212); + _curvea0[623] = _11666; + uint16_t _11667 = (uint16_t)(212); + _curvea0[624] = _11667; + uint16_t _11668 = (uint16_t)(213); + _curvea0[625] = _11668; + uint16_t _11669 = (uint16_t)(213); + _curvea0[626] = _11669; + uint16_t _11670 = (uint16_t)(213); + _curvea0[627] = _11670; + uint16_t _11671 = (uint16_t)(213); + _curvea0[628] = _11671; + uint16_t _11672 = (uint16_t)(213); + _curvea0[629] = _11672; + uint16_t _11673 = (uint16_t)(213); + _curvea0[630] = _11673; + uint16_t _11674 = (uint16_t)(213); + _curvea0[631] = _11674; + uint16_t _11675 = (uint16_t)(214); + _curvea0[632] = _11675; + uint16_t _11676 = (uint16_t)(214); + _curvea0[633] = _11676; + uint16_t _11677 = (uint16_t)(214); + _curvea0[634] = _11677; + uint16_t _11678 = (uint16_t)(214); + _curvea0[635] = _11678; + uint16_t _11679 = (uint16_t)(214); + _curvea0[636] = _11679; + uint16_t _11680 = (uint16_t)(214); + _curvea0[637] = _11680; + uint16_t _11681 = (uint16_t)(214); + _curvea0[638] = _11681; + uint16_t _11682 = (uint16_t)(215); + _curvea0[639] = _11682; + uint16_t _11683 = (uint16_t)(215); + _curvea0[640] = _11683; + uint16_t _11684 = (uint16_t)(215); + _curvea0[641] = _11684; + uint16_t _11685 = (uint16_t)(215); + _curvea0[642] = _11685; + uint16_t _11686 = (uint16_t)(215); + _curvea0[643] = _11686; + uint16_t _11687 = (uint16_t)(215); + _curvea0[644] = _11687; + uint16_t _11688 = (uint16_t)(216); + _curvea0[645] = _11688; + uint16_t _11689 = (uint16_t)(216); + _curvea0[646] = _11689; + uint16_t _11690 = (uint16_t)(216); + _curvea0[647] = _11690; + uint16_t _11691 = (uint16_t)(216); + _curvea0[648] = _11691; + uint16_t _11692 = (uint16_t)(216); + _curvea0[649] = _11692; + uint16_t _11693 = (uint16_t)(216); + _curvea0[650] = _11693; + uint16_t _11694 = (uint16_t)(216); + _curvea0[651] = _11694; + uint16_t _11695 = (uint16_t)(217); + _curvea0[652] = _11695; + uint16_t _11696 = (uint16_t)(217); + _curvea0[653] = _11696; + uint16_t _11697 = (uint16_t)(217); + _curvea0[654] = _11697; + uint16_t _11698 = (uint16_t)(217); + _curvea0[655] = _11698; + uint16_t _11699 = (uint16_t)(217); + _curvea0[656] = _11699; + uint16_t _11700 = (uint16_t)(217); + _curvea0[657] = _11700; + uint16_t _11701 = (uint16_t)(217); + _curvea0[658] = _11701; + uint16_t _11702 = (uint16_t)(218); + _curvea0[659] = _11702; + uint16_t _11703 = (uint16_t)(218); + _curvea0[660] = _11703; + uint16_t _11704 = (uint16_t)(218); + _curvea0[661] = _11704; + uint16_t _11705 = (uint16_t)(218); + _curvea0[662] = _11705; + uint16_t _11706 = (uint16_t)(218); + _curvea0[663] = _11706; + uint16_t _11707 = (uint16_t)(218); + _curvea0[664] = _11707; + uint16_t _11708 = (uint16_t)(218); + _curvea0[665] = _11708; + uint16_t _11709 = (uint16_t)(219); + _curvea0[666] = _11709; + uint16_t _11710 = (uint16_t)(219); + _curvea0[667] = _11710; + uint16_t _11711 = (uint16_t)(219); + _curvea0[668] = _11711; + uint16_t _11712 = (uint16_t)(219); + _curvea0[669] = _11712; + uint16_t _11713 = (uint16_t)(219); + _curvea0[670] = _11713; + uint16_t _11714 = (uint16_t)(219); + _curvea0[671] = _11714; + uint16_t _11715 = (uint16_t)(219); + _curvea0[672] = _11715; + uint16_t _11716 = (uint16_t)(220); + _curvea0[673] = _11716; + uint16_t _11717 = (uint16_t)(220); + _curvea0[674] = _11717; + uint16_t _11718 = (uint16_t)(220); + _curvea0[675] = _11718; + uint16_t _11719 = (uint16_t)(220); + _curvea0[676] = _11719; + uint16_t _11720 = (uint16_t)(220); + _curvea0[677] = _11720; + uint16_t _11721 = (uint16_t)(220); + _curvea0[678] = _11721; + uint16_t _11722 = (uint16_t)(220); + _curvea0[679] = _11722; + uint16_t _11723 = (uint16_t)(220); + _curvea0[680] = _11723; + uint16_t _11724 = (uint16_t)(221); + _curvea0[681] = _11724; + uint16_t _11725 = (uint16_t)(221); + _curvea0[682] = _11725; + uint16_t _11726 = (uint16_t)(221); + _curvea0[683] = _11726; + uint16_t _11727 = (uint16_t)(221); + _curvea0[684] = _11727; + uint16_t _11728 = (uint16_t)(221); + _curvea0[685] = _11728; + uint16_t _11729 = (uint16_t)(221); + _curvea0[686] = _11729; + uint16_t _11730 = (uint16_t)(221); + _curvea0[687] = _11730; + uint16_t _11731 = (uint16_t)(222); + _curvea0[688] = _11731; + uint16_t _11732 = (uint16_t)(222); + _curvea0[689] = _11732; + uint16_t _11733 = (uint16_t)(222); + _curvea0[690] = _11733; + uint16_t _11734 = (uint16_t)(222); + _curvea0[691] = _11734; + uint16_t _11735 = (uint16_t)(222); + _curvea0[692] = _11735; + uint16_t _11736 = (uint16_t)(222); + _curvea0[693] = _11736; + uint16_t _11737 = (uint16_t)(222); + _curvea0[694] = _11737; + uint16_t _11738 = (uint16_t)(223); + _curvea0[695] = _11738; + uint16_t _11739 = (uint16_t)(223); + _curvea0[696] = _11739; + uint16_t _11740 = (uint16_t)(223); + _curvea0[697] = _11740; + uint16_t _11741 = (uint16_t)(223); + _curvea0[698] = _11741; + uint16_t _11742 = (uint16_t)(223); + _curvea0[699] = _11742; + uint16_t _11743 = (uint16_t)(223); + _curvea0[700] = _11743; + uint16_t _11744 = (uint16_t)(223); + _curvea0[701] = _11744; + uint16_t _11745 = (uint16_t)(223); + _curvea0[702] = _11745; + uint16_t _11746 = (uint16_t)(224); + _curvea0[703] = _11746; + uint16_t _11747 = (uint16_t)(224); + _curvea0[704] = _11747; + uint16_t _11748 = (uint16_t)(224); + _curvea0[705] = _11748; + uint16_t _11749 = (uint16_t)(224); + _curvea0[706] = _11749; + uint16_t _11750 = (uint16_t)(224); + _curvea0[707] = _11750; + uint16_t _11751 = (uint16_t)(224); + _curvea0[708] = _11751; + uint16_t _11752 = (uint16_t)(224); + _curvea0[709] = _11752; + uint16_t _11753 = (uint16_t)(224); + _curvea0[710] = _11753; + uint16_t _11754 = (uint16_t)(225); + _curvea0[711] = _11754; + uint16_t _11755 = (uint16_t)(225); + _curvea0[712] = _11755; + uint16_t _11756 = (uint16_t)(225); + _curvea0[713] = _11756; + uint16_t _11757 = (uint16_t)(225); + _curvea0[714] = _11757; + uint16_t _11758 = (uint16_t)(225); + _curvea0[715] = _11758; + uint16_t _11759 = (uint16_t)(225); + _curvea0[716] = _11759; + uint16_t _11760 = (uint16_t)(225); + _curvea0[717] = _11760; + uint16_t _11761 = (uint16_t)(226); + _curvea0[718] = _11761; + uint16_t _11762 = (uint16_t)(226); + _curvea0[719] = _11762; + uint16_t _11763 = (uint16_t)(226); + _curvea0[720] = _11763; + uint16_t _11764 = (uint16_t)(226); + _curvea0[721] = _11764; + uint16_t _11765 = (uint16_t)(226); + _curvea0[722] = _11765; + uint16_t _11766 = (uint16_t)(226); + _curvea0[723] = _11766; + uint16_t _11767 = (uint16_t)(226); + _curvea0[724] = _11767; + uint16_t _11768 = (uint16_t)(226); + _curvea0[725] = _11768; + uint16_t _11769 = (uint16_t)(227); + _curvea0[726] = _11769; + uint16_t _11770 = (uint16_t)(227); + _curvea0[727] = _11770; + uint16_t _11771 = (uint16_t)(227); + _curvea0[728] = _11771; + uint16_t _11772 = (uint16_t)(227); + _curvea0[729] = _11772; + uint16_t _11773 = (uint16_t)(227); + _curvea0[730] = _11773; + uint16_t _11774 = (uint16_t)(227); + _curvea0[731] = _11774; + uint16_t _11775 = (uint16_t)(227); + _curvea0[732] = _11775; + uint16_t _11776 = (uint16_t)(227); + _curvea0[733] = _11776; + uint16_t _11777 = (uint16_t)(228); + _curvea0[734] = _11777; + uint16_t _11778 = (uint16_t)(228); + _curvea0[735] = _11778; + uint16_t _11779 = (uint16_t)(228); + _curvea0[736] = _11779; + uint16_t _11780 = (uint16_t)(228); + _curvea0[737] = _11780; + uint16_t _11781 = (uint16_t)(228); + _curvea0[738] = _11781; + uint16_t _11782 = (uint16_t)(228); + _curvea0[739] = _11782; + uint16_t _11783 = (uint16_t)(228); + _curvea0[740] = _11783; + uint16_t _11784 = (uint16_t)(228); + _curvea0[741] = _11784; + uint16_t _11785 = (uint16_t)(228); + _curvea0[742] = _11785; + uint16_t _11786 = (uint16_t)(229); + _curvea0[743] = _11786; + uint16_t _11787 = (uint16_t)(229); + _curvea0[744] = _11787; + uint16_t _11788 = (uint16_t)(229); + _curvea0[745] = _11788; + uint16_t _11789 = (uint16_t)(229); + _curvea0[746] = _11789; + uint16_t _11790 = (uint16_t)(229); + _curvea0[747] = _11790; + uint16_t _11791 = (uint16_t)(229); + _curvea0[748] = _11791; + uint16_t _11792 = (uint16_t)(229); + _curvea0[749] = _11792; + uint16_t _11793 = (uint16_t)(229); + _curvea0[750] = _11793; + uint16_t _11794 = (uint16_t)(230); + _curvea0[751] = _11794; + uint16_t _11795 = (uint16_t)(230); + _curvea0[752] = _11795; + uint16_t _11796 = (uint16_t)(230); + _curvea0[753] = _11796; + uint16_t _11797 = (uint16_t)(230); + _curvea0[754] = _11797; + uint16_t _11798 = (uint16_t)(230); + _curvea0[755] = _11798; + uint16_t _11799 = (uint16_t)(230); + _curvea0[756] = _11799; + uint16_t _11800 = (uint16_t)(230); + _curvea0[757] = _11800; + uint16_t _11801 = (uint16_t)(230); + _curvea0[758] = _11801; + uint16_t _11802 = (uint16_t)(231); + _curvea0[759] = _11802; + uint16_t _11803 = (uint16_t)(231); + _curvea0[760] = _11803; + uint16_t _11804 = (uint16_t)(231); + _curvea0[761] = _11804; + uint16_t _11805 = (uint16_t)(231); + _curvea0[762] = _11805; + uint16_t _11806 = (uint16_t)(231); + _curvea0[763] = _11806; + uint16_t _11807 = (uint16_t)(231); + _curvea0[764] = _11807; + uint16_t _11808 = (uint16_t)(231); + _curvea0[765] = _11808; + uint16_t _11809 = (uint16_t)(231); + _curvea0[766] = _11809; + uint16_t _11810 = (uint16_t)(231); + _curvea0[767] = _11810; + uint16_t _11811 = (uint16_t)(232); + _curvea0[768] = _11811; + uint16_t _11812 = (uint16_t)(232); + _curvea0[769] = _11812; + uint16_t _11813 = (uint16_t)(232); + _curvea0[770] = _11813; + uint16_t _11814 = (uint16_t)(232); + _curvea0[771] = _11814; + uint16_t _11815 = (uint16_t)(232); + _curvea0[772] = _11815; + uint16_t _11816 = (uint16_t)(232); + _curvea0[773] = _11816; + uint16_t _11817 = (uint16_t)(232); + _curvea0[774] = _11817; + uint16_t _11818 = (uint16_t)(232); + _curvea0[775] = _11818; + uint16_t _11819 = (uint16_t)(233); + _curvea0[776] = _11819; + uint16_t _11820 = (uint16_t)(233); + _curvea0[777] = _11820; + uint16_t _11821 = (uint16_t)(233); + _curvea0[778] = _11821; + uint16_t _11822 = (uint16_t)(233); + _curvea0[779] = _11822; + uint16_t _11823 = (uint16_t)(233); + _curvea0[780] = _11823; + uint16_t _11824 = (uint16_t)(233); + _curvea0[781] = _11824; + uint16_t _11825 = (uint16_t)(233); + _curvea0[782] = _11825; + uint16_t _11826 = (uint16_t)(233); + _curvea0[783] = _11826; + uint16_t _11827 = (uint16_t)(233); + _curvea0[784] = _11827; + uint16_t _11828 = (uint16_t)(234); + _curvea0[785] = _11828; + uint16_t _11829 = (uint16_t)(234); + _curvea0[786] = _11829; + uint16_t _11830 = (uint16_t)(234); + _curvea0[787] = _11830; + uint16_t _11831 = (uint16_t)(234); + _curvea0[788] = _11831; + uint16_t _11832 = (uint16_t)(234); + _curvea0[789] = _11832; + uint16_t _11833 = (uint16_t)(234); + _curvea0[790] = _11833; + uint16_t _11834 = (uint16_t)(234); + _curvea0[791] = _11834; + uint16_t _11835 = (uint16_t)(234); + _curvea0[792] = _11835; + uint16_t _11836 = (uint16_t)(234); + _curvea0[793] = _11836; + uint16_t _11837 = (uint16_t)(235); + _curvea0[794] = _11837; + uint16_t _11838 = (uint16_t)(235); + _curvea0[795] = _11838; + uint16_t _11839 = (uint16_t)(235); + _curvea0[796] = _11839; + uint16_t _11840 = (uint16_t)(235); + _curvea0[797] = _11840; + uint16_t _11841 = (uint16_t)(235); + _curvea0[798] = _11841; + uint16_t _11842 = (uint16_t)(235); + _curvea0[799] = _11842; + uint16_t _11843 = (uint16_t)(235); + _curvea0[800] = _11843; + uint16_t _11844 = (uint16_t)(235); + _curvea0[801] = _11844; + uint16_t _11845 = (uint16_t)(235); + _curvea0[802] = _11845; + uint16_t _11846 = (uint16_t)(236); + _curvea0[803] = _11846; + uint16_t _11847 = (uint16_t)(236); + _curvea0[804] = _11847; + uint16_t _11848 = (uint16_t)(236); + _curvea0[805] = _11848; + uint16_t _11849 = (uint16_t)(236); + _curvea0[806] = _11849; + uint16_t _11850 = (uint16_t)(236); + _curvea0[807] = _11850; + uint16_t _11851 = (uint16_t)(236); + _curvea0[808] = _11851; + uint16_t _11852 = (uint16_t)(236); + _curvea0[809] = _11852; + uint16_t _11853 = (uint16_t)(236); + _curvea0[810] = _11853; + uint16_t _11854 = (uint16_t)(236); + _curvea0[811] = _11854; + uint16_t _11855 = (uint16_t)(237); + _curvea0[812] = _11855; + uint16_t _11856 = (uint16_t)(237); + _curvea0[813] = _11856; + uint16_t _11857 = (uint16_t)(237); + _curvea0[814] = _11857; + uint16_t _11858 = (uint16_t)(237); + _curvea0[815] = _11858; + uint16_t _11859 = (uint16_t)(237); + _curvea0[816] = _11859; + uint16_t _11860 = (uint16_t)(237); + _curvea0[817] = _11860; + uint16_t _11861 = (uint16_t)(237); + _curvea0[818] = _11861; + uint16_t _11862 = (uint16_t)(237); + _curvea0[819] = _11862; + uint16_t _11863 = (uint16_t)(237); + _curvea0[820] = _11863; + uint16_t _11864 = (uint16_t)(237); + _curvea0[821] = _11864; + uint16_t _11865 = (uint16_t)(238); + _curvea0[822] = _11865; + uint16_t _11866 = (uint16_t)(238); + _curvea0[823] = _11866; + uint16_t _11867 = (uint16_t)(238); + _curvea0[824] = _11867; + uint16_t _11868 = (uint16_t)(238); + _curvea0[825] = _11868; + uint16_t _11869 = (uint16_t)(238); + _curvea0[826] = _11869; + uint16_t _11870 = (uint16_t)(238); + _curvea0[827] = _11870; + uint16_t _11871 = (uint16_t)(238); + _curvea0[828] = _11871; + uint16_t _11872 = (uint16_t)(238); + _curvea0[829] = _11872; + uint16_t _11873 = (uint16_t)(238); + _curvea0[830] = _11873; + uint16_t _11874 = (uint16_t)(239); + _curvea0[831] = _11874; + uint16_t _11875 = (uint16_t)(239); + _curvea0[832] = _11875; + uint16_t _11876 = (uint16_t)(239); + _curvea0[833] = _11876; + uint16_t _11877 = (uint16_t)(239); + _curvea0[834] = _11877; + uint16_t _11878 = (uint16_t)(239); + _curvea0[835] = _11878; + uint16_t _11879 = (uint16_t)(239); + _curvea0[836] = _11879; + uint16_t _11880 = (uint16_t)(239); + _curvea0[837] = _11880; + uint16_t _11881 = (uint16_t)(239); + _curvea0[838] = _11881; + uint16_t _11882 = (uint16_t)(239); + _curvea0[839] = _11882; + uint16_t _11883 = (uint16_t)(239); + _curvea0[840] = _11883; + uint16_t _11884 = (uint16_t)(240); + _curvea0[841] = _11884; + uint16_t _11885 = (uint16_t)(240); + _curvea0[842] = _11885; + uint16_t _11886 = (uint16_t)(240); + _curvea0[843] = _11886; + uint16_t _11887 = (uint16_t)(240); + _curvea0[844] = _11887; + uint16_t _11888 = (uint16_t)(240); + _curvea0[845] = _11888; + uint16_t _11889 = (uint16_t)(240); + _curvea0[846] = _11889; + uint16_t _11890 = (uint16_t)(240); + _curvea0[847] = _11890; + uint16_t _11891 = (uint16_t)(240); + _curvea0[848] = _11891; + uint16_t _11892 = (uint16_t)(240); + _curvea0[849] = _11892; + uint16_t _11893 = (uint16_t)(240); + _curvea0[850] = _11893; + uint16_t _11894 = (uint16_t)(241); + _curvea0[851] = _11894; + uint16_t _11895 = (uint16_t)(241); + _curvea0[852] = _11895; + uint16_t _11896 = (uint16_t)(241); + _curvea0[853] = _11896; + uint16_t _11897 = (uint16_t)(241); + _curvea0[854] = _11897; + uint16_t _11898 = (uint16_t)(241); + _curvea0[855] = _11898; + uint16_t _11899 = (uint16_t)(241); + _curvea0[856] = _11899; + uint16_t _11900 = (uint16_t)(241); + _curvea0[857] = _11900; + uint16_t _11901 = (uint16_t)(241); + _curvea0[858] = _11901; + uint16_t _11902 = (uint16_t)(241); + _curvea0[859] = _11902; + uint16_t _11903 = (uint16_t)(241); + _curvea0[860] = _11903; + uint16_t _11904 = (uint16_t)(242); + _curvea0[861] = _11904; + uint16_t _11905 = (uint16_t)(242); + _curvea0[862] = _11905; + uint16_t _11906 = (uint16_t)(242); + _curvea0[863] = _11906; + uint16_t _11907 = (uint16_t)(242); + _curvea0[864] = _11907; + uint16_t _11908 = (uint16_t)(242); + _curvea0[865] = _11908; + uint16_t _11909 = (uint16_t)(242); + _curvea0[866] = _11909; + uint16_t _11910 = (uint16_t)(242); + _curvea0[867] = _11910; + uint16_t _11911 = (uint16_t)(242); + _curvea0[868] = _11911; + uint16_t _11912 = (uint16_t)(242); + _curvea0[869] = _11912; + uint16_t _11913 = (uint16_t)(242); + _curvea0[870] = _11913; + uint16_t _11914 = (uint16_t)(243); + _curvea0[871] = _11914; + uint16_t _11915 = (uint16_t)(243); + _curvea0[872] = _11915; + uint16_t _11916 = (uint16_t)(243); + _curvea0[873] = _11916; + uint16_t _11917 = (uint16_t)(243); + _curvea0[874] = _11917; + uint16_t _11918 = (uint16_t)(243); + _curvea0[875] = _11918; + uint16_t _11919 = (uint16_t)(243); + _curvea0[876] = _11919; + uint16_t _11920 = (uint16_t)(243); + _curvea0[877] = _11920; + uint16_t _11921 = (uint16_t)(243); + _curvea0[878] = _11921; + uint16_t _11922 = (uint16_t)(243); + _curvea0[879] = _11922; + uint16_t _11923 = (uint16_t)(243); + _curvea0[880] = _11923; + uint16_t _11924 = (uint16_t)(244); + _curvea0[881] = _11924; + uint16_t _11925 = (uint16_t)(244); + _curvea0[882] = _11925; + uint16_t _11926 = (uint16_t)(244); + _curvea0[883] = _11926; + uint16_t _11927 = (uint16_t)(244); + _curvea0[884] = _11927; + uint16_t _11928 = (uint16_t)(244); + _curvea0[885] = _11928; + uint16_t _11929 = (uint16_t)(244); + _curvea0[886] = _11929; + uint16_t _11930 = (uint16_t)(244); + _curvea0[887] = _11930; + uint16_t _11931 = (uint16_t)(244); + _curvea0[888] = _11931; + uint16_t _11932 = (uint16_t)(244); + _curvea0[889] = _11932; + uint16_t _11933 = (uint16_t)(244); + _curvea0[890] = _11933; + uint16_t _11934 = (uint16_t)(244); + _curvea0[891] = _11934; + uint16_t _11935 = (uint16_t)(245); + _curvea0[892] = _11935; + uint16_t _11936 = (uint16_t)(245); + _curvea0[893] = _11936; + uint16_t _11937 = (uint16_t)(245); + _curvea0[894] = _11937; + uint16_t _11938 = (uint16_t)(245); + _curvea0[895] = _11938; + uint16_t _11939 = (uint16_t)(245); + _curvea0[896] = _11939; + uint16_t _11940 = (uint16_t)(245); + _curvea0[897] = _11940; + uint16_t _11941 = (uint16_t)(245); + _curvea0[898] = _11941; + uint16_t _11942 = (uint16_t)(245); + _curvea0[899] = _11942; + uint16_t _11943 = (uint16_t)(245); + _curvea0[900] = _11943; + uint16_t _11944 = (uint16_t)(245); + _curvea0[901] = _11944; + uint16_t _11945 = (uint16_t)(245); + _curvea0[902] = _11945; + uint16_t _11946 = (uint16_t)(246); + _curvea0[903] = _11946; + uint16_t _11947 = (uint16_t)(246); + _curvea0[904] = _11947; + uint16_t _11948 = (uint16_t)(246); + _curvea0[905] = _11948; + uint16_t _11949 = (uint16_t)(246); + _curvea0[906] = _11949; + uint16_t _11950 = (uint16_t)(246); + _curvea0[907] = _11950; + uint16_t _11951 = (uint16_t)(246); + _curvea0[908] = _11951; + uint16_t _11952 = (uint16_t)(246); + _curvea0[909] = _11952; + uint16_t _11953 = (uint16_t)(246); + _curvea0[910] = _11953; + uint16_t _11954 = (uint16_t)(246); + _curvea0[911] = _11954; + uint16_t _11955 = (uint16_t)(246); + _curvea0[912] = _11955; + uint16_t _11956 = (uint16_t)(246); + _curvea0[913] = _11956; + uint16_t _11957 = (uint16_t)(247); + _curvea0[914] = _11957; + uint16_t _11958 = (uint16_t)(247); + _curvea0[915] = _11958; + uint16_t _11959 = (uint16_t)(247); + _curvea0[916] = _11959; + uint16_t _11960 = (uint16_t)(247); + _curvea0[917] = _11960; + uint16_t _11961 = (uint16_t)(247); + _curvea0[918] = _11961; + uint16_t _11962 = (uint16_t)(247); + _curvea0[919] = _11962; + uint16_t _11963 = (uint16_t)(247); + _curvea0[920] = _11963; + uint16_t _11964 = (uint16_t)(247); + _curvea0[921] = _11964; + uint16_t _11965 = (uint16_t)(247); + _curvea0[922] = _11965; + uint16_t _11966 = (uint16_t)(247); + _curvea0[923] = _11966; + uint16_t _11967 = (uint16_t)(247); + _curvea0[924] = _11967; + uint16_t _11968 = (uint16_t)(248); + _curvea0[925] = _11968; + uint16_t _11969 = (uint16_t)(248); + _curvea0[926] = _11969; + uint16_t _11970 = (uint16_t)(248); + _curvea0[927] = _11970; + uint16_t _11971 = (uint16_t)(248); + _curvea0[928] = _11971; + uint16_t _11972 = (uint16_t)(248); + _curvea0[929] = _11972; + uint16_t _11973 = (uint16_t)(248); + _curvea0[930] = _11973; + uint16_t _11974 = (uint16_t)(248); + _curvea0[931] = _11974; + uint16_t _11975 = (uint16_t)(248); + _curvea0[932] = _11975; + uint16_t _11976 = (uint16_t)(248); + _curvea0[933] = _11976; + uint16_t _11977 = (uint16_t)(248); + _curvea0[934] = _11977; + uint16_t _11978 = (uint16_t)(248); + _curvea0[935] = _11978; + uint16_t _11979 = (uint16_t)(249); + _curvea0[936] = _11979; + uint16_t _11980 = (uint16_t)(249); + _curvea0[937] = _11980; + uint16_t _11981 = (uint16_t)(249); + _curvea0[938] = _11981; + uint16_t _11982 = (uint16_t)(249); + _curvea0[939] = _11982; + uint16_t _11983 = (uint16_t)(249); + _curvea0[940] = _11983; + uint16_t _11984 = (uint16_t)(249); + _curvea0[941] = _11984; + uint16_t _11985 = (uint16_t)(249); + _curvea0[942] = _11985; + uint16_t _11986 = (uint16_t)(249); + _curvea0[943] = _11986; + uint16_t _11987 = (uint16_t)(249); + _curvea0[944] = _11987; + uint16_t _11988 = (uint16_t)(249); + _curvea0[945] = _11988; + uint16_t _11989 = (uint16_t)(249); + _curvea0[946] = _11989; + uint16_t _11990 = (uint16_t)(249); + _curvea0[947] = _11990; + uint16_t _11991 = (uint16_t)(250); + _curvea0[948] = _11991; + uint16_t _11992 = (uint16_t)(250); + _curvea0[949] = _11992; + uint16_t _11993 = (uint16_t)(250); + _curvea0[950] = _11993; + uint16_t _11994 = (uint16_t)(250); + _curvea0[951] = _11994; + uint16_t _11995 = (uint16_t)(250); + _curvea0[952] = _11995; + uint16_t _11996 = (uint16_t)(250); + _curvea0[953] = _11996; + uint16_t _11997 = (uint16_t)(250); + _curvea0[954] = _11997; + uint16_t _11998 = (uint16_t)(250); + _curvea0[955] = _11998; + uint16_t _11999 = (uint16_t)(250); + _curvea0[956] = _11999; + uint16_t _12000 = (uint16_t)(250); + _curvea0[957] = _12000; + uint16_t _12001 = (uint16_t)(250); + _curvea0[958] = _12001; + uint16_t _12002 = (uint16_t)(250); + _curvea0[959] = _12002; + uint16_t _12003 = (uint16_t)(251); + _curvea0[960] = _12003; + uint16_t _12004 = (uint16_t)(251); + _curvea0[961] = _12004; + uint16_t _12005 = (uint16_t)(251); + _curvea0[962] = _12005; + uint16_t _12006 = (uint16_t)(251); + _curvea0[963] = _12006; + uint16_t _12007 = (uint16_t)(251); + _curvea0[964] = _12007; + uint16_t _12008 = (uint16_t)(251); + _curvea0[965] = _12008; + uint16_t _12009 = (uint16_t)(251); + _curvea0[966] = _12009; + uint16_t _12010 = (uint16_t)(251); + _curvea0[967] = _12010; + uint16_t _12011 = (uint16_t)(251); + _curvea0[968] = _12011; + uint16_t _12012 = (uint16_t)(251); + _curvea0[969] = _12012; + uint16_t _12013 = (uint16_t)(251); + _curvea0[970] = _12013; + uint16_t _12014 = (uint16_t)(251); + _curvea0[971] = _12014; + uint16_t _12015 = (uint16_t)(252); + _curvea0[972] = _12015; + uint16_t _12016 = (uint16_t)(252); + _curvea0[973] = _12016; + uint16_t _12017 = (uint16_t)(252); + _curvea0[974] = _12017; + uint16_t _12018 = (uint16_t)(252); + _curvea0[975] = _12018; + uint16_t _12019 = (uint16_t)(252); + _curvea0[976] = _12019; + uint16_t _12020 = (uint16_t)(252); + _curvea0[977] = _12020; + uint16_t _12021 = (uint16_t)(252); + _curvea0[978] = _12021; + uint16_t _12022 = (uint16_t)(252); + _curvea0[979] = _12022; + uint16_t _12023 = (uint16_t)(252); + _curvea0[980] = _12023; + uint16_t _12024 = (uint16_t)(252); + _curvea0[981] = _12024; + uint16_t _12025 = (uint16_t)(252); + _curvea0[982] = _12025; + uint16_t _12026 = (uint16_t)(252); + _curvea0[983] = _12026; + uint16_t _12027 = (uint16_t)(252); + _curvea0[984] = _12027; + uint16_t _12028 = (uint16_t)(253); + _curvea0[985] = _12028; + uint16_t _12029 = (uint16_t)(253); + _curvea0[986] = _12029; + uint16_t _12030 = (uint16_t)(253); + _curvea0[987] = _12030; + uint16_t _12031 = (uint16_t)(253); + _curvea0[988] = _12031; + uint16_t _12032 = (uint16_t)(253); + _curvea0[989] = _12032; + uint16_t _12033 = (uint16_t)(253); + _curvea0[990] = _12033; + uint16_t _12034 = (uint16_t)(253); + _curvea0[991] = _12034; + uint16_t _12035 = (uint16_t)(253); + _curvea0[992] = _12035; + uint16_t _12036 = (uint16_t)(253); + _curvea0[993] = _12036; + uint16_t _12037 = (uint16_t)(253); + _curvea0[994] = _12037; + uint16_t _12038 = (uint16_t)(253); + _curvea0[995] = _12038; + uint16_t _12039 = (uint16_t)(253); + _curvea0[996] = _12039; + uint16_t _12040 = (uint16_t)(253); + _curvea0[997] = _12040; + uint16_t _12041 = (uint16_t)(254); + _curvea0[998] = _12041; + uint16_t _12042 = (uint16_t)(254); + _curvea0[999] = _12042; + uint16_t _12043 = (uint16_t)(254); + _curvea0[1000] = _12043; + uint16_t _12044 = (uint16_t)(254); + _curvea0[1001] = _12044; + uint16_t _12045 = (uint16_t)(254); + _curvea0[1002] = _12045; + uint16_t _12046 = (uint16_t)(254); + _curvea0[1003] = _12046; + uint16_t _12047 = (uint16_t)(254); + _curvea0[1004] = _12047; + uint16_t _12048 = (uint16_t)(254); + _curvea0[1005] = _12048; + uint16_t _12049 = (uint16_t)(254); + _curvea0[1006] = _12049; + uint16_t _12050 = (uint16_t)(254); + _curvea0[1007] = _12050; + uint16_t _12051 = (uint16_t)(254); + _curvea0[1008] = _12051; + uint16_t _12052 = (uint16_t)(254); + _curvea0[1009] = _12052; + uint16_t _12053 = (uint16_t)(254); + _curvea0[1010] = _12053; + uint16_t _12054 = (uint16_t)(255); + _curvea0[1011] = _12054; + uint16_t _12055 = (uint16_t)(255); + _curvea0[1012] = _12055; + uint16_t _12056 = (uint16_t)(255); + _curvea0[1013] = _12056; + uint16_t _12057 = (uint16_t)(255); + _curvea0[1014] = _12057; + uint16_t _12058 = (uint16_t)(255); + _curvea0[1015] = _12058; + uint16_t _12059 = (uint16_t)(255); + _curvea0[1016] = _12059; + uint16_t _12060 = (uint16_t)(255); + _curvea0[1017] = _12060; + uint16_t _12061 = (uint16_t)(255); + _curvea0[1018] = _12061; + uint16_t _12062 = (uint16_t)(255); + _curvea0[1019] = _12062; + uint16_t _12063 = (uint16_t)(255); + _curvea0[1020] = _12063; + uint16_t _12064 = (uint16_t)(255); + _curvea0[1021] = _12064; + uint16_t _12065 = (uint16_t)(255); + _curvea0[1022] = _12065; + uint16_t _12066 = (uint16_t)(255); + _curvea0[1023] = _12066; + + int16_t _12067 = (int16_t)(1023); + int16_t _12068 = min(_corrected_stencil_9, _12067); + int16_t _12069 = (int16_t)(0); + int16_t _12070 = max(_12068, _12069); + uint16_t _12071 = (uint16_t)(_12070); + int32_t _12072 = (int32_t)(_12071); + uint16_t _12073 = ((const uint16_t *)_curvea0)[_12072]; + return _12073; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_9(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_10 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _12091 = (uint16_t)(0); + _curvea0[0] = _12091; + uint16_t _12092 = (uint16_t)(4); + _curvea0[1] = _12092; + uint16_t _12093 = (uint16_t)(7); + _curvea0[2] = _12093; + uint16_t _12094 = (uint16_t)(8); + _curvea0[3] = _12094; + uint16_t _12095 = (uint16_t)(10); + _curvea0[4] = _12095; + uint16_t _12096 = (uint16_t)(11); + _curvea0[5] = _12096; + uint16_t _12097 = (uint16_t)(12); + _curvea0[6] = _12097; + uint16_t _12098 = (uint16_t)(13); + _curvea0[7] = _12098; + uint16_t _12099 = (uint16_t)(14); + _curvea0[8] = _12099; + uint16_t _12100 = (uint16_t)(15); + _curvea0[9] = _12100; + uint16_t _12101 = (uint16_t)(16); + _curvea0[10] = _12101; + uint16_t _12102 = (uint16_t)(17); + _curvea0[11] = _12102; + uint16_t _12103 = (uint16_t)(18); + _curvea0[12] = _12103; + uint16_t _12104 = (uint16_t)(19); + _curvea0[13] = _12104; + uint16_t _12105 = (uint16_t)(20); + _curvea0[14] = _12105; + uint16_t _12106 = (uint16_t)(21); + _curvea0[15] = _12106; + uint16_t _12107 = (uint16_t)(22); + _curvea0[16] = _12107; + uint16_t _12108 = (uint16_t)(22); + _curvea0[17] = _12108; + uint16_t _12109 = (uint16_t)(23); + _curvea0[18] = _12109; + uint16_t _12110 = (uint16_t)(24); + _curvea0[19] = _12110; + uint16_t _12111 = (uint16_t)(25); + _curvea0[20] = _12111; + uint16_t _12112 = (uint16_t)(25); + _curvea0[21] = _12112; + uint16_t _12113 = (uint16_t)(26); + _curvea0[22] = _12113; + uint16_t _12114 = (uint16_t)(27); + _curvea0[23] = _12114; + uint16_t _12115 = (uint16_t)(27); + _curvea0[24] = _12115; + uint16_t _12116 = (uint16_t)(28); + _curvea0[25] = _12116; + uint16_t _12117 = (uint16_t)(29); + _curvea0[26] = _12117; + uint16_t _12118 = (uint16_t)(29); + _curvea0[27] = _12118; + uint16_t _12119 = (uint16_t)(30); + _curvea0[28] = _12119; + uint16_t _12120 = (uint16_t)(31); + _curvea0[29] = _12120; + uint16_t _12121 = (uint16_t)(31); + _curvea0[30] = _12121; + uint16_t _12122 = (uint16_t)(32); + _curvea0[31] = _12122; + uint16_t _12123 = (uint16_t)(33); + _curvea0[32] = _12123; + uint16_t _12124 = (uint16_t)(33); + _curvea0[33] = _12124; + uint16_t _12125 = (uint16_t)(34); + _curvea0[34] = _12125; + uint16_t _12126 = (uint16_t)(34); + _curvea0[35] = _12126; + uint16_t _12127 = (uint16_t)(35); + _curvea0[36] = _12127; + uint16_t _12128 = (uint16_t)(36); + _curvea0[37] = _12128; + uint16_t _12129 = (uint16_t)(36); + _curvea0[38] = _12129; + uint16_t _12130 = (uint16_t)(37); + _curvea0[39] = _12130; + uint16_t _12131 = (uint16_t)(37); + _curvea0[40] = _12131; + uint16_t _12132 = (uint16_t)(38); + _curvea0[41] = _12132; + uint16_t _12133 = (uint16_t)(39); + _curvea0[42] = _12133; + uint16_t _12134 = (uint16_t)(39); + _curvea0[43] = _12134; + uint16_t _12135 = (uint16_t)(40); + _curvea0[44] = _12135; + uint16_t _12136 = (uint16_t)(40); + _curvea0[45] = _12136; + uint16_t _12137 = (uint16_t)(41); + _curvea0[46] = _12137; + uint16_t _12138 = (uint16_t)(41); + _curvea0[47] = _12138; + uint16_t _12139 = (uint16_t)(42); + _curvea0[48] = _12139; + uint16_t _12140 = (uint16_t)(42); + _curvea0[49] = _12140; + uint16_t _12141 = (uint16_t)(43); + _curvea0[50] = _12141; + uint16_t _12142 = (uint16_t)(44); + _curvea0[51] = _12142; + uint16_t _12143 = (uint16_t)(44); + _curvea0[52] = _12143; + uint16_t _12144 = (uint16_t)(45); + _curvea0[53] = _12144; + uint16_t _12145 = (uint16_t)(45); + _curvea0[54] = _12145; + uint16_t _12146 = (uint16_t)(46); + _curvea0[55] = _12146; + uint16_t _12147 = (uint16_t)(46); + _curvea0[56] = _12147; + uint16_t _12148 = (uint16_t)(47); + _curvea0[57] = _12148; + uint16_t _12149 = (uint16_t)(47); + _curvea0[58] = _12149; + uint16_t _12150 = (uint16_t)(48); + _curvea0[59] = _12150; + uint16_t _12151 = (uint16_t)(48); + _curvea0[60] = _12151; + uint16_t _12152 = (uint16_t)(49); + _curvea0[61] = _12152; + uint16_t _12153 = (uint16_t)(49); + _curvea0[62] = _12153; + uint16_t _12154 = (uint16_t)(50); + _curvea0[63] = _12154; + uint16_t _12155 = (uint16_t)(50); + _curvea0[64] = _12155; + uint16_t _12156 = (uint16_t)(51); + _curvea0[65] = _12156; + uint16_t _12157 = (uint16_t)(51); + _curvea0[66] = _12157; + uint16_t _12158 = (uint16_t)(52); + _curvea0[67] = _12158; + uint16_t _12159 = (uint16_t)(52); + _curvea0[68] = _12159; + uint16_t _12160 = (uint16_t)(53); + _curvea0[69] = _12160; + uint16_t _12161 = (uint16_t)(53); + _curvea0[70] = _12161; + uint16_t _12162 = (uint16_t)(54); + _curvea0[71] = _12162; + uint16_t _12163 = (uint16_t)(54); + _curvea0[72] = _12163; + uint16_t _12164 = (uint16_t)(55); + _curvea0[73] = _12164; + uint16_t _12165 = (uint16_t)(55); + _curvea0[74] = _12165; + uint16_t _12166 = (uint16_t)(56); + _curvea0[75] = _12166; + uint16_t _12167 = (uint16_t)(56); + _curvea0[76] = _12167; + uint16_t _12168 = (uint16_t)(57); + _curvea0[77] = _12168; + uint16_t _12169 = (uint16_t)(57); + _curvea0[78] = _12169; + uint16_t _12170 = (uint16_t)(58); + _curvea0[79] = _12170; + uint16_t _12171 = (uint16_t)(58); + _curvea0[80] = _12171; + uint16_t _12172 = (uint16_t)(58); + _curvea0[81] = _12172; + uint16_t _12173 = (uint16_t)(59); + _curvea0[82] = _12173; + uint16_t _12174 = (uint16_t)(59); + _curvea0[83] = _12174; + uint16_t _12175 = (uint16_t)(60); + _curvea0[84] = _12175; + uint16_t _12176 = (uint16_t)(60); + _curvea0[85] = _12176; + uint16_t _12177 = (uint16_t)(61); + _curvea0[86] = _12177; + uint16_t _12178 = (uint16_t)(61); + _curvea0[87] = _12178; + uint16_t _12179 = (uint16_t)(62); + _curvea0[88] = _12179; + uint16_t _12180 = (uint16_t)(62); + _curvea0[89] = _12180; + uint16_t _12181 = (uint16_t)(63); + _curvea0[90] = _12181; + uint16_t _12182 = (uint16_t)(63); + _curvea0[91] = _12182; + uint16_t _12183 = (uint16_t)(64); + _curvea0[92] = _12183; + uint16_t _12184 = (uint16_t)(64); + _curvea0[93] = _12184; + uint16_t _12185 = (uint16_t)(64); + _curvea0[94] = _12185; + uint16_t _12186 = (uint16_t)(65); + _curvea0[95] = _12186; + uint16_t _12187 = (uint16_t)(65); + _curvea0[96] = _12187; + uint16_t _12188 = (uint16_t)(66); + _curvea0[97] = _12188; + uint16_t _12189 = (uint16_t)(66); + _curvea0[98] = _12189; + uint16_t _12190 = (uint16_t)(67); + _curvea0[99] = _12190; + uint16_t _12191 = (uint16_t)(67); + _curvea0[100] = _12191; + uint16_t _12192 = (uint16_t)(68); + _curvea0[101] = _12192; + uint16_t _12193 = (uint16_t)(68); + _curvea0[102] = _12193; + uint16_t _12194 = (uint16_t)(68); + _curvea0[103] = _12194; + uint16_t _12195 = (uint16_t)(69); + _curvea0[104] = _12195; + uint16_t _12196 = (uint16_t)(69); + _curvea0[105] = _12196; + uint16_t _12197 = (uint16_t)(70); + _curvea0[106] = _12197; + uint16_t _12198 = (uint16_t)(70); + _curvea0[107] = _12198; + uint16_t _12199 = (uint16_t)(71); + _curvea0[108] = _12199; + uint16_t _12200 = (uint16_t)(71); + _curvea0[109] = _12200; + uint16_t _12201 = (uint16_t)(71); + _curvea0[110] = _12201; + uint16_t _12202 = (uint16_t)(72); + _curvea0[111] = _12202; + uint16_t _12203 = (uint16_t)(72); + _curvea0[112] = _12203; + uint16_t _12204 = (uint16_t)(73); + _curvea0[113] = _12204; + uint16_t _12205 = (uint16_t)(73); + _curvea0[114] = _12205; + uint16_t _12206 = (uint16_t)(74); + _curvea0[115] = _12206; + uint16_t _12207 = (uint16_t)(74); + _curvea0[116] = _12207; + uint16_t _12208 = (uint16_t)(74); + _curvea0[117] = _12208; + uint16_t _12209 = (uint16_t)(75); + _curvea0[118] = _12209; + uint16_t _12210 = (uint16_t)(75); + _curvea0[119] = _12210; + uint16_t _12211 = (uint16_t)(76); + _curvea0[120] = _12211; + uint16_t _12212 = (uint16_t)(76); + _curvea0[121] = _12212; + uint16_t _12213 = (uint16_t)(77); + _curvea0[122] = _12213; + uint16_t _12214 = (uint16_t)(77); + _curvea0[123] = _12214; + uint16_t _12215 = (uint16_t)(77); + _curvea0[124] = _12215; + uint16_t _12216 = (uint16_t)(78); + _curvea0[125] = _12216; + uint16_t _12217 = (uint16_t)(78); + _curvea0[126] = _12217; + uint16_t _12218 = (uint16_t)(79); + _curvea0[127] = _12218; + uint16_t _12219 = (uint16_t)(79); + _curvea0[128] = _12219; + uint16_t _12220 = (uint16_t)(79); + _curvea0[129] = _12220; + uint16_t _12221 = (uint16_t)(80); + _curvea0[130] = _12221; + uint16_t _12222 = (uint16_t)(80); + _curvea0[131] = _12222; + uint16_t _12223 = (uint16_t)(81); + _curvea0[132] = _12223; + uint16_t _12224 = (uint16_t)(81); + _curvea0[133] = _12224; + uint16_t _12225 = (uint16_t)(82); + _curvea0[134] = _12225; + uint16_t _12226 = (uint16_t)(82); + _curvea0[135] = _12226; + uint16_t _12227 = (uint16_t)(82); + _curvea0[136] = _12227; + uint16_t _12228 = (uint16_t)(83); + _curvea0[137] = _12228; + uint16_t _12229 = (uint16_t)(83); + _curvea0[138] = _12229; + uint16_t _12230 = (uint16_t)(84); + _curvea0[139] = _12230; + uint16_t _12231 = (uint16_t)(84); + _curvea0[140] = _12231; + uint16_t _12232 = (uint16_t)(84); + _curvea0[141] = _12232; + uint16_t _12233 = (uint16_t)(85); + _curvea0[142] = _12233; + uint16_t _12234 = (uint16_t)(85); + _curvea0[143] = _12234; + uint16_t _12235 = (uint16_t)(86); + _curvea0[144] = _12235; + uint16_t _12236 = (uint16_t)(86); + _curvea0[145] = _12236; + uint16_t _12237 = (uint16_t)(86); + _curvea0[146] = _12237; + uint16_t _12238 = (uint16_t)(87); + _curvea0[147] = _12238; + uint16_t _12239 = (uint16_t)(87); + _curvea0[148] = _12239; + uint16_t _12240 = (uint16_t)(88); + _curvea0[149] = _12240; + uint16_t _12241 = (uint16_t)(88); + _curvea0[150] = _12241; + uint16_t _12242 = (uint16_t)(88); + _curvea0[151] = _12242; + uint16_t _12243 = (uint16_t)(89); + _curvea0[152] = _12243; + uint16_t _12244 = (uint16_t)(89); + _curvea0[153] = _12244; + uint16_t _12245 = (uint16_t)(90); + _curvea0[154] = _12245; + uint16_t _12246 = (uint16_t)(90); + _curvea0[155] = _12246; + uint16_t _12247 = (uint16_t)(90); + _curvea0[156] = _12247; + uint16_t _12248 = (uint16_t)(91); + _curvea0[157] = _12248; + uint16_t _12249 = (uint16_t)(91); + _curvea0[158] = _12249; + uint16_t _12250 = (uint16_t)(92); + _curvea0[159] = _12250; + uint16_t _12251 = (uint16_t)(92); + _curvea0[160] = _12251; + uint16_t _12252 = (uint16_t)(92); + _curvea0[161] = _12252; + uint16_t _12253 = (uint16_t)(93); + _curvea0[162] = _12253; + uint16_t _12254 = (uint16_t)(93); + _curvea0[163] = _12254; + uint16_t _12255 = (uint16_t)(93); + _curvea0[164] = _12255; + uint16_t _12256 = (uint16_t)(94); + _curvea0[165] = _12256; + uint16_t _12257 = (uint16_t)(94); + _curvea0[166] = _12257; + uint16_t _12258 = (uint16_t)(95); + _curvea0[167] = _12258; + uint16_t _12259 = (uint16_t)(95); + _curvea0[168] = _12259; + uint16_t _12260 = (uint16_t)(95); + _curvea0[169] = _12260; + uint16_t _12261 = (uint16_t)(96); + _curvea0[170] = _12261; + uint16_t _12262 = (uint16_t)(96); + _curvea0[171] = _12262; + uint16_t _12263 = (uint16_t)(97); + _curvea0[172] = _12263; + uint16_t _12264 = (uint16_t)(97); + _curvea0[173] = _12264; + uint16_t _12265 = (uint16_t)(97); + _curvea0[174] = _12265; + uint16_t _12266 = (uint16_t)(98); + _curvea0[175] = _12266; + uint16_t _12267 = (uint16_t)(98); + _curvea0[176] = _12267; + uint16_t _12268 = (uint16_t)(99); + _curvea0[177] = _12268; + uint16_t _12269 = (uint16_t)(99); + _curvea0[178] = _12269; + uint16_t _12270 = (uint16_t)(99); + _curvea0[179] = _12270; + uint16_t _12271 = (uint16_t)(100); + _curvea0[180] = _12271; + uint16_t _12272 = (uint16_t)(100); + _curvea0[181] = _12272; + uint16_t _12273 = (uint16_t)(100); + _curvea0[182] = _12273; + uint16_t _12274 = (uint16_t)(101); + _curvea0[183] = _12274; + uint16_t _12275 = (uint16_t)(101); + _curvea0[184] = _12275; + uint16_t _12276 = (uint16_t)(102); + _curvea0[185] = _12276; + uint16_t _12277 = (uint16_t)(102); + _curvea0[186] = _12277; + uint16_t _12278 = (uint16_t)(102); + _curvea0[187] = _12278; + uint16_t _12279 = (uint16_t)(103); + _curvea0[188] = _12279; + uint16_t _12280 = (uint16_t)(103); + _curvea0[189] = _12280; + uint16_t _12281 = (uint16_t)(103); + _curvea0[190] = _12281; + uint16_t _12282 = (uint16_t)(104); + _curvea0[191] = _12282; + uint16_t _12283 = (uint16_t)(104); + _curvea0[192] = _12283; + uint16_t _12284 = (uint16_t)(105); + _curvea0[193] = _12284; + uint16_t _12285 = (uint16_t)(105); + _curvea0[194] = _12285; + uint16_t _12286 = (uint16_t)(105); + _curvea0[195] = _12286; + uint16_t _12287 = (uint16_t)(106); + _curvea0[196] = _12287; + uint16_t _12288 = (uint16_t)(106); + _curvea0[197] = _12288; + uint16_t _12289 = (uint16_t)(106); + _curvea0[198] = _12289; + uint16_t _12290 = (uint16_t)(107); + _curvea0[199] = _12290; + uint16_t _12291 = (uint16_t)(107); + _curvea0[200] = _12291; + uint16_t _12292 = (uint16_t)(108); + _curvea0[201] = _12292; + uint16_t _12293 = (uint16_t)(108); + _curvea0[202] = _12293; + uint16_t _12294 = (uint16_t)(108); + _curvea0[203] = _12294; + uint16_t _12295 = (uint16_t)(109); + _curvea0[204] = _12295; + uint16_t _12296 = (uint16_t)(109); + _curvea0[205] = _12296; + uint16_t _12297 = (uint16_t)(109); + _curvea0[206] = _12297; + uint16_t _12298 = (uint16_t)(110); + _curvea0[207] = _12298; + uint16_t _12299 = (uint16_t)(110); + _curvea0[208] = _12299; + uint16_t _12300 = (uint16_t)(111); + _curvea0[209] = _12300; + uint16_t _12301 = (uint16_t)(111); + _curvea0[210] = _12301; + uint16_t _12302 = (uint16_t)(111); + _curvea0[211] = _12302; + uint16_t _12303 = (uint16_t)(112); + _curvea0[212] = _12303; + uint16_t _12304 = (uint16_t)(112); + _curvea0[213] = _12304; + uint16_t _12305 = (uint16_t)(112); + _curvea0[214] = _12305; + uint16_t _12306 = (uint16_t)(113); + _curvea0[215] = _12306; + uint16_t _12307 = (uint16_t)(113); + _curvea0[216] = _12307; + uint16_t _12308 = (uint16_t)(113); + _curvea0[217] = _12308; + uint16_t _12309 = (uint16_t)(114); + _curvea0[218] = _12309; + uint16_t _12310 = (uint16_t)(114); + _curvea0[219] = _12310; + uint16_t _12311 = (uint16_t)(115); + _curvea0[220] = _12311; + uint16_t _12312 = (uint16_t)(115); + _curvea0[221] = _12312; + uint16_t _12313 = (uint16_t)(115); + _curvea0[222] = _12313; + uint16_t _12314 = (uint16_t)(116); + _curvea0[223] = _12314; + uint16_t _12315 = (uint16_t)(116); + _curvea0[224] = _12315; + uint16_t _12316 = (uint16_t)(116); + _curvea0[225] = _12316; + uint16_t _12317 = (uint16_t)(117); + _curvea0[226] = _12317; + uint16_t _12318 = (uint16_t)(117); + _curvea0[227] = _12318; + uint16_t _12319 = (uint16_t)(117); + _curvea0[228] = _12319; + uint16_t _12320 = (uint16_t)(118); + _curvea0[229] = _12320; + uint16_t _12321 = (uint16_t)(118); + _curvea0[230] = _12321; + uint16_t _12322 = (uint16_t)(119); + _curvea0[231] = _12322; + uint16_t _12323 = (uint16_t)(119); + _curvea0[232] = _12323; + uint16_t _12324 = (uint16_t)(119); + _curvea0[233] = _12324; + uint16_t _12325 = (uint16_t)(120); + _curvea0[234] = _12325; + uint16_t _12326 = (uint16_t)(120); + _curvea0[235] = _12326; + uint16_t _12327 = (uint16_t)(120); + _curvea0[236] = _12327; + uint16_t _12328 = (uint16_t)(121); + _curvea0[237] = _12328; + uint16_t _12329 = (uint16_t)(121); + _curvea0[238] = _12329; + uint16_t _12330 = (uint16_t)(121); + _curvea0[239] = _12330; + uint16_t _12331 = (uint16_t)(122); + _curvea0[240] = _12331; + uint16_t _12332 = (uint16_t)(122); + _curvea0[241] = _12332; + uint16_t _12333 = (uint16_t)(123); + _curvea0[242] = _12333; + uint16_t _12334 = (uint16_t)(123); + _curvea0[243] = _12334; + uint16_t _12335 = (uint16_t)(123); + _curvea0[244] = _12335; + uint16_t _12336 = (uint16_t)(124); + _curvea0[245] = _12336; + uint16_t _12337 = (uint16_t)(124); + _curvea0[246] = _12337; + uint16_t _12338 = (uint16_t)(124); + _curvea0[247] = _12338; + uint16_t _12339 = (uint16_t)(125); + _curvea0[248] = _12339; + uint16_t _12340 = (uint16_t)(125); + _curvea0[249] = _12340; + uint16_t _12341 = (uint16_t)(125); + _curvea0[250] = _12341; + uint16_t _12342 = (uint16_t)(126); + _curvea0[251] = _12342; + uint16_t _12343 = (uint16_t)(126); + _curvea0[252] = _12343; + uint16_t _12344 = (uint16_t)(126); + _curvea0[253] = _12344; + uint16_t _12345 = (uint16_t)(127); + _curvea0[254] = _12345; + uint16_t _12346 = (uint16_t)(127); + _curvea0[255] = _12346; + uint16_t _12347 = (uint16_t)(128); + _curvea0[256] = _12347; + uint16_t _12348 = (uint16_t)(128); + _curvea0[257] = _12348; + uint16_t _12349 = (uint16_t)(128); + _curvea0[258] = _12349; + uint16_t _12350 = (uint16_t)(129); + _curvea0[259] = _12350; + uint16_t _12351 = (uint16_t)(129); + _curvea0[260] = _12351; + uint16_t _12352 = (uint16_t)(129); + _curvea0[261] = _12352; + uint16_t _12353 = (uint16_t)(130); + _curvea0[262] = _12353; + uint16_t _12354 = (uint16_t)(130); + _curvea0[263] = _12354; + uint16_t _12355 = (uint16_t)(130); + _curvea0[264] = _12355; + uint16_t _12356 = (uint16_t)(131); + _curvea0[265] = _12356; + uint16_t _12357 = (uint16_t)(131); + _curvea0[266] = _12357; + uint16_t _12358 = (uint16_t)(131); + _curvea0[267] = _12358; + uint16_t _12359 = (uint16_t)(132); + _curvea0[268] = _12359; + uint16_t _12360 = (uint16_t)(132); + _curvea0[269] = _12360; + uint16_t _12361 = (uint16_t)(132); + _curvea0[270] = _12361; + uint16_t _12362 = (uint16_t)(133); + _curvea0[271] = _12362; + uint16_t _12363 = (uint16_t)(133); + _curvea0[272] = _12363; + uint16_t _12364 = (uint16_t)(133); + _curvea0[273] = _12364; + uint16_t _12365 = (uint16_t)(134); + _curvea0[274] = _12365; + uint16_t _12366 = (uint16_t)(134); + _curvea0[275] = _12366; + uint16_t _12367 = (uint16_t)(134); + _curvea0[276] = _12367; + uint16_t _12368 = (uint16_t)(135); + _curvea0[277] = _12368; + uint16_t _12369 = (uint16_t)(135); + _curvea0[278] = _12369; + uint16_t _12370 = (uint16_t)(135); + _curvea0[279] = _12370; + uint16_t _12371 = (uint16_t)(136); + _curvea0[280] = _12371; + uint16_t _12372 = (uint16_t)(136); + _curvea0[281] = _12372; + uint16_t _12373 = (uint16_t)(136); + _curvea0[282] = _12373; + uint16_t _12374 = (uint16_t)(137); + _curvea0[283] = _12374; + uint16_t _12375 = (uint16_t)(137); + _curvea0[284] = _12375; + uint16_t _12376 = (uint16_t)(137); + _curvea0[285] = _12376; + uint16_t _12377 = (uint16_t)(138); + _curvea0[286] = _12377; + uint16_t _12378 = (uint16_t)(138); + _curvea0[287] = _12378; + uint16_t _12379 = (uint16_t)(138); + _curvea0[288] = _12379; + uint16_t _12380 = (uint16_t)(139); + _curvea0[289] = _12380; + uint16_t _12381 = (uint16_t)(139); + _curvea0[290] = _12381; + uint16_t _12382 = (uint16_t)(139); + _curvea0[291] = _12382; + uint16_t _12383 = (uint16_t)(140); + _curvea0[292] = _12383; + uint16_t _12384 = (uint16_t)(140); + _curvea0[293] = _12384; + uint16_t _12385 = (uint16_t)(140); + _curvea0[294] = _12385; + uint16_t _12386 = (uint16_t)(141); + _curvea0[295] = _12386; + uint16_t _12387 = (uint16_t)(141); + _curvea0[296] = _12387; + uint16_t _12388 = (uint16_t)(141); + _curvea0[297] = _12388; + uint16_t _12389 = (uint16_t)(141); + _curvea0[298] = _12389; + uint16_t _12390 = (uint16_t)(142); + _curvea0[299] = _12390; + uint16_t _12391 = (uint16_t)(142); + _curvea0[300] = _12391; + uint16_t _12392 = (uint16_t)(142); + _curvea0[301] = _12392; + uint16_t _12393 = (uint16_t)(143); + _curvea0[302] = _12393; + uint16_t _12394 = (uint16_t)(143); + _curvea0[303] = _12394; + uint16_t _12395 = (uint16_t)(143); + _curvea0[304] = _12395; + uint16_t _12396 = (uint16_t)(144); + _curvea0[305] = _12396; + uint16_t _12397 = (uint16_t)(144); + _curvea0[306] = _12397; + uint16_t _12398 = (uint16_t)(144); + _curvea0[307] = _12398; + uint16_t _12399 = (uint16_t)(145); + _curvea0[308] = _12399; + uint16_t _12400 = (uint16_t)(145); + _curvea0[309] = _12400; + uint16_t _12401 = (uint16_t)(145); + _curvea0[310] = _12401; + uint16_t _12402 = (uint16_t)(145); + _curvea0[311] = _12402; + uint16_t _12403 = (uint16_t)(146); + _curvea0[312] = _12403; + uint16_t _12404 = (uint16_t)(146); + _curvea0[313] = _12404; + uint16_t _12405 = (uint16_t)(146); + _curvea0[314] = _12405; + uint16_t _12406 = (uint16_t)(147); + _curvea0[315] = _12406; + uint16_t _12407 = (uint16_t)(147); + _curvea0[316] = _12407; + uint16_t _12408 = (uint16_t)(147); + _curvea0[317] = _12408; + uint16_t _12409 = (uint16_t)(148); + _curvea0[318] = _12409; + uint16_t _12410 = (uint16_t)(148); + _curvea0[319] = _12410; + uint16_t _12411 = (uint16_t)(148); + _curvea0[320] = _12411; + uint16_t _12412 = (uint16_t)(148); + _curvea0[321] = _12412; + uint16_t _12413 = (uint16_t)(149); + _curvea0[322] = _12413; + uint16_t _12414 = (uint16_t)(149); + _curvea0[323] = _12414; + uint16_t _12415 = (uint16_t)(149); + _curvea0[324] = _12415; + uint16_t _12416 = (uint16_t)(150); + _curvea0[325] = _12416; + uint16_t _12417 = (uint16_t)(150); + _curvea0[326] = _12417; + uint16_t _12418 = (uint16_t)(150); + _curvea0[327] = _12418; + uint16_t _12419 = (uint16_t)(150); + _curvea0[328] = _12419; + uint16_t _12420 = (uint16_t)(151); + _curvea0[329] = _12420; + uint16_t _12421 = (uint16_t)(151); + _curvea0[330] = _12421; + uint16_t _12422 = (uint16_t)(151); + _curvea0[331] = _12422; + uint16_t _12423 = (uint16_t)(152); + _curvea0[332] = _12423; + uint16_t _12424 = (uint16_t)(152); + _curvea0[333] = _12424; + uint16_t _12425 = (uint16_t)(152); + _curvea0[334] = _12425; + uint16_t _12426 = (uint16_t)(152); + _curvea0[335] = _12426; + uint16_t _12427 = (uint16_t)(153); + _curvea0[336] = _12427; + uint16_t _12428 = (uint16_t)(153); + _curvea0[337] = _12428; + uint16_t _12429 = (uint16_t)(153); + _curvea0[338] = _12429; + uint16_t _12430 = (uint16_t)(154); + _curvea0[339] = _12430; + uint16_t _12431 = (uint16_t)(154); + _curvea0[340] = _12431; + uint16_t _12432 = (uint16_t)(154); + _curvea0[341] = _12432; + uint16_t _12433 = (uint16_t)(154); + _curvea0[342] = _12433; + uint16_t _12434 = (uint16_t)(155); + _curvea0[343] = _12434; + uint16_t _12435 = (uint16_t)(155); + _curvea0[344] = _12435; + uint16_t _12436 = (uint16_t)(155); + _curvea0[345] = _12436; + uint16_t _12437 = (uint16_t)(156); + _curvea0[346] = _12437; + uint16_t _12438 = (uint16_t)(156); + _curvea0[347] = _12438; + uint16_t _12439 = (uint16_t)(156); + _curvea0[348] = _12439; + uint16_t _12440 = (uint16_t)(156); + _curvea0[349] = _12440; + uint16_t _12441 = (uint16_t)(157); + _curvea0[350] = _12441; + uint16_t _12442 = (uint16_t)(157); + _curvea0[351] = _12442; + uint16_t _12443 = (uint16_t)(157); + _curvea0[352] = _12443; + uint16_t _12444 = (uint16_t)(157); + _curvea0[353] = _12444; + uint16_t _12445 = (uint16_t)(158); + _curvea0[354] = _12445; + uint16_t _12446 = (uint16_t)(158); + _curvea0[355] = _12446; + uint16_t _12447 = (uint16_t)(158); + _curvea0[356] = _12447; + uint16_t _12448 = (uint16_t)(159); + _curvea0[357] = _12448; + uint16_t _12449 = (uint16_t)(159); + _curvea0[358] = _12449; + uint16_t _12450 = (uint16_t)(159); + _curvea0[359] = _12450; + uint16_t _12451 = (uint16_t)(159); + _curvea0[360] = _12451; + uint16_t _12452 = (uint16_t)(160); + _curvea0[361] = _12452; + uint16_t _12453 = (uint16_t)(160); + _curvea0[362] = _12453; + uint16_t _12454 = (uint16_t)(160); + _curvea0[363] = _12454; + uint16_t _12455 = (uint16_t)(160); + _curvea0[364] = _12455; + uint16_t _12456 = (uint16_t)(161); + _curvea0[365] = _12456; + uint16_t _12457 = (uint16_t)(161); + _curvea0[366] = _12457; + uint16_t _12458 = (uint16_t)(161); + _curvea0[367] = _12458; + uint16_t _12459 = (uint16_t)(161); + _curvea0[368] = _12459; + uint16_t _12460 = (uint16_t)(162); + _curvea0[369] = _12460; + uint16_t _12461 = (uint16_t)(162); + _curvea0[370] = _12461; + uint16_t _12462 = (uint16_t)(162); + _curvea0[371] = _12462; + uint16_t _12463 = (uint16_t)(162); + _curvea0[372] = _12463; + uint16_t _12464 = (uint16_t)(163); + _curvea0[373] = _12464; + uint16_t _12465 = (uint16_t)(163); + _curvea0[374] = _12465; + uint16_t _12466 = (uint16_t)(163); + _curvea0[375] = _12466; + uint16_t _12467 = (uint16_t)(163); + _curvea0[376] = _12467; + uint16_t _12468 = (uint16_t)(164); + _curvea0[377] = _12468; + uint16_t _12469 = (uint16_t)(164); + _curvea0[378] = _12469; + uint16_t _12470 = (uint16_t)(164); + _curvea0[379] = _12470; + uint16_t _12471 = (uint16_t)(164); + _curvea0[380] = _12471; + uint16_t _12472 = (uint16_t)(165); + _curvea0[381] = _12472; + uint16_t _12473 = (uint16_t)(165); + _curvea0[382] = _12473; + uint16_t _12474 = (uint16_t)(165); + _curvea0[383] = _12474; + uint16_t _12475 = (uint16_t)(166); + _curvea0[384] = _12475; + uint16_t _12476 = (uint16_t)(166); + _curvea0[385] = _12476; + uint16_t _12477 = (uint16_t)(166); + _curvea0[386] = _12477; + uint16_t _12478 = (uint16_t)(166); + _curvea0[387] = _12478; + uint16_t _12479 = (uint16_t)(167); + _curvea0[388] = _12479; + uint16_t _12480 = (uint16_t)(167); + _curvea0[389] = _12480; + uint16_t _12481 = (uint16_t)(167); + _curvea0[390] = _12481; + uint16_t _12482 = (uint16_t)(167); + _curvea0[391] = _12482; + uint16_t _12483 = (uint16_t)(167); + _curvea0[392] = _12483; + uint16_t _12484 = (uint16_t)(168); + _curvea0[393] = _12484; + uint16_t _12485 = (uint16_t)(168); + _curvea0[394] = _12485; + uint16_t _12486 = (uint16_t)(168); + _curvea0[395] = _12486; + uint16_t _12487 = (uint16_t)(168); + _curvea0[396] = _12487; + uint16_t _12488 = (uint16_t)(169); + _curvea0[397] = _12488; + uint16_t _12489 = (uint16_t)(169); + _curvea0[398] = _12489; + uint16_t _12490 = (uint16_t)(169); + _curvea0[399] = _12490; + uint16_t _12491 = (uint16_t)(169); + _curvea0[400] = _12491; + uint16_t _12492 = (uint16_t)(170); + _curvea0[401] = _12492; + uint16_t _12493 = (uint16_t)(170); + _curvea0[402] = _12493; + uint16_t _12494 = (uint16_t)(170); + _curvea0[403] = _12494; + uint16_t _12495 = (uint16_t)(170); + _curvea0[404] = _12495; + uint16_t _12496 = (uint16_t)(171); + _curvea0[405] = _12496; + uint16_t _12497 = (uint16_t)(171); + _curvea0[406] = _12497; + uint16_t _12498 = (uint16_t)(171); + _curvea0[407] = _12498; + uint16_t _12499 = (uint16_t)(171); + _curvea0[408] = _12499; + uint16_t _12500 = (uint16_t)(172); + _curvea0[409] = _12500; + uint16_t _12501 = (uint16_t)(172); + _curvea0[410] = _12501; + uint16_t _12502 = (uint16_t)(172); + _curvea0[411] = _12502; + uint16_t _12503 = (uint16_t)(172); + _curvea0[412] = _12503; + uint16_t _12504 = (uint16_t)(173); + _curvea0[413] = _12504; + uint16_t _12505 = (uint16_t)(173); + _curvea0[414] = _12505; + uint16_t _12506 = (uint16_t)(173); + _curvea0[415] = _12506; + uint16_t _12507 = (uint16_t)(173); + _curvea0[416] = _12507; + uint16_t _12508 = (uint16_t)(173); + _curvea0[417] = _12508; + uint16_t _12509 = (uint16_t)(174); + _curvea0[418] = _12509; + uint16_t _12510 = (uint16_t)(174); + _curvea0[419] = _12510; + uint16_t _12511 = (uint16_t)(174); + _curvea0[420] = _12511; + uint16_t _12512 = (uint16_t)(174); + _curvea0[421] = _12512; + uint16_t _12513 = (uint16_t)(175); + _curvea0[422] = _12513; + uint16_t _12514 = (uint16_t)(175); + _curvea0[423] = _12514; + uint16_t _12515 = (uint16_t)(175); + _curvea0[424] = _12515; + uint16_t _12516 = (uint16_t)(175); + _curvea0[425] = _12516; + uint16_t _12517 = (uint16_t)(176); + _curvea0[426] = _12517; + uint16_t _12518 = (uint16_t)(176); + _curvea0[427] = _12518; + uint16_t _12519 = (uint16_t)(176); + _curvea0[428] = _12519; + uint16_t _12520 = (uint16_t)(176); + _curvea0[429] = _12520; + uint16_t _12521 = (uint16_t)(176); + _curvea0[430] = _12521; + uint16_t _12522 = (uint16_t)(177); + _curvea0[431] = _12522; + uint16_t _12523 = (uint16_t)(177); + _curvea0[432] = _12523; + uint16_t _12524 = (uint16_t)(177); + _curvea0[433] = _12524; + uint16_t _12525 = (uint16_t)(177); + _curvea0[434] = _12525; + uint16_t _12526 = (uint16_t)(178); + _curvea0[435] = _12526; + uint16_t _12527 = (uint16_t)(178); + _curvea0[436] = _12527; + uint16_t _12528 = (uint16_t)(178); + _curvea0[437] = _12528; + uint16_t _12529 = (uint16_t)(178); + _curvea0[438] = _12529; + uint16_t _12530 = (uint16_t)(178); + _curvea0[439] = _12530; + uint16_t _12531 = (uint16_t)(179); + _curvea0[440] = _12531; + uint16_t _12532 = (uint16_t)(179); + _curvea0[441] = _12532; + uint16_t _12533 = (uint16_t)(179); + _curvea0[442] = _12533; + uint16_t _12534 = (uint16_t)(179); + _curvea0[443] = _12534; + uint16_t _12535 = (uint16_t)(180); + _curvea0[444] = _12535; + uint16_t _12536 = (uint16_t)(180); + _curvea0[445] = _12536; + uint16_t _12537 = (uint16_t)(180); + _curvea0[446] = _12537; + uint16_t _12538 = (uint16_t)(180); + _curvea0[447] = _12538; + uint16_t _12539 = (uint16_t)(180); + _curvea0[448] = _12539; + uint16_t _12540 = (uint16_t)(181); + _curvea0[449] = _12540; + uint16_t _12541 = (uint16_t)(181); + _curvea0[450] = _12541; + uint16_t _12542 = (uint16_t)(181); + _curvea0[451] = _12542; + uint16_t _12543 = (uint16_t)(181); + _curvea0[452] = _12543; + uint16_t _12544 = (uint16_t)(181); + _curvea0[453] = _12544; + uint16_t _12545 = (uint16_t)(182); + _curvea0[454] = _12545; + uint16_t _12546 = (uint16_t)(182); + _curvea0[455] = _12546; + uint16_t _12547 = (uint16_t)(182); + _curvea0[456] = _12547; + uint16_t _12548 = (uint16_t)(182); + _curvea0[457] = _12548; + uint16_t _12549 = (uint16_t)(183); + _curvea0[458] = _12549; + uint16_t _12550 = (uint16_t)(183); + _curvea0[459] = _12550; + uint16_t _12551 = (uint16_t)(183); + _curvea0[460] = _12551; + uint16_t _12552 = (uint16_t)(183); + _curvea0[461] = _12552; + uint16_t _12553 = (uint16_t)(183); + _curvea0[462] = _12553; + uint16_t _12554 = (uint16_t)(184); + _curvea0[463] = _12554; + uint16_t _12555 = (uint16_t)(184); + _curvea0[464] = _12555; + uint16_t _12556 = (uint16_t)(184); + _curvea0[465] = _12556; + uint16_t _12557 = (uint16_t)(184); + _curvea0[466] = _12557; + uint16_t _12558 = (uint16_t)(184); + _curvea0[467] = _12558; + uint16_t _12559 = (uint16_t)(185); + _curvea0[468] = _12559; + uint16_t _12560 = (uint16_t)(185); + _curvea0[469] = _12560; + uint16_t _12561 = (uint16_t)(185); + _curvea0[470] = _12561; + uint16_t _12562 = (uint16_t)(185); + _curvea0[471] = _12562; + uint16_t _12563 = (uint16_t)(185); + _curvea0[472] = _12563; + uint16_t _12564 = (uint16_t)(186); + _curvea0[473] = _12564; + uint16_t _12565 = (uint16_t)(186); + _curvea0[474] = _12565; + uint16_t _12566 = (uint16_t)(186); + _curvea0[475] = _12566; + uint16_t _12567 = (uint16_t)(186); + _curvea0[476] = _12567; + uint16_t _12568 = (uint16_t)(187); + _curvea0[477] = _12568; + uint16_t _12569 = (uint16_t)(187); + _curvea0[478] = _12569; + uint16_t _12570 = (uint16_t)(187); + _curvea0[479] = _12570; + uint16_t _12571 = (uint16_t)(187); + _curvea0[480] = _12571; + uint16_t _12572 = (uint16_t)(187); + _curvea0[481] = _12572; + uint16_t _12573 = (uint16_t)(188); + _curvea0[482] = _12573; + uint16_t _12574 = (uint16_t)(188); + _curvea0[483] = _12574; + uint16_t _12575 = (uint16_t)(188); + _curvea0[484] = _12575; + uint16_t _12576 = (uint16_t)(188); + _curvea0[485] = _12576; + uint16_t _12577 = (uint16_t)(188); + _curvea0[486] = _12577; + uint16_t _12578 = (uint16_t)(189); + _curvea0[487] = _12578; + uint16_t _12579 = (uint16_t)(189); + _curvea0[488] = _12579; + uint16_t _12580 = (uint16_t)(189); + _curvea0[489] = _12580; + uint16_t _12581 = (uint16_t)(189); + _curvea0[490] = _12581; + uint16_t _12582 = (uint16_t)(189); + _curvea0[491] = _12582; + uint16_t _12583 = (uint16_t)(190); + _curvea0[492] = _12583; + uint16_t _12584 = (uint16_t)(190); + _curvea0[493] = _12584; + uint16_t _12585 = (uint16_t)(190); + _curvea0[494] = _12585; + uint16_t _12586 = (uint16_t)(190); + _curvea0[495] = _12586; + uint16_t _12587 = (uint16_t)(190); + _curvea0[496] = _12587; + uint16_t _12588 = (uint16_t)(190); + _curvea0[497] = _12588; + uint16_t _12589 = (uint16_t)(191); + _curvea0[498] = _12589; + uint16_t _12590 = (uint16_t)(191); + _curvea0[499] = _12590; + uint16_t _12591 = (uint16_t)(191); + _curvea0[500] = _12591; + uint16_t _12592 = (uint16_t)(191); + _curvea0[501] = _12592; + uint16_t _12593 = (uint16_t)(191); + _curvea0[502] = _12593; + uint16_t _12594 = (uint16_t)(192); + _curvea0[503] = _12594; + uint16_t _12595 = (uint16_t)(192); + _curvea0[504] = _12595; + uint16_t _12596 = (uint16_t)(192); + _curvea0[505] = _12596; + uint16_t _12597 = (uint16_t)(192); + _curvea0[506] = _12597; + uint16_t _12598 = (uint16_t)(192); + _curvea0[507] = _12598; + uint16_t _12599 = (uint16_t)(193); + _curvea0[508] = _12599; + uint16_t _12600 = (uint16_t)(193); + _curvea0[509] = _12600; + uint16_t _12601 = (uint16_t)(193); + _curvea0[510] = _12601; + uint16_t _12602 = (uint16_t)(193); + _curvea0[511] = _12602; + uint16_t _12603 = (uint16_t)(193); + _curvea0[512] = _12603; + uint16_t _12604 = (uint16_t)(194); + _curvea0[513] = _12604; + uint16_t _12605 = (uint16_t)(194); + _curvea0[514] = _12605; + uint16_t _12606 = (uint16_t)(194); + _curvea0[515] = _12606; + uint16_t _12607 = (uint16_t)(194); + _curvea0[516] = _12607; + uint16_t _12608 = (uint16_t)(194); + _curvea0[517] = _12608; + uint16_t _12609 = (uint16_t)(195); + _curvea0[518] = _12609; + uint16_t _12610 = (uint16_t)(195); + _curvea0[519] = _12610; + uint16_t _12611 = (uint16_t)(195); + _curvea0[520] = _12611; + uint16_t _12612 = (uint16_t)(195); + _curvea0[521] = _12612; + uint16_t _12613 = (uint16_t)(195); + _curvea0[522] = _12613; + uint16_t _12614 = (uint16_t)(195); + _curvea0[523] = _12614; + uint16_t _12615 = (uint16_t)(196); + _curvea0[524] = _12615; + uint16_t _12616 = (uint16_t)(196); + _curvea0[525] = _12616; + uint16_t _12617 = (uint16_t)(196); + _curvea0[526] = _12617; + uint16_t _12618 = (uint16_t)(196); + _curvea0[527] = _12618; + uint16_t _12619 = (uint16_t)(196); + _curvea0[528] = _12619; + uint16_t _12620 = (uint16_t)(197); + _curvea0[529] = _12620; + uint16_t _12621 = (uint16_t)(197); + _curvea0[530] = _12621; + uint16_t _12622 = (uint16_t)(197); + _curvea0[531] = _12622; + uint16_t _12623 = (uint16_t)(197); + _curvea0[532] = _12623; + uint16_t _12624 = (uint16_t)(197); + _curvea0[533] = _12624; + uint16_t _12625 = (uint16_t)(197); + _curvea0[534] = _12625; + uint16_t _12626 = (uint16_t)(198); + _curvea0[535] = _12626; + uint16_t _12627 = (uint16_t)(198); + _curvea0[536] = _12627; + uint16_t _12628 = (uint16_t)(198); + _curvea0[537] = _12628; + uint16_t _12629 = (uint16_t)(198); + _curvea0[538] = _12629; + uint16_t _12630 = (uint16_t)(198); + _curvea0[539] = _12630; + uint16_t _12631 = (uint16_t)(199); + _curvea0[540] = _12631; + uint16_t _12632 = (uint16_t)(199); + _curvea0[541] = _12632; + uint16_t _12633 = (uint16_t)(199); + _curvea0[542] = _12633; + uint16_t _12634 = (uint16_t)(199); + _curvea0[543] = _12634; + uint16_t _12635 = (uint16_t)(199); + _curvea0[544] = _12635; + uint16_t _12636 = (uint16_t)(199); + _curvea0[545] = _12636; + uint16_t _12637 = (uint16_t)(200); + _curvea0[546] = _12637; + uint16_t _12638 = (uint16_t)(200); + _curvea0[547] = _12638; + uint16_t _12639 = (uint16_t)(200); + _curvea0[548] = _12639; + uint16_t _12640 = (uint16_t)(200); + _curvea0[549] = _12640; + uint16_t _12641 = (uint16_t)(200); + _curvea0[550] = _12641; + uint16_t _12642 = (uint16_t)(200); + _curvea0[551] = _12642; + uint16_t _12643 = (uint16_t)(201); + _curvea0[552] = _12643; + uint16_t _12644 = (uint16_t)(201); + _curvea0[553] = _12644; + uint16_t _12645 = (uint16_t)(201); + _curvea0[554] = _12645; + uint16_t _12646 = (uint16_t)(201); + _curvea0[555] = _12646; + uint16_t _12647 = (uint16_t)(201); + _curvea0[556] = _12647; + uint16_t _12648 = (uint16_t)(202); + _curvea0[557] = _12648; + uint16_t _12649 = (uint16_t)(202); + _curvea0[558] = _12649; + uint16_t _12650 = (uint16_t)(202); + _curvea0[559] = _12650; + uint16_t _12651 = (uint16_t)(202); + _curvea0[560] = _12651; + uint16_t _12652 = (uint16_t)(202); + _curvea0[561] = _12652; + uint16_t _12653 = (uint16_t)(202); + _curvea0[562] = _12653; + uint16_t _12654 = (uint16_t)(203); + _curvea0[563] = _12654; + uint16_t _12655 = (uint16_t)(203); + _curvea0[564] = _12655; + uint16_t _12656 = (uint16_t)(203); + _curvea0[565] = _12656; + uint16_t _12657 = (uint16_t)(203); + _curvea0[566] = _12657; + uint16_t _12658 = (uint16_t)(203); + _curvea0[567] = _12658; + uint16_t _12659 = (uint16_t)(203); + _curvea0[568] = _12659; + uint16_t _12660 = (uint16_t)(204); + _curvea0[569] = _12660; + uint16_t _12661 = (uint16_t)(204); + _curvea0[570] = _12661; + uint16_t _12662 = (uint16_t)(204); + _curvea0[571] = _12662; + uint16_t _12663 = (uint16_t)(204); + _curvea0[572] = _12663; + uint16_t _12664 = (uint16_t)(204); + _curvea0[573] = _12664; + uint16_t _12665 = (uint16_t)(204); + _curvea0[574] = _12665; + uint16_t _12666 = (uint16_t)(205); + _curvea0[575] = _12666; + uint16_t _12667 = (uint16_t)(205); + _curvea0[576] = _12667; + uint16_t _12668 = (uint16_t)(205); + _curvea0[577] = _12668; + uint16_t _12669 = (uint16_t)(205); + _curvea0[578] = _12669; + uint16_t _12670 = (uint16_t)(205); + _curvea0[579] = _12670; + uint16_t _12671 = (uint16_t)(205); + _curvea0[580] = _12671; + uint16_t _12672 = (uint16_t)(206); + _curvea0[581] = _12672; + uint16_t _12673 = (uint16_t)(206); + _curvea0[582] = _12673; + uint16_t _12674 = (uint16_t)(206); + _curvea0[583] = _12674; + uint16_t _12675 = (uint16_t)(206); + _curvea0[584] = _12675; + uint16_t _12676 = (uint16_t)(206); + _curvea0[585] = _12676; + uint16_t _12677 = (uint16_t)(206); + _curvea0[586] = _12677; + uint16_t _12678 = (uint16_t)(207); + _curvea0[587] = _12678; + uint16_t _12679 = (uint16_t)(207); + _curvea0[588] = _12679; + uint16_t _12680 = (uint16_t)(207); + _curvea0[589] = _12680; + uint16_t _12681 = (uint16_t)(207); + _curvea0[590] = _12681; + uint16_t _12682 = (uint16_t)(207); + _curvea0[591] = _12682; + uint16_t _12683 = (uint16_t)(207); + _curvea0[592] = _12683; + uint16_t _12684 = (uint16_t)(208); + _curvea0[593] = _12684; + uint16_t _12685 = (uint16_t)(208); + _curvea0[594] = _12685; + uint16_t _12686 = (uint16_t)(208); + _curvea0[595] = _12686; + uint16_t _12687 = (uint16_t)(208); + _curvea0[596] = _12687; + uint16_t _12688 = (uint16_t)(208); + _curvea0[597] = _12688; + uint16_t _12689 = (uint16_t)(208); + _curvea0[598] = _12689; + uint16_t _12690 = (uint16_t)(209); + _curvea0[599] = _12690; + uint16_t _12691 = (uint16_t)(209); + _curvea0[600] = _12691; + uint16_t _12692 = (uint16_t)(209); + _curvea0[601] = _12692; + uint16_t _12693 = (uint16_t)(209); + _curvea0[602] = _12693; + uint16_t _12694 = (uint16_t)(209); + _curvea0[603] = _12694; + uint16_t _12695 = (uint16_t)(209); + _curvea0[604] = _12695; + uint16_t _12696 = (uint16_t)(209); + _curvea0[605] = _12696; + uint16_t _12697 = (uint16_t)(210); + _curvea0[606] = _12697; + uint16_t _12698 = (uint16_t)(210); + _curvea0[607] = _12698; + uint16_t _12699 = (uint16_t)(210); + _curvea0[608] = _12699; + uint16_t _12700 = (uint16_t)(210); + _curvea0[609] = _12700; + uint16_t _12701 = (uint16_t)(210); + _curvea0[610] = _12701; + uint16_t _12702 = (uint16_t)(210); + _curvea0[611] = _12702; + uint16_t _12703 = (uint16_t)(211); + _curvea0[612] = _12703; + uint16_t _12704 = (uint16_t)(211); + _curvea0[613] = _12704; + uint16_t _12705 = (uint16_t)(211); + _curvea0[614] = _12705; + uint16_t _12706 = (uint16_t)(211); + _curvea0[615] = _12706; + uint16_t _12707 = (uint16_t)(211); + _curvea0[616] = _12707; + uint16_t _12708 = (uint16_t)(211); + _curvea0[617] = _12708; + uint16_t _12709 = (uint16_t)(211); + _curvea0[618] = _12709; + uint16_t _12710 = (uint16_t)(212); + _curvea0[619] = _12710; + uint16_t _12711 = (uint16_t)(212); + _curvea0[620] = _12711; + uint16_t _12712 = (uint16_t)(212); + _curvea0[621] = _12712; + uint16_t _12713 = (uint16_t)(212); + _curvea0[622] = _12713; + uint16_t _12714 = (uint16_t)(212); + _curvea0[623] = _12714; + uint16_t _12715 = (uint16_t)(212); + _curvea0[624] = _12715; + uint16_t _12716 = (uint16_t)(213); + _curvea0[625] = _12716; + uint16_t _12717 = (uint16_t)(213); + _curvea0[626] = _12717; + uint16_t _12718 = (uint16_t)(213); + _curvea0[627] = _12718; + uint16_t _12719 = (uint16_t)(213); + _curvea0[628] = _12719; + uint16_t _12720 = (uint16_t)(213); + _curvea0[629] = _12720; + uint16_t _12721 = (uint16_t)(213); + _curvea0[630] = _12721; + uint16_t _12722 = (uint16_t)(213); + _curvea0[631] = _12722; + uint16_t _12723 = (uint16_t)(214); + _curvea0[632] = _12723; + uint16_t _12724 = (uint16_t)(214); + _curvea0[633] = _12724; + uint16_t _12725 = (uint16_t)(214); + _curvea0[634] = _12725; + uint16_t _12726 = (uint16_t)(214); + _curvea0[635] = _12726; + uint16_t _12727 = (uint16_t)(214); + _curvea0[636] = _12727; + uint16_t _12728 = (uint16_t)(214); + _curvea0[637] = _12728; + uint16_t _12729 = (uint16_t)(214); + _curvea0[638] = _12729; + uint16_t _12730 = (uint16_t)(215); + _curvea0[639] = _12730; + uint16_t _12731 = (uint16_t)(215); + _curvea0[640] = _12731; + uint16_t _12732 = (uint16_t)(215); + _curvea0[641] = _12732; + uint16_t _12733 = (uint16_t)(215); + _curvea0[642] = _12733; + uint16_t _12734 = (uint16_t)(215); + _curvea0[643] = _12734; + uint16_t _12735 = (uint16_t)(215); + _curvea0[644] = _12735; + uint16_t _12736 = (uint16_t)(216); + _curvea0[645] = _12736; + uint16_t _12737 = (uint16_t)(216); + _curvea0[646] = _12737; + uint16_t _12738 = (uint16_t)(216); + _curvea0[647] = _12738; + uint16_t _12739 = (uint16_t)(216); + _curvea0[648] = _12739; + uint16_t _12740 = (uint16_t)(216); + _curvea0[649] = _12740; + uint16_t _12741 = (uint16_t)(216); + _curvea0[650] = _12741; + uint16_t _12742 = (uint16_t)(216); + _curvea0[651] = _12742; + uint16_t _12743 = (uint16_t)(217); + _curvea0[652] = _12743; + uint16_t _12744 = (uint16_t)(217); + _curvea0[653] = _12744; + uint16_t _12745 = (uint16_t)(217); + _curvea0[654] = _12745; + uint16_t _12746 = (uint16_t)(217); + _curvea0[655] = _12746; + uint16_t _12747 = (uint16_t)(217); + _curvea0[656] = _12747; + uint16_t _12748 = (uint16_t)(217); + _curvea0[657] = _12748; + uint16_t _12749 = (uint16_t)(217); + _curvea0[658] = _12749; + uint16_t _12750 = (uint16_t)(218); + _curvea0[659] = _12750; + uint16_t _12751 = (uint16_t)(218); + _curvea0[660] = _12751; + uint16_t _12752 = (uint16_t)(218); + _curvea0[661] = _12752; + uint16_t _12753 = (uint16_t)(218); + _curvea0[662] = _12753; + uint16_t _12754 = (uint16_t)(218); + _curvea0[663] = _12754; + uint16_t _12755 = (uint16_t)(218); + _curvea0[664] = _12755; + uint16_t _12756 = (uint16_t)(218); + _curvea0[665] = _12756; + uint16_t _12757 = (uint16_t)(219); + _curvea0[666] = _12757; + uint16_t _12758 = (uint16_t)(219); + _curvea0[667] = _12758; + uint16_t _12759 = (uint16_t)(219); + _curvea0[668] = _12759; + uint16_t _12760 = (uint16_t)(219); + _curvea0[669] = _12760; + uint16_t _12761 = (uint16_t)(219); + _curvea0[670] = _12761; + uint16_t _12762 = (uint16_t)(219); + _curvea0[671] = _12762; + uint16_t _12763 = (uint16_t)(219); + _curvea0[672] = _12763; + uint16_t _12764 = (uint16_t)(220); + _curvea0[673] = _12764; + uint16_t _12765 = (uint16_t)(220); + _curvea0[674] = _12765; + uint16_t _12766 = (uint16_t)(220); + _curvea0[675] = _12766; + uint16_t _12767 = (uint16_t)(220); + _curvea0[676] = _12767; + uint16_t _12768 = (uint16_t)(220); + _curvea0[677] = _12768; + uint16_t _12769 = (uint16_t)(220); + _curvea0[678] = _12769; + uint16_t _12770 = (uint16_t)(220); + _curvea0[679] = _12770; + uint16_t _12771 = (uint16_t)(220); + _curvea0[680] = _12771; + uint16_t _12772 = (uint16_t)(221); + _curvea0[681] = _12772; + uint16_t _12773 = (uint16_t)(221); + _curvea0[682] = _12773; + uint16_t _12774 = (uint16_t)(221); + _curvea0[683] = _12774; + uint16_t _12775 = (uint16_t)(221); + _curvea0[684] = _12775; + uint16_t _12776 = (uint16_t)(221); + _curvea0[685] = _12776; + uint16_t _12777 = (uint16_t)(221); + _curvea0[686] = _12777; + uint16_t _12778 = (uint16_t)(221); + _curvea0[687] = _12778; + uint16_t _12779 = (uint16_t)(222); + _curvea0[688] = _12779; + uint16_t _12780 = (uint16_t)(222); + _curvea0[689] = _12780; + uint16_t _12781 = (uint16_t)(222); + _curvea0[690] = _12781; + uint16_t _12782 = (uint16_t)(222); + _curvea0[691] = _12782; + uint16_t _12783 = (uint16_t)(222); + _curvea0[692] = _12783; + uint16_t _12784 = (uint16_t)(222); + _curvea0[693] = _12784; + uint16_t _12785 = (uint16_t)(222); + _curvea0[694] = _12785; + uint16_t _12786 = (uint16_t)(223); + _curvea0[695] = _12786; + uint16_t _12787 = (uint16_t)(223); + _curvea0[696] = _12787; + uint16_t _12788 = (uint16_t)(223); + _curvea0[697] = _12788; + uint16_t _12789 = (uint16_t)(223); + _curvea0[698] = _12789; + uint16_t _12790 = (uint16_t)(223); + _curvea0[699] = _12790; + uint16_t _12791 = (uint16_t)(223); + _curvea0[700] = _12791; + uint16_t _12792 = (uint16_t)(223); + _curvea0[701] = _12792; + uint16_t _12793 = (uint16_t)(223); + _curvea0[702] = _12793; + uint16_t _12794 = (uint16_t)(224); + _curvea0[703] = _12794; + uint16_t _12795 = (uint16_t)(224); + _curvea0[704] = _12795; + uint16_t _12796 = (uint16_t)(224); + _curvea0[705] = _12796; + uint16_t _12797 = (uint16_t)(224); + _curvea0[706] = _12797; + uint16_t _12798 = (uint16_t)(224); + _curvea0[707] = _12798; + uint16_t _12799 = (uint16_t)(224); + _curvea0[708] = _12799; + uint16_t _12800 = (uint16_t)(224); + _curvea0[709] = _12800; + uint16_t _12801 = (uint16_t)(224); + _curvea0[710] = _12801; + uint16_t _12802 = (uint16_t)(225); + _curvea0[711] = _12802; + uint16_t _12803 = (uint16_t)(225); + _curvea0[712] = _12803; + uint16_t _12804 = (uint16_t)(225); + _curvea0[713] = _12804; + uint16_t _12805 = (uint16_t)(225); + _curvea0[714] = _12805; + uint16_t _12806 = (uint16_t)(225); + _curvea0[715] = _12806; + uint16_t _12807 = (uint16_t)(225); + _curvea0[716] = _12807; + uint16_t _12808 = (uint16_t)(225); + _curvea0[717] = _12808; + uint16_t _12809 = (uint16_t)(226); + _curvea0[718] = _12809; + uint16_t _12810 = (uint16_t)(226); + _curvea0[719] = _12810; + uint16_t _12811 = (uint16_t)(226); + _curvea0[720] = _12811; + uint16_t _12812 = (uint16_t)(226); + _curvea0[721] = _12812; + uint16_t _12813 = (uint16_t)(226); + _curvea0[722] = _12813; + uint16_t _12814 = (uint16_t)(226); + _curvea0[723] = _12814; + uint16_t _12815 = (uint16_t)(226); + _curvea0[724] = _12815; + uint16_t _12816 = (uint16_t)(226); + _curvea0[725] = _12816; + uint16_t _12817 = (uint16_t)(227); + _curvea0[726] = _12817; + uint16_t _12818 = (uint16_t)(227); + _curvea0[727] = _12818; + uint16_t _12819 = (uint16_t)(227); + _curvea0[728] = _12819; + uint16_t _12820 = (uint16_t)(227); + _curvea0[729] = _12820; + uint16_t _12821 = (uint16_t)(227); + _curvea0[730] = _12821; + uint16_t _12822 = (uint16_t)(227); + _curvea0[731] = _12822; + uint16_t _12823 = (uint16_t)(227); + _curvea0[732] = _12823; + uint16_t _12824 = (uint16_t)(227); + _curvea0[733] = _12824; + uint16_t _12825 = (uint16_t)(228); + _curvea0[734] = _12825; + uint16_t _12826 = (uint16_t)(228); + _curvea0[735] = _12826; + uint16_t _12827 = (uint16_t)(228); + _curvea0[736] = _12827; + uint16_t _12828 = (uint16_t)(228); + _curvea0[737] = _12828; + uint16_t _12829 = (uint16_t)(228); + _curvea0[738] = _12829; + uint16_t _12830 = (uint16_t)(228); + _curvea0[739] = _12830; + uint16_t _12831 = (uint16_t)(228); + _curvea0[740] = _12831; + uint16_t _12832 = (uint16_t)(228); + _curvea0[741] = _12832; + uint16_t _12833 = (uint16_t)(228); + _curvea0[742] = _12833; + uint16_t _12834 = (uint16_t)(229); + _curvea0[743] = _12834; + uint16_t _12835 = (uint16_t)(229); + _curvea0[744] = _12835; + uint16_t _12836 = (uint16_t)(229); + _curvea0[745] = _12836; + uint16_t _12837 = (uint16_t)(229); + _curvea0[746] = _12837; + uint16_t _12838 = (uint16_t)(229); + _curvea0[747] = _12838; + uint16_t _12839 = (uint16_t)(229); + _curvea0[748] = _12839; + uint16_t _12840 = (uint16_t)(229); + _curvea0[749] = _12840; + uint16_t _12841 = (uint16_t)(229); + _curvea0[750] = _12841; + uint16_t _12842 = (uint16_t)(230); + _curvea0[751] = _12842; + uint16_t _12843 = (uint16_t)(230); + _curvea0[752] = _12843; + uint16_t _12844 = (uint16_t)(230); + _curvea0[753] = _12844; + uint16_t _12845 = (uint16_t)(230); + _curvea0[754] = _12845; + uint16_t _12846 = (uint16_t)(230); + _curvea0[755] = _12846; + uint16_t _12847 = (uint16_t)(230); + _curvea0[756] = _12847; + uint16_t _12848 = (uint16_t)(230); + _curvea0[757] = _12848; + uint16_t _12849 = (uint16_t)(230); + _curvea0[758] = _12849; + uint16_t _12850 = (uint16_t)(231); + _curvea0[759] = _12850; + uint16_t _12851 = (uint16_t)(231); + _curvea0[760] = _12851; + uint16_t _12852 = (uint16_t)(231); + _curvea0[761] = _12852; + uint16_t _12853 = (uint16_t)(231); + _curvea0[762] = _12853; + uint16_t _12854 = (uint16_t)(231); + _curvea0[763] = _12854; + uint16_t _12855 = (uint16_t)(231); + _curvea0[764] = _12855; + uint16_t _12856 = (uint16_t)(231); + _curvea0[765] = _12856; + uint16_t _12857 = (uint16_t)(231); + _curvea0[766] = _12857; + uint16_t _12858 = (uint16_t)(231); + _curvea0[767] = _12858; + uint16_t _12859 = (uint16_t)(232); + _curvea0[768] = _12859; + uint16_t _12860 = (uint16_t)(232); + _curvea0[769] = _12860; + uint16_t _12861 = (uint16_t)(232); + _curvea0[770] = _12861; + uint16_t _12862 = (uint16_t)(232); + _curvea0[771] = _12862; + uint16_t _12863 = (uint16_t)(232); + _curvea0[772] = _12863; + uint16_t _12864 = (uint16_t)(232); + _curvea0[773] = _12864; + uint16_t _12865 = (uint16_t)(232); + _curvea0[774] = _12865; + uint16_t _12866 = (uint16_t)(232); + _curvea0[775] = _12866; + uint16_t _12867 = (uint16_t)(233); + _curvea0[776] = _12867; + uint16_t _12868 = (uint16_t)(233); + _curvea0[777] = _12868; + uint16_t _12869 = (uint16_t)(233); + _curvea0[778] = _12869; + uint16_t _12870 = (uint16_t)(233); + _curvea0[779] = _12870; + uint16_t _12871 = (uint16_t)(233); + _curvea0[780] = _12871; + uint16_t _12872 = (uint16_t)(233); + _curvea0[781] = _12872; + uint16_t _12873 = (uint16_t)(233); + _curvea0[782] = _12873; + uint16_t _12874 = (uint16_t)(233); + _curvea0[783] = _12874; + uint16_t _12875 = (uint16_t)(233); + _curvea0[784] = _12875; + uint16_t _12876 = (uint16_t)(234); + _curvea0[785] = _12876; + uint16_t _12877 = (uint16_t)(234); + _curvea0[786] = _12877; + uint16_t _12878 = (uint16_t)(234); + _curvea0[787] = _12878; + uint16_t _12879 = (uint16_t)(234); + _curvea0[788] = _12879; + uint16_t _12880 = (uint16_t)(234); + _curvea0[789] = _12880; + uint16_t _12881 = (uint16_t)(234); + _curvea0[790] = _12881; + uint16_t _12882 = (uint16_t)(234); + _curvea0[791] = _12882; + uint16_t _12883 = (uint16_t)(234); + _curvea0[792] = _12883; + uint16_t _12884 = (uint16_t)(234); + _curvea0[793] = _12884; + uint16_t _12885 = (uint16_t)(235); + _curvea0[794] = _12885; + uint16_t _12886 = (uint16_t)(235); + _curvea0[795] = _12886; + uint16_t _12887 = (uint16_t)(235); + _curvea0[796] = _12887; + uint16_t _12888 = (uint16_t)(235); + _curvea0[797] = _12888; + uint16_t _12889 = (uint16_t)(235); + _curvea0[798] = _12889; + uint16_t _12890 = (uint16_t)(235); + _curvea0[799] = _12890; + uint16_t _12891 = (uint16_t)(235); + _curvea0[800] = _12891; + uint16_t _12892 = (uint16_t)(235); + _curvea0[801] = _12892; + uint16_t _12893 = (uint16_t)(235); + _curvea0[802] = _12893; + uint16_t _12894 = (uint16_t)(236); + _curvea0[803] = _12894; + uint16_t _12895 = (uint16_t)(236); + _curvea0[804] = _12895; + uint16_t _12896 = (uint16_t)(236); + _curvea0[805] = _12896; + uint16_t _12897 = (uint16_t)(236); + _curvea0[806] = _12897; + uint16_t _12898 = (uint16_t)(236); + _curvea0[807] = _12898; + uint16_t _12899 = (uint16_t)(236); + _curvea0[808] = _12899; + uint16_t _12900 = (uint16_t)(236); + _curvea0[809] = _12900; + uint16_t _12901 = (uint16_t)(236); + _curvea0[810] = _12901; + uint16_t _12902 = (uint16_t)(236); + _curvea0[811] = _12902; + uint16_t _12903 = (uint16_t)(237); + _curvea0[812] = _12903; + uint16_t _12904 = (uint16_t)(237); + _curvea0[813] = _12904; + uint16_t _12905 = (uint16_t)(237); + _curvea0[814] = _12905; + uint16_t _12906 = (uint16_t)(237); + _curvea0[815] = _12906; + uint16_t _12907 = (uint16_t)(237); + _curvea0[816] = _12907; + uint16_t _12908 = (uint16_t)(237); + _curvea0[817] = _12908; + uint16_t _12909 = (uint16_t)(237); + _curvea0[818] = _12909; + uint16_t _12910 = (uint16_t)(237); + _curvea0[819] = _12910; + uint16_t _12911 = (uint16_t)(237); + _curvea0[820] = _12911; + uint16_t _12912 = (uint16_t)(237); + _curvea0[821] = _12912; + uint16_t _12913 = (uint16_t)(238); + _curvea0[822] = _12913; + uint16_t _12914 = (uint16_t)(238); + _curvea0[823] = _12914; + uint16_t _12915 = (uint16_t)(238); + _curvea0[824] = _12915; + uint16_t _12916 = (uint16_t)(238); + _curvea0[825] = _12916; + uint16_t _12917 = (uint16_t)(238); + _curvea0[826] = _12917; + uint16_t _12918 = (uint16_t)(238); + _curvea0[827] = _12918; + uint16_t _12919 = (uint16_t)(238); + _curvea0[828] = _12919; + uint16_t _12920 = (uint16_t)(238); + _curvea0[829] = _12920; + uint16_t _12921 = (uint16_t)(238); + _curvea0[830] = _12921; + uint16_t _12922 = (uint16_t)(239); + _curvea0[831] = _12922; + uint16_t _12923 = (uint16_t)(239); + _curvea0[832] = _12923; + uint16_t _12924 = (uint16_t)(239); + _curvea0[833] = _12924; + uint16_t _12925 = (uint16_t)(239); + _curvea0[834] = _12925; + uint16_t _12926 = (uint16_t)(239); + _curvea0[835] = _12926; + uint16_t _12927 = (uint16_t)(239); + _curvea0[836] = _12927; + uint16_t _12928 = (uint16_t)(239); + _curvea0[837] = _12928; + uint16_t _12929 = (uint16_t)(239); + _curvea0[838] = _12929; + uint16_t _12930 = (uint16_t)(239); + _curvea0[839] = _12930; + uint16_t _12931 = (uint16_t)(239); + _curvea0[840] = _12931; + uint16_t _12932 = (uint16_t)(240); + _curvea0[841] = _12932; + uint16_t _12933 = (uint16_t)(240); + _curvea0[842] = _12933; + uint16_t _12934 = (uint16_t)(240); + _curvea0[843] = _12934; + uint16_t _12935 = (uint16_t)(240); + _curvea0[844] = _12935; + uint16_t _12936 = (uint16_t)(240); + _curvea0[845] = _12936; + uint16_t _12937 = (uint16_t)(240); + _curvea0[846] = _12937; + uint16_t _12938 = (uint16_t)(240); + _curvea0[847] = _12938; + uint16_t _12939 = (uint16_t)(240); + _curvea0[848] = _12939; + uint16_t _12940 = (uint16_t)(240); + _curvea0[849] = _12940; + uint16_t _12941 = (uint16_t)(240); + _curvea0[850] = _12941; + uint16_t _12942 = (uint16_t)(241); + _curvea0[851] = _12942; + uint16_t _12943 = (uint16_t)(241); + _curvea0[852] = _12943; + uint16_t _12944 = (uint16_t)(241); + _curvea0[853] = _12944; + uint16_t _12945 = (uint16_t)(241); + _curvea0[854] = _12945; + uint16_t _12946 = (uint16_t)(241); + _curvea0[855] = _12946; + uint16_t _12947 = (uint16_t)(241); + _curvea0[856] = _12947; + uint16_t _12948 = (uint16_t)(241); + _curvea0[857] = _12948; + uint16_t _12949 = (uint16_t)(241); + _curvea0[858] = _12949; + uint16_t _12950 = (uint16_t)(241); + _curvea0[859] = _12950; + uint16_t _12951 = (uint16_t)(241); + _curvea0[860] = _12951; + uint16_t _12952 = (uint16_t)(242); + _curvea0[861] = _12952; + uint16_t _12953 = (uint16_t)(242); + _curvea0[862] = _12953; + uint16_t _12954 = (uint16_t)(242); + _curvea0[863] = _12954; + uint16_t _12955 = (uint16_t)(242); + _curvea0[864] = _12955; + uint16_t _12956 = (uint16_t)(242); + _curvea0[865] = _12956; + uint16_t _12957 = (uint16_t)(242); + _curvea0[866] = _12957; + uint16_t _12958 = (uint16_t)(242); + _curvea0[867] = _12958; + uint16_t _12959 = (uint16_t)(242); + _curvea0[868] = _12959; + uint16_t _12960 = (uint16_t)(242); + _curvea0[869] = _12960; + uint16_t _12961 = (uint16_t)(242); + _curvea0[870] = _12961; + uint16_t _12962 = (uint16_t)(243); + _curvea0[871] = _12962; + uint16_t _12963 = (uint16_t)(243); + _curvea0[872] = _12963; + uint16_t _12964 = (uint16_t)(243); + _curvea0[873] = _12964; + uint16_t _12965 = (uint16_t)(243); + _curvea0[874] = _12965; + uint16_t _12966 = (uint16_t)(243); + _curvea0[875] = _12966; + uint16_t _12967 = (uint16_t)(243); + _curvea0[876] = _12967; + uint16_t _12968 = (uint16_t)(243); + _curvea0[877] = _12968; + uint16_t _12969 = (uint16_t)(243); + _curvea0[878] = _12969; + uint16_t _12970 = (uint16_t)(243); + _curvea0[879] = _12970; + uint16_t _12971 = (uint16_t)(243); + _curvea0[880] = _12971; + uint16_t _12972 = (uint16_t)(244); + _curvea0[881] = _12972; + uint16_t _12973 = (uint16_t)(244); + _curvea0[882] = _12973; + uint16_t _12974 = (uint16_t)(244); + _curvea0[883] = _12974; + uint16_t _12975 = (uint16_t)(244); + _curvea0[884] = _12975; + uint16_t _12976 = (uint16_t)(244); + _curvea0[885] = _12976; + uint16_t _12977 = (uint16_t)(244); + _curvea0[886] = _12977; + uint16_t _12978 = (uint16_t)(244); + _curvea0[887] = _12978; + uint16_t _12979 = (uint16_t)(244); + _curvea0[888] = _12979; + uint16_t _12980 = (uint16_t)(244); + _curvea0[889] = _12980; + uint16_t _12981 = (uint16_t)(244); + _curvea0[890] = _12981; + uint16_t _12982 = (uint16_t)(244); + _curvea0[891] = _12982; + uint16_t _12983 = (uint16_t)(245); + _curvea0[892] = _12983; + uint16_t _12984 = (uint16_t)(245); + _curvea0[893] = _12984; + uint16_t _12985 = (uint16_t)(245); + _curvea0[894] = _12985; + uint16_t _12986 = (uint16_t)(245); + _curvea0[895] = _12986; + uint16_t _12987 = (uint16_t)(245); + _curvea0[896] = _12987; + uint16_t _12988 = (uint16_t)(245); + _curvea0[897] = _12988; + uint16_t _12989 = (uint16_t)(245); + _curvea0[898] = _12989; + uint16_t _12990 = (uint16_t)(245); + _curvea0[899] = _12990; + uint16_t _12991 = (uint16_t)(245); + _curvea0[900] = _12991; + uint16_t _12992 = (uint16_t)(245); + _curvea0[901] = _12992; + uint16_t _12993 = (uint16_t)(245); + _curvea0[902] = _12993; + uint16_t _12994 = (uint16_t)(246); + _curvea0[903] = _12994; + uint16_t _12995 = (uint16_t)(246); + _curvea0[904] = _12995; + uint16_t _12996 = (uint16_t)(246); + _curvea0[905] = _12996; + uint16_t _12997 = (uint16_t)(246); + _curvea0[906] = _12997; + uint16_t _12998 = (uint16_t)(246); + _curvea0[907] = _12998; + uint16_t _12999 = (uint16_t)(246); + _curvea0[908] = _12999; + uint16_t _13000 = (uint16_t)(246); + _curvea0[909] = _13000; + uint16_t _13001 = (uint16_t)(246); + _curvea0[910] = _13001; + uint16_t _13002 = (uint16_t)(246); + _curvea0[911] = _13002; + uint16_t _13003 = (uint16_t)(246); + _curvea0[912] = _13003; + uint16_t _13004 = (uint16_t)(246); + _curvea0[913] = _13004; + uint16_t _13005 = (uint16_t)(247); + _curvea0[914] = _13005; + uint16_t _13006 = (uint16_t)(247); + _curvea0[915] = _13006; + uint16_t _13007 = (uint16_t)(247); + _curvea0[916] = _13007; + uint16_t _13008 = (uint16_t)(247); + _curvea0[917] = _13008; + uint16_t _13009 = (uint16_t)(247); + _curvea0[918] = _13009; + uint16_t _13010 = (uint16_t)(247); + _curvea0[919] = _13010; + uint16_t _13011 = (uint16_t)(247); + _curvea0[920] = _13011; + uint16_t _13012 = (uint16_t)(247); + _curvea0[921] = _13012; + uint16_t _13013 = (uint16_t)(247); + _curvea0[922] = _13013; + uint16_t _13014 = (uint16_t)(247); + _curvea0[923] = _13014; + uint16_t _13015 = (uint16_t)(247); + _curvea0[924] = _13015; + uint16_t _13016 = (uint16_t)(248); + _curvea0[925] = _13016; + uint16_t _13017 = (uint16_t)(248); + _curvea0[926] = _13017; + uint16_t _13018 = (uint16_t)(248); + _curvea0[927] = _13018; + uint16_t _13019 = (uint16_t)(248); + _curvea0[928] = _13019; + uint16_t _13020 = (uint16_t)(248); + _curvea0[929] = _13020; + uint16_t _13021 = (uint16_t)(248); + _curvea0[930] = _13021; + uint16_t _13022 = (uint16_t)(248); + _curvea0[931] = _13022; + uint16_t _13023 = (uint16_t)(248); + _curvea0[932] = _13023; + uint16_t _13024 = (uint16_t)(248); + _curvea0[933] = _13024; + uint16_t _13025 = (uint16_t)(248); + _curvea0[934] = _13025; + uint16_t _13026 = (uint16_t)(248); + _curvea0[935] = _13026; + uint16_t _13027 = (uint16_t)(249); + _curvea0[936] = _13027; + uint16_t _13028 = (uint16_t)(249); + _curvea0[937] = _13028; + uint16_t _13029 = (uint16_t)(249); + _curvea0[938] = _13029; + uint16_t _13030 = (uint16_t)(249); + _curvea0[939] = _13030; + uint16_t _13031 = (uint16_t)(249); + _curvea0[940] = _13031; + uint16_t _13032 = (uint16_t)(249); + _curvea0[941] = _13032; + uint16_t _13033 = (uint16_t)(249); + _curvea0[942] = _13033; + uint16_t _13034 = (uint16_t)(249); + _curvea0[943] = _13034; + uint16_t _13035 = (uint16_t)(249); + _curvea0[944] = _13035; + uint16_t _13036 = (uint16_t)(249); + _curvea0[945] = _13036; + uint16_t _13037 = (uint16_t)(249); + _curvea0[946] = _13037; + uint16_t _13038 = (uint16_t)(249); + _curvea0[947] = _13038; + uint16_t _13039 = (uint16_t)(250); + _curvea0[948] = _13039; + uint16_t _13040 = (uint16_t)(250); + _curvea0[949] = _13040; + uint16_t _13041 = (uint16_t)(250); + _curvea0[950] = _13041; + uint16_t _13042 = (uint16_t)(250); + _curvea0[951] = _13042; + uint16_t _13043 = (uint16_t)(250); + _curvea0[952] = _13043; + uint16_t _13044 = (uint16_t)(250); + _curvea0[953] = _13044; + uint16_t _13045 = (uint16_t)(250); + _curvea0[954] = _13045; + uint16_t _13046 = (uint16_t)(250); + _curvea0[955] = _13046; + uint16_t _13047 = (uint16_t)(250); + _curvea0[956] = _13047; + uint16_t _13048 = (uint16_t)(250); + _curvea0[957] = _13048; + uint16_t _13049 = (uint16_t)(250); + _curvea0[958] = _13049; + uint16_t _13050 = (uint16_t)(250); + _curvea0[959] = _13050; + uint16_t _13051 = (uint16_t)(251); + _curvea0[960] = _13051; + uint16_t _13052 = (uint16_t)(251); + _curvea0[961] = _13052; + uint16_t _13053 = (uint16_t)(251); + _curvea0[962] = _13053; + uint16_t _13054 = (uint16_t)(251); + _curvea0[963] = _13054; + uint16_t _13055 = (uint16_t)(251); + _curvea0[964] = _13055; + uint16_t _13056 = (uint16_t)(251); + _curvea0[965] = _13056; + uint16_t _13057 = (uint16_t)(251); + _curvea0[966] = _13057; + uint16_t _13058 = (uint16_t)(251); + _curvea0[967] = _13058; + uint16_t _13059 = (uint16_t)(251); + _curvea0[968] = _13059; + uint16_t _13060 = (uint16_t)(251); + _curvea0[969] = _13060; + uint16_t _13061 = (uint16_t)(251); + _curvea0[970] = _13061; + uint16_t _13062 = (uint16_t)(251); + _curvea0[971] = _13062; + uint16_t _13063 = (uint16_t)(252); + _curvea0[972] = _13063; + uint16_t _13064 = (uint16_t)(252); + _curvea0[973] = _13064; + uint16_t _13065 = (uint16_t)(252); + _curvea0[974] = _13065; + uint16_t _13066 = (uint16_t)(252); + _curvea0[975] = _13066; + uint16_t _13067 = (uint16_t)(252); + _curvea0[976] = _13067; + uint16_t _13068 = (uint16_t)(252); + _curvea0[977] = _13068; + uint16_t _13069 = (uint16_t)(252); + _curvea0[978] = _13069; + uint16_t _13070 = (uint16_t)(252); + _curvea0[979] = _13070; + uint16_t _13071 = (uint16_t)(252); + _curvea0[980] = _13071; + uint16_t _13072 = (uint16_t)(252); + _curvea0[981] = _13072; + uint16_t _13073 = (uint16_t)(252); + _curvea0[982] = _13073; + uint16_t _13074 = (uint16_t)(252); + _curvea0[983] = _13074; + uint16_t _13075 = (uint16_t)(252); + _curvea0[984] = _13075; + uint16_t _13076 = (uint16_t)(253); + _curvea0[985] = _13076; + uint16_t _13077 = (uint16_t)(253); + _curvea0[986] = _13077; + uint16_t _13078 = (uint16_t)(253); + _curvea0[987] = _13078; + uint16_t _13079 = (uint16_t)(253); + _curvea0[988] = _13079; + uint16_t _13080 = (uint16_t)(253); + _curvea0[989] = _13080; + uint16_t _13081 = (uint16_t)(253); + _curvea0[990] = _13081; + uint16_t _13082 = (uint16_t)(253); + _curvea0[991] = _13082; + uint16_t _13083 = (uint16_t)(253); + _curvea0[992] = _13083; + uint16_t _13084 = (uint16_t)(253); + _curvea0[993] = _13084; + uint16_t _13085 = (uint16_t)(253); + _curvea0[994] = _13085; + uint16_t _13086 = (uint16_t)(253); + _curvea0[995] = _13086; + uint16_t _13087 = (uint16_t)(253); + _curvea0[996] = _13087; + uint16_t _13088 = (uint16_t)(253); + _curvea0[997] = _13088; + uint16_t _13089 = (uint16_t)(254); + _curvea0[998] = _13089; + uint16_t _13090 = (uint16_t)(254); + _curvea0[999] = _13090; + uint16_t _13091 = (uint16_t)(254); + _curvea0[1000] = _13091; + uint16_t _13092 = (uint16_t)(254); + _curvea0[1001] = _13092; + uint16_t _13093 = (uint16_t)(254); + _curvea0[1002] = _13093; + uint16_t _13094 = (uint16_t)(254); + _curvea0[1003] = _13094; + uint16_t _13095 = (uint16_t)(254); + _curvea0[1004] = _13095; + uint16_t _13096 = (uint16_t)(254); + _curvea0[1005] = _13096; + uint16_t _13097 = (uint16_t)(254); + _curvea0[1006] = _13097; + uint16_t _13098 = (uint16_t)(254); + _curvea0[1007] = _13098; + uint16_t _13099 = (uint16_t)(254); + _curvea0[1008] = _13099; + uint16_t _13100 = (uint16_t)(254); + _curvea0[1009] = _13100; + uint16_t _13101 = (uint16_t)(254); + _curvea0[1010] = _13101; + uint16_t _13102 = (uint16_t)(255); + _curvea0[1011] = _13102; + uint16_t _13103 = (uint16_t)(255); + _curvea0[1012] = _13103; + uint16_t _13104 = (uint16_t)(255); + _curvea0[1013] = _13104; + uint16_t _13105 = (uint16_t)(255); + _curvea0[1014] = _13105; + uint16_t _13106 = (uint16_t)(255); + _curvea0[1015] = _13106; + uint16_t _13107 = (uint16_t)(255); + _curvea0[1016] = _13107; + uint16_t _13108 = (uint16_t)(255); + _curvea0[1017] = _13108; + uint16_t _13109 = (uint16_t)(255); + _curvea0[1018] = _13109; + uint16_t _13110 = (uint16_t)(255); + _curvea0[1019] = _13110; + uint16_t _13111 = (uint16_t)(255); + _curvea0[1020] = _13111; + uint16_t _13112 = (uint16_t)(255); + _curvea0[1021] = _13112; + uint16_t _13113 = (uint16_t)(255); + _curvea0[1022] = _13113; + uint16_t _13114 = (uint16_t)(255); + _curvea0[1023] = _13114; + + int16_t _13115 = (int16_t)(1023); + int16_t _13116 = min(_corrected_stencil_10, _13115); + int16_t _13117 = (int16_t)(0); + int16_t _13118 = max(_13116, _13117); + uint16_t _13119 = (uint16_t)(_13118); + int32_t _13120 = (int32_t)(_13119); + uint16_t _13121 = ((const uint16_t *)_curvea0)[_13120]; + return _13121; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_10(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_11 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _13140 = (uint16_t)(0); + _curvea0[0] = _13140; + uint16_t _13141 = (uint16_t)(4); + _curvea0[1] = _13141; + uint16_t _13142 = (uint16_t)(7); + _curvea0[2] = _13142; + uint16_t _13143 = (uint16_t)(8); + _curvea0[3] = _13143; + uint16_t _13144 = (uint16_t)(10); + _curvea0[4] = _13144; + uint16_t _13145 = (uint16_t)(11); + _curvea0[5] = _13145; + uint16_t _13146 = (uint16_t)(12); + _curvea0[6] = _13146; + uint16_t _13147 = (uint16_t)(13); + _curvea0[7] = _13147; + uint16_t _13148 = (uint16_t)(14); + _curvea0[8] = _13148; + uint16_t _13149 = (uint16_t)(15); + _curvea0[9] = _13149; + uint16_t _13150 = (uint16_t)(16); + _curvea0[10] = _13150; + uint16_t _13151 = (uint16_t)(17); + _curvea0[11] = _13151; + uint16_t _13152 = (uint16_t)(18); + _curvea0[12] = _13152; + uint16_t _13153 = (uint16_t)(19); + _curvea0[13] = _13153; + uint16_t _13154 = (uint16_t)(20); + _curvea0[14] = _13154; + uint16_t _13155 = (uint16_t)(21); + _curvea0[15] = _13155; + uint16_t _13156 = (uint16_t)(22); + _curvea0[16] = _13156; + uint16_t _13157 = (uint16_t)(22); + _curvea0[17] = _13157; + uint16_t _13158 = (uint16_t)(23); + _curvea0[18] = _13158; + uint16_t _13159 = (uint16_t)(24); + _curvea0[19] = _13159; + uint16_t _13160 = (uint16_t)(25); + _curvea0[20] = _13160; + uint16_t _13161 = (uint16_t)(25); + _curvea0[21] = _13161; + uint16_t _13162 = (uint16_t)(26); + _curvea0[22] = _13162; + uint16_t _13163 = (uint16_t)(27); + _curvea0[23] = _13163; + uint16_t _13164 = (uint16_t)(27); + _curvea0[24] = _13164; + uint16_t _13165 = (uint16_t)(28); + _curvea0[25] = _13165; + uint16_t _13166 = (uint16_t)(29); + _curvea0[26] = _13166; + uint16_t _13167 = (uint16_t)(29); + _curvea0[27] = _13167; + uint16_t _13168 = (uint16_t)(30); + _curvea0[28] = _13168; + uint16_t _13169 = (uint16_t)(31); + _curvea0[29] = _13169; + uint16_t _13170 = (uint16_t)(31); + _curvea0[30] = _13170; + uint16_t _13171 = (uint16_t)(32); + _curvea0[31] = _13171; + uint16_t _13172 = (uint16_t)(33); + _curvea0[32] = _13172; + uint16_t _13173 = (uint16_t)(33); + _curvea0[33] = _13173; + uint16_t _13174 = (uint16_t)(34); + _curvea0[34] = _13174; + uint16_t _13175 = (uint16_t)(34); + _curvea0[35] = _13175; + uint16_t _13176 = (uint16_t)(35); + _curvea0[36] = _13176; + uint16_t _13177 = (uint16_t)(36); + _curvea0[37] = _13177; + uint16_t _13178 = (uint16_t)(36); + _curvea0[38] = _13178; + uint16_t _13179 = (uint16_t)(37); + _curvea0[39] = _13179; + uint16_t _13180 = (uint16_t)(37); + _curvea0[40] = _13180; + uint16_t _13181 = (uint16_t)(38); + _curvea0[41] = _13181; + uint16_t _13182 = (uint16_t)(39); + _curvea0[42] = _13182; + uint16_t _13183 = (uint16_t)(39); + _curvea0[43] = _13183; + uint16_t _13184 = (uint16_t)(40); + _curvea0[44] = _13184; + uint16_t _13185 = (uint16_t)(40); + _curvea0[45] = _13185; + uint16_t _13186 = (uint16_t)(41); + _curvea0[46] = _13186; + uint16_t _13187 = (uint16_t)(41); + _curvea0[47] = _13187; + uint16_t _13188 = (uint16_t)(42); + _curvea0[48] = _13188; + uint16_t _13189 = (uint16_t)(42); + _curvea0[49] = _13189; + uint16_t _13190 = (uint16_t)(43); + _curvea0[50] = _13190; + uint16_t _13191 = (uint16_t)(44); + _curvea0[51] = _13191; + uint16_t _13192 = (uint16_t)(44); + _curvea0[52] = _13192; + uint16_t _13193 = (uint16_t)(45); + _curvea0[53] = _13193; + uint16_t _13194 = (uint16_t)(45); + _curvea0[54] = _13194; + uint16_t _13195 = (uint16_t)(46); + _curvea0[55] = _13195; + uint16_t _13196 = (uint16_t)(46); + _curvea0[56] = _13196; + uint16_t _13197 = (uint16_t)(47); + _curvea0[57] = _13197; + uint16_t _13198 = (uint16_t)(47); + _curvea0[58] = _13198; + uint16_t _13199 = (uint16_t)(48); + _curvea0[59] = _13199; + uint16_t _13200 = (uint16_t)(48); + _curvea0[60] = _13200; + uint16_t _13201 = (uint16_t)(49); + _curvea0[61] = _13201; + uint16_t _13202 = (uint16_t)(49); + _curvea0[62] = _13202; + uint16_t _13203 = (uint16_t)(50); + _curvea0[63] = _13203; + uint16_t _13204 = (uint16_t)(50); + _curvea0[64] = _13204; + uint16_t _13205 = (uint16_t)(51); + _curvea0[65] = _13205; + uint16_t _13206 = (uint16_t)(51); + _curvea0[66] = _13206; + uint16_t _13207 = (uint16_t)(52); + _curvea0[67] = _13207; + uint16_t _13208 = (uint16_t)(52); + _curvea0[68] = _13208; + uint16_t _13209 = (uint16_t)(53); + _curvea0[69] = _13209; + uint16_t _13210 = (uint16_t)(53); + _curvea0[70] = _13210; + uint16_t _13211 = (uint16_t)(54); + _curvea0[71] = _13211; + uint16_t _13212 = (uint16_t)(54); + _curvea0[72] = _13212; + uint16_t _13213 = (uint16_t)(55); + _curvea0[73] = _13213; + uint16_t _13214 = (uint16_t)(55); + _curvea0[74] = _13214; + uint16_t _13215 = (uint16_t)(56); + _curvea0[75] = _13215; + uint16_t _13216 = (uint16_t)(56); + _curvea0[76] = _13216; + uint16_t _13217 = (uint16_t)(57); + _curvea0[77] = _13217; + uint16_t _13218 = (uint16_t)(57); + _curvea0[78] = _13218; + uint16_t _13219 = (uint16_t)(58); + _curvea0[79] = _13219; + uint16_t _13220 = (uint16_t)(58); + _curvea0[80] = _13220; + uint16_t _13221 = (uint16_t)(58); + _curvea0[81] = _13221; + uint16_t _13222 = (uint16_t)(59); + _curvea0[82] = _13222; + uint16_t _13223 = (uint16_t)(59); + _curvea0[83] = _13223; + uint16_t _13224 = (uint16_t)(60); + _curvea0[84] = _13224; + uint16_t _13225 = (uint16_t)(60); + _curvea0[85] = _13225; + uint16_t _13226 = (uint16_t)(61); + _curvea0[86] = _13226; + uint16_t _13227 = (uint16_t)(61); + _curvea0[87] = _13227; + uint16_t _13228 = (uint16_t)(62); + _curvea0[88] = _13228; + uint16_t _13229 = (uint16_t)(62); + _curvea0[89] = _13229; + uint16_t _13230 = (uint16_t)(63); + _curvea0[90] = _13230; + uint16_t _13231 = (uint16_t)(63); + _curvea0[91] = _13231; + uint16_t _13232 = (uint16_t)(64); + _curvea0[92] = _13232; + uint16_t _13233 = (uint16_t)(64); + _curvea0[93] = _13233; + uint16_t _13234 = (uint16_t)(64); + _curvea0[94] = _13234; + uint16_t _13235 = (uint16_t)(65); + _curvea0[95] = _13235; + uint16_t _13236 = (uint16_t)(65); + _curvea0[96] = _13236; + uint16_t _13237 = (uint16_t)(66); + _curvea0[97] = _13237; + uint16_t _13238 = (uint16_t)(66); + _curvea0[98] = _13238; + uint16_t _13239 = (uint16_t)(67); + _curvea0[99] = _13239; + uint16_t _13240 = (uint16_t)(67); + _curvea0[100] = _13240; + uint16_t _13241 = (uint16_t)(68); + _curvea0[101] = _13241; + uint16_t _13242 = (uint16_t)(68); + _curvea0[102] = _13242; + uint16_t _13243 = (uint16_t)(68); + _curvea0[103] = _13243; + uint16_t _13244 = (uint16_t)(69); + _curvea0[104] = _13244; + uint16_t _13245 = (uint16_t)(69); + _curvea0[105] = _13245; + uint16_t _13246 = (uint16_t)(70); + _curvea0[106] = _13246; + uint16_t _13247 = (uint16_t)(70); + _curvea0[107] = _13247; + uint16_t _13248 = (uint16_t)(71); + _curvea0[108] = _13248; + uint16_t _13249 = (uint16_t)(71); + _curvea0[109] = _13249; + uint16_t _13250 = (uint16_t)(71); + _curvea0[110] = _13250; + uint16_t _13251 = (uint16_t)(72); + _curvea0[111] = _13251; + uint16_t _13252 = (uint16_t)(72); + _curvea0[112] = _13252; + uint16_t _13253 = (uint16_t)(73); + _curvea0[113] = _13253; + uint16_t _13254 = (uint16_t)(73); + _curvea0[114] = _13254; + uint16_t _13255 = (uint16_t)(74); + _curvea0[115] = _13255; + uint16_t _13256 = (uint16_t)(74); + _curvea0[116] = _13256; + uint16_t _13257 = (uint16_t)(74); + _curvea0[117] = _13257; + uint16_t _13258 = (uint16_t)(75); + _curvea0[118] = _13258; + uint16_t _13259 = (uint16_t)(75); + _curvea0[119] = _13259; + uint16_t _13260 = (uint16_t)(76); + _curvea0[120] = _13260; + uint16_t _13261 = (uint16_t)(76); + _curvea0[121] = _13261; + uint16_t _13262 = (uint16_t)(77); + _curvea0[122] = _13262; + uint16_t _13263 = (uint16_t)(77); + _curvea0[123] = _13263; + uint16_t _13264 = (uint16_t)(77); + _curvea0[124] = _13264; + uint16_t _13265 = (uint16_t)(78); + _curvea0[125] = _13265; + uint16_t _13266 = (uint16_t)(78); + _curvea0[126] = _13266; + uint16_t _13267 = (uint16_t)(79); + _curvea0[127] = _13267; + uint16_t _13268 = (uint16_t)(79); + _curvea0[128] = _13268; + uint16_t _13269 = (uint16_t)(79); + _curvea0[129] = _13269; + uint16_t _13270 = (uint16_t)(80); + _curvea0[130] = _13270; + uint16_t _13271 = (uint16_t)(80); + _curvea0[131] = _13271; + uint16_t _13272 = (uint16_t)(81); + _curvea0[132] = _13272; + uint16_t _13273 = (uint16_t)(81); + _curvea0[133] = _13273; + uint16_t _13274 = (uint16_t)(82); + _curvea0[134] = _13274; + uint16_t _13275 = (uint16_t)(82); + _curvea0[135] = _13275; + uint16_t _13276 = (uint16_t)(82); + _curvea0[136] = _13276; + uint16_t _13277 = (uint16_t)(83); + _curvea0[137] = _13277; + uint16_t _13278 = (uint16_t)(83); + _curvea0[138] = _13278; + uint16_t _13279 = (uint16_t)(84); + _curvea0[139] = _13279; + uint16_t _13280 = (uint16_t)(84); + _curvea0[140] = _13280; + uint16_t _13281 = (uint16_t)(84); + _curvea0[141] = _13281; + uint16_t _13282 = (uint16_t)(85); + _curvea0[142] = _13282; + uint16_t _13283 = (uint16_t)(85); + _curvea0[143] = _13283; + uint16_t _13284 = (uint16_t)(86); + _curvea0[144] = _13284; + uint16_t _13285 = (uint16_t)(86); + _curvea0[145] = _13285; + uint16_t _13286 = (uint16_t)(86); + _curvea0[146] = _13286; + uint16_t _13287 = (uint16_t)(87); + _curvea0[147] = _13287; + uint16_t _13288 = (uint16_t)(87); + _curvea0[148] = _13288; + uint16_t _13289 = (uint16_t)(88); + _curvea0[149] = _13289; + uint16_t _13290 = (uint16_t)(88); + _curvea0[150] = _13290; + uint16_t _13291 = (uint16_t)(88); + _curvea0[151] = _13291; + uint16_t _13292 = (uint16_t)(89); + _curvea0[152] = _13292; + uint16_t _13293 = (uint16_t)(89); + _curvea0[153] = _13293; + uint16_t _13294 = (uint16_t)(90); + _curvea0[154] = _13294; + uint16_t _13295 = (uint16_t)(90); + _curvea0[155] = _13295; + uint16_t _13296 = (uint16_t)(90); + _curvea0[156] = _13296; + uint16_t _13297 = (uint16_t)(91); + _curvea0[157] = _13297; + uint16_t _13298 = (uint16_t)(91); + _curvea0[158] = _13298; + uint16_t _13299 = (uint16_t)(92); + _curvea0[159] = _13299; + uint16_t _13300 = (uint16_t)(92); + _curvea0[160] = _13300; + uint16_t _13301 = (uint16_t)(92); + _curvea0[161] = _13301; + uint16_t _13302 = (uint16_t)(93); + _curvea0[162] = _13302; + uint16_t _13303 = (uint16_t)(93); + _curvea0[163] = _13303; + uint16_t _13304 = (uint16_t)(93); + _curvea0[164] = _13304; + uint16_t _13305 = (uint16_t)(94); + _curvea0[165] = _13305; + uint16_t _13306 = (uint16_t)(94); + _curvea0[166] = _13306; + uint16_t _13307 = (uint16_t)(95); + _curvea0[167] = _13307; + uint16_t _13308 = (uint16_t)(95); + _curvea0[168] = _13308; + uint16_t _13309 = (uint16_t)(95); + _curvea0[169] = _13309; + uint16_t _13310 = (uint16_t)(96); + _curvea0[170] = _13310; + uint16_t _13311 = (uint16_t)(96); + _curvea0[171] = _13311; + uint16_t _13312 = (uint16_t)(97); + _curvea0[172] = _13312; + uint16_t _13313 = (uint16_t)(97); + _curvea0[173] = _13313; + uint16_t _13314 = (uint16_t)(97); + _curvea0[174] = _13314; + uint16_t _13315 = (uint16_t)(98); + _curvea0[175] = _13315; + uint16_t _13316 = (uint16_t)(98); + _curvea0[176] = _13316; + uint16_t _13317 = (uint16_t)(99); + _curvea0[177] = _13317; + uint16_t _13318 = (uint16_t)(99); + _curvea0[178] = _13318; + uint16_t _13319 = (uint16_t)(99); + _curvea0[179] = _13319; + uint16_t _13320 = (uint16_t)(100); + _curvea0[180] = _13320; + uint16_t _13321 = (uint16_t)(100); + _curvea0[181] = _13321; + uint16_t _13322 = (uint16_t)(100); + _curvea0[182] = _13322; + uint16_t _13323 = (uint16_t)(101); + _curvea0[183] = _13323; + uint16_t _13324 = (uint16_t)(101); + _curvea0[184] = _13324; + uint16_t _13325 = (uint16_t)(102); + _curvea0[185] = _13325; + uint16_t _13326 = (uint16_t)(102); + _curvea0[186] = _13326; + uint16_t _13327 = (uint16_t)(102); + _curvea0[187] = _13327; + uint16_t _13328 = (uint16_t)(103); + _curvea0[188] = _13328; + uint16_t _13329 = (uint16_t)(103); + _curvea0[189] = _13329; + uint16_t _13330 = (uint16_t)(103); + _curvea0[190] = _13330; + uint16_t _13331 = (uint16_t)(104); + _curvea0[191] = _13331; + uint16_t _13332 = (uint16_t)(104); + _curvea0[192] = _13332; + uint16_t _13333 = (uint16_t)(105); + _curvea0[193] = _13333; + uint16_t _13334 = (uint16_t)(105); + _curvea0[194] = _13334; + uint16_t _13335 = (uint16_t)(105); + _curvea0[195] = _13335; + uint16_t _13336 = (uint16_t)(106); + _curvea0[196] = _13336; + uint16_t _13337 = (uint16_t)(106); + _curvea0[197] = _13337; + uint16_t _13338 = (uint16_t)(106); + _curvea0[198] = _13338; + uint16_t _13339 = (uint16_t)(107); + _curvea0[199] = _13339; + uint16_t _13340 = (uint16_t)(107); + _curvea0[200] = _13340; + uint16_t _13341 = (uint16_t)(108); + _curvea0[201] = _13341; + uint16_t _13342 = (uint16_t)(108); + _curvea0[202] = _13342; + uint16_t _13343 = (uint16_t)(108); + _curvea0[203] = _13343; + uint16_t _13344 = (uint16_t)(109); + _curvea0[204] = _13344; + uint16_t _13345 = (uint16_t)(109); + _curvea0[205] = _13345; + uint16_t _13346 = (uint16_t)(109); + _curvea0[206] = _13346; + uint16_t _13347 = (uint16_t)(110); + _curvea0[207] = _13347; + uint16_t _13348 = (uint16_t)(110); + _curvea0[208] = _13348; + uint16_t _13349 = (uint16_t)(111); + _curvea0[209] = _13349; + uint16_t _13350 = (uint16_t)(111); + _curvea0[210] = _13350; + uint16_t _13351 = (uint16_t)(111); + _curvea0[211] = _13351; + uint16_t _13352 = (uint16_t)(112); + _curvea0[212] = _13352; + uint16_t _13353 = (uint16_t)(112); + _curvea0[213] = _13353; + uint16_t _13354 = (uint16_t)(112); + _curvea0[214] = _13354; + uint16_t _13355 = (uint16_t)(113); + _curvea0[215] = _13355; + uint16_t _13356 = (uint16_t)(113); + _curvea0[216] = _13356; + uint16_t _13357 = (uint16_t)(113); + _curvea0[217] = _13357; + uint16_t _13358 = (uint16_t)(114); + _curvea0[218] = _13358; + uint16_t _13359 = (uint16_t)(114); + _curvea0[219] = _13359; + uint16_t _13360 = (uint16_t)(115); + _curvea0[220] = _13360; + uint16_t _13361 = (uint16_t)(115); + _curvea0[221] = _13361; + uint16_t _13362 = (uint16_t)(115); + _curvea0[222] = _13362; + uint16_t _13363 = (uint16_t)(116); + _curvea0[223] = _13363; + uint16_t _13364 = (uint16_t)(116); + _curvea0[224] = _13364; + uint16_t _13365 = (uint16_t)(116); + _curvea0[225] = _13365; + uint16_t _13366 = (uint16_t)(117); + _curvea0[226] = _13366; + uint16_t _13367 = (uint16_t)(117); + _curvea0[227] = _13367; + uint16_t _13368 = (uint16_t)(117); + _curvea0[228] = _13368; + uint16_t _13369 = (uint16_t)(118); + _curvea0[229] = _13369; + uint16_t _13370 = (uint16_t)(118); + _curvea0[230] = _13370; + uint16_t _13371 = (uint16_t)(119); + _curvea0[231] = _13371; + uint16_t _13372 = (uint16_t)(119); + _curvea0[232] = _13372; + uint16_t _13373 = (uint16_t)(119); + _curvea0[233] = _13373; + uint16_t _13374 = (uint16_t)(120); + _curvea0[234] = _13374; + uint16_t _13375 = (uint16_t)(120); + _curvea0[235] = _13375; + uint16_t _13376 = (uint16_t)(120); + _curvea0[236] = _13376; + uint16_t _13377 = (uint16_t)(121); + _curvea0[237] = _13377; + uint16_t _13378 = (uint16_t)(121); + _curvea0[238] = _13378; + uint16_t _13379 = (uint16_t)(121); + _curvea0[239] = _13379; + uint16_t _13380 = (uint16_t)(122); + _curvea0[240] = _13380; + uint16_t _13381 = (uint16_t)(122); + _curvea0[241] = _13381; + uint16_t _13382 = (uint16_t)(123); + _curvea0[242] = _13382; + uint16_t _13383 = (uint16_t)(123); + _curvea0[243] = _13383; + uint16_t _13384 = (uint16_t)(123); + _curvea0[244] = _13384; + uint16_t _13385 = (uint16_t)(124); + _curvea0[245] = _13385; + uint16_t _13386 = (uint16_t)(124); + _curvea0[246] = _13386; + uint16_t _13387 = (uint16_t)(124); + _curvea0[247] = _13387; + uint16_t _13388 = (uint16_t)(125); + _curvea0[248] = _13388; + uint16_t _13389 = (uint16_t)(125); + _curvea0[249] = _13389; + uint16_t _13390 = (uint16_t)(125); + _curvea0[250] = _13390; + uint16_t _13391 = (uint16_t)(126); + _curvea0[251] = _13391; + uint16_t _13392 = (uint16_t)(126); + _curvea0[252] = _13392; + uint16_t _13393 = (uint16_t)(126); + _curvea0[253] = _13393; + uint16_t _13394 = (uint16_t)(127); + _curvea0[254] = _13394; + uint16_t _13395 = (uint16_t)(127); + _curvea0[255] = _13395; + uint16_t _13396 = (uint16_t)(128); + _curvea0[256] = _13396; + uint16_t _13397 = (uint16_t)(128); + _curvea0[257] = _13397; + uint16_t _13398 = (uint16_t)(128); + _curvea0[258] = _13398; + uint16_t _13399 = (uint16_t)(129); + _curvea0[259] = _13399; + uint16_t _13400 = (uint16_t)(129); + _curvea0[260] = _13400; + uint16_t _13401 = (uint16_t)(129); + _curvea0[261] = _13401; + uint16_t _13402 = (uint16_t)(130); + _curvea0[262] = _13402; + uint16_t _13403 = (uint16_t)(130); + _curvea0[263] = _13403; + uint16_t _13404 = (uint16_t)(130); + _curvea0[264] = _13404; + uint16_t _13405 = (uint16_t)(131); + _curvea0[265] = _13405; + uint16_t _13406 = (uint16_t)(131); + _curvea0[266] = _13406; + uint16_t _13407 = (uint16_t)(131); + _curvea0[267] = _13407; + uint16_t _13408 = (uint16_t)(132); + _curvea0[268] = _13408; + uint16_t _13409 = (uint16_t)(132); + _curvea0[269] = _13409; + uint16_t _13410 = (uint16_t)(132); + _curvea0[270] = _13410; + uint16_t _13411 = (uint16_t)(133); + _curvea0[271] = _13411; + uint16_t _13412 = (uint16_t)(133); + _curvea0[272] = _13412; + uint16_t _13413 = (uint16_t)(133); + _curvea0[273] = _13413; + uint16_t _13414 = (uint16_t)(134); + _curvea0[274] = _13414; + uint16_t _13415 = (uint16_t)(134); + _curvea0[275] = _13415; + uint16_t _13416 = (uint16_t)(134); + _curvea0[276] = _13416; + uint16_t _13417 = (uint16_t)(135); + _curvea0[277] = _13417; + uint16_t _13418 = (uint16_t)(135); + _curvea0[278] = _13418; + uint16_t _13419 = (uint16_t)(135); + _curvea0[279] = _13419; + uint16_t _13420 = (uint16_t)(136); + _curvea0[280] = _13420; + uint16_t _13421 = (uint16_t)(136); + _curvea0[281] = _13421; + uint16_t _13422 = (uint16_t)(136); + _curvea0[282] = _13422; + uint16_t _13423 = (uint16_t)(137); + _curvea0[283] = _13423; + uint16_t _13424 = (uint16_t)(137); + _curvea0[284] = _13424; + uint16_t _13425 = (uint16_t)(137); + _curvea0[285] = _13425; + uint16_t _13426 = (uint16_t)(138); + _curvea0[286] = _13426; + uint16_t _13427 = (uint16_t)(138); + _curvea0[287] = _13427; + uint16_t _13428 = (uint16_t)(138); + _curvea0[288] = _13428; + uint16_t _13429 = (uint16_t)(139); + _curvea0[289] = _13429; + uint16_t _13430 = (uint16_t)(139); + _curvea0[290] = _13430; + uint16_t _13431 = (uint16_t)(139); + _curvea0[291] = _13431; + uint16_t _13432 = (uint16_t)(140); + _curvea0[292] = _13432; + uint16_t _13433 = (uint16_t)(140); + _curvea0[293] = _13433; + uint16_t _13434 = (uint16_t)(140); + _curvea0[294] = _13434; + uint16_t _13435 = (uint16_t)(141); + _curvea0[295] = _13435; + uint16_t _13436 = (uint16_t)(141); + _curvea0[296] = _13436; + uint16_t _13437 = (uint16_t)(141); + _curvea0[297] = _13437; + uint16_t _13438 = (uint16_t)(141); + _curvea0[298] = _13438; + uint16_t _13439 = (uint16_t)(142); + _curvea0[299] = _13439; + uint16_t _13440 = (uint16_t)(142); + _curvea0[300] = _13440; + uint16_t _13441 = (uint16_t)(142); + _curvea0[301] = _13441; + uint16_t _13442 = (uint16_t)(143); + _curvea0[302] = _13442; + uint16_t _13443 = (uint16_t)(143); + _curvea0[303] = _13443; + uint16_t _13444 = (uint16_t)(143); + _curvea0[304] = _13444; + uint16_t _13445 = (uint16_t)(144); + _curvea0[305] = _13445; + uint16_t _13446 = (uint16_t)(144); + _curvea0[306] = _13446; + uint16_t _13447 = (uint16_t)(144); + _curvea0[307] = _13447; + uint16_t _13448 = (uint16_t)(145); + _curvea0[308] = _13448; + uint16_t _13449 = (uint16_t)(145); + _curvea0[309] = _13449; + uint16_t _13450 = (uint16_t)(145); + _curvea0[310] = _13450; + uint16_t _13451 = (uint16_t)(145); + _curvea0[311] = _13451; + uint16_t _13452 = (uint16_t)(146); + _curvea0[312] = _13452; + uint16_t _13453 = (uint16_t)(146); + _curvea0[313] = _13453; + uint16_t _13454 = (uint16_t)(146); + _curvea0[314] = _13454; + uint16_t _13455 = (uint16_t)(147); + _curvea0[315] = _13455; + uint16_t _13456 = (uint16_t)(147); + _curvea0[316] = _13456; + uint16_t _13457 = (uint16_t)(147); + _curvea0[317] = _13457; + uint16_t _13458 = (uint16_t)(148); + _curvea0[318] = _13458; + uint16_t _13459 = (uint16_t)(148); + _curvea0[319] = _13459; + uint16_t _13460 = (uint16_t)(148); + _curvea0[320] = _13460; + uint16_t _13461 = (uint16_t)(148); + _curvea0[321] = _13461; + uint16_t _13462 = (uint16_t)(149); + _curvea0[322] = _13462; + uint16_t _13463 = (uint16_t)(149); + _curvea0[323] = _13463; + uint16_t _13464 = (uint16_t)(149); + _curvea0[324] = _13464; + uint16_t _13465 = (uint16_t)(150); + _curvea0[325] = _13465; + uint16_t _13466 = (uint16_t)(150); + _curvea0[326] = _13466; + uint16_t _13467 = (uint16_t)(150); + _curvea0[327] = _13467; + uint16_t _13468 = (uint16_t)(150); + _curvea0[328] = _13468; + uint16_t _13469 = (uint16_t)(151); + _curvea0[329] = _13469; + uint16_t _13470 = (uint16_t)(151); + _curvea0[330] = _13470; + uint16_t _13471 = (uint16_t)(151); + _curvea0[331] = _13471; + uint16_t _13472 = (uint16_t)(152); + _curvea0[332] = _13472; + uint16_t _13473 = (uint16_t)(152); + _curvea0[333] = _13473; + uint16_t _13474 = (uint16_t)(152); + _curvea0[334] = _13474; + uint16_t _13475 = (uint16_t)(152); + _curvea0[335] = _13475; + uint16_t _13476 = (uint16_t)(153); + _curvea0[336] = _13476; + uint16_t _13477 = (uint16_t)(153); + _curvea0[337] = _13477; + uint16_t _13478 = (uint16_t)(153); + _curvea0[338] = _13478; + uint16_t _13479 = (uint16_t)(154); + _curvea0[339] = _13479; + uint16_t _13480 = (uint16_t)(154); + _curvea0[340] = _13480; + uint16_t _13481 = (uint16_t)(154); + _curvea0[341] = _13481; + uint16_t _13482 = (uint16_t)(154); + _curvea0[342] = _13482; + uint16_t _13483 = (uint16_t)(155); + _curvea0[343] = _13483; + uint16_t _13484 = (uint16_t)(155); + _curvea0[344] = _13484; + uint16_t _13485 = (uint16_t)(155); + _curvea0[345] = _13485; + uint16_t _13486 = (uint16_t)(156); + _curvea0[346] = _13486; + uint16_t _13487 = (uint16_t)(156); + _curvea0[347] = _13487; + uint16_t _13488 = (uint16_t)(156); + _curvea0[348] = _13488; + uint16_t _13489 = (uint16_t)(156); + _curvea0[349] = _13489; + uint16_t _13490 = (uint16_t)(157); + _curvea0[350] = _13490; + uint16_t _13491 = (uint16_t)(157); + _curvea0[351] = _13491; + uint16_t _13492 = (uint16_t)(157); + _curvea0[352] = _13492; + uint16_t _13493 = (uint16_t)(157); + _curvea0[353] = _13493; + uint16_t _13494 = (uint16_t)(158); + _curvea0[354] = _13494; + uint16_t _13495 = (uint16_t)(158); + _curvea0[355] = _13495; + uint16_t _13496 = (uint16_t)(158); + _curvea0[356] = _13496; + uint16_t _13497 = (uint16_t)(159); + _curvea0[357] = _13497; + uint16_t _13498 = (uint16_t)(159); + _curvea0[358] = _13498; + uint16_t _13499 = (uint16_t)(159); + _curvea0[359] = _13499; + uint16_t _13500 = (uint16_t)(159); + _curvea0[360] = _13500; + uint16_t _13501 = (uint16_t)(160); + _curvea0[361] = _13501; + uint16_t _13502 = (uint16_t)(160); + _curvea0[362] = _13502; + uint16_t _13503 = (uint16_t)(160); + _curvea0[363] = _13503; + uint16_t _13504 = (uint16_t)(160); + _curvea0[364] = _13504; + uint16_t _13505 = (uint16_t)(161); + _curvea0[365] = _13505; + uint16_t _13506 = (uint16_t)(161); + _curvea0[366] = _13506; + uint16_t _13507 = (uint16_t)(161); + _curvea0[367] = _13507; + uint16_t _13508 = (uint16_t)(161); + _curvea0[368] = _13508; + uint16_t _13509 = (uint16_t)(162); + _curvea0[369] = _13509; + uint16_t _13510 = (uint16_t)(162); + _curvea0[370] = _13510; + uint16_t _13511 = (uint16_t)(162); + _curvea0[371] = _13511; + uint16_t _13512 = (uint16_t)(162); + _curvea0[372] = _13512; + uint16_t _13513 = (uint16_t)(163); + _curvea0[373] = _13513; + uint16_t _13514 = (uint16_t)(163); + _curvea0[374] = _13514; + uint16_t _13515 = (uint16_t)(163); + _curvea0[375] = _13515; + uint16_t _13516 = (uint16_t)(163); + _curvea0[376] = _13516; + uint16_t _13517 = (uint16_t)(164); + _curvea0[377] = _13517; + uint16_t _13518 = (uint16_t)(164); + _curvea0[378] = _13518; + uint16_t _13519 = (uint16_t)(164); + _curvea0[379] = _13519; + uint16_t _13520 = (uint16_t)(164); + _curvea0[380] = _13520; + uint16_t _13521 = (uint16_t)(165); + _curvea0[381] = _13521; + uint16_t _13522 = (uint16_t)(165); + _curvea0[382] = _13522; + uint16_t _13523 = (uint16_t)(165); + _curvea0[383] = _13523; + uint16_t _13524 = (uint16_t)(166); + _curvea0[384] = _13524; + uint16_t _13525 = (uint16_t)(166); + _curvea0[385] = _13525; + uint16_t _13526 = (uint16_t)(166); + _curvea0[386] = _13526; + uint16_t _13527 = (uint16_t)(166); + _curvea0[387] = _13527; + uint16_t _13528 = (uint16_t)(167); + _curvea0[388] = _13528; + uint16_t _13529 = (uint16_t)(167); + _curvea0[389] = _13529; + uint16_t _13530 = (uint16_t)(167); + _curvea0[390] = _13530; + uint16_t _13531 = (uint16_t)(167); + _curvea0[391] = _13531; + uint16_t _13532 = (uint16_t)(167); + _curvea0[392] = _13532; + uint16_t _13533 = (uint16_t)(168); + _curvea0[393] = _13533; + uint16_t _13534 = (uint16_t)(168); + _curvea0[394] = _13534; + uint16_t _13535 = (uint16_t)(168); + _curvea0[395] = _13535; + uint16_t _13536 = (uint16_t)(168); + _curvea0[396] = _13536; + uint16_t _13537 = (uint16_t)(169); + _curvea0[397] = _13537; + uint16_t _13538 = (uint16_t)(169); + _curvea0[398] = _13538; + uint16_t _13539 = (uint16_t)(169); + _curvea0[399] = _13539; + uint16_t _13540 = (uint16_t)(169); + _curvea0[400] = _13540; + uint16_t _13541 = (uint16_t)(170); + _curvea0[401] = _13541; + uint16_t _13542 = (uint16_t)(170); + _curvea0[402] = _13542; + uint16_t _13543 = (uint16_t)(170); + _curvea0[403] = _13543; + uint16_t _13544 = (uint16_t)(170); + _curvea0[404] = _13544; + uint16_t _13545 = (uint16_t)(171); + _curvea0[405] = _13545; + uint16_t _13546 = (uint16_t)(171); + _curvea0[406] = _13546; + uint16_t _13547 = (uint16_t)(171); + _curvea0[407] = _13547; + uint16_t _13548 = (uint16_t)(171); + _curvea0[408] = _13548; + uint16_t _13549 = (uint16_t)(172); + _curvea0[409] = _13549; + uint16_t _13550 = (uint16_t)(172); + _curvea0[410] = _13550; + uint16_t _13551 = (uint16_t)(172); + _curvea0[411] = _13551; + uint16_t _13552 = (uint16_t)(172); + _curvea0[412] = _13552; + uint16_t _13553 = (uint16_t)(173); + _curvea0[413] = _13553; + uint16_t _13554 = (uint16_t)(173); + _curvea0[414] = _13554; + uint16_t _13555 = (uint16_t)(173); + _curvea0[415] = _13555; + uint16_t _13556 = (uint16_t)(173); + _curvea0[416] = _13556; + uint16_t _13557 = (uint16_t)(173); + _curvea0[417] = _13557; + uint16_t _13558 = (uint16_t)(174); + _curvea0[418] = _13558; + uint16_t _13559 = (uint16_t)(174); + _curvea0[419] = _13559; + uint16_t _13560 = (uint16_t)(174); + _curvea0[420] = _13560; + uint16_t _13561 = (uint16_t)(174); + _curvea0[421] = _13561; + uint16_t _13562 = (uint16_t)(175); + _curvea0[422] = _13562; + uint16_t _13563 = (uint16_t)(175); + _curvea0[423] = _13563; + uint16_t _13564 = (uint16_t)(175); + _curvea0[424] = _13564; + uint16_t _13565 = (uint16_t)(175); + _curvea0[425] = _13565; + uint16_t _13566 = (uint16_t)(176); + _curvea0[426] = _13566; + uint16_t _13567 = (uint16_t)(176); + _curvea0[427] = _13567; + uint16_t _13568 = (uint16_t)(176); + _curvea0[428] = _13568; + uint16_t _13569 = (uint16_t)(176); + _curvea0[429] = _13569; + uint16_t _13570 = (uint16_t)(176); + _curvea0[430] = _13570; + uint16_t _13571 = (uint16_t)(177); + _curvea0[431] = _13571; + uint16_t _13572 = (uint16_t)(177); + _curvea0[432] = _13572; + uint16_t _13573 = (uint16_t)(177); + _curvea0[433] = _13573; + uint16_t _13574 = (uint16_t)(177); + _curvea0[434] = _13574; + uint16_t _13575 = (uint16_t)(178); + _curvea0[435] = _13575; + uint16_t _13576 = (uint16_t)(178); + _curvea0[436] = _13576; + uint16_t _13577 = (uint16_t)(178); + _curvea0[437] = _13577; + uint16_t _13578 = (uint16_t)(178); + _curvea0[438] = _13578; + uint16_t _13579 = (uint16_t)(178); + _curvea0[439] = _13579; + uint16_t _13580 = (uint16_t)(179); + _curvea0[440] = _13580; + uint16_t _13581 = (uint16_t)(179); + _curvea0[441] = _13581; + uint16_t _13582 = (uint16_t)(179); + _curvea0[442] = _13582; + uint16_t _13583 = (uint16_t)(179); + _curvea0[443] = _13583; + uint16_t _13584 = (uint16_t)(180); + _curvea0[444] = _13584; + uint16_t _13585 = (uint16_t)(180); + _curvea0[445] = _13585; + uint16_t _13586 = (uint16_t)(180); + _curvea0[446] = _13586; + uint16_t _13587 = (uint16_t)(180); + _curvea0[447] = _13587; + uint16_t _13588 = (uint16_t)(180); + _curvea0[448] = _13588; + uint16_t _13589 = (uint16_t)(181); + _curvea0[449] = _13589; + uint16_t _13590 = (uint16_t)(181); + _curvea0[450] = _13590; + uint16_t _13591 = (uint16_t)(181); + _curvea0[451] = _13591; + uint16_t _13592 = (uint16_t)(181); + _curvea0[452] = _13592; + uint16_t _13593 = (uint16_t)(181); + _curvea0[453] = _13593; + uint16_t _13594 = (uint16_t)(182); + _curvea0[454] = _13594; + uint16_t _13595 = (uint16_t)(182); + _curvea0[455] = _13595; + uint16_t _13596 = (uint16_t)(182); + _curvea0[456] = _13596; + uint16_t _13597 = (uint16_t)(182); + _curvea0[457] = _13597; + uint16_t _13598 = (uint16_t)(183); + _curvea0[458] = _13598; + uint16_t _13599 = (uint16_t)(183); + _curvea0[459] = _13599; + uint16_t _13600 = (uint16_t)(183); + _curvea0[460] = _13600; + uint16_t _13601 = (uint16_t)(183); + _curvea0[461] = _13601; + uint16_t _13602 = (uint16_t)(183); + _curvea0[462] = _13602; + uint16_t _13603 = (uint16_t)(184); + _curvea0[463] = _13603; + uint16_t _13604 = (uint16_t)(184); + _curvea0[464] = _13604; + uint16_t _13605 = (uint16_t)(184); + _curvea0[465] = _13605; + uint16_t _13606 = (uint16_t)(184); + _curvea0[466] = _13606; + uint16_t _13607 = (uint16_t)(184); + _curvea0[467] = _13607; + uint16_t _13608 = (uint16_t)(185); + _curvea0[468] = _13608; + uint16_t _13609 = (uint16_t)(185); + _curvea0[469] = _13609; + uint16_t _13610 = (uint16_t)(185); + _curvea0[470] = _13610; + uint16_t _13611 = (uint16_t)(185); + _curvea0[471] = _13611; + uint16_t _13612 = (uint16_t)(185); + _curvea0[472] = _13612; + uint16_t _13613 = (uint16_t)(186); + _curvea0[473] = _13613; + uint16_t _13614 = (uint16_t)(186); + _curvea0[474] = _13614; + uint16_t _13615 = (uint16_t)(186); + _curvea0[475] = _13615; + uint16_t _13616 = (uint16_t)(186); + _curvea0[476] = _13616; + uint16_t _13617 = (uint16_t)(187); + _curvea0[477] = _13617; + uint16_t _13618 = (uint16_t)(187); + _curvea0[478] = _13618; + uint16_t _13619 = (uint16_t)(187); + _curvea0[479] = _13619; + uint16_t _13620 = (uint16_t)(187); + _curvea0[480] = _13620; + uint16_t _13621 = (uint16_t)(187); + _curvea0[481] = _13621; + uint16_t _13622 = (uint16_t)(188); + _curvea0[482] = _13622; + uint16_t _13623 = (uint16_t)(188); + _curvea0[483] = _13623; + uint16_t _13624 = (uint16_t)(188); + _curvea0[484] = _13624; + uint16_t _13625 = (uint16_t)(188); + _curvea0[485] = _13625; + uint16_t _13626 = (uint16_t)(188); + _curvea0[486] = _13626; + uint16_t _13627 = (uint16_t)(189); + _curvea0[487] = _13627; + uint16_t _13628 = (uint16_t)(189); + _curvea0[488] = _13628; + uint16_t _13629 = (uint16_t)(189); + _curvea0[489] = _13629; + uint16_t _13630 = (uint16_t)(189); + _curvea0[490] = _13630; + uint16_t _13631 = (uint16_t)(189); + _curvea0[491] = _13631; + uint16_t _13632 = (uint16_t)(190); + _curvea0[492] = _13632; + uint16_t _13633 = (uint16_t)(190); + _curvea0[493] = _13633; + uint16_t _13634 = (uint16_t)(190); + _curvea0[494] = _13634; + uint16_t _13635 = (uint16_t)(190); + _curvea0[495] = _13635; + uint16_t _13636 = (uint16_t)(190); + _curvea0[496] = _13636; + uint16_t _13637 = (uint16_t)(190); + _curvea0[497] = _13637; + uint16_t _13638 = (uint16_t)(191); + _curvea0[498] = _13638; + uint16_t _13639 = (uint16_t)(191); + _curvea0[499] = _13639; + uint16_t _13640 = (uint16_t)(191); + _curvea0[500] = _13640; + uint16_t _13641 = (uint16_t)(191); + _curvea0[501] = _13641; + uint16_t _13642 = (uint16_t)(191); + _curvea0[502] = _13642; + uint16_t _13643 = (uint16_t)(192); + _curvea0[503] = _13643; + uint16_t _13644 = (uint16_t)(192); + _curvea0[504] = _13644; + uint16_t _13645 = (uint16_t)(192); + _curvea0[505] = _13645; + uint16_t _13646 = (uint16_t)(192); + _curvea0[506] = _13646; + uint16_t _13647 = (uint16_t)(192); + _curvea0[507] = _13647; + uint16_t _13648 = (uint16_t)(193); + _curvea0[508] = _13648; + uint16_t _13649 = (uint16_t)(193); + _curvea0[509] = _13649; + uint16_t _13650 = (uint16_t)(193); + _curvea0[510] = _13650; + uint16_t _13651 = (uint16_t)(193); + _curvea0[511] = _13651; + uint16_t _13652 = (uint16_t)(193); + _curvea0[512] = _13652; + uint16_t _13653 = (uint16_t)(194); + _curvea0[513] = _13653; + uint16_t _13654 = (uint16_t)(194); + _curvea0[514] = _13654; + uint16_t _13655 = (uint16_t)(194); + _curvea0[515] = _13655; + uint16_t _13656 = (uint16_t)(194); + _curvea0[516] = _13656; + uint16_t _13657 = (uint16_t)(194); + _curvea0[517] = _13657; + uint16_t _13658 = (uint16_t)(195); + _curvea0[518] = _13658; + uint16_t _13659 = (uint16_t)(195); + _curvea0[519] = _13659; + uint16_t _13660 = (uint16_t)(195); + _curvea0[520] = _13660; + uint16_t _13661 = (uint16_t)(195); + _curvea0[521] = _13661; + uint16_t _13662 = (uint16_t)(195); + _curvea0[522] = _13662; + uint16_t _13663 = (uint16_t)(195); + _curvea0[523] = _13663; + uint16_t _13664 = (uint16_t)(196); + _curvea0[524] = _13664; + uint16_t _13665 = (uint16_t)(196); + _curvea0[525] = _13665; + uint16_t _13666 = (uint16_t)(196); + _curvea0[526] = _13666; + uint16_t _13667 = (uint16_t)(196); + _curvea0[527] = _13667; + uint16_t _13668 = (uint16_t)(196); + _curvea0[528] = _13668; + uint16_t _13669 = (uint16_t)(197); + _curvea0[529] = _13669; + uint16_t _13670 = (uint16_t)(197); + _curvea0[530] = _13670; + uint16_t _13671 = (uint16_t)(197); + _curvea0[531] = _13671; + uint16_t _13672 = (uint16_t)(197); + _curvea0[532] = _13672; + uint16_t _13673 = (uint16_t)(197); + _curvea0[533] = _13673; + uint16_t _13674 = (uint16_t)(197); + _curvea0[534] = _13674; + uint16_t _13675 = (uint16_t)(198); + _curvea0[535] = _13675; + uint16_t _13676 = (uint16_t)(198); + _curvea0[536] = _13676; + uint16_t _13677 = (uint16_t)(198); + _curvea0[537] = _13677; + uint16_t _13678 = (uint16_t)(198); + _curvea0[538] = _13678; + uint16_t _13679 = (uint16_t)(198); + _curvea0[539] = _13679; + uint16_t _13680 = (uint16_t)(199); + _curvea0[540] = _13680; + uint16_t _13681 = (uint16_t)(199); + _curvea0[541] = _13681; + uint16_t _13682 = (uint16_t)(199); + _curvea0[542] = _13682; + uint16_t _13683 = (uint16_t)(199); + _curvea0[543] = _13683; + uint16_t _13684 = (uint16_t)(199); + _curvea0[544] = _13684; + uint16_t _13685 = (uint16_t)(199); + _curvea0[545] = _13685; + uint16_t _13686 = (uint16_t)(200); + _curvea0[546] = _13686; + uint16_t _13687 = (uint16_t)(200); + _curvea0[547] = _13687; + uint16_t _13688 = (uint16_t)(200); + _curvea0[548] = _13688; + uint16_t _13689 = (uint16_t)(200); + _curvea0[549] = _13689; + uint16_t _13690 = (uint16_t)(200); + _curvea0[550] = _13690; + uint16_t _13691 = (uint16_t)(200); + _curvea0[551] = _13691; + uint16_t _13692 = (uint16_t)(201); + _curvea0[552] = _13692; + uint16_t _13693 = (uint16_t)(201); + _curvea0[553] = _13693; + uint16_t _13694 = (uint16_t)(201); + _curvea0[554] = _13694; + uint16_t _13695 = (uint16_t)(201); + _curvea0[555] = _13695; + uint16_t _13696 = (uint16_t)(201); + _curvea0[556] = _13696; + uint16_t _13697 = (uint16_t)(202); + _curvea0[557] = _13697; + uint16_t _13698 = (uint16_t)(202); + _curvea0[558] = _13698; + uint16_t _13699 = (uint16_t)(202); + _curvea0[559] = _13699; + uint16_t _13700 = (uint16_t)(202); + _curvea0[560] = _13700; + uint16_t _13701 = (uint16_t)(202); + _curvea0[561] = _13701; + uint16_t _13702 = (uint16_t)(202); + _curvea0[562] = _13702; + uint16_t _13703 = (uint16_t)(203); + _curvea0[563] = _13703; + uint16_t _13704 = (uint16_t)(203); + _curvea0[564] = _13704; + uint16_t _13705 = (uint16_t)(203); + _curvea0[565] = _13705; + uint16_t _13706 = (uint16_t)(203); + _curvea0[566] = _13706; + uint16_t _13707 = (uint16_t)(203); + _curvea0[567] = _13707; + uint16_t _13708 = (uint16_t)(203); + _curvea0[568] = _13708; + uint16_t _13709 = (uint16_t)(204); + _curvea0[569] = _13709; + uint16_t _13710 = (uint16_t)(204); + _curvea0[570] = _13710; + uint16_t _13711 = (uint16_t)(204); + _curvea0[571] = _13711; + uint16_t _13712 = (uint16_t)(204); + _curvea0[572] = _13712; + uint16_t _13713 = (uint16_t)(204); + _curvea0[573] = _13713; + uint16_t _13714 = (uint16_t)(204); + _curvea0[574] = _13714; + uint16_t _13715 = (uint16_t)(205); + _curvea0[575] = _13715; + uint16_t _13716 = (uint16_t)(205); + _curvea0[576] = _13716; + uint16_t _13717 = (uint16_t)(205); + _curvea0[577] = _13717; + uint16_t _13718 = (uint16_t)(205); + _curvea0[578] = _13718; + uint16_t _13719 = (uint16_t)(205); + _curvea0[579] = _13719; + uint16_t _13720 = (uint16_t)(205); + _curvea0[580] = _13720; + uint16_t _13721 = (uint16_t)(206); + _curvea0[581] = _13721; + uint16_t _13722 = (uint16_t)(206); + _curvea0[582] = _13722; + uint16_t _13723 = (uint16_t)(206); + _curvea0[583] = _13723; + uint16_t _13724 = (uint16_t)(206); + _curvea0[584] = _13724; + uint16_t _13725 = (uint16_t)(206); + _curvea0[585] = _13725; + uint16_t _13726 = (uint16_t)(206); + _curvea0[586] = _13726; + uint16_t _13727 = (uint16_t)(207); + _curvea0[587] = _13727; + uint16_t _13728 = (uint16_t)(207); + _curvea0[588] = _13728; + uint16_t _13729 = (uint16_t)(207); + _curvea0[589] = _13729; + uint16_t _13730 = (uint16_t)(207); + _curvea0[590] = _13730; + uint16_t _13731 = (uint16_t)(207); + _curvea0[591] = _13731; + uint16_t _13732 = (uint16_t)(207); + _curvea0[592] = _13732; + uint16_t _13733 = (uint16_t)(208); + _curvea0[593] = _13733; + uint16_t _13734 = (uint16_t)(208); + _curvea0[594] = _13734; + uint16_t _13735 = (uint16_t)(208); + _curvea0[595] = _13735; + uint16_t _13736 = (uint16_t)(208); + _curvea0[596] = _13736; + uint16_t _13737 = (uint16_t)(208); + _curvea0[597] = _13737; + uint16_t _13738 = (uint16_t)(208); + _curvea0[598] = _13738; + uint16_t _13739 = (uint16_t)(209); + _curvea0[599] = _13739; + uint16_t _13740 = (uint16_t)(209); + _curvea0[600] = _13740; + uint16_t _13741 = (uint16_t)(209); + _curvea0[601] = _13741; + uint16_t _13742 = (uint16_t)(209); + _curvea0[602] = _13742; + uint16_t _13743 = (uint16_t)(209); + _curvea0[603] = _13743; + uint16_t _13744 = (uint16_t)(209); + _curvea0[604] = _13744; + uint16_t _13745 = (uint16_t)(209); + _curvea0[605] = _13745; + uint16_t _13746 = (uint16_t)(210); + _curvea0[606] = _13746; + uint16_t _13747 = (uint16_t)(210); + _curvea0[607] = _13747; + uint16_t _13748 = (uint16_t)(210); + _curvea0[608] = _13748; + uint16_t _13749 = (uint16_t)(210); + _curvea0[609] = _13749; + uint16_t _13750 = (uint16_t)(210); + _curvea0[610] = _13750; + uint16_t _13751 = (uint16_t)(210); + _curvea0[611] = _13751; + uint16_t _13752 = (uint16_t)(211); + _curvea0[612] = _13752; + uint16_t _13753 = (uint16_t)(211); + _curvea0[613] = _13753; + uint16_t _13754 = (uint16_t)(211); + _curvea0[614] = _13754; + uint16_t _13755 = (uint16_t)(211); + _curvea0[615] = _13755; + uint16_t _13756 = (uint16_t)(211); + _curvea0[616] = _13756; + uint16_t _13757 = (uint16_t)(211); + _curvea0[617] = _13757; + uint16_t _13758 = (uint16_t)(211); + _curvea0[618] = _13758; + uint16_t _13759 = (uint16_t)(212); + _curvea0[619] = _13759; + uint16_t _13760 = (uint16_t)(212); + _curvea0[620] = _13760; + uint16_t _13761 = (uint16_t)(212); + _curvea0[621] = _13761; + uint16_t _13762 = (uint16_t)(212); + _curvea0[622] = _13762; + uint16_t _13763 = (uint16_t)(212); + _curvea0[623] = _13763; + uint16_t _13764 = (uint16_t)(212); + _curvea0[624] = _13764; + uint16_t _13765 = (uint16_t)(213); + _curvea0[625] = _13765; + uint16_t _13766 = (uint16_t)(213); + _curvea0[626] = _13766; + uint16_t _13767 = (uint16_t)(213); + _curvea0[627] = _13767; + uint16_t _13768 = (uint16_t)(213); + _curvea0[628] = _13768; + uint16_t _13769 = (uint16_t)(213); + _curvea0[629] = _13769; + uint16_t _13770 = (uint16_t)(213); + _curvea0[630] = _13770; + uint16_t _13771 = (uint16_t)(213); + _curvea0[631] = _13771; + uint16_t _13772 = (uint16_t)(214); + _curvea0[632] = _13772; + uint16_t _13773 = (uint16_t)(214); + _curvea0[633] = _13773; + uint16_t _13774 = (uint16_t)(214); + _curvea0[634] = _13774; + uint16_t _13775 = (uint16_t)(214); + _curvea0[635] = _13775; + uint16_t _13776 = (uint16_t)(214); + _curvea0[636] = _13776; + uint16_t _13777 = (uint16_t)(214); + _curvea0[637] = _13777; + uint16_t _13778 = (uint16_t)(214); + _curvea0[638] = _13778; + uint16_t _13779 = (uint16_t)(215); + _curvea0[639] = _13779; + uint16_t _13780 = (uint16_t)(215); + _curvea0[640] = _13780; + uint16_t _13781 = (uint16_t)(215); + _curvea0[641] = _13781; + uint16_t _13782 = (uint16_t)(215); + _curvea0[642] = _13782; + uint16_t _13783 = (uint16_t)(215); + _curvea0[643] = _13783; + uint16_t _13784 = (uint16_t)(215); + _curvea0[644] = _13784; + uint16_t _13785 = (uint16_t)(216); + _curvea0[645] = _13785; + uint16_t _13786 = (uint16_t)(216); + _curvea0[646] = _13786; + uint16_t _13787 = (uint16_t)(216); + _curvea0[647] = _13787; + uint16_t _13788 = (uint16_t)(216); + _curvea0[648] = _13788; + uint16_t _13789 = (uint16_t)(216); + _curvea0[649] = _13789; + uint16_t _13790 = (uint16_t)(216); + _curvea0[650] = _13790; + uint16_t _13791 = (uint16_t)(216); + _curvea0[651] = _13791; + uint16_t _13792 = (uint16_t)(217); + _curvea0[652] = _13792; + uint16_t _13793 = (uint16_t)(217); + _curvea0[653] = _13793; + uint16_t _13794 = (uint16_t)(217); + _curvea0[654] = _13794; + uint16_t _13795 = (uint16_t)(217); + _curvea0[655] = _13795; + uint16_t _13796 = (uint16_t)(217); + _curvea0[656] = _13796; + uint16_t _13797 = (uint16_t)(217); + _curvea0[657] = _13797; + uint16_t _13798 = (uint16_t)(217); + _curvea0[658] = _13798; + uint16_t _13799 = (uint16_t)(218); + _curvea0[659] = _13799; + uint16_t _13800 = (uint16_t)(218); + _curvea0[660] = _13800; + uint16_t _13801 = (uint16_t)(218); + _curvea0[661] = _13801; + uint16_t _13802 = (uint16_t)(218); + _curvea0[662] = _13802; + uint16_t _13803 = (uint16_t)(218); + _curvea0[663] = _13803; + uint16_t _13804 = (uint16_t)(218); + _curvea0[664] = _13804; + uint16_t _13805 = (uint16_t)(218); + _curvea0[665] = _13805; + uint16_t _13806 = (uint16_t)(219); + _curvea0[666] = _13806; + uint16_t _13807 = (uint16_t)(219); + _curvea0[667] = _13807; + uint16_t _13808 = (uint16_t)(219); + _curvea0[668] = _13808; + uint16_t _13809 = (uint16_t)(219); + _curvea0[669] = _13809; + uint16_t _13810 = (uint16_t)(219); + _curvea0[670] = _13810; + uint16_t _13811 = (uint16_t)(219); + _curvea0[671] = _13811; + uint16_t _13812 = (uint16_t)(219); + _curvea0[672] = _13812; + uint16_t _13813 = (uint16_t)(220); + _curvea0[673] = _13813; + uint16_t _13814 = (uint16_t)(220); + _curvea0[674] = _13814; + uint16_t _13815 = (uint16_t)(220); + _curvea0[675] = _13815; + uint16_t _13816 = (uint16_t)(220); + _curvea0[676] = _13816; + uint16_t _13817 = (uint16_t)(220); + _curvea0[677] = _13817; + uint16_t _13818 = (uint16_t)(220); + _curvea0[678] = _13818; + uint16_t _13819 = (uint16_t)(220); + _curvea0[679] = _13819; + uint16_t _13820 = (uint16_t)(220); + _curvea0[680] = _13820; + uint16_t _13821 = (uint16_t)(221); + _curvea0[681] = _13821; + uint16_t _13822 = (uint16_t)(221); + _curvea0[682] = _13822; + uint16_t _13823 = (uint16_t)(221); + _curvea0[683] = _13823; + uint16_t _13824 = (uint16_t)(221); + _curvea0[684] = _13824; + uint16_t _13825 = (uint16_t)(221); + _curvea0[685] = _13825; + uint16_t _13826 = (uint16_t)(221); + _curvea0[686] = _13826; + uint16_t _13827 = (uint16_t)(221); + _curvea0[687] = _13827; + uint16_t _13828 = (uint16_t)(222); + _curvea0[688] = _13828; + uint16_t _13829 = (uint16_t)(222); + _curvea0[689] = _13829; + uint16_t _13830 = (uint16_t)(222); + _curvea0[690] = _13830; + uint16_t _13831 = (uint16_t)(222); + _curvea0[691] = _13831; + uint16_t _13832 = (uint16_t)(222); + _curvea0[692] = _13832; + uint16_t _13833 = (uint16_t)(222); + _curvea0[693] = _13833; + uint16_t _13834 = (uint16_t)(222); + _curvea0[694] = _13834; + uint16_t _13835 = (uint16_t)(223); + _curvea0[695] = _13835; + uint16_t _13836 = (uint16_t)(223); + _curvea0[696] = _13836; + uint16_t _13837 = (uint16_t)(223); + _curvea0[697] = _13837; + uint16_t _13838 = (uint16_t)(223); + _curvea0[698] = _13838; + uint16_t _13839 = (uint16_t)(223); + _curvea0[699] = _13839; + uint16_t _13840 = (uint16_t)(223); + _curvea0[700] = _13840; + uint16_t _13841 = (uint16_t)(223); + _curvea0[701] = _13841; + uint16_t _13842 = (uint16_t)(223); + _curvea0[702] = _13842; + uint16_t _13843 = (uint16_t)(224); + _curvea0[703] = _13843; + uint16_t _13844 = (uint16_t)(224); + _curvea0[704] = _13844; + uint16_t _13845 = (uint16_t)(224); + _curvea0[705] = _13845; + uint16_t _13846 = (uint16_t)(224); + _curvea0[706] = _13846; + uint16_t _13847 = (uint16_t)(224); + _curvea0[707] = _13847; + uint16_t _13848 = (uint16_t)(224); + _curvea0[708] = _13848; + uint16_t _13849 = (uint16_t)(224); + _curvea0[709] = _13849; + uint16_t _13850 = (uint16_t)(224); + _curvea0[710] = _13850; + uint16_t _13851 = (uint16_t)(225); + _curvea0[711] = _13851; + uint16_t _13852 = (uint16_t)(225); + _curvea0[712] = _13852; + uint16_t _13853 = (uint16_t)(225); + _curvea0[713] = _13853; + uint16_t _13854 = (uint16_t)(225); + _curvea0[714] = _13854; + uint16_t _13855 = (uint16_t)(225); + _curvea0[715] = _13855; + uint16_t _13856 = (uint16_t)(225); + _curvea0[716] = _13856; + uint16_t _13857 = (uint16_t)(225); + _curvea0[717] = _13857; + uint16_t _13858 = (uint16_t)(226); + _curvea0[718] = _13858; + uint16_t _13859 = (uint16_t)(226); + _curvea0[719] = _13859; + uint16_t _13860 = (uint16_t)(226); + _curvea0[720] = _13860; + uint16_t _13861 = (uint16_t)(226); + _curvea0[721] = _13861; + uint16_t _13862 = (uint16_t)(226); + _curvea0[722] = _13862; + uint16_t _13863 = (uint16_t)(226); + _curvea0[723] = _13863; + uint16_t _13864 = (uint16_t)(226); + _curvea0[724] = _13864; + uint16_t _13865 = (uint16_t)(226); + _curvea0[725] = _13865; + uint16_t _13866 = (uint16_t)(227); + _curvea0[726] = _13866; + uint16_t _13867 = (uint16_t)(227); + _curvea0[727] = _13867; + uint16_t _13868 = (uint16_t)(227); + _curvea0[728] = _13868; + uint16_t _13869 = (uint16_t)(227); + _curvea0[729] = _13869; + uint16_t _13870 = (uint16_t)(227); + _curvea0[730] = _13870; + uint16_t _13871 = (uint16_t)(227); + _curvea0[731] = _13871; + uint16_t _13872 = (uint16_t)(227); + _curvea0[732] = _13872; + uint16_t _13873 = (uint16_t)(227); + _curvea0[733] = _13873; + uint16_t _13874 = (uint16_t)(228); + _curvea0[734] = _13874; + uint16_t _13875 = (uint16_t)(228); + _curvea0[735] = _13875; + uint16_t _13876 = (uint16_t)(228); + _curvea0[736] = _13876; + uint16_t _13877 = (uint16_t)(228); + _curvea0[737] = _13877; + uint16_t _13878 = (uint16_t)(228); + _curvea0[738] = _13878; + uint16_t _13879 = (uint16_t)(228); + _curvea0[739] = _13879; + uint16_t _13880 = (uint16_t)(228); + _curvea0[740] = _13880; + uint16_t _13881 = (uint16_t)(228); + _curvea0[741] = _13881; + uint16_t _13882 = (uint16_t)(228); + _curvea0[742] = _13882; + uint16_t _13883 = (uint16_t)(229); + _curvea0[743] = _13883; + uint16_t _13884 = (uint16_t)(229); + _curvea0[744] = _13884; + uint16_t _13885 = (uint16_t)(229); + _curvea0[745] = _13885; + uint16_t _13886 = (uint16_t)(229); + _curvea0[746] = _13886; + uint16_t _13887 = (uint16_t)(229); + _curvea0[747] = _13887; + uint16_t _13888 = (uint16_t)(229); + _curvea0[748] = _13888; + uint16_t _13889 = (uint16_t)(229); + _curvea0[749] = _13889; + uint16_t _13890 = (uint16_t)(229); + _curvea0[750] = _13890; + uint16_t _13891 = (uint16_t)(230); + _curvea0[751] = _13891; + uint16_t _13892 = (uint16_t)(230); + _curvea0[752] = _13892; + uint16_t _13893 = (uint16_t)(230); + _curvea0[753] = _13893; + uint16_t _13894 = (uint16_t)(230); + _curvea0[754] = _13894; + uint16_t _13895 = (uint16_t)(230); + _curvea0[755] = _13895; + uint16_t _13896 = (uint16_t)(230); + _curvea0[756] = _13896; + uint16_t _13897 = (uint16_t)(230); + _curvea0[757] = _13897; + uint16_t _13898 = (uint16_t)(230); + _curvea0[758] = _13898; + uint16_t _13899 = (uint16_t)(231); + _curvea0[759] = _13899; + uint16_t _13900 = (uint16_t)(231); + _curvea0[760] = _13900; + uint16_t _13901 = (uint16_t)(231); + _curvea0[761] = _13901; + uint16_t _13902 = (uint16_t)(231); + _curvea0[762] = _13902; + uint16_t _13903 = (uint16_t)(231); + _curvea0[763] = _13903; + uint16_t _13904 = (uint16_t)(231); + _curvea0[764] = _13904; + uint16_t _13905 = (uint16_t)(231); + _curvea0[765] = _13905; + uint16_t _13906 = (uint16_t)(231); + _curvea0[766] = _13906; + uint16_t _13907 = (uint16_t)(231); + _curvea0[767] = _13907; + uint16_t _13908 = (uint16_t)(232); + _curvea0[768] = _13908; + uint16_t _13909 = (uint16_t)(232); + _curvea0[769] = _13909; + uint16_t _13910 = (uint16_t)(232); + _curvea0[770] = _13910; + uint16_t _13911 = (uint16_t)(232); + _curvea0[771] = _13911; + uint16_t _13912 = (uint16_t)(232); + _curvea0[772] = _13912; + uint16_t _13913 = (uint16_t)(232); + _curvea0[773] = _13913; + uint16_t _13914 = (uint16_t)(232); + _curvea0[774] = _13914; + uint16_t _13915 = (uint16_t)(232); + _curvea0[775] = _13915; + uint16_t _13916 = (uint16_t)(233); + _curvea0[776] = _13916; + uint16_t _13917 = (uint16_t)(233); + _curvea0[777] = _13917; + uint16_t _13918 = (uint16_t)(233); + _curvea0[778] = _13918; + uint16_t _13919 = (uint16_t)(233); + _curvea0[779] = _13919; + uint16_t _13920 = (uint16_t)(233); + _curvea0[780] = _13920; + uint16_t _13921 = (uint16_t)(233); + _curvea0[781] = _13921; + uint16_t _13922 = (uint16_t)(233); + _curvea0[782] = _13922; + uint16_t _13923 = (uint16_t)(233); + _curvea0[783] = _13923; + uint16_t _13924 = (uint16_t)(233); + _curvea0[784] = _13924; + uint16_t _13925 = (uint16_t)(234); + _curvea0[785] = _13925; + uint16_t _13926 = (uint16_t)(234); + _curvea0[786] = _13926; + uint16_t _13927 = (uint16_t)(234); + _curvea0[787] = _13927; + uint16_t _13928 = (uint16_t)(234); + _curvea0[788] = _13928; + uint16_t _13929 = (uint16_t)(234); + _curvea0[789] = _13929; + uint16_t _13930 = (uint16_t)(234); + _curvea0[790] = _13930; + uint16_t _13931 = (uint16_t)(234); + _curvea0[791] = _13931; + uint16_t _13932 = (uint16_t)(234); + _curvea0[792] = _13932; + uint16_t _13933 = (uint16_t)(234); + _curvea0[793] = _13933; + uint16_t _13934 = (uint16_t)(235); + _curvea0[794] = _13934; + uint16_t _13935 = (uint16_t)(235); + _curvea0[795] = _13935; + uint16_t _13936 = (uint16_t)(235); + _curvea0[796] = _13936; + uint16_t _13937 = (uint16_t)(235); + _curvea0[797] = _13937; + uint16_t _13938 = (uint16_t)(235); + _curvea0[798] = _13938; + uint16_t _13939 = (uint16_t)(235); + _curvea0[799] = _13939; + uint16_t _13940 = (uint16_t)(235); + _curvea0[800] = _13940; + uint16_t _13941 = (uint16_t)(235); + _curvea0[801] = _13941; + uint16_t _13942 = (uint16_t)(235); + _curvea0[802] = _13942; + uint16_t _13943 = (uint16_t)(236); + _curvea0[803] = _13943; + uint16_t _13944 = (uint16_t)(236); + _curvea0[804] = _13944; + uint16_t _13945 = (uint16_t)(236); + _curvea0[805] = _13945; + uint16_t _13946 = (uint16_t)(236); + _curvea0[806] = _13946; + uint16_t _13947 = (uint16_t)(236); + _curvea0[807] = _13947; + uint16_t _13948 = (uint16_t)(236); + _curvea0[808] = _13948; + uint16_t _13949 = (uint16_t)(236); + _curvea0[809] = _13949; + uint16_t _13950 = (uint16_t)(236); + _curvea0[810] = _13950; + uint16_t _13951 = (uint16_t)(236); + _curvea0[811] = _13951; + uint16_t _13952 = (uint16_t)(237); + _curvea0[812] = _13952; + uint16_t _13953 = (uint16_t)(237); + _curvea0[813] = _13953; + uint16_t _13954 = (uint16_t)(237); + _curvea0[814] = _13954; + uint16_t _13955 = (uint16_t)(237); + _curvea0[815] = _13955; + uint16_t _13956 = (uint16_t)(237); + _curvea0[816] = _13956; + uint16_t _13957 = (uint16_t)(237); + _curvea0[817] = _13957; + uint16_t _13958 = (uint16_t)(237); + _curvea0[818] = _13958; + uint16_t _13959 = (uint16_t)(237); + _curvea0[819] = _13959; + uint16_t _13960 = (uint16_t)(237); + _curvea0[820] = _13960; + uint16_t _13961 = (uint16_t)(237); + _curvea0[821] = _13961; + uint16_t _13962 = (uint16_t)(238); + _curvea0[822] = _13962; + uint16_t _13963 = (uint16_t)(238); + _curvea0[823] = _13963; + uint16_t _13964 = (uint16_t)(238); + _curvea0[824] = _13964; + uint16_t _13965 = (uint16_t)(238); + _curvea0[825] = _13965; + uint16_t _13966 = (uint16_t)(238); + _curvea0[826] = _13966; + uint16_t _13967 = (uint16_t)(238); + _curvea0[827] = _13967; + uint16_t _13968 = (uint16_t)(238); + _curvea0[828] = _13968; + uint16_t _13969 = (uint16_t)(238); + _curvea0[829] = _13969; + uint16_t _13970 = (uint16_t)(238); + _curvea0[830] = _13970; + uint16_t _13971 = (uint16_t)(239); + _curvea0[831] = _13971; + uint16_t _13972 = (uint16_t)(239); + _curvea0[832] = _13972; + uint16_t _13973 = (uint16_t)(239); + _curvea0[833] = _13973; + uint16_t _13974 = (uint16_t)(239); + _curvea0[834] = _13974; + uint16_t _13975 = (uint16_t)(239); + _curvea0[835] = _13975; + uint16_t _13976 = (uint16_t)(239); + _curvea0[836] = _13976; + uint16_t _13977 = (uint16_t)(239); + _curvea0[837] = _13977; + uint16_t _13978 = (uint16_t)(239); + _curvea0[838] = _13978; + uint16_t _13979 = (uint16_t)(239); + _curvea0[839] = _13979; + uint16_t _13980 = (uint16_t)(239); + _curvea0[840] = _13980; + uint16_t _13981 = (uint16_t)(240); + _curvea0[841] = _13981; + uint16_t _13982 = (uint16_t)(240); + _curvea0[842] = _13982; + uint16_t _13983 = (uint16_t)(240); + _curvea0[843] = _13983; + uint16_t _13984 = (uint16_t)(240); + _curvea0[844] = _13984; + uint16_t _13985 = (uint16_t)(240); + _curvea0[845] = _13985; + uint16_t _13986 = (uint16_t)(240); + _curvea0[846] = _13986; + uint16_t _13987 = (uint16_t)(240); + _curvea0[847] = _13987; + uint16_t _13988 = (uint16_t)(240); + _curvea0[848] = _13988; + uint16_t _13989 = (uint16_t)(240); + _curvea0[849] = _13989; + uint16_t _13990 = (uint16_t)(240); + _curvea0[850] = _13990; + uint16_t _13991 = (uint16_t)(241); + _curvea0[851] = _13991; + uint16_t _13992 = (uint16_t)(241); + _curvea0[852] = _13992; + uint16_t _13993 = (uint16_t)(241); + _curvea0[853] = _13993; + uint16_t _13994 = (uint16_t)(241); + _curvea0[854] = _13994; + uint16_t _13995 = (uint16_t)(241); + _curvea0[855] = _13995; + uint16_t _13996 = (uint16_t)(241); + _curvea0[856] = _13996; + uint16_t _13997 = (uint16_t)(241); + _curvea0[857] = _13997; + uint16_t _13998 = (uint16_t)(241); + _curvea0[858] = _13998; + uint16_t _13999 = (uint16_t)(241); + _curvea0[859] = _13999; + uint16_t _14000 = (uint16_t)(241); + _curvea0[860] = _14000; + uint16_t _14001 = (uint16_t)(242); + _curvea0[861] = _14001; + uint16_t _14002 = (uint16_t)(242); + _curvea0[862] = _14002; + uint16_t _14003 = (uint16_t)(242); + _curvea0[863] = _14003; + uint16_t _14004 = (uint16_t)(242); + _curvea0[864] = _14004; + uint16_t _14005 = (uint16_t)(242); + _curvea0[865] = _14005; + uint16_t _14006 = (uint16_t)(242); + _curvea0[866] = _14006; + uint16_t _14007 = (uint16_t)(242); + _curvea0[867] = _14007; + uint16_t _14008 = (uint16_t)(242); + _curvea0[868] = _14008; + uint16_t _14009 = (uint16_t)(242); + _curvea0[869] = _14009; + uint16_t _14010 = (uint16_t)(242); + _curvea0[870] = _14010; + uint16_t _14011 = (uint16_t)(243); + _curvea0[871] = _14011; + uint16_t _14012 = (uint16_t)(243); + _curvea0[872] = _14012; + uint16_t _14013 = (uint16_t)(243); + _curvea0[873] = _14013; + uint16_t _14014 = (uint16_t)(243); + _curvea0[874] = _14014; + uint16_t _14015 = (uint16_t)(243); + _curvea0[875] = _14015; + uint16_t _14016 = (uint16_t)(243); + _curvea0[876] = _14016; + uint16_t _14017 = (uint16_t)(243); + _curvea0[877] = _14017; + uint16_t _14018 = (uint16_t)(243); + _curvea0[878] = _14018; + uint16_t _14019 = (uint16_t)(243); + _curvea0[879] = _14019; + uint16_t _14020 = (uint16_t)(243); + _curvea0[880] = _14020; + uint16_t _14021 = (uint16_t)(244); + _curvea0[881] = _14021; + uint16_t _14022 = (uint16_t)(244); + _curvea0[882] = _14022; + uint16_t _14023 = (uint16_t)(244); + _curvea0[883] = _14023; + uint16_t _14024 = (uint16_t)(244); + _curvea0[884] = _14024; + uint16_t _14025 = (uint16_t)(244); + _curvea0[885] = _14025; + uint16_t _14026 = (uint16_t)(244); + _curvea0[886] = _14026; + uint16_t _14027 = (uint16_t)(244); + _curvea0[887] = _14027; + uint16_t _14028 = (uint16_t)(244); + _curvea0[888] = _14028; + uint16_t _14029 = (uint16_t)(244); + _curvea0[889] = _14029; + uint16_t _14030 = (uint16_t)(244); + _curvea0[890] = _14030; + uint16_t _14031 = (uint16_t)(244); + _curvea0[891] = _14031; + uint16_t _14032 = (uint16_t)(245); + _curvea0[892] = _14032; + uint16_t _14033 = (uint16_t)(245); + _curvea0[893] = _14033; + uint16_t _14034 = (uint16_t)(245); + _curvea0[894] = _14034; + uint16_t _14035 = (uint16_t)(245); + _curvea0[895] = _14035; + uint16_t _14036 = (uint16_t)(245); + _curvea0[896] = _14036; + uint16_t _14037 = (uint16_t)(245); + _curvea0[897] = _14037; + uint16_t _14038 = (uint16_t)(245); + _curvea0[898] = _14038; + uint16_t _14039 = (uint16_t)(245); + _curvea0[899] = _14039; + uint16_t _14040 = (uint16_t)(245); + _curvea0[900] = _14040; + uint16_t _14041 = (uint16_t)(245); + _curvea0[901] = _14041; + uint16_t _14042 = (uint16_t)(245); + _curvea0[902] = _14042; + uint16_t _14043 = (uint16_t)(246); + _curvea0[903] = _14043; + uint16_t _14044 = (uint16_t)(246); + _curvea0[904] = _14044; + uint16_t _14045 = (uint16_t)(246); + _curvea0[905] = _14045; + uint16_t _14046 = (uint16_t)(246); + _curvea0[906] = _14046; + uint16_t _14047 = (uint16_t)(246); + _curvea0[907] = _14047; + uint16_t _14048 = (uint16_t)(246); + _curvea0[908] = _14048; + uint16_t _14049 = (uint16_t)(246); + _curvea0[909] = _14049; + uint16_t _14050 = (uint16_t)(246); + _curvea0[910] = _14050; + uint16_t _14051 = (uint16_t)(246); + _curvea0[911] = _14051; + uint16_t _14052 = (uint16_t)(246); + _curvea0[912] = _14052; + uint16_t _14053 = (uint16_t)(246); + _curvea0[913] = _14053; + uint16_t _14054 = (uint16_t)(247); + _curvea0[914] = _14054; + uint16_t _14055 = (uint16_t)(247); + _curvea0[915] = _14055; + uint16_t _14056 = (uint16_t)(247); + _curvea0[916] = _14056; + uint16_t _14057 = (uint16_t)(247); + _curvea0[917] = _14057; + uint16_t _14058 = (uint16_t)(247); + _curvea0[918] = _14058; + uint16_t _14059 = (uint16_t)(247); + _curvea0[919] = _14059; + uint16_t _14060 = (uint16_t)(247); + _curvea0[920] = _14060; + uint16_t _14061 = (uint16_t)(247); + _curvea0[921] = _14061; + uint16_t _14062 = (uint16_t)(247); + _curvea0[922] = _14062; + uint16_t _14063 = (uint16_t)(247); + _curvea0[923] = _14063; + uint16_t _14064 = (uint16_t)(247); + _curvea0[924] = _14064; + uint16_t _14065 = (uint16_t)(248); + _curvea0[925] = _14065; + uint16_t _14066 = (uint16_t)(248); + _curvea0[926] = _14066; + uint16_t _14067 = (uint16_t)(248); + _curvea0[927] = _14067; + uint16_t _14068 = (uint16_t)(248); + _curvea0[928] = _14068; + uint16_t _14069 = (uint16_t)(248); + _curvea0[929] = _14069; + uint16_t _14070 = (uint16_t)(248); + _curvea0[930] = _14070; + uint16_t _14071 = (uint16_t)(248); + _curvea0[931] = _14071; + uint16_t _14072 = (uint16_t)(248); + _curvea0[932] = _14072; + uint16_t _14073 = (uint16_t)(248); + _curvea0[933] = _14073; + uint16_t _14074 = (uint16_t)(248); + _curvea0[934] = _14074; + uint16_t _14075 = (uint16_t)(248); + _curvea0[935] = _14075; + uint16_t _14076 = (uint16_t)(249); + _curvea0[936] = _14076; + uint16_t _14077 = (uint16_t)(249); + _curvea0[937] = _14077; + uint16_t _14078 = (uint16_t)(249); + _curvea0[938] = _14078; + uint16_t _14079 = (uint16_t)(249); + _curvea0[939] = _14079; + uint16_t _14080 = (uint16_t)(249); + _curvea0[940] = _14080; + uint16_t _14081 = (uint16_t)(249); + _curvea0[941] = _14081; + uint16_t _14082 = (uint16_t)(249); + _curvea0[942] = _14082; + uint16_t _14083 = (uint16_t)(249); + _curvea0[943] = _14083; + uint16_t _14084 = (uint16_t)(249); + _curvea0[944] = _14084; + uint16_t _14085 = (uint16_t)(249); + _curvea0[945] = _14085; + uint16_t _14086 = (uint16_t)(249); + _curvea0[946] = _14086; + uint16_t _14087 = (uint16_t)(249); + _curvea0[947] = _14087; + uint16_t _14088 = (uint16_t)(250); + _curvea0[948] = _14088; + uint16_t _14089 = (uint16_t)(250); + _curvea0[949] = _14089; + uint16_t _14090 = (uint16_t)(250); + _curvea0[950] = _14090; + uint16_t _14091 = (uint16_t)(250); + _curvea0[951] = _14091; + uint16_t _14092 = (uint16_t)(250); + _curvea0[952] = _14092; + uint16_t _14093 = (uint16_t)(250); + _curvea0[953] = _14093; + uint16_t _14094 = (uint16_t)(250); + _curvea0[954] = _14094; + uint16_t _14095 = (uint16_t)(250); + _curvea0[955] = _14095; + uint16_t _14096 = (uint16_t)(250); + _curvea0[956] = _14096; + uint16_t _14097 = (uint16_t)(250); + _curvea0[957] = _14097; + uint16_t _14098 = (uint16_t)(250); + _curvea0[958] = _14098; + uint16_t _14099 = (uint16_t)(250); + _curvea0[959] = _14099; + uint16_t _14100 = (uint16_t)(251); + _curvea0[960] = _14100; + uint16_t _14101 = (uint16_t)(251); + _curvea0[961] = _14101; + uint16_t _14102 = (uint16_t)(251); + _curvea0[962] = _14102; + uint16_t _14103 = (uint16_t)(251); + _curvea0[963] = _14103; + uint16_t _14104 = (uint16_t)(251); + _curvea0[964] = _14104; + uint16_t _14105 = (uint16_t)(251); + _curvea0[965] = _14105; + uint16_t _14106 = (uint16_t)(251); + _curvea0[966] = _14106; + uint16_t _14107 = (uint16_t)(251); + _curvea0[967] = _14107; + uint16_t _14108 = (uint16_t)(251); + _curvea0[968] = _14108; + uint16_t _14109 = (uint16_t)(251); + _curvea0[969] = _14109; + uint16_t _14110 = (uint16_t)(251); + _curvea0[970] = _14110; + uint16_t _14111 = (uint16_t)(251); + _curvea0[971] = _14111; + uint16_t _14112 = (uint16_t)(252); + _curvea0[972] = _14112; + uint16_t _14113 = (uint16_t)(252); + _curvea0[973] = _14113; + uint16_t _14114 = (uint16_t)(252); + _curvea0[974] = _14114; + uint16_t _14115 = (uint16_t)(252); + _curvea0[975] = _14115; + uint16_t _14116 = (uint16_t)(252); + _curvea0[976] = _14116; + uint16_t _14117 = (uint16_t)(252); + _curvea0[977] = _14117; + uint16_t _14118 = (uint16_t)(252); + _curvea0[978] = _14118; + uint16_t _14119 = (uint16_t)(252); + _curvea0[979] = _14119; + uint16_t _14120 = (uint16_t)(252); + _curvea0[980] = _14120; + uint16_t _14121 = (uint16_t)(252); + _curvea0[981] = _14121; + uint16_t _14122 = (uint16_t)(252); + _curvea0[982] = _14122; + uint16_t _14123 = (uint16_t)(252); + _curvea0[983] = _14123; + uint16_t _14124 = (uint16_t)(252); + _curvea0[984] = _14124; + uint16_t _14125 = (uint16_t)(253); + _curvea0[985] = _14125; + uint16_t _14126 = (uint16_t)(253); + _curvea0[986] = _14126; + uint16_t _14127 = (uint16_t)(253); + _curvea0[987] = _14127; + uint16_t _14128 = (uint16_t)(253); + _curvea0[988] = _14128; + uint16_t _14129 = (uint16_t)(253); + _curvea0[989] = _14129; + uint16_t _14130 = (uint16_t)(253); + _curvea0[990] = _14130; + uint16_t _14131 = (uint16_t)(253); + _curvea0[991] = _14131; + uint16_t _14132 = (uint16_t)(253); + _curvea0[992] = _14132; + uint16_t _14133 = (uint16_t)(253); + _curvea0[993] = _14133; + uint16_t _14134 = (uint16_t)(253); + _curvea0[994] = _14134; + uint16_t _14135 = (uint16_t)(253); + _curvea0[995] = _14135; + uint16_t _14136 = (uint16_t)(253); + _curvea0[996] = _14136; + uint16_t _14137 = (uint16_t)(253); + _curvea0[997] = _14137; + uint16_t _14138 = (uint16_t)(254); + _curvea0[998] = _14138; + uint16_t _14139 = (uint16_t)(254); + _curvea0[999] = _14139; + uint16_t _14140 = (uint16_t)(254); + _curvea0[1000] = _14140; + uint16_t _14141 = (uint16_t)(254); + _curvea0[1001] = _14141; + uint16_t _14142 = (uint16_t)(254); + _curvea0[1002] = _14142; + uint16_t _14143 = (uint16_t)(254); + _curvea0[1003] = _14143; + uint16_t _14144 = (uint16_t)(254); + _curvea0[1004] = _14144; + uint16_t _14145 = (uint16_t)(254); + _curvea0[1005] = _14145; + uint16_t _14146 = (uint16_t)(254); + _curvea0[1006] = _14146; + uint16_t _14147 = (uint16_t)(254); + _curvea0[1007] = _14147; + uint16_t _14148 = (uint16_t)(254); + _curvea0[1008] = _14148; + uint16_t _14149 = (uint16_t)(254); + _curvea0[1009] = _14149; + uint16_t _14150 = (uint16_t)(254); + _curvea0[1010] = _14150; + uint16_t _14151 = (uint16_t)(255); + _curvea0[1011] = _14151; + uint16_t _14152 = (uint16_t)(255); + _curvea0[1012] = _14152; + uint16_t _14153 = (uint16_t)(255); + _curvea0[1013] = _14153; + uint16_t _14154 = (uint16_t)(255); + _curvea0[1014] = _14154; + uint16_t _14155 = (uint16_t)(255); + _curvea0[1015] = _14155; + uint16_t _14156 = (uint16_t)(255); + _curvea0[1016] = _14156; + uint16_t _14157 = (uint16_t)(255); + _curvea0[1017] = _14157; + uint16_t _14158 = (uint16_t)(255); + _curvea0[1018] = _14158; + uint16_t _14159 = (uint16_t)(255); + _curvea0[1019] = _14159; + uint16_t _14160 = (uint16_t)(255); + _curvea0[1020] = _14160; + uint16_t _14161 = (uint16_t)(255); + _curvea0[1021] = _14161; + uint16_t _14162 = (uint16_t)(255); + _curvea0[1022] = _14162; + uint16_t _14163 = (uint16_t)(255); + _curvea0[1023] = _14163; + + int16_t _14164 = (int16_t)(1023); + int16_t _14165 = min(_corrected_stencil_11, _14164); + int16_t _14166 = (int16_t)(0); + int16_t _14167 = max(_14165, _14166); + uint16_t _14168 = (uint16_t)(_14167); + int32_t _14169 = (int32_t)(_14168); + uint16_t _14170 = ((const uint16_t *)_curvea0)[_14169]; + return _14170; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_11(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_12 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _14189 = (uint16_t)(0); + _curvea0[0] = _14189; + uint16_t _14190 = (uint16_t)(4); + _curvea0[1] = _14190; + uint16_t _14191 = (uint16_t)(7); + _curvea0[2] = _14191; + uint16_t _14192 = (uint16_t)(8); + _curvea0[3] = _14192; + uint16_t _14193 = (uint16_t)(10); + _curvea0[4] = _14193; + uint16_t _14194 = (uint16_t)(11); + _curvea0[5] = _14194; + uint16_t _14195 = (uint16_t)(12); + _curvea0[6] = _14195; + uint16_t _14196 = (uint16_t)(13); + _curvea0[7] = _14196; + uint16_t _14197 = (uint16_t)(14); + _curvea0[8] = _14197; + uint16_t _14198 = (uint16_t)(15); + _curvea0[9] = _14198; + uint16_t _14199 = (uint16_t)(16); + _curvea0[10] = _14199; + uint16_t _14200 = (uint16_t)(17); + _curvea0[11] = _14200; + uint16_t _14201 = (uint16_t)(18); + _curvea0[12] = _14201; + uint16_t _14202 = (uint16_t)(19); + _curvea0[13] = _14202; + uint16_t _14203 = (uint16_t)(20); + _curvea0[14] = _14203; + uint16_t _14204 = (uint16_t)(21); + _curvea0[15] = _14204; + uint16_t _14205 = (uint16_t)(22); + _curvea0[16] = _14205; + uint16_t _14206 = (uint16_t)(22); + _curvea0[17] = _14206; + uint16_t _14207 = (uint16_t)(23); + _curvea0[18] = _14207; + uint16_t _14208 = (uint16_t)(24); + _curvea0[19] = _14208; + uint16_t _14209 = (uint16_t)(25); + _curvea0[20] = _14209; + uint16_t _14210 = (uint16_t)(25); + _curvea0[21] = _14210; + uint16_t _14211 = (uint16_t)(26); + _curvea0[22] = _14211; + uint16_t _14212 = (uint16_t)(27); + _curvea0[23] = _14212; + uint16_t _14213 = (uint16_t)(27); + _curvea0[24] = _14213; + uint16_t _14214 = (uint16_t)(28); + _curvea0[25] = _14214; + uint16_t _14215 = (uint16_t)(29); + _curvea0[26] = _14215; + uint16_t _14216 = (uint16_t)(29); + _curvea0[27] = _14216; + uint16_t _14217 = (uint16_t)(30); + _curvea0[28] = _14217; + uint16_t _14218 = (uint16_t)(31); + _curvea0[29] = _14218; + uint16_t _14219 = (uint16_t)(31); + _curvea0[30] = _14219; + uint16_t _14220 = (uint16_t)(32); + _curvea0[31] = _14220; + uint16_t _14221 = (uint16_t)(33); + _curvea0[32] = _14221; + uint16_t _14222 = (uint16_t)(33); + _curvea0[33] = _14222; + uint16_t _14223 = (uint16_t)(34); + _curvea0[34] = _14223; + uint16_t _14224 = (uint16_t)(34); + _curvea0[35] = _14224; + uint16_t _14225 = (uint16_t)(35); + _curvea0[36] = _14225; + uint16_t _14226 = (uint16_t)(36); + _curvea0[37] = _14226; + uint16_t _14227 = (uint16_t)(36); + _curvea0[38] = _14227; + uint16_t _14228 = (uint16_t)(37); + _curvea0[39] = _14228; + uint16_t _14229 = (uint16_t)(37); + _curvea0[40] = _14229; + uint16_t _14230 = (uint16_t)(38); + _curvea0[41] = _14230; + uint16_t _14231 = (uint16_t)(39); + _curvea0[42] = _14231; + uint16_t _14232 = (uint16_t)(39); + _curvea0[43] = _14232; + uint16_t _14233 = (uint16_t)(40); + _curvea0[44] = _14233; + uint16_t _14234 = (uint16_t)(40); + _curvea0[45] = _14234; + uint16_t _14235 = (uint16_t)(41); + _curvea0[46] = _14235; + uint16_t _14236 = (uint16_t)(41); + _curvea0[47] = _14236; + uint16_t _14237 = (uint16_t)(42); + _curvea0[48] = _14237; + uint16_t _14238 = (uint16_t)(42); + _curvea0[49] = _14238; + uint16_t _14239 = (uint16_t)(43); + _curvea0[50] = _14239; + uint16_t _14240 = (uint16_t)(44); + _curvea0[51] = _14240; + uint16_t _14241 = (uint16_t)(44); + _curvea0[52] = _14241; + uint16_t _14242 = (uint16_t)(45); + _curvea0[53] = _14242; + uint16_t _14243 = (uint16_t)(45); + _curvea0[54] = _14243; + uint16_t _14244 = (uint16_t)(46); + _curvea0[55] = _14244; + uint16_t _14245 = (uint16_t)(46); + _curvea0[56] = _14245; + uint16_t _14246 = (uint16_t)(47); + _curvea0[57] = _14246; + uint16_t _14247 = (uint16_t)(47); + _curvea0[58] = _14247; + uint16_t _14248 = (uint16_t)(48); + _curvea0[59] = _14248; + uint16_t _14249 = (uint16_t)(48); + _curvea0[60] = _14249; + uint16_t _14250 = (uint16_t)(49); + _curvea0[61] = _14250; + uint16_t _14251 = (uint16_t)(49); + _curvea0[62] = _14251; + uint16_t _14252 = (uint16_t)(50); + _curvea0[63] = _14252; + uint16_t _14253 = (uint16_t)(50); + _curvea0[64] = _14253; + uint16_t _14254 = (uint16_t)(51); + _curvea0[65] = _14254; + uint16_t _14255 = (uint16_t)(51); + _curvea0[66] = _14255; + uint16_t _14256 = (uint16_t)(52); + _curvea0[67] = _14256; + uint16_t _14257 = (uint16_t)(52); + _curvea0[68] = _14257; + uint16_t _14258 = (uint16_t)(53); + _curvea0[69] = _14258; + uint16_t _14259 = (uint16_t)(53); + _curvea0[70] = _14259; + uint16_t _14260 = (uint16_t)(54); + _curvea0[71] = _14260; + uint16_t _14261 = (uint16_t)(54); + _curvea0[72] = _14261; + uint16_t _14262 = (uint16_t)(55); + _curvea0[73] = _14262; + uint16_t _14263 = (uint16_t)(55); + _curvea0[74] = _14263; + uint16_t _14264 = (uint16_t)(56); + _curvea0[75] = _14264; + uint16_t _14265 = (uint16_t)(56); + _curvea0[76] = _14265; + uint16_t _14266 = (uint16_t)(57); + _curvea0[77] = _14266; + uint16_t _14267 = (uint16_t)(57); + _curvea0[78] = _14267; + uint16_t _14268 = (uint16_t)(58); + _curvea0[79] = _14268; + uint16_t _14269 = (uint16_t)(58); + _curvea0[80] = _14269; + uint16_t _14270 = (uint16_t)(58); + _curvea0[81] = _14270; + uint16_t _14271 = (uint16_t)(59); + _curvea0[82] = _14271; + uint16_t _14272 = (uint16_t)(59); + _curvea0[83] = _14272; + uint16_t _14273 = (uint16_t)(60); + _curvea0[84] = _14273; + uint16_t _14274 = (uint16_t)(60); + _curvea0[85] = _14274; + uint16_t _14275 = (uint16_t)(61); + _curvea0[86] = _14275; + uint16_t _14276 = (uint16_t)(61); + _curvea0[87] = _14276; + uint16_t _14277 = (uint16_t)(62); + _curvea0[88] = _14277; + uint16_t _14278 = (uint16_t)(62); + _curvea0[89] = _14278; + uint16_t _14279 = (uint16_t)(63); + _curvea0[90] = _14279; + uint16_t _14280 = (uint16_t)(63); + _curvea0[91] = _14280; + uint16_t _14281 = (uint16_t)(64); + _curvea0[92] = _14281; + uint16_t _14282 = (uint16_t)(64); + _curvea0[93] = _14282; + uint16_t _14283 = (uint16_t)(64); + _curvea0[94] = _14283; + uint16_t _14284 = (uint16_t)(65); + _curvea0[95] = _14284; + uint16_t _14285 = (uint16_t)(65); + _curvea0[96] = _14285; + uint16_t _14286 = (uint16_t)(66); + _curvea0[97] = _14286; + uint16_t _14287 = (uint16_t)(66); + _curvea0[98] = _14287; + uint16_t _14288 = (uint16_t)(67); + _curvea0[99] = _14288; + uint16_t _14289 = (uint16_t)(67); + _curvea0[100] = _14289; + uint16_t _14290 = (uint16_t)(68); + _curvea0[101] = _14290; + uint16_t _14291 = (uint16_t)(68); + _curvea0[102] = _14291; + uint16_t _14292 = (uint16_t)(68); + _curvea0[103] = _14292; + uint16_t _14293 = (uint16_t)(69); + _curvea0[104] = _14293; + uint16_t _14294 = (uint16_t)(69); + _curvea0[105] = _14294; + uint16_t _14295 = (uint16_t)(70); + _curvea0[106] = _14295; + uint16_t _14296 = (uint16_t)(70); + _curvea0[107] = _14296; + uint16_t _14297 = (uint16_t)(71); + _curvea0[108] = _14297; + uint16_t _14298 = (uint16_t)(71); + _curvea0[109] = _14298; + uint16_t _14299 = (uint16_t)(71); + _curvea0[110] = _14299; + uint16_t _14300 = (uint16_t)(72); + _curvea0[111] = _14300; + uint16_t _14301 = (uint16_t)(72); + _curvea0[112] = _14301; + uint16_t _14302 = (uint16_t)(73); + _curvea0[113] = _14302; + uint16_t _14303 = (uint16_t)(73); + _curvea0[114] = _14303; + uint16_t _14304 = (uint16_t)(74); + _curvea0[115] = _14304; + uint16_t _14305 = (uint16_t)(74); + _curvea0[116] = _14305; + uint16_t _14306 = (uint16_t)(74); + _curvea0[117] = _14306; + uint16_t _14307 = (uint16_t)(75); + _curvea0[118] = _14307; + uint16_t _14308 = (uint16_t)(75); + _curvea0[119] = _14308; + uint16_t _14309 = (uint16_t)(76); + _curvea0[120] = _14309; + uint16_t _14310 = (uint16_t)(76); + _curvea0[121] = _14310; + uint16_t _14311 = (uint16_t)(77); + _curvea0[122] = _14311; + uint16_t _14312 = (uint16_t)(77); + _curvea0[123] = _14312; + uint16_t _14313 = (uint16_t)(77); + _curvea0[124] = _14313; + uint16_t _14314 = (uint16_t)(78); + _curvea0[125] = _14314; + uint16_t _14315 = (uint16_t)(78); + _curvea0[126] = _14315; + uint16_t _14316 = (uint16_t)(79); + _curvea0[127] = _14316; + uint16_t _14317 = (uint16_t)(79); + _curvea0[128] = _14317; + uint16_t _14318 = (uint16_t)(79); + _curvea0[129] = _14318; + uint16_t _14319 = (uint16_t)(80); + _curvea0[130] = _14319; + uint16_t _14320 = (uint16_t)(80); + _curvea0[131] = _14320; + uint16_t _14321 = (uint16_t)(81); + _curvea0[132] = _14321; + uint16_t _14322 = (uint16_t)(81); + _curvea0[133] = _14322; + uint16_t _14323 = (uint16_t)(82); + _curvea0[134] = _14323; + uint16_t _14324 = (uint16_t)(82); + _curvea0[135] = _14324; + uint16_t _14325 = (uint16_t)(82); + _curvea0[136] = _14325; + uint16_t _14326 = (uint16_t)(83); + _curvea0[137] = _14326; + uint16_t _14327 = (uint16_t)(83); + _curvea0[138] = _14327; + uint16_t _14328 = (uint16_t)(84); + _curvea0[139] = _14328; + uint16_t _14329 = (uint16_t)(84); + _curvea0[140] = _14329; + uint16_t _14330 = (uint16_t)(84); + _curvea0[141] = _14330; + uint16_t _14331 = (uint16_t)(85); + _curvea0[142] = _14331; + uint16_t _14332 = (uint16_t)(85); + _curvea0[143] = _14332; + uint16_t _14333 = (uint16_t)(86); + _curvea0[144] = _14333; + uint16_t _14334 = (uint16_t)(86); + _curvea0[145] = _14334; + uint16_t _14335 = (uint16_t)(86); + _curvea0[146] = _14335; + uint16_t _14336 = (uint16_t)(87); + _curvea0[147] = _14336; + uint16_t _14337 = (uint16_t)(87); + _curvea0[148] = _14337; + uint16_t _14338 = (uint16_t)(88); + _curvea0[149] = _14338; + uint16_t _14339 = (uint16_t)(88); + _curvea0[150] = _14339; + uint16_t _14340 = (uint16_t)(88); + _curvea0[151] = _14340; + uint16_t _14341 = (uint16_t)(89); + _curvea0[152] = _14341; + uint16_t _14342 = (uint16_t)(89); + _curvea0[153] = _14342; + uint16_t _14343 = (uint16_t)(90); + _curvea0[154] = _14343; + uint16_t _14344 = (uint16_t)(90); + _curvea0[155] = _14344; + uint16_t _14345 = (uint16_t)(90); + _curvea0[156] = _14345; + uint16_t _14346 = (uint16_t)(91); + _curvea0[157] = _14346; + uint16_t _14347 = (uint16_t)(91); + _curvea0[158] = _14347; + uint16_t _14348 = (uint16_t)(92); + _curvea0[159] = _14348; + uint16_t _14349 = (uint16_t)(92); + _curvea0[160] = _14349; + uint16_t _14350 = (uint16_t)(92); + _curvea0[161] = _14350; + uint16_t _14351 = (uint16_t)(93); + _curvea0[162] = _14351; + uint16_t _14352 = (uint16_t)(93); + _curvea0[163] = _14352; + uint16_t _14353 = (uint16_t)(93); + _curvea0[164] = _14353; + uint16_t _14354 = (uint16_t)(94); + _curvea0[165] = _14354; + uint16_t _14355 = (uint16_t)(94); + _curvea0[166] = _14355; + uint16_t _14356 = (uint16_t)(95); + _curvea0[167] = _14356; + uint16_t _14357 = (uint16_t)(95); + _curvea0[168] = _14357; + uint16_t _14358 = (uint16_t)(95); + _curvea0[169] = _14358; + uint16_t _14359 = (uint16_t)(96); + _curvea0[170] = _14359; + uint16_t _14360 = (uint16_t)(96); + _curvea0[171] = _14360; + uint16_t _14361 = (uint16_t)(97); + _curvea0[172] = _14361; + uint16_t _14362 = (uint16_t)(97); + _curvea0[173] = _14362; + uint16_t _14363 = (uint16_t)(97); + _curvea0[174] = _14363; + uint16_t _14364 = (uint16_t)(98); + _curvea0[175] = _14364; + uint16_t _14365 = (uint16_t)(98); + _curvea0[176] = _14365; + uint16_t _14366 = (uint16_t)(99); + _curvea0[177] = _14366; + uint16_t _14367 = (uint16_t)(99); + _curvea0[178] = _14367; + uint16_t _14368 = (uint16_t)(99); + _curvea0[179] = _14368; + uint16_t _14369 = (uint16_t)(100); + _curvea0[180] = _14369; + uint16_t _14370 = (uint16_t)(100); + _curvea0[181] = _14370; + uint16_t _14371 = (uint16_t)(100); + _curvea0[182] = _14371; + uint16_t _14372 = (uint16_t)(101); + _curvea0[183] = _14372; + uint16_t _14373 = (uint16_t)(101); + _curvea0[184] = _14373; + uint16_t _14374 = (uint16_t)(102); + _curvea0[185] = _14374; + uint16_t _14375 = (uint16_t)(102); + _curvea0[186] = _14375; + uint16_t _14376 = (uint16_t)(102); + _curvea0[187] = _14376; + uint16_t _14377 = (uint16_t)(103); + _curvea0[188] = _14377; + uint16_t _14378 = (uint16_t)(103); + _curvea0[189] = _14378; + uint16_t _14379 = (uint16_t)(103); + _curvea0[190] = _14379; + uint16_t _14380 = (uint16_t)(104); + _curvea0[191] = _14380; + uint16_t _14381 = (uint16_t)(104); + _curvea0[192] = _14381; + uint16_t _14382 = (uint16_t)(105); + _curvea0[193] = _14382; + uint16_t _14383 = (uint16_t)(105); + _curvea0[194] = _14383; + uint16_t _14384 = (uint16_t)(105); + _curvea0[195] = _14384; + uint16_t _14385 = (uint16_t)(106); + _curvea0[196] = _14385; + uint16_t _14386 = (uint16_t)(106); + _curvea0[197] = _14386; + uint16_t _14387 = (uint16_t)(106); + _curvea0[198] = _14387; + uint16_t _14388 = (uint16_t)(107); + _curvea0[199] = _14388; + uint16_t _14389 = (uint16_t)(107); + _curvea0[200] = _14389; + uint16_t _14390 = (uint16_t)(108); + _curvea0[201] = _14390; + uint16_t _14391 = (uint16_t)(108); + _curvea0[202] = _14391; + uint16_t _14392 = (uint16_t)(108); + _curvea0[203] = _14392; + uint16_t _14393 = (uint16_t)(109); + _curvea0[204] = _14393; + uint16_t _14394 = (uint16_t)(109); + _curvea0[205] = _14394; + uint16_t _14395 = (uint16_t)(109); + _curvea0[206] = _14395; + uint16_t _14396 = (uint16_t)(110); + _curvea0[207] = _14396; + uint16_t _14397 = (uint16_t)(110); + _curvea0[208] = _14397; + uint16_t _14398 = (uint16_t)(111); + _curvea0[209] = _14398; + uint16_t _14399 = (uint16_t)(111); + _curvea0[210] = _14399; + uint16_t _14400 = (uint16_t)(111); + _curvea0[211] = _14400; + uint16_t _14401 = (uint16_t)(112); + _curvea0[212] = _14401; + uint16_t _14402 = (uint16_t)(112); + _curvea0[213] = _14402; + uint16_t _14403 = (uint16_t)(112); + _curvea0[214] = _14403; + uint16_t _14404 = (uint16_t)(113); + _curvea0[215] = _14404; + uint16_t _14405 = (uint16_t)(113); + _curvea0[216] = _14405; + uint16_t _14406 = (uint16_t)(113); + _curvea0[217] = _14406; + uint16_t _14407 = (uint16_t)(114); + _curvea0[218] = _14407; + uint16_t _14408 = (uint16_t)(114); + _curvea0[219] = _14408; + uint16_t _14409 = (uint16_t)(115); + _curvea0[220] = _14409; + uint16_t _14410 = (uint16_t)(115); + _curvea0[221] = _14410; + uint16_t _14411 = (uint16_t)(115); + _curvea0[222] = _14411; + uint16_t _14412 = (uint16_t)(116); + _curvea0[223] = _14412; + uint16_t _14413 = (uint16_t)(116); + _curvea0[224] = _14413; + uint16_t _14414 = (uint16_t)(116); + _curvea0[225] = _14414; + uint16_t _14415 = (uint16_t)(117); + _curvea0[226] = _14415; + uint16_t _14416 = (uint16_t)(117); + _curvea0[227] = _14416; + uint16_t _14417 = (uint16_t)(117); + _curvea0[228] = _14417; + uint16_t _14418 = (uint16_t)(118); + _curvea0[229] = _14418; + uint16_t _14419 = (uint16_t)(118); + _curvea0[230] = _14419; + uint16_t _14420 = (uint16_t)(119); + _curvea0[231] = _14420; + uint16_t _14421 = (uint16_t)(119); + _curvea0[232] = _14421; + uint16_t _14422 = (uint16_t)(119); + _curvea0[233] = _14422; + uint16_t _14423 = (uint16_t)(120); + _curvea0[234] = _14423; + uint16_t _14424 = (uint16_t)(120); + _curvea0[235] = _14424; + uint16_t _14425 = (uint16_t)(120); + _curvea0[236] = _14425; + uint16_t _14426 = (uint16_t)(121); + _curvea0[237] = _14426; + uint16_t _14427 = (uint16_t)(121); + _curvea0[238] = _14427; + uint16_t _14428 = (uint16_t)(121); + _curvea0[239] = _14428; + uint16_t _14429 = (uint16_t)(122); + _curvea0[240] = _14429; + uint16_t _14430 = (uint16_t)(122); + _curvea0[241] = _14430; + uint16_t _14431 = (uint16_t)(123); + _curvea0[242] = _14431; + uint16_t _14432 = (uint16_t)(123); + _curvea0[243] = _14432; + uint16_t _14433 = (uint16_t)(123); + _curvea0[244] = _14433; + uint16_t _14434 = (uint16_t)(124); + _curvea0[245] = _14434; + uint16_t _14435 = (uint16_t)(124); + _curvea0[246] = _14435; + uint16_t _14436 = (uint16_t)(124); + _curvea0[247] = _14436; + uint16_t _14437 = (uint16_t)(125); + _curvea0[248] = _14437; + uint16_t _14438 = (uint16_t)(125); + _curvea0[249] = _14438; + uint16_t _14439 = (uint16_t)(125); + _curvea0[250] = _14439; + uint16_t _14440 = (uint16_t)(126); + _curvea0[251] = _14440; + uint16_t _14441 = (uint16_t)(126); + _curvea0[252] = _14441; + uint16_t _14442 = (uint16_t)(126); + _curvea0[253] = _14442; + uint16_t _14443 = (uint16_t)(127); + _curvea0[254] = _14443; + uint16_t _14444 = (uint16_t)(127); + _curvea0[255] = _14444; + uint16_t _14445 = (uint16_t)(128); + _curvea0[256] = _14445; + uint16_t _14446 = (uint16_t)(128); + _curvea0[257] = _14446; + uint16_t _14447 = (uint16_t)(128); + _curvea0[258] = _14447; + uint16_t _14448 = (uint16_t)(129); + _curvea0[259] = _14448; + uint16_t _14449 = (uint16_t)(129); + _curvea0[260] = _14449; + uint16_t _14450 = (uint16_t)(129); + _curvea0[261] = _14450; + uint16_t _14451 = (uint16_t)(130); + _curvea0[262] = _14451; + uint16_t _14452 = (uint16_t)(130); + _curvea0[263] = _14452; + uint16_t _14453 = (uint16_t)(130); + _curvea0[264] = _14453; + uint16_t _14454 = (uint16_t)(131); + _curvea0[265] = _14454; + uint16_t _14455 = (uint16_t)(131); + _curvea0[266] = _14455; + uint16_t _14456 = (uint16_t)(131); + _curvea0[267] = _14456; + uint16_t _14457 = (uint16_t)(132); + _curvea0[268] = _14457; + uint16_t _14458 = (uint16_t)(132); + _curvea0[269] = _14458; + uint16_t _14459 = (uint16_t)(132); + _curvea0[270] = _14459; + uint16_t _14460 = (uint16_t)(133); + _curvea0[271] = _14460; + uint16_t _14461 = (uint16_t)(133); + _curvea0[272] = _14461; + uint16_t _14462 = (uint16_t)(133); + _curvea0[273] = _14462; + uint16_t _14463 = (uint16_t)(134); + _curvea0[274] = _14463; + uint16_t _14464 = (uint16_t)(134); + _curvea0[275] = _14464; + uint16_t _14465 = (uint16_t)(134); + _curvea0[276] = _14465; + uint16_t _14466 = (uint16_t)(135); + _curvea0[277] = _14466; + uint16_t _14467 = (uint16_t)(135); + _curvea0[278] = _14467; + uint16_t _14468 = (uint16_t)(135); + _curvea0[279] = _14468; + uint16_t _14469 = (uint16_t)(136); + _curvea0[280] = _14469; + uint16_t _14470 = (uint16_t)(136); + _curvea0[281] = _14470; + uint16_t _14471 = (uint16_t)(136); + _curvea0[282] = _14471; + uint16_t _14472 = (uint16_t)(137); + _curvea0[283] = _14472; + uint16_t _14473 = (uint16_t)(137); + _curvea0[284] = _14473; + uint16_t _14474 = (uint16_t)(137); + _curvea0[285] = _14474; + uint16_t _14475 = (uint16_t)(138); + _curvea0[286] = _14475; + uint16_t _14476 = (uint16_t)(138); + _curvea0[287] = _14476; + uint16_t _14477 = (uint16_t)(138); + _curvea0[288] = _14477; + uint16_t _14478 = (uint16_t)(139); + _curvea0[289] = _14478; + uint16_t _14479 = (uint16_t)(139); + _curvea0[290] = _14479; + uint16_t _14480 = (uint16_t)(139); + _curvea0[291] = _14480; + uint16_t _14481 = (uint16_t)(140); + _curvea0[292] = _14481; + uint16_t _14482 = (uint16_t)(140); + _curvea0[293] = _14482; + uint16_t _14483 = (uint16_t)(140); + _curvea0[294] = _14483; + uint16_t _14484 = (uint16_t)(141); + _curvea0[295] = _14484; + uint16_t _14485 = (uint16_t)(141); + _curvea0[296] = _14485; + uint16_t _14486 = (uint16_t)(141); + _curvea0[297] = _14486; + uint16_t _14487 = (uint16_t)(141); + _curvea0[298] = _14487; + uint16_t _14488 = (uint16_t)(142); + _curvea0[299] = _14488; + uint16_t _14489 = (uint16_t)(142); + _curvea0[300] = _14489; + uint16_t _14490 = (uint16_t)(142); + _curvea0[301] = _14490; + uint16_t _14491 = (uint16_t)(143); + _curvea0[302] = _14491; + uint16_t _14492 = (uint16_t)(143); + _curvea0[303] = _14492; + uint16_t _14493 = (uint16_t)(143); + _curvea0[304] = _14493; + uint16_t _14494 = (uint16_t)(144); + _curvea0[305] = _14494; + uint16_t _14495 = (uint16_t)(144); + _curvea0[306] = _14495; + uint16_t _14496 = (uint16_t)(144); + _curvea0[307] = _14496; + uint16_t _14497 = (uint16_t)(145); + _curvea0[308] = _14497; + uint16_t _14498 = (uint16_t)(145); + _curvea0[309] = _14498; + uint16_t _14499 = (uint16_t)(145); + _curvea0[310] = _14499; + uint16_t _14500 = (uint16_t)(145); + _curvea0[311] = _14500; + uint16_t _14501 = (uint16_t)(146); + _curvea0[312] = _14501; + uint16_t _14502 = (uint16_t)(146); + _curvea0[313] = _14502; + uint16_t _14503 = (uint16_t)(146); + _curvea0[314] = _14503; + uint16_t _14504 = (uint16_t)(147); + _curvea0[315] = _14504; + uint16_t _14505 = (uint16_t)(147); + _curvea0[316] = _14505; + uint16_t _14506 = (uint16_t)(147); + _curvea0[317] = _14506; + uint16_t _14507 = (uint16_t)(148); + _curvea0[318] = _14507; + uint16_t _14508 = (uint16_t)(148); + _curvea0[319] = _14508; + uint16_t _14509 = (uint16_t)(148); + _curvea0[320] = _14509; + uint16_t _14510 = (uint16_t)(148); + _curvea0[321] = _14510; + uint16_t _14511 = (uint16_t)(149); + _curvea0[322] = _14511; + uint16_t _14512 = (uint16_t)(149); + _curvea0[323] = _14512; + uint16_t _14513 = (uint16_t)(149); + _curvea0[324] = _14513; + uint16_t _14514 = (uint16_t)(150); + _curvea0[325] = _14514; + uint16_t _14515 = (uint16_t)(150); + _curvea0[326] = _14515; + uint16_t _14516 = (uint16_t)(150); + _curvea0[327] = _14516; + uint16_t _14517 = (uint16_t)(150); + _curvea0[328] = _14517; + uint16_t _14518 = (uint16_t)(151); + _curvea0[329] = _14518; + uint16_t _14519 = (uint16_t)(151); + _curvea0[330] = _14519; + uint16_t _14520 = (uint16_t)(151); + _curvea0[331] = _14520; + uint16_t _14521 = (uint16_t)(152); + _curvea0[332] = _14521; + uint16_t _14522 = (uint16_t)(152); + _curvea0[333] = _14522; + uint16_t _14523 = (uint16_t)(152); + _curvea0[334] = _14523; + uint16_t _14524 = (uint16_t)(152); + _curvea0[335] = _14524; + uint16_t _14525 = (uint16_t)(153); + _curvea0[336] = _14525; + uint16_t _14526 = (uint16_t)(153); + _curvea0[337] = _14526; + uint16_t _14527 = (uint16_t)(153); + _curvea0[338] = _14527; + uint16_t _14528 = (uint16_t)(154); + _curvea0[339] = _14528; + uint16_t _14529 = (uint16_t)(154); + _curvea0[340] = _14529; + uint16_t _14530 = (uint16_t)(154); + _curvea0[341] = _14530; + uint16_t _14531 = (uint16_t)(154); + _curvea0[342] = _14531; + uint16_t _14532 = (uint16_t)(155); + _curvea0[343] = _14532; + uint16_t _14533 = (uint16_t)(155); + _curvea0[344] = _14533; + uint16_t _14534 = (uint16_t)(155); + _curvea0[345] = _14534; + uint16_t _14535 = (uint16_t)(156); + _curvea0[346] = _14535; + uint16_t _14536 = (uint16_t)(156); + _curvea0[347] = _14536; + uint16_t _14537 = (uint16_t)(156); + _curvea0[348] = _14537; + uint16_t _14538 = (uint16_t)(156); + _curvea0[349] = _14538; + uint16_t _14539 = (uint16_t)(157); + _curvea0[350] = _14539; + uint16_t _14540 = (uint16_t)(157); + _curvea0[351] = _14540; + uint16_t _14541 = (uint16_t)(157); + _curvea0[352] = _14541; + uint16_t _14542 = (uint16_t)(157); + _curvea0[353] = _14542; + uint16_t _14543 = (uint16_t)(158); + _curvea0[354] = _14543; + uint16_t _14544 = (uint16_t)(158); + _curvea0[355] = _14544; + uint16_t _14545 = (uint16_t)(158); + _curvea0[356] = _14545; + uint16_t _14546 = (uint16_t)(159); + _curvea0[357] = _14546; + uint16_t _14547 = (uint16_t)(159); + _curvea0[358] = _14547; + uint16_t _14548 = (uint16_t)(159); + _curvea0[359] = _14548; + uint16_t _14549 = (uint16_t)(159); + _curvea0[360] = _14549; + uint16_t _14550 = (uint16_t)(160); + _curvea0[361] = _14550; + uint16_t _14551 = (uint16_t)(160); + _curvea0[362] = _14551; + uint16_t _14552 = (uint16_t)(160); + _curvea0[363] = _14552; + uint16_t _14553 = (uint16_t)(160); + _curvea0[364] = _14553; + uint16_t _14554 = (uint16_t)(161); + _curvea0[365] = _14554; + uint16_t _14555 = (uint16_t)(161); + _curvea0[366] = _14555; + uint16_t _14556 = (uint16_t)(161); + _curvea0[367] = _14556; + uint16_t _14557 = (uint16_t)(161); + _curvea0[368] = _14557; + uint16_t _14558 = (uint16_t)(162); + _curvea0[369] = _14558; + uint16_t _14559 = (uint16_t)(162); + _curvea0[370] = _14559; + uint16_t _14560 = (uint16_t)(162); + _curvea0[371] = _14560; + uint16_t _14561 = (uint16_t)(162); + _curvea0[372] = _14561; + uint16_t _14562 = (uint16_t)(163); + _curvea0[373] = _14562; + uint16_t _14563 = (uint16_t)(163); + _curvea0[374] = _14563; + uint16_t _14564 = (uint16_t)(163); + _curvea0[375] = _14564; + uint16_t _14565 = (uint16_t)(163); + _curvea0[376] = _14565; + uint16_t _14566 = (uint16_t)(164); + _curvea0[377] = _14566; + uint16_t _14567 = (uint16_t)(164); + _curvea0[378] = _14567; + uint16_t _14568 = (uint16_t)(164); + _curvea0[379] = _14568; + uint16_t _14569 = (uint16_t)(164); + _curvea0[380] = _14569; + uint16_t _14570 = (uint16_t)(165); + _curvea0[381] = _14570; + uint16_t _14571 = (uint16_t)(165); + _curvea0[382] = _14571; + uint16_t _14572 = (uint16_t)(165); + _curvea0[383] = _14572; + uint16_t _14573 = (uint16_t)(166); + _curvea0[384] = _14573; + uint16_t _14574 = (uint16_t)(166); + _curvea0[385] = _14574; + uint16_t _14575 = (uint16_t)(166); + _curvea0[386] = _14575; + uint16_t _14576 = (uint16_t)(166); + _curvea0[387] = _14576; + uint16_t _14577 = (uint16_t)(167); + _curvea0[388] = _14577; + uint16_t _14578 = (uint16_t)(167); + _curvea0[389] = _14578; + uint16_t _14579 = (uint16_t)(167); + _curvea0[390] = _14579; + uint16_t _14580 = (uint16_t)(167); + _curvea0[391] = _14580; + uint16_t _14581 = (uint16_t)(167); + _curvea0[392] = _14581; + uint16_t _14582 = (uint16_t)(168); + _curvea0[393] = _14582; + uint16_t _14583 = (uint16_t)(168); + _curvea0[394] = _14583; + uint16_t _14584 = (uint16_t)(168); + _curvea0[395] = _14584; + uint16_t _14585 = (uint16_t)(168); + _curvea0[396] = _14585; + uint16_t _14586 = (uint16_t)(169); + _curvea0[397] = _14586; + uint16_t _14587 = (uint16_t)(169); + _curvea0[398] = _14587; + uint16_t _14588 = (uint16_t)(169); + _curvea0[399] = _14588; + uint16_t _14589 = (uint16_t)(169); + _curvea0[400] = _14589; + uint16_t _14590 = (uint16_t)(170); + _curvea0[401] = _14590; + uint16_t _14591 = (uint16_t)(170); + _curvea0[402] = _14591; + uint16_t _14592 = (uint16_t)(170); + _curvea0[403] = _14592; + uint16_t _14593 = (uint16_t)(170); + _curvea0[404] = _14593; + uint16_t _14594 = (uint16_t)(171); + _curvea0[405] = _14594; + uint16_t _14595 = (uint16_t)(171); + _curvea0[406] = _14595; + uint16_t _14596 = (uint16_t)(171); + _curvea0[407] = _14596; + uint16_t _14597 = (uint16_t)(171); + _curvea0[408] = _14597; + uint16_t _14598 = (uint16_t)(172); + _curvea0[409] = _14598; + uint16_t _14599 = (uint16_t)(172); + _curvea0[410] = _14599; + uint16_t _14600 = (uint16_t)(172); + _curvea0[411] = _14600; + uint16_t _14601 = (uint16_t)(172); + _curvea0[412] = _14601; + uint16_t _14602 = (uint16_t)(173); + _curvea0[413] = _14602; + uint16_t _14603 = (uint16_t)(173); + _curvea0[414] = _14603; + uint16_t _14604 = (uint16_t)(173); + _curvea0[415] = _14604; + uint16_t _14605 = (uint16_t)(173); + _curvea0[416] = _14605; + uint16_t _14606 = (uint16_t)(173); + _curvea0[417] = _14606; + uint16_t _14607 = (uint16_t)(174); + _curvea0[418] = _14607; + uint16_t _14608 = (uint16_t)(174); + _curvea0[419] = _14608; + uint16_t _14609 = (uint16_t)(174); + _curvea0[420] = _14609; + uint16_t _14610 = (uint16_t)(174); + _curvea0[421] = _14610; + uint16_t _14611 = (uint16_t)(175); + _curvea0[422] = _14611; + uint16_t _14612 = (uint16_t)(175); + _curvea0[423] = _14612; + uint16_t _14613 = (uint16_t)(175); + _curvea0[424] = _14613; + uint16_t _14614 = (uint16_t)(175); + _curvea0[425] = _14614; + uint16_t _14615 = (uint16_t)(176); + _curvea0[426] = _14615; + uint16_t _14616 = (uint16_t)(176); + _curvea0[427] = _14616; + uint16_t _14617 = (uint16_t)(176); + _curvea0[428] = _14617; + uint16_t _14618 = (uint16_t)(176); + _curvea0[429] = _14618; + uint16_t _14619 = (uint16_t)(176); + _curvea0[430] = _14619; + uint16_t _14620 = (uint16_t)(177); + _curvea0[431] = _14620; + uint16_t _14621 = (uint16_t)(177); + _curvea0[432] = _14621; + uint16_t _14622 = (uint16_t)(177); + _curvea0[433] = _14622; + uint16_t _14623 = (uint16_t)(177); + _curvea0[434] = _14623; + uint16_t _14624 = (uint16_t)(178); + _curvea0[435] = _14624; + uint16_t _14625 = (uint16_t)(178); + _curvea0[436] = _14625; + uint16_t _14626 = (uint16_t)(178); + _curvea0[437] = _14626; + uint16_t _14627 = (uint16_t)(178); + _curvea0[438] = _14627; + uint16_t _14628 = (uint16_t)(178); + _curvea0[439] = _14628; + uint16_t _14629 = (uint16_t)(179); + _curvea0[440] = _14629; + uint16_t _14630 = (uint16_t)(179); + _curvea0[441] = _14630; + uint16_t _14631 = (uint16_t)(179); + _curvea0[442] = _14631; + uint16_t _14632 = (uint16_t)(179); + _curvea0[443] = _14632; + uint16_t _14633 = (uint16_t)(180); + _curvea0[444] = _14633; + uint16_t _14634 = (uint16_t)(180); + _curvea0[445] = _14634; + uint16_t _14635 = (uint16_t)(180); + _curvea0[446] = _14635; + uint16_t _14636 = (uint16_t)(180); + _curvea0[447] = _14636; + uint16_t _14637 = (uint16_t)(180); + _curvea0[448] = _14637; + uint16_t _14638 = (uint16_t)(181); + _curvea0[449] = _14638; + uint16_t _14639 = (uint16_t)(181); + _curvea0[450] = _14639; + uint16_t _14640 = (uint16_t)(181); + _curvea0[451] = _14640; + uint16_t _14641 = (uint16_t)(181); + _curvea0[452] = _14641; + uint16_t _14642 = (uint16_t)(181); + _curvea0[453] = _14642; + uint16_t _14643 = (uint16_t)(182); + _curvea0[454] = _14643; + uint16_t _14644 = (uint16_t)(182); + _curvea0[455] = _14644; + uint16_t _14645 = (uint16_t)(182); + _curvea0[456] = _14645; + uint16_t _14646 = (uint16_t)(182); + _curvea0[457] = _14646; + uint16_t _14647 = (uint16_t)(183); + _curvea0[458] = _14647; + uint16_t _14648 = (uint16_t)(183); + _curvea0[459] = _14648; + uint16_t _14649 = (uint16_t)(183); + _curvea0[460] = _14649; + uint16_t _14650 = (uint16_t)(183); + _curvea0[461] = _14650; + uint16_t _14651 = (uint16_t)(183); + _curvea0[462] = _14651; + uint16_t _14652 = (uint16_t)(184); + _curvea0[463] = _14652; + uint16_t _14653 = (uint16_t)(184); + _curvea0[464] = _14653; + uint16_t _14654 = (uint16_t)(184); + _curvea0[465] = _14654; + uint16_t _14655 = (uint16_t)(184); + _curvea0[466] = _14655; + uint16_t _14656 = (uint16_t)(184); + _curvea0[467] = _14656; + uint16_t _14657 = (uint16_t)(185); + _curvea0[468] = _14657; + uint16_t _14658 = (uint16_t)(185); + _curvea0[469] = _14658; + uint16_t _14659 = (uint16_t)(185); + _curvea0[470] = _14659; + uint16_t _14660 = (uint16_t)(185); + _curvea0[471] = _14660; + uint16_t _14661 = (uint16_t)(185); + _curvea0[472] = _14661; + uint16_t _14662 = (uint16_t)(186); + _curvea0[473] = _14662; + uint16_t _14663 = (uint16_t)(186); + _curvea0[474] = _14663; + uint16_t _14664 = (uint16_t)(186); + _curvea0[475] = _14664; + uint16_t _14665 = (uint16_t)(186); + _curvea0[476] = _14665; + uint16_t _14666 = (uint16_t)(187); + _curvea0[477] = _14666; + uint16_t _14667 = (uint16_t)(187); + _curvea0[478] = _14667; + uint16_t _14668 = (uint16_t)(187); + _curvea0[479] = _14668; + uint16_t _14669 = (uint16_t)(187); + _curvea0[480] = _14669; + uint16_t _14670 = (uint16_t)(187); + _curvea0[481] = _14670; + uint16_t _14671 = (uint16_t)(188); + _curvea0[482] = _14671; + uint16_t _14672 = (uint16_t)(188); + _curvea0[483] = _14672; + uint16_t _14673 = (uint16_t)(188); + _curvea0[484] = _14673; + uint16_t _14674 = (uint16_t)(188); + _curvea0[485] = _14674; + uint16_t _14675 = (uint16_t)(188); + _curvea0[486] = _14675; + uint16_t _14676 = (uint16_t)(189); + _curvea0[487] = _14676; + uint16_t _14677 = (uint16_t)(189); + _curvea0[488] = _14677; + uint16_t _14678 = (uint16_t)(189); + _curvea0[489] = _14678; + uint16_t _14679 = (uint16_t)(189); + _curvea0[490] = _14679; + uint16_t _14680 = (uint16_t)(189); + _curvea0[491] = _14680; + uint16_t _14681 = (uint16_t)(190); + _curvea0[492] = _14681; + uint16_t _14682 = (uint16_t)(190); + _curvea0[493] = _14682; + uint16_t _14683 = (uint16_t)(190); + _curvea0[494] = _14683; + uint16_t _14684 = (uint16_t)(190); + _curvea0[495] = _14684; + uint16_t _14685 = (uint16_t)(190); + _curvea0[496] = _14685; + uint16_t _14686 = (uint16_t)(190); + _curvea0[497] = _14686; + uint16_t _14687 = (uint16_t)(191); + _curvea0[498] = _14687; + uint16_t _14688 = (uint16_t)(191); + _curvea0[499] = _14688; + uint16_t _14689 = (uint16_t)(191); + _curvea0[500] = _14689; + uint16_t _14690 = (uint16_t)(191); + _curvea0[501] = _14690; + uint16_t _14691 = (uint16_t)(191); + _curvea0[502] = _14691; + uint16_t _14692 = (uint16_t)(192); + _curvea0[503] = _14692; + uint16_t _14693 = (uint16_t)(192); + _curvea0[504] = _14693; + uint16_t _14694 = (uint16_t)(192); + _curvea0[505] = _14694; + uint16_t _14695 = (uint16_t)(192); + _curvea0[506] = _14695; + uint16_t _14696 = (uint16_t)(192); + _curvea0[507] = _14696; + uint16_t _14697 = (uint16_t)(193); + _curvea0[508] = _14697; + uint16_t _14698 = (uint16_t)(193); + _curvea0[509] = _14698; + uint16_t _14699 = (uint16_t)(193); + _curvea0[510] = _14699; + uint16_t _14700 = (uint16_t)(193); + _curvea0[511] = _14700; + uint16_t _14701 = (uint16_t)(193); + _curvea0[512] = _14701; + uint16_t _14702 = (uint16_t)(194); + _curvea0[513] = _14702; + uint16_t _14703 = (uint16_t)(194); + _curvea0[514] = _14703; + uint16_t _14704 = (uint16_t)(194); + _curvea0[515] = _14704; + uint16_t _14705 = (uint16_t)(194); + _curvea0[516] = _14705; + uint16_t _14706 = (uint16_t)(194); + _curvea0[517] = _14706; + uint16_t _14707 = (uint16_t)(195); + _curvea0[518] = _14707; + uint16_t _14708 = (uint16_t)(195); + _curvea0[519] = _14708; + uint16_t _14709 = (uint16_t)(195); + _curvea0[520] = _14709; + uint16_t _14710 = (uint16_t)(195); + _curvea0[521] = _14710; + uint16_t _14711 = (uint16_t)(195); + _curvea0[522] = _14711; + uint16_t _14712 = (uint16_t)(195); + _curvea0[523] = _14712; + uint16_t _14713 = (uint16_t)(196); + _curvea0[524] = _14713; + uint16_t _14714 = (uint16_t)(196); + _curvea0[525] = _14714; + uint16_t _14715 = (uint16_t)(196); + _curvea0[526] = _14715; + uint16_t _14716 = (uint16_t)(196); + _curvea0[527] = _14716; + uint16_t _14717 = (uint16_t)(196); + _curvea0[528] = _14717; + uint16_t _14718 = (uint16_t)(197); + _curvea0[529] = _14718; + uint16_t _14719 = (uint16_t)(197); + _curvea0[530] = _14719; + uint16_t _14720 = (uint16_t)(197); + _curvea0[531] = _14720; + uint16_t _14721 = (uint16_t)(197); + _curvea0[532] = _14721; + uint16_t _14722 = (uint16_t)(197); + _curvea0[533] = _14722; + uint16_t _14723 = (uint16_t)(197); + _curvea0[534] = _14723; + uint16_t _14724 = (uint16_t)(198); + _curvea0[535] = _14724; + uint16_t _14725 = (uint16_t)(198); + _curvea0[536] = _14725; + uint16_t _14726 = (uint16_t)(198); + _curvea0[537] = _14726; + uint16_t _14727 = (uint16_t)(198); + _curvea0[538] = _14727; + uint16_t _14728 = (uint16_t)(198); + _curvea0[539] = _14728; + uint16_t _14729 = (uint16_t)(199); + _curvea0[540] = _14729; + uint16_t _14730 = (uint16_t)(199); + _curvea0[541] = _14730; + uint16_t _14731 = (uint16_t)(199); + _curvea0[542] = _14731; + uint16_t _14732 = (uint16_t)(199); + _curvea0[543] = _14732; + uint16_t _14733 = (uint16_t)(199); + _curvea0[544] = _14733; + uint16_t _14734 = (uint16_t)(199); + _curvea0[545] = _14734; + uint16_t _14735 = (uint16_t)(200); + _curvea0[546] = _14735; + uint16_t _14736 = (uint16_t)(200); + _curvea0[547] = _14736; + uint16_t _14737 = (uint16_t)(200); + _curvea0[548] = _14737; + uint16_t _14738 = (uint16_t)(200); + _curvea0[549] = _14738; + uint16_t _14739 = (uint16_t)(200); + _curvea0[550] = _14739; + uint16_t _14740 = (uint16_t)(200); + _curvea0[551] = _14740; + uint16_t _14741 = (uint16_t)(201); + _curvea0[552] = _14741; + uint16_t _14742 = (uint16_t)(201); + _curvea0[553] = _14742; + uint16_t _14743 = (uint16_t)(201); + _curvea0[554] = _14743; + uint16_t _14744 = (uint16_t)(201); + _curvea0[555] = _14744; + uint16_t _14745 = (uint16_t)(201); + _curvea0[556] = _14745; + uint16_t _14746 = (uint16_t)(202); + _curvea0[557] = _14746; + uint16_t _14747 = (uint16_t)(202); + _curvea0[558] = _14747; + uint16_t _14748 = (uint16_t)(202); + _curvea0[559] = _14748; + uint16_t _14749 = (uint16_t)(202); + _curvea0[560] = _14749; + uint16_t _14750 = (uint16_t)(202); + _curvea0[561] = _14750; + uint16_t _14751 = (uint16_t)(202); + _curvea0[562] = _14751; + uint16_t _14752 = (uint16_t)(203); + _curvea0[563] = _14752; + uint16_t _14753 = (uint16_t)(203); + _curvea0[564] = _14753; + uint16_t _14754 = (uint16_t)(203); + _curvea0[565] = _14754; + uint16_t _14755 = (uint16_t)(203); + _curvea0[566] = _14755; + uint16_t _14756 = (uint16_t)(203); + _curvea0[567] = _14756; + uint16_t _14757 = (uint16_t)(203); + _curvea0[568] = _14757; + uint16_t _14758 = (uint16_t)(204); + _curvea0[569] = _14758; + uint16_t _14759 = (uint16_t)(204); + _curvea0[570] = _14759; + uint16_t _14760 = (uint16_t)(204); + _curvea0[571] = _14760; + uint16_t _14761 = (uint16_t)(204); + _curvea0[572] = _14761; + uint16_t _14762 = (uint16_t)(204); + _curvea0[573] = _14762; + uint16_t _14763 = (uint16_t)(204); + _curvea0[574] = _14763; + uint16_t _14764 = (uint16_t)(205); + _curvea0[575] = _14764; + uint16_t _14765 = (uint16_t)(205); + _curvea0[576] = _14765; + uint16_t _14766 = (uint16_t)(205); + _curvea0[577] = _14766; + uint16_t _14767 = (uint16_t)(205); + _curvea0[578] = _14767; + uint16_t _14768 = (uint16_t)(205); + _curvea0[579] = _14768; + uint16_t _14769 = (uint16_t)(205); + _curvea0[580] = _14769; + uint16_t _14770 = (uint16_t)(206); + _curvea0[581] = _14770; + uint16_t _14771 = (uint16_t)(206); + _curvea0[582] = _14771; + uint16_t _14772 = (uint16_t)(206); + _curvea0[583] = _14772; + uint16_t _14773 = (uint16_t)(206); + _curvea0[584] = _14773; + uint16_t _14774 = (uint16_t)(206); + _curvea0[585] = _14774; + uint16_t _14775 = (uint16_t)(206); + _curvea0[586] = _14775; + uint16_t _14776 = (uint16_t)(207); + _curvea0[587] = _14776; + uint16_t _14777 = (uint16_t)(207); + _curvea0[588] = _14777; + uint16_t _14778 = (uint16_t)(207); + _curvea0[589] = _14778; + uint16_t _14779 = (uint16_t)(207); + _curvea0[590] = _14779; + uint16_t _14780 = (uint16_t)(207); + _curvea0[591] = _14780; + uint16_t _14781 = (uint16_t)(207); + _curvea0[592] = _14781; + uint16_t _14782 = (uint16_t)(208); + _curvea0[593] = _14782; + uint16_t _14783 = (uint16_t)(208); + _curvea0[594] = _14783; + uint16_t _14784 = (uint16_t)(208); + _curvea0[595] = _14784; + uint16_t _14785 = (uint16_t)(208); + _curvea0[596] = _14785; + uint16_t _14786 = (uint16_t)(208); + _curvea0[597] = _14786; + uint16_t _14787 = (uint16_t)(208); + _curvea0[598] = _14787; + uint16_t _14788 = (uint16_t)(209); + _curvea0[599] = _14788; + uint16_t _14789 = (uint16_t)(209); + _curvea0[600] = _14789; + uint16_t _14790 = (uint16_t)(209); + _curvea0[601] = _14790; + uint16_t _14791 = (uint16_t)(209); + _curvea0[602] = _14791; + uint16_t _14792 = (uint16_t)(209); + _curvea0[603] = _14792; + uint16_t _14793 = (uint16_t)(209); + _curvea0[604] = _14793; + uint16_t _14794 = (uint16_t)(209); + _curvea0[605] = _14794; + uint16_t _14795 = (uint16_t)(210); + _curvea0[606] = _14795; + uint16_t _14796 = (uint16_t)(210); + _curvea0[607] = _14796; + uint16_t _14797 = (uint16_t)(210); + _curvea0[608] = _14797; + uint16_t _14798 = (uint16_t)(210); + _curvea0[609] = _14798; + uint16_t _14799 = (uint16_t)(210); + _curvea0[610] = _14799; + uint16_t _14800 = (uint16_t)(210); + _curvea0[611] = _14800; + uint16_t _14801 = (uint16_t)(211); + _curvea0[612] = _14801; + uint16_t _14802 = (uint16_t)(211); + _curvea0[613] = _14802; + uint16_t _14803 = (uint16_t)(211); + _curvea0[614] = _14803; + uint16_t _14804 = (uint16_t)(211); + _curvea0[615] = _14804; + uint16_t _14805 = (uint16_t)(211); + _curvea0[616] = _14805; + uint16_t _14806 = (uint16_t)(211); + _curvea0[617] = _14806; + uint16_t _14807 = (uint16_t)(211); + _curvea0[618] = _14807; + uint16_t _14808 = (uint16_t)(212); + _curvea0[619] = _14808; + uint16_t _14809 = (uint16_t)(212); + _curvea0[620] = _14809; + uint16_t _14810 = (uint16_t)(212); + _curvea0[621] = _14810; + uint16_t _14811 = (uint16_t)(212); + _curvea0[622] = _14811; + uint16_t _14812 = (uint16_t)(212); + _curvea0[623] = _14812; + uint16_t _14813 = (uint16_t)(212); + _curvea0[624] = _14813; + uint16_t _14814 = (uint16_t)(213); + _curvea0[625] = _14814; + uint16_t _14815 = (uint16_t)(213); + _curvea0[626] = _14815; + uint16_t _14816 = (uint16_t)(213); + _curvea0[627] = _14816; + uint16_t _14817 = (uint16_t)(213); + _curvea0[628] = _14817; + uint16_t _14818 = (uint16_t)(213); + _curvea0[629] = _14818; + uint16_t _14819 = (uint16_t)(213); + _curvea0[630] = _14819; + uint16_t _14820 = (uint16_t)(213); + _curvea0[631] = _14820; + uint16_t _14821 = (uint16_t)(214); + _curvea0[632] = _14821; + uint16_t _14822 = (uint16_t)(214); + _curvea0[633] = _14822; + uint16_t _14823 = (uint16_t)(214); + _curvea0[634] = _14823; + uint16_t _14824 = (uint16_t)(214); + _curvea0[635] = _14824; + uint16_t _14825 = (uint16_t)(214); + _curvea0[636] = _14825; + uint16_t _14826 = (uint16_t)(214); + _curvea0[637] = _14826; + uint16_t _14827 = (uint16_t)(214); + _curvea0[638] = _14827; + uint16_t _14828 = (uint16_t)(215); + _curvea0[639] = _14828; + uint16_t _14829 = (uint16_t)(215); + _curvea0[640] = _14829; + uint16_t _14830 = (uint16_t)(215); + _curvea0[641] = _14830; + uint16_t _14831 = (uint16_t)(215); + _curvea0[642] = _14831; + uint16_t _14832 = (uint16_t)(215); + _curvea0[643] = _14832; + uint16_t _14833 = (uint16_t)(215); + _curvea0[644] = _14833; + uint16_t _14834 = (uint16_t)(216); + _curvea0[645] = _14834; + uint16_t _14835 = (uint16_t)(216); + _curvea0[646] = _14835; + uint16_t _14836 = (uint16_t)(216); + _curvea0[647] = _14836; + uint16_t _14837 = (uint16_t)(216); + _curvea0[648] = _14837; + uint16_t _14838 = (uint16_t)(216); + _curvea0[649] = _14838; + uint16_t _14839 = (uint16_t)(216); + _curvea0[650] = _14839; + uint16_t _14840 = (uint16_t)(216); + _curvea0[651] = _14840; + uint16_t _14841 = (uint16_t)(217); + _curvea0[652] = _14841; + uint16_t _14842 = (uint16_t)(217); + _curvea0[653] = _14842; + uint16_t _14843 = (uint16_t)(217); + _curvea0[654] = _14843; + uint16_t _14844 = (uint16_t)(217); + _curvea0[655] = _14844; + uint16_t _14845 = (uint16_t)(217); + _curvea0[656] = _14845; + uint16_t _14846 = (uint16_t)(217); + _curvea0[657] = _14846; + uint16_t _14847 = (uint16_t)(217); + _curvea0[658] = _14847; + uint16_t _14848 = (uint16_t)(218); + _curvea0[659] = _14848; + uint16_t _14849 = (uint16_t)(218); + _curvea0[660] = _14849; + uint16_t _14850 = (uint16_t)(218); + _curvea0[661] = _14850; + uint16_t _14851 = (uint16_t)(218); + _curvea0[662] = _14851; + uint16_t _14852 = (uint16_t)(218); + _curvea0[663] = _14852; + uint16_t _14853 = (uint16_t)(218); + _curvea0[664] = _14853; + uint16_t _14854 = (uint16_t)(218); + _curvea0[665] = _14854; + uint16_t _14855 = (uint16_t)(219); + _curvea0[666] = _14855; + uint16_t _14856 = (uint16_t)(219); + _curvea0[667] = _14856; + uint16_t _14857 = (uint16_t)(219); + _curvea0[668] = _14857; + uint16_t _14858 = (uint16_t)(219); + _curvea0[669] = _14858; + uint16_t _14859 = (uint16_t)(219); + _curvea0[670] = _14859; + uint16_t _14860 = (uint16_t)(219); + _curvea0[671] = _14860; + uint16_t _14861 = (uint16_t)(219); + _curvea0[672] = _14861; + uint16_t _14862 = (uint16_t)(220); + _curvea0[673] = _14862; + uint16_t _14863 = (uint16_t)(220); + _curvea0[674] = _14863; + uint16_t _14864 = (uint16_t)(220); + _curvea0[675] = _14864; + uint16_t _14865 = (uint16_t)(220); + _curvea0[676] = _14865; + uint16_t _14866 = (uint16_t)(220); + _curvea0[677] = _14866; + uint16_t _14867 = (uint16_t)(220); + _curvea0[678] = _14867; + uint16_t _14868 = (uint16_t)(220); + _curvea0[679] = _14868; + uint16_t _14869 = (uint16_t)(220); + _curvea0[680] = _14869; + uint16_t _14870 = (uint16_t)(221); + _curvea0[681] = _14870; + uint16_t _14871 = (uint16_t)(221); + _curvea0[682] = _14871; + uint16_t _14872 = (uint16_t)(221); + _curvea0[683] = _14872; + uint16_t _14873 = (uint16_t)(221); + _curvea0[684] = _14873; + uint16_t _14874 = (uint16_t)(221); + _curvea0[685] = _14874; + uint16_t _14875 = (uint16_t)(221); + _curvea0[686] = _14875; + uint16_t _14876 = (uint16_t)(221); + _curvea0[687] = _14876; + uint16_t _14877 = (uint16_t)(222); + _curvea0[688] = _14877; + uint16_t _14878 = (uint16_t)(222); + _curvea0[689] = _14878; + uint16_t _14879 = (uint16_t)(222); + _curvea0[690] = _14879; + uint16_t _14880 = (uint16_t)(222); + _curvea0[691] = _14880; + uint16_t _14881 = (uint16_t)(222); + _curvea0[692] = _14881; + uint16_t _14882 = (uint16_t)(222); + _curvea0[693] = _14882; + uint16_t _14883 = (uint16_t)(222); + _curvea0[694] = _14883; + uint16_t _14884 = (uint16_t)(223); + _curvea0[695] = _14884; + uint16_t _14885 = (uint16_t)(223); + _curvea0[696] = _14885; + uint16_t _14886 = (uint16_t)(223); + _curvea0[697] = _14886; + uint16_t _14887 = (uint16_t)(223); + _curvea0[698] = _14887; + uint16_t _14888 = (uint16_t)(223); + _curvea0[699] = _14888; + uint16_t _14889 = (uint16_t)(223); + _curvea0[700] = _14889; + uint16_t _14890 = (uint16_t)(223); + _curvea0[701] = _14890; + uint16_t _14891 = (uint16_t)(223); + _curvea0[702] = _14891; + uint16_t _14892 = (uint16_t)(224); + _curvea0[703] = _14892; + uint16_t _14893 = (uint16_t)(224); + _curvea0[704] = _14893; + uint16_t _14894 = (uint16_t)(224); + _curvea0[705] = _14894; + uint16_t _14895 = (uint16_t)(224); + _curvea0[706] = _14895; + uint16_t _14896 = (uint16_t)(224); + _curvea0[707] = _14896; + uint16_t _14897 = (uint16_t)(224); + _curvea0[708] = _14897; + uint16_t _14898 = (uint16_t)(224); + _curvea0[709] = _14898; + uint16_t _14899 = (uint16_t)(224); + _curvea0[710] = _14899; + uint16_t _14900 = (uint16_t)(225); + _curvea0[711] = _14900; + uint16_t _14901 = (uint16_t)(225); + _curvea0[712] = _14901; + uint16_t _14902 = (uint16_t)(225); + _curvea0[713] = _14902; + uint16_t _14903 = (uint16_t)(225); + _curvea0[714] = _14903; + uint16_t _14904 = (uint16_t)(225); + _curvea0[715] = _14904; + uint16_t _14905 = (uint16_t)(225); + _curvea0[716] = _14905; + uint16_t _14906 = (uint16_t)(225); + _curvea0[717] = _14906; + uint16_t _14907 = (uint16_t)(226); + _curvea0[718] = _14907; + uint16_t _14908 = (uint16_t)(226); + _curvea0[719] = _14908; + uint16_t _14909 = (uint16_t)(226); + _curvea0[720] = _14909; + uint16_t _14910 = (uint16_t)(226); + _curvea0[721] = _14910; + uint16_t _14911 = (uint16_t)(226); + _curvea0[722] = _14911; + uint16_t _14912 = (uint16_t)(226); + _curvea0[723] = _14912; + uint16_t _14913 = (uint16_t)(226); + _curvea0[724] = _14913; + uint16_t _14914 = (uint16_t)(226); + _curvea0[725] = _14914; + uint16_t _14915 = (uint16_t)(227); + _curvea0[726] = _14915; + uint16_t _14916 = (uint16_t)(227); + _curvea0[727] = _14916; + uint16_t _14917 = (uint16_t)(227); + _curvea0[728] = _14917; + uint16_t _14918 = (uint16_t)(227); + _curvea0[729] = _14918; + uint16_t _14919 = (uint16_t)(227); + _curvea0[730] = _14919; + uint16_t _14920 = (uint16_t)(227); + _curvea0[731] = _14920; + uint16_t _14921 = (uint16_t)(227); + _curvea0[732] = _14921; + uint16_t _14922 = (uint16_t)(227); + _curvea0[733] = _14922; + uint16_t _14923 = (uint16_t)(228); + _curvea0[734] = _14923; + uint16_t _14924 = (uint16_t)(228); + _curvea0[735] = _14924; + uint16_t _14925 = (uint16_t)(228); + _curvea0[736] = _14925; + uint16_t _14926 = (uint16_t)(228); + _curvea0[737] = _14926; + uint16_t _14927 = (uint16_t)(228); + _curvea0[738] = _14927; + uint16_t _14928 = (uint16_t)(228); + _curvea0[739] = _14928; + uint16_t _14929 = (uint16_t)(228); + _curvea0[740] = _14929; + uint16_t _14930 = (uint16_t)(228); + _curvea0[741] = _14930; + uint16_t _14931 = (uint16_t)(228); + _curvea0[742] = _14931; + uint16_t _14932 = (uint16_t)(229); + _curvea0[743] = _14932; + uint16_t _14933 = (uint16_t)(229); + _curvea0[744] = _14933; + uint16_t _14934 = (uint16_t)(229); + _curvea0[745] = _14934; + uint16_t _14935 = (uint16_t)(229); + _curvea0[746] = _14935; + uint16_t _14936 = (uint16_t)(229); + _curvea0[747] = _14936; + uint16_t _14937 = (uint16_t)(229); + _curvea0[748] = _14937; + uint16_t _14938 = (uint16_t)(229); + _curvea0[749] = _14938; + uint16_t _14939 = (uint16_t)(229); + _curvea0[750] = _14939; + uint16_t _14940 = (uint16_t)(230); + _curvea0[751] = _14940; + uint16_t _14941 = (uint16_t)(230); + _curvea0[752] = _14941; + uint16_t _14942 = (uint16_t)(230); + _curvea0[753] = _14942; + uint16_t _14943 = (uint16_t)(230); + _curvea0[754] = _14943; + uint16_t _14944 = (uint16_t)(230); + _curvea0[755] = _14944; + uint16_t _14945 = (uint16_t)(230); + _curvea0[756] = _14945; + uint16_t _14946 = (uint16_t)(230); + _curvea0[757] = _14946; + uint16_t _14947 = (uint16_t)(230); + _curvea0[758] = _14947; + uint16_t _14948 = (uint16_t)(231); + _curvea0[759] = _14948; + uint16_t _14949 = (uint16_t)(231); + _curvea0[760] = _14949; + uint16_t _14950 = (uint16_t)(231); + _curvea0[761] = _14950; + uint16_t _14951 = (uint16_t)(231); + _curvea0[762] = _14951; + uint16_t _14952 = (uint16_t)(231); + _curvea0[763] = _14952; + uint16_t _14953 = (uint16_t)(231); + _curvea0[764] = _14953; + uint16_t _14954 = (uint16_t)(231); + _curvea0[765] = _14954; + uint16_t _14955 = (uint16_t)(231); + _curvea0[766] = _14955; + uint16_t _14956 = (uint16_t)(231); + _curvea0[767] = _14956; + uint16_t _14957 = (uint16_t)(232); + _curvea0[768] = _14957; + uint16_t _14958 = (uint16_t)(232); + _curvea0[769] = _14958; + uint16_t _14959 = (uint16_t)(232); + _curvea0[770] = _14959; + uint16_t _14960 = (uint16_t)(232); + _curvea0[771] = _14960; + uint16_t _14961 = (uint16_t)(232); + _curvea0[772] = _14961; + uint16_t _14962 = (uint16_t)(232); + _curvea0[773] = _14962; + uint16_t _14963 = (uint16_t)(232); + _curvea0[774] = _14963; + uint16_t _14964 = (uint16_t)(232); + _curvea0[775] = _14964; + uint16_t _14965 = (uint16_t)(233); + _curvea0[776] = _14965; + uint16_t _14966 = (uint16_t)(233); + _curvea0[777] = _14966; + uint16_t _14967 = (uint16_t)(233); + _curvea0[778] = _14967; + uint16_t _14968 = (uint16_t)(233); + _curvea0[779] = _14968; + uint16_t _14969 = (uint16_t)(233); + _curvea0[780] = _14969; + uint16_t _14970 = (uint16_t)(233); + _curvea0[781] = _14970; + uint16_t _14971 = (uint16_t)(233); + _curvea0[782] = _14971; + uint16_t _14972 = (uint16_t)(233); + _curvea0[783] = _14972; + uint16_t _14973 = (uint16_t)(233); + _curvea0[784] = _14973; + uint16_t _14974 = (uint16_t)(234); + _curvea0[785] = _14974; + uint16_t _14975 = (uint16_t)(234); + _curvea0[786] = _14975; + uint16_t _14976 = (uint16_t)(234); + _curvea0[787] = _14976; + uint16_t _14977 = (uint16_t)(234); + _curvea0[788] = _14977; + uint16_t _14978 = (uint16_t)(234); + _curvea0[789] = _14978; + uint16_t _14979 = (uint16_t)(234); + _curvea0[790] = _14979; + uint16_t _14980 = (uint16_t)(234); + _curvea0[791] = _14980; + uint16_t _14981 = (uint16_t)(234); + _curvea0[792] = _14981; + uint16_t _14982 = (uint16_t)(234); + _curvea0[793] = _14982; + uint16_t _14983 = (uint16_t)(235); + _curvea0[794] = _14983; + uint16_t _14984 = (uint16_t)(235); + _curvea0[795] = _14984; + uint16_t _14985 = (uint16_t)(235); + _curvea0[796] = _14985; + uint16_t _14986 = (uint16_t)(235); + _curvea0[797] = _14986; + uint16_t _14987 = (uint16_t)(235); + _curvea0[798] = _14987; + uint16_t _14988 = (uint16_t)(235); + _curvea0[799] = _14988; + uint16_t _14989 = (uint16_t)(235); + _curvea0[800] = _14989; + uint16_t _14990 = (uint16_t)(235); + _curvea0[801] = _14990; + uint16_t _14991 = (uint16_t)(235); + _curvea0[802] = _14991; + uint16_t _14992 = (uint16_t)(236); + _curvea0[803] = _14992; + uint16_t _14993 = (uint16_t)(236); + _curvea0[804] = _14993; + uint16_t _14994 = (uint16_t)(236); + _curvea0[805] = _14994; + uint16_t _14995 = (uint16_t)(236); + _curvea0[806] = _14995; + uint16_t _14996 = (uint16_t)(236); + _curvea0[807] = _14996; + uint16_t _14997 = (uint16_t)(236); + _curvea0[808] = _14997; + uint16_t _14998 = (uint16_t)(236); + _curvea0[809] = _14998; + uint16_t _14999 = (uint16_t)(236); + _curvea0[810] = _14999; + uint16_t _15000 = (uint16_t)(236); + _curvea0[811] = _15000; + uint16_t _15001 = (uint16_t)(237); + _curvea0[812] = _15001; + uint16_t _15002 = (uint16_t)(237); + _curvea0[813] = _15002; + uint16_t _15003 = (uint16_t)(237); + _curvea0[814] = _15003; + uint16_t _15004 = (uint16_t)(237); + _curvea0[815] = _15004; + uint16_t _15005 = (uint16_t)(237); + _curvea0[816] = _15005; + uint16_t _15006 = (uint16_t)(237); + _curvea0[817] = _15006; + uint16_t _15007 = (uint16_t)(237); + _curvea0[818] = _15007; + uint16_t _15008 = (uint16_t)(237); + _curvea0[819] = _15008; + uint16_t _15009 = (uint16_t)(237); + _curvea0[820] = _15009; + uint16_t _15010 = (uint16_t)(237); + _curvea0[821] = _15010; + uint16_t _15011 = (uint16_t)(238); + _curvea0[822] = _15011; + uint16_t _15012 = (uint16_t)(238); + _curvea0[823] = _15012; + uint16_t _15013 = (uint16_t)(238); + _curvea0[824] = _15013; + uint16_t _15014 = (uint16_t)(238); + _curvea0[825] = _15014; + uint16_t _15015 = (uint16_t)(238); + _curvea0[826] = _15015; + uint16_t _15016 = (uint16_t)(238); + _curvea0[827] = _15016; + uint16_t _15017 = (uint16_t)(238); + _curvea0[828] = _15017; + uint16_t _15018 = (uint16_t)(238); + _curvea0[829] = _15018; + uint16_t _15019 = (uint16_t)(238); + _curvea0[830] = _15019; + uint16_t _15020 = (uint16_t)(239); + _curvea0[831] = _15020; + uint16_t _15021 = (uint16_t)(239); + _curvea0[832] = _15021; + uint16_t _15022 = (uint16_t)(239); + _curvea0[833] = _15022; + uint16_t _15023 = (uint16_t)(239); + _curvea0[834] = _15023; + uint16_t _15024 = (uint16_t)(239); + _curvea0[835] = _15024; + uint16_t _15025 = (uint16_t)(239); + _curvea0[836] = _15025; + uint16_t _15026 = (uint16_t)(239); + _curvea0[837] = _15026; + uint16_t _15027 = (uint16_t)(239); + _curvea0[838] = _15027; + uint16_t _15028 = (uint16_t)(239); + _curvea0[839] = _15028; + uint16_t _15029 = (uint16_t)(239); + _curvea0[840] = _15029; + uint16_t _15030 = (uint16_t)(240); + _curvea0[841] = _15030; + uint16_t _15031 = (uint16_t)(240); + _curvea0[842] = _15031; + uint16_t _15032 = (uint16_t)(240); + _curvea0[843] = _15032; + uint16_t _15033 = (uint16_t)(240); + _curvea0[844] = _15033; + uint16_t _15034 = (uint16_t)(240); + _curvea0[845] = _15034; + uint16_t _15035 = (uint16_t)(240); + _curvea0[846] = _15035; + uint16_t _15036 = (uint16_t)(240); + _curvea0[847] = _15036; + uint16_t _15037 = (uint16_t)(240); + _curvea0[848] = _15037; + uint16_t _15038 = (uint16_t)(240); + _curvea0[849] = _15038; + uint16_t _15039 = (uint16_t)(240); + _curvea0[850] = _15039; + uint16_t _15040 = (uint16_t)(241); + _curvea0[851] = _15040; + uint16_t _15041 = (uint16_t)(241); + _curvea0[852] = _15041; + uint16_t _15042 = (uint16_t)(241); + _curvea0[853] = _15042; + uint16_t _15043 = (uint16_t)(241); + _curvea0[854] = _15043; + uint16_t _15044 = (uint16_t)(241); + _curvea0[855] = _15044; + uint16_t _15045 = (uint16_t)(241); + _curvea0[856] = _15045; + uint16_t _15046 = (uint16_t)(241); + _curvea0[857] = _15046; + uint16_t _15047 = (uint16_t)(241); + _curvea0[858] = _15047; + uint16_t _15048 = (uint16_t)(241); + _curvea0[859] = _15048; + uint16_t _15049 = (uint16_t)(241); + _curvea0[860] = _15049; + uint16_t _15050 = (uint16_t)(242); + _curvea0[861] = _15050; + uint16_t _15051 = (uint16_t)(242); + _curvea0[862] = _15051; + uint16_t _15052 = (uint16_t)(242); + _curvea0[863] = _15052; + uint16_t _15053 = (uint16_t)(242); + _curvea0[864] = _15053; + uint16_t _15054 = (uint16_t)(242); + _curvea0[865] = _15054; + uint16_t _15055 = (uint16_t)(242); + _curvea0[866] = _15055; + uint16_t _15056 = (uint16_t)(242); + _curvea0[867] = _15056; + uint16_t _15057 = (uint16_t)(242); + _curvea0[868] = _15057; + uint16_t _15058 = (uint16_t)(242); + _curvea0[869] = _15058; + uint16_t _15059 = (uint16_t)(242); + _curvea0[870] = _15059; + uint16_t _15060 = (uint16_t)(243); + _curvea0[871] = _15060; + uint16_t _15061 = (uint16_t)(243); + _curvea0[872] = _15061; + uint16_t _15062 = (uint16_t)(243); + _curvea0[873] = _15062; + uint16_t _15063 = (uint16_t)(243); + _curvea0[874] = _15063; + uint16_t _15064 = (uint16_t)(243); + _curvea0[875] = _15064; + uint16_t _15065 = (uint16_t)(243); + _curvea0[876] = _15065; + uint16_t _15066 = (uint16_t)(243); + _curvea0[877] = _15066; + uint16_t _15067 = (uint16_t)(243); + _curvea0[878] = _15067; + uint16_t _15068 = (uint16_t)(243); + _curvea0[879] = _15068; + uint16_t _15069 = (uint16_t)(243); + _curvea0[880] = _15069; + uint16_t _15070 = (uint16_t)(244); + _curvea0[881] = _15070; + uint16_t _15071 = (uint16_t)(244); + _curvea0[882] = _15071; + uint16_t _15072 = (uint16_t)(244); + _curvea0[883] = _15072; + uint16_t _15073 = (uint16_t)(244); + _curvea0[884] = _15073; + uint16_t _15074 = (uint16_t)(244); + _curvea0[885] = _15074; + uint16_t _15075 = (uint16_t)(244); + _curvea0[886] = _15075; + uint16_t _15076 = (uint16_t)(244); + _curvea0[887] = _15076; + uint16_t _15077 = (uint16_t)(244); + _curvea0[888] = _15077; + uint16_t _15078 = (uint16_t)(244); + _curvea0[889] = _15078; + uint16_t _15079 = (uint16_t)(244); + _curvea0[890] = _15079; + uint16_t _15080 = (uint16_t)(244); + _curvea0[891] = _15080; + uint16_t _15081 = (uint16_t)(245); + _curvea0[892] = _15081; + uint16_t _15082 = (uint16_t)(245); + _curvea0[893] = _15082; + uint16_t _15083 = (uint16_t)(245); + _curvea0[894] = _15083; + uint16_t _15084 = (uint16_t)(245); + _curvea0[895] = _15084; + uint16_t _15085 = (uint16_t)(245); + _curvea0[896] = _15085; + uint16_t _15086 = (uint16_t)(245); + _curvea0[897] = _15086; + uint16_t _15087 = (uint16_t)(245); + _curvea0[898] = _15087; + uint16_t _15088 = (uint16_t)(245); + _curvea0[899] = _15088; + uint16_t _15089 = (uint16_t)(245); + _curvea0[900] = _15089; + uint16_t _15090 = (uint16_t)(245); + _curvea0[901] = _15090; + uint16_t _15091 = (uint16_t)(245); + _curvea0[902] = _15091; + uint16_t _15092 = (uint16_t)(246); + _curvea0[903] = _15092; + uint16_t _15093 = (uint16_t)(246); + _curvea0[904] = _15093; + uint16_t _15094 = (uint16_t)(246); + _curvea0[905] = _15094; + uint16_t _15095 = (uint16_t)(246); + _curvea0[906] = _15095; + uint16_t _15096 = (uint16_t)(246); + _curvea0[907] = _15096; + uint16_t _15097 = (uint16_t)(246); + _curvea0[908] = _15097; + uint16_t _15098 = (uint16_t)(246); + _curvea0[909] = _15098; + uint16_t _15099 = (uint16_t)(246); + _curvea0[910] = _15099; + uint16_t _15100 = (uint16_t)(246); + _curvea0[911] = _15100; + uint16_t _15101 = (uint16_t)(246); + _curvea0[912] = _15101; + uint16_t _15102 = (uint16_t)(246); + _curvea0[913] = _15102; + uint16_t _15103 = (uint16_t)(247); + _curvea0[914] = _15103; + uint16_t _15104 = (uint16_t)(247); + _curvea0[915] = _15104; + uint16_t _15105 = (uint16_t)(247); + _curvea0[916] = _15105; + uint16_t _15106 = (uint16_t)(247); + _curvea0[917] = _15106; + uint16_t _15107 = (uint16_t)(247); + _curvea0[918] = _15107; + uint16_t _15108 = (uint16_t)(247); + _curvea0[919] = _15108; + uint16_t _15109 = (uint16_t)(247); + _curvea0[920] = _15109; + uint16_t _15110 = (uint16_t)(247); + _curvea0[921] = _15110; + uint16_t _15111 = (uint16_t)(247); + _curvea0[922] = _15111; + uint16_t _15112 = (uint16_t)(247); + _curvea0[923] = _15112; + uint16_t _15113 = (uint16_t)(247); + _curvea0[924] = _15113; + uint16_t _15114 = (uint16_t)(248); + _curvea0[925] = _15114; + uint16_t _15115 = (uint16_t)(248); + _curvea0[926] = _15115; + uint16_t _15116 = (uint16_t)(248); + _curvea0[927] = _15116; + uint16_t _15117 = (uint16_t)(248); + _curvea0[928] = _15117; + uint16_t _15118 = (uint16_t)(248); + _curvea0[929] = _15118; + uint16_t _15119 = (uint16_t)(248); + _curvea0[930] = _15119; + uint16_t _15120 = (uint16_t)(248); + _curvea0[931] = _15120; + uint16_t _15121 = (uint16_t)(248); + _curvea0[932] = _15121; + uint16_t _15122 = (uint16_t)(248); + _curvea0[933] = _15122; + uint16_t _15123 = (uint16_t)(248); + _curvea0[934] = _15123; + uint16_t _15124 = (uint16_t)(248); + _curvea0[935] = _15124; + uint16_t _15125 = (uint16_t)(249); + _curvea0[936] = _15125; + uint16_t _15126 = (uint16_t)(249); + _curvea0[937] = _15126; + uint16_t _15127 = (uint16_t)(249); + _curvea0[938] = _15127; + uint16_t _15128 = (uint16_t)(249); + _curvea0[939] = _15128; + uint16_t _15129 = (uint16_t)(249); + _curvea0[940] = _15129; + uint16_t _15130 = (uint16_t)(249); + _curvea0[941] = _15130; + uint16_t _15131 = (uint16_t)(249); + _curvea0[942] = _15131; + uint16_t _15132 = (uint16_t)(249); + _curvea0[943] = _15132; + uint16_t _15133 = (uint16_t)(249); + _curvea0[944] = _15133; + uint16_t _15134 = (uint16_t)(249); + _curvea0[945] = _15134; + uint16_t _15135 = (uint16_t)(249); + _curvea0[946] = _15135; + uint16_t _15136 = (uint16_t)(249); + _curvea0[947] = _15136; + uint16_t _15137 = (uint16_t)(250); + _curvea0[948] = _15137; + uint16_t _15138 = (uint16_t)(250); + _curvea0[949] = _15138; + uint16_t _15139 = (uint16_t)(250); + _curvea0[950] = _15139; + uint16_t _15140 = (uint16_t)(250); + _curvea0[951] = _15140; + uint16_t _15141 = (uint16_t)(250); + _curvea0[952] = _15141; + uint16_t _15142 = (uint16_t)(250); + _curvea0[953] = _15142; + uint16_t _15143 = (uint16_t)(250); + _curvea0[954] = _15143; + uint16_t _15144 = (uint16_t)(250); + _curvea0[955] = _15144; + uint16_t _15145 = (uint16_t)(250); + _curvea0[956] = _15145; + uint16_t _15146 = (uint16_t)(250); + _curvea0[957] = _15146; + uint16_t _15147 = (uint16_t)(250); + _curvea0[958] = _15147; + uint16_t _15148 = (uint16_t)(250); + _curvea0[959] = _15148; + uint16_t _15149 = (uint16_t)(251); + _curvea0[960] = _15149; + uint16_t _15150 = (uint16_t)(251); + _curvea0[961] = _15150; + uint16_t _15151 = (uint16_t)(251); + _curvea0[962] = _15151; + uint16_t _15152 = (uint16_t)(251); + _curvea0[963] = _15152; + uint16_t _15153 = (uint16_t)(251); + _curvea0[964] = _15153; + uint16_t _15154 = (uint16_t)(251); + _curvea0[965] = _15154; + uint16_t _15155 = (uint16_t)(251); + _curvea0[966] = _15155; + uint16_t _15156 = (uint16_t)(251); + _curvea0[967] = _15156; + uint16_t _15157 = (uint16_t)(251); + _curvea0[968] = _15157; + uint16_t _15158 = (uint16_t)(251); + _curvea0[969] = _15158; + uint16_t _15159 = (uint16_t)(251); + _curvea0[970] = _15159; + uint16_t _15160 = (uint16_t)(251); + _curvea0[971] = _15160; + uint16_t _15161 = (uint16_t)(252); + _curvea0[972] = _15161; + uint16_t _15162 = (uint16_t)(252); + _curvea0[973] = _15162; + uint16_t _15163 = (uint16_t)(252); + _curvea0[974] = _15163; + uint16_t _15164 = (uint16_t)(252); + _curvea0[975] = _15164; + uint16_t _15165 = (uint16_t)(252); + _curvea0[976] = _15165; + uint16_t _15166 = (uint16_t)(252); + _curvea0[977] = _15166; + uint16_t _15167 = (uint16_t)(252); + _curvea0[978] = _15167; + uint16_t _15168 = (uint16_t)(252); + _curvea0[979] = _15168; + uint16_t _15169 = (uint16_t)(252); + _curvea0[980] = _15169; + uint16_t _15170 = (uint16_t)(252); + _curvea0[981] = _15170; + uint16_t _15171 = (uint16_t)(252); + _curvea0[982] = _15171; + uint16_t _15172 = (uint16_t)(252); + _curvea0[983] = _15172; + uint16_t _15173 = (uint16_t)(252); + _curvea0[984] = _15173; + uint16_t _15174 = (uint16_t)(253); + _curvea0[985] = _15174; + uint16_t _15175 = (uint16_t)(253); + _curvea0[986] = _15175; + uint16_t _15176 = (uint16_t)(253); + _curvea0[987] = _15176; + uint16_t _15177 = (uint16_t)(253); + _curvea0[988] = _15177; + uint16_t _15178 = (uint16_t)(253); + _curvea0[989] = _15178; + uint16_t _15179 = (uint16_t)(253); + _curvea0[990] = _15179; + uint16_t _15180 = (uint16_t)(253); + _curvea0[991] = _15180; + uint16_t _15181 = (uint16_t)(253); + _curvea0[992] = _15181; + uint16_t _15182 = (uint16_t)(253); + _curvea0[993] = _15182; + uint16_t _15183 = (uint16_t)(253); + _curvea0[994] = _15183; + uint16_t _15184 = (uint16_t)(253); + _curvea0[995] = _15184; + uint16_t _15185 = (uint16_t)(253); + _curvea0[996] = _15185; + uint16_t _15186 = (uint16_t)(253); + _curvea0[997] = _15186; + uint16_t _15187 = (uint16_t)(254); + _curvea0[998] = _15187; + uint16_t _15188 = (uint16_t)(254); + _curvea0[999] = _15188; + uint16_t _15189 = (uint16_t)(254); + _curvea0[1000] = _15189; + uint16_t _15190 = (uint16_t)(254); + _curvea0[1001] = _15190; + uint16_t _15191 = (uint16_t)(254); + _curvea0[1002] = _15191; + uint16_t _15192 = (uint16_t)(254); + _curvea0[1003] = _15192; + uint16_t _15193 = (uint16_t)(254); + _curvea0[1004] = _15193; + uint16_t _15194 = (uint16_t)(254); + _curvea0[1005] = _15194; + uint16_t _15195 = (uint16_t)(254); + _curvea0[1006] = _15195; + uint16_t _15196 = (uint16_t)(254); + _curvea0[1007] = _15196; + uint16_t _15197 = (uint16_t)(254); + _curvea0[1008] = _15197; + uint16_t _15198 = (uint16_t)(254); + _curvea0[1009] = _15198; + uint16_t _15199 = (uint16_t)(254); + _curvea0[1010] = _15199; + uint16_t _15200 = (uint16_t)(255); + _curvea0[1011] = _15200; + uint16_t _15201 = (uint16_t)(255); + _curvea0[1012] = _15201; + uint16_t _15202 = (uint16_t)(255); + _curvea0[1013] = _15202; + uint16_t _15203 = (uint16_t)(255); + _curvea0[1014] = _15203; + uint16_t _15204 = (uint16_t)(255); + _curvea0[1015] = _15204; + uint16_t _15205 = (uint16_t)(255); + _curvea0[1016] = _15205; + uint16_t _15206 = (uint16_t)(255); + _curvea0[1017] = _15206; + uint16_t _15207 = (uint16_t)(255); + _curvea0[1018] = _15207; + uint16_t _15208 = (uint16_t)(255); + _curvea0[1019] = _15208; + uint16_t _15209 = (uint16_t)(255); + _curvea0[1020] = _15209; + uint16_t _15210 = (uint16_t)(255); + _curvea0[1021] = _15210; + uint16_t _15211 = (uint16_t)(255); + _curvea0[1022] = _15211; + uint16_t _15212 = (uint16_t)(255); + _curvea0[1023] = _15212; + + int16_t _15213 = (int16_t)(1023); + int16_t _15214 = min(_corrected_stencil_12, _15213); + int16_t _15215 = (int16_t)(0); + int16_t _15216 = max(_15214, _15215); + uint16_t _15217 = (uint16_t)(_15216); + int32_t _15218 = (int32_t)(_15217); + uint16_t _15219 = ((const uint16_t *)_curvea0)[_15218]; + return _15219; +} + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 0) +hw_uint<16> hcompute_hw_output_glb_stencil(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_1 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_1; +} + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_1(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_2 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_2; +} + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_2(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_3 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_3; +} + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 0) +hw_uint<16> hcompute_hw_output_glb_stencil_3(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_4 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_4; +} + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_4(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_5 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_5; +} + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_5(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_6 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_6; +} + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 0) +hw_uint<16> hcompute_hw_output_glb_stencil_6(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_7 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_7; +} + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_7(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_8 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_8; +} + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_8(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_9 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_9; +} + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 0) +hw_uint<16> hcompute_hw_output_glb_stencil_9(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_10 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_10; +} + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_10(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_11 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_11; +} + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_11(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_12 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_12; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_1 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_1; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_1(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_2 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_2; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_2(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_3 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_3; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_3(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_4 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_4; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_4(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_5 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_5; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_5(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_6 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_6; +} + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_6(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_7 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_7; +} + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_7(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_8 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_8; +} + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_8(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_9 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_9; +} + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_9(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_10 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_10; +} + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_10(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_11 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_11; +} + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_11(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_12 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_12; +} + diff --git a/camera_pipeline_2x2_unroll_compute.h b/camera_pipeline_2x2_unroll_compute.h new file mode 100644 index 000000000..38bffd4b8 --- /dev/null +++ b/camera_pipeline_2x2_unroll_compute.h @@ -0,0 +1,26493 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_1(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_2 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_2(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_3 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_3(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_4 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_4; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_1 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_1; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_1(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_2 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_2; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_2(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_3 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_3; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_3(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_4 = (uint16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_4; +} + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 2)))))) +hw_uint<16> hcompute_denoised_1_stencil(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_1 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_2 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_3 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_4 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_5 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _372 = max(_hw_input_global_wrapper_global_wrapper_stencil_4, _hw_input_global_wrapper_global_wrapper_stencil_5); + uint16_t _373 = max(_hw_input_global_wrapper_global_wrapper_stencil_3, _372); + uint16_t _374 = max(_hw_input_global_wrapper_global_wrapper_stencil_2, _373); + uint16_t _375 = min(_hw_input_global_wrapper_global_wrapper_stencil_1, _374); + return _375; +} + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 3)))))) +hw_uint<16> hcompute_denoised_1_stencil_1(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_10 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_6 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_7 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_8 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_9 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _395 = max(_hw_input_global_wrapper_global_wrapper_stencil_9, _hw_input_global_wrapper_global_wrapper_stencil_10); + uint16_t _396 = max(_hw_input_global_wrapper_global_wrapper_stencil_8, _395); + uint16_t _397 = max(_hw_input_global_wrapper_global_wrapper_stencil_7, _396); + uint16_t _398 = min(_hw_input_global_wrapper_global_wrapper_stencil_6, _397); + return _398; +} + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 2)))))) +hw_uint<16> hcompute_denoised_1_stencil_2(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_11 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_12 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_13 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_14 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_15 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _419 = max(_hw_input_global_wrapper_global_wrapper_stencil_14, _hw_input_global_wrapper_global_wrapper_stencil_15); + uint16_t _420 = max(_hw_input_global_wrapper_global_wrapper_stencil_13, _419); + uint16_t _421 = max(_hw_input_global_wrapper_global_wrapper_stencil_12, _420); + uint16_t _422 = min(_hw_input_global_wrapper_global_wrapper_stencil_11, _421); + return _422; +} + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 3)))))) +hw_uint<16> hcompute_denoised_1_stencil_3(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_16 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_17 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_18 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_19 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_20 = (uint16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>()); + + uint16_t _443 = max(_hw_input_global_wrapper_global_wrapper_stencil_19, _hw_input_global_wrapper_global_wrapper_stencil_20); + uint16_t _444 = max(_hw_input_global_wrapper_global_wrapper_stencil_18, _443); + uint16_t _445 = max(_hw_input_global_wrapper_global_wrapper_stencil_17, _444); + uint16_t _446 = min(_hw_input_global_wrapper_global_wrapper_stencil_16, _445); + return _446; +} + +//store is: b_b.stencil((b_b_s0_x_x*2), (b_b_s0_y_yio*2)) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), ((b_b_s0_y_yio*4) + 1)) +hw_uint<16> hcompute_b_b_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_1 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_1; +} + +//store is: b_b.stencil((b_b_s0_x_x*2), ((b_b_s0_y_yio*2) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), ((b_b_s0_y_yio*4) + 3)) +hw_uint<16> hcompute_b_b_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_2 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_2; +} + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), (b_b_s0_y_yio*2)) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), ((b_b_s0_y_yio*4) + 1)) +hw_uint<16> hcompute_b_b_stencil_2(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_3 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_3; +} + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), ((b_b_s0_y_yio*2) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), ((b_b_s0_y_yio*4) + 3)) +hw_uint<16> hcompute_b_b_stencil_3(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_4 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_4; +} + +//store is: g_gb.stencil((g_gb_s0_x_x*2), (g_gb_s0_y_yio*2)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), ((g_gb_s0_y_yio*4) + 1)) +hw_uint<16> hcompute_g_gb_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_5 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_5; +} + +//store is: g_gb.stencil((g_gb_s0_x_x*2), ((g_gb_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), ((g_gb_s0_y_yio*4) + 3)) +hw_uint<16> hcompute_g_gb_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_6 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_6; +} + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), (g_gb_s0_y_yio*2)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), ((g_gb_s0_y_yio*4) + 1)) +hw_uint<16> hcompute_g_gb_stencil_2(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_7 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_7; +} + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), ((g_gb_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), ((g_gb_s0_y_yio*4) + 3)) +hw_uint<16> hcompute_g_gb_stencil_3(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_8 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_8; +} + +//store is: g_gr.stencil((g_gr_s0_x_x*2), (g_gr_s0_y_yio*2)) = denoised$1.stencil((g_gr_s0_x_x*4), (g_gr_s0_y_yio*4)) +hw_uint<16> hcompute_g_gr_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_9 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_9; +} + +//store is: g_gr.stencil((g_gr_s0_x_x*2), ((g_gr_s0_y_yio*2) + 1)) = denoised$1.stencil((g_gr_s0_x_x*4), ((g_gr_s0_y_yio*4) + 2)) +hw_uint<16> hcompute_g_gr_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_10 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_10; +} + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), (g_gr_s0_y_yio*2)) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), (g_gr_s0_y_yio*4)) +hw_uint<16> hcompute_g_gr_stencil_2(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_11 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_11; +} + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), ((g_gr_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), ((g_gr_s0_y_yio*4) + 2)) +hw_uint<16> hcompute_g_gr_stencil_3(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_12 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_12; +} + +//store is: g_b.stencil((g_b_s0_x_x*2), (g_b_s0_y_yio*2)) = select((absd(g_gb.stencil((g_b_s0_x_x*2), (g_b_s0_y_yio*2)), g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)), g_gr.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)))), ((g_gb.stencil((g_b_s0_x_x*2), (g_b_s0_y_yio*2)) + g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)) + g_gr.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)))/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_1 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_2 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_1 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_2 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _560 = _g_gb_stencil_1 + _g_gb_stencil_2; + uint16_t _561 = (uint16_t)(1); + uint16_t _562 = _560 >> _561; + uint16_t _563 = _g_gr_stencil_1 + _g_gr_stencil_2; + uint16_t _564 = _563 >> _561; + uint16_t _565 = _g_gb_stencil_2 - _g_gb_stencil_1; + uint16_t _566 = _g_gb_stencil_1 - _g_gb_stencil_2; + bool _567 = _g_gb_stencil_1 < _g_gb_stencil_2; + uint16_t _568 = (uint16_t)(_567 ? _565 : _566); + uint16_t _569 = _568; + uint16_t _570 = _g_gr_stencil_2 - _g_gr_stencil_1; + uint16_t _571 = _g_gr_stencil_1 - _g_gr_stencil_2; + bool _572 = _g_gr_stencil_1 < _g_gr_stencil_2; + uint16_t _573 = (uint16_t)(_572 ? _570 : _571); + uint16_t _574 = _573; + bool _575 = _569 < _574; + uint16_t _576 = (uint16_t)(_575 ? _562 : _564); + return _576; +} + +//store is: g_b.stencil((g_b_s0_x_x*2), ((g_b_s0_y_yio*2) + 1)) = select((absd(g_gb.stencil((g_b_s0_x_x*2), ((g_b_s0_y_yio*2) + 1)), g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 2)), g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)))), ((g_gb.stencil((g_b_s0_x_x*2), ((g_b_s0_y_yio*2) + 1)) + g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 2)) + g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil_1(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_3 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_4 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_3 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_4 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _611 = _g_gb_stencil_3 + _g_gb_stencil_4; + uint16_t _612 = (uint16_t)(1); + uint16_t _613 = _611 >> _612; + uint16_t _614 = _g_gr_stencil_3 + _g_gr_stencil_4; + uint16_t _615 = _614 >> _612; + uint16_t _616 = _g_gb_stencil_4 - _g_gb_stencil_3; + uint16_t _617 = _g_gb_stencil_3 - _g_gb_stencil_4; + bool _618 = _g_gb_stencil_3 < _g_gb_stencil_4; + uint16_t _619 = (uint16_t)(_618 ? _616 : _617); + uint16_t _620 = _619; + uint16_t _621 = _g_gr_stencil_4 - _g_gr_stencil_3; + uint16_t _622 = _g_gr_stencil_3 - _g_gr_stencil_4; + bool _623 = _g_gr_stencil_3 < _g_gr_stencil_4; + uint16_t _624 = (uint16_t)(_623 ? _621 : _622); + uint16_t _625 = _624; + bool _626 = _620 < _625; + uint16_t _627 = (uint16_t)(_626 ? _613 : _615); + return _627; +} + +//store is: g_b.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)) = select((absd(g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)), g_gb.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)), g_gr.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2)))), ((g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)) + g_gb.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)) + g_gr.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2)))/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil_2(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_5 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_6 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_5 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_6 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _663 = _g_gb_stencil_5 + _g_gb_stencil_6; + uint16_t _664 = (uint16_t)(1); + uint16_t _665 = _663 >> _664; + uint16_t _666 = _g_gr_stencil_5 + _g_gr_stencil_6; + uint16_t _667 = _666 >> _664; + uint16_t _668 = _g_gb_stencil_6 - _g_gb_stencil_5; + uint16_t _669 = _g_gb_stencil_5 - _g_gb_stencil_6; + bool _670 = _g_gb_stencil_5 < _g_gb_stencil_6; + uint16_t _671 = (uint16_t)(_670 ? _668 : _669); + uint16_t _672 = _671; + uint16_t _673 = _g_gr_stencil_6 - _g_gr_stencil_5; + uint16_t _674 = _g_gr_stencil_5 - _g_gr_stencil_6; + bool _675 = _g_gr_stencil_5 < _g_gr_stencil_6; + uint16_t _676 = (uint16_t)(_675 ? _673 : _674); + uint16_t _677 = _676; + bool _678 = _672 < _677; + uint16_t _679 = (uint16_t)(_678 ? _665 : _667); + return _679; +} + +//store is: g_b.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)) = select((absd(g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)), g_gb.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 2)), g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)))), ((g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)) + g_gb.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 2)) + g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil_3(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_7 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_8 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_7 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_8 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _715 = _g_gb_stencil_7 + _g_gb_stencil_8; + uint16_t _716 = (uint16_t)(1); + uint16_t _717 = _715 >> _716; + uint16_t _718 = _g_gr_stencil_7 + _g_gr_stencil_8; + uint16_t _719 = _718 >> _716; + uint16_t _720 = _g_gb_stencil_8 - _g_gb_stencil_7; + uint16_t _721 = _g_gb_stencil_7 - _g_gb_stencil_8; + bool _722 = _g_gb_stencil_7 < _g_gb_stencil_8; + uint16_t _723 = (uint16_t)(_722 ? _720 : _721); + uint16_t _724 = _723; + uint16_t _725 = _g_gr_stencil_8 - _g_gr_stencil_7; + uint16_t _726 = _g_gr_stencil_7 - _g_gr_stencil_8; + bool _727 = _g_gr_stencil_7 < _g_gr_stencil_8; + uint16_t _728 = (uint16_t)(_727 ? _725 : _726); + uint16_t _729 = _728; + bool _730 = _724 < _729; + uint16_t _731 = (uint16_t)(_730 ? _717 : _719); + return _731; +} + +//store is: b_gb.stencil((b_gb_s0_x_x*2), (b_gb_s0_y_yio*2)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) + ((b_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 1)) + b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 1)) + g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_1 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_2 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_1 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_2 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gb_stencil_9 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _768 = _b_b_stencil_1 + _b_b_stencil_2; + uint16_t _769 = (uint16_t)(1); + uint16_t _770 = _768 >> _769; + uint16_t _771 = _g_gb_stencil_9 + _770; + uint16_t _772 = _g_b_stencil_1 + _g_b_stencil_2; + uint16_t _773 = _772 >> _769; + uint16_t _774 = _771 - _773; + return _774; +} + +//store is: b_gb.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)) + ((b_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 2)) + b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 2)) + g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil_1(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_3 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_4 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_3 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_4 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gb_stencil_10 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _798 = _b_b_stencil_3 + _b_b_stencil_4; + uint16_t _799 = (uint16_t)(1); + uint16_t _800 = _798 >> _799; + uint16_t _801 = _g_gb_stencil_10 + _800; + uint16_t _802 = _g_b_stencil_3 + _g_b_stencil_4; + uint16_t _803 = _802 >> _799; + uint16_t _804 = _801 - _803; + return _804; +} + +//store is: b_gb.stencil(((b_gb_s0_x_x*2) + 1), (b_gb_s0_y_yio*2)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) + b_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) + g_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil_2(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_5 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_6 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_5 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_6 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gb_stencil_11 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _829 = _b_b_stencil_5 + _b_b_stencil_6; + uint16_t _830 = (uint16_t)(1); + uint16_t _831 = _829 >> _830; + uint16_t _832 = _g_gb_stencil_11 + _831; + uint16_t _833 = _g_b_stencil_5 + _g_b_stencil_6; + uint16_t _834 = _833 >> _830; + uint16_t _835 = _832 - _834; + return _835; +} + +//store is: b_gb.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 2)) + ((b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)) + b_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)) + g_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil_3(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_7 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_8 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_7 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_8 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gb_stencil_12 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _860 = _b_b_stencil_7 + _b_b_stencil_8; + uint16_t _861 = (uint16_t)(1); + uint16_t _862 = _860 >> _861; + uint16_t _863 = _g_gb_stencil_12 + _862; + uint16_t _864 = _g_b_stencil_7 + _g_b_stencil_8; + uint16_t _865 = _864 >> _861; + uint16_t _866 = _863 - _865; + return _866; +} + +//store is: b_gr.stencil((b_gr_s0_x_x*2), (b_gr_s0_y_yio*2)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) + ((b_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)) + b_b.stencil((b_gr_s0_x_x*2), (b_gr_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)) + g_b.stencil((b_gr_s0_x_x*2), (b_gr_s0_y_yio*2)))/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_10 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_9 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_10 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_9 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_9 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _892 = _b_b_stencil_9 + _b_b_stencil_10; + uint16_t _893 = (uint16_t)(1); + uint16_t _894 = _892 >> _893; + uint16_t _895 = _g_gr_stencil_9 + _894; + uint16_t _896 = _g_b_stencil_9 + _g_b_stencil_10; + uint16_t _897 = _896 >> _893; + uint16_t _898 = _895 - _897; + return _898; +} + +//store is: b_gr.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 2)) + ((b_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 2)) + b_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 2)) + g_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil_1(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_11 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_12 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_11 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_12 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_10 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _922 = _b_b_stencil_11 + _b_b_stencil_12; + uint16_t _923 = (uint16_t)(1); + uint16_t _924 = _922 >> _923; + uint16_t _925 = _g_gr_stencil_10 + _924; + uint16_t _926 = _g_b_stencil_11 + _g_b_stencil_12; + uint16_t _927 = _926 >> _923; + uint16_t _928 = _925 - _927; + return _928; +} + +//store is: b_gr.stencil(((b_gr_s0_x_x*2) + 1), (b_gr_s0_y_yio*2)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 2), ((b_gr_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) + b_b.stencil(((b_gr_s0_x_x*2) + 1), (b_gr_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) + g_b.stencil(((b_gr_s0_x_x*2) + 1), (b_gr_s0_y_yio*2)))/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil_2(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_13 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_14 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_13 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_14 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_11 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _953 = _b_b_stencil_13 + _b_b_stencil_14; + uint16_t _954 = (uint16_t)(1); + uint16_t _955 = _953 >> _954; + uint16_t _956 = _g_gr_stencil_11 + _955; + uint16_t _957 = _g_b_stencil_13 + _g_b_stencil_14; + uint16_t _958 = _957 >> _954; + uint16_t _959 = _956 - _958; + return _959; +} + +//store is: b_gr.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 2), ((b_gr_s0_y_yio*2) + 2)) + ((b_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 2)) + b_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 2)) + g_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil_3(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_15 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_16 = (uint16_t) (b_b_stencil.extract<16, 31>()); + + uint16_t _g_b_stencil_15 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_16 = (uint16_t) (g_b_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_12 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _984 = _b_b_stencil_15 + _b_b_stencil_16; + uint16_t _985 = (uint16_t)(1); + uint16_t _986 = _984 >> _985; + uint16_t _987 = _g_gr_stencil_12 + _986; + uint16_t _988 = _g_b_stencil_15 + _g_b_stencil_16; + uint16_t _989 = _988 >> _985; + uint16_t _990 = _987 - _989; + return _990; +} + +//store is: g_r.stencil((g_r_s0_x_x*2), (g_r_s0_y_yio*2)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)), g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1))) < absd(g_gb.stencil((g_r_s0_x_x*2), (g_r_s0_y_yio*2)), g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)) + g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)))/(uint16)2), ((g_gb.stencil((g_r_s0_x_x*2), (g_r_s0_y_yio*2)) + g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_13 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_14 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_13 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_14 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _1016 = _g_gr_stencil_13 + _g_gr_stencil_14; + uint16_t _1017 = (uint16_t)(1); + uint16_t _1018 = _1016 >> _1017; + uint16_t _1019 = _g_gb_stencil_13 + _g_gb_stencil_14; + uint16_t _1020 = _1019 >> _1017; + uint16_t _1021 = _g_gr_stencil_14 - _g_gr_stencil_13; + uint16_t _1022 = _g_gr_stencil_13 - _g_gr_stencil_14; + bool _1023 = _g_gr_stencil_13 < _g_gr_stencil_14; + uint16_t _1024 = (uint16_t)(_1023 ? _1021 : _1022); + uint16_t _1025 = _1024; + uint16_t _1026 = _g_gb_stencil_14 - _g_gb_stencil_13; + uint16_t _1027 = _g_gb_stencil_13 - _g_gb_stencil_14; + bool _1028 = _g_gb_stencil_13 < _g_gb_stencil_14; + uint16_t _1029 = (uint16_t)(_1028 ? _1026 : _1027); + uint16_t _1030 = _1029; + bool _1031 = _1025 < _1030; + uint16_t _1032 = (uint16_t)(_1031 ? _1018 : _1020); + return _1032; +} + +//store is: g_r.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)), g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2))) < absd(g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)), g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)) + g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2)))/(uint16)2), ((g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)) + g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2)))/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil_1(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_15 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_16 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_15 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_16 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _1067 = _g_gr_stencil_15 + _g_gr_stencil_16; + uint16_t _1068 = (uint16_t)(1); + uint16_t _1069 = _1067 >> _1068; + uint16_t _1070 = _g_gb_stencil_15 + _g_gb_stencil_16; + uint16_t _1071 = _1070 >> _1068; + uint16_t _1072 = _g_gr_stencil_16 - _g_gr_stencil_15; + uint16_t _1073 = _g_gr_stencil_15 - _g_gr_stencil_16; + bool _1074 = _g_gr_stencil_15 < _g_gr_stencil_16; + uint16_t _1075 = (uint16_t)(_1074 ? _1072 : _1073); + uint16_t _1076 = _1075; + uint16_t _1077 = _g_gb_stencil_16 - _g_gb_stencil_15; + uint16_t _1078 = _g_gb_stencil_15 - _g_gb_stencil_16; + bool _1079 = _g_gb_stencil_15 < _g_gb_stencil_16; + uint16_t _1080 = (uint16_t)(_1079 ? _1077 : _1078); + uint16_t _1081 = _1080; + bool _1082 = _1076 < _1081; + uint16_t _1083 = (uint16_t)(_1082 ? _1069 : _1071); + return _1083; +} + +//store is: g_r.stencil(((g_r_s0_x_x*2) + 1), (g_r_s0_y_yio*2)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 1)), g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1))) < absd(g_gb.stencil(((g_r_s0_x_x*2) + 1), (g_r_s0_y_yio*2)), g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 1)) + g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)))/(uint16)2), ((g_gb.stencil(((g_r_s0_x_x*2) + 1), (g_r_s0_y_yio*2)) + g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil_2(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_17 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_18 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_17 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_18 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _1119 = _g_gr_stencil_17 + _g_gr_stencil_18; + uint16_t _1120 = (uint16_t)(1); + uint16_t _1121 = _1119 >> _1120; + uint16_t _1122 = _g_gb_stencil_17 + _g_gb_stencil_18; + uint16_t _1123 = _1122 >> _1120; + uint16_t _1124 = _g_gr_stencil_18 - _g_gr_stencil_17; + uint16_t _1125 = _g_gr_stencil_17 - _g_gr_stencil_18; + bool _1126 = _g_gr_stencil_17 < _g_gr_stencil_18; + uint16_t _1127 = (uint16_t)(_1126 ? _1124 : _1125); + uint16_t _1128 = _1127; + uint16_t _1129 = _g_gb_stencil_18 - _g_gb_stencil_17; + uint16_t _1130 = _g_gb_stencil_17 - _g_gb_stencil_18; + bool _1131 = _g_gb_stencil_17 < _g_gb_stencil_18; + uint16_t _1132 = (uint16_t)(_1131 ? _1129 : _1130); + uint16_t _1133 = _1132; + bool _1134 = _1128 < _1133; + uint16_t _1135 = (uint16_t)(_1134 ? _1121 : _1123); + return _1135; +} + +//store is: g_r.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 2)), g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2))) < absd(g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)), g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 2)) + g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)))/(uint16)2), ((g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)) + g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)))/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil_3(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_19 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + uint16_t _g_gb_stencil_20 = (uint16_t) (g_gb_stencil.extract<16, 31>()); + + uint16_t _g_gr_stencil_19 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + uint16_t _g_gr_stencil_20 = (uint16_t) (g_gr_stencil.extract<16, 31>()); + + uint16_t _1171 = _g_gr_stencil_19 + _g_gr_stencil_20; + uint16_t _1172 = (uint16_t)(1); + uint16_t _1173 = _1171 >> _1172; + uint16_t _1174 = _g_gb_stencil_19 + _g_gb_stencil_20; + uint16_t _1175 = _1174 >> _1172; + uint16_t _1176 = _g_gr_stencil_20 - _g_gr_stencil_19; + uint16_t _1177 = _g_gr_stencil_19 - _g_gr_stencil_20; + bool _1178 = _g_gr_stencil_19 < _g_gr_stencil_20; + uint16_t _1179 = (uint16_t)(_1178 ? _1176 : _1177); + uint16_t _1180 = _1179; + uint16_t _1181 = _g_gb_stencil_20 - _g_gb_stencil_19; + uint16_t _1182 = _g_gb_stencil_19 - _g_gb_stencil_20; + bool _1183 = _g_gb_stencil_19 < _g_gb_stencil_20; + uint16_t _1184 = (uint16_t)(_1183 ? _1181 : _1182); + uint16_t _1185 = _1184; + bool _1186 = _1180 < _1185; + uint16_t _1187 = (uint16_t)(_1186 ? _1173 : _1175); + return _1187; +} + +//store is: b_r.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)) = select((absd(b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)), b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)), b_b.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)))), ((g_r.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)) + ((b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)))/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_17 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_18 = (uint16_t) (b_b_stencil.extract<16, 31>()); + uint16_t _b_b_stencil_19 = (uint16_t) (b_b_stencil.extract<32, 47>()); + uint16_t _b_b_stencil_20 = (uint16_t) (b_b_stencil.extract<48, 63>()); + + uint16_t _g_b_stencil_17 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_18 = (uint16_t) (g_b_stencil.extract<16, 31>()); + uint16_t _g_b_stencil_19 = (uint16_t) (g_b_stencil.extract<32, 47>()); + uint16_t _g_b_stencil_20 = (uint16_t) (g_b_stencil.extract<48, 63>()); + + uint16_t _g_r_stencil_1 = (uint16_t) (g_r_stencil.extract<0, 15>()); + + uint16_t _1224 = _b_b_stencil_17 + _b_b_stencil_18; + uint16_t _1225 = (uint16_t)(1); + uint16_t _1226 = _1224 >> _1225; + uint16_t _1227 = _g_r_stencil_1 + _1226; + uint16_t _1228 = _g_b_stencil_17 + _g_b_stencil_18; + uint16_t _1229 = _1228 >> _1225; + uint16_t _1230 = _1227 - _1229; + uint16_t _1231 = _b_b_stencil_19 + _b_b_stencil_20; + uint16_t _1232 = _1231 >> _1225; + uint16_t _1233 = _g_r_stencil_1 + _1232; + uint16_t _1234 = _g_b_stencil_19 + _g_b_stencil_20; + uint16_t _1235 = _1234 >> _1225; + uint16_t _1236 = _1233 - _1235; + uint16_t _1237 = _b_b_stencil_18 - _b_b_stencil_17; + uint16_t _1238 = _b_b_stencil_17 - _b_b_stencil_18; + bool _1239 = _b_b_stencil_17 < _b_b_stencil_18; + uint16_t _1240 = (uint16_t)(_1239 ? _1237 : _1238); + uint16_t _1241 = _1240; + uint16_t _1242 = _b_b_stencil_20 - _b_b_stencil_19; + uint16_t _1243 = _b_b_stencil_19 - _b_b_stencil_20; + bool _1244 = _b_b_stencil_19 < _b_b_stencil_20; + uint16_t _1245 = (uint16_t)(_1244 ? _1242 : _1243); + uint16_t _1246 = _1245; + bool _1247 = _1241 < _1246; + uint16_t _1248 = (uint16_t)(_1247 ? _1230 : _1236); + return _1248; +} + +//store is: b_r.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)) = select((absd(b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 2)), b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)), b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)))), ((g_r.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil_1(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_21 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_22 = (uint16_t) (b_b_stencil.extract<16, 31>()); + uint16_t _b_b_stencil_23 = (uint16_t) (b_b_stencil.extract<32, 47>()); + uint16_t _b_b_stencil_24 = (uint16_t) (b_b_stencil.extract<48, 63>()); + + uint16_t _g_b_stencil_21 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_22 = (uint16_t) (g_b_stencil.extract<16, 31>()); + uint16_t _g_b_stencil_23 = (uint16_t) (g_b_stencil.extract<32, 47>()); + uint16_t _g_b_stencil_24 = (uint16_t) (g_b_stencil.extract<48, 63>()); + + uint16_t _g_r_stencil_2 = (uint16_t) (g_r_stencil.extract<0, 15>()); + + uint16_t _1304 = _b_b_stencil_21 + _b_b_stencil_22; + uint16_t _1305 = (uint16_t)(1); + uint16_t _1306 = _1304 >> _1305; + uint16_t _1307 = _g_r_stencil_2 + _1306; + uint16_t _1308 = _g_b_stencil_21 + _g_b_stencil_22; + uint16_t _1309 = _1308 >> _1305; + uint16_t _1310 = _1307 - _1309; + uint16_t _1311 = _b_b_stencil_23 + _b_b_stencil_24; + uint16_t _1312 = _1311 >> _1305; + uint16_t _1313 = _g_r_stencil_2 + _1312; + uint16_t _1314 = _g_b_stencil_23 + _g_b_stencil_24; + uint16_t _1315 = _1314 >> _1305; + uint16_t _1316 = _1313 - _1315; + uint16_t _1317 = _b_b_stencil_22 - _b_b_stencil_21; + uint16_t _1318 = _b_b_stencil_21 - _b_b_stencil_22; + bool _1319 = _b_b_stencil_21 < _b_b_stencil_22; + uint16_t _1320 = (uint16_t)(_1319 ? _1317 : _1318); + uint16_t _1321 = _1320; + uint16_t _1322 = _b_b_stencil_24 - _b_b_stencil_23; + uint16_t _1323 = _b_b_stencil_23 - _b_b_stencil_24; + bool _1324 = _b_b_stencil_23 < _b_b_stencil_24; + uint16_t _1325 = (uint16_t)(_1324 ? _1322 : _1323); + uint16_t _1326 = _1325; + bool _1327 = _1321 < _1326; + uint16_t _1328 = (uint16_t)(_1327 ? _1310 : _1316); + return _1328; +} + +//store is: b_r.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)) = select((absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)), b_b.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)), b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))), ((g_r.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)) + ((b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil_2(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_25 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_26 = (uint16_t) (b_b_stencil.extract<16, 31>()); + uint16_t _b_b_stencil_27 = (uint16_t) (b_b_stencil.extract<32, 47>()); + uint16_t _b_b_stencil_28 = (uint16_t) (b_b_stencil.extract<48, 63>()); + + uint16_t _g_b_stencil_25 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_26 = (uint16_t) (g_b_stencil.extract<16, 31>()); + uint16_t _g_b_stencil_27 = (uint16_t) (g_b_stencil.extract<32, 47>()); + uint16_t _g_b_stencil_28 = (uint16_t) (g_b_stencil.extract<48, 63>()); + + uint16_t _g_r_stencil_3 = (uint16_t) (g_r_stencil.extract<0, 15>()); + + uint16_t _1385 = _b_b_stencil_25 + _b_b_stencil_26; + uint16_t _1386 = (uint16_t)(1); + uint16_t _1387 = _1385 >> _1386; + uint16_t _1388 = _g_r_stencil_3 + _1387; + uint16_t _1389 = _g_b_stencil_25 + _g_b_stencil_26; + uint16_t _1390 = _1389 >> _1386; + uint16_t _1391 = _1388 - _1390; + uint16_t _1392 = _b_b_stencil_27 + _b_b_stencil_28; + uint16_t _1393 = _1392 >> _1386; + uint16_t _1394 = _g_r_stencil_3 + _1393; + uint16_t _1395 = _g_b_stencil_27 + _g_b_stencil_28; + uint16_t _1396 = _1395 >> _1386; + uint16_t _1397 = _1394 - _1396; + uint16_t _1398 = _b_b_stencil_26 - _b_b_stencil_25; + uint16_t _1399 = _b_b_stencil_25 - _b_b_stencil_26; + bool _1400 = _b_b_stencil_25 < _b_b_stencil_26; + uint16_t _1401 = (uint16_t)(_1400 ? _1398 : _1399); + uint16_t _1402 = _1401; + uint16_t _1403 = _b_b_stencil_28 - _b_b_stencil_27; + uint16_t _1404 = _b_b_stencil_27 - _b_b_stencil_28; + bool _1405 = _b_b_stencil_27 < _b_b_stencil_28; + uint16_t _1406 = (uint16_t)(_1405 ? _1403 : _1404); + uint16_t _1407 = _1406; + bool _1408 = _1402 < _1407; + uint16_t _1409 = (uint16_t)(_1408 ? _1391 : _1397); + return _1409; +} + +//store is: b_r.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) = select((absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)), b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 2)), b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))), ((g_r.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil_3(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_29 = (uint16_t) (b_b_stencil.extract<0, 15>()); + uint16_t _b_b_stencil_30 = (uint16_t) (b_b_stencil.extract<16, 31>()); + uint16_t _b_b_stencil_31 = (uint16_t) (b_b_stencil.extract<32, 47>()); + uint16_t _b_b_stencil_32 = (uint16_t) (b_b_stencil.extract<48, 63>()); + + uint16_t _g_b_stencil_29 = (uint16_t) (g_b_stencil.extract<0, 15>()); + uint16_t _g_b_stencil_30 = (uint16_t) (g_b_stencil.extract<16, 31>()); + uint16_t _g_b_stencil_31 = (uint16_t) (g_b_stencil.extract<32, 47>()); + uint16_t _g_b_stencil_32 = (uint16_t) (g_b_stencil.extract<48, 63>()); + + uint16_t _g_r_stencil_4 = (uint16_t) (g_r_stencil.extract<0, 15>()); + + uint16_t _1466 = _b_b_stencil_29 + _b_b_stencil_30; + uint16_t _1467 = (uint16_t)(1); + uint16_t _1468 = _1466 >> _1467; + uint16_t _1469 = _g_r_stencil_4 + _1468; + uint16_t _1470 = _g_b_stencil_29 + _g_b_stencil_30; + uint16_t _1471 = _1470 >> _1467; + uint16_t _1472 = _1469 - _1471; + uint16_t _1473 = _b_b_stencil_31 + _b_b_stencil_32; + uint16_t _1474 = _1473 >> _1467; + uint16_t _1475 = _g_r_stencil_4 + _1474; + uint16_t _1476 = _g_b_stencil_31 + _g_b_stencil_32; + uint16_t _1477 = _1476 >> _1467; + uint16_t _1478 = _1475 - _1477; + uint16_t _1479 = _b_b_stencil_30 - _b_b_stencil_29; + uint16_t _1480 = _b_b_stencil_29 - _b_b_stencil_30; + bool _1481 = _b_b_stencil_29 < _b_b_stencil_30; + uint16_t _1482 = (uint16_t)(_1481 ? _1479 : _1480); + uint16_t _1483 = _1482; + uint16_t _1484 = _b_b_stencil_32 - _b_b_stencil_31; + uint16_t _1485 = _b_b_stencil_31 - _b_b_stencil_32; + bool _1486 = _b_b_stencil_31 < _b_b_stencil_32; + uint16_t _1487 = (uint16_t)(_1486 ? _1484 : _1485); + uint16_t _1488 = _1487; + bool _1489 = _1483 < _1488; + uint16_t _1490 = (uint16_t)(_1489 ? _1472 : _1478); + return _1490; +} + +//store is: r_r.stencil((r_r_s0_x_x*2), (r_r_s0_y_yio*2)) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y_yio*4) + 2)) +hw_uint<16> hcompute_r_r_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_13 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_13; +} + +//store is: r_r.stencil((r_r_s0_x_x*2), ((r_r_s0_y_yio*2) + 1)) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y_yio*4) + 4)) +hw_uint<16> hcompute_r_r_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_14 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_14; +} + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), (r_r_s0_y_yio*2)) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y_yio*4) + 2)) +hw_uint<16> hcompute_r_r_stencil_2(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_15 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_15; +} + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), ((r_r_s0_y_yio*2) + 1)) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y_yio*4) + 4)) +hw_uint<16> hcompute_r_r_stencil_3(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_16 = (uint16_t) (denoised_1_stencil.extract<0, 15>()); + + return _denoised_1_stencil_16; +} + +//store is: r_b.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)), r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1))) < absd(r_r.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + g_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_33 = (uint16_t) (g_b_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_5 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_6 = (uint16_t) (g_r_stencil.extract<16, 31>()); + uint16_t _g_r_stencil_7 = (uint16_t) (g_r_stencil.extract<32, 47>()); + uint16_t _g_r_stencil_8 = (uint16_t) (g_r_stencil.extract<48, 63>()); + + uint16_t _r_r_stencil_1 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_2 = (uint16_t) (r_r_stencil.extract<16, 31>()); + uint16_t _r_r_stencil_3 = (uint16_t) (r_r_stencil.extract<32, 47>()); + uint16_t _r_r_stencil_4 = (uint16_t) (r_r_stencil.extract<48, 63>()); + + uint16_t _1580 = _r_r_stencil_1 + _r_r_stencil_2; + uint16_t _1581 = (uint16_t)(1); + uint16_t _1582 = _1580 >> _1581; + uint16_t _1583 = _g_b_stencil_33 + _1582; + uint16_t _1584 = _g_r_stencil_5 + _g_r_stencil_6; + uint16_t _1585 = _1584 >> _1581; + uint16_t _1586 = _1583 - _1585; + uint16_t _1587 = _r_r_stencil_3 + _r_r_stencil_4; + uint16_t _1588 = _1587 >> _1581; + uint16_t _1589 = _g_b_stencil_33 + _1588; + uint16_t _1590 = _g_r_stencil_7 + _g_r_stencil_8; + uint16_t _1591 = _1590 >> _1581; + uint16_t _1592 = _1589 - _1591; + uint16_t _1593 = _r_r_stencil_2 - _r_r_stencil_1; + uint16_t _1594 = _r_r_stencil_1 - _r_r_stencil_2; + bool _1595 = _r_r_stencil_1 < _r_r_stencil_2; + uint16_t _1596 = (uint16_t)(_1595 ? _1593 : _1594); + uint16_t _1597 = _1596; + uint16_t _1598 = _r_r_stencil_4 - _r_r_stencil_3; + uint16_t _1599 = _r_r_stencil_3 - _r_r_stencil_4; + bool _1600 = _r_r_stencil_3 < _r_r_stencil_4; + uint16_t _1601 = (uint16_t)(_1600 ? _1598 : _1599); + uint16_t _1602 = _1601; + bool _1603 = _1597 < _1602; + uint16_t _1604 = (uint16_t)(_1603 ? _1586 : _1592); + return _1604; +} + +//store is: r_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)), r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2))) < absd(r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil_1(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_34 = (uint16_t) (g_b_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_10 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_11 = (uint16_t) (g_r_stencil.extract<16, 31>()); + uint16_t _g_r_stencil_12 = (uint16_t) (g_r_stencil.extract<32, 47>()); + uint16_t _g_r_stencil_9 = (uint16_t) (g_r_stencil.extract<48, 63>()); + + uint16_t _r_r_stencil_5 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_6 = (uint16_t) (r_r_stencil.extract<16, 31>()); + uint16_t _r_r_stencil_7 = (uint16_t) (r_r_stencil.extract<32, 47>()); + uint16_t _r_r_stencil_8 = (uint16_t) (r_r_stencil.extract<48, 63>()); + + uint16_t _1660 = _r_r_stencil_5 + _r_r_stencil_6; + uint16_t _1661 = (uint16_t)(1); + uint16_t _1662 = _1660 >> _1661; + uint16_t _1663 = _g_b_stencil_34 + _1662; + uint16_t _1664 = _g_r_stencil_9 + _g_r_stencil_10; + uint16_t _1665 = _1664 >> _1661; + uint16_t _1666 = _1663 - _1665; + uint16_t _1667 = _r_r_stencil_7 + _r_r_stencil_8; + uint16_t _1668 = _1667 >> _1661; + uint16_t _1669 = _g_b_stencil_34 + _1668; + uint16_t _1670 = _g_r_stencil_11 + _g_r_stencil_12; + uint16_t _1671 = _1670 >> _1661; + uint16_t _1672 = _1669 - _1671; + uint16_t _1673 = _r_r_stencil_6 - _r_r_stencil_5; + uint16_t _1674 = _r_r_stencil_5 - _r_r_stencil_6; + bool _1675 = _r_r_stencil_5 < _r_r_stencil_6; + uint16_t _1676 = (uint16_t)(_1675 ? _1673 : _1674); + uint16_t _1677 = _1676; + uint16_t _1678 = _r_r_stencil_8 - _r_r_stencil_7; + uint16_t _1679 = _r_r_stencil_7 - _r_r_stencil_8; + bool _1680 = _r_r_stencil_7 < _r_r_stencil_8; + uint16_t _1681 = (uint16_t)(_1680 ? _1678 : _1679); + uint16_t _1682 = _1681; + bool _1683 = _1677 < _1682; + uint16_t _1684 = (uint16_t)(_1683 ? _1666 : _1672); + return _1684; +} + +//store is: r_b.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 2), (r_b_s0_y_yio*2)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1))) < absd(r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)), r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)))), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_b_s0_x_x*2) + 2), (r_b_s0_y_yio*2)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 2), (r_b_s0_y_yio*2)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + g_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil_2(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_35 = (uint16_t) (g_b_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_13 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_14 = (uint16_t) (g_r_stencil.extract<16, 31>()); + uint16_t _g_r_stencil_15 = (uint16_t) (g_r_stencil.extract<32, 47>()); + uint16_t _g_r_stencil_16 = (uint16_t) (g_r_stencil.extract<48, 63>()); + + uint16_t _r_r_stencil_10 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_11 = (uint16_t) (r_r_stencil.extract<16, 31>()); + uint16_t _r_r_stencil_12 = (uint16_t) (r_r_stencil.extract<32, 47>()); + uint16_t _r_r_stencil_9 = (uint16_t) (r_r_stencil.extract<48, 63>()); + + uint16_t _1741 = _r_r_stencil_9 + _r_r_stencil_10; + uint16_t _1742 = (uint16_t)(1); + uint16_t _1743 = _1741 >> _1742; + uint16_t _1744 = _g_b_stencil_35 + _1743; + uint16_t _1745 = _g_r_stencil_13 + _g_r_stencil_14; + uint16_t _1746 = _1745 >> _1742; + uint16_t _1747 = _1744 - _1746; + uint16_t _1748 = _r_r_stencil_11 + _r_r_stencil_12; + uint16_t _1749 = _1748 >> _1742; + uint16_t _1750 = _g_b_stencil_35 + _1749; + uint16_t _1751 = _g_r_stencil_15 + _g_r_stencil_16; + uint16_t _1752 = _1751 >> _1742; + uint16_t _1753 = _1750 - _1752; + uint16_t _1754 = _r_r_stencil_10 - _r_r_stencil_9; + uint16_t _1755 = _r_r_stencil_9 - _r_r_stencil_10; + bool _1756 = _r_r_stencil_9 < _r_r_stencil_10; + uint16_t _1757 = (uint16_t)(_1756 ? _1754 : _1755); + uint16_t _1758 = _1757; + uint16_t _1759 = _r_r_stencil_12 - _r_r_stencil_11; + uint16_t _1760 = _r_r_stencil_11 - _r_r_stencil_12; + bool _1761 = _r_r_stencil_11 < _r_r_stencil_12; + uint16_t _1762 = (uint16_t)(_1761 ? _1759 : _1760); + uint16_t _1763 = _1762; + bool _1764 = _1758 < _1763; + uint16_t _1765 = (uint16_t)(_1764 ? _1747 : _1753); + return _1765; +} + +//store is: r_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2))) < absd(r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)), r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 2)))), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil_3(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_36 = (uint16_t) (g_b_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_17 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_18 = (uint16_t) (g_r_stencil.extract<16, 31>()); + uint16_t _g_r_stencil_19 = (uint16_t) (g_r_stencil.extract<32, 47>()); + uint16_t _g_r_stencil_20 = (uint16_t) (g_r_stencil.extract<48, 63>()); + + uint16_t _r_r_stencil_13 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_14 = (uint16_t) (r_r_stencil.extract<16, 31>()); + uint16_t _r_r_stencil_15 = (uint16_t) (r_r_stencil.extract<32, 47>()); + uint16_t _r_r_stencil_16 = (uint16_t) (r_r_stencil.extract<48, 63>()); + + uint16_t _1822 = _r_r_stencil_13 + _r_r_stencil_14; + uint16_t _1823 = (uint16_t)(1); + uint16_t _1824 = _1822 >> _1823; + uint16_t _1825 = _g_b_stencil_36 + _1824; + uint16_t _1826 = _g_r_stencil_17 + _g_r_stencil_18; + uint16_t _1827 = _1826 >> _1823; + uint16_t _1828 = _1825 - _1827; + uint16_t _1829 = _r_r_stencil_15 + _r_r_stencil_16; + uint16_t _1830 = _1829 >> _1823; + uint16_t _1831 = _g_b_stencil_36 + _1830; + uint16_t _1832 = _g_r_stencil_19 + _g_r_stencil_20; + uint16_t _1833 = _1832 >> _1823; + uint16_t _1834 = _1831 - _1833; + uint16_t _1835 = _r_r_stencil_14 - _r_r_stencil_13; + uint16_t _1836 = _r_r_stencil_13 - _r_r_stencil_14; + bool _1837 = _r_r_stencil_13 < _r_r_stencil_14; + uint16_t _1838 = (uint16_t)(_1837 ? _1835 : _1836); + uint16_t _1839 = _1838; + uint16_t _1840 = _r_r_stencil_16 - _r_r_stencil_15; + uint16_t _1841 = _r_r_stencil_15 - _r_r_stencil_16; + bool _1842 = _r_r_stencil_15 < _r_r_stencil_16; + uint16_t _1843 = (uint16_t)(_1842 ? _1840 : _1841); + uint16_t _1844 = _1843; + bool _1845 = _1839 < _1844; + uint16_t _1846 = (uint16_t)(_1845 ? _1828 : _1834); + return _1846; +} + +//store is: r_gb.stencil((r_gb_s0_x_x*2), (r_gb_s0_y_yio*2)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 1), (r_gb_s0_y_yio*2)) + r_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 1), (r_gb_s0_y_yio*2)) + g_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_21 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_21 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_22 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_17 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_18 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _1904 = _r_r_stencil_17 + _r_r_stencil_18; + uint16_t _1905 = (uint16_t)(1); + uint16_t _1906 = _1904 >> _1905; + uint16_t _1907 = _g_gb_stencil_21 + _1906; + uint16_t _1908 = _g_r_stencil_21 + _g_r_stencil_22; + uint16_t _1909 = _1908 >> _1905; + uint16_t _1910 = _1907 - _1909; + return _1910; +} + +//store is: r_gb.stencil((r_gb_s0_x_x*2), ((r_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) + r_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) + g_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil_1(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_22 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_23 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_24 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_19 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_20 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _1934 = _r_r_stencil_19 + _r_r_stencil_20; + uint16_t _1935 = (uint16_t)(1); + uint16_t _1936 = _1934 >> _1935; + uint16_t _1937 = _g_gb_stencil_22 + _1936; + uint16_t _1938 = _g_r_stencil_23 + _g_r_stencil_24; + uint16_t _1939 = _1938 >> _1935; + uint16_t _1940 = _1937 - _1939; + return _1940; +} + +//store is: r_gb.stencil(((r_gb_s0_x_x*2) + 1), (r_gb_s0_y_yio*2)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 2), (r_gb_s0_y_yio*2)) + r_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 2), (r_gb_s0_y_yio*2)) + g_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil_2(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_23 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_25 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_26 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_21 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_22 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _1965 = _r_r_stencil_21 + _r_r_stencil_22; + uint16_t _1966 = (uint16_t)(1); + uint16_t _1967 = _1965 >> _1966; + uint16_t _1968 = _g_gb_stencil_23 + _1967; + uint16_t _1969 = _g_r_stencil_25 + _g_r_stencil_26; + uint16_t _1970 = _1969 >> _1966; + uint16_t _1971 = _1968 - _1970; + return _1971; +} + +//store is: r_gb.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)) + r_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)) + g_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil_3(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_24 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_27 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_28 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_23 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_24 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _1996 = _r_r_stencil_23 + _r_r_stencil_24; + uint16_t _1997 = (uint16_t)(1); + uint16_t _1998 = _1996 >> _1997; + uint16_t _1999 = _g_gb_stencil_24 + _1998; + uint16_t _2000 = _g_r_stencil_27 + _g_r_stencil_28; + uint16_t _2001 = _2000 >> _1997; + uint16_t _2002 = _1999 - _2001; + return _2002; +} + +//store is: r_gr.stencil((r_gr_s0_x_x*2), (r_gr_s0_y_yio*2)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) + ((r_r.stencil((r_gr_s0_x_x*2), (r_gr_s0_y_yio*2)) + r_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)) + g_r.stencil((r_gr_s0_x_x*2), (r_gr_s0_y_yio*2)))/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_21 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_29 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_30 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_25 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_26 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _2028 = _r_r_stencil_25 + _r_r_stencil_26; + uint16_t _2029 = (uint16_t)(1); + uint16_t _2030 = _2028 >> _2029; + uint16_t _2031 = _g_gr_stencil_21 + _2030; + uint16_t _2032 = _g_r_stencil_29 + _g_r_stencil_30; + uint16_t _2033 = _2032 >> _2029; + uint16_t _2034 = _2031 - _2033; + return _2034; +} + +//store is: r_gr.stencil((r_gr_s0_x_x*2), ((r_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 2)) + ((r_r.stencil((r_gr_s0_x_x*2), ((r_gr_s0_y_yio*2) + 1)) + r_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) + g_r.stencil((r_gr_s0_x_x*2), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil_1(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_22 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_31 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_32 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_27 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_28 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _2058 = _r_r_stencil_27 + _r_r_stencil_28; + uint16_t _2059 = (uint16_t)(1); + uint16_t _2060 = _2058 >> _2059; + uint16_t _2061 = _g_gr_stencil_22 + _2060; + uint16_t _2062 = _g_r_stencil_31 + _g_r_stencil_32; + uint16_t _2063 = _2062 >> _2059; + uint16_t _2064 = _2061 - _2063; + return _2064; +} + +//store is: r_gr.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)) + r_r.stencil(((r_gr_s0_x_x*2) + 2), (r_gr_s0_y_yio*2)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 2), (r_gr_s0_y_yio*2)) + g_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)))/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil_2(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_23 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_33 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_34 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_29 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_30 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _2089 = _r_r_stencil_29 + _r_r_stencil_30; + uint16_t _2090 = (uint16_t)(1); + uint16_t _2091 = _2089 >> _2090; + uint16_t _2092 = _g_gr_stencil_23 + _2091; + uint16_t _2093 = _g_r_stencil_33 + _g_r_stencil_34; + uint16_t _2094 = _2093 >> _2090; + uint16_t _2095 = _2092 - _2094; + return _2095; +} + +//store is: r_gr.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) + r_r.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 1)) + g_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil_3(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_24 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + uint16_t _g_r_stencil_35 = (uint16_t) (g_r_stencil.extract<0, 15>()); + uint16_t _g_r_stencil_36 = (uint16_t) (g_r_stencil.extract<16, 31>()); + + uint16_t _r_r_stencil_31 = (uint16_t) (r_r_stencil.extract<0, 15>()); + uint16_t _r_r_stencil_32 = (uint16_t) (r_r_stencil.extract<16, 31>()); + + uint16_t _2120 = _r_r_stencil_31 + _r_r_stencil_32; + uint16_t _2121 = (uint16_t)(1); + uint16_t _2122 = _2120 >> _2121; + uint16_t _2123 = _g_gr_stencil_24 + _2122; + uint16_t _2124 = _g_r_stencil_35 + _g_r_stencil_36; + uint16_t _2125 = _2124 >> _2121; + uint16_t _2126 = _2123 - _2125; + return _2126; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 0) = r_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil(hw_uint<16>& r_gr_stencil) { + uint16_t _r_gr_stencil_1 = (uint16_t) (r_gr_stencil.extract<0, 15>()); + + return _r_gr_stencil_1; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 1) = g_gr.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_1(hw_uint<16>& g_gr_stencil) { + uint16_t _g_gr_stencil_25 = (uint16_t) (g_gr_stencil.extract<0, 15>()); + + return _g_gr_stencil_25; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 2) = b_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_2(hw_uint<16>& b_gr_stencil) { + uint16_t _b_gr_stencil_1 = (uint16_t) (b_gr_stencil.extract<0, 15>()); + + return _b_gr_stencil_1; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_b.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_3(hw_uint<16>& r_b_stencil) { + uint16_t _r_b_stencil_1 = (uint16_t) (r_b_stencil.extract<0, 15>()); + + return _r_b_stencil_1; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_4(hw_uint<16>& g_b_stencil) { + uint16_t _g_b_stencil_37 = (uint16_t) (g_b_stencil.extract<0, 15>()); + + return _g_b_stencil_37; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_5(hw_uint<16>& b_b_stencil) { + uint16_t _b_b_stencil_33 = (uint16_t) (b_b_stencil.extract<0, 15>()); + + return _b_b_stencil_33; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 0) = r_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_6(hw_uint<16>& r_r_stencil) { + uint16_t _r_r_stencil_33 = (uint16_t) (r_r_stencil.extract<0, 15>()); + + return _r_r_stencil_33; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 1) = g_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_7(hw_uint<16>& g_r_stencil) { + uint16_t _g_r_stencil_37 = (uint16_t) (g_r_stencil.extract<0, 15>()); + + return _g_r_stencil_37; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 2) = b_r.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_8(hw_uint<16>& b_r_stencil) { + uint16_t _b_r_stencil_1 = (uint16_t) (b_r_stencil.extract<0, 15>()); + + return _b_r_stencil_1; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_9(hw_uint<16>& r_gb_stencil) { + uint16_t _r_gb_stencil_1 = (uint16_t) (r_gb_stencil.extract<0, 15>()); + + return _r_gb_stencil_1; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_gb.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) +hw_uint<16> hcompute_demosaicked_1_stencil_10(hw_uint<16>& g_gb_stencil) { + uint16_t _g_gb_stencil_25 = (uint16_t) (g_gb_stencil.extract<0, 15>()); + + return _g_gb_stencil_25; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) +hw_uint<16> hcompute_demosaicked_1_stencil_11(hw_uint<16>& b_gb_stencil) { + uint16_t _b_gb_stencil_1 = (uint16_t) (b_gb_stencil.extract<0, 15>()); + + return _b_gb_stencil_1; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_1 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_2 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_3 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2208 = (uint16_t)(10000); + uint16_t _2209 = min(_demosaicked_1_stencil_1, _2208); + int32_t _2210 = (int32_t)(_2209); + int32_t _2211 = _2210 * 549; + int32_t _2212 = _2211 >> 8; + int16_t _2213 = (int16_t)(_2212); + uint16_t _2214 = min(_demosaicked_1_stencil_2, _2208); + int32_t _2215 = (int32_t)(_2214); + int32_t _2216 = _2215 * -103; + int32_t _2217 = _2216 >> 8; + int16_t _2218 = (int16_t)(_2217); + int16_t _2219 = _2213 + _2218; + uint16_t _2220 = min(_demosaicked_1_stencil_3, _2208); + int32_t _2221 = (int32_t)(_2220); + int32_t _2222 = _2221 * 7; + int32_t _2223 = _2222 >> 8; + int16_t _2224 = (int16_t)(_2223); + int16_t _2225 = _2219 + _2224; + int16_t _2226 = (int16_t)(-40); + int16_t _2227 = _2225 + _2226; + return _2227; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_1(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_4 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_5 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_6 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2267 = (uint16_t)(10000); + uint16_t _2268 = min(_demosaicked_1_stencil_4, _2267); + int32_t _2269 = (int32_t)(_2268); + int32_t _2270 = _2269 * -96; + int32_t _2271 = _2270 >> 8; + int16_t _2272 = (int16_t)(_2271); + uint16_t _2273 = min(_demosaicked_1_stencil_5, _2267); + int32_t _2274 = (int32_t)(_2273); + int32_t _2275 = _2274 * 373; + int32_t _2276 = _2275 >> 8; + int16_t _2277 = (int16_t)(_2276); + int16_t _2278 = _2272 + _2277; + uint16_t _2279 = min(_demosaicked_1_stencil_6, _2267); + int32_t _2280 = (int32_t)(_2279); + int32_t _2281 = _2280 * 62; + int32_t _2282 = _2281 >> 8; + int16_t _2283 = (int16_t)(_2282); + int16_t _2284 = _2278 + _2283; + int16_t _2285 = (int16_t)(-29); + int16_t _2286 = _2284 + _2285; + return _2286; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_2(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_7 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_8 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_9 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2326 = (uint16_t)(10000); + uint16_t _2327 = min(_demosaicked_1_stencil_7, _2326); + int32_t _2328 = (int32_t)(_2327); + int32_t _2329 = _2328 * -31; + int32_t _2330 = _2329 >> 8; + int16_t _2331 = (int16_t)(_2330); + uint16_t _2332 = min(_demosaicked_1_stencil_8, _2326); + int32_t _2333 = (int32_t)(_2332); + int32_t _2334 = _2333 * -261; + int32_t _2335 = _2334 >> 8; + int16_t _2336 = (int16_t)(_2335); + int16_t _2337 = _2331 + _2336; + uint16_t _2338 = min(_demosaicked_1_stencil_9, _2326); + int32_t _2339 = (int32_t)(_2338); + int32_t _2340 = _2339 * 883; + int32_t _2341 = _2340 >> 8; + int16_t _2342 = (int16_t)(_2341); + int16_t _2343 = _2337 + _2342; + int16_t _2344 = (int16_t)(-22); + int16_t _2345 = _2343 + _2344; + return _2345; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_3(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_10 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_11 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_12 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2385 = (uint16_t)(10000); + uint16_t _2386 = min(_demosaicked_1_stencil_10, _2385); + int32_t _2387 = (int32_t)(_2386); + int32_t _2388 = _2387 * 549; + int32_t _2389 = _2388 >> 8; + int16_t _2390 = (int16_t)(_2389); + uint16_t _2391 = min(_demosaicked_1_stencil_11, _2385); + int32_t _2392 = (int32_t)(_2391); + int32_t _2393 = _2392 * -103; + int32_t _2394 = _2393 >> 8; + int16_t _2395 = (int16_t)(_2394); + int16_t _2396 = _2390 + _2395; + uint16_t _2397 = min(_demosaicked_1_stencil_12, _2385); + int32_t _2398 = (int32_t)(_2397); + int32_t _2399 = _2398 * 7; + int32_t _2400 = _2399 >> 8; + int16_t _2401 = (int16_t)(_2400); + int16_t _2402 = _2396 + _2401; + int16_t _2403 = (int16_t)(-40); + int16_t _2404 = _2402 + _2403; + return _2404; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_4(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_13 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_14 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_15 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2445 = (uint16_t)(10000); + uint16_t _2446 = min(_demosaicked_1_stencil_13, _2445); + int32_t _2447 = (int32_t)(_2446); + int32_t _2448 = _2447 * -96; + int32_t _2449 = _2448 >> 8; + int16_t _2450 = (int16_t)(_2449); + uint16_t _2451 = min(_demosaicked_1_stencil_14, _2445); + int32_t _2452 = (int32_t)(_2451); + int32_t _2453 = _2452 * 373; + int32_t _2454 = _2453 >> 8; + int16_t _2455 = (int16_t)(_2454); + int16_t _2456 = _2450 + _2455; + uint16_t _2457 = min(_demosaicked_1_stencil_15, _2445); + int32_t _2458 = (int32_t)(_2457); + int32_t _2459 = _2458 * 62; + int32_t _2460 = _2459 >> 8; + int16_t _2461 = (int16_t)(_2460); + int16_t _2462 = _2456 + _2461; + int16_t _2463 = (int16_t)(-29); + int16_t _2464 = _2462 + _2463; + return _2464; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_5(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_16 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_17 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_18 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2505 = (uint16_t)(10000); + uint16_t _2506 = min(_demosaicked_1_stencil_16, _2505); + int32_t _2507 = (int32_t)(_2506); + int32_t _2508 = _2507 * -31; + int32_t _2509 = _2508 >> 8; + int16_t _2510 = (int16_t)(_2509); + uint16_t _2511 = min(_demosaicked_1_stencil_17, _2505); + int32_t _2512 = (int32_t)(_2511); + int32_t _2513 = _2512 * -261; + int32_t _2514 = _2513 >> 8; + int16_t _2515 = (int16_t)(_2514); + int16_t _2516 = _2510 + _2515; + uint16_t _2517 = min(_demosaicked_1_stencil_18, _2505); + int32_t _2518 = (int32_t)(_2517); + int32_t _2519 = _2518 * 883; + int32_t _2520 = _2519 >> 8; + int16_t _2521 = (int16_t)(_2520); + int16_t _2522 = _2516 + _2521; + int16_t _2523 = (int16_t)(-22); + int16_t _2524 = _2522 + _2523; + return _2524; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_6(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_19 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_20 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_21 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2565 = (uint16_t)(10000); + uint16_t _2566 = min(_demosaicked_1_stencil_19, _2565); + int32_t _2567 = (int32_t)(_2566); + int32_t _2568 = _2567 * 549; + int32_t _2569 = _2568 >> 8; + int16_t _2570 = (int16_t)(_2569); + uint16_t _2571 = min(_demosaicked_1_stencil_20, _2565); + int32_t _2572 = (int32_t)(_2571); + int32_t _2573 = _2572 * -103; + int32_t _2574 = _2573 >> 8; + int16_t _2575 = (int16_t)(_2574); + int16_t _2576 = _2570 + _2575; + uint16_t _2577 = min(_demosaicked_1_stencil_21, _2565); + int32_t _2578 = (int32_t)(_2577); + int32_t _2579 = _2578 * 7; + int32_t _2580 = _2579 >> 8; + int16_t _2581 = (int16_t)(_2580); + int16_t _2582 = _2576 + _2581; + int16_t _2583 = (int16_t)(-40); + int16_t _2584 = _2582 + _2583; + return _2584; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_7(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_22 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_23 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_24 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2625 = (uint16_t)(10000); + uint16_t _2626 = min(_demosaicked_1_stencil_22, _2625); + int32_t _2627 = (int32_t)(_2626); + int32_t _2628 = _2627 * -96; + int32_t _2629 = _2628 >> 8; + int16_t _2630 = (int16_t)(_2629); + uint16_t _2631 = min(_demosaicked_1_stencil_23, _2625); + int32_t _2632 = (int32_t)(_2631); + int32_t _2633 = _2632 * 373; + int32_t _2634 = _2633 >> 8; + int16_t _2635 = (int16_t)(_2634); + int16_t _2636 = _2630 + _2635; + uint16_t _2637 = min(_demosaicked_1_stencil_24, _2625); + int32_t _2638 = (int32_t)(_2637); + int32_t _2639 = _2638 * 62; + int32_t _2640 = _2639 >> 8; + int16_t _2641 = (int16_t)(_2640); + int16_t _2642 = _2636 + _2641; + int16_t _2643 = (int16_t)(-29); + int16_t _2644 = _2642 + _2643; + return _2644; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_8(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_25 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_26 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_27 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2685 = (uint16_t)(10000); + uint16_t _2686 = min(_demosaicked_1_stencil_25, _2685); + int32_t _2687 = (int32_t)(_2686); + int32_t _2688 = _2687 * -31; + int32_t _2689 = _2688 >> 8; + int16_t _2690 = (int16_t)(_2689); + uint16_t _2691 = min(_demosaicked_1_stencil_26, _2685); + int32_t _2692 = (int32_t)(_2691); + int32_t _2693 = _2692 * -261; + int32_t _2694 = _2693 >> 8; + int16_t _2695 = (int16_t)(_2694); + int16_t _2696 = _2690 + _2695; + uint16_t _2697 = min(_demosaicked_1_stencil_27, _2685); + int32_t _2698 = (int32_t)(_2697); + int32_t _2699 = _2698 * 883; + int32_t _2700 = _2699 >> 8; + int16_t _2701 = (int16_t)(_2700); + int16_t _2702 = _2696 + _2701; + int16_t _2703 = (int16_t)(-22); + int16_t _2704 = _2702 + _2703; + return _2704; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_9(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_28 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_29 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_30 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2745 = (uint16_t)(10000); + uint16_t _2746 = min(_demosaicked_1_stencil_28, _2745); + int32_t _2747 = (int32_t)(_2746); + int32_t _2748 = _2747 * 549; + int32_t _2749 = _2748 >> 8; + int16_t _2750 = (int16_t)(_2749); + uint16_t _2751 = min(_demosaicked_1_stencil_29, _2745); + int32_t _2752 = (int32_t)(_2751); + int32_t _2753 = _2752 * -103; + int32_t _2754 = _2753 >> 8; + int16_t _2755 = (int16_t)(_2754); + int16_t _2756 = _2750 + _2755; + uint16_t _2757 = min(_demosaicked_1_stencil_30, _2745); + int32_t _2758 = (int32_t)(_2757); + int32_t _2759 = _2758 * 7; + int32_t _2760 = _2759 >> 8; + int16_t _2761 = (int16_t)(_2760); + int16_t _2762 = _2756 + _2761; + int16_t _2763 = (int16_t)(-40); + int16_t _2764 = _2762 + _2763; + return _2764; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_10(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_31 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_32 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_33 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2806 = (uint16_t)(10000); + uint16_t _2807 = min(_demosaicked_1_stencil_31, _2806); + int32_t _2808 = (int32_t)(_2807); + int32_t _2809 = _2808 * -96; + int32_t _2810 = _2809 >> 8; + int16_t _2811 = (int16_t)(_2810); + uint16_t _2812 = min(_demosaicked_1_stencil_32, _2806); + int32_t _2813 = (int32_t)(_2812); + int32_t _2814 = _2813 * 373; + int32_t _2815 = _2814 >> 8; + int16_t _2816 = (int16_t)(_2815); + int16_t _2817 = _2811 + _2816; + uint16_t _2818 = min(_demosaicked_1_stencil_33, _2806); + int32_t _2819 = (int32_t)(_2818); + int32_t _2820 = _2819 * 62; + int32_t _2821 = _2820 >> 8; + int16_t _2822 = (int16_t)(_2821); + int16_t _2823 = _2817 + _2822; + int16_t _2824 = (int16_t)(-29); + int16_t _2825 = _2823 + _2824; + return _2825; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_11(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_34 = (uint16_t) (demosaicked_1_stencil.extract<0, 15>()); + uint16_t _demosaicked_1_stencil_35 = (uint16_t) (demosaicked_1_stencil.extract<16, 31>()); + uint16_t _demosaicked_1_stencil_36 = (uint16_t) (demosaicked_1_stencil.extract<32, 47>()); + + uint16_t _2867 = (uint16_t)(10000); + uint16_t _2868 = min(_demosaicked_1_stencil_34, _2867); + int32_t _2869 = (int32_t)(_2868); + int32_t _2870 = _2869 * -31; + int32_t _2871 = _2870 >> 8; + int16_t _2872 = (int16_t)(_2871); + uint16_t _2873 = min(_demosaicked_1_stencil_35, _2867); + int32_t _2874 = (int32_t)(_2873); + int32_t _2875 = _2874 * -261; + int32_t _2876 = _2875 >> 8; + int16_t _2877 = (int16_t)(_2876); + int16_t _2878 = _2872 + _2877; + uint16_t _2879 = min(_demosaicked_1_stencil_36, _2867); + int32_t _2880 = (int32_t)(_2879); + int32_t _2881 = _2880 * 883; + int32_t _2882 = _2881 >> 8; + int16_t _2883 = (int16_t)(_2882); + int16_t _2884 = _2878 + _2883; + int16_t _2885 = (int16_t)(-22); + int16_t _2886 = _2884 + _2885; + return _2886; +} + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_1 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _3952 = (uint16_t)(0); + _curvea0[0] = _3952; + uint16_t _3953 = (uint16_t)(4); + _curvea0[1] = _3953; + uint16_t _3954 = (uint16_t)(7); + _curvea0[2] = _3954; + uint16_t _3955 = (uint16_t)(8); + _curvea0[3] = _3955; + uint16_t _3956 = (uint16_t)(10); + _curvea0[4] = _3956; + uint16_t _3957 = (uint16_t)(11); + _curvea0[5] = _3957; + uint16_t _3958 = (uint16_t)(12); + _curvea0[6] = _3958; + uint16_t _3959 = (uint16_t)(13); + _curvea0[7] = _3959; + uint16_t _3960 = (uint16_t)(14); + _curvea0[8] = _3960; + uint16_t _3961 = (uint16_t)(15); + _curvea0[9] = _3961; + uint16_t _3962 = (uint16_t)(16); + _curvea0[10] = _3962; + uint16_t _3963 = (uint16_t)(17); + _curvea0[11] = _3963; + uint16_t _3964 = (uint16_t)(18); + _curvea0[12] = _3964; + uint16_t _3965 = (uint16_t)(19); + _curvea0[13] = _3965; + uint16_t _3966 = (uint16_t)(20); + _curvea0[14] = _3966; + uint16_t _3967 = (uint16_t)(21); + _curvea0[15] = _3967; + uint16_t _3968 = (uint16_t)(22); + _curvea0[16] = _3968; + uint16_t _3969 = (uint16_t)(22); + _curvea0[17] = _3969; + uint16_t _3970 = (uint16_t)(23); + _curvea0[18] = _3970; + uint16_t _3971 = (uint16_t)(24); + _curvea0[19] = _3971; + uint16_t _3972 = (uint16_t)(25); + _curvea0[20] = _3972; + uint16_t _3973 = (uint16_t)(25); + _curvea0[21] = _3973; + uint16_t _3974 = (uint16_t)(26); + _curvea0[22] = _3974; + uint16_t _3975 = (uint16_t)(27); + _curvea0[23] = _3975; + uint16_t _3976 = (uint16_t)(27); + _curvea0[24] = _3976; + uint16_t _3977 = (uint16_t)(28); + _curvea0[25] = _3977; + uint16_t _3978 = (uint16_t)(29); + _curvea0[26] = _3978; + uint16_t _3979 = (uint16_t)(29); + _curvea0[27] = _3979; + uint16_t _3980 = (uint16_t)(30); + _curvea0[28] = _3980; + uint16_t _3981 = (uint16_t)(31); + _curvea0[29] = _3981; + uint16_t _3982 = (uint16_t)(31); + _curvea0[30] = _3982; + uint16_t _3983 = (uint16_t)(32); + _curvea0[31] = _3983; + uint16_t _3984 = (uint16_t)(33); + _curvea0[32] = _3984; + uint16_t _3985 = (uint16_t)(33); + _curvea0[33] = _3985; + uint16_t _3986 = (uint16_t)(34); + _curvea0[34] = _3986; + uint16_t _3987 = (uint16_t)(34); + _curvea0[35] = _3987; + uint16_t _3988 = (uint16_t)(35); + _curvea0[36] = _3988; + uint16_t _3989 = (uint16_t)(36); + _curvea0[37] = _3989; + uint16_t _3990 = (uint16_t)(36); + _curvea0[38] = _3990; + uint16_t _3991 = (uint16_t)(37); + _curvea0[39] = _3991; + uint16_t _3992 = (uint16_t)(37); + _curvea0[40] = _3992; + uint16_t _3993 = (uint16_t)(38); + _curvea0[41] = _3993; + uint16_t _3994 = (uint16_t)(39); + _curvea0[42] = _3994; + uint16_t _3995 = (uint16_t)(39); + _curvea0[43] = _3995; + uint16_t _3996 = (uint16_t)(40); + _curvea0[44] = _3996; + uint16_t _3997 = (uint16_t)(40); + _curvea0[45] = _3997; + uint16_t _3998 = (uint16_t)(41); + _curvea0[46] = _3998; + uint16_t _3999 = (uint16_t)(41); + _curvea0[47] = _3999; + uint16_t _4000 = (uint16_t)(42); + _curvea0[48] = _4000; + uint16_t _4001 = (uint16_t)(42); + _curvea0[49] = _4001; + uint16_t _4002 = (uint16_t)(43); + _curvea0[50] = _4002; + uint16_t _4003 = (uint16_t)(44); + _curvea0[51] = _4003; + uint16_t _4004 = (uint16_t)(44); + _curvea0[52] = _4004; + uint16_t _4005 = (uint16_t)(45); + _curvea0[53] = _4005; + uint16_t _4006 = (uint16_t)(45); + _curvea0[54] = _4006; + uint16_t _4007 = (uint16_t)(46); + _curvea0[55] = _4007; + uint16_t _4008 = (uint16_t)(46); + _curvea0[56] = _4008; + uint16_t _4009 = (uint16_t)(47); + _curvea0[57] = _4009; + uint16_t _4010 = (uint16_t)(47); + _curvea0[58] = _4010; + uint16_t _4011 = (uint16_t)(48); + _curvea0[59] = _4011; + uint16_t _4012 = (uint16_t)(48); + _curvea0[60] = _4012; + uint16_t _4013 = (uint16_t)(49); + _curvea0[61] = _4013; + uint16_t _4014 = (uint16_t)(49); + _curvea0[62] = _4014; + uint16_t _4015 = (uint16_t)(50); + _curvea0[63] = _4015; + uint16_t _4016 = (uint16_t)(50); + _curvea0[64] = _4016; + uint16_t _4017 = (uint16_t)(51); + _curvea0[65] = _4017; + uint16_t _4018 = (uint16_t)(51); + _curvea0[66] = _4018; + uint16_t _4019 = (uint16_t)(52); + _curvea0[67] = _4019; + uint16_t _4020 = (uint16_t)(52); + _curvea0[68] = _4020; + uint16_t _4021 = (uint16_t)(53); + _curvea0[69] = _4021; + uint16_t _4022 = (uint16_t)(53); + _curvea0[70] = _4022; + uint16_t _4023 = (uint16_t)(54); + _curvea0[71] = _4023; + uint16_t _4024 = (uint16_t)(54); + _curvea0[72] = _4024; + uint16_t _4025 = (uint16_t)(55); + _curvea0[73] = _4025; + uint16_t _4026 = (uint16_t)(55); + _curvea0[74] = _4026; + uint16_t _4027 = (uint16_t)(56); + _curvea0[75] = _4027; + uint16_t _4028 = (uint16_t)(56); + _curvea0[76] = _4028; + uint16_t _4029 = (uint16_t)(57); + _curvea0[77] = _4029; + uint16_t _4030 = (uint16_t)(57); + _curvea0[78] = _4030; + uint16_t _4031 = (uint16_t)(58); + _curvea0[79] = _4031; + uint16_t _4032 = (uint16_t)(58); + _curvea0[80] = _4032; + uint16_t _4033 = (uint16_t)(58); + _curvea0[81] = _4033; + uint16_t _4034 = (uint16_t)(59); + _curvea0[82] = _4034; + uint16_t _4035 = (uint16_t)(59); + _curvea0[83] = _4035; + uint16_t _4036 = (uint16_t)(60); + _curvea0[84] = _4036; + uint16_t _4037 = (uint16_t)(60); + _curvea0[85] = _4037; + uint16_t _4038 = (uint16_t)(61); + _curvea0[86] = _4038; + uint16_t _4039 = (uint16_t)(61); + _curvea0[87] = _4039; + uint16_t _4040 = (uint16_t)(62); + _curvea0[88] = _4040; + uint16_t _4041 = (uint16_t)(62); + _curvea0[89] = _4041; + uint16_t _4042 = (uint16_t)(63); + _curvea0[90] = _4042; + uint16_t _4043 = (uint16_t)(63); + _curvea0[91] = _4043; + uint16_t _4044 = (uint16_t)(64); + _curvea0[92] = _4044; + uint16_t _4045 = (uint16_t)(64); + _curvea0[93] = _4045; + uint16_t _4046 = (uint16_t)(64); + _curvea0[94] = _4046; + uint16_t _4047 = (uint16_t)(65); + _curvea0[95] = _4047; + uint16_t _4048 = (uint16_t)(65); + _curvea0[96] = _4048; + uint16_t _4049 = (uint16_t)(66); + _curvea0[97] = _4049; + uint16_t _4050 = (uint16_t)(66); + _curvea0[98] = _4050; + uint16_t _4051 = (uint16_t)(67); + _curvea0[99] = _4051; + uint16_t _4052 = (uint16_t)(67); + _curvea0[100] = _4052; + uint16_t _4053 = (uint16_t)(68); + _curvea0[101] = _4053; + uint16_t _4054 = (uint16_t)(68); + _curvea0[102] = _4054; + uint16_t _4055 = (uint16_t)(68); + _curvea0[103] = _4055; + uint16_t _4056 = (uint16_t)(69); + _curvea0[104] = _4056; + uint16_t _4057 = (uint16_t)(69); + _curvea0[105] = _4057; + uint16_t _4058 = (uint16_t)(70); + _curvea0[106] = _4058; + uint16_t _4059 = (uint16_t)(70); + _curvea0[107] = _4059; + uint16_t _4060 = (uint16_t)(71); + _curvea0[108] = _4060; + uint16_t _4061 = (uint16_t)(71); + _curvea0[109] = _4061; + uint16_t _4062 = (uint16_t)(71); + _curvea0[110] = _4062; + uint16_t _4063 = (uint16_t)(72); + _curvea0[111] = _4063; + uint16_t _4064 = (uint16_t)(72); + _curvea0[112] = _4064; + uint16_t _4065 = (uint16_t)(73); + _curvea0[113] = _4065; + uint16_t _4066 = (uint16_t)(73); + _curvea0[114] = _4066; + uint16_t _4067 = (uint16_t)(74); + _curvea0[115] = _4067; + uint16_t _4068 = (uint16_t)(74); + _curvea0[116] = _4068; + uint16_t _4069 = (uint16_t)(74); + _curvea0[117] = _4069; + uint16_t _4070 = (uint16_t)(75); + _curvea0[118] = _4070; + uint16_t _4071 = (uint16_t)(75); + _curvea0[119] = _4071; + uint16_t _4072 = (uint16_t)(76); + _curvea0[120] = _4072; + uint16_t _4073 = (uint16_t)(76); + _curvea0[121] = _4073; + uint16_t _4074 = (uint16_t)(77); + _curvea0[122] = _4074; + uint16_t _4075 = (uint16_t)(77); + _curvea0[123] = _4075; + uint16_t _4076 = (uint16_t)(77); + _curvea0[124] = _4076; + uint16_t _4077 = (uint16_t)(78); + _curvea0[125] = _4077; + uint16_t _4078 = (uint16_t)(78); + _curvea0[126] = _4078; + uint16_t _4079 = (uint16_t)(79); + _curvea0[127] = _4079; + uint16_t _4080 = (uint16_t)(79); + _curvea0[128] = _4080; + uint16_t _4081 = (uint16_t)(79); + _curvea0[129] = _4081; + uint16_t _4082 = (uint16_t)(80); + _curvea0[130] = _4082; + uint16_t _4083 = (uint16_t)(80); + _curvea0[131] = _4083; + uint16_t _4084 = (uint16_t)(81); + _curvea0[132] = _4084; + uint16_t _4085 = (uint16_t)(81); + _curvea0[133] = _4085; + uint16_t _4086 = (uint16_t)(82); + _curvea0[134] = _4086; + uint16_t _4087 = (uint16_t)(82); + _curvea0[135] = _4087; + uint16_t _4088 = (uint16_t)(82); + _curvea0[136] = _4088; + uint16_t _4089 = (uint16_t)(83); + _curvea0[137] = _4089; + uint16_t _4090 = (uint16_t)(83); + _curvea0[138] = _4090; + uint16_t _4091 = (uint16_t)(84); + _curvea0[139] = _4091; + uint16_t _4092 = (uint16_t)(84); + _curvea0[140] = _4092; + uint16_t _4093 = (uint16_t)(84); + _curvea0[141] = _4093; + uint16_t _4094 = (uint16_t)(85); + _curvea0[142] = _4094; + uint16_t _4095 = (uint16_t)(85); + _curvea0[143] = _4095; + uint16_t _4096 = (uint16_t)(86); + _curvea0[144] = _4096; + uint16_t _4097 = (uint16_t)(86); + _curvea0[145] = _4097; + uint16_t _4098 = (uint16_t)(86); + _curvea0[146] = _4098; + uint16_t _4099 = (uint16_t)(87); + _curvea0[147] = _4099; + uint16_t _4100 = (uint16_t)(87); + _curvea0[148] = _4100; + uint16_t _4101 = (uint16_t)(88); + _curvea0[149] = _4101; + uint16_t _4102 = (uint16_t)(88); + _curvea0[150] = _4102; + uint16_t _4103 = (uint16_t)(88); + _curvea0[151] = _4103; + uint16_t _4104 = (uint16_t)(89); + _curvea0[152] = _4104; + uint16_t _4105 = (uint16_t)(89); + _curvea0[153] = _4105; + uint16_t _4106 = (uint16_t)(90); + _curvea0[154] = _4106; + uint16_t _4107 = (uint16_t)(90); + _curvea0[155] = _4107; + uint16_t _4108 = (uint16_t)(90); + _curvea0[156] = _4108; + uint16_t _4109 = (uint16_t)(91); + _curvea0[157] = _4109; + uint16_t _4110 = (uint16_t)(91); + _curvea0[158] = _4110; + uint16_t _4111 = (uint16_t)(92); + _curvea0[159] = _4111; + uint16_t _4112 = (uint16_t)(92); + _curvea0[160] = _4112; + uint16_t _4113 = (uint16_t)(92); + _curvea0[161] = _4113; + uint16_t _4114 = (uint16_t)(93); + _curvea0[162] = _4114; + uint16_t _4115 = (uint16_t)(93); + _curvea0[163] = _4115; + uint16_t _4116 = (uint16_t)(93); + _curvea0[164] = _4116; + uint16_t _4117 = (uint16_t)(94); + _curvea0[165] = _4117; + uint16_t _4118 = (uint16_t)(94); + _curvea0[166] = _4118; + uint16_t _4119 = (uint16_t)(95); + _curvea0[167] = _4119; + uint16_t _4120 = (uint16_t)(95); + _curvea0[168] = _4120; + uint16_t _4121 = (uint16_t)(95); + _curvea0[169] = _4121; + uint16_t _4122 = (uint16_t)(96); + _curvea0[170] = _4122; + uint16_t _4123 = (uint16_t)(96); + _curvea0[171] = _4123; + uint16_t _4124 = (uint16_t)(97); + _curvea0[172] = _4124; + uint16_t _4125 = (uint16_t)(97); + _curvea0[173] = _4125; + uint16_t _4126 = (uint16_t)(97); + _curvea0[174] = _4126; + uint16_t _4127 = (uint16_t)(98); + _curvea0[175] = _4127; + uint16_t _4128 = (uint16_t)(98); + _curvea0[176] = _4128; + uint16_t _4129 = (uint16_t)(99); + _curvea0[177] = _4129; + uint16_t _4130 = (uint16_t)(99); + _curvea0[178] = _4130; + uint16_t _4131 = (uint16_t)(99); + _curvea0[179] = _4131; + uint16_t _4132 = (uint16_t)(100); + _curvea0[180] = _4132; + uint16_t _4133 = (uint16_t)(100); + _curvea0[181] = _4133; + uint16_t _4134 = (uint16_t)(100); + _curvea0[182] = _4134; + uint16_t _4135 = (uint16_t)(101); + _curvea0[183] = _4135; + uint16_t _4136 = (uint16_t)(101); + _curvea0[184] = _4136; + uint16_t _4137 = (uint16_t)(102); + _curvea0[185] = _4137; + uint16_t _4138 = (uint16_t)(102); + _curvea0[186] = _4138; + uint16_t _4139 = (uint16_t)(102); + _curvea0[187] = _4139; + uint16_t _4140 = (uint16_t)(103); + _curvea0[188] = _4140; + uint16_t _4141 = (uint16_t)(103); + _curvea0[189] = _4141; + uint16_t _4142 = (uint16_t)(103); + _curvea0[190] = _4142; + uint16_t _4143 = (uint16_t)(104); + _curvea0[191] = _4143; + uint16_t _4144 = (uint16_t)(104); + _curvea0[192] = _4144; + uint16_t _4145 = (uint16_t)(105); + _curvea0[193] = _4145; + uint16_t _4146 = (uint16_t)(105); + _curvea0[194] = _4146; + uint16_t _4147 = (uint16_t)(105); + _curvea0[195] = _4147; + uint16_t _4148 = (uint16_t)(106); + _curvea0[196] = _4148; + uint16_t _4149 = (uint16_t)(106); + _curvea0[197] = _4149; + uint16_t _4150 = (uint16_t)(106); + _curvea0[198] = _4150; + uint16_t _4151 = (uint16_t)(107); + _curvea0[199] = _4151; + uint16_t _4152 = (uint16_t)(107); + _curvea0[200] = _4152; + uint16_t _4153 = (uint16_t)(108); + _curvea0[201] = _4153; + uint16_t _4154 = (uint16_t)(108); + _curvea0[202] = _4154; + uint16_t _4155 = (uint16_t)(108); + _curvea0[203] = _4155; + uint16_t _4156 = (uint16_t)(109); + _curvea0[204] = _4156; + uint16_t _4157 = (uint16_t)(109); + _curvea0[205] = _4157; + uint16_t _4158 = (uint16_t)(109); + _curvea0[206] = _4158; + uint16_t _4159 = (uint16_t)(110); + _curvea0[207] = _4159; + uint16_t _4160 = (uint16_t)(110); + _curvea0[208] = _4160; + uint16_t _4161 = (uint16_t)(111); + _curvea0[209] = _4161; + uint16_t _4162 = (uint16_t)(111); + _curvea0[210] = _4162; + uint16_t _4163 = (uint16_t)(111); + _curvea0[211] = _4163; + uint16_t _4164 = (uint16_t)(112); + _curvea0[212] = _4164; + uint16_t _4165 = (uint16_t)(112); + _curvea0[213] = _4165; + uint16_t _4166 = (uint16_t)(112); + _curvea0[214] = _4166; + uint16_t _4167 = (uint16_t)(113); + _curvea0[215] = _4167; + uint16_t _4168 = (uint16_t)(113); + _curvea0[216] = _4168; + uint16_t _4169 = (uint16_t)(113); + _curvea0[217] = _4169; + uint16_t _4170 = (uint16_t)(114); + _curvea0[218] = _4170; + uint16_t _4171 = (uint16_t)(114); + _curvea0[219] = _4171; + uint16_t _4172 = (uint16_t)(115); + _curvea0[220] = _4172; + uint16_t _4173 = (uint16_t)(115); + _curvea0[221] = _4173; + uint16_t _4174 = (uint16_t)(115); + _curvea0[222] = _4174; + uint16_t _4175 = (uint16_t)(116); + _curvea0[223] = _4175; + uint16_t _4176 = (uint16_t)(116); + _curvea0[224] = _4176; + uint16_t _4177 = (uint16_t)(116); + _curvea0[225] = _4177; + uint16_t _4178 = (uint16_t)(117); + _curvea0[226] = _4178; + uint16_t _4179 = (uint16_t)(117); + _curvea0[227] = _4179; + uint16_t _4180 = (uint16_t)(117); + _curvea0[228] = _4180; + uint16_t _4181 = (uint16_t)(118); + _curvea0[229] = _4181; + uint16_t _4182 = (uint16_t)(118); + _curvea0[230] = _4182; + uint16_t _4183 = (uint16_t)(119); + _curvea0[231] = _4183; + uint16_t _4184 = (uint16_t)(119); + _curvea0[232] = _4184; + uint16_t _4185 = (uint16_t)(119); + _curvea0[233] = _4185; + uint16_t _4186 = (uint16_t)(120); + _curvea0[234] = _4186; + uint16_t _4187 = (uint16_t)(120); + _curvea0[235] = _4187; + uint16_t _4188 = (uint16_t)(120); + _curvea0[236] = _4188; + uint16_t _4189 = (uint16_t)(121); + _curvea0[237] = _4189; + uint16_t _4190 = (uint16_t)(121); + _curvea0[238] = _4190; + uint16_t _4191 = (uint16_t)(121); + _curvea0[239] = _4191; + uint16_t _4192 = (uint16_t)(122); + _curvea0[240] = _4192; + uint16_t _4193 = (uint16_t)(122); + _curvea0[241] = _4193; + uint16_t _4194 = (uint16_t)(123); + _curvea0[242] = _4194; + uint16_t _4195 = (uint16_t)(123); + _curvea0[243] = _4195; + uint16_t _4196 = (uint16_t)(123); + _curvea0[244] = _4196; + uint16_t _4197 = (uint16_t)(124); + _curvea0[245] = _4197; + uint16_t _4198 = (uint16_t)(124); + _curvea0[246] = _4198; + uint16_t _4199 = (uint16_t)(124); + _curvea0[247] = _4199; + uint16_t _4200 = (uint16_t)(125); + _curvea0[248] = _4200; + uint16_t _4201 = (uint16_t)(125); + _curvea0[249] = _4201; + uint16_t _4202 = (uint16_t)(125); + _curvea0[250] = _4202; + uint16_t _4203 = (uint16_t)(126); + _curvea0[251] = _4203; + uint16_t _4204 = (uint16_t)(126); + _curvea0[252] = _4204; + uint16_t _4205 = (uint16_t)(126); + _curvea0[253] = _4205; + uint16_t _4206 = (uint16_t)(127); + _curvea0[254] = _4206; + uint16_t _4207 = (uint16_t)(127); + _curvea0[255] = _4207; + uint16_t _4208 = (uint16_t)(128); + _curvea0[256] = _4208; + uint16_t _4209 = (uint16_t)(128); + _curvea0[257] = _4209; + uint16_t _4210 = (uint16_t)(128); + _curvea0[258] = _4210; + uint16_t _4211 = (uint16_t)(129); + _curvea0[259] = _4211; + uint16_t _4212 = (uint16_t)(129); + _curvea0[260] = _4212; + uint16_t _4213 = (uint16_t)(129); + _curvea0[261] = _4213; + uint16_t _4214 = (uint16_t)(130); + _curvea0[262] = _4214; + uint16_t _4215 = (uint16_t)(130); + _curvea0[263] = _4215; + uint16_t _4216 = (uint16_t)(130); + _curvea0[264] = _4216; + uint16_t _4217 = (uint16_t)(131); + _curvea0[265] = _4217; + uint16_t _4218 = (uint16_t)(131); + _curvea0[266] = _4218; + uint16_t _4219 = (uint16_t)(131); + _curvea0[267] = _4219; + uint16_t _4220 = (uint16_t)(132); + _curvea0[268] = _4220; + uint16_t _4221 = (uint16_t)(132); + _curvea0[269] = _4221; + uint16_t _4222 = (uint16_t)(132); + _curvea0[270] = _4222; + uint16_t _4223 = (uint16_t)(133); + _curvea0[271] = _4223; + uint16_t _4224 = (uint16_t)(133); + _curvea0[272] = _4224; + uint16_t _4225 = (uint16_t)(133); + _curvea0[273] = _4225; + uint16_t _4226 = (uint16_t)(134); + _curvea0[274] = _4226; + uint16_t _4227 = (uint16_t)(134); + _curvea0[275] = _4227; + uint16_t _4228 = (uint16_t)(134); + _curvea0[276] = _4228; + uint16_t _4229 = (uint16_t)(135); + _curvea0[277] = _4229; + uint16_t _4230 = (uint16_t)(135); + _curvea0[278] = _4230; + uint16_t _4231 = (uint16_t)(135); + _curvea0[279] = _4231; + uint16_t _4232 = (uint16_t)(136); + _curvea0[280] = _4232; + uint16_t _4233 = (uint16_t)(136); + _curvea0[281] = _4233; + uint16_t _4234 = (uint16_t)(136); + _curvea0[282] = _4234; + uint16_t _4235 = (uint16_t)(137); + _curvea0[283] = _4235; + uint16_t _4236 = (uint16_t)(137); + _curvea0[284] = _4236; + uint16_t _4237 = (uint16_t)(137); + _curvea0[285] = _4237; + uint16_t _4238 = (uint16_t)(138); + _curvea0[286] = _4238; + uint16_t _4239 = (uint16_t)(138); + _curvea0[287] = _4239; + uint16_t _4240 = (uint16_t)(138); + _curvea0[288] = _4240; + uint16_t _4241 = (uint16_t)(139); + _curvea0[289] = _4241; + uint16_t _4242 = (uint16_t)(139); + _curvea0[290] = _4242; + uint16_t _4243 = (uint16_t)(139); + _curvea0[291] = _4243; + uint16_t _4244 = (uint16_t)(140); + _curvea0[292] = _4244; + uint16_t _4245 = (uint16_t)(140); + _curvea0[293] = _4245; + uint16_t _4246 = (uint16_t)(140); + _curvea0[294] = _4246; + uint16_t _4247 = (uint16_t)(141); + _curvea0[295] = _4247; + uint16_t _4248 = (uint16_t)(141); + _curvea0[296] = _4248; + uint16_t _4249 = (uint16_t)(141); + _curvea0[297] = _4249; + uint16_t _4250 = (uint16_t)(141); + _curvea0[298] = _4250; + uint16_t _4251 = (uint16_t)(142); + _curvea0[299] = _4251; + uint16_t _4252 = (uint16_t)(142); + _curvea0[300] = _4252; + uint16_t _4253 = (uint16_t)(142); + _curvea0[301] = _4253; + uint16_t _4254 = (uint16_t)(143); + _curvea0[302] = _4254; + uint16_t _4255 = (uint16_t)(143); + _curvea0[303] = _4255; + uint16_t _4256 = (uint16_t)(143); + _curvea0[304] = _4256; + uint16_t _4257 = (uint16_t)(144); + _curvea0[305] = _4257; + uint16_t _4258 = (uint16_t)(144); + _curvea0[306] = _4258; + uint16_t _4259 = (uint16_t)(144); + _curvea0[307] = _4259; + uint16_t _4260 = (uint16_t)(145); + _curvea0[308] = _4260; + uint16_t _4261 = (uint16_t)(145); + _curvea0[309] = _4261; + uint16_t _4262 = (uint16_t)(145); + _curvea0[310] = _4262; + uint16_t _4263 = (uint16_t)(145); + _curvea0[311] = _4263; + uint16_t _4264 = (uint16_t)(146); + _curvea0[312] = _4264; + uint16_t _4265 = (uint16_t)(146); + _curvea0[313] = _4265; + uint16_t _4266 = (uint16_t)(146); + _curvea0[314] = _4266; + uint16_t _4267 = (uint16_t)(147); + _curvea0[315] = _4267; + uint16_t _4268 = (uint16_t)(147); + _curvea0[316] = _4268; + uint16_t _4269 = (uint16_t)(147); + _curvea0[317] = _4269; + uint16_t _4270 = (uint16_t)(148); + _curvea0[318] = _4270; + uint16_t _4271 = (uint16_t)(148); + _curvea0[319] = _4271; + uint16_t _4272 = (uint16_t)(148); + _curvea0[320] = _4272; + uint16_t _4273 = (uint16_t)(148); + _curvea0[321] = _4273; + uint16_t _4274 = (uint16_t)(149); + _curvea0[322] = _4274; + uint16_t _4275 = (uint16_t)(149); + _curvea0[323] = _4275; + uint16_t _4276 = (uint16_t)(149); + _curvea0[324] = _4276; + uint16_t _4277 = (uint16_t)(150); + _curvea0[325] = _4277; + uint16_t _4278 = (uint16_t)(150); + _curvea0[326] = _4278; + uint16_t _4279 = (uint16_t)(150); + _curvea0[327] = _4279; + uint16_t _4280 = (uint16_t)(150); + _curvea0[328] = _4280; + uint16_t _4281 = (uint16_t)(151); + _curvea0[329] = _4281; + uint16_t _4282 = (uint16_t)(151); + _curvea0[330] = _4282; + uint16_t _4283 = (uint16_t)(151); + _curvea0[331] = _4283; + uint16_t _4284 = (uint16_t)(152); + _curvea0[332] = _4284; + uint16_t _4285 = (uint16_t)(152); + _curvea0[333] = _4285; + uint16_t _4286 = (uint16_t)(152); + _curvea0[334] = _4286; + uint16_t _4287 = (uint16_t)(152); + _curvea0[335] = _4287; + uint16_t _4288 = (uint16_t)(153); + _curvea0[336] = _4288; + uint16_t _4289 = (uint16_t)(153); + _curvea0[337] = _4289; + uint16_t _4290 = (uint16_t)(153); + _curvea0[338] = _4290; + uint16_t _4291 = (uint16_t)(154); + _curvea0[339] = _4291; + uint16_t _4292 = (uint16_t)(154); + _curvea0[340] = _4292; + uint16_t _4293 = (uint16_t)(154); + _curvea0[341] = _4293; + uint16_t _4294 = (uint16_t)(154); + _curvea0[342] = _4294; + uint16_t _4295 = (uint16_t)(155); + _curvea0[343] = _4295; + uint16_t _4296 = (uint16_t)(155); + _curvea0[344] = _4296; + uint16_t _4297 = (uint16_t)(155); + _curvea0[345] = _4297; + uint16_t _4298 = (uint16_t)(156); + _curvea0[346] = _4298; + uint16_t _4299 = (uint16_t)(156); + _curvea0[347] = _4299; + uint16_t _4300 = (uint16_t)(156); + _curvea0[348] = _4300; + uint16_t _4301 = (uint16_t)(156); + _curvea0[349] = _4301; + uint16_t _4302 = (uint16_t)(157); + _curvea0[350] = _4302; + uint16_t _4303 = (uint16_t)(157); + _curvea0[351] = _4303; + uint16_t _4304 = (uint16_t)(157); + _curvea0[352] = _4304; + uint16_t _4305 = (uint16_t)(157); + _curvea0[353] = _4305; + uint16_t _4306 = (uint16_t)(158); + _curvea0[354] = _4306; + uint16_t _4307 = (uint16_t)(158); + _curvea0[355] = _4307; + uint16_t _4308 = (uint16_t)(158); + _curvea0[356] = _4308; + uint16_t _4309 = (uint16_t)(159); + _curvea0[357] = _4309; + uint16_t _4310 = (uint16_t)(159); + _curvea0[358] = _4310; + uint16_t _4311 = (uint16_t)(159); + _curvea0[359] = _4311; + uint16_t _4312 = (uint16_t)(159); + _curvea0[360] = _4312; + uint16_t _4313 = (uint16_t)(160); + _curvea0[361] = _4313; + uint16_t _4314 = (uint16_t)(160); + _curvea0[362] = _4314; + uint16_t _4315 = (uint16_t)(160); + _curvea0[363] = _4315; + uint16_t _4316 = (uint16_t)(160); + _curvea0[364] = _4316; + uint16_t _4317 = (uint16_t)(161); + _curvea0[365] = _4317; + uint16_t _4318 = (uint16_t)(161); + _curvea0[366] = _4318; + uint16_t _4319 = (uint16_t)(161); + _curvea0[367] = _4319; + uint16_t _4320 = (uint16_t)(161); + _curvea0[368] = _4320; + uint16_t _4321 = (uint16_t)(162); + _curvea0[369] = _4321; + uint16_t _4322 = (uint16_t)(162); + _curvea0[370] = _4322; + uint16_t _4323 = (uint16_t)(162); + _curvea0[371] = _4323; + uint16_t _4324 = (uint16_t)(162); + _curvea0[372] = _4324; + uint16_t _4325 = (uint16_t)(163); + _curvea0[373] = _4325; + uint16_t _4326 = (uint16_t)(163); + _curvea0[374] = _4326; + uint16_t _4327 = (uint16_t)(163); + _curvea0[375] = _4327; + uint16_t _4328 = (uint16_t)(163); + _curvea0[376] = _4328; + uint16_t _4329 = (uint16_t)(164); + _curvea0[377] = _4329; + uint16_t _4330 = (uint16_t)(164); + _curvea0[378] = _4330; + uint16_t _4331 = (uint16_t)(164); + _curvea0[379] = _4331; + uint16_t _4332 = (uint16_t)(164); + _curvea0[380] = _4332; + uint16_t _4333 = (uint16_t)(165); + _curvea0[381] = _4333; + uint16_t _4334 = (uint16_t)(165); + _curvea0[382] = _4334; + uint16_t _4335 = (uint16_t)(165); + _curvea0[383] = _4335; + uint16_t _4336 = (uint16_t)(166); + _curvea0[384] = _4336; + uint16_t _4337 = (uint16_t)(166); + _curvea0[385] = _4337; + uint16_t _4338 = (uint16_t)(166); + _curvea0[386] = _4338; + uint16_t _4339 = (uint16_t)(166); + _curvea0[387] = _4339; + uint16_t _4340 = (uint16_t)(167); + _curvea0[388] = _4340; + uint16_t _4341 = (uint16_t)(167); + _curvea0[389] = _4341; + uint16_t _4342 = (uint16_t)(167); + _curvea0[390] = _4342; + uint16_t _4343 = (uint16_t)(167); + _curvea0[391] = _4343; + uint16_t _4344 = (uint16_t)(167); + _curvea0[392] = _4344; + uint16_t _4345 = (uint16_t)(168); + _curvea0[393] = _4345; + uint16_t _4346 = (uint16_t)(168); + _curvea0[394] = _4346; + uint16_t _4347 = (uint16_t)(168); + _curvea0[395] = _4347; + uint16_t _4348 = (uint16_t)(168); + _curvea0[396] = _4348; + uint16_t _4349 = (uint16_t)(169); + _curvea0[397] = _4349; + uint16_t _4350 = (uint16_t)(169); + _curvea0[398] = _4350; + uint16_t _4351 = (uint16_t)(169); + _curvea0[399] = _4351; + uint16_t _4352 = (uint16_t)(169); + _curvea0[400] = _4352; + uint16_t _4353 = (uint16_t)(170); + _curvea0[401] = _4353; + uint16_t _4354 = (uint16_t)(170); + _curvea0[402] = _4354; + uint16_t _4355 = (uint16_t)(170); + _curvea0[403] = _4355; + uint16_t _4356 = (uint16_t)(170); + _curvea0[404] = _4356; + uint16_t _4357 = (uint16_t)(171); + _curvea0[405] = _4357; + uint16_t _4358 = (uint16_t)(171); + _curvea0[406] = _4358; + uint16_t _4359 = (uint16_t)(171); + _curvea0[407] = _4359; + uint16_t _4360 = (uint16_t)(171); + _curvea0[408] = _4360; + uint16_t _4361 = (uint16_t)(172); + _curvea0[409] = _4361; + uint16_t _4362 = (uint16_t)(172); + _curvea0[410] = _4362; + uint16_t _4363 = (uint16_t)(172); + _curvea0[411] = _4363; + uint16_t _4364 = (uint16_t)(172); + _curvea0[412] = _4364; + uint16_t _4365 = (uint16_t)(173); + _curvea0[413] = _4365; + uint16_t _4366 = (uint16_t)(173); + _curvea0[414] = _4366; + uint16_t _4367 = (uint16_t)(173); + _curvea0[415] = _4367; + uint16_t _4368 = (uint16_t)(173); + _curvea0[416] = _4368; + uint16_t _4369 = (uint16_t)(173); + _curvea0[417] = _4369; + uint16_t _4370 = (uint16_t)(174); + _curvea0[418] = _4370; + uint16_t _4371 = (uint16_t)(174); + _curvea0[419] = _4371; + uint16_t _4372 = (uint16_t)(174); + _curvea0[420] = _4372; + uint16_t _4373 = (uint16_t)(174); + _curvea0[421] = _4373; + uint16_t _4374 = (uint16_t)(175); + _curvea0[422] = _4374; + uint16_t _4375 = (uint16_t)(175); + _curvea0[423] = _4375; + uint16_t _4376 = (uint16_t)(175); + _curvea0[424] = _4376; + uint16_t _4377 = (uint16_t)(175); + _curvea0[425] = _4377; + uint16_t _4378 = (uint16_t)(176); + _curvea0[426] = _4378; + uint16_t _4379 = (uint16_t)(176); + _curvea0[427] = _4379; + uint16_t _4380 = (uint16_t)(176); + _curvea0[428] = _4380; + uint16_t _4381 = (uint16_t)(176); + _curvea0[429] = _4381; + uint16_t _4382 = (uint16_t)(176); + _curvea0[430] = _4382; + uint16_t _4383 = (uint16_t)(177); + _curvea0[431] = _4383; + uint16_t _4384 = (uint16_t)(177); + _curvea0[432] = _4384; + uint16_t _4385 = (uint16_t)(177); + _curvea0[433] = _4385; + uint16_t _4386 = (uint16_t)(177); + _curvea0[434] = _4386; + uint16_t _4387 = (uint16_t)(178); + _curvea0[435] = _4387; + uint16_t _4388 = (uint16_t)(178); + _curvea0[436] = _4388; + uint16_t _4389 = (uint16_t)(178); + _curvea0[437] = _4389; + uint16_t _4390 = (uint16_t)(178); + _curvea0[438] = _4390; + uint16_t _4391 = (uint16_t)(178); + _curvea0[439] = _4391; + uint16_t _4392 = (uint16_t)(179); + _curvea0[440] = _4392; + uint16_t _4393 = (uint16_t)(179); + _curvea0[441] = _4393; + uint16_t _4394 = (uint16_t)(179); + _curvea0[442] = _4394; + uint16_t _4395 = (uint16_t)(179); + _curvea0[443] = _4395; + uint16_t _4396 = (uint16_t)(180); + _curvea0[444] = _4396; + uint16_t _4397 = (uint16_t)(180); + _curvea0[445] = _4397; + uint16_t _4398 = (uint16_t)(180); + _curvea0[446] = _4398; + uint16_t _4399 = (uint16_t)(180); + _curvea0[447] = _4399; + uint16_t _4400 = (uint16_t)(180); + _curvea0[448] = _4400; + uint16_t _4401 = (uint16_t)(181); + _curvea0[449] = _4401; + uint16_t _4402 = (uint16_t)(181); + _curvea0[450] = _4402; + uint16_t _4403 = (uint16_t)(181); + _curvea0[451] = _4403; + uint16_t _4404 = (uint16_t)(181); + _curvea0[452] = _4404; + uint16_t _4405 = (uint16_t)(181); + _curvea0[453] = _4405; + uint16_t _4406 = (uint16_t)(182); + _curvea0[454] = _4406; + uint16_t _4407 = (uint16_t)(182); + _curvea0[455] = _4407; + uint16_t _4408 = (uint16_t)(182); + _curvea0[456] = _4408; + uint16_t _4409 = (uint16_t)(182); + _curvea0[457] = _4409; + uint16_t _4410 = (uint16_t)(183); + _curvea0[458] = _4410; + uint16_t _4411 = (uint16_t)(183); + _curvea0[459] = _4411; + uint16_t _4412 = (uint16_t)(183); + _curvea0[460] = _4412; + uint16_t _4413 = (uint16_t)(183); + _curvea0[461] = _4413; + uint16_t _4414 = (uint16_t)(183); + _curvea0[462] = _4414; + uint16_t _4415 = (uint16_t)(184); + _curvea0[463] = _4415; + uint16_t _4416 = (uint16_t)(184); + _curvea0[464] = _4416; + uint16_t _4417 = (uint16_t)(184); + _curvea0[465] = _4417; + uint16_t _4418 = (uint16_t)(184); + _curvea0[466] = _4418; + uint16_t _4419 = (uint16_t)(184); + _curvea0[467] = _4419; + uint16_t _4420 = (uint16_t)(185); + _curvea0[468] = _4420; + uint16_t _4421 = (uint16_t)(185); + _curvea0[469] = _4421; + uint16_t _4422 = (uint16_t)(185); + _curvea0[470] = _4422; + uint16_t _4423 = (uint16_t)(185); + _curvea0[471] = _4423; + uint16_t _4424 = (uint16_t)(185); + _curvea0[472] = _4424; + uint16_t _4425 = (uint16_t)(186); + _curvea0[473] = _4425; + uint16_t _4426 = (uint16_t)(186); + _curvea0[474] = _4426; + uint16_t _4427 = (uint16_t)(186); + _curvea0[475] = _4427; + uint16_t _4428 = (uint16_t)(186); + _curvea0[476] = _4428; + uint16_t _4429 = (uint16_t)(187); + _curvea0[477] = _4429; + uint16_t _4430 = (uint16_t)(187); + _curvea0[478] = _4430; + uint16_t _4431 = (uint16_t)(187); + _curvea0[479] = _4431; + uint16_t _4432 = (uint16_t)(187); + _curvea0[480] = _4432; + uint16_t _4433 = (uint16_t)(187); + _curvea0[481] = _4433; + uint16_t _4434 = (uint16_t)(188); + _curvea0[482] = _4434; + uint16_t _4435 = (uint16_t)(188); + _curvea0[483] = _4435; + uint16_t _4436 = (uint16_t)(188); + _curvea0[484] = _4436; + uint16_t _4437 = (uint16_t)(188); + _curvea0[485] = _4437; + uint16_t _4438 = (uint16_t)(188); + _curvea0[486] = _4438; + uint16_t _4439 = (uint16_t)(189); + _curvea0[487] = _4439; + uint16_t _4440 = (uint16_t)(189); + _curvea0[488] = _4440; + uint16_t _4441 = (uint16_t)(189); + _curvea0[489] = _4441; + uint16_t _4442 = (uint16_t)(189); + _curvea0[490] = _4442; + uint16_t _4443 = (uint16_t)(189); + _curvea0[491] = _4443; + uint16_t _4444 = (uint16_t)(190); + _curvea0[492] = _4444; + uint16_t _4445 = (uint16_t)(190); + _curvea0[493] = _4445; + uint16_t _4446 = (uint16_t)(190); + _curvea0[494] = _4446; + uint16_t _4447 = (uint16_t)(190); + _curvea0[495] = _4447; + uint16_t _4448 = (uint16_t)(190); + _curvea0[496] = _4448; + uint16_t _4449 = (uint16_t)(190); + _curvea0[497] = _4449; + uint16_t _4450 = (uint16_t)(191); + _curvea0[498] = _4450; + uint16_t _4451 = (uint16_t)(191); + _curvea0[499] = _4451; + uint16_t _4452 = (uint16_t)(191); + _curvea0[500] = _4452; + uint16_t _4453 = (uint16_t)(191); + _curvea0[501] = _4453; + uint16_t _4454 = (uint16_t)(191); + _curvea0[502] = _4454; + uint16_t _4455 = (uint16_t)(192); + _curvea0[503] = _4455; + uint16_t _4456 = (uint16_t)(192); + _curvea0[504] = _4456; + uint16_t _4457 = (uint16_t)(192); + _curvea0[505] = _4457; + uint16_t _4458 = (uint16_t)(192); + _curvea0[506] = _4458; + uint16_t _4459 = (uint16_t)(192); + _curvea0[507] = _4459; + uint16_t _4460 = (uint16_t)(193); + _curvea0[508] = _4460; + uint16_t _4461 = (uint16_t)(193); + _curvea0[509] = _4461; + uint16_t _4462 = (uint16_t)(193); + _curvea0[510] = _4462; + uint16_t _4463 = (uint16_t)(193); + _curvea0[511] = _4463; + uint16_t _4464 = (uint16_t)(193); + _curvea0[512] = _4464; + uint16_t _4465 = (uint16_t)(194); + _curvea0[513] = _4465; + uint16_t _4466 = (uint16_t)(194); + _curvea0[514] = _4466; + uint16_t _4467 = (uint16_t)(194); + _curvea0[515] = _4467; + uint16_t _4468 = (uint16_t)(194); + _curvea0[516] = _4468; + uint16_t _4469 = (uint16_t)(194); + _curvea0[517] = _4469; + uint16_t _4470 = (uint16_t)(195); + _curvea0[518] = _4470; + uint16_t _4471 = (uint16_t)(195); + _curvea0[519] = _4471; + uint16_t _4472 = (uint16_t)(195); + _curvea0[520] = _4472; + uint16_t _4473 = (uint16_t)(195); + _curvea0[521] = _4473; + uint16_t _4474 = (uint16_t)(195); + _curvea0[522] = _4474; + uint16_t _4475 = (uint16_t)(195); + _curvea0[523] = _4475; + uint16_t _4476 = (uint16_t)(196); + _curvea0[524] = _4476; + uint16_t _4477 = (uint16_t)(196); + _curvea0[525] = _4477; + uint16_t _4478 = (uint16_t)(196); + _curvea0[526] = _4478; + uint16_t _4479 = (uint16_t)(196); + _curvea0[527] = _4479; + uint16_t _4480 = (uint16_t)(196); + _curvea0[528] = _4480; + uint16_t _4481 = (uint16_t)(197); + _curvea0[529] = _4481; + uint16_t _4482 = (uint16_t)(197); + _curvea0[530] = _4482; + uint16_t _4483 = (uint16_t)(197); + _curvea0[531] = _4483; + uint16_t _4484 = (uint16_t)(197); + _curvea0[532] = _4484; + uint16_t _4485 = (uint16_t)(197); + _curvea0[533] = _4485; + uint16_t _4486 = (uint16_t)(197); + _curvea0[534] = _4486; + uint16_t _4487 = (uint16_t)(198); + _curvea0[535] = _4487; + uint16_t _4488 = (uint16_t)(198); + _curvea0[536] = _4488; + uint16_t _4489 = (uint16_t)(198); + _curvea0[537] = _4489; + uint16_t _4490 = (uint16_t)(198); + _curvea0[538] = _4490; + uint16_t _4491 = (uint16_t)(198); + _curvea0[539] = _4491; + uint16_t _4492 = (uint16_t)(199); + _curvea0[540] = _4492; + uint16_t _4493 = (uint16_t)(199); + _curvea0[541] = _4493; + uint16_t _4494 = (uint16_t)(199); + _curvea0[542] = _4494; + uint16_t _4495 = (uint16_t)(199); + _curvea0[543] = _4495; + uint16_t _4496 = (uint16_t)(199); + _curvea0[544] = _4496; + uint16_t _4497 = (uint16_t)(199); + _curvea0[545] = _4497; + uint16_t _4498 = (uint16_t)(200); + _curvea0[546] = _4498; + uint16_t _4499 = (uint16_t)(200); + _curvea0[547] = _4499; + uint16_t _4500 = (uint16_t)(200); + _curvea0[548] = _4500; + uint16_t _4501 = (uint16_t)(200); + _curvea0[549] = _4501; + uint16_t _4502 = (uint16_t)(200); + _curvea0[550] = _4502; + uint16_t _4503 = (uint16_t)(200); + _curvea0[551] = _4503; + uint16_t _4504 = (uint16_t)(201); + _curvea0[552] = _4504; + uint16_t _4505 = (uint16_t)(201); + _curvea0[553] = _4505; + uint16_t _4506 = (uint16_t)(201); + _curvea0[554] = _4506; + uint16_t _4507 = (uint16_t)(201); + _curvea0[555] = _4507; + uint16_t _4508 = (uint16_t)(201); + _curvea0[556] = _4508; + uint16_t _4509 = (uint16_t)(202); + _curvea0[557] = _4509; + uint16_t _4510 = (uint16_t)(202); + _curvea0[558] = _4510; + uint16_t _4511 = (uint16_t)(202); + _curvea0[559] = _4511; + uint16_t _4512 = (uint16_t)(202); + _curvea0[560] = _4512; + uint16_t _4513 = (uint16_t)(202); + _curvea0[561] = _4513; + uint16_t _4514 = (uint16_t)(202); + _curvea0[562] = _4514; + uint16_t _4515 = (uint16_t)(203); + _curvea0[563] = _4515; + uint16_t _4516 = (uint16_t)(203); + _curvea0[564] = _4516; + uint16_t _4517 = (uint16_t)(203); + _curvea0[565] = _4517; + uint16_t _4518 = (uint16_t)(203); + _curvea0[566] = _4518; + uint16_t _4519 = (uint16_t)(203); + _curvea0[567] = _4519; + uint16_t _4520 = (uint16_t)(203); + _curvea0[568] = _4520; + uint16_t _4521 = (uint16_t)(204); + _curvea0[569] = _4521; + uint16_t _4522 = (uint16_t)(204); + _curvea0[570] = _4522; + uint16_t _4523 = (uint16_t)(204); + _curvea0[571] = _4523; + uint16_t _4524 = (uint16_t)(204); + _curvea0[572] = _4524; + uint16_t _4525 = (uint16_t)(204); + _curvea0[573] = _4525; + uint16_t _4526 = (uint16_t)(204); + _curvea0[574] = _4526; + uint16_t _4527 = (uint16_t)(205); + _curvea0[575] = _4527; + uint16_t _4528 = (uint16_t)(205); + _curvea0[576] = _4528; + uint16_t _4529 = (uint16_t)(205); + _curvea0[577] = _4529; + uint16_t _4530 = (uint16_t)(205); + _curvea0[578] = _4530; + uint16_t _4531 = (uint16_t)(205); + _curvea0[579] = _4531; + uint16_t _4532 = (uint16_t)(205); + _curvea0[580] = _4532; + uint16_t _4533 = (uint16_t)(206); + _curvea0[581] = _4533; + uint16_t _4534 = (uint16_t)(206); + _curvea0[582] = _4534; + uint16_t _4535 = (uint16_t)(206); + _curvea0[583] = _4535; + uint16_t _4536 = (uint16_t)(206); + _curvea0[584] = _4536; + uint16_t _4537 = (uint16_t)(206); + _curvea0[585] = _4537; + uint16_t _4538 = (uint16_t)(206); + _curvea0[586] = _4538; + uint16_t _4539 = (uint16_t)(207); + _curvea0[587] = _4539; + uint16_t _4540 = (uint16_t)(207); + _curvea0[588] = _4540; + uint16_t _4541 = (uint16_t)(207); + _curvea0[589] = _4541; + uint16_t _4542 = (uint16_t)(207); + _curvea0[590] = _4542; + uint16_t _4543 = (uint16_t)(207); + _curvea0[591] = _4543; + uint16_t _4544 = (uint16_t)(207); + _curvea0[592] = _4544; + uint16_t _4545 = (uint16_t)(208); + _curvea0[593] = _4545; + uint16_t _4546 = (uint16_t)(208); + _curvea0[594] = _4546; + uint16_t _4547 = (uint16_t)(208); + _curvea0[595] = _4547; + uint16_t _4548 = (uint16_t)(208); + _curvea0[596] = _4548; + uint16_t _4549 = (uint16_t)(208); + _curvea0[597] = _4549; + uint16_t _4550 = (uint16_t)(208); + _curvea0[598] = _4550; + uint16_t _4551 = (uint16_t)(209); + _curvea0[599] = _4551; + uint16_t _4552 = (uint16_t)(209); + _curvea0[600] = _4552; + uint16_t _4553 = (uint16_t)(209); + _curvea0[601] = _4553; + uint16_t _4554 = (uint16_t)(209); + _curvea0[602] = _4554; + uint16_t _4555 = (uint16_t)(209); + _curvea0[603] = _4555; + uint16_t _4556 = (uint16_t)(209); + _curvea0[604] = _4556; + uint16_t _4557 = (uint16_t)(209); + _curvea0[605] = _4557; + uint16_t _4558 = (uint16_t)(210); + _curvea0[606] = _4558; + uint16_t _4559 = (uint16_t)(210); + _curvea0[607] = _4559; + uint16_t _4560 = (uint16_t)(210); + _curvea0[608] = _4560; + uint16_t _4561 = (uint16_t)(210); + _curvea0[609] = _4561; + uint16_t _4562 = (uint16_t)(210); + _curvea0[610] = _4562; + uint16_t _4563 = (uint16_t)(210); + _curvea0[611] = _4563; + uint16_t _4564 = (uint16_t)(211); + _curvea0[612] = _4564; + uint16_t _4565 = (uint16_t)(211); + _curvea0[613] = _4565; + uint16_t _4566 = (uint16_t)(211); + _curvea0[614] = _4566; + uint16_t _4567 = (uint16_t)(211); + _curvea0[615] = _4567; + uint16_t _4568 = (uint16_t)(211); + _curvea0[616] = _4568; + uint16_t _4569 = (uint16_t)(211); + _curvea0[617] = _4569; + uint16_t _4570 = (uint16_t)(211); + _curvea0[618] = _4570; + uint16_t _4571 = (uint16_t)(212); + _curvea0[619] = _4571; + uint16_t _4572 = (uint16_t)(212); + _curvea0[620] = _4572; + uint16_t _4573 = (uint16_t)(212); + _curvea0[621] = _4573; + uint16_t _4574 = (uint16_t)(212); + _curvea0[622] = _4574; + uint16_t _4575 = (uint16_t)(212); + _curvea0[623] = _4575; + uint16_t _4576 = (uint16_t)(212); + _curvea0[624] = _4576; + uint16_t _4577 = (uint16_t)(213); + _curvea0[625] = _4577; + uint16_t _4578 = (uint16_t)(213); + _curvea0[626] = _4578; + uint16_t _4579 = (uint16_t)(213); + _curvea0[627] = _4579; + uint16_t _4580 = (uint16_t)(213); + _curvea0[628] = _4580; + uint16_t _4581 = (uint16_t)(213); + _curvea0[629] = _4581; + uint16_t _4582 = (uint16_t)(213); + _curvea0[630] = _4582; + uint16_t _4583 = (uint16_t)(213); + _curvea0[631] = _4583; + uint16_t _4584 = (uint16_t)(214); + _curvea0[632] = _4584; + uint16_t _4585 = (uint16_t)(214); + _curvea0[633] = _4585; + uint16_t _4586 = (uint16_t)(214); + _curvea0[634] = _4586; + uint16_t _4587 = (uint16_t)(214); + _curvea0[635] = _4587; + uint16_t _4588 = (uint16_t)(214); + _curvea0[636] = _4588; + uint16_t _4589 = (uint16_t)(214); + _curvea0[637] = _4589; + uint16_t _4590 = (uint16_t)(214); + _curvea0[638] = _4590; + uint16_t _4591 = (uint16_t)(215); + _curvea0[639] = _4591; + uint16_t _4592 = (uint16_t)(215); + _curvea0[640] = _4592; + uint16_t _4593 = (uint16_t)(215); + _curvea0[641] = _4593; + uint16_t _4594 = (uint16_t)(215); + _curvea0[642] = _4594; + uint16_t _4595 = (uint16_t)(215); + _curvea0[643] = _4595; + uint16_t _4596 = (uint16_t)(215); + _curvea0[644] = _4596; + uint16_t _4597 = (uint16_t)(216); + _curvea0[645] = _4597; + uint16_t _4598 = (uint16_t)(216); + _curvea0[646] = _4598; + uint16_t _4599 = (uint16_t)(216); + _curvea0[647] = _4599; + uint16_t _4600 = (uint16_t)(216); + _curvea0[648] = _4600; + uint16_t _4601 = (uint16_t)(216); + _curvea0[649] = _4601; + uint16_t _4602 = (uint16_t)(216); + _curvea0[650] = _4602; + uint16_t _4603 = (uint16_t)(216); + _curvea0[651] = _4603; + uint16_t _4604 = (uint16_t)(217); + _curvea0[652] = _4604; + uint16_t _4605 = (uint16_t)(217); + _curvea0[653] = _4605; + uint16_t _4606 = (uint16_t)(217); + _curvea0[654] = _4606; + uint16_t _4607 = (uint16_t)(217); + _curvea0[655] = _4607; + uint16_t _4608 = (uint16_t)(217); + _curvea0[656] = _4608; + uint16_t _4609 = (uint16_t)(217); + _curvea0[657] = _4609; + uint16_t _4610 = (uint16_t)(217); + _curvea0[658] = _4610; + uint16_t _4611 = (uint16_t)(218); + _curvea0[659] = _4611; + uint16_t _4612 = (uint16_t)(218); + _curvea0[660] = _4612; + uint16_t _4613 = (uint16_t)(218); + _curvea0[661] = _4613; + uint16_t _4614 = (uint16_t)(218); + _curvea0[662] = _4614; + uint16_t _4615 = (uint16_t)(218); + _curvea0[663] = _4615; + uint16_t _4616 = (uint16_t)(218); + _curvea0[664] = _4616; + uint16_t _4617 = (uint16_t)(218); + _curvea0[665] = _4617; + uint16_t _4618 = (uint16_t)(219); + _curvea0[666] = _4618; + uint16_t _4619 = (uint16_t)(219); + _curvea0[667] = _4619; + uint16_t _4620 = (uint16_t)(219); + _curvea0[668] = _4620; + uint16_t _4621 = (uint16_t)(219); + _curvea0[669] = _4621; + uint16_t _4622 = (uint16_t)(219); + _curvea0[670] = _4622; + uint16_t _4623 = (uint16_t)(219); + _curvea0[671] = _4623; + uint16_t _4624 = (uint16_t)(219); + _curvea0[672] = _4624; + uint16_t _4625 = (uint16_t)(220); + _curvea0[673] = _4625; + uint16_t _4626 = (uint16_t)(220); + _curvea0[674] = _4626; + uint16_t _4627 = (uint16_t)(220); + _curvea0[675] = _4627; + uint16_t _4628 = (uint16_t)(220); + _curvea0[676] = _4628; + uint16_t _4629 = (uint16_t)(220); + _curvea0[677] = _4629; + uint16_t _4630 = (uint16_t)(220); + _curvea0[678] = _4630; + uint16_t _4631 = (uint16_t)(220); + _curvea0[679] = _4631; + uint16_t _4632 = (uint16_t)(220); + _curvea0[680] = _4632; + uint16_t _4633 = (uint16_t)(221); + _curvea0[681] = _4633; + uint16_t _4634 = (uint16_t)(221); + _curvea0[682] = _4634; + uint16_t _4635 = (uint16_t)(221); + _curvea0[683] = _4635; + uint16_t _4636 = (uint16_t)(221); + _curvea0[684] = _4636; + uint16_t _4637 = (uint16_t)(221); + _curvea0[685] = _4637; + uint16_t _4638 = (uint16_t)(221); + _curvea0[686] = _4638; + uint16_t _4639 = (uint16_t)(221); + _curvea0[687] = _4639; + uint16_t _4640 = (uint16_t)(222); + _curvea0[688] = _4640; + uint16_t _4641 = (uint16_t)(222); + _curvea0[689] = _4641; + uint16_t _4642 = (uint16_t)(222); + _curvea0[690] = _4642; + uint16_t _4643 = (uint16_t)(222); + _curvea0[691] = _4643; + uint16_t _4644 = (uint16_t)(222); + _curvea0[692] = _4644; + uint16_t _4645 = (uint16_t)(222); + _curvea0[693] = _4645; + uint16_t _4646 = (uint16_t)(222); + _curvea0[694] = _4646; + uint16_t _4647 = (uint16_t)(223); + _curvea0[695] = _4647; + uint16_t _4648 = (uint16_t)(223); + _curvea0[696] = _4648; + uint16_t _4649 = (uint16_t)(223); + _curvea0[697] = _4649; + uint16_t _4650 = (uint16_t)(223); + _curvea0[698] = _4650; + uint16_t _4651 = (uint16_t)(223); + _curvea0[699] = _4651; + uint16_t _4652 = (uint16_t)(223); + _curvea0[700] = _4652; + uint16_t _4653 = (uint16_t)(223); + _curvea0[701] = _4653; + uint16_t _4654 = (uint16_t)(223); + _curvea0[702] = _4654; + uint16_t _4655 = (uint16_t)(224); + _curvea0[703] = _4655; + uint16_t _4656 = (uint16_t)(224); + _curvea0[704] = _4656; + uint16_t _4657 = (uint16_t)(224); + _curvea0[705] = _4657; + uint16_t _4658 = (uint16_t)(224); + _curvea0[706] = _4658; + uint16_t _4659 = (uint16_t)(224); + _curvea0[707] = _4659; + uint16_t _4660 = (uint16_t)(224); + _curvea0[708] = _4660; + uint16_t _4661 = (uint16_t)(224); + _curvea0[709] = _4661; + uint16_t _4662 = (uint16_t)(224); + _curvea0[710] = _4662; + uint16_t _4663 = (uint16_t)(225); + _curvea0[711] = _4663; + uint16_t _4664 = (uint16_t)(225); + _curvea0[712] = _4664; + uint16_t _4665 = (uint16_t)(225); + _curvea0[713] = _4665; + uint16_t _4666 = (uint16_t)(225); + _curvea0[714] = _4666; + uint16_t _4667 = (uint16_t)(225); + _curvea0[715] = _4667; + uint16_t _4668 = (uint16_t)(225); + _curvea0[716] = _4668; + uint16_t _4669 = (uint16_t)(225); + _curvea0[717] = _4669; + uint16_t _4670 = (uint16_t)(226); + _curvea0[718] = _4670; + uint16_t _4671 = (uint16_t)(226); + _curvea0[719] = _4671; + uint16_t _4672 = (uint16_t)(226); + _curvea0[720] = _4672; + uint16_t _4673 = (uint16_t)(226); + _curvea0[721] = _4673; + uint16_t _4674 = (uint16_t)(226); + _curvea0[722] = _4674; + uint16_t _4675 = (uint16_t)(226); + _curvea0[723] = _4675; + uint16_t _4676 = (uint16_t)(226); + _curvea0[724] = _4676; + uint16_t _4677 = (uint16_t)(226); + _curvea0[725] = _4677; + uint16_t _4678 = (uint16_t)(227); + _curvea0[726] = _4678; + uint16_t _4679 = (uint16_t)(227); + _curvea0[727] = _4679; + uint16_t _4680 = (uint16_t)(227); + _curvea0[728] = _4680; + uint16_t _4681 = (uint16_t)(227); + _curvea0[729] = _4681; + uint16_t _4682 = (uint16_t)(227); + _curvea0[730] = _4682; + uint16_t _4683 = (uint16_t)(227); + _curvea0[731] = _4683; + uint16_t _4684 = (uint16_t)(227); + _curvea0[732] = _4684; + uint16_t _4685 = (uint16_t)(227); + _curvea0[733] = _4685; + uint16_t _4686 = (uint16_t)(228); + _curvea0[734] = _4686; + uint16_t _4687 = (uint16_t)(228); + _curvea0[735] = _4687; + uint16_t _4688 = (uint16_t)(228); + _curvea0[736] = _4688; + uint16_t _4689 = (uint16_t)(228); + _curvea0[737] = _4689; + uint16_t _4690 = (uint16_t)(228); + _curvea0[738] = _4690; + uint16_t _4691 = (uint16_t)(228); + _curvea0[739] = _4691; + uint16_t _4692 = (uint16_t)(228); + _curvea0[740] = _4692; + uint16_t _4693 = (uint16_t)(228); + _curvea0[741] = _4693; + uint16_t _4694 = (uint16_t)(228); + _curvea0[742] = _4694; + uint16_t _4695 = (uint16_t)(229); + _curvea0[743] = _4695; + uint16_t _4696 = (uint16_t)(229); + _curvea0[744] = _4696; + uint16_t _4697 = (uint16_t)(229); + _curvea0[745] = _4697; + uint16_t _4698 = (uint16_t)(229); + _curvea0[746] = _4698; + uint16_t _4699 = (uint16_t)(229); + _curvea0[747] = _4699; + uint16_t _4700 = (uint16_t)(229); + _curvea0[748] = _4700; + uint16_t _4701 = (uint16_t)(229); + _curvea0[749] = _4701; + uint16_t _4702 = (uint16_t)(229); + _curvea0[750] = _4702; + uint16_t _4703 = (uint16_t)(230); + _curvea0[751] = _4703; + uint16_t _4704 = (uint16_t)(230); + _curvea0[752] = _4704; + uint16_t _4705 = (uint16_t)(230); + _curvea0[753] = _4705; + uint16_t _4706 = (uint16_t)(230); + _curvea0[754] = _4706; + uint16_t _4707 = (uint16_t)(230); + _curvea0[755] = _4707; + uint16_t _4708 = (uint16_t)(230); + _curvea0[756] = _4708; + uint16_t _4709 = (uint16_t)(230); + _curvea0[757] = _4709; + uint16_t _4710 = (uint16_t)(230); + _curvea0[758] = _4710; + uint16_t _4711 = (uint16_t)(231); + _curvea0[759] = _4711; + uint16_t _4712 = (uint16_t)(231); + _curvea0[760] = _4712; + uint16_t _4713 = (uint16_t)(231); + _curvea0[761] = _4713; + uint16_t _4714 = (uint16_t)(231); + _curvea0[762] = _4714; + uint16_t _4715 = (uint16_t)(231); + _curvea0[763] = _4715; + uint16_t _4716 = (uint16_t)(231); + _curvea0[764] = _4716; + uint16_t _4717 = (uint16_t)(231); + _curvea0[765] = _4717; + uint16_t _4718 = (uint16_t)(231); + _curvea0[766] = _4718; + uint16_t _4719 = (uint16_t)(231); + _curvea0[767] = _4719; + uint16_t _4720 = (uint16_t)(232); + _curvea0[768] = _4720; + uint16_t _4721 = (uint16_t)(232); + _curvea0[769] = _4721; + uint16_t _4722 = (uint16_t)(232); + _curvea0[770] = _4722; + uint16_t _4723 = (uint16_t)(232); + _curvea0[771] = _4723; + uint16_t _4724 = (uint16_t)(232); + _curvea0[772] = _4724; + uint16_t _4725 = (uint16_t)(232); + _curvea0[773] = _4725; + uint16_t _4726 = (uint16_t)(232); + _curvea0[774] = _4726; + uint16_t _4727 = (uint16_t)(232); + _curvea0[775] = _4727; + uint16_t _4728 = (uint16_t)(233); + _curvea0[776] = _4728; + uint16_t _4729 = (uint16_t)(233); + _curvea0[777] = _4729; + uint16_t _4730 = (uint16_t)(233); + _curvea0[778] = _4730; + uint16_t _4731 = (uint16_t)(233); + _curvea0[779] = _4731; + uint16_t _4732 = (uint16_t)(233); + _curvea0[780] = _4732; + uint16_t _4733 = (uint16_t)(233); + _curvea0[781] = _4733; + uint16_t _4734 = (uint16_t)(233); + _curvea0[782] = _4734; + uint16_t _4735 = (uint16_t)(233); + _curvea0[783] = _4735; + uint16_t _4736 = (uint16_t)(233); + _curvea0[784] = _4736; + uint16_t _4737 = (uint16_t)(234); + _curvea0[785] = _4737; + uint16_t _4738 = (uint16_t)(234); + _curvea0[786] = _4738; + uint16_t _4739 = (uint16_t)(234); + _curvea0[787] = _4739; + uint16_t _4740 = (uint16_t)(234); + _curvea0[788] = _4740; + uint16_t _4741 = (uint16_t)(234); + _curvea0[789] = _4741; + uint16_t _4742 = (uint16_t)(234); + _curvea0[790] = _4742; + uint16_t _4743 = (uint16_t)(234); + _curvea0[791] = _4743; + uint16_t _4744 = (uint16_t)(234); + _curvea0[792] = _4744; + uint16_t _4745 = (uint16_t)(234); + _curvea0[793] = _4745; + uint16_t _4746 = (uint16_t)(235); + _curvea0[794] = _4746; + uint16_t _4747 = (uint16_t)(235); + _curvea0[795] = _4747; + uint16_t _4748 = (uint16_t)(235); + _curvea0[796] = _4748; + uint16_t _4749 = (uint16_t)(235); + _curvea0[797] = _4749; + uint16_t _4750 = (uint16_t)(235); + _curvea0[798] = _4750; + uint16_t _4751 = (uint16_t)(235); + _curvea0[799] = _4751; + uint16_t _4752 = (uint16_t)(235); + _curvea0[800] = _4752; + uint16_t _4753 = (uint16_t)(235); + _curvea0[801] = _4753; + uint16_t _4754 = (uint16_t)(235); + _curvea0[802] = _4754; + uint16_t _4755 = (uint16_t)(236); + _curvea0[803] = _4755; + uint16_t _4756 = (uint16_t)(236); + _curvea0[804] = _4756; + uint16_t _4757 = (uint16_t)(236); + _curvea0[805] = _4757; + uint16_t _4758 = (uint16_t)(236); + _curvea0[806] = _4758; + uint16_t _4759 = (uint16_t)(236); + _curvea0[807] = _4759; + uint16_t _4760 = (uint16_t)(236); + _curvea0[808] = _4760; + uint16_t _4761 = (uint16_t)(236); + _curvea0[809] = _4761; + uint16_t _4762 = (uint16_t)(236); + _curvea0[810] = _4762; + uint16_t _4763 = (uint16_t)(236); + _curvea0[811] = _4763; + uint16_t _4764 = (uint16_t)(237); + _curvea0[812] = _4764; + uint16_t _4765 = (uint16_t)(237); + _curvea0[813] = _4765; + uint16_t _4766 = (uint16_t)(237); + _curvea0[814] = _4766; + uint16_t _4767 = (uint16_t)(237); + _curvea0[815] = _4767; + uint16_t _4768 = (uint16_t)(237); + _curvea0[816] = _4768; + uint16_t _4769 = (uint16_t)(237); + _curvea0[817] = _4769; + uint16_t _4770 = (uint16_t)(237); + _curvea0[818] = _4770; + uint16_t _4771 = (uint16_t)(237); + _curvea0[819] = _4771; + uint16_t _4772 = (uint16_t)(237); + _curvea0[820] = _4772; + uint16_t _4773 = (uint16_t)(237); + _curvea0[821] = _4773; + uint16_t _4774 = (uint16_t)(238); + _curvea0[822] = _4774; + uint16_t _4775 = (uint16_t)(238); + _curvea0[823] = _4775; + uint16_t _4776 = (uint16_t)(238); + _curvea0[824] = _4776; + uint16_t _4777 = (uint16_t)(238); + _curvea0[825] = _4777; + uint16_t _4778 = (uint16_t)(238); + _curvea0[826] = _4778; + uint16_t _4779 = (uint16_t)(238); + _curvea0[827] = _4779; + uint16_t _4780 = (uint16_t)(238); + _curvea0[828] = _4780; + uint16_t _4781 = (uint16_t)(238); + _curvea0[829] = _4781; + uint16_t _4782 = (uint16_t)(238); + _curvea0[830] = _4782; + uint16_t _4783 = (uint16_t)(239); + _curvea0[831] = _4783; + uint16_t _4784 = (uint16_t)(239); + _curvea0[832] = _4784; + uint16_t _4785 = (uint16_t)(239); + _curvea0[833] = _4785; + uint16_t _4786 = (uint16_t)(239); + _curvea0[834] = _4786; + uint16_t _4787 = (uint16_t)(239); + _curvea0[835] = _4787; + uint16_t _4788 = (uint16_t)(239); + _curvea0[836] = _4788; + uint16_t _4789 = (uint16_t)(239); + _curvea0[837] = _4789; + uint16_t _4790 = (uint16_t)(239); + _curvea0[838] = _4790; + uint16_t _4791 = (uint16_t)(239); + _curvea0[839] = _4791; + uint16_t _4792 = (uint16_t)(239); + _curvea0[840] = _4792; + uint16_t _4793 = (uint16_t)(240); + _curvea0[841] = _4793; + uint16_t _4794 = (uint16_t)(240); + _curvea0[842] = _4794; + uint16_t _4795 = (uint16_t)(240); + _curvea0[843] = _4795; + uint16_t _4796 = (uint16_t)(240); + _curvea0[844] = _4796; + uint16_t _4797 = (uint16_t)(240); + _curvea0[845] = _4797; + uint16_t _4798 = (uint16_t)(240); + _curvea0[846] = _4798; + uint16_t _4799 = (uint16_t)(240); + _curvea0[847] = _4799; + uint16_t _4800 = (uint16_t)(240); + _curvea0[848] = _4800; + uint16_t _4801 = (uint16_t)(240); + _curvea0[849] = _4801; + uint16_t _4802 = (uint16_t)(240); + _curvea0[850] = _4802; + uint16_t _4803 = (uint16_t)(241); + _curvea0[851] = _4803; + uint16_t _4804 = (uint16_t)(241); + _curvea0[852] = _4804; + uint16_t _4805 = (uint16_t)(241); + _curvea0[853] = _4805; + uint16_t _4806 = (uint16_t)(241); + _curvea0[854] = _4806; + uint16_t _4807 = (uint16_t)(241); + _curvea0[855] = _4807; + uint16_t _4808 = (uint16_t)(241); + _curvea0[856] = _4808; + uint16_t _4809 = (uint16_t)(241); + _curvea0[857] = _4809; + uint16_t _4810 = (uint16_t)(241); + _curvea0[858] = _4810; + uint16_t _4811 = (uint16_t)(241); + _curvea0[859] = _4811; + uint16_t _4812 = (uint16_t)(241); + _curvea0[860] = _4812; + uint16_t _4813 = (uint16_t)(242); + _curvea0[861] = _4813; + uint16_t _4814 = (uint16_t)(242); + _curvea0[862] = _4814; + uint16_t _4815 = (uint16_t)(242); + _curvea0[863] = _4815; + uint16_t _4816 = (uint16_t)(242); + _curvea0[864] = _4816; + uint16_t _4817 = (uint16_t)(242); + _curvea0[865] = _4817; + uint16_t _4818 = (uint16_t)(242); + _curvea0[866] = _4818; + uint16_t _4819 = (uint16_t)(242); + _curvea0[867] = _4819; + uint16_t _4820 = (uint16_t)(242); + _curvea0[868] = _4820; + uint16_t _4821 = (uint16_t)(242); + _curvea0[869] = _4821; + uint16_t _4822 = (uint16_t)(242); + _curvea0[870] = _4822; + uint16_t _4823 = (uint16_t)(243); + _curvea0[871] = _4823; + uint16_t _4824 = (uint16_t)(243); + _curvea0[872] = _4824; + uint16_t _4825 = (uint16_t)(243); + _curvea0[873] = _4825; + uint16_t _4826 = (uint16_t)(243); + _curvea0[874] = _4826; + uint16_t _4827 = (uint16_t)(243); + _curvea0[875] = _4827; + uint16_t _4828 = (uint16_t)(243); + _curvea0[876] = _4828; + uint16_t _4829 = (uint16_t)(243); + _curvea0[877] = _4829; + uint16_t _4830 = (uint16_t)(243); + _curvea0[878] = _4830; + uint16_t _4831 = (uint16_t)(243); + _curvea0[879] = _4831; + uint16_t _4832 = (uint16_t)(243); + _curvea0[880] = _4832; + uint16_t _4833 = (uint16_t)(244); + _curvea0[881] = _4833; + uint16_t _4834 = (uint16_t)(244); + _curvea0[882] = _4834; + uint16_t _4835 = (uint16_t)(244); + _curvea0[883] = _4835; + uint16_t _4836 = (uint16_t)(244); + _curvea0[884] = _4836; + uint16_t _4837 = (uint16_t)(244); + _curvea0[885] = _4837; + uint16_t _4838 = (uint16_t)(244); + _curvea0[886] = _4838; + uint16_t _4839 = (uint16_t)(244); + _curvea0[887] = _4839; + uint16_t _4840 = (uint16_t)(244); + _curvea0[888] = _4840; + uint16_t _4841 = (uint16_t)(244); + _curvea0[889] = _4841; + uint16_t _4842 = (uint16_t)(244); + _curvea0[890] = _4842; + uint16_t _4843 = (uint16_t)(244); + _curvea0[891] = _4843; + uint16_t _4844 = (uint16_t)(245); + _curvea0[892] = _4844; + uint16_t _4845 = (uint16_t)(245); + _curvea0[893] = _4845; + uint16_t _4846 = (uint16_t)(245); + _curvea0[894] = _4846; + uint16_t _4847 = (uint16_t)(245); + _curvea0[895] = _4847; + uint16_t _4848 = (uint16_t)(245); + _curvea0[896] = _4848; + uint16_t _4849 = (uint16_t)(245); + _curvea0[897] = _4849; + uint16_t _4850 = (uint16_t)(245); + _curvea0[898] = _4850; + uint16_t _4851 = (uint16_t)(245); + _curvea0[899] = _4851; + uint16_t _4852 = (uint16_t)(245); + _curvea0[900] = _4852; + uint16_t _4853 = (uint16_t)(245); + _curvea0[901] = _4853; + uint16_t _4854 = (uint16_t)(245); + _curvea0[902] = _4854; + uint16_t _4855 = (uint16_t)(246); + _curvea0[903] = _4855; + uint16_t _4856 = (uint16_t)(246); + _curvea0[904] = _4856; + uint16_t _4857 = (uint16_t)(246); + _curvea0[905] = _4857; + uint16_t _4858 = (uint16_t)(246); + _curvea0[906] = _4858; + uint16_t _4859 = (uint16_t)(246); + _curvea0[907] = _4859; + uint16_t _4860 = (uint16_t)(246); + _curvea0[908] = _4860; + uint16_t _4861 = (uint16_t)(246); + _curvea0[909] = _4861; + uint16_t _4862 = (uint16_t)(246); + _curvea0[910] = _4862; + uint16_t _4863 = (uint16_t)(246); + _curvea0[911] = _4863; + uint16_t _4864 = (uint16_t)(246); + _curvea0[912] = _4864; + uint16_t _4865 = (uint16_t)(246); + _curvea0[913] = _4865; + uint16_t _4866 = (uint16_t)(247); + _curvea0[914] = _4866; + uint16_t _4867 = (uint16_t)(247); + _curvea0[915] = _4867; + uint16_t _4868 = (uint16_t)(247); + _curvea0[916] = _4868; + uint16_t _4869 = (uint16_t)(247); + _curvea0[917] = _4869; + uint16_t _4870 = (uint16_t)(247); + _curvea0[918] = _4870; + uint16_t _4871 = (uint16_t)(247); + _curvea0[919] = _4871; + uint16_t _4872 = (uint16_t)(247); + _curvea0[920] = _4872; + uint16_t _4873 = (uint16_t)(247); + _curvea0[921] = _4873; + uint16_t _4874 = (uint16_t)(247); + _curvea0[922] = _4874; + uint16_t _4875 = (uint16_t)(247); + _curvea0[923] = _4875; + uint16_t _4876 = (uint16_t)(247); + _curvea0[924] = _4876; + uint16_t _4877 = (uint16_t)(248); + _curvea0[925] = _4877; + uint16_t _4878 = (uint16_t)(248); + _curvea0[926] = _4878; + uint16_t _4879 = (uint16_t)(248); + _curvea0[927] = _4879; + uint16_t _4880 = (uint16_t)(248); + _curvea0[928] = _4880; + uint16_t _4881 = (uint16_t)(248); + _curvea0[929] = _4881; + uint16_t _4882 = (uint16_t)(248); + _curvea0[930] = _4882; + uint16_t _4883 = (uint16_t)(248); + _curvea0[931] = _4883; + uint16_t _4884 = (uint16_t)(248); + _curvea0[932] = _4884; + uint16_t _4885 = (uint16_t)(248); + _curvea0[933] = _4885; + uint16_t _4886 = (uint16_t)(248); + _curvea0[934] = _4886; + uint16_t _4887 = (uint16_t)(248); + _curvea0[935] = _4887; + uint16_t _4888 = (uint16_t)(249); + _curvea0[936] = _4888; + uint16_t _4889 = (uint16_t)(249); + _curvea0[937] = _4889; + uint16_t _4890 = (uint16_t)(249); + _curvea0[938] = _4890; + uint16_t _4891 = (uint16_t)(249); + _curvea0[939] = _4891; + uint16_t _4892 = (uint16_t)(249); + _curvea0[940] = _4892; + uint16_t _4893 = (uint16_t)(249); + _curvea0[941] = _4893; + uint16_t _4894 = (uint16_t)(249); + _curvea0[942] = _4894; + uint16_t _4895 = (uint16_t)(249); + _curvea0[943] = _4895; + uint16_t _4896 = (uint16_t)(249); + _curvea0[944] = _4896; + uint16_t _4897 = (uint16_t)(249); + _curvea0[945] = _4897; + uint16_t _4898 = (uint16_t)(249); + _curvea0[946] = _4898; + uint16_t _4899 = (uint16_t)(249); + _curvea0[947] = _4899; + uint16_t _4900 = (uint16_t)(250); + _curvea0[948] = _4900; + uint16_t _4901 = (uint16_t)(250); + _curvea0[949] = _4901; + uint16_t _4902 = (uint16_t)(250); + _curvea0[950] = _4902; + uint16_t _4903 = (uint16_t)(250); + _curvea0[951] = _4903; + uint16_t _4904 = (uint16_t)(250); + _curvea0[952] = _4904; + uint16_t _4905 = (uint16_t)(250); + _curvea0[953] = _4905; + uint16_t _4906 = (uint16_t)(250); + _curvea0[954] = _4906; + uint16_t _4907 = (uint16_t)(250); + _curvea0[955] = _4907; + uint16_t _4908 = (uint16_t)(250); + _curvea0[956] = _4908; + uint16_t _4909 = (uint16_t)(250); + _curvea0[957] = _4909; + uint16_t _4910 = (uint16_t)(250); + _curvea0[958] = _4910; + uint16_t _4911 = (uint16_t)(250); + _curvea0[959] = _4911; + uint16_t _4912 = (uint16_t)(251); + _curvea0[960] = _4912; + uint16_t _4913 = (uint16_t)(251); + _curvea0[961] = _4913; + uint16_t _4914 = (uint16_t)(251); + _curvea0[962] = _4914; + uint16_t _4915 = (uint16_t)(251); + _curvea0[963] = _4915; + uint16_t _4916 = (uint16_t)(251); + _curvea0[964] = _4916; + uint16_t _4917 = (uint16_t)(251); + _curvea0[965] = _4917; + uint16_t _4918 = (uint16_t)(251); + _curvea0[966] = _4918; + uint16_t _4919 = (uint16_t)(251); + _curvea0[967] = _4919; + uint16_t _4920 = (uint16_t)(251); + _curvea0[968] = _4920; + uint16_t _4921 = (uint16_t)(251); + _curvea0[969] = _4921; + uint16_t _4922 = (uint16_t)(251); + _curvea0[970] = _4922; + uint16_t _4923 = (uint16_t)(251); + _curvea0[971] = _4923; + uint16_t _4924 = (uint16_t)(252); + _curvea0[972] = _4924; + uint16_t _4925 = (uint16_t)(252); + _curvea0[973] = _4925; + uint16_t _4926 = (uint16_t)(252); + _curvea0[974] = _4926; + uint16_t _4927 = (uint16_t)(252); + _curvea0[975] = _4927; + uint16_t _4928 = (uint16_t)(252); + _curvea0[976] = _4928; + uint16_t _4929 = (uint16_t)(252); + _curvea0[977] = _4929; + uint16_t _4930 = (uint16_t)(252); + _curvea0[978] = _4930; + uint16_t _4931 = (uint16_t)(252); + _curvea0[979] = _4931; + uint16_t _4932 = (uint16_t)(252); + _curvea0[980] = _4932; + uint16_t _4933 = (uint16_t)(252); + _curvea0[981] = _4933; + uint16_t _4934 = (uint16_t)(252); + _curvea0[982] = _4934; + uint16_t _4935 = (uint16_t)(252); + _curvea0[983] = _4935; + uint16_t _4936 = (uint16_t)(252); + _curvea0[984] = _4936; + uint16_t _4937 = (uint16_t)(253); + _curvea0[985] = _4937; + uint16_t _4938 = (uint16_t)(253); + _curvea0[986] = _4938; + uint16_t _4939 = (uint16_t)(253); + _curvea0[987] = _4939; + uint16_t _4940 = (uint16_t)(253); + _curvea0[988] = _4940; + uint16_t _4941 = (uint16_t)(253); + _curvea0[989] = _4941; + uint16_t _4942 = (uint16_t)(253); + _curvea0[990] = _4942; + uint16_t _4943 = (uint16_t)(253); + _curvea0[991] = _4943; + uint16_t _4944 = (uint16_t)(253); + _curvea0[992] = _4944; + uint16_t _4945 = (uint16_t)(253); + _curvea0[993] = _4945; + uint16_t _4946 = (uint16_t)(253); + _curvea0[994] = _4946; + uint16_t _4947 = (uint16_t)(253); + _curvea0[995] = _4947; + uint16_t _4948 = (uint16_t)(253); + _curvea0[996] = _4948; + uint16_t _4949 = (uint16_t)(253); + _curvea0[997] = _4949; + uint16_t _4950 = (uint16_t)(254); + _curvea0[998] = _4950; + uint16_t _4951 = (uint16_t)(254); + _curvea0[999] = _4951; + uint16_t _4952 = (uint16_t)(254); + _curvea0[1000] = _4952; + uint16_t _4953 = (uint16_t)(254); + _curvea0[1001] = _4953; + uint16_t _4954 = (uint16_t)(254); + _curvea0[1002] = _4954; + uint16_t _4955 = (uint16_t)(254); + _curvea0[1003] = _4955; + uint16_t _4956 = (uint16_t)(254); + _curvea0[1004] = _4956; + uint16_t _4957 = (uint16_t)(254); + _curvea0[1005] = _4957; + uint16_t _4958 = (uint16_t)(254); + _curvea0[1006] = _4958; + uint16_t _4959 = (uint16_t)(254); + _curvea0[1007] = _4959; + uint16_t _4960 = (uint16_t)(254); + _curvea0[1008] = _4960; + uint16_t _4961 = (uint16_t)(254); + _curvea0[1009] = _4961; + uint16_t _4962 = (uint16_t)(254); + _curvea0[1010] = _4962; + uint16_t _4963 = (uint16_t)(255); + _curvea0[1011] = _4963; + uint16_t _4964 = (uint16_t)(255); + _curvea0[1012] = _4964; + uint16_t _4965 = (uint16_t)(255); + _curvea0[1013] = _4965; + uint16_t _4966 = (uint16_t)(255); + _curvea0[1014] = _4966; + uint16_t _4967 = (uint16_t)(255); + _curvea0[1015] = _4967; + uint16_t _4968 = (uint16_t)(255); + _curvea0[1016] = _4968; + uint16_t _4969 = (uint16_t)(255); + _curvea0[1017] = _4969; + uint16_t _4970 = (uint16_t)(255); + _curvea0[1018] = _4970; + uint16_t _4971 = (uint16_t)(255); + _curvea0[1019] = _4971; + uint16_t _4972 = (uint16_t)(255); + _curvea0[1020] = _4972; + uint16_t _4973 = (uint16_t)(255); + _curvea0[1021] = _4973; + uint16_t _4974 = (uint16_t)(255); + _curvea0[1022] = _4974; + uint16_t _4975 = (uint16_t)(255); + _curvea0[1023] = _4975; + + int16_t _4976 = (int16_t)(1023); + int16_t _4977 = min(_corrected_stencil_1, _4976); + int16_t _4978 = (int16_t)(0); + int16_t _4979 = max(_4977, _4978); + uint16_t _4980 = (uint16_t)(_4979); + int32_t _4981 = (int32_t)(_4980); + uint16_t _4982 = ((const uint16_t *)_curvea0)[_4981]; + return _4982; +} + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_1(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_2 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _4999 = (uint16_t)(0); + _curvea0[0] = _4999; + uint16_t _5000 = (uint16_t)(4); + _curvea0[1] = _5000; + uint16_t _5001 = (uint16_t)(7); + _curvea0[2] = _5001; + uint16_t _5002 = (uint16_t)(8); + _curvea0[3] = _5002; + uint16_t _5003 = (uint16_t)(10); + _curvea0[4] = _5003; + uint16_t _5004 = (uint16_t)(11); + _curvea0[5] = _5004; + uint16_t _5005 = (uint16_t)(12); + _curvea0[6] = _5005; + uint16_t _5006 = (uint16_t)(13); + _curvea0[7] = _5006; + uint16_t _5007 = (uint16_t)(14); + _curvea0[8] = _5007; + uint16_t _5008 = (uint16_t)(15); + _curvea0[9] = _5008; + uint16_t _5009 = (uint16_t)(16); + _curvea0[10] = _5009; + uint16_t _5010 = (uint16_t)(17); + _curvea0[11] = _5010; + uint16_t _5011 = (uint16_t)(18); + _curvea0[12] = _5011; + uint16_t _5012 = (uint16_t)(19); + _curvea0[13] = _5012; + uint16_t _5013 = (uint16_t)(20); + _curvea0[14] = _5013; + uint16_t _5014 = (uint16_t)(21); + _curvea0[15] = _5014; + uint16_t _5015 = (uint16_t)(22); + _curvea0[16] = _5015; + uint16_t _5016 = (uint16_t)(22); + _curvea0[17] = _5016; + uint16_t _5017 = (uint16_t)(23); + _curvea0[18] = _5017; + uint16_t _5018 = (uint16_t)(24); + _curvea0[19] = _5018; + uint16_t _5019 = (uint16_t)(25); + _curvea0[20] = _5019; + uint16_t _5020 = (uint16_t)(25); + _curvea0[21] = _5020; + uint16_t _5021 = (uint16_t)(26); + _curvea0[22] = _5021; + uint16_t _5022 = (uint16_t)(27); + _curvea0[23] = _5022; + uint16_t _5023 = (uint16_t)(27); + _curvea0[24] = _5023; + uint16_t _5024 = (uint16_t)(28); + _curvea0[25] = _5024; + uint16_t _5025 = (uint16_t)(29); + _curvea0[26] = _5025; + uint16_t _5026 = (uint16_t)(29); + _curvea0[27] = _5026; + uint16_t _5027 = (uint16_t)(30); + _curvea0[28] = _5027; + uint16_t _5028 = (uint16_t)(31); + _curvea0[29] = _5028; + uint16_t _5029 = (uint16_t)(31); + _curvea0[30] = _5029; + uint16_t _5030 = (uint16_t)(32); + _curvea0[31] = _5030; + uint16_t _5031 = (uint16_t)(33); + _curvea0[32] = _5031; + uint16_t _5032 = (uint16_t)(33); + _curvea0[33] = _5032; + uint16_t _5033 = (uint16_t)(34); + _curvea0[34] = _5033; + uint16_t _5034 = (uint16_t)(34); + _curvea0[35] = _5034; + uint16_t _5035 = (uint16_t)(35); + _curvea0[36] = _5035; + uint16_t _5036 = (uint16_t)(36); + _curvea0[37] = _5036; + uint16_t _5037 = (uint16_t)(36); + _curvea0[38] = _5037; + uint16_t _5038 = (uint16_t)(37); + _curvea0[39] = _5038; + uint16_t _5039 = (uint16_t)(37); + _curvea0[40] = _5039; + uint16_t _5040 = (uint16_t)(38); + _curvea0[41] = _5040; + uint16_t _5041 = (uint16_t)(39); + _curvea0[42] = _5041; + uint16_t _5042 = (uint16_t)(39); + _curvea0[43] = _5042; + uint16_t _5043 = (uint16_t)(40); + _curvea0[44] = _5043; + uint16_t _5044 = (uint16_t)(40); + _curvea0[45] = _5044; + uint16_t _5045 = (uint16_t)(41); + _curvea0[46] = _5045; + uint16_t _5046 = (uint16_t)(41); + _curvea0[47] = _5046; + uint16_t _5047 = (uint16_t)(42); + _curvea0[48] = _5047; + uint16_t _5048 = (uint16_t)(42); + _curvea0[49] = _5048; + uint16_t _5049 = (uint16_t)(43); + _curvea0[50] = _5049; + uint16_t _5050 = (uint16_t)(44); + _curvea0[51] = _5050; + uint16_t _5051 = (uint16_t)(44); + _curvea0[52] = _5051; + uint16_t _5052 = (uint16_t)(45); + _curvea0[53] = _5052; + uint16_t _5053 = (uint16_t)(45); + _curvea0[54] = _5053; + uint16_t _5054 = (uint16_t)(46); + _curvea0[55] = _5054; + uint16_t _5055 = (uint16_t)(46); + _curvea0[56] = _5055; + uint16_t _5056 = (uint16_t)(47); + _curvea0[57] = _5056; + uint16_t _5057 = (uint16_t)(47); + _curvea0[58] = _5057; + uint16_t _5058 = (uint16_t)(48); + _curvea0[59] = _5058; + uint16_t _5059 = (uint16_t)(48); + _curvea0[60] = _5059; + uint16_t _5060 = (uint16_t)(49); + _curvea0[61] = _5060; + uint16_t _5061 = (uint16_t)(49); + _curvea0[62] = _5061; + uint16_t _5062 = (uint16_t)(50); + _curvea0[63] = _5062; + uint16_t _5063 = (uint16_t)(50); + _curvea0[64] = _5063; + uint16_t _5064 = (uint16_t)(51); + _curvea0[65] = _5064; + uint16_t _5065 = (uint16_t)(51); + _curvea0[66] = _5065; + uint16_t _5066 = (uint16_t)(52); + _curvea0[67] = _5066; + uint16_t _5067 = (uint16_t)(52); + _curvea0[68] = _5067; + uint16_t _5068 = (uint16_t)(53); + _curvea0[69] = _5068; + uint16_t _5069 = (uint16_t)(53); + _curvea0[70] = _5069; + uint16_t _5070 = (uint16_t)(54); + _curvea0[71] = _5070; + uint16_t _5071 = (uint16_t)(54); + _curvea0[72] = _5071; + uint16_t _5072 = (uint16_t)(55); + _curvea0[73] = _5072; + uint16_t _5073 = (uint16_t)(55); + _curvea0[74] = _5073; + uint16_t _5074 = (uint16_t)(56); + _curvea0[75] = _5074; + uint16_t _5075 = (uint16_t)(56); + _curvea0[76] = _5075; + uint16_t _5076 = (uint16_t)(57); + _curvea0[77] = _5076; + uint16_t _5077 = (uint16_t)(57); + _curvea0[78] = _5077; + uint16_t _5078 = (uint16_t)(58); + _curvea0[79] = _5078; + uint16_t _5079 = (uint16_t)(58); + _curvea0[80] = _5079; + uint16_t _5080 = (uint16_t)(58); + _curvea0[81] = _5080; + uint16_t _5081 = (uint16_t)(59); + _curvea0[82] = _5081; + uint16_t _5082 = (uint16_t)(59); + _curvea0[83] = _5082; + uint16_t _5083 = (uint16_t)(60); + _curvea0[84] = _5083; + uint16_t _5084 = (uint16_t)(60); + _curvea0[85] = _5084; + uint16_t _5085 = (uint16_t)(61); + _curvea0[86] = _5085; + uint16_t _5086 = (uint16_t)(61); + _curvea0[87] = _5086; + uint16_t _5087 = (uint16_t)(62); + _curvea0[88] = _5087; + uint16_t _5088 = (uint16_t)(62); + _curvea0[89] = _5088; + uint16_t _5089 = (uint16_t)(63); + _curvea0[90] = _5089; + uint16_t _5090 = (uint16_t)(63); + _curvea0[91] = _5090; + uint16_t _5091 = (uint16_t)(64); + _curvea0[92] = _5091; + uint16_t _5092 = (uint16_t)(64); + _curvea0[93] = _5092; + uint16_t _5093 = (uint16_t)(64); + _curvea0[94] = _5093; + uint16_t _5094 = (uint16_t)(65); + _curvea0[95] = _5094; + uint16_t _5095 = (uint16_t)(65); + _curvea0[96] = _5095; + uint16_t _5096 = (uint16_t)(66); + _curvea0[97] = _5096; + uint16_t _5097 = (uint16_t)(66); + _curvea0[98] = _5097; + uint16_t _5098 = (uint16_t)(67); + _curvea0[99] = _5098; + uint16_t _5099 = (uint16_t)(67); + _curvea0[100] = _5099; + uint16_t _5100 = (uint16_t)(68); + _curvea0[101] = _5100; + uint16_t _5101 = (uint16_t)(68); + _curvea0[102] = _5101; + uint16_t _5102 = (uint16_t)(68); + _curvea0[103] = _5102; + uint16_t _5103 = (uint16_t)(69); + _curvea0[104] = _5103; + uint16_t _5104 = (uint16_t)(69); + _curvea0[105] = _5104; + uint16_t _5105 = (uint16_t)(70); + _curvea0[106] = _5105; + uint16_t _5106 = (uint16_t)(70); + _curvea0[107] = _5106; + uint16_t _5107 = (uint16_t)(71); + _curvea0[108] = _5107; + uint16_t _5108 = (uint16_t)(71); + _curvea0[109] = _5108; + uint16_t _5109 = (uint16_t)(71); + _curvea0[110] = _5109; + uint16_t _5110 = (uint16_t)(72); + _curvea0[111] = _5110; + uint16_t _5111 = (uint16_t)(72); + _curvea0[112] = _5111; + uint16_t _5112 = (uint16_t)(73); + _curvea0[113] = _5112; + uint16_t _5113 = (uint16_t)(73); + _curvea0[114] = _5113; + uint16_t _5114 = (uint16_t)(74); + _curvea0[115] = _5114; + uint16_t _5115 = (uint16_t)(74); + _curvea0[116] = _5115; + uint16_t _5116 = (uint16_t)(74); + _curvea0[117] = _5116; + uint16_t _5117 = (uint16_t)(75); + _curvea0[118] = _5117; + uint16_t _5118 = (uint16_t)(75); + _curvea0[119] = _5118; + uint16_t _5119 = (uint16_t)(76); + _curvea0[120] = _5119; + uint16_t _5120 = (uint16_t)(76); + _curvea0[121] = _5120; + uint16_t _5121 = (uint16_t)(77); + _curvea0[122] = _5121; + uint16_t _5122 = (uint16_t)(77); + _curvea0[123] = _5122; + uint16_t _5123 = (uint16_t)(77); + _curvea0[124] = _5123; + uint16_t _5124 = (uint16_t)(78); + _curvea0[125] = _5124; + uint16_t _5125 = (uint16_t)(78); + _curvea0[126] = _5125; + uint16_t _5126 = (uint16_t)(79); + _curvea0[127] = _5126; + uint16_t _5127 = (uint16_t)(79); + _curvea0[128] = _5127; + uint16_t _5128 = (uint16_t)(79); + _curvea0[129] = _5128; + uint16_t _5129 = (uint16_t)(80); + _curvea0[130] = _5129; + uint16_t _5130 = (uint16_t)(80); + _curvea0[131] = _5130; + uint16_t _5131 = (uint16_t)(81); + _curvea0[132] = _5131; + uint16_t _5132 = (uint16_t)(81); + _curvea0[133] = _5132; + uint16_t _5133 = (uint16_t)(82); + _curvea0[134] = _5133; + uint16_t _5134 = (uint16_t)(82); + _curvea0[135] = _5134; + uint16_t _5135 = (uint16_t)(82); + _curvea0[136] = _5135; + uint16_t _5136 = (uint16_t)(83); + _curvea0[137] = _5136; + uint16_t _5137 = (uint16_t)(83); + _curvea0[138] = _5137; + uint16_t _5138 = (uint16_t)(84); + _curvea0[139] = _5138; + uint16_t _5139 = (uint16_t)(84); + _curvea0[140] = _5139; + uint16_t _5140 = (uint16_t)(84); + _curvea0[141] = _5140; + uint16_t _5141 = (uint16_t)(85); + _curvea0[142] = _5141; + uint16_t _5142 = (uint16_t)(85); + _curvea0[143] = _5142; + uint16_t _5143 = (uint16_t)(86); + _curvea0[144] = _5143; + uint16_t _5144 = (uint16_t)(86); + _curvea0[145] = _5144; + uint16_t _5145 = (uint16_t)(86); + _curvea0[146] = _5145; + uint16_t _5146 = (uint16_t)(87); + _curvea0[147] = _5146; + uint16_t _5147 = (uint16_t)(87); + _curvea0[148] = _5147; + uint16_t _5148 = (uint16_t)(88); + _curvea0[149] = _5148; + uint16_t _5149 = (uint16_t)(88); + _curvea0[150] = _5149; + uint16_t _5150 = (uint16_t)(88); + _curvea0[151] = _5150; + uint16_t _5151 = (uint16_t)(89); + _curvea0[152] = _5151; + uint16_t _5152 = (uint16_t)(89); + _curvea0[153] = _5152; + uint16_t _5153 = (uint16_t)(90); + _curvea0[154] = _5153; + uint16_t _5154 = (uint16_t)(90); + _curvea0[155] = _5154; + uint16_t _5155 = (uint16_t)(90); + _curvea0[156] = _5155; + uint16_t _5156 = (uint16_t)(91); + _curvea0[157] = _5156; + uint16_t _5157 = (uint16_t)(91); + _curvea0[158] = _5157; + uint16_t _5158 = (uint16_t)(92); + _curvea0[159] = _5158; + uint16_t _5159 = (uint16_t)(92); + _curvea0[160] = _5159; + uint16_t _5160 = (uint16_t)(92); + _curvea0[161] = _5160; + uint16_t _5161 = (uint16_t)(93); + _curvea0[162] = _5161; + uint16_t _5162 = (uint16_t)(93); + _curvea0[163] = _5162; + uint16_t _5163 = (uint16_t)(93); + _curvea0[164] = _5163; + uint16_t _5164 = (uint16_t)(94); + _curvea0[165] = _5164; + uint16_t _5165 = (uint16_t)(94); + _curvea0[166] = _5165; + uint16_t _5166 = (uint16_t)(95); + _curvea0[167] = _5166; + uint16_t _5167 = (uint16_t)(95); + _curvea0[168] = _5167; + uint16_t _5168 = (uint16_t)(95); + _curvea0[169] = _5168; + uint16_t _5169 = (uint16_t)(96); + _curvea0[170] = _5169; + uint16_t _5170 = (uint16_t)(96); + _curvea0[171] = _5170; + uint16_t _5171 = (uint16_t)(97); + _curvea0[172] = _5171; + uint16_t _5172 = (uint16_t)(97); + _curvea0[173] = _5172; + uint16_t _5173 = (uint16_t)(97); + _curvea0[174] = _5173; + uint16_t _5174 = (uint16_t)(98); + _curvea0[175] = _5174; + uint16_t _5175 = (uint16_t)(98); + _curvea0[176] = _5175; + uint16_t _5176 = (uint16_t)(99); + _curvea0[177] = _5176; + uint16_t _5177 = (uint16_t)(99); + _curvea0[178] = _5177; + uint16_t _5178 = (uint16_t)(99); + _curvea0[179] = _5178; + uint16_t _5179 = (uint16_t)(100); + _curvea0[180] = _5179; + uint16_t _5180 = (uint16_t)(100); + _curvea0[181] = _5180; + uint16_t _5181 = (uint16_t)(100); + _curvea0[182] = _5181; + uint16_t _5182 = (uint16_t)(101); + _curvea0[183] = _5182; + uint16_t _5183 = (uint16_t)(101); + _curvea0[184] = _5183; + uint16_t _5184 = (uint16_t)(102); + _curvea0[185] = _5184; + uint16_t _5185 = (uint16_t)(102); + _curvea0[186] = _5185; + uint16_t _5186 = (uint16_t)(102); + _curvea0[187] = _5186; + uint16_t _5187 = (uint16_t)(103); + _curvea0[188] = _5187; + uint16_t _5188 = (uint16_t)(103); + _curvea0[189] = _5188; + uint16_t _5189 = (uint16_t)(103); + _curvea0[190] = _5189; + uint16_t _5190 = (uint16_t)(104); + _curvea0[191] = _5190; + uint16_t _5191 = (uint16_t)(104); + _curvea0[192] = _5191; + uint16_t _5192 = (uint16_t)(105); + _curvea0[193] = _5192; + uint16_t _5193 = (uint16_t)(105); + _curvea0[194] = _5193; + uint16_t _5194 = (uint16_t)(105); + _curvea0[195] = _5194; + uint16_t _5195 = (uint16_t)(106); + _curvea0[196] = _5195; + uint16_t _5196 = (uint16_t)(106); + _curvea0[197] = _5196; + uint16_t _5197 = (uint16_t)(106); + _curvea0[198] = _5197; + uint16_t _5198 = (uint16_t)(107); + _curvea0[199] = _5198; + uint16_t _5199 = (uint16_t)(107); + _curvea0[200] = _5199; + uint16_t _5200 = (uint16_t)(108); + _curvea0[201] = _5200; + uint16_t _5201 = (uint16_t)(108); + _curvea0[202] = _5201; + uint16_t _5202 = (uint16_t)(108); + _curvea0[203] = _5202; + uint16_t _5203 = (uint16_t)(109); + _curvea0[204] = _5203; + uint16_t _5204 = (uint16_t)(109); + _curvea0[205] = _5204; + uint16_t _5205 = (uint16_t)(109); + _curvea0[206] = _5205; + uint16_t _5206 = (uint16_t)(110); + _curvea0[207] = _5206; + uint16_t _5207 = (uint16_t)(110); + _curvea0[208] = _5207; + uint16_t _5208 = (uint16_t)(111); + _curvea0[209] = _5208; + uint16_t _5209 = (uint16_t)(111); + _curvea0[210] = _5209; + uint16_t _5210 = (uint16_t)(111); + _curvea0[211] = _5210; + uint16_t _5211 = (uint16_t)(112); + _curvea0[212] = _5211; + uint16_t _5212 = (uint16_t)(112); + _curvea0[213] = _5212; + uint16_t _5213 = (uint16_t)(112); + _curvea0[214] = _5213; + uint16_t _5214 = (uint16_t)(113); + _curvea0[215] = _5214; + uint16_t _5215 = (uint16_t)(113); + _curvea0[216] = _5215; + uint16_t _5216 = (uint16_t)(113); + _curvea0[217] = _5216; + uint16_t _5217 = (uint16_t)(114); + _curvea0[218] = _5217; + uint16_t _5218 = (uint16_t)(114); + _curvea0[219] = _5218; + uint16_t _5219 = (uint16_t)(115); + _curvea0[220] = _5219; + uint16_t _5220 = (uint16_t)(115); + _curvea0[221] = _5220; + uint16_t _5221 = (uint16_t)(115); + _curvea0[222] = _5221; + uint16_t _5222 = (uint16_t)(116); + _curvea0[223] = _5222; + uint16_t _5223 = (uint16_t)(116); + _curvea0[224] = _5223; + uint16_t _5224 = (uint16_t)(116); + _curvea0[225] = _5224; + uint16_t _5225 = (uint16_t)(117); + _curvea0[226] = _5225; + uint16_t _5226 = (uint16_t)(117); + _curvea0[227] = _5226; + uint16_t _5227 = (uint16_t)(117); + _curvea0[228] = _5227; + uint16_t _5228 = (uint16_t)(118); + _curvea0[229] = _5228; + uint16_t _5229 = (uint16_t)(118); + _curvea0[230] = _5229; + uint16_t _5230 = (uint16_t)(119); + _curvea0[231] = _5230; + uint16_t _5231 = (uint16_t)(119); + _curvea0[232] = _5231; + uint16_t _5232 = (uint16_t)(119); + _curvea0[233] = _5232; + uint16_t _5233 = (uint16_t)(120); + _curvea0[234] = _5233; + uint16_t _5234 = (uint16_t)(120); + _curvea0[235] = _5234; + uint16_t _5235 = (uint16_t)(120); + _curvea0[236] = _5235; + uint16_t _5236 = (uint16_t)(121); + _curvea0[237] = _5236; + uint16_t _5237 = (uint16_t)(121); + _curvea0[238] = _5237; + uint16_t _5238 = (uint16_t)(121); + _curvea0[239] = _5238; + uint16_t _5239 = (uint16_t)(122); + _curvea0[240] = _5239; + uint16_t _5240 = (uint16_t)(122); + _curvea0[241] = _5240; + uint16_t _5241 = (uint16_t)(123); + _curvea0[242] = _5241; + uint16_t _5242 = (uint16_t)(123); + _curvea0[243] = _5242; + uint16_t _5243 = (uint16_t)(123); + _curvea0[244] = _5243; + uint16_t _5244 = (uint16_t)(124); + _curvea0[245] = _5244; + uint16_t _5245 = (uint16_t)(124); + _curvea0[246] = _5245; + uint16_t _5246 = (uint16_t)(124); + _curvea0[247] = _5246; + uint16_t _5247 = (uint16_t)(125); + _curvea0[248] = _5247; + uint16_t _5248 = (uint16_t)(125); + _curvea0[249] = _5248; + uint16_t _5249 = (uint16_t)(125); + _curvea0[250] = _5249; + uint16_t _5250 = (uint16_t)(126); + _curvea0[251] = _5250; + uint16_t _5251 = (uint16_t)(126); + _curvea0[252] = _5251; + uint16_t _5252 = (uint16_t)(126); + _curvea0[253] = _5252; + uint16_t _5253 = (uint16_t)(127); + _curvea0[254] = _5253; + uint16_t _5254 = (uint16_t)(127); + _curvea0[255] = _5254; + uint16_t _5255 = (uint16_t)(128); + _curvea0[256] = _5255; + uint16_t _5256 = (uint16_t)(128); + _curvea0[257] = _5256; + uint16_t _5257 = (uint16_t)(128); + _curvea0[258] = _5257; + uint16_t _5258 = (uint16_t)(129); + _curvea0[259] = _5258; + uint16_t _5259 = (uint16_t)(129); + _curvea0[260] = _5259; + uint16_t _5260 = (uint16_t)(129); + _curvea0[261] = _5260; + uint16_t _5261 = (uint16_t)(130); + _curvea0[262] = _5261; + uint16_t _5262 = (uint16_t)(130); + _curvea0[263] = _5262; + uint16_t _5263 = (uint16_t)(130); + _curvea0[264] = _5263; + uint16_t _5264 = (uint16_t)(131); + _curvea0[265] = _5264; + uint16_t _5265 = (uint16_t)(131); + _curvea0[266] = _5265; + uint16_t _5266 = (uint16_t)(131); + _curvea0[267] = _5266; + uint16_t _5267 = (uint16_t)(132); + _curvea0[268] = _5267; + uint16_t _5268 = (uint16_t)(132); + _curvea0[269] = _5268; + uint16_t _5269 = (uint16_t)(132); + _curvea0[270] = _5269; + uint16_t _5270 = (uint16_t)(133); + _curvea0[271] = _5270; + uint16_t _5271 = (uint16_t)(133); + _curvea0[272] = _5271; + uint16_t _5272 = (uint16_t)(133); + _curvea0[273] = _5272; + uint16_t _5273 = (uint16_t)(134); + _curvea0[274] = _5273; + uint16_t _5274 = (uint16_t)(134); + _curvea0[275] = _5274; + uint16_t _5275 = (uint16_t)(134); + _curvea0[276] = _5275; + uint16_t _5276 = (uint16_t)(135); + _curvea0[277] = _5276; + uint16_t _5277 = (uint16_t)(135); + _curvea0[278] = _5277; + uint16_t _5278 = (uint16_t)(135); + _curvea0[279] = _5278; + uint16_t _5279 = (uint16_t)(136); + _curvea0[280] = _5279; + uint16_t _5280 = (uint16_t)(136); + _curvea0[281] = _5280; + uint16_t _5281 = (uint16_t)(136); + _curvea0[282] = _5281; + uint16_t _5282 = (uint16_t)(137); + _curvea0[283] = _5282; + uint16_t _5283 = (uint16_t)(137); + _curvea0[284] = _5283; + uint16_t _5284 = (uint16_t)(137); + _curvea0[285] = _5284; + uint16_t _5285 = (uint16_t)(138); + _curvea0[286] = _5285; + uint16_t _5286 = (uint16_t)(138); + _curvea0[287] = _5286; + uint16_t _5287 = (uint16_t)(138); + _curvea0[288] = _5287; + uint16_t _5288 = (uint16_t)(139); + _curvea0[289] = _5288; + uint16_t _5289 = (uint16_t)(139); + _curvea0[290] = _5289; + uint16_t _5290 = (uint16_t)(139); + _curvea0[291] = _5290; + uint16_t _5291 = (uint16_t)(140); + _curvea0[292] = _5291; + uint16_t _5292 = (uint16_t)(140); + _curvea0[293] = _5292; + uint16_t _5293 = (uint16_t)(140); + _curvea0[294] = _5293; + uint16_t _5294 = (uint16_t)(141); + _curvea0[295] = _5294; + uint16_t _5295 = (uint16_t)(141); + _curvea0[296] = _5295; + uint16_t _5296 = (uint16_t)(141); + _curvea0[297] = _5296; + uint16_t _5297 = (uint16_t)(141); + _curvea0[298] = _5297; + uint16_t _5298 = (uint16_t)(142); + _curvea0[299] = _5298; + uint16_t _5299 = (uint16_t)(142); + _curvea0[300] = _5299; + uint16_t _5300 = (uint16_t)(142); + _curvea0[301] = _5300; + uint16_t _5301 = (uint16_t)(143); + _curvea0[302] = _5301; + uint16_t _5302 = (uint16_t)(143); + _curvea0[303] = _5302; + uint16_t _5303 = (uint16_t)(143); + _curvea0[304] = _5303; + uint16_t _5304 = (uint16_t)(144); + _curvea0[305] = _5304; + uint16_t _5305 = (uint16_t)(144); + _curvea0[306] = _5305; + uint16_t _5306 = (uint16_t)(144); + _curvea0[307] = _5306; + uint16_t _5307 = (uint16_t)(145); + _curvea0[308] = _5307; + uint16_t _5308 = (uint16_t)(145); + _curvea0[309] = _5308; + uint16_t _5309 = (uint16_t)(145); + _curvea0[310] = _5309; + uint16_t _5310 = (uint16_t)(145); + _curvea0[311] = _5310; + uint16_t _5311 = (uint16_t)(146); + _curvea0[312] = _5311; + uint16_t _5312 = (uint16_t)(146); + _curvea0[313] = _5312; + uint16_t _5313 = (uint16_t)(146); + _curvea0[314] = _5313; + uint16_t _5314 = (uint16_t)(147); + _curvea0[315] = _5314; + uint16_t _5315 = (uint16_t)(147); + _curvea0[316] = _5315; + uint16_t _5316 = (uint16_t)(147); + _curvea0[317] = _5316; + uint16_t _5317 = (uint16_t)(148); + _curvea0[318] = _5317; + uint16_t _5318 = (uint16_t)(148); + _curvea0[319] = _5318; + uint16_t _5319 = (uint16_t)(148); + _curvea0[320] = _5319; + uint16_t _5320 = (uint16_t)(148); + _curvea0[321] = _5320; + uint16_t _5321 = (uint16_t)(149); + _curvea0[322] = _5321; + uint16_t _5322 = (uint16_t)(149); + _curvea0[323] = _5322; + uint16_t _5323 = (uint16_t)(149); + _curvea0[324] = _5323; + uint16_t _5324 = (uint16_t)(150); + _curvea0[325] = _5324; + uint16_t _5325 = (uint16_t)(150); + _curvea0[326] = _5325; + uint16_t _5326 = (uint16_t)(150); + _curvea0[327] = _5326; + uint16_t _5327 = (uint16_t)(150); + _curvea0[328] = _5327; + uint16_t _5328 = (uint16_t)(151); + _curvea0[329] = _5328; + uint16_t _5329 = (uint16_t)(151); + _curvea0[330] = _5329; + uint16_t _5330 = (uint16_t)(151); + _curvea0[331] = _5330; + uint16_t _5331 = (uint16_t)(152); + _curvea0[332] = _5331; + uint16_t _5332 = (uint16_t)(152); + _curvea0[333] = _5332; + uint16_t _5333 = (uint16_t)(152); + _curvea0[334] = _5333; + uint16_t _5334 = (uint16_t)(152); + _curvea0[335] = _5334; + uint16_t _5335 = (uint16_t)(153); + _curvea0[336] = _5335; + uint16_t _5336 = (uint16_t)(153); + _curvea0[337] = _5336; + uint16_t _5337 = (uint16_t)(153); + _curvea0[338] = _5337; + uint16_t _5338 = (uint16_t)(154); + _curvea0[339] = _5338; + uint16_t _5339 = (uint16_t)(154); + _curvea0[340] = _5339; + uint16_t _5340 = (uint16_t)(154); + _curvea0[341] = _5340; + uint16_t _5341 = (uint16_t)(154); + _curvea0[342] = _5341; + uint16_t _5342 = (uint16_t)(155); + _curvea0[343] = _5342; + uint16_t _5343 = (uint16_t)(155); + _curvea0[344] = _5343; + uint16_t _5344 = (uint16_t)(155); + _curvea0[345] = _5344; + uint16_t _5345 = (uint16_t)(156); + _curvea0[346] = _5345; + uint16_t _5346 = (uint16_t)(156); + _curvea0[347] = _5346; + uint16_t _5347 = (uint16_t)(156); + _curvea0[348] = _5347; + uint16_t _5348 = (uint16_t)(156); + _curvea0[349] = _5348; + uint16_t _5349 = (uint16_t)(157); + _curvea0[350] = _5349; + uint16_t _5350 = (uint16_t)(157); + _curvea0[351] = _5350; + uint16_t _5351 = (uint16_t)(157); + _curvea0[352] = _5351; + uint16_t _5352 = (uint16_t)(157); + _curvea0[353] = _5352; + uint16_t _5353 = (uint16_t)(158); + _curvea0[354] = _5353; + uint16_t _5354 = (uint16_t)(158); + _curvea0[355] = _5354; + uint16_t _5355 = (uint16_t)(158); + _curvea0[356] = _5355; + uint16_t _5356 = (uint16_t)(159); + _curvea0[357] = _5356; + uint16_t _5357 = (uint16_t)(159); + _curvea0[358] = _5357; + uint16_t _5358 = (uint16_t)(159); + _curvea0[359] = _5358; + uint16_t _5359 = (uint16_t)(159); + _curvea0[360] = _5359; + uint16_t _5360 = (uint16_t)(160); + _curvea0[361] = _5360; + uint16_t _5361 = (uint16_t)(160); + _curvea0[362] = _5361; + uint16_t _5362 = (uint16_t)(160); + _curvea0[363] = _5362; + uint16_t _5363 = (uint16_t)(160); + _curvea0[364] = _5363; + uint16_t _5364 = (uint16_t)(161); + _curvea0[365] = _5364; + uint16_t _5365 = (uint16_t)(161); + _curvea0[366] = _5365; + uint16_t _5366 = (uint16_t)(161); + _curvea0[367] = _5366; + uint16_t _5367 = (uint16_t)(161); + _curvea0[368] = _5367; + uint16_t _5368 = (uint16_t)(162); + _curvea0[369] = _5368; + uint16_t _5369 = (uint16_t)(162); + _curvea0[370] = _5369; + uint16_t _5370 = (uint16_t)(162); + _curvea0[371] = _5370; + uint16_t _5371 = (uint16_t)(162); + _curvea0[372] = _5371; + uint16_t _5372 = (uint16_t)(163); + _curvea0[373] = _5372; + uint16_t _5373 = (uint16_t)(163); + _curvea0[374] = _5373; + uint16_t _5374 = (uint16_t)(163); + _curvea0[375] = _5374; + uint16_t _5375 = (uint16_t)(163); + _curvea0[376] = _5375; + uint16_t _5376 = (uint16_t)(164); + _curvea0[377] = _5376; + uint16_t _5377 = (uint16_t)(164); + _curvea0[378] = _5377; + uint16_t _5378 = (uint16_t)(164); + _curvea0[379] = _5378; + uint16_t _5379 = (uint16_t)(164); + _curvea0[380] = _5379; + uint16_t _5380 = (uint16_t)(165); + _curvea0[381] = _5380; + uint16_t _5381 = (uint16_t)(165); + _curvea0[382] = _5381; + uint16_t _5382 = (uint16_t)(165); + _curvea0[383] = _5382; + uint16_t _5383 = (uint16_t)(166); + _curvea0[384] = _5383; + uint16_t _5384 = (uint16_t)(166); + _curvea0[385] = _5384; + uint16_t _5385 = (uint16_t)(166); + _curvea0[386] = _5385; + uint16_t _5386 = (uint16_t)(166); + _curvea0[387] = _5386; + uint16_t _5387 = (uint16_t)(167); + _curvea0[388] = _5387; + uint16_t _5388 = (uint16_t)(167); + _curvea0[389] = _5388; + uint16_t _5389 = (uint16_t)(167); + _curvea0[390] = _5389; + uint16_t _5390 = (uint16_t)(167); + _curvea0[391] = _5390; + uint16_t _5391 = (uint16_t)(167); + _curvea0[392] = _5391; + uint16_t _5392 = (uint16_t)(168); + _curvea0[393] = _5392; + uint16_t _5393 = (uint16_t)(168); + _curvea0[394] = _5393; + uint16_t _5394 = (uint16_t)(168); + _curvea0[395] = _5394; + uint16_t _5395 = (uint16_t)(168); + _curvea0[396] = _5395; + uint16_t _5396 = (uint16_t)(169); + _curvea0[397] = _5396; + uint16_t _5397 = (uint16_t)(169); + _curvea0[398] = _5397; + uint16_t _5398 = (uint16_t)(169); + _curvea0[399] = _5398; + uint16_t _5399 = (uint16_t)(169); + _curvea0[400] = _5399; + uint16_t _5400 = (uint16_t)(170); + _curvea0[401] = _5400; + uint16_t _5401 = (uint16_t)(170); + _curvea0[402] = _5401; + uint16_t _5402 = (uint16_t)(170); + _curvea0[403] = _5402; + uint16_t _5403 = (uint16_t)(170); + _curvea0[404] = _5403; + uint16_t _5404 = (uint16_t)(171); + _curvea0[405] = _5404; + uint16_t _5405 = (uint16_t)(171); + _curvea0[406] = _5405; + uint16_t _5406 = (uint16_t)(171); + _curvea0[407] = _5406; + uint16_t _5407 = (uint16_t)(171); + _curvea0[408] = _5407; + uint16_t _5408 = (uint16_t)(172); + _curvea0[409] = _5408; + uint16_t _5409 = (uint16_t)(172); + _curvea0[410] = _5409; + uint16_t _5410 = (uint16_t)(172); + _curvea0[411] = _5410; + uint16_t _5411 = (uint16_t)(172); + _curvea0[412] = _5411; + uint16_t _5412 = (uint16_t)(173); + _curvea0[413] = _5412; + uint16_t _5413 = (uint16_t)(173); + _curvea0[414] = _5413; + uint16_t _5414 = (uint16_t)(173); + _curvea0[415] = _5414; + uint16_t _5415 = (uint16_t)(173); + _curvea0[416] = _5415; + uint16_t _5416 = (uint16_t)(173); + _curvea0[417] = _5416; + uint16_t _5417 = (uint16_t)(174); + _curvea0[418] = _5417; + uint16_t _5418 = (uint16_t)(174); + _curvea0[419] = _5418; + uint16_t _5419 = (uint16_t)(174); + _curvea0[420] = _5419; + uint16_t _5420 = (uint16_t)(174); + _curvea0[421] = _5420; + uint16_t _5421 = (uint16_t)(175); + _curvea0[422] = _5421; + uint16_t _5422 = (uint16_t)(175); + _curvea0[423] = _5422; + uint16_t _5423 = (uint16_t)(175); + _curvea0[424] = _5423; + uint16_t _5424 = (uint16_t)(175); + _curvea0[425] = _5424; + uint16_t _5425 = (uint16_t)(176); + _curvea0[426] = _5425; + uint16_t _5426 = (uint16_t)(176); + _curvea0[427] = _5426; + uint16_t _5427 = (uint16_t)(176); + _curvea0[428] = _5427; + uint16_t _5428 = (uint16_t)(176); + _curvea0[429] = _5428; + uint16_t _5429 = (uint16_t)(176); + _curvea0[430] = _5429; + uint16_t _5430 = (uint16_t)(177); + _curvea0[431] = _5430; + uint16_t _5431 = (uint16_t)(177); + _curvea0[432] = _5431; + uint16_t _5432 = (uint16_t)(177); + _curvea0[433] = _5432; + uint16_t _5433 = (uint16_t)(177); + _curvea0[434] = _5433; + uint16_t _5434 = (uint16_t)(178); + _curvea0[435] = _5434; + uint16_t _5435 = (uint16_t)(178); + _curvea0[436] = _5435; + uint16_t _5436 = (uint16_t)(178); + _curvea0[437] = _5436; + uint16_t _5437 = (uint16_t)(178); + _curvea0[438] = _5437; + uint16_t _5438 = (uint16_t)(178); + _curvea0[439] = _5438; + uint16_t _5439 = (uint16_t)(179); + _curvea0[440] = _5439; + uint16_t _5440 = (uint16_t)(179); + _curvea0[441] = _5440; + uint16_t _5441 = (uint16_t)(179); + _curvea0[442] = _5441; + uint16_t _5442 = (uint16_t)(179); + _curvea0[443] = _5442; + uint16_t _5443 = (uint16_t)(180); + _curvea0[444] = _5443; + uint16_t _5444 = (uint16_t)(180); + _curvea0[445] = _5444; + uint16_t _5445 = (uint16_t)(180); + _curvea0[446] = _5445; + uint16_t _5446 = (uint16_t)(180); + _curvea0[447] = _5446; + uint16_t _5447 = (uint16_t)(180); + _curvea0[448] = _5447; + uint16_t _5448 = (uint16_t)(181); + _curvea0[449] = _5448; + uint16_t _5449 = (uint16_t)(181); + _curvea0[450] = _5449; + uint16_t _5450 = (uint16_t)(181); + _curvea0[451] = _5450; + uint16_t _5451 = (uint16_t)(181); + _curvea0[452] = _5451; + uint16_t _5452 = (uint16_t)(181); + _curvea0[453] = _5452; + uint16_t _5453 = (uint16_t)(182); + _curvea0[454] = _5453; + uint16_t _5454 = (uint16_t)(182); + _curvea0[455] = _5454; + uint16_t _5455 = (uint16_t)(182); + _curvea0[456] = _5455; + uint16_t _5456 = (uint16_t)(182); + _curvea0[457] = _5456; + uint16_t _5457 = (uint16_t)(183); + _curvea0[458] = _5457; + uint16_t _5458 = (uint16_t)(183); + _curvea0[459] = _5458; + uint16_t _5459 = (uint16_t)(183); + _curvea0[460] = _5459; + uint16_t _5460 = (uint16_t)(183); + _curvea0[461] = _5460; + uint16_t _5461 = (uint16_t)(183); + _curvea0[462] = _5461; + uint16_t _5462 = (uint16_t)(184); + _curvea0[463] = _5462; + uint16_t _5463 = (uint16_t)(184); + _curvea0[464] = _5463; + uint16_t _5464 = (uint16_t)(184); + _curvea0[465] = _5464; + uint16_t _5465 = (uint16_t)(184); + _curvea0[466] = _5465; + uint16_t _5466 = (uint16_t)(184); + _curvea0[467] = _5466; + uint16_t _5467 = (uint16_t)(185); + _curvea0[468] = _5467; + uint16_t _5468 = (uint16_t)(185); + _curvea0[469] = _5468; + uint16_t _5469 = (uint16_t)(185); + _curvea0[470] = _5469; + uint16_t _5470 = (uint16_t)(185); + _curvea0[471] = _5470; + uint16_t _5471 = (uint16_t)(185); + _curvea0[472] = _5471; + uint16_t _5472 = (uint16_t)(186); + _curvea0[473] = _5472; + uint16_t _5473 = (uint16_t)(186); + _curvea0[474] = _5473; + uint16_t _5474 = (uint16_t)(186); + _curvea0[475] = _5474; + uint16_t _5475 = (uint16_t)(186); + _curvea0[476] = _5475; + uint16_t _5476 = (uint16_t)(187); + _curvea0[477] = _5476; + uint16_t _5477 = (uint16_t)(187); + _curvea0[478] = _5477; + uint16_t _5478 = (uint16_t)(187); + _curvea0[479] = _5478; + uint16_t _5479 = (uint16_t)(187); + _curvea0[480] = _5479; + uint16_t _5480 = (uint16_t)(187); + _curvea0[481] = _5480; + uint16_t _5481 = (uint16_t)(188); + _curvea0[482] = _5481; + uint16_t _5482 = (uint16_t)(188); + _curvea0[483] = _5482; + uint16_t _5483 = (uint16_t)(188); + _curvea0[484] = _5483; + uint16_t _5484 = (uint16_t)(188); + _curvea0[485] = _5484; + uint16_t _5485 = (uint16_t)(188); + _curvea0[486] = _5485; + uint16_t _5486 = (uint16_t)(189); + _curvea0[487] = _5486; + uint16_t _5487 = (uint16_t)(189); + _curvea0[488] = _5487; + uint16_t _5488 = (uint16_t)(189); + _curvea0[489] = _5488; + uint16_t _5489 = (uint16_t)(189); + _curvea0[490] = _5489; + uint16_t _5490 = (uint16_t)(189); + _curvea0[491] = _5490; + uint16_t _5491 = (uint16_t)(190); + _curvea0[492] = _5491; + uint16_t _5492 = (uint16_t)(190); + _curvea0[493] = _5492; + uint16_t _5493 = (uint16_t)(190); + _curvea0[494] = _5493; + uint16_t _5494 = (uint16_t)(190); + _curvea0[495] = _5494; + uint16_t _5495 = (uint16_t)(190); + _curvea0[496] = _5495; + uint16_t _5496 = (uint16_t)(190); + _curvea0[497] = _5496; + uint16_t _5497 = (uint16_t)(191); + _curvea0[498] = _5497; + uint16_t _5498 = (uint16_t)(191); + _curvea0[499] = _5498; + uint16_t _5499 = (uint16_t)(191); + _curvea0[500] = _5499; + uint16_t _5500 = (uint16_t)(191); + _curvea0[501] = _5500; + uint16_t _5501 = (uint16_t)(191); + _curvea0[502] = _5501; + uint16_t _5502 = (uint16_t)(192); + _curvea0[503] = _5502; + uint16_t _5503 = (uint16_t)(192); + _curvea0[504] = _5503; + uint16_t _5504 = (uint16_t)(192); + _curvea0[505] = _5504; + uint16_t _5505 = (uint16_t)(192); + _curvea0[506] = _5505; + uint16_t _5506 = (uint16_t)(192); + _curvea0[507] = _5506; + uint16_t _5507 = (uint16_t)(193); + _curvea0[508] = _5507; + uint16_t _5508 = (uint16_t)(193); + _curvea0[509] = _5508; + uint16_t _5509 = (uint16_t)(193); + _curvea0[510] = _5509; + uint16_t _5510 = (uint16_t)(193); + _curvea0[511] = _5510; + uint16_t _5511 = (uint16_t)(193); + _curvea0[512] = _5511; + uint16_t _5512 = (uint16_t)(194); + _curvea0[513] = _5512; + uint16_t _5513 = (uint16_t)(194); + _curvea0[514] = _5513; + uint16_t _5514 = (uint16_t)(194); + _curvea0[515] = _5514; + uint16_t _5515 = (uint16_t)(194); + _curvea0[516] = _5515; + uint16_t _5516 = (uint16_t)(194); + _curvea0[517] = _5516; + uint16_t _5517 = (uint16_t)(195); + _curvea0[518] = _5517; + uint16_t _5518 = (uint16_t)(195); + _curvea0[519] = _5518; + uint16_t _5519 = (uint16_t)(195); + _curvea0[520] = _5519; + uint16_t _5520 = (uint16_t)(195); + _curvea0[521] = _5520; + uint16_t _5521 = (uint16_t)(195); + _curvea0[522] = _5521; + uint16_t _5522 = (uint16_t)(195); + _curvea0[523] = _5522; + uint16_t _5523 = (uint16_t)(196); + _curvea0[524] = _5523; + uint16_t _5524 = (uint16_t)(196); + _curvea0[525] = _5524; + uint16_t _5525 = (uint16_t)(196); + _curvea0[526] = _5525; + uint16_t _5526 = (uint16_t)(196); + _curvea0[527] = _5526; + uint16_t _5527 = (uint16_t)(196); + _curvea0[528] = _5527; + uint16_t _5528 = (uint16_t)(197); + _curvea0[529] = _5528; + uint16_t _5529 = (uint16_t)(197); + _curvea0[530] = _5529; + uint16_t _5530 = (uint16_t)(197); + _curvea0[531] = _5530; + uint16_t _5531 = (uint16_t)(197); + _curvea0[532] = _5531; + uint16_t _5532 = (uint16_t)(197); + _curvea0[533] = _5532; + uint16_t _5533 = (uint16_t)(197); + _curvea0[534] = _5533; + uint16_t _5534 = (uint16_t)(198); + _curvea0[535] = _5534; + uint16_t _5535 = (uint16_t)(198); + _curvea0[536] = _5535; + uint16_t _5536 = (uint16_t)(198); + _curvea0[537] = _5536; + uint16_t _5537 = (uint16_t)(198); + _curvea0[538] = _5537; + uint16_t _5538 = (uint16_t)(198); + _curvea0[539] = _5538; + uint16_t _5539 = (uint16_t)(199); + _curvea0[540] = _5539; + uint16_t _5540 = (uint16_t)(199); + _curvea0[541] = _5540; + uint16_t _5541 = (uint16_t)(199); + _curvea0[542] = _5541; + uint16_t _5542 = (uint16_t)(199); + _curvea0[543] = _5542; + uint16_t _5543 = (uint16_t)(199); + _curvea0[544] = _5543; + uint16_t _5544 = (uint16_t)(199); + _curvea0[545] = _5544; + uint16_t _5545 = (uint16_t)(200); + _curvea0[546] = _5545; + uint16_t _5546 = (uint16_t)(200); + _curvea0[547] = _5546; + uint16_t _5547 = (uint16_t)(200); + _curvea0[548] = _5547; + uint16_t _5548 = (uint16_t)(200); + _curvea0[549] = _5548; + uint16_t _5549 = (uint16_t)(200); + _curvea0[550] = _5549; + uint16_t _5550 = (uint16_t)(200); + _curvea0[551] = _5550; + uint16_t _5551 = (uint16_t)(201); + _curvea0[552] = _5551; + uint16_t _5552 = (uint16_t)(201); + _curvea0[553] = _5552; + uint16_t _5553 = (uint16_t)(201); + _curvea0[554] = _5553; + uint16_t _5554 = (uint16_t)(201); + _curvea0[555] = _5554; + uint16_t _5555 = (uint16_t)(201); + _curvea0[556] = _5555; + uint16_t _5556 = (uint16_t)(202); + _curvea0[557] = _5556; + uint16_t _5557 = (uint16_t)(202); + _curvea0[558] = _5557; + uint16_t _5558 = (uint16_t)(202); + _curvea0[559] = _5558; + uint16_t _5559 = (uint16_t)(202); + _curvea0[560] = _5559; + uint16_t _5560 = (uint16_t)(202); + _curvea0[561] = _5560; + uint16_t _5561 = (uint16_t)(202); + _curvea0[562] = _5561; + uint16_t _5562 = (uint16_t)(203); + _curvea0[563] = _5562; + uint16_t _5563 = (uint16_t)(203); + _curvea0[564] = _5563; + uint16_t _5564 = (uint16_t)(203); + _curvea0[565] = _5564; + uint16_t _5565 = (uint16_t)(203); + _curvea0[566] = _5565; + uint16_t _5566 = (uint16_t)(203); + _curvea0[567] = _5566; + uint16_t _5567 = (uint16_t)(203); + _curvea0[568] = _5567; + uint16_t _5568 = (uint16_t)(204); + _curvea0[569] = _5568; + uint16_t _5569 = (uint16_t)(204); + _curvea0[570] = _5569; + uint16_t _5570 = (uint16_t)(204); + _curvea0[571] = _5570; + uint16_t _5571 = (uint16_t)(204); + _curvea0[572] = _5571; + uint16_t _5572 = (uint16_t)(204); + _curvea0[573] = _5572; + uint16_t _5573 = (uint16_t)(204); + _curvea0[574] = _5573; + uint16_t _5574 = (uint16_t)(205); + _curvea0[575] = _5574; + uint16_t _5575 = (uint16_t)(205); + _curvea0[576] = _5575; + uint16_t _5576 = (uint16_t)(205); + _curvea0[577] = _5576; + uint16_t _5577 = (uint16_t)(205); + _curvea0[578] = _5577; + uint16_t _5578 = (uint16_t)(205); + _curvea0[579] = _5578; + uint16_t _5579 = (uint16_t)(205); + _curvea0[580] = _5579; + uint16_t _5580 = (uint16_t)(206); + _curvea0[581] = _5580; + uint16_t _5581 = (uint16_t)(206); + _curvea0[582] = _5581; + uint16_t _5582 = (uint16_t)(206); + _curvea0[583] = _5582; + uint16_t _5583 = (uint16_t)(206); + _curvea0[584] = _5583; + uint16_t _5584 = (uint16_t)(206); + _curvea0[585] = _5584; + uint16_t _5585 = (uint16_t)(206); + _curvea0[586] = _5585; + uint16_t _5586 = (uint16_t)(207); + _curvea0[587] = _5586; + uint16_t _5587 = (uint16_t)(207); + _curvea0[588] = _5587; + uint16_t _5588 = (uint16_t)(207); + _curvea0[589] = _5588; + uint16_t _5589 = (uint16_t)(207); + _curvea0[590] = _5589; + uint16_t _5590 = (uint16_t)(207); + _curvea0[591] = _5590; + uint16_t _5591 = (uint16_t)(207); + _curvea0[592] = _5591; + uint16_t _5592 = (uint16_t)(208); + _curvea0[593] = _5592; + uint16_t _5593 = (uint16_t)(208); + _curvea0[594] = _5593; + uint16_t _5594 = (uint16_t)(208); + _curvea0[595] = _5594; + uint16_t _5595 = (uint16_t)(208); + _curvea0[596] = _5595; + uint16_t _5596 = (uint16_t)(208); + _curvea0[597] = _5596; + uint16_t _5597 = (uint16_t)(208); + _curvea0[598] = _5597; + uint16_t _5598 = (uint16_t)(209); + _curvea0[599] = _5598; + uint16_t _5599 = (uint16_t)(209); + _curvea0[600] = _5599; + uint16_t _5600 = (uint16_t)(209); + _curvea0[601] = _5600; + uint16_t _5601 = (uint16_t)(209); + _curvea0[602] = _5601; + uint16_t _5602 = (uint16_t)(209); + _curvea0[603] = _5602; + uint16_t _5603 = (uint16_t)(209); + _curvea0[604] = _5603; + uint16_t _5604 = (uint16_t)(209); + _curvea0[605] = _5604; + uint16_t _5605 = (uint16_t)(210); + _curvea0[606] = _5605; + uint16_t _5606 = (uint16_t)(210); + _curvea0[607] = _5606; + uint16_t _5607 = (uint16_t)(210); + _curvea0[608] = _5607; + uint16_t _5608 = (uint16_t)(210); + _curvea0[609] = _5608; + uint16_t _5609 = (uint16_t)(210); + _curvea0[610] = _5609; + uint16_t _5610 = (uint16_t)(210); + _curvea0[611] = _5610; + uint16_t _5611 = (uint16_t)(211); + _curvea0[612] = _5611; + uint16_t _5612 = (uint16_t)(211); + _curvea0[613] = _5612; + uint16_t _5613 = (uint16_t)(211); + _curvea0[614] = _5613; + uint16_t _5614 = (uint16_t)(211); + _curvea0[615] = _5614; + uint16_t _5615 = (uint16_t)(211); + _curvea0[616] = _5615; + uint16_t _5616 = (uint16_t)(211); + _curvea0[617] = _5616; + uint16_t _5617 = (uint16_t)(211); + _curvea0[618] = _5617; + uint16_t _5618 = (uint16_t)(212); + _curvea0[619] = _5618; + uint16_t _5619 = (uint16_t)(212); + _curvea0[620] = _5619; + uint16_t _5620 = (uint16_t)(212); + _curvea0[621] = _5620; + uint16_t _5621 = (uint16_t)(212); + _curvea0[622] = _5621; + uint16_t _5622 = (uint16_t)(212); + _curvea0[623] = _5622; + uint16_t _5623 = (uint16_t)(212); + _curvea0[624] = _5623; + uint16_t _5624 = (uint16_t)(213); + _curvea0[625] = _5624; + uint16_t _5625 = (uint16_t)(213); + _curvea0[626] = _5625; + uint16_t _5626 = (uint16_t)(213); + _curvea0[627] = _5626; + uint16_t _5627 = (uint16_t)(213); + _curvea0[628] = _5627; + uint16_t _5628 = (uint16_t)(213); + _curvea0[629] = _5628; + uint16_t _5629 = (uint16_t)(213); + _curvea0[630] = _5629; + uint16_t _5630 = (uint16_t)(213); + _curvea0[631] = _5630; + uint16_t _5631 = (uint16_t)(214); + _curvea0[632] = _5631; + uint16_t _5632 = (uint16_t)(214); + _curvea0[633] = _5632; + uint16_t _5633 = (uint16_t)(214); + _curvea0[634] = _5633; + uint16_t _5634 = (uint16_t)(214); + _curvea0[635] = _5634; + uint16_t _5635 = (uint16_t)(214); + _curvea0[636] = _5635; + uint16_t _5636 = (uint16_t)(214); + _curvea0[637] = _5636; + uint16_t _5637 = (uint16_t)(214); + _curvea0[638] = _5637; + uint16_t _5638 = (uint16_t)(215); + _curvea0[639] = _5638; + uint16_t _5639 = (uint16_t)(215); + _curvea0[640] = _5639; + uint16_t _5640 = (uint16_t)(215); + _curvea0[641] = _5640; + uint16_t _5641 = (uint16_t)(215); + _curvea0[642] = _5641; + uint16_t _5642 = (uint16_t)(215); + _curvea0[643] = _5642; + uint16_t _5643 = (uint16_t)(215); + _curvea0[644] = _5643; + uint16_t _5644 = (uint16_t)(216); + _curvea0[645] = _5644; + uint16_t _5645 = (uint16_t)(216); + _curvea0[646] = _5645; + uint16_t _5646 = (uint16_t)(216); + _curvea0[647] = _5646; + uint16_t _5647 = (uint16_t)(216); + _curvea0[648] = _5647; + uint16_t _5648 = (uint16_t)(216); + _curvea0[649] = _5648; + uint16_t _5649 = (uint16_t)(216); + _curvea0[650] = _5649; + uint16_t _5650 = (uint16_t)(216); + _curvea0[651] = _5650; + uint16_t _5651 = (uint16_t)(217); + _curvea0[652] = _5651; + uint16_t _5652 = (uint16_t)(217); + _curvea0[653] = _5652; + uint16_t _5653 = (uint16_t)(217); + _curvea0[654] = _5653; + uint16_t _5654 = (uint16_t)(217); + _curvea0[655] = _5654; + uint16_t _5655 = (uint16_t)(217); + _curvea0[656] = _5655; + uint16_t _5656 = (uint16_t)(217); + _curvea0[657] = _5656; + uint16_t _5657 = (uint16_t)(217); + _curvea0[658] = _5657; + uint16_t _5658 = (uint16_t)(218); + _curvea0[659] = _5658; + uint16_t _5659 = (uint16_t)(218); + _curvea0[660] = _5659; + uint16_t _5660 = (uint16_t)(218); + _curvea0[661] = _5660; + uint16_t _5661 = (uint16_t)(218); + _curvea0[662] = _5661; + uint16_t _5662 = (uint16_t)(218); + _curvea0[663] = _5662; + uint16_t _5663 = (uint16_t)(218); + _curvea0[664] = _5663; + uint16_t _5664 = (uint16_t)(218); + _curvea0[665] = _5664; + uint16_t _5665 = (uint16_t)(219); + _curvea0[666] = _5665; + uint16_t _5666 = (uint16_t)(219); + _curvea0[667] = _5666; + uint16_t _5667 = (uint16_t)(219); + _curvea0[668] = _5667; + uint16_t _5668 = (uint16_t)(219); + _curvea0[669] = _5668; + uint16_t _5669 = (uint16_t)(219); + _curvea0[670] = _5669; + uint16_t _5670 = (uint16_t)(219); + _curvea0[671] = _5670; + uint16_t _5671 = (uint16_t)(219); + _curvea0[672] = _5671; + uint16_t _5672 = (uint16_t)(220); + _curvea0[673] = _5672; + uint16_t _5673 = (uint16_t)(220); + _curvea0[674] = _5673; + uint16_t _5674 = (uint16_t)(220); + _curvea0[675] = _5674; + uint16_t _5675 = (uint16_t)(220); + _curvea0[676] = _5675; + uint16_t _5676 = (uint16_t)(220); + _curvea0[677] = _5676; + uint16_t _5677 = (uint16_t)(220); + _curvea0[678] = _5677; + uint16_t _5678 = (uint16_t)(220); + _curvea0[679] = _5678; + uint16_t _5679 = (uint16_t)(220); + _curvea0[680] = _5679; + uint16_t _5680 = (uint16_t)(221); + _curvea0[681] = _5680; + uint16_t _5681 = (uint16_t)(221); + _curvea0[682] = _5681; + uint16_t _5682 = (uint16_t)(221); + _curvea0[683] = _5682; + uint16_t _5683 = (uint16_t)(221); + _curvea0[684] = _5683; + uint16_t _5684 = (uint16_t)(221); + _curvea0[685] = _5684; + uint16_t _5685 = (uint16_t)(221); + _curvea0[686] = _5685; + uint16_t _5686 = (uint16_t)(221); + _curvea0[687] = _5686; + uint16_t _5687 = (uint16_t)(222); + _curvea0[688] = _5687; + uint16_t _5688 = (uint16_t)(222); + _curvea0[689] = _5688; + uint16_t _5689 = (uint16_t)(222); + _curvea0[690] = _5689; + uint16_t _5690 = (uint16_t)(222); + _curvea0[691] = _5690; + uint16_t _5691 = (uint16_t)(222); + _curvea0[692] = _5691; + uint16_t _5692 = (uint16_t)(222); + _curvea0[693] = _5692; + uint16_t _5693 = (uint16_t)(222); + _curvea0[694] = _5693; + uint16_t _5694 = (uint16_t)(223); + _curvea0[695] = _5694; + uint16_t _5695 = (uint16_t)(223); + _curvea0[696] = _5695; + uint16_t _5696 = (uint16_t)(223); + _curvea0[697] = _5696; + uint16_t _5697 = (uint16_t)(223); + _curvea0[698] = _5697; + uint16_t _5698 = (uint16_t)(223); + _curvea0[699] = _5698; + uint16_t _5699 = (uint16_t)(223); + _curvea0[700] = _5699; + uint16_t _5700 = (uint16_t)(223); + _curvea0[701] = _5700; + uint16_t _5701 = (uint16_t)(223); + _curvea0[702] = _5701; + uint16_t _5702 = (uint16_t)(224); + _curvea0[703] = _5702; + uint16_t _5703 = (uint16_t)(224); + _curvea0[704] = _5703; + uint16_t _5704 = (uint16_t)(224); + _curvea0[705] = _5704; + uint16_t _5705 = (uint16_t)(224); + _curvea0[706] = _5705; + uint16_t _5706 = (uint16_t)(224); + _curvea0[707] = _5706; + uint16_t _5707 = (uint16_t)(224); + _curvea0[708] = _5707; + uint16_t _5708 = (uint16_t)(224); + _curvea0[709] = _5708; + uint16_t _5709 = (uint16_t)(224); + _curvea0[710] = _5709; + uint16_t _5710 = (uint16_t)(225); + _curvea0[711] = _5710; + uint16_t _5711 = (uint16_t)(225); + _curvea0[712] = _5711; + uint16_t _5712 = (uint16_t)(225); + _curvea0[713] = _5712; + uint16_t _5713 = (uint16_t)(225); + _curvea0[714] = _5713; + uint16_t _5714 = (uint16_t)(225); + _curvea0[715] = _5714; + uint16_t _5715 = (uint16_t)(225); + _curvea0[716] = _5715; + uint16_t _5716 = (uint16_t)(225); + _curvea0[717] = _5716; + uint16_t _5717 = (uint16_t)(226); + _curvea0[718] = _5717; + uint16_t _5718 = (uint16_t)(226); + _curvea0[719] = _5718; + uint16_t _5719 = (uint16_t)(226); + _curvea0[720] = _5719; + uint16_t _5720 = (uint16_t)(226); + _curvea0[721] = _5720; + uint16_t _5721 = (uint16_t)(226); + _curvea0[722] = _5721; + uint16_t _5722 = (uint16_t)(226); + _curvea0[723] = _5722; + uint16_t _5723 = (uint16_t)(226); + _curvea0[724] = _5723; + uint16_t _5724 = (uint16_t)(226); + _curvea0[725] = _5724; + uint16_t _5725 = (uint16_t)(227); + _curvea0[726] = _5725; + uint16_t _5726 = (uint16_t)(227); + _curvea0[727] = _5726; + uint16_t _5727 = (uint16_t)(227); + _curvea0[728] = _5727; + uint16_t _5728 = (uint16_t)(227); + _curvea0[729] = _5728; + uint16_t _5729 = (uint16_t)(227); + _curvea0[730] = _5729; + uint16_t _5730 = (uint16_t)(227); + _curvea0[731] = _5730; + uint16_t _5731 = (uint16_t)(227); + _curvea0[732] = _5731; + uint16_t _5732 = (uint16_t)(227); + _curvea0[733] = _5732; + uint16_t _5733 = (uint16_t)(228); + _curvea0[734] = _5733; + uint16_t _5734 = (uint16_t)(228); + _curvea0[735] = _5734; + uint16_t _5735 = (uint16_t)(228); + _curvea0[736] = _5735; + uint16_t _5736 = (uint16_t)(228); + _curvea0[737] = _5736; + uint16_t _5737 = (uint16_t)(228); + _curvea0[738] = _5737; + uint16_t _5738 = (uint16_t)(228); + _curvea0[739] = _5738; + uint16_t _5739 = (uint16_t)(228); + _curvea0[740] = _5739; + uint16_t _5740 = (uint16_t)(228); + _curvea0[741] = _5740; + uint16_t _5741 = (uint16_t)(228); + _curvea0[742] = _5741; + uint16_t _5742 = (uint16_t)(229); + _curvea0[743] = _5742; + uint16_t _5743 = (uint16_t)(229); + _curvea0[744] = _5743; + uint16_t _5744 = (uint16_t)(229); + _curvea0[745] = _5744; + uint16_t _5745 = (uint16_t)(229); + _curvea0[746] = _5745; + uint16_t _5746 = (uint16_t)(229); + _curvea0[747] = _5746; + uint16_t _5747 = (uint16_t)(229); + _curvea0[748] = _5747; + uint16_t _5748 = (uint16_t)(229); + _curvea0[749] = _5748; + uint16_t _5749 = (uint16_t)(229); + _curvea0[750] = _5749; + uint16_t _5750 = (uint16_t)(230); + _curvea0[751] = _5750; + uint16_t _5751 = (uint16_t)(230); + _curvea0[752] = _5751; + uint16_t _5752 = (uint16_t)(230); + _curvea0[753] = _5752; + uint16_t _5753 = (uint16_t)(230); + _curvea0[754] = _5753; + uint16_t _5754 = (uint16_t)(230); + _curvea0[755] = _5754; + uint16_t _5755 = (uint16_t)(230); + _curvea0[756] = _5755; + uint16_t _5756 = (uint16_t)(230); + _curvea0[757] = _5756; + uint16_t _5757 = (uint16_t)(230); + _curvea0[758] = _5757; + uint16_t _5758 = (uint16_t)(231); + _curvea0[759] = _5758; + uint16_t _5759 = (uint16_t)(231); + _curvea0[760] = _5759; + uint16_t _5760 = (uint16_t)(231); + _curvea0[761] = _5760; + uint16_t _5761 = (uint16_t)(231); + _curvea0[762] = _5761; + uint16_t _5762 = (uint16_t)(231); + _curvea0[763] = _5762; + uint16_t _5763 = (uint16_t)(231); + _curvea0[764] = _5763; + uint16_t _5764 = (uint16_t)(231); + _curvea0[765] = _5764; + uint16_t _5765 = (uint16_t)(231); + _curvea0[766] = _5765; + uint16_t _5766 = (uint16_t)(231); + _curvea0[767] = _5766; + uint16_t _5767 = (uint16_t)(232); + _curvea0[768] = _5767; + uint16_t _5768 = (uint16_t)(232); + _curvea0[769] = _5768; + uint16_t _5769 = (uint16_t)(232); + _curvea0[770] = _5769; + uint16_t _5770 = (uint16_t)(232); + _curvea0[771] = _5770; + uint16_t _5771 = (uint16_t)(232); + _curvea0[772] = _5771; + uint16_t _5772 = (uint16_t)(232); + _curvea0[773] = _5772; + uint16_t _5773 = (uint16_t)(232); + _curvea0[774] = _5773; + uint16_t _5774 = (uint16_t)(232); + _curvea0[775] = _5774; + uint16_t _5775 = (uint16_t)(233); + _curvea0[776] = _5775; + uint16_t _5776 = (uint16_t)(233); + _curvea0[777] = _5776; + uint16_t _5777 = (uint16_t)(233); + _curvea0[778] = _5777; + uint16_t _5778 = (uint16_t)(233); + _curvea0[779] = _5778; + uint16_t _5779 = (uint16_t)(233); + _curvea0[780] = _5779; + uint16_t _5780 = (uint16_t)(233); + _curvea0[781] = _5780; + uint16_t _5781 = (uint16_t)(233); + _curvea0[782] = _5781; + uint16_t _5782 = (uint16_t)(233); + _curvea0[783] = _5782; + uint16_t _5783 = (uint16_t)(233); + _curvea0[784] = _5783; + uint16_t _5784 = (uint16_t)(234); + _curvea0[785] = _5784; + uint16_t _5785 = (uint16_t)(234); + _curvea0[786] = _5785; + uint16_t _5786 = (uint16_t)(234); + _curvea0[787] = _5786; + uint16_t _5787 = (uint16_t)(234); + _curvea0[788] = _5787; + uint16_t _5788 = (uint16_t)(234); + _curvea0[789] = _5788; + uint16_t _5789 = (uint16_t)(234); + _curvea0[790] = _5789; + uint16_t _5790 = (uint16_t)(234); + _curvea0[791] = _5790; + uint16_t _5791 = (uint16_t)(234); + _curvea0[792] = _5791; + uint16_t _5792 = (uint16_t)(234); + _curvea0[793] = _5792; + uint16_t _5793 = (uint16_t)(235); + _curvea0[794] = _5793; + uint16_t _5794 = (uint16_t)(235); + _curvea0[795] = _5794; + uint16_t _5795 = (uint16_t)(235); + _curvea0[796] = _5795; + uint16_t _5796 = (uint16_t)(235); + _curvea0[797] = _5796; + uint16_t _5797 = (uint16_t)(235); + _curvea0[798] = _5797; + uint16_t _5798 = (uint16_t)(235); + _curvea0[799] = _5798; + uint16_t _5799 = (uint16_t)(235); + _curvea0[800] = _5799; + uint16_t _5800 = (uint16_t)(235); + _curvea0[801] = _5800; + uint16_t _5801 = (uint16_t)(235); + _curvea0[802] = _5801; + uint16_t _5802 = (uint16_t)(236); + _curvea0[803] = _5802; + uint16_t _5803 = (uint16_t)(236); + _curvea0[804] = _5803; + uint16_t _5804 = (uint16_t)(236); + _curvea0[805] = _5804; + uint16_t _5805 = (uint16_t)(236); + _curvea0[806] = _5805; + uint16_t _5806 = (uint16_t)(236); + _curvea0[807] = _5806; + uint16_t _5807 = (uint16_t)(236); + _curvea0[808] = _5807; + uint16_t _5808 = (uint16_t)(236); + _curvea0[809] = _5808; + uint16_t _5809 = (uint16_t)(236); + _curvea0[810] = _5809; + uint16_t _5810 = (uint16_t)(236); + _curvea0[811] = _5810; + uint16_t _5811 = (uint16_t)(237); + _curvea0[812] = _5811; + uint16_t _5812 = (uint16_t)(237); + _curvea0[813] = _5812; + uint16_t _5813 = (uint16_t)(237); + _curvea0[814] = _5813; + uint16_t _5814 = (uint16_t)(237); + _curvea0[815] = _5814; + uint16_t _5815 = (uint16_t)(237); + _curvea0[816] = _5815; + uint16_t _5816 = (uint16_t)(237); + _curvea0[817] = _5816; + uint16_t _5817 = (uint16_t)(237); + _curvea0[818] = _5817; + uint16_t _5818 = (uint16_t)(237); + _curvea0[819] = _5818; + uint16_t _5819 = (uint16_t)(237); + _curvea0[820] = _5819; + uint16_t _5820 = (uint16_t)(237); + _curvea0[821] = _5820; + uint16_t _5821 = (uint16_t)(238); + _curvea0[822] = _5821; + uint16_t _5822 = (uint16_t)(238); + _curvea0[823] = _5822; + uint16_t _5823 = (uint16_t)(238); + _curvea0[824] = _5823; + uint16_t _5824 = (uint16_t)(238); + _curvea0[825] = _5824; + uint16_t _5825 = (uint16_t)(238); + _curvea0[826] = _5825; + uint16_t _5826 = (uint16_t)(238); + _curvea0[827] = _5826; + uint16_t _5827 = (uint16_t)(238); + _curvea0[828] = _5827; + uint16_t _5828 = (uint16_t)(238); + _curvea0[829] = _5828; + uint16_t _5829 = (uint16_t)(238); + _curvea0[830] = _5829; + uint16_t _5830 = (uint16_t)(239); + _curvea0[831] = _5830; + uint16_t _5831 = (uint16_t)(239); + _curvea0[832] = _5831; + uint16_t _5832 = (uint16_t)(239); + _curvea0[833] = _5832; + uint16_t _5833 = (uint16_t)(239); + _curvea0[834] = _5833; + uint16_t _5834 = (uint16_t)(239); + _curvea0[835] = _5834; + uint16_t _5835 = (uint16_t)(239); + _curvea0[836] = _5835; + uint16_t _5836 = (uint16_t)(239); + _curvea0[837] = _5836; + uint16_t _5837 = (uint16_t)(239); + _curvea0[838] = _5837; + uint16_t _5838 = (uint16_t)(239); + _curvea0[839] = _5838; + uint16_t _5839 = (uint16_t)(239); + _curvea0[840] = _5839; + uint16_t _5840 = (uint16_t)(240); + _curvea0[841] = _5840; + uint16_t _5841 = (uint16_t)(240); + _curvea0[842] = _5841; + uint16_t _5842 = (uint16_t)(240); + _curvea0[843] = _5842; + uint16_t _5843 = (uint16_t)(240); + _curvea0[844] = _5843; + uint16_t _5844 = (uint16_t)(240); + _curvea0[845] = _5844; + uint16_t _5845 = (uint16_t)(240); + _curvea0[846] = _5845; + uint16_t _5846 = (uint16_t)(240); + _curvea0[847] = _5846; + uint16_t _5847 = (uint16_t)(240); + _curvea0[848] = _5847; + uint16_t _5848 = (uint16_t)(240); + _curvea0[849] = _5848; + uint16_t _5849 = (uint16_t)(240); + _curvea0[850] = _5849; + uint16_t _5850 = (uint16_t)(241); + _curvea0[851] = _5850; + uint16_t _5851 = (uint16_t)(241); + _curvea0[852] = _5851; + uint16_t _5852 = (uint16_t)(241); + _curvea0[853] = _5852; + uint16_t _5853 = (uint16_t)(241); + _curvea0[854] = _5853; + uint16_t _5854 = (uint16_t)(241); + _curvea0[855] = _5854; + uint16_t _5855 = (uint16_t)(241); + _curvea0[856] = _5855; + uint16_t _5856 = (uint16_t)(241); + _curvea0[857] = _5856; + uint16_t _5857 = (uint16_t)(241); + _curvea0[858] = _5857; + uint16_t _5858 = (uint16_t)(241); + _curvea0[859] = _5858; + uint16_t _5859 = (uint16_t)(241); + _curvea0[860] = _5859; + uint16_t _5860 = (uint16_t)(242); + _curvea0[861] = _5860; + uint16_t _5861 = (uint16_t)(242); + _curvea0[862] = _5861; + uint16_t _5862 = (uint16_t)(242); + _curvea0[863] = _5862; + uint16_t _5863 = (uint16_t)(242); + _curvea0[864] = _5863; + uint16_t _5864 = (uint16_t)(242); + _curvea0[865] = _5864; + uint16_t _5865 = (uint16_t)(242); + _curvea0[866] = _5865; + uint16_t _5866 = (uint16_t)(242); + _curvea0[867] = _5866; + uint16_t _5867 = (uint16_t)(242); + _curvea0[868] = _5867; + uint16_t _5868 = (uint16_t)(242); + _curvea0[869] = _5868; + uint16_t _5869 = (uint16_t)(242); + _curvea0[870] = _5869; + uint16_t _5870 = (uint16_t)(243); + _curvea0[871] = _5870; + uint16_t _5871 = (uint16_t)(243); + _curvea0[872] = _5871; + uint16_t _5872 = (uint16_t)(243); + _curvea0[873] = _5872; + uint16_t _5873 = (uint16_t)(243); + _curvea0[874] = _5873; + uint16_t _5874 = (uint16_t)(243); + _curvea0[875] = _5874; + uint16_t _5875 = (uint16_t)(243); + _curvea0[876] = _5875; + uint16_t _5876 = (uint16_t)(243); + _curvea0[877] = _5876; + uint16_t _5877 = (uint16_t)(243); + _curvea0[878] = _5877; + uint16_t _5878 = (uint16_t)(243); + _curvea0[879] = _5878; + uint16_t _5879 = (uint16_t)(243); + _curvea0[880] = _5879; + uint16_t _5880 = (uint16_t)(244); + _curvea0[881] = _5880; + uint16_t _5881 = (uint16_t)(244); + _curvea0[882] = _5881; + uint16_t _5882 = (uint16_t)(244); + _curvea0[883] = _5882; + uint16_t _5883 = (uint16_t)(244); + _curvea0[884] = _5883; + uint16_t _5884 = (uint16_t)(244); + _curvea0[885] = _5884; + uint16_t _5885 = (uint16_t)(244); + _curvea0[886] = _5885; + uint16_t _5886 = (uint16_t)(244); + _curvea0[887] = _5886; + uint16_t _5887 = (uint16_t)(244); + _curvea0[888] = _5887; + uint16_t _5888 = (uint16_t)(244); + _curvea0[889] = _5888; + uint16_t _5889 = (uint16_t)(244); + _curvea0[890] = _5889; + uint16_t _5890 = (uint16_t)(244); + _curvea0[891] = _5890; + uint16_t _5891 = (uint16_t)(245); + _curvea0[892] = _5891; + uint16_t _5892 = (uint16_t)(245); + _curvea0[893] = _5892; + uint16_t _5893 = (uint16_t)(245); + _curvea0[894] = _5893; + uint16_t _5894 = (uint16_t)(245); + _curvea0[895] = _5894; + uint16_t _5895 = (uint16_t)(245); + _curvea0[896] = _5895; + uint16_t _5896 = (uint16_t)(245); + _curvea0[897] = _5896; + uint16_t _5897 = (uint16_t)(245); + _curvea0[898] = _5897; + uint16_t _5898 = (uint16_t)(245); + _curvea0[899] = _5898; + uint16_t _5899 = (uint16_t)(245); + _curvea0[900] = _5899; + uint16_t _5900 = (uint16_t)(245); + _curvea0[901] = _5900; + uint16_t _5901 = (uint16_t)(245); + _curvea0[902] = _5901; + uint16_t _5902 = (uint16_t)(246); + _curvea0[903] = _5902; + uint16_t _5903 = (uint16_t)(246); + _curvea0[904] = _5903; + uint16_t _5904 = (uint16_t)(246); + _curvea0[905] = _5904; + uint16_t _5905 = (uint16_t)(246); + _curvea0[906] = _5905; + uint16_t _5906 = (uint16_t)(246); + _curvea0[907] = _5906; + uint16_t _5907 = (uint16_t)(246); + _curvea0[908] = _5907; + uint16_t _5908 = (uint16_t)(246); + _curvea0[909] = _5908; + uint16_t _5909 = (uint16_t)(246); + _curvea0[910] = _5909; + uint16_t _5910 = (uint16_t)(246); + _curvea0[911] = _5910; + uint16_t _5911 = (uint16_t)(246); + _curvea0[912] = _5911; + uint16_t _5912 = (uint16_t)(246); + _curvea0[913] = _5912; + uint16_t _5913 = (uint16_t)(247); + _curvea0[914] = _5913; + uint16_t _5914 = (uint16_t)(247); + _curvea0[915] = _5914; + uint16_t _5915 = (uint16_t)(247); + _curvea0[916] = _5915; + uint16_t _5916 = (uint16_t)(247); + _curvea0[917] = _5916; + uint16_t _5917 = (uint16_t)(247); + _curvea0[918] = _5917; + uint16_t _5918 = (uint16_t)(247); + _curvea0[919] = _5918; + uint16_t _5919 = (uint16_t)(247); + _curvea0[920] = _5919; + uint16_t _5920 = (uint16_t)(247); + _curvea0[921] = _5920; + uint16_t _5921 = (uint16_t)(247); + _curvea0[922] = _5921; + uint16_t _5922 = (uint16_t)(247); + _curvea0[923] = _5922; + uint16_t _5923 = (uint16_t)(247); + _curvea0[924] = _5923; + uint16_t _5924 = (uint16_t)(248); + _curvea0[925] = _5924; + uint16_t _5925 = (uint16_t)(248); + _curvea0[926] = _5925; + uint16_t _5926 = (uint16_t)(248); + _curvea0[927] = _5926; + uint16_t _5927 = (uint16_t)(248); + _curvea0[928] = _5927; + uint16_t _5928 = (uint16_t)(248); + _curvea0[929] = _5928; + uint16_t _5929 = (uint16_t)(248); + _curvea0[930] = _5929; + uint16_t _5930 = (uint16_t)(248); + _curvea0[931] = _5930; + uint16_t _5931 = (uint16_t)(248); + _curvea0[932] = _5931; + uint16_t _5932 = (uint16_t)(248); + _curvea0[933] = _5932; + uint16_t _5933 = (uint16_t)(248); + _curvea0[934] = _5933; + uint16_t _5934 = (uint16_t)(248); + _curvea0[935] = _5934; + uint16_t _5935 = (uint16_t)(249); + _curvea0[936] = _5935; + uint16_t _5936 = (uint16_t)(249); + _curvea0[937] = _5936; + uint16_t _5937 = (uint16_t)(249); + _curvea0[938] = _5937; + uint16_t _5938 = (uint16_t)(249); + _curvea0[939] = _5938; + uint16_t _5939 = (uint16_t)(249); + _curvea0[940] = _5939; + uint16_t _5940 = (uint16_t)(249); + _curvea0[941] = _5940; + uint16_t _5941 = (uint16_t)(249); + _curvea0[942] = _5941; + uint16_t _5942 = (uint16_t)(249); + _curvea0[943] = _5942; + uint16_t _5943 = (uint16_t)(249); + _curvea0[944] = _5943; + uint16_t _5944 = (uint16_t)(249); + _curvea0[945] = _5944; + uint16_t _5945 = (uint16_t)(249); + _curvea0[946] = _5945; + uint16_t _5946 = (uint16_t)(249); + _curvea0[947] = _5946; + uint16_t _5947 = (uint16_t)(250); + _curvea0[948] = _5947; + uint16_t _5948 = (uint16_t)(250); + _curvea0[949] = _5948; + uint16_t _5949 = (uint16_t)(250); + _curvea0[950] = _5949; + uint16_t _5950 = (uint16_t)(250); + _curvea0[951] = _5950; + uint16_t _5951 = (uint16_t)(250); + _curvea0[952] = _5951; + uint16_t _5952 = (uint16_t)(250); + _curvea0[953] = _5952; + uint16_t _5953 = (uint16_t)(250); + _curvea0[954] = _5953; + uint16_t _5954 = (uint16_t)(250); + _curvea0[955] = _5954; + uint16_t _5955 = (uint16_t)(250); + _curvea0[956] = _5955; + uint16_t _5956 = (uint16_t)(250); + _curvea0[957] = _5956; + uint16_t _5957 = (uint16_t)(250); + _curvea0[958] = _5957; + uint16_t _5958 = (uint16_t)(250); + _curvea0[959] = _5958; + uint16_t _5959 = (uint16_t)(251); + _curvea0[960] = _5959; + uint16_t _5960 = (uint16_t)(251); + _curvea0[961] = _5960; + uint16_t _5961 = (uint16_t)(251); + _curvea0[962] = _5961; + uint16_t _5962 = (uint16_t)(251); + _curvea0[963] = _5962; + uint16_t _5963 = (uint16_t)(251); + _curvea0[964] = _5963; + uint16_t _5964 = (uint16_t)(251); + _curvea0[965] = _5964; + uint16_t _5965 = (uint16_t)(251); + _curvea0[966] = _5965; + uint16_t _5966 = (uint16_t)(251); + _curvea0[967] = _5966; + uint16_t _5967 = (uint16_t)(251); + _curvea0[968] = _5967; + uint16_t _5968 = (uint16_t)(251); + _curvea0[969] = _5968; + uint16_t _5969 = (uint16_t)(251); + _curvea0[970] = _5969; + uint16_t _5970 = (uint16_t)(251); + _curvea0[971] = _5970; + uint16_t _5971 = (uint16_t)(252); + _curvea0[972] = _5971; + uint16_t _5972 = (uint16_t)(252); + _curvea0[973] = _5972; + uint16_t _5973 = (uint16_t)(252); + _curvea0[974] = _5973; + uint16_t _5974 = (uint16_t)(252); + _curvea0[975] = _5974; + uint16_t _5975 = (uint16_t)(252); + _curvea0[976] = _5975; + uint16_t _5976 = (uint16_t)(252); + _curvea0[977] = _5976; + uint16_t _5977 = (uint16_t)(252); + _curvea0[978] = _5977; + uint16_t _5978 = (uint16_t)(252); + _curvea0[979] = _5978; + uint16_t _5979 = (uint16_t)(252); + _curvea0[980] = _5979; + uint16_t _5980 = (uint16_t)(252); + _curvea0[981] = _5980; + uint16_t _5981 = (uint16_t)(252); + _curvea0[982] = _5981; + uint16_t _5982 = (uint16_t)(252); + _curvea0[983] = _5982; + uint16_t _5983 = (uint16_t)(252); + _curvea0[984] = _5983; + uint16_t _5984 = (uint16_t)(253); + _curvea0[985] = _5984; + uint16_t _5985 = (uint16_t)(253); + _curvea0[986] = _5985; + uint16_t _5986 = (uint16_t)(253); + _curvea0[987] = _5986; + uint16_t _5987 = (uint16_t)(253); + _curvea0[988] = _5987; + uint16_t _5988 = (uint16_t)(253); + _curvea0[989] = _5988; + uint16_t _5989 = (uint16_t)(253); + _curvea0[990] = _5989; + uint16_t _5990 = (uint16_t)(253); + _curvea0[991] = _5990; + uint16_t _5991 = (uint16_t)(253); + _curvea0[992] = _5991; + uint16_t _5992 = (uint16_t)(253); + _curvea0[993] = _5992; + uint16_t _5993 = (uint16_t)(253); + _curvea0[994] = _5993; + uint16_t _5994 = (uint16_t)(253); + _curvea0[995] = _5994; + uint16_t _5995 = (uint16_t)(253); + _curvea0[996] = _5995; + uint16_t _5996 = (uint16_t)(253); + _curvea0[997] = _5996; + uint16_t _5997 = (uint16_t)(254); + _curvea0[998] = _5997; + uint16_t _5998 = (uint16_t)(254); + _curvea0[999] = _5998; + uint16_t _5999 = (uint16_t)(254); + _curvea0[1000] = _5999; + uint16_t _6000 = (uint16_t)(254); + _curvea0[1001] = _6000; + uint16_t _6001 = (uint16_t)(254); + _curvea0[1002] = _6001; + uint16_t _6002 = (uint16_t)(254); + _curvea0[1003] = _6002; + uint16_t _6003 = (uint16_t)(254); + _curvea0[1004] = _6003; + uint16_t _6004 = (uint16_t)(254); + _curvea0[1005] = _6004; + uint16_t _6005 = (uint16_t)(254); + _curvea0[1006] = _6005; + uint16_t _6006 = (uint16_t)(254); + _curvea0[1007] = _6006; + uint16_t _6007 = (uint16_t)(254); + _curvea0[1008] = _6007; + uint16_t _6008 = (uint16_t)(254); + _curvea0[1009] = _6008; + uint16_t _6009 = (uint16_t)(254); + _curvea0[1010] = _6009; + uint16_t _6010 = (uint16_t)(255); + _curvea0[1011] = _6010; + uint16_t _6011 = (uint16_t)(255); + _curvea0[1012] = _6011; + uint16_t _6012 = (uint16_t)(255); + _curvea0[1013] = _6012; + uint16_t _6013 = (uint16_t)(255); + _curvea0[1014] = _6013; + uint16_t _6014 = (uint16_t)(255); + _curvea0[1015] = _6014; + uint16_t _6015 = (uint16_t)(255); + _curvea0[1016] = _6015; + uint16_t _6016 = (uint16_t)(255); + _curvea0[1017] = _6016; + uint16_t _6017 = (uint16_t)(255); + _curvea0[1018] = _6017; + uint16_t _6018 = (uint16_t)(255); + _curvea0[1019] = _6018; + uint16_t _6019 = (uint16_t)(255); + _curvea0[1020] = _6019; + uint16_t _6020 = (uint16_t)(255); + _curvea0[1021] = _6020; + uint16_t _6021 = (uint16_t)(255); + _curvea0[1022] = _6021; + uint16_t _6022 = (uint16_t)(255); + _curvea0[1023] = _6022; + + int16_t _6023 = (int16_t)(1023); + int16_t _6024 = min(_corrected_stencil_2, _6023); + int16_t _6025 = (int16_t)(0); + int16_t _6026 = max(_6024, _6025); + uint16_t _6027 = (uint16_t)(_6026); + int32_t _6028 = (int32_t)(_6027); + uint16_t _6029 = ((const uint16_t *)_curvea0)[_6028]; + return _6029; +} + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_2(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_3 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _6046 = (uint16_t)(0); + _curvea0[0] = _6046; + uint16_t _6047 = (uint16_t)(4); + _curvea0[1] = _6047; + uint16_t _6048 = (uint16_t)(7); + _curvea0[2] = _6048; + uint16_t _6049 = (uint16_t)(8); + _curvea0[3] = _6049; + uint16_t _6050 = (uint16_t)(10); + _curvea0[4] = _6050; + uint16_t _6051 = (uint16_t)(11); + _curvea0[5] = _6051; + uint16_t _6052 = (uint16_t)(12); + _curvea0[6] = _6052; + uint16_t _6053 = (uint16_t)(13); + _curvea0[7] = _6053; + uint16_t _6054 = (uint16_t)(14); + _curvea0[8] = _6054; + uint16_t _6055 = (uint16_t)(15); + _curvea0[9] = _6055; + uint16_t _6056 = (uint16_t)(16); + _curvea0[10] = _6056; + uint16_t _6057 = (uint16_t)(17); + _curvea0[11] = _6057; + uint16_t _6058 = (uint16_t)(18); + _curvea0[12] = _6058; + uint16_t _6059 = (uint16_t)(19); + _curvea0[13] = _6059; + uint16_t _6060 = (uint16_t)(20); + _curvea0[14] = _6060; + uint16_t _6061 = (uint16_t)(21); + _curvea0[15] = _6061; + uint16_t _6062 = (uint16_t)(22); + _curvea0[16] = _6062; + uint16_t _6063 = (uint16_t)(22); + _curvea0[17] = _6063; + uint16_t _6064 = (uint16_t)(23); + _curvea0[18] = _6064; + uint16_t _6065 = (uint16_t)(24); + _curvea0[19] = _6065; + uint16_t _6066 = (uint16_t)(25); + _curvea0[20] = _6066; + uint16_t _6067 = (uint16_t)(25); + _curvea0[21] = _6067; + uint16_t _6068 = (uint16_t)(26); + _curvea0[22] = _6068; + uint16_t _6069 = (uint16_t)(27); + _curvea0[23] = _6069; + uint16_t _6070 = (uint16_t)(27); + _curvea0[24] = _6070; + uint16_t _6071 = (uint16_t)(28); + _curvea0[25] = _6071; + uint16_t _6072 = (uint16_t)(29); + _curvea0[26] = _6072; + uint16_t _6073 = (uint16_t)(29); + _curvea0[27] = _6073; + uint16_t _6074 = (uint16_t)(30); + _curvea0[28] = _6074; + uint16_t _6075 = (uint16_t)(31); + _curvea0[29] = _6075; + uint16_t _6076 = (uint16_t)(31); + _curvea0[30] = _6076; + uint16_t _6077 = (uint16_t)(32); + _curvea0[31] = _6077; + uint16_t _6078 = (uint16_t)(33); + _curvea0[32] = _6078; + uint16_t _6079 = (uint16_t)(33); + _curvea0[33] = _6079; + uint16_t _6080 = (uint16_t)(34); + _curvea0[34] = _6080; + uint16_t _6081 = (uint16_t)(34); + _curvea0[35] = _6081; + uint16_t _6082 = (uint16_t)(35); + _curvea0[36] = _6082; + uint16_t _6083 = (uint16_t)(36); + _curvea0[37] = _6083; + uint16_t _6084 = (uint16_t)(36); + _curvea0[38] = _6084; + uint16_t _6085 = (uint16_t)(37); + _curvea0[39] = _6085; + uint16_t _6086 = (uint16_t)(37); + _curvea0[40] = _6086; + uint16_t _6087 = (uint16_t)(38); + _curvea0[41] = _6087; + uint16_t _6088 = (uint16_t)(39); + _curvea0[42] = _6088; + uint16_t _6089 = (uint16_t)(39); + _curvea0[43] = _6089; + uint16_t _6090 = (uint16_t)(40); + _curvea0[44] = _6090; + uint16_t _6091 = (uint16_t)(40); + _curvea0[45] = _6091; + uint16_t _6092 = (uint16_t)(41); + _curvea0[46] = _6092; + uint16_t _6093 = (uint16_t)(41); + _curvea0[47] = _6093; + uint16_t _6094 = (uint16_t)(42); + _curvea0[48] = _6094; + uint16_t _6095 = (uint16_t)(42); + _curvea0[49] = _6095; + uint16_t _6096 = (uint16_t)(43); + _curvea0[50] = _6096; + uint16_t _6097 = (uint16_t)(44); + _curvea0[51] = _6097; + uint16_t _6098 = (uint16_t)(44); + _curvea0[52] = _6098; + uint16_t _6099 = (uint16_t)(45); + _curvea0[53] = _6099; + uint16_t _6100 = (uint16_t)(45); + _curvea0[54] = _6100; + uint16_t _6101 = (uint16_t)(46); + _curvea0[55] = _6101; + uint16_t _6102 = (uint16_t)(46); + _curvea0[56] = _6102; + uint16_t _6103 = (uint16_t)(47); + _curvea0[57] = _6103; + uint16_t _6104 = (uint16_t)(47); + _curvea0[58] = _6104; + uint16_t _6105 = (uint16_t)(48); + _curvea0[59] = _6105; + uint16_t _6106 = (uint16_t)(48); + _curvea0[60] = _6106; + uint16_t _6107 = (uint16_t)(49); + _curvea0[61] = _6107; + uint16_t _6108 = (uint16_t)(49); + _curvea0[62] = _6108; + uint16_t _6109 = (uint16_t)(50); + _curvea0[63] = _6109; + uint16_t _6110 = (uint16_t)(50); + _curvea0[64] = _6110; + uint16_t _6111 = (uint16_t)(51); + _curvea0[65] = _6111; + uint16_t _6112 = (uint16_t)(51); + _curvea0[66] = _6112; + uint16_t _6113 = (uint16_t)(52); + _curvea0[67] = _6113; + uint16_t _6114 = (uint16_t)(52); + _curvea0[68] = _6114; + uint16_t _6115 = (uint16_t)(53); + _curvea0[69] = _6115; + uint16_t _6116 = (uint16_t)(53); + _curvea0[70] = _6116; + uint16_t _6117 = (uint16_t)(54); + _curvea0[71] = _6117; + uint16_t _6118 = (uint16_t)(54); + _curvea0[72] = _6118; + uint16_t _6119 = (uint16_t)(55); + _curvea0[73] = _6119; + uint16_t _6120 = (uint16_t)(55); + _curvea0[74] = _6120; + uint16_t _6121 = (uint16_t)(56); + _curvea0[75] = _6121; + uint16_t _6122 = (uint16_t)(56); + _curvea0[76] = _6122; + uint16_t _6123 = (uint16_t)(57); + _curvea0[77] = _6123; + uint16_t _6124 = (uint16_t)(57); + _curvea0[78] = _6124; + uint16_t _6125 = (uint16_t)(58); + _curvea0[79] = _6125; + uint16_t _6126 = (uint16_t)(58); + _curvea0[80] = _6126; + uint16_t _6127 = (uint16_t)(58); + _curvea0[81] = _6127; + uint16_t _6128 = (uint16_t)(59); + _curvea0[82] = _6128; + uint16_t _6129 = (uint16_t)(59); + _curvea0[83] = _6129; + uint16_t _6130 = (uint16_t)(60); + _curvea0[84] = _6130; + uint16_t _6131 = (uint16_t)(60); + _curvea0[85] = _6131; + uint16_t _6132 = (uint16_t)(61); + _curvea0[86] = _6132; + uint16_t _6133 = (uint16_t)(61); + _curvea0[87] = _6133; + uint16_t _6134 = (uint16_t)(62); + _curvea0[88] = _6134; + uint16_t _6135 = (uint16_t)(62); + _curvea0[89] = _6135; + uint16_t _6136 = (uint16_t)(63); + _curvea0[90] = _6136; + uint16_t _6137 = (uint16_t)(63); + _curvea0[91] = _6137; + uint16_t _6138 = (uint16_t)(64); + _curvea0[92] = _6138; + uint16_t _6139 = (uint16_t)(64); + _curvea0[93] = _6139; + uint16_t _6140 = (uint16_t)(64); + _curvea0[94] = _6140; + uint16_t _6141 = (uint16_t)(65); + _curvea0[95] = _6141; + uint16_t _6142 = (uint16_t)(65); + _curvea0[96] = _6142; + uint16_t _6143 = (uint16_t)(66); + _curvea0[97] = _6143; + uint16_t _6144 = (uint16_t)(66); + _curvea0[98] = _6144; + uint16_t _6145 = (uint16_t)(67); + _curvea0[99] = _6145; + uint16_t _6146 = (uint16_t)(67); + _curvea0[100] = _6146; + uint16_t _6147 = (uint16_t)(68); + _curvea0[101] = _6147; + uint16_t _6148 = (uint16_t)(68); + _curvea0[102] = _6148; + uint16_t _6149 = (uint16_t)(68); + _curvea0[103] = _6149; + uint16_t _6150 = (uint16_t)(69); + _curvea0[104] = _6150; + uint16_t _6151 = (uint16_t)(69); + _curvea0[105] = _6151; + uint16_t _6152 = (uint16_t)(70); + _curvea0[106] = _6152; + uint16_t _6153 = (uint16_t)(70); + _curvea0[107] = _6153; + uint16_t _6154 = (uint16_t)(71); + _curvea0[108] = _6154; + uint16_t _6155 = (uint16_t)(71); + _curvea0[109] = _6155; + uint16_t _6156 = (uint16_t)(71); + _curvea0[110] = _6156; + uint16_t _6157 = (uint16_t)(72); + _curvea0[111] = _6157; + uint16_t _6158 = (uint16_t)(72); + _curvea0[112] = _6158; + uint16_t _6159 = (uint16_t)(73); + _curvea0[113] = _6159; + uint16_t _6160 = (uint16_t)(73); + _curvea0[114] = _6160; + uint16_t _6161 = (uint16_t)(74); + _curvea0[115] = _6161; + uint16_t _6162 = (uint16_t)(74); + _curvea0[116] = _6162; + uint16_t _6163 = (uint16_t)(74); + _curvea0[117] = _6163; + uint16_t _6164 = (uint16_t)(75); + _curvea0[118] = _6164; + uint16_t _6165 = (uint16_t)(75); + _curvea0[119] = _6165; + uint16_t _6166 = (uint16_t)(76); + _curvea0[120] = _6166; + uint16_t _6167 = (uint16_t)(76); + _curvea0[121] = _6167; + uint16_t _6168 = (uint16_t)(77); + _curvea0[122] = _6168; + uint16_t _6169 = (uint16_t)(77); + _curvea0[123] = _6169; + uint16_t _6170 = (uint16_t)(77); + _curvea0[124] = _6170; + uint16_t _6171 = (uint16_t)(78); + _curvea0[125] = _6171; + uint16_t _6172 = (uint16_t)(78); + _curvea0[126] = _6172; + uint16_t _6173 = (uint16_t)(79); + _curvea0[127] = _6173; + uint16_t _6174 = (uint16_t)(79); + _curvea0[128] = _6174; + uint16_t _6175 = (uint16_t)(79); + _curvea0[129] = _6175; + uint16_t _6176 = (uint16_t)(80); + _curvea0[130] = _6176; + uint16_t _6177 = (uint16_t)(80); + _curvea0[131] = _6177; + uint16_t _6178 = (uint16_t)(81); + _curvea0[132] = _6178; + uint16_t _6179 = (uint16_t)(81); + _curvea0[133] = _6179; + uint16_t _6180 = (uint16_t)(82); + _curvea0[134] = _6180; + uint16_t _6181 = (uint16_t)(82); + _curvea0[135] = _6181; + uint16_t _6182 = (uint16_t)(82); + _curvea0[136] = _6182; + uint16_t _6183 = (uint16_t)(83); + _curvea0[137] = _6183; + uint16_t _6184 = (uint16_t)(83); + _curvea0[138] = _6184; + uint16_t _6185 = (uint16_t)(84); + _curvea0[139] = _6185; + uint16_t _6186 = (uint16_t)(84); + _curvea0[140] = _6186; + uint16_t _6187 = (uint16_t)(84); + _curvea0[141] = _6187; + uint16_t _6188 = (uint16_t)(85); + _curvea0[142] = _6188; + uint16_t _6189 = (uint16_t)(85); + _curvea0[143] = _6189; + uint16_t _6190 = (uint16_t)(86); + _curvea0[144] = _6190; + uint16_t _6191 = (uint16_t)(86); + _curvea0[145] = _6191; + uint16_t _6192 = (uint16_t)(86); + _curvea0[146] = _6192; + uint16_t _6193 = (uint16_t)(87); + _curvea0[147] = _6193; + uint16_t _6194 = (uint16_t)(87); + _curvea0[148] = _6194; + uint16_t _6195 = (uint16_t)(88); + _curvea0[149] = _6195; + uint16_t _6196 = (uint16_t)(88); + _curvea0[150] = _6196; + uint16_t _6197 = (uint16_t)(88); + _curvea0[151] = _6197; + uint16_t _6198 = (uint16_t)(89); + _curvea0[152] = _6198; + uint16_t _6199 = (uint16_t)(89); + _curvea0[153] = _6199; + uint16_t _6200 = (uint16_t)(90); + _curvea0[154] = _6200; + uint16_t _6201 = (uint16_t)(90); + _curvea0[155] = _6201; + uint16_t _6202 = (uint16_t)(90); + _curvea0[156] = _6202; + uint16_t _6203 = (uint16_t)(91); + _curvea0[157] = _6203; + uint16_t _6204 = (uint16_t)(91); + _curvea0[158] = _6204; + uint16_t _6205 = (uint16_t)(92); + _curvea0[159] = _6205; + uint16_t _6206 = (uint16_t)(92); + _curvea0[160] = _6206; + uint16_t _6207 = (uint16_t)(92); + _curvea0[161] = _6207; + uint16_t _6208 = (uint16_t)(93); + _curvea0[162] = _6208; + uint16_t _6209 = (uint16_t)(93); + _curvea0[163] = _6209; + uint16_t _6210 = (uint16_t)(93); + _curvea0[164] = _6210; + uint16_t _6211 = (uint16_t)(94); + _curvea0[165] = _6211; + uint16_t _6212 = (uint16_t)(94); + _curvea0[166] = _6212; + uint16_t _6213 = (uint16_t)(95); + _curvea0[167] = _6213; + uint16_t _6214 = (uint16_t)(95); + _curvea0[168] = _6214; + uint16_t _6215 = (uint16_t)(95); + _curvea0[169] = _6215; + uint16_t _6216 = (uint16_t)(96); + _curvea0[170] = _6216; + uint16_t _6217 = (uint16_t)(96); + _curvea0[171] = _6217; + uint16_t _6218 = (uint16_t)(97); + _curvea0[172] = _6218; + uint16_t _6219 = (uint16_t)(97); + _curvea0[173] = _6219; + uint16_t _6220 = (uint16_t)(97); + _curvea0[174] = _6220; + uint16_t _6221 = (uint16_t)(98); + _curvea0[175] = _6221; + uint16_t _6222 = (uint16_t)(98); + _curvea0[176] = _6222; + uint16_t _6223 = (uint16_t)(99); + _curvea0[177] = _6223; + uint16_t _6224 = (uint16_t)(99); + _curvea0[178] = _6224; + uint16_t _6225 = (uint16_t)(99); + _curvea0[179] = _6225; + uint16_t _6226 = (uint16_t)(100); + _curvea0[180] = _6226; + uint16_t _6227 = (uint16_t)(100); + _curvea0[181] = _6227; + uint16_t _6228 = (uint16_t)(100); + _curvea0[182] = _6228; + uint16_t _6229 = (uint16_t)(101); + _curvea0[183] = _6229; + uint16_t _6230 = (uint16_t)(101); + _curvea0[184] = _6230; + uint16_t _6231 = (uint16_t)(102); + _curvea0[185] = _6231; + uint16_t _6232 = (uint16_t)(102); + _curvea0[186] = _6232; + uint16_t _6233 = (uint16_t)(102); + _curvea0[187] = _6233; + uint16_t _6234 = (uint16_t)(103); + _curvea0[188] = _6234; + uint16_t _6235 = (uint16_t)(103); + _curvea0[189] = _6235; + uint16_t _6236 = (uint16_t)(103); + _curvea0[190] = _6236; + uint16_t _6237 = (uint16_t)(104); + _curvea0[191] = _6237; + uint16_t _6238 = (uint16_t)(104); + _curvea0[192] = _6238; + uint16_t _6239 = (uint16_t)(105); + _curvea0[193] = _6239; + uint16_t _6240 = (uint16_t)(105); + _curvea0[194] = _6240; + uint16_t _6241 = (uint16_t)(105); + _curvea0[195] = _6241; + uint16_t _6242 = (uint16_t)(106); + _curvea0[196] = _6242; + uint16_t _6243 = (uint16_t)(106); + _curvea0[197] = _6243; + uint16_t _6244 = (uint16_t)(106); + _curvea0[198] = _6244; + uint16_t _6245 = (uint16_t)(107); + _curvea0[199] = _6245; + uint16_t _6246 = (uint16_t)(107); + _curvea0[200] = _6246; + uint16_t _6247 = (uint16_t)(108); + _curvea0[201] = _6247; + uint16_t _6248 = (uint16_t)(108); + _curvea0[202] = _6248; + uint16_t _6249 = (uint16_t)(108); + _curvea0[203] = _6249; + uint16_t _6250 = (uint16_t)(109); + _curvea0[204] = _6250; + uint16_t _6251 = (uint16_t)(109); + _curvea0[205] = _6251; + uint16_t _6252 = (uint16_t)(109); + _curvea0[206] = _6252; + uint16_t _6253 = (uint16_t)(110); + _curvea0[207] = _6253; + uint16_t _6254 = (uint16_t)(110); + _curvea0[208] = _6254; + uint16_t _6255 = (uint16_t)(111); + _curvea0[209] = _6255; + uint16_t _6256 = (uint16_t)(111); + _curvea0[210] = _6256; + uint16_t _6257 = (uint16_t)(111); + _curvea0[211] = _6257; + uint16_t _6258 = (uint16_t)(112); + _curvea0[212] = _6258; + uint16_t _6259 = (uint16_t)(112); + _curvea0[213] = _6259; + uint16_t _6260 = (uint16_t)(112); + _curvea0[214] = _6260; + uint16_t _6261 = (uint16_t)(113); + _curvea0[215] = _6261; + uint16_t _6262 = (uint16_t)(113); + _curvea0[216] = _6262; + uint16_t _6263 = (uint16_t)(113); + _curvea0[217] = _6263; + uint16_t _6264 = (uint16_t)(114); + _curvea0[218] = _6264; + uint16_t _6265 = (uint16_t)(114); + _curvea0[219] = _6265; + uint16_t _6266 = (uint16_t)(115); + _curvea0[220] = _6266; + uint16_t _6267 = (uint16_t)(115); + _curvea0[221] = _6267; + uint16_t _6268 = (uint16_t)(115); + _curvea0[222] = _6268; + uint16_t _6269 = (uint16_t)(116); + _curvea0[223] = _6269; + uint16_t _6270 = (uint16_t)(116); + _curvea0[224] = _6270; + uint16_t _6271 = (uint16_t)(116); + _curvea0[225] = _6271; + uint16_t _6272 = (uint16_t)(117); + _curvea0[226] = _6272; + uint16_t _6273 = (uint16_t)(117); + _curvea0[227] = _6273; + uint16_t _6274 = (uint16_t)(117); + _curvea0[228] = _6274; + uint16_t _6275 = (uint16_t)(118); + _curvea0[229] = _6275; + uint16_t _6276 = (uint16_t)(118); + _curvea0[230] = _6276; + uint16_t _6277 = (uint16_t)(119); + _curvea0[231] = _6277; + uint16_t _6278 = (uint16_t)(119); + _curvea0[232] = _6278; + uint16_t _6279 = (uint16_t)(119); + _curvea0[233] = _6279; + uint16_t _6280 = (uint16_t)(120); + _curvea0[234] = _6280; + uint16_t _6281 = (uint16_t)(120); + _curvea0[235] = _6281; + uint16_t _6282 = (uint16_t)(120); + _curvea0[236] = _6282; + uint16_t _6283 = (uint16_t)(121); + _curvea0[237] = _6283; + uint16_t _6284 = (uint16_t)(121); + _curvea0[238] = _6284; + uint16_t _6285 = (uint16_t)(121); + _curvea0[239] = _6285; + uint16_t _6286 = (uint16_t)(122); + _curvea0[240] = _6286; + uint16_t _6287 = (uint16_t)(122); + _curvea0[241] = _6287; + uint16_t _6288 = (uint16_t)(123); + _curvea0[242] = _6288; + uint16_t _6289 = (uint16_t)(123); + _curvea0[243] = _6289; + uint16_t _6290 = (uint16_t)(123); + _curvea0[244] = _6290; + uint16_t _6291 = (uint16_t)(124); + _curvea0[245] = _6291; + uint16_t _6292 = (uint16_t)(124); + _curvea0[246] = _6292; + uint16_t _6293 = (uint16_t)(124); + _curvea0[247] = _6293; + uint16_t _6294 = (uint16_t)(125); + _curvea0[248] = _6294; + uint16_t _6295 = (uint16_t)(125); + _curvea0[249] = _6295; + uint16_t _6296 = (uint16_t)(125); + _curvea0[250] = _6296; + uint16_t _6297 = (uint16_t)(126); + _curvea0[251] = _6297; + uint16_t _6298 = (uint16_t)(126); + _curvea0[252] = _6298; + uint16_t _6299 = (uint16_t)(126); + _curvea0[253] = _6299; + uint16_t _6300 = (uint16_t)(127); + _curvea0[254] = _6300; + uint16_t _6301 = (uint16_t)(127); + _curvea0[255] = _6301; + uint16_t _6302 = (uint16_t)(128); + _curvea0[256] = _6302; + uint16_t _6303 = (uint16_t)(128); + _curvea0[257] = _6303; + uint16_t _6304 = (uint16_t)(128); + _curvea0[258] = _6304; + uint16_t _6305 = (uint16_t)(129); + _curvea0[259] = _6305; + uint16_t _6306 = (uint16_t)(129); + _curvea0[260] = _6306; + uint16_t _6307 = (uint16_t)(129); + _curvea0[261] = _6307; + uint16_t _6308 = (uint16_t)(130); + _curvea0[262] = _6308; + uint16_t _6309 = (uint16_t)(130); + _curvea0[263] = _6309; + uint16_t _6310 = (uint16_t)(130); + _curvea0[264] = _6310; + uint16_t _6311 = (uint16_t)(131); + _curvea0[265] = _6311; + uint16_t _6312 = (uint16_t)(131); + _curvea0[266] = _6312; + uint16_t _6313 = (uint16_t)(131); + _curvea0[267] = _6313; + uint16_t _6314 = (uint16_t)(132); + _curvea0[268] = _6314; + uint16_t _6315 = (uint16_t)(132); + _curvea0[269] = _6315; + uint16_t _6316 = (uint16_t)(132); + _curvea0[270] = _6316; + uint16_t _6317 = (uint16_t)(133); + _curvea0[271] = _6317; + uint16_t _6318 = (uint16_t)(133); + _curvea0[272] = _6318; + uint16_t _6319 = (uint16_t)(133); + _curvea0[273] = _6319; + uint16_t _6320 = (uint16_t)(134); + _curvea0[274] = _6320; + uint16_t _6321 = (uint16_t)(134); + _curvea0[275] = _6321; + uint16_t _6322 = (uint16_t)(134); + _curvea0[276] = _6322; + uint16_t _6323 = (uint16_t)(135); + _curvea0[277] = _6323; + uint16_t _6324 = (uint16_t)(135); + _curvea0[278] = _6324; + uint16_t _6325 = (uint16_t)(135); + _curvea0[279] = _6325; + uint16_t _6326 = (uint16_t)(136); + _curvea0[280] = _6326; + uint16_t _6327 = (uint16_t)(136); + _curvea0[281] = _6327; + uint16_t _6328 = (uint16_t)(136); + _curvea0[282] = _6328; + uint16_t _6329 = (uint16_t)(137); + _curvea0[283] = _6329; + uint16_t _6330 = (uint16_t)(137); + _curvea0[284] = _6330; + uint16_t _6331 = (uint16_t)(137); + _curvea0[285] = _6331; + uint16_t _6332 = (uint16_t)(138); + _curvea0[286] = _6332; + uint16_t _6333 = (uint16_t)(138); + _curvea0[287] = _6333; + uint16_t _6334 = (uint16_t)(138); + _curvea0[288] = _6334; + uint16_t _6335 = (uint16_t)(139); + _curvea0[289] = _6335; + uint16_t _6336 = (uint16_t)(139); + _curvea0[290] = _6336; + uint16_t _6337 = (uint16_t)(139); + _curvea0[291] = _6337; + uint16_t _6338 = (uint16_t)(140); + _curvea0[292] = _6338; + uint16_t _6339 = (uint16_t)(140); + _curvea0[293] = _6339; + uint16_t _6340 = (uint16_t)(140); + _curvea0[294] = _6340; + uint16_t _6341 = (uint16_t)(141); + _curvea0[295] = _6341; + uint16_t _6342 = (uint16_t)(141); + _curvea0[296] = _6342; + uint16_t _6343 = (uint16_t)(141); + _curvea0[297] = _6343; + uint16_t _6344 = (uint16_t)(141); + _curvea0[298] = _6344; + uint16_t _6345 = (uint16_t)(142); + _curvea0[299] = _6345; + uint16_t _6346 = (uint16_t)(142); + _curvea0[300] = _6346; + uint16_t _6347 = (uint16_t)(142); + _curvea0[301] = _6347; + uint16_t _6348 = (uint16_t)(143); + _curvea0[302] = _6348; + uint16_t _6349 = (uint16_t)(143); + _curvea0[303] = _6349; + uint16_t _6350 = (uint16_t)(143); + _curvea0[304] = _6350; + uint16_t _6351 = (uint16_t)(144); + _curvea0[305] = _6351; + uint16_t _6352 = (uint16_t)(144); + _curvea0[306] = _6352; + uint16_t _6353 = (uint16_t)(144); + _curvea0[307] = _6353; + uint16_t _6354 = (uint16_t)(145); + _curvea0[308] = _6354; + uint16_t _6355 = (uint16_t)(145); + _curvea0[309] = _6355; + uint16_t _6356 = (uint16_t)(145); + _curvea0[310] = _6356; + uint16_t _6357 = (uint16_t)(145); + _curvea0[311] = _6357; + uint16_t _6358 = (uint16_t)(146); + _curvea0[312] = _6358; + uint16_t _6359 = (uint16_t)(146); + _curvea0[313] = _6359; + uint16_t _6360 = (uint16_t)(146); + _curvea0[314] = _6360; + uint16_t _6361 = (uint16_t)(147); + _curvea0[315] = _6361; + uint16_t _6362 = (uint16_t)(147); + _curvea0[316] = _6362; + uint16_t _6363 = (uint16_t)(147); + _curvea0[317] = _6363; + uint16_t _6364 = (uint16_t)(148); + _curvea0[318] = _6364; + uint16_t _6365 = (uint16_t)(148); + _curvea0[319] = _6365; + uint16_t _6366 = (uint16_t)(148); + _curvea0[320] = _6366; + uint16_t _6367 = (uint16_t)(148); + _curvea0[321] = _6367; + uint16_t _6368 = (uint16_t)(149); + _curvea0[322] = _6368; + uint16_t _6369 = (uint16_t)(149); + _curvea0[323] = _6369; + uint16_t _6370 = (uint16_t)(149); + _curvea0[324] = _6370; + uint16_t _6371 = (uint16_t)(150); + _curvea0[325] = _6371; + uint16_t _6372 = (uint16_t)(150); + _curvea0[326] = _6372; + uint16_t _6373 = (uint16_t)(150); + _curvea0[327] = _6373; + uint16_t _6374 = (uint16_t)(150); + _curvea0[328] = _6374; + uint16_t _6375 = (uint16_t)(151); + _curvea0[329] = _6375; + uint16_t _6376 = (uint16_t)(151); + _curvea0[330] = _6376; + uint16_t _6377 = (uint16_t)(151); + _curvea0[331] = _6377; + uint16_t _6378 = (uint16_t)(152); + _curvea0[332] = _6378; + uint16_t _6379 = (uint16_t)(152); + _curvea0[333] = _6379; + uint16_t _6380 = (uint16_t)(152); + _curvea0[334] = _6380; + uint16_t _6381 = (uint16_t)(152); + _curvea0[335] = _6381; + uint16_t _6382 = (uint16_t)(153); + _curvea0[336] = _6382; + uint16_t _6383 = (uint16_t)(153); + _curvea0[337] = _6383; + uint16_t _6384 = (uint16_t)(153); + _curvea0[338] = _6384; + uint16_t _6385 = (uint16_t)(154); + _curvea0[339] = _6385; + uint16_t _6386 = (uint16_t)(154); + _curvea0[340] = _6386; + uint16_t _6387 = (uint16_t)(154); + _curvea0[341] = _6387; + uint16_t _6388 = (uint16_t)(154); + _curvea0[342] = _6388; + uint16_t _6389 = (uint16_t)(155); + _curvea0[343] = _6389; + uint16_t _6390 = (uint16_t)(155); + _curvea0[344] = _6390; + uint16_t _6391 = (uint16_t)(155); + _curvea0[345] = _6391; + uint16_t _6392 = (uint16_t)(156); + _curvea0[346] = _6392; + uint16_t _6393 = (uint16_t)(156); + _curvea0[347] = _6393; + uint16_t _6394 = (uint16_t)(156); + _curvea0[348] = _6394; + uint16_t _6395 = (uint16_t)(156); + _curvea0[349] = _6395; + uint16_t _6396 = (uint16_t)(157); + _curvea0[350] = _6396; + uint16_t _6397 = (uint16_t)(157); + _curvea0[351] = _6397; + uint16_t _6398 = (uint16_t)(157); + _curvea0[352] = _6398; + uint16_t _6399 = (uint16_t)(157); + _curvea0[353] = _6399; + uint16_t _6400 = (uint16_t)(158); + _curvea0[354] = _6400; + uint16_t _6401 = (uint16_t)(158); + _curvea0[355] = _6401; + uint16_t _6402 = (uint16_t)(158); + _curvea0[356] = _6402; + uint16_t _6403 = (uint16_t)(159); + _curvea0[357] = _6403; + uint16_t _6404 = (uint16_t)(159); + _curvea0[358] = _6404; + uint16_t _6405 = (uint16_t)(159); + _curvea0[359] = _6405; + uint16_t _6406 = (uint16_t)(159); + _curvea0[360] = _6406; + uint16_t _6407 = (uint16_t)(160); + _curvea0[361] = _6407; + uint16_t _6408 = (uint16_t)(160); + _curvea0[362] = _6408; + uint16_t _6409 = (uint16_t)(160); + _curvea0[363] = _6409; + uint16_t _6410 = (uint16_t)(160); + _curvea0[364] = _6410; + uint16_t _6411 = (uint16_t)(161); + _curvea0[365] = _6411; + uint16_t _6412 = (uint16_t)(161); + _curvea0[366] = _6412; + uint16_t _6413 = (uint16_t)(161); + _curvea0[367] = _6413; + uint16_t _6414 = (uint16_t)(161); + _curvea0[368] = _6414; + uint16_t _6415 = (uint16_t)(162); + _curvea0[369] = _6415; + uint16_t _6416 = (uint16_t)(162); + _curvea0[370] = _6416; + uint16_t _6417 = (uint16_t)(162); + _curvea0[371] = _6417; + uint16_t _6418 = (uint16_t)(162); + _curvea0[372] = _6418; + uint16_t _6419 = (uint16_t)(163); + _curvea0[373] = _6419; + uint16_t _6420 = (uint16_t)(163); + _curvea0[374] = _6420; + uint16_t _6421 = (uint16_t)(163); + _curvea0[375] = _6421; + uint16_t _6422 = (uint16_t)(163); + _curvea0[376] = _6422; + uint16_t _6423 = (uint16_t)(164); + _curvea0[377] = _6423; + uint16_t _6424 = (uint16_t)(164); + _curvea0[378] = _6424; + uint16_t _6425 = (uint16_t)(164); + _curvea0[379] = _6425; + uint16_t _6426 = (uint16_t)(164); + _curvea0[380] = _6426; + uint16_t _6427 = (uint16_t)(165); + _curvea0[381] = _6427; + uint16_t _6428 = (uint16_t)(165); + _curvea0[382] = _6428; + uint16_t _6429 = (uint16_t)(165); + _curvea0[383] = _6429; + uint16_t _6430 = (uint16_t)(166); + _curvea0[384] = _6430; + uint16_t _6431 = (uint16_t)(166); + _curvea0[385] = _6431; + uint16_t _6432 = (uint16_t)(166); + _curvea0[386] = _6432; + uint16_t _6433 = (uint16_t)(166); + _curvea0[387] = _6433; + uint16_t _6434 = (uint16_t)(167); + _curvea0[388] = _6434; + uint16_t _6435 = (uint16_t)(167); + _curvea0[389] = _6435; + uint16_t _6436 = (uint16_t)(167); + _curvea0[390] = _6436; + uint16_t _6437 = (uint16_t)(167); + _curvea0[391] = _6437; + uint16_t _6438 = (uint16_t)(167); + _curvea0[392] = _6438; + uint16_t _6439 = (uint16_t)(168); + _curvea0[393] = _6439; + uint16_t _6440 = (uint16_t)(168); + _curvea0[394] = _6440; + uint16_t _6441 = (uint16_t)(168); + _curvea0[395] = _6441; + uint16_t _6442 = (uint16_t)(168); + _curvea0[396] = _6442; + uint16_t _6443 = (uint16_t)(169); + _curvea0[397] = _6443; + uint16_t _6444 = (uint16_t)(169); + _curvea0[398] = _6444; + uint16_t _6445 = (uint16_t)(169); + _curvea0[399] = _6445; + uint16_t _6446 = (uint16_t)(169); + _curvea0[400] = _6446; + uint16_t _6447 = (uint16_t)(170); + _curvea0[401] = _6447; + uint16_t _6448 = (uint16_t)(170); + _curvea0[402] = _6448; + uint16_t _6449 = (uint16_t)(170); + _curvea0[403] = _6449; + uint16_t _6450 = (uint16_t)(170); + _curvea0[404] = _6450; + uint16_t _6451 = (uint16_t)(171); + _curvea0[405] = _6451; + uint16_t _6452 = (uint16_t)(171); + _curvea0[406] = _6452; + uint16_t _6453 = (uint16_t)(171); + _curvea0[407] = _6453; + uint16_t _6454 = (uint16_t)(171); + _curvea0[408] = _6454; + uint16_t _6455 = (uint16_t)(172); + _curvea0[409] = _6455; + uint16_t _6456 = (uint16_t)(172); + _curvea0[410] = _6456; + uint16_t _6457 = (uint16_t)(172); + _curvea0[411] = _6457; + uint16_t _6458 = (uint16_t)(172); + _curvea0[412] = _6458; + uint16_t _6459 = (uint16_t)(173); + _curvea0[413] = _6459; + uint16_t _6460 = (uint16_t)(173); + _curvea0[414] = _6460; + uint16_t _6461 = (uint16_t)(173); + _curvea0[415] = _6461; + uint16_t _6462 = (uint16_t)(173); + _curvea0[416] = _6462; + uint16_t _6463 = (uint16_t)(173); + _curvea0[417] = _6463; + uint16_t _6464 = (uint16_t)(174); + _curvea0[418] = _6464; + uint16_t _6465 = (uint16_t)(174); + _curvea0[419] = _6465; + uint16_t _6466 = (uint16_t)(174); + _curvea0[420] = _6466; + uint16_t _6467 = (uint16_t)(174); + _curvea0[421] = _6467; + uint16_t _6468 = (uint16_t)(175); + _curvea0[422] = _6468; + uint16_t _6469 = (uint16_t)(175); + _curvea0[423] = _6469; + uint16_t _6470 = (uint16_t)(175); + _curvea0[424] = _6470; + uint16_t _6471 = (uint16_t)(175); + _curvea0[425] = _6471; + uint16_t _6472 = (uint16_t)(176); + _curvea0[426] = _6472; + uint16_t _6473 = (uint16_t)(176); + _curvea0[427] = _6473; + uint16_t _6474 = (uint16_t)(176); + _curvea0[428] = _6474; + uint16_t _6475 = (uint16_t)(176); + _curvea0[429] = _6475; + uint16_t _6476 = (uint16_t)(176); + _curvea0[430] = _6476; + uint16_t _6477 = (uint16_t)(177); + _curvea0[431] = _6477; + uint16_t _6478 = (uint16_t)(177); + _curvea0[432] = _6478; + uint16_t _6479 = (uint16_t)(177); + _curvea0[433] = _6479; + uint16_t _6480 = (uint16_t)(177); + _curvea0[434] = _6480; + uint16_t _6481 = (uint16_t)(178); + _curvea0[435] = _6481; + uint16_t _6482 = (uint16_t)(178); + _curvea0[436] = _6482; + uint16_t _6483 = (uint16_t)(178); + _curvea0[437] = _6483; + uint16_t _6484 = (uint16_t)(178); + _curvea0[438] = _6484; + uint16_t _6485 = (uint16_t)(178); + _curvea0[439] = _6485; + uint16_t _6486 = (uint16_t)(179); + _curvea0[440] = _6486; + uint16_t _6487 = (uint16_t)(179); + _curvea0[441] = _6487; + uint16_t _6488 = (uint16_t)(179); + _curvea0[442] = _6488; + uint16_t _6489 = (uint16_t)(179); + _curvea0[443] = _6489; + uint16_t _6490 = (uint16_t)(180); + _curvea0[444] = _6490; + uint16_t _6491 = (uint16_t)(180); + _curvea0[445] = _6491; + uint16_t _6492 = (uint16_t)(180); + _curvea0[446] = _6492; + uint16_t _6493 = (uint16_t)(180); + _curvea0[447] = _6493; + uint16_t _6494 = (uint16_t)(180); + _curvea0[448] = _6494; + uint16_t _6495 = (uint16_t)(181); + _curvea0[449] = _6495; + uint16_t _6496 = (uint16_t)(181); + _curvea0[450] = _6496; + uint16_t _6497 = (uint16_t)(181); + _curvea0[451] = _6497; + uint16_t _6498 = (uint16_t)(181); + _curvea0[452] = _6498; + uint16_t _6499 = (uint16_t)(181); + _curvea0[453] = _6499; + uint16_t _6500 = (uint16_t)(182); + _curvea0[454] = _6500; + uint16_t _6501 = (uint16_t)(182); + _curvea0[455] = _6501; + uint16_t _6502 = (uint16_t)(182); + _curvea0[456] = _6502; + uint16_t _6503 = (uint16_t)(182); + _curvea0[457] = _6503; + uint16_t _6504 = (uint16_t)(183); + _curvea0[458] = _6504; + uint16_t _6505 = (uint16_t)(183); + _curvea0[459] = _6505; + uint16_t _6506 = (uint16_t)(183); + _curvea0[460] = _6506; + uint16_t _6507 = (uint16_t)(183); + _curvea0[461] = _6507; + uint16_t _6508 = (uint16_t)(183); + _curvea0[462] = _6508; + uint16_t _6509 = (uint16_t)(184); + _curvea0[463] = _6509; + uint16_t _6510 = (uint16_t)(184); + _curvea0[464] = _6510; + uint16_t _6511 = (uint16_t)(184); + _curvea0[465] = _6511; + uint16_t _6512 = (uint16_t)(184); + _curvea0[466] = _6512; + uint16_t _6513 = (uint16_t)(184); + _curvea0[467] = _6513; + uint16_t _6514 = (uint16_t)(185); + _curvea0[468] = _6514; + uint16_t _6515 = (uint16_t)(185); + _curvea0[469] = _6515; + uint16_t _6516 = (uint16_t)(185); + _curvea0[470] = _6516; + uint16_t _6517 = (uint16_t)(185); + _curvea0[471] = _6517; + uint16_t _6518 = (uint16_t)(185); + _curvea0[472] = _6518; + uint16_t _6519 = (uint16_t)(186); + _curvea0[473] = _6519; + uint16_t _6520 = (uint16_t)(186); + _curvea0[474] = _6520; + uint16_t _6521 = (uint16_t)(186); + _curvea0[475] = _6521; + uint16_t _6522 = (uint16_t)(186); + _curvea0[476] = _6522; + uint16_t _6523 = (uint16_t)(187); + _curvea0[477] = _6523; + uint16_t _6524 = (uint16_t)(187); + _curvea0[478] = _6524; + uint16_t _6525 = (uint16_t)(187); + _curvea0[479] = _6525; + uint16_t _6526 = (uint16_t)(187); + _curvea0[480] = _6526; + uint16_t _6527 = (uint16_t)(187); + _curvea0[481] = _6527; + uint16_t _6528 = (uint16_t)(188); + _curvea0[482] = _6528; + uint16_t _6529 = (uint16_t)(188); + _curvea0[483] = _6529; + uint16_t _6530 = (uint16_t)(188); + _curvea0[484] = _6530; + uint16_t _6531 = (uint16_t)(188); + _curvea0[485] = _6531; + uint16_t _6532 = (uint16_t)(188); + _curvea0[486] = _6532; + uint16_t _6533 = (uint16_t)(189); + _curvea0[487] = _6533; + uint16_t _6534 = (uint16_t)(189); + _curvea0[488] = _6534; + uint16_t _6535 = (uint16_t)(189); + _curvea0[489] = _6535; + uint16_t _6536 = (uint16_t)(189); + _curvea0[490] = _6536; + uint16_t _6537 = (uint16_t)(189); + _curvea0[491] = _6537; + uint16_t _6538 = (uint16_t)(190); + _curvea0[492] = _6538; + uint16_t _6539 = (uint16_t)(190); + _curvea0[493] = _6539; + uint16_t _6540 = (uint16_t)(190); + _curvea0[494] = _6540; + uint16_t _6541 = (uint16_t)(190); + _curvea0[495] = _6541; + uint16_t _6542 = (uint16_t)(190); + _curvea0[496] = _6542; + uint16_t _6543 = (uint16_t)(190); + _curvea0[497] = _6543; + uint16_t _6544 = (uint16_t)(191); + _curvea0[498] = _6544; + uint16_t _6545 = (uint16_t)(191); + _curvea0[499] = _6545; + uint16_t _6546 = (uint16_t)(191); + _curvea0[500] = _6546; + uint16_t _6547 = (uint16_t)(191); + _curvea0[501] = _6547; + uint16_t _6548 = (uint16_t)(191); + _curvea0[502] = _6548; + uint16_t _6549 = (uint16_t)(192); + _curvea0[503] = _6549; + uint16_t _6550 = (uint16_t)(192); + _curvea0[504] = _6550; + uint16_t _6551 = (uint16_t)(192); + _curvea0[505] = _6551; + uint16_t _6552 = (uint16_t)(192); + _curvea0[506] = _6552; + uint16_t _6553 = (uint16_t)(192); + _curvea0[507] = _6553; + uint16_t _6554 = (uint16_t)(193); + _curvea0[508] = _6554; + uint16_t _6555 = (uint16_t)(193); + _curvea0[509] = _6555; + uint16_t _6556 = (uint16_t)(193); + _curvea0[510] = _6556; + uint16_t _6557 = (uint16_t)(193); + _curvea0[511] = _6557; + uint16_t _6558 = (uint16_t)(193); + _curvea0[512] = _6558; + uint16_t _6559 = (uint16_t)(194); + _curvea0[513] = _6559; + uint16_t _6560 = (uint16_t)(194); + _curvea0[514] = _6560; + uint16_t _6561 = (uint16_t)(194); + _curvea0[515] = _6561; + uint16_t _6562 = (uint16_t)(194); + _curvea0[516] = _6562; + uint16_t _6563 = (uint16_t)(194); + _curvea0[517] = _6563; + uint16_t _6564 = (uint16_t)(195); + _curvea0[518] = _6564; + uint16_t _6565 = (uint16_t)(195); + _curvea0[519] = _6565; + uint16_t _6566 = (uint16_t)(195); + _curvea0[520] = _6566; + uint16_t _6567 = (uint16_t)(195); + _curvea0[521] = _6567; + uint16_t _6568 = (uint16_t)(195); + _curvea0[522] = _6568; + uint16_t _6569 = (uint16_t)(195); + _curvea0[523] = _6569; + uint16_t _6570 = (uint16_t)(196); + _curvea0[524] = _6570; + uint16_t _6571 = (uint16_t)(196); + _curvea0[525] = _6571; + uint16_t _6572 = (uint16_t)(196); + _curvea0[526] = _6572; + uint16_t _6573 = (uint16_t)(196); + _curvea0[527] = _6573; + uint16_t _6574 = (uint16_t)(196); + _curvea0[528] = _6574; + uint16_t _6575 = (uint16_t)(197); + _curvea0[529] = _6575; + uint16_t _6576 = (uint16_t)(197); + _curvea0[530] = _6576; + uint16_t _6577 = (uint16_t)(197); + _curvea0[531] = _6577; + uint16_t _6578 = (uint16_t)(197); + _curvea0[532] = _6578; + uint16_t _6579 = (uint16_t)(197); + _curvea0[533] = _6579; + uint16_t _6580 = (uint16_t)(197); + _curvea0[534] = _6580; + uint16_t _6581 = (uint16_t)(198); + _curvea0[535] = _6581; + uint16_t _6582 = (uint16_t)(198); + _curvea0[536] = _6582; + uint16_t _6583 = (uint16_t)(198); + _curvea0[537] = _6583; + uint16_t _6584 = (uint16_t)(198); + _curvea0[538] = _6584; + uint16_t _6585 = (uint16_t)(198); + _curvea0[539] = _6585; + uint16_t _6586 = (uint16_t)(199); + _curvea0[540] = _6586; + uint16_t _6587 = (uint16_t)(199); + _curvea0[541] = _6587; + uint16_t _6588 = (uint16_t)(199); + _curvea0[542] = _6588; + uint16_t _6589 = (uint16_t)(199); + _curvea0[543] = _6589; + uint16_t _6590 = (uint16_t)(199); + _curvea0[544] = _6590; + uint16_t _6591 = (uint16_t)(199); + _curvea0[545] = _6591; + uint16_t _6592 = (uint16_t)(200); + _curvea0[546] = _6592; + uint16_t _6593 = (uint16_t)(200); + _curvea0[547] = _6593; + uint16_t _6594 = (uint16_t)(200); + _curvea0[548] = _6594; + uint16_t _6595 = (uint16_t)(200); + _curvea0[549] = _6595; + uint16_t _6596 = (uint16_t)(200); + _curvea0[550] = _6596; + uint16_t _6597 = (uint16_t)(200); + _curvea0[551] = _6597; + uint16_t _6598 = (uint16_t)(201); + _curvea0[552] = _6598; + uint16_t _6599 = (uint16_t)(201); + _curvea0[553] = _6599; + uint16_t _6600 = (uint16_t)(201); + _curvea0[554] = _6600; + uint16_t _6601 = (uint16_t)(201); + _curvea0[555] = _6601; + uint16_t _6602 = (uint16_t)(201); + _curvea0[556] = _6602; + uint16_t _6603 = (uint16_t)(202); + _curvea0[557] = _6603; + uint16_t _6604 = (uint16_t)(202); + _curvea0[558] = _6604; + uint16_t _6605 = (uint16_t)(202); + _curvea0[559] = _6605; + uint16_t _6606 = (uint16_t)(202); + _curvea0[560] = _6606; + uint16_t _6607 = (uint16_t)(202); + _curvea0[561] = _6607; + uint16_t _6608 = (uint16_t)(202); + _curvea0[562] = _6608; + uint16_t _6609 = (uint16_t)(203); + _curvea0[563] = _6609; + uint16_t _6610 = (uint16_t)(203); + _curvea0[564] = _6610; + uint16_t _6611 = (uint16_t)(203); + _curvea0[565] = _6611; + uint16_t _6612 = (uint16_t)(203); + _curvea0[566] = _6612; + uint16_t _6613 = (uint16_t)(203); + _curvea0[567] = _6613; + uint16_t _6614 = (uint16_t)(203); + _curvea0[568] = _6614; + uint16_t _6615 = (uint16_t)(204); + _curvea0[569] = _6615; + uint16_t _6616 = (uint16_t)(204); + _curvea0[570] = _6616; + uint16_t _6617 = (uint16_t)(204); + _curvea0[571] = _6617; + uint16_t _6618 = (uint16_t)(204); + _curvea0[572] = _6618; + uint16_t _6619 = (uint16_t)(204); + _curvea0[573] = _6619; + uint16_t _6620 = (uint16_t)(204); + _curvea0[574] = _6620; + uint16_t _6621 = (uint16_t)(205); + _curvea0[575] = _6621; + uint16_t _6622 = (uint16_t)(205); + _curvea0[576] = _6622; + uint16_t _6623 = (uint16_t)(205); + _curvea0[577] = _6623; + uint16_t _6624 = (uint16_t)(205); + _curvea0[578] = _6624; + uint16_t _6625 = (uint16_t)(205); + _curvea0[579] = _6625; + uint16_t _6626 = (uint16_t)(205); + _curvea0[580] = _6626; + uint16_t _6627 = (uint16_t)(206); + _curvea0[581] = _6627; + uint16_t _6628 = (uint16_t)(206); + _curvea0[582] = _6628; + uint16_t _6629 = (uint16_t)(206); + _curvea0[583] = _6629; + uint16_t _6630 = (uint16_t)(206); + _curvea0[584] = _6630; + uint16_t _6631 = (uint16_t)(206); + _curvea0[585] = _6631; + uint16_t _6632 = (uint16_t)(206); + _curvea0[586] = _6632; + uint16_t _6633 = (uint16_t)(207); + _curvea0[587] = _6633; + uint16_t _6634 = (uint16_t)(207); + _curvea0[588] = _6634; + uint16_t _6635 = (uint16_t)(207); + _curvea0[589] = _6635; + uint16_t _6636 = (uint16_t)(207); + _curvea0[590] = _6636; + uint16_t _6637 = (uint16_t)(207); + _curvea0[591] = _6637; + uint16_t _6638 = (uint16_t)(207); + _curvea0[592] = _6638; + uint16_t _6639 = (uint16_t)(208); + _curvea0[593] = _6639; + uint16_t _6640 = (uint16_t)(208); + _curvea0[594] = _6640; + uint16_t _6641 = (uint16_t)(208); + _curvea0[595] = _6641; + uint16_t _6642 = (uint16_t)(208); + _curvea0[596] = _6642; + uint16_t _6643 = (uint16_t)(208); + _curvea0[597] = _6643; + uint16_t _6644 = (uint16_t)(208); + _curvea0[598] = _6644; + uint16_t _6645 = (uint16_t)(209); + _curvea0[599] = _6645; + uint16_t _6646 = (uint16_t)(209); + _curvea0[600] = _6646; + uint16_t _6647 = (uint16_t)(209); + _curvea0[601] = _6647; + uint16_t _6648 = (uint16_t)(209); + _curvea0[602] = _6648; + uint16_t _6649 = (uint16_t)(209); + _curvea0[603] = _6649; + uint16_t _6650 = (uint16_t)(209); + _curvea0[604] = _6650; + uint16_t _6651 = (uint16_t)(209); + _curvea0[605] = _6651; + uint16_t _6652 = (uint16_t)(210); + _curvea0[606] = _6652; + uint16_t _6653 = (uint16_t)(210); + _curvea0[607] = _6653; + uint16_t _6654 = (uint16_t)(210); + _curvea0[608] = _6654; + uint16_t _6655 = (uint16_t)(210); + _curvea0[609] = _6655; + uint16_t _6656 = (uint16_t)(210); + _curvea0[610] = _6656; + uint16_t _6657 = (uint16_t)(210); + _curvea0[611] = _6657; + uint16_t _6658 = (uint16_t)(211); + _curvea0[612] = _6658; + uint16_t _6659 = (uint16_t)(211); + _curvea0[613] = _6659; + uint16_t _6660 = (uint16_t)(211); + _curvea0[614] = _6660; + uint16_t _6661 = (uint16_t)(211); + _curvea0[615] = _6661; + uint16_t _6662 = (uint16_t)(211); + _curvea0[616] = _6662; + uint16_t _6663 = (uint16_t)(211); + _curvea0[617] = _6663; + uint16_t _6664 = (uint16_t)(211); + _curvea0[618] = _6664; + uint16_t _6665 = (uint16_t)(212); + _curvea0[619] = _6665; + uint16_t _6666 = (uint16_t)(212); + _curvea0[620] = _6666; + uint16_t _6667 = (uint16_t)(212); + _curvea0[621] = _6667; + uint16_t _6668 = (uint16_t)(212); + _curvea0[622] = _6668; + uint16_t _6669 = (uint16_t)(212); + _curvea0[623] = _6669; + uint16_t _6670 = (uint16_t)(212); + _curvea0[624] = _6670; + uint16_t _6671 = (uint16_t)(213); + _curvea0[625] = _6671; + uint16_t _6672 = (uint16_t)(213); + _curvea0[626] = _6672; + uint16_t _6673 = (uint16_t)(213); + _curvea0[627] = _6673; + uint16_t _6674 = (uint16_t)(213); + _curvea0[628] = _6674; + uint16_t _6675 = (uint16_t)(213); + _curvea0[629] = _6675; + uint16_t _6676 = (uint16_t)(213); + _curvea0[630] = _6676; + uint16_t _6677 = (uint16_t)(213); + _curvea0[631] = _6677; + uint16_t _6678 = (uint16_t)(214); + _curvea0[632] = _6678; + uint16_t _6679 = (uint16_t)(214); + _curvea0[633] = _6679; + uint16_t _6680 = (uint16_t)(214); + _curvea0[634] = _6680; + uint16_t _6681 = (uint16_t)(214); + _curvea0[635] = _6681; + uint16_t _6682 = (uint16_t)(214); + _curvea0[636] = _6682; + uint16_t _6683 = (uint16_t)(214); + _curvea0[637] = _6683; + uint16_t _6684 = (uint16_t)(214); + _curvea0[638] = _6684; + uint16_t _6685 = (uint16_t)(215); + _curvea0[639] = _6685; + uint16_t _6686 = (uint16_t)(215); + _curvea0[640] = _6686; + uint16_t _6687 = (uint16_t)(215); + _curvea0[641] = _6687; + uint16_t _6688 = (uint16_t)(215); + _curvea0[642] = _6688; + uint16_t _6689 = (uint16_t)(215); + _curvea0[643] = _6689; + uint16_t _6690 = (uint16_t)(215); + _curvea0[644] = _6690; + uint16_t _6691 = (uint16_t)(216); + _curvea0[645] = _6691; + uint16_t _6692 = (uint16_t)(216); + _curvea0[646] = _6692; + uint16_t _6693 = (uint16_t)(216); + _curvea0[647] = _6693; + uint16_t _6694 = (uint16_t)(216); + _curvea0[648] = _6694; + uint16_t _6695 = (uint16_t)(216); + _curvea0[649] = _6695; + uint16_t _6696 = (uint16_t)(216); + _curvea0[650] = _6696; + uint16_t _6697 = (uint16_t)(216); + _curvea0[651] = _6697; + uint16_t _6698 = (uint16_t)(217); + _curvea0[652] = _6698; + uint16_t _6699 = (uint16_t)(217); + _curvea0[653] = _6699; + uint16_t _6700 = (uint16_t)(217); + _curvea0[654] = _6700; + uint16_t _6701 = (uint16_t)(217); + _curvea0[655] = _6701; + uint16_t _6702 = (uint16_t)(217); + _curvea0[656] = _6702; + uint16_t _6703 = (uint16_t)(217); + _curvea0[657] = _6703; + uint16_t _6704 = (uint16_t)(217); + _curvea0[658] = _6704; + uint16_t _6705 = (uint16_t)(218); + _curvea0[659] = _6705; + uint16_t _6706 = (uint16_t)(218); + _curvea0[660] = _6706; + uint16_t _6707 = (uint16_t)(218); + _curvea0[661] = _6707; + uint16_t _6708 = (uint16_t)(218); + _curvea0[662] = _6708; + uint16_t _6709 = (uint16_t)(218); + _curvea0[663] = _6709; + uint16_t _6710 = (uint16_t)(218); + _curvea0[664] = _6710; + uint16_t _6711 = (uint16_t)(218); + _curvea0[665] = _6711; + uint16_t _6712 = (uint16_t)(219); + _curvea0[666] = _6712; + uint16_t _6713 = (uint16_t)(219); + _curvea0[667] = _6713; + uint16_t _6714 = (uint16_t)(219); + _curvea0[668] = _6714; + uint16_t _6715 = (uint16_t)(219); + _curvea0[669] = _6715; + uint16_t _6716 = (uint16_t)(219); + _curvea0[670] = _6716; + uint16_t _6717 = (uint16_t)(219); + _curvea0[671] = _6717; + uint16_t _6718 = (uint16_t)(219); + _curvea0[672] = _6718; + uint16_t _6719 = (uint16_t)(220); + _curvea0[673] = _6719; + uint16_t _6720 = (uint16_t)(220); + _curvea0[674] = _6720; + uint16_t _6721 = (uint16_t)(220); + _curvea0[675] = _6721; + uint16_t _6722 = (uint16_t)(220); + _curvea0[676] = _6722; + uint16_t _6723 = (uint16_t)(220); + _curvea0[677] = _6723; + uint16_t _6724 = (uint16_t)(220); + _curvea0[678] = _6724; + uint16_t _6725 = (uint16_t)(220); + _curvea0[679] = _6725; + uint16_t _6726 = (uint16_t)(220); + _curvea0[680] = _6726; + uint16_t _6727 = (uint16_t)(221); + _curvea0[681] = _6727; + uint16_t _6728 = (uint16_t)(221); + _curvea0[682] = _6728; + uint16_t _6729 = (uint16_t)(221); + _curvea0[683] = _6729; + uint16_t _6730 = (uint16_t)(221); + _curvea0[684] = _6730; + uint16_t _6731 = (uint16_t)(221); + _curvea0[685] = _6731; + uint16_t _6732 = (uint16_t)(221); + _curvea0[686] = _6732; + uint16_t _6733 = (uint16_t)(221); + _curvea0[687] = _6733; + uint16_t _6734 = (uint16_t)(222); + _curvea0[688] = _6734; + uint16_t _6735 = (uint16_t)(222); + _curvea0[689] = _6735; + uint16_t _6736 = (uint16_t)(222); + _curvea0[690] = _6736; + uint16_t _6737 = (uint16_t)(222); + _curvea0[691] = _6737; + uint16_t _6738 = (uint16_t)(222); + _curvea0[692] = _6738; + uint16_t _6739 = (uint16_t)(222); + _curvea0[693] = _6739; + uint16_t _6740 = (uint16_t)(222); + _curvea0[694] = _6740; + uint16_t _6741 = (uint16_t)(223); + _curvea0[695] = _6741; + uint16_t _6742 = (uint16_t)(223); + _curvea0[696] = _6742; + uint16_t _6743 = (uint16_t)(223); + _curvea0[697] = _6743; + uint16_t _6744 = (uint16_t)(223); + _curvea0[698] = _6744; + uint16_t _6745 = (uint16_t)(223); + _curvea0[699] = _6745; + uint16_t _6746 = (uint16_t)(223); + _curvea0[700] = _6746; + uint16_t _6747 = (uint16_t)(223); + _curvea0[701] = _6747; + uint16_t _6748 = (uint16_t)(223); + _curvea0[702] = _6748; + uint16_t _6749 = (uint16_t)(224); + _curvea0[703] = _6749; + uint16_t _6750 = (uint16_t)(224); + _curvea0[704] = _6750; + uint16_t _6751 = (uint16_t)(224); + _curvea0[705] = _6751; + uint16_t _6752 = (uint16_t)(224); + _curvea0[706] = _6752; + uint16_t _6753 = (uint16_t)(224); + _curvea0[707] = _6753; + uint16_t _6754 = (uint16_t)(224); + _curvea0[708] = _6754; + uint16_t _6755 = (uint16_t)(224); + _curvea0[709] = _6755; + uint16_t _6756 = (uint16_t)(224); + _curvea0[710] = _6756; + uint16_t _6757 = (uint16_t)(225); + _curvea0[711] = _6757; + uint16_t _6758 = (uint16_t)(225); + _curvea0[712] = _6758; + uint16_t _6759 = (uint16_t)(225); + _curvea0[713] = _6759; + uint16_t _6760 = (uint16_t)(225); + _curvea0[714] = _6760; + uint16_t _6761 = (uint16_t)(225); + _curvea0[715] = _6761; + uint16_t _6762 = (uint16_t)(225); + _curvea0[716] = _6762; + uint16_t _6763 = (uint16_t)(225); + _curvea0[717] = _6763; + uint16_t _6764 = (uint16_t)(226); + _curvea0[718] = _6764; + uint16_t _6765 = (uint16_t)(226); + _curvea0[719] = _6765; + uint16_t _6766 = (uint16_t)(226); + _curvea0[720] = _6766; + uint16_t _6767 = (uint16_t)(226); + _curvea0[721] = _6767; + uint16_t _6768 = (uint16_t)(226); + _curvea0[722] = _6768; + uint16_t _6769 = (uint16_t)(226); + _curvea0[723] = _6769; + uint16_t _6770 = (uint16_t)(226); + _curvea0[724] = _6770; + uint16_t _6771 = (uint16_t)(226); + _curvea0[725] = _6771; + uint16_t _6772 = (uint16_t)(227); + _curvea0[726] = _6772; + uint16_t _6773 = (uint16_t)(227); + _curvea0[727] = _6773; + uint16_t _6774 = (uint16_t)(227); + _curvea0[728] = _6774; + uint16_t _6775 = (uint16_t)(227); + _curvea0[729] = _6775; + uint16_t _6776 = (uint16_t)(227); + _curvea0[730] = _6776; + uint16_t _6777 = (uint16_t)(227); + _curvea0[731] = _6777; + uint16_t _6778 = (uint16_t)(227); + _curvea0[732] = _6778; + uint16_t _6779 = (uint16_t)(227); + _curvea0[733] = _6779; + uint16_t _6780 = (uint16_t)(228); + _curvea0[734] = _6780; + uint16_t _6781 = (uint16_t)(228); + _curvea0[735] = _6781; + uint16_t _6782 = (uint16_t)(228); + _curvea0[736] = _6782; + uint16_t _6783 = (uint16_t)(228); + _curvea0[737] = _6783; + uint16_t _6784 = (uint16_t)(228); + _curvea0[738] = _6784; + uint16_t _6785 = (uint16_t)(228); + _curvea0[739] = _6785; + uint16_t _6786 = (uint16_t)(228); + _curvea0[740] = _6786; + uint16_t _6787 = (uint16_t)(228); + _curvea0[741] = _6787; + uint16_t _6788 = (uint16_t)(228); + _curvea0[742] = _6788; + uint16_t _6789 = (uint16_t)(229); + _curvea0[743] = _6789; + uint16_t _6790 = (uint16_t)(229); + _curvea0[744] = _6790; + uint16_t _6791 = (uint16_t)(229); + _curvea0[745] = _6791; + uint16_t _6792 = (uint16_t)(229); + _curvea0[746] = _6792; + uint16_t _6793 = (uint16_t)(229); + _curvea0[747] = _6793; + uint16_t _6794 = (uint16_t)(229); + _curvea0[748] = _6794; + uint16_t _6795 = (uint16_t)(229); + _curvea0[749] = _6795; + uint16_t _6796 = (uint16_t)(229); + _curvea0[750] = _6796; + uint16_t _6797 = (uint16_t)(230); + _curvea0[751] = _6797; + uint16_t _6798 = (uint16_t)(230); + _curvea0[752] = _6798; + uint16_t _6799 = (uint16_t)(230); + _curvea0[753] = _6799; + uint16_t _6800 = (uint16_t)(230); + _curvea0[754] = _6800; + uint16_t _6801 = (uint16_t)(230); + _curvea0[755] = _6801; + uint16_t _6802 = (uint16_t)(230); + _curvea0[756] = _6802; + uint16_t _6803 = (uint16_t)(230); + _curvea0[757] = _6803; + uint16_t _6804 = (uint16_t)(230); + _curvea0[758] = _6804; + uint16_t _6805 = (uint16_t)(231); + _curvea0[759] = _6805; + uint16_t _6806 = (uint16_t)(231); + _curvea0[760] = _6806; + uint16_t _6807 = (uint16_t)(231); + _curvea0[761] = _6807; + uint16_t _6808 = (uint16_t)(231); + _curvea0[762] = _6808; + uint16_t _6809 = (uint16_t)(231); + _curvea0[763] = _6809; + uint16_t _6810 = (uint16_t)(231); + _curvea0[764] = _6810; + uint16_t _6811 = (uint16_t)(231); + _curvea0[765] = _6811; + uint16_t _6812 = (uint16_t)(231); + _curvea0[766] = _6812; + uint16_t _6813 = (uint16_t)(231); + _curvea0[767] = _6813; + uint16_t _6814 = (uint16_t)(232); + _curvea0[768] = _6814; + uint16_t _6815 = (uint16_t)(232); + _curvea0[769] = _6815; + uint16_t _6816 = (uint16_t)(232); + _curvea0[770] = _6816; + uint16_t _6817 = (uint16_t)(232); + _curvea0[771] = _6817; + uint16_t _6818 = (uint16_t)(232); + _curvea0[772] = _6818; + uint16_t _6819 = (uint16_t)(232); + _curvea0[773] = _6819; + uint16_t _6820 = (uint16_t)(232); + _curvea0[774] = _6820; + uint16_t _6821 = (uint16_t)(232); + _curvea0[775] = _6821; + uint16_t _6822 = (uint16_t)(233); + _curvea0[776] = _6822; + uint16_t _6823 = (uint16_t)(233); + _curvea0[777] = _6823; + uint16_t _6824 = (uint16_t)(233); + _curvea0[778] = _6824; + uint16_t _6825 = (uint16_t)(233); + _curvea0[779] = _6825; + uint16_t _6826 = (uint16_t)(233); + _curvea0[780] = _6826; + uint16_t _6827 = (uint16_t)(233); + _curvea0[781] = _6827; + uint16_t _6828 = (uint16_t)(233); + _curvea0[782] = _6828; + uint16_t _6829 = (uint16_t)(233); + _curvea0[783] = _6829; + uint16_t _6830 = (uint16_t)(233); + _curvea0[784] = _6830; + uint16_t _6831 = (uint16_t)(234); + _curvea0[785] = _6831; + uint16_t _6832 = (uint16_t)(234); + _curvea0[786] = _6832; + uint16_t _6833 = (uint16_t)(234); + _curvea0[787] = _6833; + uint16_t _6834 = (uint16_t)(234); + _curvea0[788] = _6834; + uint16_t _6835 = (uint16_t)(234); + _curvea0[789] = _6835; + uint16_t _6836 = (uint16_t)(234); + _curvea0[790] = _6836; + uint16_t _6837 = (uint16_t)(234); + _curvea0[791] = _6837; + uint16_t _6838 = (uint16_t)(234); + _curvea0[792] = _6838; + uint16_t _6839 = (uint16_t)(234); + _curvea0[793] = _6839; + uint16_t _6840 = (uint16_t)(235); + _curvea0[794] = _6840; + uint16_t _6841 = (uint16_t)(235); + _curvea0[795] = _6841; + uint16_t _6842 = (uint16_t)(235); + _curvea0[796] = _6842; + uint16_t _6843 = (uint16_t)(235); + _curvea0[797] = _6843; + uint16_t _6844 = (uint16_t)(235); + _curvea0[798] = _6844; + uint16_t _6845 = (uint16_t)(235); + _curvea0[799] = _6845; + uint16_t _6846 = (uint16_t)(235); + _curvea0[800] = _6846; + uint16_t _6847 = (uint16_t)(235); + _curvea0[801] = _6847; + uint16_t _6848 = (uint16_t)(235); + _curvea0[802] = _6848; + uint16_t _6849 = (uint16_t)(236); + _curvea0[803] = _6849; + uint16_t _6850 = (uint16_t)(236); + _curvea0[804] = _6850; + uint16_t _6851 = (uint16_t)(236); + _curvea0[805] = _6851; + uint16_t _6852 = (uint16_t)(236); + _curvea0[806] = _6852; + uint16_t _6853 = (uint16_t)(236); + _curvea0[807] = _6853; + uint16_t _6854 = (uint16_t)(236); + _curvea0[808] = _6854; + uint16_t _6855 = (uint16_t)(236); + _curvea0[809] = _6855; + uint16_t _6856 = (uint16_t)(236); + _curvea0[810] = _6856; + uint16_t _6857 = (uint16_t)(236); + _curvea0[811] = _6857; + uint16_t _6858 = (uint16_t)(237); + _curvea0[812] = _6858; + uint16_t _6859 = (uint16_t)(237); + _curvea0[813] = _6859; + uint16_t _6860 = (uint16_t)(237); + _curvea0[814] = _6860; + uint16_t _6861 = (uint16_t)(237); + _curvea0[815] = _6861; + uint16_t _6862 = (uint16_t)(237); + _curvea0[816] = _6862; + uint16_t _6863 = (uint16_t)(237); + _curvea0[817] = _6863; + uint16_t _6864 = (uint16_t)(237); + _curvea0[818] = _6864; + uint16_t _6865 = (uint16_t)(237); + _curvea0[819] = _6865; + uint16_t _6866 = (uint16_t)(237); + _curvea0[820] = _6866; + uint16_t _6867 = (uint16_t)(237); + _curvea0[821] = _6867; + uint16_t _6868 = (uint16_t)(238); + _curvea0[822] = _6868; + uint16_t _6869 = (uint16_t)(238); + _curvea0[823] = _6869; + uint16_t _6870 = (uint16_t)(238); + _curvea0[824] = _6870; + uint16_t _6871 = (uint16_t)(238); + _curvea0[825] = _6871; + uint16_t _6872 = (uint16_t)(238); + _curvea0[826] = _6872; + uint16_t _6873 = (uint16_t)(238); + _curvea0[827] = _6873; + uint16_t _6874 = (uint16_t)(238); + _curvea0[828] = _6874; + uint16_t _6875 = (uint16_t)(238); + _curvea0[829] = _6875; + uint16_t _6876 = (uint16_t)(238); + _curvea0[830] = _6876; + uint16_t _6877 = (uint16_t)(239); + _curvea0[831] = _6877; + uint16_t _6878 = (uint16_t)(239); + _curvea0[832] = _6878; + uint16_t _6879 = (uint16_t)(239); + _curvea0[833] = _6879; + uint16_t _6880 = (uint16_t)(239); + _curvea0[834] = _6880; + uint16_t _6881 = (uint16_t)(239); + _curvea0[835] = _6881; + uint16_t _6882 = (uint16_t)(239); + _curvea0[836] = _6882; + uint16_t _6883 = (uint16_t)(239); + _curvea0[837] = _6883; + uint16_t _6884 = (uint16_t)(239); + _curvea0[838] = _6884; + uint16_t _6885 = (uint16_t)(239); + _curvea0[839] = _6885; + uint16_t _6886 = (uint16_t)(239); + _curvea0[840] = _6886; + uint16_t _6887 = (uint16_t)(240); + _curvea0[841] = _6887; + uint16_t _6888 = (uint16_t)(240); + _curvea0[842] = _6888; + uint16_t _6889 = (uint16_t)(240); + _curvea0[843] = _6889; + uint16_t _6890 = (uint16_t)(240); + _curvea0[844] = _6890; + uint16_t _6891 = (uint16_t)(240); + _curvea0[845] = _6891; + uint16_t _6892 = (uint16_t)(240); + _curvea0[846] = _6892; + uint16_t _6893 = (uint16_t)(240); + _curvea0[847] = _6893; + uint16_t _6894 = (uint16_t)(240); + _curvea0[848] = _6894; + uint16_t _6895 = (uint16_t)(240); + _curvea0[849] = _6895; + uint16_t _6896 = (uint16_t)(240); + _curvea0[850] = _6896; + uint16_t _6897 = (uint16_t)(241); + _curvea0[851] = _6897; + uint16_t _6898 = (uint16_t)(241); + _curvea0[852] = _6898; + uint16_t _6899 = (uint16_t)(241); + _curvea0[853] = _6899; + uint16_t _6900 = (uint16_t)(241); + _curvea0[854] = _6900; + uint16_t _6901 = (uint16_t)(241); + _curvea0[855] = _6901; + uint16_t _6902 = (uint16_t)(241); + _curvea0[856] = _6902; + uint16_t _6903 = (uint16_t)(241); + _curvea0[857] = _6903; + uint16_t _6904 = (uint16_t)(241); + _curvea0[858] = _6904; + uint16_t _6905 = (uint16_t)(241); + _curvea0[859] = _6905; + uint16_t _6906 = (uint16_t)(241); + _curvea0[860] = _6906; + uint16_t _6907 = (uint16_t)(242); + _curvea0[861] = _6907; + uint16_t _6908 = (uint16_t)(242); + _curvea0[862] = _6908; + uint16_t _6909 = (uint16_t)(242); + _curvea0[863] = _6909; + uint16_t _6910 = (uint16_t)(242); + _curvea0[864] = _6910; + uint16_t _6911 = (uint16_t)(242); + _curvea0[865] = _6911; + uint16_t _6912 = (uint16_t)(242); + _curvea0[866] = _6912; + uint16_t _6913 = (uint16_t)(242); + _curvea0[867] = _6913; + uint16_t _6914 = (uint16_t)(242); + _curvea0[868] = _6914; + uint16_t _6915 = (uint16_t)(242); + _curvea0[869] = _6915; + uint16_t _6916 = (uint16_t)(242); + _curvea0[870] = _6916; + uint16_t _6917 = (uint16_t)(243); + _curvea0[871] = _6917; + uint16_t _6918 = (uint16_t)(243); + _curvea0[872] = _6918; + uint16_t _6919 = (uint16_t)(243); + _curvea0[873] = _6919; + uint16_t _6920 = (uint16_t)(243); + _curvea0[874] = _6920; + uint16_t _6921 = (uint16_t)(243); + _curvea0[875] = _6921; + uint16_t _6922 = (uint16_t)(243); + _curvea0[876] = _6922; + uint16_t _6923 = (uint16_t)(243); + _curvea0[877] = _6923; + uint16_t _6924 = (uint16_t)(243); + _curvea0[878] = _6924; + uint16_t _6925 = (uint16_t)(243); + _curvea0[879] = _6925; + uint16_t _6926 = (uint16_t)(243); + _curvea0[880] = _6926; + uint16_t _6927 = (uint16_t)(244); + _curvea0[881] = _6927; + uint16_t _6928 = (uint16_t)(244); + _curvea0[882] = _6928; + uint16_t _6929 = (uint16_t)(244); + _curvea0[883] = _6929; + uint16_t _6930 = (uint16_t)(244); + _curvea0[884] = _6930; + uint16_t _6931 = (uint16_t)(244); + _curvea0[885] = _6931; + uint16_t _6932 = (uint16_t)(244); + _curvea0[886] = _6932; + uint16_t _6933 = (uint16_t)(244); + _curvea0[887] = _6933; + uint16_t _6934 = (uint16_t)(244); + _curvea0[888] = _6934; + uint16_t _6935 = (uint16_t)(244); + _curvea0[889] = _6935; + uint16_t _6936 = (uint16_t)(244); + _curvea0[890] = _6936; + uint16_t _6937 = (uint16_t)(244); + _curvea0[891] = _6937; + uint16_t _6938 = (uint16_t)(245); + _curvea0[892] = _6938; + uint16_t _6939 = (uint16_t)(245); + _curvea0[893] = _6939; + uint16_t _6940 = (uint16_t)(245); + _curvea0[894] = _6940; + uint16_t _6941 = (uint16_t)(245); + _curvea0[895] = _6941; + uint16_t _6942 = (uint16_t)(245); + _curvea0[896] = _6942; + uint16_t _6943 = (uint16_t)(245); + _curvea0[897] = _6943; + uint16_t _6944 = (uint16_t)(245); + _curvea0[898] = _6944; + uint16_t _6945 = (uint16_t)(245); + _curvea0[899] = _6945; + uint16_t _6946 = (uint16_t)(245); + _curvea0[900] = _6946; + uint16_t _6947 = (uint16_t)(245); + _curvea0[901] = _6947; + uint16_t _6948 = (uint16_t)(245); + _curvea0[902] = _6948; + uint16_t _6949 = (uint16_t)(246); + _curvea0[903] = _6949; + uint16_t _6950 = (uint16_t)(246); + _curvea0[904] = _6950; + uint16_t _6951 = (uint16_t)(246); + _curvea0[905] = _6951; + uint16_t _6952 = (uint16_t)(246); + _curvea0[906] = _6952; + uint16_t _6953 = (uint16_t)(246); + _curvea0[907] = _6953; + uint16_t _6954 = (uint16_t)(246); + _curvea0[908] = _6954; + uint16_t _6955 = (uint16_t)(246); + _curvea0[909] = _6955; + uint16_t _6956 = (uint16_t)(246); + _curvea0[910] = _6956; + uint16_t _6957 = (uint16_t)(246); + _curvea0[911] = _6957; + uint16_t _6958 = (uint16_t)(246); + _curvea0[912] = _6958; + uint16_t _6959 = (uint16_t)(246); + _curvea0[913] = _6959; + uint16_t _6960 = (uint16_t)(247); + _curvea0[914] = _6960; + uint16_t _6961 = (uint16_t)(247); + _curvea0[915] = _6961; + uint16_t _6962 = (uint16_t)(247); + _curvea0[916] = _6962; + uint16_t _6963 = (uint16_t)(247); + _curvea0[917] = _6963; + uint16_t _6964 = (uint16_t)(247); + _curvea0[918] = _6964; + uint16_t _6965 = (uint16_t)(247); + _curvea0[919] = _6965; + uint16_t _6966 = (uint16_t)(247); + _curvea0[920] = _6966; + uint16_t _6967 = (uint16_t)(247); + _curvea0[921] = _6967; + uint16_t _6968 = (uint16_t)(247); + _curvea0[922] = _6968; + uint16_t _6969 = (uint16_t)(247); + _curvea0[923] = _6969; + uint16_t _6970 = (uint16_t)(247); + _curvea0[924] = _6970; + uint16_t _6971 = (uint16_t)(248); + _curvea0[925] = _6971; + uint16_t _6972 = (uint16_t)(248); + _curvea0[926] = _6972; + uint16_t _6973 = (uint16_t)(248); + _curvea0[927] = _6973; + uint16_t _6974 = (uint16_t)(248); + _curvea0[928] = _6974; + uint16_t _6975 = (uint16_t)(248); + _curvea0[929] = _6975; + uint16_t _6976 = (uint16_t)(248); + _curvea0[930] = _6976; + uint16_t _6977 = (uint16_t)(248); + _curvea0[931] = _6977; + uint16_t _6978 = (uint16_t)(248); + _curvea0[932] = _6978; + uint16_t _6979 = (uint16_t)(248); + _curvea0[933] = _6979; + uint16_t _6980 = (uint16_t)(248); + _curvea0[934] = _6980; + uint16_t _6981 = (uint16_t)(248); + _curvea0[935] = _6981; + uint16_t _6982 = (uint16_t)(249); + _curvea0[936] = _6982; + uint16_t _6983 = (uint16_t)(249); + _curvea0[937] = _6983; + uint16_t _6984 = (uint16_t)(249); + _curvea0[938] = _6984; + uint16_t _6985 = (uint16_t)(249); + _curvea0[939] = _6985; + uint16_t _6986 = (uint16_t)(249); + _curvea0[940] = _6986; + uint16_t _6987 = (uint16_t)(249); + _curvea0[941] = _6987; + uint16_t _6988 = (uint16_t)(249); + _curvea0[942] = _6988; + uint16_t _6989 = (uint16_t)(249); + _curvea0[943] = _6989; + uint16_t _6990 = (uint16_t)(249); + _curvea0[944] = _6990; + uint16_t _6991 = (uint16_t)(249); + _curvea0[945] = _6991; + uint16_t _6992 = (uint16_t)(249); + _curvea0[946] = _6992; + uint16_t _6993 = (uint16_t)(249); + _curvea0[947] = _6993; + uint16_t _6994 = (uint16_t)(250); + _curvea0[948] = _6994; + uint16_t _6995 = (uint16_t)(250); + _curvea0[949] = _6995; + uint16_t _6996 = (uint16_t)(250); + _curvea0[950] = _6996; + uint16_t _6997 = (uint16_t)(250); + _curvea0[951] = _6997; + uint16_t _6998 = (uint16_t)(250); + _curvea0[952] = _6998; + uint16_t _6999 = (uint16_t)(250); + _curvea0[953] = _6999; + uint16_t _7000 = (uint16_t)(250); + _curvea0[954] = _7000; + uint16_t _7001 = (uint16_t)(250); + _curvea0[955] = _7001; + uint16_t _7002 = (uint16_t)(250); + _curvea0[956] = _7002; + uint16_t _7003 = (uint16_t)(250); + _curvea0[957] = _7003; + uint16_t _7004 = (uint16_t)(250); + _curvea0[958] = _7004; + uint16_t _7005 = (uint16_t)(250); + _curvea0[959] = _7005; + uint16_t _7006 = (uint16_t)(251); + _curvea0[960] = _7006; + uint16_t _7007 = (uint16_t)(251); + _curvea0[961] = _7007; + uint16_t _7008 = (uint16_t)(251); + _curvea0[962] = _7008; + uint16_t _7009 = (uint16_t)(251); + _curvea0[963] = _7009; + uint16_t _7010 = (uint16_t)(251); + _curvea0[964] = _7010; + uint16_t _7011 = (uint16_t)(251); + _curvea0[965] = _7011; + uint16_t _7012 = (uint16_t)(251); + _curvea0[966] = _7012; + uint16_t _7013 = (uint16_t)(251); + _curvea0[967] = _7013; + uint16_t _7014 = (uint16_t)(251); + _curvea0[968] = _7014; + uint16_t _7015 = (uint16_t)(251); + _curvea0[969] = _7015; + uint16_t _7016 = (uint16_t)(251); + _curvea0[970] = _7016; + uint16_t _7017 = (uint16_t)(251); + _curvea0[971] = _7017; + uint16_t _7018 = (uint16_t)(252); + _curvea0[972] = _7018; + uint16_t _7019 = (uint16_t)(252); + _curvea0[973] = _7019; + uint16_t _7020 = (uint16_t)(252); + _curvea0[974] = _7020; + uint16_t _7021 = (uint16_t)(252); + _curvea0[975] = _7021; + uint16_t _7022 = (uint16_t)(252); + _curvea0[976] = _7022; + uint16_t _7023 = (uint16_t)(252); + _curvea0[977] = _7023; + uint16_t _7024 = (uint16_t)(252); + _curvea0[978] = _7024; + uint16_t _7025 = (uint16_t)(252); + _curvea0[979] = _7025; + uint16_t _7026 = (uint16_t)(252); + _curvea0[980] = _7026; + uint16_t _7027 = (uint16_t)(252); + _curvea0[981] = _7027; + uint16_t _7028 = (uint16_t)(252); + _curvea0[982] = _7028; + uint16_t _7029 = (uint16_t)(252); + _curvea0[983] = _7029; + uint16_t _7030 = (uint16_t)(252); + _curvea0[984] = _7030; + uint16_t _7031 = (uint16_t)(253); + _curvea0[985] = _7031; + uint16_t _7032 = (uint16_t)(253); + _curvea0[986] = _7032; + uint16_t _7033 = (uint16_t)(253); + _curvea0[987] = _7033; + uint16_t _7034 = (uint16_t)(253); + _curvea0[988] = _7034; + uint16_t _7035 = (uint16_t)(253); + _curvea0[989] = _7035; + uint16_t _7036 = (uint16_t)(253); + _curvea0[990] = _7036; + uint16_t _7037 = (uint16_t)(253); + _curvea0[991] = _7037; + uint16_t _7038 = (uint16_t)(253); + _curvea0[992] = _7038; + uint16_t _7039 = (uint16_t)(253); + _curvea0[993] = _7039; + uint16_t _7040 = (uint16_t)(253); + _curvea0[994] = _7040; + uint16_t _7041 = (uint16_t)(253); + _curvea0[995] = _7041; + uint16_t _7042 = (uint16_t)(253); + _curvea0[996] = _7042; + uint16_t _7043 = (uint16_t)(253); + _curvea0[997] = _7043; + uint16_t _7044 = (uint16_t)(254); + _curvea0[998] = _7044; + uint16_t _7045 = (uint16_t)(254); + _curvea0[999] = _7045; + uint16_t _7046 = (uint16_t)(254); + _curvea0[1000] = _7046; + uint16_t _7047 = (uint16_t)(254); + _curvea0[1001] = _7047; + uint16_t _7048 = (uint16_t)(254); + _curvea0[1002] = _7048; + uint16_t _7049 = (uint16_t)(254); + _curvea0[1003] = _7049; + uint16_t _7050 = (uint16_t)(254); + _curvea0[1004] = _7050; + uint16_t _7051 = (uint16_t)(254); + _curvea0[1005] = _7051; + uint16_t _7052 = (uint16_t)(254); + _curvea0[1006] = _7052; + uint16_t _7053 = (uint16_t)(254); + _curvea0[1007] = _7053; + uint16_t _7054 = (uint16_t)(254); + _curvea0[1008] = _7054; + uint16_t _7055 = (uint16_t)(254); + _curvea0[1009] = _7055; + uint16_t _7056 = (uint16_t)(254); + _curvea0[1010] = _7056; + uint16_t _7057 = (uint16_t)(255); + _curvea0[1011] = _7057; + uint16_t _7058 = (uint16_t)(255); + _curvea0[1012] = _7058; + uint16_t _7059 = (uint16_t)(255); + _curvea0[1013] = _7059; + uint16_t _7060 = (uint16_t)(255); + _curvea0[1014] = _7060; + uint16_t _7061 = (uint16_t)(255); + _curvea0[1015] = _7061; + uint16_t _7062 = (uint16_t)(255); + _curvea0[1016] = _7062; + uint16_t _7063 = (uint16_t)(255); + _curvea0[1017] = _7063; + uint16_t _7064 = (uint16_t)(255); + _curvea0[1018] = _7064; + uint16_t _7065 = (uint16_t)(255); + _curvea0[1019] = _7065; + uint16_t _7066 = (uint16_t)(255); + _curvea0[1020] = _7066; + uint16_t _7067 = (uint16_t)(255); + _curvea0[1021] = _7067; + uint16_t _7068 = (uint16_t)(255); + _curvea0[1022] = _7068; + uint16_t _7069 = (uint16_t)(255); + _curvea0[1023] = _7069; + + int16_t _7070 = (int16_t)(1023); + int16_t _7071 = min(_corrected_stencil_3, _7070); + int16_t _7072 = (int16_t)(0); + int16_t _7073 = max(_7071, _7072); + uint16_t _7074 = (uint16_t)(_7073); + int32_t _7075 = (int32_t)(_7074); + uint16_t _7076 = ((const uint16_t *)_curvea0)[_7075]; + return _7076; +} + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_3(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_4 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _7093 = (uint16_t)(0); + _curvea0[0] = _7093; + uint16_t _7094 = (uint16_t)(4); + _curvea0[1] = _7094; + uint16_t _7095 = (uint16_t)(7); + _curvea0[2] = _7095; + uint16_t _7096 = (uint16_t)(8); + _curvea0[3] = _7096; + uint16_t _7097 = (uint16_t)(10); + _curvea0[4] = _7097; + uint16_t _7098 = (uint16_t)(11); + _curvea0[5] = _7098; + uint16_t _7099 = (uint16_t)(12); + _curvea0[6] = _7099; + uint16_t _7100 = (uint16_t)(13); + _curvea0[7] = _7100; + uint16_t _7101 = (uint16_t)(14); + _curvea0[8] = _7101; + uint16_t _7102 = (uint16_t)(15); + _curvea0[9] = _7102; + uint16_t _7103 = (uint16_t)(16); + _curvea0[10] = _7103; + uint16_t _7104 = (uint16_t)(17); + _curvea0[11] = _7104; + uint16_t _7105 = (uint16_t)(18); + _curvea0[12] = _7105; + uint16_t _7106 = (uint16_t)(19); + _curvea0[13] = _7106; + uint16_t _7107 = (uint16_t)(20); + _curvea0[14] = _7107; + uint16_t _7108 = (uint16_t)(21); + _curvea0[15] = _7108; + uint16_t _7109 = (uint16_t)(22); + _curvea0[16] = _7109; + uint16_t _7110 = (uint16_t)(22); + _curvea0[17] = _7110; + uint16_t _7111 = (uint16_t)(23); + _curvea0[18] = _7111; + uint16_t _7112 = (uint16_t)(24); + _curvea0[19] = _7112; + uint16_t _7113 = (uint16_t)(25); + _curvea0[20] = _7113; + uint16_t _7114 = (uint16_t)(25); + _curvea0[21] = _7114; + uint16_t _7115 = (uint16_t)(26); + _curvea0[22] = _7115; + uint16_t _7116 = (uint16_t)(27); + _curvea0[23] = _7116; + uint16_t _7117 = (uint16_t)(27); + _curvea0[24] = _7117; + uint16_t _7118 = (uint16_t)(28); + _curvea0[25] = _7118; + uint16_t _7119 = (uint16_t)(29); + _curvea0[26] = _7119; + uint16_t _7120 = (uint16_t)(29); + _curvea0[27] = _7120; + uint16_t _7121 = (uint16_t)(30); + _curvea0[28] = _7121; + uint16_t _7122 = (uint16_t)(31); + _curvea0[29] = _7122; + uint16_t _7123 = (uint16_t)(31); + _curvea0[30] = _7123; + uint16_t _7124 = (uint16_t)(32); + _curvea0[31] = _7124; + uint16_t _7125 = (uint16_t)(33); + _curvea0[32] = _7125; + uint16_t _7126 = (uint16_t)(33); + _curvea0[33] = _7126; + uint16_t _7127 = (uint16_t)(34); + _curvea0[34] = _7127; + uint16_t _7128 = (uint16_t)(34); + _curvea0[35] = _7128; + uint16_t _7129 = (uint16_t)(35); + _curvea0[36] = _7129; + uint16_t _7130 = (uint16_t)(36); + _curvea0[37] = _7130; + uint16_t _7131 = (uint16_t)(36); + _curvea0[38] = _7131; + uint16_t _7132 = (uint16_t)(37); + _curvea0[39] = _7132; + uint16_t _7133 = (uint16_t)(37); + _curvea0[40] = _7133; + uint16_t _7134 = (uint16_t)(38); + _curvea0[41] = _7134; + uint16_t _7135 = (uint16_t)(39); + _curvea0[42] = _7135; + uint16_t _7136 = (uint16_t)(39); + _curvea0[43] = _7136; + uint16_t _7137 = (uint16_t)(40); + _curvea0[44] = _7137; + uint16_t _7138 = (uint16_t)(40); + _curvea0[45] = _7138; + uint16_t _7139 = (uint16_t)(41); + _curvea0[46] = _7139; + uint16_t _7140 = (uint16_t)(41); + _curvea0[47] = _7140; + uint16_t _7141 = (uint16_t)(42); + _curvea0[48] = _7141; + uint16_t _7142 = (uint16_t)(42); + _curvea0[49] = _7142; + uint16_t _7143 = (uint16_t)(43); + _curvea0[50] = _7143; + uint16_t _7144 = (uint16_t)(44); + _curvea0[51] = _7144; + uint16_t _7145 = (uint16_t)(44); + _curvea0[52] = _7145; + uint16_t _7146 = (uint16_t)(45); + _curvea0[53] = _7146; + uint16_t _7147 = (uint16_t)(45); + _curvea0[54] = _7147; + uint16_t _7148 = (uint16_t)(46); + _curvea0[55] = _7148; + uint16_t _7149 = (uint16_t)(46); + _curvea0[56] = _7149; + uint16_t _7150 = (uint16_t)(47); + _curvea0[57] = _7150; + uint16_t _7151 = (uint16_t)(47); + _curvea0[58] = _7151; + uint16_t _7152 = (uint16_t)(48); + _curvea0[59] = _7152; + uint16_t _7153 = (uint16_t)(48); + _curvea0[60] = _7153; + uint16_t _7154 = (uint16_t)(49); + _curvea0[61] = _7154; + uint16_t _7155 = (uint16_t)(49); + _curvea0[62] = _7155; + uint16_t _7156 = (uint16_t)(50); + _curvea0[63] = _7156; + uint16_t _7157 = (uint16_t)(50); + _curvea0[64] = _7157; + uint16_t _7158 = (uint16_t)(51); + _curvea0[65] = _7158; + uint16_t _7159 = (uint16_t)(51); + _curvea0[66] = _7159; + uint16_t _7160 = (uint16_t)(52); + _curvea0[67] = _7160; + uint16_t _7161 = (uint16_t)(52); + _curvea0[68] = _7161; + uint16_t _7162 = (uint16_t)(53); + _curvea0[69] = _7162; + uint16_t _7163 = (uint16_t)(53); + _curvea0[70] = _7163; + uint16_t _7164 = (uint16_t)(54); + _curvea0[71] = _7164; + uint16_t _7165 = (uint16_t)(54); + _curvea0[72] = _7165; + uint16_t _7166 = (uint16_t)(55); + _curvea0[73] = _7166; + uint16_t _7167 = (uint16_t)(55); + _curvea0[74] = _7167; + uint16_t _7168 = (uint16_t)(56); + _curvea0[75] = _7168; + uint16_t _7169 = (uint16_t)(56); + _curvea0[76] = _7169; + uint16_t _7170 = (uint16_t)(57); + _curvea0[77] = _7170; + uint16_t _7171 = (uint16_t)(57); + _curvea0[78] = _7171; + uint16_t _7172 = (uint16_t)(58); + _curvea0[79] = _7172; + uint16_t _7173 = (uint16_t)(58); + _curvea0[80] = _7173; + uint16_t _7174 = (uint16_t)(58); + _curvea0[81] = _7174; + uint16_t _7175 = (uint16_t)(59); + _curvea0[82] = _7175; + uint16_t _7176 = (uint16_t)(59); + _curvea0[83] = _7176; + uint16_t _7177 = (uint16_t)(60); + _curvea0[84] = _7177; + uint16_t _7178 = (uint16_t)(60); + _curvea0[85] = _7178; + uint16_t _7179 = (uint16_t)(61); + _curvea0[86] = _7179; + uint16_t _7180 = (uint16_t)(61); + _curvea0[87] = _7180; + uint16_t _7181 = (uint16_t)(62); + _curvea0[88] = _7181; + uint16_t _7182 = (uint16_t)(62); + _curvea0[89] = _7182; + uint16_t _7183 = (uint16_t)(63); + _curvea0[90] = _7183; + uint16_t _7184 = (uint16_t)(63); + _curvea0[91] = _7184; + uint16_t _7185 = (uint16_t)(64); + _curvea0[92] = _7185; + uint16_t _7186 = (uint16_t)(64); + _curvea0[93] = _7186; + uint16_t _7187 = (uint16_t)(64); + _curvea0[94] = _7187; + uint16_t _7188 = (uint16_t)(65); + _curvea0[95] = _7188; + uint16_t _7189 = (uint16_t)(65); + _curvea0[96] = _7189; + uint16_t _7190 = (uint16_t)(66); + _curvea0[97] = _7190; + uint16_t _7191 = (uint16_t)(66); + _curvea0[98] = _7191; + uint16_t _7192 = (uint16_t)(67); + _curvea0[99] = _7192; + uint16_t _7193 = (uint16_t)(67); + _curvea0[100] = _7193; + uint16_t _7194 = (uint16_t)(68); + _curvea0[101] = _7194; + uint16_t _7195 = (uint16_t)(68); + _curvea0[102] = _7195; + uint16_t _7196 = (uint16_t)(68); + _curvea0[103] = _7196; + uint16_t _7197 = (uint16_t)(69); + _curvea0[104] = _7197; + uint16_t _7198 = (uint16_t)(69); + _curvea0[105] = _7198; + uint16_t _7199 = (uint16_t)(70); + _curvea0[106] = _7199; + uint16_t _7200 = (uint16_t)(70); + _curvea0[107] = _7200; + uint16_t _7201 = (uint16_t)(71); + _curvea0[108] = _7201; + uint16_t _7202 = (uint16_t)(71); + _curvea0[109] = _7202; + uint16_t _7203 = (uint16_t)(71); + _curvea0[110] = _7203; + uint16_t _7204 = (uint16_t)(72); + _curvea0[111] = _7204; + uint16_t _7205 = (uint16_t)(72); + _curvea0[112] = _7205; + uint16_t _7206 = (uint16_t)(73); + _curvea0[113] = _7206; + uint16_t _7207 = (uint16_t)(73); + _curvea0[114] = _7207; + uint16_t _7208 = (uint16_t)(74); + _curvea0[115] = _7208; + uint16_t _7209 = (uint16_t)(74); + _curvea0[116] = _7209; + uint16_t _7210 = (uint16_t)(74); + _curvea0[117] = _7210; + uint16_t _7211 = (uint16_t)(75); + _curvea0[118] = _7211; + uint16_t _7212 = (uint16_t)(75); + _curvea0[119] = _7212; + uint16_t _7213 = (uint16_t)(76); + _curvea0[120] = _7213; + uint16_t _7214 = (uint16_t)(76); + _curvea0[121] = _7214; + uint16_t _7215 = (uint16_t)(77); + _curvea0[122] = _7215; + uint16_t _7216 = (uint16_t)(77); + _curvea0[123] = _7216; + uint16_t _7217 = (uint16_t)(77); + _curvea0[124] = _7217; + uint16_t _7218 = (uint16_t)(78); + _curvea0[125] = _7218; + uint16_t _7219 = (uint16_t)(78); + _curvea0[126] = _7219; + uint16_t _7220 = (uint16_t)(79); + _curvea0[127] = _7220; + uint16_t _7221 = (uint16_t)(79); + _curvea0[128] = _7221; + uint16_t _7222 = (uint16_t)(79); + _curvea0[129] = _7222; + uint16_t _7223 = (uint16_t)(80); + _curvea0[130] = _7223; + uint16_t _7224 = (uint16_t)(80); + _curvea0[131] = _7224; + uint16_t _7225 = (uint16_t)(81); + _curvea0[132] = _7225; + uint16_t _7226 = (uint16_t)(81); + _curvea0[133] = _7226; + uint16_t _7227 = (uint16_t)(82); + _curvea0[134] = _7227; + uint16_t _7228 = (uint16_t)(82); + _curvea0[135] = _7228; + uint16_t _7229 = (uint16_t)(82); + _curvea0[136] = _7229; + uint16_t _7230 = (uint16_t)(83); + _curvea0[137] = _7230; + uint16_t _7231 = (uint16_t)(83); + _curvea0[138] = _7231; + uint16_t _7232 = (uint16_t)(84); + _curvea0[139] = _7232; + uint16_t _7233 = (uint16_t)(84); + _curvea0[140] = _7233; + uint16_t _7234 = (uint16_t)(84); + _curvea0[141] = _7234; + uint16_t _7235 = (uint16_t)(85); + _curvea0[142] = _7235; + uint16_t _7236 = (uint16_t)(85); + _curvea0[143] = _7236; + uint16_t _7237 = (uint16_t)(86); + _curvea0[144] = _7237; + uint16_t _7238 = (uint16_t)(86); + _curvea0[145] = _7238; + uint16_t _7239 = (uint16_t)(86); + _curvea0[146] = _7239; + uint16_t _7240 = (uint16_t)(87); + _curvea0[147] = _7240; + uint16_t _7241 = (uint16_t)(87); + _curvea0[148] = _7241; + uint16_t _7242 = (uint16_t)(88); + _curvea0[149] = _7242; + uint16_t _7243 = (uint16_t)(88); + _curvea0[150] = _7243; + uint16_t _7244 = (uint16_t)(88); + _curvea0[151] = _7244; + uint16_t _7245 = (uint16_t)(89); + _curvea0[152] = _7245; + uint16_t _7246 = (uint16_t)(89); + _curvea0[153] = _7246; + uint16_t _7247 = (uint16_t)(90); + _curvea0[154] = _7247; + uint16_t _7248 = (uint16_t)(90); + _curvea0[155] = _7248; + uint16_t _7249 = (uint16_t)(90); + _curvea0[156] = _7249; + uint16_t _7250 = (uint16_t)(91); + _curvea0[157] = _7250; + uint16_t _7251 = (uint16_t)(91); + _curvea0[158] = _7251; + uint16_t _7252 = (uint16_t)(92); + _curvea0[159] = _7252; + uint16_t _7253 = (uint16_t)(92); + _curvea0[160] = _7253; + uint16_t _7254 = (uint16_t)(92); + _curvea0[161] = _7254; + uint16_t _7255 = (uint16_t)(93); + _curvea0[162] = _7255; + uint16_t _7256 = (uint16_t)(93); + _curvea0[163] = _7256; + uint16_t _7257 = (uint16_t)(93); + _curvea0[164] = _7257; + uint16_t _7258 = (uint16_t)(94); + _curvea0[165] = _7258; + uint16_t _7259 = (uint16_t)(94); + _curvea0[166] = _7259; + uint16_t _7260 = (uint16_t)(95); + _curvea0[167] = _7260; + uint16_t _7261 = (uint16_t)(95); + _curvea0[168] = _7261; + uint16_t _7262 = (uint16_t)(95); + _curvea0[169] = _7262; + uint16_t _7263 = (uint16_t)(96); + _curvea0[170] = _7263; + uint16_t _7264 = (uint16_t)(96); + _curvea0[171] = _7264; + uint16_t _7265 = (uint16_t)(97); + _curvea0[172] = _7265; + uint16_t _7266 = (uint16_t)(97); + _curvea0[173] = _7266; + uint16_t _7267 = (uint16_t)(97); + _curvea0[174] = _7267; + uint16_t _7268 = (uint16_t)(98); + _curvea0[175] = _7268; + uint16_t _7269 = (uint16_t)(98); + _curvea0[176] = _7269; + uint16_t _7270 = (uint16_t)(99); + _curvea0[177] = _7270; + uint16_t _7271 = (uint16_t)(99); + _curvea0[178] = _7271; + uint16_t _7272 = (uint16_t)(99); + _curvea0[179] = _7272; + uint16_t _7273 = (uint16_t)(100); + _curvea0[180] = _7273; + uint16_t _7274 = (uint16_t)(100); + _curvea0[181] = _7274; + uint16_t _7275 = (uint16_t)(100); + _curvea0[182] = _7275; + uint16_t _7276 = (uint16_t)(101); + _curvea0[183] = _7276; + uint16_t _7277 = (uint16_t)(101); + _curvea0[184] = _7277; + uint16_t _7278 = (uint16_t)(102); + _curvea0[185] = _7278; + uint16_t _7279 = (uint16_t)(102); + _curvea0[186] = _7279; + uint16_t _7280 = (uint16_t)(102); + _curvea0[187] = _7280; + uint16_t _7281 = (uint16_t)(103); + _curvea0[188] = _7281; + uint16_t _7282 = (uint16_t)(103); + _curvea0[189] = _7282; + uint16_t _7283 = (uint16_t)(103); + _curvea0[190] = _7283; + uint16_t _7284 = (uint16_t)(104); + _curvea0[191] = _7284; + uint16_t _7285 = (uint16_t)(104); + _curvea0[192] = _7285; + uint16_t _7286 = (uint16_t)(105); + _curvea0[193] = _7286; + uint16_t _7287 = (uint16_t)(105); + _curvea0[194] = _7287; + uint16_t _7288 = (uint16_t)(105); + _curvea0[195] = _7288; + uint16_t _7289 = (uint16_t)(106); + _curvea0[196] = _7289; + uint16_t _7290 = (uint16_t)(106); + _curvea0[197] = _7290; + uint16_t _7291 = (uint16_t)(106); + _curvea0[198] = _7291; + uint16_t _7292 = (uint16_t)(107); + _curvea0[199] = _7292; + uint16_t _7293 = (uint16_t)(107); + _curvea0[200] = _7293; + uint16_t _7294 = (uint16_t)(108); + _curvea0[201] = _7294; + uint16_t _7295 = (uint16_t)(108); + _curvea0[202] = _7295; + uint16_t _7296 = (uint16_t)(108); + _curvea0[203] = _7296; + uint16_t _7297 = (uint16_t)(109); + _curvea0[204] = _7297; + uint16_t _7298 = (uint16_t)(109); + _curvea0[205] = _7298; + uint16_t _7299 = (uint16_t)(109); + _curvea0[206] = _7299; + uint16_t _7300 = (uint16_t)(110); + _curvea0[207] = _7300; + uint16_t _7301 = (uint16_t)(110); + _curvea0[208] = _7301; + uint16_t _7302 = (uint16_t)(111); + _curvea0[209] = _7302; + uint16_t _7303 = (uint16_t)(111); + _curvea0[210] = _7303; + uint16_t _7304 = (uint16_t)(111); + _curvea0[211] = _7304; + uint16_t _7305 = (uint16_t)(112); + _curvea0[212] = _7305; + uint16_t _7306 = (uint16_t)(112); + _curvea0[213] = _7306; + uint16_t _7307 = (uint16_t)(112); + _curvea0[214] = _7307; + uint16_t _7308 = (uint16_t)(113); + _curvea0[215] = _7308; + uint16_t _7309 = (uint16_t)(113); + _curvea0[216] = _7309; + uint16_t _7310 = (uint16_t)(113); + _curvea0[217] = _7310; + uint16_t _7311 = (uint16_t)(114); + _curvea0[218] = _7311; + uint16_t _7312 = (uint16_t)(114); + _curvea0[219] = _7312; + uint16_t _7313 = (uint16_t)(115); + _curvea0[220] = _7313; + uint16_t _7314 = (uint16_t)(115); + _curvea0[221] = _7314; + uint16_t _7315 = (uint16_t)(115); + _curvea0[222] = _7315; + uint16_t _7316 = (uint16_t)(116); + _curvea0[223] = _7316; + uint16_t _7317 = (uint16_t)(116); + _curvea0[224] = _7317; + uint16_t _7318 = (uint16_t)(116); + _curvea0[225] = _7318; + uint16_t _7319 = (uint16_t)(117); + _curvea0[226] = _7319; + uint16_t _7320 = (uint16_t)(117); + _curvea0[227] = _7320; + uint16_t _7321 = (uint16_t)(117); + _curvea0[228] = _7321; + uint16_t _7322 = (uint16_t)(118); + _curvea0[229] = _7322; + uint16_t _7323 = (uint16_t)(118); + _curvea0[230] = _7323; + uint16_t _7324 = (uint16_t)(119); + _curvea0[231] = _7324; + uint16_t _7325 = (uint16_t)(119); + _curvea0[232] = _7325; + uint16_t _7326 = (uint16_t)(119); + _curvea0[233] = _7326; + uint16_t _7327 = (uint16_t)(120); + _curvea0[234] = _7327; + uint16_t _7328 = (uint16_t)(120); + _curvea0[235] = _7328; + uint16_t _7329 = (uint16_t)(120); + _curvea0[236] = _7329; + uint16_t _7330 = (uint16_t)(121); + _curvea0[237] = _7330; + uint16_t _7331 = (uint16_t)(121); + _curvea0[238] = _7331; + uint16_t _7332 = (uint16_t)(121); + _curvea0[239] = _7332; + uint16_t _7333 = (uint16_t)(122); + _curvea0[240] = _7333; + uint16_t _7334 = (uint16_t)(122); + _curvea0[241] = _7334; + uint16_t _7335 = (uint16_t)(123); + _curvea0[242] = _7335; + uint16_t _7336 = (uint16_t)(123); + _curvea0[243] = _7336; + uint16_t _7337 = (uint16_t)(123); + _curvea0[244] = _7337; + uint16_t _7338 = (uint16_t)(124); + _curvea0[245] = _7338; + uint16_t _7339 = (uint16_t)(124); + _curvea0[246] = _7339; + uint16_t _7340 = (uint16_t)(124); + _curvea0[247] = _7340; + uint16_t _7341 = (uint16_t)(125); + _curvea0[248] = _7341; + uint16_t _7342 = (uint16_t)(125); + _curvea0[249] = _7342; + uint16_t _7343 = (uint16_t)(125); + _curvea0[250] = _7343; + uint16_t _7344 = (uint16_t)(126); + _curvea0[251] = _7344; + uint16_t _7345 = (uint16_t)(126); + _curvea0[252] = _7345; + uint16_t _7346 = (uint16_t)(126); + _curvea0[253] = _7346; + uint16_t _7347 = (uint16_t)(127); + _curvea0[254] = _7347; + uint16_t _7348 = (uint16_t)(127); + _curvea0[255] = _7348; + uint16_t _7349 = (uint16_t)(128); + _curvea0[256] = _7349; + uint16_t _7350 = (uint16_t)(128); + _curvea0[257] = _7350; + uint16_t _7351 = (uint16_t)(128); + _curvea0[258] = _7351; + uint16_t _7352 = (uint16_t)(129); + _curvea0[259] = _7352; + uint16_t _7353 = (uint16_t)(129); + _curvea0[260] = _7353; + uint16_t _7354 = (uint16_t)(129); + _curvea0[261] = _7354; + uint16_t _7355 = (uint16_t)(130); + _curvea0[262] = _7355; + uint16_t _7356 = (uint16_t)(130); + _curvea0[263] = _7356; + uint16_t _7357 = (uint16_t)(130); + _curvea0[264] = _7357; + uint16_t _7358 = (uint16_t)(131); + _curvea0[265] = _7358; + uint16_t _7359 = (uint16_t)(131); + _curvea0[266] = _7359; + uint16_t _7360 = (uint16_t)(131); + _curvea0[267] = _7360; + uint16_t _7361 = (uint16_t)(132); + _curvea0[268] = _7361; + uint16_t _7362 = (uint16_t)(132); + _curvea0[269] = _7362; + uint16_t _7363 = (uint16_t)(132); + _curvea0[270] = _7363; + uint16_t _7364 = (uint16_t)(133); + _curvea0[271] = _7364; + uint16_t _7365 = (uint16_t)(133); + _curvea0[272] = _7365; + uint16_t _7366 = (uint16_t)(133); + _curvea0[273] = _7366; + uint16_t _7367 = (uint16_t)(134); + _curvea0[274] = _7367; + uint16_t _7368 = (uint16_t)(134); + _curvea0[275] = _7368; + uint16_t _7369 = (uint16_t)(134); + _curvea0[276] = _7369; + uint16_t _7370 = (uint16_t)(135); + _curvea0[277] = _7370; + uint16_t _7371 = (uint16_t)(135); + _curvea0[278] = _7371; + uint16_t _7372 = (uint16_t)(135); + _curvea0[279] = _7372; + uint16_t _7373 = (uint16_t)(136); + _curvea0[280] = _7373; + uint16_t _7374 = (uint16_t)(136); + _curvea0[281] = _7374; + uint16_t _7375 = (uint16_t)(136); + _curvea0[282] = _7375; + uint16_t _7376 = (uint16_t)(137); + _curvea0[283] = _7376; + uint16_t _7377 = (uint16_t)(137); + _curvea0[284] = _7377; + uint16_t _7378 = (uint16_t)(137); + _curvea0[285] = _7378; + uint16_t _7379 = (uint16_t)(138); + _curvea0[286] = _7379; + uint16_t _7380 = (uint16_t)(138); + _curvea0[287] = _7380; + uint16_t _7381 = (uint16_t)(138); + _curvea0[288] = _7381; + uint16_t _7382 = (uint16_t)(139); + _curvea0[289] = _7382; + uint16_t _7383 = (uint16_t)(139); + _curvea0[290] = _7383; + uint16_t _7384 = (uint16_t)(139); + _curvea0[291] = _7384; + uint16_t _7385 = (uint16_t)(140); + _curvea0[292] = _7385; + uint16_t _7386 = (uint16_t)(140); + _curvea0[293] = _7386; + uint16_t _7387 = (uint16_t)(140); + _curvea0[294] = _7387; + uint16_t _7388 = (uint16_t)(141); + _curvea0[295] = _7388; + uint16_t _7389 = (uint16_t)(141); + _curvea0[296] = _7389; + uint16_t _7390 = (uint16_t)(141); + _curvea0[297] = _7390; + uint16_t _7391 = (uint16_t)(141); + _curvea0[298] = _7391; + uint16_t _7392 = (uint16_t)(142); + _curvea0[299] = _7392; + uint16_t _7393 = (uint16_t)(142); + _curvea0[300] = _7393; + uint16_t _7394 = (uint16_t)(142); + _curvea0[301] = _7394; + uint16_t _7395 = (uint16_t)(143); + _curvea0[302] = _7395; + uint16_t _7396 = (uint16_t)(143); + _curvea0[303] = _7396; + uint16_t _7397 = (uint16_t)(143); + _curvea0[304] = _7397; + uint16_t _7398 = (uint16_t)(144); + _curvea0[305] = _7398; + uint16_t _7399 = (uint16_t)(144); + _curvea0[306] = _7399; + uint16_t _7400 = (uint16_t)(144); + _curvea0[307] = _7400; + uint16_t _7401 = (uint16_t)(145); + _curvea0[308] = _7401; + uint16_t _7402 = (uint16_t)(145); + _curvea0[309] = _7402; + uint16_t _7403 = (uint16_t)(145); + _curvea0[310] = _7403; + uint16_t _7404 = (uint16_t)(145); + _curvea0[311] = _7404; + uint16_t _7405 = (uint16_t)(146); + _curvea0[312] = _7405; + uint16_t _7406 = (uint16_t)(146); + _curvea0[313] = _7406; + uint16_t _7407 = (uint16_t)(146); + _curvea0[314] = _7407; + uint16_t _7408 = (uint16_t)(147); + _curvea0[315] = _7408; + uint16_t _7409 = (uint16_t)(147); + _curvea0[316] = _7409; + uint16_t _7410 = (uint16_t)(147); + _curvea0[317] = _7410; + uint16_t _7411 = (uint16_t)(148); + _curvea0[318] = _7411; + uint16_t _7412 = (uint16_t)(148); + _curvea0[319] = _7412; + uint16_t _7413 = (uint16_t)(148); + _curvea0[320] = _7413; + uint16_t _7414 = (uint16_t)(148); + _curvea0[321] = _7414; + uint16_t _7415 = (uint16_t)(149); + _curvea0[322] = _7415; + uint16_t _7416 = (uint16_t)(149); + _curvea0[323] = _7416; + uint16_t _7417 = (uint16_t)(149); + _curvea0[324] = _7417; + uint16_t _7418 = (uint16_t)(150); + _curvea0[325] = _7418; + uint16_t _7419 = (uint16_t)(150); + _curvea0[326] = _7419; + uint16_t _7420 = (uint16_t)(150); + _curvea0[327] = _7420; + uint16_t _7421 = (uint16_t)(150); + _curvea0[328] = _7421; + uint16_t _7422 = (uint16_t)(151); + _curvea0[329] = _7422; + uint16_t _7423 = (uint16_t)(151); + _curvea0[330] = _7423; + uint16_t _7424 = (uint16_t)(151); + _curvea0[331] = _7424; + uint16_t _7425 = (uint16_t)(152); + _curvea0[332] = _7425; + uint16_t _7426 = (uint16_t)(152); + _curvea0[333] = _7426; + uint16_t _7427 = (uint16_t)(152); + _curvea0[334] = _7427; + uint16_t _7428 = (uint16_t)(152); + _curvea0[335] = _7428; + uint16_t _7429 = (uint16_t)(153); + _curvea0[336] = _7429; + uint16_t _7430 = (uint16_t)(153); + _curvea0[337] = _7430; + uint16_t _7431 = (uint16_t)(153); + _curvea0[338] = _7431; + uint16_t _7432 = (uint16_t)(154); + _curvea0[339] = _7432; + uint16_t _7433 = (uint16_t)(154); + _curvea0[340] = _7433; + uint16_t _7434 = (uint16_t)(154); + _curvea0[341] = _7434; + uint16_t _7435 = (uint16_t)(154); + _curvea0[342] = _7435; + uint16_t _7436 = (uint16_t)(155); + _curvea0[343] = _7436; + uint16_t _7437 = (uint16_t)(155); + _curvea0[344] = _7437; + uint16_t _7438 = (uint16_t)(155); + _curvea0[345] = _7438; + uint16_t _7439 = (uint16_t)(156); + _curvea0[346] = _7439; + uint16_t _7440 = (uint16_t)(156); + _curvea0[347] = _7440; + uint16_t _7441 = (uint16_t)(156); + _curvea0[348] = _7441; + uint16_t _7442 = (uint16_t)(156); + _curvea0[349] = _7442; + uint16_t _7443 = (uint16_t)(157); + _curvea0[350] = _7443; + uint16_t _7444 = (uint16_t)(157); + _curvea0[351] = _7444; + uint16_t _7445 = (uint16_t)(157); + _curvea0[352] = _7445; + uint16_t _7446 = (uint16_t)(157); + _curvea0[353] = _7446; + uint16_t _7447 = (uint16_t)(158); + _curvea0[354] = _7447; + uint16_t _7448 = (uint16_t)(158); + _curvea0[355] = _7448; + uint16_t _7449 = (uint16_t)(158); + _curvea0[356] = _7449; + uint16_t _7450 = (uint16_t)(159); + _curvea0[357] = _7450; + uint16_t _7451 = (uint16_t)(159); + _curvea0[358] = _7451; + uint16_t _7452 = (uint16_t)(159); + _curvea0[359] = _7452; + uint16_t _7453 = (uint16_t)(159); + _curvea0[360] = _7453; + uint16_t _7454 = (uint16_t)(160); + _curvea0[361] = _7454; + uint16_t _7455 = (uint16_t)(160); + _curvea0[362] = _7455; + uint16_t _7456 = (uint16_t)(160); + _curvea0[363] = _7456; + uint16_t _7457 = (uint16_t)(160); + _curvea0[364] = _7457; + uint16_t _7458 = (uint16_t)(161); + _curvea0[365] = _7458; + uint16_t _7459 = (uint16_t)(161); + _curvea0[366] = _7459; + uint16_t _7460 = (uint16_t)(161); + _curvea0[367] = _7460; + uint16_t _7461 = (uint16_t)(161); + _curvea0[368] = _7461; + uint16_t _7462 = (uint16_t)(162); + _curvea0[369] = _7462; + uint16_t _7463 = (uint16_t)(162); + _curvea0[370] = _7463; + uint16_t _7464 = (uint16_t)(162); + _curvea0[371] = _7464; + uint16_t _7465 = (uint16_t)(162); + _curvea0[372] = _7465; + uint16_t _7466 = (uint16_t)(163); + _curvea0[373] = _7466; + uint16_t _7467 = (uint16_t)(163); + _curvea0[374] = _7467; + uint16_t _7468 = (uint16_t)(163); + _curvea0[375] = _7468; + uint16_t _7469 = (uint16_t)(163); + _curvea0[376] = _7469; + uint16_t _7470 = (uint16_t)(164); + _curvea0[377] = _7470; + uint16_t _7471 = (uint16_t)(164); + _curvea0[378] = _7471; + uint16_t _7472 = (uint16_t)(164); + _curvea0[379] = _7472; + uint16_t _7473 = (uint16_t)(164); + _curvea0[380] = _7473; + uint16_t _7474 = (uint16_t)(165); + _curvea0[381] = _7474; + uint16_t _7475 = (uint16_t)(165); + _curvea0[382] = _7475; + uint16_t _7476 = (uint16_t)(165); + _curvea0[383] = _7476; + uint16_t _7477 = (uint16_t)(166); + _curvea0[384] = _7477; + uint16_t _7478 = (uint16_t)(166); + _curvea0[385] = _7478; + uint16_t _7479 = (uint16_t)(166); + _curvea0[386] = _7479; + uint16_t _7480 = (uint16_t)(166); + _curvea0[387] = _7480; + uint16_t _7481 = (uint16_t)(167); + _curvea0[388] = _7481; + uint16_t _7482 = (uint16_t)(167); + _curvea0[389] = _7482; + uint16_t _7483 = (uint16_t)(167); + _curvea0[390] = _7483; + uint16_t _7484 = (uint16_t)(167); + _curvea0[391] = _7484; + uint16_t _7485 = (uint16_t)(167); + _curvea0[392] = _7485; + uint16_t _7486 = (uint16_t)(168); + _curvea0[393] = _7486; + uint16_t _7487 = (uint16_t)(168); + _curvea0[394] = _7487; + uint16_t _7488 = (uint16_t)(168); + _curvea0[395] = _7488; + uint16_t _7489 = (uint16_t)(168); + _curvea0[396] = _7489; + uint16_t _7490 = (uint16_t)(169); + _curvea0[397] = _7490; + uint16_t _7491 = (uint16_t)(169); + _curvea0[398] = _7491; + uint16_t _7492 = (uint16_t)(169); + _curvea0[399] = _7492; + uint16_t _7493 = (uint16_t)(169); + _curvea0[400] = _7493; + uint16_t _7494 = (uint16_t)(170); + _curvea0[401] = _7494; + uint16_t _7495 = (uint16_t)(170); + _curvea0[402] = _7495; + uint16_t _7496 = (uint16_t)(170); + _curvea0[403] = _7496; + uint16_t _7497 = (uint16_t)(170); + _curvea0[404] = _7497; + uint16_t _7498 = (uint16_t)(171); + _curvea0[405] = _7498; + uint16_t _7499 = (uint16_t)(171); + _curvea0[406] = _7499; + uint16_t _7500 = (uint16_t)(171); + _curvea0[407] = _7500; + uint16_t _7501 = (uint16_t)(171); + _curvea0[408] = _7501; + uint16_t _7502 = (uint16_t)(172); + _curvea0[409] = _7502; + uint16_t _7503 = (uint16_t)(172); + _curvea0[410] = _7503; + uint16_t _7504 = (uint16_t)(172); + _curvea0[411] = _7504; + uint16_t _7505 = (uint16_t)(172); + _curvea0[412] = _7505; + uint16_t _7506 = (uint16_t)(173); + _curvea0[413] = _7506; + uint16_t _7507 = (uint16_t)(173); + _curvea0[414] = _7507; + uint16_t _7508 = (uint16_t)(173); + _curvea0[415] = _7508; + uint16_t _7509 = (uint16_t)(173); + _curvea0[416] = _7509; + uint16_t _7510 = (uint16_t)(173); + _curvea0[417] = _7510; + uint16_t _7511 = (uint16_t)(174); + _curvea0[418] = _7511; + uint16_t _7512 = (uint16_t)(174); + _curvea0[419] = _7512; + uint16_t _7513 = (uint16_t)(174); + _curvea0[420] = _7513; + uint16_t _7514 = (uint16_t)(174); + _curvea0[421] = _7514; + uint16_t _7515 = (uint16_t)(175); + _curvea0[422] = _7515; + uint16_t _7516 = (uint16_t)(175); + _curvea0[423] = _7516; + uint16_t _7517 = (uint16_t)(175); + _curvea0[424] = _7517; + uint16_t _7518 = (uint16_t)(175); + _curvea0[425] = _7518; + uint16_t _7519 = (uint16_t)(176); + _curvea0[426] = _7519; + uint16_t _7520 = (uint16_t)(176); + _curvea0[427] = _7520; + uint16_t _7521 = (uint16_t)(176); + _curvea0[428] = _7521; + uint16_t _7522 = (uint16_t)(176); + _curvea0[429] = _7522; + uint16_t _7523 = (uint16_t)(176); + _curvea0[430] = _7523; + uint16_t _7524 = (uint16_t)(177); + _curvea0[431] = _7524; + uint16_t _7525 = (uint16_t)(177); + _curvea0[432] = _7525; + uint16_t _7526 = (uint16_t)(177); + _curvea0[433] = _7526; + uint16_t _7527 = (uint16_t)(177); + _curvea0[434] = _7527; + uint16_t _7528 = (uint16_t)(178); + _curvea0[435] = _7528; + uint16_t _7529 = (uint16_t)(178); + _curvea0[436] = _7529; + uint16_t _7530 = (uint16_t)(178); + _curvea0[437] = _7530; + uint16_t _7531 = (uint16_t)(178); + _curvea0[438] = _7531; + uint16_t _7532 = (uint16_t)(178); + _curvea0[439] = _7532; + uint16_t _7533 = (uint16_t)(179); + _curvea0[440] = _7533; + uint16_t _7534 = (uint16_t)(179); + _curvea0[441] = _7534; + uint16_t _7535 = (uint16_t)(179); + _curvea0[442] = _7535; + uint16_t _7536 = (uint16_t)(179); + _curvea0[443] = _7536; + uint16_t _7537 = (uint16_t)(180); + _curvea0[444] = _7537; + uint16_t _7538 = (uint16_t)(180); + _curvea0[445] = _7538; + uint16_t _7539 = (uint16_t)(180); + _curvea0[446] = _7539; + uint16_t _7540 = (uint16_t)(180); + _curvea0[447] = _7540; + uint16_t _7541 = (uint16_t)(180); + _curvea0[448] = _7541; + uint16_t _7542 = (uint16_t)(181); + _curvea0[449] = _7542; + uint16_t _7543 = (uint16_t)(181); + _curvea0[450] = _7543; + uint16_t _7544 = (uint16_t)(181); + _curvea0[451] = _7544; + uint16_t _7545 = (uint16_t)(181); + _curvea0[452] = _7545; + uint16_t _7546 = (uint16_t)(181); + _curvea0[453] = _7546; + uint16_t _7547 = (uint16_t)(182); + _curvea0[454] = _7547; + uint16_t _7548 = (uint16_t)(182); + _curvea0[455] = _7548; + uint16_t _7549 = (uint16_t)(182); + _curvea0[456] = _7549; + uint16_t _7550 = (uint16_t)(182); + _curvea0[457] = _7550; + uint16_t _7551 = (uint16_t)(183); + _curvea0[458] = _7551; + uint16_t _7552 = (uint16_t)(183); + _curvea0[459] = _7552; + uint16_t _7553 = (uint16_t)(183); + _curvea0[460] = _7553; + uint16_t _7554 = (uint16_t)(183); + _curvea0[461] = _7554; + uint16_t _7555 = (uint16_t)(183); + _curvea0[462] = _7555; + uint16_t _7556 = (uint16_t)(184); + _curvea0[463] = _7556; + uint16_t _7557 = (uint16_t)(184); + _curvea0[464] = _7557; + uint16_t _7558 = (uint16_t)(184); + _curvea0[465] = _7558; + uint16_t _7559 = (uint16_t)(184); + _curvea0[466] = _7559; + uint16_t _7560 = (uint16_t)(184); + _curvea0[467] = _7560; + uint16_t _7561 = (uint16_t)(185); + _curvea0[468] = _7561; + uint16_t _7562 = (uint16_t)(185); + _curvea0[469] = _7562; + uint16_t _7563 = (uint16_t)(185); + _curvea0[470] = _7563; + uint16_t _7564 = (uint16_t)(185); + _curvea0[471] = _7564; + uint16_t _7565 = (uint16_t)(185); + _curvea0[472] = _7565; + uint16_t _7566 = (uint16_t)(186); + _curvea0[473] = _7566; + uint16_t _7567 = (uint16_t)(186); + _curvea0[474] = _7567; + uint16_t _7568 = (uint16_t)(186); + _curvea0[475] = _7568; + uint16_t _7569 = (uint16_t)(186); + _curvea0[476] = _7569; + uint16_t _7570 = (uint16_t)(187); + _curvea0[477] = _7570; + uint16_t _7571 = (uint16_t)(187); + _curvea0[478] = _7571; + uint16_t _7572 = (uint16_t)(187); + _curvea0[479] = _7572; + uint16_t _7573 = (uint16_t)(187); + _curvea0[480] = _7573; + uint16_t _7574 = (uint16_t)(187); + _curvea0[481] = _7574; + uint16_t _7575 = (uint16_t)(188); + _curvea0[482] = _7575; + uint16_t _7576 = (uint16_t)(188); + _curvea0[483] = _7576; + uint16_t _7577 = (uint16_t)(188); + _curvea0[484] = _7577; + uint16_t _7578 = (uint16_t)(188); + _curvea0[485] = _7578; + uint16_t _7579 = (uint16_t)(188); + _curvea0[486] = _7579; + uint16_t _7580 = (uint16_t)(189); + _curvea0[487] = _7580; + uint16_t _7581 = (uint16_t)(189); + _curvea0[488] = _7581; + uint16_t _7582 = (uint16_t)(189); + _curvea0[489] = _7582; + uint16_t _7583 = (uint16_t)(189); + _curvea0[490] = _7583; + uint16_t _7584 = (uint16_t)(189); + _curvea0[491] = _7584; + uint16_t _7585 = (uint16_t)(190); + _curvea0[492] = _7585; + uint16_t _7586 = (uint16_t)(190); + _curvea0[493] = _7586; + uint16_t _7587 = (uint16_t)(190); + _curvea0[494] = _7587; + uint16_t _7588 = (uint16_t)(190); + _curvea0[495] = _7588; + uint16_t _7589 = (uint16_t)(190); + _curvea0[496] = _7589; + uint16_t _7590 = (uint16_t)(190); + _curvea0[497] = _7590; + uint16_t _7591 = (uint16_t)(191); + _curvea0[498] = _7591; + uint16_t _7592 = (uint16_t)(191); + _curvea0[499] = _7592; + uint16_t _7593 = (uint16_t)(191); + _curvea0[500] = _7593; + uint16_t _7594 = (uint16_t)(191); + _curvea0[501] = _7594; + uint16_t _7595 = (uint16_t)(191); + _curvea0[502] = _7595; + uint16_t _7596 = (uint16_t)(192); + _curvea0[503] = _7596; + uint16_t _7597 = (uint16_t)(192); + _curvea0[504] = _7597; + uint16_t _7598 = (uint16_t)(192); + _curvea0[505] = _7598; + uint16_t _7599 = (uint16_t)(192); + _curvea0[506] = _7599; + uint16_t _7600 = (uint16_t)(192); + _curvea0[507] = _7600; + uint16_t _7601 = (uint16_t)(193); + _curvea0[508] = _7601; + uint16_t _7602 = (uint16_t)(193); + _curvea0[509] = _7602; + uint16_t _7603 = (uint16_t)(193); + _curvea0[510] = _7603; + uint16_t _7604 = (uint16_t)(193); + _curvea0[511] = _7604; + uint16_t _7605 = (uint16_t)(193); + _curvea0[512] = _7605; + uint16_t _7606 = (uint16_t)(194); + _curvea0[513] = _7606; + uint16_t _7607 = (uint16_t)(194); + _curvea0[514] = _7607; + uint16_t _7608 = (uint16_t)(194); + _curvea0[515] = _7608; + uint16_t _7609 = (uint16_t)(194); + _curvea0[516] = _7609; + uint16_t _7610 = (uint16_t)(194); + _curvea0[517] = _7610; + uint16_t _7611 = (uint16_t)(195); + _curvea0[518] = _7611; + uint16_t _7612 = (uint16_t)(195); + _curvea0[519] = _7612; + uint16_t _7613 = (uint16_t)(195); + _curvea0[520] = _7613; + uint16_t _7614 = (uint16_t)(195); + _curvea0[521] = _7614; + uint16_t _7615 = (uint16_t)(195); + _curvea0[522] = _7615; + uint16_t _7616 = (uint16_t)(195); + _curvea0[523] = _7616; + uint16_t _7617 = (uint16_t)(196); + _curvea0[524] = _7617; + uint16_t _7618 = (uint16_t)(196); + _curvea0[525] = _7618; + uint16_t _7619 = (uint16_t)(196); + _curvea0[526] = _7619; + uint16_t _7620 = (uint16_t)(196); + _curvea0[527] = _7620; + uint16_t _7621 = (uint16_t)(196); + _curvea0[528] = _7621; + uint16_t _7622 = (uint16_t)(197); + _curvea0[529] = _7622; + uint16_t _7623 = (uint16_t)(197); + _curvea0[530] = _7623; + uint16_t _7624 = (uint16_t)(197); + _curvea0[531] = _7624; + uint16_t _7625 = (uint16_t)(197); + _curvea0[532] = _7625; + uint16_t _7626 = (uint16_t)(197); + _curvea0[533] = _7626; + uint16_t _7627 = (uint16_t)(197); + _curvea0[534] = _7627; + uint16_t _7628 = (uint16_t)(198); + _curvea0[535] = _7628; + uint16_t _7629 = (uint16_t)(198); + _curvea0[536] = _7629; + uint16_t _7630 = (uint16_t)(198); + _curvea0[537] = _7630; + uint16_t _7631 = (uint16_t)(198); + _curvea0[538] = _7631; + uint16_t _7632 = (uint16_t)(198); + _curvea0[539] = _7632; + uint16_t _7633 = (uint16_t)(199); + _curvea0[540] = _7633; + uint16_t _7634 = (uint16_t)(199); + _curvea0[541] = _7634; + uint16_t _7635 = (uint16_t)(199); + _curvea0[542] = _7635; + uint16_t _7636 = (uint16_t)(199); + _curvea0[543] = _7636; + uint16_t _7637 = (uint16_t)(199); + _curvea0[544] = _7637; + uint16_t _7638 = (uint16_t)(199); + _curvea0[545] = _7638; + uint16_t _7639 = (uint16_t)(200); + _curvea0[546] = _7639; + uint16_t _7640 = (uint16_t)(200); + _curvea0[547] = _7640; + uint16_t _7641 = (uint16_t)(200); + _curvea0[548] = _7641; + uint16_t _7642 = (uint16_t)(200); + _curvea0[549] = _7642; + uint16_t _7643 = (uint16_t)(200); + _curvea0[550] = _7643; + uint16_t _7644 = (uint16_t)(200); + _curvea0[551] = _7644; + uint16_t _7645 = (uint16_t)(201); + _curvea0[552] = _7645; + uint16_t _7646 = (uint16_t)(201); + _curvea0[553] = _7646; + uint16_t _7647 = (uint16_t)(201); + _curvea0[554] = _7647; + uint16_t _7648 = (uint16_t)(201); + _curvea0[555] = _7648; + uint16_t _7649 = (uint16_t)(201); + _curvea0[556] = _7649; + uint16_t _7650 = (uint16_t)(202); + _curvea0[557] = _7650; + uint16_t _7651 = (uint16_t)(202); + _curvea0[558] = _7651; + uint16_t _7652 = (uint16_t)(202); + _curvea0[559] = _7652; + uint16_t _7653 = (uint16_t)(202); + _curvea0[560] = _7653; + uint16_t _7654 = (uint16_t)(202); + _curvea0[561] = _7654; + uint16_t _7655 = (uint16_t)(202); + _curvea0[562] = _7655; + uint16_t _7656 = (uint16_t)(203); + _curvea0[563] = _7656; + uint16_t _7657 = (uint16_t)(203); + _curvea0[564] = _7657; + uint16_t _7658 = (uint16_t)(203); + _curvea0[565] = _7658; + uint16_t _7659 = (uint16_t)(203); + _curvea0[566] = _7659; + uint16_t _7660 = (uint16_t)(203); + _curvea0[567] = _7660; + uint16_t _7661 = (uint16_t)(203); + _curvea0[568] = _7661; + uint16_t _7662 = (uint16_t)(204); + _curvea0[569] = _7662; + uint16_t _7663 = (uint16_t)(204); + _curvea0[570] = _7663; + uint16_t _7664 = (uint16_t)(204); + _curvea0[571] = _7664; + uint16_t _7665 = (uint16_t)(204); + _curvea0[572] = _7665; + uint16_t _7666 = (uint16_t)(204); + _curvea0[573] = _7666; + uint16_t _7667 = (uint16_t)(204); + _curvea0[574] = _7667; + uint16_t _7668 = (uint16_t)(205); + _curvea0[575] = _7668; + uint16_t _7669 = (uint16_t)(205); + _curvea0[576] = _7669; + uint16_t _7670 = (uint16_t)(205); + _curvea0[577] = _7670; + uint16_t _7671 = (uint16_t)(205); + _curvea0[578] = _7671; + uint16_t _7672 = (uint16_t)(205); + _curvea0[579] = _7672; + uint16_t _7673 = (uint16_t)(205); + _curvea0[580] = _7673; + uint16_t _7674 = (uint16_t)(206); + _curvea0[581] = _7674; + uint16_t _7675 = (uint16_t)(206); + _curvea0[582] = _7675; + uint16_t _7676 = (uint16_t)(206); + _curvea0[583] = _7676; + uint16_t _7677 = (uint16_t)(206); + _curvea0[584] = _7677; + uint16_t _7678 = (uint16_t)(206); + _curvea0[585] = _7678; + uint16_t _7679 = (uint16_t)(206); + _curvea0[586] = _7679; + uint16_t _7680 = (uint16_t)(207); + _curvea0[587] = _7680; + uint16_t _7681 = (uint16_t)(207); + _curvea0[588] = _7681; + uint16_t _7682 = (uint16_t)(207); + _curvea0[589] = _7682; + uint16_t _7683 = (uint16_t)(207); + _curvea0[590] = _7683; + uint16_t _7684 = (uint16_t)(207); + _curvea0[591] = _7684; + uint16_t _7685 = (uint16_t)(207); + _curvea0[592] = _7685; + uint16_t _7686 = (uint16_t)(208); + _curvea0[593] = _7686; + uint16_t _7687 = (uint16_t)(208); + _curvea0[594] = _7687; + uint16_t _7688 = (uint16_t)(208); + _curvea0[595] = _7688; + uint16_t _7689 = (uint16_t)(208); + _curvea0[596] = _7689; + uint16_t _7690 = (uint16_t)(208); + _curvea0[597] = _7690; + uint16_t _7691 = (uint16_t)(208); + _curvea0[598] = _7691; + uint16_t _7692 = (uint16_t)(209); + _curvea0[599] = _7692; + uint16_t _7693 = (uint16_t)(209); + _curvea0[600] = _7693; + uint16_t _7694 = (uint16_t)(209); + _curvea0[601] = _7694; + uint16_t _7695 = (uint16_t)(209); + _curvea0[602] = _7695; + uint16_t _7696 = (uint16_t)(209); + _curvea0[603] = _7696; + uint16_t _7697 = (uint16_t)(209); + _curvea0[604] = _7697; + uint16_t _7698 = (uint16_t)(209); + _curvea0[605] = _7698; + uint16_t _7699 = (uint16_t)(210); + _curvea0[606] = _7699; + uint16_t _7700 = (uint16_t)(210); + _curvea0[607] = _7700; + uint16_t _7701 = (uint16_t)(210); + _curvea0[608] = _7701; + uint16_t _7702 = (uint16_t)(210); + _curvea0[609] = _7702; + uint16_t _7703 = (uint16_t)(210); + _curvea0[610] = _7703; + uint16_t _7704 = (uint16_t)(210); + _curvea0[611] = _7704; + uint16_t _7705 = (uint16_t)(211); + _curvea0[612] = _7705; + uint16_t _7706 = (uint16_t)(211); + _curvea0[613] = _7706; + uint16_t _7707 = (uint16_t)(211); + _curvea0[614] = _7707; + uint16_t _7708 = (uint16_t)(211); + _curvea0[615] = _7708; + uint16_t _7709 = (uint16_t)(211); + _curvea0[616] = _7709; + uint16_t _7710 = (uint16_t)(211); + _curvea0[617] = _7710; + uint16_t _7711 = (uint16_t)(211); + _curvea0[618] = _7711; + uint16_t _7712 = (uint16_t)(212); + _curvea0[619] = _7712; + uint16_t _7713 = (uint16_t)(212); + _curvea0[620] = _7713; + uint16_t _7714 = (uint16_t)(212); + _curvea0[621] = _7714; + uint16_t _7715 = (uint16_t)(212); + _curvea0[622] = _7715; + uint16_t _7716 = (uint16_t)(212); + _curvea0[623] = _7716; + uint16_t _7717 = (uint16_t)(212); + _curvea0[624] = _7717; + uint16_t _7718 = (uint16_t)(213); + _curvea0[625] = _7718; + uint16_t _7719 = (uint16_t)(213); + _curvea0[626] = _7719; + uint16_t _7720 = (uint16_t)(213); + _curvea0[627] = _7720; + uint16_t _7721 = (uint16_t)(213); + _curvea0[628] = _7721; + uint16_t _7722 = (uint16_t)(213); + _curvea0[629] = _7722; + uint16_t _7723 = (uint16_t)(213); + _curvea0[630] = _7723; + uint16_t _7724 = (uint16_t)(213); + _curvea0[631] = _7724; + uint16_t _7725 = (uint16_t)(214); + _curvea0[632] = _7725; + uint16_t _7726 = (uint16_t)(214); + _curvea0[633] = _7726; + uint16_t _7727 = (uint16_t)(214); + _curvea0[634] = _7727; + uint16_t _7728 = (uint16_t)(214); + _curvea0[635] = _7728; + uint16_t _7729 = (uint16_t)(214); + _curvea0[636] = _7729; + uint16_t _7730 = (uint16_t)(214); + _curvea0[637] = _7730; + uint16_t _7731 = (uint16_t)(214); + _curvea0[638] = _7731; + uint16_t _7732 = (uint16_t)(215); + _curvea0[639] = _7732; + uint16_t _7733 = (uint16_t)(215); + _curvea0[640] = _7733; + uint16_t _7734 = (uint16_t)(215); + _curvea0[641] = _7734; + uint16_t _7735 = (uint16_t)(215); + _curvea0[642] = _7735; + uint16_t _7736 = (uint16_t)(215); + _curvea0[643] = _7736; + uint16_t _7737 = (uint16_t)(215); + _curvea0[644] = _7737; + uint16_t _7738 = (uint16_t)(216); + _curvea0[645] = _7738; + uint16_t _7739 = (uint16_t)(216); + _curvea0[646] = _7739; + uint16_t _7740 = (uint16_t)(216); + _curvea0[647] = _7740; + uint16_t _7741 = (uint16_t)(216); + _curvea0[648] = _7741; + uint16_t _7742 = (uint16_t)(216); + _curvea0[649] = _7742; + uint16_t _7743 = (uint16_t)(216); + _curvea0[650] = _7743; + uint16_t _7744 = (uint16_t)(216); + _curvea0[651] = _7744; + uint16_t _7745 = (uint16_t)(217); + _curvea0[652] = _7745; + uint16_t _7746 = (uint16_t)(217); + _curvea0[653] = _7746; + uint16_t _7747 = (uint16_t)(217); + _curvea0[654] = _7747; + uint16_t _7748 = (uint16_t)(217); + _curvea0[655] = _7748; + uint16_t _7749 = (uint16_t)(217); + _curvea0[656] = _7749; + uint16_t _7750 = (uint16_t)(217); + _curvea0[657] = _7750; + uint16_t _7751 = (uint16_t)(217); + _curvea0[658] = _7751; + uint16_t _7752 = (uint16_t)(218); + _curvea0[659] = _7752; + uint16_t _7753 = (uint16_t)(218); + _curvea0[660] = _7753; + uint16_t _7754 = (uint16_t)(218); + _curvea0[661] = _7754; + uint16_t _7755 = (uint16_t)(218); + _curvea0[662] = _7755; + uint16_t _7756 = (uint16_t)(218); + _curvea0[663] = _7756; + uint16_t _7757 = (uint16_t)(218); + _curvea0[664] = _7757; + uint16_t _7758 = (uint16_t)(218); + _curvea0[665] = _7758; + uint16_t _7759 = (uint16_t)(219); + _curvea0[666] = _7759; + uint16_t _7760 = (uint16_t)(219); + _curvea0[667] = _7760; + uint16_t _7761 = (uint16_t)(219); + _curvea0[668] = _7761; + uint16_t _7762 = (uint16_t)(219); + _curvea0[669] = _7762; + uint16_t _7763 = (uint16_t)(219); + _curvea0[670] = _7763; + uint16_t _7764 = (uint16_t)(219); + _curvea0[671] = _7764; + uint16_t _7765 = (uint16_t)(219); + _curvea0[672] = _7765; + uint16_t _7766 = (uint16_t)(220); + _curvea0[673] = _7766; + uint16_t _7767 = (uint16_t)(220); + _curvea0[674] = _7767; + uint16_t _7768 = (uint16_t)(220); + _curvea0[675] = _7768; + uint16_t _7769 = (uint16_t)(220); + _curvea0[676] = _7769; + uint16_t _7770 = (uint16_t)(220); + _curvea0[677] = _7770; + uint16_t _7771 = (uint16_t)(220); + _curvea0[678] = _7771; + uint16_t _7772 = (uint16_t)(220); + _curvea0[679] = _7772; + uint16_t _7773 = (uint16_t)(220); + _curvea0[680] = _7773; + uint16_t _7774 = (uint16_t)(221); + _curvea0[681] = _7774; + uint16_t _7775 = (uint16_t)(221); + _curvea0[682] = _7775; + uint16_t _7776 = (uint16_t)(221); + _curvea0[683] = _7776; + uint16_t _7777 = (uint16_t)(221); + _curvea0[684] = _7777; + uint16_t _7778 = (uint16_t)(221); + _curvea0[685] = _7778; + uint16_t _7779 = (uint16_t)(221); + _curvea0[686] = _7779; + uint16_t _7780 = (uint16_t)(221); + _curvea0[687] = _7780; + uint16_t _7781 = (uint16_t)(222); + _curvea0[688] = _7781; + uint16_t _7782 = (uint16_t)(222); + _curvea0[689] = _7782; + uint16_t _7783 = (uint16_t)(222); + _curvea0[690] = _7783; + uint16_t _7784 = (uint16_t)(222); + _curvea0[691] = _7784; + uint16_t _7785 = (uint16_t)(222); + _curvea0[692] = _7785; + uint16_t _7786 = (uint16_t)(222); + _curvea0[693] = _7786; + uint16_t _7787 = (uint16_t)(222); + _curvea0[694] = _7787; + uint16_t _7788 = (uint16_t)(223); + _curvea0[695] = _7788; + uint16_t _7789 = (uint16_t)(223); + _curvea0[696] = _7789; + uint16_t _7790 = (uint16_t)(223); + _curvea0[697] = _7790; + uint16_t _7791 = (uint16_t)(223); + _curvea0[698] = _7791; + uint16_t _7792 = (uint16_t)(223); + _curvea0[699] = _7792; + uint16_t _7793 = (uint16_t)(223); + _curvea0[700] = _7793; + uint16_t _7794 = (uint16_t)(223); + _curvea0[701] = _7794; + uint16_t _7795 = (uint16_t)(223); + _curvea0[702] = _7795; + uint16_t _7796 = (uint16_t)(224); + _curvea0[703] = _7796; + uint16_t _7797 = (uint16_t)(224); + _curvea0[704] = _7797; + uint16_t _7798 = (uint16_t)(224); + _curvea0[705] = _7798; + uint16_t _7799 = (uint16_t)(224); + _curvea0[706] = _7799; + uint16_t _7800 = (uint16_t)(224); + _curvea0[707] = _7800; + uint16_t _7801 = (uint16_t)(224); + _curvea0[708] = _7801; + uint16_t _7802 = (uint16_t)(224); + _curvea0[709] = _7802; + uint16_t _7803 = (uint16_t)(224); + _curvea0[710] = _7803; + uint16_t _7804 = (uint16_t)(225); + _curvea0[711] = _7804; + uint16_t _7805 = (uint16_t)(225); + _curvea0[712] = _7805; + uint16_t _7806 = (uint16_t)(225); + _curvea0[713] = _7806; + uint16_t _7807 = (uint16_t)(225); + _curvea0[714] = _7807; + uint16_t _7808 = (uint16_t)(225); + _curvea0[715] = _7808; + uint16_t _7809 = (uint16_t)(225); + _curvea0[716] = _7809; + uint16_t _7810 = (uint16_t)(225); + _curvea0[717] = _7810; + uint16_t _7811 = (uint16_t)(226); + _curvea0[718] = _7811; + uint16_t _7812 = (uint16_t)(226); + _curvea0[719] = _7812; + uint16_t _7813 = (uint16_t)(226); + _curvea0[720] = _7813; + uint16_t _7814 = (uint16_t)(226); + _curvea0[721] = _7814; + uint16_t _7815 = (uint16_t)(226); + _curvea0[722] = _7815; + uint16_t _7816 = (uint16_t)(226); + _curvea0[723] = _7816; + uint16_t _7817 = (uint16_t)(226); + _curvea0[724] = _7817; + uint16_t _7818 = (uint16_t)(226); + _curvea0[725] = _7818; + uint16_t _7819 = (uint16_t)(227); + _curvea0[726] = _7819; + uint16_t _7820 = (uint16_t)(227); + _curvea0[727] = _7820; + uint16_t _7821 = (uint16_t)(227); + _curvea0[728] = _7821; + uint16_t _7822 = (uint16_t)(227); + _curvea0[729] = _7822; + uint16_t _7823 = (uint16_t)(227); + _curvea0[730] = _7823; + uint16_t _7824 = (uint16_t)(227); + _curvea0[731] = _7824; + uint16_t _7825 = (uint16_t)(227); + _curvea0[732] = _7825; + uint16_t _7826 = (uint16_t)(227); + _curvea0[733] = _7826; + uint16_t _7827 = (uint16_t)(228); + _curvea0[734] = _7827; + uint16_t _7828 = (uint16_t)(228); + _curvea0[735] = _7828; + uint16_t _7829 = (uint16_t)(228); + _curvea0[736] = _7829; + uint16_t _7830 = (uint16_t)(228); + _curvea0[737] = _7830; + uint16_t _7831 = (uint16_t)(228); + _curvea0[738] = _7831; + uint16_t _7832 = (uint16_t)(228); + _curvea0[739] = _7832; + uint16_t _7833 = (uint16_t)(228); + _curvea0[740] = _7833; + uint16_t _7834 = (uint16_t)(228); + _curvea0[741] = _7834; + uint16_t _7835 = (uint16_t)(228); + _curvea0[742] = _7835; + uint16_t _7836 = (uint16_t)(229); + _curvea0[743] = _7836; + uint16_t _7837 = (uint16_t)(229); + _curvea0[744] = _7837; + uint16_t _7838 = (uint16_t)(229); + _curvea0[745] = _7838; + uint16_t _7839 = (uint16_t)(229); + _curvea0[746] = _7839; + uint16_t _7840 = (uint16_t)(229); + _curvea0[747] = _7840; + uint16_t _7841 = (uint16_t)(229); + _curvea0[748] = _7841; + uint16_t _7842 = (uint16_t)(229); + _curvea0[749] = _7842; + uint16_t _7843 = (uint16_t)(229); + _curvea0[750] = _7843; + uint16_t _7844 = (uint16_t)(230); + _curvea0[751] = _7844; + uint16_t _7845 = (uint16_t)(230); + _curvea0[752] = _7845; + uint16_t _7846 = (uint16_t)(230); + _curvea0[753] = _7846; + uint16_t _7847 = (uint16_t)(230); + _curvea0[754] = _7847; + uint16_t _7848 = (uint16_t)(230); + _curvea0[755] = _7848; + uint16_t _7849 = (uint16_t)(230); + _curvea0[756] = _7849; + uint16_t _7850 = (uint16_t)(230); + _curvea0[757] = _7850; + uint16_t _7851 = (uint16_t)(230); + _curvea0[758] = _7851; + uint16_t _7852 = (uint16_t)(231); + _curvea0[759] = _7852; + uint16_t _7853 = (uint16_t)(231); + _curvea0[760] = _7853; + uint16_t _7854 = (uint16_t)(231); + _curvea0[761] = _7854; + uint16_t _7855 = (uint16_t)(231); + _curvea0[762] = _7855; + uint16_t _7856 = (uint16_t)(231); + _curvea0[763] = _7856; + uint16_t _7857 = (uint16_t)(231); + _curvea0[764] = _7857; + uint16_t _7858 = (uint16_t)(231); + _curvea0[765] = _7858; + uint16_t _7859 = (uint16_t)(231); + _curvea0[766] = _7859; + uint16_t _7860 = (uint16_t)(231); + _curvea0[767] = _7860; + uint16_t _7861 = (uint16_t)(232); + _curvea0[768] = _7861; + uint16_t _7862 = (uint16_t)(232); + _curvea0[769] = _7862; + uint16_t _7863 = (uint16_t)(232); + _curvea0[770] = _7863; + uint16_t _7864 = (uint16_t)(232); + _curvea0[771] = _7864; + uint16_t _7865 = (uint16_t)(232); + _curvea0[772] = _7865; + uint16_t _7866 = (uint16_t)(232); + _curvea0[773] = _7866; + uint16_t _7867 = (uint16_t)(232); + _curvea0[774] = _7867; + uint16_t _7868 = (uint16_t)(232); + _curvea0[775] = _7868; + uint16_t _7869 = (uint16_t)(233); + _curvea0[776] = _7869; + uint16_t _7870 = (uint16_t)(233); + _curvea0[777] = _7870; + uint16_t _7871 = (uint16_t)(233); + _curvea0[778] = _7871; + uint16_t _7872 = (uint16_t)(233); + _curvea0[779] = _7872; + uint16_t _7873 = (uint16_t)(233); + _curvea0[780] = _7873; + uint16_t _7874 = (uint16_t)(233); + _curvea0[781] = _7874; + uint16_t _7875 = (uint16_t)(233); + _curvea0[782] = _7875; + uint16_t _7876 = (uint16_t)(233); + _curvea0[783] = _7876; + uint16_t _7877 = (uint16_t)(233); + _curvea0[784] = _7877; + uint16_t _7878 = (uint16_t)(234); + _curvea0[785] = _7878; + uint16_t _7879 = (uint16_t)(234); + _curvea0[786] = _7879; + uint16_t _7880 = (uint16_t)(234); + _curvea0[787] = _7880; + uint16_t _7881 = (uint16_t)(234); + _curvea0[788] = _7881; + uint16_t _7882 = (uint16_t)(234); + _curvea0[789] = _7882; + uint16_t _7883 = (uint16_t)(234); + _curvea0[790] = _7883; + uint16_t _7884 = (uint16_t)(234); + _curvea0[791] = _7884; + uint16_t _7885 = (uint16_t)(234); + _curvea0[792] = _7885; + uint16_t _7886 = (uint16_t)(234); + _curvea0[793] = _7886; + uint16_t _7887 = (uint16_t)(235); + _curvea0[794] = _7887; + uint16_t _7888 = (uint16_t)(235); + _curvea0[795] = _7888; + uint16_t _7889 = (uint16_t)(235); + _curvea0[796] = _7889; + uint16_t _7890 = (uint16_t)(235); + _curvea0[797] = _7890; + uint16_t _7891 = (uint16_t)(235); + _curvea0[798] = _7891; + uint16_t _7892 = (uint16_t)(235); + _curvea0[799] = _7892; + uint16_t _7893 = (uint16_t)(235); + _curvea0[800] = _7893; + uint16_t _7894 = (uint16_t)(235); + _curvea0[801] = _7894; + uint16_t _7895 = (uint16_t)(235); + _curvea0[802] = _7895; + uint16_t _7896 = (uint16_t)(236); + _curvea0[803] = _7896; + uint16_t _7897 = (uint16_t)(236); + _curvea0[804] = _7897; + uint16_t _7898 = (uint16_t)(236); + _curvea0[805] = _7898; + uint16_t _7899 = (uint16_t)(236); + _curvea0[806] = _7899; + uint16_t _7900 = (uint16_t)(236); + _curvea0[807] = _7900; + uint16_t _7901 = (uint16_t)(236); + _curvea0[808] = _7901; + uint16_t _7902 = (uint16_t)(236); + _curvea0[809] = _7902; + uint16_t _7903 = (uint16_t)(236); + _curvea0[810] = _7903; + uint16_t _7904 = (uint16_t)(236); + _curvea0[811] = _7904; + uint16_t _7905 = (uint16_t)(237); + _curvea0[812] = _7905; + uint16_t _7906 = (uint16_t)(237); + _curvea0[813] = _7906; + uint16_t _7907 = (uint16_t)(237); + _curvea0[814] = _7907; + uint16_t _7908 = (uint16_t)(237); + _curvea0[815] = _7908; + uint16_t _7909 = (uint16_t)(237); + _curvea0[816] = _7909; + uint16_t _7910 = (uint16_t)(237); + _curvea0[817] = _7910; + uint16_t _7911 = (uint16_t)(237); + _curvea0[818] = _7911; + uint16_t _7912 = (uint16_t)(237); + _curvea0[819] = _7912; + uint16_t _7913 = (uint16_t)(237); + _curvea0[820] = _7913; + uint16_t _7914 = (uint16_t)(237); + _curvea0[821] = _7914; + uint16_t _7915 = (uint16_t)(238); + _curvea0[822] = _7915; + uint16_t _7916 = (uint16_t)(238); + _curvea0[823] = _7916; + uint16_t _7917 = (uint16_t)(238); + _curvea0[824] = _7917; + uint16_t _7918 = (uint16_t)(238); + _curvea0[825] = _7918; + uint16_t _7919 = (uint16_t)(238); + _curvea0[826] = _7919; + uint16_t _7920 = (uint16_t)(238); + _curvea0[827] = _7920; + uint16_t _7921 = (uint16_t)(238); + _curvea0[828] = _7921; + uint16_t _7922 = (uint16_t)(238); + _curvea0[829] = _7922; + uint16_t _7923 = (uint16_t)(238); + _curvea0[830] = _7923; + uint16_t _7924 = (uint16_t)(239); + _curvea0[831] = _7924; + uint16_t _7925 = (uint16_t)(239); + _curvea0[832] = _7925; + uint16_t _7926 = (uint16_t)(239); + _curvea0[833] = _7926; + uint16_t _7927 = (uint16_t)(239); + _curvea0[834] = _7927; + uint16_t _7928 = (uint16_t)(239); + _curvea0[835] = _7928; + uint16_t _7929 = (uint16_t)(239); + _curvea0[836] = _7929; + uint16_t _7930 = (uint16_t)(239); + _curvea0[837] = _7930; + uint16_t _7931 = (uint16_t)(239); + _curvea0[838] = _7931; + uint16_t _7932 = (uint16_t)(239); + _curvea0[839] = _7932; + uint16_t _7933 = (uint16_t)(239); + _curvea0[840] = _7933; + uint16_t _7934 = (uint16_t)(240); + _curvea0[841] = _7934; + uint16_t _7935 = (uint16_t)(240); + _curvea0[842] = _7935; + uint16_t _7936 = (uint16_t)(240); + _curvea0[843] = _7936; + uint16_t _7937 = (uint16_t)(240); + _curvea0[844] = _7937; + uint16_t _7938 = (uint16_t)(240); + _curvea0[845] = _7938; + uint16_t _7939 = (uint16_t)(240); + _curvea0[846] = _7939; + uint16_t _7940 = (uint16_t)(240); + _curvea0[847] = _7940; + uint16_t _7941 = (uint16_t)(240); + _curvea0[848] = _7941; + uint16_t _7942 = (uint16_t)(240); + _curvea0[849] = _7942; + uint16_t _7943 = (uint16_t)(240); + _curvea0[850] = _7943; + uint16_t _7944 = (uint16_t)(241); + _curvea0[851] = _7944; + uint16_t _7945 = (uint16_t)(241); + _curvea0[852] = _7945; + uint16_t _7946 = (uint16_t)(241); + _curvea0[853] = _7946; + uint16_t _7947 = (uint16_t)(241); + _curvea0[854] = _7947; + uint16_t _7948 = (uint16_t)(241); + _curvea0[855] = _7948; + uint16_t _7949 = (uint16_t)(241); + _curvea0[856] = _7949; + uint16_t _7950 = (uint16_t)(241); + _curvea0[857] = _7950; + uint16_t _7951 = (uint16_t)(241); + _curvea0[858] = _7951; + uint16_t _7952 = (uint16_t)(241); + _curvea0[859] = _7952; + uint16_t _7953 = (uint16_t)(241); + _curvea0[860] = _7953; + uint16_t _7954 = (uint16_t)(242); + _curvea0[861] = _7954; + uint16_t _7955 = (uint16_t)(242); + _curvea0[862] = _7955; + uint16_t _7956 = (uint16_t)(242); + _curvea0[863] = _7956; + uint16_t _7957 = (uint16_t)(242); + _curvea0[864] = _7957; + uint16_t _7958 = (uint16_t)(242); + _curvea0[865] = _7958; + uint16_t _7959 = (uint16_t)(242); + _curvea0[866] = _7959; + uint16_t _7960 = (uint16_t)(242); + _curvea0[867] = _7960; + uint16_t _7961 = (uint16_t)(242); + _curvea0[868] = _7961; + uint16_t _7962 = (uint16_t)(242); + _curvea0[869] = _7962; + uint16_t _7963 = (uint16_t)(242); + _curvea0[870] = _7963; + uint16_t _7964 = (uint16_t)(243); + _curvea0[871] = _7964; + uint16_t _7965 = (uint16_t)(243); + _curvea0[872] = _7965; + uint16_t _7966 = (uint16_t)(243); + _curvea0[873] = _7966; + uint16_t _7967 = (uint16_t)(243); + _curvea0[874] = _7967; + uint16_t _7968 = (uint16_t)(243); + _curvea0[875] = _7968; + uint16_t _7969 = (uint16_t)(243); + _curvea0[876] = _7969; + uint16_t _7970 = (uint16_t)(243); + _curvea0[877] = _7970; + uint16_t _7971 = (uint16_t)(243); + _curvea0[878] = _7971; + uint16_t _7972 = (uint16_t)(243); + _curvea0[879] = _7972; + uint16_t _7973 = (uint16_t)(243); + _curvea0[880] = _7973; + uint16_t _7974 = (uint16_t)(244); + _curvea0[881] = _7974; + uint16_t _7975 = (uint16_t)(244); + _curvea0[882] = _7975; + uint16_t _7976 = (uint16_t)(244); + _curvea0[883] = _7976; + uint16_t _7977 = (uint16_t)(244); + _curvea0[884] = _7977; + uint16_t _7978 = (uint16_t)(244); + _curvea0[885] = _7978; + uint16_t _7979 = (uint16_t)(244); + _curvea0[886] = _7979; + uint16_t _7980 = (uint16_t)(244); + _curvea0[887] = _7980; + uint16_t _7981 = (uint16_t)(244); + _curvea0[888] = _7981; + uint16_t _7982 = (uint16_t)(244); + _curvea0[889] = _7982; + uint16_t _7983 = (uint16_t)(244); + _curvea0[890] = _7983; + uint16_t _7984 = (uint16_t)(244); + _curvea0[891] = _7984; + uint16_t _7985 = (uint16_t)(245); + _curvea0[892] = _7985; + uint16_t _7986 = (uint16_t)(245); + _curvea0[893] = _7986; + uint16_t _7987 = (uint16_t)(245); + _curvea0[894] = _7987; + uint16_t _7988 = (uint16_t)(245); + _curvea0[895] = _7988; + uint16_t _7989 = (uint16_t)(245); + _curvea0[896] = _7989; + uint16_t _7990 = (uint16_t)(245); + _curvea0[897] = _7990; + uint16_t _7991 = (uint16_t)(245); + _curvea0[898] = _7991; + uint16_t _7992 = (uint16_t)(245); + _curvea0[899] = _7992; + uint16_t _7993 = (uint16_t)(245); + _curvea0[900] = _7993; + uint16_t _7994 = (uint16_t)(245); + _curvea0[901] = _7994; + uint16_t _7995 = (uint16_t)(245); + _curvea0[902] = _7995; + uint16_t _7996 = (uint16_t)(246); + _curvea0[903] = _7996; + uint16_t _7997 = (uint16_t)(246); + _curvea0[904] = _7997; + uint16_t _7998 = (uint16_t)(246); + _curvea0[905] = _7998; + uint16_t _7999 = (uint16_t)(246); + _curvea0[906] = _7999; + uint16_t _8000 = (uint16_t)(246); + _curvea0[907] = _8000; + uint16_t _8001 = (uint16_t)(246); + _curvea0[908] = _8001; + uint16_t _8002 = (uint16_t)(246); + _curvea0[909] = _8002; + uint16_t _8003 = (uint16_t)(246); + _curvea0[910] = _8003; + uint16_t _8004 = (uint16_t)(246); + _curvea0[911] = _8004; + uint16_t _8005 = (uint16_t)(246); + _curvea0[912] = _8005; + uint16_t _8006 = (uint16_t)(246); + _curvea0[913] = _8006; + uint16_t _8007 = (uint16_t)(247); + _curvea0[914] = _8007; + uint16_t _8008 = (uint16_t)(247); + _curvea0[915] = _8008; + uint16_t _8009 = (uint16_t)(247); + _curvea0[916] = _8009; + uint16_t _8010 = (uint16_t)(247); + _curvea0[917] = _8010; + uint16_t _8011 = (uint16_t)(247); + _curvea0[918] = _8011; + uint16_t _8012 = (uint16_t)(247); + _curvea0[919] = _8012; + uint16_t _8013 = (uint16_t)(247); + _curvea0[920] = _8013; + uint16_t _8014 = (uint16_t)(247); + _curvea0[921] = _8014; + uint16_t _8015 = (uint16_t)(247); + _curvea0[922] = _8015; + uint16_t _8016 = (uint16_t)(247); + _curvea0[923] = _8016; + uint16_t _8017 = (uint16_t)(247); + _curvea0[924] = _8017; + uint16_t _8018 = (uint16_t)(248); + _curvea0[925] = _8018; + uint16_t _8019 = (uint16_t)(248); + _curvea0[926] = _8019; + uint16_t _8020 = (uint16_t)(248); + _curvea0[927] = _8020; + uint16_t _8021 = (uint16_t)(248); + _curvea0[928] = _8021; + uint16_t _8022 = (uint16_t)(248); + _curvea0[929] = _8022; + uint16_t _8023 = (uint16_t)(248); + _curvea0[930] = _8023; + uint16_t _8024 = (uint16_t)(248); + _curvea0[931] = _8024; + uint16_t _8025 = (uint16_t)(248); + _curvea0[932] = _8025; + uint16_t _8026 = (uint16_t)(248); + _curvea0[933] = _8026; + uint16_t _8027 = (uint16_t)(248); + _curvea0[934] = _8027; + uint16_t _8028 = (uint16_t)(248); + _curvea0[935] = _8028; + uint16_t _8029 = (uint16_t)(249); + _curvea0[936] = _8029; + uint16_t _8030 = (uint16_t)(249); + _curvea0[937] = _8030; + uint16_t _8031 = (uint16_t)(249); + _curvea0[938] = _8031; + uint16_t _8032 = (uint16_t)(249); + _curvea0[939] = _8032; + uint16_t _8033 = (uint16_t)(249); + _curvea0[940] = _8033; + uint16_t _8034 = (uint16_t)(249); + _curvea0[941] = _8034; + uint16_t _8035 = (uint16_t)(249); + _curvea0[942] = _8035; + uint16_t _8036 = (uint16_t)(249); + _curvea0[943] = _8036; + uint16_t _8037 = (uint16_t)(249); + _curvea0[944] = _8037; + uint16_t _8038 = (uint16_t)(249); + _curvea0[945] = _8038; + uint16_t _8039 = (uint16_t)(249); + _curvea0[946] = _8039; + uint16_t _8040 = (uint16_t)(249); + _curvea0[947] = _8040; + uint16_t _8041 = (uint16_t)(250); + _curvea0[948] = _8041; + uint16_t _8042 = (uint16_t)(250); + _curvea0[949] = _8042; + uint16_t _8043 = (uint16_t)(250); + _curvea0[950] = _8043; + uint16_t _8044 = (uint16_t)(250); + _curvea0[951] = _8044; + uint16_t _8045 = (uint16_t)(250); + _curvea0[952] = _8045; + uint16_t _8046 = (uint16_t)(250); + _curvea0[953] = _8046; + uint16_t _8047 = (uint16_t)(250); + _curvea0[954] = _8047; + uint16_t _8048 = (uint16_t)(250); + _curvea0[955] = _8048; + uint16_t _8049 = (uint16_t)(250); + _curvea0[956] = _8049; + uint16_t _8050 = (uint16_t)(250); + _curvea0[957] = _8050; + uint16_t _8051 = (uint16_t)(250); + _curvea0[958] = _8051; + uint16_t _8052 = (uint16_t)(250); + _curvea0[959] = _8052; + uint16_t _8053 = (uint16_t)(251); + _curvea0[960] = _8053; + uint16_t _8054 = (uint16_t)(251); + _curvea0[961] = _8054; + uint16_t _8055 = (uint16_t)(251); + _curvea0[962] = _8055; + uint16_t _8056 = (uint16_t)(251); + _curvea0[963] = _8056; + uint16_t _8057 = (uint16_t)(251); + _curvea0[964] = _8057; + uint16_t _8058 = (uint16_t)(251); + _curvea0[965] = _8058; + uint16_t _8059 = (uint16_t)(251); + _curvea0[966] = _8059; + uint16_t _8060 = (uint16_t)(251); + _curvea0[967] = _8060; + uint16_t _8061 = (uint16_t)(251); + _curvea0[968] = _8061; + uint16_t _8062 = (uint16_t)(251); + _curvea0[969] = _8062; + uint16_t _8063 = (uint16_t)(251); + _curvea0[970] = _8063; + uint16_t _8064 = (uint16_t)(251); + _curvea0[971] = _8064; + uint16_t _8065 = (uint16_t)(252); + _curvea0[972] = _8065; + uint16_t _8066 = (uint16_t)(252); + _curvea0[973] = _8066; + uint16_t _8067 = (uint16_t)(252); + _curvea0[974] = _8067; + uint16_t _8068 = (uint16_t)(252); + _curvea0[975] = _8068; + uint16_t _8069 = (uint16_t)(252); + _curvea0[976] = _8069; + uint16_t _8070 = (uint16_t)(252); + _curvea0[977] = _8070; + uint16_t _8071 = (uint16_t)(252); + _curvea0[978] = _8071; + uint16_t _8072 = (uint16_t)(252); + _curvea0[979] = _8072; + uint16_t _8073 = (uint16_t)(252); + _curvea0[980] = _8073; + uint16_t _8074 = (uint16_t)(252); + _curvea0[981] = _8074; + uint16_t _8075 = (uint16_t)(252); + _curvea0[982] = _8075; + uint16_t _8076 = (uint16_t)(252); + _curvea0[983] = _8076; + uint16_t _8077 = (uint16_t)(252); + _curvea0[984] = _8077; + uint16_t _8078 = (uint16_t)(253); + _curvea0[985] = _8078; + uint16_t _8079 = (uint16_t)(253); + _curvea0[986] = _8079; + uint16_t _8080 = (uint16_t)(253); + _curvea0[987] = _8080; + uint16_t _8081 = (uint16_t)(253); + _curvea0[988] = _8081; + uint16_t _8082 = (uint16_t)(253); + _curvea0[989] = _8082; + uint16_t _8083 = (uint16_t)(253); + _curvea0[990] = _8083; + uint16_t _8084 = (uint16_t)(253); + _curvea0[991] = _8084; + uint16_t _8085 = (uint16_t)(253); + _curvea0[992] = _8085; + uint16_t _8086 = (uint16_t)(253); + _curvea0[993] = _8086; + uint16_t _8087 = (uint16_t)(253); + _curvea0[994] = _8087; + uint16_t _8088 = (uint16_t)(253); + _curvea0[995] = _8088; + uint16_t _8089 = (uint16_t)(253); + _curvea0[996] = _8089; + uint16_t _8090 = (uint16_t)(253); + _curvea0[997] = _8090; + uint16_t _8091 = (uint16_t)(254); + _curvea0[998] = _8091; + uint16_t _8092 = (uint16_t)(254); + _curvea0[999] = _8092; + uint16_t _8093 = (uint16_t)(254); + _curvea0[1000] = _8093; + uint16_t _8094 = (uint16_t)(254); + _curvea0[1001] = _8094; + uint16_t _8095 = (uint16_t)(254); + _curvea0[1002] = _8095; + uint16_t _8096 = (uint16_t)(254); + _curvea0[1003] = _8096; + uint16_t _8097 = (uint16_t)(254); + _curvea0[1004] = _8097; + uint16_t _8098 = (uint16_t)(254); + _curvea0[1005] = _8098; + uint16_t _8099 = (uint16_t)(254); + _curvea0[1006] = _8099; + uint16_t _8100 = (uint16_t)(254); + _curvea0[1007] = _8100; + uint16_t _8101 = (uint16_t)(254); + _curvea0[1008] = _8101; + uint16_t _8102 = (uint16_t)(254); + _curvea0[1009] = _8102; + uint16_t _8103 = (uint16_t)(254); + _curvea0[1010] = _8103; + uint16_t _8104 = (uint16_t)(255); + _curvea0[1011] = _8104; + uint16_t _8105 = (uint16_t)(255); + _curvea0[1012] = _8105; + uint16_t _8106 = (uint16_t)(255); + _curvea0[1013] = _8106; + uint16_t _8107 = (uint16_t)(255); + _curvea0[1014] = _8107; + uint16_t _8108 = (uint16_t)(255); + _curvea0[1015] = _8108; + uint16_t _8109 = (uint16_t)(255); + _curvea0[1016] = _8109; + uint16_t _8110 = (uint16_t)(255); + _curvea0[1017] = _8110; + uint16_t _8111 = (uint16_t)(255); + _curvea0[1018] = _8111; + uint16_t _8112 = (uint16_t)(255); + _curvea0[1019] = _8112; + uint16_t _8113 = (uint16_t)(255); + _curvea0[1020] = _8113; + uint16_t _8114 = (uint16_t)(255); + _curvea0[1021] = _8114; + uint16_t _8115 = (uint16_t)(255); + _curvea0[1022] = _8115; + uint16_t _8116 = (uint16_t)(255); + _curvea0[1023] = _8116; + + int16_t _8117 = (int16_t)(1023); + int16_t _8118 = min(_corrected_stencil_4, _8117); + int16_t _8119 = (int16_t)(0); + int16_t _8120 = max(_8118, _8119); + uint16_t _8121 = (uint16_t)(_8120); + int32_t _8122 = (int32_t)(_8121); + uint16_t _8123 = ((const uint16_t *)_curvea0)[_8122]; + return _8123; +} + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_4(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_5 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _8141 = (uint16_t)(0); + _curvea0[0] = _8141; + uint16_t _8142 = (uint16_t)(4); + _curvea0[1] = _8142; + uint16_t _8143 = (uint16_t)(7); + _curvea0[2] = _8143; + uint16_t _8144 = (uint16_t)(8); + _curvea0[3] = _8144; + uint16_t _8145 = (uint16_t)(10); + _curvea0[4] = _8145; + uint16_t _8146 = (uint16_t)(11); + _curvea0[5] = _8146; + uint16_t _8147 = (uint16_t)(12); + _curvea0[6] = _8147; + uint16_t _8148 = (uint16_t)(13); + _curvea0[7] = _8148; + uint16_t _8149 = (uint16_t)(14); + _curvea0[8] = _8149; + uint16_t _8150 = (uint16_t)(15); + _curvea0[9] = _8150; + uint16_t _8151 = (uint16_t)(16); + _curvea0[10] = _8151; + uint16_t _8152 = (uint16_t)(17); + _curvea0[11] = _8152; + uint16_t _8153 = (uint16_t)(18); + _curvea0[12] = _8153; + uint16_t _8154 = (uint16_t)(19); + _curvea0[13] = _8154; + uint16_t _8155 = (uint16_t)(20); + _curvea0[14] = _8155; + uint16_t _8156 = (uint16_t)(21); + _curvea0[15] = _8156; + uint16_t _8157 = (uint16_t)(22); + _curvea0[16] = _8157; + uint16_t _8158 = (uint16_t)(22); + _curvea0[17] = _8158; + uint16_t _8159 = (uint16_t)(23); + _curvea0[18] = _8159; + uint16_t _8160 = (uint16_t)(24); + _curvea0[19] = _8160; + uint16_t _8161 = (uint16_t)(25); + _curvea0[20] = _8161; + uint16_t _8162 = (uint16_t)(25); + _curvea0[21] = _8162; + uint16_t _8163 = (uint16_t)(26); + _curvea0[22] = _8163; + uint16_t _8164 = (uint16_t)(27); + _curvea0[23] = _8164; + uint16_t _8165 = (uint16_t)(27); + _curvea0[24] = _8165; + uint16_t _8166 = (uint16_t)(28); + _curvea0[25] = _8166; + uint16_t _8167 = (uint16_t)(29); + _curvea0[26] = _8167; + uint16_t _8168 = (uint16_t)(29); + _curvea0[27] = _8168; + uint16_t _8169 = (uint16_t)(30); + _curvea0[28] = _8169; + uint16_t _8170 = (uint16_t)(31); + _curvea0[29] = _8170; + uint16_t _8171 = (uint16_t)(31); + _curvea0[30] = _8171; + uint16_t _8172 = (uint16_t)(32); + _curvea0[31] = _8172; + uint16_t _8173 = (uint16_t)(33); + _curvea0[32] = _8173; + uint16_t _8174 = (uint16_t)(33); + _curvea0[33] = _8174; + uint16_t _8175 = (uint16_t)(34); + _curvea0[34] = _8175; + uint16_t _8176 = (uint16_t)(34); + _curvea0[35] = _8176; + uint16_t _8177 = (uint16_t)(35); + _curvea0[36] = _8177; + uint16_t _8178 = (uint16_t)(36); + _curvea0[37] = _8178; + uint16_t _8179 = (uint16_t)(36); + _curvea0[38] = _8179; + uint16_t _8180 = (uint16_t)(37); + _curvea0[39] = _8180; + uint16_t _8181 = (uint16_t)(37); + _curvea0[40] = _8181; + uint16_t _8182 = (uint16_t)(38); + _curvea0[41] = _8182; + uint16_t _8183 = (uint16_t)(39); + _curvea0[42] = _8183; + uint16_t _8184 = (uint16_t)(39); + _curvea0[43] = _8184; + uint16_t _8185 = (uint16_t)(40); + _curvea0[44] = _8185; + uint16_t _8186 = (uint16_t)(40); + _curvea0[45] = _8186; + uint16_t _8187 = (uint16_t)(41); + _curvea0[46] = _8187; + uint16_t _8188 = (uint16_t)(41); + _curvea0[47] = _8188; + uint16_t _8189 = (uint16_t)(42); + _curvea0[48] = _8189; + uint16_t _8190 = (uint16_t)(42); + _curvea0[49] = _8190; + uint16_t _8191 = (uint16_t)(43); + _curvea0[50] = _8191; + uint16_t _8192 = (uint16_t)(44); + _curvea0[51] = _8192; + uint16_t _8193 = (uint16_t)(44); + _curvea0[52] = _8193; + uint16_t _8194 = (uint16_t)(45); + _curvea0[53] = _8194; + uint16_t _8195 = (uint16_t)(45); + _curvea0[54] = _8195; + uint16_t _8196 = (uint16_t)(46); + _curvea0[55] = _8196; + uint16_t _8197 = (uint16_t)(46); + _curvea0[56] = _8197; + uint16_t _8198 = (uint16_t)(47); + _curvea0[57] = _8198; + uint16_t _8199 = (uint16_t)(47); + _curvea0[58] = _8199; + uint16_t _8200 = (uint16_t)(48); + _curvea0[59] = _8200; + uint16_t _8201 = (uint16_t)(48); + _curvea0[60] = _8201; + uint16_t _8202 = (uint16_t)(49); + _curvea0[61] = _8202; + uint16_t _8203 = (uint16_t)(49); + _curvea0[62] = _8203; + uint16_t _8204 = (uint16_t)(50); + _curvea0[63] = _8204; + uint16_t _8205 = (uint16_t)(50); + _curvea0[64] = _8205; + uint16_t _8206 = (uint16_t)(51); + _curvea0[65] = _8206; + uint16_t _8207 = (uint16_t)(51); + _curvea0[66] = _8207; + uint16_t _8208 = (uint16_t)(52); + _curvea0[67] = _8208; + uint16_t _8209 = (uint16_t)(52); + _curvea0[68] = _8209; + uint16_t _8210 = (uint16_t)(53); + _curvea0[69] = _8210; + uint16_t _8211 = (uint16_t)(53); + _curvea0[70] = _8211; + uint16_t _8212 = (uint16_t)(54); + _curvea0[71] = _8212; + uint16_t _8213 = (uint16_t)(54); + _curvea0[72] = _8213; + uint16_t _8214 = (uint16_t)(55); + _curvea0[73] = _8214; + uint16_t _8215 = (uint16_t)(55); + _curvea0[74] = _8215; + uint16_t _8216 = (uint16_t)(56); + _curvea0[75] = _8216; + uint16_t _8217 = (uint16_t)(56); + _curvea0[76] = _8217; + uint16_t _8218 = (uint16_t)(57); + _curvea0[77] = _8218; + uint16_t _8219 = (uint16_t)(57); + _curvea0[78] = _8219; + uint16_t _8220 = (uint16_t)(58); + _curvea0[79] = _8220; + uint16_t _8221 = (uint16_t)(58); + _curvea0[80] = _8221; + uint16_t _8222 = (uint16_t)(58); + _curvea0[81] = _8222; + uint16_t _8223 = (uint16_t)(59); + _curvea0[82] = _8223; + uint16_t _8224 = (uint16_t)(59); + _curvea0[83] = _8224; + uint16_t _8225 = (uint16_t)(60); + _curvea0[84] = _8225; + uint16_t _8226 = (uint16_t)(60); + _curvea0[85] = _8226; + uint16_t _8227 = (uint16_t)(61); + _curvea0[86] = _8227; + uint16_t _8228 = (uint16_t)(61); + _curvea0[87] = _8228; + uint16_t _8229 = (uint16_t)(62); + _curvea0[88] = _8229; + uint16_t _8230 = (uint16_t)(62); + _curvea0[89] = _8230; + uint16_t _8231 = (uint16_t)(63); + _curvea0[90] = _8231; + uint16_t _8232 = (uint16_t)(63); + _curvea0[91] = _8232; + uint16_t _8233 = (uint16_t)(64); + _curvea0[92] = _8233; + uint16_t _8234 = (uint16_t)(64); + _curvea0[93] = _8234; + uint16_t _8235 = (uint16_t)(64); + _curvea0[94] = _8235; + uint16_t _8236 = (uint16_t)(65); + _curvea0[95] = _8236; + uint16_t _8237 = (uint16_t)(65); + _curvea0[96] = _8237; + uint16_t _8238 = (uint16_t)(66); + _curvea0[97] = _8238; + uint16_t _8239 = (uint16_t)(66); + _curvea0[98] = _8239; + uint16_t _8240 = (uint16_t)(67); + _curvea0[99] = _8240; + uint16_t _8241 = (uint16_t)(67); + _curvea0[100] = _8241; + uint16_t _8242 = (uint16_t)(68); + _curvea0[101] = _8242; + uint16_t _8243 = (uint16_t)(68); + _curvea0[102] = _8243; + uint16_t _8244 = (uint16_t)(68); + _curvea0[103] = _8244; + uint16_t _8245 = (uint16_t)(69); + _curvea0[104] = _8245; + uint16_t _8246 = (uint16_t)(69); + _curvea0[105] = _8246; + uint16_t _8247 = (uint16_t)(70); + _curvea0[106] = _8247; + uint16_t _8248 = (uint16_t)(70); + _curvea0[107] = _8248; + uint16_t _8249 = (uint16_t)(71); + _curvea0[108] = _8249; + uint16_t _8250 = (uint16_t)(71); + _curvea0[109] = _8250; + uint16_t _8251 = (uint16_t)(71); + _curvea0[110] = _8251; + uint16_t _8252 = (uint16_t)(72); + _curvea0[111] = _8252; + uint16_t _8253 = (uint16_t)(72); + _curvea0[112] = _8253; + uint16_t _8254 = (uint16_t)(73); + _curvea0[113] = _8254; + uint16_t _8255 = (uint16_t)(73); + _curvea0[114] = _8255; + uint16_t _8256 = (uint16_t)(74); + _curvea0[115] = _8256; + uint16_t _8257 = (uint16_t)(74); + _curvea0[116] = _8257; + uint16_t _8258 = (uint16_t)(74); + _curvea0[117] = _8258; + uint16_t _8259 = (uint16_t)(75); + _curvea0[118] = _8259; + uint16_t _8260 = (uint16_t)(75); + _curvea0[119] = _8260; + uint16_t _8261 = (uint16_t)(76); + _curvea0[120] = _8261; + uint16_t _8262 = (uint16_t)(76); + _curvea0[121] = _8262; + uint16_t _8263 = (uint16_t)(77); + _curvea0[122] = _8263; + uint16_t _8264 = (uint16_t)(77); + _curvea0[123] = _8264; + uint16_t _8265 = (uint16_t)(77); + _curvea0[124] = _8265; + uint16_t _8266 = (uint16_t)(78); + _curvea0[125] = _8266; + uint16_t _8267 = (uint16_t)(78); + _curvea0[126] = _8267; + uint16_t _8268 = (uint16_t)(79); + _curvea0[127] = _8268; + uint16_t _8269 = (uint16_t)(79); + _curvea0[128] = _8269; + uint16_t _8270 = (uint16_t)(79); + _curvea0[129] = _8270; + uint16_t _8271 = (uint16_t)(80); + _curvea0[130] = _8271; + uint16_t _8272 = (uint16_t)(80); + _curvea0[131] = _8272; + uint16_t _8273 = (uint16_t)(81); + _curvea0[132] = _8273; + uint16_t _8274 = (uint16_t)(81); + _curvea0[133] = _8274; + uint16_t _8275 = (uint16_t)(82); + _curvea0[134] = _8275; + uint16_t _8276 = (uint16_t)(82); + _curvea0[135] = _8276; + uint16_t _8277 = (uint16_t)(82); + _curvea0[136] = _8277; + uint16_t _8278 = (uint16_t)(83); + _curvea0[137] = _8278; + uint16_t _8279 = (uint16_t)(83); + _curvea0[138] = _8279; + uint16_t _8280 = (uint16_t)(84); + _curvea0[139] = _8280; + uint16_t _8281 = (uint16_t)(84); + _curvea0[140] = _8281; + uint16_t _8282 = (uint16_t)(84); + _curvea0[141] = _8282; + uint16_t _8283 = (uint16_t)(85); + _curvea0[142] = _8283; + uint16_t _8284 = (uint16_t)(85); + _curvea0[143] = _8284; + uint16_t _8285 = (uint16_t)(86); + _curvea0[144] = _8285; + uint16_t _8286 = (uint16_t)(86); + _curvea0[145] = _8286; + uint16_t _8287 = (uint16_t)(86); + _curvea0[146] = _8287; + uint16_t _8288 = (uint16_t)(87); + _curvea0[147] = _8288; + uint16_t _8289 = (uint16_t)(87); + _curvea0[148] = _8289; + uint16_t _8290 = (uint16_t)(88); + _curvea0[149] = _8290; + uint16_t _8291 = (uint16_t)(88); + _curvea0[150] = _8291; + uint16_t _8292 = (uint16_t)(88); + _curvea0[151] = _8292; + uint16_t _8293 = (uint16_t)(89); + _curvea0[152] = _8293; + uint16_t _8294 = (uint16_t)(89); + _curvea0[153] = _8294; + uint16_t _8295 = (uint16_t)(90); + _curvea0[154] = _8295; + uint16_t _8296 = (uint16_t)(90); + _curvea0[155] = _8296; + uint16_t _8297 = (uint16_t)(90); + _curvea0[156] = _8297; + uint16_t _8298 = (uint16_t)(91); + _curvea0[157] = _8298; + uint16_t _8299 = (uint16_t)(91); + _curvea0[158] = _8299; + uint16_t _8300 = (uint16_t)(92); + _curvea0[159] = _8300; + uint16_t _8301 = (uint16_t)(92); + _curvea0[160] = _8301; + uint16_t _8302 = (uint16_t)(92); + _curvea0[161] = _8302; + uint16_t _8303 = (uint16_t)(93); + _curvea0[162] = _8303; + uint16_t _8304 = (uint16_t)(93); + _curvea0[163] = _8304; + uint16_t _8305 = (uint16_t)(93); + _curvea0[164] = _8305; + uint16_t _8306 = (uint16_t)(94); + _curvea0[165] = _8306; + uint16_t _8307 = (uint16_t)(94); + _curvea0[166] = _8307; + uint16_t _8308 = (uint16_t)(95); + _curvea0[167] = _8308; + uint16_t _8309 = (uint16_t)(95); + _curvea0[168] = _8309; + uint16_t _8310 = (uint16_t)(95); + _curvea0[169] = _8310; + uint16_t _8311 = (uint16_t)(96); + _curvea0[170] = _8311; + uint16_t _8312 = (uint16_t)(96); + _curvea0[171] = _8312; + uint16_t _8313 = (uint16_t)(97); + _curvea0[172] = _8313; + uint16_t _8314 = (uint16_t)(97); + _curvea0[173] = _8314; + uint16_t _8315 = (uint16_t)(97); + _curvea0[174] = _8315; + uint16_t _8316 = (uint16_t)(98); + _curvea0[175] = _8316; + uint16_t _8317 = (uint16_t)(98); + _curvea0[176] = _8317; + uint16_t _8318 = (uint16_t)(99); + _curvea0[177] = _8318; + uint16_t _8319 = (uint16_t)(99); + _curvea0[178] = _8319; + uint16_t _8320 = (uint16_t)(99); + _curvea0[179] = _8320; + uint16_t _8321 = (uint16_t)(100); + _curvea0[180] = _8321; + uint16_t _8322 = (uint16_t)(100); + _curvea0[181] = _8322; + uint16_t _8323 = (uint16_t)(100); + _curvea0[182] = _8323; + uint16_t _8324 = (uint16_t)(101); + _curvea0[183] = _8324; + uint16_t _8325 = (uint16_t)(101); + _curvea0[184] = _8325; + uint16_t _8326 = (uint16_t)(102); + _curvea0[185] = _8326; + uint16_t _8327 = (uint16_t)(102); + _curvea0[186] = _8327; + uint16_t _8328 = (uint16_t)(102); + _curvea0[187] = _8328; + uint16_t _8329 = (uint16_t)(103); + _curvea0[188] = _8329; + uint16_t _8330 = (uint16_t)(103); + _curvea0[189] = _8330; + uint16_t _8331 = (uint16_t)(103); + _curvea0[190] = _8331; + uint16_t _8332 = (uint16_t)(104); + _curvea0[191] = _8332; + uint16_t _8333 = (uint16_t)(104); + _curvea0[192] = _8333; + uint16_t _8334 = (uint16_t)(105); + _curvea0[193] = _8334; + uint16_t _8335 = (uint16_t)(105); + _curvea0[194] = _8335; + uint16_t _8336 = (uint16_t)(105); + _curvea0[195] = _8336; + uint16_t _8337 = (uint16_t)(106); + _curvea0[196] = _8337; + uint16_t _8338 = (uint16_t)(106); + _curvea0[197] = _8338; + uint16_t _8339 = (uint16_t)(106); + _curvea0[198] = _8339; + uint16_t _8340 = (uint16_t)(107); + _curvea0[199] = _8340; + uint16_t _8341 = (uint16_t)(107); + _curvea0[200] = _8341; + uint16_t _8342 = (uint16_t)(108); + _curvea0[201] = _8342; + uint16_t _8343 = (uint16_t)(108); + _curvea0[202] = _8343; + uint16_t _8344 = (uint16_t)(108); + _curvea0[203] = _8344; + uint16_t _8345 = (uint16_t)(109); + _curvea0[204] = _8345; + uint16_t _8346 = (uint16_t)(109); + _curvea0[205] = _8346; + uint16_t _8347 = (uint16_t)(109); + _curvea0[206] = _8347; + uint16_t _8348 = (uint16_t)(110); + _curvea0[207] = _8348; + uint16_t _8349 = (uint16_t)(110); + _curvea0[208] = _8349; + uint16_t _8350 = (uint16_t)(111); + _curvea0[209] = _8350; + uint16_t _8351 = (uint16_t)(111); + _curvea0[210] = _8351; + uint16_t _8352 = (uint16_t)(111); + _curvea0[211] = _8352; + uint16_t _8353 = (uint16_t)(112); + _curvea0[212] = _8353; + uint16_t _8354 = (uint16_t)(112); + _curvea0[213] = _8354; + uint16_t _8355 = (uint16_t)(112); + _curvea0[214] = _8355; + uint16_t _8356 = (uint16_t)(113); + _curvea0[215] = _8356; + uint16_t _8357 = (uint16_t)(113); + _curvea0[216] = _8357; + uint16_t _8358 = (uint16_t)(113); + _curvea0[217] = _8358; + uint16_t _8359 = (uint16_t)(114); + _curvea0[218] = _8359; + uint16_t _8360 = (uint16_t)(114); + _curvea0[219] = _8360; + uint16_t _8361 = (uint16_t)(115); + _curvea0[220] = _8361; + uint16_t _8362 = (uint16_t)(115); + _curvea0[221] = _8362; + uint16_t _8363 = (uint16_t)(115); + _curvea0[222] = _8363; + uint16_t _8364 = (uint16_t)(116); + _curvea0[223] = _8364; + uint16_t _8365 = (uint16_t)(116); + _curvea0[224] = _8365; + uint16_t _8366 = (uint16_t)(116); + _curvea0[225] = _8366; + uint16_t _8367 = (uint16_t)(117); + _curvea0[226] = _8367; + uint16_t _8368 = (uint16_t)(117); + _curvea0[227] = _8368; + uint16_t _8369 = (uint16_t)(117); + _curvea0[228] = _8369; + uint16_t _8370 = (uint16_t)(118); + _curvea0[229] = _8370; + uint16_t _8371 = (uint16_t)(118); + _curvea0[230] = _8371; + uint16_t _8372 = (uint16_t)(119); + _curvea0[231] = _8372; + uint16_t _8373 = (uint16_t)(119); + _curvea0[232] = _8373; + uint16_t _8374 = (uint16_t)(119); + _curvea0[233] = _8374; + uint16_t _8375 = (uint16_t)(120); + _curvea0[234] = _8375; + uint16_t _8376 = (uint16_t)(120); + _curvea0[235] = _8376; + uint16_t _8377 = (uint16_t)(120); + _curvea0[236] = _8377; + uint16_t _8378 = (uint16_t)(121); + _curvea0[237] = _8378; + uint16_t _8379 = (uint16_t)(121); + _curvea0[238] = _8379; + uint16_t _8380 = (uint16_t)(121); + _curvea0[239] = _8380; + uint16_t _8381 = (uint16_t)(122); + _curvea0[240] = _8381; + uint16_t _8382 = (uint16_t)(122); + _curvea0[241] = _8382; + uint16_t _8383 = (uint16_t)(123); + _curvea0[242] = _8383; + uint16_t _8384 = (uint16_t)(123); + _curvea0[243] = _8384; + uint16_t _8385 = (uint16_t)(123); + _curvea0[244] = _8385; + uint16_t _8386 = (uint16_t)(124); + _curvea0[245] = _8386; + uint16_t _8387 = (uint16_t)(124); + _curvea0[246] = _8387; + uint16_t _8388 = (uint16_t)(124); + _curvea0[247] = _8388; + uint16_t _8389 = (uint16_t)(125); + _curvea0[248] = _8389; + uint16_t _8390 = (uint16_t)(125); + _curvea0[249] = _8390; + uint16_t _8391 = (uint16_t)(125); + _curvea0[250] = _8391; + uint16_t _8392 = (uint16_t)(126); + _curvea0[251] = _8392; + uint16_t _8393 = (uint16_t)(126); + _curvea0[252] = _8393; + uint16_t _8394 = (uint16_t)(126); + _curvea0[253] = _8394; + uint16_t _8395 = (uint16_t)(127); + _curvea0[254] = _8395; + uint16_t _8396 = (uint16_t)(127); + _curvea0[255] = _8396; + uint16_t _8397 = (uint16_t)(128); + _curvea0[256] = _8397; + uint16_t _8398 = (uint16_t)(128); + _curvea0[257] = _8398; + uint16_t _8399 = (uint16_t)(128); + _curvea0[258] = _8399; + uint16_t _8400 = (uint16_t)(129); + _curvea0[259] = _8400; + uint16_t _8401 = (uint16_t)(129); + _curvea0[260] = _8401; + uint16_t _8402 = (uint16_t)(129); + _curvea0[261] = _8402; + uint16_t _8403 = (uint16_t)(130); + _curvea0[262] = _8403; + uint16_t _8404 = (uint16_t)(130); + _curvea0[263] = _8404; + uint16_t _8405 = (uint16_t)(130); + _curvea0[264] = _8405; + uint16_t _8406 = (uint16_t)(131); + _curvea0[265] = _8406; + uint16_t _8407 = (uint16_t)(131); + _curvea0[266] = _8407; + uint16_t _8408 = (uint16_t)(131); + _curvea0[267] = _8408; + uint16_t _8409 = (uint16_t)(132); + _curvea0[268] = _8409; + uint16_t _8410 = (uint16_t)(132); + _curvea0[269] = _8410; + uint16_t _8411 = (uint16_t)(132); + _curvea0[270] = _8411; + uint16_t _8412 = (uint16_t)(133); + _curvea0[271] = _8412; + uint16_t _8413 = (uint16_t)(133); + _curvea0[272] = _8413; + uint16_t _8414 = (uint16_t)(133); + _curvea0[273] = _8414; + uint16_t _8415 = (uint16_t)(134); + _curvea0[274] = _8415; + uint16_t _8416 = (uint16_t)(134); + _curvea0[275] = _8416; + uint16_t _8417 = (uint16_t)(134); + _curvea0[276] = _8417; + uint16_t _8418 = (uint16_t)(135); + _curvea0[277] = _8418; + uint16_t _8419 = (uint16_t)(135); + _curvea0[278] = _8419; + uint16_t _8420 = (uint16_t)(135); + _curvea0[279] = _8420; + uint16_t _8421 = (uint16_t)(136); + _curvea0[280] = _8421; + uint16_t _8422 = (uint16_t)(136); + _curvea0[281] = _8422; + uint16_t _8423 = (uint16_t)(136); + _curvea0[282] = _8423; + uint16_t _8424 = (uint16_t)(137); + _curvea0[283] = _8424; + uint16_t _8425 = (uint16_t)(137); + _curvea0[284] = _8425; + uint16_t _8426 = (uint16_t)(137); + _curvea0[285] = _8426; + uint16_t _8427 = (uint16_t)(138); + _curvea0[286] = _8427; + uint16_t _8428 = (uint16_t)(138); + _curvea0[287] = _8428; + uint16_t _8429 = (uint16_t)(138); + _curvea0[288] = _8429; + uint16_t _8430 = (uint16_t)(139); + _curvea0[289] = _8430; + uint16_t _8431 = (uint16_t)(139); + _curvea0[290] = _8431; + uint16_t _8432 = (uint16_t)(139); + _curvea0[291] = _8432; + uint16_t _8433 = (uint16_t)(140); + _curvea0[292] = _8433; + uint16_t _8434 = (uint16_t)(140); + _curvea0[293] = _8434; + uint16_t _8435 = (uint16_t)(140); + _curvea0[294] = _8435; + uint16_t _8436 = (uint16_t)(141); + _curvea0[295] = _8436; + uint16_t _8437 = (uint16_t)(141); + _curvea0[296] = _8437; + uint16_t _8438 = (uint16_t)(141); + _curvea0[297] = _8438; + uint16_t _8439 = (uint16_t)(141); + _curvea0[298] = _8439; + uint16_t _8440 = (uint16_t)(142); + _curvea0[299] = _8440; + uint16_t _8441 = (uint16_t)(142); + _curvea0[300] = _8441; + uint16_t _8442 = (uint16_t)(142); + _curvea0[301] = _8442; + uint16_t _8443 = (uint16_t)(143); + _curvea0[302] = _8443; + uint16_t _8444 = (uint16_t)(143); + _curvea0[303] = _8444; + uint16_t _8445 = (uint16_t)(143); + _curvea0[304] = _8445; + uint16_t _8446 = (uint16_t)(144); + _curvea0[305] = _8446; + uint16_t _8447 = (uint16_t)(144); + _curvea0[306] = _8447; + uint16_t _8448 = (uint16_t)(144); + _curvea0[307] = _8448; + uint16_t _8449 = (uint16_t)(145); + _curvea0[308] = _8449; + uint16_t _8450 = (uint16_t)(145); + _curvea0[309] = _8450; + uint16_t _8451 = (uint16_t)(145); + _curvea0[310] = _8451; + uint16_t _8452 = (uint16_t)(145); + _curvea0[311] = _8452; + uint16_t _8453 = (uint16_t)(146); + _curvea0[312] = _8453; + uint16_t _8454 = (uint16_t)(146); + _curvea0[313] = _8454; + uint16_t _8455 = (uint16_t)(146); + _curvea0[314] = _8455; + uint16_t _8456 = (uint16_t)(147); + _curvea0[315] = _8456; + uint16_t _8457 = (uint16_t)(147); + _curvea0[316] = _8457; + uint16_t _8458 = (uint16_t)(147); + _curvea0[317] = _8458; + uint16_t _8459 = (uint16_t)(148); + _curvea0[318] = _8459; + uint16_t _8460 = (uint16_t)(148); + _curvea0[319] = _8460; + uint16_t _8461 = (uint16_t)(148); + _curvea0[320] = _8461; + uint16_t _8462 = (uint16_t)(148); + _curvea0[321] = _8462; + uint16_t _8463 = (uint16_t)(149); + _curvea0[322] = _8463; + uint16_t _8464 = (uint16_t)(149); + _curvea0[323] = _8464; + uint16_t _8465 = (uint16_t)(149); + _curvea0[324] = _8465; + uint16_t _8466 = (uint16_t)(150); + _curvea0[325] = _8466; + uint16_t _8467 = (uint16_t)(150); + _curvea0[326] = _8467; + uint16_t _8468 = (uint16_t)(150); + _curvea0[327] = _8468; + uint16_t _8469 = (uint16_t)(150); + _curvea0[328] = _8469; + uint16_t _8470 = (uint16_t)(151); + _curvea0[329] = _8470; + uint16_t _8471 = (uint16_t)(151); + _curvea0[330] = _8471; + uint16_t _8472 = (uint16_t)(151); + _curvea0[331] = _8472; + uint16_t _8473 = (uint16_t)(152); + _curvea0[332] = _8473; + uint16_t _8474 = (uint16_t)(152); + _curvea0[333] = _8474; + uint16_t _8475 = (uint16_t)(152); + _curvea0[334] = _8475; + uint16_t _8476 = (uint16_t)(152); + _curvea0[335] = _8476; + uint16_t _8477 = (uint16_t)(153); + _curvea0[336] = _8477; + uint16_t _8478 = (uint16_t)(153); + _curvea0[337] = _8478; + uint16_t _8479 = (uint16_t)(153); + _curvea0[338] = _8479; + uint16_t _8480 = (uint16_t)(154); + _curvea0[339] = _8480; + uint16_t _8481 = (uint16_t)(154); + _curvea0[340] = _8481; + uint16_t _8482 = (uint16_t)(154); + _curvea0[341] = _8482; + uint16_t _8483 = (uint16_t)(154); + _curvea0[342] = _8483; + uint16_t _8484 = (uint16_t)(155); + _curvea0[343] = _8484; + uint16_t _8485 = (uint16_t)(155); + _curvea0[344] = _8485; + uint16_t _8486 = (uint16_t)(155); + _curvea0[345] = _8486; + uint16_t _8487 = (uint16_t)(156); + _curvea0[346] = _8487; + uint16_t _8488 = (uint16_t)(156); + _curvea0[347] = _8488; + uint16_t _8489 = (uint16_t)(156); + _curvea0[348] = _8489; + uint16_t _8490 = (uint16_t)(156); + _curvea0[349] = _8490; + uint16_t _8491 = (uint16_t)(157); + _curvea0[350] = _8491; + uint16_t _8492 = (uint16_t)(157); + _curvea0[351] = _8492; + uint16_t _8493 = (uint16_t)(157); + _curvea0[352] = _8493; + uint16_t _8494 = (uint16_t)(157); + _curvea0[353] = _8494; + uint16_t _8495 = (uint16_t)(158); + _curvea0[354] = _8495; + uint16_t _8496 = (uint16_t)(158); + _curvea0[355] = _8496; + uint16_t _8497 = (uint16_t)(158); + _curvea0[356] = _8497; + uint16_t _8498 = (uint16_t)(159); + _curvea0[357] = _8498; + uint16_t _8499 = (uint16_t)(159); + _curvea0[358] = _8499; + uint16_t _8500 = (uint16_t)(159); + _curvea0[359] = _8500; + uint16_t _8501 = (uint16_t)(159); + _curvea0[360] = _8501; + uint16_t _8502 = (uint16_t)(160); + _curvea0[361] = _8502; + uint16_t _8503 = (uint16_t)(160); + _curvea0[362] = _8503; + uint16_t _8504 = (uint16_t)(160); + _curvea0[363] = _8504; + uint16_t _8505 = (uint16_t)(160); + _curvea0[364] = _8505; + uint16_t _8506 = (uint16_t)(161); + _curvea0[365] = _8506; + uint16_t _8507 = (uint16_t)(161); + _curvea0[366] = _8507; + uint16_t _8508 = (uint16_t)(161); + _curvea0[367] = _8508; + uint16_t _8509 = (uint16_t)(161); + _curvea0[368] = _8509; + uint16_t _8510 = (uint16_t)(162); + _curvea0[369] = _8510; + uint16_t _8511 = (uint16_t)(162); + _curvea0[370] = _8511; + uint16_t _8512 = (uint16_t)(162); + _curvea0[371] = _8512; + uint16_t _8513 = (uint16_t)(162); + _curvea0[372] = _8513; + uint16_t _8514 = (uint16_t)(163); + _curvea0[373] = _8514; + uint16_t _8515 = (uint16_t)(163); + _curvea0[374] = _8515; + uint16_t _8516 = (uint16_t)(163); + _curvea0[375] = _8516; + uint16_t _8517 = (uint16_t)(163); + _curvea0[376] = _8517; + uint16_t _8518 = (uint16_t)(164); + _curvea0[377] = _8518; + uint16_t _8519 = (uint16_t)(164); + _curvea0[378] = _8519; + uint16_t _8520 = (uint16_t)(164); + _curvea0[379] = _8520; + uint16_t _8521 = (uint16_t)(164); + _curvea0[380] = _8521; + uint16_t _8522 = (uint16_t)(165); + _curvea0[381] = _8522; + uint16_t _8523 = (uint16_t)(165); + _curvea0[382] = _8523; + uint16_t _8524 = (uint16_t)(165); + _curvea0[383] = _8524; + uint16_t _8525 = (uint16_t)(166); + _curvea0[384] = _8525; + uint16_t _8526 = (uint16_t)(166); + _curvea0[385] = _8526; + uint16_t _8527 = (uint16_t)(166); + _curvea0[386] = _8527; + uint16_t _8528 = (uint16_t)(166); + _curvea0[387] = _8528; + uint16_t _8529 = (uint16_t)(167); + _curvea0[388] = _8529; + uint16_t _8530 = (uint16_t)(167); + _curvea0[389] = _8530; + uint16_t _8531 = (uint16_t)(167); + _curvea0[390] = _8531; + uint16_t _8532 = (uint16_t)(167); + _curvea0[391] = _8532; + uint16_t _8533 = (uint16_t)(167); + _curvea0[392] = _8533; + uint16_t _8534 = (uint16_t)(168); + _curvea0[393] = _8534; + uint16_t _8535 = (uint16_t)(168); + _curvea0[394] = _8535; + uint16_t _8536 = (uint16_t)(168); + _curvea0[395] = _8536; + uint16_t _8537 = (uint16_t)(168); + _curvea0[396] = _8537; + uint16_t _8538 = (uint16_t)(169); + _curvea0[397] = _8538; + uint16_t _8539 = (uint16_t)(169); + _curvea0[398] = _8539; + uint16_t _8540 = (uint16_t)(169); + _curvea0[399] = _8540; + uint16_t _8541 = (uint16_t)(169); + _curvea0[400] = _8541; + uint16_t _8542 = (uint16_t)(170); + _curvea0[401] = _8542; + uint16_t _8543 = (uint16_t)(170); + _curvea0[402] = _8543; + uint16_t _8544 = (uint16_t)(170); + _curvea0[403] = _8544; + uint16_t _8545 = (uint16_t)(170); + _curvea0[404] = _8545; + uint16_t _8546 = (uint16_t)(171); + _curvea0[405] = _8546; + uint16_t _8547 = (uint16_t)(171); + _curvea0[406] = _8547; + uint16_t _8548 = (uint16_t)(171); + _curvea0[407] = _8548; + uint16_t _8549 = (uint16_t)(171); + _curvea0[408] = _8549; + uint16_t _8550 = (uint16_t)(172); + _curvea0[409] = _8550; + uint16_t _8551 = (uint16_t)(172); + _curvea0[410] = _8551; + uint16_t _8552 = (uint16_t)(172); + _curvea0[411] = _8552; + uint16_t _8553 = (uint16_t)(172); + _curvea0[412] = _8553; + uint16_t _8554 = (uint16_t)(173); + _curvea0[413] = _8554; + uint16_t _8555 = (uint16_t)(173); + _curvea0[414] = _8555; + uint16_t _8556 = (uint16_t)(173); + _curvea0[415] = _8556; + uint16_t _8557 = (uint16_t)(173); + _curvea0[416] = _8557; + uint16_t _8558 = (uint16_t)(173); + _curvea0[417] = _8558; + uint16_t _8559 = (uint16_t)(174); + _curvea0[418] = _8559; + uint16_t _8560 = (uint16_t)(174); + _curvea0[419] = _8560; + uint16_t _8561 = (uint16_t)(174); + _curvea0[420] = _8561; + uint16_t _8562 = (uint16_t)(174); + _curvea0[421] = _8562; + uint16_t _8563 = (uint16_t)(175); + _curvea0[422] = _8563; + uint16_t _8564 = (uint16_t)(175); + _curvea0[423] = _8564; + uint16_t _8565 = (uint16_t)(175); + _curvea0[424] = _8565; + uint16_t _8566 = (uint16_t)(175); + _curvea0[425] = _8566; + uint16_t _8567 = (uint16_t)(176); + _curvea0[426] = _8567; + uint16_t _8568 = (uint16_t)(176); + _curvea0[427] = _8568; + uint16_t _8569 = (uint16_t)(176); + _curvea0[428] = _8569; + uint16_t _8570 = (uint16_t)(176); + _curvea0[429] = _8570; + uint16_t _8571 = (uint16_t)(176); + _curvea0[430] = _8571; + uint16_t _8572 = (uint16_t)(177); + _curvea0[431] = _8572; + uint16_t _8573 = (uint16_t)(177); + _curvea0[432] = _8573; + uint16_t _8574 = (uint16_t)(177); + _curvea0[433] = _8574; + uint16_t _8575 = (uint16_t)(177); + _curvea0[434] = _8575; + uint16_t _8576 = (uint16_t)(178); + _curvea0[435] = _8576; + uint16_t _8577 = (uint16_t)(178); + _curvea0[436] = _8577; + uint16_t _8578 = (uint16_t)(178); + _curvea0[437] = _8578; + uint16_t _8579 = (uint16_t)(178); + _curvea0[438] = _8579; + uint16_t _8580 = (uint16_t)(178); + _curvea0[439] = _8580; + uint16_t _8581 = (uint16_t)(179); + _curvea0[440] = _8581; + uint16_t _8582 = (uint16_t)(179); + _curvea0[441] = _8582; + uint16_t _8583 = (uint16_t)(179); + _curvea0[442] = _8583; + uint16_t _8584 = (uint16_t)(179); + _curvea0[443] = _8584; + uint16_t _8585 = (uint16_t)(180); + _curvea0[444] = _8585; + uint16_t _8586 = (uint16_t)(180); + _curvea0[445] = _8586; + uint16_t _8587 = (uint16_t)(180); + _curvea0[446] = _8587; + uint16_t _8588 = (uint16_t)(180); + _curvea0[447] = _8588; + uint16_t _8589 = (uint16_t)(180); + _curvea0[448] = _8589; + uint16_t _8590 = (uint16_t)(181); + _curvea0[449] = _8590; + uint16_t _8591 = (uint16_t)(181); + _curvea0[450] = _8591; + uint16_t _8592 = (uint16_t)(181); + _curvea0[451] = _8592; + uint16_t _8593 = (uint16_t)(181); + _curvea0[452] = _8593; + uint16_t _8594 = (uint16_t)(181); + _curvea0[453] = _8594; + uint16_t _8595 = (uint16_t)(182); + _curvea0[454] = _8595; + uint16_t _8596 = (uint16_t)(182); + _curvea0[455] = _8596; + uint16_t _8597 = (uint16_t)(182); + _curvea0[456] = _8597; + uint16_t _8598 = (uint16_t)(182); + _curvea0[457] = _8598; + uint16_t _8599 = (uint16_t)(183); + _curvea0[458] = _8599; + uint16_t _8600 = (uint16_t)(183); + _curvea0[459] = _8600; + uint16_t _8601 = (uint16_t)(183); + _curvea0[460] = _8601; + uint16_t _8602 = (uint16_t)(183); + _curvea0[461] = _8602; + uint16_t _8603 = (uint16_t)(183); + _curvea0[462] = _8603; + uint16_t _8604 = (uint16_t)(184); + _curvea0[463] = _8604; + uint16_t _8605 = (uint16_t)(184); + _curvea0[464] = _8605; + uint16_t _8606 = (uint16_t)(184); + _curvea0[465] = _8606; + uint16_t _8607 = (uint16_t)(184); + _curvea0[466] = _8607; + uint16_t _8608 = (uint16_t)(184); + _curvea0[467] = _8608; + uint16_t _8609 = (uint16_t)(185); + _curvea0[468] = _8609; + uint16_t _8610 = (uint16_t)(185); + _curvea0[469] = _8610; + uint16_t _8611 = (uint16_t)(185); + _curvea0[470] = _8611; + uint16_t _8612 = (uint16_t)(185); + _curvea0[471] = _8612; + uint16_t _8613 = (uint16_t)(185); + _curvea0[472] = _8613; + uint16_t _8614 = (uint16_t)(186); + _curvea0[473] = _8614; + uint16_t _8615 = (uint16_t)(186); + _curvea0[474] = _8615; + uint16_t _8616 = (uint16_t)(186); + _curvea0[475] = _8616; + uint16_t _8617 = (uint16_t)(186); + _curvea0[476] = _8617; + uint16_t _8618 = (uint16_t)(187); + _curvea0[477] = _8618; + uint16_t _8619 = (uint16_t)(187); + _curvea0[478] = _8619; + uint16_t _8620 = (uint16_t)(187); + _curvea0[479] = _8620; + uint16_t _8621 = (uint16_t)(187); + _curvea0[480] = _8621; + uint16_t _8622 = (uint16_t)(187); + _curvea0[481] = _8622; + uint16_t _8623 = (uint16_t)(188); + _curvea0[482] = _8623; + uint16_t _8624 = (uint16_t)(188); + _curvea0[483] = _8624; + uint16_t _8625 = (uint16_t)(188); + _curvea0[484] = _8625; + uint16_t _8626 = (uint16_t)(188); + _curvea0[485] = _8626; + uint16_t _8627 = (uint16_t)(188); + _curvea0[486] = _8627; + uint16_t _8628 = (uint16_t)(189); + _curvea0[487] = _8628; + uint16_t _8629 = (uint16_t)(189); + _curvea0[488] = _8629; + uint16_t _8630 = (uint16_t)(189); + _curvea0[489] = _8630; + uint16_t _8631 = (uint16_t)(189); + _curvea0[490] = _8631; + uint16_t _8632 = (uint16_t)(189); + _curvea0[491] = _8632; + uint16_t _8633 = (uint16_t)(190); + _curvea0[492] = _8633; + uint16_t _8634 = (uint16_t)(190); + _curvea0[493] = _8634; + uint16_t _8635 = (uint16_t)(190); + _curvea0[494] = _8635; + uint16_t _8636 = (uint16_t)(190); + _curvea0[495] = _8636; + uint16_t _8637 = (uint16_t)(190); + _curvea0[496] = _8637; + uint16_t _8638 = (uint16_t)(190); + _curvea0[497] = _8638; + uint16_t _8639 = (uint16_t)(191); + _curvea0[498] = _8639; + uint16_t _8640 = (uint16_t)(191); + _curvea0[499] = _8640; + uint16_t _8641 = (uint16_t)(191); + _curvea0[500] = _8641; + uint16_t _8642 = (uint16_t)(191); + _curvea0[501] = _8642; + uint16_t _8643 = (uint16_t)(191); + _curvea0[502] = _8643; + uint16_t _8644 = (uint16_t)(192); + _curvea0[503] = _8644; + uint16_t _8645 = (uint16_t)(192); + _curvea0[504] = _8645; + uint16_t _8646 = (uint16_t)(192); + _curvea0[505] = _8646; + uint16_t _8647 = (uint16_t)(192); + _curvea0[506] = _8647; + uint16_t _8648 = (uint16_t)(192); + _curvea0[507] = _8648; + uint16_t _8649 = (uint16_t)(193); + _curvea0[508] = _8649; + uint16_t _8650 = (uint16_t)(193); + _curvea0[509] = _8650; + uint16_t _8651 = (uint16_t)(193); + _curvea0[510] = _8651; + uint16_t _8652 = (uint16_t)(193); + _curvea0[511] = _8652; + uint16_t _8653 = (uint16_t)(193); + _curvea0[512] = _8653; + uint16_t _8654 = (uint16_t)(194); + _curvea0[513] = _8654; + uint16_t _8655 = (uint16_t)(194); + _curvea0[514] = _8655; + uint16_t _8656 = (uint16_t)(194); + _curvea0[515] = _8656; + uint16_t _8657 = (uint16_t)(194); + _curvea0[516] = _8657; + uint16_t _8658 = (uint16_t)(194); + _curvea0[517] = _8658; + uint16_t _8659 = (uint16_t)(195); + _curvea0[518] = _8659; + uint16_t _8660 = (uint16_t)(195); + _curvea0[519] = _8660; + uint16_t _8661 = (uint16_t)(195); + _curvea0[520] = _8661; + uint16_t _8662 = (uint16_t)(195); + _curvea0[521] = _8662; + uint16_t _8663 = (uint16_t)(195); + _curvea0[522] = _8663; + uint16_t _8664 = (uint16_t)(195); + _curvea0[523] = _8664; + uint16_t _8665 = (uint16_t)(196); + _curvea0[524] = _8665; + uint16_t _8666 = (uint16_t)(196); + _curvea0[525] = _8666; + uint16_t _8667 = (uint16_t)(196); + _curvea0[526] = _8667; + uint16_t _8668 = (uint16_t)(196); + _curvea0[527] = _8668; + uint16_t _8669 = (uint16_t)(196); + _curvea0[528] = _8669; + uint16_t _8670 = (uint16_t)(197); + _curvea0[529] = _8670; + uint16_t _8671 = (uint16_t)(197); + _curvea0[530] = _8671; + uint16_t _8672 = (uint16_t)(197); + _curvea0[531] = _8672; + uint16_t _8673 = (uint16_t)(197); + _curvea0[532] = _8673; + uint16_t _8674 = (uint16_t)(197); + _curvea0[533] = _8674; + uint16_t _8675 = (uint16_t)(197); + _curvea0[534] = _8675; + uint16_t _8676 = (uint16_t)(198); + _curvea0[535] = _8676; + uint16_t _8677 = (uint16_t)(198); + _curvea0[536] = _8677; + uint16_t _8678 = (uint16_t)(198); + _curvea0[537] = _8678; + uint16_t _8679 = (uint16_t)(198); + _curvea0[538] = _8679; + uint16_t _8680 = (uint16_t)(198); + _curvea0[539] = _8680; + uint16_t _8681 = (uint16_t)(199); + _curvea0[540] = _8681; + uint16_t _8682 = (uint16_t)(199); + _curvea0[541] = _8682; + uint16_t _8683 = (uint16_t)(199); + _curvea0[542] = _8683; + uint16_t _8684 = (uint16_t)(199); + _curvea0[543] = _8684; + uint16_t _8685 = (uint16_t)(199); + _curvea0[544] = _8685; + uint16_t _8686 = (uint16_t)(199); + _curvea0[545] = _8686; + uint16_t _8687 = (uint16_t)(200); + _curvea0[546] = _8687; + uint16_t _8688 = (uint16_t)(200); + _curvea0[547] = _8688; + uint16_t _8689 = (uint16_t)(200); + _curvea0[548] = _8689; + uint16_t _8690 = (uint16_t)(200); + _curvea0[549] = _8690; + uint16_t _8691 = (uint16_t)(200); + _curvea0[550] = _8691; + uint16_t _8692 = (uint16_t)(200); + _curvea0[551] = _8692; + uint16_t _8693 = (uint16_t)(201); + _curvea0[552] = _8693; + uint16_t _8694 = (uint16_t)(201); + _curvea0[553] = _8694; + uint16_t _8695 = (uint16_t)(201); + _curvea0[554] = _8695; + uint16_t _8696 = (uint16_t)(201); + _curvea0[555] = _8696; + uint16_t _8697 = (uint16_t)(201); + _curvea0[556] = _8697; + uint16_t _8698 = (uint16_t)(202); + _curvea0[557] = _8698; + uint16_t _8699 = (uint16_t)(202); + _curvea0[558] = _8699; + uint16_t _8700 = (uint16_t)(202); + _curvea0[559] = _8700; + uint16_t _8701 = (uint16_t)(202); + _curvea0[560] = _8701; + uint16_t _8702 = (uint16_t)(202); + _curvea0[561] = _8702; + uint16_t _8703 = (uint16_t)(202); + _curvea0[562] = _8703; + uint16_t _8704 = (uint16_t)(203); + _curvea0[563] = _8704; + uint16_t _8705 = (uint16_t)(203); + _curvea0[564] = _8705; + uint16_t _8706 = (uint16_t)(203); + _curvea0[565] = _8706; + uint16_t _8707 = (uint16_t)(203); + _curvea0[566] = _8707; + uint16_t _8708 = (uint16_t)(203); + _curvea0[567] = _8708; + uint16_t _8709 = (uint16_t)(203); + _curvea0[568] = _8709; + uint16_t _8710 = (uint16_t)(204); + _curvea0[569] = _8710; + uint16_t _8711 = (uint16_t)(204); + _curvea0[570] = _8711; + uint16_t _8712 = (uint16_t)(204); + _curvea0[571] = _8712; + uint16_t _8713 = (uint16_t)(204); + _curvea0[572] = _8713; + uint16_t _8714 = (uint16_t)(204); + _curvea0[573] = _8714; + uint16_t _8715 = (uint16_t)(204); + _curvea0[574] = _8715; + uint16_t _8716 = (uint16_t)(205); + _curvea0[575] = _8716; + uint16_t _8717 = (uint16_t)(205); + _curvea0[576] = _8717; + uint16_t _8718 = (uint16_t)(205); + _curvea0[577] = _8718; + uint16_t _8719 = (uint16_t)(205); + _curvea0[578] = _8719; + uint16_t _8720 = (uint16_t)(205); + _curvea0[579] = _8720; + uint16_t _8721 = (uint16_t)(205); + _curvea0[580] = _8721; + uint16_t _8722 = (uint16_t)(206); + _curvea0[581] = _8722; + uint16_t _8723 = (uint16_t)(206); + _curvea0[582] = _8723; + uint16_t _8724 = (uint16_t)(206); + _curvea0[583] = _8724; + uint16_t _8725 = (uint16_t)(206); + _curvea0[584] = _8725; + uint16_t _8726 = (uint16_t)(206); + _curvea0[585] = _8726; + uint16_t _8727 = (uint16_t)(206); + _curvea0[586] = _8727; + uint16_t _8728 = (uint16_t)(207); + _curvea0[587] = _8728; + uint16_t _8729 = (uint16_t)(207); + _curvea0[588] = _8729; + uint16_t _8730 = (uint16_t)(207); + _curvea0[589] = _8730; + uint16_t _8731 = (uint16_t)(207); + _curvea0[590] = _8731; + uint16_t _8732 = (uint16_t)(207); + _curvea0[591] = _8732; + uint16_t _8733 = (uint16_t)(207); + _curvea0[592] = _8733; + uint16_t _8734 = (uint16_t)(208); + _curvea0[593] = _8734; + uint16_t _8735 = (uint16_t)(208); + _curvea0[594] = _8735; + uint16_t _8736 = (uint16_t)(208); + _curvea0[595] = _8736; + uint16_t _8737 = (uint16_t)(208); + _curvea0[596] = _8737; + uint16_t _8738 = (uint16_t)(208); + _curvea0[597] = _8738; + uint16_t _8739 = (uint16_t)(208); + _curvea0[598] = _8739; + uint16_t _8740 = (uint16_t)(209); + _curvea0[599] = _8740; + uint16_t _8741 = (uint16_t)(209); + _curvea0[600] = _8741; + uint16_t _8742 = (uint16_t)(209); + _curvea0[601] = _8742; + uint16_t _8743 = (uint16_t)(209); + _curvea0[602] = _8743; + uint16_t _8744 = (uint16_t)(209); + _curvea0[603] = _8744; + uint16_t _8745 = (uint16_t)(209); + _curvea0[604] = _8745; + uint16_t _8746 = (uint16_t)(209); + _curvea0[605] = _8746; + uint16_t _8747 = (uint16_t)(210); + _curvea0[606] = _8747; + uint16_t _8748 = (uint16_t)(210); + _curvea0[607] = _8748; + uint16_t _8749 = (uint16_t)(210); + _curvea0[608] = _8749; + uint16_t _8750 = (uint16_t)(210); + _curvea0[609] = _8750; + uint16_t _8751 = (uint16_t)(210); + _curvea0[610] = _8751; + uint16_t _8752 = (uint16_t)(210); + _curvea0[611] = _8752; + uint16_t _8753 = (uint16_t)(211); + _curvea0[612] = _8753; + uint16_t _8754 = (uint16_t)(211); + _curvea0[613] = _8754; + uint16_t _8755 = (uint16_t)(211); + _curvea0[614] = _8755; + uint16_t _8756 = (uint16_t)(211); + _curvea0[615] = _8756; + uint16_t _8757 = (uint16_t)(211); + _curvea0[616] = _8757; + uint16_t _8758 = (uint16_t)(211); + _curvea0[617] = _8758; + uint16_t _8759 = (uint16_t)(211); + _curvea0[618] = _8759; + uint16_t _8760 = (uint16_t)(212); + _curvea0[619] = _8760; + uint16_t _8761 = (uint16_t)(212); + _curvea0[620] = _8761; + uint16_t _8762 = (uint16_t)(212); + _curvea0[621] = _8762; + uint16_t _8763 = (uint16_t)(212); + _curvea0[622] = _8763; + uint16_t _8764 = (uint16_t)(212); + _curvea0[623] = _8764; + uint16_t _8765 = (uint16_t)(212); + _curvea0[624] = _8765; + uint16_t _8766 = (uint16_t)(213); + _curvea0[625] = _8766; + uint16_t _8767 = (uint16_t)(213); + _curvea0[626] = _8767; + uint16_t _8768 = (uint16_t)(213); + _curvea0[627] = _8768; + uint16_t _8769 = (uint16_t)(213); + _curvea0[628] = _8769; + uint16_t _8770 = (uint16_t)(213); + _curvea0[629] = _8770; + uint16_t _8771 = (uint16_t)(213); + _curvea0[630] = _8771; + uint16_t _8772 = (uint16_t)(213); + _curvea0[631] = _8772; + uint16_t _8773 = (uint16_t)(214); + _curvea0[632] = _8773; + uint16_t _8774 = (uint16_t)(214); + _curvea0[633] = _8774; + uint16_t _8775 = (uint16_t)(214); + _curvea0[634] = _8775; + uint16_t _8776 = (uint16_t)(214); + _curvea0[635] = _8776; + uint16_t _8777 = (uint16_t)(214); + _curvea0[636] = _8777; + uint16_t _8778 = (uint16_t)(214); + _curvea0[637] = _8778; + uint16_t _8779 = (uint16_t)(214); + _curvea0[638] = _8779; + uint16_t _8780 = (uint16_t)(215); + _curvea0[639] = _8780; + uint16_t _8781 = (uint16_t)(215); + _curvea0[640] = _8781; + uint16_t _8782 = (uint16_t)(215); + _curvea0[641] = _8782; + uint16_t _8783 = (uint16_t)(215); + _curvea0[642] = _8783; + uint16_t _8784 = (uint16_t)(215); + _curvea0[643] = _8784; + uint16_t _8785 = (uint16_t)(215); + _curvea0[644] = _8785; + uint16_t _8786 = (uint16_t)(216); + _curvea0[645] = _8786; + uint16_t _8787 = (uint16_t)(216); + _curvea0[646] = _8787; + uint16_t _8788 = (uint16_t)(216); + _curvea0[647] = _8788; + uint16_t _8789 = (uint16_t)(216); + _curvea0[648] = _8789; + uint16_t _8790 = (uint16_t)(216); + _curvea0[649] = _8790; + uint16_t _8791 = (uint16_t)(216); + _curvea0[650] = _8791; + uint16_t _8792 = (uint16_t)(216); + _curvea0[651] = _8792; + uint16_t _8793 = (uint16_t)(217); + _curvea0[652] = _8793; + uint16_t _8794 = (uint16_t)(217); + _curvea0[653] = _8794; + uint16_t _8795 = (uint16_t)(217); + _curvea0[654] = _8795; + uint16_t _8796 = (uint16_t)(217); + _curvea0[655] = _8796; + uint16_t _8797 = (uint16_t)(217); + _curvea0[656] = _8797; + uint16_t _8798 = (uint16_t)(217); + _curvea0[657] = _8798; + uint16_t _8799 = (uint16_t)(217); + _curvea0[658] = _8799; + uint16_t _8800 = (uint16_t)(218); + _curvea0[659] = _8800; + uint16_t _8801 = (uint16_t)(218); + _curvea0[660] = _8801; + uint16_t _8802 = (uint16_t)(218); + _curvea0[661] = _8802; + uint16_t _8803 = (uint16_t)(218); + _curvea0[662] = _8803; + uint16_t _8804 = (uint16_t)(218); + _curvea0[663] = _8804; + uint16_t _8805 = (uint16_t)(218); + _curvea0[664] = _8805; + uint16_t _8806 = (uint16_t)(218); + _curvea0[665] = _8806; + uint16_t _8807 = (uint16_t)(219); + _curvea0[666] = _8807; + uint16_t _8808 = (uint16_t)(219); + _curvea0[667] = _8808; + uint16_t _8809 = (uint16_t)(219); + _curvea0[668] = _8809; + uint16_t _8810 = (uint16_t)(219); + _curvea0[669] = _8810; + uint16_t _8811 = (uint16_t)(219); + _curvea0[670] = _8811; + uint16_t _8812 = (uint16_t)(219); + _curvea0[671] = _8812; + uint16_t _8813 = (uint16_t)(219); + _curvea0[672] = _8813; + uint16_t _8814 = (uint16_t)(220); + _curvea0[673] = _8814; + uint16_t _8815 = (uint16_t)(220); + _curvea0[674] = _8815; + uint16_t _8816 = (uint16_t)(220); + _curvea0[675] = _8816; + uint16_t _8817 = (uint16_t)(220); + _curvea0[676] = _8817; + uint16_t _8818 = (uint16_t)(220); + _curvea0[677] = _8818; + uint16_t _8819 = (uint16_t)(220); + _curvea0[678] = _8819; + uint16_t _8820 = (uint16_t)(220); + _curvea0[679] = _8820; + uint16_t _8821 = (uint16_t)(220); + _curvea0[680] = _8821; + uint16_t _8822 = (uint16_t)(221); + _curvea0[681] = _8822; + uint16_t _8823 = (uint16_t)(221); + _curvea0[682] = _8823; + uint16_t _8824 = (uint16_t)(221); + _curvea0[683] = _8824; + uint16_t _8825 = (uint16_t)(221); + _curvea0[684] = _8825; + uint16_t _8826 = (uint16_t)(221); + _curvea0[685] = _8826; + uint16_t _8827 = (uint16_t)(221); + _curvea0[686] = _8827; + uint16_t _8828 = (uint16_t)(221); + _curvea0[687] = _8828; + uint16_t _8829 = (uint16_t)(222); + _curvea0[688] = _8829; + uint16_t _8830 = (uint16_t)(222); + _curvea0[689] = _8830; + uint16_t _8831 = (uint16_t)(222); + _curvea0[690] = _8831; + uint16_t _8832 = (uint16_t)(222); + _curvea0[691] = _8832; + uint16_t _8833 = (uint16_t)(222); + _curvea0[692] = _8833; + uint16_t _8834 = (uint16_t)(222); + _curvea0[693] = _8834; + uint16_t _8835 = (uint16_t)(222); + _curvea0[694] = _8835; + uint16_t _8836 = (uint16_t)(223); + _curvea0[695] = _8836; + uint16_t _8837 = (uint16_t)(223); + _curvea0[696] = _8837; + uint16_t _8838 = (uint16_t)(223); + _curvea0[697] = _8838; + uint16_t _8839 = (uint16_t)(223); + _curvea0[698] = _8839; + uint16_t _8840 = (uint16_t)(223); + _curvea0[699] = _8840; + uint16_t _8841 = (uint16_t)(223); + _curvea0[700] = _8841; + uint16_t _8842 = (uint16_t)(223); + _curvea0[701] = _8842; + uint16_t _8843 = (uint16_t)(223); + _curvea0[702] = _8843; + uint16_t _8844 = (uint16_t)(224); + _curvea0[703] = _8844; + uint16_t _8845 = (uint16_t)(224); + _curvea0[704] = _8845; + uint16_t _8846 = (uint16_t)(224); + _curvea0[705] = _8846; + uint16_t _8847 = (uint16_t)(224); + _curvea0[706] = _8847; + uint16_t _8848 = (uint16_t)(224); + _curvea0[707] = _8848; + uint16_t _8849 = (uint16_t)(224); + _curvea0[708] = _8849; + uint16_t _8850 = (uint16_t)(224); + _curvea0[709] = _8850; + uint16_t _8851 = (uint16_t)(224); + _curvea0[710] = _8851; + uint16_t _8852 = (uint16_t)(225); + _curvea0[711] = _8852; + uint16_t _8853 = (uint16_t)(225); + _curvea0[712] = _8853; + uint16_t _8854 = (uint16_t)(225); + _curvea0[713] = _8854; + uint16_t _8855 = (uint16_t)(225); + _curvea0[714] = _8855; + uint16_t _8856 = (uint16_t)(225); + _curvea0[715] = _8856; + uint16_t _8857 = (uint16_t)(225); + _curvea0[716] = _8857; + uint16_t _8858 = (uint16_t)(225); + _curvea0[717] = _8858; + uint16_t _8859 = (uint16_t)(226); + _curvea0[718] = _8859; + uint16_t _8860 = (uint16_t)(226); + _curvea0[719] = _8860; + uint16_t _8861 = (uint16_t)(226); + _curvea0[720] = _8861; + uint16_t _8862 = (uint16_t)(226); + _curvea0[721] = _8862; + uint16_t _8863 = (uint16_t)(226); + _curvea0[722] = _8863; + uint16_t _8864 = (uint16_t)(226); + _curvea0[723] = _8864; + uint16_t _8865 = (uint16_t)(226); + _curvea0[724] = _8865; + uint16_t _8866 = (uint16_t)(226); + _curvea0[725] = _8866; + uint16_t _8867 = (uint16_t)(227); + _curvea0[726] = _8867; + uint16_t _8868 = (uint16_t)(227); + _curvea0[727] = _8868; + uint16_t _8869 = (uint16_t)(227); + _curvea0[728] = _8869; + uint16_t _8870 = (uint16_t)(227); + _curvea0[729] = _8870; + uint16_t _8871 = (uint16_t)(227); + _curvea0[730] = _8871; + uint16_t _8872 = (uint16_t)(227); + _curvea0[731] = _8872; + uint16_t _8873 = (uint16_t)(227); + _curvea0[732] = _8873; + uint16_t _8874 = (uint16_t)(227); + _curvea0[733] = _8874; + uint16_t _8875 = (uint16_t)(228); + _curvea0[734] = _8875; + uint16_t _8876 = (uint16_t)(228); + _curvea0[735] = _8876; + uint16_t _8877 = (uint16_t)(228); + _curvea0[736] = _8877; + uint16_t _8878 = (uint16_t)(228); + _curvea0[737] = _8878; + uint16_t _8879 = (uint16_t)(228); + _curvea0[738] = _8879; + uint16_t _8880 = (uint16_t)(228); + _curvea0[739] = _8880; + uint16_t _8881 = (uint16_t)(228); + _curvea0[740] = _8881; + uint16_t _8882 = (uint16_t)(228); + _curvea0[741] = _8882; + uint16_t _8883 = (uint16_t)(228); + _curvea0[742] = _8883; + uint16_t _8884 = (uint16_t)(229); + _curvea0[743] = _8884; + uint16_t _8885 = (uint16_t)(229); + _curvea0[744] = _8885; + uint16_t _8886 = (uint16_t)(229); + _curvea0[745] = _8886; + uint16_t _8887 = (uint16_t)(229); + _curvea0[746] = _8887; + uint16_t _8888 = (uint16_t)(229); + _curvea0[747] = _8888; + uint16_t _8889 = (uint16_t)(229); + _curvea0[748] = _8889; + uint16_t _8890 = (uint16_t)(229); + _curvea0[749] = _8890; + uint16_t _8891 = (uint16_t)(229); + _curvea0[750] = _8891; + uint16_t _8892 = (uint16_t)(230); + _curvea0[751] = _8892; + uint16_t _8893 = (uint16_t)(230); + _curvea0[752] = _8893; + uint16_t _8894 = (uint16_t)(230); + _curvea0[753] = _8894; + uint16_t _8895 = (uint16_t)(230); + _curvea0[754] = _8895; + uint16_t _8896 = (uint16_t)(230); + _curvea0[755] = _8896; + uint16_t _8897 = (uint16_t)(230); + _curvea0[756] = _8897; + uint16_t _8898 = (uint16_t)(230); + _curvea0[757] = _8898; + uint16_t _8899 = (uint16_t)(230); + _curvea0[758] = _8899; + uint16_t _8900 = (uint16_t)(231); + _curvea0[759] = _8900; + uint16_t _8901 = (uint16_t)(231); + _curvea0[760] = _8901; + uint16_t _8902 = (uint16_t)(231); + _curvea0[761] = _8902; + uint16_t _8903 = (uint16_t)(231); + _curvea0[762] = _8903; + uint16_t _8904 = (uint16_t)(231); + _curvea0[763] = _8904; + uint16_t _8905 = (uint16_t)(231); + _curvea0[764] = _8905; + uint16_t _8906 = (uint16_t)(231); + _curvea0[765] = _8906; + uint16_t _8907 = (uint16_t)(231); + _curvea0[766] = _8907; + uint16_t _8908 = (uint16_t)(231); + _curvea0[767] = _8908; + uint16_t _8909 = (uint16_t)(232); + _curvea0[768] = _8909; + uint16_t _8910 = (uint16_t)(232); + _curvea0[769] = _8910; + uint16_t _8911 = (uint16_t)(232); + _curvea0[770] = _8911; + uint16_t _8912 = (uint16_t)(232); + _curvea0[771] = _8912; + uint16_t _8913 = (uint16_t)(232); + _curvea0[772] = _8913; + uint16_t _8914 = (uint16_t)(232); + _curvea0[773] = _8914; + uint16_t _8915 = (uint16_t)(232); + _curvea0[774] = _8915; + uint16_t _8916 = (uint16_t)(232); + _curvea0[775] = _8916; + uint16_t _8917 = (uint16_t)(233); + _curvea0[776] = _8917; + uint16_t _8918 = (uint16_t)(233); + _curvea0[777] = _8918; + uint16_t _8919 = (uint16_t)(233); + _curvea0[778] = _8919; + uint16_t _8920 = (uint16_t)(233); + _curvea0[779] = _8920; + uint16_t _8921 = (uint16_t)(233); + _curvea0[780] = _8921; + uint16_t _8922 = (uint16_t)(233); + _curvea0[781] = _8922; + uint16_t _8923 = (uint16_t)(233); + _curvea0[782] = _8923; + uint16_t _8924 = (uint16_t)(233); + _curvea0[783] = _8924; + uint16_t _8925 = (uint16_t)(233); + _curvea0[784] = _8925; + uint16_t _8926 = (uint16_t)(234); + _curvea0[785] = _8926; + uint16_t _8927 = (uint16_t)(234); + _curvea0[786] = _8927; + uint16_t _8928 = (uint16_t)(234); + _curvea0[787] = _8928; + uint16_t _8929 = (uint16_t)(234); + _curvea0[788] = _8929; + uint16_t _8930 = (uint16_t)(234); + _curvea0[789] = _8930; + uint16_t _8931 = (uint16_t)(234); + _curvea0[790] = _8931; + uint16_t _8932 = (uint16_t)(234); + _curvea0[791] = _8932; + uint16_t _8933 = (uint16_t)(234); + _curvea0[792] = _8933; + uint16_t _8934 = (uint16_t)(234); + _curvea0[793] = _8934; + uint16_t _8935 = (uint16_t)(235); + _curvea0[794] = _8935; + uint16_t _8936 = (uint16_t)(235); + _curvea0[795] = _8936; + uint16_t _8937 = (uint16_t)(235); + _curvea0[796] = _8937; + uint16_t _8938 = (uint16_t)(235); + _curvea0[797] = _8938; + uint16_t _8939 = (uint16_t)(235); + _curvea0[798] = _8939; + uint16_t _8940 = (uint16_t)(235); + _curvea0[799] = _8940; + uint16_t _8941 = (uint16_t)(235); + _curvea0[800] = _8941; + uint16_t _8942 = (uint16_t)(235); + _curvea0[801] = _8942; + uint16_t _8943 = (uint16_t)(235); + _curvea0[802] = _8943; + uint16_t _8944 = (uint16_t)(236); + _curvea0[803] = _8944; + uint16_t _8945 = (uint16_t)(236); + _curvea0[804] = _8945; + uint16_t _8946 = (uint16_t)(236); + _curvea0[805] = _8946; + uint16_t _8947 = (uint16_t)(236); + _curvea0[806] = _8947; + uint16_t _8948 = (uint16_t)(236); + _curvea0[807] = _8948; + uint16_t _8949 = (uint16_t)(236); + _curvea0[808] = _8949; + uint16_t _8950 = (uint16_t)(236); + _curvea0[809] = _8950; + uint16_t _8951 = (uint16_t)(236); + _curvea0[810] = _8951; + uint16_t _8952 = (uint16_t)(236); + _curvea0[811] = _8952; + uint16_t _8953 = (uint16_t)(237); + _curvea0[812] = _8953; + uint16_t _8954 = (uint16_t)(237); + _curvea0[813] = _8954; + uint16_t _8955 = (uint16_t)(237); + _curvea0[814] = _8955; + uint16_t _8956 = (uint16_t)(237); + _curvea0[815] = _8956; + uint16_t _8957 = (uint16_t)(237); + _curvea0[816] = _8957; + uint16_t _8958 = (uint16_t)(237); + _curvea0[817] = _8958; + uint16_t _8959 = (uint16_t)(237); + _curvea0[818] = _8959; + uint16_t _8960 = (uint16_t)(237); + _curvea0[819] = _8960; + uint16_t _8961 = (uint16_t)(237); + _curvea0[820] = _8961; + uint16_t _8962 = (uint16_t)(237); + _curvea0[821] = _8962; + uint16_t _8963 = (uint16_t)(238); + _curvea0[822] = _8963; + uint16_t _8964 = (uint16_t)(238); + _curvea0[823] = _8964; + uint16_t _8965 = (uint16_t)(238); + _curvea0[824] = _8965; + uint16_t _8966 = (uint16_t)(238); + _curvea0[825] = _8966; + uint16_t _8967 = (uint16_t)(238); + _curvea0[826] = _8967; + uint16_t _8968 = (uint16_t)(238); + _curvea0[827] = _8968; + uint16_t _8969 = (uint16_t)(238); + _curvea0[828] = _8969; + uint16_t _8970 = (uint16_t)(238); + _curvea0[829] = _8970; + uint16_t _8971 = (uint16_t)(238); + _curvea0[830] = _8971; + uint16_t _8972 = (uint16_t)(239); + _curvea0[831] = _8972; + uint16_t _8973 = (uint16_t)(239); + _curvea0[832] = _8973; + uint16_t _8974 = (uint16_t)(239); + _curvea0[833] = _8974; + uint16_t _8975 = (uint16_t)(239); + _curvea0[834] = _8975; + uint16_t _8976 = (uint16_t)(239); + _curvea0[835] = _8976; + uint16_t _8977 = (uint16_t)(239); + _curvea0[836] = _8977; + uint16_t _8978 = (uint16_t)(239); + _curvea0[837] = _8978; + uint16_t _8979 = (uint16_t)(239); + _curvea0[838] = _8979; + uint16_t _8980 = (uint16_t)(239); + _curvea0[839] = _8980; + uint16_t _8981 = (uint16_t)(239); + _curvea0[840] = _8981; + uint16_t _8982 = (uint16_t)(240); + _curvea0[841] = _8982; + uint16_t _8983 = (uint16_t)(240); + _curvea0[842] = _8983; + uint16_t _8984 = (uint16_t)(240); + _curvea0[843] = _8984; + uint16_t _8985 = (uint16_t)(240); + _curvea0[844] = _8985; + uint16_t _8986 = (uint16_t)(240); + _curvea0[845] = _8986; + uint16_t _8987 = (uint16_t)(240); + _curvea0[846] = _8987; + uint16_t _8988 = (uint16_t)(240); + _curvea0[847] = _8988; + uint16_t _8989 = (uint16_t)(240); + _curvea0[848] = _8989; + uint16_t _8990 = (uint16_t)(240); + _curvea0[849] = _8990; + uint16_t _8991 = (uint16_t)(240); + _curvea0[850] = _8991; + uint16_t _8992 = (uint16_t)(241); + _curvea0[851] = _8992; + uint16_t _8993 = (uint16_t)(241); + _curvea0[852] = _8993; + uint16_t _8994 = (uint16_t)(241); + _curvea0[853] = _8994; + uint16_t _8995 = (uint16_t)(241); + _curvea0[854] = _8995; + uint16_t _8996 = (uint16_t)(241); + _curvea0[855] = _8996; + uint16_t _8997 = (uint16_t)(241); + _curvea0[856] = _8997; + uint16_t _8998 = (uint16_t)(241); + _curvea0[857] = _8998; + uint16_t _8999 = (uint16_t)(241); + _curvea0[858] = _8999; + uint16_t _9000 = (uint16_t)(241); + _curvea0[859] = _9000; + uint16_t _9001 = (uint16_t)(241); + _curvea0[860] = _9001; + uint16_t _9002 = (uint16_t)(242); + _curvea0[861] = _9002; + uint16_t _9003 = (uint16_t)(242); + _curvea0[862] = _9003; + uint16_t _9004 = (uint16_t)(242); + _curvea0[863] = _9004; + uint16_t _9005 = (uint16_t)(242); + _curvea0[864] = _9005; + uint16_t _9006 = (uint16_t)(242); + _curvea0[865] = _9006; + uint16_t _9007 = (uint16_t)(242); + _curvea0[866] = _9007; + uint16_t _9008 = (uint16_t)(242); + _curvea0[867] = _9008; + uint16_t _9009 = (uint16_t)(242); + _curvea0[868] = _9009; + uint16_t _9010 = (uint16_t)(242); + _curvea0[869] = _9010; + uint16_t _9011 = (uint16_t)(242); + _curvea0[870] = _9011; + uint16_t _9012 = (uint16_t)(243); + _curvea0[871] = _9012; + uint16_t _9013 = (uint16_t)(243); + _curvea0[872] = _9013; + uint16_t _9014 = (uint16_t)(243); + _curvea0[873] = _9014; + uint16_t _9015 = (uint16_t)(243); + _curvea0[874] = _9015; + uint16_t _9016 = (uint16_t)(243); + _curvea0[875] = _9016; + uint16_t _9017 = (uint16_t)(243); + _curvea0[876] = _9017; + uint16_t _9018 = (uint16_t)(243); + _curvea0[877] = _9018; + uint16_t _9019 = (uint16_t)(243); + _curvea0[878] = _9019; + uint16_t _9020 = (uint16_t)(243); + _curvea0[879] = _9020; + uint16_t _9021 = (uint16_t)(243); + _curvea0[880] = _9021; + uint16_t _9022 = (uint16_t)(244); + _curvea0[881] = _9022; + uint16_t _9023 = (uint16_t)(244); + _curvea0[882] = _9023; + uint16_t _9024 = (uint16_t)(244); + _curvea0[883] = _9024; + uint16_t _9025 = (uint16_t)(244); + _curvea0[884] = _9025; + uint16_t _9026 = (uint16_t)(244); + _curvea0[885] = _9026; + uint16_t _9027 = (uint16_t)(244); + _curvea0[886] = _9027; + uint16_t _9028 = (uint16_t)(244); + _curvea0[887] = _9028; + uint16_t _9029 = (uint16_t)(244); + _curvea0[888] = _9029; + uint16_t _9030 = (uint16_t)(244); + _curvea0[889] = _9030; + uint16_t _9031 = (uint16_t)(244); + _curvea0[890] = _9031; + uint16_t _9032 = (uint16_t)(244); + _curvea0[891] = _9032; + uint16_t _9033 = (uint16_t)(245); + _curvea0[892] = _9033; + uint16_t _9034 = (uint16_t)(245); + _curvea0[893] = _9034; + uint16_t _9035 = (uint16_t)(245); + _curvea0[894] = _9035; + uint16_t _9036 = (uint16_t)(245); + _curvea0[895] = _9036; + uint16_t _9037 = (uint16_t)(245); + _curvea0[896] = _9037; + uint16_t _9038 = (uint16_t)(245); + _curvea0[897] = _9038; + uint16_t _9039 = (uint16_t)(245); + _curvea0[898] = _9039; + uint16_t _9040 = (uint16_t)(245); + _curvea0[899] = _9040; + uint16_t _9041 = (uint16_t)(245); + _curvea0[900] = _9041; + uint16_t _9042 = (uint16_t)(245); + _curvea0[901] = _9042; + uint16_t _9043 = (uint16_t)(245); + _curvea0[902] = _9043; + uint16_t _9044 = (uint16_t)(246); + _curvea0[903] = _9044; + uint16_t _9045 = (uint16_t)(246); + _curvea0[904] = _9045; + uint16_t _9046 = (uint16_t)(246); + _curvea0[905] = _9046; + uint16_t _9047 = (uint16_t)(246); + _curvea0[906] = _9047; + uint16_t _9048 = (uint16_t)(246); + _curvea0[907] = _9048; + uint16_t _9049 = (uint16_t)(246); + _curvea0[908] = _9049; + uint16_t _9050 = (uint16_t)(246); + _curvea0[909] = _9050; + uint16_t _9051 = (uint16_t)(246); + _curvea0[910] = _9051; + uint16_t _9052 = (uint16_t)(246); + _curvea0[911] = _9052; + uint16_t _9053 = (uint16_t)(246); + _curvea0[912] = _9053; + uint16_t _9054 = (uint16_t)(246); + _curvea0[913] = _9054; + uint16_t _9055 = (uint16_t)(247); + _curvea0[914] = _9055; + uint16_t _9056 = (uint16_t)(247); + _curvea0[915] = _9056; + uint16_t _9057 = (uint16_t)(247); + _curvea0[916] = _9057; + uint16_t _9058 = (uint16_t)(247); + _curvea0[917] = _9058; + uint16_t _9059 = (uint16_t)(247); + _curvea0[918] = _9059; + uint16_t _9060 = (uint16_t)(247); + _curvea0[919] = _9060; + uint16_t _9061 = (uint16_t)(247); + _curvea0[920] = _9061; + uint16_t _9062 = (uint16_t)(247); + _curvea0[921] = _9062; + uint16_t _9063 = (uint16_t)(247); + _curvea0[922] = _9063; + uint16_t _9064 = (uint16_t)(247); + _curvea0[923] = _9064; + uint16_t _9065 = (uint16_t)(247); + _curvea0[924] = _9065; + uint16_t _9066 = (uint16_t)(248); + _curvea0[925] = _9066; + uint16_t _9067 = (uint16_t)(248); + _curvea0[926] = _9067; + uint16_t _9068 = (uint16_t)(248); + _curvea0[927] = _9068; + uint16_t _9069 = (uint16_t)(248); + _curvea0[928] = _9069; + uint16_t _9070 = (uint16_t)(248); + _curvea0[929] = _9070; + uint16_t _9071 = (uint16_t)(248); + _curvea0[930] = _9071; + uint16_t _9072 = (uint16_t)(248); + _curvea0[931] = _9072; + uint16_t _9073 = (uint16_t)(248); + _curvea0[932] = _9073; + uint16_t _9074 = (uint16_t)(248); + _curvea0[933] = _9074; + uint16_t _9075 = (uint16_t)(248); + _curvea0[934] = _9075; + uint16_t _9076 = (uint16_t)(248); + _curvea0[935] = _9076; + uint16_t _9077 = (uint16_t)(249); + _curvea0[936] = _9077; + uint16_t _9078 = (uint16_t)(249); + _curvea0[937] = _9078; + uint16_t _9079 = (uint16_t)(249); + _curvea0[938] = _9079; + uint16_t _9080 = (uint16_t)(249); + _curvea0[939] = _9080; + uint16_t _9081 = (uint16_t)(249); + _curvea0[940] = _9081; + uint16_t _9082 = (uint16_t)(249); + _curvea0[941] = _9082; + uint16_t _9083 = (uint16_t)(249); + _curvea0[942] = _9083; + uint16_t _9084 = (uint16_t)(249); + _curvea0[943] = _9084; + uint16_t _9085 = (uint16_t)(249); + _curvea0[944] = _9085; + uint16_t _9086 = (uint16_t)(249); + _curvea0[945] = _9086; + uint16_t _9087 = (uint16_t)(249); + _curvea0[946] = _9087; + uint16_t _9088 = (uint16_t)(249); + _curvea0[947] = _9088; + uint16_t _9089 = (uint16_t)(250); + _curvea0[948] = _9089; + uint16_t _9090 = (uint16_t)(250); + _curvea0[949] = _9090; + uint16_t _9091 = (uint16_t)(250); + _curvea0[950] = _9091; + uint16_t _9092 = (uint16_t)(250); + _curvea0[951] = _9092; + uint16_t _9093 = (uint16_t)(250); + _curvea0[952] = _9093; + uint16_t _9094 = (uint16_t)(250); + _curvea0[953] = _9094; + uint16_t _9095 = (uint16_t)(250); + _curvea0[954] = _9095; + uint16_t _9096 = (uint16_t)(250); + _curvea0[955] = _9096; + uint16_t _9097 = (uint16_t)(250); + _curvea0[956] = _9097; + uint16_t _9098 = (uint16_t)(250); + _curvea0[957] = _9098; + uint16_t _9099 = (uint16_t)(250); + _curvea0[958] = _9099; + uint16_t _9100 = (uint16_t)(250); + _curvea0[959] = _9100; + uint16_t _9101 = (uint16_t)(251); + _curvea0[960] = _9101; + uint16_t _9102 = (uint16_t)(251); + _curvea0[961] = _9102; + uint16_t _9103 = (uint16_t)(251); + _curvea0[962] = _9103; + uint16_t _9104 = (uint16_t)(251); + _curvea0[963] = _9104; + uint16_t _9105 = (uint16_t)(251); + _curvea0[964] = _9105; + uint16_t _9106 = (uint16_t)(251); + _curvea0[965] = _9106; + uint16_t _9107 = (uint16_t)(251); + _curvea0[966] = _9107; + uint16_t _9108 = (uint16_t)(251); + _curvea0[967] = _9108; + uint16_t _9109 = (uint16_t)(251); + _curvea0[968] = _9109; + uint16_t _9110 = (uint16_t)(251); + _curvea0[969] = _9110; + uint16_t _9111 = (uint16_t)(251); + _curvea0[970] = _9111; + uint16_t _9112 = (uint16_t)(251); + _curvea0[971] = _9112; + uint16_t _9113 = (uint16_t)(252); + _curvea0[972] = _9113; + uint16_t _9114 = (uint16_t)(252); + _curvea0[973] = _9114; + uint16_t _9115 = (uint16_t)(252); + _curvea0[974] = _9115; + uint16_t _9116 = (uint16_t)(252); + _curvea0[975] = _9116; + uint16_t _9117 = (uint16_t)(252); + _curvea0[976] = _9117; + uint16_t _9118 = (uint16_t)(252); + _curvea0[977] = _9118; + uint16_t _9119 = (uint16_t)(252); + _curvea0[978] = _9119; + uint16_t _9120 = (uint16_t)(252); + _curvea0[979] = _9120; + uint16_t _9121 = (uint16_t)(252); + _curvea0[980] = _9121; + uint16_t _9122 = (uint16_t)(252); + _curvea0[981] = _9122; + uint16_t _9123 = (uint16_t)(252); + _curvea0[982] = _9123; + uint16_t _9124 = (uint16_t)(252); + _curvea0[983] = _9124; + uint16_t _9125 = (uint16_t)(252); + _curvea0[984] = _9125; + uint16_t _9126 = (uint16_t)(253); + _curvea0[985] = _9126; + uint16_t _9127 = (uint16_t)(253); + _curvea0[986] = _9127; + uint16_t _9128 = (uint16_t)(253); + _curvea0[987] = _9128; + uint16_t _9129 = (uint16_t)(253); + _curvea0[988] = _9129; + uint16_t _9130 = (uint16_t)(253); + _curvea0[989] = _9130; + uint16_t _9131 = (uint16_t)(253); + _curvea0[990] = _9131; + uint16_t _9132 = (uint16_t)(253); + _curvea0[991] = _9132; + uint16_t _9133 = (uint16_t)(253); + _curvea0[992] = _9133; + uint16_t _9134 = (uint16_t)(253); + _curvea0[993] = _9134; + uint16_t _9135 = (uint16_t)(253); + _curvea0[994] = _9135; + uint16_t _9136 = (uint16_t)(253); + _curvea0[995] = _9136; + uint16_t _9137 = (uint16_t)(253); + _curvea0[996] = _9137; + uint16_t _9138 = (uint16_t)(253); + _curvea0[997] = _9138; + uint16_t _9139 = (uint16_t)(254); + _curvea0[998] = _9139; + uint16_t _9140 = (uint16_t)(254); + _curvea0[999] = _9140; + uint16_t _9141 = (uint16_t)(254); + _curvea0[1000] = _9141; + uint16_t _9142 = (uint16_t)(254); + _curvea0[1001] = _9142; + uint16_t _9143 = (uint16_t)(254); + _curvea0[1002] = _9143; + uint16_t _9144 = (uint16_t)(254); + _curvea0[1003] = _9144; + uint16_t _9145 = (uint16_t)(254); + _curvea0[1004] = _9145; + uint16_t _9146 = (uint16_t)(254); + _curvea0[1005] = _9146; + uint16_t _9147 = (uint16_t)(254); + _curvea0[1006] = _9147; + uint16_t _9148 = (uint16_t)(254); + _curvea0[1007] = _9148; + uint16_t _9149 = (uint16_t)(254); + _curvea0[1008] = _9149; + uint16_t _9150 = (uint16_t)(254); + _curvea0[1009] = _9150; + uint16_t _9151 = (uint16_t)(254); + _curvea0[1010] = _9151; + uint16_t _9152 = (uint16_t)(255); + _curvea0[1011] = _9152; + uint16_t _9153 = (uint16_t)(255); + _curvea0[1012] = _9153; + uint16_t _9154 = (uint16_t)(255); + _curvea0[1013] = _9154; + uint16_t _9155 = (uint16_t)(255); + _curvea0[1014] = _9155; + uint16_t _9156 = (uint16_t)(255); + _curvea0[1015] = _9156; + uint16_t _9157 = (uint16_t)(255); + _curvea0[1016] = _9157; + uint16_t _9158 = (uint16_t)(255); + _curvea0[1017] = _9158; + uint16_t _9159 = (uint16_t)(255); + _curvea0[1018] = _9159; + uint16_t _9160 = (uint16_t)(255); + _curvea0[1019] = _9160; + uint16_t _9161 = (uint16_t)(255); + _curvea0[1020] = _9161; + uint16_t _9162 = (uint16_t)(255); + _curvea0[1021] = _9162; + uint16_t _9163 = (uint16_t)(255); + _curvea0[1022] = _9163; + uint16_t _9164 = (uint16_t)(255); + _curvea0[1023] = _9164; + + int16_t _9165 = (int16_t)(1023); + int16_t _9166 = min(_corrected_stencil_5, _9165); + int16_t _9167 = (int16_t)(0); + int16_t _9168 = max(_9166, _9167); + uint16_t _9169 = (uint16_t)(_9168); + int32_t _9170 = (int32_t)(_9169); + uint16_t _9171 = ((const uint16_t *)_curvea0)[_9170]; + return _9171; +} + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_5(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_6 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _9189 = (uint16_t)(0); + _curvea0[0] = _9189; + uint16_t _9190 = (uint16_t)(4); + _curvea0[1] = _9190; + uint16_t _9191 = (uint16_t)(7); + _curvea0[2] = _9191; + uint16_t _9192 = (uint16_t)(8); + _curvea0[3] = _9192; + uint16_t _9193 = (uint16_t)(10); + _curvea0[4] = _9193; + uint16_t _9194 = (uint16_t)(11); + _curvea0[5] = _9194; + uint16_t _9195 = (uint16_t)(12); + _curvea0[6] = _9195; + uint16_t _9196 = (uint16_t)(13); + _curvea0[7] = _9196; + uint16_t _9197 = (uint16_t)(14); + _curvea0[8] = _9197; + uint16_t _9198 = (uint16_t)(15); + _curvea0[9] = _9198; + uint16_t _9199 = (uint16_t)(16); + _curvea0[10] = _9199; + uint16_t _9200 = (uint16_t)(17); + _curvea0[11] = _9200; + uint16_t _9201 = (uint16_t)(18); + _curvea0[12] = _9201; + uint16_t _9202 = (uint16_t)(19); + _curvea0[13] = _9202; + uint16_t _9203 = (uint16_t)(20); + _curvea0[14] = _9203; + uint16_t _9204 = (uint16_t)(21); + _curvea0[15] = _9204; + uint16_t _9205 = (uint16_t)(22); + _curvea0[16] = _9205; + uint16_t _9206 = (uint16_t)(22); + _curvea0[17] = _9206; + uint16_t _9207 = (uint16_t)(23); + _curvea0[18] = _9207; + uint16_t _9208 = (uint16_t)(24); + _curvea0[19] = _9208; + uint16_t _9209 = (uint16_t)(25); + _curvea0[20] = _9209; + uint16_t _9210 = (uint16_t)(25); + _curvea0[21] = _9210; + uint16_t _9211 = (uint16_t)(26); + _curvea0[22] = _9211; + uint16_t _9212 = (uint16_t)(27); + _curvea0[23] = _9212; + uint16_t _9213 = (uint16_t)(27); + _curvea0[24] = _9213; + uint16_t _9214 = (uint16_t)(28); + _curvea0[25] = _9214; + uint16_t _9215 = (uint16_t)(29); + _curvea0[26] = _9215; + uint16_t _9216 = (uint16_t)(29); + _curvea0[27] = _9216; + uint16_t _9217 = (uint16_t)(30); + _curvea0[28] = _9217; + uint16_t _9218 = (uint16_t)(31); + _curvea0[29] = _9218; + uint16_t _9219 = (uint16_t)(31); + _curvea0[30] = _9219; + uint16_t _9220 = (uint16_t)(32); + _curvea0[31] = _9220; + uint16_t _9221 = (uint16_t)(33); + _curvea0[32] = _9221; + uint16_t _9222 = (uint16_t)(33); + _curvea0[33] = _9222; + uint16_t _9223 = (uint16_t)(34); + _curvea0[34] = _9223; + uint16_t _9224 = (uint16_t)(34); + _curvea0[35] = _9224; + uint16_t _9225 = (uint16_t)(35); + _curvea0[36] = _9225; + uint16_t _9226 = (uint16_t)(36); + _curvea0[37] = _9226; + uint16_t _9227 = (uint16_t)(36); + _curvea0[38] = _9227; + uint16_t _9228 = (uint16_t)(37); + _curvea0[39] = _9228; + uint16_t _9229 = (uint16_t)(37); + _curvea0[40] = _9229; + uint16_t _9230 = (uint16_t)(38); + _curvea0[41] = _9230; + uint16_t _9231 = (uint16_t)(39); + _curvea0[42] = _9231; + uint16_t _9232 = (uint16_t)(39); + _curvea0[43] = _9232; + uint16_t _9233 = (uint16_t)(40); + _curvea0[44] = _9233; + uint16_t _9234 = (uint16_t)(40); + _curvea0[45] = _9234; + uint16_t _9235 = (uint16_t)(41); + _curvea0[46] = _9235; + uint16_t _9236 = (uint16_t)(41); + _curvea0[47] = _9236; + uint16_t _9237 = (uint16_t)(42); + _curvea0[48] = _9237; + uint16_t _9238 = (uint16_t)(42); + _curvea0[49] = _9238; + uint16_t _9239 = (uint16_t)(43); + _curvea0[50] = _9239; + uint16_t _9240 = (uint16_t)(44); + _curvea0[51] = _9240; + uint16_t _9241 = (uint16_t)(44); + _curvea0[52] = _9241; + uint16_t _9242 = (uint16_t)(45); + _curvea0[53] = _9242; + uint16_t _9243 = (uint16_t)(45); + _curvea0[54] = _9243; + uint16_t _9244 = (uint16_t)(46); + _curvea0[55] = _9244; + uint16_t _9245 = (uint16_t)(46); + _curvea0[56] = _9245; + uint16_t _9246 = (uint16_t)(47); + _curvea0[57] = _9246; + uint16_t _9247 = (uint16_t)(47); + _curvea0[58] = _9247; + uint16_t _9248 = (uint16_t)(48); + _curvea0[59] = _9248; + uint16_t _9249 = (uint16_t)(48); + _curvea0[60] = _9249; + uint16_t _9250 = (uint16_t)(49); + _curvea0[61] = _9250; + uint16_t _9251 = (uint16_t)(49); + _curvea0[62] = _9251; + uint16_t _9252 = (uint16_t)(50); + _curvea0[63] = _9252; + uint16_t _9253 = (uint16_t)(50); + _curvea0[64] = _9253; + uint16_t _9254 = (uint16_t)(51); + _curvea0[65] = _9254; + uint16_t _9255 = (uint16_t)(51); + _curvea0[66] = _9255; + uint16_t _9256 = (uint16_t)(52); + _curvea0[67] = _9256; + uint16_t _9257 = (uint16_t)(52); + _curvea0[68] = _9257; + uint16_t _9258 = (uint16_t)(53); + _curvea0[69] = _9258; + uint16_t _9259 = (uint16_t)(53); + _curvea0[70] = _9259; + uint16_t _9260 = (uint16_t)(54); + _curvea0[71] = _9260; + uint16_t _9261 = (uint16_t)(54); + _curvea0[72] = _9261; + uint16_t _9262 = (uint16_t)(55); + _curvea0[73] = _9262; + uint16_t _9263 = (uint16_t)(55); + _curvea0[74] = _9263; + uint16_t _9264 = (uint16_t)(56); + _curvea0[75] = _9264; + uint16_t _9265 = (uint16_t)(56); + _curvea0[76] = _9265; + uint16_t _9266 = (uint16_t)(57); + _curvea0[77] = _9266; + uint16_t _9267 = (uint16_t)(57); + _curvea0[78] = _9267; + uint16_t _9268 = (uint16_t)(58); + _curvea0[79] = _9268; + uint16_t _9269 = (uint16_t)(58); + _curvea0[80] = _9269; + uint16_t _9270 = (uint16_t)(58); + _curvea0[81] = _9270; + uint16_t _9271 = (uint16_t)(59); + _curvea0[82] = _9271; + uint16_t _9272 = (uint16_t)(59); + _curvea0[83] = _9272; + uint16_t _9273 = (uint16_t)(60); + _curvea0[84] = _9273; + uint16_t _9274 = (uint16_t)(60); + _curvea0[85] = _9274; + uint16_t _9275 = (uint16_t)(61); + _curvea0[86] = _9275; + uint16_t _9276 = (uint16_t)(61); + _curvea0[87] = _9276; + uint16_t _9277 = (uint16_t)(62); + _curvea0[88] = _9277; + uint16_t _9278 = (uint16_t)(62); + _curvea0[89] = _9278; + uint16_t _9279 = (uint16_t)(63); + _curvea0[90] = _9279; + uint16_t _9280 = (uint16_t)(63); + _curvea0[91] = _9280; + uint16_t _9281 = (uint16_t)(64); + _curvea0[92] = _9281; + uint16_t _9282 = (uint16_t)(64); + _curvea0[93] = _9282; + uint16_t _9283 = (uint16_t)(64); + _curvea0[94] = _9283; + uint16_t _9284 = (uint16_t)(65); + _curvea0[95] = _9284; + uint16_t _9285 = (uint16_t)(65); + _curvea0[96] = _9285; + uint16_t _9286 = (uint16_t)(66); + _curvea0[97] = _9286; + uint16_t _9287 = (uint16_t)(66); + _curvea0[98] = _9287; + uint16_t _9288 = (uint16_t)(67); + _curvea0[99] = _9288; + uint16_t _9289 = (uint16_t)(67); + _curvea0[100] = _9289; + uint16_t _9290 = (uint16_t)(68); + _curvea0[101] = _9290; + uint16_t _9291 = (uint16_t)(68); + _curvea0[102] = _9291; + uint16_t _9292 = (uint16_t)(68); + _curvea0[103] = _9292; + uint16_t _9293 = (uint16_t)(69); + _curvea0[104] = _9293; + uint16_t _9294 = (uint16_t)(69); + _curvea0[105] = _9294; + uint16_t _9295 = (uint16_t)(70); + _curvea0[106] = _9295; + uint16_t _9296 = (uint16_t)(70); + _curvea0[107] = _9296; + uint16_t _9297 = (uint16_t)(71); + _curvea0[108] = _9297; + uint16_t _9298 = (uint16_t)(71); + _curvea0[109] = _9298; + uint16_t _9299 = (uint16_t)(71); + _curvea0[110] = _9299; + uint16_t _9300 = (uint16_t)(72); + _curvea0[111] = _9300; + uint16_t _9301 = (uint16_t)(72); + _curvea0[112] = _9301; + uint16_t _9302 = (uint16_t)(73); + _curvea0[113] = _9302; + uint16_t _9303 = (uint16_t)(73); + _curvea0[114] = _9303; + uint16_t _9304 = (uint16_t)(74); + _curvea0[115] = _9304; + uint16_t _9305 = (uint16_t)(74); + _curvea0[116] = _9305; + uint16_t _9306 = (uint16_t)(74); + _curvea0[117] = _9306; + uint16_t _9307 = (uint16_t)(75); + _curvea0[118] = _9307; + uint16_t _9308 = (uint16_t)(75); + _curvea0[119] = _9308; + uint16_t _9309 = (uint16_t)(76); + _curvea0[120] = _9309; + uint16_t _9310 = (uint16_t)(76); + _curvea0[121] = _9310; + uint16_t _9311 = (uint16_t)(77); + _curvea0[122] = _9311; + uint16_t _9312 = (uint16_t)(77); + _curvea0[123] = _9312; + uint16_t _9313 = (uint16_t)(77); + _curvea0[124] = _9313; + uint16_t _9314 = (uint16_t)(78); + _curvea0[125] = _9314; + uint16_t _9315 = (uint16_t)(78); + _curvea0[126] = _9315; + uint16_t _9316 = (uint16_t)(79); + _curvea0[127] = _9316; + uint16_t _9317 = (uint16_t)(79); + _curvea0[128] = _9317; + uint16_t _9318 = (uint16_t)(79); + _curvea0[129] = _9318; + uint16_t _9319 = (uint16_t)(80); + _curvea0[130] = _9319; + uint16_t _9320 = (uint16_t)(80); + _curvea0[131] = _9320; + uint16_t _9321 = (uint16_t)(81); + _curvea0[132] = _9321; + uint16_t _9322 = (uint16_t)(81); + _curvea0[133] = _9322; + uint16_t _9323 = (uint16_t)(82); + _curvea0[134] = _9323; + uint16_t _9324 = (uint16_t)(82); + _curvea0[135] = _9324; + uint16_t _9325 = (uint16_t)(82); + _curvea0[136] = _9325; + uint16_t _9326 = (uint16_t)(83); + _curvea0[137] = _9326; + uint16_t _9327 = (uint16_t)(83); + _curvea0[138] = _9327; + uint16_t _9328 = (uint16_t)(84); + _curvea0[139] = _9328; + uint16_t _9329 = (uint16_t)(84); + _curvea0[140] = _9329; + uint16_t _9330 = (uint16_t)(84); + _curvea0[141] = _9330; + uint16_t _9331 = (uint16_t)(85); + _curvea0[142] = _9331; + uint16_t _9332 = (uint16_t)(85); + _curvea0[143] = _9332; + uint16_t _9333 = (uint16_t)(86); + _curvea0[144] = _9333; + uint16_t _9334 = (uint16_t)(86); + _curvea0[145] = _9334; + uint16_t _9335 = (uint16_t)(86); + _curvea0[146] = _9335; + uint16_t _9336 = (uint16_t)(87); + _curvea0[147] = _9336; + uint16_t _9337 = (uint16_t)(87); + _curvea0[148] = _9337; + uint16_t _9338 = (uint16_t)(88); + _curvea0[149] = _9338; + uint16_t _9339 = (uint16_t)(88); + _curvea0[150] = _9339; + uint16_t _9340 = (uint16_t)(88); + _curvea0[151] = _9340; + uint16_t _9341 = (uint16_t)(89); + _curvea0[152] = _9341; + uint16_t _9342 = (uint16_t)(89); + _curvea0[153] = _9342; + uint16_t _9343 = (uint16_t)(90); + _curvea0[154] = _9343; + uint16_t _9344 = (uint16_t)(90); + _curvea0[155] = _9344; + uint16_t _9345 = (uint16_t)(90); + _curvea0[156] = _9345; + uint16_t _9346 = (uint16_t)(91); + _curvea0[157] = _9346; + uint16_t _9347 = (uint16_t)(91); + _curvea0[158] = _9347; + uint16_t _9348 = (uint16_t)(92); + _curvea0[159] = _9348; + uint16_t _9349 = (uint16_t)(92); + _curvea0[160] = _9349; + uint16_t _9350 = (uint16_t)(92); + _curvea0[161] = _9350; + uint16_t _9351 = (uint16_t)(93); + _curvea0[162] = _9351; + uint16_t _9352 = (uint16_t)(93); + _curvea0[163] = _9352; + uint16_t _9353 = (uint16_t)(93); + _curvea0[164] = _9353; + uint16_t _9354 = (uint16_t)(94); + _curvea0[165] = _9354; + uint16_t _9355 = (uint16_t)(94); + _curvea0[166] = _9355; + uint16_t _9356 = (uint16_t)(95); + _curvea0[167] = _9356; + uint16_t _9357 = (uint16_t)(95); + _curvea0[168] = _9357; + uint16_t _9358 = (uint16_t)(95); + _curvea0[169] = _9358; + uint16_t _9359 = (uint16_t)(96); + _curvea0[170] = _9359; + uint16_t _9360 = (uint16_t)(96); + _curvea0[171] = _9360; + uint16_t _9361 = (uint16_t)(97); + _curvea0[172] = _9361; + uint16_t _9362 = (uint16_t)(97); + _curvea0[173] = _9362; + uint16_t _9363 = (uint16_t)(97); + _curvea0[174] = _9363; + uint16_t _9364 = (uint16_t)(98); + _curvea0[175] = _9364; + uint16_t _9365 = (uint16_t)(98); + _curvea0[176] = _9365; + uint16_t _9366 = (uint16_t)(99); + _curvea0[177] = _9366; + uint16_t _9367 = (uint16_t)(99); + _curvea0[178] = _9367; + uint16_t _9368 = (uint16_t)(99); + _curvea0[179] = _9368; + uint16_t _9369 = (uint16_t)(100); + _curvea0[180] = _9369; + uint16_t _9370 = (uint16_t)(100); + _curvea0[181] = _9370; + uint16_t _9371 = (uint16_t)(100); + _curvea0[182] = _9371; + uint16_t _9372 = (uint16_t)(101); + _curvea0[183] = _9372; + uint16_t _9373 = (uint16_t)(101); + _curvea0[184] = _9373; + uint16_t _9374 = (uint16_t)(102); + _curvea0[185] = _9374; + uint16_t _9375 = (uint16_t)(102); + _curvea0[186] = _9375; + uint16_t _9376 = (uint16_t)(102); + _curvea0[187] = _9376; + uint16_t _9377 = (uint16_t)(103); + _curvea0[188] = _9377; + uint16_t _9378 = (uint16_t)(103); + _curvea0[189] = _9378; + uint16_t _9379 = (uint16_t)(103); + _curvea0[190] = _9379; + uint16_t _9380 = (uint16_t)(104); + _curvea0[191] = _9380; + uint16_t _9381 = (uint16_t)(104); + _curvea0[192] = _9381; + uint16_t _9382 = (uint16_t)(105); + _curvea0[193] = _9382; + uint16_t _9383 = (uint16_t)(105); + _curvea0[194] = _9383; + uint16_t _9384 = (uint16_t)(105); + _curvea0[195] = _9384; + uint16_t _9385 = (uint16_t)(106); + _curvea0[196] = _9385; + uint16_t _9386 = (uint16_t)(106); + _curvea0[197] = _9386; + uint16_t _9387 = (uint16_t)(106); + _curvea0[198] = _9387; + uint16_t _9388 = (uint16_t)(107); + _curvea0[199] = _9388; + uint16_t _9389 = (uint16_t)(107); + _curvea0[200] = _9389; + uint16_t _9390 = (uint16_t)(108); + _curvea0[201] = _9390; + uint16_t _9391 = (uint16_t)(108); + _curvea0[202] = _9391; + uint16_t _9392 = (uint16_t)(108); + _curvea0[203] = _9392; + uint16_t _9393 = (uint16_t)(109); + _curvea0[204] = _9393; + uint16_t _9394 = (uint16_t)(109); + _curvea0[205] = _9394; + uint16_t _9395 = (uint16_t)(109); + _curvea0[206] = _9395; + uint16_t _9396 = (uint16_t)(110); + _curvea0[207] = _9396; + uint16_t _9397 = (uint16_t)(110); + _curvea0[208] = _9397; + uint16_t _9398 = (uint16_t)(111); + _curvea0[209] = _9398; + uint16_t _9399 = (uint16_t)(111); + _curvea0[210] = _9399; + uint16_t _9400 = (uint16_t)(111); + _curvea0[211] = _9400; + uint16_t _9401 = (uint16_t)(112); + _curvea0[212] = _9401; + uint16_t _9402 = (uint16_t)(112); + _curvea0[213] = _9402; + uint16_t _9403 = (uint16_t)(112); + _curvea0[214] = _9403; + uint16_t _9404 = (uint16_t)(113); + _curvea0[215] = _9404; + uint16_t _9405 = (uint16_t)(113); + _curvea0[216] = _9405; + uint16_t _9406 = (uint16_t)(113); + _curvea0[217] = _9406; + uint16_t _9407 = (uint16_t)(114); + _curvea0[218] = _9407; + uint16_t _9408 = (uint16_t)(114); + _curvea0[219] = _9408; + uint16_t _9409 = (uint16_t)(115); + _curvea0[220] = _9409; + uint16_t _9410 = (uint16_t)(115); + _curvea0[221] = _9410; + uint16_t _9411 = (uint16_t)(115); + _curvea0[222] = _9411; + uint16_t _9412 = (uint16_t)(116); + _curvea0[223] = _9412; + uint16_t _9413 = (uint16_t)(116); + _curvea0[224] = _9413; + uint16_t _9414 = (uint16_t)(116); + _curvea0[225] = _9414; + uint16_t _9415 = (uint16_t)(117); + _curvea0[226] = _9415; + uint16_t _9416 = (uint16_t)(117); + _curvea0[227] = _9416; + uint16_t _9417 = (uint16_t)(117); + _curvea0[228] = _9417; + uint16_t _9418 = (uint16_t)(118); + _curvea0[229] = _9418; + uint16_t _9419 = (uint16_t)(118); + _curvea0[230] = _9419; + uint16_t _9420 = (uint16_t)(119); + _curvea0[231] = _9420; + uint16_t _9421 = (uint16_t)(119); + _curvea0[232] = _9421; + uint16_t _9422 = (uint16_t)(119); + _curvea0[233] = _9422; + uint16_t _9423 = (uint16_t)(120); + _curvea0[234] = _9423; + uint16_t _9424 = (uint16_t)(120); + _curvea0[235] = _9424; + uint16_t _9425 = (uint16_t)(120); + _curvea0[236] = _9425; + uint16_t _9426 = (uint16_t)(121); + _curvea0[237] = _9426; + uint16_t _9427 = (uint16_t)(121); + _curvea0[238] = _9427; + uint16_t _9428 = (uint16_t)(121); + _curvea0[239] = _9428; + uint16_t _9429 = (uint16_t)(122); + _curvea0[240] = _9429; + uint16_t _9430 = (uint16_t)(122); + _curvea0[241] = _9430; + uint16_t _9431 = (uint16_t)(123); + _curvea0[242] = _9431; + uint16_t _9432 = (uint16_t)(123); + _curvea0[243] = _9432; + uint16_t _9433 = (uint16_t)(123); + _curvea0[244] = _9433; + uint16_t _9434 = (uint16_t)(124); + _curvea0[245] = _9434; + uint16_t _9435 = (uint16_t)(124); + _curvea0[246] = _9435; + uint16_t _9436 = (uint16_t)(124); + _curvea0[247] = _9436; + uint16_t _9437 = (uint16_t)(125); + _curvea0[248] = _9437; + uint16_t _9438 = (uint16_t)(125); + _curvea0[249] = _9438; + uint16_t _9439 = (uint16_t)(125); + _curvea0[250] = _9439; + uint16_t _9440 = (uint16_t)(126); + _curvea0[251] = _9440; + uint16_t _9441 = (uint16_t)(126); + _curvea0[252] = _9441; + uint16_t _9442 = (uint16_t)(126); + _curvea0[253] = _9442; + uint16_t _9443 = (uint16_t)(127); + _curvea0[254] = _9443; + uint16_t _9444 = (uint16_t)(127); + _curvea0[255] = _9444; + uint16_t _9445 = (uint16_t)(128); + _curvea0[256] = _9445; + uint16_t _9446 = (uint16_t)(128); + _curvea0[257] = _9446; + uint16_t _9447 = (uint16_t)(128); + _curvea0[258] = _9447; + uint16_t _9448 = (uint16_t)(129); + _curvea0[259] = _9448; + uint16_t _9449 = (uint16_t)(129); + _curvea0[260] = _9449; + uint16_t _9450 = (uint16_t)(129); + _curvea0[261] = _9450; + uint16_t _9451 = (uint16_t)(130); + _curvea0[262] = _9451; + uint16_t _9452 = (uint16_t)(130); + _curvea0[263] = _9452; + uint16_t _9453 = (uint16_t)(130); + _curvea0[264] = _9453; + uint16_t _9454 = (uint16_t)(131); + _curvea0[265] = _9454; + uint16_t _9455 = (uint16_t)(131); + _curvea0[266] = _9455; + uint16_t _9456 = (uint16_t)(131); + _curvea0[267] = _9456; + uint16_t _9457 = (uint16_t)(132); + _curvea0[268] = _9457; + uint16_t _9458 = (uint16_t)(132); + _curvea0[269] = _9458; + uint16_t _9459 = (uint16_t)(132); + _curvea0[270] = _9459; + uint16_t _9460 = (uint16_t)(133); + _curvea0[271] = _9460; + uint16_t _9461 = (uint16_t)(133); + _curvea0[272] = _9461; + uint16_t _9462 = (uint16_t)(133); + _curvea0[273] = _9462; + uint16_t _9463 = (uint16_t)(134); + _curvea0[274] = _9463; + uint16_t _9464 = (uint16_t)(134); + _curvea0[275] = _9464; + uint16_t _9465 = (uint16_t)(134); + _curvea0[276] = _9465; + uint16_t _9466 = (uint16_t)(135); + _curvea0[277] = _9466; + uint16_t _9467 = (uint16_t)(135); + _curvea0[278] = _9467; + uint16_t _9468 = (uint16_t)(135); + _curvea0[279] = _9468; + uint16_t _9469 = (uint16_t)(136); + _curvea0[280] = _9469; + uint16_t _9470 = (uint16_t)(136); + _curvea0[281] = _9470; + uint16_t _9471 = (uint16_t)(136); + _curvea0[282] = _9471; + uint16_t _9472 = (uint16_t)(137); + _curvea0[283] = _9472; + uint16_t _9473 = (uint16_t)(137); + _curvea0[284] = _9473; + uint16_t _9474 = (uint16_t)(137); + _curvea0[285] = _9474; + uint16_t _9475 = (uint16_t)(138); + _curvea0[286] = _9475; + uint16_t _9476 = (uint16_t)(138); + _curvea0[287] = _9476; + uint16_t _9477 = (uint16_t)(138); + _curvea0[288] = _9477; + uint16_t _9478 = (uint16_t)(139); + _curvea0[289] = _9478; + uint16_t _9479 = (uint16_t)(139); + _curvea0[290] = _9479; + uint16_t _9480 = (uint16_t)(139); + _curvea0[291] = _9480; + uint16_t _9481 = (uint16_t)(140); + _curvea0[292] = _9481; + uint16_t _9482 = (uint16_t)(140); + _curvea0[293] = _9482; + uint16_t _9483 = (uint16_t)(140); + _curvea0[294] = _9483; + uint16_t _9484 = (uint16_t)(141); + _curvea0[295] = _9484; + uint16_t _9485 = (uint16_t)(141); + _curvea0[296] = _9485; + uint16_t _9486 = (uint16_t)(141); + _curvea0[297] = _9486; + uint16_t _9487 = (uint16_t)(141); + _curvea0[298] = _9487; + uint16_t _9488 = (uint16_t)(142); + _curvea0[299] = _9488; + uint16_t _9489 = (uint16_t)(142); + _curvea0[300] = _9489; + uint16_t _9490 = (uint16_t)(142); + _curvea0[301] = _9490; + uint16_t _9491 = (uint16_t)(143); + _curvea0[302] = _9491; + uint16_t _9492 = (uint16_t)(143); + _curvea0[303] = _9492; + uint16_t _9493 = (uint16_t)(143); + _curvea0[304] = _9493; + uint16_t _9494 = (uint16_t)(144); + _curvea0[305] = _9494; + uint16_t _9495 = (uint16_t)(144); + _curvea0[306] = _9495; + uint16_t _9496 = (uint16_t)(144); + _curvea0[307] = _9496; + uint16_t _9497 = (uint16_t)(145); + _curvea0[308] = _9497; + uint16_t _9498 = (uint16_t)(145); + _curvea0[309] = _9498; + uint16_t _9499 = (uint16_t)(145); + _curvea0[310] = _9499; + uint16_t _9500 = (uint16_t)(145); + _curvea0[311] = _9500; + uint16_t _9501 = (uint16_t)(146); + _curvea0[312] = _9501; + uint16_t _9502 = (uint16_t)(146); + _curvea0[313] = _9502; + uint16_t _9503 = (uint16_t)(146); + _curvea0[314] = _9503; + uint16_t _9504 = (uint16_t)(147); + _curvea0[315] = _9504; + uint16_t _9505 = (uint16_t)(147); + _curvea0[316] = _9505; + uint16_t _9506 = (uint16_t)(147); + _curvea0[317] = _9506; + uint16_t _9507 = (uint16_t)(148); + _curvea0[318] = _9507; + uint16_t _9508 = (uint16_t)(148); + _curvea0[319] = _9508; + uint16_t _9509 = (uint16_t)(148); + _curvea0[320] = _9509; + uint16_t _9510 = (uint16_t)(148); + _curvea0[321] = _9510; + uint16_t _9511 = (uint16_t)(149); + _curvea0[322] = _9511; + uint16_t _9512 = (uint16_t)(149); + _curvea0[323] = _9512; + uint16_t _9513 = (uint16_t)(149); + _curvea0[324] = _9513; + uint16_t _9514 = (uint16_t)(150); + _curvea0[325] = _9514; + uint16_t _9515 = (uint16_t)(150); + _curvea0[326] = _9515; + uint16_t _9516 = (uint16_t)(150); + _curvea0[327] = _9516; + uint16_t _9517 = (uint16_t)(150); + _curvea0[328] = _9517; + uint16_t _9518 = (uint16_t)(151); + _curvea0[329] = _9518; + uint16_t _9519 = (uint16_t)(151); + _curvea0[330] = _9519; + uint16_t _9520 = (uint16_t)(151); + _curvea0[331] = _9520; + uint16_t _9521 = (uint16_t)(152); + _curvea0[332] = _9521; + uint16_t _9522 = (uint16_t)(152); + _curvea0[333] = _9522; + uint16_t _9523 = (uint16_t)(152); + _curvea0[334] = _9523; + uint16_t _9524 = (uint16_t)(152); + _curvea0[335] = _9524; + uint16_t _9525 = (uint16_t)(153); + _curvea0[336] = _9525; + uint16_t _9526 = (uint16_t)(153); + _curvea0[337] = _9526; + uint16_t _9527 = (uint16_t)(153); + _curvea0[338] = _9527; + uint16_t _9528 = (uint16_t)(154); + _curvea0[339] = _9528; + uint16_t _9529 = (uint16_t)(154); + _curvea0[340] = _9529; + uint16_t _9530 = (uint16_t)(154); + _curvea0[341] = _9530; + uint16_t _9531 = (uint16_t)(154); + _curvea0[342] = _9531; + uint16_t _9532 = (uint16_t)(155); + _curvea0[343] = _9532; + uint16_t _9533 = (uint16_t)(155); + _curvea0[344] = _9533; + uint16_t _9534 = (uint16_t)(155); + _curvea0[345] = _9534; + uint16_t _9535 = (uint16_t)(156); + _curvea0[346] = _9535; + uint16_t _9536 = (uint16_t)(156); + _curvea0[347] = _9536; + uint16_t _9537 = (uint16_t)(156); + _curvea0[348] = _9537; + uint16_t _9538 = (uint16_t)(156); + _curvea0[349] = _9538; + uint16_t _9539 = (uint16_t)(157); + _curvea0[350] = _9539; + uint16_t _9540 = (uint16_t)(157); + _curvea0[351] = _9540; + uint16_t _9541 = (uint16_t)(157); + _curvea0[352] = _9541; + uint16_t _9542 = (uint16_t)(157); + _curvea0[353] = _9542; + uint16_t _9543 = (uint16_t)(158); + _curvea0[354] = _9543; + uint16_t _9544 = (uint16_t)(158); + _curvea0[355] = _9544; + uint16_t _9545 = (uint16_t)(158); + _curvea0[356] = _9545; + uint16_t _9546 = (uint16_t)(159); + _curvea0[357] = _9546; + uint16_t _9547 = (uint16_t)(159); + _curvea0[358] = _9547; + uint16_t _9548 = (uint16_t)(159); + _curvea0[359] = _9548; + uint16_t _9549 = (uint16_t)(159); + _curvea0[360] = _9549; + uint16_t _9550 = (uint16_t)(160); + _curvea0[361] = _9550; + uint16_t _9551 = (uint16_t)(160); + _curvea0[362] = _9551; + uint16_t _9552 = (uint16_t)(160); + _curvea0[363] = _9552; + uint16_t _9553 = (uint16_t)(160); + _curvea0[364] = _9553; + uint16_t _9554 = (uint16_t)(161); + _curvea0[365] = _9554; + uint16_t _9555 = (uint16_t)(161); + _curvea0[366] = _9555; + uint16_t _9556 = (uint16_t)(161); + _curvea0[367] = _9556; + uint16_t _9557 = (uint16_t)(161); + _curvea0[368] = _9557; + uint16_t _9558 = (uint16_t)(162); + _curvea0[369] = _9558; + uint16_t _9559 = (uint16_t)(162); + _curvea0[370] = _9559; + uint16_t _9560 = (uint16_t)(162); + _curvea0[371] = _9560; + uint16_t _9561 = (uint16_t)(162); + _curvea0[372] = _9561; + uint16_t _9562 = (uint16_t)(163); + _curvea0[373] = _9562; + uint16_t _9563 = (uint16_t)(163); + _curvea0[374] = _9563; + uint16_t _9564 = (uint16_t)(163); + _curvea0[375] = _9564; + uint16_t _9565 = (uint16_t)(163); + _curvea0[376] = _9565; + uint16_t _9566 = (uint16_t)(164); + _curvea0[377] = _9566; + uint16_t _9567 = (uint16_t)(164); + _curvea0[378] = _9567; + uint16_t _9568 = (uint16_t)(164); + _curvea0[379] = _9568; + uint16_t _9569 = (uint16_t)(164); + _curvea0[380] = _9569; + uint16_t _9570 = (uint16_t)(165); + _curvea0[381] = _9570; + uint16_t _9571 = (uint16_t)(165); + _curvea0[382] = _9571; + uint16_t _9572 = (uint16_t)(165); + _curvea0[383] = _9572; + uint16_t _9573 = (uint16_t)(166); + _curvea0[384] = _9573; + uint16_t _9574 = (uint16_t)(166); + _curvea0[385] = _9574; + uint16_t _9575 = (uint16_t)(166); + _curvea0[386] = _9575; + uint16_t _9576 = (uint16_t)(166); + _curvea0[387] = _9576; + uint16_t _9577 = (uint16_t)(167); + _curvea0[388] = _9577; + uint16_t _9578 = (uint16_t)(167); + _curvea0[389] = _9578; + uint16_t _9579 = (uint16_t)(167); + _curvea0[390] = _9579; + uint16_t _9580 = (uint16_t)(167); + _curvea0[391] = _9580; + uint16_t _9581 = (uint16_t)(167); + _curvea0[392] = _9581; + uint16_t _9582 = (uint16_t)(168); + _curvea0[393] = _9582; + uint16_t _9583 = (uint16_t)(168); + _curvea0[394] = _9583; + uint16_t _9584 = (uint16_t)(168); + _curvea0[395] = _9584; + uint16_t _9585 = (uint16_t)(168); + _curvea0[396] = _9585; + uint16_t _9586 = (uint16_t)(169); + _curvea0[397] = _9586; + uint16_t _9587 = (uint16_t)(169); + _curvea0[398] = _9587; + uint16_t _9588 = (uint16_t)(169); + _curvea0[399] = _9588; + uint16_t _9589 = (uint16_t)(169); + _curvea0[400] = _9589; + uint16_t _9590 = (uint16_t)(170); + _curvea0[401] = _9590; + uint16_t _9591 = (uint16_t)(170); + _curvea0[402] = _9591; + uint16_t _9592 = (uint16_t)(170); + _curvea0[403] = _9592; + uint16_t _9593 = (uint16_t)(170); + _curvea0[404] = _9593; + uint16_t _9594 = (uint16_t)(171); + _curvea0[405] = _9594; + uint16_t _9595 = (uint16_t)(171); + _curvea0[406] = _9595; + uint16_t _9596 = (uint16_t)(171); + _curvea0[407] = _9596; + uint16_t _9597 = (uint16_t)(171); + _curvea0[408] = _9597; + uint16_t _9598 = (uint16_t)(172); + _curvea0[409] = _9598; + uint16_t _9599 = (uint16_t)(172); + _curvea0[410] = _9599; + uint16_t _9600 = (uint16_t)(172); + _curvea0[411] = _9600; + uint16_t _9601 = (uint16_t)(172); + _curvea0[412] = _9601; + uint16_t _9602 = (uint16_t)(173); + _curvea0[413] = _9602; + uint16_t _9603 = (uint16_t)(173); + _curvea0[414] = _9603; + uint16_t _9604 = (uint16_t)(173); + _curvea0[415] = _9604; + uint16_t _9605 = (uint16_t)(173); + _curvea0[416] = _9605; + uint16_t _9606 = (uint16_t)(173); + _curvea0[417] = _9606; + uint16_t _9607 = (uint16_t)(174); + _curvea0[418] = _9607; + uint16_t _9608 = (uint16_t)(174); + _curvea0[419] = _9608; + uint16_t _9609 = (uint16_t)(174); + _curvea0[420] = _9609; + uint16_t _9610 = (uint16_t)(174); + _curvea0[421] = _9610; + uint16_t _9611 = (uint16_t)(175); + _curvea0[422] = _9611; + uint16_t _9612 = (uint16_t)(175); + _curvea0[423] = _9612; + uint16_t _9613 = (uint16_t)(175); + _curvea0[424] = _9613; + uint16_t _9614 = (uint16_t)(175); + _curvea0[425] = _9614; + uint16_t _9615 = (uint16_t)(176); + _curvea0[426] = _9615; + uint16_t _9616 = (uint16_t)(176); + _curvea0[427] = _9616; + uint16_t _9617 = (uint16_t)(176); + _curvea0[428] = _9617; + uint16_t _9618 = (uint16_t)(176); + _curvea0[429] = _9618; + uint16_t _9619 = (uint16_t)(176); + _curvea0[430] = _9619; + uint16_t _9620 = (uint16_t)(177); + _curvea0[431] = _9620; + uint16_t _9621 = (uint16_t)(177); + _curvea0[432] = _9621; + uint16_t _9622 = (uint16_t)(177); + _curvea0[433] = _9622; + uint16_t _9623 = (uint16_t)(177); + _curvea0[434] = _9623; + uint16_t _9624 = (uint16_t)(178); + _curvea0[435] = _9624; + uint16_t _9625 = (uint16_t)(178); + _curvea0[436] = _9625; + uint16_t _9626 = (uint16_t)(178); + _curvea0[437] = _9626; + uint16_t _9627 = (uint16_t)(178); + _curvea0[438] = _9627; + uint16_t _9628 = (uint16_t)(178); + _curvea0[439] = _9628; + uint16_t _9629 = (uint16_t)(179); + _curvea0[440] = _9629; + uint16_t _9630 = (uint16_t)(179); + _curvea0[441] = _9630; + uint16_t _9631 = (uint16_t)(179); + _curvea0[442] = _9631; + uint16_t _9632 = (uint16_t)(179); + _curvea0[443] = _9632; + uint16_t _9633 = (uint16_t)(180); + _curvea0[444] = _9633; + uint16_t _9634 = (uint16_t)(180); + _curvea0[445] = _9634; + uint16_t _9635 = (uint16_t)(180); + _curvea0[446] = _9635; + uint16_t _9636 = (uint16_t)(180); + _curvea0[447] = _9636; + uint16_t _9637 = (uint16_t)(180); + _curvea0[448] = _9637; + uint16_t _9638 = (uint16_t)(181); + _curvea0[449] = _9638; + uint16_t _9639 = (uint16_t)(181); + _curvea0[450] = _9639; + uint16_t _9640 = (uint16_t)(181); + _curvea0[451] = _9640; + uint16_t _9641 = (uint16_t)(181); + _curvea0[452] = _9641; + uint16_t _9642 = (uint16_t)(181); + _curvea0[453] = _9642; + uint16_t _9643 = (uint16_t)(182); + _curvea0[454] = _9643; + uint16_t _9644 = (uint16_t)(182); + _curvea0[455] = _9644; + uint16_t _9645 = (uint16_t)(182); + _curvea0[456] = _9645; + uint16_t _9646 = (uint16_t)(182); + _curvea0[457] = _9646; + uint16_t _9647 = (uint16_t)(183); + _curvea0[458] = _9647; + uint16_t _9648 = (uint16_t)(183); + _curvea0[459] = _9648; + uint16_t _9649 = (uint16_t)(183); + _curvea0[460] = _9649; + uint16_t _9650 = (uint16_t)(183); + _curvea0[461] = _9650; + uint16_t _9651 = (uint16_t)(183); + _curvea0[462] = _9651; + uint16_t _9652 = (uint16_t)(184); + _curvea0[463] = _9652; + uint16_t _9653 = (uint16_t)(184); + _curvea0[464] = _9653; + uint16_t _9654 = (uint16_t)(184); + _curvea0[465] = _9654; + uint16_t _9655 = (uint16_t)(184); + _curvea0[466] = _9655; + uint16_t _9656 = (uint16_t)(184); + _curvea0[467] = _9656; + uint16_t _9657 = (uint16_t)(185); + _curvea0[468] = _9657; + uint16_t _9658 = (uint16_t)(185); + _curvea0[469] = _9658; + uint16_t _9659 = (uint16_t)(185); + _curvea0[470] = _9659; + uint16_t _9660 = (uint16_t)(185); + _curvea0[471] = _9660; + uint16_t _9661 = (uint16_t)(185); + _curvea0[472] = _9661; + uint16_t _9662 = (uint16_t)(186); + _curvea0[473] = _9662; + uint16_t _9663 = (uint16_t)(186); + _curvea0[474] = _9663; + uint16_t _9664 = (uint16_t)(186); + _curvea0[475] = _9664; + uint16_t _9665 = (uint16_t)(186); + _curvea0[476] = _9665; + uint16_t _9666 = (uint16_t)(187); + _curvea0[477] = _9666; + uint16_t _9667 = (uint16_t)(187); + _curvea0[478] = _9667; + uint16_t _9668 = (uint16_t)(187); + _curvea0[479] = _9668; + uint16_t _9669 = (uint16_t)(187); + _curvea0[480] = _9669; + uint16_t _9670 = (uint16_t)(187); + _curvea0[481] = _9670; + uint16_t _9671 = (uint16_t)(188); + _curvea0[482] = _9671; + uint16_t _9672 = (uint16_t)(188); + _curvea0[483] = _9672; + uint16_t _9673 = (uint16_t)(188); + _curvea0[484] = _9673; + uint16_t _9674 = (uint16_t)(188); + _curvea0[485] = _9674; + uint16_t _9675 = (uint16_t)(188); + _curvea0[486] = _9675; + uint16_t _9676 = (uint16_t)(189); + _curvea0[487] = _9676; + uint16_t _9677 = (uint16_t)(189); + _curvea0[488] = _9677; + uint16_t _9678 = (uint16_t)(189); + _curvea0[489] = _9678; + uint16_t _9679 = (uint16_t)(189); + _curvea0[490] = _9679; + uint16_t _9680 = (uint16_t)(189); + _curvea0[491] = _9680; + uint16_t _9681 = (uint16_t)(190); + _curvea0[492] = _9681; + uint16_t _9682 = (uint16_t)(190); + _curvea0[493] = _9682; + uint16_t _9683 = (uint16_t)(190); + _curvea0[494] = _9683; + uint16_t _9684 = (uint16_t)(190); + _curvea0[495] = _9684; + uint16_t _9685 = (uint16_t)(190); + _curvea0[496] = _9685; + uint16_t _9686 = (uint16_t)(190); + _curvea0[497] = _9686; + uint16_t _9687 = (uint16_t)(191); + _curvea0[498] = _9687; + uint16_t _9688 = (uint16_t)(191); + _curvea0[499] = _9688; + uint16_t _9689 = (uint16_t)(191); + _curvea0[500] = _9689; + uint16_t _9690 = (uint16_t)(191); + _curvea0[501] = _9690; + uint16_t _9691 = (uint16_t)(191); + _curvea0[502] = _9691; + uint16_t _9692 = (uint16_t)(192); + _curvea0[503] = _9692; + uint16_t _9693 = (uint16_t)(192); + _curvea0[504] = _9693; + uint16_t _9694 = (uint16_t)(192); + _curvea0[505] = _9694; + uint16_t _9695 = (uint16_t)(192); + _curvea0[506] = _9695; + uint16_t _9696 = (uint16_t)(192); + _curvea0[507] = _9696; + uint16_t _9697 = (uint16_t)(193); + _curvea0[508] = _9697; + uint16_t _9698 = (uint16_t)(193); + _curvea0[509] = _9698; + uint16_t _9699 = (uint16_t)(193); + _curvea0[510] = _9699; + uint16_t _9700 = (uint16_t)(193); + _curvea0[511] = _9700; + uint16_t _9701 = (uint16_t)(193); + _curvea0[512] = _9701; + uint16_t _9702 = (uint16_t)(194); + _curvea0[513] = _9702; + uint16_t _9703 = (uint16_t)(194); + _curvea0[514] = _9703; + uint16_t _9704 = (uint16_t)(194); + _curvea0[515] = _9704; + uint16_t _9705 = (uint16_t)(194); + _curvea0[516] = _9705; + uint16_t _9706 = (uint16_t)(194); + _curvea0[517] = _9706; + uint16_t _9707 = (uint16_t)(195); + _curvea0[518] = _9707; + uint16_t _9708 = (uint16_t)(195); + _curvea0[519] = _9708; + uint16_t _9709 = (uint16_t)(195); + _curvea0[520] = _9709; + uint16_t _9710 = (uint16_t)(195); + _curvea0[521] = _9710; + uint16_t _9711 = (uint16_t)(195); + _curvea0[522] = _9711; + uint16_t _9712 = (uint16_t)(195); + _curvea0[523] = _9712; + uint16_t _9713 = (uint16_t)(196); + _curvea0[524] = _9713; + uint16_t _9714 = (uint16_t)(196); + _curvea0[525] = _9714; + uint16_t _9715 = (uint16_t)(196); + _curvea0[526] = _9715; + uint16_t _9716 = (uint16_t)(196); + _curvea0[527] = _9716; + uint16_t _9717 = (uint16_t)(196); + _curvea0[528] = _9717; + uint16_t _9718 = (uint16_t)(197); + _curvea0[529] = _9718; + uint16_t _9719 = (uint16_t)(197); + _curvea0[530] = _9719; + uint16_t _9720 = (uint16_t)(197); + _curvea0[531] = _9720; + uint16_t _9721 = (uint16_t)(197); + _curvea0[532] = _9721; + uint16_t _9722 = (uint16_t)(197); + _curvea0[533] = _9722; + uint16_t _9723 = (uint16_t)(197); + _curvea0[534] = _9723; + uint16_t _9724 = (uint16_t)(198); + _curvea0[535] = _9724; + uint16_t _9725 = (uint16_t)(198); + _curvea0[536] = _9725; + uint16_t _9726 = (uint16_t)(198); + _curvea0[537] = _9726; + uint16_t _9727 = (uint16_t)(198); + _curvea0[538] = _9727; + uint16_t _9728 = (uint16_t)(198); + _curvea0[539] = _9728; + uint16_t _9729 = (uint16_t)(199); + _curvea0[540] = _9729; + uint16_t _9730 = (uint16_t)(199); + _curvea0[541] = _9730; + uint16_t _9731 = (uint16_t)(199); + _curvea0[542] = _9731; + uint16_t _9732 = (uint16_t)(199); + _curvea0[543] = _9732; + uint16_t _9733 = (uint16_t)(199); + _curvea0[544] = _9733; + uint16_t _9734 = (uint16_t)(199); + _curvea0[545] = _9734; + uint16_t _9735 = (uint16_t)(200); + _curvea0[546] = _9735; + uint16_t _9736 = (uint16_t)(200); + _curvea0[547] = _9736; + uint16_t _9737 = (uint16_t)(200); + _curvea0[548] = _9737; + uint16_t _9738 = (uint16_t)(200); + _curvea0[549] = _9738; + uint16_t _9739 = (uint16_t)(200); + _curvea0[550] = _9739; + uint16_t _9740 = (uint16_t)(200); + _curvea0[551] = _9740; + uint16_t _9741 = (uint16_t)(201); + _curvea0[552] = _9741; + uint16_t _9742 = (uint16_t)(201); + _curvea0[553] = _9742; + uint16_t _9743 = (uint16_t)(201); + _curvea0[554] = _9743; + uint16_t _9744 = (uint16_t)(201); + _curvea0[555] = _9744; + uint16_t _9745 = (uint16_t)(201); + _curvea0[556] = _9745; + uint16_t _9746 = (uint16_t)(202); + _curvea0[557] = _9746; + uint16_t _9747 = (uint16_t)(202); + _curvea0[558] = _9747; + uint16_t _9748 = (uint16_t)(202); + _curvea0[559] = _9748; + uint16_t _9749 = (uint16_t)(202); + _curvea0[560] = _9749; + uint16_t _9750 = (uint16_t)(202); + _curvea0[561] = _9750; + uint16_t _9751 = (uint16_t)(202); + _curvea0[562] = _9751; + uint16_t _9752 = (uint16_t)(203); + _curvea0[563] = _9752; + uint16_t _9753 = (uint16_t)(203); + _curvea0[564] = _9753; + uint16_t _9754 = (uint16_t)(203); + _curvea0[565] = _9754; + uint16_t _9755 = (uint16_t)(203); + _curvea0[566] = _9755; + uint16_t _9756 = (uint16_t)(203); + _curvea0[567] = _9756; + uint16_t _9757 = (uint16_t)(203); + _curvea0[568] = _9757; + uint16_t _9758 = (uint16_t)(204); + _curvea0[569] = _9758; + uint16_t _9759 = (uint16_t)(204); + _curvea0[570] = _9759; + uint16_t _9760 = (uint16_t)(204); + _curvea0[571] = _9760; + uint16_t _9761 = (uint16_t)(204); + _curvea0[572] = _9761; + uint16_t _9762 = (uint16_t)(204); + _curvea0[573] = _9762; + uint16_t _9763 = (uint16_t)(204); + _curvea0[574] = _9763; + uint16_t _9764 = (uint16_t)(205); + _curvea0[575] = _9764; + uint16_t _9765 = (uint16_t)(205); + _curvea0[576] = _9765; + uint16_t _9766 = (uint16_t)(205); + _curvea0[577] = _9766; + uint16_t _9767 = (uint16_t)(205); + _curvea0[578] = _9767; + uint16_t _9768 = (uint16_t)(205); + _curvea0[579] = _9768; + uint16_t _9769 = (uint16_t)(205); + _curvea0[580] = _9769; + uint16_t _9770 = (uint16_t)(206); + _curvea0[581] = _9770; + uint16_t _9771 = (uint16_t)(206); + _curvea0[582] = _9771; + uint16_t _9772 = (uint16_t)(206); + _curvea0[583] = _9772; + uint16_t _9773 = (uint16_t)(206); + _curvea0[584] = _9773; + uint16_t _9774 = (uint16_t)(206); + _curvea0[585] = _9774; + uint16_t _9775 = (uint16_t)(206); + _curvea0[586] = _9775; + uint16_t _9776 = (uint16_t)(207); + _curvea0[587] = _9776; + uint16_t _9777 = (uint16_t)(207); + _curvea0[588] = _9777; + uint16_t _9778 = (uint16_t)(207); + _curvea0[589] = _9778; + uint16_t _9779 = (uint16_t)(207); + _curvea0[590] = _9779; + uint16_t _9780 = (uint16_t)(207); + _curvea0[591] = _9780; + uint16_t _9781 = (uint16_t)(207); + _curvea0[592] = _9781; + uint16_t _9782 = (uint16_t)(208); + _curvea0[593] = _9782; + uint16_t _9783 = (uint16_t)(208); + _curvea0[594] = _9783; + uint16_t _9784 = (uint16_t)(208); + _curvea0[595] = _9784; + uint16_t _9785 = (uint16_t)(208); + _curvea0[596] = _9785; + uint16_t _9786 = (uint16_t)(208); + _curvea0[597] = _9786; + uint16_t _9787 = (uint16_t)(208); + _curvea0[598] = _9787; + uint16_t _9788 = (uint16_t)(209); + _curvea0[599] = _9788; + uint16_t _9789 = (uint16_t)(209); + _curvea0[600] = _9789; + uint16_t _9790 = (uint16_t)(209); + _curvea0[601] = _9790; + uint16_t _9791 = (uint16_t)(209); + _curvea0[602] = _9791; + uint16_t _9792 = (uint16_t)(209); + _curvea0[603] = _9792; + uint16_t _9793 = (uint16_t)(209); + _curvea0[604] = _9793; + uint16_t _9794 = (uint16_t)(209); + _curvea0[605] = _9794; + uint16_t _9795 = (uint16_t)(210); + _curvea0[606] = _9795; + uint16_t _9796 = (uint16_t)(210); + _curvea0[607] = _9796; + uint16_t _9797 = (uint16_t)(210); + _curvea0[608] = _9797; + uint16_t _9798 = (uint16_t)(210); + _curvea0[609] = _9798; + uint16_t _9799 = (uint16_t)(210); + _curvea0[610] = _9799; + uint16_t _9800 = (uint16_t)(210); + _curvea0[611] = _9800; + uint16_t _9801 = (uint16_t)(211); + _curvea0[612] = _9801; + uint16_t _9802 = (uint16_t)(211); + _curvea0[613] = _9802; + uint16_t _9803 = (uint16_t)(211); + _curvea0[614] = _9803; + uint16_t _9804 = (uint16_t)(211); + _curvea0[615] = _9804; + uint16_t _9805 = (uint16_t)(211); + _curvea0[616] = _9805; + uint16_t _9806 = (uint16_t)(211); + _curvea0[617] = _9806; + uint16_t _9807 = (uint16_t)(211); + _curvea0[618] = _9807; + uint16_t _9808 = (uint16_t)(212); + _curvea0[619] = _9808; + uint16_t _9809 = (uint16_t)(212); + _curvea0[620] = _9809; + uint16_t _9810 = (uint16_t)(212); + _curvea0[621] = _9810; + uint16_t _9811 = (uint16_t)(212); + _curvea0[622] = _9811; + uint16_t _9812 = (uint16_t)(212); + _curvea0[623] = _9812; + uint16_t _9813 = (uint16_t)(212); + _curvea0[624] = _9813; + uint16_t _9814 = (uint16_t)(213); + _curvea0[625] = _9814; + uint16_t _9815 = (uint16_t)(213); + _curvea0[626] = _9815; + uint16_t _9816 = (uint16_t)(213); + _curvea0[627] = _9816; + uint16_t _9817 = (uint16_t)(213); + _curvea0[628] = _9817; + uint16_t _9818 = (uint16_t)(213); + _curvea0[629] = _9818; + uint16_t _9819 = (uint16_t)(213); + _curvea0[630] = _9819; + uint16_t _9820 = (uint16_t)(213); + _curvea0[631] = _9820; + uint16_t _9821 = (uint16_t)(214); + _curvea0[632] = _9821; + uint16_t _9822 = (uint16_t)(214); + _curvea0[633] = _9822; + uint16_t _9823 = (uint16_t)(214); + _curvea0[634] = _9823; + uint16_t _9824 = (uint16_t)(214); + _curvea0[635] = _9824; + uint16_t _9825 = (uint16_t)(214); + _curvea0[636] = _9825; + uint16_t _9826 = (uint16_t)(214); + _curvea0[637] = _9826; + uint16_t _9827 = (uint16_t)(214); + _curvea0[638] = _9827; + uint16_t _9828 = (uint16_t)(215); + _curvea0[639] = _9828; + uint16_t _9829 = (uint16_t)(215); + _curvea0[640] = _9829; + uint16_t _9830 = (uint16_t)(215); + _curvea0[641] = _9830; + uint16_t _9831 = (uint16_t)(215); + _curvea0[642] = _9831; + uint16_t _9832 = (uint16_t)(215); + _curvea0[643] = _9832; + uint16_t _9833 = (uint16_t)(215); + _curvea0[644] = _9833; + uint16_t _9834 = (uint16_t)(216); + _curvea0[645] = _9834; + uint16_t _9835 = (uint16_t)(216); + _curvea0[646] = _9835; + uint16_t _9836 = (uint16_t)(216); + _curvea0[647] = _9836; + uint16_t _9837 = (uint16_t)(216); + _curvea0[648] = _9837; + uint16_t _9838 = (uint16_t)(216); + _curvea0[649] = _9838; + uint16_t _9839 = (uint16_t)(216); + _curvea0[650] = _9839; + uint16_t _9840 = (uint16_t)(216); + _curvea0[651] = _9840; + uint16_t _9841 = (uint16_t)(217); + _curvea0[652] = _9841; + uint16_t _9842 = (uint16_t)(217); + _curvea0[653] = _9842; + uint16_t _9843 = (uint16_t)(217); + _curvea0[654] = _9843; + uint16_t _9844 = (uint16_t)(217); + _curvea0[655] = _9844; + uint16_t _9845 = (uint16_t)(217); + _curvea0[656] = _9845; + uint16_t _9846 = (uint16_t)(217); + _curvea0[657] = _9846; + uint16_t _9847 = (uint16_t)(217); + _curvea0[658] = _9847; + uint16_t _9848 = (uint16_t)(218); + _curvea0[659] = _9848; + uint16_t _9849 = (uint16_t)(218); + _curvea0[660] = _9849; + uint16_t _9850 = (uint16_t)(218); + _curvea0[661] = _9850; + uint16_t _9851 = (uint16_t)(218); + _curvea0[662] = _9851; + uint16_t _9852 = (uint16_t)(218); + _curvea0[663] = _9852; + uint16_t _9853 = (uint16_t)(218); + _curvea0[664] = _9853; + uint16_t _9854 = (uint16_t)(218); + _curvea0[665] = _9854; + uint16_t _9855 = (uint16_t)(219); + _curvea0[666] = _9855; + uint16_t _9856 = (uint16_t)(219); + _curvea0[667] = _9856; + uint16_t _9857 = (uint16_t)(219); + _curvea0[668] = _9857; + uint16_t _9858 = (uint16_t)(219); + _curvea0[669] = _9858; + uint16_t _9859 = (uint16_t)(219); + _curvea0[670] = _9859; + uint16_t _9860 = (uint16_t)(219); + _curvea0[671] = _9860; + uint16_t _9861 = (uint16_t)(219); + _curvea0[672] = _9861; + uint16_t _9862 = (uint16_t)(220); + _curvea0[673] = _9862; + uint16_t _9863 = (uint16_t)(220); + _curvea0[674] = _9863; + uint16_t _9864 = (uint16_t)(220); + _curvea0[675] = _9864; + uint16_t _9865 = (uint16_t)(220); + _curvea0[676] = _9865; + uint16_t _9866 = (uint16_t)(220); + _curvea0[677] = _9866; + uint16_t _9867 = (uint16_t)(220); + _curvea0[678] = _9867; + uint16_t _9868 = (uint16_t)(220); + _curvea0[679] = _9868; + uint16_t _9869 = (uint16_t)(220); + _curvea0[680] = _9869; + uint16_t _9870 = (uint16_t)(221); + _curvea0[681] = _9870; + uint16_t _9871 = (uint16_t)(221); + _curvea0[682] = _9871; + uint16_t _9872 = (uint16_t)(221); + _curvea0[683] = _9872; + uint16_t _9873 = (uint16_t)(221); + _curvea0[684] = _9873; + uint16_t _9874 = (uint16_t)(221); + _curvea0[685] = _9874; + uint16_t _9875 = (uint16_t)(221); + _curvea0[686] = _9875; + uint16_t _9876 = (uint16_t)(221); + _curvea0[687] = _9876; + uint16_t _9877 = (uint16_t)(222); + _curvea0[688] = _9877; + uint16_t _9878 = (uint16_t)(222); + _curvea0[689] = _9878; + uint16_t _9879 = (uint16_t)(222); + _curvea0[690] = _9879; + uint16_t _9880 = (uint16_t)(222); + _curvea0[691] = _9880; + uint16_t _9881 = (uint16_t)(222); + _curvea0[692] = _9881; + uint16_t _9882 = (uint16_t)(222); + _curvea0[693] = _9882; + uint16_t _9883 = (uint16_t)(222); + _curvea0[694] = _9883; + uint16_t _9884 = (uint16_t)(223); + _curvea0[695] = _9884; + uint16_t _9885 = (uint16_t)(223); + _curvea0[696] = _9885; + uint16_t _9886 = (uint16_t)(223); + _curvea0[697] = _9886; + uint16_t _9887 = (uint16_t)(223); + _curvea0[698] = _9887; + uint16_t _9888 = (uint16_t)(223); + _curvea0[699] = _9888; + uint16_t _9889 = (uint16_t)(223); + _curvea0[700] = _9889; + uint16_t _9890 = (uint16_t)(223); + _curvea0[701] = _9890; + uint16_t _9891 = (uint16_t)(223); + _curvea0[702] = _9891; + uint16_t _9892 = (uint16_t)(224); + _curvea0[703] = _9892; + uint16_t _9893 = (uint16_t)(224); + _curvea0[704] = _9893; + uint16_t _9894 = (uint16_t)(224); + _curvea0[705] = _9894; + uint16_t _9895 = (uint16_t)(224); + _curvea0[706] = _9895; + uint16_t _9896 = (uint16_t)(224); + _curvea0[707] = _9896; + uint16_t _9897 = (uint16_t)(224); + _curvea0[708] = _9897; + uint16_t _9898 = (uint16_t)(224); + _curvea0[709] = _9898; + uint16_t _9899 = (uint16_t)(224); + _curvea0[710] = _9899; + uint16_t _9900 = (uint16_t)(225); + _curvea0[711] = _9900; + uint16_t _9901 = (uint16_t)(225); + _curvea0[712] = _9901; + uint16_t _9902 = (uint16_t)(225); + _curvea0[713] = _9902; + uint16_t _9903 = (uint16_t)(225); + _curvea0[714] = _9903; + uint16_t _9904 = (uint16_t)(225); + _curvea0[715] = _9904; + uint16_t _9905 = (uint16_t)(225); + _curvea0[716] = _9905; + uint16_t _9906 = (uint16_t)(225); + _curvea0[717] = _9906; + uint16_t _9907 = (uint16_t)(226); + _curvea0[718] = _9907; + uint16_t _9908 = (uint16_t)(226); + _curvea0[719] = _9908; + uint16_t _9909 = (uint16_t)(226); + _curvea0[720] = _9909; + uint16_t _9910 = (uint16_t)(226); + _curvea0[721] = _9910; + uint16_t _9911 = (uint16_t)(226); + _curvea0[722] = _9911; + uint16_t _9912 = (uint16_t)(226); + _curvea0[723] = _9912; + uint16_t _9913 = (uint16_t)(226); + _curvea0[724] = _9913; + uint16_t _9914 = (uint16_t)(226); + _curvea0[725] = _9914; + uint16_t _9915 = (uint16_t)(227); + _curvea0[726] = _9915; + uint16_t _9916 = (uint16_t)(227); + _curvea0[727] = _9916; + uint16_t _9917 = (uint16_t)(227); + _curvea0[728] = _9917; + uint16_t _9918 = (uint16_t)(227); + _curvea0[729] = _9918; + uint16_t _9919 = (uint16_t)(227); + _curvea0[730] = _9919; + uint16_t _9920 = (uint16_t)(227); + _curvea0[731] = _9920; + uint16_t _9921 = (uint16_t)(227); + _curvea0[732] = _9921; + uint16_t _9922 = (uint16_t)(227); + _curvea0[733] = _9922; + uint16_t _9923 = (uint16_t)(228); + _curvea0[734] = _9923; + uint16_t _9924 = (uint16_t)(228); + _curvea0[735] = _9924; + uint16_t _9925 = (uint16_t)(228); + _curvea0[736] = _9925; + uint16_t _9926 = (uint16_t)(228); + _curvea0[737] = _9926; + uint16_t _9927 = (uint16_t)(228); + _curvea0[738] = _9927; + uint16_t _9928 = (uint16_t)(228); + _curvea0[739] = _9928; + uint16_t _9929 = (uint16_t)(228); + _curvea0[740] = _9929; + uint16_t _9930 = (uint16_t)(228); + _curvea0[741] = _9930; + uint16_t _9931 = (uint16_t)(228); + _curvea0[742] = _9931; + uint16_t _9932 = (uint16_t)(229); + _curvea0[743] = _9932; + uint16_t _9933 = (uint16_t)(229); + _curvea0[744] = _9933; + uint16_t _9934 = (uint16_t)(229); + _curvea0[745] = _9934; + uint16_t _9935 = (uint16_t)(229); + _curvea0[746] = _9935; + uint16_t _9936 = (uint16_t)(229); + _curvea0[747] = _9936; + uint16_t _9937 = (uint16_t)(229); + _curvea0[748] = _9937; + uint16_t _9938 = (uint16_t)(229); + _curvea0[749] = _9938; + uint16_t _9939 = (uint16_t)(229); + _curvea0[750] = _9939; + uint16_t _9940 = (uint16_t)(230); + _curvea0[751] = _9940; + uint16_t _9941 = (uint16_t)(230); + _curvea0[752] = _9941; + uint16_t _9942 = (uint16_t)(230); + _curvea0[753] = _9942; + uint16_t _9943 = (uint16_t)(230); + _curvea0[754] = _9943; + uint16_t _9944 = (uint16_t)(230); + _curvea0[755] = _9944; + uint16_t _9945 = (uint16_t)(230); + _curvea0[756] = _9945; + uint16_t _9946 = (uint16_t)(230); + _curvea0[757] = _9946; + uint16_t _9947 = (uint16_t)(230); + _curvea0[758] = _9947; + uint16_t _9948 = (uint16_t)(231); + _curvea0[759] = _9948; + uint16_t _9949 = (uint16_t)(231); + _curvea0[760] = _9949; + uint16_t _9950 = (uint16_t)(231); + _curvea0[761] = _9950; + uint16_t _9951 = (uint16_t)(231); + _curvea0[762] = _9951; + uint16_t _9952 = (uint16_t)(231); + _curvea0[763] = _9952; + uint16_t _9953 = (uint16_t)(231); + _curvea0[764] = _9953; + uint16_t _9954 = (uint16_t)(231); + _curvea0[765] = _9954; + uint16_t _9955 = (uint16_t)(231); + _curvea0[766] = _9955; + uint16_t _9956 = (uint16_t)(231); + _curvea0[767] = _9956; + uint16_t _9957 = (uint16_t)(232); + _curvea0[768] = _9957; + uint16_t _9958 = (uint16_t)(232); + _curvea0[769] = _9958; + uint16_t _9959 = (uint16_t)(232); + _curvea0[770] = _9959; + uint16_t _9960 = (uint16_t)(232); + _curvea0[771] = _9960; + uint16_t _9961 = (uint16_t)(232); + _curvea0[772] = _9961; + uint16_t _9962 = (uint16_t)(232); + _curvea0[773] = _9962; + uint16_t _9963 = (uint16_t)(232); + _curvea0[774] = _9963; + uint16_t _9964 = (uint16_t)(232); + _curvea0[775] = _9964; + uint16_t _9965 = (uint16_t)(233); + _curvea0[776] = _9965; + uint16_t _9966 = (uint16_t)(233); + _curvea0[777] = _9966; + uint16_t _9967 = (uint16_t)(233); + _curvea0[778] = _9967; + uint16_t _9968 = (uint16_t)(233); + _curvea0[779] = _9968; + uint16_t _9969 = (uint16_t)(233); + _curvea0[780] = _9969; + uint16_t _9970 = (uint16_t)(233); + _curvea0[781] = _9970; + uint16_t _9971 = (uint16_t)(233); + _curvea0[782] = _9971; + uint16_t _9972 = (uint16_t)(233); + _curvea0[783] = _9972; + uint16_t _9973 = (uint16_t)(233); + _curvea0[784] = _9973; + uint16_t _9974 = (uint16_t)(234); + _curvea0[785] = _9974; + uint16_t _9975 = (uint16_t)(234); + _curvea0[786] = _9975; + uint16_t _9976 = (uint16_t)(234); + _curvea0[787] = _9976; + uint16_t _9977 = (uint16_t)(234); + _curvea0[788] = _9977; + uint16_t _9978 = (uint16_t)(234); + _curvea0[789] = _9978; + uint16_t _9979 = (uint16_t)(234); + _curvea0[790] = _9979; + uint16_t _9980 = (uint16_t)(234); + _curvea0[791] = _9980; + uint16_t _9981 = (uint16_t)(234); + _curvea0[792] = _9981; + uint16_t _9982 = (uint16_t)(234); + _curvea0[793] = _9982; + uint16_t _9983 = (uint16_t)(235); + _curvea0[794] = _9983; + uint16_t _9984 = (uint16_t)(235); + _curvea0[795] = _9984; + uint16_t _9985 = (uint16_t)(235); + _curvea0[796] = _9985; + uint16_t _9986 = (uint16_t)(235); + _curvea0[797] = _9986; + uint16_t _9987 = (uint16_t)(235); + _curvea0[798] = _9987; + uint16_t _9988 = (uint16_t)(235); + _curvea0[799] = _9988; + uint16_t _9989 = (uint16_t)(235); + _curvea0[800] = _9989; + uint16_t _9990 = (uint16_t)(235); + _curvea0[801] = _9990; + uint16_t _9991 = (uint16_t)(235); + _curvea0[802] = _9991; + uint16_t _9992 = (uint16_t)(236); + _curvea0[803] = _9992; + uint16_t _9993 = (uint16_t)(236); + _curvea0[804] = _9993; + uint16_t _9994 = (uint16_t)(236); + _curvea0[805] = _9994; + uint16_t _9995 = (uint16_t)(236); + _curvea0[806] = _9995; + uint16_t _9996 = (uint16_t)(236); + _curvea0[807] = _9996; + uint16_t _9997 = (uint16_t)(236); + _curvea0[808] = _9997; + uint16_t _9998 = (uint16_t)(236); + _curvea0[809] = _9998; + uint16_t _9999 = (uint16_t)(236); + _curvea0[810] = _9999; + uint16_t _10000 = (uint16_t)(236); + _curvea0[811] = _10000; + uint16_t _10001 = (uint16_t)(237); + _curvea0[812] = _10001; + uint16_t _10002 = (uint16_t)(237); + _curvea0[813] = _10002; + uint16_t _10003 = (uint16_t)(237); + _curvea0[814] = _10003; + uint16_t _10004 = (uint16_t)(237); + _curvea0[815] = _10004; + uint16_t _10005 = (uint16_t)(237); + _curvea0[816] = _10005; + uint16_t _10006 = (uint16_t)(237); + _curvea0[817] = _10006; + uint16_t _10007 = (uint16_t)(237); + _curvea0[818] = _10007; + uint16_t _10008 = (uint16_t)(237); + _curvea0[819] = _10008; + uint16_t _10009 = (uint16_t)(237); + _curvea0[820] = _10009; + uint16_t _10010 = (uint16_t)(237); + _curvea0[821] = _10010; + uint16_t _10011 = (uint16_t)(238); + _curvea0[822] = _10011; + uint16_t _10012 = (uint16_t)(238); + _curvea0[823] = _10012; + uint16_t _10013 = (uint16_t)(238); + _curvea0[824] = _10013; + uint16_t _10014 = (uint16_t)(238); + _curvea0[825] = _10014; + uint16_t _10015 = (uint16_t)(238); + _curvea0[826] = _10015; + uint16_t _10016 = (uint16_t)(238); + _curvea0[827] = _10016; + uint16_t _10017 = (uint16_t)(238); + _curvea0[828] = _10017; + uint16_t _10018 = (uint16_t)(238); + _curvea0[829] = _10018; + uint16_t _10019 = (uint16_t)(238); + _curvea0[830] = _10019; + uint16_t _10020 = (uint16_t)(239); + _curvea0[831] = _10020; + uint16_t _10021 = (uint16_t)(239); + _curvea0[832] = _10021; + uint16_t _10022 = (uint16_t)(239); + _curvea0[833] = _10022; + uint16_t _10023 = (uint16_t)(239); + _curvea0[834] = _10023; + uint16_t _10024 = (uint16_t)(239); + _curvea0[835] = _10024; + uint16_t _10025 = (uint16_t)(239); + _curvea0[836] = _10025; + uint16_t _10026 = (uint16_t)(239); + _curvea0[837] = _10026; + uint16_t _10027 = (uint16_t)(239); + _curvea0[838] = _10027; + uint16_t _10028 = (uint16_t)(239); + _curvea0[839] = _10028; + uint16_t _10029 = (uint16_t)(239); + _curvea0[840] = _10029; + uint16_t _10030 = (uint16_t)(240); + _curvea0[841] = _10030; + uint16_t _10031 = (uint16_t)(240); + _curvea0[842] = _10031; + uint16_t _10032 = (uint16_t)(240); + _curvea0[843] = _10032; + uint16_t _10033 = (uint16_t)(240); + _curvea0[844] = _10033; + uint16_t _10034 = (uint16_t)(240); + _curvea0[845] = _10034; + uint16_t _10035 = (uint16_t)(240); + _curvea0[846] = _10035; + uint16_t _10036 = (uint16_t)(240); + _curvea0[847] = _10036; + uint16_t _10037 = (uint16_t)(240); + _curvea0[848] = _10037; + uint16_t _10038 = (uint16_t)(240); + _curvea0[849] = _10038; + uint16_t _10039 = (uint16_t)(240); + _curvea0[850] = _10039; + uint16_t _10040 = (uint16_t)(241); + _curvea0[851] = _10040; + uint16_t _10041 = (uint16_t)(241); + _curvea0[852] = _10041; + uint16_t _10042 = (uint16_t)(241); + _curvea0[853] = _10042; + uint16_t _10043 = (uint16_t)(241); + _curvea0[854] = _10043; + uint16_t _10044 = (uint16_t)(241); + _curvea0[855] = _10044; + uint16_t _10045 = (uint16_t)(241); + _curvea0[856] = _10045; + uint16_t _10046 = (uint16_t)(241); + _curvea0[857] = _10046; + uint16_t _10047 = (uint16_t)(241); + _curvea0[858] = _10047; + uint16_t _10048 = (uint16_t)(241); + _curvea0[859] = _10048; + uint16_t _10049 = (uint16_t)(241); + _curvea0[860] = _10049; + uint16_t _10050 = (uint16_t)(242); + _curvea0[861] = _10050; + uint16_t _10051 = (uint16_t)(242); + _curvea0[862] = _10051; + uint16_t _10052 = (uint16_t)(242); + _curvea0[863] = _10052; + uint16_t _10053 = (uint16_t)(242); + _curvea0[864] = _10053; + uint16_t _10054 = (uint16_t)(242); + _curvea0[865] = _10054; + uint16_t _10055 = (uint16_t)(242); + _curvea0[866] = _10055; + uint16_t _10056 = (uint16_t)(242); + _curvea0[867] = _10056; + uint16_t _10057 = (uint16_t)(242); + _curvea0[868] = _10057; + uint16_t _10058 = (uint16_t)(242); + _curvea0[869] = _10058; + uint16_t _10059 = (uint16_t)(242); + _curvea0[870] = _10059; + uint16_t _10060 = (uint16_t)(243); + _curvea0[871] = _10060; + uint16_t _10061 = (uint16_t)(243); + _curvea0[872] = _10061; + uint16_t _10062 = (uint16_t)(243); + _curvea0[873] = _10062; + uint16_t _10063 = (uint16_t)(243); + _curvea0[874] = _10063; + uint16_t _10064 = (uint16_t)(243); + _curvea0[875] = _10064; + uint16_t _10065 = (uint16_t)(243); + _curvea0[876] = _10065; + uint16_t _10066 = (uint16_t)(243); + _curvea0[877] = _10066; + uint16_t _10067 = (uint16_t)(243); + _curvea0[878] = _10067; + uint16_t _10068 = (uint16_t)(243); + _curvea0[879] = _10068; + uint16_t _10069 = (uint16_t)(243); + _curvea0[880] = _10069; + uint16_t _10070 = (uint16_t)(244); + _curvea0[881] = _10070; + uint16_t _10071 = (uint16_t)(244); + _curvea0[882] = _10071; + uint16_t _10072 = (uint16_t)(244); + _curvea0[883] = _10072; + uint16_t _10073 = (uint16_t)(244); + _curvea0[884] = _10073; + uint16_t _10074 = (uint16_t)(244); + _curvea0[885] = _10074; + uint16_t _10075 = (uint16_t)(244); + _curvea0[886] = _10075; + uint16_t _10076 = (uint16_t)(244); + _curvea0[887] = _10076; + uint16_t _10077 = (uint16_t)(244); + _curvea0[888] = _10077; + uint16_t _10078 = (uint16_t)(244); + _curvea0[889] = _10078; + uint16_t _10079 = (uint16_t)(244); + _curvea0[890] = _10079; + uint16_t _10080 = (uint16_t)(244); + _curvea0[891] = _10080; + uint16_t _10081 = (uint16_t)(245); + _curvea0[892] = _10081; + uint16_t _10082 = (uint16_t)(245); + _curvea0[893] = _10082; + uint16_t _10083 = (uint16_t)(245); + _curvea0[894] = _10083; + uint16_t _10084 = (uint16_t)(245); + _curvea0[895] = _10084; + uint16_t _10085 = (uint16_t)(245); + _curvea0[896] = _10085; + uint16_t _10086 = (uint16_t)(245); + _curvea0[897] = _10086; + uint16_t _10087 = (uint16_t)(245); + _curvea0[898] = _10087; + uint16_t _10088 = (uint16_t)(245); + _curvea0[899] = _10088; + uint16_t _10089 = (uint16_t)(245); + _curvea0[900] = _10089; + uint16_t _10090 = (uint16_t)(245); + _curvea0[901] = _10090; + uint16_t _10091 = (uint16_t)(245); + _curvea0[902] = _10091; + uint16_t _10092 = (uint16_t)(246); + _curvea0[903] = _10092; + uint16_t _10093 = (uint16_t)(246); + _curvea0[904] = _10093; + uint16_t _10094 = (uint16_t)(246); + _curvea0[905] = _10094; + uint16_t _10095 = (uint16_t)(246); + _curvea0[906] = _10095; + uint16_t _10096 = (uint16_t)(246); + _curvea0[907] = _10096; + uint16_t _10097 = (uint16_t)(246); + _curvea0[908] = _10097; + uint16_t _10098 = (uint16_t)(246); + _curvea0[909] = _10098; + uint16_t _10099 = (uint16_t)(246); + _curvea0[910] = _10099; + uint16_t _10100 = (uint16_t)(246); + _curvea0[911] = _10100; + uint16_t _10101 = (uint16_t)(246); + _curvea0[912] = _10101; + uint16_t _10102 = (uint16_t)(246); + _curvea0[913] = _10102; + uint16_t _10103 = (uint16_t)(247); + _curvea0[914] = _10103; + uint16_t _10104 = (uint16_t)(247); + _curvea0[915] = _10104; + uint16_t _10105 = (uint16_t)(247); + _curvea0[916] = _10105; + uint16_t _10106 = (uint16_t)(247); + _curvea0[917] = _10106; + uint16_t _10107 = (uint16_t)(247); + _curvea0[918] = _10107; + uint16_t _10108 = (uint16_t)(247); + _curvea0[919] = _10108; + uint16_t _10109 = (uint16_t)(247); + _curvea0[920] = _10109; + uint16_t _10110 = (uint16_t)(247); + _curvea0[921] = _10110; + uint16_t _10111 = (uint16_t)(247); + _curvea0[922] = _10111; + uint16_t _10112 = (uint16_t)(247); + _curvea0[923] = _10112; + uint16_t _10113 = (uint16_t)(247); + _curvea0[924] = _10113; + uint16_t _10114 = (uint16_t)(248); + _curvea0[925] = _10114; + uint16_t _10115 = (uint16_t)(248); + _curvea0[926] = _10115; + uint16_t _10116 = (uint16_t)(248); + _curvea0[927] = _10116; + uint16_t _10117 = (uint16_t)(248); + _curvea0[928] = _10117; + uint16_t _10118 = (uint16_t)(248); + _curvea0[929] = _10118; + uint16_t _10119 = (uint16_t)(248); + _curvea0[930] = _10119; + uint16_t _10120 = (uint16_t)(248); + _curvea0[931] = _10120; + uint16_t _10121 = (uint16_t)(248); + _curvea0[932] = _10121; + uint16_t _10122 = (uint16_t)(248); + _curvea0[933] = _10122; + uint16_t _10123 = (uint16_t)(248); + _curvea0[934] = _10123; + uint16_t _10124 = (uint16_t)(248); + _curvea0[935] = _10124; + uint16_t _10125 = (uint16_t)(249); + _curvea0[936] = _10125; + uint16_t _10126 = (uint16_t)(249); + _curvea0[937] = _10126; + uint16_t _10127 = (uint16_t)(249); + _curvea0[938] = _10127; + uint16_t _10128 = (uint16_t)(249); + _curvea0[939] = _10128; + uint16_t _10129 = (uint16_t)(249); + _curvea0[940] = _10129; + uint16_t _10130 = (uint16_t)(249); + _curvea0[941] = _10130; + uint16_t _10131 = (uint16_t)(249); + _curvea0[942] = _10131; + uint16_t _10132 = (uint16_t)(249); + _curvea0[943] = _10132; + uint16_t _10133 = (uint16_t)(249); + _curvea0[944] = _10133; + uint16_t _10134 = (uint16_t)(249); + _curvea0[945] = _10134; + uint16_t _10135 = (uint16_t)(249); + _curvea0[946] = _10135; + uint16_t _10136 = (uint16_t)(249); + _curvea0[947] = _10136; + uint16_t _10137 = (uint16_t)(250); + _curvea0[948] = _10137; + uint16_t _10138 = (uint16_t)(250); + _curvea0[949] = _10138; + uint16_t _10139 = (uint16_t)(250); + _curvea0[950] = _10139; + uint16_t _10140 = (uint16_t)(250); + _curvea0[951] = _10140; + uint16_t _10141 = (uint16_t)(250); + _curvea0[952] = _10141; + uint16_t _10142 = (uint16_t)(250); + _curvea0[953] = _10142; + uint16_t _10143 = (uint16_t)(250); + _curvea0[954] = _10143; + uint16_t _10144 = (uint16_t)(250); + _curvea0[955] = _10144; + uint16_t _10145 = (uint16_t)(250); + _curvea0[956] = _10145; + uint16_t _10146 = (uint16_t)(250); + _curvea0[957] = _10146; + uint16_t _10147 = (uint16_t)(250); + _curvea0[958] = _10147; + uint16_t _10148 = (uint16_t)(250); + _curvea0[959] = _10148; + uint16_t _10149 = (uint16_t)(251); + _curvea0[960] = _10149; + uint16_t _10150 = (uint16_t)(251); + _curvea0[961] = _10150; + uint16_t _10151 = (uint16_t)(251); + _curvea0[962] = _10151; + uint16_t _10152 = (uint16_t)(251); + _curvea0[963] = _10152; + uint16_t _10153 = (uint16_t)(251); + _curvea0[964] = _10153; + uint16_t _10154 = (uint16_t)(251); + _curvea0[965] = _10154; + uint16_t _10155 = (uint16_t)(251); + _curvea0[966] = _10155; + uint16_t _10156 = (uint16_t)(251); + _curvea0[967] = _10156; + uint16_t _10157 = (uint16_t)(251); + _curvea0[968] = _10157; + uint16_t _10158 = (uint16_t)(251); + _curvea0[969] = _10158; + uint16_t _10159 = (uint16_t)(251); + _curvea0[970] = _10159; + uint16_t _10160 = (uint16_t)(251); + _curvea0[971] = _10160; + uint16_t _10161 = (uint16_t)(252); + _curvea0[972] = _10161; + uint16_t _10162 = (uint16_t)(252); + _curvea0[973] = _10162; + uint16_t _10163 = (uint16_t)(252); + _curvea0[974] = _10163; + uint16_t _10164 = (uint16_t)(252); + _curvea0[975] = _10164; + uint16_t _10165 = (uint16_t)(252); + _curvea0[976] = _10165; + uint16_t _10166 = (uint16_t)(252); + _curvea0[977] = _10166; + uint16_t _10167 = (uint16_t)(252); + _curvea0[978] = _10167; + uint16_t _10168 = (uint16_t)(252); + _curvea0[979] = _10168; + uint16_t _10169 = (uint16_t)(252); + _curvea0[980] = _10169; + uint16_t _10170 = (uint16_t)(252); + _curvea0[981] = _10170; + uint16_t _10171 = (uint16_t)(252); + _curvea0[982] = _10171; + uint16_t _10172 = (uint16_t)(252); + _curvea0[983] = _10172; + uint16_t _10173 = (uint16_t)(252); + _curvea0[984] = _10173; + uint16_t _10174 = (uint16_t)(253); + _curvea0[985] = _10174; + uint16_t _10175 = (uint16_t)(253); + _curvea0[986] = _10175; + uint16_t _10176 = (uint16_t)(253); + _curvea0[987] = _10176; + uint16_t _10177 = (uint16_t)(253); + _curvea0[988] = _10177; + uint16_t _10178 = (uint16_t)(253); + _curvea0[989] = _10178; + uint16_t _10179 = (uint16_t)(253); + _curvea0[990] = _10179; + uint16_t _10180 = (uint16_t)(253); + _curvea0[991] = _10180; + uint16_t _10181 = (uint16_t)(253); + _curvea0[992] = _10181; + uint16_t _10182 = (uint16_t)(253); + _curvea0[993] = _10182; + uint16_t _10183 = (uint16_t)(253); + _curvea0[994] = _10183; + uint16_t _10184 = (uint16_t)(253); + _curvea0[995] = _10184; + uint16_t _10185 = (uint16_t)(253); + _curvea0[996] = _10185; + uint16_t _10186 = (uint16_t)(253); + _curvea0[997] = _10186; + uint16_t _10187 = (uint16_t)(254); + _curvea0[998] = _10187; + uint16_t _10188 = (uint16_t)(254); + _curvea0[999] = _10188; + uint16_t _10189 = (uint16_t)(254); + _curvea0[1000] = _10189; + uint16_t _10190 = (uint16_t)(254); + _curvea0[1001] = _10190; + uint16_t _10191 = (uint16_t)(254); + _curvea0[1002] = _10191; + uint16_t _10192 = (uint16_t)(254); + _curvea0[1003] = _10192; + uint16_t _10193 = (uint16_t)(254); + _curvea0[1004] = _10193; + uint16_t _10194 = (uint16_t)(254); + _curvea0[1005] = _10194; + uint16_t _10195 = (uint16_t)(254); + _curvea0[1006] = _10195; + uint16_t _10196 = (uint16_t)(254); + _curvea0[1007] = _10196; + uint16_t _10197 = (uint16_t)(254); + _curvea0[1008] = _10197; + uint16_t _10198 = (uint16_t)(254); + _curvea0[1009] = _10198; + uint16_t _10199 = (uint16_t)(254); + _curvea0[1010] = _10199; + uint16_t _10200 = (uint16_t)(255); + _curvea0[1011] = _10200; + uint16_t _10201 = (uint16_t)(255); + _curvea0[1012] = _10201; + uint16_t _10202 = (uint16_t)(255); + _curvea0[1013] = _10202; + uint16_t _10203 = (uint16_t)(255); + _curvea0[1014] = _10203; + uint16_t _10204 = (uint16_t)(255); + _curvea0[1015] = _10204; + uint16_t _10205 = (uint16_t)(255); + _curvea0[1016] = _10205; + uint16_t _10206 = (uint16_t)(255); + _curvea0[1017] = _10206; + uint16_t _10207 = (uint16_t)(255); + _curvea0[1018] = _10207; + uint16_t _10208 = (uint16_t)(255); + _curvea0[1019] = _10208; + uint16_t _10209 = (uint16_t)(255); + _curvea0[1020] = _10209; + uint16_t _10210 = (uint16_t)(255); + _curvea0[1021] = _10210; + uint16_t _10211 = (uint16_t)(255); + _curvea0[1022] = _10211; + uint16_t _10212 = (uint16_t)(255); + _curvea0[1023] = _10212; + + int16_t _10213 = (int16_t)(1023); + int16_t _10214 = min(_corrected_stencil_6, _10213); + int16_t _10215 = (int16_t)(0); + int16_t _10216 = max(_10214, _10215); + uint16_t _10217 = (uint16_t)(_10216); + int32_t _10218 = (int32_t)(_10217); + uint16_t _10219 = ((const uint16_t *)_curvea0)[_10218]; + return _10219; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_6(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_7 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _10237 = (uint16_t)(0); + _curvea0[0] = _10237; + uint16_t _10238 = (uint16_t)(4); + _curvea0[1] = _10238; + uint16_t _10239 = (uint16_t)(7); + _curvea0[2] = _10239; + uint16_t _10240 = (uint16_t)(8); + _curvea0[3] = _10240; + uint16_t _10241 = (uint16_t)(10); + _curvea0[4] = _10241; + uint16_t _10242 = (uint16_t)(11); + _curvea0[5] = _10242; + uint16_t _10243 = (uint16_t)(12); + _curvea0[6] = _10243; + uint16_t _10244 = (uint16_t)(13); + _curvea0[7] = _10244; + uint16_t _10245 = (uint16_t)(14); + _curvea0[8] = _10245; + uint16_t _10246 = (uint16_t)(15); + _curvea0[9] = _10246; + uint16_t _10247 = (uint16_t)(16); + _curvea0[10] = _10247; + uint16_t _10248 = (uint16_t)(17); + _curvea0[11] = _10248; + uint16_t _10249 = (uint16_t)(18); + _curvea0[12] = _10249; + uint16_t _10250 = (uint16_t)(19); + _curvea0[13] = _10250; + uint16_t _10251 = (uint16_t)(20); + _curvea0[14] = _10251; + uint16_t _10252 = (uint16_t)(21); + _curvea0[15] = _10252; + uint16_t _10253 = (uint16_t)(22); + _curvea0[16] = _10253; + uint16_t _10254 = (uint16_t)(22); + _curvea0[17] = _10254; + uint16_t _10255 = (uint16_t)(23); + _curvea0[18] = _10255; + uint16_t _10256 = (uint16_t)(24); + _curvea0[19] = _10256; + uint16_t _10257 = (uint16_t)(25); + _curvea0[20] = _10257; + uint16_t _10258 = (uint16_t)(25); + _curvea0[21] = _10258; + uint16_t _10259 = (uint16_t)(26); + _curvea0[22] = _10259; + uint16_t _10260 = (uint16_t)(27); + _curvea0[23] = _10260; + uint16_t _10261 = (uint16_t)(27); + _curvea0[24] = _10261; + uint16_t _10262 = (uint16_t)(28); + _curvea0[25] = _10262; + uint16_t _10263 = (uint16_t)(29); + _curvea0[26] = _10263; + uint16_t _10264 = (uint16_t)(29); + _curvea0[27] = _10264; + uint16_t _10265 = (uint16_t)(30); + _curvea0[28] = _10265; + uint16_t _10266 = (uint16_t)(31); + _curvea0[29] = _10266; + uint16_t _10267 = (uint16_t)(31); + _curvea0[30] = _10267; + uint16_t _10268 = (uint16_t)(32); + _curvea0[31] = _10268; + uint16_t _10269 = (uint16_t)(33); + _curvea0[32] = _10269; + uint16_t _10270 = (uint16_t)(33); + _curvea0[33] = _10270; + uint16_t _10271 = (uint16_t)(34); + _curvea0[34] = _10271; + uint16_t _10272 = (uint16_t)(34); + _curvea0[35] = _10272; + uint16_t _10273 = (uint16_t)(35); + _curvea0[36] = _10273; + uint16_t _10274 = (uint16_t)(36); + _curvea0[37] = _10274; + uint16_t _10275 = (uint16_t)(36); + _curvea0[38] = _10275; + uint16_t _10276 = (uint16_t)(37); + _curvea0[39] = _10276; + uint16_t _10277 = (uint16_t)(37); + _curvea0[40] = _10277; + uint16_t _10278 = (uint16_t)(38); + _curvea0[41] = _10278; + uint16_t _10279 = (uint16_t)(39); + _curvea0[42] = _10279; + uint16_t _10280 = (uint16_t)(39); + _curvea0[43] = _10280; + uint16_t _10281 = (uint16_t)(40); + _curvea0[44] = _10281; + uint16_t _10282 = (uint16_t)(40); + _curvea0[45] = _10282; + uint16_t _10283 = (uint16_t)(41); + _curvea0[46] = _10283; + uint16_t _10284 = (uint16_t)(41); + _curvea0[47] = _10284; + uint16_t _10285 = (uint16_t)(42); + _curvea0[48] = _10285; + uint16_t _10286 = (uint16_t)(42); + _curvea0[49] = _10286; + uint16_t _10287 = (uint16_t)(43); + _curvea0[50] = _10287; + uint16_t _10288 = (uint16_t)(44); + _curvea0[51] = _10288; + uint16_t _10289 = (uint16_t)(44); + _curvea0[52] = _10289; + uint16_t _10290 = (uint16_t)(45); + _curvea0[53] = _10290; + uint16_t _10291 = (uint16_t)(45); + _curvea0[54] = _10291; + uint16_t _10292 = (uint16_t)(46); + _curvea0[55] = _10292; + uint16_t _10293 = (uint16_t)(46); + _curvea0[56] = _10293; + uint16_t _10294 = (uint16_t)(47); + _curvea0[57] = _10294; + uint16_t _10295 = (uint16_t)(47); + _curvea0[58] = _10295; + uint16_t _10296 = (uint16_t)(48); + _curvea0[59] = _10296; + uint16_t _10297 = (uint16_t)(48); + _curvea0[60] = _10297; + uint16_t _10298 = (uint16_t)(49); + _curvea0[61] = _10298; + uint16_t _10299 = (uint16_t)(49); + _curvea0[62] = _10299; + uint16_t _10300 = (uint16_t)(50); + _curvea0[63] = _10300; + uint16_t _10301 = (uint16_t)(50); + _curvea0[64] = _10301; + uint16_t _10302 = (uint16_t)(51); + _curvea0[65] = _10302; + uint16_t _10303 = (uint16_t)(51); + _curvea0[66] = _10303; + uint16_t _10304 = (uint16_t)(52); + _curvea0[67] = _10304; + uint16_t _10305 = (uint16_t)(52); + _curvea0[68] = _10305; + uint16_t _10306 = (uint16_t)(53); + _curvea0[69] = _10306; + uint16_t _10307 = (uint16_t)(53); + _curvea0[70] = _10307; + uint16_t _10308 = (uint16_t)(54); + _curvea0[71] = _10308; + uint16_t _10309 = (uint16_t)(54); + _curvea0[72] = _10309; + uint16_t _10310 = (uint16_t)(55); + _curvea0[73] = _10310; + uint16_t _10311 = (uint16_t)(55); + _curvea0[74] = _10311; + uint16_t _10312 = (uint16_t)(56); + _curvea0[75] = _10312; + uint16_t _10313 = (uint16_t)(56); + _curvea0[76] = _10313; + uint16_t _10314 = (uint16_t)(57); + _curvea0[77] = _10314; + uint16_t _10315 = (uint16_t)(57); + _curvea0[78] = _10315; + uint16_t _10316 = (uint16_t)(58); + _curvea0[79] = _10316; + uint16_t _10317 = (uint16_t)(58); + _curvea0[80] = _10317; + uint16_t _10318 = (uint16_t)(58); + _curvea0[81] = _10318; + uint16_t _10319 = (uint16_t)(59); + _curvea0[82] = _10319; + uint16_t _10320 = (uint16_t)(59); + _curvea0[83] = _10320; + uint16_t _10321 = (uint16_t)(60); + _curvea0[84] = _10321; + uint16_t _10322 = (uint16_t)(60); + _curvea0[85] = _10322; + uint16_t _10323 = (uint16_t)(61); + _curvea0[86] = _10323; + uint16_t _10324 = (uint16_t)(61); + _curvea0[87] = _10324; + uint16_t _10325 = (uint16_t)(62); + _curvea0[88] = _10325; + uint16_t _10326 = (uint16_t)(62); + _curvea0[89] = _10326; + uint16_t _10327 = (uint16_t)(63); + _curvea0[90] = _10327; + uint16_t _10328 = (uint16_t)(63); + _curvea0[91] = _10328; + uint16_t _10329 = (uint16_t)(64); + _curvea0[92] = _10329; + uint16_t _10330 = (uint16_t)(64); + _curvea0[93] = _10330; + uint16_t _10331 = (uint16_t)(64); + _curvea0[94] = _10331; + uint16_t _10332 = (uint16_t)(65); + _curvea0[95] = _10332; + uint16_t _10333 = (uint16_t)(65); + _curvea0[96] = _10333; + uint16_t _10334 = (uint16_t)(66); + _curvea0[97] = _10334; + uint16_t _10335 = (uint16_t)(66); + _curvea0[98] = _10335; + uint16_t _10336 = (uint16_t)(67); + _curvea0[99] = _10336; + uint16_t _10337 = (uint16_t)(67); + _curvea0[100] = _10337; + uint16_t _10338 = (uint16_t)(68); + _curvea0[101] = _10338; + uint16_t _10339 = (uint16_t)(68); + _curvea0[102] = _10339; + uint16_t _10340 = (uint16_t)(68); + _curvea0[103] = _10340; + uint16_t _10341 = (uint16_t)(69); + _curvea0[104] = _10341; + uint16_t _10342 = (uint16_t)(69); + _curvea0[105] = _10342; + uint16_t _10343 = (uint16_t)(70); + _curvea0[106] = _10343; + uint16_t _10344 = (uint16_t)(70); + _curvea0[107] = _10344; + uint16_t _10345 = (uint16_t)(71); + _curvea0[108] = _10345; + uint16_t _10346 = (uint16_t)(71); + _curvea0[109] = _10346; + uint16_t _10347 = (uint16_t)(71); + _curvea0[110] = _10347; + uint16_t _10348 = (uint16_t)(72); + _curvea0[111] = _10348; + uint16_t _10349 = (uint16_t)(72); + _curvea0[112] = _10349; + uint16_t _10350 = (uint16_t)(73); + _curvea0[113] = _10350; + uint16_t _10351 = (uint16_t)(73); + _curvea0[114] = _10351; + uint16_t _10352 = (uint16_t)(74); + _curvea0[115] = _10352; + uint16_t _10353 = (uint16_t)(74); + _curvea0[116] = _10353; + uint16_t _10354 = (uint16_t)(74); + _curvea0[117] = _10354; + uint16_t _10355 = (uint16_t)(75); + _curvea0[118] = _10355; + uint16_t _10356 = (uint16_t)(75); + _curvea0[119] = _10356; + uint16_t _10357 = (uint16_t)(76); + _curvea0[120] = _10357; + uint16_t _10358 = (uint16_t)(76); + _curvea0[121] = _10358; + uint16_t _10359 = (uint16_t)(77); + _curvea0[122] = _10359; + uint16_t _10360 = (uint16_t)(77); + _curvea0[123] = _10360; + uint16_t _10361 = (uint16_t)(77); + _curvea0[124] = _10361; + uint16_t _10362 = (uint16_t)(78); + _curvea0[125] = _10362; + uint16_t _10363 = (uint16_t)(78); + _curvea0[126] = _10363; + uint16_t _10364 = (uint16_t)(79); + _curvea0[127] = _10364; + uint16_t _10365 = (uint16_t)(79); + _curvea0[128] = _10365; + uint16_t _10366 = (uint16_t)(79); + _curvea0[129] = _10366; + uint16_t _10367 = (uint16_t)(80); + _curvea0[130] = _10367; + uint16_t _10368 = (uint16_t)(80); + _curvea0[131] = _10368; + uint16_t _10369 = (uint16_t)(81); + _curvea0[132] = _10369; + uint16_t _10370 = (uint16_t)(81); + _curvea0[133] = _10370; + uint16_t _10371 = (uint16_t)(82); + _curvea0[134] = _10371; + uint16_t _10372 = (uint16_t)(82); + _curvea0[135] = _10372; + uint16_t _10373 = (uint16_t)(82); + _curvea0[136] = _10373; + uint16_t _10374 = (uint16_t)(83); + _curvea0[137] = _10374; + uint16_t _10375 = (uint16_t)(83); + _curvea0[138] = _10375; + uint16_t _10376 = (uint16_t)(84); + _curvea0[139] = _10376; + uint16_t _10377 = (uint16_t)(84); + _curvea0[140] = _10377; + uint16_t _10378 = (uint16_t)(84); + _curvea0[141] = _10378; + uint16_t _10379 = (uint16_t)(85); + _curvea0[142] = _10379; + uint16_t _10380 = (uint16_t)(85); + _curvea0[143] = _10380; + uint16_t _10381 = (uint16_t)(86); + _curvea0[144] = _10381; + uint16_t _10382 = (uint16_t)(86); + _curvea0[145] = _10382; + uint16_t _10383 = (uint16_t)(86); + _curvea0[146] = _10383; + uint16_t _10384 = (uint16_t)(87); + _curvea0[147] = _10384; + uint16_t _10385 = (uint16_t)(87); + _curvea0[148] = _10385; + uint16_t _10386 = (uint16_t)(88); + _curvea0[149] = _10386; + uint16_t _10387 = (uint16_t)(88); + _curvea0[150] = _10387; + uint16_t _10388 = (uint16_t)(88); + _curvea0[151] = _10388; + uint16_t _10389 = (uint16_t)(89); + _curvea0[152] = _10389; + uint16_t _10390 = (uint16_t)(89); + _curvea0[153] = _10390; + uint16_t _10391 = (uint16_t)(90); + _curvea0[154] = _10391; + uint16_t _10392 = (uint16_t)(90); + _curvea0[155] = _10392; + uint16_t _10393 = (uint16_t)(90); + _curvea0[156] = _10393; + uint16_t _10394 = (uint16_t)(91); + _curvea0[157] = _10394; + uint16_t _10395 = (uint16_t)(91); + _curvea0[158] = _10395; + uint16_t _10396 = (uint16_t)(92); + _curvea0[159] = _10396; + uint16_t _10397 = (uint16_t)(92); + _curvea0[160] = _10397; + uint16_t _10398 = (uint16_t)(92); + _curvea0[161] = _10398; + uint16_t _10399 = (uint16_t)(93); + _curvea0[162] = _10399; + uint16_t _10400 = (uint16_t)(93); + _curvea0[163] = _10400; + uint16_t _10401 = (uint16_t)(93); + _curvea0[164] = _10401; + uint16_t _10402 = (uint16_t)(94); + _curvea0[165] = _10402; + uint16_t _10403 = (uint16_t)(94); + _curvea0[166] = _10403; + uint16_t _10404 = (uint16_t)(95); + _curvea0[167] = _10404; + uint16_t _10405 = (uint16_t)(95); + _curvea0[168] = _10405; + uint16_t _10406 = (uint16_t)(95); + _curvea0[169] = _10406; + uint16_t _10407 = (uint16_t)(96); + _curvea0[170] = _10407; + uint16_t _10408 = (uint16_t)(96); + _curvea0[171] = _10408; + uint16_t _10409 = (uint16_t)(97); + _curvea0[172] = _10409; + uint16_t _10410 = (uint16_t)(97); + _curvea0[173] = _10410; + uint16_t _10411 = (uint16_t)(97); + _curvea0[174] = _10411; + uint16_t _10412 = (uint16_t)(98); + _curvea0[175] = _10412; + uint16_t _10413 = (uint16_t)(98); + _curvea0[176] = _10413; + uint16_t _10414 = (uint16_t)(99); + _curvea0[177] = _10414; + uint16_t _10415 = (uint16_t)(99); + _curvea0[178] = _10415; + uint16_t _10416 = (uint16_t)(99); + _curvea0[179] = _10416; + uint16_t _10417 = (uint16_t)(100); + _curvea0[180] = _10417; + uint16_t _10418 = (uint16_t)(100); + _curvea0[181] = _10418; + uint16_t _10419 = (uint16_t)(100); + _curvea0[182] = _10419; + uint16_t _10420 = (uint16_t)(101); + _curvea0[183] = _10420; + uint16_t _10421 = (uint16_t)(101); + _curvea0[184] = _10421; + uint16_t _10422 = (uint16_t)(102); + _curvea0[185] = _10422; + uint16_t _10423 = (uint16_t)(102); + _curvea0[186] = _10423; + uint16_t _10424 = (uint16_t)(102); + _curvea0[187] = _10424; + uint16_t _10425 = (uint16_t)(103); + _curvea0[188] = _10425; + uint16_t _10426 = (uint16_t)(103); + _curvea0[189] = _10426; + uint16_t _10427 = (uint16_t)(103); + _curvea0[190] = _10427; + uint16_t _10428 = (uint16_t)(104); + _curvea0[191] = _10428; + uint16_t _10429 = (uint16_t)(104); + _curvea0[192] = _10429; + uint16_t _10430 = (uint16_t)(105); + _curvea0[193] = _10430; + uint16_t _10431 = (uint16_t)(105); + _curvea0[194] = _10431; + uint16_t _10432 = (uint16_t)(105); + _curvea0[195] = _10432; + uint16_t _10433 = (uint16_t)(106); + _curvea0[196] = _10433; + uint16_t _10434 = (uint16_t)(106); + _curvea0[197] = _10434; + uint16_t _10435 = (uint16_t)(106); + _curvea0[198] = _10435; + uint16_t _10436 = (uint16_t)(107); + _curvea0[199] = _10436; + uint16_t _10437 = (uint16_t)(107); + _curvea0[200] = _10437; + uint16_t _10438 = (uint16_t)(108); + _curvea0[201] = _10438; + uint16_t _10439 = (uint16_t)(108); + _curvea0[202] = _10439; + uint16_t _10440 = (uint16_t)(108); + _curvea0[203] = _10440; + uint16_t _10441 = (uint16_t)(109); + _curvea0[204] = _10441; + uint16_t _10442 = (uint16_t)(109); + _curvea0[205] = _10442; + uint16_t _10443 = (uint16_t)(109); + _curvea0[206] = _10443; + uint16_t _10444 = (uint16_t)(110); + _curvea0[207] = _10444; + uint16_t _10445 = (uint16_t)(110); + _curvea0[208] = _10445; + uint16_t _10446 = (uint16_t)(111); + _curvea0[209] = _10446; + uint16_t _10447 = (uint16_t)(111); + _curvea0[210] = _10447; + uint16_t _10448 = (uint16_t)(111); + _curvea0[211] = _10448; + uint16_t _10449 = (uint16_t)(112); + _curvea0[212] = _10449; + uint16_t _10450 = (uint16_t)(112); + _curvea0[213] = _10450; + uint16_t _10451 = (uint16_t)(112); + _curvea0[214] = _10451; + uint16_t _10452 = (uint16_t)(113); + _curvea0[215] = _10452; + uint16_t _10453 = (uint16_t)(113); + _curvea0[216] = _10453; + uint16_t _10454 = (uint16_t)(113); + _curvea0[217] = _10454; + uint16_t _10455 = (uint16_t)(114); + _curvea0[218] = _10455; + uint16_t _10456 = (uint16_t)(114); + _curvea0[219] = _10456; + uint16_t _10457 = (uint16_t)(115); + _curvea0[220] = _10457; + uint16_t _10458 = (uint16_t)(115); + _curvea0[221] = _10458; + uint16_t _10459 = (uint16_t)(115); + _curvea0[222] = _10459; + uint16_t _10460 = (uint16_t)(116); + _curvea0[223] = _10460; + uint16_t _10461 = (uint16_t)(116); + _curvea0[224] = _10461; + uint16_t _10462 = (uint16_t)(116); + _curvea0[225] = _10462; + uint16_t _10463 = (uint16_t)(117); + _curvea0[226] = _10463; + uint16_t _10464 = (uint16_t)(117); + _curvea0[227] = _10464; + uint16_t _10465 = (uint16_t)(117); + _curvea0[228] = _10465; + uint16_t _10466 = (uint16_t)(118); + _curvea0[229] = _10466; + uint16_t _10467 = (uint16_t)(118); + _curvea0[230] = _10467; + uint16_t _10468 = (uint16_t)(119); + _curvea0[231] = _10468; + uint16_t _10469 = (uint16_t)(119); + _curvea0[232] = _10469; + uint16_t _10470 = (uint16_t)(119); + _curvea0[233] = _10470; + uint16_t _10471 = (uint16_t)(120); + _curvea0[234] = _10471; + uint16_t _10472 = (uint16_t)(120); + _curvea0[235] = _10472; + uint16_t _10473 = (uint16_t)(120); + _curvea0[236] = _10473; + uint16_t _10474 = (uint16_t)(121); + _curvea0[237] = _10474; + uint16_t _10475 = (uint16_t)(121); + _curvea0[238] = _10475; + uint16_t _10476 = (uint16_t)(121); + _curvea0[239] = _10476; + uint16_t _10477 = (uint16_t)(122); + _curvea0[240] = _10477; + uint16_t _10478 = (uint16_t)(122); + _curvea0[241] = _10478; + uint16_t _10479 = (uint16_t)(123); + _curvea0[242] = _10479; + uint16_t _10480 = (uint16_t)(123); + _curvea0[243] = _10480; + uint16_t _10481 = (uint16_t)(123); + _curvea0[244] = _10481; + uint16_t _10482 = (uint16_t)(124); + _curvea0[245] = _10482; + uint16_t _10483 = (uint16_t)(124); + _curvea0[246] = _10483; + uint16_t _10484 = (uint16_t)(124); + _curvea0[247] = _10484; + uint16_t _10485 = (uint16_t)(125); + _curvea0[248] = _10485; + uint16_t _10486 = (uint16_t)(125); + _curvea0[249] = _10486; + uint16_t _10487 = (uint16_t)(125); + _curvea0[250] = _10487; + uint16_t _10488 = (uint16_t)(126); + _curvea0[251] = _10488; + uint16_t _10489 = (uint16_t)(126); + _curvea0[252] = _10489; + uint16_t _10490 = (uint16_t)(126); + _curvea0[253] = _10490; + uint16_t _10491 = (uint16_t)(127); + _curvea0[254] = _10491; + uint16_t _10492 = (uint16_t)(127); + _curvea0[255] = _10492; + uint16_t _10493 = (uint16_t)(128); + _curvea0[256] = _10493; + uint16_t _10494 = (uint16_t)(128); + _curvea0[257] = _10494; + uint16_t _10495 = (uint16_t)(128); + _curvea0[258] = _10495; + uint16_t _10496 = (uint16_t)(129); + _curvea0[259] = _10496; + uint16_t _10497 = (uint16_t)(129); + _curvea0[260] = _10497; + uint16_t _10498 = (uint16_t)(129); + _curvea0[261] = _10498; + uint16_t _10499 = (uint16_t)(130); + _curvea0[262] = _10499; + uint16_t _10500 = (uint16_t)(130); + _curvea0[263] = _10500; + uint16_t _10501 = (uint16_t)(130); + _curvea0[264] = _10501; + uint16_t _10502 = (uint16_t)(131); + _curvea0[265] = _10502; + uint16_t _10503 = (uint16_t)(131); + _curvea0[266] = _10503; + uint16_t _10504 = (uint16_t)(131); + _curvea0[267] = _10504; + uint16_t _10505 = (uint16_t)(132); + _curvea0[268] = _10505; + uint16_t _10506 = (uint16_t)(132); + _curvea0[269] = _10506; + uint16_t _10507 = (uint16_t)(132); + _curvea0[270] = _10507; + uint16_t _10508 = (uint16_t)(133); + _curvea0[271] = _10508; + uint16_t _10509 = (uint16_t)(133); + _curvea0[272] = _10509; + uint16_t _10510 = (uint16_t)(133); + _curvea0[273] = _10510; + uint16_t _10511 = (uint16_t)(134); + _curvea0[274] = _10511; + uint16_t _10512 = (uint16_t)(134); + _curvea0[275] = _10512; + uint16_t _10513 = (uint16_t)(134); + _curvea0[276] = _10513; + uint16_t _10514 = (uint16_t)(135); + _curvea0[277] = _10514; + uint16_t _10515 = (uint16_t)(135); + _curvea0[278] = _10515; + uint16_t _10516 = (uint16_t)(135); + _curvea0[279] = _10516; + uint16_t _10517 = (uint16_t)(136); + _curvea0[280] = _10517; + uint16_t _10518 = (uint16_t)(136); + _curvea0[281] = _10518; + uint16_t _10519 = (uint16_t)(136); + _curvea0[282] = _10519; + uint16_t _10520 = (uint16_t)(137); + _curvea0[283] = _10520; + uint16_t _10521 = (uint16_t)(137); + _curvea0[284] = _10521; + uint16_t _10522 = (uint16_t)(137); + _curvea0[285] = _10522; + uint16_t _10523 = (uint16_t)(138); + _curvea0[286] = _10523; + uint16_t _10524 = (uint16_t)(138); + _curvea0[287] = _10524; + uint16_t _10525 = (uint16_t)(138); + _curvea0[288] = _10525; + uint16_t _10526 = (uint16_t)(139); + _curvea0[289] = _10526; + uint16_t _10527 = (uint16_t)(139); + _curvea0[290] = _10527; + uint16_t _10528 = (uint16_t)(139); + _curvea0[291] = _10528; + uint16_t _10529 = (uint16_t)(140); + _curvea0[292] = _10529; + uint16_t _10530 = (uint16_t)(140); + _curvea0[293] = _10530; + uint16_t _10531 = (uint16_t)(140); + _curvea0[294] = _10531; + uint16_t _10532 = (uint16_t)(141); + _curvea0[295] = _10532; + uint16_t _10533 = (uint16_t)(141); + _curvea0[296] = _10533; + uint16_t _10534 = (uint16_t)(141); + _curvea0[297] = _10534; + uint16_t _10535 = (uint16_t)(141); + _curvea0[298] = _10535; + uint16_t _10536 = (uint16_t)(142); + _curvea0[299] = _10536; + uint16_t _10537 = (uint16_t)(142); + _curvea0[300] = _10537; + uint16_t _10538 = (uint16_t)(142); + _curvea0[301] = _10538; + uint16_t _10539 = (uint16_t)(143); + _curvea0[302] = _10539; + uint16_t _10540 = (uint16_t)(143); + _curvea0[303] = _10540; + uint16_t _10541 = (uint16_t)(143); + _curvea0[304] = _10541; + uint16_t _10542 = (uint16_t)(144); + _curvea0[305] = _10542; + uint16_t _10543 = (uint16_t)(144); + _curvea0[306] = _10543; + uint16_t _10544 = (uint16_t)(144); + _curvea0[307] = _10544; + uint16_t _10545 = (uint16_t)(145); + _curvea0[308] = _10545; + uint16_t _10546 = (uint16_t)(145); + _curvea0[309] = _10546; + uint16_t _10547 = (uint16_t)(145); + _curvea0[310] = _10547; + uint16_t _10548 = (uint16_t)(145); + _curvea0[311] = _10548; + uint16_t _10549 = (uint16_t)(146); + _curvea0[312] = _10549; + uint16_t _10550 = (uint16_t)(146); + _curvea0[313] = _10550; + uint16_t _10551 = (uint16_t)(146); + _curvea0[314] = _10551; + uint16_t _10552 = (uint16_t)(147); + _curvea0[315] = _10552; + uint16_t _10553 = (uint16_t)(147); + _curvea0[316] = _10553; + uint16_t _10554 = (uint16_t)(147); + _curvea0[317] = _10554; + uint16_t _10555 = (uint16_t)(148); + _curvea0[318] = _10555; + uint16_t _10556 = (uint16_t)(148); + _curvea0[319] = _10556; + uint16_t _10557 = (uint16_t)(148); + _curvea0[320] = _10557; + uint16_t _10558 = (uint16_t)(148); + _curvea0[321] = _10558; + uint16_t _10559 = (uint16_t)(149); + _curvea0[322] = _10559; + uint16_t _10560 = (uint16_t)(149); + _curvea0[323] = _10560; + uint16_t _10561 = (uint16_t)(149); + _curvea0[324] = _10561; + uint16_t _10562 = (uint16_t)(150); + _curvea0[325] = _10562; + uint16_t _10563 = (uint16_t)(150); + _curvea0[326] = _10563; + uint16_t _10564 = (uint16_t)(150); + _curvea0[327] = _10564; + uint16_t _10565 = (uint16_t)(150); + _curvea0[328] = _10565; + uint16_t _10566 = (uint16_t)(151); + _curvea0[329] = _10566; + uint16_t _10567 = (uint16_t)(151); + _curvea0[330] = _10567; + uint16_t _10568 = (uint16_t)(151); + _curvea0[331] = _10568; + uint16_t _10569 = (uint16_t)(152); + _curvea0[332] = _10569; + uint16_t _10570 = (uint16_t)(152); + _curvea0[333] = _10570; + uint16_t _10571 = (uint16_t)(152); + _curvea0[334] = _10571; + uint16_t _10572 = (uint16_t)(152); + _curvea0[335] = _10572; + uint16_t _10573 = (uint16_t)(153); + _curvea0[336] = _10573; + uint16_t _10574 = (uint16_t)(153); + _curvea0[337] = _10574; + uint16_t _10575 = (uint16_t)(153); + _curvea0[338] = _10575; + uint16_t _10576 = (uint16_t)(154); + _curvea0[339] = _10576; + uint16_t _10577 = (uint16_t)(154); + _curvea0[340] = _10577; + uint16_t _10578 = (uint16_t)(154); + _curvea0[341] = _10578; + uint16_t _10579 = (uint16_t)(154); + _curvea0[342] = _10579; + uint16_t _10580 = (uint16_t)(155); + _curvea0[343] = _10580; + uint16_t _10581 = (uint16_t)(155); + _curvea0[344] = _10581; + uint16_t _10582 = (uint16_t)(155); + _curvea0[345] = _10582; + uint16_t _10583 = (uint16_t)(156); + _curvea0[346] = _10583; + uint16_t _10584 = (uint16_t)(156); + _curvea0[347] = _10584; + uint16_t _10585 = (uint16_t)(156); + _curvea0[348] = _10585; + uint16_t _10586 = (uint16_t)(156); + _curvea0[349] = _10586; + uint16_t _10587 = (uint16_t)(157); + _curvea0[350] = _10587; + uint16_t _10588 = (uint16_t)(157); + _curvea0[351] = _10588; + uint16_t _10589 = (uint16_t)(157); + _curvea0[352] = _10589; + uint16_t _10590 = (uint16_t)(157); + _curvea0[353] = _10590; + uint16_t _10591 = (uint16_t)(158); + _curvea0[354] = _10591; + uint16_t _10592 = (uint16_t)(158); + _curvea0[355] = _10592; + uint16_t _10593 = (uint16_t)(158); + _curvea0[356] = _10593; + uint16_t _10594 = (uint16_t)(159); + _curvea0[357] = _10594; + uint16_t _10595 = (uint16_t)(159); + _curvea0[358] = _10595; + uint16_t _10596 = (uint16_t)(159); + _curvea0[359] = _10596; + uint16_t _10597 = (uint16_t)(159); + _curvea0[360] = _10597; + uint16_t _10598 = (uint16_t)(160); + _curvea0[361] = _10598; + uint16_t _10599 = (uint16_t)(160); + _curvea0[362] = _10599; + uint16_t _10600 = (uint16_t)(160); + _curvea0[363] = _10600; + uint16_t _10601 = (uint16_t)(160); + _curvea0[364] = _10601; + uint16_t _10602 = (uint16_t)(161); + _curvea0[365] = _10602; + uint16_t _10603 = (uint16_t)(161); + _curvea0[366] = _10603; + uint16_t _10604 = (uint16_t)(161); + _curvea0[367] = _10604; + uint16_t _10605 = (uint16_t)(161); + _curvea0[368] = _10605; + uint16_t _10606 = (uint16_t)(162); + _curvea0[369] = _10606; + uint16_t _10607 = (uint16_t)(162); + _curvea0[370] = _10607; + uint16_t _10608 = (uint16_t)(162); + _curvea0[371] = _10608; + uint16_t _10609 = (uint16_t)(162); + _curvea0[372] = _10609; + uint16_t _10610 = (uint16_t)(163); + _curvea0[373] = _10610; + uint16_t _10611 = (uint16_t)(163); + _curvea0[374] = _10611; + uint16_t _10612 = (uint16_t)(163); + _curvea0[375] = _10612; + uint16_t _10613 = (uint16_t)(163); + _curvea0[376] = _10613; + uint16_t _10614 = (uint16_t)(164); + _curvea0[377] = _10614; + uint16_t _10615 = (uint16_t)(164); + _curvea0[378] = _10615; + uint16_t _10616 = (uint16_t)(164); + _curvea0[379] = _10616; + uint16_t _10617 = (uint16_t)(164); + _curvea0[380] = _10617; + uint16_t _10618 = (uint16_t)(165); + _curvea0[381] = _10618; + uint16_t _10619 = (uint16_t)(165); + _curvea0[382] = _10619; + uint16_t _10620 = (uint16_t)(165); + _curvea0[383] = _10620; + uint16_t _10621 = (uint16_t)(166); + _curvea0[384] = _10621; + uint16_t _10622 = (uint16_t)(166); + _curvea0[385] = _10622; + uint16_t _10623 = (uint16_t)(166); + _curvea0[386] = _10623; + uint16_t _10624 = (uint16_t)(166); + _curvea0[387] = _10624; + uint16_t _10625 = (uint16_t)(167); + _curvea0[388] = _10625; + uint16_t _10626 = (uint16_t)(167); + _curvea0[389] = _10626; + uint16_t _10627 = (uint16_t)(167); + _curvea0[390] = _10627; + uint16_t _10628 = (uint16_t)(167); + _curvea0[391] = _10628; + uint16_t _10629 = (uint16_t)(167); + _curvea0[392] = _10629; + uint16_t _10630 = (uint16_t)(168); + _curvea0[393] = _10630; + uint16_t _10631 = (uint16_t)(168); + _curvea0[394] = _10631; + uint16_t _10632 = (uint16_t)(168); + _curvea0[395] = _10632; + uint16_t _10633 = (uint16_t)(168); + _curvea0[396] = _10633; + uint16_t _10634 = (uint16_t)(169); + _curvea0[397] = _10634; + uint16_t _10635 = (uint16_t)(169); + _curvea0[398] = _10635; + uint16_t _10636 = (uint16_t)(169); + _curvea0[399] = _10636; + uint16_t _10637 = (uint16_t)(169); + _curvea0[400] = _10637; + uint16_t _10638 = (uint16_t)(170); + _curvea0[401] = _10638; + uint16_t _10639 = (uint16_t)(170); + _curvea0[402] = _10639; + uint16_t _10640 = (uint16_t)(170); + _curvea0[403] = _10640; + uint16_t _10641 = (uint16_t)(170); + _curvea0[404] = _10641; + uint16_t _10642 = (uint16_t)(171); + _curvea0[405] = _10642; + uint16_t _10643 = (uint16_t)(171); + _curvea0[406] = _10643; + uint16_t _10644 = (uint16_t)(171); + _curvea0[407] = _10644; + uint16_t _10645 = (uint16_t)(171); + _curvea0[408] = _10645; + uint16_t _10646 = (uint16_t)(172); + _curvea0[409] = _10646; + uint16_t _10647 = (uint16_t)(172); + _curvea0[410] = _10647; + uint16_t _10648 = (uint16_t)(172); + _curvea0[411] = _10648; + uint16_t _10649 = (uint16_t)(172); + _curvea0[412] = _10649; + uint16_t _10650 = (uint16_t)(173); + _curvea0[413] = _10650; + uint16_t _10651 = (uint16_t)(173); + _curvea0[414] = _10651; + uint16_t _10652 = (uint16_t)(173); + _curvea0[415] = _10652; + uint16_t _10653 = (uint16_t)(173); + _curvea0[416] = _10653; + uint16_t _10654 = (uint16_t)(173); + _curvea0[417] = _10654; + uint16_t _10655 = (uint16_t)(174); + _curvea0[418] = _10655; + uint16_t _10656 = (uint16_t)(174); + _curvea0[419] = _10656; + uint16_t _10657 = (uint16_t)(174); + _curvea0[420] = _10657; + uint16_t _10658 = (uint16_t)(174); + _curvea0[421] = _10658; + uint16_t _10659 = (uint16_t)(175); + _curvea0[422] = _10659; + uint16_t _10660 = (uint16_t)(175); + _curvea0[423] = _10660; + uint16_t _10661 = (uint16_t)(175); + _curvea0[424] = _10661; + uint16_t _10662 = (uint16_t)(175); + _curvea0[425] = _10662; + uint16_t _10663 = (uint16_t)(176); + _curvea0[426] = _10663; + uint16_t _10664 = (uint16_t)(176); + _curvea0[427] = _10664; + uint16_t _10665 = (uint16_t)(176); + _curvea0[428] = _10665; + uint16_t _10666 = (uint16_t)(176); + _curvea0[429] = _10666; + uint16_t _10667 = (uint16_t)(176); + _curvea0[430] = _10667; + uint16_t _10668 = (uint16_t)(177); + _curvea0[431] = _10668; + uint16_t _10669 = (uint16_t)(177); + _curvea0[432] = _10669; + uint16_t _10670 = (uint16_t)(177); + _curvea0[433] = _10670; + uint16_t _10671 = (uint16_t)(177); + _curvea0[434] = _10671; + uint16_t _10672 = (uint16_t)(178); + _curvea0[435] = _10672; + uint16_t _10673 = (uint16_t)(178); + _curvea0[436] = _10673; + uint16_t _10674 = (uint16_t)(178); + _curvea0[437] = _10674; + uint16_t _10675 = (uint16_t)(178); + _curvea0[438] = _10675; + uint16_t _10676 = (uint16_t)(178); + _curvea0[439] = _10676; + uint16_t _10677 = (uint16_t)(179); + _curvea0[440] = _10677; + uint16_t _10678 = (uint16_t)(179); + _curvea0[441] = _10678; + uint16_t _10679 = (uint16_t)(179); + _curvea0[442] = _10679; + uint16_t _10680 = (uint16_t)(179); + _curvea0[443] = _10680; + uint16_t _10681 = (uint16_t)(180); + _curvea0[444] = _10681; + uint16_t _10682 = (uint16_t)(180); + _curvea0[445] = _10682; + uint16_t _10683 = (uint16_t)(180); + _curvea0[446] = _10683; + uint16_t _10684 = (uint16_t)(180); + _curvea0[447] = _10684; + uint16_t _10685 = (uint16_t)(180); + _curvea0[448] = _10685; + uint16_t _10686 = (uint16_t)(181); + _curvea0[449] = _10686; + uint16_t _10687 = (uint16_t)(181); + _curvea0[450] = _10687; + uint16_t _10688 = (uint16_t)(181); + _curvea0[451] = _10688; + uint16_t _10689 = (uint16_t)(181); + _curvea0[452] = _10689; + uint16_t _10690 = (uint16_t)(181); + _curvea0[453] = _10690; + uint16_t _10691 = (uint16_t)(182); + _curvea0[454] = _10691; + uint16_t _10692 = (uint16_t)(182); + _curvea0[455] = _10692; + uint16_t _10693 = (uint16_t)(182); + _curvea0[456] = _10693; + uint16_t _10694 = (uint16_t)(182); + _curvea0[457] = _10694; + uint16_t _10695 = (uint16_t)(183); + _curvea0[458] = _10695; + uint16_t _10696 = (uint16_t)(183); + _curvea0[459] = _10696; + uint16_t _10697 = (uint16_t)(183); + _curvea0[460] = _10697; + uint16_t _10698 = (uint16_t)(183); + _curvea0[461] = _10698; + uint16_t _10699 = (uint16_t)(183); + _curvea0[462] = _10699; + uint16_t _10700 = (uint16_t)(184); + _curvea0[463] = _10700; + uint16_t _10701 = (uint16_t)(184); + _curvea0[464] = _10701; + uint16_t _10702 = (uint16_t)(184); + _curvea0[465] = _10702; + uint16_t _10703 = (uint16_t)(184); + _curvea0[466] = _10703; + uint16_t _10704 = (uint16_t)(184); + _curvea0[467] = _10704; + uint16_t _10705 = (uint16_t)(185); + _curvea0[468] = _10705; + uint16_t _10706 = (uint16_t)(185); + _curvea0[469] = _10706; + uint16_t _10707 = (uint16_t)(185); + _curvea0[470] = _10707; + uint16_t _10708 = (uint16_t)(185); + _curvea0[471] = _10708; + uint16_t _10709 = (uint16_t)(185); + _curvea0[472] = _10709; + uint16_t _10710 = (uint16_t)(186); + _curvea0[473] = _10710; + uint16_t _10711 = (uint16_t)(186); + _curvea0[474] = _10711; + uint16_t _10712 = (uint16_t)(186); + _curvea0[475] = _10712; + uint16_t _10713 = (uint16_t)(186); + _curvea0[476] = _10713; + uint16_t _10714 = (uint16_t)(187); + _curvea0[477] = _10714; + uint16_t _10715 = (uint16_t)(187); + _curvea0[478] = _10715; + uint16_t _10716 = (uint16_t)(187); + _curvea0[479] = _10716; + uint16_t _10717 = (uint16_t)(187); + _curvea0[480] = _10717; + uint16_t _10718 = (uint16_t)(187); + _curvea0[481] = _10718; + uint16_t _10719 = (uint16_t)(188); + _curvea0[482] = _10719; + uint16_t _10720 = (uint16_t)(188); + _curvea0[483] = _10720; + uint16_t _10721 = (uint16_t)(188); + _curvea0[484] = _10721; + uint16_t _10722 = (uint16_t)(188); + _curvea0[485] = _10722; + uint16_t _10723 = (uint16_t)(188); + _curvea0[486] = _10723; + uint16_t _10724 = (uint16_t)(189); + _curvea0[487] = _10724; + uint16_t _10725 = (uint16_t)(189); + _curvea0[488] = _10725; + uint16_t _10726 = (uint16_t)(189); + _curvea0[489] = _10726; + uint16_t _10727 = (uint16_t)(189); + _curvea0[490] = _10727; + uint16_t _10728 = (uint16_t)(189); + _curvea0[491] = _10728; + uint16_t _10729 = (uint16_t)(190); + _curvea0[492] = _10729; + uint16_t _10730 = (uint16_t)(190); + _curvea0[493] = _10730; + uint16_t _10731 = (uint16_t)(190); + _curvea0[494] = _10731; + uint16_t _10732 = (uint16_t)(190); + _curvea0[495] = _10732; + uint16_t _10733 = (uint16_t)(190); + _curvea0[496] = _10733; + uint16_t _10734 = (uint16_t)(190); + _curvea0[497] = _10734; + uint16_t _10735 = (uint16_t)(191); + _curvea0[498] = _10735; + uint16_t _10736 = (uint16_t)(191); + _curvea0[499] = _10736; + uint16_t _10737 = (uint16_t)(191); + _curvea0[500] = _10737; + uint16_t _10738 = (uint16_t)(191); + _curvea0[501] = _10738; + uint16_t _10739 = (uint16_t)(191); + _curvea0[502] = _10739; + uint16_t _10740 = (uint16_t)(192); + _curvea0[503] = _10740; + uint16_t _10741 = (uint16_t)(192); + _curvea0[504] = _10741; + uint16_t _10742 = (uint16_t)(192); + _curvea0[505] = _10742; + uint16_t _10743 = (uint16_t)(192); + _curvea0[506] = _10743; + uint16_t _10744 = (uint16_t)(192); + _curvea0[507] = _10744; + uint16_t _10745 = (uint16_t)(193); + _curvea0[508] = _10745; + uint16_t _10746 = (uint16_t)(193); + _curvea0[509] = _10746; + uint16_t _10747 = (uint16_t)(193); + _curvea0[510] = _10747; + uint16_t _10748 = (uint16_t)(193); + _curvea0[511] = _10748; + uint16_t _10749 = (uint16_t)(193); + _curvea0[512] = _10749; + uint16_t _10750 = (uint16_t)(194); + _curvea0[513] = _10750; + uint16_t _10751 = (uint16_t)(194); + _curvea0[514] = _10751; + uint16_t _10752 = (uint16_t)(194); + _curvea0[515] = _10752; + uint16_t _10753 = (uint16_t)(194); + _curvea0[516] = _10753; + uint16_t _10754 = (uint16_t)(194); + _curvea0[517] = _10754; + uint16_t _10755 = (uint16_t)(195); + _curvea0[518] = _10755; + uint16_t _10756 = (uint16_t)(195); + _curvea0[519] = _10756; + uint16_t _10757 = (uint16_t)(195); + _curvea0[520] = _10757; + uint16_t _10758 = (uint16_t)(195); + _curvea0[521] = _10758; + uint16_t _10759 = (uint16_t)(195); + _curvea0[522] = _10759; + uint16_t _10760 = (uint16_t)(195); + _curvea0[523] = _10760; + uint16_t _10761 = (uint16_t)(196); + _curvea0[524] = _10761; + uint16_t _10762 = (uint16_t)(196); + _curvea0[525] = _10762; + uint16_t _10763 = (uint16_t)(196); + _curvea0[526] = _10763; + uint16_t _10764 = (uint16_t)(196); + _curvea0[527] = _10764; + uint16_t _10765 = (uint16_t)(196); + _curvea0[528] = _10765; + uint16_t _10766 = (uint16_t)(197); + _curvea0[529] = _10766; + uint16_t _10767 = (uint16_t)(197); + _curvea0[530] = _10767; + uint16_t _10768 = (uint16_t)(197); + _curvea0[531] = _10768; + uint16_t _10769 = (uint16_t)(197); + _curvea0[532] = _10769; + uint16_t _10770 = (uint16_t)(197); + _curvea0[533] = _10770; + uint16_t _10771 = (uint16_t)(197); + _curvea0[534] = _10771; + uint16_t _10772 = (uint16_t)(198); + _curvea0[535] = _10772; + uint16_t _10773 = (uint16_t)(198); + _curvea0[536] = _10773; + uint16_t _10774 = (uint16_t)(198); + _curvea0[537] = _10774; + uint16_t _10775 = (uint16_t)(198); + _curvea0[538] = _10775; + uint16_t _10776 = (uint16_t)(198); + _curvea0[539] = _10776; + uint16_t _10777 = (uint16_t)(199); + _curvea0[540] = _10777; + uint16_t _10778 = (uint16_t)(199); + _curvea0[541] = _10778; + uint16_t _10779 = (uint16_t)(199); + _curvea0[542] = _10779; + uint16_t _10780 = (uint16_t)(199); + _curvea0[543] = _10780; + uint16_t _10781 = (uint16_t)(199); + _curvea0[544] = _10781; + uint16_t _10782 = (uint16_t)(199); + _curvea0[545] = _10782; + uint16_t _10783 = (uint16_t)(200); + _curvea0[546] = _10783; + uint16_t _10784 = (uint16_t)(200); + _curvea0[547] = _10784; + uint16_t _10785 = (uint16_t)(200); + _curvea0[548] = _10785; + uint16_t _10786 = (uint16_t)(200); + _curvea0[549] = _10786; + uint16_t _10787 = (uint16_t)(200); + _curvea0[550] = _10787; + uint16_t _10788 = (uint16_t)(200); + _curvea0[551] = _10788; + uint16_t _10789 = (uint16_t)(201); + _curvea0[552] = _10789; + uint16_t _10790 = (uint16_t)(201); + _curvea0[553] = _10790; + uint16_t _10791 = (uint16_t)(201); + _curvea0[554] = _10791; + uint16_t _10792 = (uint16_t)(201); + _curvea0[555] = _10792; + uint16_t _10793 = (uint16_t)(201); + _curvea0[556] = _10793; + uint16_t _10794 = (uint16_t)(202); + _curvea0[557] = _10794; + uint16_t _10795 = (uint16_t)(202); + _curvea0[558] = _10795; + uint16_t _10796 = (uint16_t)(202); + _curvea0[559] = _10796; + uint16_t _10797 = (uint16_t)(202); + _curvea0[560] = _10797; + uint16_t _10798 = (uint16_t)(202); + _curvea0[561] = _10798; + uint16_t _10799 = (uint16_t)(202); + _curvea0[562] = _10799; + uint16_t _10800 = (uint16_t)(203); + _curvea0[563] = _10800; + uint16_t _10801 = (uint16_t)(203); + _curvea0[564] = _10801; + uint16_t _10802 = (uint16_t)(203); + _curvea0[565] = _10802; + uint16_t _10803 = (uint16_t)(203); + _curvea0[566] = _10803; + uint16_t _10804 = (uint16_t)(203); + _curvea0[567] = _10804; + uint16_t _10805 = (uint16_t)(203); + _curvea0[568] = _10805; + uint16_t _10806 = (uint16_t)(204); + _curvea0[569] = _10806; + uint16_t _10807 = (uint16_t)(204); + _curvea0[570] = _10807; + uint16_t _10808 = (uint16_t)(204); + _curvea0[571] = _10808; + uint16_t _10809 = (uint16_t)(204); + _curvea0[572] = _10809; + uint16_t _10810 = (uint16_t)(204); + _curvea0[573] = _10810; + uint16_t _10811 = (uint16_t)(204); + _curvea0[574] = _10811; + uint16_t _10812 = (uint16_t)(205); + _curvea0[575] = _10812; + uint16_t _10813 = (uint16_t)(205); + _curvea0[576] = _10813; + uint16_t _10814 = (uint16_t)(205); + _curvea0[577] = _10814; + uint16_t _10815 = (uint16_t)(205); + _curvea0[578] = _10815; + uint16_t _10816 = (uint16_t)(205); + _curvea0[579] = _10816; + uint16_t _10817 = (uint16_t)(205); + _curvea0[580] = _10817; + uint16_t _10818 = (uint16_t)(206); + _curvea0[581] = _10818; + uint16_t _10819 = (uint16_t)(206); + _curvea0[582] = _10819; + uint16_t _10820 = (uint16_t)(206); + _curvea0[583] = _10820; + uint16_t _10821 = (uint16_t)(206); + _curvea0[584] = _10821; + uint16_t _10822 = (uint16_t)(206); + _curvea0[585] = _10822; + uint16_t _10823 = (uint16_t)(206); + _curvea0[586] = _10823; + uint16_t _10824 = (uint16_t)(207); + _curvea0[587] = _10824; + uint16_t _10825 = (uint16_t)(207); + _curvea0[588] = _10825; + uint16_t _10826 = (uint16_t)(207); + _curvea0[589] = _10826; + uint16_t _10827 = (uint16_t)(207); + _curvea0[590] = _10827; + uint16_t _10828 = (uint16_t)(207); + _curvea0[591] = _10828; + uint16_t _10829 = (uint16_t)(207); + _curvea0[592] = _10829; + uint16_t _10830 = (uint16_t)(208); + _curvea0[593] = _10830; + uint16_t _10831 = (uint16_t)(208); + _curvea0[594] = _10831; + uint16_t _10832 = (uint16_t)(208); + _curvea0[595] = _10832; + uint16_t _10833 = (uint16_t)(208); + _curvea0[596] = _10833; + uint16_t _10834 = (uint16_t)(208); + _curvea0[597] = _10834; + uint16_t _10835 = (uint16_t)(208); + _curvea0[598] = _10835; + uint16_t _10836 = (uint16_t)(209); + _curvea0[599] = _10836; + uint16_t _10837 = (uint16_t)(209); + _curvea0[600] = _10837; + uint16_t _10838 = (uint16_t)(209); + _curvea0[601] = _10838; + uint16_t _10839 = (uint16_t)(209); + _curvea0[602] = _10839; + uint16_t _10840 = (uint16_t)(209); + _curvea0[603] = _10840; + uint16_t _10841 = (uint16_t)(209); + _curvea0[604] = _10841; + uint16_t _10842 = (uint16_t)(209); + _curvea0[605] = _10842; + uint16_t _10843 = (uint16_t)(210); + _curvea0[606] = _10843; + uint16_t _10844 = (uint16_t)(210); + _curvea0[607] = _10844; + uint16_t _10845 = (uint16_t)(210); + _curvea0[608] = _10845; + uint16_t _10846 = (uint16_t)(210); + _curvea0[609] = _10846; + uint16_t _10847 = (uint16_t)(210); + _curvea0[610] = _10847; + uint16_t _10848 = (uint16_t)(210); + _curvea0[611] = _10848; + uint16_t _10849 = (uint16_t)(211); + _curvea0[612] = _10849; + uint16_t _10850 = (uint16_t)(211); + _curvea0[613] = _10850; + uint16_t _10851 = (uint16_t)(211); + _curvea0[614] = _10851; + uint16_t _10852 = (uint16_t)(211); + _curvea0[615] = _10852; + uint16_t _10853 = (uint16_t)(211); + _curvea0[616] = _10853; + uint16_t _10854 = (uint16_t)(211); + _curvea0[617] = _10854; + uint16_t _10855 = (uint16_t)(211); + _curvea0[618] = _10855; + uint16_t _10856 = (uint16_t)(212); + _curvea0[619] = _10856; + uint16_t _10857 = (uint16_t)(212); + _curvea0[620] = _10857; + uint16_t _10858 = (uint16_t)(212); + _curvea0[621] = _10858; + uint16_t _10859 = (uint16_t)(212); + _curvea0[622] = _10859; + uint16_t _10860 = (uint16_t)(212); + _curvea0[623] = _10860; + uint16_t _10861 = (uint16_t)(212); + _curvea0[624] = _10861; + uint16_t _10862 = (uint16_t)(213); + _curvea0[625] = _10862; + uint16_t _10863 = (uint16_t)(213); + _curvea0[626] = _10863; + uint16_t _10864 = (uint16_t)(213); + _curvea0[627] = _10864; + uint16_t _10865 = (uint16_t)(213); + _curvea0[628] = _10865; + uint16_t _10866 = (uint16_t)(213); + _curvea0[629] = _10866; + uint16_t _10867 = (uint16_t)(213); + _curvea0[630] = _10867; + uint16_t _10868 = (uint16_t)(213); + _curvea0[631] = _10868; + uint16_t _10869 = (uint16_t)(214); + _curvea0[632] = _10869; + uint16_t _10870 = (uint16_t)(214); + _curvea0[633] = _10870; + uint16_t _10871 = (uint16_t)(214); + _curvea0[634] = _10871; + uint16_t _10872 = (uint16_t)(214); + _curvea0[635] = _10872; + uint16_t _10873 = (uint16_t)(214); + _curvea0[636] = _10873; + uint16_t _10874 = (uint16_t)(214); + _curvea0[637] = _10874; + uint16_t _10875 = (uint16_t)(214); + _curvea0[638] = _10875; + uint16_t _10876 = (uint16_t)(215); + _curvea0[639] = _10876; + uint16_t _10877 = (uint16_t)(215); + _curvea0[640] = _10877; + uint16_t _10878 = (uint16_t)(215); + _curvea0[641] = _10878; + uint16_t _10879 = (uint16_t)(215); + _curvea0[642] = _10879; + uint16_t _10880 = (uint16_t)(215); + _curvea0[643] = _10880; + uint16_t _10881 = (uint16_t)(215); + _curvea0[644] = _10881; + uint16_t _10882 = (uint16_t)(216); + _curvea0[645] = _10882; + uint16_t _10883 = (uint16_t)(216); + _curvea0[646] = _10883; + uint16_t _10884 = (uint16_t)(216); + _curvea0[647] = _10884; + uint16_t _10885 = (uint16_t)(216); + _curvea0[648] = _10885; + uint16_t _10886 = (uint16_t)(216); + _curvea0[649] = _10886; + uint16_t _10887 = (uint16_t)(216); + _curvea0[650] = _10887; + uint16_t _10888 = (uint16_t)(216); + _curvea0[651] = _10888; + uint16_t _10889 = (uint16_t)(217); + _curvea0[652] = _10889; + uint16_t _10890 = (uint16_t)(217); + _curvea0[653] = _10890; + uint16_t _10891 = (uint16_t)(217); + _curvea0[654] = _10891; + uint16_t _10892 = (uint16_t)(217); + _curvea0[655] = _10892; + uint16_t _10893 = (uint16_t)(217); + _curvea0[656] = _10893; + uint16_t _10894 = (uint16_t)(217); + _curvea0[657] = _10894; + uint16_t _10895 = (uint16_t)(217); + _curvea0[658] = _10895; + uint16_t _10896 = (uint16_t)(218); + _curvea0[659] = _10896; + uint16_t _10897 = (uint16_t)(218); + _curvea0[660] = _10897; + uint16_t _10898 = (uint16_t)(218); + _curvea0[661] = _10898; + uint16_t _10899 = (uint16_t)(218); + _curvea0[662] = _10899; + uint16_t _10900 = (uint16_t)(218); + _curvea0[663] = _10900; + uint16_t _10901 = (uint16_t)(218); + _curvea0[664] = _10901; + uint16_t _10902 = (uint16_t)(218); + _curvea0[665] = _10902; + uint16_t _10903 = (uint16_t)(219); + _curvea0[666] = _10903; + uint16_t _10904 = (uint16_t)(219); + _curvea0[667] = _10904; + uint16_t _10905 = (uint16_t)(219); + _curvea0[668] = _10905; + uint16_t _10906 = (uint16_t)(219); + _curvea0[669] = _10906; + uint16_t _10907 = (uint16_t)(219); + _curvea0[670] = _10907; + uint16_t _10908 = (uint16_t)(219); + _curvea0[671] = _10908; + uint16_t _10909 = (uint16_t)(219); + _curvea0[672] = _10909; + uint16_t _10910 = (uint16_t)(220); + _curvea0[673] = _10910; + uint16_t _10911 = (uint16_t)(220); + _curvea0[674] = _10911; + uint16_t _10912 = (uint16_t)(220); + _curvea0[675] = _10912; + uint16_t _10913 = (uint16_t)(220); + _curvea0[676] = _10913; + uint16_t _10914 = (uint16_t)(220); + _curvea0[677] = _10914; + uint16_t _10915 = (uint16_t)(220); + _curvea0[678] = _10915; + uint16_t _10916 = (uint16_t)(220); + _curvea0[679] = _10916; + uint16_t _10917 = (uint16_t)(220); + _curvea0[680] = _10917; + uint16_t _10918 = (uint16_t)(221); + _curvea0[681] = _10918; + uint16_t _10919 = (uint16_t)(221); + _curvea0[682] = _10919; + uint16_t _10920 = (uint16_t)(221); + _curvea0[683] = _10920; + uint16_t _10921 = (uint16_t)(221); + _curvea0[684] = _10921; + uint16_t _10922 = (uint16_t)(221); + _curvea0[685] = _10922; + uint16_t _10923 = (uint16_t)(221); + _curvea0[686] = _10923; + uint16_t _10924 = (uint16_t)(221); + _curvea0[687] = _10924; + uint16_t _10925 = (uint16_t)(222); + _curvea0[688] = _10925; + uint16_t _10926 = (uint16_t)(222); + _curvea0[689] = _10926; + uint16_t _10927 = (uint16_t)(222); + _curvea0[690] = _10927; + uint16_t _10928 = (uint16_t)(222); + _curvea0[691] = _10928; + uint16_t _10929 = (uint16_t)(222); + _curvea0[692] = _10929; + uint16_t _10930 = (uint16_t)(222); + _curvea0[693] = _10930; + uint16_t _10931 = (uint16_t)(222); + _curvea0[694] = _10931; + uint16_t _10932 = (uint16_t)(223); + _curvea0[695] = _10932; + uint16_t _10933 = (uint16_t)(223); + _curvea0[696] = _10933; + uint16_t _10934 = (uint16_t)(223); + _curvea0[697] = _10934; + uint16_t _10935 = (uint16_t)(223); + _curvea0[698] = _10935; + uint16_t _10936 = (uint16_t)(223); + _curvea0[699] = _10936; + uint16_t _10937 = (uint16_t)(223); + _curvea0[700] = _10937; + uint16_t _10938 = (uint16_t)(223); + _curvea0[701] = _10938; + uint16_t _10939 = (uint16_t)(223); + _curvea0[702] = _10939; + uint16_t _10940 = (uint16_t)(224); + _curvea0[703] = _10940; + uint16_t _10941 = (uint16_t)(224); + _curvea0[704] = _10941; + uint16_t _10942 = (uint16_t)(224); + _curvea0[705] = _10942; + uint16_t _10943 = (uint16_t)(224); + _curvea0[706] = _10943; + uint16_t _10944 = (uint16_t)(224); + _curvea0[707] = _10944; + uint16_t _10945 = (uint16_t)(224); + _curvea0[708] = _10945; + uint16_t _10946 = (uint16_t)(224); + _curvea0[709] = _10946; + uint16_t _10947 = (uint16_t)(224); + _curvea0[710] = _10947; + uint16_t _10948 = (uint16_t)(225); + _curvea0[711] = _10948; + uint16_t _10949 = (uint16_t)(225); + _curvea0[712] = _10949; + uint16_t _10950 = (uint16_t)(225); + _curvea0[713] = _10950; + uint16_t _10951 = (uint16_t)(225); + _curvea0[714] = _10951; + uint16_t _10952 = (uint16_t)(225); + _curvea0[715] = _10952; + uint16_t _10953 = (uint16_t)(225); + _curvea0[716] = _10953; + uint16_t _10954 = (uint16_t)(225); + _curvea0[717] = _10954; + uint16_t _10955 = (uint16_t)(226); + _curvea0[718] = _10955; + uint16_t _10956 = (uint16_t)(226); + _curvea0[719] = _10956; + uint16_t _10957 = (uint16_t)(226); + _curvea0[720] = _10957; + uint16_t _10958 = (uint16_t)(226); + _curvea0[721] = _10958; + uint16_t _10959 = (uint16_t)(226); + _curvea0[722] = _10959; + uint16_t _10960 = (uint16_t)(226); + _curvea0[723] = _10960; + uint16_t _10961 = (uint16_t)(226); + _curvea0[724] = _10961; + uint16_t _10962 = (uint16_t)(226); + _curvea0[725] = _10962; + uint16_t _10963 = (uint16_t)(227); + _curvea0[726] = _10963; + uint16_t _10964 = (uint16_t)(227); + _curvea0[727] = _10964; + uint16_t _10965 = (uint16_t)(227); + _curvea0[728] = _10965; + uint16_t _10966 = (uint16_t)(227); + _curvea0[729] = _10966; + uint16_t _10967 = (uint16_t)(227); + _curvea0[730] = _10967; + uint16_t _10968 = (uint16_t)(227); + _curvea0[731] = _10968; + uint16_t _10969 = (uint16_t)(227); + _curvea0[732] = _10969; + uint16_t _10970 = (uint16_t)(227); + _curvea0[733] = _10970; + uint16_t _10971 = (uint16_t)(228); + _curvea0[734] = _10971; + uint16_t _10972 = (uint16_t)(228); + _curvea0[735] = _10972; + uint16_t _10973 = (uint16_t)(228); + _curvea0[736] = _10973; + uint16_t _10974 = (uint16_t)(228); + _curvea0[737] = _10974; + uint16_t _10975 = (uint16_t)(228); + _curvea0[738] = _10975; + uint16_t _10976 = (uint16_t)(228); + _curvea0[739] = _10976; + uint16_t _10977 = (uint16_t)(228); + _curvea0[740] = _10977; + uint16_t _10978 = (uint16_t)(228); + _curvea0[741] = _10978; + uint16_t _10979 = (uint16_t)(228); + _curvea0[742] = _10979; + uint16_t _10980 = (uint16_t)(229); + _curvea0[743] = _10980; + uint16_t _10981 = (uint16_t)(229); + _curvea0[744] = _10981; + uint16_t _10982 = (uint16_t)(229); + _curvea0[745] = _10982; + uint16_t _10983 = (uint16_t)(229); + _curvea0[746] = _10983; + uint16_t _10984 = (uint16_t)(229); + _curvea0[747] = _10984; + uint16_t _10985 = (uint16_t)(229); + _curvea0[748] = _10985; + uint16_t _10986 = (uint16_t)(229); + _curvea0[749] = _10986; + uint16_t _10987 = (uint16_t)(229); + _curvea0[750] = _10987; + uint16_t _10988 = (uint16_t)(230); + _curvea0[751] = _10988; + uint16_t _10989 = (uint16_t)(230); + _curvea0[752] = _10989; + uint16_t _10990 = (uint16_t)(230); + _curvea0[753] = _10990; + uint16_t _10991 = (uint16_t)(230); + _curvea0[754] = _10991; + uint16_t _10992 = (uint16_t)(230); + _curvea0[755] = _10992; + uint16_t _10993 = (uint16_t)(230); + _curvea0[756] = _10993; + uint16_t _10994 = (uint16_t)(230); + _curvea0[757] = _10994; + uint16_t _10995 = (uint16_t)(230); + _curvea0[758] = _10995; + uint16_t _10996 = (uint16_t)(231); + _curvea0[759] = _10996; + uint16_t _10997 = (uint16_t)(231); + _curvea0[760] = _10997; + uint16_t _10998 = (uint16_t)(231); + _curvea0[761] = _10998; + uint16_t _10999 = (uint16_t)(231); + _curvea0[762] = _10999; + uint16_t _11000 = (uint16_t)(231); + _curvea0[763] = _11000; + uint16_t _11001 = (uint16_t)(231); + _curvea0[764] = _11001; + uint16_t _11002 = (uint16_t)(231); + _curvea0[765] = _11002; + uint16_t _11003 = (uint16_t)(231); + _curvea0[766] = _11003; + uint16_t _11004 = (uint16_t)(231); + _curvea0[767] = _11004; + uint16_t _11005 = (uint16_t)(232); + _curvea0[768] = _11005; + uint16_t _11006 = (uint16_t)(232); + _curvea0[769] = _11006; + uint16_t _11007 = (uint16_t)(232); + _curvea0[770] = _11007; + uint16_t _11008 = (uint16_t)(232); + _curvea0[771] = _11008; + uint16_t _11009 = (uint16_t)(232); + _curvea0[772] = _11009; + uint16_t _11010 = (uint16_t)(232); + _curvea0[773] = _11010; + uint16_t _11011 = (uint16_t)(232); + _curvea0[774] = _11011; + uint16_t _11012 = (uint16_t)(232); + _curvea0[775] = _11012; + uint16_t _11013 = (uint16_t)(233); + _curvea0[776] = _11013; + uint16_t _11014 = (uint16_t)(233); + _curvea0[777] = _11014; + uint16_t _11015 = (uint16_t)(233); + _curvea0[778] = _11015; + uint16_t _11016 = (uint16_t)(233); + _curvea0[779] = _11016; + uint16_t _11017 = (uint16_t)(233); + _curvea0[780] = _11017; + uint16_t _11018 = (uint16_t)(233); + _curvea0[781] = _11018; + uint16_t _11019 = (uint16_t)(233); + _curvea0[782] = _11019; + uint16_t _11020 = (uint16_t)(233); + _curvea0[783] = _11020; + uint16_t _11021 = (uint16_t)(233); + _curvea0[784] = _11021; + uint16_t _11022 = (uint16_t)(234); + _curvea0[785] = _11022; + uint16_t _11023 = (uint16_t)(234); + _curvea0[786] = _11023; + uint16_t _11024 = (uint16_t)(234); + _curvea0[787] = _11024; + uint16_t _11025 = (uint16_t)(234); + _curvea0[788] = _11025; + uint16_t _11026 = (uint16_t)(234); + _curvea0[789] = _11026; + uint16_t _11027 = (uint16_t)(234); + _curvea0[790] = _11027; + uint16_t _11028 = (uint16_t)(234); + _curvea0[791] = _11028; + uint16_t _11029 = (uint16_t)(234); + _curvea0[792] = _11029; + uint16_t _11030 = (uint16_t)(234); + _curvea0[793] = _11030; + uint16_t _11031 = (uint16_t)(235); + _curvea0[794] = _11031; + uint16_t _11032 = (uint16_t)(235); + _curvea0[795] = _11032; + uint16_t _11033 = (uint16_t)(235); + _curvea0[796] = _11033; + uint16_t _11034 = (uint16_t)(235); + _curvea0[797] = _11034; + uint16_t _11035 = (uint16_t)(235); + _curvea0[798] = _11035; + uint16_t _11036 = (uint16_t)(235); + _curvea0[799] = _11036; + uint16_t _11037 = (uint16_t)(235); + _curvea0[800] = _11037; + uint16_t _11038 = (uint16_t)(235); + _curvea0[801] = _11038; + uint16_t _11039 = (uint16_t)(235); + _curvea0[802] = _11039; + uint16_t _11040 = (uint16_t)(236); + _curvea0[803] = _11040; + uint16_t _11041 = (uint16_t)(236); + _curvea0[804] = _11041; + uint16_t _11042 = (uint16_t)(236); + _curvea0[805] = _11042; + uint16_t _11043 = (uint16_t)(236); + _curvea0[806] = _11043; + uint16_t _11044 = (uint16_t)(236); + _curvea0[807] = _11044; + uint16_t _11045 = (uint16_t)(236); + _curvea0[808] = _11045; + uint16_t _11046 = (uint16_t)(236); + _curvea0[809] = _11046; + uint16_t _11047 = (uint16_t)(236); + _curvea0[810] = _11047; + uint16_t _11048 = (uint16_t)(236); + _curvea0[811] = _11048; + uint16_t _11049 = (uint16_t)(237); + _curvea0[812] = _11049; + uint16_t _11050 = (uint16_t)(237); + _curvea0[813] = _11050; + uint16_t _11051 = (uint16_t)(237); + _curvea0[814] = _11051; + uint16_t _11052 = (uint16_t)(237); + _curvea0[815] = _11052; + uint16_t _11053 = (uint16_t)(237); + _curvea0[816] = _11053; + uint16_t _11054 = (uint16_t)(237); + _curvea0[817] = _11054; + uint16_t _11055 = (uint16_t)(237); + _curvea0[818] = _11055; + uint16_t _11056 = (uint16_t)(237); + _curvea0[819] = _11056; + uint16_t _11057 = (uint16_t)(237); + _curvea0[820] = _11057; + uint16_t _11058 = (uint16_t)(237); + _curvea0[821] = _11058; + uint16_t _11059 = (uint16_t)(238); + _curvea0[822] = _11059; + uint16_t _11060 = (uint16_t)(238); + _curvea0[823] = _11060; + uint16_t _11061 = (uint16_t)(238); + _curvea0[824] = _11061; + uint16_t _11062 = (uint16_t)(238); + _curvea0[825] = _11062; + uint16_t _11063 = (uint16_t)(238); + _curvea0[826] = _11063; + uint16_t _11064 = (uint16_t)(238); + _curvea0[827] = _11064; + uint16_t _11065 = (uint16_t)(238); + _curvea0[828] = _11065; + uint16_t _11066 = (uint16_t)(238); + _curvea0[829] = _11066; + uint16_t _11067 = (uint16_t)(238); + _curvea0[830] = _11067; + uint16_t _11068 = (uint16_t)(239); + _curvea0[831] = _11068; + uint16_t _11069 = (uint16_t)(239); + _curvea0[832] = _11069; + uint16_t _11070 = (uint16_t)(239); + _curvea0[833] = _11070; + uint16_t _11071 = (uint16_t)(239); + _curvea0[834] = _11071; + uint16_t _11072 = (uint16_t)(239); + _curvea0[835] = _11072; + uint16_t _11073 = (uint16_t)(239); + _curvea0[836] = _11073; + uint16_t _11074 = (uint16_t)(239); + _curvea0[837] = _11074; + uint16_t _11075 = (uint16_t)(239); + _curvea0[838] = _11075; + uint16_t _11076 = (uint16_t)(239); + _curvea0[839] = _11076; + uint16_t _11077 = (uint16_t)(239); + _curvea0[840] = _11077; + uint16_t _11078 = (uint16_t)(240); + _curvea0[841] = _11078; + uint16_t _11079 = (uint16_t)(240); + _curvea0[842] = _11079; + uint16_t _11080 = (uint16_t)(240); + _curvea0[843] = _11080; + uint16_t _11081 = (uint16_t)(240); + _curvea0[844] = _11081; + uint16_t _11082 = (uint16_t)(240); + _curvea0[845] = _11082; + uint16_t _11083 = (uint16_t)(240); + _curvea0[846] = _11083; + uint16_t _11084 = (uint16_t)(240); + _curvea0[847] = _11084; + uint16_t _11085 = (uint16_t)(240); + _curvea0[848] = _11085; + uint16_t _11086 = (uint16_t)(240); + _curvea0[849] = _11086; + uint16_t _11087 = (uint16_t)(240); + _curvea0[850] = _11087; + uint16_t _11088 = (uint16_t)(241); + _curvea0[851] = _11088; + uint16_t _11089 = (uint16_t)(241); + _curvea0[852] = _11089; + uint16_t _11090 = (uint16_t)(241); + _curvea0[853] = _11090; + uint16_t _11091 = (uint16_t)(241); + _curvea0[854] = _11091; + uint16_t _11092 = (uint16_t)(241); + _curvea0[855] = _11092; + uint16_t _11093 = (uint16_t)(241); + _curvea0[856] = _11093; + uint16_t _11094 = (uint16_t)(241); + _curvea0[857] = _11094; + uint16_t _11095 = (uint16_t)(241); + _curvea0[858] = _11095; + uint16_t _11096 = (uint16_t)(241); + _curvea0[859] = _11096; + uint16_t _11097 = (uint16_t)(241); + _curvea0[860] = _11097; + uint16_t _11098 = (uint16_t)(242); + _curvea0[861] = _11098; + uint16_t _11099 = (uint16_t)(242); + _curvea0[862] = _11099; + uint16_t _11100 = (uint16_t)(242); + _curvea0[863] = _11100; + uint16_t _11101 = (uint16_t)(242); + _curvea0[864] = _11101; + uint16_t _11102 = (uint16_t)(242); + _curvea0[865] = _11102; + uint16_t _11103 = (uint16_t)(242); + _curvea0[866] = _11103; + uint16_t _11104 = (uint16_t)(242); + _curvea0[867] = _11104; + uint16_t _11105 = (uint16_t)(242); + _curvea0[868] = _11105; + uint16_t _11106 = (uint16_t)(242); + _curvea0[869] = _11106; + uint16_t _11107 = (uint16_t)(242); + _curvea0[870] = _11107; + uint16_t _11108 = (uint16_t)(243); + _curvea0[871] = _11108; + uint16_t _11109 = (uint16_t)(243); + _curvea0[872] = _11109; + uint16_t _11110 = (uint16_t)(243); + _curvea0[873] = _11110; + uint16_t _11111 = (uint16_t)(243); + _curvea0[874] = _11111; + uint16_t _11112 = (uint16_t)(243); + _curvea0[875] = _11112; + uint16_t _11113 = (uint16_t)(243); + _curvea0[876] = _11113; + uint16_t _11114 = (uint16_t)(243); + _curvea0[877] = _11114; + uint16_t _11115 = (uint16_t)(243); + _curvea0[878] = _11115; + uint16_t _11116 = (uint16_t)(243); + _curvea0[879] = _11116; + uint16_t _11117 = (uint16_t)(243); + _curvea0[880] = _11117; + uint16_t _11118 = (uint16_t)(244); + _curvea0[881] = _11118; + uint16_t _11119 = (uint16_t)(244); + _curvea0[882] = _11119; + uint16_t _11120 = (uint16_t)(244); + _curvea0[883] = _11120; + uint16_t _11121 = (uint16_t)(244); + _curvea0[884] = _11121; + uint16_t _11122 = (uint16_t)(244); + _curvea0[885] = _11122; + uint16_t _11123 = (uint16_t)(244); + _curvea0[886] = _11123; + uint16_t _11124 = (uint16_t)(244); + _curvea0[887] = _11124; + uint16_t _11125 = (uint16_t)(244); + _curvea0[888] = _11125; + uint16_t _11126 = (uint16_t)(244); + _curvea0[889] = _11126; + uint16_t _11127 = (uint16_t)(244); + _curvea0[890] = _11127; + uint16_t _11128 = (uint16_t)(244); + _curvea0[891] = _11128; + uint16_t _11129 = (uint16_t)(245); + _curvea0[892] = _11129; + uint16_t _11130 = (uint16_t)(245); + _curvea0[893] = _11130; + uint16_t _11131 = (uint16_t)(245); + _curvea0[894] = _11131; + uint16_t _11132 = (uint16_t)(245); + _curvea0[895] = _11132; + uint16_t _11133 = (uint16_t)(245); + _curvea0[896] = _11133; + uint16_t _11134 = (uint16_t)(245); + _curvea0[897] = _11134; + uint16_t _11135 = (uint16_t)(245); + _curvea0[898] = _11135; + uint16_t _11136 = (uint16_t)(245); + _curvea0[899] = _11136; + uint16_t _11137 = (uint16_t)(245); + _curvea0[900] = _11137; + uint16_t _11138 = (uint16_t)(245); + _curvea0[901] = _11138; + uint16_t _11139 = (uint16_t)(245); + _curvea0[902] = _11139; + uint16_t _11140 = (uint16_t)(246); + _curvea0[903] = _11140; + uint16_t _11141 = (uint16_t)(246); + _curvea0[904] = _11141; + uint16_t _11142 = (uint16_t)(246); + _curvea0[905] = _11142; + uint16_t _11143 = (uint16_t)(246); + _curvea0[906] = _11143; + uint16_t _11144 = (uint16_t)(246); + _curvea0[907] = _11144; + uint16_t _11145 = (uint16_t)(246); + _curvea0[908] = _11145; + uint16_t _11146 = (uint16_t)(246); + _curvea0[909] = _11146; + uint16_t _11147 = (uint16_t)(246); + _curvea0[910] = _11147; + uint16_t _11148 = (uint16_t)(246); + _curvea0[911] = _11148; + uint16_t _11149 = (uint16_t)(246); + _curvea0[912] = _11149; + uint16_t _11150 = (uint16_t)(246); + _curvea0[913] = _11150; + uint16_t _11151 = (uint16_t)(247); + _curvea0[914] = _11151; + uint16_t _11152 = (uint16_t)(247); + _curvea0[915] = _11152; + uint16_t _11153 = (uint16_t)(247); + _curvea0[916] = _11153; + uint16_t _11154 = (uint16_t)(247); + _curvea0[917] = _11154; + uint16_t _11155 = (uint16_t)(247); + _curvea0[918] = _11155; + uint16_t _11156 = (uint16_t)(247); + _curvea0[919] = _11156; + uint16_t _11157 = (uint16_t)(247); + _curvea0[920] = _11157; + uint16_t _11158 = (uint16_t)(247); + _curvea0[921] = _11158; + uint16_t _11159 = (uint16_t)(247); + _curvea0[922] = _11159; + uint16_t _11160 = (uint16_t)(247); + _curvea0[923] = _11160; + uint16_t _11161 = (uint16_t)(247); + _curvea0[924] = _11161; + uint16_t _11162 = (uint16_t)(248); + _curvea0[925] = _11162; + uint16_t _11163 = (uint16_t)(248); + _curvea0[926] = _11163; + uint16_t _11164 = (uint16_t)(248); + _curvea0[927] = _11164; + uint16_t _11165 = (uint16_t)(248); + _curvea0[928] = _11165; + uint16_t _11166 = (uint16_t)(248); + _curvea0[929] = _11166; + uint16_t _11167 = (uint16_t)(248); + _curvea0[930] = _11167; + uint16_t _11168 = (uint16_t)(248); + _curvea0[931] = _11168; + uint16_t _11169 = (uint16_t)(248); + _curvea0[932] = _11169; + uint16_t _11170 = (uint16_t)(248); + _curvea0[933] = _11170; + uint16_t _11171 = (uint16_t)(248); + _curvea0[934] = _11171; + uint16_t _11172 = (uint16_t)(248); + _curvea0[935] = _11172; + uint16_t _11173 = (uint16_t)(249); + _curvea0[936] = _11173; + uint16_t _11174 = (uint16_t)(249); + _curvea0[937] = _11174; + uint16_t _11175 = (uint16_t)(249); + _curvea0[938] = _11175; + uint16_t _11176 = (uint16_t)(249); + _curvea0[939] = _11176; + uint16_t _11177 = (uint16_t)(249); + _curvea0[940] = _11177; + uint16_t _11178 = (uint16_t)(249); + _curvea0[941] = _11178; + uint16_t _11179 = (uint16_t)(249); + _curvea0[942] = _11179; + uint16_t _11180 = (uint16_t)(249); + _curvea0[943] = _11180; + uint16_t _11181 = (uint16_t)(249); + _curvea0[944] = _11181; + uint16_t _11182 = (uint16_t)(249); + _curvea0[945] = _11182; + uint16_t _11183 = (uint16_t)(249); + _curvea0[946] = _11183; + uint16_t _11184 = (uint16_t)(249); + _curvea0[947] = _11184; + uint16_t _11185 = (uint16_t)(250); + _curvea0[948] = _11185; + uint16_t _11186 = (uint16_t)(250); + _curvea0[949] = _11186; + uint16_t _11187 = (uint16_t)(250); + _curvea0[950] = _11187; + uint16_t _11188 = (uint16_t)(250); + _curvea0[951] = _11188; + uint16_t _11189 = (uint16_t)(250); + _curvea0[952] = _11189; + uint16_t _11190 = (uint16_t)(250); + _curvea0[953] = _11190; + uint16_t _11191 = (uint16_t)(250); + _curvea0[954] = _11191; + uint16_t _11192 = (uint16_t)(250); + _curvea0[955] = _11192; + uint16_t _11193 = (uint16_t)(250); + _curvea0[956] = _11193; + uint16_t _11194 = (uint16_t)(250); + _curvea0[957] = _11194; + uint16_t _11195 = (uint16_t)(250); + _curvea0[958] = _11195; + uint16_t _11196 = (uint16_t)(250); + _curvea0[959] = _11196; + uint16_t _11197 = (uint16_t)(251); + _curvea0[960] = _11197; + uint16_t _11198 = (uint16_t)(251); + _curvea0[961] = _11198; + uint16_t _11199 = (uint16_t)(251); + _curvea0[962] = _11199; + uint16_t _11200 = (uint16_t)(251); + _curvea0[963] = _11200; + uint16_t _11201 = (uint16_t)(251); + _curvea0[964] = _11201; + uint16_t _11202 = (uint16_t)(251); + _curvea0[965] = _11202; + uint16_t _11203 = (uint16_t)(251); + _curvea0[966] = _11203; + uint16_t _11204 = (uint16_t)(251); + _curvea0[967] = _11204; + uint16_t _11205 = (uint16_t)(251); + _curvea0[968] = _11205; + uint16_t _11206 = (uint16_t)(251); + _curvea0[969] = _11206; + uint16_t _11207 = (uint16_t)(251); + _curvea0[970] = _11207; + uint16_t _11208 = (uint16_t)(251); + _curvea0[971] = _11208; + uint16_t _11209 = (uint16_t)(252); + _curvea0[972] = _11209; + uint16_t _11210 = (uint16_t)(252); + _curvea0[973] = _11210; + uint16_t _11211 = (uint16_t)(252); + _curvea0[974] = _11211; + uint16_t _11212 = (uint16_t)(252); + _curvea0[975] = _11212; + uint16_t _11213 = (uint16_t)(252); + _curvea0[976] = _11213; + uint16_t _11214 = (uint16_t)(252); + _curvea0[977] = _11214; + uint16_t _11215 = (uint16_t)(252); + _curvea0[978] = _11215; + uint16_t _11216 = (uint16_t)(252); + _curvea0[979] = _11216; + uint16_t _11217 = (uint16_t)(252); + _curvea0[980] = _11217; + uint16_t _11218 = (uint16_t)(252); + _curvea0[981] = _11218; + uint16_t _11219 = (uint16_t)(252); + _curvea0[982] = _11219; + uint16_t _11220 = (uint16_t)(252); + _curvea0[983] = _11220; + uint16_t _11221 = (uint16_t)(252); + _curvea0[984] = _11221; + uint16_t _11222 = (uint16_t)(253); + _curvea0[985] = _11222; + uint16_t _11223 = (uint16_t)(253); + _curvea0[986] = _11223; + uint16_t _11224 = (uint16_t)(253); + _curvea0[987] = _11224; + uint16_t _11225 = (uint16_t)(253); + _curvea0[988] = _11225; + uint16_t _11226 = (uint16_t)(253); + _curvea0[989] = _11226; + uint16_t _11227 = (uint16_t)(253); + _curvea0[990] = _11227; + uint16_t _11228 = (uint16_t)(253); + _curvea0[991] = _11228; + uint16_t _11229 = (uint16_t)(253); + _curvea0[992] = _11229; + uint16_t _11230 = (uint16_t)(253); + _curvea0[993] = _11230; + uint16_t _11231 = (uint16_t)(253); + _curvea0[994] = _11231; + uint16_t _11232 = (uint16_t)(253); + _curvea0[995] = _11232; + uint16_t _11233 = (uint16_t)(253); + _curvea0[996] = _11233; + uint16_t _11234 = (uint16_t)(253); + _curvea0[997] = _11234; + uint16_t _11235 = (uint16_t)(254); + _curvea0[998] = _11235; + uint16_t _11236 = (uint16_t)(254); + _curvea0[999] = _11236; + uint16_t _11237 = (uint16_t)(254); + _curvea0[1000] = _11237; + uint16_t _11238 = (uint16_t)(254); + _curvea0[1001] = _11238; + uint16_t _11239 = (uint16_t)(254); + _curvea0[1002] = _11239; + uint16_t _11240 = (uint16_t)(254); + _curvea0[1003] = _11240; + uint16_t _11241 = (uint16_t)(254); + _curvea0[1004] = _11241; + uint16_t _11242 = (uint16_t)(254); + _curvea0[1005] = _11242; + uint16_t _11243 = (uint16_t)(254); + _curvea0[1006] = _11243; + uint16_t _11244 = (uint16_t)(254); + _curvea0[1007] = _11244; + uint16_t _11245 = (uint16_t)(254); + _curvea0[1008] = _11245; + uint16_t _11246 = (uint16_t)(254); + _curvea0[1009] = _11246; + uint16_t _11247 = (uint16_t)(254); + _curvea0[1010] = _11247; + uint16_t _11248 = (uint16_t)(255); + _curvea0[1011] = _11248; + uint16_t _11249 = (uint16_t)(255); + _curvea0[1012] = _11249; + uint16_t _11250 = (uint16_t)(255); + _curvea0[1013] = _11250; + uint16_t _11251 = (uint16_t)(255); + _curvea0[1014] = _11251; + uint16_t _11252 = (uint16_t)(255); + _curvea0[1015] = _11252; + uint16_t _11253 = (uint16_t)(255); + _curvea0[1016] = _11253; + uint16_t _11254 = (uint16_t)(255); + _curvea0[1017] = _11254; + uint16_t _11255 = (uint16_t)(255); + _curvea0[1018] = _11255; + uint16_t _11256 = (uint16_t)(255); + _curvea0[1019] = _11256; + uint16_t _11257 = (uint16_t)(255); + _curvea0[1020] = _11257; + uint16_t _11258 = (uint16_t)(255); + _curvea0[1021] = _11258; + uint16_t _11259 = (uint16_t)(255); + _curvea0[1022] = _11259; + uint16_t _11260 = (uint16_t)(255); + _curvea0[1023] = _11260; + + int16_t _11261 = (int16_t)(1023); + int16_t _11262 = min(_corrected_stencil_7, _11261); + int16_t _11263 = (int16_t)(0); + int16_t _11264 = max(_11262, _11263); + uint16_t _11265 = (uint16_t)(_11264); + int32_t _11266 = (int32_t)(_11265); + uint16_t _11267 = ((const uint16_t *)_curvea0)[_11266]; + return _11267; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_7(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_8 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _11285 = (uint16_t)(0); + _curvea0[0] = _11285; + uint16_t _11286 = (uint16_t)(4); + _curvea0[1] = _11286; + uint16_t _11287 = (uint16_t)(7); + _curvea0[2] = _11287; + uint16_t _11288 = (uint16_t)(8); + _curvea0[3] = _11288; + uint16_t _11289 = (uint16_t)(10); + _curvea0[4] = _11289; + uint16_t _11290 = (uint16_t)(11); + _curvea0[5] = _11290; + uint16_t _11291 = (uint16_t)(12); + _curvea0[6] = _11291; + uint16_t _11292 = (uint16_t)(13); + _curvea0[7] = _11292; + uint16_t _11293 = (uint16_t)(14); + _curvea0[8] = _11293; + uint16_t _11294 = (uint16_t)(15); + _curvea0[9] = _11294; + uint16_t _11295 = (uint16_t)(16); + _curvea0[10] = _11295; + uint16_t _11296 = (uint16_t)(17); + _curvea0[11] = _11296; + uint16_t _11297 = (uint16_t)(18); + _curvea0[12] = _11297; + uint16_t _11298 = (uint16_t)(19); + _curvea0[13] = _11298; + uint16_t _11299 = (uint16_t)(20); + _curvea0[14] = _11299; + uint16_t _11300 = (uint16_t)(21); + _curvea0[15] = _11300; + uint16_t _11301 = (uint16_t)(22); + _curvea0[16] = _11301; + uint16_t _11302 = (uint16_t)(22); + _curvea0[17] = _11302; + uint16_t _11303 = (uint16_t)(23); + _curvea0[18] = _11303; + uint16_t _11304 = (uint16_t)(24); + _curvea0[19] = _11304; + uint16_t _11305 = (uint16_t)(25); + _curvea0[20] = _11305; + uint16_t _11306 = (uint16_t)(25); + _curvea0[21] = _11306; + uint16_t _11307 = (uint16_t)(26); + _curvea0[22] = _11307; + uint16_t _11308 = (uint16_t)(27); + _curvea0[23] = _11308; + uint16_t _11309 = (uint16_t)(27); + _curvea0[24] = _11309; + uint16_t _11310 = (uint16_t)(28); + _curvea0[25] = _11310; + uint16_t _11311 = (uint16_t)(29); + _curvea0[26] = _11311; + uint16_t _11312 = (uint16_t)(29); + _curvea0[27] = _11312; + uint16_t _11313 = (uint16_t)(30); + _curvea0[28] = _11313; + uint16_t _11314 = (uint16_t)(31); + _curvea0[29] = _11314; + uint16_t _11315 = (uint16_t)(31); + _curvea0[30] = _11315; + uint16_t _11316 = (uint16_t)(32); + _curvea0[31] = _11316; + uint16_t _11317 = (uint16_t)(33); + _curvea0[32] = _11317; + uint16_t _11318 = (uint16_t)(33); + _curvea0[33] = _11318; + uint16_t _11319 = (uint16_t)(34); + _curvea0[34] = _11319; + uint16_t _11320 = (uint16_t)(34); + _curvea0[35] = _11320; + uint16_t _11321 = (uint16_t)(35); + _curvea0[36] = _11321; + uint16_t _11322 = (uint16_t)(36); + _curvea0[37] = _11322; + uint16_t _11323 = (uint16_t)(36); + _curvea0[38] = _11323; + uint16_t _11324 = (uint16_t)(37); + _curvea0[39] = _11324; + uint16_t _11325 = (uint16_t)(37); + _curvea0[40] = _11325; + uint16_t _11326 = (uint16_t)(38); + _curvea0[41] = _11326; + uint16_t _11327 = (uint16_t)(39); + _curvea0[42] = _11327; + uint16_t _11328 = (uint16_t)(39); + _curvea0[43] = _11328; + uint16_t _11329 = (uint16_t)(40); + _curvea0[44] = _11329; + uint16_t _11330 = (uint16_t)(40); + _curvea0[45] = _11330; + uint16_t _11331 = (uint16_t)(41); + _curvea0[46] = _11331; + uint16_t _11332 = (uint16_t)(41); + _curvea0[47] = _11332; + uint16_t _11333 = (uint16_t)(42); + _curvea0[48] = _11333; + uint16_t _11334 = (uint16_t)(42); + _curvea0[49] = _11334; + uint16_t _11335 = (uint16_t)(43); + _curvea0[50] = _11335; + uint16_t _11336 = (uint16_t)(44); + _curvea0[51] = _11336; + uint16_t _11337 = (uint16_t)(44); + _curvea0[52] = _11337; + uint16_t _11338 = (uint16_t)(45); + _curvea0[53] = _11338; + uint16_t _11339 = (uint16_t)(45); + _curvea0[54] = _11339; + uint16_t _11340 = (uint16_t)(46); + _curvea0[55] = _11340; + uint16_t _11341 = (uint16_t)(46); + _curvea0[56] = _11341; + uint16_t _11342 = (uint16_t)(47); + _curvea0[57] = _11342; + uint16_t _11343 = (uint16_t)(47); + _curvea0[58] = _11343; + uint16_t _11344 = (uint16_t)(48); + _curvea0[59] = _11344; + uint16_t _11345 = (uint16_t)(48); + _curvea0[60] = _11345; + uint16_t _11346 = (uint16_t)(49); + _curvea0[61] = _11346; + uint16_t _11347 = (uint16_t)(49); + _curvea0[62] = _11347; + uint16_t _11348 = (uint16_t)(50); + _curvea0[63] = _11348; + uint16_t _11349 = (uint16_t)(50); + _curvea0[64] = _11349; + uint16_t _11350 = (uint16_t)(51); + _curvea0[65] = _11350; + uint16_t _11351 = (uint16_t)(51); + _curvea0[66] = _11351; + uint16_t _11352 = (uint16_t)(52); + _curvea0[67] = _11352; + uint16_t _11353 = (uint16_t)(52); + _curvea0[68] = _11353; + uint16_t _11354 = (uint16_t)(53); + _curvea0[69] = _11354; + uint16_t _11355 = (uint16_t)(53); + _curvea0[70] = _11355; + uint16_t _11356 = (uint16_t)(54); + _curvea0[71] = _11356; + uint16_t _11357 = (uint16_t)(54); + _curvea0[72] = _11357; + uint16_t _11358 = (uint16_t)(55); + _curvea0[73] = _11358; + uint16_t _11359 = (uint16_t)(55); + _curvea0[74] = _11359; + uint16_t _11360 = (uint16_t)(56); + _curvea0[75] = _11360; + uint16_t _11361 = (uint16_t)(56); + _curvea0[76] = _11361; + uint16_t _11362 = (uint16_t)(57); + _curvea0[77] = _11362; + uint16_t _11363 = (uint16_t)(57); + _curvea0[78] = _11363; + uint16_t _11364 = (uint16_t)(58); + _curvea0[79] = _11364; + uint16_t _11365 = (uint16_t)(58); + _curvea0[80] = _11365; + uint16_t _11366 = (uint16_t)(58); + _curvea0[81] = _11366; + uint16_t _11367 = (uint16_t)(59); + _curvea0[82] = _11367; + uint16_t _11368 = (uint16_t)(59); + _curvea0[83] = _11368; + uint16_t _11369 = (uint16_t)(60); + _curvea0[84] = _11369; + uint16_t _11370 = (uint16_t)(60); + _curvea0[85] = _11370; + uint16_t _11371 = (uint16_t)(61); + _curvea0[86] = _11371; + uint16_t _11372 = (uint16_t)(61); + _curvea0[87] = _11372; + uint16_t _11373 = (uint16_t)(62); + _curvea0[88] = _11373; + uint16_t _11374 = (uint16_t)(62); + _curvea0[89] = _11374; + uint16_t _11375 = (uint16_t)(63); + _curvea0[90] = _11375; + uint16_t _11376 = (uint16_t)(63); + _curvea0[91] = _11376; + uint16_t _11377 = (uint16_t)(64); + _curvea0[92] = _11377; + uint16_t _11378 = (uint16_t)(64); + _curvea0[93] = _11378; + uint16_t _11379 = (uint16_t)(64); + _curvea0[94] = _11379; + uint16_t _11380 = (uint16_t)(65); + _curvea0[95] = _11380; + uint16_t _11381 = (uint16_t)(65); + _curvea0[96] = _11381; + uint16_t _11382 = (uint16_t)(66); + _curvea0[97] = _11382; + uint16_t _11383 = (uint16_t)(66); + _curvea0[98] = _11383; + uint16_t _11384 = (uint16_t)(67); + _curvea0[99] = _11384; + uint16_t _11385 = (uint16_t)(67); + _curvea0[100] = _11385; + uint16_t _11386 = (uint16_t)(68); + _curvea0[101] = _11386; + uint16_t _11387 = (uint16_t)(68); + _curvea0[102] = _11387; + uint16_t _11388 = (uint16_t)(68); + _curvea0[103] = _11388; + uint16_t _11389 = (uint16_t)(69); + _curvea0[104] = _11389; + uint16_t _11390 = (uint16_t)(69); + _curvea0[105] = _11390; + uint16_t _11391 = (uint16_t)(70); + _curvea0[106] = _11391; + uint16_t _11392 = (uint16_t)(70); + _curvea0[107] = _11392; + uint16_t _11393 = (uint16_t)(71); + _curvea0[108] = _11393; + uint16_t _11394 = (uint16_t)(71); + _curvea0[109] = _11394; + uint16_t _11395 = (uint16_t)(71); + _curvea0[110] = _11395; + uint16_t _11396 = (uint16_t)(72); + _curvea0[111] = _11396; + uint16_t _11397 = (uint16_t)(72); + _curvea0[112] = _11397; + uint16_t _11398 = (uint16_t)(73); + _curvea0[113] = _11398; + uint16_t _11399 = (uint16_t)(73); + _curvea0[114] = _11399; + uint16_t _11400 = (uint16_t)(74); + _curvea0[115] = _11400; + uint16_t _11401 = (uint16_t)(74); + _curvea0[116] = _11401; + uint16_t _11402 = (uint16_t)(74); + _curvea0[117] = _11402; + uint16_t _11403 = (uint16_t)(75); + _curvea0[118] = _11403; + uint16_t _11404 = (uint16_t)(75); + _curvea0[119] = _11404; + uint16_t _11405 = (uint16_t)(76); + _curvea0[120] = _11405; + uint16_t _11406 = (uint16_t)(76); + _curvea0[121] = _11406; + uint16_t _11407 = (uint16_t)(77); + _curvea0[122] = _11407; + uint16_t _11408 = (uint16_t)(77); + _curvea0[123] = _11408; + uint16_t _11409 = (uint16_t)(77); + _curvea0[124] = _11409; + uint16_t _11410 = (uint16_t)(78); + _curvea0[125] = _11410; + uint16_t _11411 = (uint16_t)(78); + _curvea0[126] = _11411; + uint16_t _11412 = (uint16_t)(79); + _curvea0[127] = _11412; + uint16_t _11413 = (uint16_t)(79); + _curvea0[128] = _11413; + uint16_t _11414 = (uint16_t)(79); + _curvea0[129] = _11414; + uint16_t _11415 = (uint16_t)(80); + _curvea0[130] = _11415; + uint16_t _11416 = (uint16_t)(80); + _curvea0[131] = _11416; + uint16_t _11417 = (uint16_t)(81); + _curvea0[132] = _11417; + uint16_t _11418 = (uint16_t)(81); + _curvea0[133] = _11418; + uint16_t _11419 = (uint16_t)(82); + _curvea0[134] = _11419; + uint16_t _11420 = (uint16_t)(82); + _curvea0[135] = _11420; + uint16_t _11421 = (uint16_t)(82); + _curvea0[136] = _11421; + uint16_t _11422 = (uint16_t)(83); + _curvea0[137] = _11422; + uint16_t _11423 = (uint16_t)(83); + _curvea0[138] = _11423; + uint16_t _11424 = (uint16_t)(84); + _curvea0[139] = _11424; + uint16_t _11425 = (uint16_t)(84); + _curvea0[140] = _11425; + uint16_t _11426 = (uint16_t)(84); + _curvea0[141] = _11426; + uint16_t _11427 = (uint16_t)(85); + _curvea0[142] = _11427; + uint16_t _11428 = (uint16_t)(85); + _curvea0[143] = _11428; + uint16_t _11429 = (uint16_t)(86); + _curvea0[144] = _11429; + uint16_t _11430 = (uint16_t)(86); + _curvea0[145] = _11430; + uint16_t _11431 = (uint16_t)(86); + _curvea0[146] = _11431; + uint16_t _11432 = (uint16_t)(87); + _curvea0[147] = _11432; + uint16_t _11433 = (uint16_t)(87); + _curvea0[148] = _11433; + uint16_t _11434 = (uint16_t)(88); + _curvea0[149] = _11434; + uint16_t _11435 = (uint16_t)(88); + _curvea0[150] = _11435; + uint16_t _11436 = (uint16_t)(88); + _curvea0[151] = _11436; + uint16_t _11437 = (uint16_t)(89); + _curvea0[152] = _11437; + uint16_t _11438 = (uint16_t)(89); + _curvea0[153] = _11438; + uint16_t _11439 = (uint16_t)(90); + _curvea0[154] = _11439; + uint16_t _11440 = (uint16_t)(90); + _curvea0[155] = _11440; + uint16_t _11441 = (uint16_t)(90); + _curvea0[156] = _11441; + uint16_t _11442 = (uint16_t)(91); + _curvea0[157] = _11442; + uint16_t _11443 = (uint16_t)(91); + _curvea0[158] = _11443; + uint16_t _11444 = (uint16_t)(92); + _curvea0[159] = _11444; + uint16_t _11445 = (uint16_t)(92); + _curvea0[160] = _11445; + uint16_t _11446 = (uint16_t)(92); + _curvea0[161] = _11446; + uint16_t _11447 = (uint16_t)(93); + _curvea0[162] = _11447; + uint16_t _11448 = (uint16_t)(93); + _curvea0[163] = _11448; + uint16_t _11449 = (uint16_t)(93); + _curvea0[164] = _11449; + uint16_t _11450 = (uint16_t)(94); + _curvea0[165] = _11450; + uint16_t _11451 = (uint16_t)(94); + _curvea0[166] = _11451; + uint16_t _11452 = (uint16_t)(95); + _curvea0[167] = _11452; + uint16_t _11453 = (uint16_t)(95); + _curvea0[168] = _11453; + uint16_t _11454 = (uint16_t)(95); + _curvea0[169] = _11454; + uint16_t _11455 = (uint16_t)(96); + _curvea0[170] = _11455; + uint16_t _11456 = (uint16_t)(96); + _curvea0[171] = _11456; + uint16_t _11457 = (uint16_t)(97); + _curvea0[172] = _11457; + uint16_t _11458 = (uint16_t)(97); + _curvea0[173] = _11458; + uint16_t _11459 = (uint16_t)(97); + _curvea0[174] = _11459; + uint16_t _11460 = (uint16_t)(98); + _curvea0[175] = _11460; + uint16_t _11461 = (uint16_t)(98); + _curvea0[176] = _11461; + uint16_t _11462 = (uint16_t)(99); + _curvea0[177] = _11462; + uint16_t _11463 = (uint16_t)(99); + _curvea0[178] = _11463; + uint16_t _11464 = (uint16_t)(99); + _curvea0[179] = _11464; + uint16_t _11465 = (uint16_t)(100); + _curvea0[180] = _11465; + uint16_t _11466 = (uint16_t)(100); + _curvea0[181] = _11466; + uint16_t _11467 = (uint16_t)(100); + _curvea0[182] = _11467; + uint16_t _11468 = (uint16_t)(101); + _curvea0[183] = _11468; + uint16_t _11469 = (uint16_t)(101); + _curvea0[184] = _11469; + uint16_t _11470 = (uint16_t)(102); + _curvea0[185] = _11470; + uint16_t _11471 = (uint16_t)(102); + _curvea0[186] = _11471; + uint16_t _11472 = (uint16_t)(102); + _curvea0[187] = _11472; + uint16_t _11473 = (uint16_t)(103); + _curvea0[188] = _11473; + uint16_t _11474 = (uint16_t)(103); + _curvea0[189] = _11474; + uint16_t _11475 = (uint16_t)(103); + _curvea0[190] = _11475; + uint16_t _11476 = (uint16_t)(104); + _curvea0[191] = _11476; + uint16_t _11477 = (uint16_t)(104); + _curvea0[192] = _11477; + uint16_t _11478 = (uint16_t)(105); + _curvea0[193] = _11478; + uint16_t _11479 = (uint16_t)(105); + _curvea0[194] = _11479; + uint16_t _11480 = (uint16_t)(105); + _curvea0[195] = _11480; + uint16_t _11481 = (uint16_t)(106); + _curvea0[196] = _11481; + uint16_t _11482 = (uint16_t)(106); + _curvea0[197] = _11482; + uint16_t _11483 = (uint16_t)(106); + _curvea0[198] = _11483; + uint16_t _11484 = (uint16_t)(107); + _curvea0[199] = _11484; + uint16_t _11485 = (uint16_t)(107); + _curvea0[200] = _11485; + uint16_t _11486 = (uint16_t)(108); + _curvea0[201] = _11486; + uint16_t _11487 = (uint16_t)(108); + _curvea0[202] = _11487; + uint16_t _11488 = (uint16_t)(108); + _curvea0[203] = _11488; + uint16_t _11489 = (uint16_t)(109); + _curvea0[204] = _11489; + uint16_t _11490 = (uint16_t)(109); + _curvea0[205] = _11490; + uint16_t _11491 = (uint16_t)(109); + _curvea0[206] = _11491; + uint16_t _11492 = (uint16_t)(110); + _curvea0[207] = _11492; + uint16_t _11493 = (uint16_t)(110); + _curvea0[208] = _11493; + uint16_t _11494 = (uint16_t)(111); + _curvea0[209] = _11494; + uint16_t _11495 = (uint16_t)(111); + _curvea0[210] = _11495; + uint16_t _11496 = (uint16_t)(111); + _curvea0[211] = _11496; + uint16_t _11497 = (uint16_t)(112); + _curvea0[212] = _11497; + uint16_t _11498 = (uint16_t)(112); + _curvea0[213] = _11498; + uint16_t _11499 = (uint16_t)(112); + _curvea0[214] = _11499; + uint16_t _11500 = (uint16_t)(113); + _curvea0[215] = _11500; + uint16_t _11501 = (uint16_t)(113); + _curvea0[216] = _11501; + uint16_t _11502 = (uint16_t)(113); + _curvea0[217] = _11502; + uint16_t _11503 = (uint16_t)(114); + _curvea0[218] = _11503; + uint16_t _11504 = (uint16_t)(114); + _curvea0[219] = _11504; + uint16_t _11505 = (uint16_t)(115); + _curvea0[220] = _11505; + uint16_t _11506 = (uint16_t)(115); + _curvea0[221] = _11506; + uint16_t _11507 = (uint16_t)(115); + _curvea0[222] = _11507; + uint16_t _11508 = (uint16_t)(116); + _curvea0[223] = _11508; + uint16_t _11509 = (uint16_t)(116); + _curvea0[224] = _11509; + uint16_t _11510 = (uint16_t)(116); + _curvea0[225] = _11510; + uint16_t _11511 = (uint16_t)(117); + _curvea0[226] = _11511; + uint16_t _11512 = (uint16_t)(117); + _curvea0[227] = _11512; + uint16_t _11513 = (uint16_t)(117); + _curvea0[228] = _11513; + uint16_t _11514 = (uint16_t)(118); + _curvea0[229] = _11514; + uint16_t _11515 = (uint16_t)(118); + _curvea0[230] = _11515; + uint16_t _11516 = (uint16_t)(119); + _curvea0[231] = _11516; + uint16_t _11517 = (uint16_t)(119); + _curvea0[232] = _11517; + uint16_t _11518 = (uint16_t)(119); + _curvea0[233] = _11518; + uint16_t _11519 = (uint16_t)(120); + _curvea0[234] = _11519; + uint16_t _11520 = (uint16_t)(120); + _curvea0[235] = _11520; + uint16_t _11521 = (uint16_t)(120); + _curvea0[236] = _11521; + uint16_t _11522 = (uint16_t)(121); + _curvea0[237] = _11522; + uint16_t _11523 = (uint16_t)(121); + _curvea0[238] = _11523; + uint16_t _11524 = (uint16_t)(121); + _curvea0[239] = _11524; + uint16_t _11525 = (uint16_t)(122); + _curvea0[240] = _11525; + uint16_t _11526 = (uint16_t)(122); + _curvea0[241] = _11526; + uint16_t _11527 = (uint16_t)(123); + _curvea0[242] = _11527; + uint16_t _11528 = (uint16_t)(123); + _curvea0[243] = _11528; + uint16_t _11529 = (uint16_t)(123); + _curvea0[244] = _11529; + uint16_t _11530 = (uint16_t)(124); + _curvea0[245] = _11530; + uint16_t _11531 = (uint16_t)(124); + _curvea0[246] = _11531; + uint16_t _11532 = (uint16_t)(124); + _curvea0[247] = _11532; + uint16_t _11533 = (uint16_t)(125); + _curvea0[248] = _11533; + uint16_t _11534 = (uint16_t)(125); + _curvea0[249] = _11534; + uint16_t _11535 = (uint16_t)(125); + _curvea0[250] = _11535; + uint16_t _11536 = (uint16_t)(126); + _curvea0[251] = _11536; + uint16_t _11537 = (uint16_t)(126); + _curvea0[252] = _11537; + uint16_t _11538 = (uint16_t)(126); + _curvea0[253] = _11538; + uint16_t _11539 = (uint16_t)(127); + _curvea0[254] = _11539; + uint16_t _11540 = (uint16_t)(127); + _curvea0[255] = _11540; + uint16_t _11541 = (uint16_t)(128); + _curvea0[256] = _11541; + uint16_t _11542 = (uint16_t)(128); + _curvea0[257] = _11542; + uint16_t _11543 = (uint16_t)(128); + _curvea0[258] = _11543; + uint16_t _11544 = (uint16_t)(129); + _curvea0[259] = _11544; + uint16_t _11545 = (uint16_t)(129); + _curvea0[260] = _11545; + uint16_t _11546 = (uint16_t)(129); + _curvea0[261] = _11546; + uint16_t _11547 = (uint16_t)(130); + _curvea0[262] = _11547; + uint16_t _11548 = (uint16_t)(130); + _curvea0[263] = _11548; + uint16_t _11549 = (uint16_t)(130); + _curvea0[264] = _11549; + uint16_t _11550 = (uint16_t)(131); + _curvea0[265] = _11550; + uint16_t _11551 = (uint16_t)(131); + _curvea0[266] = _11551; + uint16_t _11552 = (uint16_t)(131); + _curvea0[267] = _11552; + uint16_t _11553 = (uint16_t)(132); + _curvea0[268] = _11553; + uint16_t _11554 = (uint16_t)(132); + _curvea0[269] = _11554; + uint16_t _11555 = (uint16_t)(132); + _curvea0[270] = _11555; + uint16_t _11556 = (uint16_t)(133); + _curvea0[271] = _11556; + uint16_t _11557 = (uint16_t)(133); + _curvea0[272] = _11557; + uint16_t _11558 = (uint16_t)(133); + _curvea0[273] = _11558; + uint16_t _11559 = (uint16_t)(134); + _curvea0[274] = _11559; + uint16_t _11560 = (uint16_t)(134); + _curvea0[275] = _11560; + uint16_t _11561 = (uint16_t)(134); + _curvea0[276] = _11561; + uint16_t _11562 = (uint16_t)(135); + _curvea0[277] = _11562; + uint16_t _11563 = (uint16_t)(135); + _curvea0[278] = _11563; + uint16_t _11564 = (uint16_t)(135); + _curvea0[279] = _11564; + uint16_t _11565 = (uint16_t)(136); + _curvea0[280] = _11565; + uint16_t _11566 = (uint16_t)(136); + _curvea0[281] = _11566; + uint16_t _11567 = (uint16_t)(136); + _curvea0[282] = _11567; + uint16_t _11568 = (uint16_t)(137); + _curvea0[283] = _11568; + uint16_t _11569 = (uint16_t)(137); + _curvea0[284] = _11569; + uint16_t _11570 = (uint16_t)(137); + _curvea0[285] = _11570; + uint16_t _11571 = (uint16_t)(138); + _curvea0[286] = _11571; + uint16_t _11572 = (uint16_t)(138); + _curvea0[287] = _11572; + uint16_t _11573 = (uint16_t)(138); + _curvea0[288] = _11573; + uint16_t _11574 = (uint16_t)(139); + _curvea0[289] = _11574; + uint16_t _11575 = (uint16_t)(139); + _curvea0[290] = _11575; + uint16_t _11576 = (uint16_t)(139); + _curvea0[291] = _11576; + uint16_t _11577 = (uint16_t)(140); + _curvea0[292] = _11577; + uint16_t _11578 = (uint16_t)(140); + _curvea0[293] = _11578; + uint16_t _11579 = (uint16_t)(140); + _curvea0[294] = _11579; + uint16_t _11580 = (uint16_t)(141); + _curvea0[295] = _11580; + uint16_t _11581 = (uint16_t)(141); + _curvea0[296] = _11581; + uint16_t _11582 = (uint16_t)(141); + _curvea0[297] = _11582; + uint16_t _11583 = (uint16_t)(141); + _curvea0[298] = _11583; + uint16_t _11584 = (uint16_t)(142); + _curvea0[299] = _11584; + uint16_t _11585 = (uint16_t)(142); + _curvea0[300] = _11585; + uint16_t _11586 = (uint16_t)(142); + _curvea0[301] = _11586; + uint16_t _11587 = (uint16_t)(143); + _curvea0[302] = _11587; + uint16_t _11588 = (uint16_t)(143); + _curvea0[303] = _11588; + uint16_t _11589 = (uint16_t)(143); + _curvea0[304] = _11589; + uint16_t _11590 = (uint16_t)(144); + _curvea0[305] = _11590; + uint16_t _11591 = (uint16_t)(144); + _curvea0[306] = _11591; + uint16_t _11592 = (uint16_t)(144); + _curvea0[307] = _11592; + uint16_t _11593 = (uint16_t)(145); + _curvea0[308] = _11593; + uint16_t _11594 = (uint16_t)(145); + _curvea0[309] = _11594; + uint16_t _11595 = (uint16_t)(145); + _curvea0[310] = _11595; + uint16_t _11596 = (uint16_t)(145); + _curvea0[311] = _11596; + uint16_t _11597 = (uint16_t)(146); + _curvea0[312] = _11597; + uint16_t _11598 = (uint16_t)(146); + _curvea0[313] = _11598; + uint16_t _11599 = (uint16_t)(146); + _curvea0[314] = _11599; + uint16_t _11600 = (uint16_t)(147); + _curvea0[315] = _11600; + uint16_t _11601 = (uint16_t)(147); + _curvea0[316] = _11601; + uint16_t _11602 = (uint16_t)(147); + _curvea0[317] = _11602; + uint16_t _11603 = (uint16_t)(148); + _curvea0[318] = _11603; + uint16_t _11604 = (uint16_t)(148); + _curvea0[319] = _11604; + uint16_t _11605 = (uint16_t)(148); + _curvea0[320] = _11605; + uint16_t _11606 = (uint16_t)(148); + _curvea0[321] = _11606; + uint16_t _11607 = (uint16_t)(149); + _curvea0[322] = _11607; + uint16_t _11608 = (uint16_t)(149); + _curvea0[323] = _11608; + uint16_t _11609 = (uint16_t)(149); + _curvea0[324] = _11609; + uint16_t _11610 = (uint16_t)(150); + _curvea0[325] = _11610; + uint16_t _11611 = (uint16_t)(150); + _curvea0[326] = _11611; + uint16_t _11612 = (uint16_t)(150); + _curvea0[327] = _11612; + uint16_t _11613 = (uint16_t)(150); + _curvea0[328] = _11613; + uint16_t _11614 = (uint16_t)(151); + _curvea0[329] = _11614; + uint16_t _11615 = (uint16_t)(151); + _curvea0[330] = _11615; + uint16_t _11616 = (uint16_t)(151); + _curvea0[331] = _11616; + uint16_t _11617 = (uint16_t)(152); + _curvea0[332] = _11617; + uint16_t _11618 = (uint16_t)(152); + _curvea0[333] = _11618; + uint16_t _11619 = (uint16_t)(152); + _curvea0[334] = _11619; + uint16_t _11620 = (uint16_t)(152); + _curvea0[335] = _11620; + uint16_t _11621 = (uint16_t)(153); + _curvea0[336] = _11621; + uint16_t _11622 = (uint16_t)(153); + _curvea0[337] = _11622; + uint16_t _11623 = (uint16_t)(153); + _curvea0[338] = _11623; + uint16_t _11624 = (uint16_t)(154); + _curvea0[339] = _11624; + uint16_t _11625 = (uint16_t)(154); + _curvea0[340] = _11625; + uint16_t _11626 = (uint16_t)(154); + _curvea0[341] = _11626; + uint16_t _11627 = (uint16_t)(154); + _curvea0[342] = _11627; + uint16_t _11628 = (uint16_t)(155); + _curvea0[343] = _11628; + uint16_t _11629 = (uint16_t)(155); + _curvea0[344] = _11629; + uint16_t _11630 = (uint16_t)(155); + _curvea0[345] = _11630; + uint16_t _11631 = (uint16_t)(156); + _curvea0[346] = _11631; + uint16_t _11632 = (uint16_t)(156); + _curvea0[347] = _11632; + uint16_t _11633 = (uint16_t)(156); + _curvea0[348] = _11633; + uint16_t _11634 = (uint16_t)(156); + _curvea0[349] = _11634; + uint16_t _11635 = (uint16_t)(157); + _curvea0[350] = _11635; + uint16_t _11636 = (uint16_t)(157); + _curvea0[351] = _11636; + uint16_t _11637 = (uint16_t)(157); + _curvea0[352] = _11637; + uint16_t _11638 = (uint16_t)(157); + _curvea0[353] = _11638; + uint16_t _11639 = (uint16_t)(158); + _curvea0[354] = _11639; + uint16_t _11640 = (uint16_t)(158); + _curvea0[355] = _11640; + uint16_t _11641 = (uint16_t)(158); + _curvea0[356] = _11641; + uint16_t _11642 = (uint16_t)(159); + _curvea0[357] = _11642; + uint16_t _11643 = (uint16_t)(159); + _curvea0[358] = _11643; + uint16_t _11644 = (uint16_t)(159); + _curvea0[359] = _11644; + uint16_t _11645 = (uint16_t)(159); + _curvea0[360] = _11645; + uint16_t _11646 = (uint16_t)(160); + _curvea0[361] = _11646; + uint16_t _11647 = (uint16_t)(160); + _curvea0[362] = _11647; + uint16_t _11648 = (uint16_t)(160); + _curvea0[363] = _11648; + uint16_t _11649 = (uint16_t)(160); + _curvea0[364] = _11649; + uint16_t _11650 = (uint16_t)(161); + _curvea0[365] = _11650; + uint16_t _11651 = (uint16_t)(161); + _curvea0[366] = _11651; + uint16_t _11652 = (uint16_t)(161); + _curvea0[367] = _11652; + uint16_t _11653 = (uint16_t)(161); + _curvea0[368] = _11653; + uint16_t _11654 = (uint16_t)(162); + _curvea0[369] = _11654; + uint16_t _11655 = (uint16_t)(162); + _curvea0[370] = _11655; + uint16_t _11656 = (uint16_t)(162); + _curvea0[371] = _11656; + uint16_t _11657 = (uint16_t)(162); + _curvea0[372] = _11657; + uint16_t _11658 = (uint16_t)(163); + _curvea0[373] = _11658; + uint16_t _11659 = (uint16_t)(163); + _curvea0[374] = _11659; + uint16_t _11660 = (uint16_t)(163); + _curvea0[375] = _11660; + uint16_t _11661 = (uint16_t)(163); + _curvea0[376] = _11661; + uint16_t _11662 = (uint16_t)(164); + _curvea0[377] = _11662; + uint16_t _11663 = (uint16_t)(164); + _curvea0[378] = _11663; + uint16_t _11664 = (uint16_t)(164); + _curvea0[379] = _11664; + uint16_t _11665 = (uint16_t)(164); + _curvea0[380] = _11665; + uint16_t _11666 = (uint16_t)(165); + _curvea0[381] = _11666; + uint16_t _11667 = (uint16_t)(165); + _curvea0[382] = _11667; + uint16_t _11668 = (uint16_t)(165); + _curvea0[383] = _11668; + uint16_t _11669 = (uint16_t)(166); + _curvea0[384] = _11669; + uint16_t _11670 = (uint16_t)(166); + _curvea0[385] = _11670; + uint16_t _11671 = (uint16_t)(166); + _curvea0[386] = _11671; + uint16_t _11672 = (uint16_t)(166); + _curvea0[387] = _11672; + uint16_t _11673 = (uint16_t)(167); + _curvea0[388] = _11673; + uint16_t _11674 = (uint16_t)(167); + _curvea0[389] = _11674; + uint16_t _11675 = (uint16_t)(167); + _curvea0[390] = _11675; + uint16_t _11676 = (uint16_t)(167); + _curvea0[391] = _11676; + uint16_t _11677 = (uint16_t)(167); + _curvea0[392] = _11677; + uint16_t _11678 = (uint16_t)(168); + _curvea0[393] = _11678; + uint16_t _11679 = (uint16_t)(168); + _curvea0[394] = _11679; + uint16_t _11680 = (uint16_t)(168); + _curvea0[395] = _11680; + uint16_t _11681 = (uint16_t)(168); + _curvea0[396] = _11681; + uint16_t _11682 = (uint16_t)(169); + _curvea0[397] = _11682; + uint16_t _11683 = (uint16_t)(169); + _curvea0[398] = _11683; + uint16_t _11684 = (uint16_t)(169); + _curvea0[399] = _11684; + uint16_t _11685 = (uint16_t)(169); + _curvea0[400] = _11685; + uint16_t _11686 = (uint16_t)(170); + _curvea0[401] = _11686; + uint16_t _11687 = (uint16_t)(170); + _curvea0[402] = _11687; + uint16_t _11688 = (uint16_t)(170); + _curvea0[403] = _11688; + uint16_t _11689 = (uint16_t)(170); + _curvea0[404] = _11689; + uint16_t _11690 = (uint16_t)(171); + _curvea0[405] = _11690; + uint16_t _11691 = (uint16_t)(171); + _curvea0[406] = _11691; + uint16_t _11692 = (uint16_t)(171); + _curvea0[407] = _11692; + uint16_t _11693 = (uint16_t)(171); + _curvea0[408] = _11693; + uint16_t _11694 = (uint16_t)(172); + _curvea0[409] = _11694; + uint16_t _11695 = (uint16_t)(172); + _curvea0[410] = _11695; + uint16_t _11696 = (uint16_t)(172); + _curvea0[411] = _11696; + uint16_t _11697 = (uint16_t)(172); + _curvea0[412] = _11697; + uint16_t _11698 = (uint16_t)(173); + _curvea0[413] = _11698; + uint16_t _11699 = (uint16_t)(173); + _curvea0[414] = _11699; + uint16_t _11700 = (uint16_t)(173); + _curvea0[415] = _11700; + uint16_t _11701 = (uint16_t)(173); + _curvea0[416] = _11701; + uint16_t _11702 = (uint16_t)(173); + _curvea0[417] = _11702; + uint16_t _11703 = (uint16_t)(174); + _curvea0[418] = _11703; + uint16_t _11704 = (uint16_t)(174); + _curvea0[419] = _11704; + uint16_t _11705 = (uint16_t)(174); + _curvea0[420] = _11705; + uint16_t _11706 = (uint16_t)(174); + _curvea0[421] = _11706; + uint16_t _11707 = (uint16_t)(175); + _curvea0[422] = _11707; + uint16_t _11708 = (uint16_t)(175); + _curvea0[423] = _11708; + uint16_t _11709 = (uint16_t)(175); + _curvea0[424] = _11709; + uint16_t _11710 = (uint16_t)(175); + _curvea0[425] = _11710; + uint16_t _11711 = (uint16_t)(176); + _curvea0[426] = _11711; + uint16_t _11712 = (uint16_t)(176); + _curvea0[427] = _11712; + uint16_t _11713 = (uint16_t)(176); + _curvea0[428] = _11713; + uint16_t _11714 = (uint16_t)(176); + _curvea0[429] = _11714; + uint16_t _11715 = (uint16_t)(176); + _curvea0[430] = _11715; + uint16_t _11716 = (uint16_t)(177); + _curvea0[431] = _11716; + uint16_t _11717 = (uint16_t)(177); + _curvea0[432] = _11717; + uint16_t _11718 = (uint16_t)(177); + _curvea0[433] = _11718; + uint16_t _11719 = (uint16_t)(177); + _curvea0[434] = _11719; + uint16_t _11720 = (uint16_t)(178); + _curvea0[435] = _11720; + uint16_t _11721 = (uint16_t)(178); + _curvea0[436] = _11721; + uint16_t _11722 = (uint16_t)(178); + _curvea0[437] = _11722; + uint16_t _11723 = (uint16_t)(178); + _curvea0[438] = _11723; + uint16_t _11724 = (uint16_t)(178); + _curvea0[439] = _11724; + uint16_t _11725 = (uint16_t)(179); + _curvea0[440] = _11725; + uint16_t _11726 = (uint16_t)(179); + _curvea0[441] = _11726; + uint16_t _11727 = (uint16_t)(179); + _curvea0[442] = _11727; + uint16_t _11728 = (uint16_t)(179); + _curvea0[443] = _11728; + uint16_t _11729 = (uint16_t)(180); + _curvea0[444] = _11729; + uint16_t _11730 = (uint16_t)(180); + _curvea0[445] = _11730; + uint16_t _11731 = (uint16_t)(180); + _curvea0[446] = _11731; + uint16_t _11732 = (uint16_t)(180); + _curvea0[447] = _11732; + uint16_t _11733 = (uint16_t)(180); + _curvea0[448] = _11733; + uint16_t _11734 = (uint16_t)(181); + _curvea0[449] = _11734; + uint16_t _11735 = (uint16_t)(181); + _curvea0[450] = _11735; + uint16_t _11736 = (uint16_t)(181); + _curvea0[451] = _11736; + uint16_t _11737 = (uint16_t)(181); + _curvea0[452] = _11737; + uint16_t _11738 = (uint16_t)(181); + _curvea0[453] = _11738; + uint16_t _11739 = (uint16_t)(182); + _curvea0[454] = _11739; + uint16_t _11740 = (uint16_t)(182); + _curvea0[455] = _11740; + uint16_t _11741 = (uint16_t)(182); + _curvea0[456] = _11741; + uint16_t _11742 = (uint16_t)(182); + _curvea0[457] = _11742; + uint16_t _11743 = (uint16_t)(183); + _curvea0[458] = _11743; + uint16_t _11744 = (uint16_t)(183); + _curvea0[459] = _11744; + uint16_t _11745 = (uint16_t)(183); + _curvea0[460] = _11745; + uint16_t _11746 = (uint16_t)(183); + _curvea0[461] = _11746; + uint16_t _11747 = (uint16_t)(183); + _curvea0[462] = _11747; + uint16_t _11748 = (uint16_t)(184); + _curvea0[463] = _11748; + uint16_t _11749 = (uint16_t)(184); + _curvea0[464] = _11749; + uint16_t _11750 = (uint16_t)(184); + _curvea0[465] = _11750; + uint16_t _11751 = (uint16_t)(184); + _curvea0[466] = _11751; + uint16_t _11752 = (uint16_t)(184); + _curvea0[467] = _11752; + uint16_t _11753 = (uint16_t)(185); + _curvea0[468] = _11753; + uint16_t _11754 = (uint16_t)(185); + _curvea0[469] = _11754; + uint16_t _11755 = (uint16_t)(185); + _curvea0[470] = _11755; + uint16_t _11756 = (uint16_t)(185); + _curvea0[471] = _11756; + uint16_t _11757 = (uint16_t)(185); + _curvea0[472] = _11757; + uint16_t _11758 = (uint16_t)(186); + _curvea0[473] = _11758; + uint16_t _11759 = (uint16_t)(186); + _curvea0[474] = _11759; + uint16_t _11760 = (uint16_t)(186); + _curvea0[475] = _11760; + uint16_t _11761 = (uint16_t)(186); + _curvea0[476] = _11761; + uint16_t _11762 = (uint16_t)(187); + _curvea0[477] = _11762; + uint16_t _11763 = (uint16_t)(187); + _curvea0[478] = _11763; + uint16_t _11764 = (uint16_t)(187); + _curvea0[479] = _11764; + uint16_t _11765 = (uint16_t)(187); + _curvea0[480] = _11765; + uint16_t _11766 = (uint16_t)(187); + _curvea0[481] = _11766; + uint16_t _11767 = (uint16_t)(188); + _curvea0[482] = _11767; + uint16_t _11768 = (uint16_t)(188); + _curvea0[483] = _11768; + uint16_t _11769 = (uint16_t)(188); + _curvea0[484] = _11769; + uint16_t _11770 = (uint16_t)(188); + _curvea0[485] = _11770; + uint16_t _11771 = (uint16_t)(188); + _curvea0[486] = _11771; + uint16_t _11772 = (uint16_t)(189); + _curvea0[487] = _11772; + uint16_t _11773 = (uint16_t)(189); + _curvea0[488] = _11773; + uint16_t _11774 = (uint16_t)(189); + _curvea0[489] = _11774; + uint16_t _11775 = (uint16_t)(189); + _curvea0[490] = _11775; + uint16_t _11776 = (uint16_t)(189); + _curvea0[491] = _11776; + uint16_t _11777 = (uint16_t)(190); + _curvea0[492] = _11777; + uint16_t _11778 = (uint16_t)(190); + _curvea0[493] = _11778; + uint16_t _11779 = (uint16_t)(190); + _curvea0[494] = _11779; + uint16_t _11780 = (uint16_t)(190); + _curvea0[495] = _11780; + uint16_t _11781 = (uint16_t)(190); + _curvea0[496] = _11781; + uint16_t _11782 = (uint16_t)(190); + _curvea0[497] = _11782; + uint16_t _11783 = (uint16_t)(191); + _curvea0[498] = _11783; + uint16_t _11784 = (uint16_t)(191); + _curvea0[499] = _11784; + uint16_t _11785 = (uint16_t)(191); + _curvea0[500] = _11785; + uint16_t _11786 = (uint16_t)(191); + _curvea0[501] = _11786; + uint16_t _11787 = (uint16_t)(191); + _curvea0[502] = _11787; + uint16_t _11788 = (uint16_t)(192); + _curvea0[503] = _11788; + uint16_t _11789 = (uint16_t)(192); + _curvea0[504] = _11789; + uint16_t _11790 = (uint16_t)(192); + _curvea0[505] = _11790; + uint16_t _11791 = (uint16_t)(192); + _curvea0[506] = _11791; + uint16_t _11792 = (uint16_t)(192); + _curvea0[507] = _11792; + uint16_t _11793 = (uint16_t)(193); + _curvea0[508] = _11793; + uint16_t _11794 = (uint16_t)(193); + _curvea0[509] = _11794; + uint16_t _11795 = (uint16_t)(193); + _curvea0[510] = _11795; + uint16_t _11796 = (uint16_t)(193); + _curvea0[511] = _11796; + uint16_t _11797 = (uint16_t)(193); + _curvea0[512] = _11797; + uint16_t _11798 = (uint16_t)(194); + _curvea0[513] = _11798; + uint16_t _11799 = (uint16_t)(194); + _curvea0[514] = _11799; + uint16_t _11800 = (uint16_t)(194); + _curvea0[515] = _11800; + uint16_t _11801 = (uint16_t)(194); + _curvea0[516] = _11801; + uint16_t _11802 = (uint16_t)(194); + _curvea0[517] = _11802; + uint16_t _11803 = (uint16_t)(195); + _curvea0[518] = _11803; + uint16_t _11804 = (uint16_t)(195); + _curvea0[519] = _11804; + uint16_t _11805 = (uint16_t)(195); + _curvea0[520] = _11805; + uint16_t _11806 = (uint16_t)(195); + _curvea0[521] = _11806; + uint16_t _11807 = (uint16_t)(195); + _curvea0[522] = _11807; + uint16_t _11808 = (uint16_t)(195); + _curvea0[523] = _11808; + uint16_t _11809 = (uint16_t)(196); + _curvea0[524] = _11809; + uint16_t _11810 = (uint16_t)(196); + _curvea0[525] = _11810; + uint16_t _11811 = (uint16_t)(196); + _curvea0[526] = _11811; + uint16_t _11812 = (uint16_t)(196); + _curvea0[527] = _11812; + uint16_t _11813 = (uint16_t)(196); + _curvea0[528] = _11813; + uint16_t _11814 = (uint16_t)(197); + _curvea0[529] = _11814; + uint16_t _11815 = (uint16_t)(197); + _curvea0[530] = _11815; + uint16_t _11816 = (uint16_t)(197); + _curvea0[531] = _11816; + uint16_t _11817 = (uint16_t)(197); + _curvea0[532] = _11817; + uint16_t _11818 = (uint16_t)(197); + _curvea0[533] = _11818; + uint16_t _11819 = (uint16_t)(197); + _curvea0[534] = _11819; + uint16_t _11820 = (uint16_t)(198); + _curvea0[535] = _11820; + uint16_t _11821 = (uint16_t)(198); + _curvea0[536] = _11821; + uint16_t _11822 = (uint16_t)(198); + _curvea0[537] = _11822; + uint16_t _11823 = (uint16_t)(198); + _curvea0[538] = _11823; + uint16_t _11824 = (uint16_t)(198); + _curvea0[539] = _11824; + uint16_t _11825 = (uint16_t)(199); + _curvea0[540] = _11825; + uint16_t _11826 = (uint16_t)(199); + _curvea0[541] = _11826; + uint16_t _11827 = (uint16_t)(199); + _curvea0[542] = _11827; + uint16_t _11828 = (uint16_t)(199); + _curvea0[543] = _11828; + uint16_t _11829 = (uint16_t)(199); + _curvea0[544] = _11829; + uint16_t _11830 = (uint16_t)(199); + _curvea0[545] = _11830; + uint16_t _11831 = (uint16_t)(200); + _curvea0[546] = _11831; + uint16_t _11832 = (uint16_t)(200); + _curvea0[547] = _11832; + uint16_t _11833 = (uint16_t)(200); + _curvea0[548] = _11833; + uint16_t _11834 = (uint16_t)(200); + _curvea0[549] = _11834; + uint16_t _11835 = (uint16_t)(200); + _curvea0[550] = _11835; + uint16_t _11836 = (uint16_t)(200); + _curvea0[551] = _11836; + uint16_t _11837 = (uint16_t)(201); + _curvea0[552] = _11837; + uint16_t _11838 = (uint16_t)(201); + _curvea0[553] = _11838; + uint16_t _11839 = (uint16_t)(201); + _curvea0[554] = _11839; + uint16_t _11840 = (uint16_t)(201); + _curvea0[555] = _11840; + uint16_t _11841 = (uint16_t)(201); + _curvea0[556] = _11841; + uint16_t _11842 = (uint16_t)(202); + _curvea0[557] = _11842; + uint16_t _11843 = (uint16_t)(202); + _curvea0[558] = _11843; + uint16_t _11844 = (uint16_t)(202); + _curvea0[559] = _11844; + uint16_t _11845 = (uint16_t)(202); + _curvea0[560] = _11845; + uint16_t _11846 = (uint16_t)(202); + _curvea0[561] = _11846; + uint16_t _11847 = (uint16_t)(202); + _curvea0[562] = _11847; + uint16_t _11848 = (uint16_t)(203); + _curvea0[563] = _11848; + uint16_t _11849 = (uint16_t)(203); + _curvea0[564] = _11849; + uint16_t _11850 = (uint16_t)(203); + _curvea0[565] = _11850; + uint16_t _11851 = (uint16_t)(203); + _curvea0[566] = _11851; + uint16_t _11852 = (uint16_t)(203); + _curvea0[567] = _11852; + uint16_t _11853 = (uint16_t)(203); + _curvea0[568] = _11853; + uint16_t _11854 = (uint16_t)(204); + _curvea0[569] = _11854; + uint16_t _11855 = (uint16_t)(204); + _curvea0[570] = _11855; + uint16_t _11856 = (uint16_t)(204); + _curvea0[571] = _11856; + uint16_t _11857 = (uint16_t)(204); + _curvea0[572] = _11857; + uint16_t _11858 = (uint16_t)(204); + _curvea0[573] = _11858; + uint16_t _11859 = (uint16_t)(204); + _curvea0[574] = _11859; + uint16_t _11860 = (uint16_t)(205); + _curvea0[575] = _11860; + uint16_t _11861 = (uint16_t)(205); + _curvea0[576] = _11861; + uint16_t _11862 = (uint16_t)(205); + _curvea0[577] = _11862; + uint16_t _11863 = (uint16_t)(205); + _curvea0[578] = _11863; + uint16_t _11864 = (uint16_t)(205); + _curvea0[579] = _11864; + uint16_t _11865 = (uint16_t)(205); + _curvea0[580] = _11865; + uint16_t _11866 = (uint16_t)(206); + _curvea0[581] = _11866; + uint16_t _11867 = (uint16_t)(206); + _curvea0[582] = _11867; + uint16_t _11868 = (uint16_t)(206); + _curvea0[583] = _11868; + uint16_t _11869 = (uint16_t)(206); + _curvea0[584] = _11869; + uint16_t _11870 = (uint16_t)(206); + _curvea0[585] = _11870; + uint16_t _11871 = (uint16_t)(206); + _curvea0[586] = _11871; + uint16_t _11872 = (uint16_t)(207); + _curvea0[587] = _11872; + uint16_t _11873 = (uint16_t)(207); + _curvea0[588] = _11873; + uint16_t _11874 = (uint16_t)(207); + _curvea0[589] = _11874; + uint16_t _11875 = (uint16_t)(207); + _curvea0[590] = _11875; + uint16_t _11876 = (uint16_t)(207); + _curvea0[591] = _11876; + uint16_t _11877 = (uint16_t)(207); + _curvea0[592] = _11877; + uint16_t _11878 = (uint16_t)(208); + _curvea0[593] = _11878; + uint16_t _11879 = (uint16_t)(208); + _curvea0[594] = _11879; + uint16_t _11880 = (uint16_t)(208); + _curvea0[595] = _11880; + uint16_t _11881 = (uint16_t)(208); + _curvea0[596] = _11881; + uint16_t _11882 = (uint16_t)(208); + _curvea0[597] = _11882; + uint16_t _11883 = (uint16_t)(208); + _curvea0[598] = _11883; + uint16_t _11884 = (uint16_t)(209); + _curvea0[599] = _11884; + uint16_t _11885 = (uint16_t)(209); + _curvea0[600] = _11885; + uint16_t _11886 = (uint16_t)(209); + _curvea0[601] = _11886; + uint16_t _11887 = (uint16_t)(209); + _curvea0[602] = _11887; + uint16_t _11888 = (uint16_t)(209); + _curvea0[603] = _11888; + uint16_t _11889 = (uint16_t)(209); + _curvea0[604] = _11889; + uint16_t _11890 = (uint16_t)(209); + _curvea0[605] = _11890; + uint16_t _11891 = (uint16_t)(210); + _curvea0[606] = _11891; + uint16_t _11892 = (uint16_t)(210); + _curvea0[607] = _11892; + uint16_t _11893 = (uint16_t)(210); + _curvea0[608] = _11893; + uint16_t _11894 = (uint16_t)(210); + _curvea0[609] = _11894; + uint16_t _11895 = (uint16_t)(210); + _curvea0[610] = _11895; + uint16_t _11896 = (uint16_t)(210); + _curvea0[611] = _11896; + uint16_t _11897 = (uint16_t)(211); + _curvea0[612] = _11897; + uint16_t _11898 = (uint16_t)(211); + _curvea0[613] = _11898; + uint16_t _11899 = (uint16_t)(211); + _curvea0[614] = _11899; + uint16_t _11900 = (uint16_t)(211); + _curvea0[615] = _11900; + uint16_t _11901 = (uint16_t)(211); + _curvea0[616] = _11901; + uint16_t _11902 = (uint16_t)(211); + _curvea0[617] = _11902; + uint16_t _11903 = (uint16_t)(211); + _curvea0[618] = _11903; + uint16_t _11904 = (uint16_t)(212); + _curvea0[619] = _11904; + uint16_t _11905 = (uint16_t)(212); + _curvea0[620] = _11905; + uint16_t _11906 = (uint16_t)(212); + _curvea0[621] = _11906; + uint16_t _11907 = (uint16_t)(212); + _curvea0[622] = _11907; + uint16_t _11908 = (uint16_t)(212); + _curvea0[623] = _11908; + uint16_t _11909 = (uint16_t)(212); + _curvea0[624] = _11909; + uint16_t _11910 = (uint16_t)(213); + _curvea0[625] = _11910; + uint16_t _11911 = (uint16_t)(213); + _curvea0[626] = _11911; + uint16_t _11912 = (uint16_t)(213); + _curvea0[627] = _11912; + uint16_t _11913 = (uint16_t)(213); + _curvea0[628] = _11913; + uint16_t _11914 = (uint16_t)(213); + _curvea0[629] = _11914; + uint16_t _11915 = (uint16_t)(213); + _curvea0[630] = _11915; + uint16_t _11916 = (uint16_t)(213); + _curvea0[631] = _11916; + uint16_t _11917 = (uint16_t)(214); + _curvea0[632] = _11917; + uint16_t _11918 = (uint16_t)(214); + _curvea0[633] = _11918; + uint16_t _11919 = (uint16_t)(214); + _curvea0[634] = _11919; + uint16_t _11920 = (uint16_t)(214); + _curvea0[635] = _11920; + uint16_t _11921 = (uint16_t)(214); + _curvea0[636] = _11921; + uint16_t _11922 = (uint16_t)(214); + _curvea0[637] = _11922; + uint16_t _11923 = (uint16_t)(214); + _curvea0[638] = _11923; + uint16_t _11924 = (uint16_t)(215); + _curvea0[639] = _11924; + uint16_t _11925 = (uint16_t)(215); + _curvea0[640] = _11925; + uint16_t _11926 = (uint16_t)(215); + _curvea0[641] = _11926; + uint16_t _11927 = (uint16_t)(215); + _curvea0[642] = _11927; + uint16_t _11928 = (uint16_t)(215); + _curvea0[643] = _11928; + uint16_t _11929 = (uint16_t)(215); + _curvea0[644] = _11929; + uint16_t _11930 = (uint16_t)(216); + _curvea0[645] = _11930; + uint16_t _11931 = (uint16_t)(216); + _curvea0[646] = _11931; + uint16_t _11932 = (uint16_t)(216); + _curvea0[647] = _11932; + uint16_t _11933 = (uint16_t)(216); + _curvea0[648] = _11933; + uint16_t _11934 = (uint16_t)(216); + _curvea0[649] = _11934; + uint16_t _11935 = (uint16_t)(216); + _curvea0[650] = _11935; + uint16_t _11936 = (uint16_t)(216); + _curvea0[651] = _11936; + uint16_t _11937 = (uint16_t)(217); + _curvea0[652] = _11937; + uint16_t _11938 = (uint16_t)(217); + _curvea0[653] = _11938; + uint16_t _11939 = (uint16_t)(217); + _curvea0[654] = _11939; + uint16_t _11940 = (uint16_t)(217); + _curvea0[655] = _11940; + uint16_t _11941 = (uint16_t)(217); + _curvea0[656] = _11941; + uint16_t _11942 = (uint16_t)(217); + _curvea0[657] = _11942; + uint16_t _11943 = (uint16_t)(217); + _curvea0[658] = _11943; + uint16_t _11944 = (uint16_t)(218); + _curvea0[659] = _11944; + uint16_t _11945 = (uint16_t)(218); + _curvea0[660] = _11945; + uint16_t _11946 = (uint16_t)(218); + _curvea0[661] = _11946; + uint16_t _11947 = (uint16_t)(218); + _curvea0[662] = _11947; + uint16_t _11948 = (uint16_t)(218); + _curvea0[663] = _11948; + uint16_t _11949 = (uint16_t)(218); + _curvea0[664] = _11949; + uint16_t _11950 = (uint16_t)(218); + _curvea0[665] = _11950; + uint16_t _11951 = (uint16_t)(219); + _curvea0[666] = _11951; + uint16_t _11952 = (uint16_t)(219); + _curvea0[667] = _11952; + uint16_t _11953 = (uint16_t)(219); + _curvea0[668] = _11953; + uint16_t _11954 = (uint16_t)(219); + _curvea0[669] = _11954; + uint16_t _11955 = (uint16_t)(219); + _curvea0[670] = _11955; + uint16_t _11956 = (uint16_t)(219); + _curvea0[671] = _11956; + uint16_t _11957 = (uint16_t)(219); + _curvea0[672] = _11957; + uint16_t _11958 = (uint16_t)(220); + _curvea0[673] = _11958; + uint16_t _11959 = (uint16_t)(220); + _curvea0[674] = _11959; + uint16_t _11960 = (uint16_t)(220); + _curvea0[675] = _11960; + uint16_t _11961 = (uint16_t)(220); + _curvea0[676] = _11961; + uint16_t _11962 = (uint16_t)(220); + _curvea0[677] = _11962; + uint16_t _11963 = (uint16_t)(220); + _curvea0[678] = _11963; + uint16_t _11964 = (uint16_t)(220); + _curvea0[679] = _11964; + uint16_t _11965 = (uint16_t)(220); + _curvea0[680] = _11965; + uint16_t _11966 = (uint16_t)(221); + _curvea0[681] = _11966; + uint16_t _11967 = (uint16_t)(221); + _curvea0[682] = _11967; + uint16_t _11968 = (uint16_t)(221); + _curvea0[683] = _11968; + uint16_t _11969 = (uint16_t)(221); + _curvea0[684] = _11969; + uint16_t _11970 = (uint16_t)(221); + _curvea0[685] = _11970; + uint16_t _11971 = (uint16_t)(221); + _curvea0[686] = _11971; + uint16_t _11972 = (uint16_t)(221); + _curvea0[687] = _11972; + uint16_t _11973 = (uint16_t)(222); + _curvea0[688] = _11973; + uint16_t _11974 = (uint16_t)(222); + _curvea0[689] = _11974; + uint16_t _11975 = (uint16_t)(222); + _curvea0[690] = _11975; + uint16_t _11976 = (uint16_t)(222); + _curvea0[691] = _11976; + uint16_t _11977 = (uint16_t)(222); + _curvea0[692] = _11977; + uint16_t _11978 = (uint16_t)(222); + _curvea0[693] = _11978; + uint16_t _11979 = (uint16_t)(222); + _curvea0[694] = _11979; + uint16_t _11980 = (uint16_t)(223); + _curvea0[695] = _11980; + uint16_t _11981 = (uint16_t)(223); + _curvea0[696] = _11981; + uint16_t _11982 = (uint16_t)(223); + _curvea0[697] = _11982; + uint16_t _11983 = (uint16_t)(223); + _curvea0[698] = _11983; + uint16_t _11984 = (uint16_t)(223); + _curvea0[699] = _11984; + uint16_t _11985 = (uint16_t)(223); + _curvea0[700] = _11985; + uint16_t _11986 = (uint16_t)(223); + _curvea0[701] = _11986; + uint16_t _11987 = (uint16_t)(223); + _curvea0[702] = _11987; + uint16_t _11988 = (uint16_t)(224); + _curvea0[703] = _11988; + uint16_t _11989 = (uint16_t)(224); + _curvea0[704] = _11989; + uint16_t _11990 = (uint16_t)(224); + _curvea0[705] = _11990; + uint16_t _11991 = (uint16_t)(224); + _curvea0[706] = _11991; + uint16_t _11992 = (uint16_t)(224); + _curvea0[707] = _11992; + uint16_t _11993 = (uint16_t)(224); + _curvea0[708] = _11993; + uint16_t _11994 = (uint16_t)(224); + _curvea0[709] = _11994; + uint16_t _11995 = (uint16_t)(224); + _curvea0[710] = _11995; + uint16_t _11996 = (uint16_t)(225); + _curvea0[711] = _11996; + uint16_t _11997 = (uint16_t)(225); + _curvea0[712] = _11997; + uint16_t _11998 = (uint16_t)(225); + _curvea0[713] = _11998; + uint16_t _11999 = (uint16_t)(225); + _curvea0[714] = _11999; + uint16_t _12000 = (uint16_t)(225); + _curvea0[715] = _12000; + uint16_t _12001 = (uint16_t)(225); + _curvea0[716] = _12001; + uint16_t _12002 = (uint16_t)(225); + _curvea0[717] = _12002; + uint16_t _12003 = (uint16_t)(226); + _curvea0[718] = _12003; + uint16_t _12004 = (uint16_t)(226); + _curvea0[719] = _12004; + uint16_t _12005 = (uint16_t)(226); + _curvea0[720] = _12005; + uint16_t _12006 = (uint16_t)(226); + _curvea0[721] = _12006; + uint16_t _12007 = (uint16_t)(226); + _curvea0[722] = _12007; + uint16_t _12008 = (uint16_t)(226); + _curvea0[723] = _12008; + uint16_t _12009 = (uint16_t)(226); + _curvea0[724] = _12009; + uint16_t _12010 = (uint16_t)(226); + _curvea0[725] = _12010; + uint16_t _12011 = (uint16_t)(227); + _curvea0[726] = _12011; + uint16_t _12012 = (uint16_t)(227); + _curvea0[727] = _12012; + uint16_t _12013 = (uint16_t)(227); + _curvea0[728] = _12013; + uint16_t _12014 = (uint16_t)(227); + _curvea0[729] = _12014; + uint16_t _12015 = (uint16_t)(227); + _curvea0[730] = _12015; + uint16_t _12016 = (uint16_t)(227); + _curvea0[731] = _12016; + uint16_t _12017 = (uint16_t)(227); + _curvea0[732] = _12017; + uint16_t _12018 = (uint16_t)(227); + _curvea0[733] = _12018; + uint16_t _12019 = (uint16_t)(228); + _curvea0[734] = _12019; + uint16_t _12020 = (uint16_t)(228); + _curvea0[735] = _12020; + uint16_t _12021 = (uint16_t)(228); + _curvea0[736] = _12021; + uint16_t _12022 = (uint16_t)(228); + _curvea0[737] = _12022; + uint16_t _12023 = (uint16_t)(228); + _curvea0[738] = _12023; + uint16_t _12024 = (uint16_t)(228); + _curvea0[739] = _12024; + uint16_t _12025 = (uint16_t)(228); + _curvea0[740] = _12025; + uint16_t _12026 = (uint16_t)(228); + _curvea0[741] = _12026; + uint16_t _12027 = (uint16_t)(228); + _curvea0[742] = _12027; + uint16_t _12028 = (uint16_t)(229); + _curvea0[743] = _12028; + uint16_t _12029 = (uint16_t)(229); + _curvea0[744] = _12029; + uint16_t _12030 = (uint16_t)(229); + _curvea0[745] = _12030; + uint16_t _12031 = (uint16_t)(229); + _curvea0[746] = _12031; + uint16_t _12032 = (uint16_t)(229); + _curvea0[747] = _12032; + uint16_t _12033 = (uint16_t)(229); + _curvea0[748] = _12033; + uint16_t _12034 = (uint16_t)(229); + _curvea0[749] = _12034; + uint16_t _12035 = (uint16_t)(229); + _curvea0[750] = _12035; + uint16_t _12036 = (uint16_t)(230); + _curvea0[751] = _12036; + uint16_t _12037 = (uint16_t)(230); + _curvea0[752] = _12037; + uint16_t _12038 = (uint16_t)(230); + _curvea0[753] = _12038; + uint16_t _12039 = (uint16_t)(230); + _curvea0[754] = _12039; + uint16_t _12040 = (uint16_t)(230); + _curvea0[755] = _12040; + uint16_t _12041 = (uint16_t)(230); + _curvea0[756] = _12041; + uint16_t _12042 = (uint16_t)(230); + _curvea0[757] = _12042; + uint16_t _12043 = (uint16_t)(230); + _curvea0[758] = _12043; + uint16_t _12044 = (uint16_t)(231); + _curvea0[759] = _12044; + uint16_t _12045 = (uint16_t)(231); + _curvea0[760] = _12045; + uint16_t _12046 = (uint16_t)(231); + _curvea0[761] = _12046; + uint16_t _12047 = (uint16_t)(231); + _curvea0[762] = _12047; + uint16_t _12048 = (uint16_t)(231); + _curvea0[763] = _12048; + uint16_t _12049 = (uint16_t)(231); + _curvea0[764] = _12049; + uint16_t _12050 = (uint16_t)(231); + _curvea0[765] = _12050; + uint16_t _12051 = (uint16_t)(231); + _curvea0[766] = _12051; + uint16_t _12052 = (uint16_t)(231); + _curvea0[767] = _12052; + uint16_t _12053 = (uint16_t)(232); + _curvea0[768] = _12053; + uint16_t _12054 = (uint16_t)(232); + _curvea0[769] = _12054; + uint16_t _12055 = (uint16_t)(232); + _curvea0[770] = _12055; + uint16_t _12056 = (uint16_t)(232); + _curvea0[771] = _12056; + uint16_t _12057 = (uint16_t)(232); + _curvea0[772] = _12057; + uint16_t _12058 = (uint16_t)(232); + _curvea0[773] = _12058; + uint16_t _12059 = (uint16_t)(232); + _curvea0[774] = _12059; + uint16_t _12060 = (uint16_t)(232); + _curvea0[775] = _12060; + uint16_t _12061 = (uint16_t)(233); + _curvea0[776] = _12061; + uint16_t _12062 = (uint16_t)(233); + _curvea0[777] = _12062; + uint16_t _12063 = (uint16_t)(233); + _curvea0[778] = _12063; + uint16_t _12064 = (uint16_t)(233); + _curvea0[779] = _12064; + uint16_t _12065 = (uint16_t)(233); + _curvea0[780] = _12065; + uint16_t _12066 = (uint16_t)(233); + _curvea0[781] = _12066; + uint16_t _12067 = (uint16_t)(233); + _curvea0[782] = _12067; + uint16_t _12068 = (uint16_t)(233); + _curvea0[783] = _12068; + uint16_t _12069 = (uint16_t)(233); + _curvea0[784] = _12069; + uint16_t _12070 = (uint16_t)(234); + _curvea0[785] = _12070; + uint16_t _12071 = (uint16_t)(234); + _curvea0[786] = _12071; + uint16_t _12072 = (uint16_t)(234); + _curvea0[787] = _12072; + uint16_t _12073 = (uint16_t)(234); + _curvea0[788] = _12073; + uint16_t _12074 = (uint16_t)(234); + _curvea0[789] = _12074; + uint16_t _12075 = (uint16_t)(234); + _curvea0[790] = _12075; + uint16_t _12076 = (uint16_t)(234); + _curvea0[791] = _12076; + uint16_t _12077 = (uint16_t)(234); + _curvea0[792] = _12077; + uint16_t _12078 = (uint16_t)(234); + _curvea0[793] = _12078; + uint16_t _12079 = (uint16_t)(235); + _curvea0[794] = _12079; + uint16_t _12080 = (uint16_t)(235); + _curvea0[795] = _12080; + uint16_t _12081 = (uint16_t)(235); + _curvea0[796] = _12081; + uint16_t _12082 = (uint16_t)(235); + _curvea0[797] = _12082; + uint16_t _12083 = (uint16_t)(235); + _curvea0[798] = _12083; + uint16_t _12084 = (uint16_t)(235); + _curvea0[799] = _12084; + uint16_t _12085 = (uint16_t)(235); + _curvea0[800] = _12085; + uint16_t _12086 = (uint16_t)(235); + _curvea0[801] = _12086; + uint16_t _12087 = (uint16_t)(235); + _curvea0[802] = _12087; + uint16_t _12088 = (uint16_t)(236); + _curvea0[803] = _12088; + uint16_t _12089 = (uint16_t)(236); + _curvea0[804] = _12089; + uint16_t _12090 = (uint16_t)(236); + _curvea0[805] = _12090; + uint16_t _12091 = (uint16_t)(236); + _curvea0[806] = _12091; + uint16_t _12092 = (uint16_t)(236); + _curvea0[807] = _12092; + uint16_t _12093 = (uint16_t)(236); + _curvea0[808] = _12093; + uint16_t _12094 = (uint16_t)(236); + _curvea0[809] = _12094; + uint16_t _12095 = (uint16_t)(236); + _curvea0[810] = _12095; + uint16_t _12096 = (uint16_t)(236); + _curvea0[811] = _12096; + uint16_t _12097 = (uint16_t)(237); + _curvea0[812] = _12097; + uint16_t _12098 = (uint16_t)(237); + _curvea0[813] = _12098; + uint16_t _12099 = (uint16_t)(237); + _curvea0[814] = _12099; + uint16_t _12100 = (uint16_t)(237); + _curvea0[815] = _12100; + uint16_t _12101 = (uint16_t)(237); + _curvea0[816] = _12101; + uint16_t _12102 = (uint16_t)(237); + _curvea0[817] = _12102; + uint16_t _12103 = (uint16_t)(237); + _curvea0[818] = _12103; + uint16_t _12104 = (uint16_t)(237); + _curvea0[819] = _12104; + uint16_t _12105 = (uint16_t)(237); + _curvea0[820] = _12105; + uint16_t _12106 = (uint16_t)(237); + _curvea0[821] = _12106; + uint16_t _12107 = (uint16_t)(238); + _curvea0[822] = _12107; + uint16_t _12108 = (uint16_t)(238); + _curvea0[823] = _12108; + uint16_t _12109 = (uint16_t)(238); + _curvea0[824] = _12109; + uint16_t _12110 = (uint16_t)(238); + _curvea0[825] = _12110; + uint16_t _12111 = (uint16_t)(238); + _curvea0[826] = _12111; + uint16_t _12112 = (uint16_t)(238); + _curvea0[827] = _12112; + uint16_t _12113 = (uint16_t)(238); + _curvea0[828] = _12113; + uint16_t _12114 = (uint16_t)(238); + _curvea0[829] = _12114; + uint16_t _12115 = (uint16_t)(238); + _curvea0[830] = _12115; + uint16_t _12116 = (uint16_t)(239); + _curvea0[831] = _12116; + uint16_t _12117 = (uint16_t)(239); + _curvea0[832] = _12117; + uint16_t _12118 = (uint16_t)(239); + _curvea0[833] = _12118; + uint16_t _12119 = (uint16_t)(239); + _curvea0[834] = _12119; + uint16_t _12120 = (uint16_t)(239); + _curvea0[835] = _12120; + uint16_t _12121 = (uint16_t)(239); + _curvea0[836] = _12121; + uint16_t _12122 = (uint16_t)(239); + _curvea0[837] = _12122; + uint16_t _12123 = (uint16_t)(239); + _curvea0[838] = _12123; + uint16_t _12124 = (uint16_t)(239); + _curvea0[839] = _12124; + uint16_t _12125 = (uint16_t)(239); + _curvea0[840] = _12125; + uint16_t _12126 = (uint16_t)(240); + _curvea0[841] = _12126; + uint16_t _12127 = (uint16_t)(240); + _curvea0[842] = _12127; + uint16_t _12128 = (uint16_t)(240); + _curvea0[843] = _12128; + uint16_t _12129 = (uint16_t)(240); + _curvea0[844] = _12129; + uint16_t _12130 = (uint16_t)(240); + _curvea0[845] = _12130; + uint16_t _12131 = (uint16_t)(240); + _curvea0[846] = _12131; + uint16_t _12132 = (uint16_t)(240); + _curvea0[847] = _12132; + uint16_t _12133 = (uint16_t)(240); + _curvea0[848] = _12133; + uint16_t _12134 = (uint16_t)(240); + _curvea0[849] = _12134; + uint16_t _12135 = (uint16_t)(240); + _curvea0[850] = _12135; + uint16_t _12136 = (uint16_t)(241); + _curvea0[851] = _12136; + uint16_t _12137 = (uint16_t)(241); + _curvea0[852] = _12137; + uint16_t _12138 = (uint16_t)(241); + _curvea0[853] = _12138; + uint16_t _12139 = (uint16_t)(241); + _curvea0[854] = _12139; + uint16_t _12140 = (uint16_t)(241); + _curvea0[855] = _12140; + uint16_t _12141 = (uint16_t)(241); + _curvea0[856] = _12141; + uint16_t _12142 = (uint16_t)(241); + _curvea0[857] = _12142; + uint16_t _12143 = (uint16_t)(241); + _curvea0[858] = _12143; + uint16_t _12144 = (uint16_t)(241); + _curvea0[859] = _12144; + uint16_t _12145 = (uint16_t)(241); + _curvea0[860] = _12145; + uint16_t _12146 = (uint16_t)(242); + _curvea0[861] = _12146; + uint16_t _12147 = (uint16_t)(242); + _curvea0[862] = _12147; + uint16_t _12148 = (uint16_t)(242); + _curvea0[863] = _12148; + uint16_t _12149 = (uint16_t)(242); + _curvea0[864] = _12149; + uint16_t _12150 = (uint16_t)(242); + _curvea0[865] = _12150; + uint16_t _12151 = (uint16_t)(242); + _curvea0[866] = _12151; + uint16_t _12152 = (uint16_t)(242); + _curvea0[867] = _12152; + uint16_t _12153 = (uint16_t)(242); + _curvea0[868] = _12153; + uint16_t _12154 = (uint16_t)(242); + _curvea0[869] = _12154; + uint16_t _12155 = (uint16_t)(242); + _curvea0[870] = _12155; + uint16_t _12156 = (uint16_t)(243); + _curvea0[871] = _12156; + uint16_t _12157 = (uint16_t)(243); + _curvea0[872] = _12157; + uint16_t _12158 = (uint16_t)(243); + _curvea0[873] = _12158; + uint16_t _12159 = (uint16_t)(243); + _curvea0[874] = _12159; + uint16_t _12160 = (uint16_t)(243); + _curvea0[875] = _12160; + uint16_t _12161 = (uint16_t)(243); + _curvea0[876] = _12161; + uint16_t _12162 = (uint16_t)(243); + _curvea0[877] = _12162; + uint16_t _12163 = (uint16_t)(243); + _curvea0[878] = _12163; + uint16_t _12164 = (uint16_t)(243); + _curvea0[879] = _12164; + uint16_t _12165 = (uint16_t)(243); + _curvea0[880] = _12165; + uint16_t _12166 = (uint16_t)(244); + _curvea0[881] = _12166; + uint16_t _12167 = (uint16_t)(244); + _curvea0[882] = _12167; + uint16_t _12168 = (uint16_t)(244); + _curvea0[883] = _12168; + uint16_t _12169 = (uint16_t)(244); + _curvea0[884] = _12169; + uint16_t _12170 = (uint16_t)(244); + _curvea0[885] = _12170; + uint16_t _12171 = (uint16_t)(244); + _curvea0[886] = _12171; + uint16_t _12172 = (uint16_t)(244); + _curvea0[887] = _12172; + uint16_t _12173 = (uint16_t)(244); + _curvea0[888] = _12173; + uint16_t _12174 = (uint16_t)(244); + _curvea0[889] = _12174; + uint16_t _12175 = (uint16_t)(244); + _curvea0[890] = _12175; + uint16_t _12176 = (uint16_t)(244); + _curvea0[891] = _12176; + uint16_t _12177 = (uint16_t)(245); + _curvea0[892] = _12177; + uint16_t _12178 = (uint16_t)(245); + _curvea0[893] = _12178; + uint16_t _12179 = (uint16_t)(245); + _curvea0[894] = _12179; + uint16_t _12180 = (uint16_t)(245); + _curvea0[895] = _12180; + uint16_t _12181 = (uint16_t)(245); + _curvea0[896] = _12181; + uint16_t _12182 = (uint16_t)(245); + _curvea0[897] = _12182; + uint16_t _12183 = (uint16_t)(245); + _curvea0[898] = _12183; + uint16_t _12184 = (uint16_t)(245); + _curvea0[899] = _12184; + uint16_t _12185 = (uint16_t)(245); + _curvea0[900] = _12185; + uint16_t _12186 = (uint16_t)(245); + _curvea0[901] = _12186; + uint16_t _12187 = (uint16_t)(245); + _curvea0[902] = _12187; + uint16_t _12188 = (uint16_t)(246); + _curvea0[903] = _12188; + uint16_t _12189 = (uint16_t)(246); + _curvea0[904] = _12189; + uint16_t _12190 = (uint16_t)(246); + _curvea0[905] = _12190; + uint16_t _12191 = (uint16_t)(246); + _curvea0[906] = _12191; + uint16_t _12192 = (uint16_t)(246); + _curvea0[907] = _12192; + uint16_t _12193 = (uint16_t)(246); + _curvea0[908] = _12193; + uint16_t _12194 = (uint16_t)(246); + _curvea0[909] = _12194; + uint16_t _12195 = (uint16_t)(246); + _curvea0[910] = _12195; + uint16_t _12196 = (uint16_t)(246); + _curvea0[911] = _12196; + uint16_t _12197 = (uint16_t)(246); + _curvea0[912] = _12197; + uint16_t _12198 = (uint16_t)(246); + _curvea0[913] = _12198; + uint16_t _12199 = (uint16_t)(247); + _curvea0[914] = _12199; + uint16_t _12200 = (uint16_t)(247); + _curvea0[915] = _12200; + uint16_t _12201 = (uint16_t)(247); + _curvea0[916] = _12201; + uint16_t _12202 = (uint16_t)(247); + _curvea0[917] = _12202; + uint16_t _12203 = (uint16_t)(247); + _curvea0[918] = _12203; + uint16_t _12204 = (uint16_t)(247); + _curvea0[919] = _12204; + uint16_t _12205 = (uint16_t)(247); + _curvea0[920] = _12205; + uint16_t _12206 = (uint16_t)(247); + _curvea0[921] = _12206; + uint16_t _12207 = (uint16_t)(247); + _curvea0[922] = _12207; + uint16_t _12208 = (uint16_t)(247); + _curvea0[923] = _12208; + uint16_t _12209 = (uint16_t)(247); + _curvea0[924] = _12209; + uint16_t _12210 = (uint16_t)(248); + _curvea0[925] = _12210; + uint16_t _12211 = (uint16_t)(248); + _curvea0[926] = _12211; + uint16_t _12212 = (uint16_t)(248); + _curvea0[927] = _12212; + uint16_t _12213 = (uint16_t)(248); + _curvea0[928] = _12213; + uint16_t _12214 = (uint16_t)(248); + _curvea0[929] = _12214; + uint16_t _12215 = (uint16_t)(248); + _curvea0[930] = _12215; + uint16_t _12216 = (uint16_t)(248); + _curvea0[931] = _12216; + uint16_t _12217 = (uint16_t)(248); + _curvea0[932] = _12217; + uint16_t _12218 = (uint16_t)(248); + _curvea0[933] = _12218; + uint16_t _12219 = (uint16_t)(248); + _curvea0[934] = _12219; + uint16_t _12220 = (uint16_t)(248); + _curvea0[935] = _12220; + uint16_t _12221 = (uint16_t)(249); + _curvea0[936] = _12221; + uint16_t _12222 = (uint16_t)(249); + _curvea0[937] = _12222; + uint16_t _12223 = (uint16_t)(249); + _curvea0[938] = _12223; + uint16_t _12224 = (uint16_t)(249); + _curvea0[939] = _12224; + uint16_t _12225 = (uint16_t)(249); + _curvea0[940] = _12225; + uint16_t _12226 = (uint16_t)(249); + _curvea0[941] = _12226; + uint16_t _12227 = (uint16_t)(249); + _curvea0[942] = _12227; + uint16_t _12228 = (uint16_t)(249); + _curvea0[943] = _12228; + uint16_t _12229 = (uint16_t)(249); + _curvea0[944] = _12229; + uint16_t _12230 = (uint16_t)(249); + _curvea0[945] = _12230; + uint16_t _12231 = (uint16_t)(249); + _curvea0[946] = _12231; + uint16_t _12232 = (uint16_t)(249); + _curvea0[947] = _12232; + uint16_t _12233 = (uint16_t)(250); + _curvea0[948] = _12233; + uint16_t _12234 = (uint16_t)(250); + _curvea0[949] = _12234; + uint16_t _12235 = (uint16_t)(250); + _curvea0[950] = _12235; + uint16_t _12236 = (uint16_t)(250); + _curvea0[951] = _12236; + uint16_t _12237 = (uint16_t)(250); + _curvea0[952] = _12237; + uint16_t _12238 = (uint16_t)(250); + _curvea0[953] = _12238; + uint16_t _12239 = (uint16_t)(250); + _curvea0[954] = _12239; + uint16_t _12240 = (uint16_t)(250); + _curvea0[955] = _12240; + uint16_t _12241 = (uint16_t)(250); + _curvea0[956] = _12241; + uint16_t _12242 = (uint16_t)(250); + _curvea0[957] = _12242; + uint16_t _12243 = (uint16_t)(250); + _curvea0[958] = _12243; + uint16_t _12244 = (uint16_t)(250); + _curvea0[959] = _12244; + uint16_t _12245 = (uint16_t)(251); + _curvea0[960] = _12245; + uint16_t _12246 = (uint16_t)(251); + _curvea0[961] = _12246; + uint16_t _12247 = (uint16_t)(251); + _curvea0[962] = _12247; + uint16_t _12248 = (uint16_t)(251); + _curvea0[963] = _12248; + uint16_t _12249 = (uint16_t)(251); + _curvea0[964] = _12249; + uint16_t _12250 = (uint16_t)(251); + _curvea0[965] = _12250; + uint16_t _12251 = (uint16_t)(251); + _curvea0[966] = _12251; + uint16_t _12252 = (uint16_t)(251); + _curvea0[967] = _12252; + uint16_t _12253 = (uint16_t)(251); + _curvea0[968] = _12253; + uint16_t _12254 = (uint16_t)(251); + _curvea0[969] = _12254; + uint16_t _12255 = (uint16_t)(251); + _curvea0[970] = _12255; + uint16_t _12256 = (uint16_t)(251); + _curvea0[971] = _12256; + uint16_t _12257 = (uint16_t)(252); + _curvea0[972] = _12257; + uint16_t _12258 = (uint16_t)(252); + _curvea0[973] = _12258; + uint16_t _12259 = (uint16_t)(252); + _curvea0[974] = _12259; + uint16_t _12260 = (uint16_t)(252); + _curvea0[975] = _12260; + uint16_t _12261 = (uint16_t)(252); + _curvea0[976] = _12261; + uint16_t _12262 = (uint16_t)(252); + _curvea0[977] = _12262; + uint16_t _12263 = (uint16_t)(252); + _curvea0[978] = _12263; + uint16_t _12264 = (uint16_t)(252); + _curvea0[979] = _12264; + uint16_t _12265 = (uint16_t)(252); + _curvea0[980] = _12265; + uint16_t _12266 = (uint16_t)(252); + _curvea0[981] = _12266; + uint16_t _12267 = (uint16_t)(252); + _curvea0[982] = _12267; + uint16_t _12268 = (uint16_t)(252); + _curvea0[983] = _12268; + uint16_t _12269 = (uint16_t)(252); + _curvea0[984] = _12269; + uint16_t _12270 = (uint16_t)(253); + _curvea0[985] = _12270; + uint16_t _12271 = (uint16_t)(253); + _curvea0[986] = _12271; + uint16_t _12272 = (uint16_t)(253); + _curvea0[987] = _12272; + uint16_t _12273 = (uint16_t)(253); + _curvea0[988] = _12273; + uint16_t _12274 = (uint16_t)(253); + _curvea0[989] = _12274; + uint16_t _12275 = (uint16_t)(253); + _curvea0[990] = _12275; + uint16_t _12276 = (uint16_t)(253); + _curvea0[991] = _12276; + uint16_t _12277 = (uint16_t)(253); + _curvea0[992] = _12277; + uint16_t _12278 = (uint16_t)(253); + _curvea0[993] = _12278; + uint16_t _12279 = (uint16_t)(253); + _curvea0[994] = _12279; + uint16_t _12280 = (uint16_t)(253); + _curvea0[995] = _12280; + uint16_t _12281 = (uint16_t)(253); + _curvea0[996] = _12281; + uint16_t _12282 = (uint16_t)(253); + _curvea0[997] = _12282; + uint16_t _12283 = (uint16_t)(254); + _curvea0[998] = _12283; + uint16_t _12284 = (uint16_t)(254); + _curvea0[999] = _12284; + uint16_t _12285 = (uint16_t)(254); + _curvea0[1000] = _12285; + uint16_t _12286 = (uint16_t)(254); + _curvea0[1001] = _12286; + uint16_t _12287 = (uint16_t)(254); + _curvea0[1002] = _12287; + uint16_t _12288 = (uint16_t)(254); + _curvea0[1003] = _12288; + uint16_t _12289 = (uint16_t)(254); + _curvea0[1004] = _12289; + uint16_t _12290 = (uint16_t)(254); + _curvea0[1005] = _12290; + uint16_t _12291 = (uint16_t)(254); + _curvea0[1006] = _12291; + uint16_t _12292 = (uint16_t)(254); + _curvea0[1007] = _12292; + uint16_t _12293 = (uint16_t)(254); + _curvea0[1008] = _12293; + uint16_t _12294 = (uint16_t)(254); + _curvea0[1009] = _12294; + uint16_t _12295 = (uint16_t)(254); + _curvea0[1010] = _12295; + uint16_t _12296 = (uint16_t)(255); + _curvea0[1011] = _12296; + uint16_t _12297 = (uint16_t)(255); + _curvea0[1012] = _12297; + uint16_t _12298 = (uint16_t)(255); + _curvea0[1013] = _12298; + uint16_t _12299 = (uint16_t)(255); + _curvea0[1014] = _12299; + uint16_t _12300 = (uint16_t)(255); + _curvea0[1015] = _12300; + uint16_t _12301 = (uint16_t)(255); + _curvea0[1016] = _12301; + uint16_t _12302 = (uint16_t)(255); + _curvea0[1017] = _12302; + uint16_t _12303 = (uint16_t)(255); + _curvea0[1018] = _12303; + uint16_t _12304 = (uint16_t)(255); + _curvea0[1019] = _12304; + uint16_t _12305 = (uint16_t)(255); + _curvea0[1020] = _12305; + uint16_t _12306 = (uint16_t)(255); + _curvea0[1021] = _12306; + uint16_t _12307 = (uint16_t)(255); + _curvea0[1022] = _12307; + uint16_t _12308 = (uint16_t)(255); + _curvea0[1023] = _12308; + + int16_t _12309 = (int16_t)(1023); + int16_t _12310 = min(_corrected_stencil_8, _12309); + int16_t _12311 = (int16_t)(0); + int16_t _12312 = max(_12310, _12311); + uint16_t _12313 = (uint16_t)(_12312); + int32_t _12314 = (int32_t)(_12313); + uint16_t _12315 = ((const uint16_t *)_curvea0)[_12314]; + return _12315; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_8(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_9 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _12333 = (uint16_t)(0); + _curvea0[0] = _12333; + uint16_t _12334 = (uint16_t)(4); + _curvea0[1] = _12334; + uint16_t _12335 = (uint16_t)(7); + _curvea0[2] = _12335; + uint16_t _12336 = (uint16_t)(8); + _curvea0[3] = _12336; + uint16_t _12337 = (uint16_t)(10); + _curvea0[4] = _12337; + uint16_t _12338 = (uint16_t)(11); + _curvea0[5] = _12338; + uint16_t _12339 = (uint16_t)(12); + _curvea0[6] = _12339; + uint16_t _12340 = (uint16_t)(13); + _curvea0[7] = _12340; + uint16_t _12341 = (uint16_t)(14); + _curvea0[8] = _12341; + uint16_t _12342 = (uint16_t)(15); + _curvea0[9] = _12342; + uint16_t _12343 = (uint16_t)(16); + _curvea0[10] = _12343; + uint16_t _12344 = (uint16_t)(17); + _curvea0[11] = _12344; + uint16_t _12345 = (uint16_t)(18); + _curvea0[12] = _12345; + uint16_t _12346 = (uint16_t)(19); + _curvea0[13] = _12346; + uint16_t _12347 = (uint16_t)(20); + _curvea0[14] = _12347; + uint16_t _12348 = (uint16_t)(21); + _curvea0[15] = _12348; + uint16_t _12349 = (uint16_t)(22); + _curvea0[16] = _12349; + uint16_t _12350 = (uint16_t)(22); + _curvea0[17] = _12350; + uint16_t _12351 = (uint16_t)(23); + _curvea0[18] = _12351; + uint16_t _12352 = (uint16_t)(24); + _curvea0[19] = _12352; + uint16_t _12353 = (uint16_t)(25); + _curvea0[20] = _12353; + uint16_t _12354 = (uint16_t)(25); + _curvea0[21] = _12354; + uint16_t _12355 = (uint16_t)(26); + _curvea0[22] = _12355; + uint16_t _12356 = (uint16_t)(27); + _curvea0[23] = _12356; + uint16_t _12357 = (uint16_t)(27); + _curvea0[24] = _12357; + uint16_t _12358 = (uint16_t)(28); + _curvea0[25] = _12358; + uint16_t _12359 = (uint16_t)(29); + _curvea0[26] = _12359; + uint16_t _12360 = (uint16_t)(29); + _curvea0[27] = _12360; + uint16_t _12361 = (uint16_t)(30); + _curvea0[28] = _12361; + uint16_t _12362 = (uint16_t)(31); + _curvea0[29] = _12362; + uint16_t _12363 = (uint16_t)(31); + _curvea0[30] = _12363; + uint16_t _12364 = (uint16_t)(32); + _curvea0[31] = _12364; + uint16_t _12365 = (uint16_t)(33); + _curvea0[32] = _12365; + uint16_t _12366 = (uint16_t)(33); + _curvea0[33] = _12366; + uint16_t _12367 = (uint16_t)(34); + _curvea0[34] = _12367; + uint16_t _12368 = (uint16_t)(34); + _curvea0[35] = _12368; + uint16_t _12369 = (uint16_t)(35); + _curvea0[36] = _12369; + uint16_t _12370 = (uint16_t)(36); + _curvea0[37] = _12370; + uint16_t _12371 = (uint16_t)(36); + _curvea0[38] = _12371; + uint16_t _12372 = (uint16_t)(37); + _curvea0[39] = _12372; + uint16_t _12373 = (uint16_t)(37); + _curvea0[40] = _12373; + uint16_t _12374 = (uint16_t)(38); + _curvea0[41] = _12374; + uint16_t _12375 = (uint16_t)(39); + _curvea0[42] = _12375; + uint16_t _12376 = (uint16_t)(39); + _curvea0[43] = _12376; + uint16_t _12377 = (uint16_t)(40); + _curvea0[44] = _12377; + uint16_t _12378 = (uint16_t)(40); + _curvea0[45] = _12378; + uint16_t _12379 = (uint16_t)(41); + _curvea0[46] = _12379; + uint16_t _12380 = (uint16_t)(41); + _curvea0[47] = _12380; + uint16_t _12381 = (uint16_t)(42); + _curvea0[48] = _12381; + uint16_t _12382 = (uint16_t)(42); + _curvea0[49] = _12382; + uint16_t _12383 = (uint16_t)(43); + _curvea0[50] = _12383; + uint16_t _12384 = (uint16_t)(44); + _curvea0[51] = _12384; + uint16_t _12385 = (uint16_t)(44); + _curvea0[52] = _12385; + uint16_t _12386 = (uint16_t)(45); + _curvea0[53] = _12386; + uint16_t _12387 = (uint16_t)(45); + _curvea0[54] = _12387; + uint16_t _12388 = (uint16_t)(46); + _curvea0[55] = _12388; + uint16_t _12389 = (uint16_t)(46); + _curvea0[56] = _12389; + uint16_t _12390 = (uint16_t)(47); + _curvea0[57] = _12390; + uint16_t _12391 = (uint16_t)(47); + _curvea0[58] = _12391; + uint16_t _12392 = (uint16_t)(48); + _curvea0[59] = _12392; + uint16_t _12393 = (uint16_t)(48); + _curvea0[60] = _12393; + uint16_t _12394 = (uint16_t)(49); + _curvea0[61] = _12394; + uint16_t _12395 = (uint16_t)(49); + _curvea0[62] = _12395; + uint16_t _12396 = (uint16_t)(50); + _curvea0[63] = _12396; + uint16_t _12397 = (uint16_t)(50); + _curvea0[64] = _12397; + uint16_t _12398 = (uint16_t)(51); + _curvea0[65] = _12398; + uint16_t _12399 = (uint16_t)(51); + _curvea0[66] = _12399; + uint16_t _12400 = (uint16_t)(52); + _curvea0[67] = _12400; + uint16_t _12401 = (uint16_t)(52); + _curvea0[68] = _12401; + uint16_t _12402 = (uint16_t)(53); + _curvea0[69] = _12402; + uint16_t _12403 = (uint16_t)(53); + _curvea0[70] = _12403; + uint16_t _12404 = (uint16_t)(54); + _curvea0[71] = _12404; + uint16_t _12405 = (uint16_t)(54); + _curvea0[72] = _12405; + uint16_t _12406 = (uint16_t)(55); + _curvea0[73] = _12406; + uint16_t _12407 = (uint16_t)(55); + _curvea0[74] = _12407; + uint16_t _12408 = (uint16_t)(56); + _curvea0[75] = _12408; + uint16_t _12409 = (uint16_t)(56); + _curvea0[76] = _12409; + uint16_t _12410 = (uint16_t)(57); + _curvea0[77] = _12410; + uint16_t _12411 = (uint16_t)(57); + _curvea0[78] = _12411; + uint16_t _12412 = (uint16_t)(58); + _curvea0[79] = _12412; + uint16_t _12413 = (uint16_t)(58); + _curvea0[80] = _12413; + uint16_t _12414 = (uint16_t)(58); + _curvea0[81] = _12414; + uint16_t _12415 = (uint16_t)(59); + _curvea0[82] = _12415; + uint16_t _12416 = (uint16_t)(59); + _curvea0[83] = _12416; + uint16_t _12417 = (uint16_t)(60); + _curvea0[84] = _12417; + uint16_t _12418 = (uint16_t)(60); + _curvea0[85] = _12418; + uint16_t _12419 = (uint16_t)(61); + _curvea0[86] = _12419; + uint16_t _12420 = (uint16_t)(61); + _curvea0[87] = _12420; + uint16_t _12421 = (uint16_t)(62); + _curvea0[88] = _12421; + uint16_t _12422 = (uint16_t)(62); + _curvea0[89] = _12422; + uint16_t _12423 = (uint16_t)(63); + _curvea0[90] = _12423; + uint16_t _12424 = (uint16_t)(63); + _curvea0[91] = _12424; + uint16_t _12425 = (uint16_t)(64); + _curvea0[92] = _12425; + uint16_t _12426 = (uint16_t)(64); + _curvea0[93] = _12426; + uint16_t _12427 = (uint16_t)(64); + _curvea0[94] = _12427; + uint16_t _12428 = (uint16_t)(65); + _curvea0[95] = _12428; + uint16_t _12429 = (uint16_t)(65); + _curvea0[96] = _12429; + uint16_t _12430 = (uint16_t)(66); + _curvea0[97] = _12430; + uint16_t _12431 = (uint16_t)(66); + _curvea0[98] = _12431; + uint16_t _12432 = (uint16_t)(67); + _curvea0[99] = _12432; + uint16_t _12433 = (uint16_t)(67); + _curvea0[100] = _12433; + uint16_t _12434 = (uint16_t)(68); + _curvea0[101] = _12434; + uint16_t _12435 = (uint16_t)(68); + _curvea0[102] = _12435; + uint16_t _12436 = (uint16_t)(68); + _curvea0[103] = _12436; + uint16_t _12437 = (uint16_t)(69); + _curvea0[104] = _12437; + uint16_t _12438 = (uint16_t)(69); + _curvea0[105] = _12438; + uint16_t _12439 = (uint16_t)(70); + _curvea0[106] = _12439; + uint16_t _12440 = (uint16_t)(70); + _curvea0[107] = _12440; + uint16_t _12441 = (uint16_t)(71); + _curvea0[108] = _12441; + uint16_t _12442 = (uint16_t)(71); + _curvea0[109] = _12442; + uint16_t _12443 = (uint16_t)(71); + _curvea0[110] = _12443; + uint16_t _12444 = (uint16_t)(72); + _curvea0[111] = _12444; + uint16_t _12445 = (uint16_t)(72); + _curvea0[112] = _12445; + uint16_t _12446 = (uint16_t)(73); + _curvea0[113] = _12446; + uint16_t _12447 = (uint16_t)(73); + _curvea0[114] = _12447; + uint16_t _12448 = (uint16_t)(74); + _curvea0[115] = _12448; + uint16_t _12449 = (uint16_t)(74); + _curvea0[116] = _12449; + uint16_t _12450 = (uint16_t)(74); + _curvea0[117] = _12450; + uint16_t _12451 = (uint16_t)(75); + _curvea0[118] = _12451; + uint16_t _12452 = (uint16_t)(75); + _curvea0[119] = _12452; + uint16_t _12453 = (uint16_t)(76); + _curvea0[120] = _12453; + uint16_t _12454 = (uint16_t)(76); + _curvea0[121] = _12454; + uint16_t _12455 = (uint16_t)(77); + _curvea0[122] = _12455; + uint16_t _12456 = (uint16_t)(77); + _curvea0[123] = _12456; + uint16_t _12457 = (uint16_t)(77); + _curvea0[124] = _12457; + uint16_t _12458 = (uint16_t)(78); + _curvea0[125] = _12458; + uint16_t _12459 = (uint16_t)(78); + _curvea0[126] = _12459; + uint16_t _12460 = (uint16_t)(79); + _curvea0[127] = _12460; + uint16_t _12461 = (uint16_t)(79); + _curvea0[128] = _12461; + uint16_t _12462 = (uint16_t)(79); + _curvea0[129] = _12462; + uint16_t _12463 = (uint16_t)(80); + _curvea0[130] = _12463; + uint16_t _12464 = (uint16_t)(80); + _curvea0[131] = _12464; + uint16_t _12465 = (uint16_t)(81); + _curvea0[132] = _12465; + uint16_t _12466 = (uint16_t)(81); + _curvea0[133] = _12466; + uint16_t _12467 = (uint16_t)(82); + _curvea0[134] = _12467; + uint16_t _12468 = (uint16_t)(82); + _curvea0[135] = _12468; + uint16_t _12469 = (uint16_t)(82); + _curvea0[136] = _12469; + uint16_t _12470 = (uint16_t)(83); + _curvea0[137] = _12470; + uint16_t _12471 = (uint16_t)(83); + _curvea0[138] = _12471; + uint16_t _12472 = (uint16_t)(84); + _curvea0[139] = _12472; + uint16_t _12473 = (uint16_t)(84); + _curvea0[140] = _12473; + uint16_t _12474 = (uint16_t)(84); + _curvea0[141] = _12474; + uint16_t _12475 = (uint16_t)(85); + _curvea0[142] = _12475; + uint16_t _12476 = (uint16_t)(85); + _curvea0[143] = _12476; + uint16_t _12477 = (uint16_t)(86); + _curvea0[144] = _12477; + uint16_t _12478 = (uint16_t)(86); + _curvea0[145] = _12478; + uint16_t _12479 = (uint16_t)(86); + _curvea0[146] = _12479; + uint16_t _12480 = (uint16_t)(87); + _curvea0[147] = _12480; + uint16_t _12481 = (uint16_t)(87); + _curvea0[148] = _12481; + uint16_t _12482 = (uint16_t)(88); + _curvea0[149] = _12482; + uint16_t _12483 = (uint16_t)(88); + _curvea0[150] = _12483; + uint16_t _12484 = (uint16_t)(88); + _curvea0[151] = _12484; + uint16_t _12485 = (uint16_t)(89); + _curvea0[152] = _12485; + uint16_t _12486 = (uint16_t)(89); + _curvea0[153] = _12486; + uint16_t _12487 = (uint16_t)(90); + _curvea0[154] = _12487; + uint16_t _12488 = (uint16_t)(90); + _curvea0[155] = _12488; + uint16_t _12489 = (uint16_t)(90); + _curvea0[156] = _12489; + uint16_t _12490 = (uint16_t)(91); + _curvea0[157] = _12490; + uint16_t _12491 = (uint16_t)(91); + _curvea0[158] = _12491; + uint16_t _12492 = (uint16_t)(92); + _curvea0[159] = _12492; + uint16_t _12493 = (uint16_t)(92); + _curvea0[160] = _12493; + uint16_t _12494 = (uint16_t)(92); + _curvea0[161] = _12494; + uint16_t _12495 = (uint16_t)(93); + _curvea0[162] = _12495; + uint16_t _12496 = (uint16_t)(93); + _curvea0[163] = _12496; + uint16_t _12497 = (uint16_t)(93); + _curvea0[164] = _12497; + uint16_t _12498 = (uint16_t)(94); + _curvea0[165] = _12498; + uint16_t _12499 = (uint16_t)(94); + _curvea0[166] = _12499; + uint16_t _12500 = (uint16_t)(95); + _curvea0[167] = _12500; + uint16_t _12501 = (uint16_t)(95); + _curvea0[168] = _12501; + uint16_t _12502 = (uint16_t)(95); + _curvea0[169] = _12502; + uint16_t _12503 = (uint16_t)(96); + _curvea0[170] = _12503; + uint16_t _12504 = (uint16_t)(96); + _curvea0[171] = _12504; + uint16_t _12505 = (uint16_t)(97); + _curvea0[172] = _12505; + uint16_t _12506 = (uint16_t)(97); + _curvea0[173] = _12506; + uint16_t _12507 = (uint16_t)(97); + _curvea0[174] = _12507; + uint16_t _12508 = (uint16_t)(98); + _curvea0[175] = _12508; + uint16_t _12509 = (uint16_t)(98); + _curvea0[176] = _12509; + uint16_t _12510 = (uint16_t)(99); + _curvea0[177] = _12510; + uint16_t _12511 = (uint16_t)(99); + _curvea0[178] = _12511; + uint16_t _12512 = (uint16_t)(99); + _curvea0[179] = _12512; + uint16_t _12513 = (uint16_t)(100); + _curvea0[180] = _12513; + uint16_t _12514 = (uint16_t)(100); + _curvea0[181] = _12514; + uint16_t _12515 = (uint16_t)(100); + _curvea0[182] = _12515; + uint16_t _12516 = (uint16_t)(101); + _curvea0[183] = _12516; + uint16_t _12517 = (uint16_t)(101); + _curvea0[184] = _12517; + uint16_t _12518 = (uint16_t)(102); + _curvea0[185] = _12518; + uint16_t _12519 = (uint16_t)(102); + _curvea0[186] = _12519; + uint16_t _12520 = (uint16_t)(102); + _curvea0[187] = _12520; + uint16_t _12521 = (uint16_t)(103); + _curvea0[188] = _12521; + uint16_t _12522 = (uint16_t)(103); + _curvea0[189] = _12522; + uint16_t _12523 = (uint16_t)(103); + _curvea0[190] = _12523; + uint16_t _12524 = (uint16_t)(104); + _curvea0[191] = _12524; + uint16_t _12525 = (uint16_t)(104); + _curvea0[192] = _12525; + uint16_t _12526 = (uint16_t)(105); + _curvea0[193] = _12526; + uint16_t _12527 = (uint16_t)(105); + _curvea0[194] = _12527; + uint16_t _12528 = (uint16_t)(105); + _curvea0[195] = _12528; + uint16_t _12529 = (uint16_t)(106); + _curvea0[196] = _12529; + uint16_t _12530 = (uint16_t)(106); + _curvea0[197] = _12530; + uint16_t _12531 = (uint16_t)(106); + _curvea0[198] = _12531; + uint16_t _12532 = (uint16_t)(107); + _curvea0[199] = _12532; + uint16_t _12533 = (uint16_t)(107); + _curvea0[200] = _12533; + uint16_t _12534 = (uint16_t)(108); + _curvea0[201] = _12534; + uint16_t _12535 = (uint16_t)(108); + _curvea0[202] = _12535; + uint16_t _12536 = (uint16_t)(108); + _curvea0[203] = _12536; + uint16_t _12537 = (uint16_t)(109); + _curvea0[204] = _12537; + uint16_t _12538 = (uint16_t)(109); + _curvea0[205] = _12538; + uint16_t _12539 = (uint16_t)(109); + _curvea0[206] = _12539; + uint16_t _12540 = (uint16_t)(110); + _curvea0[207] = _12540; + uint16_t _12541 = (uint16_t)(110); + _curvea0[208] = _12541; + uint16_t _12542 = (uint16_t)(111); + _curvea0[209] = _12542; + uint16_t _12543 = (uint16_t)(111); + _curvea0[210] = _12543; + uint16_t _12544 = (uint16_t)(111); + _curvea0[211] = _12544; + uint16_t _12545 = (uint16_t)(112); + _curvea0[212] = _12545; + uint16_t _12546 = (uint16_t)(112); + _curvea0[213] = _12546; + uint16_t _12547 = (uint16_t)(112); + _curvea0[214] = _12547; + uint16_t _12548 = (uint16_t)(113); + _curvea0[215] = _12548; + uint16_t _12549 = (uint16_t)(113); + _curvea0[216] = _12549; + uint16_t _12550 = (uint16_t)(113); + _curvea0[217] = _12550; + uint16_t _12551 = (uint16_t)(114); + _curvea0[218] = _12551; + uint16_t _12552 = (uint16_t)(114); + _curvea0[219] = _12552; + uint16_t _12553 = (uint16_t)(115); + _curvea0[220] = _12553; + uint16_t _12554 = (uint16_t)(115); + _curvea0[221] = _12554; + uint16_t _12555 = (uint16_t)(115); + _curvea0[222] = _12555; + uint16_t _12556 = (uint16_t)(116); + _curvea0[223] = _12556; + uint16_t _12557 = (uint16_t)(116); + _curvea0[224] = _12557; + uint16_t _12558 = (uint16_t)(116); + _curvea0[225] = _12558; + uint16_t _12559 = (uint16_t)(117); + _curvea0[226] = _12559; + uint16_t _12560 = (uint16_t)(117); + _curvea0[227] = _12560; + uint16_t _12561 = (uint16_t)(117); + _curvea0[228] = _12561; + uint16_t _12562 = (uint16_t)(118); + _curvea0[229] = _12562; + uint16_t _12563 = (uint16_t)(118); + _curvea0[230] = _12563; + uint16_t _12564 = (uint16_t)(119); + _curvea0[231] = _12564; + uint16_t _12565 = (uint16_t)(119); + _curvea0[232] = _12565; + uint16_t _12566 = (uint16_t)(119); + _curvea0[233] = _12566; + uint16_t _12567 = (uint16_t)(120); + _curvea0[234] = _12567; + uint16_t _12568 = (uint16_t)(120); + _curvea0[235] = _12568; + uint16_t _12569 = (uint16_t)(120); + _curvea0[236] = _12569; + uint16_t _12570 = (uint16_t)(121); + _curvea0[237] = _12570; + uint16_t _12571 = (uint16_t)(121); + _curvea0[238] = _12571; + uint16_t _12572 = (uint16_t)(121); + _curvea0[239] = _12572; + uint16_t _12573 = (uint16_t)(122); + _curvea0[240] = _12573; + uint16_t _12574 = (uint16_t)(122); + _curvea0[241] = _12574; + uint16_t _12575 = (uint16_t)(123); + _curvea0[242] = _12575; + uint16_t _12576 = (uint16_t)(123); + _curvea0[243] = _12576; + uint16_t _12577 = (uint16_t)(123); + _curvea0[244] = _12577; + uint16_t _12578 = (uint16_t)(124); + _curvea0[245] = _12578; + uint16_t _12579 = (uint16_t)(124); + _curvea0[246] = _12579; + uint16_t _12580 = (uint16_t)(124); + _curvea0[247] = _12580; + uint16_t _12581 = (uint16_t)(125); + _curvea0[248] = _12581; + uint16_t _12582 = (uint16_t)(125); + _curvea0[249] = _12582; + uint16_t _12583 = (uint16_t)(125); + _curvea0[250] = _12583; + uint16_t _12584 = (uint16_t)(126); + _curvea0[251] = _12584; + uint16_t _12585 = (uint16_t)(126); + _curvea0[252] = _12585; + uint16_t _12586 = (uint16_t)(126); + _curvea0[253] = _12586; + uint16_t _12587 = (uint16_t)(127); + _curvea0[254] = _12587; + uint16_t _12588 = (uint16_t)(127); + _curvea0[255] = _12588; + uint16_t _12589 = (uint16_t)(128); + _curvea0[256] = _12589; + uint16_t _12590 = (uint16_t)(128); + _curvea0[257] = _12590; + uint16_t _12591 = (uint16_t)(128); + _curvea0[258] = _12591; + uint16_t _12592 = (uint16_t)(129); + _curvea0[259] = _12592; + uint16_t _12593 = (uint16_t)(129); + _curvea0[260] = _12593; + uint16_t _12594 = (uint16_t)(129); + _curvea0[261] = _12594; + uint16_t _12595 = (uint16_t)(130); + _curvea0[262] = _12595; + uint16_t _12596 = (uint16_t)(130); + _curvea0[263] = _12596; + uint16_t _12597 = (uint16_t)(130); + _curvea0[264] = _12597; + uint16_t _12598 = (uint16_t)(131); + _curvea0[265] = _12598; + uint16_t _12599 = (uint16_t)(131); + _curvea0[266] = _12599; + uint16_t _12600 = (uint16_t)(131); + _curvea0[267] = _12600; + uint16_t _12601 = (uint16_t)(132); + _curvea0[268] = _12601; + uint16_t _12602 = (uint16_t)(132); + _curvea0[269] = _12602; + uint16_t _12603 = (uint16_t)(132); + _curvea0[270] = _12603; + uint16_t _12604 = (uint16_t)(133); + _curvea0[271] = _12604; + uint16_t _12605 = (uint16_t)(133); + _curvea0[272] = _12605; + uint16_t _12606 = (uint16_t)(133); + _curvea0[273] = _12606; + uint16_t _12607 = (uint16_t)(134); + _curvea0[274] = _12607; + uint16_t _12608 = (uint16_t)(134); + _curvea0[275] = _12608; + uint16_t _12609 = (uint16_t)(134); + _curvea0[276] = _12609; + uint16_t _12610 = (uint16_t)(135); + _curvea0[277] = _12610; + uint16_t _12611 = (uint16_t)(135); + _curvea0[278] = _12611; + uint16_t _12612 = (uint16_t)(135); + _curvea0[279] = _12612; + uint16_t _12613 = (uint16_t)(136); + _curvea0[280] = _12613; + uint16_t _12614 = (uint16_t)(136); + _curvea0[281] = _12614; + uint16_t _12615 = (uint16_t)(136); + _curvea0[282] = _12615; + uint16_t _12616 = (uint16_t)(137); + _curvea0[283] = _12616; + uint16_t _12617 = (uint16_t)(137); + _curvea0[284] = _12617; + uint16_t _12618 = (uint16_t)(137); + _curvea0[285] = _12618; + uint16_t _12619 = (uint16_t)(138); + _curvea0[286] = _12619; + uint16_t _12620 = (uint16_t)(138); + _curvea0[287] = _12620; + uint16_t _12621 = (uint16_t)(138); + _curvea0[288] = _12621; + uint16_t _12622 = (uint16_t)(139); + _curvea0[289] = _12622; + uint16_t _12623 = (uint16_t)(139); + _curvea0[290] = _12623; + uint16_t _12624 = (uint16_t)(139); + _curvea0[291] = _12624; + uint16_t _12625 = (uint16_t)(140); + _curvea0[292] = _12625; + uint16_t _12626 = (uint16_t)(140); + _curvea0[293] = _12626; + uint16_t _12627 = (uint16_t)(140); + _curvea0[294] = _12627; + uint16_t _12628 = (uint16_t)(141); + _curvea0[295] = _12628; + uint16_t _12629 = (uint16_t)(141); + _curvea0[296] = _12629; + uint16_t _12630 = (uint16_t)(141); + _curvea0[297] = _12630; + uint16_t _12631 = (uint16_t)(141); + _curvea0[298] = _12631; + uint16_t _12632 = (uint16_t)(142); + _curvea0[299] = _12632; + uint16_t _12633 = (uint16_t)(142); + _curvea0[300] = _12633; + uint16_t _12634 = (uint16_t)(142); + _curvea0[301] = _12634; + uint16_t _12635 = (uint16_t)(143); + _curvea0[302] = _12635; + uint16_t _12636 = (uint16_t)(143); + _curvea0[303] = _12636; + uint16_t _12637 = (uint16_t)(143); + _curvea0[304] = _12637; + uint16_t _12638 = (uint16_t)(144); + _curvea0[305] = _12638; + uint16_t _12639 = (uint16_t)(144); + _curvea0[306] = _12639; + uint16_t _12640 = (uint16_t)(144); + _curvea0[307] = _12640; + uint16_t _12641 = (uint16_t)(145); + _curvea0[308] = _12641; + uint16_t _12642 = (uint16_t)(145); + _curvea0[309] = _12642; + uint16_t _12643 = (uint16_t)(145); + _curvea0[310] = _12643; + uint16_t _12644 = (uint16_t)(145); + _curvea0[311] = _12644; + uint16_t _12645 = (uint16_t)(146); + _curvea0[312] = _12645; + uint16_t _12646 = (uint16_t)(146); + _curvea0[313] = _12646; + uint16_t _12647 = (uint16_t)(146); + _curvea0[314] = _12647; + uint16_t _12648 = (uint16_t)(147); + _curvea0[315] = _12648; + uint16_t _12649 = (uint16_t)(147); + _curvea0[316] = _12649; + uint16_t _12650 = (uint16_t)(147); + _curvea0[317] = _12650; + uint16_t _12651 = (uint16_t)(148); + _curvea0[318] = _12651; + uint16_t _12652 = (uint16_t)(148); + _curvea0[319] = _12652; + uint16_t _12653 = (uint16_t)(148); + _curvea0[320] = _12653; + uint16_t _12654 = (uint16_t)(148); + _curvea0[321] = _12654; + uint16_t _12655 = (uint16_t)(149); + _curvea0[322] = _12655; + uint16_t _12656 = (uint16_t)(149); + _curvea0[323] = _12656; + uint16_t _12657 = (uint16_t)(149); + _curvea0[324] = _12657; + uint16_t _12658 = (uint16_t)(150); + _curvea0[325] = _12658; + uint16_t _12659 = (uint16_t)(150); + _curvea0[326] = _12659; + uint16_t _12660 = (uint16_t)(150); + _curvea0[327] = _12660; + uint16_t _12661 = (uint16_t)(150); + _curvea0[328] = _12661; + uint16_t _12662 = (uint16_t)(151); + _curvea0[329] = _12662; + uint16_t _12663 = (uint16_t)(151); + _curvea0[330] = _12663; + uint16_t _12664 = (uint16_t)(151); + _curvea0[331] = _12664; + uint16_t _12665 = (uint16_t)(152); + _curvea0[332] = _12665; + uint16_t _12666 = (uint16_t)(152); + _curvea0[333] = _12666; + uint16_t _12667 = (uint16_t)(152); + _curvea0[334] = _12667; + uint16_t _12668 = (uint16_t)(152); + _curvea0[335] = _12668; + uint16_t _12669 = (uint16_t)(153); + _curvea0[336] = _12669; + uint16_t _12670 = (uint16_t)(153); + _curvea0[337] = _12670; + uint16_t _12671 = (uint16_t)(153); + _curvea0[338] = _12671; + uint16_t _12672 = (uint16_t)(154); + _curvea0[339] = _12672; + uint16_t _12673 = (uint16_t)(154); + _curvea0[340] = _12673; + uint16_t _12674 = (uint16_t)(154); + _curvea0[341] = _12674; + uint16_t _12675 = (uint16_t)(154); + _curvea0[342] = _12675; + uint16_t _12676 = (uint16_t)(155); + _curvea0[343] = _12676; + uint16_t _12677 = (uint16_t)(155); + _curvea0[344] = _12677; + uint16_t _12678 = (uint16_t)(155); + _curvea0[345] = _12678; + uint16_t _12679 = (uint16_t)(156); + _curvea0[346] = _12679; + uint16_t _12680 = (uint16_t)(156); + _curvea0[347] = _12680; + uint16_t _12681 = (uint16_t)(156); + _curvea0[348] = _12681; + uint16_t _12682 = (uint16_t)(156); + _curvea0[349] = _12682; + uint16_t _12683 = (uint16_t)(157); + _curvea0[350] = _12683; + uint16_t _12684 = (uint16_t)(157); + _curvea0[351] = _12684; + uint16_t _12685 = (uint16_t)(157); + _curvea0[352] = _12685; + uint16_t _12686 = (uint16_t)(157); + _curvea0[353] = _12686; + uint16_t _12687 = (uint16_t)(158); + _curvea0[354] = _12687; + uint16_t _12688 = (uint16_t)(158); + _curvea0[355] = _12688; + uint16_t _12689 = (uint16_t)(158); + _curvea0[356] = _12689; + uint16_t _12690 = (uint16_t)(159); + _curvea0[357] = _12690; + uint16_t _12691 = (uint16_t)(159); + _curvea0[358] = _12691; + uint16_t _12692 = (uint16_t)(159); + _curvea0[359] = _12692; + uint16_t _12693 = (uint16_t)(159); + _curvea0[360] = _12693; + uint16_t _12694 = (uint16_t)(160); + _curvea0[361] = _12694; + uint16_t _12695 = (uint16_t)(160); + _curvea0[362] = _12695; + uint16_t _12696 = (uint16_t)(160); + _curvea0[363] = _12696; + uint16_t _12697 = (uint16_t)(160); + _curvea0[364] = _12697; + uint16_t _12698 = (uint16_t)(161); + _curvea0[365] = _12698; + uint16_t _12699 = (uint16_t)(161); + _curvea0[366] = _12699; + uint16_t _12700 = (uint16_t)(161); + _curvea0[367] = _12700; + uint16_t _12701 = (uint16_t)(161); + _curvea0[368] = _12701; + uint16_t _12702 = (uint16_t)(162); + _curvea0[369] = _12702; + uint16_t _12703 = (uint16_t)(162); + _curvea0[370] = _12703; + uint16_t _12704 = (uint16_t)(162); + _curvea0[371] = _12704; + uint16_t _12705 = (uint16_t)(162); + _curvea0[372] = _12705; + uint16_t _12706 = (uint16_t)(163); + _curvea0[373] = _12706; + uint16_t _12707 = (uint16_t)(163); + _curvea0[374] = _12707; + uint16_t _12708 = (uint16_t)(163); + _curvea0[375] = _12708; + uint16_t _12709 = (uint16_t)(163); + _curvea0[376] = _12709; + uint16_t _12710 = (uint16_t)(164); + _curvea0[377] = _12710; + uint16_t _12711 = (uint16_t)(164); + _curvea0[378] = _12711; + uint16_t _12712 = (uint16_t)(164); + _curvea0[379] = _12712; + uint16_t _12713 = (uint16_t)(164); + _curvea0[380] = _12713; + uint16_t _12714 = (uint16_t)(165); + _curvea0[381] = _12714; + uint16_t _12715 = (uint16_t)(165); + _curvea0[382] = _12715; + uint16_t _12716 = (uint16_t)(165); + _curvea0[383] = _12716; + uint16_t _12717 = (uint16_t)(166); + _curvea0[384] = _12717; + uint16_t _12718 = (uint16_t)(166); + _curvea0[385] = _12718; + uint16_t _12719 = (uint16_t)(166); + _curvea0[386] = _12719; + uint16_t _12720 = (uint16_t)(166); + _curvea0[387] = _12720; + uint16_t _12721 = (uint16_t)(167); + _curvea0[388] = _12721; + uint16_t _12722 = (uint16_t)(167); + _curvea0[389] = _12722; + uint16_t _12723 = (uint16_t)(167); + _curvea0[390] = _12723; + uint16_t _12724 = (uint16_t)(167); + _curvea0[391] = _12724; + uint16_t _12725 = (uint16_t)(167); + _curvea0[392] = _12725; + uint16_t _12726 = (uint16_t)(168); + _curvea0[393] = _12726; + uint16_t _12727 = (uint16_t)(168); + _curvea0[394] = _12727; + uint16_t _12728 = (uint16_t)(168); + _curvea0[395] = _12728; + uint16_t _12729 = (uint16_t)(168); + _curvea0[396] = _12729; + uint16_t _12730 = (uint16_t)(169); + _curvea0[397] = _12730; + uint16_t _12731 = (uint16_t)(169); + _curvea0[398] = _12731; + uint16_t _12732 = (uint16_t)(169); + _curvea0[399] = _12732; + uint16_t _12733 = (uint16_t)(169); + _curvea0[400] = _12733; + uint16_t _12734 = (uint16_t)(170); + _curvea0[401] = _12734; + uint16_t _12735 = (uint16_t)(170); + _curvea0[402] = _12735; + uint16_t _12736 = (uint16_t)(170); + _curvea0[403] = _12736; + uint16_t _12737 = (uint16_t)(170); + _curvea0[404] = _12737; + uint16_t _12738 = (uint16_t)(171); + _curvea0[405] = _12738; + uint16_t _12739 = (uint16_t)(171); + _curvea0[406] = _12739; + uint16_t _12740 = (uint16_t)(171); + _curvea0[407] = _12740; + uint16_t _12741 = (uint16_t)(171); + _curvea0[408] = _12741; + uint16_t _12742 = (uint16_t)(172); + _curvea0[409] = _12742; + uint16_t _12743 = (uint16_t)(172); + _curvea0[410] = _12743; + uint16_t _12744 = (uint16_t)(172); + _curvea0[411] = _12744; + uint16_t _12745 = (uint16_t)(172); + _curvea0[412] = _12745; + uint16_t _12746 = (uint16_t)(173); + _curvea0[413] = _12746; + uint16_t _12747 = (uint16_t)(173); + _curvea0[414] = _12747; + uint16_t _12748 = (uint16_t)(173); + _curvea0[415] = _12748; + uint16_t _12749 = (uint16_t)(173); + _curvea0[416] = _12749; + uint16_t _12750 = (uint16_t)(173); + _curvea0[417] = _12750; + uint16_t _12751 = (uint16_t)(174); + _curvea0[418] = _12751; + uint16_t _12752 = (uint16_t)(174); + _curvea0[419] = _12752; + uint16_t _12753 = (uint16_t)(174); + _curvea0[420] = _12753; + uint16_t _12754 = (uint16_t)(174); + _curvea0[421] = _12754; + uint16_t _12755 = (uint16_t)(175); + _curvea0[422] = _12755; + uint16_t _12756 = (uint16_t)(175); + _curvea0[423] = _12756; + uint16_t _12757 = (uint16_t)(175); + _curvea0[424] = _12757; + uint16_t _12758 = (uint16_t)(175); + _curvea0[425] = _12758; + uint16_t _12759 = (uint16_t)(176); + _curvea0[426] = _12759; + uint16_t _12760 = (uint16_t)(176); + _curvea0[427] = _12760; + uint16_t _12761 = (uint16_t)(176); + _curvea0[428] = _12761; + uint16_t _12762 = (uint16_t)(176); + _curvea0[429] = _12762; + uint16_t _12763 = (uint16_t)(176); + _curvea0[430] = _12763; + uint16_t _12764 = (uint16_t)(177); + _curvea0[431] = _12764; + uint16_t _12765 = (uint16_t)(177); + _curvea0[432] = _12765; + uint16_t _12766 = (uint16_t)(177); + _curvea0[433] = _12766; + uint16_t _12767 = (uint16_t)(177); + _curvea0[434] = _12767; + uint16_t _12768 = (uint16_t)(178); + _curvea0[435] = _12768; + uint16_t _12769 = (uint16_t)(178); + _curvea0[436] = _12769; + uint16_t _12770 = (uint16_t)(178); + _curvea0[437] = _12770; + uint16_t _12771 = (uint16_t)(178); + _curvea0[438] = _12771; + uint16_t _12772 = (uint16_t)(178); + _curvea0[439] = _12772; + uint16_t _12773 = (uint16_t)(179); + _curvea0[440] = _12773; + uint16_t _12774 = (uint16_t)(179); + _curvea0[441] = _12774; + uint16_t _12775 = (uint16_t)(179); + _curvea0[442] = _12775; + uint16_t _12776 = (uint16_t)(179); + _curvea0[443] = _12776; + uint16_t _12777 = (uint16_t)(180); + _curvea0[444] = _12777; + uint16_t _12778 = (uint16_t)(180); + _curvea0[445] = _12778; + uint16_t _12779 = (uint16_t)(180); + _curvea0[446] = _12779; + uint16_t _12780 = (uint16_t)(180); + _curvea0[447] = _12780; + uint16_t _12781 = (uint16_t)(180); + _curvea0[448] = _12781; + uint16_t _12782 = (uint16_t)(181); + _curvea0[449] = _12782; + uint16_t _12783 = (uint16_t)(181); + _curvea0[450] = _12783; + uint16_t _12784 = (uint16_t)(181); + _curvea0[451] = _12784; + uint16_t _12785 = (uint16_t)(181); + _curvea0[452] = _12785; + uint16_t _12786 = (uint16_t)(181); + _curvea0[453] = _12786; + uint16_t _12787 = (uint16_t)(182); + _curvea0[454] = _12787; + uint16_t _12788 = (uint16_t)(182); + _curvea0[455] = _12788; + uint16_t _12789 = (uint16_t)(182); + _curvea0[456] = _12789; + uint16_t _12790 = (uint16_t)(182); + _curvea0[457] = _12790; + uint16_t _12791 = (uint16_t)(183); + _curvea0[458] = _12791; + uint16_t _12792 = (uint16_t)(183); + _curvea0[459] = _12792; + uint16_t _12793 = (uint16_t)(183); + _curvea0[460] = _12793; + uint16_t _12794 = (uint16_t)(183); + _curvea0[461] = _12794; + uint16_t _12795 = (uint16_t)(183); + _curvea0[462] = _12795; + uint16_t _12796 = (uint16_t)(184); + _curvea0[463] = _12796; + uint16_t _12797 = (uint16_t)(184); + _curvea0[464] = _12797; + uint16_t _12798 = (uint16_t)(184); + _curvea0[465] = _12798; + uint16_t _12799 = (uint16_t)(184); + _curvea0[466] = _12799; + uint16_t _12800 = (uint16_t)(184); + _curvea0[467] = _12800; + uint16_t _12801 = (uint16_t)(185); + _curvea0[468] = _12801; + uint16_t _12802 = (uint16_t)(185); + _curvea0[469] = _12802; + uint16_t _12803 = (uint16_t)(185); + _curvea0[470] = _12803; + uint16_t _12804 = (uint16_t)(185); + _curvea0[471] = _12804; + uint16_t _12805 = (uint16_t)(185); + _curvea0[472] = _12805; + uint16_t _12806 = (uint16_t)(186); + _curvea0[473] = _12806; + uint16_t _12807 = (uint16_t)(186); + _curvea0[474] = _12807; + uint16_t _12808 = (uint16_t)(186); + _curvea0[475] = _12808; + uint16_t _12809 = (uint16_t)(186); + _curvea0[476] = _12809; + uint16_t _12810 = (uint16_t)(187); + _curvea0[477] = _12810; + uint16_t _12811 = (uint16_t)(187); + _curvea0[478] = _12811; + uint16_t _12812 = (uint16_t)(187); + _curvea0[479] = _12812; + uint16_t _12813 = (uint16_t)(187); + _curvea0[480] = _12813; + uint16_t _12814 = (uint16_t)(187); + _curvea0[481] = _12814; + uint16_t _12815 = (uint16_t)(188); + _curvea0[482] = _12815; + uint16_t _12816 = (uint16_t)(188); + _curvea0[483] = _12816; + uint16_t _12817 = (uint16_t)(188); + _curvea0[484] = _12817; + uint16_t _12818 = (uint16_t)(188); + _curvea0[485] = _12818; + uint16_t _12819 = (uint16_t)(188); + _curvea0[486] = _12819; + uint16_t _12820 = (uint16_t)(189); + _curvea0[487] = _12820; + uint16_t _12821 = (uint16_t)(189); + _curvea0[488] = _12821; + uint16_t _12822 = (uint16_t)(189); + _curvea0[489] = _12822; + uint16_t _12823 = (uint16_t)(189); + _curvea0[490] = _12823; + uint16_t _12824 = (uint16_t)(189); + _curvea0[491] = _12824; + uint16_t _12825 = (uint16_t)(190); + _curvea0[492] = _12825; + uint16_t _12826 = (uint16_t)(190); + _curvea0[493] = _12826; + uint16_t _12827 = (uint16_t)(190); + _curvea0[494] = _12827; + uint16_t _12828 = (uint16_t)(190); + _curvea0[495] = _12828; + uint16_t _12829 = (uint16_t)(190); + _curvea0[496] = _12829; + uint16_t _12830 = (uint16_t)(190); + _curvea0[497] = _12830; + uint16_t _12831 = (uint16_t)(191); + _curvea0[498] = _12831; + uint16_t _12832 = (uint16_t)(191); + _curvea0[499] = _12832; + uint16_t _12833 = (uint16_t)(191); + _curvea0[500] = _12833; + uint16_t _12834 = (uint16_t)(191); + _curvea0[501] = _12834; + uint16_t _12835 = (uint16_t)(191); + _curvea0[502] = _12835; + uint16_t _12836 = (uint16_t)(192); + _curvea0[503] = _12836; + uint16_t _12837 = (uint16_t)(192); + _curvea0[504] = _12837; + uint16_t _12838 = (uint16_t)(192); + _curvea0[505] = _12838; + uint16_t _12839 = (uint16_t)(192); + _curvea0[506] = _12839; + uint16_t _12840 = (uint16_t)(192); + _curvea0[507] = _12840; + uint16_t _12841 = (uint16_t)(193); + _curvea0[508] = _12841; + uint16_t _12842 = (uint16_t)(193); + _curvea0[509] = _12842; + uint16_t _12843 = (uint16_t)(193); + _curvea0[510] = _12843; + uint16_t _12844 = (uint16_t)(193); + _curvea0[511] = _12844; + uint16_t _12845 = (uint16_t)(193); + _curvea0[512] = _12845; + uint16_t _12846 = (uint16_t)(194); + _curvea0[513] = _12846; + uint16_t _12847 = (uint16_t)(194); + _curvea0[514] = _12847; + uint16_t _12848 = (uint16_t)(194); + _curvea0[515] = _12848; + uint16_t _12849 = (uint16_t)(194); + _curvea0[516] = _12849; + uint16_t _12850 = (uint16_t)(194); + _curvea0[517] = _12850; + uint16_t _12851 = (uint16_t)(195); + _curvea0[518] = _12851; + uint16_t _12852 = (uint16_t)(195); + _curvea0[519] = _12852; + uint16_t _12853 = (uint16_t)(195); + _curvea0[520] = _12853; + uint16_t _12854 = (uint16_t)(195); + _curvea0[521] = _12854; + uint16_t _12855 = (uint16_t)(195); + _curvea0[522] = _12855; + uint16_t _12856 = (uint16_t)(195); + _curvea0[523] = _12856; + uint16_t _12857 = (uint16_t)(196); + _curvea0[524] = _12857; + uint16_t _12858 = (uint16_t)(196); + _curvea0[525] = _12858; + uint16_t _12859 = (uint16_t)(196); + _curvea0[526] = _12859; + uint16_t _12860 = (uint16_t)(196); + _curvea0[527] = _12860; + uint16_t _12861 = (uint16_t)(196); + _curvea0[528] = _12861; + uint16_t _12862 = (uint16_t)(197); + _curvea0[529] = _12862; + uint16_t _12863 = (uint16_t)(197); + _curvea0[530] = _12863; + uint16_t _12864 = (uint16_t)(197); + _curvea0[531] = _12864; + uint16_t _12865 = (uint16_t)(197); + _curvea0[532] = _12865; + uint16_t _12866 = (uint16_t)(197); + _curvea0[533] = _12866; + uint16_t _12867 = (uint16_t)(197); + _curvea0[534] = _12867; + uint16_t _12868 = (uint16_t)(198); + _curvea0[535] = _12868; + uint16_t _12869 = (uint16_t)(198); + _curvea0[536] = _12869; + uint16_t _12870 = (uint16_t)(198); + _curvea0[537] = _12870; + uint16_t _12871 = (uint16_t)(198); + _curvea0[538] = _12871; + uint16_t _12872 = (uint16_t)(198); + _curvea0[539] = _12872; + uint16_t _12873 = (uint16_t)(199); + _curvea0[540] = _12873; + uint16_t _12874 = (uint16_t)(199); + _curvea0[541] = _12874; + uint16_t _12875 = (uint16_t)(199); + _curvea0[542] = _12875; + uint16_t _12876 = (uint16_t)(199); + _curvea0[543] = _12876; + uint16_t _12877 = (uint16_t)(199); + _curvea0[544] = _12877; + uint16_t _12878 = (uint16_t)(199); + _curvea0[545] = _12878; + uint16_t _12879 = (uint16_t)(200); + _curvea0[546] = _12879; + uint16_t _12880 = (uint16_t)(200); + _curvea0[547] = _12880; + uint16_t _12881 = (uint16_t)(200); + _curvea0[548] = _12881; + uint16_t _12882 = (uint16_t)(200); + _curvea0[549] = _12882; + uint16_t _12883 = (uint16_t)(200); + _curvea0[550] = _12883; + uint16_t _12884 = (uint16_t)(200); + _curvea0[551] = _12884; + uint16_t _12885 = (uint16_t)(201); + _curvea0[552] = _12885; + uint16_t _12886 = (uint16_t)(201); + _curvea0[553] = _12886; + uint16_t _12887 = (uint16_t)(201); + _curvea0[554] = _12887; + uint16_t _12888 = (uint16_t)(201); + _curvea0[555] = _12888; + uint16_t _12889 = (uint16_t)(201); + _curvea0[556] = _12889; + uint16_t _12890 = (uint16_t)(202); + _curvea0[557] = _12890; + uint16_t _12891 = (uint16_t)(202); + _curvea0[558] = _12891; + uint16_t _12892 = (uint16_t)(202); + _curvea0[559] = _12892; + uint16_t _12893 = (uint16_t)(202); + _curvea0[560] = _12893; + uint16_t _12894 = (uint16_t)(202); + _curvea0[561] = _12894; + uint16_t _12895 = (uint16_t)(202); + _curvea0[562] = _12895; + uint16_t _12896 = (uint16_t)(203); + _curvea0[563] = _12896; + uint16_t _12897 = (uint16_t)(203); + _curvea0[564] = _12897; + uint16_t _12898 = (uint16_t)(203); + _curvea0[565] = _12898; + uint16_t _12899 = (uint16_t)(203); + _curvea0[566] = _12899; + uint16_t _12900 = (uint16_t)(203); + _curvea0[567] = _12900; + uint16_t _12901 = (uint16_t)(203); + _curvea0[568] = _12901; + uint16_t _12902 = (uint16_t)(204); + _curvea0[569] = _12902; + uint16_t _12903 = (uint16_t)(204); + _curvea0[570] = _12903; + uint16_t _12904 = (uint16_t)(204); + _curvea0[571] = _12904; + uint16_t _12905 = (uint16_t)(204); + _curvea0[572] = _12905; + uint16_t _12906 = (uint16_t)(204); + _curvea0[573] = _12906; + uint16_t _12907 = (uint16_t)(204); + _curvea0[574] = _12907; + uint16_t _12908 = (uint16_t)(205); + _curvea0[575] = _12908; + uint16_t _12909 = (uint16_t)(205); + _curvea0[576] = _12909; + uint16_t _12910 = (uint16_t)(205); + _curvea0[577] = _12910; + uint16_t _12911 = (uint16_t)(205); + _curvea0[578] = _12911; + uint16_t _12912 = (uint16_t)(205); + _curvea0[579] = _12912; + uint16_t _12913 = (uint16_t)(205); + _curvea0[580] = _12913; + uint16_t _12914 = (uint16_t)(206); + _curvea0[581] = _12914; + uint16_t _12915 = (uint16_t)(206); + _curvea0[582] = _12915; + uint16_t _12916 = (uint16_t)(206); + _curvea0[583] = _12916; + uint16_t _12917 = (uint16_t)(206); + _curvea0[584] = _12917; + uint16_t _12918 = (uint16_t)(206); + _curvea0[585] = _12918; + uint16_t _12919 = (uint16_t)(206); + _curvea0[586] = _12919; + uint16_t _12920 = (uint16_t)(207); + _curvea0[587] = _12920; + uint16_t _12921 = (uint16_t)(207); + _curvea0[588] = _12921; + uint16_t _12922 = (uint16_t)(207); + _curvea0[589] = _12922; + uint16_t _12923 = (uint16_t)(207); + _curvea0[590] = _12923; + uint16_t _12924 = (uint16_t)(207); + _curvea0[591] = _12924; + uint16_t _12925 = (uint16_t)(207); + _curvea0[592] = _12925; + uint16_t _12926 = (uint16_t)(208); + _curvea0[593] = _12926; + uint16_t _12927 = (uint16_t)(208); + _curvea0[594] = _12927; + uint16_t _12928 = (uint16_t)(208); + _curvea0[595] = _12928; + uint16_t _12929 = (uint16_t)(208); + _curvea0[596] = _12929; + uint16_t _12930 = (uint16_t)(208); + _curvea0[597] = _12930; + uint16_t _12931 = (uint16_t)(208); + _curvea0[598] = _12931; + uint16_t _12932 = (uint16_t)(209); + _curvea0[599] = _12932; + uint16_t _12933 = (uint16_t)(209); + _curvea0[600] = _12933; + uint16_t _12934 = (uint16_t)(209); + _curvea0[601] = _12934; + uint16_t _12935 = (uint16_t)(209); + _curvea0[602] = _12935; + uint16_t _12936 = (uint16_t)(209); + _curvea0[603] = _12936; + uint16_t _12937 = (uint16_t)(209); + _curvea0[604] = _12937; + uint16_t _12938 = (uint16_t)(209); + _curvea0[605] = _12938; + uint16_t _12939 = (uint16_t)(210); + _curvea0[606] = _12939; + uint16_t _12940 = (uint16_t)(210); + _curvea0[607] = _12940; + uint16_t _12941 = (uint16_t)(210); + _curvea0[608] = _12941; + uint16_t _12942 = (uint16_t)(210); + _curvea0[609] = _12942; + uint16_t _12943 = (uint16_t)(210); + _curvea0[610] = _12943; + uint16_t _12944 = (uint16_t)(210); + _curvea0[611] = _12944; + uint16_t _12945 = (uint16_t)(211); + _curvea0[612] = _12945; + uint16_t _12946 = (uint16_t)(211); + _curvea0[613] = _12946; + uint16_t _12947 = (uint16_t)(211); + _curvea0[614] = _12947; + uint16_t _12948 = (uint16_t)(211); + _curvea0[615] = _12948; + uint16_t _12949 = (uint16_t)(211); + _curvea0[616] = _12949; + uint16_t _12950 = (uint16_t)(211); + _curvea0[617] = _12950; + uint16_t _12951 = (uint16_t)(211); + _curvea0[618] = _12951; + uint16_t _12952 = (uint16_t)(212); + _curvea0[619] = _12952; + uint16_t _12953 = (uint16_t)(212); + _curvea0[620] = _12953; + uint16_t _12954 = (uint16_t)(212); + _curvea0[621] = _12954; + uint16_t _12955 = (uint16_t)(212); + _curvea0[622] = _12955; + uint16_t _12956 = (uint16_t)(212); + _curvea0[623] = _12956; + uint16_t _12957 = (uint16_t)(212); + _curvea0[624] = _12957; + uint16_t _12958 = (uint16_t)(213); + _curvea0[625] = _12958; + uint16_t _12959 = (uint16_t)(213); + _curvea0[626] = _12959; + uint16_t _12960 = (uint16_t)(213); + _curvea0[627] = _12960; + uint16_t _12961 = (uint16_t)(213); + _curvea0[628] = _12961; + uint16_t _12962 = (uint16_t)(213); + _curvea0[629] = _12962; + uint16_t _12963 = (uint16_t)(213); + _curvea0[630] = _12963; + uint16_t _12964 = (uint16_t)(213); + _curvea0[631] = _12964; + uint16_t _12965 = (uint16_t)(214); + _curvea0[632] = _12965; + uint16_t _12966 = (uint16_t)(214); + _curvea0[633] = _12966; + uint16_t _12967 = (uint16_t)(214); + _curvea0[634] = _12967; + uint16_t _12968 = (uint16_t)(214); + _curvea0[635] = _12968; + uint16_t _12969 = (uint16_t)(214); + _curvea0[636] = _12969; + uint16_t _12970 = (uint16_t)(214); + _curvea0[637] = _12970; + uint16_t _12971 = (uint16_t)(214); + _curvea0[638] = _12971; + uint16_t _12972 = (uint16_t)(215); + _curvea0[639] = _12972; + uint16_t _12973 = (uint16_t)(215); + _curvea0[640] = _12973; + uint16_t _12974 = (uint16_t)(215); + _curvea0[641] = _12974; + uint16_t _12975 = (uint16_t)(215); + _curvea0[642] = _12975; + uint16_t _12976 = (uint16_t)(215); + _curvea0[643] = _12976; + uint16_t _12977 = (uint16_t)(215); + _curvea0[644] = _12977; + uint16_t _12978 = (uint16_t)(216); + _curvea0[645] = _12978; + uint16_t _12979 = (uint16_t)(216); + _curvea0[646] = _12979; + uint16_t _12980 = (uint16_t)(216); + _curvea0[647] = _12980; + uint16_t _12981 = (uint16_t)(216); + _curvea0[648] = _12981; + uint16_t _12982 = (uint16_t)(216); + _curvea0[649] = _12982; + uint16_t _12983 = (uint16_t)(216); + _curvea0[650] = _12983; + uint16_t _12984 = (uint16_t)(216); + _curvea0[651] = _12984; + uint16_t _12985 = (uint16_t)(217); + _curvea0[652] = _12985; + uint16_t _12986 = (uint16_t)(217); + _curvea0[653] = _12986; + uint16_t _12987 = (uint16_t)(217); + _curvea0[654] = _12987; + uint16_t _12988 = (uint16_t)(217); + _curvea0[655] = _12988; + uint16_t _12989 = (uint16_t)(217); + _curvea0[656] = _12989; + uint16_t _12990 = (uint16_t)(217); + _curvea0[657] = _12990; + uint16_t _12991 = (uint16_t)(217); + _curvea0[658] = _12991; + uint16_t _12992 = (uint16_t)(218); + _curvea0[659] = _12992; + uint16_t _12993 = (uint16_t)(218); + _curvea0[660] = _12993; + uint16_t _12994 = (uint16_t)(218); + _curvea0[661] = _12994; + uint16_t _12995 = (uint16_t)(218); + _curvea0[662] = _12995; + uint16_t _12996 = (uint16_t)(218); + _curvea0[663] = _12996; + uint16_t _12997 = (uint16_t)(218); + _curvea0[664] = _12997; + uint16_t _12998 = (uint16_t)(218); + _curvea0[665] = _12998; + uint16_t _12999 = (uint16_t)(219); + _curvea0[666] = _12999; + uint16_t _13000 = (uint16_t)(219); + _curvea0[667] = _13000; + uint16_t _13001 = (uint16_t)(219); + _curvea0[668] = _13001; + uint16_t _13002 = (uint16_t)(219); + _curvea0[669] = _13002; + uint16_t _13003 = (uint16_t)(219); + _curvea0[670] = _13003; + uint16_t _13004 = (uint16_t)(219); + _curvea0[671] = _13004; + uint16_t _13005 = (uint16_t)(219); + _curvea0[672] = _13005; + uint16_t _13006 = (uint16_t)(220); + _curvea0[673] = _13006; + uint16_t _13007 = (uint16_t)(220); + _curvea0[674] = _13007; + uint16_t _13008 = (uint16_t)(220); + _curvea0[675] = _13008; + uint16_t _13009 = (uint16_t)(220); + _curvea0[676] = _13009; + uint16_t _13010 = (uint16_t)(220); + _curvea0[677] = _13010; + uint16_t _13011 = (uint16_t)(220); + _curvea0[678] = _13011; + uint16_t _13012 = (uint16_t)(220); + _curvea0[679] = _13012; + uint16_t _13013 = (uint16_t)(220); + _curvea0[680] = _13013; + uint16_t _13014 = (uint16_t)(221); + _curvea0[681] = _13014; + uint16_t _13015 = (uint16_t)(221); + _curvea0[682] = _13015; + uint16_t _13016 = (uint16_t)(221); + _curvea0[683] = _13016; + uint16_t _13017 = (uint16_t)(221); + _curvea0[684] = _13017; + uint16_t _13018 = (uint16_t)(221); + _curvea0[685] = _13018; + uint16_t _13019 = (uint16_t)(221); + _curvea0[686] = _13019; + uint16_t _13020 = (uint16_t)(221); + _curvea0[687] = _13020; + uint16_t _13021 = (uint16_t)(222); + _curvea0[688] = _13021; + uint16_t _13022 = (uint16_t)(222); + _curvea0[689] = _13022; + uint16_t _13023 = (uint16_t)(222); + _curvea0[690] = _13023; + uint16_t _13024 = (uint16_t)(222); + _curvea0[691] = _13024; + uint16_t _13025 = (uint16_t)(222); + _curvea0[692] = _13025; + uint16_t _13026 = (uint16_t)(222); + _curvea0[693] = _13026; + uint16_t _13027 = (uint16_t)(222); + _curvea0[694] = _13027; + uint16_t _13028 = (uint16_t)(223); + _curvea0[695] = _13028; + uint16_t _13029 = (uint16_t)(223); + _curvea0[696] = _13029; + uint16_t _13030 = (uint16_t)(223); + _curvea0[697] = _13030; + uint16_t _13031 = (uint16_t)(223); + _curvea0[698] = _13031; + uint16_t _13032 = (uint16_t)(223); + _curvea0[699] = _13032; + uint16_t _13033 = (uint16_t)(223); + _curvea0[700] = _13033; + uint16_t _13034 = (uint16_t)(223); + _curvea0[701] = _13034; + uint16_t _13035 = (uint16_t)(223); + _curvea0[702] = _13035; + uint16_t _13036 = (uint16_t)(224); + _curvea0[703] = _13036; + uint16_t _13037 = (uint16_t)(224); + _curvea0[704] = _13037; + uint16_t _13038 = (uint16_t)(224); + _curvea0[705] = _13038; + uint16_t _13039 = (uint16_t)(224); + _curvea0[706] = _13039; + uint16_t _13040 = (uint16_t)(224); + _curvea0[707] = _13040; + uint16_t _13041 = (uint16_t)(224); + _curvea0[708] = _13041; + uint16_t _13042 = (uint16_t)(224); + _curvea0[709] = _13042; + uint16_t _13043 = (uint16_t)(224); + _curvea0[710] = _13043; + uint16_t _13044 = (uint16_t)(225); + _curvea0[711] = _13044; + uint16_t _13045 = (uint16_t)(225); + _curvea0[712] = _13045; + uint16_t _13046 = (uint16_t)(225); + _curvea0[713] = _13046; + uint16_t _13047 = (uint16_t)(225); + _curvea0[714] = _13047; + uint16_t _13048 = (uint16_t)(225); + _curvea0[715] = _13048; + uint16_t _13049 = (uint16_t)(225); + _curvea0[716] = _13049; + uint16_t _13050 = (uint16_t)(225); + _curvea0[717] = _13050; + uint16_t _13051 = (uint16_t)(226); + _curvea0[718] = _13051; + uint16_t _13052 = (uint16_t)(226); + _curvea0[719] = _13052; + uint16_t _13053 = (uint16_t)(226); + _curvea0[720] = _13053; + uint16_t _13054 = (uint16_t)(226); + _curvea0[721] = _13054; + uint16_t _13055 = (uint16_t)(226); + _curvea0[722] = _13055; + uint16_t _13056 = (uint16_t)(226); + _curvea0[723] = _13056; + uint16_t _13057 = (uint16_t)(226); + _curvea0[724] = _13057; + uint16_t _13058 = (uint16_t)(226); + _curvea0[725] = _13058; + uint16_t _13059 = (uint16_t)(227); + _curvea0[726] = _13059; + uint16_t _13060 = (uint16_t)(227); + _curvea0[727] = _13060; + uint16_t _13061 = (uint16_t)(227); + _curvea0[728] = _13061; + uint16_t _13062 = (uint16_t)(227); + _curvea0[729] = _13062; + uint16_t _13063 = (uint16_t)(227); + _curvea0[730] = _13063; + uint16_t _13064 = (uint16_t)(227); + _curvea0[731] = _13064; + uint16_t _13065 = (uint16_t)(227); + _curvea0[732] = _13065; + uint16_t _13066 = (uint16_t)(227); + _curvea0[733] = _13066; + uint16_t _13067 = (uint16_t)(228); + _curvea0[734] = _13067; + uint16_t _13068 = (uint16_t)(228); + _curvea0[735] = _13068; + uint16_t _13069 = (uint16_t)(228); + _curvea0[736] = _13069; + uint16_t _13070 = (uint16_t)(228); + _curvea0[737] = _13070; + uint16_t _13071 = (uint16_t)(228); + _curvea0[738] = _13071; + uint16_t _13072 = (uint16_t)(228); + _curvea0[739] = _13072; + uint16_t _13073 = (uint16_t)(228); + _curvea0[740] = _13073; + uint16_t _13074 = (uint16_t)(228); + _curvea0[741] = _13074; + uint16_t _13075 = (uint16_t)(228); + _curvea0[742] = _13075; + uint16_t _13076 = (uint16_t)(229); + _curvea0[743] = _13076; + uint16_t _13077 = (uint16_t)(229); + _curvea0[744] = _13077; + uint16_t _13078 = (uint16_t)(229); + _curvea0[745] = _13078; + uint16_t _13079 = (uint16_t)(229); + _curvea0[746] = _13079; + uint16_t _13080 = (uint16_t)(229); + _curvea0[747] = _13080; + uint16_t _13081 = (uint16_t)(229); + _curvea0[748] = _13081; + uint16_t _13082 = (uint16_t)(229); + _curvea0[749] = _13082; + uint16_t _13083 = (uint16_t)(229); + _curvea0[750] = _13083; + uint16_t _13084 = (uint16_t)(230); + _curvea0[751] = _13084; + uint16_t _13085 = (uint16_t)(230); + _curvea0[752] = _13085; + uint16_t _13086 = (uint16_t)(230); + _curvea0[753] = _13086; + uint16_t _13087 = (uint16_t)(230); + _curvea0[754] = _13087; + uint16_t _13088 = (uint16_t)(230); + _curvea0[755] = _13088; + uint16_t _13089 = (uint16_t)(230); + _curvea0[756] = _13089; + uint16_t _13090 = (uint16_t)(230); + _curvea0[757] = _13090; + uint16_t _13091 = (uint16_t)(230); + _curvea0[758] = _13091; + uint16_t _13092 = (uint16_t)(231); + _curvea0[759] = _13092; + uint16_t _13093 = (uint16_t)(231); + _curvea0[760] = _13093; + uint16_t _13094 = (uint16_t)(231); + _curvea0[761] = _13094; + uint16_t _13095 = (uint16_t)(231); + _curvea0[762] = _13095; + uint16_t _13096 = (uint16_t)(231); + _curvea0[763] = _13096; + uint16_t _13097 = (uint16_t)(231); + _curvea0[764] = _13097; + uint16_t _13098 = (uint16_t)(231); + _curvea0[765] = _13098; + uint16_t _13099 = (uint16_t)(231); + _curvea0[766] = _13099; + uint16_t _13100 = (uint16_t)(231); + _curvea0[767] = _13100; + uint16_t _13101 = (uint16_t)(232); + _curvea0[768] = _13101; + uint16_t _13102 = (uint16_t)(232); + _curvea0[769] = _13102; + uint16_t _13103 = (uint16_t)(232); + _curvea0[770] = _13103; + uint16_t _13104 = (uint16_t)(232); + _curvea0[771] = _13104; + uint16_t _13105 = (uint16_t)(232); + _curvea0[772] = _13105; + uint16_t _13106 = (uint16_t)(232); + _curvea0[773] = _13106; + uint16_t _13107 = (uint16_t)(232); + _curvea0[774] = _13107; + uint16_t _13108 = (uint16_t)(232); + _curvea0[775] = _13108; + uint16_t _13109 = (uint16_t)(233); + _curvea0[776] = _13109; + uint16_t _13110 = (uint16_t)(233); + _curvea0[777] = _13110; + uint16_t _13111 = (uint16_t)(233); + _curvea0[778] = _13111; + uint16_t _13112 = (uint16_t)(233); + _curvea0[779] = _13112; + uint16_t _13113 = (uint16_t)(233); + _curvea0[780] = _13113; + uint16_t _13114 = (uint16_t)(233); + _curvea0[781] = _13114; + uint16_t _13115 = (uint16_t)(233); + _curvea0[782] = _13115; + uint16_t _13116 = (uint16_t)(233); + _curvea0[783] = _13116; + uint16_t _13117 = (uint16_t)(233); + _curvea0[784] = _13117; + uint16_t _13118 = (uint16_t)(234); + _curvea0[785] = _13118; + uint16_t _13119 = (uint16_t)(234); + _curvea0[786] = _13119; + uint16_t _13120 = (uint16_t)(234); + _curvea0[787] = _13120; + uint16_t _13121 = (uint16_t)(234); + _curvea0[788] = _13121; + uint16_t _13122 = (uint16_t)(234); + _curvea0[789] = _13122; + uint16_t _13123 = (uint16_t)(234); + _curvea0[790] = _13123; + uint16_t _13124 = (uint16_t)(234); + _curvea0[791] = _13124; + uint16_t _13125 = (uint16_t)(234); + _curvea0[792] = _13125; + uint16_t _13126 = (uint16_t)(234); + _curvea0[793] = _13126; + uint16_t _13127 = (uint16_t)(235); + _curvea0[794] = _13127; + uint16_t _13128 = (uint16_t)(235); + _curvea0[795] = _13128; + uint16_t _13129 = (uint16_t)(235); + _curvea0[796] = _13129; + uint16_t _13130 = (uint16_t)(235); + _curvea0[797] = _13130; + uint16_t _13131 = (uint16_t)(235); + _curvea0[798] = _13131; + uint16_t _13132 = (uint16_t)(235); + _curvea0[799] = _13132; + uint16_t _13133 = (uint16_t)(235); + _curvea0[800] = _13133; + uint16_t _13134 = (uint16_t)(235); + _curvea0[801] = _13134; + uint16_t _13135 = (uint16_t)(235); + _curvea0[802] = _13135; + uint16_t _13136 = (uint16_t)(236); + _curvea0[803] = _13136; + uint16_t _13137 = (uint16_t)(236); + _curvea0[804] = _13137; + uint16_t _13138 = (uint16_t)(236); + _curvea0[805] = _13138; + uint16_t _13139 = (uint16_t)(236); + _curvea0[806] = _13139; + uint16_t _13140 = (uint16_t)(236); + _curvea0[807] = _13140; + uint16_t _13141 = (uint16_t)(236); + _curvea0[808] = _13141; + uint16_t _13142 = (uint16_t)(236); + _curvea0[809] = _13142; + uint16_t _13143 = (uint16_t)(236); + _curvea0[810] = _13143; + uint16_t _13144 = (uint16_t)(236); + _curvea0[811] = _13144; + uint16_t _13145 = (uint16_t)(237); + _curvea0[812] = _13145; + uint16_t _13146 = (uint16_t)(237); + _curvea0[813] = _13146; + uint16_t _13147 = (uint16_t)(237); + _curvea0[814] = _13147; + uint16_t _13148 = (uint16_t)(237); + _curvea0[815] = _13148; + uint16_t _13149 = (uint16_t)(237); + _curvea0[816] = _13149; + uint16_t _13150 = (uint16_t)(237); + _curvea0[817] = _13150; + uint16_t _13151 = (uint16_t)(237); + _curvea0[818] = _13151; + uint16_t _13152 = (uint16_t)(237); + _curvea0[819] = _13152; + uint16_t _13153 = (uint16_t)(237); + _curvea0[820] = _13153; + uint16_t _13154 = (uint16_t)(237); + _curvea0[821] = _13154; + uint16_t _13155 = (uint16_t)(238); + _curvea0[822] = _13155; + uint16_t _13156 = (uint16_t)(238); + _curvea0[823] = _13156; + uint16_t _13157 = (uint16_t)(238); + _curvea0[824] = _13157; + uint16_t _13158 = (uint16_t)(238); + _curvea0[825] = _13158; + uint16_t _13159 = (uint16_t)(238); + _curvea0[826] = _13159; + uint16_t _13160 = (uint16_t)(238); + _curvea0[827] = _13160; + uint16_t _13161 = (uint16_t)(238); + _curvea0[828] = _13161; + uint16_t _13162 = (uint16_t)(238); + _curvea0[829] = _13162; + uint16_t _13163 = (uint16_t)(238); + _curvea0[830] = _13163; + uint16_t _13164 = (uint16_t)(239); + _curvea0[831] = _13164; + uint16_t _13165 = (uint16_t)(239); + _curvea0[832] = _13165; + uint16_t _13166 = (uint16_t)(239); + _curvea0[833] = _13166; + uint16_t _13167 = (uint16_t)(239); + _curvea0[834] = _13167; + uint16_t _13168 = (uint16_t)(239); + _curvea0[835] = _13168; + uint16_t _13169 = (uint16_t)(239); + _curvea0[836] = _13169; + uint16_t _13170 = (uint16_t)(239); + _curvea0[837] = _13170; + uint16_t _13171 = (uint16_t)(239); + _curvea0[838] = _13171; + uint16_t _13172 = (uint16_t)(239); + _curvea0[839] = _13172; + uint16_t _13173 = (uint16_t)(239); + _curvea0[840] = _13173; + uint16_t _13174 = (uint16_t)(240); + _curvea0[841] = _13174; + uint16_t _13175 = (uint16_t)(240); + _curvea0[842] = _13175; + uint16_t _13176 = (uint16_t)(240); + _curvea0[843] = _13176; + uint16_t _13177 = (uint16_t)(240); + _curvea0[844] = _13177; + uint16_t _13178 = (uint16_t)(240); + _curvea0[845] = _13178; + uint16_t _13179 = (uint16_t)(240); + _curvea0[846] = _13179; + uint16_t _13180 = (uint16_t)(240); + _curvea0[847] = _13180; + uint16_t _13181 = (uint16_t)(240); + _curvea0[848] = _13181; + uint16_t _13182 = (uint16_t)(240); + _curvea0[849] = _13182; + uint16_t _13183 = (uint16_t)(240); + _curvea0[850] = _13183; + uint16_t _13184 = (uint16_t)(241); + _curvea0[851] = _13184; + uint16_t _13185 = (uint16_t)(241); + _curvea0[852] = _13185; + uint16_t _13186 = (uint16_t)(241); + _curvea0[853] = _13186; + uint16_t _13187 = (uint16_t)(241); + _curvea0[854] = _13187; + uint16_t _13188 = (uint16_t)(241); + _curvea0[855] = _13188; + uint16_t _13189 = (uint16_t)(241); + _curvea0[856] = _13189; + uint16_t _13190 = (uint16_t)(241); + _curvea0[857] = _13190; + uint16_t _13191 = (uint16_t)(241); + _curvea0[858] = _13191; + uint16_t _13192 = (uint16_t)(241); + _curvea0[859] = _13192; + uint16_t _13193 = (uint16_t)(241); + _curvea0[860] = _13193; + uint16_t _13194 = (uint16_t)(242); + _curvea0[861] = _13194; + uint16_t _13195 = (uint16_t)(242); + _curvea0[862] = _13195; + uint16_t _13196 = (uint16_t)(242); + _curvea0[863] = _13196; + uint16_t _13197 = (uint16_t)(242); + _curvea0[864] = _13197; + uint16_t _13198 = (uint16_t)(242); + _curvea0[865] = _13198; + uint16_t _13199 = (uint16_t)(242); + _curvea0[866] = _13199; + uint16_t _13200 = (uint16_t)(242); + _curvea0[867] = _13200; + uint16_t _13201 = (uint16_t)(242); + _curvea0[868] = _13201; + uint16_t _13202 = (uint16_t)(242); + _curvea0[869] = _13202; + uint16_t _13203 = (uint16_t)(242); + _curvea0[870] = _13203; + uint16_t _13204 = (uint16_t)(243); + _curvea0[871] = _13204; + uint16_t _13205 = (uint16_t)(243); + _curvea0[872] = _13205; + uint16_t _13206 = (uint16_t)(243); + _curvea0[873] = _13206; + uint16_t _13207 = (uint16_t)(243); + _curvea0[874] = _13207; + uint16_t _13208 = (uint16_t)(243); + _curvea0[875] = _13208; + uint16_t _13209 = (uint16_t)(243); + _curvea0[876] = _13209; + uint16_t _13210 = (uint16_t)(243); + _curvea0[877] = _13210; + uint16_t _13211 = (uint16_t)(243); + _curvea0[878] = _13211; + uint16_t _13212 = (uint16_t)(243); + _curvea0[879] = _13212; + uint16_t _13213 = (uint16_t)(243); + _curvea0[880] = _13213; + uint16_t _13214 = (uint16_t)(244); + _curvea0[881] = _13214; + uint16_t _13215 = (uint16_t)(244); + _curvea0[882] = _13215; + uint16_t _13216 = (uint16_t)(244); + _curvea0[883] = _13216; + uint16_t _13217 = (uint16_t)(244); + _curvea0[884] = _13217; + uint16_t _13218 = (uint16_t)(244); + _curvea0[885] = _13218; + uint16_t _13219 = (uint16_t)(244); + _curvea0[886] = _13219; + uint16_t _13220 = (uint16_t)(244); + _curvea0[887] = _13220; + uint16_t _13221 = (uint16_t)(244); + _curvea0[888] = _13221; + uint16_t _13222 = (uint16_t)(244); + _curvea0[889] = _13222; + uint16_t _13223 = (uint16_t)(244); + _curvea0[890] = _13223; + uint16_t _13224 = (uint16_t)(244); + _curvea0[891] = _13224; + uint16_t _13225 = (uint16_t)(245); + _curvea0[892] = _13225; + uint16_t _13226 = (uint16_t)(245); + _curvea0[893] = _13226; + uint16_t _13227 = (uint16_t)(245); + _curvea0[894] = _13227; + uint16_t _13228 = (uint16_t)(245); + _curvea0[895] = _13228; + uint16_t _13229 = (uint16_t)(245); + _curvea0[896] = _13229; + uint16_t _13230 = (uint16_t)(245); + _curvea0[897] = _13230; + uint16_t _13231 = (uint16_t)(245); + _curvea0[898] = _13231; + uint16_t _13232 = (uint16_t)(245); + _curvea0[899] = _13232; + uint16_t _13233 = (uint16_t)(245); + _curvea0[900] = _13233; + uint16_t _13234 = (uint16_t)(245); + _curvea0[901] = _13234; + uint16_t _13235 = (uint16_t)(245); + _curvea0[902] = _13235; + uint16_t _13236 = (uint16_t)(246); + _curvea0[903] = _13236; + uint16_t _13237 = (uint16_t)(246); + _curvea0[904] = _13237; + uint16_t _13238 = (uint16_t)(246); + _curvea0[905] = _13238; + uint16_t _13239 = (uint16_t)(246); + _curvea0[906] = _13239; + uint16_t _13240 = (uint16_t)(246); + _curvea0[907] = _13240; + uint16_t _13241 = (uint16_t)(246); + _curvea0[908] = _13241; + uint16_t _13242 = (uint16_t)(246); + _curvea0[909] = _13242; + uint16_t _13243 = (uint16_t)(246); + _curvea0[910] = _13243; + uint16_t _13244 = (uint16_t)(246); + _curvea0[911] = _13244; + uint16_t _13245 = (uint16_t)(246); + _curvea0[912] = _13245; + uint16_t _13246 = (uint16_t)(246); + _curvea0[913] = _13246; + uint16_t _13247 = (uint16_t)(247); + _curvea0[914] = _13247; + uint16_t _13248 = (uint16_t)(247); + _curvea0[915] = _13248; + uint16_t _13249 = (uint16_t)(247); + _curvea0[916] = _13249; + uint16_t _13250 = (uint16_t)(247); + _curvea0[917] = _13250; + uint16_t _13251 = (uint16_t)(247); + _curvea0[918] = _13251; + uint16_t _13252 = (uint16_t)(247); + _curvea0[919] = _13252; + uint16_t _13253 = (uint16_t)(247); + _curvea0[920] = _13253; + uint16_t _13254 = (uint16_t)(247); + _curvea0[921] = _13254; + uint16_t _13255 = (uint16_t)(247); + _curvea0[922] = _13255; + uint16_t _13256 = (uint16_t)(247); + _curvea0[923] = _13256; + uint16_t _13257 = (uint16_t)(247); + _curvea0[924] = _13257; + uint16_t _13258 = (uint16_t)(248); + _curvea0[925] = _13258; + uint16_t _13259 = (uint16_t)(248); + _curvea0[926] = _13259; + uint16_t _13260 = (uint16_t)(248); + _curvea0[927] = _13260; + uint16_t _13261 = (uint16_t)(248); + _curvea0[928] = _13261; + uint16_t _13262 = (uint16_t)(248); + _curvea0[929] = _13262; + uint16_t _13263 = (uint16_t)(248); + _curvea0[930] = _13263; + uint16_t _13264 = (uint16_t)(248); + _curvea0[931] = _13264; + uint16_t _13265 = (uint16_t)(248); + _curvea0[932] = _13265; + uint16_t _13266 = (uint16_t)(248); + _curvea0[933] = _13266; + uint16_t _13267 = (uint16_t)(248); + _curvea0[934] = _13267; + uint16_t _13268 = (uint16_t)(248); + _curvea0[935] = _13268; + uint16_t _13269 = (uint16_t)(249); + _curvea0[936] = _13269; + uint16_t _13270 = (uint16_t)(249); + _curvea0[937] = _13270; + uint16_t _13271 = (uint16_t)(249); + _curvea0[938] = _13271; + uint16_t _13272 = (uint16_t)(249); + _curvea0[939] = _13272; + uint16_t _13273 = (uint16_t)(249); + _curvea0[940] = _13273; + uint16_t _13274 = (uint16_t)(249); + _curvea0[941] = _13274; + uint16_t _13275 = (uint16_t)(249); + _curvea0[942] = _13275; + uint16_t _13276 = (uint16_t)(249); + _curvea0[943] = _13276; + uint16_t _13277 = (uint16_t)(249); + _curvea0[944] = _13277; + uint16_t _13278 = (uint16_t)(249); + _curvea0[945] = _13278; + uint16_t _13279 = (uint16_t)(249); + _curvea0[946] = _13279; + uint16_t _13280 = (uint16_t)(249); + _curvea0[947] = _13280; + uint16_t _13281 = (uint16_t)(250); + _curvea0[948] = _13281; + uint16_t _13282 = (uint16_t)(250); + _curvea0[949] = _13282; + uint16_t _13283 = (uint16_t)(250); + _curvea0[950] = _13283; + uint16_t _13284 = (uint16_t)(250); + _curvea0[951] = _13284; + uint16_t _13285 = (uint16_t)(250); + _curvea0[952] = _13285; + uint16_t _13286 = (uint16_t)(250); + _curvea0[953] = _13286; + uint16_t _13287 = (uint16_t)(250); + _curvea0[954] = _13287; + uint16_t _13288 = (uint16_t)(250); + _curvea0[955] = _13288; + uint16_t _13289 = (uint16_t)(250); + _curvea0[956] = _13289; + uint16_t _13290 = (uint16_t)(250); + _curvea0[957] = _13290; + uint16_t _13291 = (uint16_t)(250); + _curvea0[958] = _13291; + uint16_t _13292 = (uint16_t)(250); + _curvea0[959] = _13292; + uint16_t _13293 = (uint16_t)(251); + _curvea0[960] = _13293; + uint16_t _13294 = (uint16_t)(251); + _curvea0[961] = _13294; + uint16_t _13295 = (uint16_t)(251); + _curvea0[962] = _13295; + uint16_t _13296 = (uint16_t)(251); + _curvea0[963] = _13296; + uint16_t _13297 = (uint16_t)(251); + _curvea0[964] = _13297; + uint16_t _13298 = (uint16_t)(251); + _curvea0[965] = _13298; + uint16_t _13299 = (uint16_t)(251); + _curvea0[966] = _13299; + uint16_t _13300 = (uint16_t)(251); + _curvea0[967] = _13300; + uint16_t _13301 = (uint16_t)(251); + _curvea0[968] = _13301; + uint16_t _13302 = (uint16_t)(251); + _curvea0[969] = _13302; + uint16_t _13303 = (uint16_t)(251); + _curvea0[970] = _13303; + uint16_t _13304 = (uint16_t)(251); + _curvea0[971] = _13304; + uint16_t _13305 = (uint16_t)(252); + _curvea0[972] = _13305; + uint16_t _13306 = (uint16_t)(252); + _curvea0[973] = _13306; + uint16_t _13307 = (uint16_t)(252); + _curvea0[974] = _13307; + uint16_t _13308 = (uint16_t)(252); + _curvea0[975] = _13308; + uint16_t _13309 = (uint16_t)(252); + _curvea0[976] = _13309; + uint16_t _13310 = (uint16_t)(252); + _curvea0[977] = _13310; + uint16_t _13311 = (uint16_t)(252); + _curvea0[978] = _13311; + uint16_t _13312 = (uint16_t)(252); + _curvea0[979] = _13312; + uint16_t _13313 = (uint16_t)(252); + _curvea0[980] = _13313; + uint16_t _13314 = (uint16_t)(252); + _curvea0[981] = _13314; + uint16_t _13315 = (uint16_t)(252); + _curvea0[982] = _13315; + uint16_t _13316 = (uint16_t)(252); + _curvea0[983] = _13316; + uint16_t _13317 = (uint16_t)(252); + _curvea0[984] = _13317; + uint16_t _13318 = (uint16_t)(253); + _curvea0[985] = _13318; + uint16_t _13319 = (uint16_t)(253); + _curvea0[986] = _13319; + uint16_t _13320 = (uint16_t)(253); + _curvea0[987] = _13320; + uint16_t _13321 = (uint16_t)(253); + _curvea0[988] = _13321; + uint16_t _13322 = (uint16_t)(253); + _curvea0[989] = _13322; + uint16_t _13323 = (uint16_t)(253); + _curvea0[990] = _13323; + uint16_t _13324 = (uint16_t)(253); + _curvea0[991] = _13324; + uint16_t _13325 = (uint16_t)(253); + _curvea0[992] = _13325; + uint16_t _13326 = (uint16_t)(253); + _curvea0[993] = _13326; + uint16_t _13327 = (uint16_t)(253); + _curvea0[994] = _13327; + uint16_t _13328 = (uint16_t)(253); + _curvea0[995] = _13328; + uint16_t _13329 = (uint16_t)(253); + _curvea0[996] = _13329; + uint16_t _13330 = (uint16_t)(253); + _curvea0[997] = _13330; + uint16_t _13331 = (uint16_t)(254); + _curvea0[998] = _13331; + uint16_t _13332 = (uint16_t)(254); + _curvea0[999] = _13332; + uint16_t _13333 = (uint16_t)(254); + _curvea0[1000] = _13333; + uint16_t _13334 = (uint16_t)(254); + _curvea0[1001] = _13334; + uint16_t _13335 = (uint16_t)(254); + _curvea0[1002] = _13335; + uint16_t _13336 = (uint16_t)(254); + _curvea0[1003] = _13336; + uint16_t _13337 = (uint16_t)(254); + _curvea0[1004] = _13337; + uint16_t _13338 = (uint16_t)(254); + _curvea0[1005] = _13338; + uint16_t _13339 = (uint16_t)(254); + _curvea0[1006] = _13339; + uint16_t _13340 = (uint16_t)(254); + _curvea0[1007] = _13340; + uint16_t _13341 = (uint16_t)(254); + _curvea0[1008] = _13341; + uint16_t _13342 = (uint16_t)(254); + _curvea0[1009] = _13342; + uint16_t _13343 = (uint16_t)(254); + _curvea0[1010] = _13343; + uint16_t _13344 = (uint16_t)(255); + _curvea0[1011] = _13344; + uint16_t _13345 = (uint16_t)(255); + _curvea0[1012] = _13345; + uint16_t _13346 = (uint16_t)(255); + _curvea0[1013] = _13346; + uint16_t _13347 = (uint16_t)(255); + _curvea0[1014] = _13347; + uint16_t _13348 = (uint16_t)(255); + _curvea0[1015] = _13348; + uint16_t _13349 = (uint16_t)(255); + _curvea0[1016] = _13349; + uint16_t _13350 = (uint16_t)(255); + _curvea0[1017] = _13350; + uint16_t _13351 = (uint16_t)(255); + _curvea0[1018] = _13351; + uint16_t _13352 = (uint16_t)(255); + _curvea0[1019] = _13352; + uint16_t _13353 = (uint16_t)(255); + _curvea0[1020] = _13353; + uint16_t _13354 = (uint16_t)(255); + _curvea0[1021] = _13354; + uint16_t _13355 = (uint16_t)(255); + _curvea0[1022] = _13355; + uint16_t _13356 = (uint16_t)(255); + _curvea0[1023] = _13356; + + int16_t _13357 = (int16_t)(1023); + int16_t _13358 = min(_corrected_stencil_9, _13357); + int16_t _13359 = (int16_t)(0); + int16_t _13360 = max(_13358, _13359); + uint16_t _13361 = (uint16_t)(_13360); + int32_t _13362 = (int32_t)(_13361); + uint16_t _13363 = ((const uint16_t *)_curvea0)[_13362]; + return _13363; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_9(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_10 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _13381 = (uint16_t)(0); + _curvea0[0] = _13381; + uint16_t _13382 = (uint16_t)(4); + _curvea0[1] = _13382; + uint16_t _13383 = (uint16_t)(7); + _curvea0[2] = _13383; + uint16_t _13384 = (uint16_t)(8); + _curvea0[3] = _13384; + uint16_t _13385 = (uint16_t)(10); + _curvea0[4] = _13385; + uint16_t _13386 = (uint16_t)(11); + _curvea0[5] = _13386; + uint16_t _13387 = (uint16_t)(12); + _curvea0[6] = _13387; + uint16_t _13388 = (uint16_t)(13); + _curvea0[7] = _13388; + uint16_t _13389 = (uint16_t)(14); + _curvea0[8] = _13389; + uint16_t _13390 = (uint16_t)(15); + _curvea0[9] = _13390; + uint16_t _13391 = (uint16_t)(16); + _curvea0[10] = _13391; + uint16_t _13392 = (uint16_t)(17); + _curvea0[11] = _13392; + uint16_t _13393 = (uint16_t)(18); + _curvea0[12] = _13393; + uint16_t _13394 = (uint16_t)(19); + _curvea0[13] = _13394; + uint16_t _13395 = (uint16_t)(20); + _curvea0[14] = _13395; + uint16_t _13396 = (uint16_t)(21); + _curvea0[15] = _13396; + uint16_t _13397 = (uint16_t)(22); + _curvea0[16] = _13397; + uint16_t _13398 = (uint16_t)(22); + _curvea0[17] = _13398; + uint16_t _13399 = (uint16_t)(23); + _curvea0[18] = _13399; + uint16_t _13400 = (uint16_t)(24); + _curvea0[19] = _13400; + uint16_t _13401 = (uint16_t)(25); + _curvea0[20] = _13401; + uint16_t _13402 = (uint16_t)(25); + _curvea0[21] = _13402; + uint16_t _13403 = (uint16_t)(26); + _curvea0[22] = _13403; + uint16_t _13404 = (uint16_t)(27); + _curvea0[23] = _13404; + uint16_t _13405 = (uint16_t)(27); + _curvea0[24] = _13405; + uint16_t _13406 = (uint16_t)(28); + _curvea0[25] = _13406; + uint16_t _13407 = (uint16_t)(29); + _curvea0[26] = _13407; + uint16_t _13408 = (uint16_t)(29); + _curvea0[27] = _13408; + uint16_t _13409 = (uint16_t)(30); + _curvea0[28] = _13409; + uint16_t _13410 = (uint16_t)(31); + _curvea0[29] = _13410; + uint16_t _13411 = (uint16_t)(31); + _curvea0[30] = _13411; + uint16_t _13412 = (uint16_t)(32); + _curvea0[31] = _13412; + uint16_t _13413 = (uint16_t)(33); + _curvea0[32] = _13413; + uint16_t _13414 = (uint16_t)(33); + _curvea0[33] = _13414; + uint16_t _13415 = (uint16_t)(34); + _curvea0[34] = _13415; + uint16_t _13416 = (uint16_t)(34); + _curvea0[35] = _13416; + uint16_t _13417 = (uint16_t)(35); + _curvea0[36] = _13417; + uint16_t _13418 = (uint16_t)(36); + _curvea0[37] = _13418; + uint16_t _13419 = (uint16_t)(36); + _curvea0[38] = _13419; + uint16_t _13420 = (uint16_t)(37); + _curvea0[39] = _13420; + uint16_t _13421 = (uint16_t)(37); + _curvea0[40] = _13421; + uint16_t _13422 = (uint16_t)(38); + _curvea0[41] = _13422; + uint16_t _13423 = (uint16_t)(39); + _curvea0[42] = _13423; + uint16_t _13424 = (uint16_t)(39); + _curvea0[43] = _13424; + uint16_t _13425 = (uint16_t)(40); + _curvea0[44] = _13425; + uint16_t _13426 = (uint16_t)(40); + _curvea0[45] = _13426; + uint16_t _13427 = (uint16_t)(41); + _curvea0[46] = _13427; + uint16_t _13428 = (uint16_t)(41); + _curvea0[47] = _13428; + uint16_t _13429 = (uint16_t)(42); + _curvea0[48] = _13429; + uint16_t _13430 = (uint16_t)(42); + _curvea0[49] = _13430; + uint16_t _13431 = (uint16_t)(43); + _curvea0[50] = _13431; + uint16_t _13432 = (uint16_t)(44); + _curvea0[51] = _13432; + uint16_t _13433 = (uint16_t)(44); + _curvea0[52] = _13433; + uint16_t _13434 = (uint16_t)(45); + _curvea0[53] = _13434; + uint16_t _13435 = (uint16_t)(45); + _curvea0[54] = _13435; + uint16_t _13436 = (uint16_t)(46); + _curvea0[55] = _13436; + uint16_t _13437 = (uint16_t)(46); + _curvea0[56] = _13437; + uint16_t _13438 = (uint16_t)(47); + _curvea0[57] = _13438; + uint16_t _13439 = (uint16_t)(47); + _curvea0[58] = _13439; + uint16_t _13440 = (uint16_t)(48); + _curvea0[59] = _13440; + uint16_t _13441 = (uint16_t)(48); + _curvea0[60] = _13441; + uint16_t _13442 = (uint16_t)(49); + _curvea0[61] = _13442; + uint16_t _13443 = (uint16_t)(49); + _curvea0[62] = _13443; + uint16_t _13444 = (uint16_t)(50); + _curvea0[63] = _13444; + uint16_t _13445 = (uint16_t)(50); + _curvea0[64] = _13445; + uint16_t _13446 = (uint16_t)(51); + _curvea0[65] = _13446; + uint16_t _13447 = (uint16_t)(51); + _curvea0[66] = _13447; + uint16_t _13448 = (uint16_t)(52); + _curvea0[67] = _13448; + uint16_t _13449 = (uint16_t)(52); + _curvea0[68] = _13449; + uint16_t _13450 = (uint16_t)(53); + _curvea0[69] = _13450; + uint16_t _13451 = (uint16_t)(53); + _curvea0[70] = _13451; + uint16_t _13452 = (uint16_t)(54); + _curvea0[71] = _13452; + uint16_t _13453 = (uint16_t)(54); + _curvea0[72] = _13453; + uint16_t _13454 = (uint16_t)(55); + _curvea0[73] = _13454; + uint16_t _13455 = (uint16_t)(55); + _curvea0[74] = _13455; + uint16_t _13456 = (uint16_t)(56); + _curvea0[75] = _13456; + uint16_t _13457 = (uint16_t)(56); + _curvea0[76] = _13457; + uint16_t _13458 = (uint16_t)(57); + _curvea0[77] = _13458; + uint16_t _13459 = (uint16_t)(57); + _curvea0[78] = _13459; + uint16_t _13460 = (uint16_t)(58); + _curvea0[79] = _13460; + uint16_t _13461 = (uint16_t)(58); + _curvea0[80] = _13461; + uint16_t _13462 = (uint16_t)(58); + _curvea0[81] = _13462; + uint16_t _13463 = (uint16_t)(59); + _curvea0[82] = _13463; + uint16_t _13464 = (uint16_t)(59); + _curvea0[83] = _13464; + uint16_t _13465 = (uint16_t)(60); + _curvea0[84] = _13465; + uint16_t _13466 = (uint16_t)(60); + _curvea0[85] = _13466; + uint16_t _13467 = (uint16_t)(61); + _curvea0[86] = _13467; + uint16_t _13468 = (uint16_t)(61); + _curvea0[87] = _13468; + uint16_t _13469 = (uint16_t)(62); + _curvea0[88] = _13469; + uint16_t _13470 = (uint16_t)(62); + _curvea0[89] = _13470; + uint16_t _13471 = (uint16_t)(63); + _curvea0[90] = _13471; + uint16_t _13472 = (uint16_t)(63); + _curvea0[91] = _13472; + uint16_t _13473 = (uint16_t)(64); + _curvea0[92] = _13473; + uint16_t _13474 = (uint16_t)(64); + _curvea0[93] = _13474; + uint16_t _13475 = (uint16_t)(64); + _curvea0[94] = _13475; + uint16_t _13476 = (uint16_t)(65); + _curvea0[95] = _13476; + uint16_t _13477 = (uint16_t)(65); + _curvea0[96] = _13477; + uint16_t _13478 = (uint16_t)(66); + _curvea0[97] = _13478; + uint16_t _13479 = (uint16_t)(66); + _curvea0[98] = _13479; + uint16_t _13480 = (uint16_t)(67); + _curvea0[99] = _13480; + uint16_t _13481 = (uint16_t)(67); + _curvea0[100] = _13481; + uint16_t _13482 = (uint16_t)(68); + _curvea0[101] = _13482; + uint16_t _13483 = (uint16_t)(68); + _curvea0[102] = _13483; + uint16_t _13484 = (uint16_t)(68); + _curvea0[103] = _13484; + uint16_t _13485 = (uint16_t)(69); + _curvea0[104] = _13485; + uint16_t _13486 = (uint16_t)(69); + _curvea0[105] = _13486; + uint16_t _13487 = (uint16_t)(70); + _curvea0[106] = _13487; + uint16_t _13488 = (uint16_t)(70); + _curvea0[107] = _13488; + uint16_t _13489 = (uint16_t)(71); + _curvea0[108] = _13489; + uint16_t _13490 = (uint16_t)(71); + _curvea0[109] = _13490; + uint16_t _13491 = (uint16_t)(71); + _curvea0[110] = _13491; + uint16_t _13492 = (uint16_t)(72); + _curvea0[111] = _13492; + uint16_t _13493 = (uint16_t)(72); + _curvea0[112] = _13493; + uint16_t _13494 = (uint16_t)(73); + _curvea0[113] = _13494; + uint16_t _13495 = (uint16_t)(73); + _curvea0[114] = _13495; + uint16_t _13496 = (uint16_t)(74); + _curvea0[115] = _13496; + uint16_t _13497 = (uint16_t)(74); + _curvea0[116] = _13497; + uint16_t _13498 = (uint16_t)(74); + _curvea0[117] = _13498; + uint16_t _13499 = (uint16_t)(75); + _curvea0[118] = _13499; + uint16_t _13500 = (uint16_t)(75); + _curvea0[119] = _13500; + uint16_t _13501 = (uint16_t)(76); + _curvea0[120] = _13501; + uint16_t _13502 = (uint16_t)(76); + _curvea0[121] = _13502; + uint16_t _13503 = (uint16_t)(77); + _curvea0[122] = _13503; + uint16_t _13504 = (uint16_t)(77); + _curvea0[123] = _13504; + uint16_t _13505 = (uint16_t)(77); + _curvea0[124] = _13505; + uint16_t _13506 = (uint16_t)(78); + _curvea0[125] = _13506; + uint16_t _13507 = (uint16_t)(78); + _curvea0[126] = _13507; + uint16_t _13508 = (uint16_t)(79); + _curvea0[127] = _13508; + uint16_t _13509 = (uint16_t)(79); + _curvea0[128] = _13509; + uint16_t _13510 = (uint16_t)(79); + _curvea0[129] = _13510; + uint16_t _13511 = (uint16_t)(80); + _curvea0[130] = _13511; + uint16_t _13512 = (uint16_t)(80); + _curvea0[131] = _13512; + uint16_t _13513 = (uint16_t)(81); + _curvea0[132] = _13513; + uint16_t _13514 = (uint16_t)(81); + _curvea0[133] = _13514; + uint16_t _13515 = (uint16_t)(82); + _curvea0[134] = _13515; + uint16_t _13516 = (uint16_t)(82); + _curvea0[135] = _13516; + uint16_t _13517 = (uint16_t)(82); + _curvea0[136] = _13517; + uint16_t _13518 = (uint16_t)(83); + _curvea0[137] = _13518; + uint16_t _13519 = (uint16_t)(83); + _curvea0[138] = _13519; + uint16_t _13520 = (uint16_t)(84); + _curvea0[139] = _13520; + uint16_t _13521 = (uint16_t)(84); + _curvea0[140] = _13521; + uint16_t _13522 = (uint16_t)(84); + _curvea0[141] = _13522; + uint16_t _13523 = (uint16_t)(85); + _curvea0[142] = _13523; + uint16_t _13524 = (uint16_t)(85); + _curvea0[143] = _13524; + uint16_t _13525 = (uint16_t)(86); + _curvea0[144] = _13525; + uint16_t _13526 = (uint16_t)(86); + _curvea0[145] = _13526; + uint16_t _13527 = (uint16_t)(86); + _curvea0[146] = _13527; + uint16_t _13528 = (uint16_t)(87); + _curvea0[147] = _13528; + uint16_t _13529 = (uint16_t)(87); + _curvea0[148] = _13529; + uint16_t _13530 = (uint16_t)(88); + _curvea0[149] = _13530; + uint16_t _13531 = (uint16_t)(88); + _curvea0[150] = _13531; + uint16_t _13532 = (uint16_t)(88); + _curvea0[151] = _13532; + uint16_t _13533 = (uint16_t)(89); + _curvea0[152] = _13533; + uint16_t _13534 = (uint16_t)(89); + _curvea0[153] = _13534; + uint16_t _13535 = (uint16_t)(90); + _curvea0[154] = _13535; + uint16_t _13536 = (uint16_t)(90); + _curvea0[155] = _13536; + uint16_t _13537 = (uint16_t)(90); + _curvea0[156] = _13537; + uint16_t _13538 = (uint16_t)(91); + _curvea0[157] = _13538; + uint16_t _13539 = (uint16_t)(91); + _curvea0[158] = _13539; + uint16_t _13540 = (uint16_t)(92); + _curvea0[159] = _13540; + uint16_t _13541 = (uint16_t)(92); + _curvea0[160] = _13541; + uint16_t _13542 = (uint16_t)(92); + _curvea0[161] = _13542; + uint16_t _13543 = (uint16_t)(93); + _curvea0[162] = _13543; + uint16_t _13544 = (uint16_t)(93); + _curvea0[163] = _13544; + uint16_t _13545 = (uint16_t)(93); + _curvea0[164] = _13545; + uint16_t _13546 = (uint16_t)(94); + _curvea0[165] = _13546; + uint16_t _13547 = (uint16_t)(94); + _curvea0[166] = _13547; + uint16_t _13548 = (uint16_t)(95); + _curvea0[167] = _13548; + uint16_t _13549 = (uint16_t)(95); + _curvea0[168] = _13549; + uint16_t _13550 = (uint16_t)(95); + _curvea0[169] = _13550; + uint16_t _13551 = (uint16_t)(96); + _curvea0[170] = _13551; + uint16_t _13552 = (uint16_t)(96); + _curvea0[171] = _13552; + uint16_t _13553 = (uint16_t)(97); + _curvea0[172] = _13553; + uint16_t _13554 = (uint16_t)(97); + _curvea0[173] = _13554; + uint16_t _13555 = (uint16_t)(97); + _curvea0[174] = _13555; + uint16_t _13556 = (uint16_t)(98); + _curvea0[175] = _13556; + uint16_t _13557 = (uint16_t)(98); + _curvea0[176] = _13557; + uint16_t _13558 = (uint16_t)(99); + _curvea0[177] = _13558; + uint16_t _13559 = (uint16_t)(99); + _curvea0[178] = _13559; + uint16_t _13560 = (uint16_t)(99); + _curvea0[179] = _13560; + uint16_t _13561 = (uint16_t)(100); + _curvea0[180] = _13561; + uint16_t _13562 = (uint16_t)(100); + _curvea0[181] = _13562; + uint16_t _13563 = (uint16_t)(100); + _curvea0[182] = _13563; + uint16_t _13564 = (uint16_t)(101); + _curvea0[183] = _13564; + uint16_t _13565 = (uint16_t)(101); + _curvea0[184] = _13565; + uint16_t _13566 = (uint16_t)(102); + _curvea0[185] = _13566; + uint16_t _13567 = (uint16_t)(102); + _curvea0[186] = _13567; + uint16_t _13568 = (uint16_t)(102); + _curvea0[187] = _13568; + uint16_t _13569 = (uint16_t)(103); + _curvea0[188] = _13569; + uint16_t _13570 = (uint16_t)(103); + _curvea0[189] = _13570; + uint16_t _13571 = (uint16_t)(103); + _curvea0[190] = _13571; + uint16_t _13572 = (uint16_t)(104); + _curvea0[191] = _13572; + uint16_t _13573 = (uint16_t)(104); + _curvea0[192] = _13573; + uint16_t _13574 = (uint16_t)(105); + _curvea0[193] = _13574; + uint16_t _13575 = (uint16_t)(105); + _curvea0[194] = _13575; + uint16_t _13576 = (uint16_t)(105); + _curvea0[195] = _13576; + uint16_t _13577 = (uint16_t)(106); + _curvea0[196] = _13577; + uint16_t _13578 = (uint16_t)(106); + _curvea0[197] = _13578; + uint16_t _13579 = (uint16_t)(106); + _curvea0[198] = _13579; + uint16_t _13580 = (uint16_t)(107); + _curvea0[199] = _13580; + uint16_t _13581 = (uint16_t)(107); + _curvea0[200] = _13581; + uint16_t _13582 = (uint16_t)(108); + _curvea0[201] = _13582; + uint16_t _13583 = (uint16_t)(108); + _curvea0[202] = _13583; + uint16_t _13584 = (uint16_t)(108); + _curvea0[203] = _13584; + uint16_t _13585 = (uint16_t)(109); + _curvea0[204] = _13585; + uint16_t _13586 = (uint16_t)(109); + _curvea0[205] = _13586; + uint16_t _13587 = (uint16_t)(109); + _curvea0[206] = _13587; + uint16_t _13588 = (uint16_t)(110); + _curvea0[207] = _13588; + uint16_t _13589 = (uint16_t)(110); + _curvea0[208] = _13589; + uint16_t _13590 = (uint16_t)(111); + _curvea0[209] = _13590; + uint16_t _13591 = (uint16_t)(111); + _curvea0[210] = _13591; + uint16_t _13592 = (uint16_t)(111); + _curvea0[211] = _13592; + uint16_t _13593 = (uint16_t)(112); + _curvea0[212] = _13593; + uint16_t _13594 = (uint16_t)(112); + _curvea0[213] = _13594; + uint16_t _13595 = (uint16_t)(112); + _curvea0[214] = _13595; + uint16_t _13596 = (uint16_t)(113); + _curvea0[215] = _13596; + uint16_t _13597 = (uint16_t)(113); + _curvea0[216] = _13597; + uint16_t _13598 = (uint16_t)(113); + _curvea0[217] = _13598; + uint16_t _13599 = (uint16_t)(114); + _curvea0[218] = _13599; + uint16_t _13600 = (uint16_t)(114); + _curvea0[219] = _13600; + uint16_t _13601 = (uint16_t)(115); + _curvea0[220] = _13601; + uint16_t _13602 = (uint16_t)(115); + _curvea0[221] = _13602; + uint16_t _13603 = (uint16_t)(115); + _curvea0[222] = _13603; + uint16_t _13604 = (uint16_t)(116); + _curvea0[223] = _13604; + uint16_t _13605 = (uint16_t)(116); + _curvea0[224] = _13605; + uint16_t _13606 = (uint16_t)(116); + _curvea0[225] = _13606; + uint16_t _13607 = (uint16_t)(117); + _curvea0[226] = _13607; + uint16_t _13608 = (uint16_t)(117); + _curvea0[227] = _13608; + uint16_t _13609 = (uint16_t)(117); + _curvea0[228] = _13609; + uint16_t _13610 = (uint16_t)(118); + _curvea0[229] = _13610; + uint16_t _13611 = (uint16_t)(118); + _curvea0[230] = _13611; + uint16_t _13612 = (uint16_t)(119); + _curvea0[231] = _13612; + uint16_t _13613 = (uint16_t)(119); + _curvea0[232] = _13613; + uint16_t _13614 = (uint16_t)(119); + _curvea0[233] = _13614; + uint16_t _13615 = (uint16_t)(120); + _curvea0[234] = _13615; + uint16_t _13616 = (uint16_t)(120); + _curvea0[235] = _13616; + uint16_t _13617 = (uint16_t)(120); + _curvea0[236] = _13617; + uint16_t _13618 = (uint16_t)(121); + _curvea0[237] = _13618; + uint16_t _13619 = (uint16_t)(121); + _curvea0[238] = _13619; + uint16_t _13620 = (uint16_t)(121); + _curvea0[239] = _13620; + uint16_t _13621 = (uint16_t)(122); + _curvea0[240] = _13621; + uint16_t _13622 = (uint16_t)(122); + _curvea0[241] = _13622; + uint16_t _13623 = (uint16_t)(123); + _curvea0[242] = _13623; + uint16_t _13624 = (uint16_t)(123); + _curvea0[243] = _13624; + uint16_t _13625 = (uint16_t)(123); + _curvea0[244] = _13625; + uint16_t _13626 = (uint16_t)(124); + _curvea0[245] = _13626; + uint16_t _13627 = (uint16_t)(124); + _curvea0[246] = _13627; + uint16_t _13628 = (uint16_t)(124); + _curvea0[247] = _13628; + uint16_t _13629 = (uint16_t)(125); + _curvea0[248] = _13629; + uint16_t _13630 = (uint16_t)(125); + _curvea0[249] = _13630; + uint16_t _13631 = (uint16_t)(125); + _curvea0[250] = _13631; + uint16_t _13632 = (uint16_t)(126); + _curvea0[251] = _13632; + uint16_t _13633 = (uint16_t)(126); + _curvea0[252] = _13633; + uint16_t _13634 = (uint16_t)(126); + _curvea0[253] = _13634; + uint16_t _13635 = (uint16_t)(127); + _curvea0[254] = _13635; + uint16_t _13636 = (uint16_t)(127); + _curvea0[255] = _13636; + uint16_t _13637 = (uint16_t)(128); + _curvea0[256] = _13637; + uint16_t _13638 = (uint16_t)(128); + _curvea0[257] = _13638; + uint16_t _13639 = (uint16_t)(128); + _curvea0[258] = _13639; + uint16_t _13640 = (uint16_t)(129); + _curvea0[259] = _13640; + uint16_t _13641 = (uint16_t)(129); + _curvea0[260] = _13641; + uint16_t _13642 = (uint16_t)(129); + _curvea0[261] = _13642; + uint16_t _13643 = (uint16_t)(130); + _curvea0[262] = _13643; + uint16_t _13644 = (uint16_t)(130); + _curvea0[263] = _13644; + uint16_t _13645 = (uint16_t)(130); + _curvea0[264] = _13645; + uint16_t _13646 = (uint16_t)(131); + _curvea0[265] = _13646; + uint16_t _13647 = (uint16_t)(131); + _curvea0[266] = _13647; + uint16_t _13648 = (uint16_t)(131); + _curvea0[267] = _13648; + uint16_t _13649 = (uint16_t)(132); + _curvea0[268] = _13649; + uint16_t _13650 = (uint16_t)(132); + _curvea0[269] = _13650; + uint16_t _13651 = (uint16_t)(132); + _curvea0[270] = _13651; + uint16_t _13652 = (uint16_t)(133); + _curvea0[271] = _13652; + uint16_t _13653 = (uint16_t)(133); + _curvea0[272] = _13653; + uint16_t _13654 = (uint16_t)(133); + _curvea0[273] = _13654; + uint16_t _13655 = (uint16_t)(134); + _curvea0[274] = _13655; + uint16_t _13656 = (uint16_t)(134); + _curvea0[275] = _13656; + uint16_t _13657 = (uint16_t)(134); + _curvea0[276] = _13657; + uint16_t _13658 = (uint16_t)(135); + _curvea0[277] = _13658; + uint16_t _13659 = (uint16_t)(135); + _curvea0[278] = _13659; + uint16_t _13660 = (uint16_t)(135); + _curvea0[279] = _13660; + uint16_t _13661 = (uint16_t)(136); + _curvea0[280] = _13661; + uint16_t _13662 = (uint16_t)(136); + _curvea0[281] = _13662; + uint16_t _13663 = (uint16_t)(136); + _curvea0[282] = _13663; + uint16_t _13664 = (uint16_t)(137); + _curvea0[283] = _13664; + uint16_t _13665 = (uint16_t)(137); + _curvea0[284] = _13665; + uint16_t _13666 = (uint16_t)(137); + _curvea0[285] = _13666; + uint16_t _13667 = (uint16_t)(138); + _curvea0[286] = _13667; + uint16_t _13668 = (uint16_t)(138); + _curvea0[287] = _13668; + uint16_t _13669 = (uint16_t)(138); + _curvea0[288] = _13669; + uint16_t _13670 = (uint16_t)(139); + _curvea0[289] = _13670; + uint16_t _13671 = (uint16_t)(139); + _curvea0[290] = _13671; + uint16_t _13672 = (uint16_t)(139); + _curvea0[291] = _13672; + uint16_t _13673 = (uint16_t)(140); + _curvea0[292] = _13673; + uint16_t _13674 = (uint16_t)(140); + _curvea0[293] = _13674; + uint16_t _13675 = (uint16_t)(140); + _curvea0[294] = _13675; + uint16_t _13676 = (uint16_t)(141); + _curvea0[295] = _13676; + uint16_t _13677 = (uint16_t)(141); + _curvea0[296] = _13677; + uint16_t _13678 = (uint16_t)(141); + _curvea0[297] = _13678; + uint16_t _13679 = (uint16_t)(141); + _curvea0[298] = _13679; + uint16_t _13680 = (uint16_t)(142); + _curvea0[299] = _13680; + uint16_t _13681 = (uint16_t)(142); + _curvea0[300] = _13681; + uint16_t _13682 = (uint16_t)(142); + _curvea0[301] = _13682; + uint16_t _13683 = (uint16_t)(143); + _curvea0[302] = _13683; + uint16_t _13684 = (uint16_t)(143); + _curvea0[303] = _13684; + uint16_t _13685 = (uint16_t)(143); + _curvea0[304] = _13685; + uint16_t _13686 = (uint16_t)(144); + _curvea0[305] = _13686; + uint16_t _13687 = (uint16_t)(144); + _curvea0[306] = _13687; + uint16_t _13688 = (uint16_t)(144); + _curvea0[307] = _13688; + uint16_t _13689 = (uint16_t)(145); + _curvea0[308] = _13689; + uint16_t _13690 = (uint16_t)(145); + _curvea0[309] = _13690; + uint16_t _13691 = (uint16_t)(145); + _curvea0[310] = _13691; + uint16_t _13692 = (uint16_t)(145); + _curvea0[311] = _13692; + uint16_t _13693 = (uint16_t)(146); + _curvea0[312] = _13693; + uint16_t _13694 = (uint16_t)(146); + _curvea0[313] = _13694; + uint16_t _13695 = (uint16_t)(146); + _curvea0[314] = _13695; + uint16_t _13696 = (uint16_t)(147); + _curvea0[315] = _13696; + uint16_t _13697 = (uint16_t)(147); + _curvea0[316] = _13697; + uint16_t _13698 = (uint16_t)(147); + _curvea0[317] = _13698; + uint16_t _13699 = (uint16_t)(148); + _curvea0[318] = _13699; + uint16_t _13700 = (uint16_t)(148); + _curvea0[319] = _13700; + uint16_t _13701 = (uint16_t)(148); + _curvea0[320] = _13701; + uint16_t _13702 = (uint16_t)(148); + _curvea0[321] = _13702; + uint16_t _13703 = (uint16_t)(149); + _curvea0[322] = _13703; + uint16_t _13704 = (uint16_t)(149); + _curvea0[323] = _13704; + uint16_t _13705 = (uint16_t)(149); + _curvea0[324] = _13705; + uint16_t _13706 = (uint16_t)(150); + _curvea0[325] = _13706; + uint16_t _13707 = (uint16_t)(150); + _curvea0[326] = _13707; + uint16_t _13708 = (uint16_t)(150); + _curvea0[327] = _13708; + uint16_t _13709 = (uint16_t)(150); + _curvea0[328] = _13709; + uint16_t _13710 = (uint16_t)(151); + _curvea0[329] = _13710; + uint16_t _13711 = (uint16_t)(151); + _curvea0[330] = _13711; + uint16_t _13712 = (uint16_t)(151); + _curvea0[331] = _13712; + uint16_t _13713 = (uint16_t)(152); + _curvea0[332] = _13713; + uint16_t _13714 = (uint16_t)(152); + _curvea0[333] = _13714; + uint16_t _13715 = (uint16_t)(152); + _curvea0[334] = _13715; + uint16_t _13716 = (uint16_t)(152); + _curvea0[335] = _13716; + uint16_t _13717 = (uint16_t)(153); + _curvea0[336] = _13717; + uint16_t _13718 = (uint16_t)(153); + _curvea0[337] = _13718; + uint16_t _13719 = (uint16_t)(153); + _curvea0[338] = _13719; + uint16_t _13720 = (uint16_t)(154); + _curvea0[339] = _13720; + uint16_t _13721 = (uint16_t)(154); + _curvea0[340] = _13721; + uint16_t _13722 = (uint16_t)(154); + _curvea0[341] = _13722; + uint16_t _13723 = (uint16_t)(154); + _curvea0[342] = _13723; + uint16_t _13724 = (uint16_t)(155); + _curvea0[343] = _13724; + uint16_t _13725 = (uint16_t)(155); + _curvea0[344] = _13725; + uint16_t _13726 = (uint16_t)(155); + _curvea0[345] = _13726; + uint16_t _13727 = (uint16_t)(156); + _curvea0[346] = _13727; + uint16_t _13728 = (uint16_t)(156); + _curvea0[347] = _13728; + uint16_t _13729 = (uint16_t)(156); + _curvea0[348] = _13729; + uint16_t _13730 = (uint16_t)(156); + _curvea0[349] = _13730; + uint16_t _13731 = (uint16_t)(157); + _curvea0[350] = _13731; + uint16_t _13732 = (uint16_t)(157); + _curvea0[351] = _13732; + uint16_t _13733 = (uint16_t)(157); + _curvea0[352] = _13733; + uint16_t _13734 = (uint16_t)(157); + _curvea0[353] = _13734; + uint16_t _13735 = (uint16_t)(158); + _curvea0[354] = _13735; + uint16_t _13736 = (uint16_t)(158); + _curvea0[355] = _13736; + uint16_t _13737 = (uint16_t)(158); + _curvea0[356] = _13737; + uint16_t _13738 = (uint16_t)(159); + _curvea0[357] = _13738; + uint16_t _13739 = (uint16_t)(159); + _curvea0[358] = _13739; + uint16_t _13740 = (uint16_t)(159); + _curvea0[359] = _13740; + uint16_t _13741 = (uint16_t)(159); + _curvea0[360] = _13741; + uint16_t _13742 = (uint16_t)(160); + _curvea0[361] = _13742; + uint16_t _13743 = (uint16_t)(160); + _curvea0[362] = _13743; + uint16_t _13744 = (uint16_t)(160); + _curvea0[363] = _13744; + uint16_t _13745 = (uint16_t)(160); + _curvea0[364] = _13745; + uint16_t _13746 = (uint16_t)(161); + _curvea0[365] = _13746; + uint16_t _13747 = (uint16_t)(161); + _curvea0[366] = _13747; + uint16_t _13748 = (uint16_t)(161); + _curvea0[367] = _13748; + uint16_t _13749 = (uint16_t)(161); + _curvea0[368] = _13749; + uint16_t _13750 = (uint16_t)(162); + _curvea0[369] = _13750; + uint16_t _13751 = (uint16_t)(162); + _curvea0[370] = _13751; + uint16_t _13752 = (uint16_t)(162); + _curvea0[371] = _13752; + uint16_t _13753 = (uint16_t)(162); + _curvea0[372] = _13753; + uint16_t _13754 = (uint16_t)(163); + _curvea0[373] = _13754; + uint16_t _13755 = (uint16_t)(163); + _curvea0[374] = _13755; + uint16_t _13756 = (uint16_t)(163); + _curvea0[375] = _13756; + uint16_t _13757 = (uint16_t)(163); + _curvea0[376] = _13757; + uint16_t _13758 = (uint16_t)(164); + _curvea0[377] = _13758; + uint16_t _13759 = (uint16_t)(164); + _curvea0[378] = _13759; + uint16_t _13760 = (uint16_t)(164); + _curvea0[379] = _13760; + uint16_t _13761 = (uint16_t)(164); + _curvea0[380] = _13761; + uint16_t _13762 = (uint16_t)(165); + _curvea0[381] = _13762; + uint16_t _13763 = (uint16_t)(165); + _curvea0[382] = _13763; + uint16_t _13764 = (uint16_t)(165); + _curvea0[383] = _13764; + uint16_t _13765 = (uint16_t)(166); + _curvea0[384] = _13765; + uint16_t _13766 = (uint16_t)(166); + _curvea0[385] = _13766; + uint16_t _13767 = (uint16_t)(166); + _curvea0[386] = _13767; + uint16_t _13768 = (uint16_t)(166); + _curvea0[387] = _13768; + uint16_t _13769 = (uint16_t)(167); + _curvea0[388] = _13769; + uint16_t _13770 = (uint16_t)(167); + _curvea0[389] = _13770; + uint16_t _13771 = (uint16_t)(167); + _curvea0[390] = _13771; + uint16_t _13772 = (uint16_t)(167); + _curvea0[391] = _13772; + uint16_t _13773 = (uint16_t)(167); + _curvea0[392] = _13773; + uint16_t _13774 = (uint16_t)(168); + _curvea0[393] = _13774; + uint16_t _13775 = (uint16_t)(168); + _curvea0[394] = _13775; + uint16_t _13776 = (uint16_t)(168); + _curvea0[395] = _13776; + uint16_t _13777 = (uint16_t)(168); + _curvea0[396] = _13777; + uint16_t _13778 = (uint16_t)(169); + _curvea0[397] = _13778; + uint16_t _13779 = (uint16_t)(169); + _curvea0[398] = _13779; + uint16_t _13780 = (uint16_t)(169); + _curvea0[399] = _13780; + uint16_t _13781 = (uint16_t)(169); + _curvea0[400] = _13781; + uint16_t _13782 = (uint16_t)(170); + _curvea0[401] = _13782; + uint16_t _13783 = (uint16_t)(170); + _curvea0[402] = _13783; + uint16_t _13784 = (uint16_t)(170); + _curvea0[403] = _13784; + uint16_t _13785 = (uint16_t)(170); + _curvea0[404] = _13785; + uint16_t _13786 = (uint16_t)(171); + _curvea0[405] = _13786; + uint16_t _13787 = (uint16_t)(171); + _curvea0[406] = _13787; + uint16_t _13788 = (uint16_t)(171); + _curvea0[407] = _13788; + uint16_t _13789 = (uint16_t)(171); + _curvea0[408] = _13789; + uint16_t _13790 = (uint16_t)(172); + _curvea0[409] = _13790; + uint16_t _13791 = (uint16_t)(172); + _curvea0[410] = _13791; + uint16_t _13792 = (uint16_t)(172); + _curvea0[411] = _13792; + uint16_t _13793 = (uint16_t)(172); + _curvea0[412] = _13793; + uint16_t _13794 = (uint16_t)(173); + _curvea0[413] = _13794; + uint16_t _13795 = (uint16_t)(173); + _curvea0[414] = _13795; + uint16_t _13796 = (uint16_t)(173); + _curvea0[415] = _13796; + uint16_t _13797 = (uint16_t)(173); + _curvea0[416] = _13797; + uint16_t _13798 = (uint16_t)(173); + _curvea0[417] = _13798; + uint16_t _13799 = (uint16_t)(174); + _curvea0[418] = _13799; + uint16_t _13800 = (uint16_t)(174); + _curvea0[419] = _13800; + uint16_t _13801 = (uint16_t)(174); + _curvea0[420] = _13801; + uint16_t _13802 = (uint16_t)(174); + _curvea0[421] = _13802; + uint16_t _13803 = (uint16_t)(175); + _curvea0[422] = _13803; + uint16_t _13804 = (uint16_t)(175); + _curvea0[423] = _13804; + uint16_t _13805 = (uint16_t)(175); + _curvea0[424] = _13805; + uint16_t _13806 = (uint16_t)(175); + _curvea0[425] = _13806; + uint16_t _13807 = (uint16_t)(176); + _curvea0[426] = _13807; + uint16_t _13808 = (uint16_t)(176); + _curvea0[427] = _13808; + uint16_t _13809 = (uint16_t)(176); + _curvea0[428] = _13809; + uint16_t _13810 = (uint16_t)(176); + _curvea0[429] = _13810; + uint16_t _13811 = (uint16_t)(176); + _curvea0[430] = _13811; + uint16_t _13812 = (uint16_t)(177); + _curvea0[431] = _13812; + uint16_t _13813 = (uint16_t)(177); + _curvea0[432] = _13813; + uint16_t _13814 = (uint16_t)(177); + _curvea0[433] = _13814; + uint16_t _13815 = (uint16_t)(177); + _curvea0[434] = _13815; + uint16_t _13816 = (uint16_t)(178); + _curvea0[435] = _13816; + uint16_t _13817 = (uint16_t)(178); + _curvea0[436] = _13817; + uint16_t _13818 = (uint16_t)(178); + _curvea0[437] = _13818; + uint16_t _13819 = (uint16_t)(178); + _curvea0[438] = _13819; + uint16_t _13820 = (uint16_t)(178); + _curvea0[439] = _13820; + uint16_t _13821 = (uint16_t)(179); + _curvea0[440] = _13821; + uint16_t _13822 = (uint16_t)(179); + _curvea0[441] = _13822; + uint16_t _13823 = (uint16_t)(179); + _curvea0[442] = _13823; + uint16_t _13824 = (uint16_t)(179); + _curvea0[443] = _13824; + uint16_t _13825 = (uint16_t)(180); + _curvea0[444] = _13825; + uint16_t _13826 = (uint16_t)(180); + _curvea0[445] = _13826; + uint16_t _13827 = (uint16_t)(180); + _curvea0[446] = _13827; + uint16_t _13828 = (uint16_t)(180); + _curvea0[447] = _13828; + uint16_t _13829 = (uint16_t)(180); + _curvea0[448] = _13829; + uint16_t _13830 = (uint16_t)(181); + _curvea0[449] = _13830; + uint16_t _13831 = (uint16_t)(181); + _curvea0[450] = _13831; + uint16_t _13832 = (uint16_t)(181); + _curvea0[451] = _13832; + uint16_t _13833 = (uint16_t)(181); + _curvea0[452] = _13833; + uint16_t _13834 = (uint16_t)(181); + _curvea0[453] = _13834; + uint16_t _13835 = (uint16_t)(182); + _curvea0[454] = _13835; + uint16_t _13836 = (uint16_t)(182); + _curvea0[455] = _13836; + uint16_t _13837 = (uint16_t)(182); + _curvea0[456] = _13837; + uint16_t _13838 = (uint16_t)(182); + _curvea0[457] = _13838; + uint16_t _13839 = (uint16_t)(183); + _curvea0[458] = _13839; + uint16_t _13840 = (uint16_t)(183); + _curvea0[459] = _13840; + uint16_t _13841 = (uint16_t)(183); + _curvea0[460] = _13841; + uint16_t _13842 = (uint16_t)(183); + _curvea0[461] = _13842; + uint16_t _13843 = (uint16_t)(183); + _curvea0[462] = _13843; + uint16_t _13844 = (uint16_t)(184); + _curvea0[463] = _13844; + uint16_t _13845 = (uint16_t)(184); + _curvea0[464] = _13845; + uint16_t _13846 = (uint16_t)(184); + _curvea0[465] = _13846; + uint16_t _13847 = (uint16_t)(184); + _curvea0[466] = _13847; + uint16_t _13848 = (uint16_t)(184); + _curvea0[467] = _13848; + uint16_t _13849 = (uint16_t)(185); + _curvea0[468] = _13849; + uint16_t _13850 = (uint16_t)(185); + _curvea0[469] = _13850; + uint16_t _13851 = (uint16_t)(185); + _curvea0[470] = _13851; + uint16_t _13852 = (uint16_t)(185); + _curvea0[471] = _13852; + uint16_t _13853 = (uint16_t)(185); + _curvea0[472] = _13853; + uint16_t _13854 = (uint16_t)(186); + _curvea0[473] = _13854; + uint16_t _13855 = (uint16_t)(186); + _curvea0[474] = _13855; + uint16_t _13856 = (uint16_t)(186); + _curvea0[475] = _13856; + uint16_t _13857 = (uint16_t)(186); + _curvea0[476] = _13857; + uint16_t _13858 = (uint16_t)(187); + _curvea0[477] = _13858; + uint16_t _13859 = (uint16_t)(187); + _curvea0[478] = _13859; + uint16_t _13860 = (uint16_t)(187); + _curvea0[479] = _13860; + uint16_t _13861 = (uint16_t)(187); + _curvea0[480] = _13861; + uint16_t _13862 = (uint16_t)(187); + _curvea0[481] = _13862; + uint16_t _13863 = (uint16_t)(188); + _curvea0[482] = _13863; + uint16_t _13864 = (uint16_t)(188); + _curvea0[483] = _13864; + uint16_t _13865 = (uint16_t)(188); + _curvea0[484] = _13865; + uint16_t _13866 = (uint16_t)(188); + _curvea0[485] = _13866; + uint16_t _13867 = (uint16_t)(188); + _curvea0[486] = _13867; + uint16_t _13868 = (uint16_t)(189); + _curvea0[487] = _13868; + uint16_t _13869 = (uint16_t)(189); + _curvea0[488] = _13869; + uint16_t _13870 = (uint16_t)(189); + _curvea0[489] = _13870; + uint16_t _13871 = (uint16_t)(189); + _curvea0[490] = _13871; + uint16_t _13872 = (uint16_t)(189); + _curvea0[491] = _13872; + uint16_t _13873 = (uint16_t)(190); + _curvea0[492] = _13873; + uint16_t _13874 = (uint16_t)(190); + _curvea0[493] = _13874; + uint16_t _13875 = (uint16_t)(190); + _curvea0[494] = _13875; + uint16_t _13876 = (uint16_t)(190); + _curvea0[495] = _13876; + uint16_t _13877 = (uint16_t)(190); + _curvea0[496] = _13877; + uint16_t _13878 = (uint16_t)(190); + _curvea0[497] = _13878; + uint16_t _13879 = (uint16_t)(191); + _curvea0[498] = _13879; + uint16_t _13880 = (uint16_t)(191); + _curvea0[499] = _13880; + uint16_t _13881 = (uint16_t)(191); + _curvea0[500] = _13881; + uint16_t _13882 = (uint16_t)(191); + _curvea0[501] = _13882; + uint16_t _13883 = (uint16_t)(191); + _curvea0[502] = _13883; + uint16_t _13884 = (uint16_t)(192); + _curvea0[503] = _13884; + uint16_t _13885 = (uint16_t)(192); + _curvea0[504] = _13885; + uint16_t _13886 = (uint16_t)(192); + _curvea0[505] = _13886; + uint16_t _13887 = (uint16_t)(192); + _curvea0[506] = _13887; + uint16_t _13888 = (uint16_t)(192); + _curvea0[507] = _13888; + uint16_t _13889 = (uint16_t)(193); + _curvea0[508] = _13889; + uint16_t _13890 = (uint16_t)(193); + _curvea0[509] = _13890; + uint16_t _13891 = (uint16_t)(193); + _curvea0[510] = _13891; + uint16_t _13892 = (uint16_t)(193); + _curvea0[511] = _13892; + uint16_t _13893 = (uint16_t)(193); + _curvea0[512] = _13893; + uint16_t _13894 = (uint16_t)(194); + _curvea0[513] = _13894; + uint16_t _13895 = (uint16_t)(194); + _curvea0[514] = _13895; + uint16_t _13896 = (uint16_t)(194); + _curvea0[515] = _13896; + uint16_t _13897 = (uint16_t)(194); + _curvea0[516] = _13897; + uint16_t _13898 = (uint16_t)(194); + _curvea0[517] = _13898; + uint16_t _13899 = (uint16_t)(195); + _curvea0[518] = _13899; + uint16_t _13900 = (uint16_t)(195); + _curvea0[519] = _13900; + uint16_t _13901 = (uint16_t)(195); + _curvea0[520] = _13901; + uint16_t _13902 = (uint16_t)(195); + _curvea0[521] = _13902; + uint16_t _13903 = (uint16_t)(195); + _curvea0[522] = _13903; + uint16_t _13904 = (uint16_t)(195); + _curvea0[523] = _13904; + uint16_t _13905 = (uint16_t)(196); + _curvea0[524] = _13905; + uint16_t _13906 = (uint16_t)(196); + _curvea0[525] = _13906; + uint16_t _13907 = (uint16_t)(196); + _curvea0[526] = _13907; + uint16_t _13908 = (uint16_t)(196); + _curvea0[527] = _13908; + uint16_t _13909 = (uint16_t)(196); + _curvea0[528] = _13909; + uint16_t _13910 = (uint16_t)(197); + _curvea0[529] = _13910; + uint16_t _13911 = (uint16_t)(197); + _curvea0[530] = _13911; + uint16_t _13912 = (uint16_t)(197); + _curvea0[531] = _13912; + uint16_t _13913 = (uint16_t)(197); + _curvea0[532] = _13913; + uint16_t _13914 = (uint16_t)(197); + _curvea0[533] = _13914; + uint16_t _13915 = (uint16_t)(197); + _curvea0[534] = _13915; + uint16_t _13916 = (uint16_t)(198); + _curvea0[535] = _13916; + uint16_t _13917 = (uint16_t)(198); + _curvea0[536] = _13917; + uint16_t _13918 = (uint16_t)(198); + _curvea0[537] = _13918; + uint16_t _13919 = (uint16_t)(198); + _curvea0[538] = _13919; + uint16_t _13920 = (uint16_t)(198); + _curvea0[539] = _13920; + uint16_t _13921 = (uint16_t)(199); + _curvea0[540] = _13921; + uint16_t _13922 = (uint16_t)(199); + _curvea0[541] = _13922; + uint16_t _13923 = (uint16_t)(199); + _curvea0[542] = _13923; + uint16_t _13924 = (uint16_t)(199); + _curvea0[543] = _13924; + uint16_t _13925 = (uint16_t)(199); + _curvea0[544] = _13925; + uint16_t _13926 = (uint16_t)(199); + _curvea0[545] = _13926; + uint16_t _13927 = (uint16_t)(200); + _curvea0[546] = _13927; + uint16_t _13928 = (uint16_t)(200); + _curvea0[547] = _13928; + uint16_t _13929 = (uint16_t)(200); + _curvea0[548] = _13929; + uint16_t _13930 = (uint16_t)(200); + _curvea0[549] = _13930; + uint16_t _13931 = (uint16_t)(200); + _curvea0[550] = _13931; + uint16_t _13932 = (uint16_t)(200); + _curvea0[551] = _13932; + uint16_t _13933 = (uint16_t)(201); + _curvea0[552] = _13933; + uint16_t _13934 = (uint16_t)(201); + _curvea0[553] = _13934; + uint16_t _13935 = (uint16_t)(201); + _curvea0[554] = _13935; + uint16_t _13936 = (uint16_t)(201); + _curvea0[555] = _13936; + uint16_t _13937 = (uint16_t)(201); + _curvea0[556] = _13937; + uint16_t _13938 = (uint16_t)(202); + _curvea0[557] = _13938; + uint16_t _13939 = (uint16_t)(202); + _curvea0[558] = _13939; + uint16_t _13940 = (uint16_t)(202); + _curvea0[559] = _13940; + uint16_t _13941 = (uint16_t)(202); + _curvea0[560] = _13941; + uint16_t _13942 = (uint16_t)(202); + _curvea0[561] = _13942; + uint16_t _13943 = (uint16_t)(202); + _curvea0[562] = _13943; + uint16_t _13944 = (uint16_t)(203); + _curvea0[563] = _13944; + uint16_t _13945 = (uint16_t)(203); + _curvea0[564] = _13945; + uint16_t _13946 = (uint16_t)(203); + _curvea0[565] = _13946; + uint16_t _13947 = (uint16_t)(203); + _curvea0[566] = _13947; + uint16_t _13948 = (uint16_t)(203); + _curvea0[567] = _13948; + uint16_t _13949 = (uint16_t)(203); + _curvea0[568] = _13949; + uint16_t _13950 = (uint16_t)(204); + _curvea0[569] = _13950; + uint16_t _13951 = (uint16_t)(204); + _curvea0[570] = _13951; + uint16_t _13952 = (uint16_t)(204); + _curvea0[571] = _13952; + uint16_t _13953 = (uint16_t)(204); + _curvea0[572] = _13953; + uint16_t _13954 = (uint16_t)(204); + _curvea0[573] = _13954; + uint16_t _13955 = (uint16_t)(204); + _curvea0[574] = _13955; + uint16_t _13956 = (uint16_t)(205); + _curvea0[575] = _13956; + uint16_t _13957 = (uint16_t)(205); + _curvea0[576] = _13957; + uint16_t _13958 = (uint16_t)(205); + _curvea0[577] = _13958; + uint16_t _13959 = (uint16_t)(205); + _curvea0[578] = _13959; + uint16_t _13960 = (uint16_t)(205); + _curvea0[579] = _13960; + uint16_t _13961 = (uint16_t)(205); + _curvea0[580] = _13961; + uint16_t _13962 = (uint16_t)(206); + _curvea0[581] = _13962; + uint16_t _13963 = (uint16_t)(206); + _curvea0[582] = _13963; + uint16_t _13964 = (uint16_t)(206); + _curvea0[583] = _13964; + uint16_t _13965 = (uint16_t)(206); + _curvea0[584] = _13965; + uint16_t _13966 = (uint16_t)(206); + _curvea0[585] = _13966; + uint16_t _13967 = (uint16_t)(206); + _curvea0[586] = _13967; + uint16_t _13968 = (uint16_t)(207); + _curvea0[587] = _13968; + uint16_t _13969 = (uint16_t)(207); + _curvea0[588] = _13969; + uint16_t _13970 = (uint16_t)(207); + _curvea0[589] = _13970; + uint16_t _13971 = (uint16_t)(207); + _curvea0[590] = _13971; + uint16_t _13972 = (uint16_t)(207); + _curvea0[591] = _13972; + uint16_t _13973 = (uint16_t)(207); + _curvea0[592] = _13973; + uint16_t _13974 = (uint16_t)(208); + _curvea0[593] = _13974; + uint16_t _13975 = (uint16_t)(208); + _curvea0[594] = _13975; + uint16_t _13976 = (uint16_t)(208); + _curvea0[595] = _13976; + uint16_t _13977 = (uint16_t)(208); + _curvea0[596] = _13977; + uint16_t _13978 = (uint16_t)(208); + _curvea0[597] = _13978; + uint16_t _13979 = (uint16_t)(208); + _curvea0[598] = _13979; + uint16_t _13980 = (uint16_t)(209); + _curvea0[599] = _13980; + uint16_t _13981 = (uint16_t)(209); + _curvea0[600] = _13981; + uint16_t _13982 = (uint16_t)(209); + _curvea0[601] = _13982; + uint16_t _13983 = (uint16_t)(209); + _curvea0[602] = _13983; + uint16_t _13984 = (uint16_t)(209); + _curvea0[603] = _13984; + uint16_t _13985 = (uint16_t)(209); + _curvea0[604] = _13985; + uint16_t _13986 = (uint16_t)(209); + _curvea0[605] = _13986; + uint16_t _13987 = (uint16_t)(210); + _curvea0[606] = _13987; + uint16_t _13988 = (uint16_t)(210); + _curvea0[607] = _13988; + uint16_t _13989 = (uint16_t)(210); + _curvea0[608] = _13989; + uint16_t _13990 = (uint16_t)(210); + _curvea0[609] = _13990; + uint16_t _13991 = (uint16_t)(210); + _curvea0[610] = _13991; + uint16_t _13992 = (uint16_t)(210); + _curvea0[611] = _13992; + uint16_t _13993 = (uint16_t)(211); + _curvea0[612] = _13993; + uint16_t _13994 = (uint16_t)(211); + _curvea0[613] = _13994; + uint16_t _13995 = (uint16_t)(211); + _curvea0[614] = _13995; + uint16_t _13996 = (uint16_t)(211); + _curvea0[615] = _13996; + uint16_t _13997 = (uint16_t)(211); + _curvea0[616] = _13997; + uint16_t _13998 = (uint16_t)(211); + _curvea0[617] = _13998; + uint16_t _13999 = (uint16_t)(211); + _curvea0[618] = _13999; + uint16_t _14000 = (uint16_t)(212); + _curvea0[619] = _14000; + uint16_t _14001 = (uint16_t)(212); + _curvea0[620] = _14001; + uint16_t _14002 = (uint16_t)(212); + _curvea0[621] = _14002; + uint16_t _14003 = (uint16_t)(212); + _curvea0[622] = _14003; + uint16_t _14004 = (uint16_t)(212); + _curvea0[623] = _14004; + uint16_t _14005 = (uint16_t)(212); + _curvea0[624] = _14005; + uint16_t _14006 = (uint16_t)(213); + _curvea0[625] = _14006; + uint16_t _14007 = (uint16_t)(213); + _curvea0[626] = _14007; + uint16_t _14008 = (uint16_t)(213); + _curvea0[627] = _14008; + uint16_t _14009 = (uint16_t)(213); + _curvea0[628] = _14009; + uint16_t _14010 = (uint16_t)(213); + _curvea0[629] = _14010; + uint16_t _14011 = (uint16_t)(213); + _curvea0[630] = _14011; + uint16_t _14012 = (uint16_t)(213); + _curvea0[631] = _14012; + uint16_t _14013 = (uint16_t)(214); + _curvea0[632] = _14013; + uint16_t _14014 = (uint16_t)(214); + _curvea0[633] = _14014; + uint16_t _14015 = (uint16_t)(214); + _curvea0[634] = _14015; + uint16_t _14016 = (uint16_t)(214); + _curvea0[635] = _14016; + uint16_t _14017 = (uint16_t)(214); + _curvea0[636] = _14017; + uint16_t _14018 = (uint16_t)(214); + _curvea0[637] = _14018; + uint16_t _14019 = (uint16_t)(214); + _curvea0[638] = _14019; + uint16_t _14020 = (uint16_t)(215); + _curvea0[639] = _14020; + uint16_t _14021 = (uint16_t)(215); + _curvea0[640] = _14021; + uint16_t _14022 = (uint16_t)(215); + _curvea0[641] = _14022; + uint16_t _14023 = (uint16_t)(215); + _curvea0[642] = _14023; + uint16_t _14024 = (uint16_t)(215); + _curvea0[643] = _14024; + uint16_t _14025 = (uint16_t)(215); + _curvea0[644] = _14025; + uint16_t _14026 = (uint16_t)(216); + _curvea0[645] = _14026; + uint16_t _14027 = (uint16_t)(216); + _curvea0[646] = _14027; + uint16_t _14028 = (uint16_t)(216); + _curvea0[647] = _14028; + uint16_t _14029 = (uint16_t)(216); + _curvea0[648] = _14029; + uint16_t _14030 = (uint16_t)(216); + _curvea0[649] = _14030; + uint16_t _14031 = (uint16_t)(216); + _curvea0[650] = _14031; + uint16_t _14032 = (uint16_t)(216); + _curvea0[651] = _14032; + uint16_t _14033 = (uint16_t)(217); + _curvea0[652] = _14033; + uint16_t _14034 = (uint16_t)(217); + _curvea0[653] = _14034; + uint16_t _14035 = (uint16_t)(217); + _curvea0[654] = _14035; + uint16_t _14036 = (uint16_t)(217); + _curvea0[655] = _14036; + uint16_t _14037 = (uint16_t)(217); + _curvea0[656] = _14037; + uint16_t _14038 = (uint16_t)(217); + _curvea0[657] = _14038; + uint16_t _14039 = (uint16_t)(217); + _curvea0[658] = _14039; + uint16_t _14040 = (uint16_t)(218); + _curvea0[659] = _14040; + uint16_t _14041 = (uint16_t)(218); + _curvea0[660] = _14041; + uint16_t _14042 = (uint16_t)(218); + _curvea0[661] = _14042; + uint16_t _14043 = (uint16_t)(218); + _curvea0[662] = _14043; + uint16_t _14044 = (uint16_t)(218); + _curvea0[663] = _14044; + uint16_t _14045 = (uint16_t)(218); + _curvea0[664] = _14045; + uint16_t _14046 = (uint16_t)(218); + _curvea0[665] = _14046; + uint16_t _14047 = (uint16_t)(219); + _curvea0[666] = _14047; + uint16_t _14048 = (uint16_t)(219); + _curvea0[667] = _14048; + uint16_t _14049 = (uint16_t)(219); + _curvea0[668] = _14049; + uint16_t _14050 = (uint16_t)(219); + _curvea0[669] = _14050; + uint16_t _14051 = (uint16_t)(219); + _curvea0[670] = _14051; + uint16_t _14052 = (uint16_t)(219); + _curvea0[671] = _14052; + uint16_t _14053 = (uint16_t)(219); + _curvea0[672] = _14053; + uint16_t _14054 = (uint16_t)(220); + _curvea0[673] = _14054; + uint16_t _14055 = (uint16_t)(220); + _curvea0[674] = _14055; + uint16_t _14056 = (uint16_t)(220); + _curvea0[675] = _14056; + uint16_t _14057 = (uint16_t)(220); + _curvea0[676] = _14057; + uint16_t _14058 = (uint16_t)(220); + _curvea0[677] = _14058; + uint16_t _14059 = (uint16_t)(220); + _curvea0[678] = _14059; + uint16_t _14060 = (uint16_t)(220); + _curvea0[679] = _14060; + uint16_t _14061 = (uint16_t)(220); + _curvea0[680] = _14061; + uint16_t _14062 = (uint16_t)(221); + _curvea0[681] = _14062; + uint16_t _14063 = (uint16_t)(221); + _curvea0[682] = _14063; + uint16_t _14064 = (uint16_t)(221); + _curvea0[683] = _14064; + uint16_t _14065 = (uint16_t)(221); + _curvea0[684] = _14065; + uint16_t _14066 = (uint16_t)(221); + _curvea0[685] = _14066; + uint16_t _14067 = (uint16_t)(221); + _curvea0[686] = _14067; + uint16_t _14068 = (uint16_t)(221); + _curvea0[687] = _14068; + uint16_t _14069 = (uint16_t)(222); + _curvea0[688] = _14069; + uint16_t _14070 = (uint16_t)(222); + _curvea0[689] = _14070; + uint16_t _14071 = (uint16_t)(222); + _curvea0[690] = _14071; + uint16_t _14072 = (uint16_t)(222); + _curvea0[691] = _14072; + uint16_t _14073 = (uint16_t)(222); + _curvea0[692] = _14073; + uint16_t _14074 = (uint16_t)(222); + _curvea0[693] = _14074; + uint16_t _14075 = (uint16_t)(222); + _curvea0[694] = _14075; + uint16_t _14076 = (uint16_t)(223); + _curvea0[695] = _14076; + uint16_t _14077 = (uint16_t)(223); + _curvea0[696] = _14077; + uint16_t _14078 = (uint16_t)(223); + _curvea0[697] = _14078; + uint16_t _14079 = (uint16_t)(223); + _curvea0[698] = _14079; + uint16_t _14080 = (uint16_t)(223); + _curvea0[699] = _14080; + uint16_t _14081 = (uint16_t)(223); + _curvea0[700] = _14081; + uint16_t _14082 = (uint16_t)(223); + _curvea0[701] = _14082; + uint16_t _14083 = (uint16_t)(223); + _curvea0[702] = _14083; + uint16_t _14084 = (uint16_t)(224); + _curvea0[703] = _14084; + uint16_t _14085 = (uint16_t)(224); + _curvea0[704] = _14085; + uint16_t _14086 = (uint16_t)(224); + _curvea0[705] = _14086; + uint16_t _14087 = (uint16_t)(224); + _curvea0[706] = _14087; + uint16_t _14088 = (uint16_t)(224); + _curvea0[707] = _14088; + uint16_t _14089 = (uint16_t)(224); + _curvea0[708] = _14089; + uint16_t _14090 = (uint16_t)(224); + _curvea0[709] = _14090; + uint16_t _14091 = (uint16_t)(224); + _curvea0[710] = _14091; + uint16_t _14092 = (uint16_t)(225); + _curvea0[711] = _14092; + uint16_t _14093 = (uint16_t)(225); + _curvea0[712] = _14093; + uint16_t _14094 = (uint16_t)(225); + _curvea0[713] = _14094; + uint16_t _14095 = (uint16_t)(225); + _curvea0[714] = _14095; + uint16_t _14096 = (uint16_t)(225); + _curvea0[715] = _14096; + uint16_t _14097 = (uint16_t)(225); + _curvea0[716] = _14097; + uint16_t _14098 = (uint16_t)(225); + _curvea0[717] = _14098; + uint16_t _14099 = (uint16_t)(226); + _curvea0[718] = _14099; + uint16_t _14100 = (uint16_t)(226); + _curvea0[719] = _14100; + uint16_t _14101 = (uint16_t)(226); + _curvea0[720] = _14101; + uint16_t _14102 = (uint16_t)(226); + _curvea0[721] = _14102; + uint16_t _14103 = (uint16_t)(226); + _curvea0[722] = _14103; + uint16_t _14104 = (uint16_t)(226); + _curvea0[723] = _14104; + uint16_t _14105 = (uint16_t)(226); + _curvea0[724] = _14105; + uint16_t _14106 = (uint16_t)(226); + _curvea0[725] = _14106; + uint16_t _14107 = (uint16_t)(227); + _curvea0[726] = _14107; + uint16_t _14108 = (uint16_t)(227); + _curvea0[727] = _14108; + uint16_t _14109 = (uint16_t)(227); + _curvea0[728] = _14109; + uint16_t _14110 = (uint16_t)(227); + _curvea0[729] = _14110; + uint16_t _14111 = (uint16_t)(227); + _curvea0[730] = _14111; + uint16_t _14112 = (uint16_t)(227); + _curvea0[731] = _14112; + uint16_t _14113 = (uint16_t)(227); + _curvea0[732] = _14113; + uint16_t _14114 = (uint16_t)(227); + _curvea0[733] = _14114; + uint16_t _14115 = (uint16_t)(228); + _curvea0[734] = _14115; + uint16_t _14116 = (uint16_t)(228); + _curvea0[735] = _14116; + uint16_t _14117 = (uint16_t)(228); + _curvea0[736] = _14117; + uint16_t _14118 = (uint16_t)(228); + _curvea0[737] = _14118; + uint16_t _14119 = (uint16_t)(228); + _curvea0[738] = _14119; + uint16_t _14120 = (uint16_t)(228); + _curvea0[739] = _14120; + uint16_t _14121 = (uint16_t)(228); + _curvea0[740] = _14121; + uint16_t _14122 = (uint16_t)(228); + _curvea0[741] = _14122; + uint16_t _14123 = (uint16_t)(228); + _curvea0[742] = _14123; + uint16_t _14124 = (uint16_t)(229); + _curvea0[743] = _14124; + uint16_t _14125 = (uint16_t)(229); + _curvea0[744] = _14125; + uint16_t _14126 = (uint16_t)(229); + _curvea0[745] = _14126; + uint16_t _14127 = (uint16_t)(229); + _curvea0[746] = _14127; + uint16_t _14128 = (uint16_t)(229); + _curvea0[747] = _14128; + uint16_t _14129 = (uint16_t)(229); + _curvea0[748] = _14129; + uint16_t _14130 = (uint16_t)(229); + _curvea0[749] = _14130; + uint16_t _14131 = (uint16_t)(229); + _curvea0[750] = _14131; + uint16_t _14132 = (uint16_t)(230); + _curvea0[751] = _14132; + uint16_t _14133 = (uint16_t)(230); + _curvea0[752] = _14133; + uint16_t _14134 = (uint16_t)(230); + _curvea0[753] = _14134; + uint16_t _14135 = (uint16_t)(230); + _curvea0[754] = _14135; + uint16_t _14136 = (uint16_t)(230); + _curvea0[755] = _14136; + uint16_t _14137 = (uint16_t)(230); + _curvea0[756] = _14137; + uint16_t _14138 = (uint16_t)(230); + _curvea0[757] = _14138; + uint16_t _14139 = (uint16_t)(230); + _curvea0[758] = _14139; + uint16_t _14140 = (uint16_t)(231); + _curvea0[759] = _14140; + uint16_t _14141 = (uint16_t)(231); + _curvea0[760] = _14141; + uint16_t _14142 = (uint16_t)(231); + _curvea0[761] = _14142; + uint16_t _14143 = (uint16_t)(231); + _curvea0[762] = _14143; + uint16_t _14144 = (uint16_t)(231); + _curvea0[763] = _14144; + uint16_t _14145 = (uint16_t)(231); + _curvea0[764] = _14145; + uint16_t _14146 = (uint16_t)(231); + _curvea0[765] = _14146; + uint16_t _14147 = (uint16_t)(231); + _curvea0[766] = _14147; + uint16_t _14148 = (uint16_t)(231); + _curvea0[767] = _14148; + uint16_t _14149 = (uint16_t)(232); + _curvea0[768] = _14149; + uint16_t _14150 = (uint16_t)(232); + _curvea0[769] = _14150; + uint16_t _14151 = (uint16_t)(232); + _curvea0[770] = _14151; + uint16_t _14152 = (uint16_t)(232); + _curvea0[771] = _14152; + uint16_t _14153 = (uint16_t)(232); + _curvea0[772] = _14153; + uint16_t _14154 = (uint16_t)(232); + _curvea0[773] = _14154; + uint16_t _14155 = (uint16_t)(232); + _curvea0[774] = _14155; + uint16_t _14156 = (uint16_t)(232); + _curvea0[775] = _14156; + uint16_t _14157 = (uint16_t)(233); + _curvea0[776] = _14157; + uint16_t _14158 = (uint16_t)(233); + _curvea0[777] = _14158; + uint16_t _14159 = (uint16_t)(233); + _curvea0[778] = _14159; + uint16_t _14160 = (uint16_t)(233); + _curvea0[779] = _14160; + uint16_t _14161 = (uint16_t)(233); + _curvea0[780] = _14161; + uint16_t _14162 = (uint16_t)(233); + _curvea0[781] = _14162; + uint16_t _14163 = (uint16_t)(233); + _curvea0[782] = _14163; + uint16_t _14164 = (uint16_t)(233); + _curvea0[783] = _14164; + uint16_t _14165 = (uint16_t)(233); + _curvea0[784] = _14165; + uint16_t _14166 = (uint16_t)(234); + _curvea0[785] = _14166; + uint16_t _14167 = (uint16_t)(234); + _curvea0[786] = _14167; + uint16_t _14168 = (uint16_t)(234); + _curvea0[787] = _14168; + uint16_t _14169 = (uint16_t)(234); + _curvea0[788] = _14169; + uint16_t _14170 = (uint16_t)(234); + _curvea0[789] = _14170; + uint16_t _14171 = (uint16_t)(234); + _curvea0[790] = _14171; + uint16_t _14172 = (uint16_t)(234); + _curvea0[791] = _14172; + uint16_t _14173 = (uint16_t)(234); + _curvea0[792] = _14173; + uint16_t _14174 = (uint16_t)(234); + _curvea0[793] = _14174; + uint16_t _14175 = (uint16_t)(235); + _curvea0[794] = _14175; + uint16_t _14176 = (uint16_t)(235); + _curvea0[795] = _14176; + uint16_t _14177 = (uint16_t)(235); + _curvea0[796] = _14177; + uint16_t _14178 = (uint16_t)(235); + _curvea0[797] = _14178; + uint16_t _14179 = (uint16_t)(235); + _curvea0[798] = _14179; + uint16_t _14180 = (uint16_t)(235); + _curvea0[799] = _14180; + uint16_t _14181 = (uint16_t)(235); + _curvea0[800] = _14181; + uint16_t _14182 = (uint16_t)(235); + _curvea0[801] = _14182; + uint16_t _14183 = (uint16_t)(235); + _curvea0[802] = _14183; + uint16_t _14184 = (uint16_t)(236); + _curvea0[803] = _14184; + uint16_t _14185 = (uint16_t)(236); + _curvea0[804] = _14185; + uint16_t _14186 = (uint16_t)(236); + _curvea0[805] = _14186; + uint16_t _14187 = (uint16_t)(236); + _curvea0[806] = _14187; + uint16_t _14188 = (uint16_t)(236); + _curvea0[807] = _14188; + uint16_t _14189 = (uint16_t)(236); + _curvea0[808] = _14189; + uint16_t _14190 = (uint16_t)(236); + _curvea0[809] = _14190; + uint16_t _14191 = (uint16_t)(236); + _curvea0[810] = _14191; + uint16_t _14192 = (uint16_t)(236); + _curvea0[811] = _14192; + uint16_t _14193 = (uint16_t)(237); + _curvea0[812] = _14193; + uint16_t _14194 = (uint16_t)(237); + _curvea0[813] = _14194; + uint16_t _14195 = (uint16_t)(237); + _curvea0[814] = _14195; + uint16_t _14196 = (uint16_t)(237); + _curvea0[815] = _14196; + uint16_t _14197 = (uint16_t)(237); + _curvea0[816] = _14197; + uint16_t _14198 = (uint16_t)(237); + _curvea0[817] = _14198; + uint16_t _14199 = (uint16_t)(237); + _curvea0[818] = _14199; + uint16_t _14200 = (uint16_t)(237); + _curvea0[819] = _14200; + uint16_t _14201 = (uint16_t)(237); + _curvea0[820] = _14201; + uint16_t _14202 = (uint16_t)(237); + _curvea0[821] = _14202; + uint16_t _14203 = (uint16_t)(238); + _curvea0[822] = _14203; + uint16_t _14204 = (uint16_t)(238); + _curvea0[823] = _14204; + uint16_t _14205 = (uint16_t)(238); + _curvea0[824] = _14205; + uint16_t _14206 = (uint16_t)(238); + _curvea0[825] = _14206; + uint16_t _14207 = (uint16_t)(238); + _curvea0[826] = _14207; + uint16_t _14208 = (uint16_t)(238); + _curvea0[827] = _14208; + uint16_t _14209 = (uint16_t)(238); + _curvea0[828] = _14209; + uint16_t _14210 = (uint16_t)(238); + _curvea0[829] = _14210; + uint16_t _14211 = (uint16_t)(238); + _curvea0[830] = _14211; + uint16_t _14212 = (uint16_t)(239); + _curvea0[831] = _14212; + uint16_t _14213 = (uint16_t)(239); + _curvea0[832] = _14213; + uint16_t _14214 = (uint16_t)(239); + _curvea0[833] = _14214; + uint16_t _14215 = (uint16_t)(239); + _curvea0[834] = _14215; + uint16_t _14216 = (uint16_t)(239); + _curvea0[835] = _14216; + uint16_t _14217 = (uint16_t)(239); + _curvea0[836] = _14217; + uint16_t _14218 = (uint16_t)(239); + _curvea0[837] = _14218; + uint16_t _14219 = (uint16_t)(239); + _curvea0[838] = _14219; + uint16_t _14220 = (uint16_t)(239); + _curvea0[839] = _14220; + uint16_t _14221 = (uint16_t)(239); + _curvea0[840] = _14221; + uint16_t _14222 = (uint16_t)(240); + _curvea0[841] = _14222; + uint16_t _14223 = (uint16_t)(240); + _curvea0[842] = _14223; + uint16_t _14224 = (uint16_t)(240); + _curvea0[843] = _14224; + uint16_t _14225 = (uint16_t)(240); + _curvea0[844] = _14225; + uint16_t _14226 = (uint16_t)(240); + _curvea0[845] = _14226; + uint16_t _14227 = (uint16_t)(240); + _curvea0[846] = _14227; + uint16_t _14228 = (uint16_t)(240); + _curvea0[847] = _14228; + uint16_t _14229 = (uint16_t)(240); + _curvea0[848] = _14229; + uint16_t _14230 = (uint16_t)(240); + _curvea0[849] = _14230; + uint16_t _14231 = (uint16_t)(240); + _curvea0[850] = _14231; + uint16_t _14232 = (uint16_t)(241); + _curvea0[851] = _14232; + uint16_t _14233 = (uint16_t)(241); + _curvea0[852] = _14233; + uint16_t _14234 = (uint16_t)(241); + _curvea0[853] = _14234; + uint16_t _14235 = (uint16_t)(241); + _curvea0[854] = _14235; + uint16_t _14236 = (uint16_t)(241); + _curvea0[855] = _14236; + uint16_t _14237 = (uint16_t)(241); + _curvea0[856] = _14237; + uint16_t _14238 = (uint16_t)(241); + _curvea0[857] = _14238; + uint16_t _14239 = (uint16_t)(241); + _curvea0[858] = _14239; + uint16_t _14240 = (uint16_t)(241); + _curvea0[859] = _14240; + uint16_t _14241 = (uint16_t)(241); + _curvea0[860] = _14241; + uint16_t _14242 = (uint16_t)(242); + _curvea0[861] = _14242; + uint16_t _14243 = (uint16_t)(242); + _curvea0[862] = _14243; + uint16_t _14244 = (uint16_t)(242); + _curvea0[863] = _14244; + uint16_t _14245 = (uint16_t)(242); + _curvea0[864] = _14245; + uint16_t _14246 = (uint16_t)(242); + _curvea0[865] = _14246; + uint16_t _14247 = (uint16_t)(242); + _curvea0[866] = _14247; + uint16_t _14248 = (uint16_t)(242); + _curvea0[867] = _14248; + uint16_t _14249 = (uint16_t)(242); + _curvea0[868] = _14249; + uint16_t _14250 = (uint16_t)(242); + _curvea0[869] = _14250; + uint16_t _14251 = (uint16_t)(242); + _curvea0[870] = _14251; + uint16_t _14252 = (uint16_t)(243); + _curvea0[871] = _14252; + uint16_t _14253 = (uint16_t)(243); + _curvea0[872] = _14253; + uint16_t _14254 = (uint16_t)(243); + _curvea0[873] = _14254; + uint16_t _14255 = (uint16_t)(243); + _curvea0[874] = _14255; + uint16_t _14256 = (uint16_t)(243); + _curvea0[875] = _14256; + uint16_t _14257 = (uint16_t)(243); + _curvea0[876] = _14257; + uint16_t _14258 = (uint16_t)(243); + _curvea0[877] = _14258; + uint16_t _14259 = (uint16_t)(243); + _curvea0[878] = _14259; + uint16_t _14260 = (uint16_t)(243); + _curvea0[879] = _14260; + uint16_t _14261 = (uint16_t)(243); + _curvea0[880] = _14261; + uint16_t _14262 = (uint16_t)(244); + _curvea0[881] = _14262; + uint16_t _14263 = (uint16_t)(244); + _curvea0[882] = _14263; + uint16_t _14264 = (uint16_t)(244); + _curvea0[883] = _14264; + uint16_t _14265 = (uint16_t)(244); + _curvea0[884] = _14265; + uint16_t _14266 = (uint16_t)(244); + _curvea0[885] = _14266; + uint16_t _14267 = (uint16_t)(244); + _curvea0[886] = _14267; + uint16_t _14268 = (uint16_t)(244); + _curvea0[887] = _14268; + uint16_t _14269 = (uint16_t)(244); + _curvea0[888] = _14269; + uint16_t _14270 = (uint16_t)(244); + _curvea0[889] = _14270; + uint16_t _14271 = (uint16_t)(244); + _curvea0[890] = _14271; + uint16_t _14272 = (uint16_t)(244); + _curvea0[891] = _14272; + uint16_t _14273 = (uint16_t)(245); + _curvea0[892] = _14273; + uint16_t _14274 = (uint16_t)(245); + _curvea0[893] = _14274; + uint16_t _14275 = (uint16_t)(245); + _curvea0[894] = _14275; + uint16_t _14276 = (uint16_t)(245); + _curvea0[895] = _14276; + uint16_t _14277 = (uint16_t)(245); + _curvea0[896] = _14277; + uint16_t _14278 = (uint16_t)(245); + _curvea0[897] = _14278; + uint16_t _14279 = (uint16_t)(245); + _curvea0[898] = _14279; + uint16_t _14280 = (uint16_t)(245); + _curvea0[899] = _14280; + uint16_t _14281 = (uint16_t)(245); + _curvea0[900] = _14281; + uint16_t _14282 = (uint16_t)(245); + _curvea0[901] = _14282; + uint16_t _14283 = (uint16_t)(245); + _curvea0[902] = _14283; + uint16_t _14284 = (uint16_t)(246); + _curvea0[903] = _14284; + uint16_t _14285 = (uint16_t)(246); + _curvea0[904] = _14285; + uint16_t _14286 = (uint16_t)(246); + _curvea0[905] = _14286; + uint16_t _14287 = (uint16_t)(246); + _curvea0[906] = _14287; + uint16_t _14288 = (uint16_t)(246); + _curvea0[907] = _14288; + uint16_t _14289 = (uint16_t)(246); + _curvea0[908] = _14289; + uint16_t _14290 = (uint16_t)(246); + _curvea0[909] = _14290; + uint16_t _14291 = (uint16_t)(246); + _curvea0[910] = _14291; + uint16_t _14292 = (uint16_t)(246); + _curvea0[911] = _14292; + uint16_t _14293 = (uint16_t)(246); + _curvea0[912] = _14293; + uint16_t _14294 = (uint16_t)(246); + _curvea0[913] = _14294; + uint16_t _14295 = (uint16_t)(247); + _curvea0[914] = _14295; + uint16_t _14296 = (uint16_t)(247); + _curvea0[915] = _14296; + uint16_t _14297 = (uint16_t)(247); + _curvea0[916] = _14297; + uint16_t _14298 = (uint16_t)(247); + _curvea0[917] = _14298; + uint16_t _14299 = (uint16_t)(247); + _curvea0[918] = _14299; + uint16_t _14300 = (uint16_t)(247); + _curvea0[919] = _14300; + uint16_t _14301 = (uint16_t)(247); + _curvea0[920] = _14301; + uint16_t _14302 = (uint16_t)(247); + _curvea0[921] = _14302; + uint16_t _14303 = (uint16_t)(247); + _curvea0[922] = _14303; + uint16_t _14304 = (uint16_t)(247); + _curvea0[923] = _14304; + uint16_t _14305 = (uint16_t)(247); + _curvea0[924] = _14305; + uint16_t _14306 = (uint16_t)(248); + _curvea0[925] = _14306; + uint16_t _14307 = (uint16_t)(248); + _curvea0[926] = _14307; + uint16_t _14308 = (uint16_t)(248); + _curvea0[927] = _14308; + uint16_t _14309 = (uint16_t)(248); + _curvea0[928] = _14309; + uint16_t _14310 = (uint16_t)(248); + _curvea0[929] = _14310; + uint16_t _14311 = (uint16_t)(248); + _curvea0[930] = _14311; + uint16_t _14312 = (uint16_t)(248); + _curvea0[931] = _14312; + uint16_t _14313 = (uint16_t)(248); + _curvea0[932] = _14313; + uint16_t _14314 = (uint16_t)(248); + _curvea0[933] = _14314; + uint16_t _14315 = (uint16_t)(248); + _curvea0[934] = _14315; + uint16_t _14316 = (uint16_t)(248); + _curvea0[935] = _14316; + uint16_t _14317 = (uint16_t)(249); + _curvea0[936] = _14317; + uint16_t _14318 = (uint16_t)(249); + _curvea0[937] = _14318; + uint16_t _14319 = (uint16_t)(249); + _curvea0[938] = _14319; + uint16_t _14320 = (uint16_t)(249); + _curvea0[939] = _14320; + uint16_t _14321 = (uint16_t)(249); + _curvea0[940] = _14321; + uint16_t _14322 = (uint16_t)(249); + _curvea0[941] = _14322; + uint16_t _14323 = (uint16_t)(249); + _curvea0[942] = _14323; + uint16_t _14324 = (uint16_t)(249); + _curvea0[943] = _14324; + uint16_t _14325 = (uint16_t)(249); + _curvea0[944] = _14325; + uint16_t _14326 = (uint16_t)(249); + _curvea0[945] = _14326; + uint16_t _14327 = (uint16_t)(249); + _curvea0[946] = _14327; + uint16_t _14328 = (uint16_t)(249); + _curvea0[947] = _14328; + uint16_t _14329 = (uint16_t)(250); + _curvea0[948] = _14329; + uint16_t _14330 = (uint16_t)(250); + _curvea0[949] = _14330; + uint16_t _14331 = (uint16_t)(250); + _curvea0[950] = _14331; + uint16_t _14332 = (uint16_t)(250); + _curvea0[951] = _14332; + uint16_t _14333 = (uint16_t)(250); + _curvea0[952] = _14333; + uint16_t _14334 = (uint16_t)(250); + _curvea0[953] = _14334; + uint16_t _14335 = (uint16_t)(250); + _curvea0[954] = _14335; + uint16_t _14336 = (uint16_t)(250); + _curvea0[955] = _14336; + uint16_t _14337 = (uint16_t)(250); + _curvea0[956] = _14337; + uint16_t _14338 = (uint16_t)(250); + _curvea0[957] = _14338; + uint16_t _14339 = (uint16_t)(250); + _curvea0[958] = _14339; + uint16_t _14340 = (uint16_t)(250); + _curvea0[959] = _14340; + uint16_t _14341 = (uint16_t)(251); + _curvea0[960] = _14341; + uint16_t _14342 = (uint16_t)(251); + _curvea0[961] = _14342; + uint16_t _14343 = (uint16_t)(251); + _curvea0[962] = _14343; + uint16_t _14344 = (uint16_t)(251); + _curvea0[963] = _14344; + uint16_t _14345 = (uint16_t)(251); + _curvea0[964] = _14345; + uint16_t _14346 = (uint16_t)(251); + _curvea0[965] = _14346; + uint16_t _14347 = (uint16_t)(251); + _curvea0[966] = _14347; + uint16_t _14348 = (uint16_t)(251); + _curvea0[967] = _14348; + uint16_t _14349 = (uint16_t)(251); + _curvea0[968] = _14349; + uint16_t _14350 = (uint16_t)(251); + _curvea0[969] = _14350; + uint16_t _14351 = (uint16_t)(251); + _curvea0[970] = _14351; + uint16_t _14352 = (uint16_t)(251); + _curvea0[971] = _14352; + uint16_t _14353 = (uint16_t)(252); + _curvea0[972] = _14353; + uint16_t _14354 = (uint16_t)(252); + _curvea0[973] = _14354; + uint16_t _14355 = (uint16_t)(252); + _curvea0[974] = _14355; + uint16_t _14356 = (uint16_t)(252); + _curvea0[975] = _14356; + uint16_t _14357 = (uint16_t)(252); + _curvea0[976] = _14357; + uint16_t _14358 = (uint16_t)(252); + _curvea0[977] = _14358; + uint16_t _14359 = (uint16_t)(252); + _curvea0[978] = _14359; + uint16_t _14360 = (uint16_t)(252); + _curvea0[979] = _14360; + uint16_t _14361 = (uint16_t)(252); + _curvea0[980] = _14361; + uint16_t _14362 = (uint16_t)(252); + _curvea0[981] = _14362; + uint16_t _14363 = (uint16_t)(252); + _curvea0[982] = _14363; + uint16_t _14364 = (uint16_t)(252); + _curvea0[983] = _14364; + uint16_t _14365 = (uint16_t)(252); + _curvea0[984] = _14365; + uint16_t _14366 = (uint16_t)(253); + _curvea0[985] = _14366; + uint16_t _14367 = (uint16_t)(253); + _curvea0[986] = _14367; + uint16_t _14368 = (uint16_t)(253); + _curvea0[987] = _14368; + uint16_t _14369 = (uint16_t)(253); + _curvea0[988] = _14369; + uint16_t _14370 = (uint16_t)(253); + _curvea0[989] = _14370; + uint16_t _14371 = (uint16_t)(253); + _curvea0[990] = _14371; + uint16_t _14372 = (uint16_t)(253); + _curvea0[991] = _14372; + uint16_t _14373 = (uint16_t)(253); + _curvea0[992] = _14373; + uint16_t _14374 = (uint16_t)(253); + _curvea0[993] = _14374; + uint16_t _14375 = (uint16_t)(253); + _curvea0[994] = _14375; + uint16_t _14376 = (uint16_t)(253); + _curvea0[995] = _14376; + uint16_t _14377 = (uint16_t)(253); + _curvea0[996] = _14377; + uint16_t _14378 = (uint16_t)(253); + _curvea0[997] = _14378; + uint16_t _14379 = (uint16_t)(254); + _curvea0[998] = _14379; + uint16_t _14380 = (uint16_t)(254); + _curvea0[999] = _14380; + uint16_t _14381 = (uint16_t)(254); + _curvea0[1000] = _14381; + uint16_t _14382 = (uint16_t)(254); + _curvea0[1001] = _14382; + uint16_t _14383 = (uint16_t)(254); + _curvea0[1002] = _14383; + uint16_t _14384 = (uint16_t)(254); + _curvea0[1003] = _14384; + uint16_t _14385 = (uint16_t)(254); + _curvea0[1004] = _14385; + uint16_t _14386 = (uint16_t)(254); + _curvea0[1005] = _14386; + uint16_t _14387 = (uint16_t)(254); + _curvea0[1006] = _14387; + uint16_t _14388 = (uint16_t)(254); + _curvea0[1007] = _14388; + uint16_t _14389 = (uint16_t)(254); + _curvea0[1008] = _14389; + uint16_t _14390 = (uint16_t)(254); + _curvea0[1009] = _14390; + uint16_t _14391 = (uint16_t)(254); + _curvea0[1010] = _14391; + uint16_t _14392 = (uint16_t)(255); + _curvea0[1011] = _14392; + uint16_t _14393 = (uint16_t)(255); + _curvea0[1012] = _14393; + uint16_t _14394 = (uint16_t)(255); + _curvea0[1013] = _14394; + uint16_t _14395 = (uint16_t)(255); + _curvea0[1014] = _14395; + uint16_t _14396 = (uint16_t)(255); + _curvea0[1015] = _14396; + uint16_t _14397 = (uint16_t)(255); + _curvea0[1016] = _14397; + uint16_t _14398 = (uint16_t)(255); + _curvea0[1017] = _14398; + uint16_t _14399 = (uint16_t)(255); + _curvea0[1018] = _14399; + uint16_t _14400 = (uint16_t)(255); + _curvea0[1019] = _14400; + uint16_t _14401 = (uint16_t)(255); + _curvea0[1020] = _14401; + uint16_t _14402 = (uint16_t)(255); + _curvea0[1021] = _14402; + uint16_t _14403 = (uint16_t)(255); + _curvea0[1022] = _14403; + uint16_t _14404 = (uint16_t)(255); + _curvea0[1023] = _14404; + + int16_t _14405 = (int16_t)(1023); + int16_t _14406 = min(_corrected_stencil_10, _14405); + int16_t _14407 = (int16_t)(0); + int16_t _14408 = max(_14406, _14407); + uint16_t _14409 = (uint16_t)(_14408); + int32_t _14410 = (int32_t)(_14409); + uint16_t _14411 = ((const uint16_t *)_curvea0)[_14410]; + return _14411; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_10(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_11 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _14430 = (uint16_t)(0); + _curvea0[0] = _14430; + uint16_t _14431 = (uint16_t)(4); + _curvea0[1] = _14431; + uint16_t _14432 = (uint16_t)(7); + _curvea0[2] = _14432; + uint16_t _14433 = (uint16_t)(8); + _curvea0[3] = _14433; + uint16_t _14434 = (uint16_t)(10); + _curvea0[4] = _14434; + uint16_t _14435 = (uint16_t)(11); + _curvea0[5] = _14435; + uint16_t _14436 = (uint16_t)(12); + _curvea0[6] = _14436; + uint16_t _14437 = (uint16_t)(13); + _curvea0[7] = _14437; + uint16_t _14438 = (uint16_t)(14); + _curvea0[8] = _14438; + uint16_t _14439 = (uint16_t)(15); + _curvea0[9] = _14439; + uint16_t _14440 = (uint16_t)(16); + _curvea0[10] = _14440; + uint16_t _14441 = (uint16_t)(17); + _curvea0[11] = _14441; + uint16_t _14442 = (uint16_t)(18); + _curvea0[12] = _14442; + uint16_t _14443 = (uint16_t)(19); + _curvea0[13] = _14443; + uint16_t _14444 = (uint16_t)(20); + _curvea0[14] = _14444; + uint16_t _14445 = (uint16_t)(21); + _curvea0[15] = _14445; + uint16_t _14446 = (uint16_t)(22); + _curvea0[16] = _14446; + uint16_t _14447 = (uint16_t)(22); + _curvea0[17] = _14447; + uint16_t _14448 = (uint16_t)(23); + _curvea0[18] = _14448; + uint16_t _14449 = (uint16_t)(24); + _curvea0[19] = _14449; + uint16_t _14450 = (uint16_t)(25); + _curvea0[20] = _14450; + uint16_t _14451 = (uint16_t)(25); + _curvea0[21] = _14451; + uint16_t _14452 = (uint16_t)(26); + _curvea0[22] = _14452; + uint16_t _14453 = (uint16_t)(27); + _curvea0[23] = _14453; + uint16_t _14454 = (uint16_t)(27); + _curvea0[24] = _14454; + uint16_t _14455 = (uint16_t)(28); + _curvea0[25] = _14455; + uint16_t _14456 = (uint16_t)(29); + _curvea0[26] = _14456; + uint16_t _14457 = (uint16_t)(29); + _curvea0[27] = _14457; + uint16_t _14458 = (uint16_t)(30); + _curvea0[28] = _14458; + uint16_t _14459 = (uint16_t)(31); + _curvea0[29] = _14459; + uint16_t _14460 = (uint16_t)(31); + _curvea0[30] = _14460; + uint16_t _14461 = (uint16_t)(32); + _curvea0[31] = _14461; + uint16_t _14462 = (uint16_t)(33); + _curvea0[32] = _14462; + uint16_t _14463 = (uint16_t)(33); + _curvea0[33] = _14463; + uint16_t _14464 = (uint16_t)(34); + _curvea0[34] = _14464; + uint16_t _14465 = (uint16_t)(34); + _curvea0[35] = _14465; + uint16_t _14466 = (uint16_t)(35); + _curvea0[36] = _14466; + uint16_t _14467 = (uint16_t)(36); + _curvea0[37] = _14467; + uint16_t _14468 = (uint16_t)(36); + _curvea0[38] = _14468; + uint16_t _14469 = (uint16_t)(37); + _curvea0[39] = _14469; + uint16_t _14470 = (uint16_t)(37); + _curvea0[40] = _14470; + uint16_t _14471 = (uint16_t)(38); + _curvea0[41] = _14471; + uint16_t _14472 = (uint16_t)(39); + _curvea0[42] = _14472; + uint16_t _14473 = (uint16_t)(39); + _curvea0[43] = _14473; + uint16_t _14474 = (uint16_t)(40); + _curvea0[44] = _14474; + uint16_t _14475 = (uint16_t)(40); + _curvea0[45] = _14475; + uint16_t _14476 = (uint16_t)(41); + _curvea0[46] = _14476; + uint16_t _14477 = (uint16_t)(41); + _curvea0[47] = _14477; + uint16_t _14478 = (uint16_t)(42); + _curvea0[48] = _14478; + uint16_t _14479 = (uint16_t)(42); + _curvea0[49] = _14479; + uint16_t _14480 = (uint16_t)(43); + _curvea0[50] = _14480; + uint16_t _14481 = (uint16_t)(44); + _curvea0[51] = _14481; + uint16_t _14482 = (uint16_t)(44); + _curvea0[52] = _14482; + uint16_t _14483 = (uint16_t)(45); + _curvea0[53] = _14483; + uint16_t _14484 = (uint16_t)(45); + _curvea0[54] = _14484; + uint16_t _14485 = (uint16_t)(46); + _curvea0[55] = _14485; + uint16_t _14486 = (uint16_t)(46); + _curvea0[56] = _14486; + uint16_t _14487 = (uint16_t)(47); + _curvea0[57] = _14487; + uint16_t _14488 = (uint16_t)(47); + _curvea0[58] = _14488; + uint16_t _14489 = (uint16_t)(48); + _curvea0[59] = _14489; + uint16_t _14490 = (uint16_t)(48); + _curvea0[60] = _14490; + uint16_t _14491 = (uint16_t)(49); + _curvea0[61] = _14491; + uint16_t _14492 = (uint16_t)(49); + _curvea0[62] = _14492; + uint16_t _14493 = (uint16_t)(50); + _curvea0[63] = _14493; + uint16_t _14494 = (uint16_t)(50); + _curvea0[64] = _14494; + uint16_t _14495 = (uint16_t)(51); + _curvea0[65] = _14495; + uint16_t _14496 = (uint16_t)(51); + _curvea0[66] = _14496; + uint16_t _14497 = (uint16_t)(52); + _curvea0[67] = _14497; + uint16_t _14498 = (uint16_t)(52); + _curvea0[68] = _14498; + uint16_t _14499 = (uint16_t)(53); + _curvea0[69] = _14499; + uint16_t _14500 = (uint16_t)(53); + _curvea0[70] = _14500; + uint16_t _14501 = (uint16_t)(54); + _curvea0[71] = _14501; + uint16_t _14502 = (uint16_t)(54); + _curvea0[72] = _14502; + uint16_t _14503 = (uint16_t)(55); + _curvea0[73] = _14503; + uint16_t _14504 = (uint16_t)(55); + _curvea0[74] = _14504; + uint16_t _14505 = (uint16_t)(56); + _curvea0[75] = _14505; + uint16_t _14506 = (uint16_t)(56); + _curvea0[76] = _14506; + uint16_t _14507 = (uint16_t)(57); + _curvea0[77] = _14507; + uint16_t _14508 = (uint16_t)(57); + _curvea0[78] = _14508; + uint16_t _14509 = (uint16_t)(58); + _curvea0[79] = _14509; + uint16_t _14510 = (uint16_t)(58); + _curvea0[80] = _14510; + uint16_t _14511 = (uint16_t)(58); + _curvea0[81] = _14511; + uint16_t _14512 = (uint16_t)(59); + _curvea0[82] = _14512; + uint16_t _14513 = (uint16_t)(59); + _curvea0[83] = _14513; + uint16_t _14514 = (uint16_t)(60); + _curvea0[84] = _14514; + uint16_t _14515 = (uint16_t)(60); + _curvea0[85] = _14515; + uint16_t _14516 = (uint16_t)(61); + _curvea0[86] = _14516; + uint16_t _14517 = (uint16_t)(61); + _curvea0[87] = _14517; + uint16_t _14518 = (uint16_t)(62); + _curvea0[88] = _14518; + uint16_t _14519 = (uint16_t)(62); + _curvea0[89] = _14519; + uint16_t _14520 = (uint16_t)(63); + _curvea0[90] = _14520; + uint16_t _14521 = (uint16_t)(63); + _curvea0[91] = _14521; + uint16_t _14522 = (uint16_t)(64); + _curvea0[92] = _14522; + uint16_t _14523 = (uint16_t)(64); + _curvea0[93] = _14523; + uint16_t _14524 = (uint16_t)(64); + _curvea0[94] = _14524; + uint16_t _14525 = (uint16_t)(65); + _curvea0[95] = _14525; + uint16_t _14526 = (uint16_t)(65); + _curvea0[96] = _14526; + uint16_t _14527 = (uint16_t)(66); + _curvea0[97] = _14527; + uint16_t _14528 = (uint16_t)(66); + _curvea0[98] = _14528; + uint16_t _14529 = (uint16_t)(67); + _curvea0[99] = _14529; + uint16_t _14530 = (uint16_t)(67); + _curvea0[100] = _14530; + uint16_t _14531 = (uint16_t)(68); + _curvea0[101] = _14531; + uint16_t _14532 = (uint16_t)(68); + _curvea0[102] = _14532; + uint16_t _14533 = (uint16_t)(68); + _curvea0[103] = _14533; + uint16_t _14534 = (uint16_t)(69); + _curvea0[104] = _14534; + uint16_t _14535 = (uint16_t)(69); + _curvea0[105] = _14535; + uint16_t _14536 = (uint16_t)(70); + _curvea0[106] = _14536; + uint16_t _14537 = (uint16_t)(70); + _curvea0[107] = _14537; + uint16_t _14538 = (uint16_t)(71); + _curvea0[108] = _14538; + uint16_t _14539 = (uint16_t)(71); + _curvea0[109] = _14539; + uint16_t _14540 = (uint16_t)(71); + _curvea0[110] = _14540; + uint16_t _14541 = (uint16_t)(72); + _curvea0[111] = _14541; + uint16_t _14542 = (uint16_t)(72); + _curvea0[112] = _14542; + uint16_t _14543 = (uint16_t)(73); + _curvea0[113] = _14543; + uint16_t _14544 = (uint16_t)(73); + _curvea0[114] = _14544; + uint16_t _14545 = (uint16_t)(74); + _curvea0[115] = _14545; + uint16_t _14546 = (uint16_t)(74); + _curvea0[116] = _14546; + uint16_t _14547 = (uint16_t)(74); + _curvea0[117] = _14547; + uint16_t _14548 = (uint16_t)(75); + _curvea0[118] = _14548; + uint16_t _14549 = (uint16_t)(75); + _curvea0[119] = _14549; + uint16_t _14550 = (uint16_t)(76); + _curvea0[120] = _14550; + uint16_t _14551 = (uint16_t)(76); + _curvea0[121] = _14551; + uint16_t _14552 = (uint16_t)(77); + _curvea0[122] = _14552; + uint16_t _14553 = (uint16_t)(77); + _curvea0[123] = _14553; + uint16_t _14554 = (uint16_t)(77); + _curvea0[124] = _14554; + uint16_t _14555 = (uint16_t)(78); + _curvea0[125] = _14555; + uint16_t _14556 = (uint16_t)(78); + _curvea0[126] = _14556; + uint16_t _14557 = (uint16_t)(79); + _curvea0[127] = _14557; + uint16_t _14558 = (uint16_t)(79); + _curvea0[128] = _14558; + uint16_t _14559 = (uint16_t)(79); + _curvea0[129] = _14559; + uint16_t _14560 = (uint16_t)(80); + _curvea0[130] = _14560; + uint16_t _14561 = (uint16_t)(80); + _curvea0[131] = _14561; + uint16_t _14562 = (uint16_t)(81); + _curvea0[132] = _14562; + uint16_t _14563 = (uint16_t)(81); + _curvea0[133] = _14563; + uint16_t _14564 = (uint16_t)(82); + _curvea0[134] = _14564; + uint16_t _14565 = (uint16_t)(82); + _curvea0[135] = _14565; + uint16_t _14566 = (uint16_t)(82); + _curvea0[136] = _14566; + uint16_t _14567 = (uint16_t)(83); + _curvea0[137] = _14567; + uint16_t _14568 = (uint16_t)(83); + _curvea0[138] = _14568; + uint16_t _14569 = (uint16_t)(84); + _curvea0[139] = _14569; + uint16_t _14570 = (uint16_t)(84); + _curvea0[140] = _14570; + uint16_t _14571 = (uint16_t)(84); + _curvea0[141] = _14571; + uint16_t _14572 = (uint16_t)(85); + _curvea0[142] = _14572; + uint16_t _14573 = (uint16_t)(85); + _curvea0[143] = _14573; + uint16_t _14574 = (uint16_t)(86); + _curvea0[144] = _14574; + uint16_t _14575 = (uint16_t)(86); + _curvea0[145] = _14575; + uint16_t _14576 = (uint16_t)(86); + _curvea0[146] = _14576; + uint16_t _14577 = (uint16_t)(87); + _curvea0[147] = _14577; + uint16_t _14578 = (uint16_t)(87); + _curvea0[148] = _14578; + uint16_t _14579 = (uint16_t)(88); + _curvea0[149] = _14579; + uint16_t _14580 = (uint16_t)(88); + _curvea0[150] = _14580; + uint16_t _14581 = (uint16_t)(88); + _curvea0[151] = _14581; + uint16_t _14582 = (uint16_t)(89); + _curvea0[152] = _14582; + uint16_t _14583 = (uint16_t)(89); + _curvea0[153] = _14583; + uint16_t _14584 = (uint16_t)(90); + _curvea0[154] = _14584; + uint16_t _14585 = (uint16_t)(90); + _curvea0[155] = _14585; + uint16_t _14586 = (uint16_t)(90); + _curvea0[156] = _14586; + uint16_t _14587 = (uint16_t)(91); + _curvea0[157] = _14587; + uint16_t _14588 = (uint16_t)(91); + _curvea0[158] = _14588; + uint16_t _14589 = (uint16_t)(92); + _curvea0[159] = _14589; + uint16_t _14590 = (uint16_t)(92); + _curvea0[160] = _14590; + uint16_t _14591 = (uint16_t)(92); + _curvea0[161] = _14591; + uint16_t _14592 = (uint16_t)(93); + _curvea0[162] = _14592; + uint16_t _14593 = (uint16_t)(93); + _curvea0[163] = _14593; + uint16_t _14594 = (uint16_t)(93); + _curvea0[164] = _14594; + uint16_t _14595 = (uint16_t)(94); + _curvea0[165] = _14595; + uint16_t _14596 = (uint16_t)(94); + _curvea0[166] = _14596; + uint16_t _14597 = (uint16_t)(95); + _curvea0[167] = _14597; + uint16_t _14598 = (uint16_t)(95); + _curvea0[168] = _14598; + uint16_t _14599 = (uint16_t)(95); + _curvea0[169] = _14599; + uint16_t _14600 = (uint16_t)(96); + _curvea0[170] = _14600; + uint16_t _14601 = (uint16_t)(96); + _curvea0[171] = _14601; + uint16_t _14602 = (uint16_t)(97); + _curvea0[172] = _14602; + uint16_t _14603 = (uint16_t)(97); + _curvea0[173] = _14603; + uint16_t _14604 = (uint16_t)(97); + _curvea0[174] = _14604; + uint16_t _14605 = (uint16_t)(98); + _curvea0[175] = _14605; + uint16_t _14606 = (uint16_t)(98); + _curvea0[176] = _14606; + uint16_t _14607 = (uint16_t)(99); + _curvea0[177] = _14607; + uint16_t _14608 = (uint16_t)(99); + _curvea0[178] = _14608; + uint16_t _14609 = (uint16_t)(99); + _curvea0[179] = _14609; + uint16_t _14610 = (uint16_t)(100); + _curvea0[180] = _14610; + uint16_t _14611 = (uint16_t)(100); + _curvea0[181] = _14611; + uint16_t _14612 = (uint16_t)(100); + _curvea0[182] = _14612; + uint16_t _14613 = (uint16_t)(101); + _curvea0[183] = _14613; + uint16_t _14614 = (uint16_t)(101); + _curvea0[184] = _14614; + uint16_t _14615 = (uint16_t)(102); + _curvea0[185] = _14615; + uint16_t _14616 = (uint16_t)(102); + _curvea0[186] = _14616; + uint16_t _14617 = (uint16_t)(102); + _curvea0[187] = _14617; + uint16_t _14618 = (uint16_t)(103); + _curvea0[188] = _14618; + uint16_t _14619 = (uint16_t)(103); + _curvea0[189] = _14619; + uint16_t _14620 = (uint16_t)(103); + _curvea0[190] = _14620; + uint16_t _14621 = (uint16_t)(104); + _curvea0[191] = _14621; + uint16_t _14622 = (uint16_t)(104); + _curvea0[192] = _14622; + uint16_t _14623 = (uint16_t)(105); + _curvea0[193] = _14623; + uint16_t _14624 = (uint16_t)(105); + _curvea0[194] = _14624; + uint16_t _14625 = (uint16_t)(105); + _curvea0[195] = _14625; + uint16_t _14626 = (uint16_t)(106); + _curvea0[196] = _14626; + uint16_t _14627 = (uint16_t)(106); + _curvea0[197] = _14627; + uint16_t _14628 = (uint16_t)(106); + _curvea0[198] = _14628; + uint16_t _14629 = (uint16_t)(107); + _curvea0[199] = _14629; + uint16_t _14630 = (uint16_t)(107); + _curvea0[200] = _14630; + uint16_t _14631 = (uint16_t)(108); + _curvea0[201] = _14631; + uint16_t _14632 = (uint16_t)(108); + _curvea0[202] = _14632; + uint16_t _14633 = (uint16_t)(108); + _curvea0[203] = _14633; + uint16_t _14634 = (uint16_t)(109); + _curvea0[204] = _14634; + uint16_t _14635 = (uint16_t)(109); + _curvea0[205] = _14635; + uint16_t _14636 = (uint16_t)(109); + _curvea0[206] = _14636; + uint16_t _14637 = (uint16_t)(110); + _curvea0[207] = _14637; + uint16_t _14638 = (uint16_t)(110); + _curvea0[208] = _14638; + uint16_t _14639 = (uint16_t)(111); + _curvea0[209] = _14639; + uint16_t _14640 = (uint16_t)(111); + _curvea0[210] = _14640; + uint16_t _14641 = (uint16_t)(111); + _curvea0[211] = _14641; + uint16_t _14642 = (uint16_t)(112); + _curvea0[212] = _14642; + uint16_t _14643 = (uint16_t)(112); + _curvea0[213] = _14643; + uint16_t _14644 = (uint16_t)(112); + _curvea0[214] = _14644; + uint16_t _14645 = (uint16_t)(113); + _curvea0[215] = _14645; + uint16_t _14646 = (uint16_t)(113); + _curvea0[216] = _14646; + uint16_t _14647 = (uint16_t)(113); + _curvea0[217] = _14647; + uint16_t _14648 = (uint16_t)(114); + _curvea0[218] = _14648; + uint16_t _14649 = (uint16_t)(114); + _curvea0[219] = _14649; + uint16_t _14650 = (uint16_t)(115); + _curvea0[220] = _14650; + uint16_t _14651 = (uint16_t)(115); + _curvea0[221] = _14651; + uint16_t _14652 = (uint16_t)(115); + _curvea0[222] = _14652; + uint16_t _14653 = (uint16_t)(116); + _curvea0[223] = _14653; + uint16_t _14654 = (uint16_t)(116); + _curvea0[224] = _14654; + uint16_t _14655 = (uint16_t)(116); + _curvea0[225] = _14655; + uint16_t _14656 = (uint16_t)(117); + _curvea0[226] = _14656; + uint16_t _14657 = (uint16_t)(117); + _curvea0[227] = _14657; + uint16_t _14658 = (uint16_t)(117); + _curvea0[228] = _14658; + uint16_t _14659 = (uint16_t)(118); + _curvea0[229] = _14659; + uint16_t _14660 = (uint16_t)(118); + _curvea0[230] = _14660; + uint16_t _14661 = (uint16_t)(119); + _curvea0[231] = _14661; + uint16_t _14662 = (uint16_t)(119); + _curvea0[232] = _14662; + uint16_t _14663 = (uint16_t)(119); + _curvea0[233] = _14663; + uint16_t _14664 = (uint16_t)(120); + _curvea0[234] = _14664; + uint16_t _14665 = (uint16_t)(120); + _curvea0[235] = _14665; + uint16_t _14666 = (uint16_t)(120); + _curvea0[236] = _14666; + uint16_t _14667 = (uint16_t)(121); + _curvea0[237] = _14667; + uint16_t _14668 = (uint16_t)(121); + _curvea0[238] = _14668; + uint16_t _14669 = (uint16_t)(121); + _curvea0[239] = _14669; + uint16_t _14670 = (uint16_t)(122); + _curvea0[240] = _14670; + uint16_t _14671 = (uint16_t)(122); + _curvea0[241] = _14671; + uint16_t _14672 = (uint16_t)(123); + _curvea0[242] = _14672; + uint16_t _14673 = (uint16_t)(123); + _curvea0[243] = _14673; + uint16_t _14674 = (uint16_t)(123); + _curvea0[244] = _14674; + uint16_t _14675 = (uint16_t)(124); + _curvea0[245] = _14675; + uint16_t _14676 = (uint16_t)(124); + _curvea0[246] = _14676; + uint16_t _14677 = (uint16_t)(124); + _curvea0[247] = _14677; + uint16_t _14678 = (uint16_t)(125); + _curvea0[248] = _14678; + uint16_t _14679 = (uint16_t)(125); + _curvea0[249] = _14679; + uint16_t _14680 = (uint16_t)(125); + _curvea0[250] = _14680; + uint16_t _14681 = (uint16_t)(126); + _curvea0[251] = _14681; + uint16_t _14682 = (uint16_t)(126); + _curvea0[252] = _14682; + uint16_t _14683 = (uint16_t)(126); + _curvea0[253] = _14683; + uint16_t _14684 = (uint16_t)(127); + _curvea0[254] = _14684; + uint16_t _14685 = (uint16_t)(127); + _curvea0[255] = _14685; + uint16_t _14686 = (uint16_t)(128); + _curvea0[256] = _14686; + uint16_t _14687 = (uint16_t)(128); + _curvea0[257] = _14687; + uint16_t _14688 = (uint16_t)(128); + _curvea0[258] = _14688; + uint16_t _14689 = (uint16_t)(129); + _curvea0[259] = _14689; + uint16_t _14690 = (uint16_t)(129); + _curvea0[260] = _14690; + uint16_t _14691 = (uint16_t)(129); + _curvea0[261] = _14691; + uint16_t _14692 = (uint16_t)(130); + _curvea0[262] = _14692; + uint16_t _14693 = (uint16_t)(130); + _curvea0[263] = _14693; + uint16_t _14694 = (uint16_t)(130); + _curvea0[264] = _14694; + uint16_t _14695 = (uint16_t)(131); + _curvea0[265] = _14695; + uint16_t _14696 = (uint16_t)(131); + _curvea0[266] = _14696; + uint16_t _14697 = (uint16_t)(131); + _curvea0[267] = _14697; + uint16_t _14698 = (uint16_t)(132); + _curvea0[268] = _14698; + uint16_t _14699 = (uint16_t)(132); + _curvea0[269] = _14699; + uint16_t _14700 = (uint16_t)(132); + _curvea0[270] = _14700; + uint16_t _14701 = (uint16_t)(133); + _curvea0[271] = _14701; + uint16_t _14702 = (uint16_t)(133); + _curvea0[272] = _14702; + uint16_t _14703 = (uint16_t)(133); + _curvea0[273] = _14703; + uint16_t _14704 = (uint16_t)(134); + _curvea0[274] = _14704; + uint16_t _14705 = (uint16_t)(134); + _curvea0[275] = _14705; + uint16_t _14706 = (uint16_t)(134); + _curvea0[276] = _14706; + uint16_t _14707 = (uint16_t)(135); + _curvea0[277] = _14707; + uint16_t _14708 = (uint16_t)(135); + _curvea0[278] = _14708; + uint16_t _14709 = (uint16_t)(135); + _curvea0[279] = _14709; + uint16_t _14710 = (uint16_t)(136); + _curvea0[280] = _14710; + uint16_t _14711 = (uint16_t)(136); + _curvea0[281] = _14711; + uint16_t _14712 = (uint16_t)(136); + _curvea0[282] = _14712; + uint16_t _14713 = (uint16_t)(137); + _curvea0[283] = _14713; + uint16_t _14714 = (uint16_t)(137); + _curvea0[284] = _14714; + uint16_t _14715 = (uint16_t)(137); + _curvea0[285] = _14715; + uint16_t _14716 = (uint16_t)(138); + _curvea0[286] = _14716; + uint16_t _14717 = (uint16_t)(138); + _curvea0[287] = _14717; + uint16_t _14718 = (uint16_t)(138); + _curvea0[288] = _14718; + uint16_t _14719 = (uint16_t)(139); + _curvea0[289] = _14719; + uint16_t _14720 = (uint16_t)(139); + _curvea0[290] = _14720; + uint16_t _14721 = (uint16_t)(139); + _curvea0[291] = _14721; + uint16_t _14722 = (uint16_t)(140); + _curvea0[292] = _14722; + uint16_t _14723 = (uint16_t)(140); + _curvea0[293] = _14723; + uint16_t _14724 = (uint16_t)(140); + _curvea0[294] = _14724; + uint16_t _14725 = (uint16_t)(141); + _curvea0[295] = _14725; + uint16_t _14726 = (uint16_t)(141); + _curvea0[296] = _14726; + uint16_t _14727 = (uint16_t)(141); + _curvea0[297] = _14727; + uint16_t _14728 = (uint16_t)(141); + _curvea0[298] = _14728; + uint16_t _14729 = (uint16_t)(142); + _curvea0[299] = _14729; + uint16_t _14730 = (uint16_t)(142); + _curvea0[300] = _14730; + uint16_t _14731 = (uint16_t)(142); + _curvea0[301] = _14731; + uint16_t _14732 = (uint16_t)(143); + _curvea0[302] = _14732; + uint16_t _14733 = (uint16_t)(143); + _curvea0[303] = _14733; + uint16_t _14734 = (uint16_t)(143); + _curvea0[304] = _14734; + uint16_t _14735 = (uint16_t)(144); + _curvea0[305] = _14735; + uint16_t _14736 = (uint16_t)(144); + _curvea0[306] = _14736; + uint16_t _14737 = (uint16_t)(144); + _curvea0[307] = _14737; + uint16_t _14738 = (uint16_t)(145); + _curvea0[308] = _14738; + uint16_t _14739 = (uint16_t)(145); + _curvea0[309] = _14739; + uint16_t _14740 = (uint16_t)(145); + _curvea0[310] = _14740; + uint16_t _14741 = (uint16_t)(145); + _curvea0[311] = _14741; + uint16_t _14742 = (uint16_t)(146); + _curvea0[312] = _14742; + uint16_t _14743 = (uint16_t)(146); + _curvea0[313] = _14743; + uint16_t _14744 = (uint16_t)(146); + _curvea0[314] = _14744; + uint16_t _14745 = (uint16_t)(147); + _curvea0[315] = _14745; + uint16_t _14746 = (uint16_t)(147); + _curvea0[316] = _14746; + uint16_t _14747 = (uint16_t)(147); + _curvea0[317] = _14747; + uint16_t _14748 = (uint16_t)(148); + _curvea0[318] = _14748; + uint16_t _14749 = (uint16_t)(148); + _curvea0[319] = _14749; + uint16_t _14750 = (uint16_t)(148); + _curvea0[320] = _14750; + uint16_t _14751 = (uint16_t)(148); + _curvea0[321] = _14751; + uint16_t _14752 = (uint16_t)(149); + _curvea0[322] = _14752; + uint16_t _14753 = (uint16_t)(149); + _curvea0[323] = _14753; + uint16_t _14754 = (uint16_t)(149); + _curvea0[324] = _14754; + uint16_t _14755 = (uint16_t)(150); + _curvea0[325] = _14755; + uint16_t _14756 = (uint16_t)(150); + _curvea0[326] = _14756; + uint16_t _14757 = (uint16_t)(150); + _curvea0[327] = _14757; + uint16_t _14758 = (uint16_t)(150); + _curvea0[328] = _14758; + uint16_t _14759 = (uint16_t)(151); + _curvea0[329] = _14759; + uint16_t _14760 = (uint16_t)(151); + _curvea0[330] = _14760; + uint16_t _14761 = (uint16_t)(151); + _curvea0[331] = _14761; + uint16_t _14762 = (uint16_t)(152); + _curvea0[332] = _14762; + uint16_t _14763 = (uint16_t)(152); + _curvea0[333] = _14763; + uint16_t _14764 = (uint16_t)(152); + _curvea0[334] = _14764; + uint16_t _14765 = (uint16_t)(152); + _curvea0[335] = _14765; + uint16_t _14766 = (uint16_t)(153); + _curvea0[336] = _14766; + uint16_t _14767 = (uint16_t)(153); + _curvea0[337] = _14767; + uint16_t _14768 = (uint16_t)(153); + _curvea0[338] = _14768; + uint16_t _14769 = (uint16_t)(154); + _curvea0[339] = _14769; + uint16_t _14770 = (uint16_t)(154); + _curvea0[340] = _14770; + uint16_t _14771 = (uint16_t)(154); + _curvea0[341] = _14771; + uint16_t _14772 = (uint16_t)(154); + _curvea0[342] = _14772; + uint16_t _14773 = (uint16_t)(155); + _curvea0[343] = _14773; + uint16_t _14774 = (uint16_t)(155); + _curvea0[344] = _14774; + uint16_t _14775 = (uint16_t)(155); + _curvea0[345] = _14775; + uint16_t _14776 = (uint16_t)(156); + _curvea0[346] = _14776; + uint16_t _14777 = (uint16_t)(156); + _curvea0[347] = _14777; + uint16_t _14778 = (uint16_t)(156); + _curvea0[348] = _14778; + uint16_t _14779 = (uint16_t)(156); + _curvea0[349] = _14779; + uint16_t _14780 = (uint16_t)(157); + _curvea0[350] = _14780; + uint16_t _14781 = (uint16_t)(157); + _curvea0[351] = _14781; + uint16_t _14782 = (uint16_t)(157); + _curvea0[352] = _14782; + uint16_t _14783 = (uint16_t)(157); + _curvea0[353] = _14783; + uint16_t _14784 = (uint16_t)(158); + _curvea0[354] = _14784; + uint16_t _14785 = (uint16_t)(158); + _curvea0[355] = _14785; + uint16_t _14786 = (uint16_t)(158); + _curvea0[356] = _14786; + uint16_t _14787 = (uint16_t)(159); + _curvea0[357] = _14787; + uint16_t _14788 = (uint16_t)(159); + _curvea0[358] = _14788; + uint16_t _14789 = (uint16_t)(159); + _curvea0[359] = _14789; + uint16_t _14790 = (uint16_t)(159); + _curvea0[360] = _14790; + uint16_t _14791 = (uint16_t)(160); + _curvea0[361] = _14791; + uint16_t _14792 = (uint16_t)(160); + _curvea0[362] = _14792; + uint16_t _14793 = (uint16_t)(160); + _curvea0[363] = _14793; + uint16_t _14794 = (uint16_t)(160); + _curvea0[364] = _14794; + uint16_t _14795 = (uint16_t)(161); + _curvea0[365] = _14795; + uint16_t _14796 = (uint16_t)(161); + _curvea0[366] = _14796; + uint16_t _14797 = (uint16_t)(161); + _curvea0[367] = _14797; + uint16_t _14798 = (uint16_t)(161); + _curvea0[368] = _14798; + uint16_t _14799 = (uint16_t)(162); + _curvea0[369] = _14799; + uint16_t _14800 = (uint16_t)(162); + _curvea0[370] = _14800; + uint16_t _14801 = (uint16_t)(162); + _curvea0[371] = _14801; + uint16_t _14802 = (uint16_t)(162); + _curvea0[372] = _14802; + uint16_t _14803 = (uint16_t)(163); + _curvea0[373] = _14803; + uint16_t _14804 = (uint16_t)(163); + _curvea0[374] = _14804; + uint16_t _14805 = (uint16_t)(163); + _curvea0[375] = _14805; + uint16_t _14806 = (uint16_t)(163); + _curvea0[376] = _14806; + uint16_t _14807 = (uint16_t)(164); + _curvea0[377] = _14807; + uint16_t _14808 = (uint16_t)(164); + _curvea0[378] = _14808; + uint16_t _14809 = (uint16_t)(164); + _curvea0[379] = _14809; + uint16_t _14810 = (uint16_t)(164); + _curvea0[380] = _14810; + uint16_t _14811 = (uint16_t)(165); + _curvea0[381] = _14811; + uint16_t _14812 = (uint16_t)(165); + _curvea0[382] = _14812; + uint16_t _14813 = (uint16_t)(165); + _curvea0[383] = _14813; + uint16_t _14814 = (uint16_t)(166); + _curvea0[384] = _14814; + uint16_t _14815 = (uint16_t)(166); + _curvea0[385] = _14815; + uint16_t _14816 = (uint16_t)(166); + _curvea0[386] = _14816; + uint16_t _14817 = (uint16_t)(166); + _curvea0[387] = _14817; + uint16_t _14818 = (uint16_t)(167); + _curvea0[388] = _14818; + uint16_t _14819 = (uint16_t)(167); + _curvea0[389] = _14819; + uint16_t _14820 = (uint16_t)(167); + _curvea0[390] = _14820; + uint16_t _14821 = (uint16_t)(167); + _curvea0[391] = _14821; + uint16_t _14822 = (uint16_t)(167); + _curvea0[392] = _14822; + uint16_t _14823 = (uint16_t)(168); + _curvea0[393] = _14823; + uint16_t _14824 = (uint16_t)(168); + _curvea0[394] = _14824; + uint16_t _14825 = (uint16_t)(168); + _curvea0[395] = _14825; + uint16_t _14826 = (uint16_t)(168); + _curvea0[396] = _14826; + uint16_t _14827 = (uint16_t)(169); + _curvea0[397] = _14827; + uint16_t _14828 = (uint16_t)(169); + _curvea0[398] = _14828; + uint16_t _14829 = (uint16_t)(169); + _curvea0[399] = _14829; + uint16_t _14830 = (uint16_t)(169); + _curvea0[400] = _14830; + uint16_t _14831 = (uint16_t)(170); + _curvea0[401] = _14831; + uint16_t _14832 = (uint16_t)(170); + _curvea0[402] = _14832; + uint16_t _14833 = (uint16_t)(170); + _curvea0[403] = _14833; + uint16_t _14834 = (uint16_t)(170); + _curvea0[404] = _14834; + uint16_t _14835 = (uint16_t)(171); + _curvea0[405] = _14835; + uint16_t _14836 = (uint16_t)(171); + _curvea0[406] = _14836; + uint16_t _14837 = (uint16_t)(171); + _curvea0[407] = _14837; + uint16_t _14838 = (uint16_t)(171); + _curvea0[408] = _14838; + uint16_t _14839 = (uint16_t)(172); + _curvea0[409] = _14839; + uint16_t _14840 = (uint16_t)(172); + _curvea0[410] = _14840; + uint16_t _14841 = (uint16_t)(172); + _curvea0[411] = _14841; + uint16_t _14842 = (uint16_t)(172); + _curvea0[412] = _14842; + uint16_t _14843 = (uint16_t)(173); + _curvea0[413] = _14843; + uint16_t _14844 = (uint16_t)(173); + _curvea0[414] = _14844; + uint16_t _14845 = (uint16_t)(173); + _curvea0[415] = _14845; + uint16_t _14846 = (uint16_t)(173); + _curvea0[416] = _14846; + uint16_t _14847 = (uint16_t)(173); + _curvea0[417] = _14847; + uint16_t _14848 = (uint16_t)(174); + _curvea0[418] = _14848; + uint16_t _14849 = (uint16_t)(174); + _curvea0[419] = _14849; + uint16_t _14850 = (uint16_t)(174); + _curvea0[420] = _14850; + uint16_t _14851 = (uint16_t)(174); + _curvea0[421] = _14851; + uint16_t _14852 = (uint16_t)(175); + _curvea0[422] = _14852; + uint16_t _14853 = (uint16_t)(175); + _curvea0[423] = _14853; + uint16_t _14854 = (uint16_t)(175); + _curvea0[424] = _14854; + uint16_t _14855 = (uint16_t)(175); + _curvea0[425] = _14855; + uint16_t _14856 = (uint16_t)(176); + _curvea0[426] = _14856; + uint16_t _14857 = (uint16_t)(176); + _curvea0[427] = _14857; + uint16_t _14858 = (uint16_t)(176); + _curvea0[428] = _14858; + uint16_t _14859 = (uint16_t)(176); + _curvea0[429] = _14859; + uint16_t _14860 = (uint16_t)(176); + _curvea0[430] = _14860; + uint16_t _14861 = (uint16_t)(177); + _curvea0[431] = _14861; + uint16_t _14862 = (uint16_t)(177); + _curvea0[432] = _14862; + uint16_t _14863 = (uint16_t)(177); + _curvea0[433] = _14863; + uint16_t _14864 = (uint16_t)(177); + _curvea0[434] = _14864; + uint16_t _14865 = (uint16_t)(178); + _curvea0[435] = _14865; + uint16_t _14866 = (uint16_t)(178); + _curvea0[436] = _14866; + uint16_t _14867 = (uint16_t)(178); + _curvea0[437] = _14867; + uint16_t _14868 = (uint16_t)(178); + _curvea0[438] = _14868; + uint16_t _14869 = (uint16_t)(178); + _curvea0[439] = _14869; + uint16_t _14870 = (uint16_t)(179); + _curvea0[440] = _14870; + uint16_t _14871 = (uint16_t)(179); + _curvea0[441] = _14871; + uint16_t _14872 = (uint16_t)(179); + _curvea0[442] = _14872; + uint16_t _14873 = (uint16_t)(179); + _curvea0[443] = _14873; + uint16_t _14874 = (uint16_t)(180); + _curvea0[444] = _14874; + uint16_t _14875 = (uint16_t)(180); + _curvea0[445] = _14875; + uint16_t _14876 = (uint16_t)(180); + _curvea0[446] = _14876; + uint16_t _14877 = (uint16_t)(180); + _curvea0[447] = _14877; + uint16_t _14878 = (uint16_t)(180); + _curvea0[448] = _14878; + uint16_t _14879 = (uint16_t)(181); + _curvea0[449] = _14879; + uint16_t _14880 = (uint16_t)(181); + _curvea0[450] = _14880; + uint16_t _14881 = (uint16_t)(181); + _curvea0[451] = _14881; + uint16_t _14882 = (uint16_t)(181); + _curvea0[452] = _14882; + uint16_t _14883 = (uint16_t)(181); + _curvea0[453] = _14883; + uint16_t _14884 = (uint16_t)(182); + _curvea0[454] = _14884; + uint16_t _14885 = (uint16_t)(182); + _curvea0[455] = _14885; + uint16_t _14886 = (uint16_t)(182); + _curvea0[456] = _14886; + uint16_t _14887 = (uint16_t)(182); + _curvea0[457] = _14887; + uint16_t _14888 = (uint16_t)(183); + _curvea0[458] = _14888; + uint16_t _14889 = (uint16_t)(183); + _curvea0[459] = _14889; + uint16_t _14890 = (uint16_t)(183); + _curvea0[460] = _14890; + uint16_t _14891 = (uint16_t)(183); + _curvea0[461] = _14891; + uint16_t _14892 = (uint16_t)(183); + _curvea0[462] = _14892; + uint16_t _14893 = (uint16_t)(184); + _curvea0[463] = _14893; + uint16_t _14894 = (uint16_t)(184); + _curvea0[464] = _14894; + uint16_t _14895 = (uint16_t)(184); + _curvea0[465] = _14895; + uint16_t _14896 = (uint16_t)(184); + _curvea0[466] = _14896; + uint16_t _14897 = (uint16_t)(184); + _curvea0[467] = _14897; + uint16_t _14898 = (uint16_t)(185); + _curvea0[468] = _14898; + uint16_t _14899 = (uint16_t)(185); + _curvea0[469] = _14899; + uint16_t _14900 = (uint16_t)(185); + _curvea0[470] = _14900; + uint16_t _14901 = (uint16_t)(185); + _curvea0[471] = _14901; + uint16_t _14902 = (uint16_t)(185); + _curvea0[472] = _14902; + uint16_t _14903 = (uint16_t)(186); + _curvea0[473] = _14903; + uint16_t _14904 = (uint16_t)(186); + _curvea0[474] = _14904; + uint16_t _14905 = (uint16_t)(186); + _curvea0[475] = _14905; + uint16_t _14906 = (uint16_t)(186); + _curvea0[476] = _14906; + uint16_t _14907 = (uint16_t)(187); + _curvea0[477] = _14907; + uint16_t _14908 = (uint16_t)(187); + _curvea0[478] = _14908; + uint16_t _14909 = (uint16_t)(187); + _curvea0[479] = _14909; + uint16_t _14910 = (uint16_t)(187); + _curvea0[480] = _14910; + uint16_t _14911 = (uint16_t)(187); + _curvea0[481] = _14911; + uint16_t _14912 = (uint16_t)(188); + _curvea0[482] = _14912; + uint16_t _14913 = (uint16_t)(188); + _curvea0[483] = _14913; + uint16_t _14914 = (uint16_t)(188); + _curvea0[484] = _14914; + uint16_t _14915 = (uint16_t)(188); + _curvea0[485] = _14915; + uint16_t _14916 = (uint16_t)(188); + _curvea0[486] = _14916; + uint16_t _14917 = (uint16_t)(189); + _curvea0[487] = _14917; + uint16_t _14918 = (uint16_t)(189); + _curvea0[488] = _14918; + uint16_t _14919 = (uint16_t)(189); + _curvea0[489] = _14919; + uint16_t _14920 = (uint16_t)(189); + _curvea0[490] = _14920; + uint16_t _14921 = (uint16_t)(189); + _curvea0[491] = _14921; + uint16_t _14922 = (uint16_t)(190); + _curvea0[492] = _14922; + uint16_t _14923 = (uint16_t)(190); + _curvea0[493] = _14923; + uint16_t _14924 = (uint16_t)(190); + _curvea0[494] = _14924; + uint16_t _14925 = (uint16_t)(190); + _curvea0[495] = _14925; + uint16_t _14926 = (uint16_t)(190); + _curvea0[496] = _14926; + uint16_t _14927 = (uint16_t)(190); + _curvea0[497] = _14927; + uint16_t _14928 = (uint16_t)(191); + _curvea0[498] = _14928; + uint16_t _14929 = (uint16_t)(191); + _curvea0[499] = _14929; + uint16_t _14930 = (uint16_t)(191); + _curvea0[500] = _14930; + uint16_t _14931 = (uint16_t)(191); + _curvea0[501] = _14931; + uint16_t _14932 = (uint16_t)(191); + _curvea0[502] = _14932; + uint16_t _14933 = (uint16_t)(192); + _curvea0[503] = _14933; + uint16_t _14934 = (uint16_t)(192); + _curvea0[504] = _14934; + uint16_t _14935 = (uint16_t)(192); + _curvea0[505] = _14935; + uint16_t _14936 = (uint16_t)(192); + _curvea0[506] = _14936; + uint16_t _14937 = (uint16_t)(192); + _curvea0[507] = _14937; + uint16_t _14938 = (uint16_t)(193); + _curvea0[508] = _14938; + uint16_t _14939 = (uint16_t)(193); + _curvea0[509] = _14939; + uint16_t _14940 = (uint16_t)(193); + _curvea0[510] = _14940; + uint16_t _14941 = (uint16_t)(193); + _curvea0[511] = _14941; + uint16_t _14942 = (uint16_t)(193); + _curvea0[512] = _14942; + uint16_t _14943 = (uint16_t)(194); + _curvea0[513] = _14943; + uint16_t _14944 = (uint16_t)(194); + _curvea0[514] = _14944; + uint16_t _14945 = (uint16_t)(194); + _curvea0[515] = _14945; + uint16_t _14946 = (uint16_t)(194); + _curvea0[516] = _14946; + uint16_t _14947 = (uint16_t)(194); + _curvea0[517] = _14947; + uint16_t _14948 = (uint16_t)(195); + _curvea0[518] = _14948; + uint16_t _14949 = (uint16_t)(195); + _curvea0[519] = _14949; + uint16_t _14950 = (uint16_t)(195); + _curvea0[520] = _14950; + uint16_t _14951 = (uint16_t)(195); + _curvea0[521] = _14951; + uint16_t _14952 = (uint16_t)(195); + _curvea0[522] = _14952; + uint16_t _14953 = (uint16_t)(195); + _curvea0[523] = _14953; + uint16_t _14954 = (uint16_t)(196); + _curvea0[524] = _14954; + uint16_t _14955 = (uint16_t)(196); + _curvea0[525] = _14955; + uint16_t _14956 = (uint16_t)(196); + _curvea0[526] = _14956; + uint16_t _14957 = (uint16_t)(196); + _curvea0[527] = _14957; + uint16_t _14958 = (uint16_t)(196); + _curvea0[528] = _14958; + uint16_t _14959 = (uint16_t)(197); + _curvea0[529] = _14959; + uint16_t _14960 = (uint16_t)(197); + _curvea0[530] = _14960; + uint16_t _14961 = (uint16_t)(197); + _curvea0[531] = _14961; + uint16_t _14962 = (uint16_t)(197); + _curvea0[532] = _14962; + uint16_t _14963 = (uint16_t)(197); + _curvea0[533] = _14963; + uint16_t _14964 = (uint16_t)(197); + _curvea0[534] = _14964; + uint16_t _14965 = (uint16_t)(198); + _curvea0[535] = _14965; + uint16_t _14966 = (uint16_t)(198); + _curvea0[536] = _14966; + uint16_t _14967 = (uint16_t)(198); + _curvea0[537] = _14967; + uint16_t _14968 = (uint16_t)(198); + _curvea0[538] = _14968; + uint16_t _14969 = (uint16_t)(198); + _curvea0[539] = _14969; + uint16_t _14970 = (uint16_t)(199); + _curvea0[540] = _14970; + uint16_t _14971 = (uint16_t)(199); + _curvea0[541] = _14971; + uint16_t _14972 = (uint16_t)(199); + _curvea0[542] = _14972; + uint16_t _14973 = (uint16_t)(199); + _curvea0[543] = _14973; + uint16_t _14974 = (uint16_t)(199); + _curvea0[544] = _14974; + uint16_t _14975 = (uint16_t)(199); + _curvea0[545] = _14975; + uint16_t _14976 = (uint16_t)(200); + _curvea0[546] = _14976; + uint16_t _14977 = (uint16_t)(200); + _curvea0[547] = _14977; + uint16_t _14978 = (uint16_t)(200); + _curvea0[548] = _14978; + uint16_t _14979 = (uint16_t)(200); + _curvea0[549] = _14979; + uint16_t _14980 = (uint16_t)(200); + _curvea0[550] = _14980; + uint16_t _14981 = (uint16_t)(200); + _curvea0[551] = _14981; + uint16_t _14982 = (uint16_t)(201); + _curvea0[552] = _14982; + uint16_t _14983 = (uint16_t)(201); + _curvea0[553] = _14983; + uint16_t _14984 = (uint16_t)(201); + _curvea0[554] = _14984; + uint16_t _14985 = (uint16_t)(201); + _curvea0[555] = _14985; + uint16_t _14986 = (uint16_t)(201); + _curvea0[556] = _14986; + uint16_t _14987 = (uint16_t)(202); + _curvea0[557] = _14987; + uint16_t _14988 = (uint16_t)(202); + _curvea0[558] = _14988; + uint16_t _14989 = (uint16_t)(202); + _curvea0[559] = _14989; + uint16_t _14990 = (uint16_t)(202); + _curvea0[560] = _14990; + uint16_t _14991 = (uint16_t)(202); + _curvea0[561] = _14991; + uint16_t _14992 = (uint16_t)(202); + _curvea0[562] = _14992; + uint16_t _14993 = (uint16_t)(203); + _curvea0[563] = _14993; + uint16_t _14994 = (uint16_t)(203); + _curvea0[564] = _14994; + uint16_t _14995 = (uint16_t)(203); + _curvea0[565] = _14995; + uint16_t _14996 = (uint16_t)(203); + _curvea0[566] = _14996; + uint16_t _14997 = (uint16_t)(203); + _curvea0[567] = _14997; + uint16_t _14998 = (uint16_t)(203); + _curvea0[568] = _14998; + uint16_t _14999 = (uint16_t)(204); + _curvea0[569] = _14999; + uint16_t _15000 = (uint16_t)(204); + _curvea0[570] = _15000; + uint16_t _15001 = (uint16_t)(204); + _curvea0[571] = _15001; + uint16_t _15002 = (uint16_t)(204); + _curvea0[572] = _15002; + uint16_t _15003 = (uint16_t)(204); + _curvea0[573] = _15003; + uint16_t _15004 = (uint16_t)(204); + _curvea0[574] = _15004; + uint16_t _15005 = (uint16_t)(205); + _curvea0[575] = _15005; + uint16_t _15006 = (uint16_t)(205); + _curvea0[576] = _15006; + uint16_t _15007 = (uint16_t)(205); + _curvea0[577] = _15007; + uint16_t _15008 = (uint16_t)(205); + _curvea0[578] = _15008; + uint16_t _15009 = (uint16_t)(205); + _curvea0[579] = _15009; + uint16_t _15010 = (uint16_t)(205); + _curvea0[580] = _15010; + uint16_t _15011 = (uint16_t)(206); + _curvea0[581] = _15011; + uint16_t _15012 = (uint16_t)(206); + _curvea0[582] = _15012; + uint16_t _15013 = (uint16_t)(206); + _curvea0[583] = _15013; + uint16_t _15014 = (uint16_t)(206); + _curvea0[584] = _15014; + uint16_t _15015 = (uint16_t)(206); + _curvea0[585] = _15015; + uint16_t _15016 = (uint16_t)(206); + _curvea0[586] = _15016; + uint16_t _15017 = (uint16_t)(207); + _curvea0[587] = _15017; + uint16_t _15018 = (uint16_t)(207); + _curvea0[588] = _15018; + uint16_t _15019 = (uint16_t)(207); + _curvea0[589] = _15019; + uint16_t _15020 = (uint16_t)(207); + _curvea0[590] = _15020; + uint16_t _15021 = (uint16_t)(207); + _curvea0[591] = _15021; + uint16_t _15022 = (uint16_t)(207); + _curvea0[592] = _15022; + uint16_t _15023 = (uint16_t)(208); + _curvea0[593] = _15023; + uint16_t _15024 = (uint16_t)(208); + _curvea0[594] = _15024; + uint16_t _15025 = (uint16_t)(208); + _curvea0[595] = _15025; + uint16_t _15026 = (uint16_t)(208); + _curvea0[596] = _15026; + uint16_t _15027 = (uint16_t)(208); + _curvea0[597] = _15027; + uint16_t _15028 = (uint16_t)(208); + _curvea0[598] = _15028; + uint16_t _15029 = (uint16_t)(209); + _curvea0[599] = _15029; + uint16_t _15030 = (uint16_t)(209); + _curvea0[600] = _15030; + uint16_t _15031 = (uint16_t)(209); + _curvea0[601] = _15031; + uint16_t _15032 = (uint16_t)(209); + _curvea0[602] = _15032; + uint16_t _15033 = (uint16_t)(209); + _curvea0[603] = _15033; + uint16_t _15034 = (uint16_t)(209); + _curvea0[604] = _15034; + uint16_t _15035 = (uint16_t)(209); + _curvea0[605] = _15035; + uint16_t _15036 = (uint16_t)(210); + _curvea0[606] = _15036; + uint16_t _15037 = (uint16_t)(210); + _curvea0[607] = _15037; + uint16_t _15038 = (uint16_t)(210); + _curvea0[608] = _15038; + uint16_t _15039 = (uint16_t)(210); + _curvea0[609] = _15039; + uint16_t _15040 = (uint16_t)(210); + _curvea0[610] = _15040; + uint16_t _15041 = (uint16_t)(210); + _curvea0[611] = _15041; + uint16_t _15042 = (uint16_t)(211); + _curvea0[612] = _15042; + uint16_t _15043 = (uint16_t)(211); + _curvea0[613] = _15043; + uint16_t _15044 = (uint16_t)(211); + _curvea0[614] = _15044; + uint16_t _15045 = (uint16_t)(211); + _curvea0[615] = _15045; + uint16_t _15046 = (uint16_t)(211); + _curvea0[616] = _15046; + uint16_t _15047 = (uint16_t)(211); + _curvea0[617] = _15047; + uint16_t _15048 = (uint16_t)(211); + _curvea0[618] = _15048; + uint16_t _15049 = (uint16_t)(212); + _curvea0[619] = _15049; + uint16_t _15050 = (uint16_t)(212); + _curvea0[620] = _15050; + uint16_t _15051 = (uint16_t)(212); + _curvea0[621] = _15051; + uint16_t _15052 = (uint16_t)(212); + _curvea0[622] = _15052; + uint16_t _15053 = (uint16_t)(212); + _curvea0[623] = _15053; + uint16_t _15054 = (uint16_t)(212); + _curvea0[624] = _15054; + uint16_t _15055 = (uint16_t)(213); + _curvea0[625] = _15055; + uint16_t _15056 = (uint16_t)(213); + _curvea0[626] = _15056; + uint16_t _15057 = (uint16_t)(213); + _curvea0[627] = _15057; + uint16_t _15058 = (uint16_t)(213); + _curvea0[628] = _15058; + uint16_t _15059 = (uint16_t)(213); + _curvea0[629] = _15059; + uint16_t _15060 = (uint16_t)(213); + _curvea0[630] = _15060; + uint16_t _15061 = (uint16_t)(213); + _curvea0[631] = _15061; + uint16_t _15062 = (uint16_t)(214); + _curvea0[632] = _15062; + uint16_t _15063 = (uint16_t)(214); + _curvea0[633] = _15063; + uint16_t _15064 = (uint16_t)(214); + _curvea0[634] = _15064; + uint16_t _15065 = (uint16_t)(214); + _curvea0[635] = _15065; + uint16_t _15066 = (uint16_t)(214); + _curvea0[636] = _15066; + uint16_t _15067 = (uint16_t)(214); + _curvea0[637] = _15067; + uint16_t _15068 = (uint16_t)(214); + _curvea0[638] = _15068; + uint16_t _15069 = (uint16_t)(215); + _curvea0[639] = _15069; + uint16_t _15070 = (uint16_t)(215); + _curvea0[640] = _15070; + uint16_t _15071 = (uint16_t)(215); + _curvea0[641] = _15071; + uint16_t _15072 = (uint16_t)(215); + _curvea0[642] = _15072; + uint16_t _15073 = (uint16_t)(215); + _curvea0[643] = _15073; + uint16_t _15074 = (uint16_t)(215); + _curvea0[644] = _15074; + uint16_t _15075 = (uint16_t)(216); + _curvea0[645] = _15075; + uint16_t _15076 = (uint16_t)(216); + _curvea0[646] = _15076; + uint16_t _15077 = (uint16_t)(216); + _curvea0[647] = _15077; + uint16_t _15078 = (uint16_t)(216); + _curvea0[648] = _15078; + uint16_t _15079 = (uint16_t)(216); + _curvea0[649] = _15079; + uint16_t _15080 = (uint16_t)(216); + _curvea0[650] = _15080; + uint16_t _15081 = (uint16_t)(216); + _curvea0[651] = _15081; + uint16_t _15082 = (uint16_t)(217); + _curvea0[652] = _15082; + uint16_t _15083 = (uint16_t)(217); + _curvea0[653] = _15083; + uint16_t _15084 = (uint16_t)(217); + _curvea0[654] = _15084; + uint16_t _15085 = (uint16_t)(217); + _curvea0[655] = _15085; + uint16_t _15086 = (uint16_t)(217); + _curvea0[656] = _15086; + uint16_t _15087 = (uint16_t)(217); + _curvea0[657] = _15087; + uint16_t _15088 = (uint16_t)(217); + _curvea0[658] = _15088; + uint16_t _15089 = (uint16_t)(218); + _curvea0[659] = _15089; + uint16_t _15090 = (uint16_t)(218); + _curvea0[660] = _15090; + uint16_t _15091 = (uint16_t)(218); + _curvea0[661] = _15091; + uint16_t _15092 = (uint16_t)(218); + _curvea0[662] = _15092; + uint16_t _15093 = (uint16_t)(218); + _curvea0[663] = _15093; + uint16_t _15094 = (uint16_t)(218); + _curvea0[664] = _15094; + uint16_t _15095 = (uint16_t)(218); + _curvea0[665] = _15095; + uint16_t _15096 = (uint16_t)(219); + _curvea0[666] = _15096; + uint16_t _15097 = (uint16_t)(219); + _curvea0[667] = _15097; + uint16_t _15098 = (uint16_t)(219); + _curvea0[668] = _15098; + uint16_t _15099 = (uint16_t)(219); + _curvea0[669] = _15099; + uint16_t _15100 = (uint16_t)(219); + _curvea0[670] = _15100; + uint16_t _15101 = (uint16_t)(219); + _curvea0[671] = _15101; + uint16_t _15102 = (uint16_t)(219); + _curvea0[672] = _15102; + uint16_t _15103 = (uint16_t)(220); + _curvea0[673] = _15103; + uint16_t _15104 = (uint16_t)(220); + _curvea0[674] = _15104; + uint16_t _15105 = (uint16_t)(220); + _curvea0[675] = _15105; + uint16_t _15106 = (uint16_t)(220); + _curvea0[676] = _15106; + uint16_t _15107 = (uint16_t)(220); + _curvea0[677] = _15107; + uint16_t _15108 = (uint16_t)(220); + _curvea0[678] = _15108; + uint16_t _15109 = (uint16_t)(220); + _curvea0[679] = _15109; + uint16_t _15110 = (uint16_t)(220); + _curvea0[680] = _15110; + uint16_t _15111 = (uint16_t)(221); + _curvea0[681] = _15111; + uint16_t _15112 = (uint16_t)(221); + _curvea0[682] = _15112; + uint16_t _15113 = (uint16_t)(221); + _curvea0[683] = _15113; + uint16_t _15114 = (uint16_t)(221); + _curvea0[684] = _15114; + uint16_t _15115 = (uint16_t)(221); + _curvea0[685] = _15115; + uint16_t _15116 = (uint16_t)(221); + _curvea0[686] = _15116; + uint16_t _15117 = (uint16_t)(221); + _curvea0[687] = _15117; + uint16_t _15118 = (uint16_t)(222); + _curvea0[688] = _15118; + uint16_t _15119 = (uint16_t)(222); + _curvea0[689] = _15119; + uint16_t _15120 = (uint16_t)(222); + _curvea0[690] = _15120; + uint16_t _15121 = (uint16_t)(222); + _curvea0[691] = _15121; + uint16_t _15122 = (uint16_t)(222); + _curvea0[692] = _15122; + uint16_t _15123 = (uint16_t)(222); + _curvea0[693] = _15123; + uint16_t _15124 = (uint16_t)(222); + _curvea0[694] = _15124; + uint16_t _15125 = (uint16_t)(223); + _curvea0[695] = _15125; + uint16_t _15126 = (uint16_t)(223); + _curvea0[696] = _15126; + uint16_t _15127 = (uint16_t)(223); + _curvea0[697] = _15127; + uint16_t _15128 = (uint16_t)(223); + _curvea0[698] = _15128; + uint16_t _15129 = (uint16_t)(223); + _curvea0[699] = _15129; + uint16_t _15130 = (uint16_t)(223); + _curvea0[700] = _15130; + uint16_t _15131 = (uint16_t)(223); + _curvea0[701] = _15131; + uint16_t _15132 = (uint16_t)(223); + _curvea0[702] = _15132; + uint16_t _15133 = (uint16_t)(224); + _curvea0[703] = _15133; + uint16_t _15134 = (uint16_t)(224); + _curvea0[704] = _15134; + uint16_t _15135 = (uint16_t)(224); + _curvea0[705] = _15135; + uint16_t _15136 = (uint16_t)(224); + _curvea0[706] = _15136; + uint16_t _15137 = (uint16_t)(224); + _curvea0[707] = _15137; + uint16_t _15138 = (uint16_t)(224); + _curvea0[708] = _15138; + uint16_t _15139 = (uint16_t)(224); + _curvea0[709] = _15139; + uint16_t _15140 = (uint16_t)(224); + _curvea0[710] = _15140; + uint16_t _15141 = (uint16_t)(225); + _curvea0[711] = _15141; + uint16_t _15142 = (uint16_t)(225); + _curvea0[712] = _15142; + uint16_t _15143 = (uint16_t)(225); + _curvea0[713] = _15143; + uint16_t _15144 = (uint16_t)(225); + _curvea0[714] = _15144; + uint16_t _15145 = (uint16_t)(225); + _curvea0[715] = _15145; + uint16_t _15146 = (uint16_t)(225); + _curvea0[716] = _15146; + uint16_t _15147 = (uint16_t)(225); + _curvea0[717] = _15147; + uint16_t _15148 = (uint16_t)(226); + _curvea0[718] = _15148; + uint16_t _15149 = (uint16_t)(226); + _curvea0[719] = _15149; + uint16_t _15150 = (uint16_t)(226); + _curvea0[720] = _15150; + uint16_t _15151 = (uint16_t)(226); + _curvea0[721] = _15151; + uint16_t _15152 = (uint16_t)(226); + _curvea0[722] = _15152; + uint16_t _15153 = (uint16_t)(226); + _curvea0[723] = _15153; + uint16_t _15154 = (uint16_t)(226); + _curvea0[724] = _15154; + uint16_t _15155 = (uint16_t)(226); + _curvea0[725] = _15155; + uint16_t _15156 = (uint16_t)(227); + _curvea0[726] = _15156; + uint16_t _15157 = (uint16_t)(227); + _curvea0[727] = _15157; + uint16_t _15158 = (uint16_t)(227); + _curvea0[728] = _15158; + uint16_t _15159 = (uint16_t)(227); + _curvea0[729] = _15159; + uint16_t _15160 = (uint16_t)(227); + _curvea0[730] = _15160; + uint16_t _15161 = (uint16_t)(227); + _curvea0[731] = _15161; + uint16_t _15162 = (uint16_t)(227); + _curvea0[732] = _15162; + uint16_t _15163 = (uint16_t)(227); + _curvea0[733] = _15163; + uint16_t _15164 = (uint16_t)(228); + _curvea0[734] = _15164; + uint16_t _15165 = (uint16_t)(228); + _curvea0[735] = _15165; + uint16_t _15166 = (uint16_t)(228); + _curvea0[736] = _15166; + uint16_t _15167 = (uint16_t)(228); + _curvea0[737] = _15167; + uint16_t _15168 = (uint16_t)(228); + _curvea0[738] = _15168; + uint16_t _15169 = (uint16_t)(228); + _curvea0[739] = _15169; + uint16_t _15170 = (uint16_t)(228); + _curvea0[740] = _15170; + uint16_t _15171 = (uint16_t)(228); + _curvea0[741] = _15171; + uint16_t _15172 = (uint16_t)(228); + _curvea0[742] = _15172; + uint16_t _15173 = (uint16_t)(229); + _curvea0[743] = _15173; + uint16_t _15174 = (uint16_t)(229); + _curvea0[744] = _15174; + uint16_t _15175 = (uint16_t)(229); + _curvea0[745] = _15175; + uint16_t _15176 = (uint16_t)(229); + _curvea0[746] = _15176; + uint16_t _15177 = (uint16_t)(229); + _curvea0[747] = _15177; + uint16_t _15178 = (uint16_t)(229); + _curvea0[748] = _15178; + uint16_t _15179 = (uint16_t)(229); + _curvea0[749] = _15179; + uint16_t _15180 = (uint16_t)(229); + _curvea0[750] = _15180; + uint16_t _15181 = (uint16_t)(230); + _curvea0[751] = _15181; + uint16_t _15182 = (uint16_t)(230); + _curvea0[752] = _15182; + uint16_t _15183 = (uint16_t)(230); + _curvea0[753] = _15183; + uint16_t _15184 = (uint16_t)(230); + _curvea0[754] = _15184; + uint16_t _15185 = (uint16_t)(230); + _curvea0[755] = _15185; + uint16_t _15186 = (uint16_t)(230); + _curvea0[756] = _15186; + uint16_t _15187 = (uint16_t)(230); + _curvea0[757] = _15187; + uint16_t _15188 = (uint16_t)(230); + _curvea0[758] = _15188; + uint16_t _15189 = (uint16_t)(231); + _curvea0[759] = _15189; + uint16_t _15190 = (uint16_t)(231); + _curvea0[760] = _15190; + uint16_t _15191 = (uint16_t)(231); + _curvea0[761] = _15191; + uint16_t _15192 = (uint16_t)(231); + _curvea0[762] = _15192; + uint16_t _15193 = (uint16_t)(231); + _curvea0[763] = _15193; + uint16_t _15194 = (uint16_t)(231); + _curvea0[764] = _15194; + uint16_t _15195 = (uint16_t)(231); + _curvea0[765] = _15195; + uint16_t _15196 = (uint16_t)(231); + _curvea0[766] = _15196; + uint16_t _15197 = (uint16_t)(231); + _curvea0[767] = _15197; + uint16_t _15198 = (uint16_t)(232); + _curvea0[768] = _15198; + uint16_t _15199 = (uint16_t)(232); + _curvea0[769] = _15199; + uint16_t _15200 = (uint16_t)(232); + _curvea0[770] = _15200; + uint16_t _15201 = (uint16_t)(232); + _curvea0[771] = _15201; + uint16_t _15202 = (uint16_t)(232); + _curvea0[772] = _15202; + uint16_t _15203 = (uint16_t)(232); + _curvea0[773] = _15203; + uint16_t _15204 = (uint16_t)(232); + _curvea0[774] = _15204; + uint16_t _15205 = (uint16_t)(232); + _curvea0[775] = _15205; + uint16_t _15206 = (uint16_t)(233); + _curvea0[776] = _15206; + uint16_t _15207 = (uint16_t)(233); + _curvea0[777] = _15207; + uint16_t _15208 = (uint16_t)(233); + _curvea0[778] = _15208; + uint16_t _15209 = (uint16_t)(233); + _curvea0[779] = _15209; + uint16_t _15210 = (uint16_t)(233); + _curvea0[780] = _15210; + uint16_t _15211 = (uint16_t)(233); + _curvea0[781] = _15211; + uint16_t _15212 = (uint16_t)(233); + _curvea0[782] = _15212; + uint16_t _15213 = (uint16_t)(233); + _curvea0[783] = _15213; + uint16_t _15214 = (uint16_t)(233); + _curvea0[784] = _15214; + uint16_t _15215 = (uint16_t)(234); + _curvea0[785] = _15215; + uint16_t _15216 = (uint16_t)(234); + _curvea0[786] = _15216; + uint16_t _15217 = (uint16_t)(234); + _curvea0[787] = _15217; + uint16_t _15218 = (uint16_t)(234); + _curvea0[788] = _15218; + uint16_t _15219 = (uint16_t)(234); + _curvea0[789] = _15219; + uint16_t _15220 = (uint16_t)(234); + _curvea0[790] = _15220; + uint16_t _15221 = (uint16_t)(234); + _curvea0[791] = _15221; + uint16_t _15222 = (uint16_t)(234); + _curvea0[792] = _15222; + uint16_t _15223 = (uint16_t)(234); + _curvea0[793] = _15223; + uint16_t _15224 = (uint16_t)(235); + _curvea0[794] = _15224; + uint16_t _15225 = (uint16_t)(235); + _curvea0[795] = _15225; + uint16_t _15226 = (uint16_t)(235); + _curvea0[796] = _15226; + uint16_t _15227 = (uint16_t)(235); + _curvea0[797] = _15227; + uint16_t _15228 = (uint16_t)(235); + _curvea0[798] = _15228; + uint16_t _15229 = (uint16_t)(235); + _curvea0[799] = _15229; + uint16_t _15230 = (uint16_t)(235); + _curvea0[800] = _15230; + uint16_t _15231 = (uint16_t)(235); + _curvea0[801] = _15231; + uint16_t _15232 = (uint16_t)(235); + _curvea0[802] = _15232; + uint16_t _15233 = (uint16_t)(236); + _curvea0[803] = _15233; + uint16_t _15234 = (uint16_t)(236); + _curvea0[804] = _15234; + uint16_t _15235 = (uint16_t)(236); + _curvea0[805] = _15235; + uint16_t _15236 = (uint16_t)(236); + _curvea0[806] = _15236; + uint16_t _15237 = (uint16_t)(236); + _curvea0[807] = _15237; + uint16_t _15238 = (uint16_t)(236); + _curvea0[808] = _15238; + uint16_t _15239 = (uint16_t)(236); + _curvea0[809] = _15239; + uint16_t _15240 = (uint16_t)(236); + _curvea0[810] = _15240; + uint16_t _15241 = (uint16_t)(236); + _curvea0[811] = _15241; + uint16_t _15242 = (uint16_t)(237); + _curvea0[812] = _15242; + uint16_t _15243 = (uint16_t)(237); + _curvea0[813] = _15243; + uint16_t _15244 = (uint16_t)(237); + _curvea0[814] = _15244; + uint16_t _15245 = (uint16_t)(237); + _curvea0[815] = _15245; + uint16_t _15246 = (uint16_t)(237); + _curvea0[816] = _15246; + uint16_t _15247 = (uint16_t)(237); + _curvea0[817] = _15247; + uint16_t _15248 = (uint16_t)(237); + _curvea0[818] = _15248; + uint16_t _15249 = (uint16_t)(237); + _curvea0[819] = _15249; + uint16_t _15250 = (uint16_t)(237); + _curvea0[820] = _15250; + uint16_t _15251 = (uint16_t)(237); + _curvea0[821] = _15251; + uint16_t _15252 = (uint16_t)(238); + _curvea0[822] = _15252; + uint16_t _15253 = (uint16_t)(238); + _curvea0[823] = _15253; + uint16_t _15254 = (uint16_t)(238); + _curvea0[824] = _15254; + uint16_t _15255 = (uint16_t)(238); + _curvea0[825] = _15255; + uint16_t _15256 = (uint16_t)(238); + _curvea0[826] = _15256; + uint16_t _15257 = (uint16_t)(238); + _curvea0[827] = _15257; + uint16_t _15258 = (uint16_t)(238); + _curvea0[828] = _15258; + uint16_t _15259 = (uint16_t)(238); + _curvea0[829] = _15259; + uint16_t _15260 = (uint16_t)(238); + _curvea0[830] = _15260; + uint16_t _15261 = (uint16_t)(239); + _curvea0[831] = _15261; + uint16_t _15262 = (uint16_t)(239); + _curvea0[832] = _15262; + uint16_t _15263 = (uint16_t)(239); + _curvea0[833] = _15263; + uint16_t _15264 = (uint16_t)(239); + _curvea0[834] = _15264; + uint16_t _15265 = (uint16_t)(239); + _curvea0[835] = _15265; + uint16_t _15266 = (uint16_t)(239); + _curvea0[836] = _15266; + uint16_t _15267 = (uint16_t)(239); + _curvea0[837] = _15267; + uint16_t _15268 = (uint16_t)(239); + _curvea0[838] = _15268; + uint16_t _15269 = (uint16_t)(239); + _curvea0[839] = _15269; + uint16_t _15270 = (uint16_t)(239); + _curvea0[840] = _15270; + uint16_t _15271 = (uint16_t)(240); + _curvea0[841] = _15271; + uint16_t _15272 = (uint16_t)(240); + _curvea0[842] = _15272; + uint16_t _15273 = (uint16_t)(240); + _curvea0[843] = _15273; + uint16_t _15274 = (uint16_t)(240); + _curvea0[844] = _15274; + uint16_t _15275 = (uint16_t)(240); + _curvea0[845] = _15275; + uint16_t _15276 = (uint16_t)(240); + _curvea0[846] = _15276; + uint16_t _15277 = (uint16_t)(240); + _curvea0[847] = _15277; + uint16_t _15278 = (uint16_t)(240); + _curvea0[848] = _15278; + uint16_t _15279 = (uint16_t)(240); + _curvea0[849] = _15279; + uint16_t _15280 = (uint16_t)(240); + _curvea0[850] = _15280; + uint16_t _15281 = (uint16_t)(241); + _curvea0[851] = _15281; + uint16_t _15282 = (uint16_t)(241); + _curvea0[852] = _15282; + uint16_t _15283 = (uint16_t)(241); + _curvea0[853] = _15283; + uint16_t _15284 = (uint16_t)(241); + _curvea0[854] = _15284; + uint16_t _15285 = (uint16_t)(241); + _curvea0[855] = _15285; + uint16_t _15286 = (uint16_t)(241); + _curvea0[856] = _15286; + uint16_t _15287 = (uint16_t)(241); + _curvea0[857] = _15287; + uint16_t _15288 = (uint16_t)(241); + _curvea0[858] = _15288; + uint16_t _15289 = (uint16_t)(241); + _curvea0[859] = _15289; + uint16_t _15290 = (uint16_t)(241); + _curvea0[860] = _15290; + uint16_t _15291 = (uint16_t)(242); + _curvea0[861] = _15291; + uint16_t _15292 = (uint16_t)(242); + _curvea0[862] = _15292; + uint16_t _15293 = (uint16_t)(242); + _curvea0[863] = _15293; + uint16_t _15294 = (uint16_t)(242); + _curvea0[864] = _15294; + uint16_t _15295 = (uint16_t)(242); + _curvea0[865] = _15295; + uint16_t _15296 = (uint16_t)(242); + _curvea0[866] = _15296; + uint16_t _15297 = (uint16_t)(242); + _curvea0[867] = _15297; + uint16_t _15298 = (uint16_t)(242); + _curvea0[868] = _15298; + uint16_t _15299 = (uint16_t)(242); + _curvea0[869] = _15299; + uint16_t _15300 = (uint16_t)(242); + _curvea0[870] = _15300; + uint16_t _15301 = (uint16_t)(243); + _curvea0[871] = _15301; + uint16_t _15302 = (uint16_t)(243); + _curvea0[872] = _15302; + uint16_t _15303 = (uint16_t)(243); + _curvea0[873] = _15303; + uint16_t _15304 = (uint16_t)(243); + _curvea0[874] = _15304; + uint16_t _15305 = (uint16_t)(243); + _curvea0[875] = _15305; + uint16_t _15306 = (uint16_t)(243); + _curvea0[876] = _15306; + uint16_t _15307 = (uint16_t)(243); + _curvea0[877] = _15307; + uint16_t _15308 = (uint16_t)(243); + _curvea0[878] = _15308; + uint16_t _15309 = (uint16_t)(243); + _curvea0[879] = _15309; + uint16_t _15310 = (uint16_t)(243); + _curvea0[880] = _15310; + uint16_t _15311 = (uint16_t)(244); + _curvea0[881] = _15311; + uint16_t _15312 = (uint16_t)(244); + _curvea0[882] = _15312; + uint16_t _15313 = (uint16_t)(244); + _curvea0[883] = _15313; + uint16_t _15314 = (uint16_t)(244); + _curvea0[884] = _15314; + uint16_t _15315 = (uint16_t)(244); + _curvea0[885] = _15315; + uint16_t _15316 = (uint16_t)(244); + _curvea0[886] = _15316; + uint16_t _15317 = (uint16_t)(244); + _curvea0[887] = _15317; + uint16_t _15318 = (uint16_t)(244); + _curvea0[888] = _15318; + uint16_t _15319 = (uint16_t)(244); + _curvea0[889] = _15319; + uint16_t _15320 = (uint16_t)(244); + _curvea0[890] = _15320; + uint16_t _15321 = (uint16_t)(244); + _curvea0[891] = _15321; + uint16_t _15322 = (uint16_t)(245); + _curvea0[892] = _15322; + uint16_t _15323 = (uint16_t)(245); + _curvea0[893] = _15323; + uint16_t _15324 = (uint16_t)(245); + _curvea0[894] = _15324; + uint16_t _15325 = (uint16_t)(245); + _curvea0[895] = _15325; + uint16_t _15326 = (uint16_t)(245); + _curvea0[896] = _15326; + uint16_t _15327 = (uint16_t)(245); + _curvea0[897] = _15327; + uint16_t _15328 = (uint16_t)(245); + _curvea0[898] = _15328; + uint16_t _15329 = (uint16_t)(245); + _curvea0[899] = _15329; + uint16_t _15330 = (uint16_t)(245); + _curvea0[900] = _15330; + uint16_t _15331 = (uint16_t)(245); + _curvea0[901] = _15331; + uint16_t _15332 = (uint16_t)(245); + _curvea0[902] = _15332; + uint16_t _15333 = (uint16_t)(246); + _curvea0[903] = _15333; + uint16_t _15334 = (uint16_t)(246); + _curvea0[904] = _15334; + uint16_t _15335 = (uint16_t)(246); + _curvea0[905] = _15335; + uint16_t _15336 = (uint16_t)(246); + _curvea0[906] = _15336; + uint16_t _15337 = (uint16_t)(246); + _curvea0[907] = _15337; + uint16_t _15338 = (uint16_t)(246); + _curvea0[908] = _15338; + uint16_t _15339 = (uint16_t)(246); + _curvea0[909] = _15339; + uint16_t _15340 = (uint16_t)(246); + _curvea0[910] = _15340; + uint16_t _15341 = (uint16_t)(246); + _curvea0[911] = _15341; + uint16_t _15342 = (uint16_t)(246); + _curvea0[912] = _15342; + uint16_t _15343 = (uint16_t)(246); + _curvea0[913] = _15343; + uint16_t _15344 = (uint16_t)(247); + _curvea0[914] = _15344; + uint16_t _15345 = (uint16_t)(247); + _curvea0[915] = _15345; + uint16_t _15346 = (uint16_t)(247); + _curvea0[916] = _15346; + uint16_t _15347 = (uint16_t)(247); + _curvea0[917] = _15347; + uint16_t _15348 = (uint16_t)(247); + _curvea0[918] = _15348; + uint16_t _15349 = (uint16_t)(247); + _curvea0[919] = _15349; + uint16_t _15350 = (uint16_t)(247); + _curvea0[920] = _15350; + uint16_t _15351 = (uint16_t)(247); + _curvea0[921] = _15351; + uint16_t _15352 = (uint16_t)(247); + _curvea0[922] = _15352; + uint16_t _15353 = (uint16_t)(247); + _curvea0[923] = _15353; + uint16_t _15354 = (uint16_t)(247); + _curvea0[924] = _15354; + uint16_t _15355 = (uint16_t)(248); + _curvea0[925] = _15355; + uint16_t _15356 = (uint16_t)(248); + _curvea0[926] = _15356; + uint16_t _15357 = (uint16_t)(248); + _curvea0[927] = _15357; + uint16_t _15358 = (uint16_t)(248); + _curvea0[928] = _15358; + uint16_t _15359 = (uint16_t)(248); + _curvea0[929] = _15359; + uint16_t _15360 = (uint16_t)(248); + _curvea0[930] = _15360; + uint16_t _15361 = (uint16_t)(248); + _curvea0[931] = _15361; + uint16_t _15362 = (uint16_t)(248); + _curvea0[932] = _15362; + uint16_t _15363 = (uint16_t)(248); + _curvea0[933] = _15363; + uint16_t _15364 = (uint16_t)(248); + _curvea0[934] = _15364; + uint16_t _15365 = (uint16_t)(248); + _curvea0[935] = _15365; + uint16_t _15366 = (uint16_t)(249); + _curvea0[936] = _15366; + uint16_t _15367 = (uint16_t)(249); + _curvea0[937] = _15367; + uint16_t _15368 = (uint16_t)(249); + _curvea0[938] = _15368; + uint16_t _15369 = (uint16_t)(249); + _curvea0[939] = _15369; + uint16_t _15370 = (uint16_t)(249); + _curvea0[940] = _15370; + uint16_t _15371 = (uint16_t)(249); + _curvea0[941] = _15371; + uint16_t _15372 = (uint16_t)(249); + _curvea0[942] = _15372; + uint16_t _15373 = (uint16_t)(249); + _curvea0[943] = _15373; + uint16_t _15374 = (uint16_t)(249); + _curvea0[944] = _15374; + uint16_t _15375 = (uint16_t)(249); + _curvea0[945] = _15375; + uint16_t _15376 = (uint16_t)(249); + _curvea0[946] = _15376; + uint16_t _15377 = (uint16_t)(249); + _curvea0[947] = _15377; + uint16_t _15378 = (uint16_t)(250); + _curvea0[948] = _15378; + uint16_t _15379 = (uint16_t)(250); + _curvea0[949] = _15379; + uint16_t _15380 = (uint16_t)(250); + _curvea0[950] = _15380; + uint16_t _15381 = (uint16_t)(250); + _curvea0[951] = _15381; + uint16_t _15382 = (uint16_t)(250); + _curvea0[952] = _15382; + uint16_t _15383 = (uint16_t)(250); + _curvea0[953] = _15383; + uint16_t _15384 = (uint16_t)(250); + _curvea0[954] = _15384; + uint16_t _15385 = (uint16_t)(250); + _curvea0[955] = _15385; + uint16_t _15386 = (uint16_t)(250); + _curvea0[956] = _15386; + uint16_t _15387 = (uint16_t)(250); + _curvea0[957] = _15387; + uint16_t _15388 = (uint16_t)(250); + _curvea0[958] = _15388; + uint16_t _15389 = (uint16_t)(250); + _curvea0[959] = _15389; + uint16_t _15390 = (uint16_t)(251); + _curvea0[960] = _15390; + uint16_t _15391 = (uint16_t)(251); + _curvea0[961] = _15391; + uint16_t _15392 = (uint16_t)(251); + _curvea0[962] = _15392; + uint16_t _15393 = (uint16_t)(251); + _curvea0[963] = _15393; + uint16_t _15394 = (uint16_t)(251); + _curvea0[964] = _15394; + uint16_t _15395 = (uint16_t)(251); + _curvea0[965] = _15395; + uint16_t _15396 = (uint16_t)(251); + _curvea0[966] = _15396; + uint16_t _15397 = (uint16_t)(251); + _curvea0[967] = _15397; + uint16_t _15398 = (uint16_t)(251); + _curvea0[968] = _15398; + uint16_t _15399 = (uint16_t)(251); + _curvea0[969] = _15399; + uint16_t _15400 = (uint16_t)(251); + _curvea0[970] = _15400; + uint16_t _15401 = (uint16_t)(251); + _curvea0[971] = _15401; + uint16_t _15402 = (uint16_t)(252); + _curvea0[972] = _15402; + uint16_t _15403 = (uint16_t)(252); + _curvea0[973] = _15403; + uint16_t _15404 = (uint16_t)(252); + _curvea0[974] = _15404; + uint16_t _15405 = (uint16_t)(252); + _curvea0[975] = _15405; + uint16_t _15406 = (uint16_t)(252); + _curvea0[976] = _15406; + uint16_t _15407 = (uint16_t)(252); + _curvea0[977] = _15407; + uint16_t _15408 = (uint16_t)(252); + _curvea0[978] = _15408; + uint16_t _15409 = (uint16_t)(252); + _curvea0[979] = _15409; + uint16_t _15410 = (uint16_t)(252); + _curvea0[980] = _15410; + uint16_t _15411 = (uint16_t)(252); + _curvea0[981] = _15411; + uint16_t _15412 = (uint16_t)(252); + _curvea0[982] = _15412; + uint16_t _15413 = (uint16_t)(252); + _curvea0[983] = _15413; + uint16_t _15414 = (uint16_t)(252); + _curvea0[984] = _15414; + uint16_t _15415 = (uint16_t)(253); + _curvea0[985] = _15415; + uint16_t _15416 = (uint16_t)(253); + _curvea0[986] = _15416; + uint16_t _15417 = (uint16_t)(253); + _curvea0[987] = _15417; + uint16_t _15418 = (uint16_t)(253); + _curvea0[988] = _15418; + uint16_t _15419 = (uint16_t)(253); + _curvea0[989] = _15419; + uint16_t _15420 = (uint16_t)(253); + _curvea0[990] = _15420; + uint16_t _15421 = (uint16_t)(253); + _curvea0[991] = _15421; + uint16_t _15422 = (uint16_t)(253); + _curvea0[992] = _15422; + uint16_t _15423 = (uint16_t)(253); + _curvea0[993] = _15423; + uint16_t _15424 = (uint16_t)(253); + _curvea0[994] = _15424; + uint16_t _15425 = (uint16_t)(253); + _curvea0[995] = _15425; + uint16_t _15426 = (uint16_t)(253); + _curvea0[996] = _15426; + uint16_t _15427 = (uint16_t)(253); + _curvea0[997] = _15427; + uint16_t _15428 = (uint16_t)(254); + _curvea0[998] = _15428; + uint16_t _15429 = (uint16_t)(254); + _curvea0[999] = _15429; + uint16_t _15430 = (uint16_t)(254); + _curvea0[1000] = _15430; + uint16_t _15431 = (uint16_t)(254); + _curvea0[1001] = _15431; + uint16_t _15432 = (uint16_t)(254); + _curvea0[1002] = _15432; + uint16_t _15433 = (uint16_t)(254); + _curvea0[1003] = _15433; + uint16_t _15434 = (uint16_t)(254); + _curvea0[1004] = _15434; + uint16_t _15435 = (uint16_t)(254); + _curvea0[1005] = _15435; + uint16_t _15436 = (uint16_t)(254); + _curvea0[1006] = _15436; + uint16_t _15437 = (uint16_t)(254); + _curvea0[1007] = _15437; + uint16_t _15438 = (uint16_t)(254); + _curvea0[1008] = _15438; + uint16_t _15439 = (uint16_t)(254); + _curvea0[1009] = _15439; + uint16_t _15440 = (uint16_t)(254); + _curvea0[1010] = _15440; + uint16_t _15441 = (uint16_t)(255); + _curvea0[1011] = _15441; + uint16_t _15442 = (uint16_t)(255); + _curvea0[1012] = _15442; + uint16_t _15443 = (uint16_t)(255); + _curvea0[1013] = _15443; + uint16_t _15444 = (uint16_t)(255); + _curvea0[1014] = _15444; + uint16_t _15445 = (uint16_t)(255); + _curvea0[1015] = _15445; + uint16_t _15446 = (uint16_t)(255); + _curvea0[1016] = _15446; + uint16_t _15447 = (uint16_t)(255); + _curvea0[1017] = _15447; + uint16_t _15448 = (uint16_t)(255); + _curvea0[1018] = _15448; + uint16_t _15449 = (uint16_t)(255); + _curvea0[1019] = _15449; + uint16_t _15450 = (uint16_t)(255); + _curvea0[1020] = _15450; + uint16_t _15451 = (uint16_t)(255); + _curvea0[1021] = _15451; + uint16_t _15452 = (uint16_t)(255); + _curvea0[1022] = _15452; + uint16_t _15453 = (uint16_t)(255); + _curvea0[1023] = _15453; + + int16_t _15454 = (int16_t)(1023); + int16_t _15455 = min(_corrected_stencil_11, _15454); + int16_t _15456 = (int16_t)(0); + int16_t _15457 = max(_15455, _15456); + uint16_t _15458 = (uint16_t)(_15457); + int32_t _15459 = (int32_t)(_15458); + uint16_t _15460 = ((const uint16_t *)_curvea0)[_15459]; + return _15460; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_11(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_12 = (int16_t) (corrected_stencil.extract<0, 15>()); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _15479 = (uint16_t)(0); + _curvea0[0] = _15479; + uint16_t _15480 = (uint16_t)(4); + _curvea0[1] = _15480; + uint16_t _15481 = (uint16_t)(7); + _curvea0[2] = _15481; + uint16_t _15482 = (uint16_t)(8); + _curvea0[3] = _15482; + uint16_t _15483 = (uint16_t)(10); + _curvea0[4] = _15483; + uint16_t _15484 = (uint16_t)(11); + _curvea0[5] = _15484; + uint16_t _15485 = (uint16_t)(12); + _curvea0[6] = _15485; + uint16_t _15486 = (uint16_t)(13); + _curvea0[7] = _15486; + uint16_t _15487 = (uint16_t)(14); + _curvea0[8] = _15487; + uint16_t _15488 = (uint16_t)(15); + _curvea0[9] = _15488; + uint16_t _15489 = (uint16_t)(16); + _curvea0[10] = _15489; + uint16_t _15490 = (uint16_t)(17); + _curvea0[11] = _15490; + uint16_t _15491 = (uint16_t)(18); + _curvea0[12] = _15491; + uint16_t _15492 = (uint16_t)(19); + _curvea0[13] = _15492; + uint16_t _15493 = (uint16_t)(20); + _curvea0[14] = _15493; + uint16_t _15494 = (uint16_t)(21); + _curvea0[15] = _15494; + uint16_t _15495 = (uint16_t)(22); + _curvea0[16] = _15495; + uint16_t _15496 = (uint16_t)(22); + _curvea0[17] = _15496; + uint16_t _15497 = (uint16_t)(23); + _curvea0[18] = _15497; + uint16_t _15498 = (uint16_t)(24); + _curvea0[19] = _15498; + uint16_t _15499 = (uint16_t)(25); + _curvea0[20] = _15499; + uint16_t _15500 = (uint16_t)(25); + _curvea0[21] = _15500; + uint16_t _15501 = (uint16_t)(26); + _curvea0[22] = _15501; + uint16_t _15502 = (uint16_t)(27); + _curvea0[23] = _15502; + uint16_t _15503 = (uint16_t)(27); + _curvea0[24] = _15503; + uint16_t _15504 = (uint16_t)(28); + _curvea0[25] = _15504; + uint16_t _15505 = (uint16_t)(29); + _curvea0[26] = _15505; + uint16_t _15506 = (uint16_t)(29); + _curvea0[27] = _15506; + uint16_t _15507 = (uint16_t)(30); + _curvea0[28] = _15507; + uint16_t _15508 = (uint16_t)(31); + _curvea0[29] = _15508; + uint16_t _15509 = (uint16_t)(31); + _curvea0[30] = _15509; + uint16_t _15510 = (uint16_t)(32); + _curvea0[31] = _15510; + uint16_t _15511 = (uint16_t)(33); + _curvea0[32] = _15511; + uint16_t _15512 = (uint16_t)(33); + _curvea0[33] = _15512; + uint16_t _15513 = (uint16_t)(34); + _curvea0[34] = _15513; + uint16_t _15514 = (uint16_t)(34); + _curvea0[35] = _15514; + uint16_t _15515 = (uint16_t)(35); + _curvea0[36] = _15515; + uint16_t _15516 = (uint16_t)(36); + _curvea0[37] = _15516; + uint16_t _15517 = (uint16_t)(36); + _curvea0[38] = _15517; + uint16_t _15518 = (uint16_t)(37); + _curvea0[39] = _15518; + uint16_t _15519 = (uint16_t)(37); + _curvea0[40] = _15519; + uint16_t _15520 = (uint16_t)(38); + _curvea0[41] = _15520; + uint16_t _15521 = (uint16_t)(39); + _curvea0[42] = _15521; + uint16_t _15522 = (uint16_t)(39); + _curvea0[43] = _15522; + uint16_t _15523 = (uint16_t)(40); + _curvea0[44] = _15523; + uint16_t _15524 = (uint16_t)(40); + _curvea0[45] = _15524; + uint16_t _15525 = (uint16_t)(41); + _curvea0[46] = _15525; + uint16_t _15526 = (uint16_t)(41); + _curvea0[47] = _15526; + uint16_t _15527 = (uint16_t)(42); + _curvea0[48] = _15527; + uint16_t _15528 = (uint16_t)(42); + _curvea0[49] = _15528; + uint16_t _15529 = (uint16_t)(43); + _curvea0[50] = _15529; + uint16_t _15530 = (uint16_t)(44); + _curvea0[51] = _15530; + uint16_t _15531 = (uint16_t)(44); + _curvea0[52] = _15531; + uint16_t _15532 = (uint16_t)(45); + _curvea0[53] = _15532; + uint16_t _15533 = (uint16_t)(45); + _curvea0[54] = _15533; + uint16_t _15534 = (uint16_t)(46); + _curvea0[55] = _15534; + uint16_t _15535 = (uint16_t)(46); + _curvea0[56] = _15535; + uint16_t _15536 = (uint16_t)(47); + _curvea0[57] = _15536; + uint16_t _15537 = (uint16_t)(47); + _curvea0[58] = _15537; + uint16_t _15538 = (uint16_t)(48); + _curvea0[59] = _15538; + uint16_t _15539 = (uint16_t)(48); + _curvea0[60] = _15539; + uint16_t _15540 = (uint16_t)(49); + _curvea0[61] = _15540; + uint16_t _15541 = (uint16_t)(49); + _curvea0[62] = _15541; + uint16_t _15542 = (uint16_t)(50); + _curvea0[63] = _15542; + uint16_t _15543 = (uint16_t)(50); + _curvea0[64] = _15543; + uint16_t _15544 = (uint16_t)(51); + _curvea0[65] = _15544; + uint16_t _15545 = (uint16_t)(51); + _curvea0[66] = _15545; + uint16_t _15546 = (uint16_t)(52); + _curvea0[67] = _15546; + uint16_t _15547 = (uint16_t)(52); + _curvea0[68] = _15547; + uint16_t _15548 = (uint16_t)(53); + _curvea0[69] = _15548; + uint16_t _15549 = (uint16_t)(53); + _curvea0[70] = _15549; + uint16_t _15550 = (uint16_t)(54); + _curvea0[71] = _15550; + uint16_t _15551 = (uint16_t)(54); + _curvea0[72] = _15551; + uint16_t _15552 = (uint16_t)(55); + _curvea0[73] = _15552; + uint16_t _15553 = (uint16_t)(55); + _curvea0[74] = _15553; + uint16_t _15554 = (uint16_t)(56); + _curvea0[75] = _15554; + uint16_t _15555 = (uint16_t)(56); + _curvea0[76] = _15555; + uint16_t _15556 = (uint16_t)(57); + _curvea0[77] = _15556; + uint16_t _15557 = (uint16_t)(57); + _curvea0[78] = _15557; + uint16_t _15558 = (uint16_t)(58); + _curvea0[79] = _15558; + uint16_t _15559 = (uint16_t)(58); + _curvea0[80] = _15559; + uint16_t _15560 = (uint16_t)(58); + _curvea0[81] = _15560; + uint16_t _15561 = (uint16_t)(59); + _curvea0[82] = _15561; + uint16_t _15562 = (uint16_t)(59); + _curvea0[83] = _15562; + uint16_t _15563 = (uint16_t)(60); + _curvea0[84] = _15563; + uint16_t _15564 = (uint16_t)(60); + _curvea0[85] = _15564; + uint16_t _15565 = (uint16_t)(61); + _curvea0[86] = _15565; + uint16_t _15566 = (uint16_t)(61); + _curvea0[87] = _15566; + uint16_t _15567 = (uint16_t)(62); + _curvea0[88] = _15567; + uint16_t _15568 = (uint16_t)(62); + _curvea0[89] = _15568; + uint16_t _15569 = (uint16_t)(63); + _curvea0[90] = _15569; + uint16_t _15570 = (uint16_t)(63); + _curvea0[91] = _15570; + uint16_t _15571 = (uint16_t)(64); + _curvea0[92] = _15571; + uint16_t _15572 = (uint16_t)(64); + _curvea0[93] = _15572; + uint16_t _15573 = (uint16_t)(64); + _curvea0[94] = _15573; + uint16_t _15574 = (uint16_t)(65); + _curvea0[95] = _15574; + uint16_t _15575 = (uint16_t)(65); + _curvea0[96] = _15575; + uint16_t _15576 = (uint16_t)(66); + _curvea0[97] = _15576; + uint16_t _15577 = (uint16_t)(66); + _curvea0[98] = _15577; + uint16_t _15578 = (uint16_t)(67); + _curvea0[99] = _15578; + uint16_t _15579 = (uint16_t)(67); + _curvea0[100] = _15579; + uint16_t _15580 = (uint16_t)(68); + _curvea0[101] = _15580; + uint16_t _15581 = (uint16_t)(68); + _curvea0[102] = _15581; + uint16_t _15582 = (uint16_t)(68); + _curvea0[103] = _15582; + uint16_t _15583 = (uint16_t)(69); + _curvea0[104] = _15583; + uint16_t _15584 = (uint16_t)(69); + _curvea0[105] = _15584; + uint16_t _15585 = (uint16_t)(70); + _curvea0[106] = _15585; + uint16_t _15586 = (uint16_t)(70); + _curvea0[107] = _15586; + uint16_t _15587 = (uint16_t)(71); + _curvea0[108] = _15587; + uint16_t _15588 = (uint16_t)(71); + _curvea0[109] = _15588; + uint16_t _15589 = (uint16_t)(71); + _curvea0[110] = _15589; + uint16_t _15590 = (uint16_t)(72); + _curvea0[111] = _15590; + uint16_t _15591 = (uint16_t)(72); + _curvea0[112] = _15591; + uint16_t _15592 = (uint16_t)(73); + _curvea0[113] = _15592; + uint16_t _15593 = (uint16_t)(73); + _curvea0[114] = _15593; + uint16_t _15594 = (uint16_t)(74); + _curvea0[115] = _15594; + uint16_t _15595 = (uint16_t)(74); + _curvea0[116] = _15595; + uint16_t _15596 = (uint16_t)(74); + _curvea0[117] = _15596; + uint16_t _15597 = (uint16_t)(75); + _curvea0[118] = _15597; + uint16_t _15598 = (uint16_t)(75); + _curvea0[119] = _15598; + uint16_t _15599 = (uint16_t)(76); + _curvea0[120] = _15599; + uint16_t _15600 = (uint16_t)(76); + _curvea0[121] = _15600; + uint16_t _15601 = (uint16_t)(77); + _curvea0[122] = _15601; + uint16_t _15602 = (uint16_t)(77); + _curvea0[123] = _15602; + uint16_t _15603 = (uint16_t)(77); + _curvea0[124] = _15603; + uint16_t _15604 = (uint16_t)(78); + _curvea0[125] = _15604; + uint16_t _15605 = (uint16_t)(78); + _curvea0[126] = _15605; + uint16_t _15606 = (uint16_t)(79); + _curvea0[127] = _15606; + uint16_t _15607 = (uint16_t)(79); + _curvea0[128] = _15607; + uint16_t _15608 = (uint16_t)(79); + _curvea0[129] = _15608; + uint16_t _15609 = (uint16_t)(80); + _curvea0[130] = _15609; + uint16_t _15610 = (uint16_t)(80); + _curvea0[131] = _15610; + uint16_t _15611 = (uint16_t)(81); + _curvea0[132] = _15611; + uint16_t _15612 = (uint16_t)(81); + _curvea0[133] = _15612; + uint16_t _15613 = (uint16_t)(82); + _curvea0[134] = _15613; + uint16_t _15614 = (uint16_t)(82); + _curvea0[135] = _15614; + uint16_t _15615 = (uint16_t)(82); + _curvea0[136] = _15615; + uint16_t _15616 = (uint16_t)(83); + _curvea0[137] = _15616; + uint16_t _15617 = (uint16_t)(83); + _curvea0[138] = _15617; + uint16_t _15618 = (uint16_t)(84); + _curvea0[139] = _15618; + uint16_t _15619 = (uint16_t)(84); + _curvea0[140] = _15619; + uint16_t _15620 = (uint16_t)(84); + _curvea0[141] = _15620; + uint16_t _15621 = (uint16_t)(85); + _curvea0[142] = _15621; + uint16_t _15622 = (uint16_t)(85); + _curvea0[143] = _15622; + uint16_t _15623 = (uint16_t)(86); + _curvea0[144] = _15623; + uint16_t _15624 = (uint16_t)(86); + _curvea0[145] = _15624; + uint16_t _15625 = (uint16_t)(86); + _curvea0[146] = _15625; + uint16_t _15626 = (uint16_t)(87); + _curvea0[147] = _15626; + uint16_t _15627 = (uint16_t)(87); + _curvea0[148] = _15627; + uint16_t _15628 = (uint16_t)(88); + _curvea0[149] = _15628; + uint16_t _15629 = (uint16_t)(88); + _curvea0[150] = _15629; + uint16_t _15630 = (uint16_t)(88); + _curvea0[151] = _15630; + uint16_t _15631 = (uint16_t)(89); + _curvea0[152] = _15631; + uint16_t _15632 = (uint16_t)(89); + _curvea0[153] = _15632; + uint16_t _15633 = (uint16_t)(90); + _curvea0[154] = _15633; + uint16_t _15634 = (uint16_t)(90); + _curvea0[155] = _15634; + uint16_t _15635 = (uint16_t)(90); + _curvea0[156] = _15635; + uint16_t _15636 = (uint16_t)(91); + _curvea0[157] = _15636; + uint16_t _15637 = (uint16_t)(91); + _curvea0[158] = _15637; + uint16_t _15638 = (uint16_t)(92); + _curvea0[159] = _15638; + uint16_t _15639 = (uint16_t)(92); + _curvea0[160] = _15639; + uint16_t _15640 = (uint16_t)(92); + _curvea0[161] = _15640; + uint16_t _15641 = (uint16_t)(93); + _curvea0[162] = _15641; + uint16_t _15642 = (uint16_t)(93); + _curvea0[163] = _15642; + uint16_t _15643 = (uint16_t)(93); + _curvea0[164] = _15643; + uint16_t _15644 = (uint16_t)(94); + _curvea0[165] = _15644; + uint16_t _15645 = (uint16_t)(94); + _curvea0[166] = _15645; + uint16_t _15646 = (uint16_t)(95); + _curvea0[167] = _15646; + uint16_t _15647 = (uint16_t)(95); + _curvea0[168] = _15647; + uint16_t _15648 = (uint16_t)(95); + _curvea0[169] = _15648; + uint16_t _15649 = (uint16_t)(96); + _curvea0[170] = _15649; + uint16_t _15650 = (uint16_t)(96); + _curvea0[171] = _15650; + uint16_t _15651 = (uint16_t)(97); + _curvea0[172] = _15651; + uint16_t _15652 = (uint16_t)(97); + _curvea0[173] = _15652; + uint16_t _15653 = (uint16_t)(97); + _curvea0[174] = _15653; + uint16_t _15654 = (uint16_t)(98); + _curvea0[175] = _15654; + uint16_t _15655 = (uint16_t)(98); + _curvea0[176] = _15655; + uint16_t _15656 = (uint16_t)(99); + _curvea0[177] = _15656; + uint16_t _15657 = (uint16_t)(99); + _curvea0[178] = _15657; + uint16_t _15658 = (uint16_t)(99); + _curvea0[179] = _15658; + uint16_t _15659 = (uint16_t)(100); + _curvea0[180] = _15659; + uint16_t _15660 = (uint16_t)(100); + _curvea0[181] = _15660; + uint16_t _15661 = (uint16_t)(100); + _curvea0[182] = _15661; + uint16_t _15662 = (uint16_t)(101); + _curvea0[183] = _15662; + uint16_t _15663 = (uint16_t)(101); + _curvea0[184] = _15663; + uint16_t _15664 = (uint16_t)(102); + _curvea0[185] = _15664; + uint16_t _15665 = (uint16_t)(102); + _curvea0[186] = _15665; + uint16_t _15666 = (uint16_t)(102); + _curvea0[187] = _15666; + uint16_t _15667 = (uint16_t)(103); + _curvea0[188] = _15667; + uint16_t _15668 = (uint16_t)(103); + _curvea0[189] = _15668; + uint16_t _15669 = (uint16_t)(103); + _curvea0[190] = _15669; + uint16_t _15670 = (uint16_t)(104); + _curvea0[191] = _15670; + uint16_t _15671 = (uint16_t)(104); + _curvea0[192] = _15671; + uint16_t _15672 = (uint16_t)(105); + _curvea0[193] = _15672; + uint16_t _15673 = (uint16_t)(105); + _curvea0[194] = _15673; + uint16_t _15674 = (uint16_t)(105); + _curvea0[195] = _15674; + uint16_t _15675 = (uint16_t)(106); + _curvea0[196] = _15675; + uint16_t _15676 = (uint16_t)(106); + _curvea0[197] = _15676; + uint16_t _15677 = (uint16_t)(106); + _curvea0[198] = _15677; + uint16_t _15678 = (uint16_t)(107); + _curvea0[199] = _15678; + uint16_t _15679 = (uint16_t)(107); + _curvea0[200] = _15679; + uint16_t _15680 = (uint16_t)(108); + _curvea0[201] = _15680; + uint16_t _15681 = (uint16_t)(108); + _curvea0[202] = _15681; + uint16_t _15682 = (uint16_t)(108); + _curvea0[203] = _15682; + uint16_t _15683 = (uint16_t)(109); + _curvea0[204] = _15683; + uint16_t _15684 = (uint16_t)(109); + _curvea0[205] = _15684; + uint16_t _15685 = (uint16_t)(109); + _curvea0[206] = _15685; + uint16_t _15686 = (uint16_t)(110); + _curvea0[207] = _15686; + uint16_t _15687 = (uint16_t)(110); + _curvea0[208] = _15687; + uint16_t _15688 = (uint16_t)(111); + _curvea0[209] = _15688; + uint16_t _15689 = (uint16_t)(111); + _curvea0[210] = _15689; + uint16_t _15690 = (uint16_t)(111); + _curvea0[211] = _15690; + uint16_t _15691 = (uint16_t)(112); + _curvea0[212] = _15691; + uint16_t _15692 = (uint16_t)(112); + _curvea0[213] = _15692; + uint16_t _15693 = (uint16_t)(112); + _curvea0[214] = _15693; + uint16_t _15694 = (uint16_t)(113); + _curvea0[215] = _15694; + uint16_t _15695 = (uint16_t)(113); + _curvea0[216] = _15695; + uint16_t _15696 = (uint16_t)(113); + _curvea0[217] = _15696; + uint16_t _15697 = (uint16_t)(114); + _curvea0[218] = _15697; + uint16_t _15698 = (uint16_t)(114); + _curvea0[219] = _15698; + uint16_t _15699 = (uint16_t)(115); + _curvea0[220] = _15699; + uint16_t _15700 = (uint16_t)(115); + _curvea0[221] = _15700; + uint16_t _15701 = (uint16_t)(115); + _curvea0[222] = _15701; + uint16_t _15702 = (uint16_t)(116); + _curvea0[223] = _15702; + uint16_t _15703 = (uint16_t)(116); + _curvea0[224] = _15703; + uint16_t _15704 = (uint16_t)(116); + _curvea0[225] = _15704; + uint16_t _15705 = (uint16_t)(117); + _curvea0[226] = _15705; + uint16_t _15706 = (uint16_t)(117); + _curvea0[227] = _15706; + uint16_t _15707 = (uint16_t)(117); + _curvea0[228] = _15707; + uint16_t _15708 = (uint16_t)(118); + _curvea0[229] = _15708; + uint16_t _15709 = (uint16_t)(118); + _curvea0[230] = _15709; + uint16_t _15710 = (uint16_t)(119); + _curvea0[231] = _15710; + uint16_t _15711 = (uint16_t)(119); + _curvea0[232] = _15711; + uint16_t _15712 = (uint16_t)(119); + _curvea0[233] = _15712; + uint16_t _15713 = (uint16_t)(120); + _curvea0[234] = _15713; + uint16_t _15714 = (uint16_t)(120); + _curvea0[235] = _15714; + uint16_t _15715 = (uint16_t)(120); + _curvea0[236] = _15715; + uint16_t _15716 = (uint16_t)(121); + _curvea0[237] = _15716; + uint16_t _15717 = (uint16_t)(121); + _curvea0[238] = _15717; + uint16_t _15718 = (uint16_t)(121); + _curvea0[239] = _15718; + uint16_t _15719 = (uint16_t)(122); + _curvea0[240] = _15719; + uint16_t _15720 = (uint16_t)(122); + _curvea0[241] = _15720; + uint16_t _15721 = (uint16_t)(123); + _curvea0[242] = _15721; + uint16_t _15722 = (uint16_t)(123); + _curvea0[243] = _15722; + uint16_t _15723 = (uint16_t)(123); + _curvea0[244] = _15723; + uint16_t _15724 = (uint16_t)(124); + _curvea0[245] = _15724; + uint16_t _15725 = (uint16_t)(124); + _curvea0[246] = _15725; + uint16_t _15726 = (uint16_t)(124); + _curvea0[247] = _15726; + uint16_t _15727 = (uint16_t)(125); + _curvea0[248] = _15727; + uint16_t _15728 = (uint16_t)(125); + _curvea0[249] = _15728; + uint16_t _15729 = (uint16_t)(125); + _curvea0[250] = _15729; + uint16_t _15730 = (uint16_t)(126); + _curvea0[251] = _15730; + uint16_t _15731 = (uint16_t)(126); + _curvea0[252] = _15731; + uint16_t _15732 = (uint16_t)(126); + _curvea0[253] = _15732; + uint16_t _15733 = (uint16_t)(127); + _curvea0[254] = _15733; + uint16_t _15734 = (uint16_t)(127); + _curvea0[255] = _15734; + uint16_t _15735 = (uint16_t)(128); + _curvea0[256] = _15735; + uint16_t _15736 = (uint16_t)(128); + _curvea0[257] = _15736; + uint16_t _15737 = (uint16_t)(128); + _curvea0[258] = _15737; + uint16_t _15738 = (uint16_t)(129); + _curvea0[259] = _15738; + uint16_t _15739 = (uint16_t)(129); + _curvea0[260] = _15739; + uint16_t _15740 = (uint16_t)(129); + _curvea0[261] = _15740; + uint16_t _15741 = (uint16_t)(130); + _curvea0[262] = _15741; + uint16_t _15742 = (uint16_t)(130); + _curvea0[263] = _15742; + uint16_t _15743 = (uint16_t)(130); + _curvea0[264] = _15743; + uint16_t _15744 = (uint16_t)(131); + _curvea0[265] = _15744; + uint16_t _15745 = (uint16_t)(131); + _curvea0[266] = _15745; + uint16_t _15746 = (uint16_t)(131); + _curvea0[267] = _15746; + uint16_t _15747 = (uint16_t)(132); + _curvea0[268] = _15747; + uint16_t _15748 = (uint16_t)(132); + _curvea0[269] = _15748; + uint16_t _15749 = (uint16_t)(132); + _curvea0[270] = _15749; + uint16_t _15750 = (uint16_t)(133); + _curvea0[271] = _15750; + uint16_t _15751 = (uint16_t)(133); + _curvea0[272] = _15751; + uint16_t _15752 = (uint16_t)(133); + _curvea0[273] = _15752; + uint16_t _15753 = (uint16_t)(134); + _curvea0[274] = _15753; + uint16_t _15754 = (uint16_t)(134); + _curvea0[275] = _15754; + uint16_t _15755 = (uint16_t)(134); + _curvea0[276] = _15755; + uint16_t _15756 = (uint16_t)(135); + _curvea0[277] = _15756; + uint16_t _15757 = (uint16_t)(135); + _curvea0[278] = _15757; + uint16_t _15758 = (uint16_t)(135); + _curvea0[279] = _15758; + uint16_t _15759 = (uint16_t)(136); + _curvea0[280] = _15759; + uint16_t _15760 = (uint16_t)(136); + _curvea0[281] = _15760; + uint16_t _15761 = (uint16_t)(136); + _curvea0[282] = _15761; + uint16_t _15762 = (uint16_t)(137); + _curvea0[283] = _15762; + uint16_t _15763 = (uint16_t)(137); + _curvea0[284] = _15763; + uint16_t _15764 = (uint16_t)(137); + _curvea0[285] = _15764; + uint16_t _15765 = (uint16_t)(138); + _curvea0[286] = _15765; + uint16_t _15766 = (uint16_t)(138); + _curvea0[287] = _15766; + uint16_t _15767 = (uint16_t)(138); + _curvea0[288] = _15767; + uint16_t _15768 = (uint16_t)(139); + _curvea0[289] = _15768; + uint16_t _15769 = (uint16_t)(139); + _curvea0[290] = _15769; + uint16_t _15770 = (uint16_t)(139); + _curvea0[291] = _15770; + uint16_t _15771 = (uint16_t)(140); + _curvea0[292] = _15771; + uint16_t _15772 = (uint16_t)(140); + _curvea0[293] = _15772; + uint16_t _15773 = (uint16_t)(140); + _curvea0[294] = _15773; + uint16_t _15774 = (uint16_t)(141); + _curvea0[295] = _15774; + uint16_t _15775 = (uint16_t)(141); + _curvea0[296] = _15775; + uint16_t _15776 = (uint16_t)(141); + _curvea0[297] = _15776; + uint16_t _15777 = (uint16_t)(141); + _curvea0[298] = _15777; + uint16_t _15778 = (uint16_t)(142); + _curvea0[299] = _15778; + uint16_t _15779 = (uint16_t)(142); + _curvea0[300] = _15779; + uint16_t _15780 = (uint16_t)(142); + _curvea0[301] = _15780; + uint16_t _15781 = (uint16_t)(143); + _curvea0[302] = _15781; + uint16_t _15782 = (uint16_t)(143); + _curvea0[303] = _15782; + uint16_t _15783 = (uint16_t)(143); + _curvea0[304] = _15783; + uint16_t _15784 = (uint16_t)(144); + _curvea0[305] = _15784; + uint16_t _15785 = (uint16_t)(144); + _curvea0[306] = _15785; + uint16_t _15786 = (uint16_t)(144); + _curvea0[307] = _15786; + uint16_t _15787 = (uint16_t)(145); + _curvea0[308] = _15787; + uint16_t _15788 = (uint16_t)(145); + _curvea0[309] = _15788; + uint16_t _15789 = (uint16_t)(145); + _curvea0[310] = _15789; + uint16_t _15790 = (uint16_t)(145); + _curvea0[311] = _15790; + uint16_t _15791 = (uint16_t)(146); + _curvea0[312] = _15791; + uint16_t _15792 = (uint16_t)(146); + _curvea0[313] = _15792; + uint16_t _15793 = (uint16_t)(146); + _curvea0[314] = _15793; + uint16_t _15794 = (uint16_t)(147); + _curvea0[315] = _15794; + uint16_t _15795 = (uint16_t)(147); + _curvea0[316] = _15795; + uint16_t _15796 = (uint16_t)(147); + _curvea0[317] = _15796; + uint16_t _15797 = (uint16_t)(148); + _curvea0[318] = _15797; + uint16_t _15798 = (uint16_t)(148); + _curvea0[319] = _15798; + uint16_t _15799 = (uint16_t)(148); + _curvea0[320] = _15799; + uint16_t _15800 = (uint16_t)(148); + _curvea0[321] = _15800; + uint16_t _15801 = (uint16_t)(149); + _curvea0[322] = _15801; + uint16_t _15802 = (uint16_t)(149); + _curvea0[323] = _15802; + uint16_t _15803 = (uint16_t)(149); + _curvea0[324] = _15803; + uint16_t _15804 = (uint16_t)(150); + _curvea0[325] = _15804; + uint16_t _15805 = (uint16_t)(150); + _curvea0[326] = _15805; + uint16_t _15806 = (uint16_t)(150); + _curvea0[327] = _15806; + uint16_t _15807 = (uint16_t)(150); + _curvea0[328] = _15807; + uint16_t _15808 = (uint16_t)(151); + _curvea0[329] = _15808; + uint16_t _15809 = (uint16_t)(151); + _curvea0[330] = _15809; + uint16_t _15810 = (uint16_t)(151); + _curvea0[331] = _15810; + uint16_t _15811 = (uint16_t)(152); + _curvea0[332] = _15811; + uint16_t _15812 = (uint16_t)(152); + _curvea0[333] = _15812; + uint16_t _15813 = (uint16_t)(152); + _curvea0[334] = _15813; + uint16_t _15814 = (uint16_t)(152); + _curvea0[335] = _15814; + uint16_t _15815 = (uint16_t)(153); + _curvea0[336] = _15815; + uint16_t _15816 = (uint16_t)(153); + _curvea0[337] = _15816; + uint16_t _15817 = (uint16_t)(153); + _curvea0[338] = _15817; + uint16_t _15818 = (uint16_t)(154); + _curvea0[339] = _15818; + uint16_t _15819 = (uint16_t)(154); + _curvea0[340] = _15819; + uint16_t _15820 = (uint16_t)(154); + _curvea0[341] = _15820; + uint16_t _15821 = (uint16_t)(154); + _curvea0[342] = _15821; + uint16_t _15822 = (uint16_t)(155); + _curvea0[343] = _15822; + uint16_t _15823 = (uint16_t)(155); + _curvea0[344] = _15823; + uint16_t _15824 = (uint16_t)(155); + _curvea0[345] = _15824; + uint16_t _15825 = (uint16_t)(156); + _curvea0[346] = _15825; + uint16_t _15826 = (uint16_t)(156); + _curvea0[347] = _15826; + uint16_t _15827 = (uint16_t)(156); + _curvea0[348] = _15827; + uint16_t _15828 = (uint16_t)(156); + _curvea0[349] = _15828; + uint16_t _15829 = (uint16_t)(157); + _curvea0[350] = _15829; + uint16_t _15830 = (uint16_t)(157); + _curvea0[351] = _15830; + uint16_t _15831 = (uint16_t)(157); + _curvea0[352] = _15831; + uint16_t _15832 = (uint16_t)(157); + _curvea0[353] = _15832; + uint16_t _15833 = (uint16_t)(158); + _curvea0[354] = _15833; + uint16_t _15834 = (uint16_t)(158); + _curvea0[355] = _15834; + uint16_t _15835 = (uint16_t)(158); + _curvea0[356] = _15835; + uint16_t _15836 = (uint16_t)(159); + _curvea0[357] = _15836; + uint16_t _15837 = (uint16_t)(159); + _curvea0[358] = _15837; + uint16_t _15838 = (uint16_t)(159); + _curvea0[359] = _15838; + uint16_t _15839 = (uint16_t)(159); + _curvea0[360] = _15839; + uint16_t _15840 = (uint16_t)(160); + _curvea0[361] = _15840; + uint16_t _15841 = (uint16_t)(160); + _curvea0[362] = _15841; + uint16_t _15842 = (uint16_t)(160); + _curvea0[363] = _15842; + uint16_t _15843 = (uint16_t)(160); + _curvea0[364] = _15843; + uint16_t _15844 = (uint16_t)(161); + _curvea0[365] = _15844; + uint16_t _15845 = (uint16_t)(161); + _curvea0[366] = _15845; + uint16_t _15846 = (uint16_t)(161); + _curvea0[367] = _15846; + uint16_t _15847 = (uint16_t)(161); + _curvea0[368] = _15847; + uint16_t _15848 = (uint16_t)(162); + _curvea0[369] = _15848; + uint16_t _15849 = (uint16_t)(162); + _curvea0[370] = _15849; + uint16_t _15850 = (uint16_t)(162); + _curvea0[371] = _15850; + uint16_t _15851 = (uint16_t)(162); + _curvea0[372] = _15851; + uint16_t _15852 = (uint16_t)(163); + _curvea0[373] = _15852; + uint16_t _15853 = (uint16_t)(163); + _curvea0[374] = _15853; + uint16_t _15854 = (uint16_t)(163); + _curvea0[375] = _15854; + uint16_t _15855 = (uint16_t)(163); + _curvea0[376] = _15855; + uint16_t _15856 = (uint16_t)(164); + _curvea0[377] = _15856; + uint16_t _15857 = (uint16_t)(164); + _curvea0[378] = _15857; + uint16_t _15858 = (uint16_t)(164); + _curvea0[379] = _15858; + uint16_t _15859 = (uint16_t)(164); + _curvea0[380] = _15859; + uint16_t _15860 = (uint16_t)(165); + _curvea0[381] = _15860; + uint16_t _15861 = (uint16_t)(165); + _curvea0[382] = _15861; + uint16_t _15862 = (uint16_t)(165); + _curvea0[383] = _15862; + uint16_t _15863 = (uint16_t)(166); + _curvea0[384] = _15863; + uint16_t _15864 = (uint16_t)(166); + _curvea0[385] = _15864; + uint16_t _15865 = (uint16_t)(166); + _curvea0[386] = _15865; + uint16_t _15866 = (uint16_t)(166); + _curvea0[387] = _15866; + uint16_t _15867 = (uint16_t)(167); + _curvea0[388] = _15867; + uint16_t _15868 = (uint16_t)(167); + _curvea0[389] = _15868; + uint16_t _15869 = (uint16_t)(167); + _curvea0[390] = _15869; + uint16_t _15870 = (uint16_t)(167); + _curvea0[391] = _15870; + uint16_t _15871 = (uint16_t)(167); + _curvea0[392] = _15871; + uint16_t _15872 = (uint16_t)(168); + _curvea0[393] = _15872; + uint16_t _15873 = (uint16_t)(168); + _curvea0[394] = _15873; + uint16_t _15874 = (uint16_t)(168); + _curvea0[395] = _15874; + uint16_t _15875 = (uint16_t)(168); + _curvea0[396] = _15875; + uint16_t _15876 = (uint16_t)(169); + _curvea0[397] = _15876; + uint16_t _15877 = (uint16_t)(169); + _curvea0[398] = _15877; + uint16_t _15878 = (uint16_t)(169); + _curvea0[399] = _15878; + uint16_t _15879 = (uint16_t)(169); + _curvea0[400] = _15879; + uint16_t _15880 = (uint16_t)(170); + _curvea0[401] = _15880; + uint16_t _15881 = (uint16_t)(170); + _curvea0[402] = _15881; + uint16_t _15882 = (uint16_t)(170); + _curvea0[403] = _15882; + uint16_t _15883 = (uint16_t)(170); + _curvea0[404] = _15883; + uint16_t _15884 = (uint16_t)(171); + _curvea0[405] = _15884; + uint16_t _15885 = (uint16_t)(171); + _curvea0[406] = _15885; + uint16_t _15886 = (uint16_t)(171); + _curvea0[407] = _15886; + uint16_t _15887 = (uint16_t)(171); + _curvea0[408] = _15887; + uint16_t _15888 = (uint16_t)(172); + _curvea0[409] = _15888; + uint16_t _15889 = (uint16_t)(172); + _curvea0[410] = _15889; + uint16_t _15890 = (uint16_t)(172); + _curvea0[411] = _15890; + uint16_t _15891 = (uint16_t)(172); + _curvea0[412] = _15891; + uint16_t _15892 = (uint16_t)(173); + _curvea0[413] = _15892; + uint16_t _15893 = (uint16_t)(173); + _curvea0[414] = _15893; + uint16_t _15894 = (uint16_t)(173); + _curvea0[415] = _15894; + uint16_t _15895 = (uint16_t)(173); + _curvea0[416] = _15895; + uint16_t _15896 = (uint16_t)(173); + _curvea0[417] = _15896; + uint16_t _15897 = (uint16_t)(174); + _curvea0[418] = _15897; + uint16_t _15898 = (uint16_t)(174); + _curvea0[419] = _15898; + uint16_t _15899 = (uint16_t)(174); + _curvea0[420] = _15899; + uint16_t _15900 = (uint16_t)(174); + _curvea0[421] = _15900; + uint16_t _15901 = (uint16_t)(175); + _curvea0[422] = _15901; + uint16_t _15902 = (uint16_t)(175); + _curvea0[423] = _15902; + uint16_t _15903 = (uint16_t)(175); + _curvea0[424] = _15903; + uint16_t _15904 = (uint16_t)(175); + _curvea0[425] = _15904; + uint16_t _15905 = (uint16_t)(176); + _curvea0[426] = _15905; + uint16_t _15906 = (uint16_t)(176); + _curvea0[427] = _15906; + uint16_t _15907 = (uint16_t)(176); + _curvea0[428] = _15907; + uint16_t _15908 = (uint16_t)(176); + _curvea0[429] = _15908; + uint16_t _15909 = (uint16_t)(176); + _curvea0[430] = _15909; + uint16_t _15910 = (uint16_t)(177); + _curvea0[431] = _15910; + uint16_t _15911 = (uint16_t)(177); + _curvea0[432] = _15911; + uint16_t _15912 = (uint16_t)(177); + _curvea0[433] = _15912; + uint16_t _15913 = (uint16_t)(177); + _curvea0[434] = _15913; + uint16_t _15914 = (uint16_t)(178); + _curvea0[435] = _15914; + uint16_t _15915 = (uint16_t)(178); + _curvea0[436] = _15915; + uint16_t _15916 = (uint16_t)(178); + _curvea0[437] = _15916; + uint16_t _15917 = (uint16_t)(178); + _curvea0[438] = _15917; + uint16_t _15918 = (uint16_t)(178); + _curvea0[439] = _15918; + uint16_t _15919 = (uint16_t)(179); + _curvea0[440] = _15919; + uint16_t _15920 = (uint16_t)(179); + _curvea0[441] = _15920; + uint16_t _15921 = (uint16_t)(179); + _curvea0[442] = _15921; + uint16_t _15922 = (uint16_t)(179); + _curvea0[443] = _15922; + uint16_t _15923 = (uint16_t)(180); + _curvea0[444] = _15923; + uint16_t _15924 = (uint16_t)(180); + _curvea0[445] = _15924; + uint16_t _15925 = (uint16_t)(180); + _curvea0[446] = _15925; + uint16_t _15926 = (uint16_t)(180); + _curvea0[447] = _15926; + uint16_t _15927 = (uint16_t)(180); + _curvea0[448] = _15927; + uint16_t _15928 = (uint16_t)(181); + _curvea0[449] = _15928; + uint16_t _15929 = (uint16_t)(181); + _curvea0[450] = _15929; + uint16_t _15930 = (uint16_t)(181); + _curvea0[451] = _15930; + uint16_t _15931 = (uint16_t)(181); + _curvea0[452] = _15931; + uint16_t _15932 = (uint16_t)(181); + _curvea0[453] = _15932; + uint16_t _15933 = (uint16_t)(182); + _curvea0[454] = _15933; + uint16_t _15934 = (uint16_t)(182); + _curvea0[455] = _15934; + uint16_t _15935 = (uint16_t)(182); + _curvea0[456] = _15935; + uint16_t _15936 = (uint16_t)(182); + _curvea0[457] = _15936; + uint16_t _15937 = (uint16_t)(183); + _curvea0[458] = _15937; + uint16_t _15938 = (uint16_t)(183); + _curvea0[459] = _15938; + uint16_t _15939 = (uint16_t)(183); + _curvea0[460] = _15939; + uint16_t _15940 = (uint16_t)(183); + _curvea0[461] = _15940; + uint16_t _15941 = (uint16_t)(183); + _curvea0[462] = _15941; + uint16_t _15942 = (uint16_t)(184); + _curvea0[463] = _15942; + uint16_t _15943 = (uint16_t)(184); + _curvea0[464] = _15943; + uint16_t _15944 = (uint16_t)(184); + _curvea0[465] = _15944; + uint16_t _15945 = (uint16_t)(184); + _curvea0[466] = _15945; + uint16_t _15946 = (uint16_t)(184); + _curvea0[467] = _15946; + uint16_t _15947 = (uint16_t)(185); + _curvea0[468] = _15947; + uint16_t _15948 = (uint16_t)(185); + _curvea0[469] = _15948; + uint16_t _15949 = (uint16_t)(185); + _curvea0[470] = _15949; + uint16_t _15950 = (uint16_t)(185); + _curvea0[471] = _15950; + uint16_t _15951 = (uint16_t)(185); + _curvea0[472] = _15951; + uint16_t _15952 = (uint16_t)(186); + _curvea0[473] = _15952; + uint16_t _15953 = (uint16_t)(186); + _curvea0[474] = _15953; + uint16_t _15954 = (uint16_t)(186); + _curvea0[475] = _15954; + uint16_t _15955 = (uint16_t)(186); + _curvea0[476] = _15955; + uint16_t _15956 = (uint16_t)(187); + _curvea0[477] = _15956; + uint16_t _15957 = (uint16_t)(187); + _curvea0[478] = _15957; + uint16_t _15958 = (uint16_t)(187); + _curvea0[479] = _15958; + uint16_t _15959 = (uint16_t)(187); + _curvea0[480] = _15959; + uint16_t _15960 = (uint16_t)(187); + _curvea0[481] = _15960; + uint16_t _15961 = (uint16_t)(188); + _curvea0[482] = _15961; + uint16_t _15962 = (uint16_t)(188); + _curvea0[483] = _15962; + uint16_t _15963 = (uint16_t)(188); + _curvea0[484] = _15963; + uint16_t _15964 = (uint16_t)(188); + _curvea0[485] = _15964; + uint16_t _15965 = (uint16_t)(188); + _curvea0[486] = _15965; + uint16_t _15966 = (uint16_t)(189); + _curvea0[487] = _15966; + uint16_t _15967 = (uint16_t)(189); + _curvea0[488] = _15967; + uint16_t _15968 = (uint16_t)(189); + _curvea0[489] = _15968; + uint16_t _15969 = (uint16_t)(189); + _curvea0[490] = _15969; + uint16_t _15970 = (uint16_t)(189); + _curvea0[491] = _15970; + uint16_t _15971 = (uint16_t)(190); + _curvea0[492] = _15971; + uint16_t _15972 = (uint16_t)(190); + _curvea0[493] = _15972; + uint16_t _15973 = (uint16_t)(190); + _curvea0[494] = _15973; + uint16_t _15974 = (uint16_t)(190); + _curvea0[495] = _15974; + uint16_t _15975 = (uint16_t)(190); + _curvea0[496] = _15975; + uint16_t _15976 = (uint16_t)(190); + _curvea0[497] = _15976; + uint16_t _15977 = (uint16_t)(191); + _curvea0[498] = _15977; + uint16_t _15978 = (uint16_t)(191); + _curvea0[499] = _15978; + uint16_t _15979 = (uint16_t)(191); + _curvea0[500] = _15979; + uint16_t _15980 = (uint16_t)(191); + _curvea0[501] = _15980; + uint16_t _15981 = (uint16_t)(191); + _curvea0[502] = _15981; + uint16_t _15982 = (uint16_t)(192); + _curvea0[503] = _15982; + uint16_t _15983 = (uint16_t)(192); + _curvea0[504] = _15983; + uint16_t _15984 = (uint16_t)(192); + _curvea0[505] = _15984; + uint16_t _15985 = (uint16_t)(192); + _curvea0[506] = _15985; + uint16_t _15986 = (uint16_t)(192); + _curvea0[507] = _15986; + uint16_t _15987 = (uint16_t)(193); + _curvea0[508] = _15987; + uint16_t _15988 = (uint16_t)(193); + _curvea0[509] = _15988; + uint16_t _15989 = (uint16_t)(193); + _curvea0[510] = _15989; + uint16_t _15990 = (uint16_t)(193); + _curvea0[511] = _15990; + uint16_t _15991 = (uint16_t)(193); + _curvea0[512] = _15991; + uint16_t _15992 = (uint16_t)(194); + _curvea0[513] = _15992; + uint16_t _15993 = (uint16_t)(194); + _curvea0[514] = _15993; + uint16_t _15994 = (uint16_t)(194); + _curvea0[515] = _15994; + uint16_t _15995 = (uint16_t)(194); + _curvea0[516] = _15995; + uint16_t _15996 = (uint16_t)(194); + _curvea0[517] = _15996; + uint16_t _15997 = (uint16_t)(195); + _curvea0[518] = _15997; + uint16_t _15998 = (uint16_t)(195); + _curvea0[519] = _15998; + uint16_t _15999 = (uint16_t)(195); + _curvea0[520] = _15999; + uint16_t _16000 = (uint16_t)(195); + _curvea0[521] = _16000; + uint16_t _16001 = (uint16_t)(195); + _curvea0[522] = _16001; + uint16_t _16002 = (uint16_t)(195); + _curvea0[523] = _16002; + uint16_t _16003 = (uint16_t)(196); + _curvea0[524] = _16003; + uint16_t _16004 = (uint16_t)(196); + _curvea0[525] = _16004; + uint16_t _16005 = (uint16_t)(196); + _curvea0[526] = _16005; + uint16_t _16006 = (uint16_t)(196); + _curvea0[527] = _16006; + uint16_t _16007 = (uint16_t)(196); + _curvea0[528] = _16007; + uint16_t _16008 = (uint16_t)(197); + _curvea0[529] = _16008; + uint16_t _16009 = (uint16_t)(197); + _curvea0[530] = _16009; + uint16_t _16010 = (uint16_t)(197); + _curvea0[531] = _16010; + uint16_t _16011 = (uint16_t)(197); + _curvea0[532] = _16011; + uint16_t _16012 = (uint16_t)(197); + _curvea0[533] = _16012; + uint16_t _16013 = (uint16_t)(197); + _curvea0[534] = _16013; + uint16_t _16014 = (uint16_t)(198); + _curvea0[535] = _16014; + uint16_t _16015 = (uint16_t)(198); + _curvea0[536] = _16015; + uint16_t _16016 = (uint16_t)(198); + _curvea0[537] = _16016; + uint16_t _16017 = (uint16_t)(198); + _curvea0[538] = _16017; + uint16_t _16018 = (uint16_t)(198); + _curvea0[539] = _16018; + uint16_t _16019 = (uint16_t)(199); + _curvea0[540] = _16019; + uint16_t _16020 = (uint16_t)(199); + _curvea0[541] = _16020; + uint16_t _16021 = (uint16_t)(199); + _curvea0[542] = _16021; + uint16_t _16022 = (uint16_t)(199); + _curvea0[543] = _16022; + uint16_t _16023 = (uint16_t)(199); + _curvea0[544] = _16023; + uint16_t _16024 = (uint16_t)(199); + _curvea0[545] = _16024; + uint16_t _16025 = (uint16_t)(200); + _curvea0[546] = _16025; + uint16_t _16026 = (uint16_t)(200); + _curvea0[547] = _16026; + uint16_t _16027 = (uint16_t)(200); + _curvea0[548] = _16027; + uint16_t _16028 = (uint16_t)(200); + _curvea0[549] = _16028; + uint16_t _16029 = (uint16_t)(200); + _curvea0[550] = _16029; + uint16_t _16030 = (uint16_t)(200); + _curvea0[551] = _16030; + uint16_t _16031 = (uint16_t)(201); + _curvea0[552] = _16031; + uint16_t _16032 = (uint16_t)(201); + _curvea0[553] = _16032; + uint16_t _16033 = (uint16_t)(201); + _curvea0[554] = _16033; + uint16_t _16034 = (uint16_t)(201); + _curvea0[555] = _16034; + uint16_t _16035 = (uint16_t)(201); + _curvea0[556] = _16035; + uint16_t _16036 = (uint16_t)(202); + _curvea0[557] = _16036; + uint16_t _16037 = (uint16_t)(202); + _curvea0[558] = _16037; + uint16_t _16038 = (uint16_t)(202); + _curvea0[559] = _16038; + uint16_t _16039 = (uint16_t)(202); + _curvea0[560] = _16039; + uint16_t _16040 = (uint16_t)(202); + _curvea0[561] = _16040; + uint16_t _16041 = (uint16_t)(202); + _curvea0[562] = _16041; + uint16_t _16042 = (uint16_t)(203); + _curvea0[563] = _16042; + uint16_t _16043 = (uint16_t)(203); + _curvea0[564] = _16043; + uint16_t _16044 = (uint16_t)(203); + _curvea0[565] = _16044; + uint16_t _16045 = (uint16_t)(203); + _curvea0[566] = _16045; + uint16_t _16046 = (uint16_t)(203); + _curvea0[567] = _16046; + uint16_t _16047 = (uint16_t)(203); + _curvea0[568] = _16047; + uint16_t _16048 = (uint16_t)(204); + _curvea0[569] = _16048; + uint16_t _16049 = (uint16_t)(204); + _curvea0[570] = _16049; + uint16_t _16050 = (uint16_t)(204); + _curvea0[571] = _16050; + uint16_t _16051 = (uint16_t)(204); + _curvea0[572] = _16051; + uint16_t _16052 = (uint16_t)(204); + _curvea0[573] = _16052; + uint16_t _16053 = (uint16_t)(204); + _curvea0[574] = _16053; + uint16_t _16054 = (uint16_t)(205); + _curvea0[575] = _16054; + uint16_t _16055 = (uint16_t)(205); + _curvea0[576] = _16055; + uint16_t _16056 = (uint16_t)(205); + _curvea0[577] = _16056; + uint16_t _16057 = (uint16_t)(205); + _curvea0[578] = _16057; + uint16_t _16058 = (uint16_t)(205); + _curvea0[579] = _16058; + uint16_t _16059 = (uint16_t)(205); + _curvea0[580] = _16059; + uint16_t _16060 = (uint16_t)(206); + _curvea0[581] = _16060; + uint16_t _16061 = (uint16_t)(206); + _curvea0[582] = _16061; + uint16_t _16062 = (uint16_t)(206); + _curvea0[583] = _16062; + uint16_t _16063 = (uint16_t)(206); + _curvea0[584] = _16063; + uint16_t _16064 = (uint16_t)(206); + _curvea0[585] = _16064; + uint16_t _16065 = (uint16_t)(206); + _curvea0[586] = _16065; + uint16_t _16066 = (uint16_t)(207); + _curvea0[587] = _16066; + uint16_t _16067 = (uint16_t)(207); + _curvea0[588] = _16067; + uint16_t _16068 = (uint16_t)(207); + _curvea0[589] = _16068; + uint16_t _16069 = (uint16_t)(207); + _curvea0[590] = _16069; + uint16_t _16070 = (uint16_t)(207); + _curvea0[591] = _16070; + uint16_t _16071 = (uint16_t)(207); + _curvea0[592] = _16071; + uint16_t _16072 = (uint16_t)(208); + _curvea0[593] = _16072; + uint16_t _16073 = (uint16_t)(208); + _curvea0[594] = _16073; + uint16_t _16074 = (uint16_t)(208); + _curvea0[595] = _16074; + uint16_t _16075 = (uint16_t)(208); + _curvea0[596] = _16075; + uint16_t _16076 = (uint16_t)(208); + _curvea0[597] = _16076; + uint16_t _16077 = (uint16_t)(208); + _curvea0[598] = _16077; + uint16_t _16078 = (uint16_t)(209); + _curvea0[599] = _16078; + uint16_t _16079 = (uint16_t)(209); + _curvea0[600] = _16079; + uint16_t _16080 = (uint16_t)(209); + _curvea0[601] = _16080; + uint16_t _16081 = (uint16_t)(209); + _curvea0[602] = _16081; + uint16_t _16082 = (uint16_t)(209); + _curvea0[603] = _16082; + uint16_t _16083 = (uint16_t)(209); + _curvea0[604] = _16083; + uint16_t _16084 = (uint16_t)(209); + _curvea0[605] = _16084; + uint16_t _16085 = (uint16_t)(210); + _curvea0[606] = _16085; + uint16_t _16086 = (uint16_t)(210); + _curvea0[607] = _16086; + uint16_t _16087 = (uint16_t)(210); + _curvea0[608] = _16087; + uint16_t _16088 = (uint16_t)(210); + _curvea0[609] = _16088; + uint16_t _16089 = (uint16_t)(210); + _curvea0[610] = _16089; + uint16_t _16090 = (uint16_t)(210); + _curvea0[611] = _16090; + uint16_t _16091 = (uint16_t)(211); + _curvea0[612] = _16091; + uint16_t _16092 = (uint16_t)(211); + _curvea0[613] = _16092; + uint16_t _16093 = (uint16_t)(211); + _curvea0[614] = _16093; + uint16_t _16094 = (uint16_t)(211); + _curvea0[615] = _16094; + uint16_t _16095 = (uint16_t)(211); + _curvea0[616] = _16095; + uint16_t _16096 = (uint16_t)(211); + _curvea0[617] = _16096; + uint16_t _16097 = (uint16_t)(211); + _curvea0[618] = _16097; + uint16_t _16098 = (uint16_t)(212); + _curvea0[619] = _16098; + uint16_t _16099 = (uint16_t)(212); + _curvea0[620] = _16099; + uint16_t _16100 = (uint16_t)(212); + _curvea0[621] = _16100; + uint16_t _16101 = (uint16_t)(212); + _curvea0[622] = _16101; + uint16_t _16102 = (uint16_t)(212); + _curvea0[623] = _16102; + uint16_t _16103 = (uint16_t)(212); + _curvea0[624] = _16103; + uint16_t _16104 = (uint16_t)(213); + _curvea0[625] = _16104; + uint16_t _16105 = (uint16_t)(213); + _curvea0[626] = _16105; + uint16_t _16106 = (uint16_t)(213); + _curvea0[627] = _16106; + uint16_t _16107 = (uint16_t)(213); + _curvea0[628] = _16107; + uint16_t _16108 = (uint16_t)(213); + _curvea0[629] = _16108; + uint16_t _16109 = (uint16_t)(213); + _curvea0[630] = _16109; + uint16_t _16110 = (uint16_t)(213); + _curvea0[631] = _16110; + uint16_t _16111 = (uint16_t)(214); + _curvea0[632] = _16111; + uint16_t _16112 = (uint16_t)(214); + _curvea0[633] = _16112; + uint16_t _16113 = (uint16_t)(214); + _curvea0[634] = _16113; + uint16_t _16114 = (uint16_t)(214); + _curvea0[635] = _16114; + uint16_t _16115 = (uint16_t)(214); + _curvea0[636] = _16115; + uint16_t _16116 = (uint16_t)(214); + _curvea0[637] = _16116; + uint16_t _16117 = (uint16_t)(214); + _curvea0[638] = _16117; + uint16_t _16118 = (uint16_t)(215); + _curvea0[639] = _16118; + uint16_t _16119 = (uint16_t)(215); + _curvea0[640] = _16119; + uint16_t _16120 = (uint16_t)(215); + _curvea0[641] = _16120; + uint16_t _16121 = (uint16_t)(215); + _curvea0[642] = _16121; + uint16_t _16122 = (uint16_t)(215); + _curvea0[643] = _16122; + uint16_t _16123 = (uint16_t)(215); + _curvea0[644] = _16123; + uint16_t _16124 = (uint16_t)(216); + _curvea0[645] = _16124; + uint16_t _16125 = (uint16_t)(216); + _curvea0[646] = _16125; + uint16_t _16126 = (uint16_t)(216); + _curvea0[647] = _16126; + uint16_t _16127 = (uint16_t)(216); + _curvea0[648] = _16127; + uint16_t _16128 = (uint16_t)(216); + _curvea0[649] = _16128; + uint16_t _16129 = (uint16_t)(216); + _curvea0[650] = _16129; + uint16_t _16130 = (uint16_t)(216); + _curvea0[651] = _16130; + uint16_t _16131 = (uint16_t)(217); + _curvea0[652] = _16131; + uint16_t _16132 = (uint16_t)(217); + _curvea0[653] = _16132; + uint16_t _16133 = (uint16_t)(217); + _curvea0[654] = _16133; + uint16_t _16134 = (uint16_t)(217); + _curvea0[655] = _16134; + uint16_t _16135 = (uint16_t)(217); + _curvea0[656] = _16135; + uint16_t _16136 = (uint16_t)(217); + _curvea0[657] = _16136; + uint16_t _16137 = (uint16_t)(217); + _curvea0[658] = _16137; + uint16_t _16138 = (uint16_t)(218); + _curvea0[659] = _16138; + uint16_t _16139 = (uint16_t)(218); + _curvea0[660] = _16139; + uint16_t _16140 = (uint16_t)(218); + _curvea0[661] = _16140; + uint16_t _16141 = (uint16_t)(218); + _curvea0[662] = _16141; + uint16_t _16142 = (uint16_t)(218); + _curvea0[663] = _16142; + uint16_t _16143 = (uint16_t)(218); + _curvea0[664] = _16143; + uint16_t _16144 = (uint16_t)(218); + _curvea0[665] = _16144; + uint16_t _16145 = (uint16_t)(219); + _curvea0[666] = _16145; + uint16_t _16146 = (uint16_t)(219); + _curvea0[667] = _16146; + uint16_t _16147 = (uint16_t)(219); + _curvea0[668] = _16147; + uint16_t _16148 = (uint16_t)(219); + _curvea0[669] = _16148; + uint16_t _16149 = (uint16_t)(219); + _curvea0[670] = _16149; + uint16_t _16150 = (uint16_t)(219); + _curvea0[671] = _16150; + uint16_t _16151 = (uint16_t)(219); + _curvea0[672] = _16151; + uint16_t _16152 = (uint16_t)(220); + _curvea0[673] = _16152; + uint16_t _16153 = (uint16_t)(220); + _curvea0[674] = _16153; + uint16_t _16154 = (uint16_t)(220); + _curvea0[675] = _16154; + uint16_t _16155 = (uint16_t)(220); + _curvea0[676] = _16155; + uint16_t _16156 = (uint16_t)(220); + _curvea0[677] = _16156; + uint16_t _16157 = (uint16_t)(220); + _curvea0[678] = _16157; + uint16_t _16158 = (uint16_t)(220); + _curvea0[679] = _16158; + uint16_t _16159 = (uint16_t)(220); + _curvea0[680] = _16159; + uint16_t _16160 = (uint16_t)(221); + _curvea0[681] = _16160; + uint16_t _16161 = (uint16_t)(221); + _curvea0[682] = _16161; + uint16_t _16162 = (uint16_t)(221); + _curvea0[683] = _16162; + uint16_t _16163 = (uint16_t)(221); + _curvea0[684] = _16163; + uint16_t _16164 = (uint16_t)(221); + _curvea0[685] = _16164; + uint16_t _16165 = (uint16_t)(221); + _curvea0[686] = _16165; + uint16_t _16166 = (uint16_t)(221); + _curvea0[687] = _16166; + uint16_t _16167 = (uint16_t)(222); + _curvea0[688] = _16167; + uint16_t _16168 = (uint16_t)(222); + _curvea0[689] = _16168; + uint16_t _16169 = (uint16_t)(222); + _curvea0[690] = _16169; + uint16_t _16170 = (uint16_t)(222); + _curvea0[691] = _16170; + uint16_t _16171 = (uint16_t)(222); + _curvea0[692] = _16171; + uint16_t _16172 = (uint16_t)(222); + _curvea0[693] = _16172; + uint16_t _16173 = (uint16_t)(222); + _curvea0[694] = _16173; + uint16_t _16174 = (uint16_t)(223); + _curvea0[695] = _16174; + uint16_t _16175 = (uint16_t)(223); + _curvea0[696] = _16175; + uint16_t _16176 = (uint16_t)(223); + _curvea0[697] = _16176; + uint16_t _16177 = (uint16_t)(223); + _curvea0[698] = _16177; + uint16_t _16178 = (uint16_t)(223); + _curvea0[699] = _16178; + uint16_t _16179 = (uint16_t)(223); + _curvea0[700] = _16179; + uint16_t _16180 = (uint16_t)(223); + _curvea0[701] = _16180; + uint16_t _16181 = (uint16_t)(223); + _curvea0[702] = _16181; + uint16_t _16182 = (uint16_t)(224); + _curvea0[703] = _16182; + uint16_t _16183 = (uint16_t)(224); + _curvea0[704] = _16183; + uint16_t _16184 = (uint16_t)(224); + _curvea0[705] = _16184; + uint16_t _16185 = (uint16_t)(224); + _curvea0[706] = _16185; + uint16_t _16186 = (uint16_t)(224); + _curvea0[707] = _16186; + uint16_t _16187 = (uint16_t)(224); + _curvea0[708] = _16187; + uint16_t _16188 = (uint16_t)(224); + _curvea0[709] = _16188; + uint16_t _16189 = (uint16_t)(224); + _curvea0[710] = _16189; + uint16_t _16190 = (uint16_t)(225); + _curvea0[711] = _16190; + uint16_t _16191 = (uint16_t)(225); + _curvea0[712] = _16191; + uint16_t _16192 = (uint16_t)(225); + _curvea0[713] = _16192; + uint16_t _16193 = (uint16_t)(225); + _curvea0[714] = _16193; + uint16_t _16194 = (uint16_t)(225); + _curvea0[715] = _16194; + uint16_t _16195 = (uint16_t)(225); + _curvea0[716] = _16195; + uint16_t _16196 = (uint16_t)(225); + _curvea0[717] = _16196; + uint16_t _16197 = (uint16_t)(226); + _curvea0[718] = _16197; + uint16_t _16198 = (uint16_t)(226); + _curvea0[719] = _16198; + uint16_t _16199 = (uint16_t)(226); + _curvea0[720] = _16199; + uint16_t _16200 = (uint16_t)(226); + _curvea0[721] = _16200; + uint16_t _16201 = (uint16_t)(226); + _curvea0[722] = _16201; + uint16_t _16202 = (uint16_t)(226); + _curvea0[723] = _16202; + uint16_t _16203 = (uint16_t)(226); + _curvea0[724] = _16203; + uint16_t _16204 = (uint16_t)(226); + _curvea0[725] = _16204; + uint16_t _16205 = (uint16_t)(227); + _curvea0[726] = _16205; + uint16_t _16206 = (uint16_t)(227); + _curvea0[727] = _16206; + uint16_t _16207 = (uint16_t)(227); + _curvea0[728] = _16207; + uint16_t _16208 = (uint16_t)(227); + _curvea0[729] = _16208; + uint16_t _16209 = (uint16_t)(227); + _curvea0[730] = _16209; + uint16_t _16210 = (uint16_t)(227); + _curvea0[731] = _16210; + uint16_t _16211 = (uint16_t)(227); + _curvea0[732] = _16211; + uint16_t _16212 = (uint16_t)(227); + _curvea0[733] = _16212; + uint16_t _16213 = (uint16_t)(228); + _curvea0[734] = _16213; + uint16_t _16214 = (uint16_t)(228); + _curvea0[735] = _16214; + uint16_t _16215 = (uint16_t)(228); + _curvea0[736] = _16215; + uint16_t _16216 = (uint16_t)(228); + _curvea0[737] = _16216; + uint16_t _16217 = (uint16_t)(228); + _curvea0[738] = _16217; + uint16_t _16218 = (uint16_t)(228); + _curvea0[739] = _16218; + uint16_t _16219 = (uint16_t)(228); + _curvea0[740] = _16219; + uint16_t _16220 = (uint16_t)(228); + _curvea0[741] = _16220; + uint16_t _16221 = (uint16_t)(228); + _curvea0[742] = _16221; + uint16_t _16222 = (uint16_t)(229); + _curvea0[743] = _16222; + uint16_t _16223 = (uint16_t)(229); + _curvea0[744] = _16223; + uint16_t _16224 = (uint16_t)(229); + _curvea0[745] = _16224; + uint16_t _16225 = (uint16_t)(229); + _curvea0[746] = _16225; + uint16_t _16226 = (uint16_t)(229); + _curvea0[747] = _16226; + uint16_t _16227 = (uint16_t)(229); + _curvea0[748] = _16227; + uint16_t _16228 = (uint16_t)(229); + _curvea0[749] = _16228; + uint16_t _16229 = (uint16_t)(229); + _curvea0[750] = _16229; + uint16_t _16230 = (uint16_t)(230); + _curvea0[751] = _16230; + uint16_t _16231 = (uint16_t)(230); + _curvea0[752] = _16231; + uint16_t _16232 = (uint16_t)(230); + _curvea0[753] = _16232; + uint16_t _16233 = (uint16_t)(230); + _curvea0[754] = _16233; + uint16_t _16234 = (uint16_t)(230); + _curvea0[755] = _16234; + uint16_t _16235 = (uint16_t)(230); + _curvea0[756] = _16235; + uint16_t _16236 = (uint16_t)(230); + _curvea0[757] = _16236; + uint16_t _16237 = (uint16_t)(230); + _curvea0[758] = _16237; + uint16_t _16238 = (uint16_t)(231); + _curvea0[759] = _16238; + uint16_t _16239 = (uint16_t)(231); + _curvea0[760] = _16239; + uint16_t _16240 = (uint16_t)(231); + _curvea0[761] = _16240; + uint16_t _16241 = (uint16_t)(231); + _curvea0[762] = _16241; + uint16_t _16242 = (uint16_t)(231); + _curvea0[763] = _16242; + uint16_t _16243 = (uint16_t)(231); + _curvea0[764] = _16243; + uint16_t _16244 = (uint16_t)(231); + _curvea0[765] = _16244; + uint16_t _16245 = (uint16_t)(231); + _curvea0[766] = _16245; + uint16_t _16246 = (uint16_t)(231); + _curvea0[767] = _16246; + uint16_t _16247 = (uint16_t)(232); + _curvea0[768] = _16247; + uint16_t _16248 = (uint16_t)(232); + _curvea0[769] = _16248; + uint16_t _16249 = (uint16_t)(232); + _curvea0[770] = _16249; + uint16_t _16250 = (uint16_t)(232); + _curvea0[771] = _16250; + uint16_t _16251 = (uint16_t)(232); + _curvea0[772] = _16251; + uint16_t _16252 = (uint16_t)(232); + _curvea0[773] = _16252; + uint16_t _16253 = (uint16_t)(232); + _curvea0[774] = _16253; + uint16_t _16254 = (uint16_t)(232); + _curvea0[775] = _16254; + uint16_t _16255 = (uint16_t)(233); + _curvea0[776] = _16255; + uint16_t _16256 = (uint16_t)(233); + _curvea0[777] = _16256; + uint16_t _16257 = (uint16_t)(233); + _curvea0[778] = _16257; + uint16_t _16258 = (uint16_t)(233); + _curvea0[779] = _16258; + uint16_t _16259 = (uint16_t)(233); + _curvea0[780] = _16259; + uint16_t _16260 = (uint16_t)(233); + _curvea0[781] = _16260; + uint16_t _16261 = (uint16_t)(233); + _curvea0[782] = _16261; + uint16_t _16262 = (uint16_t)(233); + _curvea0[783] = _16262; + uint16_t _16263 = (uint16_t)(233); + _curvea0[784] = _16263; + uint16_t _16264 = (uint16_t)(234); + _curvea0[785] = _16264; + uint16_t _16265 = (uint16_t)(234); + _curvea0[786] = _16265; + uint16_t _16266 = (uint16_t)(234); + _curvea0[787] = _16266; + uint16_t _16267 = (uint16_t)(234); + _curvea0[788] = _16267; + uint16_t _16268 = (uint16_t)(234); + _curvea0[789] = _16268; + uint16_t _16269 = (uint16_t)(234); + _curvea0[790] = _16269; + uint16_t _16270 = (uint16_t)(234); + _curvea0[791] = _16270; + uint16_t _16271 = (uint16_t)(234); + _curvea0[792] = _16271; + uint16_t _16272 = (uint16_t)(234); + _curvea0[793] = _16272; + uint16_t _16273 = (uint16_t)(235); + _curvea0[794] = _16273; + uint16_t _16274 = (uint16_t)(235); + _curvea0[795] = _16274; + uint16_t _16275 = (uint16_t)(235); + _curvea0[796] = _16275; + uint16_t _16276 = (uint16_t)(235); + _curvea0[797] = _16276; + uint16_t _16277 = (uint16_t)(235); + _curvea0[798] = _16277; + uint16_t _16278 = (uint16_t)(235); + _curvea0[799] = _16278; + uint16_t _16279 = (uint16_t)(235); + _curvea0[800] = _16279; + uint16_t _16280 = (uint16_t)(235); + _curvea0[801] = _16280; + uint16_t _16281 = (uint16_t)(235); + _curvea0[802] = _16281; + uint16_t _16282 = (uint16_t)(236); + _curvea0[803] = _16282; + uint16_t _16283 = (uint16_t)(236); + _curvea0[804] = _16283; + uint16_t _16284 = (uint16_t)(236); + _curvea0[805] = _16284; + uint16_t _16285 = (uint16_t)(236); + _curvea0[806] = _16285; + uint16_t _16286 = (uint16_t)(236); + _curvea0[807] = _16286; + uint16_t _16287 = (uint16_t)(236); + _curvea0[808] = _16287; + uint16_t _16288 = (uint16_t)(236); + _curvea0[809] = _16288; + uint16_t _16289 = (uint16_t)(236); + _curvea0[810] = _16289; + uint16_t _16290 = (uint16_t)(236); + _curvea0[811] = _16290; + uint16_t _16291 = (uint16_t)(237); + _curvea0[812] = _16291; + uint16_t _16292 = (uint16_t)(237); + _curvea0[813] = _16292; + uint16_t _16293 = (uint16_t)(237); + _curvea0[814] = _16293; + uint16_t _16294 = (uint16_t)(237); + _curvea0[815] = _16294; + uint16_t _16295 = (uint16_t)(237); + _curvea0[816] = _16295; + uint16_t _16296 = (uint16_t)(237); + _curvea0[817] = _16296; + uint16_t _16297 = (uint16_t)(237); + _curvea0[818] = _16297; + uint16_t _16298 = (uint16_t)(237); + _curvea0[819] = _16298; + uint16_t _16299 = (uint16_t)(237); + _curvea0[820] = _16299; + uint16_t _16300 = (uint16_t)(237); + _curvea0[821] = _16300; + uint16_t _16301 = (uint16_t)(238); + _curvea0[822] = _16301; + uint16_t _16302 = (uint16_t)(238); + _curvea0[823] = _16302; + uint16_t _16303 = (uint16_t)(238); + _curvea0[824] = _16303; + uint16_t _16304 = (uint16_t)(238); + _curvea0[825] = _16304; + uint16_t _16305 = (uint16_t)(238); + _curvea0[826] = _16305; + uint16_t _16306 = (uint16_t)(238); + _curvea0[827] = _16306; + uint16_t _16307 = (uint16_t)(238); + _curvea0[828] = _16307; + uint16_t _16308 = (uint16_t)(238); + _curvea0[829] = _16308; + uint16_t _16309 = (uint16_t)(238); + _curvea0[830] = _16309; + uint16_t _16310 = (uint16_t)(239); + _curvea0[831] = _16310; + uint16_t _16311 = (uint16_t)(239); + _curvea0[832] = _16311; + uint16_t _16312 = (uint16_t)(239); + _curvea0[833] = _16312; + uint16_t _16313 = (uint16_t)(239); + _curvea0[834] = _16313; + uint16_t _16314 = (uint16_t)(239); + _curvea0[835] = _16314; + uint16_t _16315 = (uint16_t)(239); + _curvea0[836] = _16315; + uint16_t _16316 = (uint16_t)(239); + _curvea0[837] = _16316; + uint16_t _16317 = (uint16_t)(239); + _curvea0[838] = _16317; + uint16_t _16318 = (uint16_t)(239); + _curvea0[839] = _16318; + uint16_t _16319 = (uint16_t)(239); + _curvea0[840] = _16319; + uint16_t _16320 = (uint16_t)(240); + _curvea0[841] = _16320; + uint16_t _16321 = (uint16_t)(240); + _curvea0[842] = _16321; + uint16_t _16322 = (uint16_t)(240); + _curvea0[843] = _16322; + uint16_t _16323 = (uint16_t)(240); + _curvea0[844] = _16323; + uint16_t _16324 = (uint16_t)(240); + _curvea0[845] = _16324; + uint16_t _16325 = (uint16_t)(240); + _curvea0[846] = _16325; + uint16_t _16326 = (uint16_t)(240); + _curvea0[847] = _16326; + uint16_t _16327 = (uint16_t)(240); + _curvea0[848] = _16327; + uint16_t _16328 = (uint16_t)(240); + _curvea0[849] = _16328; + uint16_t _16329 = (uint16_t)(240); + _curvea0[850] = _16329; + uint16_t _16330 = (uint16_t)(241); + _curvea0[851] = _16330; + uint16_t _16331 = (uint16_t)(241); + _curvea0[852] = _16331; + uint16_t _16332 = (uint16_t)(241); + _curvea0[853] = _16332; + uint16_t _16333 = (uint16_t)(241); + _curvea0[854] = _16333; + uint16_t _16334 = (uint16_t)(241); + _curvea0[855] = _16334; + uint16_t _16335 = (uint16_t)(241); + _curvea0[856] = _16335; + uint16_t _16336 = (uint16_t)(241); + _curvea0[857] = _16336; + uint16_t _16337 = (uint16_t)(241); + _curvea0[858] = _16337; + uint16_t _16338 = (uint16_t)(241); + _curvea0[859] = _16338; + uint16_t _16339 = (uint16_t)(241); + _curvea0[860] = _16339; + uint16_t _16340 = (uint16_t)(242); + _curvea0[861] = _16340; + uint16_t _16341 = (uint16_t)(242); + _curvea0[862] = _16341; + uint16_t _16342 = (uint16_t)(242); + _curvea0[863] = _16342; + uint16_t _16343 = (uint16_t)(242); + _curvea0[864] = _16343; + uint16_t _16344 = (uint16_t)(242); + _curvea0[865] = _16344; + uint16_t _16345 = (uint16_t)(242); + _curvea0[866] = _16345; + uint16_t _16346 = (uint16_t)(242); + _curvea0[867] = _16346; + uint16_t _16347 = (uint16_t)(242); + _curvea0[868] = _16347; + uint16_t _16348 = (uint16_t)(242); + _curvea0[869] = _16348; + uint16_t _16349 = (uint16_t)(242); + _curvea0[870] = _16349; + uint16_t _16350 = (uint16_t)(243); + _curvea0[871] = _16350; + uint16_t _16351 = (uint16_t)(243); + _curvea0[872] = _16351; + uint16_t _16352 = (uint16_t)(243); + _curvea0[873] = _16352; + uint16_t _16353 = (uint16_t)(243); + _curvea0[874] = _16353; + uint16_t _16354 = (uint16_t)(243); + _curvea0[875] = _16354; + uint16_t _16355 = (uint16_t)(243); + _curvea0[876] = _16355; + uint16_t _16356 = (uint16_t)(243); + _curvea0[877] = _16356; + uint16_t _16357 = (uint16_t)(243); + _curvea0[878] = _16357; + uint16_t _16358 = (uint16_t)(243); + _curvea0[879] = _16358; + uint16_t _16359 = (uint16_t)(243); + _curvea0[880] = _16359; + uint16_t _16360 = (uint16_t)(244); + _curvea0[881] = _16360; + uint16_t _16361 = (uint16_t)(244); + _curvea0[882] = _16361; + uint16_t _16362 = (uint16_t)(244); + _curvea0[883] = _16362; + uint16_t _16363 = (uint16_t)(244); + _curvea0[884] = _16363; + uint16_t _16364 = (uint16_t)(244); + _curvea0[885] = _16364; + uint16_t _16365 = (uint16_t)(244); + _curvea0[886] = _16365; + uint16_t _16366 = (uint16_t)(244); + _curvea0[887] = _16366; + uint16_t _16367 = (uint16_t)(244); + _curvea0[888] = _16367; + uint16_t _16368 = (uint16_t)(244); + _curvea0[889] = _16368; + uint16_t _16369 = (uint16_t)(244); + _curvea0[890] = _16369; + uint16_t _16370 = (uint16_t)(244); + _curvea0[891] = _16370; + uint16_t _16371 = (uint16_t)(245); + _curvea0[892] = _16371; + uint16_t _16372 = (uint16_t)(245); + _curvea0[893] = _16372; + uint16_t _16373 = (uint16_t)(245); + _curvea0[894] = _16373; + uint16_t _16374 = (uint16_t)(245); + _curvea0[895] = _16374; + uint16_t _16375 = (uint16_t)(245); + _curvea0[896] = _16375; + uint16_t _16376 = (uint16_t)(245); + _curvea0[897] = _16376; + uint16_t _16377 = (uint16_t)(245); + _curvea0[898] = _16377; + uint16_t _16378 = (uint16_t)(245); + _curvea0[899] = _16378; + uint16_t _16379 = (uint16_t)(245); + _curvea0[900] = _16379; + uint16_t _16380 = (uint16_t)(245); + _curvea0[901] = _16380; + uint16_t _16381 = (uint16_t)(245); + _curvea0[902] = _16381; + uint16_t _16382 = (uint16_t)(246); + _curvea0[903] = _16382; + uint16_t _16383 = (uint16_t)(246); + _curvea0[904] = _16383; + uint16_t _16384 = (uint16_t)(246); + _curvea0[905] = _16384; + uint16_t _16385 = (uint16_t)(246); + _curvea0[906] = _16385; + uint16_t _16386 = (uint16_t)(246); + _curvea0[907] = _16386; + uint16_t _16387 = (uint16_t)(246); + _curvea0[908] = _16387; + uint16_t _16388 = (uint16_t)(246); + _curvea0[909] = _16388; + uint16_t _16389 = (uint16_t)(246); + _curvea0[910] = _16389; + uint16_t _16390 = (uint16_t)(246); + _curvea0[911] = _16390; + uint16_t _16391 = (uint16_t)(246); + _curvea0[912] = _16391; + uint16_t _16392 = (uint16_t)(246); + _curvea0[913] = _16392; + uint16_t _16393 = (uint16_t)(247); + _curvea0[914] = _16393; + uint16_t _16394 = (uint16_t)(247); + _curvea0[915] = _16394; + uint16_t _16395 = (uint16_t)(247); + _curvea0[916] = _16395; + uint16_t _16396 = (uint16_t)(247); + _curvea0[917] = _16396; + uint16_t _16397 = (uint16_t)(247); + _curvea0[918] = _16397; + uint16_t _16398 = (uint16_t)(247); + _curvea0[919] = _16398; + uint16_t _16399 = (uint16_t)(247); + _curvea0[920] = _16399; + uint16_t _16400 = (uint16_t)(247); + _curvea0[921] = _16400; + uint16_t _16401 = (uint16_t)(247); + _curvea0[922] = _16401; + uint16_t _16402 = (uint16_t)(247); + _curvea0[923] = _16402; + uint16_t _16403 = (uint16_t)(247); + _curvea0[924] = _16403; + uint16_t _16404 = (uint16_t)(248); + _curvea0[925] = _16404; + uint16_t _16405 = (uint16_t)(248); + _curvea0[926] = _16405; + uint16_t _16406 = (uint16_t)(248); + _curvea0[927] = _16406; + uint16_t _16407 = (uint16_t)(248); + _curvea0[928] = _16407; + uint16_t _16408 = (uint16_t)(248); + _curvea0[929] = _16408; + uint16_t _16409 = (uint16_t)(248); + _curvea0[930] = _16409; + uint16_t _16410 = (uint16_t)(248); + _curvea0[931] = _16410; + uint16_t _16411 = (uint16_t)(248); + _curvea0[932] = _16411; + uint16_t _16412 = (uint16_t)(248); + _curvea0[933] = _16412; + uint16_t _16413 = (uint16_t)(248); + _curvea0[934] = _16413; + uint16_t _16414 = (uint16_t)(248); + _curvea0[935] = _16414; + uint16_t _16415 = (uint16_t)(249); + _curvea0[936] = _16415; + uint16_t _16416 = (uint16_t)(249); + _curvea0[937] = _16416; + uint16_t _16417 = (uint16_t)(249); + _curvea0[938] = _16417; + uint16_t _16418 = (uint16_t)(249); + _curvea0[939] = _16418; + uint16_t _16419 = (uint16_t)(249); + _curvea0[940] = _16419; + uint16_t _16420 = (uint16_t)(249); + _curvea0[941] = _16420; + uint16_t _16421 = (uint16_t)(249); + _curvea0[942] = _16421; + uint16_t _16422 = (uint16_t)(249); + _curvea0[943] = _16422; + uint16_t _16423 = (uint16_t)(249); + _curvea0[944] = _16423; + uint16_t _16424 = (uint16_t)(249); + _curvea0[945] = _16424; + uint16_t _16425 = (uint16_t)(249); + _curvea0[946] = _16425; + uint16_t _16426 = (uint16_t)(249); + _curvea0[947] = _16426; + uint16_t _16427 = (uint16_t)(250); + _curvea0[948] = _16427; + uint16_t _16428 = (uint16_t)(250); + _curvea0[949] = _16428; + uint16_t _16429 = (uint16_t)(250); + _curvea0[950] = _16429; + uint16_t _16430 = (uint16_t)(250); + _curvea0[951] = _16430; + uint16_t _16431 = (uint16_t)(250); + _curvea0[952] = _16431; + uint16_t _16432 = (uint16_t)(250); + _curvea0[953] = _16432; + uint16_t _16433 = (uint16_t)(250); + _curvea0[954] = _16433; + uint16_t _16434 = (uint16_t)(250); + _curvea0[955] = _16434; + uint16_t _16435 = (uint16_t)(250); + _curvea0[956] = _16435; + uint16_t _16436 = (uint16_t)(250); + _curvea0[957] = _16436; + uint16_t _16437 = (uint16_t)(250); + _curvea0[958] = _16437; + uint16_t _16438 = (uint16_t)(250); + _curvea0[959] = _16438; + uint16_t _16439 = (uint16_t)(251); + _curvea0[960] = _16439; + uint16_t _16440 = (uint16_t)(251); + _curvea0[961] = _16440; + uint16_t _16441 = (uint16_t)(251); + _curvea0[962] = _16441; + uint16_t _16442 = (uint16_t)(251); + _curvea0[963] = _16442; + uint16_t _16443 = (uint16_t)(251); + _curvea0[964] = _16443; + uint16_t _16444 = (uint16_t)(251); + _curvea0[965] = _16444; + uint16_t _16445 = (uint16_t)(251); + _curvea0[966] = _16445; + uint16_t _16446 = (uint16_t)(251); + _curvea0[967] = _16446; + uint16_t _16447 = (uint16_t)(251); + _curvea0[968] = _16447; + uint16_t _16448 = (uint16_t)(251); + _curvea0[969] = _16448; + uint16_t _16449 = (uint16_t)(251); + _curvea0[970] = _16449; + uint16_t _16450 = (uint16_t)(251); + _curvea0[971] = _16450; + uint16_t _16451 = (uint16_t)(252); + _curvea0[972] = _16451; + uint16_t _16452 = (uint16_t)(252); + _curvea0[973] = _16452; + uint16_t _16453 = (uint16_t)(252); + _curvea0[974] = _16453; + uint16_t _16454 = (uint16_t)(252); + _curvea0[975] = _16454; + uint16_t _16455 = (uint16_t)(252); + _curvea0[976] = _16455; + uint16_t _16456 = (uint16_t)(252); + _curvea0[977] = _16456; + uint16_t _16457 = (uint16_t)(252); + _curvea0[978] = _16457; + uint16_t _16458 = (uint16_t)(252); + _curvea0[979] = _16458; + uint16_t _16459 = (uint16_t)(252); + _curvea0[980] = _16459; + uint16_t _16460 = (uint16_t)(252); + _curvea0[981] = _16460; + uint16_t _16461 = (uint16_t)(252); + _curvea0[982] = _16461; + uint16_t _16462 = (uint16_t)(252); + _curvea0[983] = _16462; + uint16_t _16463 = (uint16_t)(252); + _curvea0[984] = _16463; + uint16_t _16464 = (uint16_t)(253); + _curvea0[985] = _16464; + uint16_t _16465 = (uint16_t)(253); + _curvea0[986] = _16465; + uint16_t _16466 = (uint16_t)(253); + _curvea0[987] = _16466; + uint16_t _16467 = (uint16_t)(253); + _curvea0[988] = _16467; + uint16_t _16468 = (uint16_t)(253); + _curvea0[989] = _16468; + uint16_t _16469 = (uint16_t)(253); + _curvea0[990] = _16469; + uint16_t _16470 = (uint16_t)(253); + _curvea0[991] = _16470; + uint16_t _16471 = (uint16_t)(253); + _curvea0[992] = _16471; + uint16_t _16472 = (uint16_t)(253); + _curvea0[993] = _16472; + uint16_t _16473 = (uint16_t)(253); + _curvea0[994] = _16473; + uint16_t _16474 = (uint16_t)(253); + _curvea0[995] = _16474; + uint16_t _16475 = (uint16_t)(253); + _curvea0[996] = _16475; + uint16_t _16476 = (uint16_t)(253); + _curvea0[997] = _16476; + uint16_t _16477 = (uint16_t)(254); + _curvea0[998] = _16477; + uint16_t _16478 = (uint16_t)(254); + _curvea0[999] = _16478; + uint16_t _16479 = (uint16_t)(254); + _curvea0[1000] = _16479; + uint16_t _16480 = (uint16_t)(254); + _curvea0[1001] = _16480; + uint16_t _16481 = (uint16_t)(254); + _curvea0[1002] = _16481; + uint16_t _16482 = (uint16_t)(254); + _curvea0[1003] = _16482; + uint16_t _16483 = (uint16_t)(254); + _curvea0[1004] = _16483; + uint16_t _16484 = (uint16_t)(254); + _curvea0[1005] = _16484; + uint16_t _16485 = (uint16_t)(254); + _curvea0[1006] = _16485; + uint16_t _16486 = (uint16_t)(254); + _curvea0[1007] = _16486; + uint16_t _16487 = (uint16_t)(254); + _curvea0[1008] = _16487; + uint16_t _16488 = (uint16_t)(254); + _curvea0[1009] = _16488; + uint16_t _16489 = (uint16_t)(254); + _curvea0[1010] = _16489; + uint16_t _16490 = (uint16_t)(255); + _curvea0[1011] = _16490; + uint16_t _16491 = (uint16_t)(255); + _curvea0[1012] = _16491; + uint16_t _16492 = (uint16_t)(255); + _curvea0[1013] = _16492; + uint16_t _16493 = (uint16_t)(255); + _curvea0[1014] = _16493; + uint16_t _16494 = (uint16_t)(255); + _curvea0[1015] = _16494; + uint16_t _16495 = (uint16_t)(255); + _curvea0[1016] = _16495; + uint16_t _16496 = (uint16_t)(255); + _curvea0[1017] = _16496; + uint16_t _16497 = (uint16_t)(255); + _curvea0[1018] = _16497; + uint16_t _16498 = (uint16_t)(255); + _curvea0[1019] = _16498; + uint16_t _16499 = (uint16_t)(255); + _curvea0[1020] = _16499; + uint16_t _16500 = (uint16_t)(255); + _curvea0[1021] = _16500; + uint16_t _16501 = (uint16_t)(255); + _curvea0[1022] = _16501; + uint16_t _16502 = (uint16_t)(255); + _curvea0[1023] = _16502; + + int16_t _16503 = (int16_t)(1023); + int16_t _16504 = min(_corrected_stencil_12, _16503); + int16_t _16505 = (int16_t)(0); + int16_t _16506 = max(_16504, _16505); + uint16_t _16507 = (uint16_t)(_16506); + int32_t _16508 = (int32_t)(_16507); + uint16_t _16509 = ((const uint16_t *)_curvea0)[_16508]; + return _16509; +} + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 0) +hw_uint<16> hcompute_hw_output_glb_stencil(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_1 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_1; +} + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_1(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_2 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_2; +} + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_2(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_3 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_3; +} + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 0) +hw_uint<16> hcompute_hw_output_glb_stencil_3(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_4 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_4; +} + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_4(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_5 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_5; +} + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_5(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_6 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_6; +} + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 0) +hw_uint<16> hcompute_hw_output_glb_stencil_6(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_7 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_7; +} + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_7(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_8 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_8; +} + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_8(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_9 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_9; +} + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 0) +hw_uint<16> hcompute_hw_output_glb_stencil_9(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_10 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_10; +} + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_10(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_11 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_11; +} + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_11(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_12 = (uint16_t) (curved_stencil.extract<0, 15>()); + + return _curved_stencil_12; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_1 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_1; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_1(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_2 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_2; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_2(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_3 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_3; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_3(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_4 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_4; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_4(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_5 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_5; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_5(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_6 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_6; +} + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_6(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_7 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_7; +} + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_7(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_8 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_8; +} + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_8(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_9 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_9; +} + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_9(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_10 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_10; +} + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_10(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_11 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_11; +} + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_11(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_12 = (uint16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_12; +} + diff --git a/camera_pipeline_extra_buf_compute.h b/camera_pipeline_extra_buf_compute.h new file mode 100644 index 000000000..85e213b03 --- /dev/null +++ b/camera_pipeline_extra_buf_compute.h @@ -0,0 +1,6686 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_s0_x_x, ((hw_input_global_wrapper_s0_y + -4) + 4)) = hw_input.stencil((hw_input_global_wrapper_s0_x_x + ((0*248) + -4)), (hw_input_global_wrapper_s0_y + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -4) + 4)) = hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -4) + 4)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_1 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_1; +} + +//store is: denoised$1.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y + -2) + 2)) = min(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y + -2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y + -2) + 6)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y + -2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y + -2) + 4)), hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 4), ((denoised_1_s0_y + -2) + 4)))))) +hw_uint<16> hcompute_denoised_1_stencil(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_1 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_2 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_3 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_4 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_5 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>(); + + uint16_t _334 = max(_hw_input_global_wrapper_global_wrapper_stencil_4, _hw_input_global_wrapper_global_wrapper_stencil_5); + uint16_t _335 = max(_hw_input_global_wrapper_global_wrapper_stencil_3, _334); + uint16_t _336 = max(_hw_input_global_wrapper_global_wrapper_stencil_2, _335); + uint16_t _337 = min(_hw_input_global_wrapper_global_wrapper_stencil_1, _336); + return _337; +} + +//store is: b_b.stencil(b_b_s0_x_x, ((b_b_s0_y + -1) + 1)) = denoised$1.stencil(((b_b_s0_x_x*2) + 2), (((b_b_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_b_b_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_1 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_1; +} + +//store is: g_gb.stencil(g_gb_s0_x_x, ((g_gb_s0_y + -1) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*2) + 1), (((g_gb_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_g_gb_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_2 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_2; +} + +//store is: g_gr.stencil(g_gr_s0_x_x, ((g_gr_s0_y + -1) + 1)) = denoised$1.stencil((g_gr_s0_x_x*2), (((g_gr_s0_y + -1)*2) + 2)) +hw_uint<16> hcompute_g_gr_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_3 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_3; +} + +//store is: g_b.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)) = select((absd(g_gb.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)), g_gb.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1))) < absd(g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 2)), g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)))), (((g_gb.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)) + g_gb.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1))) + (uint16)1)/(uint16)2), (((g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)) + g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 2))) + (uint16)1)/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_1 = (uint16_t) g_gb_stencil.extract<0, 15>(); + uint16_t _g_gb_stencil_2 = (uint16_t) g_gb_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_1 = (uint16_t) g_gr_stencil.extract<0, 15>(); + uint16_t _g_gr_stencil_2 = (uint16_t) g_gr_stencil.extract<16, 31>(); + + uint16_t _382 = _g_gb_stencil_2 + _g_gb_stencil_1; + uint16_t _383 = (uint16_t)(1); + uint16_t _384 = _382 + _383; + uint16_t _385 = _384 >> _383; + uint16_t _386 = _g_gr_stencil_2 + _g_gr_stencil_1; + uint16_t _387 = _386 + _383; + uint16_t _388 = _387 >> _383; + uint16_t _389 = _g_gb_stencil_2 - _g_gb_stencil_1; + uint16_t _390 = _g_gb_stencil_1 - _g_gb_stencil_2; + bool _391 = _g_gb_stencil_1 < _g_gb_stencil_2; + uint16_t _392 = (uint16_t)(_391 ? _389 : _390); + uint16_t _393 = _392; + uint16_t _394 = _g_gr_stencil_2 - _g_gr_stencil_1; + uint16_t _395 = _g_gr_stencil_1 - _g_gr_stencil_2; + bool _396 = _g_gr_stencil_1 < _g_gr_stencil_2; + uint16_t _397 = (uint16_t)(_396 ? _394 : _395); + uint16_t _398 = _397; + bool _399 = _393 < _398; + uint16_t _400 = (uint16_t)(_399 ? _385 : _388); + return _400; +} + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + (((b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1))) + (uint16)1)/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_1 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_2 = (uint16_t) b_b_stencil.extract<16, 31>(); + + uint16_t _g_b_stencil_1 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_2 = (uint16_t) g_b_stencil.extract<16, 31>(); + + uint16_t _g_gb_stencil_3 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _440 = _b_b_stencil_1 + _b_b_stencil_2; + uint16_t _441 = (uint16_t)(1); + uint16_t _442 = _440 + _441; + uint16_t _443 = _442 >> _441; + uint16_t _444 = _g_gb_stencil_3 + _443; + uint16_t _445 = _g_b_stencil_1 + _g_b_stencil_2; + uint16_t _446 = _445 + _441; + uint16_t _447 = _446 >> _441; + uint16_t _448 = _444 - _447; + return _448; +} + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + (((b_b.stencil(b_gr_s0_x, b_gr_s0_y) + b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil(b_gr_s0_x, b_gr_s0_y) + g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1))) + (uint16)1)/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_3 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_4 = (uint16_t) b_b_stencil.extract<16, 31>(); + + uint16_t _g_b_stencil_3 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_4 = (uint16_t) g_b_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_3 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _475 = _b_b_stencil_3 + _b_b_stencil_4; + uint16_t _476 = (uint16_t)(1); + uint16_t _477 = _475 + _476; + uint16_t _478 = _477 >> _476; + uint16_t _479 = _g_gr_stencil_3 + _478; + uint16_t _480 = _g_b_stencil_3 + _g_b_stencil_4; + uint16_t _481 = _480 + _476; + uint16_t _482 = _481 >> _476; + uint16_t _483 = _479 - _482; + return _483; +} + +//store is: g_r.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y) = select((absd(g_gr.stencil(((g_r_s0_x + -1) + 2), (g_r_s0_y + 1)), g_gr.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1))) < absd(g_gb.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y), g_gb.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)))), (((g_gr.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)) + g_gr.stencil(((g_r_s0_x + -1) + 2), (g_r_s0_y + 1))) + (uint16)1)/(uint16)2), (((g_gb.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)) + g_gb.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y)) + (uint16)1)/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_4 = (uint16_t) g_gb_stencil.extract<0, 15>(); + uint16_t _g_gb_stencil_5 = (uint16_t) g_gb_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_4 = (uint16_t) g_gr_stencil.extract<0, 15>(); + uint16_t _g_gr_stencil_5 = (uint16_t) g_gr_stencil.extract<16, 31>(); + + uint16_t _511 = _g_gr_stencil_5 + _g_gr_stencil_4; + uint16_t _512 = (uint16_t)(1); + uint16_t _513 = _511 + _512; + uint16_t _514 = _513 >> _512; + uint16_t _515 = _g_gb_stencil_5 + _g_gb_stencil_4; + uint16_t _516 = _515 + _512; + uint16_t _517 = _516 >> _512; + uint16_t _518 = _g_gr_stencil_5 - _g_gr_stencil_4; + uint16_t _519 = _g_gr_stencil_4 - _g_gr_stencil_5; + bool _520 = _g_gr_stencil_4 < _g_gr_stencil_5; + uint16_t _521 = (uint16_t)(_520 ? _518 : _519); + uint16_t _522 = _521; + uint16_t _523 = _g_gb_stencil_5 - _g_gb_stencil_4; + uint16_t _524 = _g_gb_stencil_4 - _g_gb_stencil_5; + bool _525 = _g_gb_stencil_4 < _g_gb_stencil_5; + uint16_t _526 = (uint16_t)(_525 ? _523 : _524); + uint16_t _527 = _526; + bool _528 = _522 < _527; + uint16_t _529 = (uint16_t)(_528 ? _514 : _517); + return _529; +} + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + (((b_b.stencil((b_r_s0_x + 1), b_r_s0_y) + b_b.stencil(b_r_s0_x, (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil((b_r_s0_x + 1), b_r_s0_y) + g_b.stencil(b_r_s0_x, (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + (((b_b.stencil(b_r_s0_x, b_r_s0_y) + b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil(b_r_s0_x, b_r_s0_y) + g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1))) + (uint16)1)/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_5 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_6 = (uint16_t) b_b_stencil.extract<16, 31>(); + uint16_t _b_b_stencil_7 = (uint16_t) b_b_stencil.extract<32, 47>(); + uint16_t _b_b_stencil_8 = (uint16_t) b_b_stencil.extract<48, 63>(); + + uint16_t _g_b_stencil_5 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_6 = (uint16_t) g_b_stencil.extract<16, 31>(); + uint16_t _g_b_stencil_7 = (uint16_t) g_b_stencil.extract<32, 47>(); + uint16_t _g_b_stencil_8 = (uint16_t) g_b_stencil.extract<48, 63>(); + + uint16_t _g_r_stencil_1 = (uint16_t) g_r_stencil.extract<0, 15>(); + + uint16_t _569 = _b_b_stencil_6 + _b_b_stencil_5; + uint16_t _570 = (uint16_t)(1); + uint16_t _571 = _569 + _570; + uint16_t _572 = _571 >> _570; + uint16_t _573 = _g_r_stencil_1 + _572; + uint16_t _574 = _g_b_stencil_5 + _g_b_stencil_6; + uint16_t _575 = _574 + _570; + uint16_t _576 = _575 >> _570; + uint16_t _577 = _573 - _576; + uint16_t _578 = _b_b_stencil_8 + _b_b_stencil_7; + uint16_t _579 = _578 + _570; + uint16_t _580 = _579 >> _570; + uint16_t _581 = _g_r_stencil_1 + _580; + uint16_t _582 = _g_b_stencil_7 + _g_b_stencil_8; + uint16_t _583 = _582 + _570; + uint16_t _584 = _583 >> _570; + uint16_t _585 = _581 - _584; + uint16_t _586 = _b_b_stencil_6 - _b_b_stencil_5; + uint16_t _587 = _b_b_stencil_5 - _b_b_stencil_6; + bool _588 = _b_b_stencil_5 < _b_b_stencil_6; + uint16_t _589 = (uint16_t)(_588 ? _586 : _587); + uint16_t _590 = _589; + uint16_t _591 = _b_b_stencil_8 - _b_b_stencil_7; + uint16_t _592 = _b_b_stencil_7 - _b_b_stencil_8; + bool _593 = _b_b_stencil_7 < _b_b_stencil_8; + uint16_t _594 = (uint16_t)(_593 ? _591 : _592); + uint16_t _595 = _594; + bool _596 = _590 < _595; + uint16_t _597 = (uint16_t)(_596 ? _577 : _585); + return _597; +} + +//store is: r_r.stencil(r_r_s0_x_x, r_r_s0_y) = denoised$1.stencil(((r_r_s0_x_x*2) + 1), ((r_r_s0_y*2) + 2)) +hw_uint<16> hcompute_r_r_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_4 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_4; +} + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + (((r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)) + r_r.stencil((r_b_s0_x + 1), r_b_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)) + g_r.stencil((r_b_s0_x + 1), r_b_s0_y)) + (uint16)1)/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + (((r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)) + r_r.stencil(r_b_s0_x, r_b_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)) + g_r.stencil(r_b_s0_x, r_b_s0_y)) + (uint16)1)/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_9 = (uint16_t) g_b_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_2 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_3 = (uint16_t) g_r_stencil.extract<16, 31>(); + uint16_t _g_r_stencil_4 = (uint16_t) g_r_stencil.extract<32, 47>(); + uint16_t _g_r_stencil_5 = (uint16_t) g_r_stencil.extract<48, 63>(); + + uint16_t _r_r_stencil_1 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_2 = (uint16_t) r_r_stencil.extract<16, 31>(); + uint16_t _r_r_stencil_3 = (uint16_t) r_r_stencil.extract<32, 47>(); + uint16_t _r_r_stencil_4 = (uint16_t) r_r_stencil.extract<48, 63>(); + + uint16_t _665 = _r_r_stencil_2 + _r_r_stencil_1; + uint16_t _666 = (uint16_t)(1); + uint16_t _667 = _665 + _666; + uint16_t _668 = _667 >> _666; + uint16_t _669 = _g_b_stencil_9 + _668; + uint16_t _670 = _g_r_stencil_2 + _g_r_stencil_3; + uint16_t _671 = _670 + _666; + uint16_t _672 = _671 >> _666; + uint16_t _673 = _669 - _672; + uint16_t _674 = _r_r_stencil_4 + _r_r_stencil_3; + uint16_t _675 = _674 + _666; + uint16_t _676 = _675 >> _666; + uint16_t _677 = _g_b_stencil_9 + _676; + uint16_t _678 = _g_r_stencil_4 + _g_r_stencil_5; + uint16_t _679 = _678 + _666; + uint16_t _680 = _679 >> _666; + uint16_t _681 = _677 - _680; + uint16_t _682 = _r_r_stencil_2 - _r_r_stencil_1; + uint16_t _683 = _r_r_stencil_1 - _r_r_stencil_2; + bool _684 = _r_r_stencil_1 < _r_r_stencil_2; + uint16_t _685 = (uint16_t)(_684 ? _682 : _683); + uint16_t _686 = _685; + uint16_t _687 = _r_r_stencil_4 - _r_r_stencil_3; + uint16_t _688 = _r_r_stencil_3 - _r_r_stencil_4; + bool _689 = _r_r_stencil_3 < _r_r_stencil_4; + uint16_t _690 = (uint16_t)(_689 ? _687 : _688); + uint16_t _691 = _690; + bool _692 = _686 < _691; + uint16_t _693 = (uint16_t)(_692 ? _673 : _681); + return _693; +} + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + (((r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y)) + (uint16)1)/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_6 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_6 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_7 = (uint16_t) g_r_stencil.extract<16, 31>(); + + uint16_t _r_r_stencil_5 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_6 = (uint16_t) r_r_stencil.extract<16, 31>(); + + uint16_t _756 = _r_r_stencil_5 + _r_r_stencil_6; + uint16_t _757 = (uint16_t)(1); + uint16_t _758 = _756 + _757; + uint16_t _759 = _758 >> _757; + uint16_t _760 = _g_gb_stencil_6 + _759; + uint16_t _761 = _g_r_stencil_6 + _g_r_stencil_7; + uint16_t _762 = _761 + _757; + uint16_t _763 = _762 >> _757; + uint16_t _764 = _760 - _763; + return _764; +} + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + (((r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + r_r.stencil(r_gr_s0_x, r_gr_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil(r_gr_s0_x, r_gr_s0_y) + g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y)) + (uint16)1)/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_6 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_8 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_9 = (uint16_t) g_r_stencil.extract<16, 31>(); + + uint16_t _r_r_stencil_7 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_8 = (uint16_t) r_r_stencil.extract<16, 31>(); + + uint16_t _791 = _r_r_stencil_7 + _r_r_stencil_8; + uint16_t _792 = (uint16_t)(1); + uint16_t _793 = _791 + _792; + uint16_t _794 = _793 >> _792; + uint16_t _795 = _g_gr_stencil_6 + _794; + uint16_t _796 = _g_r_stencil_8 + _g_r_stencil_9; + uint16_t _797 = _796 + _792; + uint16_t _798 = _797 >> _792; + uint16_t _799 = _795 - _798; + return _799; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 0) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), r_gr.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), r_r.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), r_b.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), r_gb.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)))) +hw_uint<16> hcompute_demosaicked_1_stencil(hw_uint<16>& r_b_stencil, hw_uint<16>& r_gb_stencil, hw_uint<16>& r_gr_stencil, hw_uint<16>& r_r_stencil, const int _demosaicked_1_s0_x_x, const int _demosaicked_1_s0_y) { + uint16_t _r_b_stencil_1 = (uint16_t) r_b_stencil.extract<0, 15>(); + + uint16_t _r_gb_stencil_1 = (uint16_t) r_gb_stencil.extract<0, 15>(); + + uint16_t _r_gr_stencil_1 = (uint16_t) r_gr_stencil.extract<0, 15>(); + + uint16_t _r_r_stencil_9 = (uint16_t) r_r_stencil.extract<0, 15>(); + + int32_t _825 = _demosaicked_1_s0_x_x & 1; + bool _826 = _825 == 0; + uint16_t _827 = (uint16_t)(_826 ? _r_gr_stencil_1 : _r_r_stencil_9); + uint16_t _828 = (uint16_t)(_826 ? _r_b_stencil_1 : _r_gb_stencil_1); + int32_t _829 = _demosaicked_1_s0_y & 1; + bool _830 = _829 == 0; + uint16_t _831 = (uint16_t)(_830 ? _827 : _828); + return _831; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 1) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), g_gr.stencil(((demosaicked_1_s0_x_x/2) + 1), ((demosaicked_1_s0_y/2) + 1)), g_r.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), g_b.stencil((demosaicked_1_s0_x_x/2), ((demosaicked_1_s0_y/2) + 1)), g_gb.stencil(((demosaicked_1_s0_x_x/2) + 1), ((demosaicked_1_s0_y/2) + 1)))) +hw_uint<16> hcompute_demosaicked_1_stencil_1(hw_uint<16>& g_b_stencil, hw_uint<16>& g_gb_stencil, hw_uint<16>& g_gr_stencil, hw_uint<16>& g_r_stencil, const int _demosaicked_1_s0_x_x, const int _demosaicked_1_s0_y) { + uint16_t _g_b_stencil_10 = (uint16_t) g_b_stencil.extract<0, 15>(); + + uint16_t _g_gb_stencil_7 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _g_gr_stencil_7 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_10 = (uint16_t) g_r_stencil.extract<0, 15>(); + + int32_t _854 = _demosaicked_1_s0_x_x & 1; + bool _855 = _854 == 0; + uint16_t _856 = (uint16_t)(_855 ? _g_gr_stencil_7 : _g_r_stencil_10); + uint16_t _857 = (uint16_t)(_855 ? _g_b_stencil_10 : _g_gb_stencil_7); + int32_t _858 = _demosaicked_1_s0_y & 1; + bool _859 = _858 == 0; + uint16_t _860 = (uint16_t)(_859 ? _856 : _857); + return _860; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 2) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), b_gr.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), b_r.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), b_b.stencil((demosaicked_1_s0_x_x/2), ((demosaicked_1_s0_y/2) + 1)), b_gb.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)))) +hw_uint<16> hcompute_demosaicked_1_stencil_2(hw_uint<16>& b_b_stencil, hw_uint<16>& b_gb_stencil, hw_uint<16>& b_gr_stencil, hw_uint<16>& b_r_stencil, const int _demosaicked_1_s0_x_x, const int _demosaicked_1_s0_y) { + uint16_t _b_b_stencil_9 = (uint16_t) b_b_stencil.extract<0, 15>(); + + uint16_t _b_gb_stencil_1 = (uint16_t) b_gb_stencil.extract<0, 15>(); + + uint16_t _b_gr_stencil_1 = (uint16_t) b_gr_stencil.extract<0, 15>(); + + uint16_t _b_r_stencil_1 = (uint16_t) b_r_stencil.extract<0, 15>(); + + int32_t _884 = _demosaicked_1_s0_x_x & 1; + bool _885 = _884 == 0; + uint16_t _886 = (uint16_t)(_885 ? _b_gr_stencil_1 : _b_r_stencil_1); + uint16_t _887 = (uint16_t)(_885 ? _b_b_stencil_9 : _b_gb_stencil_1); + int32_t _888 = _demosaicked_1_s0_y & 1; + bool _889 = _888 == 0; + uint16_t _890 = (uint16_t)(_889 ? _886 : _887); + return _890; +} + +//store is: corrected.stencil(corrected_s0_x_x, corrected_s0_y, 0) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, corrected_s0_y, 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, corrected_s0_y, 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, corrected_s0_y, 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_1 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_2 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_3 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _913 = (uint16_t)(10000); + uint16_t _914 = min(_demosaicked_1_stencil_1, _913); + int32_t _915 = (int32_t)(_914); + int32_t _916 = _915 * 549; + int32_t _917 = _916 >> 8; + int16_t _918 = (int16_t)(_917); + uint16_t _919 = min(_demosaicked_1_stencil_2, _913); + int32_t _920 = (int32_t)(_919); + int32_t _921 = _920 * -103; + int32_t _922 = _921 >> 8; + int16_t _923 = (int16_t)(_922); + int16_t _924 = _918 + _923; + uint16_t _925 = min(_demosaicked_1_stencil_3, _913); + int32_t _926 = (int32_t)(_925); + int32_t _927 = _926 * 7; + int32_t _928 = _927 >> 8; + int16_t _929 = (int16_t)(_928); + int16_t _930 = _924 + _929; + int16_t _931 = (int16_t)(-40); + int16_t _932 = _930 + _931; + return _932; +} + +//store is: corrected.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 1) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_1(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_4 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_5 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_6 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _970 = (uint16_t)(10000); + uint16_t _971 = min(_demosaicked_1_stencil_4, _970); + int32_t _972 = (int32_t)(_971); + int32_t _973 = _972 * -96; + int32_t _974 = _973 >> 8; + int16_t _975 = (int16_t)(_974); + uint16_t _976 = min(_demosaicked_1_stencil_5, _970); + int32_t _977 = (int32_t)(_976); + int32_t _978 = _977 * 373; + int32_t _979 = _978 >> 8; + int16_t _980 = (int16_t)(_979); + int16_t _981 = _975 + _980; + uint16_t _982 = min(_demosaicked_1_stencil_6, _970); + int32_t _983 = (int32_t)(_982); + int32_t _984 = _983 * 62; + int32_t _985 = _984 >> 8; + int16_t _986 = (int16_t)(_985); + int16_t _987 = _981 + _986; + int16_t _988 = (int16_t)(-29); + int16_t _989 = _987 + _988; + return _989; +} + +//store is: corrected.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 2) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_2(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_7 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_8 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_9 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1027 = (uint16_t)(10000); + uint16_t _1028 = min(_demosaicked_1_stencil_7, _1027); + int32_t _1029 = (int32_t)(_1028); + int32_t _1030 = _1029 * -31; + int32_t _1031 = _1030 >> 8; + int16_t _1032 = (int16_t)(_1031); + uint16_t _1033 = min(_demosaicked_1_stencil_8, _1027); + int32_t _1034 = (int32_t)(_1033); + int32_t _1035 = _1034 * -261; + int32_t _1036 = _1035 >> 8; + int16_t _1037 = (int16_t)(_1036); + int16_t _1038 = _1032 + _1037; + uint16_t _1039 = min(_demosaicked_1_stencil_9, _1027); + int32_t _1040 = (int32_t)(_1039); + int32_t _1041 = _1040 * 883; + int32_t _1042 = _1041 >> 8; + int16_t _1043 = (int16_t)(_1042); + int16_t _1044 = _1038 + _1043; + int16_t _1045 = (int16_t)(-22); + int16_t _1046 = _1044 + _1045; + return _1046; +} + +//store is: curved.stencil(curved_s0_x_x, curved_s0_y, 0) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, curved_s0_y, 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_1 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _2108 = (uint16_t)(0); + _curvea0[0] = _2108; + uint16_t _2109 = (uint16_t)(4); + _curvea0[1] = _2109; + uint16_t _2110 = (uint16_t)(7); + _curvea0[2] = _2110; + uint16_t _2111 = (uint16_t)(8); + _curvea0[3] = _2111; + uint16_t _2112 = (uint16_t)(10); + _curvea0[4] = _2112; + uint16_t _2113 = (uint16_t)(11); + _curvea0[5] = _2113; + uint16_t _2114 = (uint16_t)(12); + _curvea0[6] = _2114; + uint16_t _2115 = (uint16_t)(13); + _curvea0[7] = _2115; + uint16_t _2116 = (uint16_t)(14); + _curvea0[8] = _2116; + uint16_t _2117 = (uint16_t)(15); + _curvea0[9] = _2117; + uint16_t _2118 = (uint16_t)(16); + _curvea0[10] = _2118; + uint16_t _2119 = (uint16_t)(17); + _curvea0[11] = _2119; + uint16_t _2120 = (uint16_t)(18); + _curvea0[12] = _2120; + uint16_t _2121 = (uint16_t)(19); + _curvea0[13] = _2121; + uint16_t _2122 = (uint16_t)(20); + _curvea0[14] = _2122; + uint16_t _2123 = (uint16_t)(21); + _curvea0[15] = _2123; + uint16_t _2124 = (uint16_t)(22); + _curvea0[16] = _2124; + uint16_t _2125 = (uint16_t)(22); + _curvea0[17] = _2125; + uint16_t _2126 = (uint16_t)(23); + _curvea0[18] = _2126; + uint16_t _2127 = (uint16_t)(24); + _curvea0[19] = _2127; + uint16_t _2128 = (uint16_t)(25); + _curvea0[20] = _2128; + uint16_t _2129 = (uint16_t)(25); + _curvea0[21] = _2129; + uint16_t _2130 = (uint16_t)(26); + _curvea0[22] = _2130; + uint16_t _2131 = (uint16_t)(27); + _curvea0[23] = _2131; + uint16_t _2132 = (uint16_t)(27); + _curvea0[24] = _2132; + uint16_t _2133 = (uint16_t)(28); + _curvea0[25] = _2133; + uint16_t _2134 = (uint16_t)(29); + _curvea0[26] = _2134; + uint16_t _2135 = (uint16_t)(29); + _curvea0[27] = _2135; + uint16_t _2136 = (uint16_t)(30); + _curvea0[28] = _2136; + uint16_t _2137 = (uint16_t)(31); + _curvea0[29] = _2137; + uint16_t _2138 = (uint16_t)(31); + _curvea0[30] = _2138; + uint16_t _2139 = (uint16_t)(32); + _curvea0[31] = _2139; + uint16_t _2140 = (uint16_t)(33); + _curvea0[32] = _2140; + uint16_t _2141 = (uint16_t)(33); + _curvea0[33] = _2141; + uint16_t _2142 = (uint16_t)(34); + _curvea0[34] = _2142; + uint16_t _2143 = (uint16_t)(34); + _curvea0[35] = _2143; + uint16_t _2144 = (uint16_t)(35); + _curvea0[36] = _2144; + uint16_t _2145 = (uint16_t)(36); + _curvea0[37] = _2145; + uint16_t _2146 = (uint16_t)(36); + _curvea0[38] = _2146; + uint16_t _2147 = (uint16_t)(37); + _curvea0[39] = _2147; + uint16_t _2148 = (uint16_t)(37); + _curvea0[40] = _2148; + uint16_t _2149 = (uint16_t)(38); + _curvea0[41] = _2149; + uint16_t _2150 = (uint16_t)(39); + _curvea0[42] = _2150; + uint16_t _2151 = (uint16_t)(39); + _curvea0[43] = _2151; + uint16_t _2152 = (uint16_t)(40); + _curvea0[44] = _2152; + uint16_t _2153 = (uint16_t)(40); + _curvea0[45] = _2153; + uint16_t _2154 = (uint16_t)(41); + _curvea0[46] = _2154; + uint16_t _2155 = (uint16_t)(41); + _curvea0[47] = _2155; + uint16_t _2156 = (uint16_t)(42); + _curvea0[48] = _2156; + uint16_t _2157 = (uint16_t)(42); + _curvea0[49] = _2157; + uint16_t _2158 = (uint16_t)(43); + _curvea0[50] = _2158; + uint16_t _2159 = (uint16_t)(44); + _curvea0[51] = _2159; + uint16_t _2160 = (uint16_t)(44); + _curvea0[52] = _2160; + uint16_t _2161 = (uint16_t)(45); + _curvea0[53] = _2161; + uint16_t _2162 = (uint16_t)(45); + _curvea0[54] = _2162; + uint16_t _2163 = (uint16_t)(46); + _curvea0[55] = _2163; + uint16_t _2164 = (uint16_t)(46); + _curvea0[56] = _2164; + uint16_t _2165 = (uint16_t)(47); + _curvea0[57] = _2165; + uint16_t _2166 = (uint16_t)(47); + _curvea0[58] = _2166; + uint16_t _2167 = (uint16_t)(48); + _curvea0[59] = _2167; + uint16_t _2168 = (uint16_t)(48); + _curvea0[60] = _2168; + uint16_t _2169 = (uint16_t)(49); + _curvea0[61] = _2169; + uint16_t _2170 = (uint16_t)(49); + _curvea0[62] = _2170; + uint16_t _2171 = (uint16_t)(50); + _curvea0[63] = _2171; + uint16_t _2172 = (uint16_t)(50); + _curvea0[64] = _2172; + uint16_t _2173 = (uint16_t)(51); + _curvea0[65] = _2173; + uint16_t _2174 = (uint16_t)(51); + _curvea0[66] = _2174; + uint16_t _2175 = (uint16_t)(52); + _curvea0[67] = _2175; + uint16_t _2176 = (uint16_t)(52); + _curvea0[68] = _2176; + uint16_t _2177 = (uint16_t)(53); + _curvea0[69] = _2177; + uint16_t _2178 = (uint16_t)(53); + _curvea0[70] = _2178; + uint16_t _2179 = (uint16_t)(54); + _curvea0[71] = _2179; + uint16_t _2180 = (uint16_t)(54); + _curvea0[72] = _2180; + uint16_t _2181 = (uint16_t)(55); + _curvea0[73] = _2181; + uint16_t _2182 = (uint16_t)(55); + _curvea0[74] = _2182; + uint16_t _2183 = (uint16_t)(56); + _curvea0[75] = _2183; + uint16_t _2184 = (uint16_t)(56); + _curvea0[76] = _2184; + uint16_t _2185 = (uint16_t)(57); + _curvea0[77] = _2185; + uint16_t _2186 = (uint16_t)(57); + _curvea0[78] = _2186; + uint16_t _2187 = (uint16_t)(58); + _curvea0[79] = _2187; + uint16_t _2188 = (uint16_t)(58); + _curvea0[80] = _2188; + uint16_t _2189 = (uint16_t)(58); + _curvea0[81] = _2189; + uint16_t _2190 = (uint16_t)(59); + _curvea0[82] = _2190; + uint16_t _2191 = (uint16_t)(59); + _curvea0[83] = _2191; + uint16_t _2192 = (uint16_t)(60); + _curvea0[84] = _2192; + uint16_t _2193 = (uint16_t)(60); + _curvea0[85] = _2193; + uint16_t _2194 = (uint16_t)(61); + _curvea0[86] = _2194; + uint16_t _2195 = (uint16_t)(61); + _curvea0[87] = _2195; + uint16_t _2196 = (uint16_t)(62); + _curvea0[88] = _2196; + uint16_t _2197 = (uint16_t)(62); + _curvea0[89] = _2197; + uint16_t _2198 = (uint16_t)(63); + _curvea0[90] = _2198; + uint16_t _2199 = (uint16_t)(63); + _curvea0[91] = _2199; + uint16_t _2200 = (uint16_t)(64); + _curvea0[92] = _2200; + uint16_t _2201 = (uint16_t)(64); + _curvea0[93] = _2201; + uint16_t _2202 = (uint16_t)(64); + _curvea0[94] = _2202; + uint16_t _2203 = (uint16_t)(65); + _curvea0[95] = _2203; + uint16_t _2204 = (uint16_t)(65); + _curvea0[96] = _2204; + uint16_t _2205 = (uint16_t)(66); + _curvea0[97] = _2205; + uint16_t _2206 = (uint16_t)(66); + _curvea0[98] = _2206; + uint16_t _2207 = (uint16_t)(67); + _curvea0[99] = _2207; + uint16_t _2208 = (uint16_t)(67); + _curvea0[100] = _2208; + uint16_t _2209 = (uint16_t)(68); + _curvea0[101] = _2209; + uint16_t _2210 = (uint16_t)(68); + _curvea0[102] = _2210; + uint16_t _2211 = (uint16_t)(68); + _curvea0[103] = _2211; + uint16_t _2212 = (uint16_t)(69); + _curvea0[104] = _2212; + uint16_t _2213 = (uint16_t)(69); + _curvea0[105] = _2213; + uint16_t _2214 = (uint16_t)(70); + _curvea0[106] = _2214; + uint16_t _2215 = (uint16_t)(70); + _curvea0[107] = _2215; + uint16_t _2216 = (uint16_t)(71); + _curvea0[108] = _2216; + uint16_t _2217 = (uint16_t)(71); + _curvea0[109] = _2217; + uint16_t _2218 = (uint16_t)(71); + _curvea0[110] = _2218; + uint16_t _2219 = (uint16_t)(72); + _curvea0[111] = _2219; + uint16_t _2220 = (uint16_t)(72); + _curvea0[112] = _2220; + uint16_t _2221 = (uint16_t)(73); + _curvea0[113] = _2221; + uint16_t _2222 = (uint16_t)(73); + _curvea0[114] = _2222; + uint16_t _2223 = (uint16_t)(74); + _curvea0[115] = _2223; + uint16_t _2224 = (uint16_t)(74); + _curvea0[116] = _2224; + uint16_t _2225 = (uint16_t)(74); + _curvea0[117] = _2225; + uint16_t _2226 = (uint16_t)(75); + _curvea0[118] = _2226; + uint16_t _2227 = (uint16_t)(75); + _curvea0[119] = _2227; + uint16_t _2228 = (uint16_t)(76); + _curvea0[120] = _2228; + uint16_t _2229 = (uint16_t)(76); + _curvea0[121] = _2229; + uint16_t _2230 = (uint16_t)(77); + _curvea0[122] = _2230; + uint16_t _2231 = (uint16_t)(77); + _curvea0[123] = _2231; + uint16_t _2232 = (uint16_t)(77); + _curvea0[124] = _2232; + uint16_t _2233 = (uint16_t)(78); + _curvea0[125] = _2233; + uint16_t _2234 = (uint16_t)(78); + _curvea0[126] = _2234; + uint16_t _2235 = (uint16_t)(79); + _curvea0[127] = _2235; + uint16_t _2236 = (uint16_t)(79); + _curvea0[128] = _2236; + uint16_t _2237 = (uint16_t)(79); + _curvea0[129] = _2237; + uint16_t _2238 = (uint16_t)(80); + _curvea0[130] = _2238; + uint16_t _2239 = (uint16_t)(80); + _curvea0[131] = _2239; + uint16_t _2240 = (uint16_t)(81); + _curvea0[132] = _2240; + uint16_t _2241 = (uint16_t)(81); + _curvea0[133] = _2241; + uint16_t _2242 = (uint16_t)(82); + _curvea0[134] = _2242; + uint16_t _2243 = (uint16_t)(82); + _curvea0[135] = _2243; + uint16_t _2244 = (uint16_t)(82); + _curvea0[136] = _2244; + uint16_t _2245 = (uint16_t)(83); + _curvea0[137] = _2245; + uint16_t _2246 = (uint16_t)(83); + _curvea0[138] = _2246; + uint16_t _2247 = (uint16_t)(84); + _curvea0[139] = _2247; + uint16_t _2248 = (uint16_t)(84); + _curvea0[140] = _2248; + uint16_t _2249 = (uint16_t)(84); + _curvea0[141] = _2249; + uint16_t _2250 = (uint16_t)(85); + _curvea0[142] = _2250; + uint16_t _2251 = (uint16_t)(85); + _curvea0[143] = _2251; + uint16_t _2252 = (uint16_t)(86); + _curvea0[144] = _2252; + uint16_t _2253 = (uint16_t)(86); + _curvea0[145] = _2253; + uint16_t _2254 = (uint16_t)(86); + _curvea0[146] = _2254; + uint16_t _2255 = (uint16_t)(87); + _curvea0[147] = _2255; + uint16_t _2256 = (uint16_t)(87); + _curvea0[148] = _2256; + uint16_t _2257 = (uint16_t)(88); + _curvea0[149] = _2257; + uint16_t _2258 = (uint16_t)(88); + _curvea0[150] = _2258; + uint16_t _2259 = (uint16_t)(88); + _curvea0[151] = _2259; + uint16_t _2260 = (uint16_t)(89); + _curvea0[152] = _2260; + uint16_t _2261 = (uint16_t)(89); + _curvea0[153] = _2261; + uint16_t _2262 = (uint16_t)(90); + _curvea0[154] = _2262; + uint16_t _2263 = (uint16_t)(90); + _curvea0[155] = _2263; + uint16_t _2264 = (uint16_t)(90); + _curvea0[156] = _2264; + uint16_t _2265 = (uint16_t)(91); + _curvea0[157] = _2265; + uint16_t _2266 = (uint16_t)(91); + _curvea0[158] = _2266; + uint16_t _2267 = (uint16_t)(92); + _curvea0[159] = _2267; + uint16_t _2268 = (uint16_t)(92); + _curvea0[160] = _2268; + uint16_t _2269 = (uint16_t)(92); + _curvea0[161] = _2269; + uint16_t _2270 = (uint16_t)(93); + _curvea0[162] = _2270; + uint16_t _2271 = (uint16_t)(93); + _curvea0[163] = _2271; + uint16_t _2272 = (uint16_t)(93); + _curvea0[164] = _2272; + uint16_t _2273 = (uint16_t)(94); + _curvea0[165] = _2273; + uint16_t _2274 = (uint16_t)(94); + _curvea0[166] = _2274; + uint16_t _2275 = (uint16_t)(95); + _curvea0[167] = _2275; + uint16_t _2276 = (uint16_t)(95); + _curvea0[168] = _2276; + uint16_t _2277 = (uint16_t)(95); + _curvea0[169] = _2277; + uint16_t _2278 = (uint16_t)(96); + _curvea0[170] = _2278; + uint16_t _2279 = (uint16_t)(96); + _curvea0[171] = _2279; + uint16_t _2280 = (uint16_t)(97); + _curvea0[172] = _2280; + uint16_t _2281 = (uint16_t)(97); + _curvea0[173] = _2281; + uint16_t _2282 = (uint16_t)(97); + _curvea0[174] = _2282; + uint16_t _2283 = (uint16_t)(98); + _curvea0[175] = _2283; + uint16_t _2284 = (uint16_t)(98); + _curvea0[176] = _2284; + uint16_t _2285 = (uint16_t)(99); + _curvea0[177] = _2285; + uint16_t _2286 = (uint16_t)(99); + _curvea0[178] = _2286; + uint16_t _2287 = (uint16_t)(99); + _curvea0[179] = _2287; + uint16_t _2288 = (uint16_t)(100); + _curvea0[180] = _2288; + uint16_t _2289 = (uint16_t)(100); + _curvea0[181] = _2289; + uint16_t _2290 = (uint16_t)(100); + _curvea0[182] = _2290; + uint16_t _2291 = (uint16_t)(101); + _curvea0[183] = _2291; + uint16_t _2292 = (uint16_t)(101); + _curvea0[184] = _2292; + uint16_t _2293 = (uint16_t)(102); + _curvea0[185] = _2293; + uint16_t _2294 = (uint16_t)(102); + _curvea0[186] = _2294; + uint16_t _2295 = (uint16_t)(102); + _curvea0[187] = _2295; + uint16_t _2296 = (uint16_t)(103); + _curvea0[188] = _2296; + uint16_t _2297 = (uint16_t)(103); + _curvea0[189] = _2297; + uint16_t _2298 = (uint16_t)(103); + _curvea0[190] = _2298; + uint16_t _2299 = (uint16_t)(104); + _curvea0[191] = _2299; + uint16_t _2300 = (uint16_t)(104); + _curvea0[192] = _2300; + uint16_t _2301 = (uint16_t)(105); + _curvea0[193] = _2301; + uint16_t _2302 = (uint16_t)(105); + _curvea0[194] = _2302; + uint16_t _2303 = (uint16_t)(105); + _curvea0[195] = _2303; + uint16_t _2304 = (uint16_t)(106); + _curvea0[196] = _2304; + uint16_t _2305 = (uint16_t)(106); + _curvea0[197] = _2305; + uint16_t _2306 = (uint16_t)(106); + _curvea0[198] = _2306; + uint16_t _2307 = (uint16_t)(107); + _curvea0[199] = _2307; + uint16_t _2308 = (uint16_t)(107); + _curvea0[200] = _2308; + uint16_t _2309 = (uint16_t)(108); + _curvea0[201] = _2309; + uint16_t _2310 = (uint16_t)(108); + _curvea0[202] = _2310; + uint16_t _2311 = (uint16_t)(108); + _curvea0[203] = _2311; + uint16_t _2312 = (uint16_t)(109); + _curvea0[204] = _2312; + uint16_t _2313 = (uint16_t)(109); + _curvea0[205] = _2313; + uint16_t _2314 = (uint16_t)(109); + _curvea0[206] = _2314; + uint16_t _2315 = (uint16_t)(110); + _curvea0[207] = _2315; + uint16_t _2316 = (uint16_t)(110); + _curvea0[208] = _2316; + uint16_t _2317 = (uint16_t)(111); + _curvea0[209] = _2317; + uint16_t _2318 = (uint16_t)(111); + _curvea0[210] = _2318; + uint16_t _2319 = (uint16_t)(111); + _curvea0[211] = _2319; + uint16_t _2320 = (uint16_t)(112); + _curvea0[212] = _2320; + uint16_t _2321 = (uint16_t)(112); + _curvea0[213] = _2321; + uint16_t _2322 = (uint16_t)(112); + _curvea0[214] = _2322; + uint16_t _2323 = (uint16_t)(113); + _curvea0[215] = _2323; + uint16_t _2324 = (uint16_t)(113); + _curvea0[216] = _2324; + uint16_t _2325 = (uint16_t)(113); + _curvea0[217] = _2325; + uint16_t _2326 = (uint16_t)(114); + _curvea0[218] = _2326; + uint16_t _2327 = (uint16_t)(114); + _curvea0[219] = _2327; + uint16_t _2328 = (uint16_t)(115); + _curvea0[220] = _2328; + uint16_t _2329 = (uint16_t)(115); + _curvea0[221] = _2329; + uint16_t _2330 = (uint16_t)(115); + _curvea0[222] = _2330; + uint16_t _2331 = (uint16_t)(116); + _curvea0[223] = _2331; + uint16_t _2332 = (uint16_t)(116); + _curvea0[224] = _2332; + uint16_t _2333 = (uint16_t)(116); + _curvea0[225] = _2333; + uint16_t _2334 = (uint16_t)(117); + _curvea0[226] = _2334; + uint16_t _2335 = (uint16_t)(117); + _curvea0[227] = _2335; + uint16_t _2336 = (uint16_t)(117); + _curvea0[228] = _2336; + uint16_t _2337 = (uint16_t)(118); + _curvea0[229] = _2337; + uint16_t _2338 = (uint16_t)(118); + _curvea0[230] = _2338; + uint16_t _2339 = (uint16_t)(119); + _curvea0[231] = _2339; + uint16_t _2340 = (uint16_t)(119); + _curvea0[232] = _2340; + uint16_t _2341 = (uint16_t)(119); + _curvea0[233] = _2341; + uint16_t _2342 = (uint16_t)(120); + _curvea0[234] = _2342; + uint16_t _2343 = (uint16_t)(120); + _curvea0[235] = _2343; + uint16_t _2344 = (uint16_t)(120); + _curvea0[236] = _2344; + uint16_t _2345 = (uint16_t)(121); + _curvea0[237] = _2345; + uint16_t _2346 = (uint16_t)(121); + _curvea0[238] = _2346; + uint16_t _2347 = (uint16_t)(121); + _curvea0[239] = _2347; + uint16_t _2348 = (uint16_t)(122); + _curvea0[240] = _2348; + uint16_t _2349 = (uint16_t)(122); + _curvea0[241] = _2349; + uint16_t _2350 = (uint16_t)(123); + _curvea0[242] = _2350; + uint16_t _2351 = (uint16_t)(123); + _curvea0[243] = _2351; + uint16_t _2352 = (uint16_t)(123); + _curvea0[244] = _2352; + uint16_t _2353 = (uint16_t)(124); + _curvea0[245] = _2353; + uint16_t _2354 = (uint16_t)(124); + _curvea0[246] = _2354; + uint16_t _2355 = (uint16_t)(124); + _curvea0[247] = _2355; + uint16_t _2356 = (uint16_t)(125); + _curvea0[248] = _2356; + uint16_t _2357 = (uint16_t)(125); + _curvea0[249] = _2357; + uint16_t _2358 = (uint16_t)(125); + _curvea0[250] = _2358; + uint16_t _2359 = (uint16_t)(126); + _curvea0[251] = _2359; + uint16_t _2360 = (uint16_t)(126); + _curvea0[252] = _2360; + uint16_t _2361 = (uint16_t)(126); + _curvea0[253] = _2361; + uint16_t _2362 = (uint16_t)(127); + _curvea0[254] = _2362; + uint16_t _2363 = (uint16_t)(127); + _curvea0[255] = _2363; + uint16_t _2364 = (uint16_t)(128); + _curvea0[256] = _2364; + uint16_t _2365 = (uint16_t)(128); + _curvea0[257] = _2365; + uint16_t _2366 = (uint16_t)(128); + _curvea0[258] = _2366; + uint16_t _2367 = (uint16_t)(129); + _curvea0[259] = _2367; + uint16_t _2368 = (uint16_t)(129); + _curvea0[260] = _2368; + uint16_t _2369 = (uint16_t)(129); + _curvea0[261] = _2369; + uint16_t _2370 = (uint16_t)(130); + _curvea0[262] = _2370; + uint16_t _2371 = (uint16_t)(130); + _curvea0[263] = _2371; + uint16_t _2372 = (uint16_t)(130); + _curvea0[264] = _2372; + uint16_t _2373 = (uint16_t)(131); + _curvea0[265] = _2373; + uint16_t _2374 = (uint16_t)(131); + _curvea0[266] = _2374; + uint16_t _2375 = (uint16_t)(131); + _curvea0[267] = _2375; + uint16_t _2376 = (uint16_t)(132); + _curvea0[268] = _2376; + uint16_t _2377 = (uint16_t)(132); + _curvea0[269] = _2377; + uint16_t _2378 = (uint16_t)(132); + _curvea0[270] = _2378; + uint16_t _2379 = (uint16_t)(133); + _curvea0[271] = _2379; + uint16_t _2380 = (uint16_t)(133); + _curvea0[272] = _2380; + uint16_t _2381 = (uint16_t)(133); + _curvea0[273] = _2381; + uint16_t _2382 = (uint16_t)(134); + _curvea0[274] = _2382; + uint16_t _2383 = (uint16_t)(134); + _curvea0[275] = _2383; + uint16_t _2384 = (uint16_t)(134); + _curvea0[276] = _2384; + uint16_t _2385 = (uint16_t)(135); + _curvea0[277] = _2385; + uint16_t _2386 = (uint16_t)(135); + _curvea0[278] = _2386; + uint16_t _2387 = (uint16_t)(135); + _curvea0[279] = _2387; + uint16_t _2388 = (uint16_t)(136); + _curvea0[280] = _2388; + uint16_t _2389 = (uint16_t)(136); + _curvea0[281] = _2389; + uint16_t _2390 = (uint16_t)(136); + _curvea0[282] = _2390; + uint16_t _2391 = (uint16_t)(137); + _curvea0[283] = _2391; + uint16_t _2392 = (uint16_t)(137); + _curvea0[284] = _2392; + uint16_t _2393 = (uint16_t)(137); + _curvea0[285] = _2393; + uint16_t _2394 = (uint16_t)(138); + _curvea0[286] = _2394; + uint16_t _2395 = (uint16_t)(138); + _curvea0[287] = _2395; + uint16_t _2396 = (uint16_t)(138); + _curvea0[288] = _2396; + uint16_t _2397 = (uint16_t)(139); + _curvea0[289] = _2397; + uint16_t _2398 = (uint16_t)(139); + _curvea0[290] = _2398; + uint16_t _2399 = (uint16_t)(139); + _curvea0[291] = _2399; + uint16_t _2400 = (uint16_t)(140); + _curvea0[292] = _2400; + uint16_t _2401 = (uint16_t)(140); + _curvea0[293] = _2401; + uint16_t _2402 = (uint16_t)(140); + _curvea0[294] = _2402; + uint16_t _2403 = (uint16_t)(141); + _curvea0[295] = _2403; + uint16_t _2404 = (uint16_t)(141); + _curvea0[296] = _2404; + uint16_t _2405 = (uint16_t)(141); + _curvea0[297] = _2405; + uint16_t _2406 = (uint16_t)(141); + _curvea0[298] = _2406; + uint16_t _2407 = (uint16_t)(142); + _curvea0[299] = _2407; + uint16_t _2408 = (uint16_t)(142); + _curvea0[300] = _2408; + uint16_t _2409 = (uint16_t)(142); + _curvea0[301] = _2409; + uint16_t _2410 = (uint16_t)(143); + _curvea0[302] = _2410; + uint16_t _2411 = (uint16_t)(143); + _curvea0[303] = _2411; + uint16_t _2412 = (uint16_t)(143); + _curvea0[304] = _2412; + uint16_t _2413 = (uint16_t)(144); + _curvea0[305] = _2413; + uint16_t _2414 = (uint16_t)(144); + _curvea0[306] = _2414; + uint16_t _2415 = (uint16_t)(144); + _curvea0[307] = _2415; + uint16_t _2416 = (uint16_t)(145); + _curvea0[308] = _2416; + uint16_t _2417 = (uint16_t)(145); + _curvea0[309] = _2417; + uint16_t _2418 = (uint16_t)(145); + _curvea0[310] = _2418; + uint16_t _2419 = (uint16_t)(145); + _curvea0[311] = _2419; + uint16_t _2420 = (uint16_t)(146); + _curvea0[312] = _2420; + uint16_t _2421 = (uint16_t)(146); + _curvea0[313] = _2421; + uint16_t _2422 = (uint16_t)(146); + _curvea0[314] = _2422; + uint16_t _2423 = (uint16_t)(147); + _curvea0[315] = _2423; + uint16_t _2424 = (uint16_t)(147); + _curvea0[316] = _2424; + uint16_t _2425 = (uint16_t)(147); + _curvea0[317] = _2425; + uint16_t _2426 = (uint16_t)(148); + _curvea0[318] = _2426; + uint16_t _2427 = (uint16_t)(148); + _curvea0[319] = _2427; + uint16_t _2428 = (uint16_t)(148); + _curvea0[320] = _2428; + uint16_t _2429 = (uint16_t)(148); + _curvea0[321] = _2429; + uint16_t _2430 = (uint16_t)(149); + _curvea0[322] = _2430; + uint16_t _2431 = (uint16_t)(149); + _curvea0[323] = _2431; + uint16_t _2432 = (uint16_t)(149); + _curvea0[324] = _2432; + uint16_t _2433 = (uint16_t)(150); + _curvea0[325] = _2433; + uint16_t _2434 = (uint16_t)(150); + _curvea0[326] = _2434; + uint16_t _2435 = (uint16_t)(150); + _curvea0[327] = _2435; + uint16_t _2436 = (uint16_t)(150); + _curvea0[328] = _2436; + uint16_t _2437 = (uint16_t)(151); + _curvea0[329] = _2437; + uint16_t _2438 = (uint16_t)(151); + _curvea0[330] = _2438; + uint16_t _2439 = (uint16_t)(151); + _curvea0[331] = _2439; + uint16_t _2440 = (uint16_t)(152); + _curvea0[332] = _2440; + uint16_t _2441 = (uint16_t)(152); + _curvea0[333] = _2441; + uint16_t _2442 = (uint16_t)(152); + _curvea0[334] = _2442; + uint16_t _2443 = (uint16_t)(152); + _curvea0[335] = _2443; + uint16_t _2444 = (uint16_t)(153); + _curvea0[336] = _2444; + uint16_t _2445 = (uint16_t)(153); + _curvea0[337] = _2445; + uint16_t _2446 = (uint16_t)(153); + _curvea0[338] = _2446; + uint16_t _2447 = (uint16_t)(154); + _curvea0[339] = _2447; + uint16_t _2448 = (uint16_t)(154); + _curvea0[340] = _2448; + uint16_t _2449 = (uint16_t)(154); + _curvea0[341] = _2449; + uint16_t _2450 = (uint16_t)(154); + _curvea0[342] = _2450; + uint16_t _2451 = (uint16_t)(155); + _curvea0[343] = _2451; + uint16_t _2452 = (uint16_t)(155); + _curvea0[344] = _2452; + uint16_t _2453 = (uint16_t)(155); + _curvea0[345] = _2453; + uint16_t _2454 = (uint16_t)(156); + _curvea0[346] = _2454; + uint16_t _2455 = (uint16_t)(156); + _curvea0[347] = _2455; + uint16_t _2456 = (uint16_t)(156); + _curvea0[348] = _2456; + uint16_t _2457 = (uint16_t)(156); + _curvea0[349] = _2457; + uint16_t _2458 = (uint16_t)(157); + _curvea0[350] = _2458; + uint16_t _2459 = (uint16_t)(157); + _curvea0[351] = _2459; + uint16_t _2460 = (uint16_t)(157); + _curvea0[352] = _2460; + uint16_t _2461 = (uint16_t)(157); + _curvea0[353] = _2461; + uint16_t _2462 = (uint16_t)(158); + _curvea0[354] = _2462; + uint16_t _2463 = (uint16_t)(158); + _curvea0[355] = _2463; + uint16_t _2464 = (uint16_t)(158); + _curvea0[356] = _2464; + uint16_t _2465 = (uint16_t)(159); + _curvea0[357] = _2465; + uint16_t _2466 = (uint16_t)(159); + _curvea0[358] = _2466; + uint16_t _2467 = (uint16_t)(159); + _curvea0[359] = _2467; + uint16_t _2468 = (uint16_t)(159); + _curvea0[360] = _2468; + uint16_t _2469 = (uint16_t)(160); + _curvea0[361] = _2469; + uint16_t _2470 = (uint16_t)(160); + _curvea0[362] = _2470; + uint16_t _2471 = (uint16_t)(160); + _curvea0[363] = _2471; + uint16_t _2472 = (uint16_t)(160); + _curvea0[364] = _2472; + uint16_t _2473 = (uint16_t)(161); + _curvea0[365] = _2473; + uint16_t _2474 = (uint16_t)(161); + _curvea0[366] = _2474; + uint16_t _2475 = (uint16_t)(161); + _curvea0[367] = _2475; + uint16_t _2476 = (uint16_t)(161); + _curvea0[368] = _2476; + uint16_t _2477 = (uint16_t)(162); + _curvea0[369] = _2477; + uint16_t _2478 = (uint16_t)(162); + _curvea0[370] = _2478; + uint16_t _2479 = (uint16_t)(162); + _curvea0[371] = _2479; + uint16_t _2480 = (uint16_t)(162); + _curvea0[372] = _2480; + uint16_t _2481 = (uint16_t)(163); + _curvea0[373] = _2481; + uint16_t _2482 = (uint16_t)(163); + _curvea0[374] = _2482; + uint16_t _2483 = (uint16_t)(163); + _curvea0[375] = _2483; + uint16_t _2484 = (uint16_t)(163); + _curvea0[376] = _2484; + uint16_t _2485 = (uint16_t)(164); + _curvea0[377] = _2485; + uint16_t _2486 = (uint16_t)(164); + _curvea0[378] = _2486; + uint16_t _2487 = (uint16_t)(164); + _curvea0[379] = _2487; + uint16_t _2488 = (uint16_t)(164); + _curvea0[380] = _2488; + uint16_t _2489 = (uint16_t)(165); + _curvea0[381] = _2489; + uint16_t _2490 = (uint16_t)(165); + _curvea0[382] = _2490; + uint16_t _2491 = (uint16_t)(165); + _curvea0[383] = _2491; + uint16_t _2492 = (uint16_t)(166); + _curvea0[384] = _2492; + uint16_t _2493 = (uint16_t)(166); + _curvea0[385] = _2493; + uint16_t _2494 = (uint16_t)(166); + _curvea0[386] = _2494; + uint16_t _2495 = (uint16_t)(166); + _curvea0[387] = _2495; + uint16_t _2496 = (uint16_t)(167); + _curvea0[388] = _2496; + uint16_t _2497 = (uint16_t)(167); + _curvea0[389] = _2497; + uint16_t _2498 = (uint16_t)(167); + _curvea0[390] = _2498; + uint16_t _2499 = (uint16_t)(167); + _curvea0[391] = _2499; + uint16_t _2500 = (uint16_t)(167); + _curvea0[392] = _2500; + uint16_t _2501 = (uint16_t)(168); + _curvea0[393] = _2501; + uint16_t _2502 = (uint16_t)(168); + _curvea0[394] = _2502; + uint16_t _2503 = (uint16_t)(168); + _curvea0[395] = _2503; + uint16_t _2504 = (uint16_t)(168); + _curvea0[396] = _2504; + uint16_t _2505 = (uint16_t)(169); + _curvea0[397] = _2505; + uint16_t _2506 = (uint16_t)(169); + _curvea0[398] = _2506; + uint16_t _2507 = (uint16_t)(169); + _curvea0[399] = _2507; + uint16_t _2508 = (uint16_t)(169); + _curvea0[400] = _2508; + uint16_t _2509 = (uint16_t)(170); + _curvea0[401] = _2509; + uint16_t _2510 = (uint16_t)(170); + _curvea0[402] = _2510; + uint16_t _2511 = (uint16_t)(170); + _curvea0[403] = _2511; + uint16_t _2512 = (uint16_t)(170); + _curvea0[404] = _2512; + uint16_t _2513 = (uint16_t)(171); + _curvea0[405] = _2513; + uint16_t _2514 = (uint16_t)(171); + _curvea0[406] = _2514; + uint16_t _2515 = (uint16_t)(171); + _curvea0[407] = _2515; + uint16_t _2516 = (uint16_t)(171); + _curvea0[408] = _2516; + uint16_t _2517 = (uint16_t)(172); + _curvea0[409] = _2517; + uint16_t _2518 = (uint16_t)(172); + _curvea0[410] = _2518; + uint16_t _2519 = (uint16_t)(172); + _curvea0[411] = _2519; + uint16_t _2520 = (uint16_t)(172); + _curvea0[412] = _2520; + uint16_t _2521 = (uint16_t)(173); + _curvea0[413] = _2521; + uint16_t _2522 = (uint16_t)(173); + _curvea0[414] = _2522; + uint16_t _2523 = (uint16_t)(173); + _curvea0[415] = _2523; + uint16_t _2524 = (uint16_t)(173); + _curvea0[416] = _2524; + uint16_t _2525 = (uint16_t)(173); + _curvea0[417] = _2525; + uint16_t _2526 = (uint16_t)(174); + _curvea0[418] = _2526; + uint16_t _2527 = (uint16_t)(174); + _curvea0[419] = _2527; + uint16_t _2528 = (uint16_t)(174); + _curvea0[420] = _2528; + uint16_t _2529 = (uint16_t)(174); + _curvea0[421] = _2529; + uint16_t _2530 = (uint16_t)(175); + _curvea0[422] = _2530; + uint16_t _2531 = (uint16_t)(175); + _curvea0[423] = _2531; + uint16_t _2532 = (uint16_t)(175); + _curvea0[424] = _2532; + uint16_t _2533 = (uint16_t)(175); + _curvea0[425] = _2533; + uint16_t _2534 = (uint16_t)(176); + _curvea0[426] = _2534; + uint16_t _2535 = (uint16_t)(176); + _curvea0[427] = _2535; + uint16_t _2536 = (uint16_t)(176); + _curvea0[428] = _2536; + uint16_t _2537 = (uint16_t)(176); + _curvea0[429] = _2537; + uint16_t _2538 = (uint16_t)(176); + _curvea0[430] = _2538; + uint16_t _2539 = (uint16_t)(177); + _curvea0[431] = _2539; + uint16_t _2540 = (uint16_t)(177); + _curvea0[432] = _2540; + uint16_t _2541 = (uint16_t)(177); + _curvea0[433] = _2541; + uint16_t _2542 = (uint16_t)(177); + _curvea0[434] = _2542; + uint16_t _2543 = (uint16_t)(178); + _curvea0[435] = _2543; + uint16_t _2544 = (uint16_t)(178); + _curvea0[436] = _2544; + uint16_t _2545 = (uint16_t)(178); + _curvea0[437] = _2545; + uint16_t _2546 = (uint16_t)(178); + _curvea0[438] = _2546; + uint16_t _2547 = (uint16_t)(178); + _curvea0[439] = _2547; + uint16_t _2548 = (uint16_t)(179); + _curvea0[440] = _2548; + uint16_t _2549 = (uint16_t)(179); + _curvea0[441] = _2549; + uint16_t _2550 = (uint16_t)(179); + _curvea0[442] = _2550; + uint16_t _2551 = (uint16_t)(179); + _curvea0[443] = _2551; + uint16_t _2552 = (uint16_t)(180); + _curvea0[444] = _2552; + uint16_t _2553 = (uint16_t)(180); + _curvea0[445] = _2553; + uint16_t _2554 = (uint16_t)(180); + _curvea0[446] = _2554; + uint16_t _2555 = (uint16_t)(180); + _curvea0[447] = _2555; + uint16_t _2556 = (uint16_t)(180); + _curvea0[448] = _2556; + uint16_t _2557 = (uint16_t)(181); + _curvea0[449] = _2557; + uint16_t _2558 = (uint16_t)(181); + _curvea0[450] = _2558; + uint16_t _2559 = (uint16_t)(181); + _curvea0[451] = _2559; + uint16_t _2560 = (uint16_t)(181); + _curvea0[452] = _2560; + uint16_t _2561 = (uint16_t)(181); + _curvea0[453] = _2561; + uint16_t _2562 = (uint16_t)(182); + _curvea0[454] = _2562; + uint16_t _2563 = (uint16_t)(182); + _curvea0[455] = _2563; + uint16_t _2564 = (uint16_t)(182); + _curvea0[456] = _2564; + uint16_t _2565 = (uint16_t)(182); + _curvea0[457] = _2565; + uint16_t _2566 = (uint16_t)(183); + _curvea0[458] = _2566; + uint16_t _2567 = (uint16_t)(183); + _curvea0[459] = _2567; + uint16_t _2568 = (uint16_t)(183); + _curvea0[460] = _2568; + uint16_t _2569 = (uint16_t)(183); + _curvea0[461] = _2569; + uint16_t _2570 = (uint16_t)(183); + _curvea0[462] = _2570; + uint16_t _2571 = (uint16_t)(184); + _curvea0[463] = _2571; + uint16_t _2572 = (uint16_t)(184); + _curvea0[464] = _2572; + uint16_t _2573 = (uint16_t)(184); + _curvea0[465] = _2573; + uint16_t _2574 = (uint16_t)(184); + _curvea0[466] = _2574; + uint16_t _2575 = (uint16_t)(184); + _curvea0[467] = _2575; + uint16_t _2576 = (uint16_t)(185); + _curvea0[468] = _2576; + uint16_t _2577 = (uint16_t)(185); + _curvea0[469] = _2577; + uint16_t _2578 = (uint16_t)(185); + _curvea0[470] = _2578; + uint16_t _2579 = (uint16_t)(185); + _curvea0[471] = _2579; + uint16_t _2580 = (uint16_t)(185); + _curvea0[472] = _2580; + uint16_t _2581 = (uint16_t)(186); + _curvea0[473] = _2581; + uint16_t _2582 = (uint16_t)(186); + _curvea0[474] = _2582; + uint16_t _2583 = (uint16_t)(186); + _curvea0[475] = _2583; + uint16_t _2584 = (uint16_t)(186); + _curvea0[476] = _2584; + uint16_t _2585 = (uint16_t)(187); + _curvea0[477] = _2585; + uint16_t _2586 = (uint16_t)(187); + _curvea0[478] = _2586; + uint16_t _2587 = (uint16_t)(187); + _curvea0[479] = _2587; + uint16_t _2588 = (uint16_t)(187); + _curvea0[480] = _2588; + uint16_t _2589 = (uint16_t)(187); + _curvea0[481] = _2589; + uint16_t _2590 = (uint16_t)(188); + _curvea0[482] = _2590; + uint16_t _2591 = (uint16_t)(188); + _curvea0[483] = _2591; + uint16_t _2592 = (uint16_t)(188); + _curvea0[484] = _2592; + uint16_t _2593 = (uint16_t)(188); + _curvea0[485] = _2593; + uint16_t _2594 = (uint16_t)(188); + _curvea0[486] = _2594; + uint16_t _2595 = (uint16_t)(189); + _curvea0[487] = _2595; + uint16_t _2596 = (uint16_t)(189); + _curvea0[488] = _2596; + uint16_t _2597 = (uint16_t)(189); + _curvea0[489] = _2597; + uint16_t _2598 = (uint16_t)(189); + _curvea0[490] = _2598; + uint16_t _2599 = (uint16_t)(189); + _curvea0[491] = _2599; + uint16_t _2600 = (uint16_t)(190); + _curvea0[492] = _2600; + uint16_t _2601 = (uint16_t)(190); + _curvea0[493] = _2601; + uint16_t _2602 = (uint16_t)(190); + _curvea0[494] = _2602; + uint16_t _2603 = (uint16_t)(190); + _curvea0[495] = _2603; + uint16_t _2604 = (uint16_t)(190); + _curvea0[496] = _2604; + uint16_t _2605 = (uint16_t)(190); + _curvea0[497] = _2605; + uint16_t _2606 = (uint16_t)(191); + _curvea0[498] = _2606; + uint16_t _2607 = (uint16_t)(191); + _curvea0[499] = _2607; + uint16_t _2608 = (uint16_t)(191); + _curvea0[500] = _2608; + uint16_t _2609 = (uint16_t)(191); + _curvea0[501] = _2609; + uint16_t _2610 = (uint16_t)(191); + _curvea0[502] = _2610; + uint16_t _2611 = (uint16_t)(192); + _curvea0[503] = _2611; + uint16_t _2612 = (uint16_t)(192); + _curvea0[504] = _2612; + uint16_t _2613 = (uint16_t)(192); + _curvea0[505] = _2613; + uint16_t _2614 = (uint16_t)(192); + _curvea0[506] = _2614; + uint16_t _2615 = (uint16_t)(192); + _curvea0[507] = _2615; + uint16_t _2616 = (uint16_t)(193); + _curvea0[508] = _2616; + uint16_t _2617 = (uint16_t)(193); + _curvea0[509] = _2617; + uint16_t _2618 = (uint16_t)(193); + _curvea0[510] = _2618; + uint16_t _2619 = (uint16_t)(193); + _curvea0[511] = _2619; + uint16_t _2620 = (uint16_t)(193); + _curvea0[512] = _2620; + uint16_t _2621 = (uint16_t)(194); + _curvea0[513] = _2621; + uint16_t _2622 = (uint16_t)(194); + _curvea0[514] = _2622; + uint16_t _2623 = (uint16_t)(194); + _curvea0[515] = _2623; + uint16_t _2624 = (uint16_t)(194); + _curvea0[516] = _2624; + uint16_t _2625 = (uint16_t)(194); + _curvea0[517] = _2625; + uint16_t _2626 = (uint16_t)(195); + _curvea0[518] = _2626; + uint16_t _2627 = (uint16_t)(195); + _curvea0[519] = _2627; + uint16_t _2628 = (uint16_t)(195); + _curvea0[520] = _2628; + uint16_t _2629 = (uint16_t)(195); + _curvea0[521] = _2629; + uint16_t _2630 = (uint16_t)(195); + _curvea0[522] = _2630; + uint16_t _2631 = (uint16_t)(195); + _curvea0[523] = _2631; + uint16_t _2632 = (uint16_t)(196); + _curvea0[524] = _2632; + uint16_t _2633 = (uint16_t)(196); + _curvea0[525] = _2633; + uint16_t _2634 = (uint16_t)(196); + _curvea0[526] = _2634; + uint16_t _2635 = (uint16_t)(196); + _curvea0[527] = _2635; + uint16_t _2636 = (uint16_t)(196); + _curvea0[528] = _2636; + uint16_t _2637 = (uint16_t)(197); + _curvea0[529] = _2637; + uint16_t _2638 = (uint16_t)(197); + _curvea0[530] = _2638; + uint16_t _2639 = (uint16_t)(197); + _curvea0[531] = _2639; + uint16_t _2640 = (uint16_t)(197); + _curvea0[532] = _2640; + uint16_t _2641 = (uint16_t)(197); + _curvea0[533] = _2641; + uint16_t _2642 = (uint16_t)(197); + _curvea0[534] = _2642; + uint16_t _2643 = (uint16_t)(198); + _curvea0[535] = _2643; + uint16_t _2644 = (uint16_t)(198); + _curvea0[536] = _2644; + uint16_t _2645 = (uint16_t)(198); + _curvea0[537] = _2645; + uint16_t _2646 = (uint16_t)(198); + _curvea0[538] = _2646; + uint16_t _2647 = (uint16_t)(198); + _curvea0[539] = _2647; + uint16_t _2648 = (uint16_t)(199); + _curvea0[540] = _2648; + uint16_t _2649 = (uint16_t)(199); + _curvea0[541] = _2649; + uint16_t _2650 = (uint16_t)(199); + _curvea0[542] = _2650; + uint16_t _2651 = (uint16_t)(199); + _curvea0[543] = _2651; + uint16_t _2652 = (uint16_t)(199); + _curvea0[544] = _2652; + uint16_t _2653 = (uint16_t)(199); + _curvea0[545] = _2653; + uint16_t _2654 = (uint16_t)(200); + _curvea0[546] = _2654; + uint16_t _2655 = (uint16_t)(200); + _curvea0[547] = _2655; + uint16_t _2656 = (uint16_t)(200); + _curvea0[548] = _2656; + uint16_t _2657 = (uint16_t)(200); + _curvea0[549] = _2657; + uint16_t _2658 = (uint16_t)(200); + _curvea0[550] = _2658; + uint16_t _2659 = (uint16_t)(200); + _curvea0[551] = _2659; + uint16_t _2660 = (uint16_t)(201); + _curvea0[552] = _2660; + uint16_t _2661 = (uint16_t)(201); + _curvea0[553] = _2661; + uint16_t _2662 = (uint16_t)(201); + _curvea0[554] = _2662; + uint16_t _2663 = (uint16_t)(201); + _curvea0[555] = _2663; + uint16_t _2664 = (uint16_t)(201); + _curvea0[556] = _2664; + uint16_t _2665 = (uint16_t)(202); + _curvea0[557] = _2665; + uint16_t _2666 = (uint16_t)(202); + _curvea0[558] = _2666; + uint16_t _2667 = (uint16_t)(202); + _curvea0[559] = _2667; + uint16_t _2668 = (uint16_t)(202); + _curvea0[560] = _2668; + uint16_t _2669 = (uint16_t)(202); + _curvea0[561] = _2669; + uint16_t _2670 = (uint16_t)(202); + _curvea0[562] = _2670; + uint16_t _2671 = (uint16_t)(203); + _curvea0[563] = _2671; + uint16_t _2672 = (uint16_t)(203); + _curvea0[564] = _2672; + uint16_t _2673 = (uint16_t)(203); + _curvea0[565] = _2673; + uint16_t _2674 = (uint16_t)(203); + _curvea0[566] = _2674; + uint16_t _2675 = (uint16_t)(203); + _curvea0[567] = _2675; + uint16_t _2676 = (uint16_t)(203); + _curvea0[568] = _2676; + uint16_t _2677 = (uint16_t)(204); + _curvea0[569] = _2677; + uint16_t _2678 = (uint16_t)(204); + _curvea0[570] = _2678; + uint16_t _2679 = (uint16_t)(204); + _curvea0[571] = _2679; + uint16_t _2680 = (uint16_t)(204); + _curvea0[572] = _2680; + uint16_t _2681 = (uint16_t)(204); + _curvea0[573] = _2681; + uint16_t _2682 = (uint16_t)(204); + _curvea0[574] = _2682; + uint16_t _2683 = (uint16_t)(205); + _curvea0[575] = _2683; + uint16_t _2684 = (uint16_t)(205); + _curvea0[576] = _2684; + uint16_t _2685 = (uint16_t)(205); + _curvea0[577] = _2685; + uint16_t _2686 = (uint16_t)(205); + _curvea0[578] = _2686; + uint16_t _2687 = (uint16_t)(205); + _curvea0[579] = _2687; + uint16_t _2688 = (uint16_t)(205); + _curvea0[580] = _2688; + uint16_t _2689 = (uint16_t)(206); + _curvea0[581] = _2689; + uint16_t _2690 = (uint16_t)(206); + _curvea0[582] = _2690; + uint16_t _2691 = (uint16_t)(206); + _curvea0[583] = _2691; + uint16_t _2692 = (uint16_t)(206); + _curvea0[584] = _2692; + uint16_t _2693 = (uint16_t)(206); + _curvea0[585] = _2693; + uint16_t _2694 = (uint16_t)(206); + _curvea0[586] = _2694; + uint16_t _2695 = (uint16_t)(207); + _curvea0[587] = _2695; + uint16_t _2696 = (uint16_t)(207); + _curvea0[588] = _2696; + uint16_t _2697 = (uint16_t)(207); + _curvea0[589] = _2697; + uint16_t _2698 = (uint16_t)(207); + _curvea0[590] = _2698; + uint16_t _2699 = (uint16_t)(207); + _curvea0[591] = _2699; + uint16_t _2700 = (uint16_t)(207); + _curvea0[592] = _2700; + uint16_t _2701 = (uint16_t)(208); + _curvea0[593] = _2701; + uint16_t _2702 = (uint16_t)(208); + _curvea0[594] = _2702; + uint16_t _2703 = (uint16_t)(208); + _curvea0[595] = _2703; + uint16_t _2704 = (uint16_t)(208); + _curvea0[596] = _2704; + uint16_t _2705 = (uint16_t)(208); + _curvea0[597] = _2705; + uint16_t _2706 = (uint16_t)(208); + _curvea0[598] = _2706; + uint16_t _2707 = (uint16_t)(209); + _curvea0[599] = _2707; + uint16_t _2708 = (uint16_t)(209); + _curvea0[600] = _2708; + uint16_t _2709 = (uint16_t)(209); + _curvea0[601] = _2709; + uint16_t _2710 = (uint16_t)(209); + _curvea0[602] = _2710; + uint16_t _2711 = (uint16_t)(209); + _curvea0[603] = _2711; + uint16_t _2712 = (uint16_t)(209); + _curvea0[604] = _2712; + uint16_t _2713 = (uint16_t)(209); + _curvea0[605] = _2713; + uint16_t _2714 = (uint16_t)(210); + _curvea0[606] = _2714; + uint16_t _2715 = (uint16_t)(210); + _curvea0[607] = _2715; + uint16_t _2716 = (uint16_t)(210); + _curvea0[608] = _2716; + uint16_t _2717 = (uint16_t)(210); + _curvea0[609] = _2717; + uint16_t _2718 = (uint16_t)(210); + _curvea0[610] = _2718; + uint16_t _2719 = (uint16_t)(210); + _curvea0[611] = _2719; + uint16_t _2720 = (uint16_t)(211); + _curvea0[612] = _2720; + uint16_t _2721 = (uint16_t)(211); + _curvea0[613] = _2721; + uint16_t _2722 = (uint16_t)(211); + _curvea0[614] = _2722; + uint16_t _2723 = (uint16_t)(211); + _curvea0[615] = _2723; + uint16_t _2724 = (uint16_t)(211); + _curvea0[616] = _2724; + uint16_t _2725 = (uint16_t)(211); + _curvea0[617] = _2725; + uint16_t _2726 = (uint16_t)(211); + _curvea0[618] = _2726; + uint16_t _2727 = (uint16_t)(212); + _curvea0[619] = _2727; + uint16_t _2728 = (uint16_t)(212); + _curvea0[620] = _2728; + uint16_t _2729 = (uint16_t)(212); + _curvea0[621] = _2729; + uint16_t _2730 = (uint16_t)(212); + _curvea0[622] = _2730; + uint16_t _2731 = (uint16_t)(212); + _curvea0[623] = _2731; + uint16_t _2732 = (uint16_t)(212); + _curvea0[624] = _2732; + uint16_t _2733 = (uint16_t)(213); + _curvea0[625] = _2733; + uint16_t _2734 = (uint16_t)(213); + _curvea0[626] = _2734; + uint16_t _2735 = (uint16_t)(213); + _curvea0[627] = _2735; + uint16_t _2736 = (uint16_t)(213); + _curvea0[628] = _2736; + uint16_t _2737 = (uint16_t)(213); + _curvea0[629] = _2737; + uint16_t _2738 = (uint16_t)(213); + _curvea0[630] = _2738; + uint16_t _2739 = (uint16_t)(213); + _curvea0[631] = _2739; + uint16_t _2740 = (uint16_t)(214); + _curvea0[632] = _2740; + uint16_t _2741 = (uint16_t)(214); + _curvea0[633] = _2741; + uint16_t _2742 = (uint16_t)(214); + _curvea0[634] = _2742; + uint16_t _2743 = (uint16_t)(214); + _curvea0[635] = _2743; + uint16_t _2744 = (uint16_t)(214); + _curvea0[636] = _2744; + uint16_t _2745 = (uint16_t)(214); + _curvea0[637] = _2745; + uint16_t _2746 = (uint16_t)(214); + _curvea0[638] = _2746; + uint16_t _2747 = (uint16_t)(215); + _curvea0[639] = _2747; + uint16_t _2748 = (uint16_t)(215); + _curvea0[640] = _2748; + uint16_t _2749 = (uint16_t)(215); + _curvea0[641] = _2749; + uint16_t _2750 = (uint16_t)(215); + _curvea0[642] = _2750; + uint16_t _2751 = (uint16_t)(215); + _curvea0[643] = _2751; + uint16_t _2752 = (uint16_t)(215); + _curvea0[644] = _2752; + uint16_t _2753 = (uint16_t)(216); + _curvea0[645] = _2753; + uint16_t _2754 = (uint16_t)(216); + _curvea0[646] = _2754; + uint16_t _2755 = (uint16_t)(216); + _curvea0[647] = _2755; + uint16_t _2756 = (uint16_t)(216); + _curvea0[648] = _2756; + uint16_t _2757 = (uint16_t)(216); + _curvea0[649] = _2757; + uint16_t _2758 = (uint16_t)(216); + _curvea0[650] = _2758; + uint16_t _2759 = (uint16_t)(216); + _curvea0[651] = _2759; + uint16_t _2760 = (uint16_t)(217); + _curvea0[652] = _2760; + uint16_t _2761 = (uint16_t)(217); + _curvea0[653] = _2761; + uint16_t _2762 = (uint16_t)(217); + _curvea0[654] = _2762; + uint16_t _2763 = (uint16_t)(217); + _curvea0[655] = _2763; + uint16_t _2764 = (uint16_t)(217); + _curvea0[656] = _2764; + uint16_t _2765 = (uint16_t)(217); + _curvea0[657] = _2765; + uint16_t _2766 = (uint16_t)(217); + _curvea0[658] = _2766; + uint16_t _2767 = (uint16_t)(218); + _curvea0[659] = _2767; + uint16_t _2768 = (uint16_t)(218); + _curvea0[660] = _2768; + uint16_t _2769 = (uint16_t)(218); + _curvea0[661] = _2769; + uint16_t _2770 = (uint16_t)(218); + _curvea0[662] = _2770; + uint16_t _2771 = (uint16_t)(218); + _curvea0[663] = _2771; + uint16_t _2772 = (uint16_t)(218); + _curvea0[664] = _2772; + uint16_t _2773 = (uint16_t)(218); + _curvea0[665] = _2773; + uint16_t _2774 = (uint16_t)(219); + _curvea0[666] = _2774; + uint16_t _2775 = (uint16_t)(219); + _curvea0[667] = _2775; + uint16_t _2776 = (uint16_t)(219); + _curvea0[668] = _2776; + uint16_t _2777 = (uint16_t)(219); + _curvea0[669] = _2777; + uint16_t _2778 = (uint16_t)(219); + _curvea0[670] = _2778; + uint16_t _2779 = (uint16_t)(219); + _curvea0[671] = _2779; + uint16_t _2780 = (uint16_t)(219); + _curvea0[672] = _2780; + uint16_t _2781 = (uint16_t)(220); + _curvea0[673] = _2781; + uint16_t _2782 = (uint16_t)(220); + _curvea0[674] = _2782; + uint16_t _2783 = (uint16_t)(220); + _curvea0[675] = _2783; + uint16_t _2784 = (uint16_t)(220); + _curvea0[676] = _2784; + uint16_t _2785 = (uint16_t)(220); + _curvea0[677] = _2785; + uint16_t _2786 = (uint16_t)(220); + _curvea0[678] = _2786; + uint16_t _2787 = (uint16_t)(220); + _curvea0[679] = _2787; + uint16_t _2788 = (uint16_t)(220); + _curvea0[680] = _2788; + uint16_t _2789 = (uint16_t)(221); + _curvea0[681] = _2789; + uint16_t _2790 = (uint16_t)(221); + _curvea0[682] = _2790; + uint16_t _2791 = (uint16_t)(221); + _curvea0[683] = _2791; + uint16_t _2792 = (uint16_t)(221); + _curvea0[684] = _2792; + uint16_t _2793 = (uint16_t)(221); + _curvea0[685] = _2793; + uint16_t _2794 = (uint16_t)(221); + _curvea0[686] = _2794; + uint16_t _2795 = (uint16_t)(221); + _curvea0[687] = _2795; + uint16_t _2796 = (uint16_t)(222); + _curvea0[688] = _2796; + uint16_t _2797 = (uint16_t)(222); + _curvea0[689] = _2797; + uint16_t _2798 = (uint16_t)(222); + _curvea0[690] = _2798; + uint16_t _2799 = (uint16_t)(222); + _curvea0[691] = _2799; + uint16_t _2800 = (uint16_t)(222); + _curvea0[692] = _2800; + uint16_t _2801 = (uint16_t)(222); + _curvea0[693] = _2801; + uint16_t _2802 = (uint16_t)(222); + _curvea0[694] = _2802; + uint16_t _2803 = (uint16_t)(223); + _curvea0[695] = _2803; + uint16_t _2804 = (uint16_t)(223); + _curvea0[696] = _2804; + uint16_t _2805 = (uint16_t)(223); + _curvea0[697] = _2805; + uint16_t _2806 = (uint16_t)(223); + _curvea0[698] = _2806; + uint16_t _2807 = (uint16_t)(223); + _curvea0[699] = _2807; + uint16_t _2808 = (uint16_t)(223); + _curvea0[700] = _2808; + uint16_t _2809 = (uint16_t)(223); + _curvea0[701] = _2809; + uint16_t _2810 = (uint16_t)(223); + _curvea0[702] = _2810; + uint16_t _2811 = (uint16_t)(224); + _curvea0[703] = _2811; + uint16_t _2812 = (uint16_t)(224); + _curvea0[704] = _2812; + uint16_t _2813 = (uint16_t)(224); + _curvea0[705] = _2813; + uint16_t _2814 = (uint16_t)(224); + _curvea0[706] = _2814; + uint16_t _2815 = (uint16_t)(224); + _curvea0[707] = _2815; + uint16_t _2816 = (uint16_t)(224); + _curvea0[708] = _2816; + uint16_t _2817 = (uint16_t)(224); + _curvea0[709] = _2817; + uint16_t _2818 = (uint16_t)(224); + _curvea0[710] = _2818; + uint16_t _2819 = (uint16_t)(225); + _curvea0[711] = _2819; + uint16_t _2820 = (uint16_t)(225); + _curvea0[712] = _2820; + uint16_t _2821 = (uint16_t)(225); + _curvea0[713] = _2821; + uint16_t _2822 = (uint16_t)(225); + _curvea0[714] = _2822; + uint16_t _2823 = (uint16_t)(225); + _curvea0[715] = _2823; + uint16_t _2824 = (uint16_t)(225); + _curvea0[716] = _2824; + uint16_t _2825 = (uint16_t)(225); + _curvea0[717] = _2825; + uint16_t _2826 = (uint16_t)(226); + _curvea0[718] = _2826; + uint16_t _2827 = (uint16_t)(226); + _curvea0[719] = _2827; + uint16_t _2828 = (uint16_t)(226); + _curvea0[720] = _2828; + uint16_t _2829 = (uint16_t)(226); + _curvea0[721] = _2829; + uint16_t _2830 = (uint16_t)(226); + _curvea0[722] = _2830; + uint16_t _2831 = (uint16_t)(226); + _curvea0[723] = _2831; + uint16_t _2832 = (uint16_t)(226); + _curvea0[724] = _2832; + uint16_t _2833 = (uint16_t)(226); + _curvea0[725] = _2833; + uint16_t _2834 = (uint16_t)(227); + _curvea0[726] = _2834; + uint16_t _2835 = (uint16_t)(227); + _curvea0[727] = _2835; + uint16_t _2836 = (uint16_t)(227); + _curvea0[728] = _2836; + uint16_t _2837 = (uint16_t)(227); + _curvea0[729] = _2837; + uint16_t _2838 = (uint16_t)(227); + _curvea0[730] = _2838; + uint16_t _2839 = (uint16_t)(227); + _curvea0[731] = _2839; + uint16_t _2840 = (uint16_t)(227); + _curvea0[732] = _2840; + uint16_t _2841 = (uint16_t)(227); + _curvea0[733] = _2841; + uint16_t _2842 = (uint16_t)(228); + _curvea0[734] = _2842; + uint16_t _2843 = (uint16_t)(228); + _curvea0[735] = _2843; + uint16_t _2844 = (uint16_t)(228); + _curvea0[736] = _2844; + uint16_t _2845 = (uint16_t)(228); + _curvea0[737] = _2845; + uint16_t _2846 = (uint16_t)(228); + _curvea0[738] = _2846; + uint16_t _2847 = (uint16_t)(228); + _curvea0[739] = _2847; + uint16_t _2848 = (uint16_t)(228); + _curvea0[740] = _2848; + uint16_t _2849 = (uint16_t)(228); + _curvea0[741] = _2849; + uint16_t _2850 = (uint16_t)(228); + _curvea0[742] = _2850; + uint16_t _2851 = (uint16_t)(229); + _curvea0[743] = _2851; + uint16_t _2852 = (uint16_t)(229); + _curvea0[744] = _2852; + uint16_t _2853 = (uint16_t)(229); + _curvea0[745] = _2853; + uint16_t _2854 = (uint16_t)(229); + _curvea0[746] = _2854; + uint16_t _2855 = (uint16_t)(229); + _curvea0[747] = _2855; + uint16_t _2856 = (uint16_t)(229); + _curvea0[748] = _2856; + uint16_t _2857 = (uint16_t)(229); + _curvea0[749] = _2857; + uint16_t _2858 = (uint16_t)(229); + _curvea0[750] = _2858; + uint16_t _2859 = (uint16_t)(230); + _curvea0[751] = _2859; + uint16_t _2860 = (uint16_t)(230); + _curvea0[752] = _2860; + uint16_t _2861 = (uint16_t)(230); + _curvea0[753] = _2861; + uint16_t _2862 = (uint16_t)(230); + _curvea0[754] = _2862; + uint16_t _2863 = (uint16_t)(230); + _curvea0[755] = _2863; + uint16_t _2864 = (uint16_t)(230); + _curvea0[756] = _2864; + uint16_t _2865 = (uint16_t)(230); + _curvea0[757] = _2865; + uint16_t _2866 = (uint16_t)(230); + _curvea0[758] = _2866; + uint16_t _2867 = (uint16_t)(231); + _curvea0[759] = _2867; + uint16_t _2868 = (uint16_t)(231); + _curvea0[760] = _2868; + uint16_t _2869 = (uint16_t)(231); + _curvea0[761] = _2869; + uint16_t _2870 = (uint16_t)(231); + _curvea0[762] = _2870; + uint16_t _2871 = (uint16_t)(231); + _curvea0[763] = _2871; + uint16_t _2872 = (uint16_t)(231); + _curvea0[764] = _2872; + uint16_t _2873 = (uint16_t)(231); + _curvea0[765] = _2873; + uint16_t _2874 = (uint16_t)(231); + _curvea0[766] = _2874; + uint16_t _2875 = (uint16_t)(231); + _curvea0[767] = _2875; + uint16_t _2876 = (uint16_t)(232); + _curvea0[768] = _2876; + uint16_t _2877 = (uint16_t)(232); + _curvea0[769] = _2877; + uint16_t _2878 = (uint16_t)(232); + _curvea0[770] = _2878; + uint16_t _2879 = (uint16_t)(232); + _curvea0[771] = _2879; + uint16_t _2880 = (uint16_t)(232); + _curvea0[772] = _2880; + uint16_t _2881 = (uint16_t)(232); + _curvea0[773] = _2881; + uint16_t _2882 = (uint16_t)(232); + _curvea0[774] = _2882; + uint16_t _2883 = (uint16_t)(232); + _curvea0[775] = _2883; + uint16_t _2884 = (uint16_t)(233); + _curvea0[776] = _2884; + uint16_t _2885 = (uint16_t)(233); + _curvea0[777] = _2885; + uint16_t _2886 = (uint16_t)(233); + _curvea0[778] = _2886; + uint16_t _2887 = (uint16_t)(233); + _curvea0[779] = _2887; + uint16_t _2888 = (uint16_t)(233); + _curvea0[780] = _2888; + uint16_t _2889 = (uint16_t)(233); + _curvea0[781] = _2889; + uint16_t _2890 = (uint16_t)(233); + _curvea0[782] = _2890; + uint16_t _2891 = (uint16_t)(233); + _curvea0[783] = _2891; + uint16_t _2892 = (uint16_t)(233); + _curvea0[784] = _2892; + uint16_t _2893 = (uint16_t)(234); + _curvea0[785] = _2893; + uint16_t _2894 = (uint16_t)(234); + _curvea0[786] = _2894; + uint16_t _2895 = (uint16_t)(234); + _curvea0[787] = _2895; + uint16_t _2896 = (uint16_t)(234); + _curvea0[788] = _2896; + uint16_t _2897 = (uint16_t)(234); + _curvea0[789] = _2897; + uint16_t _2898 = (uint16_t)(234); + _curvea0[790] = _2898; + uint16_t _2899 = (uint16_t)(234); + _curvea0[791] = _2899; + uint16_t _2900 = (uint16_t)(234); + _curvea0[792] = _2900; + uint16_t _2901 = (uint16_t)(234); + _curvea0[793] = _2901; + uint16_t _2902 = (uint16_t)(235); + _curvea0[794] = _2902; + uint16_t _2903 = (uint16_t)(235); + _curvea0[795] = _2903; + uint16_t _2904 = (uint16_t)(235); + _curvea0[796] = _2904; + uint16_t _2905 = (uint16_t)(235); + _curvea0[797] = _2905; + uint16_t _2906 = (uint16_t)(235); + _curvea0[798] = _2906; + uint16_t _2907 = (uint16_t)(235); + _curvea0[799] = _2907; + uint16_t _2908 = (uint16_t)(235); + _curvea0[800] = _2908; + uint16_t _2909 = (uint16_t)(235); + _curvea0[801] = _2909; + uint16_t _2910 = (uint16_t)(235); + _curvea0[802] = _2910; + uint16_t _2911 = (uint16_t)(236); + _curvea0[803] = _2911; + uint16_t _2912 = (uint16_t)(236); + _curvea0[804] = _2912; + uint16_t _2913 = (uint16_t)(236); + _curvea0[805] = _2913; + uint16_t _2914 = (uint16_t)(236); + _curvea0[806] = _2914; + uint16_t _2915 = (uint16_t)(236); + _curvea0[807] = _2915; + uint16_t _2916 = (uint16_t)(236); + _curvea0[808] = _2916; + uint16_t _2917 = (uint16_t)(236); + _curvea0[809] = _2917; + uint16_t _2918 = (uint16_t)(236); + _curvea0[810] = _2918; + uint16_t _2919 = (uint16_t)(236); + _curvea0[811] = _2919; + uint16_t _2920 = (uint16_t)(237); + _curvea0[812] = _2920; + uint16_t _2921 = (uint16_t)(237); + _curvea0[813] = _2921; + uint16_t _2922 = (uint16_t)(237); + _curvea0[814] = _2922; + uint16_t _2923 = (uint16_t)(237); + _curvea0[815] = _2923; + uint16_t _2924 = (uint16_t)(237); + _curvea0[816] = _2924; + uint16_t _2925 = (uint16_t)(237); + _curvea0[817] = _2925; + uint16_t _2926 = (uint16_t)(237); + _curvea0[818] = _2926; + uint16_t _2927 = (uint16_t)(237); + _curvea0[819] = _2927; + uint16_t _2928 = (uint16_t)(237); + _curvea0[820] = _2928; + uint16_t _2929 = (uint16_t)(237); + _curvea0[821] = _2929; + uint16_t _2930 = (uint16_t)(238); + _curvea0[822] = _2930; + uint16_t _2931 = (uint16_t)(238); + _curvea0[823] = _2931; + uint16_t _2932 = (uint16_t)(238); + _curvea0[824] = _2932; + uint16_t _2933 = (uint16_t)(238); + _curvea0[825] = _2933; + uint16_t _2934 = (uint16_t)(238); + _curvea0[826] = _2934; + uint16_t _2935 = (uint16_t)(238); + _curvea0[827] = _2935; + uint16_t _2936 = (uint16_t)(238); + _curvea0[828] = _2936; + uint16_t _2937 = (uint16_t)(238); + _curvea0[829] = _2937; + uint16_t _2938 = (uint16_t)(238); + _curvea0[830] = _2938; + uint16_t _2939 = (uint16_t)(239); + _curvea0[831] = _2939; + uint16_t _2940 = (uint16_t)(239); + _curvea0[832] = _2940; + uint16_t _2941 = (uint16_t)(239); + _curvea0[833] = _2941; + uint16_t _2942 = (uint16_t)(239); + _curvea0[834] = _2942; + uint16_t _2943 = (uint16_t)(239); + _curvea0[835] = _2943; + uint16_t _2944 = (uint16_t)(239); + _curvea0[836] = _2944; + uint16_t _2945 = (uint16_t)(239); + _curvea0[837] = _2945; + uint16_t _2946 = (uint16_t)(239); + _curvea0[838] = _2946; + uint16_t _2947 = (uint16_t)(239); + _curvea0[839] = _2947; + uint16_t _2948 = (uint16_t)(239); + _curvea0[840] = _2948; + uint16_t _2949 = (uint16_t)(240); + _curvea0[841] = _2949; + uint16_t _2950 = (uint16_t)(240); + _curvea0[842] = _2950; + uint16_t _2951 = (uint16_t)(240); + _curvea0[843] = _2951; + uint16_t _2952 = (uint16_t)(240); + _curvea0[844] = _2952; + uint16_t _2953 = (uint16_t)(240); + _curvea0[845] = _2953; + uint16_t _2954 = (uint16_t)(240); + _curvea0[846] = _2954; + uint16_t _2955 = (uint16_t)(240); + _curvea0[847] = _2955; + uint16_t _2956 = (uint16_t)(240); + _curvea0[848] = _2956; + uint16_t _2957 = (uint16_t)(240); + _curvea0[849] = _2957; + uint16_t _2958 = (uint16_t)(240); + _curvea0[850] = _2958; + uint16_t _2959 = (uint16_t)(241); + _curvea0[851] = _2959; + uint16_t _2960 = (uint16_t)(241); + _curvea0[852] = _2960; + uint16_t _2961 = (uint16_t)(241); + _curvea0[853] = _2961; + uint16_t _2962 = (uint16_t)(241); + _curvea0[854] = _2962; + uint16_t _2963 = (uint16_t)(241); + _curvea0[855] = _2963; + uint16_t _2964 = (uint16_t)(241); + _curvea0[856] = _2964; + uint16_t _2965 = (uint16_t)(241); + _curvea0[857] = _2965; + uint16_t _2966 = (uint16_t)(241); + _curvea0[858] = _2966; + uint16_t _2967 = (uint16_t)(241); + _curvea0[859] = _2967; + uint16_t _2968 = (uint16_t)(241); + _curvea0[860] = _2968; + uint16_t _2969 = (uint16_t)(242); + _curvea0[861] = _2969; + uint16_t _2970 = (uint16_t)(242); + _curvea0[862] = _2970; + uint16_t _2971 = (uint16_t)(242); + _curvea0[863] = _2971; + uint16_t _2972 = (uint16_t)(242); + _curvea0[864] = _2972; + uint16_t _2973 = (uint16_t)(242); + _curvea0[865] = _2973; + uint16_t _2974 = (uint16_t)(242); + _curvea0[866] = _2974; + uint16_t _2975 = (uint16_t)(242); + _curvea0[867] = _2975; + uint16_t _2976 = (uint16_t)(242); + _curvea0[868] = _2976; + uint16_t _2977 = (uint16_t)(242); + _curvea0[869] = _2977; + uint16_t _2978 = (uint16_t)(242); + _curvea0[870] = _2978; + uint16_t _2979 = (uint16_t)(243); + _curvea0[871] = _2979; + uint16_t _2980 = (uint16_t)(243); + _curvea0[872] = _2980; + uint16_t _2981 = (uint16_t)(243); + _curvea0[873] = _2981; + uint16_t _2982 = (uint16_t)(243); + _curvea0[874] = _2982; + uint16_t _2983 = (uint16_t)(243); + _curvea0[875] = _2983; + uint16_t _2984 = (uint16_t)(243); + _curvea0[876] = _2984; + uint16_t _2985 = (uint16_t)(243); + _curvea0[877] = _2985; + uint16_t _2986 = (uint16_t)(243); + _curvea0[878] = _2986; + uint16_t _2987 = (uint16_t)(243); + _curvea0[879] = _2987; + uint16_t _2988 = (uint16_t)(243); + _curvea0[880] = _2988; + uint16_t _2989 = (uint16_t)(244); + _curvea0[881] = _2989; + uint16_t _2990 = (uint16_t)(244); + _curvea0[882] = _2990; + uint16_t _2991 = (uint16_t)(244); + _curvea0[883] = _2991; + uint16_t _2992 = (uint16_t)(244); + _curvea0[884] = _2992; + uint16_t _2993 = (uint16_t)(244); + _curvea0[885] = _2993; + uint16_t _2994 = (uint16_t)(244); + _curvea0[886] = _2994; + uint16_t _2995 = (uint16_t)(244); + _curvea0[887] = _2995; + uint16_t _2996 = (uint16_t)(244); + _curvea0[888] = _2996; + uint16_t _2997 = (uint16_t)(244); + _curvea0[889] = _2997; + uint16_t _2998 = (uint16_t)(244); + _curvea0[890] = _2998; + uint16_t _2999 = (uint16_t)(244); + _curvea0[891] = _2999; + uint16_t _3000 = (uint16_t)(245); + _curvea0[892] = _3000; + uint16_t _3001 = (uint16_t)(245); + _curvea0[893] = _3001; + uint16_t _3002 = (uint16_t)(245); + _curvea0[894] = _3002; + uint16_t _3003 = (uint16_t)(245); + _curvea0[895] = _3003; + uint16_t _3004 = (uint16_t)(245); + _curvea0[896] = _3004; + uint16_t _3005 = (uint16_t)(245); + _curvea0[897] = _3005; + uint16_t _3006 = (uint16_t)(245); + _curvea0[898] = _3006; + uint16_t _3007 = (uint16_t)(245); + _curvea0[899] = _3007; + uint16_t _3008 = (uint16_t)(245); + _curvea0[900] = _3008; + uint16_t _3009 = (uint16_t)(245); + _curvea0[901] = _3009; + uint16_t _3010 = (uint16_t)(245); + _curvea0[902] = _3010; + uint16_t _3011 = (uint16_t)(246); + _curvea0[903] = _3011; + uint16_t _3012 = (uint16_t)(246); + _curvea0[904] = _3012; + uint16_t _3013 = (uint16_t)(246); + _curvea0[905] = _3013; + uint16_t _3014 = (uint16_t)(246); + _curvea0[906] = _3014; + uint16_t _3015 = (uint16_t)(246); + _curvea0[907] = _3015; + uint16_t _3016 = (uint16_t)(246); + _curvea0[908] = _3016; + uint16_t _3017 = (uint16_t)(246); + _curvea0[909] = _3017; + uint16_t _3018 = (uint16_t)(246); + _curvea0[910] = _3018; + uint16_t _3019 = (uint16_t)(246); + _curvea0[911] = _3019; + uint16_t _3020 = (uint16_t)(246); + _curvea0[912] = _3020; + uint16_t _3021 = (uint16_t)(246); + _curvea0[913] = _3021; + uint16_t _3022 = (uint16_t)(247); + _curvea0[914] = _3022; + uint16_t _3023 = (uint16_t)(247); + _curvea0[915] = _3023; + uint16_t _3024 = (uint16_t)(247); + _curvea0[916] = _3024; + uint16_t _3025 = (uint16_t)(247); + _curvea0[917] = _3025; + uint16_t _3026 = (uint16_t)(247); + _curvea0[918] = _3026; + uint16_t _3027 = (uint16_t)(247); + _curvea0[919] = _3027; + uint16_t _3028 = (uint16_t)(247); + _curvea0[920] = _3028; + uint16_t _3029 = (uint16_t)(247); + _curvea0[921] = _3029; + uint16_t _3030 = (uint16_t)(247); + _curvea0[922] = _3030; + uint16_t _3031 = (uint16_t)(247); + _curvea0[923] = _3031; + uint16_t _3032 = (uint16_t)(247); + _curvea0[924] = _3032; + uint16_t _3033 = (uint16_t)(248); + _curvea0[925] = _3033; + uint16_t _3034 = (uint16_t)(248); + _curvea0[926] = _3034; + uint16_t _3035 = (uint16_t)(248); + _curvea0[927] = _3035; + uint16_t _3036 = (uint16_t)(248); + _curvea0[928] = _3036; + uint16_t _3037 = (uint16_t)(248); + _curvea0[929] = _3037; + uint16_t _3038 = (uint16_t)(248); + _curvea0[930] = _3038; + uint16_t _3039 = (uint16_t)(248); + _curvea0[931] = _3039; + uint16_t _3040 = (uint16_t)(248); + _curvea0[932] = _3040; + uint16_t _3041 = (uint16_t)(248); + _curvea0[933] = _3041; + uint16_t _3042 = (uint16_t)(248); + _curvea0[934] = _3042; + uint16_t _3043 = (uint16_t)(248); + _curvea0[935] = _3043; + uint16_t _3044 = (uint16_t)(249); + _curvea0[936] = _3044; + uint16_t _3045 = (uint16_t)(249); + _curvea0[937] = _3045; + uint16_t _3046 = (uint16_t)(249); + _curvea0[938] = _3046; + uint16_t _3047 = (uint16_t)(249); + _curvea0[939] = _3047; + uint16_t _3048 = (uint16_t)(249); + _curvea0[940] = _3048; + uint16_t _3049 = (uint16_t)(249); + _curvea0[941] = _3049; + uint16_t _3050 = (uint16_t)(249); + _curvea0[942] = _3050; + uint16_t _3051 = (uint16_t)(249); + _curvea0[943] = _3051; + uint16_t _3052 = (uint16_t)(249); + _curvea0[944] = _3052; + uint16_t _3053 = (uint16_t)(249); + _curvea0[945] = _3053; + uint16_t _3054 = (uint16_t)(249); + _curvea0[946] = _3054; + uint16_t _3055 = (uint16_t)(249); + _curvea0[947] = _3055; + uint16_t _3056 = (uint16_t)(250); + _curvea0[948] = _3056; + uint16_t _3057 = (uint16_t)(250); + _curvea0[949] = _3057; + uint16_t _3058 = (uint16_t)(250); + _curvea0[950] = _3058; + uint16_t _3059 = (uint16_t)(250); + _curvea0[951] = _3059; + uint16_t _3060 = (uint16_t)(250); + _curvea0[952] = _3060; + uint16_t _3061 = (uint16_t)(250); + _curvea0[953] = _3061; + uint16_t _3062 = (uint16_t)(250); + _curvea0[954] = _3062; + uint16_t _3063 = (uint16_t)(250); + _curvea0[955] = _3063; + uint16_t _3064 = (uint16_t)(250); + _curvea0[956] = _3064; + uint16_t _3065 = (uint16_t)(250); + _curvea0[957] = _3065; + uint16_t _3066 = (uint16_t)(250); + _curvea0[958] = _3066; + uint16_t _3067 = (uint16_t)(250); + _curvea0[959] = _3067; + uint16_t _3068 = (uint16_t)(251); + _curvea0[960] = _3068; + uint16_t _3069 = (uint16_t)(251); + _curvea0[961] = _3069; + uint16_t _3070 = (uint16_t)(251); + _curvea0[962] = _3070; + uint16_t _3071 = (uint16_t)(251); + _curvea0[963] = _3071; + uint16_t _3072 = (uint16_t)(251); + _curvea0[964] = _3072; + uint16_t _3073 = (uint16_t)(251); + _curvea0[965] = _3073; + uint16_t _3074 = (uint16_t)(251); + _curvea0[966] = _3074; + uint16_t _3075 = (uint16_t)(251); + _curvea0[967] = _3075; + uint16_t _3076 = (uint16_t)(251); + _curvea0[968] = _3076; + uint16_t _3077 = (uint16_t)(251); + _curvea0[969] = _3077; + uint16_t _3078 = (uint16_t)(251); + _curvea0[970] = _3078; + uint16_t _3079 = (uint16_t)(251); + _curvea0[971] = _3079; + uint16_t _3080 = (uint16_t)(252); + _curvea0[972] = _3080; + uint16_t _3081 = (uint16_t)(252); + _curvea0[973] = _3081; + uint16_t _3082 = (uint16_t)(252); + _curvea0[974] = _3082; + uint16_t _3083 = (uint16_t)(252); + _curvea0[975] = _3083; + uint16_t _3084 = (uint16_t)(252); + _curvea0[976] = _3084; + uint16_t _3085 = (uint16_t)(252); + _curvea0[977] = _3085; + uint16_t _3086 = (uint16_t)(252); + _curvea0[978] = _3086; + uint16_t _3087 = (uint16_t)(252); + _curvea0[979] = _3087; + uint16_t _3088 = (uint16_t)(252); + _curvea0[980] = _3088; + uint16_t _3089 = (uint16_t)(252); + _curvea0[981] = _3089; + uint16_t _3090 = (uint16_t)(252); + _curvea0[982] = _3090; + uint16_t _3091 = (uint16_t)(252); + _curvea0[983] = _3091; + uint16_t _3092 = (uint16_t)(252); + _curvea0[984] = _3092; + uint16_t _3093 = (uint16_t)(253); + _curvea0[985] = _3093; + uint16_t _3094 = (uint16_t)(253); + _curvea0[986] = _3094; + uint16_t _3095 = (uint16_t)(253); + _curvea0[987] = _3095; + uint16_t _3096 = (uint16_t)(253); + _curvea0[988] = _3096; + uint16_t _3097 = (uint16_t)(253); + _curvea0[989] = _3097; + uint16_t _3098 = (uint16_t)(253); + _curvea0[990] = _3098; + uint16_t _3099 = (uint16_t)(253); + _curvea0[991] = _3099; + uint16_t _3100 = (uint16_t)(253); + _curvea0[992] = _3100; + uint16_t _3101 = (uint16_t)(253); + _curvea0[993] = _3101; + uint16_t _3102 = (uint16_t)(253); + _curvea0[994] = _3102; + uint16_t _3103 = (uint16_t)(253); + _curvea0[995] = _3103; + uint16_t _3104 = (uint16_t)(253); + _curvea0[996] = _3104; + uint16_t _3105 = (uint16_t)(253); + _curvea0[997] = _3105; + uint16_t _3106 = (uint16_t)(254); + _curvea0[998] = _3106; + uint16_t _3107 = (uint16_t)(254); + _curvea0[999] = _3107; + uint16_t _3108 = (uint16_t)(254); + _curvea0[1000] = _3108; + uint16_t _3109 = (uint16_t)(254); + _curvea0[1001] = _3109; + uint16_t _3110 = (uint16_t)(254); + _curvea0[1002] = _3110; + uint16_t _3111 = (uint16_t)(254); + _curvea0[1003] = _3111; + uint16_t _3112 = (uint16_t)(254); + _curvea0[1004] = _3112; + uint16_t _3113 = (uint16_t)(254); + _curvea0[1005] = _3113; + uint16_t _3114 = (uint16_t)(254); + _curvea0[1006] = _3114; + uint16_t _3115 = (uint16_t)(254); + _curvea0[1007] = _3115; + uint16_t _3116 = (uint16_t)(254); + _curvea0[1008] = _3116; + uint16_t _3117 = (uint16_t)(254); + _curvea0[1009] = _3117; + uint16_t _3118 = (uint16_t)(254); + _curvea0[1010] = _3118; + uint16_t _3119 = (uint16_t)(255); + _curvea0[1011] = _3119; + uint16_t _3120 = (uint16_t)(255); + _curvea0[1012] = _3120; + uint16_t _3121 = (uint16_t)(255); + _curvea0[1013] = _3121; + uint16_t _3122 = (uint16_t)(255); + _curvea0[1014] = _3122; + uint16_t _3123 = (uint16_t)(255); + _curvea0[1015] = _3123; + uint16_t _3124 = (uint16_t)(255); + _curvea0[1016] = _3124; + uint16_t _3125 = (uint16_t)(255); + _curvea0[1017] = _3125; + uint16_t _3126 = (uint16_t)(255); + _curvea0[1018] = _3126; + uint16_t _3127 = (uint16_t)(255); + _curvea0[1019] = _3127; + uint16_t _3128 = (uint16_t)(255); + _curvea0[1020] = _3128; + uint16_t _3129 = (uint16_t)(255); + _curvea0[1021] = _3129; + uint16_t _3130 = (uint16_t)(255); + _curvea0[1022] = _3130; + uint16_t _3131 = (uint16_t)(255); + _curvea0[1023] = _3131; + + int16_t _3132 = (int16_t)(1023); + int16_t _3133 = min(_corrected_stencil_1, _3132); + int16_t _3134 = (int16_t)(0); + int16_t _3135 = max(_3133, _3134); + uint16_t _3136 = (uint16_t)(_3135); + int32_t _3137 = (int32_t)(_3136); + uint16_t _3138 = ((const uint16_t *)_curvea0)[_3137]; + return _3138; +} + +//store is: curved.stencil(curved_s0_x_x_1, curved_s0_y_1, 1) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x_1, curved_s0_y_1, 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_1(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_2 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _3153 = (uint16_t)(0); + _curvea0[0] = _3153; + uint16_t _3154 = (uint16_t)(4); + _curvea0[1] = _3154; + uint16_t _3155 = (uint16_t)(7); + _curvea0[2] = _3155; + uint16_t _3156 = (uint16_t)(8); + _curvea0[3] = _3156; + uint16_t _3157 = (uint16_t)(10); + _curvea0[4] = _3157; + uint16_t _3158 = (uint16_t)(11); + _curvea0[5] = _3158; + uint16_t _3159 = (uint16_t)(12); + _curvea0[6] = _3159; + uint16_t _3160 = (uint16_t)(13); + _curvea0[7] = _3160; + uint16_t _3161 = (uint16_t)(14); + _curvea0[8] = _3161; + uint16_t _3162 = (uint16_t)(15); + _curvea0[9] = _3162; + uint16_t _3163 = (uint16_t)(16); + _curvea0[10] = _3163; + uint16_t _3164 = (uint16_t)(17); + _curvea0[11] = _3164; + uint16_t _3165 = (uint16_t)(18); + _curvea0[12] = _3165; + uint16_t _3166 = (uint16_t)(19); + _curvea0[13] = _3166; + uint16_t _3167 = (uint16_t)(20); + _curvea0[14] = _3167; + uint16_t _3168 = (uint16_t)(21); + _curvea0[15] = _3168; + uint16_t _3169 = (uint16_t)(22); + _curvea0[16] = _3169; + uint16_t _3170 = (uint16_t)(22); + _curvea0[17] = _3170; + uint16_t _3171 = (uint16_t)(23); + _curvea0[18] = _3171; + uint16_t _3172 = (uint16_t)(24); + _curvea0[19] = _3172; + uint16_t _3173 = (uint16_t)(25); + _curvea0[20] = _3173; + uint16_t _3174 = (uint16_t)(25); + _curvea0[21] = _3174; + uint16_t _3175 = (uint16_t)(26); + _curvea0[22] = _3175; + uint16_t _3176 = (uint16_t)(27); + _curvea0[23] = _3176; + uint16_t _3177 = (uint16_t)(27); + _curvea0[24] = _3177; + uint16_t _3178 = (uint16_t)(28); + _curvea0[25] = _3178; + uint16_t _3179 = (uint16_t)(29); + _curvea0[26] = _3179; + uint16_t _3180 = (uint16_t)(29); + _curvea0[27] = _3180; + uint16_t _3181 = (uint16_t)(30); + _curvea0[28] = _3181; + uint16_t _3182 = (uint16_t)(31); + _curvea0[29] = _3182; + uint16_t _3183 = (uint16_t)(31); + _curvea0[30] = _3183; + uint16_t _3184 = (uint16_t)(32); + _curvea0[31] = _3184; + uint16_t _3185 = (uint16_t)(33); + _curvea0[32] = _3185; + uint16_t _3186 = (uint16_t)(33); + _curvea0[33] = _3186; + uint16_t _3187 = (uint16_t)(34); + _curvea0[34] = _3187; + uint16_t _3188 = (uint16_t)(34); + _curvea0[35] = _3188; + uint16_t _3189 = (uint16_t)(35); + _curvea0[36] = _3189; + uint16_t _3190 = (uint16_t)(36); + _curvea0[37] = _3190; + uint16_t _3191 = (uint16_t)(36); + _curvea0[38] = _3191; + uint16_t _3192 = (uint16_t)(37); + _curvea0[39] = _3192; + uint16_t _3193 = (uint16_t)(37); + _curvea0[40] = _3193; + uint16_t _3194 = (uint16_t)(38); + _curvea0[41] = _3194; + uint16_t _3195 = (uint16_t)(39); + _curvea0[42] = _3195; + uint16_t _3196 = (uint16_t)(39); + _curvea0[43] = _3196; + uint16_t _3197 = (uint16_t)(40); + _curvea0[44] = _3197; + uint16_t _3198 = (uint16_t)(40); + _curvea0[45] = _3198; + uint16_t _3199 = (uint16_t)(41); + _curvea0[46] = _3199; + uint16_t _3200 = (uint16_t)(41); + _curvea0[47] = _3200; + uint16_t _3201 = (uint16_t)(42); + _curvea0[48] = _3201; + uint16_t _3202 = (uint16_t)(42); + _curvea0[49] = _3202; + uint16_t _3203 = (uint16_t)(43); + _curvea0[50] = _3203; + uint16_t _3204 = (uint16_t)(44); + _curvea0[51] = _3204; + uint16_t _3205 = (uint16_t)(44); + _curvea0[52] = _3205; + uint16_t _3206 = (uint16_t)(45); + _curvea0[53] = _3206; + uint16_t _3207 = (uint16_t)(45); + _curvea0[54] = _3207; + uint16_t _3208 = (uint16_t)(46); + _curvea0[55] = _3208; + uint16_t _3209 = (uint16_t)(46); + _curvea0[56] = _3209; + uint16_t _3210 = (uint16_t)(47); + _curvea0[57] = _3210; + uint16_t _3211 = (uint16_t)(47); + _curvea0[58] = _3211; + uint16_t _3212 = (uint16_t)(48); + _curvea0[59] = _3212; + uint16_t _3213 = (uint16_t)(48); + _curvea0[60] = _3213; + uint16_t _3214 = (uint16_t)(49); + _curvea0[61] = _3214; + uint16_t _3215 = (uint16_t)(49); + _curvea0[62] = _3215; + uint16_t _3216 = (uint16_t)(50); + _curvea0[63] = _3216; + uint16_t _3217 = (uint16_t)(50); + _curvea0[64] = _3217; + uint16_t _3218 = (uint16_t)(51); + _curvea0[65] = _3218; + uint16_t _3219 = (uint16_t)(51); + _curvea0[66] = _3219; + uint16_t _3220 = (uint16_t)(52); + _curvea0[67] = _3220; + uint16_t _3221 = (uint16_t)(52); + _curvea0[68] = _3221; + uint16_t _3222 = (uint16_t)(53); + _curvea0[69] = _3222; + uint16_t _3223 = (uint16_t)(53); + _curvea0[70] = _3223; + uint16_t _3224 = (uint16_t)(54); + _curvea0[71] = _3224; + uint16_t _3225 = (uint16_t)(54); + _curvea0[72] = _3225; + uint16_t _3226 = (uint16_t)(55); + _curvea0[73] = _3226; + uint16_t _3227 = (uint16_t)(55); + _curvea0[74] = _3227; + uint16_t _3228 = (uint16_t)(56); + _curvea0[75] = _3228; + uint16_t _3229 = (uint16_t)(56); + _curvea0[76] = _3229; + uint16_t _3230 = (uint16_t)(57); + _curvea0[77] = _3230; + uint16_t _3231 = (uint16_t)(57); + _curvea0[78] = _3231; + uint16_t _3232 = (uint16_t)(58); + _curvea0[79] = _3232; + uint16_t _3233 = (uint16_t)(58); + _curvea0[80] = _3233; + uint16_t _3234 = (uint16_t)(58); + _curvea0[81] = _3234; + uint16_t _3235 = (uint16_t)(59); + _curvea0[82] = _3235; + uint16_t _3236 = (uint16_t)(59); + _curvea0[83] = _3236; + uint16_t _3237 = (uint16_t)(60); + _curvea0[84] = _3237; + uint16_t _3238 = (uint16_t)(60); + _curvea0[85] = _3238; + uint16_t _3239 = (uint16_t)(61); + _curvea0[86] = _3239; + uint16_t _3240 = (uint16_t)(61); + _curvea0[87] = _3240; + uint16_t _3241 = (uint16_t)(62); + _curvea0[88] = _3241; + uint16_t _3242 = (uint16_t)(62); + _curvea0[89] = _3242; + uint16_t _3243 = (uint16_t)(63); + _curvea0[90] = _3243; + uint16_t _3244 = (uint16_t)(63); + _curvea0[91] = _3244; + uint16_t _3245 = (uint16_t)(64); + _curvea0[92] = _3245; + uint16_t _3246 = (uint16_t)(64); + _curvea0[93] = _3246; + uint16_t _3247 = (uint16_t)(64); + _curvea0[94] = _3247; + uint16_t _3248 = (uint16_t)(65); + _curvea0[95] = _3248; + uint16_t _3249 = (uint16_t)(65); + _curvea0[96] = _3249; + uint16_t _3250 = (uint16_t)(66); + _curvea0[97] = _3250; + uint16_t _3251 = (uint16_t)(66); + _curvea0[98] = _3251; + uint16_t _3252 = (uint16_t)(67); + _curvea0[99] = _3252; + uint16_t _3253 = (uint16_t)(67); + _curvea0[100] = _3253; + uint16_t _3254 = (uint16_t)(68); + _curvea0[101] = _3254; + uint16_t _3255 = (uint16_t)(68); + _curvea0[102] = _3255; + uint16_t _3256 = (uint16_t)(68); + _curvea0[103] = _3256; + uint16_t _3257 = (uint16_t)(69); + _curvea0[104] = _3257; + uint16_t _3258 = (uint16_t)(69); + _curvea0[105] = _3258; + uint16_t _3259 = (uint16_t)(70); + _curvea0[106] = _3259; + uint16_t _3260 = (uint16_t)(70); + _curvea0[107] = _3260; + uint16_t _3261 = (uint16_t)(71); + _curvea0[108] = _3261; + uint16_t _3262 = (uint16_t)(71); + _curvea0[109] = _3262; + uint16_t _3263 = (uint16_t)(71); + _curvea0[110] = _3263; + uint16_t _3264 = (uint16_t)(72); + _curvea0[111] = _3264; + uint16_t _3265 = (uint16_t)(72); + _curvea0[112] = _3265; + uint16_t _3266 = (uint16_t)(73); + _curvea0[113] = _3266; + uint16_t _3267 = (uint16_t)(73); + _curvea0[114] = _3267; + uint16_t _3268 = (uint16_t)(74); + _curvea0[115] = _3268; + uint16_t _3269 = (uint16_t)(74); + _curvea0[116] = _3269; + uint16_t _3270 = (uint16_t)(74); + _curvea0[117] = _3270; + uint16_t _3271 = (uint16_t)(75); + _curvea0[118] = _3271; + uint16_t _3272 = (uint16_t)(75); + _curvea0[119] = _3272; + uint16_t _3273 = (uint16_t)(76); + _curvea0[120] = _3273; + uint16_t _3274 = (uint16_t)(76); + _curvea0[121] = _3274; + uint16_t _3275 = (uint16_t)(77); + _curvea0[122] = _3275; + uint16_t _3276 = (uint16_t)(77); + _curvea0[123] = _3276; + uint16_t _3277 = (uint16_t)(77); + _curvea0[124] = _3277; + uint16_t _3278 = (uint16_t)(78); + _curvea0[125] = _3278; + uint16_t _3279 = (uint16_t)(78); + _curvea0[126] = _3279; + uint16_t _3280 = (uint16_t)(79); + _curvea0[127] = _3280; + uint16_t _3281 = (uint16_t)(79); + _curvea0[128] = _3281; + uint16_t _3282 = (uint16_t)(79); + _curvea0[129] = _3282; + uint16_t _3283 = (uint16_t)(80); + _curvea0[130] = _3283; + uint16_t _3284 = (uint16_t)(80); + _curvea0[131] = _3284; + uint16_t _3285 = (uint16_t)(81); + _curvea0[132] = _3285; + uint16_t _3286 = (uint16_t)(81); + _curvea0[133] = _3286; + uint16_t _3287 = (uint16_t)(82); + _curvea0[134] = _3287; + uint16_t _3288 = (uint16_t)(82); + _curvea0[135] = _3288; + uint16_t _3289 = (uint16_t)(82); + _curvea0[136] = _3289; + uint16_t _3290 = (uint16_t)(83); + _curvea0[137] = _3290; + uint16_t _3291 = (uint16_t)(83); + _curvea0[138] = _3291; + uint16_t _3292 = (uint16_t)(84); + _curvea0[139] = _3292; + uint16_t _3293 = (uint16_t)(84); + _curvea0[140] = _3293; + uint16_t _3294 = (uint16_t)(84); + _curvea0[141] = _3294; + uint16_t _3295 = (uint16_t)(85); + _curvea0[142] = _3295; + uint16_t _3296 = (uint16_t)(85); + _curvea0[143] = _3296; + uint16_t _3297 = (uint16_t)(86); + _curvea0[144] = _3297; + uint16_t _3298 = (uint16_t)(86); + _curvea0[145] = _3298; + uint16_t _3299 = (uint16_t)(86); + _curvea0[146] = _3299; + uint16_t _3300 = (uint16_t)(87); + _curvea0[147] = _3300; + uint16_t _3301 = (uint16_t)(87); + _curvea0[148] = _3301; + uint16_t _3302 = (uint16_t)(88); + _curvea0[149] = _3302; + uint16_t _3303 = (uint16_t)(88); + _curvea0[150] = _3303; + uint16_t _3304 = (uint16_t)(88); + _curvea0[151] = _3304; + uint16_t _3305 = (uint16_t)(89); + _curvea0[152] = _3305; + uint16_t _3306 = (uint16_t)(89); + _curvea0[153] = _3306; + uint16_t _3307 = (uint16_t)(90); + _curvea0[154] = _3307; + uint16_t _3308 = (uint16_t)(90); + _curvea0[155] = _3308; + uint16_t _3309 = (uint16_t)(90); + _curvea0[156] = _3309; + uint16_t _3310 = (uint16_t)(91); + _curvea0[157] = _3310; + uint16_t _3311 = (uint16_t)(91); + _curvea0[158] = _3311; + uint16_t _3312 = (uint16_t)(92); + _curvea0[159] = _3312; + uint16_t _3313 = (uint16_t)(92); + _curvea0[160] = _3313; + uint16_t _3314 = (uint16_t)(92); + _curvea0[161] = _3314; + uint16_t _3315 = (uint16_t)(93); + _curvea0[162] = _3315; + uint16_t _3316 = (uint16_t)(93); + _curvea0[163] = _3316; + uint16_t _3317 = (uint16_t)(93); + _curvea0[164] = _3317; + uint16_t _3318 = (uint16_t)(94); + _curvea0[165] = _3318; + uint16_t _3319 = (uint16_t)(94); + _curvea0[166] = _3319; + uint16_t _3320 = (uint16_t)(95); + _curvea0[167] = _3320; + uint16_t _3321 = (uint16_t)(95); + _curvea0[168] = _3321; + uint16_t _3322 = (uint16_t)(95); + _curvea0[169] = _3322; + uint16_t _3323 = (uint16_t)(96); + _curvea0[170] = _3323; + uint16_t _3324 = (uint16_t)(96); + _curvea0[171] = _3324; + uint16_t _3325 = (uint16_t)(97); + _curvea0[172] = _3325; + uint16_t _3326 = (uint16_t)(97); + _curvea0[173] = _3326; + uint16_t _3327 = (uint16_t)(97); + _curvea0[174] = _3327; + uint16_t _3328 = (uint16_t)(98); + _curvea0[175] = _3328; + uint16_t _3329 = (uint16_t)(98); + _curvea0[176] = _3329; + uint16_t _3330 = (uint16_t)(99); + _curvea0[177] = _3330; + uint16_t _3331 = (uint16_t)(99); + _curvea0[178] = _3331; + uint16_t _3332 = (uint16_t)(99); + _curvea0[179] = _3332; + uint16_t _3333 = (uint16_t)(100); + _curvea0[180] = _3333; + uint16_t _3334 = (uint16_t)(100); + _curvea0[181] = _3334; + uint16_t _3335 = (uint16_t)(100); + _curvea0[182] = _3335; + uint16_t _3336 = (uint16_t)(101); + _curvea0[183] = _3336; + uint16_t _3337 = (uint16_t)(101); + _curvea0[184] = _3337; + uint16_t _3338 = (uint16_t)(102); + _curvea0[185] = _3338; + uint16_t _3339 = (uint16_t)(102); + _curvea0[186] = _3339; + uint16_t _3340 = (uint16_t)(102); + _curvea0[187] = _3340; + uint16_t _3341 = (uint16_t)(103); + _curvea0[188] = _3341; + uint16_t _3342 = (uint16_t)(103); + _curvea0[189] = _3342; + uint16_t _3343 = (uint16_t)(103); + _curvea0[190] = _3343; + uint16_t _3344 = (uint16_t)(104); + _curvea0[191] = _3344; + uint16_t _3345 = (uint16_t)(104); + _curvea0[192] = _3345; + uint16_t _3346 = (uint16_t)(105); + _curvea0[193] = _3346; + uint16_t _3347 = (uint16_t)(105); + _curvea0[194] = _3347; + uint16_t _3348 = (uint16_t)(105); + _curvea0[195] = _3348; + uint16_t _3349 = (uint16_t)(106); + _curvea0[196] = _3349; + uint16_t _3350 = (uint16_t)(106); + _curvea0[197] = _3350; + uint16_t _3351 = (uint16_t)(106); + _curvea0[198] = _3351; + uint16_t _3352 = (uint16_t)(107); + _curvea0[199] = _3352; + uint16_t _3353 = (uint16_t)(107); + _curvea0[200] = _3353; + uint16_t _3354 = (uint16_t)(108); + _curvea0[201] = _3354; + uint16_t _3355 = (uint16_t)(108); + _curvea0[202] = _3355; + uint16_t _3356 = (uint16_t)(108); + _curvea0[203] = _3356; + uint16_t _3357 = (uint16_t)(109); + _curvea0[204] = _3357; + uint16_t _3358 = (uint16_t)(109); + _curvea0[205] = _3358; + uint16_t _3359 = (uint16_t)(109); + _curvea0[206] = _3359; + uint16_t _3360 = (uint16_t)(110); + _curvea0[207] = _3360; + uint16_t _3361 = (uint16_t)(110); + _curvea0[208] = _3361; + uint16_t _3362 = (uint16_t)(111); + _curvea0[209] = _3362; + uint16_t _3363 = (uint16_t)(111); + _curvea0[210] = _3363; + uint16_t _3364 = (uint16_t)(111); + _curvea0[211] = _3364; + uint16_t _3365 = (uint16_t)(112); + _curvea0[212] = _3365; + uint16_t _3366 = (uint16_t)(112); + _curvea0[213] = _3366; + uint16_t _3367 = (uint16_t)(112); + _curvea0[214] = _3367; + uint16_t _3368 = (uint16_t)(113); + _curvea0[215] = _3368; + uint16_t _3369 = (uint16_t)(113); + _curvea0[216] = _3369; + uint16_t _3370 = (uint16_t)(113); + _curvea0[217] = _3370; + uint16_t _3371 = (uint16_t)(114); + _curvea0[218] = _3371; + uint16_t _3372 = (uint16_t)(114); + _curvea0[219] = _3372; + uint16_t _3373 = (uint16_t)(115); + _curvea0[220] = _3373; + uint16_t _3374 = (uint16_t)(115); + _curvea0[221] = _3374; + uint16_t _3375 = (uint16_t)(115); + _curvea0[222] = _3375; + uint16_t _3376 = (uint16_t)(116); + _curvea0[223] = _3376; + uint16_t _3377 = (uint16_t)(116); + _curvea0[224] = _3377; + uint16_t _3378 = (uint16_t)(116); + _curvea0[225] = _3378; + uint16_t _3379 = (uint16_t)(117); + _curvea0[226] = _3379; + uint16_t _3380 = (uint16_t)(117); + _curvea0[227] = _3380; + uint16_t _3381 = (uint16_t)(117); + _curvea0[228] = _3381; + uint16_t _3382 = (uint16_t)(118); + _curvea0[229] = _3382; + uint16_t _3383 = (uint16_t)(118); + _curvea0[230] = _3383; + uint16_t _3384 = (uint16_t)(119); + _curvea0[231] = _3384; + uint16_t _3385 = (uint16_t)(119); + _curvea0[232] = _3385; + uint16_t _3386 = (uint16_t)(119); + _curvea0[233] = _3386; + uint16_t _3387 = (uint16_t)(120); + _curvea0[234] = _3387; + uint16_t _3388 = (uint16_t)(120); + _curvea0[235] = _3388; + uint16_t _3389 = (uint16_t)(120); + _curvea0[236] = _3389; + uint16_t _3390 = (uint16_t)(121); + _curvea0[237] = _3390; + uint16_t _3391 = (uint16_t)(121); + _curvea0[238] = _3391; + uint16_t _3392 = (uint16_t)(121); + _curvea0[239] = _3392; + uint16_t _3393 = (uint16_t)(122); + _curvea0[240] = _3393; + uint16_t _3394 = (uint16_t)(122); + _curvea0[241] = _3394; + uint16_t _3395 = (uint16_t)(123); + _curvea0[242] = _3395; + uint16_t _3396 = (uint16_t)(123); + _curvea0[243] = _3396; + uint16_t _3397 = (uint16_t)(123); + _curvea0[244] = _3397; + uint16_t _3398 = (uint16_t)(124); + _curvea0[245] = _3398; + uint16_t _3399 = (uint16_t)(124); + _curvea0[246] = _3399; + uint16_t _3400 = (uint16_t)(124); + _curvea0[247] = _3400; + uint16_t _3401 = (uint16_t)(125); + _curvea0[248] = _3401; + uint16_t _3402 = (uint16_t)(125); + _curvea0[249] = _3402; + uint16_t _3403 = (uint16_t)(125); + _curvea0[250] = _3403; + uint16_t _3404 = (uint16_t)(126); + _curvea0[251] = _3404; + uint16_t _3405 = (uint16_t)(126); + _curvea0[252] = _3405; + uint16_t _3406 = (uint16_t)(126); + _curvea0[253] = _3406; + uint16_t _3407 = (uint16_t)(127); + _curvea0[254] = _3407; + uint16_t _3408 = (uint16_t)(127); + _curvea0[255] = _3408; + uint16_t _3409 = (uint16_t)(128); + _curvea0[256] = _3409; + uint16_t _3410 = (uint16_t)(128); + _curvea0[257] = _3410; + uint16_t _3411 = (uint16_t)(128); + _curvea0[258] = _3411; + uint16_t _3412 = (uint16_t)(129); + _curvea0[259] = _3412; + uint16_t _3413 = (uint16_t)(129); + _curvea0[260] = _3413; + uint16_t _3414 = (uint16_t)(129); + _curvea0[261] = _3414; + uint16_t _3415 = (uint16_t)(130); + _curvea0[262] = _3415; + uint16_t _3416 = (uint16_t)(130); + _curvea0[263] = _3416; + uint16_t _3417 = (uint16_t)(130); + _curvea0[264] = _3417; + uint16_t _3418 = (uint16_t)(131); + _curvea0[265] = _3418; + uint16_t _3419 = (uint16_t)(131); + _curvea0[266] = _3419; + uint16_t _3420 = (uint16_t)(131); + _curvea0[267] = _3420; + uint16_t _3421 = (uint16_t)(132); + _curvea0[268] = _3421; + uint16_t _3422 = (uint16_t)(132); + _curvea0[269] = _3422; + uint16_t _3423 = (uint16_t)(132); + _curvea0[270] = _3423; + uint16_t _3424 = (uint16_t)(133); + _curvea0[271] = _3424; + uint16_t _3425 = (uint16_t)(133); + _curvea0[272] = _3425; + uint16_t _3426 = (uint16_t)(133); + _curvea0[273] = _3426; + uint16_t _3427 = (uint16_t)(134); + _curvea0[274] = _3427; + uint16_t _3428 = (uint16_t)(134); + _curvea0[275] = _3428; + uint16_t _3429 = (uint16_t)(134); + _curvea0[276] = _3429; + uint16_t _3430 = (uint16_t)(135); + _curvea0[277] = _3430; + uint16_t _3431 = (uint16_t)(135); + _curvea0[278] = _3431; + uint16_t _3432 = (uint16_t)(135); + _curvea0[279] = _3432; + uint16_t _3433 = (uint16_t)(136); + _curvea0[280] = _3433; + uint16_t _3434 = (uint16_t)(136); + _curvea0[281] = _3434; + uint16_t _3435 = (uint16_t)(136); + _curvea0[282] = _3435; + uint16_t _3436 = (uint16_t)(137); + _curvea0[283] = _3436; + uint16_t _3437 = (uint16_t)(137); + _curvea0[284] = _3437; + uint16_t _3438 = (uint16_t)(137); + _curvea0[285] = _3438; + uint16_t _3439 = (uint16_t)(138); + _curvea0[286] = _3439; + uint16_t _3440 = (uint16_t)(138); + _curvea0[287] = _3440; + uint16_t _3441 = (uint16_t)(138); + _curvea0[288] = _3441; + uint16_t _3442 = (uint16_t)(139); + _curvea0[289] = _3442; + uint16_t _3443 = (uint16_t)(139); + _curvea0[290] = _3443; + uint16_t _3444 = (uint16_t)(139); + _curvea0[291] = _3444; + uint16_t _3445 = (uint16_t)(140); + _curvea0[292] = _3445; + uint16_t _3446 = (uint16_t)(140); + _curvea0[293] = _3446; + uint16_t _3447 = (uint16_t)(140); + _curvea0[294] = _3447; + uint16_t _3448 = (uint16_t)(141); + _curvea0[295] = _3448; + uint16_t _3449 = (uint16_t)(141); + _curvea0[296] = _3449; + uint16_t _3450 = (uint16_t)(141); + _curvea0[297] = _3450; + uint16_t _3451 = (uint16_t)(141); + _curvea0[298] = _3451; + uint16_t _3452 = (uint16_t)(142); + _curvea0[299] = _3452; + uint16_t _3453 = (uint16_t)(142); + _curvea0[300] = _3453; + uint16_t _3454 = (uint16_t)(142); + _curvea0[301] = _3454; + uint16_t _3455 = (uint16_t)(143); + _curvea0[302] = _3455; + uint16_t _3456 = (uint16_t)(143); + _curvea0[303] = _3456; + uint16_t _3457 = (uint16_t)(143); + _curvea0[304] = _3457; + uint16_t _3458 = (uint16_t)(144); + _curvea0[305] = _3458; + uint16_t _3459 = (uint16_t)(144); + _curvea0[306] = _3459; + uint16_t _3460 = (uint16_t)(144); + _curvea0[307] = _3460; + uint16_t _3461 = (uint16_t)(145); + _curvea0[308] = _3461; + uint16_t _3462 = (uint16_t)(145); + _curvea0[309] = _3462; + uint16_t _3463 = (uint16_t)(145); + _curvea0[310] = _3463; + uint16_t _3464 = (uint16_t)(145); + _curvea0[311] = _3464; + uint16_t _3465 = (uint16_t)(146); + _curvea0[312] = _3465; + uint16_t _3466 = (uint16_t)(146); + _curvea0[313] = _3466; + uint16_t _3467 = (uint16_t)(146); + _curvea0[314] = _3467; + uint16_t _3468 = (uint16_t)(147); + _curvea0[315] = _3468; + uint16_t _3469 = (uint16_t)(147); + _curvea0[316] = _3469; + uint16_t _3470 = (uint16_t)(147); + _curvea0[317] = _3470; + uint16_t _3471 = (uint16_t)(148); + _curvea0[318] = _3471; + uint16_t _3472 = (uint16_t)(148); + _curvea0[319] = _3472; + uint16_t _3473 = (uint16_t)(148); + _curvea0[320] = _3473; + uint16_t _3474 = (uint16_t)(148); + _curvea0[321] = _3474; + uint16_t _3475 = (uint16_t)(149); + _curvea0[322] = _3475; + uint16_t _3476 = (uint16_t)(149); + _curvea0[323] = _3476; + uint16_t _3477 = (uint16_t)(149); + _curvea0[324] = _3477; + uint16_t _3478 = (uint16_t)(150); + _curvea0[325] = _3478; + uint16_t _3479 = (uint16_t)(150); + _curvea0[326] = _3479; + uint16_t _3480 = (uint16_t)(150); + _curvea0[327] = _3480; + uint16_t _3481 = (uint16_t)(150); + _curvea0[328] = _3481; + uint16_t _3482 = (uint16_t)(151); + _curvea0[329] = _3482; + uint16_t _3483 = (uint16_t)(151); + _curvea0[330] = _3483; + uint16_t _3484 = (uint16_t)(151); + _curvea0[331] = _3484; + uint16_t _3485 = (uint16_t)(152); + _curvea0[332] = _3485; + uint16_t _3486 = (uint16_t)(152); + _curvea0[333] = _3486; + uint16_t _3487 = (uint16_t)(152); + _curvea0[334] = _3487; + uint16_t _3488 = (uint16_t)(152); + _curvea0[335] = _3488; + uint16_t _3489 = (uint16_t)(153); + _curvea0[336] = _3489; + uint16_t _3490 = (uint16_t)(153); + _curvea0[337] = _3490; + uint16_t _3491 = (uint16_t)(153); + _curvea0[338] = _3491; + uint16_t _3492 = (uint16_t)(154); + _curvea0[339] = _3492; + uint16_t _3493 = (uint16_t)(154); + _curvea0[340] = _3493; + uint16_t _3494 = (uint16_t)(154); + _curvea0[341] = _3494; + uint16_t _3495 = (uint16_t)(154); + _curvea0[342] = _3495; + uint16_t _3496 = (uint16_t)(155); + _curvea0[343] = _3496; + uint16_t _3497 = (uint16_t)(155); + _curvea0[344] = _3497; + uint16_t _3498 = (uint16_t)(155); + _curvea0[345] = _3498; + uint16_t _3499 = (uint16_t)(156); + _curvea0[346] = _3499; + uint16_t _3500 = (uint16_t)(156); + _curvea0[347] = _3500; + uint16_t _3501 = (uint16_t)(156); + _curvea0[348] = _3501; + uint16_t _3502 = (uint16_t)(156); + _curvea0[349] = _3502; + uint16_t _3503 = (uint16_t)(157); + _curvea0[350] = _3503; + uint16_t _3504 = (uint16_t)(157); + _curvea0[351] = _3504; + uint16_t _3505 = (uint16_t)(157); + _curvea0[352] = _3505; + uint16_t _3506 = (uint16_t)(157); + _curvea0[353] = _3506; + uint16_t _3507 = (uint16_t)(158); + _curvea0[354] = _3507; + uint16_t _3508 = (uint16_t)(158); + _curvea0[355] = _3508; + uint16_t _3509 = (uint16_t)(158); + _curvea0[356] = _3509; + uint16_t _3510 = (uint16_t)(159); + _curvea0[357] = _3510; + uint16_t _3511 = (uint16_t)(159); + _curvea0[358] = _3511; + uint16_t _3512 = (uint16_t)(159); + _curvea0[359] = _3512; + uint16_t _3513 = (uint16_t)(159); + _curvea0[360] = _3513; + uint16_t _3514 = (uint16_t)(160); + _curvea0[361] = _3514; + uint16_t _3515 = (uint16_t)(160); + _curvea0[362] = _3515; + uint16_t _3516 = (uint16_t)(160); + _curvea0[363] = _3516; + uint16_t _3517 = (uint16_t)(160); + _curvea0[364] = _3517; + uint16_t _3518 = (uint16_t)(161); + _curvea0[365] = _3518; + uint16_t _3519 = (uint16_t)(161); + _curvea0[366] = _3519; + uint16_t _3520 = (uint16_t)(161); + _curvea0[367] = _3520; + uint16_t _3521 = (uint16_t)(161); + _curvea0[368] = _3521; + uint16_t _3522 = (uint16_t)(162); + _curvea0[369] = _3522; + uint16_t _3523 = (uint16_t)(162); + _curvea0[370] = _3523; + uint16_t _3524 = (uint16_t)(162); + _curvea0[371] = _3524; + uint16_t _3525 = (uint16_t)(162); + _curvea0[372] = _3525; + uint16_t _3526 = (uint16_t)(163); + _curvea0[373] = _3526; + uint16_t _3527 = (uint16_t)(163); + _curvea0[374] = _3527; + uint16_t _3528 = (uint16_t)(163); + _curvea0[375] = _3528; + uint16_t _3529 = (uint16_t)(163); + _curvea0[376] = _3529; + uint16_t _3530 = (uint16_t)(164); + _curvea0[377] = _3530; + uint16_t _3531 = (uint16_t)(164); + _curvea0[378] = _3531; + uint16_t _3532 = (uint16_t)(164); + _curvea0[379] = _3532; + uint16_t _3533 = (uint16_t)(164); + _curvea0[380] = _3533; + uint16_t _3534 = (uint16_t)(165); + _curvea0[381] = _3534; + uint16_t _3535 = (uint16_t)(165); + _curvea0[382] = _3535; + uint16_t _3536 = (uint16_t)(165); + _curvea0[383] = _3536; + uint16_t _3537 = (uint16_t)(166); + _curvea0[384] = _3537; + uint16_t _3538 = (uint16_t)(166); + _curvea0[385] = _3538; + uint16_t _3539 = (uint16_t)(166); + _curvea0[386] = _3539; + uint16_t _3540 = (uint16_t)(166); + _curvea0[387] = _3540; + uint16_t _3541 = (uint16_t)(167); + _curvea0[388] = _3541; + uint16_t _3542 = (uint16_t)(167); + _curvea0[389] = _3542; + uint16_t _3543 = (uint16_t)(167); + _curvea0[390] = _3543; + uint16_t _3544 = (uint16_t)(167); + _curvea0[391] = _3544; + uint16_t _3545 = (uint16_t)(167); + _curvea0[392] = _3545; + uint16_t _3546 = (uint16_t)(168); + _curvea0[393] = _3546; + uint16_t _3547 = (uint16_t)(168); + _curvea0[394] = _3547; + uint16_t _3548 = (uint16_t)(168); + _curvea0[395] = _3548; + uint16_t _3549 = (uint16_t)(168); + _curvea0[396] = _3549; + uint16_t _3550 = (uint16_t)(169); + _curvea0[397] = _3550; + uint16_t _3551 = (uint16_t)(169); + _curvea0[398] = _3551; + uint16_t _3552 = (uint16_t)(169); + _curvea0[399] = _3552; + uint16_t _3553 = (uint16_t)(169); + _curvea0[400] = _3553; + uint16_t _3554 = (uint16_t)(170); + _curvea0[401] = _3554; + uint16_t _3555 = (uint16_t)(170); + _curvea0[402] = _3555; + uint16_t _3556 = (uint16_t)(170); + _curvea0[403] = _3556; + uint16_t _3557 = (uint16_t)(170); + _curvea0[404] = _3557; + uint16_t _3558 = (uint16_t)(171); + _curvea0[405] = _3558; + uint16_t _3559 = (uint16_t)(171); + _curvea0[406] = _3559; + uint16_t _3560 = (uint16_t)(171); + _curvea0[407] = _3560; + uint16_t _3561 = (uint16_t)(171); + _curvea0[408] = _3561; + uint16_t _3562 = (uint16_t)(172); + _curvea0[409] = _3562; + uint16_t _3563 = (uint16_t)(172); + _curvea0[410] = _3563; + uint16_t _3564 = (uint16_t)(172); + _curvea0[411] = _3564; + uint16_t _3565 = (uint16_t)(172); + _curvea0[412] = _3565; + uint16_t _3566 = (uint16_t)(173); + _curvea0[413] = _3566; + uint16_t _3567 = (uint16_t)(173); + _curvea0[414] = _3567; + uint16_t _3568 = (uint16_t)(173); + _curvea0[415] = _3568; + uint16_t _3569 = (uint16_t)(173); + _curvea0[416] = _3569; + uint16_t _3570 = (uint16_t)(173); + _curvea0[417] = _3570; + uint16_t _3571 = (uint16_t)(174); + _curvea0[418] = _3571; + uint16_t _3572 = (uint16_t)(174); + _curvea0[419] = _3572; + uint16_t _3573 = (uint16_t)(174); + _curvea0[420] = _3573; + uint16_t _3574 = (uint16_t)(174); + _curvea0[421] = _3574; + uint16_t _3575 = (uint16_t)(175); + _curvea0[422] = _3575; + uint16_t _3576 = (uint16_t)(175); + _curvea0[423] = _3576; + uint16_t _3577 = (uint16_t)(175); + _curvea0[424] = _3577; + uint16_t _3578 = (uint16_t)(175); + _curvea0[425] = _3578; + uint16_t _3579 = (uint16_t)(176); + _curvea0[426] = _3579; + uint16_t _3580 = (uint16_t)(176); + _curvea0[427] = _3580; + uint16_t _3581 = (uint16_t)(176); + _curvea0[428] = _3581; + uint16_t _3582 = (uint16_t)(176); + _curvea0[429] = _3582; + uint16_t _3583 = (uint16_t)(176); + _curvea0[430] = _3583; + uint16_t _3584 = (uint16_t)(177); + _curvea0[431] = _3584; + uint16_t _3585 = (uint16_t)(177); + _curvea0[432] = _3585; + uint16_t _3586 = (uint16_t)(177); + _curvea0[433] = _3586; + uint16_t _3587 = (uint16_t)(177); + _curvea0[434] = _3587; + uint16_t _3588 = (uint16_t)(178); + _curvea0[435] = _3588; + uint16_t _3589 = (uint16_t)(178); + _curvea0[436] = _3589; + uint16_t _3590 = (uint16_t)(178); + _curvea0[437] = _3590; + uint16_t _3591 = (uint16_t)(178); + _curvea0[438] = _3591; + uint16_t _3592 = (uint16_t)(178); + _curvea0[439] = _3592; + uint16_t _3593 = (uint16_t)(179); + _curvea0[440] = _3593; + uint16_t _3594 = (uint16_t)(179); + _curvea0[441] = _3594; + uint16_t _3595 = (uint16_t)(179); + _curvea0[442] = _3595; + uint16_t _3596 = (uint16_t)(179); + _curvea0[443] = _3596; + uint16_t _3597 = (uint16_t)(180); + _curvea0[444] = _3597; + uint16_t _3598 = (uint16_t)(180); + _curvea0[445] = _3598; + uint16_t _3599 = (uint16_t)(180); + _curvea0[446] = _3599; + uint16_t _3600 = (uint16_t)(180); + _curvea0[447] = _3600; + uint16_t _3601 = (uint16_t)(180); + _curvea0[448] = _3601; + uint16_t _3602 = (uint16_t)(181); + _curvea0[449] = _3602; + uint16_t _3603 = (uint16_t)(181); + _curvea0[450] = _3603; + uint16_t _3604 = (uint16_t)(181); + _curvea0[451] = _3604; + uint16_t _3605 = (uint16_t)(181); + _curvea0[452] = _3605; + uint16_t _3606 = (uint16_t)(181); + _curvea0[453] = _3606; + uint16_t _3607 = (uint16_t)(182); + _curvea0[454] = _3607; + uint16_t _3608 = (uint16_t)(182); + _curvea0[455] = _3608; + uint16_t _3609 = (uint16_t)(182); + _curvea0[456] = _3609; + uint16_t _3610 = (uint16_t)(182); + _curvea0[457] = _3610; + uint16_t _3611 = (uint16_t)(183); + _curvea0[458] = _3611; + uint16_t _3612 = (uint16_t)(183); + _curvea0[459] = _3612; + uint16_t _3613 = (uint16_t)(183); + _curvea0[460] = _3613; + uint16_t _3614 = (uint16_t)(183); + _curvea0[461] = _3614; + uint16_t _3615 = (uint16_t)(183); + _curvea0[462] = _3615; + uint16_t _3616 = (uint16_t)(184); + _curvea0[463] = _3616; + uint16_t _3617 = (uint16_t)(184); + _curvea0[464] = _3617; + uint16_t _3618 = (uint16_t)(184); + _curvea0[465] = _3618; + uint16_t _3619 = (uint16_t)(184); + _curvea0[466] = _3619; + uint16_t _3620 = (uint16_t)(184); + _curvea0[467] = _3620; + uint16_t _3621 = (uint16_t)(185); + _curvea0[468] = _3621; + uint16_t _3622 = (uint16_t)(185); + _curvea0[469] = _3622; + uint16_t _3623 = (uint16_t)(185); + _curvea0[470] = _3623; + uint16_t _3624 = (uint16_t)(185); + _curvea0[471] = _3624; + uint16_t _3625 = (uint16_t)(185); + _curvea0[472] = _3625; + uint16_t _3626 = (uint16_t)(186); + _curvea0[473] = _3626; + uint16_t _3627 = (uint16_t)(186); + _curvea0[474] = _3627; + uint16_t _3628 = (uint16_t)(186); + _curvea0[475] = _3628; + uint16_t _3629 = (uint16_t)(186); + _curvea0[476] = _3629; + uint16_t _3630 = (uint16_t)(187); + _curvea0[477] = _3630; + uint16_t _3631 = (uint16_t)(187); + _curvea0[478] = _3631; + uint16_t _3632 = (uint16_t)(187); + _curvea0[479] = _3632; + uint16_t _3633 = (uint16_t)(187); + _curvea0[480] = _3633; + uint16_t _3634 = (uint16_t)(187); + _curvea0[481] = _3634; + uint16_t _3635 = (uint16_t)(188); + _curvea0[482] = _3635; + uint16_t _3636 = (uint16_t)(188); + _curvea0[483] = _3636; + uint16_t _3637 = (uint16_t)(188); + _curvea0[484] = _3637; + uint16_t _3638 = (uint16_t)(188); + _curvea0[485] = _3638; + uint16_t _3639 = (uint16_t)(188); + _curvea0[486] = _3639; + uint16_t _3640 = (uint16_t)(189); + _curvea0[487] = _3640; + uint16_t _3641 = (uint16_t)(189); + _curvea0[488] = _3641; + uint16_t _3642 = (uint16_t)(189); + _curvea0[489] = _3642; + uint16_t _3643 = (uint16_t)(189); + _curvea0[490] = _3643; + uint16_t _3644 = (uint16_t)(189); + _curvea0[491] = _3644; + uint16_t _3645 = (uint16_t)(190); + _curvea0[492] = _3645; + uint16_t _3646 = (uint16_t)(190); + _curvea0[493] = _3646; + uint16_t _3647 = (uint16_t)(190); + _curvea0[494] = _3647; + uint16_t _3648 = (uint16_t)(190); + _curvea0[495] = _3648; + uint16_t _3649 = (uint16_t)(190); + _curvea0[496] = _3649; + uint16_t _3650 = (uint16_t)(190); + _curvea0[497] = _3650; + uint16_t _3651 = (uint16_t)(191); + _curvea0[498] = _3651; + uint16_t _3652 = (uint16_t)(191); + _curvea0[499] = _3652; + uint16_t _3653 = (uint16_t)(191); + _curvea0[500] = _3653; + uint16_t _3654 = (uint16_t)(191); + _curvea0[501] = _3654; + uint16_t _3655 = (uint16_t)(191); + _curvea0[502] = _3655; + uint16_t _3656 = (uint16_t)(192); + _curvea0[503] = _3656; + uint16_t _3657 = (uint16_t)(192); + _curvea0[504] = _3657; + uint16_t _3658 = (uint16_t)(192); + _curvea0[505] = _3658; + uint16_t _3659 = (uint16_t)(192); + _curvea0[506] = _3659; + uint16_t _3660 = (uint16_t)(192); + _curvea0[507] = _3660; + uint16_t _3661 = (uint16_t)(193); + _curvea0[508] = _3661; + uint16_t _3662 = (uint16_t)(193); + _curvea0[509] = _3662; + uint16_t _3663 = (uint16_t)(193); + _curvea0[510] = _3663; + uint16_t _3664 = (uint16_t)(193); + _curvea0[511] = _3664; + uint16_t _3665 = (uint16_t)(193); + _curvea0[512] = _3665; + uint16_t _3666 = (uint16_t)(194); + _curvea0[513] = _3666; + uint16_t _3667 = (uint16_t)(194); + _curvea0[514] = _3667; + uint16_t _3668 = (uint16_t)(194); + _curvea0[515] = _3668; + uint16_t _3669 = (uint16_t)(194); + _curvea0[516] = _3669; + uint16_t _3670 = (uint16_t)(194); + _curvea0[517] = _3670; + uint16_t _3671 = (uint16_t)(195); + _curvea0[518] = _3671; + uint16_t _3672 = (uint16_t)(195); + _curvea0[519] = _3672; + uint16_t _3673 = (uint16_t)(195); + _curvea0[520] = _3673; + uint16_t _3674 = (uint16_t)(195); + _curvea0[521] = _3674; + uint16_t _3675 = (uint16_t)(195); + _curvea0[522] = _3675; + uint16_t _3676 = (uint16_t)(195); + _curvea0[523] = _3676; + uint16_t _3677 = (uint16_t)(196); + _curvea0[524] = _3677; + uint16_t _3678 = (uint16_t)(196); + _curvea0[525] = _3678; + uint16_t _3679 = (uint16_t)(196); + _curvea0[526] = _3679; + uint16_t _3680 = (uint16_t)(196); + _curvea0[527] = _3680; + uint16_t _3681 = (uint16_t)(196); + _curvea0[528] = _3681; + uint16_t _3682 = (uint16_t)(197); + _curvea0[529] = _3682; + uint16_t _3683 = (uint16_t)(197); + _curvea0[530] = _3683; + uint16_t _3684 = (uint16_t)(197); + _curvea0[531] = _3684; + uint16_t _3685 = (uint16_t)(197); + _curvea0[532] = _3685; + uint16_t _3686 = (uint16_t)(197); + _curvea0[533] = _3686; + uint16_t _3687 = (uint16_t)(197); + _curvea0[534] = _3687; + uint16_t _3688 = (uint16_t)(198); + _curvea0[535] = _3688; + uint16_t _3689 = (uint16_t)(198); + _curvea0[536] = _3689; + uint16_t _3690 = (uint16_t)(198); + _curvea0[537] = _3690; + uint16_t _3691 = (uint16_t)(198); + _curvea0[538] = _3691; + uint16_t _3692 = (uint16_t)(198); + _curvea0[539] = _3692; + uint16_t _3693 = (uint16_t)(199); + _curvea0[540] = _3693; + uint16_t _3694 = (uint16_t)(199); + _curvea0[541] = _3694; + uint16_t _3695 = (uint16_t)(199); + _curvea0[542] = _3695; + uint16_t _3696 = (uint16_t)(199); + _curvea0[543] = _3696; + uint16_t _3697 = (uint16_t)(199); + _curvea0[544] = _3697; + uint16_t _3698 = (uint16_t)(199); + _curvea0[545] = _3698; + uint16_t _3699 = (uint16_t)(200); + _curvea0[546] = _3699; + uint16_t _3700 = (uint16_t)(200); + _curvea0[547] = _3700; + uint16_t _3701 = (uint16_t)(200); + _curvea0[548] = _3701; + uint16_t _3702 = (uint16_t)(200); + _curvea0[549] = _3702; + uint16_t _3703 = (uint16_t)(200); + _curvea0[550] = _3703; + uint16_t _3704 = (uint16_t)(200); + _curvea0[551] = _3704; + uint16_t _3705 = (uint16_t)(201); + _curvea0[552] = _3705; + uint16_t _3706 = (uint16_t)(201); + _curvea0[553] = _3706; + uint16_t _3707 = (uint16_t)(201); + _curvea0[554] = _3707; + uint16_t _3708 = (uint16_t)(201); + _curvea0[555] = _3708; + uint16_t _3709 = (uint16_t)(201); + _curvea0[556] = _3709; + uint16_t _3710 = (uint16_t)(202); + _curvea0[557] = _3710; + uint16_t _3711 = (uint16_t)(202); + _curvea0[558] = _3711; + uint16_t _3712 = (uint16_t)(202); + _curvea0[559] = _3712; + uint16_t _3713 = (uint16_t)(202); + _curvea0[560] = _3713; + uint16_t _3714 = (uint16_t)(202); + _curvea0[561] = _3714; + uint16_t _3715 = (uint16_t)(202); + _curvea0[562] = _3715; + uint16_t _3716 = (uint16_t)(203); + _curvea0[563] = _3716; + uint16_t _3717 = (uint16_t)(203); + _curvea0[564] = _3717; + uint16_t _3718 = (uint16_t)(203); + _curvea0[565] = _3718; + uint16_t _3719 = (uint16_t)(203); + _curvea0[566] = _3719; + uint16_t _3720 = (uint16_t)(203); + _curvea0[567] = _3720; + uint16_t _3721 = (uint16_t)(203); + _curvea0[568] = _3721; + uint16_t _3722 = (uint16_t)(204); + _curvea0[569] = _3722; + uint16_t _3723 = (uint16_t)(204); + _curvea0[570] = _3723; + uint16_t _3724 = (uint16_t)(204); + _curvea0[571] = _3724; + uint16_t _3725 = (uint16_t)(204); + _curvea0[572] = _3725; + uint16_t _3726 = (uint16_t)(204); + _curvea0[573] = _3726; + uint16_t _3727 = (uint16_t)(204); + _curvea0[574] = _3727; + uint16_t _3728 = (uint16_t)(205); + _curvea0[575] = _3728; + uint16_t _3729 = (uint16_t)(205); + _curvea0[576] = _3729; + uint16_t _3730 = (uint16_t)(205); + _curvea0[577] = _3730; + uint16_t _3731 = (uint16_t)(205); + _curvea0[578] = _3731; + uint16_t _3732 = (uint16_t)(205); + _curvea0[579] = _3732; + uint16_t _3733 = (uint16_t)(205); + _curvea0[580] = _3733; + uint16_t _3734 = (uint16_t)(206); + _curvea0[581] = _3734; + uint16_t _3735 = (uint16_t)(206); + _curvea0[582] = _3735; + uint16_t _3736 = (uint16_t)(206); + _curvea0[583] = _3736; + uint16_t _3737 = (uint16_t)(206); + _curvea0[584] = _3737; + uint16_t _3738 = (uint16_t)(206); + _curvea0[585] = _3738; + uint16_t _3739 = (uint16_t)(206); + _curvea0[586] = _3739; + uint16_t _3740 = (uint16_t)(207); + _curvea0[587] = _3740; + uint16_t _3741 = (uint16_t)(207); + _curvea0[588] = _3741; + uint16_t _3742 = (uint16_t)(207); + _curvea0[589] = _3742; + uint16_t _3743 = (uint16_t)(207); + _curvea0[590] = _3743; + uint16_t _3744 = (uint16_t)(207); + _curvea0[591] = _3744; + uint16_t _3745 = (uint16_t)(207); + _curvea0[592] = _3745; + uint16_t _3746 = (uint16_t)(208); + _curvea0[593] = _3746; + uint16_t _3747 = (uint16_t)(208); + _curvea0[594] = _3747; + uint16_t _3748 = (uint16_t)(208); + _curvea0[595] = _3748; + uint16_t _3749 = (uint16_t)(208); + _curvea0[596] = _3749; + uint16_t _3750 = (uint16_t)(208); + _curvea0[597] = _3750; + uint16_t _3751 = (uint16_t)(208); + _curvea0[598] = _3751; + uint16_t _3752 = (uint16_t)(209); + _curvea0[599] = _3752; + uint16_t _3753 = (uint16_t)(209); + _curvea0[600] = _3753; + uint16_t _3754 = (uint16_t)(209); + _curvea0[601] = _3754; + uint16_t _3755 = (uint16_t)(209); + _curvea0[602] = _3755; + uint16_t _3756 = (uint16_t)(209); + _curvea0[603] = _3756; + uint16_t _3757 = (uint16_t)(209); + _curvea0[604] = _3757; + uint16_t _3758 = (uint16_t)(209); + _curvea0[605] = _3758; + uint16_t _3759 = (uint16_t)(210); + _curvea0[606] = _3759; + uint16_t _3760 = (uint16_t)(210); + _curvea0[607] = _3760; + uint16_t _3761 = (uint16_t)(210); + _curvea0[608] = _3761; + uint16_t _3762 = (uint16_t)(210); + _curvea0[609] = _3762; + uint16_t _3763 = (uint16_t)(210); + _curvea0[610] = _3763; + uint16_t _3764 = (uint16_t)(210); + _curvea0[611] = _3764; + uint16_t _3765 = (uint16_t)(211); + _curvea0[612] = _3765; + uint16_t _3766 = (uint16_t)(211); + _curvea0[613] = _3766; + uint16_t _3767 = (uint16_t)(211); + _curvea0[614] = _3767; + uint16_t _3768 = (uint16_t)(211); + _curvea0[615] = _3768; + uint16_t _3769 = (uint16_t)(211); + _curvea0[616] = _3769; + uint16_t _3770 = (uint16_t)(211); + _curvea0[617] = _3770; + uint16_t _3771 = (uint16_t)(211); + _curvea0[618] = _3771; + uint16_t _3772 = (uint16_t)(212); + _curvea0[619] = _3772; + uint16_t _3773 = (uint16_t)(212); + _curvea0[620] = _3773; + uint16_t _3774 = (uint16_t)(212); + _curvea0[621] = _3774; + uint16_t _3775 = (uint16_t)(212); + _curvea0[622] = _3775; + uint16_t _3776 = (uint16_t)(212); + _curvea0[623] = _3776; + uint16_t _3777 = (uint16_t)(212); + _curvea0[624] = _3777; + uint16_t _3778 = (uint16_t)(213); + _curvea0[625] = _3778; + uint16_t _3779 = (uint16_t)(213); + _curvea0[626] = _3779; + uint16_t _3780 = (uint16_t)(213); + _curvea0[627] = _3780; + uint16_t _3781 = (uint16_t)(213); + _curvea0[628] = _3781; + uint16_t _3782 = (uint16_t)(213); + _curvea0[629] = _3782; + uint16_t _3783 = (uint16_t)(213); + _curvea0[630] = _3783; + uint16_t _3784 = (uint16_t)(213); + _curvea0[631] = _3784; + uint16_t _3785 = (uint16_t)(214); + _curvea0[632] = _3785; + uint16_t _3786 = (uint16_t)(214); + _curvea0[633] = _3786; + uint16_t _3787 = (uint16_t)(214); + _curvea0[634] = _3787; + uint16_t _3788 = (uint16_t)(214); + _curvea0[635] = _3788; + uint16_t _3789 = (uint16_t)(214); + _curvea0[636] = _3789; + uint16_t _3790 = (uint16_t)(214); + _curvea0[637] = _3790; + uint16_t _3791 = (uint16_t)(214); + _curvea0[638] = _3791; + uint16_t _3792 = (uint16_t)(215); + _curvea0[639] = _3792; + uint16_t _3793 = (uint16_t)(215); + _curvea0[640] = _3793; + uint16_t _3794 = (uint16_t)(215); + _curvea0[641] = _3794; + uint16_t _3795 = (uint16_t)(215); + _curvea0[642] = _3795; + uint16_t _3796 = (uint16_t)(215); + _curvea0[643] = _3796; + uint16_t _3797 = (uint16_t)(215); + _curvea0[644] = _3797; + uint16_t _3798 = (uint16_t)(216); + _curvea0[645] = _3798; + uint16_t _3799 = (uint16_t)(216); + _curvea0[646] = _3799; + uint16_t _3800 = (uint16_t)(216); + _curvea0[647] = _3800; + uint16_t _3801 = (uint16_t)(216); + _curvea0[648] = _3801; + uint16_t _3802 = (uint16_t)(216); + _curvea0[649] = _3802; + uint16_t _3803 = (uint16_t)(216); + _curvea0[650] = _3803; + uint16_t _3804 = (uint16_t)(216); + _curvea0[651] = _3804; + uint16_t _3805 = (uint16_t)(217); + _curvea0[652] = _3805; + uint16_t _3806 = (uint16_t)(217); + _curvea0[653] = _3806; + uint16_t _3807 = (uint16_t)(217); + _curvea0[654] = _3807; + uint16_t _3808 = (uint16_t)(217); + _curvea0[655] = _3808; + uint16_t _3809 = (uint16_t)(217); + _curvea0[656] = _3809; + uint16_t _3810 = (uint16_t)(217); + _curvea0[657] = _3810; + uint16_t _3811 = (uint16_t)(217); + _curvea0[658] = _3811; + uint16_t _3812 = (uint16_t)(218); + _curvea0[659] = _3812; + uint16_t _3813 = (uint16_t)(218); + _curvea0[660] = _3813; + uint16_t _3814 = (uint16_t)(218); + _curvea0[661] = _3814; + uint16_t _3815 = (uint16_t)(218); + _curvea0[662] = _3815; + uint16_t _3816 = (uint16_t)(218); + _curvea0[663] = _3816; + uint16_t _3817 = (uint16_t)(218); + _curvea0[664] = _3817; + uint16_t _3818 = (uint16_t)(218); + _curvea0[665] = _3818; + uint16_t _3819 = (uint16_t)(219); + _curvea0[666] = _3819; + uint16_t _3820 = (uint16_t)(219); + _curvea0[667] = _3820; + uint16_t _3821 = (uint16_t)(219); + _curvea0[668] = _3821; + uint16_t _3822 = (uint16_t)(219); + _curvea0[669] = _3822; + uint16_t _3823 = (uint16_t)(219); + _curvea0[670] = _3823; + uint16_t _3824 = (uint16_t)(219); + _curvea0[671] = _3824; + uint16_t _3825 = (uint16_t)(219); + _curvea0[672] = _3825; + uint16_t _3826 = (uint16_t)(220); + _curvea0[673] = _3826; + uint16_t _3827 = (uint16_t)(220); + _curvea0[674] = _3827; + uint16_t _3828 = (uint16_t)(220); + _curvea0[675] = _3828; + uint16_t _3829 = (uint16_t)(220); + _curvea0[676] = _3829; + uint16_t _3830 = (uint16_t)(220); + _curvea0[677] = _3830; + uint16_t _3831 = (uint16_t)(220); + _curvea0[678] = _3831; + uint16_t _3832 = (uint16_t)(220); + _curvea0[679] = _3832; + uint16_t _3833 = (uint16_t)(220); + _curvea0[680] = _3833; + uint16_t _3834 = (uint16_t)(221); + _curvea0[681] = _3834; + uint16_t _3835 = (uint16_t)(221); + _curvea0[682] = _3835; + uint16_t _3836 = (uint16_t)(221); + _curvea0[683] = _3836; + uint16_t _3837 = (uint16_t)(221); + _curvea0[684] = _3837; + uint16_t _3838 = (uint16_t)(221); + _curvea0[685] = _3838; + uint16_t _3839 = (uint16_t)(221); + _curvea0[686] = _3839; + uint16_t _3840 = (uint16_t)(221); + _curvea0[687] = _3840; + uint16_t _3841 = (uint16_t)(222); + _curvea0[688] = _3841; + uint16_t _3842 = (uint16_t)(222); + _curvea0[689] = _3842; + uint16_t _3843 = (uint16_t)(222); + _curvea0[690] = _3843; + uint16_t _3844 = (uint16_t)(222); + _curvea0[691] = _3844; + uint16_t _3845 = (uint16_t)(222); + _curvea0[692] = _3845; + uint16_t _3846 = (uint16_t)(222); + _curvea0[693] = _3846; + uint16_t _3847 = (uint16_t)(222); + _curvea0[694] = _3847; + uint16_t _3848 = (uint16_t)(223); + _curvea0[695] = _3848; + uint16_t _3849 = (uint16_t)(223); + _curvea0[696] = _3849; + uint16_t _3850 = (uint16_t)(223); + _curvea0[697] = _3850; + uint16_t _3851 = (uint16_t)(223); + _curvea0[698] = _3851; + uint16_t _3852 = (uint16_t)(223); + _curvea0[699] = _3852; + uint16_t _3853 = (uint16_t)(223); + _curvea0[700] = _3853; + uint16_t _3854 = (uint16_t)(223); + _curvea0[701] = _3854; + uint16_t _3855 = (uint16_t)(223); + _curvea0[702] = _3855; + uint16_t _3856 = (uint16_t)(224); + _curvea0[703] = _3856; + uint16_t _3857 = (uint16_t)(224); + _curvea0[704] = _3857; + uint16_t _3858 = (uint16_t)(224); + _curvea0[705] = _3858; + uint16_t _3859 = (uint16_t)(224); + _curvea0[706] = _3859; + uint16_t _3860 = (uint16_t)(224); + _curvea0[707] = _3860; + uint16_t _3861 = (uint16_t)(224); + _curvea0[708] = _3861; + uint16_t _3862 = (uint16_t)(224); + _curvea0[709] = _3862; + uint16_t _3863 = (uint16_t)(224); + _curvea0[710] = _3863; + uint16_t _3864 = (uint16_t)(225); + _curvea0[711] = _3864; + uint16_t _3865 = (uint16_t)(225); + _curvea0[712] = _3865; + uint16_t _3866 = (uint16_t)(225); + _curvea0[713] = _3866; + uint16_t _3867 = (uint16_t)(225); + _curvea0[714] = _3867; + uint16_t _3868 = (uint16_t)(225); + _curvea0[715] = _3868; + uint16_t _3869 = (uint16_t)(225); + _curvea0[716] = _3869; + uint16_t _3870 = (uint16_t)(225); + _curvea0[717] = _3870; + uint16_t _3871 = (uint16_t)(226); + _curvea0[718] = _3871; + uint16_t _3872 = (uint16_t)(226); + _curvea0[719] = _3872; + uint16_t _3873 = (uint16_t)(226); + _curvea0[720] = _3873; + uint16_t _3874 = (uint16_t)(226); + _curvea0[721] = _3874; + uint16_t _3875 = (uint16_t)(226); + _curvea0[722] = _3875; + uint16_t _3876 = (uint16_t)(226); + _curvea0[723] = _3876; + uint16_t _3877 = (uint16_t)(226); + _curvea0[724] = _3877; + uint16_t _3878 = (uint16_t)(226); + _curvea0[725] = _3878; + uint16_t _3879 = (uint16_t)(227); + _curvea0[726] = _3879; + uint16_t _3880 = (uint16_t)(227); + _curvea0[727] = _3880; + uint16_t _3881 = (uint16_t)(227); + _curvea0[728] = _3881; + uint16_t _3882 = (uint16_t)(227); + _curvea0[729] = _3882; + uint16_t _3883 = (uint16_t)(227); + _curvea0[730] = _3883; + uint16_t _3884 = (uint16_t)(227); + _curvea0[731] = _3884; + uint16_t _3885 = (uint16_t)(227); + _curvea0[732] = _3885; + uint16_t _3886 = (uint16_t)(227); + _curvea0[733] = _3886; + uint16_t _3887 = (uint16_t)(228); + _curvea0[734] = _3887; + uint16_t _3888 = (uint16_t)(228); + _curvea0[735] = _3888; + uint16_t _3889 = (uint16_t)(228); + _curvea0[736] = _3889; + uint16_t _3890 = (uint16_t)(228); + _curvea0[737] = _3890; + uint16_t _3891 = (uint16_t)(228); + _curvea0[738] = _3891; + uint16_t _3892 = (uint16_t)(228); + _curvea0[739] = _3892; + uint16_t _3893 = (uint16_t)(228); + _curvea0[740] = _3893; + uint16_t _3894 = (uint16_t)(228); + _curvea0[741] = _3894; + uint16_t _3895 = (uint16_t)(228); + _curvea0[742] = _3895; + uint16_t _3896 = (uint16_t)(229); + _curvea0[743] = _3896; + uint16_t _3897 = (uint16_t)(229); + _curvea0[744] = _3897; + uint16_t _3898 = (uint16_t)(229); + _curvea0[745] = _3898; + uint16_t _3899 = (uint16_t)(229); + _curvea0[746] = _3899; + uint16_t _3900 = (uint16_t)(229); + _curvea0[747] = _3900; + uint16_t _3901 = (uint16_t)(229); + _curvea0[748] = _3901; + uint16_t _3902 = (uint16_t)(229); + _curvea0[749] = _3902; + uint16_t _3903 = (uint16_t)(229); + _curvea0[750] = _3903; + uint16_t _3904 = (uint16_t)(230); + _curvea0[751] = _3904; + uint16_t _3905 = (uint16_t)(230); + _curvea0[752] = _3905; + uint16_t _3906 = (uint16_t)(230); + _curvea0[753] = _3906; + uint16_t _3907 = (uint16_t)(230); + _curvea0[754] = _3907; + uint16_t _3908 = (uint16_t)(230); + _curvea0[755] = _3908; + uint16_t _3909 = (uint16_t)(230); + _curvea0[756] = _3909; + uint16_t _3910 = (uint16_t)(230); + _curvea0[757] = _3910; + uint16_t _3911 = (uint16_t)(230); + _curvea0[758] = _3911; + uint16_t _3912 = (uint16_t)(231); + _curvea0[759] = _3912; + uint16_t _3913 = (uint16_t)(231); + _curvea0[760] = _3913; + uint16_t _3914 = (uint16_t)(231); + _curvea0[761] = _3914; + uint16_t _3915 = (uint16_t)(231); + _curvea0[762] = _3915; + uint16_t _3916 = (uint16_t)(231); + _curvea0[763] = _3916; + uint16_t _3917 = (uint16_t)(231); + _curvea0[764] = _3917; + uint16_t _3918 = (uint16_t)(231); + _curvea0[765] = _3918; + uint16_t _3919 = (uint16_t)(231); + _curvea0[766] = _3919; + uint16_t _3920 = (uint16_t)(231); + _curvea0[767] = _3920; + uint16_t _3921 = (uint16_t)(232); + _curvea0[768] = _3921; + uint16_t _3922 = (uint16_t)(232); + _curvea0[769] = _3922; + uint16_t _3923 = (uint16_t)(232); + _curvea0[770] = _3923; + uint16_t _3924 = (uint16_t)(232); + _curvea0[771] = _3924; + uint16_t _3925 = (uint16_t)(232); + _curvea0[772] = _3925; + uint16_t _3926 = (uint16_t)(232); + _curvea0[773] = _3926; + uint16_t _3927 = (uint16_t)(232); + _curvea0[774] = _3927; + uint16_t _3928 = (uint16_t)(232); + _curvea0[775] = _3928; + uint16_t _3929 = (uint16_t)(233); + _curvea0[776] = _3929; + uint16_t _3930 = (uint16_t)(233); + _curvea0[777] = _3930; + uint16_t _3931 = (uint16_t)(233); + _curvea0[778] = _3931; + uint16_t _3932 = (uint16_t)(233); + _curvea0[779] = _3932; + uint16_t _3933 = (uint16_t)(233); + _curvea0[780] = _3933; + uint16_t _3934 = (uint16_t)(233); + _curvea0[781] = _3934; + uint16_t _3935 = (uint16_t)(233); + _curvea0[782] = _3935; + uint16_t _3936 = (uint16_t)(233); + _curvea0[783] = _3936; + uint16_t _3937 = (uint16_t)(233); + _curvea0[784] = _3937; + uint16_t _3938 = (uint16_t)(234); + _curvea0[785] = _3938; + uint16_t _3939 = (uint16_t)(234); + _curvea0[786] = _3939; + uint16_t _3940 = (uint16_t)(234); + _curvea0[787] = _3940; + uint16_t _3941 = (uint16_t)(234); + _curvea0[788] = _3941; + uint16_t _3942 = (uint16_t)(234); + _curvea0[789] = _3942; + uint16_t _3943 = (uint16_t)(234); + _curvea0[790] = _3943; + uint16_t _3944 = (uint16_t)(234); + _curvea0[791] = _3944; + uint16_t _3945 = (uint16_t)(234); + _curvea0[792] = _3945; + uint16_t _3946 = (uint16_t)(234); + _curvea0[793] = _3946; + uint16_t _3947 = (uint16_t)(235); + _curvea0[794] = _3947; + uint16_t _3948 = (uint16_t)(235); + _curvea0[795] = _3948; + uint16_t _3949 = (uint16_t)(235); + _curvea0[796] = _3949; + uint16_t _3950 = (uint16_t)(235); + _curvea0[797] = _3950; + uint16_t _3951 = (uint16_t)(235); + _curvea0[798] = _3951; + uint16_t _3952 = (uint16_t)(235); + _curvea0[799] = _3952; + uint16_t _3953 = (uint16_t)(235); + _curvea0[800] = _3953; + uint16_t _3954 = (uint16_t)(235); + _curvea0[801] = _3954; + uint16_t _3955 = (uint16_t)(235); + _curvea0[802] = _3955; + uint16_t _3956 = (uint16_t)(236); + _curvea0[803] = _3956; + uint16_t _3957 = (uint16_t)(236); + _curvea0[804] = _3957; + uint16_t _3958 = (uint16_t)(236); + _curvea0[805] = _3958; + uint16_t _3959 = (uint16_t)(236); + _curvea0[806] = _3959; + uint16_t _3960 = (uint16_t)(236); + _curvea0[807] = _3960; + uint16_t _3961 = (uint16_t)(236); + _curvea0[808] = _3961; + uint16_t _3962 = (uint16_t)(236); + _curvea0[809] = _3962; + uint16_t _3963 = (uint16_t)(236); + _curvea0[810] = _3963; + uint16_t _3964 = (uint16_t)(236); + _curvea0[811] = _3964; + uint16_t _3965 = (uint16_t)(237); + _curvea0[812] = _3965; + uint16_t _3966 = (uint16_t)(237); + _curvea0[813] = _3966; + uint16_t _3967 = (uint16_t)(237); + _curvea0[814] = _3967; + uint16_t _3968 = (uint16_t)(237); + _curvea0[815] = _3968; + uint16_t _3969 = (uint16_t)(237); + _curvea0[816] = _3969; + uint16_t _3970 = (uint16_t)(237); + _curvea0[817] = _3970; + uint16_t _3971 = (uint16_t)(237); + _curvea0[818] = _3971; + uint16_t _3972 = (uint16_t)(237); + _curvea0[819] = _3972; + uint16_t _3973 = (uint16_t)(237); + _curvea0[820] = _3973; + uint16_t _3974 = (uint16_t)(237); + _curvea0[821] = _3974; + uint16_t _3975 = (uint16_t)(238); + _curvea0[822] = _3975; + uint16_t _3976 = (uint16_t)(238); + _curvea0[823] = _3976; + uint16_t _3977 = (uint16_t)(238); + _curvea0[824] = _3977; + uint16_t _3978 = (uint16_t)(238); + _curvea0[825] = _3978; + uint16_t _3979 = (uint16_t)(238); + _curvea0[826] = _3979; + uint16_t _3980 = (uint16_t)(238); + _curvea0[827] = _3980; + uint16_t _3981 = (uint16_t)(238); + _curvea0[828] = _3981; + uint16_t _3982 = (uint16_t)(238); + _curvea0[829] = _3982; + uint16_t _3983 = (uint16_t)(238); + _curvea0[830] = _3983; + uint16_t _3984 = (uint16_t)(239); + _curvea0[831] = _3984; + uint16_t _3985 = (uint16_t)(239); + _curvea0[832] = _3985; + uint16_t _3986 = (uint16_t)(239); + _curvea0[833] = _3986; + uint16_t _3987 = (uint16_t)(239); + _curvea0[834] = _3987; + uint16_t _3988 = (uint16_t)(239); + _curvea0[835] = _3988; + uint16_t _3989 = (uint16_t)(239); + _curvea0[836] = _3989; + uint16_t _3990 = (uint16_t)(239); + _curvea0[837] = _3990; + uint16_t _3991 = (uint16_t)(239); + _curvea0[838] = _3991; + uint16_t _3992 = (uint16_t)(239); + _curvea0[839] = _3992; + uint16_t _3993 = (uint16_t)(239); + _curvea0[840] = _3993; + uint16_t _3994 = (uint16_t)(240); + _curvea0[841] = _3994; + uint16_t _3995 = (uint16_t)(240); + _curvea0[842] = _3995; + uint16_t _3996 = (uint16_t)(240); + _curvea0[843] = _3996; + uint16_t _3997 = (uint16_t)(240); + _curvea0[844] = _3997; + uint16_t _3998 = (uint16_t)(240); + _curvea0[845] = _3998; + uint16_t _3999 = (uint16_t)(240); + _curvea0[846] = _3999; + uint16_t _4000 = (uint16_t)(240); + _curvea0[847] = _4000; + uint16_t _4001 = (uint16_t)(240); + _curvea0[848] = _4001; + uint16_t _4002 = (uint16_t)(240); + _curvea0[849] = _4002; + uint16_t _4003 = (uint16_t)(240); + _curvea0[850] = _4003; + uint16_t _4004 = (uint16_t)(241); + _curvea0[851] = _4004; + uint16_t _4005 = (uint16_t)(241); + _curvea0[852] = _4005; + uint16_t _4006 = (uint16_t)(241); + _curvea0[853] = _4006; + uint16_t _4007 = (uint16_t)(241); + _curvea0[854] = _4007; + uint16_t _4008 = (uint16_t)(241); + _curvea0[855] = _4008; + uint16_t _4009 = (uint16_t)(241); + _curvea0[856] = _4009; + uint16_t _4010 = (uint16_t)(241); + _curvea0[857] = _4010; + uint16_t _4011 = (uint16_t)(241); + _curvea0[858] = _4011; + uint16_t _4012 = (uint16_t)(241); + _curvea0[859] = _4012; + uint16_t _4013 = (uint16_t)(241); + _curvea0[860] = _4013; + uint16_t _4014 = (uint16_t)(242); + _curvea0[861] = _4014; + uint16_t _4015 = (uint16_t)(242); + _curvea0[862] = _4015; + uint16_t _4016 = (uint16_t)(242); + _curvea0[863] = _4016; + uint16_t _4017 = (uint16_t)(242); + _curvea0[864] = _4017; + uint16_t _4018 = (uint16_t)(242); + _curvea0[865] = _4018; + uint16_t _4019 = (uint16_t)(242); + _curvea0[866] = _4019; + uint16_t _4020 = (uint16_t)(242); + _curvea0[867] = _4020; + uint16_t _4021 = (uint16_t)(242); + _curvea0[868] = _4021; + uint16_t _4022 = (uint16_t)(242); + _curvea0[869] = _4022; + uint16_t _4023 = (uint16_t)(242); + _curvea0[870] = _4023; + uint16_t _4024 = (uint16_t)(243); + _curvea0[871] = _4024; + uint16_t _4025 = (uint16_t)(243); + _curvea0[872] = _4025; + uint16_t _4026 = (uint16_t)(243); + _curvea0[873] = _4026; + uint16_t _4027 = (uint16_t)(243); + _curvea0[874] = _4027; + uint16_t _4028 = (uint16_t)(243); + _curvea0[875] = _4028; + uint16_t _4029 = (uint16_t)(243); + _curvea0[876] = _4029; + uint16_t _4030 = (uint16_t)(243); + _curvea0[877] = _4030; + uint16_t _4031 = (uint16_t)(243); + _curvea0[878] = _4031; + uint16_t _4032 = (uint16_t)(243); + _curvea0[879] = _4032; + uint16_t _4033 = (uint16_t)(243); + _curvea0[880] = _4033; + uint16_t _4034 = (uint16_t)(244); + _curvea0[881] = _4034; + uint16_t _4035 = (uint16_t)(244); + _curvea0[882] = _4035; + uint16_t _4036 = (uint16_t)(244); + _curvea0[883] = _4036; + uint16_t _4037 = (uint16_t)(244); + _curvea0[884] = _4037; + uint16_t _4038 = (uint16_t)(244); + _curvea0[885] = _4038; + uint16_t _4039 = (uint16_t)(244); + _curvea0[886] = _4039; + uint16_t _4040 = (uint16_t)(244); + _curvea0[887] = _4040; + uint16_t _4041 = (uint16_t)(244); + _curvea0[888] = _4041; + uint16_t _4042 = (uint16_t)(244); + _curvea0[889] = _4042; + uint16_t _4043 = (uint16_t)(244); + _curvea0[890] = _4043; + uint16_t _4044 = (uint16_t)(244); + _curvea0[891] = _4044; + uint16_t _4045 = (uint16_t)(245); + _curvea0[892] = _4045; + uint16_t _4046 = (uint16_t)(245); + _curvea0[893] = _4046; + uint16_t _4047 = (uint16_t)(245); + _curvea0[894] = _4047; + uint16_t _4048 = (uint16_t)(245); + _curvea0[895] = _4048; + uint16_t _4049 = (uint16_t)(245); + _curvea0[896] = _4049; + uint16_t _4050 = (uint16_t)(245); + _curvea0[897] = _4050; + uint16_t _4051 = (uint16_t)(245); + _curvea0[898] = _4051; + uint16_t _4052 = (uint16_t)(245); + _curvea0[899] = _4052; + uint16_t _4053 = (uint16_t)(245); + _curvea0[900] = _4053; + uint16_t _4054 = (uint16_t)(245); + _curvea0[901] = _4054; + uint16_t _4055 = (uint16_t)(245); + _curvea0[902] = _4055; + uint16_t _4056 = (uint16_t)(246); + _curvea0[903] = _4056; + uint16_t _4057 = (uint16_t)(246); + _curvea0[904] = _4057; + uint16_t _4058 = (uint16_t)(246); + _curvea0[905] = _4058; + uint16_t _4059 = (uint16_t)(246); + _curvea0[906] = _4059; + uint16_t _4060 = (uint16_t)(246); + _curvea0[907] = _4060; + uint16_t _4061 = (uint16_t)(246); + _curvea0[908] = _4061; + uint16_t _4062 = (uint16_t)(246); + _curvea0[909] = _4062; + uint16_t _4063 = (uint16_t)(246); + _curvea0[910] = _4063; + uint16_t _4064 = (uint16_t)(246); + _curvea0[911] = _4064; + uint16_t _4065 = (uint16_t)(246); + _curvea0[912] = _4065; + uint16_t _4066 = (uint16_t)(246); + _curvea0[913] = _4066; + uint16_t _4067 = (uint16_t)(247); + _curvea0[914] = _4067; + uint16_t _4068 = (uint16_t)(247); + _curvea0[915] = _4068; + uint16_t _4069 = (uint16_t)(247); + _curvea0[916] = _4069; + uint16_t _4070 = (uint16_t)(247); + _curvea0[917] = _4070; + uint16_t _4071 = (uint16_t)(247); + _curvea0[918] = _4071; + uint16_t _4072 = (uint16_t)(247); + _curvea0[919] = _4072; + uint16_t _4073 = (uint16_t)(247); + _curvea0[920] = _4073; + uint16_t _4074 = (uint16_t)(247); + _curvea0[921] = _4074; + uint16_t _4075 = (uint16_t)(247); + _curvea0[922] = _4075; + uint16_t _4076 = (uint16_t)(247); + _curvea0[923] = _4076; + uint16_t _4077 = (uint16_t)(247); + _curvea0[924] = _4077; + uint16_t _4078 = (uint16_t)(248); + _curvea0[925] = _4078; + uint16_t _4079 = (uint16_t)(248); + _curvea0[926] = _4079; + uint16_t _4080 = (uint16_t)(248); + _curvea0[927] = _4080; + uint16_t _4081 = (uint16_t)(248); + _curvea0[928] = _4081; + uint16_t _4082 = (uint16_t)(248); + _curvea0[929] = _4082; + uint16_t _4083 = (uint16_t)(248); + _curvea0[930] = _4083; + uint16_t _4084 = (uint16_t)(248); + _curvea0[931] = _4084; + uint16_t _4085 = (uint16_t)(248); + _curvea0[932] = _4085; + uint16_t _4086 = (uint16_t)(248); + _curvea0[933] = _4086; + uint16_t _4087 = (uint16_t)(248); + _curvea0[934] = _4087; + uint16_t _4088 = (uint16_t)(248); + _curvea0[935] = _4088; + uint16_t _4089 = (uint16_t)(249); + _curvea0[936] = _4089; + uint16_t _4090 = (uint16_t)(249); + _curvea0[937] = _4090; + uint16_t _4091 = (uint16_t)(249); + _curvea0[938] = _4091; + uint16_t _4092 = (uint16_t)(249); + _curvea0[939] = _4092; + uint16_t _4093 = (uint16_t)(249); + _curvea0[940] = _4093; + uint16_t _4094 = (uint16_t)(249); + _curvea0[941] = _4094; + uint16_t _4095 = (uint16_t)(249); + _curvea0[942] = _4095; + uint16_t _4096 = (uint16_t)(249); + _curvea0[943] = _4096; + uint16_t _4097 = (uint16_t)(249); + _curvea0[944] = _4097; + uint16_t _4098 = (uint16_t)(249); + _curvea0[945] = _4098; + uint16_t _4099 = (uint16_t)(249); + _curvea0[946] = _4099; + uint16_t _4100 = (uint16_t)(249); + _curvea0[947] = _4100; + uint16_t _4101 = (uint16_t)(250); + _curvea0[948] = _4101; + uint16_t _4102 = (uint16_t)(250); + _curvea0[949] = _4102; + uint16_t _4103 = (uint16_t)(250); + _curvea0[950] = _4103; + uint16_t _4104 = (uint16_t)(250); + _curvea0[951] = _4104; + uint16_t _4105 = (uint16_t)(250); + _curvea0[952] = _4105; + uint16_t _4106 = (uint16_t)(250); + _curvea0[953] = _4106; + uint16_t _4107 = (uint16_t)(250); + _curvea0[954] = _4107; + uint16_t _4108 = (uint16_t)(250); + _curvea0[955] = _4108; + uint16_t _4109 = (uint16_t)(250); + _curvea0[956] = _4109; + uint16_t _4110 = (uint16_t)(250); + _curvea0[957] = _4110; + uint16_t _4111 = (uint16_t)(250); + _curvea0[958] = _4111; + uint16_t _4112 = (uint16_t)(250); + _curvea0[959] = _4112; + uint16_t _4113 = (uint16_t)(251); + _curvea0[960] = _4113; + uint16_t _4114 = (uint16_t)(251); + _curvea0[961] = _4114; + uint16_t _4115 = (uint16_t)(251); + _curvea0[962] = _4115; + uint16_t _4116 = (uint16_t)(251); + _curvea0[963] = _4116; + uint16_t _4117 = (uint16_t)(251); + _curvea0[964] = _4117; + uint16_t _4118 = (uint16_t)(251); + _curvea0[965] = _4118; + uint16_t _4119 = (uint16_t)(251); + _curvea0[966] = _4119; + uint16_t _4120 = (uint16_t)(251); + _curvea0[967] = _4120; + uint16_t _4121 = (uint16_t)(251); + _curvea0[968] = _4121; + uint16_t _4122 = (uint16_t)(251); + _curvea0[969] = _4122; + uint16_t _4123 = (uint16_t)(251); + _curvea0[970] = _4123; + uint16_t _4124 = (uint16_t)(251); + _curvea0[971] = _4124; + uint16_t _4125 = (uint16_t)(252); + _curvea0[972] = _4125; + uint16_t _4126 = (uint16_t)(252); + _curvea0[973] = _4126; + uint16_t _4127 = (uint16_t)(252); + _curvea0[974] = _4127; + uint16_t _4128 = (uint16_t)(252); + _curvea0[975] = _4128; + uint16_t _4129 = (uint16_t)(252); + _curvea0[976] = _4129; + uint16_t _4130 = (uint16_t)(252); + _curvea0[977] = _4130; + uint16_t _4131 = (uint16_t)(252); + _curvea0[978] = _4131; + uint16_t _4132 = (uint16_t)(252); + _curvea0[979] = _4132; + uint16_t _4133 = (uint16_t)(252); + _curvea0[980] = _4133; + uint16_t _4134 = (uint16_t)(252); + _curvea0[981] = _4134; + uint16_t _4135 = (uint16_t)(252); + _curvea0[982] = _4135; + uint16_t _4136 = (uint16_t)(252); + _curvea0[983] = _4136; + uint16_t _4137 = (uint16_t)(252); + _curvea0[984] = _4137; + uint16_t _4138 = (uint16_t)(253); + _curvea0[985] = _4138; + uint16_t _4139 = (uint16_t)(253); + _curvea0[986] = _4139; + uint16_t _4140 = (uint16_t)(253); + _curvea0[987] = _4140; + uint16_t _4141 = (uint16_t)(253); + _curvea0[988] = _4141; + uint16_t _4142 = (uint16_t)(253); + _curvea0[989] = _4142; + uint16_t _4143 = (uint16_t)(253); + _curvea0[990] = _4143; + uint16_t _4144 = (uint16_t)(253); + _curvea0[991] = _4144; + uint16_t _4145 = (uint16_t)(253); + _curvea0[992] = _4145; + uint16_t _4146 = (uint16_t)(253); + _curvea0[993] = _4146; + uint16_t _4147 = (uint16_t)(253); + _curvea0[994] = _4147; + uint16_t _4148 = (uint16_t)(253); + _curvea0[995] = _4148; + uint16_t _4149 = (uint16_t)(253); + _curvea0[996] = _4149; + uint16_t _4150 = (uint16_t)(253); + _curvea0[997] = _4150; + uint16_t _4151 = (uint16_t)(254); + _curvea0[998] = _4151; + uint16_t _4152 = (uint16_t)(254); + _curvea0[999] = _4152; + uint16_t _4153 = (uint16_t)(254); + _curvea0[1000] = _4153; + uint16_t _4154 = (uint16_t)(254); + _curvea0[1001] = _4154; + uint16_t _4155 = (uint16_t)(254); + _curvea0[1002] = _4155; + uint16_t _4156 = (uint16_t)(254); + _curvea0[1003] = _4156; + uint16_t _4157 = (uint16_t)(254); + _curvea0[1004] = _4157; + uint16_t _4158 = (uint16_t)(254); + _curvea0[1005] = _4158; + uint16_t _4159 = (uint16_t)(254); + _curvea0[1006] = _4159; + uint16_t _4160 = (uint16_t)(254); + _curvea0[1007] = _4160; + uint16_t _4161 = (uint16_t)(254); + _curvea0[1008] = _4161; + uint16_t _4162 = (uint16_t)(254); + _curvea0[1009] = _4162; + uint16_t _4163 = (uint16_t)(254); + _curvea0[1010] = _4163; + uint16_t _4164 = (uint16_t)(255); + _curvea0[1011] = _4164; + uint16_t _4165 = (uint16_t)(255); + _curvea0[1012] = _4165; + uint16_t _4166 = (uint16_t)(255); + _curvea0[1013] = _4166; + uint16_t _4167 = (uint16_t)(255); + _curvea0[1014] = _4167; + uint16_t _4168 = (uint16_t)(255); + _curvea0[1015] = _4168; + uint16_t _4169 = (uint16_t)(255); + _curvea0[1016] = _4169; + uint16_t _4170 = (uint16_t)(255); + _curvea0[1017] = _4170; + uint16_t _4171 = (uint16_t)(255); + _curvea0[1018] = _4171; + uint16_t _4172 = (uint16_t)(255); + _curvea0[1019] = _4172; + uint16_t _4173 = (uint16_t)(255); + _curvea0[1020] = _4173; + uint16_t _4174 = (uint16_t)(255); + _curvea0[1021] = _4174; + uint16_t _4175 = (uint16_t)(255); + _curvea0[1022] = _4175; + uint16_t _4176 = (uint16_t)(255); + _curvea0[1023] = _4176; + + int16_t _4177 = (int16_t)(1023); + int16_t _4178 = min(_corrected_stencil_2, _4177); + int16_t _4179 = (int16_t)(0); + int16_t _4180 = max(_4178, _4179); + uint16_t _4181 = (uint16_t)(_4180); + int32_t _4182 = (int32_t)(_4181); + uint16_t _4183 = ((const uint16_t *)_curvea0)[_4182]; + return _4183; +} + +//store is: curved.stencil(curved_s0_x_x_2, curved_s0_y_2, 2) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x_2, curved_s0_y_2, 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_2(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_3 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _4198 = (uint16_t)(0); + _curvea0[0] = _4198; + uint16_t _4199 = (uint16_t)(4); + _curvea0[1] = _4199; + uint16_t _4200 = (uint16_t)(7); + _curvea0[2] = _4200; + uint16_t _4201 = (uint16_t)(8); + _curvea0[3] = _4201; + uint16_t _4202 = (uint16_t)(10); + _curvea0[4] = _4202; + uint16_t _4203 = (uint16_t)(11); + _curvea0[5] = _4203; + uint16_t _4204 = (uint16_t)(12); + _curvea0[6] = _4204; + uint16_t _4205 = (uint16_t)(13); + _curvea0[7] = _4205; + uint16_t _4206 = (uint16_t)(14); + _curvea0[8] = _4206; + uint16_t _4207 = (uint16_t)(15); + _curvea0[9] = _4207; + uint16_t _4208 = (uint16_t)(16); + _curvea0[10] = _4208; + uint16_t _4209 = (uint16_t)(17); + _curvea0[11] = _4209; + uint16_t _4210 = (uint16_t)(18); + _curvea0[12] = _4210; + uint16_t _4211 = (uint16_t)(19); + _curvea0[13] = _4211; + uint16_t _4212 = (uint16_t)(20); + _curvea0[14] = _4212; + uint16_t _4213 = (uint16_t)(21); + _curvea0[15] = _4213; + uint16_t _4214 = (uint16_t)(22); + _curvea0[16] = _4214; + uint16_t _4215 = (uint16_t)(22); + _curvea0[17] = _4215; + uint16_t _4216 = (uint16_t)(23); + _curvea0[18] = _4216; + uint16_t _4217 = (uint16_t)(24); + _curvea0[19] = _4217; + uint16_t _4218 = (uint16_t)(25); + _curvea0[20] = _4218; + uint16_t _4219 = (uint16_t)(25); + _curvea0[21] = _4219; + uint16_t _4220 = (uint16_t)(26); + _curvea0[22] = _4220; + uint16_t _4221 = (uint16_t)(27); + _curvea0[23] = _4221; + uint16_t _4222 = (uint16_t)(27); + _curvea0[24] = _4222; + uint16_t _4223 = (uint16_t)(28); + _curvea0[25] = _4223; + uint16_t _4224 = (uint16_t)(29); + _curvea0[26] = _4224; + uint16_t _4225 = (uint16_t)(29); + _curvea0[27] = _4225; + uint16_t _4226 = (uint16_t)(30); + _curvea0[28] = _4226; + uint16_t _4227 = (uint16_t)(31); + _curvea0[29] = _4227; + uint16_t _4228 = (uint16_t)(31); + _curvea0[30] = _4228; + uint16_t _4229 = (uint16_t)(32); + _curvea0[31] = _4229; + uint16_t _4230 = (uint16_t)(33); + _curvea0[32] = _4230; + uint16_t _4231 = (uint16_t)(33); + _curvea0[33] = _4231; + uint16_t _4232 = (uint16_t)(34); + _curvea0[34] = _4232; + uint16_t _4233 = (uint16_t)(34); + _curvea0[35] = _4233; + uint16_t _4234 = (uint16_t)(35); + _curvea0[36] = _4234; + uint16_t _4235 = (uint16_t)(36); + _curvea0[37] = _4235; + uint16_t _4236 = (uint16_t)(36); + _curvea0[38] = _4236; + uint16_t _4237 = (uint16_t)(37); + _curvea0[39] = _4237; + uint16_t _4238 = (uint16_t)(37); + _curvea0[40] = _4238; + uint16_t _4239 = (uint16_t)(38); + _curvea0[41] = _4239; + uint16_t _4240 = (uint16_t)(39); + _curvea0[42] = _4240; + uint16_t _4241 = (uint16_t)(39); + _curvea0[43] = _4241; + uint16_t _4242 = (uint16_t)(40); + _curvea0[44] = _4242; + uint16_t _4243 = (uint16_t)(40); + _curvea0[45] = _4243; + uint16_t _4244 = (uint16_t)(41); + _curvea0[46] = _4244; + uint16_t _4245 = (uint16_t)(41); + _curvea0[47] = _4245; + uint16_t _4246 = (uint16_t)(42); + _curvea0[48] = _4246; + uint16_t _4247 = (uint16_t)(42); + _curvea0[49] = _4247; + uint16_t _4248 = (uint16_t)(43); + _curvea0[50] = _4248; + uint16_t _4249 = (uint16_t)(44); + _curvea0[51] = _4249; + uint16_t _4250 = (uint16_t)(44); + _curvea0[52] = _4250; + uint16_t _4251 = (uint16_t)(45); + _curvea0[53] = _4251; + uint16_t _4252 = (uint16_t)(45); + _curvea0[54] = _4252; + uint16_t _4253 = (uint16_t)(46); + _curvea0[55] = _4253; + uint16_t _4254 = (uint16_t)(46); + _curvea0[56] = _4254; + uint16_t _4255 = (uint16_t)(47); + _curvea0[57] = _4255; + uint16_t _4256 = (uint16_t)(47); + _curvea0[58] = _4256; + uint16_t _4257 = (uint16_t)(48); + _curvea0[59] = _4257; + uint16_t _4258 = (uint16_t)(48); + _curvea0[60] = _4258; + uint16_t _4259 = (uint16_t)(49); + _curvea0[61] = _4259; + uint16_t _4260 = (uint16_t)(49); + _curvea0[62] = _4260; + uint16_t _4261 = (uint16_t)(50); + _curvea0[63] = _4261; + uint16_t _4262 = (uint16_t)(50); + _curvea0[64] = _4262; + uint16_t _4263 = (uint16_t)(51); + _curvea0[65] = _4263; + uint16_t _4264 = (uint16_t)(51); + _curvea0[66] = _4264; + uint16_t _4265 = (uint16_t)(52); + _curvea0[67] = _4265; + uint16_t _4266 = (uint16_t)(52); + _curvea0[68] = _4266; + uint16_t _4267 = (uint16_t)(53); + _curvea0[69] = _4267; + uint16_t _4268 = (uint16_t)(53); + _curvea0[70] = _4268; + uint16_t _4269 = (uint16_t)(54); + _curvea0[71] = _4269; + uint16_t _4270 = (uint16_t)(54); + _curvea0[72] = _4270; + uint16_t _4271 = (uint16_t)(55); + _curvea0[73] = _4271; + uint16_t _4272 = (uint16_t)(55); + _curvea0[74] = _4272; + uint16_t _4273 = (uint16_t)(56); + _curvea0[75] = _4273; + uint16_t _4274 = (uint16_t)(56); + _curvea0[76] = _4274; + uint16_t _4275 = (uint16_t)(57); + _curvea0[77] = _4275; + uint16_t _4276 = (uint16_t)(57); + _curvea0[78] = _4276; + uint16_t _4277 = (uint16_t)(58); + _curvea0[79] = _4277; + uint16_t _4278 = (uint16_t)(58); + _curvea0[80] = _4278; + uint16_t _4279 = (uint16_t)(58); + _curvea0[81] = _4279; + uint16_t _4280 = (uint16_t)(59); + _curvea0[82] = _4280; + uint16_t _4281 = (uint16_t)(59); + _curvea0[83] = _4281; + uint16_t _4282 = (uint16_t)(60); + _curvea0[84] = _4282; + uint16_t _4283 = (uint16_t)(60); + _curvea0[85] = _4283; + uint16_t _4284 = (uint16_t)(61); + _curvea0[86] = _4284; + uint16_t _4285 = (uint16_t)(61); + _curvea0[87] = _4285; + uint16_t _4286 = (uint16_t)(62); + _curvea0[88] = _4286; + uint16_t _4287 = (uint16_t)(62); + _curvea0[89] = _4287; + uint16_t _4288 = (uint16_t)(63); + _curvea0[90] = _4288; + uint16_t _4289 = (uint16_t)(63); + _curvea0[91] = _4289; + uint16_t _4290 = (uint16_t)(64); + _curvea0[92] = _4290; + uint16_t _4291 = (uint16_t)(64); + _curvea0[93] = _4291; + uint16_t _4292 = (uint16_t)(64); + _curvea0[94] = _4292; + uint16_t _4293 = (uint16_t)(65); + _curvea0[95] = _4293; + uint16_t _4294 = (uint16_t)(65); + _curvea0[96] = _4294; + uint16_t _4295 = (uint16_t)(66); + _curvea0[97] = _4295; + uint16_t _4296 = (uint16_t)(66); + _curvea0[98] = _4296; + uint16_t _4297 = (uint16_t)(67); + _curvea0[99] = _4297; + uint16_t _4298 = (uint16_t)(67); + _curvea0[100] = _4298; + uint16_t _4299 = (uint16_t)(68); + _curvea0[101] = _4299; + uint16_t _4300 = (uint16_t)(68); + _curvea0[102] = _4300; + uint16_t _4301 = (uint16_t)(68); + _curvea0[103] = _4301; + uint16_t _4302 = (uint16_t)(69); + _curvea0[104] = _4302; + uint16_t _4303 = (uint16_t)(69); + _curvea0[105] = _4303; + uint16_t _4304 = (uint16_t)(70); + _curvea0[106] = _4304; + uint16_t _4305 = (uint16_t)(70); + _curvea0[107] = _4305; + uint16_t _4306 = (uint16_t)(71); + _curvea0[108] = _4306; + uint16_t _4307 = (uint16_t)(71); + _curvea0[109] = _4307; + uint16_t _4308 = (uint16_t)(71); + _curvea0[110] = _4308; + uint16_t _4309 = (uint16_t)(72); + _curvea0[111] = _4309; + uint16_t _4310 = (uint16_t)(72); + _curvea0[112] = _4310; + uint16_t _4311 = (uint16_t)(73); + _curvea0[113] = _4311; + uint16_t _4312 = (uint16_t)(73); + _curvea0[114] = _4312; + uint16_t _4313 = (uint16_t)(74); + _curvea0[115] = _4313; + uint16_t _4314 = (uint16_t)(74); + _curvea0[116] = _4314; + uint16_t _4315 = (uint16_t)(74); + _curvea0[117] = _4315; + uint16_t _4316 = (uint16_t)(75); + _curvea0[118] = _4316; + uint16_t _4317 = (uint16_t)(75); + _curvea0[119] = _4317; + uint16_t _4318 = (uint16_t)(76); + _curvea0[120] = _4318; + uint16_t _4319 = (uint16_t)(76); + _curvea0[121] = _4319; + uint16_t _4320 = (uint16_t)(77); + _curvea0[122] = _4320; + uint16_t _4321 = (uint16_t)(77); + _curvea0[123] = _4321; + uint16_t _4322 = (uint16_t)(77); + _curvea0[124] = _4322; + uint16_t _4323 = (uint16_t)(78); + _curvea0[125] = _4323; + uint16_t _4324 = (uint16_t)(78); + _curvea0[126] = _4324; + uint16_t _4325 = (uint16_t)(79); + _curvea0[127] = _4325; + uint16_t _4326 = (uint16_t)(79); + _curvea0[128] = _4326; + uint16_t _4327 = (uint16_t)(79); + _curvea0[129] = _4327; + uint16_t _4328 = (uint16_t)(80); + _curvea0[130] = _4328; + uint16_t _4329 = (uint16_t)(80); + _curvea0[131] = _4329; + uint16_t _4330 = (uint16_t)(81); + _curvea0[132] = _4330; + uint16_t _4331 = (uint16_t)(81); + _curvea0[133] = _4331; + uint16_t _4332 = (uint16_t)(82); + _curvea0[134] = _4332; + uint16_t _4333 = (uint16_t)(82); + _curvea0[135] = _4333; + uint16_t _4334 = (uint16_t)(82); + _curvea0[136] = _4334; + uint16_t _4335 = (uint16_t)(83); + _curvea0[137] = _4335; + uint16_t _4336 = (uint16_t)(83); + _curvea0[138] = _4336; + uint16_t _4337 = (uint16_t)(84); + _curvea0[139] = _4337; + uint16_t _4338 = (uint16_t)(84); + _curvea0[140] = _4338; + uint16_t _4339 = (uint16_t)(84); + _curvea0[141] = _4339; + uint16_t _4340 = (uint16_t)(85); + _curvea0[142] = _4340; + uint16_t _4341 = (uint16_t)(85); + _curvea0[143] = _4341; + uint16_t _4342 = (uint16_t)(86); + _curvea0[144] = _4342; + uint16_t _4343 = (uint16_t)(86); + _curvea0[145] = _4343; + uint16_t _4344 = (uint16_t)(86); + _curvea0[146] = _4344; + uint16_t _4345 = (uint16_t)(87); + _curvea0[147] = _4345; + uint16_t _4346 = (uint16_t)(87); + _curvea0[148] = _4346; + uint16_t _4347 = (uint16_t)(88); + _curvea0[149] = _4347; + uint16_t _4348 = (uint16_t)(88); + _curvea0[150] = _4348; + uint16_t _4349 = (uint16_t)(88); + _curvea0[151] = _4349; + uint16_t _4350 = (uint16_t)(89); + _curvea0[152] = _4350; + uint16_t _4351 = (uint16_t)(89); + _curvea0[153] = _4351; + uint16_t _4352 = (uint16_t)(90); + _curvea0[154] = _4352; + uint16_t _4353 = (uint16_t)(90); + _curvea0[155] = _4353; + uint16_t _4354 = (uint16_t)(90); + _curvea0[156] = _4354; + uint16_t _4355 = (uint16_t)(91); + _curvea0[157] = _4355; + uint16_t _4356 = (uint16_t)(91); + _curvea0[158] = _4356; + uint16_t _4357 = (uint16_t)(92); + _curvea0[159] = _4357; + uint16_t _4358 = (uint16_t)(92); + _curvea0[160] = _4358; + uint16_t _4359 = (uint16_t)(92); + _curvea0[161] = _4359; + uint16_t _4360 = (uint16_t)(93); + _curvea0[162] = _4360; + uint16_t _4361 = (uint16_t)(93); + _curvea0[163] = _4361; + uint16_t _4362 = (uint16_t)(93); + _curvea0[164] = _4362; + uint16_t _4363 = (uint16_t)(94); + _curvea0[165] = _4363; + uint16_t _4364 = (uint16_t)(94); + _curvea0[166] = _4364; + uint16_t _4365 = (uint16_t)(95); + _curvea0[167] = _4365; + uint16_t _4366 = (uint16_t)(95); + _curvea0[168] = _4366; + uint16_t _4367 = (uint16_t)(95); + _curvea0[169] = _4367; + uint16_t _4368 = (uint16_t)(96); + _curvea0[170] = _4368; + uint16_t _4369 = (uint16_t)(96); + _curvea0[171] = _4369; + uint16_t _4370 = (uint16_t)(97); + _curvea0[172] = _4370; + uint16_t _4371 = (uint16_t)(97); + _curvea0[173] = _4371; + uint16_t _4372 = (uint16_t)(97); + _curvea0[174] = _4372; + uint16_t _4373 = (uint16_t)(98); + _curvea0[175] = _4373; + uint16_t _4374 = (uint16_t)(98); + _curvea0[176] = _4374; + uint16_t _4375 = (uint16_t)(99); + _curvea0[177] = _4375; + uint16_t _4376 = (uint16_t)(99); + _curvea0[178] = _4376; + uint16_t _4377 = (uint16_t)(99); + _curvea0[179] = _4377; + uint16_t _4378 = (uint16_t)(100); + _curvea0[180] = _4378; + uint16_t _4379 = (uint16_t)(100); + _curvea0[181] = _4379; + uint16_t _4380 = (uint16_t)(100); + _curvea0[182] = _4380; + uint16_t _4381 = (uint16_t)(101); + _curvea0[183] = _4381; + uint16_t _4382 = (uint16_t)(101); + _curvea0[184] = _4382; + uint16_t _4383 = (uint16_t)(102); + _curvea0[185] = _4383; + uint16_t _4384 = (uint16_t)(102); + _curvea0[186] = _4384; + uint16_t _4385 = (uint16_t)(102); + _curvea0[187] = _4385; + uint16_t _4386 = (uint16_t)(103); + _curvea0[188] = _4386; + uint16_t _4387 = (uint16_t)(103); + _curvea0[189] = _4387; + uint16_t _4388 = (uint16_t)(103); + _curvea0[190] = _4388; + uint16_t _4389 = (uint16_t)(104); + _curvea0[191] = _4389; + uint16_t _4390 = (uint16_t)(104); + _curvea0[192] = _4390; + uint16_t _4391 = (uint16_t)(105); + _curvea0[193] = _4391; + uint16_t _4392 = (uint16_t)(105); + _curvea0[194] = _4392; + uint16_t _4393 = (uint16_t)(105); + _curvea0[195] = _4393; + uint16_t _4394 = (uint16_t)(106); + _curvea0[196] = _4394; + uint16_t _4395 = (uint16_t)(106); + _curvea0[197] = _4395; + uint16_t _4396 = (uint16_t)(106); + _curvea0[198] = _4396; + uint16_t _4397 = (uint16_t)(107); + _curvea0[199] = _4397; + uint16_t _4398 = (uint16_t)(107); + _curvea0[200] = _4398; + uint16_t _4399 = (uint16_t)(108); + _curvea0[201] = _4399; + uint16_t _4400 = (uint16_t)(108); + _curvea0[202] = _4400; + uint16_t _4401 = (uint16_t)(108); + _curvea0[203] = _4401; + uint16_t _4402 = (uint16_t)(109); + _curvea0[204] = _4402; + uint16_t _4403 = (uint16_t)(109); + _curvea0[205] = _4403; + uint16_t _4404 = (uint16_t)(109); + _curvea0[206] = _4404; + uint16_t _4405 = (uint16_t)(110); + _curvea0[207] = _4405; + uint16_t _4406 = (uint16_t)(110); + _curvea0[208] = _4406; + uint16_t _4407 = (uint16_t)(111); + _curvea0[209] = _4407; + uint16_t _4408 = (uint16_t)(111); + _curvea0[210] = _4408; + uint16_t _4409 = (uint16_t)(111); + _curvea0[211] = _4409; + uint16_t _4410 = (uint16_t)(112); + _curvea0[212] = _4410; + uint16_t _4411 = (uint16_t)(112); + _curvea0[213] = _4411; + uint16_t _4412 = (uint16_t)(112); + _curvea0[214] = _4412; + uint16_t _4413 = (uint16_t)(113); + _curvea0[215] = _4413; + uint16_t _4414 = (uint16_t)(113); + _curvea0[216] = _4414; + uint16_t _4415 = (uint16_t)(113); + _curvea0[217] = _4415; + uint16_t _4416 = (uint16_t)(114); + _curvea0[218] = _4416; + uint16_t _4417 = (uint16_t)(114); + _curvea0[219] = _4417; + uint16_t _4418 = (uint16_t)(115); + _curvea0[220] = _4418; + uint16_t _4419 = (uint16_t)(115); + _curvea0[221] = _4419; + uint16_t _4420 = (uint16_t)(115); + _curvea0[222] = _4420; + uint16_t _4421 = (uint16_t)(116); + _curvea0[223] = _4421; + uint16_t _4422 = (uint16_t)(116); + _curvea0[224] = _4422; + uint16_t _4423 = (uint16_t)(116); + _curvea0[225] = _4423; + uint16_t _4424 = (uint16_t)(117); + _curvea0[226] = _4424; + uint16_t _4425 = (uint16_t)(117); + _curvea0[227] = _4425; + uint16_t _4426 = (uint16_t)(117); + _curvea0[228] = _4426; + uint16_t _4427 = (uint16_t)(118); + _curvea0[229] = _4427; + uint16_t _4428 = (uint16_t)(118); + _curvea0[230] = _4428; + uint16_t _4429 = (uint16_t)(119); + _curvea0[231] = _4429; + uint16_t _4430 = (uint16_t)(119); + _curvea0[232] = _4430; + uint16_t _4431 = (uint16_t)(119); + _curvea0[233] = _4431; + uint16_t _4432 = (uint16_t)(120); + _curvea0[234] = _4432; + uint16_t _4433 = (uint16_t)(120); + _curvea0[235] = _4433; + uint16_t _4434 = (uint16_t)(120); + _curvea0[236] = _4434; + uint16_t _4435 = (uint16_t)(121); + _curvea0[237] = _4435; + uint16_t _4436 = (uint16_t)(121); + _curvea0[238] = _4436; + uint16_t _4437 = (uint16_t)(121); + _curvea0[239] = _4437; + uint16_t _4438 = (uint16_t)(122); + _curvea0[240] = _4438; + uint16_t _4439 = (uint16_t)(122); + _curvea0[241] = _4439; + uint16_t _4440 = (uint16_t)(123); + _curvea0[242] = _4440; + uint16_t _4441 = (uint16_t)(123); + _curvea0[243] = _4441; + uint16_t _4442 = (uint16_t)(123); + _curvea0[244] = _4442; + uint16_t _4443 = (uint16_t)(124); + _curvea0[245] = _4443; + uint16_t _4444 = (uint16_t)(124); + _curvea0[246] = _4444; + uint16_t _4445 = (uint16_t)(124); + _curvea0[247] = _4445; + uint16_t _4446 = (uint16_t)(125); + _curvea0[248] = _4446; + uint16_t _4447 = (uint16_t)(125); + _curvea0[249] = _4447; + uint16_t _4448 = (uint16_t)(125); + _curvea0[250] = _4448; + uint16_t _4449 = (uint16_t)(126); + _curvea0[251] = _4449; + uint16_t _4450 = (uint16_t)(126); + _curvea0[252] = _4450; + uint16_t _4451 = (uint16_t)(126); + _curvea0[253] = _4451; + uint16_t _4452 = (uint16_t)(127); + _curvea0[254] = _4452; + uint16_t _4453 = (uint16_t)(127); + _curvea0[255] = _4453; + uint16_t _4454 = (uint16_t)(128); + _curvea0[256] = _4454; + uint16_t _4455 = (uint16_t)(128); + _curvea0[257] = _4455; + uint16_t _4456 = (uint16_t)(128); + _curvea0[258] = _4456; + uint16_t _4457 = (uint16_t)(129); + _curvea0[259] = _4457; + uint16_t _4458 = (uint16_t)(129); + _curvea0[260] = _4458; + uint16_t _4459 = (uint16_t)(129); + _curvea0[261] = _4459; + uint16_t _4460 = (uint16_t)(130); + _curvea0[262] = _4460; + uint16_t _4461 = (uint16_t)(130); + _curvea0[263] = _4461; + uint16_t _4462 = (uint16_t)(130); + _curvea0[264] = _4462; + uint16_t _4463 = (uint16_t)(131); + _curvea0[265] = _4463; + uint16_t _4464 = (uint16_t)(131); + _curvea0[266] = _4464; + uint16_t _4465 = (uint16_t)(131); + _curvea0[267] = _4465; + uint16_t _4466 = (uint16_t)(132); + _curvea0[268] = _4466; + uint16_t _4467 = (uint16_t)(132); + _curvea0[269] = _4467; + uint16_t _4468 = (uint16_t)(132); + _curvea0[270] = _4468; + uint16_t _4469 = (uint16_t)(133); + _curvea0[271] = _4469; + uint16_t _4470 = (uint16_t)(133); + _curvea0[272] = _4470; + uint16_t _4471 = (uint16_t)(133); + _curvea0[273] = _4471; + uint16_t _4472 = (uint16_t)(134); + _curvea0[274] = _4472; + uint16_t _4473 = (uint16_t)(134); + _curvea0[275] = _4473; + uint16_t _4474 = (uint16_t)(134); + _curvea0[276] = _4474; + uint16_t _4475 = (uint16_t)(135); + _curvea0[277] = _4475; + uint16_t _4476 = (uint16_t)(135); + _curvea0[278] = _4476; + uint16_t _4477 = (uint16_t)(135); + _curvea0[279] = _4477; + uint16_t _4478 = (uint16_t)(136); + _curvea0[280] = _4478; + uint16_t _4479 = (uint16_t)(136); + _curvea0[281] = _4479; + uint16_t _4480 = (uint16_t)(136); + _curvea0[282] = _4480; + uint16_t _4481 = (uint16_t)(137); + _curvea0[283] = _4481; + uint16_t _4482 = (uint16_t)(137); + _curvea0[284] = _4482; + uint16_t _4483 = (uint16_t)(137); + _curvea0[285] = _4483; + uint16_t _4484 = (uint16_t)(138); + _curvea0[286] = _4484; + uint16_t _4485 = (uint16_t)(138); + _curvea0[287] = _4485; + uint16_t _4486 = (uint16_t)(138); + _curvea0[288] = _4486; + uint16_t _4487 = (uint16_t)(139); + _curvea0[289] = _4487; + uint16_t _4488 = (uint16_t)(139); + _curvea0[290] = _4488; + uint16_t _4489 = (uint16_t)(139); + _curvea0[291] = _4489; + uint16_t _4490 = (uint16_t)(140); + _curvea0[292] = _4490; + uint16_t _4491 = (uint16_t)(140); + _curvea0[293] = _4491; + uint16_t _4492 = (uint16_t)(140); + _curvea0[294] = _4492; + uint16_t _4493 = (uint16_t)(141); + _curvea0[295] = _4493; + uint16_t _4494 = (uint16_t)(141); + _curvea0[296] = _4494; + uint16_t _4495 = (uint16_t)(141); + _curvea0[297] = _4495; + uint16_t _4496 = (uint16_t)(141); + _curvea0[298] = _4496; + uint16_t _4497 = (uint16_t)(142); + _curvea0[299] = _4497; + uint16_t _4498 = (uint16_t)(142); + _curvea0[300] = _4498; + uint16_t _4499 = (uint16_t)(142); + _curvea0[301] = _4499; + uint16_t _4500 = (uint16_t)(143); + _curvea0[302] = _4500; + uint16_t _4501 = (uint16_t)(143); + _curvea0[303] = _4501; + uint16_t _4502 = (uint16_t)(143); + _curvea0[304] = _4502; + uint16_t _4503 = (uint16_t)(144); + _curvea0[305] = _4503; + uint16_t _4504 = (uint16_t)(144); + _curvea0[306] = _4504; + uint16_t _4505 = (uint16_t)(144); + _curvea0[307] = _4505; + uint16_t _4506 = (uint16_t)(145); + _curvea0[308] = _4506; + uint16_t _4507 = (uint16_t)(145); + _curvea0[309] = _4507; + uint16_t _4508 = (uint16_t)(145); + _curvea0[310] = _4508; + uint16_t _4509 = (uint16_t)(145); + _curvea0[311] = _4509; + uint16_t _4510 = (uint16_t)(146); + _curvea0[312] = _4510; + uint16_t _4511 = (uint16_t)(146); + _curvea0[313] = _4511; + uint16_t _4512 = (uint16_t)(146); + _curvea0[314] = _4512; + uint16_t _4513 = (uint16_t)(147); + _curvea0[315] = _4513; + uint16_t _4514 = (uint16_t)(147); + _curvea0[316] = _4514; + uint16_t _4515 = (uint16_t)(147); + _curvea0[317] = _4515; + uint16_t _4516 = (uint16_t)(148); + _curvea0[318] = _4516; + uint16_t _4517 = (uint16_t)(148); + _curvea0[319] = _4517; + uint16_t _4518 = (uint16_t)(148); + _curvea0[320] = _4518; + uint16_t _4519 = (uint16_t)(148); + _curvea0[321] = _4519; + uint16_t _4520 = (uint16_t)(149); + _curvea0[322] = _4520; + uint16_t _4521 = (uint16_t)(149); + _curvea0[323] = _4521; + uint16_t _4522 = (uint16_t)(149); + _curvea0[324] = _4522; + uint16_t _4523 = (uint16_t)(150); + _curvea0[325] = _4523; + uint16_t _4524 = (uint16_t)(150); + _curvea0[326] = _4524; + uint16_t _4525 = (uint16_t)(150); + _curvea0[327] = _4525; + uint16_t _4526 = (uint16_t)(150); + _curvea0[328] = _4526; + uint16_t _4527 = (uint16_t)(151); + _curvea0[329] = _4527; + uint16_t _4528 = (uint16_t)(151); + _curvea0[330] = _4528; + uint16_t _4529 = (uint16_t)(151); + _curvea0[331] = _4529; + uint16_t _4530 = (uint16_t)(152); + _curvea0[332] = _4530; + uint16_t _4531 = (uint16_t)(152); + _curvea0[333] = _4531; + uint16_t _4532 = (uint16_t)(152); + _curvea0[334] = _4532; + uint16_t _4533 = (uint16_t)(152); + _curvea0[335] = _4533; + uint16_t _4534 = (uint16_t)(153); + _curvea0[336] = _4534; + uint16_t _4535 = (uint16_t)(153); + _curvea0[337] = _4535; + uint16_t _4536 = (uint16_t)(153); + _curvea0[338] = _4536; + uint16_t _4537 = (uint16_t)(154); + _curvea0[339] = _4537; + uint16_t _4538 = (uint16_t)(154); + _curvea0[340] = _4538; + uint16_t _4539 = (uint16_t)(154); + _curvea0[341] = _4539; + uint16_t _4540 = (uint16_t)(154); + _curvea0[342] = _4540; + uint16_t _4541 = (uint16_t)(155); + _curvea0[343] = _4541; + uint16_t _4542 = (uint16_t)(155); + _curvea0[344] = _4542; + uint16_t _4543 = (uint16_t)(155); + _curvea0[345] = _4543; + uint16_t _4544 = (uint16_t)(156); + _curvea0[346] = _4544; + uint16_t _4545 = (uint16_t)(156); + _curvea0[347] = _4545; + uint16_t _4546 = (uint16_t)(156); + _curvea0[348] = _4546; + uint16_t _4547 = (uint16_t)(156); + _curvea0[349] = _4547; + uint16_t _4548 = (uint16_t)(157); + _curvea0[350] = _4548; + uint16_t _4549 = (uint16_t)(157); + _curvea0[351] = _4549; + uint16_t _4550 = (uint16_t)(157); + _curvea0[352] = _4550; + uint16_t _4551 = (uint16_t)(157); + _curvea0[353] = _4551; + uint16_t _4552 = (uint16_t)(158); + _curvea0[354] = _4552; + uint16_t _4553 = (uint16_t)(158); + _curvea0[355] = _4553; + uint16_t _4554 = (uint16_t)(158); + _curvea0[356] = _4554; + uint16_t _4555 = (uint16_t)(159); + _curvea0[357] = _4555; + uint16_t _4556 = (uint16_t)(159); + _curvea0[358] = _4556; + uint16_t _4557 = (uint16_t)(159); + _curvea0[359] = _4557; + uint16_t _4558 = (uint16_t)(159); + _curvea0[360] = _4558; + uint16_t _4559 = (uint16_t)(160); + _curvea0[361] = _4559; + uint16_t _4560 = (uint16_t)(160); + _curvea0[362] = _4560; + uint16_t _4561 = (uint16_t)(160); + _curvea0[363] = _4561; + uint16_t _4562 = (uint16_t)(160); + _curvea0[364] = _4562; + uint16_t _4563 = (uint16_t)(161); + _curvea0[365] = _4563; + uint16_t _4564 = (uint16_t)(161); + _curvea0[366] = _4564; + uint16_t _4565 = (uint16_t)(161); + _curvea0[367] = _4565; + uint16_t _4566 = (uint16_t)(161); + _curvea0[368] = _4566; + uint16_t _4567 = (uint16_t)(162); + _curvea0[369] = _4567; + uint16_t _4568 = (uint16_t)(162); + _curvea0[370] = _4568; + uint16_t _4569 = (uint16_t)(162); + _curvea0[371] = _4569; + uint16_t _4570 = (uint16_t)(162); + _curvea0[372] = _4570; + uint16_t _4571 = (uint16_t)(163); + _curvea0[373] = _4571; + uint16_t _4572 = (uint16_t)(163); + _curvea0[374] = _4572; + uint16_t _4573 = (uint16_t)(163); + _curvea0[375] = _4573; + uint16_t _4574 = (uint16_t)(163); + _curvea0[376] = _4574; + uint16_t _4575 = (uint16_t)(164); + _curvea0[377] = _4575; + uint16_t _4576 = (uint16_t)(164); + _curvea0[378] = _4576; + uint16_t _4577 = (uint16_t)(164); + _curvea0[379] = _4577; + uint16_t _4578 = (uint16_t)(164); + _curvea0[380] = _4578; + uint16_t _4579 = (uint16_t)(165); + _curvea0[381] = _4579; + uint16_t _4580 = (uint16_t)(165); + _curvea0[382] = _4580; + uint16_t _4581 = (uint16_t)(165); + _curvea0[383] = _4581; + uint16_t _4582 = (uint16_t)(166); + _curvea0[384] = _4582; + uint16_t _4583 = (uint16_t)(166); + _curvea0[385] = _4583; + uint16_t _4584 = (uint16_t)(166); + _curvea0[386] = _4584; + uint16_t _4585 = (uint16_t)(166); + _curvea0[387] = _4585; + uint16_t _4586 = (uint16_t)(167); + _curvea0[388] = _4586; + uint16_t _4587 = (uint16_t)(167); + _curvea0[389] = _4587; + uint16_t _4588 = (uint16_t)(167); + _curvea0[390] = _4588; + uint16_t _4589 = (uint16_t)(167); + _curvea0[391] = _4589; + uint16_t _4590 = (uint16_t)(167); + _curvea0[392] = _4590; + uint16_t _4591 = (uint16_t)(168); + _curvea0[393] = _4591; + uint16_t _4592 = (uint16_t)(168); + _curvea0[394] = _4592; + uint16_t _4593 = (uint16_t)(168); + _curvea0[395] = _4593; + uint16_t _4594 = (uint16_t)(168); + _curvea0[396] = _4594; + uint16_t _4595 = (uint16_t)(169); + _curvea0[397] = _4595; + uint16_t _4596 = (uint16_t)(169); + _curvea0[398] = _4596; + uint16_t _4597 = (uint16_t)(169); + _curvea0[399] = _4597; + uint16_t _4598 = (uint16_t)(169); + _curvea0[400] = _4598; + uint16_t _4599 = (uint16_t)(170); + _curvea0[401] = _4599; + uint16_t _4600 = (uint16_t)(170); + _curvea0[402] = _4600; + uint16_t _4601 = (uint16_t)(170); + _curvea0[403] = _4601; + uint16_t _4602 = (uint16_t)(170); + _curvea0[404] = _4602; + uint16_t _4603 = (uint16_t)(171); + _curvea0[405] = _4603; + uint16_t _4604 = (uint16_t)(171); + _curvea0[406] = _4604; + uint16_t _4605 = (uint16_t)(171); + _curvea0[407] = _4605; + uint16_t _4606 = (uint16_t)(171); + _curvea0[408] = _4606; + uint16_t _4607 = (uint16_t)(172); + _curvea0[409] = _4607; + uint16_t _4608 = (uint16_t)(172); + _curvea0[410] = _4608; + uint16_t _4609 = (uint16_t)(172); + _curvea0[411] = _4609; + uint16_t _4610 = (uint16_t)(172); + _curvea0[412] = _4610; + uint16_t _4611 = (uint16_t)(173); + _curvea0[413] = _4611; + uint16_t _4612 = (uint16_t)(173); + _curvea0[414] = _4612; + uint16_t _4613 = (uint16_t)(173); + _curvea0[415] = _4613; + uint16_t _4614 = (uint16_t)(173); + _curvea0[416] = _4614; + uint16_t _4615 = (uint16_t)(173); + _curvea0[417] = _4615; + uint16_t _4616 = (uint16_t)(174); + _curvea0[418] = _4616; + uint16_t _4617 = (uint16_t)(174); + _curvea0[419] = _4617; + uint16_t _4618 = (uint16_t)(174); + _curvea0[420] = _4618; + uint16_t _4619 = (uint16_t)(174); + _curvea0[421] = _4619; + uint16_t _4620 = (uint16_t)(175); + _curvea0[422] = _4620; + uint16_t _4621 = (uint16_t)(175); + _curvea0[423] = _4621; + uint16_t _4622 = (uint16_t)(175); + _curvea0[424] = _4622; + uint16_t _4623 = (uint16_t)(175); + _curvea0[425] = _4623; + uint16_t _4624 = (uint16_t)(176); + _curvea0[426] = _4624; + uint16_t _4625 = (uint16_t)(176); + _curvea0[427] = _4625; + uint16_t _4626 = (uint16_t)(176); + _curvea0[428] = _4626; + uint16_t _4627 = (uint16_t)(176); + _curvea0[429] = _4627; + uint16_t _4628 = (uint16_t)(176); + _curvea0[430] = _4628; + uint16_t _4629 = (uint16_t)(177); + _curvea0[431] = _4629; + uint16_t _4630 = (uint16_t)(177); + _curvea0[432] = _4630; + uint16_t _4631 = (uint16_t)(177); + _curvea0[433] = _4631; + uint16_t _4632 = (uint16_t)(177); + _curvea0[434] = _4632; + uint16_t _4633 = (uint16_t)(178); + _curvea0[435] = _4633; + uint16_t _4634 = (uint16_t)(178); + _curvea0[436] = _4634; + uint16_t _4635 = (uint16_t)(178); + _curvea0[437] = _4635; + uint16_t _4636 = (uint16_t)(178); + _curvea0[438] = _4636; + uint16_t _4637 = (uint16_t)(178); + _curvea0[439] = _4637; + uint16_t _4638 = (uint16_t)(179); + _curvea0[440] = _4638; + uint16_t _4639 = (uint16_t)(179); + _curvea0[441] = _4639; + uint16_t _4640 = (uint16_t)(179); + _curvea0[442] = _4640; + uint16_t _4641 = (uint16_t)(179); + _curvea0[443] = _4641; + uint16_t _4642 = (uint16_t)(180); + _curvea0[444] = _4642; + uint16_t _4643 = (uint16_t)(180); + _curvea0[445] = _4643; + uint16_t _4644 = (uint16_t)(180); + _curvea0[446] = _4644; + uint16_t _4645 = (uint16_t)(180); + _curvea0[447] = _4645; + uint16_t _4646 = (uint16_t)(180); + _curvea0[448] = _4646; + uint16_t _4647 = (uint16_t)(181); + _curvea0[449] = _4647; + uint16_t _4648 = (uint16_t)(181); + _curvea0[450] = _4648; + uint16_t _4649 = (uint16_t)(181); + _curvea0[451] = _4649; + uint16_t _4650 = (uint16_t)(181); + _curvea0[452] = _4650; + uint16_t _4651 = (uint16_t)(181); + _curvea0[453] = _4651; + uint16_t _4652 = (uint16_t)(182); + _curvea0[454] = _4652; + uint16_t _4653 = (uint16_t)(182); + _curvea0[455] = _4653; + uint16_t _4654 = (uint16_t)(182); + _curvea0[456] = _4654; + uint16_t _4655 = (uint16_t)(182); + _curvea0[457] = _4655; + uint16_t _4656 = (uint16_t)(183); + _curvea0[458] = _4656; + uint16_t _4657 = (uint16_t)(183); + _curvea0[459] = _4657; + uint16_t _4658 = (uint16_t)(183); + _curvea0[460] = _4658; + uint16_t _4659 = (uint16_t)(183); + _curvea0[461] = _4659; + uint16_t _4660 = (uint16_t)(183); + _curvea0[462] = _4660; + uint16_t _4661 = (uint16_t)(184); + _curvea0[463] = _4661; + uint16_t _4662 = (uint16_t)(184); + _curvea0[464] = _4662; + uint16_t _4663 = (uint16_t)(184); + _curvea0[465] = _4663; + uint16_t _4664 = (uint16_t)(184); + _curvea0[466] = _4664; + uint16_t _4665 = (uint16_t)(184); + _curvea0[467] = _4665; + uint16_t _4666 = (uint16_t)(185); + _curvea0[468] = _4666; + uint16_t _4667 = (uint16_t)(185); + _curvea0[469] = _4667; + uint16_t _4668 = (uint16_t)(185); + _curvea0[470] = _4668; + uint16_t _4669 = (uint16_t)(185); + _curvea0[471] = _4669; + uint16_t _4670 = (uint16_t)(185); + _curvea0[472] = _4670; + uint16_t _4671 = (uint16_t)(186); + _curvea0[473] = _4671; + uint16_t _4672 = (uint16_t)(186); + _curvea0[474] = _4672; + uint16_t _4673 = (uint16_t)(186); + _curvea0[475] = _4673; + uint16_t _4674 = (uint16_t)(186); + _curvea0[476] = _4674; + uint16_t _4675 = (uint16_t)(187); + _curvea0[477] = _4675; + uint16_t _4676 = (uint16_t)(187); + _curvea0[478] = _4676; + uint16_t _4677 = (uint16_t)(187); + _curvea0[479] = _4677; + uint16_t _4678 = (uint16_t)(187); + _curvea0[480] = _4678; + uint16_t _4679 = (uint16_t)(187); + _curvea0[481] = _4679; + uint16_t _4680 = (uint16_t)(188); + _curvea0[482] = _4680; + uint16_t _4681 = (uint16_t)(188); + _curvea0[483] = _4681; + uint16_t _4682 = (uint16_t)(188); + _curvea0[484] = _4682; + uint16_t _4683 = (uint16_t)(188); + _curvea0[485] = _4683; + uint16_t _4684 = (uint16_t)(188); + _curvea0[486] = _4684; + uint16_t _4685 = (uint16_t)(189); + _curvea0[487] = _4685; + uint16_t _4686 = (uint16_t)(189); + _curvea0[488] = _4686; + uint16_t _4687 = (uint16_t)(189); + _curvea0[489] = _4687; + uint16_t _4688 = (uint16_t)(189); + _curvea0[490] = _4688; + uint16_t _4689 = (uint16_t)(189); + _curvea0[491] = _4689; + uint16_t _4690 = (uint16_t)(190); + _curvea0[492] = _4690; + uint16_t _4691 = (uint16_t)(190); + _curvea0[493] = _4691; + uint16_t _4692 = (uint16_t)(190); + _curvea0[494] = _4692; + uint16_t _4693 = (uint16_t)(190); + _curvea0[495] = _4693; + uint16_t _4694 = (uint16_t)(190); + _curvea0[496] = _4694; + uint16_t _4695 = (uint16_t)(190); + _curvea0[497] = _4695; + uint16_t _4696 = (uint16_t)(191); + _curvea0[498] = _4696; + uint16_t _4697 = (uint16_t)(191); + _curvea0[499] = _4697; + uint16_t _4698 = (uint16_t)(191); + _curvea0[500] = _4698; + uint16_t _4699 = (uint16_t)(191); + _curvea0[501] = _4699; + uint16_t _4700 = (uint16_t)(191); + _curvea0[502] = _4700; + uint16_t _4701 = (uint16_t)(192); + _curvea0[503] = _4701; + uint16_t _4702 = (uint16_t)(192); + _curvea0[504] = _4702; + uint16_t _4703 = (uint16_t)(192); + _curvea0[505] = _4703; + uint16_t _4704 = (uint16_t)(192); + _curvea0[506] = _4704; + uint16_t _4705 = (uint16_t)(192); + _curvea0[507] = _4705; + uint16_t _4706 = (uint16_t)(193); + _curvea0[508] = _4706; + uint16_t _4707 = (uint16_t)(193); + _curvea0[509] = _4707; + uint16_t _4708 = (uint16_t)(193); + _curvea0[510] = _4708; + uint16_t _4709 = (uint16_t)(193); + _curvea0[511] = _4709; + uint16_t _4710 = (uint16_t)(193); + _curvea0[512] = _4710; + uint16_t _4711 = (uint16_t)(194); + _curvea0[513] = _4711; + uint16_t _4712 = (uint16_t)(194); + _curvea0[514] = _4712; + uint16_t _4713 = (uint16_t)(194); + _curvea0[515] = _4713; + uint16_t _4714 = (uint16_t)(194); + _curvea0[516] = _4714; + uint16_t _4715 = (uint16_t)(194); + _curvea0[517] = _4715; + uint16_t _4716 = (uint16_t)(195); + _curvea0[518] = _4716; + uint16_t _4717 = (uint16_t)(195); + _curvea0[519] = _4717; + uint16_t _4718 = (uint16_t)(195); + _curvea0[520] = _4718; + uint16_t _4719 = (uint16_t)(195); + _curvea0[521] = _4719; + uint16_t _4720 = (uint16_t)(195); + _curvea0[522] = _4720; + uint16_t _4721 = (uint16_t)(195); + _curvea0[523] = _4721; + uint16_t _4722 = (uint16_t)(196); + _curvea0[524] = _4722; + uint16_t _4723 = (uint16_t)(196); + _curvea0[525] = _4723; + uint16_t _4724 = (uint16_t)(196); + _curvea0[526] = _4724; + uint16_t _4725 = (uint16_t)(196); + _curvea0[527] = _4725; + uint16_t _4726 = (uint16_t)(196); + _curvea0[528] = _4726; + uint16_t _4727 = (uint16_t)(197); + _curvea0[529] = _4727; + uint16_t _4728 = (uint16_t)(197); + _curvea0[530] = _4728; + uint16_t _4729 = (uint16_t)(197); + _curvea0[531] = _4729; + uint16_t _4730 = (uint16_t)(197); + _curvea0[532] = _4730; + uint16_t _4731 = (uint16_t)(197); + _curvea0[533] = _4731; + uint16_t _4732 = (uint16_t)(197); + _curvea0[534] = _4732; + uint16_t _4733 = (uint16_t)(198); + _curvea0[535] = _4733; + uint16_t _4734 = (uint16_t)(198); + _curvea0[536] = _4734; + uint16_t _4735 = (uint16_t)(198); + _curvea0[537] = _4735; + uint16_t _4736 = (uint16_t)(198); + _curvea0[538] = _4736; + uint16_t _4737 = (uint16_t)(198); + _curvea0[539] = _4737; + uint16_t _4738 = (uint16_t)(199); + _curvea0[540] = _4738; + uint16_t _4739 = (uint16_t)(199); + _curvea0[541] = _4739; + uint16_t _4740 = (uint16_t)(199); + _curvea0[542] = _4740; + uint16_t _4741 = (uint16_t)(199); + _curvea0[543] = _4741; + uint16_t _4742 = (uint16_t)(199); + _curvea0[544] = _4742; + uint16_t _4743 = (uint16_t)(199); + _curvea0[545] = _4743; + uint16_t _4744 = (uint16_t)(200); + _curvea0[546] = _4744; + uint16_t _4745 = (uint16_t)(200); + _curvea0[547] = _4745; + uint16_t _4746 = (uint16_t)(200); + _curvea0[548] = _4746; + uint16_t _4747 = (uint16_t)(200); + _curvea0[549] = _4747; + uint16_t _4748 = (uint16_t)(200); + _curvea0[550] = _4748; + uint16_t _4749 = (uint16_t)(200); + _curvea0[551] = _4749; + uint16_t _4750 = (uint16_t)(201); + _curvea0[552] = _4750; + uint16_t _4751 = (uint16_t)(201); + _curvea0[553] = _4751; + uint16_t _4752 = (uint16_t)(201); + _curvea0[554] = _4752; + uint16_t _4753 = (uint16_t)(201); + _curvea0[555] = _4753; + uint16_t _4754 = (uint16_t)(201); + _curvea0[556] = _4754; + uint16_t _4755 = (uint16_t)(202); + _curvea0[557] = _4755; + uint16_t _4756 = (uint16_t)(202); + _curvea0[558] = _4756; + uint16_t _4757 = (uint16_t)(202); + _curvea0[559] = _4757; + uint16_t _4758 = (uint16_t)(202); + _curvea0[560] = _4758; + uint16_t _4759 = (uint16_t)(202); + _curvea0[561] = _4759; + uint16_t _4760 = (uint16_t)(202); + _curvea0[562] = _4760; + uint16_t _4761 = (uint16_t)(203); + _curvea0[563] = _4761; + uint16_t _4762 = (uint16_t)(203); + _curvea0[564] = _4762; + uint16_t _4763 = (uint16_t)(203); + _curvea0[565] = _4763; + uint16_t _4764 = (uint16_t)(203); + _curvea0[566] = _4764; + uint16_t _4765 = (uint16_t)(203); + _curvea0[567] = _4765; + uint16_t _4766 = (uint16_t)(203); + _curvea0[568] = _4766; + uint16_t _4767 = (uint16_t)(204); + _curvea0[569] = _4767; + uint16_t _4768 = (uint16_t)(204); + _curvea0[570] = _4768; + uint16_t _4769 = (uint16_t)(204); + _curvea0[571] = _4769; + uint16_t _4770 = (uint16_t)(204); + _curvea0[572] = _4770; + uint16_t _4771 = (uint16_t)(204); + _curvea0[573] = _4771; + uint16_t _4772 = (uint16_t)(204); + _curvea0[574] = _4772; + uint16_t _4773 = (uint16_t)(205); + _curvea0[575] = _4773; + uint16_t _4774 = (uint16_t)(205); + _curvea0[576] = _4774; + uint16_t _4775 = (uint16_t)(205); + _curvea0[577] = _4775; + uint16_t _4776 = (uint16_t)(205); + _curvea0[578] = _4776; + uint16_t _4777 = (uint16_t)(205); + _curvea0[579] = _4777; + uint16_t _4778 = (uint16_t)(205); + _curvea0[580] = _4778; + uint16_t _4779 = (uint16_t)(206); + _curvea0[581] = _4779; + uint16_t _4780 = (uint16_t)(206); + _curvea0[582] = _4780; + uint16_t _4781 = (uint16_t)(206); + _curvea0[583] = _4781; + uint16_t _4782 = (uint16_t)(206); + _curvea0[584] = _4782; + uint16_t _4783 = (uint16_t)(206); + _curvea0[585] = _4783; + uint16_t _4784 = (uint16_t)(206); + _curvea0[586] = _4784; + uint16_t _4785 = (uint16_t)(207); + _curvea0[587] = _4785; + uint16_t _4786 = (uint16_t)(207); + _curvea0[588] = _4786; + uint16_t _4787 = (uint16_t)(207); + _curvea0[589] = _4787; + uint16_t _4788 = (uint16_t)(207); + _curvea0[590] = _4788; + uint16_t _4789 = (uint16_t)(207); + _curvea0[591] = _4789; + uint16_t _4790 = (uint16_t)(207); + _curvea0[592] = _4790; + uint16_t _4791 = (uint16_t)(208); + _curvea0[593] = _4791; + uint16_t _4792 = (uint16_t)(208); + _curvea0[594] = _4792; + uint16_t _4793 = (uint16_t)(208); + _curvea0[595] = _4793; + uint16_t _4794 = (uint16_t)(208); + _curvea0[596] = _4794; + uint16_t _4795 = (uint16_t)(208); + _curvea0[597] = _4795; + uint16_t _4796 = (uint16_t)(208); + _curvea0[598] = _4796; + uint16_t _4797 = (uint16_t)(209); + _curvea0[599] = _4797; + uint16_t _4798 = (uint16_t)(209); + _curvea0[600] = _4798; + uint16_t _4799 = (uint16_t)(209); + _curvea0[601] = _4799; + uint16_t _4800 = (uint16_t)(209); + _curvea0[602] = _4800; + uint16_t _4801 = (uint16_t)(209); + _curvea0[603] = _4801; + uint16_t _4802 = (uint16_t)(209); + _curvea0[604] = _4802; + uint16_t _4803 = (uint16_t)(209); + _curvea0[605] = _4803; + uint16_t _4804 = (uint16_t)(210); + _curvea0[606] = _4804; + uint16_t _4805 = (uint16_t)(210); + _curvea0[607] = _4805; + uint16_t _4806 = (uint16_t)(210); + _curvea0[608] = _4806; + uint16_t _4807 = (uint16_t)(210); + _curvea0[609] = _4807; + uint16_t _4808 = (uint16_t)(210); + _curvea0[610] = _4808; + uint16_t _4809 = (uint16_t)(210); + _curvea0[611] = _4809; + uint16_t _4810 = (uint16_t)(211); + _curvea0[612] = _4810; + uint16_t _4811 = (uint16_t)(211); + _curvea0[613] = _4811; + uint16_t _4812 = (uint16_t)(211); + _curvea0[614] = _4812; + uint16_t _4813 = (uint16_t)(211); + _curvea0[615] = _4813; + uint16_t _4814 = (uint16_t)(211); + _curvea0[616] = _4814; + uint16_t _4815 = (uint16_t)(211); + _curvea0[617] = _4815; + uint16_t _4816 = (uint16_t)(211); + _curvea0[618] = _4816; + uint16_t _4817 = (uint16_t)(212); + _curvea0[619] = _4817; + uint16_t _4818 = (uint16_t)(212); + _curvea0[620] = _4818; + uint16_t _4819 = (uint16_t)(212); + _curvea0[621] = _4819; + uint16_t _4820 = (uint16_t)(212); + _curvea0[622] = _4820; + uint16_t _4821 = (uint16_t)(212); + _curvea0[623] = _4821; + uint16_t _4822 = (uint16_t)(212); + _curvea0[624] = _4822; + uint16_t _4823 = (uint16_t)(213); + _curvea0[625] = _4823; + uint16_t _4824 = (uint16_t)(213); + _curvea0[626] = _4824; + uint16_t _4825 = (uint16_t)(213); + _curvea0[627] = _4825; + uint16_t _4826 = (uint16_t)(213); + _curvea0[628] = _4826; + uint16_t _4827 = (uint16_t)(213); + _curvea0[629] = _4827; + uint16_t _4828 = (uint16_t)(213); + _curvea0[630] = _4828; + uint16_t _4829 = (uint16_t)(213); + _curvea0[631] = _4829; + uint16_t _4830 = (uint16_t)(214); + _curvea0[632] = _4830; + uint16_t _4831 = (uint16_t)(214); + _curvea0[633] = _4831; + uint16_t _4832 = (uint16_t)(214); + _curvea0[634] = _4832; + uint16_t _4833 = (uint16_t)(214); + _curvea0[635] = _4833; + uint16_t _4834 = (uint16_t)(214); + _curvea0[636] = _4834; + uint16_t _4835 = (uint16_t)(214); + _curvea0[637] = _4835; + uint16_t _4836 = (uint16_t)(214); + _curvea0[638] = _4836; + uint16_t _4837 = (uint16_t)(215); + _curvea0[639] = _4837; + uint16_t _4838 = (uint16_t)(215); + _curvea0[640] = _4838; + uint16_t _4839 = (uint16_t)(215); + _curvea0[641] = _4839; + uint16_t _4840 = (uint16_t)(215); + _curvea0[642] = _4840; + uint16_t _4841 = (uint16_t)(215); + _curvea0[643] = _4841; + uint16_t _4842 = (uint16_t)(215); + _curvea0[644] = _4842; + uint16_t _4843 = (uint16_t)(216); + _curvea0[645] = _4843; + uint16_t _4844 = (uint16_t)(216); + _curvea0[646] = _4844; + uint16_t _4845 = (uint16_t)(216); + _curvea0[647] = _4845; + uint16_t _4846 = (uint16_t)(216); + _curvea0[648] = _4846; + uint16_t _4847 = (uint16_t)(216); + _curvea0[649] = _4847; + uint16_t _4848 = (uint16_t)(216); + _curvea0[650] = _4848; + uint16_t _4849 = (uint16_t)(216); + _curvea0[651] = _4849; + uint16_t _4850 = (uint16_t)(217); + _curvea0[652] = _4850; + uint16_t _4851 = (uint16_t)(217); + _curvea0[653] = _4851; + uint16_t _4852 = (uint16_t)(217); + _curvea0[654] = _4852; + uint16_t _4853 = (uint16_t)(217); + _curvea0[655] = _4853; + uint16_t _4854 = (uint16_t)(217); + _curvea0[656] = _4854; + uint16_t _4855 = (uint16_t)(217); + _curvea0[657] = _4855; + uint16_t _4856 = (uint16_t)(217); + _curvea0[658] = _4856; + uint16_t _4857 = (uint16_t)(218); + _curvea0[659] = _4857; + uint16_t _4858 = (uint16_t)(218); + _curvea0[660] = _4858; + uint16_t _4859 = (uint16_t)(218); + _curvea0[661] = _4859; + uint16_t _4860 = (uint16_t)(218); + _curvea0[662] = _4860; + uint16_t _4861 = (uint16_t)(218); + _curvea0[663] = _4861; + uint16_t _4862 = (uint16_t)(218); + _curvea0[664] = _4862; + uint16_t _4863 = (uint16_t)(218); + _curvea0[665] = _4863; + uint16_t _4864 = (uint16_t)(219); + _curvea0[666] = _4864; + uint16_t _4865 = (uint16_t)(219); + _curvea0[667] = _4865; + uint16_t _4866 = (uint16_t)(219); + _curvea0[668] = _4866; + uint16_t _4867 = (uint16_t)(219); + _curvea0[669] = _4867; + uint16_t _4868 = (uint16_t)(219); + _curvea0[670] = _4868; + uint16_t _4869 = (uint16_t)(219); + _curvea0[671] = _4869; + uint16_t _4870 = (uint16_t)(219); + _curvea0[672] = _4870; + uint16_t _4871 = (uint16_t)(220); + _curvea0[673] = _4871; + uint16_t _4872 = (uint16_t)(220); + _curvea0[674] = _4872; + uint16_t _4873 = (uint16_t)(220); + _curvea0[675] = _4873; + uint16_t _4874 = (uint16_t)(220); + _curvea0[676] = _4874; + uint16_t _4875 = (uint16_t)(220); + _curvea0[677] = _4875; + uint16_t _4876 = (uint16_t)(220); + _curvea0[678] = _4876; + uint16_t _4877 = (uint16_t)(220); + _curvea0[679] = _4877; + uint16_t _4878 = (uint16_t)(220); + _curvea0[680] = _4878; + uint16_t _4879 = (uint16_t)(221); + _curvea0[681] = _4879; + uint16_t _4880 = (uint16_t)(221); + _curvea0[682] = _4880; + uint16_t _4881 = (uint16_t)(221); + _curvea0[683] = _4881; + uint16_t _4882 = (uint16_t)(221); + _curvea0[684] = _4882; + uint16_t _4883 = (uint16_t)(221); + _curvea0[685] = _4883; + uint16_t _4884 = (uint16_t)(221); + _curvea0[686] = _4884; + uint16_t _4885 = (uint16_t)(221); + _curvea0[687] = _4885; + uint16_t _4886 = (uint16_t)(222); + _curvea0[688] = _4886; + uint16_t _4887 = (uint16_t)(222); + _curvea0[689] = _4887; + uint16_t _4888 = (uint16_t)(222); + _curvea0[690] = _4888; + uint16_t _4889 = (uint16_t)(222); + _curvea0[691] = _4889; + uint16_t _4890 = (uint16_t)(222); + _curvea0[692] = _4890; + uint16_t _4891 = (uint16_t)(222); + _curvea0[693] = _4891; + uint16_t _4892 = (uint16_t)(222); + _curvea0[694] = _4892; + uint16_t _4893 = (uint16_t)(223); + _curvea0[695] = _4893; + uint16_t _4894 = (uint16_t)(223); + _curvea0[696] = _4894; + uint16_t _4895 = (uint16_t)(223); + _curvea0[697] = _4895; + uint16_t _4896 = (uint16_t)(223); + _curvea0[698] = _4896; + uint16_t _4897 = (uint16_t)(223); + _curvea0[699] = _4897; + uint16_t _4898 = (uint16_t)(223); + _curvea0[700] = _4898; + uint16_t _4899 = (uint16_t)(223); + _curvea0[701] = _4899; + uint16_t _4900 = (uint16_t)(223); + _curvea0[702] = _4900; + uint16_t _4901 = (uint16_t)(224); + _curvea0[703] = _4901; + uint16_t _4902 = (uint16_t)(224); + _curvea0[704] = _4902; + uint16_t _4903 = (uint16_t)(224); + _curvea0[705] = _4903; + uint16_t _4904 = (uint16_t)(224); + _curvea0[706] = _4904; + uint16_t _4905 = (uint16_t)(224); + _curvea0[707] = _4905; + uint16_t _4906 = (uint16_t)(224); + _curvea0[708] = _4906; + uint16_t _4907 = (uint16_t)(224); + _curvea0[709] = _4907; + uint16_t _4908 = (uint16_t)(224); + _curvea0[710] = _4908; + uint16_t _4909 = (uint16_t)(225); + _curvea0[711] = _4909; + uint16_t _4910 = (uint16_t)(225); + _curvea0[712] = _4910; + uint16_t _4911 = (uint16_t)(225); + _curvea0[713] = _4911; + uint16_t _4912 = (uint16_t)(225); + _curvea0[714] = _4912; + uint16_t _4913 = (uint16_t)(225); + _curvea0[715] = _4913; + uint16_t _4914 = (uint16_t)(225); + _curvea0[716] = _4914; + uint16_t _4915 = (uint16_t)(225); + _curvea0[717] = _4915; + uint16_t _4916 = (uint16_t)(226); + _curvea0[718] = _4916; + uint16_t _4917 = (uint16_t)(226); + _curvea0[719] = _4917; + uint16_t _4918 = (uint16_t)(226); + _curvea0[720] = _4918; + uint16_t _4919 = (uint16_t)(226); + _curvea0[721] = _4919; + uint16_t _4920 = (uint16_t)(226); + _curvea0[722] = _4920; + uint16_t _4921 = (uint16_t)(226); + _curvea0[723] = _4921; + uint16_t _4922 = (uint16_t)(226); + _curvea0[724] = _4922; + uint16_t _4923 = (uint16_t)(226); + _curvea0[725] = _4923; + uint16_t _4924 = (uint16_t)(227); + _curvea0[726] = _4924; + uint16_t _4925 = (uint16_t)(227); + _curvea0[727] = _4925; + uint16_t _4926 = (uint16_t)(227); + _curvea0[728] = _4926; + uint16_t _4927 = (uint16_t)(227); + _curvea0[729] = _4927; + uint16_t _4928 = (uint16_t)(227); + _curvea0[730] = _4928; + uint16_t _4929 = (uint16_t)(227); + _curvea0[731] = _4929; + uint16_t _4930 = (uint16_t)(227); + _curvea0[732] = _4930; + uint16_t _4931 = (uint16_t)(227); + _curvea0[733] = _4931; + uint16_t _4932 = (uint16_t)(228); + _curvea0[734] = _4932; + uint16_t _4933 = (uint16_t)(228); + _curvea0[735] = _4933; + uint16_t _4934 = (uint16_t)(228); + _curvea0[736] = _4934; + uint16_t _4935 = (uint16_t)(228); + _curvea0[737] = _4935; + uint16_t _4936 = (uint16_t)(228); + _curvea0[738] = _4936; + uint16_t _4937 = (uint16_t)(228); + _curvea0[739] = _4937; + uint16_t _4938 = (uint16_t)(228); + _curvea0[740] = _4938; + uint16_t _4939 = (uint16_t)(228); + _curvea0[741] = _4939; + uint16_t _4940 = (uint16_t)(228); + _curvea0[742] = _4940; + uint16_t _4941 = (uint16_t)(229); + _curvea0[743] = _4941; + uint16_t _4942 = (uint16_t)(229); + _curvea0[744] = _4942; + uint16_t _4943 = (uint16_t)(229); + _curvea0[745] = _4943; + uint16_t _4944 = (uint16_t)(229); + _curvea0[746] = _4944; + uint16_t _4945 = (uint16_t)(229); + _curvea0[747] = _4945; + uint16_t _4946 = (uint16_t)(229); + _curvea0[748] = _4946; + uint16_t _4947 = (uint16_t)(229); + _curvea0[749] = _4947; + uint16_t _4948 = (uint16_t)(229); + _curvea0[750] = _4948; + uint16_t _4949 = (uint16_t)(230); + _curvea0[751] = _4949; + uint16_t _4950 = (uint16_t)(230); + _curvea0[752] = _4950; + uint16_t _4951 = (uint16_t)(230); + _curvea0[753] = _4951; + uint16_t _4952 = (uint16_t)(230); + _curvea0[754] = _4952; + uint16_t _4953 = (uint16_t)(230); + _curvea0[755] = _4953; + uint16_t _4954 = (uint16_t)(230); + _curvea0[756] = _4954; + uint16_t _4955 = (uint16_t)(230); + _curvea0[757] = _4955; + uint16_t _4956 = (uint16_t)(230); + _curvea0[758] = _4956; + uint16_t _4957 = (uint16_t)(231); + _curvea0[759] = _4957; + uint16_t _4958 = (uint16_t)(231); + _curvea0[760] = _4958; + uint16_t _4959 = (uint16_t)(231); + _curvea0[761] = _4959; + uint16_t _4960 = (uint16_t)(231); + _curvea0[762] = _4960; + uint16_t _4961 = (uint16_t)(231); + _curvea0[763] = _4961; + uint16_t _4962 = (uint16_t)(231); + _curvea0[764] = _4962; + uint16_t _4963 = (uint16_t)(231); + _curvea0[765] = _4963; + uint16_t _4964 = (uint16_t)(231); + _curvea0[766] = _4964; + uint16_t _4965 = (uint16_t)(231); + _curvea0[767] = _4965; + uint16_t _4966 = (uint16_t)(232); + _curvea0[768] = _4966; + uint16_t _4967 = (uint16_t)(232); + _curvea0[769] = _4967; + uint16_t _4968 = (uint16_t)(232); + _curvea0[770] = _4968; + uint16_t _4969 = (uint16_t)(232); + _curvea0[771] = _4969; + uint16_t _4970 = (uint16_t)(232); + _curvea0[772] = _4970; + uint16_t _4971 = (uint16_t)(232); + _curvea0[773] = _4971; + uint16_t _4972 = (uint16_t)(232); + _curvea0[774] = _4972; + uint16_t _4973 = (uint16_t)(232); + _curvea0[775] = _4973; + uint16_t _4974 = (uint16_t)(233); + _curvea0[776] = _4974; + uint16_t _4975 = (uint16_t)(233); + _curvea0[777] = _4975; + uint16_t _4976 = (uint16_t)(233); + _curvea0[778] = _4976; + uint16_t _4977 = (uint16_t)(233); + _curvea0[779] = _4977; + uint16_t _4978 = (uint16_t)(233); + _curvea0[780] = _4978; + uint16_t _4979 = (uint16_t)(233); + _curvea0[781] = _4979; + uint16_t _4980 = (uint16_t)(233); + _curvea0[782] = _4980; + uint16_t _4981 = (uint16_t)(233); + _curvea0[783] = _4981; + uint16_t _4982 = (uint16_t)(233); + _curvea0[784] = _4982; + uint16_t _4983 = (uint16_t)(234); + _curvea0[785] = _4983; + uint16_t _4984 = (uint16_t)(234); + _curvea0[786] = _4984; + uint16_t _4985 = (uint16_t)(234); + _curvea0[787] = _4985; + uint16_t _4986 = (uint16_t)(234); + _curvea0[788] = _4986; + uint16_t _4987 = (uint16_t)(234); + _curvea0[789] = _4987; + uint16_t _4988 = (uint16_t)(234); + _curvea0[790] = _4988; + uint16_t _4989 = (uint16_t)(234); + _curvea0[791] = _4989; + uint16_t _4990 = (uint16_t)(234); + _curvea0[792] = _4990; + uint16_t _4991 = (uint16_t)(234); + _curvea0[793] = _4991; + uint16_t _4992 = (uint16_t)(235); + _curvea0[794] = _4992; + uint16_t _4993 = (uint16_t)(235); + _curvea0[795] = _4993; + uint16_t _4994 = (uint16_t)(235); + _curvea0[796] = _4994; + uint16_t _4995 = (uint16_t)(235); + _curvea0[797] = _4995; + uint16_t _4996 = (uint16_t)(235); + _curvea0[798] = _4996; + uint16_t _4997 = (uint16_t)(235); + _curvea0[799] = _4997; + uint16_t _4998 = (uint16_t)(235); + _curvea0[800] = _4998; + uint16_t _4999 = (uint16_t)(235); + _curvea0[801] = _4999; + uint16_t _5000 = (uint16_t)(235); + _curvea0[802] = _5000; + uint16_t _5001 = (uint16_t)(236); + _curvea0[803] = _5001; + uint16_t _5002 = (uint16_t)(236); + _curvea0[804] = _5002; + uint16_t _5003 = (uint16_t)(236); + _curvea0[805] = _5003; + uint16_t _5004 = (uint16_t)(236); + _curvea0[806] = _5004; + uint16_t _5005 = (uint16_t)(236); + _curvea0[807] = _5005; + uint16_t _5006 = (uint16_t)(236); + _curvea0[808] = _5006; + uint16_t _5007 = (uint16_t)(236); + _curvea0[809] = _5007; + uint16_t _5008 = (uint16_t)(236); + _curvea0[810] = _5008; + uint16_t _5009 = (uint16_t)(236); + _curvea0[811] = _5009; + uint16_t _5010 = (uint16_t)(237); + _curvea0[812] = _5010; + uint16_t _5011 = (uint16_t)(237); + _curvea0[813] = _5011; + uint16_t _5012 = (uint16_t)(237); + _curvea0[814] = _5012; + uint16_t _5013 = (uint16_t)(237); + _curvea0[815] = _5013; + uint16_t _5014 = (uint16_t)(237); + _curvea0[816] = _5014; + uint16_t _5015 = (uint16_t)(237); + _curvea0[817] = _5015; + uint16_t _5016 = (uint16_t)(237); + _curvea0[818] = _5016; + uint16_t _5017 = (uint16_t)(237); + _curvea0[819] = _5017; + uint16_t _5018 = (uint16_t)(237); + _curvea0[820] = _5018; + uint16_t _5019 = (uint16_t)(237); + _curvea0[821] = _5019; + uint16_t _5020 = (uint16_t)(238); + _curvea0[822] = _5020; + uint16_t _5021 = (uint16_t)(238); + _curvea0[823] = _5021; + uint16_t _5022 = (uint16_t)(238); + _curvea0[824] = _5022; + uint16_t _5023 = (uint16_t)(238); + _curvea0[825] = _5023; + uint16_t _5024 = (uint16_t)(238); + _curvea0[826] = _5024; + uint16_t _5025 = (uint16_t)(238); + _curvea0[827] = _5025; + uint16_t _5026 = (uint16_t)(238); + _curvea0[828] = _5026; + uint16_t _5027 = (uint16_t)(238); + _curvea0[829] = _5027; + uint16_t _5028 = (uint16_t)(238); + _curvea0[830] = _5028; + uint16_t _5029 = (uint16_t)(239); + _curvea0[831] = _5029; + uint16_t _5030 = (uint16_t)(239); + _curvea0[832] = _5030; + uint16_t _5031 = (uint16_t)(239); + _curvea0[833] = _5031; + uint16_t _5032 = (uint16_t)(239); + _curvea0[834] = _5032; + uint16_t _5033 = (uint16_t)(239); + _curvea0[835] = _5033; + uint16_t _5034 = (uint16_t)(239); + _curvea0[836] = _5034; + uint16_t _5035 = (uint16_t)(239); + _curvea0[837] = _5035; + uint16_t _5036 = (uint16_t)(239); + _curvea0[838] = _5036; + uint16_t _5037 = (uint16_t)(239); + _curvea0[839] = _5037; + uint16_t _5038 = (uint16_t)(239); + _curvea0[840] = _5038; + uint16_t _5039 = (uint16_t)(240); + _curvea0[841] = _5039; + uint16_t _5040 = (uint16_t)(240); + _curvea0[842] = _5040; + uint16_t _5041 = (uint16_t)(240); + _curvea0[843] = _5041; + uint16_t _5042 = (uint16_t)(240); + _curvea0[844] = _5042; + uint16_t _5043 = (uint16_t)(240); + _curvea0[845] = _5043; + uint16_t _5044 = (uint16_t)(240); + _curvea0[846] = _5044; + uint16_t _5045 = (uint16_t)(240); + _curvea0[847] = _5045; + uint16_t _5046 = (uint16_t)(240); + _curvea0[848] = _5046; + uint16_t _5047 = (uint16_t)(240); + _curvea0[849] = _5047; + uint16_t _5048 = (uint16_t)(240); + _curvea0[850] = _5048; + uint16_t _5049 = (uint16_t)(241); + _curvea0[851] = _5049; + uint16_t _5050 = (uint16_t)(241); + _curvea0[852] = _5050; + uint16_t _5051 = (uint16_t)(241); + _curvea0[853] = _5051; + uint16_t _5052 = (uint16_t)(241); + _curvea0[854] = _5052; + uint16_t _5053 = (uint16_t)(241); + _curvea0[855] = _5053; + uint16_t _5054 = (uint16_t)(241); + _curvea0[856] = _5054; + uint16_t _5055 = (uint16_t)(241); + _curvea0[857] = _5055; + uint16_t _5056 = (uint16_t)(241); + _curvea0[858] = _5056; + uint16_t _5057 = (uint16_t)(241); + _curvea0[859] = _5057; + uint16_t _5058 = (uint16_t)(241); + _curvea0[860] = _5058; + uint16_t _5059 = (uint16_t)(242); + _curvea0[861] = _5059; + uint16_t _5060 = (uint16_t)(242); + _curvea0[862] = _5060; + uint16_t _5061 = (uint16_t)(242); + _curvea0[863] = _5061; + uint16_t _5062 = (uint16_t)(242); + _curvea0[864] = _5062; + uint16_t _5063 = (uint16_t)(242); + _curvea0[865] = _5063; + uint16_t _5064 = (uint16_t)(242); + _curvea0[866] = _5064; + uint16_t _5065 = (uint16_t)(242); + _curvea0[867] = _5065; + uint16_t _5066 = (uint16_t)(242); + _curvea0[868] = _5066; + uint16_t _5067 = (uint16_t)(242); + _curvea0[869] = _5067; + uint16_t _5068 = (uint16_t)(242); + _curvea0[870] = _5068; + uint16_t _5069 = (uint16_t)(243); + _curvea0[871] = _5069; + uint16_t _5070 = (uint16_t)(243); + _curvea0[872] = _5070; + uint16_t _5071 = (uint16_t)(243); + _curvea0[873] = _5071; + uint16_t _5072 = (uint16_t)(243); + _curvea0[874] = _5072; + uint16_t _5073 = (uint16_t)(243); + _curvea0[875] = _5073; + uint16_t _5074 = (uint16_t)(243); + _curvea0[876] = _5074; + uint16_t _5075 = (uint16_t)(243); + _curvea0[877] = _5075; + uint16_t _5076 = (uint16_t)(243); + _curvea0[878] = _5076; + uint16_t _5077 = (uint16_t)(243); + _curvea0[879] = _5077; + uint16_t _5078 = (uint16_t)(243); + _curvea0[880] = _5078; + uint16_t _5079 = (uint16_t)(244); + _curvea0[881] = _5079; + uint16_t _5080 = (uint16_t)(244); + _curvea0[882] = _5080; + uint16_t _5081 = (uint16_t)(244); + _curvea0[883] = _5081; + uint16_t _5082 = (uint16_t)(244); + _curvea0[884] = _5082; + uint16_t _5083 = (uint16_t)(244); + _curvea0[885] = _5083; + uint16_t _5084 = (uint16_t)(244); + _curvea0[886] = _5084; + uint16_t _5085 = (uint16_t)(244); + _curvea0[887] = _5085; + uint16_t _5086 = (uint16_t)(244); + _curvea0[888] = _5086; + uint16_t _5087 = (uint16_t)(244); + _curvea0[889] = _5087; + uint16_t _5088 = (uint16_t)(244); + _curvea0[890] = _5088; + uint16_t _5089 = (uint16_t)(244); + _curvea0[891] = _5089; + uint16_t _5090 = (uint16_t)(245); + _curvea0[892] = _5090; + uint16_t _5091 = (uint16_t)(245); + _curvea0[893] = _5091; + uint16_t _5092 = (uint16_t)(245); + _curvea0[894] = _5092; + uint16_t _5093 = (uint16_t)(245); + _curvea0[895] = _5093; + uint16_t _5094 = (uint16_t)(245); + _curvea0[896] = _5094; + uint16_t _5095 = (uint16_t)(245); + _curvea0[897] = _5095; + uint16_t _5096 = (uint16_t)(245); + _curvea0[898] = _5096; + uint16_t _5097 = (uint16_t)(245); + _curvea0[899] = _5097; + uint16_t _5098 = (uint16_t)(245); + _curvea0[900] = _5098; + uint16_t _5099 = (uint16_t)(245); + _curvea0[901] = _5099; + uint16_t _5100 = (uint16_t)(245); + _curvea0[902] = _5100; + uint16_t _5101 = (uint16_t)(246); + _curvea0[903] = _5101; + uint16_t _5102 = (uint16_t)(246); + _curvea0[904] = _5102; + uint16_t _5103 = (uint16_t)(246); + _curvea0[905] = _5103; + uint16_t _5104 = (uint16_t)(246); + _curvea0[906] = _5104; + uint16_t _5105 = (uint16_t)(246); + _curvea0[907] = _5105; + uint16_t _5106 = (uint16_t)(246); + _curvea0[908] = _5106; + uint16_t _5107 = (uint16_t)(246); + _curvea0[909] = _5107; + uint16_t _5108 = (uint16_t)(246); + _curvea0[910] = _5108; + uint16_t _5109 = (uint16_t)(246); + _curvea0[911] = _5109; + uint16_t _5110 = (uint16_t)(246); + _curvea0[912] = _5110; + uint16_t _5111 = (uint16_t)(246); + _curvea0[913] = _5111; + uint16_t _5112 = (uint16_t)(247); + _curvea0[914] = _5112; + uint16_t _5113 = (uint16_t)(247); + _curvea0[915] = _5113; + uint16_t _5114 = (uint16_t)(247); + _curvea0[916] = _5114; + uint16_t _5115 = (uint16_t)(247); + _curvea0[917] = _5115; + uint16_t _5116 = (uint16_t)(247); + _curvea0[918] = _5116; + uint16_t _5117 = (uint16_t)(247); + _curvea0[919] = _5117; + uint16_t _5118 = (uint16_t)(247); + _curvea0[920] = _5118; + uint16_t _5119 = (uint16_t)(247); + _curvea0[921] = _5119; + uint16_t _5120 = (uint16_t)(247); + _curvea0[922] = _5120; + uint16_t _5121 = (uint16_t)(247); + _curvea0[923] = _5121; + uint16_t _5122 = (uint16_t)(247); + _curvea0[924] = _5122; + uint16_t _5123 = (uint16_t)(248); + _curvea0[925] = _5123; + uint16_t _5124 = (uint16_t)(248); + _curvea0[926] = _5124; + uint16_t _5125 = (uint16_t)(248); + _curvea0[927] = _5125; + uint16_t _5126 = (uint16_t)(248); + _curvea0[928] = _5126; + uint16_t _5127 = (uint16_t)(248); + _curvea0[929] = _5127; + uint16_t _5128 = (uint16_t)(248); + _curvea0[930] = _5128; + uint16_t _5129 = (uint16_t)(248); + _curvea0[931] = _5129; + uint16_t _5130 = (uint16_t)(248); + _curvea0[932] = _5130; + uint16_t _5131 = (uint16_t)(248); + _curvea0[933] = _5131; + uint16_t _5132 = (uint16_t)(248); + _curvea0[934] = _5132; + uint16_t _5133 = (uint16_t)(248); + _curvea0[935] = _5133; + uint16_t _5134 = (uint16_t)(249); + _curvea0[936] = _5134; + uint16_t _5135 = (uint16_t)(249); + _curvea0[937] = _5135; + uint16_t _5136 = (uint16_t)(249); + _curvea0[938] = _5136; + uint16_t _5137 = (uint16_t)(249); + _curvea0[939] = _5137; + uint16_t _5138 = (uint16_t)(249); + _curvea0[940] = _5138; + uint16_t _5139 = (uint16_t)(249); + _curvea0[941] = _5139; + uint16_t _5140 = (uint16_t)(249); + _curvea0[942] = _5140; + uint16_t _5141 = (uint16_t)(249); + _curvea0[943] = _5141; + uint16_t _5142 = (uint16_t)(249); + _curvea0[944] = _5142; + uint16_t _5143 = (uint16_t)(249); + _curvea0[945] = _5143; + uint16_t _5144 = (uint16_t)(249); + _curvea0[946] = _5144; + uint16_t _5145 = (uint16_t)(249); + _curvea0[947] = _5145; + uint16_t _5146 = (uint16_t)(250); + _curvea0[948] = _5146; + uint16_t _5147 = (uint16_t)(250); + _curvea0[949] = _5147; + uint16_t _5148 = (uint16_t)(250); + _curvea0[950] = _5148; + uint16_t _5149 = (uint16_t)(250); + _curvea0[951] = _5149; + uint16_t _5150 = (uint16_t)(250); + _curvea0[952] = _5150; + uint16_t _5151 = (uint16_t)(250); + _curvea0[953] = _5151; + uint16_t _5152 = (uint16_t)(250); + _curvea0[954] = _5152; + uint16_t _5153 = (uint16_t)(250); + _curvea0[955] = _5153; + uint16_t _5154 = (uint16_t)(250); + _curvea0[956] = _5154; + uint16_t _5155 = (uint16_t)(250); + _curvea0[957] = _5155; + uint16_t _5156 = (uint16_t)(250); + _curvea0[958] = _5156; + uint16_t _5157 = (uint16_t)(250); + _curvea0[959] = _5157; + uint16_t _5158 = (uint16_t)(251); + _curvea0[960] = _5158; + uint16_t _5159 = (uint16_t)(251); + _curvea0[961] = _5159; + uint16_t _5160 = (uint16_t)(251); + _curvea0[962] = _5160; + uint16_t _5161 = (uint16_t)(251); + _curvea0[963] = _5161; + uint16_t _5162 = (uint16_t)(251); + _curvea0[964] = _5162; + uint16_t _5163 = (uint16_t)(251); + _curvea0[965] = _5163; + uint16_t _5164 = (uint16_t)(251); + _curvea0[966] = _5164; + uint16_t _5165 = (uint16_t)(251); + _curvea0[967] = _5165; + uint16_t _5166 = (uint16_t)(251); + _curvea0[968] = _5166; + uint16_t _5167 = (uint16_t)(251); + _curvea0[969] = _5167; + uint16_t _5168 = (uint16_t)(251); + _curvea0[970] = _5168; + uint16_t _5169 = (uint16_t)(251); + _curvea0[971] = _5169; + uint16_t _5170 = (uint16_t)(252); + _curvea0[972] = _5170; + uint16_t _5171 = (uint16_t)(252); + _curvea0[973] = _5171; + uint16_t _5172 = (uint16_t)(252); + _curvea0[974] = _5172; + uint16_t _5173 = (uint16_t)(252); + _curvea0[975] = _5173; + uint16_t _5174 = (uint16_t)(252); + _curvea0[976] = _5174; + uint16_t _5175 = (uint16_t)(252); + _curvea0[977] = _5175; + uint16_t _5176 = (uint16_t)(252); + _curvea0[978] = _5176; + uint16_t _5177 = (uint16_t)(252); + _curvea0[979] = _5177; + uint16_t _5178 = (uint16_t)(252); + _curvea0[980] = _5178; + uint16_t _5179 = (uint16_t)(252); + _curvea0[981] = _5179; + uint16_t _5180 = (uint16_t)(252); + _curvea0[982] = _5180; + uint16_t _5181 = (uint16_t)(252); + _curvea0[983] = _5181; + uint16_t _5182 = (uint16_t)(252); + _curvea0[984] = _5182; + uint16_t _5183 = (uint16_t)(253); + _curvea0[985] = _5183; + uint16_t _5184 = (uint16_t)(253); + _curvea0[986] = _5184; + uint16_t _5185 = (uint16_t)(253); + _curvea0[987] = _5185; + uint16_t _5186 = (uint16_t)(253); + _curvea0[988] = _5186; + uint16_t _5187 = (uint16_t)(253); + _curvea0[989] = _5187; + uint16_t _5188 = (uint16_t)(253); + _curvea0[990] = _5188; + uint16_t _5189 = (uint16_t)(253); + _curvea0[991] = _5189; + uint16_t _5190 = (uint16_t)(253); + _curvea0[992] = _5190; + uint16_t _5191 = (uint16_t)(253); + _curvea0[993] = _5191; + uint16_t _5192 = (uint16_t)(253); + _curvea0[994] = _5192; + uint16_t _5193 = (uint16_t)(253); + _curvea0[995] = _5193; + uint16_t _5194 = (uint16_t)(253); + _curvea0[996] = _5194; + uint16_t _5195 = (uint16_t)(253); + _curvea0[997] = _5195; + uint16_t _5196 = (uint16_t)(254); + _curvea0[998] = _5196; + uint16_t _5197 = (uint16_t)(254); + _curvea0[999] = _5197; + uint16_t _5198 = (uint16_t)(254); + _curvea0[1000] = _5198; + uint16_t _5199 = (uint16_t)(254); + _curvea0[1001] = _5199; + uint16_t _5200 = (uint16_t)(254); + _curvea0[1002] = _5200; + uint16_t _5201 = (uint16_t)(254); + _curvea0[1003] = _5201; + uint16_t _5202 = (uint16_t)(254); + _curvea0[1004] = _5202; + uint16_t _5203 = (uint16_t)(254); + _curvea0[1005] = _5203; + uint16_t _5204 = (uint16_t)(254); + _curvea0[1006] = _5204; + uint16_t _5205 = (uint16_t)(254); + _curvea0[1007] = _5205; + uint16_t _5206 = (uint16_t)(254); + _curvea0[1008] = _5206; + uint16_t _5207 = (uint16_t)(254); + _curvea0[1009] = _5207; + uint16_t _5208 = (uint16_t)(254); + _curvea0[1010] = _5208; + uint16_t _5209 = (uint16_t)(255); + _curvea0[1011] = _5209; + uint16_t _5210 = (uint16_t)(255); + _curvea0[1012] = _5210; + uint16_t _5211 = (uint16_t)(255); + _curvea0[1013] = _5211; + uint16_t _5212 = (uint16_t)(255); + _curvea0[1014] = _5212; + uint16_t _5213 = (uint16_t)(255); + _curvea0[1015] = _5213; + uint16_t _5214 = (uint16_t)(255); + _curvea0[1016] = _5214; + uint16_t _5215 = (uint16_t)(255); + _curvea0[1017] = _5215; + uint16_t _5216 = (uint16_t)(255); + _curvea0[1018] = _5216; + uint16_t _5217 = (uint16_t)(255); + _curvea0[1019] = _5217; + uint16_t _5218 = (uint16_t)(255); + _curvea0[1020] = _5218; + uint16_t _5219 = (uint16_t)(255); + _curvea0[1021] = _5219; + uint16_t _5220 = (uint16_t)(255); + _curvea0[1022] = _5220; + uint16_t _5221 = (uint16_t)(255); + _curvea0[1023] = _5221; + + int16_t _5222 = (int16_t)(1023); + int16_t _5223 = min(_corrected_stencil_3, _5222); + int16_t _5224 = (int16_t)(0); + int16_t _5225 = max(_5223, _5224); + uint16_t _5226 = (uint16_t)(_5225); + int32_t _5227 = (int32_t)(_5226); + uint16_t _5228 = ((const uint16_t *)_curvea0)[_5227]; + return _5228; +} + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = curved.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi, 0) +hw_uint<16> hcompute_hw_output_glb_stencil(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_1 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_1; +} + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = curved.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi, 1) +hw_uint<16> hcompute_hw_output_glb_stencil_1(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_2 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_2; +} + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = curved.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi, 2) +hw_uint<16> hcompute_hw_output_glb_stencil_2(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_3 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_3; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_1 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_1; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_1(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_2 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_2; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_2(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_3 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_3; +} + diff --git a/camera_pipeline_extra_buf_glb_compute.h b/camera_pipeline_extra_buf_glb_compute.h new file mode 100644 index 000000000..6b7fb4cbb --- /dev/null +++ b/camera_pipeline_extra_buf_glb_compute.h @@ -0,0 +1,13059 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_s0_y + -4) + 4)) = hw_input.stencil((((hw_input_global_wrapper_s0_x_x + (0*124))*2) + -4), (hw_input_global_wrapper_s0_y + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_s0_y + -4) + 4)) = hw_input.stencil((((hw_input_global_wrapper_s0_x_x + (0*124))*2) + -3), (hw_input_global_wrapper_s0_y + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_1(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_2 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y + -4) + 4)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y + -4) + 4)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_1 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_1; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -4) + 4)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -4) + 4)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_1(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_2 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_2; +} + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y + -2) + 2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y + -2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y + -2) + 6)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y + -2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y + -2) + 4)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y + -2) + 4)))))) +hw_uint<16> hcompute_denoised_1_stencil(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_1 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_2 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_3 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_4 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_5 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>(); + + uint16_t _351 = max(_hw_input_global_wrapper_global_wrapper_stencil_4, _hw_input_global_wrapper_global_wrapper_stencil_5); + uint16_t _352 = max(_hw_input_global_wrapper_global_wrapper_stencil_3, _351); + uint16_t _353 = max(_hw_input_global_wrapper_global_wrapper_stencil_2, _352); + uint16_t _354 = min(_hw_input_global_wrapper_global_wrapper_stencil_1, _353); + return _354; +} + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y + -2) + 2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y + -2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y + -2) + 6)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y + -2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y + -2) + 4)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y + -2) + 4)))))) +hw_uint<16> hcompute_denoised_1_stencil_1(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_10 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_6 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_7 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_8 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_9 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>(); + + uint16_t _375 = max(_hw_input_global_wrapper_global_wrapper_stencil_9, _hw_input_global_wrapper_global_wrapper_stencil_10); + uint16_t _376 = max(_hw_input_global_wrapper_global_wrapper_stencil_8, _375); + uint16_t _377 = max(_hw_input_global_wrapper_global_wrapper_stencil_7, _376); + uint16_t _378 = min(_hw_input_global_wrapper_global_wrapper_stencil_6, _377); + return _378; +} + +//store is: b_b.stencil((b_b_s0_x_x*2), ((b_b_s0_y + -1) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), (((b_b_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_b_b_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_1 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_1; +} + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), ((b_b_s0_y + -1) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), (((b_b_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_b_b_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_2 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_2; +} + +//store is: g_gb.stencil((g_gb_s0_x_x*2), ((g_gb_s0_y + -1) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), (((g_gb_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_g_gb_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_3 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_3; +} + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), ((g_gb_s0_y + -1) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), (((g_gb_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_g_gb_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_4 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_4; +} + +//store is: g_gr.stencil((g_gr_s0_x_x*2), ((g_gr_s0_y + -1) + 1)) = denoised$1.stencil((g_gr_s0_x_x*4), (((g_gr_s0_y + -1)*2) + 2)) +hw_uint<16> hcompute_g_gr_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_5 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_5; +} + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), ((g_gr_s0_y + -1) + 1)) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), (((g_gr_s0_y + -1)*2) + 2)) +hw_uint<16> hcompute_g_gr_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_6 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_6; +} + +//store is: g_b.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)) = select((absd(g_gb.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)), g_gb.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1))) < absd(g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 2)), g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)))), ((g_gb.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)) + g_gb.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)))/(uint16)2), ((g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 2)) + g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_1 = (uint16_t) g_gb_stencil.extract<0, 15>(); + uint16_t _g_gb_stencil_2 = (uint16_t) g_gb_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_1 = (uint16_t) g_gr_stencil.extract<0, 15>(); + uint16_t _g_gr_stencil_2 = (uint16_t) g_gr_stencil.extract<16, 31>(); + + uint16_t _455 = _g_gb_stencil_1 + _g_gb_stencil_2; + uint16_t _456 = (uint16_t)(1); + uint16_t _457 = _455 >> _456; + uint16_t _458 = _g_gr_stencil_1 + _g_gr_stencil_2; + uint16_t _459 = _458 >> _456; + uint16_t _460 = _g_gb_stencil_2 - _g_gb_stencil_1; + uint16_t _461 = _g_gb_stencil_1 - _g_gb_stencil_2; + bool _462 = _g_gb_stencil_1 < _g_gb_stencil_2; + uint16_t _463 = (uint16_t)(_462 ? _460 : _461); + uint16_t _464 = _463; + uint16_t _465 = _g_gr_stencil_2 - _g_gr_stencil_1; + uint16_t _466 = _g_gr_stencil_1 - _g_gr_stencil_2; + bool _467 = _g_gr_stencil_1 < _g_gr_stencil_2; + uint16_t _468 = (uint16_t)(_467 ? _465 : _466); + uint16_t _469 = _468; + bool _470 = _464 < _469; + uint16_t _471 = (uint16_t)(_470 ? _457 : _459); + return _471; +} + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + ((b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) - ((g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_1 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_2 = (uint16_t) b_b_stencil.extract<16, 31>(); + + uint16_t _g_b_stencil_1 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_2 = (uint16_t) g_b_stencil.extract<16, 31>(); + + uint16_t _g_gb_stencil_3 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _507 = _b_b_stencil_1 + _b_b_stencil_2; + uint16_t _508 = (uint16_t)(1); + uint16_t _509 = _507 >> _508; + uint16_t _510 = _g_gb_stencil_3 + _509; + uint16_t _511 = _g_b_stencil_1 + _g_b_stencil_2; + uint16_t _512 = _511 >> _508; + uint16_t _513 = _510 - _512; + return _513; +} + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + ((b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + b_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) - ((g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + g_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_3 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_4 = (uint16_t) b_b_stencil.extract<16, 31>(); + + uint16_t _g_b_stencil_3 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_4 = (uint16_t) g_b_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_3 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _536 = _b_b_stencil_3 + _b_b_stencil_4; + uint16_t _537 = (uint16_t)(1); + uint16_t _538 = _536 >> _537; + uint16_t _539 = _g_gr_stencil_3 + _538; + uint16_t _540 = _g_b_stencil_3 + _g_b_stencil_4; + uint16_t _541 = _540 >> _537; + uint16_t _542 = _539 - _541; + return _542; +} + +//store is: g_r.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y) = select((absd(g_gr.stencil(((g_r_s0_x + -1) + 2), (g_r_s0_y + 1)), g_gr.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1))) < absd(g_gb.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y), g_gb.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)))), ((g_gr.stencil(((g_r_s0_x + -1) + 2), (g_r_s0_y + 1)) + g_gr.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)))/(uint16)2), ((g_gb.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y) + g_gb.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_4 = (uint16_t) g_gb_stencil.extract<0, 15>(); + uint16_t _g_gb_stencil_5 = (uint16_t) g_gb_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_4 = (uint16_t) g_gr_stencil.extract<0, 15>(); + uint16_t _g_gr_stencil_5 = (uint16_t) g_gr_stencil.extract<16, 31>(); + + uint16_t _566 = _g_gr_stencil_4 + _g_gr_stencil_5; + uint16_t _567 = (uint16_t)(1); + uint16_t _568 = _566 >> _567; + uint16_t _569 = _g_gb_stencil_4 + _g_gb_stencil_5; + uint16_t _570 = _569 >> _567; + uint16_t _571 = _g_gr_stencil_5 - _g_gr_stencil_4; + uint16_t _572 = _g_gr_stencil_4 - _g_gr_stencil_5; + bool _573 = _g_gr_stencil_4 < _g_gr_stencil_5; + uint16_t _574 = (uint16_t)(_573 ? _571 : _572); + uint16_t _575 = _574; + uint16_t _576 = _g_gb_stencil_5 - _g_gb_stencil_4; + uint16_t _577 = _g_gb_stencil_4 - _g_gb_stencil_5; + bool _578 = _g_gb_stencil_4 < _g_gb_stencil_5; + uint16_t _579 = (uint16_t)(_578 ? _576 : _577); + uint16_t _580 = _579; + bool _581 = _575 < _580; + uint16_t _582 = (uint16_t)(_581 ? _568 : _570); + return _582; +} + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + b_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)) - ((g_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + g_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + b_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2)) - ((g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + g_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_5 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_6 = (uint16_t) b_b_stencil.extract<16, 31>(); + uint16_t _b_b_stencil_7 = (uint16_t) b_b_stencil.extract<32, 47>(); + uint16_t _b_b_stencil_8 = (uint16_t) b_b_stencil.extract<48, 63>(); + + uint16_t _g_b_stencil_5 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_6 = (uint16_t) g_b_stencil.extract<16, 31>(); + uint16_t _g_b_stencil_7 = (uint16_t) g_b_stencil.extract<32, 47>(); + uint16_t _g_b_stencil_8 = (uint16_t) g_b_stencil.extract<48, 63>(); + + uint16_t _g_r_stencil_1 = (uint16_t) g_r_stencil.extract<0, 15>(); + + uint16_t _618 = _b_b_stencil_5 + _b_b_stencil_6; + uint16_t _619 = (uint16_t)(1); + uint16_t _620 = _618 >> _619; + uint16_t _621 = _g_r_stencil_1 + _620; + uint16_t _622 = _g_b_stencil_5 + _g_b_stencil_6; + uint16_t _623 = _622 >> _619; + uint16_t _624 = _621 - _623; + uint16_t _625 = _b_b_stencil_7 + _b_b_stencil_8; + uint16_t _626 = _625 >> _619; + uint16_t _627 = _g_r_stencil_1 + _626; + uint16_t _628 = _g_b_stencil_7 + _g_b_stencil_8; + uint16_t _629 = _628 >> _619; + uint16_t _630 = _627 - _629; + uint16_t _631 = _b_b_stencil_6 - _b_b_stencil_5; + uint16_t _632 = _b_b_stencil_5 - _b_b_stencil_6; + bool _633 = _b_b_stencil_5 < _b_b_stencil_6; + uint16_t _634 = (uint16_t)(_633 ? _631 : _632); + uint16_t _635 = _634; + uint16_t _636 = _b_b_stencil_8 - _b_b_stencil_7; + uint16_t _637 = _b_b_stencil_7 - _b_b_stencil_8; + bool _638 = _b_b_stencil_7 < _b_b_stencil_8; + uint16_t _639 = (uint16_t)(_638 ? _636 : _637); + uint16_t _640 = _639; + bool _641 = _635 < _640; + uint16_t _642 = (uint16_t)(_641 ? _624 : _630); + return _642; +} + +//store is: r_r.stencil((r_r_s0_x_x*2), r_r_s0_y) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y*2) + 2)) +hw_uint<16> hcompute_r_r_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_7 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_7; +} + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), r_r_s0_y) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y*2) + 2)) +hw_uint<16> hcompute_r_r_stencil_1(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_8 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_8; +} + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil((r_b_s0_x + 1), r_b_s0_y) + r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x + 1), r_b_s0_y) + g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil(r_b_s0_x, r_b_s0_y) + r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil(r_b_s0_x, r_b_s0_y) + g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_9 = (uint16_t) g_b_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_2 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_3 = (uint16_t) g_r_stencil.extract<16, 31>(); + uint16_t _g_r_stencil_4 = (uint16_t) g_r_stencil.extract<32, 47>(); + uint16_t _g_r_stencil_5 = (uint16_t) g_r_stencil.extract<48, 63>(); + + uint16_t _r_r_stencil_1 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_2 = (uint16_t) r_r_stencil.extract<16, 31>(); + uint16_t _r_r_stencil_3 = (uint16_t) r_r_stencil.extract<32, 47>(); + uint16_t _r_r_stencil_4 = (uint16_t) r_r_stencil.extract<48, 63>(); + + uint16_t _710 = _r_r_stencil_1 + _r_r_stencil_2; + uint16_t _711 = (uint16_t)(1); + uint16_t _712 = _710 >> _711; + uint16_t _713 = _g_b_stencil_9 + _712; + uint16_t _714 = _g_r_stencil_2 + _g_r_stencil_3; + uint16_t _715 = _714 >> _711; + uint16_t _716 = _713 - _715; + uint16_t _717 = _r_r_stencil_3 + _r_r_stencil_4; + uint16_t _718 = _717 >> _711; + uint16_t _719 = _g_b_stencil_9 + _718; + uint16_t _720 = _g_r_stencil_4 + _g_r_stencil_5; + uint16_t _721 = _720 >> _711; + uint16_t _722 = _719 - _721; + uint16_t _723 = _r_r_stencil_2 - _r_r_stencil_1; + uint16_t _724 = _r_r_stencil_1 - _r_r_stencil_2; + bool _725 = _r_r_stencil_1 < _r_r_stencil_2; + uint16_t _726 = (uint16_t)(_725 ? _723 : _724); + uint16_t _727 = _726; + uint16_t _728 = _r_r_stencil_4 - _r_r_stencil_3; + uint16_t _729 = _r_r_stencil_3 - _r_r_stencil_4; + bool _730 = _r_r_stencil_3 < _r_r_stencil_4; + uint16_t _731 = (uint16_t)(_730 ? _728 : _729); + uint16_t _732 = _731; + bool _733 = _727 < _732; + uint16_t _734 = (uint16_t)(_733 ? _716 : _722); + return _734; +} + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + ((r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_6 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_6 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_7 = (uint16_t) g_r_stencil.extract<16, 31>(); + + uint16_t _r_r_stencil_5 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_6 = (uint16_t) r_r_stencil.extract<16, 31>(); + + uint16_t _789 = _r_r_stencil_5 + _r_r_stencil_6; + uint16_t _790 = (uint16_t)(1); + uint16_t _791 = _789 >> _790; + uint16_t _792 = _g_gb_stencil_6 + _791; + uint16_t _793 = _g_r_stencil_6 + _g_r_stencil_7; + uint16_t _794 = _793 >> _790; + uint16_t _795 = _792 - _794; + return _795; +} + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + ((r_r.stencil(r_gr_s0_x, r_gr_s0_y) + r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y))/(uint16)2)) - ((g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + g_r.stencil(r_gr_s0_x, r_gr_s0_y))/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_6 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_8 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_9 = (uint16_t) g_r_stencil.extract<16, 31>(); + + uint16_t _r_r_stencil_7 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_8 = (uint16_t) r_r_stencil.extract<16, 31>(); + + uint16_t _818 = _r_r_stencil_7 + _r_r_stencil_8; + uint16_t _819 = (uint16_t)(1); + uint16_t _820 = _818 >> _819; + uint16_t _821 = _g_gr_stencil_6 + _820; + uint16_t _822 = _g_r_stencil_8 + _g_r_stencil_9; + uint16_t _823 = _822 >> _819; + uint16_t _824 = _821 - _823; + return _824; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), demosaicked_1_s0_y, 0) = select(((demosaicked_1_s0_y % 2) == 0), r_gr.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2)), r_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2))) +hw_uint<16> hcompute_demosaicked_1_stencil(hw_uint<16>& r_b_stencil, hw_uint<16>& r_gr_stencil, const int _demosaicked_1_s0_y) { + uint16_t _r_b_stencil_1 = (uint16_t) r_b_stencil.extract<0, 15>(); + + uint16_t _r_gr_stencil_1 = (uint16_t) r_gr_stencil.extract<0, 15>(); + + int32_t _846 = _demosaicked_1_s0_y & 1; + bool _847 = _846 == 0; + uint16_t _848 = (uint16_t)(_847 ? _r_gr_stencil_1 : _r_b_stencil_1); + return _848; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), demosaicked_1_s0_y, 1) = select(((demosaicked_1_s0_y % 2) == 0), g_gr.stencil((demosaicked_1_s0_x_x + 1), ((demosaicked_1_s0_y/2) + 1)), g_b.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y/2) + 1))) +hw_uint<16> hcompute_demosaicked_1_stencil_1(hw_uint<16>& g_b_stencil, hw_uint<16>& g_gr_stencil, const int _demosaicked_1_s0_y) { + uint16_t _g_b_stencil_10 = (uint16_t) g_b_stencil.extract<0, 15>(); + + uint16_t _g_gr_stencil_7 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + int32_t _860 = _demosaicked_1_s0_y & 1; + bool _861 = _860 == 0; + uint16_t _862 = (uint16_t)(_861 ? _g_gr_stencil_7 : _g_b_stencil_10); + return _862; +} + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), demosaicked_1_s0_y, 2) = select(((demosaicked_1_s0_y % 2) == 0), b_gr.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2)), b_b.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y/2) + 1))) +hw_uint<16> hcompute_demosaicked_1_stencil_2(hw_uint<16>& b_b_stencil, hw_uint<16>& b_gr_stencil, const int _demosaicked_1_s0_y) { + uint16_t _b_b_stencil_9 = (uint16_t) b_b_stencil.extract<0, 15>(); + + uint16_t _b_gr_stencil_1 = (uint16_t) b_gr_stencil.extract<0, 15>(); + + int32_t _876 = _demosaicked_1_s0_y & 1; + bool _877 = _876 == 0; + uint16_t _878 = (uint16_t)(_877 ? _b_gr_stencil_1 : _b_b_stencil_9); + return _878; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), demosaicked_1_s0_y, 0) = select(((demosaicked_1_s0_y % 2) == 0), r_r.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y/2)), r_gb.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2))) +hw_uint<16> hcompute_demosaicked_1_stencil_3(hw_uint<16>& r_gb_stencil, hw_uint<16>& r_r_stencil, const int _demosaicked_1_s0_y) { + uint16_t _r_gb_stencil_1 = (uint16_t) r_gb_stencil.extract<0, 15>(); + + uint16_t _r_r_stencil_9 = (uint16_t) r_r_stencil.extract<0, 15>(); + + int32_t _891 = _demosaicked_1_s0_y & 1; + bool _892 = _891 == 0; + uint16_t _893 = (uint16_t)(_892 ? _r_r_stencil_9 : _r_gb_stencil_1); + return _893; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), demosaicked_1_s0_y, 1) = select(((demosaicked_1_s0_y % 2) == 0), g_r.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y/2)), g_gb.stencil((demosaicked_1_s0_x_x + 1), ((demosaicked_1_s0_y/2) + 1))) +hw_uint<16> hcompute_demosaicked_1_stencil_4(hw_uint<16>& g_gb_stencil, hw_uint<16>& g_r_stencil, const int _demosaicked_1_s0_y) { + uint16_t _g_gb_stencil_7 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_10 = (uint16_t) g_r_stencil.extract<0, 15>(); + + int32_t _907 = _demosaicked_1_s0_y & 1; + bool _908 = _907 == 0; + uint16_t _909 = (uint16_t)(_908 ? _g_r_stencil_10 : _g_gb_stencil_7); + return _909; +} + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), demosaicked_1_s0_y, 2) = select(((demosaicked_1_s0_y % 2) == 0), b_r.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2)), b_gb.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2))) +hw_uint<16> hcompute_demosaicked_1_stencil_5(hw_uint<16>& b_gb_stencil, hw_uint<16>& b_r_stencil, const int _demosaicked_1_s0_y) { + uint16_t _b_gb_stencil_1 = (uint16_t) b_gb_stencil.extract<0, 15>(); + + uint16_t _b_r_stencil_1 = (uint16_t) b_r_stencil.extract<0, 15>(); + + int32_t _924 = _demosaicked_1_s0_y & 1; + bool _925 = _924 == 0; + uint16_t _926 = (uint16_t)(_925 ? _b_r_stencil_1 : _b_gb_stencil_1); + return _926; +} + +//store is: corrected.stencil((corrected_s0_x_x*2), corrected_s0_y, 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), corrected_s0_y, 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), corrected_s0_y, 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), corrected_s0_y, 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_1 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_2 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_3 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _939 = (uint16_t)(10000); + uint16_t _940 = min(_demosaicked_1_stencil_1, _939); + int32_t _941 = (int32_t)(_940); + int32_t _942 = _941 * 549; + int32_t _943 = _942 >> 8; + int16_t _944 = (int16_t)(_943); + uint16_t _945 = min(_demosaicked_1_stencil_2, _939); + int32_t _946 = (int32_t)(_945); + int32_t _947 = _946 * -103; + int32_t _948 = _947 >> 8; + int16_t _949 = (int16_t)(_948); + int16_t _950 = _944 + _949; + uint16_t _951 = min(_demosaicked_1_stencil_3, _939); + int32_t _952 = (int32_t)(_951); + int32_t _953 = _952 * 7; + int32_t _954 = _953 >> 8; + int16_t _955 = (int16_t)(_954); + int16_t _956 = _950 + _955; + int16_t _957 = (int16_t)(-40); + int16_t _958 = _956 + _957; + return _958; +} + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_1(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_4 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_5 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_6 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _997 = (uint16_t)(10000); + uint16_t _998 = min(_demosaicked_1_stencil_4, _997); + int32_t _999 = (int32_t)(_998); + int32_t _1000 = _999 * 549; + int32_t _1001 = _1000 >> 8; + int16_t _1002 = (int16_t)(_1001); + uint16_t _1003 = min(_demosaicked_1_stencil_5, _997); + int32_t _1004 = (int32_t)(_1003); + int32_t _1005 = _1004 * -103; + int32_t _1006 = _1005 >> 8; + int16_t _1007 = (int16_t)(_1006); + int16_t _1008 = _1002 + _1007; + uint16_t _1009 = min(_demosaicked_1_stencil_6, _997); + int32_t _1010 = (int32_t)(_1009); + int32_t _1011 = _1010 * 7; + int32_t _1012 = _1011 >> 8; + int16_t _1013 = (int16_t)(_1012); + int16_t _1014 = _1008 + _1013; + int16_t _1015 = (int16_t)(-40); + int16_t _1016 = _1014 + _1015; + return _1016; +} + +//store is: corrected.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_2(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_7 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_8 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_9 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1056 = (uint16_t)(10000); + uint16_t _1057 = min(_demosaicked_1_stencil_7, _1056); + int32_t _1058 = (int32_t)(_1057); + int32_t _1059 = _1058 * -96; + int32_t _1060 = _1059 >> 8; + int16_t _1061 = (int16_t)(_1060); + uint16_t _1062 = min(_demosaicked_1_stencil_8, _1056); + int32_t _1063 = (int32_t)(_1062); + int32_t _1064 = _1063 * 373; + int32_t _1065 = _1064 >> 8; + int16_t _1066 = (int16_t)(_1065); + int16_t _1067 = _1061 + _1066; + uint16_t _1068 = min(_demosaicked_1_stencil_9, _1056); + int32_t _1069 = (int32_t)(_1068); + int32_t _1070 = _1069 * 62; + int32_t _1071 = _1070 >> 8; + int16_t _1072 = (int16_t)(_1071); + int16_t _1073 = _1067 + _1072; + int16_t _1074 = (int16_t)(-29); + int16_t _1075 = _1073 + _1074; + return _1075; +} + +//store is: corrected.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_3(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_10 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_11 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_12 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1114 = (uint16_t)(10000); + uint16_t _1115 = min(_demosaicked_1_stencil_10, _1114); + int32_t _1116 = (int32_t)(_1115); + int32_t _1117 = _1116 * -96; + int32_t _1118 = _1117 >> 8; + int16_t _1119 = (int16_t)(_1118); + uint16_t _1120 = min(_demosaicked_1_stencil_11, _1114); + int32_t _1121 = (int32_t)(_1120); + int32_t _1122 = _1121 * 373; + int32_t _1123 = _1122 >> 8; + int16_t _1124 = (int16_t)(_1123); + int16_t _1125 = _1119 + _1124; + uint16_t _1126 = min(_demosaicked_1_stencil_12, _1114); + int32_t _1127 = (int32_t)(_1126); + int32_t _1128 = _1127 * 62; + int32_t _1129 = _1128 >> 8; + int16_t _1130 = (int16_t)(_1129); + int16_t _1131 = _1125 + _1130; + int16_t _1132 = (int16_t)(-29); + int16_t _1133 = _1131 + _1132; + return _1133; +} + +//store is: corrected.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_4(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_13 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_14 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_15 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1173 = (uint16_t)(10000); + uint16_t _1174 = min(_demosaicked_1_stencil_13, _1173); + int32_t _1175 = (int32_t)(_1174); + int32_t _1176 = _1175 * -31; + int32_t _1177 = _1176 >> 8; + int16_t _1178 = (int16_t)(_1177); + uint16_t _1179 = min(_demosaicked_1_stencil_14, _1173); + int32_t _1180 = (int32_t)(_1179); + int32_t _1181 = _1180 * -261; + int32_t _1182 = _1181 >> 8; + int16_t _1183 = (int16_t)(_1182); + int16_t _1184 = _1178 + _1183; + uint16_t _1185 = min(_demosaicked_1_stencil_15, _1173); + int32_t _1186 = (int32_t)(_1185); + int32_t _1187 = _1186 * 883; + int32_t _1188 = _1187 >> 8; + int16_t _1189 = (int16_t)(_1188); + int16_t _1190 = _1184 + _1189; + int16_t _1191 = (int16_t)(-22); + int16_t _1192 = _1190 + _1191; + return _1192; +} + +//store is: corrected.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_5(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_16 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_17 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_18 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1231 = (uint16_t)(10000); + uint16_t _1232 = min(_demosaicked_1_stencil_16, _1231); + int32_t _1233 = (int32_t)(_1232); + int32_t _1234 = _1233 * -31; + int32_t _1235 = _1234 >> 8; + int16_t _1236 = (int16_t)(_1235); + uint16_t _1237 = min(_demosaicked_1_stencil_17, _1231); + int32_t _1238 = (int32_t)(_1237); + int32_t _1239 = _1238 * -261; + int32_t _1240 = _1239 >> 8; + int16_t _1241 = (int16_t)(_1240); + int16_t _1242 = _1236 + _1241; + uint16_t _1243 = min(_demosaicked_1_stencil_18, _1231); + int32_t _1244 = (int32_t)(_1243); + int32_t _1245 = _1244 * 883; + int32_t _1246 = _1245 >> 8; + int16_t _1247 = (int16_t)(_1246); + int16_t _1248 = _1242 + _1247; + int16_t _1249 = (int16_t)(-22); + int16_t _1250 = _1248 + _1249; + return _1250; +} + +//store is: curved.stencil((curved_s0_x_x*2), curved_s0_y, 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), curved_s0_y, 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_1 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _2314 = (uint16_t)(0); + _curvea0[0] = _2314; + uint16_t _2315 = (uint16_t)(4); + _curvea0[1] = _2315; + uint16_t _2316 = (uint16_t)(7); + _curvea0[2] = _2316; + uint16_t _2317 = (uint16_t)(8); + _curvea0[3] = _2317; + uint16_t _2318 = (uint16_t)(10); + _curvea0[4] = _2318; + uint16_t _2319 = (uint16_t)(11); + _curvea0[5] = _2319; + uint16_t _2320 = (uint16_t)(12); + _curvea0[6] = _2320; + uint16_t _2321 = (uint16_t)(13); + _curvea0[7] = _2321; + uint16_t _2322 = (uint16_t)(14); + _curvea0[8] = _2322; + uint16_t _2323 = (uint16_t)(15); + _curvea0[9] = _2323; + uint16_t _2324 = (uint16_t)(16); + _curvea0[10] = _2324; + uint16_t _2325 = (uint16_t)(17); + _curvea0[11] = _2325; + uint16_t _2326 = (uint16_t)(18); + _curvea0[12] = _2326; + uint16_t _2327 = (uint16_t)(19); + _curvea0[13] = _2327; + uint16_t _2328 = (uint16_t)(20); + _curvea0[14] = _2328; + uint16_t _2329 = (uint16_t)(21); + _curvea0[15] = _2329; + uint16_t _2330 = (uint16_t)(22); + _curvea0[16] = _2330; + uint16_t _2331 = (uint16_t)(22); + _curvea0[17] = _2331; + uint16_t _2332 = (uint16_t)(23); + _curvea0[18] = _2332; + uint16_t _2333 = (uint16_t)(24); + _curvea0[19] = _2333; + uint16_t _2334 = (uint16_t)(25); + _curvea0[20] = _2334; + uint16_t _2335 = (uint16_t)(25); + _curvea0[21] = _2335; + uint16_t _2336 = (uint16_t)(26); + _curvea0[22] = _2336; + uint16_t _2337 = (uint16_t)(27); + _curvea0[23] = _2337; + uint16_t _2338 = (uint16_t)(27); + _curvea0[24] = _2338; + uint16_t _2339 = (uint16_t)(28); + _curvea0[25] = _2339; + uint16_t _2340 = (uint16_t)(29); + _curvea0[26] = _2340; + uint16_t _2341 = (uint16_t)(29); + _curvea0[27] = _2341; + uint16_t _2342 = (uint16_t)(30); + _curvea0[28] = _2342; + uint16_t _2343 = (uint16_t)(31); + _curvea0[29] = _2343; + uint16_t _2344 = (uint16_t)(31); + _curvea0[30] = _2344; + uint16_t _2345 = (uint16_t)(32); + _curvea0[31] = _2345; + uint16_t _2346 = (uint16_t)(33); + _curvea0[32] = _2346; + uint16_t _2347 = (uint16_t)(33); + _curvea0[33] = _2347; + uint16_t _2348 = (uint16_t)(34); + _curvea0[34] = _2348; + uint16_t _2349 = (uint16_t)(34); + _curvea0[35] = _2349; + uint16_t _2350 = (uint16_t)(35); + _curvea0[36] = _2350; + uint16_t _2351 = (uint16_t)(36); + _curvea0[37] = _2351; + uint16_t _2352 = (uint16_t)(36); + _curvea0[38] = _2352; + uint16_t _2353 = (uint16_t)(37); + _curvea0[39] = _2353; + uint16_t _2354 = (uint16_t)(37); + _curvea0[40] = _2354; + uint16_t _2355 = (uint16_t)(38); + _curvea0[41] = _2355; + uint16_t _2356 = (uint16_t)(39); + _curvea0[42] = _2356; + uint16_t _2357 = (uint16_t)(39); + _curvea0[43] = _2357; + uint16_t _2358 = (uint16_t)(40); + _curvea0[44] = _2358; + uint16_t _2359 = (uint16_t)(40); + _curvea0[45] = _2359; + uint16_t _2360 = (uint16_t)(41); + _curvea0[46] = _2360; + uint16_t _2361 = (uint16_t)(41); + _curvea0[47] = _2361; + uint16_t _2362 = (uint16_t)(42); + _curvea0[48] = _2362; + uint16_t _2363 = (uint16_t)(42); + _curvea0[49] = _2363; + uint16_t _2364 = (uint16_t)(43); + _curvea0[50] = _2364; + uint16_t _2365 = (uint16_t)(44); + _curvea0[51] = _2365; + uint16_t _2366 = (uint16_t)(44); + _curvea0[52] = _2366; + uint16_t _2367 = (uint16_t)(45); + _curvea0[53] = _2367; + uint16_t _2368 = (uint16_t)(45); + _curvea0[54] = _2368; + uint16_t _2369 = (uint16_t)(46); + _curvea0[55] = _2369; + uint16_t _2370 = (uint16_t)(46); + _curvea0[56] = _2370; + uint16_t _2371 = (uint16_t)(47); + _curvea0[57] = _2371; + uint16_t _2372 = (uint16_t)(47); + _curvea0[58] = _2372; + uint16_t _2373 = (uint16_t)(48); + _curvea0[59] = _2373; + uint16_t _2374 = (uint16_t)(48); + _curvea0[60] = _2374; + uint16_t _2375 = (uint16_t)(49); + _curvea0[61] = _2375; + uint16_t _2376 = (uint16_t)(49); + _curvea0[62] = _2376; + uint16_t _2377 = (uint16_t)(50); + _curvea0[63] = _2377; + uint16_t _2378 = (uint16_t)(50); + _curvea0[64] = _2378; + uint16_t _2379 = (uint16_t)(51); + _curvea0[65] = _2379; + uint16_t _2380 = (uint16_t)(51); + _curvea0[66] = _2380; + uint16_t _2381 = (uint16_t)(52); + _curvea0[67] = _2381; + uint16_t _2382 = (uint16_t)(52); + _curvea0[68] = _2382; + uint16_t _2383 = (uint16_t)(53); + _curvea0[69] = _2383; + uint16_t _2384 = (uint16_t)(53); + _curvea0[70] = _2384; + uint16_t _2385 = (uint16_t)(54); + _curvea0[71] = _2385; + uint16_t _2386 = (uint16_t)(54); + _curvea0[72] = _2386; + uint16_t _2387 = (uint16_t)(55); + _curvea0[73] = _2387; + uint16_t _2388 = (uint16_t)(55); + _curvea0[74] = _2388; + uint16_t _2389 = (uint16_t)(56); + _curvea0[75] = _2389; + uint16_t _2390 = (uint16_t)(56); + _curvea0[76] = _2390; + uint16_t _2391 = (uint16_t)(57); + _curvea0[77] = _2391; + uint16_t _2392 = (uint16_t)(57); + _curvea0[78] = _2392; + uint16_t _2393 = (uint16_t)(58); + _curvea0[79] = _2393; + uint16_t _2394 = (uint16_t)(58); + _curvea0[80] = _2394; + uint16_t _2395 = (uint16_t)(58); + _curvea0[81] = _2395; + uint16_t _2396 = (uint16_t)(59); + _curvea0[82] = _2396; + uint16_t _2397 = (uint16_t)(59); + _curvea0[83] = _2397; + uint16_t _2398 = (uint16_t)(60); + _curvea0[84] = _2398; + uint16_t _2399 = (uint16_t)(60); + _curvea0[85] = _2399; + uint16_t _2400 = (uint16_t)(61); + _curvea0[86] = _2400; + uint16_t _2401 = (uint16_t)(61); + _curvea0[87] = _2401; + uint16_t _2402 = (uint16_t)(62); + _curvea0[88] = _2402; + uint16_t _2403 = (uint16_t)(62); + _curvea0[89] = _2403; + uint16_t _2404 = (uint16_t)(63); + _curvea0[90] = _2404; + uint16_t _2405 = (uint16_t)(63); + _curvea0[91] = _2405; + uint16_t _2406 = (uint16_t)(64); + _curvea0[92] = _2406; + uint16_t _2407 = (uint16_t)(64); + _curvea0[93] = _2407; + uint16_t _2408 = (uint16_t)(64); + _curvea0[94] = _2408; + uint16_t _2409 = (uint16_t)(65); + _curvea0[95] = _2409; + uint16_t _2410 = (uint16_t)(65); + _curvea0[96] = _2410; + uint16_t _2411 = (uint16_t)(66); + _curvea0[97] = _2411; + uint16_t _2412 = (uint16_t)(66); + _curvea0[98] = _2412; + uint16_t _2413 = (uint16_t)(67); + _curvea0[99] = _2413; + uint16_t _2414 = (uint16_t)(67); + _curvea0[100] = _2414; + uint16_t _2415 = (uint16_t)(68); + _curvea0[101] = _2415; + uint16_t _2416 = (uint16_t)(68); + _curvea0[102] = _2416; + uint16_t _2417 = (uint16_t)(68); + _curvea0[103] = _2417; + uint16_t _2418 = (uint16_t)(69); + _curvea0[104] = _2418; + uint16_t _2419 = (uint16_t)(69); + _curvea0[105] = _2419; + uint16_t _2420 = (uint16_t)(70); + _curvea0[106] = _2420; + uint16_t _2421 = (uint16_t)(70); + _curvea0[107] = _2421; + uint16_t _2422 = (uint16_t)(71); + _curvea0[108] = _2422; + uint16_t _2423 = (uint16_t)(71); + _curvea0[109] = _2423; + uint16_t _2424 = (uint16_t)(71); + _curvea0[110] = _2424; + uint16_t _2425 = (uint16_t)(72); + _curvea0[111] = _2425; + uint16_t _2426 = (uint16_t)(72); + _curvea0[112] = _2426; + uint16_t _2427 = (uint16_t)(73); + _curvea0[113] = _2427; + uint16_t _2428 = (uint16_t)(73); + _curvea0[114] = _2428; + uint16_t _2429 = (uint16_t)(74); + _curvea0[115] = _2429; + uint16_t _2430 = (uint16_t)(74); + _curvea0[116] = _2430; + uint16_t _2431 = (uint16_t)(74); + _curvea0[117] = _2431; + uint16_t _2432 = (uint16_t)(75); + _curvea0[118] = _2432; + uint16_t _2433 = (uint16_t)(75); + _curvea0[119] = _2433; + uint16_t _2434 = (uint16_t)(76); + _curvea0[120] = _2434; + uint16_t _2435 = (uint16_t)(76); + _curvea0[121] = _2435; + uint16_t _2436 = (uint16_t)(77); + _curvea0[122] = _2436; + uint16_t _2437 = (uint16_t)(77); + _curvea0[123] = _2437; + uint16_t _2438 = (uint16_t)(77); + _curvea0[124] = _2438; + uint16_t _2439 = (uint16_t)(78); + _curvea0[125] = _2439; + uint16_t _2440 = (uint16_t)(78); + _curvea0[126] = _2440; + uint16_t _2441 = (uint16_t)(79); + _curvea0[127] = _2441; + uint16_t _2442 = (uint16_t)(79); + _curvea0[128] = _2442; + uint16_t _2443 = (uint16_t)(79); + _curvea0[129] = _2443; + uint16_t _2444 = (uint16_t)(80); + _curvea0[130] = _2444; + uint16_t _2445 = (uint16_t)(80); + _curvea0[131] = _2445; + uint16_t _2446 = (uint16_t)(81); + _curvea0[132] = _2446; + uint16_t _2447 = (uint16_t)(81); + _curvea0[133] = _2447; + uint16_t _2448 = (uint16_t)(82); + _curvea0[134] = _2448; + uint16_t _2449 = (uint16_t)(82); + _curvea0[135] = _2449; + uint16_t _2450 = (uint16_t)(82); + _curvea0[136] = _2450; + uint16_t _2451 = (uint16_t)(83); + _curvea0[137] = _2451; + uint16_t _2452 = (uint16_t)(83); + _curvea0[138] = _2452; + uint16_t _2453 = (uint16_t)(84); + _curvea0[139] = _2453; + uint16_t _2454 = (uint16_t)(84); + _curvea0[140] = _2454; + uint16_t _2455 = (uint16_t)(84); + _curvea0[141] = _2455; + uint16_t _2456 = (uint16_t)(85); + _curvea0[142] = _2456; + uint16_t _2457 = (uint16_t)(85); + _curvea0[143] = _2457; + uint16_t _2458 = (uint16_t)(86); + _curvea0[144] = _2458; + uint16_t _2459 = (uint16_t)(86); + _curvea0[145] = _2459; + uint16_t _2460 = (uint16_t)(86); + _curvea0[146] = _2460; + uint16_t _2461 = (uint16_t)(87); + _curvea0[147] = _2461; + uint16_t _2462 = (uint16_t)(87); + _curvea0[148] = _2462; + uint16_t _2463 = (uint16_t)(88); + _curvea0[149] = _2463; + uint16_t _2464 = (uint16_t)(88); + _curvea0[150] = _2464; + uint16_t _2465 = (uint16_t)(88); + _curvea0[151] = _2465; + uint16_t _2466 = (uint16_t)(89); + _curvea0[152] = _2466; + uint16_t _2467 = (uint16_t)(89); + _curvea0[153] = _2467; + uint16_t _2468 = (uint16_t)(90); + _curvea0[154] = _2468; + uint16_t _2469 = (uint16_t)(90); + _curvea0[155] = _2469; + uint16_t _2470 = (uint16_t)(90); + _curvea0[156] = _2470; + uint16_t _2471 = (uint16_t)(91); + _curvea0[157] = _2471; + uint16_t _2472 = (uint16_t)(91); + _curvea0[158] = _2472; + uint16_t _2473 = (uint16_t)(92); + _curvea0[159] = _2473; + uint16_t _2474 = (uint16_t)(92); + _curvea0[160] = _2474; + uint16_t _2475 = (uint16_t)(92); + _curvea0[161] = _2475; + uint16_t _2476 = (uint16_t)(93); + _curvea0[162] = _2476; + uint16_t _2477 = (uint16_t)(93); + _curvea0[163] = _2477; + uint16_t _2478 = (uint16_t)(93); + _curvea0[164] = _2478; + uint16_t _2479 = (uint16_t)(94); + _curvea0[165] = _2479; + uint16_t _2480 = (uint16_t)(94); + _curvea0[166] = _2480; + uint16_t _2481 = (uint16_t)(95); + _curvea0[167] = _2481; + uint16_t _2482 = (uint16_t)(95); + _curvea0[168] = _2482; + uint16_t _2483 = (uint16_t)(95); + _curvea0[169] = _2483; + uint16_t _2484 = (uint16_t)(96); + _curvea0[170] = _2484; + uint16_t _2485 = (uint16_t)(96); + _curvea0[171] = _2485; + uint16_t _2486 = (uint16_t)(97); + _curvea0[172] = _2486; + uint16_t _2487 = (uint16_t)(97); + _curvea0[173] = _2487; + uint16_t _2488 = (uint16_t)(97); + _curvea0[174] = _2488; + uint16_t _2489 = (uint16_t)(98); + _curvea0[175] = _2489; + uint16_t _2490 = (uint16_t)(98); + _curvea0[176] = _2490; + uint16_t _2491 = (uint16_t)(99); + _curvea0[177] = _2491; + uint16_t _2492 = (uint16_t)(99); + _curvea0[178] = _2492; + uint16_t _2493 = (uint16_t)(99); + _curvea0[179] = _2493; + uint16_t _2494 = (uint16_t)(100); + _curvea0[180] = _2494; + uint16_t _2495 = (uint16_t)(100); + _curvea0[181] = _2495; + uint16_t _2496 = (uint16_t)(100); + _curvea0[182] = _2496; + uint16_t _2497 = (uint16_t)(101); + _curvea0[183] = _2497; + uint16_t _2498 = (uint16_t)(101); + _curvea0[184] = _2498; + uint16_t _2499 = (uint16_t)(102); + _curvea0[185] = _2499; + uint16_t _2500 = (uint16_t)(102); + _curvea0[186] = _2500; + uint16_t _2501 = (uint16_t)(102); + _curvea0[187] = _2501; + uint16_t _2502 = (uint16_t)(103); + _curvea0[188] = _2502; + uint16_t _2503 = (uint16_t)(103); + _curvea0[189] = _2503; + uint16_t _2504 = (uint16_t)(103); + _curvea0[190] = _2504; + uint16_t _2505 = (uint16_t)(104); + _curvea0[191] = _2505; + uint16_t _2506 = (uint16_t)(104); + _curvea0[192] = _2506; + uint16_t _2507 = (uint16_t)(105); + _curvea0[193] = _2507; + uint16_t _2508 = (uint16_t)(105); + _curvea0[194] = _2508; + uint16_t _2509 = (uint16_t)(105); + _curvea0[195] = _2509; + uint16_t _2510 = (uint16_t)(106); + _curvea0[196] = _2510; + uint16_t _2511 = (uint16_t)(106); + _curvea0[197] = _2511; + uint16_t _2512 = (uint16_t)(106); + _curvea0[198] = _2512; + uint16_t _2513 = (uint16_t)(107); + _curvea0[199] = _2513; + uint16_t _2514 = (uint16_t)(107); + _curvea0[200] = _2514; + uint16_t _2515 = (uint16_t)(108); + _curvea0[201] = _2515; + uint16_t _2516 = (uint16_t)(108); + _curvea0[202] = _2516; + uint16_t _2517 = (uint16_t)(108); + _curvea0[203] = _2517; + uint16_t _2518 = (uint16_t)(109); + _curvea0[204] = _2518; + uint16_t _2519 = (uint16_t)(109); + _curvea0[205] = _2519; + uint16_t _2520 = (uint16_t)(109); + _curvea0[206] = _2520; + uint16_t _2521 = (uint16_t)(110); + _curvea0[207] = _2521; + uint16_t _2522 = (uint16_t)(110); + _curvea0[208] = _2522; + uint16_t _2523 = (uint16_t)(111); + _curvea0[209] = _2523; + uint16_t _2524 = (uint16_t)(111); + _curvea0[210] = _2524; + uint16_t _2525 = (uint16_t)(111); + _curvea0[211] = _2525; + uint16_t _2526 = (uint16_t)(112); + _curvea0[212] = _2526; + uint16_t _2527 = (uint16_t)(112); + _curvea0[213] = _2527; + uint16_t _2528 = (uint16_t)(112); + _curvea0[214] = _2528; + uint16_t _2529 = (uint16_t)(113); + _curvea0[215] = _2529; + uint16_t _2530 = (uint16_t)(113); + _curvea0[216] = _2530; + uint16_t _2531 = (uint16_t)(113); + _curvea0[217] = _2531; + uint16_t _2532 = (uint16_t)(114); + _curvea0[218] = _2532; + uint16_t _2533 = (uint16_t)(114); + _curvea0[219] = _2533; + uint16_t _2534 = (uint16_t)(115); + _curvea0[220] = _2534; + uint16_t _2535 = (uint16_t)(115); + _curvea0[221] = _2535; + uint16_t _2536 = (uint16_t)(115); + _curvea0[222] = _2536; + uint16_t _2537 = (uint16_t)(116); + _curvea0[223] = _2537; + uint16_t _2538 = (uint16_t)(116); + _curvea0[224] = _2538; + uint16_t _2539 = (uint16_t)(116); + _curvea0[225] = _2539; + uint16_t _2540 = (uint16_t)(117); + _curvea0[226] = _2540; + uint16_t _2541 = (uint16_t)(117); + _curvea0[227] = _2541; + uint16_t _2542 = (uint16_t)(117); + _curvea0[228] = _2542; + uint16_t _2543 = (uint16_t)(118); + _curvea0[229] = _2543; + uint16_t _2544 = (uint16_t)(118); + _curvea0[230] = _2544; + uint16_t _2545 = (uint16_t)(119); + _curvea0[231] = _2545; + uint16_t _2546 = (uint16_t)(119); + _curvea0[232] = _2546; + uint16_t _2547 = (uint16_t)(119); + _curvea0[233] = _2547; + uint16_t _2548 = (uint16_t)(120); + _curvea0[234] = _2548; + uint16_t _2549 = (uint16_t)(120); + _curvea0[235] = _2549; + uint16_t _2550 = (uint16_t)(120); + _curvea0[236] = _2550; + uint16_t _2551 = (uint16_t)(121); + _curvea0[237] = _2551; + uint16_t _2552 = (uint16_t)(121); + _curvea0[238] = _2552; + uint16_t _2553 = (uint16_t)(121); + _curvea0[239] = _2553; + uint16_t _2554 = (uint16_t)(122); + _curvea0[240] = _2554; + uint16_t _2555 = (uint16_t)(122); + _curvea0[241] = _2555; + uint16_t _2556 = (uint16_t)(123); + _curvea0[242] = _2556; + uint16_t _2557 = (uint16_t)(123); + _curvea0[243] = _2557; + uint16_t _2558 = (uint16_t)(123); + _curvea0[244] = _2558; + uint16_t _2559 = (uint16_t)(124); + _curvea0[245] = _2559; + uint16_t _2560 = (uint16_t)(124); + _curvea0[246] = _2560; + uint16_t _2561 = (uint16_t)(124); + _curvea0[247] = _2561; + uint16_t _2562 = (uint16_t)(125); + _curvea0[248] = _2562; + uint16_t _2563 = (uint16_t)(125); + _curvea0[249] = _2563; + uint16_t _2564 = (uint16_t)(125); + _curvea0[250] = _2564; + uint16_t _2565 = (uint16_t)(126); + _curvea0[251] = _2565; + uint16_t _2566 = (uint16_t)(126); + _curvea0[252] = _2566; + uint16_t _2567 = (uint16_t)(126); + _curvea0[253] = _2567; + uint16_t _2568 = (uint16_t)(127); + _curvea0[254] = _2568; + uint16_t _2569 = (uint16_t)(127); + _curvea0[255] = _2569; + uint16_t _2570 = (uint16_t)(128); + _curvea0[256] = _2570; + uint16_t _2571 = (uint16_t)(128); + _curvea0[257] = _2571; + uint16_t _2572 = (uint16_t)(128); + _curvea0[258] = _2572; + uint16_t _2573 = (uint16_t)(129); + _curvea0[259] = _2573; + uint16_t _2574 = (uint16_t)(129); + _curvea0[260] = _2574; + uint16_t _2575 = (uint16_t)(129); + _curvea0[261] = _2575; + uint16_t _2576 = (uint16_t)(130); + _curvea0[262] = _2576; + uint16_t _2577 = (uint16_t)(130); + _curvea0[263] = _2577; + uint16_t _2578 = (uint16_t)(130); + _curvea0[264] = _2578; + uint16_t _2579 = (uint16_t)(131); + _curvea0[265] = _2579; + uint16_t _2580 = (uint16_t)(131); + _curvea0[266] = _2580; + uint16_t _2581 = (uint16_t)(131); + _curvea0[267] = _2581; + uint16_t _2582 = (uint16_t)(132); + _curvea0[268] = _2582; + uint16_t _2583 = (uint16_t)(132); + _curvea0[269] = _2583; + uint16_t _2584 = (uint16_t)(132); + _curvea0[270] = _2584; + uint16_t _2585 = (uint16_t)(133); + _curvea0[271] = _2585; + uint16_t _2586 = (uint16_t)(133); + _curvea0[272] = _2586; + uint16_t _2587 = (uint16_t)(133); + _curvea0[273] = _2587; + uint16_t _2588 = (uint16_t)(134); + _curvea0[274] = _2588; + uint16_t _2589 = (uint16_t)(134); + _curvea0[275] = _2589; + uint16_t _2590 = (uint16_t)(134); + _curvea0[276] = _2590; + uint16_t _2591 = (uint16_t)(135); + _curvea0[277] = _2591; + uint16_t _2592 = (uint16_t)(135); + _curvea0[278] = _2592; + uint16_t _2593 = (uint16_t)(135); + _curvea0[279] = _2593; + uint16_t _2594 = (uint16_t)(136); + _curvea0[280] = _2594; + uint16_t _2595 = (uint16_t)(136); + _curvea0[281] = _2595; + uint16_t _2596 = (uint16_t)(136); + _curvea0[282] = _2596; + uint16_t _2597 = (uint16_t)(137); + _curvea0[283] = _2597; + uint16_t _2598 = (uint16_t)(137); + _curvea0[284] = _2598; + uint16_t _2599 = (uint16_t)(137); + _curvea0[285] = _2599; + uint16_t _2600 = (uint16_t)(138); + _curvea0[286] = _2600; + uint16_t _2601 = (uint16_t)(138); + _curvea0[287] = _2601; + uint16_t _2602 = (uint16_t)(138); + _curvea0[288] = _2602; + uint16_t _2603 = (uint16_t)(139); + _curvea0[289] = _2603; + uint16_t _2604 = (uint16_t)(139); + _curvea0[290] = _2604; + uint16_t _2605 = (uint16_t)(139); + _curvea0[291] = _2605; + uint16_t _2606 = (uint16_t)(140); + _curvea0[292] = _2606; + uint16_t _2607 = (uint16_t)(140); + _curvea0[293] = _2607; + uint16_t _2608 = (uint16_t)(140); + _curvea0[294] = _2608; + uint16_t _2609 = (uint16_t)(141); + _curvea0[295] = _2609; + uint16_t _2610 = (uint16_t)(141); + _curvea0[296] = _2610; + uint16_t _2611 = (uint16_t)(141); + _curvea0[297] = _2611; + uint16_t _2612 = (uint16_t)(141); + _curvea0[298] = _2612; + uint16_t _2613 = (uint16_t)(142); + _curvea0[299] = _2613; + uint16_t _2614 = (uint16_t)(142); + _curvea0[300] = _2614; + uint16_t _2615 = (uint16_t)(142); + _curvea0[301] = _2615; + uint16_t _2616 = (uint16_t)(143); + _curvea0[302] = _2616; + uint16_t _2617 = (uint16_t)(143); + _curvea0[303] = _2617; + uint16_t _2618 = (uint16_t)(143); + _curvea0[304] = _2618; + uint16_t _2619 = (uint16_t)(144); + _curvea0[305] = _2619; + uint16_t _2620 = (uint16_t)(144); + _curvea0[306] = _2620; + uint16_t _2621 = (uint16_t)(144); + _curvea0[307] = _2621; + uint16_t _2622 = (uint16_t)(145); + _curvea0[308] = _2622; + uint16_t _2623 = (uint16_t)(145); + _curvea0[309] = _2623; + uint16_t _2624 = (uint16_t)(145); + _curvea0[310] = _2624; + uint16_t _2625 = (uint16_t)(145); + _curvea0[311] = _2625; + uint16_t _2626 = (uint16_t)(146); + _curvea0[312] = _2626; + uint16_t _2627 = (uint16_t)(146); + _curvea0[313] = _2627; + uint16_t _2628 = (uint16_t)(146); + _curvea0[314] = _2628; + uint16_t _2629 = (uint16_t)(147); + _curvea0[315] = _2629; + uint16_t _2630 = (uint16_t)(147); + _curvea0[316] = _2630; + uint16_t _2631 = (uint16_t)(147); + _curvea0[317] = _2631; + uint16_t _2632 = (uint16_t)(148); + _curvea0[318] = _2632; + uint16_t _2633 = (uint16_t)(148); + _curvea0[319] = _2633; + uint16_t _2634 = (uint16_t)(148); + _curvea0[320] = _2634; + uint16_t _2635 = (uint16_t)(148); + _curvea0[321] = _2635; + uint16_t _2636 = (uint16_t)(149); + _curvea0[322] = _2636; + uint16_t _2637 = (uint16_t)(149); + _curvea0[323] = _2637; + uint16_t _2638 = (uint16_t)(149); + _curvea0[324] = _2638; + uint16_t _2639 = (uint16_t)(150); + _curvea0[325] = _2639; + uint16_t _2640 = (uint16_t)(150); + _curvea0[326] = _2640; + uint16_t _2641 = (uint16_t)(150); + _curvea0[327] = _2641; + uint16_t _2642 = (uint16_t)(150); + _curvea0[328] = _2642; + uint16_t _2643 = (uint16_t)(151); + _curvea0[329] = _2643; + uint16_t _2644 = (uint16_t)(151); + _curvea0[330] = _2644; + uint16_t _2645 = (uint16_t)(151); + _curvea0[331] = _2645; + uint16_t _2646 = (uint16_t)(152); + _curvea0[332] = _2646; + uint16_t _2647 = (uint16_t)(152); + _curvea0[333] = _2647; + uint16_t _2648 = (uint16_t)(152); + _curvea0[334] = _2648; + uint16_t _2649 = (uint16_t)(152); + _curvea0[335] = _2649; + uint16_t _2650 = (uint16_t)(153); + _curvea0[336] = _2650; + uint16_t _2651 = (uint16_t)(153); + _curvea0[337] = _2651; + uint16_t _2652 = (uint16_t)(153); + _curvea0[338] = _2652; + uint16_t _2653 = (uint16_t)(154); + _curvea0[339] = _2653; + uint16_t _2654 = (uint16_t)(154); + _curvea0[340] = _2654; + uint16_t _2655 = (uint16_t)(154); + _curvea0[341] = _2655; + uint16_t _2656 = (uint16_t)(154); + _curvea0[342] = _2656; + uint16_t _2657 = (uint16_t)(155); + _curvea0[343] = _2657; + uint16_t _2658 = (uint16_t)(155); + _curvea0[344] = _2658; + uint16_t _2659 = (uint16_t)(155); + _curvea0[345] = _2659; + uint16_t _2660 = (uint16_t)(156); + _curvea0[346] = _2660; + uint16_t _2661 = (uint16_t)(156); + _curvea0[347] = _2661; + uint16_t _2662 = (uint16_t)(156); + _curvea0[348] = _2662; + uint16_t _2663 = (uint16_t)(156); + _curvea0[349] = _2663; + uint16_t _2664 = (uint16_t)(157); + _curvea0[350] = _2664; + uint16_t _2665 = (uint16_t)(157); + _curvea0[351] = _2665; + uint16_t _2666 = (uint16_t)(157); + _curvea0[352] = _2666; + uint16_t _2667 = (uint16_t)(157); + _curvea0[353] = _2667; + uint16_t _2668 = (uint16_t)(158); + _curvea0[354] = _2668; + uint16_t _2669 = (uint16_t)(158); + _curvea0[355] = _2669; + uint16_t _2670 = (uint16_t)(158); + _curvea0[356] = _2670; + uint16_t _2671 = (uint16_t)(159); + _curvea0[357] = _2671; + uint16_t _2672 = (uint16_t)(159); + _curvea0[358] = _2672; + uint16_t _2673 = (uint16_t)(159); + _curvea0[359] = _2673; + uint16_t _2674 = (uint16_t)(159); + _curvea0[360] = _2674; + uint16_t _2675 = (uint16_t)(160); + _curvea0[361] = _2675; + uint16_t _2676 = (uint16_t)(160); + _curvea0[362] = _2676; + uint16_t _2677 = (uint16_t)(160); + _curvea0[363] = _2677; + uint16_t _2678 = (uint16_t)(160); + _curvea0[364] = _2678; + uint16_t _2679 = (uint16_t)(161); + _curvea0[365] = _2679; + uint16_t _2680 = (uint16_t)(161); + _curvea0[366] = _2680; + uint16_t _2681 = (uint16_t)(161); + _curvea0[367] = _2681; + uint16_t _2682 = (uint16_t)(161); + _curvea0[368] = _2682; + uint16_t _2683 = (uint16_t)(162); + _curvea0[369] = _2683; + uint16_t _2684 = (uint16_t)(162); + _curvea0[370] = _2684; + uint16_t _2685 = (uint16_t)(162); + _curvea0[371] = _2685; + uint16_t _2686 = (uint16_t)(162); + _curvea0[372] = _2686; + uint16_t _2687 = (uint16_t)(163); + _curvea0[373] = _2687; + uint16_t _2688 = (uint16_t)(163); + _curvea0[374] = _2688; + uint16_t _2689 = (uint16_t)(163); + _curvea0[375] = _2689; + uint16_t _2690 = (uint16_t)(163); + _curvea0[376] = _2690; + uint16_t _2691 = (uint16_t)(164); + _curvea0[377] = _2691; + uint16_t _2692 = (uint16_t)(164); + _curvea0[378] = _2692; + uint16_t _2693 = (uint16_t)(164); + _curvea0[379] = _2693; + uint16_t _2694 = (uint16_t)(164); + _curvea0[380] = _2694; + uint16_t _2695 = (uint16_t)(165); + _curvea0[381] = _2695; + uint16_t _2696 = (uint16_t)(165); + _curvea0[382] = _2696; + uint16_t _2697 = (uint16_t)(165); + _curvea0[383] = _2697; + uint16_t _2698 = (uint16_t)(166); + _curvea0[384] = _2698; + uint16_t _2699 = (uint16_t)(166); + _curvea0[385] = _2699; + uint16_t _2700 = (uint16_t)(166); + _curvea0[386] = _2700; + uint16_t _2701 = (uint16_t)(166); + _curvea0[387] = _2701; + uint16_t _2702 = (uint16_t)(167); + _curvea0[388] = _2702; + uint16_t _2703 = (uint16_t)(167); + _curvea0[389] = _2703; + uint16_t _2704 = (uint16_t)(167); + _curvea0[390] = _2704; + uint16_t _2705 = (uint16_t)(167); + _curvea0[391] = _2705; + uint16_t _2706 = (uint16_t)(167); + _curvea0[392] = _2706; + uint16_t _2707 = (uint16_t)(168); + _curvea0[393] = _2707; + uint16_t _2708 = (uint16_t)(168); + _curvea0[394] = _2708; + uint16_t _2709 = (uint16_t)(168); + _curvea0[395] = _2709; + uint16_t _2710 = (uint16_t)(168); + _curvea0[396] = _2710; + uint16_t _2711 = (uint16_t)(169); + _curvea0[397] = _2711; + uint16_t _2712 = (uint16_t)(169); + _curvea0[398] = _2712; + uint16_t _2713 = (uint16_t)(169); + _curvea0[399] = _2713; + uint16_t _2714 = (uint16_t)(169); + _curvea0[400] = _2714; + uint16_t _2715 = (uint16_t)(170); + _curvea0[401] = _2715; + uint16_t _2716 = (uint16_t)(170); + _curvea0[402] = _2716; + uint16_t _2717 = (uint16_t)(170); + _curvea0[403] = _2717; + uint16_t _2718 = (uint16_t)(170); + _curvea0[404] = _2718; + uint16_t _2719 = (uint16_t)(171); + _curvea0[405] = _2719; + uint16_t _2720 = (uint16_t)(171); + _curvea0[406] = _2720; + uint16_t _2721 = (uint16_t)(171); + _curvea0[407] = _2721; + uint16_t _2722 = (uint16_t)(171); + _curvea0[408] = _2722; + uint16_t _2723 = (uint16_t)(172); + _curvea0[409] = _2723; + uint16_t _2724 = (uint16_t)(172); + _curvea0[410] = _2724; + uint16_t _2725 = (uint16_t)(172); + _curvea0[411] = _2725; + uint16_t _2726 = (uint16_t)(172); + _curvea0[412] = _2726; + uint16_t _2727 = (uint16_t)(173); + _curvea0[413] = _2727; + uint16_t _2728 = (uint16_t)(173); + _curvea0[414] = _2728; + uint16_t _2729 = (uint16_t)(173); + _curvea0[415] = _2729; + uint16_t _2730 = (uint16_t)(173); + _curvea0[416] = _2730; + uint16_t _2731 = (uint16_t)(173); + _curvea0[417] = _2731; + uint16_t _2732 = (uint16_t)(174); + _curvea0[418] = _2732; + uint16_t _2733 = (uint16_t)(174); + _curvea0[419] = _2733; + uint16_t _2734 = (uint16_t)(174); + _curvea0[420] = _2734; + uint16_t _2735 = (uint16_t)(174); + _curvea0[421] = _2735; + uint16_t _2736 = (uint16_t)(175); + _curvea0[422] = _2736; + uint16_t _2737 = (uint16_t)(175); + _curvea0[423] = _2737; + uint16_t _2738 = (uint16_t)(175); + _curvea0[424] = _2738; + uint16_t _2739 = (uint16_t)(175); + _curvea0[425] = _2739; + uint16_t _2740 = (uint16_t)(176); + _curvea0[426] = _2740; + uint16_t _2741 = (uint16_t)(176); + _curvea0[427] = _2741; + uint16_t _2742 = (uint16_t)(176); + _curvea0[428] = _2742; + uint16_t _2743 = (uint16_t)(176); + _curvea0[429] = _2743; + uint16_t _2744 = (uint16_t)(176); + _curvea0[430] = _2744; + uint16_t _2745 = (uint16_t)(177); + _curvea0[431] = _2745; + uint16_t _2746 = (uint16_t)(177); + _curvea0[432] = _2746; + uint16_t _2747 = (uint16_t)(177); + _curvea0[433] = _2747; + uint16_t _2748 = (uint16_t)(177); + _curvea0[434] = _2748; + uint16_t _2749 = (uint16_t)(178); + _curvea0[435] = _2749; + uint16_t _2750 = (uint16_t)(178); + _curvea0[436] = _2750; + uint16_t _2751 = (uint16_t)(178); + _curvea0[437] = _2751; + uint16_t _2752 = (uint16_t)(178); + _curvea0[438] = _2752; + uint16_t _2753 = (uint16_t)(178); + _curvea0[439] = _2753; + uint16_t _2754 = (uint16_t)(179); + _curvea0[440] = _2754; + uint16_t _2755 = (uint16_t)(179); + _curvea0[441] = _2755; + uint16_t _2756 = (uint16_t)(179); + _curvea0[442] = _2756; + uint16_t _2757 = (uint16_t)(179); + _curvea0[443] = _2757; + uint16_t _2758 = (uint16_t)(180); + _curvea0[444] = _2758; + uint16_t _2759 = (uint16_t)(180); + _curvea0[445] = _2759; + uint16_t _2760 = (uint16_t)(180); + _curvea0[446] = _2760; + uint16_t _2761 = (uint16_t)(180); + _curvea0[447] = _2761; + uint16_t _2762 = (uint16_t)(180); + _curvea0[448] = _2762; + uint16_t _2763 = (uint16_t)(181); + _curvea0[449] = _2763; + uint16_t _2764 = (uint16_t)(181); + _curvea0[450] = _2764; + uint16_t _2765 = (uint16_t)(181); + _curvea0[451] = _2765; + uint16_t _2766 = (uint16_t)(181); + _curvea0[452] = _2766; + uint16_t _2767 = (uint16_t)(181); + _curvea0[453] = _2767; + uint16_t _2768 = (uint16_t)(182); + _curvea0[454] = _2768; + uint16_t _2769 = (uint16_t)(182); + _curvea0[455] = _2769; + uint16_t _2770 = (uint16_t)(182); + _curvea0[456] = _2770; + uint16_t _2771 = (uint16_t)(182); + _curvea0[457] = _2771; + uint16_t _2772 = (uint16_t)(183); + _curvea0[458] = _2772; + uint16_t _2773 = (uint16_t)(183); + _curvea0[459] = _2773; + uint16_t _2774 = (uint16_t)(183); + _curvea0[460] = _2774; + uint16_t _2775 = (uint16_t)(183); + _curvea0[461] = _2775; + uint16_t _2776 = (uint16_t)(183); + _curvea0[462] = _2776; + uint16_t _2777 = (uint16_t)(184); + _curvea0[463] = _2777; + uint16_t _2778 = (uint16_t)(184); + _curvea0[464] = _2778; + uint16_t _2779 = (uint16_t)(184); + _curvea0[465] = _2779; + uint16_t _2780 = (uint16_t)(184); + _curvea0[466] = _2780; + uint16_t _2781 = (uint16_t)(184); + _curvea0[467] = _2781; + uint16_t _2782 = (uint16_t)(185); + _curvea0[468] = _2782; + uint16_t _2783 = (uint16_t)(185); + _curvea0[469] = _2783; + uint16_t _2784 = (uint16_t)(185); + _curvea0[470] = _2784; + uint16_t _2785 = (uint16_t)(185); + _curvea0[471] = _2785; + uint16_t _2786 = (uint16_t)(185); + _curvea0[472] = _2786; + uint16_t _2787 = (uint16_t)(186); + _curvea0[473] = _2787; + uint16_t _2788 = (uint16_t)(186); + _curvea0[474] = _2788; + uint16_t _2789 = (uint16_t)(186); + _curvea0[475] = _2789; + uint16_t _2790 = (uint16_t)(186); + _curvea0[476] = _2790; + uint16_t _2791 = (uint16_t)(187); + _curvea0[477] = _2791; + uint16_t _2792 = (uint16_t)(187); + _curvea0[478] = _2792; + uint16_t _2793 = (uint16_t)(187); + _curvea0[479] = _2793; + uint16_t _2794 = (uint16_t)(187); + _curvea0[480] = _2794; + uint16_t _2795 = (uint16_t)(187); + _curvea0[481] = _2795; + uint16_t _2796 = (uint16_t)(188); + _curvea0[482] = _2796; + uint16_t _2797 = (uint16_t)(188); + _curvea0[483] = _2797; + uint16_t _2798 = (uint16_t)(188); + _curvea0[484] = _2798; + uint16_t _2799 = (uint16_t)(188); + _curvea0[485] = _2799; + uint16_t _2800 = (uint16_t)(188); + _curvea0[486] = _2800; + uint16_t _2801 = (uint16_t)(189); + _curvea0[487] = _2801; + uint16_t _2802 = (uint16_t)(189); + _curvea0[488] = _2802; + uint16_t _2803 = (uint16_t)(189); + _curvea0[489] = _2803; + uint16_t _2804 = (uint16_t)(189); + _curvea0[490] = _2804; + uint16_t _2805 = (uint16_t)(189); + _curvea0[491] = _2805; + uint16_t _2806 = (uint16_t)(190); + _curvea0[492] = _2806; + uint16_t _2807 = (uint16_t)(190); + _curvea0[493] = _2807; + uint16_t _2808 = (uint16_t)(190); + _curvea0[494] = _2808; + uint16_t _2809 = (uint16_t)(190); + _curvea0[495] = _2809; + uint16_t _2810 = (uint16_t)(190); + _curvea0[496] = _2810; + uint16_t _2811 = (uint16_t)(190); + _curvea0[497] = _2811; + uint16_t _2812 = (uint16_t)(191); + _curvea0[498] = _2812; + uint16_t _2813 = (uint16_t)(191); + _curvea0[499] = _2813; + uint16_t _2814 = (uint16_t)(191); + _curvea0[500] = _2814; + uint16_t _2815 = (uint16_t)(191); + _curvea0[501] = _2815; + uint16_t _2816 = (uint16_t)(191); + _curvea0[502] = _2816; + uint16_t _2817 = (uint16_t)(192); + _curvea0[503] = _2817; + uint16_t _2818 = (uint16_t)(192); + _curvea0[504] = _2818; + uint16_t _2819 = (uint16_t)(192); + _curvea0[505] = _2819; + uint16_t _2820 = (uint16_t)(192); + _curvea0[506] = _2820; + uint16_t _2821 = (uint16_t)(192); + _curvea0[507] = _2821; + uint16_t _2822 = (uint16_t)(193); + _curvea0[508] = _2822; + uint16_t _2823 = (uint16_t)(193); + _curvea0[509] = _2823; + uint16_t _2824 = (uint16_t)(193); + _curvea0[510] = _2824; + uint16_t _2825 = (uint16_t)(193); + _curvea0[511] = _2825; + uint16_t _2826 = (uint16_t)(193); + _curvea0[512] = _2826; + uint16_t _2827 = (uint16_t)(194); + _curvea0[513] = _2827; + uint16_t _2828 = (uint16_t)(194); + _curvea0[514] = _2828; + uint16_t _2829 = (uint16_t)(194); + _curvea0[515] = _2829; + uint16_t _2830 = (uint16_t)(194); + _curvea0[516] = _2830; + uint16_t _2831 = (uint16_t)(194); + _curvea0[517] = _2831; + uint16_t _2832 = (uint16_t)(195); + _curvea0[518] = _2832; + uint16_t _2833 = (uint16_t)(195); + _curvea0[519] = _2833; + uint16_t _2834 = (uint16_t)(195); + _curvea0[520] = _2834; + uint16_t _2835 = (uint16_t)(195); + _curvea0[521] = _2835; + uint16_t _2836 = (uint16_t)(195); + _curvea0[522] = _2836; + uint16_t _2837 = (uint16_t)(195); + _curvea0[523] = _2837; + uint16_t _2838 = (uint16_t)(196); + _curvea0[524] = _2838; + uint16_t _2839 = (uint16_t)(196); + _curvea0[525] = _2839; + uint16_t _2840 = (uint16_t)(196); + _curvea0[526] = _2840; + uint16_t _2841 = (uint16_t)(196); + _curvea0[527] = _2841; + uint16_t _2842 = (uint16_t)(196); + _curvea0[528] = _2842; + uint16_t _2843 = (uint16_t)(197); + _curvea0[529] = _2843; + uint16_t _2844 = (uint16_t)(197); + _curvea0[530] = _2844; + uint16_t _2845 = (uint16_t)(197); + _curvea0[531] = _2845; + uint16_t _2846 = (uint16_t)(197); + _curvea0[532] = _2846; + uint16_t _2847 = (uint16_t)(197); + _curvea0[533] = _2847; + uint16_t _2848 = (uint16_t)(197); + _curvea0[534] = _2848; + uint16_t _2849 = (uint16_t)(198); + _curvea0[535] = _2849; + uint16_t _2850 = (uint16_t)(198); + _curvea0[536] = _2850; + uint16_t _2851 = (uint16_t)(198); + _curvea0[537] = _2851; + uint16_t _2852 = (uint16_t)(198); + _curvea0[538] = _2852; + uint16_t _2853 = (uint16_t)(198); + _curvea0[539] = _2853; + uint16_t _2854 = (uint16_t)(199); + _curvea0[540] = _2854; + uint16_t _2855 = (uint16_t)(199); + _curvea0[541] = _2855; + uint16_t _2856 = (uint16_t)(199); + _curvea0[542] = _2856; + uint16_t _2857 = (uint16_t)(199); + _curvea0[543] = _2857; + uint16_t _2858 = (uint16_t)(199); + _curvea0[544] = _2858; + uint16_t _2859 = (uint16_t)(199); + _curvea0[545] = _2859; + uint16_t _2860 = (uint16_t)(200); + _curvea0[546] = _2860; + uint16_t _2861 = (uint16_t)(200); + _curvea0[547] = _2861; + uint16_t _2862 = (uint16_t)(200); + _curvea0[548] = _2862; + uint16_t _2863 = (uint16_t)(200); + _curvea0[549] = _2863; + uint16_t _2864 = (uint16_t)(200); + _curvea0[550] = _2864; + uint16_t _2865 = (uint16_t)(200); + _curvea0[551] = _2865; + uint16_t _2866 = (uint16_t)(201); + _curvea0[552] = _2866; + uint16_t _2867 = (uint16_t)(201); + _curvea0[553] = _2867; + uint16_t _2868 = (uint16_t)(201); + _curvea0[554] = _2868; + uint16_t _2869 = (uint16_t)(201); + _curvea0[555] = _2869; + uint16_t _2870 = (uint16_t)(201); + _curvea0[556] = _2870; + uint16_t _2871 = (uint16_t)(202); + _curvea0[557] = _2871; + uint16_t _2872 = (uint16_t)(202); + _curvea0[558] = _2872; + uint16_t _2873 = (uint16_t)(202); + _curvea0[559] = _2873; + uint16_t _2874 = (uint16_t)(202); + _curvea0[560] = _2874; + uint16_t _2875 = (uint16_t)(202); + _curvea0[561] = _2875; + uint16_t _2876 = (uint16_t)(202); + _curvea0[562] = _2876; + uint16_t _2877 = (uint16_t)(203); + _curvea0[563] = _2877; + uint16_t _2878 = (uint16_t)(203); + _curvea0[564] = _2878; + uint16_t _2879 = (uint16_t)(203); + _curvea0[565] = _2879; + uint16_t _2880 = (uint16_t)(203); + _curvea0[566] = _2880; + uint16_t _2881 = (uint16_t)(203); + _curvea0[567] = _2881; + uint16_t _2882 = (uint16_t)(203); + _curvea0[568] = _2882; + uint16_t _2883 = (uint16_t)(204); + _curvea0[569] = _2883; + uint16_t _2884 = (uint16_t)(204); + _curvea0[570] = _2884; + uint16_t _2885 = (uint16_t)(204); + _curvea0[571] = _2885; + uint16_t _2886 = (uint16_t)(204); + _curvea0[572] = _2886; + uint16_t _2887 = (uint16_t)(204); + _curvea0[573] = _2887; + uint16_t _2888 = (uint16_t)(204); + _curvea0[574] = _2888; + uint16_t _2889 = (uint16_t)(205); + _curvea0[575] = _2889; + uint16_t _2890 = (uint16_t)(205); + _curvea0[576] = _2890; + uint16_t _2891 = (uint16_t)(205); + _curvea0[577] = _2891; + uint16_t _2892 = (uint16_t)(205); + _curvea0[578] = _2892; + uint16_t _2893 = (uint16_t)(205); + _curvea0[579] = _2893; + uint16_t _2894 = (uint16_t)(205); + _curvea0[580] = _2894; + uint16_t _2895 = (uint16_t)(206); + _curvea0[581] = _2895; + uint16_t _2896 = (uint16_t)(206); + _curvea0[582] = _2896; + uint16_t _2897 = (uint16_t)(206); + _curvea0[583] = _2897; + uint16_t _2898 = (uint16_t)(206); + _curvea0[584] = _2898; + uint16_t _2899 = (uint16_t)(206); + _curvea0[585] = _2899; + uint16_t _2900 = (uint16_t)(206); + _curvea0[586] = _2900; + uint16_t _2901 = (uint16_t)(207); + _curvea0[587] = _2901; + uint16_t _2902 = (uint16_t)(207); + _curvea0[588] = _2902; + uint16_t _2903 = (uint16_t)(207); + _curvea0[589] = _2903; + uint16_t _2904 = (uint16_t)(207); + _curvea0[590] = _2904; + uint16_t _2905 = (uint16_t)(207); + _curvea0[591] = _2905; + uint16_t _2906 = (uint16_t)(207); + _curvea0[592] = _2906; + uint16_t _2907 = (uint16_t)(208); + _curvea0[593] = _2907; + uint16_t _2908 = (uint16_t)(208); + _curvea0[594] = _2908; + uint16_t _2909 = (uint16_t)(208); + _curvea0[595] = _2909; + uint16_t _2910 = (uint16_t)(208); + _curvea0[596] = _2910; + uint16_t _2911 = (uint16_t)(208); + _curvea0[597] = _2911; + uint16_t _2912 = (uint16_t)(208); + _curvea0[598] = _2912; + uint16_t _2913 = (uint16_t)(209); + _curvea0[599] = _2913; + uint16_t _2914 = (uint16_t)(209); + _curvea0[600] = _2914; + uint16_t _2915 = (uint16_t)(209); + _curvea0[601] = _2915; + uint16_t _2916 = (uint16_t)(209); + _curvea0[602] = _2916; + uint16_t _2917 = (uint16_t)(209); + _curvea0[603] = _2917; + uint16_t _2918 = (uint16_t)(209); + _curvea0[604] = _2918; + uint16_t _2919 = (uint16_t)(209); + _curvea0[605] = _2919; + uint16_t _2920 = (uint16_t)(210); + _curvea0[606] = _2920; + uint16_t _2921 = (uint16_t)(210); + _curvea0[607] = _2921; + uint16_t _2922 = (uint16_t)(210); + _curvea0[608] = _2922; + uint16_t _2923 = (uint16_t)(210); + _curvea0[609] = _2923; + uint16_t _2924 = (uint16_t)(210); + _curvea0[610] = _2924; + uint16_t _2925 = (uint16_t)(210); + _curvea0[611] = _2925; + uint16_t _2926 = (uint16_t)(211); + _curvea0[612] = _2926; + uint16_t _2927 = (uint16_t)(211); + _curvea0[613] = _2927; + uint16_t _2928 = (uint16_t)(211); + _curvea0[614] = _2928; + uint16_t _2929 = (uint16_t)(211); + _curvea0[615] = _2929; + uint16_t _2930 = (uint16_t)(211); + _curvea0[616] = _2930; + uint16_t _2931 = (uint16_t)(211); + _curvea0[617] = _2931; + uint16_t _2932 = (uint16_t)(211); + _curvea0[618] = _2932; + uint16_t _2933 = (uint16_t)(212); + _curvea0[619] = _2933; + uint16_t _2934 = (uint16_t)(212); + _curvea0[620] = _2934; + uint16_t _2935 = (uint16_t)(212); + _curvea0[621] = _2935; + uint16_t _2936 = (uint16_t)(212); + _curvea0[622] = _2936; + uint16_t _2937 = (uint16_t)(212); + _curvea0[623] = _2937; + uint16_t _2938 = (uint16_t)(212); + _curvea0[624] = _2938; + uint16_t _2939 = (uint16_t)(213); + _curvea0[625] = _2939; + uint16_t _2940 = (uint16_t)(213); + _curvea0[626] = _2940; + uint16_t _2941 = (uint16_t)(213); + _curvea0[627] = _2941; + uint16_t _2942 = (uint16_t)(213); + _curvea0[628] = _2942; + uint16_t _2943 = (uint16_t)(213); + _curvea0[629] = _2943; + uint16_t _2944 = (uint16_t)(213); + _curvea0[630] = _2944; + uint16_t _2945 = (uint16_t)(213); + _curvea0[631] = _2945; + uint16_t _2946 = (uint16_t)(214); + _curvea0[632] = _2946; + uint16_t _2947 = (uint16_t)(214); + _curvea0[633] = _2947; + uint16_t _2948 = (uint16_t)(214); + _curvea0[634] = _2948; + uint16_t _2949 = (uint16_t)(214); + _curvea0[635] = _2949; + uint16_t _2950 = (uint16_t)(214); + _curvea0[636] = _2950; + uint16_t _2951 = (uint16_t)(214); + _curvea0[637] = _2951; + uint16_t _2952 = (uint16_t)(214); + _curvea0[638] = _2952; + uint16_t _2953 = (uint16_t)(215); + _curvea0[639] = _2953; + uint16_t _2954 = (uint16_t)(215); + _curvea0[640] = _2954; + uint16_t _2955 = (uint16_t)(215); + _curvea0[641] = _2955; + uint16_t _2956 = (uint16_t)(215); + _curvea0[642] = _2956; + uint16_t _2957 = (uint16_t)(215); + _curvea0[643] = _2957; + uint16_t _2958 = (uint16_t)(215); + _curvea0[644] = _2958; + uint16_t _2959 = (uint16_t)(216); + _curvea0[645] = _2959; + uint16_t _2960 = (uint16_t)(216); + _curvea0[646] = _2960; + uint16_t _2961 = (uint16_t)(216); + _curvea0[647] = _2961; + uint16_t _2962 = (uint16_t)(216); + _curvea0[648] = _2962; + uint16_t _2963 = (uint16_t)(216); + _curvea0[649] = _2963; + uint16_t _2964 = (uint16_t)(216); + _curvea0[650] = _2964; + uint16_t _2965 = (uint16_t)(216); + _curvea0[651] = _2965; + uint16_t _2966 = (uint16_t)(217); + _curvea0[652] = _2966; + uint16_t _2967 = (uint16_t)(217); + _curvea0[653] = _2967; + uint16_t _2968 = (uint16_t)(217); + _curvea0[654] = _2968; + uint16_t _2969 = (uint16_t)(217); + _curvea0[655] = _2969; + uint16_t _2970 = (uint16_t)(217); + _curvea0[656] = _2970; + uint16_t _2971 = (uint16_t)(217); + _curvea0[657] = _2971; + uint16_t _2972 = (uint16_t)(217); + _curvea0[658] = _2972; + uint16_t _2973 = (uint16_t)(218); + _curvea0[659] = _2973; + uint16_t _2974 = (uint16_t)(218); + _curvea0[660] = _2974; + uint16_t _2975 = (uint16_t)(218); + _curvea0[661] = _2975; + uint16_t _2976 = (uint16_t)(218); + _curvea0[662] = _2976; + uint16_t _2977 = (uint16_t)(218); + _curvea0[663] = _2977; + uint16_t _2978 = (uint16_t)(218); + _curvea0[664] = _2978; + uint16_t _2979 = (uint16_t)(218); + _curvea0[665] = _2979; + uint16_t _2980 = (uint16_t)(219); + _curvea0[666] = _2980; + uint16_t _2981 = (uint16_t)(219); + _curvea0[667] = _2981; + uint16_t _2982 = (uint16_t)(219); + _curvea0[668] = _2982; + uint16_t _2983 = (uint16_t)(219); + _curvea0[669] = _2983; + uint16_t _2984 = (uint16_t)(219); + _curvea0[670] = _2984; + uint16_t _2985 = (uint16_t)(219); + _curvea0[671] = _2985; + uint16_t _2986 = (uint16_t)(219); + _curvea0[672] = _2986; + uint16_t _2987 = (uint16_t)(220); + _curvea0[673] = _2987; + uint16_t _2988 = (uint16_t)(220); + _curvea0[674] = _2988; + uint16_t _2989 = (uint16_t)(220); + _curvea0[675] = _2989; + uint16_t _2990 = (uint16_t)(220); + _curvea0[676] = _2990; + uint16_t _2991 = (uint16_t)(220); + _curvea0[677] = _2991; + uint16_t _2992 = (uint16_t)(220); + _curvea0[678] = _2992; + uint16_t _2993 = (uint16_t)(220); + _curvea0[679] = _2993; + uint16_t _2994 = (uint16_t)(220); + _curvea0[680] = _2994; + uint16_t _2995 = (uint16_t)(221); + _curvea0[681] = _2995; + uint16_t _2996 = (uint16_t)(221); + _curvea0[682] = _2996; + uint16_t _2997 = (uint16_t)(221); + _curvea0[683] = _2997; + uint16_t _2998 = (uint16_t)(221); + _curvea0[684] = _2998; + uint16_t _2999 = (uint16_t)(221); + _curvea0[685] = _2999; + uint16_t _3000 = (uint16_t)(221); + _curvea0[686] = _3000; + uint16_t _3001 = (uint16_t)(221); + _curvea0[687] = _3001; + uint16_t _3002 = (uint16_t)(222); + _curvea0[688] = _3002; + uint16_t _3003 = (uint16_t)(222); + _curvea0[689] = _3003; + uint16_t _3004 = (uint16_t)(222); + _curvea0[690] = _3004; + uint16_t _3005 = (uint16_t)(222); + _curvea0[691] = _3005; + uint16_t _3006 = (uint16_t)(222); + _curvea0[692] = _3006; + uint16_t _3007 = (uint16_t)(222); + _curvea0[693] = _3007; + uint16_t _3008 = (uint16_t)(222); + _curvea0[694] = _3008; + uint16_t _3009 = (uint16_t)(223); + _curvea0[695] = _3009; + uint16_t _3010 = (uint16_t)(223); + _curvea0[696] = _3010; + uint16_t _3011 = (uint16_t)(223); + _curvea0[697] = _3011; + uint16_t _3012 = (uint16_t)(223); + _curvea0[698] = _3012; + uint16_t _3013 = (uint16_t)(223); + _curvea0[699] = _3013; + uint16_t _3014 = (uint16_t)(223); + _curvea0[700] = _3014; + uint16_t _3015 = (uint16_t)(223); + _curvea0[701] = _3015; + uint16_t _3016 = (uint16_t)(223); + _curvea0[702] = _3016; + uint16_t _3017 = (uint16_t)(224); + _curvea0[703] = _3017; + uint16_t _3018 = (uint16_t)(224); + _curvea0[704] = _3018; + uint16_t _3019 = (uint16_t)(224); + _curvea0[705] = _3019; + uint16_t _3020 = (uint16_t)(224); + _curvea0[706] = _3020; + uint16_t _3021 = (uint16_t)(224); + _curvea0[707] = _3021; + uint16_t _3022 = (uint16_t)(224); + _curvea0[708] = _3022; + uint16_t _3023 = (uint16_t)(224); + _curvea0[709] = _3023; + uint16_t _3024 = (uint16_t)(224); + _curvea0[710] = _3024; + uint16_t _3025 = (uint16_t)(225); + _curvea0[711] = _3025; + uint16_t _3026 = (uint16_t)(225); + _curvea0[712] = _3026; + uint16_t _3027 = (uint16_t)(225); + _curvea0[713] = _3027; + uint16_t _3028 = (uint16_t)(225); + _curvea0[714] = _3028; + uint16_t _3029 = (uint16_t)(225); + _curvea0[715] = _3029; + uint16_t _3030 = (uint16_t)(225); + _curvea0[716] = _3030; + uint16_t _3031 = (uint16_t)(225); + _curvea0[717] = _3031; + uint16_t _3032 = (uint16_t)(226); + _curvea0[718] = _3032; + uint16_t _3033 = (uint16_t)(226); + _curvea0[719] = _3033; + uint16_t _3034 = (uint16_t)(226); + _curvea0[720] = _3034; + uint16_t _3035 = (uint16_t)(226); + _curvea0[721] = _3035; + uint16_t _3036 = (uint16_t)(226); + _curvea0[722] = _3036; + uint16_t _3037 = (uint16_t)(226); + _curvea0[723] = _3037; + uint16_t _3038 = (uint16_t)(226); + _curvea0[724] = _3038; + uint16_t _3039 = (uint16_t)(226); + _curvea0[725] = _3039; + uint16_t _3040 = (uint16_t)(227); + _curvea0[726] = _3040; + uint16_t _3041 = (uint16_t)(227); + _curvea0[727] = _3041; + uint16_t _3042 = (uint16_t)(227); + _curvea0[728] = _3042; + uint16_t _3043 = (uint16_t)(227); + _curvea0[729] = _3043; + uint16_t _3044 = (uint16_t)(227); + _curvea0[730] = _3044; + uint16_t _3045 = (uint16_t)(227); + _curvea0[731] = _3045; + uint16_t _3046 = (uint16_t)(227); + _curvea0[732] = _3046; + uint16_t _3047 = (uint16_t)(227); + _curvea0[733] = _3047; + uint16_t _3048 = (uint16_t)(228); + _curvea0[734] = _3048; + uint16_t _3049 = (uint16_t)(228); + _curvea0[735] = _3049; + uint16_t _3050 = (uint16_t)(228); + _curvea0[736] = _3050; + uint16_t _3051 = (uint16_t)(228); + _curvea0[737] = _3051; + uint16_t _3052 = (uint16_t)(228); + _curvea0[738] = _3052; + uint16_t _3053 = (uint16_t)(228); + _curvea0[739] = _3053; + uint16_t _3054 = (uint16_t)(228); + _curvea0[740] = _3054; + uint16_t _3055 = (uint16_t)(228); + _curvea0[741] = _3055; + uint16_t _3056 = (uint16_t)(228); + _curvea0[742] = _3056; + uint16_t _3057 = (uint16_t)(229); + _curvea0[743] = _3057; + uint16_t _3058 = (uint16_t)(229); + _curvea0[744] = _3058; + uint16_t _3059 = (uint16_t)(229); + _curvea0[745] = _3059; + uint16_t _3060 = (uint16_t)(229); + _curvea0[746] = _3060; + uint16_t _3061 = (uint16_t)(229); + _curvea0[747] = _3061; + uint16_t _3062 = (uint16_t)(229); + _curvea0[748] = _3062; + uint16_t _3063 = (uint16_t)(229); + _curvea0[749] = _3063; + uint16_t _3064 = (uint16_t)(229); + _curvea0[750] = _3064; + uint16_t _3065 = (uint16_t)(230); + _curvea0[751] = _3065; + uint16_t _3066 = (uint16_t)(230); + _curvea0[752] = _3066; + uint16_t _3067 = (uint16_t)(230); + _curvea0[753] = _3067; + uint16_t _3068 = (uint16_t)(230); + _curvea0[754] = _3068; + uint16_t _3069 = (uint16_t)(230); + _curvea0[755] = _3069; + uint16_t _3070 = (uint16_t)(230); + _curvea0[756] = _3070; + uint16_t _3071 = (uint16_t)(230); + _curvea0[757] = _3071; + uint16_t _3072 = (uint16_t)(230); + _curvea0[758] = _3072; + uint16_t _3073 = (uint16_t)(231); + _curvea0[759] = _3073; + uint16_t _3074 = (uint16_t)(231); + _curvea0[760] = _3074; + uint16_t _3075 = (uint16_t)(231); + _curvea0[761] = _3075; + uint16_t _3076 = (uint16_t)(231); + _curvea0[762] = _3076; + uint16_t _3077 = (uint16_t)(231); + _curvea0[763] = _3077; + uint16_t _3078 = (uint16_t)(231); + _curvea0[764] = _3078; + uint16_t _3079 = (uint16_t)(231); + _curvea0[765] = _3079; + uint16_t _3080 = (uint16_t)(231); + _curvea0[766] = _3080; + uint16_t _3081 = (uint16_t)(231); + _curvea0[767] = _3081; + uint16_t _3082 = (uint16_t)(232); + _curvea0[768] = _3082; + uint16_t _3083 = (uint16_t)(232); + _curvea0[769] = _3083; + uint16_t _3084 = (uint16_t)(232); + _curvea0[770] = _3084; + uint16_t _3085 = (uint16_t)(232); + _curvea0[771] = _3085; + uint16_t _3086 = (uint16_t)(232); + _curvea0[772] = _3086; + uint16_t _3087 = (uint16_t)(232); + _curvea0[773] = _3087; + uint16_t _3088 = (uint16_t)(232); + _curvea0[774] = _3088; + uint16_t _3089 = (uint16_t)(232); + _curvea0[775] = _3089; + uint16_t _3090 = (uint16_t)(233); + _curvea0[776] = _3090; + uint16_t _3091 = (uint16_t)(233); + _curvea0[777] = _3091; + uint16_t _3092 = (uint16_t)(233); + _curvea0[778] = _3092; + uint16_t _3093 = (uint16_t)(233); + _curvea0[779] = _3093; + uint16_t _3094 = (uint16_t)(233); + _curvea0[780] = _3094; + uint16_t _3095 = (uint16_t)(233); + _curvea0[781] = _3095; + uint16_t _3096 = (uint16_t)(233); + _curvea0[782] = _3096; + uint16_t _3097 = (uint16_t)(233); + _curvea0[783] = _3097; + uint16_t _3098 = (uint16_t)(233); + _curvea0[784] = _3098; + uint16_t _3099 = (uint16_t)(234); + _curvea0[785] = _3099; + uint16_t _3100 = (uint16_t)(234); + _curvea0[786] = _3100; + uint16_t _3101 = (uint16_t)(234); + _curvea0[787] = _3101; + uint16_t _3102 = (uint16_t)(234); + _curvea0[788] = _3102; + uint16_t _3103 = (uint16_t)(234); + _curvea0[789] = _3103; + uint16_t _3104 = (uint16_t)(234); + _curvea0[790] = _3104; + uint16_t _3105 = (uint16_t)(234); + _curvea0[791] = _3105; + uint16_t _3106 = (uint16_t)(234); + _curvea0[792] = _3106; + uint16_t _3107 = (uint16_t)(234); + _curvea0[793] = _3107; + uint16_t _3108 = (uint16_t)(235); + _curvea0[794] = _3108; + uint16_t _3109 = (uint16_t)(235); + _curvea0[795] = _3109; + uint16_t _3110 = (uint16_t)(235); + _curvea0[796] = _3110; + uint16_t _3111 = (uint16_t)(235); + _curvea0[797] = _3111; + uint16_t _3112 = (uint16_t)(235); + _curvea0[798] = _3112; + uint16_t _3113 = (uint16_t)(235); + _curvea0[799] = _3113; + uint16_t _3114 = (uint16_t)(235); + _curvea0[800] = _3114; + uint16_t _3115 = (uint16_t)(235); + _curvea0[801] = _3115; + uint16_t _3116 = (uint16_t)(235); + _curvea0[802] = _3116; + uint16_t _3117 = (uint16_t)(236); + _curvea0[803] = _3117; + uint16_t _3118 = (uint16_t)(236); + _curvea0[804] = _3118; + uint16_t _3119 = (uint16_t)(236); + _curvea0[805] = _3119; + uint16_t _3120 = (uint16_t)(236); + _curvea0[806] = _3120; + uint16_t _3121 = (uint16_t)(236); + _curvea0[807] = _3121; + uint16_t _3122 = (uint16_t)(236); + _curvea0[808] = _3122; + uint16_t _3123 = (uint16_t)(236); + _curvea0[809] = _3123; + uint16_t _3124 = (uint16_t)(236); + _curvea0[810] = _3124; + uint16_t _3125 = (uint16_t)(236); + _curvea0[811] = _3125; + uint16_t _3126 = (uint16_t)(237); + _curvea0[812] = _3126; + uint16_t _3127 = (uint16_t)(237); + _curvea0[813] = _3127; + uint16_t _3128 = (uint16_t)(237); + _curvea0[814] = _3128; + uint16_t _3129 = (uint16_t)(237); + _curvea0[815] = _3129; + uint16_t _3130 = (uint16_t)(237); + _curvea0[816] = _3130; + uint16_t _3131 = (uint16_t)(237); + _curvea0[817] = _3131; + uint16_t _3132 = (uint16_t)(237); + _curvea0[818] = _3132; + uint16_t _3133 = (uint16_t)(237); + _curvea0[819] = _3133; + uint16_t _3134 = (uint16_t)(237); + _curvea0[820] = _3134; + uint16_t _3135 = (uint16_t)(237); + _curvea0[821] = _3135; + uint16_t _3136 = (uint16_t)(238); + _curvea0[822] = _3136; + uint16_t _3137 = (uint16_t)(238); + _curvea0[823] = _3137; + uint16_t _3138 = (uint16_t)(238); + _curvea0[824] = _3138; + uint16_t _3139 = (uint16_t)(238); + _curvea0[825] = _3139; + uint16_t _3140 = (uint16_t)(238); + _curvea0[826] = _3140; + uint16_t _3141 = (uint16_t)(238); + _curvea0[827] = _3141; + uint16_t _3142 = (uint16_t)(238); + _curvea0[828] = _3142; + uint16_t _3143 = (uint16_t)(238); + _curvea0[829] = _3143; + uint16_t _3144 = (uint16_t)(238); + _curvea0[830] = _3144; + uint16_t _3145 = (uint16_t)(239); + _curvea0[831] = _3145; + uint16_t _3146 = (uint16_t)(239); + _curvea0[832] = _3146; + uint16_t _3147 = (uint16_t)(239); + _curvea0[833] = _3147; + uint16_t _3148 = (uint16_t)(239); + _curvea0[834] = _3148; + uint16_t _3149 = (uint16_t)(239); + _curvea0[835] = _3149; + uint16_t _3150 = (uint16_t)(239); + _curvea0[836] = _3150; + uint16_t _3151 = (uint16_t)(239); + _curvea0[837] = _3151; + uint16_t _3152 = (uint16_t)(239); + _curvea0[838] = _3152; + uint16_t _3153 = (uint16_t)(239); + _curvea0[839] = _3153; + uint16_t _3154 = (uint16_t)(239); + _curvea0[840] = _3154; + uint16_t _3155 = (uint16_t)(240); + _curvea0[841] = _3155; + uint16_t _3156 = (uint16_t)(240); + _curvea0[842] = _3156; + uint16_t _3157 = (uint16_t)(240); + _curvea0[843] = _3157; + uint16_t _3158 = (uint16_t)(240); + _curvea0[844] = _3158; + uint16_t _3159 = (uint16_t)(240); + _curvea0[845] = _3159; + uint16_t _3160 = (uint16_t)(240); + _curvea0[846] = _3160; + uint16_t _3161 = (uint16_t)(240); + _curvea0[847] = _3161; + uint16_t _3162 = (uint16_t)(240); + _curvea0[848] = _3162; + uint16_t _3163 = (uint16_t)(240); + _curvea0[849] = _3163; + uint16_t _3164 = (uint16_t)(240); + _curvea0[850] = _3164; + uint16_t _3165 = (uint16_t)(241); + _curvea0[851] = _3165; + uint16_t _3166 = (uint16_t)(241); + _curvea0[852] = _3166; + uint16_t _3167 = (uint16_t)(241); + _curvea0[853] = _3167; + uint16_t _3168 = (uint16_t)(241); + _curvea0[854] = _3168; + uint16_t _3169 = (uint16_t)(241); + _curvea0[855] = _3169; + uint16_t _3170 = (uint16_t)(241); + _curvea0[856] = _3170; + uint16_t _3171 = (uint16_t)(241); + _curvea0[857] = _3171; + uint16_t _3172 = (uint16_t)(241); + _curvea0[858] = _3172; + uint16_t _3173 = (uint16_t)(241); + _curvea0[859] = _3173; + uint16_t _3174 = (uint16_t)(241); + _curvea0[860] = _3174; + uint16_t _3175 = (uint16_t)(242); + _curvea0[861] = _3175; + uint16_t _3176 = (uint16_t)(242); + _curvea0[862] = _3176; + uint16_t _3177 = (uint16_t)(242); + _curvea0[863] = _3177; + uint16_t _3178 = (uint16_t)(242); + _curvea0[864] = _3178; + uint16_t _3179 = (uint16_t)(242); + _curvea0[865] = _3179; + uint16_t _3180 = (uint16_t)(242); + _curvea0[866] = _3180; + uint16_t _3181 = (uint16_t)(242); + _curvea0[867] = _3181; + uint16_t _3182 = (uint16_t)(242); + _curvea0[868] = _3182; + uint16_t _3183 = (uint16_t)(242); + _curvea0[869] = _3183; + uint16_t _3184 = (uint16_t)(242); + _curvea0[870] = _3184; + uint16_t _3185 = (uint16_t)(243); + _curvea0[871] = _3185; + uint16_t _3186 = (uint16_t)(243); + _curvea0[872] = _3186; + uint16_t _3187 = (uint16_t)(243); + _curvea0[873] = _3187; + uint16_t _3188 = (uint16_t)(243); + _curvea0[874] = _3188; + uint16_t _3189 = (uint16_t)(243); + _curvea0[875] = _3189; + uint16_t _3190 = (uint16_t)(243); + _curvea0[876] = _3190; + uint16_t _3191 = (uint16_t)(243); + _curvea0[877] = _3191; + uint16_t _3192 = (uint16_t)(243); + _curvea0[878] = _3192; + uint16_t _3193 = (uint16_t)(243); + _curvea0[879] = _3193; + uint16_t _3194 = (uint16_t)(243); + _curvea0[880] = _3194; + uint16_t _3195 = (uint16_t)(244); + _curvea0[881] = _3195; + uint16_t _3196 = (uint16_t)(244); + _curvea0[882] = _3196; + uint16_t _3197 = (uint16_t)(244); + _curvea0[883] = _3197; + uint16_t _3198 = (uint16_t)(244); + _curvea0[884] = _3198; + uint16_t _3199 = (uint16_t)(244); + _curvea0[885] = _3199; + uint16_t _3200 = (uint16_t)(244); + _curvea0[886] = _3200; + uint16_t _3201 = (uint16_t)(244); + _curvea0[887] = _3201; + uint16_t _3202 = (uint16_t)(244); + _curvea0[888] = _3202; + uint16_t _3203 = (uint16_t)(244); + _curvea0[889] = _3203; + uint16_t _3204 = (uint16_t)(244); + _curvea0[890] = _3204; + uint16_t _3205 = (uint16_t)(244); + _curvea0[891] = _3205; + uint16_t _3206 = (uint16_t)(245); + _curvea0[892] = _3206; + uint16_t _3207 = (uint16_t)(245); + _curvea0[893] = _3207; + uint16_t _3208 = (uint16_t)(245); + _curvea0[894] = _3208; + uint16_t _3209 = (uint16_t)(245); + _curvea0[895] = _3209; + uint16_t _3210 = (uint16_t)(245); + _curvea0[896] = _3210; + uint16_t _3211 = (uint16_t)(245); + _curvea0[897] = _3211; + uint16_t _3212 = (uint16_t)(245); + _curvea0[898] = _3212; + uint16_t _3213 = (uint16_t)(245); + _curvea0[899] = _3213; + uint16_t _3214 = (uint16_t)(245); + _curvea0[900] = _3214; + uint16_t _3215 = (uint16_t)(245); + _curvea0[901] = _3215; + uint16_t _3216 = (uint16_t)(245); + _curvea0[902] = _3216; + uint16_t _3217 = (uint16_t)(246); + _curvea0[903] = _3217; + uint16_t _3218 = (uint16_t)(246); + _curvea0[904] = _3218; + uint16_t _3219 = (uint16_t)(246); + _curvea0[905] = _3219; + uint16_t _3220 = (uint16_t)(246); + _curvea0[906] = _3220; + uint16_t _3221 = (uint16_t)(246); + _curvea0[907] = _3221; + uint16_t _3222 = (uint16_t)(246); + _curvea0[908] = _3222; + uint16_t _3223 = (uint16_t)(246); + _curvea0[909] = _3223; + uint16_t _3224 = (uint16_t)(246); + _curvea0[910] = _3224; + uint16_t _3225 = (uint16_t)(246); + _curvea0[911] = _3225; + uint16_t _3226 = (uint16_t)(246); + _curvea0[912] = _3226; + uint16_t _3227 = (uint16_t)(246); + _curvea0[913] = _3227; + uint16_t _3228 = (uint16_t)(247); + _curvea0[914] = _3228; + uint16_t _3229 = (uint16_t)(247); + _curvea0[915] = _3229; + uint16_t _3230 = (uint16_t)(247); + _curvea0[916] = _3230; + uint16_t _3231 = (uint16_t)(247); + _curvea0[917] = _3231; + uint16_t _3232 = (uint16_t)(247); + _curvea0[918] = _3232; + uint16_t _3233 = (uint16_t)(247); + _curvea0[919] = _3233; + uint16_t _3234 = (uint16_t)(247); + _curvea0[920] = _3234; + uint16_t _3235 = (uint16_t)(247); + _curvea0[921] = _3235; + uint16_t _3236 = (uint16_t)(247); + _curvea0[922] = _3236; + uint16_t _3237 = (uint16_t)(247); + _curvea0[923] = _3237; + uint16_t _3238 = (uint16_t)(247); + _curvea0[924] = _3238; + uint16_t _3239 = (uint16_t)(248); + _curvea0[925] = _3239; + uint16_t _3240 = (uint16_t)(248); + _curvea0[926] = _3240; + uint16_t _3241 = (uint16_t)(248); + _curvea0[927] = _3241; + uint16_t _3242 = (uint16_t)(248); + _curvea0[928] = _3242; + uint16_t _3243 = (uint16_t)(248); + _curvea0[929] = _3243; + uint16_t _3244 = (uint16_t)(248); + _curvea0[930] = _3244; + uint16_t _3245 = (uint16_t)(248); + _curvea0[931] = _3245; + uint16_t _3246 = (uint16_t)(248); + _curvea0[932] = _3246; + uint16_t _3247 = (uint16_t)(248); + _curvea0[933] = _3247; + uint16_t _3248 = (uint16_t)(248); + _curvea0[934] = _3248; + uint16_t _3249 = (uint16_t)(248); + _curvea0[935] = _3249; + uint16_t _3250 = (uint16_t)(249); + _curvea0[936] = _3250; + uint16_t _3251 = (uint16_t)(249); + _curvea0[937] = _3251; + uint16_t _3252 = (uint16_t)(249); + _curvea0[938] = _3252; + uint16_t _3253 = (uint16_t)(249); + _curvea0[939] = _3253; + uint16_t _3254 = (uint16_t)(249); + _curvea0[940] = _3254; + uint16_t _3255 = (uint16_t)(249); + _curvea0[941] = _3255; + uint16_t _3256 = (uint16_t)(249); + _curvea0[942] = _3256; + uint16_t _3257 = (uint16_t)(249); + _curvea0[943] = _3257; + uint16_t _3258 = (uint16_t)(249); + _curvea0[944] = _3258; + uint16_t _3259 = (uint16_t)(249); + _curvea0[945] = _3259; + uint16_t _3260 = (uint16_t)(249); + _curvea0[946] = _3260; + uint16_t _3261 = (uint16_t)(249); + _curvea0[947] = _3261; + uint16_t _3262 = (uint16_t)(250); + _curvea0[948] = _3262; + uint16_t _3263 = (uint16_t)(250); + _curvea0[949] = _3263; + uint16_t _3264 = (uint16_t)(250); + _curvea0[950] = _3264; + uint16_t _3265 = (uint16_t)(250); + _curvea0[951] = _3265; + uint16_t _3266 = (uint16_t)(250); + _curvea0[952] = _3266; + uint16_t _3267 = (uint16_t)(250); + _curvea0[953] = _3267; + uint16_t _3268 = (uint16_t)(250); + _curvea0[954] = _3268; + uint16_t _3269 = (uint16_t)(250); + _curvea0[955] = _3269; + uint16_t _3270 = (uint16_t)(250); + _curvea0[956] = _3270; + uint16_t _3271 = (uint16_t)(250); + _curvea0[957] = _3271; + uint16_t _3272 = (uint16_t)(250); + _curvea0[958] = _3272; + uint16_t _3273 = (uint16_t)(250); + _curvea0[959] = _3273; + uint16_t _3274 = (uint16_t)(251); + _curvea0[960] = _3274; + uint16_t _3275 = (uint16_t)(251); + _curvea0[961] = _3275; + uint16_t _3276 = (uint16_t)(251); + _curvea0[962] = _3276; + uint16_t _3277 = (uint16_t)(251); + _curvea0[963] = _3277; + uint16_t _3278 = (uint16_t)(251); + _curvea0[964] = _3278; + uint16_t _3279 = (uint16_t)(251); + _curvea0[965] = _3279; + uint16_t _3280 = (uint16_t)(251); + _curvea0[966] = _3280; + uint16_t _3281 = (uint16_t)(251); + _curvea0[967] = _3281; + uint16_t _3282 = (uint16_t)(251); + _curvea0[968] = _3282; + uint16_t _3283 = (uint16_t)(251); + _curvea0[969] = _3283; + uint16_t _3284 = (uint16_t)(251); + _curvea0[970] = _3284; + uint16_t _3285 = (uint16_t)(251); + _curvea0[971] = _3285; + uint16_t _3286 = (uint16_t)(252); + _curvea0[972] = _3286; + uint16_t _3287 = (uint16_t)(252); + _curvea0[973] = _3287; + uint16_t _3288 = (uint16_t)(252); + _curvea0[974] = _3288; + uint16_t _3289 = (uint16_t)(252); + _curvea0[975] = _3289; + uint16_t _3290 = (uint16_t)(252); + _curvea0[976] = _3290; + uint16_t _3291 = (uint16_t)(252); + _curvea0[977] = _3291; + uint16_t _3292 = (uint16_t)(252); + _curvea0[978] = _3292; + uint16_t _3293 = (uint16_t)(252); + _curvea0[979] = _3293; + uint16_t _3294 = (uint16_t)(252); + _curvea0[980] = _3294; + uint16_t _3295 = (uint16_t)(252); + _curvea0[981] = _3295; + uint16_t _3296 = (uint16_t)(252); + _curvea0[982] = _3296; + uint16_t _3297 = (uint16_t)(252); + _curvea0[983] = _3297; + uint16_t _3298 = (uint16_t)(252); + _curvea0[984] = _3298; + uint16_t _3299 = (uint16_t)(253); + _curvea0[985] = _3299; + uint16_t _3300 = (uint16_t)(253); + _curvea0[986] = _3300; + uint16_t _3301 = (uint16_t)(253); + _curvea0[987] = _3301; + uint16_t _3302 = (uint16_t)(253); + _curvea0[988] = _3302; + uint16_t _3303 = (uint16_t)(253); + _curvea0[989] = _3303; + uint16_t _3304 = (uint16_t)(253); + _curvea0[990] = _3304; + uint16_t _3305 = (uint16_t)(253); + _curvea0[991] = _3305; + uint16_t _3306 = (uint16_t)(253); + _curvea0[992] = _3306; + uint16_t _3307 = (uint16_t)(253); + _curvea0[993] = _3307; + uint16_t _3308 = (uint16_t)(253); + _curvea0[994] = _3308; + uint16_t _3309 = (uint16_t)(253); + _curvea0[995] = _3309; + uint16_t _3310 = (uint16_t)(253); + _curvea0[996] = _3310; + uint16_t _3311 = (uint16_t)(253); + _curvea0[997] = _3311; + uint16_t _3312 = (uint16_t)(254); + _curvea0[998] = _3312; + uint16_t _3313 = (uint16_t)(254); + _curvea0[999] = _3313; + uint16_t _3314 = (uint16_t)(254); + _curvea0[1000] = _3314; + uint16_t _3315 = (uint16_t)(254); + _curvea0[1001] = _3315; + uint16_t _3316 = (uint16_t)(254); + _curvea0[1002] = _3316; + uint16_t _3317 = (uint16_t)(254); + _curvea0[1003] = _3317; + uint16_t _3318 = (uint16_t)(254); + _curvea0[1004] = _3318; + uint16_t _3319 = (uint16_t)(254); + _curvea0[1005] = _3319; + uint16_t _3320 = (uint16_t)(254); + _curvea0[1006] = _3320; + uint16_t _3321 = (uint16_t)(254); + _curvea0[1007] = _3321; + uint16_t _3322 = (uint16_t)(254); + _curvea0[1008] = _3322; + uint16_t _3323 = (uint16_t)(254); + _curvea0[1009] = _3323; + uint16_t _3324 = (uint16_t)(254); + _curvea0[1010] = _3324; + uint16_t _3325 = (uint16_t)(255); + _curvea0[1011] = _3325; + uint16_t _3326 = (uint16_t)(255); + _curvea0[1012] = _3326; + uint16_t _3327 = (uint16_t)(255); + _curvea0[1013] = _3327; + uint16_t _3328 = (uint16_t)(255); + _curvea0[1014] = _3328; + uint16_t _3329 = (uint16_t)(255); + _curvea0[1015] = _3329; + uint16_t _3330 = (uint16_t)(255); + _curvea0[1016] = _3330; + uint16_t _3331 = (uint16_t)(255); + _curvea0[1017] = _3331; + uint16_t _3332 = (uint16_t)(255); + _curvea0[1018] = _3332; + uint16_t _3333 = (uint16_t)(255); + _curvea0[1019] = _3333; + uint16_t _3334 = (uint16_t)(255); + _curvea0[1020] = _3334; + uint16_t _3335 = (uint16_t)(255); + _curvea0[1021] = _3335; + uint16_t _3336 = (uint16_t)(255); + _curvea0[1022] = _3336; + uint16_t _3337 = (uint16_t)(255); + _curvea0[1023] = _3337; + + int16_t _3338 = (int16_t)(1023); + int16_t _3339 = min(_corrected_stencil_1, _3338); + int16_t _3340 = (int16_t)(0); + int16_t _3341 = max(_3339, _3340); + uint16_t _3342 = (uint16_t)(_3341); + int32_t _3343 = (int32_t)(_3342); + uint16_t _3344 = ((const uint16_t *)_curvea0)[_3343]; + return _3344; +} + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), curved_s0_y, 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), curved_s0_y, 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_1(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_2 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _3360 = (uint16_t)(0); + _curvea0[0] = _3360; + uint16_t _3361 = (uint16_t)(4); + _curvea0[1] = _3361; + uint16_t _3362 = (uint16_t)(7); + _curvea0[2] = _3362; + uint16_t _3363 = (uint16_t)(8); + _curvea0[3] = _3363; + uint16_t _3364 = (uint16_t)(10); + _curvea0[4] = _3364; + uint16_t _3365 = (uint16_t)(11); + _curvea0[5] = _3365; + uint16_t _3366 = (uint16_t)(12); + _curvea0[6] = _3366; + uint16_t _3367 = (uint16_t)(13); + _curvea0[7] = _3367; + uint16_t _3368 = (uint16_t)(14); + _curvea0[8] = _3368; + uint16_t _3369 = (uint16_t)(15); + _curvea0[9] = _3369; + uint16_t _3370 = (uint16_t)(16); + _curvea0[10] = _3370; + uint16_t _3371 = (uint16_t)(17); + _curvea0[11] = _3371; + uint16_t _3372 = (uint16_t)(18); + _curvea0[12] = _3372; + uint16_t _3373 = (uint16_t)(19); + _curvea0[13] = _3373; + uint16_t _3374 = (uint16_t)(20); + _curvea0[14] = _3374; + uint16_t _3375 = (uint16_t)(21); + _curvea0[15] = _3375; + uint16_t _3376 = (uint16_t)(22); + _curvea0[16] = _3376; + uint16_t _3377 = (uint16_t)(22); + _curvea0[17] = _3377; + uint16_t _3378 = (uint16_t)(23); + _curvea0[18] = _3378; + uint16_t _3379 = (uint16_t)(24); + _curvea0[19] = _3379; + uint16_t _3380 = (uint16_t)(25); + _curvea0[20] = _3380; + uint16_t _3381 = (uint16_t)(25); + _curvea0[21] = _3381; + uint16_t _3382 = (uint16_t)(26); + _curvea0[22] = _3382; + uint16_t _3383 = (uint16_t)(27); + _curvea0[23] = _3383; + uint16_t _3384 = (uint16_t)(27); + _curvea0[24] = _3384; + uint16_t _3385 = (uint16_t)(28); + _curvea0[25] = _3385; + uint16_t _3386 = (uint16_t)(29); + _curvea0[26] = _3386; + uint16_t _3387 = (uint16_t)(29); + _curvea0[27] = _3387; + uint16_t _3388 = (uint16_t)(30); + _curvea0[28] = _3388; + uint16_t _3389 = (uint16_t)(31); + _curvea0[29] = _3389; + uint16_t _3390 = (uint16_t)(31); + _curvea0[30] = _3390; + uint16_t _3391 = (uint16_t)(32); + _curvea0[31] = _3391; + uint16_t _3392 = (uint16_t)(33); + _curvea0[32] = _3392; + uint16_t _3393 = (uint16_t)(33); + _curvea0[33] = _3393; + uint16_t _3394 = (uint16_t)(34); + _curvea0[34] = _3394; + uint16_t _3395 = (uint16_t)(34); + _curvea0[35] = _3395; + uint16_t _3396 = (uint16_t)(35); + _curvea0[36] = _3396; + uint16_t _3397 = (uint16_t)(36); + _curvea0[37] = _3397; + uint16_t _3398 = (uint16_t)(36); + _curvea0[38] = _3398; + uint16_t _3399 = (uint16_t)(37); + _curvea0[39] = _3399; + uint16_t _3400 = (uint16_t)(37); + _curvea0[40] = _3400; + uint16_t _3401 = (uint16_t)(38); + _curvea0[41] = _3401; + uint16_t _3402 = (uint16_t)(39); + _curvea0[42] = _3402; + uint16_t _3403 = (uint16_t)(39); + _curvea0[43] = _3403; + uint16_t _3404 = (uint16_t)(40); + _curvea0[44] = _3404; + uint16_t _3405 = (uint16_t)(40); + _curvea0[45] = _3405; + uint16_t _3406 = (uint16_t)(41); + _curvea0[46] = _3406; + uint16_t _3407 = (uint16_t)(41); + _curvea0[47] = _3407; + uint16_t _3408 = (uint16_t)(42); + _curvea0[48] = _3408; + uint16_t _3409 = (uint16_t)(42); + _curvea0[49] = _3409; + uint16_t _3410 = (uint16_t)(43); + _curvea0[50] = _3410; + uint16_t _3411 = (uint16_t)(44); + _curvea0[51] = _3411; + uint16_t _3412 = (uint16_t)(44); + _curvea0[52] = _3412; + uint16_t _3413 = (uint16_t)(45); + _curvea0[53] = _3413; + uint16_t _3414 = (uint16_t)(45); + _curvea0[54] = _3414; + uint16_t _3415 = (uint16_t)(46); + _curvea0[55] = _3415; + uint16_t _3416 = (uint16_t)(46); + _curvea0[56] = _3416; + uint16_t _3417 = (uint16_t)(47); + _curvea0[57] = _3417; + uint16_t _3418 = (uint16_t)(47); + _curvea0[58] = _3418; + uint16_t _3419 = (uint16_t)(48); + _curvea0[59] = _3419; + uint16_t _3420 = (uint16_t)(48); + _curvea0[60] = _3420; + uint16_t _3421 = (uint16_t)(49); + _curvea0[61] = _3421; + uint16_t _3422 = (uint16_t)(49); + _curvea0[62] = _3422; + uint16_t _3423 = (uint16_t)(50); + _curvea0[63] = _3423; + uint16_t _3424 = (uint16_t)(50); + _curvea0[64] = _3424; + uint16_t _3425 = (uint16_t)(51); + _curvea0[65] = _3425; + uint16_t _3426 = (uint16_t)(51); + _curvea0[66] = _3426; + uint16_t _3427 = (uint16_t)(52); + _curvea0[67] = _3427; + uint16_t _3428 = (uint16_t)(52); + _curvea0[68] = _3428; + uint16_t _3429 = (uint16_t)(53); + _curvea0[69] = _3429; + uint16_t _3430 = (uint16_t)(53); + _curvea0[70] = _3430; + uint16_t _3431 = (uint16_t)(54); + _curvea0[71] = _3431; + uint16_t _3432 = (uint16_t)(54); + _curvea0[72] = _3432; + uint16_t _3433 = (uint16_t)(55); + _curvea0[73] = _3433; + uint16_t _3434 = (uint16_t)(55); + _curvea0[74] = _3434; + uint16_t _3435 = (uint16_t)(56); + _curvea0[75] = _3435; + uint16_t _3436 = (uint16_t)(56); + _curvea0[76] = _3436; + uint16_t _3437 = (uint16_t)(57); + _curvea0[77] = _3437; + uint16_t _3438 = (uint16_t)(57); + _curvea0[78] = _3438; + uint16_t _3439 = (uint16_t)(58); + _curvea0[79] = _3439; + uint16_t _3440 = (uint16_t)(58); + _curvea0[80] = _3440; + uint16_t _3441 = (uint16_t)(58); + _curvea0[81] = _3441; + uint16_t _3442 = (uint16_t)(59); + _curvea0[82] = _3442; + uint16_t _3443 = (uint16_t)(59); + _curvea0[83] = _3443; + uint16_t _3444 = (uint16_t)(60); + _curvea0[84] = _3444; + uint16_t _3445 = (uint16_t)(60); + _curvea0[85] = _3445; + uint16_t _3446 = (uint16_t)(61); + _curvea0[86] = _3446; + uint16_t _3447 = (uint16_t)(61); + _curvea0[87] = _3447; + uint16_t _3448 = (uint16_t)(62); + _curvea0[88] = _3448; + uint16_t _3449 = (uint16_t)(62); + _curvea0[89] = _3449; + uint16_t _3450 = (uint16_t)(63); + _curvea0[90] = _3450; + uint16_t _3451 = (uint16_t)(63); + _curvea0[91] = _3451; + uint16_t _3452 = (uint16_t)(64); + _curvea0[92] = _3452; + uint16_t _3453 = (uint16_t)(64); + _curvea0[93] = _3453; + uint16_t _3454 = (uint16_t)(64); + _curvea0[94] = _3454; + uint16_t _3455 = (uint16_t)(65); + _curvea0[95] = _3455; + uint16_t _3456 = (uint16_t)(65); + _curvea0[96] = _3456; + uint16_t _3457 = (uint16_t)(66); + _curvea0[97] = _3457; + uint16_t _3458 = (uint16_t)(66); + _curvea0[98] = _3458; + uint16_t _3459 = (uint16_t)(67); + _curvea0[99] = _3459; + uint16_t _3460 = (uint16_t)(67); + _curvea0[100] = _3460; + uint16_t _3461 = (uint16_t)(68); + _curvea0[101] = _3461; + uint16_t _3462 = (uint16_t)(68); + _curvea0[102] = _3462; + uint16_t _3463 = (uint16_t)(68); + _curvea0[103] = _3463; + uint16_t _3464 = (uint16_t)(69); + _curvea0[104] = _3464; + uint16_t _3465 = (uint16_t)(69); + _curvea0[105] = _3465; + uint16_t _3466 = (uint16_t)(70); + _curvea0[106] = _3466; + uint16_t _3467 = (uint16_t)(70); + _curvea0[107] = _3467; + uint16_t _3468 = (uint16_t)(71); + _curvea0[108] = _3468; + uint16_t _3469 = (uint16_t)(71); + _curvea0[109] = _3469; + uint16_t _3470 = (uint16_t)(71); + _curvea0[110] = _3470; + uint16_t _3471 = (uint16_t)(72); + _curvea0[111] = _3471; + uint16_t _3472 = (uint16_t)(72); + _curvea0[112] = _3472; + uint16_t _3473 = (uint16_t)(73); + _curvea0[113] = _3473; + uint16_t _3474 = (uint16_t)(73); + _curvea0[114] = _3474; + uint16_t _3475 = (uint16_t)(74); + _curvea0[115] = _3475; + uint16_t _3476 = (uint16_t)(74); + _curvea0[116] = _3476; + uint16_t _3477 = (uint16_t)(74); + _curvea0[117] = _3477; + uint16_t _3478 = (uint16_t)(75); + _curvea0[118] = _3478; + uint16_t _3479 = (uint16_t)(75); + _curvea0[119] = _3479; + uint16_t _3480 = (uint16_t)(76); + _curvea0[120] = _3480; + uint16_t _3481 = (uint16_t)(76); + _curvea0[121] = _3481; + uint16_t _3482 = (uint16_t)(77); + _curvea0[122] = _3482; + uint16_t _3483 = (uint16_t)(77); + _curvea0[123] = _3483; + uint16_t _3484 = (uint16_t)(77); + _curvea0[124] = _3484; + uint16_t _3485 = (uint16_t)(78); + _curvea0[125] = _3485; + uint16_t _3486 = (uint16_t)(78); + _curvea0[126] = _3486; + uint16_t _3487 = (uint16_t)(79); + _curvea0[127] = _3487; + uint16_t _3488 = (uint16_t)(79); + _curvea0[128] = _3488; + uint16_t _3489 = (uint16_t)(79); + _curvea0[129] = _3489; + uint16_t _3490 = (uint16_t)(80); + _curvea0[130] = _3490; + uint16_t _3491 = (uint16_t)(80); + _curvea0[131] = _3491; + uint16_t _3492 = (uint16_t)(81); + _curvea0[132] = _3492; + uint16_t _3493 = (uint16_t)(81); + _curvea0[133] = _3493; + uint16_t _3494 = (uint16_t)(82); + _curvea0[134] = _3494; + uint16_t _3495 = (uint16_t)(82); + _curvea0[135] = _3495; + uint16_t _3496 = (uint16_t)(82); + _curvea0[136] = _3496; + uint16_t _3497 = (uint16_t)(83); + _curvea0[137] = _3497; + uint16_t _3498 = (uint16_t)(83); + _curvea0[138] = _3498; + uint16_t _3499 = (uint16_t)(84); + _curvea0[139] = _3499; + uint16_t _3500 = (uint16_t)(84); + _curvea0[140] = _3500; + uint16_t _3501 = (uint16_t)(84); + _curvea0[141] = _3501; + uint16_t _3502 = (uint16_t)(85); + _curvea0[142] = _3502; + uint16_t _3503 = (uint16_t)(85); + _curvea0[143] = _3503; + uint16_t _3504 = (uint16_t)(86); + _curvea0[144] = _3504; + uint16_t _3505 = (uint16_t)(86); + _curvea0[145] = _3505; + uint16_t _3506 = (uint16_t)(86); + _curvea0[146] = _3506; + uint16_t _3507 = (uint16_t)(87); + _curvea0[147] = _3507; + uint16_t _3508 = (uint16_t)(87); + _curvea0[148] = _3508; + uint16_t _3509 = (uint16_t)(88); + _curvea0[149] = _3509; + uint16_t _3510 = (uint16_t)(88); + _curvea0[150] = _3510; + uint16_t _3511 = (uint16_t)(88); + _curvea0[151] = _3511; + uint16_t _3512 = (uint16_t)(89); + _curvea0[152] = _3512; + uint16_t _3513 = (uint16_t)(89); + _curvea0[153] = _3513; + uint16_t _3514 = (uint16_t)(90); + _curvea0[154] = _3514; + uint16_t _3515 = (uint16_t)(90); + _curvea0[155] = _3515; + uint16_t _3516 = (uint16_t)(90); + _curvea0[156] = _3516; + uint16_t _3517 = (uint16_t)(91); + _curvea0[157] = _3517; + uint16_t _3518 = (uint16_t)(91); + _curvea0[158] = _3518; + uint16_t _3519 = (uint16_t)(92); + _curvea0[159] = _3519; + uint16_t _3520 = (uint16_t)(92); + _curvea0[160] = _3520; + uint16_t _3521 = (uint16_t)(92); + _curvea0[161] = _3521; + uint16_t _3522 = (uint16_t)(93); + _curvea0[162] = _3522; + uint16_t _3523 = (uint16_t)(93); + _curvea0[163] = _3523; + uint16_t _3524 = (uint16_t)(93); + _curvea0[164] = _3524; + uint16_t _3525 = (uint16_t)(94); + _curvea0[165] = _3525; + uint16_t _3526 = (uint16_t)(94); + _curvea0[166] = _3526; + uint16_t _3527 = (uint16_t)(95); + _curvea0[167] = _3527; + uint16_t _3528 = (uint16_t)(95); + _curvea0[168] = _3528; + uint16_t _3529 = (uint16_t)(95); + _curvea0[169] = _3529; + uint16_t _3530 = (uint16_t)(96); + _curvea0[170] = _3530; + uint16_t _3531 = (uint16_t)(96); + _curvea0[171] = _3531; + uint16_t _3532 = (uint16_t)(97); + _curvea0[172] = _3532; + uint16_t _3533 = (uint16_t)(97); + _curvea0[173] = _3533; + uint16_t _3534 = (uint16_t)(97); + _curvea0[174] = _3534; + uint16_t _3535 = (uint16_t)(98); + _curvea0[175] = _3535; + uint16_t _3536 = (uint16_t)(98); + _curvea0[176] = _3536; + uint16_t _3537 = (uint16_t)(99); + _curvea0[177] = _3537; + uint16_t _3538 = (uint16_t)(99); + _curvea0[178] = _3538; + uint16_t _3539 = (uint16_t)(99); + _curvea0[179] = _3539; + uint16_t _3540 = (uint16_t)(100); + _curvea0[180] = _3540; + uint16_t _3541 = (uint16_t)(100); + _curvea0[181] = _3541; + uint16_t _3542 = (uint16_t)(100); + _curvea0[182] = _3542; + uint16_t _3543 = (uint16_t)(101); + _curvea0[183] = _3543; + uint16_t _3544 = (uint16_t)(101); + _curvea0[184] = _3544; + uint16_t _3545 = (uint16_t)(102); + _curvea0[185] = _3545; + uint16_t _3546 = (uint16_t)(102); + _curvea0[186] = _3546; + uint16_t _3547 = (uint16_t)(102); + _curvea0[187] = _3547; + uint16_t _3548 = (uint16_t)(103); + _curvea0[188] = _3548; + uint16_t _3549 = (uint16_t)(103); + _curvea0[189] = _3549; + uint16_t _3550 = (uint16_t)(103); + _curvea0[190] = _3550; + uint16_t _3551 = (uint16_t)(104); + _curvea0[191] = _3551; + uint16_t _3552 = (uint16_t)(104); + _curvea0[192] = _3552; + uint16_t _3553 = (uint16_t)(105); + _curvea0[193] = _3553; + uint16_t _3554 = (uint16_t)(105); + _curvea0[194] = _3554; + uint16_t _3555 = (uint16_t)(105); + _curvea0[195] = _3555; + uint16_t _3556 = (uint16_t)(106); + _curvea0[196] = _3556; + uint16_t _3557 = (uint16_t)(106); + _curvea0[197] = _3557; + uint16_t _3558 = (uint16_t)(106); + _curvea0[198] = _3558; + uint16_t _3559 = (uint16_t)(107); + _curvea0[199] = _3559; + uint16_t _3560 = (uint16_t)(107); + _curvea0[200] = _3560; + uint16_t _3561 = (uint16_t)(108); + _curvea0[201] = _3561; + uint16_t _3562 = (uint16_t)(108); + _curvea0[202] = _3562; + uint16_t _3563 = (uint16_t)(108); + _curvea0[203] = _3563; + uint16_t _3564 = (uint16_t)(109); + _curvea0[204] = _3564; + uint16_t _3565 = (uint16_t)(109); + _curvea0[205] = _3565; + uint16_t _3566 = (uint16_t)(109); + _curvea0[206] = _3566; + uint16_t _3567 = (uint16_t)(110); + _curvea0[207] = _3567; + uint16_t _3568 = (uint16_t)(110); + _curvea0[208] = _3568; + uint16_t _3569 = (uint16_t)(111); + _curvea0[209] = _3569; + uint16_t _3570 = (uint16_t)(111); + _curvea0[210] = _3570; + uint16_t _3571 = (uint16_t)(111); + _curvea0[211] = _3571; + uint16_t _3572 = (uint16_t)(112); + _curvea0[212] = _3572; + uint16_t _3573 = (uint16_t)(112); + _curvea0[213] = _3573; + uint16_t _3574 = (uint16_t)(112); + _curvea0[214] = _3574; + uint16_t _3575 = (uint16_t)(113); + _curvea0[215] = _3575; + uint16_t _3576 = (uint16_t)(113); + _curvea0[216] = _3576; + uint16_t _3577 = (uint16_t)(113); + _curvea0[217] = _3577; + uint16_t _3578 = (uint16_t)(114); + _curvea0[218] = _3578; + uint16_t _3579 = (uint16_t)(114); + _curvea0[219] = _3579; + uint16_t _3580 = (uint16_t)(115); + _curvea0[220] = _3580; + uint16_t _3581 = (uint16_t)(115); + _curvea0[221] = _3581; + uint16_t _3582 = (uint16_t)(115); + _curvea0[222] = _3582; + uint16_t _3583 = (uint16_t)(116); + _curvea0[223] = _3583; + uint16_t _3584 = (uint16_t)(116); + _curvea0[224] = _3584; + uint16_t _3585 = (uint16_t)(116); + _curvea0[225] = _3585; + uint16_t _3586 = (uint16_t)(117); + _curvea0[226] = _3586; + uint16_t _3587 = (uint16_t)(117); + _curvea0[227] = _3587; + uint16_t _3588 = (uint16_t)(117); + _curvea0[228] = _3588; + uint16_t _3589 = (uint16_t)(118); + _curvea0[229] = _3589; + uint16_t _3590 = (uint16_t)(118); + _curvea0[230] = _3590; + uint16_t _3591 = (uint16_t)(119); + _curvea0[231] = _3591; + uint16_t _3592 = (uint16_t)(119); + _curvea0[232] = _3592; + uint16_t _3593 = (uint16_t)(119); + _curvea0[233] = _3593; + uint16_t _3594 = (uint16_t)(120); + _curvea0[234] = _3594; + uint16_t _3595 = (uint16_t)(120); + _curvea0[235] = _3595; + uint16_t _3596 = (uint16_t)(120); + _curvea0[236] = _3596; + uint16_t _3597 = (uint16_t)(121); + _curvea0[237] = _3597; + uint16_t _3598 = (uint16_t)(121); + _curvea0[238] = _3598; + uint16_t _3599 = (uint16_t)(121); + _curvea0[239] = _3599; + uint16_t _3600 = (uint16_t)(122); + _curvea0[240] = _3600; + uint16_t _3601 = (uint16_t)(122); + _curvea0[241] = _3601; + uint16_t _3602 = (uint16_t)(123); + _curvea0[242] = _3602; + uint16_t _3603 = (uint16_t)(123); + _curvea0[243] = _3603; + uint16_t _3604 = (uint16_t)(123); + _curvea0[244] = _3604; + uint16_t _3605 = (uint16_t)(124); + _curvea0[245] = _3605; + uint16_t _3606 = (uint16_t)(124); + _curvea0[246] = _3606; + uint16_t _3607 = (uint16_t)(124); + _curvea0[247] = _3607; + uint16_t _3608 = (uint16_t)(125); + _curvea0[248] = _3608; + uint16_t _3609 = (uint16_t)(125); + _curvea0[249] = _3609; + uint16_t _3610 = (uint16_t)(125); + _curvea0[250] = _3610; + uint16_t _3611 = (uint16_t)(126); + _curvea0[251] = _3611; + uint16_t _3612 = (uint16_t)(126); + _curvea0[252] = _3612; + uint16_t _3613 = (uint16_t)(126); + _curvea0[253] = _3613; + uint16_t _3614 = (uint16_t)(127); + _curvea0[254] = _3614; + uint16_t _3615 = (uint16_t)(127); + _curvea0[255] = _3615; + uint16_t _3616 = (uint16_t)(128); + _curvea0[256] = _3616; + uint16_t _3617 = (uint16_t)(128); + _curvea0[257] = _3617; + uint16_t _3618 = (uint16_t)(128); + _curvea0[258] = _3618; + uint16_t _3619 = (uint16_t)(129); + _curvea0[259] = _3619; + uint16_t _3620 = (uint16_t)(129); + _curvea0[260] = _3620; + uint16_t _3621 = (uint16_t)(129); + _curvea0[261] = _3621; + uint16_t _3622 = (uint16_t)(130); + _curvea0[262] = _3622; + uint16_t _3623 = (uint16_t)(130); + _curvea0[263] = _3623; + uint16_t _3624 = (uint16_t)(130); + _curvea0[264] = _3624; + uint16_t _3625 = (uint16_t)(131); + _curvea0[265] = _3625; + uint16_t _3626 = (uint16_t)(131); + _curvea0[266] = _3626; + uint16_t _3627 = (uint16_t)(131); + _curvea0[267] = _3627; + uint16_t _3628 = (uint16_t)(132); + _curvea0[268] = _3628; + uint16_t _3629 = (uint16_t)(132); + _curvea0[269] = _3629; + uint16_t _3630 = (uint16_t)(132); + _curvea0[270] = _3630; + uint16_t _3631 = (uint16_t)(133); + _curvea0[271] = _3631; + uint16_t _3632 = (uint16_t)(133); + _curvea0[272] = _3632; + uint16_t _3633 = (uint16_t)(133); + _curvea0[273] = _3633; + uint16_t _3634 = (uint16_t)(134); + _curvea0[274] = _3634; + uint16_t _3635 = (uint16_t)(134); + _curvea0[275] = _3635; + uint16_t _3636 = (uint16_t)(134); + _curvea0[276] = _3636; + uint16_t _3637 = (uint16_t)(135); + _curvea0[277] = _3637; + uint16_t _3638 = (uint16_t)(135); + _curvea0[278] = _3638; + uint16_t _3639 = (uint16_t)(135); + _curvea0[279] = _3639; + uint16_t _3640 = (uint16_t)(136); + _curvea0[280] = _3640; + uint16_t _3641 = (uint16_t)(136); + _curvea0[281] = _3641; + uint16_t _3642 = (uint16_t)(136); + _curvea0[282] = _3642; + uint16_t _3643 = (uint16_t)(137); + _curvea0[283] = _3643; + uint16_t _3644 = (uint16_t)(137); + _curvea0[284] = _3644; + uint16_t _3645 = (uint16_t)(137); + _curvea0[285] = _3645; + uint16_t _3646 = (uint16_t)(138); + _curvea0[286] = _3646; + uint16_t _3647 = (uint16_t)(138); + _curvea0[287] = _3647; + uint16_t _3648 = (uint16_t)(138); + _curvea0[288] = _3648; + uint16_t _3649 = (uint16_t)(139); + _curvea0[289] = _3649; + uint16_t _3650 = (uint16_t)(139); + _curvea0[290] = _3650; + uint16_t _3651 = (uint16_t)(139); + _curvea0[291] = _3651; + uint16_t _3652 = (uint16_t)(140); + _curvea0[292] = _3652; + uint16_t _3653 = (uint16_t)(140); + _curvea0[293] = _3653; + uint16_t _3654 = (uint16_t)(140); + _curvea0[294] = _3654; + uint16_t _3655 = (uint16_t)(141); + _curvea0[295] = _3655; + uint16_t _3656 = (uint16_t)(141); + _curvea0[296] = _3656; + uint16_t _3657 = (uint16_t)(141); + _curvea0[297] = _3657; + uint16_t _3658 = (uint16_t)(141); + _curvea0[298] = _3658; + uint16_t _3659 = (uint16_t)(142); + _curvea0[299] = _3659; + uint16_t _3660 = (uint16_t)(142); + _curvea0[300] = _3660; + uint16_t _3661 = (uint16_t)(142); + _curvea0[301] = _3661; + uint16_t _3662 = (uint16_t)(143); + _curvea0[302] = _3662; + uint16_t _3663 = (uint16_t)(143); + _curvea0[303] = _3663; + uint16_t _3664 = (uint16_t)(143); + _curvea0[304] = _3664; + uint16_t _3665 = (uint16_t)(144); + _curvea0[305] = _3665; + uint16_t _3666 = (uint16_t)(144); + _curvea0[306] = _3666; + uint16_t _3667 = (uint16_t)(144); + _curvea0[307] = _3667; + uint16_t _3668 = (uint16_t)(145); + _curvea0[308] = _3668; + uint16_t _3669 = (uint16_t)(145); + _curvea0[309] = _3669; + uint16_t _3670 = (uint16_t)(145); + _curvea0[310] = _3670; + uint16_t _3671 = (uint16_t)(145); + _curvea0[311] = _3671; + uint16_t _3672 = (uint16_t)(146); + _curvea0[312] = _3672; + uint16_t _3673 = (uint16_t)(146); + _curvea0[313] = _3673; + uint16_t _3674 = (uint16_t)(146); + _curvea0[314] = _3674; + uint16_t _3675 = (uint16_t)(147); + _curvea0[315] = _3675; + uint16_t _3676 = (uint16_t)(147); + _curvea0[316] = _3676; + uint16_t _3677 = (uint16_t)(147); + _curvea0[317] = _3677; + uint16_t _3678 = (uint16_t)(148); + _curvea0[318] = _3678; + uint16_t _3679 = (uint16_t)(148); + _curvea0[319] = _3679; + uint16_t _3680 = (uint16_t)(148); + _curvea0[320] = _3680; + uint16_t _3681 = (uint16_t)(148); + _curvea0[321] = _3681; + uint16_t _3682 = (uint16_t)(149); + _curvea0[322] = _3682; + uint16_t _3683 = (uint16_t)(149); + _curvea0[323] = _3683; + uint16_t _3684 = (uint16_t)(149); + _curvea0[324] = _3684; + uint16_t _3685 = (uint16_t)(150); + _curvea0[325] = _3685; + uint16_t _3686 = (uint16_t)(150); + _curvea0[326] = _3686; + uint16_t _3687 = (uint16_t)(150); + _curvea0[327] = _3687; + uint16_t _3688 = (uint16_t)(150); + _curvea0[328] = _3688; + uint16_t _3689 = (uint16_t)(151); + _curvea0[329] = _3689; + uint16_t _3690 = (uint16_t)(151); + _curvea0[330] = _3690; + uint16_t _3691 = (uint16_t)(151); + _curvea0[331] = _3691; + uint16_t _3692 = (uint16_t)(152); + _curvea0[332] = _3692; + uint16_t _3693 = (uint16_t)(152); + _curvea0[333] = _3693; + uint16_t _3694 = (uint16_t)(152); + _curvea0[334] = _3694; + uint16_t _3695 = (uint16_t)(152); + _curvea0[335] = _3695; + uint16_t _3696 = (uint16_t)(153); + _curvea0[336] = _3696; + uint16_t _3697 = (uint16_t)(153); + _curvea0[337] = _3697; + uint16_t _3698 = (uint16_t)(153); + _curvea0[338] = _3698; + uint16_t _3699 = (uint16_t)(154); + _curvea0[339] = _3699; + uint16_t _3700 = (uint16_t)(154); + _curvea0[340] = _3700; + uint16_t _3701 = (uint16_t)(154); + _curvea0[341] = _3701; + uint16_t _3702 = (uint16_t)(154); + _curvea0[342] = _3702; + uint16_t _3703 = (uint16_t)(155); + _curvea0[343] = _3703; + uint16_t _3704 = (uint16_t)(155); + _curvea0[344] = _3704; + uint16_t _3705 = (uint16_t)(155); + _curvea0[345] = _3705; + uint16_t _3706 = (uint16_t)(156); + _curvea0[346] = _3706; + uint16_t _3707 = (uint16_t)(156); + _curvea0[347] = _3707; + uint16_t _3708 = (uint16_t)(156); + _curvea0[348] = _3708; + uint16_t _3709 = (uint16_t)(156); + _curvea0[349] = _3709; + uint16_t _3710 = (uint16_t)(157); + _curvea0[350] = _3710; + uint16_t _3711 = (uint16_t)(157); + _curvea0[351] = _3711; + uint16_t _3712 = (uint16_t)(157); + _curvea0[352] = _3712; + uint16_t _3713 = (uint16_t)(157); + _curvea0[353] = _3713; + uint16_t _3714 = (uint16_t)(158); + _curvea0[354] = _3714; + uint16_t _3715 = (uint16_t)(158); + _curvea0[355] = _3715; + uint16_t _3716 = (uint16_t)(158); + _curvea0[356] = _3716; + uint16_t _3717 = (uint16_t)(159); + _curvea0[357] = _3717; + uint16_t _3718 = (uint16_t)(159); + _curvea0[358] = _3718; + uint16_t _3719 = (uint16_t)(159); + _curvea0[359] = _3719; + uint16_t _3720 = (uint16_t)(159); + _curvea0[360] = _3720; + uint16_t _3721 = (uint16_t)(160); + _curvea0[361] = _3721; + uint16_t _3722 = (uint16_t)(160); + _curvea0[362] = _3722; + uint16_t _3723 = (uint16_t)(160); + _curvea0[363] = _3723; + uint16_t _3724 = (uint16_t)(160); + _curvea0[364] = _3724; + uint16_t _3725 = (uint16_t)(161); + _curvea0[365] = _3725; + uint16_t _3726 = (uint16_t)(161); + _curvea0[366] = _3726; + uint16_t _3727 = (uint16_t)(161); + _curvea0[367] = _3727; + uint16_t _3728 = (uint16_t)(161); + _curvea0[368] = _3728; + uint16_t _3729 = (uint16_t)(162); + _curvea0[369] = _3729; + uint16_t _3730 = (uint16_t)(162); + _curvea0[370] = _3730; + uint16_t _3731 = (uint16_t)(162); + _curvea0[371] = _3731; + uint16_t _3732 = (uint16_t)(162); + _curvea0[372] = _3732; + uint16_t _3733 = (uint16_t)(163); + _curvea0[373] = _3733; + uint16_t _3734 = (uint16_t)(163); + _curvea0[374] = _3734; + uint16_t _3735 = (uint16_t)(163); + _curvea0[375] = _3735; + uint16_t _3736 = (uint16_t)(163); + _curvea0[376] = _3736; + uint16_t _3737 = (uint16_t)(164); + _curvea0[377] = _3737; + uint16_t _3738 = (uint16_t)(164); + _curvea0[378] = _3738; + uint16_t _3739 = (uint16_t)(164); + _curvea0[379] = _3739; + uint16_t _3740 = (uint16_t)(164); + _curvea0[380] = _3740; + uint16_t _3741 = (uint16_t)(165); + _curvea0[381] = _3741; + uint16_t _3742 = (uint16_t)(165); + _curvea0[382] = _3742; + uint16_t _3743 = (uint16_t)(165); + _curvea0[383] = _3743; + uint16_t _3744 = (uint16_t)(166); + _curvea0[384] = _3744; + uint16_t _3745 = (uint16_t)(166); + _curvea0[385] = _3745; + uint16_t _3746 = (uint16_t)(166); + _curvea0[386] = _3746; + uint16_t _3747 = (uint16_t)(166); + _curvea0[387] = _3747; + uint16_t _3748 = (uint16_t)(167); + _curvea0[388] = _3748; + uint16_t _3749 = (uint16_t)(167); + _curvea0[389] = _3749; + uint16_t _3750 = (uint16_t)(167); + _curvea0[390] = _3750; + uint16_t _3751 = (uint16_t)(167); + _curvea0[391] = _3751; + uint16_t _3752 = (uint16_t)(167); + _curvea0[392] = _3752; + uint16_t _3753 = (uint16_t)(168); + _curvea0[393] = _3753; + uint16_t _3754 = (uint16_t)(168); + _curvea0[394] = _3754; + uint16_t _3755 = (uint16_t)(168); + _curvea0[395] = _3755; + uint16_t _3756 = (uint16_t)(168); + _curvea0[396] = _3756; + uint16_t _3757 = (uint16_t)(169); + _curvea0[397] = _3757; + uint16_t _3758 = (uint16_t)(169); + _curvea0[398] = _3758; + uint16_t _3759 = (uint16_t)(169); + _curvea0[399] = _3759; + uint16_t _3760 = (uint16_t)(169); + _curvea0[400] = _3760; + uint16_t _3761 = (uint16_t)(170); + _curvea0[401] = _3761; + uint16_t _3762 = (uint16_t)(170); + _curvea0[402] = _3762; + uint16_t _3763 = (uint16_t)(170); + _curvea0[403] = _3763; + uint16_t _3764 = (uint16_t)(170); + _curvea0[404] = _3764; + uint16_t _3765 = (uint16_t)(171); + _curvea0[405] = _3765; + uint16_t _3766 = (uint16_t)(171); + _curvea0[406] = _3766; + uint16_t _3767 = (uint16_t)(171); + _curvea0[407] = _3767; + uint16_t _3768 = (uint16_t)(171); + _curvea0[408] = _3768; + uint16_t _3769 = (uint16_t)(172); + _curvea0[409] = _3769; + uint16_t _3770 = (uint16_t)(172); + _curvea0[410] = _3770; + uint16_t _3771 = (uint16_t)(172); + _curvea0[411] = _3771; + uint16_t _3772 = (uint16_t)(172); + _curvea0[412] = _3772; + uint16_t _3773 = (uint16_t)(173); + _curvea0[413] = _3773; + uint16_t _3774 = (uint16_t)(173); + _curvea0[414] = _3774; + uint16_t _3775 = (uint16_t)(173); + _curvea0[415] = _3775; + uint16_t _3776 = (uint16_t)(173); + _curvea0[416] = _3776; + uint16_t _3777 = (uint16_t)(173); + _curvea0[417] = _3777; + uint16_t _3778 = (uint16_t)(174); + _curvea0[418] = _3778; + uint16_t _3779 = (uint16_t)(174); + _curvea0[419] = _3779; + uint16_t _3780 = (uint16_t)(174); + _curvea0[420] = _3780; + uint16_t _3781 = (uint16_t)(174); + _curvea0[421] = _3781; + uint16_t _3782 = (uint16_t)(175); + _curvea0[422] = _3782; + uint16_t _3783 = (uint16_t)(175); + _curvea0[423] = _3783; + uint16_t _3784 = (uint16_t)(175); + _curvea0[424] = _3784; + uint16_t _3785 = (uint16_t)(175); + _curvea0[425] = _3785; + uint16_t _3786 = (uint16_t)(176); + _curvea0[426] = _3786; + uint16_t _3787 = (uint16_t)(176); + _curvea0[427] = _3787; + uint16_t _3788 = (uint16_t)(176); + _curvea0[428] = _3788; + uint16_t _3789 = (uint16_t)(176); + _curvea0[429] = _3789; + uint16_t _3790 = (uint16_t)(176); + _curvea0[430] = _3790; + uint16_t _3791 = (uint16_t)(177); + _curvea0[431] = _3791; + uint16_t _3792 = (uint16_t)(177); + _curvea0[432] = _3792; + uint16_t _3793 = (uint16_t)(177); + _curvea0[433] = _3793; + uint16_t _3794 = (uint16_t)(177); + _curvea0[434] = _3794; + uint16_t _3795 = (uint16_t)(178); + _curvea0[435] = _3795; + uint16_t _3796 = (uint16_t)(178); + _curvea0[436] = _3796; + uint16_t _3797 = (uint16_t)(178); + _curvea0[437] = _3797; + uint16_t _3798 = (uint16_t)(178); + _curvea0[438] = _3798; + uint16_t _3799 = (uint16_t)(178); + _curvea0[439] = _3799; + uint16_t _3800 = (uint16_t)(179); + _curvea0[440] = _3800; + uint16_t _3801 = (uint16_t)(179); + _curvea0[441] = _3801; + uint16_t _3802 = (uint16_t)(179); + _curvea0[442] = _3802; + uint16_t _3803 = (uint16_t)(179); + _curvea0[443] = _3803; + uint16_t _3804 = (uint16_t)(180); + _curvea0[444] = _3804; + uint16_t _3805 = (uint16_t)(180); + _curvea0[445] = _3805; + uint16_t _3806 = (uint16_t)(180); + _curvea0[446] = _3806; + uint16_t _3807 = (uint16_t)(180); + _curvea0[447] = _3807; + uint16_t _3808 = (uint16_t)(180); + _curvea0[448] = _3808; + uint16_t _3809 = (uint16_t)(181); + _curvea0[449] = _3809; + uint16_t _3810 = (uint16_t)(181); + _curvea0[450] = _3810; + uint16_t _3811 = (uint16_t)(181); + _curvea0[451] = _3811; + uint16_t _3812 = (uint16_t)(181); + _curvea0[452] = _3812; + uint16_t _3813 = (uint16_t)(181); + _curvea0[453] = _3813; + uint16_t _3814 = (uint16_t)(182); + _curvea0[454] = _3814; + uint16_t _3815 = (uint16_t)(182); + _curvea0[455] = _3815; + uint16_t _3816 = (uint16_t)(182); + _curvea0[456] = _3816; + uint16_t _3817 = (uint16_t)(182); + _curvea0[457] = _3817; + uint16_t _3818 = (uint16_t)(183); + _curvea0[458] = _3818; + uint16_t _3819 = (uint16_t)(183); + _curvea0[459] = _3819; + uint16_t _3820 = (uint16_t)(183); + _curvea0[460] = _3820; + uint16_t _3821 = (uint16_t)(183); + _curvea0[461] = _3821; + uint16_t _3822 = (uint16_t)(183); + _curvea0[462] = _3822; + uint16_t _3823 = (uint16_t)(184); + _curvea0[463] = _3823; + uint16_t _3824 = (uint16_t)(184); + _curvea0[464] = _3824; + uint16_t _3825 = (uint16_t)(184); + _curvea0[465] = _3825; + uint16_t _3826 = (uint16_t)(184); + _curvea0[466] = _3826; + uint16_t _3827 = (uint16_t)(184); + _curvea0[467] = _3827; + uint16_t _3828 = (uint16_t)(185); + _curvea0[468] = _3828; + uint16_t _3829 = (uint16_t)(185); + _curvea0[469] = _3829; + uint16_t _3830 = (uint16_t)(185); + _curvea0[470] = _3830; + uint16_t _3831 = (uint16_t)(185); + _curvea0[471] = _3831; + uint16_t _3832 = (uint16_t)(185); + _curvea0[472] = _3832; + uint16_t _3833 = (uint16_t)(186); + _curvea0[473] = _3833; + uint16_t _3834 = (uint16_t)(186); + _curvea0[474] = _3834; + uint16_t _3835 = (uint16_t)(186); + _curvea0[475] = _3835; + uint16_t _3836 = (uint16_t)(186); + _curvea0[476] = _3836; + uint16_t _3837 = (uint16_t)(187); + _curvea0[477] = _3837; + uint16_t _3838 = (uint16_t)(187); + _curvea0[478] = _3838; + uint16_t _3839 = (uint16_t)(187); + _curvea0[479] = _3839; + uint16_t _3840 = (uint16_t)(187); + _curvea0[480] = _3840; + uint16_t _3841 = (uint16_t)(187); + _curvea0[481] = _3841; + uint16_t _3842 = (uint16_t)(188); + _curvea0[482] = _3842; + uint16_t _3843 = (uint16_t)(188); + _curvea0[483] = _3843; + uint16_t _3844 = (uint16_t)(188); + _curvea0[484] = _3844; + uint16_t _3845 = (uint16_t)(188); + _curvea0[485] = _3845; + uint16_t _3846 = (uint16_t)(188); + _curvea0[486] = _3846; + uint16_t _3847 = (uint16_t)(189); + _curvea0[487] = _3847; + uint16_t _3848 = (uint16_t)(189); + _curvea0[488] = _3848; + uint16_t _3849 = (uint16_t)(189); + _curvea0[489] = _3849; + uint16_t _3850 = (uint16_t)(189); + _curvea0[490] = _3850; + uint16_t _3851 = (uint16_t)(189); + _curvea0[491] = _3851; + uint16_t _3852 = (uint16_t)(190); + _curvea0[492] = _3852; + uint16_t _3853 = (uint16_t)(190); + _curvea0[493] = _3853; + uint16_t _3854 = (uint16_t)(190); + _curvea0[494] = _3854; + uint16_t _3855 = (uint16_t)(190); + _curvea0[495] = _3855; + uint16_t _3856 = (uint16_t)(190); + _curvea0[496] = _3856; + uint16_t _3857 = (uint16_t)(190); + _curvea0[497] = _3857; + uint16_t _3858 = (uint16_t)(191); + _curvea0[498] = _3858; + uint16_t _3859 = (uint16_t)(191); + _curvea0[499] = _3859; + uint16_t _3860 = (uint16_t)(191); + _curvea0[500] = _3860; + uint16_t _3861 = (uint16_t)(191); + _curvea0[501] = _3861; + uint16_t _3862 = (uint16_t)(191); + _curvea0[502] = _3862; + uint16_t _3863 = (uint16_t)(192); + _curvea0[503] = _3863; + uint16_t _3864 = (uint16_t)(192); + _curvea0[504] = _3864; + uint16_t _3865 = (uint16_t)(192); + _curvea0[505] = _3865; + uint16_t _3866 = (uint16_t)(192); + _curvea0[506] = _3866; + uint16_t _3867 = (uint16_t)(192); + _curvea0[507] = _3867; + uint16_t _3868 = (uint16_t)(193); + _curvea0[508] = _3868; + uint16_t _3869 = (uint16_t)(193); + _curvea0[509] = _3869; + uint16_t _3870 = (uint16_t)(193); + _curvea0[510] = _3870; + uint16_t _3871 = (uint16_t)(193); + _curvea0[511] = _3871; + uint16_t _3872 = (uint16_t)(193); + _curvea0[512] = _3872; + uint16_t _3873 = (uint16_t)(194); + _curvea0[513] = _3873; + uint16_t _3874 = (uint16_t)(194); + _curvea0[514] = _3874; + uint16_t _3875 = (uint16_t)(194); + _curvea0[515] = _3875; + uint16_t _3876 = (uint16_t)(194); + _curvea0[516] = _3876; + uint16_t _3877 = (uint16_t)(194); + _curvea0[517] = _3877; + uint16_t _3878 = (uint16_t)(195); + _curvea0[518] = _3878; + uint16_t _3879 = (uint16_t)(195); + _curvea0[519] = _3879; + uint16_t _3880 = (uint16_t)(195); + _curvea0[520] = _3880; + uint16_t _3881 = (uint16_t)(195); + _curvea0[521] = _3881; + uint16_t _3882 = (uint16_t)(195); + _curvea0[522] = _3882; + uint16_t _3883 = (uint16_t)(195); + _curvea0[523] = _3883; + uint16_t _3884 = (uint16_t)(196); + _curvea0[524] = _3884; + uint16_t _3885 = (uint16_t)(196); + _curvea0[525] = _3885; + uint16_t _3886 = (uint16_t)(196); + _curvea0[526] = _3886; + uint16_t _3887 = (uint16_t)(196); + _curvea0[527] = _3887; + uint16_t _3888 = (uint16_t)(196); + _curvea0[528] = _3888; + uint16_t _3889 = (uint16_t)(197); + _curvea0[529] = _3889; + uint16_t _3890 = (uint16_t)(197); + _curvea0[530] = _3890; + uint16_t _3891 = (uint16_t)(197); + _curvea0[531] = _3891; + uint16_t _3892 = (uint16_t)(197); + _curvea0[532] = _3892; + uint16_t _3893 = (uint16_t)(197); + _curvea0[533] = _3893; + uint16_t _3894 = (uint16_t)(197); + _curvea0[534] = _3894; + uint16_t _3895 = (uint16_t)(198); + _curvea0[535] = _3895; + uint16_t _3896 = (uint16_t)(198); + _curvea0[536] = _3896; + uint16_t _3897 = (uint16_t)(198); + _curvea0[537] = _3897; + uint16_t _3898 = (uint16_t)(198); + _curvea0[538] = _3898; + uint16_t _3899 = (uint16_t)(198); + _curvea0[539] = _3899; + uint16_t _3900 = (uint16_t)(199); + _curvea0[540] = _3900; + uint16_t _3901 = (uint16_t)(199); + _curvea0[541] = _3901; + uint16_t _3902 = (uint16_t)(199); + _curvea0[542] = _3902; + uint16_t _3903 = (uint16_t)(199); + _curvea0[543] = _3903; + uint16_t _3904 = (uint16_t)(199); + _curvea0[544] = _3904; + uint16_t _3905 = (uint16_t)(199); + _curvea0[545] = _3905; + uint16_t _3906 = (uint16_t)(200); + _curvea0[546] = _3906; + uint16_t _3907 = (uint16_t)(200); + _curvea0[547] = _3907; + uint16_t _3908 = (uint16_t)(200); + _curvea0[548] = _3908; + uint16_t _3909 = (uint16_t)(200); + _curvea0[549] = _3909; + uint16_t _3910 = (uint16_t)(200); + _curvea0[550] = _3910; + uint16_t _3911 = (uint16_t)(200); + _curvea0[551] = _3911; + uint16_t _3912 = (uint16_t)(201); + _curvea0[552] = _3912; + uint16_t _3913 = (uint16_t)(201); + _curvea0[553] = _3913; + uint16_t _3914 = (uint16_t)(201); + _curvea0[554] = _3914; + uint16_t _3915 = (uint16_t)(201); + _curvea0[555] = _3915; + uint16_t _3916 = (uint16_t)(201); + _curvea0[556] = _3916; + uint16_t _3917 = (uint16_t)(202); + _curvea0[557] = _3917; + uint16_t _3918 = (uint16_t)(202); + _curvea0[558] = _3918; + uint16_t _3919 = (uint16_t)(202); + _curvea0[559] = _3919; + uint16_t _3920 = (uint16_t)(202); + _curvea0[560] = _3920; + uint16_t _3921 = (uint16_t)(202); + _curvea0[561] = _3921; + uint16_t _3922 = (uint16_t)(202); + _curvea0[562] = _3922; + uint16_t _3923 = (uint16_t)(203); + _curvea0[563] = _3923; + uint16_t _3924 = (uint16_t)(203); + _curvea0[564] = _3924; + uint16_t _3925 = (uint16_t)(203); + _curvea0[565] = _3925; + uint16_t _3926 = (uint16_t)(203); + _curvea0[566] = _3926; + uint16_t _3927 = (uint16_t)(203); + _curvea0[567] = _3927; + uint16_t _3928 = (uint16_t)(203); + _curvea0[568] = _3928; + uint16_t _3929 = (uint16_t)(204); + _curvea0[569] = _3929; + uint16_t _3930 = (uint16_t)(204); + _curvea0[570] = _3930; + uint16_t _3931 = (uint16_t)(204); + _curvea0[571] = _3931; + uint16_t _3932 = (uint16_t)(204); + _curvea0[572] = _3932; + uint16_t _3933 = (uint16_t)(204); + _curvea0[573] = _3933; + uint16_t _3934 = (uint16_t)(204); + _curvea0[574] = _3934; + uint16_t _3935 = (uint16_t)(205); + _curvea0[575] = _3935; + uint16_t _3936 = (uint16_t)(205); + _curvea0[576] = _3936; + uint16_t _3937 = (uint16_t)(205); + _curvea0[577] = _3937; + uint16_t _3938 = (uint16_t)(205); + _curvea0[578] = _3938; + uint16_t _3939 = (uint16_t)(205); + _curvea0[579] = _3939; + uint16_t _3940 = (uint16_t)(205); + _curvea0[580] = _3940; + uint16_t _3941 = (uint16_t)(206); + _curvea0[581] = _3941; + uint16_t _3942 = (uint16_t)(206); + _curvea0[582] = _3942; + uint16_t _3943 = (uint16_t)(206); + _curvea0[583] = _3943; + uint16_t _3944 = (uint16_t)(206); + _curvea0[584] = _3944; + uint16_t _3945 = (uint16_t)(206); + _curvea0[585] = _3945; + uint16_t _3946 = (uint16_t)(206); + _curvea0[586] = _3946; + uint16_t _3947 = (uint16_t)(207); + _curvea0[587] = _3947; + uint16_t _3948 = (uint16_t)(207); + _curvea0[588] = _3948; + uint16_t _3949 = (uint16_t)(207); + _curvea0[589] = _3949; + uint16_t _3950 = (uint16_t)(207); + _curvea0[590] = _3950; + uint16_t _3951 = (uint16_t)(207); + _curvea0[591] = _3951; + uint16_t _3952 = (uint16_t)(207); + _curvea0[592] = _3952; + uint16_t _3953 = (uint16_t)(208); + _curvea0[593] = _3953; + uint16_t _3954 = (uint16_t)(208); + _curvea0[594] = _3954; + uint16_t _3955 = (uint16_t)(208); + _curvea0[595] = _3955; + uint16_t _3956 = (uint16_t)(208); + _curvea0[596] = _3956; + uint16_t _3957 = (uint16_t)(208); + _curvea0[597] = _3957; + uint16_t _3958 = (uint16_t)(208); + _curvea0[598] = _3958; + uint16_t _3959 = (uint16_t)(209); + _curvea0[599] = _3959; + uint16_t _3960 = (uint16_t)(209); + _curvea0[600] = _3960; + uint16_t _3961 = (uint16_t)(209); + _curvea0[601] = _3961; + uint16_t _3962 = (uint16_t)(209); + _curvea0[602] = _3962; + uint16_t _3963 = (uint16_t)(209); + _curvea0[603] = _3963; + uint16_t _3964 = (uint16_t)(209); + _curvea0[604] = _3964; + uint16_t _3965 = (uint16_t)(209); + _curvea0[605] = _3965; + uint16_t _3966 = (uint16_t)(210); + _curvea0[606] = _3966; + uint16_t _3967 = (uint16_t)(210); + _curvea0[607] = _3967; + uint16_t _3968 = (uint16_t)(210); + _curvea0[608] = _3968; + uint16_t _3969 = (uint16_t)(210); + _curvea0[609] = _3969; + uint16_t _3970 = (uint16_t)(210); + _curvea0[610] = _3970; + uint16_t _3971 = (uint16_t)(210); + _curvea0[611] = _3971; + uint16_t _3972 = (uint16_t)(211); + _curvea0[612] = _3972; + uint16_t _3973 = (uint16_t)(211); + _curvea0[613] = _3973; + uint16_t _3974 = (uint16_t)(211); + _curvea0[614] = _3974; + uint16_t _3975 = (uint16_t)(211); + _curvea0[615] = _3975; + uint16_t _3976 = (uint16_t)(211); + _curvea0[616] = _3976; + uint16_t _3977 = (uint16_t)(211); + _curvea0[617] = _3977; + uint16_t _3978 = (uint16_t)(211); + _curvea0[618] = _3978; + uint16_t _3979 = (uint16_t)(212); + _curvea0[619] = _3979; + uint16_t _3980 = (uint16_t)(212); + _curvea0[620] = _3980; + uint16_t _3981 = (uint16_t)(212); + _curvea0[621] = _3981; + uint16_t _3982 = (uint16_t)(212); + _curvea0[622] = _3982; + uint16_t _3983 = (uint16_t)(212); + _curvea0[623] = _3983; + uint16_t _3984 = (uint16_t)(212); + _curvea0[624] = _3984; + uint16_t _3985 = (uint16_t)(213); + _curvea0[625] = _3985; + uint16_t _3986 = (uint16_t)(213); + _curvea0[626] = _3986; + uint16_t _3987 = (uint16_t)(213); + _curvea0[627] = _3987; + uint16_t _3988 = (uint16_t)(213); + _curvea0[628] = _3988; + uint16_t _3989 = (uint16_t)(213); + _curvea0[629] = _3989; + uint16_t _3990 = (uint16_t)(213); + _curvea0[630] = _3990; + uint16_t _3991 = (uint16_t)(213); + _curvea0[631] = _3991; + uint16_t _3992 = (uint16_t)(214); + _curvea0[632] = _3992; + uint16_t _3993 = (uint16_t)(214); + _curvea0[633] = _3993; + uint16_t _3994 = (uint16_t)(214); + _curvea0[634] = _3994; + uint16_t _3995 = (uint16_t)(214); + _curvea0[635] = _3995; + uint16_t _3996 = (uint16_t)(214); + _curvea0[636] = _3996; + uint16_t _3997 = (uint16_t)(214); + _curvea0[637] = _3997; + uint16_t _3998 = (uint16_t)(214); + _curvea0[638] = _3998; + uint16_t _3999 = (uint16_t)(215); + _curvea0[639] = _3999; + uint16_t _4000 = (uint16_t)(215); + _curvea0[640] = _4000; + uint16_t _4001 = (uint16_t)(215); + _curvea0[641] = _4001; + uint16_t _4002 = (uint16_t)(215); + _curvea0[642] = _4002; + uint16_t _4003 = (uint16_t)(215); + _curvea0[643] = _4003; + uint16_t _4004 = (uint16_t)(215); + _curvea0[644] = _4004; + uint16_t _4005 = (uint16_t)(216); + _curvea0[645] = _4005; + uint16_t _4006 = (uint16_t)(216); + _curvea0[646] = _4006; + uint16_t _4007 = (uint16_t)(216); + _curvea0[647] = _4007; + uint16_t _4008 = (uint16_t)(216); + _curvea0[648] = _4008; + uint16_t _4009 = (uint16_t)(216); + _curvea0[649] = _4009; + uint16_t _4010 = (uint16_t)(216); + _curvea0[650] = _4010; + uint16_t _4011 = (uint16_t)(216); + _curvea0[651] = _4011; + uint16_t _4012 = (uint16_t)(217); + _curvea0[652] = _4012; + uint16_t _4013 = (uint16_t)(217); + _curvea0[653] = _4013; + uint16_t _4014 = (uint16_t)(217); + _curvea0[654] = _4014; + uint16_t _4015 = (uint16_t)(217); + _curvea0[655] = _4015; + uint16_t _4016 = (uint16_t)(217); + _curvea0[656] = _4016; + uint16_t _4017 = (uint16_t)(217); + _curvea0[657] = _4017; + uint16_t _4018 = (uint16_t)(217); + _curvea0[658] = _4018; + uint16_t _4019 = (uint16_t)(218); + _curvea0[659] = _4019; + uint16_t _4020 = (uint16_t)(218); + _curvea0[660] = _4020; + uint16_t _4021 = (uint16_t)(218); + _curvea0[661] = _4021; + uint16_t _4022 = (uint16_t)(218); + _curvea0[662] = _4022; + uint16_t _4023 = (uint16_t)(218); + _curvea0[663] = _4023; + uint16_t _4024 = (uint16_t)(218); + _curvea0[664] = _4024; + uint16_t _4025 = (uint16_t)(218); + _curvea0[665] = _4025; + uint16_t _4026 = (uint16_t)(219); + _curvea0[666] = _4026; + uint16_t _4027 = (uint16_t)(219); + _curvea0[667] = _4027; + uint16_t _4028 = (uint16_t)(219); + _curvea0[668] = _4028; + uint16_t _4029 = (uint16_t)(219); + _curvea0[669] = _4029; + uint16_t _4030 = (uint16_t)(219); + _curvea0[670] = _4030; + uint16_t _4031 = (uint16_t)(219); + _curvea0[671] = _4031; + uint16_t _4032 = (uint16_t)(219); + _curvea0[672] = _4032; + uint16_t _4033 = (uint16_t)(220); + _curvea0[673] = _4033; + uint16_t _4034 = (uint16_t)(220); + _curvea0[674] = _4034; + uint16_t _4035 = (uint16_t)(220); + _curvea0[675] = _4035; + uint16_t _4036 = (uint16_t)(220); + _curvea0[676] = _4036; + uint16_t _4037 = (uint16_t)(220); + _curvea0[677] = _4037; + uint16_t _4038 = (uint16_t)(220); + _curvea0[678] = _4038; + uint16_t _4039 = (uint16_t)(220); + _curvea0[679] = _4039; + uint16_t _4040 = (uint16_t)(220); + _curvea0[680] = _4040; + uint16_t _4041 = (uint16_t)(221); + _curvea0[681] = _4041; + uint16_t _4042 = (uint16_t)(221); + _curvea0[682] = _4042; + uint16_t _4043 = (uint16_t)(221); + _curvea0[683] = _4043; + uint16_t _4044 = (uint16_t)(221); + _curvea0[684] = _4044; + uint16_t _4045 = (uint16_t)(221); + _curvea0[685] = _4045; + uint16_t _4046 = (uint16_t)(221); + _curvea0[686] = _4046; + uint16_t _4047 = (uint16_t)(221); + _curvea0[687] = _4047; + uint16_t _4048 = (uint16_t)(222); + _curvea0[688] = _4048; + uint16_t _4049 = (uint16_t)(222); + _curvea0[689] = _4049; + uint16_t _4050 = (uint16_t)(222); + _curvea0[690] = _4050; + uint16_t _4051 = (uint16_t)(222); + _curvea0[691] = _4051; + uint16_t _4052 = (uint16_t)(222); + _curvea0[692] = _4052; + uint16_t _4053 = (uint16_t)(222); + _curvea0[693] = _4053; + uint16_t _4054 = (uint16_t)(222); + _curvea0[694] = _4054; + uint16_t _4055 = (uint16_t)(223); + _curvea0[695] = _4055; + uint16_t _4056 = (uint16_t)(223); + _curvea0[696] = _4056; + uint16_t _4057 = (uint16_t)(223); + _curvea0[697] = _4057; + uint16_t _4058 = (uint16_t)(223); + _curvea0[698] = _4058; + uint16_t _4059 = (uint16_t)(223); + _curvea0[699] = _4059; + uint16_t _4060 = (uint16_t)(223); + _curvea0[700] = _4060; + uint16_t _4061 = (uint16_t)(223); + _curvea0[701] = _4061; + uint16_t _4062 = (uint16_t)(223); + _curvea0[702] = _4062; + uint16_t _4063 = (uint16_t)(224); + _curvea0[703] = _4063; + uint16_t _4064 = (uint16_t)(224); + _curvea0[704] = _4064; + uint16_t _4065 = (uint16_t)(224); + _curvea0[705] = _4065; + uint16_t _4066 = (uint16_t)(224); + _curvea0[706] = _4066; + uint16_t _4067 = (uint16_t)(224); + _curvea0[707] = _4067; + uint16_t _4068 = (uint16_t)(224); + _curvea0[708] = _4068; + uint16_t _4069 = (uint16_t)(224); + _curvea0[709] = _4069; + uint16_t _4070 = (uint16_t)(224); + _curvea0[710] = _4070; + uint16_t _4071 = (uint16_t)(225); + _curvea0[711] = _4071; + uint16_t _4072 = (uint16_t)(225); + _curvea0[712] = _4072; + uint16_t _4073 = (uint16_t)(225); + _curvea0[713] = _4073; + uint16_t _4074 = (uint16_t)(225); + _curvea0[714] = _4074; + uint16_t _4075 = (uint16_t)(225); + _curvea0[715] = _4075; + uint16_t _4076 = (uint16_t)(225); + _curvea0[716] = _4076; + uint16_t _4077 = (uint16_t)(225); + _curvea0[717] = _4077; + uint16_t _4078 = (uint16_t)(226); + _curvea0[718] = _4078; + uint16_t _4079 = (uint16_t)(226); + _curvea0[719] = _4079; + uint16_t _4080 = (uint16_t)(226); + _curvea0[720] = _4080; + uint16_t _4081 = (uint16_t)(226); + _curvea0[721] = _4081; + uint16_t _4082 = (uint16_t)(226); + _curvea0[722] = _4082; + uint16_t _4083 = (uint16_t)(226); + _curvea0[723] = _4083; + uint16_t _4084 = (uint16_t)(226); + _curvea0[724] = _4084; + uint16_t _4085 = (uint16_t)(226); + _curvea0[725] = _4085; + uint16_t _4086 = (uint16_t)(227); + _curvea0[726] = _4086; + uint16_t _4087 = (uint16_t)(227); + _curvea0[727] = _4087; + uint16_t _4088 = (uint16_t)(227); + _curvea0[728] = _4088; + uint16_t _4089 = (uint16_t)(227); + _curvea0[729] = _4089; + uint16_t _4090 = (uint16_t)(227); + _curvea0[730] = _4090; + uint16_t _4091 = (uint16_t)(227); + _curvea0[731] = _4091; + uint16_t _4092 = (uint16_t)(227); + _curvea0[732] = _4092; + uint16_t _4093 = (uint16_t)(227); + _curvea0[733] = _4093; + uint16_t _4094 = (uint16_t)(228); + _curvea0[734] = _4094; + uint16_t _4095 = (uint16_t)(228); + _curvea0[735] = _4095; + uint16_t _4096 = (uint16_t)(228); + _curvea0[736] = _4096; + uint16_t _4097 = (uint16_t)(228); + _curvea0[737] = _4097; + uint16_t _4098 = (uint16_t)(228); + _curvea0[738] = _4098; + uint16_t _4099 = (uint16_t)(228); + _curvea0[739] = _4099; + uint16_t _4100 = (uint16_t)(228); + _curvea0[740] = _4100; + uint16_t _4101 = (uint16_t)(228); + _curvea0[741] = _4101; + uint16_t _4102 = (uint16_t)(228); + _curvea0[742] = _4102; + uint16_t _4103 = (uint16_t)(229); + _curvea0[743] = _4103; + uint16_t _4104 = (uint16_t)(229); + _curvea0[744] = _4104; + uint16_t _4105 = (uint16_t)(229); + _curvea0[745] = _4105; + uint16_t _4106 = (uint16_t)(229); + _curvea0[746] = _4106; + uint16_t _4107 = (uint16_t)(229); + _curvea0[747] = _4107; + uint16_t _4108 = (uint16_t)(229); + _curvea0[748] = _4108; + uint16_t _4109 = (uint16_t)(229); + _curvea0[749] = _4109; + uint16_t _4110 = (uint16_t)(229); + _curvea0[750] = _4110; + uint16_t _4111 = (uint16_t)(230); + _curvea0[751] = _4111; + uint16_t _4112 = (uint16_t)(230); + _curvea0[752] = _4112; + uint16_t _4113 = (uint16_t)(230); + _curvea0[753] = _4113; + uint16_t _4114 = (uint16_t)(230); + _curvea0[754] = _4114; + uint16_t _4115 = (uint16_t)(230); + _curvea0[755] = _4115; + uint16_t _4116 = (uint16_t)(230); + _curvea0[756] = _4116; + uint16_t _4117 = (uint16_t)(230); + _curvea0[757] = _4117; + uint16_t _4118 = (uint16_t)(230); + _curvea0[758] = _4118; + uint16_t _4119 = (uint16_t)(231); + _curvea0[759] = _4119; + uint16_t _4120 = (uint16_t)(231); + _curvea0[760] = _4120; + uint16_t _4121 = (uint16_t)(231); + _curvea0[761] = _4121; + uint16_t _4122 = (uint16_t)(231); + _curvea0[762] = _4122; + uint16_t _4123 = (uint16_t)(231); + _curvea0[763] = _4123; + uint16_t _4124 = (uint16_t)(231); + _curvea0[764] = _4124; + uint16_t _4125 = (uint16_t)(231); + _curvea0[765] = _4125; + uint16_t _4126 = (uint16_t)(231); + _curvea0[766] = _4126; + uint16_t _4127 = (uint16_t)(231); + _curvea0[767] = _4127; + uint16_t _4128 = (uint16_t)(232); + _curvea0[768] = _4128; + uint16_t _4129 = (uint16_t)(232); + _curvea0[769] = _4129; + uint16_t _4130 = (uint16_t)(232); + _curvea0[770] = _4130; + uint16_t _4131 = (uint16_t)(232); + _curvea0[771] = _4131; + uint16_t _4132 = (uint16_t)(232); + _curvea0[772] = _4132; + uint16_t _4133 = (uint16_t)(232); + _curvea0[773] = _4133; + uint16_t _4134 = (uint16_t)(232); + _curvea0[774] = _4134; + uint16_t _4135 = (uint16_t)(232); + _curvea0[775] = _4135; + uint16_t _4136 = (uint16_t)(233); + _curvea0[776] = _4136; + uint16_t _4137 = (uint16_t)(233); + _curvea0[777] = _4137; + uint16_t _4138 = (uint16_t)(233); + _curvea0[778] = _4138; + uint16_t _4139 = (uint16_t)(233); + _curvea0[779] = _4139; + uint16_t _4140 = (uint16_t)(233); + _curvea0[780] = _4140; + uint16_t _4141 = (uint16_t)(233); + _curvea0[781] = _4141; + uint16_t _4142 = (uint16_t)(233); + _curvea0[782] = _4142; + uint16_t _4143 = (uint16_t)(233); + _curvea0[783] = _4143; + uint16_t _4144 = (uint16_t)(233); + _curvea0[784] = _4144; + uint16_t _4145 = (uint16_t)(234); + _curvea0[785] = _4145; + uint16_t _4146 = (uint16_t)(234); + _curvea0[786] = _4146; + uint16_t _4147 = (uint16_t)(234); + _curvea0[787] = _4147; + uint16_t _4148 = (uint16_t)(234); + _curvea0[788] = _4148; + uint16_t _4149 = (uint16_t)(234); + _curvea0[789] = _4149; + uint16_t _4150 = (uint16_t)(234); + _curvea0[790] = _4150; + uint16_t _4151 = (uint16_t)(234); + _curvea0[791] = _4151; + uint16_t _4152 = (uint16_t)(234); + _curvea0[792] = _4152; + uint16_t _4153 = (uint16_t)(234); + _curvea0[793] = _4153; + uint16_t _4154 = (uint16_t)(235); + _curvea0[794] = _4154; + uint16_t _4155 = (uint16_t)(235); + _curvea0[795] = _4155; + uint16_t _4156 = (uint16_t)(235); + _curvea0[796] = _4156; + uint16_t _4157 = (uint16_t)(235); + _curvea0[797] = _4157; + uint16_t _4158 = (uint16_t)(235); + _curvea0[798] = _4158; + uint16_t _4159 = (uint16_t)(235); + _curvea0[799] = _4159; + uint16_t _4160 = (uint16_t)(235); + _curvea0[800] = _4160; + uint16_t _4161 = (uint16_t)(235); + _curvea0[801] = _4161; + uint16_t _4162 = (uint16_t)(235); + _curvea0[802] = _4162; + uint16_t _4163 = (uint16_t)(236); + _curvea0[803] = _4163; + uint16_t _4164 = (uint16_t)(236); + _curvea0[804] = _4164; + uint16_t _4165 = (uint16_t)(236); + _curvea0[805] = _4165; + uint16_t _4166 = (uint16_t)(236); + _curvea0[806] = _4166; + uint16_t _4167 = (uint16_t)(236); + _curvea0[807] = _4167; + uint16_t _4168 = (uint16_t)(236); + _curvea0[808] = _4168; + uint16_t _4169 = (uint16_t)(236); + _curvea0[809] = _4169; + uint16_t _4170 = (uint16_t)(236); + _curvea0[810] = _4170; + uint16_t _4171 = (uint16_t)(236); + _curvea0[811] = _4171; + uint16_t _4172 = (uint16_t)(237); + _curvea0[812] = _4172; + uint16_t _4173 = (uint16_t)(237); + _curvea0[813] = _4173; + uint16_t _4174 = (uint16_t)(237); + _curvea0[814] = _4174; + uint16_t _4175 = (uint16_t)(237); + _curvea0[815] = _4175; + uint16_t _4176 = (uint16_t)(237); + _curvea0[816] = _4176; + uint16_t _4177 = (uint16_t)(237); + _curvea0[817] = _4177; + uint16_t _4178 = (uint16_t)(237); + _curvea0[818] = _4178; + uint16_t _4179 = (uint16_t)(237); + _curvea0[819] = _4179; + uint16_t _4180 = (uint16_t)(237); + _curvea0[820] = _4180; + uint16_t _4181 = (uint16_t)(237); + _curvea0[821] = _4181; + uint16_t _4182 = (uint16_t)(238); + _curvea0[822] = _4182; + uint16_t _4183 = (uint16_t)(238); + _curvea0[823] = _4183; + uint16_t _4184 = (uint16_t)(238); + _curvea0[824] = _4184; + uint16_t _4185 = (uint16_t)(238); + _curvea0[825] = _4185; + uint16_t _4186 = (uint16_t)(238); + _curvea0[826] = _4186; + uint16_t _4187 = (uint16_t)(238); + _curvea0[827] = _4187; + uint16_t _4188 = (uint16_t)(238); + _curvea0[828] = _4188; + uint16_t _4189 = (uint16_t)(238); + _curvea0[829] = _4189; + uint16_t _4190 = (uint16_t)(238); + _curvea0[830] = _4190; + uint16_t _4191 = (uint16_t)(239); + _curvea0[831] = _4191; + uint16_t _4192 = (uint16_t)(239); + _curvea0[832] = _4192; + uint16_t _4193 = (uint16_t)(239); + _curvea0[833] = _4193; + uint16_t _4194 = (uint16_t)(239); + _curvea0[834] = _4194; + uint16_t _4195 = (uint16_t)(239); + _curvea0[835] = _4195; + uint16_t _4196 = (uint16_t)(239); + _curvea0[836] = _4196; + uint16_t _4197 = (uint16_t)(239); + _curvea0[837] = _4197; + uint16_t _4198 = (uint16_t)(239); + _curvea0[838] = _4198; + uint16_t _4199 = (uint16_t)(239); + _curvea0[839] = _4199; + uint16_t _4200 = (uint16_t)(239); + _curvea0[840] = _4200; + uint16_t _4201 = (uint16_t)(240); + _curvea0[841] = _4201; + uint16_t _4202 = (uint16_t)(240); + _curvea0[842] = _4202; + uint16_t _4203 = (uint16_t)(240); + _curvea0[843] = _4203; + uint16_t _4204 = (uint16_t)(240); + _curvea0[844] = _4204; + uint16_t _4205 = (uint16_t)(240); + _curvea0[845] = _4205; + uint16_t _4206 = (uint16_t)(240); + _curvea0[846] = _4206; + uint16_t _4207 = (uint16_t)(240); + _curvea0[847] = _4207; + uint16_t _4208 = (uint16_t)(240); + _curvea0[848] = _4208; + uint16_t _4209 = (uint16_t)(240); + _curvea0[849] = _4209; + uint16_t _4210 = (uint16_t)(240); + _curvea0[850] = _4210; + uint16_t _4211 = (uint16_t)(241); + _curvea0[851] = _4211; + uint16_t _4212 = (uint16_t)(241); + _curvea0[852] = _4212; + uint16_t _4213 = (uint16_t)(241); + _curvea0[853] = _4213; + uint16_t _4214 = (uint16_t)(241); + _curvea0[854] = _4214; + uint16_t _4215 = (uint16_t)(241); + _curvea0[855] = _4215; + uint16_t _4216 = (uint16_t)(241); + _curvea0[856] = _4216; + uint16_t _4217 = (uint16_t)(241); + _curvea0[857] = _4217; + uint16_t _4218 = (uint16_t)(241); + _curvea0[858] = _4218; + uint16_t _4219 = (uint16_t)(241); + _curvea0[859] = _4219; + uint16_t _4220 = (uint16_t)(241); + _curvea0[860] = _4220; + uint16_t _4221 = (uint16_t)(242); + _curvea0[861] = _4221; + uint16_t _4222 = (uint16_t)(242); + _curvea0[862] = _4222; + uint16_t _4223 = (uint16_t)(242); + _curvea0[863] = _4223; + uint16_t _4224 = (uint16_t)(242); + _curvea0[864] = _4224; + uint16_t _4225 = (uint16_t)(242); + _curvea0[865] = _4225; + uint16_t _4226 = (uint16_t)(242); + _curvea0[866] = _4226; + uint16_t _4227 = (uint16_t)(242); + _curvea0[867] = _4227; + uint16_t _4228 = (uint16_t)(242); + _curvea0[868] = _4228; + uint16_t _4229 = (uint16_t)(242); + _curvea0[869] = _4229; + uint16_t _4230 = (uint16_t)(242); + _curvea0[870] = _4230; + uint16_t _4231 = (uint16_t)(243); + _curvea0[871] = _4231; + uint16_t _4232 = (uint16_t)(243); + _curvea0[872] = _4232; + uint16_t _4233 = (uint16_t)(243); + _curvea0[873] = _4233; + uint16_t _4234 = (uint16_t)(243); + _curvea0[874] = _4234; + uint16_t _4235 = (uint16_t)(243); + _curvea0[875] = _4235; + uint16_t _4236 = (uint16_t)(243); + _curvea0[876] = _4236; + uint16_t _4237 = (uint16_t)(243); + _curvea0[877] = _4237; + uint16_t _4238 = (uint16_t)(243); + _curvea0[878] = _4238; + uint16_t _4239 = (uint16_t)(243); + _curvea0[879] = _4239; + uint16_t _4240 = (uint16_t)(243); + _curvea0[880] = _4240; + uint16_t _4241 = (uint16_t)(244); + _curvea0[881] = _4241; + uint16_t _4242 = (uint16_t)(244); + _curvea0[882] = _4242; + uint16_t _4243 = (uint16_t)(244); + _curvea0[883] = _4243; + uint16_t _4244 = (uint16_t)(244); + _curvea0[884] = _4244; + uint16_t _4245 = (uint16_t)(244); + _curvea0[885] = _4245; + uint16_t _4246 = (uint16_t)(244); + _curvea0[886] = _4246; + uint16_t _4247 = (uint16_t)(244); + _curvea0[887] = _4247; + uint16_t _4248 = (uint16_t)(244); + _curvea0[888] = _4248; + uint16_t _4249 = (uint16_t)(244); + _curvea0[889] = _4249; + uint16_t _4250 = (uint16_t)(244); + _curvea0[890] = _4250; + uint16_t _4251 = (uint16_t)(244); + _curvea0[891] = _4251; + uint16_t _4252 = (uint16_t)(245); + _curvea0[892] = _4252; + uint16_t _4253 = (uint16_t)(245); + _curvea0[893] = _4253; + uint16_t _4254 = (uint16_t)(245); + _curvea0[894] = _4254; + uint16_t _4255 = (uint16_t)(245); + _curvea0[895] = _4255; + uint16_t _4256 = (uint16_t)(245); + _curvea0[896] = _4256; + uint16_t _4257 = (uint16_t)(245); + _curvea0[897] = _4257; + uint16_t _4258 = (uint16_t)(245); + _curvea0[898] = _4258; + uint16_t _4259 = (uint16_t)(245); + _curvea0[899] = _4259; + uint16_t _4260 = (uint16_t)(245); + _curvea0[900] = _4260; + uint16_t _4261 = (uint16_t)(245); + _curvea0[901] = _4261; + uint16_t _4262 = (uint16_t)(245); + _curvea0[902] = _4262; + uint16_t _4263 = (uint16_t)(246); + _curvea0[903] = _4263; + uint16_t _4264 = (uint16_t)(246); + _curvea0[904] = _4264; + uint16_t _4265 = (uint16_t)(246); + _curvea0[905] = _4265; + uint16_t _4266 = (uint16_t)(246); + _curvea0[906] = _4266; + uint16_t _4267 = (uint16_t)(246); + _curvea0[907] = _4267; + uint16_t _4268 = (uint16_t)(246); + _curvea0[908] = _4268; + uint16_t _4269 = (uint16_t)(246); + _curvea0[909] = _4269; + uint16_t _4270 = (uint16_t)(246); + _curvea0[910] = _4270; + uint16_t _4271 = (uint16_t)(246); + _curvea0[911] = _4271; + uint16_t _4272 = (uint16_t)(246); + _curvea0[912] = _4272; + uint16_t _4273 = (uint16_t)(246); + _curvea0[913] = _4273; + uint16_t _4274 = (uint16_t)(247); + _curvea0[914] = _4274; + uint16_t _4275 = (uint16_t)(247); + _curvea0[915] = _4275; + uint16_t _4276 = (uint16_t)(247); + _curvea0[916] = _4276; + uint16_t _4277 = (uint16_t)(247); + _curvea0[917] = _4277; + uint16_t _4278 = (uint16_t)(247); + _curvea0[918] = _4278; + uint16_t _4279 = (uint16_t)(247); + _curvea0[919] = _4279; + uint16_t _4280 = (uint16_t)(247); + _curvea0[920] = _4280; + uint16_t _4281 = (uint16_t)(247); + _curvea0[921] = _4281; + uint16_t _4282 = (uint16_t)(247); + _curvea0[922] = _4282; + uint16_t _4283 = (uint16_t)(247); + _curvea0[923] = _4283; + uint16_t _4284 = (uint16_t)(247); + _curvea0[924] = _4284; + uint16_t _4285 = (uint16_t)(248); + _curvea0[925] = _4285; + uint16_t _4286 = (uint16_t)(248); + _curvea0[926] = _4286; + uint16_t _4287 = (uint16_t)(248); + _curvea0[927] = _4287; + uint16_t _4288 = (uint16_t)(248); + _curvea0[928] = _4288; + uint16_t _4289 = (uint16_t)(248); + _curvea0[929] = _4289; + uint16_t _4290 = (uint16_t)(248); + _curvea0[930] = _4290; + uint16_t _4291 = (uint16_t)(248); + _curvea0[931] = _4291; + uint16_t _4292 = (uint16_t)(248); + _curvea0[932] = _4292; + uint16_t _4293 = (uint16_t)(248); + _curvea0[933] = _4293; + uint16_t _4294 = (uint16_t)(248); + _curvea0[934] = _4294; + uint16_t _4295 = (uint16_t)(248); + _curvea0[935] = _4295; + uint16_t _4296 = (uint16_t)(249); + _curvea0[936] = _4296; + uint16_t _4297 = (uint16_t)(249); + _curvea0[937] = _4297; + uint16_t _4298 = (uint16_t)(249); + _curvea0[938] = _4298; + uint16_t _4299 = (uint16_t)(249); + _curvea0[939] = _4299; + uint16_t _4300 = (uint16_t)(249); + _curvea0[940] = _4300; + uint16_t _4301 = (uint16_t)(249); + _curvea0[941] = _4301; + uint16_t _4302 = (uint16_t)(249); + _curvea0[942] = _4302; + uint16_t _4303 = (uint16_t)(249); + _curvea0[943] = _4303; + uint16_t _4304 = (uint16_t)(249); + _curvea0[944] = _4304; + uint16_t _4305 = (uint16_t)(249); + _curvea0[945] = _4305; + uint16_t _4306 = (uint16_t)(249); + _curvea0[946] = _4306; + uint16_t _4307 = (uint16_t)(249); + _curvea0[947] = _4307; + uint16_t _4308 = (uint16_t)(250); + _curvea0[948] = _4308; + uint16_t _4309 = (uint16_t)(250); + _curvea0[949] = _4309; + uint16_t _4310 = (uint16_t)(250); + _curvea0[950] = _4310; + uint16_t _4311 = (uint16_t)(250); + _curvea0[951] = _4311; + uint16_t _4312 = (uint16_t)(250); + _curvea0[952] = _4312; + uint16_t _4313 = (uint16_t)(250); + _curvea0[953] = _4313; + uint16_t _4314 = (uint16_t)(250); + _curvea0[954] = _4314; + uint16_t _4315 = (uint16_t)(250); + _curvea0[955] = _4315; + uint16_t _4316 = (uint16_t)(250); + _curvea0[956] = _4316; + uint16_t _4317 = (uint16_t)(250); + _curvea0[957] = _4317; + uint16_t _4318 = (uint16_t)(250); + _curvea0[958] = _4318; + uint16_t _4319 = (uint16_t)(250); + _curvea0[959] = _4319; + uint16_t _4320 = (uint16_t)(251); + _curvea0[960] = _4320; + uint16_t _4321 = (uint16_t)(251); + _curvea0[961] = _4321; + uint16_t _4322 = (uint16_t)(251); + _curvea0[962] = _4322; + uint16_t _4323 = (uint16_t)(251); + _curvea0[963] = _4323; + uint16_t _4324 = (uint16_t)(251); + _curvea0[964] = _4324; + uint16_t _4325 = (uint16_t)(251); + _curvea0[965] = _4325; + uint16_t _4326 = (uint16_t)(251); + _curvea0[966] = _4326; + uint16_t _4327 = (uint16_t)(251); + _curvea0[967] = _4327; + uint16_t _4328 = (uint16_t)(251); + _curvea0[968] = _4328; + uint16_t _4329 = (uint16_t)(251); + _curvea0[969] = _4329; + uint16_t _4330 = (uint16_t)(251); + _curvea0[970] = _4330; + uint16_t _4331 = (uint16_t)(251); + _curvea0[971] = _4331; + uint16_t _4332 = (uint16_t)(252); + _curvea0[972] = _4332; + uint16_t _4333 = (uint16_t)(252); + _curvea0[973] = _4333; + uint16_t _4334 = (uint16_t)(252); + _curvea0[974] = _4334; + uint16_t _4335 = (uint16_t)(252); + _curvea0[975] = _4335; + uint16_t _4336 = (uint16_t)(252); + _curvea0[976] = _4336; + uint16_t _4337 = (uint16_t)(252); + _curvea0[977] = _4337; + uint16_t _4338 = (uint16_t)(252); + _curvea0[978] = _4338; + uint16_t _4339 = (uint16_t)(252); + _curvea0[979] = _4339; + uint16_t _4340 = (uint16_t)(252); + _curvea0[980] = _4340; + uint16_t _4341 = (uint16_t)(252); + _curvea0[981] = _4341; + uint16_t _4342 = (uint16_t)(252); + _curvea0[982] = _4342; + uint16_t _4343 = (uint16_t)(252); + _curvea0[983] = _4343; + uint16_t _4344 = (uint16_t)(252); + _curvea0[984] = _4344; + uint16_t _4345 = (uint16_t)(253); + _curvea0[985] = _4345; + uint16_t _4346 = (uint16_t)(253); + _curvea0[986] = _4346; + uint16_t _4347 = (uint16_t)(253); + _curvea0[987] = _4347; + uint16_t _4348 = (uint16_t)(253); + _curvea0[988] = _4348; + uint16_t _4349 = (uint16_t)(253); + _curvea0[989] = _4349; + uint16_t _4350 = (uint16_t)(253); + _curvea0[990] = _4350; + uint16_t _4351 = (uint16_t)(253); + _curvea0[991] = _4351; + uint16_t _4352 = (uint16_t)(253); + _curvea0[992] = _4352; + uint16_t _4353 = (uint16_t)(253); + _curvea0[993] = _4353; + uint16_t _4354 = (uint16_t)(253); + _curvea0[994] = _4354; + uint16_t _4355 = (uint16_t)(253); + _curvea0[995] = _4355; + uint16_t _4356 = (uint16_t)(253); + _curvea0[996] = _4356; + uint16_t _4357 = (uint16_t)(253); + _curvea0[997] = _4357; + uint16_t _4358 = (uint16_t)(254); + _curvea0[998] = _4358; + uint16_t _4359 = (uint16_t)(254); + _curvea0[999] = _4359; + uint16_t _4360 = (uint16_t)(254); + _curvea0[1000] = _4360; + uint16_t _4361 = (uint16_t)(254); + _curvea0[1001] = _4361; + uint16_t _4362 = (uint16_t)(254); + _curvea0[1002] = _4362; + uint16_t _4363 = (uint16_t)(254); + _curvea0[1003] = _4363; + uint16_t _4364 = (uint16_t)(254); + _curvea0[1004] = _4364; + uint16_t _4365 = (uint16_t)(254); + _curvea0[1005] = _4365; + uint16_t _4366 = (uint16_t)(254); + _curvea0[1006] = _4366; + uint16_t _4367 = (uint16_t)(254); + _curvea0[1007] = _4367; + uint16_t _4368 = (uint16_t)(254); + _curvea0[1008] = _4368; + uint16_t _4369 = (uint16_t)(254); + _curvea0[1009] = _4369; + uint16_t _4370 = (uint16_t)(254); + _curvea0[1010] = _4370; + uint16_t _4371 = (uint16_t)(255); + _curvea0[1011] = _4371; + uint16_t _4372 = (uint16_t)(255); + _curvea0[1012] = _4372; + uint16_t _4373 = (uint16_t)(255); + _curvea0[1013] = _4373; + uint16_t _4374 = (uint16_t)(255); + _curvea0[1014] = _4374; + uint16_t _4375 = (uint16_t)(255); + _curvea0[1015] = _4375; + uint16_t _4376 = (uint16_t)(255); + _curvea0[1016] = _4376; + uint16_t _4377 = (uint16_t)(255); + _curvea0[1017] = _4377; + uint16_t _4378 = (uint16_t)(255); + _curvea0[1018] = _4378; + uint16_t _4379 = (uint16_t)(255); + _curvea0[1019] = _4379; + uint16_t _4380 = (uint16_t)(255); + _curvea0[1020] = _4380; + uint16_t _4381 = (uint16_t)(255); + _curvea0[1021] = _4381; + uint16_t _4382 = (uint16_t)(255); + _curvea0[1022] = _4382; + uint16_t _4383 = (uint16_t)(255); + _curvea0[1023] = _4383; + + int16_t _4384 = (int16_t)(1023); + int16_t _4385 = min(_corrected_stencil_2, _4384); + int16_t _4386 = (int16_t)(0); + int16_t _4387 = max(_4385, _4386); + uint16_t _4388 = (uint16_t)(_4387); + int32_t _4389 = (int32_t)(_4388); + uint16_t _4390 = ((const uint16_t *)_curvea0)[_4389]; + return _4390; +} + +//store is: curved.stencil((curved_s0_x_x_1*2), curved_s0_y_1, 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x_1*2), curved_s0_y_1, 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_2(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_3 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _4407 = (uint16_t)(0); + _curvea0[0] = _4407; + uint16_t _4408 = (uint16_t)(4); + _curvea0[1] = _4408; + uint16_t _4409 = (uint16_t)(7); + _curvea0[2] = _4409; + uint16_t _4410 = (uint16_t)(8); + _curvea0[3] = _4410; + uint16_t _4411 = (uint16_t)(10); + _curvea0[4] = _4411; + uint16_t _4412 = (uint16_t)(11); + _curvea0[5] = _4412; + uint16_t _4413 = (uint16_t)(12); + _curvea0[6] = _4413; + uint16_t _4414 = (uint16_t)(13); + _curvea0[7] = _4414; + uint16_t _4415 = (uint16_t)(14); + _curvea0[8] = _4415; + uint16_t _4416 = (uint16_t)(15); + _curvea0[9] = _4416; + uint16_t _4417 = (uint16_t)(16); + _curvea0[10] = _4417; + uint16_t _4418 = (uint16_t)(17); + _curvea0[11] = _4418; + uint16_t _4419 = (uint16_t)(18); + _curvea0[12] = _4419; + uint16_t _4420 = (uint16_t)(19); + _curvea0[13] = _4420; + uint16_t _4421 = (uint16_t)(20); + _curvea0[14] = _4421; + uint16_t _4422 = (uint16_t)(21); + _curvea0[15] = _4422; + uint16_t _4423 = (uint16_t)(22); + _curvea0[16] = _4423; + uint16_t _4424 = (uint16_t)(22); + _curvea0[17] = _4424; + uint16_t _4425 = (uint16_t)(23); + _curvea0[18] = _4425; + uint16_t _4426 = (uint16_t)(24); + _curvea0[19] = _4426; + uint16_t _4427 = (uint16_t)(25); + _curvea0[20] = _4427; + uint16_t _4428 = (uint16_t)(25); + _curvea0[21] = _4428; + uint16_t _4429 = (uint16_t)(26); + _curvea0[22] = _4429; + uint16_t _4430 = (uint16_t)(27); + _curvea0[23] = _4430; + uint16_t _4431 = (uint16_t)(27); + _curvea0[24] = _4431; + uint16_t _4432 = (uint16_t)(28); + _curvea0[25] = _4432; + uint16_t _4433 = (uint16_t)(29); + _curvea0[26] = _4433; + uint16_t _4434 = (uint16_t)(29); + _curvea0[27] = _4434; + uint16_t _4435 = (uint16_t)(30); + _curvea0[28] = _4435; + uint16_t _4436 = (uint16_t)(31); + _curvea0[29] = _4436; + uint16_t _4437 = (uint16_t)(31); + _curvea0[30] = _4437; + uint16_t _4438 = (uint16_t)(32); + _curvea0[31] = _4438; + uint16_t _4439 = (uint16_t)(33); + _curvea0[32] = _4439; + uint16_t _4440 = (uint16_t)(33); + _curvea0[33] = _4440; + uint16_t _4441 = (uint16_t)(34); + _curvea0[34] = _4441; + uint16_t _4442 = (uint16_t)(34); + _curvea0[35] = _4442; + uint16_t _4443 = (uint16_t)(35); + _curvea0[36] = _4443; + uint16_t _4444 = (uint16_t)(36); + _curvea0[37] = _4444; + uint16_t _4445 = (uint16_t)(36); + _curvea0[38] = _4445; + uint16_t _4446 = (uint16_t)(37); + _curvea0[39] = _4446; + uint16_t _4447 = (uint16_t)(37); + _curvea0[40] = _4447; + uint16_t _4448 = (uint16_t)(38); + _curvea0[41] = _4448; + uint16_t _4449 = (uint16_t)(39); + _curvea0[42] = _4449; + uint16_t _4450 = (uint16_t)(39); + _curvea0[43] = _4450; + uint16_t _4451 = (uint16_t)(40); + _curvea0[44] = _4451; + uint16_t _4452 = (uint16_t)(40); + _curvea0[45] = _4452; + uint16_t _4453 = (uint16_t)(41); + _curvea0[46] = _4453; + uint16_t _4454 = (uint16_t)(41); + _curvea0[47] = _4454; + uint16_t _4455 = (uint16_t)(42); + _curvea0[48] = _4455; + uint16_t _4456 = (uint16_t)(42); + _curvea0[49] = _4456; + uint16_t _4457 = (uint16_t)(43); + _curvea0[50] = _4457; + uint16_t _4458 = (uint16_t)(44); + _curvea0[51] = _4458; + uint16_t _4459 = (uint16_t)(44); + _curvea0[52] = _4459; + uint16_t _4460 = (uint16_t)(45); + _curvea0[53] = _4460; + uint16_t _4461 = (uint16_t)(45); + _curvea0[54] = _4461; + uint16_t _4462 = (uint16_t)(46); + _curvea0[55] = _4462; + uint16_t _4463 = (uint16_t)(46); + _curvea0[56] = _4463; + uint16_t _4464 = (uint16_t)(47); + _curvea0[57] = _4464; + uint16_t _4465 = (uint16_t)(47); + _curvea0[58] = _4465; + uint16_t _4466 = (uint16_t)(48); + _curvea0[59] = _4466; + uint16_t _4467 = (uint16_t)(48); + _curvea0[60] = _4467; + uint16_t _4468 = (uint16_t)(49); + _curvea0[61] = _4468; + uint16_t _4469 = (uint16_t)(49); + _curvea0[62] = _4469; + uint16_t _4470 = (uint16_t)(50); + _curvea0[63] = _4470; + uint16_t _4471 = (uint16_t)(50); + _curvea0[64] = _4471; + uint16_t _4472 = (uint16_t)(51); + _curvea0[65] = _4472; + uint16_t _4473 = (uint16_t)(51); + _curvea0[66] = _4473; + uint16_t _4474 = (uint16_t)(52); + _curvea0[67] = _4474; + uint16_t _4475 = (uint16_t)(52); + _curvea0[68] = _4475; + uint16_t _4476 = (uint16_t)(53); + _curvea0[69] = _4476; + uint16_t _4477 = (uint16_t)(53); + _curvea0[70] = _4477; + uint16_t _4478 = (uint16_t)(54); + _curvea0[71] = _4478; + uint16_t _4479 = (uint16_t)(54); + _curvea0[72] = _4479; + uint16_t _4480 = (uint16_t)(55); + _curvea0[73] = _4480; + uint16_t _4481 = (uint16_t)(55); + _curvea0[74] = _4481; + uint16_t _4482 = (uint16_t)(56); + _curvea0[75] = _4482; + uint16_t _4483 = (uint16_t)(56); + _curvea0[76] = _4483; + uint16_t _4484 = (uint16_t)(57); + _curvea0[77] = _4484; + uint16_t _4485 = (uint16_t)(57); + _curvea0[78] = _4485; + uint16_t _4486 = (uint16_t)(58); + _curvea0[79] = _4486; + uint16_t _4487 = (uint16_t)(58); + _curvea0[80] = _4487; + uint16_t _4488 = (uint16_t)(58); + _curvea0[81] = _4488; + uint16_t _4489 = (uint16_t)(59); + _curvea0[82] = _4489; + uint16_t _4490 = (uint16_t)(59); + _curvea0[83] = _4490; + uint16_t _4491 = (uint16_t)(60); + _curvea0[84] = _4491; + uint16_t _4492 = (uint16_t)(60); + _curvea0[85] = _4492; + uint16_t _4493 = (uint16_t)(61); + _curvea0[86] = _4493; + uint16_t _4494 = (uint16_t)(61); + _curvea0[87] = _4494; + uint16_t _4495 = (uint16_t)(62); + _curvea0[88] = _4495; + uint16_t _4496 = (uint16_t)(62); + _curvea0[89] = _4496; + uint16_t _4497 = (uint16_t)(63); + _curvea0[90] = _4497; + uint16_t _4498 = (uint16_t)(63); + _curvea0[91] = _4498; + uint16_t _4499 = (uint16_t)(64); + _curvea0[92] = _4499; + uint16_t _4500 = (uint16_t)(64); + _curvea0[93] = _4500; + uint16_t _4501 = (uint16_t)(64); + _curvea0[94] = _4501; + uint16_t _4502 = (uint16_t)(65); + _curvea0[95] = _4502; + uint16_t _4503 = (uint16_t)(65); + _curvea0[96] = _4503; + uint16_t _4504 = (uint16_t)(66); + _curvea0[97] = _4504; + uint16_t _4505 = (uint16_t)(66); + _curvea0[98] = _4505; + uint16_t _4506 = (uint16_t)(67); + _curvea0[99] = _4506; + uint16_t _4507 = (uint16_t)(67); + _curvea0[100] = _4507; + uint16_t _4508 = (uint16_t)(68); + _curvea0[101] = _4508; + uint16_t _4509 = (uint16_t)(68); + _curvea0[102] = _4509; + uint16_t _4510 = (uint16_t)(68); + _curvea0[103] = _4510; + uint16_t _4511 = (uint16_t)(69); + _curvea0[104] = _4511; + uint16_t _4512 = (uint16_t)(69); + _curvea0[105] = _4512; + uint16_t _4513 = (uint16_t)(70); + _curvea0[106] = _4513; + uint16_t _4514 = (uint16_t)(70); + _curvea0[107] = _4514; + uint16_t _4515 = (uint16_t)(71); + _curvea0[108] = _4515; + uint16_t _4516 = (uint16_t)(71); + _curvea0[109] = _4516; + uint16_t _4517 = (uint16_t)(71); + _curvea0[110] = _4517; + uint16_t _4518 = (uint16_t)(72); + _curvea0[111] = _4518; + uint16_t _4519 = (uint16_t)(72); + _curvea0[112] = _4519; + uint16_t _4520 = (uint16_t)(73); + _curvea0[113] = _4520; + uint16_t _4521 = (uint16_t)(73); + _curvea0[114] = _4521; + uint16_t _4522 = (uint16_t)(74); + _curvea0[115] = _4522; + uint16_t _4523 = (uint16_t)(74); + _curvea0[116] = _4523; + uint16_t _4524 = (uint16_t)(74); + _curvea0[117] = _4524; + uint16_t _4525 = (uint16_t)(75); + _curvea0[118] = _4525; + uint16_t _4526 = (uint16_t)(75); + _curvea0[119] = _4526; + uint16_t _4527 = (uint16_t)(76); + _curvea0[120] = _4527; + uint16_t _4528 = (uint16_t)(76); + _curvea0[121] = _4528; + uint16_t _4529 = (uint16_t)(77); + _curvea0[122] = _4529; + uint16_t _4530 = (uint16_t)(77); + _curvea0[123] = _4530; + uint16_t _4531 = (uint16_t)(77); + _curvea0[124] = _4531; + uint16_t _4532 = (uint16_t)(78); + _curvea0[125] = _4532; + uint16_t _4533 = (uint16_t)(78); + _curvea0[126] = _4533; + uint16_t _4534 = (uint16_t)(79); + _curvea0[127] = _4534; + uint16_t _4535 = (uint16_t)(79); + _curvea0[128] = _4535; + uint16_t _4536 = (uint16_t)(79); + _curvea0[129] = _4536; + uint16_t _4537 = (uint16_t)(80); + _curvea0[130] = _4537; + uint16_t _4538 = (uint16_t)(80); + _curvea0[131] = _4538; + uint16_t _4539 = (uint16_t)(81); + _curvea0[132] = _4539; + uint16_t _4540 = (uint16_t)(81); + _curvea0[133] = _4540; + uint16_t _4541 = (uint16_t)(82); + _curvea0[134] = _4541; + uint16_t _4542 = (uint16_t)(82); + _curvea0[135] = _4542; + uint16_t _4543 = (uint16_t)(82); + _curvea0[136] = _4543; + uint16_t _4544 = (uint16_t)(83); + _curvea0[137] = _4544; + uint16_t _4545 = (uint16_t)(83); + _curvea0[138] = _4545; + uint16_t _4546 = (uint16_t)(84); + _curvea0[139] = _4546; + uint16_t _4547 = (uint16_t)(84); + _curvea0[140] = _4547; + uint16_t _4548 = (uint16_t)(84); + _curvea0[141] = _4548; + uint16_t _4549 = (uint16_t)(85); + _curvea0[142] = _4549; + uint16_t _4550 = (uint16_t)(85); + _curvea0[143] = _4550; + uint16_t _4551 = (uint16_t)(86); + _curvea0[144] = _4551; + uint16_t _4552 = (uint16_t)(86); + _curvea0[145] = _4552; + uint16_t _4553 = (uint16_t)(86); + _curvea0[146] = _4553; + uint16_t _4554 = (uint16_t)(87); + _curvea0[147] = _4554; + uint16_t _4555 = (uint16_t)(87); + _curvea0[148] = _4555; + uint16_t _4556 = (uint16_t)(88); + _curvea0[149] = _4556; + uint16_t _4557 = (uint16_t)(88); + _curvea0[150] = _4557; + uint16_t _4558 = (uint16_t)(88); + _curvea0[151] = _4558; + uint16_t _4559 = (uint16_t)(89); + _curvea0[152] = _4559; + uint16_t _4560 = (uint16_t)(89); + _curvea0[153] = _4560; + uint16_t _4561 = (uint16_t)(90); + _curvea0[154] = _4561; + uint16_t _4562 = (uint16_t)(90); + _curvea0[155] = _4562; + uint16_t _4563 = (uint16_t)(90); + _curvea0[156] = _4563; + uint16_t _4564 = (uint16_t)(91); + _curvea0[157] = _4564; + uint16_t _4565 = (uint16_t)(91); + _curvea0[158] = _4565; + uint16_t _4566 = (uint16_t)(92); + _curvea0[159] = _4566; + uint16_t _4567 = (uint16_t)(92); + _curvea0[160] = _4567; + uint16_t _4568 = (uint16_t)(92); + _curvea0[161] = _4568; + uint16_t _4569 = (uint16_t)(93); + _curvea0[162] = _4569; + uint16_t _4570 = (uint16_t)(93); + _curvea0[163] = _4570; + uint16_t _4571 = (uint16_t)(93); + _curvea0[164] = _4571; + uint16_t _4572 = (uint16_t)(94); + _curvea0[165] = _4572; + uint16_t _4573 = (uint16_t)(94); + _curvea0[166] = _4573; + uint16_t _4574 = (uint16_t)(95); + _curvea0[167] = _4574; + uint16_t _4575 = (uint16_t)(95); + _curvea0[168] = _4575; + uint16_t _4576 = (uint16_t)(95); + _curvea0[169] = _4576; + uint16_t _4577 = (uint16_t)(96); + _curvea0[170] = _4577; + uint16_t _4578 = (uint16_t)(96); + _curvea0[171] = _4578; + uint16_t _4579 = (uint16_t)(97); + _curvea0[172] = _4579; + uint16_t _4580 = (uint16_t)(97); + _curvea0[173] = _4580; + uint16_t _4581 = (uint16_t)(97); + _curvea0[174] = _4581; + uint16_t _4582 = (uint16_t)(98); + _curvea0[175] = _4582; + uint16_t _4583 = (uint16_t)(98); + _curvea0[176] = _4583; + uint16_t _4584 = (uint16_t)(99); + _curvea0[177] = _4584; + uint16_t _4585 = (uint16_t)(99); + _curvea0[178] = _4585; + uint16_t _4586 = (uint16_t)(99); + _curvea0[179] = _4586; + uint16_t _4587 = (uint16_t)(100); + _curvea0[180] = _4587; + uint16_t _4588 = (uint16_t)(100); + _curvea0[181] = _4588; + uint16_t _4589 = (uint16_t)(100); + _curvea0[182] = _4589; + uint16_t _4590 = (uint16_t)(101); + _curvea0[183] = _4590; + uint16_t _4591 = (uint16_t)(101); + _curvea0[184] = _4591; + uint16_t _4592 = (uint16_t)(102); + _curvea0[185] = _4592; + uint16_t _4593 = (uint16_t)(102); + _curvea0[186] = _4593; + uint16_t _4594 = (uint16_t)(102); + _curvea0[187] = _4594; + uint16_t _4595 = (uint16_t)(103); + _curvea0[188] = _4595; + uint16_t _4596 = (uint16_t)(103); + _curvea0[189] = _4596; + uint16_t _4597 = (uint16_t)(103); + _curvea0[190] = _4597; + uint16_t _4598 = (uint16_t)(104); + _curvea0[191] = _4598; + uint16_t _4599 = (uint16_t)(104); + _curvea0[192] = _4599; + uint16_t _4600 = (uint16_t)(105); + _curvea0[193] = _4600; + uint16_t _4601 = (uint16_t)(105); + _curvea0[194] = _4601; + uint16_t _4602 = (uint16_t)(105); + _curvea0[195] = _4602; + uint16_t _4603 = (uint16_t)(106); + _curvea0[196] = _4603; + uint16_t _4604 = (uint16_t)(106); + _curvea0[197] = _4604; + uint16_t _4605 = (uint16_t)(106); + _curvea0[198] = _4605; + uint16_t _4606 = (uint16_t)(107); + _curvea0[199] = _4606; + uint16_t _4607 = (uint16_t)(107); + _curvea0[200] = _4607; + uint16_t _4608 = (uint16_t)(108); + _curvea0[201] = _4608; + uint16_t _4609 = (uint16_t)(108); + _curvea0[202] = _4609; + uint16_t _4610 = (uint16_t)(108); + _curvea0[203] = _4610; + uint16_t _4611 = (uint16_t)(109); + _curvea0[204] = _4611; + uint16_t _4612 = (uint16_t)(109); + _curvea0[205] = _4612; + uint16_t _4613 = (uint16_t)(109); + _curvea0[206] = _4613; + uint16_t _4614 = (uint16_t)(110); + _curvea0[207] = _4614; + uint16_t _4615 = (uint16_t)(110); + _curvea0[208] = _4615; + uint16_t _4616 = (uint16_t)(111); + _curvea0[209] = _4616; + uint16_t _4617 = (uint16_t)(111); + _curvea0[210] = _4617; + uint16_t _4618 = (uint16_t)(111); + _curvea0[211] = _4618; + uint16_t _4619 = (uint16_t)(112); + _curvea0[212] = _4619; + uint16_t _4620 = (uint16_t)(112); + _curvea0[213] = _4620; + uint16_t _4621 = (uint16_t)(112); + _curvea0[214] = _4621; + uint16_t _4622 = (uint16_t)(113); + _curvea0[215] = _4622; + uint16_t _4623 = (uint16_t)(113); + _curvea0[216] = _4623; + uint16_t _4624 = (uint16_t)(113); + _curvea0[217] = _4624; + uint16_t _4625 = (uint16_t)(114); + _curvea0[218] = _4625; + uint16_t _4626 = (uint16_t)(114); + _curvea0[219] = _4626; + uint16_t _4627 = (uint16_t)(115); + _curvea0[220] = _4627; + uint16_t _4628 = (uint16_t)(115); + _curvea0[221] = _4628; + uint16_t _4629 = (uint16_t)(115); + _curvea0[222] = _4629; + uint16_t _4630 = (uint16_t)(116); + _curvea0[223] = _4630; + uint16_t _4631 = (uint16_t)(116); + _curvea0[224] = _4631; + uint16_t _4632 = (uint16_t)(116); + _curvea0[225] = _4632; + uint16_t _4633 = (uint16_t)(117); + _curvea0[226] = _4633; + uint16_t _4634 = (uint16_t)(117); + _curvea0[227] = _4634; + uint16_t _4635 = (uint16_t)(117); + _curvea0[228] = _4635; + uint16_t _4636 = (uint16_t)(118); + _curvea0[229] = _4636; + uint16_t _4637 = (uint16_t)(118); + _curvea0[230] = _4637; + uint16_t _4638 = (uint16_t)(119); + _curvea0[231] = _4638; + uint16_t _4639 = (uint16_t)(119); + _curvea0[232] = _4639; + uint16_t _4640 = (uint16_t)(119); + _curvea0[233] = _4640; + uint16_t _4641 = (uint16_t)(120); + _curvea0[234] = _4641; + uint16_t _4642 = (uint16_t)(120); + _curvea0[235] = _4642; + uint16_t _4643 = (uint16_t)(120); + _curvea0[236] = _4643; + uint16_t _4644 = (uint16_t)(121); + _curvea0[237] = _4644; + uint16_t _4645 = (uint16_t)(121); + _curvea0[238] = _4645; + uint16_t _4646 = (uint16_t)(121); + _curvea0[239] = _4646; + uint16_t _4647 = (uint16_t)(122); + _curvea0[240] = _4647; + uint16_t _4648 = (uint16_t)(122); + _curvea0[241] = _4648; + uint16_t _4649 = (uint16_t)(123); + _curvea0[242] = _4649; + uint16_t _4650 = (uint16_t)(123); + _curvea0[243] = _4650; + uint16_t _4651 = (uint16_t)(123); + _curvea0[244] = _4651; + uint16_t _4652 = (uint16_t)(124); + _curvea0[245] = _4652; + uint16_t _4653 = (uint16_t)(124); + _curvea0[246] = _4653; + uint16_t _4654 = (uint16_t)(124); + _curvea0[247] = _4654; + uint16_t _4655 = (uint16_t)(125); + _curvea0[248] = _4655; + uint16_t _4656 = (uint16_t)(125); + _curvea0[249] = _4656; + uint16_t _4657 = (uint16_t)(125); + _curvea0[250] = _4657; + uint16_t _4658 = (uint16_t)(126); + _curvea0[251] = _4658; + uint16_t _4659 = (uint16_t)(126); + _curvea0[252] = _4659; + uint16_t _4660 = (uint16_t)(126); + _curvea0[253] = _4660; + uint16_t _4661 = (uint16_t)(127); + _curvea0[254] = _4661; + uint16_t _4662 = (uint16_t)(127); + _curvea0[255] = _4662; + uint16_t _4663 = (uint16_t)(128); + _curvea0[256] = _4663; + uint16_t _4664 = (uint16_t)(128); + _curvea0[257] = _4664; + uint16_t _4665 = (uint16_t)(128); + _curvea0[258] = _4665; + uint16_t _4666 = (uint16_t)(129); + _curvea0[259] = _4666; + uint16_t _4667 = (uint16_t)(129); + _curvea0[260] = _4667; + uint16_t _4668 = (uint16_t)(129); + _curvea0[261] = _4668; + uint16_t _4669 = (uint16_t)(130); + _curvea0[262] = _4669; + uint16_t _4670 = (uint16_t)(130); + _curvea0[263] = _4670; + uint16_t _4671 = (uint16_t)(130); + _curvea0[264] = _4671; + uint16_t _4672 = (uint16_t)(131); + _curvea0[265] = _4672; + uint16_t _4673 = (uint16_t)(131); + _curvea0[266] = _4673; + uint16_t _4674 = (uint16_t)(131); + _curvea0[267] = _4674; + uint16_t _4675 = (uint16_t)(132); + _curvea0[268] = _4675; + uint16_t _4676 = (uint16_t)(132); + _curvea0[269] = _4676; + uint16_t _4677 = (uint16_t)(132); + _curvea0[270] = _4677; + uint16_t _4678 = (uint16_t)(133); + _curvea0[271] = _4678; + uint16_t _4679 = (uint16_t)(133); + _curvea0[272] = _4679; + uint16_t _4680 = (uint16_t)(133); + _curvea0[273] = _4680; + uint16_t _4681 = (uint16_t)(134); + _curvea0[274] = _4681; + uint16_t _4682 = (uint16_t)(134); + _curvea0[275] = _4682; + uint16_t _4683 = (uint16_t)(134); + _curvea0[276] = _4683; + uint16_t _4684 = (uint16_t)(135); + _curvea0[277] = _4684; + uint16_t _4685 = (uint16_t)(135); + _curvea0[278] = _4685; + uint16_t _4686 = (uint16_t)(135); + _curvea0[279] = _4686; + uint16_t _4687 = (uint16_t)(136); + _curvea0[280] = _4687; + uint16_t _4688 = (uint16_t)(136); + _curvea0[281] = _4688; + uint16_t _4689 = (uint16_t)(136); + _curvea0[282] = _4689; + uint16_t _4690 = (uint16_t)(137); + _curvea0[283] = _4690; + uint16_t _4691 = (uint16_t)(137); + _curvea0[284] = _4691; + uint16_t _4692 = (uint16_t)(137); + _curvea0[285] = _4692; + uint16_t _4693 = (uint16_t)(138); + _curvea0[286] = _4693; + uint16_t _4694 = (uint16_t)(138); + _curvea0[287] = _4694; + uint16_t _4695 = (uint16_t)(138); + _curvea0[288] = _4695; + uint16_t _4696 = (uint16_t)(139); + _curvea0[289] = _4696; + uint16_t _4697 = (uint16_t)(139); + _curvea0[290] = _4697; + uint16_t _4698 = (uint16_t)(139); + _curvea0[291] = _4698; + uint16_t _4699 = (uint16_t)(140); + _curvea0[292] = _4699; + uint16_t _4700 = (uint16_t)(140); + _curvea0[293] = _4700; + uint16_t _4701 = (uint16_t)(140); + _curvea0[294] = _4701; + uint16_t _4702 = (uint16_t)(141); + _curvea0[295] = _4702; + uint16_t _4703 = (uint16_t)(141); + _curvea0[296] = _4703; + uint16_t _4704 = (uint16_t)(141); + _curvea0[297] = _4704; + uint16_t _4705 = (uint16_t)(141); + _curvea0[298] = _4705; + uint16_t _4706 = (uint16_t)(142); + _curvea0[299] = _4706; + uint16_t _4707 = (uint16_t)(142); + _curvea0[300] = _4707; + uint16_t _4708 = (uint16_t)(142); + _curvea0[301] = _4708; + uint16_t _4709 = (uint16_t)(143); + _curvea0[302] = _4709; + uint16_t _4710 = (uint16_t)(143); + _curvea0[303] = _4710; + uint16_t _4711 = (uint16_t)(143); + _curvea0[304] = _4711; + uint16_t _4712 = (uint16_t)(144); + _curvea0[305] = _4712; + uint16_t _4713 = (uint16_t)(144); + _curvea0[306] = _4713; + uint16_t _4714 = (uint16_t)(144); + _curvea0[307] = _4714; + uint16_t _4715 = (uint16_t)(145); + _curvea0[308] = _4715; + uint16_t _4716 = (uint16_t)(145); + _curvea0[309] = _4716; + uint16_t _4717 = (uint16_t)(145); + _curvea0[310] = _4717; + uint16_t _4718 = (uint16_t)(145); + _curvea0[311] = _4718; + uint16_t _4719 = (uint16_t)(146); + _curvea0[312] = _4719; + uint16_t _4720 = (uint16_t)(146); + _curvea0[313] = _4720; + uint16_t _4721 = (uint16_t)(146); + _curvea0[314] = _4721; + uint16_t _4722 = (uint16_t)(147); + _curvea0[315] = _4722; + uint16_t _4723 = (uint16_t)(147); + _curvea0[316] = _4723; + uint16_t _4724 = (uint16_t)(147); + _curvea0[317] = _4724; + uint16_t _4725 = (uint16_t)(148); + _curvea0[318] = _4725; + uint16_t _4726 = (uint16_t)(148); + _curvea0[319] = _4726; + uint16_t _4727 = (uint16_t)(148); + _curvea0[320] = _4727; + uint16_t _4728 = (uint16_t)(148); + _curvea0[321] = _4728; + uint16_t _4729 = (uint16_t)(149); + _curvea0[322] = _4729; + uint16_t _4730 = (uint16_t)(149); + _curvea0[323] = _4730; + uint16_t _4731 = (uint16_t)(149); + _curvea0[324] = _4731; + uint16_t _4732 = (uint16_t)(150); + _curvea0[325] = _4732; + uint16_t _4733 = (uint16_t)(150); + _curvea0[326] = _4733; + uint16_t _4734 = (uint16_t)(150); + _curvea0[327] = _4734; + uint16_t _4735 = (uint16_t)(150); + _curvea0[328] = _4735; + uint16_t _4736 = (uint16_t)(151); + _curvea0[329] = _4736; + uint16_t _4737 = (uint16_t)(151); + _curvea0[330] = _4737; + uint16_t _4738 = (uint16_t)(151); + _curvea0[331] = _4738; + uint16_t _4739 = (uint16_t)(152); + _curvea0[332] = _4739; + uint16_t _4740 = (uint16_t)(152); + _curvea0[333] = _4740; + uint16_t _4741 = (uint16_t)(152); + _curvea0[334] = _4741; + uint16_t _4742 = (uint16_t)(152); + _curvea0[335] = _4742; + uint16_t _4743 = (uint16_t)(153); + _curvea0[336] = _4743; + uint16_t _4744 = (uint16_t)(153); + _curvea0[337] = _4744; + uint16_t _4745 = (uint16_t)(153); + _curvea0[338] = _4745; + uint16_t _4746 = (uint16_t)(154); + _curvea0[339] = _4746; + uint16_t _4747 = (uint16_t)(154); + _curvea0[340] = _4747; + uint16_t _4748 = (uint16_t)(154); + _curvea0[341] = _4748; + uint16_t _4749 = (uint16_t)(154); + _curvea0[342] = _4749; + uint16_t _4750 = (uint16_t)(155); + _curvea0[343] = _4750; + uint16_t _4751 = (uint16_t)(155); + _curvea0[344] = _4751; + uint16_t _4752 = (uint16_t)(155); + _curvea0[345] = _4752; + uint16_t _4753 = (uint16_t)(156); + _curvea0[346] = _4753; + uint16_t _4754 = (uint16_t)(156); + _curvea0[347] = _4754; + uint16_t _4755 = (uint16_t)(156); + _curvea0[348] = _4755; + uint16_t _4756 = (uint16_t)(156); + _curvea0[349] = _4756; + uint16_t _4757 = (uint16_t)(157); + _curvea0[350] = _4757; + uint16_t _4758 = (uint16_t)(157); + _curvea0[351] = _4758; + uint16_t _4759 = (uint16_t)(157); + _curvea0[352] = _4759; + uint16_t _4760 = (uint16_t)(157); + _curvea0[353] = _4760; + uint16_t _4761 = (uint16_t)(158); + _curvea0[354] = _4761; + uint16_t _4762 = (uint16_t)(158); + _curvea0[355] = _4762; + uint16_t _4763 = (uint16_t)(158); + _curvea0[356] = _4763; + uint16_t _4764 = (uint16_t)(159); + _curvea0[357] = _4764; + uint16_t _4765 = (uint16_t)(159); + _curvea0[358] = _4765; + uint16_t _4766 = (uint16_t)(159); + _curvea0[359] = _4766; + uint16_t _4767 = (uint16_t)(159); + _curvea0[360] = _4767; + uint16_t _4768 = (uint16_t)(160); + _curvea0[361] = _4768; + uint16_t _4769 = (uint16_t)(160); + _curvea0[362] = _4769; + uint16_t _4770 = (uint16_t)(160); + _curvea0[363] = _4770; + uint16_t _4771 = (uint16_t)(160); + _curvea0[364] = _4771; + uint16_t _4772 = (uint16_t)(161); + _curvea0[365] = _4772; + uint16_t _4773 = (uint16_t)(161); + _curvea0[366] = _4773; + uint16_t _4774 = (uint16_t)(161); + _curvea0[367] = _4774; + uint16_t _4775 = (uint16_t)(161); + _curvea0[368] = _4775; + uint16_t _4776 = (uint16_t)(162); + _curvea0[369] = _4776; + uint16_t _4777 = (uint16_t)(162); + _curvea0[370] = _4777; + uint16_t _4778 = (uint16_t)(162); + _curvea0[371] = _4778; + uint16_t _4779 = (uint16_t)(162); + _curvea0[372] = _4779; + uint16_t _4780 = (uint16_t)(163); + _curvea0[373] = _4780; + uint16_t _4781 = (uint16_t)(163); + _curvea0[374] = _4781; + uint16_t _4782 = (uint16_t)(163); + _curvea0[375] = _4782; + uint16_t _4783 = (uint16_t)(163); + _curvea0[376] = _4783; + uint16_t _4784 = (uint16_t)(164); + _curvea0[377] = _4784; + uint16_t _4785 = (uint16_t)(164); + _curvea0[378] = _4785; + uint16_t _4786 = (uint16_t)(164); + _curvea0[379] = _4786; + uint16_t _4787 = (uint16_t)(164); + _curvea0[380] = _4787; + uint16_t _4788 = (uint16_t)(165); + _curvea0[381] = _4788; + uint16_t _4789 = (uint16_t)(165); + _curvea0[382] = _4789; + uint16_t _4790 = (uint16_t)(165); + _curvea0[383] = _4790; + uint16_t _4791 = (uint16_t)(166); + _curvea0[384] = _4791; + uint16_t _4792 = (uint16_t)(166); + _curvea0[385] = _4792; + uint16_t _4793 = (uint16_t)(166); + _curvea0[386] = _4793; + uint16_t _4794 = (uint16_t)(166); + _curvea0[387] = _4794; + uint16_t _4795 = (uint16_t)(167); + _curvea0[388] = _4795; + uint16_t _4796 = (uint16_t)(167); + _curvea0[389] = _4796; + uint16_t _4797 = (uint16_t)(167); + _curvea0[390] = _4797; + uint16_t _4798 = (uint16_t)(167); + _curvea0[391] = _4798; + uint16_t _4799 = (uint16_t)(167); + _curvea0[392] = _4799; + uint16_t _4800 = (uint16_t)(168); + _curvea0[393] = _4800; + uint16_t _4801 = (uint16_t)(168); + _curvea0[394] = _4801; + uint16_t _4802 = (uint16_t)(168); + _curvea0[395] = _4802; + uint16_t _4803 = (uint16_t)(168); + _curvea0[396] = _4803; + uint16_t _4804 = (uint16_t)(169); + _curvea0[397] = _4804; + uint16_t _4805 = (uint16_t)(169); + _curvea0[398] = _4805; + uint16_t _4806 = (uint16_t)(169); + _curvea0[399] = _4806; + uint16_t _4807 = (uint16_t)(169); + _curvea0[400] = _4807; + uint16_t _4808 = (uint16_t)(170); + _curvea0[401] = _4808; + uint16_t _4809 = (uint16_t)(170); + _curvea0[402] = _4809; + uint16_t _4810 = (uint16_t)(170); + _curvea0[403] = _4810; + uint16_t _4811 = (uint16_t)(170); + _curvea0[404] = _4811; + uint16_t _4812 = (uint16_t)(171); + _curvea0[405] = _4812; + uint16_t _4813 = (uint16_t)(171); + _curvea0[406] = _4813; + uint16_t _4814 = (uint16_t)(171); + _curvea0[407] = _4814; + uint16_t _4815 = (uint16_t)(171); + _curvea0[408] = _4815; + uint16_t _4816 = (uint16_t)(172); + _curvea0[409] = _4816; + uint16_t _4817 = (uint16_t)(172); + _curvea0[410] = _4817; + uint16_t _4818 = (uint16_t)(172); + _curvea0[411] = _4818; + uint16_t _4819 = (uint16_t)(172); + _curvea0[412] = _4819; + uint16_t _4820 = (uint16_t)(173); + _curvea0[413] = _4820; + uint16_t _4821 = (uint16_t)(173); + _curvea0[414] = _4821; + uint16_t _4822 = (uint16_t)(173); + _curvea0[415] = _4822; + uint16_t _4823 = (uint16_t)(173); + _curvea0[416] = _4823; + uint16_t _4824 = (uint16_t)(173); + _curvea0[417] = _4824; + uint16_t _4825 = (uint16_t)(174); + _curvea0[418] = _4825; + uint16_t _4826 = (uint16_t)(174); + _curvea0[419] = _4826; + uint16_t _4827 = (uint16_t)(174); + _curvea0[420] = _4827; + uint16_t _4828 = (uint16_t)(174); + _curvea0[421] = _4828; + uint16_t _4829 = (uint16_t)(175); + _curvea0[422] = _4829; + uint16_t _4830 = (uint16_t)(175); + _curvea0[423] = _4830; + uint16_t _4831 = (uint16_t)(175); + _curvea0[424] = _4831; + uint16_t _4832 = (uint16_t)(175); + _curvea0[425] = _4832; + uint16_t _4833 = (uint16_t)(176); + _curvea0[426] = _4833; + uint16_t _4834 = (uint16_t)(176); + _curvea0[427] = _4834; + uint16_t _4835 = (uint16_t)(176); + _curvea0[428] = _4835; + uint16_t _4836 = (uint16_t)(176); + _curvea0[429] = _4836; + uint16_t _4837 = (uint16_t)(176); + _curvea0[430] = _4837; + uint16_t _4838 = (uint16_t)(177); + _curvea0[431] = _4838; + uint16_t _4839 = (uint16_t)(177); + _curvea0[432] = _4839; + uint16_t _4840 = (uint16_t)(177); + _curvea0[433] = _4840; + uint16_t _4841 = (uint16_t)(177); + _curvea0[434] = _4841; + uint16_t _4842 = (uint16_t)(178); + _curvea0[435] = _4842; + uint16_t _4843 = (uint16_t)(178); + _curvea0[436] = _4843; + uint16_t _4844 = (uint16_t)(178); + _curvea0[437] = _4844; + uint16_t _4845 = (uint16_t)(178); + _curvea0[438] = _4845; + uint16_t _4846 = (uint16_t)(178); + _curvea0[439] = _4846; + uint16_t _4847 = (uint16_t)(179); + _curvea0[440] = _4847; + uint16_t _4848 = (uint16_t)(179); + _curvea0[441] = _4848; + uint16_t _4849 = (uint16_t)(179); + _curvea0[442] = _4849; + uint16_t _4850 = (uint16_t)(179); + _curvea0[443] = _4850; + uint16_t _4851 = (uint16_t)(180); + _curvea0[444] = _4851; + uint16_t _4852 = (uint16_t)(180); + _curvea0[445] = _4852; + uint16_t _4853 = (uint16_t)(180); + _curvea0[446] = _4853; + uint16_t _4854 = (uint16_t)(180); + _curvea0[447] = _4854; + uint16_t _4855 = (uint16_t)(180); + _curvea0[448] = _4855; + uint16_t _4856 = (uint16_t)(181); + _curvea0[449] = _4856; + uint16_t _4857 = (uint16_t)(181); + _curvea0[450] = _4857; + uint16_t _4858 = (uint16_t)(181); + _curvea0[451] = _4858; + uint16_t _4859 = (uint16_t)(181); + _curvea0[452] = _4859; + uint16_t _4860 = (uint16_t)(181); + _curvea0[453] = _4860; + uint16_t _4861 = (uint16_t)(182); + _curvea0[454] = _4861; + uint16_t _4862 = (uint16_t)(182); + _curvea0[455] = _4862; + uint16_t _4863 = (uint16_t)(182); + _curvea0[456] = _4863; + uint16_t _4864 = (uint16_t)(182); + _curvea0[457] = _4864; + uint16_t _4865 = (uint16_t)(183); + _curvea0[458] = _4865; + uint16_t _4866 = (uint16_t)(183); + _curvea0[459] = _4866; + uint16_t _4867 = (uint16_t)(183); + _curvea0[460] = _4867; + uint16_t _4868 = (uint16_t)(183); + _curvea0[461] = _4868; + uint16_t _4869 = (uint16_t)(183); + _curvea0[462] = _4869; + uint16_t _4870 = (uint16_t)(184); + _curvea0[463] = _4870; + uint16_t _4871 = (uint16_t)(184); + _curvea0[464] = _4871; + uint16_t _4872 = (uint16_t)(184); + _curvea0[465] = _4872; + uint16_t _4873 = (uint16_t)(184); + _curvea0[466] = _4873; + uint16_t _4874 = (uint16_t)(184); + _curvea0[467] = _4874; + uint16_t _4875 = (uint16_t)(185); + _curvea0[468] = _4875; + uint16_t _4876 = (uint16_t)(185); + _curvea0[469] = _4876; + uint16_t _4877 = (uint16_t)(185); + _curvea0[470] = _4877; + uint16_t _4878 = (uint16_t)(185); + _curvea0[471] = _4878; + uint16_t _4879 = (uint16_t)(185); + _curvea0[472] = _4879; + uint16_t _4880 = (uint16_t)(186); + _curvea0[473] = _4880; + uint16_t _4881 = (uint16_t)(186); + _curvea0[474] = _4881; + uint16_t _4882 = (uint16_t)(186); + _curvea0[475] = _4882; + uint16_t _4883 = (uint16_t)(186); + _curvea0[476] = _4883; + uint16_t _4884 = (uint16_t)(187); + _curvea0[477] = _4884; + uint16_t _4885 = (uint16_t)(187); + _curvea0[478] = _4885; + uint16_t _4886 = (uint16_t)(187); + _curvea0[479] = _4886; + uint16_t _4887 = (uint16_t)(187); + _curvea0[480] = _4887; + uint16_t _4888 = (uint16_t)(187); + _curvea0[481] = _4888; + uint16_t _4889 = (uint16_t)(188); + _curvea0[482] = _4889; + uint16_t _4890 = (uint16_t)(188); + _curvea0[483] = _4890; + uint16_t _4891 = (uint16_t)(188); + _curvea0[484] = _4891; + uint16_t _4892 = (uint16_t)(188); + _curvea0[485] = _4892; + uint16_t _4893 = (uint16_t)(188); + _curvea0[486] = _4893; + uint16_t _4894 = (uint16_t)(189); + _curvea0[487] = _4894; + uint16_t _4895 = (uint16_t)(189); + _curvea0[488] = _4895; + uint16_t _4896 = (uint16_t)(189); + _curvea0[489] = _4896; + uint16_t _4897 = (uint16_t)(189); + _curvea0[490] = _4897; + uint16_t _4898 = (uint16_t)(189); + _curvea0[491] = _4898; + uint16_t _4899 = (uint16_t)(190); + _curvea0[492] = _4899; + uint16_t _4900 = (uint16_t)(190); + _curvea0[493] = _4900; + uint16_t _4901 = (uint16_t)(190); + _curvea0[494] = _4901; + uint16_t _4902 = (uint16_t)(190); + _curvea0[495] = _4902; + uint16_t _4903 = (uint16_t)(190); + _curvea0[496] = _4903; + uint16_t _4904 = (uint16_t)(190); + _curvea0[497] = _4904; + uint16_t _4905 = (uint16_t)(191); + _curvea0[498] = _4905; + uint16_t _4906 = (uint16_t)(191); + _curvea0[499] = _4906; + uint16_t _4907 = (uint16_t)(191); + _curvea0[500] = _4907; + uint16_t _4908 = (uint16_t)(191); + _curvea0[501] = _4908; + uint16_t _4909 = (uint16_t)(191); + _curvea0[502] = _4909; + uint16_t _4910 = (uint16_t)(192); + _curvea0[503] = _4910; + uint16_t _4911 = (uint16_t)(192); + _curvea0[504] = _4911; + uint16_t _4912 = (uint16_t)(192); + _curvea0[505] = _4912; + uint16_t _4913 = (uint16_t)(192); + _curvea0[506] = _4913; + uint16_t _4914 = (uint16_t)(192); + _curvea0[507] = _4914; + uint16_t _4915 = (uint16_t)(193); + _curvea0[508] = _4915; + uint16_t _4916 = (uint16_t)(193); + _curvea0[509] = _4916; + uint16_t _4917 = (uint16_t)(193); + _curvea0[510] = _4917; + uint16_t _4918 = (uint16_t)(193); + _curvea0[511] = _4918; + uint16_t _4919 = (uint16_t)(193); + _curvea0[512] = _4919; + uint16_t _4920 = (uint16_t)(194); + _curvea0[513] = _4920; + uint16_t _4921 = (uint16_t)(194); + _curvea0[514] = _4921; + uint16_t _4922 = (uint16_t)(194); + _curvea0[515] = _4922; + uint16_t _4923 = (uint16_t)(194); + _curvea0[516] = _4923; + uint16_t _4924 = (uint16_t)(194); + _curvea0[517] = _4924; + uint16_t _4925 = (uint16_t)(195); + _curvea0[518] = _4925; + uint16_t _4926 = (uint16_t)(195); + _curvea0[519] = _4926; + uint16_t _4927 = (uint16_t)(195); + _curvea0[520] = _4927; + uint16_t _4928 = (uint16_t)(195); + _curvea0[521] = _4928; + uint16_t _4929 = (uint16_t)(195); + _curvea0[522] = _4929; + uint16_t _4930 = (uint16_t)(195); + _curvea0[523] = _4930; + uint16_t _4931 = (uint16_t)(196); + _curvea0[524] = _4931; + uint16_t _4932 = (uint16_t)(196); + _curvea0[525] = _4932; + uint16_t _4933 = (uint16_t)(196); + _curvea0[526] = _4933; + uint16_t _4934 = (uint16_t)(196); + _curvea0[527] = _4934; + uint16_t _4935 = (uint16_t)(196); + _curvea0[528] = _4935; + uint16_t _4936 = (uint16_t)(197); + _curvea0[529] = _4936; + uint16_t _4937 = (uint16_t)(197); + _curvea0[530] = _4937; + uint16_t _4938 = (uint16_t)(197); + _curvea0[531] = _4938; + uint16_t _4939 = (uint16_t)(197); + _curvea0[532] = _4939; + uint16_t _4940 = (uint16_t)(197); + _curvea0[533] = _4940; + uint16_t _4941 = (uint16_t)(197); + _curvea0[534] = _4941; + uint16_t _4942 = (uint16_t)(198); + _curvea0[535] = _4942; + uint16_t _4943 = (uint16_t)(198); + _curvea0[536] = _4943; + uint16_t _4944 = (uint16_t)(198); + _curvea0[537] = _4944; + uint16_t _4945 = (uint16_t)(198); + _curvea0[538] = _4945; + uint16_t _4946 = (uint16_t)(198); + _curvea0[539] = _4946; + uint16_t _4947 = (uint16_t)(199); + _curvea0[540] = _4947; + uint16_t _4948 = (uint16_t)(199); + _curvea0[541] = _4948; + uint16_t _4949 = (uint16_t)(199); + _curvea0[542] = _4949; + uint16_t _4950 = (uint16_t)(199); + _curvea0[543] = _4950; + uint16_t _4951 = (uint16_t)(199); + _curvea0[544] = _4951; + uint16_t _4952 = (uint16_t)(199); + _curvea0[545] = _4952; + uint16_t _4953 = (uint16_t)(200); + _curvea0[546] = _4953; + uint16_t _4954 = (uint16_t)(200); + _curvea0[547] = _4954; + uint16_t _4955 = (uint16_t)(200); + _curvea0[548] = _4955; + uint16_t _4956 = (uint16_t)(200); + _curvea0[549] = _4956; + uint16_t _4957 = (uint16_t)(200); + _curvea0[550] = _4957; + uint16_t _4958 = (uint16_t)(200); + _curvea0[551] = _4958; + uint16_t _4959 = (uint16_t)(201); + _curvea0[552] = _4959; + uint16_t _4960 = (uint16_t)(201); + _curvea0[553] = _4960; + uint16_t _4961 = (uint16_t)(201); + _curvea0[554] = _4961; + uint16_t _4962 = (uint16_t)(201); + _curvea0[555] = _4962; + uint16_t _4963 = (uint16_t)(201); + _curvea0[556] = _4963; + uint16_t _4964 = (uint16_t)(202); + _curvea0[557] = _4964; + uint16_t _4965 = (uint16_t)(202); + _curvea0[558] = _4965; + uint16_t _4966 = (uint16_t)(202); + _curvea0[559] = _4966; + uint16_t _4967 = (uint16_t)(202); + _curvea0[560] = _4967; + uint16_t _4968 = (uint16_t)(202); + _curvea0[561] = _4968; + uint16_t _4969 = (uint16_t)(202); + _curvea0[562] = _4969; + uint16_t _4970 = (uint16_t)(203); + _curvea0[563] = _4970; + uint16_t _4971 = (uint16_t)(203); + _curvea0[564] = _4971; + uint16_t _4972 = (uint16_t)(203); + _curvea0[565] = _4972; + uint16_t _4973 = (uint16_t)(203); + _curvea0[566] = _4973; + uint16_t _4974 = (uint16_t)(203); + _curvea0[567] = _4974; + uint16_t _4975 = (uint16_t)(203); + _curvea0[568] = _4975; + uint16_t _4976 = (uint16_t)(204); + _curvea0[569] = _4976; + uint16_t _4977 = (uint16_t)(204); + _curvea0[570] = _4977; + uint16_t _4978 = (uint16_t)(204); + _curvea0[571] = _4978; + uint16_t _4979 = (uint16_t)(204); + _curvea0[572] = _4979; + uint16_t _4980 = (uint16_t)(204); + _curvea0[573] = _4980; + uint16_t _4981 = (uint16_t)(204); + _curvea0[574] = _4981; + uint16_t _4982 = (uint16_t)(205); + _curvea0[575] = _4982; + uint16_t _4983 = (uint16_t)(205); + _curvea0[576] = _4983; + uint16_t _4984 = (uint16_t)(205); + _curvea0[577] = _4984; + uint16_t _4985 = (uint16_t)(205); + _curvea0[578] = _4985; + uint16_t _4986 = (uint16_t)(205); + _curvea0[579] = _4986; + uint16_t _4987 = (uint16_t)(205); + _curvea0[580] = _4987; + uint16_t _4988 = (uint16_t)(206); + _curvea0[581] = _4988; + uint16_t _4989 = (uint16_t)(206); + _curvea0[582] = _4989; + uint16_t _4990 = (uint16_t)(206); + _curvea0[583] = _4990; + uint16_t _4991 = (uint16_t)(206); + _curvea0[584] = _4991; + uint16_t _4992 = (uint16_t)(206); + _curvea0[585] = _4992; + uint16_t _4993 = (uint16_t)(206); + _curvea0[586] = _4993; + uint16_t _4994 = (uint16_t)(207); + _curvea0[587] = _4994; + uint16_t _4995 = (uint16_t)(207); + _curvea0[588] = _4995; + uint16_t _4996 = (uint16_t)(207); + _curvea0[589] = _4996; + uint16_t _4997 = (uint16_t)(207); + _curvea0[590] = _4997; + uint16_t _4998 = (uint16_t)(207); + _curvea0[591] = _4998; + uint16_t _4999 = (uint16_t)(207); + _curvea0[592] = _4999; + uint16_t _5000 = (uint16_t)(208); + _curvea0[593] = _5000; + uint16_t _5001 = (uint16_t)(208); + _curvea0[594] = _5001; + uint16_t _5002 = (uint16_t)(208); + _curvea0[595] = _5002; + uint16_t _5003 = (uint16_t)(208); + _curvea0[596] = _5003; + uint16_t _5004 = (uint16_t)(208); + _curvea0[597] = _5004; + uint16_t _5005 = (uint16_t)(208); + _curvea0[598] = _5005; + uint16_t _5006 = (uint16_t)(209); + _curvea0[599] = _5006; + uint16_t _5007 = (uint16_t)(209); + _curvea0[600] = _5007; + uint16_t _5008 = (uint16_t)(209); + _curvea0[601] = _5008; + uint16_t _5009 = (uint16_t)(209); + _curvea0[602] = _5009; + uint16_t _5010 = (uint16_t)(209); + _curvea0[603] = _5010; + uint16_t _5011 = (uint16_t)(209); + _curvea0[604] = _5011; + uint16_t _5012 = (uint16_t)(209); + _curvea0[605] = _5012; + uint16_t _5013 = (uint16_t)(210); + _curvea0[606] = _5013; + uint16_t _5014 = (uint16_t)(210); + _curvea0[607] = _5014; + uint16_t _5015 = (uint16_t)(210); + _curvea0[608] = _5015; + uint16_t _5016 = (uint16_t)(210); + _curvea0[609] = _5016; + uint16_t _5017 = (uint16_t)(210); + _curvea0[610] = _5017; + uint16_t _5018 = (uint16_t)(210); + _curvea0[611] = _5018; + uint16_t _5019 = (uint16_t)(211); + _curvea0[612] = _5019; + uint16_t _5020 = (uint16_t)(211); + _curvea0[613] = _5020; + uint16_t _5021 = (uint16_t)(211); + _curvea0[614] = _5021; + uint16_t _5022 = (uint16_t)(211); + _curvea0[615] = _5022; + uint16_t _5023 = (uint16_t)(211); + _curvea0[616] = _5023; + uint16_t _5024 = (uint16_t)(211); + _curvea0[617] = _5024; + uint16_t _5025 = (uint16_t)(211); + _curvea0[618] = _5025; + uint16_t _5026 = (uint16_t)(212); + _curvea0[619] = _5026; + uint16_t _5027 = (uint16_t)(212); + _curvea0[620] = _5027; + uint16_t _5028 = (uint16_t)(212); + _curvea0[621] = _5028; + uint16_t _5029 = (uint16_t)(212); + _curvea0[622] = _5029; + uint16_t _5030 = (uint16_t)(212); + _curvea0[623] = _5030; + uint16_t _5031 = (uint16_t)(212); + _curvea0[624] = _5031; + uint16_t _5032 = (uint16_t)(213); + _curvea0[625] = _5032; + uint16_t _5033 = (uint16_t)(213); + _curvea0[626] = _5033; + uint16_t _5034 = (uint16_t)(213); + _curvea0[627] = _5034; + uint16_t _5035 = (uint16_t)(213); + _curvea0[628] = _5035; + uint16_t _5036 = (uint16_t)(213); + _curvea0[629] = _5036; + uint16_t _5037 = (uint16_t)(213); + _curvea0[630] = _5037; + uint16_t _5038 = (uint16_t)(213); + _curvea0[631] = _5038; + uint16_t _5039 = (uint16_t)(214); + _curvea0[632] = _5039; + uint16_t _5040 = (uint16_t)(214); + _curvea0[633] = _5040; + uint16_t _5041 = (uint16_t)(214); + _curvea0[634] = _5041; + uint16_t _5042 = (uint16_t)(214); + _curvea0[635] = _5042; + uint16_t _5043 = (uint16_t)(214); + _curvea0[636] = _5043; + uint16_t _5044 = (uint16_t)(214); + _curvea0[637] = _5044; + uint16_t _5045 = (uint16_t)(214); + _curvea0[638] = _5045; + uint16_t _5046 = (uint16_t)(215); + _curvea0[639] = _5046; + uint16_t _5047 = (uint16_t)(215); + _curvea0[640] = _5047; + uint16_t _5048 = (uint16_t)(215); + _curvea0[641] = _5048; + uint16_t _5049 = (uint16_t)(215); + _curvea0[642] = _5049; + uint16_t _5050 = (uint16_t)(215); + _curvea0[643] = _5050; + uint16_t _5051 = (uint16_t)(215); + _curvea0[644] = _5051; + uint16_t _5052 = (uint16_t)(216); + _curvea0[645] = _5052; + uint16_t _5053 = (uint16_t)(216); + _curvea0[646] = _5053; + uint16_t _5054 = (uint16_t)(216); + _curvea0[647] = _5054; + uint16_t _5055 = (uint16_t)(216); + _curvea0[648] = _5055; + uint16_t _5056 = (uint16_t)(216); + _curvea0[649] = _5056; + uint16_t _5057 = (uint16_t)(216); + _curvea0[650] = _5057; + uint16_t _5058 = (uint16_t)(216); + _curvea0[651] = _5058; + uint16_t _5059 = (uint16_t)(217); + _curvea0[652] = _5059; + uint16_t _5060 = (uint16_t)(217); + _curvea0[653] = _5060; + uint16_t _5061 = (uint16_t)(217); + _curvea0[654] = _5061; + uint16_t _5062 = (uint16_t)(217); + _curvea0[655] = _5062; + uint16_t _5063 = (uint16_t)(217); + _curvea0[656] = _5063; + uint16_t _5064 = (uint16_t)(217); + _curvea0[657] = _5064; + uint16_t _5065 = (uint16_t)(217); + _curvea0[658] = _5065; + uint16_t _5066 = (uint16_t)(218); + _curvea0[659] = _5066; + uint16_t _5067 = (uint16_t)(218); + _curvea0[660] = _5067; + uint16_t _5068 = (uint16_t)(218); + _curvea0[661] = _5068; + uint16_t _5069 = (uint16_t)(218); + _curvea0[662] = _5069; + uint16_t _5070 = (uint16_t)(218); + _curvea0[663] = _5070; + uint16_t _5071 = (uint16_t)(218); + _curvea0[664] = _5071; + uint16_t _5072 = (uint16_t)(218); + _curvea0[665] = _5072; + uint16_t _5073 = (uint16_t)(219); + _curvea0[666] = _5073; + uint16_t _5074 = (uint16_t)(219); + _curvea0[667] = _5074; + uint16_t _5075 = (uint16_t)(219); + _curvea0[668] = _5075; + uint16_t _5076 = (uint16_t)(219); + _curvea0[669] = _5076; + uint16_t _5077 = (uint16_t)(219); + _curvea0[670] = _5077; + uint16_t _5078 = (uint16_t)(219); + _curvea0[671] = _5078; + uint16_t _5079 = (uint16_t)(219); + _curvea0[672] = _5079; + uint16_t _5080 = (uint16_t)(220); + _curvea0[673] = _5080; + uint16_t _5081 = (uint16_t)(220); + _curvea0[674] = _5081; + uint16_t _5082 = (uint16_t)(220); + _curvea0[675] = _5082; + uint16_t _5083 = (uint16_t)(220); + _curvea0[676] = _5083; + uint16_t _5084 = (uint16_t)(220); + _curvea0[677] = _5084; + uint16_t _5085 = (uint16_t)(220); + _curvea0[678] = _5085; + uint16_t _5086 = (uint16_t)(220); + _curvea0[679] = _5086; + uint16_t _5087 = (uint16_t)(220); + _curvea0[680] = _5087; + uint16_t _5088 = (uint16_t)(221); + _curvea0[681] = _5088; + uint16_t _5089 = (uint16_t)(221); + _curvea0[682] = _5089; + uint16_t _5090 = (uint16_t)(221); + _curvea0[683] = _5090; + uint16_t _5091 = (uint16_t)(221); + _curvea0[684] = _5091; + uint16_t _5092 = (uint16_t)(221); + _curvea0[685] = _5092; + uint16_t _5093 = (uint16_t)(221); + _curvea0[686] = _5093; + uint16_t _5094 = (uint16_t)(221); + _curvea0[687] = _5094; + uint16_t _5095 = (uint16_t)(222); + _curvea0[688] = _5095; + uint16_t _5096 = (uint16_t)(222); + _curvea0[689] = _5096; + uint16_t _5097 = (uint16_t)(222); + _curvea0[690] = _5097; + uint16_t _5098 = (uint16_t)(222); + _curvea0[691] = _5098; + uint16_t _5099 = (uint16_t)(222); + _curvea0[692] = _5099; + uint16_t _5100 = (uint16_t)(222); + _curvea0[693] = _5100; + uint16_t _5101 = (uint16_t)(222); + _curvea0[694] = _5101; + uint16_t _5102 = (uint16_t)(223); + _curvea0[695] = _5102; + uint16_t _5103 = (uint16_t)(223); + _curvea0[696] = _5103; + uint16_t _5104 = (uint16_t)(223); + _curvea0[697] = _5104; + uint16_t _5105 = (uint16_t)(223); + _curvea0[698] = _5105; + uint16_t _5106 = (uint16_t)(223); + _curvea0[699] = _5106; + uint16_t _5107 = (uint16_t)(223); + _curvea0[700] = _5107; + uint16_t _5108 = (uint16_t)(223); + _curvea0[701] = _5108; + uint16_t _5109 = (uint16_t)(223); + _curvea0[702] = _5109; + uint16_t _5110 = (uint16_t)(224); + _curvea0[703] = _5110; + uint16_t _5111 = (uint16_t)(224); + _curvea0[704] = _5111; + uint16_t _5112 = (uint16_t)(224); + _curvea0[705] = _5112; + uint16_t _5113 = (uint16_t)(224); + _curvea0[706] = _5113; + uint16_t _5114 = (uint16_t)(224); + _curvea0[707] = _5114; + uint16_t _5115 = (uint16_t)(224); + _curvea0[708] = _5115; + uint16_t _5116 = (uint16_t)(224); + _curvea0[709] = _5116; + uint16_t _5117 = (uint16_t)(224); + _curvea0[710] = _5117; + uint16_t _5118 = (uint16_t)(225); + _curvea0[711] = _5118; + uint16_t _5119 = (uint16_t)(225); + _curvea0[712] = _5119; + uint16_t _5120 = (uint16_t)(225); + _curvea0[713] = _5120; + uint16_t _5121 = (uint16_t)(225); + _curvea0[714] = _5121; + uint16_t _5122 = (uint16_t)(225); + _curvea0[715] = _5122; + uint16_t _5123 = (uint16_t)(225); + _curvea0[716] = _5123; + uint16_t _5124 = (uint16_t)(225); + _curvea0[717] = _5124; + uint16_t _5125 = (uint16_t)(226); + _curvea0[718] = _5125; + uint16_t _5126 = (uint16_t)(226); + _curvea0[719] = _5126; + uint16_t _5127 = (uint16_t)(226); + _curvea0[720] = _5127; + uint16_t _5128 = (uint16_t)(226); + _curvea0[721] = _5128; + uint16_t _5129 = (uint16_t)(226); + _curvea0[722] = _5129; + uint16_t _5130 = (uint16_t)(226); + _curvea0[723] = _5130; + uint16_t _5131 = (uint16_t)(226); + _curvea0[724] = _5131; + uint16_t _5132 = (uint16_t)(226); + _curvea0[725] = _5132; + uint16_t _5133 = (uint16_t)(227); + _curvea0[726] = _5133; + uint16_t _5134 = (uint16_t)(227); + _curvea0[727] = _5134; + uint16_t _5135 = (uint16_t)(227); + _curvea0[728] = _5135; + uint16_t _5136 = (uint16_t)(227); + _curvea0[729] = _5136; + uint16_t _5137 = (uint16_t)(227); + _curvea0[730] = _5137; + uint16_t _5138 = (uint16_t)(227); + _curvea0[731] = _5138; + uint16_t _5139 = (uint16_t)(227); + _curvea0[732] = _5139; + uint16_t _5140 = (uint16_t)(227); + _curvea0[733] = _5140; + uint16_t _5141 = (uint16_t)(228); + _curvea0[734] = _5141; + uint16_t _5142 = (uint16_t)(228); + _curvea0[735] = _5142; + uint16_t _5143 = (uint16_t)(228); + _curvea0[736] = _5143; + uint16_t _5144 = (uint16_t)(228); + _curvea0[737] = _5144; + uint16_t _5145 = (uint16_t)(228); + _curvea0[738] = _5145; + uint16_t _5146 = (uint16_t)(228); + _curvea0[739] = _5146; + uint16_t _5147 = (uint16_t)(228); + _curvea0[740] = _5147; + uint16_t _5148 = (uint16_t)(228); + _curvea0[741] = _5148; + uint16_t _5149 = (uint16_t)(228); + _curvea0[742] = _5149; + uint16_t _5150 = (uint16_t)(229); + _curvea0[743] = _5150; + uint16_t _5151 = (uint16_t)(229); + _curvea0[744] = _5151; + uint16_t _5152 = (uint16_t)(229); + _curvea0[745] = _5152; + uint16_t _5153 = (uint16_t)(229); + _curvea0[746] = _5153; + uint16_t _5154 = (uint16_t)(229); + _curvea0[747] = _5154; + uint16_t _5155 = (uint16_t)(229); + _curvea0[748] = _5155; + uint16_t _5156 = (uint16_t)(229); + _curvea0[749] = _5156; + uint16_t _5157 = (uint16_t)(229); + _curvea0[750] = _5157; + uint16_t _5158 = (uint16_t)(230); + _curvea0[751] = _5158; + uint16_t _5159 = (uint16_t)(230); + _curvea0[752] = _5159; + uint16_t _5160 = (uint16_t)(230); + _curvea0[753] = _5160; + uint16_t _5161 = (uint16_t)(230); + _curvea0[754] = _5161; + uint16_t _5162 = (uint16_t)(230); + _curvea0[755] = _5162; + uint16_t _5163 = (uint16_t)(230); + _curvea0[756] = _5163; + uint16_t _5164 = (uint16_t)(230); + _curvea0[757] = _5164; + uint16_t _5165 = (uint16_t)(230); + _curvea0[758] = _5165; + uint16_t _5166 = (uint16_t)(231); + _curvea0[759] = _5166; + uint16_t _5167 = (uint16_t)(231); + _curvea0[760] = _5167; + uint16_t _5168 = (uint16_t)(231); + _curvea0[761] = _5168; + uint16_t _5169 = (uint16_t)(231); + _curvea0[762] = _5169; + uint16_t _5170 = (uint16_t)(231); + _curvea0[763] = _5170; + uint16_t _5171 = (uint16_t)(231); + _curvea0[764] = _5171; + uint16_t _5172 = (uint16_t)(231); + _curvea0[765] = _5172; + uint16_t _5173 = (uint16_t)(231); + _curvea0[766] = _5173; + uint16_t _5174 = (uint16_t)(231); + _curvea0[767] = _5174; + uint16_t _5175 = (uint16_t)(232); + _curvea0[768] = _5175; + uint16_t _5176 = (uint16_t)(232); + _curvea0[769] = _5176; + uint16_t _5177 = (uint16_t)(232); + _curvea0[770] = _5177; + uint16_t _5178 = (uint16_t)(232); + _curvea0[771] = _5178; + uint16_t _5179 = (uint16_t)(232); + _curvea0[772] = _5179; + uint16_t _5180 = (uint16_t)(232); + _curvea0[773] = _5180; + uint16_t _5181 = (uint16_t)(232); + _curvea0[774] = _5181; + uint16_t _5182 = (uint16_t)(232); + _curvea0[775] = _5182; + uint16_t _5183 = (uint16_t)(233); + _curvea0[776] = _5183; + uint16_t _5184 = (uint16_t)(233); + _curvea0[777] = _5184; + uint16_t _5185 = (uint16_t)(233); + _curvea0[778] = _5185; + uint16_t _5186 = (uint16_t)(233); + _curvea0[779] = _5186; + uint16_t _5187 = (uint16_t)(233); + _curvea0[780] = _5187; + uint16_t _5188 = (uint16_t)(233); + _curvea0[781] = _5188; + uint16_t _5189 = (uint16_t)(233); + _curvea0[782] = _5189; + uint16_t _5190 = (uint16_t)(233); + _curvea0[783] = _5190; + uint16_t _5191 = (uint16_t)(233); + _curvea0[784] = _5191; + uint16_t _5192 = (uint16_t)(234); + _curvea0[785] = _5192; + uint16_t _5193 = (uint16_t)(234); + _curvea0[786] = _5193; + uint16_t _5194 = (uint16_t)(234); + _curvea0[787] = _5194; + uint16_t _5195 = (uint16_t)(234); + _curvea0[788] = _5195; + uint16_t _5196 = (uint16_t)(234); + _curvea0[789] = _5196; + uint16_t _5197 = (uint16_t)(234); + _curvea0[790] = _5197; + uint16_t _5198 = (uint16_t)(234); + _curvea0[791] = _5198; + uint16_t _5199 = (uint16_t)(234); + _curvea0[792] = _5199; + uint16_t _5200 = (uint16_t)(234); + _curvea0[793] = _5200; + uint16_t _5201 = (uint16_t)(235); + _curvea0[794] = _5201; + uint16_t _5202 = (uint16_t)(235); + _curvea0[795] = _5202; + uint16_t _5203 = (uint16_t)(235); + _curvea0[796] = _5203; + uint16_t _5204 = (uint16_t)(235); + _curvea0[797] = _5204; + uint16_t _5205 = (uint16_t)(235); + _curvea0[798] = _5205; + uint16_t _5206 = (uint16_t)(235); + _curvea0[799] = _5206; + uint16_t _5207 = (uint16_t)(235); + _curvea0[800] = _5207; + uint16_t _5208 = (uint16_t)(235); + _curvea0[801] = _5208; + uint16_t _5209 = (uint16_t)(235); + _curvea0[802] = _5209; + uint16_t _5210 = (uint16_t)(236); + _curvea0[803] = _5210; + uint16_t _5211 = (uint16_t)(236); + _curvea0[804] = _5211; + uint16_t _5212 = (uint16_t)(236); + _curvea0[805] = _5212; + uint16_t _5213 = (uint16_t)(236); + _curvea0[806] = _5213; + uint16_t _5214 = (uint16_t)(236); + _curvea0[807] = _5214; + uint16_t _5215 = (uint16_t)(236); + _curvea0[808] = _5215; + uint16_t _5216 = (uint16_t)(236); + _curvea0[809] = _5216; + uint16_t _5217 = (uint16_t)(236); + _curvea0[810] = _5217; + uint16_t _5218 = (uint16_t)(236); + _curvea0[811] = _5218; + uint16_t _5219 = (uint16_t)(237); + _curvea0[812] = _5219; + uint16_t _5220 = (uint16_t)(237); + _curvea0[813] = _5220; + uint16_t _5221 = (uint16_t)(237); + _curvea0[814] = _5221; + uint16_t _5222 = (uint16_t)(237); + _curvea0[815] = _5222; + uint16_t _5223 = (uint16_t)(237); + _curvea0[816] = _5223; + uint16_t _5224 = (uint16_t)(237); + _curvea0[817] = _5224; + uint16_t _5225 = (uint16_t)(237); + _curvea0[818] = _5225; + uint16_t _5226 = (uint16_t)(237); + _curvea0[819] = _5226; + uint16_t _5227 = (uint16_t)(237); + _curvea0[820] = _5227; + uint16_t _5228 = (uint16_t)(237); + _curvea0[821] = _5228; + uint16_t _5229 = (uint16_t)(238); + _curvea0[822] = _5229; + uint16_t _5230 = (uint16_t)(238); + _curvea0[823] = _5230; + uint16_t _5231 = (uint16_t)(238); + _curvea0[824] = _5231; + uint16_t _5232 = (uint16_t)(238); + _curvea0[825] = _5232; + uint16_t _5233 = (uint16_t)(238); + _curvea0[826] = _5233; + uint16_t _5234 = (uint16_t)(238); + _curvea0[827] = _5234; + uint16_t _5235 = (uint16_t)(238); + _curvea0[828] = _5235; + uint16_t _5236 = (uint16_t)(238); + _curvea0[829] = _5236; + uint16_t _5237 = (uint16_t)(238); + _curvea0[830] = _5237; + uint16_t _5238 = (uint16_t)(239); + _curvea0[831] = _5238; + uint16_t _5239 = (uint16_t)(239); + _curvea0[832] = _5239; + uint16_t _5240 = (uint16_t)(239); + _curvea0[833] = _5240; + uint16_t _5241 = (uint16_t)(239); + _curvea0[834] = _5241; + uint16_t _5242 = (uint16_t)(239); + _curvea0[835] = _5242; + uint16_t _5243 = (uint16_t)(239); + _curvea0[836] = _5243; + uint16_t _5244 = (uint16_t)(239); + _curvea0[837] = _5244; + uint16_t _5245 = (uint16_t)(239); + _curvea0[838] = _5245; + uint16_t _5246 = (uint16_t)(239); + _curvea0[839] = _5246; + uint16_t _5247 = (uint16_t)(239); + _curvea0[840] = _5247; + uint16_t _5248 = (uint16_t)(240); + _curvea0[841] = _5248; + uint16_t _5249 = (uint16_t)(240); + _curvea0[842] = _5249; + uint16_t _5250 = (uint16_t)(240); + _curvea0[843] = _5250; + uint16_t _5251 = (uint16_t)(240); + _curvea0[844] = _5251; + uint16_t _5252 = (uint16_t)(240); + _curvea0[845] = _5252; + uint16_t _5253 = (uint16_t)(240); + _curvea0[846] = _5253; + uint16_t _5254 = (uint16_t)(240); + _curvea0[847] = _5254; + uint16_t _5255 = (uint16_t)(240); + _curvea0[848] = _5255; + uint16_t _5256 = (uint16_t)(240); + _curvea0[849] = _5256; + uint16_t _5257 = (uint16_t)(240); + _curvea0[850] = _5257; + uint16_t _5258 = (uint16_t)(241); + _curvea0[851] = _5258; + uint16_t _5259 = (uint16_t)(241); + _curvea0[852] = _5259; + uint16_t _5260 = (uint16_t)(241); + _curvea0[853] = _5260; + uint16_t _5261 = (uint16_t)(241); + _curvea0[854] = _5261; + uint16_t _5262 = (uint16_t)(241); + _curvea0[855] = _5262; + uint16_t _5263 = (uint16_t)(241); + _curvea0[856] = _5263; + uint16_t _5264 = (uint16_t)(241); + _curvea0[857] = _5264; + uint16_t _5265 = (uint16_t)(241); + _curvea0[858] = _5265; + uint16_t _5266 = (uint16_t)(241); + _curvea0[859] = _5266; + uint16_t _5267 = (uint16_t)(241); + _curvea0[860] = _5267; + uint16_t _5268 = (uint16_t)(242); + _curvea0[861] = _5268; + uint16_t _5269 = (uint16_t)(242); + _curvea0[862] = _5269; + uint16_t _5270 = (uint16_t)(242); + _curvea0[863] = _5270; + uint16_t _5271 = (uint16_t)(242); + _curvea0[864] = _5271; + uint16_t _5272 = (uint16_t)(242); + _curvea0[865] = _5272; + uint16_t _5273 = (uint16_t)(242); + _curvea0[866] = _5273; + uint16_t _5274 = (uint16_t)(242); + _curvea0[867] = _5274; + uint16_t _5275 = (uint16_t)(242); + _curvea0[868] = _5275; + uint16_t _5276 = (uint16_t)(242); + _curvea0[869] = _5276; + uint16_t _5277 = (uint16_t)(242); + _curvea0[870] = _5277; + uint16_t _5278 = (uint16_t)(243); + _curvea0[871] = _5278; + uint16_t _5279 = (uint16_t)(243); + _curvea0[872] = _5279; + uint16_t _5280 = (uint16_t)(243); + _curvea0[873] = _5280; + uint16_t _5281 = (uint16_t)(243); + _curvea0[874] = _5281; + uint16_t _5282 = (uint16_t)(243); + _curvea0[875] = _5282; + uint16_t _5283 = (uint16_t)(243); + _curvea0[876] = _5283; + uint16_t _5284 = (uint16_t)(243); + _curvea0[877] = _5284; + uint16_t _5285 = (uint16_t)(243); + _curvea0[878] = _5285; + uint16_t _5286 = (uint16_t)(243); + _curvea0[879] = _5286; + uint16_t _5287 = (uint16_t)(243); + _curvea0[880] = _5287; + uint16_t _5288 = (uint16_t)(244); + _curvea0[881] = _5288; + uint16_t _5289 = (uint16_t)(244); + _curvea0[882] = _5289; + uint16_t _5290 = (uint16_t)(244); + _curvea0[883] = _5290; + uint16_t _5291 = (uint16_t)(244); + _curvea0[884] = _5291; + uint16_t _5292 = (uint16_t)(244); + _curvea0[885] = _5292; + uint16_t _5293 = (uint16_t)(244); + _curvea0[886] = _5293; + uint16_t _5294 = (uint16_t)(244); + _curvea0[887] = _5294; + uint16_t _5295 = (uint16_t)(244); + _curvea0[888] = _5295; + uint16_t _5296 = (uint16_t)(244); + _curvea0[889] = _5296; + uint16_t _5297 = (uint16_t)(244); + _curvea0[890] = _5297; + uint16_t _5298 = (uint16_t)(244); + _curvea0[891] = _5298; + uint16_t _5299 = (uint16_t)(245); + _curvea0[892] = _5299; + uint16_t _5300 = (uint16_t)(245); + _curvea0[893] = _5300; + uint16_t _5301 = (uint16_t)(245); + _curvea0[894] = _5301; + uint16_t _5302 = (uint16_t)(245); + _curvea0[895] = _5302; + uint16_t _5303 = (uint16_t)(245); + _curvea0[896] = _5303; + uint16_t _5304 = (uint16_t)(245); + _curvea0[897] = _5304; + uint16_t _5305 = (uint16_t)(245); + _curvea0[898] = _5305; + uint16_t _5306 = (uint16_t)(245); + _curvea0[899] = _5306; + uint16_t _5307 = (uint16_t)(245); + _curvea0[900] = _5307; + uint16_t _5308 = (uint16_t)(245); + _curvea0[901] = _5308; + uint16_t _5309 = (uint16_t)(245); + _curvea0[902] = _5309; + uint16_t _5310 = (uint16_t)(246); + _curvea0[903] = _5310; + uint16_t _5311 = (uint16_t)(246); + _curvea0[904] = _5311; + uint16_t _5312 = (uint16_t)(246); + _curvea0[905] = _5312; + uint16_t _5313 = (uint16_t)(246); + _curvea0[906] = _5313; + uint16_t _5314 = (uint16_t)(246); + _curvea0[907] = _5314; + uint16_t _5315 = (uint16_t)(246); + _curvea0[908] = _5315; + uint16_t _5316 = (uint16_t)(246); + _curvea0[909] = _5316; + uint16_t _5317 = (uint16_t)(246); + _curvea0[910] = _5317; + uint16_t _5318 = (uint16_t)(246); + _curvea0[911] = _5318; + uint16_t _5319 = (uint16_t)(246); + _curvea0[912] = _5319; + uint16_t _5320 = (uint16_t)(246); + _curvea0[913] = _5320; + uint16_t _5321 = (uint16_t)(247); + _curvea0[914] = _5321; + uint16_t _5322 = (uint16_t)(247); + _curvea0[915] = _5322; + uint16_t _5323 = (uint16_t)(247); + _curvea0[916] = _5323; + uint16_t _5324 = (uint16_t)(247); + _curvea0[917] = _5324; + uint16_t _5325 = (uint16_t)(247); + _curvea0[918] = _5325; + uint16_t _5326 = (uint16_t)(247); + _curvea0[919] = _5326; + uint16_t _5327 = (uint16_t)(247); + _curvea0[920] = _5327; + uint16_t _5328 = (uint16_t)(247); + _curvea0[921] = _5328; + uint16_t _5329 = (uint16_t)(247); + _curvea0[922] = _5329; + uint16_t _5330 = (uint16_t)(247); + _curvea0[923] = _5330; + uint16_t _5331 = (uint16_t)(247); + _curvea0[924] = _5331; + uint16_t _5332 = (uint16_t)(248); + _curvea0[925] = _5332; + uint16_t _5333 = (uint16_t)(248); + _curvea0[926] = _5333; + uint16_t _5334 = (uint16_t)(248); + _curvea0[927] = _5334; + uint16_t _5335 = (uint16_t)(248); + _curvea0[928] = _5335; + uint16_t _5336 = (uint16_t)(248); + _curvea0[929] = _5336; + uint16_t _5337 = (uint16_t)(248); + _curvea0[930] = _5337; + uint16_t _5338 = (uint16_t)(248); + _curvea0[931] = _5338; + uint16_t _5339 = (uint16_t)(248); + _curvea0[932] = _5339; + uint16_t _5340 = (uint16_t)(248); + _curvea0[933] = _5340; + uint16_t _5341 = (uint16_t)(248); + _curvea0[934] = _5341; + uint16_t _5342 = (uint16_t)(248); + _curvea0[935] = _5342; + uint16_t _5343 = (uint16_t)(249); + _curvea0[936] = _5343; + uint16_t _5344 = (uint16_t)(249); + _curvea0[937] = _5344; + uint16_t _5345 = (uint16_t)(249); + _curvea0[938] = _5345; + uint16_t _5346 = (uint16_t)(249); + _curvea0[939] = _5346; + uint16_t _5347 = (uint16_t)(249); + _curvea0[940] = _5347; + uint16_t _5348 = (uint16_t)(249); + _curvea0[941] = _5348; + uint16_t _5349 = (uint16_t)(249); + _curvea0[942] = _5349; + uint16_t _5350 = (uint16_t)(249); + _curvea0[943] = _5350; + uint16_t _5351 = (uint16_t)(249); + _curvea0[944] = _5351; + uint16_t _5352 = (uint16_t)(249); + _curvea0[945] = _5352; + uint16_t _5353 = (uint16_t)(249); + _curvea0[946] = _5353; + uint16_t _5354 = (uint16_t)(249); + _curvea0[947] = _5354; + uint16_t _5355 = (uint16_t)(250); + _curvea0[948] = _5355; + uint16_t _5356 = (uint16_t)(250); + _curvea0[949] = _5356; + uint16_t _5357 = (uint16_t)(250); + _curvea0[950] = _5357; + uint16_t _5358 = (uint16_t)(250); + _curvea0[951] = _5358; + uint16_t _5359 = (uint16_t)(250); + _curvea0[952] = _5359; + uint16_t _5360 = (uint16_t)(250); + _curvea0[953] = _5360; + uint16_t _5361 = (uint16_t)(250); + _curvea0[954] = _5361; + uint16_t _5362 = (uint16_t)(250); + _curvea0[955] = _5362; + uint16_t _5363 = (uint16_t)(250); + _curvea0[956] = _5363; + uint16_t _5364 = (uint16_t)(250); + _curvea0[957] = _5364; + uint16_t _5365 = (uint16_t)(250); + _curvea0[958] = _5365; + uint16_t _5366 = (uint16_t)(250); + _curvea0[959] = _5366; + uint16_t _5367 = (uint16_t)(251); + _curvea0[960] = _5367; + uint16_t _5368 = (uint16_t)(251); + _curvea0[961] = _5368; + uint16_t _5369 = (uint16_t)(251); + _curvea0[962] = _5369; + uint16_t _5370 = (uint16_t)(251); + _curvea0[963] = _5370; + uint16_t _5371 = (uint16_t)(251); + _curvea0[964] = _5371; + uint16_t _5372 = (uint16_t)(251); + _curvea0[965] = _5372; + uint16_t _5373 = (uint16_t)(251); + _curvea0[966] = _5373; + uint16_t _5374 = (uint16_t)(251); + _curvea0[967] = _5374; + uint16_t _5375 = (uint16_t)(251); + _curvea0[968] = _5375; + uint16_t _5376 = (uint16_t)(251); + _curvea0[969] = _5376; + uint16_t _5377 = (uint16_t)(251); + _curvea0[970] = _5377; + uint16_t _5378 = (uint16_t)(251); + _curvea0[971] = _5378; + uint16_t _5379 = (uint16_t)(252); + _curvea0[972] = _5379; + uint16_t _5380 = (uint16_t)(252); + _curvea0[973] = _5380; + uint16_t _5381 = (uint16_t)(252); + _curvea0[974] = _5381; + uint16_t _5382 = (uint16_t)(252); + _curvea0[975] = _5382; + uint16_t _5383 = (uint16_t)(252); + _curvea0[976] = _5383; + uint16_t _5384 = (uint16_t)(252); + _curvea0[977] = _5384; + uint16_t _5385 = (uint16_t)(252); + _curvea0[978] = _5385; + uint16_t _5386 = (uint16_t)(252); + _curvea0[979] = _5386; + uint16_t _5387 = (uint16_t)(252); + _curvea0[980] = _5387; + uint16_t _5388 = (uint16_t)(252); + _curvea0[981] = _5388; + uint16_t _5389 = (uint16_t)(252); + _curvea0[982] = _5389; + uint16_t _5390 = (uint16_t)(252); + _curvea0[983] = _5390; + uint16_t _5391 = (uint16_t)(252); + _curvea0[984] = _5391; + uint16_t _5392 = (uint16_t)(253); + _curvea0[985] = _5392; + uint16_t _5393 = (uint16_t)(253); + _curvea0[986] = _5393; + uint16_t _5394 = (uint16_t)(253); + _curvea0[987] = _5394; + uint16_t _5395 = (uint16_t)(253); + _curvea0[988] = _5395; + uint16_t _5396 = (uint16_t)(253); + _curvea0[989] = _5396; + uint16_t _5397 = (uint16_t)(253); + _curvea0[990] = _5397; + uint16_t _5398 = (uint16_t)(253); + _curvea0[991] = _5398; + uint16_t _5399 = (uint16_t)(253); + _curvea0[992] = _5399; + uint16_t _5400 = (uint16_t)(253); + _curvea0[993] = _5400; + uint16_t _5401 = (uint16_t)(253); + _curvea0[994] = _5401; + uint16_t _5402 = (uint16_t)(253); + _curvea0[995] = _5402; + uint16_t _5403 = (uint16_t)(253); + _curvea0[996] = _5403; + uint16_t _5404 = (uint16_t)(253); + _curvea0[997] = _5404; + uint16_t _5405 = (uint16_t)(254); + _curvea0[998] = _5405; + uint16_t _5406 = (uint16_t)(254); + _curvea0[999] = _5406; + uint16_t _5407 = (uint16_t)(254); + _curvea0[1000] = _5407; + uint16_t _5408 = (uint16_t)(254); + _curvea0[1001] = _5408; + uint16_t _5409 = (uint16_t)(254); + _curvea0[1002] = _5409; + uint16_t _5410 = (uint16_t)(254); + _curvea0[1003] = _5410; + uint16_t _5411 = (uint16_t)(254); + _curvea0[1004] = _5411; + uint16_t _5412 = (uint16_t)(254); + _curvea0[1005] = _5412; + uint16_t _5413 = (uint16_t)(254); + _curvea0[1006] = _5413; + uint16_t _5414 = (uint16_t)(254); + _curvea0[1007] = _5414; + uint16_t _5415 = (uint16_t)(254); + _curvea0[1008] = _5415; + uint16_t _5416 = (uint16_t)(254); + _curvea0[1009] = _5416; + uint16_t _5417 = (uint16_t)(254); + _curvea0[1010] = _5417; + uint16_t _5418 = (uint16_t)(255); + _curvea0[1011] = _5418; + uint16_t _5419 = (uint16_t)(255); + _curvea0[1012] = _5419; + uint16_t _5420 = (uint16_t)(255); + _curvea0[1013] = _5420; + uint16_t _5421 = (uint16_t)(255); + _curvea0[1014] = _5421; + uint16_t _5422 = (uint16_t)(255); + _curvea0[1015] = _5422; + uint16_t _5423 = (uint16_t)(255); + _curvea0[1016] = _5423; + uint16_t _5424 = (uint16_t)(255); + _curvea0[1017] = _5424; + uint16_t _5425 = (uint16_t)(255); + _curvea0[1018] = _5425; + uint16_t _5426 = (uint16_t)(255); + _curvea0[1019] = _5426; + uint16_t _5427 = (uint16_t)(255); + _curvea0[1020] = _5427; + uint16_t _5428 = (uint16_t)(255); + _curvea0[1021] = _5428; + uint16_t _5429 = (uint16_t)(255); + _curvea0[1022] = _5429; + uint16_t _5430 = (uint16_t)(255); + _curvea0[1023] = _5430; + + int16_t _5431 = (int16_t)(1023); + int16_t _5432 = min(_corrected_stencil_3, _5431); + int16_t _5433 = (int16_t)(0); + int16_t _5434 = max(_5432, _5433); + uint16_t _5435 = (uint16_t)(_5434); + int32_t _5436 = (int32_t)(_5435); + uint16_t _5437 = ((const uint16_t *)_curvea0)[_5436]; + return _5437; +} + +//store is: curved.stencil(((curved_s0_x_x_1*2) + 1), curved_s0_y_1, 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x_1*2) + 1), curved_s0_y_1, 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_3(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_4 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _5453 = (uint16_t)(0); + _curvea0[0] = _5453; + uint16_t _5454 = (uint16_t)(4); + _curvea0[1] = _5454; + uint16_t _5455 = (uint16_t)(7); + _curvea0[2] = _5455; + uint16_t _5456 = (uint16_t)(8); + _curvea0[3] = _5456; + uint16_t _5457 = (uint16_t)(10); + _curvea0[4] = _5457; + uint16_t _5458 = (uint16_t)(11); + _curvea0[5] = _5458; + uint16_t _5459 = (uint16_t)(12); + _curvea0[6] = _5459; + uint16_t _5460 = (uint16_t)(13); + _curvea0[7] = _5460; + uint16_t _5461 = (uint16_t)(14); + _curvea0[8] = _5461; + uint16_t _5462 = (uint16_t)(15); + _curvea0[9] = _5462; + uint16_t _5463 = (uint16_t)(16); + _curvea0[10] = _5463; + uint16_t _5464 = (uint16_t)(17); + _curvea0[11] = _5464; + uint16_t _5465 = (uint16_t)(18); + _curvea0[12] = _5465; + uint16_t _5466 = (uint16_t)(19); + _curvea0[13] = _5466; + uint16_t _5467 = (uint16_t)(20); + _curvea0[14] = _5467; + uint16_t _5468 = (uint16_t)(21); + _curvea0[15] = _5468; + uint16_t _5469 = (uint16_t)(22); + _curvea0[16] = _5469; + uint16_t _5470 = (uint16_t)(22); + _curvea0[17] = _5470; + uint16_t _5471 = (uint16_t)(23); + _curvea0[18] = _5471; + uint16_t _5472 = (uint16_t)(24); + _curvea0[19] = _5472; + uint16_t _5473 = (uint16_t)(25); + _curvea0[20] = _5473; + uint16_t _5474 = (uint16_t)(25); + _curvea0[21] = _5474; + uint16_t _5475 = (uint16_t)(26); + _curvea0[22] = _5475; + uint16_t _5476 = (uint16_t)(27); + _curvea0[23] = _5476; + uint16_t _5477 = (uint16_t)(27); + _curvea0[24] = _5477; + uint16_t _5478 = (uint16_t)(28); + _curvea0[25] = _5478; + uint16_t _5479 = (uint16_t)(29); + _curvea0[26] = _5479; + uint16_t _5480 = (uint16_t)(29); + _curvea0[27] = _5480; + uint16_t _5481 = (uint16_t)(30); + _curvea0[28] = _5481; + uint16_t _5482 = (uint16_t)(31); + _curvea0[29] = _5482; + uint16_t _5483 = (uint16_t)(31); + _curvea0[30] = _5483; + uint16_t _5484 = (uint16_t)(32); + _curvea0[31] = _5484; + uint16_t _5485 = (uint16_t)(33); + _curvea0[32] = _5485; + uint16_t _5486 = (uint16_t)(33); + _curvea0[33] = _5486; + uint16_t _5487 = (uint16_t)(34); + _curvea0[34] = _5487; + uint16_t _5488 = (uint16_t)(34); + _curvea0[35] = _5488; + uint16_t _5489 = (uint16_t)(35); + _curvea0[36] = _5489; + uint16_t _5490 = (uint16_t)(36); + _curvea0[37] = _5490; + uint16_t _5491 = (uint16_t)(36); + _curvea0[38] = _5491; + uint16_t _5492 = (uint16_t)(37); + _curvea0[39] = _5492; + uint16_t _5493 = (uint16_t)(37); + _curvea0[40] = _5493; + uint16_t _5494 = (uint16_t)(38); + _curvea0[41] = _5494; + uint16_t _5495 = (uint16_t)(39); + _curvea0[42] = _5495; + uint16_t _5496 = (uint16_t)(39); + _curvea0[43] = _5496; + uint16_t _5497 = (uint16_t)(40); + _curvea0[44] = _5497; + uint16_t _5498 = (uint16_t)(40); + _curvea0[45] = _5498; + uint16_t _5499 = (uint16_t)(41); + _curvea0[46] = _5499; + uint16_t _5500 = (uint16_t)(41); + _curvea0[47] = _5500; + uint16_t _5501 = (uint16_t)(42); + _curvea0[48] = _5501; + uint16_t _5502 = (uint16_t)(42); + _curvea0[49] = _5502; + uint16_t _5503 = (uint16_t)(43); + _curvea0[50] = _5503; + uint16_t _5504 = (uint16_t)(44); + _curvea0[51] = _5504; + uint16_t _5505 = (uint16_t)(44); + _curvea0[52] = _5505; + uint16_t _5506 = (uint16_t)(45); + _curvea0[53] = _5506; + uint16_t _5507 = (uint16_t)(45); + _curvea0[54] = _5507; + uint16_t _5508 = (uint16_t)(46); + _curvea0[55] = _5508; + uint16_t _5509 = (uint16_t)(46); + _curvea0[56] = _5509; + uint16_t _5510 = (uint16_t)(47); + _curvea0[57] = _5510; + uint16_t _5511 = (uint16_t)(47); + _curvea0[58] = _5511; + uint16_t _5512 = (uint16_t)(48); + _curvea0[59] = _5512; + uint16_t _5513 = (uint16_t)(48); + _curvea0[60] = _5513; + uint16_t _5514 = (uint16_t)(49); + _curvea0[61] = _5514; + uint16_t _5515 = (uint16_t)(49); + _curvea0[62] = _5515; + uint16_t _5516 = (uint16_t)(50); + _curvea0[63] = _5516; + uint16_t _5517 = (uint16_t)(50); + _curvea0[64] = _5517; + uint16_t _5518 = (uint16_t)(51); + _curvea0[65] = _5518; + uint16_t _5519 = (uint16_t)(51); + _curvea0[66] = _5519; + uint16_t _5520 = (uint16_t)(52); + _curvea0[67] = _5520; + uint16_t _5521 = (uint16_t)(52); + _curvea0[68] = _5521; + uint16_t _5522 = (uint16_t)(53); + _curvea0[69] = _5522; + uint16_t _5523 = (uint16_t)(53); + _curvea0[70] = _5523; + uint16_t _5524 = (uint16_t)(54); + _curvea0[71] = _5524; + uint16_t _5525 = (uint16_t)(54); + _curvea0[72] = _5525; + uint16_t _5526 = (uint16_t)(55); + _curvea0[73] = _5526; + uint16_t _5527 = (uint16_t)(55); + _curvea0[74] = _5527; + uint16_t _5528 = (uint16_t)(56); + _curvea0[75] = _5528; + uint16_t _5529 = (uint16_t)(56); + _curvea0[76] = _5529; + uint16_t _5530 = (uint16_t)(57); + _curvea0[77] = _5530; + uint16_t _5531 = (uint16_t)(57); + _curvea0[78] = _5531; + uint16_t _5532 = (uint16_t)(58); + _curvea0[79] = _5532; + uint16_t _5533 = (uint16_t)(58); + _curvea0[80] = _5533; + uint16_t _5534 = (uint16_t)(58); + _curvea0[81] = _5534; + uint16_t _5535 = (uint16_t)(59); + _curvea0[82] = _5535; + uint16_t _5536 = (uint16_t)(59); + _curvea0[83] = _5536; + uint16_t _5537 = (uint16_t)(60); + _curvea0[84] = _5537; + uint16_t _5538 = (uint16_t)(60); + _curvea0[85] = _5538; + uint16_t _5539 = (uint16_t)(61); + _curvea0[86] = _5539; + uint16_t _5540 = (uint16_t)(61); + _curvea0[87] = _5540; + uint16_t _5541 = (uint16_t)(62); + _curvea0[88] = _5541; + uint16_t _5542 = (uint16_t)(62); + _curvea0[89] = _5542; + uint16_t _5543 = (uint16_t)(63); + _curvea0[90] = _5543; + uint16_t _5544 = (uint16_t)(63); + _curvea0[91] = _5544; + uint16_t _5545 = (uint16_t)(64); + _curvea0[92] = _5545; + uint16_t _5546 = (uint16_t)(64); + _curvea0[93] = _5546; + uint16_t _5547 = (uint16_t)(64); + _curvea0[94] = _5547; + uint16_t _5548 = (uint16_t)(65); + _curvea0[95] = _5548; + uint16_t _5549 = (uint16_t)(65); + _curvea0[96] = _5549; + uint16_t _5550 = (uint16_t)(66); + _curvea0[97] = _5550; + uint16_t _5551 = (uint16_t)(66); + _curvea0[98] = _5551; + uint16_t _5552 = (uint16_t)(67); + _curvea0[99] = _5552; + uint16_t _5553 = (uint16_t)(67); + _curvea0[100] = _5553; + uint16_t _5554 = (uint16_t)(68); + _curvea0[101] = _5554; + uint16_t _5555 = (uint16_t)(68); + _curvea0[102] = _5555; + uint16_t _5556 = (uint16_t)(68); + _curvea0[103] = _5556; + uint16_t _5557 = (uint16_t)(69); + _curvea0[104] = _5557; + uint16_t _5558 = (uint16_t)(69); + _curvea0[105] = _5558; + uint16_t _5559 = (uint16_t)(70); + _curvea0[106] = _5559; + uint16_t _5560 = (uint16_t)(70); + _curvea0[107] = _5560; + uint16_t _5561 = (uint16_t)(71); + _curvea0[108] = _5561; + uint16_t _5562 = (uint16_t)(71); + _curvea0[109] = _5562; + uint16_t _5563 = (uint16_t)(71); + _curvea0[110] = _5563; + uint16_t _5564 = (uint16_t)(72); + _curvea0[111] = _5564; + uint16_t _5565 = (uint16_t)(72); + _curvea0[112] = _5565; + uint16_t _5566 = (uint16_t)(73); + _curvea0[113] = _5566; + uint16_t _5567 = (uint16_t)(73); + _curvea0[114] = _5567; + uint16_t _5568 = (uint16_t)(74); + _curvea0[115] = _5568; + uint16_t _5569 = (uint16_t)(74); + _curvea0[116] = _5569; + uint16_t _5570 = (uint16_t)(74); + _curvea0[117] = _5570; + uint16_t _5571 = (uint16_t)(75); + _curvea0[118] = _5571; + uint16_t _5572 = (uint16_t)(75); + _curvea0[119] = _5572; + uint16_t _5573 = (uint16_t)(76); + _curvea0[120] = _5573; + uint16_t _5574 = (uint16_t)(76); + _curvea0[121] = _5574; + uint16_t _5575 = (uint16_t)(77); + _curvea0[122] = _5575; + uint16_t _5576 = (uint16_t)(77); + _curvea0[123] = _5576; + uint16_t _5577 = (uint16_t)(77); + _curvea0[124] = _5577; + uint16_t _5578 = (uint16_t)(78); + _curvea0[125] = _5578; + uint16_t _5579 = (uint16_t)(78); + _curvea0[126] = _5579; + uint16_t _5580 = (uint16_t)(79); + _curvea0[127] = _5580; + uint16_t _5581 = (uint16_t)(79); + _curvea0[128] = _5581; + uint16_t _5582 = (uint16_t)(79); + _curvea0[129] = _5582; + uint16_t _5583 = (uint16_t)(80); + _curvea0[130] = _5583; + uint16_t _5584 = (uint16_t)(80); + _curvea0[131] = _5584; + uint16_t _5585 = (uint16_t)(81); + _curvea0[132] = _5585; + uint16_t _5586 = (uint16_t)(81); + _curvea0[133] = _5586; + uint16_t _5587 = (uint16_t)(82); + _curvea0[134] = _5587; + uint16_t _5588 = (uint16_t)(82); + _curvea0[135] = _5588; + uint16_t _5589 = (uint16_t)(82); + _curvea0[136] = _5589; + uint16_t _5590 = (uint16_t)(83); + _curvea0[137] = _5590; + uint16_t _5591 = (uint16_t)(83); + _curvea0[138] = _5591; + uint16_t _5592 = (uint16_t)(84); + _curvea0[139] = _5592; + uint16_t _5593 = (uint16_t)(84); + _curvea0[140] = _5593; + uint16_t _5594 = (uint16_t)(84); + _curvea0[141] = _5594; + uint16_t _5595 = (uint16_t)(85); + _curvea0[142] = _5595; + uint16_t _5596 = (uint16_t)(85); + _curvea0[143] = _5596; + uint16_t _5597 = (uint16_t)(86); + _curvea0[144] = _5597; + uint16_t _5598 = (uint16_t)(86); + _curvea0[145] = _5598; + uint16_t _5599 = (uint16_t)(86); + _curvea0[146] = _5599; + uint16_t _5600 = (uint16_t)(87); + _curvea0[147] = _5600; + uint16_t _5601 = (uint16_t)(87); + _curvea0[148] = _5601; + uint16_t _5602 = (uint16_t)(88); + _curvea0[149] = _5602; + uint16_t _5603 = (uint16_t)(88); + _curvea0[150] = _5603; + uint16_t _5604 = (uint16_t)(88); + _curvea0[151] = _5604; + uint16_t _5605 = (uint16_t)(89); + _curvea0[152] = _5605; + uint16_t _5606 = (uint16_t)(89); + _curvea0[153] = _5606; + uint16_t _5607 = (uint16_t)(90); + _curvea0[154] = _5607; + uint16_t _5608 = (uint16_t)(90); + _curvea0[155] = _5608; + uint16_t _5609 = (uint16_t)(90); + _curvea0[156] = _5609; + uint16_t _5610 = (uint16_t)(91); + _curvea0[157] = _5610; + uint16_t _5611 = (uint16_t)(91); + _curvea0[158] = _5611; + uint16_t _5612 = (uint16_t)(92); + _curvea0[159] = _5612; + uint16_t _5613 = (uint16_t)(92); + _curvea0[160] = _5613; + uint16_t _5614 = (uint16_t)(92); + _curvea0[161] = _5614; + uint16_t _5615 = (uint16_t)(93); + _curvea0[162] = _5615; + uint16_t _5616 = (uint16_t)(93); + _curvea0[163] = _5616; + uint16_t _5617 = (uint16_t)(93); + _curvea0[164] = _5617; + uint16_t _5618 = (uint16_t)(94); + _curvea0[165] = _5618; + uint16_t _5619 = (uint16_t)(94); + _curvea0[166] = _5619; + uint16_t _5620 = (uint16_t)(95); + _curvea0[167] = _5620; + uint16_t _5621 = (uint16_t)(95); + _curvea0[168] = _5621; + uint16_t _5622 = (uint16_t)(95); + _curvea0[169] = _5622; + uint16_t _5623 = (uint16_t)(96); + _curvea0[170] = _5623; + uint16_t _5624 = (uint16_t)(96); + _curvea0[171] = _5624; + uint16_t _5625 = (uint16_t)(97); + _curvea0[172] = _5625; + uint16_t _5626 = (uint16_t)(97); + _curvea0[173] = _5626; + uint16_t _5627 = (uint16_t)(97); + _curvea0[174] = _5627; + uint16_t _5628 = (uint16_t)(98); + _curvea0[175] = _5628; + uint16_t _5629 = (uint16_t)(98); + _curvea0[176] = _5629; + uint16_t _5630 = (uint16_t)(99); + _curvea0[177] = _5630; + uint16_t _5631 = (uint16_t)(99); + _curvea0[178] = _5631; + uint16_t _5632 = (uint16_t)(99); + _curvea0[179] = _5632; + uint16_t _5633 = (uint16_t)(100); + _curvea0[180] = _5633; + uint16_t _5634 = (uint16_t)(100); + _curvea0[181] = _5634; + uint16_t _5635 = (uint16_t)(100); + _curvea0[182] = _5635; + uint16_t _5636 = (uint16_t)(101); + _curvea0[183] = _5636; + uint16_t _5637 = (uint16_t)(101); + _curvea0[184] = _5637; + uint16_t _5638 = (uint16_t)(102); + _curvea0[185] = _5638; + uint16_t _5639 = (uint16_t)(102); + _curvea0[186] = _5639; + uint16_t _5640 = (uint16_t)(102); + _curvea0[187] = _5640; + uint16_t _5641 = (uint16_t)(103); + _curvea0[188] = _5641; + uint16_t _5642 = (uint16_t)(103); + _curvea0[189] = _5642; + uint16_t _5643 = (uint16_t)(103); + _curvea0[190] = _5643; + uint16_t _5644 = (uint16_t)(104); + _curvea0[191] = _5644; + uint16_t _5645 = (uint16_t)(104); + _curvea0[192] = _5645; + uint16_t _5646 = (uint16_t)(105); + _curvea0[193] = _5646; + uint16_t _5647 = (uint16_t)(105); + _curvea0[194] = _5647; + uint16_t _5648 = (uint16_t)(105); + _curvea0[195] = _5648; + uint16_t _5649 = (uint16_t)(106); + _curvea0[196] = _5649; + uint16_t _5650 = (uint16_t)(106); + _curvea0[197] = _5650; + uint16_t _5651 = (uint16_t)(106); + _curvea0[198] = _5651; + uint16_t _5652 = (uint16_t)(107); + _curvea0[199] = _5652; + uint16_t _5653 = (uint16_t)(107); + _curvea0[200] = _5653; + uint16_t _5654 = (uint16_t)(108); + _curvea0[201] = _5654; + uint16_t _5655 = (uint16_t)(108); + _curvea0[202] = _5655; + uint16_t _5656 = (uint16_t)(108); + _curvea0[203] = _5656; + uint16_t _5657 = (uint16_t)(109); + _curvea0[204] = _5657; + uint16_t _5658 = (uint16_t)(109); + _curvea0[205] = _5658; + uint16_t _5659 = (uint16_t)(109); + _curvea0[206] = _5659; + uint16_t _5660 = (uint16_t)(110); + _curvea0[207] = _5660; + uint16_t _5661 = (uint16_t)(110); + _curvea0[208] = _5661; + uint16_t _5662 = (uint16_t)(111); + _curvea0[209] = _5662; + uint16_t _5663 = (uint16_t)(111); + _curvea0[210] = _5663; + uint16_t _5664 = (uint16_t)(111); + _curvea0[211] = _5664; + uint16_t _5665 = (uint16_t)(112); + _curvea0[212] = _5665; + uint16_t _5666 = (uint16_t)(112); + _curvea0[213] = _5666; + uint16_t _5667 = (uint16_t)(112); + _curvea0[214] = _5667; + uint16_t _5668 = (uint16_t)(113); + _curvea0[215] = _5668; + uint16_t _5669 = (uint16_t)(113); + _curvea0[216] = _5669; + uint16_t _5670 = (uint16_t)(113); + _curvea0[217] = _5670; + uint16_t _5671 = (uint16_t)(114); + _curvea0[218] = _5671; + uint16_t _5672 = (uint16_t)(114); + _curvea0[219] = _5672; + uint16_t _5673 = (uint16_t)(115); + _curvea0[220] = _5673; + uint16_t _5674 = (uint16_t)(115); + _curvea0[221] = _5674; + uint16_t _5675 = (uint16_t)(115); + _curvea0[222] = _5675; + uint16_t _5676 = (uint16_t)(116); + _curvea0[223] = _5676; + uint16_t _5677 = (uint16_t)(116); + _curvea0[224] = _5677; + uint16_t _5678 = (uint16_t)(116); + _curvea0[225] = _5678; + uint16_t _5679 = (uint16_t)(117); + _curvea0[226] = _5679; + uint16_t _5680 = (uint16_t)(117); + _curvea0[227] = _5680; + uint16_t _5681 = (uint16_t)(117); + _curvea0[228] = _5681; + uint16_t _5682 = (uint16_t)(118); + _curvea0[229] = _5682; + uint16_t _5683 = (uint16_t)(118); + _curvea0[230] = _5683; + uint16_t _5684 = (uint16_t)(119); + _curvea0[231] = _5684; + uint16_t _5685 = (uint16_t)(119); + _curvea0[232] = _5685; + uint16_t _5686 = (uint16_t)(119); + _curvea0[233] = _5686; + uint16_t _5687 = (uint16_t)(120); + _curvea0[234] = _5687; + uint16_t _5688 = (uint16_t)(120); + _curvea0[235] = _5688; + uint16_t _5689 = (uint16_t)(120); + _curvea0[236] = _5689; + uint16_t _5690 = (uint16_t)(121); + _curvea0[237] = _5690; + uint16_t _5691 = (uint16_t)(121); + _curvea0[238] = _5691; + uint16_t _5692 = (uint16_t)(121); + _curvea0[239] = _5692; + uint16_t _5693 = (uint16_t)(122); + _curvea0[240] = _5693; + uint16_t _5694 = (uint16_t)(122); + _curvea0[241] = _5694; + uint16_t _5695 = (uint16_t)(123); + _curvea0[242] = _5695; + uint16_t _5696 = (uint16_t)(123); + _curvea0[243] = _5696; + uint16_t _5697 = (uint16_t)(123); + _curvea0[244] = _5697; + uint16_t _5698 = (uint16_t)(124); + _curvea0[245] = _5698; + uint16_t _5699 = (uint16_t)(124); + _curvea0[246] = _5699; + uint16_t _5700 = (uint16_t)(124); + _curvea0[247] = _5700; + uint16_t _5701 = (uint16_t)(125); + _curvea0[248] = _5701; + uint16_t _5702 = (uint16_t)(125); + _curvea0[249] = _5702; + uint16_t _5703 = (uint16_t)(125); + _curvea0[250] = _5703; + uint16_t _5704 = (uint16_t)(126); + _curvea0[251] = _5704; + uint16_t _5705 = (uint16_t)(126); + _curvea0[252] = _5705; + uint16_t _5706 = (uint16_t)(126); + _curvea0[253] = _5706; + uint16_t _5707 = (uint16_t)(127); + _curvea0[254] = _5707; + uint16_t _5708 = (uint16_t)(127); + _curvea0[255] = _5708; + uint16_t _5709 = (uint16_t)(128); + _curvea0[256] = _5709; + uint16_t _5710 = (uint16_t)(128); + _curvea0[257] = _5710; + uint16_t _5711 = (uint16_t)(128); + _curvea0[258] = _5711; + uint16_t _5712 = (uint16_t)(129); + _curvea0[259] = _5712; + uint16_t _5713 = (uint16_t)(129); + _curvea0[260] = _5713; + uint16_t _5714 = (uint16_t)(129); + _curvea0[261] = _5714; + uint16_t _5715 = (uint16_t)(130); + _curvea0[262] = _5715; + uint16_t _5716 = (uint16_t)(130); + _curvea0[263] = _5716; + uint16_t _5717 = (uint16_t)(130); + _curvea0[264] = _5717; + uint16_t _5718 = (uint16_t)(131); + _curvea0[265] = _5718; + uint16_t _5719 = (uint16_t)(131); + _curvea0[266] = _5719; + uint16_t _5720 = (uint16_t)(131); + _curvea0[267] = _5720; + uint16_t _5721 = (uint16_t)(132); + _curvea0[268] = _5721; + uint16_t _5722 = (uint16_t)(132); + _curvea0[269] = _5722; + uint16_t _5723 = (uint16_t)(132); + _curvea0[270] = _5723; + uint16_t _5724 = (uint16_t)(133); + _curvea0[271] = _5724; + uint16_t _5725 = (uint16_t)(133); + _curvea0[272] = _5725; + uint16_t _5726 = (uint16_t)(133); + _curvea0[273] = _5726; + uint16_t _5727 = (uint16_t)(134); + _curvea0[274] = _5727; + uint16_t _5728 = (uint16_t)(134); + _curvea0[275] = _5728; + uint16_t _5729 = (uint16_t)(134); + _curvea0[276] = _5729; + uint16_t _5730 = (uint16_t)(135); + _curvea0[277] = _5730; + uint16_t _5731 = (uint16_t)(135); + _curvea0[278] = _5731; + uint16_t _5732 = (uint16_t)(135); + _curvea0[279] = _5732; + uint16_t _5733 = (uint16_t)(136); + _curvea0[280] = _5733; + uint16_t _5734 = (uint16_t)(136); + _curvea0[281] = _5734; + uint16_t _5735 = (uint16_t)(136); + _curvea0[282] = _5735; + uint16_t _5736 = (uint16_t)(137); + _curvea0[283] = _5736; + uint16_t _5737 = (uint16_t)(137); + _curvea0[284] = _5737; + uint16_t _5738 = (uint16_t)(137); + _curvea0[285] = _5738; + uint16_t _5739 = (uint16_t)(138); + _curvea0[286] = _5739; + uint16_t _5740 = (uint16_t)(138); + _curvea0[287] = _5740; + uint16_t _5741 = (uint16_t)(138); + _curvea0[288] = _5741; + uint16_t _5742 = (uint16_t)(139); + _curvea0[289] = _5742; + uint16_t _5743 = (uint16_t)(139); + _curvea0[290] = _5743; + uint16_t _5744 = (uint16_t)(139); + _curvea0[291] = _5744; + uint16_t _5745 = (uint16_t)(140); + _curvea0[292] = _5745; + uint16_t _5746 = (uint16_t)(140); + _curvea0[293] = _5746; + uint16_t _5747 = (uint16_t)(140); + _curvea0[294] = _5747; + uint16_t _5748 = (uint16_t)(141); + _curvea0[295] = _5748; + uint16_t _5749 = (uint16_t)(141); + _curvea0[296] = _5749; + uint16_t _5750 = (uint16_t)(141); + _curvea0[297] = _5750; + uint16_t _5751 = (uint16_t)(141); + _curvea0[298] = _5751; + uint16_t _5752 = (uint16_t)(142); + _curvea0[299] = _5752; + uint16_t _5753 = (uint16_t)(142); + _curvea0[300] = _5753; + uint16_t _5754 = (uint16_t)(142); + _curvea0[301] = _5754; + uint16_t _5755 = (uint16_t)(143); + _curvea0[302] = _5755; + uint16_t _5756 = (uint16_t)(143); + _curvea0[303] = _5756; + uint16_t _5757 = (uint16_t)(143); + _curvea0[304] = _5757; + uint16_t _5758 = (uint16_t)(144); + _curvea0[305] = _5758; + uint16_t _5759 = (uint16_t)(144); + _curvea0[306] = _5759; + uint16_t _5760 = (uint16_t)(144); + _curvea0[307] = _5760; + uint16_t _5761 = (uint16_t)(145); + _curvea0[308] = _5761; + uint16_t _5762 = (uint16_t)(145); + _curvea0[309] = _5762; + uint16_t _5763 = (uint16_t)(145); + _curvea0[310] = _5763; + uint16_t _5764 = (uint16_t)(145); + _curvea0[311] = _5764; + uint16_t _5765 = (uint16_t)(146); + _curvea0[312] = _5765; + uint16_t _5766 = (uint16_t)(146); + _curvea0[313] = _5766; + uint16_t _5767 = (uint16_t)(146); + _curvea0[314] = _5767; + uint16_t _5768 = (uint16_t)(147); + _curvea0[315] = _5768; + uint16_t _5769 = (uint16_t)(147); + _curvea0[316] = _5769; + uint16_t _5770 = (uint16_t)(147); + _curvea0[317] = _5770; + uint16_t _5771 = (uint16_t)(148); + _curvea0[318] = _5771; + uint16_t _5772 = (uint16_t)(148); + _curvea0[319] = _5772; + uint16_t _5773 = (uint16_t)(148); + _curvea0[320] = _5773; + uint16_t _5774 = (uint16_t)(148); + _curvea0[321] = _5774; + uint16_t _5775 = (uint16_t)(149); + _curvea0[322] = _5775; + uint16_t _5776 = (uint16_t)(149); + _curvea0[323] = _5776; + uint16_t _5777 = (uint16_t)(149); + _curvea0[324] = _5777; + uint16_t _5778 = (uint16_t)(150); + _curvea0[325] = _5778; + uint16_t _5779 = (uint16_t)(150); + _curvea0[326] = _5779; + uint16_t _5780 = (uint16_t)(150); + _curvea0[327] = _5780; + uint16_t _5781 = (uint16_t)(150); + _curvea0[328] = _5781; + uint16_t _5782 = (uint16_t)(151); + _curvea0[329] = _5782; + uint16_t _5783 = (uint16_t)(151); + _curvea0[330] = _5783; + uint16_t _5784 = (uint16_t)(151); + _curvea0[331] = _5784; + uint16_t _5785 = (uint16_t)(152); + _curvea0[332] = _5785; + uint16_t _5786 = (uint16_t)(152); + _curvea0[333] = _5786; + uint16_t _5787 = (uint16_t)(152); + _curvea0[334] = _5787; + uint16_t _5788 = (uint16_t)(152); + _curvea0[335] = _5788; + uint16_t _5789 = (uint16_t)(153); + _curvea0[336] = _5789; + uint16_t _5790 = (uint16_t)(153); + _curvea0[337] = _5790; + uint16_t _5791 = (uint16_t)(153); + _curvea0[338] = _5791; + uint16_t _5792 = (uint16_t)(154); + _curvea0[339] = _5792; + uint16_t _5793 = (uint16_t)(154); + _curvea0[340] = _5793; + uint16_t _5794 = (uint16_t)(154); + _curvea0[341] = _5794; + uint16_t _5795 = (uint16_t)(154); + _curvea0[342] = _5795; + uint16_t _5796 = (uint16_t)(155); + _curvea0[343] = _5796; + uint16_t _5797 = (uint16_t)(155); + _curvea0[344] = _5797; + uint16_t _5798 = (uint16_t)(155); + _curvea0[345] = _5798; + uint16_t _5799 = (uint16_t)(156); + _curvea0[346] = _5799; + uint16_t _5800 = (uint16_t)(156); + _curvea0[347] = _5800; + uint16_t _5801 = (uint16_t)(156); + _curvea0[348] = _5801; + uint16_t _5802 = (uint16_t)(156); + _curvea0[349] = _5802; + uint16_t _5803 = (uint16_t)(157); + _curvea0[350] = _5803; + uint16_t _5804 = (uint16_t)(157); + _curvea0[351] = _5804; + uint16_t _5805 = (uint16_t)(157); + _curvea0[352] = _5805; + uint16_t _5806 = (uint16_t)(157); + _curvea0[353] = _5806; + uint16_t _5807 = (uint16_t)(158); + _curvea0[354] = _5807; + uint16_t _5808 = (uint16_t)(158); + _curvea0[355] = _5808; + uint16_t _5809 = (uint16_t)(158); + _curvea0[356] = _5809; + uint16_t _5810 = (uint16_t)(159); + _curvea0[357] = _5810; + uint16_t _5811 = (uint16_t)(159); + _curvea0[358] = _5811; + uint16_t _5812 = (uint16_t)(159); + _curvea0[359] = _5812; + uint16_t _5813 = (uint16_t)(159); + _curvea0[360] = _5813; + uint16_t _5814 = (uint16_t)(160); + _curvea0[361] = _5814; + uint16_t _5815 = (uint16_t)(160); + _curvea0[362] = _5815; + uint16_t _5816 = (uint16_t)(160); + _curvea0[363] = _5816; + uint16_t _5817 = (uint16_t)(160); + _curvea0[364] = _5817; + uint16_t _5818 = (uint16_t)(161); + _curvea0[365] = _5818; + uint16_t _5819 = (uint16_t)(161); + _curvea0[366] = _5819; + uint16_t _5820 = (uint16_t)(161); + _curvea0[367] = _5820; + uint16_t _5821 = (uint16_t)(161); + _curvea0[368] = _5821; + uint16_t _5822 = (uint16_t)(162); + _curvea0[369] = _5822; + uint16_t _5823 = (uint16_t)(162); + _curvea0[370] = _5823; + uint16_t _5824 = (uint16_t)(162); + _curvea0[371] = _5824; + uint16_t _5825 = (uint16_t)(162); + _curvea0[372] = _5825; + uint16_t _5826 = (uint16_t)(163); + _curvea0[373] = _5826; + uint16_t _5827 = (uint16_t)(163); + _curvea0[374] = _5827; + uint16_t _5828 = (uint16_t)(163); + _curvea0[375] = _5828; + uint16_t _5829 = (uint16_t)(163); + _curvea0[376] = _5829; + uint16_t _5830 = (uint16_t)(164); + _curvea0[377] = _5830; + uint16_t _5831 = (uint16_t)(164); + _curvea0[378] = _5831; + uint16_t _5832 = (uint16_t)(164); + _curvea0[379] = _5832; + uint16_t _5833 = (uint16_t)(164); + _curvea0[380] = _5833; + uint16_t _5834 = (uint16_t)(165); + _curvea0[381] = _5834; + uint16_t _5835 = (uint16_t)(165); + _curvea0[382] = _5835; + uint16_t _5836 = (uint16_t)(165); + _curvea0[383] = _5836; + uint16_t _5837 = (uint16_t)(166); + _curvea0[384] = _5837; + uint16_t _5838 = (uint16_t)(166); + _curvea0[385] = _5838; + uint16_t _5839 = (uint16_t)(166); + _curvea0[386] = _5839; + uint16_t _5840 = (uint16_t)(166); + _curvea0[387] = _5840; + uint16_t _5841 = (uint16_t)(167); + _curvea0[388] = _5841; + uint16_t _5842 = (uint16_t)(167); + _curvea0[389] = _5842; + uint16_t _5843 = (uint16_t)(167); + _curvea0[390] = _5843; + uint16_t _5844 = (uint16_t)(167); + _curvea0[391] = _5844; + uint16_t _5845 = (uint16_t)(167); + _curvea0[392] = _5845; + uint16_t _5846 = (uint16_t)(168); + _curvea0[393] = _5846; + uint16_t _5847 = (uint16_t)(168); + _curvea0[394] = _5847; + uint16_t _5848 = (uint16_t)(168); + _curvea0[395] = _5848; + uint16_t _5849 = (uint16_t)(168); + _curvea0[396] = _5849; + uint16_t _5850 = (uint16_t)(169); + _curvea0[397] = _5850; + uint16_t _5851 = (uint16_t)(169); + _curvea0[398] = _5851; + uint16_t _5852 = (uint16_t)(169); + _curvea0[399] = _5852; + uint16_t _5853 = (uint16_t)(169); + _curvea0[400] = _5853; + uint16_t _5854 = (uint16_t)(170); + _curvea0[401] = _5854; + uint16_t _5855 = (uint16_t)(170); + _curvea0[402] = _5855; + uint16_t _5856 = (uint16_t)(170); + _curvea0[403] = _5856; + uint16_t _5857 = (uint16_t)(170); + _curvea0[404] = _5857; + uint16_t _5858 = (uint16_t)(171); + _curvea0[405] = _5858; + uint16_t _5859 = (uint16_t)(171); + _curvea0[406] = _5859; + uint16_t _5860 = (uint16_t)(171); + _curvea0[407] = _5860; + uint16_t _5861 = (uint16_t)(171); + _curvea0[408] = _5861; + uint16_t _5862 = (uint16_t)(172); + _curvea0[409] = _5862; + uint16_t _5863 = (uint16_t)(172); + _curvea0[410] = _5863; + uint16_t _5864 = (uint16_t)(172); + _curvea0[411] = _5864; + uint16_t _5865 = (uint16_t)(172); + _curvea0[412] = _5865; + uint16_t _5866 = (uint16_t)(173); + _curvea0[413] = _5866; + uint16_t _5867 = (uint16_t)(173); + _curvea0[414] = _5867; + uint16_t _5868 = (uint16_t)(173); + _curvea0[415] = _5868; + uint16_t _5869 = (uint16_t)(173); + _curvea0[416] = _5869; + uint16_t _5870 = (uint16_t)(173); + _curvea0[417] = _5870; + uint16_t _5871 = (uint16_t)(174); + _curvea0[418] = _5871; + uint16_t _5872 = (uint16_t)(174); + _curvea0[419] = _5872; + uint16_t _5873 = (uint16_t)(174); + _curvea0[420] = _5873; + uint16_t _5874 = (uint16_t)(174); + _curvea0[421] = _5874; + uint16_t _5875 = (uint16_t)(175); + _curvea0[422] = _5875; + uint16_t _5876 = (uint16_t)(175); + _curvea0[423] = _5876; + uint16_t _5877 = (uint16_t)(175); + _curvea0[424] = _5877; + uint16_t _5878 = (uint16_t)(175); + _curvea0[425] = _5878; + uint16_t _5879 = (uint16_t)(176); + _curvea0[426] = _5879; + uint16_t _5880 = (uint16_t)(176); + _curvea0[427] = _5880; + uint16_t _5881 = (uint16_t)(176); + _curvea0[428] = _5881; + uint16_t _5882 = (uint16_t)(176); + _curvea0[429] = _5882; + uint16_t _5883 = (uint16_t)(176); + _curvea0[430] = _5883; + uint16_t _5884 = (uint16_t)(177); + _curvea0[431] = _5884; + uint16_t _5885 = (uint16_t)(177); + _curvea0[432] = _5885; + uint16_t _5886 = (uint16_t)(177); + _curvea0[433] = _5886; + uint16_t _5887 = (uint16_t)(177); + _curvea0[434] = _5887; + uint16_t _5888 = (uint16_t)(178); + _curvea0[435] = _5888; + uint16_t _5889 = (uint16_t)(178); + _curvea0[436] = _5889; + uint16_t _5890 = (uint16_t)(178); + _curvea0[437] = _5890; + uint16_t _5891 = (uint16_t)(178); + _curvea0[438] = _5891; + uint16_t _5892 = (uint16_t)(178); + _curvea0[439] = _5892; + uint16_t _5893 = (uint16_t)(179); + _curvea0[440] = _5893; + uint16_t _5894 = (uint16_t)(179); + _curvea0[441] = _5894; + uint16_t _5895 = (uint16_t)(179); + _curvea0[442] = _5895; + uint16_t _5896 = (uint16_t)(179); + _curvea0[443] = _5896; + uint16_t _5897 = (uint16_t)(180); + _curvea0[444] = _5897; + uint16_t _5898 = (uint16_t)(180); + _curvea0[445] = _5898; + uint16_t _5899 = (uint16_t)(180); + _curvea0[446] = _5899; + uint16_t _5900 = (uint16_t)(180); + _curvea0[447] = _5900; + uint16_t _5901 = (uint16_t)(180); + _curvea0[448] = _5901; + uint16_t _5902 = (uint16_t)(181); + _curvea0[449] = _5902; + uint16_t _5903 = (uint16_t)(181); + _curvea0[450] = _5903; + uint16_t _5904 = (uint16_t)(181); + _curvea0[451] = _5904; + uint16_t _5905 = (uint16_t)(181); + _curvea0[452] = _5905; + uint16_t _5906 = (uint16_t)(181); + _curvea0[453] = _5906; + uint16_t _5907 = (uint16_t)(182); + _curvea0[454] = _5907; + uint16_t _5908 = (uint16_t)(182); + _curvea0[455] = _5908; + uint16_t _5909 = (uint16_t)(182); + _curvea0[456] = _5909; + uint16_t _5910 = (uint16_t)(182); + _curvea0[457] = _5910; + uint16_t _5911 = (uint16_t)(183); + _curvea0[458] = _5911; + uint16_t _5912 = (uint16_t)(183); + _curvea0[459] = _5912; + uint16_t _5913 = (uint16_t)(183); + _curvea0[460] = _5913; + uint16_t _5914 = (uint16_t)(183); + _curvea0[461] = _5914; + uint16_t _5915 = (uint16_t)(183); + _curvea0[462] = _5915; + uint16_t _5916 = (uint16_t)(184); + _curvea0[463] = _5916; + uint16_t _5917 = (uint16_t)(184); + _curvea0[464] = _5917; + uint16_t _5918 = (uint16_t)(184); + _curvea0[465] = _5918; + uint16_t _5919 = (uint16_t)(184); + _curvea0[466] = _5919; + uint16_t _5920 = (uint16_t)(184); + _curvea0[467] = _5920; + uint16_t _5921 = (uint16_t)(185); + _curvea0[468] = _5921; + uint16_t _5922 = (uint16_t)(185); + _curvea0[469] = _5922; + uint16_t _5923 = (uint16_t)(185); + _curvea0[470] = _5923; + uint16_t _5924 = (uint16_t)(185); + _curvea0[471] = _5924; + uint16_t _5925 = (uint16_t)(185); + _curvea0[472] = _5925; + uint16_t _5926 = (uint16_t)(186); + _curvea0[473] = _5926; + uint16_t _5927 = (uint16_t)(186); + _curvea0[474] = _5927; + uint16_t _5928 = (uint16_t)(186); + _curvea0[475] = _5928; + uint16_t _5929 = (uint16_t)(186); + _curvea0[476] = _5929; + uint16_t _5930 = (uint16_t)(187); + _curvea0[477] = _5930; + uint16_t _5931 = (uint16_t)(187); + _curvea0[478] = _5931; + uint16_t _5932 = (uint16_t)(187); + _curvea0[479] = _5932; + uint16_t _5933 = (uint16_t)(187); + _curvea0[480] = _5933; + uint16_t _5934 = (uint16_t)(187); + _curvea0[481] = _5934; + uint16_t _5935 = (uint16_t)(188); + _curvea0[482] = _5935; + uint16_t _5936 = (uint16_t)(188); + _curvea0[483] = _5936; + uint16_t _5937 = (uint16_t)(188); + _curvea0[484] = _5937; + uint16_t _5938 = (uint16_t)(188); + _curvea0[485] = _5938; + uint16_t _5939 = (uint16_t)(188); + _curvea0[486] = _5939; + uint16_t _5940 = (uint16_t)(189); + _curvea0[487] = _5940; + uint16_t _5941 = (uint16_t)(189); + _curvea0[488] = _5941; + uint16_t _5942 = (uint16_t)(189); + _curvea0[489] = _5942; + uint16_t _5943 = (uint16_t)(189); + _curvea0[490] = _5943; + uint16_t _5944 = (uint16_t)(189); + _curvea0[491] = _5944; + uint16_t _5945 = (uint16_t)(190); + _curvea0[492] = _5945; + uint16_t _5946 = (uint16_t)(190); + _curvea0[493] = _5946; + uint16_t _5947 = (uint16_t)(190); + _curvea0[494] = _5947; + uint16_t _5948 = (uint16_t)(190); + _curvea0[495] = _5948; + uint16_t _5949 = (uint16_t)(190); + _curvea0[496] = _5949; + uint16_t _5950 = (uint16_t)(190); + _curvea0[497] = _5950; + uint16_t _5951 = (uint16_t)(191); + _curvea0[498] = _5951; + uint16_t _5952 = (uint16_t)(191); + _curvea0[499] = _5952; + uint16_t _5953 = (uint16_t)(191); + _curvea0[500] = _5953; + uint16_t _5954 = (uint16_t)(191); + _curvea0[501] = _5954; + uint16_t _5955 = (uint16_t)(191); + _curvea0[502] = _5955; + uint16_t _5956 = (uint16_t)(192); + _curvea0[503] = _5956; + uint16_t _5957 = (uint16_t)(192); + _curvea0[504] = _5957; + uint16_t _5958 = (uint16_t)(192); + _curvea0[505] = _5958; + uint16_t _5959 = (uint16_t)(192); + _curvea0[506] = _5959; + uint16_t _5960 = (uint16_t)(192); + _curvea0[507] = _5960; + uint16_t _5961 = (uint16_t)(193); + _curvea0[508] = _5961; + uint16_t _5962 = (uint16_t)(193); + _curvea0[509] = _5962; + uint16_t _5963 = (uint16_t)(193); + _curvea0[510] = _5963; + uint16_t _5964 = (uint16_t)(193); + _curvea0[511] = _5964; + uint16_t _5965 = (uint16_t)(193); + _curvea0[512] = _5965; + uint16_t _5966 = (uint16_t)(194); + _curvea0[513] = _5966; + uint16_t _5967 = (uint16_t)(194); + _curvea0[514] = _5967; + uint16_t _5968 = (uint16_t)(194); + _curvea0[515] = _5968; + uint16_t _5969 = (uint16_t)(194); + _curvea0[516] = _5969; + uint16_t _5970 = (uint16_t)(194); + _curvea0[517] = _5970; + uint16_t _5971 = (uint16_t)(195); + _curvea0[518] = _5971; + uint16_t _5972 = (uint16_t)(195); + _curvea0[519] = _5972; + uint16_t _5973 = (uint16_t)(195); + _curvea0[520] = _5973; + uint16_t _5974 = (uint16_t)(195); + _curvea0[521] = _5974; + uint16_t _5975 = (uint16_t)(195); + _curvea0[522] = _5975; + uint16_t _5976 = (uint16_t)(195); + _curvea0[523] = _5976; + uint16_t _5977 = (uint16_t)(196); + _curvea0[524] = _5977; + uint16_t _5978 = (uint16_t)(196); + _curvea0[525] = _5978; + uint16_t _5979 = (uint16_t)(196); + _curvea0[526] = _5979; + uint16_t _5980 = (uint16_t)(196); + _curvea0[527] = _5980; + uint16_t _5981 = (uint16_t)(196); + _curvea0[528] = _5981; + uint16_t _5982 = (uint16_t)(197); + _curvea0[529] = _5982; + uint16_t _5983 = (uint16_t)(197); + _curvea0[530] = _5983; + uint16_t _5984 = (uint16_t)(197); + _curvea0[531] = _5984; + uint16_t _5985 = (uint16_t)(197); + _curvea0[532] = _5985; + uint16_t _5986 = (uint16_t)(197); + _curvea0[533] = _5986; + uint16_t _5987 = (uint16_t)(197); + _curvea0[534] = _5987; + uint16_t _5988 = (uint16_t)(198); + _curvea0[535] = _5988; + uint16_t _5989 = (uint16_t)(198); + _curvea0[536] = _5989; + uint16_t _5990 = (uint16_t)(198); + _curvea0[537] = _5990; + uint16_t _5991 = (uint16_t)(198); + _curvea0[538] = _5991; + uint16_t _5992 = (uint16_t)(198); + _curvea0[539] = _5992; + uint16_t _5993 = (uint16_t)(199); + _curvea0[540] = _5993; + uint16_t _5994 = (uint16_t)(199); + _curvea0[541] = _5994; + uint16_t _5995 = (uint16_t)(199); + _curvea0[542] = _5995; + uint16_t _5996 = (uint16_t)(199); + _curvea0[543] = _5996; + uint16_t _5997 = (uint16_t)(199); + _curvea0[544] = _5997; + uint16_t _5998 = (uint16_t)(199); + _curvea0[545] = _5998; + uint16_t _5999 = (uint16_t)(200); + _curvea0[546] = _5999; + uint16_t _6000 = (uint16_t)(200); + _curvea0[547] = _6000; + uint16_t _6001 = (uint16_t)(200); + _curvea0[548] = _6001; + uint16_t _6002 = (uint16_t)(200); + _curvea0[549] = _6002; + uint16_t _6003 = (uint16_t)(200); + _curvea0[550] = _6003; + uint16_t _6004 = (uint16_t)(200); + _curvea0[551] = _6004; + uint16_t _6005 = (uint16_t)(201); + _curvea0[552] = _6005; + uint16_t _6006 = (uint16_t)(201); + _curvea0[553] = _6006; + uint16_t _6007 = (uint16_t)(201); + _curvea0[554] = _6007; + uint16_t _6008 = (uint16_t)(201); + _curvea0[555] = _6008; + uint16_t _6009 = (uint16_t)(201); + _curvea0[556] = _6009; + uint16_t _6010 = (uint16_t)(202); + _curvea0[557] = _6010; + uint16_t _6011 = (uint16_t)(202); + _curvea0[558] = _6011; + uint16_t _6012 = (uint16_t)(202); + _curvea0[559] = _6012; + uint16_t _6013 = (uint16_t)(202); + _curvea0[560] = _6013; + uint16_t _6014 = (uint16_t)(202); + _curvea0[561] = _6014; + uint16_t _6015 = (uint16_t)(202); + _curvea0[562] = _6015; + uint16_t _6016 = (uint16_t)(203); + _curvea0[563] = _6016; + uint16_t _6017 = (uint16_t)(203); + _curvea0[564] = _6017; + uint16_t _6018 = (uint16_t)(203); + _curvea0[565] = _6018; + uint16_t _6019 = (uint16_t)(203); + _curvea0[566] = _6019; + uint16_t _6020 = (uint16_t)(203); + _curvea0[567] = _6020; + uint16_t _6021 = (uint16_t)(203); + _curvea0[568] = _6021; + uint16_t _6022 = (uint16_t)(204); + _curvea0[569] = _6022; + uint16_t _6023 = (uint16_t)(204); + _curvea0[570] = _6023; + uint16_t _6024 = (uint16_t)(204); + _curvea0[571] = _6024; + uint16_t _6025 = (uint16_t)(204); + _curvea0[572] = _6025; + uint16_t _6026 = (uint16_t)(204); + _curvea0[573] = _6026; + uint16_t _6027 = (uint16_t)(204); + _curvea0[574] = _6027; + uint16_t _6028 = (uint16_t)(205); + _curvea0[575] = _6028; + uint16_t _6029 = (uint16_t)(205); + _curvea0[576] = _6029; + uint16_t _6030 = (uint16_t)(205); + _curvea0[577] = _6030; + uint16_t _6031 = (uint16_t)(205); + _curvea0[578] = _6031; + uint16_t _6032 = (uint16_t)(205); + _curvea0[579] = _6032; + uint16_t _6033 = (uint16_t)(205); + _curvea0[580] = _6033; + uint16_t _6034 = (uint16_t)(206); + _curvea0[581] = _6034; + uint16_t _6035 = (uint16_t)(206); + _curvea0[582] = _6035; + uint16_t _6036 = (uint16_t)(206); + _curvea0[583] = _6036; + uint16_t _6037 = (uint16_t)(206); + _curvea0[584] = _6037; + uint16_t _6038 = (uint16_t)(206); + _curvea0[585] = _6038; + uint16_t _6039 = (uint16_t)(206); + _curvea0[586] = _6039; + uint16_t _6040 = (uint16_t)(207); + _curvea0[587] = _6040; + uint16_t _6041 = (uint16_t)(207); + _curvea0[588] = _6041; + uint16_t _6042 = (uint16_t)(207); + _curvea0[589] = _6042; + uint16_t _6043 = (uint16_t)(207); + _curvea0[590] = _6043; + uint16_t _6044 = (uint16_t)(207); + _curvea0[591] = _6044; + uint16_t _6045 = (uint16_t)(207); + _curvea0[592] = _6045; + uint16_t _6046 = (uint16_t)(208); + _curvea0[593] = _6046; + uint16_t _6047 = (uint16_t)(208); + _curvea0[594] = _6047; + uint16_t _6048 = (uint16_t)(208); + _curvea0[595] = _6048; + uint16_t _6049 = (uint16_t)(208); + _curvea0[596] = _6049; + uint16_t _6050 = (uint16_t)(208); + _curvea0[597] = _6050; + uint16_t _6051 = (uint16_t)(208); + _curvea0[598] = _6051; + uint16_t _6052 = (uint16_t)(209); + _curvea0[599] = _6052; + uint16_t _6053 = (uint16_t)(209); + _curvea0[600] = _6053; + uint16_t _6054 = (uint16_t)(209); + _curvea0[601] = _6054; + uint16_t _6055 = (uint16_t)(209); + _curvea0[602] = _6055; + uint16_t _6056 = (uint16_t)(209); + _curvea0[603] = _6056; + uint16_t _6057 = (uint16_t)(209); + _curvea0[604] = _6057; + uint16_t _6058 = (uint16_t)(209); + _curvea0[605] = _6058; + uint16_t _6059 = (uint16_t)(210); + _curvea0[606] = _6059; + uint16_t _6060 = (uint16_t)(210); + _curvea0[607] = _6060; + uint16_t _6061 = (uint16_t)(210); + _curvea0[608] = _6061; + uint16_t _6062 = (uint16_t)(210); + _curvea0[609] = _6062; + uint16_t _6063 = (uint16_t)(210); + _curvea0[610] = _6063; + uint16_t _6064 = (uint16_t)(210); + _curvea0[611] = _6064; + uint16_t _6065 = (uint16_t)(211); + _curvea0[612] = _6065; + uint16_t _6066 = (uint16_t)(211); + _curvea0[613] = _6066; + uint16_t _6067 = (uint16_t)(211); + _curvea0[614] = _6067; + uint16_t _6068 = (uint16_t)(211); + _curvea0[615] = _6068; + uint16_t _6069 = (uint16_t)(211); + _curvea0[616] = _6069; + uint16_t _6070 = (uint16_t)(211); + _curvea0[617] = _6070; + uint16_t _6071 = (uint16_t)(211); + _curvea0[618] = _6071; + uint16_t _6072 = (uint16_t)(212); + _curvea0[619] = _6072; + uint16_t _6073 = (uint16_t)(212); + _curvea0[620] = _6073; + uint16_t _6074 = (uint16_t)(212); + _curvea0[621] = _6074; + uint16_t _6075 = (uint16_t)(212); + _curvea0[622] = _6075; + uint16_t _6076 = (uint16_t)(212); + _curvea0[623] = _6076; + uint16_t _6077 = (uint16_t)(212); + _curvea0[624] = _6077; + uint16_t _6078 = (uint16_t)(213); + _curvea0[625] = _6078; + uint16_t _6079 = (uint16_t)(213); + _curvea0[626] = _6079; + uint16_t _6080 = (uint16_t)(213); + _curvea0[627] = _6080; + uint16_t _6081 = (uint16_t)(213); + _curvea0[628] = _6081; + uint16_t _6082 = (uint16_t)(213); + _curvea0[629] = _6082; + uint16_t _6083 = (uint16_t)(213); + _curvea0[630] = _6083; + uint16_t _6084 = (uint16_t)(213); + _curvea0[631] = _6084; + uint16_t _6085 = (uint16_t)(214); + _curvea0[632] = _6085; + uint16_t _6086 = (uint16_t)(214); + _curvea0[633] = _6086; + uint16_t _6087 = (uint16_t)(214); + _curvea0[634] = _6087; + uint16_t _6088 = (uint16_t)(214); + _curvea0[635] = _6088; + uint16_t _6089 = (uint16_t)(214); + _curvea0[636] = _6089; + uint16_t _6090 = (uint16_t)(214); + _curvea0[637] = _6090; + uint16_t _6091 = (uint16_t)(214); + _curvea0[638] = _6091; + uint16_t _6092 = (uint16_t)(215); + _curvea0[639] = _6092; + uint16_t _6093 = (uint16_t)(215); + _curvea0[640] = _6093; + uint16_t _6094 = (uint16_t)(215); + _curvea0[641] = _6094; + uint16_t _6095 = (uint16_t)(215); + _curvea0[642] = _6095; + uint16_t _6096 = (uint16_t)(215); + _curvea0[643] = _6096; + uint16_t _6097 = (uint16_t)(215); + _curvea0[644] = _6097; + uint16_t _6098 = (uint16_t)(216); + _curvea0[645] = _6098; + uint16_t _6099 = (uint16_t)(216); + _curvea0[646] = _6099; + uint16_t _6100 = (uint16_t)(216); + _curvea0[647] = _6100; + uint16_t _6101 = (uint16_t)(216); + _curvea0[648] = _6101; + uint16_t _6102 = (uint16_t)(216); + _curvea0[649] = _6102; + uint16_t _6103 = (uint16_t)(216); + _curvea0[650] = _6103; + uint16_t _6104 = (uint16_t)(216); + _curvea0[651] = _6104; + uint16_t _6105 = (uint16_t)(217); + _curvea0[652] = _6105; + uint16_t _6106 = (uint16_t)(217); + _curvea0[653] = _6106; + uint16_t _6107 = (uint16_t)(217); + _curvea0[654] = _6107; + uint16_t _6108 = (uint16_t)(217); + _curvea0[655] = _6108; + uint16_t _6109 = (uint16_t)(217); + _curvea0[656] = _6109; + uint16_t _6110 = (uint16_t)(217); + _curvea0[657] = _6110; + uint16_t _6111 = (uint16_t)(217); + _curvea0[658] = _6111; + uint16_t _6112 = (uint16_t)(218); + _curvea0[659] = _6112; + uint16_t _6113 = (uint16_t)(218); + _curvea0[660] = _6113; + uint16_t _6114 = (uint16_t)(218); + _curvea0[661] = _6114; + uint16_t _6115 = (uint16_t)(218); + _curvea0[662] = _6115; + uint16_t _6116 = (uint16_t)(218); + _curvea0[663] = _6116; + uint16_t _6117 = (uint16_t)(218); + _curvea0[664] = _6117; + uint16_t _6118 = (uint16_t)(218); + _curvea0[665] = _6118; + uint16_t _6119 = (uint16_t)(219); + _curvea0[666] = _6119; + uint16_t _6120 = (uint16_t)(219); + _curvea0[667] = _6120; + uint16_t _6121 = (uint16_t)(219); + _curvea0[668] = _6121; + uint16_t _6122 = (uint16_t)(219); + _curvea0[669] = _6122; + uint16_t _6123 = (uint16_t)(219); + _curvea0[670] = _6123; + uint16_t _6124 = (uint16_t)(219); + _curvea0[671] = _6124; + uint16_t _6125 = (uint16_t)(219); + _curvea0[672] = _6125; + uint16_t _6126 = (uint16_t)(220); + _curvea0[673] = _6126; + uint16_t _6127 = (uint16_t)(220); + _curvea0[674] = _6127; + uint16_t _6128 = (uint16_t)(220); + _curvea0[675] = _6128; + uint16_t _6129 = (uint16_t)(220); + _curvea0[676] = _6129; + uint16_t _6130 = (uint16_t)(220); + _curvea0[677] = _6130; + uint16_t _6131 = (uint16_t)(220); + _curvea0[678] = _6131; + uint16_t _6132 = (uint16_t)(220); + _curvea0[679] = _6132; + uint16_t _6133 = (uint16_t)(220); + _curvea0[680] = _6133; + uint16_t _6134 = (uint16_t)(221); + _curvea0[681] = _6134; + uint16_t _6135 = (uint16_t)(221); + _curvea0[682] = _6135; + uint16_t _6136 = (uint16_t)(221); + _curvea0[683] = _6136; + uint16_t _6137 = (uint16_t)(221); + _curvea0[684] = _6137; + uint16_t _6138 = (uint16_t)(221); + _curvea0[685] = _6138; + uint16_t _6139 = (uint16_t)(221); + _curvea0[686] = _6139; + uint16_t _6140 = (uint16_t)(221); + _curvea0[687] = _6140; + uint16_t _6141 = (uint16_t)(222); + _curvea0[688] = _6141; + uint16_t _6142 = (uint16_t)(222); + _curvea0[689] = _6142; + uint16_t _6143 = (uint16_t)(222); + _curvea0[690] = _6143; + uint16_t _6144 = (uint16_t)(222); + _curvea0[691] = _6144; + uint16_t _6145 = (uint16_t)(222); + _curvea0[692] = _6145; + uint16_t _6146 = (uint16_t)(222); + _curvea0[693] = _6146; + uint16_t _6147 = (uint16_t)(222); + _curvea0[694] = _6147; + uint16_t _6148 = (uint16_t)(223); + _curvea0[695] = _6148; + uint16_t _6149 = (uint16_t)(223); + _curvea0[696] = _6149; + uint16_t _6150 = (uint16_t)(223); + _curvea0[697] = _6150; + uint16_t _6151 = (uint16_t)(223); + _curvea0[698] = _6151; + uint16_t _6152 = (uint16_t)(223); + _curvea0[699] = _6152; + uint16_t _6153 = (uint16_t)(223); + _curvea0[700] = _6153; + uint16_t _6154 = (uint16_t)(223); + _curvea0[701] = _6154; + uint16_t _6155 = (uint16_t)(223); + _curvea0[702] = _6155; + uint16_t _6156 = (uint16_t)(224); + _curvea0[703] = _6156; + uint16_t _6157 = (uint16_t)(224); + _curvea0[704] = _6157; + uint16_t _6158 = (uint16_t)(224); + _curvea0[705] = _6158; + uint16_t _6159 = (uint16_t)(224); + _curvea0[706] = _6159; + uint16_t _6160 = (uint16_t)(224); + _curvea0[707] = _6160; + uint16_t _6161 = (uint16_t)(224); + _curvea0[708] = _6161; + uint16_t _6162 = (uint16_t)(224); + _curvea0[709] = _6162; + uint16_t _6163 = (uint16_t)(224); + _curvea0[710] = _6163; + uint16_t _6164 = (uint16_t)(225); + _curvea0[711] = _6164; + uint16_t _6165 = (uint16_t)(225); + _curvea0[712] = _6165; + uint16_t _6166 = (uint16_t)(225); + _curvea0[713] = _6166; + uint16_t _6167 = (uint16_t)(225); + _curvea0[714] = _6167; + uint16_t _6168 = (uint16_t)(225); + _curvea0[715] = _6168; + uint16_t _6169 = (uint16_t)(225); + _curvea0[716] = _6169; + uint16_t _6170 = (uint16_t)(225); + _curvea0[717] = _6170; + uint16_t _6171 = (uint16_t)(226); + _curvea0[718] = _6171; + uint16_t _6172 = (uint16_t)(226); + _curvea0[719] = _6172; + uint16_t _6173 = (uint16_t)(226); + _curvea0[720] = _6173; + uint16_t _6174 = (uint16_t)(226); + _curvea0[721] = _6174; + uint16_t _6175 = (uint16_t)(226); + _curvea0[722] = _6175; + uint16_t _6176 = (uint16_t)(226); + _curvea0[723] = _6176; + uint16_t _6177 = (uint16_t)(226); + _curvea0[724] = _6177; + uint16_t _6178 = (uint16_t)(226); + _curvea0[725] = _6178; + uint16_t _6179 = (uint16_t)(227); + _curvea0[726] = _6179; + uint16_t _6180 = (uint16_t)(227); + _curvea0[727] = _6180; + uint16_t _6181 = (uint16_t)(227); + _curvea0[728] = _6181; + uint16_t _6182 = (uint16_t)(227); + _curvea0[729] = _6182; + uint16_t _6183 = (uint16_t)(227); + _curvea0[730] = _6183; + uint16_t _6184 = (uint16_t)(227); + _curvea0[731] = _6184; + uint16_t _6185 = (uint16_t)(227); + _curvea0[732] = _6185; + uint16_t _6186 = (uint16_t)(227); + _curvea0[733] = _6186; + uint16_t _6187 = (uint16_t)(228); + _curvea0[734] = _6187; + uint16_t _6188 = (uint16_t)(228); + _curvea0[735] = _6188; + uint16_t _6189 = (uint16_t)(228); + _curvea0[736] = _6189; + uint16_t _6190 = (uint16_t)(228); + _curvea0[737] = _6190; + uint16_t _6191 = (uint16_t)(228); + _curvea0[738] = _6191; + uint16_t _6192 = (uint16_t)(228); + _curvea0[739] = _6192; + uint16_t _6193 = (uint16_t)(228); + _curvea0[740] = _6193; + uint16_t _6194 = (uint16_t)(228); + _curvea0[741] = _6194; + uint16_t _6195 = (uint16_t)(228); + _curvea0[742] = _6195; + uint16_t _6196 = (uint16_t)(229); + _curvea0[743] = _6196; + uint16_t _6197 = (uint16_t)(229); + _curvea0[744] = _6197; + uint16_t _6198 = (uint16_t)(229); + _curvea0[745] = _6198; + uint16_t _6199 = (uint16_t)(229); + _curvea0[746] = _6199; + uint16_t _6200 = (uint16_t)(229); + _curvea0[747] = _6200; + uint16_t _6201 = (uint16_t)(229); + _curvea0[748] = _6201; + uint16_t _6202 = (uint16_t)(229); + _curvea0[749] = _6202; + uint16_t _6203 = (uint16_t)(229); + _curvea0[750] = _6203; + uint16_t _6204 = (uint16_t)(230); + _curvea0[751] = _6204; + uint16_t _6205 = (uint16_t)(230); + _curvea0[752] = _6205; + uint16_t _6206 = (uint16_t)(230); + _curvea0[753] = _6206; + uint16_t _6207 = (uint16_t)(230); + _curvea0[754] = _6207; + uint16_t _6208 = (uint16_t)(230); + _curvea0[755] = _6208; + uint16_t _6209 = (uint16_t)(230); + _curvea0[756] = _6209; + uint16_t _6210 = (uint16_t)(230); + _curvea0[757] = _6210; + uint16_t _6211 = (uint16_t)(230); + _curvea0[758] = _6211; + uint16_t _6212 = (uint16_t)(231); + _curvea0[759] = _6212; + uint16_t _6213 = (uint16_t)(231); + _curvea0[760] = _6213; + uint16_t _6214 = (uint16_t)(231); + _curvea0[761] = _6214; + uint16_t _6215 = (uint16_t)(231); + _curvea0[762] = _6215; + uint16_t _6216 = (uint16_t)(231); + _curvea0[763] = _6216; + uint16_t _6217 = (uint16_t)(231); + _curvea0[764] = _6217; + uint16_t _6218 = (uint16_t)(231); + _curvea0[765] = _6218; + uint16_t _6219 = (uint16_t)(231); + _curvea0[766] = _6219; + uint16_t _6220 = (uint16_t)(231); + _curvea0[767] = _6220; + uint16_t _6221 = (uint16_t)(232); + _curvea0[768] = _6221; + uint16_t _6222 = (uint16_t)(232); + _curvea0[769] = _6222; + uint16_t _6223 = (uint16_t)(232); + _curvea0[770] = _6223; + uint16_t _6224 = (uint16_t)(232); + _curvea0[771] = _6224; + uint16_t _6225 = (uint16_t)(232); + _curvea0[772] = _6225; + uint16_t _6226 = (uint16_t)(232); + _curvea0[773] = _6226; + uint16_t _6227 = (uint16_t)(232); + _curvea0[774] = _6227; + uint16_t _6228 = (uint16_t)(232); + _curvea0[775] = _6228; + uint16_t _6229 = (uint16_t)(233); + _curvea0[776] = _6229; + uint16_t _6230 = (uint16_t)(233); + _curvea0[777] = _6230; + uint16_t _6231 = (uint16_t)(233); + _curvea0[778] = _6231; + uint16_t _6232 = (uint16_t)(233); + _curvea0[779] = _6232; + uint16_t _6233 = (uint16_t)(233); + _curvea0[780] = _6233; + uint16_t _6234 = (uint16_t)(233); + _curvea0[781] = _6234; + uint16_t _6235 = (uint16_t)(233); + _curvea0[782] = _6235; + uint16_t _6236 = (uint16_t)(233); + _curvea0[783] = _6236; + uint16_t _6237 = (uint16_t)(233); + _curvea0[784] = _6237; + uint16_t _6238 = (uint16_t)(234); + _curvea0[785] = _6238; + uint16_t _6239 = (uint16_t)(234); + _curvea0[786] = _6239; + uint16_t _6240 = (uint16_t)(234); + _curvea0[787] = _6240; + uint16_t _6241 = (uint16_t)(234); + _curvea0[788] = _6241; + uint16_t _6242 = (uint16_t)(234); + _curvea0[789] = _6242; + uint16_t _6243 = (uint16_t)(234); + _curvea0[790] = _6243; + uint16_t _6244 = (uint16_t)(234); + _curvea0[791] = _6244; + uint16_t _6245 = (uint16_t)(234); + _curvea0[792] = _6245; + uint16_t _6246 = (uint16_t)(234); + _curvea0[793] = _6246; + uint16_t _6247 = (uint16_t)(235); + _curvea0[794] = _6247; + uint16_t _6248 = (uint16_t)(235); + _curvea0[795] = _6248; + uint16_t _6249 = (uint16_t)(235); + _curvea0[796] = _6249; + uint16_t _6250 = (uint16_t)(235); + _curvea0[797] = _6250; + uint16_t _6251 = (uint16_t)(235); + _curvea0[798] = _6251; + uint16_t _6252 = (uint16_t)(235); + _curvea0[799] = _6252; + uint16_t _6253 = (uint16_t)(235); + _curvea0[800] = _6253; + uint16_t _6254 = (uint16_t)(235); + _curvea0[801] = _6254; + uint16_t _6255 = (uint16_t)(235); + _curvea0[802] = _6255; + uint16_t _6256 = (uint16_t)(236); + _curvea0[803] = _6256; + uint16_t _6257 = (uint16_t)(236); + _curvea0[804] = _6257; + uint16_t _6258 = (uint16_t)(236); + _curvea0[805] = _6258; + uint16_t _6259 = (uint16_t)(236); + _curvea0[806] = _6259; + uint16_t _6260 = (uint16_t)(236); + _curvea0[807] = _6260; + uint16_t _6261 = (uint16_t)(236); + _curvea0[808] = _6261; + uint16_t _6262 = (uint16_t)(236); + _curvea0[809] = _6262; + uint16_t _6263 = (uint16_t)(236); + _curvea0[810] = _6263; + uint16_t _6264 = (uint16_t)(236); + _curvea0[811] = _6264; + uint16_t _6265 = (uint16_t)(237); + _curvea0[812] = _6265; + uint16_t _6266 = (uint16_t)(237); + _curvea0[813] = _6266; + uint16_t _6267 = (uint16_t)(237); + _curvea0[814] = _6267; + uint16_t _6268 = (uint16_t)(237); + _curvea0[815] = _6268; + uint16_t _6269 = (uint16_t)(237); + _curvea0[816] = _6269; + uint16_t _6270 = (uint16_t)(237); + _curvea0[817] = _6270; + uint16_t _6271 = (uint16_t)(237); + _curvea0[818] = _6271; + uint16_t _6272 = (uint16_t)(237); + _curvea0[819] = _6272; + uint16_t _6273 = (uint16_t)(237); + _curvea0[820] = _6273; + uint16_t _6274 = (uint16_t)(237); + _curvea0[821] = _6274; + uint16_t _6275 = (uint16_t)(238); + _curvea0[822] = _6275; + uint16_t _6276 = (uint16_t)(238); + _curvea0[823] = _6276; + uint16_t _6277 = (uint16_t)(238); + _curvea0[824] = _6277; + uint16_t _6278 = (uint16_t)(238); + _curvea0[825] = _6278; + uint16_t _6279 = (uint16_t)(238); + _curvea0[826] = _6279; + uint16_t _6280 = (uint16_t)(238); + _curvea0[827] = _6280; + uint16_t _6281 = (uint16_t)(238); + _curvea0[828] = _6281; + uint16_t _6282 = (uint16_t)(238); + _curvea0[829] = _6282; + uint16_t _6283 = (uint16_t)(238); + _curvea0[830] = _6283; + uint16_t _6284 = (uint16_t)(239); + _curvea0[831] = _6284; + uint16_t _6285 = (uint16_t)(239); + _curvea0[832] = _6285; + uint16_t _6286 = (uint16_t)(239); + _curvea0[833] = _6286; + uint16_t _6287 = (uint16_t)(239); + _curvea0[834] = _6287; + uint16_t _6288 = (uint16_t)(239); + _curvea0[835] = _6288; + uint16_t _6289 = (uint16_t)(239); + _curvea0[836] = _6289; + uint16_t _6290 = (uint16_t)(239); + _curvea0[837] = _6290; + uint16_t _6291 = (uint16_t)(239); + _curvea0[838] = _6291; + uint16_t _6292 = (uint16_t)(239); + _curvea0[839] = _6292; + uint16_t _6293 = (uint16_t)(239); + _curvea0[840] = _6293; + uint16_t _6294 = (uint16_t)(240); + _curvea0[841] = _6294; + uint16_t _6295 = (uint16_t)(240); + _curvea0[842] = _6295; + uint16_t _6296 = (uint16_t)(240); + _curvea0[843] = _6296; + uint16_t _6297 = (uint16_t)(240); + _curvea0[844] = _6297; + uint16_t _6298 = (uint16_t)(240); + _curvea0[845] = _6298; + uint16_t _6299 = (uint16_t)(240); + _curvea0[846] = _6299; + uint16_t _6300 = (uint16_t)(240); + _curvea0[847] = _6300; + uint16_t _6301 = (uint16_t)(240); + _curvea0[848] = _6301; + uint16_t _6302 = (uint16_t)(240); + _curvea0[849] = _6302; + uint16_t _6303 = (uint16_t)(240); + _curvea0[850] = _6303; + uint16_t _6304 = (uint16_t)(241); + _curvea0[851] = _6304; + uint16_t _6305 = (uint16_t)(241); + _curvea0[852] = _6305; + uint16_t _6306 = (uint16_t)(241); + _curvea0[853] = _6306; + uint16_t _6307 = (uint16_t)(241); + _curvea0[854] = _6307; + uint16_t _6308 = (uint16_t)(241); + _curvea0[855] = _6308; + uint16_t _6309 = (uint16_t)(241); + _curvea0[856] = _6309; + uint16_t _6310 = (uint16_t)(241); + _curvea0[857] = _6310; + uint16_t _6311 = (uint16_t)(241); + _curvea0[858] = _6311; + uint16_t _6312 = (uint16_t)(241); + _curvea0[859] = _6312; + uint16_t _6313 = (uint16_t)(241); + _curvea0[860] = _6313; + uint16_t _6314 = (uint16_t)(242); + _curvea0[861] = _6314; + uint16_t _6315 = (uint16_t)(242); + _curvea0[862] = _6315; + uint16_t _6316 = (uint16_t)(242); + _curvea0[863] = _6316; + uint16_t _6317 = (uint16_t)(242); + _curvea0[864] = _6317; + uint16_t _6318 = (uint16_t)(242); + _curvea0[865] = _6318; + uint16_t _6319 = (uint16_t)(242); + _curvea0[866] = _6319; + uint16_t _6320 = (uint16_t)(242); + _curvea0[867] = _6320; + uint16_t _6321 = (uint16_t)(242); + _curvea0[868] = _6321; + uint16_t _6322 = (uint16_t)(242); + _curvea0[869] = _6322; + uint16_t _6323 = (uint16_t)(242); + _curvea0[870] = _6323; + uint16_t _6324 = (uint16_t)(243); + _curvea0[871] = _6324; + uint16_t _6325 = (uint16_t)(243); + _curvea0[872] = _6325; + uint16_t _6326 = (uint16_t)(243); + _curvea0[873] = _6326; + uint16_t _6327 = (uint16_t)(243); + _curvea0[874] = _6327; + uint16_t _6328 = (uint16_t)(243); + _curvea0[875] = _6328; + uint16_t _6329 = (uint16_t)(243); + _curvea0[876] = _6329; + uint16_t _6330 = (uint16_t)(243); + _curvea0[877] = _6330; + uint16_t _6331 = (uint16_t)(243); + _curvea0[878] = _6331; + uint16_t _6332 = (uint16_t)(243); + _curvea0[879] = _6332; + uint16_t _6333 = (uint16_t)(243); + _curvea0[880] = _6333; + uint16_t _6334 = (uint16_t)(244); + _curvea0[881] = _6334; + uint16_t _6335 = (uint16_t)(244); + _curvea0[882] = _6335; + uint16_t _6336 = (uint16_t)(244); + _curvea0[883] = _6336; + uint16_t _6337 = (uint16_t)(244); + _curvea0[884] = _6337; + uint16_t _6338 = (uint16_t)(244); + _curvea0[885] = _6338; + uint16_t _6339 = (uint16_t)(244); + _curvea0[886] = _6339; + uint16_t _6340 = (uint16_t)(244); + _curvea0[887] = _6340; + uint16_t _6341 = (uint16_t)(244); + _curvea0[888] = _6341; + uint16_t _6342 = (uint16_t)(244); + _curvea0[889] = _6342; + uint16_t _6343 = (uint16_t)(244); + _curvea0[890] = _6343; + uint16_t _6344 = (uint16_t)(244); + _curvea0[891] = _6344; + uint16_t _6345 = (uint16_t)(245); + _curvea0[892] = _6345; + uint16_t _6346 = (uint16_t)(245); + _curvea0[893] = _6346; + uint16_t _6347 = (uint16_t)(245); + _curvea0[894] = _6347; + uint16_t _6348 = (uint16_t)(245); + _curvea0[895] = _6348; + uint16_t _6349 = (uint16_t)(245); + _curvea0[896] = _6349; + uint16_t _6350 = (uint16_t)(245); + _curvea0[897] = _6350; + uint16_t _6351 = (uint16_t)(245); + _curvea0[898] = _6351; + uint16_t _6352 = (uint16_t)(245); + _curvea0[899] = _6352; + uint16_t _6353 = (uint16_t)(245); + _curvea0[900] = _6353; + uint16_t _6354 = (uint16_t)(245); + _curvea0[901] = _6354; + uint16_t _6355 = (uint16_t)(245); + _curvea0[902] = _6355; + uint16_t _6356 = (uint16_t)(246); + _curvea0[903] = _6356; + uint16_t _6357 = (uint16_t)(246); + _curvea0[904] = _6357; + uint16_t _6358 = (uint16_t)(246); + _curvea0[905] = _6358; + uint16_t _6359 = (uint16_t)(246); + _curvea0[906] = _6359; + uint16_t _6360 = (uint16_t)(246); + _curvea0[907] = _6360; + uint16_t _6361 = (uint16_t)(246); + _curvea0[908] = _6361; + uint16_t _6362 = (uint16_t)(246); + _curvea0[909] = _6362; + uint16_t _6363 = (uint16_t)(246); + _curvea0[910] = _6363; + uint16_t _6364 = (uint16_t)(246); + _curvea0[911] = _6364; + uint16_t _6365 = (uint16_t)(246); + _curvea0[912] = _6365; + uint16_t _6366 = (uint16_t)(246); + _curvea0[913] = _6366; + uint16_t _6367 = (uint16_t)(247); + _curvea0[914] = _6367; + uint16_t _6368 = (uint16_t)(247); + _curvea0[915] = _6368; + uint16_t _6369 = (uint16_t)(247); + _curvea0[916] = _6369; + uint16_t _6370 = (uint16_t)(247); + _curvea0[917] = _6370; + uint16_t _6371 = (uint16_t)(247); + _curvea0[918] = _6371; + uint16_t _6372 = (uint16_t)(247); + _curvea0[919] = _6372; + uint16_t _6373 = (uint16_t)(247); + _curvea0[920] = _6373; + uint16_t _6374 = (uint16_t)(247); + _curvea0[921] = _6374; + uint16_t _6375 = (uint16_t)(247); + _curvea0[922] = _6375; + uint16_t _6376 = (uint16_t)(247); + _curvea0[923] = _6376; + uint16_t _6377 = (uint16_t)(247); + _curvea0[924] = _6377; + uint16_t _6378 = (uint16_t)(248); + _curvea0[925] = _6378; + uint16_t _6379 = (uint16_t)(248); + _curvea0[926] = _6379; + uint16_t _6380 = (uint16_t)(248); + _curvea0[927] = _6380; + uint16_t _6381 = (uint16_t)(248); + _curvea0[928] = _6381; + uint16_t _6382 = (uint16_t)(248); + _curvea0[929] = _6382; + uint16_t _6383 = (uint16_t)(248); + _curvea0[930] = _6383; + uint16_t _6384 = (uint16_t)(248); + _curvea0[931] = _6384; + uint16_t _6385 = (uint16_t)(248); + _curvea0[932] = _6385; + uint16_t _6386 = (uint16_t)(248); + _curvea0[933] = _6386; + uint16_t _6387 = (uint16_t)(248); + _curvea0[934] = _6387; + uint16_t _6388 = (uint16_t)(248); + _curvea0[935] = _6388; + uint16_t _6389 = (uint16_t)(249); + _curvea0[936] = _6389; + uint16_t _6390 = (uint16_t)(249); + _curvea0[937] = _6390; + uint16_t _6391 = (uint16_t)(249); + _curvea0[938] = _6391; + uint16_t _6392 = (uint16_t)(249); + _curvea0[939] = _6392; + uint16_t _6393 = (uint16_t)(249); + _curvea0[940] = _6393; + uint16_t _6394 = (uint16_t)(249); + _curvea0[941] = _6394; + uint16_t _6395 = (uint16_t)(249); + _curvea0[942] = _6395; + uint16_t _6396 = (uint16_t)(249); + _curvea0[943] = _6396; + uint16_t _6397 = (uint16_t)(249); + _curvea0[944] = _6397; + uint16_t _6398 = (uint16_t)(249); + _curvea0[945] = _6398; + uint16_t _6399 = (uint16_t)(249); + _curvea0[946] = _6399; + uint16_t _6400 = (uint16_t)(249); + _curvea0[947] = _6400; + uint16_t _6401 = (uint16_t)(250); + _curvea0[948] = _6401; + uint16_t _6402 = (uint16_t)(250); + _curvea0[949] = _6402; + uint16_t _6403 = (uint16_t)(250); + _curvea0[950] = _6403; + uint16_t _6404 = (uint16_t)(250); + _curvea0[951] = _6404; + uint16_t _6405 = (uint16_t)(250); + _curvea0[952] = _6405; + uint16_t _6406 = (uint16_t)(250); + _curvea0[953] = _6406; + uint16_t _6407 = (uint16_t)(250); + _curvea0[954] = _6407; + uint16_t _6408 = (uint16_t)(250); + _curvea0[955] = _6408; + uint16_t _6409 = (uint16_t)(250); + _curvea0[956] = _6409; + uint16_t _6410 = (uint16_t)(250); + _curvea0[957] = _6410; + uint16_t _6411 = (uint16_t)(250); + _curvea0[958] = _6411; + uint16_t _6412 = (uint16_t)(250); + _curvea0[959] = _6412; + uint16_t _6413 = (uint16_t)(251); + _curvea0[960] = _6413; + uint16_t _6414 = (uint16_t)(251); + _curvea0[961] = _6414; + uint16_t _6415 = (uint16_t)(251); + _curvea0[962] = _6415; + uint16_t _6416 = (uint16_t)(251); + _curvea0[963] = _6416; + uint16_t _6417 = (uint16_t)(251); + _curvea0[964] = _6417; + uint16_t _6418 = (uint16_t)(251); + _curvea0[965] = _6418; + uint16_t _6419 = (uint16_t)(251); + _curvea0[966] = _6419; + uint16_t _6420 = (uint16_t)(251); + _curvea0[967] = _6420; + uint16_t _6421 = (uint16_t)(251); + _curvea0[968] = _6421; + uint16_t _6422 = (uint16_t)(251); + _curvea0[969] = _6422; + uint16_t _6423 = (uint16_t)(251); + _curvea0[970] = _6423; + uint16_t _6424 = (uint16_t)(251); + _curvea0[971] = _6424; + uint16_t _6425 = (uint16_t)(252); + _curvea0[972] = _6425; + uint16_t _6426 = (uint16_t)(252); + _curvea0[973] = _6426; + uint16_t _6427 = (uint16_t)(252); + _curvea0[974] = _6427; + uint16_t _6428 = (uint16_t)(252); + _curvea0[975] = _6428; + uint16_t _6429 = (uint16_t)(252); + _curvea0[976] = _6429; + uint16_t _6430 = (uint16_t)(252); + _curvea0[977] = _6430; + uint16_t _6431 = (uint16_t)(252); + _curvea0[978] = _6431; + uint16_t _6432 = (uint16_t)(252); + _curvea0[979] = _6432; + uint16_t _6433 = (uint16_t)(252); + _curvea0[980] = _6433; + uint16_t _6434 = (uint16_t)(252); + _curvea0[981] = _6434; + uint16_t _6435 = (uint16_t)(252); + _curvea0[982] = _6435; + uint16_t _6436 = (uint16_t)(252); + _curvea0[983] = _6436; + uint16_t _6437 = (uint16_t)(252); + _curvea0[984] = _6437; + uint16_t _6438 = (uint16_t)(253); + _curvea0[985] = _6438; + uint16_t _6439 = (uint16_t)(253); + _curvea0[986] = _6439; + uint16_t _6440 = (uint16_t)(253); + _curvea0[987] = _6440; + uint16_t _6441 = (uint16_t)(253); + _curvea0[988] = _6441; + uint16_t _6442 = (uint16_t)(253); + _curvea0[989] = _6442; + uint16_t _6443 = (uint16_t)(253); + _curvea0[990] = _6443; + uint16_t _6444 = (uint16_t)(253); + _curvea0[991] = _6444; + uint16_t _6445 = (uint16_t)(253); + _curvea0[992] = _6445; + uint16_t _6446 = (uint16_t)(253); + _curvea0[993] = _6446; + uint16_t _6447 = (uint16_t)(253); + _curvea0[994] = _6447; + uint16_t _6448 = (uint16_t)(253); + _curvea0[995] = _6448; + uint16_t _6449 = (uint16_t)(253); + _curvea0[996] = _6449; + uint16_t _6450 = (uint16_t)(253); + _curvea0[997] = _6450; + uint16_t _6451 = (uint16_t)(254); + _curvea0[998] = _6451; + uint16_t _6452 = (uint16_t)(254); + _curvea0[999] = _6452; + uint16_t _6453 = (uint16_t)(254); + _curvea0[1000] = _6453; + uint16_t _6454 = (uint16_t)(254); + _curvea0[1001] = _6454; + uint16_t _6455 = (uint16_t)(254); + _curvea0[1002] = _6455; + uint16_t _6456 = (uint16_t)(254); + _curvea0[1003] = _6456; + uint16_t _6457 = (uint16_t)(254); + _curvea0[1004] = _6457; + uint16_t _6458 = (uint16_t)(254); + _curvea0[1005] = _6458; + uint16_t _6459 = (uint16_t)(254); + _curvea0[1006] = _6459; + uint16_t _6460 = (uint16_t)(254); + _curvea0[1007] = _6460; + uint16_t _6461 = (uint16_t)(254); + _curvea0[1008] = _6461; + uint16_t _6462 = (uint16_t)(254); + _curvea0[1009] = _6462; + uint16_t _6463 = (uint16_t)(254); + _curvea0[1010] = _6463; + uint16_t _6464 = (uint16_t)(255); + _curvea0[1011] = _6464; + uint16_t _6465 = (uint16_t)(255); + _curvea0[1012] = _6465; + uint16_t _6466 = (uint16_t)(255); + _curvea0[1013] = _6466; + uint16_t _6467 = (uint16_t)(255); + _curvea0[1014] = _6467; + uint16_t _6468 = (uint16_t)(255); + _curvea0[1015] = _6468; + uint16_t _6469 = (uint16_t)(255); + _curvea0[1016] = _6469; + uint16_t _6470 = (uint16_t)(255); + _curvea0[1017] = _6470; + uint16_t _6471 = (uint16_t)(255); + _curvea0[1018] = _6471; + uint16_t _6472 = (uint16_t)(255); + _curvea0[1019] = _6472; + uint16_t _6473 = (uint16_t)(255); + _curvea0[1020] = _6473; + uint16_t _6474 = (uint16_t)(255); + _curvea0[1021] = _6474; + uint16_t _6475 = (uint16_t)(255); + _curvea0[1022] = _6475; + uint16_t _6476 = (uint16_t)(255); + _curvea0[1023] = _6476; + + int16_t _6477 = (int16_t)(1023); + int16_t _6478 = min(_corrected_stencil_4, _6477); + int16_t _6479 = (int16_t)(0); + int16_t _6480 = max(_6478, _6479); + uint16_t _6481 = (uint16_t)(_6480); + int32_t _6482 = (int32_t)(_6481); + uint16_t _6483 = ((const uint16_t *)_curvea0)[_6482]; + return _6483; +} + +//store is: curved.stencil((curved_s0_x_x_2*2), curved_s0_y_2, 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x_2*2), curved_s0_y_2, 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_4(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_5 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _6500 = (uint16_t)(0); + _curvea0[0] = _6500; + uint16_t _6501 = (uint16_t)(4); + _curvea0[1] = _6501; + uint16_t _6502 = (uint16_t)(7); + _curvea0[2] = _6502; + uint16_t _6503 = (uint16_t)(8); + _curvea0[3] = _6503; + uint16_t _6504 = (uint16_t)(10); + _curvea0[4] = _6504; + uint16_t _6505 = (uint16_t)(11); + _curvea0[5] = _6505; + uint16_t _6506 = (uint16_t)(12); + _curvea0[6] = _6506; + uint16_t _6507 = (uint16_t)(13); + _curvea0[7] = _6507; + uint16_t _6508 = (uint16_t)(14); + _curvea0[8] = _6508; + uint16_t _6509 = (uint16_t)(15); + _curvea0[9] = _6509; + uint16_t _6510 = (uint16_t)(16); + _curvea0[10] = _6510; + uint16_t _6511 = (uint16_t)(17); + _curvea0[11] = _6511; + uint16_t _6512 = (uint16_t)(18); + _curvea0[12] = _6512; + uint16_t _6513 = (uint16_t)(19); + _curvea0[13] = _6513; + uint16_t _6514 = (uint16_t)(20); + _curvea0[14] = _6514; + uint16_t _6515 = (uint16_t)(21); + _curvea0[15] = _6515; + uint16_t _6516 = (uint16_t)(22); + _curvea0[16] = _6516; + uint16_t _6517 = (uint16_t)(22); + _curvea0[17] = _6517; + uint16_t _6518 = (uint16_t)(23); + _curvea0[18] = _6518; + uint16_t _6519 = (uint16_t)(24); + _curvea0[19] = _6519; + uint16_t _6520 = (uint16_t)(25); + _curvea0[20] = _6520; + uint16_t _6521 = (uint16_t)(25); + _curvea0[21] = _6521; + uint16_t _6522 = (uint16_t)(26); + _curvea0[22] = _6522; + uint16_t _6523 = (uint16_t)(27); + _curvea0[23] = _6523; + uint16_t _6524 = (uint16_t)(27); + _curvea0[24] = _6524; + uint16_t _6525 = (uint16_t)(28); + _curvea0[25] = _6525; + uint16_t _6526 = (uint16_t)(29); + _curvea0[26] = _6526; + uint16_t _6527 = (uint16_t)(29); + _curvea0[27] = _6527; + uint16_t _6528 = (uint16_t)(30); + _curvea0[28] = _6528; + uint16_t _6529 = (uint16_t)(31); + _curvea0[29] = _6529; + uint16_t _6530 = (uint16_t)(31); + _curvea0[30] = _6530; + uint16_t _6531 = (uint16_t)(32); + _curvea0[31] = _6531; + uint16_t _6532 = (uint16_t)(33); + _curvea0[32] = _6532; + uint16_t _6533 = (uint16_t)(33); + _curvea0[33] = _6533; + uint16_t _6534 = (uint16_t)(34); + _curvea0[34] = _6534; + uint16_t _6535 = (uint16_t)(34); + _curvea0[35] = _6535; + uint16_t _6536 = (uint16_t)(35); + _curvea0[36] = _6536; + uint16_t _6537 = (uint16_t)(36); + _curvea0[37] = _6537; + uint16_t _6538 = (uint16_t)(36); + _curvea0[38] = _6538; + uint16_t _6539 = (uint16_t)(37); + _curvea0[39] = _6539; + uint16_t _6540 = (uint16_t)(37); + _curvea0[40] = _6540; + uint16_t _6541 = (uint16_t)(38); + _curvea0[41] = _6541; + uint16_t _6542 = (uint16_t)(39); + _curvea0[42] = _6542; + uint16_t _6543 = (uint16_t)(39); + _curvea0[43] = _6543; + uint16_t _6544 = (uint16_t)(40); + _curvea0[44] = _6544; + uint16_t _6545 = (uint16_t)(40); + _curvea0[45] = _6545; + uint16_t _6546 = (uint16_t)(41); + _curvea0[46] = _6546; + uint16_t _6547 = (uint16_t)(41); + _curvea0[47] = _6547; + uint16_t _6548 = (uint16_t)(42); + _curvea0[48] = _6548; + uint16_t _6549 = (uint16_t)(42); + _curvea0[49] = _6549; + uint16_t _6550 = (uint16_t)(43); + _curvea0[50] = _6550; + uint16_t _6551 = (uint16_t)(44); + _curvea0[51] = _6551; + uint16_t _6552 = (uint16_t)(44); + _curvea0[52] = _6552; + uint16_t _6553 = (uint16_t)(45); + _curvea0[53] = _6553; + uint16_t _6554 = (uint16_t)(45); + _curvea0[54] = _6554; + uint16_t _6555 = (uint16_t)(46); + _curvea0[55] = _6555; + uint16_t _6556 = (uint16_t)(46); + _curvea0[56] = _6556; + uint16_t _6557 = (uint16_t)(47); + _curvea0[57] = _6557; + uint16_t _6558 = (uint16_t)(47); + _curvea0[58] = _6558; + uint16_t _6559 = (uint16_t)(48); + _curvea0[59] = _6559; + uint16_t _6560 = (uint16_t)(48); + _curvea0[60] = _6560; + uint16_t _6561 = (uint16_t)(49); + _curvea0[61] = _6561; + uint16_t _6562 = (uint16_t)(49); + _curvea0[62] = _6562; + uint16_t _6563 = (uint16_t)(50); + _curvea0[63] = _6563; + uint16_t _6564 = (uint16_t)(50); + _curvea0[64] = _6564; + uint16_t _6565 = (uint16_t)(51); + _curvea0[65] = _6565; + uint16_t _6566 = (uint16_t)(51); + _curvea0[66] = _6566; + uint16_t _6567 = (uint16_t)(52); + _curvea0[67] = _6567; + uint16_t _6568 = (uint16_t)(52); + _curvea0[68] = _6568; + uint16_t _6569 = (uint16_t)(53); + _curvea0[69] = _6569; + uint16_t _6570 = (uint16_t)(53); + _curvea0[70] = _6570; + uint16_t _6571 = (uint16_t)(54); + _curvea0[71] = _6571; + uint16_t _6572 = (uint16_t)(54); + _curvea0[72] = _6572; + uint16_t _6573 = (uint16_t)(55); + _curvea0[73] = _6573; + uint16_t _6574 = (uint16_t)(55); + _curvea0[74] = _6574; + uint16_t _6575 = (uint16_t)(56); + _curvea0[75] = _6575; + uint16_t _6576 = (uint16_t)(56); + _curvea0[76] = _6576; + uint16_t _6577 = (uint16_t)(57); + _curvea0[77] = _6577; + uint16_t _6578 = (uint16_t)(57); + _curvea0[78] = _6578; + uint16_t _6579 = (uint16_t)(58); + _curvea0[79] = _6579; + uint16_t _6580 = (uint16_t)(58); + _curvea0[80] = _6580; + uint16_t _6581 = (uint16_t)(58); + _curvea0[81] = _6581; + uint16_t _6582 = (uint16_t)(59); + _curvea0[82] = _6582; + uint16_t _6583 = (uint16_t)(59); + _curvea0[83] = _6583; + uint16_t _6584 = (uint16_t)(60); + _curvea0[84] = _6584; + uint16_t _6585 = (uint16_t)(60); + _curvea0[85] = _6585; + uint16_t _6586 = (uint16_t)(61); + _curvea0[86] = _6586; + uint16_t _6587 = (uint16_t)(61); + _curvea0[87] = _6587; + uint16_t _6588 = (uint16_t)(62); + _curvea0[88] = _6588; + uint16_t _6589 = (uint16_t)(62); + _curvea0[89] = _6589; + uint16_t _6590 = (uint16_t)(63); + _curvea0[90] = _6590; + uint16_t _6591 = (uint16_t)(63); + _curvea0[91] = _6591; + uint16_t _6592 = (uint16_t)(64); + _curvea0[92] = _6592; + uint16_t _6593 = (uint16_t)(64); + _curvea0[93] = _6593; + uint16_t _6594 = (uint16_t)(64); + _curvea0[94] = _6594; + uint16_t _6595 = (uint16_t)(65); + _curvea0[95] = _6595; + uint16_t _6596 = (uint16_t)(65); + _curvea0[96] = _6596; + uint16_t _6597 = (uint16_t)(66); + _curvea0[97] = _6597; + uint16_t _6598 = (uint16_t)(66); + _curvea0[98] = _6598; + uint16_t _6599 = (uint16_t)(67); + _curvea0[99] = _6599; + uint16_t _6600 = (uint16_t)(67); + _curvea0[100] = _6600; + uint16_t _6601 = (uint16_t)(68); + _curvea0[101] = _6601; + uint16_t _6602 = (uint16_t)(68); + _curvea0[102] = _6602; + uint16_t _6603 = (uint16_t)(68); + _curvea0[103] = _6603; + uint16_t _6604 = (uint16_t)(69); + _curvea0[104] = _6604; + uint16_t _6605 = (uint16_t)(69); + _curvea0[105] = _6605; + uint16_t _6606 = (uint16_t)(70); + _curvea0[106] = _6606; + uint16_t _6607 = (uint16_t)(70); + _curvea0[107] = _6607; + uint16_t _6608 = (uint16_t)(71); + _curvea0[108] = _6608; + uint16_t _6609 = (uint16_t)(71); + _curvea0[109] = _6609; + uint16_t _6610 = (uint16_t)(71); + _curvea0[110] = _6610; + uint16_t _6611 = (uint16_t)(72); + _curvea0[111] = _6611; + uint16_t _6612 = (uint16_t)(72); + _curvea0[112] = _6612; + uint16_t _6613 = (uint16_t)(73); + _curvea0[113] = _6613; + uint16_t _6614 = (uint16_t)(73); + _curvea0[114] = _6614; + uint16_t _6615 = (uint16_t)(74); + _curvea0[115] = _6615; + uint16_t _6616 = (uint16_t)(74); + _curvea0[116] = _6616; + uint16_t _6617 = (uint16_t)(74); + _curvea0[117] = _6617; + uint16_t _6618 = (uint16_t)(75); + _curvea0[118] = _6618; + uint16_t _6619 = (uint16_t)(75); + _curvea0[119] = _6619; + uint16_t _6620 = (uint16_t)(76); + _curvea0[120] = _6620; + uint16_t _6621 = (uint16_t)(76); + _curvea0[121] = _6621; + uint16_t _6622 = (uint16_t)(77); + _curvea0[122] = _6622; + uint16_t _6623 = (uint16_t)(77); + _curvea0[123] = _6623; + uint16_t _6624 = (uint16_t)(77); + _curvea0[124] = _6624; + uint16_t _6625 = (uint16_t)(78); + _curvea0[125] = _6625; + uint16_t _6626 = (uint16_t)(78); + _curvea0[126] = _6626; + uint16_t _6627 = (uint16_t)(79); + _curvea0[127] = _6627; + uint16_t _6628 = (uint16_t)(79); + _curvea0[128] = _6628; + uint16_t _6629 = (uint16_t)(79); + _curvea0[129] = _6629; + uint16_t _6630 = (uint16_t)(80); + _curvea0[130] = _6630; + uint16_t _6631 = (uint16_t)(80); + _curvea0[131] = _6631; + uint16_t _6632 = (uint16_t)(81); + _curvea0[132] = _6632; + uint16_t _6633 = (uint16_t)(81); + _curvea0[133] = _6633; + uint16_t _6634 = (uint16_t)(82); + _curvea0[134] = _6634; + uint16_t _6635 = (uint16_t)(82); + _curvea0[135] = _6635; + uint16_t _6636 = (uint16_t)(82); + _curvea0[136] = _6636; + uint16_t _6637 = (uint16_t)(83); + _curvea0[137] = _6637; + uint16_t _6638 = (uint16_t)(83); + _curvea0[138] = _6638; + uint16_t _6639 = (uint16_t)(84); + _curvea0[139] = _6639; + uint16_t _6640 = (uint16_t)(84); + _curvea0[140] = _6640; + uint16_t _6641 = (uint16_t)(84); + _curvea0[141] = _6641; + uint16_t _6642 = (uint16_t)(85); + _curvea0[142] = _6642; + uint16_t _6643 = (uint16_t)(85); + _curvea0[143] = _6643; + uint16_t _6644 = (uint16_t)(86); + _curvea0[144] = _6644; + uint16_t _6645 = (uint16_t)(86); + _curvea0[145] = _6645; + uint16_t _6646 = (uint16_t)(86); + _curvea0[146] = _6646; + uint16_t _6647 = (uint16_t)(87); + _curvea0[147] = _6647; + uint16_t _6648 = (uint16_t)(87); + _curvea0[148] = _6648; + uint16_t _6649 = (uint16_t)(88); + _curvea0[149] = _6649; + uint16_t _6650 = (uint16_t)(88); + _curvea0[150] = _6650; + uint16_t _6651 = (uint16_t)(88); + _curvea0[151] = _6651; + uint16_t _6652 = (uint16_t)(89); + _curvea0[152] = _6652; + uint16_t _6653 = (uint16_t)(89); + _curvea0[153] = _6653; + uint16_t _6654 = (uint16_t)(90); + _curvea0[154] = _6654; + uint16_t _6655 = (uint16_t)(90); + _curvea0[155] = _6655; + uint16_t _6656 = (uint16_t)(90); + _curvea0[156] = _6656; + uint16_t _6657 = (uint16_t)(91); + _curvea0[157] = _6657; + uint16_t _6658 = (uint16_t)(91); + _curvea0[158] = _6658; + uint16_t _6659 = (uint16_t)(92); + _curvea0[159] = _6659; + uint16_t _6660 = (uint16_t)(92); + _curvea0[160] = _6660; + uint16_t _6661 = (uint16_t)(92); + _curvea0[161] = _6661; + uint16_t _6662 = (uint16_t)(93); + _curvea0[162] = _6662; + uint16_t _6663 = (uint16_t)(93); + _curvea0[163] = _6663; + uint16_t _6664 = (uint16_t)(93); + _curvea0[164] = _6664; + uint16_t _6665 = (uint16_t)(94); + _curvea0[165] = _6665; + uint16_t _6666 = (uint16_t)(94); + _curvea0[166] = _6666; + uint16_t _6667 = (uint16_t)(95); + _curvea0[167] = _6667; + uint16_t _6668 = (uint16_t)(95); + _curvea0[168] = _6668; + uint16_t _6669 = (uint16_t)(95); + _curvea0[169] = _6669; + uint16_t _6670 = (uint16_t)(96); + _curvea0[170] = _6670; + uint16_t _6671 = (uint16_t)(96); + _curvea0[171] = _6671; + uint16_t _6672 = (uint16_t)(97); + _curvea0[172] = _6672; + uint16_t _6673 = (uint16_t)(97); + _curvea0[173] = _6673; + uint16_t _6674 = (uint16_t)(97); + _curvea0[174] = _6674; + uint16_t _6675 = (uint16_t)(98); + _curvea0[175] = _6675; + uint16_t _6676 = (uint16_t)(98); + _curvea0[176] = _6676; + uint16_t _6677 = (uint16_t)(99); + _curvea0[177] = _6677; + uint16_t _6678 = (uint16_t)(99); + _curvea0[178] = _6678; + uint16_t _6679 = (uint16_t)(99); + _curvea0[179] = _6679; + uint16_t _6680 = (uint16_t)(100); + _curvea0[180] = _6680; + uint16_t _6681 = (uint16_t)(100); + _curvea0[181] = _6681; + uint16_t _6682 = (uint16_t)(100); + _curvea0[182] = _6682; + uint16_t _6683 = (uint16_t)(101); + _curvea0[183] = _6683; + uint16_t _6684 = (uint16_t)(101); + _curvea0[184] = _6684; + uint16_t _6685 = (uint16_t)(102); + _curvea0[185] = _6685; + uint16_t _6686 = (uint16_t)(102); + _curvea0[186] = _6686; + uint16_t _6687 = (uint16_t)(102); + _curvea0[187] = _6687; + uint16_t _6688 = (uint16_t)(103); + _curvea0[188] = _6688; + uint16_t _6689 = (uint16_t)(103); + _curvea0[189] = _6689; + uint16_t _6690 = (uint16_t)(103); + _curvea0[190] = _6690; + uint16_t _6691 = (uint16_t)(104); + _curvea0[191] = _6691; + uint16_t _6692 = (uint16_t)(104); + _curvea0[192] = _6692; + uint16_t _6693 = (uint16_t)(105); + _curvea0[193] = _6693; + uint16_t _6694 = (uint16_t)(105); + _curvea0[194] = _6694; + uint16_t _6695 = (uint16_t)(105); + _curvea0[195] = _6695; + uint16_t _6696 = (uint16_t)(106); + _curvea0[196] = _6696; + uint16_t _6697 = (uint16_t)(106); + _curvea0[197] = _6697; + uint16_t _6698 = (uint16_t)(106); + _curvea0[198] = _6698; + uint16_t _6699 = (uint16_t)(107); + _curvea0[199] = _6699; + uint16_t _6700 = (uint16_t)(107); + _curvea0[200] = _6700; + uint16_t _6701 = (uint16_t)(108); + _curvea0[201] = _6701; + uint16_t _6702 = (uint16_t)(108); + _curvea0[202] = _6702; + uint16_t _6703 = (uint16_t)(108); + _curvea0[203] = _6703; + uint16_t _6704 = (uint16_t)(109); + _curvea0[204] = _6704; + uint16_t _6705 = (uint16_t)(109); + _curvea0[205] = _6705; + uint16_t _6706 = (uint16_t)(109); + _curvea0[206] = _6706; + uint16_t _6707 = (uint16_t)(110); + _curvea0[207] = _6707; + uint16_t _6708 = (uint16_t)(110); + _curvea0[208] = _6708; + uint16_t _6709 = (uint16_t)(111); + _curvea0[209] = _6709; + uint16_t _6710 = (uint16_t)(111); + _curvea0[210] = _6710; + uint16_t _6711 = (uint16_t)(111); + _curvea0[211] = _6711; + uint16_t _6712 = (uint16_t)(112); + _curvea0[212] = _6712; + uint16_t _6713 = (uint16_t)(112); + _curvea0[213] = _6713; + uint16_t _6714 = (uint16_t)(112); + _curvea0[214] = _6714; + uint16_t _6715 = (uint16_t)(113); + _curvea0[215] = _6715; + uint16_t _6716 = (uint16_t)(113); + _curvea0[216] = _6716; + uint16_t _6717 = (uint16_t)(113); + _curvea0[217] = _6717; + uint16_t _6718 = (uint16_t)(114); + _curvea0[218] = _6718; + uint16_t _6719 = (uint16_t)(114); + _curvea0[219] = _6719; + uint16_t _6720 = (uint16_t)(115); + _curvea0[220] = _6720; + uint16_t _6721 = (uint16_t)(115); + _curvea0[221] = _6721; + uint16_t _6722 = (uint16_t)(115); + _curvea0[222] = _6722; + uint16_t _6723 = (uint16_t)(116); + _curvea0[223] = _6723; + uint16_t _6724 = (uint16_t)(116); + _curvea0[224] = _6724; + uint16_t _6725 = (uint16_t)(116); + _curvea0[225] = _6725; + uint16_t _6726 = (uint16_t)(117); + _curvea0[226] = _6726; + uint16_t _6727 = (uint16_t)(117); + _curvea0[227] = _6727; + uint16_t _6728 = (uint16_t)(117); + _curvea0[228] = _6728; + uint16_t _6729 = (uint16_t)(118); + _curvea0[229] = _6729; + uint16_t _6730 = (uint16_t)(118); + _curvea0[230] = _6730; + uint16_t _6731 = (uint16_t)(119); + _curvea0[231] = _6731; + uint16_t _6732 = (uint16_t)(119); + _curvea0[232] = _6732; + uint16_t _6733 = (uint16_t)(119); + _curvea0[233] = _6733; + uint16_t _6734 = (uint16_t)(120); + _curvea0[234] = _6734; + uint16_t _6735 = (uint16_t)(120); + _curvea0[235] = _6735; + uint16_t _6736 = (uint16_t)(120); + _curvea0[236] = _6736; + uint16_t _6737 = (uint16_t)(121); + _curvea0[237] = _6737; + uint16_t _6738 = (uint16_t)(121); + _curvea0[238] = _6738; + uint16_t _6739 = (uint16_t)(121); + _curvea0[239] = _6739; + uint16_t _6740 = (uint16_t)(122); + _curvea0[240] = _6740; + uint16_t _6741 = (uint16_t)(122); + _curvea0[241] = _6741; + uint16_t _6742 = (uint16_t)(123); + _curvea0[242] = _6742; + uint16_t _6743 = (uint16_t)(123); + _curvea0[243] = _6743; + uint16_t _6744 = (uint16_t)(123); + _curvea0[244] = _6744; + uint16_t _6745 = (uint16_t)(124); + _curvea0[245] = _6745; + uint16_t _6746 = (uint16_t)(124); + _curvea0[246] = _6746; + uint16_t _6747 = (uint16_t)(124); + _curvea0[247] = _6747; + uint16_t _6748 = (uint16_t)(125); + _curvea0[248] = _6748; + uint16_t _6749 = (uint16_t)(125); + _curvea0[249] = _6749; + uint16_t _6750 = (uint16_t)(125); + _curvea0[250] = _6750; + uint16_t _6751 = (uint16_t)(126); + _curvea0[251] = _6751; + uint16_t _6752 = (uint16_t)(126); + _curvea0[252] = _6752; + uint16_t _6753 = (uint16_t)(126); + _curvea0[253] = _6753; + uint16_t _6754 = (uint16_t)(127); + _curvea0[254] = _6754; + uint16_t _6755 = (uint16_t)(127); + _curvea0[255] = _6755; + uint16_t _6756 = (uint16_t)(128); + _curvea0[256] = _6756; + uint16_t _6757 = (uint16_t)(128); + _curvea0[257] = _6757; + uint16_t _6758 = (uint16_t)(128); + _curvea0[258] = _6758; + uint16_t _6759 = (uint16_t)(129); + _curvea0[259] = _6759; + uint16_t _6760 = (uint16_t)(129); + _curvea0[260] = _6760; + uint16_t _6761 = (uint16_t)(129); + _curvea0[261] = _6761; + uint16_t _6762 = (uint16_t)(130); + _curvea0[262] = _6762; + uint16_t _6763 = (uint16_t)(130); + _curvea0[263] = _6763; + uint16_t _6764 = (uint16_t)(130); + _curvea0[264] = _6764; + uint16_t _6765 = (uint16_t)(131); + _curvea0[265] = _6765; + uint16_t _6766 = (uint16_t)(131); + _curvea0[266] = _6766; + uint16_t _6767 = (uint16_t)(131); + _curvea0[267] = _6767; + uint16_t _6768 = (uint16_t)(132); + _curvea0[268] = _6768; + uint16_t _6769 = (uint16_t)(132); + _curvea0[269] = _6769; + uint16_t _6770 = (uint16_t)(132); + _curvea0[270] = _6770; + uint16_t _6771 = (uint16_t)(133); + _curvea0[271] = _6771; + uint16_t _6772 = (uint16_t)(133); + _curvea0[272] = _6772; + uint16_t _6773 = (uint16_t)(133); + _curvea0[273] = _6773; + uint16_t _6774 = (uint16_t)(134); + _curvea0[274] = _6774; + uint16_t _6775 = (uint16_t)(134); + _curvea0[275] = _6775; + uint16_t _6776 = (uint16_t)(134); + _curvea0[276] = _6776; + uint16_t _6777 = (uint16_t)(135); + _curvea0[277] = _6777; + uint16_t _6778 = (uint16_t)(135); + _curvea0[278] = _6778; + uint16_t _6779 = (uint16_t)(135); + _curvea0[279] = _6779; + uint16_t _6780 = (uint16_t)(136); + _curvea0[280] = _6780; + uint16_t _6781 = (uint16_t)(136); + _curvea0[281] = _6781; + uint16_t _6782 = (uint16_t)(136); + _curvea0[282] = _6782; + uint16_t _6783 = (uint16_t)(137); + _curvea0[283] = _6783; + uint16_t _6784 = (uint16_t)(137); + _curvea0[284] = _6784; + uint16_t _6785 = (uint16_t)(137); + _curvea0[285] = _6785; + uint16_t _6786 = (uint16_t)(138); + _curvea0[286] = _6786; + uint16_t _6787 = (uint16_t)(138); + _curvea0[287] = _6787; + uint16_t _6788 = (uint16_t)(138); + _curvea0[288] = _6788; + uint16_t _6789 = (uint16_t)(139); + _curvea0[289] = _6789; + uint16_t _6790 = (uint16_t)(139); + _curvea0[290] = _6790; + uint16_t _6791 = (uint16_t)(139); + _curvea0[291] = _6791; + uint16_t _6792 = (uint16_t)(140); + _curvea0[292] = _6792; + uint16_t _6793 = (uint16_t)(140); + _curvea0[293] = _6793; + uint16_t _6794 = (uint16_t)(140); + _curvea0[294] = _6794; + uint16_t _6795 = (uint16_t)(141); + _curvea0[295] = _6795; + uint16_t _6796 = (uint16_t)(141); + _curvea0[296] = _6796; + uint16_t _6797 = (uint16_t)(141); + _curvea0[297] = _6797; + uint16_t _6798 = (uint16_t)(141); + _curvea0[298] = _6798; + uint16_t _6799 = (uint16_t)(142); + _curvea0[299] = _6799; + uint16_t _6800 = (uint16_t)(142); + _curvea0[300] = _6800; + uint16_t _6801 = (uint16_t)(142); + _curvea0[301] = _6801; + uint16_t _6802 = (uint16_t)(143); + _curvea0[302] = _6802; + uint16_t _6803 = (uint16_t)(143); + _curvea0[303] = _6803; + uint16_t _6804 = (uint16_t)(143); + _curvea0[304] = _6804; + uint16_t _6805 = (uint16_t)(144); + _curvea0[305] = _6805; + uint16_t _6806 = (uint16_t)(144); + _curvea0[306] = _6806; + uint16_t _6807 = (uint16_t)(144); + _curvea0[307] = _6807; + uint16_t _6808 = (uint16_t)(145); + _curvea0[308] = _6808; + uint16_t _6809 = (uint16_t)(145); + _curvea0[309] = _6809; + uint16_t _6810 = (uint16_t)(145); + _curvea0[310] = _6810; + uint16_t _6811 = (uint16_t)(145); + _curvea0[311] = _6811; + uint16_t _6812 = (uint16_t)(146); + _curvea0[312] = _6812; + uint16_t _6813 = (uint16_t)(146); + _curvea0[313] = _6813; + uint16_t _6814 = (uint16_t)(146); + _curvea0[314] = _6814; + uint16_t _6815 = (uint16_t)(147); + _curvea0[315] = _6815; + uint16_t _6816 = (uint16_t)(147); + _curvea0[316] = _6816; + uint16_t _6817 = (uint16_t)(147); + _curvea0[317] = _6817; + uint16_t _6818 = (uint16_t)(148); + _curvea0[318] = _6818; + uint16_t _6819 = (uint16_t)(148); + _curvea0[319] = _6819; + uint16_t _6820 = (uint16_t)(148); + _curvea0[320] = _6820; + uint16_t _6821 = (uint16_t)(148); + _curvea0[321] = _6821; + uint16_t _6822 = (uint16_t)(149); + _curvea0[322] = _6822; + uint16_t _6823 = (uint16_t)(149); + _curvea0[323] = _6823; + uint16_t _6824 = (uint16_t)(149); + _curvea0[324] = _6824; + uint16_t _6825 = (uint16_t)(150); + _curvea0[325] = _6825; + uint16_t _6826 = (uint16_t)(150); + _curvea0[326] = _6826; + uint16_t _6827 = (uint16_t)(150); + _curvea0[327] = _6827; + uint16_t _6828 = (uint16_t)(150); + _curvea0[328] = _6828; + uint16_t _6829 = (uint16_t)(151); + _curvea0[329] = _6829; + uint16_t _6830 = (uint16_t)(151); + _curvea0[330] = _6830; + uint16_t _6831 = (uint16_t)(151); + _curvea0[331] = _6831; + uint16_t _6832 = (uint16_t)(152); + _curvea0[332] = _6832; + uint16_t _6833 = (uint16_t)(152); + _curvea0[333] = _6833; + uint16_t _6834 = (uint16_t)(152); + _curvea0[334] = _6834; + uint16_t _6835 = (uint16_t)(152); + _curvea0[335] = _6835; + uint16_t _6836 = (uint16_t)(153); + _curvea0[336] = _6836; + uint16_t _6837 = (uint16_t)(153); + _curvea0[337] = _6837; + uint16_t _6838 = (uint16_t)(153); + _curvea0[338] = _6838; + uint16_t _6839 = (uint16_t)(154); + _curvea0[339] = _6839; + uint16_t _6840 = (uint16_t)(154); + _curvea0[340] = _6840; + uint16_t _6841 = (uint16_t)(154); + _curvea0[341] = _6841; + uint16_t _6842 = (uint16_t)(154); + _curvea0[342] = _6842; + uint16_t _6843 = (uint16_t)(155); + _curvea0[343] = _6843; + uint16_t _6844 = (uint16_t)(155); + _curvea0[344] = _6844; + uint16_t _6845 = (uint16_t)(155); + _curvea0[345] = _6845; + uint16_t _6846 = (uint16_t)(156); + _curvea0[346] = _6846; + uint16_t _6847 = (uint16_t)(156); + _curvea0[347] = _6847; + uint16_t _6848 = (uint16_t)(156); + _curvea0[348] = _6848; + uint16_t _6849 = (uint16_t)(156); + _curvea0[349] = _6849; + uint16_t _6850 = (uint16_t)(157); + _curvea0[350] = _6850; + uint16_t _6851 = (uint16_t)(157); + _curvea0[351] = _6851; + uint16_t _6852 = (uint16_t)(157); + _curvea0[352] = _6852; + uint16_t _6853 = (uint16_t)(157); + _curvea0[353] = _6853; + uint16_t _6854 = (uint16_t)(158); + _curvea0[354] = _6854; + uint16_t _6855 = (uint16_t)(158); + _curvea0[355] = _6855; + uint16_t _6856 = (uint16_t)(158); + _curvea0[356] = _6856; + uint16_t _6857 = (uint16_t)(159); + _curvea0[357] = _6857; + uint16_t _6858 = (uint16_t)(159); + _curvea0[358] = _6858; + uint16_t _6859 = (uint16_t)(159); + _curvea0[359] = _6859; + uint16_t _6860 = (uint16_t)(159); + _curvea0[360] = _6860; + uint16_t _6861 = (uint16_t)(160); + _curvea0[361] = _6861; + uint16_t _6862 = (uint16_t)(160); + _curvea0[362] = _6862; + uint16_t _6863 = (uint16_t)(160); + _curvea0[363] = _6863; + uint16_t _6864 = (uint16_t)(160); + _curvea0[364] = _6864; + uint16_t _6865 = (uint16_t)(161); + _curvea0[365] = _6865; + uint16_t _6866 = (uint16_t)(161); + _curvea0[366] = _6866; + uint16_t _6867 = (uint16_t)(161); + _curvea0[367] = _6867; + uint16_t _6868 = (uint16_t)(161); + _curvea0[368] = _6868; + uint16_t _6869 = (uint16_t)(162); + _curvea0[369] = _6869; + uint16_t _6870 = (uint16_t)(162); + _curvea0[370] = _6870; + uint16_t _6871 = (uint16_t)(162); + _curvea0[371] = _6871; + uint16_t _6872 = (uint16_t)(162); + _curvea0[372] = _6872; + uint16_t _6873 = (uint16_t)(163); + _curvea0[373] = _6873; + uint16_t _6874 = (uint16_t)(163); + _curvea0[374] = _6874; + uint16_t _6875 = (uint16_t)(163); + _curvea0[375] = _6875; + uint16_t _6876 = (uint16_t)(163); + _curvea0[376] = _6876; + uint16_t _6877 = (uint16_t)(164); + _curvea0[377] = _6877; + uint16_t _6878 = (uint16_t)(164); + _curvea0[378] = _6878; + uint16_t _6879 = (uint16_t)(164); + _curvea0[379] = _6879; + uint16_t _6880 = (uint16_t)(164); + _curvea0[380] = _6880; + uint16_t _6881 = (uint16_t)(165); + _curvea0[381] = _6881; + uint16_t _6882 = (uint16_t)(165); + _curvea0[382] = _6882; + uint16_t _6883 = (uint16_t)(165); + _curvea0[383] = _6883; + uint16_t _6884 = (uint16_t)(166); + _curvea0[384] = _6884; + uint16_t _6885 = (uint16_t)(166); + _curvea0[385] = _6885; + uint16_t _6886 = (uint16_t)(166); + _curvea0[386] = _6886; + uint16_t _6887 = (uint16_t)(166); + _curvea0[387] = _6887; + uint16_t _6888 = (uint16_t)(167); + _curvea0[388] = _6888; + uint16_t _6889 = (uint16_t)(167); + _curvea0[389] = _6889; + uint16_t _6890 = (uint16_t)(167); + _curvea0[390] = _6890; + uint16_t _6891 = (uint16_t)(167); + _curvea0[391] = _6891; + uint16_t _6892 = (uint16_t)(167); + _curvea0[392] = _6892; + uint16_t _6893 = (uint16_t)(168); + _curvea0[393] = _6893; + uint16_t _6894 = (uint16_t)(168); + _curvea0[394] = _6894; + uint16_t _6895 = (uint16_t)(168); + _curvea0[395] = _6895; + uint16_t _6896 = (uint16_t)(168); + _curvea0[396] = _6896; + uint16_t _6897 = (uint16_t)(169); + _curvea0[397] = _6897; + uint16_t _6898 = (uint16_t)(169); + _curvea0[398] = _6898; + uint16_t _6899 = (uint16_t)(169); + _curvea0[399] = _6899; + uint16_t _6900 = (uint16_t)(169); + _curvea0[400] = _6900; + uint16_t _6901 = (uint16_t)(170); + _curvea0[401] = _6901; + uint16_t _6902 = (uint16_t)(170); + _curvea0[402] = _6902; + uint16_t _6903 = (uint16_t)(170); + _curvea0[403] = _6903; + uint16_t _6904 = (uint16_t)(170); + _curvea0[404] = _6904; + uint16_t _6905 = (uint16_t)(171); + _curvea0[405] = _6905; + uint16_t _6906 = (uint16_t)(171); + _curvea0[406] = _6906; + uint16_t _6907 = (uint16_t)(171); + _curvea0[407] = _6907; + uint16_t _6908 = (uint16_t)(171); + _curvea0[408] = _6908; + uint16_t _6909 = (uint16_t)(172); + _curvea0[409] = _6909; + uint16_t _6910 = (uint16_t)(172); + _curvea0[410] = _6910; + uint16_t _6911 = (uint16_t)(172); + _curvea0[411] = _6911; + uint16_t _6912 = (uint16_t)(172); + _curvea0[412] = _6912; + uint16_t _6913 = (uint16_t)(173); + _curvea0[413] = _6913; + uint16_t _6914 = (uint16_t)(173); + _curvea0[414] = _6914; + uint16_t _6915 = (uint16_t)(173); + _curvea0[415] = _6915; + uint16_t _6916 = (uint16_t)(173); + _curvea0[416] = _6916; + uint16_t _6917 = (uint16_t)(173); + _curvea0[417] = _6917; + uint16_t _6918 = (uint16_t)(174); + _curvea0[418] = _6918; + uint16_t _6919 = (uint16_t)(174); + _curvea0[419] = _6919; + uint16_t _6920 = (uint16_t)(174); + _curvea0[420] = _6920; + uint16_t _6921 = (uint16_t)(174); + _curvea0[421] = _6921; + uint16_t _6922 = (uint16_t)(175); + _curvea0[422] = _6922; + uint16_t _6923 = (uint16_t)(175); + _curvea0[423] = _6923; + uint16_t _6924 = (uint16_t)(175); + _curvea0[424] = _6924; + uint16_t _6925 = (uint16_t)(175); + _curvea0[425] = _6925; + uint16_t _6926 = (uint16_t)(176); + _curvea0[426] = _6926; + uint16_t _6927 = (uint16_t)(176); + _curvea0[427] = _6927; + uint16_t _6928 = (uint16_t)(176); + _curvea0[428] = _6928; + uint16_t _6929 = (uint16_t)(176); + _curvea0[429] = _6929; + uint16_t _6930 = (uint16_t)(176); + _curvea0[430] = _6930; + uint16_t _6931 = (uint16_t)(177); + _curvea0[431] = _6931; + uint16_t _6932 = (uint16_t)(177); + _curvea0[432] = _6932; + uint16_t _6933 = (uint16_t)(177); + _curvea0[433] = _6933; + uint16_t _6934 = (uint16_t)(177); + _curvea0[434] = _6934; + uint16_t _6935 = (uint16_t)(178); + _curvea0[435] = _6935; + uint16_t _6936 = (uint16_t)(178); + _curvea0[436] = _6936; + uint16_t _6937 = (uint16_t)(178); + _curvea0[437] = _6937; + uint16_t _6938 = (uint16_t)(178); + _curvea0[438] = _6938; + uint16_t _6939 = (uint16_t)(178); + _curvea0[439] = _6939; + uint16_t _6940 = (uint16_t)(179); + _curvea0[440] = _6940; + uint16_t _6941 = (uint16_t)(179); + _curvea0[441] = _6941; + uint16_t _6942 = (uint16_t)(179); + _curvea0[442] = _6942; + uint16_t _6943 = (uint16_t)(179); + _curvea0[443] = _6943; + uint16_t _6944 = (uint16_t)(180); + _curvea0[444] = _6944; + uint16_t _6945 = (uint16_t)(180); + _curvea0[445] = _6945; + uint16_t _6946 = (uint16_t)(180); + _curvea0[446] = _6946; + uint16_t _6947 = (uint16_t)(180); + _curvea0[447] = _6947; + uint16_t _6948 = (uint16_t)(180); + _curvea0[448] = _6948; + uint16_t _6949 = (uint16_t)(181); + _curvea0[449] = _6949; + uint16_t _6950 = (uint16_t)(181); + _curvea0[450] = _6950; + uint16_t _6951 = (uint16_t)(181); + _curvea0[451] = _6951; + uint16_t _6952 = (uint16_t)(181); + _curvea0[452] = _6952; + uint16_t _6953 = (uint16_t)(181); + _curvea0[453] = _6953; + uint16_t _6954 = (uint16_t)(182); + _curvea0[454] = _6954; + uint16_t _6955 = (uint16_t)(182); + _curvea0[455] = _6955; + uint16_t _6956 = (uint16_t)(182); + _curvea0[456] = _6956; + uint16_t _6957 = (uint16_t)(182); + _curvea0[457] = _6957; + uint16_t _6958 = (uint16_t)(183); + _curvea0[458] = _6958; + uint16_t _6959 = (uint16_t)(183); + _curvea0[459] = _6959; + uint16_t _6960 = (uint16_t)(183); + _curvea0[460] = _6960; + uint16_t _6961 = (uint16_t)(183); + _curvea0[461] = _6961; + uint16_t _6962 = (uint16_t)(183); + _curvea0[462] = _6962; + uint16_t _6963 = (uint16_t)(184); + _curvea0[463] = _6963; + uint16_t _6964 = (uint16_t)(184); + _curvea0[464] = _6964; + uint16_t _6965 = (uint16_t)(184); + _curvea0[465] = _6965; + uint16_t _6966 = (uint16_t)(184); + _curvea0[466] = _6966; + uint16_t _6967 = (uint16_t)(184); + _curvea0[467] = _6967; + uint16_t _6968 = (uint16_t)(185); + _curvea0[468] = _6968; + uint16_t _6969 = (uint16_t)(185); + _curvea0[469] = _6969; + uint16_t _6970 = (uint16_t)(185); + _curvea0[470] = _6970; + uint16_t _6971 = (uint16_t)(185); + _curvea0[471] = _6971; + uint16_t _6972 = (uint16_t)(185); + _curvea0[472] = _6972; + uint16_t _6973 = (uint16_t)(186); + _curvea0[473] = _6973; + uint16_t _6974 = (uint16_t)(186); + _curvea0[474] = _6974; + uint16_t _6975 = (uint16_t)(186); + _curvea0[475] = _6975; + uint16_t _6976 = (uint16_t)(186); + _curvea0[476] = _6976; + uint16_t _6977 = (uint16_t)(187); + _curvea0[477] = _6977; + uint16_t _6978 = (uint16_t)(187); + _curvea0[478] = _6978; + uint16_t _6979 = (uint16_t)(187); + _curvea0[479] = _6979; + uint16_t _6980 = (uint16_t)(187); + _curvea0[480] = _6980; + uint16_t _6981 = (uint16_t)(187); + _curvea0[481] = _6981; + uint16_t _6982 = (uint16_t)(188); + _curvea0[482] = _6982; + uint16_t _6983 = (uint16_t)(188); + _curvea0[483] = _6983; + uint16_t _6984 = (uint16_t)(188); + _curvea0[484] = _6984; + uint16_t _6985 = (uint16_t)(188); + _curvea0[485] = _6985; + uint16_t _6986 = (uint16_t)(188); + _curvea0[486] = _6986; + uint16_t _6987 = (uint16_t)(189); + _curvea0[487] = _6987; + uint16_t _6988 = (uint16_t)(189); + _curvea0[488] = _6988; + uint16_t _6989 = (uint16_t)(189); + _curvea0[489] = _6989; + uint16_t _6990 = (uint16_t)(189); + _curvea0[490] = _6990; + uint16_t _6991 = (uint16_t)(189); + _curvea0[491] = _6991; + uint16_t _6992 = (uint16_t)(190); + _curvea0[492] = _6992; + uint16_t _6993 = (uint16_t)(190); + _curvea0[493] = _6993; + uint16_t _6994 = (uint16_t)(190); + _curvea0[494] = _6994; + uint16_t _6995 = (uint16_t)(190); + _curvea0[495] = _6995; + uint16_t _6996 = (uint16_t)(190); + _curvea0[496] = _6996; + uint16_t _6997 = (uint16_t)(190); + _curvea0[497] = _6997; + uint16_t _6998 = (uint16_t)(191); + _curvea0[498] = _6998; + uint16_t _6999 = (uint16_t)(191); + _curvea0[499] = _6999; + uint16_t _7000 = (uint16_t)(191); + _curvea0[500] = _7000; + uint16_t _7001 = (uint16_t)(191); + _curvea0[501] = _7001; + uint16_t _7002 = (uint16_t)(191); + _curvea0[502] = _7002; + uint16_t _7003 = (uint16_t)(192); + _curvea0[503] = _7003; + uint16_t _7004 = (uint16_t)(192); + _curvea0[504] = _7004; + uint16_t _7005 = (uint16_t)(192); + _curvea0[505] = _7005; + uint16_t _7006 = (uint16_t)(192); + _curvea0[506] = _7006; + uint16_t _7007 = (uint16_t)(192); + _curvea0[507] = _7007; + uint16_t _7008 = (uint16_t)(193); + _curvea0[508] = _7008; + uint16_t _7009 = (uint16_t)(193); + _curvea0[509] = _7009; + uint16_t _7010 = (uint16_t)(193); + _curvea0[510] = _7010; + uint16_t _7011 = (uint16_t)(193); + _curvea0[511] = _7011; + uint16_t _7012 = (uint16_t)(193); + _curvea0[512] = _7012; + uint16_t _7013 = (uint16_t)(194); + _curvea0[513] = _7013; + uint16_t _7014 = (uint16_t)(194); + _curvea0[514] = _7014; + uint16_t _7015 = (uint16_t)(194); + _curvea0[515] = _7015; + uint16_t _7016 = (uint16_t)(194); + _curvea0[516] = _7016; + uint16_t _7017 = (uint16_t)(194); + _curvea0[517] = _7017; + uint16_t _7018 = (uint16_t)(195); + _curvea0[518] = _7018; + uint16_t _7019 = (uint16_t)(195); + _curvea0[519] = _7019; + uint16_t _7020 = (uint16_t)(195); + _curvea0[520] = _7020; + uint16_t _7021 = (uint16_t)(195); + _curvea0[521] = _7021; + uint16_t _7022 = (uint16_t)(195); + _curvea0[522] = _7022; + uint16_t _7023 = (uint16_t)(195); + _curvea0[523] = _7023; + uint16_t _7024 = (uint16_t)(196); + _curvea0[524] = _7024; + uint16_t _7025 = (uint16_t)(196); + _curvea0[525] = _7025; + uint16_t _7026 = (uint16_t)(196); + _curvea0[526] = _7026; + uint16_t _7027 = (uint16_t)(196); + _curvea0[527] = _7027; + uint16_t _7028 = (uint16_t)(196); + _curvea0[528] = _7028; + uint16_t _7029 = (uint16_t)(197); + _curvea0[529] = _7029; + uint16_t _7030 = (uint16_t)(197); + _curvea0[530] = _7030; + uint16_t _7031 = (uint16_t)(197); + _curvea0[531] = _7031; + uint16_t _7032 = (uint16_t)(197); + _curvea0[532] = _7032; + uint16_t _7033 = (uint16_t)(197); + _curvea0[533] = _7033; + uint16_t _7034 = (uint16_t)(197); + _curvea0[534] = _7034; + uint16_t _7035 = (uint16_t)(198); + _curvea0[535] = _7035; + uint16_t _7036 = (uint16_t)(198); + _curvea0[536] = _7036; + uint16_t _7037 = (uint16_t)(198); + _curvea0[537] = _7037; + uint16_t _7038 = (uint16_t)(198); + _curvea0[538] = _7038; + uint16_t _7039 = (uint16_t)(198); + _curvea0[539] = _7039; + uint16_t _7040 = (uint16_t)(199); + _curvea0[540] = _7040; + uint16_t _7041 = (uint16_t)(199); + _curvea0[541] = _7041; + uint16_t _7042 = (uint16_t)(199); + _curvea0[542] = _7042; + uint16_t _7043 = (uint16_t)(199); + _curvea0[543] = _7043; + uint16_t _7044 = (uint16_t)(199); + _curvea0[544] = _7044; + uint16_t _7045 = (uint16_t)(199); + _curvea0[545] = _7045; + uint16_t _7046 = (uint16_t)(200); + _curvea0[546] = _7046; + uint16_t _7047 = (uint16_t)(200); + _curvea0[547] = _7047; + uint16_t _7048 = (uint16_t)(200); + _curvea0[548] = _7048; + uint16_t _7049 = (uint16_t)(200); + _curvea0[549] = _7049; + uint16_t _7050 = (uint16_t)(200); + _curvea0[550] = _7050; + uint16_t _7051 = (uint16_t)(200); + _curvea0[551] = _7051; + uint16_t _7052 = (uint16_t)(201); + _curvea0[552] = _7052; + uint16_t _7053 = (uint16_t)(201); + _curvea0[553] = _7053; + uint16_t _7054 = (uint16_t)(201); + _curvea0[554] = _7054; + uint16_t _7055 = (uint16_t)(201); + _curvea0[555] = _7055; + uint16_t _7056 = (uint16_t)(201); + _curvea0[556] = _7056; + uint16_t _7057 = (uint16_t)(202); + _curvea0[557] = _7057; + uint16_t _7058 = (uint16_t)(202); + _curvea0[558] = _7058; + uint16_t _7059 = (uint16_t)(202); + _curvea0[559] = _7059; + uint16_t _7060 = (uint16_t)(202); + _curvea0[560] = _7060; + uint16_t _7061 = (uint16_t)(202); + _curvea0[561] = _7061; + uint16_t _7062 = (uint16_t)(202); + _curvea0[562] = _7062; + uint16_t _7063 = (uint16_t)(203); + _curvea0[563] = _7063; + uint16_t _7064 = (uint16_t)(203); + _curvea0[564] = _7064; + uint16_t _7065 = (uint16_t)(203); + _curvea0[565] = _7065; + uint16_t _7066 = (uint16_t)(203); + _curvea0[566] = _7066; + uint16_t _7067 = (uint16_t)(203); + _curvea0[567] = _7067; + uint16_t _7068 = (uint16_t)(203); + _curvea0[568] = _7068; + uint16_t _7069 = (uint16_t)(204); + _curvea0[569] = _7069; + uint16_t _7070 = (uint16_t)(204); + _curvea0[570] = _7070; + uint16_t _7071 = (uint16_t)(204); + _curvea0[571] = _7071; + uint16_t _7072 = (uint16_t)(204); + _curvea0[572] = _7072; + uint16_t _7073 = (uint16_t)(204); + _curvea0[573] = _7073; + uint16_t _7074 = (uint16_t)(204); + _curvea0[574] = _7074; + uint16_t _7075 = (uint16_t)(205); + _curvea0[575] = _7075; + uint16_t _7076 = (uint16_t)(205); + _curvea0[576] = _7076; + uint16_t _7077 = (uint16_t)(205); + _curvea0[577] = _7077; + uint16_t _7078 = (uint16_t)(205); + _curvea0[578] = _7078; + uint16_t _7079 = (uint16_t)(205); + _curvea0[579] = _7079; + uint16_t _7080 = (uint16_t)(205); + _curvea0[580] = _7080; + uint16_t _7081 = (uint16_t)(206); + _curvea0[581] = _7081; + uint16_t _7082 = (uint16_t)(206); + _curvea0[582] = _7082; + uint16_t _7083 = (uint16_t)(206); + _curvea0[583] = _7083; + uint16_t _7084 = (uint16_t)(206); + _curvea0[584] = _7084; + uint16_t _7085 = (uint16_t)(206); + _curvea0[585] = _7085; + uint16_t _7086 = (uint16_t)(206); + _curvea0[586] = _7086; + uint16_t _7087 = (uint16_t)(207); + _curvea0[587] = _7087; + uint16_t _7088 = (uint16_t)(207); + _curvea0[588] = _7088; + uint16_t _7089 = (uint16_t)(207); + _curvea0[589] = _7089; + uint16_t _7090 = (uint16_t)(207); + _curvea0[590] = _7090; + uint16_t _7091 = (uint16_t)(207); + _curvea0[591] = _7091; + uint16_t _7092 = (uint16_t)(207); + _curvea0[592] = _7092; + uint16_t _7093 = (uint16_t)(208); + _curvea0[593] = _7093; + uint16_t _7094 = (uint16_t)(208); + _curvea0[594] = _7094; + uint16_t _7095 = (uint16_t)(208); + _curvea0[595] = _7095; + uint16_t _7096 = (uint16_t)(208); + _curvea0[596] = _7096; + uint16_t _7097 = (uint16_t)(208); + _curvea0[597] = _7097; + uint16_t _7098 = (uint16_t)(208); + _curvea0[598] = _7098; + uint16_t _7099 = (uint16_t)(209); + _curvea0[599] = _7099; + uint16_t _7100 = (uint16_t)(209); + _curvea0[600] = _7100; + uint16_t _7101 = (uint16_t)(209); + _curvea0[601] = _7101; + uint16_t _7102 = (uint16_t)(209); + _curvea0[602] = _7102; + uint16_t _7103 = (uint16_t)(209); + _curvea0[603] = _7103; + uint16_t _7104 = (uint16_t)(209); + _curvea0[604] = _7104; + uint16_t _7105 = (uint16_t)(209); + _curvea0[605] = _7105; + uint16_t _7106 = (uint16_t)(210); + _curvea0[606] = _7106; + uint16_t _7107 = (uint16_t)(210); + _curvea0[607] = _7107; + uint16_t _7108 = (uint16_t)(210); + _curvea0[608] = _7108; + uint16_t _7109 = (uint16_t)(210); + _curvea0[609] = _7109; + uint16_t _7110 = (uint16_t)(210); + _curvea0[610] = _7110; + uint16_t _7111 = (uint16_t)(210); + _curvea0[611] = _7111; + uint16_t _7112 = (uint16_t)(211); + _curvea0[612] = _7112; + uint16_t _7113 = (uint16_t)(211); + _curvea0[613] = _7113; + uint16_t _7114 = (uint16_t)(211); + _curvea0[614] = _7114; + uint16_t _7115 = (uint16_t)(211); + _curvea0[615] = _7115; + uint16_t _7116 = (uint16_t)(211); + _curvea0[616] = _7116; + uint16_t _7117 = (uint16_t)(211); + _curvea0[617] = _7117; + uint16_t _7118 = (uint16_t)(211); + _curvea0[618] = _7118; + uint16_t _7119 = (uint16_t)(212); + _curvea0[619] = _7119; + uint16_t _7120 = (uint16_t)(212); + _curvea0[620] = _7120; + uint16_t _7121 = (uint16_t)(212); + _curvea0[621] = _7121; + uint16_t _7122 = (uint16_t)(212); + _curvea0[622] = _7122; + uint16_t _7123 = (uint16_t)(212); + _curvea0[623] = _7123; + uint16_t _7124 = (uint16_t)(212); + _curvea0[624] = _7124; + uint16_t _7125 = (uint16_t)(213); + _curvea0[625] = _7125; + uint16_t _7126 = (uint16_t)(213); + _curvea0[626] = _7126; + uint16_t _7127 = (uint16_t)(213); + _curvea0[627] = _7127; + uint16_t _7128 = (uint16_t)(213); + _curvea0[628] = _7128; + uint16_t _7129 = (uint16_t)(213); + _curvea0[629] = _7129; + uint16_t _7130 = (uint16_t)(213); + _curvea0[630] = _7130; + uint16_t _7131 = (uint16_t)(213); + _curvea0[631] = _7131; + uint16_t _7132 = (uint16_t)(214); + _curvea0[632] = _7132; + uint16_t _7133 = (uint16_t)(214); + _curvea0[633] = _7133; + uint16_t _7134 = (uint16_t)(214); + _curvea0[634] = _7134; + uint16_t _7135 = (uint16_t)(214); + _curvea0[635] = _7135; + uint16_t _7136 = (uint16_t)(214); + _curvea0[636] = _7136; + uint16_t _7137 = (uint16_t)(214); + _curvea0[637] = _7137; + uint16_t _7138 = (uint16_t)(214); + _curvea0[638] = _7138; + uint16_t _7139 = (uint16_t)(215); + _curvea0[639] = _7139; + uint16_t _7140 = (uint16_t)(215); + _curvea0[640] = _7140; + uint16_t _7141 = (uint16_t)(215); + _curvea0[641] = _7141; + uint16_t _7142 = (uint16_t)(215); + _curvea0[642] = _7142; + uint16_t _7143 = (uint16_t)(215); + _curvea0[643] = _7143; + uint16_t _7144 = (uint16_t)(215); + _curvea0[644] = _7144; + uint16_t _7145 = (uint16_t)(216); + _curvea0[645] = _7145; + uint16_t _7146 = (uint16_t)(216); + _curvea0[646] = _7146; + uint16_t _7147 = (uint16_t)(216); + _curvea0[647] = _7147; + uint16_t _7148 = (uint16_t)(216); + _curvea0[648] = _7148; + uint16_t _7149 = (uint16_t)(216); + _curvea0[649] = _7149; + uint16_t _7150 = (uint16_t)(216); + _curvea0[650] = _7150; + uint16_t _7151 = (uint16_t)(216); + _curvea0[651] = _7151; + uint16_t _7152 = (uint16_t)(217); + _curvea0[652] = _7152; + uint16_t _7153 = (uint16_t)(217); + _curvea0[653] = _7153; + uint16_t _7154 = (uint16_t)(217); + _curvea0[654] = _7154; + uint16_t _7155 = (uint16_t)(217); + _curvea0[655] = _7155; + uint16_t _7156 = (uint16_t)(217); + _curvea0[656] = _7156; + uint16_t _7157 = (uint16_t)(217); + _curvea0[657] = _7157; + uint16_t _7158 = (uint16_t)(217); + _curvea0[658] = _7158; + uint16_t _7159 = (uint16_t)(218); + _curvea0[659] = _7159; + uint16_t _7160 = (uint16_t)(218); + _curvea0[660] = _7160; + uint16_t _7161 = (uint16_t)(218); + _curvea0[661] = _7161; + uint16_t _7162 = (uint16_t)(218); + _curvea0[662] = _7162; + uint16_t _7163 = (uint16_t)(218); + _curvea0[663] = _7163; + uint16_t _7164 = (uint16_t)(218); + _curvea0[664] = _7164; + uint16_t _7165 = (uint16_t)(218); + _curvea0[665] = _7165; + uint16_t _7166 = (uint16_t)(219); + _curvea0[666] = _7166; + uint16_t _7167 = (uint16_t)(219); + _curvea0[667] = _7167; + uint16_t _7168 = (uint16_t)(219); + _curvea0[668] = _7168; + uint16_t _7169 = (uint16_t)(219); + _curvea0[669] = _7169; + uint16_t _7170 = (uint16_t)(219); + _curvea0[670] = _7170; + uint16_t _7171 = (uint16_t)(219); + _curvea0[671] = _7171; + uint16_t _7172 = (uint16_t)(219); + _curvea0[672] = _7172; + uint16_t _7173 = (uint16_t)(220); + _curvea0[673] = _7173; + uint16_t _7174 = (uint16_t)(220); + _curvea0[674] = _7174; + uint16_t _7175 = (uint16_t)(220); + _curvea0[675] = _7175; + uint16_t _7176 = (uint16_t)(220); + _curvea0[676] = _7176; + uint16_t _7177 = (uint16_t)(220); + _curvea0[677] = _7177; + uint16_t _7178 = (uint16_t)(220); + _curvea0[678] = _7178; + uint16_t _7179 = (uint16_t)(220); + _curvea0[679] = _7179; + uint16_t _7180 = (uint16_t)(220); + _curvea0[680] = _7180; + uint16_t _7181 = (uint16_t)(221); + _curvea0[681] = _7181; + uint16_t _7182 = (uint16_t)(221); + _curvea0[682] = _7182; + uint16_t _7183 = (uint16_t)(221); + _curvea0[683] = _7183; + uint16_t _7184 = (uint16_t)(221); + _curvea0[684] = _7184; + uint16_t _7185 = (uint16_t)(221); + _curvea0[685] = _7185; + uint16_t _7186 = (uint16_t)(221); + _curvea0[686] = _7186; + uint16_t _7187 = (uint16_t)(221); + _curvea0[687] = _7187; + uint16_t _7188 = (uint16_t)(222); + _curvea0[688] = _7188; + uint16_t _7189 = (uint16_t)(222); + _curvea0[689] = _7189; + uint16_t _7190 = (uint16_t)(222); + _curvea0[690] = _7190; + uint16_t _7191 = (uint16_t)(222); + _curvea0[691] = _7191; + uint16_t _7192 = (uint16_t)(222); + _curvea0[692] = _7192; + uint16_t _7193 = (uint16_t)(222); + _curvea0[693] = _7193; + uint16_t _7194 = (uint16_t)(222); + _curvea0[694] = _7194; + uint16_t _7195 = (uint16_t)(223); + _curvea0[695] = _7195; + uint16_t _7196 = (uint16_t)(223); + _curvea0[696] = _7196; + uint16_t _7197 = (uint16_t)(223); + _curvea0[697] = _7197; + uint16_t _7198 = (uint16_t)(223); + _curvea0[698] = _7198; + uint16_t _7199 = (uint16_t)(223); + _curvea0[699] = _7199; + uint16_t _7200 = (uint16_t)(223); + _curvea0[700] = _7200; + uint16_t _7201 = (uint16_t)(223); + _curvea0[701] = _7201; + uint16_t _7202 = (uint16_t)(223); + _curvea0[702] = _7202; + uint16_t _7203 = (uint16_t)(224); + _curvea0[703] = _7203; + uint16_t _7204 = (uint16_t)(224); + _curvea0[704] = _7204; + uint16_t _7205 = (uint16_t)(224); + _curvea0[705] = _7205; + uint16_t _7206 = (uint16_t)(224); + _curvea0[706] = _7206; + uint16_t _7207 = (uint16_t)(224); + _curvea0[707] = _7207; + uint16_t _7208 = (uint16_t)(224); + _curvea0[708] = _7208; + uint16_t _7209 = (uint16_t)(224); + _curvea0[709] = _7209; + uint16_t _7210 = (uint16_t)(224); + _curvea0[710] = _7210; + uint16_t _7211 = (uint16_t)(225); + _curvea0[711] = _7211; + uint16_t _7212 = (uint16_t)(225); + _curvea0[712] = _7212; + uint16_t _7213 = (uint16_t)(225); + _curvea0[713] = _7213; + uint16_t _7214 = (uint16_t)(225); + _curvea0[714] = _7214; + uint16_t _7215 = (uint16_t)(225); + _curvea0[715] = _7215; + uint16_t _7216 = (uint16_t)(225); + _curvea0[716] = _7216; + uint16_t _7217 = (uint16_t)(225); + _curvea0[717] = _7217; + uint16_t _7218 = (uint16_t)(226); + _curvea0[718] = _7218; + uint16_t _7219 = (uint16_t)(226); + _curvea0[719] = _7219; + uint16_t _7220 = (uint16_t)(226); + _curvea0[720] = _7220; + uint16_t _7221 = (uint16_t)(226); + _curvea0[721] = _7221; + uint16_t _7222 = (uint16_t)(226); + _curvea0[722] = _7222; + uint16_t _7223 = (uint16_t)(226); + _curvea0[723] = _7223; + uint16_t _7224 = (uint16_t)(226); + _curvea0[724] = _7224; + uint16_t _7225 = (uint16_t)(226); + _curvea0[725] = _7225; + uint16_t _7226 = (uint16_t)(227); + _curvea0[726] = _7226; + uint16_t _7227 = (uint16_t)(227); + _curvea0[727] = _7227; + uint16_t _7228 = (uint16_t)(227); + _curvea0[728] = _7228; + uint16_t _7229 = (uint16_t)(227); + _curvea0[729] = _7229; + uint16_t _7230 = (uint16_t)(227); + _curvea0[730] = _7230; + uint16_t _7231 = (uint16_t)(227); + _curvea0[731] = _7231; + uint16_t _7232 = (uint16_t)(227); + _curvea0[732] = _7232; + uint16_t _7233 = (uint16_t)(227); + _curvea0[733] = _7233; + uint16_t _7234 = (uint16_t)(228); + _curvea0[734] = _7234; + uint16_t _7235 = (uint16_t)(228); + _curvea0[735] = _7235; + uint16_t _7236 = (uint16_t)(228); + _curvea0[736] = _7236; + uint16_t _7237 = (uint16_t)(228); + _curvea0[737] = _7237; + uint16_t _7238 = (uint16_t)(228); + _curvea0[738] = _7238; + uint16_t _7239 = (uint16_t)(228); + _curvea0[739] = _7239; + uint16_t _7240 = (uint16_t)(228); + _curvea0[740] = _7240; + uint16_t _7241 = (uint16_t)(228); + _curvea0[741] = _7241; + uint16_t _7242 = (uint16_t)(228); + _curvea0[742] = _7242; + uint16_t _7243 = (uint16_t)(229); + _curvea0[743] = _7243; + uint16_t _7244 = (uint16_t)(229); + _curvea0[744] = _7244; + uint16_t _7245 = (uint16_t)(229); + _curvea0[745] = _7245; + uint16_t _7246 = (uint16_t)(229); + _curvea0[746] = _7246; + uint16_t _7247 = (uint16_t)(229); + _curvea0[747] = _7247; + uint16_t _7248 = (uint16_t)(229); + _curvea0[748] = _7248; + uint16_t _7249 = (uint16_t)(229); + _curvea0[749] = _7249; + uint16_t _7250 = (uint16_t)(229); + _curvea0[750] = _7250; + uint16_t _7251 = (uint16_t)(230); + _curvea0[751] = _7251; + uint16_t _7252 = (uint16_t)(230); + _curvea0[752] = _7252; + uint16_t _7253 = (uint16_t)(230); + _curvea0[753] = _7253; + uint16_t _7254 = (uint16_t)(230); + _curvea0[754] = _7254; + uint16_t _7255 = (uint16_t)(230); + _curvea0[755] = _7255; + uint16_t _7256 = (uint16_t)(230); + _curvea0[756] = _7256; + uint16_t _7257 = (uint16_t)(230); + _curvea0[757] = _7257; + uint16_t _7258 = (uint16_t)(230); + _curvea0[758] = _7258; + uint16_t _7259 = (uint16_t)(231); + _curvea0[759] = _7259; + uint16_t _7260 = (uint16_t)(231); + _curvea0[760] = _7260; + uint16_t _7261 = (uint16_t)(231); + _curvea0[761] = _7261; + uint16_t _7262 = (uint16_t)(231); + _curvea0[762] = _7262; + uint16_t _7263 = (uint16_t)(231); + _curvea0[763] = _7263; + uint16_t _7264 = (uint16_t)(231); + _curvea0[764] = _7264; + uint16_t _7265 = (uint16_t)(231); + _curvea0[765] = _7265; + uint16_t _7266 = (uint16_t)(231); + _curvea0[766] = _7266; + uint16_t _7267 = (uint16_t)(231); + _curvea0[767] = _7267; + uint16_t _7268 = (uint16_t)(232); + _curvea0[768] = _7268; + uint16_t _7269 = (uint16_t)(232); + _curvea0[769] = _7269; + uint16_t _7270 = (uint16_t)(232); + _curvea0[770] = _7270; + uint16_t _7271 = (uint16_t)(232); + _curvea0[771] = _7271; + uint16_t _7272 = (uint16_t)(232); + _curvea0[772] = _7272; + uint16_t _7273 = (uint16_t)(232); + _curvea0[773] = _7273; + uint16_t _7274 = (uint16_t)(232); + _curvea0[774] = _7274; + uint16_t _7275 = (uint16_t)(232); + _curvea0[775] = _7275; + uint16_t _7276 = (uint16_t)(233); + _curvea0[776] = _7276; + uint16_t _7277 = (uint16_t)(233); + _curvea0[777] = _7277; + uint16_t _7278 = (uint16_t)(233); + _curvea0[778] = _7278; + uint16_t _7279 = (uint16_t)(233); + _curvea0[779] = _7279; + uint16_t _7280 = (uint16_t)(233); + _curvea0[780] = _7280; + uint16_t _7281 = (uint16_t)(233); + _curvea0[781] = _7281; + uint16_t _7282 = (uint16_t)(233); + _curvea0[782] = _7282; + uint16_t _7283 = (uint16_t)(233); + _curvea0[783] = _7283; + uint16_t _7284 = (uint16_t)(233); + _curvea0[784] = _7284; + uint16_t _7285 = (uint16_t)(234); + _curvea0[785] = _7285; + uint16_t _7286 = (uint16_t)(234); + _curvea0[786] = _7286; + uint16_t _7287 = (uint16_t)(234); + _curvea0[787] = _7287; + uint16_t _7288 = (uint16_t)(234); + _curvea0[788] = _7288; + uint16_t _7289 = (uint16_t)(234); + _curvea0[789] = _7289; + uint16_t _7290 = (uint16_t)(234); + _curvea0[790] = _7290; + uint16_t _7291 = (uint16_t)(234); + _curvea0[791] = _7291; + uint16_t _7292 = (uint16_t)(234); + _curvea0[792] = _7292; + uint16_t _7293 = (uint16_t)(234); + _curvea0[793] = _7293; + uint16_t _7294 = (uint16_t)(235); + _curvea0[794] = _7294; + uint16_t _7295 = (uint16_t)(235); + _curvea0[795] = _7295; + uint16_t _7296 = (uint16_t)(235); + _curvea0[796] = _7296; + uint16_t _7297 = (uint16_t)(235); + _curvea0[797] = _7297; + uint16_t _7298 = (uint16_t)(235); + _curvea0[798] = _7298; + uint16_t _7299 = (uint16_t)(235); + _curvea0[799] = _7299; + uint16_t _7300 = (uint16_t)(235); + _curvea0[800] = _7300; + uint16_t _7301 = (uint16_t)(235); + _curvea0[801] = _7301; + uint16_t _7302 = (uint16_t)(235); + _curvea0[802] = _7302; + uint16_t _7303 = (uint16_t)(236); + _curvea0[803] = _7303; + uint16_t _7304 = (uint16_t)(236); + _curvea0[804] = _7304; + uint16_t _7305 = (uint16_t)(236); + _curvea0[805] = _7305; + uint16_t _7306 = (uint16_t)(236); + _curvea0[806] = _7306; + uint16_t _7307 = (uint16_t)(236); + _curvea0[807] = _7307; + uint16_t _7308 = (uint16_t)(236); + _curvea0[808] = _7308; + uint16_t _7309 = (uint16_t)(236); + _curvea0[809] = _7309; + uint16_t _7310 = (uint16_t)(236); + _curvea0[810] = _7310; + uint16_t _7311 = (uint16_t)(236); + _curvea0[811] = _7311; + uint16_t _7312 = (uint16_t)(237); + _curvea0[812] = _7312; + uint16_t _7313 = (uint16_t)(237); + _curvea0[813] = _7313; + uint16_t _7314 = (uint16_t)(237); + _curvea0[814] = _7314; + uint16_t _7315 = (uint16_t)(237); + _curvea0[815] = _7315; + uint16_t _7316 = (uint16_t)(237); + _curvea0[816] = _7316; + uint16_t _7317 = (uint16_t)(237); + _curvea0[817] = _7317; + uint16_t _7318 = (uint16_t)(237); + _curvea0[818] = _7318; + uint16_t _7319 = (uint16_t)(237); + _curvea0[819] = _7319; + uint16_t _7320 = (uint16_t)(237); + _curvea0[820] = _7320; + uint16_t _7321 = (uint16_t)(237); + _curvea0[821] = _7321; + uint16_t _7322 = (uint16_t)(238); + _curvea0[822] = _7322; + uint16_t _7323 = (uint16_t)(238); + _curvea0[823] = _7323; + uint16_t _7324 = (uint16_t)(238); + _curvea0[824] = _7324; + uint16_t _7325 = (uint16_t)(238); + _curvea0[825] = _7325; + uint16_t _7326 = (uint16_t)(238); + _curvea0[826] = _7326; + uint16_t _7327 = (uint16_t)(238); + _curvea0[827] = _7327; + uint16_t _7328 = (uint16_t)(238); + _curvea0[828] = _7328; + uint16_t _7329 = (uint16_t)(238); + _curvea0[829] = _7329; + uint16_t _7330 = (uint16_t)(238); + _curvea0[830] = _7330; + uint16_t _7331 = (uint16_t)(239); + _curvea0[831] = _7331; + uint16_t _7332 = (uint16_t)(239); + _curvea0[832] = _7332; + uint16_t _7333 = (uint16_t)(239); + _curvea0[833] = _7333; + uint16_t _7334 = (uint16_t)(239); + _curvea0[834] = _7334; + uint16_t _7335 = (uint16_t)(239); + _curvea0[835] = _7335; + uint16_t _7336 = (uint16_t)(239); + _curvea0[836] = _7336; + uint16_t _7337 = (uint16_t)(239); + _curvea0[837] = _7337; + uint16_t _7338 = (uint16_t)(239); + _curvea0[838] = _7338; + uint16_t _7339 = (uint16_t)(239); + _curvea0[839] = _7339; + uint16_t _7340 = (uint16_t)(239); + _curvea0[840] = _7340; + uint16_t _7341 = (uint16_t)(240); + _curvea0[841] = _7341; + uint16_t _7342 = (uint16_t)(240); + _curvea0[842] = _7342; + uint16_t _7343 = (uint16_t)(240); + _curvea0[843] = _7343; + uint16_t _7344 = (uint16_t)(240); + _curvea0[844] = _7344; + uint16_t _7345 = (uint16_t)(240); + _curvea0[845] = _7345; + uint16_t _7346 = (uint16_t)(240); + _curvea0[846] = _7346; + uint16_t _7347 = (uint16_t)(240); + _curvea0[847] = _7347; + uint16_t _7348 = (uint16_t)(240); + _curvea0[848] = _7348; + uint16_t _7349 = (uint16_t)(240); + _curvea0[849] = _7349; + uint16_t _7350 = (uint16_t)(240); + _curvea0[850] = _7350; + uint16_t _7351 = (uint16_t)(241); + _curvea0[851] = _7351; + uint16_t _7352 = (uint16_t)(241); + _curvea0[852] = _7352; + uint16_t _7353 = (uint16_t)(241); + _curvea0[853] = _7353; + uint16_t _7354 = (uint16_t)(241); + _curvea0[854] = _7354; + uint16_t _7355 = (uint16_t)(241); + _curvea0[855] = _7355; + uint16_t _7356 = (uint16_t)(241); + _curvea0[856] = _7356; + uint16_t _7357 = (uint16_t)(241); + _curvea0[857] = _7357; + uint16_t _7358 = (uint16_t)(241); + _curvea0[858] = _7358; + uint16_t _7359 = (uint16_t)(241); + _curvea0[859] = _7359; + uint16_t _7360 = (uint16_t)(241); + _curvea0[860] = _7360; + uint16_t _7361 = (uint16_t)(242); + _curvea0[861] = _7361; + uint16_t _7362 = (uint16_t)(242); + _curvea0[862] = _7362; + uint16_t _7363 = (uint16_t)(242); + _curvea0[863] = _7363; + uint16_t _7364 = (uint16_t)(242); + _curvea0[864] = _7364; + uint16_t _7365 = (uint16_t)(242); + _curvea0[865] = _7365; + uint16_t _7366 = (uint16_t)(242); + _curvea0[866] = _7366; + uint16_t _7367 = (uint16_t)(242); + _curvea0[867] = _7367; + uint16_t _7368 = (uint16_t)(242); + _curvea0[868] = _7368; + uint16_t _7369 = (uint16_t)(242); + _curvea0[869] = _7369; + uint16_t _7370 = (uint16_t)(242); + _curvea0[870] = _7370; + uint16_t _7371 = (uint16_t)(243); + _curvea0[871] = _7371; + uint16_t _7372 = (uint16_t)(243); + _curvea0[872] = _7372; + uint16_t _7373 = (uint16_t)(243); + _curvea0[873] = _7373; + uint16_t _7374 = (uint16_t)(243); + _curvea0[874] = _7374; + uint16_t _7375 = (uint16_t)(243); + _curvea0[875] = _7375; + uint16_t _7376 = (uint16_t)(243); + _curvea0[876] = _7376; + uint16_t _7377 = (uint16_t)(243); + _curvea0[877] = _7377; + uint16_t _7378 = (uint16_t)(243); + _curvea0[878] = _7378; + uint16_t _7379 = (uint16_t)(243); + _curvea0[879] = _7379; + uint16_t _7380 = (uint16_t)(243); + _curvea0[880] = _7380; + uint16_t _7381 = (uint16_t)(244); + _curvea0[881] = _7381; + uint16_t _7382 = (uint16_t)(244); + _curvea0[882] = _7382; + uint16_t _7383 = (uint16_t)(244); + _curvea0[883] = _7383; + uint16_t _7384 = (uint16_t)(244); + _curvea0[884] = _7384; + uint16_t _7385 = (uint16_t)(244); + _curvea0[885] = _7385; + uint16_t _7386 = (uint16_t)(244); + _curvea0[886] = _7386; + uint16_t _7387 = (uint16_t)(244); + _curvea0[887] = _7387; + uint16_t _7388 = (uint16_t)(244); + _curvea0[888] = _7388; + uint16_t _7389 = (uint16_t)(244); + _curvea0[889] = _7389; + uint16_t _7390 = (uint16_t)(244); + _curvea0[890] = _7390; + uint16_t _7391 = (uint16_t)(244); + _curvea0[891] = _7391; + uint16_t _7392 = (uint16_t)(245); + _curvea0[892] = _7392; + uint16_t _7393 = (uint16_t)(245); + _curvea0[893] = _7393; + uint16_t _7394 = (uint16_t)(245); + _curvea0[894] = _7394; + uint16_t _7395 = (uint16_t)(245); + _curvea0[895] = _7395; + uint16_t _7396 = (uint16_t)(245); + _curvea0[896] = _7396; + uint16_t _7397 = (uint16_t)(245); + _curvea0[897] = _7397; + uint16_t _7398 = (uint16_t)(245); + _curvea0[898] = _7398; + uint16_t _7399 = (uint16_t)(245); + _curvea0[899] = _7399; + uint16_t _7400 = (uint16_t)(245); + _curvea0[900] = _7400; + uint16_t _7401 = (uint16_t)(245); + _curvea0[901] = _7401; + uint16_t _7402 = (uint16_t)(245); + _curvea0[902] = _7402; + uint16_t _7403 = (uint16_t)(246); + _curvea0[903] = _7403; + uint16_t _7404 = (uint16_t)(246); + _curvea0[904] = _7404; + uint16_t _7405 = (uint16_t)(246); + _curvea0[905] = _7405; + uint16_t _7406 = (uint16_t)(246); + _curvea0[906] = _7406; + uint16_t _7407 = (uint16_t)(246); + _curvea0[907] = _7407; + uint16_t _7408 = (uint16_t)(246); + _curvea0[908] = _7408; + uint16_t _7409 = (uint16_t)(246); + _curvea0[909] = _7409; + uint16_t _7410 = (uint16_t)(246); + _curvea0[910] = _7410; + uint16_t _7411 = (uint16_t)(246); + _curvea0[911] = _7411; + uint16_t _7412 = (uint16_t)(246); + _curvea0[912] = _7412; + uint16_t _7413 = (uint16_t)(246); + _curvea0[913] = _7413; + uint16_t _7414 = (uint16_t)(247); + _curvea0[914] = _7414; + uint16_t _7415 = (uint16_t)(247); + _curvea0[915] = _7415; + uint16_t _7416 = (uint16_t)(247); + _curvea0[916] = _7416; + uint16_t _7417 = (uint16_t)(247); + _curvea0[917] = _7417; + uint16_t _7418 = (uint16_t)(247); + _curvea0[918] = _7418; + uint16_t _7419 = (uint16_t)(247); + _curvea0[919] = _7419; + uint16_t _7420 = (uint16_t)(247); + _curvea0[920] = _7420; + uint16_t _7421 = (uint16_t)(247); + _curvea0[921] = _7421; + uint16_t _7422 = (uint16_t)(247); + _curvea0[922] = _7422; + uint16_t _7423 = (uint16_t)(247); + _curvea0[923] = _7423; + uint16_t _7424 = (uint16_t)(247); + _curvea0[924] = _7424; + uint16_t _7425 = (uint16_t)(248); + _curvea0[925] = _7425; + uint16_t _7426 = (uint16_t)(248); + _curvea0[926] = _7426; + uint16_t _7427 = (uint16_t)(248); + _curvea0[927] = _7427; + uint16_t _7428 = (uint16_t)(248); + _curvea0[928] = _7428; + uint16_t _7429 = (uint16_t)(248); + _curvea0[929] = _7429; + uint16_t _7430 = (uint16_t)(248); + _curvea0[930] = _7430; + uint16_t _7431 = (uint16_t)(248); + _curvea0[931] = _7431; + uint16_t _7432 = (uint16_t)(248); + _curvea0[932] = _7432; + uint16_t _7433 = (uint16_t)(248); + _curvea0[933] = _7433; + uint16_t _7434 = (uint16_t)(248); + _curvea0[934] = _7434; + uint16_t _7435 = (uint16_t)(248); + _curvea0[935] = _7435; + uint16_t _7436 = (uint16_t)(249); + _curvea0[936] = _7436; + uint16_t _7437 = (uint16_t)(249); + _curvea0[937] = _7437; + uint16_t _7438 = (uint16_t)(249); + _curvea0[938] = _7438; + uint16_t _7439 = (uint16_t)(249); + _curvea0[939] = _7439; + uint16_t _7440 = (uint16_t)(249); + _curvea0[940] = _7440; + uint16_t _7441 = (uint16_t)(249); + _curvea0[941] = _7441; + uint16_t _7442 = (uint16_t)(249); + _curvea0[942] = _7442; + uint16_t _7443 = (uint16_t)(249); + _curvea0[943] = _7443; + uint16_t _7444 = (uint16_t)(249); + _curvea0[944] = _7444; + uint16_t _7445 = (uint16_t)(249); + _curvea0[945] = _7445; + uint16_t _7446 = (uint16_t)(249); + _curvea0[946] = _7446; + uint16_t _7447 = (uint16_t)(249); + _curvea0[947] = _7447; + uint16_t _7448 = (uint16_t)(250); + _curvea0[948] = _7448; + uint16_t _7449 = (uint16_t)(250); + _curvea0[949] = _7449; + uint16_t _7450 = (uint16_t)(250); + _curvea0[950] = _7450; + uint16_t _7451 = (uint16_t)(250); + _curvea0[951] = _7451; + uint16_t _7452 = (uint16_t)(250); + _curvea0[952] = _7452; + uint16_t _7453 = (uint16_t)(250); + _curvea0[953] = _7453; + uint16_t _7454 = (uint16_t)(250); + _curvea0[954] = _7454; + uint16_t _7455 = (uint16_t)(250); + _curvea0[955] = _7455; + uint16_t _7456 = (uint16_t)(250); + _curvea0[956] = _7456; + uint16_t _7457 = (uint16_t)(250); + _curvea0[957] = _7457; + uint16_t _7458 = (uint16_t)(250); + _curvea0[958] = _7458; + uint16_t _7459 = (uint16_t)(250); + _curvea0[959] = _7459; + uint16_t _7460 = (uint16_t)(251); + _curvea0[960] = _7460; + uint16_t _7461 = (uint16_t)(251); + _curvea0[961] = _7461; + uint16_t _7462 = (uint16_t)(251); + _curvea0[962] = _7462; + uint16_t _7463 = (uint16_t)(251); + _curvea0[963] = _7463; + uint16_t _7464 = (uint16_t)(251); + _curvea0[964] = _7464; + uint16_t _7465 = (uint16_t)(251); + _curvea0[965] = _7465; + uint16_t _7466 = (uint16_t)(251); + _curvea0[966] = _7466; + uint16_t _7467 = (uint16_t)(251); + _curvea0[967] = _7467; + uint16_t _7468 = (uint16_t)(251); + _curvea0[968] = _7468; + uint16_t _7469 = (uint16_t)(251); + _curvea0[969] = _7469; + uint16_t _7470 = (uint16_t)(251); + _curvea0[970] = _7470; + uint16_t _7471 = (uint16_t)(251); + _curvea0[971] = _7471; + uint16_t _7472 = (uint16_t)(252); + _curvea0[972] = _7472; + uint16_t _7473 = (uint16_t)(252); + _curvea0[973] = _7473; + uint16_t _7474 = (uint16_t)(252); + _curvea0[974] = _7474; + uint16_t _7475 = (uint16_t)(252); + _curvea0[975] = _7475; + uint16_t _7476 = (uint16_t)(252); + _curvea0[976] = _7476; + uint16_t _7477 = (uint16_t)(252); + _curvea0[977] = _7477; + uint16_t _7478 = (uint16_t)(252); + _curvea0[978] = _7478; + uint16_t _7479 = (uint16_t)(252); + _curvea0[979] = _7479; + uint16_t _7480 = (uint16_t)(252); + _curvea0[980] = _7480; + uint16_t _7481 = (uint16_t)(252); + _curvea0[981] = _7481; + uint16_t _7482 = (uint16_t)(252); + _curvea0[982] = _7482; + uint16_t _7483 = (uint16_t)(252); + _curvea0[983] = _7483; + uint16_t _7484 = (uint16_t)(252); + _curvea0[984] = _7484; + uint16_t _7485 = (uint16_t)(253); + _curvea0[985] = _7485; + uint16_t _7486 = (uint16_t)(253); + _curvea0[986] = _7486; + uint16_t _7487 = (uint16_t)(253); + _curvea0[987] = _7487; + uint16_t _7488 = (uint16_t)(253); + _curvea0[988] = _7488; + uint16_t _7489 = (uint16_t)(253); + _curvea0[989] = _7489; + uint16_t _7490 = (uint16_t)(253); + _curvea0[990] = _7490; + uint16_t _7491 = (uint16_t)(253); + _curvea0[991] = _7491; + uint16_t _7492 = (uint16_t)(253); + _curvea0[992] = _7492; + uint16_t _7493 = (uint16_t)(253); + _curvea0[993] = _7493; + uint16_t _7494 = (uint16_t)(253); + _curvea0[994] = _7494; + uint16_t _7495 = (uint16_t)(253); + _curvea0[995] = _7495; + uint16_t _7496 = (uint16_t)(253); + _curvea0[996] = _7496; + uint16_t _7497 = (uint16_t)(253); + _curvea0[997] = _7497; + uint16_t _7498 = (uint16_t)(254); + _curvea0[998] = _7498; + uint16_t _7499 = (uint16_t)(254); + _curvea0[999] = _7499; + uint16_t _7500 = (uint16_t)(254); + _curvea0[1000] = _7500; + uint16_t _7501 = (uint16_t)(254); + _curvea0[1001] = _7501; + uint16_t _7502 = (uint16_t)(254); + _curvea0[1002] = _7502; + uint16_t _7503 = (uint16_t)(254); + _curvea0[1003] = _7503; + uint16_t _7504 = (uint16_t)(254); + _curvea0[1004] = _7504; + uint16_t _7505 = (uint16_t)(254); + _curvea0[1005] = _7505; + uint16_t _7506 = (uint16_t)(254); + _curvea0[1006] = _7506; + uint16_t _7507 = (uint16_t)(254); + _curvea0[1007] = _7507; + uint16_t _7508 = (uint16_t)(254); + _curvea0[1008] = _7508; + uint16_t _7509 = (uint16_t)(254); + _curvea0[1009] = _7509; + uint16_t _7510 = (uint16_t)(254); + _curvea0[1010] = _7510; + uint16_t _7511 = (uint16_t)(255); + _curvea0[1011] = _7511; + uint16_t _7512 = (uint16_t)(255); + _curvea0[1012] = _7512; + uint16_t _7513 = (uint16_t)(255); + _curvea0[1013] = _7513; + uint16_t _7514 = (uint16_t)(255); + _curvea0[1014] = _7514; + uint16_t _7515 = (uint16_t)(255); + _curvea0[1015] = _7515; + uint16_t _7516 = (uint16_t)(255); + _curvea0[1016] = _7516; + uint16_t _7517 = (uint16_t)(255); + _curvea0[1017] = _7517; + uint16_t _7518 = (uint16_t)(255); + _curvea0[1018] = _7518; + uint16_t _7519 = (uint16_t)(255); + _curvea0[1019] = _7519; + uint16_t _7520 = (uint16_t)(255); + _curvea0[1020] = _7520; + uint16_t _7521 = (uint16_t)(255); + _curvea0[1021] = _7521; + uint16_t _7522 = (uint16_t)(255); + _curvea0[1022] = _7522; + uint16_t _7523 = (uint16_t)(255); + _curvea0[1023] = _7523; + + int16_t _7524 = (int16_t)(1023); + int16_t _7525 = min(_corrected_stencil_5, _7524); + int16_t _7526 = (int16_t)(0); + int16_t _7527 = max(_7525, _7526); + uint16_t _7528 = (uint16_t)(_7527); + int32_t _7529 = (int32_t)(_7528); + uint16_t _7530 = ((const uint16_t *)_curvea0)[_7529]; + return _7530; +} + +//store is: curved.stencil(((curved_s0_x_x_2*2) + 1), curved_s0_y_2, 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x_2*2) + 1), curved_s0_y_2, 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_5(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_6 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _7546 = (uint16_t)(0); + _curvea0[0] = _7546; + uint16_t _7547 = (uint16_t)(4); + _curvea0[1] = _7547; + uint16_t _7548 = (uint16_t)(7); + _curvea0[2] = _7548; + uint16_t _7549 = (uint16_t)(8); + _curvea0[3] = _7549; + uint16_t _7550 = (uint16_t)(10); + _curvea0[4] = _7550; + uint16_t _7551 = (uint16_t)(11); + _curvea0[5] = _7551; + uint16_t _7552 = (uint16_t)(12); + _curvea0[6] = _7552; + uint16_t _7553 = (uint16_t)(13); + _curvea0[7] = _7553; + uint16_t _7554 = (uint16_t)(14); + _curvea0[8] = _7554; + uint16_t _7555 = (uint16_t)(15); + _curvea0[9] = _7555; + uint16_t _7556 = (uint16_t)(16); + _curvea0[10] = _7556; + uint16_t _7557 = (uint16_t)(17); + _curvea0[11] = _7557; + uint16_t _7558 = (uint16_t)(18); + _curvea0[12] = _7558; + uint16_t _7559 = (uint16_t)(19); + _curvea0[13] = _7559; + uint16_t _7560 = (uint16_t)(20); + _curvea0[14] = _7560; + uint16_t _7561 = (uint16_t)(21); + _curvea0[15] = _7561; + uint16_t _7562 = (uint16_t)(22); + _curvea0[16] = _7562; + uint16_t _7563 = (uint16_t)(22); + _curvea0[17] = _7563; + uint16_t _7564 = (uint16_t)(23); + _curvea0[18] = _7564; + uint16_t _7565 = (uint16_t)(24); + _curvea0[19] = _7565; + uint16_t _7566 = (uint16_t)(25); + _curvea0[20] = _7566; + uint16_t _7567 = (uint16_t)(25); + _curvea0[21] = _7567; + uint16_t _7568 = (uint16_t)(26); + _curvea0[22] = _7568; + uint16_t _7569 = (uint16_t)(27); + _curvea0[23] = _7569; + uint16_t _7570 = (uint16_t)(27); + _curvea0[24] = _7570; + uint16_t _7571 = (uint16_t)(28); + _curvea0[25] = _7571; + uint16_t _7572 = (uint16_t)(29); + _curvea0[26] = _7572; + uint16_t _7573 = (uint16_t)(29); + _curvea0[27] = _7573; + uint16_t _7574 = (uint16_t)(30); + _curvea0[28] = _7574; + uint16_t _7575 = (uint16_t)(31); + _curvea0[29] = _7575; + uint16_t _7576 = (uint16_t)(31); + _curvea0[30] = _7576; + uint16_t _7577 = (uint16_t)(32); + _curvea0[31] = _7577; + uint16_t _7578 = (uint16_t)(33); + _curvea0[32] = _7578; + uint16_t _7579 = (uint16_t)(33); + _curvea0[33] = _7579; + uint16_t _7580 = (uint16_t)(34); + _curvea0[34] = _7580; + uint16_t _7581 = (uint16_t)(34); + _curvea0[35] = _7581; + uint16_t _7582 = (uint16_t)(35); + _curvea0[36] = _7582; + uint16_t _7583 = (uint16_t)(36); + _curvea0[37] = _7583; + uint16_t _7584 = (uint16_t)(36); + _curvea0[38] = _7584; + uint16_t _7585 = (uint16_t)(37); + _curvea0[39] = _7585; + uint16_t _7586 = (uint16_t)(37); + _curvea0[40] = _7586; + uint16_t _7587 = (uint16_t)(38); + _curvea0[41] = _7587; + uint16_t _7588 = (uint16_t)(39); + _curvea0[42] = _7588; + uint16_t _7589 = (uint16_t)(39); + _curvea0[43] = _7589; + uint16_t _7590 = (uint16_t)(40); + _curvea0[44] = _7590; + uint16_t _7591 = (uint16_t)(40); + _curvea0[45] = _7591; + uint16_t _7592 = (uint16_t)(41); + _curvea0[46] = _7592; + uint16_t _7593 = (uint16_t)(41); + _curvea0[47] = _7593; + uint16_t _7594 = (uint16_t)(42); + _curvea0[48] = _7594; + uint16_t _7595 = (uint16_t)(42); + _curvea0[49] = _7595; + uint16_t _7596 = (uint16_t)(43); + _curvea0[50] = _7596; + uint16_t _7597 = (uint16_t)(44); + _curvea0[51] = _7597; + uint16_t _7598 = (uint16_t)(44); + _curvea0[52] = _7598; + uint16_t _7599 = (uint16_t)(45); + _curvea0[53] = _7599; + uint16_t _7600 = (uint16_t)(45); + _curvea0[54] = _7600; + uint16_t _7601 = (uint16_t)(46); + _curvea0[55] = _7601; + uint16_t _7602 = (uint16_t)(46); + _curvea0[56] = _7602; + uint16_t _7603 = (uint16_t)(47); + _curvea0[57] = _7603; + uint16_t _7604 = (uint16_t)(47); + _curvea0[58] = _7604; + uint16_t _7605 = (uint16_t)(48); + _curvea0[59] = _7605; + uint16_t _7606 = (uint16_t)(48); + _curvea0[60] = _7606; + uint16_t _7607 = (uint16_t)(49); + _curvea0[61] = _7607; + uint16_t _7608 = (uint16_t)(49); + _curvea0[62] = _7608; + uint16_t _7609 = (uint16_t)(50); + _curvea0[63] = _7609; + uint16_t _7610 = (uint16_t)(50); + _curvea0[64] = _7610; + uint16_t _7611 = (uint16_t)(51); + _curvea0[65] = _7611; + uint16_t _7612 = (uint16_t)(51); + _curvea0[66] = _7612; + uint16_t _7613 = (uint16_t)(52); + _curvea0[67] = _7613; + uint16_t _7614 = (uint16_t)(52); + _curvea0[68] = _7614; + uint16_t _7615 = (uint16_t)(53); + _curvea0[69] = _7615; + uint16_t _7616 = (uint16_t)(53); + _curvea0[70] = _7616; + uint16_t _7617 = (uint16_t)(54); + _curvea0[71] = _7617; + uint16_t _7618 = (uint16_t)(54); + _curvea0[72] = _7618; + uint16_t _7619 = (uint16_t)(55); + _curvea0[73] = _7619; + uint16_t _7620 = (uint16_t)(55); + _curvea0[74] = _7620; + uint16_t _7621 = (uint16_t)(56); + _curvea0[75] = _7621; + uint16_t _7622 = (uint16_t)(56); + _curvea0[76] = _7622; + uint16_t _7623 = (uint16_t)(57); + _curvea0[77] = _7623; + uint16_t _7624 = (uint16_t)(57); + _curvea0[78] = _7624; + uint16_t _7625 = (uint16_t)(58); + _curvea0[79] = _7625; + uint16_t _7626 = (uint16_t)(58); + _curvea0[80] = _7626; + uint16_t _7627 = (uint16_t)(58); + _curvea0[81] = _7627; + uint16_t _7628 = (uint16_t)(59); + _curvea0[82] = _7628; + uint16_t _7629 = (uint16_t)(59); + _curvea0[83] = _7629; + uint16_t _7630 = (uint16_t)(60); + _curvea0[84] = _7630; + uint16_t _7631 = (uint16_t)(60); + _curvea0[85] = _7631; + uint16_t _7632 = (uint16_t)(61); + _curvea0[86] = _7632; + uint16_t _7633 = (uint16_t)(61); + _curvea0[87] = _7633; + uint16_t _7634 = (uint16_t)(62); + _curvea0[88] = _7634; + uint16_t _7635 = (uint16_t)(62); + _curvea0[89] = _7635; + uint16_t _7636 = (uint16_t)(63); + _curvea0[90] = _7636; + uint16_t _7637 = (uint16_t)(63); + _curvea0[91] = _7637; + uint16_t _7638 = (uint16_t)(64); + _curvea0[92] = _7638; + uint16_t _7639 = (uint16_t)(64); + _curvea0[93] = _7639; + uint16_t _7640 = (uint16_t)(64); + _curvea0[94] = _7640; + uint16_t _7641 = (uint16_t)(65); + _curvea0[95] = _7641; + uint16_t _7642 = (uint16_t)(65); + _curvea0[96] = _7642; + uint16_t _7643 = (uint16_t)(66); + _curvea0[97] = _7643; + uint16_t _7644 = (uint16_t)(66); + _curvea0[98] = _7644; + uint16_t _7645 = (uint16_t)(67); + _curvea0[99] = _7645; + uint16_t _7646 = (uint16_t)(67); + _curvea0[100] = _7646; + uint16_t _7647 = (uint16_t)(68); + _curvea0[101] = _7647; + uint16_t _7648 = (uint16_t)(68); + _curvea0[102] = _7648; + uint16_t _7649 = (uint16_t)(68); + _curvea0[103] = _7649; + uint16_t _7650 = (uint16_t)(69); + _curvea0[104] = _7650; + uint16_t _7651 = (uint16_t)(69); + _curvea0[105] = _7651; + uint16_t _7652 = (uint16_t)(70); + _curvea0[106] = _7652; + uint16_t _7653 = (uint16_t)(70); + _curvea0[107] = _7653; + uint16_t _7654 = (uint16_t)(71); + _curvea0[108] = _7654; + uint16_t _7655 = (uint16_t)(71); + _curvea0[109] = _7655; + uint16_t _7656 = (uint16_t)(71); + _curvea0[110] = _7656; + uint16_t _7657 = (uint16_t)(72); + _curvea0[111] = _7657; + uint16_t _7658 = (uint16_t)(72); + _curvea0[112] = _7658; + uint16_t _7659 = (uint16_t)(73); + _curvea0[113] = _7659; + uint16_t _7660 = (uint16_t)(73); + _curvea0[114] = _7660; + uint16_t _7661 = (uint16_t)(74); + _curvea0[115] = _7661; + uint16_t _7662 = (uint16_t)(74); + _curvea0[116] = _7662; + uint16_t _7663 = (uint16_t)(74); + _curvea0[117] = _7663; + uint16_t _7664 = (uint16_t)(75); + _curvea0[118] = _7664; + uint16_t _7665 = (uint16_t)(75); + _curvea0[119] = _7665; + uint16_t _7666 = (uint16_t)(76); + _curvea0[120] = _7666; + uint16_t _7667 = (uint16_t)(76); + _curvea0[121] = _7667; + uint16_t _7668 = (uint16_t)(77); + _curvea0[122] = _7668; + uint16_t _7669 = (uint16_t)(77); + _curvea0[123] = _7669; + uint16_t _7670 = (uint16_t)(77); + _curvea0[124] = _7670; + uint16_t _7671 = (uint16_t)(78); + _curvea0[125] = _7671; + uint16_t _7672 = (uint16_t)(78); + _curvea0[126] = _7672; + uint16_t _7673 = (uint16_t)(79); + _curvea0[127] = _7673; + uint16_t _7674 = (uint16_t)(79); + _curvea0[128] = _7674; + uint16_t _7675 = (uint16_t)(79); + _curvea0[129] = _7675; + uint16_t _7676 = (uint16_t)(80); + _curvea0[130] = _7676; + uint16_t _7677 = (uint16_t)(80); + _curvea0[131] = _7677; + uint16_t _7678 = (uint16_t)(81); + _curvea0[132] = _7678; + uint16_t _7679 = (uint16_t)(81); + _curvea0[133] = _7679; + uint16_t _7680 = (uint16_t)(82); + _curvea0[134] = _7680; + uint16_t _7681 = (uint16_t)(82); + _curvea0[135] = _7681; + uint16_t _7682 = (uint16_t)(82); + _curvea0[136] = _7682; + uint16_t _7683 = (uint16_t)(83); + _curvea0[137] = _7683; + uint16_t _7684 = (uint16_t)(83); + _curvea0[138] = _7684; + uint16_t _7685 = (uint16_t)(84); + _curvea0[139] = _7685; + uint16_t _7686 = (uint16_t)(84); + _curvea0[140] = _7686; + uint16_t _7687 = (uint16_t)(84); + _curvea0[141] = _7687; + uint16_t _7688 = (uint16_t)(85); + _curvea0[142] = _7688; + uint16_t _7689 = (uint16_t)(85); + _curvea0[143] = _7689; + uint16_t _7690 = (uint16_t)(86); + _curvea0[144] = _7690; + uint16_t _7691 = (uint16_t)(86); + _curvea0[145] = _7691; + uint16_t _7692 = (uint16_t)(86); + _curvea0[146] = _7692; + uint16_t _7693 = (uint16_t)(87); + _curvea0[147] = _7693; + uint16_t _7694 = (uint16_t)(87); + _curvea0[148] = _7694; + uint16_t _7695 = (uint16_t)(88); + _curvea0[149] = _7695; + uint16_t _7696 = (uint16_t)(88); + _curvea0[150] = _7696; + uint16_t _7697 = (uint16_t)(88); + _curvea0[151] = _7697; + uint16_t _7698 = (uint16_t)(89); + _curvea0[152] = _7698; + uint16_t _7699 = (uint16_t)(89); + _curvea0[153] = _7699; + uint16_t _7700 = (uint16_t)(90); + _curvea0[154] = _7700; + uint16_t _7701 = (uint16_t)(90); + _curvea0[155] = _7701; + uint16_t _7702 = (uint16_t)(90); + _curvea0[156] = _7702; + uint16_t _7703 = (uint16_t)(91); + _curvea0[157] = _7703; + uint16_t _7704 = (uint16_t)(91); + _curvea0[158] = _7704; + uint16_t _7705 = (uint16_t)(92); + _curvea0[159] = _7705; + uint16_t _7706 = (uint16_t)(92); + _curvea0[160] = _7706; + uint16_t _7707 = (uint16_t)(92); + _curvea0[161] = _7707; + uint16_t _7708 = (uint16_t)(93); + _curvea0[162] = _7708; + uint16_t _7709 = (uint16_t)(93); + _curvea0[163] = _7709; + uint16_t _7710 = (uint16_t)(93); + _curvea0[164] = _7710; + uint16_t _7711 = (uint16_t)(94); + _curvea0[165] = _7711; + uint16_t _7712 = (uint16_t)(94); + _curvea0[166] = _7712; + uint16_t _7713 = (uint16_t)(95); + _curvea0[167] = _7713; + uint16_t _7714 = (uint16_t)(95); + _curvea0[168] = _7714; + uint16_t _7715 = (uint16_t)(95); + _curvea0[169] = _7715; + uint16_t _7716 = (uint16_t)(96); + _curvea0[170] = _7716; + uint16_t _7717 = (uint16_t)(96); + _curvea0[171] = _7717; + uint16_t _7718 = (uint16_t)(97); + _curvea0[172] = _7718; + uint16_t _7719 = (uint16_t)(97); + _curvea0[173] = _7719; + uint16_t _7720 = (uint16_t)(97); + _curvea0[174] = _7720; + uint16_t _7721 = (uint16_t)(98); + _curvea0[175] = _7721; + uint16_t _7722 = (uint16_t)(98); + _curvea0[176] = _7722; + uint16_t _7723 = (uint16_t)(99); + _curvea0[177] = _7723; + uint16_t _7724 = (uint16_t)(99); + _curvea0[178] = _7724; + uint16_t _7725 = (uint16_t)(99); + _curvea0[179] = _7725; + uint16_t _7726 = (uint16_t)(100); + _curvea0[180] = _7726; + uint16_t _7727 = (uint16_t)(100); + _curvea0[181] = _7727; + uint16_t _7728 = (uint16_t)(100); + _curvea0[182] = _7728; + uint16_t _7729 = (uint16_t)(101); + _curvea0[183] = _7729; + uint16_t _7730 = (uint16_t)(101); + _curvea0[184] = _7730; + uint16_t _7731 = (uint16_t)(102); + _curvea0[185] = _7731; + uint16_t _7732 = (uint16_t)(102); + _curvea0[186] = _7732; + uint16_t _7733 = (uint16_t)(102); + _curvea0[187] = _7733; + uint16_t _7734 = (uint16_t)(103); + _curvea0[188] = _7734; + uint16_t _7735 = (uint16_t)(103); + _curvea0[189] = _7735; + uint16_t _7736 = (uint16_t)(103); + _curvea0[190] = _7736; + uint16_t _7737 = (uint16_t)(104); + _curvea0[191] = _7737; + uint16_t _7738 = (uint16_t)(104); + _curvea0[192] = _7738; + uint16_t _7739 = (uint16_t)(105); + _curvea0[193] = _7739; + uint16_t _7740 = (uint16_t)(105); + _curvea0[194] = _7740; + uint16_t _7741 = (uint16_t)(105); + _curvea0[195] = _7741; + uint16_t _7742 = (uint16_t)(106); + _curvea0[196] = _7742; + uint16_t _7743 = (uint16_t)(106); + _curvea0[197] = _7743; + uint16_t _7744 = (uint16_t)(106); + _curvea0[198] = _7744; + uint16_t _7745 = (uint16_t)(107); + _curvea0[199] = _7745; + uint16_t _7746 = (uint16_t)(107); + _curvea0[200] = _7746; + uint16_t _7747 = (uint16_t)(108); + _curvea0[201] = _7747; + uint16_t _7748 = (uint16_t)(108); + _curvea0[202] = _7748; + uint16_t _7749 = (uint16_t)(108); + _curvea0[203] = _7749; + uint16_t _7750 = (uint16_t)(109); + _curvea0[204] = _7750; + uint16_t _7751 = (uint16_t)(109); + _curvea0[205] = _7751; + uint16_t _7752 = (uint16_t)(109); + _curvea0[206] = _7752; + uint16_t _7753 = (uint16_t)(110); + _curvea0[207] = _7753; + uint16_t _7754 = (uint16_t)(110); + _curvea0[208] = _7754; + uint16_t _7755 = (uint16_t)(111); + _curvea0[209] = _7755; + uint16_t _7756 = (uint16_t)(111); + _curvea0[210] = _7756; + uint16_t _7757 = (uint16_t)(111); + _curvea0[211] = _7757; + uint16_t _7758 = (uint16_t)(112); + _curvea0[212] = _7758; + uint16_t _7759 = (uint16_t)(112); + _curvea0[213] = _7759; + uint16_t _7760 = (uint16_t)(112); + _curvea0[214] = _7760; + uint16_t _7761 = (uint16_t)(113); + _curvea0[215] = _7761; + uint16_t _7762 = (uint16_t)(113); + _curvea0[216] = _7762; + uint16_t _7763 = (uint16_t)(113); + _curvea0[217] = _7763; + uint16_t _7764 = (uint16_t)(114); + _curvea0[218] = _7764; + uint16_t _7765 = (uint16_t)(114); + _curvea0[219] = _7765; + uint16_t _7766 = (uint16_t)(115); + _curvea0[220] = _7766; + uint16_t _7767 = (uint16_t)(115); + _curvea0[221] = _7767; + uint16_t _7768 = (uint16_t)(115); + _curvea0[222] = _7768; + uint16_t _7769 = (uint16_t)(116); + _curvea0[223] = _7769; + uint16_t _7770 = (uint16_t)(116); + _curvea0[224] = _7770; + uint16_t _7771 = (uint16_t)(116); + _curvea0[225] = _7771; + uint16_t _7772 = (uint16_t)(117); + _curvea0[226] = _7772; + uint16_t _7773 = (uint16_t)(117); + _curvea0[227] = _7773; + uint16_t _7774 = (uint16_t)(117); + _curvea0[228] = _7774; + uint16_t _7775 = (uint16_t)(118); + _curvea0[229] = _7775; + uint16_t _7776 = (uint16_t)(118); + _curvea0[230] = _7776; + uint16_t _7777 = (uint16_t)(119); + _curvea0[231] = _7777; + uint16_t _7778 = (uint16_t)(119); + _curvea0[232] = _7778; + uint16_t _7779 = (uint16_t)(119); + _curvea0[233] = _7779; + uint16_t _7780 = (uint16_t)(120); + _curvea0[234] = _7780; + uint16_t _7781 = (uint16_t)(120); + _curvea0[235] = _7781; + uint16_t _7782 = (uint16_t)(120); + _curvea0[236] = _7782; + uint16_t _7783 = (uint16_t)(121); + _curvea0[237] = _7783; + uint16_t _7784 = (uint16_t)(121); + _curvea0[238] = _7784; + uint16_t _7785 = (uint16_t)(121); + _curvea0[239] = _7785; + uint16_t _7786 = (uint16_t)(122); + _curvea0[240] = _7786; + uint16_t _7787 = (uint16_t)(122); + _curvea0[241] = _7787; + uint16_t _7788 = (uint16_t)(123); + _curvea0[242] = _7788; + uint16_t _7789 = (uint16_t)(123); + _curvea0[243] = _7789; + uint16_t _7790 = (uint16_t)(123); + _curvea0[244] = _7790; + uint16_t _7791 = (uint16_t)(124); + _curvea0[245] = _7791; + uint16_t _7792 = (uint16_t)(124); + _curvea0[246] = _7792; + uint16_t _7793 = (uint16_t)(124); + _curvea0[247] = _7793; + uint16_t _7794 = (uint16_t)(125); + _curvea0[248] = _7794; + uint16_t _7795 = (uint16_t)(125); + _curvea0[249] = _7795; + uint16_t _7796 = (uint16_t)(125); + _curvea0[250] = _7796; + uint16_t _7797 = (uint16_t)(126); + _curvea0[251] = _7797; + uint16_t _7798 = (uint16_t)(126); + _curvea0[252] = _7798; + uint16_t _7799 = (uint16_t)(126); + _curvea0[253] = _7799; + uint16_t _7800 = (uint16_t)(127); + _curvea0[254] = _7800; + uint16_t _7801 = (uint16_t)(127); + _curvea0[255] = _7801; + uint16_t _7802 = (uint16_t)(128); + _curvea0[256] = _7802; + uint16_t _7803 = (uint16_t)(128); + _curvea0[257] = _7803; + uint16_t _7804 = (uint16_t)(128); + _curvea0[258] = _7804; + uint16_t _7805 = (uint16_t)(129); + _curvea0[259] = _7805; + uint16_t _7806 = (uint16_t)(129); + _curvea0[260] = _7806; + uint16_t _7807 = (uint16_t)(129); + _curvea0[261] = _7807; + uint16_t _7808 = (uint16_t)(130); + _curvea0[262] = _7808; + uint16_t _7809 = (uint16_t)(130); + _curvea0[263] = _7809; + uint16_t _7810 = (uint16_t)(130); + _curvea0[264] = _7810; + uint16_t _7811 = (uint16_t)(131); + _curvea0[265] = _7811; + uint16_t _7812 = (uint16_t)(131); + _curvea0[266] = _7812; + uint16_t _7813 = (uint16_t)(131); + _curvea0[267] = _7813; + uint16_t _7814 = (uint16_t)(132); + _curvea0[268] = _7814; + uint16_t _7815 = (uint16_t)(132); + _curvea0[269] = _7815; + uint16_t _7816 = (uint16_t)(132); + _curvea0[270] = _7816; + uint16_t _7817 = (uint16_t)(133); + _curvea0[271] = _7817; + uint16_t _7818 = (uint16_t)(133); + _curvea0[272] = _7818; + uint16_t _7819 = (uint16_t)(133); + _curvea0[273] = _7819; + uint16_t _7820 = (uint16_t)(134); + _curvea0[274] = _7820; + uint16_t _7821 = (uint16_t)(134); + _curvea0[275] = _7821; + uint16_t _7822 = (uint16_t)(134); + _curvea0[276] = _7822; + uint16_t _7823 = (uint16_t)(135); + _curvea0[277] = _7823; + uint16_t _7824 = (uint16_t)(135); + _curvea0[278] = _7824; + uint16_t _7825 = (uint16_t)(135); + _curvea0[279] = _7825; + uint16_t _7826 = (uint16_t)(136); + _curvea0[280] = _7826; + uint16_t _7827 = (uint16_t)(136); + _curvea0[281] = _7827; + uint16_t _7828 = (uint16_t)(136); + _curvea0[282] = _7828; + uint16_t _7829 = (uint16_t)(137); + _curvea0[283] = _7829; + uint16_t _7830 = (uint16_t)(137); + _curvea0[284] = _7830; + uint16_t _7831 = (uint16_t)(137); + _curvea0[285] = _7831; + uint16_t _7832 = (uint16_t)(138); + _curvea0[286] = _7832; + uint16_t _7833 = (uint16_t)(138); + _curvea0[287] = _7833; + uint16_t _7834 = (uint16_t)(138); + _curvea0[288] = _7834; + uint16_t _7835 = (uint16_t)(139); + _curvea0[289] = _7835; + uint16_t _7836 = (uint16_t)(139); + _curvea0[290] = _7836; + uint16_t _7837 = (uint16_t)(139); + _curvea0[291] = _7837; + uint16_t _7838 = (uint16_t)(140); + _curvea0[292] = _7838; + uint16_t _7839 = (uint16_t)(140); + _curvea0[293] = _7839; + uint16_t _7840 = (uint16_t)(140); + _curvea0[294] = _7840; + uint16_t _7841 = (uint16_t)(141); + _curvea0[295] = _7841; + uint16_t _7842 = (uint16_t)(141); + _curvea0[296] = _7842; + uint16_t _7843 = (uint16_t)(141); + _curvea0[297] = _7843; + uint16_t _7844 = (uint16_t)(141); + _curvea0[298] = _7844; + uint16_t _7845 = (uint16_t)(142); + _curvea0[299] = _7845; + uint16_t _7846 = (uint16_t)(142); + _curvea0[300] = _7846; + uint16_t _7847 = (uint16_t)(142); + _curvea0[301] = _7847; + uint16_t _7848 = (uint16_t)(143); + _curvea0[302] = _7848; + uint16_t _7849 = (uint16_t)(143); + _curvea0[303] = _7849; + uint16_t _7850 = (uint16_t)(143); + _curvea0[304] = _7850; + uint16_t _7851 = (uint16_t)(144); + _curvea0[305] = _7851; + uint16_t _7852 = (uint16_t)(144); + _curvea0[306] = _7852; + uint16_t _7853 = (uint16_t)(144); + _curvea0[307] = _7853; + uint16_t _7854 = (uint16_t)(145); + _curvea0[308] = _7854; + uint16_t _7855 = (uint16_t)(145); + _curvea0[309] = _7855; + uint16_t _7856 = (uint16_t)(145); + _curvea0[310] = _7856; + uint16_t _7857 = (uint16_t)(145); + _curvea0[311] = _7857; + uint16_t _7858 = (uint16_t)(146); + _curvea0[312] = _7858; + uint16_t _7859 = (uint16_t)(146); + _curvea0[313] = _7859; + uint16_t _7860 = (uint16_t)(146); + _curvea0[314] = _7860; + uint16_t _7861 = (uint16_t)(147); + _curvea0[315] = _7861; + uint16_t _7862 = (uint16_t)(147); + _curvea0[316] = _7862; + uint16_t _7863 = (uint16_t)(147); + _curvea0[317] = _7863; + uint16_t _7864 = (uint16_t)(148); + _curvea0[318] = _7864; + uint16_t _7865 = (uint16_t)(148); + _curvea0[319] = _7865; + uint16_t _7866 = (uint16_t)(148); + _curvea0[320] = _7866; + uint16_t _7867 = (uint16_t)(148); + _curvea0[321] = _7867; + uint16_t _7868 = (uint16_t)(149); + _curvea0[322] = _7868; + uint16_t _7869 = (uint16_t)(149); + _curvea0[323] = _7869; + uint16_t _7870 = (uint16_t)(149); + _curvea0[324] = _7870; + uint16_t _7871 = (uint16_t)(150); + _curvea0[325] = _7871; + uint16_t _7872 = (uint16_t)(150); + _curvea0[326] = _7872; + uint16_t _7873 = (uint16_t)(150); + _curvea0[327] = _7873; + uint16_t _7874 = (uint16_t)(150); + _curvea0[328] = _7874; + uint16_t _7875 = (uint16_t)(151); + _curvea0[329] = _7875; + uint16_t _7876 = (uint16_t)(151); + _curvea0[330] = _7876; + uint16_t _7877 = (uint16_t)(151); + _curvea0[331] = _7877; + uint16_t _7878 = (uint16_t)(152); + _curvea0[332] = _7878; + uint16_t _7879 = (uint16_t)(152); + _curvea0[333] = _7879; + uint16_t _7880 = (uint16_t)(152); + _curvea0[334] = _7880; + uint16_t _7881 = (uint16_t)(152); + _curvea0[335] = _7881; + uint16_t _7882 = (uint16_t)(153); + _curvea0[336] = _7882; + uint16_t _7883 = (uint16_t)(153); + _curvea0[337] = _7883; + uint16_t _7884 = (uint16_t)(153); + _curvea0[338] = _7884; + uint16_t _7885 = (uint16_t)(154); + _curvea0[339] = _7885; + uint16_t _7886 = (uint16_t)(154); + _curvea0[340] = _7886; + uint16_t _7887 = (uint16_t)(154); + _curvea0[341] = _7887; + uint16_t _7888 = (uint16_t)(154); + _curvea0[342] = _7888; + uint16_t _7889 = (uint16_t)(155); + _curvea0[343] = _7889; + uint16_t _7890 = (uint16_t)(155); + _curvea0[344] = _7890; + uint16_t _7891 = (uint16_t)(155); + _curvea0[345] = _7891; + uint16_t _7892 = (uint16_t)(156); + _curvea0[346] = _7892; + uint16_t _7893 = (uint16_t)(156); + _curvea0[347] = _7893; + uint16_t _7894 = (uint16_t)(156); + _curvea0[348] = _7894; + uint16_t _7895 = (uint16_t)(156); + _curvea0[349] = _7895; + uint16_t _7896 = (uint16_t)(157); + _curvea0[350] = _7896; + uint16_t _7897 = (uint16_t)(157); + _curvea0[351] = _7897; + uint16_t _7898 = (uint16_t)(157); + _curvea0[352] = _7898; + uint16_t _7899 = (uint16_t)(157); + _curvea0[353] = _7899; + uint16_t _7900 = (uint16_t)(158); + _curvea0[354] = _7900; + uint16_t _7901 = (uint16_t)(158); + _curvea0[355] = _7901; + uint16_t _7902 = (uint16_t)(158); + _curvea0[356] = _7902; + uint16_t _7903 = (uint16_t)(159); + _curvea0[357] = _7903; + uint16_t _7904 = (uint16_t)(159); + _curvea0[358] = _7904; + uint16_t _7905 = (uint16_t)(159); + _curvea0[359] = _7905; + uint16_t _7906 = (uint16_t)(159); + _curvea0[360] = _7906; + uint16_t _7907 = (uint16_t)(160); + _curvea0[361] = _7907; + uint16_t _7908 = (uint16_t)(160); + _curvea0[362] = _7908; + uint16_t _7909 = (uint16_t)(160); + _curvea0[363] = _7909; + uint16_t _7910 = (uint16_t)(160); + _curvea0[364] = _7910; + uint16_t _7911 = (uint16_t)(161); + _curvea0[365] = _7911; + uint16_t _7912 = (uint16_t)(161); + _curvea0[366] = _7912; + uint16_t _7913 = (uint16_t)(161); + _curvea0[367] = _7913; + uint16_t _7914 = (uint16_t)(161); + _curvea0[368] = _7914; + uint16_t _7915 = (uint16_t)(162); + _curvea0[369] = _7915; + uint16_t _7916 = (uint16_t)(162); + _curvea0[370] = _7916; + uint16_t _7917 = (uint16_t)(162); + _curvea0[371] = _7917; + uint16_t _7918 = (uint16_t)(162); + _curvea0[372] = _7918; + uint16_t _7919 = (uint16_t)(163); + _curvea0[373] = _7919; + uint16_t _7920 = (uint16_t)(163); + _curvea0[374] = _7920; + uint16_t _7921 = (uint16_t)(163); + _curvea0[375] = _7921; + uint16_t _7922 = (uint16_t)(163); + _curvea0[376] = _7922; + uint16_t _7923 = (uint16_t)(164); + _curvea0[377] = _7923; + uint16_t _7924 = (uint16_t)(164); + _curvea0[378] = _7924; + uint16_t _7925 = (uint16_t)(164); + _curvea0[379] = _7925; + uint16_t _7926 = (uint16_t)(164); + _curvea0[380] = _7926; + uint16_t _7927 = (uint16_t)(165); + _curvea0[381] = _7927; + uint16_t _7928 = (uint16_t)(165); + _curvea0[382] = _7928; + uint16_t _7929 = (uint16_t)(165); + _curvea0[383] = _7929; + uint16_t _7930 = (uint16_t)(166); + _curvea0[384] = _7930; + uint16_t _7931 = (uint16_t)(166); + _curvea0[385] = _7931; + uint16_t _7932 = (uint16_t)(166); + _curvea0[386] = _7932; + uint16_t _7933 = (uint16_t)(166); + _curvea0[387] = _7933; + uint16_t _7934 = (uint16_t)(167); + _curvea0[388] = _7934; + uint16_t _7935 = (uint16_t)(167); + _curvea0[389] = _7935; + uint16_t _7936 = (uint16_t)(167); + _curvea0[390] = _7936; + uint16_t _7937 = (uint16_t)(167); + _curvea0[391] = _7937; + uint16_t _7938 = (uint16_t)(167); + _curvea0[392] = _7938; + uint16_t _7939 = (uint16_t)(168); + _curvea0[393] = _7939; + uint16_t _7940 = (uint16_t)(168); + _curvea0[394] = _7940; + uint16_t _7941 = (uint16_t)(168); + _curvea0[395] = _7941; + uint16_t _7942 = (uint16_t)(168); + _curvea0[396] = _7942; + uint16_t _7943 = (uint16_t)(169); + _curvea0[397] = _7943; + uint16_t _7944 = (uint16_t)(169); + _curvea0[398] = _7944; + uint16_t _7945 = (uint16_t)(169); + _curvea0[399] = _7945; + uint16_t _7946 = (uint16_t)(169); + _curvea0[400] = _7946; + uint16_t _7947 = (uint16_t)(170); + _curvea0[401] = _7947; + uint16_t _7948 = (uint16_t)(170); + _curvea0[402] = _7948; + uint16_t _7949 = (uint16_t)(170); + _curvea0[403] = _7949; + uint16_t _7950 = (uint16_t)(170); + _curvea0[404] = _7950; + uint16_t _7951 = (uint16_t)(171); + _curvea0[405] = _7951; + uint16_t _7952 = (uint16_t)(171); + _curvea0[406] = _7952; + uint16_t _7953 = (uint16_t)(171); + _curvea0[407] = _7953; + uint16_t _7954 = (uint16_t)(171); + _curvea0[408] = _7954; + uint16_t _7955 = (uint16_t)(172); + _curvea0[409] = _7955; + uint16_t _7956 = (uint16_t)(172); + _curvea0[410] = _7956; + uint16_t _7957 = (uint16_t)(172); + _curvea0[411] = _7957; + uint16_t _7958 = (uint16_t)(172); + _curvea0[412] = _7958; + uint16_t _7959 = (uint16_t)(173); + _curvea0[413] = _7959; + uint16_t _7960 = (uint16_t)(173); + _curvea0[414] = _7960; + uint16_t _7961 = (uint16_t)(173); + _curvea0[415] = _7961; + uint16_t _7962 = (uint16_t)(173); + _curvea0[416] = _7962; + uint16_t _7963 = (uint16_t)(173); + _curvea0[417] = _7963; + uint16_t _7964 = (uint16_t)(174); + _curvea0[418] = _7964; + uint16_t _7965 = (uint16_t)(174); + _curvea0[419] = _7965; + uint16_t _7966 = (uint16_t)(174); + _curvea0[420] = _7966; + uint16_t _7967 = (uint16_t)(174); + _curvea0[421] = _7967; + uint16_t _7968 = (uint16_t)(175); + _curvea0[422] = _7968; + uint16_t _7969 = (uint16_t)(175); + _curvea0[423] = _7969; + uint16_t _7970 = (uint16_t)(175); + _curvea0[424] = _7970; + uint16_t _7971 = (uint16_t)(175); + _curvea0[425] = _7971; + uint16_t _7972 = (uint16_t)(176); + _curvea0[426] = _7972; + uint16_t _7973 = (uint16_t)(176); + _curvea0[427] = _7973; + uint16_t _7974 = (uint16_t)(176); + _curvea0[428] = _7974; + uint16_t _7975 = (uint16_t)(176); + _curvea0[429] = _7975; + uint16_t _7976 = (uint16_t)(176); + _curvea0[430] = _7976; + uint16_t _7977 = (uint16_t)(177); + _curvea0[431] = _7977; + uint16_t _7978 = (uint16_t)(177); + _curvea0[432] = _7978; + uint16_t _7979 = (uint16_t)(177); + _curvea0[433] = _7979; + uint16_t _7980 = (uint16_t)(177); + _curvea0[434] = _7980; + uint16_t _7981 = (uint16_t)(178); + _curvea0[435] = _7981; + uint16_t _7982 = (uint16_t)(178); + _curvea0[436] = _7982; + uint16_t _7983 = (uint16_t)(178); + _curvea0[437] = _7983; + uint16_t _7984 = (uint16_t)(178); + _curvea0[438] = _7984; + uint16_t _7985 = (uint16_t)(178); + _curvea0[439] = _7985; + uint16_t _7986 = (uint16_t)(179); + _curvea0[440] = _7986; + uint16_t _7987 = (uint16_t)(179); + _curvea0[441] = _7987; + uint16_t _7988 = (uint16_t)(179); + _curvea0[442] = _7988; + uint16_t _7989 = (uint16_t)(179); + _curvea0[443] = _7989; + uint16_t _7990 = (uint16_t)(180); + _curvea0[444] = _7990; + uint16_t _7991 = (uint16_t)(180); + _curvea0[445] = _7991; + uint16_t _7992 = (uint16_t)(180); + _curvea0[446] = _7992; + uint16_t _7993 = (uint16_t)(180); + _curvea0[447] = _7993; + uint16_t _7994 = (uint16_t)(180); + _curvea0[448] = _7994; + uint16_t _7995 = (uint16_t)(181); + _curvea0[449] = _7995; + uint16_t _7996 = (uint16_t)(181); + _curvea0[450] = _7996; + uint16_t _7997 = (uint16_t)(181); + _curvea0[451] = _7997; + uint16_t _7998 = (uint16_t)(181); + _curvea0[452] = _7998; + uint16_t _7999 = (uint16_t)(181); + _curvea0[453] = _7999; + uint16_t _8000 = (uint16_t)(182); + _curvea0[454] = _8000; + uint16_t _8001 = (uint16_t)(182); + _curvea0[455] = _8001; + uint16_t _8002 = (uint16_t)(182); + _curvea0[456] = _8002; + uint16_t _8003 = (uint16_t)(182); + _curvea0[457] = _8003; + uint16_t _8004 = (uint16_t)(183); + _curvea0[458] = _8004; + uint16_t _8005 = (uint16_t)(183); + _curvea0[459] = _8005; + uint16_t _8006 = (uint16_t)(183); + _curvea0[460] = _8006; + uint16_t _8007 = (uint16_t)(183); + _curvea0[461] = _8007; + uint16_t _8008 = (uint16_t)(183); + _curvea0[462] = _8008; + uint16_t _8009 = (uint16_t)(184); + _curvea0[463] = _8009; + uint16_t _8010 = (uint16_t)(184); + _curvea0[464] = _8010; + uint16_t _8011 = (uint16_t)(184); + _curvea0[465] = _8011; + uint16_t _8012 = (uint16_t)(184); + _curvea0[466] = _8012; + uint16_t _8013 = (uint16_t)(184); + _curvea0[467] = _8013; + uint16_t _8014 = (uint16_t)(185); + _curvea0[468] = _8014; + uint16_t _8015 = (uint16_t)(185); + _curvea0[469] = _8015; + uint16_t _8016 = (uint16_t)(185); + _curvea0[470] = _8016; + uint16_t _8017 = (uint16_t)(185); + _curvea0[471] = _8017; + uint16_t _8018 = (uint16_t)(185); + _curvea0[472] = _8018; + uint16_t _8019 = (uint16_t)(186); + _curvea0[473] = _8019; + uint16_t _8020 = (uint16_t)(186); + _curvea0[474] = _8020; + uint16_t _8021 = (uint16_t)(186); + _curvea0[475] = _8021; + uint16_t _8022 = (uint16_t)(186); + _curvea0[476] = _8022; + uint16_t _8023 = (uint16_t)(187); + _curvea0[477] = _8023; + uint16_t _8024 = (uint16_t)(187); + _curvea0[478] = _8024; + uint16_t _8025 = (uint16_t)(187); + _curvea0[479] = _8025; + uint16_t _8026 = (uint16_t)(187); + _curvea0[480] = _8026; + uint16_t _8027 = (uint16_t)(187); + _curvea0[481] = _8027; + uint16_t _8028 = (uint16_t)(188); + _curvea0[482] = _8028; + uint16_t _8029 = (uint16_t)(188); + _curvea0[483] = _8029; + uint16_t _8030 = (uint16_t)(188); + _curvea0[484] = _8030; + uint16_t _8031 = (uint16_t)(188); + _curvea0[485] = _8031; + uint16_t _8032 = (uint16_t)(188); + _curvea0[486] = _8032; + uint16_t _8033 = (uint16_t)(189); + _curvea0[487] = _8033; + uint16_t _8034 = (uint16_t)(189); + _curvea0[488] = _8034; + uint16_t _8035 = (uint16_t)(189); + _curvea0[489] = _8035; + uint16_t _8036 = (uint16_t)(189); + _curvea0[490] = _8036; + uint16_t _8037 = (uint16_t)(189); + _curvea0[491] = _8037; + uint16_t _8038 = (uint16_t)(190); + _curvea0[492] = _8038; + uint16_t _8039 = (uint16_t)(190); + _curvea0[493] = _8039; + uint16_t _8040 = (uint16_t)(190); + _curvea0[494] = _8040; + uint16_t _8041 = (uint16_t)(190); + _curvea0[495] = _8041; + uint16_t _8042 = (uint16_t)(190); + _curvea0[496] = _8042; + uint16_t _8043 = (uint16_t)(190); + _curvea0[497] = _8043; + uint16_t _8044 = (uint16_t)(191); + _curvea0[498] = _8044; + uint16_t _8045 = (uint16_t)(191); + _curvea0[499] = _8045; + uint16_t _8046 = (uint16_t)(191); + _curvea0[500] = _8046; + uint16_t _8047 = (uint16_t)(191); + _curvea0[501] = _8047; + uint16_t _8048 = (uint16_t)(191); + _curvea0[502] = _8048; + uint16_t _8049 = (uint16_t)(192); + _curvea0[503] = _8049; + uint16_t _8050 = (uint16_t)(192); + _curvea0[504] = _8050; + uint16_t _8051 = (uint16_t)(192); + _curvea0[505] = _8051; + uint16_t _8052 = (uint16_t)(192); + _curvea0[506] = _8052; + uint16_t _8053 = (uint16_t)(192); + _curvea0[507] = _8053; + uint16_t _8054 = (uint16_t)(193); + _curvea0[508] = _8054; + uint16_t _8055 = (uint16_t)(193); + _curvea0[509] = _8055; + uint16_t _8056 = (uint16_t)(193); + _curvea0[510] = _8056; + uint16_t _8057 = (uint16_t)(193); + _curvea0[511] = _8057; + uint16_t _8058 = (uint16_t)(193); + _curvea0[512] = _8058; + uint16_t _8059 = (uint16_t)(194); + _curvea0[513] = _8059; + uint16_t _8060 = (uint16_t)(194); + _curvea0[514] = _8060; + uint16_t _8061 = (uint16_t)(194); + _curvea0[515] = _8061; + uint16_t _8062 = (uint16_t)(194); + _curvea0[516] = _8062; + uint16_t _8063 = (uint16_t)(194); + _curvea0[517] = _8063; + uint16_t _8064 = (uint16_t)(195); + _curvea0[518] = _8064; + uint16_t _8065 = (uint16_t)(195); + _curvea0[519] = _8065; + uint16_t _8066 = (uint16_t)(195); + _curvea0[520] = _8066; + uint16_t _8067 = (uint16_t)(195); + _curvea0[521] = _8067; + uint16_t _8068 = (uint16_t)(195); + _curvea0[522] = _8068; + uint16_t _8069 = (uint16_t)(195); + _curvea0[523] = _8069; + uint16_t _8070 = (uint16_t)(196); + _curvea0[524] = _8070; + uint16_t _8071 = (uint16_t)(196); + _curvea0[525] = _8071; + uint16_t _8072 = (uint16_t)(196); + _curvea0[526] = _8072; + uint16_t _8073 = (uint16_t)(196); + _curvea0[527] = _8073; + uint16_t _8074 = (uint16_t)(196); + _curvea0[528] = _8074; + uint16_t _8075 = (uint16_t)(197); + _curvea0[529] = _8075; + uint16_t _8076 = (uint16_t)(197); + _curvea0[530] = _8076; + uint16_t _8077 = (uint16_t)(197); + _curvea0[531] = _8077; + uint16_t _8078 = (uint16_t)(197); + _curvea0[532] = _8078; + uint16_t _8079 = (uint16_t)(197); + _curvea0[533] = _8079; + uint16_t _8080 = (uint16_t)(197); + _curvea0[534] = _8080; + uint16_t _8081 = (uint16_t)(198); + _curvea0[535] = _8081; + uint16_t _8082 = (uint16_t)(198); + _curvea0[536] = _8082; + uint16_t _8083 = (uint16_t)(198); + _curvea0[537] = _8083; + uint16_t _8084 = (uint16_t)(198); + _curvea0[538] = _8084; + uint16_t _8085 = (uint16_t)(198); + _curvea0[539] = _8085; + uint16_t _8086 = (uint16_t)(199); + _curvea0[540] = _8086; + uint16_t _8087 = (uint16_t)(199); + _curvea0[541] = _8087; + uint16_t _8088 = (uint16_t)(199); + _curvea0[542] = _8088; + uint16_t _8089 = (uint16_t)(199); + _curvea0[543] = _8089; + uint16_t _8090 = (uint16_t)(199); + _curvea0[544] = _8090; + uint16_t _8091 = (uint16_t)(199); + _curvea0[545] = _8091; + uint16_t _8092 = (uint16_t)(200); + _curvea0[546] = _8092; + uint16_t _8093 = (uint16_t)(200); + _curvea0[547] = _8093; + uint16_t _8094 = (uint16_t)(200); + _curvea0[548] = _8094; + uint16_t _8095 = (uint16_t)(200); + _curvea0[549] = _8095; + uint16_t _8096 = (uint16_t)(200); + _curvea0[550] = _8096; + uint16_t _8097 = (uint16_t)(200); + _curvea0[551] = _8097; + uint16_t _8098 = (uint16_t)(201); + _curvea0[552] = _8098; + uint16_t _8099 = (uint16_t)(201); + _curvea0[553] = _8099; + uint16_t _8100 = (uint16_t)(201); + _curvea0[554] = _8100; + uint16_t _8101 = (uint16_t)(201); + _curvea0[555] = _8101; + uint16_t _8102 = (uint16_t)(201); + _curvea0[556] = _8102; + uint16_t _8103 = (uint16_t)(202); + _curvea0[557] = _8103; + uint16_t _8104 = (uint16_t)(202); + _curvea0[558] = _8104; + uint16_t _8105 = (uint16_t)(202); + _curvea0[559] = _8105; + uint16_t _8106 = (uint16_t)(202); + _curvea0[560] = _8106; + uint16_t _8107 = (uint16_t)(202); + _curvea0[561] = _8107; + uint16_t _8108 = (uint16_t)(202); + _curvea0[562] = _8108; + uint16_t _8109 = (uint16_t)(203); + _curvea0[563] = _8109; + uint16_t _8110 = (uint16_t)(203); + _curvea0[564] = _8110; + uint16_t _8111 = (uint16_t)(203); + _curvea0[565] = _8111; + uint16_t _8112 = (uint16_t)(203); + _curvea0[566] = _8112; + uint16_t _8113 = (uint16_t)(203); + _curvea0[567] = _8113; + uint16_t _8114 = (uint16_t)(203); + _curvea0[568] = _8114; + uint16_t _8115 = (uint16_t)(204); + _curvea0[569] = _8115; + uint16_t _8116 = (uint16_t)(204); + _curvea0[570] = _8116; + uint16_t _8117 = (uint16_t)(204); + _curvea0[571] = _8117; + uint16_t _8118 = (uint16_t)(204); + _curvea0[572] = _8118; + uint16_t _8119 = (uint16_t)(204); + _curvea0[573] = _8119; + uint16_t _8120 = (uint16_t)(204); + _curvea0[574] = _8120; + uint16_t _8121 = (uint16_t)(205); + _curvea0[575] = _8121; + uint16_t _8122 = (uint16_t)(205); + _curvea0[576] = _8122; + uint16_t _8123 = (uint16_t)(205); + _curvea0[577] = _8123; + uint16_t _8124 = (uint16_t)(205); + _curvea0[578] = _8124; + uint16_t _8125 = (uint16_t)(205); + _curvea0[579] = _8125; + uint16_t _8126 = (uint16_t)(205); + _curvea0[580] = _8126; + uint16_t _8127 = (uint16_t)(206); + _curvea0[581] = _8127; + uint16_t _8128 = (uint16_t)(206); + _curvea0[582] = _8128; + uint16_t _8129 = (uint16_t)(206); + _curvea0[583] = _8129; + uint16_t _8130 = (uint16_t)(206); + _curvea0[584] = _8130; + uint16_t _8131 = (uint16_t)(206); + _curvea0[585] = _8131; + uint16_t _8132 = (uint16_t)(206); + _curvea0[586] = _8132; + uint16_t _8133 = (uint16_t)(207); + _curvea0[587] = _8133; + uint16_t _8134 = (uint16_t)(207); + _curvea0[588] = _8134; + uint16_t _8135 = (uint16_t)(207); + _curvea0[589] = _8135; + uint16_t _8136 = (uint16_t)(207); + _curvea0[590] = _8136; + uint16_t _8137 = (uint16_t)(207); + _curvea0[591] = _8137; + uint16_t _8138 = (uint16_t)(207); + _curvea0[592] = _8138; + uint16_t _8139 = (uint16_t)(208); + _curvea0[593] = _8139; + uint16_t _8140 = (uint16_t)(208); + _curvea0[594] = _8140; + uint16_t _8141 = (uint16_t)(208); + _curvea0[595] = _8141; + uint16_t _8142 = (uint16_t)(208); + _curvea0[596] = _8142; + uint16_t _8143 = (uint16_t)(208); + _curvea0[597] = _8143; + uint16_t _8144 = (uint16_t)(208); + _curvea0[598] = _8144; + uint16_t _8145 = (uint16_t)(209); + _curvea0[599] = _8145; + uint16_t _8146 = (uint16_t)(209); + _curvea0[600] = _8146; + uint16_t _8147 = (uint16_t)(209); + _curvea0[601] = _8147; + uint16_t _8148 = (uint16_t)(209); + _curvea0[602] = _8148; + uint16_t _8149 = (uint16_t)(209); + _curvea0[603] = _8149; + uint16_t _8150 = (uint16_t)(209); + _curvea0[604] = _8150; + uint16_t _8151 = (uint16_t)(209); + _curvea0[605] = _8151; + uint16_t _8152 = (uint16_t)(210); + _curvea0[606] = _8152; + uint16_t _8153 = (uint16_t)(210); + _curvea0[607] = _8153; + uint16_t _8154 = (uint16_t)(210); + _curvea0[608] = _8154; + uint16_t _8155 = (uint16_t)(210); + _curvea0[609] = _8155; + uint16_t _8156 = (uint16_t)(210); + _curvea0[610] = _8156; + uint16_t _8157 = (uint16_t)(210); + _curvea0[611] = _8157; + uint16_t _8158 = (uint16_t)(211); + _curvea0[612] = _8158; + uint16_t _8159 = (uint16_t)(211); + _curvea0[613] = _8159; + uint16_t _8160 = (uint16_t)(211); + _curvea0[614] = _8160; + uint16_t _8161 = (uint16_t)(211); + _curvea0[615] = _8161; + uint16_t _8162 = (uint16_t)(211); + _curvea0[616] = _8162; + uint16_t _8163 = (uint16_t)(211); + _curvea0[617] = _8163; + uint16_t _8164 = (uint16_t)(211); + _curvea0[618] = _8164; + uint16_t _8165 = (uint16_t)(212); + _curvea0[619] = _8165; + uint16_t _8166 = (uint16_t)(212); + _curvea0[620] = _8166; + uint16_t _8167 = (uint16_t)(212); + _curvea0[621] = _8167; + uint16_t _8168 = (uint16_t)(212); + _curvea0[622] = _8168; + uint16_t _8169 = (uint16_t)(212); + _curvea0[623] = _8169; + uint16_t _8170 = (uint16_t)(212); + _curvea0[624] = _8170; + uint16_t _8171 = (uint16_t)(213); + _curvea0[625] = _8171; + uint16_t _8172 = (uint16_t)(213); + _curvea0[626] = _8172; + uint16_t _8173 = (uint16_t)(213); + _curvea0[627] = _8173; + uint16_t _8174 = (uint16_t)(213); + _curvea0[628] = _8174; + uint16_t _8175 = (uint16_t)(213); + _curvea0[629] = _8175; + uint16_t _8176 = (uint16_t)(213); + _curvea0[630] = _8176; + uint16_t _8177 = (uint16_t)(213); + _curvea0[631] = _8177; + uint16_t _8178 = (uint16_t)(214); + _curvea0[632] = _8178; + uint16_t _8179 = (uint16_t)(214); + _curvea0[633] = _8179; + uint16_t _8180 = (uint16_t)(214); + _curvea0[634] = _8180; + uint16_t _8181 = (uint16_t)(214); + _curvea0[635] = _8181; + uint16_t _8182 = (uint16_t)(214); + _curvea0[636] = _8182; + uint16_t _8183 = (uint16_t)(214); + _curvea0[637] = _8183; + uint16_t _8184 = (uint16_t)(214); + _curvea0[638] = _8184; + uint16_t _8185 = (uint16_t)(215); + _curvea0[639] = _8185; + uint16_t _8186 = (uint16_t)(215); + _curvea0[640] = _8186; + uint16_t _8187 = (uint16_t)(215); + _curvea0[641] = _8187; + uint16_t _8188 = (uint16_t)(215); + _curvea0[642] = _8188; + uint16_t _8189 = (uint16_t)(215); + _curvea0[643] = _8189; + uint16_t _8190 = (uint16_t)(215); + _curvea0[644] = _8190; + uint16_t _8191 = (uint16_t)(216); + _curvea0[645] = _8191; + uint16_t _8192 = (uint16_t)(216); + _curvea0[646] = _8192; + uint16_t _8193 = (uint16_t)(216); + _curvea0[647] = _8193; + uint16_t _8194 = (uint16_t)(216); + _curvea0[648] = _8194; + uint16_t _8195 = (uint16_t)(216); + _curvea0[649] = _8195; + uint16_t _8196 = (uint16_t)(216); + _curvea0[650] = _8196; + uint16_t _8197 = (uint16_t)(216); + _curvea0[651] = _8197; + uint16_t _8198 = (uint16_t)(217); + _curvea0[652] = _8198; + uint16_t _8199 = (uint16_t)(217); + _curvea0[653] = _8199; + uint16_t _8200 = (uint16_t)(217); + _curvea0[654] = _8200; + uint16_t _8201 = (uint16_t)(217); + _curvea0[655] = _8201; + uint16_t _8202 = (uint16_t)(217); + _curvea0[656] = _8202; + uint16_t _8203 = (uint16_t)(217); + _curvea0[657] = _8203; + uint16_t _8204 = (uint16_t)(217); + _curvea0[658] = _8204; + uint16_t _8205 = (uint16_t)(218); + _curvea0[659] = _8205; + uint16_t _8206 = (uint16_t)(218); + _curvea0[660] = _8206; + uint16_t _8207 = (uint16_t)(218); + _curvea0[661] = _8207; + uint16_t _8208 = (uint16_t)(218); + _curvea0[662] = _8208; + uint16_t _8209 = (uint16_t)(218); + _curvea0[663] = _8209; + uint16_t _8210 = (uint16_t)(218); + _curvea0[664] = _8210; + uint16_t _8211 = (uint16_t)(218); + _curvea0[665] = _8211; + uint16_t _8212 = (uint16_t)(219); + _curvea0[666] = _8212; + uint16_t _8213 = (uint16_t)(219); + _curvea0[667] = _8213; + uint16_t _8214 = (uint16_t)(219); + _curvea0[668] = _8214; + uint16_t _8215 = (uint16_t)(219); + _curvea0[669] = _8215; + uint16_t _8216 = (uint16_t)(219); + _curvea0[670] = _8216; + uint16_t _8217 = (uint16_t)(219); + _curvea0[671] = _8217; + uint16_t _8218 = (uint16_t)(219); + _curvea0[672] = _8218; + uint16_t _8219 = (uint16_t)(220); + _curvea0[673] = _8219; + uint16_t _8220 = (uint16_t)(220); + _curvea0[674] = _8220; + uint16_t _8221 = (uint16_t)(220); + _curvea0[675] = _8221; + uint16_t _8222 = (uint16_t)(220); + _curvea0[676] = _8222; + uint16_t _8223 = (uint16_t)(220); + _curvea0[677] = _8223; + uint16_t _8224 = (uint16_t)(220); + _curvea0[678] = _8224; + uint16_t _8225 = (uint16_t)(220); + _curvea0[679] = _8225; + uint16_t _8226 = (uint16_t)(220); + _curvea0[680] = _8226; + uint16_t _8227 = (uint16_t)(221); + _curvea0[681] = _8227; + uint16_t _8228 = (uint16_t)(221); + _curvea0[682] = _8228; + uint16_t _8229 = (uint16_t)(221); + _curvea0[683] = _8229; + uint16_t _8230 = (uint16_t)(221); + _curvea0[684] = _8230; + uint16_t _8231 = (uint16_t)(221); + _curvea0[685] = _8231; + uint16_t _8232 = (uint16_t)(221); + _curvea0[686] = _8232; + uint16_t _8233 = (uint16_t)(221); + _curvea0[687] = _8233; + uint16_t _8234 = (uint16_t)(222); + _curvea0[688] = _8234; + uint16_t _8235 = (uint16_t)(222); + _curvea0[689] = _8235; + uint16_t _8236 = (uint16_t)(222); + _curvea0[690] = _8236; + uint16_t _8237 = (uint16_t)(222); + _curvea0[691] = _8237; + uint16_t _8238 = (uint16_t)(222); + _curvea0[692] = _8238; + uint16_t _8239 = (uint16_t)(222); + _curvea0[693] = _8239; + uint16_t _8240 = (uint16_t)(222); + _curvea0[694] = _8240; + uint16_t _8241 = (uint16_t)(223); + _curvea0[695] = _8241; + uint16_t _8242 = (uint16_t)(223); + _curvea0[696] = _8242; + uint16_t _8243 = (uint16_t)(223); + _curvea0[697] = _8243; + uint16_t _8244 = (uint16_t)(223); + _curvea0[698] = _8244; + uint16_t _8245 = (uint16_t)(223); + _curvea0[699] = _8245; + uint16_t _8246 = (uint16_t)(223); + _curvea0[700] = _8246; + uint16_t _8247 = (uint16_t)(223); + _curvea0[701] = _8247; + uint16_t _8248 = (uint16_t)(223); + _curvea0[702] = _8248; + uint16_t _8249 = (uint16_t)(224); + _curvea0[703] = _8249; + uint16_t _8250 = (uint16_t)(224); + _curvea0[704] = _8250; + uint16_t _8251 = (uint16_t)(224); + _curvea0[705] = _8251; + uint16_t _8252 = (uint16_t)(224); + _curvea0[706] = _8252; + uint16_t _8253 = (uint16_t)(224); + _curvea0[707] = _8253; + uint16_t _8254 = (uint16_t)(224); + _curvea0[708] = _8254; + uint16_t _8255 = (uint16_t)(224); + _curvea0[709] = _8255; + uint16_t _8256 = (uint16_t)(224); + _curvea0[710] = _8256; + uint16_t _8257 = (uint16_t)(225); + _curvea0[711] = _8257; + uint16_t _8258 = (uint16_t)(225); + _curvea0[712] = _8258; + uint16_t _8259 = (uint16_t)(225); + _curvea0[713] = _8259; + uint16_t _8260 = (uint16_t)(225); + _curvea0[714] = _8260; + uint16_t _8261 = (uint16_t)(225); + _curvea0[715] = _8261; + uint16_t _8262 = (uint16_t)(225); + _curvea0[716] = _8262; + uint16_t _8263 = (uint16_t)(225); + _curvea0[717] = _8263; + uint16_t _8264 = (uint16_t)(226); + _curvea0[718] = _8264; + uint16_t _8265 = (uint16_t)(226); + _curvea0[719] = _8265; + uint16_t _8266 = (uint16_t)(226); + _curvea0[720] = _8266; + uint16_t _8267 = (uint16_t)(226); + _curvea0[721] = _8267; + uint16_t _8268 = (uint16_t)(226); + _curvea0[722] = _8268; + uint16_t _8269 = (uint16_t)(226); + _curvea0[723] = _8269; + uint16_t _8270 = (uint16_t)(226); + _curvea0[724] = _8270; + uint16_t _8271 = (uint16_t)(226); + _curvea0[725] = _8271; + uint16_t _8272 = (uint16_t)(227); + _curvea0[726] = _8272; + uint16_t _8273 = (uint16_t)(227); + _curvea0[727] = _8273; + uint16_t _8274 = (uint16_t)(227); + _curvea0[728] = _8274; + uint16_t _8275 = (uint16_t)(227); + _curvea0[729] = _8275; + uint16_t _8276 = (uint16_t)(227); + _curvea0[730] = _8276; + uint16_t _8277 = (uint16_t)(227); + _curvea0[731] = _8277; + uint16_t _8278 = (uint16_t)(227); + _curvea0[732] = _8278; + uint16_t _8279 = (uint16_t)(227); + _curvea0[733] = _8279; + uint16_t _8280 = (uint16_t)(228); + _curvea0[734] = _8280; + uint16_t _8281 = (uint16_t)(228); + _curvea0[735] = _8281; + uint16_t _8282 = (uint16_t)(228); + _curvea0[736] = _8282; + uint16_t _8283 = (uint16_t)(228); + _curvea0[737] = _8283; + uint16_t _8284 = (uint16_t)(228); + _curvea0[738] = _8284; + uint16_t _8285 = (uint16_t)(228); + _curvea0[739] = _8285; + uint16_t _8286 = (uint16_t)(228); + _curvea0[740] = _8286; + uint16_t _8287 = (uint16_t)(228); + _curvea0[741] = _8287; + uint16_t _8288 = (uint16_t)(228); + _curvea0[742] = _8288; + uint16_t _8289 = (uint16_t)(229); + _curvea0[743] = _8289; + uint16_t _8290 = (uint16_t)(229); + _curvea0[744] = _8290; + uint16_t _8291 = (uint16_t)(229); + _curvea0[745] = _8291; + uint16_t _8292 = (uint16_t)(229); + _curvea0[746] = _8292; + uint16_t _8293 = (uint16_t)(229); + _curvea0[747] = _8293; + uint16_t _8294 = (uint16_t)(229); + _curvea0[748] = _8294; + uint16_t _8295 = (uint16_t)(229); + _curvea0[749] = _8295; + uint16_t _8296 = (uint16_t)(229); + _curvea0[750] = _8296; + uint16_t _8297 = (uint16_t)(230); + _curvea0[751] = _8297; + uint16_t _8298 = (uint16_t)(230); + _curvea0[752] = _8298; + uint16_t _8299 = (uint16_t)(230); + _curvea0[753] = _8299; + uint16_t _8300 = (uint16_t)(230); + _curvea0[754] = _8300; + uint16_t _8301 = (uint16_t)(230); + _curvea0[755] = _8301; + uint16_t _8302 = (uint16_t)(230); + _curvea0[756] = _8302; + uint16_t _8303 = (uint16_t)(230); + _curvea0[757] = _8303; + uint16_t _8304 = (uint16_t)(230); + _curvea0[758] = _8304; + uint16_t _8305 = (uint16_t)(231); + _curvea0[759] = _8305; + uint16_t _8306 = (uint16_t)(231); + _curvea0[760] = _8306; + uint16_t _8307 = (uint16_t)(231); + _curvea0[761] = _8307; + uint16_t _8308 = (uint16_t)(231); + _curvea0[762] = _8308; + uint16_t _8309 = (uint16_t)(231); + _curvea0[763] = _8309; + uint16_t _8310 = (uint16_t)(231); + _curvea0[764] = _8310; + uint16_t _8311 = (uint16_t)(231); + _curvea0[765] = _8311; + uint16_t _8312 = (uint16_t)(231); + _curvea0[766] = _8312; + uint16_t _8313 = (uint16_t)(231); + _curvea0[767] = _8313; + uint16_t _8314 = (uint16_t)(232); + _curvea0[768] = _8314; + uint16_t _8315 = (uint16_t)(232); + _curvea0[769] = _8315; + uint16_t _8316 = (uint16_t)(232); + _curvea0[770] = _8316; + uint16_t _8317 = (uint16_t)(232); + _curvea0[771] = _8317; + uint16_t _8318 = (uint16_t)(232); + _curvea0[772] = _8318; + uint16_t _8319 = (uint16_t)(232); + _curvea0[773] = _8319; + uint16_t _8320 = (uint16_t)(232); + _curvea0[774] = _8320; + uint16_t _8321 = (uint16_t)(232); + _curvea0[775] = _8321; + uint16_t _8322 = (uint16_t)(233); + _curvea0[776] = _8322; + uint16_t _8323 = (uint16_t)(233); + _curvea0[777] = _8323; + uint16_t _8324 = (uint16_t)(233); + _curvea0[778] = _8324; + uint16_t _8325 = (uint16_t)(233); + _curvea0[779] = _8325; + uint16_t _8326 = (uint16_t)(233); + _curvea0[780] = _8326; + uint16_t _8327 = (uint16_t)(233); + _curvea0[781] = _8327; + uint16_t _8328 = (uint16_t)(233); + _curvea0[782] = _8328; + uint16_t _8329 = (uint16_t)(233); + _curvea0[783] = _8329; + uint16_t _8330 = (uint16_t)(233); + _curvea0[784] = _8330; + uint16_t _8331 = (uint16_t)(234); + _curvea0[785] = _8331; + uint16_t _8332 = (uint16_t)(234); + _curvea0[786] = _8332; + uint16_t _8333 = (uint16_t)(234); + _curvea0[787] = _8333; + uint16_t _8334 = (uint16_t)(234); + _curvea0[788] = _8334; + uint16_t _8335 = (uint16_t)(234); + _curvea0[789] = _8335; + uint16_t _8336 = (uint16_t)(234); + _curvea0[790] = _8336; + uint16_t _8337 = (uint16_t)(234); + _curvea0[791] = _8337; + uint16_t _8338 = (uint16_t)(234); + _curvea0[792] = _8338; + uint16_t _8339 = (uint16_t)(234); + _curvea0[793] = _8339; + uint16_t _8340 = (uint16_t)(235); + _curvea0[794] = _8340; + uint16_t _8341 = (uint16_t)(235); + _curvea0[795] = _8341; + uint16_t _8342 = (uint16_t)(235); + _curvea0[796] = _8342; + uint16_t _8343 = (uint16_t)(235); + _curvea0[797] = _8343; + uint16_t _8344 = (uint16_t)(235); + _curvea0[798] = _8344; + uint16_t _8345 = (uint16_t)(235); + _curvea0[799] = _8345; + uint16_t _8346 = (uint16_t)(235); + _curvea0[800] = _8346; + uint16_t _8347 = (uint16_t)(235); + _curvea0[801] = _8347; + uint16_t _8348 = (uint16_t)(235); + _curvea0[802] = _8348; + uint16_t _8349 = (uint16_t)(236); + _curvea0[803] = _8349; + uint16_t _8350 = (uint16_t)(236); + _curvea0[804] = _8350; + uint16_t _8351 = (uint16_t)(236); + _curvea0[805] = _8351; + uint16_t _8352 = (uint16_t)(236); + _curvea0[806] = _8352; + uint16_t _8353 = (uint16_t)(236); + _curvea0[807] = _8353; + uint16_t _8354 = (uint16_t)(236); + _curvea0[808] = _8354; + uint16_t _8355 = (uint16_t)(236); + _curvea0[809] = _8355; + uint16_t _8356 = (uint16_t)(236); + _curvea0[810] = _8356; + uint16_t _8357 = (uint16_t)(236); + _curvea0[811] = _8357; + uint16_t _8358 = (uint16_t)(237); + _curvea0[812] = _8358; + uint16_t _8359 = (uint16_t)(237); + _curvea0[813] = _8359; + uint16_t _8360 = (uint16_t)(237); + _curvea0[814] = _8360; + uint16_t _8361 = (uint16_t)(237); + _curvea0[815] = _8361; + uint16_t _8362 = (uint16_t)(237); + _curvea0[816] = _8362; + uint16_t _8363 = (uint16_t)(237); + _curvea0[817] = _8363; + uint16_t _8364 = (uint16_t)(237); + _curvea0[818] = _8364; + uint16_t _8365 = (uint16_t)(237); + _curvea0[819] = _8365; + uint16_t _8366 = (uint16_t)(237); + _curvea0[820] = _8366; + uint16_t _8367 = (uint16_t)(237); + _curvea0[821] = _8367; + uint16_t _8368 = (uint16_t)(238); + _curvea0[822] = _8368; + uint16_t _8369 = (uint16_t)(238); + _curvea0[823] = _8369; + uint16_t _8370 = (uint16_t)(238); + _curvea0[824] = _8370; + uint16_t _8371 = (uint16_t)(238); + _curvea0[825] = _8371; + uint16_t _8372 = (uint16_t)(238); + _curvea0[826] = _8372; + uint16_t _8373 = (uint16_t)(238); + _curvea0[827] = _8373; + uint16_t _8374 = (uint16_t)(238); + _curvea0[828] = _8374; + uint16_t _8375 = (uint16_t)(238); + _curvea0[829] = _8375; + uint16_t _8376 = (uint16_t)(238); + _curvea0[830] = _8376; + uint16_t _8377 = (uint16_t)(239); + _curvea0[831] = _8377; + uint16_t _8378 = (uint16_t)(239); + _curvea0[832] = _8378; + uint16_t _8379 = (uint16_t)(239); + _curvea0[833] = _8379; + uint16_t _8380 = (uint16_t)(239); + _curvea0[834] = _8380; + uint16_t _8381 = (uint16_t)(239); + _curvea0[835] = _8381; + uint16_t _8382 = (uint16_t)(239); + _curvea0[836] = _8382; + uint16_t _8383 = (uint16_t)(239); + _curvea0[837] = _8383; + uint16_t _8384 = (uint16_t)(239); + _curvea0[838] = _8384; + uint16_t _8385 = (uint16_t)(239); + _curvea0[839] = _8385; + uint16_t _8386 = (uint16_t)(239); + _curvea0[840] = _8386; + uint16_t _8387 = (uint16_t)(240); + _curvea0[841] = _8387; + uint16_t _8388 = (uint16_t)(240); + _curvea0[842] = _8388; + uint16_t _8389 = (uint16_t)(240); + _curvea0[843] = _8389; + uint16_t _8390 = (uint16_t)(240); + _curvea0[844] = _8390; + uint16_t _8391 = (uint16_t)(240); + _curvea0[845] = _8391; + uint16_t _8392 = (uint16_t)(240); + _curvea0[846] = _8392; + uint16_t _8393 = (uint16_t)(240); + _curvea0[847] = _8393; + uint16_t _8394 = (uint16_t)(240); + _curvea0[848] = _8394; + uint16_t _8395 = (uint16_t)(240); + _curvea0[849] = _8395; + uint16_t _8396 = (uint16_t)(240); + _curvea0[850] = _8396; + uint16_t _8397 = (uint16_t)(241); + _curvea0[851] = _8397; + uint16_t _8398 = (uint16_t)(241); + _curvea0[852] = _8398; + uint16_t _8399 = (uint16_t)(241); + _curvea0[853] = _8399; + uint16_t _8400 = (uint16_t)(241); + _curvea0[854] = _8400; + uint16_t _8401 = (uint16_t)(241); + _curvea0[855] = _8401; + uint16_t _8402 = (uint16_t)(241); + _curvea0[856] = _8402; + uint16_t _8403 = (uint16_t)(241); + _curvea0[857] = _8403; + uint16_t _8404 = (uint16_t)(241); + _curvea0[858] = _8404; + uint16_t _8405 = (uint16_t)(241); + _curvea0[859] = _8405; + uint16_t _8406 = (uint16_t)(241); + _curvea0[860] = _8406; + uint16_t _8407 = (uint16_t)(242); + _curvea0[861] = _8407; + uint16_t _8408 = (uint16_t)(242); + _curvea0[862] = _8408; + uint16_t _8409 = (uint16_t)(242); + _curvea0[863] = _8409; + uint16_t _8410 = (uint16_t)(242); + _curvea0[864] = _8410; + uint16_t _8411 = (uint16_t)(242); + _curvea0[865] = _8411; + uint16_t _8412 = (uint16_t)(242); + _curvea0[866] = _8412; + uint16_t _8413 = (uint16_t)(242); + _curvea0[867] = _8413; + uint16_t _8414 = (uint16_t)(242); + _curvea0[868] = _8414; + uint16_t _8415 = (uint16_t)(242); + _curvea0[869] = _8415; + uint16_t _8416 = (uint16_t)(242); + _curvea0[870] = _8416; + uint16_t _8417 = (uint16_t)(243); + _curvea0[871] = _8417; + uint16_t _8418 = (uint16_t)(243); + _curvea0[872] = _8418; + uint16_t _8419 = (uint16_t)(243); + _curvea0[873] = _8419; + uint16_t _8420 = (uint16_t)(243); + _curvea0[874] = _8420; + uint16_t _8421 = (uint16_t)(243); + _curvea0[875] = _8421; + uint16_t _8422 = (uint16_t)(243); + _curvea0[876] = _8422; + uint16_t _8423 = (uint16_t)(243); + _curvea0[877] = _8423; + uint16_t _8424 = (uint16_t)(243); + _curvea0[878] = _8424; + uint16_t _8425 = (uint16_t)(243); + _curvea0[879] = _8425; + uint16_t _8426 = (uint16_t)(243); + _curvea0[880] = _8426; + uint16_t _8427 = (uint16_t)(244); + _curvea0[881] = _8427; + uint16_t _8428 = (uint16_t)(244); + _curvea0[882] = _8428; + uint16_t _8429 = (uint16_t)(244); + _curvea0[883] = _8429; + uint16_t _8430 = (uint16_t)(244); + _curvea0[884] = _8430; + uint16_t _8431 = (uint16_t)(244); + _curvea0[885] = _8431; + uint16_t _8432 = (uint16_t)(244); + _curvea0[886] = _8432; + uint16_t _8433 = (uint16_t)(244); + _curvea0[887] = _8433; + uint16_t _8434 = (uint16_t)(244); + _curvea0[888] = _8434; + uint16_t _8435 = (uint16_t)(244); + _curvea0[889] = _8435; + uint16_t _8436 = (uint16_t)(244); + _curvea0[890] = _8436; + uint16_t _8437 = (uint16_t)(244); + _curvea0[891] = _8437; + uint16_t _8438 = (uint16_t)(245); + _curvea0[892] = _8438; + uint16_t _8439 = (uint16_t)(245); + _curvea0[893] = _8439; + uint16_t _8440 = (uint16_t)(245); + _curvea0[894] = _8440; + uint16_t _8441 = (uint16_t)(245); + _curvea0[895] = _8441; + uint16_t _8442 = (uint16_t)(245); + _curvea0[896] = _8442; + uint16_t _8443 = (uint16_t)(245); + _curvea0[897] = _8443; + uint16_t _8444 = (uint16_t)(245); + _curvea0[898] = _8444; + uint16_t _8445 = (uint16_t)(245); + _curvea0[899] = _8445; + uint16_t _8446 = (uint16_t)(245); + _curvea0[900] = _8446; + uint16_t _8447 = (uint16_t)(245); + _curvea0[901] = _8447; + uint16_t _8448 = (uint16_t)(245); + _curvea0[902] = _8448; + uint16_t _8449 = (uint16_t)(246); + _curvea0[903] = _8449; + uint16_t _8450 = (uint16_t)(246); + _curvea0[904] = _8450; + uint16_t _8451 = (uint16_t)(246); + _curvea0[905] = _8451; + uint16_t _8452 = (uint16_t)(246); + _curvea0[906] = _8452; + uint16_t _8453 = (uint16_t)(246); + _curvea0[907] = _8453; + uint16_t _8454 = (uint16_t)(246); + _curvea0[908] = _8454; + uint16_t _8455 = (uint16_t)(246); + _curvea0[909] = _8455; + uint16_t _8456 = (uint16_t)(246); + _curvea0[910] = _8456; + uint16_t _8457 = (uint16_t)(246); + _curvea0[911] = _8457; + uint16_t _8458 = (uint16_t)(246); + _curvea0[912] = _8458; + uint16_t _8459 = (uint16_t)(246); + _curvea0[913] = _8459; + uint16_t _8460 = (uint16_t)(247); + _curvea0[914] = _8460; + uint16_t _8461 = (uint16_t)(247); + _curvea0[915] = _8461; + uint16_t _8462 = (uint16_t)(247); + _curvea0[916] = _8462; + uint16_t _8463 = (uint16_t)(247); + _curvea0[917] = _8463; + uint16_t _8464 = (uint16_t)(247); + _curvea0[918] = _8464; + uint16_t _8465 = (uint16_t)(247); + _curvea0[919] = _8465; + uint16_t _8466 = (uint16_t)(247); + _curvea0[920] = _8466; + uint16_t _8467 = (uint16_t)(247); + _curvea0[921] = _8467; + uint16_t _8468 = (uint16_t)(247); + _curvea0[922] = _8468; + uint16_t _8469 = (uint16_t)(247); + _curvea0[923] = _8469; + uint16_t _8470 = (uint16_t)(247); + _curvea0[924] = _8470; + uint16_t _8471 = (uint16_t)(248); + _curvea0[925] = _8471; + uint16_t _8472 = (uint16_t)(248); + _curvea0[926] = _8472; + uint16_t _8473 = (uint16_t)(248); + _curvea0[927] = _8473; + uint16_t _8474 = (uint16_t)(248); + _curvea0[928] = _8474; + uint16_t _8475 = (uint16_t)(248); + _curvea0[929] = _8475; + uint16_t _8476 = (uint16_t)(248); + _curvea0[930] = _8476; + uint16_t _8477 = (uint16_t)(248); + _curvea0[931] = _8477; + uint16_t _8478 = (uint16_t)(248); + _curvea0[932] = _8478; + uint16_t _8479 = (uint16_t)(248); + _curvea0[933] = _8479; + uint16_t _8480 = (uint16_t)(248); + _curvea0[934] = _8480; + uint16_t _8481 = (uint16_t)(248); + _curvea0[935] = _8481; + uint16_t _8482 = (uint16_t)(249); + _curvea0[936] = _8482; + uint16_t _8483 = (uint16_t)(249); + _curvea0[937] = _8483; + uint16_t _8484 = (uint16_t)(249); + _curvea0[938] = _8484; + uint16_t _8485 = (uint16_t)(249); + _curvea0[939] = _8485; + uint16_t _8486 = (uint16_t)(249); + _curvea0[940] = _8486; + uint16_t _8487 = (uint16_t)(249); + _curvea0[941] = _8487; + uint16_t _8488 = (uint16_t)(249); + _curvea0[942] = _8488; + uint16_t _8489 = (uint16_t)(249); + _curvea0[943] = _8489; + uint16_t _8490 = (uint16_t)(249); + _curvea0[944] = _8490; + uint16_t _8491 = (uint16_t)(249); + _curvea0[945] = _8491; + uint16_t _8492 = (uint16_t)(249); + _curvea0[946] = _8492; + uint16_t _8493 = (uint16_t)(249); + _curvea0[947] = _8493; + uint16_t _8494 = (uint16_t)(250); + _curvea0[948] = _8494; + uint16_t _8495 = (uint16_t)(250); + _curvea0[949] = _8495; + uint16_t _8496 = (uint16_t)(250); + _curvea0[950] = _8496; + uint16_t _8497 = (uint16_t)(250); + _curvea0[951] = _8497; + uint16_t _8498 = (uint16_t)(250); + _curvea0[952] = _8498; + uint16_t _8499 = (uint16_t)(250); + _curvea0[953] = _8499; + uint16_t _8500 = (uint16_t)(250); + _curvea0[954] = _8500; + uint16_t _8501 = (uint16_t)(250); + _curvea0[955] = _8501; + uint16_t _8502 = (uint16_t)(250); + _curvea0[956] = _8502; + uint16_t _8503 = (uint16_t)(250); + _curvea0[957] = _8503; + uint16_t _8504 = (uint16_t)(250); + _curvea0[958] = _8504; + uint16_t _8505 = (uint16_t)(250); + _curvea0[959] = _8505; + uint16_t _8506 = (uint16_t)(251); + _curvea0[960] = _8506; + uint16_t _8507 = (uint16_t)(251); + _curvea0[961] = _8507; + uint16_t _8508 = (uint16_t)(251); + _curvea0[962] = _8508; + uint16_t _8509 = (uint16_t)(251); + _curvea0[963] = _8509; + uint16_t _8510 = (uint16_t)(251); + _curvea0[964] = _8510; + uint16_t _8511 = (uint16_t)(251); + _curvea0[965] = _8511; + uint16_t _8512 = (uint16_t)(251); + _curvea0[966] = _8512; + uint16_t _8513 = (uint16_t)(251); + _curvea0[967] = _8513; + uint16_t _8514 = (uint16_t)(251); + _curvea0[968] = _8514; + uint16_t _8515 = (uint16_t)(251); + _curvea0[969] = _8515; + uint16_t _8516 = (uint16_t)(251); + _curvea0[970] = _8516; + uint16_t _8517 = (uint16_t)(251); + _curvea0[971] = _8517; + uint16_t _8518 = (uint16_t)(252); + _curvea0[972] = _8518; + uint16_t _8519 = (uint16_t)(252); + _curvea0[973] = _8519; + uint16_t _8520 = (uint16_t)(252); + _curvea0[974] = _8520; + uint16_t _8521 = (uint16_t)(252); + _curvea0[975] = _8521; + uint16_t _8522 = (uint16_t)(252); + _curvea0[976] = _8522; + uint16_t _8523 = (uint16_t)(252); + _curvea0[977] = _8523; + uint16_t _8524 = (uint16_t)(252); + _curvea0[978] = _8524; + uint16_t _8525 = (uint16_t)(252); + _curvea0[979] = _8525; + uint16_t _8526 = (uint16_t)(252); + _curvea0[980] = _8526; + uint16_t _8527 = (uint16_t)(252); + _curvea0[981] = _8527; + uint16_t _8528 = (uint16_t)(252); + _curvea0[982] = _8528; + uint16_t _8529 = (uint16_t)(252); + _curvea0[983] = _8529; + uint16_t _8530 = (uint16_t)(252); + _curvea0[984] = _8530; + uint16_t _8531 = (uint16_t)(253); + _curvea0[985] = _8531; + uint16_t _8532 = (uint16_t)(253); + _curvea0[986] = _8532; + uint16_t _8533 = (uint16_t)(253); + _curvea0[987] = _8533; + uint16_t _8534 = (uint16_t)(253); + _curvea0[988] = _8534; + uint16_t _8535 = (uint16_t)(253); + _curvea0[989] = _8535; + uint16_t _8536 = (uint16_t)(253); + _curvea0[990] = _8536; + uint16_t _8537 = (uint16_t)(253); + _curvea0[991] = _8537; + uint16_t _8538 = (uint16_t)(253); + _curvea0[992] = _8538; + uint16_t _8539 = (uint16_t)(253); + _curvea0[993] = _8539; + uint16_t _8540 = (uint16_t)(253); + _curvea0[994] = _8540; + uint16_t _8541 = (uint16_t)(253); + _curvea0[995] = _8541; + uint16_t _8542 = (uint16_t)(253); + _curvea0[996] = _8542; + uint16_t _8543 = (uint16_t)(253); + _curvea0[997] = _8543; + uint16_t _8544 = (uint16_t)(254); + _curvea0[998] = _8544; + uint16_t _8545 = (uint16_t)(254); + _curvea0[999] = _8545; + uint16_t _8546 = (uint16_t)(254); + _curvea0[1000] = _8546; + uint16_t _8547 = (uint16_t)(254); + _curvea0[1001] = _8547; + uint16_t _8548 = (uint16_t)(254); + _curvea0[1002] = _8548; + uint16_t _8549 = (uint16_t)(254); + _curvea0[1003] = _8549; + uint16_t _8550 = (uint16_t)(254); + _curvea0[1004] = _8550; + uint16_t _8551 = (uint16_t)(254); + _curvea0[1005] = _8551; + uint16_t _8552 = (uint16_t)(254); + _curvea0[1006] = _8552; + uint16_t _8553 = (uint16_t)(254); + _curvea0[1007] = _8553; + uint16_t _8554 = (uint16_t)(254); + _curvea0[1008] = _8554; + uint16_t _8555 = (uint16_t)(254); + _curvea0[1009] = _8555; + uint16_t _8556 = (uint16_t)(254); + _curvea0[1010] = _8556; + uint16_t _8557 = (uint16_t)(255); + _curvea0[1011] = _8557; + uint16_t _8558 = (uint16_t)(255); + _curvea0[1012] = _8558; + uint16_t _8559 = (uint16_t)(255); + _curvea0[1013] = _8559; + uint16_t _8560 = (uint16_t)(255); + _curvea0[1014] = _8560; + uint16_t _8561 = (uint16_t)(255); + _curvea0[1015] = _8561; + uint16_t _8562 = (uint16_t)(255); + _curvea0[1016] = _8562; + uint16_t _8563 = (uint16_t)(255); + _curvea0[1017] = _8563; + uint16_t _8564 = (uint16_t)(255); + _curvea0[1018] = _8564; + uint16_t _8565 = (uint16_t)(255); + _curvea0[1019] = _8565; + uint16_t _8566 = (uint16_t)(255); + _curvea0[1020] = _8566; + uint16_t _8567 = (uint16_t)(255); + _curvea0[1021] = _8567; + uint16_t _8568 = (uint16_t)(255); + _curvea0[1022] = _8568; + uint16_t _8569 = (uint16_t)(255); + _curvea0[1023] = _8569; + + int16_t _8570 = (int16_t)(1023); + int16_t _8571 = min(_corrected_stencil_6, _8570); + int16_t _8572 = (int16_t)(0); + int16_t _8573 = max(_8571, _8572); + uint16_t _8574 = (uint16_t)(_8573); + int32_t _8575 = (int32_t)(_8574); + uint16_t _8576 = ((const uint16_t *)_curvea0)[_8575]; + return _8576; +} + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi) = curved.stencil((hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi, 0) +hw_uint<16> hcompute_hw_output_glb_stencil(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_1 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_1; +} + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi) = curved.stencil((hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi, 1) +hw_uint<16> hcompute_hw_output_glb_stencil_1(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_2 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_2; +} + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi) = curved.stencil((hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi, 2) +hw_uint<16> hcompute_hw_output_glb_stencil_2(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_3 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_3; +} + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi, 0) +hw_uint<16> hcompute_hw_output_glb_stencil_3(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_4 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_4; +} + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi, 1) +hw_uint<16> hcompute_hw_output_glb_stencil_4(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_5 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_5; +} + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi, 2) +hw_uint<16> hcompute_hw_output_glb_stencil_5(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_6 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_6; +} + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi + (0*124))*2), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_1 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_1; +} + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi + (0*124))*2), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_1(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_2 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_2; +} + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi + (0*124))*2), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_2(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_3 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_3; +} + +//store is: hw_output_global_wrapper.stencil(0, (((hw_output_global_wrapper_s0_x_xi_xi + (0*124))*2) + 1), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_3(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_4 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_4; +} + +//store is: hw_output_global_wrapper.stencil(1, (((hw_output_global_wrapper_s0_x_xi_xi + (0*124))*2) + 1), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_4(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_5 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_5; +} + +//store is: hw_output_global_wrapper.stencil(2, (((hw_output_global_wrapper_s0_x_xi_xi + (0*124))*2) + 1), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_5(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_6 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_6; +} + diff --git a/camera_pipeline_unrolly_compute.h b/camera_pipeline_unrolly_compute.h new file mode 100644 index 000000000..847e5023f --- /dev/null +++ b/camera_pipeline_unrolly_compute.h @@ -0,0 +1,13031 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_s0_x_x, (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil((hw_input_global_wrapper_s0_x_x + ((0*248) + -4)), (((hw_input_global_wrapper_s0_y_yio + 0)*2) + -4)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_s0_x_x, ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil((hw_input_global_wrapper_s0_x_x + ((0*248) + -4)), (((hw_input_global_wrapper_s0_y_yio + 0)*2) + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_1(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_2 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_1 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_1; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_1(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_2 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_2; +} + +//store is: denoised$1.stencil(denoised_1_s0_x_x, (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 4), ((denoised_1_s0_y_yio*2) + 2)))))) +hw_uint<16> hcompute_denoised_1_stencil(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_1 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_2 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_3 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_4 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_5 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>(); + + uint16_t _344 = max(_hw_input_global_wrapper_global_wrapper_stencil_4, _hw_input_global_wrapper_global_wrapper_stencil_5); + uint16_t _345 = max(_hw_input_global_wrapper_global_wrapper_stencil_3, _344); + uint16_t _346 = max(_hw_input_global_wrapper_global_wrapper_stencil_2, _345); + uint16_t _347 = min(_hw_input_global_wrapper_global_wrapper_stencil_1, _346); + return _347; +} + +//store is: denoised$1.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 4), ((denoised_1_s0_y_yio*2) + 3)))))) +hw_uint<16> hcompute_denoised_1_stencil_1(hw_uint<80>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_10 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_6 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_7 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_8 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<48, 63>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_9 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<64, 79>(); + + uint16_t _366 = max(_hw_input_global_wrapper_global_wrapper_stencil_9, _hw_input_global_wrapper_global_wrapper_stencil_10); + uint16_t _367 = max(_hw_input_global_wrapper_global_wrapper_stencil_8, _366); + uint16_t _368 = max(_hw_input_global_wrapper_global_wrapper_stencil_7, _367); + uint16_t _369 = min(_hw_input_global_wrapper_global_wrapper_stencil_6, _368); + return _369; +} + +//store is: b_b.stencil(b_b_s0_x, ((b_b_s0_y + -1) + 1)) = denoised$1.stencil(((b_b_s0_x*2) + 2), (((b_b_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_b_b_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_1 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_1; +} + +//store is: g_gb.stencil(((g_gb_s0_x + -1) + 1), ((g_gb_s0_y + -1) + 1)) = denoised$1.stencil((((g_gb_s0_x + -1)*2) + 3), (((g_gb_s0_y + -1)*2) + 3)) +hw_uint<16> hcompute_g_gb_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_2 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_2; +} + +//store is: g_gr.stencil(((g_gr_s0_x + -1) + 1), ((g_gr_s0_y + -1) + 1)) = denoised$1.stencil((((g_gr_s0_x + -1)*2) + 2), (((g_gr_s0_y + -1)*2) + 2)) +hw_uint<16> hcompute_g_gr_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_3 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_3; +} + +//store is: g_b.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)) = select((absd(g_gb.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)), g_gb.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1))) < absd(g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 2)), g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)))), ((g_gb.stencil(g_b_s0_x, ((g_b_s0_y + -1) + 1)) + g_gb.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)))/(uint16)2), ((g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 2)) + g_gr.stencil((g_b_s0_x + 1), ((g_b_s0_y + -1) + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_b_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_1 = (uint16_t) g_gb_stencil.extract<0, 15>(); + uint16_t _g_gb_stencil_2 = (uint16_t) g_gb_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_1 = (uint16_t) g_gr_stencil.extract<0, 15>(); + uint16_t _g_gr_stencil_2 = (uint16_t) g_gr_stencil.extract<16, 31>(); + + uint16_t _424 = _g_gb_stencil_1 + _g_gb_stencil_2; + uint16_t _425 = (uint16_t)(1); + uint16_t _426 = _424 >> _425; + uint16_t _427 = _g_gr_stencil_1 + _g_gr_stencil_2; + uint16_t _428 = _427 >> _425; + uint16_t _429 = _g_gb_stencil_2 - _g_gb_stencil_1; + uint16_t _430 = _g_gb_stencil_1 - _g_gb_stencil_2; + bool _431 = _g_gb_stencil_1 < _g_gb_stencil_2; + uint16_t _432 = (uint16_t)(_431 ? _429 : _430); + uint16_t _433 = _432; + uint16_t _434 = _g_gr_stencil_2 - _g_gr_stencil_1; + uint16_t _435 = _g_gr_stencil_1 - _g_gr_stencil_2; + bool _436 = _g_gr_stencil_1 < _g_gr_stencil_2; + uint16_t _437 = (uint16_t)(_436 ? _434 : _435); + uint16_t _438 = _437; + bool _439 = _433 < _438; + uint16_t _440 = (uint16_t)(_439 ? _426 : _428); + return _440; +} + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + ((b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) - ((g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_b_gb_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gb_stencil) { + uint16_t _b_b_stencil_1 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_2 = (uint16_t) b_b_stencil.extract<16, 31>(); + + uint16_t _g_b_stencil_1 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_2 = (uint16_t) g_b_stencil.extract<16, 31>(); + + uint16_t _g_gb_stencil_3 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _476 = _b_b_stencil_1 + _b_b_stencil_2; + uint16_t _477 = (uint16_t)(1); + uint16_t _478 = _476 >> _477; + uint16_t _479 = _g_gb_stencil_3 + _478; + uint16_t _480 = _g_b_stencil_1 + _g_b_stencil_2; + uint16_t _481 = _480 >> _477; + uint16_t _482 = _479 - _481; + return _482; +} + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + ((b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + b_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) - ((g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + g_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) +hw_uint<16> hcompute_b_gr_stencil(hw_uint<32>& b_b_stencil, hw_uint<32>& g_b_stencil, hw_uint<16>& g_gr_stencil) { + uint16_t _b_b_stencil_3 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_4 = (uint16_t) b_b_stencil.extract<16, 31>(); + + uint16_t _g_b_stencil_3 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_4 = (uint16_t) g_b_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_3 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _505 = _b_b_stencil_3 + _b_b_stencil_4; + uint16_t _506 = (uint16_t)(1); + uint16_t _507 = _505 >> _506; + uint16_t _508 = _g_gr_stencil_3 + _507; + uint16_t _509 = _g_b_stencil_3 + _g_b_stencil_4; + uint16_t _510 = _509 >> _506; + uint16_t _511 = _508 - _510; + return _511; +} + +//store is: g_r.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y) = select((absd(g_gr.stencil(((g_r_s0_x + -1) + 2), (g_r_s0_y + 1)), g_gr.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1))) < absd(g_gb.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y), g_gb.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)))), ((g_gr.stencil(((g_r_s0_x + -1) + 2), (g_r_s0_y + 1)) + g_gr.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)))/(uint16)2), ((g_gb.stencil(((g_r_s0_x + -1) + 1), g_r_s0_y) + g_gb.stencil(((g_r_s0_x + -1) + 1), (g_r_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_g_r_stencil(hw_uint<32>& g_gb_stencil, hw_uint<32>& g_gr_stencil) { + uint16_t _g_gb_stencil_4 = (uint16_t) g_gb_stencil.extract<0, 15>(); + uint16_t _g_gb_stencil_5 = (uint16_t) g_gb_stencil.extract<16, 31>(); + + uint16_t _g_gr_stencil_4 = (uint16_t) g_gr_stencil.extract<0, 15>(); + uint16_t _g_gr_stencil_5 = (uint16_t) g_gr_stencil.extract<16, 31>(); + + uint16_t _535 = _g_gr_stencil_4 + _g_gr_stencil_5; + uint16_t _536 = (uint16_t)(1); + uint16_t _537 = _535 >> _536; + uint16_t _538 = _g_gb_stencil_4 + _g_gb_stencil_5; + uint16_t _539 = _538 >> _536; + uint16_t _540 = _g_gr_stencil_5 - _g_gr_stencil_4; + uint16_t _541 = _g_gr_stencil_4 - _g_gr_stencil_5; + bool _542 = _g_gr_stencil_4 < _g_gr_stencil_5; + uint16_t _543 = (uint16_t)(_542 ? _540 : _541); + uint16_t _544 = _543; + uint16_t _545 = _g_gb_stencil_5 - _g_gb_stencil_4; + uint16_t _546 = _g_gb_stencil_4 - _g_gb_stencil_5; + bool _547 = _g_gb_stencil_4 < _g_gb_stencil_5; + uint16_t _548 = (uint16_t)(_547 ? _545 : _546); + uint16_t _549 = _548; + bool _550 = _544 < _549; + uint16_t _551 = (uint16_t)(_550 ? _537 : _539); + return _551; +} + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + b_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)) - ((g_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + g_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + b_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2)) - ((g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + g_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2))) +hw_uint<16> hcompute_b_r_stencil(hw_uint<64>& b_b_stencil, hw_uint<64>& g_b_stencil, hw_uint<16>& g_r_stencil) { + uint16_t _b_b_stencil_5 = (uint16_t) b_b_stencil.extract<0, 15>(); + uint16_t _b_b_stencil_6 = (uint16_t) b_b_stencil.extract<16, 31>(); + uint16_t _b_b_stencil_7 = (uint16_t) b_b_stencil.extract<32, 47>(); + uint16_t _b_b_stencil_8 = (uint16_t) b_b_stencil.extract<48, 63>(); + + uint16_t _g_b_stencil_5 = (uint16_t) g_b_stencil.extract<0, 15>(); + uint16_t _g_b_stencil_6 = (uint16_t) g_b_stencil.extract<16, 31>(); + uint16_t _g_b_stencil_7 = (uint16_t) g_b_stencil.extract<32, 47>(); + uint16_t _g_b_stencil_8 = (uint16_t) g_b_stencil.extract<48, 63>(); + + uint16_t _g_r_stencil_1 = (uint16_t) g_r_stencil.extract<0, 15>(); + + uint16_t _587 = _b_b_stencil_5 + _b_b_stencil_6; + uint16_t _588 = (uint16_t)(1); + uint16_t _589 = _587 >> _588; + uint16_t _590 = _g_r_stencil_1 + _589; + uint16_t _591 = _g_b_stencil_5 + _g_b_stencil_6; + uint16_t _592 = _591 >> _588; + uint16_t _593 = _590 - _592; + uint16_t _594 = _b_b_stencil_7 + _b_b_stencil_8; + uint16_t _595 = _594 >> _588; + uint16_t _596 = _g_r_stencil_1 + _595; + uint16_t _597 = _g_b_stencil_7 + _g_b_stencil_8; + uint16_t _598 = _597 >> _588; + uint16_t _599 = _596 - _598; + uint16_t _600 = _b_b_stencil_6 - _b_b_stencil_5; + uint16_t _601 = _b_b_stencil_5 - _b_b_stencil_6; + bool _602 = _b_b_stencil_5 < _b_b_stencil_6; + uint16_t _603 = (uint16_t)(_602 ? _600 : _601); + uint16_t _604 = _603; + uint16_t _605 = _b_b_stencil_8 - _b_b_stencil_7; + uint16_t _606 = _b_b_stencil_7 - _b_b_stencil_8; + bool _607 = _b_b_stencil_7 < _b_b_stencil_8; + uint16_t _608 = (uint16_t)(_607 ? _605 : _606); + uint16_t _609 = _608; + bool _610 = _604 < _609; + uint16_t _611 = (uint16_t)(_610 ? _593 : _599); + return _611; +} + +//store is: r_r.stencil(((r_r_s0_x + -1) + 1), r_r_s0_y) = denoised$1.stencil((((r_r_s0_x + -1)*2) + 3), ((r_r_s0_y*2) + 2)) +hw_uint<16> hcompute_r_r_stencil(hw_uint<16>& denoised_1_stencil) { + uint16_t _denoised_1_stencil_4 = (uint16_t) denoised_1_stencil.extract<0, 15>(); + + return _denoised_1_stencil_4; +} + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil((r_b_s0_x + 1), r_b_s0_y) + r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x + 1), r_b_s0_y) + g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil(r_b_s0_x, r_b_s0_y) + r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil(r_b_s0_x, r_b_s0_y) + g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2))) +hw_uint<16> hcompute_r_b_stencil(hw_uint<16>& g_b_stencil, hw_uint<64>& g_r_stencil, hw_uint<64>& r_r_stencil) { + uint16_t _g_b_stencil_9 = (uint16_t) g_b_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_2 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_3 = (uint16_t) g_r_stencil.extract<16, 31>(); + uint16_t _g_r_stencil_4 = (uint16_t) g_r_stencil.extract<32, 47>(); + uint16_t _g_r_stencil_5 = (uint16_t) g_r_stencil.extract<48, 63>(); + + uint16_t _r_r_stencil_1 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_2 = (uint16_t) r_r_stencil.extract<16, 31>(); + uint16_t _r_r_stencil_3 = (uint16_t) r_r_stencil.extract<32, 47>(); + uint16_t _r_r_stencil_4 = (uint16_t) r_r_stencil.extract<48, 63>(); + + uint16_t _675 = _r_r_stencil_1 + _r_r_stencil_2; + uint16_t _676 = (uint16_t)(1); + uint16_t _677 = _675 >> _676; + uint16_t _678 = _g_b_stencil_9 + _677; + uint16_t _679 = _g_r_stencil_2 + _g_r_stencil_3; + uint16_t _680 = _679 >> _676; + uint16_t _681 = _678 - _680; + uint16_t _682 = _r_r_stencil_3 + _r_r_stencil_4; + uint16_t _683 = _682 >> _676; + uint16_t _684 = _g_b_stencil_9 + _683; + uint16_t _685 = _g_r_stencil_4 + _g_r_stencil_5; + uint16_t _686 = _685 >> _676; + uint16_t _687 = _684 - _686; + uint16_t _688 = _r_r_stencil_2 - _r_r_stencil_1; + uint16_t _689 = _r_r_stencil_1 - _r_r_stencil_2; + bool _690 = _r_r_stencil_1 < _r_r_stencil_2; + uint16_t _691 = (uint16_t)(_690 ? _688 : _689); + uint16_t _692 = _691; + uint16_t _693 = _r_r_stencil_4 - _r_r_stencil_3; + uint16_t _694 = _r_r_stencil_3 - _r_r_stencil_4; + bool _695 = _r_r_stencil_3 < _r_r_stencil_4; + uint16_t _696 = (uint16_t)(_695 ? _693 : _694); + uint16_t _697 = _696; + bool _698 = _692 < _697; + uint16_t _699 = (uint16_t)(_698 ? _681 : _687); + return _699; +} + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + ((r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) +hw_uint<16> hcompute_r_gb_stencil(hw_uint<16>& g_gb_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gb_stencil_6 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_6 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_7 = (uint16_t) g_r_stencil.extract<16, 31>(); + + uint16_t _r_r_stencil_5 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_6 = (uint16_t) r_r_stencil.extract<16, 31>(); + + uint16_t _754 = _r_r_stencil_5 + _r_r_stencil_6; + uint16_t _755 = (uint16_t)(1); + uint16_t _756 = _754 >> _755; + uint16_t _757 = _g_gb_stencil_6 + _756; + uint16_t _758 = _g_r_stencil_6 + _g_r_stencil_7; + uint16_t _759 = _758 >> _755; + uint16_t _760 = _757 - _759; + return _760; +} + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + ((r_r.stencil(r_gr_s0_x, r_gr_s0_y) + r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y))/(uint16)2)) - ((g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + g_r.stencil(r_gr_s0_x, r_gr_s0_y))/(uint16)2)) +hw_uint<16> hcompute_r_gr_stencil(hw_uint<16>& g_gr_stencil, hw_uint<32>& g_r_stencil, hw_uint<32>& r_r_stencil) { + uint16_t _g_gr_stencil_6 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_8 = (uint16_t) g_r_stencil.extract<0, 15>(); + uint16_t _g_r_stencil_9 = (uint16_t) g_r_stencil.extract<16, 31>(); + + uint16_t _r_r_stencil_7 = (uint16_t) r_r_stencil.extract<0, 15>(); + uint16_t _r_r_stencil_8 = (uint16_t) r_r_stencil.extract<16, 31>(); + + uint16_t _783 = _r_r_stencil_7 + _r_r_stencil_8; + uint16_t _784 = (uint16_t)(1); + uint16_t _785 = _783 >> _784; + uint16_t _786 = _g_gr_stencil_6 + _785; + uint16_t _787 = _g_r_stencil_8 + _g_r_stencil_9; + uint16_t _788 = _787 >> _784; + uint16_t _789 = _786 - _788; + return _789; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio*2), 0) = select(((demosaicked_1_s0_x_x % 2) == 0), r_gr.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio), r_r.stencil(((demosaicked_1_s0_x_x/2) + 1), demosaicked_1_s0_y_yio)) +hw_uint<16> hcompute_demosaicked_1_stencil(hw_uint<16>& r_gr_stencil, hw_uint<16>& r_r_stencil, const int _demosaicked_1_s0_x_x) { + uint16_t _r_gr_stencil_1 = (uint16_t) r_gr_stencil.extract<0, 15>(); + + uint16_t _r_r_stencil_9 = (uint16_t) r_r_stencil.extract<0, 15>(); + + int32_t _811 = _demosaicked_1_s0_x_x & 1; + bool _812 = _811 == 0; + uint16_t _813 = (uint16_t)(_812 ? _r_gr_stencil_1 : _r_r_stencil_9); + return _813; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio*2), 1) = select(((demosaicked_1_s0_x_x % 2) == 0), g_gr.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y_yio + 1)), g_r.stencil(((demosaicked_1_s0_x_x/2) + 1), demosaicked_1_s0_y_yio)) +hw_uint<16> hcompute_demosaicked_1_stencil_1(hw_uint<16>& g_gr_stencil, hw_uint<16>& g_r_stencil, const int _demosaicked_1_s0_x_x) { + uint16_t _g_gr_stencil_7 = (uint16_t) g_gr_stencil.extract<0, 15>(); + + uint16_t _g_r_stencil_10 = (uint16_t) g_r_stencil.extract<0, 15>(); + + int32_t _826 = _demosaicked_1_s0_x_x & 1; + bool _827 = _826 == 0; + uint16_t _828 = (uint16_t)(_827 ? _g_gr_stencil_7 : _g_r_stencil_10); + return _828; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio*2), 2) = select(((demosaicked_1_s0_x_x % 2) == 0), b_gr.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio), b_r.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio)) +hw_uint<16> hcompute_demosaicked_1_stencil_2(hw_uint<16>& b_gr_stencil, hw_uint<16>& b_r_stencil, const int _demosaicked_1_s0_x_x) { + uint16_t _b_gr_stencil_1 = (uint16_t) b_gr_stencil.extract<0, 15>(); + + uint16_t _b_r_stencil_1 = (uint16_t) b_r_stencil.extract<0, 15>(); + + int32_t _842 = _demosaicked_1_s0_x_x & 1; + bool _843 = _842 == 0; + uint16_t _844 = (uint16_t)(_843 ? _b_gr_stencil_1 : _b_r_stencil_1); + return _844; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y_yio*2) + 1), 0) = select(((demosaicked_1_s0_x_x % 2) == 0), r_b.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio), r_gb.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio)) +hw_uint<16> hcompute_demosaicked_1_stencil_3(hw_uint<16>& r_b_stencil, hw_uint<16>& r_gb_stencil, const int _demosaicked_1_s0_x_x) { + uint16_t _r_b_stencil_1 = (uint16_t) r_b_stencil.extract<0, 15>(); + + uint16_t _r_gb_stencil_1 = (uint16_t) r_gb_stencil.extract<0, 15>(); + + int32_t _856 = _demosaicked_1_s0_x_x & 1; + bool _857 = _856 == 0; + uint16_t _858 = (uint16_t)(_857 ? _r_b_stencil_1 : _r_gb_stencil_1); + return _858; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y_yio*2) + 1), 1) = select(((demosaicked_1_s0_x_x % 2) == 0), g_b.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y_yio + 1)), g_gb.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y_yio + 1))) +hw_uint<16> hcompute_demosaicked_1_stencil_4(hw_uint<16>& g_b_stencil, hw_uint<16>& g_gb_stencil, const int _demosaicked_1_s0_x_x) { + uint16_t _g_b_stencil_10 = (uint16_t) g_b_stencil.extract<0, 15>(); + + uint16_t _g_gb_stencil_7 = (uint16_t) g_gb_stencil.extract<0, 15>(); + + int32_t _871 = _demosaicked_1_s0_x_x & 1; + bool _872 = _871 == 0; + uint16_t _873 = (uint16_t)(_872 ? _g_b_stencil_10 : _g_gb_stencil_7); + return _873; +} + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y_yio*2) + 1), 2) = select(((demosaicked_1_s0_x_x % 2) == 0), b_b.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y_yio + 1)), b_gb.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio)) +hw_uint<16> hcompute_demosaicked_1_stencil_5(hw_uint<16>& b_b_stencil, hw_uint<16>& b_gb_stencil, const int _demosaicked_1_s0_x_x) { + uint16_t _b_b_stencil_9 = (uint16_t) b_b_stencil.extract<0, 15>(); + + uint16_t _b_gb_stencil_1 = (uint16_t) b_gb_stencil.extract<0, 15>(); + + int32_t _888 = _demosaicked_1_s0_x_x & 1; + bool _889 = _888 == 0; + uint16_t _890 = (uint16_t)(_889 ? _b_b_stencil_9 : _b_gb_stencil_1); + return _890; +} + +//store is: corrected.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_1 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_2 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_3 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _904 = (uint16_t)(10000); + uint16_t _905 = min(_demosaicked_1_stencil_1, _904); + int32_t _906 = (int32_t)(_905); + int32_t _907 = _906 * 549; + int32_t _908 = _907 >> 8; + int16_t _909 = (int16_t)(_908); + uint16_t _910 = min(_demosaicked_1_stencil_2, _904); + int32_t _911 = (int32_t)(_910); + int32_t _912 = _911 * -103; + int32_t _913 = _912 >> 8; + int16_t _914 = (int16_t)(_913); + int16_t _915 = _909 + _914; + uint16_t _916 = min(_demosaicked_1_stencil_3, _904); + int32_t _917 = (int32_t)(_916); + int32_t _918 = _917 * 7; + int32_t _919 = _918 >> 8; + int16_t _920 = (int16_t)(_919); + int16_t _921 = _915 + _920; + int16_t _922 = (int16_t)(-40); + int16_t _923 = _921 + _922; + return _923; +} + +//store is: corrected.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_1(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_4 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_5 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_6 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _962 = (uint16_t)(10000); + uint16_t _963 = min(_demosaicked_1_stencil_4, _962); + int32_t _964 = (int32_t)(_963); + int32_t _965 = _964 * -96; + int32_t _966 = _965 >> 8; + int16_t _967 = (int16_t)(_966); + uint16_t _968 = min(_demosaicked_1_stencil_5, _962); + int32_t _969 = (int32_t)(_968); + int32_t _970 = _969 * 373; + int32_t _971 = _970 >> 8; + int16_t _972 = (int16_t)(_971); + int16_t _973 = _967 + _972; + uint16_t _974 = min(_demosaicked_1_stencil_6, _962); + int32_t _975 = (int32_t)(_974); + int32_t _976 = _975 * 62; + int32_t _977 = _976 >> 8; + int16_t _978 = (int16_t)(_977); + int16_t _979 = _973 + _978; + int16_t _980 = (int16_t)(-29); + int16_t _981 = _979 + _980; + return _981; +} + +//store is: corrected.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_2(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_7 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_8 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_9 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1020 = (uint16_t)(10000); + uint16_t _1021 = min(_demosaicked_1_stencil_7, _1020); + int32_t _1022 = (int32_t)(_1021); + int32_t _1023 = _1022 * -31; + int32_t _1024 = _1023 >> 8; + int16_t _1025 = (int16_t)(_1024); + uint16_t _1026 = min(_demosaicked_1_stencil_8, _1020); + int32_t _1027 = (int32_t)(_1026); + int32_t _1028 = _1027 * -261; + int32_t _1029 = _1028 >> 8; + int16_t _1030 = (int16_t)(_1029); + int16_t _1031 = _1025 + _1030; + uint16_t _1032 = min(_demosaicked_1_stencil_9, _1020); + int32_t _1033 = (int32_t)(_1032); + int32_t _1034 = _1033 * 883; + int32_t _1035 = _1034 >> 8; + int16_t _1036 = (int16_t)(_1035); + int16_t _1037 = _1031 + _1036; + int16_t _1038 = (int16_t)(-22); + int16_t _1039 = _1037 + _1038; + return _1039; +} + +//store is: corrected.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) +hw_uint<16> hcompute_corrected_stencil_3(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_10 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_11 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_12 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1078 = (uint16_t)(10000); + uint16_t _1079 = min(_demosaicked_1_stencil_10, _1078); + int32_t _1080 = (int32_t)(_1079); + int32_t _1081 = _1080 * 549; + int32_t _1082 = _1081 >> 8; + int16_t _1083 = (int16_t)(_1082); + uint16_t _1084 = min(_demosaicked_1_stencil_11, _1078); + int32_t _1085 = (int32_t)(_1084); + int32_t _1086 = _1085 * -103; + int32_t _1087 = _1086 >> 8; + int16_t _1088 = (int16_t)(_1087); + int16_t _1089 = _1083 + _1088; + uint16_t _1090 = min(_demosaicked_1_stencil_12, _1078); + int32_t _1091 = (int32_t)(_1090); + int32_t _1092 = _1091 * 7; + int32_t _1093 = _1092 >> 8; + int16_t _1094 = (int16_t)(_1093); + int16_t _1095 = _1089 + _1094; + int16_t _1096 = (int16_t)(-40); + int16_t _1097 = _1095 + _1096; + return _1097; +} + +//store is: corrected.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) +hw_uint<16> hcompute_corrected_stencil_4(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_13 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_14 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_15 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1137 = (uint16_t)(10000); + uint16_t _1138 = min(_demosaicked_1_stencil_13, _1137); + int32_t _1139 = (int32_t)(_1138); + int32_t _1140 = _1139 * -96; + int32_t _1141 = _1140 >> 8; + int16_t _1142 = (int16_t)(_1141); + uint16_t _1143 = min(_demosaicked_1_stencil_14, _1137); + int32_t _1144 = (int32_t)(_1143); + int32_t _1145 = _1144 * 373; + int32_t _1146 = _1145 >> 8; + int16_t _1147 = (int16_t)(_1146); + int16_t _1148 = _1142 + _1147; + uint16_t _1149 = min(_demosaicked_1_stencil_15, _1137); + int32_t _1150 = (int32_t)(_1149); + int32_t _1151 = _1150 * 62; + int32_t _1152 = _1151 >> 8; + int16_t _1153 = (int16_t)(_1152); + int16_t _1154 = _1148 + _1153; + int16_t _1155 = (int16_t)(-29); + int16_t _1156 = _1154 + _1155; + return _1156; +} + +//store is: corrected.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) +hw_uint<16> hcompute_corrected_stencil_5(hw_uint<48>& demosaicked_1_stencil) { + uint16_t _demosaicked_1_stencil_16 = (uint16_t) demosaicked_1_stencil.extract<0, 15>(); + uint16_t _demosaicked_1_stencil_17 = (uint16_t) demosaicked_1_stencil.extract<16, 31>(); + uint16_t _demosaicked_1_stencil_18 = (uint16_t) demosaicked_1_stencil.extract<32, 47>(); + + uint16_t _1196 = (uint16_t)(10000); + uint16_t _1197 = min(_demosaicked_1_stencil_16, _1196); + int32_t _1198 = (int32_t)(_1197); + int32_t _1199 = _1198 * -31; + int32_t _1200 = _1199 >> 8; + int16_t _1201 = (int16_t)(_1200); + uint16_t _1202 = min(_demosaicked_1_stencil_17, _1196); + int32_t _1203 = (int32_t)(_1202); + int32_t _1204 = _1203 * -261; + int32_t _1205 = _1204 >> 8; + int16_t _1206 = (int16_t)(_1205); + int16_t _1207 = _1201 + _1206; + uint16_t _1208 = min(_demosaicked_1_stencil_18, _1196); + int32_t _1209 = (int32_t)(_1208); + int32_t _1210 = _1209 * 883; + int32_t _1211 = _1210 >> 8; + int16_t _1212 = (int16_t)(_1211); + int16_t _1213 = _1207 + _1212; + int16_t _1214 = (int16_t)(-22); + int16_t _1215 = _1213 + _1214; + return _1215; +} + +//store is: curved.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_1 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _2279 = (uint16_t)(0); + _curvea0[0] = _2279; + uint16_t _2280 = (uint16_t)(4); + _curvea0[1] = _2280; + uint16_t _2281 = (uint16_t)(7); + _curvea0[2] = _2281; + uint16_t _2282 = (uint16_t)(8); + _curvea0[3] = _2282; + uint16_t _2283 = (uint16_t)(10); + _curvea0[4] = _2283; + uint16_t _2284 = (uint16_t)(11); + _curvea0[5] = _2284; + uint16_t _2285 = (uint16_t)(12); + _curvea0[6] = _2285; + uint16_t _2286 = (uint16_t)(13); + _curvea0[7] = _2286; + uint16_t _2287 = (uint16_t)(14); + _curvea0[8] = _2287; + uint16_t _2288 = (uint16_t)(15); + _curvea0[9] = _2288; + uint16_t _2289 = (uint16_t)(16); + _curvea0[10] = _2289; + uint16_t _2290 = (uint16_t)(17); + _curvea0[11] = _2290; + uint16_t _2291 = (uint16_t)(18); + _curvea0[12] = _2291; + uint16_t _2292 = (uint16_t)(19); + _curvea0[13] = _2292; + uint16_t _2293 = (uint16_t)(20); + _curvea0[14] = _2293; + uint16_t _2294 = (uint16_t)(21); + _curvea0[15] = _2294; + uint16_t _2295 = (uint16_t)(22); + _curvea0[16] = _2295; + uint16_t _2296 = (uint16_t)(22); + _curvea0[17] = _2296; + uint16_t _2297 = (uint16_t)(23); + _curvea0[18] = _2297; + uint16_t _2298 = (uint16_t)(24); + _curvea0[19] = _2298; + uint16_t _2299 = (uint16_t)(25); + _curvea0[20] = _2299; + uint16_t _2300 = (uint16_t)(25); + _curvea0[21] = _2300; + uint16_t _2301 = (uint16_t)(26); + _curvea0[22] = _2301; + uint16_t _2302 = (uint16_t)(27); + _curvea0[23] = _2302; + uint16_t _2303 = (uint16_t)(27); + _curvea0[24] = _2303; + uint16_t _2304 = (uint16_t)(28); + _curvea0[25] = _2304; + uint16_t _2305 = (uint16_t)(29); + _curvea0[26] = _2305; + uint16_t _2306 = (uint16_t)(29); + _curvea0[27] = _2306; + uint16_t _2307 = (uint16_t)(30); + _curvea0[28] = _2307; + uint16_t _2308 = (uint16_t)(31); + _curvea0[29] = _2308; + uint16_t _2309 = (uint16_t)(31); + _curvea0[30] = _2309; + uint16_t _2310 = (uint16_t)(32); + _curvea0[31] = _2310; + uint16_t _2311 = (uint16_t)(33); + _curvea0[32] = _2311; + uint16_t _2312 = (uint16_t)(33); + _curvea0[33] = _2312; + uint16_t _2313 = (uint16_t)(34); + _curvea0[34] = _2313; + uint16_t _2314 = (uint16_t)(34); + _curvea0[35] = _2314; + uint16_t _2315 = (uint16_t)(35); + _curvea0[36] = _2315; + uint16_t _2316 = (uint16_t)(36); + _curvea0[37] = _2316; + uint16_t _2317 = (uint16_t)(36); + _curvea0[38] = _2317; + uint16_t _2318 = (uint16_t)(37); + _curvea0[39] = _2318; + uint16_t _2319 = (uint16_t)(37); + _curvea0[40] = _2319; + uint16_t _2320 = (uint16_t)(38); + _curvea0[41] = _2320; + uint16_t _2321 = (uint16_t)(39); + _curvea0[42] = _2321; + uint16_t _2322 = (uint16_t)(39); + _curvea0[43] = _2322; + uint16_t _2323 = (uint16_t)(40); + _curvea0[44] = _2323; + uint16_t _2324 = (uint16_t)(40); + _curvea0[45] = _2324; + uint16_t _2325 = (uint16_t)(41); + _curvea0[46] = _2325; + uint16_t _2326 = (uint16_t)(41); + _curvea0[47] = _2326; + uint16_t _2327 = (uint16_t)(42); + _curvea0[48] = _2327; + uint16_t _2328 = (uint16_t)(42); + _curvea0[49] = _2328; + uint16_t _2329 = (uint16_t)(43); + _curvea0[50] = _2329; + uint16_t _2330 = (uint16_t)(44); + _curvea0[51] = _2330; + uint16_t _2331 = (uint16_t)(44); + _curvea0[52] = _2331; + uint16_t _2332 = (uint16_t)(45); + _curvea0[53] = _2332; + uint16_t _2333 = (uint16_t)(45); + _curvea0[54] = _2333; + uint16_t _2334 = (uint16_t)(46); + _curvea0[55] = _2334; + uint16_t _2335 = (uint16_t)(46); + _curvea0[56] = _2335; + uint16_t _2336 = (uint16_t)(47); + _curvea0[57] = _2336; + uint16_t _2337 = (uint16_t)(47); + _curvea0[58] = _2337; + uint16_t _2338 = (uint16_t)(48); + _curvea0[59] = _2338; + uint16_t _2339 = (uint16_t)(48); + _curvea0[60] = _2339; + uint16_t _2340 = (uint16_t)(49); + _curvea0[61] = _2340; + uint16_t _2341 = (uint16_t)(49); + _curvea0[62] = _2341; + uint16_t _2342 = (uint16_t)(50); + _curvea0[63] = _2342; + uint16_t _2343 = (uint16_t)(50); + _curvea0[64] = _2343; + uint16_t _2344 = (uint16_t)(51); + _curvea0[65] = _2344; + uint16_t _2345 = (uint16_t)(51); + _curvea0[66] = _2345; + uint16_t _2346 = (uint16_t)(52); + _curvea0[67] = _2346; + uint16_t _2347 = (uint16_t)(52); + _curvea0[68] = _2347; + uint16_t _2348 = (uint16_t)(53); + _curvea0[69] = _2348; + uint16_t _2349 = (uint16_t)(53); + _curvea0[70] = _2349; + uint16_t _2350 = (uint16_t)(54); + _curvea0[71] = _2350; + uint16_t _2351 = (uint16_t)(54); + _curvea0[72] = _2351; + uint16_t _2352 = (uint16_t)(55); + _curvea0[73] = _2352; + uint16_t _2353 = (uint16_t)(55); + _curvea0[74] = _2353; + uint16_t _2354 = (uint16_t)(56); + _curvea0[75] = _2354; + uint16_t _2355 = (uint16_t)(56); + _curvea0[76] = _2355; + uint16_t _2356 = (uint16_t)(57); + _curvea0[77] = _2356; + uint16_t _2357 = (uint16_t)(57); + _curvea0[78] = _2357; + uint16_t _2358 = (uint16_t)(58); + _curvea0[79] = _2358; + uint16_t _2359 = (uint16_t)(58); + _curvea0[80] = _2359; + uint16_t _2360 = (uint16_t)(58); + _curvea0[81] = _2360; + uint16_t _2361 = (uint16_t)(59); + _curvea0[82] = _2361; + uint16_t _2362 = (uint16_t)(59); + _curvea0[83] = _2362; + uint16_t _2363 = (uint16_t)(60); + _curvea0[84] = _2363; + uint16_t _2364 = (uint16_t)(60); + _curvea0[85] = _2364; + uint16_t _2365 = (uint16_t)(61); + _curvea0[86] = _2365; + uint16_t _2366 = (uint16_t)(61); + _curvea0[87] = _2366; + uint16_t _2367 = (uint16_t)(62); + _curvea0[88] = _2367; + uint16_t _2368 = (uint16_t)(62); + _curvea0[89] = _2368; + uint16_t _2369 = (uint16_t)(63); + _curvea0[90] = _2369; + uint16_t _2370 = (uint16_t)(63); + _curvea0[91] = _2370; + uint16_t _2371 = (uint16_t)(64); + _curvea0[92] = _2371; + uint16_t _2372 = (uint16_t)(64); + _curvea0[93] = _2372; + uint16_t _2373 = (uint16_t)(64); + _curvea0[94] = _2373; + uint16_t _2374 = (uint16_t)(65); + _curvea0[95] = _2374; + uint16_t _2375 = (uint16_t)(65); + _curvea0[96] = _2375; + uint16_t _2376 = (uint16_t)(66); + _curvea0[97] = _2376; + uint16_t _2377 = (uint16_t)(66); + _curvea0[98] = _2377; + uint16_t _2378 = (uint16_t)(67); + _curvea0[99] = _2378; + uint16_t _2379 = (uint16_t)(67); + _curvea0[100] = _2379; + uint16_t _2380 = (uint16_t)(68); + _curvea0[101] = _2380; + uint16_t _2381 = (uint16_t)(68); + _curvea0[102] = _2381; + uint16_t _2382 = (uint16_t)(68); + _curvea0[103] = _2382; + uint16_t _2383 = (uint16_t)(69); + _curvea0[104] = _2383; + uint16_t _2384 = (uint16_t)(69); + _curvea0[105] = _2384; + uint16_t _2385 = (uint16_t)(70); + _curvea0[106] = _2385; + uint16_t _2386 = (uint16_t)(70); + _curvea0[107] = _2386; + uint16_t _2387 = (uint16_t)(71); + _curvea0[108] = _2387; + uint16_t _2388 = (uint16_t)(71); + _curvea0[109] = _2388; + uint16_t _2389 = (uint16_t)(71); + _curvea0[110] = _2389; + uint16_t _2390 = (uint16_t)(72); + _curvea0[111] = _2390; + uint16_t _2391 = (uint16_t)(72); + _curvea0[112] = _2391; + uint16_t _2392 = (uint16_t)(73); + _curvea0[113] = _2392; + uint16_t _2393 = (uint16_t)(73); + _curvea0[114] = _2393; + uint16_t _2394 = (uint16_t)(74); + _curvea0[115] = _2394; + uint16_t _2395 = (uint16_t)(74); + _curvea0[116] = _2395; + uint16_t _2396 = (uint16_t)(74); + _curvea0[117] = _2396; + uint16_t _2397 = (uint16_t)(75); + _curvea0[118] = _2397; + uint16_t _2398 = (uint16_t)(75); + _curvea0[119] = _2398; + uint16_t _2399 = (uint16_t)(76); + _curvea0[120] = _2399; + uint16_t _2400 = (uint16_t)(76); + _curvea0[121] = _2400; + uint16_t _2401 = (uint16_t)(77); + _curvea0[122] = _2401; + uint16_t _2402 = (uint16_t)(77); + _curvea0[123] = _2402; + uint16_t _2403 = (uint16_t)(77); + _curvea0[124] = _2403; + uint16_t _2404 = (uint16_t)(78); + _curvea0[125] = _2404; + uint16_t _2405 = (uint16_t)(78); + _curvea0[126] = _2405; + uint16_t _2406 = (uint16_t)(79); + _curvea0[127] = _2406; + uint16_t _2407 = (uint16_t)(79); + _curvea0[128] = _2407; + uint16_t _2408 = (uint16_t)(79); + _curvea0[129] = _2408; + uint16_t _2409 = (uint16_t)(80); + _curvea0[130] = _2409; + uint16_t _2410 = (uint16_t)(80); + _curvea0[131] = _2410; + uint16_t _2411 = (uint16_t)(81); + _curvea0[132] = _2411; + uint16_t _2412 = (uint16_t)(81); + _curvea0[133] = _2412; + uint16_t _2413 = (uint16_t)(82); + _curvea0[134] = _2413; + uint16_t _2414 = (uint16_t)(82); + _curvea0[135] = _2414; + uint16_t _2415 = (uint16_t)(82); + _curvea0[136] = _2415; + uint16_t _2416 = (uint16_t)(83); + _curvea0[137] = _2416; + uint16_t _2417 = (uint16_t)(83); + _curvea0[138] = _2417; + uint16_t _2418 = (uint16_t)(84); + _curvea0[139] = _2418; + uint16_t _2419 = (uint16_t)(84); + _curvea0[140] = _2419; + uint16_t _2420 = (uint16_t)(84); + _curvea0[141] = _2420; + uint16_t _2421 = (uint16_t)(85); + _curvea0[142] = _2421; + uint16_t _2422 = (uint16_t)(85); + _curvea0[143] = _2422; + uint16_t _2423 = (uint16_t)(86); + _curvea0[144] = _2423; + uint16_t _2424 = (uint16_t)(86); + _curvea0[145] = _2424; + uint16_t _2425 = (uint16_t)(86); + _curvea0[146] = _2425; + uint16_t _2426 = (uint16_t)(87); + _curvea0[147] = _2426; + uint16_t _2427 = (uint16_t)(87); + _curvea0[148] = _2427; + uint16_t _2428 = (uint16_t)(88); + _curvea0[149] = _2428; + uint16_t _2429 = (uint16_t)(88); + _curvea0[150] = _2429; + uint16_t _2430 = (uint16_t)(88); + _curvea0[151] = _2430; + uint16_t _2431 = (uint16_t)(89); + _curvea0[152] = _2431; + uint16_t _2432 = (uint16_t)(89); + _curvea0[153] = _2432; + uint16_t _2433 = (uint16_t)(90); + _curvea0[154] = _2433; + uint16_t _2434 = (uint16_t)(90); + _curvea0[155] = _2434; + uint16_t _2435 = (uint16_t)(90); + _curvea0[156] = _2435; + uint16_t _2436 = (uint16_t)(91); + _curvea0[157] = _2436; + uint16_t _2437 = (uint16_t)(91); + _curvea0[158] = _2437; + uint16_t _2438 = (uint16_t)(92); + _curvea0[159] = _2438; + uint16_t _2439 = (uint16_t)(92); + _curvea0[160] = _2439; + uint16_t _2440 = (uint16_t)(92); + _curvea0[161] = _2440; + uint16_t _2441 = (uint16_t)(93); + _curvea0[162] = _2441; + uint16_t _2442 = (uint16_t)(93); + _curvea0[163] = _2442; + uint16_t _2443 = (uint16_t)(93); + _curvea0[164] = _2443; + uint16_t _2444 = (uint16_t)(94); + _curvea0[165] = _2444; + uint16_t _2445 = (uint16_t)(94); + _curvea0[166] = _2445; + uint16_t _2446 = (uint16_t)(95); + _curvea0[167] = _2446; + uint16_t _2447 = (uint16_t)(95); + _curvea0[168] = _2447; + uint16_t _2448 = (uint16_t)(95); + _curvea0[169] = _2448; + uint16_t _2449 = (uint16_t)(96); + _curvea0[170] = _2449; + uint16_t _2450 = (uint16_t)(96); + _curvea0[171] = _2450; + uint16_t _2451 = (uint16_t)(97); + _curvea0[172] = _2451; + uint16_t _2452 = (uint16_t)(97); + _curvea0[173] = _2452; + uint16_t _2453 = (uint16_t)(97); + _curvea0[174] = _2453; + uint16_t _2454 = (uint16_t)(98); + _curvea0[175] = _2454; + uint16_t _2455 = (uint16_t)(98); + _curvea0[176] = _2455; + uint16_t _2456 = (uint16_t)(99); + _curvea0[177] = _2456; + uint16_t _2457 = (uint16_t)(99); + _curvea0[178] = _2457; + uint16_t _2458 = (uint16_t)(99); + _curvea0[179] = _2458; + uint16_t _2459 = (uint16_t)(100); + _curvea0[180] = _2459; + uint16_t _2460 = (uint16_t)(100); + _curvea0[181] = _2460; + uint16_t _2461 = (uint16_t)(100); + _curvea0[182] = _2461; + uint16_t _2462 = (uint16_t)(101); + _curvea0[183] = _2462; + uint16_t _2463 = (uint16_t)(101); + _curvea0[184] = _2463; + uint16_t _2464 = (uint16_t)(102); + _curvea0[185] = _2464; + uint16_t _2465 = (uint16_t)(102); + _curvea0[186] = _2465; + uint16_t _2466 = (uint16_t)(102); + _curvea0[187] = _2466; + uint16_t _2467 = (uint16_t)(103); + _curvea0[188] = _2467; + uint16_t _2468 = (uint16_t)(103); + _curvea0[189] = _2468; + uint16_t _2469 = (uint16_t)(103); + _curvea0[190] = _2469; + uint16_t _2470 = (uint16_t)(104); + _curvea0[191] = _2470; + uint16_t _2471 = (uint16_t)(104); + _curvea0[192] = _2471; + uint16_t _2472 = (uint16_t)(105); + _curvea0[193] = _2472; + uint16_t _2473 = (uint16_t)(105); + _curvea0[194] = _2473; + uint16_t _2474 = (uint16_t)(105); + _curvea0[195] = _2474; + uint16_t _2475 = (uint16_t)(106); + _curvea0[196] = _2475; + uint16_t _2476 = (uint16_t)(106); + _curvea0[197] = _2476; + uint16_t _2477 = (uint16_t)(106); + _curvea0[198] = _2477; + uint16_t _2478 = (uint16_t)(107); + _curvea0[199] = _2478; + uint16_t _2479 = (uint16_t)(107); + _curvea0[200] = _2479; + uint16_t _2480 = (uint16_t)(108); + _curvea0[201] = _2480; + uint16_t _2481 = (uint16_t)(108); + _curvea0[202] = _2481; + uint16_t _2482 = (uint16_t)(108); + _curvea0[203] = _2482; + uint16_t _2483 = (uint16_t)(109); + _curvea0[204] = _2483; + uint16_t _2484 = (uint16_t)(109); + _curvea0[205] = _2484; + uint16_t _2485 = (uint16_t)(109); + _curvea0[206] = _2485; + uint16_t _2486 = (uint16_t)(110); + _curvea0[207] = _2486; + uint16_t _2487 = (uint16_t)(110); + _curvea0[208] = _2487; + uint16_t _2488 = (uint16_t)(111); + _curvea0[209] = _2488; + uint16_t _2489 = (uint16_t)(111); + _curvea0[210] = _2489; + uint16_t _2490 = (uint16_t)(111); + _curvea0[211] = _2490; + uint16_t _2491 = (uint16_t)(112); + _curvea0[212] = _2491; + uint16_t _2492 = (uint16_t)(112); + _curvea0[213] = _2492; + uint16_t _2493 = (uint16_t)(112); + _curvea0[214] = _2493; + uint16_t _2494 = (uint16_t)(113); + _curvea0[215] = _2494; + uint16_t _2495 = (uint16_t)(113); + _curvea0[216] = _2495; + uint16_t _2496 = (uint16_t)(113); + _curvea0[217] = _2496; + uint16_t _2497 = (uint16_t)(114); + _curvea0[218] = _2497; + uint16_t _2498 = (uint16_t)(114); + _curvea0[219] = _2498; + uint16_t _2499 = (uint16_t)(115); + _curvea0[220] = _2499; + uint16_t _2500 = (uint16_t)(115); + _curvea0[221] = _2500; + uint16_t _2501 = (uint16_t)(115); + _curvea0[222] = _2501; + uint16_t _2502 = (uint16_t)(116); + _curvea0[223] = _2502; + uint16_t _2503 = (uint16_t)(116); + _curvea0[224] = _2503; + uint16_t _2504 = (uint16_t)(116); + _curvea0[225] = _2504; + uint16_t _2505 = (uint16_t)(117); + _curvea0[226] = _2505; + uint16_t _2506 = (uint16_t)(117); + _curvea0[227] = _2506; + uint16_t _2507 = (uint16_t)(117); + _curvea0[228] = _2507; + uint16_t _2508 = (uint16_t)(118); + _curvea0[229] = _2508; + uint16_t _2509 = (uint16_t)(118); + _curvea0[230] = _2509; + uint16_t _2510 = (uint16_t)(119); + _curvea0[231] = _2510; + uint16_t _2511 = (uint16_t)(119); + _curvea0[232] = _2511; + uint16_t _2512 = (uint16_t)(119); + _curvea0[233] = _2512; + uint16_t _2513 = (uint16_t)(120); + _curvea0[234] = _2513; + uint16_t _2514 = (uint16_t)(120); + _curvea0[235] = _2514; + uint16_t _2515 = (uint16_t)(120); + _curvea0[236] = _2515; + uint16_t _2516 = (uint16_t)(121); + _curvea0[237] = _2516; + uint16_t _2517 = (uint16_t)(121); + _curvea0[238] = _2517; + uint16_t _2518 = (uint16_t)(121); + _curvea0[239] = _2518; + uint16_t _2519 = (uint16_t)(122); + _curvea0[240] = _2519; + uint16_t _2520 = (uint16_t)(122); + _curvea0[241] = _2520; + uint16_t _2521 = (uint16_t)(123); + _curvea0[242] = _2521; + uint16_t _2522 = (uint16_t)(123); + _curvea0[243] = _2522; + uint16_t _2523 = (uint16_t)(123); + _curvea0[244] = _2523; + uint16_t _2524 = (uint16_t)(124); + _curvea0[245] = _2524; + uint16_t _2525 = (uint16_t)(124); + _curvea0[246] = _2525; + uint16_t _2526 = (uint16_t)(124); + _curvea0[247] = _2526; + uint16_t _2527 = (uint16_t)(125); + _curvea0[248] = _2527; + uint16_t _2528 = (uint16_t)(125); + _curvea0[249] = _2528; + uint16_t _2529 = (uint16_t)(125); + _curvea0[250] = _2529; + uint16_t _2530 = (uint16_t)(126); + _curvea0[251] = _2530; + uint16_t _2531 = (uint16_t)(126); + _curvea0[252] = _2531; + uint16_t _2532 = (uint16_t)(126); + _curvea0[253] = _2532; + uint16_t _2533 = (uint16_t)(127); + _curvea0[254] = _2533; + uint16_t _2534 = (uint16_t)(127); + _curvea0[255] = _2534; + uint16_t _2535 = (uint16_t)(128); + _curvea0[256] = _2535; + uint16_t _2536 = (uint16_t)(128); + _curvea0[257] = _2536; + uint16_t _2537 = (uint16_t)(128); + _curvea0[258] = _2537; + uint16_t _2538 = (uint16_t)(129); + _curvea0[259] = _2538; + uint16_t _2539 = (uint16_t)(129); + _curvea0[260] = _2539; + uint16_t _2540 = (uint16_t)(129); + _curvea0[261] = _2540; + uint16_t _2541 = (uint16_t)(130); + _curvea0[262] = _2541; + uint16_t _2542 = (uint16_t)(130); + _curvea0[263] = _2542; + uint16_t _2543 = (uint16_t)(130); + _curvea0[264] = _2543; + uint16_t _2544 = (uint16_t)(131); + _curvea0[265] = _2544; + uint16_t _2545 = (uint16_t)(131); + _curvea0[266] = _2545; + uint16_t _2546 = (uint16_t)(131); + _curvea0[267] = _2546; + uint16_t _2547 = (uint16_t)(132); + _curvea0[268] = _2547; + uint16_t _2548 = (uint16_t)(132); + _curvea0[269] = _2548; + uint16_t _2549 = (uint16_t)(132); + _curvea0[270] = _2549; + uint16_t _2550 = (uint16_t)(133); + _curvea0[271] = _2550; + uint16_t _2551 = (uint16_t)(133); + _curvea0[272] = _2551; + uint16_t _2552 = (uint16_t)(133); + _curvea0[273] = _2552; + uint16_t _2553 = (uint16_t)(134); + _curvea0[274] = _2553; + uint16_t _2554 = (uint16_t)(134); + _curvea0[275] = _2554; + uint16_t _2555 = (uint16_t)(134); + _curvea0[276] = _2555; + uint16_t _2556 = (uint16_t)(135); + _curvea0[277] = _2556; + uint16_t _2557 = (uint16_t)(135); + _curvea0[278] = _2557; + uint16_t _2558 = (uint16_t)(135); + _curvea0[279] = _2558; + uint16_t _2559 = (uint16_t)(136); + _curvea0[280] = _2559; + uint16_t _2560 = (uint16_t)(136); + _curvea0[281] = _2560; + uint16_t _2561 = (uint16_t)(136); + _curvea0[282] = _2561; + uint16_t _2562 = (uint16_t)(137); + _curvea0[283] = _2562; + uint16_t _2563 = (uint16_t)(137); + _curvea0[284] = _2563; + uint16_t _2564 = (uint16_t)(137); + _curvea0[285] = _2564; + uint16_t _2565 = (uint16_t)(138); + _curvea0[286] = _2565; + uint16_t _2566 = (uint16_t)(138); + _curvea0[287] = _2566; + uint16_t _2567 = (uint16_t)(138); + _curvea0[288] = _2567; + uint16_t _2568 = (uint16_t)(139); + _curvea0[289] = _2568; + uint16_t _2569 = (uint16_t)(139); + _curvea0[290] = _2569; + uint16_t _2570 = (uint16_t)(139); + _curvea0[291] = _2570; + uint16_t _2571 = (uint16_t)(140); + _curvea0[292] = _2571; + uint16_t _2572 = (uint16_t)(140); + _curvea0[293] = _2572; + uint16_t _2573 = (uint16_t)(140); + _curvea0[294] = _2573; + uint16_t _2574 = (uint16_t)(141); + _curvea0[295] = _2574; + uint16_t _2575 = (uint16_t)(141); + _curvea0[296] = _2575; + uint16_t _2576 = (uint16_t)(141); + _curvea0[297] = _2576; + uint16_t _2577 = (uint16_t)(141); + _curvea0[298] = _2577; + uint16_t _2578 = (uint16_t)(142); + _curvea0[299] = _2578; + uint16_t _2579 = (uint16_t)(142); + _curvea0[300] = _2579; + uint16_t _2580 = (uint16_t)(142); + _curvea0[301] = _2580; + uint16_t _2581 = (uint16_t)(143); + _curvea0[302] = _2581; + uint16_t _2582 = (uint16_t)(143); + _curvea0[303] = _2582; + uint16_t _2583 = (uint16_t)(143); + _curvea0[304] = _2583; + uint16_t _2584 = (uint16_t)(144); + _curvea0[305] = _2584; + uint16_t _2585 = (uint16_t)(144); + _curvea0[306] = _2585; + uint16_t _2586 = (uint16_t)(144); + _curvea0[307] = _2586; + uint16_t _2587 = (uint16_t)(145); + _curvea0[308] = _2587; + uint16_t _2588 = (uint16_t)(145); + _curvea0[309] = _2588; + uint16_t _2589 = (uint16_t)(145); + _curvea0[310] = _2589; + uint16_t _2590 = (uint16_t)(145); + _curvea0[311] = _2590; + uint16_t _2591 = (uint16_t)(146); + _curvea0[312] = _2591; + uint16_t _2592 = (uint16_t)(146); + _curvea0[313] = _2592; + uint16_t _2593 = (uint16_t)(146); + _curvea0[314] = _2593; + uint16_t _2594 = (uint16_t)(147); + _curvea0[315] = _2594; + uint16_t _2595 = (uint16_t)(147); + _curvea0[316] = _2595; + uint16_t _2596 = (uint16_t)(147); + _curvea0[317] = _2596; + uint16_t _2597 = (uint16_t)(148); + _curvea0[318] = _2597; + uint16_t _2598 = (uint16_t)(148); + _curvea0[319] = _2598; + uint16_t _2599 = (uint16_t)(148); + _curvea0[320] = _2599; + uint16_t _2600 = (uint16_t)(148); + _curvea0[321] = _2600; + uint16_t _2601 = (uint16_t)(149); + _curvea0[322] = _2601; + uint16_t _2602 = (uint16_t)(149); + _curvea0[323] = _2602; + uint16_t _2603 = (uint16_t)(149); + _curvea0[324] = _2603; + uint16_t _2604 = (uint16_t)(150); + _curvea0[325] = _2604; + uint16_t _2605 = (uint16_t)(150); + _curvea0[326] = _2605; + uint16_t _2606 = (uint16_t)(150); + _curvea0[327] = _2606; + uint16_t _2607 = (uint16_t)(150); + _curvea0[328] = _2607; + uint16_t _2608 = (uint16_t)(151); + _curvea0[329] = _2608; + uint16_t _2609 = (uint16_t)(151); + _curvea0[330] = _2609; + uint16_t _2610 = (uint16_t)(151); + _curvea0[331] = _2610; + uint16_t _2611 = (uint16_t)(152); + _curvea0[332] = _2611; + uint16_t _2612 = (uint16_t)(152); + _curvea0[333] = _2612; + uint16_t _2613 = (uint16_t)(152); + _curvea0[334] = _2613; + uint16_t _2614 = (uint16_t)(152); + _curvea0[335] = _2614; + uint16_t _2615 = (uint16_t)(153); + _curvea0[336] = _2615; + uint16_t _2616 = (uint16_t)(153); + _curvea0[337] = _2616; + uint16_t _2617 = (uint16_t)(153); + _curvea0[338] = _2617; + uint16_t _2618 = (uint16_t)(154); + _curvea0[339] = _2618; + uint16_t _2619 = (uint16_t)(154); + _curvea0[340] = _2619; + uint16_t _2620 = (uint16_t)(154); + _curvea0[341] = _2620; + uint16_t _2621 = (uint16_t)(154); + _curvea0[342] = _2621; + uint16_t _2622 = (uint16_t)(155); + _curvea0[343] = _2622; + uint16_t _2623 = (uint16_t)(155); + _curvea0[344] = _2623; + uint16_t _2624 = (uint16_t)(155); + _curvea0[345] = _2624; + uint16_t _2625 = (uint16_t)(156); + _curvea0[346] = _2625; + uint16_t _2626 = (uint16_t)(156); + _curvea0[347] = _2626; + uint16_t _2627 = (uint16_t)(156); + _curvea0[348] = _2627; + uint16_t _2628 = (uint16_t)(156); + _curvea0[349] = _2628; + uint16_t _2629 = (uint16_t)(157); + _curvea0[350] = _2629; + uint16_t _2630 = (uint16_t)(157); + _curvea0[351] = _2630; + uint16_t _2631 = (uint16_t)(157); + _curvea0[352] = _2631; + uint16_t _2632 = (uint16_t)(157); + _curvea0[353] = _2632; + uint16_t _2633 = (uint16_t)(158); + _curvea0[354] = _2633; + uint16_t _2634 = (uint16_t)(158); + _curvea0[355] = _2634; + uint16_t _2635 = (uint16_t)(158); + _curvea0[356] = _2635; + uint16_t _2636 = (uint16_t)(159); + _curvea0[357] = _2636; + uint16_t _2637 = (uint16_t)(159); + _curvea0[358] = _2637; + uint16_t _2638 = (uint16_t)(159); + _curvea0[359] = _2638; + uint16_t _2639 = (uint16_t)(159); + _curvea0[360] = _2639; + uint16_t _2640 = (uint16_t)(160); + _curvea0[361] = _2640; + uint16_t _2641 = (uint16_t)(160); + _curvea0[362] = _2641; + uint16_t _2642 = (uint16_t)(160); + _curvea0[363] = _2642; + uint16_t _2643 = (uint16_t)(160); + _curvea0[364] = _2643; + uint16_t _2644 = (uint16_t)(161); + _curvea0[365] = _2644; + uint16_t _2645 = (uint16_t)(161); + _curvea0[366] = _2645; + uint16_t _2646 = (uint16_t)(161); + _curvea0[367] = _2646; + uint16_t _2647 = (uint16_t)(161); + _curvea0[368] = _2647; + uint16_t _2648 = (uint16_t)(162); + _curvea0[369] = _2648; + uint16_t _2649 = (uint16_t)(162); + _curvea0[370] = _2649; + uint16_t _2650 = (uint16_t)(162); + _curvea0[371] = _2650; + uint16_t _2651 = (uint16_t)(162); + _curvea0[372] = _2651; + uint16_t _2652 = (uint16_t)(163); + _curvea0[373] = _2652; + uint16_t _2653 = (uint16_t)(163); + _curvea0[374] = _2653; + uint16_t _2654 = (uint16_t)(163); + _curvea0[375] = _2654; + uint16_t _2655 = (uint16_t)(163); + _curvea0[376] = _2655; + uint16_t _2656 = (uint16_t)(164); + _curvea0[377] = _2656; + uint16_t _2657 = (uint16_t)(164); + _curvea0[378] = _2657; + uint16_t _2658 = (uint16_t)(164); + _curvea0[379] = _2658; + uint16_t _2659 = (uint16_t)(164); + _curvea0[380] = _2659; + uint16_t _2660 = (uint16_t)(165); + _curvea0[381] = _2660; + uint16_t _2661 = (uint16_t)(165); + _curvea0[382] = _2661; + uint16_t _2662 = (uint16_t)(165); + _curvea0[383] = _2662; + uint16_t _2663 = (uint16_t)(166); + _curvea0[384] = _2663; + uint16_t _2664 = (uint16_t)(166); + _curvea0[385] = _2664; + uint16_t _2665 = (uint16_t)(166); + _curvea0[386] = _2665; + uint16_t _2666 = (uint16_t)(166); + _curvea0[387] = _2666; + uint16_t _2667 = (uint16_t)(167); + _curvea0[388] = _2667; + uint16_t _2668 = (uint16_t)(167); + _curvea0[389] = _2668; + uint16_t _2669 = (uint16_t)(167); + _curvea0[390] = _2669; + uint16_t _2670 = (uint16_t)(167); + _curvea0[391] = _2670; + uint16_t _2671 = (uint16_t)(167); + _curvea0[392] = _2671; + uint16_t _2672 = (uint16_t)(168); + _curvea0[393] = _2672; + uint16_t _2673 = (uint16_t)(168); + _curvea0[394] = _2673; + uint16_t _2674 = (uint16_t)(168); + _curvea0[395] = _2674; + uint16_t _2675 = (uint16_t)(168); + _curvea0[396] = _2675; + uint16_t _2676 = (uint16_t)(169); + _curvea0[397] = _2676; + uint16_t _2677 = (uint16_t)(169); + _curvea0[398] = _2677; + uint16_t _2678 = (uint16_t)(169); + _curvea0[399] = _2678; + uint16_t _2679 = (uint16_t)(169); + _curvea0[400] = _2679; + uint16_t _2680 = (uint16_t)(170); + _curvea0[401] = _2680; + uint16_t _2681 = (uint16_t)(170); + _curvea0[402] = _2681; + uint16_t _2682 = (uint16_t)(170); + _curvea0[403] = _2682; + uint16_t _2683 = (uint16_t)(170); + _curvea0[404] = _2683; + uint16_t _2684 = (uint16_t)(171); + _curvea0[405] = _2684; + uint16_t _2685 = (uint16_t)(171); + _curvea0[406] = _2685; + uint16_t _2686 = (uint16_t)(171); + _curvea0[407] = _2686; + uint16_t _2687 = (uint16_t)(171); + _curvea0[408] = _2687; + uint16_t _2688 = (uint16_t)(172); + _curvea0[409] = _2688; + uint16_t _2689 = (uint16_t)(172); + _curvea0[410] = _2689; + uint16_t _2690 = (uint16_t)(172); + _curvea0[411] = _2690; + uint16_t _2691 = (uint16_t)(172); + _curvea0[412] = _2691; + uint16_t _2692 = (uint16_t)(173); + _curvea0[413] = _2692; + uint16_t _2693 = (uint16_t)(173); + _curvea0[414] = _2693; + uint16_t _2694 = (uint16_t)(173); + _curvea0[415] = _2694; + uint16_t _2695 = (uint16_t)(173); + _curvea0[416] = _2695; + uint16_t _2696 = (uint16_t)(173); + _curvea0[417] = _2696; + uint16_t _2697 = (uint16_t)(174); + _curvea0[418] = _2697; + uint16_t _2698 = (uint16_t)(174); + _curvea0[419] = _2698; + uint16_t _2699 = (uint16_t)(174); + _curvea0[420] = _2699; + uint16_t _2700 = (uint16_t)(174); + _curvea0[421] = _2700; + uint16_t _2701 = (uint16_t)(175); + _curvea0[422] = _2701; + uint16_t _2702 = (uint16_t)(175); + _curvea0[423] = _2702; + uint16_t _2703 = (uint16_t)(175); + _curvea0[424] = _2703; + uint16_t _2704 = (uint16_t)(175); + _curvea0[425] = _2704; + uint16_t _2705 = (uint16_t)(176); + _curvea0[426] = _2705; + uint16_t _2706 = (uint16_t)(176); + _curvea0[427] = _2706; + uint16_t _2707 = (uint16_t)(176); + _curvea0[428] = _2707; + uint16_t _2708 = (uint16_t)(176); + _curvea0[429] = _2708; + uint16_t _2709 = (uint16_t)(176); + _curvea0[430] = _2709; + uint16_t _2710 = (uint16_t)(177); + _curvea0[431] = _2710; + uint16_t _2711 = (uint16_t)(177); + _curvea0[432] = _2711; + uint16_t _2712 = (uint16_t)(177); + _curvea0[433] = _2712; + uint16_t _2713 = (uint16_t)(177); + _curvea0[434] = _2713; + uint16_t _2714 = (uint16_t)(178); + _curvea0[435] = _2714; + uint16_t _2715 = (uint16_t)(178); + _curvea0[436] = _2715; + uint16_t _2716 = (uint16_t)(178); + _curvea0[437] = _2716; + uint16_t _2717 = (uint16_t)(178); + _curvea0[438] = _2717; + uint16_t _2718 = (uint16_t)(178); + _curvea0[439] = _2718; + uint16_t _2719 = (uint16_t)(179); + _curvea0[440] = _2719; + uint16_t _2720 = (uint16_t)(179); + _curvea0[441] = _2720; + uint16_t _2721 = (uint16_t)(179); + _curvea0[442] = _2721; + uint16_t _2722 = (uint16_t)(179); + _curvea0[443] = _2722; + uint16_t _2723 = (uint16_t)(180); + _curvea0[444] = _2723; + uint16_t _2724 = (uint16_t)(180); + _curvea0[445] = _2724; + uint16_t _2725 = (uint16_t)(180); + _curvea0[446] = _2725; + uint16_t _2726 = (uint16_t)(180); + _curvea0[447] = _2726; + uint16_t _2727 = (uint16_t)(180); + _curvea0[448] = _2727; + uint16_t _2728 = (uint16_t)(181); + _curvea0[449] = _2728; + uint16_t _2729 = (uint16_t)(181); + _curvea0[450] = _2729; + uint16_t _2730 = (uint16_t)(181); + _curvea0[451] = _2730; + uint16_t _2731 = (uint16_t)(181); + _curvea0[452] = _2731; + uint16_t _2732 = (uint16_t)(181); + _curvea0[453] = _2732; + uint16_t _2733 = (uint16_t)(182); + _curvea0[454] = _2733; + uint16_t _2734 = (uint16_t)(182); + _curvea0[455] = _2734; + uint16_t _2735 = (uint16_t)(182); + _curvea0[456] = _2735; + uint16_t _2736 = (uint16_t)(182); + _curvea0[457] = _2736; + uint16_t _2737 = (uint16_t)(183); + _curvea0[458] = _2737; + uint16_t _2738 = (uint16_t)(183); + _curvea0[459] = _2738; + uint16_t _2739 = (uint16_t)(183); + _curvea0[460] = _2739; + uint16_t _2740 = (uint16_t)(183); + _curvea0[461] = _2740; + uint16_t _2741 = (uint16_t)(183); + _curvea0[462] = _2741; + uint16_t _2742 = (uint16_t)(184); + _curvea0[463] = _2742; + uint16_t _2743 = (uint16_t)(184); + _curvea0[464] = _2743; + uint16_t _2744 = (uint16_t)(184); + _curvea0[465] = _2744; + uint16_t _2745 = (uint16_t)(184); + _curvea0[466] = _2745; + uint16_t _2746 = (uint16_t)(184); + _curvea0[467] = _2746; + uint16_t _2747 = (uint16_t)(185); + _curvea0[468] = _2747; + uint16_t _2748 = (uint16_t)(185); + _curvea0[469] = _2748; + uint16_t _2749 = (uint16_t)(185); + _curvea0[470] = _2749; + uint16_t _2750 = (uint16_t)(185); + _curvea0[471] = _2750; + uint16_t _2751 = (uint16_t)(185); + _curvea0[472] = _2751; + uint16_t _2752 = (uint16_t)(186); + _curvea0[473] = _2752; + uint16_t _2753 = (uint16_t)(186); + _curvea0[474] = _2753; + uint16_t _2754 = (uint16_t)(186); + _curvea0[475] = _2754; + uint16_t _2755 = (uint16_t)(186); + _curvea0[476] = _2755; + uint16_t _2756 = (uint16_t)(187); + _curvea0[477] = _2756; + uint16_t _2757 = (uint16_t)(187); + _curvea0[478] = _2757; + uint16_t _2758 = (uint16_t)(187); + _curvea0[479] = _2758; + uint16_t _2759 = (uint16_t)(187); + _curvea0[480] = _2759; + uint16_t _2760 = (uint16_t)(187); + _curvea0[481] = _2760; + uint16_t _2761 = (uint16_t)(188); + _curvea0[482] = _2761; + uint16_t _2762 = (uint16_t)(188); + _curvea0[483] = _2762; + uint16_t _2763 = (uint16_t)(188); + _curvea0[484] = _2763; + uint16_t _2764 = (uint16_t)(188); + _curvea0[485] = _2764; + uint16_t _2765 = (uint16_t)(188); + _curvea0[486] = _2765; + uint16_t _2766 = (uint16_t)(189); + _curvea0[487] = _2766; + uint16_t _2767 = (uint16_t)(189); + _curvea0[488] = _2767; + uint16_t _2768 = (uint16_t)(189); + _curvea0[489] = _2768; + uint16_t _2769 = (uint16_t)(189); + _curvea0[490] = _2769; + uint16_t _2770 = (uint16_t)(189); + _curvea0[491] = _2770; + uint16_t _2771 = (uint16_t)(190); + _curvea0[492] = _2771; + uint16_t _2772 = (uint16_t)(190); + _curvea0[493] = _2772; + uint16_t _2773 = (uint16_t)(190); + _curvea0[494] = _2773; + uint16_t _2774 = (uint16_t)(190); + _curvea0[495] = _2774; + uint16_t _2775 = (uint16_t)(190); + _curvea0[496] = _2775; + uint16_t _2776 = (uint16_t)(190); + _curvea0[497] = _2776; + uint16_t _2777 = (uint16_t)(191); + _curvea0[498] = _2777; + uint16_t _2778 = (uint16_t)(191); + _curvea0[499] = _2778; + uint16_t _2779 = (uint16_t)(191); + _curvea0[500] = _2779; + uint16_t _2780 = (uint16_t)(191); + _curvea0[501] = _2780; + uint16_t _2781 = (uint16_t)(191); + _curvea0[502] = _2781; + uint16_t _2782 = (uint16_t)(192); + _curvea0[503] = _2782; + uint16_t _2783 = (uint16_t)(192); + _curvea0[504] = _2783; + uint16_t _2784 = (uint16_t)(192); + _curvea0[505] = _2784; + uint16_t _2785 = (uint16_t)(192); + _curvea0[506] = _2785; + uint16_t _2786 = (uint16_t)(192); + _curvea0[507] = _2786; + uint16_t _2787 = (uint16_t)(193); + _curvea0[508] = _2787; + uint16_t _2788 = (uint16_t)(193); + _curvea0[509] = _2788; + uint16_t _2789 = (uint16_t)(193); + _curvea0[510] = _2789; + uint16_t _2790 = (uint16_t)(193); + _curvea0[511] = _2790; + uint16_t _2791 = (uint16_t)(193); + _curvea0[512] = _2791; + uint16_t _2792 = (uint16_t)(194); + _curvea0[513] = _2792; + uint16_t _2793 = (uint16_t)(194); + _curvea0[514] = _2793; + uint16_t _2794 = (uint16_t)(194); + _curvea0[515] = _2794; + uint16_t _2795 = (uint16_t)(194); + _curvea0[516] = _2795; + uint16_t _2796 = (uint16_t)(194); + _curvea0[517] = _2796; + uint16_t _2797 = (uint16_t)(195); + _curvea0[518] = _2797; + uint16_t _2798 = (uint16_t)(195); + _curvea0[519] = _2798; + uint16_t _2799 = (uint16_t)(195); + _curvea0[520] = _2799; + uint16_t _2800 = (uint16_t)(195); + _curvea0[521] = _2800; + uint16_t _2801 = (uint16_t)(195); + _curvea0[522] = _2801; + uint16_t _2802 = (uint16_t)(195); + _curvea0[523] = _2802; + uint16_t _2803 = (uint16_t)(196); + _curvea0[524] = _2803; + uint16_t _2804 = (uint16_t)(196); + _curvea0[525] = _2804; + uint16_t _2805 = (uint16_t)(196); + _curvea0[526] = _2805; + uint16_t _2806 = (uint16_t)(196); + _curvea0[527] = _2806; + uint16_t _2807 = (uint16_t)(196); + _curvea0[528] = _2807; + uint16_t _2808 = (uint16_t)(197); + _curvea0[529] = _2808; + uint16_t _2809 = (uint16_t)(197); + _curvea0[530] = _2809; + uint16_t _2810 = (uint16_t)(197); + _curvea0[531] = _2810; + uint16_t _2811 = (uint16_t)(197); + _curvea0[532] = _2811; + uint16_t _2812 = (uint16_t)(197); + _curvea0[533] = _2812; + uint16_t _2813 = (uint16_t)(197); + _curvea0[534] = _2813; + uint16_t _2814 = (uint16_t)(198); + _curvea0[535] = _2814; + uint16_t _2815 = (uint16_t)(198); + _curvea0[536] = _2815; + uint16_t _2816 = (uint16_t)(198); + _curvea0[537] = _2816; + uint16_t _2817 = (uint16_t)(198); + _curvea0[538] = _2817; + uint16_t _2818 = (uint16_t)(198); + _curvea0[539] = _2818; + uint16_t _2819 = (uint16_t)(199); + _curvea0[540] = _2819; + uint16_t _2820 = (uint16_t)(199); + _curvea0[541] = _2820; + uint16_t _2821 = (uint16_t)(199); + _curvea0[542] = _2821; + uint16_t _2822 = (uint16_t)(199); + _curvea0[543] = _2822; + uint16_t _2823 = (uint16_t)(199); + _curvea0[544] = _2823; + uint16_t _2824 = (uint16_t)(199); + _curvea0[545] = _2824; + uint16_t _2825 = (uint16_t)(200); + _curvea0[546] = _2825; + uint16_t _2826 = (uint16_t)(200); + _curvea0[547] = _2826; + uint16_t _2827 = (uint16_t)(200); + _curvea0[548] = _2827; + uint16_t _2828 = (uint16_t)(200); + _curvea0[549] = _2828; + uint16_t _2829 = (uint16_t)(200); + _curvea0[550] = _2829; + uint16_t _2830 = (uint16_t)(200); + _curvea0[551] = _2830; + uint16_t _2831 = (uint16_t)(201); + _curvea0[552] = _2831; + uint16_t _2832 = (uint16_t)(201); + _curvea0[553] = _2832; + uint16_t _2833 = (uint16_t)(201); + _curvea0[554] = _2833; + uint16_t _2834 = (uint16_t)(201); + _curvea0[555] = _2834; + uint16_t _2835 = (uint16_t)(201); + _curvea0[556] = _2835; + uint16_t _2836 = (uint16_t)(202); + _curvea0[557] = _2836; + uint16_t _2837 = (uint16_t)(202); + _curvea0[558] = _2837; + uint16_t _2838 = (uint16_t)(202); + _curvea0[559] = _2838; + uint16_t _2839 = (uint16_t)(202); + _curvea0[560] = _2839; + uint16_t _2840 = (uint16_t)(202); + _curvea0[561] = _2840; + uint16_t _2841 = (uint16_t)(202); + _curvea0[562] = _2841; + uint16_t _2842 = (uint16_t)(203); + _curvea0[563] = _2842; + uint16_t _2843 = (uint16_t)(203); + _curvea0[564] = _2843; + uint16_t _2844 = (uint16_t)(203); + _curvea0[565] = _2844; + uint16_t _2845 = (uint16_t)(203); + _curvea0[566] = _2845; + uint16_t _2846 = (uint16_t)(203); + _curvea0[567] = _2846; + uint16_t _2847 = (uint16_t)(203); + _curvea0[568] = _2847; + uint16_t _2848 = (uint16_t)(204); + _curvea0[569] = _2848; + uint16_t _2849 = (uint16_t)(204); + _curvea0[570] = _2849; + uint16_t _2850 = (uint16_t)(204); + _curvea0[571] = _2850; + uint16_t _2851 = (uint16_t)(204); + _curvea0[572] = _2851; + uint16_t _2852 = (uint16_t)(204); + _curvea0[573] = _2852; + uint16_t _2853 = (uint16_t)(204); + _curvea0[574] = _2853; + uint16_t _2854 = (uint16_t)(205); + _curvea0[575] = _2854; + uint16_t _2855 = (uint16_t)(205); + _curvea0[576] = _2855; + uint16_t _2856 = (uint16_t)(205); + _curvea0[577] = _2856; + uint16_t _2857 = (uint16_t)(205); + _curvea0[578] = _2857; + uint16_t _2858 = (uint16_t)(205); + _curvea0[579] = _2858; + uint16_t _2859 = (uint16_t)(205); + _curvea0[580] = _2859; + uint16_t _2860 = (uint16_t)(206); + _curvea0[581] = _2860; + uint16_t _2861 = (uint16_t)(206); + _curvea0[582] = _2861; + uint16_t _2862 = (uint16_t)(206); + _curvea0[583] = _2862; + uint16_t _2863 = (uint16_t)(206); + _curvea0[584] = _2863; + uint16_t _2864 = (uint16_t)(206); + _curvea0[585] = _2864; + uint16_t _2865 = (uint16_t)(206); + _curvea0[586] = _2865; + uint16_t _2866 = (uint16_t)(207); + _curvea0[587] = _2866; + uint16_t _2867 = (uint16_t)(207); + _curvea0[588] = _2867; + uint16_t _2868 = (uint16_t)(207); + _curvea0[589] = _2868; + uint16_t _2869 = (uint16_t)(207); + _curvea0[590] = _2869; + uint16_t _2870 = (uint16_t)(207); + _curvea0[591] = _2870; + uint16_t _2871 = (uint16_t)(207); + _curvea0[592] = _2871; + uint16_t _2872 = (uint16_t)(208); + _curvea0[593] = _2872; + uint16_t _2873 = (uint16_t)(208); + _curvea0[594] = _2873; + uint16_t _2874 = (uint16_t)(208); + _curvea0[595] = _2874; + uint16_t _2875 = (uint16_t)(208); + _curvea0[596] = _2875; + uint16_t _2876 = (uint16_t)(208); + _curvea0[597] = _2876; + uint16_t _2877 = (uint16_t)(208); + _curvea0[598] = _2877; + uint16_t _2878 = (uint16_t)(209); + _curvea0[599] = _2878; + uint16_t _2879 = (uint16_t)(209); + _curvea0[600] = _2879; + uint16_t _2880 = (uint16_t)(209); + _curvea0[601] = _2880; + uint16_t _2881 = (uint16_t)(209); + _curvea0[602] = _2881; + uint16_t _2882 = (uint16_t)(209); + _curvea0[603] = _2882; + uint16_t _2883 = (uint16_t)(209); + _curvea0[604] = _2883; + uint16_t _2884 = (uint16_t)(209); + _curvea0[605] = _2884; + uint16_t _2885 = (uint16_t)(210); + _curvea0[606] = _2885; + uint16_t _2886 = (uint16_t)(210); + _curvea0[607] = _2886; + uint16_t _2887 = (uint16_t)(210); + _curvea0[608] = _2887; + uint16_t _2888 = (uint16_t)(210); + _curvea0[609] = _2888; + uint16_t _2889 = (uint16_t)(210); + _curvea0[610] = _2889; + uint16_t _2890 = (uint16_t)(210); + _curvea0[611] = _2890; + uint16_t _2891 = (uint16_t)(211); + _curvea0[612] = _2891; + uint16_t _2892 = (uint16_t)(211); + _curvea0[613] = _2892; + uint16_t _2893 = (uint16_t)(211); + _curvea0[614] = _2893; + uint16_t _2894 = (uint16_t)(211); + _curvea0[615] = _2894; + uint16_t _2895 = (uint16_t)(211); + _curvea0[616] = _2895; + uint16_t _2896 = (uint16_t)(211); + _curvea0[617] = _2896; + uint16_t _2897 = (uint16_t)(211); + _curvea0[618] = _2897; + uint16_t _2898 = (uint16_t)(212); + _curvea0[619] = _2898; + uint16_t _2899 = (uint16_t)(212); + _curvea0[620] = _2899; + uint16_t _2900 = (uint16_t)(212); + _curvea0[621] = _2900; + uint16_t _2901 = (uint16_t)(212); + _curvea0[622] = _2901; + uint16_t _2902 = (uint16_t)(212); + _curvea0[623] = _2902; + uint16_t _2903 = (uint16_t)(212); + _curvea0[624] = _2903; + uint16_t _2904 = (uint16_t)(213); + _curvea0[625] = _2904; + uint16_t _2905 = (uint16_t)(213); + _curvea0[626] = _2905; + uint16_t _2906 = (uint16_t)(213); + _curvea0[627] = _2906; + uint16_t _2907 = (uint16_t)(213); + _curvea0[628] = _2907; + uint16_t _2908 = (uint16_t)(213); + _curvea0[629] = _2908; + uint16_t _2909 = (uint16_t)(213); + _curvea0[630] = _2909; + uint16_t _2910 = (uint16_t)(213); + _curvea0[631] = _2910; + uint16_t _2911 = (uint16_t)(214); + _curvea0[632] = _2911; + uint16_t _2912 = (uint16_t)(214); + _curvea0[633] = _2912; + uint16_t _2913 = (uint16_t)(214); + _curvea0[634] = _2913; + uint16_t _2914 = (uint16_t)(214); + _curvea0[635] = _2914; + uint16_t _2915 = (uint16_t)(214); + _curvea0[636] = _2915; + uint16_t _2916 = (uint16_t)(214); + _curvea0[637] = _2916; + uint16_t _2917 = (uint16_t)(214); + _curvea0[638] = _2917; + uint16_t _2918 = (uint16_t)(215); + _curvea0[639] = _2918; + uint16_t _2919 = (uint16_t)(215); + _curvea0[640] = _2919; + uint16_t _2920 = (uint16_t)(215); + _curvea0[641] = _2920; + uint16_t _2921 = (uint16_t)(215); + _curvea0[642] = _2921; + uint16_t _2922 = (uint16_t)(215); + _curvea0[643] = _2922; + uint16_t _2923 = (uint16_t)(215); + _curvea0[644] = _2923; + uint16_t _2924 = (uint16_t)(216); + _curvea0[645] = _2924; + uint16_t _2925 = (uint16_t)(216); + _curvea0[646] = _2925; + uint16_t _2926 = (uint16_t)(216); + _curvea0[647] = _2926; + uint16_t _2927 = (uint16_t)(216); + _curvea0[648] = _2927; + uint16_t _2928 = (uint16_t)(216); + _curvea0[649] = _2928; + uint16_t _2929 = (uint16_t)(216); + _curvea0[650] = _2929; + uint16_t _2930 = (uint16_t)(216); + _curvea0[651] = _2930; + uint16_t _2931 = (uint16_t)(217); + _curvea0[652] = _2931; + uint16_t _2932 = (uint16_t)(217); + _curvea0[653] = _2932; + uint16_t _2933 = (uint16_t)(217); + _curvea0[654] = _2933; + uint16_t _2934 = (uint16_t)(217); + _curvea0[655] = _2934; + uint16_t _2935 = (uint16_t)(217); + _curvea0[656] = _2935; + uint16_t _2936 = (uint16_t)(217); + _curvea0[657] = _2936; + uint16_t _2937 = (uint16_t)(217); + _curvea0[658] = _2937; + uint16_t _2938 = (uint16_t)(218); + _curvea0[659] = _2938; + uint16_t _2939 = (uint16_t)(218); + _curvea0[660] = _2939; + uint16_t _2940 = (uint16_t)(218); + _curvea0[661] = _2940; + uint16_t _2941 = (uint16_t)(218); + _curvea0[662] = _2941; + uint16_t _2942 = (uint16_t)(218); + _curvea0[663] = _2942; + uint16_t _2943 = (uint16_t)(218); + _curvea0[664] = _2943; + uint16_t _2944 = (uint16_t)(218); + _curvea0[665] = _2944; + uint16_t _2945 = (uint16_t)(219); + _curvea0[666] = _2945; + uint16_t _2946 = (uint16_t)(219); + _curvea0[667] = _2946; + uint16_t _2947 = (uint16_t)(219); + _curvea0[668] = _2947; + uint16_t _2948 = (uint16_t)(219); + _curvea0[669] = _2948; + uint16_t _2949 = (uint16_t)(219); + _curvea0[670] = _2949; + uint16_t _2950 = (uint16_t)(219); + _curvea0[671] = _2950; + uint16_t _2951 = (uint16_t)(219); + _curvea0[672] = _2951; + uint16_t _2952 = (uint16_t)(220); + _curvea0[673] = _2952; + uint16_t _2953 = (uint16_t)(220); + _curvea0[674] = _2953; + uint16_t _2954 = (uint16_t)(220); + _curvea0[675] = _2954; + uint16_t _2955 = (uint16_t)(220); + _curvea0[676] = _2955; + uint16_t _2956 = (uint16_t)(220); + _curvea0[677] = _2956; + uint16_t _2957 = (uint16_t)(220); + _curvea0[678] = _2957; + uint16_t _2958 = (uint16_t)(220); + _curvea0[679] = _2958; + uint16_t _2959 = (uint16_t)(220); + _curvea0[680] = _2959; + uint16_t _2960 = (uint16_t)(221); + _curvea0[681] = _2960; + uint16_t _2961 = (uint16_t)(221); + _curvea0[682] = _2961; + uint16_t _2962 = (uint16_t)(221); + _curvea0[683] = _2962; + uint16_t _2963 = (uint16_t)(221); + _curvea0[684] = _2963; + uint16_t _2964 = (uint16_t)(221); + _curvea0[685] = _2964; + uint16_t _2965 = (uint16_t)(221); + _curvea0[686] = _2965; + uint16_t _2966 = (uint16_t)(221); + _curvea0[687] = _2966; + uint16_t _2967 = (uint16_t)(222); + _curvea0[688] = _2967; + uint16_t _2968 = (uint16_t)(222); + _curvea0[689] = _2968; + uint16_t _2969 = (uint16_t)(222); + _curvea0[690] = _2969; + uint16_t _2970 = (uint16_t)(222); + _curvea0[691] = _2970; + uint16_t _2971 = (uint16_t)(222); + _curvea0[692] = _2971; + uint16_t _2972 = (uint16_t)(222); + _curvea0[693] = _2972; + uint16_t _2973 = (uint16_t)(222); + _curvea0[694] = _2973; + uint16_t _2974 = (uint16_t)(223); + _curvea0[695] = _2974; + uint16_t _2975 = (uint16_t)(223); + _curvea0[696] = _2975; + uint16_t _2976 = (uint16_t)(223); + _curvea0[697] = _2976; + uint16_t _2977 = (uint16_t)(223); + _curvea0[698] = _2977; + uint16_t _2978 = (uint16_t)(223); + _curvea0[699] = _2978; + uint16_t _2979 = (uint16_t)(223); + _curvea0[700] = _2979; + uint16_t _2980 = (uint16_t)(223); + _curvea0[701] = _2980; + uint16_t _2981 = (uint16_t)(223); + _curvea0[702] = _2981; + uint16_t _2982 = (uint16_t)(224); + _curvea0[703] = _2982; + uint16_t _2983 = (uint16_t)(224); + _curvea0[704] = _2983; + uint16_t _2984 = (uint16_t)(224); + _curvea0[705] = _2984; + uint16_t _2985 = (uint16_t)(224); + _curvea0[706] = _2985; + uint16_t _2986 = (uint16_t)(224); + _curvea0[707] = _2986; + uint16_t _2987 = (uint16_t)(224); + _curvea0[708] = _2987; + uint16_t _2988 = (uint16_t)(224); + _curvea0[709] = _2988; + uint16_t _2989 = (uint16_t)(224); + _curvea0[710] = _2989; + uint16_t _2990 = (uint16_t)(225); + _curvea0[711] = _2990; + uint16_t _2991 = (uint16_t)(225); + _curvea0[712] = _2991; + uint16_t _2992 = (uint16_t)(225); + _curvea0[713] = _2992; + uint16_t _2993 = (uint16_t)(225); + _curvea0[714] = _2993; + uint16_t _2994 = (uint16_t)(225); + _curvea0[715] = _2994; + uint16_t _2995 = (uint16_t)(225); + _curvea0[716] = _2995; + uint16_t _2996 = (uint16_t)(225); + _curvea0[717] = _2996; + uint16_t _2997 = (uint16_t)(226); + _curvea0[718] = _2997; + uint16_t _2998 = (uint16_t)(226); + _curvea0[719] = _2998; + uint16_t _2999 = (uint16_t)(226); + _curvea0[720] = _2999; + uint16_t _3000 = (uint16_t)(226); + _curvea0[721] = _3000; + uint16_t _3001 = (uint16_t)(226); + _curvea0[722] = _3001; + uint16_t _3002 = (uint16_t)(226); + _curvea0[723] = _3002; + uint16_t _3003 = (uint16_t)(226); + _curvea0[724] = _3003; + uint16_t _3004 = (uint16_t)(226); + _curvea0[725] = _3004; + uint16_t _3005 = (uint16_t)(227); + _curvea0[726] = _3005; + uint16_t _3006 = (uint16_t)(227); + _curvea0[727] = _3006; + uint16_t _3007 = (uint16_t)(227); + _curvea0[728] = _3007; + uint16_t _3008 = (uint16_t)(227); + _curvea0[729] = _3008; + uint16_t _3009 = (uint16_t)(227); + _curvea0[730] = _3009; + uint16_t _3010 = (uint16_t)(227); + _curvea0[731] = _3010; + uint16_t _3011 = (uint16_t)(227); + _curvea0[732] = _3011; + uint16_t _3012 = (uint16_t)(227); + _curvea0[733] = _3012; + uint16_t _3013 = (uint16_t)(228); + _curvea0[734] = _3013; + uint16_t _3014 = (uint16_t)(228); + _curvea0[735] = _3014; + uint16_t _3015 = (uint16_t)(228); + _curvea0[736] = _3015; + uint16_t _3016 = (uint16_t)(228); + _curvea0[737] = _3016; + uint16_t _3017 = (uint16_t)(228); + _curvea0[738] = _3017; + uint16_t _3018 = (uint16_t)(228); + _curvea0[739] = _3018; + uint16_t _3019 = (uint16_t)(228); + _curvea0[740] = _3019; + uint16_t _3020 = (uint16_t)(228); + _curvea0[741] = _3020; + uint16_t _3021 = (uint16_t)(228); + _curvea0[742] = _3021; + uint16_t _3022 = (uint16_t)(229); + _curvea0[743] = _3022; + uint16_t _3023 = (uint16_t)(229); + _curvea0[744] = _3023; + uint16_t _3024 = (uint16_t)(229); + _curvea0[745] = _3024; + uint16_t _3025 = (uint16_t)(229); + _curvea0[746] = _3025; + uint16_t _3026 = (uint16_t)(229); + _curvea0[747] = _3026; + uint16_t _3027 = (uint16_t)(229); + _curvea0[748] = _3027; + uint16_t _3028 = (uint16_t)(229); + _curvea0[749] = _3028; + uint16_t _3029 = (uint16_t)(229); + _curvea0[750] = _3029; + uint16_t _3030 = (uint16_t)(230); + _curvea0[751] = _3030; + uint16_t _3031 = (uint16_t)(230); + _curvea0[752] = _3031; + uint16_t _3032 = (uint16_t)(230); + _curvea0[753] = _3032; + uint16_t _3033 = (uint16_t)(230); + _curvea0[754] = _3033; + uint16_t _3034 = (uint16_t)(230); + _curvea0[755] = _3034; + uint16_t _3035 = (uint16_t)(230); + _curvea0[756] = _3035; + uint16_t _3036 = (uint16_t)(230); + _curvea0[757] = _3036; + uint16_t _3037 = (uint16_t)(230); + _curvea0[758] = _3037; + uint16_t _3038 = (uint16_t)(231); + _curvea0[759] = _3038; + uint16_t _3039 = (uint16_t)(231); + _curvea0[760] = _3039; + uint16_t _3040 = (uint16_t)(231); + _curvea0[761] = _3040; + uint16_t _3041 = (uint16_t)(231); + _curvea0[762] = _3041; + uint16_t _3042 = (uint16_t)(231); + _curvea0[763] = _3042; + uint16_t _3043 = (uint16_t)(231); + _curvea0[764] = _3043; + uint16_t _3044 = (uint16_t)(231); + _curvea0[765] = _3044; + uint16_t _3045 = (uint16_t)(231); + _curvea0[766] = _3045; + uint16_t _3046 = (uint16_t)(231); + _curvea0[767] = _3046; + uint16_t _3047 = (uint16_t)(232); + _curvea0[768] = _3047; + uint16_t _3048 = (uint16_t)(232); + _curvea0[769] = _3048; + uint16_t _3049 = (uint16_t)(232); + _curvea0[770] = _3049; + uint16_t _3050 = (uint16_t)(232); + _curvea0[771] = _3050; + uint16_t _3051 = (uint16_t)(232); + _curvea0[772] = _3051; + uint16_t _3052 = (uint16_t)(232); + _curvea0[773] = _3052; + uint16_t _3053 = (uint16_t)(232); + _curvea0[774] = _3053; + uint16_t _3054 = (uint16_t)(232); + _curvea0[775] = _3054; + uint16_t _3055 = (uint16_t)(233); + _curvea0[776] = _3055; + uint16_t _3056 = (uint16_t)(233); + _curvea0[777] = _3056; + uint16_t _3057 = (uint16_t)(233); + _curvea0[778] = _3057; + uint16_t _3058 = (uint16_t)(233); + _curvea0[779] = _3058; + uint16_t _3059 = (uint16_t)(233); + _curvea0[780] = _3059; + uint16_t _3060 = (uint16_t)(233); + _curvea0[781] = _3060; + uint16_t _3061 = (uint16_t)(233); + _curvea0[782] = _3061; + uint16_t _3062 = (uint16_t)(233); + _curvea0[783] = _3062; + uint16_t _3063 = (uint16_t)(233); + _curvea0[784] = _3063; + uint16_t _3064 = (uint16_t)(234); + _curvea0[785] = _3064; + uint16_t _3065 = (uint16_t)(234); + _curvea0[786] = _3065; + uint16_t _3066 = (uint16_t)(234); + _curvea0[787] = _3066; + uint16_t _3067 = (uint16_t)(234); + _curvea0[788] = _3067; + uint16_t _3068 = (uint16_t)(234); + _curvea0[789] = _3068; + uint16_t _3069 = (uint16_t)(234); + _curvea0[790] = _3069; + uint16_t _3070 = (uint16_t)(234); + _curvea0[791] = _3070; + uint16_t _3071 = (uint16_t)(234); + _curvea0[792] = _3071; + uint16_t _3072 = (uint16_t)(234); + _curvea0[793] = _3072; + uint16_t _3073 = (uint16_t)(235); + _curvea0[794] = _3073; + uint16_t _3074 = (uint16_t)(235); + _curvea0[795] = _3074; + uint16_t _3075 = (uint16_t)(235); + _curvea0[796] = _3075; + uint16_t _3076 = (uint16_t)(235); + _curvea0[797] = _3076; + uint16_t _3077 = (uint16_t)(235); + _curvea0[798] = _3077; + uint16_t _3078 = (uint16_t)(235); + _curvea0[799] = _3078; + uint16_t _3079 = (uint16_t)(235); + _curvea0[800] = _3079; + uint16_t _3080 = (uint16_t)(235); + _curvea0[801] = _3080; + uint16_t _3081 = (uint16_t)(235); + _curvea0[802] = _3081; + uint16_t _3082 = (uint16_t)(236); + _curvea0[803] = _3082; + uint16_t _3083 = (uint16_t)(236); + _curvea0[804] = _3083; + uint16_t _3084 = (uint16_t)(236); + _curvea0[805] = _3084; + uint16_t _3085 = (uint16_t)(236); + _curvea0[806] = _3085; + uint16_t _3086 = (uint16_t)(236); + _curvea0[807] = _3086; + uint16_t _3087 = (uint16_t)(236); + _curvea0[808] = _3087; + uint16_t _3088 = (uint16_t)(236); + _curvea0[809] = _3088; + uint16_t _3089 = (uint16_t)(236); + _curvea0[810] = _3089; + uint16_t _3090 = (uint16_t)(236); + _curvea0[811] = _3090; + uint16_t _3091 = (uint16_t)(237); + _curvea0[812] = _3091; + uint16_t _3092 = (uint16_t)(237); + _curvea0[813] = _3092; + uint16_t _3093 = (uint16_t)(237); + _curvea0[814] = _3093; + uint16_t _3094 = (uint16_t)(237); + _curvea0[815] = _3094; + uint16_t _3095 = (uint16_t)(237); + _curvea0[816] = _3095; + uint16_t _3096 = (uint16_t)(237); + _curvea0[817] = _3096; + uint16_t _3097 = (uint16_t)(237); + _curvea0[818] = _3097; + uint16_t _3098 = (uint16_t)(237); + _curvea0[819] = _3098; + uint16_t _3099 = (uint16_t)(237); + _curvea0[820] = _3099; + uint16_t _3100 = (uint16_t)(237); + _curvea0[821] = _3100; + uint16_t _3101 = (uint16_t)(238); + _curvea0[822] = _3101; + uint16_t _3102 = (uint16_t)(238); + _curvea0[823] = _3102; + uint16_t _3103 = (uint16_t)(238); + _curvea0[824] = _3103; + uint16_t _3104 = (uint16_t)(238); + _curvea0[825] = _3104; + uint16_t _3105 = (uint16_t)(238); + _curvea0[826] = _3105; + uint16_t _3106 = (uint16_t)(238); + _curvea0[827] = _3106; + uint16_t _3107 = (uint16_t)(238); + _curvea0[828] = _3107; + uint16_t _3108 = (uint16_t)(238); + _curvea0[829] = _3108; + uint16_t _3109 = (uint16_t)(238); + _curvea0[830] = _3109; + uint16_t _3110 = (uint16_t)(239); + _curvea0[831] = _3110; + uint16_t _3111 = (uint16_t)(239); + _curvea0[832] = _3111; + uint16_t _3112 = (uint16_t)(239); + _curvea0[833] = _3112; + uint16_t _3113 = (uint16_t)(239); + _curvea0[834] = _3113; + uint16_t _3114 = (uint16_t)(239); + _curvea0[835] = _3114; + uint16_t _3115 = (uint16_t)(239); + _curvea0[836] = _3115; + uint16_t _3116 = (uint16_t)(239); + _curvea0[837] = _3116; + uint16_t _3117 = (uint16_t)(239); + _curvea0[838] = _3117; + uint16_t _3118 = (uint16_t)(239); + _curvea0[839] = _3118; + uint16_t _3119 = (uint16_t)(239); + _curvea0[840] = _3119; + uint16_t _3120 = (uint16_t)(240); + _curvea0[841] = _3120; + uint16_t _3121 = (uint16_t)(240); + _curvea0[842] = _3121; + uint16_t _3122 = (uint16_t)(240); + _curvea0[843] = _3122; + uint16_t _3123 = (uint16_t)(240); + _curvea0[844] = _3123; + uint16_t _3124 = (uint16_t)(240); + _curvea0[845] = _3124; + uint16_t _3125 = (uint16_t)(240); + _curvea0[846] = _3125; + uint16_t _3126 = (uint16_t)(240); + _curvea0[847] = _3126; + uint16_t _3127 = (uint16_t)(240); + _curvea0[848] = _3127; + uint16_t _3128 = (uint16_t)(240); + _curvea0[849] = _3128; + uint16_t _3129 = (uint16_t)(240); + _curvea0[850] = _3129; + uint16_t _3130 = (uint16_t)(241); + _curvea0[851] = _3130; + uint16_t _3131 = (uint16_t)(241); + _curvea0[852] = _3131; + uint16_t _3132 = (uint16_t)(241); + _curvea0[853] = _3132; + uint16_t _3133 = (uint16_t)(241); + _curvea0[854] = _3133; + uint16_t _3134 = (uint16_t)(241); + _curvea0[855] = _3134; + uint16_t _3135 = (uint16_t)(241); + _curvea0[856] = _3135; + uint16_t _3136 = (uint16_t)(241); + _curvea0[857] = _3136; + uint16_t _3137 = (uint16_t)(241); + _curvea0[858] = _3137; + uint16_t _3138 = (uint16_t)(241); + _curvea0[859] = _3138; + uint16_t _3139 = (uint16_t)(241); + _curvea0[860] = _3139; + uint16_t _3140 = (uint16_t)(242); + _curvea0[861] = _3140; + uint16_t _3141 = (uint16_t)(242); + _curvea0[862] = _3141; + uint16_t _3142 = (uint16_t)(242); + _curvea0[863] = _3142; + uint16_t _3143 = (uint16_t)(242); + _curvea0[864] = _3143; + uint16_t _3144 = (uint16_t)(242); + _curvea0[865] = _3144; + uint16_t _3145 = (uint16_t)(242); + _curvea0[866] = _3145; + uint16_t _3146 = (uint16_t)(242); + _curvea0[867] = _3146; + uint16_t _3147 = (uint16_t)(242); + _curvea0[868] = _3147; + uint16_t _3148 = (uint16_t)(242); + _curvea0[869] = _3148; + uint16_t _3149 = (uint16_t)(242); + _curvea0[870] = _3149; + uint16_t _3150 = (uint16_t)(243); + _curvea0[871] = _3150; + uint16_t _3151 = (uint16_t)(243); + _curvea0[872] = _3151; + uint16_t _3152 = (uint16_t)(243); + _curvea0[873] = _3152; + uint16_t _3153 = (uint16_t)(243); + _curvea0[874] = _3153; + uint16_t _3154 = (uint16_t)(243); + _curvea0[875] = _3154; + uint16_t _3155 = (uint16_t)(243); + _curvea0[876] = _3155; + uint16_t _3156 = (uint16_t)(243); + _curvea0[877] = _3156; + uint16_t _3157 = (uint16_t)(243); + _curvea0[878] = _3157; + uint16_t _3158 = (uint16_t)(243); + _curvea0[879] = _3158; + uint16_t _3159 = (uint16_t)(243); + _curvea0[880] = _3159; + uint16_t _3160 = (uint16_t)(244); + _curvea0[881] = _3160; + uint16_t _3161 = (uint16_t)(244); + _curvea0[882] = _3161; + uint16_t _3162 = (uint16_t)(244); + _curvea0[883] = _3162; + uint16_t _3163 = (uint16_t)(244); + _curvea0[884] = _3163; + uint16_t _3164 = (uint16_t)(244); + _curvea0[885] = _3164; + uint16_t _3165 = (uint16_t)(244); + _curvea0[886] = _3165; + uint16_t _3166 = (uint16_t)(244); + _curvea0[887] = _3166; + uint16_t _3167 = (uint16_t)(244); + _curvea0[888] = _3167; + uint16_t _3168 = (uint16_t)(244); + _curvea0[889] = _3168; + uint16_t _3169 = (uint16_t)(244); + _curvea0[890] = _3169; + uint16_t _3170 = (uint16_t)(244); + _curvea0[891] = _3170; + uint16_t _3171 = (uint16_t)(245); + _curvea0[892] = _3171; + uint16_t _3172 = (uint16_t)(245); + _curvea0[893] = _3172; + uint16_t _3173 = (uint16_t)(245); + _curvea0[894] = _3173; + uint16_t _3174 = (uint16_t)(245); + _curvea0[895] = _3174; + uint16_t _3175 = (uint16_t)(245); + _curvea0[896] = _3175; + uint16_t _3176 = (uint16_t)(245); + _curvea0[897] = _3176; + uint16_t _3177 = (uint16_t)(245); + _curvea0[898] = _3177; + uint16_t _3178 = (uint16_t)(245); + _curvea0[899] = _3178; + uint16_t _3179 = (uint16_t)(245); + _curvea0[900] = _3179; + uint16_t _3180 = (uint16_t)(245); + _curvea0[901] = _3180; + uint16_t _3181 = (uint16_t)(245); + _curvea0[902] = _3181; + uint16_t _3182 = (uint16_t)(246); + _curvea0[903] = _3182; + uint16_t _3183 = (uint16_t)(246); + _curvea0[904] = _3183; + uint16_t _3184 = (uint16_t)(246); + _curvea0[905] = _3184; + uint16_t _3185 = (uint16_t)(246); + _curvea0[906] = _3185; + uint16_t _3186 = (uint16_t)(246); + _curvea0[907] = _3186; + uint16_t _3187 = (uint16_t)(246); + _curvea0[908] = _3187; + uint16_t _3188 = (uint16_t)(246); + _curvea0[909] = _3188; + uint16_t _3189 = (uint16_t)(246); + _curvea0[910] = _3189; + uint16_t _3190 = (uint16_t)(246); + _curvea0[911] = _3190; + uint16_t _3191 = (uint16_t)(246); + _curvea0[912] = _3191; + uint16_t _3192 = (uint16_t)(246); + _curvea0[913] = _3192; + uint16_t _3193 = (uint16_t)(247); + _curvea0[914] = _3193; + uint16_t _3194 = (uint16_t)(247); + _curvea0[915] = _3194; + uint16_t _3195 = (uint16_t)(247); + _curvea0[916] = _3195; + uint16_t _3196 = (uint16_t)(247); + _curvea0[917] = _3196; + uint16_t _3197 = (uint16_t)(247); + _curvea0[918] = _3197; + uint16_t _3198 = (uint16_t)(247); + _curvea0[919] = _3198; + uint16_t _3199 = (uint16_t)(247); + _curvea0[920] = _3199; + uint16_t _3200 = (uint16_t)(247); + _curvea0[921] = _3200; + uint16_t _3201 = (uint16_t)(247); + _curvea0[922] = _3201; + uint16_t _3202 = (uint16_t)(247); + _curvea0[923] = _3202; + uint16_t _3203 = (uint16_t)(247); + _curvea0[924] = _3203; + uint16_t _3204 = (uint16_t)(248); + _curvea0[925] = _3204; + uint16_t _3205 = (uint16_t)(248); + _curvea0[926] = _3205; + uint16_t _3206 = (uint16_t)(248); + _curvea0[927] = _3206; + uint16_t _3207 = (uint16_t)(248); + _curvea0[928] = _3207; + uint16_t _3208 = (uint16_t)(248); + _curvea0[929] = _3208; + uint16_t _3209 = (uint16_t)(248); + _curvea0[930] = _3209; + uint16_t _3210 = (uint16_t)(248); + _curvea0[931] = _3210; + uint16_t _3211 = (uint16_t)(248); + _curvea0[932] = _3211; + uint16_t _3212 = (uint16_t)(248); + _curvea0[933] = _3212; + uint16_t _3213 = (uint16_t)(248); + _curvea0[934] = _3213; + uint16_t _3214 = (uint16_t)(248); + _curvea0[935] = _3214; + uint16_t _3215 = (uint16_t)(249); + _curvea0[936] = _3215; + uint16_t _3216 = (uint16_t)(249); + _curvea0[937] = _3216; + uint16_t _3217 = (uint16_t)(249); + _curvea0[938] = _3217; + uint16_t _3218 = (uint16_t)(249); + _curvea0[939] = _3218; + uint16_t _3219 = (uint16_t)(249); + _curvea0[940] = _3219; + uint16_t _3220 = (uint16_t)(249); + _curvea0[941] = _3220; + uint16_t _3221 = (uint16_t)(249); + _curvea0[942] = _3221; + uint16_t _3222 = (uint16_t)(249); + _curvea0[943] = _3222; + uint16_t _3223 = (uint16_t)(249); + _curvea0[944] = _3223; + uint16_t _3224 = (uint16_t)(249); + _curvea0[945] = _3224; + uint16_t _3225 = (uint16_t)(249); + _curvea0[946] = _3225; + uint16_t _3226 = (uint16_t)(249); + _curvea0[947] = _3226; + uint16_t _3227 = (uint16_t)(250); + _curvea0[948] = _3227; + uint16_t _3228 = (uint16_t)(250); + _curvea0[949] = _3228; + uint16_t _3229 = (uint16_t)(250); + _curvea0[950] = _3229; + uint16_t _3230 = (uint16_t)(250); + _curvea0[951] = _3230; + uint16_t _3231 = (uint16_t)(250); + _curvea0[952] = _3231; + uint16_t _3232 = (uint16_t)(250); + _curvea0[953] = _3232; + uint16_t _3233 = (uint16_t)(250); + _curvea0[954] = _3233; + uint16_t _3234 = (uint16_t)(250); + _curvea0[955] = _3234; + uint16_t _3235 = (uint16_t)(250); + _curvea0[956] = _3235; + uint16_t _3236 = (uint16_t)(250); + _curvea0[957] = _3236; + uint16_t _3237 = (uint16_t)(250); + _curvea0[958] = _3237; + uint16_t _3238 = (uint16_t)(250); + _curvea0[959] = _3238; + uint16_t _3239 = (uint16_t)(251); + _curvea0[960] = _3239; + uint16_t _3240 = (uint16_t)(251); + _curvea0[961] = _3240; + uint16_t _3241 = (uint16_t)(251); + _curvea0[962] = _3241; + uint16_t _3242 = (uint16_t)(251); + _curvea0[963] = _3242; + uint16_t _3243 = (uint16_t)(251); + _curvea0[964] = _3243; + uint16_t _3244 = (uint16_t)(251); + _curvea0[965] = _3244; + uint16_t _3245 = (uint16_t)(251); + _curvea0[966] = _3245; + uint16_t _3246 = (uint16_t)(251); + _curvea0[967] = _3246; + uint16_t _3247 = (uint16_t)(251); + _curvea0[968] = _3247; + uint16_t _3248 = (uint16_t)(251); + _curvea0[969] = _3248; + uint16_t _3249 = (uint16_t)(251); + _curvea0[970] = _3249; + uint16_t _3250 = (uint16_t)(251); + _curvea0[971] = _3250; + uint16_t _3251 = (uint16_t)(252); + _curvea0[972] = _3251; + uint16_t _3252 = (uint16_t)(252); + _curvea0[973] = _3252; + uint16_t _3253 = (uint16_t)(252); + _curvea0[974] = _3253; + uint16_t _3254 = (uint16_t)(252); + _curvea0[975] = _3254; + uint16_t _3255 = (uint16_t)(252); + _curvea0[976] = _3255; + uint16_t _3256 = (uint16_t)(252); + _curvea0[977] = _3256; + uint16_t _3257 = (uint16_t)(252); + _curvea0[978] = _3257; + uint16_t _3258 = (uint16_t)(252); + _curvea0[979] = _3258; + uint16_t _3259 = (uint16_t)(252); + _curvea0[980] = _3259; + uint16_t _3260 = (uint16_t)(252); + _curvea0[981] = _3260; + uint16_t _3261 = (uint16_t)(252); + _curvea0[982] = _3261; + uint16_t _3262 = (uint16_t)(252); + _curvea0[983] = _3262; + uint16_t _3263 = (uint16_t)(252); + _curvea0[984] = _3263; + uint16_t _3264 = (uint16_t)(253); + _curvea0[985] = _3264; + uint16_t _3265 = (uint16_t)(253); + _curvea0[986] = _3265; + uint16_t _3266 = (uint16_t)(253); + _curvea0[987] = _3266; + uint16_t _3267 = (uint16_t)(253); + _curvea0[988] = _3267; + uint16_t _3268 = (uint16_t)(253); + _curvea0[989] = _3268; + uint16_t _3269 = (uint16_t)(253); + _curvea0[990] = _3269; + uint16_t _3270 = (uint16_t)(253); + _curvea0[991] = _3270; + uint16_t _3271 = (uint16_t)(253); + _curvea0[992] = _3271; + uint16_t _3272 = (uint16_t)(253); + _curvea0[993] = _3272; + uint16_t _3273 = (uint16_t)(253); + _curvea0[994] = _3273; + uint16_t _3274 = (uint16_t)(253); + _curvea0[995] = _3274; + uint16_t _3275 = (uint16_t)(253); + _curvea0[996] = _3275; + uint16_t _3276 = (uint16_t)(253); + _curvea0[997] = _3276; + uint16_t _3277 = (uint16_t)(254); + _curvea0[998] = _3277; + uint16_t _3278 = (uint16_t)(254); + _curvea0[999] = _3278; + uint16_t _3279 = (uint16_t)(254); + _curvea0[1000] = _3279; + uint16_t _3280 = (uint16_t)(254); + _curvea0[1001] = _3280; + uint16_t _3281 = (uint16_t)(254); + _curvea0[1002] = _3281; + uint16_t _3282 = (uint16_t)(254); + _curvea0[1003] = _3282; + uint16_t _3283 = (uint16_t)(254); + _curvea0[1004] = _3283; + uint16_t _3284 = (uint16_t)(254); + _curvea0[1005] = _3284; + uint16_t _3285 = (uint16_t)(254); + _curvea0[1006] = _3285; + uint16_t _3286 = (uint16_t)(254); + _curvea0[1007] = _3286; + uint16_t _3287 = (uint16_t)(254); + _curvea0[1008] = _3287; + uint16_t _3288 = (uint16_t)(254); + _curvea0[1009] = _3288; + uint16_t _3289 = (uint16_t)(254); + _curvea0[1010] = _3289; + uint16_t _3290 = (uint16_t)(255); + _curvea0[1011] = _3290; + uint16_t _3291 = (uint16_t)(255); + _curvea0[1012] = _3291; + uint16_t _3292 = (uint16_t)(255); + _curvea0[1013] = _3292; + uint16_t _3293 = (uint16_t)(255); + _curvea0[1014] = _3293; + uint16_t _3294 = (uint16_t)(255); + _curvea0[1015] = _3294; + uint16_t _3295 = (uint16_t)(255); + _curvea0[1016] = _3295; + uint16_t _3296 = (uint16_t)(255); + _curvea0[1017] = _3296; + uint16_t _3297 = (uint16_t)(255); + _curvea0[1018] = _3297; + uint16_t _3298 = (uint16_t)(255); + _curvea0[1019] = _3298; + uint16_t _3299 = (uint16_t)(255); + _curvea0[1020] = _3299; + uint16_t _3300 = (uint16_t)(255); + _curvea0[1021] = _3300; + uint16_t _3301 = (uint16_t)(255); + _curvea0[1022] = _3301; + uint16_t _3302 = (uint16_t)(255); + _curvea0[1023] = _3302; + + int16_t _3303 = (int16_t)(1023); + int16_t _3304 = min(_corrected_stencil_1, _3303); + int16_t _3305 = (int16_t)(0); + int16_t _3306 = max(_3304, _3305); + uint16_t _3307 = (uint16_t)(_3306); + int32_t _3308 = (int32_t)(_3307); + uint16_t _3309 = ((const uint16_t *)_curvea0)[_3308]; + return _3309; +} + +//store is: curved.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_1(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_2 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _3325 = (uint16_t)(0); + _curvea0[0] = _3325; + uint16_t _3326 = (uint16_t)(4); + _curvea0[1] = _3326; + uint16_t _3327 = (uint16_t)(7); + _curvea0[2] = _3327; + uint16_t _3328 = (uint16_t)(8); + _curvea0[3] = _3328; + uint16_t _3329 = (uint16_t)(10); + _curvea0[4] = _3329; + uint16_t _3330 = (uint16_t)(11); + _curvea0[5] = _3330; + uint16_t _3331 = (uint16_t)(12); + _curvea0[6] = _3331; + uint16_t _3332 = (uint16_t)(13); + _curvea0[7] = _3332; + uint16_t _3333 = (uint16_t)(14); + _curvea0[8] = _3333; + uint16_t _3334 = (uint16_t)(15); + _curvea0[9] = _3334; + uint16_t _3335 = (uint16_t)(16); + _curvea0[10] = _3335; + uint16_t _3336 = (uint16_t)(17); + _curvea0[11] = _3336; + uint16_t _3337 = (uint16_t)(18); + _curvea0[12] = _3337; + uint16_t _3338 = (uint16_t)(19); + _curvea0[13] = _3338; + uint16_t _3339 = (uint16_t)(20); + _curvea0[14] = _3339; + uint16_t _3340 = (uint16_t)(21); + _curvea0[15] = _3340; + uint16_t _3341 = (uint16_t)(22); + _curvea0[16] = _3341; + uint16_t _3342 = (uint16_t)(22); + _curvea0[17] = _3342; + uint16_t _3343 = (uint16_t)(23); + _curvea0[18] = _3343; + uint16_t _3344 = (uint16_t)(24); + _curvea0[19] = _3344; + uint16_t _3345 = (uint16_t)(25); + _curvea0[20] = _3345; + uint16_t _3346 = (uint16_t)(25); + _curvea0[21] = _3346; + uint16_t _3347 = (uint16_t)(26); + _curvea0[22] = _3347; + uint16_t _3348 = (uint16_t)(27); + _curvea0[23] = _3348; + uint16_t _3349 = (uint16_t)(27); + _curvea0[24] = _3349; + uint16_t _3350 = (uint16_t)(28); + _curvea0[25] = _3350; + uint16_t _3351 = (uint16_t)(29); + _curvea0[26] = _3351; + uint16_t _3352 = (uint16_t)(29); + _curvea0[27] = _3352; + uint16_t _3353 = (uint16_t)(30); + _curvea0[28] = _3353; + uint16_t _3354 = (uint16_t)(31); + _curvea0[29] = _3354; + uint16_t _3355 = (uint16_t)(31); + _curvea0[30] = _3355; + uint16_t _3356 = (uint16_t)(32); + _curvea0[31] = _3356; + uint16_t _3357 = (uint16_t)(33); + _curvea0[32] = _3357; + uint16_t _3358 = (uint16_t)(33); + _curvea0[33] = _3358; + uint16_t _3359 = (uint16_t)(34); + _curvea0[34] = _3359; + uint16_t _3360 = (uint16_t)(34); + _curvea0[35] = _3360; + uint16_t _3361 = (uint16_t)(35); + _curvea0[36] = _3361; + uint16_t _3362 = (uint16_t)(36); + _curvea0[37] = _3362; + uint16_t _3363 = (uint16_t)(36); + _curvea0[38] = _3363; + uint16_t _3364 = (uint16_t)(37); + _curvea0[39] = _3364; + uint16_t _3365 = (uint16_t)(37); + _curvea0[40] = _3365; + uint16_t _3366 = (uint16_t)(38); + _curvea0[41] = _3366; + uint16_t _3367 = (uint16_t)(39); + _curvea0[42] = _3367; + uint16_t _3368 = (uint16_t)(39); + _curvea0[43] = _3368; + uint16_t _3369 = (uint16_t)(40); + _curvea0[44] = _3369; + uint16_t _3370 = (uint16_t)(40); + _curvea0[45] = _3370; + uint16_t _3371 = (uint16_t)(41); + _curvea0[46] = _3371; + uint16_t _3372 = (uint16_t)(41); + _curvea0[47] = _3372; + uint16_t _3373 = (uint16_t)(42); + _curvea0[48] = _3373; + uint16_t _3374 = (uint16_t)(42); + _curvea0[49] = _3374; + uint16_t _3375 = (uint16_t)(43); + _curvea0[50] = _3375; + uint16_t _3376 = (uint16_t)(44); + _curvea0[51] = _3376; + uint16_t _3377 = (uint16_t)(44); + _curvea0[52] = _3377; + uint16_t _3378 = (uint16_t)(45); + _curvea0[53] = _3378; + uint16_t _3379 = (uint16_t)(45); + _curvea0[54] = _3379; + uint16_t _3380 = (uint16_t)(46); + _curvea0[55] = _3380; + uint16_t _3381 = (uint16_t)(46); + _curvea0[56] = _3381; + uint16_t _3382 = (uint16_t)(47); + _curvea0[57] = _3382; + uint16_t _3383 = (uint16_t)(47); + _curvea0[58] = _3383; + uint16_t _3384 = (uint16_t)(48); + _curvea0[59] = _3384; + uint16_t _3385 = (uint16_t)(48); + _curvea0[60] = _3385; + uint16_t _3386 = (uint16_t)(49); + _curvea0[61] = _3386; + uint16_t _3387 = (uint16_t)(49); + _curvea0[62] = _3387; + uint16_t _3388 = (uint16_t)(50); + _curvea0[63] = _3388; + uint16_t _3389 = (uint16_t)(50); + _curvea0[64] = _3389; + uint16_t _3390 = (uint16_t)(51); + _curvea0[65] = _3390; + uint16_t _3391 = (uint16_t)(51); + _curvea0[66] = _3391; + uint16_t _3392 = (uint16_t)(52); + _curvea0[67] = _3392; + uint16_t _3393 = (uint16_t)(52); + _curvea0[68] = _3393; + uint16_t _3394 = (uint16_t)(53); + _curvea0[69] = _3394; + uint16_t _3395 = (uint16_t)(53); + _curvea0[70] = _3395; + uint16_t _3396 = (uint16_t)(54); + _curvea0[71] = _3396; + uint16_t _3397 = (uint16_t)(54); + _curvea0[72] = _3397; + uint16_t _3398 = (uint16_t)(55); + _curvea0[73] = _3398; + uint16_t _3399 = (uint16_t)(55); + _curvea0[74] = _3399; + uint16_t _3400 = (uint16_t)(56); + _curvea0[75] = _3400; + uint16_t _3401 = (uint16_t)(56); + _curvea0[76] = _3401; + uint16_t _3402 = (uint16_t)(57); + _curvea0[77] = _3402; + uint16_t _3403 = (uint16_t)(57); + _curvea0[78] = _3403; + uint16_t _3404 = (uint16_t)(58); + _curvea0[79] = _3404; + uint16_t _3405 = (uint16_t)(58); + _curvea0[80] = _3405; + uint16_t _3406 = (uint16_t)(58); + _curvea0[81] = _3406; + uint16_t _3407 = (uint16_t)(59); + _curvea0[82] = _3407; + uint16_t _3408 = (uint16_t)(59); + _curvea0[83] = _3408; + uint16_t _3409 = (uint16_t)(60); + _curvea0[84] = _3409; + uint16_t _3410 = (uint16_t)(60); + _curvea0[85] = _3410; + uint16_t _3411 = (uint16_t)(61); + _curvea0[86] = _3411; + uint16_t _3412 = (uint16_t)(61); + _curvea0[87] = _3412; + uint16_t _3413 = (uint16_t)(62); + _curvea0[88] = _3413; + uint16_t _3414 = (uint16_t)(62); + _curvea0[89] = _3414; + uint16_t _3415 = (uint16_t)(63); + _curvea0[90] = _3415; + uint16_t _3416 = (uint16_t)(63); + _curvea0[91] = _3416; + uint16_t _3417 = (uint16_t)(64); + _curvea0[92] = _3417; + uint16_t _3418 = (uint16_t)(64); + _curvea0[93] = _3418; + uint16_t _3419 = (uint16_t)(64); + _curvea0[94] = _3419; + uint16_t _3420 = (uint16_t)(65); + _curvea0[95] = _3420; + uint16_t _3421 = (uint16_t)(65); + _curvea0[96] = _3421; + uint16_t _3422 = (uint16_t)(66); + _curvea0[97] = _3422; + uint16_t _3423 = (uint16_t)(66); + _curvea0[98] = _3423; + uint16_t _3424 = (uint16_t)(67); + _curvea0[99] = _3424; + uint16_t _3425 = (uint16_t)(67); + _curvea0[100] = _3425; + uint16_t _3426 = (uint16_t)(68); + _curvea0[101] = _3426; + uint16_t _3427 = (uint16_t)(68); + _curvea0[102] = _3427; + uint16_t _3428 = (uint16_t)(68); + _curvea0[103] = _3428; + uint16_t _3429 = (uint16_t)(69); + _curvea0[104] = _3429; + uint16_t _3430 = (uint16_t)(69); + _curvea0[105] = _3430; + uint16_t _3431 = (uint16_t)(70); + _curvea0[106] = _3431; + uint16_t _3432 = (uint16_t)(70); + _curvea0[107] = _3432; + uint16_t _3433 = (uint16_t)(71); + _curvea0[108] = _3433; + uint16_t _3434 = (uint16_t)(71); + _curvea0[109] = _3434; + uint16_t _3435 = (uint16_t)(71); + _curvea0[110] = _3435; + uint16_t _3436 = (uint16_t)(72); + _curvea0[111] = _3436; + uint16_t _3437 = (uint16_t)(72); + _curvea0[112] = _3437; + uint16_t _3438 = (uint16_t)(73); + _curvea0[113] = _3438; + uint16_t _3439 = (uint16_t)(73); + _curvea0[114] = _3439; + uint16_t _3440 = (uint16_t)(74); + _curvea0[115] = _3440; + uint16_t _3441 = (uint16_t)(74); + _curvea0[116] = _3441; + uint16_t _3442 = (uint16_t)(74); + _curvea0[117] = _3442; + uint16_t _3443 = (uint16_t)(75); + _curvea0[118] = _3443; + uint16_t _3444 = (uint16_t)(75); + _curvea0[119] = _3444; + uint16_t _3445 = (uint16_t)(76); + _curvea0[120] = _3445; + uint16_t _3446 = (uint16_t)(76); + _curvea0[121] = _3446; + uint16_t _3447 = (uint16_t)(77); + _curvea0[122] = _3447; + uint16_t _3448 = (uint16_t)(77); + _curvea0[123] = _3448; + uint16_t _3449 = (uint16_t)(77); + _curvea0[124] = _3449; + uint16_t _3450 = (uint16_t)(78); + _curvea0[125] = _3450; + uint16_t _3451 = (uint16_t)(78); + _curvea0[126] = _3451; + uint16_t _3452 = (uint16_t)(79); + _curvea0[127] = _3452; + uint16_t _3453 = (uint16_t)(79); + _curvea0[128] = _3453; + uint16_t _3454 = (uint16_t)(79); + _curvea0[129] = _3454; + uint16_t _3455 = (uint16_t)(80); + _curvea0[130] = _3455; + uint16_t _3456 = (uint16_t)(80); + _curvea0[131] = _3456; + uint16_t _3457 = (uint16_t)(81); + _curvea0[132] = _3457; + uint16_t _3458 = (uint16_t)(81); + _curvea0[133] = _3458; + uint16_t _3459 = (uint16_t)(82); + _curvea0[134] = _3459; + uint16_t _3460 = (uint16_t)(82); + _curvea0[135] = _3460; + uint16_t _3461 = (uint16_t)(82); + _curvea0[136] = _3461; + uint16_t _3462 = (uint16_t)(83); + _curvea0[137] = _3462; + uint16_t _3463 = (uint16_t)(83); + _curvea0[138] = _3463; + uint16_t _3464 = (uint16_t)(84); + _curvea0[139] = _3464; + uint16_t _3465 = (uint16_t)(84); + _curvea0[140] = _3465; + uint16_t _3466 = (uint16_t)(84); + _curvea0[141] = _3466; + uint16_t _3467 = (uint16_t)(85); + _curvea0[142] = _3467; + uint16_t _3468 = (uint16_t)(85); + _curvea0[143] = _3468; + uint16_t _3469 = (uint16_t)(86); + _curvea0[144] = _3469; + uint16_t _3470 = (uint16_t)(86); + _curvea0[145] = _3470; + uint16_t _3471 = (uint16_t)(86); + _curvea0[146] = _3471; + uint16_t _3472 = (uint16_t)(87); + _curvea0[147] = _3472; + uint16_t _3473 = (uint16_t)(87); + _curvea0[148] = _3473; + uint16_t _3474 = (uint16_t)(88); + _curvea0[149] = _3474; + uint16_t _3475 = (uint16_t)(88); + _curvea0[150] = _3475; + uint16_t _3476 = (uint16_t)(88); + _curvea0[151] = _3476; + uint16_t _3477 = (uint16_t)(89); + _curvea0[152] = _3477; + uint16_t _3478 = (uint16_t)(89); + _curvea0[153] = _3478; + uint16_t _3479 = (uint16_t)(90); + _curvea0[154] = _3479; + uint16_t _3480 = (uint16_t)(90); + _curvea0[155] = _3480; + uint16_t _3481 = (uint16_t)(90); + _curvea0[156] = _3481; + uint16_t _3482 = (uint16_t)(91); + _curvea0[157] = _3482; + uint16_t _3483 = (uint16_t)(91); + _curvea0[158] = _3483; + uint16_t _3484 = (uint16_t)(92); + _curvea0[159] = _3484; + uint16_t _3485 = (uint16_t)(92); + _curvea0[160] = _3485; + uint16_t _3486 = (uint16_t)(92); + _curvea0[161] = _3486; + uint16_t _3487 = (uint16_t)(93); + _curvea0[162] = _3487; + uint16_t _3488 = (uint16_t)(93); + _curvea0[163] = _3488; + uint16_t _3489 = (uint16_t)(93); + _curvea0[164] = _3489; + uint16_t _3490 = (uint16_t)(94); + _curvea0[165] = _3490; + uint16_t _3491 = (uint16_t)(94); + _curvea0[166] = _3491; + uint16_t _3492 = (uint16_t)(95); + _curvea0[167] = _3492; + uint16_t _3493 = (uint16_t)(95); + _curvea0[168] = _3493; + uint16_t _3494 = (uint16_t)(95); + _curvea0[169] = _3494; + uint16_t _3495 = (uint16_t)(96); + _curvea0[170] = _3495; + uint16_t _3496 = (uint16_t)(96); + _curvea0[171] = _3496; + uint16_t _3497 = (uint16_t)(97); + _curvea0[172] = _3497; + uint16_t _3498 = (uint16_t)(97); + _curvea0[173] = _3498; + uint16_t _3499 = (uint16_t)(97); + _curvea0[174] = _3499; + uint16_t _3500 = (uint16_t)(98); + _curvea0[175] = _3500; + uint16_t _3501 = (uint16_t)(98); + _curvea0[176] = _3501; + uint16_t _3502 = (uint16_t)(99); + _curvea0[177] = _3502; + uint16_t _3503 = (uint16_t)(99); + _curvea0[178] = _3503; + uint16_t _3504 = (uint16_t)(99); + _curvea0[179] = _3504; + uint16_t _3505 = (uint16_t)(100); + _curvea0[180] = _3505; + uint16_t _3506 = (uint16_t)(100); + _curvea0[181] = _3506; + uint16_t _3507 = (uint16_t)(100); + _curvea0[182] = _3507; + uint16_t _3508 = (uint16_t)(101); + _curvea0[183] = _3508; + uint16_t _3509 = (uint16_t)(101); + _curvea0[184] = _3509; + uint16_t _3510 = (uint16_t)(102); + _curvea0[185] = _3510; + uint16_t _3511 = (uint16_t)(102); + _curvea0[186] = _3511; + uint16_t _3512 = (uint16_t)(102); + _curvea0[187] = _3512; + uint16_t _3513 = (uint16_t)(103); + _curvea0[188] = _3513; + uint16_t _3514 = (uint16_t)(103); + _curvea0[189] = _3514; + uint16_t _3515 = (uint16_t)(103); + _curvea0[190] = _3515; + uint16_t _3516 = (uint16_t)(104); + _curvea0[191] = _3516; + uint16_t _3517 = (uint16_t)(104); + _curvea0[192] = _3517; + uint16_t _3518 = (uint16_t)(105); + _curvea0[193] = _3518; + uint16_t _3519 = (uint16_t)(105); + _curvea0[194] = _3519; + uint16_t _3520 = (uint16_t)(105); + _curvea0[195] = _3520; + uint16_t _3521 = (uint16_t)(106); + _curvea0[196] = _3521; + uint16_t _3522 = (uint16_t)(106); + _curvea0[197] = _3522; + uint16_t _3523 = (uint16_t)(106); + _curvea0[198] = _3523; + uint16_t _3524 = (uint16_t)(107); + _curvea0[199] = _3524; + uint16_t _3525 = (uint16_t)(107); + _curvea0[200] = _3525; + uint16_t _3526 = (uint16_t)(108); + _curvea0[201] = _3526; + uint16_t _3527 = (uint16_t)(108); + _curvea0[202] = _3527; + uint16_t _3528 = (uint16_t)(108); + _curvea0[203] = _3528; + uint16_t _3529 = (uint16_t)(109); + _curvea0[204] = _3529; + uint16_t _3530 = (uint16_t)(109); + _curvea0[205] = _3530; + uint16_t _3531 = (uint16_t)(109); + _curvea0[206] = _3531; + uint16_t _3532 = (uint16_t)(110); + _curvea0[207] = _3532; + uint16_t _3533 = (uint16_t)(110); + _curvea0[208] = _3533; + uint16_t _3534 = (uint16_t)(111); + _curvea0[209] = _3534; + uint16_t _3535 = (uint16_t)(111); + _curvea0[210] = _3535; + uint16_t _3536 = (uint16_t)(111); + _curvea0[211] = _3536; + uint16_t _3537 = (uint16_t)(112); + _curvea0[212] = _3537; + uint16_t _3538 = (uint16_t)(112); + _curvea0[213] = _3538; + uint16_t _3539 = (uint16_t)(112); + _curvea0[214] = _3539; + uint16_t _3540 = (uint16_t)(113); + _curvea0[215] = _3540; + uint16_t _3541 = (uint16_t)(113); + _curvea0[216] = _3541; + uint16_t _3542 = (uint16_t)(113); + _curvea0[217] = _3542; + uint16_t _3543 = (uint16_t)(114); + _curvea0[218] = _3543; + uint16_t _3544 = (uint16_t)(114); + _curvea0[219] = _3544; + uint16_t _3545 = (uint16_t)(115); + _curvea0[220] = _3545; + uint16_t _3546 = (uint16_t)(115); + _curvea0[221] = _3546; + uint16_t _3547 = (uint16_t)(115); + _curvea0[222] = _3547; + uint16_t _3548 = (uint16_t)(116); + _curvea0[223] = _3548; + uint16_t _3549 = (uint16_t)(116); + _curvea0[224] = _3549; + uint16_t _3550 = (uint16_t)(116); + _curvea0[225] = _3550; + uint16_t _3551 = (uint16_t)(117); + _curvea0[226] = _3551; + uint16_t _3552 = (uint16_t)(117); + _curvea0[227] = _3552; + uint16_t _3553 = (uint16_t)(117); + _curvea0[228] = _3553; + uint16_t _3554 = (uint16_t)(118); + _curvea0[229] = _3554; + uint16_t _3555 = (uint16_t)(118); + _curvea0[230] = _3555; + uint16_t _3556 = (uint16_t)(119); + _curvea0[231] = _3556; + uint16_t _3557 = (uint16_t)(119); + _curvea0[232] = _3557; + uint16_t _3558 = (uint16_t)(119); + _curvea0[233] = _3558; + uint16_t _3559 = (uint16_t)(120); + _curvea0[234] = _3559; + uint16_t _3560 = (uint16_t)(120); + _curvea0[235] = _3560; + uint16_t _3561 = (uint16_t)(120); + _curvea0[236] = _3561; + uint16_t _3562 = (uint16_t)(121); + _curvea0[237] = _3562; + uint16_t _3563 = (uint16_t)(121); + _curvea0[238] = _3563; + uint16_t _3564 = (uint16_t)(121); + _curvea0[239] = _3564; + uint16_t _3565 = (uint16_t)(122); + _curvea0[240] = _3565; + uint16_t _3566 = (uint16_t)(122); + _curvea0[241] = _3566; + uint16_t _3567 = (uint16_t)(123); + _curvea0[242] = _3567; + uint16_t _3568 = (uint16_t)(123); + _curvea0[243] = _3568; + uint16_t _3569 = (uint16_t)(123); + _curvea0[244] = _3569; + uint16_t _3570 = (uint16_t)(124); + _curvea0[245] = _3570; + uint16_t _3571 = (uint16_t)(124); + _curvea0[246] = _3571; + uint16_t _3572 = (uint16_t)(124); + _curvea0[247] = _3572; + uint16_t _3573 = (uint16_t)(125); + _curvea0[248] = _3573; + uint16_t _3574 = (uint16_t)(125); + _curvea0[249] = _3574; + uint16_t _3575 = (uint16_t)(125); + _curvea0[250] = _3575; + uint16_t _3576 = (uint16_t)(126); + _curvea0[251] = _3576; + uint16_t _3577 = (uint16_t)(126); + _curvea0[252] = _3577; + uint16_t _3578 = (uint16_t)(126); + _curvea0[253] = _3578; + uint16_t _3579 = (uint16_t)(127); + _curvea0[254] = _3579; + uint16_t _3580 = (uint16_t)(127); + _curvea0[255] = _3580; + uint16_t _3581 = (uint16_t)(128); + _curvea0[256] = _3581; + uint16_t _3582 = (uint16_t)(128); + _curvea0[257] = _3582; + uint16_t _3583 = (uint16_t)(128); + _curvea0[258] = _3583; + uint16_t _3584 = (uint16_t)(129); + _curvea0[259] = _3584; + uint16_t _3585 = (uint16_t)(129); + _curvea0[260] = _3585; + uint16_t _3586 = (uint16_t)(129); + _curvea0[261] = _3586; + uint16_t _3587 = (uint16_t)(130); + _curvea0[262] = _3587; + uint16_t _3588 = (uint16_t)(130); + _curvea0[263] = _3588; + uint16_t _3589 = (uint16_t)(130); + _curvea0[264] = _3589; + uint16_t _3590 = (uint16_t)(131); + _curvea0[265] = _3590; + uint16_t _3591 = (uint16_t)(131); + _curvea0[266] = _3591; + uint16_t _3592 = (uint16_t)(131); + _curvea0[267] = _3592; + uint16_t _3593 = (uint16_t)(132); + _curvea0[268] = _3593; + uint16_t _3594 = (uint16_t)(132); + _curvea0[269] = _3594; + uint16_t _3595 = (uint16_t)(132); + _curvea0[270] = _3595; + uint16_t _3596 = (uint16_t)(133); + _curvea0[271] = _3596; + uint16_t _3597 = (uint16_t)(133); + _curvea0[272] = _3597; + uint16_t _3598 = (uint16_t)(133); + _curvea0[273] = _3598; + uint16_t _3599 = (uint16_t)(134); + _curvea0[274] = _3599; + uint16_t _3600 = (uint16_t)(134); + _curvea0[275] = _3600; + uint16_t _3601 = (uint16_t)(134); + _curvea0[276] = _3601; + uint16_t _3602 = (uint16_t)(135); + _curvea0[277] = _3602; + uint16_t _3603 = (uint16_t)(135); + _curvea0[278] = _3603; + uint16_t _3604 = (uint16_t)(135); + _curvea0[279] = _3604; + uint16_t _3605 = (uint16_t)(136); + _curvea0[280] = _3605; + uint16_t _3606 = (uint16_t)(136); + _curvea0[281] = _3606; + uint16_t _3607 = (uint16_t)(136); + _curvea0[282] = _3607; + uint16_t _3608 = (uint16_t)(137); + _curvea0[283] = _3608; + uint16_t _3609 = (uint16_t)(137); + _curvea0[284] = _3609; + uint16_t _3610 = (uint16_t)(137); + _curvea0[285] = _3610; + uint16_t _3611 = (uint16_t)(138); + _curvea0[286] = _3611; + uint16_t _3612 = (uint16_t)(138); + _curvea0[287] = _3612; + uint16_t _3613 = (uint16_t)(138); + _curvea0[288] = _3613; + uint16_t _3614 = (uint16_t)(139); + _curvea0[289] = _3614; + uint16_t _3615 = (uint16_t)(139); + _curvea0[290] = _3615; + uint16_t _3616 = (uint16_t)(139); + _curvea0[291] = _3616; + uint16_t _3617 = (uint16_t)(140); + _curvea0[292] = _3617; + uint16_t _3618 = (uint16_t)(140); + _curvea0[293] = _3618; + uint16_t _3619 = (uint16_t)(140); + _curvea0[294] = _3619; + uint16_t _3620 = (uint16_t)(141); + _curvea0[295] = _3620; + uint16_t _3621 = (uint16_t)(141); + _curvea0[296] = _3621; + uint16_t _3622 = (uint16_t)(141); + _curvea0[297] = _3622; + uint16_t _3623 = (uint16_t)(141); + _curvea0[298] = _3623; + uint16_t _3624 = (uint16_t)(142); + _curvea0[299] = _3624; + uint16_t _3625 = (uint16_t)(142); + _curvea0[300] = _3625; + uint16_t _3626 = (uint16_t)(142); + _curvea0[301] = _3626; + uint16_t _3627 = (uint16_t)(143); + _curvea0[302] = _3627; + uint16_t _3628 = (uint16_t)(143); + _curvea0[303] = _3628; + uint16_t _3629 = (uint16_t)(143); + _curvea0[304] = _3629; + uint16_t _3630 = (uint16_t)(144); + _curvea0[305] = _3630; + uint16_t _3631 = (uint16_t)(144); + _curvea0[306] = _3631; + uint16_t _3632 = (uint16_t)(144); + _curvea0[307] = _3632; + uint16_t _3633 = (uint16_t)(145); + _curvea0[308] = _3633; + uint16_t _3634 = (uint16_t)(145); + _curvea0[309] = _3634; + uint16_t _3635 = (uint16_t)(145); + _curvea0[310] = _3635; + uint16_t _3636 = (uint16_t)(145); + _curvea0[311] = _3636; + uint16_t _3637 = (uint16_t)(146); + _curvea0[312] = _3637; + uint16_t _3638 = (uint16_t)(146); + _curvea0[313] = _3638; + uint16_t _3639 = (uint16_t)(146); + _curvea0[314] = _3639; + uint16_t _3640 = (uint16_t)(147); + _curvea0[315] = _3640; + uint16_t _3641 = (uint16_t)(147); + _curvea0[316] = _3641; + uint16_t _3642 = (uint16_t)(147); + _curvea0[317] = _3642; + uint16_t _3643 = (uint16_t)(148); + _curvea0[318] = _3643; + uint16_t _3644 = (uint16_t)(148); + _curvea0[319] = _3644; + uint16_t _3645 = (uint16_t)(148); + _curvea0[320] = _3645; + uint16_t _3646 = (uint16_t)(148); + _curvea0[321] = _3646; + uint16_t _3647 = (uint16_t)(149); + _curvea0[322] = _3647; + uint16_t _3648 = (uint16_t)(149); + _curvea0[323] = _3648; + uint16_t _3649 = (uint16_t)(149); + _curvea0[324] = _3649; + uint16_t _3650 = (uint16_t)(150); + _curvea0[325] = _3650; + uint16_t _3651 = (uint16_t)(150); + _curvea0[326] = _3651; + uint16_t _3652 = (uint16_t)(150); + _curvea0[327] = _3652; + uint16_t _3653 = (uint16_t)(150); + _curvea0[328] = _3653; + uint16_t _3654 = (uint16_t)(151); + _curvea0[329] = _3654; + uint16_t _3655 = (uint16_t)(151); + _curvea0[330] = _3655; + uint16_t _3656 = (uint16_t)(151); + _curvea0[331] = _3656; + uint16_t _3657 = (uint16_t)(152); + _curvea0[332] = _3657; + uint16_t _3658 = (uint16_t)(152); + _curvea0[333] = _3658; + uint16_t _3659 = (uint16_t)(152); + _curvea0[334] = _3659; + uint16_t _3660 = (uint16_t)(152); + _curvea0[335] = _3660; + uint16_t _3661 = (uint16_t)(153); + _curvea0[336] = _3661; + uint16_t _3662 = (uint16_t)(153); + _curvea0[337] = _3662; + uint16_t _3663 = (uint16_t)(153); + _curvea0[338] = _3663; + uint16_t _3664 = (uint16_t)(154); + _curvea0[339] = _3664; + uint16_t _3665 = (uint16_t)(154); + _curvea0[340] = _3665; + uint16_t _3666 = (uint16_t)(154); + _curvea0[341] = _3666; + uint16_t _3667 = (uint16_t)(154); + _curvea0[342] = _3667; + uint16_t _3668 = (uint16_t)(155); + _curvea0[343] = _3668; + uint16_t _3669 = (uint16_t)(155); + _curvea0[344] = _3669; + uint16_t _3670 = (uint16_t)(155); + _curvea0[345] = _3670; + uint16_t _3671 = (uint16_t)(156); + _curvea0[346] = _3671; + uint16_t _3672 = (uint16_t)(156); + _curvea0[347] = _3672; + uint16_t _3673 = (uint16_t)(156); + _curvea0[348] = _3673; + uint16_t _3674 = (uint16_t)(156); + _curvea0[349] = _3674; + uint16_t _3675 = (uint16_t)(157); + _curvea0[350] = _3675; + uint16_t _3676 = (uint16_t)(157); + _curvea0[351] = _3676; + uint16_t _3677 = (uint16_t)(157); + _curvea0[352] = _3677; + uint16_t _3678 = (uint16_t)(157); + _curvea0[353] = _3678; + uint16_t _3679 = (uint16_t)(158); + _curvea0[354] = _3679; + uint16_t _3680 = (uint16_t)(158); + _curvea0[355] = _3680; + uint16_t _3681 = (uint16_t)(158); + _curvea0[356] = _3681; + uint16_t _3682 = (uint16_t)(159); + _curvea0[357] = _3682; + uint16_t _3683 = (uint16_t)(159); + _curvea0[358] = _3683; + uint16_t _3684 = (uint16_t)(159); + _curvea0[359] = _3684; + uint16_t _3685 = (uint16_t)(159); + _curvea0[360] = _3685; + uint16_t _3686 = (uint16_t)(160); + _curvea0[361] = _3686; + uint16_t _3687 = (uint16_t)(160); + _curvea0[362] = _3687; + uint16_t _3688 = (uint16_t)(160); + _curvea0[363] = _3688; + uint16_t _3689 = (uint16_t)(160); + _curvea0[364] = _3689; + uint16_t _3690 = (uint16_t)(161); + _curvea0[365] = _3690; + uint16_t _3691 = (uint16_t)(161); + _curvea0[366] = _3691; + uint16_t _3692 = (uint16_t)(161); + _curvea0[367] = _3692; + uint16_t _3693 = (uint16_t)(161); + _curvea0[368] = _3693; + uint16_t _3694 = (uint16_t)(162); + _curvea0[369] = _3694; + uint16_t _3695 = (uint16_t)(162); + _curvea0[370] = _3695; + uint16_t _3696 = (uint16_t)(162); + _curvea0[371] = _3696; + uint16_t _3697 = (uint16_t)(162); + _curvea0[372] = _3697; + uint16_t _3698 = (uint16_t)(163); + _curvea0[373] = _3698; + uint16_t _3699 = (uint16_t)(163); + _curvea0[374] = _3699; + uint16_t _3700 = (uint16_t)(163); + _curvea0[375] = _3700; + uint16_t _3701 = (uint16_t)(163); + _curvea0[376] = _3701; + uint16_t _3702 = (uint16_t)(164); + _curvea0[377] = _3702; + uint16_t _3703 = (uint16_t)(164); + _curvea0[378] = _3703; + uint16_t _3704 = (uint16_t)(164); + _curvea0[379] = _3704; + uint16_t _3705 = (uint16_t)(164); + _curvea0[380] = _3705; + uint16_t _3706 = (uint16_t)(165); + _curvea0[381] = _3706; + uint16_t _3707 = (uint16_t)(165); + _curvea0[382] = _3707; + uint16_t _3708 = (uint16_t)(165); + _curvea0[383] = _3708; + uint16_t _3709 = (uint16_t)(166); + _curvea0[384] = _3709; + uint16_t _3710 = (uint16_t)(166); + _curvea0[385] = _3710; + uint16_t _3711 = (uint16_t)(166); + _curvea0[386] = _3711; + uint16_t _3712 = (uint16_t)(166); + _curvea0[387] = _3712; + uint16_t _3713 = (uint16_t)(167); + _curvea0[388] = _3713; + uint16_t _3714 = (uint16_t)(167); + _curvea0[389] = _3714; + uint16_t _3715 = (uint16_t)(167); + _curvea0[390] = _3715; + uint16_t _3716 = (uint16_t)(167); + _curvea0[391] = _3716; + uint16_t _3717 = (uint16_t)(167); + _curvea0[392] = _3717; + uint16_t _3718 = (uint16_t)(168); + _curvea0[393] = _3718; + uint16_t _3719 = (uint16_t)(168); + _curvea0[394] = _3719; + uint16_t _3720 = (uint16_t)(168); + _curvea0[395] = _3720; + uint16_t _3721 = (uint16_t)(168); + _curvea0[396] = _3721; + uint16_t _3722 = (uint16_t)(169); + _curvea0[397] = _3722; + uint16_t _3723 = (uint16_t)(169); + _curvea0[398] = _3723; + uint16_t _3724 = (uint16_t)(169); + _curvea0[399] = _3724; + uint16_t _3725 = (uint16_t)(169); + _curvea0[400] = _3725; + uint16_t _3726 = (uint16_t)(170); + _curvea0[401] = _3726; + uint16_t _3727 = (uint16_t)(170); + _curvea0[402] = _3727; + uint16_t _3728 = (uint16_t)(170); + _curvea0[403] = _3728; + uint16_t _3729 = (uint16_t)(170); + _curvea0[404] = _3729; + uint16_t _3730 = (uint16_t)(171); + _curvea0[405] = _3730; + uint16_t _3731 = (uint16_t)(171); + _curvea0[406] = _3731; + uint16_t _3732 = (uint16_t)(171); + _curvea0[407] = _3732; + uint16_t _3733 = (uint16_t)(171); + _curvea0[408] = _3733; + uint16_t _3734 = (uint16_t)(172); + _curvea0[409] = _3734; + uint16_t _3735 = (uint16_t)(172); + _curvea0[410] = _3735; + uint16_t _3736 = (uint16_t)(172); + _curvea0[411] = _3736; + uint16_t _3737 = (uint16_t)(172); + _curvea0[412] = _3737; + uint16_t _3738 = (uint16_t)(173); + _curvea0[413] = _3738; + uint16_t _3739 = (uint16_t)(173); + _curvea0[414] = _3739; + uint16_t _3740 = (uint16_t)(173); + _curvea0[415] = _3740; + uint16_t _3741 = (uint16_t)(173); + _curvea0[416] = _3741; + uint16_t _3742 = (uint16_t)(173); + _curvea0[417] = _3742; + uint16_t _3743 = (uint16_t)(174); + _curvea0[418] = _3743; + uint16_t _3744 = (uint16_t)(174); + _curvea0[419] = _3744; + uint16_t _3745 = (uint16_t)(174); + _curvea0[420] = _3745; + uint16_t _3746 = (uint16_t)(174); + _curvea0[421] = _3746; + uint16_t _3747 = (uint16_t)(175); + _curvea0[422] = _3747; + uint16_t _3748 = (uint16_t)(175); + _curvea0[423] = _3748; + uint16_t _3749 = (uint16_t)(175); + _curvea0[424] = _3749; + uint16_t _3750 = (uint16_t)(175); + _curvea0[425] = _3750; + uint16_t _3751 = (uint16_t)(176); + _curvea0[426] = _3751; + uint16_t _3752 = (uint16_t)(176); + _curvea0[427] = _3752; + uint16_t _3753 = (uint16_t)(176); + _curvea0[428] = _3753; + uint16_t _3754 = (uint16_t)(176); + _curvea0[429] = _3754; + uint16_t _3755 = (uint16_t)(176); + _curvea0[430] = _3755; + uint16_t _3756 = (uint16_t)(177); + _curvea0[431] = _3756; + uint16_t _3757 = (uint16_t)(177); + _curvea0[432] = _3757; + uint16_t _3758 = (uint16_t)(177); + _curvea0[433] = _3758; + uint16_t _3759 = (uint16_t)(177); + _curvea0[434] = _3759; + uint16_t _3760 = (uint16_t)(178); + _curvea0[435] = _3760; + uint16_t _3761 = (uint16_t)(178); + _curvea0[436] = _3761; + uint16_t _3762 = (uint16_t)(178); + _curvea0[437] = _3762; + uint16_t _3763 = (uint16_t)(178); + _curvea0[438] = _3763; + uint16_t _3764 = (uint16_t)(178); + _curvea0[439] = _3764; + uint16_t _3765 = (uint16_t)(179); + _curvea0[440] = _3765; + uint16_t _3766 = (uint16_t)(179); + _curvea0[441] = _3766; + uint16_t _3767 = (uint16_t)(179); + _curvea0[442] = _3767; + uint16_t _3768 = (uint16_t)(179); + _curvea0[443] = _3768; + uint16_t _3769 = (uint16_t)(180); + _curvea0[444] = _3769; + uint16_t _3770 = (uint16_t)(180); + _curvea0[445] = _3770; + uint16_t _3771 = (uint16_t)(180); + _curvea0[446] = _3771; + uint16_t _3772 = (uint16_t)(180); + _curvea0[447] = _3772; + uint16_t _3773 = (uint16_t)(180); + _curvea0[448] = _3773; + uint16_t _3774 = (uint16_t)(181); + _curvea0[449] = _3774; + uint16_t _3775 = (uint16_t)(181); + _curvea0[450] = _3775; + uint16_t _3776 = (uint16_t)(181); + _curvea0[451] = _3776; + uint16_t _3777 = (uint16_t)(181); + _curvea0[452] = _3777; + uint16_t _3778 = (uint16_t)(181); + _curvea0[453] = _3778; + uint16_t _3779 = (uint16_t)(182); + _curvea0[454] = _3779; + uint16_t _3780 = (uint16_t)(182); + _curvea0[455] = _3780; + uint16_t _3781 = (uint16_t)(182); + _curvea0[456] = _3781; + uint16_t _3782 = (uint16_t)(182); + _curvea0[457] = _3782; + uint16_t _3783 = (uint16_t)(183); + _curvea0[458] = _3783; + uint16_t _3784 = (uint16_t)(183); + _curvea0[459] = _3784; + uint16_t _3785 = (uint16_t)(183); + _curvea0[460] = _3785; + uint16_t _3786 = (uint16_t)(183); + _curvea0[461] = _3786; + uint16_t _3787 = (uint16_t)(183); + _curvea0[462] = _3787; + uint16_t _3788 = (uint16_t)(184); + _curvea0[463] = _3788; + uint16_t _3789 = (uint16_t)(184); + _curvea0[464] = _3789; + uint16_t _3790 = (uint16_t)(184); + _curvea0[465] = _3790; + uint16_t _3791 = (uint16_t)(184); + _curvea0[466] = _3791; + uint16_t _3792 = (uint16_t)(184); + _curvea0[467] = _3792; + uint16_t _3793 = (uint16_t)(185); + _curvea0[468] = _3793; + uint16_t _3794 = (uint16_t)(185); + _curvea0[469] = _3794; + uint16_t _3795 = (uint16_t)(185); + _curvea0[470] = _3795; + uint16_t _3796 = (uint16_t)(185); + _curvea0[471] = _3796; + uint16_t _3797 = (uint16_t)(185); + _curvea0[472] = _3797; + uint16_t _3798 = (uint16_t)(186); + _curvea0[473] = _3798; + uint16_t _3799 = (uint16_t)(186); + _curvea0[474] = _3799; + uint16_t _3800 = (uint16_t)(186); + _curvea0[475] = _3800; + uint16_t _3801 = (uint16_t)(186); + _curvea0[476] = _3801; + uint16_t _3802 = (uint16_t)(187); + _curvea0[477] = _3802; + uint16_t _3803 = (uint16_t)(187); + _curvea0[478] = _3803; + uint16_t _3804 = (uint16_t)(187); + _curvea0[479] = _3804; + uint16_t _3805 = (uint16_t)(187); + _curvea0[480] = _3805; + uint16_t _3806 = (uint16_t)(187); + _curvea0[481] = _3806; + uint16_t _3807 = (uint16_t)(188); + _curvea0[482] = _3807; + uint16_t _3808 = (uint16_t)(188); + _curvea0[483] = _3808; + uint16_t _3809 = (uint16_t)(188); + _curvea0[484] = _3809; + uint16_t _3810 = (uint16_t)(188); + _curvea0[485] = _3810; + uint16_t _3811 = (uint16_t)(188); + _curvea0[486] = _3811; + uint16_t _3812 = (uint16_t)(189); + _curvea0[487] = _3812; + uint16_t _3813 = (uint16_t)(189); + _curvea0[488] = _3813; + uint16_t _3814 = (uint16_t)(189); + _curvea0[489] = _3814; + uint16_t _3815 = (uint16_t)(189); + _curvea0[490] = _3815; + uint16_t _3816 = (uint16_t)(189); + _curvea0[491] = _3816; + uint16_t _3817 = (uint16_t)(190); + _curvea0[492] = _3817; + uint16_t _3818 = (uint16_t)(190); + _curvea0[493] = _3818; + uint16_t _3819 = (uint16_t)(190); + _curvea0[494] = _3819; + uint16_t _3820 = (uint16_t)(190); + _curvea0[495] = _3820; + uint16_t _3821 = (uint16_t)(190); + _curvea0[496] = _3821; + uint16_t _3822 = (uint16_t)(190); + _curvea0[497] = _3822; + uint16_t _3823 = (uint16_t)(191); + _curvea0[498] = _3823; + uint16_t _3824 = (uint16_t)(191); + _curvea0[499] = _3824; + uint16_t _3825 = (uint16_t)(191); + _curvea0[500] = _3825; + uint16_t _3826 = (uint16_t)(191); + _curvea0[501] = _3826; + uint16_t _3827 = (uint16_t)(191); + _curvea0[502] = _3827; + uint16_t _3828 = (uint16_t)(192); + _curvea0[503] = _3828; + uint16_t _3829 = (uint16_t)(192); + _curvea0[504] = _3829; + uint16_t _3830 = (uint16_t)(192); + _curvea0[505] = _3830; + uint16_t _3831 = (uint16_t)(192); + _curvea0[506] = _3831; + uint16_t _3832 = (uint16_t)(192); + _curvea0[507] = _3832; + uint16_t _3833 = (uint16_t)(193); + _curvea0[508] = _3833; + uint16_t _3834 = (uint16_t)(193); + _curvea0[509] = _3834; + uint16_t _3835 = (uint16_t)(193); + _curvea0[510] = _3835; + uint16_t _3836 = (uint16_t)(193); + _curvea0[511] = _3836; + uint16_t _3837 = (uint16_t)(193); + _curvea0[512] = _3837; + uint16_t _3838 = (uint16_t)(194); + _curvea0[513] = _3838; + uint16_t _3839 = (uint16_t)(194); + _curvea0[514] = _3839; + uint16_t _3840 = (uint16_t)(194); + _curvea0[515] = _3840; + uint16_t _3841 = (uint16_t)(194); + _curvea0[516] = _3841; + uint16_t _3842 = (uint16_t)(194); + _curvea0[517] = _3842; + uint16_t _3843 = (uint16_t)(195); + _curvea0[518] = _3843; + uint16_t _3844 = (uint16_t)(195); + _curvea0[519] = _3844; + uint16_t _3845 = (uint16_t)(195); + _curvea0[520] = _3845; + uint16_t _3846 = (uint16_t)(195); + _curvea0[521] = _3846; + uint16_t _3847 = (uint16_t)(195); + _curvea0[522] = _3847; + uint16_t _3848 = (uint16_t)(195); + _curvea0[523] = _3848; + uint16_t _3849 = (uint16_t)(196); + _curvea0[524] = _3849; + uint16_t _3850 = (uint16_t)(196); + _curvea0[525] = _3850; + uint16_t _3851 = (uint16_t)(196); + _curvea0[526] = _3851; + uint16_t _3852 = (uint16_t)(196); + _curvea0[527] = _3852; + uint16_t _3853 = (uint16_t)(196); + _curvea0[528] = _3853; + uint16_t _3854 = (uint16_t)(197); + _curvea0[529] = _3854; + uint16_t _3855 = (uint16_t)(197); + _curvea0[530] = _3855; + uint16_t _3856 = (uint16_t)(197); + _curvea0[531] = _3856; + uint16_t _3857 = (uint16_t)(197); + _curvea0[532] = _3857; + uint16_t _3858 = (uint16_t)(197); + _curvea0[533] = _3858; + uint16_t _3859 = (uint16_t)(197); + _curvea0[534] = _3859; + uint16_t _3860 = (uint16_t)(198); + _curvea0[535] = _3860; + uint16_t _3861 = (uint16_t)(198); + _curvea0[536] = _3861; + uint16_t _3862 = (uint16_t)(198); + _curvea0[537] = _3862; + uint16_t _3863 = (uint16_t)(198); + _curvea0[538] = _3863; + uint16_t _3864 = (uint16_t)(198); + _curvea0[539] = _3864; + uint16_t _3865 = (uint16_t)(199); + _curvea0[540] = _3865; + uint16_t _3866 = (uint16_t)(199); + _curvea0[541] = _3866; + uint16_t _3867 = (uint16_t)(199); + _curvea0[542] = _3867; + uint16_t _3868 = (uint16_t)(199); + _curvea0[543] = _3868; + uint16_t _3869 = (uint16_t)(199); + _curvea0[544] = _3869; + uint16_t _3870 = (uint16_t)(199); + _curvea0[545] = _3870; + uint16_t _3871 = (uint16_t)(200); + _curvea0[546] = _3871; + uint16_t _3872 = (uint16_t)(200); + _curvea0[547] = _3872; + uint16_t _3873 = (uint16_t)(200); + _curvea0[548] = _3873; + uint16_t _3874 = (uint16_t)(200); + _curvea0[549] = _3874; + uint16_t _3875 = (uint16_t)(200); + _curvea0[550] = _3875; + uint16_t _3876 = (uint16_t)(200); + _curvea0[551] = _3876; + uint16_t _3877 = (uint16_t)(201); + _curvea0[552] = _3877; + uint16_t _3878 = (uint16_t)(201); + _curvea0[553] = _3878; + uint16_t _3879 = (uint16_t)(201); + _curvea0[554] = _3879; + uint16_t _3880 = (uint16_t)(201); + _curvea0[555] = _3880; + uint16_t _3881 = (uint16_t)(201); + _curvea0[556] = _3881; + uint16_t _3882 = (uint16_t)(202); + _curvea0[557] = _3882; + uint16_t _3883 = (uint16_t)(202); + _curvea0[558] = _3883; + uint16_t _3884 = (uint16_t)(202); + _curvea0[559] = _3884; + uint16_t _3885 = (uint16_t)(202); + _curvea0[560] = _3885; + uint16_t _3886 = (uint16_t)(202); + _curvea0[561] = _3886; + uint16_t _3887 = (uint16_t)(202); + _curvea0[562] = _3887; + uint16_t _3888 = (uint16_t)(203); + _curvea0[563] = _3888; + uint16_t _3889 = (uint16_t)(203); + _curvea0[564] = _3889; + uint16_t _3890 = (uint16_t)(203); + _curvea0[565] = _3890; + uint16_t _3891 = (uint16_t)(203); + _curvea0[566] = _3891; + uint16_t _3892 = (uint16_t)(203); + _curvea0[567] = _3892; + uint16_t _3893 = (uint16_t)(203); + _curvea0[568] = _3893; + uint16_t _3894 = (uint16_t)(204); + _curvea0[569] = _3894; + uint16_t _3895 = (uint16_t)(204); + _curvea0[570] = _3895; + uint16_t _3896 = (uint16_t)(204); + _curvea0[571] = _3896; + uint16_t _3897 = (uint16_t)(204); + _curvea0[572] = _3897; + uint16_t _3898 = (uint16_t)(204); + _curvea0[573] = _3898; + uint16_t _3899 = (uint16_t)(204); + _curvea0[574] = _3899; + uint16_t _3900 = (uint16_t)(205); + _curvea0[575] = _3900; + uint16_t _3901 = (uint16_t)(205); + _curvea0[576] = _3901; + uint16_t _3902 = (uint16_t)(205); + _curvea0[577] = _3902; + uint16_t _3903 = (uint16_t)(205); + _curvea0[578] = _3903; + uint16_t _3904 = (uint16_t)(205); + _curvea0[579] = _3904; + uint16_t _3905 = (uint16_t)(205); + _curvea0[580] = _3905; + uint16_t _3906 = (uint16_t)(206); + _curvea0[581] = _3906; + uint16_t _3907 = (uint16_t)(206); + _curvea0[582] = _3907; + uint16_t _3908 = (uint16_t)(206); + _curvea0[583] = _3908; + uint16_t _3909 = (uint16_t)(206); + _curvea0[584] = _3909; + uint16_t _3910 = (uint16_t)(206); + _curvea0[585] = _3910; + uint16_t _3911 = (uint16_t)(206); + _curvea0[586] = _3911; + uint16_t _3912 = (uint16_t)(207); + _curvea0[587] = _3912; + uint16_t _3913 = (uint16_t)(207); + _curvea0[588] = _3913; + uint16_t _3914 = (uint16_t)(207); + _curvea0[589] = _3914; + uint16_t _3915 = (uint16_t)(207); + _curvea0[590] = _3915; + uint16_t _3916 = (uint16_t)(207); + _curvea0[591] = _3916; + uint16_t _3917 = (uint16_t)(207); + _curvea0[592] = _3917; + uint16_t _3918 = (uint16_t)(208); + _curvea0[593] = _3918; + uint16_t _3919 = (uint16_t)(208); + _curvea0[594] = _3919; + uint16_t _3920 = (uint16_t)(208); + _curvea0[595] = _3920; + uint16_t _3921 = (uint16_t)(208); + _curvea0[596] = _3921; + uint16_t _3922 = (uint16_t)(208); + _curvea0[597] = _3922; + uint16_t _3923 = (uint16_t)(208); + _curvea0[598] = _3923; + uint16_t _3924 = (uint16_t)(209); + _curvea0[599] = _3924; + uint16_t _3925 = (uint16_t)(209); + _curvea0[600] = _3925; + uint16_t _3926 = (uint16_t)(209); + _curvea0[601] = _3926; + uint16_t _3927 = (uint16_t)(209); + _curvea0[602] = _3927; + uint16_t _3928 = (uint16_t)(209); + _curvea0[603] = _3928; + uint16_t _3929 = (uint16_t)(209); + _curvea0[604] = _3929; + uint16_t _3930 = (uint16_t)(209); + _curvea0[605] = _3930; + uint16_t _3931 = (uint16_t)(210); + _curvea0[606] = _3931; + uint16_t _3932 = (uint16_t)(210); + _curvea0[607] = _3932; + uint16_t _3933 = (uint16_t)(210); + _curvea0[608] = _3933; + uint16_t _3934 = (uint16_t)(210); + _curvea0[609] = _3934; + uint16_t _3935 = (uint16_t)(210); + _curvea0[610] = _3935; + uint16_t _3936 = (uint16_t)(210); + _curvea0[611] = _3936; + uint16_t _3937 = (uint16_t)(211); + _curvea0[612] = _3937; + uint16_t _3938 = (uint16_t)(211); + _curvea0[613] = _3938; + uint16_t _3939 = (uint16_t)(211); + _curvea0[614] = _3939; + uint16_t _3940 = (uint16_t)(211); + _curvea0[615] = _3940; + uint16_t _3941 = (uint16_t)(211); + _curvea0[616] = _3941; + uint16_t _3942 = (uint16_t)(211); + _curvea0[617] = _3942; + uint16_t _3943 = (uint16_t)(211); + _curvea0[618] = _3943; + uint16_t _3944 = (uint16_t)(212); + _curvea0[619] = _3944; + uint16_t _3945 = (uint16_t)(212); + _curvea0[620] = _3945; + uint16_t _3946 = (uint16_t)(212); + _curvea0[621] = _3946; + uint16_t _3947 = (uint16_t)(212); + _curvea0[622] = _3947; + uint16_t _3948 = (uint16_t)(212); + _curvea0[623] = _3948; + uint16_t _3949 = (uint16_t)(212); + _curvea0[624] = _3949; + uint16_t _3950 = (uint16_t)(213); + _curvea0[625] = _3950; + uint16_t _3951 = (uint16_t)(213); + _curvea0[626] = _3951; + uint16_t _3952 = (uint16_t)(213); + _curvea0[627] = _3952; + uint16_t _3953 = (uint16_t)(213); + _curvea0[628] = _3953; + uint16_t _3954 = (uint16_t)(213); + _curvea0[629] = _3954; + uint16_t _3955 = (uint16_t)(213); + _curvea0[630] = _3955; + uint16_t _3956 = (uint16_t)(213); + _curvea0[631] = _3956; + uint16_t _3957 = (uint16_t)(214); + _curvea0[632] = _3957; + uint16_t _3958 = (uint16_t)(214); + _curvea0[633] = _3958; + uint16_t _3959 = (uint16_t)(214); + _curvea0[634] = _3959; + uint16_t _3960 = (uint16_t)(214); + _curvea0[635] = _3960; + uint16_t _3961 = (uint16_t)(214); + _curvea0[636] = _3961; + uint16_t _3962 = (uint16_t)(214); + _curvea0[637] = _3962; + uint16_t _3963 = (uint16_t)(214); + _curvea0[638] = _3963; + uint16_t _3964 = (uint16_t)(215); + _curvea0[639] = _3964; + uint16_t _3965 = (uint16_t)(215); + _curvea0[640] = _3965; + uint16_t _3966 = (uint16_t)(215); + _curvea0[641] = _3966; + uint16_t _3967 = (uint16_t)(215); + _curvea0[642] = _3967; + uint16_t _3968 = (uint16_t)(215); + _curvea0[643] = _3968; + uint16_t _3969 = (uint16_t)(215); + _curvea0[644] = _3969; + uint16_t _3970 = (uint16_t)(216); + _curvea0[645] = _3970; + uint16_t _3971 = (uint16_t)(216); + _curvea0[646] = _3971; + uint16_t _3972 = (uint16_t)(216); + _curvea0[647] = _3972; + uint16_t _3973 = (uint16_t)(216); + _curvea0[648] = _3973; + uint16_t _3974 = (uint16_t)(216); + _curvea0[649] = _3974; + uint16_t _3975 = (uint16_t)(216); + _curvea0[650] = _3975; + uint16_t _3976 = (uint16_t)(216); + _curvea0[651] = _3976; + uint16_t _3977 = (uint16_t)(217); + _curvea0[652] = _3977; + uint16_t _3978 = (uint16_t)(217); + _curvea0[653] = _3978; + uint16_t _3979 = (uint16_t)(217); + _curvea0[654] = _3979; + uint16_t _3980 = (uint16_t)(217); + _curvea0[655] = _3980; + uint16_t _3981 = (uint16_t)(217); + _curvea0[656] = _3981; + uint16_t _3982 = (uint16_t)(217); + _curvea0[657] = _3982; + uint16_t _3983 = (uint16_t)(217); + _curvea0[658] = _3983; + uint16_t _3984 = (uint16_t)(218); + _curvea0[659] = _3984; + uint16_t _3985 = (uint16_t)(218); + _curvea0[660] = _3985; + uint16_t _3986 = (uint16_t)(218); + _curvea0[661] = _3986; + uint16_t _3987 = (uint16_t)(218); + _curvea0[662] = _3987; + uint16_t _3988 = (uint16_t)(218); + _curvea0[663] = _3988; + uint16_t _3989 = (uint16_t)(218); + _curvea0[664] = _3989; + uint16_t _3990 = (uint16_t)(218); + _curvea0[665] = _3990; + uint16_t _3991 = (uint16_t)(219); + _curvea0[666] = _3991; + uint16_t _3992 = (uint16_t)(219); + _curvea0[667] = _3992; + uint16_t _3993 = (uint16_t)(219); + _curvea0[668] = _3993; + uint16_t _3994 = (uint16_t)(219); + _curvea0[669] = _3994; + uint16_t _3995 = (uint16_t)(219); + _curvea0[670] = _3995; + uint16_t _3996 = (uint16_t)(219); + _curvea0[671] = _3996; + uint16_t _3997 = (uint16_t)(219); + _curvea0[672] = _3997; + uint16_t _3998 = (uint16_t)(220); + _curvea0[673] = _3998; + uint16_t _3999 = (uint16_t)(220); + _curvea0[674] = _3999; + uint16_t _4000 = (uint16_t)(220); + _curvea0[675] = _4000; + uint16_t _4001 = (uint16_t)(220); + _curvea0[676] = _4001; + uint16_t _4002 = (uint16_t)(220); + _curvea0[677] = _4002; + uint16_t _4003 = (uint16_t)(220); + _curvea0[678] = _4003; + uint16_t _4004 = (uint16_t)(220); + _curvea0[679] = _4004; + uint16_t _4005 = (uint16_t)(220); + _curvea0[680] = _4005; + uint16_t _4006 = (uint16_t)(221); + _curvea0[681] = _4006; + uint16_t _4007 = (uint16_t)(221); + _curvea0[682] = _4007; + uint16_t _4008 = (uint16_t)(221); + _curvea0[683] = _4008; + uint16_t _4009 = (uint16_t)(221); + _curvea0[684] = _4009; + uint16_t _4010 = (uint16_t)(221); + _curvea0[685] = _4010; + uint16_t _4011 = (uint16_t)(221); + _curvea0[686] = _4011; + uint16_t _4012 = (uint16_t)(221); + _curvea0[687] = _4012; + uint16_t _4013 = (uint16_t)(222); + _curvea0[688] = _4013; + uint16_t _4014 = (uint16_t)(222); + _curvea0[689] = _4014; + uint16_t _4015 = (uint16_t)(222); + _curvea0[690] = _4015; + uint16_t _4016 = (uint16_t)(222); + _curvea0[691] = _4016; + uint16_t _4017 = (uint16_t)(222); + _curvea0[692] = _4017; + uint16_t _4018 = (uint16_t)(222); + _curvea0[693] = _4018; + uint16_t _4019 = (uint16_t)(222); + _curvea0[694] = _4019; + uint16_t _4020 = (uint16_t)(223); + _curvea0[695] = _4020; + uint16_t _4021 = (uint16_t)(223); + _curvea0[696] = _4021; + uint16_t _4022 = (uint16_t)(223); + _curvea0[697] = _4022; + uint16_t _4023 = (uint16_t)(223); + _curvea0[698] = _4023; + uint16_t _4024 = (uint16_t)(223); + _curvea0[699] = _4024; + uint16_t _4025 = (uint16_t)(223); + _curvea0[700] = _4025; + uint16_t _4026 = (uint16_t)(223); + _curvea0[701] = _4026; + uint16_t _4027 = (uint16_t)(223); + _curvea0[702] = _4027; + uint16_t _4028 = (uint16_t)(224); + _curvea0[703] = _4028; + uint16_t _4029 = (uint16_t)(224); + _curvea0[704] = _4029; + uint16_t _4030 = (uint16_t)(224); + _curvea0[705] = _4030; + uint16_t _4031 = (uint16_t)(224); + _curvea0[706] = _4031; + uint16_t _4032 = (uint16_t)(224); + _curvea0[707] = _4032; + uint16_t _4033 = (uint16_t)(224); + _curvea0[708] = _4033; + uint16_t _4034 = (uint16_t)(224); + _curvea0[709] = _4034; + uint16_t _4035 = (uint16_t)(224); + _curvea0[710] = _4035; + uint16_t _4036 = (uint16_t)(225); + _curvea0[711] = _4036; + uint16_t _4037 = (uint16_t)(225); + _curvea0[712] = _4037; + uint16_t _4038 = (uint16_t)(225); + _curvea0[713] = _4038; + uint16_t _4039 = (uint16_t)(225); + _curvea0[714] = _4039; + uint16_t _4040 = (uint16_t)(225); + _curvea0[715] = _4040; + uint16_t _4041 = (uint16_t)(225); + _curvea0[716] = _4041; + uint16_t _4042 = (uint16_t)(225); + _curvea0[717] = _4042; + uint16_t _4043 = (uint16_t)(226); + _curvea0[718] = _4043; + uint16_t _4044 = (uint16_t)(226); + _curvea0[719] = _4044; + uint16_t _4045 = (uint16_t)(226); + _curvea0[720] = _4045; + uint16_t _4046 = (uint16_t)(226); + _curvea0[721] = _4046; + uint16_t _4047 = (uint16_t)(226); + _curvea0[722] = _4047; + uint16_t _4048 = (uint16_t)(226); + _curvea0[723] = _4048; + uint16_t _4049 = (uint16_t)(226); + _curvea0[724] = _4049; + uint16_t _4050 = (uint16_t)(226); + _curvea0[725] = _4050; + uint16_t _4051 = (uint16_t)(227); + _curvea0[726] = _4051; + uint16_t _4052 = (uint16_t)(227); + _curvea0[727] = _4052; + uint16_t _4053 = (uint16_t)(227); + _curvea0[728] = _4053; + uint16_t _4054 = (uint16_t)(227); + _curvea0[729] = _4054; + uint16_t _4055 = (uint16_t)(227); + _curvea0[730] = _4055; + uint16_t _4056 = (uint16_t)(227); + _curvea0[731] = _4056; + uint16_t _4057 = (uint16_t)(227); + _curvea0[732] = _4057; + uint16_t _4058 = (uint16_t)(227); + _curvea0[733] = _4058; + uint16_t _4059 = (uint16_t)(228); + _curvea0[734] = _4059; + uint16_t _4060 = (uint16_t)(228); + _curvea0[735] = _4060; + uint16_t _4061 = (uint16_t)(228); + _curvea0[736] = _4061; + uint16_t _4062 = (uint16_t)(228); + _curvea0[737] = _4062; + uint16_t _4063 = (uint16_t)(228); + _curvea0[738] = _4063; + uint16_t _4064 = (uint16_t)(228); + _curvea0[739] = _4064; + uint16_t _4065 = (uint16_t)(228); + _curvea0[740] = _4065; + uint16_t _4066 = (uint16_t)(228); + _curvea0[741] = _4066; + uint16_t _4067 = (uint16_t)(228); + _curvea0[742] = _4067; + uint16_t _4068 = (uint16_t)(229); + _curvea0[743] = _4068; + uint16_t _4069 = (uint16_t)(229); + _curvea0[744] = _4069; + uint16_t _4070 = (uint16_t)(229); + _curvea0[745] = _4070; + uint16_t _4071 = (uint16_t)(229); + _curvea0[746] = _4071; + uint16_t _4072 = (uint16_t)(229); + _curvea0[747] = _4072; + uint16_t _4073 = (uint16_t)(229); + _curvea0[748] = _4073; + uint16_t _4074 = (uint16_t)(229); + _curvea0[749] = _4074; + uint16_t _4075 = (uint16_t)(229); + _curvea0[750] = _4075; + uint16_t _4076 = (uint16_t)(230); + _curvea0[751] = _4076; + uint16_t _4077 = (uint16_t)(230); + _curvea0[752] = _4077; + uint16_t _4078 = (uint16_t)(230); + _curvea0[753] = _4078; + uint16_t _4079 = (uint16_t)(230); + _curvea0[754] = _4079; + uint16_t _4080 = (uint16_t)(230); + _curvea0[755] = _4080; + uint16_t _4081 = (uint16_t)(230); + _curvea0[756] = _4081; + uint16_t _4082 = (uint16_t)(230); + _curvea0[757] = _4082; + uint16_t _4083 = (uint16_t)(230); + _curvea0[758] = _4083; + uint16_t _4084 = (uint16_t)(231); + _curvea0[759] = _4084; + uint16_t _4085 = (uint16_t)(231); + _curvea0[760] = _4085; + uint16_t _4086 = (uint16_t)(231); + _curvea0[761] = _4086; + uint16_t _4087 = (uint16_t)(231); + _curvea0[762] = _4087; + uint16_t _4088 = (uint16_t)(231); + _curvea0[763] = _4088; + uint16_t _4089 = (uint16_t)(231); + _curvea0[764] = _4089; + uint16_t _4090 = (uint16_t)(231); + _curvea0[765] = _4090; + uint16_t _4091 = (uint16_t)(231); + _curvea0[766] = _4091; + uint16_t _4092 = (uint16_t)(231); + _curvea0[767] = _4092; + uint16_t _4093 = (uint16_t)(232); + _curvea0[768] = _4093; + uint16_t _4094 = (uint16_t)(232); + _curvea0[769] = _4094; + uint16_t _4095 = (uint16_t)(232); + _curvea0[770] = _4095; + uint16_t _4096 = (uint16_t)(232); + _curvea0[771] = _4096; + uint16_t _4097 = (uint16_t)(232); + _curvea0[772] = _4097; + uint16_t _4098 = (uint16_t)(232); + _curvea0[773] = _4098; + uint16_t _4099 = (uint16_t)(232); + _curvea0[774] = _4099; + uint16_t _4100 = (uint16_t)(232); + _curvea0[775] = _4100; + uint16_t _4101 = (uint16_t)(233); + _curvea0[776] = _4101; + uint16_t _4102 = (uint16_t)(233); + _curvea0[777] = _4102; + uint16_t _4103 = (uint16_t)(233); + _curvea0[778] = _4103; + uint16_t _4104 = (uint16_t)(233); + _curvea0[779] = _4104; + uint16_t _4105 = (uint16_t)(233); + _curvea0[780] = _4105; + uint16_t _4106 = (uint16_t)(233); + _curvea0[781] = _4106; + uint16_t _4107 = (uint16_t)(233); + _curvea0[782] = _4107; + uint16_t _4108 = (uint16_t)(233); + _curvea0[783] = _4108; + uint16_t _4109 = (uint16_t)(233); + _curvea0[784] = _4109; + uint16_t _4110 = (uint16_t)(234); + _curvea0[785] = _4110; + uint16_t _4111 = (uint16_t)(234); + _curvea0[786] = _4111; + uint16_t _4112 = (uint16_t)(234); + _curvea0[787] = _4112; + uint16_t _4113 = (uint16_t)(234); + _curvea0[788] = _4113; + uint16_t _4114 = (uint16_t)(234); + _curvea0[789] = _4114; + uint16_t _4115 = (uint16_t)(234); + _curvea0[790] = _4115; + uint16_t _4116 = (uint16_t)(234); + _curvea0[791] = _4116; + uint16_t _4117 = (uint16_t)(234); + _curvea0[792] = _4117; + uint16_t _4118 = (uint16_t)(234); + _curvea0[793] = _4118; + uint16_t _4119 = (uint16_t)(235); + _curvea0[794] = _4119; + uint16_t _4120 = (uint16_t)(235); + _curvea0[795] = _4120; + uint16_t _4121 = (uint16_t)(235); + _curvea0[796] = _4121; + uint16_t _4122 = (uint16_t)(235); + _curvea0[797] = _4122; + uint16_t _4123 = (uint16_t)(235); + _curvea0[798] = _4123; + uint16_t _4124 = (uint16_t)(235); + _curvea0[799] = _4124; + uint16_t _4125 = (uint16_t)(235); + _curvea0[800] = _4125; + uint16_t _4126 = (uint16_t)(235); + _curvea0[801] = _4126; + uint16_t _4127 = (uint16_t)(235); + _curvea0[802] = _4127; + uint16_t _4128 = (uint16_t)(236); + _curvea0[803] = _4128; + uint16_t _4129 = (uint16_t)(236); + _curvea0[804] = _4129; + uint16_t _4130 = (uint16_t)(236); + _curvea0[805] = _4130; + uint16_t _4131 = (uint16_t)(236); + _curvea0[806] = _4131; + uint16_t _4132 = (uint16_t)(236); + _curvea0[807] = _4132; + uint16_t _4133 = (uint16_t)(236); + _curvea0[808] = _4133; + uint16_t _4134 = (uint16_t)(236); + _curvea0[809] = _4134; + uint16_t _4135 = (uint16_t)(236); + _curvea0[810] = _4135; + uint16_t _4136 = (uint16_t)(236); + _curvea0[811] = _4136; + uint16_t _4137 = (uint16_t)(237); + _curvea0[812] = _4137; + uint16_t _4138 = (uint16_t)(237); + _curvea0[813] = _4138; + uint16_t _4139 = (uint16_t)(237); + _curvea0[814] = _4139; + uint16_t _4140 = (uint16_t)(237); + _curvea0[815] = _4140; + uint16_t _4141 = (uint16_t)(237); + _curvea0[816] = _4141; + uint16_t _4142 = (uint16_t)(237); + _curvea0[817] = _4142; + uint16_t _4143 = (uint16_t)(237); + _curvea0[818] = _4143; + uint16_t _4144 = (uint16_t)(237); + _curvea0[819] = _4144; + uint16_t _4145 = (uint16_t)(237); + _curvea0[820] = _4145; + uint16_t _4146 = (uint16_t)(237); + _curvea0[821] = _4146; + uint16_t _4147 = (uint16_t)(238); + _curvea0[822] = _4147; + uint16_t _4148 = (uint16_t)(238); + _curvea0[823] = _4148; + uint16_t _4149 = (uint16_t)(238); + _curvea0[824] = _4149; + uint16_t _4150 = (uint16_t)(238); + _curvea0[825] = _4150; + uint16_t _4151 = (uint16_t)(238); + _curvea0[826] = _4151; + uint16_t _4152 = (uint16_t)(238); + _curvea0[827] = _4152; + uint16_t _4153 = (uint16_t)(238); + _curvea0[828] = _4153; + uint16_t _4154 = (uint16_t)(238); + _curvea0[829] = _4154; + uint16_t _4155 = (uint16_t)(238); + _curvea0[830] = _4155; + uint16_t _4156 = (uint16_t)(239); + _curvea0[831] = _4156; + uint16_t _4157 = (uint16_t)(239); + _curvea0[832] = _4157; + uint16_t _4158 = (uint16_t)(239); + _curvea0[833] = _4158; + uint16_t _4159 = (uint16_t)(239); + _curvea0[834] = _4159; + uint16_t _4160 = (uint16_t)(239); + _curvea0[835] = _4160; + uint16_t _4161 = (uint16_t)(239); + _curvea0[836] = _4161; + uint16_t _4162 = (uint16_t)(239); + _curvea0[837] = _4162; + uint16_t _4163 = (uint16_t)(239); + _curvea0[838] = _4163; + uint16_t _4164 = (uint16_t)(239); + _curvea0[839] = _4164; + uint16_t _4165 = (uint16_t)(239); + _curvea0[840] = _4165; + uint16_t _4166 = (uint16_t)(240); + _curvea0[841] = _4166; + uint16_t _4167 = (uint16_t)(240); + _curvea0[842] = _4167; + uint16_t _4168 = (uint16_t)(240); + _curvea0[843] = _4168; + uint16_t _4169 = (uint16_t)(240); + _curvea0[844] = _4169; + uint16_t _4170 = (uint16_t)(240); + _curvea0[845] = _4170; + uint16_t _4171 = (uint16_t)(240); + _curvea0[846] = _4171; + uint16_t _4172 = (uint16_t)(240); + _curvea0[847] = _4172; + uint16_t _4173 = (uint16_t)(240); + _curvea0[848] = _4173; + uint16_t _4174 = (uint16_t)(240); + _curvea0[849] = _4174; + uint16_t _4175 = (uint16_t)(240); + _curvea0[850] = _4175; + uint16_t _4176 = (uint16_t)(241); + _curvea0[851] = _4176; + uint16_t _4177 = (uint16_t)(241); + _curvea0[852] = _4177; + uint16_t _4178 = (uint16_t)(241); + _curvea0[853] = _4178; + uint16_t _4179 = (uint16_t)(241); + _curvea0[854] = _4179; + uint16_t _4180 = (uint16_t)(241); + _curvea0[855] = _4180; + uint16_t _4181 = (uint16_t)(241); + _curvea0[856] = _4181; + uint16_t _4182 = (uint16_t)(241); + _curvea0[857] = _4182; + uint16_t _4183 = (uint16_t)(241); + _curvea0[858] = _4183; + uint16_t _4184 = (uint16_t)(241); + _curvea0[859] = _4184; + uint16_t _4185 = (uint16_t)(241); + _curvea0[860] = _4185; + uint16_t _4186 = (uint16_t)(242); + _curvea0[861] = _4186; + uint16_t _4187 = (uint16_t)(242); + _curvea0[862] = _4187; + uint16_t _4188 = (uint16_t)(242); + _curvea0[863] = _4188; + uint16_t _4189 = (uint16_t)(242); + _curvea0[864] = _4189; + uint16_t _4190 = (uint16_t)(242); + _curvea0[865] = _4190; + uint16_t _4191 = (uint16_t)(242); + _curvea0[866] = _4191; + uint16_t _4192 = (uint16_t)(242); + _curvea0[867] = _4192; + uint16_t _4193 = (uint16_t)(242); + _curvea0[868] = _4193; + uint16_t _4194 = (uint16_t)(242); + _curvea0[869] = _4194; + uint16_t _4195 = (uint16_t)(242); + _curvea0[870] = _4195; + uint16_t _4196 = (uint16_t)(243); + _curvea0[871] = _4196; + uint16_t _4197 = (uint16_t)(243); + _curvea0[872] = _4197; + uint16_t _4198 = (uint16_t)(243); + _curvea0[873] = _4198; + uint16_t _4199 = (uint16_t)(243); + _curvea0[874] = _4199; + uint16_t _4200 = (uint16_t)(243); + _curvea0[875] = _4200; + uint16_t _4201 = (uint16_t)(243); + _curvea0[876] = _4201; + uint16_t _4202 = (uint16_t)(243); + _curvea0[877] = _4202; + uint16_t _4203 = (uint16_t)(243); + _curvea0[878] = _4203; + uint16_t _4204 = (uint16_t)(243); + _curvea0[879] = _4204; + uint16_t _4205 = (uint16_t)(243); + _curvea0[880] = _4205; + uint16_t _4206 = (uint16_t)(244); + _curvea0[881] = _4206; + uint16_t _4207 = (uint16_t)(244); + _curvea0[882] = _4207; + uint16_t _4208 = (uint16_t)(244); + _curvea0[883] = _4208; + uint16_t _4209 = (uint16_t)(244); + _curvea0[884] = _4209; + uint16_t _4210 = (uint16_t)(244); + _curvea0[885] = _4210; + uint16_t _4211 = (uint16_t)(244); + _curvea0[886] = _4211; + uint16_t _4212 = (uint16_t)(244); + _curvea0[887] = _4212; + uint16_t _4213 = (uint16_t)(244); + _curvea0[888] = _4213; + uint16_t _4214 = (uint16_t)(244); + _curvea0[889] = _4214; + uint16_t _4215 = (uint16_t)(244); + _curvea0[890] = _4215; + uint16_t _4216 = (uint16_t)(244); + _curvea0[891] = _4216; + uint16_t _4217 = (uint16_t)(245); + _curvea0[892] = _4217; + uint16_t _4218 = (uint16_t)(245); + _curvea0[893] = _4218; + uint16_t _4219 = (uint16_t)(245); + _curvea0[894] = _4219; + uint16_t _4220 = (uint16_t)(245); + _curvea0[895] = _4220; + uint16_t _4221 = (uint16_t)(245); + _curvea0[896] = _4221; + uint16_t _4222 = (uint16_t)(245); + _curvea0[897] = _4222; + uint16_t _4223 = (uint16_t)(245); + _curvea0[898] = _4223; + uint16_t _4224 = (uint16_t)(245); + _curvea0[899] = _4224; + uint16_t _4225 = (uint16_t)(245); + _curvea0[900] = _4225; + uint16_t _4226 = (uint16_t)(245); + _curvea0[901] = _4226; + uint16_t _4227 = (uint16_t)(245); + _curvea0[902] = _4227; + uint16_t _4228 = (uint16_t)(246); + _curvea0[903] = _4228; + uint16_t _4229 = (uint16_t)(246); + _curvea0[904] = _4229; + uint16_t _4230 = (uint16_t)(246); + _curvea0[905] = _4230; + uint16_t _4231 = (uint16_t)(246); + _curvea0[906] = _4231; + uint16_t _4232 = (uint16_t)(246); + _curvea0[907] = _4232; + uint16_t _4233 = (uint16_t)(246); + _curvea0[908] = _4233; + uint16_t _4234 = (uint16_t)(246); + _curvea0[909] = _4234; + uint16_t _4235 = (uint16_t)(246); + _curvea0[910] = _4235; + uint16_t _4236 = (uint16_t)(246); + _curvea0[911] = _4236; + uint16_t _4237 = (uint16_t)(246); + _curvea0[912] = _4237; + uint16_t _4238 = (uint16_t)(246); + _curvea0[913] = _4238; + uint16_t _4239 = (uint16_t)(247); + _curvea0[914] = _4239; + uint16_t _4240 = (uint16_t)(247); + _curvea0[915] = _4240; + uint16_t _4241 = (uint16_t)(247); + _curvea0[916] = _4241; + uint16_t _4242 = (uint16_t)(247); + _curvea0[917] = _4242; + uint16_t _4243 = (uint16_t)(247); + _curvea0[918] = _4243; + uint16_t _4244 = (uint16_t)(247); + _curvea0[919] = _4244; + uint16_t _4245 = (uint16_t)(247); + _curvea0[920] = _4245; + uint16_t _4246 = (uint16_t)(247); + _curvea0[921] = _4246; + uint16_t _4247 = (uint16_t)(247); + _curvea0[922] = _4247; + uint16_t _4248 = (uint16_t)(247); + _curvea0[923] = _4248; + uint16_t _4249 = (uint16_t)(247); + _curvea0[924] = _4249; + uint16_t _4250 = (uint16_t)(248); + _curvea0[925] = _4250; + uint16_t _4251 = (uint16_t)(248); + _curvea0[926] = _4251; + uint16_t _4252 = (uint16_t)(248); + _curvea0[927] = _4252; + uint16_t _4253 = (uint16_t)(248); + _curvea0[928] = _4253; + uint16_t _4254 = (uint16_t)(248); + _curvea0[929] = _4254; + uint16_t _4255 = (uint16_t)(248); + _curvea0[930] = _4255; + uint16_t _4256 = (uint16_t)(248); + _curvea0[931] = _4256; + uint16_t _4257 = (uint16_t)(248); + _curvea0[932] = _4257; + uint16_t _4258 = (uint16_t)(248); + _curvea0[933] = _4258; + uint16_t _4259 = (uint16_t)(248); + _curvea0[934] = _4259; + uint16_t _4260 = (uint16_t)(248); + _curvea0[935] = _4260; + uint16_t _4261 = (uint16_t)(249); + _curvea0[936] = _4261; + uint16_t _4262 = (uint16_t)(249); + _curvea0[937] = _4262; + uint16_t _4263 = (uint16_t)(249); + _curvea0[938] = _4263; + uint16_t _4264 = (uint16_t)(249); + _curvea0[939] = _4264; + uint16_t _4265 = (uint16_t)(249); + _curvea0[940] = _4265; + uint16_t _4266 = (uint16_t)(249); + _curvea0[941] = _4266; + uint16_t _4267 = (uint16_t)(249); + _curvea0[942] = _4267; + uint16_t _4268 = (uint16_t)(249); + _curvea0[943] = _4268; + uint16_t _4269 = (uint16_t)(249); + _curvea0[944] = _4269; + uint16_t _4270 = (uint16_t)(249); + _curvea0[945] = _4270; + uint16_t _4271 = (uint16_t)(249); + _curvea0[946] = _4271; + uint16_t _4272 = (uint16_t)(249); + _curvea0[947] = _4272; + uint16_t _4273 = (uint16_t)(250); + _curvea0[948] = _4273; + uint16_t _4274 = (uint16_t)(250); + _curvea0[949] = _4274; + uint16_t _4275 = (uint16_t)(250); + _curvea0[950] = _4275; + uint16_t _4276 = (uint16_t)(250); + _curvea0[951] = _4276; + uint16_t _4277 = (uint16_t)(250); + _curvea0[952] = _4277; + uint16_t _4278 = (uint16_t)(250); + _curvea0[953] = _4278; + uint16_t _4279 = (uint16_t)(250); + _curvea0[954] = _4279; + uint16_t _4280 = (uint16_t)(250); + _curvea0[955] = _4280; + uint16_t _4281 = (uint16_t)(250); + _curvea0[956] = _4281; + uint16_t _4282 = (uint16_t)(250); + _curvea0[957] = _4282; + uint16_t _4283 = (uint16_t)(250); + _curvea0[958] = _4283; + uint16_t _4284 = (uint16_t)(250); + _curvea0[959] = _4284; + uint16_t _4285 = (uint16_t)(251); + _curvea0[960] = _4285; + uint16_t _4286 = (uint16_t)(251); + _curvea0[961] = _4286; + uint16_t _4287 = (uint16_t)(251); + _curvea0[962] = _4287; + uint16_t _4288 = (uint16_t)(251); + _curvea0[963] = _4288; + uint16_t _4289 = (uint16_t)(251); + _curvea0[964] = _4289; + uint16_t _4290 = (uint16_t)(251); + _curvea0[965] = _4290; + uint16_t _4291 = (uint16_t)(251); + _curvea0[966] = _4291; + uint16_t _4292 = (uint16_t)(251); + _curvea0[967] = _4292; + uint16_t _4293 = (uint16_t)(251); + _curvea0[968] = _4293; + uint16_t _4294 = (uint16_t)(251); + _curvea0[969] = _4294; + uint16_t _4295 = (uint16_t)(251); + _curvea0[970] = _4295; + uint16_t _4296 = (uint16_t)(251); + _curvea0[971] = _4296; + uint16_t _4297 = (uint16_t)(252); + _curvea0[972] = _4297; + uint16_t _4298 = (uint16_t)(252); + _curvea0[973] = _4298; + uint16_t _4299 = (uint16_t)(252); + _curvea0[974] = _4299; + uint16_t _4300 = (uint16_t)(252); + _curvea0[975] = _4300; + uint16_t _4301 = (uint16_t)(252); + _curvea0[976] = _4301; + uint16_t _4302 = (uint16_t)(252); + _curvea0[977] = _4302; + uint16_t _4303 = (uint16_t)(252); + _curvea0[978] = _4303; + uint16_t _4304 = (uint16_t)(252); + _curvea0[979] = _4304; + uint16_t _4305 = (uint16_t)(252); + _curvea0[980] = _4305; + uint16_t _4306 = (uint16_t)(252); + _curvea0[981] = _4306; + uint16_t _4307 = (uint16_t)(252); + _curvea0[982] = _4307; + uint16_t _4308 = (uint16_t)(252); + _curvea0[983] = _4308; + uint16_t _4309 = (uint16_t)(252); + _curvea0[984] = _4309; + uint16_t _4310 = (uint16_t)(253); + _curvea0[985] = _4310; + uint16_t _4311 = (uint16_t)(253); + _curvea0[986] = _4311; + uint16_t _4312 = (uint16_t)(253); + _curvea0[987] = _4312; + uint16_t _4313 = (uint16_t)(253); + _curvea0[988] = _4313; + uint16_t _4314 = (uint16_t)(253); + _curvea0[989] = _4314; + uint16_t _4315 = (uint16_t)(253); + _curvea0[990] = _4315; + uint16_t _4316 = (uint16_t)(253); + _curvea0[991] = _4316; + uint16_t _4317 = (uint16_t)(253); + _curvea0[992] = _4317; + uint16_t _4318 = (uint16_t)(253); + _curvea0[993] = _4318; + uint16_t _4319 = (uint16_t)(253); + _curvea0[994] = _4319; + uint16_t _4320 = (uint16_t)(253); + _curvea0[995] = _4320; + uint16_t _4321 = (uint16_t)(253); + _curvea0[996] = _4321; + uint16_t _4322 = (uint16_t)(253); + _curvea0[997] = _4322; + uint16_t _4323 = (uint16_t)(254); + _curvea0[998] = _4323; + uint16_t _4324 = (uint16_t)(254); + _curvea0[999] = _4324; + uint16_t _4325 = (uint16_t)(254); + _curvea0[1000] = _4325; + uint16_t _4326 = (uint16_t)(254); + _curvea0[1001] = _4326; + uint16_t _4327 = (uint16_t)(254); + _curvea0[1002] = _4327; + uint16_t _4328 = (uint16_t)(254); + _curvea0[1003] = _4328; + uint16_t _4329 = (uint16_t)(254); + _curvea0[1004] = _4329; + uint16_t _4330 = (uint16_t)(254); + _curvea0[1005] = _4330; + uint16_t _4331 = (uint16_t)(254); + _curvea0[1006] = _4331; + uint16_t _4332 = (uint16_t)(254); + _curvea0[1007] = _4332; + uint16_t _4333 = (uint16_t)(254); + _curvea0[1008] = _4333; + uint16_t _4334 = (uint16_t)(254); + _curvea0[1009] = _4334; + uint16_t _4335 = (uint16_t)(254); + _curvea0[1010] = _4335; + uint16_t _4336 = (uint16_t)(255); + _curvea0[1011] = _4336; + uint16_t _4337 = (uint16_t)(255); + _curvea0[1012] = _4337; + uint16_t _4338 = (uint16_t)(255); + _curvea0[1013] = _4338; + uint16_t _4339 = (uint16_t)(255); + _curvea0[1014] = _4339; + uint16_t _4340 = (uint16_t)(255); + _curvea0[1015] = _4340; + uint16_t _4341 = (uint16_t)(255); + _curvea0[1016] = _4341; + uint16_t _4342 = (uint16_t)(255); + _curvea0[1017] = _4342; + uint16_t _4343 = (uint16_t)(255); + _curvea0[1018] = _4343; + uint16_t _4344 = (uint16_t)(255); + _curvea0[1019] = _4344; + uint16_t _4345 = (uint16_t)(255); + _curvea0[1020] = _4345; + uint16_t _4346 = (uint16_t)(255); + _curvea0[1021] = _4346; + uint16_t _4347 = (uint16_t)(255); + _curvea0[1022] = _4347; + uint16_t _4348 = (uint16_t)(255); + _curvea0[1023] = _4348; + + int16_t _4349 = (int16_t)(1023); + int16_t _4350 = min(_corrected_stencil_2, _4349); + int16_t _4351 = (int16_t)(0); + int16_t _4352 = max(_4350, _4351); + uint16_t _4353 = (uint16_t)(_4352); + int32_t _4354 = (int32_t)(_4353); + uint16_t _4355 = ((const uint16_t *)_curvea0)[_4354]; + return _4355; +} + +//store is: curved.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_2(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_3 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _4371 = (uint16_t)(0); + _curvea0[0] = _4371; + uint16_t _4372 = (uint16_t)(4); + _curvea0[1] = _4372; + uint16_t _4373 = (uint16_t)(7); + _curvea0[2] = _4373; + uint16_t _4374 = (uint16_t)(8); + _curvea0[3] = _4374; + uint16_t _4375 = (uint16_t)(10); + _curvea0[4] = _4375; + uint16_t _4376 = (uint16_t)(11); + _curvea0[5] = _4376; + uint16_t _4377 = (uint16_t)(12); + _curvea0[6] = _4377; + uint16_t _4378 = (uint16_t)(13); + _curvea0[7] = _4378; + uint16_t _4379 = (uint16_t)(14); + _curvea0[8] = _4379; + uint16_t _4380 = (uint16_t)(15); + _curvea0[9] = _4380; + uint16_t _4381 = (uint16_t)(16); + _curvea0[10] = _4381; + uint16_t _4382 = (uint16_t)(17); + _curvea0[11] = _4382; + uint16_t _4383 = (uint16_t)(18); + _curvea0[12] = _4383; + uint16_t _4384 = (uint16_t)(19); + _curvea0[13] = _4384; + uint16_t _4385 = (uint16_t)(20); + _curvea0[14] = _4385; + uint16_t _4386 = (uint16_t)(21); + _curvea0[15] = _4386; + uint16_t _4387 = (uint16_t)(22); + _curvea0[16] = _4387; + uint16_t _4388 = (uint16_t)(22); + _curvea0[17] = _4388; + uint16_t _4389 = (uint16_t)(23); + _curvea0[18] = _4389; + uint16_t _4390 = (uint16_t)(24); + _curvea0[19] = _4390; + uint16_t _4391 = (uint16_t)(25); + _curvea0[20] = _4391; + uint16_t _4392 = (uint16_t)(25); + _curvea0[21] = _4392; + uint16_t _4393 = (uint16_t)(26); + _curvea0[22] = _4393; + uint16_t _4394 = (uint16_t)(27); + _curvea0[23] = _4394; + uint16_t _4395 = (uint16_t)(27); + _curvea0[24] = _4395; + uint16_t _4396 = (uint16_t)(28); + _curvea0[25] = _4396; + uint16_t _4397 = (uint16_t)(29); + _curvea0[26] = _4397; + uint16_t _4398 = (uint16_t)(29); + _curvea0[27] = _4398; + uint16_t _4399 = (uint16_t)(30); + _curvea0[28] = _4399; + uint16_t _4400 = (uint16_t)(31); + _curvea0[29] = _4400; + uint16_t _4401 = (uint16_t)(31); + _curvea0[30] = _4401; + uint16_t _4402 = (uint16_t)(32); + _curvea0[31] = _4402; + uint16_t _4403 = (uint16_t)(33); + _curvea0[32] = _4403; + uint16_t _4404 = (uint16_t)(33); + _curvea0[33] = _4404; + uint16_t _4405 = (uint16_t)(34); + _curvea0[34] = _4405; + uint16_t _4406 = (uint16_t)(34); + _curvea0[35] = _4406; + uint16_t _4407 = (uint16_t)(35); + _curvea0[36] = _4407; + uint16_t _4408 = (uint16_t)(36); + _curvea0[37] = _4408; + uint16_t _4409 = (uint16_t)(36); + _curvea0[38] = _4409; + uint16_t _4410 = (uint16_t)(37); + _curvea0[39] = _4410; + uint16_t _4411 = (uint16_t)(37); + _curvea0[40] = _4411; + uint16_t _4412 = (uint16_t)(38); + _curvea0[41] = _4412; + uint16_t _4413 = (uint16_t)(39); + _curvea0[42] = _4413; + uint16_t _4414 = (uint16_t)(39); + _curvea0[43] = _4414; + uint16_t _4415 = (uint16_t)(40); + _curvea0[44] = _4415; + uint16_t _4416 = (uint16_t)(40); + _curvea0[45] = _4416; + uint16_t _4417 = (uint16_t)(41); + _curvea0[46] = _4417; + uint16_t _4418 = (uint16_t)(41); + _curvea0[47] = _4418; + uint16_t _4419 = (uint16_t)(42); + _curvea0[48] = _4419; + uint16_t _4420 = (uint16_t)(42); + _curvea0[49] = _4420; + uint16_t _4421 = (uint16_t)(43); + _curvea0[50] = _4421; + uint16_t _4422 = (uint16_t)(44); + _curvea0[51] = _4422; + uint16_t _4423 = (uint16_t)(44); + _curvea0[52] = _4423; + uint16_t _4424 = (uint16_t)(45); + _curvea0[53] = _4424; + uint16_t _4425 = (uint16_t)(45); + _curvea0[54] = _4425; + uint16_t _4426 = (uint16_t)(46); + _curvea0[55] = _4426; + uint16_t _4427 = (uint16_t)(46); + _curvea0[56] = _4427; + uint16_t _4428 = (uint16_t)(47); + _curvea0[57] = _4428; + uint16_t _4429 = (uint16_t)(47); + _curvea0[58] = _4429; + uint16_t _4430 = (uint16_t)(48); + _curvea0[59] = _4430; + uint16_t _4431 = (uint16_t)(48); + _curvea0[60] = _4431; + uint16_t _4432 = (uint16_t)(49); + _curvea0[61] = _4432; + uint16_t _4433 = (uint16_t)(49); + _curvea0[62] = _4433; + uint16_t _4434 = (uint16_t)(50); + _curvea0[63] = _4434; + uint16_t _4435 = (uint16_t)(50); + _curvea0[64] = _4435; + uint16_t _4436 = (uint16_t)(51); + _curvea0[65] = _4436; + uint16_t _4437 = (uint16_t)(51); + _curvea0[66] = _4437; + uint16_t _4438 = (uint16_t)(52); + _curvea0[67] = _4438; + uint16_t _4439 = (uint16_t)(52); + _curvea0[68] = _4439; + uint16_t _4440 = (uint16_t)(53); + _curvea0[69] = _4440; + uint16_t _4441 = (uint16_t)(53); + _curvea0[70] = _4441; + uint16_t _4442 = (uint16_t)(54); + _curvea0[71] = _4442; + uint16_t _4443 = (uint16_t)(54); + _curvea0[72] = _4443; + uint16_t _4444 = (uint16_t)(55); + _curvea0[73] = _4444; + uint16_t _4445 = (uint16_t)(55); + _curvea0[74] = _4445; + uint16_t _4446 = (uint16_t)(56); + _curvea0[75] = _4446; + uint16_t _4447 = (uint16_t)(56); + _curvea0[76] = _4447; + uint16_t _4448 = (uint16_t)(57); + _curvea0[77] = _4448; + uint16_t _4449 = (uint16_t)(57); + _curvea0[78] = _4449; + uint16_t _4450 = (uint16_t)(58); + _curvea0[79] = _4450; + uint16_t _4451 = (uint16_t)(58); + _curvea0[80] = _4451; + uint16_t _4452 = (uint16_t)(58); + _curvea0[81] = _4452; + uint16_t _4453 = (uint16_t)(59); + _curvea0[82] = _4453; + uint16_t _4454 = (uint16_t)(59); + _curvea0[83] = _4454; + uint16_t _4455 = (uint16_t)(60); + _curvea0[84] = _4455; + uint16_t _4456 = (uint16_t)(60); + _curvea0[85] = _4456; + uint16_t _4457 = (uint16_t)(61); + _curvea0[86] = _4457; + uint16_t _4458 = (uint16_t)(61); + _curvea0[87] = _4458; + uint16_t _4459 = (uint16_t)(62); + _curvea0[88] = _4459; + uint16_t _4460 = (uint16_t)(62); + _curvea0[89] = _4460; + uint16_t _4461 = (uint16_t)(63); + _curvea0[90] = _4461; + uint16_t _4462 = (uint16_t)(63); + _curvea0[91] = _4462; + uint16_t _4463 = (uint16_t)(64); + _curvea0[92] = _4463; + uint16_t _4464 = (uint16_t)(64); + _curvea0[93] = _4464; + uint16_t _4465 = (uint16_t)(64); + _curvea0[94] = _4465; + uint16_t _4466 = (uint16_t)(65); + _curvea0[95] = _4466; + uint16_t _4467 = (uint16_t)(65); + _curvea0[96] = _4467; + uint16_t _4468 = (uint16_t)(66); + _curvea0[97] = _4468; + uint16_t _4469 = (uint16_t)(66); + _curvea0[98] = _4469; + uint16_t _4470 = (uint16_t)(67); + _curvea0[99] = _4470; + uint16_t _4471 = (uint16_t)(67); + _curvea0[100] = _4471; + uint16_t _4472 = (uint16_t)(68); + _curvea0[101] = _4472; + uint16_t _4473 = (uint16_t)(68); + _curvea0[102] = _4473; + uint16_t _4474 = (uint16_t)(68); + _curvea0[103] = _4474; + uint16_t _4475 = (uint16_t)(69); + _curvea0[104] = _4475; + uint16_t _4476 = (uint16_t)(69); + _curvea0[105] = _4476; + uint16_t _4477 = (uint16_t)(70); + _curvea0[106] = _4477; + uint16_t _4478 = (uint16_t)(70); + _curvea0[107] = _4478; + uint16_t _4479 = (uint16_t)(71); + _curvea0[108] = _4479; + uint16_t _4480 = (uint16_t)(71); + _curvea0[109] = _4480; + uint16_t _4481 = (uint16_t)(71); + _curvea0[110] = _4481; + uint16_t _4482 = (uint16_t)(72); + _curvea0[111] = _4482; + uint16_t _4483 = (uint16_t)(72); + _curvea0[112] = _4483; + uint16_t _4484 = (uint16_t)(73); + _curvea0[113] = _4484; + uint16_t _4485 = (uint16_t)(73); + _curvea0[114] = _4485; + uint16_t _4486 = (uint16_t)(74); + _curvea0[115] = _4486; + uint16_t _4487 = (uint16_t)(74); + _curvea0[116] = _4487; + uint16_t _4488 = (uint16_t)(74); + _curvea0[117] = _4488; + uint16_t _4489 = (uint16_t)(75); + _curvea0[118] = _4489; + uint16_t _4490 = (uint16_t)(75); + _curvea0[119] = _4490; + uint16_t _4491 = (uint16_t)(76); + _curvea0[120] = _4491; + uint16_t _4492 = (uint16_t)(76); + _curvea0[121] = _4492; + uint16_t _4493 = (uint16_t)(77); + _curvea0[122] = _4493; + uint16_t _4494 = (uint16_t)(77); + _curvea0[123] = _4494; + uint16_t _4495 = (uint16_t)(77); + _curvea0[124] = _4495; + uint16_t _4496 = (uint16_t)(78); + _curvea0[125] = _4496; + uint16_t _4497 = (uint16_t)(78); + _curvea0[126] = _4497; + uint16_t _4498 = (uint16_t)(79); + _curvea0[127] = _4498; + uint16_t _4499 = (uint16_t)(79); + _curvea0[128] = _4499; + uint16_t _4500 = (uint16_t)(79); + _curvea0[129] = _4500; + uint16_t _4501 = (uint16_t)(80); + _curvea0[130] = _4501; + uint16_t _4502 = (uint16_t)(80); + _curvea0[131] = _4502; + uint16_t _4503 = (uint16_t)(81); + _curvea0[132] = _4503; + uint16_t _4504 = (uint16_t)(81); + _curvea0[133] = _4504; + uint16_t _4505 = (uint16_t)(82); + _curvea0[134] = _4505; + uint16_t _4506 = (uint16_t)(82); + _curvea0[135] = _4506; + uint16_t _4507 = (uint16_t)(82); + _curvea0[136] = _4507; + uint16_t _4508 = (uint16_t)(83); + _curvea0[137] = _4508; + uint16_t _4509 = (uint16_t)(83); + _curvea0[138] = _4509; + uint16_t _4510 = (uint16_t)(84); + _curvea0[139] = _4510; + uint16_t _4511 = (uint16_t)(84); + _curvea0[140] = _4511; + uint16_t _4512 = (uint16_t)(84); + _curvea0[141] = _4512; + uint16_t _4513 = (uint16_t)(85); + _curvea0[142] = _4513; + uint16_t _4514 = (uint16_t)(85); + _curvea0[143] = _4514; + uint16_t _4515 = (uint16_t)(86); + _curvea0[144] = _4515; + uint16_t _4516 = (uint16_t)(86); + _curvea0[145] = _4516; + uint16_t _4517 = (uint16_t)(86); + _curvea0[146] = _4517; + uint16_t _4518 = (uint16_t)(87); + _curvea0[147] = _4518; + uint16_t _4519 = (uint16_t)(87); + _curvea0[148] = _4519; + uint16_t _4520 = (uint16_t)(88); + _curvea0[149] = _4520; + uint16_t _4521 = (uint16_t)(88); + _curvea0[150] = _4521; + uint16_t _4522 = (uint16_t)(88); + _curvea0[151] = _4522; + uint16_t _4523 = (uint16_t)(89); + _curvea0[152] = _4523; + uint16_t _4524 = (uint16_t)(89); + _curvea0[153] = _4524; + uint16_t _4525 = (uint16_t)(90); + _curvea0[154] = _4525; + uint16_t _4526 = (uint16_t)(90); + _curvea0[155] = _4526; + uint16_t _4527 = (uint16_t)(90); + _curvea0[156] = _4527; + uint16_t _4528 = (uint16_t)(91); + _curvea0[157] = _4528; + uint16_t _4529 = (uint16_t)(91); + _curvea0[158] = _4529; + uint16_t _4530 = (uint16_t)(92); + _curvea0[159] = _4530; + uint16_t _4531 = (uint16_t)(92); + _curvea0[160] = _4531; + uint16_t _4532 = (uint16_t)(92); + _curvea0[161] = _4532; + uint16_t _4533 = (uint16_t)(93); + _curvea0[162] = _4533; + uint16_t _4534 = (uint16_t)(93); + _curvea0[163] = _4534; + uint16_t _4535 = (uint16_t)(93); + _curvea0[164] = _4535; + uint16_t _4536 = (uint16_t)(94); + _curvea0[165] = _4536; + uint16_t _4537 = (uint16_t)(94); + _curvea0[166] = _4537; + uint16_t _4538 = (uint16_t)(95); + _curvea0[167] = _4538; + uint16_t _4539 = (uint16_t)(95); + _curvea0[168] = _4539; + uint16_t _4540 = (uint16_t)(95); + _curvea0[169] = _4540; + uint16_t _4541 = (uint16_t)(96); + _curvea0[170] = _4541; + uint16_t _4542 = (uint16_t)(96); + _curvea0[171] = _4542; + uint16_t _4543 = (uint16_t)(97); + _curvea0[172] = _4543; + uint16_t _4544 = (uint16_t)(97); + _curvea0[173] = _4544; + uint16_t _4545 = (uint16_t)(97); + _curvea0[174] = _4545; + uint16_t _4546 = (uint16_t)(98); + _curvea0[175] = _4546; + uint16_t _4547 = (uint16_t)(98); + _curvea0[176] = _4547; + uint16_t _4548 = (uint16_t)(99); + _curvea0[177] = _4548; + uint16_t _4549 = (uint16_t)(99); + _curvea0[178] = _4549; + uint16_t _4550 = (uint16_t)(99); + _curvea0[179] = _4550; + uint16_t _4551 = (uint16_t)(100); + _curvea0[180] = _4551; + uint16_t _4552 = (uint16_t)(100); + _curvea0[181] = _4552; + uint16_t _4553 = (uint16_t)(100); + _curvea0[182] = _4553; + uint16_t _4554 = (uint16_t)(101); + _curvea0[183] = _4554; + uint16_t _4555 = (uint16_t)(101); + _curvea0[184] = _4555; + uint16_t _4556 = (uint16_t)(102); + _curvea0[185] = _4556; + uint16_t _4557 = (uint16_t)(102); + _curvea0[186] = _4557; + uint16_t _4558 = (uint16_t)(102); + _curvea0[187] = _4558; + uint16_t _4559 = (uint16_t)(103); + _curvea0[188] = _4559; + uint16_t _4560 = (uint16_t)(103); + _curvea0[189] = _4560; + uint16_t _4561 = (uint16_t)(103); + _curvea0[190] = _4561; + uint16_t _4562 = (uint16_t)(104); + _curvea0[191] = _4562; + uint16_t _4563 = (uint16_t)(104); + _curvea0[192] = _4563; + uint16_t _4564 = (uint16_t)(105); + _curvea0[193] = _4564; + uint16_t _4565 = (uint16_t)(105); + _curvea0[194] = _4565; + uint16_t _4566 = (uint16_t)(105); + _curvea0[195] = _4566; + uint16_t _4567 = (uint16_t)(106); + _curvea0[196] = _4567; + uint16_t _4568 = (uint16_t)(106); + _curvea0[197] = _4568; + uint16_t _4569 = (uint16_t)(106); + _curvea0[198] = _4569; + uint16_t _4570 = (uint16_t)(107); + _curvea0[199] = _4570; + uint16_t _4571 = (uint16_t)(107); + _curvea0[200] = _4571; + uint16_t _4572 = (uint16_t)(108); + _curvea0[201] = _4572; + uint16_t _4573 = (uint16_t)(108); + _curvea0[202] = _4573; + uint16_t _4574 = (uint16_t)(108); + _curvea0[203] = _4574; + uint16_t _4575 = (uint16_t)(109); + _curvea0[204] = _4575; + uint16_t _4576 = (uint16_t)(109); + _curvea0[205] = _4576; + uint16_t _4577 = (uint16_t)(109); + _curvea0[206] = _4577; + uint16_t _4578 = (uint16_t)(110); + _curvea0[207] = _4578; + uint16_t _4579 = (uint16_t)(110); + _curvea0[208] = _4579; + uint16_t _4580 = (uint16_t)(111); + _curvea0[209] = _4580; + uint16_t _4581 = (uint16_t)(111); + _curvea0[210] = _4581; + uint16_t _4582 = (uint16_t)(111); + _curvea0[211] = _4582; + uint16_t _4583 = (uint16_t)(112); + _curvea0[212] = _4583; + uint16_t _4584 = (uint16_t)(112); + _curvea0[213] = _4584; + uint16_t _4585 = (uint16_t)(112); + _curvea0[214] = _4585; + uint16_t _4586 = (uint16_t)(113); + _curvea0[215] = _4586; + uint16_t _4587 = (uint16_t)(113); + _curvea0[216] = _4587; + uint16_t _4588 = (uint16_t)(113); + _curvea0[217] = _4588; + uint16_t _4589 = (uint16_t)(114); + _curvea0[218] = _4589; + uint16_t _4590 = (uint16_t)(114); + _curvea0[219] = _4590; + uint16_t _4591 = (uint16_t)(115); + _curvea0[220] = _4591; + uint16_t _4592 = (uint16_t)(115); + _curvea0[221] = _4592; + uint16_t _4593 = (uint16_t)(115); + _curvea0[222] = _4593; + uint16_t _4594 = (uint16_t)(116); + _curvea0[223] = _4594; + uint16_t _4595 = (uint16_t)(116); + _curvea0[224] = _4595; + uint16_t _4596 = (uint16_t)(116); + _curvea0[225] = _4596; + uint16_t _4597 = (uint16_t)(117); + _curvea0[226] = _4597; + uint16_t _4598 = (uint16_t)(117); + _curvea0[227] = _4598; + uint16_t _4599 = (uint16_t)(117); + _curvea0[228] = _4599; + uint16_t _4600 = (uint16_t)(118); + _curvea0[229] = _4600; + uint16_t _4601 = (uint16_t)(118); + _curvea0[230] = _4601; + uint16_t _4602 = (uint16_t)(119); + _curvea0[231] = _4602; + uint16_t _4603 = (uint16_t)(119); + _curvea0[232] = _4603; + uint16_t _4604 = (uint16_t)(119); + _curvea0[233] = _4604; + uint16_t _4605 = (uint16_t)(120); + _curvea0[234] = _4605; + uint16_t _4606 = (uint16_t)(120); + _curvea0[235] = _4606; + uint16_t _4607 = (uint16_t)(120); + _curvea0[236] = _4607; + uint16_t _4608 = (uint16_t)(121); + _curvea0[237] = _4608; + uint16_t _4609 = (uint16_t)(121); + _curvea0[238] = _4609; + uint16_t _4610 = (uint16_t)(121); + _curvea0[239] = _4610; + uint16_t _4611 = (uint16_t)(122); + _curvea0[240] = _4611; + uint16_t _4612 = (uint16_t)(122); + _curvea0[241] = _4612; + uint16_t _4613 = (uint16_t)(123); + _curvea0[242] = _4613; + uint16_t _4614 = (uint16_t)(123); + _curvea0[243] = _4614; + uint16_t _4615 = (uint16_t)(123); + _curvea0[244] = _4615; + uint16_t _4616 = (uint16_t)(124); + _curvea0[245] = _4616; + uint16_t _4617 = (uint16_t)(124); + _curvea0[246] = _4617; + uint16_t _4618 = (uint16_t)(124); + _curvea0[247] = _4618; + uint16_t _4619 = (uint16_t)(125); + _curvea0[248] = _4619; + uint16_t _4620 = (uint16_t)(125); + _curvea0[249] = _4620; + uint16_t _4621 = (uint16_t)(125); + _curvea0[250] = _4621; + uint16_t _4622 = (uint16_t)(126); + _curvea0[251] = _4622; + uint16_t _4623 = (uint16_t)(126); + _curvea0[252] = _4623; + uint16_t _4624 = (uint16_t)(126); + _curvea0[253] = _4624; + uint16_t _4625 = (uint16_t)(127); + _curvea0[254] = _4625; + uint16_t _4626 = (uint16_t)(127); + _curvea0[255] = _4626; + uint16_t _4627 = (uint16_t)(128); + _curvea0[256] = _4627; + uint16_t _4628 = (uint16_t)(128); + _curvea0[257] = _4628; + uint16_t _4629 = (uint16_t)(128); + _curvea0[258] = _4629; + uint16_t _4630 = (uint16_t)(129); + _curvea0[259] = _4630; + uint16_t _4631 = (uint16_t)(129); + _curvea0[260] = _4631; + uint16_t _4632 = (uint16_t)(129); + _curvea0[261] = _4632; + uint16_t _4633 = (uint16_t)(130); + _curvea0[262] = _4633; + uint16_t _4634 = (uint16_t)(130); + _curvea0[263] = _4634; + uint16_t _4635 = (uint16_t)(130); + _curvea0[264] = _4635; + uint16_t _4636 = (uint16_t)(131); + _curvea0[265] = _4636; + uint16_t _4637 = (uint16_t)(131); + _curvea0[266] = _4637; + uint16_t _4638 = (uint16_t)(131); + _curvea0[267] = _4638; + uint16_t _4639 = (uint16_t)(132); + _curvea0[268] = _4639; + uint16_t _4640 = (uint16_t)(132); + _curvea0[269] = _4640; + uint16_t _4641 = (uint16_t)(132); + _curvea0[270] = _4641; + uint16_t _4642 = (uint16_t)(133); + _curvea0[271] = _4642; + uint16_t _4643 = (uint16_t)(133); + _curvea0[272] = _4643; + uint16_t _4644 = (uint16_t)(133); + _curvea0[273] = _4644; + uint16_t _4645 = (uint16_t)(134); + _curvea0[274] = _4645; + uint16_t _4646 = (uint16_t)(134); + _curvea0[275] = _4646; + uint16_t _4647 = (uint16_t)(134); + _curvea0[276] = _4647; + uint16_t _4648 = (uint16_t)(135); + _curvea0[277] = _4648; + uint16_t _4649 = (uint16_t)(135); + _curvea0[278] = _4649; + uint16_t _4650 = (uint16_t)(135); + _curvea0[279] = _4650; + uint16_t _4651 = (uint16_t)(136); + _curvea0[280] = _4651; + uint16_t _4652 = (uint16_t)(136); + _curvea0[281] = _4652; + uint16_t _4653 = (uint16_t)(136); + _curvea0[282] = _4653; + uint16_t _4654 = (uint16_t)(137); + _curvea0[283] = _4654; + uint16_t _4655 = (uint16_t)(137); + _curvea0[284] = _4655; + uint16_t _4656 = (uint16_t)(137); + _curvea0[285] = _4656; + uint16_t _4657 = (uint16_t)(138); + _curvea0[286] = _4657; + uint16_t _4658 = (uint16_t)(138); + _curvea0[287] = _4658; + uint16_t _4659 = (uint16_t)(138); + _curvea0[288] = _4659; + uint16_t _4660 = (uint16_t)(139); + _curvea0[289] = _4660; + uint16_t _4661 = (uint16_t)(139); + _curvea0[290] = _4661; + uint16_t _4662 = (uint16_t)(139); + _curvea0[291] = _4662; + uint16_t _4663 = (uint16_t)(140); + _curvea0[292] = _4663; + uint16_t _4664 = (uint16_t)(140); + _curvea0[293] = _4664; + uint16_t _4665 = (uint16_t)(140); + _curvea0[294] = _4665; + uint16_t _4666 = (uint16_t)(141); + _curvea0[295] = _4666; + uint16_t _4667 = (uint16_t)(141); + _curvea0[296] = _4667; + uint16_t _4668 = (uint16_t)(141); + _curvea0[297] = _4668; + uint16_t _4669 = (uint16_t)(141); + _curvea0[298] = _4669; + uint16_t _4670 = (uint16_t)(142); + _curvea0[299] = _4670; + uint16_t _4671 = (uint16_t)(142); + _curvea0[300] = _4671; + uint16_t _4672 = (uint16_t)(142); + _curvea0[301] = _4672; + uint16_t _4673 = (uint16_t)(143); + _curvea0[302] = _4673; + uint16_t _4674 = (uint16_t)(143); + _curvea0[303] = _4674; + uint16_t _4675 = (uint16_t)(143); + _curvea0[304] = _4675; + uint16_t _4676 = (uint16_t)(144); + _curvea0[305] = _4676; + uint16_t _4677 = (uint16_t)(144); + _curvea0[306] = _4677; + uint16_t _4678 = (uint16_t)(144); + _curvea0[307] = _4678; + uint16_t _4679 = (uint16_t)(145); + _curvea0[308] = _4679; + uint16_t _4680 = (uint16_t)(145); + _curvea0[309] = _4680; + uint16_t _4681 = (uint16_t)(145); + _curvea0[310] = _4681; + uint16_t _4682 = (uint16_t)(145); + _curvea0[311] = _4682; + uint16_t _4683 = (uint16_t)(146); + _curvea0[312] = _4683; + uint16_t _4684 = (uint16_t)(146); + _curvea0[313] = _4684; + uint16_t _4685 = (uint16_t)(146); + _curvea0[314] = _4685; + uint16_t _4686 = (uint16_t)(147); + _curvea0[315] = _4686; + uint16_t _4687 = (uint16_t)(147); + _curvea0[316] = _4687; + uint16_t _4688 = (uint16_t)(147); + _curvea0[317] = _4688; + uint16_t _4689 = (uint16_t)(148); + _curvea0[318] = _4689; + uint16_t _4690 = (uint16_t)(148); + _curvea0[319] = _4690; + uint16_t _4691 = (uint16_t)(148); + _curvea0[320] = _4691; + uint16_t _4692 = (uint16_t)(148); + _curvea0[321] = _4692; + uint16_t _4693 = (uint16_t)(149); + _curvea0[322] = _4693; + uint16_t _4694 = (uint16_t)(149); + _curvea0[323] = _4694; + uint16_t _4695 = (uint16_t)(149); + _curvea0[324] = _4695; + uint16_t _4696 = (uint16_t)(150); + _curvea0[325] = _4696; + uint16_t _4697 = (uint16_t)(150); + _curvea0[326] = _4697; + uint16_t _4698 = (uint16_t)(150); + _curvea0[327] = _4698; + uint16_t _4699 = (uint16_t)(150); + _curvea0[328] = _4699; + uint16_t _4700 = (uint16_t)(151); + _curvea0[329] = _4700; + uint16_t _4701 = (uint16_t)(151); + _curvea0[330] = _4701; + uint16_t _4702 = (uint16_t)(151); + _curvea0[331] = _4702; + uint16_t _4703 = (uint16_t)(152); + _curvea0[332] = _4703; + uint16_t _4704 = (uint16_t)(152); + _curvea0[333] = _4704; + uint16_t _4705 = (uint16_t)(152); + _curvea0[334] = _4705; + uint16_t _4706 = (uint16_t)(152); + _curvea0[335] = _4706; + uint16_t _4707 = (uint16_t)(153); + _curvea0[336] = _4707; + uint16_t _4708 = (uint16_t)(153); + _curvea0[337] = _4708; + uint16_t _4709 = (uint16_t)(153); + _curvea0[338] = _4709; + uint16_t _4710 = (uint16_t)(154); + _curvea0[339] = _4710; + uint16_t _4711 = (uint16_t)(154); + _curvea0[340] = _4711; + uint16_t _4712 = (uint16_t)(154); + _curvea0[341] = _4712; + uint16_t _4713 = (uint16_t)(154); + _curvea0[342] = _4713; + uint16_t _4714 = (uint16_t)(155); + _curvea0[343] = _4714; + uint16_t _4715 = (uint16_t)(155); + _curvea0[344] = _4715; + uint16_t _4716 = (uint16_t)(155); + _curvea0[345] = _4716; + uint16_t _4717 = (uint16_t)(156); + _curvea0[346] = _4717; + uint16_t _4718 = (uint16_t)(156); + _curvea0[347] = _4718; + uint16_t _4719 = (uint16_t)(156); + _curvea0[348] = _4719; + uint16_t _4720 = (uint16_t)(156); + _curvea0[349] = _4720; + uint16_t _4721 = (uint16_t)(157); + _curvea0[350] = _4721; + uint16_t _4722 = (uint16_t)(157); + _curvea0[351] = _4722; + uint16_t _4723 = (uint16_t)(157); + _curvea0[352] = _4723; + uint16_t _4724 = (uint16_t)(157); + _curvea0[353] = _4724; + uint16_t _4725 = (uint16_t)(158); + _curvea0[354] = _4725; + uint16_t _4726 = (uint16_t)(158); + _curvea0[355] = _4726; + uint16_t _4727 = (uint16_t)(158); + _curvea0[356] = _4727; + uint16_t _4728 = (uint16_t)(159); + _curvea0[357] = _4728; + uint16_t _4729 = (uint16_t)(159); + _curvea0[358] = _4729; + uint16_t _4730 = (uint16_t)(159); + _curvea0[359] = _4730; + uint16_t _4731 = (uint16_t)(159); + _curvea0[360] = _4731; + uint16_t _4732 = (uint16_t)(160); + _curvea0[361] = _4732; + uint16_t _4733 = (uint16_t)(160); + _curvea0[362] = _4733; + uint16_t _4734 = (uint16_t)(160); + _curvea0[363] = _4734; + uint16_t _4735 = (uint16_t)(160); + _curvea0[364] = _4735; + uint16_t _4736 = (uint16_t)(161); + _curvea0[365] = _4736; + uint16_t _4737 = (uint16_t)(161); + _curvea0[366] = _4737; + uint16_t _4738 = (uint16_t)(161); + _curvea0[367] = _4738; + uint16_t _4739 = (uint16_t)(161); + _curvea0[368] = _4739; + uint16_t _4740 = (uint16_t)(162); + _curvea0[369] = _4740; + uint16_t _4741 = (uint16_t)(162); + _curvea0[370] = _4741; + uint16_t _4742 = (uint16_t)(162); + _curvea0[371] = _4742; + uint16_t _4743 = (uint16_t)(162); + _curvea0[372] = _4743; + uint16_t _4744 = (uint16_t)(163); + _curvea0[373] = _4744; + uint16_t _4745 = (uint16_t)(163); + _curvea0[374] = _4745; + uint16_t _4746 = (uint16_t)(163); + _curvea0[375] = _4746; + uint16_t _4747 = (uint16_t)(163); + _curvea0[376] = _4747; + uint16_t _4748 = (uint16_t)(164); + _curvea0[377] = _4748; + uint16_t _4749 = (uint16_t)(164); + _curvea0[378] = _4749; + uint16_t _4750 = (uint16_t)(164); + _curvea0[379] = _4750; + uint16_t _4751 = (uint16_t)(164); + _curvea0[380] = _4751; + uint16_t _4752 = (uint16_t)(165); + _curvea0[381] = _4752; + uint16_t _4753 = (uint16_t)(165); + _curvea0[382] = _4753; + uint16_t _4754 = (uint16_t)(165); + _curvea0[383] = _4754; + uint16_t _4755 = (uint16_t)(166); + _curvea0[384] = _4755; + uint16_t _4756 = (uint16_t)(166); + _curvea0[385] = _4756; + uint16_t _4757 = (uint16_t)(166); + _curvea0[386] = _4757; + uint16_t _4758 = (uint16_t)(166); + _curvea0[387] = _4758; + uint16_t _4759 = (uint16_t)(167); + _curvea0[388] = _4759; + uint16_t _4760 = (uint16_t)(167); + _curvea0[389] = _4760; + uint16_t _4761 = (uint16_t)(167); + _curvea0[390] = _4761; + uint16_t _4762 = (uint16_t)(167); + _curvea0[391] = _4762; + uint16_t _4763 = (uint16_t)(167); + _curvea0[392] = _4763; + uint16_t _4764 = (uint16_t)(168); + _curvea0[393] = _4764; + uint16_t _4765 = (uint16_t)(168); + _curvea0[394] = _4765; + uint16_t _4766 = (uint16_t)(168); + _curvea0[395] = _4766; + uint16_t _4767 = (uint16_t)(168); + _curvea0[396] = _4767; + uint16_t _4768 = (uint16_t)(169); + _curvea0[397] = _4768; + uint16_t _4769 = (uint16_t)(169); + _curvea0[398] = _4769; + uint16_t _4770 = (uint16_t)(169); + _curvea0[399] = _4770; + uint16_t _4771 = (uint16_t)(169); + _curvea0[400] = _4771; + uint16_t _4772 = (uint16_t)(170); + _curvea0[401] = _4772; + uint16_t _4773 = (uint16_t)(170); + _curvea0[402] = _4773; + uint16_t _4774 = (uint16_t)(170); + _curvea0[403] = _4774; + uint16_t _4775 = (uint16_t)(170); + _curvea0[404] = _4775; + uint16_t _4776 = (uint16_t)(171); + _curvea0[405] = _4776; + uint16_t _4777 = (uint16_t)(171); + _curvea0[406] = _4777; + uint16_t _4778 = (uint16_t)(171); + _curvea0[407] = _4778; + uint16_t _4779 = (uint16_t)(171); + _curvea0[408] = _4779; + uint16_t _4780 = (uint16_t)(172); + _curvea0[409] = _4780; + uint16_t _4781 = (uint16_t)(172); + _curvea0[410] = _4781; + uint16_t _4782 = (uint16_t)(172); + _curvea0[411] = _4782; + uint16_t _4783 = (uint16_t)(172); + _curvea0[412] = _4783; + uint16_t _4784 = (uint16_t)(173); + _curvea0[413] = _4784; + uint16_t _4785 = (uint16_t)(173); + _curvea0[414] = _4785; + uint16_t _4786 = (uint16_t)(173); + _curvea0[415] = _4786; + uint16_t _4787 = (uint16_t)(173); + _curvea0[416] = _4787; + uint16_t _4788 = (uint16_t)(173); + _curvea0[417] = _4788; + uint16_t _4789 = (uint16_t)(174); + _curvea0[418] = _4789; + uint16_t _4790 = (uint16_t)(174); + _curvea0[419] = _4790; + uint16_t _4791 = (uint16_t)(174); + _curvea0[420] = _4791; + uint16_t _4792 = (uint16_t)(174); + _curvea0[421] = _4792; + uint16_t _4793 = (uint16_t)(175); + _curvea0[422] = _4793; + uint16_t _4794 = (uint16_t)(175); + _curvea0[423] = _4794; + uint16_t _4795 = (uint16_t)(175); + _curvea0[424] = _4795; + uint16_t _4796 = (uint16_t)(175); + _curvea0[425] = _4796; + uint16_t _4797 = (uint16_t)(176); + _curvea0[426] = _4797; + uint16_t _4798 = (uint16_t)(176); + _curvea0[427] = _4798; + uint16_t _4799 = (uint16_t)(176); + _curvea0[428] = _4799; + uint16_t _4800 = (uint16_t)(176); + _curvea0[429] = _4800; + uint16_t _4801 = (uint16_t)(176); + _curvea0[430] = _4801; + uint16_t _4802 = (uint16_t)(177); + _curvea0[431] = _4802; + uint16_t _4803 = (uint16_t)(177); + _curvea0[432] = _4803; + uint16_t _4804 = (uint16_t)(177); + _curvea0[433] = _4804; + uint16_t _4805 = (uint16_t)(177); + _curvea0[434] = _4805; + uint16_t _4806 = (uint16_t)(178); + _curvea0[435] = _4806; + uint16_t _4807 = (uint16_t)(178); + _curvea0[436] = _4807; + uint16_t _4808 = (uint16_t)(178); + _curvea0[437] = _4808; + uint16_t _4809 = (uint16_t)(178); + _curvea0[438] = _4809; + uint16_t _4810 = (uint16_t)(178); + _curvea0[439] = _4810; + uint16_t _4811 = (uint16_t)(179); + _curvea0[440] = _4811; + uint16_t _4812 = (uint16_t)(179); + _curvea0[441] = _4812; + uint16_t _4813 = (uint16_t)(179); + _curvea0[442] = _4813; + uint16_t _4814 = (uint16_t)(179); + _curvea0[443] = _4814; + uint16_t _4815 = (uint16_t)(180); + _curvea0[444] = _4815; + uint16_t _4816 = (uint16_t)(180); + _curvea0[445] = _4816; + uint16_t _4817 = (uint16_t)(180); + _curvea0[446] = _4817; + uint16_t _4818 = (uint16_t)(180); + _curvea0[447] = _4818; + uint16_t _4819 = (uint16_t)(180); + _curvea0[448] = _4819; + uint16_t _4820 = (uint16_t)(181); + _curvea0[449] = _4820; + uint16_t _4821 = (uint16_t)(181); + _curvea0[450] = _4821; + uint16_t _4822 = (uint16_t)(181); + _curvea0[451] = _4822; + uint16_t _4823 = (uint16_t)(181); + _curvea0[452] = _4823; + uint16_t _4824 = (uint16_t)(181); + _curvea0[453] = _4824; + uint16_t _4825 = (uint16_t)(182); + _curvea0[454] = _4825; + uint16_t _4826 = (uint16_t)(182); + _curvea0[455] = _4826; + uint16_t _4827 = (uint16_t)(182); + _curvea0[456] = _4827; + uint16_t _4828 = (uint16_t)(182); + _curvea0[457] = _4828; + uint16_t _4829 = (uint16_t)(183); + _curvea0[458] = _4829; + uint16_t _4830 = (uint16_t)(183); + _curvea0[459] = _4830; + uint16_t _4831 = (uint16_t)(183); + _curvea0[460] = _4831; + uint16_t _4832 = (uint16_t)(183); + _curvea0[461] = _4832; + uint16_t _4833 = (uint16_t)(183); + _curvea0[462] = _4833; + uint16_t _4834 = (uint16_t)(184); + _curvea0[463] = _4834; + uint16_t _4835 = (uint16_t)(184); + _curvea0[464] = _4835; + uint16_t _4836 = (uint16_t)(184); + _curvea0[465] = _4836; + uint16_t _4837 = (uint16_t)(184); + _curvea0[466] = _4837; + uint16_t _4838 = (uint16_t)(184); + _curvea0[467] = _4838; + uint16_t _4839 = (uint16_t)(185); + _curvea0[468] = _4839; + uint16_t _4840 = (uint16_t)(185); + _curvea0[469] = _4840; + uint16_t _4841 = (uint16_t)(185); + _curvea0[470] = _4841; + uint16_t _4842 = (uint16_t)(185); + _curvea0[471] = _4842; + uint16_t _4843 = (uint16_t)(185); + _curvea0[472] = _4843; + uint16_t _4844 = (uint16_t)(186); + _curvea0[473] = _4844; + uint16_t _4845 = (uint16_t)(186); + _curvea0[474] = _4845; + uint16_t _4846 = (uint16_t)(186); + _curvea0[475] = _4846; + uint16_t _4847 = (uint16_t)(186); + _curvea0[476] = _4847; + uint16_t _4848 = (uint16_t)(187); + _curvea0[477] = _4848; + uint16_t _4849 = (uint16_t)(187); + _curvea0[478] = _4849; + uint16_t _4850 = (uint16_t)(187); + _curvea0[479] = _4850; + uint16_t _4851 = (uint16_t)(187); + _curvea0[480] = _4851; + uint16_t _4852 = (uint16_t)(187); + _curvea0[481] = _4852; + uint16_t _4853 = (uint16_t)(188); + _curvea0[482] = _4853; + uint16_t _4854 = (uint16_t)(188); + _curvea0[483] = _4854; + uint16_t _4855 = (uint16_t)(188); + _curvea0[484] = _4855; + uint16_t _4856 = (uint16_t)(188); + _curvea0[485] = _4856; + uint16_t _4857 = (uint16_t)(188); + _curvea0[486] = _4857; + uint16_t _4858 = (uint16_t)(189); + _curvea0[487] = _4858; + uint16_t _4859 = (uint16_t)(189); + _curvea0[488] = _4859; + uint16_t _4860 = (uint16_t)(189); + _curvea0[489] = _4860; + uint16_t _4861 = (uint16_t)(189); + _curvea0[490] = _4861; + uint16_t _4862 = (uint16_t)(189); + _curvea0[491] = _4862; + uint16_t _4863 = (uint16_t)(190); + _curvea0[492] = _4863; + uint16_t _4864 = (uint16_t)(190); + _curvea0[493] = _4864; + uint16_t _4865 = (uint16_t)(190); + _curvea0[494] = _4865; + uint16_t _4866 = (uint16_t)(190); + _curvea0[495] = _4866; + uint16_t _4867 = (uint16_t)(190); + _curvea0[496] = _4867; + uint16_t _4868 = (uint16_t)(190); + _curvea0[497] = _4868; + uint16_t _4869 = (uint16_t)(191); + _curvea0[498] = _4869; + uint16_t _4870 = (uint16_t)(191); + _curvea0[499] = _4870; + uint16_t _4871 = (uint16_t)(191); + _curvea0[500] = _4871; + uint16_t _4872 = (uint16_t)(191); + _curvea0[501] = _4872; + uint16_t _4873 = (uint16_t)(191); + _curvea0[502] = _4873; + uint16_t _4874 = (uint16_t)(192); + _curvea0[503] = _4874; + uint16_t _4875 = (uint16_t)(192); + _curvea0[504] = _4875; + uint16_t _4876 = (uint16_t)(192); + _curvea0[505] = _4876; + uint16_t _4877 = (uint16_t)(192); + _curvea0[506] = _4877; + uint16_t _4878 = (uint16_t)(192); + _curvea0[507] = _4878; + uint16_t _4879 = (uint16_t)(193); + _curvea0[508] = _4879; + uint16_t _4880 = (uint16_t)(193); + _curvea0[509] = _4880; + uint16_t _4881 = (uint16_t)(193); + _curvea0[510] = _4881; + uint16_t _4882 = (uint16_t)(193); + _curvea0[511] = _4882; + uint16_t _4883 = (uint16_t)(193); + _curvea0[512] = _4883; + uint16_t _4884 = (uint16_t)(194); + _curvea0[513] = _4884; + uint16_t _4885 = (uint16_t)(194); + _curvea0[514] = _4885; + uint16_t _4886 = (uint16_t)(194); + _curvea0[515] = _4886; + uint16_t _4887 = (uint16_t)(194); + _curvea0[516] = _4887; + uint16_t _4888 = (uint16_t)(194); + _curvea0[517] = _4888; + uint16_t _4889 = (uint16_t)(195); + _curvea0[518] = _4889; + uint16_t _4890 = (uint16_t)(195); + _curvea0[519] = _4890; + uint16_t _4891 = (uint16_t)(195); + _curvea0[520] = _4891; + uint16_t _4892 = (uint16_t)(195); + _curvea0[521] = _4892; + uint16_t _4893 = (uint16_t)(195); + _curvea0[522] = _4893; + uint16_t _4894 = (uint16_t)(195); + _curvea0[523] = _4894; + uint16_t _4895 = (uint16_t)(196); + _curvea0[524] = _4895; + uint16_t _4896 = (uint16_t)(196); + _curvea0[525] = _4896; + uint16_t _4897 = (uint16_t)(196); + _curvea0[526] = _4897; + uint16_t _4898 = (uint16_t)(196); + _curvea0[527] = _4898; + uint16_t _4899 = (uint16_t)(196); + _curvea0[528] = _4899; + uint16_t _4900 = (uint16_t)(197); + _curvea0[529] = _4900; + uint16_t _4901 = (uint16_t)(197); + _curvea0[530] = _4901; + uint16_t _4902 = (uint16_t)(197); + _curvea0[531] = _4902; + uint16_t _4903 = (uint16_t)(197); + _curvea0[532] = _4903; + uint16_t _4904 = (uint16_t)(197); + _curvea0[533] = _4904; + uint16_t _4905 = (uint16_t)(197); + _curvea0[534] = _4905; + uint16_t _4906 = (uint16_t)(198); + _curvea0[535] = _4906; + uint16_t _4907 = (uint16_t)(198); + _curvea0[536] = _4907; + uint16_t _4908 = (uint16_t)(198); + _curvea0[537] = _4908; + uint16_t _4909 = (uint16_t)(198); + _curvea0[538] = _4909; + uint16_t _4910 = (uint16_t)(198); + _curvea0[539] = _4910; + uint16_t _4911 = (uint16_t)(199); + _curvea0[540] = _4911; + uint16_t _4912 = (uint16_t)(199); + _curvea0[541] = _4912; + uint16_t _4913 = (uint16_t)(199); + _curvea0[542] = _4913; + uint16_t _4914 = (uint16_t)(199); + _curvea0[543] = _4914; + uint16_t _4915 = (uint16_t)(199); + _curvea0[544] = _4915; + uint16_t _4916 = (uint16_t)(199); + _curvea0[545] = _4916; + uint16_t _4917 = (uint16_t)(200); + _curvea0[546] = _4917; + uint16_t _4918 = (uint16_t)(200); + _curvea0[547] = _4918; + uint16_t _4919 = (uint16_t)(200); + _curvea0[548] = _4919; + uint16_t _4920 = (uint16_t)(200); + _curvea0[549] = _4920; + uint16_t _4921 = (uint16_t)(200); + _curvea0[550] = _4921; + uint16_t _4922 = (uint16_t)(200); + _curvea0[551] = _4922; + uint16_t _4923 = (uint16_t)(201); + _curvea0[552] = _4923; + uint16_t _4924 = (uint16_t)(201); + _curvea0[553] = _4924; + uint16_t _4925 = (uint16_t)(201); + _curvea0[554] = _4925; + uint16_t _4926 = (uint16_t)(201); + _curvea0[555] = _4926; + uint16_t _4927 = (uint16_t)(201); + _curvea0[556] = _4927; + uint16_t _4928 = (uint16_t)(202); + _curvea0[557] = _4928; + uint16_t _4929 = (uint16_t)(202); + _curvea0[558] = _4929; + uint16_t _4930 = (uint16_t)(202); + _curvea0[559] = _4930; + uint16_t _4931 = (uint16_t)(202); + _curvea0[560] = _4931; + uint16_t _4932 = (uint16_t)(202); + _curvea0[561] = _4932; + uint16_t _4933 = (uint16_t)(202); + _curvea0[562] = _4933; + uint16_t _4934 = (uint16_t)(203); + _curvea0[563] = _4934; + uint16_t _4935 = (uint16_t)(203); + _curvea0[564] = _4935; + uint16_t _4936 = (uint16_t)(203); + _curvea0[565] = _4936; + uint16_t _4937 = (uint16_t)(203); + _curvea0[566] = _4937; + uint16_t _4938 = (uint16_t)(203); + _curvea0[567] = _4938; + uint16_t _4939 = (uint16_t)(203); + _curvea0[568] = _4939; + uint16_t _4940 = (uint16_t)(204); + _curvea0[569] = _4940; + uint16_t _4941 = (uint16_t)(204); + _curvea0[570] = _4941; + uint16_t _4942 = (uint16_t)(204); + _curvea0[571] = _4942; + uint16_t _4943 = (uint16_t)(204); + _curvea0[572] = _4943; + uint16_t _4944 = (uint16_t)(204); + _curvea0[573] = _4944; + uint16_t _4945 = (uint16_t)(204); + _curvea0[574] = _4945; + uint16_t _4946 = (uint16_t)(205); + _curvea0[575] = _4946; + uint16_t _4947 = (uint16_t)(205); + _curvea0[576] = _4947; + uint16_t _4948 = (uint16_t)(205); + _curvea0[577] = _4948; + uint16_t _4949 = (uint16_t)(205); + _curvea0[578] = _4949; + uint16_t _4950 = (uint16_t)(205); + _curvea0[579] = _4950; + uint16_t _4951 = (uint16_t)(205); + _curvea0[580] = _4951; + uint16_t _4952 = (uint16_t)(206); + _curvea0[581] = _4952; + uint16_t _4953 = (uint16_t)(206); + _curvea0[582] = _4953; + uint16_t _4954 = (uint16_t)(206); + _curvea0[583] = _4954; + uint16_t _4955 = (uint16_t)(206); + _curvea0[584] = _4955; + uint16_t _4956 = (uint16_t)(206); + _curvea0[585] = _4956; + uint16_t _4957 = (uint16_t)(206); + _curvea0[586] = _4957; + uint16_t _4958 = (uint16_t)(207); + _curvea0[587] = _4958; + uint16_t _4959 = (uint16_t)(207); + _curvea0[588] = _4959; + uint16_t _4960 = (uint16_t)(207); + _curvea0[589] = _4960; + uint16_t _4961 = (uint16_t)(207); + _curvea0[590] = _4961; + uint16_t _4962 = (uint16_t)(207); + _curvea0[591] = _4962; + uint16_t _4963 = (uint16_t)(207); + _curvea0[592] = _4963; + uint16_t _4964 = (uint16_t)(208); + _curvea0[593] = _4964; + uint16_t _4965 = (uint16_t)(208); + _curvea0[594] = _4965; + uint16_t _4966 = (uint16_t)(208); + _curvea0[595] = _4966; + uint16_t _4967 = (uint16_t)(208); + _curvea0[596] = _4967; + uint16_t _4968 = (uint16_t)(208); + _curvea0[597] = _4968; + uint16_t _4969 = (uint16_t)(208); + _curvea0[598] = _4969; + uint16_t _4970 = (uint16_t)(209); + _curvea0[599] = _4970; + uint16_t _4971 = (uint16_t)(209); + _curvea0[600] = _4971; + uint16_t _4972 = (uint16_t)(209); + _curvea0[601] = _4972; + uint16_t _4973 = (uint16_t)(209); + _curvea0[602] = _4973; + uint16_t _4974 = (uint16_t)(209); + _curvea0[603] = _4974; + uint16_t _4975 = (uint16_t)(209); + _curvea0[604] = _4975; + uint16_t _4976 = (uint16_t)(209); + _curvea0[605] = _4976; + uint16_t _4977 = (uint16_t)(210); + _curvea0[606] = _4977; + uint16_t _4978 = (uint16_t)(210); + _curvea0[607] = _4978; + uint16_t _4979 = (uint16_t)(210); + _curvea0[608] = _4979; + uint16_t _4980 = (uint16_t)(210); + _curvea0[609] = _4980; + uint16_t _4981 = (uint16_t)(210); + _curvea0[610] = _4981; + uint16_t _4982 = (uint16_t)(210); + _curvea0[611] = _4982; + uint16_t _4983 = (uint16_t)(211); + _curvea0[612] = _4983; + uint16_t _4984 = (uint16_t)(211); + _curvea0[613] = _4984; + uint16_t _4985 = (uint16_t)(211); + _curvea0[614] = _4985; + uint16_t _4986 = (uint16_t)(211); + _curvea0[615] = _4986; + uint16_t _4987 = (uint16_t)(211); + _curvea0[616] = _4987; + uint16_t _4988 = (uint16_t)(211); + _curvea0[617] = _4988; + uint16_t _4989 = (uint16_t)(211); + _curvea0[618] = _4989; + uint16_t _4990 = (uint16_t)(212); + _curvea0[619] = _4990; + uint16_t _4991 = (uint16_t)(212); + _curvea0[620] = _4991; + uint16_t _4992 = (uint16_t)(212); + _curvea0[621] = _4992; + uint16_t _4993 = (uint16_t)(212); + _curvea0[622] = _4993; + uint16_t _4994 = (uint16_t)(212); + _curvea0[623] = _4994; + uint16_t _4995 = (uint16_t)(212); + _curvea0[624] = _4995; + uint16_t _4996 = (uint16_t)(213); + _curvea0[625] = _4996; + uint16_t _4997 = (uint16_t)(213); + _curvea0[626] = _4997; + uint16_t _4998 = (uint16_t)(213); + _curvea0[627] = _4998; + uint16_t _4999 = (uint16_t)(213); + _curvea0[628] = _4999; + uint16_t _5000 = (uint16_t)(213); + _curvea0[629] = _5000; + uint16_t _5001 = (uint16_t)(213); + _curvea0[630] = _5001; + uint16_t _5002 = (uint16_t)(213); + _curvea0[631] = _5002; + uint16_t _5003 = (uint16_t)(214); + _curvea0[632] = _5003; + uint16_t _5004 = (uint16_t)(214); + _curvea0[633] = _5004; + uint16_t _5005 = (uint16_t)(214); + _curvea0[634] = _5005; + uint16_t _5006 = (uint16_t)(214); + _curvea0[635] = _5006; + uint16_t _5007 = (uint16_t)(214); + _curvea0[636] = _5007; + uint16_t _5008 = (uint16_t)(214); + _curvea0[637] = _5008; + uint16_t _5009 = (uint16_t)(214); + _curvea0[638] = _5009; + uint16_t _5010 = (uint16_t)(215); + _curvea0[639] = _5010; + uint16_t _5011 = (uint16_t)(215); + _curvea0[640] = _5011; + uint16_t _5012 = (uint16_t)(215); + _curvea0[641] = _5012; + uint16_t _5013 = (uint16_t)(215); + _curvea0[642] = _5013; + uint16_t _5014 = (uint16_t)(215); + _curvea0[643] = _5014; + uint16_t _5015 = (uint16_t)(215); + _curvea0[644] = _5015; + uint16_t _5016 = (uint16_t)(216); + _curvea0[645] = _5016; + uint16_t _5017 = (uint16_t)(216); + _curvea0[646] = _5017; + uint16_t _5018 = (uint16_t)(216); + _curvea0[647] = _5018; + uint16_t _5019 = (uint16_t)(216); + _curvea0[648] = _5019; + uint16_t _5020 = (uint16_t)(216); + _curvea0[649] = _5020; + uint16_t _5021 = (uint16_t)(216); + _curvea0[650] = _5021; + uint16_t _5022 = (uint16_t)(216); + _curvea0[651] = _5022; + uint16_t _5023 = (uint16_t)(217); + _curvea0[652] = _5023; + uint16_t _5024 = (uint16_t)(217); + _curvea0[653] = _5024; + uint16_t _5025 = (uint16_t)(217); + _curvea0[654] = _5025; + uint16_t _5026 = (uint16_t)(217); + _curvea0[655] = _5026; + uint16_t _5027 = (uint16_t)(217); + _curvea0[656] = _5027; + uint16_t _5028 = (uint16_t)(217); + _curvea0[657] = _5028; + uint16_t _5029 = (uint16_t)(217); + _curvea0[658] = _5029; + uint16_t _5030 = (uint16_t)(218); + _curvea0[659] = _5030; + uint16_t _5031 = (uint16_t)(218); + _curvea0[660] = _5031; + uint16_t _5032 = (uint16_t)(218); + _curvea0[661] = _5032; + uint16_t _5033 = (uint16_t)(218); + _curvea0[662] = _5033; + uint16_t _5034 = (uint16_t)(218); + _curvea0[663] = _5034; + uint16_t _5035 = (uint16_t)(218); + _curvea0[664] = _5035; + uint16_t _5036 = (uint16_t)(218); + _curvea0[665] = _5036; + uint16_t _5037 = (uint16_t)(219); + _curvea0[666] = _5037; + uint16_t _5038 = (uint16_t)(219); + _curvea0[667] = _5038; + uint16_t _5039 = (uint16_t)(219); + _curvea0[668] = _5039; + uint16_t _5040 = (uint16_t)(219); + _curvea0[669] = _5040; + uint16_t _5041 = (uint16_t)(219); + _curvea0[670] = _5041; + uint16_t _5042 = (uint16_t)(219); + _curvea0[671] = _5042; + uint16_t _5043 = (uint16_t)(219); + _curvea0[672] = _5043; + uint16_t _5044 = (uint16_t)(220); + _curvea0[673] = _5044; + uint16_t _5045 = (uint16_t)(220); + _curvea0[674] = _5045; + uint16_t _5046 = (uint16_t)(220); + _curvea0[675] = _5046; + uint16_t _5047 = (uint16_t)(220); + _curvea0[676] = _5047; + uint16_t _5048 = (uint16_t)(220); + _curvea0[677] = _5048; + uint16_t _5049 = (uint16_t)(220); + _curvea0[678] = _5049; + uint16_t _5050 = (uint16_t)(220); + _curvea0[679] = _5050; + uint16_t _5051 = (uint16_t)(220); + _curvea0[680] = _5051; + uint16_t _5052 = (uint16_t)(221); + _curvea0[681] = _5052; + uint16_t _5053 = (uint16_t)(221); + _curvea0[682] = _5053; + uint16_t _5054 = (uint16_t)(221); + _curvea0[683] = _5054; + uint16_t _5055 = (uint16_t)(221); + _curvea0[684] = _5055; + uint16_t _5056 = (uint16_t)(221); + _curvea0[685] = _5056; + uint16_t _5057 = (uint16_t)(221); + _curvea0[686] = _5057; + uint16_t _5058 = (uint16_t)(221); + _curvea0[687] = _5058; + uint16_t _5059 = (uint16_t)(222); + _curvea0[688] = _5059; + uint16_t _5060 = (uint16_t)(222); + _curvea0[689] = _5060; + uint16_t _5061 = (uint16_t)(222); + _curvea0[690] = _5061; + uint16_t _5062 = (uint16_t)(222); + _curvea0[691] = _5062; + uint16_t _5063 = (uint16_t)(222); + _curvea0[692] = _5063; + uint16_t _5064 = (uint16_t)(222); + _curvea0[693] = _5064; + uint16_t _5065 = (uint16_t)(222); + _curvea0[694] = _5065; + uint16_t _5066 = (uint16_t)(223); + _curvea0[695] = _5066; + uint16_t _5067 = (uint16_t)(223); + _curvea0[696] = _5067; + uint16_t _5068 = (uint16_t)(223); + _curvea0[697] = _5068; + uint16_t _5069 = (uint16_t)(223); + _curvea0[698] = _5069; + uint16_t _5070 = (uint16_t)(223); + _curvea0[699] = _5070; + uint16_t _5071 = (uint16_t)(223); + _curvea0[700] = _5071; + uint16_t _5072 = (uint16_t)(223); + _curvea0[701] = _5072; + uint16_t _5073 = (uint16_t)(223); + _curvea0[702] = _5073; + uint16_t _5074 = (uint16_t)(224); + _curvea0[703] = _5074; + uint16_t _5075 = (uint16_t)(224); + _curvea0[704] = _5075; + uint16_t _5076 = (uint16_t)(224); + _curvea0[705] = _5076; + uint16_t _5077 = (uint16_t)(224); + _curvea0[706] = _5077; + uint16_t _5078 = (uint16_t)(224); + _curvea0[707] = _5078; + uint16_t _5079 = (uint16_t)(224); + _curvea0[708] = _5079; + uint16_t _5080 = (uint16_t)(224); + _curvea0[709] = _5080; + uint16_t _5081 = (uint16_t)(224); + _curvea0[710] = _5081; + uint16_t _5082 = (uint16_t)(225); + _curvea0[711] = _5082; + uint16_t _5083 = (uint16_t)(225); + _curvea0[712] = _5083; + uint16_t _5084 = (uint16_t)(225); + _curvea0[713] = _5084; + uint16_t _5085 = (uint16_t)(225); + _curvea0[714] = _5085; + uint16_t _5086 = (uint16_t)(225); + _curvea0[715] = _5086; + uint16_t _5087 = (uint16_t)(225); + _curvea0[716] = _5087; + uint16_t _5088 = (uint16_t)(225); + _curvea0[717] = _5088; + uint16_t _5089 = (uint16_t)(226); + _curvea0[718] = _5089; + uint16_t _5090 = (uint16_t)(226); + _curvea0[719] = _5090; + uint16_t _5091 = (uint16_t)(226); + _curvea0[720] = _5091; + uint16_t _5092 = (uint16_t)(226); + _curvea0[721] = _5092; + uint16_t _5093 = (uint16_t)(226); + _curvea0[722] = _5093; + uint16_t _5094 = (uint16_t)(226); + _curvea0[723] = _5094; + uint16_t _5095 = (uint16_t)(226); + _curvea0[724] = _5095; + uint16_t _5096 = (uint16_t)(226); + _curvea0[725] = _5096; + uint16_t _5097 = (uint16_t)(227); + _curvea0[726] = _5097; + uint16_t _5098 = (uint16_t)(227); + _curvea0[727] = _5098; + uint16_t _5099 = (uint16_t)(227); + _curvea0[728] = _5099; + uint16_t _5100 = (uint16_t)(227); + _curvea0[729] = _5100; + uint16_t _5101 = (uint16_t)(227); + _curvea0[730] = _5101; + uint16_t _5102 = (uint16_t)(227); + _curvea0[731] = _5102; + uint16_t _5103 = (uint16_t)(227); + _curvea0[732] = _5103; + uint16_t _5104 = (uint16_t)(227); + _curvea0[733] = _5104; + uint16_t _5105 = (uint16_t)(228); + _curvea0[734] = _5105; + uint16_t _5106 = (uint16_t)(228); + _curvea0[735] = _5106; + uint16_t _5107 = (uint16_t)(228); + _curvea0[736] = _5107; + uint16_t _5108 = (uint16_t)(228); + _curvea0[737] = _5108; + uint16_t _5109 = (uint16_t)(228); + _curvea0[738] = _5109; + uint16_t _5110 = (uint16_t)(228); + _curvea0[739] = _5110; + uint16_t _5111 = (uint16_t)(228); + _curvea0[740] = _5111; + uint16_t _5112 = (uint16_t)(228); + _curvea0[741] = _5112; + uint16_t _5113 = (uint16_t)(228); + _curvea0[742] = _5113; + uint16_t _5114 = (uint16_t)(229); + _curvea0[743] = _5114; + uint16_t _5115 = (uint16_t)(229); + _curvea0[744] = _5115; + uint16_t _5116 = (uint16_t)(229); + _curvea0[745] = _5116; + uint16_t _5117 = (uint16_t)(229); + _curvea0[746] = _5117; + uint16_t _5118 = (uint16_t)(229); + _curvea0[747] = _5118; + uint16_t _5119 = (uint16_t)(229); + _curvea0[748] = _5119; + uint16_t _5120 = (uint16_t)(229); + _curvea0[749] = _5120; + uint16_t _5121 = (uint16_t)(229); + _curvea0[750] = _5121; + uint16_t _5122 = (uint16_t)(230); + _curvea0[751] = _5122; + uint16_t _5123 = (uint16_t)(230); + _curvea0[752] = _5123; + uint16_t _5124 = (uint16_t)(230); + _curvea0[753] = _5124; + uint16_t _5125 = (uint16_t)(230); + _curvea0[754] = _5125; + uint16_t _5126 = (uint16_t)(230); + _curvea0[755] = _5126; + uint16_t _5127 = (uint16_t)(230); + _curvea0[756] = _5127; + uint16_t _5128 = (uint16_t)(230); + _curvea0[757] = _5128; + uint16_t _5129 = (uint16_t)(230); + _curvea0[758] = _5129; + uint16_t _5130 = (uint16_t)(231); + _curvea0[759] = _5130; + uint16_t _5131 = (uint16_t)(231); + _curvea0[760] = _5131; + uint16_t _5132 = (uint16_t)(231); + _curvea0[761] = _5132; + uint16_t _5133 = (uint16_t)(231); + _curvea0[762] = _5133; + uint16_t _5134 = (uint16_t)(231); + _curvea0[763] = _5134; + uint16_t _5135 = (uint16_t)(231); + _curvea0[764] = _5135; + uint16_t _5136 = (uint16_t)(231); + _curvea0[765] = _5136; + uint16_t _5137 = (uint16_t)(231); + _curvea0[766] = _5137; + uint16_t _5138 = (uint16_t)(231); + _curvea0[767] = _5138; + uint16_t _5139 = (uint16_t)(232); + _curvea0[768] = _5139; + uint16_t _5140 = (uint16_t)(232); + _curvea0[769] = _5140; + uint16_t _5141 = (uint16_t)(232); + _curvea0[770] = _5141; + uint16_t _5142 = (uint16_t)(232); + _curvea0[771] = _5142; + uint16_t _5143 = (uint16_t)(232); + _curvea0[772] = _5143; + uint16_t _5144 = (uint16_t)(232); + _curvea0[773] = _5144; + uint16_t _5145 = (uint16_t)(232); + _curvea0[774] = _5145; + uint16_t _5146 = (uint16_t)(232); + _curvea0[775] = _5146; + uint16_t _5147 = (uint16_t)(233); + _curvea0[776] = _5147; + uint16_t _5148 = (uint16_t)(233); + _curvea0[777] = _5148; + uint16_t _5149 = (uint16_t)(233); + _curvea0[778] = _5149; + uint16_t _5150 = (uint16_t)(233); + _curvea0[779] = _5150; + uint16_t _5151 = (uint16_t)(233); + _curvea0[780] = _5151; + uint16_t _5152 = (uint16_t)(233); + _curvea0[781] = _5152; + uint16_t _5153 = (uint16_t)(233); + _curvea0[782] = _5153; + uint16_t _5154 = (uint16_t)(233); + _curvea0[783] = _5154; + uint16_t _5155 = (uint16_t)(233); + _curvea0[784] = _5155; + uint16_t _5156 = (uint16_t)(234); + _curvea0[785] = _5156; + uint16_t _5157 = (uint16_t)(234); + _curvea0[786] = _5157; + uint16_t _5158 = (uint16_t)(234); + _curvea0[787] = _5158; + uint16_t _5159 = (uint16_t)(234); + _curvea0[788] = _5159; + uint16_t _5160 = (uint16_t)(234); + _curvea0[789] = _5160; + uint16_t _5161 = (uint16_t)(234); + _curvea0[790] = _5161; + uint16_t _5162 = (uint16_t)(234); + _curvea0[791] = _5162; + uint16_t _5163 = (uint16_t)(234); + _curvea0[792] = _5163; + uint16_t _5164 = (uint16_t)(234); + _curvea0[793] = _5164; + uint16_t _5165 = (uint16_t)(235); + _curvea0[794] = _5165; + uint16_t _5166 = (uint16_t)(235); + _curvea0[795] = _5166; + uint16_t _5167 = (uint16_t)(235); + _curvea0[796] = _5167; + uint16_t _5168 = (uint16_t)(235); + _curvea0[797] = _5168; + uint16_t _5169 = (uint16_t)(235); + _curvea0[798] = _5169; + uint16_t _5170 = (uint16_t)(235); + _curvea0[799] = _5170; + uint16_t _5171 = (uint16_t)(235); + _curvea0[800] = _5171; + uint16_t _5172 = (uint16_t)(235); + _curvea0[801] = _5172; + uint16_t _5173 = (uint16_t)(235); + _curvea0[802] = _5173; + uint16_t _5174 = (uint16_t)(236); + _curvea0[803] = _5174; + uint16_t _5175 = (uint16_t)(236); + _curvea0[804] = _5175; + uint16_t _5176 = (uint16_t)(236); + _curvea0[805] = _5176; + uint16_t _5177 = (uint16_t)(236); + _curvea0[806] = _5177; + uint16_t _5178 = (uint16_t)(236); + _curvea0[807] = _5178; + uint16_t _5179 = (uint16_t)(236); + _curvea0[808] = _5179; + uint16_t _5180 = (uint16_t)(236); + _curvea0[809] = _5180; + uint16_t _5181 = (uint16_t)(236); + _curvea0[810] = _5181; + uint16_t _5182 = (uint16_t)(236); + _curvea0[811] = _5182; + uint16_t _5183 = (uint16_t)(237); + _curvea0[812] = _5183; + uint16_t _5184 = (uint16_t)(237); + _curvea0[813] = _5184; + uint16_t _5185 = (uint16_t)(237); + _curvea0[814] = _5185; + uint16_t _5186 = (uint16_t)(237); + _curvea0[815] = _5186; + uint16_t _5187 = (uint16_t)(237); + _curvea0[816] = _5187; + uint16_t _5188 = (uint16_t)(237); + _curvea0[817] = _5188; + uint16_t _5189 = (uint16_t)(237); + _curvea0[818] = _5189; + uint16_t _5190 = (uint16_t)(237); + _curvea0[819] = _5190; + uint16_t _5191 = (uint16_t)(237); + _curvea0[820] = _5191; + uint16_t _5192 = (uint16_t)(237); + _curvea0[821] = _5192; + uint16_t _5193 = (uint16_t)(238); + _curvea0[822] = _5193; + uint16_t _5194 = (uint16_t)(238); + _curvea0[823] = _5194; + uint16_t _5195 = (uint16_t)(238); + _curvea0[824] = _5195; + uint16_t _5196 = (uint16_t)(238); + _curvea0[825] = _5196; + uint16_t _5197 = (uint16_t)(238); + _curvea0[826] = _5197; + uint16_t _5198 = (uint16_t)(238); + _curvea0[827] = _5198; + uint16_t _5199 = (uint16_t)(238); + _curvea0[828] = _5199; + uint16_t _5200 = (uint16_t)(238); + _curvea0[829] = _5200; + uint16_t _5201 = (uint16_t)(238); + _curvea0[830] = _5201; + uint16_t _5202 = (uint16_t)(239); + _curvea0[831] = _5202; + uint16_t _5203 = (uint16_t)(239); + _curvea0[832] = _5203; + uint16_t _5204 = (uint16_t)(239); + _curvea0[833] = _5204; + uint16_t _5205 = (uint16_t)(239); + _curvea0[834] = _5205; + uint16_t _5206 = (uint16_t)(239); + _curvea0[835] = _5206; + uint16_t _5207 = (uint16_t)(239); + _curvea0[836] = _5207; + uint16_t _5208 = (uint16_t)(239); + _curvea0[837] = _5208; + uint16_t _5209 = (uint16_t)(239); + _curvea0[838] = _5209; + uint16_t _5210 = (uint16_t)(239); + _curvea0[839] = _5210; + uint16_t _5211 = (uint16_t)(239); + _curvea0[840] = _5211; + uint16_t _5212 = (uint16_t)(240); + _curvea0[841] = _5212; + uint16_t _5213 = (uint16_t)(240); + _curvea0[842] = _5213; + uint16_t _5214 = (uint16_t)(240); + _curvea0[843] = _5214; + uint16_t _5215 = (uint16_t)(240); + _curvea0[844] = _5215; + uint16_t _5216 = (uint16_t)(240); + _curvea0[845] = _5216; + uint16_t _5217 = (uint16_t)(240); + _curvea0[846] = _5217; + uint16_t _5218 = (uint16_t)(240); + _curvea0[847] = _5218; + uint16_t _5219 = (uint16_t)(240); + _curvea0[848] = _5219; + uint16_t _5220 = (uint16_t)(240); + _curvea0[849] = _5220; + uint16_t _5221 = (uint16_t)(240); + _curvea0[850] = _5221; + uint16_t _5222 = (uint16_t)(241); + _curvea0[851] = _5222; + uint16_t _5223 = (uint16_t)(241); + _curvea0[852] = _5223; + uint16_t _5224 = (uint16_t)(241); + _curvea0[853] = _5224; + uint16_t _5225 = (uint16_t)(241); + _curvea0[854] = _5225; + uint16_t _5226 = (uint16_t)(241); + _curvea0[855] = _5226; + uint16_t _5227 = (uint16_t)(241); + _curvea0[856] = _5227; + uint16_t _5228 = (uint16_t)(241); + _curvea0[857] = _5228; + uint16_t _5229 = (uint16_t)(241); + _curvea0[858] = _5229; + uint16_t _5230 = (uint16_t)(241); + _curvea0[859] = _5230; + uint16_t _5231 = (uint16_t)(241); + _curvea0[860] = _5231; + uint16_t _5232 = (uint16_t)(242); + _curvea0[861] = _5232; + uint16_t _5233 = (uint16_t)(242); + _curvea0[862] = _5233; + uint16_t _5234 = (uint16_t)(242); + _curvea0[863] = _5234; + uint16_t _5235 = (uint16_t)(242); + _curvea0[864] = _5235; + uint16_t _5236 = (uint16_t)(242); + _curvea0[865] = _5236; + uint16_t _5237 = (uint16_t)(242); + _curvea0[866] = _5237; + uint16_t _5238 = (uint16_t)(242); + _curvea0[867] = _5238; + uint16_t _5239 = (uint16_t)(242); + _curvea0[868] = _5239; + uint16_t _5240 = (uint16_t)(242); + _curvea0[869] = _5240; + uint16_t _5241 = (uint16_t)(242); + _curvea0[870] = _5241; + uint16_t _5242 = (uint16_t)(243); + _curvea0[871] = _5242; + uint16_t _5243 = (uint16_t)(243); + _curvea0[872] = _5243; + uint16_t _5244 = (uint16_t)(243); + _curvea0[873] = _5244; + uint16_t _5245 = (uint16_t)(243); + _curvea0[874] = _5245; + uint16_t _5246 = (uint16_t)(243); + _curvea0[875] = _5246; + uint16_t _5247 = (uint16_t)(243); + _curvea0[876] = _5247; + uint16_t _5248 = (uint16_t)(243); + _curvea0[877] = _5248; + uint16_t _5249 = (uint16_t)(243); + _curvea0[878] = _5249; + uint16_t _5250 = (uint16_t)(243); + _curvea0[879] = _5250; + uint16_t _5251 = (uint16_t)(243); + _curvea0[880] = _5251; + uint16_t _5252 = (uint16_t)(244); + _curvea0[881] = _5252; + uint16_t _5253 = (uint16_t)(244); + _curvea0[882] = _5253; + uint16_t _5254 = (uint16_t)(244); + _curvea0[883] = _5254; + uint16_t _5255 = (uint16_t)(244); + _curvea0[884] = _5255; + uint16_t _5256 = (uint16_t)(244); + _curvea0[885] = _5256; + uint16_t _5257 = (uint16_t)(244); + _curvea0[886] = _5257; + uint16_t _5258 = (uint16_t)(244); + _curvea0[887] = _5258; + uint16_t _5259 = (uint16_t)(244); + _curvea0[888] = _5259; + uint16_t _5260 = (uint16_t)(244); + _curvea0[889] = _5260; + uint16_t _5261 = (uint16_t)(244); + _curvea0[890] = _5261; + uint16_t _5262 = (uint16_t)(244); + _curvea0[891] = _5262; + uint16_t _5263 = (uint16_t)(245); + _curvea0[892] = _5263; + uint16_t _5264 = (uint16_t)(245); + _curvea0[893] = _5264; + uint16_t _5265 = (uint16_t)(245); + _curvea0[894] = _5265; + uint16_t _5266 = (uint16_t)(245); + _curvea0[895] = _5266; + uint16_t _5267 = (uint16_t)(245); + _curvea0[896] = _5267; + uint16_t _5268 = (uint16_t)(245); + _curvea0[897] = _5268; + uint16_t _5269 = (uint16_t)(245); + _curvea0[898] = _5269; + uint16_t _5270 = (uint16_t)(245); + _curvea0[899] = _5270; + uint16_t _5271 = (uint16_t)(245); + _curvea0[900] = _5271; + uint16_t _5272 = (uint16_t)(245); + _curvea0[901] = _5272; + uint16_t _5273 = (uint16_t)(245); + _curvea0[902] = _5273; + uint16_t _5274 = (uint16_t)(246); + _curvea0[903] = _5274; + uint16_t _5275 = (uint16_t)(246); + _curvea0[904] = _5275; + uint16_t _5276 = (uint16_t)(246); + _curvea0[905] = _5276; + uint16_t _5277 = (uint16_t)(246); + _curvea0[906] = _5277; + uint16_t _5278 = (uint16_t)(246); + _curvea0[907] = _5278; + uint16_t _5279 = (uint16_t)(246); + _curvea0[908] = _5279; + uint16_t _5280 = (uint16_t)(246); + _curvea0[909] = _5280; + uint16_t _5281 = (uint16_t)(246); + _curvea0[910] = _5281; + uint16_t _5282 = (uint16_t)(246); + _curvea0[911] = _5282; + uint16_t _5283 = (uint16_t)(246); + _curvea0[912] = _5283; + uint16_t _5284 = (uint16_t)(246); + _curvea0[913] = _5284; + uint16_t _5285 = (uint16_t)(247); + _curvea0[914] = _5285; + uint16_t _5286 = (uint16_t)(247); + _curvea0[915] = _5286; + uint16_t _5287 = (uint16_t)(247); + _curvea0[916] = _5287; + uint16_t _5288 = (uint16_t)(247); + _curvea0[917] = _5288; + uint16_t _5289 = (uint16_t)(247); + _curvea0[918] = _5289; + uint16_t _5290 = (uint16_t)(247); + _curvea0[919] = _5290; + uint16_t _5291 = (uint16_t)(247); + _curvea0[920] = _5291; + uint16_t _5292 = (uint16_t)(247); + _curvea0[921] = _5292; + uint16_t _5293 = (uint16_t)(247); + _curvea0[922] = _5293; + uint16_t _5294 = (uint16_t)(247); + _curvea0[923] = _5294; + uint16_t _5295 = (uint16_t)(247); + _curvea0[924] = _5295; + uint16_t _5296 = (uint16_t)(248); + _curvea0[925] = _5296; + uint16_t _5297 = (uint16_t)(248); + _curvea0[926] = _5297; + uint16_t _5298 = (uint16_t)(248); + _curvea0[927] = _5298; + uint16_t _5299 = (uint16_t)(248); + _curvea0[928] = _5299; + uint16_t _5300 = (uint16_t)(248); + _curvea0[929] = _5300; + uint16_t _5301 = (uint16_t)(248); + _curvea0[930] = _5301; + uint16_t _5302 = (uint16_t)(248); + _curvea0[931] = _5302; + uint16_t _5303 = (uint16_t)(248); + _curvea0[932] = _5303; + uint16_t _5304 = (uint16_t)(248); + _curvea0[933] = _5304; + uint16_t _5305 = (uint16_t)(248); + _curvea0[934] = _5305; + uint16_t _5306 = (uint16_t)(248); + _curvea0[935] = _5306; + uint16_t _5307 = (uint16_t)(249); + _curvea0[936] = _5307; + uint16_t _5308 = (uint16_t)(249); + _curvea0[937] = _5308; + uint16_t _5309 = (uint16_t)(249); + _curvea0[938] = _5309; + uint16_t _5310 = (uint16_t)(249); + _curvea0[939] = _5310; + uint16_t _5311 = (uint16_t)(249); + _curvea0[940] = _5311; + uint16_t _5312 = (uint16_t)(249); + _curvea0[941] = _5312; + uint16_t _5313 = (uint16_t)(249); + _curvea0[942] = _5313; + uint16_t _5314 = (uint16_t)(249); + _curvea0[943] = _5314; + uint16_t _5315 = (uint16_t)(249); + _curvea0[944] = _5315; + uint16_t _5316 = (uint16_t)(249); + _curvea0[945] = _5316; + uint16_t _5317 = (uint16_t)(249); + _curvea0[946] = _5317; + uint16_t _5318 = (uint16_t)(249); + _curvea0[947] = _5318; + uint16_t _5319 = (uint16_t)(250); + _curvea0[948] = _5319; + uint16_t _5320 = (uint16_t)(250); + _curvea0[949] = _5320; + uint16_t _5321 = (uint16_t)(250); + _curvea0[950] = _5321; + uint16_t _5322 = (uint16_t)(250); + _curvea0[951] = _5322; + uint16_t _5323 = (uint16_t)(250); + _curvea0[952] = _5323; + uint16_t _5324 = (uint16_t)(250); + _curvea0[953] = _5324; + uint16_t _5325 = (uint16_t)(250); + _curvea0[954] = _5325; + uint16_t _5326 = (uint16_t)(250); + _curvea0[955] = _5326; + uint16_t _5327 = (uint16_t)(250); + _curvea0[956] = _5327; + uint16_t _5328 = (uint16_t)(250); + _curvea0[957] = _5328; + uint16_t _5329 = (uint16_t)(250); + _curvea0[958] = _5329; + uint16_t _5330 = (uint16_t)(250); + _curvea0[959] = _5330; + uint16_t _5331 = (uint16_t)(251); + _curvea0[960] = _5331; + uint16_t _5332 = (uint16_t)(251); + _curvea0[961] = _5332; + uint16_t _5333 = (uint16_t)(251); + _curvea0[962] = _5333; + uint16_t _5334 = (uint16_t)(251); + _curvea0[963] = _5334; + uint16_t _5335 = (uint16_t)(251); + _curvea0[964] = _5335; + uint16_t _5336 = (uint16_t)(251); + _curvea0[965] = _5336; + uint16_t _5337 = (uint16_t)(251); + _curvea0[966] = _5337; + uint16_t _5338 = (uint16_t)(251); + _curvea0[967] = _5338; + uint16_t _5339 = (uint16_t)(251); + _curvea0[968] = _5339; + uint16_t _5340 = (uint16_t)(251); + _curvea0[969] = _5340; + uint16_t _5341 = (uint16_t)(251); + _curvea0[970] = _5341; + uint16_t _5342 = (uint16_t)(251); + _curvea0[971] = _5342; + uint16_t _5343 = (uint16_t)(252); + _curvea0[972] = _5343; + uint16_t _5344 = (uint16_t)(252); + _curvea0[973] = _5344; + uint16_t _5345 = (uint16_t)(252); + _curvea0[974] = _5345; + uint16_t _5346 = (uint16_t)(252); + _curvea0[975] = _5346; + uint16_t _5347 = (uint16_t)(252); + _curvea0[976] = _5347; + uint16_t _5348 = (uint16_t)(252); + _curvea0[977] = _5348; + uint16_t _5349 = (uint16_t)(252); + _curvea0[978] = _5349; + uint16_t _5350 = (uint16_t)(252); + _curvea0[979] = _5350; + uint16_t _5351 = (uint16_t)(252); + _curvea0[980] = _5351; + uint16_t _5352 = (uint16_t)(252); + _curvea0[981] = _5352; + uint16_t _5353 = (uint16_t)(252); + _curvea0[982] = _5353; + uint16_t _5354 = (uint16_t)(252); + _curvea0[983] = _5354; + uint16_t _5355 = (uint16_t)(252); + _curvea0[984] = _5355; + uint16_t _5356 = (uint16_t)(253); + _curvea0[985] = _5356; + uint16_t _5357 = (uint16_t)(253); + _curvea0[986] = _5357; + uint16_t _5358 = (uint16_t)(253); + _curvea0[987] = _5358; + uint16_t _5359 = (uint16_t)(253); + _curvea0[988] = _5359; + uint16_t _5360 = (uint16_t)(253); + _curvea0[989] = _5360; + uint16_t _5361 = (uint16_t)(253); + _curvea0[990] = _5361; + uint16_t _5362 = (uint16_t)(253); + _curvea0[991] = _5362; + uint16_t _5363 = (uint16_t)(253); + _curvea0[992] = _5363; + uint16_t _5364 = (uint16_t)(253); + _curvea0[993] = _5364; + uint16_t _5365 = (uint16_t)(253); + _curvea0[994] = _5365; + uint16_t _5366 = (uint16_t)(253); + _curvea0[995] = _5366; + uint16_t _5367 = (uint16_t)(253); + _curvea0[996] = _5367; + uint16_t _5368 = (uint16_t)(253); + _curvea0[997] = _5368; + uint16_t _5369 = (uint16_t)(254); + _curvea0[998] = _5369; + uint16_t _5370 = (uint16_t)(254); + _curvea0[999] = _5370; + uint16_t _5371 = (uint16_t)(254); + _curvea0[1000] = _5371; + uint16_t _5372 = (uint16_t)(254); + _curvea0[1001] = _5372; + uint16_t _5373 = (uint16_t)(254); + _curvea0[1002] = _5373; + uint16_t _5374 = (uint16_t)(254); + _curvea0[1003] = _5374; + uint16_t _5375 = (uint16_t)(254); + _curvea0[1004] = _5375; + uint16_t _5376 = (uint16_t)(254); + _curvea0[1005] = _5376; + uint16_t _5377 = (uint16_t)(254); + _curvea0[1006] = _5377; + uint16_t _5378 = (uint16_t)(254); + _curvea0[1007] = _5378; + uint16_t _5379 = (uint16_t)(254); + _curvea0[1008] = _5379; + uint16_t _5380 = (uint16_t)(254); + _curvea0[1009] = _5380; + uint16_t _5381 = (uint16_t)(254); + _curvea0[1010] = _5381; + uint16_t _5382 = (uint16_t)(255); + _curvea0[1011] = _5382; + uint16_t _5383 = (uint16_t)(255); + _curvea0[1012] = _5383; + uint16_t _5384 = (uint16_t)(255); + _curvea0[1013] = _5384; + uint16_t _5385 = (uint16_t)(255); + _curvea0[1014] = _5385; + uint16_t _5386 = (uint16_t)(255); + _curvea0[1015] = _5386; + uint16_t _5387 = (uint16_t)(255); + _curvea0[1016] = _5387; + uint16_t _5388 = (uint16_t)(255); + _curvea0[1017] = _5388; + uint16_t _5389 = (uint16_t)(255); + _curvea0[1018] = _5389; + uint16_t _5390 = (uint16_t)(255); + _curvea0[1019] = _5390; + uint16_t _5391 = (uint16_t)(255); + _curvea0[1020] = _5391; + uint16_t _5392 = (uint16_t)(255); + _curvea0[1021] = _5392; + uint16_t _5393 = (uint16_t)(255); + _curvea0[1022] = _5393; + uint16_t _5394 = (uint16_t)(255); + _curvea0[1023] = _5394; + + int16_t _5395 = (int16_t)(1023); + int16_t _5396 = min(_corrected_stencil_3, _5395); + int16_t _5397 = (int16_t)(0); + int16_t _5398 = max(_5396, _5397); + uint16_t _5399 = (uint16_t)(_5398); + int32_t _5400 = (int32_t)(_5399); + uint16_t _5401 = ((const uint16_t *)_curvea0)[_5400]; + return _5401; +} + +//store is: curved.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_3(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_4 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _5417 = (uint16_t)(0); + _curvea0[0] = _5417; + uint16_t _5418 = (uint16_t)(4); + _curvea0[1] = _5418; + uint16_t _5419 = (uint16_t)(7); + _curvea0[2] = _5419; + uint16_t _5420 = (uint16_t)(8); + _curvea0[3] = _5420; + uint16_t _5421 = (uint16_t)(10); + _curvea0[4] = _5421; + uint16_t _5422 = (uint16_t)(11); + _curvea0[5] = _5422; + uint16_t _5423 = (uint16_t)(12); + _curvea0[6] = _5423; + uint16_t _5424 = (uint16_t)(13); + _curvea0[7] = _5424; + uint16_t _5425 = (uint16_t)(14); + _curvea0[8] = _5425; + uint16_t _5426 = (uint16_t)(15); + _curvea0[9] = _5426; + uint16_t _5427 = (uint16_t)(16); + _curvea0[10] = _5427; + uint16_t _5428 = (uint16_t)(17); + _curvea0[11] = _5428; + uint16_t _5429 = (uint16_t)(18); + _curvea0[12] = _5429; + uint16_t _5430 = (uint16_t)(19); + _curvea0[13] = _5430; + uint16_t _5431 = (uint16_t)(20); + _curvea0[14] = _5431; + uint16_t _5432 = (uint16_t)(21); + _curvea0[15] = _5432; + uint16_t _5433 = (uint16_t)(22); + _curvea0[16] = _5433; + uint16_t _5434 = (uint16_t)(22); + _curvea0[17] = _5434; + uint16_t _5435 = (uint16_t)(23); + _curvea0[18] = _5435; + uint16_t _5436 = (uint16_t)(24); + _curvea0[19] = _5436; + uint16_t _5437 = (uint16_t)(25); + _curvea0[20] = _5437; + uint16_t _5438 = (uint16_t)(25); + _curvea0[21] = _5438; + uint16_t _5439 = (uint16_t)(26); + _curvea0[22] = _5439; + uint16_t _5440 = (uint16_t)(27); + _curvea0[23] = _5440; + uint16_t _5441 = (uint16_t)(27); + _curvea0[24] = _5441; + uint16_t _5442 = (uint16_t)(28); + _curvea0[25] = _5442; + uint16_t _5443 = (uint16_t)(29); + _curvea0[26] = _5443; + uint16_t _5444 = (uint16_t)(29); + _curvea0[27] = _5444; + uint16_t _5445 = (uint16_t)(30); + _curvea0[28] = _5445; + uint16_t _5446 = (uint16_t)(31); + _curvea0[29] = _5446; + uint16_t _5447 = (uint16_t)(31); + _curvea0[30] = _5447; + uint16_t _5448 = (uint16_t)(32); + _curvea0[31] = _5448; + uint16_t _5449 = (uint16_t)(33); + _curvea0[32] = _5449; + uint16_t _5450 = (uint16_t)(33); + _curvea0[33] = _5450; + uint16_t _5451 = (uint16_t)(34); + _curvea0[34] = _5451; + uint16_t _5452 = (uint16_t)(34); + _curvea0[35] = _5452; + uint16_t _5453 = (uint16_t)(35); + _curvea0[36] = _5453; + uint16_t _5454 = (uint16_t)(36); + _curvea0[37] = _5454; + uint16_t _5455 = (uint16_t)(36); + _curvea0[38] = _5455; + uint16_t _5456 = (uint16_t)(37); + _curvea0[39] = _5456; + uint16_t _5457 = (uint16_t)(37); + _curvea0[40] = _5457; + uint16_t _5458 = (uint16_t)(38); + _curvea0[41] = _5458; + uint16_t _5459 = (uint16_t)(39); + _curvea0[42] = _5459; + uint16_t _5460 = (uint16_t)(39); + _curvea0[43] = _5460; + uint16_t _5461 = (uint16_t)(40); + _curvea0[44] = _5461; + uint16_t _5462 = (uint16_t)(40); + _curvea0[45] = _5462; + uint16_t _5463 = (uint16_t)(41); + _curvea0[46] = _5463; + uint16_t _5464 = (uint16_t)(41); + _curvea0[47] = _5464; + uint16_t _5465 = (uint16_t)(42); + _curvea0[48] = _5465; + uint16_t _5466 = (uint16_t)(42); + _curvea0[49] = _5466; + uint16_t _5467 = (uint16_t)(43); + _curvea0[50] = _5467; + uint16_t _5468 = (uint16_t)(44); + _curvea0[51] = _5468; + uint16_t _5469 = (uint16_t)(44); + _curvea0[52] = _5469; + uint16_t _5470 = (uint16_t)(45); + _curvea0[53] = _5470; + uint16_t _5471 = (uint16_t)(45); + _curvea0[54] = _5471; + uint16_t _5472 = (uint16_t)(46); + _curvea0[55] = _5472; + uint16_t _5473 = (uint16_t)(46); + _curvea0[56] = _5473; + uint16_t _5474 = (uint16_t)(47); + _curvea0[57] = _5474; + uint16_t _5475 = (uint16_t)(47); + _curvea0[58] = _5475; + uint16_t _5476 = (uint16_t)(48); + _curvea0[59] = _5476; + uint16_t _5477 = (uint16_t)(48); + _curvea0[60] = _5477; + uint16_t _5478 = (uint16_t)(49); + _curvea0[61] = _5478; + uint16_t _5479 = (uint16_t)(49); + _curvea0[62] = _5479; + uint16_t _5480 = (uint16_t)(50); + _curvea0[63] = _5480; + uint16_t _5481 = (uint16_t)(50); + _curvea0[64] = _5481; + uint16_t _5482 = (uint16_t)(51); + _curvea0[65] = _5482; + uint16_t _5483 = (uint16_t)(51); + _curvea0[66] = _5483; + uint16_t _5484 = (uint16_t)(52); + _curvea0[67] = _5484; + uint16_t _5485 = (uint16_t)(52); + _curvea0[68] = _5485; + uint16_t _5486 = (uint16_t)(53); + _curvea0[69] = _5486; + uint16_t _5487 = (uint16_t)(53); + _curvea0[70] = _5487; + uint16_t _5488 = (uint16_t)(54); + _curvea0[71] = _5488; + uint16_t _5489 = (uint16_t)(54); + _curvea0[72] = _5489; + uint16_t _5490 = (uint16_t)(55); + _curvea0[73] = _5490; + uint16_t _5491 = (uint16_t)(55); + _curvea0[74] = _5491; + uint16_t _5492 = (uint16_t)(56); + _curvea0[75] = _5492; + uint16_t _5493 = (uint16_t)(56); + _curvea0[76] = _5493; + uint16_t _5494 = (uint16_t)(57); + _curvea0[77] = _5494; + uint16_t _5495 = (uint16_t)(57); + _curvea0[78] = _5495; + uint16_t _5496 = (uint16_t)(58); + _curvea0[79] = _5496; + uint16_t _5497 = (uint16_t)(58); + _curvea0[80] = _5497; + uint16_t _5498 = (uint16_t)(58); + _curvea0[81] = _5498; + uint16_t _5499 = (uint16_t)(59); + _curvea0[82] = _5499; + uint16_t _5500 = (uint16_t)(59); + _curvea0[83] = _5500; + uint16_t _5501 = (uint16_t)(60); + _curvea0[84] = _5501; + uint16_t _5502 = (uint16_t)(60); + _curvea0[85] = _5502; + uint16_t _5503 = (uint16_t)(61); + _curvea0[86] = _5503; + uint16_t _5504 = (uint16_t)(61); + _curvea0[87] = _5504; + uint16_t _5505 = (uint16_t)(62); + _curvea0[88] = _5505; + uint16_t _5506 = (uint16_t)(62); + _curvea0[89] = _5506; + uint16_t _5507 = (uint16_t)(63); + _curvea0[90] = _5507; + uint16_t _5508 = (uint16_t)(63); + _curvea0[91] = _5508; + uint16_t _5509 = (uint16_t)(64); + _curvea0[92] = _5509; + uint16_t _5510 = (uint16_t)(64); + _curvea0[93] = _5510; + uint16_t _5511 = (uint16_t)(64); + _curvea0[94] = _5511; + uint16_t _5512 = (uint16_t)(65); + _curvea0[95] = _5512; + uint16_t _5513 = (uint16_t)(65); + _curvea0[96] = _5513; + uint16_t _5514 = (uint16_t)(66); + _curvea0[97] = _5514; + uint16_t _5515 = (uint16_t)(66); + _curvea0[98] = _5515; + uint16_t _5516 = (uint16_t)(67); + _curvea0[99] = _5516; + uint16_t _5517 = (uint16_t)(67); + _curvea0[100] = _5517; + uint16_t _5518 = (uint16_t)(68); + _curvea0[101] = _5518; + uint16_t _5519 = (uint16_t)(68); + _curvea0[102] = _5519; + uint16_t _5520 = (uint16_t)(68); + _curvea0[103] = _5520; + uint16_t _5521 = (uint16_t)(69); + _curvea0[104] = _5521; + uint16_t _5522 = (uint16_t)(69); + _curvea0[105] = _5522; + uint16_t _5523 = (uint16_t)(70); + _curvea0[106] = _5523; + uint16_t _5524 = (uint16_t)(70); + _curvea0[107] = _5524; + uint16_t _5525 = (uint16_t)(71); + _curvea0[108] = _5525; + uint16_t _5526 = (uint16_t)(71); + _curvea0[109] = _5526; + uint16_t _5527 = (uint16_t)(71); + _curvea0[110] = _5527; + uint16_t _5528 = (uint16_t)(72); + _curvea0[111] = _5528; + uint16_t _5529 = (uint16_t)(72); + _curvea0[112] = _5529; + uint16_t _5530 = (uint16_t)(73); + _curvea0[113] = _5530; + uint16_t _5531 = (uint16_t)(73); + _curvea0[114] = _5531; + uint16_t _5532 = (uint16_t)(74); + _curvea0[115] = _5532; + uint16_t _5533 = (uint16_t)(74); + _curvea0[116] = _5533; + uint16_t _5534 = (uint16_t)(74); + _curvea0[117] = _5534; + uint16_t _5535 = (uint16_t)(75); + _curvea0[118] = _5535; + uint16_t _5536 = (uint16_t)(75); + _curvea0[119] = _5536; + uint16_t _5537 = (uint16_t)(76); + _curvea0[120] = _5537; + uint16_t _5538 = (uint16_t)(76); + _curvea0[121] = _5538; + uint16_t _5539 = (uint16_t)(77); + _curvea0[122] = _5539; + uint16_t _5540 = (uint16_t)(77); + _curvea0[123] = _5540; + uint16_t _5541 = (uint16_t)(77); + _curvea0[124] = _5541; + uint16_t _5542 = (uint16_t)(78); + _curvea0[125] = _5542; + uint16_t _5543 = (uint16_t)(78); + _curvea0[126] = _5543; + uint16_t _5544 = (uint16_t)(79); + _curvea0[127] = _5544; + uint16_t _5545 = (uint16_t)(79); + _curvea0[128] = _5545; + uint16_t _5546 = (uint16_t)(79); + _curvea0[129] = _5546; + uint16_t _5547 = (uint16_t)(80); + _curvea0[130] = _5547; + uint16_t _5548 = (uint16_t)(80); + _curvea0[131] = _5548; + uint16_t _5549 = (uint16_t)(81); + _curvea0[132] = _5549; + uint16_t _5550 = (uint16_t)(81); + _curvea0[133] = _5550; + uint16_t _5551 = (uint16_t)(82); + _curvea0[134] = _5551; + uint16_t _5552 = (uint16_t)(82); + _curvea0[135] = _5552; + uint16_t _5553 = (uint16_t)(82); + _curvea0[136] = _5553; + uint16_t _5554 = (uint16_t)(83); + _curvea0[137] = _5554; + uint16_t _5555 = (uint16_t)(83); + _curvea0[138] = _5555; + uint16_t _5556 = (uint16_t)(84); + _curvea0[139] = _5556; + uint16_t _5557 = (uint16_t)(84); + _curvea0[140] = _5557; + uint16_t _5558 = (uint16_t)(84); + _curvea0[141] = _5558; + uint16_t _5559 = (uint16_t)(85); + _curvea0[142] = _5559; + uint16_t _5560 = (uint16_t)(85); + _curvea0[143] = _5560; + uint16_t _5561 = (uint16_t)(86); + _curvea0[144] = _5561; + uint16_t _5562 = (uint16_t)(86); + _curvea0[145] = _5562; + uint16_t _5563 = (uint16_t)(86); + _curvea0[146] = _5563; + uint16_t _5564 = (uint16_t)(87); + _curvea0[147] = _5564; + uint16_t _5565 = (uint16_t)(87); + _curvea0[148] = _5565; + uint16_t _5566 = (uint16_t)(88); + _curvea0[149] = _5566; + uint16_t _5567 = (uint16_t)(88); + _curvea0[150] = _5567; + uint16_t _5568 = (uint16_t)(88); + _curvea0[151] = _5568; + uint16_t _5569 = (uint16_t)(89); + _curvea0[152] = _5569; + uint16_t _5570 = (uint16_t)(89); + _curvea0[153] = _5570; + uint16_t _5571 = (uint16_t)(90); + _curvea0[154] = _5571; + uint16_t _5572 = (uint16_t)(90); + _curvea0[155] = _5572; + uint16_t _5573 = (uint16_t)(90); + _curvea0[156] = _5573; + uint16_t _5574 = (uint16_t)(91); + _curvea0[157] = _5574; + uint16_t _5575 = (uint16_t)(91); + _curvea0[158] = _5575; + uint16_t _5576 = (uint16_t)(92); + _curvea0[159] = _5576; + uint16_t _5577 = (uint16_t)(92); + _curvea0[160] = _5577; + uint16_t _5578 = (uint16_t)(92); + _curvea0[161] = _5578; + uint16_t _5579 = (uint16_t)(93); + _curvea0[162] = _5579; + uint16_t _5580 = (uint16_t)(93); + _curvea0[163] = _5580; + uint16_t _5581 = (uint16_t)(93); + _curvea0[164] = _5581; + uint16_t _5582 = (uint16_t)(94); + _curvea0[165] = _5582; + uint16_t _5583 = (uint16_t)(94); + _curvea0[166] = _5583; + uint16_t _5584 = (uint16_t)(95); + _curvea0[167] = _5584; + uint16_t _5585 = (uint16_t)(95); + _curvea0[168] = _5585; + uint16_t _5586 = (uint16_t)(95); + _curvea0[169] = _5586; + uint16_t _5587 = (uint16_t)(96); + _curvea0[170] = _5587; + uint16_t _5588 = (uint16_t)(96); + _curvea0[171] = _5588; + uint16_t _5589 = (uint16_t)(97); + _curvea0[172] = _5589; + uint16_t _5590 = (uint16_t)(97); + _curvea0[173] = _5590; + uint16_t _5591 = (uint16_t)(97); + _curvea0[174] = _5591; + uint16_t _5592 = (uint16_t)(98); + _curvea0[175] = _5592; + uint16_t _5593 = (uint16_t)(98); + _curvea0[176] = _5593; + uint16_t _5594 = (uint16_t)(99); + _curvea0[177] = _5594; + uint16_t _5595 = (uint16_t)(99); + _curvea0[178] = _5595; + uint16_t _5596 = (uint16_t)(99); + _curvea0[179] = _5596; + uint16_t _5597 = (uint16_t)(100); + _curvea0[180] = _5597; + uint16_t _5598 = (uint16_t)(100); + _curvea0[181] = _5598; + uint16_t _5599 = (uint16_t)(100); + _curvea0[182] = _5599; + uint16_t _5600 = (uint16_t)(101); + _curvea0[183] = _5600; + uint16_t _5601 = (uint16_t)(101); + _curvea0[184] = _5601; + uint16_t _5602 = (uint16_t)(102); + _curvea0[185] = _5602; + uint16_t _5603 = (uint16_t)(102); + _curvea0[186] = _5603; + uint16_t _5604 = (uint16_t)(102); + _curvea0[187] = _5604; + uint16_t _5605 = (uint16_t)(103); + _curvea0[188] = _5605; + uint16_t _5606 = (uint16_t)(103); + _curvea0[189] = _5606; + uint16_t _5607 = (uint16_t)(103); + _curvea0[190] = _5607; + uint16_t _5608 = (uint16_t)(104); + _curvea0[191] = _5608; + uint16_t _5609 = (uint16_t)(104); + _curvea0[192] = _5609; + uint16_t _5610 = (uint16_t)(105); + _curvea0[193] = _5610; + uint16_t _5611 = (uint16_t)(105); + _curvea0[194] = _5611; + uint16_t _5612 = (uint16_t)(105); + _curvea0[195] = _5612; + uint16_t _5613 = (uint16_t)(106); + _curvea0[196] = _5613; + uint16_t _5614 = (uint16_t)(106); + _curvea0[197] = _5614; + uint16_t _5615 = (uint16_t)(106); + _curvea0[198] = _5615; + uint16_t _5616 = (uint16_t)(107); + _curvea0[199] = _5616; + uint16_t _5617 = (uint16_t)(107); + _curvea0[200] = _5617; + uint16_t _5618 = (uint16_t)(108); + _curvea0[201] = _5618; + uint16_t _5619 = (uint16_t)(108); + _curvea0[202] = _5619; + uint16_t _5620 = (uint16_t)(108); + _curvea0[203] = _5620; + uint16_t _5621 = (uint16_t)(109); + _curvea0[204] = _5621; + uint16_t _5622 = (uint16_t)(109); + _curvea0[205] = _5622; + uint16_t _5623 = (uint16_t)(109); + _curvea0[206] = _5623; + uint16_t _5624 = (uint16_t)(110); + _curvea0[207] = _5624; + uint16_t _5625 = (uint16_t)(110); + _curvea0[208] = _5625; + uint16_t _5626 = (uint16_t)(111); + _curvea0[209] = _5626; + uint16_t _5627 = (uint16_t)(111); + _curvea0[210] = _5627; + uint16_t _5628 = (uint16_t)(111); + _curvea0[211] = _5628; + uint16_t _5629 = (uint16_t)(112); + _curvea0[212] = _5629; + uint16_t _5630 = (uint16_t)(112); + _curvea0[213] = _5630; + uint16_t _5631 = (uint16_t)(112); + _curvea0[214] = _5631; + uint16_t _5632 = (uint16_t)(113); + _curvea0[215] = _5632; + uint16_t _5633 = (uint16_t)(113); + _curvea0[216] = _5633; + uint16_t _5634 = (uint16_t)(113); + _curvea0[217] = _5634; + uint16_t _5635 = (uint16_t)(114); + _curvea0[218] = _5635; + uint16_t _5636 = (uint16_t)(114); + _curvea0[219] = _5636; + uint16_t _5637 = (uint16_t)(115); + _curvea0[220] = _5637; + uint16_t _5638 = (uint16_t)(115); + _curvea0[221] = _5638; + uint16_t _5639 = (uint16_t)(115); + _curvea0[222] = _5639; + uint16_t _5640 = (uint16_t)(116); + _curvea0[223] = _5640; + uint16_t _5641 = (uint16_t)(116); + _curvea0[224] = _5641; + uint16_t _5642 = (uint16_t)(116); + _curvea0[225] = _5642; + uint16_t _5643 = (uint16_t)(117); + _curvea0[226] = _5643; + uint16_t _5644 = (uint16_t)(117); + _curvea0[227] = _5644; + uint16_t _5645 = (uint16_t)(117); + _curvea0[228] = _5645; + uint16_t _5646 = (uint16_t)(118); + _curvea0[229] = _5646; + uint16_t _5647 = (uint16_t)(118); + _curvea0[230] = _5647; + uint16_t _5648 = (uint16_t)(119); + _curvea0[231] = _5648; + uint16_t _5649 = (uint16_t)(119); + _curvea0[232] = _5649; + uint16_t _5650 = (uint16_t)(119); + _curvea0[233] = _5650; + uint16_t _5651 = (uint16_t)(120); + _curvea0[234] = _5651; + uint16_t _5652 = (uint16_t)(120); + _curvea0[235] = _5652; + uint16_t _5653 = (uint16_t)(120); + _curvea0[236] = _5653; + uint16_t _5654 = (uint16_t)(121); + _curvea0[237] = _5654; + uint16_t _5655 = (uint16_t)(121); + _curvea0[238] = _5655; + uint16_t _5656 = (uint16_t)(121); + _curvea0[239] = _5656; + uint16_t _5657 = (uint16_t)(122); + _curvea0[240] = _5657; + uint16_t _5658 = (uint16_t)(122); + _curvea0[241] = _5658; + uint16_t _5659 = (uint16_t)(123); + _curvea0[242] = _5659; + uint16_t _5660 = (uint16_t)(123); + _curvea0[243] = _5660; + uint16_t _5661 = (uint16_t)(123); + _curvea0[244] = _5661; + uint16_t _5662 = (uint16_t)(124); + _curvea0[245] = _5662; + uint16_t _5663 = (uint16_t)(124); + _curvea0[246] = _5663; + uint16_t _5664 = (uint16_t)(124); + _curvea0[247] = _5664; + uint16_t _5665 = (uint16_t)(125); + _curvea0[248] = _5665; + uint16_t _5666 = (uint16_t)(125); + _curvea0[249] = _5666; + uint16_t _5667 = (uint16_t)(125); + _curvea0[250] = _5667; + uint16_t _5668 = (uint16_t)(126); + _curvea0[251] = _5668; + uint16_t _5669 = (uint16_t)(126); + _curvea0[252] = _5669; + uint16_t _5670 = (uint16_t)(126); + _curvea0[253] = _5670; + uint16_t _5671 = (uint16_t)(127); + _curvea0[254] = _5671; + uint16_t _5672 = (uint16_t)(127); + _curvea0[255] = _5672; + uint16_t _5673 = (uint16_t)(128); + _curvea0[256] = _5673; + uint16_t _5674 = (uint16_t)(128); + _curvea0[257] = _5674; + uint16_t _5675 = (uint16_t)(128); + _curvea0[258] = _5675; + uint16_t _5676 = (uint16_t)(129); + _curvea0[259] = _5676; + uint16_t _5677 = (uint16_t)(129); + _curvea0[260] = _5677; + uint16_t _5678 = (uint16_t)(129); + _curvea0[261] = _5678; + uint16_t _5679 = (uint16_t)(130); + _curvea0[262] = _5679; + uint16_t _5680 = (uint16_t)(130); + _curvea0[263] = _5680; + uint16_t _5681 = (uint16_t)(130); + _curvea0[264] = _5681; + uint16_t _5682 = (uint16_t)(131); + _curvea0[265] = _5682; + uint16_t _5683 = (uint16_t)(131); + _curvea0[266] = _5683; + uint16_t _5684 = (uint16_t)(131); + _curvea0[267] = _5684; + uint16_t _5685 = (uint16_t)(132); + _curvea0[268] = _5685; + uint16_t _5686 = (uint16_t)(132); + _curvea0[269] = _5686; + uint16_t _5687 = (uint16_t)(132); + _curvea0[270] = _5687; + uint16_t _5688 = (uint16_t)(133); + _curvea0[271] = _5688; + uint16_t _5689 = (uint16_t)(133); + _curvea0[272] = _5689; + uint16_t _5690 = (uint16_t)(133); + _curvea0[273] = _5690; + uint16_t _5691 = (uint16_t)(134); + _curvea0[274] = _5691; + uint16_t _5692 = (uint16_t)(134); + _curvea0[275] = _5692; + uint16_t _5693 = (uint16_t)(134); + _curvea0[276] = _5693; + uint16_t _5694 = (uint16_t)(135); + _curvea0[277] = _5694; + uint16_t _5695 = (uint16_t)(135); + _curvea0[278] = _5695; + uint16_t _5696 = (uint16_t)(135); + _curvea0[279] = _5696; + uint16_t _5697 = (uint16_t)(136); + _curvea0[280] = _5697; + uint16_t _5698 = (uint16_t)(136); + _curvea0[281] = _5698; + uint16_t _5699 = (uint16_t)(136); + _curvea0[282] = _5699; + uint16_t _5700 = (uint16_t)(137); + _curvea0[283] = _5700; + uint16_t _5701 = (uint16_t)(137); + _curvea0[284] = _5701; + uint16_t _5702 = (uint16_t)(137); + _curvea0[285] = _5702; + uint16_t _5703 = (uint16_t)(138); + _curvea0[286] = _5703; + uint16_t _5704 = (uint16_t)(138); + _curvea0[287] = _5704; + uint16_t _5705 = (uint16_t)(138); + _curvea0[288] = _5705; + uint16_t _5706 = (uint16_t)(139); + _curvea0[289] = _5706; + uint16_t _5707 = (uint16_t)(139); + _curvea0[290] = _5707; + uint16_t _5708 = (uint16_t)(139); + _curvea0[291] = _5708; + uint16_t _5709 = (uint16_t)(140); + _curvea0[292] = _5709; + uint16_t _5710 = (uint16_t)(140); + _curvea0[293] = _5710; + uint16_t _5711 = (uint16_t)(140); + _curvea0[294] = _5711; + uint16_t _5712 = (uint16_t)(141); + _curvea0[295] = _5712; + uint16_t _5713 = (uint16_t)(141); + _curvea0[296] = _5713; + uint16_t _5714 = (uint16_t)(141); + _curvea0[297] = _5714; + uint16_t _5715 = (uint16_t)(141); + _curvea0[298] = _5715; + uint16_t _5716 = (uint16_t)(142); + _curvea0[299] = _5716; + uint16_t _5717 = (uint16_t)(142); + _curvea0[300] = _5717; + uint16_t _5718 = (uint16_t)(142); + _curvea0[301] = _5718; + uint16_t _5719 = (uint16_t)(143); + _curvea0[302] = _5719; + uint16_t _5720 = (uint16_t)(143); + _curvea0[303] = _5720; + uint16_t _5721 = (uint16_t)(143); + _curvea0[304] = _5721; + uint16_t _5722 = (uint16_t)(144); + _curvea0[305] = _5722; + uint16_t _5723 = (uint16_t)(144); + _curvea0[306] = _5723; + uint16_t _5724 = (uint16_t)(144); + _curvea0[307] = _5724; + uint16_t _5725 = (uint16_t)(145); + _curvea0[308] = _5725; + uint16_t _5726 = (uint16_t)(145); + _curvea0[309] = _5726; + uint16_t _5727 = (uint16_t)(145); + _curvea0[310] = _5727; + uint16_t _5728 = (uint16_t)(145); + _curvea0[311] = _5728; + uint16_t _5729 = (uint16_t)(146); + _curvea0[312] = _5729; + uint16_t _5730 = (uint16_t)(146); + _curvea0[313] = _5730; + uint16_t _5731 = (uint16_t)(146); + _curvea0[314] = _5731; + uint16_t _5732 = (uint16_t)(147); + _curvea0[315] = _5732; + uint16_t _5733 = (uint16_t)(147); + _curvea0[316] = _5733; + uint16_t _5734 = (uint16_t)(147); + _curvea0[317] = _5734; + uint16_t _5735 = (uint16_t)(148); + _curvea0[318] = _5735; + uint16_t _5736 = (uint16_t)(148); + _curvea0[319] = _5736; + uint16_t _5737 = (uint16_t)(148); + _curvea0[320] = _5737; + uint16_t _5738 = (uint16_t)(148); + _curvea0[321] = _5738; + uint16_t _5739 = (uint16_t)(149); + _curvea0[322] = _5739; + uint16_t _5740 = (uint16_t)(149); + _curvea0[323] = _5740; + uint16_t _5741 = (uint16_t)(149); + _curvea0[324] = _5741; + uint16_t _5742 = (uint16_t)(150); + _curvea0[325] = _5742; + uint16_t _5743 = (uint16_t)(150); + _curvea0[326] = _5743; + uint16_t _5744 = (uint16_t)(150); + _curvea0[327] = _5744; + uint16_t _5745 = (uint16_t)(150); + _curvea0[328] = _5745; + uint16_t _5746 = (uint16_t)(151); + _curvea0[329] = _5746; + uint16_t _5747 = (uint16_t)(151); + _curvea0[330] = _5747; + uint16_t _5748 = (uint16_t)(151); + _curvea0[331] = _5748; + uint16_t _5749 = (uint16_t)(152); + _curvea0[332] = _5749; + uint16_t _5750 = (uint16_t)(152); + _curvea0[333] = _5750; + uint16_t _5751 = (uint16_t)(152); + _curvea0[334] = _5751; + uint16_t _5752 = (uint16_t)(152); + _curvea0[335] = _5752; + uint16_t _5753 = (uint16_t)(153); + _curvea0[336] = _5753; + uint16_t _5754 = (uint16_t)(153); + _curvea0[337] = _5754; + uint16_t _5755 = (uint16_t)(153); + _curvea0[338] = _5755; + uint16_t _5756 = (uint16_t)(154); + _curvea0[339] = _5756; + uint16_t _5757 = (uint16_t)(154); + _curvea0[340] = _5757; + uint16_t _5758 = (uint16_t)(154); + _curvea0[341] = _5758; + uint16_t _5759 = (uint16_t)(154); + _curvea0[342] = _5759; + uint16_t _5760 = (uint16_t)(155); + _curvea0[343] = _5760; + uint16_t _5761 = (uint16_t)(155); + _curvea0[344] = _5761; + uint16_t _5762 = (uint16_t)(155); + _curvea0[345] = _5762; + uint16_t _5763 = (uint16_t)(156); + _curvea0[346] = _5763; + uint16_t _5764 = (uint16_t)(156); + _curvea0[347] = _5764; + uint16_t _5765 = (uint16_t)(156); + _curvea0[348] = _5765; + uint16_t _5766 = (uint16_t)(156); + _curvea0[349] = _5766; + uint16_t _5767 = (uint16_t)(157); + _curvea0[350] = _5767; + uint16_t _5768 = (uint16_t)(157); + _curvea0[351] = _5768; + uint16_t _5769 = (uint16_t)(157); + _curvea0[352] = _5769; + uint16_t _5770 = (uint16_t)(157); + _curvea0[353] = _5770; + uint16_t _5771 = (uint16_t)(158); + _curvea0[354] = _5771; + uint16_t _5772 = (uint16_t)(158); + _curvea0[355] = _5772; + uint16_t _5773 = (uint16_t)(158); + _curvea0[356] = _5773; + uint16_t _5774 = (uint16_t)(159); + _curvea0[357] = _5774; + uint16_t _5775 = (uint16_t)(159); + _curvea0[358] = _5775; + uint16_t _5776 = (uint16_t)(159); + _curvea0[359] = _5776; + uint16_t _5777 = (uint16_t)(159); + _curvea0[360] = _5777; + uint16_t _5778 = (uint16_t)(160); + _curvea0[361] = _5778; + uint16_t _5779 = (uint16_t)(160); + _curvea0[362] = _5779; + uint16_t _5780 = (uint16_t)(160); + _curvea0[363] = _5780; + uint16_t _5781 = (uint16_t)(160); + _curvea0[364] = _5781; + uint16_t _5782 = (uint16_t)(161); + _curvea0[365] = _5782; + uint16_t _5783 = (uint16_t)(161); + _curvea0[366] = _5783; + uint16_t _5784 = (uint16_t)(161); + _curvea0[367] = _5784; + uint16_t _5785 = (uint16_t)(161); + _curvea0[368] = _5785; + uint16_t _5786 = (uint16_t)(162); + _curvea0[369] = _5786; + uint16_t _5787 = (uint16_t)(162); + _curvea0[370] = _5787; + uint16_t _5788 = (uint16_t)(162); + _curvea0[371] = _5788; + uint16_t _5789 = (uint16_t)(162); + _curvea0[372] = _5789; + uint16_t _5790 = (uint16_t)(163); + _curvea0[373] = _5790; + uint16_t _5791 = (uint16_t)(163); + _curvea0[374] = _5791; + uint16_t _5792 = (uint16_t)(163); + _curvea0[375] = _5792; + uint16_t _5793 = (uint16_t)(163); + _curvea0[376] = _5793; + uint16_t _5794 = (uint16_t)(164); + _curvea0[377] = _5794; + uint16_t _5795 = (uint16_t)(164); + _curvea0[378] = _5795; + uint16_t _5796 = (uint16_t)(164); + _curvea0[379] = _5796; + uint16_t _5797 = (uint16_t)(164); + _curvea0[380] = _5797; + uint16_t _5798 = (uint16_t)(165); + _curvea0[381] = _5798; + uint16_t _5799 = (uint16_t)(165); + _curvea0[382] = _5799; + uint16_t _5800 = (uint16_t)(165); + _curvea0[383] = _5800; + uint16_t _5801 = (uint16_t)(166); + _curvea0[384] = _5801; + uint16_t _5802 = (uint16_t)(166); + _curvea0[385] = _5802; + uint16_t _5803 = (uint16_t)(166); + _curvea0[386] = _5803; + uint16_t _5804 = (uint16_t)(166); + _curvea0[387] = _5804; + uint16_t _5805 = (uint16_t)(167); + _curvea0[388] = _5805; + uint16_t _5806 = (uint16_t)(167); + _curvea0[389] = _5806; + uint16_t _5807 = (uint16_t)(167); + _curvea0[390] = _5807; + uint16_t _5808 = (uint16_t)(167); + _curvea0[391] = _5808; + uint16_t _5809 = (uint16_t)(167); + _curvea0[392] = _5809; + uint16_t _5810 = (uint16_t)(168); + _curvea0[393] = _5810; + uint16_t _5811 = (uint16_t)(168); + _curvea0[394] = _5811; + uint16_t _5812 = (uint16_t)(168); + _curvea0[395] = _5812; + uint16_t _5813 = (uint16_t)(168); + _curvea0[396] = _5813; + uint16_t _5814 = (uint16_t)(169); + _curvea0[397] = _5814; + uint16_t _5815 = (uint16_t)(169); + _curvea0[398] = _5815; + uint16_t _5816 = (uint16_t)(169); + _curvea0[399] = _5816; + uint16_t _5817 = (uint16_t)(169); + _curvea0[400] = _5817; + uint16_t _5818 = (uint16_t)(170); + _curvea0[401] = _5818; + uint16_t _5819 = (uint16_t)(170); + _curvea0[402] = _5819; + uint16_t _5820 = (uint16_t)(170); + _curvea0[403] = _5820; + uint16_t _5821 = (uint16_t)(170); + _curvea0[404] = _5821; + uint16_t _5822 = (uint16_t)(171); + _curvea0[405] = _5822; + uint16_t _5823 = (uint16_t)(171); + _curvea0[406] = _5823; + uint16_t _5824 = (uint16_t)(171); + _curvea0[407] = _5824; + uint16_t _5825 = (uint16_t)(171); + _curvea0[408] = _5825; + uint16_t _5826 = (uint16_t)(172); + _curvea0[409] = _5826; + uint16_t _5827 = (uint16_t)(172); + _curvea0[410] = _5827; + uint16_t _5828 = (uint16_t)(172); + _curvea0[411] = _5828; + uint16_t _5829 = (uint16_t)(172); + _curvea0[412] = _5829; + uint16_t _5830 = (uint16_t)(173); + _curvea0[413] = _5830; + uint16_t _5831 = (uint16_t)(173); + _curvea0[414] = _5831; + uint16_t _5832 = (uint16_t)(173); + _curvea0[415] = _5832; + uint16_t _5833 = (uint16_t)(173); + _curvea0[416] = _5833; + uint16_t _5834 = (uint16_t)(173); + _curvea0[417] = _5834; + uint16_t _5835 = (uint16_t)(174); + _curvea0[418] = _5835; + uint16_t _5836 = (uint16_t)(174); + _curvea0[419] = _5836; + uint16_t _5837 = (uint16_t)(174); + _curvea0[420] = _5837; + uint16_t _5838 = (uint16_t)(174); + _curvea0[421] = _5838; + uint16_t _5839 = (uint16_t)(175); + _curvea0[422] = _5839; + uint16_t _5840 = (uint16_t)(175); + _curvea0[423] = _5840; + uint16_t _5841 = (uint16_t)(175); + _curvea0[424] = _5841; + uint16_t _5842 = (uint16_t)(175); + _curvea0[425] = _5842; + uint16_t _5843 = (uint16_t)(176); + _curvea0[426] = _5843; + uint16_t _5844 = (uint16_t)(176); + _curvea0[427] = _5844; + uint16_t _5845 = (uint16_t)(176); + _curvea0[428] = _5845; + uint16_t _5846 = (uint16_t)(176); + _curvea0[429] = _5846; + uint16_t _5847 = (uint16_t)(176); + _curvea0[430] = _5847; + uint16_t _5848 = (uint16_t)(177); + _curvea0[431] = _5848; + uint16_t _5849 = (uint16_t)(177); + _curvea0[432] = _5849; + uint16_t _5850 = (uint16_t)(177); + _curvea0[433] = _5850; + uint16_t _5851 = (uint16_t)(177); + _curvea0[434] = _5851; + uint16_t _5852 = (uint16_t)(178); + _curvea0[435] = _5852; + uint16_t _5853 = (uint16_t)(178); + _curvea0[436] = _5853; + uint16_t _5854 = (uint16_t)(178); + _curvea0[437] = _5854; + uint16_t _5855 = (uint16_t)(178); + _curvea0[438] = _5855; + uint16_t _5856 = (uint16_t)(178); + _curvea0[439] = _5856; + uint16_t _5857 = (uint16_t)(179); + _curvea0[440] = _5857; + uint16_t _5858 = (uint16_t)(179); + _curvea0[441] = _5858; + uint16_t _5859 = (uint16_t)(179); + _curvea0[442] = _5859; + uint16_t _5860 = (uint16_t)(179); + _curvea0[443] = _5860; + uint16_t _5861 = (uint16_t)(180); + _curvea0[444] = _5861; + uint16_t _5862 = (uint16_t)(180); + _curvea0[445] = _5862; + uint16_t _5863 = (uint16_t)(180); + _curvea0[446] = _5863; + uint16_t _5864 = (uint16_t)(180); + _curvea0[447] = _5864; + uint16_t _5865 = (uint16_t)(180); + _curvea0[448] = _5865; + uint16_t _5866 = (uint16_t)(181); + _curvea0[449] = _5866; + uint16_t _5867 = (uint16_t)(181); + _curvea0[450] = _5867; + uint16_t _5868 = (uint16_t)(181); + _curvea0[451] = _5868; + uint16_t _5869 = (uint16_t)(181); + _curvea0[452] = _5869; + uint16_t _5870 = (uint16_t)(181); + _curvea0[453] = _5870; + uint16_t _5871 = (uint16_t)(182); + _curvea0[454] = _5871; + uint16_t _5872 = (uint16_t)(182); + _curvea0[455] = _5872; + uint16_t _5873 = (uint16_t)(182); + _curvea0[456] = _5873; + uint16_t _5874 = (uint16_t)(182); + _curvea0[457] = _5874; + uint16_t _5875 = (uint16_t)(183); + _curvea0[458] = _5875; + uint16_t _5876 = (uint16_t)(183); + _curvea0[459] = _5876; + uint16_t _5877 = (uint16_t)(183); + _curvea0[460] = _5877; + uint16_t _5878 = (uint16_t)(183); + _curvea0[461] = _5878; + uint16_t _5879 = (uint16_t)(183); + _curvea0[462] = _5879; + uint16_t _5880 = (uint16_t)(184); + _curvea0[463] = _5880; + uint16_t _5881 = (uint16_t)(184); + _curvea0[464] = _5881; + uint16_t _5882 = (uint16_t)(184); + _curvea0[465] = _5882; + uint16_t _5883 = (uint16_t)(184); + _curvea0[466] = _5883; + uint16_t _5884 = (uint16_t)(184); + _curvea0[467] = _5884; + uint16_t _5885 = (uint16_t)(185); + _curvea0[468] = _5885; + uint16_t _5886 = (uint16_t)(185); + _curvea0[469] = _5886; + uint16_t _5887 = (uint16_t)(185); + _curvea0[470] = _5887; + uint16_t _5888 = (uint16_t)(185); + _curvea0[471] = _5888; + uint16_t _5889 = (uint16_t)(185); + _curvea0[472] = _5889; + uint16_t _5890 = (uint16_t)(186); + _curvea0[473] = _5890; + uint16_t _5891 = (uint16_t)(186); + _curvea0[474] = _5891; + uint16_t _5892 = (uint16_t)(186); + _curvea0[475] = _5892; + uint16_t _5893 = (uint16_t)(186); + _curvea0[476] = _5893; + uint16_t _5894 = (uint16_t)(187); + _curvea0[477] = _5894; + uint16_t _5895 = (uint16_t)(187); + _curvea0[478] = _5895; + uint16_t _5896 = (uint16_t)(187); + _curvea0[479] = _5896; + uint16_t _5897 = (uint16_t)(187); + _curvea0[480] = _5897; + uint16_t _5898 = (uint16_t)(187); + _curvea0[481] = _5898; + uint16_t _5899 = (uint16_t)(188); + _curvea0[482] = _5899; + uint16_t _5900 = (uint16_t)(188); + _curvea0[483] = _5900; + uint16_t _5901 = (uint16_t)(188); + _curvea0[484] = _5901; + uint16_t _5902 = (uint16_t)(188); + _curvea0[485] = _5902; + uint16_t _5903 = (uint16_t)(188); + _curvea0[486] = _5903; + uint16_t _5904 = (uint16_t)(189); + _curvea0[487] = _5904; + uint16_t _5905 = (uint16_t)(189); + _curvea0[488] = _5905; + uint16_t _5906 = (uint16_t)(189); + _curvea0[489] = _5906; + uint16_t _5907 = (uint16_t)(189); + _curvea0[490] = _5907; + uint16_t _5908 = (uint16_t)(189); + _curvea0[491] = _5908; + uint16_t _5909 = (uint16_t)(190); + _curvea0[492] = _5909; + uint16_t _5910 = (uint16_t)(190); + _curvea0[493] = _5910; + uint16_t _5911 = (uint16_t)(190); + _curvea0[494] = _5911; + uint16_t _5912 = (uint16_t)(190); + _curvea0[495] = _5912; + uint16_t _5913 = (uint16_t)(190); + _curvea0[496] = _5913; + uint16_t _5914 = (uint16_t)(190); + _curvea0[497] = _5914; + uint16_t _5915 = (uint16_t)(191); + _curvea0[498] = _5915; + uint16_t _5916 = (uint16_t)(191); + _curvea0[499] = _5916; + uint16_t _5917 = (uint16_t)(191); + _curvea0[500] = _5917; + uint16_t _5918 = (uint16_t)(191); + _curvea0[501] = _5918; + uint16_t _5919 = (uint16_t)(191); + _curvea0[502] = _5919; + uint16_t _5920 = (uint16_t)(192); + _curvea0[503] = _5920; + uint16_t _5921 = (uint16_t)(192); + _curvea0[504] = _5921; + uint16_t _5922 = (uint16_t)(192); + _curvea0[505] = _5922; + uint16_t _5923 = (uint16_t)(192); + _curvea0[506] = _5923; + uint16_t _5924 = (uint16_t)(192); + _curvea0[507] = _5924; + uint16_t _5925 = (uint16_t)(193); + _curvea0[508] = _5925; + uint16_t _5926 = (uint16_t)(193); + _curvea0[509] = _5926; + uint16_t _5927 = (uint16_t)(193); + _curvea0[510] = _5927; + uint16_t _5928 = (uint16_t)(193); + _curvea0[511] = _5928; + uint16_t _5929 = (uint16_t)(193); + _curvea0[512] = _5929; + uint16_t _5930 = (uint16_t)(194); + _curvea0[513] = _5930; + uint16_t _5931 = (uint16_t)(194); + _curvea0[514] = _5931; + uint16_t _5932 = (uint16_t)(194); + _curvea0[515] = _5932; + uint16_t _5933 = (uint16_t)(194); + _curvea0[516] = _5933; + uint16_t _5934 = (uint16_t)(194); + _curvea0[517] = _5934; + uint16_t _5935 = (uint16_t)(195); + _curvea0[518] = _5935; + uint16_t _5936 = (uint16_t)(195); + _curvea0[519] = _5936; + uint16_t _5937 = (uint16_t)(195); + _curvea0[520] = _5937; + uint16_t _5938 = (uint16_t)(195); + _curvea0[521] = _5938; + uint16_t _5939 = (uint16_t)(195); + _curvea0[522] = _5939; + uint16_t _5940 = (uint16_t)(195); + _curvea0[523] = _5940; + uint16_t _5941 = (uint16_t)(196); + _curvea0[524] = _5941; + uint16_t _5942 = (uint16_t)(196); + _curvea0[525] = _5942; + uint16_t _5943 = (uint16_t)(196); + _curvea0[526] = _5943; + uint16_t _5944 = (uint16_t)(196); + _curvea0[527] = _5944; + uint16_t _5945 = (uint16_t)(196); + _curvea0[528] = _5945; + uint16_t _5946 = (uint16_t)(197); + _curvea0[529] = _5946; + uint16_t _5947 = (uint16_t)(197); + _curvea0[530] = _5947; + uint16_t _5948 = (uint16_t)(197); + _curvea0[531] = _5948; + uint16_t _5949 = (uint16_t)(197); + _curvea0[532] = _5949; + uint16_t _5950 = (uint16_t)(197); + _curvea0[533] = _5950; + uint16_t _5951 = (uint16_t)(197); + _curvea0[534] = _5951; + uint16_t _5952 = (uint16_t)(198); + _curvea0[535] = _5952; + uint16_t _5953 = (uint16_t)(198); + _curvea0[536] = _5953; + uint16_t _5954 = (uint16_t)(198); + _curvea0[537] = _5954; + uint16_t _5955 = (uint16_t)(198); + _curvea0[538] = _5955; + uint16_t _5956 = (uint16_t)(198); + _curvea0[539] = _5956; + uint16_t _5957 = (uint16_t)(199); + _curvea0[540] = _5957; + uint16_t _5958 = (uint16_t)(199); + _curvea0[541] = _5958; + uint16_t _5959 = (uint16_t)(199); + _curvea0[542] = _5959; + uint16_t _5960 = (uint16_t)(199); + _curvea0[543] = _5960; + uint16_t _5961 = (uint16_t)(199); + _curvea0[544] = _5961; + uint16_t _5962 = (uint16_t)(199); + _curvea0[545] = _5962; + uint16_t _5963 = (uint16_t)(200); + _curvea0[546] = _5963; + uint16_t _5964 = (uint16_t)(200); + _curvea0[547] = _5964; + uint16_t _5965 = (uint16_t)(200); + _curvea0[548] = _5965; + uint16_t _5966 = (uint16_t)(200); + _curvea0[549] = _5966; + uint16_t _5967 = (uint16_t)(200); + _curvea0[550] = _5967; + uint16_t _5968 = (uint16_t)(200); + _curvea0[551] = _5968; + uint16_t _5969 = (uint16_t)(201); + _curvea0[552] = _5969; + uint16_t _5970 = (uint16_t)(201); + _curvea0[553] = _5970; + uint16_t _5971 = (uint16_t)(201); + _curvea0[554] = _5971; + uint16_t _5972 = (uint16_t)(201); + _curvea0[555] = _5972; + uint16_t _5973 = (uint16_t)(201); + _curvea0[556] = _5973; + uint16_t _5974 = (uint16_t)(202); + _curvea0[557] = _5974; + uint16_t _5975 = (uint16_t)(202); + _curvea0[558] = _5975; + uint16_t _5976 = (uint16_t)(202); + _curvea0[559] = _5976; + uint16_t _5977 = (uint16_t)(202); + _curvea0[560] = _5977; + uint16_t _5978 = (uint16_t)(202); + _curvea0[561] = _5978; + uint16_t _5979 = (uint16_t)(202); + _curvea0[562] = _5979; + uint16_t _5980 = (uint16_t)(203); + _curvea0[563] = _5980; + uint16_t _5981 = (uint16_t)(203); + _curvea0[564] = _5981; + uint16_t _5982 = (uint16_t)(203); + _curvea0[565] = _5982; + uint16_t _5983 = (uint16_t)(203); + _curvea0[566] = _5983; + uint16_t _5984 = (uint16_t)(203); + _curvea0[567] = _5984; + uint16_t _5985 = (uint16_t)(203); + _curvea0[568] = _5985; + uint16_t _5986 = (uint16_t)(204); + _curvea0[569] = _5986; + uint16_t _5987 = (uint16_t)(204); + _curvea0[570] = _5987; + uint16_t _5988 = (uint16_t)(204); + _curvea0[571] = _5988; + uint16_t _5989 = (uint16_t)(204); + _curvea0[572] = _5989; + uint16_t _5990 = (uint16_t)(204); + _curvea0[573] = _5990; + uint16_t _5991 = (uint16_t)(204); + _curvea0[574] = _5991; + uint16_t _5992 = (uint16_t)(205); + _curvea0[575] = _5992; + uint16_t _5993 = (uint16_t)(205); + _curvea0[576] = _5993; + uint16_t _5994 = (uint16_t)(205); + _curvea0[577] = _5994; + uint16_t _5995 = (uint16_t)(205); + _curvea0[578] = _5995; + uint16_t _5996 = (uint16_t)(205); + _curvea0[579] = _5996; + uint16_t _5997 = (uint16_t)(205); + _curvea0[580] = _5997; + uint16_t _5998 = (uint16_t)(206); + _curvea0[581] = _5998; + uint16_t _5999 = (uint16_t)(206); + _curvea0[582] = _5999; + uint16_t _6000 = (uint16_t)(206); + _curvea0[583] = _6000; + uint16_t _6001 = (uint16_t)(206); + _curvea0[584] = _6001; + uint16_t _6002 = (uint16_t)(206); + _curvea0[585] = _6002; + uint16_t _6003 = (uint16_t)(206); + _curvea0[586] = _6003; + uint16_t _6004 = (uint16_t)(207); + _curvea0[587] = _6004; + uint16_t _6005 = (uint16_t)(207); + _curvea0[588] = _6005; + uint16_t _6006 = (uint16_t)(207); + _curvea0[589] = _6006; + uint16_t _6007 = (uint16_t)(207); + _curvea0[590] = _6007; + uint16_t _6008 = (uint16_t)(207); + _curvea0[591] = _6008; + uint16_t _6009 = (uint16_t)(207); + _curvea0[592] = _6009; + uint16_t _6010 = (uint16_t)(208); + _curvea0[593] = _6010; + uint16_t _6011 = (uint16_t)(208); + _curvea0[594] = _6011; + uint16_t _6012 = (uint16_t)(208); + _curvea0[595] = _6012; + uint16_t _6013 = (uint16_t)(208); + _curvea0[596] = _6013; + uint16_t _6014 = (uint16_t)(208); + _curvea0[597] = _6014; + uint16_t _6015 = (uint16_t)(208); + _curvea0[598] = _6015; + uint16_t _6016 = (uint16_t)(209); + _curvea0[599] = _6016; + uint16_t _6017 = (uint16_t)(209); + _curvea0[600] = _6017; + uint16_t _6018 = (uint16_t)(209); + _curvea0[601] = _6018; + uint16_t _6019 = (uint16_t)(209); + _curvea0[602] = _6019; + uint16_t _6020 = (uint16_t)(209); + _curvea0[603] = _6020; + uint16_t _6021 = (uint16_t)(209); + _curvea0[604] = _6021; + uint16_t _6022 = (uint16_t)(209); + _curvea0[605] = _6022; + uint16_t _6023 = (uint16_t)(210); + _curvea0[606] = _6023; + uint16_t _6024 = (uint16_t)(210); + _curvea0[607] = _6024; + uint16_t _6025 = (uint16_t)(210); + _curvea0[608] = _6025; + uint16_t _6026 = (uint16_t)(210); + _curvea0[609] = _6026; + uint16_t _6027 = (uint16_t)(210); + _curvea0[610] = _6027; + uint16_t _6028 = (uint16_t)(210); + _curvea0[611] = _6028; + uint16_t _6029 = (uint16_t)(211); + _curvea0[612] = _6029; + uint16_t _6030 = (uint16_t)(211); + _curvea0[613] = _6030; + uint16_t _6031 = (uint16_t)(211); + _curvea0[614] = _6031; + uint16_t _6032 = (uint16_t)(211); + _curvea0[615] = _6032; + uint16_t _6033 = (uint16_t)(211); + _curvea0[616] = _6033; + uint16_t _6034 = (uint16_t)(211); + _curvea0[617] = _6034; + uint16_t _6035 = (uint16_t)(211); + _curvea0[618] = _6035; + uint16_t _6036 = (uint16_t)(212); + _curvea0[619] = _6036; + uint16_t _6037 = (uint16_t)(212); + _curvea0[620] = _6037; + uint16_t _6038 = (uint16_t)(212); + _curvea0[621] = _6038; + uint16_t _6039 = (uint16_t)(212); + _curvea0[622] = _6039; + uint16_t _6040 = (uint16_t)(212); + _curvea0[623] = _6040; + uint16_t _6041 = (uint16_t)(212); + _curvea0[624] = _6041; + uint16_t _6042 = (uint16_t)(213); + _curvea0[625] = _6042; + uint16_t _6043 = (uint16_t)(213); + _curvea0[626] = _6043; + uint16_t _6044 = (uint16_t)(213); + _curvea0[627] = _6044; + uint16_t _6045 = (uint16_t)(213); + _curvea0[628] = _6045; + uint16_t _6046 = (uint16_t)(213); + _curvea0[629] = _6046; + uint16_t _6047 = (uint16_t)(213); + _curvea0[630] = _6047; + uint16_t _6048 = (uint16_t)(213); + _curvea0[631] = _6048; + uint16_t _6049 = (uint16_t)(214); + _curvea0[632] = _6049; + uint16_t _6050 = (uint16_t)(214); + _curvea0[633] = _6050; + uint16_t _6051 = (uint16_t)(214); + _curvea0[634] = _6051; + uint16_t _6052 = (uint16_t)(214); + _curvea0[635] = _6052; + uint16_t _6053 = (uint16_t)(214); + _curvea0[636] = _6053; + uint16_t _6054 = (uint16_t)(214); + _curvea0[637] = _6054; + uint16_t _6055 = (uint16_t)(214); + _curvea0[638] = _6055; + uint16_t _6056 = (uint16_t)(215); + _curvea0[639] = _6056; + uint16_t _6057 = (uint16_t)(215); + _curvea0[640] = _6057; + uint16_t _6058 = (uint16_t)(215); + _curvea0[641] = _6058; + uint16_t _6059 = (uint16_t)(215); + _curvea0[642] = _6059; + uint16_t _6060 = (uint16_t)(215); + _curvea0[643] = _6060; + uint16_t _6061 = (uint16_t)(215); + _curvea0[644] = _6061; + uint16_t _6062 = (uint16_t)(216); + _curvea0[645] = _6062; + uint16_t _6063 = (uint16_t)(216); + _curvea0[646] = _6063; + uint16_t _6064 = (uint16_t)(216); + _curvea0[647] = _6064; + uint16_t _6065 = (uint16_t)(216); + _curvea0[648] = _6065; + uint16_t _6066 = (uint16_t)(216); + _curvea0[649] = _6066; + uint16_t _6067 = (uint16_t)(216); + _curvea0[650] = _6067; + uint16_t _6068 = (uint16_t)(216); + _curvea0[651] = _6068; + uint16_t _6069 = (uint16_t)(217); + _curvea0[652] = _6069; + uint16_t _6070 = (uint16_t)(217); + _curvea0[653] = _6070; + uint16_t _6071 = (uint16_t)(217); + _curvea0[654] = _6071; + uint16_t _6072 = (uint16_t)(217); + _curvea0[655] = _6072; + uint16_t _6073 = (uint16_t)(217); + _curvea0[656] = _6073; + uint16_t _6074 = (uint16_t)(217); + _curvea0[657] = _6074; + uint16_t _6075 = (uint16_t)(217); + _curvea0[658] = _6075; + uint16_t _6076 = (uint16_t)(218); + _curvea0[659] = _6076; + uint16_t _6077 = (uint16_t)(218); + _curvea0[660] = _6077; + uint16_t _6078 = (uint16_t)(218); + _curvea0[661] = _6078; + uint16_t _6079 = (uint16_t)(218); + _curvea0[662] = _6079; + uint16_t _6080 = (uint16_t)(218); + _curvea0[663] = _6080; + uint16_t _6081 = (uint16_t)(218); + _curvea0[664] = _6081; + uint16_t _6082 = (uint16_t)(218); + _curvea0[665] = _6082; + uint16_t _6083 = (uint16_t)(219); + _curvea0[666] = _6083; + uint16_t _6084 = (uint16_t)(219); + _curvea0[667] = _6084; + uint16_t _6085 = (uint16_t)(219); + _curvea0[668] = _6085; + uint16_t _6086 = (uint16_t)(219); + _curvea0[669] = _6086; + uint16_t _6087 = (uint16_t)(219); + _curvea0[670] = _6087; + uint16_t _6088 = (uint16_t)(219); + _curvea0[671] = _6088; + uint16_t _6089 = (uint16_t)(219); + _curvea0[672] = _6089; + uint16_t _6090 = (uint16_t)(220); + _curvea0[673] = _6090; + uint16_t _6091 = (uint16_t)(220); + _curvea0[674] = _6091; + uint16_t _6092 = (uint16_t)(220); + _curvea0[675] = _6092; + uint16_t _6093 = (uint16_t)(220); + _curvea0[676] = _6093; + uint16_t _6094 = (uint16_t)(220); + _curvea0[677] = _6094; + uint16_t _6095 = (uint16_t)(220); + _curvea0[678] = _6095; + uint16_t _6096 = (uint16_t)(220); + _curvea0[679] = _6096; + uint16_t _6097 = (uint16_t)(220); + _curvea0[680] = _6097; + uint16_t _6098 = (uint16_t)(221); + _curvea0[681] = _6098; + uint16_t _6099 = (uint16_t)(221); + _curvea0[682] = _6099; + uint16_t _6100 = (uint16_t)(221); + _curvea0[683] = _6100; + uint16_t _6101 = (uint16_t)(221); + _curvea0[684] = _6101; + uint16_t _6102 = (uint16_t)(221); + _curvea0[685] = _6102; + uint16_t _6103 = (uint16_t)(221); + _curvea0[686] = _6103; + uint16_t _6104 = (uint16_t)(221); + _curvea0[687] = _6104; + uint16_t _6105 = (uint16_t)(222); + _curvea0[688] = _6105; + uint16_t _6106 = (uint16_t)(222); + _curvea0[689] = _6106; + uint16_t _6107 = (uint16_t)(222); + _curvea0[690] = _6107; + uint16_t _6108 = (uint16_t)(222); + _curvea0[691] = _6108; + uint16_t _6109 = (uint16_t)(222); + _curvea0[692] = _6109; + uint16_t _6110 = (uint16_t)(222); + _curvea0[693] = _6110; + uint16_t _6111 = (uint16_t)(222); + _curvea0[694] = _6111; + uint16_t _6112 = (uint16_t)(223); + _curvea0[695] = _6112; + uint16_t _6113 = (uint16_t)(223); + _curvea0[696] = _6113; + uint16_t _6114 = (uint16_t)(223); + _curvea0[697] = _6114; + uint16_t _6115 = (uint16_t)(223); + _curvea0[698] = _6115; + uint16_t _6116 = (uint16_t)(223); + _curvea0[699] = _6116; + uint16_t _6117 = (uint16_t)(223); + _curvea0[700] = _6117; + uint16_t _6118 = (uint16_t)(223); + _curvea0[701] = _6118; + uint16_t _6119 = (uint16_t)(223); + _curvea0[702] = _6119; + uint16_t _6120 = (uint16_t)(224); + _curvea0[703] = _6120; + uint16_t _6121 = (uint16_t)(224); + _curvea0[704] = _6121; + uint16_t _6122 = (uint16_t)(224); + _curvea0[705] = _6122; + uint16_t _6123 = (uint16_t)(224); + _curvea0[706] = _6123; + uint16_t _6124 = (uint16_t)(224); + _curvea0[707] = _6124; + uint16_t _6125 = (uint16_t)(224); + _curvea0[708] = _6125; + uint16_t _6126 = (uint16_t)(224); + _curvea0[709] = _6126; + uint16_t _6127 = (uint16_t)(224); + _curvea0[710] = _6127; + uint16_t _6128 = (uint16_t)(225); + _curvea0[711] = _6128; + uint16_t _6129 = (uint16_t)(225); + _curvea0[712] = _6129; + uint16_t _6130 = (uint16_t)(225); + _curvea0[713] = _6130; + uint16_t _6131 = (uint16_t)(225); + _curvea0[714] = _6131; + uint16_t _6132 = (uint16_t)(225); + _curvea0[715] = _6132; + uint16_t _6133 = (uint16_t)(225); + _curvea0[716] = _6133; + uint16_t _6134 = (uint16_t)(225); + _curvea0[717] = _6134; + uint16_t _6135 = (uint16_t)(226); + _curvea0[718] = _6135; + uint16_t _6136 = (uint16_t)(226); + _curvea0[719] = _6136; + uint16_t _6137 = (uint16_t)(226); + _curvea0[720] = _6137; + uint16_t _6138 = (uint16_t)(226); + _curvea0[721] = _6138; + uint16_t _6139 = (uint16_t)(226); + _curvea0[722] = _6139; + uint16_t _6140 = (uint16_t)(226); + _curvea0[723] = _6140; + uint16_t _6141 = (uint16_t)(226); + _curvea0[724] = _6141; + uint16_t _6142 = (uint16_t)(226); + _curvea0[725] = _6142; + uint16_t _6143 = (uint16_t)(227); + _curvea0[726] = _6143; + uint16_t _6144 = (uint16_t)(227); + _curvea0[727] = _6144; + uint16_t _6145 = (uint16_t)(227); + _curvea0[728] = _6145; + uint16_t _6146 = (uint16_t)(227); + _curvea0[729] = _6146; + uint16_t _6147 = (uint16_t)(227); + _curvea0[730] = _6147; + uint16_t _6148 = (uint16_t)(227); + _curvea0[731] = _6148; + uint16_t _6149 = (uint16_t)(227); + _curvea0[732] = _6149; + uint16_t _6150 = (uint16_t)(227); + _curvea0[733] = _6150; + uint16_t _6151 = (uint16_t)(228); + _curvea0[734] = _6151; + uint16_t _6152 = (uint16_t)(228); + _curvea0[735] = _6152; + uint16_t _6153 = (uint16_t)(228); + _curvea0[736] = _6153; + uint16_t _6154 = (uint16_t)(228); + _curvea0[737] = _6154; + uint16_t _6155 = (uint16_t)(228); + _curvea0[738] = _6155; + uint16_t _6156 = (uint16_t)(228); + _curvea0[739] = _6156; + uint16_t _6157 = (uint16_t)(228); + _curvea0[740] = _6157; + uint16_t _6158 = (uint16_t)(228); + _curvea0[741] = _6158; + uint16_t _6159 = (uint16_t)(228); + _curvea0[742] = _6159; + uint16_t _6160 = (uint16_t)(229); + _curvea0[743] = _6160; + uint16_t _6161 = (uint16_t)(229); + _curvea0[744] = _6161; + uint16_t _6162 = (uint16_t)(229); + _curvea0[745] = _6162; + uint16_t _6163 = (uint16_t)(229); + _curvea0[746] = _6163; + uint16_t _6164 = (uint16_t)(229); + _curvea0[747] = _6164; + uint16_t _6165 = (uint16_t)(229); + _curvea0[748] = _6165; + uint16_t _6166 = (uint16_t)(229); + _curvea0[749] = _6166; + uint16_t _6167 = (uint16_t)(229); + _curvea0[750] = _6167; + uint16_t _6168 = (uint16_t)(230); + _curvea0[751] = _6168; + uint16_t _6169 = (uint16_t)(230); + _curvea0[752] = _6169; + uint16_t _6170 = (uint16_t)(230); + _curvea0[753] = _6170; + uint16_t _6171 = (uint16_t)(230); + _curvea0[754] = _6171; + uint16_t _6172 = (uint16_t)(230); + _curvea0[755] = _6172; + uint16_t _6173 = (uint16_t)(230); + _curvea0[756] = _6173; + uint16_t _6174 = (uint16_t)(230); + _curvea0[757] = _6174; + uint16_t _6175 = (uint16_t)(230); + _curvea0[758] = _6175; + uint16_t _6176 = (uint16_t)(231); + _curvea0[759] = _6176; + uint16_t _6177 = (uint16_t)(231); + _curvea0[760] = _6177; + uint16_t _6178 = (uint16_t)(231); + _curvea0[761] = _6178; + uint16_t _6179 = (uint16_t)(231); + _curvea0[762] = _6179; + uint16_t _6180 = (uint16_t)(231); + _curvea0[763] = _6180; + uint16_t _6181 = (uint16_t)(231); + _curvea0[764] = _6181; + uint16_t _6182 = (uint16_t)(231); + _curvea0[765] = _6182; + uint16_t _6183 = (uint16_t)(231); + _curvea0[766] = _6183; + uint16_t _6184 = (uint16_t)(231); + _curvea0[767] = _6184; + uint16_t _6185 = (uint16_t)(232); + _curvea0[768] = _6185; + uint16_t _6186 = (uint16_t)(232); + _curvea0[769] = _6186; + uint16_t _6187 = (uint16_t)(232); + _curvea0[770] = _6187; + uint16_t _6188 = (uint16_t)(232); + _curvea0[771] = _6188; + uint16_t _6189 = (uint16_t)(232); + _curvea0[772] = _6189; + uint16_t _6190 = (uint16_t)(232); + _curvea0[773] = _6190; + uint16_t _6191 = (uint16_t)(232); + _curvea0[774] = _6191; + uint16_t _6192 = (uint16_t)(232); + _curvea0[775] = _6192; + uint16_t _6193 = (uint16_t)(233); + _curvea0[776] = _6193; + uint16_t _6194 = (uint16_t)(233); + _curvea0[777] = _6194; + uint16_t _6195 = (uint16_t)(233); + _curvea0[778] = _6195; + uint16_t _6196 = (uint16_t)(233); + _curvea0[779] = _6196; + uint16_t _6197 = (uint16_t)(233); + _curvea0[780] = _6197; + uint16_t _6198 = (uint16_t)(233); + _curvea0[781] = _6198; + uint16_t _6199 = (uint16_t)(233); + _curvea0[782] = _6199; + uint16_t _6200 = (uint16_t)(233); + _curvea0[783] = _6200; + uint16_t _6201 = (uint16_t)(233); + _curvea0[784] = _6201; + uint16_t _6202 = (uint16_t)(234); + _curvea0[785] = _6202; + uint16_t _6203 = (uint16_t)(234); + _curvea0[786] = _6203; + uint16_t _6204 = (uint16_t)(234); + _curvea0[787] = _6204; + uint16_t _6205 = (uint16_t)(234); + _curvea0[788] = _6205; + uint16_t _6206 = (uint16_t)(234); + _curvea0[789] = _6206; + uint16_t _6207 = (uint16_t)(234); + _curvea0[790] = _6207; + uint16_t _6208 = (uint16_t)(234); + _curvea0[791] = _6208; + uint16_t _6209 = (uint16_t)(234); + _curvea0[792] = _6209; + uint16_t _6210 = (uint16_t)(234); + _curvea0[793] = _6210; + uint16_t _6211 = (uint16_t)(235); + _curvea0[794] = _6211; + uint16_t _6212 = (uint16_t)(235); + _curvea0[795] = _6212; + uint16_t _6213 = (uint16_t)(235); + _curvea0[796] = _6213; + uint16_t _6214 = (uint16_t)(235); + _curvea0[797] = _6214; + uint16_t _6215 = (uint16_t)(235); + _curvea0[798] = _6215; + uint16_t _6216 = (uint16_t)(235); + _curvea0[799] = _6216; + uint16_t _6217 = (uint16_t)(235); + _curvea0[800] = _6217; + uint16_t _6218 = (uint16_t)(235); + _curvea0[801] = _6218; + uint16_t _6219 = (uint16_t)(235); + _curvea0[802] = _6219; + uint16_t _6220 = (uint16_t)(236); + _curvea0[803] = _6220; + uint16_t _6221 = (uint16_t)(236); + _curvea0[804] = _6221; + uint16_t _6222 = (uint16_t)(236); + _curvea0[805] = _6222; + uint16_t _6223 = (uint16_t)(236); + _curvea0[806] = _6223; + uint16_t _6224 = (uint16_t)(236); + _curvea0[807] = _6224; + uint16_t _6225 = (uint16_t)(236); + _curvea0[808] = _6225; + uint16_t _6226 = (uint16_t)(236); + _curvea0[809] = _6226; + uint16_t _6227 = (uint16_t)(236); + _curvea0[810] = _6227; + uint16_t _6228 = (uint16_t)(236); + _curvea0[811] = _6228; + uint16_t _6229 = (uint16_t)(237); + _curvea0[812] = _6229; + uint16_t _6230 = (uint16_t)(237); + _curvea0[813] = _6230; + uint16_t _6231 = (uint16_t)(237); + _curvea0[814] = _6231; + uint16_t _6232 = (uint16_t)(237); + _curvea0[815] = _6232; + uint16_t _6233 = (uint16_t)(237); + _curvea0[816] = _6233; + uint16_t _6234 = (uint16_t)(237); + _curvea0[817] = _6234; + uint16_t _6235 = (uint16_t)(237); + _curvea0[818] = _6235; + uint16_t _6236 = (uint16_t)(237); + _curvea0[819] = _6236; + uint16_t _6237 = (uint16_t)(237); + _curvea0[820] = _6237; + uint16_t _6238 = (uint16_t)(237); + _curvea0[821] = _6238; + uint16_t _6239 = (uint16_t)(238); + _curvea0[822] = _6239; + uint16_t _6240 = (uint16_t)(238); + _curvea0[823] = _6240; + uint16_t _6241 = (uint16_t)(238); + _curvea0[824] = _6241; + uint16_t _6242 = (uint16_t)(238); + _curvea0[825] = _6242; + uint16_t _6243 = (uint16_t)(238); + _curvea0[826] = _6243; + uint16_t _6244 = (uint16_t)(238); + _curvea0[827] = _6244; + uint16_t _6245 = (uint16_t)(238); + _curvea0[828] = _6245; + uint16_t _6246 = (uint16_t)(238); + _curvea0[829] = _6246; + uint16_t _6247 = (uint16_t)(238); + _curvea0[830] = _6247; + uint16_t _6248 = (uint16_t)(239); + _curvea0[831] = _6248; + uint16_t _6249 = (uint16_t)(239); + _curvea0[832] = _6249; + uint16_t _6250 = (uint16_t)(239); + _curvea0[833] = _6250; + uint16_t _6251 = (uint16_t)(239); + _curvea0[834] = _6251; + uint16_t _6252 = (uint16_t)(239); + _curvea0[835] = _6252; + uint16_t _6253 = (uint16_t)(239); + _curvea0[836] = _6253; + uint16_t _6254 = (uint16_t)(239); + _curvea0[837] = _6254; + uint16_t _6255 = (uint16_t)(239); + _curvea0[838] = _6255; + uint16_t _6256 = (uint16_t)(239); + _curvea0[839] = _6256; + uint16_t _6257 = (uint16_t)(239); + _curvea0[840] = _6257; + uint16_t _6258 = (uint16_t)(240); + _curvea0[841] = _6258; + uint16_t _6259 = (uint16_t)(240); + _curvea0[842] = _6259; + uint16_t _6260 = (uint16_t)(240); + _curvea0[843] = _6260; + uint16_t _6261 = (uint16_t)(240); + _curvea0[844] = _6261; + uint16_t _6262 = (uint16_t)(240); + _curvea0[845] = _6262; + uint16_t _6263 = (uint16_t)(240); + _curvea0[846] = _6263; + uint16_t _6264 = (uint16_t)(240); + _curvea0[847] = _6264; + uint16_t _6265 = (uint16_t)(240); + _curvea0[848] = _6265; + uint16_t _6266 = (uint16_t)(240); + _curvea0[849] = _6266; + uint16_t _6267 = (uint16_t)(240); + _curvea0[850] = _6267; + uint16_t _6268 = (uint16_t)(241); + _curvea0[851] = _6268; + uint16_t _6269 = (uint16_t)(241); + _curvea0[852] = _6269; + uint16_t _6270 = (uint16_t)(241); + _curvea0[853] = _6270; + uint16_t _6271 = (uint16_t)(241); + _curvea0[854] = _6271; + uint16_t _6272 = (uint16_t)(241); + _curvea0[855] = _6272; + uint16_t _6273 = (uint16_t)(241); + _curvea0[856] = _6273; + uint16_t _6274 = (uint16_t)(241); + _curvea0[857] = _6274; + uint16_t _6275 = (uint16_t)(241); + _curvea0[858] = _6275; + uint16_t _6276 = (uint16_t)(241); + _curvea0[859] = _6276; + uint16_t _6277 = (uint16_t)(241); + _curvea0[860] = _6277; + uint16_t _6278 = (uint16_t)(242); + _curvea0[861] = _6278; + uint16_t _6279 = (uint16_t)(242); + _curvea0[862] = _6279; + uint16_t _6280 = (uint16_t)(242); + _curvea0[863] = _6280; + uint16_t _6281 = (uint16_t)(242); + _curvea0[864] = _6281; + uint16_t _6282 = (uint16_t)(242); + _curvea0[865] = _6282; + uint16_t _6283 = (uint16_t)(242); + _curvea0[866] = _6283; + uint16_t _6284 = (uint16_t)(242); + _curvea0[867] = _6284; + uint16_t _6285 = (uint16_t)(242); + _curvea0[868] = _6285; + uint16_t _6286 = (uint16_t)(242); + _curvea0[869] = _6286; + uint16_t _6287 = (uint16_t)(242); + _curvea0[870] = _6287; + uint16_t _6288 = (uint16_t)(243); + _curvea0[871] = _6288; + uint16_t _6289 = (uint16_t)(243); + _curvea0[872] = _6289; + uint16_t _6290 = (uint16_t)(243); + _curvea0[873] = _6290; + uint16_t _6291 = (uint16_t)(243); + _curvea0[874] = _6291; + uint16_t _6292 = (uint16_t)(243); + _curvea0[875] = _6292; + uint16_t _6293 = (uint16_t)(243); + _curvea0[876] = _6293; + uint16_t _6294 = (uint16_t)(243); + _curvea0[877] = _6294; + uint16_t _6295 = (uint16_t)(243); + _curvea0[878] = _6295; + uint16_t _6296 = (uint16_t)(243); + _curvea0[879] = _6296; + uint16_t _6297 = (uint16_t)(243); + _curvea0[880] = _6297; + uint16_t _6298 = (uint16_t)(244); + _curvea0[881] = _6298; + uint16_t _6299 = (uint16_t)(244); + _curvea0[882] = _6299; + uint16_t _6300 = (uint16_t)(244); + _curvea0[883] = _6300; + uint16_t _6301 = (uint16_t)(244); + _curvea0[884] = _6301; + uint16_t _6302 = (uint16_t)(244); + _curvea0[885] = _6302; + uint16_t _6303 = (uint16_t)(244); + _curvea0[886] = _6303; + uint16_t _6304 = (uint16_t)(244); + _curvea0[887] = _6304; + uint16_t _6305 = (uint16_t)(244); + _curvea0[888] = _6305; + uint16_t _6306 = (uint16_t)(244); + _curvea0[889] = _6306; + uint16_t _6307 = (uint16_t)(244); + _curvea0[890] = _6307; + uint16_t _6308 = (uint16_t)(244); + _curvea0[891] = _6308; + uint16_t _6309 = (uint16_t)(245); + _curvea0[892] = _6309; + uint16_t _6310 = (uint16_t)(245); + _curvea0[893] = _6310; + uint16_t _6311 = (uint16_t)(245); + _curvea0[894] = _6311; + uint16_t _6312 = (uint16_t)(245); + _curvea0[895] = _6312; + uint16_t _6313 = (uint16_t)(245); + _curvea0[896] = _6313; + uint16_t _6314 = (uint16_t)(245); + _curvea0[897] = _6314; + uint16_t _6315 = (uint16_t)(245); + _curvea0[898] = _6315; + uint16_t _6316 = (uint16_t)(245); + _curvea0[899] = _6316; + uint16_t _6317 = (uint16_t)(245); + _curvea0[900] = _6317; + uint16_t _6318 = (uint16_t)(245); + _curvea0[901] = _6318; + uint16_t _6319 = (uint16_t)(245); + _curvea0[902] = _6319; + uint16_t _6320 = (uint16_t)(246); + _curvea0[903] = _6320; + uint16_t _6321 = (uint16_t)(246); + _curvea0[904] = _6321; + uint16_t _6322 = (uint16_t)(246); + _curvea0[905] = _6322; + uint16_t _6323 = (uint16_t)(246); + _curvea0[906] = _6323; + uint16_t _6324 = (uint16_t)(246); + _curvea0[907] = _6324; + uint16_t _6325 = (uint16_t)(246); + _curvea0[908] = _6325; + uint16_t _6326 = (uint16_t)(246); + _curvea0[909] = _6326; + uint16_t _6327 = (uint16_t)(246); + _curvea0[910] = _6327; + uint16_t _6328 = (uint16_t)(246); + _curvea0[911] = _6328; + uint16_t _6329 = (uint16_t)(246); + _curvea0[912] = _6329; + uint16_t _6330 = (uint16_t)(246); + _curvea0[913] = _6330; + uint16_t _6331 = (uint16_t)(247); + _curvea0[914] = _6331; + uint16_t _6332 = (uint16_t)(247); + _curvea0[915] = _6332; + uint16_t _6333 = (uint16_t)(247); + _curvea0[916] = _6333; + uint16_t _6334 = (uint16_t)(247); + _curvea0[917] = _6334; + uint16_t _6335 = (uint16_t)(247); + _curvea0[918] = _6335; + uint16_t _6336 = (uint16_t)(247); + _curvea0[919] = _6336; + uint16_t _6337 = (uint16_t)(247); + _curvea0[920] = _6337; + uint16_t _6338 = (uint16_t)(247); + _curvea0[921] = _6338; + uint16_t _6339 = (uint16_t)(247); + _curvea0[922] = _6339; + uint16_t _6340 = (uint16_t)(247); + _curvea0[923] = _6340; + uint16_t _6341 = (uint16_t)(247); + _curvea0[924] = _6341; + uint16_t _6342 = (uint16_t)(248); + _curvea0[925] = _6342; + uint16_t _6343 = (uint16_t)(248); + _curvea0[926] = _6343; + uint16_t _6344 = (uint16_t)(248); + _curvea0[927] = _6344; + uint16_t _6345 = (uint16_t)(248); + _curvea0[928] = _6345; + uint16_t _6346 = (uint16_t)(248); + _curvea0[929] = _6346; + uint16_t _6347 = (uint16_t)(248); + _curvea0[930] = _6347; + uint16_t _6348 = (uint16_t)(248); + _curvea0[931] = _6348; + uint16_t _6349 = (uint16_t)(248); + _curvea0[932] = _6349; + uint16_t _6350 = (uint16_t)(248); + _curvea0[933] = _6350; + uint16_t _6351 = (uint16_t)(248); + _curvea0[934] = _6351; + uint16_t _6352 = (uint16_t)(248); + _curvea0[935] = _6352; + uint16_t _6353 = (uint16_t)(249); + _curvea0[936] = _6353; + uint16_t _6354 = (uint16_t)(249); + _curvea0[937] = _6354; + uint16_t _6355 = (uint16_t)(249); + _curvea0[938] = _6355; + uint16_t _6356 = (uint16_t)(249); + _curvea0[939] = _6356; + uint16_t _6357 = (uint16_t)(249); + _curvea0[940] = _6357; + uint16_t _6358 = (uint16_t)(249); + _curvea0[941] = _6358; + uint16_t _6359 = (uint16_t)(249); + _curvea0[942] = _6359; + uint16_t _6360 = (uint16_t)(249); + _curvea0[943] = _6360; + uint16_t _6361 = (uint16_t)(249); + _curvea0[944] = _6361; + uint16_t _6362 = (uint16_t)(249); + _curvea0[945] = _6362; + uint16_t _6363 = (uint16_t)(249); + _curvea0[946] = _6363; + uint16_t _6364 = (uint16_t)(249); + _curvea0[947] = _6364; + uint16_t _6365 = (uint16_t)(250); + _curvea0[948] = _6365; + uint16_t _6366 = (uint16_t)(250); + _curvea0[949] = _6366; + uint16_t _6367 = (uint16_t)(250); + _curvea0[950] = _6367; + uint16_t _6368 = (uint16_t)(250); + _curvea0[951] = _6368; + uint16_t _6369 = (uint16_t)(250); + _curvea0[952] = _6369; + uint16_t _6370 = (uint16_t)(250); + _curvea0[953] = _6370; + uint16_t _6371 = (uint16_t)(250); + _curvea0[954] = _6371; + uint16_t _6372 = (uint16_t)(250); + _curvea0[955] = _6372; + uint16_t _6373 = (uint16_t)(250); + _curvea0[956] = _6373; + uint16_t _6374 = (uint16_t)(250); + _curvea0[957] = _6374; + uint16_t _6375 = (uint16_t)(250); + _curvea0[958] = _6375; + uint16_t _6376 = (uint16_t)(250); + _curvea0[959] = _6376; + uint16_t _6377 = (uint16_t)(251); + _curvea0[960] = _6377; + uint16_t _6378 = (uint16_t)(251); + _curvea0[961] = _6378; + uint16_t _6379 = (uint16_t)(251); + _curvea0[962] = _6379; + uint16_t _6380 = (uint16_t)(251); + _curvea0[963] = _6380; + uint16_t _6381 = (uint16_t)(251); + _curvea0[964] = _6381; + uint16_t _6382 = (uint16_t)(251); + _curvea0[965] = _6382; + uint16_t _6383 = (uint16_t)(251); + _curvea0[966] = _6383; + uint16_t _6384 = (uint16_t)(251); + _curvea0[967] = _6384; + uint16_t _6385 = (uint16_t)(251); + _curvea0[968] = _6385; + uint16_t _6386 = (uint16_t)(251); + _curvea0[969] = _6386; + uint16_t _6387 = (uint16_t)(251); + _curvea0[970] = _6387; + uint16_t _6388 = (uint16_t)(251); + _curvea0[971] = _6388; + uint16_t _6389 = (uint16_t)(252); + _curvea0[972] = _6389; + uint16_t _6390 = (uint16_t)(252); + _curvea0[973] = _6390; + uint16_t _6391 = (uint16_t)(252); + _curvea0[974] = _6391; + uint16_t _6392 = (uint16_t)(252); + _curvea0[975] = _6392; + uint16_t _6393 = (uint16_t)(252); + _curvea0[976] = _6393; + uint16_t _6394 = (uint16_t)(252); + _curvea0[977] = _6394; + uint16_t _6395 = (uint16_t)(252); + _curvea0[978] = _6395; + uint16_t _6396 = (uint16_t)(252); + _curvea0[979] = _6396; + uint16_t _6397 = (uint16_t)(252); + _curvea0[980] = _6397; + uint16_t _6398 = (uint16_t)(252); + _curvea0[981] = _6398; + uint16_t _6399 = (uint16_t)(252); + _curvea0[982] = _6399; + uint16_t _6400 = (uint16_t)(252); + _curvea0[983] = _6400; + uint16_t _6401 = (uint16_t)(252); + _curvea0[984] = _6401; + uint16_t _6402 = (uint16_t)(253); + _curvea0[985] = _6402; + uint16_t _6403 = (uint16_t)(253); + _curvea0[986] = _6403; + uint16_t _6404 = (uint16_t)(253); + _curvea0[987] = _6404; + uint16_t _6405 = (uint16_t)(253); + _curvea0[988] = _6405; + uint16_t _6406 = (uint16_t)(253); + _curvea0[989] = _6406; + uint16_t _6407 = (uint16_t)(253); + _curvea0[990] = _6407; + uint16_t _6408 = (uint16_t)(253); + _curvea0[991] = _6408; + uint16_t _6409 = (uint16_t)(253); + _curvea0[992] = _6409; + uint16_t _6410 = (uint16_t)(253); + _curvea0[993] = _6410; + uint16_t _6411 = (uint16_t)(253); + _curvea0[994] = _6411; + uint16_t _6412 = (uint16_t)(253); + _curvea0[995] = _6412; + uint16_t _6413 = (uint16_t)(253); + _curvea0[996] = _6413; + uint16_t _6414 = (uint16_t)(253); + _curvea0[997] = _6414; + uint16_t _6415 = (uint16_t)(254); + _curvea0[998] = _6415; + uint16_t _6416 = (uint16_t)(254); + _curvea0[999] = _6416; + uint16_t _6417 = (uint16_t)(254); + _curvea0[1000] = _6417; + uint16_t _6418 = (uint16_t)(254); + _curvea0[1001] = _6418; + uint16_t _6419 = (uint16_t)(254); + _curvea0[1002] = _6419; + uint16_t _6420 = (uint16_t)(254); + _curvea0[1003] = _6420; + uint16_t _6421 = (uint16_t)(254); + _curvea0[1004] = _6421; + uint16_t _6422 = (uint16_t)(254); + _curvea0[1005] = _6422; + uint16_t _6423 = (uint16_t)(254); + _curvea0[1006] = _6423; + uint16_t _6424 = (uint16_t)(254); + _curvea0[1007] = _6424; + uint16_t _6425 = (uint16_t)(254); + _curvea0[1008] = _6425; + uint16_t _6426 = (uint16_t)(254); + _curvea0[1009] = _6426; + uint16_t _6427 = (uint16_t)(254); + _curvea0[1010] = _6427; + uint16_t _6428 = (uint16_t)(255); + _curvea0[1011] = _6428; + uint16_t _6429 = (uint16_t)(255); + _curvea0[1012] = _6429; + uint16_t _6430 = (uint16_t)(255); + _curvea0[1013] = _6430; + uint16_t _6431 = (uint16_t)(255); + _curvea0[1014] = _6431; + uint16_t _6432 = (uint16_t)(255); + _curvea0[1015] = _6432; + uint16_t _6433 = (uint16_t)(255); + _curvea0[1016] = _6433; + uint16_t _6434 = (uint16_t)(255); + _curvea0[1017] = _6434; + uint16_t _6435 = (uint16_t)(255); + _curvea0[1018] = _6435; + uint16_t _6436 = (uint16_t)(255); + _curvea0[1019] = _6436; + uint16_t _6437 = (uint16_t)(255); + _curvea0[1020] = _6437; + uint16_t _6438 = (uint16_t)(255); + _curvea0[1021] = _6438; + uint16_t _6439 = (uint16_t)(255); + _curvea0[1022] = _6439; + uint16_t _6440 = (uint16_t)(255); + _curvea0[1023] = _6440; + + int16_t _6441 = (int16_t)(1023); + int16_t _6442 = min(_corrected_stencil_4, _6441); + int16_t _6443 = (int16_t)(0); + int16_t _6444 = max(_6442, _6443); + uint16_t _6445 = (uint16_t)(_6444); + int32_t _6446 = (int32_t)(_6445); + uint16_t _6447 = ((const uint16_t *)_curvea0)[_6446]; + return _6447; +} + +//store is: curved.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_4(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_5 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _6464 = (uint16_t)(0); + _curvea0[0] = _6464; + uint16_t _6465 = (uint16_t)(4); + _curvea0[1] = _6465; + uint16_t _6466 = (uint16_t)(7); + _curvea0[2] = _6466; + uint16_t _6467 = (uint16_t)(8); + _curvea0[3] = _6467; + uint16_t _6468 = (uint16_t)(10); + _curvea0[4] = _6468; + uint16_t _6469 = (uint16_t)(11); + _curvea0[5] = _6469; + uint16_t _6470 = (uint16_t)(12); + _curvea0[6] = _6470; + uint16_t _6471 = (uint16_t)(13); + _curvea0[7] = _6471; + uint16_t _6472 = (uint16_t)(14); + _curvea0[8] = _6472; + uint16_t _6473 = (uint16_t)(15); + _curvea0[9] = _6473; + uint16_t _6474 = (uint16_t)(16); + _curvea0[10] = _6474; + uint16_t _6475 = (uint16_t)(17); + _curvea0[11] = _6475; + uint16_t _6476 = (uint16_t)(18); + _curvea0[12] = _6476; + uint16_t _6477 = (uint16_t)(19); + _curvea0[13] = _6477; + uint16_t _6478 = (uint16_t)(20); + _curvea0[14] = _6478; + uint16_t _6479 = (uint16_t)(21); + _curvea0[15] = _6479; + uint16_t _6480 = (uint16_t)(22); + _curvea0[16] = _6480; + uint16_t _6481 = (uint16_t)(22); + _curvea0[17] = _6481; + uint16_t _6482 = (uint16_t)(23); + _curvea0[18] = _6482; + uint16_t _6483 = (uint16_t)(24); + _curvea0[19] = _6483; + uint16_t _6484 = (uint16_t)(25); + _curvea0[20] = _6484; + uint16_t _6485 = (uint16_t)(25); + _curvea0[21] = _6485; + uint16_t _6486 = (uint16_t)(26); + _curvea0[22] = _6486; + uint16_t _6487 = (uint16_t)(27); + _curvea0[23] = _6487; + uint16_t _6488 = (uint16_t)(27); + _curvea0[24] = _6488; + uint16_t _6489 = (uint16_t)(28); + _curvea0[25] = _6489; + uint16_t _6490 = (uint16_t)(29); + _curvea0[26] = _6490; + uint16_t _6491 = (uint16_t)(29); + _curvea0[27] = _6491; + uint16_t _6492 = (uint16_t)(30); + _curvea0[28] = _6492; + uint16_t _6493 = (uint16_t)(31); + _curvea0[29] = _6493; + uint16_t _6494 = (uint16_t)(31); + _curvea0[30] = _6494; + uint16_t _6495 = (uint16_t)(32); + _curvea0[31] = _6495; + uint16_t _6496 = (uint16_t)(33); + _curvea0[32] = _6496; + uint16_t _6497 = (uint16_t)(33); + _curvea0[33] = _6497; + uint16_t _6498 = (uint16_t)(34); + _curvea0[34] = _6498; + uint16_t _6499 = (uint16_t)(34); + _curvea0[35] = _6499; + uint16_t _6500 = (uint16_t)(35); + _curvea0[36] = _6500; + uint16_t _6501 = (uint16_t)(36); + _curvea0[37] = _6501; + uint16_t _6502 = (uint16_t)(36); + _curvea0[38] = _6502; + uint16_t _6503 = (uint16_t)(37); + _curvea0[39] = _6503; + uint16_t _6504 = (uint16_t)(37); + _curvea0[40] = _6504; + uint16_t _6505 = (uint16_t)(38); + _curvea0[41] = _6505; + uint16_t _6506 = (uint16_t)(39); + _curvea0[42] = _6506; + uint16_t _6507 = (uint16_t)(39); + _curvea0[43] = _6507; + uint16_t _6508 = (uint16_t)(40); + _curvea0[44] = _6508; + uint16_t _6509 = (uint16_t)(40); + _curvea0[45] = _6509; + uint16_t _6510 = (uint16_t)(41); + _curvea0[46] = _6510; + uint16_t _6511 = (uint16_t)(41); + _curvea0[47] = _6511; + uint16_t _6512 = (uint16_t)(42); + _curvea0[48] = _6512; + uint16_t _6513 = (uint16_t)(42); + _curvea0[49] = _6513; + uint16_t _6514 = (uint16_t)(43); + _curvea0[50] = _6514; + uint16_t _6515 = (uint16_t)(44); + _curvea0[51] = _6515; + uint16_t _6516 = (uint16_t)(44); + _curvea0[52] = _6516; + uint16_t _6517 = (uint16_t)(45); + _curvea0[53] = _6517; + uint16_t _6518 = (uint16_t)(45); + _curvea0[54] = _6518; + uint16_t _6519 = (uint16_t)(46); + _curvea0[55] = _6519; + uint16_t _6520 = (uint16_t)(46); + _curvea0[56] = _6520; + uint16_t _6521 = (uint16_t)(47); + _curvea0[57] = _6521; + uint16_t _6522 = (uint16_t)(47); + _curvea0[58] = _6522; + uint16_t _6523 = (uint16_t)(48); + _curvea0[59] = _6523; + uint16_t _6524 = (uint16_t)(48); + _curvea0[60] = _6524; + uint16_t _6525 = (uint16_t)(49); + _curvea0[61] = _6525; + uint16_t _6526 = (uint16_t)(49); + _curvea0[62] = _6526; + uint16_t _6527 = (uint16_t)(50); + _curvea0[63] = _6527; + uint16_t _6528 = (uint16_t)(50); + _curvea0[64] = _6528; + uint16_t _6529 = (uint16_t)(51); + _curvea0[65] = _6529; + uint16_t _6530 = (uint16_t)(51); + _curvea0[66] = _6530; + uint16_t _6531 = (uint16_t)(52); + _curvea0[67] = _6531; + uint16_t _6532 = (uint16_t)(52); + _curvea0[68] = _6532; + uint16_t _6533 = (uint16_t)(53); + _curvea0[69] = _6533; + uint16_t _6534 = (uint16_t)(53); + _curvea0[70] = _6534; + uint16_t _6535 = (uint16_t)(54); + _curvea0[71] = _6535; + uint16_t _6536 = (uint16_t)(54); + _curvea0[72] = _6536; + uint16_t _6537 = (uint16_t)(55); + _curvea0[73] = _6537; + uint16_t _6538 = (uint16_t)(55); + _curvea0[74] = _6538; + uint16_t _6539 = (uint16_t)(56); + _curvea0[75] = _6539; + uint16_t _6540 = (uint16_t)(56); + _curvea0[76] = _6540; + uint16_t _6541 = (uint16_t)(57); + _curvea0[77] = _6541; + uint16_t _6542 = (uint16_t)(57); + _curvea0[78] = _6542; + uint16_t _6543 = (uint16_t)(58); + _curvea0[79] = _6543; + uint16_t _6544 = (uint16_t)(58); + _curvea0[80] = _6544; + uint16_t _6545 = (uint16_t)(58); + _curvea0[81] = _6545; + uint16_t _6546 = (uint16_t)(59); + _curvea0[82] = _6546; + uint16_t _6547 = (uint16_t)(59); + _curvea0[83] = _6547; + uint16_t _6548 = (uint16_t)(60); + _curvea0[84] = _6548; + uint16_t _6549 = (uint16_t)(60); + _curvea0[85] = _6549; + uint16_t _6550 = (uint16_t)(61); + _curvea0[86] = _6550; + uint16_t _6551 = (uint16_t)(61); + _curvea0[87] = _6551; + uint16_t _6552 = (uint16_t)(62); + _curvea0[88] = _6552; + uint16_t _6553 = (uint16_t)(62); + _curvea0[89] = _6553; + uint16_t _6554 = (uint16_t)(63); + _curvea0[90] = _6554; + uint16_t _6555 = (uint16_t)(63); + _curvea0[91] = _6555; + uint16_t _6556 = (uint16_t)(64); + _curvea0[92] = _6556; + uint16_t _6557 = (uint16_t)(64); + _curvea0[93] = _6557; + uint16_t _6558 = (uint16_t)(64); + _curvea0[94] = _6558; + uint16_t _6559 = (uint16_t)(65); + _curvea0[95] = _6559; + uint16_t _6560 = (uint16_t)(65); + _curvea0[96] = _6560; + uint16_t _6561 = (uint16_t)(66); + _curvea0[97] = _6561; + uint16_t _6562 = (uint16_t)(66); + _curvea0[98] = _6562; + uint16_t _6563 = (uint16_t)(67); + _curvea0[99] = _6563; + uint16_t _6564 = (uint16_t)(67); + _curvea0[100] = _6564; + uint16_t _6565 = (uint16_t)(68); + _curvea0[101] = _6565; + uint16_t _6566 = (uint16_t)(68); + _curvea0[102] = _6566; + uint16_t _6567 = (uint16_t)(68); + _curvea0[103] = _6567; + uint16_t _6568 = (uint16_t)(69); + _curvea0[104] = _6568; + uint16_t _6569 = (uint16_t)(69); + _curvea0[105] = _6569; + uint16_t _6570 = (uint16_t)(70); + _curvea0[106] = _6570; + uint16_t _6571 = (uint16_t)(70); + _curvea0[107] = _6571; + uint16_t _6572 = (uint16_t)(71); + _curvea0[108] = _6572; + uint16_t _6573 = (uint16_t)(71); + _curvea0[109] = _6573; + uint16_t _6574 = (uint16_t)(71); + _curvea0[110] = _6574; + uint16_t _6575 = (uint16_t)(72); + _curvea0[111] = _6575; + uint16_t _6576 = (uint16_t)(72); + _curvea0[112] = _6576; + uint16_t _6577 = (uint16_t)(73); + _curvea0[113] = _6577; + uint16_t _6578 = (uint16_t)(73); + _curvea0[114] = _6578; + uint16_t _6579 = (uint16_t)(74); + _curvea0[115] = _6579; + uint16_t _6580 = (uint16_t)(74); + _curvea0[116] = _6580; + uint16_t _6581 = (uint16_t)(74); + _curvea0[117] = _6581; + uint16_t _6582 = (uint16_t)(75); + _curvea0[118] = _6582; + uint16_t _6583 = (uint16_t)(75); + _curvea0[119] = _6583; + uint16_t _6584 = (uint16_t)(76); + _curvea0[120] = _6584; + uint16_t _6585 = (uint16_t)(76); + _curvea0[121] = _6585; + uint16_t _6586 = (uint16_t)(77); + _curvea0[122] = _6586; + uint16_t _6587 = (uint16_t)(77); + _curvea0[123] = _6587; + uint16_t _6588 = (uint16_t)(77); + _curvea0[124] = _6588; + uint16_t _6589 = (uint16_t)(78); + _curvea0[125] = _6589; + uint16_t _6590 = (uint16_t)(78); + _curvea0[126] = _6590; + uint16_t _6591 = (uint16_t)(79); + _curvea0[127] = _6591; + uint16_t _6592 = (uint16_t)(79); + _curvea0[128] = _6592; + uint16_t _6593 = (uint16_t)(79); + _curvea0[129] = _6593; + uint16_t _6594 = (uint16_t)(80); + _curvea0[130] = _6594; + uint16_t _6595 = (uint16_t)(80); + _curvea0[131] = _6595; + uint16_t _6596 = (uint16_t)(81); + _curvea0[132] = _6596; + uint16_t _6597 = (uint16_t)(81); + _curvea0[133] = _6597; + uint16_t _6598 = (uint16_t)(82); + _curvea0[134] = _6598; + uint16_t _6599 = (uint16_t)(82); + _curvea0[135] = _6599; + uint16_t _6600 = (uint16_t)(82); + _curvea0[136] = _6600; + uint16_t _6601 = (uint16_t)(83); + _curvea0[137] = _6601; + uint16_t _6602 = (uint16_t)(83); + _curvea0[138] = _6602; + uint16_t _6603 = (uint16_t)(84); + _curvea0[139] = _6603; + uint16_t _6604 = (uint16_t)(84); + _curvea0[140] = _6604; + uint16_t _6605 = (uint16_t)(84); + _curvea0[141] = _6605; + uint16_t _6606 = (uint16_t)(85); + _curvea0[142] = _6606; + uint16_t _6607 = (uint16_t)(85); + _curvea0[143] = _6607; + uint16_t _6608 = (uint16_t)(86); + _curvea0[144] = _6608; + uint16_t _6609 = (uint16_t)(86); + _curvea0[145] = _6609; + uint16_t _6610 = (uint16_t)(86); + _curvea0[146] = _6610; + uint16_t _6611 = (uint16_t)(87); + _curvea0[147] = _6611; + uint16_t _6612 = (uint16_t)(87); + _curvea0[148] = _6612; + uint16_t _6613 = (uint16_t)(88); + _curvea0[149] = _6613; + uint16_t _6614 = (uint16_t)(88); + _curvea0[150] = _6614; + uint16_t _6615 = (uint16_t)(88); + _curvea0[151] = _6615; + uint16_t _6616 = (uint16_t)(89); + _curvea0[152] = _6616; + uint16_t _6617 = (uint16_t)(89); + _curvea0[153] = _6617; + uint16_t _6618 = (uint16_t)(90); + _curvea0[154] = _6618; + uint16_t _6619 = (uint16_t)(90); + _curvea0[155] = _6619; + uint16_t _6620 = (uint16_t)(90); + _curvea0[156] = _6620; + uint16_t _6621 = (uint16_t)(91); + _curvea0[157] = _6621; + uint16_t _6622 = (uint16_t)(91); + _curvea0[158] = _6622; + uint16_t _6623 = (uint16_t)(92); + _curvea0[159] = _6623; + uint16_t _6624 = (uint16_t)(92); + _curvea0[160] = _6624; + uint16_t _6625 = (uint16_t)(92); + _curvea0[161] = _6625; + uint16_t _6626 = (uint16_t)(93); + _curvea0[162] = _6626; + uint16_t _6627 = (uint16_t)(93); + _curvea0[163] = _6627; + uint16_t _6628 = (uint16_t)(93); + _curvea0[164] = _6628; + uint16_t _6629 = (uint16_t)(94); + _curvea0[165] = _6629; + uint16_t _6630 = (uint16_t)(94); + _curvea0[166] = _6630; + uint16_t _6631 = (uint16_t)(95); + _curvea0[167] = _6631; + uint16_t _6632 = (uint16_t)(95); + _curvea0[168] = _6632; + uint16_t _6633 = (uint16_t)(95); + _curvea0[169] = _6633; + uint16_t _6634 = (uint16_t)(96); + _curvea0[170] = _6634; + uint16_t _6635 = (uint16_t)(96); + _curvea0[171] = _6635; + uint16_t _6636 = (uint16_t)(97); + _curvea0[172] = _6636; + uint16_t _6637 = (uint16_t)(97); + _curvea0[173] = _6637; + uint16_t _6638 = (uint16_t)(97); + _curvea0[174] = _6638; + uint16_t _6639 = (uint16_t)(98); + _curvea0[175] = _6639; + uint16_t _6640 = (uint16_t)(98); + _curvea0[176] = _6640; + uint16_t _6641 = (uint16_t)(99); + _curvea0[177] = _6641; + uint16_t _6642 = (uint16_t)(99); + _curvea0[178] = _6642; + uint16_t _6643 = (uint16_t)(99); + _curvea0[179] = _6643; + uint16_t _6644 = (uint16_t)(100); + _curvea0[180] = _6644; + uint16_t _6645 = (uint16_t)(100); + _curvea0[181] = _6645; + uint16_t _6646 = (uint16_t)(100); + _curvea0[182] = _6646; + uint16_t _6647 = (uint16_t)(101); + _curvea0[183] = _6647; + uint16_t _6648 = (uint16_t)(101); + _curvea0[184] = _6648; + uint16_t _6649 = (uint16_t)(102); + _curvea0[185] = _6649; + uint16_t _6650 = (uint16_t)(102); + _curvea0[186] = _6650; + uint16_t _6651 = (uint16_t)(102); + _curvea0[187] = _6651; + uint16_t _6652 = (uint16_t)(103); + _curvea0[188] = _6652; + uint16_t _6653 = (uint16_t)(103); + _curvea0[189] = _6653; + uint16_t _6654 = (uint16_t)(103); + _curvea0[190] = _6654; + uint16_t _6655 = (uint16_t)(104); + _curvea0[191] = _6655; + uint16_t _6656 = (uint16_t)(104); + _curvea0[192] = _6656; + uint16_t _6657 = (uint16_t)(105); + _curvea0[193] = _6657; + uint16_t _6658 = (uint16_t)(105); + _curvea0[194] = _6658; + uint16_t _6659 = (uint16_t)(105); + _curvea0[195] = _6659; + uint16_t _6660 = (uint16_t)(106); + _curvea0[196] = _6660; + uint16_t _6661 = (uint16_t)(106); + _curvea0[197] = _6661; + uint16_t _6662 = (uint16_t)(106); + _curvea0[198] = _6662; + uint16_t _6663 = (uint16_t)(107); + _curvea0[199] = _6663; + uint16_t _6664 = (uint16_t)(107); + _curvea0[200] = _6664; + uint16_t _6665 = (uint16_t)(108); + _curvea0[201] = _6665; + uint16_t _6666 = (uint16_t)(108); + _curvea0[202] = _6666; + uint16_t _6667 = (uint16_t)(108); + _curvea0[203] = _6667; + uint16_t _6668 = (uint16_t)(109); + _curvea0[204] = _6668; + uint16_t _6669 = (uint16_t)(109); + _curvea0[205] = _6669; + uint16_t _6670 = (uint16_t)(109); + _curvea0[206] = _6670; + uint16_t _6671 = (uint16_t)(110); + _curvea0[207] = _6671; + uint16_t _6672 = (uint16_t)(110); + _curvea0[208] = _6672; + uint16_t _6673 = (uint16_t)(111); + _curvea0[209] = _6673; + uint16_t _6674 = (uint16_t)(111); + _curvea0[210] = _6674; + uint16_t _6675 = (uint16_t)(111); + _curvea0[211] = _6675; + uint16_t _6676 = (uint16_t)(112); + _curvea0[212] = _6676; + uint16_t _6677 = (uint16_t)(112); + _curvea0[213] = _6677; + uint16_t _6678 = (uint16_t)(112); + _curvea0[214] = _6678; + uint16_t _6679 = (uint16_t)(113); + _curvea0[215] = _6679; + uint16_t _6680 = (uint16_t)(113); + _curvea0[216] = _6680; + uint16_t _6681 = (uint16_t)(113); + _curvea0[217] = _6681; + uint16_t _6682 = (uint16_t)(114); + _curvea0[218] = _6682; + uint16_t _6683 = (uint16_t)(114); + _curvea0[219] = _6683; + uint16_t _6684 = (uint16_t)(115); + _curvea0[220] = _6684; + uint16_t _6685 = (uint16_t)(115); + _curvea0[221] = _6685; + uint16_t _6686 = (uint16_t)(115); + _curvea0[222] = _6686; + uint16_t _6687 = (uint16_t)(116); + _curvea0[223] = _6687; + uint16_t _6688 = (uint16_t)(116); + _curvea0[224] = _6688; + uint16_t _6689 = (uint16_t)(116); + _curvea0[225] = _6689; + uint16_t _6690 = (uint16_t)(117); + _curvea0[226] = _6690; + uint16_t _6691 = (uint16_t)(117); + _curvea0[227] = _6691; + uint16_t _6692 = (uint16_t)(117); + _curvea0[228] = _6692; + uint16_t _6693 = (uint16_t)(118); + _curvea0[229] = _6693; + uint16_t _6694 = (uint16_t)(118); + _curvea0[230] = _6694; + uint16_t _6695 = (uint16_t)(119); + _curvea0[231] = _6695; + uint16_t _6696 = (uint16_t)(119); + _curvea0[232] = _6696; + uint16_t _6697 = (uint16_t)(119); + _curvea0[233] = _6697; + uint16_t _6698 = (uint16_t)(120); + _curvea0[234] = _6698; + uint16_t _6699 = (uint16_t)(120); + _curvea0[235] = _6699; + uint16_t _6700 = (uint16_t)(120); + _curvea0[236] = _6700; + uint16_t _6701 = (uint16_t)(121); + _curvea0[237] = _6701; + uint16_t _6702 = (uint16_t)(121); + _curvea0[238] = _6702; + uint16_t _6703 = (uint16_t)(121); + _curvea0[239] = _6703; + uint16_t _6704 = (uint16_t)(122); + _curvea0[240] = _6704; + uint16_t _6705 = (uint16_t)(122); + _curvea0[241] = _6705; + uint16_t _6706 = (uint16_t)(123); + _curvea0[242] = _6706; + uint16_t _6707 = (uint16_t)(123); + _curvea0[243] = _6707; + uint16_t _6708 = (uint16_t)(123); + _curvea0[244] = _6708; + uint16_t _6709 = (uint16_t)(124); + _curvea0[245] = _6709; + uint16_t _6710 = (uint16_t)(124); + _curvea0[246] = _6710; + uint16_t _6711 = (uint16_t)(124); + _curvea0[247] = _6711; + uint16_t _6712 = (uint16_t)(125); + _curvea0[248] = _6712; + uint16_t _6713 = (uint16_t)(125); + _curvea0[249] = _6713; + uint16_t _6714 = (uint16_t)(125); + _curvea0[250] = _6714; + uint16_t _6715 = (uint16_t)(126); + _curvea0[251] = _6715; + uint16_t _6716 = (uint16_t)(126); + _curvea0[252] = _6716; + uint16_t _6717 = (uint16_t)(126); + _curvea0[253] = _6717; + uint16_t _6718 = (uint16_t)(127); + _curvea0[254] = _6718; + uint16_t _6719 = (uint16_t)(127); + _curvea0[255] = _6719; + uint16_t _6720 = (uint16_t)(128); + _curvea0[256] = _6720; + uint16_t _6721 = (uint16_t)(128); + _curvea0[257] = _6721; + uint16_t _6722 = (uint16_t)(128); + _curvea0[258] = _6722; + uint16_t _6723 = (uint16_t)(129); + _curvea0[259] = _6723; + uint16_t _6724 = (uint16_t)(129); + _curvea0[260] = _6724; + uint16_t _6725 = (uint16_t)(129); + _curvea0[261] = _6725; + uint16_t _6726 = (uint16_t)(130); + _curvea0[262] = _6726; + uint16_t _6727 = (uint16_t)(130); + _curvea0[263] = _6727; + uint16_t _6728 = (uint16_t)(130); + _curvea0[264] = _6728; + uint16_t _6729 = (uint16_t)(131); + _curvea0[265] = _6729; + uint16_t _6730 = (uint16_t)(131); + _curvea0[266] = _6730; + uint16_t _6731 = (uint16_t)(131); + _curvea0[267] = _6731; + uint16_t _6732 = (uint16_t)(132); + _curvea0[268] = _6732; + uint16_t _6733 = (uint16_t)(132); + _curvea0[269] = _6733; + uint16_t _6734 = (uint16_t)(132); + _curvea0[270] = _6734; + uint16_t _6735 = (uint16_t)(133); + _curvea0[271] = _6735; + uint16_t _6736 = (uint16_t)(133); + _curvea0[272] = _6736; + uint16_t _6737 = (uint16_t)(133); + _curvea0[273] = _6737; + uint16_t _6738 = (uint16_t)(134); + _curvea0[274] = _6738; + uint16_t _6739 = (uint16_t)(134); + _curvea0[275] = _6739; + uint16_t _6740 = (uint16_t)(134); + _curvea0[276] = _6740; + uint16_t _6741 = (uint16_t)(135); + _curvea0[277] = _6741; + uint16_t _6742 = (uint16_t)(135); + _curvea0[278] = _6742; + uint16_t _6743 = (uint16_t)(135); + _curvea0[279] = _6743; + uint16_t _6744 = (uint16_t)(136); + _curvea0[280] = _6744; + uint16_t _6745 = (uint16_t)(136); + _curvea0[281] = _6745; + uint16_t _6746 = (uint16_t)(136); + _curvea0[282] = _6746; + uint16_t _6747 = (uint16_t)(137); + _curvea0[283] = _6747; + uint16_t _6748 = (uint16_t)(137); + _curvea0[284] = _6748; + uint16_t _6749 = (uint16_t)(137); + _curvea0[285] = _6749; + uint16_t _6750 = (uint16_t)(138); + _curvea0[286] = _6750; + uint16_t _6751 = (uint16_t)(138); + _curvea0[287] = _6751; + uint16_t _6752 = (uint16_t)(138); + _curvea0[288] = _6752; + uint16_t _6753 = (uint16_t)(139); + _curvea0[289] = _6753; + uint16_t _6754 = (uint16_t)(139); + _curvea0[290] = _6754; + uint16_t _6755 = (uint16_t)(139); + _curvea0[291] = _6755; + uint16_t _6756 = (uint16_t)(140); + _curvea0[292] = _6756; + uint16_t _6757 = (uint16_t)(140); + _curvea0[293] = _6757; + uint16_t _6758 = (uint16_t)(140); + _curvea0[294] = _6758; + uint16_t _6759 = (uint16_t)(141); + _curvea0[295] = _6759; + uint16_t _6760 = (uint16_t)(141); + _curvea0[296] = _6760; + uint16_t _6761 = (uint16_t)(141); + _curvea0[297] = _6761; + uint16_t _6762 = (uint16_t)(141); + _curvea0[298] = _6762; + uint16_t _6763 = (uint16_t)(142); + _curvea0[299] = _6763; + uint16_t _6764 = (uint16_t)(142); + _curvea0[300] = _6764; + uint16_t _6765 = (uint16_t)(142); + _curvea0[301] = _6765; + uint16_t _6766 = (uint16_t)(143); + _curvea0[302] = _6766; + uint16_t _6767 = (uint16_t)(143); + _curvea0[303] = _6767; + uint16_t _6768 = (uint16_t)(143); + _curvea0[304] = _6768; + uint16_t _6769 = (uint16_t)(144); + _curvea0[305] = _6769; + uint16_t _6770 = (uint16_t)(144); + _curvea0[306] = _6770; + uint16_t _6771 = (uint16_t)(144); + _curvea0[307] = _6771; + uint16_t _6772 = (uint16_t)(145); + _curvea0[308] = _6772; + uint16_t _6773 = (uint16_t)(145); + _curvea0[309] = _6773; + uint16_t _6774 = (uint16_t)(145); + _curvea0[310] = _6774; + uint16_t _6775 = (uint16_t)(145); + _curvea0[311] = _6775; + uint16_t _6776 = (uint16_t)(146); + _curvea0[312] = _6776; + uint16_t _6777 = (uint16_t)(146); + _curvea0[313] = _6777; + uint16_t _6778 = (uint16_t)(146); + _curvea0[314] = _6778; + uint16_t _6779 = (uint16_t)(147); + _curvea0[315] = _6779; + uint16_t _6780 = (uint16_t)(147); + _curvea0[316] = _6780; + uint16_t _6781 = (uint16_t)(147); + _curvea0[317] = _6781; + uint16_t _6782 = (uint16_t)(148); + _curvea0[318] = _6782; + uint16_t _6783 = (uint16_t)(148); + _curvea0[319] = _6783; + uint16_t _6784 = (uint16_t)(148); + _curvea0[320] = _6784; + uint16_t _6785 = (uint16_t)(148); + _curvea0[321] = _6785; + uint16_t _6786 = (uint16_t)(149); + _curvea0[322] = _6786; + uint16_t _6787 = (uint16_t)(149); + _curvea0[323] = _6787; + uint16_t _6788 = (uint16_t)(149); + _curvea0[324] = _6788; + uint16_t _6789 = (uint16_t)(150); + _curvea0[325] = _6789; + uint16_t _6790 = (uint16_t)(150); + _curvea0[326] = _6790; + uint16_t _6791 = (uint16_t)(150); + _curvea0[327] = _6791; + uint16_t _6792 = (uint16_t)(150); + _curvea0[328] = _6792; + uint16_t _6793 = (uint16_t)(151); + _curvea0[329] = _6793; + uint16_t _6794 = (uint16_t)(151); + _curvea0[330] = _6794; + uint16_t _6795 = (uint16_t)(151); + _curvea0[331] = _6795; + uint16_t _6796 = (uint16_t)(152); + _curvea0[332] = _6796; + uint16_t _6797 = (uint16_t)(152); + _curvea0[333] = _6797; + uint16_t _6798 = (uint16_t)(152); + _curvea0[334] = _6798; + uint16_t _6799 = (uint16_t)(152); + _curvea0[335] = _6799; + uint16_t _6800 = (uint16_t)(153); + _curvea0[336] = _6800; + uint16_t _6801 = (uint16_t)(153); + _curvea0[337] = _6801; + uint16_t _6802 = (uint16_t)(153); + _curvea0[338] = _6802; + uint16_t _6803 = (uint16_t)(154); + _curvea0[339] = _6803; + uint16_t _6804 = (uint16_t)(154); + _curvea0[340] = _6804; + uint16_t _6805 = (uint16_t)(154); + _curvea0[341] = _6805; + uint16_t _6806 = (uint16_t)(154); + _curvea0[342] = _6806; + uint16_t _6807 = (uint16_t)(155); + _curvea0[343] = _6807; + uint16_t _6808 = (uint16_t)(155); + _curvea0[344] = _6808; + uint16_t _6809 = (uint16_t)(155); + _curvea0[345] = _6809; + uint16_t _6810 = (uint16_t)(156); + _curvea0[346] = _6810; + uint16_t _6811 = (uint16_t)(156); + _curvea0[347] = _6811; + uint16_t _6812 = (uint16_t)(156); + _curvea0[348] = _6812; + uint16_t _6813 = (uint16_t)(156); + _curvea0[349] = _6813; + uint16_t _6814 = (uint16_t)(157); + _curvea0[350] = _6814; + uint16_t _6815 = (uint16_t)(157); + _curvea0[351] = _6815; + uint16_t _6816 = (uint16_t)(157); + _curvea0[352] = _6816; + uint16_t _6817 = (uint16_t)(157); + _curvea0[353] = _6817; + uint16_t _6818 = (uint16_t)(158); + _curvea0[354] = _6818; + uint16_t _6819 = (uint16_t)(158); + _curvea0[355] = _6819; + uint16_t _6820 = (uint16_t)(158); + _curvea0[356] = _6820; + uint16_t _6821 = (uint16_t)(159); + _curvea0[357] = _6821; + uint16_t _6822 = (uint16_t)(159); + _curvea0[358] = _6822; + uint16_t _6823 = (uint16_t)(159); + _curvea0[359] = _6823; + uint16_t _6824 = (uint16_t)(159); + _curvea0[360] = _6824; + uint16_t _6825 = (uint16_t)(160); + _curvea0[361] = _6825; + uint16_t _6826 = (uint16_t)(160); + _curvea0[362] = _6826; + uint16_t _6827 = (uint16_t)(160); + _curvea0[363] = _6827; + uint16_t _6828 = (uint16_t)(160); + _curvea0[364] = _6828; + uint16_t _6829 = (uint16_t)(161); + _curvea0[365] = _6829; + uint16_t _6830 = (uint16_t)(161); + _curvea0[366] = _6830; + uint16_t _6831 = (uint16_t)(161); + _curvea0[367] = _6831; + uint16_t _6832 = (uint16_t)(161); + _curvea0[368] = _6832; + uint16_t _6833 = (uint16_t)(162); + _curvea0[369] = _6833; + uint16_t _6834 = (uint16_t)(162); + _curvea0[370] = _6834; + uint16_t _6835 = (uint16_t)(162); + _curvea0[371] = _6835; + uint16_t _6836 = (uint16_t)(162); + _curvea0[372] = _6836; + uint16_t _6837 = (uint16_t)(163); + _curvea0[373] = _6837; + uint16_t _6838 = (uint16_t)(163); + _curvea0[374] = _6838; + uint16_t _6839 = (uint16_t)(163); + _curvea0[375] = _6839; + uint16_t _6840 = (uint16_t)(163); + _curvea0[376] = _6840; + uint16_t _6841 = (uint16_t)(164); + _curvea0[377] = _6841; + uint16_t _6842 = (uint16_t)(164); + _curvea0[378] = _6842; + uint16_t _6843 = (uint16_t)(164); + _curvea0[379] = _6843; + uint16_t _6844 = (uint16_t)(164); + _curvea0[380] = _6844; + uint16_t _6845 = (uint16_t)(165); + _curvea0[381] = _6845; + uint16_t _6846 = (uint16_t)(165); + _curvea0[382] = _6846; + uint16_t _6847 = (uint16_t)(165); + _curvea0[383] = _6847; + uint16_t _6848 = (uint16_t)(166); + _curvea0[384] = _6848; + uint16_t _6849 = (uint16_t)(166); + _curvea0[385] = _6849; + uint16_t _6850 = (uint16_t)(166); + _curvea0[386] = _6850; + uint16_t _6851 = (uint16_t)(166); + _curvea0[387] = _6851; + uint16_t _6852 = (uint16_t)(167); + _curvea0[388] = _6852; + uint16_t _6853 = (uint16_t)(167); + _curvea0[389] = _6853; + uint16_t _6854 = (uint16_t)(167); + _curvea0[390] = _6854; + uint16_t _6855 = (uint16_t)(167); + _curvea0[391] = _6855; + uint16_t _6856 = (uint16_t)(167); + _curvea0[392] = _6856; + uint16_t _6857 = (uint16_t)(168); + _curvea0[393] = _6857; + uint16_t _6858 = (uint16_t)(168); + _curvea0[394] = _6858; + uint16_t _6859 = (uint16_t)(168); + _curvea0[395] = _6859; + uint16_t _6860 = (uint16_t)(168); + _curvea0[396] = _6860; + uint16_t _6861 = (uint16_t)(169); + _curvea0[397] = _6861; + uint16_t _6862 = (uint16_t)(169); + _curvea0[398] = _6862; + uint16_t _6863 = (uint16_t)(169); + _curvea0[399] = _6863; + uint16_t _6864 = (uint16_t)(169); + _curvea0[400] = _6864; + uint16_t _6865 = (uint16_t)(170); + _curvea0[401] = _6865; + uint16_t _6866 = (uint16_t)(170); + _curvea0[402] = _6866; + uint16_t _6867 = (uint16_t)(170); + _curvea0[403] = _6867; + uint16_t _6868 = (uint16_t)(170); + _curvea0[404] = _6868; + uint16_t _6869 = (uint16_t)(171); + _curvea0[405] = _6869; + uint16_t _6870 = (uint16_t)(171); + _curvea0[406] = _6870; + uint16_t _6871 = (uint16_t)(171); + _curvea0[407] = _6871; + uint16_t _6872 = (uint16_t)(171); + _curvea0[408] = _6872; + uint16_t _6873 = (uint16_t)(172); + _curvea0[409] = _6873; + uint16_t _6874 = (uint16_t)(172); + _curvea0[410] = _6874; + uint16_t _6875 = (uint16_t)(172); + _curvea0[411] = _6875; + uint16_t _6876 = (uint16_t)(172); + _curvea0[412] = _6876; + uint16_t _6877 = (uint16_t)(173); + _curvea0[413] = _6877; + uint16_t _6878 = (uint16_t)(173); + _curvea0[414] = _6878; + uint16_t _6879 = (uint16_t)(173); + _curvea0[415] = _6879; + uint16_t _6880 = (uint16_t)(173); + _curvea0[416] = _6880; + uint16_t _6881 = (uint16_t)(173); + _curvea0[417] = _6881; + uint16_t _6882 = (uint16_t)(174); + _curvea0[418] = _6882; + uint16_t _6883 = (uint16_t)(174); + _curvea0[419] = _6883; + uint16_t _6884 = (uint16_t)(174); + _curvea0[420] = _6884; + uint16_t _6885 = (uint16_t)(174); + _curvea0[421] = _6885; + uint16_t _6886 = (uint16_t)(175); + _curvea0[422] = _6886; + uint16_t _6887 = (uint16_t)(175); + _curvea0[423] = _6887; + uint16_t _6888 = (uint16_t)(175); + _curvea0[424] = _6888; + uint16_t _6889 = (uint16_t)(175); + _curvea0[425] = _6889; + uint16_t _6890 = (uint16_t)(176); + _curvea0[426] = _6890; + uint16_t _6891 = (uint16_t)(176); + _curvea0[427] = _6891; + uint16_t _6892 = (uint16_t)(176); + _curvea0[428] = _6892; + uint16_t _6893 = (uint16_t)(176); + _curvea0[429] = _6893; + uint16_t _6894 = (uint16_t)(176); + _curvea0[430] = _6894; + uint16_t _6895 = (uint16_t)(177); + _curvea0[431] = _6895; + uint16_t _6896 = (uint16_t)(177); + _curvea0[432] = _6896; + uint16_t _6897 = (uint16_t)(177); + _curvea0[433] = _6897; + uint16_t _6898 = (uint16_t)(177); + _curvea0[434] = _6898; + uint16_t _6899 = (uint16_t)(178); + _curvea0[435] = _6899; + uint16_t _6900 = (uint16_t)(178); + _curvea0[436] = _6900; + uint16_t _6901 = (uint16_t)(178); + _curvea0[437] = _6901; + uint16_t _6902 = (uint16_t)(178); + _curvea0[438] = _6902; + uint16_t _6903 = (uint16_t)(178); + _curvea0[439] = _6903; + uint16_t _6904 = (uint16_t)(179); + _curvea0[440] = _6904; + uint16_t _6905 = (uint16_t)(179); + _curvea0[441] = _6905; + uint16_t _6906 = (uint16_t)(179); + _curvea0[442] = _6906; + uint16_t _6907 = (uint16_t)(179); + _curvea0[443] = _6907; + uint16_t _6908 = (uint16_t)(180); + _curvea0[444] = _6908; + uint16_t _6909 = (uint16_t)(180); + _curvea0[445] = _6909; + uint16_t _6910 = (uint16_t)(180); + _curvea0[446] = _6910; + uint16_t _6911 = (uint16_t)(180); + _curvea0[447] = _6911; + uint16_t _6912 = (uint16_t)(180); + _curvea0[448] = _6912; + uint16_t _6913 = (uint16_t)(181); + _curvea0[449] = _6913; + uint16_t _6914 = (uint16_t)(181); + _curvea0[450] = _6914; + uint16_t _6915 = (uint16_t)(181); + _curvea0[451] = _6915; + uint16_t _6916 = (uint16_t)(181); + _curvea0[452] = _6916; + uint16_t _6917 = (uint16_t)(181); + _curvea0[453] = _6917; + uint16_t _6918 = (uint16_t)(182); + _curvea0[454] = _6918; + uint16_t _6919 = (uint16_t)(182); + _curvea0[455] = _6919; + uint16_t _6920 = (uint16_t)(182); + _curvea0[456] = _6920; + uint16_t _6921 = (uint16_t)(182); + _curvea0[457] = _6921; + uint16_t _6922 = (uint16_t)(183); + _curvea0[458] = _6922; + uint16_t _6923 = (uint16_t)(183); + _curvea0[459] = _6923; + uint16_t _6924 = (uint16_t)(183); + _curvea0[460] = _6924; + uint16_t _6925 = (uint16_t)(183); + _curvea0[461] = _6925; + uint16_t _6926 = (uint16_t)(183); + _curvea0[462] = _6926; + uint16_t _6927 = (uint16_t)(184); + _curvea0[463] = _6927; + uint16_t _6928 = (uint16_t)(184); + _curvea0[464] = _6928; + uint16_t _6929 = (uint16_t)(184); + _curvea0[465] = _6929; + uint16_t _6930 = (uint16_t)(184); + _curvea0[466] = _6930; + uint16_t _6931 = (uint16_t)(184); + _curvea0[467] = _6931; + uint16_t _6932 = (uint16_t)(185); + _curvea0[468] = _6932; + uint16_t _6933 = (uint16_t)(185); + _curvea0[469] = _6933; + uint16_t _6934 = (uint16_t)(185); + _curvea0[470] = _6934; + uint16_t _6935 = (uint16_t)(185); + _curvea0[471] = _6935; + uint16_t _6936 = (uint16_t)(185); + _curvea0[472] = _6936; + uint16_t _6937 = (uint16_t)(186); + _curvea0[473] = _6937; + uint16_t _6938 = (uint16_t)(186); + _curvea0[474] = _6938; + uint16_t _6939 = (uint16_t)(186); + _curvea0[475] = _6939; + uint16_t _6940 = (uint16_t)(186); + _curvea0[476] = _6940; + uint16_t _6941 = (uint16_t)(187); + _curvea0[477] = _6941; + uint16_t _6942 = (uint16_t)(187); + _curvea0[478] = _6942; + uint16_t _6943 = (uint16_t)(187); + _curvea0[479] = _6943; + uint16_t _6944 = (uint16_t)(187); + _curvea0[480] = _6944; + uint16_t _6945 = (uint16_t)(187); + _curvea0[481] = _6945; + uint16_t _6946 = (uint16_t)(188); + _curvea0[482] = _6946; + uint16_t _6947 = (uint16_t)(188); + _curvea0[483] = _6947; + uint16_t _6948 = (uint16_t)(188); + _curvea0[484] = _6948; + uint16_t _6949 = (uint16_t)(188); + _curvea0[485] = _6949; + uint16_t _6950 = (uint16_t)(188); + _curvea0[486] = _6950; + uint16_t _6951 = (uint16_t)(189); + _curvea0[487] = _6951; + uint16_t _6952 = (uint16_t)(189); + _curvea0[488] = _6952; + uint16_t _6953 = (uint16_t)(189); + _curvea0[489] = _6953; + uint16_t _6954 = (uint16_t)(189); + _curvea0[490] = _6954; + uint16_t _6955 = (uint16_t)(189); + _curvea0[491] = _6955; + uint16_t _6956 = (uint16_t)(190); + _curvea0[492] = _6956; + uint16_t _6957 = (uint16_t)(190); + _curvea0[493] = _6957; + uint16_t _6958 = (uint16_t)(190); + _curvea0[494] = _6958; + uint16_t _6959 = (uint16_t)(190); + _curvea0[495] = _6959; + uint16_t _6960 = (uint16_t)(190); + _curvea0[496] = _6960; + uint16_t _6961 = (uint16_t)(190); + _curvea0[497] = _6961; + uint16_t _6962 = (uint16_t)(191); + _curvea0[498] = _6962; + uint16_t _6963 = (uint16_t)(191); + _curvea0[499] = _6963; + uint16_t _6964 = (uint16_t)(191); + _curvea0[500] = _6964; + uint16_t _6965 = (uint16_t)(191); + _curvea0[501] = _6965; + uint16_t _6966 = (uint16_t)(191); + _curvea0[502] = _6966; + uint16_t _6967 = (uint16_t)(192); + _curvea0[503] = _6967; + uint16_t _6968 = (uint16_t)(192); + _curvea0[504] = _6968; + uint16_t _6969 = (uint16_t)(192); + _curvea0[505] = _6969; + uint16_t _6970 = (uint16_t)(192); + _curvea0[506] = _6970; + uint16_t _6971 = (uint16_t)(192); + _curvea0[507] = _6971; + uint16_t _6972 = (uint16_t)(193); + _curvea0[508] = _6972; + uint16_t _6973 = (uint16_t)(193); + _curvea0[509] = _6973; + uint16_t _6974 = (uint16_t)(193); + _curvea0[510] = _6974; + uint16_t _6975 = (uint16_t)(193); + _curvea0[511] = _6975; + uint16_t _6976 = (uint16_t)(193); + _curvea0[512] = _6976; + uint16_t _6977 = (uint16_t)(194); + _curvea0[513] = _6977; + uint16_t _6978 = (uint16_t)(194); + _curvea0[514] = _6978; + uint16_t _6979 = (uint16_t)(194); + _curvea0[515] = _6979; + uint16_t _6980 = (uint16_t)(194); + _curvea0[516] = _6980; + uint16_t _6981 = (uint16_t)(194); + _curvea0[517] = _6981; + uint16_t _6982 = (uint16_t)(195); + _curvea0[518] = _6982; + uint16_t _6983 = (uint16_t)(195); + _curvea0[519] = _6983; + uint16_t _6984 = (uint16_t)(195); + _curvea0[520] = _6984; + uint16_t _6985 = (uint16_t)(195); + _curvea0[521] = _6985; + uint16_t _6986 = (uint16_t)(195); + _curvea0[522] = _6986; + uint16_t _6987 = (uint16_t)(195); + _curvea0[523] = _6987; + uint16_t _6988 = (uint16_t)(196); + _curvea0[524] = _6988; + uint16_t _6989 = (uint16_t)(196); + _curvea0[525] = _6989; + uint16_t _6990 = (uint16_t)(196); + _curvea0[526] = _6990; + uint16_t _6991 = (uint16_t)(196); + _curvea0[527] = _6991; + uint16_t _6992 = (uint16_t)(196); + _curvea0[528] = _6992; + uint16_t _6993 = (uint16_t)(197); + _curvea0[529] = _6993; + uint16_t _6994 = (uint16_t)(197); + _curvea0[530] = _6994; + uint16_t _6995 = (uint16_t)(197); + _curvea0[531] = _6995; + uint16_t _6996 = (uint16_t)(197); + _curvea0[532] = _6996; + uint16_t _6997 = (uint16_t)(197); + _curvea0[533] = _6997; + uint16_t _6998 = (uint16_t)(197); + _curvea0[534] = _6998; + uint16_t _6999 = (uint16_t)(198); + _curvea0[535] = _6999; + uint16_t _7000 = (uint16_t)(198); + _curvea0[536] = _7000; + uint16_t _7001 = (uint16_t)(198); + _curvea0[537] = _7001; + uint16_t _7002 = (uint16_t)(198); + _curvea0[538] = _7002; + uint16_t _7003 = (uint16_t)(198); + _curvea0[539] = _7003; + uint16_t _7004 = (uint16_t)(199); + _curvea0[540] = _7004; + uint16_t _7005 = (uint16_t)(199); + _curvea0[541] = _7005; + uint16_t _7006 = (uint16_t)(199); + _curvea0[542] = _7006; + uint16_t _7007 = (uint16_t)(199); + _curvea0[543] = _7007; + uint16_t _7008 = (uint16_t)(199); + _curvea0[544] = _7008; + uint16_t _7009 = (uint16_t)(199); + _curvea0[545] = _7009; + uint16_t _7010 = (uint16_t)(200); + _curvea0[546] = _7010; + uint16_t _7011 = (uint16_t)(200); + _curvea0[547] = _7011; + uint16_t _7012 = (uint16_t)(200); + _curvea0[548] = _7012; + uint16_t _7013 = (uint16_t)(200); + _curvea0[549] = _7013; + uint16_t _7014 = (uint16_t)(200); + _curvea0[550] = _7014; + uint16_t _7015 = (uint16_t)(200); + _curvea0[551] = _7015; + uint16_t _7016 = (uint16_t)(201); + _curvea0[552] = _7016; + uint16_t _7017 = (uint16_t)(201); + _curvea0[553] = _7017; + uint16_t _7018 = (uint16_t)(201); + _curvea0[554] = _7018; + uint16_t _7019 = (uint16_t)(201); + _curvea0[555] = _7019; + uint16_t _7020 = (uint16_t)(201); + _curvea0[556] = _7020; + uint16_t _7021 = (uint16_t)(202); + _curvea0[557] = _7021; + uint16_t _7022 = (uint16_t)(202); + _curvea0[558] = _7022; + uint16_t _7023 = (uint16_t)(202); + _curvea0[559] = _7023; + uint16_t _7024 = (uint16_t)(202); + _curvea0[560] = _7024; + uint16_t _7025 = (uint16_t)(202); + _curvea0[561] = _7025; + uint16_t _7026 = (uint16_t)(202); + _curvea0[562] = _7026; + uint16_t _7027 = (uint16_t)(203); + _curvea0[563] = _7027; + uint16_t _7028 = (uint16_t)(203); + _curvea0[564] = _7028; + uint16_t _7029 = (uint16_t)(203); + _curvea0[565] = _7029; + uint16_t _7030 = (uint16_t)(203); + _curvea0[566] = _7030; + uint16_t _7031 = (uint16_t)(203); + _curvea0[567] = _7031; + uint16_t _7032 = (uint16_t)(203); + _curvea0[568] = _7032; + uint16_t _7033 = (uint16_t)(204); + _curvea0[569] = _7033; + uint16_t _7034 = (uint16_t)(204); + _curvea0[570] = _7034; + uint16_t _7035 = (uint16_t)(204); + _curvea0[571] = _7035; + uint16_t _7036 = (uint16_t)(204); + _curvea0[572] = _7036; + uint16_t _7037 = (uint16_t)(204); + _curvea0[573] = _7037; + uint16_t _7038 = (uint16_t)(204); + _curvea0[574] = _7038; + uint16_t _7039 = (uint16_t)(205); + _curvea0[575] = _7039; + uint16_t _7040 = (uint16_t)(205); + _curvea0[576] = _7040; + uint16_t _7041 = (uint16_t)(205); + _curvea0[577] = _7041; + uint16_t _7042 = (uint16_t)(205); + _curvea0[578] = _7042; + uint16_t _7043 = (uint16_t)(205); + _curvea0[579] = _7043; + uint16_t _7044 = (uint16_t)(205); + _curvea0[580] = _7044; + uint16_t _7045 = (uint16_t)(206); + _curvea0[581] = _7045; + uint16_t _7046 = (uint16_t)(206); + _curvea0[582] = _7046; + uint16_t _7047 = (uint16_t)(206); + _curvea0[583] = _7047; + uint16_t _7048 = (uint16_t)(206); + _curvea0[584] = _7048; + uint16_t _7049 = (uint16_t)(206); + _curvea0[585] = _7049; + uint16_t _7050 = (uint16_t)(206); + _curvea0[586] = _7050; + uint16_t _7051 = (uint16_t)(207); + _curvea0[587] = _7051; + uint16_t _7052 = (uint16_t)(207); + _curvea0[588] = _7052; + uint16_t _7053 = (uint16_t)(207); + _curvea0[589] = _7053; + uint16_t _7054 = (uint16_t)(207); + _curvea0[590] = _7054; + uint16_t _7055 = (uint16_t)(207); + _curvea0[591] = _7055; + uint16_t _7056 = (uint16_t)(207); + _curvea0[592] = _7056; + uint16_t _7057 = (uint16_t)(208); + _curvea0[593] = _7057; + uint16_t _7058 = (uint16_t)(208); + _curvea0[594] = _7058; + uint16_t _7059 = (uint16_t)(208); + _curvea0[595] = _7059; + uint16_t _7060 = (uint16_t)(208); + _curvea0[596] = _7060; + uint16_t _7061 = (uint16_t)(208); + _curvea0[597] = _7061; + uint16_t _7062 = (uint16_t)(208); + _curvea0[598] = _7062; + uint16_t _7063 = (uint16_t)(209); + _curvea0[599] = _7063; + uint16_t _7064 = (uint16_t)(209); + _curvea0[600] = _7064; + uint16_t _7065 = (uint16_t)(209); + _curvea0[601] = _7065; + uint16_t _7066 = (uint16_t)(209); + _curvea0[602] = _7066; + uint16_t _7067 = (uint16_t)(209); + _curvea0[603] = _7067; + uint16_t _7068 = (uint16_t)(209); + _curvea0[604] = _7068; + uint16_t _7069 = (uint16_t)(209); + _curvea0[605] = _7069; + uint16_t _7070 = (uint16_t)(210); + _curvea0[606] = _7070; + uint16_t _7071 = (uint16_t)(210); + _curvea0[607] = _7071; + uint16_t _7072 = (uint16_t)(210); + _curvea0[608] = _7072; + uint16_t _7073 = (uint16_t)(210); + _curvea0[609] = _7073; + uint16_t _7074 = (uint16_t)(210); + _curvea0[610] = _7074; + uint16_t _7075 = (uint16_t)(210); + _curvea0[611] = _7075; + uint16_t _7076 = (uint16_t)(211); + _curvea0[612] = _7076; + uint16_t _7077 = (uint16_t)(211); + _curvea0[613] = _7077; + uint16_t _7078 = (uint16_t)(211); + _curvea0[614] = _7078; + uint16_t _7079 = (uint16_t)(211); + _curvea0[615] = _7079; + uint16_t _7080 = (uint16_t)(211); + _curvea0[616] = _7080; + uint16_t _7081 = (uint16_t)(211); + _curvea0[617] = _7081; + uint16_t _7082 = (uint16_t)(211); + _curvea0[618] = _7082; + uint16_t _7083 = (uint16_t)(212); + _curvea0[619] = _7083; + uint16_t _7084 = (uint16_t)(212); + _curvea0[620] = _7084; + uint16_t _7085 = (uint16_t)(212); + _curvea0[621] = _7085; + uint16_t _7086 = (uint16_t)(212); + _curvea0[622] = _7086; + uint16_t _7087 = (uint16_t)(212); + _curvea0[623] = _7087; + uint16_t _7088 = (uint16_t)(212); + _curvea0[624] = _7088; + uint16_t _7089 = (uint16_t)(213); + _curvea0[625] = _7089; + uint16_t _7090 = (uint16_t)(213); + _curvea0[626] = _7090; + uint16_t _7091 = (uint16_t)(213); + _curvea0[627] = _7091; + uint16_t _7092 = (uint16_t)(213); + _curvea0[628] = _7092; + uint16_t _7093 = (uint16_t)(213); + _curvea0[629] = _7093; + uint16_t _7094 = (uint16_t)(213); + _curvea0[630] = _7094; + uint16_t _7095 = (uint16_t)(213); + _curvea0[631] = _7095; + uint16_t _7096 = (uint16_t)(214); + _curvea0[632] = _7096; + uint16_t _7097 = (uint16_t)(214); + _curvea0[633] = _7097; + uint16_t _7098 = (uint16_t)(214); + _curvea0[634] = _7098; + uint16_t _7099 = (uint16_t)(214); + _curvea0[635] = _7099; + uint16_t _7100 = (uint16_t)(214); + _curvea0[636] = _7100; + uint16_t _7101 = (uint16_t)(214); + _curvea0[637] = _7101; + uint16_t _7102 = (uint16_t)(214); + _curvea0[638] = _7102; + uint16_t _7103 = (uint16_t)(215); + _curvea0[639] = _7103; + uint16_t _7104 = (uint16_t)(215); + _curvea0[640] = _7104; + uint16_t _7105 = (uint16_t)(215); + _curvea0[641] = _7105; + uint16_t _7106 = (uint16_t)(215); + _curvea0[642] = _7106; + uint16_t _7107 = (uint16_t)(215); + _curvea0[643] = _7107; + uint16_t _7108 = (uint16_t)(215); + _curvea0[644] = _7108; + uint16_t _7109 = (uint16_t)(216); + _curvea0[645] = _7109; + uint16_t _7110 = (uint16_t)(216); + _curvea0[646] = _7110; + uint16_t _7111 = (uint16_t)(216); + _curvea0[647] = _7111; + uint16_t _7112 = (uint16_t)(216); + _curvea0[648] = _7112; + uint16_t _7113 = (uint16_t)(216); + _curvea0[649] = _7113; + uint16_t _7114 = (uint16_t)(216); + _curvea0[650] = _7114; + uint16_t _7115 = (uint16_t)(216); + _curvea0[651] = _7115; + uint16_t _7116 = (uint16_t)(217); + _curvea0[652] = _7116; + uint16_t _7117 = (uint16_t)(217); + _curvea0[653] = _7117; + uint16_t _7118 = (uint16_t)(217); + _curvea0[654] = _7118; + uint16_t _7119 = (uint16_t)(217); + _curvea0[655] = _7119; + uint16_t _7120 = (uint16_t)(217); + _curvea0[656] = _7120; + uint16_t _7121 = (uint16_t)(217); + _curvea0[657] = _7121; + uint16_t _7122 = (uint16_t)(217); + _curvea0[658] = _7122; + uint16_t _7123 = (uint16_t)(218); + _curvea0[659] = _7123; + uint16_t _7124 = (uint16_t)(218); + _curvea0[660] = _7124; + uint16_t _7125 = (uint16_t)(218); + _curvea0[661] = _7125; + uint16_t _7126 = (uint16_t)(218); + _curvea0[662] = _7126; + uint16_t _7127 = (uint16_t)(218); + _curvea0[663] = _7127; + uint16_t _7128 = (uint16_t)(218); + _curvea0[664] = _7128; + uint16_t _7129 = (uint16_t)(218); + _curvea0[665] = _7129; + uint16_t _7130 = (uint16_t)(219); + _curvea0[666] = _7130; + uint16_t _7131 = (uint16_t)(219); + _curvea0[667] = _7131; + uint16_t _7132 = (uint16_t)(219); + _curvea0[668] = _7132; + uint16_t _7133 = (uint16_t)(219); + _curvea0[669] = _7133; + uint16_t _7134 = (uint16_t)(219); + _curvea0[670] = _7134; + uint16_t _7135 = (uint16_t)(219); + _curvea0[671] = _7135; + uint16_t _7136 = (uint16_t)(219); + _curvea0[672] = _7136; + uint16_t _7137 = (uint16_t)(220); + _curvea0[673] = _7137; + uint16_t _7138 = (uint16_t)(220); + _curvea0[674] = _7138; + uint16_t _7139 = (uint16_t)(220); + _curvea0[675] = _7139; + uint16_t _7140 = (uint16_t)(220); + _curvea0[676] = _7140; + uint16_t _7141 = (uint16_t)(220); + _curvea0[677] = _7141; + uint16_t _7142 = (uint16_t)(220); + _curvea0[678] = _7142; + uint16_t _7143 = (uint16_t)(220); + _curvea0[679] = _7143; + uint16_t _7144 = (uint16_t)(220); + _curvea0[680] = _7144; + uint16_t _7145 = (uint16_t)(221); + _curvea0[681] = _7145; + uint16_t _7146 = (uint16_t)(221); + _curvea0[682] = _7146; + uint16_t _7147 = (uint16_t)(221); + _curvea0[683] = _7147; + uint16_t _7148 = (uint16_t)(221); + _curvea0[684] = _7148; + uint16_t _7149 = (uint16_t)(221); + _curvea0[685] = _7149; + uint16_t _7150 = (uint16_t)(221); + _curvea0[686] = _7150; + uint16_t _7151 = (uint16_t)(221); + _curvea0[687] = _7151; + uint16_t _7152 = (uint16_t)(222); + _curvea0[688] = _7152; + uint16_t _7153 = (uint16_t)(222); + _curvea0[689] = _7153; + uint16_t _7154 = (uint16_t)(222); + _curvea0[690] = _7154; + uint16_t _7155 = (uint16_t)(222); + _curvea0[691] = _7155; + uint16_t _7156 = (uint16_t)(222); + _curvea0[692] = _7156; + uint16_t _7157 = (uint16_t)(222); + _curvea0[693] = _7157; + uint16_t _7158 = (uint16_t)(222); + _curvea0[694] = _7158; + uint16_t _7159 = (uint16_t)(223); + _curvea0[695] = _7159; + uint16_t _7160 = (uint16_t)(223); + _curvea0[696] = _7160; + uint16_t _7161 = (uint16_t)(223); + _curvea0[697] = _7161; + uint16_t _7162 = (uint16_t)(223); + _curvea0[698] = _7162; + uint16_t _7163 = (uint16_t)(223); + _curvea0[699] = _7163; + uint16_t _7164 = (uint16_t)(223); + _curvea0[700] = _7164; + uint16_t _7165 = (uint16_t)(223); + _curvea0[701] = _7165; + uint16_t _7166 = (uint16_t)(223); + _curvea0[702] = _7166; + uint16_t _7167 = (uint16_t)(224); + _curvea0[703] = _7167; + uint16_t _7168 = (uint16_t)(224); + _curvea0[704] = _7168; + uint16_t _7169 = (uint16_t)(224); + _curvea0[705] = _7169; + uint16_t _7170 = (uint16_t)(224); + _curvea0[706] = _7170; + uint16_t _7171 = (uint16_t)(224); + _curvea0[707] = _7171; + uint16_t _7172 = (uint16_t)(224); + _curvea0[708] = _7172; + uint16_t _7173 = (uint16_t)(224); + _curvea0[709] = _7173; + uint16_t _7174 = (uint16_t)(224); + _curvea0[710] = _7174; + uint16_t _7175 = (uint16_t)(225); + _curvea0[711] = _7175; + uint16_t _7176 = (uint16_t)(225); + _curvea0[712] = _7176; + uint16_t _7177 = (uint16_t)(225); + _curvea0[713] = _7177; + uint16_t _7178 = (uint16_t)(225); + _curvea0[714] = _7178; + uint16_t _7179 = (uint16_t)(225); + _curvea0[715] = _7179; + uint16_t _7180 = (uint16_t)(225); + _curvea0[716] = _7180; + uint16_t _7181 = (uint16_t)(225); + _curvea0[717] = _7181; + uint16_t _7182 = (uint16_t)(226); + _curvea0[718] = _7182; + uint16_t _7183 = (uint16_t)(226); + _curvea0[719] = _7183; + uint16_t _7184 = (uint16_t)(226); + _curvea0[720] = _7184; + uint16_t _7185 = (uint16_t)(226); + _curvea0[721] = _7185; + uint16_t _7186 = (uint16_t)(226); + _curvea0[722] = _7186; + uint16_t _7187 = (uint16_t)(226); + _curvea0[723] = _7187; + uint16_t _7188 = (uint16_t)(226); + _curvea0[724] = _7188; + uint16_t _7189 = (uint16_t)(226); + _curvea0[725] = _7189; + uint16_t _7190 = (uint16_t)(227); + _curvea0[726] = _7190; + uint16_t _7191 = (uint16_t)(227); + _curvea0[727] = _7191; + uint16_t _7192 = (uint16_t)(227); + _curvea0[728] = _7192; + uint16_t _7193 = (uint16_t)(227); + _curvea0[729] = _7193; + uint16_t _7194 = (uint16_t)(227); + _curvea0[730] = _7194; + uint16_t _7195 = (uint16_t)(227); + _curvea0[731] = _7195; + uint16_t _7196 = (uint16_t)(227); + _curvea0[732] = _7196; + uint16_t _7197 = (uint16_t)(227); + _curvea0[733] = _7197; + uint16_t _7198 = (uint16_t)(228); + _curvea0[734] = _7198; + uint16_t _7199 = (uint16_t)(228); + _curvea0[735] = _7199; + uint16_t _7200 = (uint16_t)(228); + _curvea0[736] = _7200; + uint16_t _7201 = (uint16_t)(228); + _curvea0[737] = _7201; + uint16_t _7202 = (uint16_t)(228); + _curvea0[738] = _7202; + uint16_t _7203 = (uint16_t)(228); + _curvea0[739] = _7203; + uint16_t _7204 = (uint16_t)(228); + _curvea0[740] = _7204; + uint16_t _7205 = (uint16_t)(228); + _curvea0[741] = _7205; + uint16_t _7206 = (uint16_t)(228); + _curvea0[742] = _7206; + uint16_t _7207 = (uint16_t)(229); + _curvea0[743] = _7207; + uint16_t _7208 = (uint16_t)(229); + _curvea0[744] = _7208; + uint16_t _7209 = (uint16_t)(229); + _curvea0[745] = _7209; + uint16_t _7210 = (uint16_t)(229); + _curvea0[746] = _7210; + uint16_t _7211 = (uint16_t)(229); + _curvea0[747] = _7211; + uint16_t _7212 = (uint16_t)(229); + _curvea0[748] = _7212; + uint16_t _7213 = (uint16_t)(229); + _curvea0[749] = _7213; + uint16_t _7214 = (uint16_t)(229); + _curvea0[750] = _7214; + uint16_t _7215 = (uint16_t)(230); + _curvea0[751] = _7215; + uint16_t _7216 = (uint16_t)(230); + _curvea0[752] = _7216; + uint16_t _7217 = (uint16_t)(230); + _curvea0[753] = _7217; + uint16_t _7218 = (uint16_t)(230); + _curvea0[754] = _7218; + uint16_t _7219 = (uint16_t)(230); + _curvea0[755] = _7219; + uint16_t _7220 = (uint16_t)(230); + _curvea0[756] = _7220; + uint16_t _7221 = (uint16_t)(230); + _curvea0[757] = _7221; + uint16_t _7222 = (uint16_t)(230); + _curvea0[758] = _7222; + uint16_t _7223 = (uint16_t)(231); + _curvea0[759] = _7223; + uint16_t _7224 = (uint16_t)(231); + _curvea0[760] = _7224; + uint16_t _7225 = (uint16_t)(231); + _curvea0[761] = _7225; + uint16_t _7226 = (uint16_t)(231); + _curvea0[762] = _7226; + uint16_t _7227 = (uint16_t)(231); + _curvea0[763] = _7227; + uint16_t _7228 = (uint16_t)(231); + _curvea0[764] = _7228; + uint16_t _7229 = (uint16_t)(231); + _curvea0[765] = _7229; + uint16_t _7230 = (uint16_t)(231); + _curvea0[766] = _7230; + uint16_t _7231 = (uint16_t)(231); + _curvea0[767] = _7231; + uint16_t _7232 = (uint16_t)(232); + _curvea0[768] = _7232; + uint16_t _7233 = (uint16_t)(232); + _curvea0[769] = _7233; + uint16_t _7234 = (uint16_t)(232); + _curvea0[770] = _7234; + uint16_t _7235 = (uint16_t)(232); + _curvea0[771] = _7235; + uint16_t _7236 = (uint16_t)(232); + _curvea0[772] = _7236; + uint16_t _7237 = (uint16_t)(232); + _curvea0[773] = _7237; + uint16_t _7238 = (uint16_t)(232); + _curvea0[774] = _7238; + uint16_t _7239 = (uint16_t)(232); + _curvea0[775] = _7239; + uint16_t _7240 = (uint16_t)(233); + _curvea0[776] = _7240; + uint16_t _7241 = (uint16_t)(233); + _curvea0[777] = _7241; + uint16_t _7242 = (uint16_t)(233); + _curvea0[778] = _7242; + uint16_t _7243 = (uint16_t)(233); + _curvea0[779] = _7243; + uint16_t _7244 = (uint16_t)(233); + _curvea0[780] = _7244; + uint16_t _7245 = (uint16_t)(233); + _curvea0[781] = _7245; + uint16_t _7246 = (uint16_t)(233); + _curvea0[782] = _7246; + uint16_t _7247 = (uint16_t)(233); + _curvea0[783] = _7247; + uint16_t _7248 = (uint16_t)(233); + _curvea0[784] = _7248; + uint16_t _7249 = (uint16_t)(234); + _curvea0[785] = _7249; + uint16_t _7250 = (uint16_t)(234); + _curvea0[786] = _7250; + uint16_t _7251 = (uint16_t)(234); + _curvea0[787] = _7251; + uint16_t _7252 = (uint16_t)(234); + _curvea0[788] = _7252; + uint16_t _7253 = (uint16_t)(234); + _curvea0[789] = _7253; + uint16_t _7254 = (uint16_t)(234); + _curvea0[790] = _7254; + uint16_t _7255 = (uint16_t)(234); + _curvea0[791] = _7255; + uint16_t _7256 = (uint16_t)(234); + _curvea0[792] = _7256; + uint16_t _7257 = (uint16_t)(234); + _curvea0[793] = _7257; + uint16_t _7258 = (uint16_t)(235); + _curvea0[794] = _7258; + uint16_t _7259 = (uint16_t)(235); + _curvea0[795] = _7259; + uint16_t _7260 = (uint16_t)(235); + _curvea0[796] = _7260; + uint16_t _7261 = (uint16_t)(235); + _curvea0[797] = _7261; + uint16_t _7262 = (uint16_t)(235); + _curvea0[798] = _7262; + uint16_t _7263 = (uint16_t)(235); + _curvea0[799] = _7263; + uint16_t _7264 = (uint16_t)(235); + _curvea0[800] = _7264; + uint16_t _7265 = (uint16_t)(235); + _curvea0[801] = _7265; + uint16_t _7266 = (uint16_t)(235); + _curvea0[802] = _7266; + uint16_t _7267 = (uint16_t)(236); + _curvea0[803] = _7267; + uint16_t _7268 = (uint16_t)(236); + _curvea0[804] = _7268; + uint16_t _7269 = (uint16_t)(236); + _curvea0[805] = _7269; + uint16_t _7270 = (uint16_t)(236); + _curvea0[806] = _7270; + uint16_t _7271 = (uint16_t)(236); + _curvea0[807] = _7271; + uint16_t _7272 = (uint16_t)(236); + _curvea0[808] = _7272; + uint16_t _7273 = (uint16_t)(236); + _curvea0[809] = _7273; + uint16_t _7274 = (uint16_t)(236); + _curvea0[810] = _7274; + uint16_t _7275 = (uint16_t)(236); + _curvea0[811] = _7275; + uint16_t _7276 = (uint16_t)(237); + _curvea0[812] = _7276; + uint16_t _7277 = (uint16_t)(237); + _curvea0[813] = _7277; + uint16_t _7278 = (uint16_t)(237); + _curvea0[814] = _7278; + uint16_t _7279 = (uint16_t)(237); + _curvea0[815] = _7279; + uint16_t _7280 = (uint16_t)(237); + _curvea0[816] = _7280; + uint16_t _7281 = (uint16_t)(237); + _curvea0[817] = _7281; + uint16_t _7282 = (uint16_t)(237); + _curvea0[818] = _7282; + uint16_t _7283 = (uint16_t)(237); + _curvea0[819] = _7283; + uint16_t _7284 = (uint16_t)(237); + _curvea0[820] = _7284; + uint16_t _7285 = (uint16_t)(237); + _curvea0[821] = _7285; + uint16_t _7286 = (uint16_t)(238); + _curvea0[822] = _7286; + uint16_t _7287 = (uint16_t)(238); + _curvea0[823] = _7287; + uint16_t _7288 = (uint16_t)(238); + _curvea0[824] = _7288; + uint16_t _7289 = (uint16_t)(238); + _curvea0[825] = _7289; + uint16_t _7290 = (uint16_t)(238); + _curvea0[826] = _7290; + uint16_t _7291 = (uint16_t)(238); + _curvea0[827] = _7291; + uint16_t _7292 = (uint16_t)(238); + _curvea0[828] = _7292; + uint16_t _7293 = (uint16_t)(238); + _curvea0[829] = _7293; + uint16_t _7294 = (uint16_t)(238); + _curvea0[830] = _7294; + uint16_t _7295 = (uint16_t)(239); + _curvea0[831] = _7295; + uint16_t _7296 = (uint16_t)(239); + _curvea0[832] = _7296; + uint16_t _7297 = (uint16_t)(239); + _curvea0[833] = _7297; + uint16_t _7298 = (uint16_t)(239); + _curvea0[834] = _7298; + uint16_t _7299 = (uint16_t)(239); + _curvea0[835] = _7299; + uint16_t _7300 = (uint16_t)(239); + _curvea0[836] = _7300; + uint16_t _7301 = (uint16_t)(239); + _curvea0[837] = _7301; + uint16_t _7302 = (uint16_t)(239); + _curvea0[838] = _7302; + uint16_t _7303 = (uint16_t)(239); + _curvea0[839] = _7303; + uint16_t _7304 = (uint16_t)(239); + _curvea0[840] = _7304; + uint16_t _7305 = (uint16_t)(240); + _curvea0[841] = _7305; + uint16_t _7306 = (uint16_t)(240); + _curvea0[842] = _7306; + uint16_t _7307 = (uint16_t)(240); + _curvea0[843] = _7307; + uint16_t _7308 = (uint16_t)(240); + _curvea0[844] = _7308; + uint16_t _7309 = (uint16_t)(240); + _curvea0[845] = _7309; + uint16_t _7310 = (uint16_t)(240); + _curvea0[846] = _7310; + uint16_t _7311 = (uint16_t)(240); + _curvea0[847] = _7311; + uint16_t _7312 = (uint16_t)(240); + _curvea0[848] = _7312; + uint16_t _7313 = (uint16_t)(240); + _curvea0[849] = _7313; + uint16_t _7314 = (uint16_t)(240); + _curvea0[850] = _7314; + uint16_t _7315 = (uint16_t)(241); + _curvea0[851] = _7315; + uint16_t _7316 = (uint16_t)(241); + _curvea0[852] = _7316; + uint16_t _7317 = (uint16_t)(241); + _curvea0[853] = _7317; + uint16_t _7318 = (uint16_t)(241); + _curvea0[854] = _7318; + uint16_t _7319 = (uint16_t)(241); + _curvea0[855] = _7319; + uint16_t _7320 = (uint16_t)(241); + _curvea0[856] = _7320; + uint16_t _7321 = (uint16_t)(241); + _curvea0[857] = _7321; + uint16_t _7322 = (uint16_t)(241); + _curvea0[858] = _7322; + uint16_t _7323 = (uint16_t)(241); + _curvea0[859] = _7323; + uint16_t _7324 = (uint16_t)(241); + _curvea0[860] = _7324; + uint16_t _7325 = (uint16_t)(242); + _curvea0[861] = _7325; + uint16_t _7326 = (uint16_t)(242); + _curvea0[862] = _7326; + uint16_t _7327 = (uint16_t)(242); + _curvea0[863] = _7327; + uint16_t _7328 = (uint16_t)(242); + _curvea0[864] = _7328; + uint16_t _7329 = (uint16_t)(242); + _curvea0[865] = _7329; + uint16_t _7330 = (uint16_t)(242); + _curvea0[866] = _7330; + uint16_t _7331 = (uint16_t)(242); + _curvea0[867] = _7331; + uint16_t _7332 = (uint16_t)(242); + _curvea0[868] = _7332; + uint16_t _7333 = (uint16_t)(242); + _curvea0[869] = _7333; + uint16_t _7334 = (uint16_t)(242); + _curvea0[870] = _7334; + uint16_t _7335 = (uint16_t)(243); + _curvea0[871] = _7335; + uint16_t _7336 = (uint16_t)(243); + _curvea0[872] = _7336; + uint16_t _7337 = (uint16_t)(243); + _curvea0[873] = _7337; + uint16_t _7338 = (uint16_t)(243); + _curvea0[874] = _7338; + uint16_t _7339 = (uint16_t)(243); + _curvea0[875] = _7339; + uint16_t _7340 = (uint16_t)(243); + _curvea0[876] = _7340; + uint16_t _7341 = (uint16_t)(243); + _curvea0[877] = _7341; + uint16_t _7342 = (uint16_t)(243); + _curvea0[878] = _7342; + uint16_t _7343 = (uint16_t)(243); + _curvea0[879] = _7343; + uint16_t _7344 = (uint16_t)(243); + _curvea0[880] = _7344; + uint16_t _7345 = (uint16_t)(244); + _curvea0[881] = _7345; + uint16_t _7346 = (uint16_t)(244); + _curvea0[882] = _7346; + uint16_t _7347 = (uint16_t)(244); + _curvea0[883] = _7347; + uint16_t _7348 = (uint16_t)(244); + _curvea0[884] = _7348; + uint16_t _7349 = (uint16_t)(244); + _curvea0[885] = _7349; + uint16_t _7350 = (uint16_t)(244); + _curvea0[886] = _7350; + uint16_t _7351 = (uint16_t)(244); + _curvea0[887] = _7351; + uint16_t _7352 = (uint16_t)(244); + _curvea0[888] = _7352; + uint16_t _7353 = (uint16_t)(244); + _curvea0[889] = _7353; + uint16_t _7354 = (uint16_t)(244); + _curvea0[890] = _7354; + uint16_t _7355 = (uint16_t)(244); + _curvea0[891] = _7355; + uint16_t _7356 = (uint16_t)(245); + _curvea0[892] = _7356; + uint16_t _7357 = (uint16_t)(245); + _curvea0[893] = _7357; + uint16_t _7358 = (uint16_t)(245); + _curvea0[894] = _7358; + uint16_t _7359 = (uint16_t)(245); + _curvea0[895] = _7359; + uint16_t _7360 = (uint16_t)(245); + _curvea0[896] = _7360; + uint16_t _7361 = (uint16_t)(245); + _curvea0[897] = _7361; + uint16_t _7362 = (uint16_t)(245); + _curvea0[898] = _7362; + uint16_t _7363 = (uint16_t)(245); + _curvea0[899] = _7363; + uint16_t _7364 = (uint16_t)(245); + _curvea0[900] = _7364; + uint16_t _7365 = (uint16_t)(245); + _curvea0[901] = _7365; + uint16_t _7366 = (uint16_t)(245); + _curvea0[902] = _7366; + uint16_t _7367 = (uint16_t)(246); + _curvea0[903] = _7367; + uint16_t _7368 = (uint16_t)(246); + _curvea0[904] = _7368; + uint16_t _7369 = (uint16_t)(246); + _curvea0[905] = _7369; + uint16_t _7370 = (uint16_t)(246); + _curvea0[906] = _7370; + uint16_t _7371 = (uint16_t)(246); + _curvea0[907] = _7371; + uint16_t _7372 = (uint16_t)(246); + _curvea0[908] = _7372; + uint16_t _7373 = (uint16_t)(246); + _curvea0[909] = _7373; + uint16_t _7374 = (uint16_t)(246); + _curvea0[910] = _7374; + uint16_t _7375 = (uint16_t)(246); + _curvea0[911] = _7375; + uint16_t _7376 = (uint16_t)(246); + _curvea0[912] = _7376; + uint16_t _7377 = (uint16_t)(246); + _curvea0[913] = _7377; + uint16_t _7378 = (uint16_t)(247); + _curvea0[914] = _7378; + uint16_t _7379 = (uint16_t)(247); + _curvea0[915] = _7379; + uint16_t _7380 = (uint16_t)(247); + _curvea0[916] = _7380; + uint16_t _7381 = (uint16_t)(247); + _curvea0[917] = _7381; + uint16_t _7382 = (uint16_t)(247); + _curvea0[918] = _7382; + uint16_t _7383 = (uint16_t)(247); + _curvea0[919] = _7383; + uint16_t _7384 = (uint16_t)(247); + _curvea0[920] = _7384; + uint16_t _7385 = (uint16_t)(247); + _curvea0[921] = _7385; + uint16_t _7386 = (uint16_t)(247); + _curvea0[922] = _7386; + uint16_t _7387 = (uint16_t)(247); + _curvea0[923] = _7387; + uint16_t _7388 = (uint16_t)(247); + _curvea0[924] = _7388; + uint16_t _7389 = (uint16_t)(248); + _curvea0[925] = _7389; + uint16_t _7390 = (uint16_t)(248); + _curvea0[926] = _7390; + uint16_t _7391 = (uint16_t)(248); + _curvea0[927] = _7391; + uint16_t _7392 = (uint16_t)(248); + _curvea0[928] = _7392; + uint16_t _7393 = (uint16_t)(248); + _curvea0[929] = _7393; + uint16_t _7394 = (uint16_t)(248); + _curvea0[930] = _7394; + uint16_t _7395 = (uint16_t)(248); + _curvea0[931] = _7395; + uint16_t _7396 = (uint16_t)(248); + _curvea0[932] = _7396; + uint16_t _7397 = (uint16_t)(248); + _curvea0[933] = _7397; + uint16_t _7398 = (uint16_t)(248); + _curvea0[934] = _7398; + uint16_t _7399 = (uint16_t)(248); + _curvea0[935] = _7399; + uint16_t _7400 = (uint16_t)(249); + _curvea0[936] = _7400; + uint16_t _7401 = (uint16_t)(249); + _curvea0[937] = _7401; + uint16_t _7402 = (uint16_t)(249); + _curvea0[938] = _7402; + uint16_t _7403 = (uint16_t)(249); + _curvea0[939] = _7403; + uint16_t _7404 = (uint16_t)(249); + _curvea0[940] = _7404; + uint16_t _7405 = (uint16_t)(249); + _curvea0[941] = _7405; + uint16_t _7406 = (uint16_t)(249); + _curvea0[942] = _7406; + uint16_t _7407 = (uint16_t)(249); + _curvea0[943] = _7407; + uint16_t _7408 = (uint16_t)(249); + _curvea0[944] = _7408; + uint16_t _7409 = (uint16_t)(249); + _curvea0[945] = _7409; + uint16_t _7410 = (uint16_t)(249); + _curvea0[946] = _7410; + uint16_t _7411 = (uint16_t)(249); + _curvea0[947] = _7411; + uint16_t _7412 = (uint16_t)(250); + _curvea0[948] = _7412; + uint16_t _7413 = (uint16_t)(250); + _curvea0[949] = _7413; + uint16_t _7414 = (uint16_t)(250); + _curvea0[950] = _7414; + uint16_t _7415 = (uint16_t)(250); + _curvea0[951] = _7415; + uint16_t _7416 = (uint16_t)(250); + _curvea0[952] = _7416; + uint16_t _7417 = (uint16_t)(250); + _curvea0[953] = _7417; + uint16_t _7418 = (uint16_t)(250); + _curvea0[954] = _7418; + uint16_t _7419 = (uint16_t)(250); + _curvea0[955] = _7419; + uint16_t _7420 = (uint16_t)(250); + _curvea0[956] = _7420; + uint16_t _7421 = (uint16_t)(250); + _curvea0[957] = _7421; + uint16_t _7422 = (uint16_t)(250); + _curvea0[958] = _7422; + uint16_t _7423 = (uint16_t)(250); + _curvea0[959] = _7423; + uint16_t _7424 = (uint16_t)(251); + _curvea0[960] = _7424; + uint16_t _7425 = (uint16_t)(251); + _curvea0[961] = _7425; + uint16_t _7426 = (uint16_t)(251); + _curvea0[962] = _7426; + uint16_t _7427 = (uint16_t)(251); + _curvea0[963] = _7427; + uint16_t _7428 = (uint16_t)(251); + _curvea0[964] = _7428; + uint16_t _7429 = (uint16_t)(251); + _curvea0[965] = _7429; + uint16_t _7430 = (uint16_t)(251); + _curvea0[966] = _7430; + uint16_t _7431 = (uint16_t)(251); + _curvea0[967] = _7431; + uint16_t _7432 = (uint16_t)(251); + _curvea0[968] = _7432; + uint16_t _7433 = (uint16_t)(251); + _curvea0[969] = _7433; + uint16_t _7434 = (uint16_t)(251); + _curvea0[970] = _7434; + uint16_t _7435 = (uint16_t)(251); + _curvea0[971] = _7435; + uint16_t _7436 = (uint16_t)(252); + _curvea0[972] = _7436; + uint16_t _7437 = (uint16_t)(252); + _curvea0[973] = _7437; + uint16_t _7438 = (uint16_t)(252); + _curvea0[974] = _7438; + uint16_t _7439 = (uint16_t)(252); + _curvea0[975] = _7439; + uint16_t _7440 = (uint16_t)(252); + _curvea0[976] = _7440; + uint16_t _7441 = (uint16_t)(252); + _curvea0[977] = _7441; + uint16_t _7442 = (uint16_t)(252); + _curvea0[978] = _7442; + uint16_t _7443 = (uint16_t)(252); + _curvea0[979] = _7443; + uint16_t _7444 = (uint16_t)(252); + _curvea0[980] = _7444; + uint16_t _7445 = (uint16_t)(252); + _curvea0[981] = _7445; + uint16_t _7446 = (uint16_t)(252); + _curvea0[982] = _7446; + uint16_t _7447 = (uint16_t)(252); + _curvea0[983] = _7447; + uint16_t _7448 = (uint16_t)(252); + _curvea0[984] = _7448; + uint16_t _7449 = (uint16_t)(253); + _curvea0[985] = _7449; + uint16_t _7450 = (uint16_t)(253); + _curvea0[986] = _7450; + uint16_t _7451 = (uint16_t)(253); + _curvea0[987] = _7451; + uint16_t _7452 = (uint16_t)(253); + _curvea0[988] = _7452; + uint16_t _7453 = (uint16_t)(253); + _curvea0[989] = _7453; + uint16_t _7454 = (uint16_t)(253); + _curvea0[990] = _7454; + uint16_t _7455 = (uint16_t)(253); + _curvea0[991] = _7455; + uint16_t _7456 = (uint16_t)(253); + _curvea0[992] = _7456; + uint16_t _7457 = (uint16_t)(253); + _curvea0[993] = _7457; + uint16_t _7458 = (uint16_t)(253); + _curvea0[994] = _7458; + uint16_t _7459 = (uint16_t)(253); + _curvea0[995] = _7459; + uint16_t _7460 = (uint16_t)(253); + _curvea0[996] = _7460; + uint16_t _7461 = (uint16_t)(253); + _curvea0[997] = _7461; + uint16_t _7462 = (uint16_t)(254); + _curvea0[998] = _7462; + uint16_t _7463 = (uint16_t)(254); + _curvea0[999] = _7463; + uint16_t _7464 = (uint16_t)(254); + _curvea0[1000] = _7464; + uint16_t _7465 = (uint16_t)(254); + _curvea0[1001] = _7465; + uint16_t _7466 = (uint16_t)(254); + _curvea0[1002] = _7466; + uint16_t _7467 = (uint16_t)(254); + _curvea0[1003] = _7467; + uint16_t _7468 = (uint16_t)(254); + _curvea0[1004] = _7468; + uint16_t _7469 = (uint16_t)(254); + _curvea0[1005] = _7469; + uint16_t _7470 = (uint16_t)(254); + _curvea0[1006] = _7470; + uint16_t _7471 = (uint16_t)(254); + _curvea0[1007] = _7471; + uint16_t _7472 = (uint16_t)(254); + _curvea0[1008] = _7472; + uint16_t _7473 = (uint16_t)(254); + _curvea0[1009] = _7473; + uint16_t _7474 = (uint16_t)(254); + _curvea0[1010] = _7474; + uint16_t _7475 = (uint16_t)(255); + _curvea0[1011] = _7475; + uint16_t _7476 = (uint16_t)(255); + _curvea0[1012] = _7476; + uint16_t _7477 = (uint16_t)(255); + _curvea0[1013] = _7477; + uint16_t _7478 = (uint16_t)(255); + _curvea0[1014] = _7478; + uint16_t _7479 = (uint16_t)(255); + _curvea0[1015] = _7479; + uint16_t _7480 = (uint16_t)(255); + _curvea0[1016] = _7480; + uint16_t _7481 = (uint16_t)(255); + _curvea0[1017] = _7481; + uint16_t _7482 = (uint16_t)(255); + _curvea0[1018] = _7482; + uint16_t _7483 = (uint16_t)(255); + _curvea0[1019] = _7483; + uint16_t _7484 = (uint16_t)(255); + _curvea0[1020] = _7484; + uint16_t _7485 = (uint16_t)(255); + _curvea0[1021] = _7485; + uint16_t _7486 = (uint16_t)(255); + _curvea0[1022] = _7486; + uint16_t _7487 = (uint16_t)(255); + _curvea0[1023] = _7487; + + int16_t _7488 = (int16_t)(1023); + int16_t _7489 = min(_corrected_stencil_5, _7488); + int16_t _7490 = (int16_t)(0); + int16_t _7491 = max(_7489, _7490); + uint16_t _7492 = (uint16_t)(_7491); + int32_t _7493 = (int32_t)(_7492); + uint16_t _7494 = ((const uint16_t *)_curvea0)[_7493]; + return _7494; +} + +//store is: curved.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] +hw_uint<16> hcompute_curved_stencil_5(hw_uint<16>& corrected_stencil) { + int16_t _corrected_stencil_6 = (int16_t) corrected_stencil.extract<0, 15>(); + + uint16_t _curvea0[1024]; + // produce curvea0 + uint16_t _7511 = (uint16_t)(0); + _curvea0[0] = _7511; + uint16_t _7512 = (uint16_t)(4); + _curvea0[1] = _7512; + uint16_t _7513 = (uint16_t)(7); + _curvea0[2] = _7513; + uint16_t _7514 = (uint16_t)(8); + _curvea0[3] = _7514; + uint16_t _7515 = (uint16_t)(10); + _curvea0[4] = _7515; + uint16_t _7516 = (uint16_t)(11); + _curvea0[5] = _7516; + uint16_t _7517 = (uint16_t)(12); + _curvea0[6] = _7517; + uint16_t _7518 = (uint16_t)(13); + _curvea0[7] = _7518; + uint16_t _7519 = (uint16_t)(14); + _curvea0[8] = _7519; + uint16_t _7520 = (uint16_t)(15); + _curvea0[9] = _7520; + uint16_t _7521 = (uint16_t)(16); + _curvea0[10] = _7521; + uint16_t _7522 = (uint16_t)(17); + _curvea0[11] = _7522; + uint16_t _7523 = (uint16_t)(18); + _curvea0[12] = _7523; + uint16_t _7524 = (uint16_t)(19); + _curvea0[13] = _7524; + uint16_t _7525 = (uint16_t)(20); + _curvea0[14] = _7525; + uint16_t _7526 = (uint16_t)(21); + _curvea0[15] = _7526; + uint16_t _7527 = (uint16_t)(22); + _curvea0[16] = _7527; + uint16_t _7528 = (uint16_t)(22); + _curvea0[17] = _7528; + uint16_t _7529 = (uint16_t)(23); + _curvea0[18] = _7529; + uint16_t _7530 = (uint16_t)(24); + _curvea0[19] = _7530; + uint16_t _7531 = (uint16_t)(25); + _curvea0[20] = _7531; + uint16_t _7532 = (uint16_t)(25); + _curvea0[21] = _7532; + uint16_t _7533 = (uint16_t)(26); + _curvea0[22] = _7533; + uint16_t _7534 = (uint16_t)(27); + _curvea0[23] = _7534; + uint16_t _7535 = (uint16_t)(27); + _curvea0[24] = _7535; + uint16_t _7536 = (uint16_t)(28); + _curvea0[25] = _7536; + uint16_t _7537 = (uint16_t)(29); + _curvea0[26] = _7537; + uint16_t _7538 = (uint16_t)(29); + _curvea0[27] = _7538; + uint16_t _7539 = (uint16_t)(30); + _curvea0[28] = _7539; + uint16_t _7540 = (uint16_t)(31); + _curvea0[29] = _7540; + uint16_t _7541 = (uint16_t)(31); + _curvea0[30] = _7541; + uint16_t _7542 = (uint16_t)(32); + _curvea0[31] = _7542; + uint16_t _7543 = (uint16_t)(33); + _curvea0[32] = _7543; + uint16_t _7544 = (uint16_t)(33); + _curvea0[33] = _7544; + uint16_t _7545 = (uint16_t)(34); + _curvea0[34] = _7545; + uint16_t _7546 = (uint16_t)(34); + _curvea0[35] = _7546; + uint16_t _7547 = (uint16_t)(35); + _curvea0[36] = _7547; + uint16_t _7548 = (uint16_t)(36); + _curvea0[37] = _7548; + uint16_t _7549 = (uint16_t)(36); + _curvea0[38] = _7549; + uint16_t _7550 = (uint16_t)(37); + _curvea0[39] = _7550; + uint16_t _7551 = (uint16_t)(37); + _curvea0[40] = _7551; + uint16_t _7552 = (uint16_t)(38); + _curvea0[41] = _7552; + uint16_t _7553 = (uint16_t)(39); + _curvea0[42] = _7553; + uint16_t _7554 = (uint16_t)(39); + _curvea0[43] = _7554; + uint16_t _7555 = (uint16_t)(40); + _curvea0[44] = _7555; + uint16_t _7556 = (uint16_t)(40); + _curvea0[45] = _7556; + uint16_t _7557 = (uint16_t)(41); + _curvea0[46] = _7557; + uint16_t _7558 = (uint16_t)(41); + _curvea0[47] = _7558; + uint16_t _7559 = (uint16_t)(42); + _curvea0[48] = _7559; + uint16_t _7560 = (uint16_t)(42); + _curvea0[49] = _7560; + uint16_t _7561 = (uint16_t)(43); + _curvea0[50] = _7561; + uint16_t _7562 = (uint16_t)(44); + _curvea0[51] = _7562; + uint16_t _7563 = (uint16_t)(44); + _curvea0[52] = _7563; + uint16_t _7564 = (uint16_t)(45); + _curvea0[53] = _7564; + uint16_t _7565 = (uint16_t)(45); + _curvea0[54] = _7565; + uint16_t _7566 = (uint16_t)(46); + _curvea0[55] = _7566; + uint16_t _7567 = (uint16_t)(46); + _curvea0[56] = _7567; + uint16_t _7568 = (uint16_t)(47); + _curvea0[57] = _7568; + uint16_t _7569 = (uint16_t)(47); + _curvea0[58] = _7569; + uint16_t _7570 = (uint16_t)(48); + _curvea0[59] = _7570; + uint16_t _7571 = (uint16_t)(48); + _curvea0[60] = _7571; + uint16_t _7572 = (uint16_t)(49); + _curvea0[61] = _7572; + uint16_t _7573 = (uint16_t)(49); + _curvea0[62] = _7573; + uint16_t _7574 = (uint16_t)(50); + _curvea0[63] = _7574; + uint16_t _7575 = (uint16_t)(50); + _curvea0[64] = _7575; + uint16_t _7576 = (uint16_t)(51); + _curvea0[65] = _7576; + uint16_t _7577 = (uint16_t)(51); + _curvea0[66] = _7577; + uint16_t _7578 = (uint16_t)(52); + _curvea0[67] = _7578; + uint16_t _7579 = (uint16_t)(52); + _curvea0[68] = _7579; + uint16_t _7580 = (uint16_t)(53); + _curvea0[69] = _7580; + uint16_t _7581 = (uint16_t)(53); + _curvea0[70] = _7581; + uint16_t _7582 = (uint16_t)(54); + _curvea0[71] = _7582; + uint16_t _7583 = (uint16_t)(54); + _curvea0[72] = _7583; + uint16_t _7584 = (uint16_t)(55); + _curvea0[73] = _7584; + uint16_t _7585 = (uint16_t)(55); + _curvea0[74] = _7585; + uint16_t _7586 = (uint16_t)(56); + _curvea0[75] = _7586; + uint16_t _7587 = (uint16_t)(56); + _curvea0[76] = _7587; + uint16_t _7588 = (uint16_t)(57); + _curvea0[77] = _7588; + uint16_t _7589 = (uint16_t)(57); + _curvea0[78] = _7589; + uint16_t _7590 = (uint16_t)(58); + _curvea0[79] = _7590; + uint16_t _7591 = (uint16_t)(58); + _curvea0[80] = _7591; + uint16_t _7592 = (uint16_t)(58); + _curvea0[81] = _7592; + uint16_t _7593 = (uint16_t)(59); + _curvea0[82] = _7593; + uint16_t _7594 = (uint16_t)(59); + _curvea0[83] = _7594; + uint16_t _7595 = (uint16_t)(60); + _curvea0[84] = _7595; + uint16_t _7596 = (uint16_t)(60); + _curvea0[85] = _7596; + uint16_t _7597 = (uint16_t)(61); + _curvea0[86] = _7597; + uint16_t _7598 = (uint16_t)(61); + _curvea0[87] = _7598; + uint16_t _7599 = (uint16_t)(62); + _curvea0[88] = _7599; + uint16_t _7600 = (uint16_t)(62); + _curvea0[89] = _7600; + uint16_t _7601 = (uint16_t)(63); + _curvea0[90] = _7601; + uint16_t _7602 = (uint16_t)(63); + _curvea0[91] = _7602; + uint16_t _7603 = (uint16_t)(64); + _curvea0[92] = _7603; + uint16_t _7604 = (uint16_t)(64); + _curvea0[93] = _7604; + uint16_t _7605 = (uint16_t)(64); + _curvea0[94] = _7605; + uint16_t _7606 = (uint16_t)(65); + _curvea0[95] = _7606; + uint16_t _7607 = (uint16_t)(65); + _curvea0[96] = _7607; + uint16_t _7608 = (uint16_t)(66); + _curvea0[97] = _7608; + uint16_t _7609 = (uint16_t)(66); + _curvea0[98] = _7609; + uint16_t _7610 = (uint16_t)(67); + _curvea0[99] = _7610; + uint16_t _7611 = (uint16_t)(67); + _curvea0[100] = _7611; + uint16_t _7612 = (uint16_t)(68); + _curvea0[101] = _7612; + uint16_t _7613 = (uint16_t)(68); + _curvea0[102] = _7613; + uint16_t _7614 = (uint16_t)(68); + _curvea0[103] = _7614; + uint16_t _7615 = (uint16_t)(69); + _curvea0[104] = _7615; + uint16_t _7616 = (uint16_t)(69); + _curvea0[105] = _7616; + uint16_t _7617 = (uint16_t)(70); + _curvea0[106] = _7617; + uint16_t _7618 = (uint16_t)(70); + _curvea0[107] = _7618; + uint16_t _7619 = (uint16_t)(71); + _curvea0[108] = _7619; + uint16_t _7620 = (uint16_t)(71); + _curvea0[109] = _7620; + uint16_t _7621 = (uint16_t)(71); + _curvea0[110] = _7621; + uint16_t _7622 = (uint16_t)(72); + _curvea0[111] = _7622; + uint16_t _7623 = (uint16_t)(72); + _curvea0[112] = _7623; + uint16_t _7624 = (uint16_t)(73); + _curvea0[113] = _7624; + uint16_t _7625 = (uint16_t)(73); + _curvea0[114] = _7625; + uint16_t _7626 = (uint16_t)(74); + _curvea0[115] = _7626; + uint16_t _7627 = (uint16_t)(74); + _curvea0[116] = _7627; + uint16_t _7628 = (uint16_t)(74); + _curvea0[117] = _7628; + uint16_t _7629 = (uint16_t)(75); + _curvea0[118] = _7629; + uint16_t _7630 = (uint16_t)(75); + _curvea0[119] = _7630; + uint16_t _7631 = (uint16_t)(76); + _curvea0[120] = _7631; + uint16_t _7632 = (uint16_t)(76); + _curvea0[121] = _7632; + uint16_t _7633 = (uint16_t)(77); + _curvea0[122] = _7633; + uint16_t _7634 = (uint16_t)(77); + _curvea0[123] = _7634; + uint16_t _7635 = (uint16_t)(77); + _curvea0[124] = _7635; + uint16_t _7636 = (uint16_t)(78); + _curvea0[125] = _7636; + uint16_t _7637 = (uint16_t)(78); + _curvea0[126] = _7637; + uint16_t _7638 = (uint16_t)(79); + _curvea0[127] = _7638; + uint16_t _7639 = (uint16_t)(79); + _curvea0[128] = _7639; + uint16_t _7640 = (uint16_t)(79); + _curvea0[129] = _7640; + uint16_t _7641 = (uint16_t)(80); + _curvea0[130] = _7641; + uint16_t _7642 = (uint16_t)(80); + _curvea0[131] = _7642; + uint16_t _7643 = (uint16_t)(81); + _curvea0[132] = _7643; + uint16_t _7644 = (uint16_t)(81); + _curvea0[133] = _7644; + uint16_t _7645 = (uint16_t)(82); + _curvea0[134] = _7645; + uint16_t _7646 = (uint16_t)(82); + _curvea0[135] = _7646; + uint16_t _7647 = (uint16_t)(82); + _curvea0[136] = _7647; + uint16_t _7648 = (uint16_t)(83); + _curvea0[137] = _7648; + uint16_t _7649 = (uint16_t)(83); + _curvea0[138] = _7649; + uint16_t _7650 = (uint16_t)(84); + _curvea0[139] = _7650; + uint16_t _7651 = (uint16_t)(84); + _curvea0[140] = _7651; + uint16_t _7652 = (uint16_t)(84); + _curvea0[141] = _7652; + uint16_t _7653 = (uint16_t)(85); + _curvea0[142] = _7653; + uint16_t _7654 = (uint16_t)(85); + _curvea0[143] = _7654; + uint16_t _7655 = (uint16_t)(86); + _curvea0[144] = _7655; + uint16_t _7656 = (uint16_t)(86); + _curvea0[145] = _7656; + uint16_t _7657 = (uint16_t)(86); + _curvea0[146] = _7657; + uint16_t _7658 = (uint16_t)(87); + _curvea0[147] = _7658; + uint16_t _7659 = (uint16_t)(87); + _curvea0[148] = _7659; + uint16_t _7660 = (uint16_t)(88); + _curvea0[149] = _7660; + uint16_t _7661 = (uint16_t)(88); + _curvea0[150] = _7661; + uint16_t _7662 = (uint16_t)(88); + _curvea0[151] = _7662; + uint16_t _7663 = (uint16_t)(89); + _curvea0[152] = _7663; + uint16_t _7664 = (uint16_t)(89); + _curvea0[153] = _7664; + uint16_t _7665 = (uint16_t)(90); + _curvea0[154] = _7665; + uint16_t _7666 = (uint16_t)(90); + _curvea0[155] = _7666; + uint16_t _7667 = (uint16_t)(90); + _curvea0[156] = _7667; + uint16_t _7668 = (uint16_t)(91); + _curvea0[157] = _7668; + uint16_t _7669 = (uint16_t)(91); + _curvea0[158] = _7669; + uint16_t _7670 = (uint16_t)(92); + _curvea0[159] = _7670; + uint16_t _7671 = (uint16_t)(92); + _curvea0[160] = _7671; + uint16_t _7672 = (uint16_t)(92); + _curvea0[161] = _7672; + uint16_t _7673 = (uint16_t)(93); + _curvea0[162] = _7673; + uint16_t _7674 = (uint16_t)(93); + _curvea0[163] = _7674; + uint16_t _7675 = (uint16_t)(93); + _curvea0[164] = _7675; + uint16_t _7676 = (uint16_t)(94); + _curvea0[165] = _7676; + uint16_t _7677 = (uint16_t)(94); + _curvea0[166] = _7677; + uint16_t _7678 = (uint16_t)(95); + _curvea0[167] = _7678; + uint16_t _7679 = (uint16_t)(95); + _curvea0[168] = _7679; + uint16_t _7680 = (uint16_t)(95); + _curvea0[169] = _7680; + uint16_t _7681 = (uint16_t)(96); + _curvea0[170] = _7681; + uint16_t _7682 = (uint16_t)(96); + _curvea0[171] = _7682; + uint16_t _7683 = (uint16_t)(97); + _curvea0[172] = _7683; + uint16_t _7684 = (uint16_t)(97); + _curvea0[173] = _7684; + uint16_t _7685 = (uint16_t)(97); + _curvea0[174] = _7685; + uint16_t _7686 = (uint16_t)(98); + _curvea0[175] = _7686; + uint16_t _7687 = (uint16_t)(98); + _curvea0[176] = _7687; + uint16_t _7688 = (uint16_t)(99); + _curvea0[177] = _7688; + uint16_t _7689 = (uint16_t)(99); + _curvea0[178] = _7689; + uint16_t _7690 = (uint16_t)(99); + _curvea0[179] = _7690; + uint16_t _7691 = (uint16_t)(100); + _curvea0[180] = _7691; + uint16_t _7692 = (uint16_t)(100); + _curvea0[181] = _7692; + uint16_t _7693 = (uint16_t)(100); + _curvea0[182] = _7693; + uint16_t _7694 = (uint16_t)(101); + _curvea0[183] = _7694; + uint16_t _7695 = (uint16_t)(101); + _curvea0[184] = _7695; + uint16_t _7696 = (uint16_t)(102); + _curvea0[185] = _7696; + uint16_t _7697 = (uint16_t)(102); + _curvea0[186] = _7697; + uint16_t _7698 = (uint16_t)(102); + _curvea0[187] = _7698; + uint16_t _7699 = (uint16_t)(103); + _curvea0[188] = _7699; + uint16_t _7700 = (uint16_t)(103); + _curvea0[189] = _7700; + uint16_t _7701 = (uint16_t)(103); + _curvea0[190] = _7701; + uint16_t _7702 = (uint16_t)(104); + _curvea0[191] = _7702; + uint16_t _7703 = (uint16_t)(104); + _curvea0[192] = _7703; + uint16_t _7704 = (uint16_t)(105); + _curvea0[193] = _7704; + uint16_t _7705 = (uint16_t)(105); + _curvea0[194] = _7705; + uint16_t _7706 = (uint16_t)(105); + _curvea0[195] = _7706; + uint16_t _7707 = (uint16_t)(106); + _curvea0[196] = _7707; + uint16_t _7708 = (uint16_t)(106); + _curvea0[197] = _7708; + uint16_t _7709 = (uint16_t)(106); + _curvea0[198] = _7709; + uint16_t _7710 = (uint16_t)(107); + _curvea0[199] = _7710; + uint16_t _7711 = (uint16_t)(107); + _curvea0[200] = _7711; + uint16_t _7712 = (uint16_t)(108); + _curvea0[201] = _7712; + uint16_t _7713 = (uint16_t)(108); + _curvea0[202] = _7713; + uint16_t _7714 = (uint16_t)(108); + _curvea0[203] = _7714; + uint16_t _7715 = (uint16_t)(109); + _curvea0[204] = _7715; + uint16_t _7716 = (uint16_t)(109); + _curvea0[205] = _7716; + uint16_t _7717 = (uint16_t)(109); + _curvea0[206] = _7717; + uint16_t _7718 = (uint16_t)(110); + _curvea0[207] = _7718; + uint16_t _7719 = (uint16_t)(110); + _curvea0[208] = _7719; + uint16_t _7720 = (uint16_t)(111); + _curvea0[209] = _7720; + uint16_t _7721 = (uint16_t)(111); + _curvea0[210] = _7721; + uint16_t _7722 = (uint16_t)(111); + _curvea0[211] = _7722; + uint16_t _7723 = (uint16_t)(112); + _curvea0[212] = _7723; + uint16_t _7724 = (uint16_t)(112); + _curvea0[213] = _7724; + uint16_t _7725 = (uint16_t)(112); + _curvea0[214] = _7725; + uint16_t _7726 = (uint16_t)(113); + _curvea0[215] = _7726; + uint16_t _7727 = (uint16_t)(113); + _curvea0[216] = _7727; + uint16_t _7728 = (uint16_t)(113); + _curvea0[217] = _7728; + uint16_t _7729 = (uint16_t)(114); + _curvea0[218] = _7729; + uint16_t _7730 = (uint16_t)(114); + _curvea0[219] = _7730; + uint16_t _7731 = (uint16_t)(115); + _curvea0[220] = _7731; + uint16_t _7732 = (uint16_t)(115); + _curvea0[221] = _7732; + uint16_t _7733 = (uint16_t)(115); + _curvea0[222] = _7733; + uint16_t _7734 = (uint16_t)(116); + _curvea0[223] = _7734; + uint16_t _7735 = (uint16_t)(116); + _curvea0[224] = _7735; + uint16_t _7736 = (uint16_t)(116); + _curvea0[225] = _7736; + uint16_t _7737 = (uint16_t)(117); + _curvea0[226] = _7737; + uint16_t _7738 = (uint16_t)(117); + _curvea0[227] = _7738; + uint16_t _7739 = (uint16_t)(117); + _curvea0[228] = _7739; + uint16_t _7740 = (uint16_t)(118); + _curvea0[229] = _7740; + uint16_t _7741 = (uint16_t)(118); + _curvea0[230] = _7741; + uint16_t _7742 = (uint16_t)(119); + _curvea0[231] = _7742; + uint16_t _7743 = (uint16_t)(119); + _curvea0[232] = _7743; + uint16_t _7744 = (uint16_t)(119); + _curvea0[233] = _7744; + uint16_t _7745 = (uint16_t)(120); + _curvea0[234] = _7745; + uint16_t _7746 = (uint16_t)(120); + _curvea0[235] = _7746; + uint16_t _7747 = (uint16_t)(120); + _curvea0[236] = _7747; + uint16_t _7748 = (uint16_t)(121); + _curvea0[237] = _7748; + uint16_t _7749 = (uint16_t)(121); + _curvea0[238] = _7749; + uint16_t _7750 = (uint16_t)(121); + _curvea0[239] = _7750; + uint16_t _7751 = (uint16_t)(122); + _curvea0[240] = _7751; + uint16_t _7752 = (uint16_t)(122); + _curvea0[241] = _7752; + uint16_t _7753 = (uint16_t)(123); + _curvea0[242] = _7753; + uint16_t _7754 = (uint16_t)(123); + _curvea0[243] = _7754; + uint16_t _7755 = (uint16_t)(123); + _curvea0[244] = _7755; + uint16_t _7756 = (uint16_t)(124); + _curvea0[245] = _7756; + uint16_t _7757 = (uint16_t)(124); + _curvea0[246] = _7757; + uint16_t _7758 = (uint16_t)(124); + _curvea0[247] = _7758; + uint16_t _7759 = (uint16_t)(125); + _curvea0[248] = _7759; + uint16_t _7760 = (uint16_t)(125); + _curvea0[249] = _7760; + uint16_t _7761 = (uint16_t)(125); + _curvea0[250] = _7761; + uint16_t _7762 = (uint16_t)(126); + _curvea0[251] = _7762; + uint16_t _7763 = (uint16_t)(126); + _curvea0[252] = _7763; + uint16_t _7764 = (uint16_t)(126); + _curvea0[253] = _7764; + uint16_t _7765 = (uint16_t)(127); + _curvea0[254] = _7765; + uint16_t _7766 = (uint16_t)(127); + _curvea0[255] = _7766; + uint16_t _7767 = (uint16_t)(128); + _curvea0[256] = _7767; + uint16_t _7768 = (uint16_t)(128); + _curvea0[257] = _7768; + uint16_t _7769 = (uint16_t)(128); + _curvea0[258] = _7769; + uint16_t _7770 = (uint16_t)(129); + _curvea0[259] = _7770; + uint16_t _7771 = (uint16_t)(129); + _curvea0[260] = _7771; + uint16_t _7772 = (uint16_t)(129); + _curvea0[261] = _7772; + uint16_t _7773 = (uint16_t)(130); + _curvea0[262] = _7773; + uint16_t _7774 = (uint16_t)(130); + _curvea0[263] = _7774; + uint16_t _7775 = (uint16_t)(130); + _curvea0[264] = _7775; + uint16_t _7776 = (uint16_t)(131); + _curvea0[265] = _7776; + uint16_t _7777 = (uint16_t)(131); + _curvea0[266] = _7777; + uint16_t _7778 = (uint16_t)(131); + _curvea0[267] = _7778; + uint16_t _7779 = (uint16_t)(132); + _curvea0[268] = _7779; + uint16_t _7780 = (uint16_t)(132); + _curvea0[269] = _7780; + uint16_t _7781 = (uint16_t)(132); + _curvea0[270] = _7781; + uint16_t _7782 = (uint16_t)(133); + _curvea0[271] = _7782; + uint16_t _7783 = (uint16_t)(133); + _curvea0[272] = _7783; + uint16_t _7784 = (uint16_t)(133); + _curvea0[273] = _7784; + uint16_t _7785 = (uint16_t)(134); + _curvea0[274] = _7785; + uint16_t _7786 = (uint16_t)(134); + _curvea0[275] = _7786; + uint16_t _7787 = (uint16_t)(134); + _curvea0[276] = _7787; + uint16_t _7788 = (uint16_t)(135); + _curvea0[277] = _7788; + uint16_t _7789 = (uint16_t)(135); + _curvea0[278] = _7789; + uint16_t _7790 = (uint16_t)(135); + _curvea0[279] = _7790; + uint16_t _7791 = (uint16_t)(136); + _curvea0[280] = _7791; + uint16_t _7792 = (uint16_t)(136); + _curvea0[281] = _7792; + uint16_t _7793 = (uint16_t)(136); + _curvea0[282] = _7793; + uint16_t _7794 = (uint16_t)(137); + _curvea0[283] = _7794; + uint16_t _7795 = (uint16_t)(137); + _curvea0[284] = _7795; + uint16_t _7796 = (uint16_t)(137); + _curvea0[285] = _7796; + uint16_t _7797 = (uint16_t)(138); + _curvea0[286] = _7797; + uint16_t _7798 = (uint16_t)(138); + _curvea0[287] = _7798; + uint16_t _7799 = (uint16_t)(138); + _curvea0[288] = _7799; + uint16_t _7800 = (uint16_t)(139); + _curvea0[289] = _7800; + uint16_t _7801 = (uint16_t)(139); + _curvea0[290] = _7801; + uint16_t _7802 = (uint16_t)(139); + _curvea0[291] = _7802; + uint16_t _7803 = (uint16_t)(140); + _curvea0[292] = _7803; + uint16_t _7804 = (uint16_t)(140); + _curvea0[293] = _7804; + uint16_t _7805 = (uint16_t)(140); + _curvea0[294] = _7805; + uint16_t _7806 = (uint16_t)(141); + _curvea0[295] = _7806; + uint16_t _7807 = (uint16_t)(141); + _curvea0[296] = _7807; + uint16_t _7808 = (uint16_t)(141); + _curvea0[297] = _7808; + uint16_t _7809 = (uint16_t)(141); + _curvea0[298] = _7809; + uint16_t _7810 = (uint16_t)(142); + _curvea0[299] = _7810; + uint16_t _7811 = (uint16_t)(142); + _curvea0[300] = _7811; + uint16_t _7812 = (uint16_t)(142); + _curvea0[301] = _7812; + uint16_t _7813 = (uint16_t)(143); + _curvea0[302] = _7813; + uint16_t _7814 = (uint16_t)(143); + _curvea0[303] = _7814; + uint16_t _7815 = (uint16_t)(143); + _curvea0[304] = _7815; + uint16_t _7816 = (uint16_t)(144); + _curvea0[305] = _7816; + uint16_t _7817 = (uint16_t)(144); + _curvea0[306] = _7817; + uint16_t _7818 = (uint16_t)(144); + _curvea0[307] = _7818; + uint16_t _7819 = (uint16_t)(145); + _curvea0[308] = _7819; + uint16_t _7820 = (uint16_t)(145); + _curvea0[309] = _7820; + uint16_t _7821 = (uint16_t)(145); + _curvea0[310] = _7821; + uint16_t _7822 = (uint16_t)(145); + _curvea0[311] = _7822; + uint16_t _7823 = (uint16_t)(146); + _curvea0[312] = _7823; + uint16_t _7824 = (uint16_t)(146); + _curvea0[313] = _7824; + uint16_t _7825 = (uint16_t)(146); + _curvea0[314] = _7825; + uint16_t _7826 = (uint16_t)(147); + _curvea0[315] = _7826; + uint16_t _7827 = (uint16_t)(147); + _curvea0[316] = _7827; + uint16_t _7828 = (uint16_t)(147); + _curvea0[317] = _7828; + uint16_t _7829 = (uint16_t)(148); + _curvea0[318] = _7829; + uint16_t _7830 = (uint16_t)(148); + _curvea0[319] = _7830; + uint16_t _7831 = (uint16_t)(148); + _curvea0[320] = _7831; + uint16_t _7832 = (uint16_t)(148); + _curvea0[321] = _7832; + uint16_t _7833 = (uint16_t)(149); + _curvea0[322] = _7833; + uint16_t _7834 = (uint16_t)(149); + _curvea0[323] = _7834; + uint16_t _7835 = (uint16_t)(149); + _curvea0[324] = _7835; + uint16_t _7836 = (uint16_t)(150); + _curvea0[325] = _7836; + uint16_t _7837 = (uint16_t)(150); + _curvea0[326] = _7837; + uint16_t _7838 = (uint16_t)(150); + _curvea0[327] = _7838; + uint16_t _7839 = (uint16_t)(150); + _curvea0[328] = _7839; + uint16_t _7840 = (uint16_t)(151); + _curvea0[329] = _7840; + uint16_t _7841 = (uint16_t)(151); + _curvea0[330] = _7841; + uint16_t _7842 = (uint16_t)(151); + _curvea0[331] = _7842; + uint16_t _7843 = (uint16_t)(152); + _curvea0[332] = _7843; + uint16_t _7844 = (uint16_t)(152); + _curvea0[333] = _7844; + uint16_t _7845 = (uint16_t)(152); + _curvea0[334] = _7845; + uint16_t _7846 = (uint16_t)(152); + _curvea0[335] = _7846; + uint16_t _7847 = (uint16_t)(153); + _curvea0[336] = _7847; + uint16_t _7848 = (uint16_t)(153); + _curvea0[337] = _7848; + uint16_t _7849 = (uint16_t)(153); + _curvea0[338] = _7849; + uint16_t _7850 = (uint16_t)(154); + _curvea0[339] = _7850; + uint16_t _7851 = (uint16_t)(154); + _curvea0[340] = _7851; + uint16_t _7852 = (uint16_t)(154); + _curvea0[341] = _7852; + uint16_t _7853 = (uint16_t)(154); + _curvea0[342] = _7853; + uint16_t _7854 = (uint16_t)(155); + _curvea0[343] = _7854; + uint16_t _7855 = (uint16_t)(155); + _curvea0[344] = _7855; + uint16_t _7856 = (uint16_t)(155); + _curvea0[345] = _7856; + uint16_t _7857 = (uint16_t)(156); + _curvea0[346] = _7857; + uint16_t _7858 = (uint16_t)(156); + _curvea0[347] = _7858; + uint16_t _7859 = (uint16_t)(156); + _curvea0[348] = _7859; + uint16_t _7860 = (uint16_t)(156); + _curvea0[349] = _7860; + uint16_t _7861 = (uint16_t)(157); + _curvea0[350] = _7861; + uint16_t _7862 = (uint16_t)(157); + _curvea0[351] = _7862; + uint16_t _7863 = (uint16_t)(157); + _curvea0[352] = _7863; + uint16_t _7864 = (uint16_t)(157); + _curvea0[353] = _7864; + uint16_t _7865 = (uint16_t)(158); + _curvea0[354] = _7865; + uint16_t _7866 = (uint16_t)(158); + _curvea0[355] = _7866; + uint16_t _7867 = (uint16_t)(158); + _curvea0[356] = _7867; + uint16_t _7868 = (uint16_t)(159); + _curvea0[357] = _7868; + uint16_t _7869 = (uint16_t)(159); + _curvea0[358] = _7869; + uint16_t _7870 = (uint16_t)(159); + _curvea0[359] = _7870; + uint16_t _7871 = (uint16_t)(159); + _curvea0[360] = _7871; + uint16_t _7872 = (uint16_t)(160); + _curvea0[361] = _7872; + uint16_t _7873 = (uint16_t)(160); + _curvea0[362] = _7873; + uint16_t _7874 = (uint16_t)(160); + _curvea0[363] = _7874; + uint16_t _7875 = (uint16_t)(160); + _curvea0[364] = _7875; + uint16_t _7876 = (uint16_t)(161); + _curvea0[365] = _7876; + uint16_t _7877 = (uint16_t)(161); + _curvea0[366] = _7877; + uint16_t _7878 = (uint16_t)(161); + _curvea0[367] = _7878; + uint16_t _7879 = (uint16_t)(161); + _curvea0[368] = _7879; + uint16_t _7880 = (uint16_t)(162); + _curvea0[369] = _7880; + uint16_t _7881 = (uint16_t)(162); + _curvea0[370] = _7881; + uint16_t _7882 = (uint16_t)(162); + _curvea0[371] = _7882; + uint16_t _7883 = (uint16_t)(162); + _curvea0[372] = _7883; + uint16_t _7884 = (uint16_t)(163); + _curvea0[373] = _7884; + uint16_t _7885 = (uint16_t)(163); + _curvea0[374] = _7885; + uint16_t _7886 = (uint16_t)(163); + _curvea0[375] = _7886; + uint16_t _7887 = (uint16_t)(163); + _curvea0[376] = _7887; + uint16_t _7888 = (uint16_t)(164); + _curvea0[377] = _7888; + uint16_t _7889 = (uint16_t)(164); + _curvea0[378] = _7889; + uint16_t _7890 = (uint16_t)(164); + _curvea0[379] = _7890; + uint16_t _7891 = (uint16_t)(164); + _curvea0[380] = _7891; + uint16_t _7892 = (uint16_t)(165); + _curvea0[381] = _7892; + uint16_t _7893 = (uint16_t)(165); + _curvea0[382] = _7893; + uint16_t _7894 = (uint16_t)(165); + _curvea0[383] = _7894; + uint16_t _7895 = (uint16_t)(166); + _curvea0[384] = _7895; + uint16_t _7896 = (uint16_t)(166); + _curvea0[385] = _7896; + uint16_t _7897 = (uint16_t)(166); + _curvea0[386] = _7897; + uint16_t _7898 = (uint16_t)(166); + _curvea0[387] = _7898; + uint16_t _7899 = (uint16_t)(167); + _curvea0[388] = _7899; + uint16_t _7900 = (uint16_t)(167); + _curvea0[389] = _7900; + uint16_t _7901 = (uint16_t)(167); + _curvea0[390] = _7901; + uint16_t _7902 = (uint16_t)(167); + _curvea0[391] = _7902; + uint16_t _7903 = (uint16_t)(167); + _curvea0[392] = _7903; + uint16_t _7904 = (uint16_t)(168); + _curvea0[393] = _7904; + uint16_t _7905 = (uint16_t)(168); + _curvea0[394] = _7905; + uint16_t _7906 = (uint16_t)(168); + _curvea0[395] = _7906; + uint16_t _7907 = (uint16_t)(168); + _curvea0[396] = _7907; + uint16_t _7908 = (uint16_t)(169); + _curvea0[397] = _7908; + uint16_t _7909 = (uint16_t)(169); + _curvea0[398] = _7909; + uint16_t _7910 = (uint16_t)(169); + _curvea0[399] = _7910; + uint16_t _7911 = (uint16_t)(169); + _curvea0[400] = _7911; + uint16_t _7912 = (uint16_t)(170); + _curvea0[401] = _7912; + uint16_t _7913 = (uint16_t)(170); + _curvea0[402] = _7913; + uint16_t _7914 = (uint16_t)(170); + _curvea0[403] = _7914; + uint16_t _7915 = (uint16_t)(170); + _curvea0[404] = _7915; + uint16_t _7916 = (uint16_t)(171); + _curvea0[405] = _7916; + uint16_t _7917 = (uint16_t)(171); + _curvea0[406] = _7917; + uint16_t _7918 = (uint16_t)(171); + _curvea0[407] = _7918; + uint16_t _7919 = (uint16_t)(171); + _curvea0[408] = _7919; + uint16_t _7920 = (uint16_t)(172); + _curvea0[409] = _7920; + uint16_t _7921 = (uint16_t)(172); + _curvea0[410] = _7921; + uint16_t _7922 = (uint16_t)(172); + _curvea0[411] = _7922; + uint16_t _7923 = (uint16_t)(172); + _curvea0[412] = _7923; + uint16_t _7924 = (uint16_t)(173); + _curvea0[413] = _7924; + uint16_t _7925 = (uint16_t)(173); + _curvea0[414] = _7925; + uint16_t _7926 = (uint16_t)(173); + _curvea0[415] = _7926; + uint16_t _7927 = (uint16_t)(173); + _curvea0[416] = _7927; + uint16_t _7928 = (uint16_t)(173); + _curvea0[417] = _7928; + uint16_t _7929 = (uint16_t)(174); + _curvea0[418] = _7929; + uint16_t _7930 = (uint16_t)(174); + _curvea0[419] = _7930; + uint16_t _7931 = (uint16_t)(174); + _curvea0[420] = _7931; + uint16_t _7932 = (uint16_t)(174); + _curvea0[421] = _7932; + uint16_t _7933 = (uint16_t)(175); + _curvea0[422] = _7933; + uint16_t _7934 = (uint16_t)(175); + _curvea0[423] = _7934; + uint16_t _7935 = (uint16_t)(175); + _curvea0[424] = _7935; + uint16_t _7936 = (uint16_t)(175); + _curvea0[425] = _7936; + uint16_t _7937 = (uint16_t)(176); + _curvea0[426] = _7937; + uint16_t _7938 = (uint16_t)(176); + _curvea0[427] = _7938; + uint16_t _7939 = (uint16_t)(176); + _curvea0[428] = _7939; + uint16_t _7940 = (uint16_t)(176); + _curvea0[429] = _7940; + uint16_t _7941 = (uint16_t)(176); + _curvea0[430] = _7941; + uint16_t _7942 = (uint16_t)(177); + _curvea0[431] = _7942; + uint16_t _7943 = (uint16_t)(177); + _curvea0[432] = _7943; + uint16_t _7944 = (uint16_t)(177); + _curvea0[433] = _7944; + uint16_t _7945 = (uint16_t)(177); + _curvea0[434] = _7945; + uint16_t _7946 = (uint16_t)(178); + _curvea0[435] = _7946; + uint16_t _7947 = (uint16_t)(178); + _curvea0[436] = _7947; + uint16_t _7948 = (uint16_t)(178); + _curvea0[437] = _7948; + uint16_t _7949 = (uint16_t)(178); + _curvea0[438] = _7949; + uint16_t _7950 = (uint16_t)(178); + _curvea0[439] = _7950; + uint16_t _7951 = (uint16_t)(179); + _curvea0[440] = _7951; + uint16_t _7952 = (uint16_t)(179); + _curvea0[441] = _7952; + uint16_t _7953 = (uint16_t)(179); + _curvea0[442] = _7953; + uint16_t _7954 = (uint16_t)(179); + _curvea0[443] = _7954; + uint16_t _7955 = (uint16_t)(180); + _curvea0[444] = _7955; + uint16_t _7956 = (uint16_t)(180); + _curvea0[445] = _7956; + uint16_t _7957 = (uint16_t)(180); + _curvea0[446] = _7957; + uint16_t _7958 = (uint16_t)(180); + _curvea0[447] = _7958; + uint16_t _7959 = (uint16_t)(180); + _curvea0[448] = _7959; + uint16_t _7960 = (uint16_t)(181); + _curvea0[449] = _7960; + uint16_t _7961 = (uint16_t)(181); + _curvea0[450] = _7961; + uint16_t _7962 = (uint16_t)(181); + _curvea0[451] = _7962; + uint16_t _7963 = (uint16_t)(181); + _curvea0[452] = _7963; + uint16_t _7964 = (uint16_t)(181); + _curvea0[453] = _7964; + uint16_t _7965 = (uint16_t)(182); + _curvea0[454] = _7965; + uint16_t _7966 = (uint16_t)(182); + _curvea0[455] = _7966; + uint16_t _7967 = (uint16_t)(182); + _curvea0[456] = _7967; + uint16_t _7968 = (uint16_t)(182); + _curvea0[457] = _7968; + uint16_t _7969 = (uint16_t)(183); + _curvea0[458] = _7969; + uint16_t _7970 = (uint16_t)(183); + _curvea0[459] = _7970; + uint16_t _7971 = (uint16_t)(183); + _curvea0[460] = _7971; + uint16_t _7972 = (uint16_t)(183); + _curvea0[461] = _7972; + uint16_t _7973 = (uint16_t)(183); + _curvea0[462] = _7973; + uint16_t _7974 = (uint16_t)(184); + _curvea0[463] = _7974; + uint16_t _7975 = (uint16_t)(184); + _curvea0[464] = _7975; + uint16_t _7976 = (uint16_t)(184); + _curvea0[465] = _7976; + uint16_t _7977 = (uint16_t)(184); + _curvea0[466] = _7977; + uint16_t _7978 = (uint16_t)(184); + _curvea0[467] = _7978; + uint16_t _7979 = (uint16_t)(185); + _curvea0[468] = _7979; + uint16_t _7980 = (uint16_t)(185); + _curvea0[469] = _7980; + uint16_t _7981 = (uint16_t)(185); + _curvea0[470] = _7981; + uint16_t _7982 = (uint16_t)(185); + _curvea0[471] = _7982; + uint16_t _7983 = (uint16_t)(185); + _curvea0[472] = _7983; + uint16_t _7984 = (uint16_t)(186); + _curvea0[473] = _7984; + uint16_t _7985 = (uint16_t)(186); + _curvea0[474] = _7985; + uint16_t _7986 = (uint16_t)(186); + _curvea0[475] = _7986; + uint16_t _7987 = (uint16_t)(186); + _curvea0[476] = _7987; + uint16_t _7988 = (uint16_t)(187); + _curvea0[477] = _7988; + uint16_t _7989 = (uint16_t)(187); + _curvea0[478] = _7989; + uint16_t _7990 = (uint16_t)(187); + _curvea0[479] = _7990; + uint16_t _7991 = (uint16_t)(187); + _curvea0[480] = _7991; + uint16_t _7992 = (uint16_t)(187); + _curvea0[481] = _7992; + uint16_t _7993 = (uint16_t)(188); + _curvea0[482] = _7993; + uint16_t _7994 = (uint16_t)(188); + _curvea0[483] = _7994; + uint16_t _7995 = (uint16_t)(188); + _curvea0[484] = _7995; + uint16_t _7996 = (uint16_t)(188); + _curvea0[485] = _7996; + uint16_t _7997 = (uint16_t)(188); + _curvea0[486] = _7997; + uint16_t _7998 = (uint16_t)(189); + _curvea0[487] = _7998; + uint16_t _7999 = (uint16_t)(189); + _curvea0[488] = _7999; + uint16_t _8000 = (uint16_t)(189); + _curvea0[489] = _8000; + uint16_t _8001 = (uint16_t)(189); + _curvea0[490] = _8001; + uint16_t _8002 = (uint16_t)(189); + _curvea0[491] = _8002; + uint16_t _8003 = (uint16_t)(190); + _curvea0[492] = _8003; + uint16_t _8004 = (uint16_t)(190); + _curvea0[493] = _8004; + uint16_t _8005 = (uint16_t)(190); + _curvea0[494] = _8005; + uint16_t _8006 = (uint16_t)(190); + _curvea0[495] = _8006; + uint16_t _8007 = (uint16_t)(190); + _curvea0[496] = _8007; + uint16_t _8008 = (uint16_t)(190); + _curvea0[497] = _8008; + uint16_t _8009 = (uint16_t)(191); + _curvea0[498] = _8009; + uint16_t _8010 = (uint16_t)(191); + _curvea0[499] = _8010; + uint16_t _8011 = (uint16_t)(191); + _curvea0[500] = _8011; + uint16_t _8012 = (uint16_t)(191); + _curvea0[501] = _8012; + uint16_t _8013 = (uint16_t)(191); + _curvea0[502] = _8013; + uint16_t _8014 = (uint16_t)(192); + _curvea0[503] = _8014; + uint16_t _8015 = (uint16_t)(192); + _curvea0[504] = _8015; + uint16_t _8016 = (uint16_t)(192); + _curvea0[505] = _8016; + uint16_t _8017 = (uint16_t)(192); + _curvea0[506] = _8017; + uint16_t _8018 = (uint16_t)(192); + _curvea0[507] = _8018; + uint16_t _8019 = (uint16_t)(193); + _curvea0[508] = _8019; + uint16_t _8020 = (uint16_t)(193); + _curvea0[509] = _8020; + uint16_t _8021 = (uint16_t)(193); + _curvea0[510] = _8021; + uint16_t _8022 = (uint16_t)(193); + _curvea0[511] = _8022; + uint16_t _8023 = (uint16_t)(193); + _curvea0[512] = _8023; + uint16_t _8024 = (uint16_t)(194); + _curvea0[513] = _8024; + uint16_t _8025 = (uint16_t)(194); + _curvea0[514] = _8025; + uint16_t _8026 = (uint16_t)(194); + _curvea0[515] = _8026; + uint16_t _8027 = (uint16_t)(194); + _curvea0[516] = _8027; + uint16_t _8028 = (uint16_t)(194); + _curvea0[517] = _8028; + uint16_t _8029 = (uint16_t)(195); + _curvea0[518] = _8029; + uint16_t _8030 = (uint16_t)(195); + _curvea0[519] = _8030; + uint16_t _8031 = (uint16_t)(195); + _curvea0[520] = _8031; + uint16_t _8032 = (uint16_t)(195); + _curvea0[521] = _8032; + uint16_t _8033 = (uint16_t)(195); + _curvea0[522] = _8033; + uint16_t _8034 = (uint16_t)(195); + _curvea0[523] = _8034; + uint16_t _8035 = (uint16_t)(196); + _curvea0[524] = _8035; + uint16_t _8036 = (uint16_t)(196); + _curvea0[525] = _8036; + uint16_t _8037 = (uint16_t)(196); + _curvea0[526] = _8037; + uint16_t _8038 = (uint16_t)(196); + _curvea0[527] = _8038; + uint16_t _8039 = (uint16_t)(196); + _curvea0[528] = _8039; + uint16_t _8040 = (uint16_t)(197); + _curvea0[529] = _8040; + uint16_t _8041 = (uint16_t)(197); + _curvea0[530] = _8041; + uint16_t _8042 = (uint16_t)(197); + _curvea0[531] = _8042; + uint16_t _8043 = (uint16_t)(197); + _curvea0[532] = _8043; + uint16_t _8044 = (uint16_t)(197); + _curvea0[533] = _8044; + uint16_t _8045 = (uint16_t)(197); + _curvea0[534] = _8045; + uint16_t _8046 = (uint16_t)(198); + _curvea0[535] = _8046; + uint16_t _8047 = (uint16_t)(198); + _curvea0[536] = _8047; + uint16_t _8048 = (uint16_t)(198); + _curvea0[537] = _8048; + uint16_t _8049 = (uint16_t)(198); + _curvea0[538] = _8049; + uint16_t _8050 = (uint16_t)(198); + _curvea0[539] = _8050; + uint16_t _8051 = (uint16_t)(199); + _curvea0[540] = _8051; + uint16_t _8052 = (uint16_t)(199); + _curvea0[541] = _8052; + uint16_t _8053 = (uint16_t)(199); + _curvea0[542] = _8053; + uint16_t _8054 = (uint16_t)(199); + _curvea0[543] = _8054; + uint16_t _8055 = (uint16_t)(199); + _curvea0[544] = _8055; + uint16_t _8056 = (uint16_t)(199); + _curvea0[545] = _8056; + uint16_t _8057 = (uint16_t)(200); + _curvea0[546] = _8057; + uint16_t _8058 = (uint16_t)(200); + _curvea0[547] = _8058; + uint16_t _8059 = (uint16_t)(200); + _curvea0[548] = _8059; + uint16_t _8060 = (uint16_t)(200); + _curvea0[549] = _8060; + uint16_t _8061 = (uint16_t)(200); + _curvea0[550] = _8061; + uint16_t _8062 = (uint16_t)(200); + _curvea0[551] = _8062; + uint16_t _8063 = (uint16_t)(201); + _curvea0[552] = _8063; + uint16_t _8064 = (uint16_t)(201); + _curvea0[553] = _8064; + uint16_t _8065 = (uint16_t)(201); + _curvea0[554] = _8065; + uint16_t _8066 = (uint16_t)(201); + _curvea0[555] = _8066; + uint16_t _8067 = (uint16_t)(201); + _curvea0[556] = _8067; + uint16_t _8068 = (uint16_t)(202); + _curvea0[557] = _8068; + uint16_t _8069 = (uint16_t)(202); + _curvea0[558] = _8069; + uint16_t _8070 = (uint16_t)(202); + _curvea0[559] = _8070; + uint16_t _8071 = (uint16_t)(202); + _curvea0[560] = _8071; + uint16_t _8072 = (uint16_t)(202); + _curvea0[561] = _8072; + uint16_t _8073 = (uint16_t)(202); + _curvea0[562] = _8073; + uint16_t _8074 = (uint16_t)(203); + _curvea0[563] = _8074; + uint16_t _8075 = (uint16_t)(203); + _curvea0[564] = _8075; + uint16_t _8076 = (uint16_t)(203); + _curvea0[565] = _8076; + uint16_t _8077 = (uint16_t)(203); + _curvea0[566] = _8077; + uint16_t _8078 = (uint16_t)(203); + _curvea0[567] = _8078; + uint16_t _8079 = (uint16_t)(203); + _curvea0[568] = _8079; + uint16_t _8080 = (uint16_t)(204); + _curvea0[569] = _8080; + uint16_t _8081 = (uint16_t)(204); + _curvea0[570] = _8081; + uint16_t _8082 = (uint16_t)(204); + _curvea0[571] = _8082; + uint16_t _8083 = (uint16_t)(204); + _curvea0[572] = _8083; + uint16_t _8084 = (uint16_t)(204); + _curvea0[573] = _8084; + uint16_t _8085 = (uint16_t)(204); + _curvea0[574] = _8085; + uint16_t _8086 = (uint16_t)(205); + _curvea0[575] = _8086; + uint16_t _8087 = (uint16_t)(205); + _curvea0[576] = _8087; + uint16_t _8088 = (uint16_t)(205); + _curvea0[577] = _8088; + uint16_t _8089 = (uint16_t)(205); + _curvea0[578] = _8089; + uint16_t _8090 = (uint16_t)(205); + _curvea0[579] = _8090; + uint16_t _8091 = (uint16_t)(205); + _curvea0[580] = _8091; + uint16_t _8092 = (uint16_t)(206); + _curvea0[581] = _8092; + uint16_t _8093 = (uint16_t)(206); + _curvea0[582] = _8093; + uint16_t _8094 = (uint16_t)(206); + _curvea0[583] = _8094; + uint16_t _8095 = (uint16_t)(206); + _curvea0[584] = _8095; + uint16_t _8096 = (uint16_t)(206); + _curvea0[585] = _8096; + uint16_t _8097 = (uint16_t)(206); + _curvea0[586] = _8097; + uint16_t _8098 = (uint16_t)(207); + _curvea0[587] = _8098; + uint16_t _8099 = (uint16_t)(207); + _curvea0[588] = _8099; + uint16_t _8100 = (uint16_t)(207); + _curvea0[589] = _8100; + uint16_t _8101 = (uint16_t)(207); + _curvea0[590] = _8101; + uint16_t _8102 = (uint16_t)(207); + _curvea0[591] = _8102; + uint16_t _8103 = (uint16_t)(207); + _curvea0[592] = _8103; + uint16_t _8104 = (uint16_t)(208); + _curvea0[593] = _8104; + uint16_t _8105 = (uint16_t)(208); + _curvea0[594] = _8105; + uint16_t _8106 = (uint16_t)(208); + _curvea0[595] = _8106; + uint16_t _8107 = (uint16_t)(208); + _curvea0[596] = _8107; + uint16_t _8108 = (uint16_t)(208); + _curvea0[597] = _8108; + uint16_t _8109 = (uint16_t)(208); + _curvea0[598] = _8109; + uint16_t _8110 = (uint16_t)(209); + _curvea0[599] = _8110; + uint16_t _8111 = (uint16_t)(209); + _curvea0[600] = _8111; + uint16_t _8112 = (uint16_t)(209); + _curvea0[601] = _8112; + uint16_t _8113 = (uint16_t)(209); + _curvea0[602] = _8113; + uint16_t _8114 = (uint16_t)(209); + _curvea0[603] = _8114; + uint16_t _8115 = (uint16_t)(209); + _curvea0[604] = _8115; + uint16_t _8116 = (uint16_t)(209); + _curvea0[605] = _8116; + uint16_t _8117 = (uint16_t)(210); + _curvea0[606] = _8117; + uint16_t _8118 = (uint16_t)(210); + _curvea0[607] = _8118; + uint16_t _8119 = (uint16_t)(210); + _curvea0[608] = _8119; + uint16_t _8120 = (uint16_t)(210); + _curvea0[609] = _8120; + uint16_t _8121 = (uint16_t)(210); + _curvea0[610] = _8121; + uint16_t _8122 = (uint16_t)(210); + _curvea0[611] = _8122; + uint16_t _8123 = (uint16_t)(211); + _curvea0[612] = _8123; + uint16_t _8124 = (uint16_t)(211); + _curvea0[613] = _8124; + uint16_t _8125 = (uint16_t)(211); + _curvea0[614] = _8125; + uint16_t _8126 = (uint16_t)(211); + _curvea0[615] = _8126; + uint16_t _8127 = (uint16_t)(211); + _curvea0[616] = _8127; + uint16_t _8128 = (uint16_t)(211); + _curvea0[617] = _8128; + uint16_t _8129 = (uint16_t)(211); + _curvea0[618] = _8129; + uint16_t _8130 = (uint16_t)(212); + _curvea0[619] = _8130; + uint16_t _8131 = (uint16_t)(212); + _curvea0[620] = _8131; + uint16_t _8132 = (uint16_t)(212); + _curvea0[621] = _8132; + uint16_t _8133 = (uint16_t)(212); + _curvea0[622] = _8133; + uint16_t _8134 = (uint16_t)(212); + _curvea0[623] = _8134; + uint16_t _8135 = (uint16_t)(212); + _curvea0[624] = _8135; + uint16_t _8136 = (uint16_t)(213); + _curvea0[625] = _8136; + uint16_t _8137 = (uint16_t)(213); + _curvea0[626] = _8137; + uint16_t _8138 = (uint16_t)(213); + _curvea0[627] = _8138; + uint16_t _8139 = (uint16_t)(213); + _curvea0[628] = _8139; + uint16_t _8140 = (uint16_t)(213); + _curvea0[629] = _8140; + uint16_t _8141 = (uint16_t)(213); + _curvea0[630] = _8141; + uint16_t _8142 = (uint16_t)(213); + _curvea0[631] = _8142; + uint16_t _8143 = (uint16_t)(214); + _curvea0[632] = _8143; + uint16_t _8144 = (uint16_t)(214); + _curvea0[633] = _8144; + uint16_t _8145 = (uint16_t)(214); + _curvea0[634] = _8145; + uint16_t _8146 = (uint16_t)(214); + _curvea0[635] = _8146; + uint16_t _8147 = (uint16_t)(214); + _curvea0[636] = _8147; + uint16_t _8148 = (uint16_t)(214); + _curvea0[637] = _8148; + uint16_t _8149 = (uint16_t)(214); + _curvea0[638] = _8149; + uint16_t _8150 = (uint16_t)(215); + _curvea0[639] = _8150; + uint16_t _8151 = (uint16_t)(215); + _curvea0[640] = _8151; + uint16_t _8152 = (uint16_t)(215); + _curvea0[641] = _8152; + uint16_t _8153 = (uint16_t)(215); + _curvea0[642] = _8153; + uint16_t _8154 = (uint16_t)(215); + _curvea0[643] = _8154; + uint16_t _8155 = (uint16_t)(215); + _curvea0[644] = _8155; + uint16_t _8156 = (uint16_t)(216); + _curvea0[645] = _8156; + uint16_t _8157 = (uint16_t)(216); + _curvea0[646] = _8157; + uint16_t _8158 = (uint16_t)(216); + _curvea0[647] = _8158; + uint16_t _8159 = (uint16_t)(216); + _curvea0[648] = _8159; + uint16_t _8160 = (uint16_t)(216); + _curvea0[649] = _8160; + uint16_t _8161 = (uint16_t)(216); + _curvea0[650] = _8161; + uint16_t _8162 = (uint16_t)(216); + _curvea0[651] = _8162; + uint16_t _8163 = (uint16_t)(217); + _curvea0[652] = _8163; + uint16_t _8164 = (uint16_t)(217); + _curvea0[653] = _8164; + uint16_t _8165 = (uint16_t)(217); + _curvea0[654] = _8165; + uint16_t _8166 = (uint16_t)(217); + _curvea0[655] = _8166; + uint16_t _8167 = (uint16_t)(217); + _curvea0[656] = _8167; + uint16_t _8168 = (uint16_t)(217); + _curvea0[657] = _8168; + uint16_t _8169 = (uint16_t)(217); + _curvea0[658] = _8169; + uint16_t _8170 = (uint16_t)(218); + _curvea0[659] = _8170; + uint16_t _8171 = (uint16_t)(218); + _curvea0[660] = _8171; + uint16_t _8172 = (uint16_t)(218); + _curvea0[661] = _8172; + uint16_t _8173 = (uint16_t)(218); + _curvea0[662] = _8173; + uint16_t _8174 = (uint16_t)(218); + _curvea0[663] = _8174; + uint16_t _8175 = (uint16_t)(218); + _curvea0[664] = _8175; + uint16_t _8176 = (uint16_t)(218); + _curvea0[665] = _8176; + uint16_t _8177 = (uint16_t)(219); + _curvea0[666] = _8177; + uint16_t _8178 = (uint16_t)(219); + _curvea0[667] = _8178; + uint16_t _8179 = (uint16_t)(219); + _curvea0[668] = _8179; + uint16_t _8180 = (uint16_t)(219); + _curvea0[669] = _8180; + uint16_t _8181 = (uint16_t)(219); + _curvea0[670] = _8181; + uint16_t _8182 = (uint16_t)(219); + _curvea0[671] = _8182; + uint16_t _8183 = (uint16_t)(219); + _curvea0[672] = _8183; + uint16_t _8184 = (uint16_t)(220); + _curvea0[673] = _8184; + uint16_t _8185 = (uint16_t)(220); + _curvea0[674] = _8185; + uint16_t _8186 = (uint16_t)(220); + _curvea0[675] = _8186; + uint16_t _8187 = (uint16_t)(220); + _curvea0[676] = _8187; + uint16_t _8188 = (uint16_t)(220); + _curvea0[677] = _8188; + uint16_t _8189 = (uint16_t)(220); + _curvea0[678] = _8189; + uint16_t _8190 = (uint16_t)(220); + _curvea0[679] = _8190; + uint16_t _8191 = (uint16_t)(220); + _curvea0[680] = _8191; + uint16_t _8192 = (uint16_t)(221); + _curvea0[681] = _8192; + uint16_t _8193 = (uint16_t)(221); + _curvea0[682] = _8193; + uint16_t _8194 = (uint16_t)(221); + _curvea0[683] = _8194; + uint16_t _8195 = (uint16_t)(221); + _curvea0[684] = _8195; + uint16_t _8196 = (uint16_t)(221); + _curvea0[685] = _8196; + uint16_t _8197 = (uint16_t)(221); + _curvea0[686] = _8197; + uint16_t _8198 = (uint16_t)(221); + _curvea0[687] = _8198; + uint16_t _8199 = (uint16_t)(222); + _curvea0[688] = _8199; + uint16_t _8200 = (uint16_t)(222); + _curvea0[689] = _8200; + uint16_t _8201 = (uint16_t)(222); + _curvea0[690] = _8201; + uint16_t _8202 = (uint16_t)(222); + _curvea0[691] = _8202; + uint16_t _8203 = (uint16_t)(222); + _curvea0[692] = _8203; + uint16_t _8204 = (uint16_t)(222); + _curvea0[693] = _8204; + uint16_t _8205 = (uint16_t)(222); + _curvea0[694] = _8205; + uint16_t _8206 = (uint16_t)(223); + _curvea0[695] = _8206; + uint16_t _8207 = (uint16_t)(223); + _curvea0[696] = _8207; + uint16_t _8208 = (uint16_t)(223); + _curvea0[697] = _8208; + uint16_t _8209 = (uint16_t)(223); + _curvea0[698] = _8209; + uint16_t _8210 = (uint16_t)(223); + _curvea0[699] = _8210; + uint16_t _8211 = (uint16_t)(223); + _curvea0[700] = _8211; + uint16_t _8212 = (uint16_t)(223); + _curvea0[701] = _8212; + uint16_t _8213 = (uint16_t)(223); + _curvea0[702] = _8213; + uint16_t _8214 = (uint16_t)(224); + _curvea0[703] = _8214; + uint16_t _8215 = (uint16_t)(224); + _curvea0[704] = _8215; + uint16_t _8216 = (uint16_t)(224); + _curvea0[705] = _8216; + uint16_t _8217 = (uint16_t)(224); + _curvea0[706] = _8217; + uint16_t _8218 = (uint16_t)(224); + _curvea0[707] = _8218; + uint16_t _8219 = (uint16_t)(224); + _curvea0[708] = _8219; + uint16_t _8220 = (uint16_t)(224); + _curvea0[709] = _8220; + uint16_t _8221 = (uint16_t)(224); + _curvea0[710] = _8221; + uint16_t _8222 = (uint16_t)(225); + _curvea0[711] = _8222; + uint16_t _8223 = (uint16_t)(225); + _curvea0[712] = _8223; + uint16_t _8224 = (uint16_t)(225); + _curvea0[713] = _8224; + uint16_t _8225 = (uint16_t)(225); + _curvea0[714] = _8225; + uint16_t _8226 = (uint16_t)(225); + _curvea0[715] = _8226; + uint16_t _8227 = (uint16_t)(225); + _curvea0[716] = _8227; + uint16_t _8228 = (uint16_t)(225); + _curvea0[717] = _8228; + uint16_t _8229 = (uint16_t)(226); + _curvea0[718] = _8229; + uint16_t _8230 = (uint16_t)(226); + _curvea0[719] = _8230; + uint16_t _8231 = (uint16_t)(226); + _curvea0[720] = _8231; + uint16_t _8232 = (uint16_t)(226); + _curvea0[721] = _8232; + uint16_t _8233 = (uint16_t)(226); + _curvea0[722] = _8233; + uint16_t _8234 = (uint16_t)(226); + _curvea0[723] = _8234; + uint16_t _8235 = (uint16_t)(226); + _curvea0[724] = _8235; + uint16_t _8236 = (uint16_t)(226); + _curvea0[725] = _8236; + uint16_t _8237 = (uint16_t)(227); + _curvea0[726] = _8237; + uint16_t _8238 = (uint16_t)(227); + _curvea0[727] = _8238; + uint16_t _8239 = (uint16_t)(227); + _curvea0[728] = _8239; + uint16_t _8240 = (uint16_t)(227); + _curvea0[729] = _8240; + uint16_t _8241 = (uint16_t)(227); + _curvea0[730] = _8241; + uint16_t _8242 = (uint16_t)(227); + _curvea0[731] = _8242; + uint16_t _8243 = (uint16_t)(227); + _curvea0[732] = _8243; + uint16_t _8244 = (uint16_t)(227); + _curvea0[733] = _8244; + uint16_t _8245 = (uint16_t)(228); + _curvea0[734] = _8245; + uint16_t _8246 = (uint16_t)(228); + _curvea0[735] = _8246; + uint16_t _8247 = (uint16_t)(228); + _curvea0[736] = _8247; + uint16_t _8248 = (uint16_t)(228); + _curvea0[737] = _8248; + uint16_t _8249 = (uint16_t)(228); + _curvea0[738] = _8249; + uint16_t _8250 = (uint16_t)(228); + _curvea0[739] = _8250; + uint16_t _8251 = (uint16_t)(228); + _curvea0[740] = _8251; + uint16_t _8252 = (uint16_t)(228); + _curvea0[741] = _8252; + uint16_t _8253 = (uint16_t)(228); + _curvea0[742] = _8253; + uint16_t _8254 = (uint16_t)(229); + _curvea0[743] = _8254; + uint16_t _8255 = (uint16_t)(229); + _curvea0[744] = _8255; + uint16_t _8256 = (uint16_t)(229); + _curvea0[745] = _8256; + uint16_t _8257 = (uint16_t)(229); + _curvea0[746] = _8257; + uint16_t _8258 = (uint16_t)(229); + _curvea0[747] = _8258; + uint16_t _8259 = (uint16_t)(229); + _curvea0[748] = _8259; + uint16_t _8260 = (uint16_t)(229); + _curvea0[749] = _8260; + uint16_t _8261 = (uint16_t)(229); + _curvea0[750] = _8261; + uint16_t _8262 = (uint16_t)(230); + _curvea0[751] = _8262; + uint16_t _8263 = (uint16_t)(230); + _curvea0[752] = _8263; + uint16_t _8264 = (uint16_t)(230); + _curvea0[753] = _8264; + uint16_t _8265 = (uint16_t)(230); + _curvea0[754] = _8265; + uint16_t _8266 = (uint16_t)(230); + _curvea0[755] = _8266; + uint16_t _8267 = (uint16_t)(230); + _curvea0[756] = _8267; + uint16_t _8268 = (uint16_t)(230); + _curvea0[757] = _8268; + uint16_t _8269 = (uint16_t)(230); + _curvea0[758] = _8269; + uint16_t _8270 = (uint16_t)(231); + _curvea0[759] = _8270; + uint16_t _8271 = (uint16_t)(231); + _curvea0[760] = _8271; + uint16_t _8272 = (uint16_t)(231); + _curvea0[761] = _8272; + uint16_t _8273 = (uint16_t)(231); + _curvea0[762] = _8273; + uint16_t _8274 = (uint16_t)(231); + _curvea0[763] = _8274; + uint16_t _8275 = (uint16_t)(231); + _curvea0[764] = _8275; + uint16_t _8276 = (uint16_t)(231); + _curvea0[765] = _8276; + uint16_t _8277 = (uint16_t)(231); + _curvea0[766] = _8277; + uint16_t _8278 = (uint16_t)(231); + _curvea0[767] = _8278; + uint16_t _8279 = (uint16_t)(232); + _curvea0[768] = _8279; + uint16_t _8280 = (uint16_t)(232); + _curvea0[769] = _8280; + uint16_t _8281 = (uint16_t)(232); + _curvea0[770] = _8281; + uint16_t _8282 = (uint16_t)(232); + _curvea0[771] = _8282; + uint16_t _8283 = (uint16_t)(232); + _curvea0[772] = _8283; + uint16_t _8284 = (uint16_t)(232); + _curvea0[773] = _8284; + uint16_t _8285 = (uint16_t)(232); + _curvea0[774] = _8285; + uint16_t _8286 = (uint16_t)(232); + _curvea0[775] = _8286; + uint16_t _8287 = (uint16_t)(233); + _curvea0[776] = _8287; + uint16_t _8288 = (uint16_t)(233); + _curvea0[777] = _8288; + uint16_t _8289 = (uint16_t)(233); + _curvea0[778] = _8289; + uint16_t _8290 = (uint16_t)(233); + _curvea0[779] = _8290; + uint16_t _8291 = (uint16_t)(233); + _curvea0[780] = _8291; + uint16_t _8292 = (uint16_t)(233); + _curvea0[781] = _8292; + uint16_t _8293 = (uint16_t)(233); + _curvea0[782] = _8293; + uint16_t _8294 = (uint16_t)(233); + _curvea0[783] = _8294; + uint16_t _8295 = (uint16_t)(233); + _curvea0[784] = _8295; + uint16_t _8296 = (uint16_t)(234); + _curvea0[785] = _8296; + uint16_t _8297 = (uint16_t)(234); + _curvea0[786] = _8297; + uint16_t _8298 = (uint16_t)(234); + _curvea0[787] = _8298; + uint16_t _8299 = (uint16_t)(234); + _curvea0[788] = _8299; + uint16_t _8300 = (uint16_t)(234); + _curvea0[789] = _8300; + uint16_t _8301 = (uint16_t)(234); + _curvea0[790] = _8301; + uint16_t _8302 = (uint16_t)(234); + _curvea0[791] = _8302; + uint16_t _8303 = (uint16_t)(234); + _curvea0[792] = _8303; + uint16_t _8304 = (uint16_t)(234); + _curvea0[793] = _8304; + uint16_t _8305 = (uint16_t)(235); + _curvea0[794] = _8305; + uint16_t _8306 = (uint16_t)(235); + _curvea0[795] = _8306; + uint16_t _8307 = (uint16_t)(235); + _curvea0[796] = _8307; + uint16_t _8308 = (uint16_t)(235); + _curvea0[797] = _8308; + uint16_t _8309 = (uint16_t)(235); + _curvea0[798] = _8309; + uint16_t _8310 = (uint16_t)(235); + _curvea0[799] = _8310; + uint16_t _8311 = (uint16_t)(235); + _curvea0[800] = _8311; + uint16_t _8312 = (uint16_t)(235); + _curvea0[801] = _8312; + uint16_t _8313 = (uint16_t)(235); + _curvea0[802] = _8313; + uint16_t _8314 = (uint16_t)(236); + _curvea0[803] = _8314; + uint16_t _8315 = (uint16_t)(236); + _curvea0[804] = _8315; + uint16_t _8316 = (uint16_t)(236); + _curvea0[805] = _8316; + uint16_t _8317 = (uint16_t)(236); + _curvea0[806] = _8317; + uint16_t _8318 = (uint16_t)(236); + _curvea0[807] = _8318; + uint16_t _8319 = (uint16_t)(236); + _curvea0[808] = _8319; + uint16_t _8320 = (uint16_t)(236); + _curvea0[809] = _8320; + uint16_t _8321 = (uint16_t)(236); + _curvea0[810] = _8321; + uint16_t _8322 = (uint16_t)(236); + _curvea0[811] = _8322; + uint16_t _8323 = (uint16_t)(237); + _curvea0[812] = _8323; + uint16_t _8324 = (uint16_t)(237); + _curvea0[813] = _8324; + uint16_t _8325 = (uint16_t)(237); + _curvea0[814] = _8325; + uint16_t _8326 = (uint16_t)(237); + _curvea0[815] = _8326; + uint16_t _8327 = (uint16_t)(237); + _curvea0[816] = _8327; + uint16_t _8328 = (uint16_t)(237); + _curvea0[817] = _8328; + uint16_t _8329 = (uint16_t)(237); + _curvea0[818] = _8329; + uint16_t _8330 = (uint16_t)(237); + _curvea0[819] = _8330; + uint16_t _8331 = (uint16_t)(237); + _curvea0[820] = _8331; + uint16_t _8332 = (uint16_t)(237); + _curvea0[821] = _8332; + uint16_t _8333 = (uint16_t)(238); + _curvea0[822] = _8333; + uint16_t _8334 = (uint16_t)(238); + _curvea0[823] = _8334; + uint16_t _8335 = (uint16_t)(238); + _curvea0[824] = _8335; + uint16_t _8336 = (uint16_t)(238); + _curvea0[825] = _8336; + uint16_t _8337 = (uint16_t)(238); + _curvea0[826] = _8337; + uint16_t _8338 = (uint16_t)(238); + _curvea0[827] = _8338; + uint16_t _8339 = (uint16_t)(238); + _curvea0[828] = _8339; + uint16_t _8340 = (uint16_t)(238); + _curvea0[829] = _8340; + uint16_t _8341 = (uint16_t)(238); + _curvea0[830] = _8341; + uint16_t _8342 = (uint16_t)(239); + _curvea0[831] = _8342; + uint16_t _8343 = (uint16_t)(239); + _curvea0[832] = _8343; + uint16_t _8344 = (uint16_t)(239); + _curvea0[833] = _8344; + uint16_t _8345 = (uint16_t)(239); + _curvea0[834] = _8345; + uint16_t _8346 = (uint16_t)(239); + _curvea0[835] = _8346; + uint16_t _8347 = (uint16_t)(239); + _curvea0[836] = _8347; + uint16_t _8348 = (uint16_t)(239); + _curvea0[837] = _8348; + uint16_t _8349 = (uint16_t)(239); + _curvea0[838] = _8349; + uint16_t _8350 = (uint16_t)(239); + _curvea0[839] = _8350; + uint16_t _8351 = (uint16_t)(239); + _curvea0[840] = _8351; + uint16_t _8352 = (uint16_t)(240); + _curvea0[841] = _8352; + uint16_t _8353 = (uint16_t)(240); + _curvea0[842] = _8353; + uint16_t _8354 = (uint16_t)(240); + _curvea0[843] = _8354; + uint16_t _8355 = (uint16_t)(240); + _curvea0[844] = _8355; + uint16_t _8356 = (uint16_t)(240); + _curvea0[845] = _8356; + uint16_t _8357 = (uint16_t)(240); + _curvea0[846] = _8357; + uint16_t _8358 = (uint16_t)(240); + _curvea0[847] = _8358; + uint16_t _8359 = (uint16_t)(240); + _curvea0[848] = _8359; + uint16_t _8360 = (uint16_t)(240); + _curvea0[849] = _8360; + uint16_t _8361 = (uint16_t)(240); + _curvea0[850] = _8361; + uint16_t _8362 = (uint16_t)(241); + _curvea0[851] = _8362; + uint16_t _8363 = (uint16_t)(241); + _curvea0[852] = _8363; + uint16_t _8364 = (uint16_t)(241); + _curvea0[853] = _8364; + uint16_t _8365 = (uint16_t)(241); + _curvea0[854] = _8365; + uint16_t _8366 = (uint16_t)(241); + _curvea0[855] = _8366; + uint16_t _8367 = (uint16_t)(241); + _curvea0[856] = _8367; + uint16_t _8368 = (uint16_t)(241); + _curvea0[857] = _8368; + uint16_t _8369 = (uint16_t)(241); + _curvea0[858] = _8369; + uint16_t _8370 = (uint16_t)(241); + _curvea0[859] = _8370; + uint16_t _8371 = (uint16_t)(241); + _curvea0[860] = _8371; + uint16_t _8372 = (uint16_t)(242); + _curvea0[861] = _8372; + uint16_t _8373 = (uint16_t)(242); + _curvea0[862] = _8373; + uint16_t _8374 = (uint16_t)(242); + _curvea0[863] = _8374; + uint16_t _8375 = (uint16_t)(242); + _curvea0[864] = _8375; + uint16_t _8376 = (uint16_t)(242); + _curvea0[865] = _8376; + uint16_t _8377 = (uint16_t)(242); + _curvea0[866] = _8377; + uint16_t _8378 = (uint16_t)(242); + _curvea0[867] = _8378; + uint16_t _8379 = (uint16_t)(242); + _curvea0[868] = _8379; + uint16_t _8380 = (uint16_t)(242); + _curvea0[869] = _8380; + uint16_t _8381 = (uint16_t)(242); + _curvea0[870] = _8381; + uint16_t _8382 = (uint16_t)(243); + _curvea0[871] = _8382; + uint16_t _8383 = (uint16_t)(243); + _curvea0[872] = _8383; + uint16_t _8384 = (uint16_t)(243); + _curvea0[873] = _8384; + uint16_t _8385 = (uint16_t)(243); + _curvea0[874] = _8385; + uint16_t _8386 = (uint16_t)(243); + _curvea0[875] = _8386; + uint16_t _8387 = (uint16_t)(243); + _curvea0[876] = _8387; + uint16_t _8388 = (uint16_t)(243); + _curvea0[877] = _8388; + uint16_t _8389 = (uint16_t)(243); + _curvea0[878] = _8389; + uint16_t _8390 = (uint16_t)(243); + _curvea0[879] = _8390; + uint16_t _8391 = (uint16_t)(243); + _curvea0[880] = _8391; + uint16_t _8392 = (uint16_t)(244); + _curvea0[881] = _8392; + uint16_t _8393 = (uint16_t)(244); + _curvea0[882] = _8393; + uint16_t _8394 = (uint16_t)(244); + _curvea0[883] = _8394; + uint16_t _8395 = (uint16_t)(244); + _curvea0[884] = _8395; + uint16_t _8396 = (uint16_t)(244); + _curvea0[885] = _8396; + uint16_t _8397 = (uint16_t)(244); + _curvea0[886] = _8397; + uint16_t _8398 = (uint16_t)(244); + _curvea0[887] = _8398; + uint16_t _8399 = (uint16_t)(244); + _curvea0[888] = _8399; + uint16_t _8400 = (uint16_t)(244); + _curvea0[889] = _8400; + uint16_t _8401 = (uint16_t)(244); + _curvea0[890] = _8401; + uint16_t _8402 = (uint16_t)(244); + _curvea0[891] = _8402; + uint16_t _8403 = (uint16_t)(245); + _curvea0[892] = _8403; + uint16_t _8404 = (uint16_t)(245); + _curvea0[893] = _8404; + uint16_t _8405 = (uint16_t)(245); + _curvea0[894] = _8405; + uint16_t _8406 = (uint16_t)(245); + _curvea0[895] = _8406; + uint16_t _8407 = (uint16_t)(245); + _curvea0[896] = _8407; + uint16_t _8408 = (uint16_t)(245); + _curvea0[897] = _8408; + uint16_t _8409 = (uint16_t)(245); + _curvea0[898] = _8409; + uint16_t _8410 = (uint16_t)(245); + _curvea0[899] = _8410; + uint16_t _8411 = (uint16_t)(245); + _curvea0[900] = _8411; + uint16_t _8412 = (uint16_t)(245); + _curvea0[901] = _8412; + uint16_t _8413 = (uint16_t)(245); + _curvea0[902] = _8413; + uint16_t _8414 = (uint16_t)(246); + _curvea0[903] = _8414; + uint16_t _8415 = (uint16_t)(246); + _curvea0[904] = _8415; + uint16_t _8416 = (uint16_t)(246); + _curvea0[905] = _8416; + uint16_t _8417 = (uint16_t)(246); + _curvea0[906] = _8417; + uint16_t _8418 = (uint16_t)(246); + _curvea0[907] = _8418; + uint16_t _8419 = (uint16_t)(246); + _curvea0[908] = _8419; + uint16_t _8420 = (uint16_t)(246); + _curvea0[909] = _8420; + uint16_t _8421 = (uint16_t)(246); + _curvea0[910] = _8421; + uint16_t _8422 = (uint16_t)(246); + _curvea0[911] = _8422; + uint16_t _8423 = (uint16_t)(246); + _curvea0[912] = _8423; + uint16_t _8424 = (uint16_t)(246); + _curvea0[913] = _8424; + uint16_t _8425 = (uint16_t)(247); + _curvea0[914] = _8425; + uint16_t _8426 = (uint16_t)(247); + _curvea0[915] = _8426; + uint16_t _8427 = (uint16_t)(247); + _curvea0[916] = _8427; + uint16_t _8428 = (uint16_t)(247); + _curvea0[917] = _8428; + uint16_t _8429 = (uint16_t)(247); + _curvea0[918] = _8429; + uint16_t _8430 = (uint16_t)(247); + _curvea0[919] = _8430; + uint16_t _8431 = (uint16_t)(247); + _curvea0[920] = _8431; + uint16_t _8432 = (uint16_t)(247); + _curvea0[921] = _8432; + uint16_t _8433 = (uint16_t)(247); + _curvea0[922] = _8433; + uint16_t _8434 = (uint16_t)(247); + _curvea0[923] = _8434; + uint16_t _8435 = (uint16_t)(247); + _curvea0[924] = _8435; + uint16_t _8436 = (uint16_t)(248); + _curvea0[925] = _8436; + uint16_t _8437 = (uint16_t)(248); + _curvea0[926] = _8437; + uint16_t _8438 = (uint16_t)(248); + _curvea0[927] = _8438; + uint16_t _8439 = (uint16_t)(248); + _curvea0[928] = _8439; + uint16_t _8440 = (uint16_t)(248); + _curvea0[929] = _8440; + uint16_t _8441 = (uint16_t)(248); + _curvea0[930] = _8441; + uint16_t _8442 = (uint16_t)(248); + _curvea0[931] = _8442; + uint16_t _8443 = (uint16_t)(248); + _curvea0[932] = _8443; + uint16_t _8444 = (uint16_t)(248); + _curvea0[933] = _8444; + uint16_t _8445 = (uint16_t)(248); + _curvea0[934] = _8445; + uint16_t _8446 = (uint16_t)(248); + _curvea0[935] = _8446; + uint16_t _8447 = (uint16_t)(249); + _curvea0[936] = _8447; + uint16_t _8448 = (uint16_t)(249); + _curvea0[937] = _8448; + uint16_t _8449 = (uint16_t)(249); + _curvea0[938] = _8449; + uint16_t _8450 = (uint16_t)(249); + _curvea0[939] = _8450; + uint16_t _8451 = (uint16_t)(249); + _curvea0[940] = _8451; + uint16_t _8452 = (uint16_t)(249); + _curvea0[941] = _8452; + uint16_t _8453 = (uint16_t)(249); + _curvea0[942] = _8453; + uint16_t _8454 = (uint16_t)(249); + _curvea0[943] = _8454; + uint16_t _8455 = (uint16_t)(249); + _curvea0[944] = _8455; + uint16_t _8456 = (uint16_t)(249); + _curvea0[945] = _8456; + uint16_t _8457 = (uint16_t)(249); + _curvea0[946] = _8457; + uint16_t _8458 = (uint16_t)(249); + _curvea0[947] = _8458; + uint16_t _8459 = (uint16_t)(250); + _curvea0[948] = _8459; + uint16_t _8460 = (uint16_t)(250); + _curvea0[949] = _8460; + uint16_t _8461 = (uint16_t)(250); + _curvea0[950] = _8461; + uint16_t _8462 = (uint16_t)(250); + _curvea0[951] = _8462; + uint16_t _8463 = (uint16_t)(250); + _curvea0[952] = _8463; + uint16_t _8464 = (uint16_t)(250); + _curvea0[953] = _8464; + uint16_t _8465 = (uint16_t)(250); + _curvea0[954] = _8465; + uint16_t _8466 = (uint16_t)(250); + _curvea0[955] = _8466; + uint16_t _8467 = (uint16_t)(250); + _curvea0[956] = _8467; + uint16_t _8468 = (uint16_t)(250); + _curvea0[957] = _8468; + uint16_t _8469 = (uint16_t)(250); + _curvea0[958] = _8469; + uint16_t _8470 = (uint16_t)(250); + _curvea0[959] = _8470; + uint16_t _8471 = (uint16_t)(251); + _curvea0[960] = _8471; + uint16_t _8472 = (uint16_t)(251); + _curvea0[961] = _8472; + uint16_t _8473 = (uint16_t)(251); + _curvea0[962] = _8473; + uint16_t _8474 = (uint16_t)(251); + _curvea0[963] = _8474; + uint16_t _8475 = (uint16_t)(251); + _curvea0[964] = _8475; + uint16_t _8476 = (uint16_t)(251); + _curvea0[965] = _8476; + uint16_t _8477 = (uint16_t)(251); + _curvea0[966] = _8477; + uint16_t _8478 = (uint16_t)(251); + _curvea0[967] = _8478; + uint16_t _8479 = (uint16_t)(251); + _curvea0[968] = _8479; + uint16_t _8480 = (uint16_t)(251); + _curvea0[969] = _8480; + uint16_t _8481 = (uint16_t)(251); + _curvea0[970] = _8481; + uint16_t _8482 = (uint16_t)(251); + _curvea0[971] = _8482; + uint16_t _8483 = (uint16_t)(252); + _curvea0[972] = _8483; + uint16_t _8484 = (uint16_t)(252); + _curvea0[973] = _8484; + uint16_t _8485 = (uint16_t)(252); + _curvea0[974] = _8485; + uint16_t _8486 = (uint16_t)(252); + _curvea0[975] = _8486; + uint16_t _8487 = (uint16_t)(252); + _curvea0[976] = _8487; + uint16_t _8488 = (uint16_t)(252); + _curvea0[977] = _8488; + uint16_t _8489 = (uint16_t)(252); + _curvea0[978] = _8489; + uint16_t _8490 = (uint16_t)(252); + _curvea0[979] = _8490; + uint16_t _8491 = (uint16_t)(252); + _curvea0[980] = _8491; + uint16_t _8492 = (uint16_t)(252); + _curvea0[981] = _8492; + uint16_t _8493 = (uint16_t)(252); + _curvea0[982] = _8493; + uint16_t _8494 = (uint16_t)(252); + _curvea0[983] = _8494; + uint16_t _8495 = (uint16_t)(252); + _curvea0[984] = _8495; + uint16_t _8496 = (uint16_t)(253); + _curvea0[985] = _8496; + uint16_t _8497 = (uint16_t)(253); + _curvea0[986] = _8497; + uint16_t _8498 = (uint16_t)(253); + _curvea0[987] = _8498; + uint16_t _8499 = (uint16_t)(253); + _curvea0[988] = _8499; + uint16_t _8500 = (uint16_t)(253); + _curvea0[989] = _8500; + uint16_t _8501 = (uint16_t)(253); + _curvea0[990] = _8501; + uint16_t _8502 = (uint16_t)(253); + _curvea0[991] = _8502; + uint16_t _8503 = (uint16_t)(253); + _curvea0[992] = _8503; + uint16_t _8504 = (uint16_t)(253); + _curvea0[993] = _8504; + uint16_t _8505 = (uint16_t)(253); + _curvea0[994] = _8505; + uint16_t _8506 = (uint16_t)(253); + _curvea0[995] = _8506; + uint16_t _8507 = (uint16_t)(253); + _curvea0[996] = _8507; + uint16_t _8508 = (uint16_t)(253); + _curvea0[997] = _8508; + uint16_t _8509 = (uint16_t)(254); + _curvea0[998] = _8509; + uint16_t _8510 = (uint16_t)(254); + _curvea0[999] = _8510; + uint16_t _8511 = (uint16_t)(254); + _curvea0[1000] = _8511; + uint16_t _8512 = (uint16_t)(254); + _curvea0[1001] = _8512; + uint16_t _8513 = (uint16_t)(254); + _curvea0[1002] = _8513; + uint16_t _8514 = (uint16_t)(254); + _curvea0[1003] = _8514; + uint16_t _8515 = (uint16_t)(254); + _curvea0[1004] = _8515; + uint16_t _8516 = (uint16_t)(254); + _curvea0[1005] = _8516; + uint16_t _8517 = (uint16_t)(254); + _curvea0[1006] = _8517; + uint16_t _8518 = (uint16_t)(254); + _curvea0[1007] = _8518; + uint16_t _8519 = (uint16_t)(254); + _curvea0[1008] = _8519; + uint16_t _8520 = (uint16_t)(254); + _curvea0[1009] = _8520; + uint16_t _8521 = (uint16_t)(254); + _curvea0[1010] = _8521; + uint16_t _8522 = (uint16_t)(255); + _curvea0[1011] = _8522; + uint16_t _8523 = (uint16_t)(255); + _curvea0[1012] = _8523; + uint16_t _8524 = (uint16_t)(255); + _curvea0[1013] = _8524; + uint16_t _8525 = (uint16_t)(255); + _curvea0[1014] = _8525; + uint16_t _8526 = (uint16_t)(255); + _curvea0[1015] = _8526; + uint16_t _8527 = (uint16_t)(255); + _curvea0[1016] = _8527; + uint16_t _8528 = (uint16_t)(255); + _curvea0[1017] = _8528; + uint16_t _8529 = (uint16_t)(255); + _curvea0[1018] = _8529; + uint16_t _8530 = (uint16_t)(255); + _curvea0[1019] = _8530; + uint16_t _8531 = (uint16_t)(255); + _curvea0[1020] = _8531; + uint16_t _8532 = (uint16_t)(255); + _curvea0[1021] = _8532; + uint16_t _8533 = (uint16_t)(255); + _curvea0[1022] = _8533; + uint16_t _8534 = (uint16_t)(255); + _curvea0[1023] = _8534; + + int16_t _8535 = (int16_t)(1023); + int16_t _8536 = min(_corrected_stencil_6, _8535); + int16_t _8537 = (int16_t)(0); + int16_t _8538 = max(_8536, _8537); + uint16_t _8539 = (uint16_t)(_8538); + int32_t _8540 = (int32_t)(_8539); + uint16_t _8541 = ((const uint16_t *)_curvea0)[_8540]; + return _8541; +} + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2)) = curved.stencil(hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2), 0) +hw_uint<16> hcompute_hw_output_glb_stencil(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_1 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_1; +} + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2)) = curved.stencil(hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_1(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_2 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_2; +} + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2)) = curved.stencil(hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_2(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_3 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_3; +} + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1), 0) +hw_uint<16> hcompute_hw_output_glb_stencil_3(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_4 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_4; +} + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1), 1) +hw_uint<16> hcompute_hw_output_glb_stencil_4(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_5 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_5; +} + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1), 2) +hw_uint<16> hcompute_hw_output_glb_stencil_5(hw_uint<16>& curved_stencil) { + uint16_t _curved_stencil_6 = (uint16_t) curved_stencil.extract<0, 15>(); + + return _curved_stencil_6; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), ((hw_output_global_wrapper_s0_y_yi_yio + 0)*2)) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_1 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_1; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), ((hw_output_global_wrapper_s0_y_yi_yio + 0)*2)) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_1(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_2 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_2; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), ((hw_output_global_wrapper_s0_y_yi_yio + 0)*2)) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_2(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_3 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_3; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), (((hw_output_global_wrapper_s0_y_yi_yio + 0)*2) + 1)) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_3(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_4 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_4; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), (((hw_output_global_wrapper_s0_y_yi_yio + 0)*2) + 1)) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_4(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_5 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_5; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi + (0*248)), (((hw_output_global_wrapper_s0_y_yi_yio + 0)*2) + 1)) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_5(hw_uint<16>& hw_output_glb_stencil) { + uint16_t _hw_output_glb_stencil_6 = (uint16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_6; +} + diff --git a/cgra_flow.cpp b/cgra_flow.cpp new file mode 100644 index 000000000..3daa701ee --- /dev/null +++ b/cgra_flow.cpp @@ -0,0 +1,56 @@ +#include "cgra_flow.h" +#include "coreir_backend.h" + +#ifdef CGRAFLOW +vector cgra_flow_result(prog& prg, string dir) { + + string name = prg.name; + //auto verilog_files = get_files("./" + dir + "/"+name+"/verilog/"); + //verilog_files.push_back(name + ".v"); + //verilog_files.push_back("LakeWrapper.v"); + vector verilog_files; + verilog_files.push_back(name + ".v"); + verilog_files.push_back("laketop_new.sv"); + //verilog_files.push_back("laketop.sv"); + verilog_files.push_back("LakeTop_flat.v"); + verilog_files.push_back("lake_module_wrappers.v"); + add_default_initial_block("laketop", "endmodule // sram_sp__0"); + bool extra_flag_for_lake = true; + int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); + assert(res == 0); + cmd("rm lake_module_wrappers.v"); + cmd("rm laketop_new.sv"); + cmd("rm LakeTop_flat.v"); + + auto verilator_res = verilator_results(prg.name); + return verilator_res; + +} + +vector aha_flow_result(prog& prg, string dir) { + + string name = prg.name; + //auto verilog_files = get_files("./" + dir + "/"+name+"/verilog/"); + //verilog_files.push_back(name + ".v"); + //verilog_files.push_back("LakeWrapper.v"); + vector verilog_files; + verilog_files.push_back(name + ".v"); + verilog_files.push_back("PE.v"); + verilog_files.push_back("laketop_new.sv"); + //verilog_files.push_back("laketop.sv"); + verilog_files.push_back("LakeTop_flat.v"); + verilog_files.push_back("lake_module_wrappers.v"); + add_default_initial_block("laketop", "endmodule // sram_sp__0"); + bool extra_flag_for_lake = true; + int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); + assert(res == 0); + cmd("rm lake_module_wrappers.v"); + cmd("rm laketop_new.sv"); + cmd("rm LakeTop_flat.v"); + + auto verilator_res = verilator_results(prg.name); + return verilator_res; + +} + +#endif diff --git a/cgra_flow.h b/cgra_flow.h index 9f6c7bf2b..9112ca497 100755 --- a/cgra_flow.h +++ b/cgra_flow.h @@ -25,20 +25,8 @@ void preprocess_prog(prog& prg) { dsa_writers(prg); } -vector cgra_flow_result(prog& prg, string dir) { - - string name = prg.name; - auto verilog_files = get_files("./" + dir + "/"+name+"/verilog/"); - verilog_files.push_back(name + ".v"); - verilog_files.push_back("LakeWrapper.v"); - bool extra_flag_for_lake = true; - int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); - assert(res == 0); - cmd("rm LakeWrapper.v"); - - auto verilator_res = verilator_results(prg.name); - return verilator_res; -} +vector cgra_flow_result(prog& prg, string dir); +vector aha_flow_result(prog& prg, string dir); void sanity_check(prog& prg, vector& cpu, vector & verilator_res) { compare("cgra_" + prg.name + "_cpu_vs_verilog_comparison", verilator_res, cpu); @@ -49,31 +37,14 @@ void sanity_check(prog& prg, vector& cpu, vector & verilator_res cpy_app_to_folder(app_type, prg.name); } -void compile_app_for_garnet_single_port_mem(prog& prg, string dir, bool gen_config_only, bool multi_level_memory) { +void compile_app_for_garnet_single_port_mem(prog& prg, string dir, bool gen_config_only, bool multi_level_memory, bool use_metamapper) { cout << "Running CGRA flow on " << prg.name << endl; //TODO: make this argument explicit to user bool gen_smt = false; - bool use_dse_compute = false; - - compile_for_garnet_single_port_mem(prg, dir, - gen_smt, gen_config_only, multi_level_memory, use_dse_compute); + gen_smt, gen_config_only, multi_level_memory, use_metamapper, prg.name + "_compute_mapped.json", false); } -void compile_app_for_garnet_single_port_mem(prog& prg, string dir, bool gen_config_only) { - cout << "Running CGRA flow on " << prg.name << endl; - - //TODO: make this argument explicit to user - bool multi_level_memory = false; - bool gen_smt = false; - bool use_dse_compute = false; - - - - compile_for_garnet_single_port_mem(prg, dir, - gen_smt, gen_config_only, multi_level_memory, use_dse_compute); - -} diff --git a/cgralib.cpp b/cgralib.cpp index 9155c2d1a..47dcffc4c 100644 --- a/cgralib.cpp +++ b/cgralib.cpp @@ -467,9 +467,9 @@ CoreIR::Namespace* CoreIRLoadLibrary_cgralib(Context* c) { bool has_external_addrgen = genargs.at("has_external_addrgen")->get(); for (size_t i = 0; i < num_input; i ++) { - recordparams.push_back({"data_in_" + std::to_string(i), + recordparams.push_back({lake_port_map.at("data_in_" + std::to_string(i)), c->BitIn()->Arr(width)}); - recordparams.push_back({"chain_data_in_" + std::to_string(i), + recordparams.push_back({lake_port_map.at("chain_data_in_" + std::to_string(i)), c->BitIn()->Arr(width)}); if (has_external_addrgen) { @@ -483,7 +483,7 @@ CoreIR::Namespace* CoreIRLoadLibrary_cgralib(Context* c) { bool has_read_valid = genargs.at("has_read_valid")->get(); for (size_t i = 0; i < num_output; i ++) { - recordparams.push_back({"data_out_" + std::to_string(i), + recordparams.push_back({lake_port_map.at("data_out_" + std::to_string(i)), c->Bit()->Arr(width)}); if (has_read_valid) { @@ -506,16 +506,16 @@ CoreIR::Namespace* CoreIRLoadLibrary_cgralib(Context* c) { bool is_rom = genargs.at("is_rom")->get(); if (is_rom) { - recordparams.push_back({"wen_in_0", c->BitIn()}); - recordparams.push_back({"ren_in_0", c->BitIn()}); - recordparams.push_back({"addr_in_0", c->BitIn()->Arr(width)}); + recordparams.push_back({lake_port_map.at("wen_in_0"), c->BitIn()}); + recordparams.push_back({lake_port_map.at("ren_in_0"), c->BitIn()}); + recordparams.push_back({lake_port_map.at("addr_in_0"), c->BitIn()->Arr(width)}); } if (has_valid) { recordparams.push_back({"valid", c->Bit()}); } if (has_stencil_valid) { - recordparams.push_back({"stencil_valid", c->Bit()}); + recordparams.push_back({lake_port_map.at("stencil_valid"), c->Bit()}); } if (has_flush) { recordparams.push_back({"flush", c->BitIn()}); diff --git a/cgralib.h b/cgralib.h index f15609576..f740415d2 100644 --- a/cgralib.h +++ b/cgralib.h @@ -9,3 +9,21 @@ COREIR_GEN_CPP_API_DECLARATION_FOR_LIBRARY(cgralib); #endif COREIR_GEN_C_API_DECLARATION_FOR_LIBRARY(cgralib); + + +static std::map lake_port_map = + { + {"chain_data_in_0", "input_width_16_num_0"}, + {"chain_data_in_1", "input_width_16_num_1"}, + {"data_in_0", "input_width_16_num_2"}, + {"data_in_1", "input_width_16_num_3"}, + {"data_out_0", "output_width_16_num_0"}, + {"data_out_1", "output_width_16_num_1"}, + {"valid_out_0", "output_width_1_num_0"}, + {"valid_out_1", "output_width_1_num_1"}, + {"stencil_valid", "output_width_1_num_3"}, + {"addr_in_0", "input_width_16_num_2"}, + {"ren_in_0", "input_width_1_num_0"}, + {"wen_in_0", "input_width_1_num_1"} + }; + diff --git a/clockwork_standard_compute_units.h b/clockwork_standard_compute_units.h index a5df7ce08..fda29719a 100644 --- a/clockwork_standard_compute_units.h +++ b/clockwork_standard_compute_units.h @@ -27,6 +27,7 @@ float int_to_float(const hw_uint<32>& in) { return (float) in.to_int(); } + static inline float to_float(const hw_uint<32>& in) { int i = in.to_int(); @@ -783,3 +784,307 @@ static inline float float_from_bits(uint32_t bits) { return reinterpret(bits); } + + + +/** Class that provides a type that implements half precision + * floating point using the bfloat16 format. + * + * Copy from Halide Repo. */ +struct bfloat16_t { + + static const int mantissa_bits = 7; + static const uint16_t sign_mask = 0x8000; + static const uint16_t exponent_mask = 0x7f80; + static const uint16_t mantissa_mask = 0x007f; + + /// \name Constructors + /// @{ + + /** Construct from a float, double, or int using + * round-to-nearest-ties-to-even. Out-of-range values become +/- + * infinity. + */ + // @{ + explicit bfloat16_t(float value); + explicit bfloat16_t(double value); + explicit bfloat16_t(int value); + bfloat16_t(uint16_t value); + // @} + + /** Construct a bfloat16_t with the bits initialised to 0. This represents + * positive zero.*/ + bfloat16_t() = default; + + /// @} + + // Use explicit to avoid accidently raising the precision + /** Cast to float */ + explicit operator float() const; + /** Cast to double */ + explicit operator double() const; + /** Cast to int */ + explicit operator int() const; + operator uint16_t() const; + operator hw_uint<16>() const; + + /** \name Convenience "constructors" + */ + /**@{*/ + + /** Get a new bfloat16_t that represents zero + * \param positive if true then returns positive zero otherwise returns + * negative zero. + */ + static bfloat16_t make_zero(bool positive); + + /** Get a new float16_t that represents infinity + * \param positive if true then returns positive infinity otherwise returns + * negative infinity. + */ + static bfloat16_t make_infinity(bool positive); + + /** Get a new bfloat16_t that represents NaN (not a number) */ + static bfloat16_t make_nan(); + + /** Get a new bfloat16_t with the given raw bits + * + * \param bits The bits conformant to IEEE754 binary16 + */ + static bfloat16_t make_from_bits(uint16_t bits); + + /**@}*/ + + /** Return a new bfloat16_t with a negated sign bit*/ + bfloat16_t operator-() const; + + /** Arithmetic operators. */ + // @{ + bfloat16_t operator+(bfloat16_t rhs) const; + bfloat16_t operator-(bfloat16_t rhs) const; + bfloat16_t operator*(bfloat16_t rhs) const; + bfloat16_t operator/(bfloat16_t rhs) const; + bfloat16_t operator+=(bfloat16_t rhs) { return (*this = *this + rhs); } + bfloat16_t operator-=(bfloat16_t rhs) { return (*this = *this - rhs); } + bfloat16_t operator*=(bfloat16_t rhs) { return (*this = *this * rhs); } + bfloat16_t operator/=(bfloat16_t rhs) { return (*this = *this / rhs); } + // @} + + /** Comparison operators */ + // @{ + bool operator==(bfloat16_t rhs) const; + bool operator!=(bfloat16_t rhs) const { return !(*this == rhs); } + bool operator>(bfloat16_t rhs) const; + bool operator<(bfloat16_t rhs) const; + bool operator>=(bfloat16_t rhs) const { return (*this > rhs) || (*this == rhs); } + bool operator<=(bfloat16_t rhs) const { return (*this < rhs) || (*this == rhs); } + // @} + + /** Properties */ + // @{ + bool is_nan() const; + bool is_infinity() const; + bool is_negative() const; + bool is_zero() const; + // @} + + /** Returns the bits that represent this bfloat16_t. + * + * An alternative method to access the bits is to cast a pointer + * to this instance as a pointer to a uint16_t. + **/ + uint16_t to_bits() const; + +private: + // The raw bits. + uint16_t data = 0; +}; + +//static inline +//bfloat16_t int_to_float(const hw_uint<16>& in) { +// return (bfloat16_t) in.to_int(); +//} +// +//static inline +//bfloat16_t to_float(const hw_uint<16>& in) { +// int i = in.to_int(); +// void* ip = (void*)(&i); +// float* f = (float*) ip; +// return (*f); +//} +// + +float bfloat16_to_float(uint16_t b) { + // Assume little-endian floats + uint16_t bits[2] = {0, b}; + float ret; + memcpy(&ret, bits, sizeof(float)); + return ret; +} + +union { + uint32_t val; + float f; +} union_var; + +uint16_t round_to_even(float a) { + //uint32_t e = reinterpret_cast(a); + union_var.f = a; + uint32_t e = union_var.val; + + // round float to even, comment out this codeblock for truncation + uint32_t half = 0x00008000; + uint32_t sum = e + half; + + // check if bottom bits are all zero + uint32_t mantissa_mask = 0x0000ffff; + bool is_zeroed = (sum & mantissa_mask) == 0; + + // clear last bit (round even) on tie + uint32_t clear_mask = ~( ((uint32_t)is_zeroed) << 16); + e = sum & clear_mask; + + // clear bottom bits + e = e >> 16; + + //return bfloat16_t::make_from_bits(float_to_bfloat16( expf(bfloat16_to_float(a.to_bits())) )); + //return bfloat16_t::make_from_bits( (uint16_t)e ); + return (uint16_t)e; +} + +// Similar routines for bfloat. It's somewhat simpler. +uint16_t float_to_bfloat16(float f) { +// uint16_t ret[2]; +// memcpy(ret, &f, sizeof(float)); +// // Assume little-endian floats +// return ret[1]; + return round_to_even(f); +} + + +bfloat16_t::bfloat16_t(float value) : data(float_to_bfloat16(value)) {} + +bfloat16_t::bfloat16_t(double value) : data(float_to_bfloat16(value)) {} + +bfloat16_t::bfloat16_t(int value) : data(float_to_bfloat16(value)) {} + +bfloat16_t::bfloat16_t(uint16_t value) : data(value) {} + +bfloat16_t::operator float() const { + return bfloat16_to_float(data); +} + +bfloat16_t::operator double() const { + return bfloat16_to_float(data); +} + +bfloat16_t::operator int() const { + return bfloat16_to_float(data); +} + +bfloat16_t::operator uint16_t() const { + return data; +} + +bfloat16_t::operator hw_uint<16>() const { + return data; +} + +bfloat16_t bfloat16_t::make_from_bits(uint16_t bits) { + bfloat16_t f; + f.data = bits; + return f; +} + +bfloat16_t bfloat16_t::make_zero(bool positive) { + uint16_t bits = positive ? 0 : sign_mask; + return bfloat16_t::make_from_bits(bits); +} + +bfloat16_t bfloat16_t::make_infinity(bool positive) { + uint16_t bits = exponent_mask | (positive ? 0 : sign_mask); + return bfloat16_t::make_from_bits(bits); +} + +bfloat16_t bfloat16_t::make_nan() { + uint16_t bits = exponent_mask | mantissa_mask; + return bfloat16_t::make_from_bits(bits); +} + +bfloat16_t bfloat16_t::operator-() const { + return bfloat16_t(-bfloat16_to_float(data)); +} + +bfloat16_t bfloat16_t::operator+(bfloat16_t rhs) const { + return bfloat16_t(bfloat16_to_float(data) + bfloat16_to_float(rhs.data)); +} + +bfloat16_t bfloat16_t::operator-(bfloat16_t rhs) const { + return bfloat16_t(bfloat16_to_float(data) - bfloat16_to_float(rhs.data)); +} + +bfloat16_t bfloat16_t::operator*(bfloat16_t rhs) const { + return bfloat16_t(bfloat16_to_float(data) * bfloat16_to_float(rhs.data)); +} + +bfloat16_t bfloat16_t::operator/(bfloat16_t rhs) const { + return bfloat16_t(bfloat16_to_float(data) / bfloat16_to_float(rhs.data)); +} + +bool bfloat16_t::operator==(bfloat16_t rhs) const { + return bfloat16_to_float(data) == bfloat16_to_float(rhs.data); +} + +bool bfloat16_t::operator>(bfloat16_t rhs) const { + return bfloat16_to_float(data) > bfloat16_to_float(rhs.data); +} + +bool bfloat16_t::operator<(bfloat16_t rhs) const { + return bfloat16_to_float(data) < bfloat16_to_float(rhs.data); +} + +bool bfloat16_t::is_nan() const { + return ((data & exponent_mask) == exponent_mask) && (data & mantissa_mask); +} + +bool bfloat16_t::is_infinity() const { + return ((data & exponent_mask) == exponent_mask) && !(data & mantissa_mask); +} + +bool bfloat16_t::is_negative() const { + return data & sign_mask; +} + +bool bfloat16_t::is_zero() const { + return !(data & ~sign_mask); +} + +uint16_t bfloat16_t::to_bits() const { + return data; +} + +static +inline bfloat16_t bfloat_from_bits(uint32_t bits) { + return bfloat16_t(float_from_bits(bits)); +} + +bfloat16_t exp_bf16(bfloat16_t a) { + float e = bfloat16_to_float(a.to_bits()); + float result = expf(e); + bfloat16_t result_bf16 = bfloat16_t::make_from_bits(round_to_even(result)); + return result_bf16; +} +bfloat16_t pow_bf16(bfloat16_t a, bfloat16_t b) { + float e = bfloat16_to_float(a.to_bits()); + float f = bfloat16_to_float(b.to_bits()); + float result = powf(e, f); + bfloat16_t result_bf16 = bfloat16_t::make_from_bits(round_to_even(result)); + return result_bf16; +} + +bfloat16_t log_bf16(bfloat16_t a) { + float e = bfloat16_to_float(a.to_bits()); + float result = logf(e); + bfloat16_t result_bf16 = bfloat16_t::make_from_bits(round_to_even(result)); + return result_bf16; +} diff --git a/coreir_apps/platonic_buffer/resnet/resnet.json b/coreir_apps/platonic_buffer/resnet/resnet.json index feef38e92..9034e3af1 100644 --- a/coreir_apps/platonic_buffer/resnet/resnet.json +++ b/coreir_apps/platonic_buffer/resnet/resnet.json @@ -5,22 +5,18 @@ "aff__U1":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",4,["Array",16,"BitIn"]]] + ["d",["Array",3,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U11":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U12":{ + "add_all__U10":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U13":{ + "add_all__U11":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U14":{ + "add_all__U9":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, @@ -30,24 +26,19 @@ "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "coeff_1_U4":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0310"]} - }, - "coeff_2_U6":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h001c"]} }, - "coeff_3_U8":{ + "coeff_2_U6":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U10":{ + "const_term_U8":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h3e91"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "mul_d0__U3":{ "genref":"coreir.mul", @@ -60,734 +51,743 @@ "mul_d2__U7":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} - }, - "mul_d3__U9":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U3.out","add_all__U11.in0"], - ["mul_d1__U5.out","add_all__U11.in1"], - ["add_all__U12.in0","add_all__U11.out"], - ["mul_d2__U7.out","add_all__U12.in1"], - ["add_all__U13.in0","add_all__U12.out"], - ["mul_d3__U9.out","add_all__U13.in1"], - ["add_all__U14.in0","add_all__U13.out"], - ["const_term_U10.out","add_all__U14.in1"], - ["self.out","add_all__U14.out"], + ["add_all__U9.out","add_all__U10.in0"], + ["mul_d2__U7.out","add_all__U10.in1"], + ["add_all__U11.in0","add_all__U10.out"], + ["const_term_U8.out","add_all__U11.in1"], + ["self.out","add_all__U11.out"], + ["mul_d0__U3.out","add_all__U9.in0"], + ["mul_d1__U5.out","add_all__U9.in1"], ["mul_d0__U3.in0","coeff_0_U2.out"], ["mul_d1__U5.in0","coeff_1_U4.out"], ["mul_d2__U7.in0","coeff_2_U6.out"], - ["mul_d3__U9.in0","coeff_3_U8.out"], ["self.d.0","mul_d0__U3.in1"], ["self.d.1","mul_d1__U5.in1"], - ["self.d.2","mul_d2__U7.in1"], - ["self.d.3","mul_d3__U9.in1"] + ["self.d.2","mul_d2__U7.in1"] ] }, - "aff__U148":{ + "aff__U122":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",5,["Array",16,"BitIn"]]] + ["d",["Array",4,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U160":{ + "add_all__U132":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U161":{ + "add_all__U133":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U162":{ + "add_all__U134":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U163":{ + "add_all__U135":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U164":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "coeff_0_U149":{ + "coeff_0_U123":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U151":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0048"]} - }, - "coeff_2_U153":{ + "coeff_1_U125":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0018"]} + "modargs":{"value":[["BitVector",16],"16'h0310"]} }, - "coeff_3_U155":{ + "coeff_2_U127":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0008"]} + "modargs":{"value":[["BitVector",16],"16'h001c"]} }, - "coeff_4_U157":{ + "coeff_3_U129":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U159":{ + "const_term_U131":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} - }, - "mul_d0__U150":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} + "modargs":{"value":[["BitVector",16],"16'h3e91"]} }, - "mul_d1__U152":{ + "mul_d0__U124":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U154":{ + "mul_d1__U126":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d3__U156":{ + "mul_d2__U128":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d4__U158":{ + "mul_d3__U130":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U150.out","add_all__U160.in0"], - ["mul_d1__U152.out","add_all__U160.in1"], - ["add_all__U161.in0","add_all__U160.out"], - ["mul_d2__U154.out","add_all__U161.in1"], - ["add_all__U162.in0","add_all__U161.out"], - ["mul_d3__U156.out","add_all__U162.in1"], - ["add_all__U163.in0","add_all__U162.out"], - ["mul_d4__U158.out","add_all__U163.in1"], - ["add_all__U164.in0","add_all__U163.out"], - ["const_term_U159.out","add_all__U164.in1"], - ["self.out","add_all__U164.out"], - ["mul_d0__U150.in0","coeff_0_U149.out"], - ["mul_d1__U152.in0","coeff_1_U151.out"], - ["mul_d2__U154.in0","coeff_2_U153.out"], - ["mul_d3__U156.in0","coeff_3_U155.out"], - ["mul_d4__U158.in0","coeff_4_U157.out"], - ["self.d.0","mul_d0__U150.in1"], - ["self.d.1","mul_d1__U152.in1"], - ["self.d.2","mul_d2__U154.in1"], - ["self.d.3","mul_d3__U156.in1"], - ["self.d.4","mul_d4__U158.in1"] + ["mul_d0__U124.out","add_all__U132.in0"], + ["mul_d1__U126.out","add_all__U132.in1"], + ["add_all__U133.in0","add_all__U132.out"], + ["mul_d2__U128.out","add_all__U133.in1"], + ["add_all__U134.in0","add_all__U133.out"], + ["mul_d3__U130.out","add_all__U134.in1"], + ["add_all__U135.in0","add_all__U134.out"], + ["const_term_U131.out","add_all__U135.in1"], + ["self.out","add_all__U135.out"], + ["mul_d0__U124.in0","coeff_0_U123.out"], + ["mul_d1__U126.in0","coeff_1_U125.out"], + ["mul_d2__U128.in0","coeff_2_U127.out"], + ["mul_d3__U130.in0","coeff_3_U129.out"], + ["self.d.0","mul_d0__U124.in1"], + ["self.d.1","mul_d1__U126.in1"], + ["self.d.2","mul_d2__U128.in1"], + ["self.d.3","mul_d3__U130.in1"] ] }, - "aff__U184":{ + "aff__U165":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",3,["Array",16,"BitIn"]]] + ["d",["Array",5,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U192":{ + "add_all__U177":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U178":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U179":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U193":{ + "add_all__U180":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U194":{ + "add_all__U181":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U185":{ + "coeff_0_U166":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U187":{ + "coeff_1_U168":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001c"]} + "modargs":{"value":[["BitVector",16],"16'h0984"]} + }, + "coeff_2_U170":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h032c"]} + }, + "coeff_3_U172":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} }, - "coeff_2_U189":{ + "coeff_4_U174":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U191":{ + "const_term_U176":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h1f49"]} }, - "mul_d0__U186":{ + "mul_d0__U167":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d1__U188":{ + "mul_d1__U169":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U190":{ + "mul_d2__U171":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_d3__U173":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_d4__U175":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U186.out","add_all__U192.in0"], - ["mul_d1__U188.out","add_all__U192.in1"], - ["add_all__U193.in0","add_all__U192.out"], - ["mul_d2__U190.out","add_all__U193.in1"], - ["add_all__U194.in0","add_all__U193.out"], - ["const_term_U191.out","add_all__U194.in1"], - ["self.out","add_all__U194.out"], - ["mul_d0__U186.in0","coeff_0_U185.out"], - ["mul_d1__U188.in0","coeff_1_U187.out"], - ["mul_d2__U190.in0","coeff_2_U189.out"], - ["self.d.0","mul_d0__U186.in1"], - ["self.d.1","mul_d1__U188.in1"], - ["self.d.2","mul_d2__U190.in1"] + ["mul_d0__U167.out","add_all__U177.in0"], + ["mul_d1__U169.out","add_all__U177.in1"], + ["add_all__U178.in0","add_all__U177.out"], + ["mul_d2__U171.out","add_all__U178.in1"], + ["add_all__U179.in0","add_all__U178.out"], + ["mul_d3__U173.out","add_all__U179.in1"], + ["add_all__U180.in0","add_all__U179.out"], + ["mul_d4__U175.out","add_all__U180.in1"], + ["add_all__U181.in0","add_all__U180.out"], + ["const_term_U176.out","add_all__U181.in1"], + ["self.out","add_all__U181.out"], + ["mul_d0__U167.in0","coeff_0_U166.out"], + ["mul_d1__U169.in0","coeff_1_U168.out"], + ["mul_d2__U171.in0","coeff_2_U170.out"], + ["mul_d3__U173.in0","coeff_3_U172.out"], + ["mul_d4__U175.in0","coeff_4_U174.out"], + ["self.d.0","mul_d0__U167.in1"], + ["self.d.1","mul_d1__U169.in1"], + ["self.d.2","mul_d2__U171.in1"], + ["self.d.3","mul_d3__U173.in1"], + ["self.d.4","mul_d4__U175.in1"] ] }, - "aff__U207":{ + "aff__U217":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",3,["Array",16,"BitIn"]]] + ["d",["Array",5,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U215":{ + "add_all__U229":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U216":{ + "add_all__U230":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U217":{ + "add_all__U231":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U208":{ + "add_all__U232":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U233":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "coeff_0_U218":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U210":{ + "coeff_1_U220":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001c"]} + "modargs":{"value":[["BitVector",16],"16'h0984"]} + }, + "coeff_2_U222":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h032c"]} + }, + "coeff_3_U224":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} }, - "coeff_2_U212":{ + "coeff_4_U226":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U214":{ + "const_term_U228":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h1f49"]} + }, + "mul_d0__U219":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_d1__U221":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} }, - "mul_d0__U209":{ + "mul_d2__U223":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d1__U211":{ + "mul_d3__U225":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U213":{ + "mul_d4__U227":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U209.out","add_all__U215.in0"], - ["mul_d1__U211.out","add_all__U215.in1"], - ["add_all__U216.in0","add_all__U215.out"], - ["mul_d2__U213.out","add_all__U216.in1"], - ["add_all__U217.in0","add_all__U216.out"], - ["const_term_U214.out","add_all__U217.in1"], - ["self.out","add_all__U217.out"], - ["mul_d0__U209.in0","coeff_0_U208.out"], - ["mul_d1__U211.in0","coeff_1_U210.out"], - ["mul_d2__U213.in0","coeff_2_U212.out"], - ["self.d.0","mul_d0__U209.in1"], - ["self.d.1","mul_d1__U211.in1"], - ["self.d.2","mul_d2__U213.in1"] + ["mul_d0__U219.out","add_all__U229.in0"], + ["mul_d1__U221.out","add_all__U229.in1"], + ["add_all__U230.in0","add_all__U229.out"], + ["mul_d2__U223.out","add_all__U230.in1"], + ["add_all__U231.in0","add_all__U230.out"], + ["mul_d3__U225.out","add_all__U231.in1"], + ["add_all__U232.in0","add_all__U231.out"], + ["mul_d4__U227.out","add_all__U232.in1"], + ["add_all__U233.in0","add_all__U232.out"], + ["const_term_U228.out","add_all__U233.in1"], + ["self.out","add_all__U233.out"], + ["mul_d0__U219.in0","coeff_0_U218.out"], + ["mul_d1__U221.in0","coeff_1_U220.out"], + ["mul_d2__U223.in0","coeff_2_U222.out"], + ["mul_d3__U225.in0","coeff_3_U224.out"], + ["mul_d4__U227.in0","coeff_4_U226.out"], + ["self.d.0","mul_d0__U219.in1"], + ["self.d.1","mul_d1__U221.in1"], + ["self.d.2","mul_d2__U223.in1"], + ["self.d.3","mul_d3__U225.in1"], + ["self.d.4","mul_d4__U227.in1"] ] }, - "aff__U230":{ + "aff__U24":{ "type":["Record",[ ["out",["Array",16,"Bit"]], ["d",["Array",3,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U238":{ + "add_all__U32":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U239":{ + "add_all__U33":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U240":{ + "add_all__U34":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U231":{ + "coeff_0_U25":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U233":{ + "coeff_1_U27":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h001c"]} }, - "coeff_2_U235":{ + "coeff_2_U29":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U237":{ + "const_term_U31":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0002"]} }, - "mul_d0__U232":{ + "mul_d0__U26":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d1__U234":{ + "mul_d1__U28":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U236":{ + "mul_d2__U30":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U232.out","add_all__U238.in0"], - ["mul_d1__U234.out","add_all__U238.in1"], - ["add_all__U239.in0","add_all__U238.out"], - ["mul_d2__U236.out","add_all__U239.in1"], - ["add_all__U240.in0","add_all__U239.out"], - ["const_term_U237.out","add_all__U240.in1"], - ["self.out","add_all__U240.out"], - ["mul_d0__U232.in0","coeff_0_U231.out"], - ["mul_d1__U234.in0","coeff_1_U233.out"], - ["mul_d2__U236.in0","coeff_2_U235.out"], - ["self.d.0","mul_d0__U232.in1"], - ["self.d.1","mul_d1__U234.in1"], - ["self.d.2","mul_d2__U236.in1"] + ["mul_d0__U26.out","add_all__U32.in0"], + ["mul_d1__U28.out","add_all__U32.in1"], + ["add_all__U33.in0","add_all__U32.out"], + ["mul_d2__U30.out","add_all__U33.in1"], + ["add_all__U34.in0","add_all__U33.out"], + ["const_term_U31.out","add_all__U34.in1"], + ["self.out","add_all__U34.out"], + ["mul_d0__U26.in0","coeff_0_U25.out"], + ["mul_d1__U28.in0","coeff_1_U27.out"], + ["mul_d2__U30.in0","coeff_2_U29.out"], + ["self.d.0","mul_d0__U26.in1"], + ["self.d.1","mul_d1__U28.in1"], + ["self.d.2","mul_d2__U30.in1"] ] }, - "aff__U253":{ + "aff__U269":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",4,["Array",16,"BitIn"]]] + ["d",["Array",5,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U263":{ + "add_all__U281":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U282":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U264":{ + "add_all__U283":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U265":{ + "add_all__U284":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U266":{ + "add_all__U285":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U254":{ + "coeff_0_U270":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U256":{ + "coeff_1_U272":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h00f0"]} + "modargs":{"value":[["BitVector",16],"16'h0048"]} }, - "coeff_2_U258":{ + "coeff_2_U274":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0018"]} + }, + "coeff_3_U276":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0008"]} }, - "coeff_3_U260":{ + "coeff_4_U278":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U262":{ + "const_term_U280":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0001"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_d0__U271":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} }, - "mul_d0__U255":{ + "mul_d1__U273":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d1__U257":{ + "mul_d2__U275":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U259":{ + "mul_d3__U277":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d3__U261":{ + "mul_d4__U279":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U255.out","add_all__U263.in0"], - ["mul_d1__U257.out","add_all__U263.in1"], - ["add_all__U264.in0","add_all__U263.out"], - ["mul_d2__U259.out","add_all__U264.in1"], - ["add_all__U265.in0","add_all__U264.out"], - ["mul_d3__U261.out","add_all__U265.in1"], - ["add_all__U266.in0","add_all__U265.out"], - ["const_term_U262.out","add_all__U266.in1"], - ["self.out","add_all__U266.out"], - ["mul_d0__U255.in0","coeff_0_U254.out"], - ["mul_d1__U257.in0","coeff_1_U256.out"], - ["mul_d2__U259.in0","coeff_2_U258.out"], - ["mul_d3__U261.in0","coeff_3_U260.out"], - ["self.d.0","mul_d0__U255.in1"], - ["self.d.1","mul_d1__U257.in1"], - ["self.d.2","mul_d2__U259.in1"], - ["self.d.3","mul_d3__U261.in1"] + ["mul_d0__U271.out","add_all__U281.in0"], + ["mul_d1__U273.out","add_all__U281.in1"], + ["add_all__U282.in0","add_all__U281.out"], + ["mul_d2__U275.out","add_all__U282.in1"], + ["add_all__U283.in0","add_all__U282.out"], + ["mul_d3__U277.out","add_all__U283.in1"], + ["add_all__U284.in0","add_all__U283.out"], + ["mul_d4__U279.out","add_all__U284.in1"], + ["add_all__U285.in0","add_all__U284.out"], + ["const_term_U280.out","add_all__U285.in1"], + ["self.out","add_all__U285.out"], + ["mul_d0__U271.in0","coeff_0_U270.out"], + ["mul_d1__U273.in0","coeff_1_U272.out"], + ["mul_d2__U275.in0","coeff_2_U274.out"], + ["mul_d3__U277.in0","coeff_3_U276.out"], + ["mul_d4__U279.in0","coeff_4_U278.out"], + ["self.d.0","mul_d0__U271.in1"], + ["self.d.1","mul_d1__U273.in1"], + ["self.d.2","mul_d2__U275.in1"], + ["self.d.3","mul_d3__U277.in1"], + ["self.d.4","mul_d4__U279.in1"] ] }, - "aff__U282":{ + "aff__U305":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",5,["Array",16,"BitIn"]]] + ["d",["Array",4,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U294":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U295":{ + "add_all__U315":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U296":{ + "add_all__U316":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U297":{ + "add_all__U317":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U298":{ + "add_all__U318":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U283":{ + "coeff_0_U306":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U285":{ + "coeff_1_U308":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0984"]} - }, - "coeff_2_U287":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h032c"]} + "modargs":{"value":[["BitVector",16],"16'h00f0"]} }, - "coeff_3_U289":{ + "coeff_2_U310":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001d"]} + "modargs":{"value":[["BitVector",16],"16'h0008"]} }, - "coeff_4_U291":{ + "coeff_3_U312":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U293":{ + "const_term_U314":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h1f49"]} - }, - "mul_d0__U284":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} + "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "mul_d1__U286":{ + "mul_d0__U307":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U288":{ + "mul_d1__U309":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d3__U290":{ + "mul_d2__U311":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d4__U292":{ + "mul_d3__U313":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U284.out","add_all__U294.in0"], - ["mul_d1__U286.out","add_all__U294.in1"], - ["add_all__U295.in0","add_all__U294.out"], - ["mul_d2__U288.out","add_all__U295.in1"], - ["add_all__U296.in0","add_all__U295.out"], - ["mul_d3__U290.out","add_all__U296.in1"], - ["add_all__U297.in0","add_all__U296.out"], - ["mul_d4__U292.out","add_all__U297.in1"], - ["add_all__U298.in0","add_all__U297.out"], - ["const_term_U293.out","add_all__U298.in1"], - ["self.out","add_all__U298.out"], - ["mul_d0__U284.in0","coeff_0_U283.out"], - ["mul_d1__U286.in0","coeff_1_U285.out"], - ["mul_d2__U288.in0","coeff_2_U287.out"], - ["mul_d3__U290.in0","coeff_3_U289.out"], - ["mul_d4__U292.in0","coeff_4_U291.out"], - ["self.d.0","mul_d0__U284.in1"], - ["self.d.1","mul_d1__U286.in1"], - ["self.d.2","mul_d2__U288.in1"], - ["self.d.3","mul_d3__U290.in1"], - ["self.d.4","mul_d4__U292.in1"] + ["mul_d0__U307.out","add_all__U315.in0"], + ["mul_d1__U309.out","add_all__U315.in1"], + ["add_all__U316.in0","add_all__U315.out"], + ["mul_d2__U311.out","add_all__U316.in1"], + ["add_all__U317.in0","add_all__U316.out"], + ["mul_d3__U313.out","add_all__U317.in1"], + ["add_all__U318.in0","add_all__U317.out"], + ["const_term_U314.out","add_all__U318.in1"], + ["self.out","add_all__U318.out"], + ["mul_d0__U307.in0","coeff_0_U306.out"], + ["mul_d1__U309.in0","coeff_1_U308.out"], + ["mul_d2__U311.in0","coeff_2_U310.out"], + ["mul_d3__U313.in0","coeff_3_U312.out"], + ["self.d.0","mul_d0__U307.in1"], + ["self.d.1","mul_d1__U309.in1"], + ["self.d.2","mul_d2__U311.in1"], + ["self.d.3","mul_d3__U313.in1"] ] }, - "aff__U44":{ + "aff__U47":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",5,["Array",16,"BitIn"]]] + ["d",["Array",3,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U56":{ + "add_all__U55":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U57":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U58":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U59":{ + "add_all__U56":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U60":{ + "add_all__U57":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U45":{ + "coeff_0_U48":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U47":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0984"]} - }, - "coeff_2_U49":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h032c"]} - }, - "coeff_3_U51":{ + "coeff_1_U50":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001d"]} + "modargs":{"value":[["BitVector",16],"16'h001c"]} }, - "coeff_4_U53":{ + "coeff_2_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U55":{ + "const_term_U54":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h1f49"]} - }, - "mul_d0__U46":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} - }, - "mul_d1__U48":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, - "mul_d2__U50":{ + "mul_d0__U49":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d3__U52":{ + "mul_d1__U51":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d4__U54":{ + "mul_d2__U53":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U46.out","add_all__U56.in0"], - ["mul_d1__U48.out","add_all__U56.in1"], + ["mul_d0__U49.out","add_all__U55.in0"], + ["mul_d1__U51.out","add_all__U55.in1"], + ["add_all__U56.in0","add_all__U55.out"], + ["mul_d2__U53.out","add_all__U56.in1"], ["add_all__U57.in0","add_all__U56.out"], - ["mul_d2__U50.out","add_all__U57.in1"], - ["add_all__U58.in0","add_all__U57.out"], - ["mul_d3__U52.out","add_all__U58.in1"], - ["add_all__U59.in0","add_all__U58.out"], - ["mul_d4__U54.out","add_all__U59.in1"], - ["add_all__U60.in0","add_all__U59.out"], - ["const_term_U55.out","add_all__U60.in1"], - ["self.out","add_all__U60.out"], - ["mul_d0__U46.in0","coeff_0_U45.out"], - ["mul_d1__U48.in0","coeff_1_U47.out"], - ["mul_d2__U50.in0","coeff_2_U49.out"], - ["mul_d3__U52.in0","coeff_3_U51.out"], - ["mul_d4__U54.in0","coeff_4_U53.out"], - ["self.d.0","mul_d0__U46.in1"], - ["self.d.1","mul_d1__U48.in1"], - ["self.d.2","mul_d2__U50.in1"], - ["self.d.3","mul_d3__U52.in1"], - ["self.d.4","mul_d4__U54.in1"] + ["const_term_U54.out","add_all__U57.in1"], + ["self.out","add_all__U57.out"], + ["mul_d0__U49.in0","coeff_0_U48.out"], + ["mul_d1__U51.in0","coeff_1_U50.out"], + ["mul_d2__U53.in0","coeff_2_U52.out"], + ["self.d.0","mul_d0__U49.in1"], + ["self.d.1","mul_d1__U51.in1"], + ["self.d.2","mul_d2__U53.in1"] ] }, - "aff__U96":{ + "aff__U70":{ "type":["Record",[ ["out",["Array",16,"Bit"]], ["d",["Array",5,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U108":{ + "add_all__U82":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U109":{ + "add_all__U83":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U110":{ + "add_all__U84":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U111":{ + "add_all__U85":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U112":{ + "add_all__U86":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U97":{ + "coeff_0_U71":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U99":{ + "coeff_1_U73":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0984"]} }, - "coeff_2_U101":{ + "coeff_2_U75":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h032c"]} }, - "coeff_3_U103":{ + "coeff_3_U77":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h001d"]} }, - "coeff_4_U105":{ + "coeff_4_U79":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U107":{ + "const_term_U81":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h1f49"]} }, - "mul_d0__U98":{ + "mul_d0__U72":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d1__U100":{ + "mul_d1__U74":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U102":{ + "mul_d2__U76":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d3__U104":{ + "mul_d3__U78":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d4__U106":{ + "mul_d4__U80":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U98.out","add_all__U108.in0"], - ["mul_d1__U100.out","add_all__U108.in1"], - ["add_all__U109.in0","add_all__U108.out"], - ["mul_d2__U102.out","add_all__U109.in1"], - ["add_all__U110.in0","add_all__U109.out"], - ["mul_d3__U104.out","add_all__U110.in1"], - ["add_all__U111.in0","add_all__U110.out"], - ["mul_d4__U106.out","add_all__U111.in1"], - ["add_all__U112.in0","add_all__U111.out"], - ["const_term_U107.out","add_all__U112.in1"], - ["self.out","add_all__U112.out"], - ["mul_d0__U98.in0","coeff_0_U97.out"], - ["mul_d1__U100.in0","coeff_1_U99.out"], - ["mul_d2__U102.in0","coeff_2_U101.out"], - ["mul_d3__U104.in0","coeff_3_U103.out"], - ["mul_d4__U106.in0","coeff_4_U105.out"], - ["self.d.0","mul_d0__U98.in1"], - ["self.d.1","mul_d1__U100.in1"], - ["self.d.2","mul_d2__U102.in1"], - ["self.d.3","mul_d3__U104.in1"], - ["self.d.4","mul_d4__U106.in1"] + ["mul_d0__U72.out","add_all__U82.in0"], + ["mul_d1__U74.out","add_all__U82.in1"], + ["add_all__U83.in0","add_all__U82.out"], + ["mul_d2__U76.out","add_all__U83.in1"], + ["add_all__U84.in0","add_all__U83.out"], + ["mul_d3__U78.out","add_all__U84.in1"], + ["add_all__U85.in0","add_all__U84.out"], + ["mul_d4__U80.out","add_all__U85.in1"], + ["add_all__U86.in0","add_all__U85.out"], + ["const_term_U81.out","add_all__U86.in1"], + ["self.out","add_all__U86.out"], + ["mul_d0__U72.in0","coeff_0_U71.out"], + ["mul_d1__U74.in0","coeff_1_U73.out"], + ["mul_d2__U76.in0","coeff_2_U75.out"], + ["mul_d3__U78.in0","coeff_3_U77.out"], + ["mul_d4__U80.in0","coeff_4_U79.out"], + ["self.d.0","mul_d0__U72.in1"], + ["self.d.1","mul_d1__U74.in1"], + ["self.d.2","mul_d2__U76.in1"], + ["self.d.3","mul_d3__U78.in1"], + ["self.d.4","mul_d4__U80.in1"] ] }, "affine_controller__U0":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",16,"Bit"]]] + ["d",["Array",3,["Array",16,"Bit"]]] ]], "instances":{ - "_U15":{ + "_U12":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U16":{ + "_U13":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} @@ -804,13 +804,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U17":{ - "modref":"corebit.and" - }, - "d_0_am__U18":{ + "d_0_am__U14":{ "modref":"corebit.and" }, - "d_0_am__U19":{ + "d_0_am__U15":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -844,10 +841,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U20":{ - "modref":"corebit.and" - }, - "d_1_am__U21":{ + "d_1_am__U16":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -861,7 +855,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001b"]} }, "d_1_min":{ "genref":"coreir.const", @@ -881,9 +875,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U22":{ - "modref":"corebit.and" - }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -915,37 +906,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -960,34 +920,29 @@ } }, "connections":[ - ["d_0_inc.in1","_U15.out"], - ["d_1_inc.in1","_U15.out"], - ["d_2_inc.in1","_U15.out"], - ["d_3_inc.in1","_U15.out"], - ["inc_time.in1","_U15.out"], - ["cmp_time.in1","_U16.out"], + ["d_0_inc.in1","_U12.out"], + ["d_1_inc.in1","_U12.out"], + ["d_2_inc.in1","_U12.out"], + ["inc_time.in1","_U12.out"], + ["cmp_time.in1","_U13.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U17.in0"], - ["d_1_at_max.out","d_0_am__U17.in1"], - ["d_0_am__U18.in0","d_0_am__U17.out"], - ["d_2_at_max.out","d_0_am__U18.in1"], - ["d_0_am__U19.in0","d_0_am__U18.out"], - ["d_3_at_max.out","d_0_am__U19.in1"], - ["d_0_next_value.sel","d_0_am__U19.out"], + ["true.out","d_0_am__U14.in0"], + ["d_1_at_max.out","d_0_am__U14.in1"], + ["d_0_am__U15.in0","d_0_am__U14.out"], + ["d_2_at_max.out","d_0_am__U15.in1"], + ["d_0_next_value.sel","d_0_am__U15.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -999,11 +954,9 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U20.in0"], - ["d_2_at_max.out","d_1_am__U20.in1"], - ["d_1_am__U21.in0","d_1_am__U20.out"], - ["d_3_at_max.out","d_1_am__U21.in1"], - ["d_1_next_value.sel","d_1_am__U21.out"], + ["true.out","d_1_am__U16.in0"], + ["d_2_at_max.out","d_1_am__U16.in1"], + ["d_1_next_value.sel","d_1_am__U16.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1015,9 +968,6 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U22.in0"], - ["d_3_at_max.out","d_2_am__U22.in1"], - ["d_2_next_value.sel","d_2_am__U22.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -1027,41 +977,30 @@ ["d_2_reg.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg.in","d_2_next_value.out"], + ["true.out","d_2_next_value.sel"], ["self.clk","d_2_reg.clk"], - ["self.d.2","d_2_reg.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], - ["self.clk","d_3_reg.clk"], - ["self.d.3","d_3_reg.out"] + ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U147":{ + "affine_controller__U121":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",16,"Bit"]]] + ["d",["Array",4,["Array",16,"Bit"]]] ]], "instances":{ - "_U165":{ + "_U136":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U166":{ + "_U137":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U148" + "modref":"global.aff__U122" }, "cmp_time":{ "genref":"coreir.eq", @@ -1072,16 +1011,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U167":{ - "modref":"corebit.and" - }, - "d_0_am__U168":{ + "d_0_am__U138":{ "modref":"corebit.and" }, - "d_0_am__U169":{ + "d_0_am__U139":{ "modref":"corebit.and" }, - "d_0_am__U170":{ + "d_0_am__U140":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1115,13 +1051,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U171":{ - "modref":"corebit.and" - }, - "d_1_am__U172":{ + "d_1_am__U141":{ "modref":"corebit.and" }, - "d_1_am__U173":{ + "d_1_am__U142":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1155,10 +1088,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U174":{ - "modref":"corebit.and" - }, - "d_2_am__U175":{ + "d_2_am__U143":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -1172,7 +1102,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001b"]} }, "d_2_min":{ "genref":"coreir.const", @@ -1192,9 +1122,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_3_am__U176":{ - "modref":"corebit.and" - }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -1206,7 +1133,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001b"]} }, "d_3_min":{ "genref":"coreir.const", @@ -1226,37 +1153,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0007"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -1271,39 +1167,34 @@ } }, "connections":[ - ["d_0_inc.in1","_U165.out"], - ["d_1_inc.in1","_U165.out"], - ["d_2_inc.in1","_U165.out"], - ["d_3_inc.in1","_U165.out"], - ["d_4_inc.in1","_U165.out"], - ["inc_time.in1","_U165.out"], - ["cmp_time.in1","_U166.out"], + ["d_0_inc.in1","_U136.out"], + ["d_1_inc.in1","_U136.out"], + ["d_2_inc.in1","_U136.out"], + ["d_3_inc.in1","_U136.out"], + ["inc_time.in1","_U136.out"], + ["cmp_time.in1","_U137.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], ["d_3_reg.out","affine_func.d.3"], - ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], ["d_3_reg.en","cmp_time.out"], - ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U167.in0"], - ["d_1_at_max.out","d_0_am__U167.in1"], - ["d_0_am__U168.in0","d_0_am__U167.out"], - ["d_2_at_max.out","d_0_am__U168.in1"], - ["d_0_am__U169.in0","d_0_am__U168.out"], - ["d_3_at_max.out","d_0_am__U169.in1"], - ["d_0_am__U170.in0","d_0_am__U169.out"], - ["d_4_at_max.out","d_0_am__U170.in1"], - ["d_0_next_value.sel","d_0_am__U170.out"], + ["true.out","d_0_am__U138.in0"], + ["d_1_at_max.out","d_0_am__U138.in1"], + ["d_0_am__U139.in0","d_0_am__U138.out"], + ["d_2_at_max.out","d_0_am__U139.in1"], + ["d_0_am__U140.in0","d_0_am__U139.out"], + ["d_3_at_max.out","d_0_am__U140.in1"], + ["d_0_next_value.sel","d_0_am__U140.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1315,13 +1206,11 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U171.in0"], - ["d_2_at_max.out","d_1_am__U171.in1"], - ["d_1_am__U172.in0","d_1_am__U171.out"], - ["d_3_at_max.out","d_1_am__U172.in1"], - ["d_1_am__U173.in0","d_1_am__U172.out"], - ["d_4_at_max.out","d_1_am__U173.in1"], - ["d_1_next_value.sel","d_1_am__U173.out"], + ["true.out","d_1_am__U141.in0"], + ["d_2_at_max.out","d_1_am__U141.in1"], + ["d_1_am__U142.in0","d_1_am__U141.out"], + ["d_3_at_max.out","d_1_am__U142.in1"], + ["d_1_next_value.sel","d_1_am__U142.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1333,11 +1222,9 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U174.in0"], - ["d_3_at_max.out","d_2_am__U174.in1"], - ["d_2_am__U175.in0","d_2_am__U174.out"], - ["d_4_at_max.out","d_2_am__U175.in1"], - ["d_2_next_value.sel","d_2_am__U175.out"], + ["true.out","d_2_am__U143.in0"], + ["d_3_at_max.out","d_2_am__U143.in1"], + ["d_2_next_value.sel","d_2_am__U143.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -1349,9 +1236,6 @@ ["d_2_reg.in","d_2_next_value.out"], ["self.clk","d_2_reg.clk"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U176.in0"], - ["d_4_at_max.out","d_3_am__U176.in1"], - ["d_3_next_value.sel","d_3_am__U176.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -1361,41 +1245,30 @@ ["d_3_reg.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], ["self.clk","d_3_reg.clk"], - ["self.d.3","d_3_reg.out"], - ["d_4_reg.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg.in","d_4_next_value.out"], - ["true.out","d_4_next_value.sel"], - ["self.clk","d_4_reg.clk"], - ["self.d.4","d_4_reg.out"] + ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U183":{ + "affine_controller__U164":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",3,["Array",16,"Bit"]]] + ["d",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U195":{ + "_U182":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U196":{ + "_U183":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U184" + "modref":"global.aff__U165" }, "cmp_time":{ "genref":"coreir.eq", @@ -1406,10 +1279,16 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U197":{ + "d_0_am__U184":{ + "modref":"corebit.and" + }, + "d_0_am__U185":{ "modref":"corebit.and" }, - "d_0_am__U198":{ + "d_0_am__U186":{ + "modref":"corebit.and" + }, + "d_0_am__U187":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1443,7 +1322,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U199":{ + "d_1_am__U188":{ + "modref":"corebit.and" + }, + "d_1_am__U189":{ + "modref":"corebit.and" + }, + "d_1_am__U190":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1457,7 +1342,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -1477,6 +1362,12 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_2_am__U191":{ + "modref":"corebit.and" + }, + "d_2_am__U192":{ + "modref":"corebit.and" + }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -1488,7 +1379,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -1508,6 +1399,71 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_3_am__U193":{ + "modref":"corebit.and" + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001b"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001b"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -1522,29 +1478,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U195.out"], - ["d_1_inc.in1","_U195.out"], - ["d_2_inc.in1","_U195.out"], - ["inc_time.in1","_U195.out"], - ["cmp_time.in1","_U196.out"], + ["d_0_inc.in1","_U182.out"], + ["d_1_inc.in1","_U182.out"], + ["d_2_inc.in1","_U182.out"], + ["d_3_inc.in1","_U182.out"], + ["d_4_inc.in1","_U182.out"], + ["inc_time.in1","_U182.out"], + ["cmp_time.in1","_U183.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U197.in0"], - ["d_1_at_max.out","d_0_am__U197.in1"], - ["d_0_am__U198.in0","d_0_am__U197.out"], - ["d_2_at_max.out","d_0_am__U198.in1"], - ["d_0_next_value.sel","d_0_am__U198.out"], + ["true.out","d_0_am__U184.in0"], + ["d_1_at_max.out","d_0_am__U184.in1"], + ["d_0_am__U185.in0","d_0_am__U184.out"], + ["d_2_at_max.out","d_0_am__U185.in1"], + ["d_0_am__U186.in0","d_0_am__U185.out"], + ["d_3_at_max.out","d_0_am__U186.in1"], + ["d_0_am__U187.in0","d_0_am__U186.out"], + ["d_4_at_max.out","d_0_am__U187.in1"], + ["d_0_next_value.sel","d_0_am__U187.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1556,9 +1522,13 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U199.in0"], - ["d_2_at_max.out","d_1_am__U199.in1"], - ["d_1_next_value.sel","d_1_am__U199.out"], + ["true.out","d_1_am__U188.in0"], + ["d_2_at_max.out","d_1_am__U188.in1"], + ["d_1_am__U189.in0","d_1_am__U188.out"], + ["d_3_at_max.out","d_1_am__U189.in1"], + ["d_1_am__U190.in0","d_1_am__U189.out"], + ["d_4_at_max.out","d_1_am__U190.in1"], + ["d_1_next_value.sel","d_1_am__U190.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1570,6 +1540,11 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U191.in0"], + ["d_3_at_max.out","d_2_am__U191.in1"], + ["d_2_am__U192.in0","d_2_am__U191.out"], + ["d_4_at_max.out","d_2_am__U192.in1"], + ["d_2_next_value.sel","d_2_am__U192.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -1579,30 +1554,55 @@ ["d_2_reg.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg.in","d_2_next_value.out"], - ["true.out","d_2_next_value.sel"], ["self.clk","d_2_reg.clk"], - ["self.d.2","d_2_reg.out"] + ["self.d.2","d_2_reg.out"], + ["true.out","d_3_am__U193.in0"], + ["d_4_at_max.out","d_3_am__U193.in1"], + ["d_3_next_value.sel","d_3_am__U193.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["self.clk","d_3_reg.clk"], + ["self.d.3","d_3_reg.out"], + ["d_4_reg.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg.in","d_4_next_value.out"], + ["true.out","d_4_next_value.sel"], + ["self.clk","d_4_reg.clk"], + ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U206":{ + "affine_controller__U216":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",3,["Array",16,"Bit"]]] + ["d",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U218":{ + "_U234":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U219":{ + "_U235":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U207" + "modref":"global.aff__U217" }, "cmp_time":{ "genref":"coreir.eq", @@ -1613,10 +1613,16 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U220":{ + "d_0_am__U236":{ + "modref":"corebit.and" + }, + "d_0_am__U237":{ + "modref":"corebit.and" + }, + "d_0_am__U238":{ "modref":"corebit.and" }, - "d_0_am__U221":{ + "d_0_am__U239":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1650,7 +1656,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U222":{ + "d_1_am__U240":{ + "modref":"corebit.and" + }, + "d_1_am__U241":{ + "modref":"corebit.and" + }, + "d_1_am__U242":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1664,7 +1676,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -1684,6 +1696,12 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_2_am__U243":{ + "modref":"corebit.and" + }, + "d_2_am__U244":{ + "modref":"corebit.and" + }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -1695,7 +1713,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -1715,6 +1733,71 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_3_am__U245":{ + "modref":"corebit.and" + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001b"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001b"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -1729,29 +1812,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U218.out"], - ["d_1_inc.in1","_U218.out"], - ["d_2_inc.in1","_U218.out"], - ["inc_time.in1","_U218.out"], - ["cmp_time.in1","_U219.out"], + ["d_0_inc.in1","_U234.out"], + ["d_1_inc.in1","_U234.out"], + ["d_2_inc.in1","_U234.out"], + ["d_3_inc.in1","_U234.out"], + ["d_4_inc.in1","_U234.out"], + ["inc_time.in1","_U234.out"], + ["cmp_time.in1","_U235.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U220.in0"], - ["d_1_at_max.out","d_0_am__U220.in1"], - ["d_0_am__U221.in0","d_0_am__U220.out"], - ["d_2_at_max.out","d_0_am__U221.in1"], - ["d_0_next_value.sel","d_0_am__U221.out"], + ["true.out","d_0_am__U236.in0"], + ["d_1_at_max.out","d_0_am__U236.in1"], + ["d_0_am__U237.in0","d_0_am__U236.out"], + ["d_2_at_max.out","d_0_am__U237.in1"], + ["d_0_am__U238.in0","d_0_am__U237.out"], + ["d_3_at_max.out","d_0_am__U238.in1"], + ["d_0_am__U239.in0","d_0_am__U238.out"], + ["d_4_at_max.out","d_0_am__U239.in1"], + ["d_0_next_value.sel","d_0_am__U239.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1763,9 +1856,13 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U222.in0"], - ["d_2_at_max.out","d_1_am__U222.in1"], - ["d_1_next_value.sel","d_1_am__U222.out"], + ["true.out","d_1_am__U240.in0"], + ["d_2_at_max.out","d_1_am__U240.in1"], + ["d_1_am__U241.in0","d_1_am__U240.out"], + ["d_3_at_max.out","d_1_am__U241.in1"], + ["d_1_am__U242.in0","d_1_am__U241.out"], + ["d_4_at_max.out","d_1_am__U242.in1"], + ["d_1_next_value.sel","d_1_am__U242.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1777,6 +1874,11 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U243.in0"], + ["d_3_at_max.out","d_2_am__U243.in1"], + ["d_2_am__U244.in0","d_2_am__U243.out"], + ["d_4_at_max.out","d_2_am__U244.in1"], + ["d_2_next_value.sel","d_2_am__U244.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -1786,30 +1888,55 @@ ["d_2_reg.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg.in","d_2_next_value.out"], - ["true.out","d_2_next_value.sel"], ["self.clk","d_2_reg.clk"], - ["self.d.2","d_2_reg.out"] + ["self.d.2","d_2_reg.out"], + ["true.out","d_3_am__U245.in0"], + ["d_4_at_max.out","d_3_am__U245.in1"], + ["d_3_next_value.sel","d_3_am__U245.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["self.clk","d_3_reg.clk"], + ["self.d.3","d_3_reg.out"], + ["d_4_reg.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg.in","d_4_next_value.out"], + ["true.out","d_4_next_value.sel"], + ["self.clk","d_4_reg.clk"], + ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U229":{ + "affine_controller__U23":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], ["d",["Array",3,["Array",16,"Bit"]]] ]], "instances":{ - "_U241":{ + "_U35":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U242":{ + "_U36":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U230" + "modref":"global.aff__U24" }, "cmp_time":{ "genref":"coreir.eq", @@ -1820,10 +1947,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U243":{ + "d_0_am__U37":{ "modref":"corebit.and" }, - "d_0_am__U244":{ + "d_0_am__U38":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -1857,7 +1984,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U245":{ + "d_1_am__U39":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -1936,11 +2063,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U241.out"], - ["d_1_inc.in1","_U241.out"], - ["d_2_inc.in1","_U241.out"], - ["inc_time.in1","_U241.out"], - ["cmp_time.in1","_U242.out"], + ["d_0_inc.in1","_U35.out"], + ["d_1_inc.in1","_U35.out"], + ["d_2_inc.in1","_U35.out"], + ["inc_time.in1","_U35.out"], + ["cmp_time.in1","_U36.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -1954,11 +2081,11 @@ ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U243.in0"], - ["d_1_at_max.out","d_0_am__U243.in1"], - ["d_0_am__U244.in0","d_0_am__U243.out"], - ["d_2_at_max.out","d_0_am__U244.in1"], - ["d_0_next_value.sel","d_0_am__U244.out"], + ["true.out","d_0_am__U37.in0"], + ["d_1_at_max.out","d_0_am__U37.in1"], + ["d_0_am__U38.in0","d_0_am__U37.out"], + ["d_2_at_max.out","d_0_am__U38.in1"], + ["d_0_next_value.sel","d_0_am__U38.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -1970,9 +2097,9 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U245.in0"], - ["d_2_at_max.out","d_1_am__U245.in1"], - ["d_1_next_value.sel","d_1_am__U245.out"], + ["true.out","d_1_am__U39.in0"], + ["d_2_at_max.out","d_1_am__U39.in1"], + ["d_1_next_value.sel","d_1_am__U39.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -1998,25 +2125,25 @@ ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U252":{ + "affine_controller__U268":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",4,["Array",16,"Bit"]]] + ["d",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U267":{ + "_U286":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U268":{ + "_U287":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U253" + "modref":"global.aff__U269" }, "cmp_time":{ "genref":"coreir.eq", @@ -2027,13 +2154,16 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U269":{ + "d_0_am__U288":{ + "modref":"corebit.and" + }, + "d_0_am__U289":{ "modref":"corebit.and" }, - "d_0_am__U270":{ + "d_0_am__U290":{ "modref":"corebit.and" }, - "d_0_am__U271":{ + "d_0_am__U291":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2067,10 +2197,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U272":{ + "d_1_am__U292":{ "modref":"corebit.and" }, - "d_1_am__U273":{ + "d_1_am__U293":{ + "modref":"corebit.and" + }, + "d_1_am__U294":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2084,7 +2217,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001d"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2104,7 +2237,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U274":{ + "d_2_am__U295":{ + "modref":"corebit.and" + }, + "d_2_am__U296":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2118,7 +2254,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001d"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2138,6 +2274,9 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_3_am__U297":{ + "modref":"corebit.and" + }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -2149,7 +2288,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0007"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_3_min":{ "genref":"coreir.const", @@ -2169,6 +2308,37 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -2183,34 +2353,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U267.out"], - ["d_1_inc.in1","_U267.out"], - ["d_2_inc.in1","_U267.out"], - ["d_3_inc.in1","_U267.out"], - ["inc_time.in1","_U267.out"], - ["cmp_time.in1","_U268.out"], + ["d_0_inc.in1","_U286.out"], + ["d_1_inc.in1","_U286.out"], + ["d_2_inc.in1","_U286.out"], + ["d_3_inc.in1","_U286.out"], + ["d_4_inc.in1","_U286.out"], + ["inc_time.in1","_U286.out"], + ["cmp_time.in1","_U287.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], ["d_3_reg.out","affine_func.d.3"], + ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], ["d_3_reg.en","cmp_time.out"], + ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U269.in0"], - ["d_1_at_max.out","d_0_am__U269.in1"], - ["d_0_am__U270.in0","d_0_am__U269.out"], - ["d_2_at_max.out","d_0_am__U270.in1"], - ["d_0_am__U271.in0","d_0_am__U270.out"], - ["d_3_at_max.out","d_0_am__U271.in1"], - ["d_0_next_value.sel","d_0_am__U271.out"], + ["true.out","d_0_am__U288.in0"], + ["d_1_at_max.out","d_0_am__U288.in1"], + ["d_0_am__U289.in0","d_0_am__U288.out"], + ["d_2_at_max.out","d_0_am__U289.in1"], + ["d_0_am__U290.in0","d_0_am__U289.out"], + ["d_3_at_max.out","d_0_am__U290.in1"], + ["d_0_am__U291.in0","d_0_am__U290.out"], + ["d_4_at_max.out","d_0_am__U291.in1"], + ["d_0_next_value.sel","d_0_am__U291.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2222,11 +2397,13 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U272.in0"], - ["d_2_at_max.out","d_1_am__U272.in1"], - ["d_1_am__U273.in0","d_1_am__U272.out"], - ["d_3_at_max.out","d_1_am__U273.in1"], - ["d_1_next_value.sel","d_1_am__U273.out"], + ["true.out","d_1_am__U292.in0"], + ["d_2_at_max.out","d_1_am__U292.in1"], + ["d_1_am__U293.in0","d_1_am__U292.out"], + ["d_3_at_max.out","d_1_am__U293.in1"], + ["d_1_am__U294.in0","d_1_am__U293.out"], + ["d_4_at_max.out","d_1_am__U294.in1"], + ["d_1_next_value.sel","d_1_am__U294.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2238,9 +2415,11 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U274.in0"], - ["d_3_at_max.out","d_2_am__U274.in1"], - ["d_2_next_value.sel","d_2_am__U274.out"], + ["true.out","d_2_am__U295.in0"], + ["d_3_at_max.out","d_2_am__U295.in1"], + ["d_2_am__U296.in0","d_2_am__U295.out"], + ["d_4_at_max.out","d_2_am__U296.in1"], + ["d_2_next_value.sel","d_2_am__U296.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2252,6 +2431,9 @@ ["d_2_reg.in","d_2_next_value.out"], ["self.clk","d_2_reg.clk"], ["self.d.2","d_2_reg.out"], + ["true.out","d_3_am__U297.in0"], + ["d_4_at_max.out","d_3_am__U297.in1"], + ["d_3_next_value.sel","d_3_am__U297.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2261,30 +2443,41 @@ ["d_3_reg.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg.in","d_3_next_value.out"], - ["true.out","d_3_next_value.sel"], ["self.clk","d_3_reg.clk"], - ["self.d.3","d_3_reg.out"] + ["self.d.3","d_3_reg.out"], + ["d_4_reg.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg.in","d_4_next_value.out"], + ["true.out","d_4_next_value.sel"], + ["self.clk","d_4_reg.clk"], + ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U281":{ + "affine_controller__U304":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",16,"Bit"]]] + ["d",["Array",4,["Array",16,"Bit"]]] ]], "instances":{ - "_U299":{ + "_U319":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U300":{ + "_U320":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U282" + "modref":"global.aff__U305" }, "cmp_time":{ "genref":"coreir.eq", @@ -2295,16 +2488,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U301":{ + "d_0_am__U321":{ "modref":"corebit.and" }, - "d_0_am__U302":{ + "d_0_am__U322":{ "modref":"corebit.and" }, - "d_0_am__U303":{ - "modref":"corebit.and" - }, - "d_0_am__U304":{ + "d_0_am__U323":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2338,13 +2528,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U305":{ - "modref":"corebit.and" - }, - "d_1_am__U306":{ + "d_1_am__U324":{ "modref":"corebit.and" }, - "d_1_am__U307":{ + "d_1_am__U325":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2358,7 +2545,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001d"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2378,10 +2565,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U308":{ - "modref":"corebit.and" - }, - "d_2_am__U309":{ + "d_2_am__U326":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -2395,7 +2579,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001d"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2415,9 +2599,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_3_am__U310":{ - "modref":"corebit.and" - }, "d_3_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -2429,7 +2610,7 @@ "d_3_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} + "modargs":{"value":[["BitVector",16],"16'h0007"]} }, "d_3_min":{ "genref":"coreir.const", @@ -2449,37 +2630,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -2494,39 +2644,34 @@ } }, "connections":[ - ["d_0_inc.in1","_U299.out"], - ["d_1_inc.in1","_U299.out"], - ["d_2_inc.in1","_U299.out"], - ["d_3_inc.in1","_U299.out"], - ["d_4_inc.in1","_U299.out"], - ["inc_time.in1","_U299.out"], - ["cmp_time.in1","_U300.out"], + ["d_0_inc.in1","_U319.out"], + ["d_1_inc.in1","_U319.out"], + ["d_2_inc.in1","_U319.out"], + ["d_3_inc.in1","_U319.out"], + ["inc_time.in1","_U319.out"], + ["cmp_time.in1","_U320.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], ["d_3_reg.out","affine_func.d.3"], - ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], ["d_3_reg.en","cmp_time.out"], - ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U301.in0"], - ["d_1_at_max.out","d_0_am__U301.in1"], - ["d_0_am__U302.in0","d_0_am__U301.out"], - ["d_2_at_max.out","d_0_am__U302.in1"], - ["d_0_am__U303.in0","d_0_am__U302.out"], - ["d_3_at_max.out","d_0_am__U303.in1"], - ["d_0_am__U304.in0","d_0_am__U303.out"], - ["d_4_at_max.out","d_0_am__U304.in1"], - ["d_0_next_value.sel","d_0_am__U304.out"], + ["true.out","d_0_am__U321.in0"], + ["d_1_at_max.out","d_0_am__U321.in1"], + ["d_0_am__U322.in0","d_0_am__U321.out"], + ["d_2_at_max.out","d_0_am__U322.in1"], + ["d_0_am__U323.in0","d_0_am__U322.out"], + ["d_3_at_max.out","d_0_am__U323.in1"], + ["d_0_next_value.sel","d_0_am__U323.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2538,13 +2683,11 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U305.in0"], - ["d_2_at_max.out","d_1_am__U305.in1"], - ["d_1_am__U306.in0","d_1_am__U305.out"], - ["d_3_at_max.out","d_1_am__U306.in1"], - ["d_1_am__U307.in0","d_1_am__U306.out"], - ["d_4_at_max.out","d_1_am__U307.in1"], - ["d_1_next_value.sel","d_1_am__U307.out"], + ["true.out","d_1_am__U324.in0"], + ["d_2_at_max.out","d_1_am__U324.in1"], + ["d_1_am__U325.in0","d_1_am__U324.out"], + ["d_3_at_max.out","d_1_am__U325.in1"], + ["d_1_next_value.sel","d_1_am__U325.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2556,11 +2699,9 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U308.in0"], - ["d_3_at_max.out","d_2_am__U308.in1"], - ["d_2_am__U309.in0","d_2_am__U308.out"], - ["d_4_at_max.out","d_2_am__U309.in1"], - ["d_2_next_value.sel","d_2_am__U309.out"], + ["true.out","d_2_am__U326.in0"], + ["d_3_at_max.out","d_2_am__U326.in1"], + ["d_2_next_value.sel","d_2_am__U326.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2572,9 +2713,6 @@ ["d_2_reg.in","d_2_next_value.out"], ["self.clk","d_2_reg.clk"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U310.in0"], - ["d_4_at_max.out","d_3_am__U310.in1"], - ["d_3_next_value.sel","d_3_am__U310.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -2584,41 +2722,30 @@ ["d_3_reg.out","d_3_next_value.in0"], ["d_3_next_value_at_max.out","d_3_next_value.in1"], ["d_3_reg.in","d_3_next_value.out"], + ["true.out","d_3_next_value.sel"], ["self.clk","d_3_reg.clk"], - ["self.d.3","d_3_reg.out"], - ["d_4_reg.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg.in","d_4_next_value.out"], - ["true.out","d_4_next_value.sel"], - ["self.clk","d_4_reg.clk"], - ["self.d.4","d_4_reg.out"] + ["self.d.3","d_3_reg.out"] ] }, - "affine_controller__U43":{ + "affine_controller__U46":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",16,"Bit"]]] + ["d",["Array",3,["Array",16,"Bit"]]] ]], "instances":{ - "_U61":{ + "_U58":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U62":{ + "_U59":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U44" + "modref":"global.aff__U47" }, "cmp_time":{ "genref":"coreir.eq", @@ -2629,16 +2756,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U63":{ - "modref":"corebit.and" - }, - "d_0_am__U64":{ - "modref":"corebit.and" - }, - "d_0_am__U65":{ + "d_0_am__U60":{ "modref":"corebit.and" }, - "d_0_am__U66":{ + "d_0_am__U61":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -2672,13 +2793,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U67":{ - "modref":"corebit.and" - }, - "d_1_am__U68":{ - "modref":"corebit.and" - }, - "d_1_am__U69":{ + "d_1_am__U62":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -2692,7 +2807,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001b"]} }, "d_1_min":{ "genref":"coreir.const", @@ -2712,12 +2827,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U70":{ - "modref":"corebit.and" - }, - "d_2_am__U71":{ - "modref":"corebit.and" - }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -2729,7 +2838,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001b"]} }, "d_2_min":{ "genref":"coreir.const", @@ -2749,71 +2858,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_3_am__U72":{ - "modref":"corebit.and" - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -2828,39 +2872,29 @@ } }, "connections":[ - ["d_0_inc.in1","_U61.out"], - ["d_1_inc.in1","_U61.out"], - ["d_2_inc.in1","_U61.out"], - ["d_3_inc.in1","_U61.out"], - ["d_4_inc.in1","_U61.out"], - ["inc_time.in1","_U61.out"], - ["cmp_time.in1","_U62.out"], + ["d_0_inc.in1","_U58.out"], + ["d_1_inc.in1","_U58.out"], + ["d_2_inc.in1","_U58.out"], + ["inc_time.in1","_U58.out"], + ["cmp_time.in1","_U59.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U63.in0"], - ["d_1_at_max.out","d_0_am__U63.in1"], - ["d_0_am__U64.in0","d_0_am__U63.out"], - ["d_2_at_max.out","d_0_am__U64.in1"], - ["d_0_am__U65.in0","d_0_am__U64.out"], - ["d_3_at_max.out","d_0_am__U65.in1"], - ["d_0_am__U66.in0","d_0_am__U65.out"], - ["d_4_at_max.out","d_0_am__U66.in1"], - ["d_0_next_value.sel","d_0_am__U66.out"], + ["true.out","d_0_am__U60.in0"], + ["d_1_at_max.out","d_0_am__U60.in1"], + ["d_0_am__U61.in0","d_0_am__U60.out"], + ["d_2_at_max.out","d_0_am__U61.in1"], + ["d_0_next_value.sel","d_0_am__U61.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -2872,13 +2906,9 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U67.in0"], - ["d_2_at_max.out","d_1_am__U67.in1"], - ["d_1_am__U68.in0","d_1_am__U67.out"], - ["d_3_at_max.out","d_1_am__U68.in1"], - ["d_1_am__U69.in0","d_1_am__U68.out"], - ["d_4_at_max.out","d_1_am__U69.in1"], - ["d_1_next_value.sel","d_1_am__U69.out"], + ["true.out","d_1_am__U62.in0"], + ["d_2_at_max.out","d_1_am__U62.in1"], + ["d_1_next_value.sel","d_1_am__U62.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -2890,11 +2920,6 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U70.in0"], - ["d_3_at_max.out","d_2_am__U70.in1"], - ["d_2_am__U71.in0","d_2_am__U70.out"], - ["d_4_at_max.out","d_2_am__U71.in1"], - ["d_2_next_value.sel","d_2_am__U71.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -2904,55 +2929,30 @@ ["d_2_reg.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg.in","d_2_next_value.out"], + ["true.out","d_2_next_value.sel"], ["self.clk","d_2_reg.clk"], - ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U72.in0"], - ["d_4_at_max.out","d_3_am__U72.in1"], - ["d_3_next_value.sel","d_3_am__U72.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["self.clk","d_3_reg.clk"], - ["self.d.3","d_3_reg.out"], - ["d_4_reg.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg.in","d_4_next_value.out"], - ["true.out","d_4_next_value.sel"], - ["self.clk","d_4_reg.clk"], - ["self.d.4","d_4_reg.out"] + ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U95":{ + "affine_controller__U69":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], ["d",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U113":{ + "_U87":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U114":{ + "_U88":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U96" + "modref":"global.aff__U70" }, "cmp_time":{ "genref":"coreir.eq", @@ -2963,16 +2963,16 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U115":{ + "d_0_am__U89":{ "modref":"corebit.and" }, - "d_0_am__U116":{ + "d_0_am__U90":{ "modref":"corebit.and" }, - "d_0_am__U117":{ + "d_0_am__U91":{ "modref":"corebit.and" }, - "d_0_am__U118":{ + "d_0_am__U92":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -3006,13 +3006,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U119":{ + "d_1_am__U93":{ "modref":"corebit.and" }, - "d_1_am__U120":{ + "d_1_am__U94":{ "modref":"corebit.and" }, - "d_1_am__U121":{ + "d_1_am__U95":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -3046,10 +3046,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U122":{ + "d_2_am__U96":{ "modref":"corebit.and" }, - "d_2_am__U123":{ + "d_2_am__U97":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -3083,7 +3083,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_3_am__U124":{ + "d_3_am__U98":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -3162,13 +3162,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U113.out"], - ["d_1_inc.in1","_U113.out"], - ["d_2_inc.in1","_U113.out"], - ["d_3_inc.in1","_U113.out"], - ["d_4_inc.in1","_U113.out"], - ["inc_time.in1","_U113.out"], - ["cmp_time.in1","_U114.out"], + ["d_0_inc.in1","_U87.out"], + ["d_1_inc.in1","_U87.out"], + ["d_2_inc.in1","_U87.out"], + ["d_3_inc.in1","_U87.out"], + ["d_4_inc.in1","_U87.out"], + ["inc_time.in1","_U87.out"], + ["cmp_time.in1","_U88.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -3186,15 +3186,15 @@ ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U115.in0"], - ["d_1_at_max.out","d_0_am__U115.in1"], - ["d_0_am__U116.in0","d_0_am__U115.out"], - ["d_2_at_max.out","d_0_am__U116.in1"], - ["d_0_am__U117.in0","d_0_am__U116.out"], - ["d_3_at_max.out","d_0_am__U117.in1"], - ["d_0_am__U118.in0","d_0_am__U117.out"], - ["d_4_at_max.out","d_0_am__U118.in1"], - ["d_0_next_value.sel","d_0_am__U118.out"], + ["true.out","d_0_am__U89.in0"], + ["d_1_at_max.out","d_0_am__U89.in1"], + ["d_0_am__U90.in0","d_0_am__U89.out"], + ["d_2_at_max.out","d_0_am__U90.in1"], + ["d_0_am__U91.in0","d_0_am__U90.out"], + ["d_3_at_max.out","d_0_am__U91.in1"], + ["d_0_am__U92.in0","d_0_am__U91.out"], + ["d_4_at_max.out","d_0_am__U92.in1"], + ["d_0_next_value.sel","d_0_am__U92.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -3206,13 +3206,13 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U119.in0"], - ["d_2_at_max.out","d_1_am__U119.in1"], - ["d_1_am__U120.in0","d_1_am__U119.out"], - ["d_3_at_max.out","d_1_am__U120.in1"], - ["d_1_am__U121.in0","d_1_am__U120.out"], - ["d_4_at_max.out","d_1_am__U121.in1"], - ["d_1_next_value.sel","d_1_am__U121.out"], + ["true.out","d_1_am__U93.in0"], + ["d_2_at_max.out","d_1_am__U93.in1"], + ["d_1_am__U94.in0","d_1_am__U93.out"], + ["d_3_at_max.out","d_1_am__U94.in1"], + ["d_1_am__U95.in0","d_1_am__U94.out"], + ["d_4_at_max.out","d_1_am__U95.in1"], + ["d_1_next_value.sel","d_1_am__U95.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -3224,11 +3224,11 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U122.in0"], - ["d_3_at_max.out","d_2_am__U122.in1"], - ["d_2_am__U123.in0","d_2_am__U122.out"], - ["d_4_at_max.out","d_2_am__U123.in1"], - ["d_2_next_value.sel","d_2_am__U123.out"], + ["true.out","d_2_am__U96.in0"], + ["d_3_at_max.out","d_2_am__U96.in1"], + ["d_2_am__U97.in0","d_2_am__U96.out"], + ["d_4_at_max.out","d_2_am__U97.in1"], + ["d_2_next_value.sel","d_2_am__U97.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -3240,9 +3240,9 @@ ["d_2_reg.in","d_2_next_value.out"], ["self.clk","d_2_reg.clk"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U124.in0"], - ["d_4_at_max.out","d_3_am__U124.in1"], - ["d_3_next_value.sel","d_3_am__U124.out"], + ["true.out","d_3_am__U98.in0"], + ["d_4_at_max.out","d_3_am__U98.in1"], + ["d_3_next_value.sel","d_3_am__U98.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -3268,396 +3268,396 @@ ["self.d.4","d_4_reg.out"] ] }, - "array_delay_U131":{ + "array_delay_U105":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U132":{ + "_U106":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U133":{ + "_U107":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U134":{ + "_U108":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U135":{ + "_U109":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U136":{ + "_U110":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U132.clk"], - ["self.in.0","_U132.in"], - ["self.out.0","_U132.out"], - ["self.clk","_U133.clk"], - ["self.in.1","_U133.in"], - ["self.out.1","_U133.out"], - ["self.clk","_U134.clk"], - ["self.in.2","_U134.in"], - ["self.out.2","_U134.out"], - ["self.clk","_U135.clk"], - ["self.in.3","_U135.in"], - ["self.out.3","_U135.out"], - ["self.clk","_U136.clk"], - ["self.in.4","_U136.in"], - ["self.out.4","_U136.out"] + ["self.clk","_U106.clk"], + ["self.in.0","_U106.in"], + ["self.out.0","_U106.out"], + ["self.clk","_U107.clk"], + ["self.in.1","_U107.in"], + ["self.out.1","_U107.out"], + ["self.clk","_U108.clk"], + ["self.in.2","_U108.in"], + ["self.out.2","_U108.out"], + ["self.clk","_U109.clk"], + ["self.in.3","_U109.in"], + ["self.out.3","_U109.out"], + ["self.clk","_U110.clk"], + ["self.in.4","_U110.in"], + ["self.out.4","_U110.out"] ] }, - "array_delay_U141":{ + "array_delay_U115":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U142":{ + "_U116":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U143":{ + "_U117":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U144":{ + "_U118":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U145":{ + "_U119":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U146":{ + "_U120":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U142.clk"], - ["self.in.0","_U142.in"], - ["self.out.0","_U142.out"], - ["self.clk","_U143.clk"], - ["self.in.1","_U143.in"], - ["self.out.1","_U143.out"], - ["self.clk","_U144.clk"], - ["self.in.2","_U144.in"], - ["self.out.2","_U144.out"], - ["self.clk","_U145.clk"], - ["self.in.3","_U145.in"], - ["self.out.3","_U145.out"], - ["self.clk","_U146.clk"], - ["self.in.4","_U146.in"], - ["self.out.4","_U146.out"] + ["self.clk","_U116.clk"], + ["self.in.0","_U116.in"], + ["self.out.0","_U116.out"], + ["self.clk","_U117.clk"], + ["self.in.1","_U117.in"], + ["self.out.1","_U117.out"], + ["self.clk","_U118.clk"], + ["self.in.2","_U118.in"], + ["self.out.2","_U118.out"], + ["self.clk","_U119.clk"], + ["self.in.3","_U119.in"], + ["self.out.3","_U119.out"], + ["self.clk","_U120.clk"], + ["self.in.4","_U120.in"], + ["self.out.4","_U120.out"] ] }, - "array_delay_U29":{ + "array_delay_U150":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",4,["Array",16,"BitIn"]]], ["out",["Array",4,["Array",16,"Bit"]]] ]], "instances":{ - "_U30":{ + "_U151":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U31":{ + "_U152":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U32":{ + "_U153":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U33":{ + "_U154":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U30.clk"], - ["self.in.0","_U30.in"], - ["self.out.0","_U30.out"], - ["self.clk","_U31.clk"], - ["self.in.1","_U31.in"], - ["self.out.1","_U31.out"], - ["self.clk","_U32.clk"], - ["self.in.2","_U32.in"], - ["self.out.2","_U32.out"], - ["self.clk","_U33.clk"], - ["self.in.3","_U33.in"], - ["self.out.3","_U33.out"] + ["self.clk","_U151.clk"], + ["self.in.0","_U151.in"], + ["self.out.0","_U151.out"], + ["self.clk","_U152.clk"], + ["self.in.1","_U152.in"], + ["self.out.1","_U152.out"], + ["self.clk","_U153.clk"], + ["self.in.2","_U153.in"], + ["self.out.2","_U153.out"], + ["self.clk","_U154.clk"], + ["self.in.3","_U154.in"], + ["self.out.3","_U154.out"] ] }, - "array_delay_U317":{ + "array_delay_U159":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["in",["Array",5,["Array",16,"BitIn"]]], - ["out",["Array",5,["Array",16,"Bit"]]] + ["in",["Array",4,["Array",16,"BitIn"]]], + ["out",["Array",4,["Array",16,"Bit"]]] ]], "instances":{ - "_U318":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U319":{ + "_U160":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U320":{ + "_U161":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U321":{ + "_U162":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U322":{ + "_U163":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U318.clk"], - ["self.in.0","_U318.in"], - ["self.out.0","_U318.out"], - ["self.clk","_U319.clk"], - ["self.in.1","_U319.in"], - ["self.out.1","_U319.out"], - ["self.clk","_U320.clk"], - ["self.in.2","_U320.in"], - ["self.out.2","_U320.out"], - ["self.clk","_U321.clk"], - ["self.in.3","_U321.in"], - ["self.out.3","_U321.out"], - ["self.clk","_U322.clk"], - ["self.in.4","_U322.in"], - ["self.out.4","_U322.out"] + ["self.clk","_U160.clk"], + ["self.in.0","_U160.in"], + ["self.out.0","_U160.out"], + ["self.clk","_U161.clk"], + ["self.in.1","_U161.in"], + ["self.out.1","_U161.out"], + ["self.clk","_U162.clk"], + ["self.in.2","_U162.in"], + ["self.out.2","_U162.out"], + ["self.clk","_U163.clk"], + ["self.in.3","_U163.in"], + ["self.out.3","_U163.out"] ] }, - "array_delay_U327":{ + "array_delay_U200":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U328":{ + "_U201":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U329":{ + "_U202":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U330":{ + "_U203":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U331":{ + "_U204":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U332":{ + "_U205":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U328.clk"], - ["self.in.0","_U328.in"], - ["self.out.0","_U328.out"], - ["self.clk","_U329.clk"], - ["self.in.1","_U329.in"], - ["self.out.1","_U329.out"], - ["self.clk","_U330.clk"], - ["self.in.2","_U330.in"], - ["self.out.2","_U330.out"], - ["self.clk","_U331.clk"], - ["self.in.3","_U331.in"], - ["self.out.3","_U331.out"], - ["self.clk","_U332.clk"], - ["self.in.4","_U332.in"], - ["self.out.4","_U332.out"] + ["self.clk","_U201.clk"], + ["self.in.0","_U201.in"], + ["self.out.0","_U201.out"], + ["self.clk","_U202.clk"], + ["self.in.1","_U202.in"], + ["self.out.1","_U202.out"], + ["self.clk","_U203.clk"], + ["self.in.2","_U203.in"], + ["self.out.2","_U203.out"], + ["self.clk","_U204.clk"], + ["self.in.3","_U204.in"], + ["self.out.3","_U204.out"], + ["self.clk","_U205.clk"], + ["self.in.4","_U205.in"], + ["self.out.4","_U205.out"] ] }, - "array_delay_U38":{ + "array_delay_U210":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["in",["Array",4,["Array",16,"BitIn"]]], - ["out",["Array",4,["Array",16,"Bit"]]] + ["in",["Array",5,["Array",16,"BitIn"]]], + ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U39":{ + "_U211":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U212":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U40":{ + "_U213":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U41":{ + "_U214":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U42":{ + "_U215":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U39.clk"], - ["self.in.0","_U39.in"], - ["self.out.0","_U39.out"], - ["self.clk","_U40.clk"], - ["self.in.1","_U40.in"], - ["self.out.1","_U40.out"], - ["self.clk","_U41.clk"], - ["self.in.2","_U41.in"], - ["self.out.2","_U41.out"], - ["self.clk","_U42.clk"], - ["self.in.3","_U42.in"], - ["self.out.3","_U42.out"] + ["self.clk","_U211.clk"], + ["self.in.0","_U211.in"], + ["self.out.0","_U211.out"], + ["self.clk","_U212.clk"], + ["self.in.1","_U212.in"], + ["self.out.1","_U212.out"], + ["self.clk","_U213.clk"], + ["self.in.2","_U213.in"], + ["self.out.2","_U213.out"], + ["self.clk","_U214.clk"], + ["self.in.3","_U214.in"], + ["self.out.3","_U214.out"], + ["self.clk","_U215.clk"], + ["self.in.4","_U215.in"], + ["self.out.4","_U215.out"] ] }, - "array_delay_U79":{ + "array_delay_U252":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U80":{ + "_U253":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U81":{ + "_U254":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U82":{ + "_U255":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U83":{ + "_U256":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U84":{ + "_U257":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U80.clk"], - ["self.in.0","_U80.in"], - ["self.out.0","_U80.out"], - ["self.clk","_U81.clk"], - ["self.in.1","_U81.in"], - ["self.out.1","_U81.out"], - ["self.clk","_U82.clk"], - ["self.in.2","_U82.in"], - ["self.out.2","_U82.out"], - ["self.clk","_U83.clk"], - ["self.in.3","_U83.in"], - ["self.out.3","_U83.out"], - ["self.clk","_U84.clk"], - ["self.in.4","_U84.in"], - ["self.out.4","_U84.out"] + ["self.clk","_U253.clk"], + ["self.in.0","_U253.in"], + ["self.out.0","_U253.out"], + ["self.clk","_U254.clk"], + ["self.in.1","_U254.in"], + ["self.out.1","_U254.out"], + ["self.clk","_U255.clk"], + ["self.in.2","_U255.in"], + ["self.out.2","_U255.out"], + ["self.clk","_U256.clk"], + ["self.in.3","_U256.in"], + ["self.out.3","_U256.out"], + ["self.clk","_U257.clk"], + ["self.in.4","_U257.in"], + ["self.out.4","_U257.out"] ] }, - "array_delay_U89":{ + "array_delay_U262":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U90":{ + "_U263":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U91":{ + "_U264":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U92":{ + "_U265":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U93":{ + "_U266":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U94":{ + "_U267":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U90.clk"], - ["self.in.0","_U90.in"], - ["self.out.0","_U90.out"], - ["self.clk","_U91.clk"], - ["self.in.1","_U91.in"], - ["self.out.1","_U91.out"], - ["self.clk","_U92.clk"], - ["self.in.2","_U92.in"], - ["self.out.2","_U92.out"], - ["self.clk","_U93.clk"], - ["self.in.3","_U93.in"], - ["self.out.3","_U93.out"], - ["self.clk","_U94.clk"], - ["self.in.4","_U94.in"], - ["self.out.4","_U94.out"] + ["self.clk","_U263.clk"], + ["self.in.0","_U263.in"], + ["self.out.0","_U263.out"], + ["self.clk","_U264.clk"], + ["self.in.1","_U264.in"], + ["self.out.1","_U264.out"], + ["self.clk","_U265.clk"], + ["self.in.2","_U265.in"], + ["self.out.2","_U265.out"], + ["self.clk","_U266.clk"], + ["self.in.3","_U266.in"], + ["self.out.3","_U266.out"], + ["self.clk","_U267.clk"], + ["self.in.4","_U267.in"], + ["self.out.4","_U267.out"] ] }, "conv_stencil_ub":{ @@ -4326,7 +4326,7 @@ ["op_hcompute_hw_kernel_global_wrapper_stencil_write",["Array",1,["Array",16,"BitIn"]]] ]] }, - "op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U226":{ + "op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U43":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4335,7 +4335,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_exe_start_pt__U225":{ + "op_hcompute_conv_stencil_1_exe_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4344,7 +4344,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_read_start_control_vars_pt__U224":{ + "op_hcompute_conv_stencil_1_read_start_control_vars_pt__U41":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4353,7 +4353,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_read_start_pt__U223":{ + "op_hcompute_conv_stencil_1_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4362,7 +4362,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_write_start_control_vars_pt__U228":{ + "op_hcompute_conv_stencil_1_write_start_control_vars_pt__U45":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4371,7 +4371,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_write_start_pt__U227":{ + "op_hcompute_conv_stencil_1_write_start_pt__U44":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4380,7 +4380,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U203":{ + "op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U66":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4389,7 +4389,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_exe_start_pt__U202":{ + "op_hcompute_conv_stencil_2_exe_start_pt__U65":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4398,7 +4398,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_read_start_control_vars_pt__U201":{ + "op_hcompute_conv_stencil_2_read_start_control_vars_pt__U64":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4407,7 +4407,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_read_start_pt__U200":{ + "op_hcompute_conv_stencil_2_read_start_pt__U63":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4416,7 +4416,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_write_start_control_vars_pt__U205":{ + "op_hcompute_conv_stencil_2_write_start_control_vars_pt__U68":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4425,7 +4425,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_write_start_pt__U204":{ + "op_hcompute_conv_stencil_2_write_start_pt__U67":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4434,7 +4434,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U315":{ + "op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U103":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4443,7 +4443,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_exe_start_pt__U313":{ + "op_hcompute_conv_stencil_3_exe_start_pt__U101":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4452,7 +4452,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_read_start_control_vars_pt__U312":{ + "op_hcompute_conv_stencil_3_read_start_control_vars_pt__U100":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4461,7 +4461,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_read_start_pt__U311":{ + "op_hcompute_conv_stencil_3_read_start_pt__U99":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4470,7 +4470,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_write_start_control_vars_pt__U325":{ + "op_hcompute_conv_stencil_3_write_start_control_vars_pt__U113":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4479,7 +4479,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_write_start_pt__U323":{ + "op_hcompute_conv_stencil_3_write_start_pt__U111":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4488,7 +4488,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U77":{ + "op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U250":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4497,7 +4497,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_exe_start_pt__U75":{ + "op_hcompute_conv_stencil_4_exe_start_pt__U248":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4506,7 +4506,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_read_start_control_vars_pt__U74":{ + "op_hcompute_conv_stencil_4_read_start_control_vars_pt__U247":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4515,7 +4515,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_read_start_pt__U73":{ + "op_hcompute_conv_stencil_4_read_start_pt__U246":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4524,7 +4524,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_write_start_control_vars_pt__U87":{ + "op_hcompute_conv_stencil_4_write_start_control_vars_pt__U260":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4533,7 +4533,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_write_start_pt__U85":{ + "op_hcompute_conv_stencil_4_write_start_pt__U258":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4542,7 +4542,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U129":{ + "op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U198":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4551,7 +4551,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_exe_start_pt__U127":{ + "op_hcompute_conv_stencil_5_exe_start_pt__U196":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4560,7 +4560,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_read_start_control_vars_pt__U126":{ + "op_hcompute_conv_stencil_5_read_start_control_vars_pt__U195":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4569,7 +4569,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_read_start_pt__U125":{ + "op_hcompute_conv_stencil_5_read_start_pt__U194":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4578,7 +4578,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_write_start_control_vars_pt__U139":{ + "op_hcompute_conv_stencil_5_write_start_control_vars_pt__U208":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4587,7 +4587,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_write_start_pt__U137":{ + "op_hcompute_conv_stencil_5_write_start_pt__U206":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4596,7 +4596,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_exe_start_control_vars_pt__U249":{ + "op_hcompute_conv_stencil_exe_start_control_vars_pt__U20":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4605,7 +4605,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_exe_start_pt__U248":{ + "op_hcompute_conv_stencil_exe_start_pt__U19":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4614,7 +4614,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_read_start_control_vars_pt__U247":{ + "op_hcompute_conv_stencil_read_start_control_vars_pt__U18":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4623,7 +4623,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_read_start_pt__U246":{ + "op_hcompute_conv_stencil_read_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4632,7 +4632,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_write_start_control_vars_pt__U251":{ + "op_hcompute_conv_stencil_write_start_control_vars_pt__U22":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -4641,7 +4641,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_write_start_pt__U250":{ + "op_hcompute_conv_stencil_write_start_pt__U21":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4650,7 +4650,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U278":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U330":{ "type":["Record",[ ["in",["Array",4,["Array",16,"BitIn"]]], ["out",["Array",4,["Array",16,"Bit"]]] @@ -4659,7 +4659,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U277":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U329":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4668,7 +4668,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U276":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U328":{ "type":["Record",[ ["in",["Array",4,["Array",16,"BitIn"]]], ["out",["Array",4,["Array",16,"Bit"]]] @@ -4677,7 +4677,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U275":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U327":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4686,7 +4686,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U280":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U332":{ "type":["Record",[ ["in",["Array",4,["Array",16,"BitIn"]]], ["out",["Array",4,["Array",16,"Bit"]]] @@ -4695,7 +4695,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U279":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U331":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4704,7 +4704,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U180":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U301":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4713,7 +4713,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U179":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U300":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4722,7 +4722,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U178":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U299":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4731,7 +4731,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U177":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U298":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4740,7 +4740,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U182":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U303":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -4749,7 +4749,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U181":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U302":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4758,7 +4758,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U27":{ + "op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U148":{ "type":["Record",[ ["in",["Array",4,["Array",16,"BitIn"]]], ["out",["Array",4,["Array",16,"Bit"]]] @@ -4767,7 +4767,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_exe_start_pt__U25":{ + "op_hcompute_hw_output_stencil_exe_start_pt__U146":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4776,7 +4776,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U24":{ + "op_hcompute_hw_output_stencil_read_start_control_vars_pt__U145":{ "type":["Record",[ ["in",["Array",4,["Array",16,"BitIn"]]], ["out",["Array",4,["Array",16,"Bit"]]] @@ -4785,7 +4785,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_read_start_pt__U23":{ + "op_hcompute_hw_output_stencil_read_start_pt__U144":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4794,7 +4794,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U36":{ + "op_hcompute_hw_output_stencil_write_start_control_vars_pt__U157":{ "type":["Record",[ ["in",["Array",4,["Array",16,"BitIn"]]], ["out",["Array",4,["Array",16,"Bit"]]] @@ -4803,7 +4803,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_output_stencil_write_start_pt__U34":{ + "op_hcompute_hw_output_stencil_write_start_pt__U155":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -4825,62 +4825,62 @@ ["hw_output_stencil_op_hcompute_hw_output_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ - "arr__U130":{ - "modref":"global.array_delay_U131" + "arr__U104":{ + "modref":"global.array_delay_U105" }, - "arr__U140":{ - "modref":"global.array_delay_U141" + "arr__U114":{ + "modref":"global.array_delay_U115" }, - "arr__U28":{ - "modref":"global.array_delay_U29" + "arr__U149":{ + "modref":"global.array_delay_U150" }, - "arr__U316":{ - "modref":"global.array_delay_U317" + "arr__U158":{ + "modref":"global.array_delay_U159" }, - "arr__U326":{ - "modref":"global.array_delay_U327" + "arr__U199":{ + "modref":"global.array_delay_U200" }, - "arr__U37":{ - "modref":"global.array_delay_U38" + "arr__U209":{ + "modref":"global.array_delay_U210" }, - "arr__U78":{ - "modref":"global.array_delay_U79" + "arr__U251":{ + "modref":"global.array_delay_U252" }, - "arr__U88":{ - "modref":"global.array_delay_U89" + "arr__U261":{ + "modref":"global.array_delay_U262" }, "conv_stencil":{ "modref":"global.conv_stencil_ub" }, - "delay_reg__U128":{ + "delay_reg__U102":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U138":{ + "delay_reg__U112":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U26":{ + "delay_reg__U147":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U314":{ + "delay_reg__U156":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U324":{ + "delay_reg__U197":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U35":{ + "delay_reg__U207":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U76":{ + "delay_reg__U249":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U86":{ + "delay_reg__U259":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, @@ -4897,241 +4897,241 @@ "modref":"global.cu_op_hcompute_conv_stencil_1" }, "op_hcompute_conv_stencil_1_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_1_exe_start_pt__U225" + "modref":"global.op_hcompute_conv_stencil_1_exe_start_pt__U42" }, "op_hcompute_conv_stencil_1_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U226" + "modref":"global.op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U43" }, "op_hcompute_conv_stencil_1_port_controller":{ - "modref":"global.affine_controller__U206" + "modref":"global.affine_controller__U23" }, "op_hcompute_conv_stencil_1_read_start":{ - "modref":"global.op_hcompute_conv_stencil_1_read_start_pt__U223" + "modref":"global.op_hcompute_conv_stencil_1_read_start_pt__U40" }, "op_hcompute_conv_stencil_1_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_1_read_start_control_vars_pt__U224" + "modref":"global.op_hcompute_conv_stencil_1_read_start_control_vars_pt__U41" }, "op_hcompute_conv_stencil_1_write_start":{ - "modref":"global.op_hcompute_conv_stencil_1_write_start_pt__U227" + "modref":"global.op_hcompute_conv_stencil_1_write_start_pt__U44" }, "op_hcompute_conv_stencil_1_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_1_write_start_control_vars_pt__U228" + "modref":"global.op_hcompute_conv_stencil_1_write_start_control_vars_pt__U45" }, "op_hcompute_conv_stencil_2":{ "modref":"global.cu_op_hcompute_conv_stencil_2" }, "op_hcompute_conv_stencil_2_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_2_exe_start_pt__U202" + "modref":"global.op_hcompute_conv_stencil_2_exe_start_pt__U65" }, "op_hcompute_conv_stencil_2_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U203" + "modref":"global.op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U66" }, "op_hcompute_conv_stencil_2_port_controller":{ - "modref":"global.affine_controller__U183" + "modref":"global.affine_controller__U46" }, "op_hcompute_conv_stencil_2_read_start":{ - "modref":"global.op_hcompute_conv_stencil_2_read_start_pt__U200" + "modref":"global.op_hcompute_conv_stencil_2_read_start_pt__U63" }, "op_hcompute_conv_stencil_2_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_2_read_start_control_vars_pt__U201" + "modref":"global.op_hcompute_conv_stencil_2_read_start_control_vars_pt__U64" }, "op_hcompute_conv_stencil_2_write_start":{ - "modref":"global.op_hcompute_conv_stencil_2_write_start_pt__U204" + "modref":"global.op_hcompute_conv_stencil_2_write_start_pt__U67" }, "op_hcompute_conv_stencil_2_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_2_write_start_control_vars_pt__U205" + "modref":"global.op_hcompute_conv_stencil_2_write_start_control_vars_pt__U68" }, "op_hcompute_conv_stencil_3":{ "modref":"global.cu_op_hcompute_conv_stencil_3" }, "op_hcompute_conv_stencil_3_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_3_exe_start_pt__U313" + "modref":"global.op_hcompute_conv_stencil_3_exe_start_pt__U101" }, "op_hcompute_conv_stencil_3_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U315" + "modref":"global.op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U103" }, "op_hcompute_conv_stencil_3_port_controller":{ - "modref":"global.affine_controller__U281" + "modref":"global.affine_controller__U69" }, "op_hcompute_conv_stencil_3_read_start":{ - "modref":"global.op_hcompute_conv_stencil_3_read_start_pt__U311" + "modref":"global.op_hcompute_conv_stencil_3_read_start_pt__U99" }, "op_hcompute_conv_stencil_3_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_3_read_start_control_vars_pt__U312" + "modref":"global.op_hcompute_conv_stencil_3_read_start_control_vars_pt__U100" }, "op_hcompute_conv_stencil_3_write_start":{ - "modref":"global.op_hcompute_conv_stencil_3_write_start_pt__U323" + "modref":"global.op_hcompute_conv_stencil_3_write_start_pt__U111" }, "op_hcompute_conv_stencil_3_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_3_write_start_control_vars_pt__U325" + "modref":"global.op_hcompute_conv_stencil_3_write_start_control_vars_pt__U113" }, "op_hcompute_conv_stencil_4":{ "modref":"global.cu_op_hcompute_conv_stencil_4" }, "op_hcompute_conv_stencil_4_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_4_exe_start_pt__U75" + "modref":"global.op_hcompute_conv_stencil_4_exe_start_pt__U248" }, "op_hcompute_conv_stencil_4_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U77" + "modref":"global.op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U250" }, "op_hcompute_conv_stencil_4_port_controller":{ - "modref":"global.affine_controller__U43" + "modref":"global.affine_controller__U216" }, "op_hcompute_conv_stencil_4_read_start":{ - "modref":"global.op_hcompute_conv_stencil_4_read_start_pt__U73" + "modref":"global.op_hcompute_conv_stencil_4_read_start_pt__U246" }, "op_hcompute_conv_stencil_4_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_4_read_start_control_vars_pt__U74" + "modref":"global.op_hcompute_conv_stencil_4_read_start_control_vars_pt__U247" }, "op_hcompute_conv_stencil_4_write_start":{ - "modref":"global.op_hcompute_conv_stencil_4_write_start_pt__U85" + "modref":"global.op_hcompute_conv_stencil_4_write_start_pt__U258" }, "op_hcompute_conv_stencil_4_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_4_write_start_control_vars_pt__U87" + "modref":"global.op_hcompute_conv_stencil_4_write_start_control_vars_pt__U260" }, "op_hcompute_conv_stencil_5":{ "modref":"global.cu_op_hcompute_conv_stencil_5" }, "op_hcompute_conv_stencil_5_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_5_exe_start_pt__U127" + "modref":"global.op_hcompute_conv_stencil_5_exe_start_pt__U196" }, "op_hcompute_conv_stencil_5_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U129" + "modref":"global.op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U198" }, "op_hcompute_conv_stencil_5_port_controller":{ - "modref":"global.affine_controller__U95" + "modref":"global.affine_controller__U164" }, "op_hcompute_conv_stencil_5_read_start":{ - "modref":"global.op_hcompute_conv_stencil_5_read_start_pt__U125" + "modref":"global.op_hcompute_conv_stencil_5_read_start_pt__U194" }, "op_hcompute_conv_stencil_5_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_5_read_start_control_vars_pt__U126" + "modref":"global.op_hcompute_conv_stencil_5_read_start_control_vars_pt__U195" }, "op_hcompute_conv_stencil_5_write_start":{ - "modref":"global.op_hcompute_conv_stencil_5_write_start_pt__U137" + "modref":"global.op_hcompute_conv_stencil_5_write_start_pt__U206" }, "op_hcompute_conv_stencil_5_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_5_write_start_control_vars_pt__U139" + "modref":"global.op_hcompute_conv_stencil_5_write_start_control_vars_pt__U208" }, "op_hcompute_conv_stencil_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_exe_start_pt__U248" + "modref":"global.op_hcompute_conv_stencil_exe_start_pt__U19" }, "op_hcompute_conv_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_exe_start_control_vars_pt__U249" + "modref":"global.op_hcompute_conv_stencil_exe_start_control_vars_pt__U20" }, "op_hcompute_conv_stencil_port_controller":{ - "modref":"global.affine_controller__U229" + "modref":"global.affine_controller__U0" }, "op_hcompute_conv_stencil_read_start":{ - "modref":"global.op_hcompute_conv_stencil_read_start_pt__U246" + "modref":"global.op_hcompute_conv_stencil_read_start_pt__U17" }, "op_hcompute_conv_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_read_start_control_vars_pt__U247" + "modref":"global.op_hcompute_conv_stencil_read_start_control_vars_pt__U18" }, "op_hcompute_conv_stencil_write_start":{ - "modref":"global.op_hcompute_conv_stencil_write_start_pt__U250" + "modref":"global.op_hcompute_conv_stencil_write_start_pt__U21" }, "op_hcompute_conv_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_write_start_control_vars_pt__U251" + "modref":"global.op_hcompute_conv_stencil_write_start_control_vars_pt__U22" }, "op_hcompute_hw_input_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U277" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U329" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U278" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U330" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ - "modref":"global.affine_controller__U252" + "modref":"global.affine_controller__U304" }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U275" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U327" }, "op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U276" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U328" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U279" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U331" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U280" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U332" }, "op_hcompute_hw_kernel_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_kernel_global_wrapper_stencil" }, "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U179" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U300" }, "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U180" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U301" }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller":{ - "modref":"global.affine_controller__U147" + "modref":"global.affine_controller__U268" }, "op_hcompute_hw_kernel_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U177" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U298" }, "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U178" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U299" }, "op_hcompute_hw_kernel_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U181" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U302" }, "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U182" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U303" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" }, "op_hcompute_hw_output_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U25" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_pt__U146" }, "op_hcompute_hw_output_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U27" + "modref":"global.op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U148" }, "op_hcompute_hw_output_stencil_port_controller":{ - "modref":"global.affine_controller__U0" + "modref":"global.affine_controller__U121" }, "op_hcompute_hw_output_stencil_read_start":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U23" + "modref":"global.op_hcompute_hw_output_stencil_read_start_pt__U144" }, "op_hcompute_hw_output_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U24" + "modref":"global.op_hcompute_hw_output_stencil_read_start_control_vars_pt__U145" }, "op_hcompute_hw_output_stencil_write_start":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U34" + "modref":"global.op_hcompute_hw_output_stencil_write_start_pt__U155" }, "op_hcompute_hw_output_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U36" + "modref":"global.op_hcompute_hw_output_stencil_write_start_control_vars_pt__U157" } }, "connections":[ - ["self.clk","arr__U130.clk"], - ["op_hcompute_conv_stencil_5_port_controller.d","arr__U130.in"], - ["op_hcompute_conv_stencil_5_exe_start_control_vars.in","arr__U130.out"], - ["self.clk","arr__U140.clk"], - ["op_hcompute_conv_stencil_5_port_controller.d","arr__U140.in"], - ["op_hcompute_conv_stencil_5_write_start_control_vars.in","arr__U140.out"], - ["self.clk","arr__U28.clk"], - ["op_hcompute_hw_output_stencil_port_controller.d","arr__U28.in"], - ["op_hcompute_hw_output_stencil_exe_start_control_vars.in","arr__U28.out"], - ["self.clk","arr__U316.clk"], - ["op_hcompute_conv_stencil_3_port_controller.d","arr__U316.in"], - ["op_hcompute_conv_stencil_3_exe_start_control_vars.in","arr__U316.out"], - ["self.clk","arr__U326.clk"], - ["op_hcompute_conv_stencil_3_port_controller.d","arr__U326.in"], - ["op_hcompute_conv_stencil_3_write_start_control_vars.in","arr__U326.out"], - ["self.clk","arr__U37.clk"], - ["op_hcompute_hw_output_stencil_port_controller.d","arr__U37.in"], - ["op_hcompute_hw_output_stencil_write_start_control_vars.in","arr__U37.out"], - ["self.clk","arr__U78.clk"], - ["op_hcompute_conv_stencil_4_port_controller.d","arr__U78.in"], - ["op_hcompute_conv_stencil_4_exe_start_control_vars.in","arr__U78.out"], - ["self.clk","arr__U88.clk"], - ["op_hcompute_conv_stencil_4_port_controller.d","arr__U88.in"], - ["op_hcompute_conv_stencil_4_write_start_control_vars.in","arr__U88.out"], + ["self.clk","arr__U104.clk"], + ["op_hcompute_conv_stencil_3_port_controller.d","arr__U104.in"], + ["op_hcompute_conv_stencil_3_exe_start_control_vars.in","arr__U104.out"], + ["self.clk","arr__U114.clk"], + ["op_hcompute_conv_stencil_3_port_controller.d","arr__U114.in"], + ["op_hcompute_conv_stencil_3_write_start_control_vars.in","arr__U114.out"], + ["self.clk","arr__U149.clk"], + ["op_hcompute_hw_output_stencil_port_controller.d","arr__U149.in"], + ["op_hcompute_hw_output_stencil_exe_start_control_vars.in","arr__U149.out"], + ["self.clk","arr__U158.clk"], + ["op_hcompute_hw_output_stencil_port_controller.d","arr__U158.in"], + ["op_hcompute_hw_output_stencil_write_start_control_vars.in","arr__U158.out"], + ["self.clk","arr__U199.clk"], + ["op_hcompute_conv_stencil_5_port_controller.d","arr__U199.in"], + ["op_hcompute_conv_stencil_5_exe_start_control_vars.in","arr__U199.out"], + ["self.clk","arr__U209.clk"], + ["op_hcompute_conv_stencil_5_port_controller.d","arr__U209.in"], + ["op_hcompute_conv_stencil_5_write_start_control_vars.in","arr__U209.out"], + ["self.clk","arr__U251.clk"], + ["op_hcompute_conv_stencil_4_port_controller.d","arr__U251.in"], + ["op_hcompute_conv_stencil_4_exe_start_control_vars.in","arr__U251.out"], + ["self.clk","arr__U261.clk"], + ["op_hcompute_conv_stencil_4_port_controller.d","arr__U261.in"], + ["op_hcompute_conv_stencil_4_write_start_control_vars.in","arr__U261.out"], ["self.clk","conv_stencil.clk"], ["self.flush","conv_stencil.flush"], ["op_hcompute_conv_stencil_1.conv_stencil_op_hcompute_conv_stencil_1_write","conv_stencil.op_hcompute_conv_stencil_1_write"], @@ -5165,30 +5165,30 @@ ["op_hcompute_hw_output_stencil_port_controller.d","conv_stencil.op_hcompute_hw_output_stencil_read_ctrl_vars"], ["op_hcompute_hw_output_stencil_read_start.out","conv_stencil.op_hcompute_hw_output_stencil_read_ren"], ["self.rst_n","conv_stencil.rst_n"], - ["self.clk","delay_reg__U128.clk"], - ["op_hcompute_conv_stencil_5_port_controller.valid","delay_reg__U128.in"], - ["op_hcompute_conv_stencil_5_exe_start.in","delay_reg__U128.out"], - ["self.clk","delay_reg__U138.clk"], - ["op_hcompute_conv_stencil_5_port_controller.valid","delay_reg__U138.in"], - ["op_hcompute_conv_stencil_5_write_start.in","delay_reg__U138.out"], - ["self.clk","delay_reg__U26.clk"], - ["op_hcompute_hw_output_stencil_port_controller.valid","delay_reg__U26.in"], - ["op_hcompute_hw_output_stencil_exe_start.in","delay_reg__U26.out"], - ["self.clk","delay_reg__U314.clk"], - ["op_hcompute_conv_stencil_3_port_controller.valid","delay_reg__U314.in"], - ["op_hcompute_conv_stencil_3_exe_start.in","delay_reg__U314.out"], - ["self.clk","delay_reg__U324.clk"], - ["op_hcompute_conv_stencil_3_port_controller.valid","delay_reg__U324.in"], - ["op_hcompute_conv_stencil_3_write_start.in","delay_reg__U324.out"], - ["self.clk","delay_reg__U35.clk"], - ["op_hcompute_hw_output_stencil_port_controller.valid","delay_reg__U35.in"], - ["op_hcompute_hw_output_stencil_write_start.in","delay_reg__U35.out"], - ["self.clk","delay_reg__U76.clk"], - ["op_hcompute_conv_stencil_4_port_controller.valid","delay_reg__U76.in"], - ["op_hcompute_conv_stencil_4_exe_start.in","delay_reg__U76.out"], - ["self.clk","delay_reg__U86.clk"], - ["op_hcompute_conv_stencil_4_port_controller.valid","delay_reg__U86.in"], - ["op_hcompute_conv_stencil_4_write_start.in","delay_reg__U86.out"], + ["self.clk","delay_reg__U102.clk"], + ["op_hcompute_conv_stencil_3_port_controller.valid","delay_reg__U102.in"], + ["op_hcompute_conv_stencil_3_exe_start.in","delay_reg__U102.out"], + ["self.clk","delay_reg__U112.clk"], + ["op_hcompute_conv_stencil_3_port_controller.valid","delay_reg__U112.in"], + ["op_hcompute_conv_stencil_3_write_start.in","delay_reg__U112.out"], + ["self.clk","delay_reg__U147.clk"], + ["op_hcompute_hw_output_stencil_port_controller.valid","delay_reg__U147.in"], + ["op_hcompute_hw_output_stencil_exe_start.in","delay_reg__U147.out"], + ["self.clk","delay_reg__U156.clk"], + ["op_hcompute_hw_output_stencil_port_controller.valid","delay_reg__U156.in"], + ["op_hcompute_hw_output_stencil_write_start.in","delay_reg__U156.out"], + ["self.clk","delay_reg__U197.clk"], + ["op_hcompute_conv_stencil_5_port_controller.valid","delay_reg__U197.in"], + ["op_hcompute_conv_stencil_5_exe_start.in","delay_reg__U197.out"], + ["self.clk","delay_reg__U207.clk"], + ["op_hcompute_conv_stencil_5_port_controller.valid","delay_reg__U207.in"], + ["op_hcompute_conv_stencil_5_write_start.in","delay_reg__U207.out"], + ["self.clk","delay_reg__U249.clk"], + ["op_hcompute_conv_stencil_4_port_controller.valid","delay_reg__U249.in"], + ["op_hcompute_conv_stencil_4_exe_start.in","delay_reg__U249.out"], + ["self.clk","delay_reg__U259.clk"], + ["op_hcompute_conv_stencil_4_port_controller.valid","delay_reg__U259.in"], + ["op_hcompute_conv_stencil_4_write_start.in","delay_reg__U259.out"], ["self.clk","hw_input_global_wrapper_stencil.clk"], ["self.flush","hw_input_global_wrapper_stencil.flush"], ["op_hcompute_conv_stencil_3.hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_read","hw_input_global_wrapper_stencil.op_hcompute_conv_stencil_3_read"], diff --git a/coreir_apps/platonic_buffer/resnet/resnet.v b/coreir_apps/platonic_buffer/resnet/resnet.v index e054624fa..dac3a8308 100644 --- a/coreir_apps/platonic_buffer/resnet/resnet.v +++ b/coreir_apps/platonic_buffer/resnet/resnet.v @@ -1,14 +1,14 @@ // Module `hw_kernel_global_wrapper_stencil_ub` defined externally // Module `hw_input_global_wrapper_stencil_ub` defined externally // Module `conv_stencil_ub` defined externally -module op_hcompute_hw_output_stencil_write_start_pt__U34 ( +module op_hcompute_hw_output_stencil_write_start_pt__U155 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_output_stencil_write_start_control_vars_pt__U36 ( +module op_hcompute_hw_output_stencil_write_start_control_vars_pt__U157 ( input [15:0] in [3:0], output [15:0] out [3:0] ); @@ -18,14 +18,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_output_stencil_read_start_pt__U23 ( +module op_hcompute_hw_output_stencil_read_start_pt__U144 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_output_stencil_read_start_control_vars_pt__U24 ( +module op_hcompute_hw_output_stencil_read_start_control_vars_pt__U145 ( input [15:0] in [3:0], output [15:0] out [3:0] ); @@ -35,14 +35,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_output_stencil_exe_start_pt__U25 ( +module op_hcompute_hw_output_stencil_exe_start_pt__U146 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U27 ( +module op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U148 ( input [15:0] in [3:0], output [15:0] out [3:0] ); @@ -52,14 +52,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U181 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U302 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U182 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U303 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -70,14 +70,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U177 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U298 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U178 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U299 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -88,14 +88,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U179 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U300 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U180 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U301 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -106,14 +106,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U279 ( +module op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U331 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U280 ( +module op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U332 ( input [15:0] in [3:0], output [15:0] out [3:0] ); @@ -123,14 +123,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U275 ( +module op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U327 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U276 ( +module op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U328 ( input [15:0] in [3:0], output [15:0] out [3:0] ); @@ -140,14 +140,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U277 ( +module op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U329 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U278 ( +module op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U330 ( input [15:0] in [3:0], output [15:0] out [3:0] ); @@ -157,14 +157,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_write_start_pt__U250 ( +module op_hcompute_conv_stencil_write_start_pt__U21 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_write_start_control_vars_pt__U251 ( +module op_hcompute_conv_stencil_write_start_control_vars_pt__U22 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -173,14 +173,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_read_start_pt__U246 ( +module op_hcompute_conv_stencil_read_start_pt__U17 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_read_start_control_vars_pt__U247 ( +module op_hcompute_conv_stencil_read_start_control_vars_pt__U18 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -189,14 +189,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_exe_start_pt__U248 ( +module op_hcompute_conv_stencil_exe_start_pt__U19 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_exe_start_control_vars_pt__U249 ( +module op_hcompute_conv_stencil_exe_start_control_vars_pt__U20 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -205,14 +205,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_5_write_start_pt__U137 ( +module op_hcompute_conv_stencil_5_write_start_pt__U206 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_5_write_start_control_vars_pt__U139 ( +module op_hcompute_conv_stencil_5_write_start_control_vars_pt__U208 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -223,14 +223,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_5_read_start_pt__U125 ( +module op_hcompute_conv_stencil_5_read_start_pt__U194 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_5_read_start_control_vars_pt__U126 ( +module op_hcompute_conv_stencil_5_read_start_control_vars_pt__U195 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -241,14 +241,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_5_exe_start_pt__U127 ( +module op_hcompute_conv_stencil_5_exe_start_pt__U196 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U129 ( +module op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U198 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -259,14 +259,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_4_write_start_pt__U85 ( +module op_hcompute_conv_stencil_4_write_start_pt__U258 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_4_write_start_control_vars_pt__U87 ( +module op_hcompute_conv_stencil_4_write_start_control_vars_pt__U260 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -277,14 +277,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_4_read_start_pt__U73 ( +module op_hcompute_conv_stencil_4_read_start_pt__U246 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_4_read_start_control_vars_pt__U74 ( +module op_hcompute_conv_stencil_4_read_start_control_vars_pt__U247 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -295,14 +295,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_4_exe_start_pt__U75 ( +module op_hcompute_conv_stencil_4_exe_start_pt__U248 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U77 ( +module op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U250 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -313,14 +313,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_3_write_start_pt__U323 ( +module op_hcompute_conv_stencil_3_write_start_pt__U111 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_3_write_start_control_vars_pt__U325 ( +module op_hcompute_conv_stencil_3_write_start_control_vars_pt__U113 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -331,14 +331,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_3_read_start_pt__U311 ( +module op_hcompute_conv_stencil_3_read_start_pt__U99 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_3_read_start_control_vars_pt__U312 ( +module op_hcompute_conv_stencil_3_read_start_control_vars_pt__U100 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -349,14 +349,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_3_exe_start_pt__U313 ( +module op_hcompute_conv_stencil_3_exe_start_pt__U101 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U315 ( +module op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U103 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -367,14 +367,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_2_write_start_pt__U204 ( +module op_hcompute_conv_stencil_2_write_start_pt__U67 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_2_write_start_control_vars_pt__U205 ( +module op_hcompute_conv_stencil_2_write_start_control_vars_pt__U68 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -383,14 +383,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_2_read_start_pt__U200 ( +module op_hcompute_conv_stencil_2_read_start_pt__U63 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_2_read_start_control_vars_pt__U201 ( +module op_hcompute_conv_stencil_2_read_start_control_vars_pt__U64 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -399,14 +399,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_2_exe_start_pt__U202 ( +module op_hcompute_conv_stencil_2_exe_start_pt__U65 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U203 ( +module op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U66 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -415,14 +415,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_1_write_start_pt__U227 ( +module op_hcompute_conv_stencil_1_write_start_pt__U44 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_1_write_start_control_vars_pt__U228 ( +module op_hcompute_conv_stencil_1_write_start_control_vars_pt__U45 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -431,14 +431,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_1_read_start_pt__U223 ( +module op_hcompute_conv_stencil_1_read_start_pt__U40 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_1_read_start_control_vars_pt__U224 ( +module op_hcompute_conv_stencil_1_read_start_control_vars_pt__U41 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -447,14 +447,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_1_exe_start_pt__U225 ( +module op_hcompute_conv_stencil_1_exe_start_pt__U42 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U226 ( +module op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U43 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -790,412 +790,412 @@ end assign out = outReg; endmodule -module array_delay_U89 ( +module array_delay_U262 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U90_out; -wire [15:0] _U91_out; -wire [15:0] _U92_out; -wire [15:0] _U93_out; -wire [15:0] _U94_out; +wire [15:0] _U263_out; +wire [15:0] _U264_out; +wire [15:0] _U265_out; +wire [15:0] _U266_out; +wire [15:0] _U267_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U90 ( +) _U263 ( .in(in[0]), .clk(clk), - .out(_U90_out) + .out(_U263_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U91 ( +) _U264 ( .in(in[1]), .clk(clk), - .out(_U91_out) + .out(_U264_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U92 ( +) _U265 ( .in(in[2]), .clk(clk), - .out(_U92_out) + .out(_U265_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U93 ( +) _U266 ( .in(in[3]), .clk(clk), - .out(_U93_out) + .out(_U266_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U94 ( +) _U267 ( .in(in[4]), .clk(clk), - .out(_U94_out) + .out(_U267_out) ); -assign out[4] = _U94_out; -assign out[3] = _U93_out; -assign out[2] = _U92_out; -assign out[1] = _U91_out; -assign out[0] = _U90_out; +assign out[4] = _U267_out; +assign out[3] = _U266_out; +assign out[2] = _U265_out; +assign out[1] = _U264_out; +assign out[0] = _U263_out; endmodule -module array_delay_U79 ( +module array_delay_U252 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U80_out; -wire [15:0] _U81_out; -wire [15:0] _U82_out; -wire [15:0] _U83_out; -wire [15:0] _U84_out; +wire [15:0] _U253_out; +wire [15:0] _U254_out; +wire [15:0] _U255_out; +wire [15:0] _U256_out; +wire [15:0] _U257_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U80 ( +) _U253 ( .in(in[0]), .clk(clk), - .out(_U80_out) + .out(_U253_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U81 ( +) _U254 ( .in(in[1]), .clk(clk), - .out(_U81_out) + .out(_U254_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U82 ( +) _U255 ( .in(in[2]), .clk(clk), - .out(_U82_out) + .out(_U255_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U83 ( +) _U256 ( .in(in[3]), .clk(clk), - .out(_U83_out) + .out(_U256_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U84 ( +) _U257 ( .in(in[4]), .clk(clk), - .out(_U84_out) + .out(_U257_out) ); -assign out[4] = _U84_out; -assign out[3] = _U83_out; -assign out[2] = _U82_out; -assign out[1] = _U81_out; -assign out[0] = _U80_out; +assign out[4] = _U257_out; +assign out[3] = _U256_out; +assign out[2] = _U255_out; +assign out[1] = _U254_out; +assign out[0] = _U253_out; endmodule -module array_delay_U38 ( +module array_delay_U210 ( input clk, - input [15:0] in [3:0], - output [15:0] out [3:0] + input [15:0] in [4:0], + output [15:0] out [4:0] ); -wire [15:0] _U39_out; -wire [15:0] _U40_out; -wire [15:0] _U41_out; -wire [15:0] _U42_out; +wire [15:0] _U211_out; +wire [15:0] _U212_out; +wire [15:0] _U213_out; +wire [15:0] _U214_out; +wire [15:0] _U215_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U39 ( +) _U211 ( .in(in[0]), .clk(clk), - .out(_U39_out) + .out(_U211_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U40 ( +) _U212 ( .in(in[1]), .clk(clk), - .out(_U40_out) + .out(_U212_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U41 ( +) _U213 ( .in(in[2]), .clk(clk), - .out(_U41_out) + .out(_U213_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U42 ( +) _U214 ( .in(in[3]), .clk(clk), - .out(_U42_out) + .out(_U214_out) +); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U215 ( + .in(in[4]), + .clk(clk), + .out(_U215_out) ); -assign out[3] = _U42_out; -assign out[2] = _U41_out; -assign out[1] = _U40_out; -assign out[0] = _U39_out; +assign out[4] = _U215_out; +assign out[3] = _U214_out; +assign out[2] = _U213_out; +assign out[1] = _U212_out; +assign out[0] = _U211_out; endmodule -module array_delay_U327 ( +module array_delay_U200 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U328_out; -wire [15:0] _U329_out; -wire [15:0] _U330_out; -wire [15:0] _U331_out; -wire [15:0] _U332_out; +wire [15:0] _U201_out; +wire [15:0] _U202_out; +wire [15:0] _U203_out; +wire [15:0] _U204_out; +wire [15:0] _U205_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U328 ( +) _U201 ( .in(in[0]), .clk(clk), - .out(_U328_out) + .out(_U201_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U329 ( +) _U202 ( .in(in[1]), .clk(clk), - .out(_U329_out) + .out(_U202_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U330 ( +) _U203 ( .in(in[2]), .clk(clk), - .out(_U330_out) + .out(_U203_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U331 ( +) _U204 ( .in(in[3]), .clk(clk), - .out(_U331_out) + .out(_U204_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U332 ( +) _U205 ( .in(in[4]), .clk(clk), - .out(_U332_out) + .out(_U205_out) ); -assign out[4] = _U332_out; -assign out[3] = _U331_out; -assign out[2] = _U330_out; -assign out[1] = _U329_out; -assign out[0] = _U328_out; +assign out[4] = _U205_out; +assign out[3] = _U204_out; +assign out[2] = _U203_out; +assign out[1] = _U202_out; +assign out[0] = _U201_out; endmodule -module array_delay_U317 ( +module array_delay_U159 ( input clk, - input [15:0] in [4:0], - output [15:0] out [4:0] + input [15:0] in [3:0], + output [15:0] out [3:0] ); -wire [15:0] _U318_out; -wire [15:0] _U319_out; -wire [15:0] _U320_out; -wire [15:0] _U321_out; -wire [15:0] _U322_out; +wire [15:0] _U160_out; +wire [15:0] _U161_out; +wire [15:0] _U162_out; +wire [15:0] _U163_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U318 ( +) _U160 ( .in(in[0]), .clk(clk), - .out(_U318_out) + .out(_U160_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U319 ( +) _U161 ( .in(in[1]), .clk(clk), - .out(_U319_out) + .out(_U161_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U320 ( +) _U162 ( .in(in[2]), .clk(clk), - .out(_U320_out) + .out(_U162_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U321 ( +) _U163 ( .in(in[3]), .clk(clk), - .out(_U321_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U322 ( - .in(in[4]), - .clk(clk), - .out(_U322_out) + .out(_U163_out) ); -assign out[4] = _U322_out; -assign out[3] = _U321_out; -assign out[2] = _U320_out; -assign out[1] = _U319_out; -assign out[0] = _U318_out; +assign out[3] = _U163_out; +assign out[2] = _U162_out; +assign out[1] = _U161_out; +assign out[0] = _U160_out; endmodule -module array_delay_U29 ( +module array_delay_U150 ( input clk, input [15:0] in [3:0], output [15:0] out [3:0] ); -wire [15:0] _U30_out; -wire [15:0] _U31_out; -wire [15:0] _U32_out; -wire [15:0] _U33_out; +wire [15:0] _U151_out; +wire [15:0] _U152_out; +wire [15:0] _U153_out; +wire [15:0] _U154_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U30 ( +) _U151 ( .in(in[0]), .clk(clk), - .out(_U30_out) + .out(_U151_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U31 ( +) _U152 ( .in(in[1]), .clk(clk), - .out(_U31_out) + .out(_U152_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U32 ( +) _U153 ( .in(in[2]), .clk(clk), - .out(_U32_out) + .out(_U153_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U33 ( +) _U154 ( .in(in[3]), .clk(clk), - .out(_U33_out) + .out(_U154_out) ); -assign out[3] = _U33_out; -assign out[2] = _U32_out; -assign out[1] = _U31_out; -assign out[0] = _U30_out; +assign out[3] = _U154_out; +assign out[2] = _U153_out; +assign out[1] = _U152_out; +assign out[0] = _U151_out; endmodule -module array_delay_U141 ( +module array_delay_U115 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U142_out; -wire [15:0] _U143_out; -wire [15:0] _U144_out; -wire [15:0] _U145_out; -wire [15:0] _U146_out; +wire [15:0] _U116_out; +wire [15:0] _U117_out; +wire [15:0] _U118_out; +wire [15:0] _U119_out; +wire [15:0] _U120_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U142 ( +) _U116 ( .in(in[0]), .clk(clk), - .out(_U142_out) + .out(_U116_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U143 ( +) _U117 ( .in(in[1]), .clk(clk), - .out(_U143_out) + .out(_U117_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U144 ( +) _U118 ( .in(in[2]), .clk(clk), - .out(_U144_out) + .out(_U118_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U145 ( +) _U119 ( .in(in[3]), .clk(clk), - .out(_U145_out) + .out(_U119_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U146 ( +) _U120 ( .in(in[4]), .clk(clk), - .out(_U146_out) + .out(_U120_out) ); -assign out[4] = _U146_out; -assign out[3] = _U145_out; -assign out[2] = _U144_out; -assign out[1] = _U143_out; -assign out[0] = _U142_out; +assign out[4] = _U120_out; +assign out[3] = _U119_out; +assign out[2] = _U118_out; +assign out[1] = _U117_out; +assign out[0] = _U116_out; endmodule -module array_delay_U131 ( +module array_delay_U105 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U132_out; -wire [15:0] _U133_out; -wire [15:0] _U134_out; -wire [15:0] _U135_out; -wire [15:0] _U136_out; +wire [15:0] _U106_out; +wire [15:0] _U107_out; +wire [15:0] _U108_out; +wire [15:0] _U109_out; +wire [15:0] _U110_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U132 ( +) _U106 ( .in(in[0]), .clk(clk), - .out(_U132_out) + .out(_U106_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U133 ( +) _U107 ( .in(in[1]), .clk(clk), - .out(_U133_out) + .out(_U107_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U134 ( +) _U108 ( .in(in[2]), .clk(clk), - .out(_U134_out) + .out(_U108_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U135 ( +) _U109 ( .in(in[3]), .clk(clk), - .out(_U135_out) + .out(_U109_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U136 ( +) _U110 ( .in(in[4]), .clk(clk), - .out(_U136_out) + .out(_U110_out) ); -assign out[4] = _U136_out; -assign out[3] = _U135_out; -assign out[2] = _U134_out; -assign out[1] = _U133_out; -assign out[0] = _U132_out; +assign out[4] = _U110_out; +assign out[3] = _U109_out; +assign out[2] = _U108_out; +assign out[1] = _U107_out; +assign out[0] = _U106_out; endmodule -module aff__U96 ( +module aff__U70 ( output [15:0] out, input [15:0] d [4:0] ); assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0984 * d[1])))) + (16'(16'h032c * d[2])))) + (16'(16'h001d * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h1f49); endmodule -module affine_controller__U95 ( +module affine_controller__U69 ( input clk, output valid, output [15:0] d [4:0] @@ -1224,7 +1224,7 @@ assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U96 affine_func ( +aff__U70 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1294,17 +1294,17 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U44 ( +module aff__U47 ( output [15:0] out, - input [15:0] d [4:0] + input [15:0] d [2:0] ); -assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0984 * d[1])))) + (16'(16'h032c * d[2])))) + (16'(16'h001d * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h1f49); +assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001c * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0002); endmodule -module affine_controller__U43 ( +module affine_controller__U46 ( input clk, output valid, - output [15:0] d [4:0] + output [15:0] d [2:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -1317,20 +1317,12 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; -wire d_3_at_max_out; -wire [15:0] d_3_next_value_out; -wire [15:0] d_3_reg_out; -wire d_4_at_max_out; -wire [15:0] d_4_next_value_out; -wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [4:0]; -assign affine_func_d[4] = d_4_reg_out; -assign affine_func_d[3] = d_3_reg_out; +wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U44 affine_func ( +aff__U47 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1342,7 +1334,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -1351,8 +1343,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h0002; -assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h001b; +assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -1361,8 +1353,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h0002; -assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h001b; +assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -1371,46 +1363,24 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); -assign d_3_at_max_out = d_3_reg_out == 16'h001b; -assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_3_reg ( - .in(d_3_next_value_out), - .clk(clk), - .out(d_3_reg_out), - .en(cmp_time_out) -); -assign d_4_at_max_out = d_4_reg_out == 16'h001b; -assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_4_reg ( - .in(d_4_next_value_out), - .clk(clk), - .out(d_4_reg_out), - .en(cmp_time_out) -); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; -assign d[4] = d_4_reg_out; -assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U282 ( +module aff__U305 ( output [15:0] out, - input [15:0] d [4:0] + input [15:0] d [3:0] ); -assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0984 * d[1])))) + (16'(16'h032c * d[2])))) + (16'(16'h001d * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h1f49); +assign out = 16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h00f0 * d[1])))) + (16'(16'h0008 * d[2])))) + (16'(16'h0001 * d[3])))) + 16'h0001); endmodule -module affine_controller__U281 ( +module affine_controller__U304 ( input clk, output valid, - output [15:0] d [4:0] + output [15:0] d [3:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -1426,17 +1396,13 @@ wire [15:0] d_2_reg_out; wire d_3_at_max_out; wire [15:0] d_3_next_value_out; wire [15:0] d_3_reg_out; -wire d_4_at_max_out; -wire [15:0] d_4_next_value_out; -wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [4:0]; -assign affine_func_d[4] = d_4_reg_out; +wire [15:0] affine_func_d [3:0]; assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U282 affine_func ( +aff__U305 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1448,7 +1414,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = ((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -1457,8 +1423,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h0002; -assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h001d; +assign d_1_next_value_out = (1'b1 & d_2_at_max_out) & d_3_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -1467,8 +1433,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h0002; -assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h001d; +assign d_2_next_value_out = 1'b1 & d_3_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -1477,8 +1443,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); -assign d_3_at_max_out = d_3_reg_out == 16'h001b; -assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; +assign d_3_at_max_out = d_3_reg_out == 16'h0007; +assign d_3_next_value_out = 1'b1 ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_3_reg ( @@ -1487,36 +1453,25 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_3_reg_out), .en(cmp_time_out) ); -assign d_4_at_max_out = d_4_reg_out == 16'h001b; -assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_4_reg ( - .in(d_4_next_value_out), - .clk(clk), - .out(d_4_reg_out), - .en(cmp_time_out) -); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; -assign d[4] = d_4_reg_out; assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U253 ( +module aff__U269 ( output [15:0] out, - input [15:0] d [3:0] + input [15:0] d [4:0] ); -assign out = 16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h00f0 * d[1])))) + (16'(16'h0008 * d[2])))) + (16'(16'h0001 * d[3])))) + 16'h0001); +assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0048 * d[1])))) + (16'(16'h0018 * d[2])))) + (16'(16'h0008 * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h0002); endmodule -module affine_controller__U252 ( +module affine_controller__U268 ( input clk, output valid, - output [15:0] d [3:0] + output [15:0] d [4:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -1532,13 +1487,17 @@ wire [15:0] d_2_reg_out; wire d_3_at_max_out; wire [15:0] d_3_next_value_out; wire [15:0] d_3_reg_out; +wire d_4_at_max_out; +wire [15:0] d_4_next_value_out; +wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [3:0]; +wire [15:0] affine_func_d [4:0]; +assign affine_func_d[4] = d_4_reg_out; assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U253 affine_func ( +aff__U269 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1550,7 +1509,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = ((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -1559,8 +1518,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h001d; -assign d_1_next_value_out = (1'b1 & d_2_at_max_out) & d_3_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h0002; +assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -1569,8 +1528,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h001d; -assign d_2_next_value_out = 1'b1 & d_3_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h0002; +assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -1579,8 +1538,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); -assign d_3_at_max_out = d_3_reg_out == 16'h0007; -assign d_3_next_value_out = 1'b1 ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; +assign d_3_at_max_out = d_3_reg_out == 16'h0002; +assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_3_reg ( @@ -1589,22 +1548,33 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_3_reg_out), .en(cmp_time_out) ); +assign d_4_at_max_out = d_4_reg_out == 16'h0007; +assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_4_reg ( + .in(d_4_next_value_out), + .clk(clk), + .out(d_4_reg_out), + .en(cmp_time_out) +); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; +assign d[4] = d_4_reg_out; assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U230 ( +module aff__U24 ( output [15:0] out, input [15:0] d [2:0] ); assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001c * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0002); endmodule -module affine_controller__U229 ( +module affine_controller__U23 ( input clk, output valid, output [15:0] d [2:0] @@ -1625,7 +1595,7 @@ wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U230 affine_func ( +aff__U24 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1673,17 +1643,17 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U207 ( +module aff__U217 ( output [15:0] out, - input [15:0] d [2:0] + input [15:0] d [4:0] ); -assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001c * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0002); +assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0984 * d[1])))) + (16'(16'h032c * d[2])))) + (16'(16'h001d * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h1f49); endmodule -module affine_controller__U206 ( +module affine_controller__U216 ( input clk, output valid, - output [15:0] d [2:0] + output [15:0] d [4:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -1696,12 +1666,20 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; +wire d_3_at_max_out; +wire [15:0] d_3_next_value_out; +wire [15:0] d_3_reg_out; +wire d_4_at_max_out; +wire [15:0] d_4_next_value_out; +wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [2:0]; +wire [15:0] affine_func_d [4:0]; +assign affine_func_d[4] = d_4_reg_out; +assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U207 affine_func ( +aff__U217 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1713,7 +1691,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -1722,8 +1700,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h001b; -assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h0002; +assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -1732,8 +1710,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h001b; -assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h0002; +assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -1742,24 +1720,46 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); +assign d_3_at_max_out = d_3_reg_out == 16'h001b; +assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_3_reg ( + .in(d_3_next_value_out), + .clk(clk), + .out(d_3_reg_out), + .en(cmp_time_out) +); +assign d_4_at_max_out = d_4_reg_out == 16'h001b; +assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_4_reg ( + .in(d_4_next_value_out), + .clk(clk), + .out(d_4_reg_out), + .en(cmp_time_out) +); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; +assign d[4] = d_4_reg_out; +assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U184 ( +module aff__U165 ( output [15:0] out, - input [15:0] d [2:0] + input [15:0] d [4:0] ); -assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001c * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0002); +assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0984 * d[1])))) + (16'(16'h032c * d[2])))) + (16'(16'h001d * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h1f49); endmodule -module affine_controller__U183 ( +module affine_controller__U164 ( input clk, output valid, - output [15:0] d [2:0] + output [15:0] d [4:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -1772,12 +1772,20 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; +wire d_3_at_max_out; +wire [15:0] d_3_next_value_out; +wire [15:0] d_3_reg_out; +wire d_4_at_max_out; +wire [15:0] d_4_next_value_out; +wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [2:0]; +wire [15:0] affine_func_d [4:0]; +assign affine_func_d[4] = d_4_reg_out; +assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U184 affine_func ( +aff__U165 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1789,7 +1797,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -1798,8 +1806,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h001b; -assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h0002; +assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -1808,8 +1816,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h001b; -assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h0002; +assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -1818,24 +1826,46 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); +assign d_3_at_max_out = d_3_reg_out == 16'h001b; +assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_3_reg ( + .in(d_3_next_value_out), + .clk(clk), + .out(d_3_reg_out), + .en(cmp_time_out) +); +assign d_4_at_max_out = d_4_reg_out == 16'h001b; +assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_4_reg ( + .in(d_4_next_value_out), + .clk(clk), + .out(d_4_reg_out), + .en(cmp_time_out) +); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; +assign d[4] = d_4_reg_out; +assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U148 ( +module aff__U122 ( output [15:0] out, - input [15:0] d [4:0] + input [15:0] d [3:0] ); -assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0048 * d[1])))) + (16'(16'h0018 * d[2])))) + (16'(16'h0008 * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h0002); +assign out = 16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0310 * d[1])))) + (16'(16'h001c * d[2])))) + (16'(16'h0001 * d[3])))) + 16'h3e91); endmodule -module affine_controller__U147 ( +module affine_controller__U121 ( input clk, output valid, - output [15:0] d [4:0] + output [15:0] d [3:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -1851,17 +1881,13 @@ wire [15:0] d_2_reg_out; wire d_3_at_max_out; wire [15:0] d_3_next_value_out; wire [15:0] d_3_reg_out; -wire d_4_at_max_out; -wire [15:0] d_4_next_value_out; -wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [4:0]; -assign affine_func_d[4] = d_4_reg_out; +wire [15:0] affine_func_d [3:0]; assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U148 affine_func ( +aff__U122 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -1873,7 +1899,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = ((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -1883,7 +1909,7 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .en(cmp_time_out) ); assign d_1_at_max_out = d_1_reg_out == 16'h0002; -assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_next_value_out = (1'b1 & d_2_at_max_out) & d_3_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -1892,8 +1918,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h0002; -assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h001b; +assign d_2_next_value_out = 1'b1 & d_3_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -1902,8 +1928,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); -assign d_3_at_max_out = d_3_reg_out == 16'h0002; -assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; +assign d_3_at_max_out = d_3_reg_out == 16'h001b; +assign d_3_next_value_out = 1'b1 ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_3_reg ( @@ -1912,19 +1938,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_3_reg_out), .en(cmp_time_out) ); -assign d_4_at_max_out = d_4_reg_out == 16'h0007; -assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_4_reg ( - .in(d_4_next_value_out), - .clk(clk), - .out(d_4_reg_out), - .en(cmp_time_out) -); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; -assign d[4] = d_4_reg_out; assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; @@ -1933,15 +1948,15 @@ endmodule module aff__U1 ( output [15:0] out, - input [15:0] d [3:0] + input [15:0] d [2:0] ); -assign out = 16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0310 * d[1])))) + (16'(16'h001c * d[2])))) + (16'(16'h0001 * d[3])))) + 16'h3e91); +assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001c * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0002); endmodule module affine_controller__U0 ( input clk, output valid, - output [15:0] d [3:0] + output [15:0] d [2:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -1954,12 +1969,8 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; -wire d_3_at_max_out; -wire [15:0] d_3_next_value_out; -wire [15:0] d_3_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [3:0]; -assign affine_func_d[3] = d_3_reg_out; +wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; @@ -1975,7 +1986,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = ((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -1984,8 +1995,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h0002; -assign d_1_next_value_out = (1'b1 & d_2_at_max_out) & d_3_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h001b; +assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -1995,7 +2006,7 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .en(cmp_time_out) ); assign d_2_at_max_out = d_2_reg_out == 16'h001b; -assign d_2_next_value_out = 1'b1 & d_3_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -2004,19 +2015,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); -assign d_3_at_max_out = d_3_reg_out == 16'h001b; -assign d_3_next_value_out = 1'b1 ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_3_reg ( - .in(d_3_next_value_out), - .clk(clk), - .out(d_3_reg_out), - .en(cmp_time_out) -); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; -assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; @@ -2033,26 +2033,26 @@ module resnet ( output hw_output_stencil_op_hcompute_hw_output_stencil_write_valid, output [15:0] hw_output_stencil_op_hcompute_hw_output_stencil_write [0:0] ); -wire [15:0] arr__U130_out [4:0]; -wire [15:0] arr__U140_out [4:0]; -wire [15:0] arr__U28_out [3:0]; -wire [15:0] arr__U316_out [4:0]; -wire [15:0] arr__U326_out [4:0]; -wire [15:0] arr__U37_out [3:0]; -wire [15:0] arr__U78_out [4:0]; -wire [15:0] arr__U88_out [4:0]; +wire [15:0] arr__U104_out [4:0]; +wire [15:0] arr__U114_out [4:0]; +wire [15:0] arr__U149_out [3:0]; +wire [15:0] arr__U158_out [3:0]; +wire [15:0] arr__U199_out [4:0]; +wire [15:0] arr__U209_out [4:0]; +wire [15:0] arr__U251_out [4:0]; +wire [15:0] arr__U261_out [4:0]; wire [15:0] conv_stencil_op_hcompute_conv_stencil_3_read [0:0]; wire [15:0] conv_stencil_op_hcompute_conv_stencil_4_read [0:0]; wire [15:0] conv_stencil_op_hcompute_conv_stencil_5_read [0:0]; wire [15:0] conv_stencil_op_hcompute_hw_output_stencil_read [0:0]; -wire delay_reg__U128_out; -wire delay_reg__U138_out; -wire delay_reg__U26_out; -wire delay_reg__U314_out; -wire delay_reg__U324_out; -wire delay_reg__U35_out; -wire delay_reg__U76_out; -wire delay_reg__U86_out; +wire delay_reg__U102_out; +wire delay_reg__U112_out; +wire delay_reg__U147_out; +wire delay_reg__U156_out; +wire delay_reg__U197_out; +wire delay_reg__U207_out; +wire delay_reg__U249_out; +wire delay_reg__U259_out; wire [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_read [7:0]; wire [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_read [7:0]; wire [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_read [7:0]; @@ -2137,91 +2137,91 @@ wire [15:0] op_hcompute_hw_output_stencil_port_controller_d [3:0]; wire op_hcompute_hw_output_stencil_read_start_out; wire [15:0] op_hcompute_hw_output_stencil_read_start_control_vars_out [3:0]; wire [15:0] op_hcompute_hw_output_stencil_write_start_control_vars_out [3:0]; -wire [15:0] arr__U130_in [4:0]; -assign arr__U130_in[4] = op_hcompute_conv_stencil_5_port_controller_d[4]; -assign arr__U130_in[3] = op_hcompute_conv_stencil_5_port_controller_d[3]; -assign arr__U130_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; -assign arr__U130_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; -assign arr__U130_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; -array_delay_U131 arr__U130 ( - .clk(clk), - .in(arr__U130_in), - .out(arr__U130_out) -); -wire [15:0] arr__U140_in [4:0]; -assign arr__U140_in[4] = op_hcompute_conv_stencil_5_port_controller_d[4]; -assign arr__U140_in[3] = op_hcompute_conv_stencil_5_port_controller_d[3]; -assign arr__U140_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; -assign arr__U140_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; -assign arr__U140_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; -array_delay_U141 arr__U140 ( - .clk(clk), - .in(arr__U140_in), - .out(arr__U140_out) -); -wire [15:0] arr__U28_in [3:0]; -assign arr__U28_in[3] = op_hcompute_hw_output_stencil_port_controller_d[3]; -assign arr__U28_in[2] = op_hcompute_hw_output_stencil_port_controller_d[2]; -assign arr__U28_in[1] = op_hcompute_hw_output_stencil_port_controller_d[1]; -assign arr__U28_in[0] = op_hcompute_hw_output_stencil_port_controller_d[0]; -array_delay_U29 arr__U28 ( - .clk(clk), - .in(arr__U28_in), - .out(arr__U28_out) -); -wire [15:0] arr__U316_in [4:0]; -assign arr__U316_in[4] = op_hcompute_conv_stencil_3_port_controller_d[4]; -assign arr__U316_in[3] = op_hcompute_conv_stencil_3_port_controller_d[3]; -assign arr__U316_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; -assign arr__U316_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; -assign arr__U316_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; -array_delay_U317 arr__U316 ( - .clk(clk), - .in(arr__U316_in), - .out(arr__U316_out) -); -wire [15:0] arr__U326_in [4:0]; -assign arr__U326_in[4] = op_hcompute_conv_stencil_3_port_controller_d[4]; -assign arr__U326_in[3] = op_hcompute_conv_stencil_3_port_controller_d[3]; -assign arr__U326_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; -assign arr__U326_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; -assign arr__U326_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; -array_delay_U327 arr__U326 ( - .clk(clk), - .in(arr__U326_in), - .out(arr__U326_out) -); -wire [15:0] arr__U37_in [3:0]; -assign arr__U37_in[3] = op_hcompute_hw_output_stencil_port_controller_d[3]; -assign arr__U37_in[2] = op_hcompute_hw_output_stencil_port_controller_d[2]; -assign arr__U37_in[1] = op_hcompute_hw_output_stencil_port_controller_d[1]; -assign arr__U37_in[0] = op_hcompute_hw_output_stencil_port_controller_d[0]; -array_delay_U38 arr__U37 ( - .clk(clk), - .in(arr__U37_in), - .out(arr__U37_out) -); -wire [15:0] arr__U78_in [4:0]; -assign arr__U78_in[4] = op_hcompute_conv_stencil_4_port_controller_d[4]; -assign arr__U78_in[3] = op_hcompute_conv_stencil_4_port_controller_d[3]; -assign arr__U78_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; -assign arr__U78_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; -assign arr__U78_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; -array_delay_U79 arr__U78 ( - .clk(clk), - .in(arr__U78_in), - .out(arr__U78_out) -); -wire [15:0] arr__U88_in [4:0]; -assign arr__U88_in[4] = op_hcompute_conv_stencil_4_port_controller_d[4]; -assign arr__U88_in[3] = op_hcompute_conv_stencil_4_port_controller_d[3]; -assign arr__U88_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; -assign arr__U88_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; -assign arr__U88_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; -array_delay_U89 arr__U88 ( - .clk(clk), - .in(arr__U88_in), - .out(arr__U88_out) +wire [15:0] arr__U104_in [4:0]; +assign arr__U104_in[4] = op_hcompute_conv_stencil_3_port_controller_d[4]; +assign arr__U104_in[3] = op_hcompute_conv_stencil_3_port_controller_d[3]; +assign arr__U104_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; +assign arr__U104_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; +assign arr__U104_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; +array_delay_U105 arr__U104 ( + .clk(clk), + .in(arr__U104_in), + .out(arr__U104_out) +); +wire [15:0] arr__U114_in [4:0]; +assign arr__U114_in[4] = op_hcompute_conv_stencil_3_port_controller_d[4]; +assign arr__U114_in[3] = op_hcompute_conv_stencil_3_port_controller_d[3]; +assign arr__U114_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; +assign arr__U114_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; +assign arr__U114_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; +array_delay_U115 arr__U114 ( + .clk(clk), + .in(arr__U114_in), + .out(arr__U114_out) +); +wire [15:0] arr__U149_in [3:0]; +assign arr__U149_in[3] = op_hcompute_hw_output_stencil_port_controller_d[3]; +assign arr__U149_in[2] = op_hcompute_hw_output_stencil_port_controller_d[2]; +assign arr__U149_in[1] = op_hcompute_hw_output_stencil_port_controller_d[1]; +assign arr__U149_in[0] = op_hcompute_hw_output_stencil_port_controller_d[0]; +array_delay_U150 arr__U149 ( + .clk(clk), + .in(arr__U149_in), + .out(arr__U149_out) +); +wire [15:0] arr__U158_in [3:0]; +assign arr__U158_in[3] = op_hcompute_hw_output_stencil_port_controller_d[3]; +assign arr__U158_in[2] = op_hcompute_hw_output_stencil_port_controller_d[2]; +assign arr__U158_in[1] = op_hcompute_hw_output_stencil_port_controller_d[1]; +assign arr__U158_in[0] = op_hcompute_hw_output_stencil_port_controller_d[0]; +array_delay_U159 arr__U158 ( + .clk(clk), + .in(arr__U158_in), + .out(arr__U158_out) +); +wire [15:0] arr__U199_in [4:0]; +assign arr__U199_in[4] = op_hcompute_conv_stencil_5_port_controller_d[4]; +assign arr__U199_in[3] = op_hcompute_conv_stencil_5_port_controller_d[3]; +assign arr__U199_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; +assign arr__U199_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; +assign arr__U199_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; +array_delay_U200 arr__U199 ( + .clk(clk), + .in(arr__U199_in), + .out(arr__U199_out) +); +wire [15:0] arr__U209_in [4:0]; +assign arr__U209_in[4] = op_hcompute_conv_stencil_5_port_controller_d[4]; +assign arr__U209_in[3] = op_hcompute_conv_stencil_5_port_controller_d[3]; +assign arr__U209_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; +assign arr__U209_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; +assign arr__U209_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; +array_delay_U210 arr__U209 ( + .clk(clk), + .in(arr__U209_in), + .out(arr__U209_out) +); +wire [15:0] arr__U251_in [4:0]; +assign arr__U251_in[4] = op_hcompute_conv_stencil_4_port_controller_d[4]; +assign arr__U251_in[3] = op_hcompute_conv_stencil_4_port_controller_d[3]; +assign arr__U251_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; +assign arr__U251_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; +assign arr__U251_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; +array_delay_U252 arr__U251 ( + .clk(clk), + .in(arr__U251_in), + .out(arr__U251_out) +); +wire [15:0] arr__U261_in [4:0]; +assign arr__U261_in[4] = op_hcompute_conv_stencil_4_port_controller_d[4]; +assign arr__U261_in[3] = op_hcompute_conv_stencil_4_port_controller_d[3]; +assign arr__U261_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; +assign arr__U261_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; +assign arr__U261_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; +array_delay_U262 arr__U261 ( + .clk(clk), + .in(arr__U261_in), + .out(arr__U261_out) ); wire [15:0] conv_stencil_op_hcompute_conv_stencil_1_write_ctrl_vars [2:0]; assign conv_stencil_op_hcompute_conv_stencil_1_write_ctrl_vars[2] = op_hcompute_conv_stencil_1_write_start_control_vars_out[2]; @@ -2326,66 +2326,66 @@ conv_stencil_ub conv_stencil ( corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U128 ( +) delay_reg__U102 ( .clk(clk), - .in(op_hcompute_conv_stencil_5_port_controller_valid), - .out(delay_reg__U128_out) + .in(op_hcompute_conv_stencil_3_port_controller_valid), + .out(delay_reg__U102_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U138 ( +) delay_reg__U112 ( .clk(clk), - .in(op_hcompute_conv_stencil_5_port_controller_valid), - .out(delay_reg__U138_out) + .in(op_hcompute_conv_stencil_3_port_controller_valid), + .out(delay_reg__U112_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U26 ( +) delay_reg__U147 ( .clk(clk), .in(op_hcompute_hw_output_stencil_port_controller_valid), - .out(delay_reg__U26_out) + .out(delay_reg__U147_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U314 ( +) delay_reg__U156 ( .clk(clk), - .in(op_hcompute_conv_stencil_3_port_controller_valid), - .out(delay_reg__U314_out) + .in(op_hcompute_hw_output_stencil_port_controller_valid), + .out(delay_reg__U156_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U324 ( +) delay_reg__U197 ( .clk(clk), - .in(op_hcompute_conv_stencil_3_port_controller_valid), - .out(delay_reg__U324_out) + .in(op_hcompute_conv_stencil_5_port_controller_valid), + .out(delay_reg__U197_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U35 ( +) delay_reg__U207 ( .clk(clk), - .in(op_hcompute_hw_output_stencil_port_controller_valid), - .out(delay_reg__U35_out) + .in(op_hcompute_conv_stencil_5_port_controller_valid), + .out(delay_reg__U207_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U76 ( +) delay_reg__U249 ( .clk(clk), .in(op_hcompute_conv_stencil_4_port_controller_valid), - .out(delay_reg__U76_out) + .out(delay_reg__U249_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U86 ( +) delay_reg__U259 ( .clk(clk), .in(op_hcompute_conv_stencil_4_port_controller_valid), - .out(delay_reg__U86_out) + .out(delay_reg__U259_out) ); wire [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_read_ctrl_vars [4:0]; assign hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_read_ctrl_vars[4] = op_hcompute_conv_stencil_3_port_controller_d[4]; @@ -2480,7 +2480,7 @@ cu_op_hcompute_conv_stencil_1 op_hcompute_conv_stencil_1 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_1_write(op_hcompute_conv_stencil_1_conv_stencil_op_hcompute_conv_stencil_1_write) ); -op_hcompute_conv_stencil_1_exe_start_pt__U225 op_hcompute_conv_stencil_1_exe_start ( +op_hcompute_conv_stencil_1_exe_start_pt__U42 op_hcompute_conv_stencil_1_exe_start ( .in(op_hcompute_conv_stencil_1_port_controller_valid), .out(op_hcompute_conv_stencil_1_exe_start_out) ); @@ -2488,16 +2488,16 @@ wire [15:0] op_hcompute_conv_stencil_1_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_1_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_1_port_controller_d[2]; assign op_hcompute_conv_stencil_1_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_1_port_controller_d[1]; assign op_hcompute_conv_stencil_1_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_1_port_controller_d[0]; -op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U226 op_hcompute_conv_stencil_1_exe_start_control_vars ( +op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U43 op_hcompute_conv_stencil_1_exe_start_control_vars ( .in(op_hcompute_conv_stencil_1_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_1_exe_start_control_vars_out) ); -affine_controller__U206 op_hcompute_conv_stencil_1_port_controller ( +affine_controller__U23 op_hcompute_conv_stencil_1_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_1_port_controller_valid), .d(op_hcompute_conv_stencil_1_port_controller_d) ); -op_hcompute_conv_stencil_1_read_start_pt__U223 op_hcompute_conv_stencil_1_read_start ( +op_hcompute_conv_stencil_1_read_start_pt__U40 op_hcompute_conv_stencil_1_read_start ( .in(op_hcompute_conv_stencil_1_port_controller_valid), .out(op_hcompute_conv_stencil_1_read_start_out) ); @@ -2505,11 +2505,11 @@ wire [15:0] op_hcompute_conv_stencil_1_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_1_read_start_control_vars_in[2] = op_hcompute_conv_stencil_1_port_controller_d[2]; assign op_hcompute_conv_stencil_1_read_start_control_vars_in[1] = op_hcompute_conv_stencil_1_port_controller_d[1]; assign op_hcompute_conv_stencil_1_read_start_control_vars_in[0] = op_hcompute_conv_stencil_1_port_controller_d[0]; -op_hcompute_conv_stencil_1_read_start_control_vars_pt__U224 op_hcompute_conv_stencil_1_read_start_control_vars ( +op_hcompute_conv_stencil_1_read_start_control_vars_pt__U41 op_hcompute_conv_stencil_1_read_start_control_vars ( .in(op_hcompute_conv_stencil_1_read_start_control_vars_in), .out(op_hcompute_conv_stencil_1_read_start_control_vars_out) ); -op_hcompute_conv_stencil_1_write_start_pt__U227 op_hcompute_conv_stencil_1_write_start ( +op_hcompute_conv_stencil_1_write_start_pt__U44 op_hcompute_conv_stencil_1_write_start ( .in(op_hcompute_conv_stencil_1_port_controller_valid), .out(op_hcompute_conv_stencil_1_write_start_out) ); @@ -2517,7 +2517,7 @@ wire [15:0] op_hcompute_conv_stencil_1_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_1_write_start_control_vars_in[2] = op_hcompute_conv_stencil_1_port_controller_d[2]; assign op_hcompute_conv_stencil_1_write_start_control_vars_in[1] = op_hcompute_conv_stencil_1_port_controller_d[1]; assign op_hcompute_conv_stencil_1_write_start_control_vars_in[0] = op_hcompute_conv_stencil_1_port_controller_d[0]; -op_hcompute_conv_stencil_1_write_start_control_vars_pt__U228 op_hcompute_conv_stencil_1_write_start_control_vars ( +op_hcompute_conv_stencil_1_write_start_control_vars_pt__U45 op_hcompute_conv_stencil_1_write_start_control_vars ( .in(op_hcompute_conv_stencil_1_write_start_control_vars_in), .out(op_hcompute_conv_stencil_1_write_start_control_vars_out) ); @@ -2525,7 +2525,7 @@ cu_op_hcompute_conv_stencil_2 op_hcompute_conv_stencil_2 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_2_write(op_hcompute_conv_stencil_2_conv_stencil_op_hcompute_conv_stencil_2_write) ); -op_hcompute_conv_stencil_2_exe_start_pt__U202 op_hcompute_conv_stencil_2_exe_start ( +op_hcompute_conv_stencil_2_exe_start_pt__U65 op_hcompute_conv_stencil_2_exe_start ( .in(op_hcompute_conv_stencil_2_port_controller_valid), .out(op_hcompute_conv_stencil_2_exe_start_out) ); @@ -2533,16 +2533,16 @@ wire [15:0] op_hcompute_conv_stencil_2_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_2_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_2_port_controller_d[2]; assign op_hcompute_conv_stencil_2_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_2_port_controller_d[1]; assign op_hcompute_conv_stencil_2_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_2_port_controller_d[0]; -op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U203 op_hcompute_conv_stencil_2_exe_start_control_vars ( +op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U66 op_hcompute_conv_stencil_2_exe_start_control_vars ( .in(op_hcompute_conv_stencil_2_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_2_exe_start_control_vars_out) ); -affine_controller__U183 op_hcompute_conv_stencil_2_port_controller ( +affine_controller__U46 op_hcompute_conv_stencil_2_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_2_port_controller_valid), .d(op_hcompute_conv_stencil_2_port_controller_d) ); -op_hcompute_conv_stencil_2_read_start_pt__U200 op_hcompute_conv_stencil_2_read_start ( +op_hcompute_conv_stencil_2_read_start_pt__U63 op_hcompute_conv_stencil_2_read_start ( .in(op_hcompute_conv_stencil_2_port_controller_valid), .out(op_hcompute_conv_stencil_2_read_start_out) ); @@ -2550,11 +2550,11 @@ wire [15:0] op_hcompute_conv_stencil_2_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_2_read_start_control_vars_in[2] = op_hcompute_conv_stencil_2_port_controller_d[2]; assign op_hcompute_conv_stencil_2_read_start_control_vars_in[1] = op_hcompute_conv_stencil_2_port_controller_d[1]; assign op_hcompute_conv_stencil_2_read_start_control_vars_in[0] = op_hcompute_conv_stencil_2_port_controller_d[0]; -op_hcompute_conv_stencil_2_read_start_control_vars_pt__U201 op_hcompute_conv_stencil_2_read_start_control_vars ( +op_hcompute_conv_stencil_2_read_start_control_vars_pt__U64 op_hcompute_conv_stencil_2_read_start_control_vars ( .in(op_hcompute_conv_stencil_2_read_start_control_vars_in), .out(op_hcompute_conv_stencil_2_read_start_control_vars_out) ); -op_hcompute_conv_stencil_2_write_start_pt__U204 op_hcompute_conv_stencil_2_write_start ( +op_hcompute_conv_stencil_2_write_start_pt__U67 op_hcompute_conv_stencil_2_write_start ( .in(op_hcompute_conv_stencil_2_port_controller_valid), .out(op_hcompute_conv_stencil_2_write_start_out) ); @@ -2562,7 +2562,7 @@ wire [15:0] op_hcompute_conv_stencil_2_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_2_write_start_control_vars_in[2] = op_hcompute_conv_stencil_2_port_controller_d[2]; assign op_hcompute_conv_stencil_2_write_start_control_vars_in[1] = op_hcompute_conv_stencil_2_port_controller_d[1]; assign op_hcompute_conv_stencil_2_write_start_control_vars_in[0] = op_hcompute_conv_stencil_2_port_controller_d[0]; -op_hcompute_conv_stencil_2_write_start_control_vars_pt__U205 op_hcompute_conv_stencil_2_write_start_control_vars ( +op_hcompute_conv_stencil_2_write_start_control_vars_pt__U68 op_hcompute_conv_stencil_2_write_start_control_vars ( .in(op_hcompute_conv_stencil_2_write_start_control_vars_in), .out(op_hcompute_conv_stencil_2_write_start_control_vars_out) ); @@ -2593,26 +2593,26 @@ cu_op_hcompute_conv_stencil_3 op_hcompute_conv_stencil_3 ( .hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_3_read(op_hcompute_conv_stencil_3_hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_3_read), .conv_stencil_op_hcompute_conv_stencil_3_write(op_hcompute_conv_stencil_3_conv_stencil_op_hcompute_conv_stencil_3_write) ); -op_hcompute_conv_stencil_3_exe_start_pt__U313 op_hcompute_conv_stencil_3_exe_start ( - .in(delay_reg__U314_out), +op_hcompute_conv_stencil_3_exe_start_pt__U101 op_hcompute_conv_stencil_3_exe_start ( + .in(delay_reg__U102_out), .out(op_hcompute_conv_stencil_3_exe_start_out) ); wire [15:0] op_hcompute_conv_stencil_3_exe_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[4] = arr__U316_out[4]; -assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[3] = arr__U316_out[3]; -assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[2] = arr__U316_out[2]; -assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[1] = arr__U316_out[1]; -assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[0] = arr__U316_out[0]; -op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U315 op_hcompute_conv_stencil_3_exe_start_control_vars ( +assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[4] = arr__U104_out[4]; +assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[3] = arr__U104_out[3]; +assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[2] = arr__U104_out[2]; +assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[1] = arr__U104_out[1]; +assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[0] = arr__U104_out[0]; +op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U103 op_hcompute_conv_stencil_3_exe_start_control_vars ( .in(op_hcompute_conv_stencil_3_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_3_exe_start_control_vars_out) ); -affine_controller__U281 op_hcompute_conv_stencil_3_port_controller ( +affine_controller__U69 op_hcompute_conv_stencil_3_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_3_port_controller_valid), .d(op_hcompute_conv_stencil_3_port_controller_d) ); -op_hcompute_conv_stencil_3_read_start_pt__U311 op_hcompute_conv_stencil_3_read_start ( +op_hcompute_conv_stencil_3_read_start_pt__U99 op_hcompute_conv_stencil_3_read_start ( .in(op_hcompute_conv_stencil_3_port_controller_valid), .out(op_hcompute_conv_stencil_3_read_start_out) ); @@ -2622,21 +2622,21 @@ assign op_hcompute_conv_stencil_3_read_start_control_vars_in[3] = op_hcompute_co assign op_hcompute_conv_stencil_3_read_start_control_vars_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; assign op_hcompute_conv_stencil_3_read_start_control_vars_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; assign op_hcompute_conv_stencil_3_read_start_control_vars_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; -op_hcompute_conv_stencil_3_read_start_control_vars_pt__U312 op_hcompute_conv_stencil_3_read_start_control_vars ( +op_hcompute_conv_stencil_3_read_start_control_vars_pt__U100 op_hcompute_conv_stencil_3_read_start_control_vars ( .in(op_hcompute_conv_stencil_3_read_start_control_vars_in), .out(op_hcompute_conv_stencil_3_read_start_control_vars_out) ); -op_hcompute_conv_stencil_3_write_start_pt__U323 op_hcompute_conv_stencil_3_write_start ( - .in(delay_reg__U324_out), +op_hcompute_conv_stencil_3_write_start_pt__U111 op_hcompute_conv_stencil_3_write_start ( + .in(delay_reg__U112_out), .out(op_hcompute_conv_stencil_3_write_start_out) ); wire [15:0] op_hcompute_conv_stencil_3_write_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_3_write_start_control_vars_in[4] = arr__U326_out[4]; -assign op_hcompute_conv_stencil_3_write_start_control_vars_in[3] = arr__U326_out[3]; -assign op_hcompute_conv_stencil_3_write_start_control_vars_in[2] = arr__U326_out[2]; -assign op_hcompute_conv_stencil_3_write_start_control_vars_in[1] = arr__U326_out[1]; -assign op_hcompute_conv_stencil_3_write_start_control_vars_in[0] = arr__U326_out[0]; -op_hcompute_conv_stencil_3_write_start_control_vars_pt__U325 op_hcompute_conv_stencil_3_write_start_control_vars ( +assign op_hcompute_conv_stencil_3_write_start_control_vars_in[4] = arr__U114_out[4]; +assign op_hcompute_conv_stencil_3_write_start_control_vars_in[3] = arr__U114_out[3]; +assign op_hcompute_conv_stencil_3_write_start_control_vars_in[2] = arr__U114_out[2]; +assign op_hcompute_conv_stencil_3_write_start_control_vars_in[1] = arr__U114_out[1]; +assign op_hcompute_conv_stencil_3_write_start_control_vars_in[0] = arr__U114_out[0]; +op_hcompute_conv_stencil_3_write_start_control_vars_pt__U113 op_hcompute_conv_stencil_3_write_start_control_vars ( .in(op_hcompute_conv_stencil_3_write_start_control_vars_in), .out(op_hcompute_conv_stencil_3_write_start_control_vars_out) ); @@ -2667,26 +2667,26 @@ cu_op_hcompute_conv_stencil_4 op_hcompute_conv_stencil_4 ( .hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_4_read(op_hcompute_conv_stencil_4_hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_4_read), .conv_stencil_op_hcompute_conv_stencil_4_write(op_hcompute_conv_stencil_4_conv_stencil_op_hcompute_conv_stencil_4_write) ); -op_hcompute_conv_stencil_4_exe_start_pt__U75 op_hcompute_conv_stencil_4_exe_start ( - .in(delay_reg__U76_out), +op_hcompute_conv_stencil_4_exe_start_pt__U248 op_hcompute_conv_stencil_4_exe_start ( + .in(delay_reg__U249_out), .out(op_hcompute_conv_stencil_4_exe_start_out) ); wire [15:0] op_hcompute_conv_stencil_4_exe_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[4] = arr__U78_out[4]; -assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[3] = arr__U78_out[3]; -assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[2] = arr__U78_out[2]; -assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[1] = arr__U78_out[1]; -assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[0] = arr__U78_out[0]; -op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U77 op_hcompute_conv_stencil_4_exe_start_control_vars ( +assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[4] = arr__U251_out[4]; +assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[3] = arr__U251_out[3]; +assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[2] = arr__U251_out[2]; +assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[1] = arr__U251_out[1]; +assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[0] = arr__U251_out[0]; +op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U250 op_hcompute_conv_stencil_4_exe_start_control_vars ( .in(op_hcompute_conv_stencil_4_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_4_exe_start_control_vars_out) ); -affine_controller__U43 op_hcompute_conv_stencil_4_port_controller ( +affine_controller__U216 op_hcompute_conv_stencil_4_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_4_port_controller_valid), .d(op_hcompute_conv_stencil_4_port_controller_d) ); -op_hcompute_conv_stencil_4_read_start_pt__U73 op_hcompute_conv_stencil_4_read_start ( +op_hcompute_conv_stencil_4_read_start_pt__U246 op_hcompute_conv_stencil_4_read_start ( .in(op_hcompute_conv_stencil_4_port_controller_valid), .out(op_hcompute_conv_stencil_4_read_start_out) ); @@ -2696,21 +2696,21 @@ assign op_hcompute_conv_stencil_4_read_start_control_vars_in[3] = op_hcompute_co assign op_hcompute_conv_stencil_4_read_start_control_vars_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; assign op_hcompute_conv_stencil_4_read_start_control_vars_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; assign op_hcompute_conv_stencil_4_read_start_control_vars_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; -op_hcompute_conv_stencil_4_read_start_control_vars_pt__U74 op_hcompute_conv_stencil_4_read_start_control_vars ( +op_hcompute_conv_stencil_4_read_start_control_vars_pt__U247 op_hcompute_conv_stencil_4_read_start_control_vars ( .in(op_hcompute_conv_stencil_4_read_start_control_vars_in), .out(op_hcompute_conv_stencil_4_read_start_control_vars_out) ); -op_hcompute_conv_stencil_4_write_start_pt__U85 op_hcompute_conv_stencil_4_write_start ( - .in(delay_reg__U86_out), +op_hcompute_conv_stencil_4_write_start_pt__U258 op_hcompute_conv_stencil_4_write_start ( + .in(delay_reg__U259_out), .out(op_hcompute_conv_stencil_4_write_start_out) ); wire [15:0] op_hcompute_conv_stencil_4_write_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_4_write_start_control_vars_in[4] = arr__U88_out[4]; -assign op_hcompute_conv_stencil_4_write_start_control_vars_in[3] = arr__U88_out[3]; -assign op_hcompute_conv_stencil_4_write_start_control_vars_in[2] = arr__U88_out[2]; -assign op_hcompute_conv_stencil_4_write_start_control_vars_in[1] = arr__U88_out[1]; -assign op_hcompute_conv_stencil_4_write_start_control_vars_in[0] = arr__U88_out[0]; -op_hcompute_conv_stencil_4_write_start_control_vars_pt__U87 op_hcompute_conv_stencil_4_write_start_control_vars ( +assign op_hcompute_conv_stencil_4_write_start_control_vars_in[4] = arr__U261_out[4]; +assign op_hcompute_conv_stencil_4_write_start_control_vars_in[3] = arr__U261_out[3]; +assign op_hcompute_conv_stencil_4_write_start_control_vars_in[2] = arr__U261_out[2]; +assign op_hcompute_conv_stencil_4_write_start_control_vars_in[1] = arr__U261_out[1]; +assign op_hcompute_conv_stencil_4_write_start_control_vars_in[0] = arr__U261_out[0]; +op_hcompute_conv_stencil_4_write_start_control_vars_pt__U260 op_hcompute_conv_stencil_4_write_start_control_vars ( .in(op_hcompute_conv_stencil_4_write_start_control_vars_in), .out(op_hcompute_conv_stencil_4_write_start_control_vars_out) ); @@ -2741,26 +2741,26 @@ cu_op_hcompute_conv_stencil_5 op_hcompute_conv_stencil_5 ( .hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_5_read(op_hcompute_conv_stencil_5_hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_5_read), .conv_stencil_op_hcompute_conv_stencil_5_write(op_hcompute_conv_stencil_5_conv_stencil_op_hcompute_conv_stencil_5_write) ); -op_hcompute_conv_stencil_5_exe_start_pt__U127 op_hcompute_conv_stencil_5_exe_start ( - .in(delay_reg__U128_out), +op_hcompute_conv_stencil_5_exe_start_pt__U196 op_hcompute_conv_stencil_5_exe_start ( + .in(delay_reg__U197_out), .out(op_hcompute_conv_stencil_5_exe_start_out) ); wire [15:0] op_hcompute_conv_stencil_5_exe_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[4] = arr__U130_out[4]; -assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[3] = arr__U130_out[3]; -assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[2] = arr__U130_out[2]; -assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[1] = arr__U130_out[1]; -assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[0] = arr__U130_out[0]; -op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U129 op_hcompute_conv_stencil_5_exe_start_control_vars ( +assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[4] = arr__U199_out[4]; +assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[3] = arr__U199_out[3]; +assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[2] = arr__U199_out[2]; +assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[1] = arr__U199_out[1]; +assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[0] = arr__U199_out[0]; +op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U198 op_hcompute_conv_stencil_5_exe_start_control_vars ( .in(op_hcompute_conv_stencil_5_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_5_exe_start_control_vars_out) ); -affine_controller__U95 op_hcompute_conv_stencil_5_port_controller ( +affine_controller__U164 op_hcompute_conv_stencil_5_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_5_port_controller_valid), .d(op_hcompute_conv_stencil_5_port_controller_d) ); -op_hcompute_conv_stencil_5_read_start_pt__U125 op_hcompute_conv_stencil_5_read_start ( +op_hcompute_conv_stencil_5_read_start_pt__U194 op_hcompute_conv_stencil_5_read_start ( .in(op_hcompute_conv_stencil_5_port_controller_valid), .out(op_hcompute_conv_stencil_5_read_start_out) ); @@ -2770,25 +2770,25 @@ assign op_hcompute_conv_stencil_5_read_start_control_vars_in[3] = op_hcompute_co assign op_hcompute_conv_stencil_5_read_start_control_vars_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; assign op_hcompute_conv_stencil_5_read_start_control_vars_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; assign op_hcompute_conv_stencil_5_read_start_control_vars_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; -op_hcompute_conv_stencil_5_read_start_control_vars_pt__U126 op_hcompute_conv_stencil_5_read_start_control_vars ( +op_hcompute_conv_stencil_5_read_start_control_vars_pt__U195 op_hcompute_conv_stencil_5_read_start_control_vars ( .in(op_hcompute_conv_stencil_5_read_start_control_vars_in), .out(op_hcompute_conv_stencil_5_read_start_control_vars_out) ); -op_hcompute_conv_stencil_5_write_start_pt__U137 op_hcompute_conv_stencil_5_write_start ( - .in(delay_reg__U138_out), +op_hcompute_conv_stencil_5_write_start_pt__U206 op_hcompute_conv_stencil_5_write_start ( + .in(delay_reg__U207_out), .out(op_hcompute_conv_stencil_5_write_start_out) ); wire [15:0] op_hcompute_conv_stencil_5_write_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_5_write_start_control_vars_in[4] = arr__U140_out[4]; -assign op_hcompute_conv_stencil_5_write_start_control_vars_in[3] = arr__U140_out[3]; -assign op_hcompute_conv_stencil_5_write_start_control_vars_in[2] = arr__U140_out[2]; -assign op_hcompute_conv_stencil_5_write_start_control_vars_in[1] = arr__U140_out[1]; -assign op_hcompute_conv_stencil_5_write_start_control_vars_in[0] = arr__U140_out[0]; -op_hcompute_conv_stencil_5_write_start_control_vars_pt__U139 op_hcompute_conv_stencil_5_write_start_control_vars ( +assign op_hcompute_conv_stencil_5_write_start_control_vars_in[4] = arr__U209_out[4]; +assign op_hcompute_conv_stencil_5_write_start_control_vars_in[3] = arr__U209_out[3]; +assign op_hcompute_conv_stencil_5_write_start_control_vars_in[2] = arr__U209_out[2]; +assign op_hcompute_conv_stencil_5_write_start_control_vars_in[1] = arr__U209_out[1]; +assign op_hcompute_conv_stencil_5_write_start_control_vars_in[0] = arr__U209_out[0]; +op_hcompute_conv_stencil_5_write_start_control_vars_pt__U208 op_hcompute_conv_stencil_5_write_start_control_vars ( .in(op_hcompute_conv_stencil_5_write_start_control_vars_in), .out(op_hcompute_conv_stencil_5_write_start_control_vars_out) ); -op_hcompute_conv_stencil_exe_start_pt__U248 op_hcompute_conv_stencil_exe_start ( +op_hcompute_conv_stencil_exe_start_pt__U19 op_hcompute_conv_stencil_exe_start ( .in(op_hcompute_conv_stencil_port_controller_valid), .out(op_hcompute_conv_stencil_exe_start_out) ); @@ -2796,16 +2796,16 @@ wire [15:0] op_hcompute_conv_stencil_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_port_controller_d[2]; assign op_hcompute_conv_stencil_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_port_controller_d[1]; assign op_hcompute_conv_stencil_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_port_controller_d[0]; -op_hcompute_conv_stencil_exe_start_control_vars_pt__U249 op_hcompute_conv_stencil_exe_start_control_vars ( +op_hcompute_conv_stencil_exe_start_control_vars_pt__U20 op_hcompute_conv_stencil_exe_start_control_vars ( .in(op_hcompute_conv_stencil_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_exe_start_control_vars_out) ); -affine_controller__U229 op_hcompute_conv_stencil_port_controller ( +affine_controller__U0 op_hcompute_conv_stencil_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_port_controller_valid), .d(op_hcompute_conv_stencil_port_controller_d) ); -op_hcompute_conv_stencil_read_start_pt__U246 op_hcompute_conv_stencil_read_start ( +op_hcompute_conv_stencil_read_start_pt__U17 op_hcompute_conv_stencil_read_start ( .in(op_hcompute_conv_stencil_port_controller_valid), .out(op_hcompute_conv_stencil_read_start_out) ); @@ -2813,11 +2813,11 @@ wire [15:0] op_hcompute_conv_stencil_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_read_start_control_vars_in[2] = op_hcompute_conv_stencil_port_controller_d[2]; assign op_hcompute_conv_stencil_read_start_control_vars_in[1] = op_hcompute_conv_stencil_port_controller_d[1]; assign op_hcompute_conv_stencil_read_start_control_vars_in[0] = op_hcompute_conv_stencil_port_controller_d[0]; -op_hcompute_conv_stencil_read_start_control_vars_pt__U247 op_hcompute_conv_stencil_read_start_control_vars ( +op_hcompute_conv_stencil_read_start_control_vars_pt__U18 op_hcompute_conv_stencil_read_start_control_vars ( .in(op_hcompute_conv_stencil_read_start_control_vars_in), .out(op_hcompute_conv_stencil_read_start_control_vars_out) ); -op_hcompute_conv_stencil_write_start_pt__U250 op_hcompute_conv_stencil_write_start ( +op_hcompute_conv_stencil_write_start_pt__U21 op_hcompute_conv_stencil_write_start ( .in(op_hcompute_conv_stencil_port_controller_valid), .out(op_hcompute_conv_stencil_write_start_out) ); @@ -2825,7 +2825,7 @@ wire [15:0] op_hcompute_conv_stencil_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_write_start_control_vars_in[2] = op_hcompute_conv_stencil_port_controller_d[2]; assign op_hcompute_conv_stencil_write_start_control_vars_in[1] = op_hcompute_conv_stencil_port_controller_d[1]; assign op_hcompute_conv_stencil_write_start_control_vars_in[0] = op_hcompute_conv_stencil_port_controller_d[0]; -op_hcompute_conv_stencil_write_start_control_vars_pt__U251 op_hcompute_conv_stencil_write_start_control_vars ( +op_hcompute_conv_stencil_write_start_control_vars_pt__U22 op_hcompute_conv_stencil_write_start_control_vars ( .in(op_hcompute_conv_stencil_write_start_control_vars_in), .out(op_hcompute_conv_stencil_write_start_control_vars_out) ); @@ -2836,7 +2836,7 @@ cu_op_hcompute_hw_input_global_wrapper_stencil op_hcompute_hw_input_global_wrapp .hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read(op_hcompute_hw_input_global_wrapper_stencil_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write(op_hcompute_hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write) ); -op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U277 op_hcompute_hw_input_global_wrapper_stencil_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U329 op_hcompute_hw_input_global_wrapper_stencil_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_exe_start_out) ); @@ -2845,16 +2845,16 @@ assign op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in[3] assign op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U278 op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U330 op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_out) ); -affine_controller__U252 op_hcompute_hw_input_global_wrapper_stencil_port_controller ( +affine_controller__U304 op_hcompute_hw_input_global_wrapper_stencil_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U275 op_hcompute_hw_input_global_wrapper_stencil_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U327 op_hcompute_hw_input_global_wrapper_stencil_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), .out(hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_en) ); @@ -2863,11 +2863,11 @@ assign op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in[3] assign op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U276 op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U328 op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U279 op_hcompute_hw_input_global_wrapper_stencil_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U331 op_hcompute_hw_input_global_wrapper_stencil_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_write_start_out) ); @@ -2876,7 +2876,7 @@ assign op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in[3 assign op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U280 op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U332 op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_out) ); @@ -2887,7 +2887,7 @@ cu_op_hcompute_hw_kernel_global_wrapper_stencil op_hcompute_hw_kernel_global_wra .hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read(op_hcompute_hw_kernel_global_wrapper_stencil_hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read), .hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write(op_hcompute_hw_kernel_global_wrapper_stencil_hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write) ); -op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U179 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start ( +op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U300 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_out) ); @@ -2897,16 +2897,16 @@ assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[3] assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[2] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[1] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[0] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U180 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars ( +op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U301 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in), .out(op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_out) ); -affine_controller__U147 op_hcompute_hw_kernel_global_wrapper_stencil_port_controller ( +affine_controller__U268 op_hcompute_hw_kernel_global_wrapper_stencil_port_controller ( .clk(clk), .valid(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .d(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d) ); -op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U177 op_hcompute_hw_kernel_global_wrapper_stencil_read_start ( +op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U298 op_hcompute_hw_kernel_global_wrapper_stencil_read_start ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .out(hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en) ); @@ -2916,11 +2916,11 @@ assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[3 assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[2] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[1] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[0] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U178 op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars ( +op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U299 op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in), .out(op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_out) ); -op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U181 op_hcompute_hw_kernel_global_wrapper_stencil_write_start ( +op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U302 op_hcompute_hw_kernel_global_wrapper_stencil_write_start ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_kernel_global_wrapper_stencil_write_start_out) ); @@ -2930,7 +2930,7 @@ assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[ assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[2] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[1] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[0] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U182 op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars ( +op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U303 op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in), .out(op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_out) ); @@ -2941,25 +2941,25 @@ cu_op_hcompute_hw_output_stencil op_hcompute_hw_output_stencil ( .conv_stencil_op_hcompute_hw_output_stencil_read(op_hcompute_hw_output_stencil_conv_stencil_op_hcompute_hw_output_stencil_read), .hw_output_stencil_op_hcompute_hw_output_stencil_write(op_hcompute_hw_output_stencil_hw_output_stencil_op_hcompute_hw_output_stencil_write) ); -op_hcompute_hw_output_stencil_exe_start_pt__U25 op_hcompute_hw_output_stencil_exe_start ( - .in(delay_reg__U26_out), +op_hcompute_hw_output_stencil_exe_start_pt__U146 op_hcompute_hw_output_stencil_exe_start ( + .in(delay_reg__U147_out), .out(op_hcompute_hw_output_stencil_exe_start_out) ); wire [15:0] op_hcompute_hw_output_stencil_exe_start_control_vars_in [3:0]; -assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[3] = arr__U28_out[3]; -assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[2] = arr__U28_out[2]; -assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[1] = arr__U28_out[1]; -assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[0] = arr__U28_out[0]; -op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U27 op_hcompute_hw_output_stencil_exe_start_control_vars ( +assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[3] = arr__U149_out[3]; +assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[2] = arr__U149_out[2]; +assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[1] = arr__U149_out[1]; +assign op_hcompute_hw_output_stencil_exe_start_control_vars_in[0] = arr__U149_out[0]; +op_hcompute_hw_output_stencil_exe_start_control_vars_pt__U148 op_hcompute_hw_output_stencil_exe_start_control_vars ( .in(op_hcompute_hw_output_stencil_exe_start_control_vars_in), .out(op_hcompute_hw_output_stencil_exe_start_control_vars_out) ); -affine_controller__U0 op_hcompute_hw_output_stencil_port_controller ( +affine_controller__U121 op_hcompute_hw_output_stencil_port_controller ( .clk(clk), .valid(op_hcompute_hw_output_stencil_port_controller_valid), .d(op_hcompute_hw_output_stencil_port_controller_d) ); -op_hcompute_hw_output_stencil_read_start_pt__U23 op_hcompute_hw_output_stencil_read_start ( +op_hcompute_hw_output_stencil_read_start_pt__U144 op_hcompute_hw_output_stencil_read_start ( .in(op_hcompute_hw_output_stencil_port_controller_valid), .out(op_hcompute_hw_output_stencil_read_start_out) ); @@ -2968,20 +2968,20 @@ assign op_hcompute_hw_output_stencil_read_start_control_vars_in[3] = op_hcompute assign op_hcompute_hw_output_stencil_read_start_control_vars_in[2] = op_hcompute_hw_output_stencil_port_controller_d[2]; assign op_hcompute_hw_output_stencil_read_start_control_vars_in[1] = op_hcompute_hw_output_stencil_port_controller_d[1]; assign op_hcompute_hw_output_stencil_read_start_control_vars_in[0] = op_hcompute_hw_output_stencil_port_controller_d[0]; -op_hcompute_hw_output_stencil_read_start_control_vars_pt__U24 op_hcompute_hw_output_stencil_read_start_control_vars ( +op_hcompute_hw_output_stencil_read_start_control_vars_pt__U145 op_hcompute_hw_output_stencil_read_start_control_vars ( .in(op_hcompute_hw_output_stencil_read_start_control_vars_in), .out(op_hcompute_hw_output_stencil_read_start_control_vars_out) ); -op_hcompute_hw_output_stencil_write_start_pt__U34 op_hcompute_hw_output_stencil_write_start ( - .in(delay_reg__U35_out), +op_hcompute_hw_output_stencil_write_start_pt__U155 op_hcompute_hw_output_stencil_write_start ( + .in(delay_reg__U156_out), .out(hw_output_stencil_op_hcompute_hw_output_stencil_write_valid) ); wire [15:0] op_hcompute_hw_output_stencil_write_start_control_vars_in [3:0]; -assign op_hcompute_hw_output_stencil_write_start_control_vars_in[3] = arr__U37_out[3]; -assign op_hcompute_hw_output_stencil_write_start_control_vars_in[2] = arr__U37_out[2]; -assign op_hcompute_hw_output_stencil_write_start_control_vars_in[1] = arr__U37_out[1]; -assign op_hcompute_hw_output_stencil_write_start_control_vars_in[0] = arr__U37_out[0]; -op_hcompute_hw_output_stencil_write_start_control_vars_pt__U36 op_hcompute_hw_output_stencil_write_start_control_vars ( +assign op_hcompute_hw_output_stencil_write_start_control_vars_in[3] = arr__U158_out[3]; +assign op_hcompute_hw_output_stencil_write_start_control_vars_in[2] = arr__U158_out[2]; +assign op_hcompute_hw_output_stencil_write_start_control_vars_in[1] = arr__U158_out[1]; +assign op_hcompute_hw_output_stencil_write_start_control_vars_in[0] = arr__U158_out[0]; +op_hcompute_hw_output_stencil_write_start_control_vars_pt__U157 op_hcompute_hw_output_stencil_write_start_control_vars ( .in(op_hcompute_hw_output_stencil_write_start_control_vars_in), .out(op_hcompute_hw_output_stencil_write_start_control_vars_out) ); diff --git a/coreir_apps/platonic_buffer/resnet/resnet_verilog_collateral.sv b/coreir_apps/platonic_buffer/resnet/resnet_verilog_collateral.sv index b8b1e5b4c..84baed4d9 100644 --- a/coreir_apps/platonic_buffer/resnet/resnet_verilog_collateral.sv +++ b/coreir_apps/platonic_buffer/resnet/resnet_verilog_collateral.sv @@ -1064,12 +1064,16 @@ conv_stencil_embarassing_bank_selector conv_stencil_conv_stencil_op_hcompute_hw_ endmodule -// hw_input_global_wrapper_stencil has embarassing partition: 1 +// hw_input_global_wrapper_stencil has embarassing partition: 0 -module hw_input_global_wrapper_stencil_embarassing_bank_selector(input logic [16*3 - 1 :0] d, output logic [15:0] out); +module hw_input_global_wrapper_stencil_bank_selector(input logic [16*3 - 1 :0] d, output logic [15:0] out); + logic [15:0] bank_index_0; + assign bank_index_0 = (d[15:0] % 1); + logic [15:0] bank_index_1; + assign bank_index_1 = (d[31:16] % 1); logic [15:0] bank_index_2; - assign bank_index_2 = (d[47:32]); - assign out = 0+bank_index_2*1; + assign bank_index_2 = (d[47:32] % 1); + assign out = bank_index_0*1+bank_index_1*1+bank_index_2*1; endmodule @@ -1642,193 +1646,186 @@ module hw_input_global_wrapper_stencil_ub( logic [15:0]op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4:0]; logic op_hcompute_conv_stencil_5_read_ren_fsm_out; hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_read_fsm hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_read_fsm_inst (.clk(clk), .flush(flush), .rst_n(rst_n), .op_hcompute_conv_stencil_5_read_ctrl_vars( op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out), .op_hcompute_conv_stencil_5_read_ren(op_hcompute_conv_stencil_5_read_ren_fsm_out)); - // # of banks: 8 - logic [15:0] bank_0 [900]; - logic [15:0] bank_1 [900]; - logic [15:0] bank_2 [900]; - logic [15:0] bank_3 [900]; - logic [15:0] bank_4 [900]; - logic [15:0] bank_5 [900]; - logic [15:0] bank_6 [900]; - logic [15:0] bank_7 [900]; + // # of banks: 1 + logic [15:0] bank_0 [7200]; logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_2 = (((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[3])) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_44_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_45_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_46_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_47_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_48_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_49_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_50_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_0 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_1 = (((1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_3_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_3_51_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_26_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_27_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_28_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_29_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_30_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_31_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_32_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_0 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_1 = (((1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_4_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_4_33_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_0 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_1 = (((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_0})); logic [15:0] addr0; - assign addr0 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr0 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[3])) - 0)>>0)*900); always @(posedge clk) begin end always @(posedge clk) begin @@ -1838,255 +1835,93 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe always @(posedge clk) begin end logic [15:0] addr1; - assign addr1 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr1 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((2)) - 0)>>0)*900); always @(posedge clk) begin end logic [15:0] addr2; - assign addr2 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr2 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((3)) - 0)>>0)*900); always @(posedge clk) begin end logic [15:0] addr3; - assign addr3 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr3 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((4)) - 0)>>0)*900); always @(posedge clk) begin end logic [15:0] addr4; - assign addr4 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr4 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((5)) - 0)>>0)*900); always @(posedge clk) begin end logic [15:0] addr5; - assign addr5 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr5 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((7)) - 0)>>0)*900); always @(posedge clk) begin end logic [15:0] addr6; - assign addr6 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr6 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((6)) - 0)>>0)*900); always @(posedge clk) begin end logic [15:0] addr7; - assign addr7 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr7 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((0 - 0)>>0)*900); always @(posedge clk) begin end logic [15:0] addr8; - assign addr8 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr8 = (((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_5_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((1)) - 0)>>0)*900); always @(posedge clk) begin end always @(posedge clk) begin - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==0) begin - bank_0[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; - end - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==1) begin - bank_1[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; - end - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==2) begin - bank_2[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; - end - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==3) begin - bank_3[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; - end - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==4) begin - bank_4[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; - end - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==5) begin - bank_5[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; - end - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==6) begin - bank_6[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; - end - if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out==7) begin - bank_7[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; + if (op_hcompute_hw_input_global_wrapper_stencil_write_wen_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_bank_selector.out) + 0:bank_0[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; + default:bank_0[addr0] <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; + endcase end end always @(posedge clk) begin - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[2] <= bank_0[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[3] <= bank_0[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[4] <= bank_0[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[5] <= bank_0[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[6] <= bank_0[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[7] <= bank_0[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[0] <= bank_0[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==0) begin - op_hcompute_conv_stencil_5_read[1] <= bank_0[addr8]; - end - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[2] <= bank_1[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[3] <= bank_1[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[4] <= bank_1[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[5] <= bank_1[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[6] <= bank_1[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[7] <= bank_1[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[0] <= bank_1[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==1) begin - op_hcompute_conv_stencil_5_read[1] <= bank_1[addr8]; - end - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[2] <= bank_2[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[3] <= bank_2[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[4] <= bank_2[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[5] <= bank_2[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[6] <= bank_2[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[7] <= bank_2[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[0] <= bank_2[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==2) begin - op_hcompute_conv_stencil_5_read[1] <= bank_2[addr8]; - end - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[2] <= bank_3[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[3] <= bank_3[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[4] <= bank_3[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[5] <= bank_3[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[6] <= bank_3[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[7] <= bank_3[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[0] <= bank_3[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==3) begin - op_hcompute_conv_stencil_5_read[1] <= bank_3[addr8]; - end - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[2] <= bank_4[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[3] <= bank_4[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[4] <= bank_4[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[5] <= bank_4[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[6] <= bank_4[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[7] <= bank_4[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[0] <= bank_4[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==4) begin - op_hcompute_conv_stencil_5_read[1] <= bank_4[addr8]; - end - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[2] <= bank_5[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[3] <= bank_5[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[4] <= bank_5[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[5] <= bank_5[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[6] <= bank_5[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[7] <= bank_5[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[0] <= bank_5[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==5) begin - op_hcompute_conv_stencil_5_read[1] <= bank_5[addr8]; - end - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[2] <= bank_6[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[3] <= bank_6[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[4] <= bank_6[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[5] <= bank_6[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[6] <= bank_6[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[7] <= bank_6[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[0] <= bank_6[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==6) begin - op_hcompute_conv_stencil_5_read[1] <= bank_6[addr8]; - end - if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[2] <= bank_7[addr1]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[3] <= bank_7[addr2]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[4] <= bank_7[addr3]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[5] <= bank_7[addr4]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[6] <= bank_7[addr5]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[7] <= bank_7[addr6]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[0] <= bank_7[addr7]; - end - else if (op_hcompute_conv_stencil_5_read_ren_fsm_out &&hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out==7) begin - op_hcompute_conv_stencil_5_read[1] <= bank_7[addr8]; + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_10_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[2] <= bank_0[addr1]; + default:op_hcompute_conv_stencil_5_read[2] <= 327; + endcase + end + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_11_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[3] <= bank_0[addr2]; + default:op_hcompute_conv_stencil_5_read[3] <= 327; + endcase + end + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_12_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[4] <= bank_0[addr3]; + default:op_hcompute_conv_stencil_5_read[4] <= 327; + endcase + end + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_13_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[5] <= bank_0[addr4]; + default:op_hcompute_conv_stencil_5_read[5] <= 327; + endcase + end + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_14_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[6] <= bank_0[addr5]; + default:op_hcompute_conv_stencil_5_read[6] <= 327; + endcase + end + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_15_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[7] <= bank_0[addr6]; + default:op_hcompute_conv_stencil_5_read[7] <= 327; + endcase + end + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_8_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[0] <= bank_0[addr7]; + default:op_hcompute_conv_stencil_5_read[0] <= 327; + endcase + end + if (op_hcompute_conv_stencil_5_read_ren_fsm_out) begin + case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_5_9_bank_selector.out) + 0:op_hcompute_conv_stencil_5_read[1] <= bank_0[addr8]; + default:op_hcompute_conv_stencil_5_read[1] <= 327; + endcase end end diff --git a/coreir_apps/platonic_buffer/resnet88/resnet88.json b/coreir_apps/platonic_buffer/resnet88/resnet88.json index 97679424f..1c05baa1f 100644 --- a/coreir_apps/platonic_buffer/resnet88/resnet88.json +++ b/coreir_apps/platonic_buffer/resnet88/resnet88.json @@ -11,7 +11,7 @@ ["self.out","self.in"] ] }, - "_U1005_pt__U1006":{ + "_U1002_pt__U1003":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -20,7 +20,7 @@ ["self.out","self.in"] ] }, - "_U1007_pt__U1008":{ + "_U1006_pt__U1007":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -29,7 +29,7 @@ ["self.out","self.in"] ] }, - "_U1011_pt__U1012":{ + "_U1019_pt__U1020":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -38,7 +38,7 @@ ["self.out","self.in"] ] }, - "_U1013_pt__U1014":{ + "_U101_pt__U102":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -47,7 +47,7 @@ ["self.out","self.in"] ] }, - "_U1017_pt__U1018":{ + "_U1027_pt__U1028":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -56,7 +56,7 @@ ["self.out","self.in"] ] }, - "_U1026_pt__U1027":{ + "_U1035_pt__U1036":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -65,7 +65,7 @@ ["self.out","self.in"] ] }, - "_U1029_pt__U1030":{ + "_U1039_pt__U1040":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -74,7 +74,7 @@ ["self.out","self.in"] ] }, - "_U1034_pt__U1035":{ + "_U104_pt__U105":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -83,7 +83,7 @@ ["self.out","self.in"] ] }, - "_U1039_pt__U1040":{ + "_U1055_pt__U1056":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -92,7 +92,7 @@ ["self.out","self.in"] ] }, - "_U1049_pt__U1050":{ + "_U1067_pt__U1068":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -101,7 +101,7 @@ ["self.out","self.in"] ] }, - "_U1065_pt__U1066":{ + "_U1070_pt__U1071":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -110,7 +110,7 @@ ["self.out","self.in"] ] }, - "_U1074_pt__U1075":{ + "_U1072_pt__U1073":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -119,7 +119,7 @@ ["self.out","self.in"] ] }, - "_U1077_pt__U1078":{ + "_U1075_pt__U1076":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -128,7 +128,7 @@ ["self.out","self.in"] ] }, - "_U1082_pt__U1083":{ + "_U1085_pt__U1086":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -146,7 +146,7 @@ ["self.out","self.in"] ] }, - "_U1096_pt__U1097":{ + "_U1094_pt__U1095":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -164,7 +164,7 @@ ["self.out","self.in"] ] }, - "_U1102_pt__U1103":{ + "_U1101_pt__U1102":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -173,7 +173,7 @@ ["self.out","self.in"] ] }, - "_U1105_pt__U1106":{ + "_U1108_pt__U1109":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -182,7 +182,7 @@ ["self.out","self.in"] ] }, - "_U1115_pt__U1116":{ + "_U1116_pt__U1117":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -191,7 +191,7 @@ ["self.out","self.in"] ] }, - "_U1119_pt__U1120":{ + "_U1118_pt__U1119":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -209,7 +209,7 @@ ["self.out","self.in"] ] }, - "_U1123_pt__U1124":{ + "_U1120_pt__U1121":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -218,7 +218,7 @@ ["self.out","self.in"] ] }, - "_U1133_pt__U1134":{ + "_U1123_pt__U1124":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -227,7 +227,7 @@ ["self.out","self.in"] ] }, - "_U1139_pt__U1140":{ + "_U1132_pt__U1133":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -236,7 +236,7 @@ ["self.out","self.in"] ] }, - "_U1146_pt__U1147":{ + "_U1135_pt__U1136":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -245,7 +245,7 @@ ["self.out","self.in"] ] }, - "_U1154_pt__U1155":{ + "_U1138_pt__U1139":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -254,7 +254,7 @@ ["self.out","self.in"] ] }, - "_U115_pt__U116":{ + "_U1144_pt__U1145":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -263,7 +263,7 @@ ["self.out","self.in"] ] }, - "_U1162_pt__U1163":{ + "_U1147_pt__U1148":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -272,7 +272,7 @@ ["self.out","self.in"] ] }, - "_U1164_pt__U1165":{ + "_U1153_pt__U1154":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -281,7 +281,7 @@ ["self.out","self.in"] ] }, - "_U1166_pt__U1167":{ + "_U1162_pt__U1163":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -290,7 +290,7 @@ ["self.out","self.in"] ] }, - "_U1178_pt__U1179":{ + "_U1166_pt__U1167":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -299,7 +299,7 @@ ["self.out","self.in"] ] }, - "_U1181_pt__U1182":{ + "_U1171_pt__U1172":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -308,7 +308,7 @@ ["self.out","self.in"] ] }, - "_U1184_pt__U1185":{ + "_U1179_pt__U1180":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -317,7 +317,7 @@ ["self.out","self.in"] ] }, - "_U118_pt__U119":{ + "_U1183_pt__U1184":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -326,7 +326,7 @@ ["self.out","self.in"] ] }, - "_U1193_pt__U1194":{ + "_U1186_pt__U1187":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -335,7 +335,7 @@ ["self.out","self.in"] ] }, - "_U1199_pt__U1200":{ + "_U1194_pt__U1195":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -344,7 +344,7 @@ ["self.out","self.in"] ] }, - "_U1206_pt__U1207":{ + "_U1205_pt__U1206":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -353,7 +353,7 @@ ["self.out","self.in"] ] }, - "_U1209_pt__U1210":{ + "_U1211_pt__U1212":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -362,7 +362,7 @@ ["self.out","self.in"] ] }, - "_U1212_pt__U1213":{ + "_U1226_pt__U1227":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -371,7 +371,7 @@ ["self.out","self.in"] ] }, - "_U1220_pt__U1221":{ + "_U1229_pt__U1230":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -380,7 +380,7 @@ ["self.out","self.in"] ] }, - "_U1223_pt__U1224":{ + "_U1232_pt__U1233":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -389,7 +389,7 @@ ["self.out","self.in"] ] }, - "_U1228_pt__U1229":{ + "_U1235_pt__U1236":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -398,7 +398,7 @@ ["self.out","self.in"] ] }, - "_U1231_pt__U1232":{ + "_U1240_pt__U1241":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -407,7 +407,7 @@ ["self.out","self.in"] ] }, - "_U1233_pt__U1234":{ + "_U1256_pt__U1257":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -416,7 +416,7 @@ ["self.out","self.in"] ] }, - "_U1236_pt__U1237":{ + "_U1258_pt__U1259":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -425,7 +425,7 @@ ["self.out","self.in"] ] }, - "_U1240_pt__U1241":{ + "_U1260_pt__U1261":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -434,7 +434,7 @@ ["self.out","self.in"] ] }, - "_U1242_pt__U1243":{ + "_U1263_pt__U1264":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -443,7 +443,7 @@ ["self.out","self.in"] ] }, - "_U1244_pt__U1245":{ + "_U1266_pt__U1267":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -452,7 +452,7 @@ ["self.out","self.in"] ] }, - "_U1247_pt__U1248":{ + "_U1274_pt__U1275":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -461,7 +461,7 @@ ["self.out","self.in"] ] }, - "_U1250_pt__U1251":{ + "_U1277_pt__U1278":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -470,7 +470,7 @@ ["self.out","self.in"] ] }, - "_U1253_pt__U1254":{ + "_U127_pt__U128":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -479,7 +479,7 @@ ["self.out","self.in"] ] }, - "_U1259_pt__U1260":{ + "_U1283_pt__U1284":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -488,7 +488,7 @@ ["self.out","self.in"] ] }, - "_U1262_pt__U1263":{ + "_U1292_pt__U1293":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -497,7 +497,7 @@ ["self.out","self.in"] ] }, - "_U1270_pt__U1271":{ + "_U1299_pt__U1300":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -506,7 +506,7 @@ ["self.out","self.in"] ] }, - "_U1278_pt__U1279":{ + "_U129_pt__U130":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -515,16 +515,7 @@ ["self.out","self.in"] ] }, - "_U1287_pt__U1288":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U1296_pt__U1297":{ + "_U12_pt__U13":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -533,7 +524,7 @@ ["self.out","self.in"] ] }, - "_U12_pt__U13":{ + "_U1307_pt__U1308":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -542,7 +533,7 @@ ["self.out","self.in"] ] }, - "_U1313_pt__U1314":{ + "_U1315_pt__U1316":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -551,7 +542,7 @@ ["self.out","self.in"] ] }, - "_U1316_pt__U1317":{ + "_U131_pt__U132":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -560,7 +551,7 @@ ["self.out","self.in"] ] }, - "_U1319_pt__U1320":{ + "_U1324_pt__U1325":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -569,7 +560,7 @@ ["self.out","self.in"] ] }, - "_U1331_pt__U1332":{ + "_U1338_pt__U1339":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -578,7 +569,7 @@ ["self.out","self.in"] ] }, - "_U1334_pt__U1335":{ + "_U1341_pt__U1342":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -587,7 +578,7 @@ ["self.out","self.in"] ] }, - "_U1340_pt__U1341":{ + "_U1344_pt__U1345":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -596,7 +587,7 @@ ["self.out","self.in"] ] }, - "_U1346_pt__U1347":{ + "_U134_pt__U135":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -605,7 +596,7 @@ ["self.out","self.in"] ] }, - "_U134_pt__U135":{ + "_U1356_pt__U1357":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -614,7 +605,7 @@ ["self.out","self.in"] ] }, - "_U1353_pt__U1354":{ + "_U1361_pt__U1362":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -623,7 +614,7 @@ ["self.out","self.in"] ] }, - "_U1360_pt__U1361":{ + "_U1366_pt__U1367":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -632,7 +623,7 @@ ["self.out","self.in"] ] }, - "_U136_pt__U137":{ + "_U1372_pt__U1373":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -641,7 +632,7 @@ ["self.out","self.in"] ] }, - "_U1370_pt__U1371":{ + "_U1378_pt__U1379":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -650,7 +641,7 @@ ["self.out","self.in"] ] }, - "_U1373_pt__U1374":{ + "_U137_pt__U138":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -659,7 +650,7 @@ ["self.out","self.in"] ] }, - "_U1381_pt__U1382":{ + "_U1385_pt__U1386":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -668,7 +659,7 @@ ["self.out","self.in"] ] }, - "_U1385_pt__U1386":{ + "_U1388_pt__U1389":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -677,7 +668,7 @@ ["self.out","self.in"] ] }, - "_U1389_pt__U1390":{ + "_U1398_pt__U1399":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -686,7 +677,7 @@ ["self.out","self.in"] ] }, - "_U138_pt__U139":{ + "_U139_pt__U140":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -695,7 +686,7 @@ ["self.out","self.in"] ] }, - "_U1394_pt__U1395":{ + "_U1401_pt__U1402":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -704,7 +695,7 @@ ["self.out","self.in"] ] }, - "_U1399_pt__U1400":{ + "_U1405_pt__U1406":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -713,7 +704,7 @@ ["self.out","self.in"] ] }, - "_U1401_pt__U1402":{ + "_U1409_pt__U1410":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -722,7 +713,7 @@ ["self.out","self.in"] ] }, - "_U1415_pt__U1416":{ + "_U1426_pt__U1427":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -731,7 +722,7 @@ ["self.out","self.in"] ] }, - "_U1418_pt__U1419":{ + "_U1429_pt__U1430":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -740,7 +731,7 @@ ["self.out","self.in"] ] }, - "_U141_pt__U142":{ + "_U1431_pt__U1432":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -749,7 +740,7 @@ ["self.out","self.in"] ] }, - "_U1422_pt__U1423":{ + "_U1434_pt__U1435":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -758,7 +749,7 @@ ["self.out","self.in"] ] }, - "_U1425_pt__U1426":{ + "_U1438_pt__U1439":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -776,7 +767,7 @@ ["self.out","self.in"] ] }, - "_U144_pt__U145":{ + "_U1449_pt__U1450":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -785,7 +776,7 @@ ["self.out","self.in"] ] }, - "_U1450_pt__U1451":{ + "_U1457_pt__U1458":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -794,7 +785,7 @@ ["self.out","self.in"] ] }, - "_U1459_pt__U1460":{ + "_U1466_pt__U1467":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -803,7 +794,7 @@ ["self.out","self.in"] ] }, - "_U1462_pt__U1463":{ + "_U1475_pt__U1476":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -812,7 +803,7 @@ ["self.out","self.in"] ] }, - "_U1466_pt__U1467":{ + "_U1477_pt__U1478":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -821,7 +812,7 @@ ["self.out","self.in"] ] }, - "_U1470_pt__U1471":{ + "_U1480_pt__U1481":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -830,7 +821,7 @@ ["self.out","self.in"] ] }, - "_U1475_pt__U1476":{ + "_U1483_pt__U1484":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -839,7 +830,7 @@ ["self.out","self.in"] ] }, - "_U1480_pt__U1481":{ + "_U1487_pt__U1488":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -848,7 +839,7 @@ ["self.out","self.in"] ] }, - "_U1486_pt__U1487":{ + "_U1491_pt__U1492":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -857,7 +848,7 @@ ["self.out","self.in"] ] }, - "_U148_pt__U149":{ + "_U1496_pt__U1497":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -866,7 +857,7 @@ ["self.out","self.in"] ] }, - "_U1492_pt__U1493":{ + "_U14_pt__U15":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -875,7 +866,7 @@ ["self.out","self.in"] ] }, - "_U1499_pt__U1500":{ + "_U1501_pt__U1502":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -884,7 +875,7 @@ ["self.out","self.in"] ] }, - "_U14_pt__U15":{ + "_U1507_pt__U1508":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -893,7 +884,7 @@ ["self.out","self.in"] ] }, - "_U1506_pt__U1507":{ + "_U1513_pt__U1514":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -902,7 +893,7 @@ ["self.out","self.in"] ] }, - "_U1514_pt__U1515":{ + "_U1520_pt__U1521":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -911,7 +902,7 @@ ["self.out","self.in"] ] }, - "_U1522_pt__U1523":{ + "_U1527_pt__U1528":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -920,7 +911,7 @@ ["self.out","self.in"] ] }, - "_U1525_pt__U1526":{ + "_U1531_pt__U1532":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -929,7 +920,7 @@ ["self.out","self.in"] ] }, - "_U1541_pt__U1542":{ + "_U1534_pt__U1535":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -938,7 +929,7 @@ ["self.out","self.in"] ] }, - "_U1543_pt__U1544":{ + "_U153_pt__U154":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -947,7 +938,7 @@ ["self.out","self.in"] ] }, - "_U1545_pt__U1546":{ + "_U1550_pt__U1551":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -956,7 +947,7 @@ ["self.out","self.in"] ] }, - "_U1548_pt__U1549":{ + "_U1552_pt__U1553":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -965,7 +956,7 @@ ["self.out","self.in"] ] }, - "_U1556_pt__U1557":{ + "_U1555_pt__U1556":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -974,7 +965,7 @@ ["self.out","self.in"] ] }, - "_U1559_pt__U1560":{ + "_U1563_pt__U1564":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -983,7 +974,7 @@ ["self.out","self.in"] ] }, - "_U1565_pt__U1566":{ + "_U1566_pt__U1567":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -992,7 +983,7 @@ ["self.out","self.in"] ] }, - "_U1568_pt__U1569":{ + "_U156_pt__U157":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1010,7 +1001,7 @@ ["self.out","self.in"] ] }, - "_U1589_pt__U1590":{ + "_U1575_pt__U1576":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1028,7 +1019,7 @@ ["self.out","self.in"] ] }, - "_U1594_pt__U1595":{ + "_U1595_pt__U1596":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1037,7 +1028,7 @@ ["self.out","self.in"] ] }, - "_U1608_pt__U1609":{ + "_U1597_pt__U1598":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1046,7 +1037,7 @@ ["self.out","self.in"] ] }, - "_U1611_pt__U1612":{ + "_U159_pt__U160":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1055,7 +1046,7 @@ ["self.out","self.in"] ] }, - "_U1614_pt__U1615":{ + "_U1611_pt__U1612":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1064,7 +1055,7 @@ ["self.out","self.in"] ] }, - "_U1626_pt__U1627":{ + "_U1614_pt__U1615":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1073,7 +1064,7 @@ ["self.out","self.in"] ] }, - "_U1629_pt__U1630":{ + "_U1617_pt__U1618":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1082,7 +1073,7 @@ ["self.out","self.in"] ] }, - "_U162_pt__U163":{ + "_U1629_pt__U1630":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1091,7 +1082,7 @@ ["self.out","self.in"] ] }, - "_U1639_pt__U1640":{ + "_U1632_pt__U1633":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1172,7 +1163,241 @@ ["self.out","self.in"] ] }, - "_U165_pt__U166":{ + "_U16_pt__U17":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U171_pt__U172":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U174_pt__U175":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U184_pt__U185":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U187_pt__U188":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U18_pt__U19":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U195_pt__U196":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U198_pt__U199":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U207_pt__U208":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U20_pt__U21":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U216_pt__U217":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U22_pt__U23":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U233_pt__U234":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U235_pt__U236":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U241_pt__U242":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U24_pt__U25":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U254_pt__U255":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U257_pt__U258":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U259_pt__U260":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U269_pt__U270":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U26_pt__U27":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U272_pt__U273":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U275_pt__U276":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U283_pt__U284":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U286_pt__U287":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U28_pt__U29":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U292_pt__U293":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1181,250 +1406,7 @@ ["self.out","self.in"] ] }, - "_U168_pt__U169":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U16_pt__U17":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U180_pt__U181":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U183_pt__U184":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U18_pt__U19":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U193_pt__U194":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U196_pt__U197":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U204_pt__U205":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U207_pt__U208":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U20_pt__U21":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U213_pt__U214":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U22_pt__U23":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U230_pt__U231":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U233_pt__U234":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U235_pt__U236":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U24_pt__U25":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U250_pt__U251":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U253_pt__U254":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U255_pt__U256":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U267_pt__U268":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U26_pt__U27":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U270_pt__U271":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U273_pt__U274":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U283_pt__U284":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U286_pt__U287":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U28_pt__U29":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U294_pt__U295":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U297_pt__U298":{ + "_U295_pt__U296":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1442,16 +1424,7 @@ ["self.out","self.in"] ] }, - "_U303_pt__U304":{ - "type":["Record",[ - ["in",["Array",16,"BitIn"]], - ["out",["Array",16,"Bit"]] - ]], - "connections":[ - ["self.out","self.in"] - ] - }, - "_U306_pt__U307":{ + "_U307_pt__U308":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1478,7 +1451,7 @@ ["self.out","self.in"] ] }, - "_U313_pt__U314":{ + "_U320_pt__U321":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1505,7 +1478,7 @@ ["self.out","self.in"] ] }, - "_U332_pt__U333":{ + "_U331_pt__U332":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1514,7 +1487,7 @@ ["self.out","self.in"] ] }, - "_U348_pt__U349":{ + "_U338_pt__U339":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1523,7 +1496,7 @@ ["self.out","self.in"] ] }, - "_U34_pt__U35":{ + "_U354_pt__U355":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1532,7 +1505,7 @@ ["self.out","self.in"] ] }, - "_U353_pt__U354":{ + "_U35_pt__U36":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1541,7 +1514,7 @@ ["self.out","self.in"] ] }, - "_U358_pt__U359":{ + "_U361_pt__U362":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1550,7 +1523,7 @@ ["self.out","self.in"] ] }, - "_U364_pt__U365":{ + "_U368_pt__U369":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1559,7 +1532,7 @@ ["self.out","self.in"] ] }, - "_U370_pt__U371":{ + "_U376_pt__U377":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1568,7 +1541,7 @@ ["self.out","self.in"] ] }, - "_U377_pt__U378":{ + "_U384_pt__U385":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1577,7 +1550,7 @@ ["self.out","self.in"] ] }, - "_U384_pt__U385":{ + "_U393_pt__U394":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1586,7 +1559,7 @@ ["self.out","self.in"] ] }, - "_U38_pt__U39":{ + "_U39_pt__U40":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1595,7 +1568,7 @@ ["self.out","self.in"] ] }, - "_U392_pt__U393":{ + "_U402_pt__U403":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1604,7 +1577,7 @@ ["self.out","self.in"] ] }, - "_U400_pt__U401":{ + "_U404_pt__U405":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1613,7 +1586,7 @@ ["self.out","self.in"] ] }, - "_U409_pt__U410":{ + "_U406_pt__U407":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1622,7 +1595,7 @@ ["self.out","self.in"] ] }, - "_U418_pt__U419":{ + "_U409_pt__U410":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1631,7 +1604,7 @@ ["self.out","self.in"] ] }, - "_U420_pt__U421":{ + "_U412_pt__U413":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1640,7 +1613,7 @@ ["self.out","self.in"] ] }, - "_U422_pt__U423":{ + "_U416_pt__U417":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1649,7 +1622,7 @@ ["self.out","self.in"] ] }, - "_U425_pt__U426":{ + "_U420_pt__U421":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1658,7 +1631,7 @@ ["self.out","self.in"] ] }, - "_U428_pt__U429":{ + "_U425_pt__U426":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1667,7 +1640,7 @@ ["self.out","self.in"] ] }, - "_U432_pt__U433":{ + "_U430_pt__U431":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1856,7 +1829,7 @@ ["self.out","self.in"] ] }, - "_U549_pt__U550":{ + "_U53_pt__U54":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1865,7 +1838,7 @@ ["self.out","self.in"] ] }, - "_U54_pt__U55":{ + "_U549_pt__U550":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1973,7 +1946,7 @@ ["self.out","self.in"] ] }, - "_U603_pt__U604":{ + "_U59_pt__U60":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -1982,7 +1955,7 @@ ["self.out","self.in"] ] }, - "_U60_pt__U61":{ + "_U603_pt__U604":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2036,7 +2009,7 @@ ["self.out","self.in"] ] }, - "_U650_pt__U651":{ + "_U651_pt__U652":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2045,7 +2018,7 @@ ["self.out","self.in"] ] }, - "_U659_pt__U660":{ + "_U65_pt__U66":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2054,7 +2027,7 @@ ["self.out","self.in"] ] }, - "_U661_pt__U662":{ + "_U660_pt__U661":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2063,7 +2036,7 @@ ["self.out","self.in"] ] }, - "_U664_pt__U665":{ + "_U663_pt__U664":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2081,7 +2054,7 @@ ["self.out","self.in"] ] }, - "_U674_pt__U675":{ + "_U670_pt__U671":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2090,7 +2063,7 @@ ["self.out","self.in"] ] }, - "_U67_pt__U68":{ + "_U678_pt__U679":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2099,7 +2072,7 @@ ["self.out","self.in"] ] }, - "_U682_pt__U683":{ + "_U683_pt__U684":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2108,7 +2081,7 @@ ["self.out","self.in"] ] }, - "_U686_pt__U687":{ + "_U685_pt__U686":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2117,7 +2090,7 @@ ["self.out","self.in"] ] }, - "_U688_pt__U689":{ + "_U6_pt__U7":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2126,7 +2099,7 @@ ["self.out","self.in"] ] }, - "_U697_pt__U698":{ + "_U701_pt__U702":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2135,7 +2108,7 @@ ["self.out","self.in"] ] }, - "_U6_pt__U7":{ + "_U707_pt__U708":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2144,7 +2117,7 @@ ["self.out","self.in"] ] }, - "_U705_pt__U706":{ + "_U709_pt__U710":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2153,7 +2126,7 @@ ["self.out","self.in"] ] }, - "_U721_pt__U722":{ + "_U715_pt__U716":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2162,7 +2135,7 @@ ["self.out","self.in"] ] }, - "_U726_pt__U727":{ + "_U723_pt__U724":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2171,7 +2144,7 @@ ["self.out","self.in"] ] }, - "_U732_pt__U733":{ + "_U726_pt__U727":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2180,7 +2153,7 @@ ["self.out","self.in"] ] }, - "_U735_pt__U736":{ + "_U72_pt__U73":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2189,7 +2162,7 @@ ["self.out","self.in"] ] }, - "_U740_pt__U741":{ + "_U735_pt__U736":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2198,7 +2171,7 @@ ["self.out","self.in"] ] }, - "_U744_pt__U745":{ + "_U740_pt__U741":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2207,7 +2180,7 @@ ["self.out","self.in"] ] }, - "_U74_pt__U75":{ + "_U744_pt__U745":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2279,7 +2252,7 @@ ["self.out","self.in"] ] }, - "_U801_pt__U802":{ + "_U79_pt__U80":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2288,7 +2261,7 @@ ["self.out","self.in"] ] }, - "_U811_pt__U812":{ + "_U801_pt__U802":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2297,7 +2270,7 @@ ["self.out","self.in"] ] }, - "_U814_pt__U815":{ + "_U811_pt__U812":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2306,7 +2279,7 @@ ["self.out","self.in"] ] }, - "_U822_pt__U823":{ + "_U814_pt__U815":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2315,7 +2288,7 @@ ["self.out","self.in"] ] }, - "_U825_pt__U826":{ + "_U822_pt__U823":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2324,7 +2297,7 @@ ["self.out","self.in"] ] }, - "_U82_pt__U83":{ + "_U825_pt__U826":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2396,6 +2369,15 @@ ["self.out","self.in"] ] }, + "_U868_pt__U869":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, "_U870_pt__U871":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], @@ -2414,7 +2396,7 @@ ["self.out","self.in"] ] }, - "_U879_pt__U880":{ + "_U876_pt__U877":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2423,7 +2405,7 @@ ["self.out","self.in"] ] }, - "_U890_pt__U891":{ + "_U87_pt__U88":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2432,7 +2414,7 @@ ["self.out","self.in"] ] }, - "_U893_pt__U894":{ + "_U885_pt__U886":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2441,7 +2423,7 @@ ["self.out","self.in"] ] }, - "_U899_pt__U900":{ + "_U889_pt__U890":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2459,6 +2441,15 @@ ["self.out","self.in"] ] }, + "_U901_pt__U902":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, "_U907_pt__U908":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], @@ -2468,7 +2459,7 @@ ["self.out","self.in"] ] }, - "_U90_pt__U91":{ + "_U923_pt__U924":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2477,7 +2468,7 @@ ["self.out","self.in"] ] }, - "_U910_pt__U911":{ + "_U931_pt__U932":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2486,7 +2477,7 @@ ["self.out","self.in"] ] }, - "_U916_pt__U917":{ + "_U939_pt__U940":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2495,7 +2486,7 @@ ["self.out","self.in"] ] }, - "_U923_pt__U924":{ + "_U942_pt__U943":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2504,7 +2495,7 @@ ["self.out","self.in"] ] }, - "_U936_pt__U937":{ + "_U948_pt__U949":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2513,7 +2504,7 @@ ["self.out","self.in"] ] }, - "_U939_pt__U940":{ + "_U956_pt__U957":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2522,7 +2513,7 @@ ["self.out","self.in"] ] }, - "_U941_pt__U942":{ + "_U959_pt__U960":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2531,7 +2522,7 @@ ["self.out","self.in"] ] }, - "_U954_pt__U955":{ + "_U95_pt__U96":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2540,7 +2531,7 @@ ["self.out","self.in"] ] }, - "_U961_pt__U962":{ + "_U968_pt__U969":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2549,7 +2540,7 @@ ["self.out","self.in"] ] }, - "_U967_pt__U968":{ + "_U971_pt__U972":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2558,7 +2549,7 @@ ["self.out","self.in"] ] }, - "_U970_pt__U971":{ + "_U974_pt__U975":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2567,7 +2558,7 @@ ["self.out","self.in"] ] }, - "_U980_pt__U981":{ + "_U981_pt__U982":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2576,7 +2567,7 @@ ["self.out","self.in"] ] }, - "_U989_pt__U990":{ + "_U988_pt__U989":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2585,7 +2576,16 @@ ["self.out","self.in"] ] }, - "_U997_pt__U998":{ + "_U990_pt__U991":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "connections":[ + ["self.out","self.in"] + ] + }, + "_U992_pt__U993":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -2594,7 +2594,7 @@ ["self.out","self.in"] ] }, - "_U99_pt__U100":{ + "_U997_pt__U998":{ "type":["Record",[ ["in",["Array",16,"BitIn"]], ["out",["Array",16,"Bit"]] @@ -3110,18 +3110,26 @@ "aff__U162":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",3,["Array",16,"BitIn"]]] + ["d",["Array",5,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U170":{ + "add_all__U174":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U171":{ + "add_all__U175":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U172":{ + "add_all__U176":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U177":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U178":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, @@ -3133,18 +3141,28 @@ "coeff_1_U165":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001f"]} + "modargs":{"value":[["BitVector",16],"16'h00d8"]} }, "coeff_2_U167":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0001"]} + "modargs":{"value":[["BitVector",16],"16'h0048"]} + }, + "coeff_3_U169":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0009"]} }, - "const_term_U169":{ + "coeff_4_U171":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, + "const_term_U173":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, "mul_d0__U164":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} @@ -3156,22 +3174,38 @@ "mul_d2__U168":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} + }, + "mul_d3__U170":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_d4__U172":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U164.out","add_all__U170.in0"], - ["mul_d1__U166.out","add_all__U170.in1"], - ["add_all__U171.in0","add_all__U170.out"], - ["mul_d2__U168.out","add_all__U171.in1"], - ["add_all__U172.in0","add_all__U171.out"], - ["const_term_U169.out","add_all__U172.in1"], - ["self.out","add_all__U172.out"], + ["mul_d0__U164.out","add_all__U174.in0"], + ["mul_d1__U166.out","add_all__U174.in1"], + ["add_all__U175.in0","add_all__U174.out"], + ["mul_d2__U168.out","add_all__U175.in1"], + ["add_all__U176.in0","add_all__U175.out"], + ["mul_d3__U170.out","add_all__U176.in1"], + ["add_all__U177.in0","add_all__U176.out"], + ["mul_d4__U172.out","add_all__U177.in1"], + ["add_all__U178.in0","add_all__U177.out"], + ["const_term_U173.out","add_all__U178.in1"], + ["self.out","add_all__U178.out"], ["mul_d0__U164.in0","coeff_0_U163.out"], ["mul_d1__U166.in0","coeff_1_U165.out"], ["mul_d2__U168.in0","coeff_2_U167.out"], + ["mul_d3__U170.in0","coeff_3_U169.out"], + ["mul_d4__U172.in0","coeff_4_U171.out"], ["self.d.0","mul_d0__U164.in1"], ["self.d.1","mul_d1__U166.in1"], - ["self.d.2","mul_d2__U168.in1"] + ["self.d.2","mul_d2__U168.in1"], + ["self.d.3","mul_d3__U170.in1"], + ["self.d.4","mul_d4__U172.in1"] ] }, "aff__U1721":{ @@ -3275,107 +3309,6 @@ ["self.d.4","mul_d4__U1731.in1"] ] }, - "aff__U185":{ - "type":["Record",[ - ["out",["Array",16,"Bit"]], - ["d",["Array",5,["Array",16,"BitIn"]]] - ]], - "instances":{ - "add_all__U197":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U198":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U199":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U200":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U201":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "coeff_0_U186":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "coeff_1_U188":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h00d8"]} - }, - "coeff_2_U190":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0048"]} - }, - "coeff_3_U192":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0009"]} - }, - "coeff_4_U194":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0001"]} - }, - "const_term_U196":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} - }, - "mul_d0__U187":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} - }, - "mul_d1__U189":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} - }, - "mul_d2__U191":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} - }, - "mul_d3__U193":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} - }, - "mul_d4__U195":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} - } - }, - "connections":[ - ["mul_d0__U187.out","add_all__U197.in0"], - ["mul_d1__U189.out","add_all__U197.in1"], - ["add_all__U198.in0","add_all__U197.out"], - ["mul_d2__U191.out","add_all__U198.in1"], - ["add_all__U199.in0","add_all__U198.out"], - ["mul_d3__U193.out","add_all__U199.in1"], - ["add_all__U200.in0","add_all__U199.out"], - ["mul_d4__U195.out","add_all__U200.in1"], - ["add_all__U201.in0","add_all__U200.out"], - ["const_term_U196.out","add_all__U201.in1"], - ["self.out","add_all__U201.out"], - ["mul_d0__U187.in0","coeff_0_U186.out"], - ["mul_d1__U189.in0","coeff_1_U188.out"], - ["mul_d2__U191.in0","coeff_2_U190.out"], - ["mul_d3__U193.in0","coeff_3_U192.out"], - ["mul_d4__U195.in0","coeff_4_U194.out"], - ["self.d.0","mul_d0__U187.in1"], - ["self.d.1","mul_d1__U189.in1"], - ["self.d.2","mul_d2__U191.in1"], - ["self.d.3","mul_d3__U193.in1"], - ["self.d.4","mul_d4__U195.in1"] - ] - }, "aff__U1909":{ "type":["Record",[ ["out",["Array",16,"Bit"]], @@ -3510,6 +3443,73 @@ ["self.d.2","mul_d2__U1962.in1"] ] }, + "aff__U198":{ + "type":["Record",[ + ["out",["Array",16,"Bit"]], + ["d",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_all__U206":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U207":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U208":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "coeff_0_U199":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "coeff_1_U201":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "coeff_2_U203":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_term_U205":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_d0__U200":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_d1__U202":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_d2__U204":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_d0__U200.out","add_all__U206.in0"], + ["mul_d1__U202.out","add_all__U206.in1"], + ["add_all__U207.in0","add_all__U206.out"], + ["mul_d2__U204.out","add_all__U207.in1"], + ["add_all__U208.in0","add_all__U207.out"], + ["const_term_U205.out","add_all__U208.in1"], + ["self.out","add_all__U208.out"], + ["mul_d0__U200.in0","coeff_0_U199.out"], + ["mul_d1__U202.in0","coeff_1_U201.out"], + ["mul_d2__U204.in0","coeff_2_U203.out"], + ["self.d.0","mul_d0__U200.in1"], + ["self.d.1","mul_d1__U202.in1"], + ["self.d.2","mul_d2__U204.in1"] + ] + }, "aff__U2003":{ "type":["Record",[ ["out",["Array",16,"Bit"]], @@ -4451,18 +4451,26 @@ "aff__U382":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",3,["Array",16,"BitIn"]]] + ["d",["Array",5,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U390":{ + "add_all__U394":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U391":{ + "add_all__U395":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U392":{ + "add_all__U396":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U397":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_all__U398":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, @@ -4474,17 +4482,27 @@ "coeff_1_U385":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001d"]} + "modargs":{"value":[["BitVector",16],"16'h0f18"]} }, "coeff_2_U387":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0508"]} + }, + "coeff_3_U389":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h002e"]} + }, + "coeff_4_U391":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U389":{ + "const_term_U393":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h03ea"]} }, "mul_d0__U384":{ "genref":"coreir.mul", @@ -4497,190 +4515,172 @@ "mul_d2__U388":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} + }, + "mul_d3__U390":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_d4__U392":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U384.out","add_all__U390.in0"], - ["mul_d1__U386.out","add_all__U390.in1"], - ["add_all__U391.in0","add_all__U390.out"], - ["mul_d2__U388.out","add_all__U391.in1"], - ["add_all__U392.in0","add_all__U391.out"], - ["const_term_U389.out","add_all__U392.in1"], - ["self.out","add_all__U392.out"], + ["mul_d0__U384.out","add_all__U394.in0"], + ["mul_d1__U386.out","add_all__U394.in1"], + ["add_all__U395.in0","add_all__U394.out"], + ["mul_d2__U388.out","add_all__U395.in1"], + ["add_all__U396.in0","add_all__U395.out"], + ["mul_d3__U390.out","add_all__U396.in1"], + ["add_all__U397.in0","add_all__U396.out"], + ["mul_d4__U392.out","add_all__U397.in1"], + ["add_all__U398.in0","add_all__U397.out"], + ["const_term_U393.out","add_all__U398.in1"], + ["self.out","add_all__U398.out"], ["mul_d0__U384.in0","coeff_0_U383.out"], ["mul_d1__U386.in0","coeff_1_U385.out"], ["mul_d2__U388.in0","coeff_2_U387.out"], + ["mul_d3__U390.in0","coeff_3_U389.out"], + ["mul_d4__U392.in0","coeff_4_U391.out"], ["self.d.0","mul_d0__U384.in1"], ["self.d.1","mul_d1__U386.in1"], - ["self.d.2","mul_d2__U388.in1"] + ["self.d.2","mul_d2__U388.in1"], + ["self.d.3","mul_d3__U390.in1"], + ["self.d.4","mul_d4__U392.in1"] ] }, - "aff__U405":{ + "aff__U47":{ "type":["Record",[ ["out",["Array",16,"Bit"]], - ["d",["Array",5,["Array",16,"BitIn"]]] + ["d",["Array",3,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U417":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U418":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "add_all__U419":{ + "add_all__U55":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U420":{ + "add_all__U56":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U421":{ + "add_all__U57":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U406":{ + "coeff_0_U48":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U408":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0f18"]} - }, - "coeff_2_U410":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0508"]} - }, - "coeff_3_U412":{ + "coeff_1_U50":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h002e"]} + "modargs":{"value":[["BitVector",16],"16'h001f"]} }, - "coeff_4_U414":{ + "coeff_2_U52":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U416":{ + "const_term_U54":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h03ea"]} - }, - "mul_d0__U407":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} - }, - "mul_d1__U409":{ - "genref":"coreir.mul", - "genargs":{"width":["Int",16]} + "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "mul_d2__U411":{ + "mul_d0__U49":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d3__U413":{ + "mul_d1__U51":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d4__U415":{ + "mul_d2__U53":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U407.out","add_all__U417.in0"], - ["mul_d1__U409.out","add_all__U417.in1"], - ["add_all__U418.in0","add_all__U417.out"], - ["mul_d2__U411.out","add_all__U418.in1"], - ["add_all__U419.in0","add_all__U418.out"], - ["mul_d3__U413.out","add_all__U419.in1"], - ["add_all__U420.in0","add_all__U419.out"], - ["mul_d4__U415.out","add_all__U420.in1"], - ["add_all__U421.in0","add_all__U420.out"], - ["const_term_U416.out","add_all__U421.in1"], - ["self.out","add_all__U421.out"], - ["mul_d0__U407.in0","coeff_0_U406.out"], - ["mul_d1__U409.in0","coeff_1_U408.out"], - ["mul_d2__U411.in0","coeff_2_U410.out"], - ["mul_d3__U413.in0","coeff_3_U412.out"], - ["mul_d4__U415.in0","coeff_4_U414.out"], - ["self.d.0","mul_d0__U407.in1"], - ["self.d.1","mul_d1__U409.in1"], - ["self.d.2","mul_d2__U411.in1"], - ["self.d.3","mul_d3__U413.in1"], - ["self.d.4","mul_d4__U415.in1"] + ["mul_d0__U49.out","add_all__U55.in0"], + ["mul_d1__U51.out","add_all__U55.in1"], + ["add_all__U56.in0","add_all__U55.out"], + ["mul_d2__U53.out","add_all__U56.in1"], + ["add_all__U57.in0","add_all__U56.out"], + ["const_term_U54.out","add_all__U57.in1"], + ["self.out","add_all__U57.out"], + ["mul_d0__U49.in0","coeff_0_U48.out"], + ["mul_d1__U51.in0","coeff_1_U50.out"], + ["mul_d2__U53.in0","coeff_2_U52.out"], + ["self.d.0","mul_d0__U49.in1"], + ["self.d.1","mul_d1__U51.in1"], + ["self.d.2","mul_d2__U53.in1"] ] }, - "aff__U47":{ + "aff__U570":{ "type":["Record",[ ["out",["Array",16,"Bit"]], ["d",["Array",3,["Array",16,"BitIn"]]] ]], "instances":{ - "add_all__U55":{ + "add_all__U578":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U56":{ + "add_all__U579":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "add_all__U57":{ + "add_all__U580":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} }, - "coeff_0_U48":{ + "coeff_0_U571":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, - "coeff_1_U50":{ + "coeff_1_U573":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h001f"]} }, - "coeff_2_U52":{ + "coeff_2_U575":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "const_term_U54":{ + "const_term_U577":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "mul_d0__U49":{ + "mul_d0__U572":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d1__U51":{ + "mul_d1__U574":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} }, - "mul_d2__U53":{ + "mul_d2__U576":{ "genref":"coreir.mul", "genargs":{"width":["Int",16]} } }, "connections":[ - ["mul_d0__U49.out","add_all__U55.in0"], - ["mul_d1__U51.out","add_all__U55.in1"], - ["add_all__U56.in0","add_all__U55.out"], - ["mul_d2__U53.out","add_all__U56.in1"], - ["add_all__U57.in0","add_all__U56.out"], - ["const_term_U54.out","add_all__U57.in1"], - ["self.out","add_all__U57.out"], - ["mul_d0__U49.in0","coeff_0_U48.out"], - ["mul_d1__U51.in0","coeff_1_U50.out"], - ["mul_d2__U53.in0","coeff_2_U52.out"], - ["self.d.0","mul_d0__U49.in1"], - ["self.d.1","mul_d1__U51.in1"], - ["self.d.2","mul_d2__U53.in1"] + ["mul_d0__U572.out","add_all__U578.in0"], + ["mul_d1__U574.out","add_all__U578.in1"], + ["add_all__U579.in0","add_all__U578.out"], + ["mul_d2__U576.out","add_all__U579.in1"], + ["add_all__U580.in0","add_all__U579.out"], + ["const_term_U577.out","add_all__U580.in1"], + ["self.out","add_all__U580.out"], + ["mul_d0__U572.in0","coeff_0_U571.out"], + ["mul_d1__U574.in0","coeff_1_U573.out"], + ["mul_d2__U576.in0","coeff_2_U575.out"], + ["self.d.0","mul_d0__U572.in1"], + ["self.d.1","mul_d1__U574.in1"], + ["self.d.2","mul_d2__U576.in1"] ] }, "aff__U593":{ @@ -6747,15 +6747,15 @@ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",3,["Array",16,"Bit"]]] + ["d",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U173":{ + "_U179":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U174":{ + "_U180":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} @@ -6772,10 +6772,16 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U175":{ + "d_0_am__U181":{ + "modref":"corebit.and" + }, + "d_0_am__U182":{ "modref":"corebit.and" }, - "d_0_am__U176":{ + "d_0_am__U183":{ + "modref":"corebit.and" + }, + "d_0_am__U184":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -6809,7 +6815,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U177":{ + "d_1_am__U185":{ + "modref":"corebit.and" + }, + "d_1_am__U186":{ + "modref":"corebit.and" + }, + "d_1_am__U187":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -6823,7 +6835,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001d"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_1_min":{ "genref":"coreir.const", @@ -6843,6 +6855,12 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_2_am__U188":{ + "modref":"corebit.and" + }, + "d_2_am__U189":{ + "modref":"corebit.and" + }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -6854,7 +6872,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001d"]} + "modargs":{"value":[["BitVector",16],"16'h0002"]} }, "d_2_min":{ "genref":"coreir.const", @@ -6874,6 +6892,71 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "d_3_am__U190":{ + "modref":"corebit.and" + }, + "d_3_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_3_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_3_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "d_3_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_3_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_3_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_3_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_4_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_4_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_4_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "d_4_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_4_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_4_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -6888,29 +6971,39 @@ } }, "connections":[ - ["d_0_inc.in1","_U173.out"], - ["d_1_inc.in1","_U173.out"], - ["d_2_inc.in1","_U173.out"], - ["inc_time.in1","_U173.out"], - ["cmp_time.in1","_U174.out"], + ["d_0_inc.in1","_U179.out"], + ["d_1_inc.in1","_U179.out"], + ["d_2_inc.in1","_U179.out"], + ["d_3_inc.in1","_U179.out"], + ["d_4_inc.in1","_U179.out"], + ["inc_time.in1","_U179.out"], + ["cmp_time.in1","_U180.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], + ["d_3_reg.out","affine_func.d.3"], + ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], + ["d_3_reg.en","cmp_time.out"], + ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U175.in0"], - ["d_1_at_max.out","d_0_am__U175.in1"], - ["d_0_am__U176.in0","d_0_am__U175.out"], - ["d_2_at_max.out","d_0_am__U176.in1"], - ["d_0_next_value.sel","d_0_am__U176.out"], + ["true.out","d_0_am__U181.in0"], + ["d_1_at_max.out","d_0_am__U181.in1"], + ["d_0_am__U182.in0","d_0_am__U181.out"], + ["d_2_at_max.out","d_0_am__U182.in1"], + ["d_0_am__U183.in0","d_0_am__U182.out"], + ["d_3_at_max.out","d_0_am__U183.in1"], + ["d_0_am__U184.in0","d_0_am__U183.out"], + ["d_4_at_max.out","d_0_am__U184.in1"], + ["d_0_next_value.sel","d_0_am__U184.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -6922,9 +7015,13 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U177.in0"], - ["d_2_at_max.out","d_1_am__U177.in1"], - ["d_1_next_value.sel","d_1_am__U177.out"], + ["true.out","d_1_am__U185.in0"], + ["d_2_at_max.out","d_1_am__U185.in1"], + ["d_1_am__U186.in0","d_1_am__U185.out"], + ["d_3_at_max.out","d_1_am__U186.in1"], + ["d_1_am__U187.in0","d_1_am__U186.out"], + ["d_4_at_max.out","d_1_am__U187.in1"], + ["d_1_next_value.sel","d_1_am__U187.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -6936,6 +7033,11 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], + ["true.out","d_2_am__U188.in0"], + ["d_3_at_max.out","d_2_am__U188.in1"], + ["d_2_am__U189.in0","d_2_am__U188.out"], + ["d_4_at_max.out","d_2_am__U189.in1"], + ["d_2_next_value.sel","d_2_am__U189.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -6945,9 +7047,34 @@ ["d_2_reg.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg.in","d_2_next_value.out"], - ["true.out","d_2_next_value.sel"], ["self.clk","d_2_reg.clk"], - ["self.d.2","d_2_reg.out"] + ["self.d.2","d_2_reg.out"], + ["true.out","d_3_am__U190.in0"], + ["d_4_at_max.out","d_3_am__U190.in1"], + ["d_3_next_value.sel","d_3_am__U190.out"], + ["d_3_reg.out","d_3_at_max.in0"], + ["d_3_max.out","d_3_at_max.in1"], + ["d_3_next_value_at_max.sel","d_3_at_max.out"], + ["d_3_reg.out","d_3_inc.in0"], + ["d_3_next_value_at_max.in0","d_3_inc.out"], + ["d_3_next_value_at_max.in1","d_3_min.out"], + ["d_3_reg.out","d_3_next_value.in0"], + ["d_3_next_value_at_max.out","d_3_next_value.in1"], + ["d_3_reg.in","d_3_next_value.out"], + ["self.clk","d_3_reg.clk"], + ["self.d.3","d_3_reg.out"], + ["d_4_reg.out","d_4_at_max.in0"], + ["d_4_max.out","d_4_at_max.in1"], + ["d_4_next_value_at_max.sel","d_4_at_max.out"], + ["d_4_reg.out","d_4_inc.in0"], + ["d_4_next_value_at_max.in0","d_4_inc.out"], + ["d_4_next_value_at_max.in1","d_4_min.out"], + ["d_4_reg.out","d_4_next_value.in0"], + ["d_4_next_value_at_max.out","d_4_next_value.in1"], + ["d_4_reg.in","d_4_next_value.out"], + ["true.out","d_4_next_value.sel"], + ["self.clk","d_4_reg.clk"], + ["self.d.4","d_4_reg.out"] ] }, "affine_controller__U1720":{ @@ -7284,25 +7411,25 @@ ["self.d.4","d_4_reg.out"] ] }, - "affine_controller__U184":{ + "affine_controller__U1908":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",16,"Bit"]]] + ["d",["Array",3,["Array",16,"Bit"]]] ]], "instances":{ - "_U202":{ + "_U1920":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U203":{ + "_U1921":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U185" + "modref":"global.aff__U1909" }, "cmp_time":{ "genref":"coreir.eq", @@ -7313,16 +7440,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U204":{ - "modref":"corebit.and" - }, - "d_0_am__U205":{ - "modref":"corebit.and" - }, - "d_0_am__U206":{ + "d_0_am__U1922":{ "modref":"corebit.and" }, - "d_0_am__U207":{ + "d_0_am__U1923":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -7356,13 +7477,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U208":{ - "modref":"corebit.and" - }, - "d_1_am__U209":{ - "modref":"corebit.and" - }, - "d_1_am__U210":{ + "d_1_am__U1924":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -7376,7 +7491,7 @@ "d_1_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001b"]} }, "d_1_min":{ "genref":"coreir.const", @@ -7396,12 +7511,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U211":{ - "modref":"corebit.and" - }, - "d_2_am__U212":{ - "modref":"corebit.and" - }, "d_2_at_max":{ "genref":"coreir.eq", "genargs":{"width":["Int",16]} @@ -7413,7 +7522,7 @@ "d_2_max":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0002"]} + "modargs":{"value":[["BitVector",16],"16'h001b"]} }, "d_2_min":{ "genref":"coreir.const", @@ -7433,71 +7542,6 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_3_am__U213":{ - "modref":"corebit.and" - }, - "d_3_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_3_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_3_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0007"]} - }, - "d_3_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_3_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_3_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_3_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "d_4_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_4_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_4_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0007"]} - }, - "d_4_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_4_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_4_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, "inc_time":{ "genref":"coreir.add", "genargs":{"width":["Int",16]} @@ -7512,39 +7556,29 @@ } }, "connections":[ - ["d_0_inc.in1","_U202.out"], - ["d_1_inc.in1","_U202.out"], - ["d_2_inc.in1","_U202.out"], - ["d_3_inc.in1","_U202.out"], - ["d_4_inc.in1","_U202.out"], - ["inc_time.in1","_U202.out"], - ["cmp_time.in1","_U203.out"], + ["d_0_inc.in1","_U1920.out"], + ["d_1_inc.in1","_U1920.out"], + ["d_2_inc.in1","_U1920.out"], + ["inc_time.in1","_U1920.out"], + ["cmp_time.in1","_U1921.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], - ["d_3_reg.out","affine_func.d.3"], - ["d_4_reg.out","affine_func.d.4"], ["time_diff.in0","affine_func.out"], ["time_diff.out","cmp_time.in0"], ["d_0_reg.en","cmp_time.out"], ["d_1_reg.en","cmp_time.out"], ["d_2_reg.en","cmp_time.out"], - ["d_3_reg.en","cmp_time.out"], - ["d_4_reg.en","cmp_time.out"], ["self.valid","cmp_time.out"], ["self.clk","cycle_time.clk"], ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U204.in0"], - ["d_1_at_max.out","d_0_am__U204.in1"], - ["d_0_am__U205.in0","d_0_am__U204.out"], - ["d_2_at_max.out","d_0_am__U205.in1"], - ["d_0_am__U206.in0","d_0_am__U205.out"], - ["d_3_at_max.out","d_0_am__U206.in1"], - ["d_0_am__U207.in0","d_0_am__U206.out"], - ["d_4_at_max.out","d_0_am__U207.in1"], - ["d_0_next_value.sel","d_0_am__U207.out"], + ["true.out","d_0_am__U1922.in0"], + ["d_1_at_max.out","d_0_am__U1922.in1"], + ["d_0_am__U1923.in0","d_0_am__U1922.out"], + ["d_2_at_max.out","d_0_am__U1923.in1"], + ["d_0_next_value.sel","d_0_am__U1923.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7556,13 +7590,9 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U208.in0"], - ["d_2_at_max.out","d_1_am__U208.in1"], - ["d_1_am__U209.in0","d_1_am__U208.out"], - ["d_3_at_max.out","d_1_am__U209.in1"], - ["d_1_am__U210.in0","d_1_am__U209.out"], - ["d_4_at_max.out","d_1_am__U210.in1"], - ["d_1_next_value.sel","d_1_am__U210.out"], + ["true.out","d_1_am__U1924.in0"], + ["d_2_at_max.out","d_1_am__U1924.in1"], + ["d_1_next_value.sel","d_1_am__U1924.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -7574,11 +7604,6 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U211.in0"], - ["d_3_at_max.out","d_2_am__U211.in1"], - ["d_2_am__U212.in0","d_2_am__U211.out"], - ["d_4_at_max.out","d_2_am__U212.in1"], - ["d_2_next_value.sel","d_2_am__U212.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -7588,55 +7613,30 @@ ["d_2_reg.out","d_2_next_value.in0"], ["d_2_next_value_at_max.out","d_2_next_value.in1"], ["d_2_reg.in","d_2_next_value.out"], + ["true.out","d_2_next_value.sel"], ["self.clk","d_2_reg.clk"], - ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U213.in0"], - ["d_4_at_max.out","d_3_am__U213.in1"], - ["d_3_next_value.sel","d_3_am__U213.out"], - ["d_3_reg.out","d_3_at_max.in0"], - ["d_3_max.out","d_3_at_max.in1"], - ["d_3_next_value_at_max.sel","d_3_at_max.out"], - ["d_3_reg.out","d_3_inc.in0"], - ["d_3_next_value_at_max.in0","d_3_inc.out"], - ["d_3_next_value_at_max.in1","d_3_min.out"], - ["d_3_reg.out","d_3_next_value.in0"], - ["d_3_next_value_at_max.out","d_3_next_value.in1"], - ["d_3_reg.in","d_3_next_value.out"], - ["self.clk","d_3_reg.clk"], - ["self.d.3","d_3_reg.out"], - ["d_4_reg.out","d_4_at_max.in0"], - ["d_4_max.out","d_4_at_max.in1"], - ["d_4_next_value_at_max.sel","d_4_at_max.out"], - ["d_4_reg.out","d_4_inc.in0"], - ["d_4_next_value_at_max.in0","d_4_inc.out"], - ["d_4_next_value_at_max.in1","d_4_min.out"], - ["d_4_reg.out","d_4_next_value.in0"], - ["d_4_next_value_at_max.out","d_4_next_value.in1"], - ["d_4_reg.in","d_4_next_value.out"], - ["true.out","d_4_next_value.sel"], - ["self.clk","d_4_reg.clk"], - ["self.d.4","d_4_reg.out"] + ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U1908":{ + "affine_controller__U1955":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], ["d",["Array",3,["Array",16,"Bit"]]] ]], "instances":{ - "_U1920":{ + "_U1967":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U1921":{ + "_U1968":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U1909" + "modref":"global.aff__U1956" }, "cmp_time":{ "genref":"coreir.eq", @@ -7647,10 +7647,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U1922":{ + "d_0_am__U1969":{ "modref":"corebit.and" }, - "d_0_am__U1923":{ + "d_0_am__U1970":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -7684,7 +7684,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U1924":{ + "d_1_am__U1971":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -7763,11 +7763,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U1920.out"], - ["d_1_inc.in1","_U1920.out"], - ["d_2_inc.in1","_U1920.out"], - ["inc_time.in1","_U1920.out"], - ["cmp_time.in1","_U1921.out"], + ["d_0_inc.in1","_U1967.out"], + ["d_1_inc.in1","_U1967.out"], + ["d_2_inc.in1","_U1967.out"], + ["inc_time.in1","_U1967.out"], + ["cmp_time.in1","_U1968.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -7781,11 +7781,11 @@ ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U1922.in0"], - ["d_1_at_max.out","d_0_am__U1922.in1"], - ["d_0_am__U1923.in0","d_0_am__U1922.out"], - ["d_2_at_max.out","d_0_am__U1923.in1"], - ["d_0_next_value.sel","d_0_am__U1923.out"], + ["true.out","d_0_am__U1969.in0"], + ["d_1_at_max.out","d_0_am__U1969.in1"], + ["d_0_am__U1970.in0","d_0_am__U1969.out"], + ["d_2_at_max.out","d_0_am__U1970.in1"], + ["d_0_next_value.sel","d_0_am__U1970.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -7797,9 +7797,9 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U1924.in0"], - ["d_2_at_max.out","d_1_am__U1924.in1"], - ["d_1_next_value.sel","d_1_am__U1924.out"], + ["true.out","d_1_am__U1971.in0"], + ["d_2_at_max.out","d_1_am__U1971.in1"], + ["d_1_next_value.sel","d_1_am__U1971.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -7825,25 +7825,25 @@ ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U1955":{ + "affine_controller__U197":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], ["d",["Array",3,["Array",16,"Bit"]]] ]], "instances":{ - "_U1967":{ + "_U209":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U1968":{ + "_U210":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U1956" + "modref":"global.aff__U198" }, "cmp_time":{ "genref":"coreir.eq", @@ -7854,10 +7854,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U1969":{ + "d_0_am__U211":{ "modref":"corebit.and" }, - "d_0_am__U1970":{ + "d_0_am__U212":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -7891,7 +7891,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U1971":{ + "d_1_am__U213":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -7970,11 +7970,11 @@ } }, "connections":[ - ["d_0_inc.in1","_U1967.out"], - ["d_1_inc.in1","_U1967.out"], - ["d_2_inc.in1","_U1967.out"], - ["inc_time.in1","_U1967.out"], - ["cmp_time.in1","_U1968.out"], + ["d_0_inc.in1","_U209.out"], + ["d_1_inc.in1","_U209.out"], + ["d_2_inc.in1","_U209.out"], + ["inc_time.in1","_U209.out"], + ["cmp_time.in1","_U210.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -7988,11 +7988,11 @@ ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U1969.in0"], - ["d_1_at_max.out","d_0_am__U1969.in1"], - ["d_0_am__U1970.in0","d_0_am__U1969.out"], - ["d_2_at_max.out","d_0_am__U1970.in1"], - ["d_0_next_value.sel","d_0_am__U1970.out"], + ["true.out","d_0_am__U211.in0"], + ["d_1_at_max.out","d_0_am__U211.in1"], + ["d_0_am__U212.in0","d_0_am__U211.out"], + ["d_2_at_max.out","d_0_am__U212.in1"], + ["d_0_next_value.sel","d_0_am__U212.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -8004,9 +8004,9 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U1971.in0"], - ["d_2_at_max.out","d_1_am__U1971.in1"], - ["d_1_next_value.sel","d_1_am__U1971.out"], + ["true.out","d_1_am__U213.in0"], + ["d_2_at_max.out","d_1_am__U213.in1"], + ["d_1_next_value.sel","d_1_am__U213.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -10931,231 +10931,24 @@ ] }, "affine_controller__U381":{ - "type":["Record",[ - ["clk",["Named","coreir.clkIn"]], - ["valid","Bit"], - ["d",["Array",3,["Array",16,"Bit"]]] - ]], - "instances":{ - "_U393":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0001"]} - }, - "_U394":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "affine_func":{ - "modref":"global.aff__U382" - }, - "cmp_time":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "cycle_time":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "d_0_am__U395":{ - "modref":"corebit.and" - }, - "d_0_am__U396":{ - "modref":"corebit.and" - }, - "d_0_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_0_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_0_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_0_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_0_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_0_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_0_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "d_1_am__U397":{ - "modref":"corebit.and" - }, - "d_1_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_1_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_1_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} - }, - "d_1_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_1_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_1_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_1_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "d_2_at_max":{ - "genref":"coreir.eq", - "genargs":{"width":["Int",16]} - }, - "d_2_inc":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "d_2_max":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h001b"]} - }, - "d_2_min":{ - "genref":"coreir.const", - "genargs":{"width":["Int",16]}, - "modargs":{"value":[["BitVector",16],"16'h0000"]} - }, - "d_2_next_value":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_2_next_value_at_max":{ - "genref":"coreir.mux", - "genargs":{"width":["Int",16]} - }, - "d_2_reg":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "inc_time":{ - "genref":"coreir.add", - "genargs":{"width":["Int",16]} - }, - "time_diff":{ - "genref":"coreir.sub", - "genargs":{"width":["Int",16]} - }, - "true":{ - "modref":"corebit.const", - "modargs":{"value":["Bool",true]} - } - }, - "connections":[ - ["d_0_inc.in1","_U393.out"], - ["d_1_inc.in1","_U393.out"], - ["d_2_inc.in1","_U393.out"], - ["inc_time.in1","_U393.out"], - ["cmp_time.in1","_U394.out"], - ["d_0_reg.out","affine_func.d.0"], - ["d_1_reg.out","affine_func.d.1"], - ["d_2_reg.out","affine_func.d.2"], - ["time_diff.in0","affine_func.out"], - ["time_diff.out","cmp_time.in0"], - ["d_0_reg.en","cmp_time.out"], - ["d_1_reg.en","cmp_time.out"], - ["d_2_reg.en","cmp_time.out"], - ["self.valid","cmp_time.out"], - ["self.clk","cycle_time.clk"], - ["inc_time.out","cycle_time.in"], - ["inc_time.in0","cycle_time.out"], - ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U395.in0"], - ["d_1_at_max.out","d_0_am__U395.in1"], - ["d_0_am__U396.in0","d_0_am__U395.out"], - ["d_2_at_max.out","d_0_am__U396.in1"], - ["d_0_next_value.sel","d_0_am__U396.out"], - ["d_0_reg.out","d_0_at_max.in0"], - ["d_0_max.out","d_0_at_max.in1"], - ["d_0_next_value_at_max.sel","d_0_at_max.out"], - ["d_0_reg.out","d_0_inc.in0"], - ["d_0_next_value_at_max.in0","d_0_inc.out"], - ["d_0_next_value_at_max.in1","d_0_min.out"], - ["d_0_reg.out","d_0_next_value.in0"], - ["d_0_next_value_at_max.out","d_0_next_value.in1"], - ["d_0_reg.in","d_0_next_value.out"], - ["self.clk","d_0_reg.clk"], - ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U397.in0"], - ["d_2_at_max.out","d_1_am__U397.in1"], - ["d_1_next_value.sel","d_1_am__U397.out"], - ["d_1_reg.out","d_1_at_max.in0"], - ["d_1_max.out","d_1_at_max.in1"], - ["d_1_next_value_at_max.sel","d_1_at_max.out"], - ["d_1_reg.out","d_1_inc.in0"], - ["d_1_next_value_at_max.in0","d_1_inc.out"], - ["d_1_next_value_at_max.in1","d_1_min.out"], - ["d_1_reg.out","d_1_next_value.in0"], - ["d_1_next_value_at_max.out","d_1_next_value.in1"], - ["d_1_reg.in","d_1_next_value.out"], - ["self.clk","d_1_reg.clk"], - ["self.d.1","d_1_reg.out"], - ["d_2_reg.out","d_2_at_max.in0"], - ["d_2_max.out","d_2_at_max.in1"], - ["d_2_next_value_at_max.sel","d_2_at_max.out"], - ["d_2_reg.out","d_2_inc.in0"], - ["d_2_next_value_at_max.in0","d_2_inc.out"], - ["d_2_next_value_at_max.in1","d_2_min.out"], - ["d_2_reg.out","d_2_next_value.in0"], - ["d_2_next_value_at_max.out","d_2_next_value.in1"], - ["d_2_reg.in","d_2_next_value.out"], - ["true.out","d_2_next_value.sel"], - ["self.clk","d_2_reg.clk"], - ["self.d.2","d_2_reg.out"] - ] - }, - "affine_controller__U404":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], ["d",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U422":{ + "_U399":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U423":{ + "_U400":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U405" + "modref":"global.aff__U382" }, "cmp_time":{ "genref":"coreir.eq", @@ -11166,16 +10959,16 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U424":{ + "d_0_am__U401":{ "modref":"corebit.and" }, - "d_0_am__U425":{ + "d_0_am__U402":{ "modref":"corebit.and" }, - "d_0_am__U426":{ + "d_0_am__U403":{ "modref":"corebit.and" }, - "d_0_am__U427":{ + "d_0_am__U404":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -11209,13 +11002,13 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_1_am__U428":{ + "d_1_am__U405":{ "modref":"corebit.and" }, - "d_1_am__U429":{ + "d_1_am__U406":{ "modref":"corebit.and" }, - "d_1_am__U430":{ + "d_1_am__U407":{ "modref":"corebit.and" }, "d_1_at_max":{ @@ -11249,10 +11042,10 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_2_am__U431":{ + "d_2_am__U408":{ "modref":"corebit.and" }, - "d_2_am__U432":{ + "d_2_am__U409":{ "modref":"corebit.and" }, "d_2_at_max":{ @@ -11286,7 +11079,7 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_3_am__U433":{ + "d_3_am__U410":{ "modref":"corebit.and" }, "d_3_at_max":{ @@ -11365,13 +11158,13 @@ } }, "connections":[ - ["d_0_inc.in1","_U422.out"], - ["d_1_inc.in1","_U422.out"], - ["d_2_inc.in1","_U422.out"], - ["d_3_inc.in1","_U422.out"], - ["d_4_inc.in1","_U422.out"], - ["inc_time.in1","_U422.out"], - ["cmp_time.in1","_U423.out"], + ["d_0_inc.in1","_U399.out"], + ["d_1_inc.in1","_U399.out"], + ["d_2_inc.in1","_U399.out"], + ["d_3_inc.in1","_U399.out"], + ["d_4_inc.in1","_U399.out"], + ["inc_time.in1","_U399.out"], + ["cmp_time.in1","_U400.out"], ["d_0_reg.out","affine_func.d.0"], ["d_1_reg.out","affine_func.d.1"], ["d_2_reg.out","affine_func.d.2"], @@ -11389,15 +11182,15 @@ ["inc_time.out","cycle_time.in"], ["inc_time.in0","cycle_time.out"], ["time_diff.in1","cycle_time.out"], - ["true.out","d_0_am__U424.in0"], - ["d_1_at_max.out","d_0_am__U424.in1"], - ["d_0_am__U425.in0","d_0_am__U424.out"], - ["d_2_at_max.out","d_0_am__U425.in1"], - ["d_0_am__U426.in0","d_0_am__U425.out"], - ["d_3_at_max.out","d_0_am__U426.in1"], - ["d_0_am__U427.in0","d_0_am__U426.out"], - ["d_4_at_max.out","d_0_am__U427.in1"], - ["d_0_next_value.sel","d_0_am__U427.out"], + ["true.out","d_0_am__U401.in0"], + ["d_1_at_max.out","d_0_am__U401.in1"], + ["d_0_am__U402.in0","d_0_am__U401.out"], + ["d_2_at_max.out","d_0_am__U402.in1"], + ["d_0_am__U403.in0","d_0_am__U402.out"], + ["d_3_at_max.out","d_0_am__U403.in1"], + ["d_0_am__U404.in0","d_0_am__U403.out"], + ["d_4_at_max.out","d_0_am__U404.in1"], + ["d_0_next_value.sel","d_0_am__U404.out"], ["d_0_reg.out","d_0_at_max.in0"], ["d_0_max.out","d_0_at_max.in1"], ["d_0_next_value_at_max.sel","d_0_at_max.out"], @@ -11409,13 +11202,13 @@ ["d_0_reg.in","d_0_next_value.out"], ["self.clk","d_0_reg.clk"], ["self.d.0","d_0_reg.out"], - ["true.out","d_1_am__U428.in0"], - ["d_2_at_max.out","d_1_am__U428.in1"], - ["d_1_am__U429.in0","d_1_am__U428.out"], - ["d_3_at_max.out","d_1_am__U429.in1"], - ["d_1_am__U430.in0","d_1_am__U429.out"], - ["d_4_at_max.out","d_1_am__U430.in1"], - ["d_1_next_value.sel","d_1_am__U430.out"], + ["true.out","d_1_am__U405.in0"], + ["d_2_at_max.out","d_1_am__U405.in1"], + ["d_1_am__U406.in0","d_1_am__U405.out"], + ["d_3_at_max.out","d_1_am__U406.in1"], + ["d_1_am__U407.in0","d_1_am__U406.out"], + ["d_4_at_max.out","d_1_am__U407.in1"], + ["d_1_next_value.sel","d_1_am__U407.out"], ["d_1_reg.out","d_1_at_max.in0"], ["d_1_max.out","d_1_at_max.in1"], ["d_1_next_value_at_max.sel","d_1_at_max.out"], @@ -11427,11 +11220,11 @@ ["d_1_reg.in","d_1_next_value.out"], ["self.clk","d_1_reg.clk"], ["self.d.1","d_1_reg.out"], - ["true.out","d_2_am__U431.in0"], - ["d_3_at_max.out","d_2_am__U431.in1"], - ["d_2_am__U432.in0","d_2_am__U431.out"], - ["d_4_at_max.out","d_2_am__U432.in1"], - ["d_2_next_value.sel","d_2_am__U432.out"], + ["true.out","d_2_am__U408.in0"], + ["d_3_at_max.out","d_2_am__U408.in1"], + ["d_2_am__U409.in0","d_2_am__U408.out"], + ["d_4_at_max.out","d_2_am__U409.in1"], + ["d_2_next_value.sel","d_2_am__U409.out"], ["d_2_reg.out","d_2_at_max.in0"], ["d_2_max.out","d_2_at_max.in1"], ["d_2_next_value_at_max.sel","d_2_at_max.out"], @@ -11443,9 +11236,9 @@ ["d_2_reg.in","d_2_next_value.out"], ["self.clk","d_2_reg.clk"], ["self.d.2","d_2_reg.out"], - ["true.out","d_3_am__U433.in0"], - ["d_4_at_max.out","d_3_am__U433.in1"], - ["d_3_next_value.sel","d_3_am__U433.out"], + ["true.out","d_3_am__U410.in0"], + ["d_4_at_max.out","d_3_am__U410.in1"], + ["d_3_next_value.sel","d_3_am__U410.out"], ["d_3_reg.out","d_3_at_max.in0"], ["d_3_max.out","d_3_at_max.in1"], ["d_3_next_value_at_max.sel","d_3_at_max.out"], @@ -11678,25 +11471,25 @@ ["self.d.2","d_2_reg.out"] ] }, - "affine_controller__U592":{ + "affine_controller__U569":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["valid","Bit"], - ["d",["Array",5,["Array",16,"Bit"]]] + ["d",["Array",3,["Array",16,"Bit"]]] ]], "instances":{ - "_U610":{ + "_U581":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0001"]} }, - "_U611":{ + "_U582":{ "genref":"coreir.const", "genargs":{"width":["Int",16]}, "modargs":{"value":[["BitVector",16],"16'h0000"]} }, "affine_func":{ - "modref":"global.aff__U593" + "modref":"global.aff__U570" }, "cmp_time":{ "genref":"coreir.eq", @@ -11707,16 +11500,223 @@ "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "d_0_am__U612":{ - "modref":"corebit.and" - }, - "d_0_am__U613":{ + "d_0_am__U583":{ "modref":"corebit.and" }, - "d_0_am__U614":{ - "modref":"corebit.and" - }, - "d_0_am__U615":{ + "d_0_am__U584":{ + "modref":"corebit.and" + }, + "d_0_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_0_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_0_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_0_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_0_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_0_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_0_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_1_am__U585":{ + "modref":"corebit.and" + }, + "d_1_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_1_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_1_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "d_1_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_1_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_1_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_1_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_2_at_max":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "d_2_inc":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "d_2_max":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "d_2_min":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "d_2_next_value":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_2_next_value_at_max":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "d_2_reg":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",true], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "inc_time":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "time_diff":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "true":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + } + }, + "connections":[ + ["d_0_inc.in1","_U581.out"], + ["d_1_inc.in1","_U581.out"], + ["d_2_inc.in1","_U581.out"], + ["inc_time.in1","_U581.out"], + ["cmp_time.in1","_U582.out"], + ["d_0_reg.out","affine_func.d.0"], + ["d_1_reg.out","affine_func.d.1"], + ["d_2_reg.out","affine_func.d.2"], + ["time_diff.in0","affine_func.out"], + ["time_diff.out","cmp_time.in0"], + ["d_0_reg.en","cmp_time.out"], + ["d_1_reg.en","cmp_time.out"], + ["d_2_reg.en","cmp_time.out"], + ["self.valid","cmp_time.out"], + ["self.clk","cycle_time.clk"], + ["inc_time.out","cycle_time.in"], + ["inc_time.in0","cycle_time.out"], + ["time_diff.in1","cycle_time.out"], + ["true.out","d_0_am__U583.in0"], + ["d_1_at_max.out","d_0_am__U583.in1"], + ["d_0_am__U584.in0","d_0_am__U583.out"], + ["d_2_at_max.out","d_0_am__U584.in1"], + ["d_0_next_value.sel","d_0_am__U584.out"], + ["d_0_reg.out","d_0_at_max.in0"], + ["d_0_max.out","d_0_at_max.in1"], + ["d_0_next_value_at_max.sel","d_0_at_max.out"], + ["d_0_reg.out","d_0_inc.in0"], + ["d_0_next_value_at_max.in0","d_0_inc.out"], + ["d_0_next_value_at_max.in1","d_0_min.out"], + ["d_0_reg.out","d_0_next_value.in0"], + ["d_0_next_value_at_max.out","d_0_next_value.in1"], + ["d_0_reg.in","d_0_next_value.out"], + ["self.clk","d_0_reg.clk"], + ["self.d.0","d_0_reg.out"], + ["true.out","d_1_am__U585.in0"], + ["d_2_at_max.out","d_1_am__U585.in1"], + ["d_1_next_value.sel","d_1_am__U585.out"], + ["d_1_reg.out","d_1_at_max.in0"], + ["d_1_max.out","d_1_at_max.in1"], + ["d_1_next_value_at_max.sel","d_1_at_max.out"], + ["d_1_reg.out","d_1_inc.in0"], + ["d_1_next_value_at_max.in0","d_1_inc.out"], + ["d_1_next_value_at_max.in1","d_1_min.out"], + ["d_1_reg.out","d_1_next_value.in0"], + ["d_1_next_value_at_max.out","d_1_next_value.in1"], + ["d_1_reg.in","d_1_next_value.out"], + ["self.clk","d_1_reg.clk"], + ["self.d.1","d_1_reg.out"], + ["d_2_reg.out","d_2_at_max.in0"], + ["d_2_max.out","d_2_at_max.in1"], + ["d_2_next_value_at_max.sel","d_2_at_max.out"], + ["d_2_reg.out","d_2_inc.in0"], + ["d_2_next_value_at_max.in0","d_2_inc.out"], + ["d_2_next_value_at_max.in1","d_2_min.out"], + ["d_2_reg.out","d_2_next_value.in0"], + ["d_2_next_value_at_max.out","d_2_next_value.in1"], + ["d_2_reg.in","d_2_next_value.out"], + ["true.out","d_2_next_value.sel"], + ["self.clk","d_2_reg.clk"], + ["self.d.2","d_2_reg.out"] + ] + }, + "affine_controller__U592":{ + "type":["Record",[ + ["clk",["Named","coreir.clkIn"]], + ["valid","Bit"], + ["d",["Array",5,["Array",16,"Bit"]]] + ]], + "instances":{ + "_U610":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "_U611":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "affine_func":{ + "modref":"global.aff__U593" + }, + "cmp_time":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "cycle_time":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "d_0_am__U612":{ + "modref":"corebit.and" + }, + "d_0_am__U613":{ + "modref":"corebit.and" + }, + "d_0_am__U614":{ + "modref":"corebit.and" + }, + "d_0_am__U615":{ "modref":"corebit.and" }, "d_0_at_max":{ @@ -19059,973 +19059,973 @@ ["self.out.2","_U2283.out"] ] }, - "array_delay_U441":{ + "array_delay_U418":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U442":{ + "_U419":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U443":{ + "_U420":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U444":{ + "_U421":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U445":{ + "_U422":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U446":{ + "_U423":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U442.clk"], - ["self.in.0","_U442.in"], - ["self.out.0","_U442.out"], - ["self.clk","_U443.clk"], - ["self.in.1","_U443.in"], - ["self.out.1","_U443.out"], - ["self.clk","_U444.clk"], - ["self.in.2","_U444.in"], - ["self.out.2","_U444.out"], - ["self.clk","_U445.clk"], - ["self.in.3","_U445.in"], - ["self.out.3","_U445.out"], - ["self.clk","_U446.clk"], - ["self.in.4","_U446.in"], - ["self.out.4","_U446.out"] + ["self.clk","_U419.clk"], + ["self.in.0","_U419.in"], + ["self.out.0","_U419.out"], + ["self.clk","_U420.clk"], + ["self.in.1","_U420.in"], + ["self.out.1","_U420.out"], + ["self.clk","_U421.clk"], + ["self.in.2","_U421.in"], + ["self.out.2","_U421.out"], + ["self.clk","_U422.clk"], + ["self.in.3","_U422.in"], + ["self.out.3","_U422.out"], + ["self.clk","_U423.clk"], + ["self.in.4","_U423.in"], + ["self.out.4","_U423.out"] ] }, - "array_delay_U448":{ + "array_delay_U425":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U449":{ + "_U426":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U450":{ + "_U427":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U451":{ + "_U428":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U452":{ + "_U429":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U453":{ + "_U430":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U449.clk"], - ["self.in.0","_U449.in"], - ["self.out.0","_U449.out"], - ["self.clk","_U450.clk"], - ["self.in.1","_U450.in"], - ["self.out.1","_U450.out"], - ["self.clk","_U451.clk"], - ["self.in.2","_U451.in"], - ["self.out.2","_U451.out"], - ["self.clk","_U452.clk"], - ["self.in.3","_U452.in"], - ["self.out.3","_U452.out"], - ["self.clk","_U453.clk"], - ["self.in.4","_U453.in"], - ["self.out.4","_U453.out"] + ["self.clk","_U426.clk"], + ["self.in.0","_U426.in"], + ["self.out.0","_U426.out"], + ["self.clk","_U427.clk"], + ["self.in.1","_U427.in"], + ["self.out.1","_U427.out"], + ["self.clk","_U428.clk"], + ["self.in.2","_U428.in"], + ["self.out.2","_U428.out"], + ["self.clk","_U429.clk"], + ["self.in.3","_U429.in"], + ["self.out.3","_U429.out"], + ["self.clk","_U430.clk"], + ["self.in.4","_U430.in"], + ["self.out.4","_U430.out"] ] }, - "array_delay_U474":{ + "array_delay_U451":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U475":{ + "_U452":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U476":{ + "_U453":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U477":{ + "_U454":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U478":{ + "_U455":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U479":{ + "_U456":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U475.clk"], - ["self.in.0","_U475.in"], - ["self.out.0","_U475.out"], - ["self.clk","_U476.clk"], - ["self.in.1","_U476.in"], - ["self.out.1","_U476.out"], - ["self.clk","_U477.clk"], - ["self.in.2","_U477.in"], - ["self.out.2","_U477.out"], - ["self.clk","_U478.clk"], - ["self.in.3","_U478.in"], - ["self.out.3","_U478.out"], - ["self.clk","_U479.clk"], - ["self.in.4","_U479.in"], - ["self.out.4","_U479.out"] + ["self.clk","_U452.clk"], + ["self.in.0","_U452.in"], + ["self.out.0","_U452.out"], + ["self.clk","_U453.clk"], + ["self.in.1","_U453.in"], + ["self.out.1","_U453.out"], + ["self.clk","_U454.clk"], + ["self.in.2","_U454.in"], + ["self.out.2","_U454.out"], + ["self.clk","_U455.clk"], + ["self.in.3","_U455.in"], + ["self.out.3","_U455.out"], + ["self.clk","_U456.clk"], + ["self.in.4","_U456.in"], + ["self.out.4","_U456.out"] ] }, - "array_delay_U481":{ + "array_delay_U458":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U482":{ + "_U459":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U483":{ + "_U460":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U484":{ + "_U461":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U485":{ + "_U462":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U486":{ + "_U463":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U482.clk"], - ["self.in.0","_U482.in"], - ["self.out.0","_U482.out"], - ["self.clk","_U483.clk"], - ["self.in.1","_U483.in"], - ["self.out.1","_U483.out"], - ["self.clk","_U484.clk"], - ["self.in.2","_U484.in"], - ["self.out.2","_U484.out"], - ["self.clk","_U485.clk"], - ["self.in.3","_U485.in"], - ["self.out.3","_U485.out"], - ["self.clk","_U486.clk"], - ["self.in.4","_U486.in"], - ["self.out.4","_U486.out"] + ["self.clk","_U459.clk"], + ["self.in.0","_U459.in"], + ["self.out.0","_U459.out"], + ["self.clk","_U460.clk"], + ["self.in.1","_U460.in"], + ["self.out.1","_U460.out"], + ["self.clk","_U461.clk"], + ["self.in.2","_U461.in"], + ["self.out.2","_U461.out"], + ["self.clk","_U462.clk"], + ["self.in.3","_U462.in"], + ["self.out.3","_U462.out"], + ["self.clk","_U463.clk"], + ["self.in.4","_U463.in"], + ["self.out.4","_U463.out"] ] }, - "array_delay_U488":{ + "array_delay_U465":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U489":{ + "_U466":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U490":{ + "_U467":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U491":{ + "_U468":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U492":{ + "_U469":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U493":{ + "_U470":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U489.clk"], - ["self.in.0","_U489.in"], - ["self.out.0","_U489.out"], - ["self.clk","_U490.clk"], - ["self.in.1","_U490.in"], - ["self.out.1","_U490.out"], - ["self.clk","_U491.clk"], - ["self.in.2","_U491.in"], - ["self.out.2","_U491.out"], - ["self.clk","_U492.clk"], - ["self.in.3","_U492.in"], - ["self.out.3","_U492.out"], - ["self.clk","_U493.clk"], - ["self.in.4","_U493.in"], - ["self.out.4","_U493.out"] + ["self.clk","_U466.clk"], + ["self.in.0","_U466.in"], + ["self.out.0","_U466.out"], + ["self.clk","_U467.clk"], + ["self.in.1","_U467.in"], + ["self.out.1","_U467.out"], + ["self.clk","_U468.clk"], + ["self.in.2","_U468.in"], + ["self.out.2","_U468.out"], + ["self.clk","_U469.clk"], + ["self.in.3","_U469.in"], + ["self.out.3","_U469.out"], + ["self.clk","_U470.clk"], + ["self.in.4","_U470.in"], + ["self.out.4","_U470.out"] ] }, - "array_delay_U495":{ + "array_delay_U472":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U496":{ + "_U473":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U497":{ + "_U474":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U498":{ + "_U475":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U499":{ + "_U476":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U500":{ + "_U477":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U496.clk"], - ["self.in.0","_U496.in"], - ["self.out.0","_U496.out"], - ["self.clk","_U497.clk"], - ["self.in.1","_U497.in"], - ["self.out.1","_U497.out"], - ["self.clk","_U498.clk"], - ["self.in.2","_U498.in"], - ["self.out.2","_U498.out"], - ["self.clk","_U499.clk"], - ["self.in.3","_U499.in"], - ["self.out.3","_U499.out"], - ["self.clk","_U500.clk"], - ["self.in.4","_U500.in"], - ["self.out.4","_U500.out"] + ["self.clk","_U473.clk"], + ["self.in.0","_U473.in"], + ["self.out.0","_U473.out"], + ["self.clk","_U474.clk"], + ["self.in.1","_U474.in"], + ["self.out.1","_U474.out"], + ["self.clk","_U475.clk"], + ["self.in.2","_U475.in"], + ["self.out.2","_U475.out"], + ["self.clk","_U476.clk"], + ["self.in.3","_U476.in"], + ["self.out.3","_U476.out"], + ["self.clk","_U477.clk"], + ["self.in.4","_U477.in"], + ["self.out.4","_U477.out"] ] }, - "array_delay_U502":{ + "array_delay_U479":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U503":{ + "_U480":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U504":{ + "_U481":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U505":{ + "_U482":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U506":{ + "_U483":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U507":{ + "_U484":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U503.clk"], - ["self.in.0","_U503.in"], - ["self.out.0","_U503.out"], - ["self.clk","_U504.clk"], - ["self.in.1","_U504.in"], - ["self.out.1","_U504.out"], - ["self.clk","_U505.clk"], - ["self.in.2","_U505.in"], - ["self.out.2","_U505.out"], - ["self.clk","_U506.clk"], - ["self.in.3","_U506.in"], - ["self.out.3","_U506.out"], - ["self.clk","_U507.clk"], - ["self.in.4","_U507.in"], - ["self.out.4","_U507.out"] + ["self.clk","_U480.clk"], + ["self.in.0","_U480.in"], + ["self.out.0","_U480.out"], + ["self.clk","_U481.clk"], + ["self.in.1","_U481.in"], + ["self.out.1","_U481.out"], + ["self.clk","_U482.clk"], + ["self.in.2","_U482.in"], + ["self.out.2","_U482.out"], + ["self.clk","_U483.clk"], + ["self.in.3","_U483.in"], + ["self.out.3","_U483.out"], + ["self.clk","_U484.clk"], + ["self.in.4","_U484.in"], + ["self.out.4","_U484.out"] ] }, - "array_delay_U509":{ + "array_delay_U486":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U510":{ + "_U487":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U511":{ + "_U488":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U512":{ + "_U489":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U513":{ + "_U490":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U514":{ + "_U491":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U510.clk"], - ["self.in.0","_U510.in"], - ["self.out.0","_U510.out"], - ["self.clk","_U511.clk"], - ["self.in.1","_U511.in"], - ["self.out.1","_U511.out"], - ["self.clk","_U512.clk"], - ["self.in.2","_U512.in"], - ["self.out.2","_U512.out"], - ["self.clk","_U513.clk"], - ["self.in.3","_U513.in"], - ["self.out.3","_U513.out"], - ["self.clk","_U514.clk"], - ["self.in.4","_U514.in"], - ["self.out.4","_U514.out"] + ["self.clk","_U487.clk"], + ["self.in.0","_U487.in"], + ["self.out.0","_U487.out"], + ["self.clk","_U488.clk"], + ["self.in.1","_U488.in"], + ["self.out.1","_U488.out"], + ["self.clk","_U489.clk"], + ["self.in.2","_U489.in"], + ["self.out.2","_U489.out"], + ["self.clk","_U490.clk"], + ["self.in.3","_U490.in"], + ["self.out.3","_U490.out"], + ["self.clk","_U491.clk"], + ["self.in.4","_U491.in"], + ["self.out.4","_U491.out"] ] }, - "array_delay_U516":{ + "array_delay_U493":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U517":{ + "_U494":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U518":{ + "_U495":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U519":{ + "_U496":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U520":{ + "_U497":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U521":{ + "_U498":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U517.clk"], - ["self.in.0","_U517.in"], - ["self.out.0","_U517.out"], - ["self.clk","_U518.clk"], - ["self.in.1","_U518.in"], - ["self.out.1","_U518.out"], - ["self.clk","_U519.clk"], - ["self.in.2","_U519.in"], - ["self.out.2","_U519.out"], - ["self.clk","_U520.clk"], - ["self.in.3","_U520.in"], - ["self.out.3","_U520.out"], - ["self.clk","_U521.clk"], - ["self.in.4","_U521.in"], - ["self.out.4","_U521.out"] + ["self.clk","_U494.clk"], + ["self.in.0","_U494.in"], + ["self.out.0","_U494.out"], + ["self.clk","_U495.clk"], + ["self.in.1","_U495.in"], + ["self.out.1","_U495.out"], + ["self.clk","_U496.clk"], + ["self.in.2","_U496.in"], + ["self.out.2","_U496.out"], + ["self.clk","_U497.clk"], + ["self.in.3","_U497.in"], + ["self.out.3","_U497.out"], + ["self.clk","_U498.clk"], + ["self.in.4","_U498.in"], + ["self.out.4","_U498.out"] ] }, - "array_delay_U523":{ + "array_delay_U500":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U524":{ + "_U501":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U525":{ + "_U502":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U526":{ + "_U503":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U527":{ + "_U504":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U528":{ + "_U505":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U524.clk"], - ["self.in.0","_U524.in"], - ["self.out.0","_U524.out"], - ["self.clk","_U525.clk"], - ["self.in.1","_U525.in"], - ["self.out.1","_U525.out"], - ["self.clk","_U526.clk"], - ["self.in.2","_U526.in"], - ["self.out.2","_U526.out"], - ["self.clk","_U527.clk"], - ["self.in.3","_U527.in"], - ["self.out.3","_U527.out"], - ["self.clk","_U528.clk"], - ["self.in.4","_U528.in"], - ["self.out.4","_U528.out"] + ["self.clk","_U501.clk"], + ["self.in.0","_U501.in"], + ["self.out.0","_U501.out"], + ["self.clk","_U502.clk"], + ["self.in.1","_U502.in"], + ["self.out.1","_U502.out"], + ["self.clk","_U503.clk"], + ["self.in.2","_U503.in"], + ["self.out.2","_U503.out"], + ["self.clk","_U504.clk"], + ["self.in.3","_U504.in"], + ["self.out.3","_U504.out"], + ["self.clk","_U505.clk"], + ["self.in.4","_U505.in"], + ["self.out.4","_U505.out"] ] }, - "array_delay_U530":{ + "array_delay_U507":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U531":{ + "_U508":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U532":{ + "_U509":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U533":{ + "_U510":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U534":{ + "_U511":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U535":{ + "_U512":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U531.clk"], - ["self.in.0","_U531.in"], - ["self.out.0","_U531.out"], - ["self.clk","_U532.clk"], - ["self.in.1","_U532.in"], - ["self.out.1","_U532.out"], - ["self.clk","_U533.clk"], - ["self.in.2","_U533.in"], - ["self.out.2","_U533.out"], - ["self.clk","_U534.clk"], - ["self.in.3","_U534.in"], - ["self.out.3","_U534.out"], - ["self.clk","_U535.clk"], - ["self.in.4","_U535.in"], - ["self.out.4","_U535.out"] + ["self.clk","_U508.clk"], + ["self.in.0","_U508.in"], + ["self.out.0","_U508.out"], + ["self.clk","_U509.clk"], + ["self.in.1","_U509.in"], + ["self.out.1","_U509.out"], + ["self.clk","_U510.clk"], + ["self.in.2","_U510.in"], + ["self.out.2","_U510.out"], + ["self.clk","_U511.clk"], + ["self.in.3","_U511.in"], + ["self.out.3","_U511.out"], + ["self.clk","_U512.clk"], + ["self.in.4","_U512.in"], + ["self.out.4","_U512.out"] ] }, - "array_delay_U537":{ + "array_delay_U514":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U538":{ + "_U515":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U539":{ + "_U516":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U540":{ + "_U517":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U541":{ + "_U518":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U542":{ + "_U519":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U538.clk"], - ["self.in.0","_U538.in"], - ["self.out.0","_U538.out"], - ["self.clk","_U539.clk"], - ["self.in.1","_U539.in"], - ["self.out.1","_U539.out"], - ["self.clk","_U540.clk"], - ["self.in.2","_U540.in"], - ["self.out.2","_U540.out"], - ["self.clk","_U541.clk"], - ["self.in.3","_U541.in"], - ["self.out.3","_U541.out"], - ["self.clk","_U542.clk"], - ["self.in.4","_U542.in"], - ["self.out.4","_U542.out"] + ["self.clk","_U515.clk"], + ["self.in.0","_U515.in"], + ["self.out.0","_U515.out"], + ["self.clk","_U516.clk"], + ["self.in.1","_U516.in"], + ["self.out.1","_U516.out"], + ["self.clk","_U517.clk"], + ["self.in.2","_U517.in"], + ["self.out.2","_U517.out"], + ["self.clk","_U518.clk"], + ["self.in.3","_U518.in"], + ["self.out.3","_U518.out"], + ["self.clk","_U519.clk"], + ["self.in.4","_U519.in"], + ["self.out.4","_U519.out"] ] }, - "array_delay_U544":{ + "array_delay_U521":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U545":{ + "_U522":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U546":{ + "_U523":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U547":{ + "_U524":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U548":{ + "_U525":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U549":{ + "_U526":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U545.clk"], - ["self.in.0","_U545.in"], - ["self.out.0","_U545.out"], - ["self.clk","_U546.clk"], - ["self.in.1","_U546.in"], - ["self.out.1","_U546.out"], - ["self.clk","_U547.clk"], - ["self.in.2","_U547.in"], - ["self.out.2","_U547.out"], - ["self.clk","_U548.clk"], - ["self.in.3","_U548.in"], - ["self.out.3","_U548.out"], - ["self.clk","_U549.clk"], - ["self.in.4","_U549.in"], - ["self.out.4","_U549.out"] + ["self.clk","_U522.clk"], + ["self.in.0","_U522.in"], + ["self.out.0","_U522.out"], + ["self.clk","_U523.clk"], + ["self.in.1","_U523.in"], + ["self.out.1","_U523.out"], + ["self.clk","_U524.clk"], + ["self.in.2","_U524.in"], + ["self.out.2","_U524.out"], + ["self.clk","_U525.clk"], + ["self.in.3","_U525.in"], + ["self.out.3","_U525.out"], + ["self.clk","_U526.clk"], + ["self.in.4","_U526.in"], + ["self.out.4","_U526.out"] ] }, - "array_delay_U551":{ + "array_delay_U528":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U552":{ + "_U529":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U553":{ + "_U530":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U554":{ + "_U531":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U555":{ + "_U532":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U556":{ + "_U533":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U552.clk"], - ["self.in.0","_U552.in"], - ["self.out.0","_U552.out"], - ["self.clk","_U553.clk"], - ["self.in.1","_U553.in"], - ["self.out.1","_U553.out"], - ["self.clk","_U554.clk"], - ["self.in.2","_U554.in"], - ["self.out.2","_U554.out"], - ["self.clk","_U555.clk"], - ["self.in.3","_U555.in"], - ["self.out.3","_U555.out"], - ["self.clk","_U556.clk"], - ["self.in.4","_U556.in"], - ["self.out.4","_U556.out"] + ["self.clk","_U529.clk"], + ["self.in.0","_U529.in"], + ["self.out.0","_U529.out"], + ["self.clk","_U530.clk"], + ["self.in.1","_U530.in"], + ["self.out.1","_U530.out"], + ["self.clk","_U531.clk"], + ["self.in.2","_U531.in"], + ["self.out.2","_U531.out"], + ["self.clk","_U532.clk"], + ["self.in.3","_U532.in"], + ["self.out.3","_U532.out"], + ["self.clk","_U533.clk"], + ["self.in.4","_U533.in"], + ["self.out.4","_U533.out"] ] }, - "array_delay_U558":{ + "array_delay_U535":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U559":{ + "_U536":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U560":{ + "_U537":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U561":{ + "_U538":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U562":{ + "_U539":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U563":{ + "_U540":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U559.clk"], - ["self.in.0","_U559.in"], - ["self.out.0","_U559.out"], - ["self.clk","_U560.clk"], - ["self.in.1","_U560.in"], - ["self.out.1","_U560.out"], - ["self.clk","_U561.clk"], - ["self.in.2","_U561.in"], - ["self.out.2","_U561.out"], - ["self.clk","_U562.clk"], - ["self.in.3","_U562.in"], - ["self.out.3","_U562.out"], - ["self.clk","_U563.clk"], - ["self.in.4","_U563.in"], - ["self.out.4","_U563.out"] + ["self.clk","_U536.clk"], + ["self.in.0","_U536.in"], + ["self.out.0","_U536.out"], + ["self.clk","_U537.clk"], + ["self.in.1","_U537.in"], + ["self.out.1","_U537.out"], + ["self.clk","_U538.clk"], + ["self.in.2","_U538.in"], + ["self.out.2","_U538.out"], + ["self.clk","_U539.clk"], + ["self.in.3","_U539.in"], + ["self.out.3","_U539.out"], + ["self.clk","_U540.clk"], + ["self.in.4","_U540.in"], + ["self.out.4","_U540.out"] ] }, - "array_delay_U565":{ + "array_delay_U542":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U566":{ + "_U543":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U567":{ + "_U544":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U568":{ + "_U545":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U569":{ + "_U546":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U570":{ + "_U547":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U566.clk"], - ["self.in.0","_U566.in"], - ["self.out.0","_U566.out"], - ["self.clk","_U567.clk"], - ["self.in.1","_U567.in"], - ["self.out.1","_U567.out"], - ["self.clk","_U568.clk"], - ["self.in.2","_U568.in"], - ["self.out.2","_U568.out"], - ["self.clk","_U569.clk"], - ["self.in.3","_U569.in"], - ["self.out.3","_U569.out"], - ["self.clk","_U570.clk"], - ["self.in.4","_U570.in"], - ["self.out.4","_U570.out"] + ["self.clk","_U543.clk"], + ["self.in.0","_U543.in"], + ["self.out.0","_U543.out"], + ["self.clk","_U544.clk"], + ["self.in.1","_U544.in"], + ["self.out.1","_U544.out"], + ["self.clk","_U545.clk"], + ["self.in.2","_U545.in"], + ["self.out.2","_U545.out"], + ["self.clk","_U546.clk"], + ["self.in.3","_U546.in"], + ["self.out.3","_U546.out"], + ["self.clk","_U547.clk"], + ["self.in.4","_U547.in"], + ["self.out.4","_U547.out"] ] }, - "array_delay_U572":{ + "array_delay_U549":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U573":{ + "_U550":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U574":{ + "_U551":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U575":{ + "_U552":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U576":{ + "_U553":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U577":{ + "_U554":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U573.clk"], - ["self.in.0","_U573.in"], - ["self.out.0","_U573.out"], - ["self.clk","_U574.clk"], - ["self.in.1","_U574.in"], - ["self.out.1","_U574.out"], - ["self.clk","_U575.clk"], - ["self.in.2","_U575.in"], - ["self.out.2","_U575.out"], - ["self.clk","_U576.clk"], - ["self.in.3","_U576.in"], - ["self.out.3","_U576.out"], - ["self.clk","_U577.clk"], - ["self.in.4","_U577.in"], - ["self.out.4","_U577.out"] + ["self.clk","_U550.clk"], + ["self.in.0","_U550.in"], + ["self.out.0","_U550.out"], + ["self.clk","_U551.clk"], + ["self.in.1","_U551.in"], + ["self.out.1","_U551.out"], + ["self.clk","_U552.clk"], + ["self.in.2","_U552.in"], + ["self.out.2","_U552.out"], + ["self.clk","_U553.clk"], + ["self.in.3","_U553.in"], + ["self.out.3","_U553.out"], + ["self.clk","_U554.clk"], + ["self.in.4","_U554.in"], + ["self.out.4","_U554.out"] ] }, - "array_delay_U579":{ + "array_delay_U556":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U580":{ + "_U557":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U581":{ + "_U558":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U582":{ + "_U559":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U583":{ + "_U560":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U584":{ + "_U561":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U580.clk"], - ["self.in.0","_U580.in"], - ["self.out.0","_U580.out"], - ["self.clk","_U581.clk"], - ["self.in.1","_U581.in"], - ["self.out.1","_U581.out"], - ["self.clk","_U582.clk"], - ["self.in.2","_U582.in"], - ["self.out.2","_U582.out"], - ["self.clk","_U583.clk"], - ["self.in.3","_U583.in"], - ["self.out.3","_U583.out"], - ["self.clk","_U584.clk"], - ["self.in.4","_U584.in"], - ["self.out.4","_U584.out"] + ["self.clk","_U557.clk"], + ["self.in.0","_U557.in"], + ["self.out.0","_U557.out"], + ["self.clk","_U558.clk"], + ["self.in.1","_U558.in"], + ["self.out.1","_U558.out"], + ["self.clk","_U559.clk"], + ["self.in.2","_U559.in"], + ["self.out.2","_U559.out"], + ["self.clk","_U560.clk"], + ["self.in.3","_U560.in"], + ["self.out.3","_U560.out"], + ["self.clk","_U561.clk"], + ["self.in.4","_U561.in"], + ["self.out.4","_U561.out"] ] }, - "array_delay_U586":{ + "array_delay_U563":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] ]], "instances":{ - "_U587":{ + "_U564":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U588":{ + "_U565":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U589":{ + "_U566":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U590":{ + "_U567":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U591":{ + "_U568":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} } }, "connections":[ - ["self.clk","_U587.clk"], - ["self.in.0","_U587.in"], - ["self.out.0","_U587.out"], - ["self.clk","_U588.clk"], - ["self.in.1","_U588.in"], - ["self.out.1","_U588.out"], - ["self.clk","_U589.clk"], - ["self.in.2","_U589.in"], - ["self.out.2","_U589.out"], - ["self.clk","_U590.clk"], - ["self.in.3","_U590.in"], - ["self.out.3","_U590.out"], - ["self.clk","_U591.clk"], - ["self.in.4","_U591.in"], - ["self.out.4","_U591.out"] + ["self.clk","_U564.clk"], + ["self.in.0","_U564.in"], + ["self.out.0","_U564.out"], + ["self.clk","_U565.clk"], + ["self.in.1","_U565.in"], + ["self.out.1","_U565.out"], + ["self.clk","_U566.clk"], + ["self.in.2","_U566.in"], + ["self.out.2","_U566.out"], + ["self.clk","_U567.clk"], + ["self.in.3","_U567.in"], + ["self.out.3","_U567.out"], + ["self.clk","_U568.clk"], + ["self.in.4","_U568.in"], + ["self.out.4","_U568.out"] ] }, "array_delay_U629":{ @@ -22464,7 +22464,7 @@ "cu_op_hcompute_hw_input_global_wrapper_stencil":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -22473,14 +22473,14 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write.0","inner_compute.out_hw_input_global_wrapper_stencil"] ] }, "cu_op_hcompute_hw_input_global_wrapper_stencil_1":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -22489,14 +22489,14 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write.0","inner_compute.out_hw_input_global_wrapper_stencil"] ] }, "cu_op_hcompute_hw_input_global_wrapper_stencil_2":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -22505,14 +22505,14 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write.0","inner_compute.out_hw_input_global_wrapper_stencil"] ] }, "cu_op_hcompute_hw_input_global_wrapper_stencil_3":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -22521,14 +22521,14 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write.0","inner_compute.out_hw_input_global_wrapper_stencil"] ] }, "cu_op_hcompute_hw_input_global_wrapper_stencil_4":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -22537,14 +22537,14 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write.0","inner_compute.out_hw_input_global_wrapper_stencil"] ] }, "cu_op_hcompute_hw_input_global_wrapper_stencil_5":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -22553,14 +22553,14 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write.0","inner_compute.out_hw_input_global_wrapper_stencil"] ] }, "cu_op_hcompute_hw_input_global_wrapper_stencil_6":{ "type":["Record",[ ["clk",["Named","coreir.clkIn"]], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write",["Array",1,["Array",16,"Bit"]]] ]], "instances":{ @@ -22569,7 +22569,7 @@ } }, "connections":[ - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read.0","inner_compute.in0_hw_input_stencil.0"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read.0","inner_compute.in0_hw_input_stencil.0"], ["self.hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write.0","inner_compute.out_hw_input_global_wrapper_stencil"] ] }, @@ -24229,13 +24229,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U650":{ - "modref":"global._U650_pt__U651" - }, - "_U652":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U651":{ + "modref":"global._U651_pt__U652" + }, "_U653":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -24267,18 +24267,25 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U659":{ - "modref":"global._U659_pt__U660" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U661":{ - "modref":"global._U661_pt__U662" + "_U660":{ + "modref":"global._U660_pt__U661" }, - "_U663":{ + "_U662":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U664":{ - "modref":"global._U664_pt__U665" + "_U663":{ + "modref":"global._U663_pt__U664" + }, + "_U665":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U666":{ "genref":"mantle.reg", @@ -24294,28 +24301,28 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U670":{ + "modref":"global._U670_pt__U671" + }, + "_U672":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U671":{ + "_U673":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U672":{ + "_U674":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U673":{ + "_U675":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U674":{ - "modref":"global._U674_pt__U675" - }, "_U676":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -24327,44 +24334,44 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U678":{ + "modref":"global._U678_pt__U679" + }, + "_U680":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U679":{ + "_U681":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U680":{ + "_U682":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U681":{ + "_U683":{ + "modref":"global._U683_pt__U684" + }, + "_U685":{ + "modref":"global._U685_pt__U686" + }, + "_U687":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U682":{ - "modref":"global._U682_pt__U683" - }, - "_U684":{ + "_U688":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U685":{ + "_U689":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U686":{ - "modref":"global._U686_pt__U687" - }, - "_U688":{ - "modref":"global._U688_pt__U689" - }, "_U690":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -24401,28 +24408,28 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U697":{ - "modref":"global._U697_pt__U698" - }, - "_U699":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U700":{ + "_U698":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U701":{ + "_U699":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U702":{ + "_U700":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U701":{ + "modref":"global._U701_pt__U702" + }, "_U703":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -24434,27 +24441,20 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U705":{ - "modref":"global._U705_pt__U706" - }, - "_U707":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U708":{ + "_U706":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U709":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U707":{ + "modref":"global._U707_pt__U708" }, - "_U710":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U709":{ + "modref":"global._U709_pt__U710" }, "_U711":{ "genref":"mantle.reg", @@ -24477,14 +24477,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U715":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U716":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U715_pt__U716" }, "_U717":{ "genref":"mantle.reg", @@ -24507,18 +24500,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U721":{ - "modref":"global._U721_pt__U722" - }, - "_U723":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U724":{ + "_U722":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U723":{ + "modref":"global._U723_pt__U724" + }, "_U725":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -24548,7 +24541,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U732":{ - "modref":"global._U732_pt__U733" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U733":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U734":{ "genref":"mantle.reg", @@ -25018,9 +25018,9 @@ }, "connections":[ ["_U643.out","_U637.in"], - ["mul_hw_kernel_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_924.in0","_U637.out"], + ["mul_hw_kernel_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_924.in1","_U637.out"], ["self.clk","_U639.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.5","_U639.in"], + ["self.in1_hw_input_global_wrapper_stencil.5","_U639.in"], ["_U640.in","_U639.out"], ["self.clk","_U640.clk"], ["_U641.in","_U640.out"], @@ -25029,22 +25029,22 @@ ["self.clk","_U642.clk"], ["_U643.in","_U642.out"], ["self.clk","_U643.clk"], - ["_U649.out","_U644.in"], - ["mul_hw_kernel_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_923.in0","_U644.out"], + ["_U650.out","_U644.in"], + ["mul_hw_kernel_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_924.in0","_U644.out"], ["self.clk","_U646.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.4","_U646.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.5","_U646.in"], ["_U647.in","_U646.out"], ["self.clk","_U647.clk"], ["_U648.in","_U647.out"], ["self.clk","_U648.clk"], ["_U649.in","_U648.out"], ["self.clk","_U649.clk"], - ["_U658.out","_U650.in"], - ["mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926.in0","_U650.out"], - ["self.clk","_U652.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.7","_U652.in"], - ["_U653.in","_U652.out"], + ["_U650.in","_U649.out"], + ["self.clk","_U650.clk"], + ["_U659.out","_U651.in"], + ["mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926.in1","_U651.out"], ["self.clk","_U653.clk"], + ["self.in1_hw_input_global_wrapper_stencil.7","_U653.in"], ["_U654.in","_U653.out"], ["self.clk","_U654.clk"], ["_U655.in","_U654.out"], @@ -25055,54 +25055,56 @@ ["self.clk","_U657.clk"], ["_U658.in","_U657.out"], ["self.clk","_U658.clk"], - ["self.in1_hw_input_global_wrapper_stencil.0","_U659.in"], - ["mul_hw_kernel_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_919.in1","_U659.out"], - ["_U663.out","_U661.in"], - ["mul_hw_kernel_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_920.in1","_U661.out"], - ["self.clk","_U663.clk"], - ["self.in1_hw_input_global_wrapper_stencil.1","_U663.in"], - ["_U666.out","_U664.in"], - ["add_925_926_927.in1","_U664.out"], + ["_U659.in","_U658.out"], + ["self.clk","_U659.clk"], + ["_U662.out","_U660.in"], + ["mul_hw_kernel_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_920.in0","_U660.out"], + ["self.clk","_U662.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.1","_U662.in"], + ["_U666.out","_U663.in"], + ["mul_hw_kernel_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_921.in0","_U663.out"], + ["self.clk","_U665.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.2","_U665.in"], + ["_U666.in","_U665.out"], ["self.clk","_U666.clk"], - ["mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926.out","_U666.in"], - ["_U673.out","_U667.in"], - ["mul_hw_kernel_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_924.in1","_U667.out"], + ["_U669.out","_U667.in"], + ["add_925_926_927.in1","_U667.out"], ["self.clk","_U669.clk"], - ["self.in1_hw_input_global_wrapper_stencil.5","_U669.in"], - ["_U670.in","_U669.out"], - ["self.clk","_U670.clk"], - ["_U671.in","_U670.out"], - ["self.clk","_U671.clk"], - ["_U672.in","_U671.out"], + ["mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926.out","_U669.in"], + ["_U677.out","_U670.in"], + ["mul_hw_kernel_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_925.in1","_U670.out"], ["self.clk","_U672.clk"], + ["self.in1_hw_input_global_wrapper_stencil.6","_U672.in"], ["_U673.in","_U672.out"], ["self.clk","_U673.clk"], - ["_U681.out","_U674.in"], - ["mul_hw_kernel_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_925.in0","_U674.out"], + ["_U674.in","_U673.out"], + ["self.clk","_U674.clk"], + ["_U675.in","_U674.out"], + ["self.clk","_U675.clk"], + ["_U676.in","_U675.out"], ["self.clk","_U676.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.6","_U676.in"], ["_U677.in","_U676.out"], ["self.clk","_U677.clk"], - ["_U678.in","_U677.out"], - ["self.clk","_U678.clk"], - ["_U679.in","_U678.out"], - ["self.clk","_U679.clk"], - ["_U680.in","_U679.out"], + ["_U682.out","_U678.in"], + ["mul_hw_kernel_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_922.in0","_U678.out"], ["self.clk","_U680.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.3","_U680.in"], ["_U681.in","_U680.out"], ["self.clk","_U681.clk"], - ["_U685.out","_U682.in"], - ["mul_hw_kernel_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_921.in1","_U682.out"], - ["self.clk","_U684.clk"], - ["self.in1_hw_input_global_wrapper_stencil.2","_U684.in"], - ["_U685.in","_U684.out"], - ["self.clk","_U685.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.0","_U686.in"], - ["mul_hw_kernel_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_919.in0","_U686.out"], - ["_U696.out","_U688.in"], - ["mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926.in1","_U688.out"], + ["_U682.in","_U681.out"], + ["self.clk","_U682.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","_U683.in"], + ["mul_hw_kernel_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_919.in0","_U683.out"], + ["_U700.out","_U685.in"], + ["add_conv_stencil_4_932_933.in0","_U685.out"], + ["self.clk","_U687.clk"], + ["self.in0_conv_stencil.0","_U687.in"], + ["_U688.in","_U687.out"], + ["self.clk","_U688.clk"], + ["_U689.in","_U688.out"], + ["self.clk","_U689.clk"], + ["_U690.in","_U689.out"], ["self.clk","_U690.clk"], - ["self.in1_hw_input_global_wrapper_stencil.7","_U690.in"], ["_U691.in","_U690.out"], ["self.clk","_U691.clk"], ["_U692.in","_U691.out"], @@ -25115,84 +25117,82 @@ ["self.clk","_U695.clk"], ["_U696.in","_U695.out"], ["self.clk","_U696.clk"], - ["_U704.out","_U697.in"], - ["mul_hw_kernel_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_925.in1","_U697.out"], + ["_U697.in","_U696.out"], + ["self.clk","_U697.clk"], + ["_U698.in","_U697.out"], + ["self.clk","_U698.clk"], + ["_U699.in","_U698.out"], ["self.clk","_U699.clk"], - ["self.in1_hw_input_global_wrapper_stencil.6","_U699.in"], ["_U700.in","_U699.out"], ["self.clk","_U700.clk"], - ["_U701.in","_U700.out"], - ["self.clk","_U701.clk"], - ["_U702.in","_U701.out"], - ["self.clk","_U702.clk"], - ["_U703.in","_U702.out"], + ["_U706.out","_U701.in"], + ["mul_hw_kernel_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_923.in1","_U701.out"], ["self.clk","_U703.clk"], + ["self.in1_hw_input_global_wrapper_stencil.4","_U703.in"], ["_U704.in","_U703.out"], ["self.clk","_U704.clk"], - ["_U720.out","_U705.in"], - ["add_conv_stencil_4_932_933.in0","_U705.out"], - ["self.clk","_U707.clk"], - ["self.in0_conv_stencil.0","_U707.in"], - ["_U708.in","_U707.out"], - ["self.clk","_U708.clk"], - ["_U709.in","_U708.out"], - ["self.clk","_U709.clk"], - ["_U710.in","_U709.out"], - ["self.clk","_U710.clk"], - ["_U711.in","_U710.out"], + ["_U705.in","_U704.out"], + ["self.clk","_U705.clk"], + ["_U706.in","_U705.out"], + ["self.clk","_U706.clk"], + ["self.in1_hw_input_global_wrapper_stencil.0","_U707.in"], + ["mul_hw_kernel_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_919.in1","_U707.out"], + ["_U714.out","_U709.in"], + ["mul_hw_kernel_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_923.in0","_U709.out"], ["self.clk","_U711.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.4","_U711.in"], ["_U712.in","_U711.out"], ["self.clk","_U712.clk"], ["_U713.in","_U712.out"], ["self.clk","_U713.clk"], ["_U714.in","_U713.out"], ["self.clk","_U714.clk"], - ["_U715.in","_U714.out"], - ["self.clk","_U715.clk"], - ["_U716.in","_U715.out"], - ["self.clk","_U716.clk"], - ["_U717.in","_U716.out"], + ["_U722.out","_U715.in"], + ["mul_hw_kernel_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_925.in0","_U715.out"], ["self.clk","_U717.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.6","_U717.in"], ["_U718.in","_U717.out"], ["self.clk","_U718.clk"], ["_U719.in","_U718.out"], ["self.clk","_U719.clk"], ["_U720.in","_U719.out"], ["self.clk","_U720.clk"], - ["_U725.out","_U721.in"], - ["mul_hw_kernel_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_922.in1","_U721.out"], - ["self.clk","_U723.clk"], - ["self.in1_hw_input_global_wrapper_stencil.3","_U723.in"], - ["_U724.in","_U723.out"], - ["self.clk","_U724.clk"], - ["_U725.in","_U724.out"], + ["_U721.in","_U720.out"], + ["self.clk","_U721.clk"], + ["_U722.in","_U721.out"], + ["self.clk","_U722.clk"], + ["_U725.out","_U723.in"], + ["mul_hw_kernel_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_920.in1","_U723.out"], ["self.clk","_U725.clk"], - ["_U731.out","_U726.in"], - ["mul_hw_kernel_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_923.in1","_U726.out"], + ["self.in1_hw_input_global_wrapper_stencil.1","_U725.in"], + ["_U734.out","_U726.in"], + ["mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926.in0","_U726.out"], ["self.clk","_U728.clk"], - ["self.in1_hw_input_global_wrapper_stencil.4","_U728.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.7","_U728.in"], ["_U729.in","_U728.out"], ["self.clk","_U729.clk"], ["_U730.in","_U729.out"], ["self.clk","_U730.clk"], ["_U731.in","_U730.out"], ["self.clk","_U731.clk"], - ["_U734.out","_U732.in"], - ["mul_hw_kernel_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_920.in0","_U732.out"], + ["_U732.in","_U731.out"], + ["self.clk","_U732.clk"], + ["_U733.in","_U732.out"], + ["self.clk","_U733.clk"], + ["_U734.in","_U733.out"], ["self.clk","_U734.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.1","_U734.in"], ["_U739.out","_U735.in"], - ["mul_hw_kernel_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_922.in0","_U735.out"], + ["mul_hw_kernel_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_922.in1","_U735.out"], ["self.clk","_U737.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.3","_U737.in"], + ["self.in1_hw_input_global_wrapper_stencil.3","_U737.in"], ["_U738.in","_U737.out"], ["self.clk","_U738.clk"], ["_U739.in","_U738.out"], ["self.clk","_U739.clk"], ["_U743.out","_U740.in"], - ["mul_hw_kernel_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_921.in0","_U740.out"], + ["mul_hw_kernel_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_921.in1","_U740.out"], ["self.clk","_U742.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.2","_U742.in"], + ["self.in1_hw_input_global_wrapper_stencil.2","_U742.in"], ["_U743.in","_U742.out"], ["self.clk","_U743.clk"], ["_U760.out","_U744.in"], @@ -25484,26 +25484,26 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1002":{ + "modref":"global._U1002_pt__U1003" + }, + "_U1004":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1003":{ + "_U1005":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1004":{ + "_U1006":{ + "modref":"global._U1006_pt__U1007" + }, + "_U1008":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1005":{ - "modref":"global._U1005_pt__U1006" - }, - "_U1007":{ - "modref":"global._U1007_pt__U1008" - }, "_U1009":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -25515,10 +25515,24 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1011":{ - "modref":"global._U1011_pt__U1012" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1012":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1013":{ - "modref":"global._U1013_pt__U1014" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1014":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1015":{ "genref":"mantle.reg", @@ -25531,18 +25545,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1017":{ - "modref":"global._U1017_pt__U1018" - }, - "_U1019":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1020":{ + "_U1018":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1019":{ + "modref":"global._U1019_pt__U1020" + }, "_U1021":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -25569,15 +25583,22 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1026":{ - "modref":"global._U1026_pt__U1027" - }, - "_U1028":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1027":{ + "modref":"global._U1027_pt__U1028" + }, "_U1029":{ - "modref":"global._U1029_pt__U1030" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1030":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1031":{ "genref":"mantle.reg", @@ -25595,13 +25616,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1034":{ - "modref":"global._U1034_pt__U1035" - }, - "_U1036":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1035":{ + "modref":"global._U1035_pt__U1036" + }, "_U1037":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -25728,14 +25749,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U868":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U869":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U868_pt__U869" }, "_U870":{ "modref":"global._U870_pt__U871" @@ -25754,23 +25768,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U876":{ + "modref":"global._U876_pt__U877" + }, + "_U878":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U877":{ + "_U879":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U878":{ + "_U880":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U879":{ - "modref":"global._U879_pt__U880" - }, "_U881":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -25792,41 +25806,41 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U885":{ + "modref":"global._U885_pt__U886" + }, + "_U887":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U886":{ + "_U888":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U887":{ + "_U889":{ + "modref":"global._U889_pt__U890" + }, + "_U891":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U888":{ + "_U892":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U889":{ + "_U893":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U890":{ - "modref":"global._U890_pt__U891" - }, - "_U892":{ + "_U894":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U893":{ - "modref":"global._U893_pt__U894" - }, "_U895":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -25848,18 +25862,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U899":{ - "modref":"global._U899_pt__U900" - }, - "_U901":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U902":{ + "_U900":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U901":{ + "modref":"global._U901_pt__U902" + }, "_U903":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -25889,7 +25903,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U910":{ - "modref":"global._U910_pt__U911" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U911":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U912":{ "genref":"mantle.reg", @@ -25912,7 +25933,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U916":{ - "modref":"global._U916_pt__U917" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U917":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U918":{ "genref":"mantle.reg", @@ -25973,33 +26001,33 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U931":{ + "modref":"global._U931_pt__U932" + }, + "_U933":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U932":{ + "_U934":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U933":{ + "_U935":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U934":{ + "_U936":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U935":{ + "_U937":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U936":{ - "modref":"global._U936_pt__U937" - }, "_U938":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -26009,13 +26037,13 @@ "modref":"global._U939_pt__U940" }, "_U941":{ - "modref":"global._U941_pt__U942" - }, - "_U943":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U942":{ + "modref":"global._U942_pt__U943" + }, "_U944":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -26037,14 +26065,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U948":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U949":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U948_pt__U949" }, "_U950":{ "genref":"mantle.reg", @@ -26067,36 +26088,36 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U954":{ - "modref":"global._U954_pt__U955" - }, - "_U956":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U957":{ + "_U955":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U956":{ + "modref":"global._U956_pt__U957" + }, "_U958":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U959":{ + "modref":"global._U959_pt__U960" + }, + "_U961":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U960":{ + "_U962":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U961":{ - "modref":"global._U961_pt__U962" - }, "_U963":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -26118,35 +26139,28 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U967":{ - "modref":"global._U967_pt__U968" - }, - "_U969":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U970":{ - "modref":"global._U970_pt__U971" + "_U968":{ + "modref":"global._U968_pt__U969" }, - "_U972":{ + "_U970":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U971":{ + "modref":"global._U971_pt__U972" + }, "_U973":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U974":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U975":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U974_pt__U975" }, "_U976":{ "genref":"mantle.reg", @@ -26169,13 +26183,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U980":{ - "modref":"global._U980_pt__U981" - }, - "_U982":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U981":{ + "modref":"global._U981_pt__U982" + }, "_U983":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -26202,27 +26216,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U988":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U988_pt__U989" }, - "_U989":{ - "modref":"global._U989_pt__U990" - }, - "_U991":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U990":{ + "modref":"global._U990_pt__U991" }, "_U992":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U993":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U992_pt__U993" }, "_U994":{ "genref":"mantle.reg", @@ -26317,37 +26317,41 @@ ["_U999.out","_U1000.in"], ["_U1001.in","_U1000.out"], ["self.clk","_U1001.clk"], - ["_U1002.in","_U1001.out"], - ["self.clk","_U1002.clk"], - ["_U1003.in","_U1002.out"], - ["self.clk","_U1003.clk"], - ["_U1004.in","_U1003.out"], + ["_U997.in","_U1001.out"], + ["_U1005.out","_U1002.in"], + ["mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992.in0","_U1002.out"], ["self.clk","_U1004.clk"], - ["_U997.in","_U1004.out"], - ["self.in1_hw_input_global_wrapper_stencil.5","_U1005.in"], - ["mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991.in1","_U1005.out"], - ["_U1010.out","_U1007.in"], - ["mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992.in0","_U1007.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1004.in"], + ["_U1005.in","_U1004.out"], + ["self.clk","_U1005.clk"], + ["_U1018.out","_U1006.in"], + ["add_986_1000_1001.in0","_U1006.out"], + ["self.clk","_U1008.clk"], + ["mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986.out","_U1008.in"], + ["_U1009.in","_U1008.out"], ["self.clk","_U1009.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1009.in"], ["_U1010.in","_U1009.out"], ["self.clk","_U1010.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.5","_U1011.in"], - ["mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991.in0","_U1011.out"], - ["_U1016.out","_U1013.in"], - ["mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992.in1","_U1013.out"], + ["_U1011.in","_U1010.out"], + ["self.clk","_U1011.clk"], + ["_U1012.in","_U1011.out"], + ["self.clk","_U1012.clk"], + ["_U1013.in","_U1012.out"], + ["self.clk","_U1013.clk"], + ["_U1014.in","_U1013.out"], + ["self.clk","_U1014.clk"], + ["_U1015.in","_U1014.out"], ["self.clk","_U1015.clk"], - ["self.in1_hw_input_global_wrapper_stencil.6","_U1015.in"], ["_U1016.in","_U1015.out"], ["self.clk","_U1016.clk"], - ["_U1025.out","_U1017.in"], - ["mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989.in0","_U1017.out"], - ["self.clk","_U1019.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.3","_U1019.in"], - ["_U1020.in","_U1019.out"], - ["self.clk","_U1020.clk"], - ["_U1021.in","_U1020.out"], + ["_U1017.in","_U1016.out"], + ["self.clk","_U1017.clk"], + ["_U1018.in","_U1017.out"], + ["self.clk","_U1018.clk"], + ["_U1026.out","_U1019.in"], + ["mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993.in0","_U1019.out"], ["self.clk","_U1021.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1021.in"], ["_U1022.in","_U1021.out"], ["self.clk","_U1022.clk"], ["_U1023.in","_U1022.out"], @@ -26356,24 +26360,26 @@ ["self.clk","_U1024.clk"], ["_U1025.in","_U1024.out"], ["self.clk","_U1025.clk"], - ["_U1028.out","_U1026.in"], - ["mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988.in1","_U1026.out"], - ["self.clk","_U1028.clk"], - ["self.in1_hw_input_global_wrapper_stencil.2","_U1028.in"], - ["_U1033.out","_U1029.in"], - ["mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993.in1","_U1029.out"], + ["_U1026.in","_U1025.out"], + ["self.clk","_U1026.clk"], + ["_U1034.out","_U1027.in"], + ["mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993.in1","_U1027.out"], + ["self.clk","_U1029.clk"], + ["self.in1_hw_input_global_wrapper_stencil.7","_U1029.in"], + ["_U1030.in","_U1029.out"], + ["self.clk","_U1030.clk"], + ["_U1031.in","_U1030.out"], ["self.clk","_U1031.clk"], - ["self.in1_hw_input_global_wrapper_stencil.7","_U1031.in"], ["_U1032.in","_U1031.out"], ["self.clk","_U1032.clk"], ["_U1033.in","_U1032.out"], ["self.clk","_U1033.clk"], - ["_U1038.out","_U1034.in"], - ["mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993.in0","_U1034.out"], - ["self.clk","_U1036.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1036.in"], - ["_U1037.in","_U1036.out"], + ["_U1034.in","_U1033.out"], + ["self.clk","_U1034.clk"], + ["_U1038.out","_U1035.in"], + ["mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992.in1","_U1035.out"], ["self.clk","_U1037.clk"], + ["self.in1_hw_input_global_wrapper_stencil.6","_U1037.in"], ["_U1038.in","_U1037.out"], ["self.clk","_U1038.clk"], ["_U840.out","_U838.in"], @@ -26381,9 +26387,9 @@ ["self.clk","_U840.clk"], ["add_991_994_995.out","_U840.in"], ["_U847.out","_U841.in"], - ["mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987.in1","_U841.out"], + ["mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989.in0","_U841.out"], ["self.clk","_U843.clk"], - ["self.in1_hw_input_global_wrapper_stencil.1","_U843.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.3","_U843.in"], ["_U844.in","_U843.out"], ["self.clk","_U844.clk"], ["_U845.in","_U844.out"], @@ -26393,17 +26399,17 @@ ["_U847.in","_U846.out"], ["self.clk","_U847.clk"], ["_U850.out","_U848.in"], - ["add_987_998_999.in1","_U848.out"], + ["add_988_997_998.in1","_U848.out"], ["self.clk","_U850.clk"], - ["add_988_997_998.out","_U850.in"], + ["add_989_996_997.out","_U850.in"], ["_U853.out","_U851.in"], - ["add_991_994_995.in1","_U851.out"], + ["mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987.in0","_U851.out"], ["self.clk","_U853.clk"], - ["add_992_993_994.out","_U853.in"], - ["_U869.out","_U854.in"], - ["add_conv_stencil_5_999_1000.in0","_U854.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.1","_U853.in"], + ["_U867.out","_U854.in"], + ["add_987_998_999.in0","_U854.out"], ["self.clk","_U856.clk"], - ["self.in0_conv_stencil.0","_U856.in"], + ["mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987.out","_U856.in"], ["_U857.in","_U856.out"], ["self.clk","_U857.clk"], ["_U858.in","_U857.out"], @@ -26426,90 +26432,92 @@ ["self.clk","_U866.clk"], ["_U867.in","_U866.out"], ["self.clk","_U867.clk"], - ["_U868.in","_U867.out"], - ["self.clk","_U868.clk"], - ["_U869.in","_U868.out"], - ["self.clk","_U869.clk"], + ["add_986_1000_1001.out","_U868.in"], + ["self.out_conv_stencil","_U868.out"], ["_U872.out","_U870.in"], - ["mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988.in0","_U870.out"], + ["add_986_1000_1001.in1","_U870.out"], ["self.clk","_U872.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.2","_U872.in"], - ["_U878.out","_U873.in"], - ["mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986.in1","_U873.out"], + ["add_conv_stencil_5_999_1000.out","_U872.in"], + ["_U875.out","_U873.in"], + ["add_conv_stencil_5_999_1000.in1","_U873.out"], ["self.clk","_U875.clk"], - ["self.in1_hw_input_global_wrapper_stencil.0","_U875.in"], - ["_U876.in","_U875.out"], - ["self.clk","_U876.clk"], - ["_U877.in","_U876.out"], - ["self.clk","_U877.clk"], - ["_U878.in","_U877.out"], + ["add_987_998_999.out","_U875.in"], + ["_U884.out","_U876.in"], + ["mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988.in0","_U876.out"], ["self.clk","_U878.clk"], - ["_U889.out","_U879.in"], - ["add_991_994_995.in0","_U879.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.2","_U878.in"], + ["_U879.in","_U878.out"], + ["self.clk","_U879.clk"], + ["_U880.in","_U879.out"], + ["self.clk","_U880.clk"], + ["_U881.in","_U880.out"], ["self.clk","_U881.clk"], - ["mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991.out","_U881.in"], ["_U882.in","_U881.out"], ["self.clk","_U882.clk"], ["_U883.in","_U882.out"], ["self.clk","_U883.clk"], ["_U884.in","_U883.out"], ["self.clk","_U884.clk"], - ["_U885.in","_U884.out"], - ["self.clk","_U885.clk"], - ["_U886.in","_U885.out"], - ["self.clk","_U886.clk"], - ["_U887.in","_U886.out"], + ["_U888.out","_U885.in"], + ["add_992_993_994.in1","_U885.out"], ["self.clk","_U887.clk"], + ["mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993.out","_U887.in"], ["_U888.in","_U887.out"], ["self.clk","_U888.clk"], - ["_U889.in","_U888.out"], - ["self.clk","_U889.clk"], - ["_U892.out","_U890.in"], - ["add_988_997_998.in1","_U890.out"], + ["_U900.out","_U889.in"], + ["add_990_995_996.in0","_U889.out"], + ["self.clk","_U891.clk"], + ["mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990.out","_U891.in"], + ["_U892.in","_U891.out"], ["self.clk","_U892.clk"], - ["add_989_996_997.out","_U892.in"], - ["_U898.out","_U893.in"], - ["add_989_996_997.in0","_U893.out"], + ["_U893.in","_U892.out"], + ["self.clk","_U893.clk"], + ["_U894.in","_U893.out"], + ["self.clk","_U894.clk"], + ["_U895.in","_U894.out"], ["self.clk","_U895.clk"], - ["mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989.out","_U895.in"], ["_U896.in","_U895.out"], ["self.clk","_U896.clk"], ["_U897.in","_U896.out"], ["self.clk","_U897.clk"], ["_U898.in","_U897.out"], ["self.clk","_U898.clk"], - ["_U906.out","_U899.in"], - ["add_992_993_994.in0","_U899.out"], - ["self.clk","_U901.clk"], - ["mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992.out","_U901.in"], - ["_U902.in","_U901.out"], - ["self.clk","_U902.clk"], - ["_U903.in","_U902.out"], + ["_U899.in","_U898.out"], + ["self.clk","_U899.clk"], + ["_U900.in","_U899.out"], + ["self.clk","_U900.clk"], + ["_U906.out","_U901.in"], + ["mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986.in1","_U901.out"], ["self.clk","_U903.clk"], + ["self.in1_hw_input_global_wrapper_stencil.0","_U903.in"], ["_U904.in","_U903.out"], ["self.clk","_U904.clk"], ["_U905.in","_U904.out"], ["self.clk","_U905.clk"], ["_U906.in","_U905.out"], ["self.clk","_U906.clk"], - ["_U909.out","_U907.in"], - ["add_989_996_997.in1","_U907.out"], + ["_U922.out","_U907.in"], + ["add_conv_stencil_5_999_1000.in0","_U907.out"], ["self.clk","_U909.clk"], - ["add_990_995_996.out","_U909.in"], - ["_U915.out","_U910.in"], - ["add_990_995_996.in0","_U910.out"], + ["self.in0_conv_stencil.0","_U909.in"], + ["_U910.in","_U909.out"], + ["self.clk","_U910.clk"], + ["_U911.in","_U910.out"], + ["self.clk","_U911.clk"], + ["_U912.in","_U911.out"], ["self.clk","_U912.clk"], - ["mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990.out","_U912.in"], ["_U913.in","_U912.out"], ["self.clk","_U913.clk"], ["_U914.in","_U913.out"], ["self.clk","_U914.clk"], ["_U915.in","_U914.out"], ["self.clk","_U915.clk"], - ["_U922.out","_U916.in"], - ["add_992_993_994.in1","_U916.out"], + ["_U916.in","_U915.out"], + ["self.clk","_U916.clk"], + ["_U917.in","_U916.out"], + ["self.clk","_U917.clk"], + ["_U918.in","_U917.out"], ["self.clk","_U918.clk"], - ["mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993.out","_U918.in"], ["_U919.in","_U918.out"], ["self.clk","_U919.clk"], ["_U920.in","_U919.out"], @@ -26518,10 +26526,10 @@ ["self.clk","_U921.clk"], ["_U922.in","_U921.out"], ["self.clk","_U922.clk"], - ["_U935.out","_U923.in"], - ["add_986_1000_1001.in0","_U923.out"], + ["_U930.out","_U923.in"], + ["add_991_994_995.in0","_U923.out"], ["self.clk","_U925.clk"], - ["mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986.out","_U925.in"], + ["mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991.out","_U925.in"], ["_U926.in","_U925.out"], ["self.clk","_U926.clk"], ["_U927.in","_U926.out"], @@ -26532,96 +26540,92 @@ ["self.clk","_U929.clk"], ["_U930.in","_U929.out"], ["self.clk","_U930.clk"], - ["_U931.in","_U930.out"], - ["self.clk","_U931.clk"], - ["_U932.in","_U931.out"], - ["self.clk","_U932.clk"], - ["_U933.in","_U932.out"], + ["_U938.out","_U931.in"], + ["add_992_993_994.in0","_U931.out"], ["self.clk","_U933.clk"], + ["mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992.out","_U933.in"], ["_U934.in","_U933.out"], ["self.clk","_U934.clk"], ["_U935.in","_U934.out"], ["self.clk","_U935.clk"], - ["_U938.out","_U936.in"], - ["add_conv_stencil_5_999_1000.in1","_U936.out"], + ["_U936.in","_U935.out"], + ["self.clk","_U936.clk"], + ["_U937.in","_U936.out"], + ["self.clk","_U937.clk"], + ["_U938.in","_U937.out"], ["self.clk","_U938.clk"], - ["add_987_998_999.out","_U938.in"], - ["add_986_1000_1001.out","_U939.in"], - ["self.out_conv_stencil","_U939.out"], - ["_U953.out","_U941.in"], - ["add_988_997_998.in0","_U941.out"], - ["self.clk","_U943.clk"], - ["mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988.out","_U943.in"], - ["_U944.in","_U943.out"], + ["_U941.out","_U939.in"], + ["add_991_994_995.in1","_U939.out"], + ["self.clk","_U941.clk"], + ["add_992_993_994.out","_U941.in"], + ["_U947.out","_U942.in"], + ["mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986.in0","_U942.out"], ["self.clk","_U944.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","_U944.in"], ["_U945.in","_U944.out"], ["self.clk","_U945.clk"], ["_U946.in","_U945.out"], ["self.clk","_U946.clk"], ["_U947.in","_U946.out"], ["self.clk","_U947.clk"], - ["_U948.in","_U947.out"], - ["self.clk","_U948.clk"], - ["_U949.in","_U948.out"], - ["self.clk","_U949.clk"], - ["_U950.in","_U949.out"], + ["_U955.out","_U948.in"], + ["add_989_996_997.in0","_U948.out"], ["self.clk","_U950.clk"], + ["mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989.out","_U950.in"], ["_U951.in","_U950.out"], ["self.clk","_U951.clk"], ["_U952.in","_U951.out"], ["self.clk","_U952.clk"], ["_U953.in","_U952.out"], ["self.clk","_U953.clk"], - ["_U960.out","_U954.in"], - ["mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987.in0","_U954.out"], - ["self.clk","_U956.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.1","_U956.in"], - ["_U957.in","_U956.out"], - ["self.clk","_U957.clk"], - ["_U958.in","_U957.out"], + ["_U954.in","_U953.out"], + ["self.clk","_U954.clk"], + ["_U955.in","_U954.out"], + ["self.clk","_U955.clk"], + ["_U958.out","_U956.in"], + ["add_989_996_997.in1","_U956.out"], ["self.clk","_U958.clk"], - ["_U959.in","_U958.out"], - ["self.clk","_U959.clk"], - ["_U960.in","_U959.out"], - ["self.clk","_U960.clk"], - ["_U966.out","_U961.in"], - ["mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986.in0","_U961.out"], + ["add_990_995_996.out","_U958.in"], + ["_U967.out","_U959.in"], + ["mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988.in1","_U959.out"], + ["self.clk","_U961.clk"], + ["self.in1_hw_input_global_wrapper_stencil.2","_U961.in"], + ["_U962.in","_U961.out"], + ["self.clk","_U962.clk"], + ["_U963.in","_U962.out"], ["self.clk","_U963.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.0","_U963.in"], ["_U964.in","_U963.out"], ["self.clk","_U964.clk"], ["_U965.in","_U964.out"], ["self.clk","_U965.clk"], ["_U966.in","_U965.out"], ["self.clk","_U966.clk"], - ["_U969.out","_U967.in"], - ["add_986_1000_1001.in1","_U967.out"], - ["self.clk","_U969.clk"], - ["add_conv_stencil_5_999_1000.out","_U969.in"], - ["_U979.out","_U970.in"], - ["add_987_998_999.in0","_U970.out"], - ["self.clk","_U972.clk"], - ["mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987.out","_U972.in"], - ["_U973.in","_U972.out"], + ["_U967.in","_U966.out"], + ["self.clk","_U967.clk"], + ["_U970.out","_U968.in"], + ["mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987.in1","_U968.out"], + ["self.clk","_U970.clk"], + ["self.in1_hw_input_global_wrapper_stencil.1","_U970.in"], + ["_U973.out","_U971.in"], + ["add_987_998_999.in1","_U971.out"], ["self.clk","_U973.clk"], - ["_U974.in","_U973.out"], - ["self.clk","_U974.clk"], - ["_U975.in","_U974.out"], - ["self.clk","_U975.clk"], - ["_U976.in","_U975.out"], + ["add_988_997_998.out","_U973.in"], + ["_U980.out","_U974.in"], + ["add_988_997_998.in0","_U974.out"], ["self.clk","_U976.clk"], + ["mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988.out","_U976.in"], ["_U977.in","_U976.out"], ["self.clk","_U977.clk"], ["_U978.in","_U977.out"], ["self.clk","_U978.clk"], ["_U979.in","_U978.out"], ["self.clk","_U979.clk"], - ["_U988.out","_U980.in"], - ["mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989.in1","_U980.out"], - ["self.clk","_U982.clk"], - ["self.in1_hw_input_global_wrapper_stencil.3","_U982.in"], - ["_U983.in","_U982.out"], + ["_U980.in","_U979.out"], + ["self.clk","_U980.clk"], + ["_U987.out","_U981.in"], + ["mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989.in1","_U981.out"], ["self.clk","_U983.clk"], + ["self.in1_hw_input_global_wrapper_stencil.3","_U983.in"], ["_U984.in","_U983.out"], ["self.clk","_U984.clk"], ["_U985.in","_U984.out"], @@ -26630,25 +26634,21 @@ ["self.clk","_U986.clk"], ["_U987.in","_U986.out"], ["self.clk","_U987.clk"], - ["_U988.in","_U987.out"], - ["self.clk","_U988.clk"], - ["_U996.out","_U989.in"], - ["mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990.in1","_U989.out"], - ["self.clk","_U991.clk"], - ["self.in1_hw_input_global_wrapper_stencil.4","_U991.in"], - ["_U992.in","_U991.out"], - ["self.clk","_U992.clk"], - ["_U993.in","_U992.out"], - ["self.clk","_U993.clk"], - ["_U994.in","_U993.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.4","_U988.in"], + ["mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990.in0","_U988.out"], + ["self.in1_hw_input_global_wrapper_stencil.4","_U990.in"], + ["mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990.in1","_U990.out"], + ["_U996.out","_U992.in"], + ["mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991.in0","_U992.out"], ["self.clk","_U994.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.5","_U994.in"], ["_U995.in","_U994.out"], ["self.clk","_U995.clk"], ["_U996.in","_U995.out"], ["self.clk","_U996.clk"], - ["mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990.in0","_U997.out"], + ["mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991.in1","_U997.out"], ["self.clk","_U999.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.4","_U999.in"] + ["self.in1_hw_input_global_wrapper_stencil.5","_U999.in"] ] }, "hcompute_conv_stencil_13":{ @@ -26813,38 +26813,38 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1049":{ - "modref":"global._U1049_pt__U1050" - }, - "_U1051":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1052":{ + "_U1050":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1053":{ + "_U1051":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1054":{ + "_U1052":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1055":{ + "_U1053":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1056":{ + "_U1054":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1055":{ + "modref":"global._U1055_pt__U1056" + }, "_U1057":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -26886,54 +26886,47 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1065":{ - "modref":"global._U1065_pt__U1066" - }, - "_U1067":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1068":{ + "_U1066":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1067":{ + "modref":"global._U1067_pt__U1068" + }, "_U1069":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1070":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1071":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1070_pt__U1071" }, "_U1072":{ + "modref":"global._U1072_pt__U1073" + }, + "_U1074":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1073":{ + "_U1075":{ + "modref":"global._U1075_pt__U1076" + }, + "_U1077":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1074":{ - "modref":"global._U1074_pt__U1075" - }, - "_U1076":{ + "_U1078":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1077":{ - "modref":"global._U1077_pt__U1078" - }, "_U1079":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -26950,23 +26943,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1082":{ - "modref":"global._U1082_pt__U1083" - }, - "_U1084":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1085":{ + "_U1083":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1086":{ + "_U1084":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1085":{ + "modref":"global._U1085_pt__U1086" + }, "_U1087":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27003,18 +26996,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1094":{ + "modref":"global._U1094_pt__U1095" + }, + "_U1096":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1095":{ + "_U1097":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1096":{ - "modref":"global._U1096_pt__U1097" - }, "_U1098":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27031,36 +27024,36 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1101":{ + "modref":"global._U1101_pt__U1102" + }, + "_U1103":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1102":{ - "modref":"global._U1102_pt__U1103" - }, "_U1104":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1105":{ - "modref":"global._U1105_pt__U1106" - }, - "_U1107":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1108":{ + "_U1106":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1109":{ + "_U1107":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1108":{ + "modref":"global._U1108_pt__U1109" + }, "_U1110":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27087,25 +27080,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1115":{ - "modref":"global._U1115_pt__U1116" - }, - "_U1117":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1118":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U1116":{ + "modref":"global._U1116_pt__U1117" }, - "_U1119":{ - "modref":"global._U1119_pt__U1120" + "_U1118":{ + "modref":"global._U1118_pt__U1119" }, - "_U1121":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U1120":{ + "modref":"global._U1120_pt__U1121" }, "_U1122":{ "genref":"mantle.reg", @@ -27151,22 +27137,15 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1132":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1133":{ - "modref":"global._U1133_pt__U1134" + "modref":"global._U1132_pt__U1133" }, - "_U1135":{ + "_U1134":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1136":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U1135":{ + "modref":"global._U1135_pt__U1136" }, "_U1137":{ "genref":"mantle.reg", @@ -27174,13 +27153,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1138":{ + "modref":"global._U1138_pt__U1139" + }, + "_U1140":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1139":{ - "modref":"global._U1139_pt__U1140" - }, "_U1141":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27197,23 +27176,16 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1144":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1145":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1144_pt__U1145" }, "_U1146":{ - "modref":"global._U1146_pt__U1147" - }, - "_U1148":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1147":{ + "modref":"global._U1147_pt__U1148" + }, "_U1149":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27235,13 +27207,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1153":{ + "modref":"global._U1153_pt__U1154" + }, + "_U1155":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1154":{ - "modref":"global._U1154_pt__U1155" - }, "_U1156":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27276,7 +27248,14 @@ "modref":"global._U1162_pt__U1163" }, "_U1164":{ - "modref":"global._U1164_pt__U1165" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1165":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1166":{ "modref":"global._U1166_pt__U1167" @@ -27297,14 +27276,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1171":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1172":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1171_pt__U1172" }, "_U1173":{ "genref":"mantle.reg", @@ -27332,34 +27304,34 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1178":{ - "modref":"global._U1178_pt__U1179" - }, - "_U1180":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1181":{ - "modref":"global._U1181_pt__U1182" + "_U1179":{ + "modref":"global._U1179_pt__U1180" }, - "_U1183":{ + "_U1181":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1184":{ - "modref":"global._U1184_pt__U1185" - }, - "_U1186":{ + "_U1182":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1187":{ + "_U1183":{ + "modref":"global._U1183_pt__U1184" + }, + "_U1185":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1186":{ + "modref":"global._U1186_pt__U1187" + }, "_U1188":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27386,13 +27358,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1193":{ - "modref":"global._U1193_pt__U1194" - }, - "_U1195":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1194":{ + "modref":"global._U1194_pt__U1195" + }, "_U1196":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -27409,7 +27381,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1199":{ - "modref":"global._U1199_pt__U1200" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1200":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1201":{ "genref":"mantle.reg", @@ -27432,28 +27411,35 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1205":{ + "modref":"global._U1205_pt__U1206" + }, + "_U1207":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1206":{ - "modref":"global._U1206_pt__U1207" - }, "_U1208":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1209":{ - "modref":"global._U1209_pt__U1210" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1211":{ + "_U1210":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1212":{ - "modref":"global._U1212_pt__U1213" + "_U1211":{ + "modref":"global._U1211_pt__U1212" + }, + "_U1213":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1214":{ "genref":"mantle.reg", @@ -27486,7 +27472,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1220":{ - "modref":"global._U1220_pt__U1221" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1221":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1222":{ "genref":"mantle.reg", @@ -27494,44 +27487,51 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1223":{ - "modref":"global._U1223_pt__U1224" - }, - "_U1225":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1226":{ + "_U1224":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1227":{ + "_U1225":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1228":{ - "modref":"global._U1228_pt__U1229" + "_U1226":{ + "modref":"global._U1226_pt__U1227" }, - "_U1230":{ + "_U1228":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1229":{ + "modref":"global._U1229_pt__U1230" + }, "_U1231":{ - "modref":"global._U1231_pt__U1232" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1233":{ - "modref":"global._U1233_pt__U1234" + "_U1232":{ + "modref":"global._U1232_pt__U1233" }, - "_U1235":{ + "_U1234":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1236":{ - "modref":"global._U1236_pt__U1237" + "_U1235":{ + "modref":"global._U1235_pt__U1236" + }, + "_U1237":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1238":{ "genref":"mantle.reg", @@ -27609,10 +27609,10 @@ } }, "connections":[ - ["_U1048.out","_U1039.in"], - ["add_1053_1067_1068.in0","_U1039.out"], + ["_U1054.out","_U1039.in"], + ["add_conv_stencil_6_1066_1067.in0","_U1039.out"], ["self.clk","_U1041.clk"], - ["mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053.out","_U1041.in"], + ["self.in0_conv_stencil.0","_U1041.in"], ["_U1042.in","_U1041.out"], ["self.clk","_U1042.clk"], ["_U1043.in","_U1042.out"], @@ -27627,22 +27627,22 @@ ["self.clk","_U1047.clk"], ["_U1048.in","_U1047.out"], ["self.clk","_U1048.clk"], - ["_U1064.out","_U1049.in"], - ["add_conv_stencil_6_1066_1067.in0","_U1049.out"], + ["_U1049.in","_U1048.out"], + ["self.clk","_U1049.clk"], + ["_U1050.in","_U1049.out"], + ["self.clk","_U1050.clk"], + ["_U1051.in","_U1050.out"], ["self.clk","_U1051.clk"], - ["self.in0_conv_stencil.0","_U1051.in"], ["_U1052.in","_U1051.out"], ["self.clk","_U1052.clk"], ["_U1053.in","_U1052.out"], ["self.clk","_U1053.clk"], ["_U1054.in","_U1053.out"], ["self.clk","_U1054.clk"], - ["_U1055.in","_U1054.out"], - ["self.clk","_U1055.clk"], - ["_U1056.in","_U1055.out"], - ["self.clk","_U1056.clk"], - ["_U1057.in","_U1056.out"], + ["_U1066.out","_U1055.in"], + ["add_1054_1065_1066.in0","_U1055.out"], ["self.clk","_U1057.clk"], + ["mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054.out","_U1057.in"], ["_U1058.in","_U1057.out"], ["self.clk","_U1058.clk"], ["_U1059.in","_U1058.out"], @@ -27657,44 +27657,42 @@ ["self.clk","_U1063.clk"], ["_U1064.in","_U1063.out"], ["self.clk","_U1064.clk"], - ["_U1073.out","_U1065.in"], - ["mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053.in0","_U1065.out"], - ["self.clk","_U1067.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.0","_U1067.in"], - ["_U1068.in","_U1067.out"], - ["self.clk","_U1068.clk"], - ["_U1069.in","_U1068.out"], + ["_U1065.in","_U1064.out"], + ["self.clk","_U1065.clk"], + ["_U1066.in","_U1065.out"], + ["self.clk","_U1066.clk"], + ["_U1069.out","_U1067.in"], + ["add_1057_1062_1063.in1","_U1067.out"], ["self.clk","_U1069.clk"], - ["_U1070.in","_U1069.out"], - ["self.clk","_U1070.clk"], - ["_U1071.in","_U1070.out"], - ["self.clk","_U1071.clk"], - ["_U1072.in","_U1071.out"], - ["self.clk","_U1072.clk"], - ["_U1073.in","_U1072.out"], - ["self.clk","_U1073.clk"], - ["_U1076.out","_U1074.in"], - ["add_1054_1065_1066.in1","_U1074.out"], - ["self.clk","_U1076.clk"], - ["add_1055_1064_1065.out","_U1076.in"], - ["_U1081.out","_U1077.in"], - ["mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056.in1","_U1077.out"], + ["add_1058_1061_1062.out","_U1069.in"], + ["add_1053_1067_1068.out","_U1070.in"], + ["self.out_conv_stencil","_U1070.out"], + ["_U1074.out","_U1072.in"], + ["add_1058_1061_1062.in1","_U1072.out"], + ["self.clk","_U1074.clk"], + ["add_1059_1060_1061.out","_U1074.in"], + ["_U1084.out","_U1075.in"], + ["add_1055_1064_1065.in0","_U1075.out"], + ["self.clk","_U1077.clk"], + ["mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055.out","_U1077.in"], + ["_U1078.in","_U1077.out"], + ["self.clk","_U1078.clk"], + ["_U1079.in","_U1078.out"], ["self.clk","_U1079.clk"], - ["self.in1_hw_input_global_wrapper_stencil.3","_U1079.in"], ["_U1080.in","_U1079.out"], ["self.clk","_U1080.clk"], ["_U1081.in","_U1080.out"], ["self.clk","_U1081.clk"], - ["_U1095.out","_U1082.in"], - ["add_1054_1065_1066.in0","_U1082.out"], + ["_U1082.in","_U1081.out"], + ["self.clk","_U1082.clk"], + ["_U1083.in","_U1082.out"], + ["self.clk","_U1083.clk"], + ["_U1084.in","_U1083.out"], ["self.clk","_U1084.clk"], - ["mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054.out","_U1084.in"], - ["_U1085.in","_U1084.out"], - ["self.clk","_U1085.clk"], - ["_U1086.in","_U1085.out"], - ["self.clk","_U1086.clk"], - ["_U1087.in","_U1086.out"], + ["_U1093.out","_U1085.in"], + ["add_1059_1060_1061.in0","_U1085.out"], ["self.clk","_U1087.clk"], + ["mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059.out","_U1087.in"], ["_U1088.in","_U1087.out"], ["self.clk","_U1088.clk"], ["_U1089.in","_U1088.out"], @@ -27707,34 +27705,34 @@ ["self.clk","_U1092.clk"], ["_U1093.in","_U1092.out"], ["self.clk","_U1093.clk"], - ["_U1094.in","_U1093.out"], - ["self.clk","_U1094.clk"], - ["_U1095.in","_U1094.out"], - ["self.clk","_U1095.clk"], - ["_U1101.out","_U1096.in"], - ["add_1058_1061_1062.in0","_U1096.out"], + ["_U1100.out","_U1094.in"], + ["mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056.in0","_U1094.out"], + ["self.clk","_U1096.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.3","_U1096.in"], + ["_U1097.in","_U1096.out"], + ["self.clk","_U1097.clk"], + ["_U1098.in","_U1097.out"], ["self.clk","_U1098.clk"], - ["mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058.out","_U1098.in"], ["_U1099.in","_U1098.out"], ["self.clk","_U1099.clk"], ["_U1100.in","_U1099.out"], ["self.clk","_U1100.clk"], - ["_U1101.in","_U1100.out"], - ["self.clk","_U1101.clk"], - ["_U1104.out","_U1102.in"], - ["add_1055_1064_1065.in1","_U1102.out"], + ["_U1107.out","_U1101.in"], + ["mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056.in1","_U1101.out"], + ["self.clk","_U1103.clk"], + ["self.in1_hw_input_global_wrapper_stencil.3","_U1103.in"], + ["_U1104.in","_U1103.out"], ["self.clk","_U1104.clk"], - ["add_1056_1063_1064.out","_U1104.in"], - ["_U1114.out","_U1105.in"], - ["add_1056_1063_1064.in0","_U1105.out"], + ["_U1105.in","_U1104.out"], + ["self.clk","_U1105.clk"], + ["_U1106.in","_U1105.out"], + ["self.clk","_U1106.clk"], + ["_U1107.in","_U1106.out"], ["self.clk","_U1107.clk"], - ["mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056.out","_U1107.in"], - ["_U1108.in","_U1107.out"], - ["self.clk","_U1108.clk"], - ["_U1109.in","_U1108.out"], - ["self.clk","_U1109.clk"], - ["_U1110.in","_U1109.out"], + ["_U1115.out","_U1108.in"], + ["mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057.in0","_U1108.out"], ["self.clk","_U1110.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.4","_U1110.in"], ["_U1111.in","_U1110.out"], ["self.clk","_U1111.clk"], ["_U1112.in","_U1111.out"], @@ -27743,22 +27741,20 @@ ["self.clk","_U1113.clk"], ["_U1114.in","_U1113.out"], ["self.clk","_U1114.clk"], - ["_U1118.out","_U1115.in"], - ["mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055.in1","_U1115.out"], - ["self.clk","_U1117.clk"], - ["self.in1_hw_input_global_wrapper_stencil.2","_U1117.in"], - ["_U1118.in","_U1117.out"], - ["self.clk","_U1118.clk"], - ["_U1122.out","_U1119.in"], - ["add_1059_1060_1061.in0","_U1119.out"], - ["self.clk","_U1121.clk"], - ["mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059.out","_U1121.in"], - ["_U1122.in","_U1121.out"], + ["_U1115.in","_U1114.out"], + ["self.clk","_U1115.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.5","_U1116.in"], + ["mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058.in0","_U1116.out"], + ["self.in1_hw_input_global_wrapper_stencil.5","_U1118.in"], + ["mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058.in1","_U1118.out"], + ["_U1122.out","_U1120.in"], + ["mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059.in0","_U1120.out"], ["self.clk","_U1122.clk"], - ["_U1132.out","_U1123.in"], - ["add_1059_1060_1061.in1","_U1123.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1122.in"], + ["_U1131.out","_U1123.in"], + ["mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060.in0","_U1123.out"], ["self.clk","_U1125.clk"], - ["mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060.out","_U1125.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1125.in"], ["_U1126.in","_U1125.out"], ["self.clk","_U1126.clk"], ["_U1127.in","_U1126.out"], @@ -27771,48 +27767,44 @@ ["self.clk","_U1130.clk"], ["_U1131.in","_U1130.out"], ["self.clk","_U1131.clk"], - ["_U1132.in","_U1131.out"], - ["self.clk","_U1132.clk"], - ["_U1138.out","_U1133.in"], - ["mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057.in0","_U1133.out"], - ["self.clk","_U1135.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.4","_U1135.in"], - ["_U1136.in","_U1135.out"], - ["self.clk","_U1136.clk"], - ["_U1137.in","_U1136.out"], + ["_U1134.out","_U1132.in"], + ["mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059.in1","_U1132.out"], + ["self.clk","_U1134.clk"], + ["self.in1_hw_input_global_wrapper_stencil.6","_U1134.in"], + ["_U1137.out","_U1135.in"], + ["add_conv_stencil_6_1066_1067.in1","_U1135.out"], ["self.clk","_U1137.clk"], - ["_U1138.in","_U1137.out"], - ["self.clk","_U1138.clk"], - ["_U1145.out","_U1139.in"], - ["mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058.in1","_U1139.out"], + ["add_1054_1065_1066.out","_U1137.in"], + ["_U1143.out","_U1138.in"], + ["add_1057_1062_1063.in0","_U1138.out"], + ["self.clk","_U1140.clk"], + ["mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057.out","_U1140.in"], + ["_U1141.in","_U1140.out"], ["self.clk","_U1141.clk"], - ["self.in1_hw_input_global_wrapper_stencil.5","_U1141.in"], ["_U1142.in","_U1141.out"], ["self.clk","_U1142.clk"], ["_U1143.in","_U1142.out"], ["self.clk","_U1143.clk"], - ["_U1144.in","_U1143.out"], - ["self.clk","_U1144.clk"], - ["_U1145.in","_U1144.out"], - ["self.clk","_U1145.clk"], - ["_U1153.out","_U1146.in"], - ["mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059.in0","_U1146.out"], - ["self.clk","_U1148.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1148.in"], - ["_U1149.in","_U1148.out"], + ["_U1146.out","_U1144.in"], + ["add_1054_1065_1066.in1","_U1144.out"], + ["self.clk","_U1146.clk"], + ["add_1055_1064_1065.out","_U1146.in"], + ["_U1152.out","_U1147.in"], + ["mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055.in0","_U1147.out"], ["self.clk","_U1149.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.2","_U1149.in"], ["_U1150.in","_U1149.out"], ["self.clk","_U1150.clk"], ["_U1151.in","_U1150.out"], ["self.clk","_U1151.clk"], ["_U1152.in","_U1151.out"], ["self.clk","_U1152.clk"], - ["_U1153.in","_U1152.out"], - ["self.clk","_U1153.clk"], - ["_U1161.out","_U1154.in"], - ["mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059.in1","_U1154.out"], + ["_U1161.out","_U1153.in"], + ["mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060.in1","_U1153.out"], + ["self.clk","_U1155.clk"], + ["self.in1_hw_input_global_wrapper_stencil.7","_U1155.in"], + ["_U1156.in","_U1155.out"], ["self.clk","_U1156.clk"], - ["self.in1_hw_input_global_wrapper_stencil.6","_U1156.in"], ["_U1157.in","_U1156.out"], ["self.clk","_U1157.clk"], ["_U1158.in","_U1157.out"], @@ -27823,24 +27815,24 @@ ["self.clk","_U1160.clk"], ["_U1161.in","_U1160.out"], ["self.clk","_U1161.clk"], - ["self.in1_hw_input_global_wrapper_stencil.7","_U1162.in"], - ["mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060.in1","_U1162.out"], - ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1164.in"], - ["mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060.in0","_U1164.out"], - ["_U1177.out","_U1166.in"], - ["add_1055_1064_1065.in0","_U1166.out"], + ["_U1165.out","_U1162.in"], + ["mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053.in0","_U1162.out"], + ["self.clk","_U1164.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","_U1164.in"], + ["_U1165.in","_U1164.out"], + ["self.clk","_U1165.clk"], + ["_U1170.out","_U1166.in"], + ["mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054.in0","_U1166.out"], ["self.clk","_U1168.clk"], - ["mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055.out","_U1168.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.1","_U1168.in"], ["_U1169.in","_U1168.out"], ["self.clk","_U1169.clk"], ["_U1170.in","_U1169.out"], ["self.clk","_U1170.clk"], - ["_U1171.in","_U1170.out"], - ["self.clk","_U1171.clk"], - ["_U1172.in","_U1171.out"], - ["self.clk","_U1172.clk"], - ["_U1173.in","_U1172.out"], + ["_U1178.out","_U1171.in"], + ["mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057.in1","_U1171.out"], ["self.clk","_U1173.clk"], + ["self.in1_hw_input_global_wrapper_stencil.4","_U1173.in"], ["_U1174.in","_U1173.out"], ["self.clk","_U1174.clk"], ["_U1175.in","_U1174.out"], @@ -27849,22 +27841,22 @@ ["self.clk","_U1176.clk"], ["_U1177.in","_U1176.out"], ["self.clk","_U1177.clk"], - ["_U1180.out","_U1178.in"], - ["add_conv_stencil_6_1066_1067.in1","_U1178.out"], - ["self.clk","_U1180.clk"], - ["add_1054_1065_1066.out","_U1180.in"], - ["_U1183.out","_U1181.in"], - ["add_1058_1061_1062.in1","_U1181.out"], - ["self.clk","_U1183.clk"], - ["add_1059_1060_1061.out","_U1183.in"], - ["_U1192.out","_U1184.in"], - ["mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053.in1","_U1184.out"], - ["self.clk","_U1186.clk"], - ["self.in1_hw_input_global_wrapper_stencil.0","_U1186.in"], - ["_U1187.in","_U1186.out"], - ["self.clk","_U1187.clk"], - ["_U1188.in","_U1187.out"], + ["_U1178.in","_U1177.out"], + ["self.clk","_U1178.clk"], + ["_U1182.out","_U1179.in"], + ["mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053.in1","_U1179.out"], + ["self.clk","_U1181.clk"], + ["self.in1_hw_input_global_wrapper_stencil.0","_U1181.in"], + ["_U1182.in","_U1181.out"], + ["self.clk","_U1182.clk"], + ["_U1185.out","_U1183.in"], + ["add_1055_1064_1065.in1","_U1183.out"], + ["self.clk","_U1185.clk"], + ["add_1056_1063_1064.out","_U1185.in"], + ["_U1193.out","_U1186.in"], + ["add_1056_1063_1064.in0","_U1186.out"], ["self.clk","_U1188.clk"], + ["mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056.out","_U1188.in"], ["_U1189.in","_U1188.out"], ["self.clk","_U1189.clk"], ["_U1190.in","_U1189.out"], @@ -27873,40 +27865,44 @@ ["self.clk","_U1191.clk"], ["_U1192.in","_U1191.out"], ["self.clk","_U1192.clk"], - ["_U1198.out","_U1193.in"], - ["mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057.in1","_U1193.out"], - ["self.clk","_U1195.clk"], - ["self.in1_hw_input_global_wrapper_stencil.4","_U1195.in"], - ["_U1196.in","_U1195.out"], + ["_U1193.in","_U1192.out"], + ["self.clk","_U1193.clk"], + ["_U1204.out","_U1194.in"], + ["add_1058_1061_1062.in0","_U1194.out"], ["self.clk","_U1196.clk"], + ["mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058.out","_U1196.in"], ["_U1197.in","_U1196.out"], ["self.clk","_U1197.clk"], ["_U1198.in","_U1197.out"], ["self.clk","_U1198.clk"], - ["_U1205.out","_U1199.in"], - ["mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058.in0","_U1199.out"], + ["_U1199.in","_U1198.out"], + ["self.clk","_U1199.clk"], + ["_U1200.in","_U1199.out"], + ["self.clk","_U1200.clk"], + ["_U1201.in","_U1200.out"], ["self.clk","_U1201.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.5","_U1201.in"], ["_U1202.in","_U1201.out"], ["self.clk","_U1202.clk"], ["_U1203.in","_U1202.out"], ["self.clk","_U1203.clk"], ["_U1204.in","_U1203.out"], ["self.clk","_U1204.clk"], - ["_U1205.in","_U1204.out"], - ["self.clk","_U1205.clk"], - ["_U1208.out","_U1206.in"], - ["mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054.in0","_U1206.out"], + ["_U1210.out","_U1205.in"], + ["mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055.in1","_U1205.out"], + ["self.clk","_U1207.clk"], + ["self.in1_hw_input_global_wrapper_stencil.2","_U1207.in"], + ["_U1208.in","_U1207.out"], ["self.clk","_U1208.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.1","_U1208.in"], - ["_U1211.out","_U1209.in"], - ["add_1056_1063_1064.in1","_U1209.out"], - ["self.clk","_U1211.clk"], - ["add_1057_1062_1063.out","_U1211.in"], - ["_U1219.out","_U1212.in"], - ["add_1057_1062_1063.in0","_U1212.out"], + ["_U1209.in","_U1208.out"], + ["self.clk","_U1209.clk"], + ["_U1210.in","_U1209.out"], + ["self.clk","_U1210.clk"], + ["_U1225.out","_U1211.in"], + ["add_1053_1067_1068.in0","_U1211.out"], + ["self.clk","_U1213.clk"], + ["mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053.out","_U1213.in"], + ["_U1214.in","_U1213.out"], ["self.clk","_U1214.clk"], - ["mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057.out","_U1214.in"], ["_U1215.in","_U1214.out"], ["self.clk","_U1215.clk"], ["_U1216.in","_U1215.out"], @@ -27917,32 +27913,36 @@ ["self.clk","_U1218.clk"], ["_U1219.in","_U1218.out"], ["self.clk","_U1219.clk"], - ["_U1222.out","_U1220.in"], - ["add_1057_1062_1063.in1","_U1220.out"], + ["_U1220.in","_U1219.out"], + ["self.clk","_U1220.clk"], + ["_U1221.in","_U1220.out"], + ["self.clk","_U1221.clk"], + ["_U1222.in","_U1221.out"], ["self.clk","_U1222.clk"], - ["add_1058_1061_1062.out","_U1222.in"], - ["_U1227.out","_U1223.in"], - ["mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056.in0","_U1223.out"], + ["_U1223.in","_U1222.out"], + ["self.clk","_U1223.clk"], + ["_U1224.in","_U1223.out"], + ["self.clk","_U1224.clk"], + ["_U1225.in","_U1224.out"], ["self.clk","_U1225.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.3","_U1225.in"], - ["_U1226.in","_U1225.out"], - ["self.clk","_U1226.clk"], - ["_U1227.in","_U1226.out"], - ["self.clk","_U1227.clk"], - ["_U1230.out","_U1228.in"], - ["add_1053_1067_1068.in1","_U1228.out"], - ["self.clk","_U1230.clk"], - ["add_conv_stencil_6_1066_1067.out","_U1230.in"], - ["add_1053_1067_1068.out","_U1231.in"], - ["self.out_conv_stencil","_U1231.out"], - ["_U1235.out","_U1233.in"], - ["mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054.in1","_U1233.out"], - ["self.clk","_U1235.clk"], - ["self.in1_hw_input_global_wrapper_stencil.1","_U1235.in"], - ["_U1239.out","_U1236.in"], - ["mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055.in0","_U1236.out"], + ["_U1228.out","_U1226.in"], + ["add_1056_1063_1064.in1","_U1226.out"], + ["self.clk","_U1228.clk"], + ["add_1057_1062_1063.out","_U1228.in"], + ["_U1231.out","_U1229.in"], + ["add_1059_1060_1061.in1","_U1229.out"], + ["self.clk","_U1231.clk"], + ["mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060.out","_U1231.in"], + ["_U1234.out","_U1232.in"], + ["add_1053_1067_1068.in1","_U1232.out"], + ["self.clk","_U1234.clk"], + ["add_conv_stencil_6_1066_1067.out","_U1234.in"], + ["_U1239.out","_U1235.in"], + ["mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054.in1","_U1235.out"], + ["self.clk","_U1237.clk"], + ["self.in1_hw_input_global_wrapper_stencil.1","_U1237.in"], + ["_U1238.in","_U1237.out"], ["self.clk","_U1238.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.2","_U1238.in"], ["_U1239.in","_U1238.out"], ["self.clk","_U1239.clk"] ] @@ -28069,10 +28069,24 @@ "modref":"global._U1240_pt__U1241" }, "_U1242":{ - "modref":"global._U1242_pt__U1243" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1243":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1244":{ - "modref":"global._U1244_pt__U1245" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1245":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1246":{ "genref":"mantle.reg", @@ -28080,75 +28094,75 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1247":{ - "modref":"global._U1247_pt__U1248" - }, - "_U1249":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1250":{ - "modref":"global._U1250_pt__U1251" - }, - "_U1252":{ + "_U1248":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1253":{ - "modref":"global._U1253_pt__U1254" - }, - "_U1255":{ + "_U1249":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1256":{ + "_U1250":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1257":{ + "_U1251":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1258":{ + "_U1252":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1259":{ - "modref":"global._U1259_pt__U1260" - }, - "_U1261":{ + "_U1253":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1262":{ - "modref":"global._U1262_pt__U1263" - }, - "_U1264":{ + "_U1254":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1265":{ + "_U1255":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1266":{ + "_U1256":{ + "modref":"global._U1256_pt__U1257" + }, + "_U1258":{ + "modref":"global._U1258_pt__U1259" + }, + "_U1260":{ + "modref":"global._U1260_pt__U1261" + }, + "_U1262":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1267":{ + "_U1263":{ + "modref":"global._U1263_pt__U1264" + }, + "_U1265":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1266":{ + "modref":"global._U1266_pt__U1267" + }, "_U1268":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28160,41 +28174,41 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1270":{ - "modref":"global._U1270_pt__U1271" - }, - "_U1272":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1273":{ + "_U1271":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1274":{ + "_U1272":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1275":{ + "_U1273":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1274":{ + "modref":"global._U1274_pt__U1275" + }, "_U1276":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1277":{ + "modref":"global._U1277_pt__U1278" + }, + "_U1279":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1278":{ - "modref":"global._U1278_pt__U1279" - }, "_U1280":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28211,28 +28225,28 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1283":{ + "modref":"global._U1283_pt__U1284" + }, + "_U1285":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1284":{ + "_U1286":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1285":{ + "_U1287":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1286":{ + "_U1288":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1287":{ - "modref":"global._U1287_pt__U1288" - }, "_U1289":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28249,14 +28263,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1292":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1293":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1292_pt__U1293" }, "_U1294":{ "genref":"mantle.reg", @@ -28269,23 +28276,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1296":{ - "modref":"global._U1296_pt__U1297" - }, - "_U1298":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1299":{ + "_U1297":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1300":{ + "_U1298":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1299":{ + "modref":"global._U1299_pt__U1300" + }, "_U1301":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28317,79 +28324,79 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1307":{ + "modref":"global._U1307_pt__U1308" + }, + "_U1309":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1308":{ + "_U1310":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1309":{ + "_U1311":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1310":{ + "_U1312":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1311":{ + "_U1313":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1312":{ + "_U1314":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1313":{ - "modref":"global._U1313_pt__U1314" - }, "_U1315":{ + "modref":"global._U1315_pt__U1316" + }, + "_U1317":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1316":{ - "modref":"global._U1316_pt__U1317" - }, "_U1318":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1319":{ - "modref":"global._U1319_pt__U1320" - }, - "_U1321":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1322":{ + "_U1320":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1323":{ + "_U1321":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1324":{ + "_U1322":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1325":{ + "_U1323":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1324":{ + "modref":"global._U1324_pt__U1325" + }, "_U1326":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28416,7 +28423,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1331":{ - "modref":"global._U1331_pt__U1332" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1332":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1333":{ "genref":"mantle.reg", @@ -28424,54 +28438,54 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1334":{ - "modref":"global._U1334_pt__U1335" - }, - "_U1336":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1337":{ + "_U1335":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1338":{ + "_U1336":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1339":{ + "_U1337":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1340":{ - "modref":"global._U1340_pt__U1341" + "_U1338":{ + "modref":"global._U1338_pt__U1339" }, - "_U1342":{ + "_U1340":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1341":{ + "modref":"global._U1341_pt__U1342" + }, "_U1343":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1344":{ + "modref":"global._U1344_pt__U1345" + }, + "_U1346":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1345":{ + "_U1347":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1346":{ - "modref":"global._U1346_pt__U1347" - }, "_U1348":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28498,23 +28512,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1353":{ - "modref":"global._U1353_pt__U1354" - }, - "_U1355":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1356":{ + "_U1354":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1357":{ + "_U1355":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1356":{ + "modref":"global._U1356_pt__U1357" + }, "_U1358":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28526,13 +28540,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1360":{ - "modref":"global._U1360_pt__U1361" - }, - "_U1362":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1361":{ + "modref":"global._U1361_pt__U1362" + }, "_U1363":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28549,36 +28563,36 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1366":{ + "modref":"global._U1366_pt__U1367" + }, + "_U1368":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1367":{ + "_U1369":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1368":{ + "_U1370":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1369":{ + "_U1371":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1370":{ - "modref":"global._U1370_pt__U1371" - }, "_U1372":{ + "modref":"global._U1372_pt__U1373" + }, + "_U1374":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1373":{ - "modref":"global._U1373_pt__U1374" - }, "_U1375":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28595,23 +28609,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1378":{ + "modref":"global._U1378_pt__U1379" + }, + "_U1380":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1379":{ + "_U1381":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1380":{ + "_U1382":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1381":{ - "modref":"global._U1381_pt__U1382" - }, "_U1383":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28631,13 +28645,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1388":{ + "modref":"global._U1388_pt__U1389" + }, + "_U1390":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1389":{ - "modref":"global._U1389_pt__U1390" - }, "_U1391":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28654,7 +28668,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1394":{ - "modref":"global._U1394_pt__U1395" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1395":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1396":{ "genref":"mantle.reg", @@ -28667,13 +28688,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1398":{ + "modref":"global._U1398_pt__U1399" + }, + "_U1400":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1399":{ - "modref":"global._U1399_pt__U1400" - }, "_U1401":{ "modref":"global._U1401_pt__U1402" }, @@ -28688,14 +28709,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1405":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1406":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1405_pt__U1406" }, "_U1407":{ "genref":"mantle.reg", @@ -28708,14 +28722,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1409":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1410":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1409_pt__U1410" }, "_U1411":{ "genref":"mantle.reg", @@ -28738,82 +28745,82 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1415":{ - "modref":"global._U1415_pt__U1416" - }, - "_U1417":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1418":{ - "modref":"global._U1418_pt__U1419" - }, - "_U1420":{ + "_U1416":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1421":{ + "_U1417":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1422":{ - "modref":"global._U1422_pt__U1423" - }, - "_U1424":{ + "_U1418":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1425":{ - "modref":"global._U1425_pt__U1426" - }, - "_U1427":{ + "_U1419":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1428":{ + "_U1420":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1429":{ + "_U1421":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1430":{ + "_U1422":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1431":{ + "_U1423":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1432":{ + "_U1424":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1433":{ + "_U1425":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1434":{ + "_U1426":{ + "modref":"global._U1426_pt__U1427" + }, + "_U1428":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1435":{ + "_U1429":{ + "modref":"global._U1429_pt__U1430" + }, + "_U1431":{ + "modref":"global._U1431_pt__U1432" + }, + "_U1433":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1434":{ + "modref":"global._U1434_pt__U1435" + }, "_U1436":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -28825,14 +28832,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1438":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1439":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1438_pt__U1439" }, "_U1440":{ "genref":"mantle.reg", @@ -28905,106 +28905,108 @@ } }, "connections":[ - ["self.in2_hw_kernel_global_wrapper_stencil.0","_U1240.in"], - ["mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120.in0","_U1240.out"], - ["self.in1_hw_input_global_wrapper_stencil.0","_U1242.in"], - ["mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120.in1","_U1242.out"], - ["_U1246.out","_U1244.in"], - ["mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121.in0","_U1244.out"], + ["_U1255.out","_U1240.in"], + ["add_conv_stencil_7_1133_1134.in0","_U1240.out"], + ["self.clk","_U1242.clk"], + ["self.in0_conv_stencil.0","_U1242.in"], + ["_U1243.in","_U1242.out"], + ["self.clk","_U1243.clk"], + ["_U1244.in","_U1243.out"], + ["self.clk","_U1244.clk"], + ["_U1245.in","_U1244.out"], + ["self.clk","_U1245.clk"], + ["_U1246.in","_U1245.out"], ["self.clk","_U1246.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.1","_U1246.in"], - ["_U1249.out","_U1247.in"], - ["mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121.in1","_U1247.out"], + ["_U1247.in","_U1246.out"], + ["self.clk","_U1247.clk"], + ["_U1248.in","_U1247.out"], + ["self.clk","_U1248.clk"], + ["_U1249.in","_U1248.out"], ["self.clk","_U1249.clk"], - ["self.in1_hw_input_global_wrapper_stencil.1","_U1249.in"], - ["_U1252.out","_U1250.in"], - ["add_1124_1129_1130.in1","_U1250.out"], + ["_U1250.in","_U1249.out"], + ["self.clk","_U1250.clk"], + ["_U1251.in","_U1250.out"], + ["self.clk","_U1251.clk"], + ["_U1252.in","_U1251.out"], ["self.clk","_U1252.clk"], - ["add_1125_1128_1129.out","_U1252.in"], - ["_U1258.out","_U1253.in"], - ["add_1125_1128_1129.in0","_U1253.out"], + ["_U1253.in","_U1252.out"], + ["self.clk","_U1253.clk"], + ["_U1254.in","_U1253.out"], + ["self.clk","_U1254.clk"], + ["_U1255.in","_U1254.out"], ["self.clk","_U1255.clk"], - ["mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125.out","_U1255.in"], - ["_U1256.in","_U1255.out"], - ["self.clk","_U1256.clk"], - ["_U1257.in","_U1256.out"], - ["self.clk","_U1257.clk"], - ["_U1258.in","_U1257.out"], - ["self.clk","_U1258.clk"], - ["_U1261.out","_U1259.in"], - ["add_1125_1128_1129.in1","_U1259.out"], - ["self.clk","_U1261.clk"], - ["add_1126_1127_1128.out","_U1261.in"], - ["_U1269.out","_U1262.in"], - ["mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126.in0","_U1262.out"], - ["self.clk","_U1264.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1264.in"], - ["_U1265.in","_U1264.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","_U1256.in"], + ["mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120.in0","_U1256.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","_U1258.in"], + ["mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120.in1","_U1258.out"], + ["_U1262.out","_U1260.in"], + ["mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121.in0","_U1260.out"], + ["self.clk","_U1262.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.1","_U1262.in"], + ["_U1265.out","_U1263.in"], + ["add_1123_1130_1131.in1","_U1263.out"], ["self.clk","_U1265.clk"], - ["_U1266.in","_U1265.out"], - ["self.clk","_U1266.clk"], - ["_U1267.in","_U1266.out"], - ["self.clk","_U1267.clk"], - ["_U1268.in","_U1267.out"], + ["add_1124_1129_1130.out","_U1265.in"], + ["_U1273.out","_U1266.in"], + ["add_1124_1129_1130.in0","_U1266.out"], ["self.clk","_U1268.clk"], + ["mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124.out","_U1268.in"], ["_U1269.in","_U1268.out"], ["self.clk","_U1269.clk"], - ["_U1277.out","_U1270.in"], - ["mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126.in1","_U1270.out"], + ["_U1270.in","_U1269.out"], + ["self.clk","_U1270.clk"], + ["_U1271.in","_U1270.out"], + ["self.clk","_U1271.clk"], + ["_U1272.in","_U1271.out"], ["self.clk","_U1272.clk"], - ["self.in1_hw_input_global_wrapper_stencil.6","_U1272.in"], ["_U1273.in","_U1272.out"], ["self.clk","_U1273.clk"], - ["_U1274.in","_U1273.out"], - ["self.clk","_U1274.clk"], - ["_U1275.in","_U1274.out"], - ["self.clk","_U1275.clk"], - ["_U1276.in","_U1275.out"], + ["_U1276.out","_U1274.in"], + ["add_1124_1129_1130.in1","_U1274.out"], ["self.clk","_U1276.clk"], - ["_U1277.in","_U1276.out"], - ["self.clk","_U1277.clk"], - ["_U1286.out","_U1278.in"], - ["mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127.in0","_U1278.out"], + ["add_1125_1128_1129.out","_U1276.in"], + ["_U1282.out","_U1277.in"], + ["add_1125_1128_1129.in0","_U1277.out"], + ["self.clk","_U1279.clk"], + ["mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125.out","_U1279.in"], + ["_U1280.in","_U1279.out"], ["self.clk","_U1280.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1280.in"], ["_U1281.in","_U1280.out"], ["self.clk","_U1281.clk"], ["_U1282.in","_U1281.out"], ["self.clk","_U1282.clk"], - ["_U1283.in","_U1282.out"], - ["self.clk","_U1283.clk"], - ["_U1284.in","_U1283.out"], - ["self.clk","_U1284.clk"], - ["_U1285.in","_U1284.out"], + ["_U1291.out","_U1283.in"], + ["mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127.in1","_U1283.out"], ["self.clk","_U1285.clk"], + ["self.in1_hw_input_global_wrapper_stencil.7","_U1285.in"], ["_U1286.in","_U1285.out"], ["self.clk","_U1286.clk"], - ["_U1295.out","_U1287.in"], - ["mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127.in1","_U1287.out"], + ["_U1287.in","_U1286.out"], + ["self.clk","_U1287.clk"], + ["_U1288.in","_U1287.out"], + ["self.clk","_U1288.clk"], + ["_U1289.in","_U1288.out"], ["self.clk","_U1289.clk"], - ["self.in1_hw_input_global_wrapper_stencil.7","_U1289.in"], ["_U1290.in","_U1289.out"], ["self.clk","_U1290.clk"], ["_U1291.in","_U1290.out"], ["self.clk","_U1291.clk"], - ["_U1292.in","_U1291.out"], - ["self.clk","_U1292.clk"], - ["_U1293.in","_U1292.out"], - ["self.clk","_U1293.clk"], - ["_U1294.in","_U1293.out"], + ["_U1298.out","_U1292.in"], + ["mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125.in1","_U1292.out"], ["self.clk","_U1294.clk"], + ["self.in1_hw_input_global_wrapper_stencil.5","_U1294.in"], ["_U1295.in","_U1294.out"], ["self.clk","_U1295.clk"], - ["_U1312.out","_U1296.in"], - ["add_1120_1134_1135.in0","_U1296.out"], + ["_U1296.in","_U1295.out"], + ["self.clk","_U1296.clk"], + ["_U1297.in","_U1296.out"], + ["self.clk","_U1297.clk"], + ["_U1298.in","_U1297.out"], ["self.clk","_U1298.clk"], - ["mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120.out","_U1298.in"], - ["_U1299.in","_U1298.out"], - ["self.clk","_U1299.clk"], - ["_U1300.in","_U1299.out"], - ["self.clk","_U1300.clk"], - ["_U1301.in","_U1300.out"], + ["_U1306.out","_U1299.in"], + ["mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126.in0","_U1299.out"], ["self.clk","_U1301.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1301.in"], ["_U1302.in","_U1301.out"], ["self.clk","_U1302.clk"], ["_U1303.in","_U1302.out"], @@ -29015,40 +29017,40 @@ ["self.clk","_U1305.clk"], ["_U1306.in","_U1305.out"], ["self.clk","_U1306.clk"], - ["_U1307.in","_U1306.out"], - ["self.clk","_U1307.clk"], - ["_U1308.in","_U1307.out"], - ["self.clk","_U1308.clk"], - ["_U1309.in","_U1308.out"], + ["_U1314.out","_U1307.in"], + ["mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126.in1","_U1307.out"], ["self.clk","_U1309.clk"], + ["self.in1_hw_input_global_wrapper_stencil.6","_U1309.in"], ["_U1310.in","_U1309.out"], ["self.clk","_U1310.clk"], ["_U1311.in","_U1310.out"], ["self.clk","_U1311.clk"], ["_U1312.in","_U1311.out"], ["self.clk","_U1312.clk"], - ["_U1315.out","_U1313.in"], - ["add_1120_1134_1135.in1","_U1313.out"], - ["self.clk","_U1315.clk"], - ["add_conv_stencil_7_1133_1134.out","_U1315.in"], - ["_U1318.out","_U1316.in"], - ["add_conv_stencil_7_1133_1134.in1","_U1316.out"], + ["_U1313.in","_U1312.out"], + ["self.clk","_U1313.clk"], + ["_U1314.in","_U1313.out"], + ["self.clk","_U1314.clk"], + ["_U1323.out","_U1315.in"], + ["mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127.in0","_U1315.out"], + ["self.clk","_U1317.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1317.in"], + ["_U1318.in","_U1317.out"], ["self.clk","_U1318.clk"], - ["add_1121_1132_1133.out","_U1318.in"], - ["_U1330.out","_U1319.in"], - ["add_1122_1131_1132.in0","_U1319.out"], + ["_U1319.in","_U1318.out"], + ["self.clk","_U1319.clk"], + ["_U1320.in","_U1319.out"], + ["self.clk","_U1320.clk"], + ["_U1321.in","_U1320.out"], ["self.clk","_U1321.clk"], - ["mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122.out","_U1321.in"], ["_U1322.in","_U1321.out"], ["self.clk","_U1322.clk"], ["_U1323.in","_U1322.out"], ["self.clk","_U1323.clk"], - ["_U1324.in","_U1323.out"], - ["self.clk","_U1324.clk"], - ["_U1325.in","_U1324.out"], - ["self.clk","_U1325.clk"], - ["_U1326.in","_U1325.out"], + ["_U1337.out","_U1324.in"], + ["add_1121_1132_1133.in0","_U1324.out"], ["self.clk","_U1326.clk"], + ["mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121.out","_U1326.in"], ["_U1327.in","_U1326.out"], ["self.clk","_U1327.clk"], ["_U1328.in","_U1327.out"], @@ -29057,34 +29059,36 @@ ["self.clk","_U1329.clk"], ["_U1330.in","_U1329.out"], ["self.clk","_U1330.clk"], - ["_U1333.out","_U1331.in"], - ["add_1122_1131_1132.in1","_U1331.out"], + ["_U1331.in","_U1330.out"], + ["self.clk","_U1331.clk"], + ["_U1332.in","_U1331.out"], + ["self.clk","_U1332.clk"], + ["_U1333.in","_U1332.out"], ["self.clk","_U1333.clk"], - ["add_1123_1130_1131.out","_U1333.in"], - ["_U1339.out","_U1334.in"], - ["mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124.in0","_U1334.out"], + ["_U1334.in","_U1333.out"], + ["self.clk","_U1334.clk"], + ["_U1335.in","_U1334.out"], + ["self.clk","_U1335.clk"], + ["_U1336.in","_U1335.out"], ["self.clk","_U1336.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.4","_U1336.in"], ["_U1337.in","_U1336.out"], ["self.clk","_U1337.clk"], - ["_U1338.in","_U1337.out"], - ["self.clk","_U1338.clk"], - ["_U1339.in","_U1338.out"], - ["self.clk","_U1339.clk"], - ["_U1345.out","_U1340.in"], - ["mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124.in1","_U1340.out"], - ["self.clk","_U1342.clk"], - ["self.in1_hw_input_global_wrapper_stencil.4","_U1342.in"], - ["_U1343.in","_U1342.out"], + ["_U1340.out","_U1338.in"], + ["add_1121_1132_1133.in1","_U1338.out"], + ["self.clk","_U1340.clk"], + ["add_1122_1131_1132.out","_U1340.in"], + ["_U1343.out","_U1341.in"], + ["add_conv_stencil_7_1133_1134.in1","_U1341.out"], ["self.clk","_U1343.clk"], - ["_U1344.in","_U1343.out"], - ["self.clk","_U1344.clk"], - ["_U1345.in","_U1344.out"], - ["self.clk","_U1345.clk"], - ["_U1352.out","_U1346.in"], - ["mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125.in0","_U1346.out"], + ["add_1121_1132_1133.out","_U1343.in"], + ["_U1355.out","_U1344.in"], + ["add_1122_1131_1132.in0","_U1344.out"], + ["self.clk","_U1346.clk"], + ["mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122.out","_U1346.in"], + ["_U1347.in","_U1346.out"], + ["self.clk","_U1347.clk"], + ["_U1348.in","_U1347.out"], ["self.clk","_U1348.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.5","_U1348.in"], ["_U1349.in","_U1348.out"], ["self.clk","_U1349.clk"], ["_U1350.in","_U1349.out"], @@ -29093,154 +29097,150 @@ ["self.clk","_U1351.clk"], ["_U1352.in","_U1351.out"], ["self.clk","_U1352.clk"], - ["_U1359.out","_U1353.in"], - ["mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125.in1","_U1353.out"], + ["_U1353.in","_U1352.out"], + ["self.clk","_U1353.clk"], + ["_U1354.in","_U1353.out"], + ["self.clk","_U1354.clk"], + ["_U1355.in","_U1354.out"], ["self.clk","_U1355.clk"], - ["self.in1_hw_input_global_wrapper_stencil.5","_U1355.in"], - ["_U1356.in","_U1355.out"], - ["self.clk","_U1356.clk"], - ["_U1357.in","_U1356.out"], - ["self.clk","_U1357.clk"], - ["_U1358.in","_U1357.out"], + ["_U1360.out","_U1356.in"], + ["mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123.in0","_U1356.out"], ["self.clk","_U1358.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.3","_U1358.in"], ["_U1359.in","_U1358.out"], ["self.clk","_U1359.clk"], - ["_U1369.out","_U1360.in"], - ["add_1123_1130_1131.in0","_U1360.out"], - ["self.clk","_U1362.clk"], - ["mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123.out","_U1362.in"], - ["_U1363.in","_U1362.out"], + ["_U1360.in","_U1359.out"], + ["self.clk","_U1360.clk"], + ["_U1365.out","_U1361.in"], + ["mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123.in1","_U1361.out"], ["self.clk","_U1363.clk"], + ["self.in1_hw_input_global_wrapper_stencil.3","_U1363.in"], ["_U1364.in","_U1363.out"], ["self.clk","_U1364.clk"], ["_U1365.in","_U1364.out"], ["self.clk","_U1365.clk"], - ["_U1366.in","_U1365.out"], - ["self.clk","_U1366.clk"], - ["_U1367.in","_U1366.out"], - ["self.clk","_U1367.clk"], - ["_U1368.in","_U1367.out"], + ["_U1371.out","_U1366.in"], + ["mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124.in0","_U1366.out"], ["self.clk","_U1368.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.4","_U1368.in"], ["_U1369.in","_U1368.out"], ["self.clk","_U1369.clk"], - ["_U1372.out","_U1370.in"], - ["add_1123_1130_1131.in1","_U1370.out"], - ["self.clk","_U1372.clk"], - ["add_1124_1129_1130.out","_U1372.in"], - ["_U1380.out","_U1373.in"], - ["add_1124_1129_1130.in0","_U1373.out"], + ["_U1370.in","_U1369.out"], + ["self.clk","_U1370.clk"], + ["_U1371.in","_U1370.out"], + ["self.clk","_U1371.clk"], + ["_U1377.out","_U1372.in"], + ["mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124.in1","_U1372.out"], + ["self.clk","_U1374.clk"], + ["self.in1_hw_input_global_wrapper_stencil.4","_U1374.in"], + ["_U1375.in","_U1374.out"], ["self.clk","_U1375.clk"], - ["mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124.out","_U1375.in"], ["_U1376.in","_U1375.out"], ["self.clk","_U1376.clk"], ["_U1377.in","_U1376.out"], ["self.clk","_U1377.clk"], - ["_U1378.in","_U1377.out"], - ["self.clk","_U1378.clk"], - ["_U1379.in","_U1378.out"], - ["self.clk","_U1379.clk"], - ["_U1380.in","_U1379.out"], + ["_U1384.out","_U1378.in"], + ["mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125.in0","_U1378.out"], ["self.clk","_U1380.clk"], - ["_U1384.out","_U1381.in"], - ["mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122.in0","_U1381.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.5","_U1380.in"], + ["_U1381.in","_U1380.out"], + ["self.clk","_U1381.clk"], + ["_U1382.in","_U1381.out"], + ["self.clk","_U1382.clk"], + ["_U1383.in","_U1382.out"], ["self.clk","_U1383.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.2","_U1383.in"], ["_U1384.in","_U1383.out"], ["self.clk","_U1384.clk"], - ["_U1388.out","_U1385.in"], - ["mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122.in1","_U1385.out"], + ["_U1387.out","_U1385.in"], + ["add_1122_1131_1132.in1","_U1385.out"], ["self.clk","_U1387.clk"], - ["self.in1_hw_input_global_wrapper_stencil.2","_U1387.in"], - ["_U1388.in","_U1387.out"], - ["self.clk","_U1388.clk"], - ["_U1393.out","_U1389.in"], - ["mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123.in0","_U1389.out"], + ["add_1123_1130_1131.out","_U1387.in"], + ["_U1397.out","_U1388.in"], + ["add_1123_1130_1131.in0","_U1388.out"], + ["self.clk","_U1390.clk"], + ["mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123.out","_U1390.in"], + ["_U1391.in","_U1390.out"], ["self.clk","_U1391.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.3","_U1391.in"], ["_U1392.in","_U1391.out"], ["self.clk","_U1392.clk"], ["_U1393.in","_U1392.out"], ["self.clk","_U1393.clk"], - ["_U1398.out","_U1394.in"], - ["mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123.in1","_U1394.out"], + ["_U1394.in","_U1393.out"], + ["self.clk","_U1394.clk"], + ["_U1395.in","_U1394.out"], + ["self.clk","_U1395.clk"], + ["_U1396.in","_U1395.out"], ["self.clk","_U1396.clk"], - ["self.in1_hw_input_global_wrapper_stencil.3","_U1396.in"], ["_U1397.in","_U1396.out"], ["self.clk","_U1397.clk"], - ["_U1398.in","_U1397.out"], - ["self.clk","_U1398.clk"], - ["add_1120_1134_1135.out","_U1399.in"], - ["self.out_conv_stencil","_U1399.out"], - ["_U1414.out","_U1401.in"], - ["add_1121_1132_1133.in0","_U1401.out"], + ["_U1400.out","_U1398.in"], + ["mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121.in1","_U1398.out"], + ["self.clk","_U1400.clk"], + ["self.in1_hw_input_global_wrapper_stencil.1","_U1400.in"], + ["_U1404.out","_U1401.in"], + ["mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122.in0","_U1401.out"], ["self.clk","_U1403.clk"], - ["mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121.out","_U1403.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.2","_U1403.in"], ["_U1404.in","_U1403.out"], ["self.clk","_U1404.clk"], - ["_U1405.in","_U1404.out"], - ["self.clk","_U1405.clk"], - ["_U1406.in","_U1405.out"], - ["self.clk","_U1406.clk"], - ["_U1407.in","_U1406.out"], + ["_U1408.out","_U1405.in"], + ["mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122.in1","_U1405.out"], ["self.clk","_U1407.clk"], + ["self.in1_hw_input_global_wrapper_stencil.2","_U1407.in"], ["_U1408.in","_U1407.out"], ["self.clk","_U1408.clk"], - ["_U1409.in","_U1408.out"], - ["self.clk","_U1409.clk"], - ["_U1410.in","_U1409.out"], - ["self.clk","_U1410.clk"], - ["_U1411.in","_U1410.out"], + ["_U1425.out","_U1409.in"], + ["add_1120_1134_1135.in0","_U1409.out"], ["self.clk","_U1411.clk"], + ["mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120.out","_U1411.in"], ["_U1412.in","_U1411.out"], ["self.clk","_U1412.clk"], ["_U1413.in","_U1412.out"], ["self.clk","_U1413.clk"], ["_U1414.in","_U1413.out"], ["self.clk","_U1414.clk"], - ["_U1417.out","_U1415.in"], - ["add_1121_1132_1133.in1","_U1415.out"], + ["_U1415.in","_U1414.out"], + ["self.clk","_U1415.clk"], + ["_U1416.in","_U1415.out"], + ["self.clk","_U1416.clk"], + ["_U1417.in","_U1416.out"], ["self.clk","_U1417.clk"], - ["add_1122_1131_1132.out","_U1417.in"], - ["_U1421.out","_U1418.in"], - ["add_1126_1127_1128.in0","_U1418.out"], + ["_U1418.in","_U1417.out"], + ["self.clk","_U1418.clk"], + ["_U1419.in","_U1418.out"], + ["self.clk","_U1419.clk"], + ["_U1420.in","_U1419.out"], ["self.clk","_U1420.clk"], - ["mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126.out","_U1420.in"], ["_U1421.in","_U1420.out"], ["self.clk","_U1421.clk"], - ["_U1424.out","_U1422.in"], - ["add_1126_1127_1128.in1","_U1422.out"], + ["_U1422.in","_U1421.out"], + ["self.clk","_U1422.clk"], + ["_U1423.in","_U1422.out"], + ["self.clk","_U1423.clk"], + ["_U1424.in","_U1423.out"], ["self.clk","_U1424.clk"], - ["mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127.out","_U1424.in"], - ["_U1440.out","_U1425.in"], - ["add_conv_stencil_7_1133_1134.in0","_U1425.out"], - ["self.clk","_U1427.clk"], - ["self.in0_conv_stencil.0","_U1427.in"], - ["_U1428.in","_U1427.out"], + ["_U1425.in","_U1424.out"], + ["self.clk","_U1425.clk"], + ["_U1428.out","_U1426.in"], + ["add_1120_1134_1135.in1","_U1426.out"], ["self.clk","_U1428.clk"], - ["_U1429.in","_U1428.out"], - ["self.clk","_U1429.clk"], - ["_U1430.in","_U1429.out"], - ["self.clk","_U1430.clk"], - ["_U1431.in","_U1430.out"], - ["self.clk","_U1431.clk"], - ["_U1432.in","_U1431.out"], - ["self.clk","_U1432.clk"], - ["_U1433.in","_U1432.out"], + ["add_conv_stencil_7_1133_1134.out","_U1428.in"], + ["add_1120_1134_1135.out","_U1429.in"], + ["self.out_conv_stencil","_U1429.out"], + ["_U1433.out","_U1431.in"], + ["add_1125_1128_1129.in1","_U1431.out"], ["self.clk","_U1433.clk"], - ["_U1434.in","_U1433.out"], - ["self.clk","_U1434.clk"], - ["_U1435.in","_U1434.out"], - ["self.clk","_U1435.clk"], - ["_U1436.in","_U1435.out"], + ["add_1126_1127_1128.out","_U1433.in"], + ["_U1437.out","_U1434.in"], + ["add_1126_1127_1128.in0","_U1434.out"], ["self.clk","_U1436.clk"], + ["mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126.out","_U1436.in"], ["_U1437.in","_U1436.out"], ["self.clk","_U1437.clk"], - ["_U1438.in","_U1437.out"], - ["self.clk","_U1438.clk"], - ["_U1439.in","_U1438.out"], - ["self.clk","_U1439.clk"], - ["_U1440.in","_U1439.out"], - ["self.clk","_U1440.clk"] + ["_U1440.out","_U1438.in"], + ["add_1126_1127_1128.in1","_U1438.out"], + ["self.clk","_U1440.clk"], + ["mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127.out","_U1440.in"] ] }, "hcompute_conv_stencil_15":{ @@ -29395,13 +29395,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1449":{ + "modref":"global._U1449_pt__U1450" + }, + "_U1451":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1450":{ - "modref":"global._U1450_pt__U1451" - }, "_U1452":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29428,25 +29428,32 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1457":{ + "modref":"global._U1457_pt__U1458" + }, + "_U1459":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1458":{ + "_U1460":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1459":{ - "modref":"global._U1459_pt__U1460" - }, "_U1461":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1462":{ - "modref":"global._U1462_pt__U1463" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1463":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1464":{ "genref":"mantle.reg", @@ -29472,7 +29479,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1470":{ - "modref":"global._U1470_pt__U1471" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1471":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1472":{ "genref":"mantle.reg", @@ -29493,14 +29507,7 @@ "modref":"global._U1475_pt__U1476" }, "_U1477":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1478":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1477_pt__U1478" }, "_U1479":{ "genref":"mantle.reg", @@ -29516,14 +29523,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1483":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1484":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1483_pt__U1484" }, "_U1485":{ "genref":"mantle.reg", @@ -29531,13 +29531,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1486":{ - "modref":"global._U1486_pt__U1487" - }, - "_U1488":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1487":{ + "modref":"global._U1487_pt__U1488" + }, "_U1489":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29549,13 +29549,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1491":{ + "modref":"global._U1491_pt__U1492" + }, + "_U1493":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1492":{ - "modref":"global._U1492_pt__U1493" - }, "_U1494":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29567,14 +29567,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1496":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1497":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1496_pt__U1497" }, "_U1498":{ "genref":"mantle.reg", @@ -29582,18 +29575,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1499":{ - "modref":"global._U1499_pt__U1500" - }, - "_U1501":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1502":{ + "_U1500":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1501":{ + "modref":"global._U1501_pt__U1502" + }, "_U1503":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29610,13 +29603,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1506":{ - "modref":"global._U1506_pt__U1507" - }, - "_U1508":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1507":{ + "modref":"global._U1507_pt__U1508" + }, "_U1509":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29638,13 +29631,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1513":{ + "modref":"global._U1513_pt__U1514" + }, + "_U1515":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1514":{ - "modref":"global._U1514_pt__U1515" - }, "_U1516":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29666,36 +29659,36 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1520":{ + "modref":"global._U1520_pt__U1521" + }, + "_U1522":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1521":{ + "_U1523":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1522":{ - "modref":"global._U1522_pt__U1523" - }, "_U1524":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1525":{ - "modref":"global._U1525_pt__U1526" - }, - "_U1527":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1528":{ + "_U1526":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1527":{ + "modref":"global._U1527_pt__U1528" + }, "_U1529":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29707,112 +29700,119 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1531":{ + "modref":"global._U1531_pt__U1532" + }, + "_U1533":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1532":{ + "_U1534":{ + "modref":"global._U1534_pt__U1535" + }, + "_U1536":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1533":{ + "_U1537":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1534":{ + "_U1538":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1535":{ + "_U1539":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1536":{ + "_U1540":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1537":{ + "_U1541":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1538":{ + "_U1542":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1539":{ + "_U1543":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1540":{ + "_U1544":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1541":{ - "modref":"global._U1541_pt__U1542" - }, - "_U1543":{ - "modref":"global._U1543_pt__U1544" - }, "_U1545":{ - "modref":"global._U1545_pt__U1546" - }, - "_U1547":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1548":{ - "modref":"global._U1548_pt__U1549" - }, - "_U1550":{ + "_U1546":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1551":{ + "_U1547":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1552":{ + "_U1548":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1553":{ + "_U1549":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1550":{ + "modref":"global._U1550_pt__U1551" + }, + "_U1552":{ + "modref":"global._U1552_pt__U1553" + }, "_U1554":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1555":{ + "modref":"global._U1555_pt__U1556" + }, + "_U1557":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1556":{ - "modref":"global._U1556_pt__U1557" - }, "_U1558":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1559":{ - "modref":"global._U1559_pt__U1560" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1560":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1561":{ "genref":"mantle.reg", @@ -29825,26 +29825,26 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1563":{ + "modref":"global._U1563_pt__U1564" + }, + "_U1565":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1564":{ + "_U1566":{ + "modref":"global._U1566_pt__U1567" + }, + "_U1568":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1565":{ - "modref":"global._U1565_pt__U1566" - }, - "_U1567":{ + "_U1569":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1568":{ - "modref":"global._U1568_pt__U1569" - }, "_U1570":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -29864,14 +29864,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1575":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1576":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1575_pt__U1576" }, "_U1577":{ "genref":"mantle.reg", @@ -29934,34 +29927,34 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1589":{ - "modref":"global._U1589_pt__U1590" - }, - "_U1591":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1592":{ - "modref":"global._U1592_pt__U1593" - }, - "_U1594":{ - "modref":"global._U1594_pt__U1595" - }, - "_U1596":{ + "_U1590":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1597":{ + "_U1591":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1598":{ + "_U1592":{ + "modref":"global._U1592_pt__U1593" + }, + "_U1594":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1595":{ + "modref":"global._U1595_pt__U1596" + }, + "_U1597":{ + "modref":"global._U1597_pt__U1598" + }, "_U1599":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -30008,7 +30001,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1608":{ - "modref":"global._U1608_pt__U1609" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1609":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1610":{ "genref":"mantle.reg", @@ -30032,14 +30032,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1617":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U1618":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U1617_pt__U1618" }, "_U1619":{ "genref":"mantle.reg", @@ -30077,31 +30070,31 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1626":{ - "modref":"global._U1626_pt__U1627" - }, - "_U1628":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1629":{ - "modref":"global._U1629_pt__U1630" - }, - "_U1631":{ + "_U1627":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1632":{ + "_U1628":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U1633":{ + "_U1629":{ + "modref":"global._U1629_pt__U1630" + }, + "_U1631":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U1632":{ + "modref":"global._U1632_pt__U1633" + }, "_U1634":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -30128,7 +30121,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1639":{ - "modref":"global._U1639_pt__U1640" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U1640":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U1641":{ "genref":"mantle.reg", @@ -30201,10 +30201,10 @@ } }, "connections":[ - ["_U1449.out","_U1441.in"], - ["mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194.in0","_U1441.out"], + ["_U1448.out","_U1441.in"], + ["mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193.in0","_U1441.out"], ["self.clk","_U1443.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1443.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1443.in"], ["_U1444.in","_U1443.out"], ["self.clk","_U1444.clk"], ["_U1445.in","_U1444.out"], @@ -30215,12 +30215,12 @@ ["self.clk","_U1447.clk"], ["_U1448.in","_U1447.out"], ["self.clk","_U1448.clk"], - ["_U1449.in","_U1448.out"], - ["self.clk","_U1449.clk"], - ["_U1458.out","_U1450.in"], - ["mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194.in1","_U1450.out"], + ["_U1456.out","_U1449.in"], + ["mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193.in1","_U1449.out"], + ["self.clk","_U1451.clk"], + ["self.in1_hw_input_global_wrapper_stencil.6","_U1451.in"], + ["_U1452.in","_U1451.out"], ["self.clk","_U1452.clk"], - ["self.in1_hw_input_global_wrapper_stencil.7","_U1452.in"], ["_U1453.in","_U1452.out"], ["self.clk","_U1453.clk"], ["_U1454.in","_U1453.out"], @@ -30229,140 +30229,134 @@ ["self.clk","_U1455.clk"], ["_U1456.in","_U1455.out"], ["self.clk","_U1456.clk"], - ["_U1457.in","_U1456.out"], - ["self.clk","_U1457.clk"], - ["_U1458.in","_U1457.out"], - ["self.clk","_U1458.clk"], - ["_U1461.out","_U1459.in"], - ["mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188.in1","_U1459.out"], + ["_U1465.out","_U1457.in"], + ["mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194.in0","_U1457.out"], + ["self.clk","_U1459.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.7","_U1459.in"], + ["_U1460.in","_U1459.out"], + ["self.clk","_U1460.clk"], + ["_U1461.in","_U1460.out"], ["self.clk","_U1461.clk"], - ["self.in1_hw_input_global_wrapper_stencil.1","_U1461.in"], - ["_U1465.out","_U1462.in"], - ["mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189.in0","_U1462.out"], + ["_U1462.in","_U1461.out"], + ["self.clk","_U1462.clk"], + ["_U1463.in","_U1462.out"], + ["self.clk","_U1463.clk"], + ["_U1464.in","_U1463.out"], ["self.clk","_U1464.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.2","_U1464.in"], ["_U1465.in","_U1464.out"], ["self.clk","_U1465.clk"], - ["_U1469.out","_U1466.in"], - ["mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189.in1","_U1466.out"], + ["_U1474.out","_U1466.in"], + ["mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194.in1","_U1466.out"], ["self.clk","_U1468.clk"], - ["self.in1_hw_input_global_wrapper_stencil.2","_U1468.in"], + ["self.in1_hw_input_global_wrapper_stencil.7","_U1468.in"], ["_U1469.in","_U1468.out"], ["self.clk","_U1469.clk"], - ["_U1474.out","_U1470.in"], - ["mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190.in0","_U1470.out"], + ["_U1470.in","_U1469.out"], + ["self.clk","_U1470.clk"], + ["_U1471.in","_U1470.out"], + ["self.clk","_U1471.clk"], + ["_U1472.in","_U1471.out"], ["self.clk","_U1472.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.3","_U1472.in"], ["_U1473.in","_U1472.out"], ["self.clk","_U1473.clk"], ["_U1474.in","_U1473.out"], ["self.clk","_U1474.clk"], - ["_U1479.out","_U1475.in"], - ["mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190.in1","_U1475.out"], - ["self.clk","_U1477.clk"], - ["self.in1_hw_input_global_wrapper_stencil.3","_U1477.in"], - ["_U1478.in","_U1477.out"], - ["self.clk","_U1478.clk"], - ["_U1479.in","_U1478.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","_U1475.in"], + ["mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187.in1","_U1475.out"], + ["_U1479.out","_U1477.in"], + ["mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188.in0","_U1477.out"], ["self.clk","_U1479.clk"], - ["_U1485.out","_U1480.in"], - ["mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191.in0","_U1480.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.1","_U1479.in"], + ["_U1482.out","_U1480.in"], + ["mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188.in1","_U1480.out"], ["self.clk","_U1482.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.4","_U1482.in"], - ["_U1483.in","_U1482.out"], - ["self.clk","_U1483.clk"], - ["_U1484.in","_U1483.out"], - ["self.clk","_U1484.clk"], - ["_U1485.in","_U1484.out"], + ["self.in1_hw_input_global_wrapper_stencil.1","_U1482.in"], + ["_U1486.out","_U1483.in"], + ["mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189.in0","_U1483.out"], ["self.clk","_U1485.clk"], - ["_U1491.out","_U1486.in"], - ["mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191.in1","_U1486.out"], - ["self.clk","_U1488.clk"], - ["self.in1_hw_input_global_wrapper_stencil.4","_U1488.in"], - ["_U1489.in","_U1488.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.2","_U1485.in"], + ["_U1486.in","_U1485.out"], + ["self.clk","_U1486.clk"], + ["_U1490.out","_U1487.in"], + ["mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189.in1","_U1487.out"], ["self.clk","_U1489.clk"], + ["self.in1_hw_input_global_wrapper_stencil.2","_U1489.in"], ["_U1490.in","_U1489.out"], ["self.clk","_U1490.clk"], - ["_U1491.in","_U1490.out"], - ["self.clk","_U1491.clk"], - ["_U1498.out","_U1492.in"], - ["mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192.in0","_U1492.out"], + ["_U1495.out","_U1491.in"], + ["mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190.in0","_U1491.out"], + ["self.clk","_U1493.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.3","_U1493.in"], + ["_U1494.in","_U1493.out"], ["self.clk","_U1494.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.5","_U1494.in"], ["_U1495.in","_U1494.out"], ["self.clk","_U1495.clk"], - ["_U1496.in","_U1495.out"], - ["self.clk","_U1496.clk"], - ["_U1497.in","_U1496.out"], - ["self.clk","_U1497.clk"], - ["_U1498.in","_U1497.out"], + ["_U1500.out","_U1496.in"], + ["mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190.in1","_U1496.out"], ["self.clk","_U1498.clk"], - ["_U1505.out","_U1499.in"], - ["mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192.in1","_U1499.out"], - ["self.clk","_U1501.clk"], - ["self.in1_hw_input_global_wrapper_stencil.5","_U1501.in"], - ["_U1502.in","_U1501.out"], - ["self.clk","_U1502.clk"], - ["_U1503.in","_U1502.out"], + ["self.in1_hw_input_global_wrapper_stencil.3","_U1498.in"], + ["_U1499.in","_U1498.out"], + ["self.clk","_U1499.clk"], + ["_U1500.in","_U1499.out"], + ["self.clk","_U1500.clk"], + ["_U1506.out","_U1501.in"], + ["mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191.in0","_U1501.out"], ["self.clk","_U1503.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.4","_U1503.in"], ["_U1504.in","_U1503.out"], ["self.clk","_U1504.clk"], ["_U1505.in","_U1504.out"], ["self.clk","_U1505.clk"], - ["_U1513.out","_U1506.in"], - ["mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193.in0","_U1506.out"], - ["self.clk","_U1508.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.6","_U1508.in"], - ["_U1509.in","_U1508.out"], + ["_U1506.in","_U1505.out"], + ["self.clk","_U1506.clk"], + ["_U1512.out","_U1507.in"], + ["mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191.in1","_U1507.out"], ["self.clk","_U1509.clk"], + ["self.in1_hw_input_global_wrapper_stencil.4","_U1509.in"], ["_U1510.in","_U1509.out"], ["self.clk","_U1510.clk"], ["_U1511.in","_U1510.out"], ["self.clk","_U1511.clk"], ["_U1512.in","_U1511.out"], ["self.clk","_U1512.clk"], - ["_U1513.in","_U1512.out"], - ["self.clk","_U1513.clk"], - ["_U1521.out","_U1514.in"], - ["mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193.in1","_U1514.out"], + ["_U1519.out","_U1513.in"], + ["mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192.in0","_U1513.out"], + ["self.clk","_U1515.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.5","_U1515.in"], + ["_U1516.in","_U1515.out"], ["self.clk","_U1516.clk"], - ["self.in1_hw_input_global_wrapper_stencil.6","_U1516.in"], ["_U1517.in","_U1516.out"], ["self.clk","_U1517.clk"], ["_U1518.in","_U1517.out"], ["self.clk","_U1518.clk"], ["_U1519.in","_U1518.out"], ["self.clk","_U1519.clk"], - ["_U1520.in","_U1519.out"], - ["self.clk","_U1520.clk"], - ["_U1521.in","_U1520.out"], - ["self.clk","_U1521.clk"], - ["_U1524.out","_U1522.in"], - ["add_1193_1194_1195.in1","_U1522.out"], + ["_U1526.out","_U1520.in"], + ["mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192.in1","_U1520.out"], + ["self.clk","_U1522.clk"], + ["self.in1_hw_input_global_wrapper_stencil.5","_U1522.in"], + ["_U1523.in","_U1522.out"], + ["self.clk","_U1523.clk"], + ["_U1524.in","_U1523.out"], ["self.clk","_U1524.clk"], - ["mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194.out","_U1524.in"], - ["_U1540.out","_U1525.in"], - ["add_conv_stencil_8_1200_1201.in0","_U1525.out"], - ["self.clk","_U1527.clk"], - ["self.in0_conv_stencil.0","_U1527.in"], - ["_U1528.in","_U1527.out"], - ["self.clk","_U1528.clk"], - ["_U1529.in","_U1528.out"], + ["_U1525.in","_U1524.out"], + ["self.clk","_U1525.clk"], + ["_U1526.in","_U1525.out"], + ["self.clk","_U1526.clk"], + ["_U1530.out","_U1527.in"], + ["add_1193_1194_1195.in0","_U1527.out"], ["self.clk","_U1529.clk"], + ["mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193.out","_U1529.in"], ["_U1530.in","_U1529.out"], ["self.clk","_U1530.clk"], - ["_U1531.in","_U1530.out"], - ["self.clk","_U1531.clk"], - ["_U1532.in","_U1531.out"], - ["self.clk","_U1532.clk"], - ["_U1533.in","_U1532.out"], + ["_U1533.out","_U1531.in"], + ["add_1193_1194_1195.in1","_U1531.out"], ["self.clk","_U1533.clk"], - ["_U1534.in","_U1533.out"], - ["self.clk","_U1534.clk"], - ["_U1535.in","_U1534.out"], - ["self.clk","_U1535.clk"], - ["_U1536.in","_U1535.out"], + ["mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194.out","_U1533.in"], + ["_U1549.out","_U1534.in"], + ["add_conv_stencil_8_1200_1201.in0","_U1534.out"], ["self.clk","_U1536.clk"], + ["self.in0_conv_stencil.0","_U1536.in"], ["_U1537.in","_U1536.out"], ["self.clk","_U1537.clk"], ["_U1538.in","_U1537.out"], @@ -30371,62 +30365,66 @@ ["self.clk","_U1539.clk"], ["_U1540.in","_U1539.out"], ["self.clk","_U1540.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.0","_U1541.in"], - ["mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187.in0","_U1541.out"], - ["self.in1_hw_input_global_wrapper_stencil.0","_U1543.in"], - ["mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187.in1","_U1543.out"], - ["_U1547.out","_U1545.in"], - ["mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188.in0","_U1545.out"], + ["_U1541.in","_U1540.out"], + ["self.clk","_U1541.clk"], + ["_U1542.in","_U1541.out"], + ["self.clk","_U1542.clk"], + ["_U1543.in","_U1542.out"], + ["self.clk","_U1543.clk"], + ["_U1544.in","_U1543.out"], + ["self.clk","_U1544.clk"], + ["_U1545.in","_U1544.out"], + ["self.clk","_U1545.clk"], + ["_U1546.in","_U1545.out"], + ["self.clk","_U1546.clk"], + ["_U1547.in","_U1546.out"], ["self.clk","_U1547.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.1","_U1547.in"], - ["_U1555.out","_U1548.in"], - ["add_1191_1196_1197.in0","_U1548.out"], - ["self.clk","_U1550.clk"], - ["mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191.out","_U1550.in"], - ["_U1551.in","_U1550.out"], - ["self.clk","_U1551.clk"], - ["_U1552.in","_U1551.out"], - ["self.clk","_U1552.clk"], - ["_U1553.in","_U1552.out"], - ["self.clk","_U1553.clk"], - ["_U1554.in","_U1553.out"], + ["_U1548.in","_U1547.out"], + ["self.clk","_U1548.clk"], + ["_U1549.in","_U1548.out"], + ["self.clk","_U1549.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","_U1550.in"], + ["mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187.in0","_U1550.out"], + ["_U1554.out","_U1552.in"], + ["add_1190_1197_1198.in1","_U1552.out"], ["self.clk","_U1554.clk"], - ["_U1555.in","_U1554.out"], - ["self.clk","_U1555.clk"], - ["_U1558.out","_U1556.in"], - ["add_1191_1196_1197.in1","_U1556.out"], + ["add_1191_1196_1197.out","_U1554.in"], + ["_U1562.out","_U1555.in"], + ["add_1191_1196_1197.in0","_U1555.out"], + ["self.clk","_U1557.clk"], + ["mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191.out","_U1557.in"], + ["_U1558.in","_U1557.out"], ["self.clk","_U1558.clk"], - ["add_1192_1195_1196.out","_U1558.in"], - ["_U1564.out","_U1559.in"], - ["add_1192_1195_1196.in0","_U1559.out"], + ["_U1559.in","_U1558.out"], + ["self.clk","_U1559.clk"], + ["_U1560.in","_U1559.out"], + ["self.clk","_U1560.clk"], + ["_U1561.in","_U1560.out"], ["self.clk","_U1561.clk"], - ["mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192.out","_U1561.in"], ["_U1562.in","_U1561.out"], ["self.clk","_U1562.clk"], - ["_U1563.in","_U1562.out"], - ["self.clk","_U1563.clk"], - ["_U1564.in","_U1563.out"], - ["self.clk","_U1564.clk"], - ["_U1567.out","_U1565.in"], - ["add_1192_1195_1196.in1","_U1565.out"], - ["self.clk","_U1567.clk"], - ["add_1193_1194_1195.out","_U1567.in"], - ["_U1571.out","_U1568.in"], - ["add_1193_1194_1195.in0","_U1568.out"], + ["_U1565.out","_U1563.in"], + ["add_1191_1196_1197.in1","_U1563.out"], + ["self.clk","_U1565.clk"], + ["add_1192_1195_1196.out","_U1565.in"], + ["_U1571.out","_U1566.in"], + ["add_1192_1195_1196.in0","_U1566.out"], + ["self.clk","_U1568.clk"], + ["mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192.out","_U1568.in"], + ["_U1569.in","_U1568.out"], + ["self.clk","_U1569.clk"], + ["_U1570.in","_U1569.out"], ["self.clk","_U1570.clk"], - ["mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193.out","_U1570.in"], ["_U1571.in","_U1570.out"], ["self.clk","_U1571.clk"], - ["_U1588.out","_U1572.in"], - ["add_1187_1201_1202.in0","_U1572.out"], + ["_U1574.out","_U1572.in"], + ["add_1192_1195_1196.in1","_U1572.out"], ["self.clk","_U1574.clk"], - ["mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187.out","_U1574.in"], - ["_U1575.in","_U1574.out"], - ["self.clk","_U1575.clk"], - ["_U1576.in","_U1575.out"], - ["self.clk","_U1576.clk"], - ["_U1577.in","_U1576.out"], + ["add_1193_1194_1195.out","_U1574.in"], + ["_U1591.out","_U1575.in"], + ["add_1187_1201_1202.in0","_U1575.out"], ["self.clk","_U1577.clk"], + ["mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187.out","_U1577.in"], ["_U1578.in","_U1577.out"], ["self.clk","_U1578.clk"], ["_U1579.in","_U1578.out"], @@ -30449,22 +30447,22 @@ ["self.clk","_U1587.clk"], ["_U1588.in","_U1587.out"], ["self.clk","_U1588.clk"], - ["_U1591.out","_U1589.in"], - ["add_1187_1201_1202.in1","_U1589.out"], + ["_U1589.in","_U1588.out"], + ["self.clk","_U1589.clk"], + ["_U1590.in","_U1589.out"], + ["self.clk","_U1590.clk"], + ["_U1591.in","_U1590.out"], ["self.clk","_U1591.clk"], - ["add_conv_stencil_8_1200_1201.out","_U1591.in"], - ["add_1187_1201_1202.out","_U1592.in"], - ["self.out_conv_stencil","_U1592.out"], - ["_U1607.out","_U1594.in"], - ["add_1188_1199_1200.in0","_U1594.out"], - ["self.clk","_U1596.clk"], - ["mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188.out","_U1596.in"], - ["_U1597.in","_U1596.out"], - ["self.clk","_U1597.clk"], - ["_U1598.in","_U1597.out"], - ["self.clk","_U1598.clk"], - ["_U1599.in","_U1598.out"], + ["_U1594.out","_U1592.in"], + ["add_1187_1201_1202.in1","_U1592.out"], + ["self.clk","_U1594.clk"], + ["add_conv_stencil_8_1200_1201.out","_U1594.in"], + ["add_1187_1201_1202.out","_U1595.in"], + ["self.out_conv_stencil","_U1595.out"], + ["_U1610.out","_U1597.in"], + ["add_1188_1199_1200.in0","_U1597.out"], ["self.clk","_U1599.clk"], + ["mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188.out","_U1599.in"], ["_U1600.in","_U1599.out"], ["self.clk","_U1600.clk"], ["_U1601.in","_U1600.out"], @@ -30481,24 +30479,24 @@ ["self.clk","_U1606.clk"], ["_U1607.in","_U1606.out"], ["self.clk","_U1607.clk"], - ["_U1610.out","_U1608.in"], - ["add_1188_1199_1200.in1","_U1608.out"], + ["_U1608.in","_U1607.out"], + ["self.clk","_U1608.clk"], + ["_U1609.in","_U1608.out"], + ["self.clk","_U1609.clk"], + ["_U1610.in","_U1609.out"], ["self.clk","_U1610.clk"], - ["add_1189_1198_1199.out","_U1610.in"], ["_U1613.out","_U1611.in"], - ["add_conv_stencil_8_1200_1201.in1","_U1611.out"], + ["add_1188_1199_1200.in1","_U1611.out"], ["self.clk","_U1613.clk"], - ["add_1188_1199_1200.out","_U1613.in"], - ["_U1625.out","_U1614.in"], - ["add_1189_1198_1199.in0","_U1614.out"], + ["add_1189_1198_1199.out","_U1613.in"], + ["_U1616.out","_U1614.in"], + ["add_conv_stencil_8_1200_1201.in1","_U1614.out"], ["self.clk","_U1616.clk"], - ["mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189.out","_U1616.in"], - ["_U1617.in","_U1616.out"], - ["self.clk","_U1617.clk"], - ["_U1618.in","_U1617.out"], - ["self.clk","_U1618.clk"], - ["_U1619.in","_U1618.out"], + ["add_1188_1199_1200.out","_U1616.in"], + ["_U1628.out","_U1617.in"], + ["add_1189_1198_1199.in0","_U1617.out"], ["self.clk","_U1619.clk"], + ["mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189.out","_U1619.in"], ["_U1620.in","_U1619.out"], ["self.clk","_U1620.clk"], ["_U1621.in","_U1620.out"], @@ -30511,20 +30509,20 @@ ["self.clk","_U1624.clk"], ["_U1625.in","_U1624.out"], ["self.clk","_U1625.clk"], - ["_U1628.out","_U1626.in"], - ["add_1189_1198_1199.in1","_U1626.out"], + ["_U1626.in","_U1625.out"], + ["self.clk","_U1626.clk"], + ["_U1627.in","_U1626.out"], + ["self.clk","_U1627.clk"], + ["_U1628.in","_U1627.out"], ["self.clk","_U1628.clk"], - ["add_1190_1197_1198.out","_U1628.in"], - ["_U1638.out","_U1629.in"], - ["add_1190_1197_1198.in0","_U1629.out"], + ["_U1631.out","_U1629.in"], + ["add_1189_1198_1199.in1","_U1629.out"], ["self.clk","_U1631.clk"], - ["mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190.out","_U1631.in"], - ["_U1632.in","_U1631.out"], - ["self.clk","_U1632.clk"], - ["_U1633.in","_U1632.out"], - ["self.clk","_U1633.clk"], - ["_U1634.in","_U1633.out"], + ["add_1190_1197_1198.out","_U1631.in"], + ["_U1641.out","_U1632.in"], + ["add_1190_1197_1198.in0","_U1632.out"], ["self.clk","_U1634.clk"], + ["mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190.out","_U1634.in"], ["_U1635.in","_U1634.out"], ["self.clk","_U1635.clk"], ["_U1636.in","_U1635.out"], @@ -30533,10 +30531,12 @@ ["self.clk","_U1637.clk"], ["_U1638.in","_U1637.out"], ["self.clk","_U1638.clk"], - ["_U1641.out","_U1639.in"], - ["add_1190_1197_1198.in1","_U1639.out"], - ["self.clk","_U1641.clk"], - ["add_1191_1196_1197.out","_U1641.in"] + ["_U1639.in","_U1638.out"], + ["self.clk","_U1639.clk"], + ["_U1640.in","_U1639.out"], + ["self.clk","_U1640.clk"], + ["_U1641.in","_U1640.out"], + ["self.clk","_U1641.clk"] ] }, "hcompute_conv_stencil_1_pipelined":{ @@ -30544,8 +30544,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U20":{ - "modref":"global._U20_pt__U21" + "_U18":{ + "modref":"global._U18_pt__U19" }, "const_p0__682":{ "genref":"coreir.const", @@ -30554,8 +30554,8 @@ } }, "connections":[ - ["const_p0__682.out","_U20.in"], - ["self.out_conv_stencil","_U20.out"] + ["const_p0__682.out","_U18.in"], + ["self.out_conv_stencil","_U18.out"] ] }, "hcompute_conv_stencil_2":{ @@ -30578,8 +30578,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U22":{ - "modref":"global._U22_pt__U23" + "_U20":{ + "modref":"global._U20_pt__U21" }, "const_p0__685":{ "genref":"coreir.const", @@ -30588,8 +30588,8 @@ } }, "connections":[ - ["const_p0__685.out","_U22.in"], - ["self.out_conv_stencil","_U22.out"] + ["const_p0__685.out","_U20.in"], + ["self.out_conv_stencil","_U20.out"] ] }, "hcompute_conv_stencil_3":{ @@ -30612,8 +30612,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U24":{ - "modref":"global._U24_pt__U25" + "_U22":{ + "modref":"global._U22_pt__U23" }, "const_p0__688":{ "genref":"coreir.const", @@ -30622,8 +30622,8 @@ } }, "connections":[ - ["const_p0__688.out","_U24.in"], - ["self.out_conv_stencil","_U24.out"] + ["const_p0__688.out","_U22.in"], + ["self.out_conv_stencil","_U22.out"] ] }, "hcompute_conv_stencil_4":{ @@ -30646,8 +30646,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U26":{ - "modref":"global._U26_pt__U27" + "_U24":{ + "modref":"global._U24_pt__U25" }, "const_p0__691":{ "genref":"coreir.const", @@ -30656,8 +30656,8 @@ } }, "connections":[ - ["const_p0__691.out","_U26.in"], - ["self.out_conv_stencil","_U26.out"] + ["const_p0__691.out","_U24.in"], + ["self.out_conv_stencil","_U24.out"] ] }, "hcompute_conv_stencil_5":{ @@ -30680,8 +30680,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U28":{ - "modref":"global._U28_pt__U29" + "_U26":{ + "modref":"global._U26_pt__U27" }, "const_p0__694":{ "genref":"coreir.const", @@ -30690,8 +30690,8 @@ } }, "connections":[ - ["const_p0__694.out","_U28.in"], - ["self.out_conv_stencil","_U28.out"] + ["const_p0__694.out","_U26.in"], + ["self.out_conv_stencil","_U26.out"] ] }, "hcompute_conv_stencil_6":{ @@ -30714,8 +30714,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U30":{ - "modref":"global._U30_pt__U31" + "_U28":{ + "modref":"global._U28_pt__U29" }, "const_p0__697":{ "genref":"coreir.const", @@ -30724,8 +30724,8 @@ } }, "connections":[ - ["const_p0__697.out","_U30.in"], - ["self.out_conv_stencil","_U30.out"] + ["const_p0__697.out","_U28.in"], + ["self.out_conv_stencil","_U28.out"] ] }, "hcompute_conv_stencil_7":{ @@ -30748,8 +30748,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U32":{ - "modref":"global._U32_pt__U33" + "_U30":{ + "modref":"global._U30_pt__U31" }, "const_p0__700":{ "genref":"coreir.const", @@ -30758,8 +30758,8 @@ } }, "connections":[ - ["const_p0__700.out","_U32.in"], - ["self.out_conv_stencil","_U32.out"] + ["const_p0__700.out","_U30.in"], + ["self.out_conv_stencil","_U30.out"] ] }, "hcompute_conv_stencil_8":{ @@ -30880,15 +30880,13 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U101":{ + "_U100":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U102":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U101":{ + "modref":"global._U101_pt__U102" }, "_U103":{ "genref":"mantle.reg", @@ -30896,14 +30894,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U104":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U105":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U104_pt__U105" }, "_U106":{ "genref":"mantle.reg", @@ -30937,80 +30928,73 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U115":{ - "modref":"global._U115_pt__U116" - }, - "_U117":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U118":{ - "modref":"global._U118_pt__U119" - }, - "_U120":{ + "_U116":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U121":{ + "_U117":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U122":{ + "_U118":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U123":{ + "_U119":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U124":{ + "_U120":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U125":{ + "_U121":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U126":{ + "_U122":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U127":{ + "_U123":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U128":{ + "_U124":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U129":{ + "_U125":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U130":{ + "_U126":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U131":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U127":{ + "modref":"global._U127_pt__U128" }, - "_U132":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U129":{ + "modref":"global._U129_pt__U130" + }, + "_U131":{ + "modref":"global._U131_pt__U132" }, "_U133":{ "genref":"mantle.reg", @@ -31021,18 +31005,25 @@ "modref":"global._U134_pt__U135" }, "_U136":{ - "modref":"global._U136_pt__U137" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U138":{ - "modref":"global._U138_pt__U139" + "_U137":{ + "modref":"global._U137_pt__U138" }, - "_U140":{ + "_U139":{ + "modref":"global._U139_pt__U140" + }, + "_U141":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U141":{ - "modref":"global._U141_pt__U142" + "_U142":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U143":{ "genref":"mantle.reg", @@ -31040,130 +31031,130 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U144":{ - "modref":"global._U144_pt__U145" - }, - "_U146":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U147":{ + "_U145":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U148":{ - "modref":"global._U148_pt__U149" - }, - "_U150":{ + "_U146":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U151":{ + "_U147":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U152":{ + "_U148":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U153":{ + "_U149":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U154":{ + "_U150":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U155":{ + "_U151":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U156":{ + "_U152":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U157":{ + "_U153":{ + "modref":"global._U153_pt__U154" + }, + "_U155":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U156":{ + "modref":"global._U156_pt__U157" + }, "_U158":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U159":{ + "modref":"global._U159_pt__U160" + }, + "_U161":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U160":{ + "_U162":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U161":{ + "_U163":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U162":{ - "modref":"global._U162_pt__U163" - }, "_U164":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U165":{ - "modref":"global._U165_pt__U166" - }, - "_U167":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U168":{ - "modref":"global._U168_pt__U169" - }, - "_U170":{ + "_U166":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U171":{ + "_U167":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U172":{ + "_U168":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U173":{ + "_U169":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U174":{ + "_U170":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U175":{ + "_U171":{ + "modref":"global._U171_pt__U172" + }, + "_U173":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U174":{ + "modref":"global._U174_pt__U175" + }, "_U176":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31185,36 +31176,36 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U180":{ - "modref":"global._U180_pt__U181" - }, - "_U182":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U183":{ - "modref":"global._U183_pt__U184" - }, - "_U185":{ + "_U181":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U186":{ + "_U182":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U187":{ + "_U183":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U188":{ + "_U184":{ + "modref":"global._U184_pt__U185" + }, + "_U186":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U187":{ + "modref":"global._U187_pt__U188" + }, "_U189":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31236,26 +31227,26 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U193":{ - "modref":"global._U193_pt__U194" - }, - "_U195":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U196":{ - "modref":"global._U196_pt__U197" - }, - "_U198":{ + "_U194":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U199":{ + "_U195":{ + "modref":"global._U195_pt__U196" + }, + "_U197":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U198":{ + "modref":"global._U198_pt__U199" + }, "_U200":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31277,7 +31268,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U204":{ - "modref":"global._U204_pt__U205" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U205":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U206":{ "genref":"mantle.reg", @@ -31308,23 +31306,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U213":{ - "modref":"global._U213_pt__U214" - }, - "_U215":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U216":{ + "_U214":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U217":{ + "_U215":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U216":{ + "modref":"global._U216_pt__U217" + }, "_U218":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31386,37 +31384,44 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U230":{ - "modref":"global._U230_pt__U231" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U231":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U232":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U233":{ - "modref":"global._U233_pt__U234" + "_U32":{ + "modref":"global._U32_pt__U33" }, "_U34":{ - "modref":"global._U34_pt__U35" - }, - "_U36":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U35":{ + "modref":"global._U35_pt__U36" + }, "_U37":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U38":{ - "modref":"global._U38_pt__U39" - }, - "_U40":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U39":{ + "modref":"global._U39_pt__U40" + }, "_U41":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31464,13 +31469,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U53":{ + "modref":"global._U53_pt__U54" + }, + "_U55":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U54":{ - "modref":"global._U54_pt__U55" - }, "_U56":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31487,13 +31492,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U59":{ + "modref":"global._U59_pt__U60" + }, + "_U61":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U60":{ - "modref":"global._U60_pt__U61" - }, "_U62":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31510,18 +31515,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U65":{ + "modref":"global._U65_pt__U66" + }, + "_U67":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U66":{ + "_U68":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U67":{ - "modref":"global._U67_pt__U68" - }, "_U69":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31538,18 +31543,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U72":{ + "modref":"global._U72_pt__U73" + }, + "_U74":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U73":{ + "_U75":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U74":{ - "modref":"global._U74_pt__U75" - }, "_U76":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31566,23 +31571,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U79":{ + "modref":"global._U79_pt__U80" + }, + "_U81":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U80":{ + "_U82":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U81":{ + "_U83":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U82":{ - "modref":"global._U82_pt__U83" - }, "_U84":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31599,23 +31604,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U87":{ + "modref":"global._U87_pt__U88" + }, + "_U89":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U88":{ + "_U90":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U89":{ + "_U91":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U90":{ - "modref":"global._U90_pt__U91" - }, "_U92":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -31632,14 +31637,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U95":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U96":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U95_pt__U96" }, "_U97":{ "genref":"mantle.reg", @@ -31652,7 +31650,9 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U99":{ - "modref":"global._U99_pt__U100" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "add_718_732_733":{ "genref":"coreir.add", @@ -31720,39 +31720,41 @@ } }, "connections":[ - ["self.clk","_U101.clk"], - ["self.in1_hw_input_global_wrapper_stencil.7","_U101.in"], - ["_U102.in","_U101.out"], - ["self.clk","_U102.clk"], - ["_U103.in","_U102.out"], + ["self.clk","_U100.clk"], + ["_U99.out","_U100.in"], + ["_U95.in","_U100.out"], + ["_U103.out","_U101.in"], + ["add_723_726_727.in1","_U101.out"], ["self.clk","_U103.clk"], - ["_U104.in","_U103.out"], - ["self.clk","_U104.clk"], - ["_U105.in","_U104.out"], - ["self.clk","_U105.clk"], - ["_U106.in","_U105.out"], + ["add_724_725_726.out","_U103.in"], + ["_U107.out","_U104.in"], + ["add_724_725_726.in0","_U104.out"], ["self.clk","_U106.clk"], + ["mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724.out","_U106.in"], ["_U107.in","_U106.out"], ["self.clk","_U107.clk"], - ["_U99.in","_U107.out"], ["_U110.out","_U108.in"], - ["add_723_726_727.in1","_U108.out"], + ["add_724_725_726.in1","_U108.out"], ["self.clk","_U110.clk"], - ["add_724_725_726.out","_U110.in"], - ["_U114.out","_U111.in"], - ["add_724_725_726.in0","_U111.out"], + ["mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725.out","_U110.in"], + ["_U126.out","_U111.in"], + ["add_conv_stencil_1_731_732.in0","_U111.out"], ["self.clk","_U113.clk"], - ["mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724.out","_U113.in"], + ["self.in0_conv_stencil.0","_U113.in"], ["_U114.in","_U113.out"], ["self.clk","_U114.clk"], - ["_U117.out","_U115.in"], - ["add_724_725_726.in1","_U115.out"], + ["_U115.in","_U114.out"], + ["self.clk","_U115.clk"], + ["_U116.in","_U115.out"], + ["self.clk","_U116.clk"], + ["_U117.in","_U116.out"], ["self.clk","_U117.clk"], - ["mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725.out","_U117.in"], - ["_U133.out","_U118.in"], - ["add_conv_stencil_1_731_732.in0","_U118.out"], + ["_U118.in","_U117.out"], + ["self.clk","_U118.clk"], + ["_U119.in","_U118.out"], + ["self.clk","_U119.clk"], + ["_U120.in","_U119.out"], ["self.clk","_U120.clk"], - ["self.in0_conv_stencil.0","_U120.in"], ["_U121.in","_U120.out"], ["self.clk","_U121.clk"], ["_U122.in","_U121.out"], @@ -31765,158 +31767,156 @@ ["self.clk","_U125.clk"], ["_U126.in","_U125.out"], ["self.clk","_U126.clk"], - ["_U127.in","_U126.out"], - ["self.clk","_U127.clk"], - ["_U128.in","_U127.out"], - ["self.clk","_U128.clk"], - ["_U129.in","_U128.out"], - ["self.clk","_U129.clk"], - ["_U130.in","_U129.out"], - ["self.clk","_U130.clk"], - ["_U131.in","_U130.out"], - ["self.clk","_U131.clk"], - ["_U132.in","_U131.out"], - ["self.clk","_U132.clk"], - ["_U133.in","_U132.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","_U127.in"], + ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718.in0","_U127.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","_U129.in"], + ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718.in1","_U129.out"], + ["_U133.out","_U131.in"], + ["mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719.in0","_U131.out"], ["self.clk","_U133.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.0","_U134.in"], - ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718.in0","_U134.out"], - ["self.in1_hw_input_global_wrapper_stencil.0","_U136.in"], - ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718.in1","_U136.out"], - ["_U140.out","_U138.in"], - ["mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719.in0","_U138.out"], - ["self.clk","_U140.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.1","_U140.in"], - ["_U143.out","_U141.in"], - ["mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719.in1","_U141.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.1","_U133.in"], + ["_U136.out","_U134.in"], + ["add_718_732_733.in1","_U134.out"], + ["self.clk","_U136.clk"], + ["add_conv_stencil_1_731_732.out","_U136.in"], + ["add_718_732_733.out","_U137.in"], + ["self.out_conv_stencil","_U137.out"], + ["_U152.out","_U139.in"], + ["add_719_730_731.in0","_U139.out"], + ["self.clk","_U141.clk"], + ["mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719.out","_U141.in"], + ["_U142.in","_U141.out"], + ["self.clk","_U142.clk"], + ["_U143.in","_U142.out"], ["self.clk","_U143.clk"], - ["self.in1_hw_input_global_wrapper_stencil.1","_U143.in"], - ["_U147.out","_U144.in"], - ["mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720.in0","_U144.out"], + ["_U144.in","_U143.out"], + ["self.clk","_U144.clk"], + ["_U145.in","_U144.out"], + ["self.clk","_U145.clk"], + ["_U146.in","_U145.out"], ["self.clk","_U146.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.2","_U146.in"], ["_U147.in","_U146.out"], ["self.clk","_U147.clk"], - ["_U161.out","_U148.in"], - ["add_719_730_731.in0","_U148.out"], + ["_U148.in","_U147.out"], + ["self.clk","_U148.clk"], + ["_U149.in","_U148.out"], + ["self.clk","_U149.clk"], + ["_U150.in","_U149.out"], ["self.clk","_U150.clk"], - ["mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719.out","_U150.in"], ["_U151.in","_U150.out"], ["self.clk","_U151.clk"], ["_U152.in","_U151.out"], ["self.clk","_U152.clk"], - ["_U153.in","_U152.out"], - ["self.clk","_U153.clk"], - ["_U154.in","_U153.out"], - ["self.clk","_U154.clk"], - ["_U155.in","_U154.out"], + ["_U155.out","_U153.in"], + ["add_719_730_731.in1","_U153.out"], ["self.clk","_U155.clk"], - ["_U156.in","_U155.out"], - ["self.clk","_U156.clk"], - ["_U157.in","_U156.out"], - ["self.clk","_U157.clk"], - ["_U158.in","_U157.out"], + ["add_720_729_730.out","_U155.in"], + ["_U158.out","_U156.in"], + ["add_conv_stencil_1_731_732.in1","_U156.out"], ["self.clk","_U158.clk"], - ["_U159.in","_U158.out"], - ["self.clk","_U159.clk"], - ["_U160.in","_U159.out"], - ["self.clk","_U160.clk"], - ["_U161.in","_U160.out"], + ["add_719_730_731.out","_U158.in"], + ["_U170.out","_U159.in"], + ["add_720_729_730.in0","_U159.out"], ["self.clk","_U161.clk"], - ["_U164.out","_U162.in"], - ["add_719_730_731.in1","_U162.out"], + ["mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720.out","_U161.in"], + ["_U162.in","_U161.out"], + ["self.clk","_U162.clk"], + ["_U163.in","_U162.out"], + ["self.clk","_U163.clk"], + ["_U164.in","_U163.out"], ["self.clk","_U164.clk"], - ["add_720_729_730.out","_U164.in"], - ["_U167.out","_U165.in"], - ["add_conv_stencil_1_731_732.in1","_U165.out"], + ["_U165.in","_U164.out"], + ["self.clk","_U165.clk"], + ["_U166.in","_U165.out"], + ["self.clk","_U166.clk"], + ["_U167.in","_U166.out"], ["self.clk","_U167.clk"], - ["add_719_730_731.out","_U167.in"], - ["_U179.out","_U168.in"], - ["add_720_729_730.in0","_U168.out"], + ["_U168.in","_U167.out"], + ["self.clk","_U168.clk"], + ["_U169.in","_U168.out"], + ["self.clk","_U169.clk"], + ["_U170.in","_U169.out"], ["self.clk","_U170.clk"], - ["mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720.out","_U170.in"], - ["_U171.in","_U170.out"], - ["self.clk","_U171.clk"], - ["_U172.in","_U171.out"], - ["self.clk","_U172.clk"], - ["_U173.in","_U172.out"], + ["_U173.out","_U171.in"], + ["add_720_729_730.in1","_U171.out"], ["self.clk","_U173.clk"], - ["_U174.in","_U173.out"], - ["self.clk","_U174.clk"], - ["_U175.in","_U174.out"], - ["self.clk","_U175.clk"], - ["_U176.in","_U175.out"], + ["add_721_728_729.out","_U173.in"], + ["_U183.out","_U174.in"], + ["add_721_728_729.in0","_U174.out"], ["self.clk","_U176.clk"], + ["mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721.out","_U176.in"], ["_U177.in","_U176.out"], ["self.clk","_U177.clk"], ["_U178.in","_U177.out"], ["self.clk","_U178.clk"], ["_U179.in","_U178.out"], ["self.clk","_U179.clk"], - ["_U182.out","_U180.in"], - ["add_720_729_730.in1","_U180.out"], + ["_U180.in","_U179.out"], + ["self.clk","_U180.clk"], + ["_U181.in","_U180.out"], + ["self.clk","_U181.clk"], + ["_U182.in","_U181.out"], ["self.clk","_U182.clk"], - ["add_721_728_729.out","_U182.in"], - ["_U192.out","_U183.in"], - ["add_721_728_729.in0","_U183.out"], - ["self.clk","_U185.clk"], - ["mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721.out","_U185.in"], - ["_U186.in","_U185.out"], + ["_U183.in","_U182.out"], + ["self.clk","_U183.clk"], + ["_U186.out","_U184.in"], + ["add_721_728_729.in1","_U184.out"], ["self.clk","_U186.clk"], - ["_U187.in","_U186.out"], - ["self.clk","_U187.clk"], - ["_U188.in","_U187.out"], - ["self.clk","_U188.clk"], - ["_U189.in","_U188.out"], + ["add_722_727_728.out","_U186.in"], + ["_U194.out","_U187.in"], + ["add_722_727_728.in0","_U187.out"], ["self.clk","_U189.clk"], + ["mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722.out","_U189.in"], ["_U190.in","_U189.out"], ["self.clk","_U190.clk"], ["_U191.in","_U190.out"], ["self.clk","_U191.clk"], ["_U192.in","_U191.out"], ["self.clk","_U192.clk"], - ["_U195.out","_U193.in"], - ["add_721_728_729.in1","_U193.out"], - ["self.clk","_U195.clk"], - ["add_722_727_728.out","_U195.in"], - ["_U203.out","_U196.in"], - ["add_722_727_728.in0","_U196.out"], - ["self.clk","_U198.clk"], - ["mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722.out","_U198.in"], - ["_U199.in","_U198.out"], - ["self.clk","_U199.clk"], - ["_U200.in","_U199.out"], + ["_U193.in","_U192.out"], + ["self.clk","_U193.clk"], + ["_U194.in","_U193.out"], + ["self.clk","_U194.clk"], + ["_U197.out","_U195.in"], + ["add_722_727_728.in1","_U195.out"], + ["self.clk","_U197.clk"], + ["add_723_726_727.out","_U197.in"], + ["_U206.out","_U198.in"], + ["mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725.in0","_U198.out"], ["self.clk","_U200.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.7","_U200.in"], ["_U201.in","_U200.out"], ["self.clk","_U201.clk"], ["_U202.in","_U201.out"], ["self.clk","_U202.clk"], ["_U203.in","_U202.out"], ["self.clk","_U203.clk"], - ["_U206.out","_U204.in"], - ["add_722_727_728.in1","_U204.out"], + ["_U204.in","_U203.out"], + ["self.clk","_U204.clk"], + ["_U205.in","_U204.out"], + ["self.clk","_U205.clk"], + ["_U206.in","_U205.out"], ["self.clk","_U206.clk"], - ["add_723_726_727.out","_U206.in"], - ["_U212.out","_U207.in"], - ["add_723_726_727.in0","_U207.out"], + ["_U215.out","_U207.in"], + ["mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725.in1","_U207.out"], ["self.clk","_U209.clk"], - ["mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723.out","_U209.in"], + ["self.in1_hw_input_global_wrapper_stencil.7","_U209.in"], ["_U210.in","_U209.out"], ["self.clk","_U210.clk"], ["_U211.in","_U210.out"], ["self.clk","_U211.clk"], ["_U212.in","_U211.out"], ["self.clk","_U212.clk"], - ["_U229.out","_U213.in"], - ["add_718_732_733.in0","_U213.out"], + ["_U213.in","_U212.out"], + ["self.clk","_U213.clk"], + ["_U214.in","_U213.out"], + ["self.clk","_U214.clk"], + ["_U215.in","_U214.out"], ["self.clk","_U215.clk"], - ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718.out","_U215.in"], - ["_U216.in","_U215.out"], - ["self.clk","_U216.clk"], - ["_U217.in","_U216.out"], - ["self.clk","_U217.clk"], - ["_U218.in","_U217.out"], + ["_U232.out","_U216.in"], + ["add_718_732_733.in0","_U216.out"], ["self.clk","_U218.clk"], + ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718.out","_U218.in"], ["_U219.in","_U218.out"], ["self.clk","_U219.clk"], ["_U220.in","_U219.out"], @@ -31939,123 +31939,123 @@ ["self.clk","_U228.clk"], ["_U229.in","_U228.out"], ["self.clk","_U229.clk"], - ["_U232.out","_U230.in"], - ["add_718_732_733.in1","_U230.out"], + ["_U230.in","_U229.out"], + ["self.clk","_U230.clk"], + ["_U231.in","_U230.out"], + ["self.clk","_U231.clk"], + ["_U232.in","_U231.out"], ["self.clk","_U232.clk"], - ["add_conv_stencil_1_731_732.out","_U232.in"], - ["add_718_732_733.out","_U233.in"], - ["self.out_conv_stencil","_U233.out"], - ["_U37.out","_U34.in"], - ["mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720.in1","_U34.out"], - ["self.clk","_U36.clk"], - ["self.in1_hw_input_global_wrapper_stencil.2","_U36.in"], - ["_U37.in","_U36.out"], + ["_U34.out","_U32.in"], + ["mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719.in1","_U32.out"], + ["self.clk","_U34.clk"], + ["self.in1_hw_input_global_wrapper_stencil.1","_U34.in"], + ["_U38.out","_U35.in"], + ["mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720.in0","_U35.out"], ["self.clk","_U37.clk"], - ["_U42.out","_U38.in"], - ["mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721.in0","_U38.out"], - ["self.clk","_U40.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.3","_U40.in"], - ["_U41.in","_U40.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.2","_U37.in"], + ["_U38.in","_U37.out"], + ["self.clk","_U38.clk"], + ["_U42.out","_U39.in"], + ["mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720.in1","_U39.out"], ["self.clk","_U41.clk"], + ["self.in1_hw_input_global_wrapper_stencil.2","_U41.in"], ["_U42.in","_U41.out"], ["self.clk","_U42.clk"], ["_U47.out","_U43.in"], - ["mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721.in1","_U43.out"], + ["mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721.in0","_U43.out"], ["self.clk","_U45.clk"], - ["self.in1_hw_input_global_wrapper_stencil.3","_U45.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.3","_U45.in"], ["_U46.in","_U45.out"], ["self.clk","_U46.clk"], ["_U47.in","_U46.out"], ["self.clk","_U47.clk"], - ["_U53.out","_U48.in"], - ["mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722.in0","_U48.out"], + ["_U52.out","_U48.in"], + ["mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721.in1","_U48.out"], ["self.clk","_U50.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.4","_U50.in"], + ["self.in1_hw_input_global_wrapper_stencil.3","_U50.in"], ["_U51.in","_U50.out"], ["self.clk","_U51.clk"], ["_U52.in","_U51.out"], ["self.clk","_U52.clk"], - ["_U53.in","_U52.out"], - ["self.clk","_U53.clk"], - ["_U59.out","_U54.in"], - ["mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722.in1","_U54.out"], + ["_U58.out","_U53.in"], + ["mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722.in0","_U53.out"], + ["self.clk","_U55.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.4","_U55.in"], + ["_U56.in","_U55.out"], ["self.clk","_U56.clk"], - ["self.in1_hw_input_global_wrapper_stencil.4","_U56.in"], ["_U57.in","_U56.out"], ["self.clk","_U57.clk"], ["_U58.in","_U57.out"], ["self.clk","_U58.clk"], - ["_U59.in","_U58.out"], - ["self.clk","_U59.clk"], - ["_U66.out","_U60.in"], - ["mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723.in0","_U60.out"], + ["_U64.out","_U59.in"], + ["mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722.in1","_U59.out"], + ["self.clk","_U61.clk"], + ["self.in1_hw_input_global_wrapper_stencil.4","_U61.in"], + ["_U62.in","_U61.out"], ["self.clk","_U62.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.5","_U62.in"], ["_U63.in","_U62.out"], ["self.clk","_U63.clk"], ["_U64.in","_U63.out"], ["self.clk","_U64.clk"], - ["_U65.in","_U64.out"], - ["self.clk","_U65.clk"], - ["_U66.in","_U65.out"], - ["self.clk","_U66.clk"], - ["_U73.out","_U67.in"], - ["mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723.in1","_U67.out"], + ["_U71.out","_U65.in"], + ["mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723.in0","_U65.out"], + ["self.clk","_U67.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.5","_U67.in"], + ["_U68.in","_U67.out"], + ["self.clk","_U68.clk"], + ["_U69.in","_U68.out"], ["self.clk","_U69.clk"], - ["self.in1_hw_input_global_wrapper_stencil.5","_U69.in"], ["_U70.in","_U69.out"], ["self.clk","_U70.clk"], ["_U71.in","_U70.out"], ["self.clk","_U71.clk"], - ["_U72.in","_U71.out"], - ["self.clk","_U72.clk"], - ["_U73.in","_U72.out"], - ["self.clk","_U73.clk"], - ["_U81.out","_U74.in"], - ["mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724.in0","_U74.out"], + ["_U78.out","_U72.in"], + ["mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723.in1","_U72.out"], + ["self.clk","_U74.clk"], + ["self.in1_hw_input_global_wrapper_stencil.5","_U74.in"], + ["_U75.in","_U74.out"], + ["self.clk","_U75.clk"], + ["_U76.in","_U75.out"], ["self.clk","_U76.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.6","_U76.in"], ["_U77.in","_U76.out"], ["self.clk","_U77.clk"], ["_U78.in","_U77.out"], ["self.clk","_U78.clk"], - ["_U79.in","_U78.out"], - ["self.clk","_U79.clk"], - ["_U80.in","_U79.out"], - ["self.clk","_U80.clk"], - ["_U81.in","_U80.out"], + ["_U86.out","_U79.in"], + ["mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724.in0","_U79.out"], ["self.clk","_U81.clk"], - ["_U89.out","_U82.in"], - ["mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724.in1","_U82.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.6","_U81.in"], + ["_U82.in","_U81.out"], + ["self.clk","_U82.clk"], + ["_U83.in","_U82.out"], + ["self.clk","_U83.clk"], + ["_U84.in","_U83.out"], ["self.clk","_U84.clk"], - ["self.in1_hw_input_global_wrapper_stencil.6","_U84.in"], ["_U85.in","_U84.out"], ["self.clk","_U85.clk"], ["_U86.in","_U85.out"], ["self.clk","_U86.clk"], - ["_U87.in","_U86.out"], - ["self.clk","_U87.clk"], - ["_U88.in","_U87.out"], - ["self.clk","_U88.clk"], - ["_U89.in","_U88.out"], + ["_U94.out","_U87.in"], + ["mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724.in1","_U87.out"], ["self.clk","_U89.clk"], - ["_U98.out","_U90.in"], - ["mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725.in0","_U90.out"], + ["self.in1_hw_input_global_wrapper_stencil.6","_U89.in"], + ["_U90.in","_U89.out"], + ["self.clk","_U90.clk"], + ["_U91.in","_U90.out"], + ["self.clk","_U91.clk"], + ["_U92.in","_U91.out"], ["self.clk","_U92.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.7","_U92.in"], ["_U93.in","_U92.out"], ["self.clk","_U93.clk"], ["_U94.in","_U93.out"], ["self.clk","_U94.clk"], - ["_U95.in","_U94.out"], - ["self.clk","_U95.clk"], - ["_U96.in","_U95.out"], - ["self.clk","_U96.clk"], - ["_U97.in","_U96.out"], + ["add_723_726_727.in0","_U95.out"], ["self.clk","_U97.clk"], + ["mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723.out","_U97.in"], ["_U98.in","_U97.out"], ["self.clk","_U98.clk"], - ["mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725.in1","_U99.out"] + ["_U99.in","_U98.out"], + ["self.clk","_U99.clk"] ] }, "hcompute_conv_stencil_9":{ @@ -32200,14 +32200,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U241":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U242":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U241_pt__U242" }, "_U243":{ "genref":"mantle.reg", @@ -32245,39 +32238,39 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U250":{ - "modref":"global._U250_pt__U251" - }, - "_U252":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U253":{ - "modref":"global._U253_pt__U254" - }, - "_U255":{ - "modref":"global._U255_pt__U256" - }, - "_U257":{ + "_U251":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U258":{ + "_U252":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U259":{ + "_U253":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U260":{ + "_U254":{ + "modref":"global._U254_pt__U255" + }, + "_U256":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U257":{ + "modref":"global._U257_pt__U258" + }, + "_U259":{ + "modref":"global._U259_pt__U260" + }, "_U261":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32309,34 +32302,34 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U267":{ - "modref":"global._U267_pt__U268" - }, - "_U269":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U270":{ - "modref":"global._U270_pt__U271" - }, - "_U272":{ + "_U268":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U273":{ - "modref":"global._U273_pt__U274" + "_U269":{ + "modref":"global._U269_pt__U270" }, - "_U275":{ + "_U271":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U276":{ + "_U272":{ + "modref":"global._U272_pt__U273" + }, + "_U274":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U275":{ + "modref":"global._U275_pt__U276" + }, "_U277":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32399,26 +32392,26 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U292":{ + "modref":"global._U292_pt__U293" + }, + "_U294":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U293":{ + "_U295":{ + "modref":"global._U295_pt__U296" + }, + "_U297":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U294":{ - "modref":"global._U294_pt__U295" - }, - "_U296":{ + "_U298":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U297":{ - "modref":"global._U297_pt__U298" - }, "_U299":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32440,7 +32433,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U303":{ - "modref":"global._U303_pt__U304" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U304":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U305":{ "genref":"mantle.reg", @@ -32448,13 +32448,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U306":{ - "modref":"global._U306_pt__U307" - }, - "_U308":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U307":{ + "modref":"global._U307_pt__U308" + }, "_U309":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32469,43 +32469,43 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U313":{ - "modref":"global._U313_pt__U314" - }, - "_U315":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U316":{ + "_U314":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U317":{ + "_U315":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U318":{ + "_U316":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U319":{ + "_U317":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U320":{ + "_U318":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U321":{ + "_U319":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U320":{ + "modref":"global._U320_pt__U321" + }, "_U322":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32545,13 +32545,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U331":{ + "modref":"global._U331_pt__U332" + }, + "_U333":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U332":{ - "modref":"global._U332_pt__U333" - }, "_U334":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32573,14 +32573,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U338":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U339":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U338_pt__U339" }, "_U340":{ "genref":"mantle.reg", @@ -32623,7 +32616,14 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U348":{ - "modref":"global._U348_pt__U349" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U349":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U350":{ "genref":"mantle.reg", @@ -32641,13 +32641,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U353":{ - "modref":"global._U353_pt__U354" - }, - "_U355":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U354":{ + "modref":"global._U354_pt__U355" + }, "_U356":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32659,30 +32659,37 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U358":{ - "modref":"global._U358_pt__U359" - }, - "_U360":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U361":{ + "_U359":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U362":{ + "_U360":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U361":{ + "modref":"global._U361_pt__U362" + }, "_U363":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U364":{ - "modref":"global._U364_pt__U365" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U365":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U366":{ "genref":"mantle.reg", @@ -32695,18 +32702,18 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U368":{ + "modref":"global._U368_pt__U369" + }, + "_U370":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U369":{ + "_U371":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U370":{ - "modref":"global._U370_pt__U371" - }, "_U372":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32728,13 +32735,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U376":{ + "modref":"global._U376_pt__U377" + }, + "_U378":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U377":{ - "modref":"global._U377_pt__U378" - }, "_U379":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32794,13 +32801,13 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U392":{ - "modref":"global._U392_pt__U393" - }, - "_U394":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U393":{ + "modref":"global._U393_pt__U394" + }, "_U395":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, @@ -32827,37 +32834,23 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U400":{ - "modref":"global._U400_pt__U401" - }, - "_U402":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U403":{ + "_U401":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U404":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U402":{ + "modref":"global._U402_pt__U403" }, - "_U405":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "_U404":{ + "modref":"global._U404_pt__U405" }, "_U406":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U407":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U406_pt__U407" }, "_U408":{ "genref":"mantle.reg", @@ -32873,14 +32866,7 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U412":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} - }, - "_U413":{ - "genref":"mantle.reg", - "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, - "modargs":{"init":[["BitVector",16],"16'h0000"]} + "modref":"global._U412_pt__U413" }, "_U414":{ "genref":"mantle.reg", @@ -32893,23 +32879,30 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U416":{ + "modref":"global._U416_pt__U417" + }, + "_U418":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U417":{ + "_U419":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U418":{ - "modref":"global._U418_pt__U419" - }, "_U420":{ "modref":"global._U420_pt__U421" }, "_U422":{ - "modref":"global._U422_pt__U423" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U423":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U424":{ "genref":"mantle.reg", @@ -32925,20 +32918,27 @@ "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U428":{ - "modref":"global._U428_pt__U429" - }, - "_U430":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, - "_U431":{ + "_U429":{ "genref":"mantle.reg", "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, "modargs":{"init":[["BitVector",16],"16'h0000"]} }, + "_U430":{ + "modref":"global._U430_pt__U431" + }, "_U432":{ - "modref":"global._U432_pt__U433" + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} + }, + "_U433":{ + "genref":"mantle.reg", + "genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]}, + "modargs":{"init":[["BitVector",16],"16'h0000"]} }, "_U434":{ "genref":"mantle.reg", @@ -33016,22 +33016,20 @@ } }, "connections":[ - ["_U249.out","_U235.in"], - ["add_785_799_800.in0","_U235.out"], + ["_U240.out","_U235.in"], + ["mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785.in1","_U235.out"], ["self.clk","_U237.clk"], - ["mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785.out","_U237.in"], + ["self.in1_hw_input_global_wrapper_stencil.7","_U237.in"], ["_U238.in","_U237.out"], ["self.clk","_U238.clk"], ["_U239.in","_U238.out"], ["self.clk","_U239.clk"], ["_U240.in","_U239.out"], ["self.clk","_U240.clk"], - ["_U241.in","_U240.out"], - ["self.clk","_U241.clk"], - ["_U242.in","_U241.out"], - ["self.clk","_U242.clk"], - ["_U243.in","_U242.out"], + ["_U253.out","_U241.in"], + ["add_785_799_800.in0","_U241.out"], ["self.clk","_U243.clk"], + ["mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785.out","_U243.in"], ["_U244.in","_U243.out"], ["self.clk","_U244.clk"], ["_U245.in","_U244.out"], @@ -33044,24 +33042,24 @@ ["self.clk","_U248.clk"], ["_U249.in","_U248.out"], ["self.clk","_U249.clk"], - ["_U252.out","_U250.in"], - ["add_785_799_800.in1","_U250.out"], + ["_U250.in","_U249.out"], + ["self.clk","_U250.clk"], + ["_U251.in","_U250.out"], + ["self.clk","_U251.clk"], + ["_U252.in","_U251.out"], ["self.clk","_U252.clk"], - ["add_conv_stencil_2_798_799.out","_U252.in"], - ["add_785_799_800.out","_U253.in"], - ["self.out_conv_stencil","_U253.out"], - ["_U266.out","_U255.in"], - ["add_786_797_798.in0","_U255.out"], - ["self.clk","_U257.clk"], - ["mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786.out","_U257.in"], - ["_U258.in","_U257.out"], - ["self.clk","_U258.clk"], - ["_U259.in","_U258.out"], - ["self.clk","_U259.clk"], - ["_U260.in","_U259.out"], - ["self.clk","_U260.clk"], - ["_U261.in","_U260.out"], + ["_U253.in","_U252.out"], + ["self.clk","_U253.clk"], + ["_U256.out","_U254.in"], + ["add_785_799_800.in1","_U254.out"], + ["self.clk","_U256.clk"], + ["add_conv_stencil_2_798_799.out","_U256.in"], + ["add_785_799_800.out","_U257.in"], + ["self.out_conv_stencil","_U257.out"], + ["_U268.out","_U259.in"], + ["add_786_797_798.in0","_U259.out"], ["self.clk","_U261.clk"], + ["mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786.out","_U261.in"], ["_U262.in","_U261.out"], ["self.clk","_U262.clk"], ["_U263.in","_U262.out"], @@ -33072,22 +33070,22 @@ ["self.clk","_U265.clk"], ["_U266.in","_U265.out"], ["self.clk","_U266.clk"], - ["_U269.out","_U267.in"], - ["add_786_797_798.in1","_U267.out"], - ["self.clk","_U269.clk"], - ["add_787_796_797.out","_U269.in"], - ["_U272.out","_U270.in"], - ["add_conv_stencil_2_798_799.in1","_U270.out"], - ["self.clk","_U272.clk"], - ["add_786_797_798.out","_U272.in"], - ["_U282.out","_U273.in"], - ["add_787_796_797.in0","_U273.out"], - ["self.clk","_U275.clk"], - ["mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787.out","_U275.in"], - ["_U276.in","_U275.out"], - ["self.clk","_U276.clk"], - ["_U277.in","_U276.out"], + ["_U267.in","_U266.out"], + ["self.clk","_U267.clk"], + ["_U268.in","_U267.out"], + ["self.clk","_U268.clk"], + ["_U271.out","_U269.in"], + ["add_786_797_798.in1","_U269.out"], + ["self.clk","_U271.clk"], + ["add_787_796_797.out","_U271.in"], + ["_U274.out","_U272.in"], + ["add_conv_stencil_2_798_799.in1","_U272.out"], + ["self.clk","_U274.clk"], + ["add_786_797_798.out","_U274.in"], + ["_U282.out","_U275.in"], + ["add_787_796_797.in0","_U275.out"], ["self.clk","_U277.clk"], + ["mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787.out","_U277.in"], ["_U278.in","_U277.out"], ["self.clk","_U278.clk"], ["_U279.in","_U278.out"], @@ -33102,7 +33100,7 @@ ["add_787_796_797.in1","_U283.out"], ["self.clk","_U285.clk"], ["add_788_795_796.out","_U285.in"], - ["_U293.out","_U286.in"], + ["_U291.out","_U286.in"], ["add_788_795_796.in0","_U286.out"], ["self.clk","_U288.clk"], ["mul_hw_kernel_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_788.out","_U288.in"], @@ -33112,42 +33110,46 @@ ["self.clk","_U290.clk"], ["_U291.in","_U290.out"], ["self.clk","_U291.clk"], - ["_U292.in","_U291.out"], - ["self.clk","_U292.clk"], - ["_U293.in","_U292.out"], - ["self.clk","_U293.clk"], - ["_U296.out","_U294.in"], - ["add_788_795_796.in1","_U294.out"], - ["self.clk","_U296.clk"], - ["add_789_794_795.out","_U296.in"], - ["_U302.out","_U297.in"], - ["add_789_794_795.in0","_U297.out"], + ["_U294.out","_U292.in"], + ["add_788_795_796.in1","_U292.out"], + ["self.clk","_U294.clk"], + ["add_789_794_795.out","_U294.in"], + ["_U306.out","_U295.in"], + ["add_789_794_795.in0","_U295.out"], + ["self.clk","_U297.clk"], + ["mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789.out","_U297.in"], + ["_U298.in","_U297.out"], + ["self.clk","_U298.clk"], + ["_U299.in","_U298.out"], ["self.clk","_U299.clk"], - ["mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789.out","_U299.in"], ["_U300.in","_U299.out"], ["self.clk","_U300.clk"], ["_U301.in","_U300.out"], ["self.clk","_U301.clk"], ["_U302.in","_U301.out"], ["self.clk","_U302.clk"], - ["_U305.out","_U303.in"], - ["add_789_794_795.in1","_U303.out"], + ["_U303.in","_U302.out"], + ["self.clk","_U303.clk"], + ["_U304.in","_U303.out"], + ["self.clk","_U304.clk"], + ["_U305.in","_U304.out"], ["self.clk","_U305.clk"], - ["add_790_793_794.out","_U305.in"], - ["_U309.out","_U306.in"], - ["add_790_793_794.in0","_U306.out"], - ["self.clk","_U308.clk"], - ["mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790.out","_U308.in"], - ["_U309.in","_U308.out"], + ["_U306.in","_U305.out"], + ["self.clk","_U306.clk"], + ["_U309.out","_U307.in"], + ["add_789_794_795.in1","_U307.out"], ["self.clk","_U309.clk"], - ["_U312.out","_U310.in"], - ["add_790_793_794.in1","_U310.out"], + ["add_790_793_794.out","_U309.in"], + ["_U319.out","_U310.in"], + ["add_790_793_794.in0","_U310.out"], ["self.clk","_U312.clk"], - ["add_791_792_793.out","_U312.in"], - ["_U322.out","_U313.in"], - ["add_791_792_793.in0","_U313.out"], + ["mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790.out","_U312.in"], + ["_U313.in","_U312.out"], + ["self.clk","_U313.clk"], + ["_U314.in","_U313.out"], + ["self.clk","_U314.clk"], + ["_U315.in","_U314.out"], ["self.clk","_U315.clk"], - ["mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791.out","_U315.in"], ["_U316.in","_U315.out"], ["self.clk","_U316.clk"], ["_U317.in","_U316.out"], @@ -33156,16 +33158,14 @@ ["self.clk","_U318.clk"], ["_U319.in","_U318.out"], ["self.clk","_U319.clk"], - ["_U320.in","_U319.out"], - ["self.clk","_U320.clk"], - ["_U321.in","_U320.out"], - ["self.clk","_U321.clk"], - ["_U322.in","_U321.out"], + ["_U322.out","_U320.in"], + ["add_790_793_794.in1","_U320.out"], ["self.clk","_U322.clk"], - ["_U331.out","_U323.in"], - ["add_791_792_793.in1","_U323.out"], + ["add_791_792_793.out","_U322.in"], + ["_U330.out","_U323.in"], + ["add_791_792_793.in0","_U323.out"], ["self.clk","_U325.clk"], - ["mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792.out","_U325.in"], + ["mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791.out","_U325.in"], ["_U326.in","_U325.out"], ["self.clk","_U326.clk"], ["_U327.in","_U326.out"], @@ -33176,24 +33176,22 @@ ["self.clk","_U329.clk"], ["_U330.in","_U329.out"], ["self.clk","_U330.clk"], - ["_U331.in","_U330.out"], - ["self.clk","_U331.clk"], - ["_U347.out","_U332.in"], - ["add_conv_stencil_2_798_799.in0","_U332.out"], + ["_U337.out","_U331.in"], + ["add_791_792_793.in1","_U331.out"], + ["self.clk","_U333.clk"], + ["mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792.out","_U333.in"], + ["_U334.in","_U333.out"], ["self.clk","_U334.clk"], - ["self.in0_conv_stencil.0","_U334.in"], ["_U335.in","_U334.out"], ["self.clk","_U335.clk"], ["_U336.in","_U335.out"], ["self.clk","_U336.clk"], ["_U337.in","_U336.out"], ["self.clk","_U337.clk"], - ["_U338.in","_U337.out"], - ["self.clk","_U338.clk"], - ["_U339.in","_U338.out"], - ["self.clk","_U339.clk"], - ["_U340.in","_U339.out"], + ["_U353.out","_U338.in"], + ["add_conv_stencil_2_798_799.in0","_U338.out"], ["self.clk","_U340.clk"], + ["self.in0_conv_stencil.0","_U340.in"], ["_U341.in","_U340.out"], ["self.clk","_U341.clk"], ["_U342.in","_U341.out"], @@ -33208,58 +33206,62 @@ ["self.clk","_U346.clk"], ["_U347.in","_U346.out"], ["self.clk","_U347.clk"], - ["_U352.out","_U348.in"], - ["mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786.in0","_U348.out"], + ["_U348.in","_U347.out"], + ["self.clk","_U348.clk"], + ["_U349.in","_U348.out"], + ["self.clk","_U349.clk"], + ["_U350.in","_U349.out"], ["self.clk","_U350.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.0","_U350.in"], ["_U351.in","_U350.out"], ["self.clk","_U351.clk"], ["_U352.in","_U351.out"], ["self.clk","_U352.clk"], - ["_U357.out","_U353.in"], - ["mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786.in1","_U353.out"], - ["self.clk","_U355.clk"], - ["self.in1_hw_input_global_wrapper_stencil.0","_U355.in"], - ["_U356.in","_U355.out"], + ["_U353.in","_U352.out"], + ["self.clk","_U353.clk"], + ["_U360.out","_U354.in"], + ["mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786.in0","_U354.out"], ["self.clk","_U356.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","_U356.in"], ["_U357.in","_U356.out"], ["self.clk","_U357.clk"], - ["_U363.out","_U358.in"], - ["mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787.in0","_U358.out"], + ["_U358.in","_U357.out"], + ["self.clk","_U358.clk"], + ["_U359.in","_U358.out"], + ["self.clk","_U359.clk"], + ["_U360.in","_U359.out"], ["self.clk","_U360.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.1","_U360.in"], - ["_U361.in","_U360.out"], - ["self.clk","_U361.clk"], - ["_U362.in","_U361.out"], - ["self.clk","_U362.clk"], - ["_U363.in","_U362.out"], + ["_U367.out","_U361.in"], + ["mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786.in1","_U361.out"], ["self.clk","_U363.clk"], - ["_U369.out","_U364.in"], - ["mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787.in1","_U364.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","_U363.in"], + ["_U364.in","_U363.out"], + ["self.clk","_U364.clk"], + ["_U365.in","_U364.out"], + ["self.clk","_U365.clk"], + ["_U366.in","_U365.out"], ["self.clk","_U366.clk"], - ["self.in1_hw_input_global_wrapper_stencil.1","_U366.in"], ["_U367.in","_U366.out"], ["self.clk","_U367.clk"], - ["_U368.in","_U367.out"], - ["self.clk","_U368.clk"], - ["_U369.in","_U368.out"], - ["self.clk","_U369.clk"], - ["_U376.out","_U370.in"], - ["mul_hw_kernel_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_788.in0","_U370.out"], + ["_U375.out","_U368.in"], + ["mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787.in0","_U368.out"], + ["self.clk","_U370.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.1","_U370.in"], + ["_U371.in","_U370.out"], + ["self.clk","_U371.clk"], + ["_U372.in","_U371.out"], ["self.clk","_U372.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.2","_U372.in"], ["_U373.in","_U372.out"], ["self.clk","_U373.clk"], ["_U374.in","_U373.out"], ["self.clk","_U374.clk"], ["_U375.in","_U374.out"], ["self.clk","_U375.clk"], - ["_U376.in","_U375.out"], - ["self.clk","_U376.clk"], - ["_U383.out","_U377.in"], - ["mul_hw_kernel_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_788.in1","_U377.out"], + ["_U383.out","_U376.in"], + ["mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787.in1","_U376.out"], + ["self.clk","_U378.clk"], + ["self.in1_hw_input_global_wrapper_stencil.1","_U378.in"], + ["_U379.in","_U378.out"], ["self.clk","_U379.clk"], - ["self.in1_hw_input_global_wrapper_stencil.2","_U379.in"], ["_U380.in","_U379.out"], ["self.clk","_U380.clk"], ["_U381.in","_U380.out"], @@ -33268,10 +33270,10 @@ ["self.clk","_U382.clk"], ["_U383.in","_U382.out"], ["self.clk","_U383.clk"], - ["_U391.out","_U384.in"], - ["mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789.in0","_U384.out"], + ["_U392.out","_U384.in"], + ["mul_hw_kernel_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_788.in0","_U384.out"], ["self.clk","_U386.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.3","_U386.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.2","_U386.in"], ["_U387.in","_U386.out"], ["self.clk","_U387.clk"], ["_U388.in","_U387.out"], @@ -33282,12 +33284,12 @@ ["self.clk","_U390.clk"], ["_U391.in","_U390.out"], ["self.clk","_U391.clk"], - ["_U399.out","_U392.in"], - ["mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789.in1","_U392.out"], - ["self.clk","_U394.clk"], - ["self.in1_hw_input_global_wrapper_stencil.3","_U394.in"], - ["_U395.in","_U394.out"], + ["_U392.in","_U391.out"], + ["self.clk","_U392.clk"], + ["_U401.out","_U393.in"], + ["mul_hw_kernel_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_788.in1","_U393.out"], ["self.clk","_U395.clk"], + ["self.in1_hw_input_global_wrapper_stencil.2","_U395.in"], ["_U396.in","_U395.out"], ["self.clk","_U396.clk"], ["_U397.in","_U396.out"], @@ -33296,60 +33298,58 @@ ["self.clk","_U398.clk"], ["_U399.in","_U398.out"], ["self.clk","_U399.clk"], - ["_U408.out","_U400.in"], - ["mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790.in0","_U400.out"], - ["self.clk","_U402.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.4","_U402.in"], - ["_U403.in","_U402.out"], - ["self.clk","_U403.clk"], - ["_U404.in","_U403.out"], - ["self.clk","_U404.clk"], - ["_U405.in","_U404.out"], - ["self.clk","_U405.clk"], - ["_U406.in","_U405.out"], - ["self.clk","_U406.clk"], - ["_U407.in","_U406.out"], - ["self.clk","_U407.clk"], - ["_U408.in","_U407.out"], + ["_U400.in","_U399.out"], + ["self.clk","_U400.clk"], + ["_U401.in","_U400.out"], + ["self.clk","_U401.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.3","_U402.in"], + ["mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789.in0","_U402.out"], + ["self.in1_hw_input_global_wrapper_stencil.3","_U404.in"], + ["mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789.in1","_U404.out"], + ["_U408.out","_U406.in"], + ["mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790.in0","_U406.out"], ["self.clk","_U408.clk"], - ["_U417.out","_U409.in"], + ["self.in2_hw_kernel_global_wrapper_stencil.4","_U408.in"], + ["_U411.out","_U409.in"], ["mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790.in1","_U409.out"], ["self.clk","_U411.clk"], ["self.in1_hw_input_global_wrapper_stencil.4","_U411.in"], - ["_U412.in","_U411.out"], - ["self.clk","_U412.clk"], - ["_U413.in","_U412.out"], - ["self.clk","_U413.clk"], - ["_U414.in","_U413.out"], + ["_U415.out","_U412.in"], + ["mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791.in0","_U412.out"], ["self.clk","_U414.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.5","_U414.in"], ["_U415.in","_U414.out"], ["self.clk","_U415.clk"], - ["_U416.in","_U415.out"], - ["self.clk","_U416.clk"], - ["_U417.in","_U416.out"], - ["self.clk","_U417.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.5","_U418.in"], - ["mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791.in0","_U418.out"], - ["self.in1_hw_input_global_wrapper_stencil.5","_U420.in"], - ["mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791.in1","_U420.out"], - ["_U424.out","_U422.in"], - ["mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792.in0","_U422.out"], + ["_U419.out","_U416.in"], + ["mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791.in1","_U416.out"], + ["self.clk","_U418.clk"], + ["self.in1_hw_input_global_wrapper_stencil.5","_U418.in"], + ["_U419.in","_U418.out"], + ["self.clk","_U419.clk"], + ["_U424.out","_U420.in"], + ["mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792.in0","_U420.out"], + ["self.clk","_U422.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.6","_U422.in"], + ["_U423.in","_U422.out"], + ["self.clk","_U423.clk"], + ["_U424.in","_U423.out"], ["self.clk","_U424.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.6","_U424.in"], - ["_U427.out","_U425.in"], + ["_U429.out","_U425.in"], ["mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792.in1","_U425.out"], ["self.clk","_U427.clk"], ["self.in1_hw_input_global_wrapper_stencil.6","_U427.in"], - ["_U431.out","_U428.in"], - ["mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785.in0","_U428.out"], - ["self.clk","_U430.clk"], - ["self.in2_hw_kernel_global_wrapper_stencil.7","_U430.in"], - ["_U431.in","_U430.out"], - ["self.clk","_U431.clk"], - ["_U435.out","_U432.in"], - ["mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785.in1","_U432.out"], + ["_U428.in","_U427.out"], + ["self.clk","_U428.clk"], + ["_U429.in","_U428.out"], + ["self.clk","_U429.clk"], + ["_U435.out","_U430.in"], + ["mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785.in0","_U430.out"], + ["self.clk","_U432.clk"], + ["self.in2_hw_kernel_global_wrapper_stencil.7","_U432.in"], + ["_U433.in","_U432.out"], + ["self.clk","_U433.clk"], + ["_U434.in","_U433.out"], ["self.clk","_U434.clk"], - ["self.in1_hw_input_global_wrapper_stencil.7","_U434.in"], ["_U435.in","_U434.out"], ["self.clk","_U435.clk"] ] @@ -33359,8 +33359,8 @@ ["out_conv_stencil",["Array",16,"Bit"]] ]], "instances":{ - "_U18":{ - "modref":"global._U18_pt__U19" + "_U16":{ + "modref":"global._U16_pt__U17" }, "const_p0__679":{ "genref":"coreir.const", @@ -33369,8 +33369,8 @@ } }, "connections":[ - ["const_p0__679.out","_U18.in"], - ["self.out_conv_stencil","_U18.out"] + ["const_p0__679.out","_U16.in"], + ["self.out_conv_stencil","_U16.out"] ] }, "hcompute_hw_input_global_wrapper_stencil":{ @@ -33397,13 +33397,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U2":{ - "modref":"global._U2_pt__U3" + "_U6":{ + "modref":"global._U6_pt__U7" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U2.in"], - ["self.out_hw_input_global_wrapper_stencil","_U2.out"] + ["self.in0_hw_input_stencil.0","_U6.in"], + ["self.out_hw_input_global_wrapper_stencil","_U6.out"] ] }, "hcompute_hw_input_global_wrapper_stencil_2":{ @@ -33421,13 +33421,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U4":{ - "modref":"global._U4_pt__U5" + "_U10":{ + "modref":"global._U10_pt__U11" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U4.in"], - ["self.out_hw_input_global_wrapper_stencil","_U4.out"] + ["self.in0_hw_input_stencil.0","_U10.in"], + ["self.out_hw_input_global_wrapper_stencil","_U10.out"] ] }, "hcompute_hw_input_global_wrapper_stencil_3":{ @@ -33445,13 +33445,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U6":{ - "modref":"global._U6_pt__U7" + "_U8":{ + "modref":"global._U8_pt__U9" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U6.in"], - ["self.out_hw_input_global_wrapper_stencil","_U6.out"] + ["self.in0_hw_input_stencil.0","_U8.in"], + ["self.out_hw_input_global_wrapper_stencil","_U8.out"] ] }, "hcompute_hw_input_global_wrapper_stencil_4":{ @@ -33469,13 +33469,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U8":{ - "modref":"global._U8_pt__U9" + "_U0":{ + "modref":"global._U0_pt__U1" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U8.in"], - ["self.out_hw_input_global_wrapper_stencil","_U8.out"] + ["self.in0_hw_input_stencil.0","_U0.in"], + ["self.out_hw_input_global_wrapper_stencil","_U0.out"] ] }, "hcompute_hw_input_global_wrapper_stencil_5":{ @@ -33493,13 +33493,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U10":{ - "modref":"global._U10_pt__U11" + "_U2":{ + "modref":"global._U2_pt__U3" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U10.in"], - ["self.out_hw_input_global_wrapper_stencil","_U10.out"] + ["self.in0_hw_input_stencil.0","_U2.in"], + ["self.out_hw_input_global_wrapper_stencil","_U2.out"] ] }, "hcompute_hw_input_global_wrapper_stencil_6":{ @@ -33517,13 +33517,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U12":{ - "modref":"global._U12_pt__U13" + "_U4":{ + "modref":"global._U4_pt__U5" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U12.in"], - ["self.out_hw_input_global_wrapper_stencil","_U12.out"] + ["self.in0_hw_input_stencil.0","_U4.in"], + ["self.out_hw_input_global_wrapper_stencil","_U4.out"] ] }, "hcompute_hw_input_global_wrapper_stencil_7":{ @@ -33541,13 +33541,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U14":{ - "modref":"global._U14_pt__U15" + "_U233":{ + "modref":"global._U233_pt__U234" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U14.in"], - ["self.out_hw_input_global_wrapper_stencil","_U14.out"] + ["self.in0_hw_input_stencil.0","_U233.in"], + ["self.out_hw_input_global_wrapper_stencil","_U233.out"] ] }, "hcompute_hw_input_global_wrapper_stencil_pipelined":{ @@ -33556,13 +33556,13 @@ ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U0":{ - "modref":"global._U0_pt__U1" + "_U12":{ + "modref":"global._U12_pt__U13" } }, "connections":[ - ["self.in0_hw_input_stencil.0","_U0.in"], - ["self.out_hw_input_global_wrapper_stencil","_U0.out"] + ["self.in0_hw_input_stencil.0","_U12.in"], + ["self.out_hw_input_global_wrapper_stencil","_U12.out"] ] }, "hcompute_hw_kernel_global_wrapper_stencil":{ @@ -33580,13 +33580,13 @@ ["in0_hw_kernel_stencil",["Array",1,["Array",16,"BitIn"]]] ]], "instances":{ - "_U16":{ - "modref":"global._U16_pt__U17" + "_U14":{ + "modref":"global._U14_pt__U15" } }, "connections":[ - ["self.in0_hw_kernel_stencil.0","_U16.in"], - ["self.out_hw_kernel_global_wrapper_stencil","_U16.out"] + ["self.in0_hw_kernel_stencil.0","_U14.in"], + ["self.out_hw_kernel_global_wrapper_stencil","_U14.out"] ] }, "hcompute_hw_output_stencil":{ @@ -34194,7 +34194,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U263":{ + "op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U240":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34203,7 +34203,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_exe_start_pt__U262":{ + "op_hcompute_conv_stencil_1_exe_start_pt__U239":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34212,7 +34212,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_read_start_control_vars_pt__U261":{ + "op_hcompute_conv_stencil_1_read_start_control_vars_pt__U238":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34221,7 +34221,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_read_start_pt__U260":{ + "op_hcompute_conv_stencil_1_read_start_pt__U237":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34230,7 +34230,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_write_start_control_vars_pt__U265":{ + "op_hcompute_conv_stencil_1_write_start_control_vars_pt__U242":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34239,7 +34239,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_1_write_start_pt__U264":{ + "op_hcompute_conv_stencil_1_write_start_pt__U241":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34248,7 +34248,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U286":{ + "op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U263":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34257,7 +34257,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_exe_start_pt__U285":{ + "op_hcompute_conv_stencil_2_exe_start_pt__U262":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34266,7 +34266,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_read_start_control_vars_pt__U284":{ + "op_hcompute_conv_stencil_2_read_start_control_vars_pt__U261":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34275,7 +34275,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_read_start_pt__U283":{ + "op_hcompute_conv_stencil_2_read_start_pt__U260":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34284,7 +34284,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_write_start_control_vars_pt__U288":{ + "op_hcompute_conv_stencil_2_write_start_control_vars_pt__U265":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34293,7 +34293,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_2_write_start_pt__U287":{ + "op_hcompute_conv_stencil_2_write_start_pt__U264":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34302,7 +34302,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U309":{ + "op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U286":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34311,7 +34311,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_exe_start_pt__U308":{ + "op_hcompute_conv_stencil_3_exe_start_pt__U285":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34320,7 +34320,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_read_start_control_vars_pt__U307":{ + "op_hcompute_conv_stencil_3_read_start_control_vars_pt__U284":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34329,7 +34329,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_read_start_pt__U306":{ + "op_hcompute_conv_stencil_3_read_start_pt__U283":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34338,7 +34338,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_write_start_control_vars_pt__U311":{ + "op_hcompute_conv_stencil_3_write_start_control_vars_pt__U288":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34347,7 +34347,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_3_write_start_pt__U310":{ + "op_hcompute_conv_stencil_3_write_start_pt__U287":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34356,7 +34356,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U332":{ + "op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U309":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34365,7 +34365,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_exe_start_pt__U331":{ + "op_hcompute_conv_stencil_4_exe_start_pt__U308":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34374,7 +34374,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_read_start_control_vars_pt__U330":{ + "op_hcompute_conv_stencil_4_read_start_control_vars_pt__U307":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34383,7 +34383,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_read_start_pt__U329":{ + "op_hcompute_conv_stencil_4_read_start_pt__U306":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34392,7 +34392,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_write_start_control_vars_pt__U334":{ + "op_hcompute_conv_stencil_4_write_start_control_vars_pt__U311":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34401,7 +34401,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_4_write_start_pt__U333":{ + "op_hcompute_conv_stencil_4_write_start_pt__U310":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34410,7 +34410,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U355":{ + "op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U332":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34419,7 +34419,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_exe_start_pt__U354":{ + "op_hcompute_conv_stencil_5_exe_start_pt__U331":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34428,7 +34428,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_read_start_control_vars_pt__U353":{ + "op_hcompute_conv_stencil_5_read_start_control_vars_pt__U330":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34437,7 +34437,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_read_start_pt__U352":{ + "op_hcompute_conv_stencil_5_read_start_pt__U329":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34446,7 +34446,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_write_start_control_vars_pt__U357":{ + "op_hcompute_conv_stencil_5_write_start_control_vars_pt__U334":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34455,7 +34455,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_5_write_start_pt__U356":{ + "op_hcompute_conv_stencil_5_write_start_pt__U333":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34464,7 +34464,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U378":{ + "op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U355":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34473,7 +34473,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_6_exe_start_pt__U377":{ + "op_hcompute_conv_stencil_6_exe_start_pt__U354":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34482,7 +34482,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_6_read_start_control_vars_pt__U376":{ + "op_hcompute_conv_stencil_6_read_start_control_vars_pt__U353":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34491,7 +34491,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_6_read_start_pt__U375":{ + "op_hcompute_conv_stencil_6_read_start_pt__U352":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34500,7 +34500,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_6_write_start_control_vars_pt__U380":{ + "op_hcompute_conv_stencil_6_write_start_control_vars_pt__U357":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34509,7 +34509,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_6_write_start_pt__U379":{ + "op_hcompute_conv_stencil_6_write_start_pt__U356":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34518,7 +34518,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U401":{ + "op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U378":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34527,7 +34527,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_7_exe_start_pt__U400":{ + "op_hcompute_conv_stencil_7_exe_start_pt__U377":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34536,7 +34536,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_7_read_start_control_vars_pt__U399":{ + "op_hcompute_conv_stencil_7_read_start_control_vars_pt__U376":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34545,7 +34545,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_7_read_start_pt__U398":{ + "op_hcompute_conv_stencil_7_read_start_pt__U375":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34554,7 +34554,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_7_write_start_control_vars_pt__U403":{ + "op_hcompute_conv_stencil_7_write_start_control_vars_pt__U380":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34563,7 +34563,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_7_write_start_pt__U402":{ + "op_hcompute_conv_stencil_7_write_start_pt__U379":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34572,7 +34572,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U439":{ + "op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U416":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -34581,7 +34581,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_8_exe_start_pt__U436":{ + "op_hcompute_conv_stencil_8_exe_start_pt__U413":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34590,7 +34590,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_8_read_start_control_vars_pt__U435":{ + "op_hcompute_conv_stencil_8_read_start_control_vars_pt__U412":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -34599,7 +34599,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_8_read_start_pt__U434":{ + "op_hcompute_conv_stencil_8_read_start_pt__U411":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34608,7 +34608,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_8_write_start_control_vars_pt__U472":{ + "op_hcompute_conv_stencil_8_write_start_control_vars_pt__U449":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -34617,7 +34617,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_8_write_start_pt__U454":{ + "op_hcompute_conv_stencil_8_write_start_pt__U431":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34680,7 +34680,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_exe_start_control_vars_pt__U240":{ + "op_hcompute_conv_stencil_exe_start_control_vars_pt__U217":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34689,7 +34689,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_exe_start_pt__U239":{ + "op_hcompute_conv_stencil_exe_start_pt__U216":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34698,7 +34698,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_read_start_control_vars_pt__U238":{ + "op_hcompute_conv_stencil_read_start_control_vars_pt__U215":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34707,7 +34707,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_read_start_pt__U237":{ + "op_hcompute_conv_stencil_read_start_pt__U214":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34716,7 +34716,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_write_start_control_vars_pt__U242":{ + "op_hcompute_conv_stencil_write_start_control_vars_pt__U219":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34725,7 +34725,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_conv_stencil_write_start_pt__U241":{ + "op_hcompute_conv_stencil_write_start_pt__U218":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34734,7 +34734,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U43":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U89":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34743,7 +34743,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U42":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U88":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34752,7 +34752,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U41":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U87":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34761,7 +34761,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U40":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U86":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34770,7 +34770,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U45":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U91":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34779,7 +34779,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U44":{ + "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U90":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34788,7 +34788,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U66":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U135":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34797,7 +34797,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U65":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U134":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34806,7 +34806,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U64":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U133":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34815,7 +34815,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U63":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U132":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34824,7 +34824,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U68":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U137":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34833,7 +34833,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U67":{ + "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U136":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34842,7 +34842,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U89":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U112":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34851,7 +34851,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U88":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U111":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34860,7 +34860,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U87":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U110":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34869,7 +34869,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U86":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U109":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34878,7 +34878,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U91":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U114":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34887,7 +34887,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U90":{ + "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U113":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34896,7 +34896,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U112":{ + "op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U20":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34905,7 +34905,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U111":{ + "op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U19":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34914,7 +34914,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U110":{ + "op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U18":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34923,7 +34923,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U109":{ + "op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U17":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34932,7 +34932,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U114":{ + "op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U22":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34941,7 +34941,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U113":{ + "op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U21":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34950,7 +34950,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U135":{ + "op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U43":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34959,7 +34959,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U134":{ + "op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U42":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34968,7 +34968,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U133":{ + "op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U41":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34977,7 +34977,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U132":{ + "op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U40":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -34986,7 +34986,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U137":{ + "op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U45":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -34995,7 +34995,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U136":{ + "op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U44":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35004,7 +35004,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U158":{ + "op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U66":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35013,7 +35013,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U157":{ + "op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U65":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35022,7 +35022,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U156":{ + "op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U64":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35031,7 +35031,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U155":{ + "op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U63":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35040,7 +35040,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U160":{ + "op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U68":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35049,7 +35049,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U159":{ + "op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U67":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35058,7 +35058,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U181":{ + "op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U589":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35067,7 +35067,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U180":{ + "op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U588":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35076,7 +35076,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U179":{ + "op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U587":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35085,7 +35085,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U178":{ + "op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U586":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35094,7 +35094,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U183":{ + "op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U591":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35103,7 +35103,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U182":{ + "op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U590":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35112,7 +35112,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U20":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U158":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35121,7 +35121,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U19":{ + "op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U157":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35130,7 +35130,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U18":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U156":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35139,7 +35139,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U17":{ + "op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U155":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35148,7 +35148,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U22":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U160":{ "type":["Record",[ ["in",["Array",3,["Array",16,"BitIn"]]], ["out",["Array",3,["Array",16,"Bit"]]] @@ -35157,7 +35157,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U21":{ + "op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U159":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35166,7 +35166,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U217":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U194":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -35175,7 +35175,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U216":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U193":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35184,7 +35184,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U215":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U192":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -35193,7 +35193,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U214":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U191":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35202,7 +35202,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U219":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U196":{ "type":["Record",[ ["in",["Array",5,["Array",16,"BitIn"]]], ["out",["Array",5,["Array",16,"Bit"]]] @@ -35211,7 +35211,7 @@ ["self.out","self.in"] ] }, - "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U218":{ + "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U195":{ "type":["Record",[ ["in","BitIn"], ["out","Bit"] @@ -35657,20 +35657,20 @@ ["clk",["Named","coreir.clkIn"]], ["rst_n","BitIn"], ["flush","BitIn"], - ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], - ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], - ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], - ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","Bit"], - ["hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en","Bit"], - ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en","Bit"], - ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read",["Array",1,["Array",16,"BitIn"]]], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en","Bit"], - ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en","Bit"], + ["hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en","Bit"], + ["hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en","Bit"], + ["hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","Bit"], + ["hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","Bit"], + ["hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","Bit"], + ["hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read",["Array",1,["Array",16,"BitIn"]]], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en","Bit"], + ["hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read",["Array",1,["Array",16,"BitIn"]]], ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en","Bit"], ["hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read",["Array",1,["Array",16,"BitIn"]]], ["hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en","Bit"], @@ -36074,62 +36074,62 @@ "arr__U2279":{ "modref":"global.array_delay_U2280" }, - "arr__U440":{ - "modref":"global.array_delay_U441" + "arr__U417":{ + "modref":"global.array_delay_U418" }, - "arr__U447":{ - "modref":"global.array_delay_U448" + "arr__U424":{ + "modref":"global.array_delay_U425" }, - "arr__U473":{ - "modref":"global.array_delay_U474" + "arr__U450":{ + "modref":"global.array_delay_U451" }, - "arr__U480":{ - "modref":"global.array_delay_U481" + "arr__U457":{ + "modref":"global.array_delay_U458" }, - "arr__U487":{ - "modref":"global.array_delay_U488" + "arr__U464":{ + "modref":"global.array_delay_U465" }, - "arr__U494":{ - "modref":"global.array_delay_U495" + "arr__U471":{ + "modref":"global.array_delay_U472" }, - "arr__U501":{ - "modref":"global.array_delay_U502" + "arr__U478":{ + "modref":"global.array_delay_U479" }, - "arr__U508":{ - "modref":"global.array_delay_U509" + "arr__U485":{ + "modref":"global.array_delay_U486" }, - "arr__U515":{ - "modref":"global.array_delay_U516" + "arr__U492":{ + "modref":"global.array_delay_U493" }, - "arr__U522":{ - "modref":"global.array_delay_U523" + "arr__U499":{ + "modref":"global.array_delay_U500" }, - "arr__U529":{ - "modref":"global.array_delay_U530" + "arr__U506":{ + "modref":"global.array_delay_U507" }, - "arr__U536":{ - "modref":"global.array_delay_U537" + "arr__U513":{ + "modref":"global.array_delay_U514" }, - "arr__U543":{ - "modref":"global.array_delay_U544" + "arr__U520":{ + "modref":"global.array_delay_U521" }, - "arr__U550":{ - "modref":"global.array_delay_U551" + "arr__U527":{ + "modref":"global.array_delay_U528" }, - "arr__U557":{ - "modref":"global.array_delay_U558" + "arr__U534":{ + "modref":"global.array_delay_U535" }, - "arr__U564":{ - "modref":"global.array_delay_U565" + "arr__U541":{ + "modref":"global.array_delay_U542" }, - "arr__U571":{ - "modref":"global.array_delay_U572" + "arr__U548":{ + "modref":"global.array_delay_U549" }, - "arr__U578":{ - "modref":"global.array_delay_U579" + "arr__U555":{ + "modref":"global.array_delay_U556" }, - "arr__U585":{ - "modref":"global.array_delay_U586" + "arr__U562":{ + "modref":"global.array_delay_U563" }, "arr__U628":{ "modref":"global.array_delay_U629" @@ -36756,79 +36756,79 @@ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U437":{ + "delay_reg__U414":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U438":{ + "delay_reg__U415":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U455":{ + "delay_reg__U432":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U456":{ + "delay_reg__U433":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U457":{ + "delay_reg__U434":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U458":{ + "delay_reg__U435":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U459":{ + "delay_reg__U436":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U460":{ + "delay_reg__U437":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U461":{ + "delay_reg__U438":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U462":{ + "delay_reg__U439":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U463":{ + "delay_reg__U440":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U464":{ + "delay_reg__U441":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U465":{ + "delay_reg__U442":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U466":{ + "delay_reg__U443":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U467":{ + "delay_reg__U444":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U468":{ + "delay_reg__U445":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U469":{ + "delay_reg__U446":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U470":{ + "delay_reg__U447":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, - "delay_reg__U471":{ + "delay_reg__U448":{ "modref":"corebit.reg", "modargs":{"clk_posedge":["Bool",true], "init":["Bool",false]} }, @@ -37141,193 +37141,193 @@ "modref":"global.op_hcompute_conv_stencil_15_write_start_control_vars_pt__U1788" }, "op_hcompute_conv_stencil_1_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_1_exe_start_pt__U262" + "modref":"global.op_hcompute_conv_stencil_1_exe_start_pt__U239" }, "op_hcompute_conv_stencil_1_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U263" + "modref":"global.op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U240" }, "op_hcompute_conv_stencil_1_port_controller":{ - "modref":"global.affine_controller__U243" + "modref":"global.affine_controller__U220" }, "op_hcompute_conv_stencil_1_read_start":{ - "modref":"global.op_hcompute_conv_stencil_1_read_start_pt__U260" + "modref":"global.op_hcompute_conv_stencil_1_read_start_pt__U237" }, "op_hcompute_conv_stencil_1_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_1_read_start_control_vars_pt__U261" + "modref":"global.op_hcompute_conv_stencil_1_read_start_control_vars_pt__U238" }, "op_hcompute_conv_stencil_1_write_start":{ - "modref":"global.op_hcompute_conv_stencil_1_write_start_pt__U264" + "modref":"global.op_hcompute_conv_stencil_1_write_start_pt__U241" }, "op_hcompute_conv_stencil_1_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_1_write_start_control_vars_pt__U265" + "modref":"global.op_hcompute_conv_stencil_1_write_start_control_vars_pt__U242" }, "op_hcompute_conv_stencil_2":{ "modref":"global.cu_op_hcompute_conv_stencil_2" }, "op_hcompute_conv_stencil_2_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_2_exe_start_pt__U285" + "modref":"global.op_hcompute_conv_stencil_2_exe_start_pt__U262" }, "op_hcompute_conv_stencil_2_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U286" + "modref":"global.op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U263" }, "op_hcompute_conv_stencil_2_port_controller":{ - "modref":"global.affine_controller__U266" + "modref":"global.affine_controller__U243" }, "op_hcompute_conv_stencil_2_read_start":{ - "modref":"global.op_hcompute_conv_stencil_2_read_start_pt__U283" + "modref":"global.op_hcompute_conv_stencil_2_read_start_pt__U260" }, "op_hcompute_conv_stencil_2_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_2_read_start_control_vars_pt__U284" + "modref":"global.op_hcompute_conv_stencil_2_read_start_control_vars_pt__U261" }, "op_hcompute_conv_stencil_2_write_start":{ - "modref":"global.op_hcompute_conv_stencil_2_write_start_pt__U287" + "modref":"global.op_hcompute_conv_stencil_2_write_start_pt__U264" }, "op_hcompute_conv_stencil_2_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_2_write_start_control_vars_pt__U288" + "modref":"global.op_hcompute_conv_stencil_2_write_start_control_vars_pt__U265" }, "op_hcompute_conv_stencil_3":{ "modref":"global.cu_op_hcompute_conv_stencil_3" }, "op_hcompute_conv_stencil_3_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_3_exe_start_pt__U308" + "modref":"global.op_hcompute_conv_stencil_3_exe_start_pt__U285" }, "op_hcompute_conv_stencil_3_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U309" + "modref":"global.op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U286" }, "op_hcompute_conv_stencil_3_port_controller":{ - "modref":"global.affine_controller__U289" + "modref":"global.affine_controller__U266" }, "op_hcompute_conv_stencil_3_read_start":{ - "modref":"global.op_hcompute_conv_stencil_3_read_start_pt__U306" + "modref":"global.op_hcompute_conv_stencil_3_read_start_pt__U283" }, "op_hcompute_conv_stencil_3_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_3_read_start_control_vars_pt__U307" + "modref":"global.op_hcompute_conv_stencil_3_read_start_control_vars_pt__U284" }, "op_hcompute_conv_stencil_3_write_start":{ - "modref":"global.op_hcompute_conv_stencil_3_write_start_pt__U310" + "modref":"global.op_hcompute_conv_stencil_3_write_start_pt__U287" }, "op_hcompute_conv_stencil_3_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_3_write_start_control_vars_pt__U311" + "modref":"global.op_hcompute_conv_stencil_3_write_start_control_vars_pt__U288" }, "op_hcompute_conv_stencil_4":{ "modref":"global.cu_op_hcompute_conv_stencil_4" }, "op_hcompute_conv_stencil_4_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_4_exe_start_pt__U331" + "modref":"global.op_hcompute_conv_stencil_4_exe_start_pt__U308" }, "op_hcompute_conv_stencil_4_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U332" + "modref":"global.op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U309" }, "op_hcompute_conv_stencil_4_port_controller":{ - "modref":"global.affine_controller__U312" + "modref":"global.affine_controller__U289" }, "op_hcompute_conv_stencil_4_read_start":{ - "modref":"global.op_hcompute_conv_stencil_4_read_start_pt__U329" + "modref":"global.op_hcompute_conv_stencil_4_read_start_pt__U306" }, "op_hcompute_conv_stencil_4_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_4_read_start_control_vars_pt__U330" + "modref":"global.op_hcompute_conv_stencil_4_read_start_control_vars_pt__U307" }, "op_hcompute_conv_stencil_4_write_start":{ - "modref":"global.op_hcompute_conv_stencil_4_write_start_pt__U333" + "modref":"global.op_hcompute_conv_stencil_4_write_start_pt__U310" }, "op_hcompute_conv_stencil_4_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_4_write_start_control_vars_pt__U334" + "modref":"global.op_hcompute_conv_stencil_4_write_start_control_vars_pt__U311" }, "op_hcompute_conv_stencil_5":{ "modref":"global.cu_op_hcompute_conv_stencil_5" }, "op_hcompute_conv_stencil_5_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_5_exe_start_pt__U354" + "modref":"global.op_hcompute_conv_stencil_5_exe_start_pt__U331" }, "op_hcompute_conv_stencil_5_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U355" + "modref":"global.op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U332" }, "op_hcompute_conv_stencil_5_port_controller":{ - "modref":"global.affine_controller__U335" + "modref":"global.affine_controller__U312" }, "op_hcompute_conv_stencil_5_read_start":{ - "modref":"global.op_hcompute_conv_stencil_5_read_start_pt__U352" + "modref":"global.op_hcompute_conv_stencil_5_read_start_pt__U329" }, "op_hcompute_conv_stencil_5_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_5_read_start_control_vars_pt__U353" + "modref":"global.op_hcompute_conv_stencil_5_read_start_control_vars_pt__U330" }, "op_hcompute_conv_stencil_5_write_start":{ - "modref":"global.op_hcompute_conv_stencil_5_write_start_pt__U356" + "modref":"global.op_hcompute_conv_stencil_5_write_start_pt__U333" }, "op_hcompute_conv_stencil_5_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_5_write_start_control_vars_pt__U357" + "modref":"global.op_hcompute_conv_stencil_5_write_start_control_vars_pt__U334" }, "op_hcompute_conv_stencil_6":{ "modref":"global.cu_op_hcompute_conv_stencil_6" }, "op_hcompute_conv_stencil_6_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_6_exe_start_pt__U377" + "modref":"global.op_hcompute_conv_stencil_6_exe_start_pt__U354" }, "op_hcompute_conv_stencil_6_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U378" + "modref":"global.op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U355" }, "op_hcompute_conv_stencil_6_port_controller":{ - "modref":"global.affine_controller__U358" + "modref":"global.affine_controller__U335" }, "op_hcompute_conv_stencil_6_read_start":{ - "modref":"global.op_hcompute_conv_stencil_6_read_start_pt__U375" + "modref":"global.op_hcompute_conv_stencil_6_read_start_pt__U352" }, "op_hcompute_conv_stencil_6_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_6_read_start_control_vars_pt__U376" + "modref":"global.op_hcompute_conv_stencil_6_read_start_control_vars_pt__U353" }, "op_hcompute_conv_stencil_6_write_start":{ - "modref":"global.op_hcompute_conv_stencil_6_write_start_pt__U379" + "modref":"global.op_hcompute_conv_stencil_6_write_start_pt__U356" }, "op_hcompute_conv_stencil_6_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_6_write_start_control_vars_pt__U380" + "modref":"global.op_hcompute_conv_stencil_6_write_start_control_vars_pt__U357" }, "op_hcompute_conv_stencil_7":{ "modref":"global.cu_op_hcompute_conv_stencil_7" }, "op_hcompute_conv_stencil_7_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_7_exe_start_pt__U400" + "modref":"global.op_hcompute_conv_stencil_7_exe_start_pt__U377" }, "op_hcompute_conv_stencil_7_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U401" + "modref":"global.op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U378" }, "op_hcompute_conv_stencil_7_port_controller":{ - "modref":"global.affine_controller__U381" + "modref":"global.affine_controller__U358" }, "op_hcompute_conv_stencil_7_read_start":{ - "modref":"global.op_hcompute_conv_stencil_7_read_start_pt__U398" + "modref":"global.op_hcompute_conv_stencil_7_read_start_pt__U375" }, "op_hcompute_conv_stencil_7_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_7_read_start_control_vars_pt__U399" + "modref":"global.op_hcompute_conv_stencil_7_read_start_control_vars_pt__U376" }, "op_hcompute_conv_stencil_7_write_start":{ - "modref":"global.op_hcompute_conv_stencil_7_write_start_pt__U402" + "modref":"global.op_hcompute_conv_stencil_7_write_start_pt__U379" }, "op_hcompute_conv_stencil_7_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_7_write_start_control_vars_pt__U403" + "modref":"global.op_hcompute_conv_stencil_7_write_start_control_vars_pt__U380" }, "op_hcompute_conv_stencil_8":{ "modref":"global.cu_op_hcompute_conv_stencil_8" }, "op_hcompute_conv_stencil_8_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_8_exe_start_pt__U436" + "modref":"global.op_hcompute_conv_stencil_8_exe_start_pt__U413" }, "op_hcompute_conv_stencil_8_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U439" + "modref":"global.op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U416" }, "op_hcompute_conv_stencil_8_port_controller":{ - "modref":"global.affine_controller__U404" + "modref":"global.affine_controller__U381" }, "op_hcompute_conv_stencil_8_read_start":{ - "modref":"global.op_hcompute_conv_stencil_8_read_start_pt__U434" + "modref":"global.op_hcompute_conv_stencil_8_read_start_pt__U411" }, "op_hcompute_conv_stencil_8_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_8_read_start_control_vars_pt__U435" + "modref":"global.op_hcompute_conv_stencil_8_read_start_control_vars_pt__U412" }, "op_hcompute_conv_stencil_8_write_start":{ - "modref":"global.op_hcompute_conv_stencil_8_write_start_pt__U454" + "modref":"global.op_hcompute_conv_stencil_8_write_start_pt__U431" }, "op_hcompute_conv_stencil_8_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_8_write_start_control_vars_pt__U472" + "modref":"global.op_hcompute_conv_stencil_8_write_start_control_vars_pt__U449" }, "op_hcompute_conv_stencil_9":{ "modref":"global.cu_op_hcompute_conv_stencil_9" @@ -37354,25 +37354,25 @@ "modref":"global.op_hcompute_conv_stencil_9_write_start_control_vars_pt__U660" }, "op_hcompute_conv_stencil_exe_start":{ - "modref":"global.op_hcompute_conv_stencil_exe_start_pt__U239" + "modref":"global.op_hcompute_conv_stencil_exe_start_pt__U216" }, "op_hcompute_conv_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_exe_start_control_vars_pt__U240" + "modref":"global.op_hcompute_conv_stencil_exe_start_control_vars_pt__U217" }, "op_hcompute_conv_stencil_port_controller":{ - "modref":"global.affine_controller__U220" + "modref":"global.affine_controller__U197" }, "op_hcompute_conv_stencil_read_start":{ - "modref":"global.op_hcompute_conv_stencil_read_start_pt__U237" + "modref":"global.op_hcompute_conv_stencil_read_start_pt__U214" }, "op_hcompute_conv_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_read_start_control_vars_pt__U238" + "modref":"global.op_hcompute_conv_stencil_read_start_control_vars_pt__U215" }, "op_hcompute_conv_stencil_write_start":{ - "modref":"global.op_hcompute_conv_stencil_write_start_pt__U241" + "modref":"global.op_hcompute_conv_stencil_write_start_pt__U218" }, "op_hcompute_conv_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_conv_stencil_write_start_control_vars_pt__U242" + "modref":"global.op_hcompute_conv_stencil_write_start_control_vars_pt__U219" }, "op_hcompute_hw_input_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil" @@ -37381,214 +37381,214 @@ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_1" }, "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U42" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U88" }, "op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U43" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U89" }, "op_hcompute_hw_input_global_wrapper_stencil_1_port_controller":{ - "modref":"global.affine_controller__U23" + "modref":"global.affine_controller__U69" }, "op_hcompute_hw_input_global_wrapper_stencil_1_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U40" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U86" }, "op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U41" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U87" }, "op_hcompute_hw_input_global_wrapper_stencil_1_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U44" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U90" }, "op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U45" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U91" }, "op_hcompute_hw_input_global_wrapper_stencil_2":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_2" }, "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U65" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U134" }, "op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U66" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U135" }, "op_hcompute_hw_input_global_wrapper_stencil_2_port_controller":{ - "modref":"global.affine_controller__U46" + "modref":"global.affine_controller__U115" }, "op_hcompute_hw_input_global_wrapper_stencil_2_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U63" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U132" }, "op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U64" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U133" }, "op_hcompute_hw_input_global_wrapper_stencil_2_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U67" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U136" }, "op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U68" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U137" }, "op_hcompute_hw_input_global_wrapper_stencil_3":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_3" }, "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U88" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U111" }, "op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U89" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U112" }, "op_hcompute_hw_input_global_wrapper_stencil_3_port_controller":{ - "modref":"global.affine_controller__U69" + "modref":"global.affine_controller__U92" }, "op_hcompute_hw_input_global_wrapper_stencil_3_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U86" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U109" }, "op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U87" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U110" }, "op_hcompute_hw_input_global_wrapper_stencil_3_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U90" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U113" }, "op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U91" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U114" }, "op_hcompute_hw_input_global_wrapper_stencil_4":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_4" }, "op_hcompute_hw_input_global_wrapper_stencil_4_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U111" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U19" }, "op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U112" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U20" }, "op_hcompute_hw_input_global_wrapper_stencil_4_port_controller":{ - "modref":"global.affine_controller__U92" + "modref":"global.affine_controller__U0" }, "op_hcompute_hw_input_global_wrapper_stencil_4_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U109" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U17" }, "op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U110" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U18" }, "op_hcompute_hw_input_global_wrapper_stencil_4_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U113" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U21" }, "op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U114" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U22" }, "op_hcompute_hw_input_global_wrapper_stencil_5":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_5" }, "op_hcompute_hw_input_global_wrapper_stencil_5_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U134" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U42" }, "op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U135" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U43" }, "op_hcompute_hw_input_global_wrapper_stencil_5_port_controller":{ - "modref":"global.affine_controller__U115" + "modref":"global.affine_controller__U23" }, "op_hcompute_hw_input_global_wrapper_stencil_5_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U132" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U40" }, "op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U133" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U41" }, "op_hcompute_hw_input_global_wrapper_stencil_5_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U136" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U44" }, "op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U137" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U45" }, "op_hcompute_hw_input_global_wrapper_stencil_6":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_6" }, "op_hcompute_hw_input_global_wrapper_stencil_6_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U157" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U65" }, "op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U158" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U66" }, "op_hcompute_hw_input_global_wrapper_stencil_6_port_controller":{ - "modref":"global.affine_controller__U138" + "modref":"global.affine_controller__U46" }, "op_hcompute_hw_input_global_wrapper_stencil_6_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U155" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U63" }, "op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U156" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U64" }, "op_hcompute_hw_input_global_wrapper_stencil_6_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U159" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U67" }, "op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U160" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U68" }, "op_hcompute_hw_input_global_wrapper_stencil_7":{ "modref":"global.cu_op_hcompute_hw_input_global_wrapper_stencil_7" }, "op_hcompute_hw_input_global_wrapper_stencil_7_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U180" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U588" }, "op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U181" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U589" }, "op_hcompute_hw_input_global_wrapper_stencil_7_port_controller":{ - "modref":"global.affine_controller__U161" + "modref":"global.affine_controller__U569" }, "op_hcompute_hw_input_global_wrapper_stencil_7_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U178" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U586" }, "op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U179" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U587" }, "op_hcompute_hw_input_global_wrapper_stencil_7_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U182" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U590" }, "op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U183" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U591" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U19" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U157" }, "op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U20" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U158" }, "op_hcompute_hw_input_global_wrapper_stencil_port_controller":{ - "modref":"global.affine_controller__U0" + "modref":"global.affine_controller__U138" }, "op_hcompute_hw_input_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U17" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U155" }, "op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U18" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U156" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U21" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U159" }, "op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U22" + "modref":"global.op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U160" }, "op_hcompute_hw_kernel_global_wrapper_stencil":{ "modref":"global.cu_op_hcompute_hw_kernel_global_wrapper_stencil" }, "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U216" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U193" }, "op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U217" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U194" }, "op_hcompute_hw_kernel_global_wrapper_stencil_port_controller":{ - "modref":"global.affine_controller__U184" + "modref":"global.affine_controller__U161" }, "op_hcompute_hw_kernel_global_wrapper_stencil_read_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U214" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U191" }, "op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U215" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U192" }, "op_hcompute_hw_kernel_global_wrapper_stencil_write_start":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U218" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U195" }, "op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars":{ - "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U219" + "modref":"global.op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U196" }, "op_hcompute_hw_output_stencil":{ "modref":"global.cu_op_hcompute_hw_output_stencil" @@ -38064,46 +38064,46 @@ ["arr__U2279.in","arr__U2274.out"], ["self.clk","arr__U2279.clk"], ["op_hcompute_hw_output_stencil_7_write_start_control_vars.in","arr__U2279.out"], - ["self.clk","arr__U440.clk"], - ["op_hcompute_conv_stencil_8_port_controller.d","arr__U440.in"], - ["arr__U447.in","arr__U440.out"], - ["self.clk","arr__U447.clk"], - ["op_hcompute_conv_stencil_8_exe_start_control_vars.in","arr__U447.out"], - ["self.clk","arr__U473.clk"], - ["op_hcompute_conv_stencil_8_port_controller.d","arr__U473.in"], - ["arr__U480.in","arr__U473.out"], - ["self.clk","arr__U480.clk"], - ["arr__U487.in","arr__U480.out"], - ["self.clk","arr__U487.clk"], - ["arr__U494.in","arr__U487.out"], - ["self.clk","arr__U494.clk"], - ["arr__U501.in","arr__U494.out"], - ["self.clk","arr__U501.clk"], - ["arr__U508.in","arr__U501.out"], - ["self.clk","arr__U508.clk"], - ["arr__U515.in","arr__U508.out"], - ["self.clk","arr__U515.clk"], - ["arr__U522.in","arr__U515.out"], - ["self.clk","arr__U522.clk"], - ["arr__U529.in","arr__U522.out"], - ["self.clk","arr__U529.clk"], - ["arr__U536.in","arr__U529.out"], - ["self.clk","arr__U536.clk"], - ["arr__U543.in","arr__U536.out"], - ["self.clk","arr__U543.clk"], - ["arr__U550.in","arr__U543.out"], - ["self.clk","arr__U550.clk"], - ["arr__U557.in","arr__U550.out"], - ["self.clk","arr__U557.clk"], - ["arr__U564.in","arr__U557.out"], - ["self.clk","arr__U564.clk"], - ["arr__U571.in","arr__U564.out"], - ["self.clk","arr__U571.clk"], - ["arr__U578.in","arr__U571.out"], - ["self.clk","arr__U578.clk"], - ["arr__U585.in","arr__U578.out"], - ["self.clk","arr__U585.clk"], - ["op_hcompute_conv_stencil_8_write_start_control_vars.in","arr__U585.out"], + ["self.clk","arr__U417.clk"], + ["op_hcompute_conv_stencil_8_port_controller.d","arr__U417.in"], + ["arr__U424.in","arr__U417.out"], + ["self.clk","arr__U424.clk"], + ["op_hcompute_conv_stencil_8_exe_start_control_vars.in","arr__U424.out"], + ["self.clk","arr__U450.clk"], + ["op_hcompute_conv_stencil_8_port_controller.d","arr__U450.in"], + ["arr__U457.in","arr__U450.out"], + ["self.clk","arr__U457.clk"], + ["arr__U464.in","arr__U457.out"], + ["self.clk","arr__U464.clk"], + ["arr__U471.in","arr__U464.out"], + ["self.clk","arr__U471.clk"], + ["arr__U478.in","arr__U471.out"], + ["self.clk","arr__U478.clk"], + ["arr__U485.in","arr__U478.out"], + ["self.clk","arr__U485.clk"], + ["arr__U492.in","arr__U485.out"], + ["self.clk","arr__U492.clk"], + ["arr__U499.in","arr__U492.out"], + ["self.clk","arr__U499.clk"], + ["arr__U506.in","arr__U499.out"], + ["self.clk","arr__U506.clk"], + ["arr__U513.in","arr__U506.out"], + ["self.clk","arr__U513.clk"], + ["arr__U520.in","arr__U513.out"], + ["self.clk","arr__U520.clk"], + ["arr__U527.in","arr__U520.out"], + ["self.clk","arr__U527.clk"], + ["arr__U534.in","arr__U527.out"], + ["self.clk","arr__U534.clk"], + ["arr__U541.in","arr__U534.out"], + ["self.clk","arr__U541.clk"], + ["arr__U548.in","arr__U541.out"], + ["self.clk","arr__U548.clk"], + ["arr__U555.in","arr__U548.out"], + ["self.clk","arr__U555.clk"], + ["arr__U562.in","arr__U555.out"], + ["self.clk","arr__U562.clk"], + ["op_hcompute_conv_stencil_8_write_start_control_vars.in","arr__U562.out"], ["self.clk","arr__U628.clk"], ["op_hcompute_conv_stencil_9_port_controller.d","arr__U628.in"], ["arr__U635.in","arr__U628.out"], @@ -38563,46 +38563,46 @@ ["delay_reg__U2272.in","delay_reg__U2271.out"], ["self.clk","delay_reg__U2272.clk"], ["op_hcompute_hw_output_stencil_7_write_start.in","delay_reg__U2272.out"], + ["self.clk","delay_reg__U414.clk"], + ["op_hcompute_conv_stencil_8_port_controller.valid","delay_reg__U414.in"], + ["delay_reg__U415.in","delay_reg__U414.out"], + ["self.clk","delay_reg__U415.clk"], + ["op_hcompute_conv_stencil_8_exe_start.in","delay_reg__U415.out"], + ["self.clk","delay_reg__U432.clk"], + ["op_hcompute_conv_stencil_8_port_controller.valid","delay_reg__U432.in"], + ["delay_reg__U433.in","delay_reg__U432.out"], + ["self.clk","delay_reg__U433.clk"], + ["delay_reg__U434.in","delay_reg__U433.out"], + ["self.clk","delay_reg__U434.clk"], + ["delay_reg__U435.in","delay_reg__U434.out"], + ["self.clk","delay_reg__U435.clk"], + ["delay_reg__U436.in","delay_reg__U435.out"], + ["self.clk","delay_reg__U436.clk"], + ["delay_reg__U437.in","delay_reg__U436.out"], ["self.clk","delay_reg__U437.clk"], - ["op_hcompute_conv_stencil_8_port_controller.valid","delay_reg__U437.in"], ["delay_reg__U438.in","delay_reg__U437.out"], ["self.clk","delay_reg__U438.clk"], - ["op_hcompute_conv_stencil_8_exe_start.in","delay_reg__U438.out"], - ["self.clk","delay_reg__U455.clk"], - ["op_hcompute_conv_stencil_8_port_controller.valid","delay_reg__U455.in"], - ["delay_reg__U456.in","delay_reg__U455.out"], - ["self.clk","delay_reg__U456.clk"], - ["delay_reg__U457.in","delay_reg__U456.out"], - ["self.clk","delay_reg__U457.clk"], - ["delay_reg__U458.in","delay_reg__U457.out"], - ["self.clk","delay_reg__U458.clk"], - ["delay_reg__U459.in","delay_reg__U458.out"], - ["self.clk","delay_reg__U459.clk"], - ["delay_reg__U460.in","delay_reg__U459.out"], - ["self.clk","delay_reg__U460.clk"], - ["delay_reg__U461.in","delay_reg__U460.out"], - ["self.clk","delay_reg__U461.clk"], - ["delay_reg__U462.in","delay_reg__U461.out"], - ["self.clk","delay_reg__U462.clk"], - ["delay_reg__U463.in","delay_reg__U462.out"], - ["self.clk","delay_reg__U463.clk"], - ["delay_reg__U464.in","delay_reg__U463.out"], - ["self.clk","delay_reg__U464.clk"], - ["delay_reg__U465.in","delay_reg__U464.out"], - ["self.clk","delay_reg__U465.clk"], - ["delay_reg__U466.in","delay_reg__U465.out"], - ["self.clk","delay_reg__U466.clk"], - ["delay_reg__U467.in","delay_reg__U466.out"], - ["self.clk","delay_reg__U467.clk"], - ["delay_reg__U468.in","delay_reg__U467.out"], - ["self.clk","delay_reg__U468.clk"], - ["delay_reg__U469.in","delay_reg__U468.out"], - ["self.clk","delay_reg__U469.clk"], - ["delay_reg__U470.in","delay_reg__U469.out"], - ["self.clk","delay_reg__U470.clk"], - ["delay_reg__U471.in","delay_reg__U470.out"], - ["self.clk","delay_reg__U471.clk"], - ["op_hcompute_conv_stencil_8_write_start.in","delay_reg__U471.out"], + ["delay_reg__U439.in","delay_reg__U438.out"], + ["self.clk","delay_reg__U439.clk"], + ["delay_reg__U440.in","delay_reg__U439.out"], + ["self.clk","delay_reg__U440.clk"], + ["delay_reg__U441.in","delay_reg__U440.out"], + ["self.clk","delay_reg__U441.clk"], + ["delay_reg__U442.in","delay_reg__U441.out"], + ["self.clk","delay_reg__U442.clk"], + ["delay_reg__U443.in","delay_reg__U442.out"], + ["self.clk","delay_reg__U443.clk"], + ["delay_reg__U444.in","delay_reg__U443.out"], + ["self.clk","delay_reg__U444.clk"], + ["delay_reg__U445.in","delay_reg__U444.out"], + ["self.clk","delay_reg__U445.clk"], + ["delay_reg__U446.in","delay_reg__U445.out"], + ["self.clk","delay_reg__U446.clk"], + ["delay_reg__U447.in","delay_reg__U446.out"], + ["self.clk","delay_reg__U447.clk"], + ["delay_reg__U448.in","delay_reg__U447.out"], + ["self.clk","delay_reg__U448.clk"], + ["op_hcompute_conv_stencil_8_write_start.in","delay_reg__U448.out"], ["self.clk","delay_reg__U625.clk"], ["op_hcompute_conv_stencil_9_port_controller.valid","delay_reg__U625.in"], ["delay_reg__U626.in","delay_reg__U625.out"], @@ -38861,9 +38861,9 @@ ["op_hcompute_conv_stencil_read_start.in","op_hcompute_conv_stencil_port_controller.valid"], ["op_hcompute_conv_stencil_write_start.in","op_hcompute_conv_stencil_port_controller.valid"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil.clk"], - ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read","op_hcompute_hw_input_global_wrapper_stencil.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read","op_hcompute_hw_input_global_wrapper_stencil.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1.clk"], - ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read","op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read"], + ["self.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read","op_hcompute_hw_input_global_wrapper_stencil_1.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read"], ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.valid","op_hcompute_hw_input_global_wrapper_stencil_1_exe_start.in"], ["op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.d","op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.clk"], @@ -38871,9 +38871,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.d"], ["op_hcompute_hw_input_global_wrapper_stencil_1_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.valid"], ["op_hcompute_hw_input_global_wrapper_stencil_1_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_1_port_controller.valid"], - ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","op_hcompute_hw_input_global_wrapper_stencil_1_read_start.out"], + ["self.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en","op_hcompute_hw_input_global_wrapper_stencil_1_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2.clk"], - ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read","op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read","op_hcompute_hw_input_global_wrapper_stencil_2.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read"], ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.valid","op_hcompute_hw_input_global_wrapper_stencil_2_exe_start.in"], ["op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.d","op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.clk"], @@ -38881,9 +38881,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.d"], ["op_hcompute_hw_input_global_wrapper_stencil_2_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.valid"], ["op_hcompute_hw_input_global_wrapper_stencil_2_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_2_port_controller.valid"], - ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","op_hcompute_hw_input_global_wrapper_stencil_2_read_start.out"], + ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en","op_hcompute_hw_input_global_wrapper_stencil_2_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_3.clk"], - ["self.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read","op_hcompute_hw_input_global_wrapper_stencil_3.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read","op_hcompute_hw_input_global_wrapper_stencil_3.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read"], ["op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.valid","op_hcompute_hw_input_global_wrapper_stencil_3_exe_start.in"], ["op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.d","op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.clk"], @@ -38891,9 +38891,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars.in","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.d"], ["op_hcompute_hw_input_global_wrapper_stencil_3_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.valid"], ["op_hcompute_hw_input_global_wrapper_stencil_3_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_3_port_controller.valid"], - ["self.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","op_hcompute_hw_input_global_wrapper_stencil_3_read_start.out"], + ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en","op_hcompute_hw_input_global_wrapper_stencil_3_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_4.clk"], - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read","op_hcompute_hw_input_global_wrapper_stencil_4.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read","op_hcompute_hw_input_global_wrapper_stencil_4.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read"], ["op_hcompute_hw_input_global_wrapper_stencil_4_port_controller.valid","op_hcompute_hw_input_global_wrapper_stencil_4_exe_start.in"], ["op_hcompute_hw_input_global_wrapper_stencil_4_port_controller.d","op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_4_port_controller.clk"], @@ -38901,9 +38901,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars.in","op_hcompute_hw_input_global_wrapper_stencil_4_port_controller.d"], ["op_hcompute_hw_input_global_wrapper_stencil_4_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_4_port_controller.valid"], ["op_hcompute_hw_input_global_wrapper_stencil_4_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_4_port_controller.valid"], - ["self.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en","op_hcompute_hw_input_global_wrapper_stencil_4_read_start.out"], + ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en","op_hcompute_hw_input_global_wrapper_stencil_4_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_5.clk"], - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read","op_hcompute_hw_input_global_wrapper_stencil_5.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read","op_hcompute_hw_input_global_wrapper_stencil_5.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read"], ["op_hcompute_hw_input_global_wrapper_stencil_5_port_controller.valid","op_hcompute_hw_input_global_wrapper_stencil_5_exe_start.in"], ["op_hcompute_hw_input_global_wrapper_stencil_5_port_controller.d","op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_5_port_controller.clk"], @@ -38911,9 +38911,9 @@ ["op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars.in","op_hcompute_hw_input_global_wrapper_stencil_5_port_controller.d"], ["op_hcompute_hw_input_global_wrapper_stencil_5_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_5_port_controller.valid"], ["op_hcompute_hw_input_global_wrapper_stencil_5_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_5_port_controller.valid"], - ["self.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en","op_hcompute_hw_input_global_wrapper_stencil_5_read_start.out"], + ["self.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en","op_hcompute_hw_input_global_wrapper_stencil_5_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_6.clk"], - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read","op_hcompute_hw_input_global_wrapper_stencil_6.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read","op_hcompute_hw_input_global_wrapper_stencil_6.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read"], ["op_hcompute_hw_input_global_wrapper_stencil_6_port_controller.valid","op_hcompute_hw_input_global_wrapper_stencil_6_exe_start.in"], ["op_hcompute_hw_input_global_wrapper_stencil_6_port_controller.d","op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars.in"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_6_port_controller.clk"], @@ -38921,7 +38921,7 @@ ["op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars.in","op_hcompute_hw_input_global_wrapper_stencil_6_port_controller.d"], ["op_hcompute_hw_input_global_wrapper_stencil_6_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_6_port_controller.valid"], ["op_hcompute_hw_input_global_wrapper_stencil_6_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_6_port_controller.valid"], - ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en","op_hcompute_hw_input_global_wrapper_stencil_6_read_start.out"], + ["self.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en","op_hcompute_hw_input_global_wrapper_stencil_6_read_start.out"], ["self.clk","op_hcompute_hw_input_global_wrapper_stencil_7.clk"], ["self.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read","op_hcompute_hw_input_global_wrapper_stencil_7.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read"], ["op_hcompute_hw_input_global_wrapper_stencil_7_port_controller.valid","op_hcompute_hw_input_global_wrapper_stencil_7_exe_start.in"], @@ -38939,7 +38939,7 @@ ["op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.d"], ["op_hcompute_hw_input_global_wrapper_stencil_read_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.valid"], ["op_hcompute_hw_input_global_wrapper_stencil_write_start.in","op_hcompute_hw_input_global_wrapper_stencil_port_controller.valid"], - ["self.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], + ["self.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en","op_hcompute_hw_input_global_wrapper_stencil_read_start.out"], ["self.clk","op_hcompute_hw_kernel_global_wrapper_stencil.clk"], ["self.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read","op_hcompute_hw_kernel_global_wrapper_stencil.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read"], ["op_hcompute_hw_kernel_global_wrapper_stencil_port_controller.valid","op_hcompute_hw_kernel_global_wrapper_stencil_exe_start.in"], diff --git a/coreir_apps/platonic_buffer/resnet88/resnet88.v b/coreir_apps/platonic_buffer/resnet88/resnet88.v index f0c0187e1..c9b860f3d 100644 --- a/coreir_apps/platonic_buffer/resnet88/resnet88.v +++ b/coreir_apps/platonic_buffer/resnet88/resnet88.v @@ -385,14 +385,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U218 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U195 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U219 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U196 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -403,14 +403,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U214 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U191 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U215 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U192 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -421,14 +421,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U216 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U193 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U217 ( +module op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U194 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -439,14 +439,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U21 ( +module op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U159 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U22 ( +module op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U160 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -455,14 +455,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U17 ( +module op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U155 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U18 ( +module op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U156 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -471,14 +471,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U19 ( +module op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U157 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U20 ( +module op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U158 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -487,14 +487,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U182 ( +module op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U590 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U183 ( +module op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U591 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -503,14 +503,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U178 ( +module op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U586 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U179 ( +module op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U587 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -519,14 +519,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U180 ( +module op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U588 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U181 ( +module op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U589 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -535,14 +535,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U159 ( +module op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U67 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U160 ( +module op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U68 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -551,14 +551,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U155 ( +module op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U63 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U156 ( +module op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U64 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -567,14 +567,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U157 ( +module op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U65 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U158 ( +module op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U66 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -583,14 +583,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U136 ( +module op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U44 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U137 ( +module op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U45 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -599,14 +599,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U132 ( +module op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U40 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U133 ( +module op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U41 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -615,14 +615,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U134 ( +module op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U42 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U135 ( +module op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U43 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -631,14 +631,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U113 ( +module op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U21 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U114 ( +module op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U22 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -647,14 +647,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U109 ( +module op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U17 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U110 ( +module op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U18 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -663,14 +663,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U111 ( +module op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U19 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U112 ( +module op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U20 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -679,14 +679,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U90 ( +module op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U113 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U91 ( +module op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U114 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -695,14 +695,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U86 ( +module op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U109 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U87 ( +module op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U110 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -711,14 +711,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U88 ( +module op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U111 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U89 ( +module op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U112 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -727,14 +727,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U67 ( +module op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U136 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U68 ( +module op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U137 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -743,14 +743,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U63 ( +module op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U132 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U64 ( +module op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U133 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -759,14 +759,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U65 ( +module op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U134 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U66 ( +module op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U135 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -775,14 +775,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U44 ( +module op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U90 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U45 ( +module op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U91 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -791,14 +791,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U40 ( +module op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U86 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U41 ( +module op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U87 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -807,14 +807,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U42 ( +module op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U88 ( input in, output out ); assign out = in; endmodule -module op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U43 ( +module op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U89 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -823,14 +823,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_write_start_pt__U241 ( +module op_hcompute_conv_stencil_write_start_pt__U218 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_write_start_control_vars_pt__U242 ( +module op_hcompute_conv_stencil_write_start_control_vars_pt__U219 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -839,14 +839,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_read_start_pt__U237 ( +module op_hcompute_conv_stencil_read_start_pt__U214 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_read_start_control_vars_pt__U238 ( +module op_hcompute_conv_stencil_read_start_control_vars_pt__U215 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -855,14 +855,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_exe_start_pt__U239 ( +module op_hcompute_conv_stencil_exe_start_pt__U216 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_exe_start_control_vars_pt__U240 ( +module op_hcompute_conv_stencil_exe_start_control_vars_pt__U217 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -925,14 +925,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_8_write_start_pt__U454 ( +module op_hcompute_conv_stencil_8_write_start_pt__U431 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_8_write_start_control_vars_pt__U472 ( +module op_hcompute_conv_stencil_8_write_start_control_vars_pt__U449 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -943,14 +943,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_8_read_start_pt__U434 ( +module op_hcompute_conv_stencil_8_read_start_pt__U411 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_8_read_start_control_vars_pt__U435 ( +module op_hcompute_conv_stencil_8_read_start_control_vars_pt__U412 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -961,14 +961,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_8_exe_start_pt__U436 ( +module op_hcompute_conv_stencil_8_exe_start_pt__U413 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U439 ( +module op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U416 ( input [15:0] in [4:0], output [15:0] out [4:0] ); @@ -979,14 +979,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_7_write_start_pt__U402 ( +module op_hcompute_conv_stencil_7_write_start_pt__U379 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_7_write_start_control_vars_pt__U403 ( +module op_hcompute_conv_stencil_7_write_start_control_vars_pt__U380 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -995,14 +995,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_7_read_start_pt__U398 ( +module op_hcompute_conv_stencil_7_read_start_pt__U375 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_7_read_start_control_vars_pt__U399 ( +module op_hcompute_conv_stencil_7_read_start_control_vars_pt__U376 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1011,14 +1011,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_7_exe_start_pt__U400 ( +module op_hcompute_conv_stencil_7_exe_start_pt__U377 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U401 ( +module op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U378 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1027,14 +1027,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_6_write_start_pt__U379 ( +module op_hcompute_conv_stencil_6_write_start_pt__U356 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_6_write_start_control_vars_pt__U380 ( +module op_hcompute_conv_stencil_6_write_start_control_vars_pt__U357 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1043,14 +1043,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_6_read_start_pt__U375 ( +module op_hcompute_conv_stencil_6_read_start_pt__U352 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_6_read_start_control_vars_pt__U376 ( +module op_hcompute_conv_stencil_6_read_start_control_vars_pt__U353 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1059,14 +1059,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_6_exe_start_pt__U377 ( +module op_hcompute_conv_stencil_6_exe_start_pt__U354 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U378 ( +module op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U355 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1075,14 +1075,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_5_write_start_pt__U356 ( +module op_hcompute_conv_stencil_5_write_start_pt__U333 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_5_write_start_control_vars_pt__U357 ( +module op_hcompute_conv_stencil_5_write_start_control_vars_pt__U334 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1091,14 +1091,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_5_read_start_pt__U352 ( +module op_hcompute_conv_stencil_5_read_start_pt__U329 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_5_read_start_control_vars_pt__U353 ( +module op_hcompute_conv_stencil_5_read_start_control_vars_pt__U330 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1107,14 +1107,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_5_exe_start_pt__U354 ( +module op_hcompute_conv_stencil_5_exe_start_pt__U331 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U355 ( +module op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U332 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1123,14 +1123,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_4_write_start_pt__U333 ( +module op_hcompute_conv_stencil_4_write_start_pt__U310 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_4_write_start_control_vars_pt__U334 ( +module op_hcompute_conv_stencil_4_write_start_control_vars_pt__U311 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1139,14 +1139,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_4_read_start_pt__U329 ( +module op_hcompute_conv_stencil_4_read_start_pt__U306 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_4_read_start_control_vars_pt__U330 ( +module op_hcompute_conv_stencil_4_read_start_control_vars_pt__U307 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1155,14 +1155,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_4_exe_start_pt__U331 ( +module op_hcompute_conv_stencil_4_exe_start_pt__U308 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U332 ( +module op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U309 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1171,14 +1171,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_3_write_start_pt__U310 ( +module op_hcompute_conv_stencil_3_write_start_pt__U287 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_3_write_start_control_vars_pt__U311 ( +module op_hcompute_conv_stencil_3_write_start_control_vars_pt__U288 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1187,14 +1187,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_3_read_start_pt__U306 ( +module op_hcompute_conv_stencil_3_read_start_pt__U283 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_3_read_start_control_vars_pt__U307 ( +module op_hcompute_conv_stencil_3_read_start_control_vars_pt__U284 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1203,14 +1203,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_3_exe_start_pt__U308 ( +module op_hcompute_conv_stencil_3_exe_start_pt__U285 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U309 ( +module op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U286 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1219,14 +1219,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_2_write_start_pt__U287 ( +module op_hcompute_conv_stencil_2_write_start_pt__U264 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_2_write_start_control_vars_pt__U288 ( +module op_hcompute_conv_stencil_2_write_start_control_vars_pt__U265 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1235,14 +1235,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_2_read_start_pt__U283 ( +module op_hcompute_conv_stencil_2_read_start_pt__U260 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_2_read_start_control_vars_pt__U284 ( +module op_hcompute_conv_stencil_2_read_start_control_vars_pt__U261 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1251,14 +1251,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_2_exe_start_pt__U285 ( +module op_hcompute_conv_stencil_2_exe_start_pt__U262 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U286 ( +module op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U263 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1267,14 +1267,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_1_write_start_pt__U264 ( +module op_hcompute_conv_stencil_1_write_start_pt__U241 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_1_write_start_control_vars_pt__U265 ( +module op_hcompute_conv_stencil_1_write_start_control_vars_pt__U242 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1283,14 +1283,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_1_read_start_pt__U260 ( +module op_hcompute_conv_stencil_1_read_start_pt__U237 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_1_read_start_control_vars_pt__U261 ( +module op_hcompute_conv_stencil_1_read_start_control_vars_pt__U238 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -1299,14 +1299,14 @@ assign out[1] = in[1]; assign out[0] = in[0]; endmodule -module op_hcompute_conv_stencil_1_exe_start_pt__U262 ( +module op_hcompute_conv_stencil_1_exe_start_pt__U239 ( input in, output out ); assign out = in; endmodule -module op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U263 ( +module op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U240 ( input [15:0] in [2:0], output [15:0] out [2:0] ); @@ -3687,992 +3687,992 @@ assign out[1] = _U631_out; assign out[0] = _U630_out; endmodule -module array_delay_U586 ( +module array_delay_U563 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U587_out; -wire [15:0] _U588_out; -wire [15:0] _U589_out; -wire [15:0] _U590_out; -wire [15:0] _U591_out; +wire [15:0] _U564_out; +wire [15:0] _U565_out; +wire [15:0] _U566_out; +wire [15:0] _U567_out; +wire [15:0] _U568_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U587 ( +) _U564 ( .in(in[0]), .clk(clk), - .out(_U587_out) + .out(_U564_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U588 ( +) _U565 ( .in(in[1]), .clk(clk), - .out(_U588_out) + .out(_U565_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U589 ( +) _U566 ( .in(in[2]), .clk(clk), - .out(_U589_out) + .out(_U566_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U590 ( +) _U567 ( .in(in[3]), .clk(clk), - .out(_U590_out) + .out(_U567_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U591 ( +) _U568 ( .in(in[4]), .clk(clk), - .out(_U591_out) + .out(_U568_out) ); -assign out[4] = _U591_out; -assign out[3] = _U590_out; -assign out[2] = _U589_out; -assign out[1] = _U588_out; -assign out[0] = _U587_out; +assign out[4] = _U568_out; +assign out[3] = _U567_out; +assign out[2] = _U566_out; +assign out[1] = _U565_out; +assign out[0] = _U564_out; endmodule -module array_delay_U579 ( +module array_delay_U556 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U580_out; -wire [15:0] _U581_out; -wire [15:0] _U582_out; -wire [15:0] _U583_out; -wire [15:0] _U584_out; +wire [15:0] _U557_out; +wire [15:0] _U558_out; +wire [15:0] _U559_out; +wire [15:0] _U560_out; +wire [15:0] _U561_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U580 ( +) _U557 ( .in(in[0]), .clk(clk), - .out(_U580_out) + .out(_U557_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U581 ( +) _U558 ( .in(in[1]), .clk(clk), - .out(_U581_out) + .out(_U558_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U582 ( +) _U559 ( .in(in[2]), .clk(clk), - .out(_U582_out) + .out(_U559_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U583 ( +) _U560 ( .in(in[3]), .clk(clk), - .out(_U583_out) + .out(_U560_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U584 ( +) _U561 ( .in(in[4]), .clk(clk), - .out(_U584_out) + .out(_U561_out) ); -assign out[4] = _U584_out; -assign out[3] = _U583_out; -assign out[2] = _U582_out; -assign out[1] = _U581_out; -assign out[0] = _U580_out; +assign out[4] = _U561_out; +assign out[3] = _U560_out; +assign out[2] = _U559_out; +assign out[1] = _U558_out; +assign out[0] = _U557_out; endmodule -module array_delay_U572 ( +module array_delay_U549 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U573_out; -wire [15:0] _U574_out; -wire [15:0] _U575_out; -wire [15:0] _U576_out; -wire [15:0] _U577_out; +wire [15:0] _U550_out; +wire [15:0] _U551_out; +wire [15:0] _U552_out; +wire [15:0] _U553_out; +wire [15:0] _U554_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U573 ( +) _U550 ( .in(in[0]), .clk(clk), - .out(_U573_out) + .out(_U550_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U574 ( +) _U551 ( .in(in[1]), .clk(clk), - .out(_U574_out) + .out(_U551_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U575 ( +) _U552 ( .in(in[2]), .clk(clk), - .out(_U575_out) + .out(_U552_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U576 ( +) _U553 ( .in(in[3]), .clk(clk), - .out(_U576_out) + .out(_U553_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U577 ( +) _U554 ( .in(in[4]), .clk(clk), - .out(_U577_out) + .out(_U554_out) ); -assign out[4] = _U577_out; -assign out[3] = _U576_out; -assign out[2] = _U575_out; -assign out[1] = _U574_out; -assign out[0] = _U573_out; +assign out[4] = _U554_out; +assign out[3] = _U553_out; +assign out[2] = _U552_out; +assign out[1] = _U551_out; +assign out[0] = _U550_out; endmodule -module array_delay_U565 ( +module array_delay_U542 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U566_out; -wire [15:0] _U567_out; -wire [15:0] _U568_out; -wire [15:0] _U569_out; -wire [15:0] _U570_out; +wire [15:0] _U543_out; +wire [15:0] _U544_out; +wire [15:0] _U545_out; +wire [15:0] _U546_out; +wire [15:0] _U547_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U566 ( +) _U543 ( .in(in[0]), .clk(clk), - .out(_U566_out) + .out(_U543_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U567 ( +) _U544 ( .in(in[1]), .clk(clk), - .out(_U567_out) + .out(_U544_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U568 ( +) _U545 ( .in(in[2]), .clk(clk), - .out(_U568_out) + .out(_U545_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U569 ( +) _U546 ( .in(in[3]), .clk(clk), - .out(_U569_out) + .out(_U546_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U570 ( +) _U547 ( .in(in[4]), .clk(clk), - .out(_U570_out) + .out(_U547_out) ); -assign out[4] = _U570_out; -assign out[3] = _U569_out; -assign out[2] = _U568_out; -assign out[1] = _U567_out; -assign out[0] = _U566_out; +assign out[4] = _U547_out; +assign out[3] = _U546_out; +assign out[2] = _U545_out; +assign out[1] = _U544_out; +assign out[0] = _U543_out; endmodule -module array_delay_U558 ( +module array_delay_U535 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U559_out; -wire [15:0] _U560_out; -wire [15:0] _U561_out; -wire [15:0] _U562_out; -wire [15:0] _U563_out; +wire [15:0] _U536_out; +wire [15:0] _U537_out; +wire [15:0] _U538_out; +wire [15:0] _U539_out; +wire [15:0] _U540_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U559 ( +) _U536 ( .in(in[0]), .clk(clk), - .out(_U559_out) + .out(_U536_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U560 ( +) _U537 ( .in(in[1]), .clk(clk), - .out(_U560_out) + .out(_U537_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U561 ( +) _U538 ( .in(in[2]), .clk(clk), - .out(_U561_out) + .out(_U538_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U562 ( +) _U539 ( .in(in[3]), .clk(clk), - .out(_U562_out) + .out(_U539_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U563 ( +) _U540 ( .in(in[4]), .clk(clk), - .out(_U563_out) + .out(_U540_out) ); -assign out[4] = _U563_out; -assign out[3] = _U562_out; -assign out[2] = _U561_out; -assign out[1] = _U560_out; -assign out[0] = _U559_out; +assign out[4] = _U540_out; +assign out[3] = _U539_out; +assign out[2] = _U538_out; +assign out[1] = _U537_out; +assign out[0] = _U536_out; endmodule -module array_delay_U551 ( +module array_delay_U528 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U552_out; -wire [15:0] _U553_out; -wire [15:0] _U554_out; -wire [15:0] _U555_out; -wire [15:0] _U556_out; +wire [15:0] _U529_out; +wire [15:0] _U530_out; +wire [15:0] _U531_out; +wire [15:0] _U532_out; +wire [15:0] _U533_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U552 ( +) _U529 ( .in(in[0]), .clk(clk), - .out(_U552_out) + .out(_U529_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U553 ( +) _U530 ( .in(in[1]), .clk(clk), - .out(_U553_out) + .out(_U530_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U554 ( +) _U531 ( .in(in[2]), .clk(clk), - .out(_U554_out) + .out(_U531_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U555 ( +) _U532 ( .in(in[3]), .clk(clk), - .out(_U555_out) + .out(_U532_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U556 ( +) _U533 ( .in(in[4]), .clk(clk), - .out(_U556_out) + .out(_U533_out) ); -assign out[4] = _U556_out; -assign out[3] = _U555_out; -assign out[2] = _U554_out; -assign out[1] = _U553_out; -assign out[0] = _U552_out; +assign out[4] = _U533_out; +assign out[3] = _U532_out; +assign out[2] = _U531_out; +assign out[1] = _U530_out; +assign out[0] = _U529_out; endmodule -module array_delay_U544 ( +module array_delay_U521 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U545_out; -wire [15:0] _U546_out; -wire [15:0] _U547_out; -wire [15:0] _U548_out; -wire [15:0] _U549_out; +wire [15:0] _U522_out; +wire [15:0] _U523_out; +wire [15:0] _U524_out; +wire [15:0] _U525_out; +wire [15:0] _U526_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U545 ( +) _U522 ( .in(in[0]), .clk(clk), - .out(_U545_out) + .out(_U522_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U546 ( +) _U523 ( .in(in[1]), .clk(clk), - .out(_U546_out) + .out(_U523_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U547 ( +) _U524 ( .in(in[2]), .clk(clk), - .out(_U547_out) + .out(_U524_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U548 ( +) _U525 ( .in(in[3]), .clk(clk), - .out(_U548_out) + .out(_U525_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U549 ( +) _U526 ( .in(in[4]), .clk(clk), - .out(_U549_out) + .out(_U526_out) ); -assign out[4] = _U549_out; -assign out[3] = _U548_out; -assign out[2] = _U547_out; -assign out[1] = _U546_out; -assign out[0] = _U545_out; +assign out[4] = _U526_out; +assign out[3] = _U525_out; +assign out[2] = _U524_out; +assign out[1] = _U523_out; +assign out[0] = _U522_out; endmodule -module array_delay_U537 ( +module array_delay_U514 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U538_out; -wire [15:0] _U539_out; -wire [15:0] _U540_out; -wire [15:0] _U541_out; -wire [15:0] _U542_out; +wire [15:0] _U515_out; +wire [15:0] _U516_out; +wire [15:0] _U517_out; +wire [15:0] _U518_out; +wire [15:0] _U519_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U538 ( +) _U515 ( .in(in[0]), .clk(clk), - .out(_U538_out) + .out(_U515_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U539 ( +) _U516 ( .in(in[1]), .clk(clk), - .out(_U539_out) + .out(_U516_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U540 ( +) _U517 ( .in(in[2]), .clk(clk), - .out(_U540_out) + .out(_U517_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U541 ( +) _U518 ( .in(in[3]), .clk(clk), - .out(_U541_out) + .out(_U518_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U542 ( +) _U519 ( .in(in[4]), .clk(clk), - .out(_U542_out) + .out(_U519_out) ); -assign out[4] = _U542_out; -assign out[3] = _U541_out; -assign out[2] = _U540_out; -assign out[1] = _U539_out; -assign out[0] = _U538_out; +assign out[4] = _U519_out; +assign out[3] = _U518_out; +assign out[2] = _U517_out; +assign out[1] = _U516_out; +assign out[0] = _U515_out; endmodule -module array_delay_U530 ( +module array_delay_U507 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U531_out; -wire [15:0] _U532_out; -wire [15:0] _U533_out; -wire [15:0] _U534_out; -wire [15:0] _U535_out; +wire [15:0] _U508_out; +wire [15:0] _U509_out; +wire [15:0] _U510_out; +wire [15:0] _U511_out; +wire [15:0] _U512_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U531 ( +) _U508 ( .in(in[0]), .clk(clk), - .out(_U531_out) + .out(_U508_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U532 ( +) _U509 ( .in(in[1]), .clk(clk), - .out(_U532_out) + .out(_U509_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U533 ( +) _U510 ( .in(in[2]), .clk(clk), - .out(_U533_out) + .out(_U510_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U534 ( +) _U511 ( .in(in[3]), .clk(clk), - .out(_U534_out) + .out(_U511_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U535 ( +) _U512 ( .in(in[4]), .clk(clk), - .out(_U535_out) + .out(_U512_out) ); -assign out[4] = _U535_out; -assign out[3] = _U534_out; -assign out[2] = _U533_out; -assign out[1] = _U532_out; -assign out[0] = _U531_out; +assign out[4] = _U512_out; +assign out[3] = _U511_out; +assign out[2] = _U510_out; +assign out[1] = _U509_out; +assign out[0] = _U508_out; endmodule -module array_delay_U523 ( +module array_delay_U500 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U524_out; -wire [15:0] _U525_out; -wire [15:0] _U526_out; -wire [15:0] _U527_out; -wire [15:0] _U528_out; +wire [15:0] _U501_out; +wire [15:0] _U502_out; +wire [15:0] _U503_out; +wire [15:0] _U504_out; +wire [15:0] _U505_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U524 ( +) _U501 ( .in(in[0]), .clk(clk), - .out(_U524_out) + .out(_U501_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U525 ( +) _U502 ( .in(in[1]), .clk(clk), - .out(_U525_out) + .out(_U502_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U526 ( +) _U503 ( .in(in[2]), .clk(clk), - .out(_U526_out) + .out(_U503_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U527 ( +) _U504 ( .in(in[3]), .clk(clk), - .out(_U527_out) + .out(_U504_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U528 ( +) _U505 ( .in(in[4]), .clk(clk), - .out(_U528_out) + .out(_U505_out) ); -assign out[4] = _U528_out; -assign out[3] = _U527_out; -assign out[2] = _U526_out; -assign out[1] = _U525_out; -assign out[0] = _U524_out; +assign out[4] = _U505_out; +assign out[3] = _U504_out; +assign out[2] = _U503_out; +assign out[1] = _U502_out; +assign out[0] = _U501_out; endmodule -module array_delay_U516 ( +module array_delay_U493 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U517_out; -wire [15:0] _U518_out; -wire [15:0] _U519_out; -wire [15:0] _U520_out; -wire [15:0] _U521_out; +wire [15:0] _U494_out; +wire [15:0] _U495_out; +wire [15:0] _U496_out; +wire [15:0] _U497_out; +wire [15:0] _U498_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U517 ( +) _U494 ( .in(in[0]), .clk(clk), - .out(_U517_out) + .out(_U494_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U518 ( +) _U495 ( .in(in[1]), .clk(clk), - .out(_U518_out) + .out(_U495_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U519 ( +) _U496 ( .in(in[2]), .clk(clk), - .out(_U519_out) + .out(_U496_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U520 ( +) _U497 ( .in(in[3]), .clk(clk), - .out(_U520_out) + .out(_U497_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U521 ( +) _U498 ( .in(in[4]), .clk(clk), - .out(_U521_out) + .out(_U498_out) ); -assign out[4] = _U521_out; -assign out[3] = _U520_out; -assign out[2] = _U519_out; -assign out[1] = _U518_out; -assign out[0] = _U517_out; +assign out[4] = _U498_out; +assign out[3] = _U497_out; +assign out[2] = _U496_out; +assign out[1] = _U495_out; +assign out[0] = _U494_out; endmodule -module array_delay_U509 ( +module array_delay_U486 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U510_out; -wire [15:0] _U511_out; -wire [15:0] _U512_out; -wire [15:0] _U513_out; -wire [15:0] _U514_out; +wire [15:0] _U487_out; +wire [15:0] _U488_out; +wire [15:0] _U489_out; +wire [15:0] _U490_out; +wire [15:0] _U491_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U510 ( +) _U487 ( .in(in[0]), .clk(clk), - .out(_U510_out) + .out(_U487_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U511 ( +) _U488 ( .in(in[1]), .clk(clk), - .out(_U511_out) + .out(_U488_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U512 ( +) _U489 ( .in(in[2]), .clk(clk), - .out(_U512_out) + .out(_U489_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U513 ( +) _U490 ( .in(in[3]), .clk(clk), - .out(_U513_out) + .out(_U490_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U514 ( +) _U491 ( .in(in[4]), .clk(clk), - .out(_U514_out) + .out(_U491_out) ); -assign out[4] = _U514_out; -assign out[3] = _U513_out; -assign out[2] = _U512_out; -assign out[1] = _U511_out; -assign out[0] = _U510_out; +assign out[4] = _U491_out; +assign out[3] = _U490_out; +assign out[2] = _U489_out; +assign out[1] = _U488_out; +assign out[0] = _U487_out; endmodule -module array_delay_U502 ( +module array_delay_U479 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U503_out; -wire [15:0] _U504_out; -wire [15:0] _U505_out; -wire [15:0] _U506_out; -wire [15:0] _U507_out; +wire [15:0] _U480_out; +wire [15:0] _U481_out; +wire [15:0] _U482_out; +wire [15:0] _U483_out; +wire [15:0] _U484_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U503 ( +) _U480 ( .in(in[0]), .clk(clk), - .out(_U503_out) + .out(_U480_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U504 ( +) _U481 ( .in(in[1]), .clk(clk), - .out(_U504_out) + .out(_U481_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U505 ( +) _U482 ( .in(in[2]), .clk(clk), - .out(_U505_out) + .out(_U482_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U506 ( +) _U483 ( .in(in[3]), .clk(clk), - .out(_U506_out) + .out(_U483_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U507 ( +) _U484 ( .in(in[4]), .clk(clk), - .out(_U507_out) + .out(_U484_out) ); -assign out[4] = _U507_out; -assign out[3] = _U506_out; -assign out[2] = _U505_out; -assign out[1] = _U504_out; -assign out[0] = _U503_out; +assign out[4] = _U484_out; +assign out[3] = _U483_out; +assign out[2] = _U482_out; +assign out[1] = _U481_out; +assign out[0] = _U480_out; endmodule -module array_delay_U495 ( +module array_delay_U472 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U496_out; -wire [15:0] _U497_out; -wire [15:0] _U498_out; -wire [15:0] _U499_out; -wire [15:0] _U500_out; +wire [15:0] _U473_out; +wire [15:0] _U474_out; +wire [15:0] _U475_out; +wire [15:0] _U476_out; +wire [15:0] _U477_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U496 ( +) _U473 ( .in(in[0]), .clk(clk), - .out(_U496_out) + .out(_U473_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U497 ( +) _U474 ( .in(in[1]), .clk(clk), - .out(_U497_out) + .out(_U474_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U498 ( +) _U475 ( .in(in[2]), .clk(clk), - .out(_U498_out) + .out(_U475_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U499 ( +) _U476 ( .in(in[3]), .clk(clk), - .out(_U499_out) + .out(_U476_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U500 ( +) _U477 ( .in(in[4]), .clk(clk), - .out(_U500_out) + .out(_U477_out) ); -assign out[4] = _U500_out; -assign out[3] = _U499_out; -assign out[2] = _U498_out; -assign out[1] = _U497_out; -assign out[0] = _U496_out; +assign out[4] = _U477_out; +assign out[3] = _U476_out; +assign out[2] = _U475_out; +assign out[1] = _U474_out; +assign out[0] = _U473_out; endmodule -module array_delay_U488 ( +module array_delay_U465 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U489_out; -wire [15:0] _U490_out; -wire [15:0] _U491_out; -wire [15:0] _U492_out; -wire [15:0] _U493_out; +wire [15:0] _U466_out; +wire [15:0] _U467_out; +wire [15:0] _U468_out; +wire [15:0] _U469_out; +wire [15:0] _U470_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U489 ( +) _U466 ( .in(in[0]), .clk(clk), - .out(_U489_out) + .out(_U466_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U490 ( +) _U467 ( .in(in[1]), .clk(clk), - .out(_U490_out) + .out(_U467_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U491 ( +) _U468 ( .in(in[2]), .clk(clk), - .out(_U491_out) + .out(_U468_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U492 ( +) _U469 ( .in(in[3]), .clk(clk), - .out(_U492_out) + .out(_U469_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U493 ( +) _U470 ( .in(in[4]), .clk(clk), - .out(_U493_out) + .out(_U470_out) ); -assign out[4] = _U493_out; -assign out[3] = _U492_out; -assign out[2] = _U491_out; -assign out[1] = _U490_out; -assign out[0] = _U489_out; +assign out[4] = _U470_out; +assign out[3] = _U469_out; +assign out[2] = _U468_out; +assign out[1] = _U467_out; +assign out[0] = _U466_out; endmodule -module array_delay_U481 ( +module array_delay_U458 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U482_out; -wire [15:0] _U483_out; -wire [15:0] _U484_out; -wire [15:0] _U485_out; -wire [15:0] _U486_out; +wire [15:0] _U459_out; +wire [15:0] _U460_out; +wire [15:0] _U461_out; +wire [15:0] _U462_out; +wire [15:0] _U463_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U482 ( +) _U459 ( .in(in[0]), .clk(clk), - .out(_U482_out) + .out(_U459_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U483 ( +) _U460 ( .in(in[1]), .clk(clk), - .out(_U483_out) + .out(_U460_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U484 ( +) _U461 ( .in(in[2]), .clk(clk), - .out(_U484_out) + .out(_U461_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U485 ( +) _U462 ( .in(in[3]), .clk(clk), - .out(_U485_out) + .out(_U462_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U486 ( +) _U463 ( .in(in[4]), .clk(clk), - .out(_U486_out) + .out(_U463_out) ); -assign out[4] = _U486_out; -assign out[3] = _U485_out; -assign out[2] = _U484_out; -assign out[1] = _U483_out; -assign out[0] = _U482_out; +assign out[4] = _U463_out; +assign out[3] = _U462_out; +assign out[2] = _U461_out; +assign out[1] = _U460_out; +assign out[0] = _U459_out; endmodule -module array_delay_U474 ( +module array_delay_U451 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U475_out; -wire [15:0] _U476_out; -wire [15:0] _U477_out; -wire [15:0] _U478_out; -wire [15:0] _U479_out; +wire [15:0] _U452_out; +wire [15:0] _U453_out; +wire [15:0] _U454_out; +wire [15:0] _U455_out; +wire [15:0] _U456_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U475 ( +) _U452 ( .in(in[0]), .clk(clk), - .out(_U475_out) + .out(_U452_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U476 ( +) _U453 ( .in(in[1]), .clk(clk), - .out(_U476_out) + .out(_U453_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U477 ( +) _U454 ( .in(in[2]), .clk(clk), - .out(_U477_out) + .out(_U454_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U478 ( +) _U455 ( .in(in[3]), .clk(clk), - .out(_U478_out) + .out(_U455_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U479 ( +) _U456 ( .in(in[4]), .clk(clk), - .out(_U479_out) + .out(_U456_out) ); -assign out[4] = _U479_out; -assign out[3] = _U478_out; -assign out[2] = _U477_out; -assign out[1] = _U476_out; -assign out[0] = _U475_out; +assign out[4] = _U456_out; +assign out[3] = _U455_out; +assign out[2] = _U454_out; +assign out[1] = _U453_out; +assign out[0] = _U452_out; endmodule -module array_delay_U448 ( +module array_delay_U425 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U449_out; -wire [15:0] _U450_out; -wire [15:0] _U451_out; -wire [15:0] _U452_out; -wire [15:0] _U453_out; +wire [15:0] _U426_out; +wire [15:0] _U427_out; +wire [15:0] _U428_out; +wire [15:0] _U429_out; +wire [15:0] _U430_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U449 ( +) _U426 ( .in(in[0]), .clk(clk), - .out(_U449_out) + .out(_U426_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U450 ( +) _U427 ( .in(in[1]), .clk(clk), - .out(_U450_out) + .out(_U427_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U451 ( +) _U428 ( .in(in[2]), .clk(clk), - .out(_U451_out) + .out(_U428_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U452 ( +) _U429 ( .in(in[3]), .clk(clk), - .out(_U452_out) + .out(_U429_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U453 ( +) _U430 ( .in(in[4]), .clk(clk), - .out(_U453_out) + .out(_U430_out) ); -assign out[4] = _U453_out; -assign out[3] = _U452_out; -assign out[2] = _U451_out; -assign out[1] = _U450_out; -assign out[0] = _U449_out; +assign out[4] = _U430_out; +assign out[3] = _U429_out; +assign out[2] = _U428_out; +assign out[1] = _U427_out; +assign out[0] = _U426_out; endmodule -module array_delay_U441 ( +module array_delay_U418 ( input clk, input [15:0] in [4:0], output [15:0] out [4:0] ); -wire [15:0] _U442_out; -wire [15:0] _U443_out; -wire [15:0] _U444_out; -wire [15:0] _U445_out; -wire [15:0] _U446_out; +wire [15:0] _U419_out; +wire [15:0] _U420_out; +wire [15:0] _U421_out; +wire [15:0] _U422_out; +wire [15:0] _U423_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U442 ( +) _U419 ( .in(in[0]), .clk(clk), - .out(_U442_out) + .out(_U419_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U443 ( +) _U420 ( .in(in[1]), .clk(clk), - .out(_U443_out) + .out(_U420_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U444 ( +) _U421 ( .in(in[2]), .clk(clk), - .out(_U444_out) + .out(_U421_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U445 ( +) _U422 ( .in(in[3]), .clk(clk), - .out(_U445_out) + .out(_U422_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U446 ( +) _U423 ( .in(in[4]), .clk(clk), - .out(_U446_out) + .out(_U423_out) ); -assign out[4] = _U446_out; -assign out[3] = _U445_out; -assign out[2] = _U444_out; -assign out[1] = _U443_out; -assign out[0] = _U442_out; +assign out[4] = _U423_out; +assign out[3] = _U422_out; +assign out[2] = _U421_out; +assign out[1] = _U420_out; +assign out[0] = _U419_out; endmodule module array_delay_U2280 ( @@ -11173,14 +11173,14 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U47 ( +module aff__U570 ( output [15:0] out, input [15:0] d [2:0] ); assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001f * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0001); endmodule -module affine_controller__U46 ( +module affine_controller__U569 ( input clk, output valid, output [15:0] d [2:0] @@ -11201,7 +11201,7 @@ wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U47 affine_func ( +aff__U570 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -11249,17 +11249,17 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U405 ( +module aff__U47 ( output [15:0] out, - input [15:0] d [4:0] + input [15:0] d [2:0] ); -assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0f18 * d[1])))) + (16'(16'h0508 * d[2])))) + (16'(16'h002e * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h03ea); +assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001f * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0001); endmodule -module affine_controller__U404 ( +module affine_controller__U46 ( input clk, output valid, - output [15:0] d [4:0] + output [15:0] d [2:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -11272,20 +11272,12 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; -wire d_3_at_max_out; -wire [15:0] d_3_next_value_out; -wire [15:0] d_3_reg_out; -wire d_4_at_max_out; -wire [15:0] d_4_next_value_out; -wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [4:0]; -assign affine_func_d[4] = d_4_reg_out; -assign affine_func_d[3] = d_3_reg_out; +wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U405 affine_func ( +aff__U47 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -11297,7 +11289,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -11306,8 +11298,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h0002; -assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h001d; +assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -11316,8 +11308,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h0002; -assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h001d; +assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -11326,30 +11318,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); -assign d_3_at_max_out = d_3_reg_out == 16'h001b; -assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_3_reg ( - .in(d_3_next_value_out), - .clk(clk), - .out(d_3_reg_out), - .en(cmp_time_out) -); -assign d_4_at_max_out = d_4_reg_out == 16'h001b; -assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_4_reg ( - .in(d_4_next_value_out), - .clk(clk), - .out(d_4_reg_out), - .en(cmp_time_out) -); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; -assign d[4] = d_4_reg_out; -assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; @@ -11357,15 +11327,15 @@ endmodule module aff__U382 ( output [15:0] out, - input [15:0] d [2:0] + input [15:0] d [4:0] ); -assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001d * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0002); +assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h0f18 * d[1])))) + (16'(16'h0508 * d[2])))) + (16'(16'h002e * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h03ea); endmodule module affine_controller__U381 ( input clk, output valid, - output [15:0] d [2:0] + output [15:0] d [4:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -11378,8 +11348,16 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; +wire d_3_at_max_out; +wire [15:0] d_3_next_value_out; +wire [15:0] d_3_reg_out; +wire d_4_at_max_out; +wire [15:0] d_4_next_value_out; +wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [2:0]; +wire [15:0] affine_func_d [4:0]; +assign affine_func_d[4] = d_4_reg_out; +assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; @@ -11395,7 +11373,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -11404,8 +11382,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h001b; -assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h0002; +assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -11414,8 +11392,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h001b; -assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h0002; +assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -11424,8 +11402,30 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); +assign d_3_at_max_out = d_3_reg_out == 16'h001b; +assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_3_reg ( + .in(d_3_next_value_out), + .clk(clk), + .out(d_3_reg_out), + .en(cmp_time_out) +); +assign d_4_at_max_out = d_4_reg_out == 16'h001b; +assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_4_reg ( + .in(d_4_next_value_out), + .clk(clk), + .out(d_4_reg_out), + .en(cmp_time_out) +); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; +assign d[4] = d_4_reg_out; +assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; @@ -12495,14 +12495,14 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U1956 ( +module aff__U198 ( output [15:0] out, input [15:0] d [2:0] ); -assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001d * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h3e91); +assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001d * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0002); endmodule -module affine_controller__U1955 ( +module affine_controller__U197 ( input clk, output valid, output [15:0] d [2:0] @@ -12523,7 +12523,7 @@ wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U1956 affine_func ( +aff__U198 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -12571,14 +12571,14 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U1909 ( +module aff__U1956 ( output [15:0] out, input [15:0] d [2:0] ); assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001d * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h3e91); endmodule -module affine_controller__U1908 ( +module affine_controller__U1955 ( input clk, output valid, output [15:0] d [2:0] @@ -12599,7 +12599,7 @@ wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U1909 affine_func ( +aff__U1956 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -12647,17 +12647,17 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module aff__U185 ( +module aff__U1909 ( output [15:0] out, - input [15:0] d [4:0] + input [15:0] d [2:0] ); -assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h00d8 * d[1])))) + (16'(16'h0048 * d[2])))) + (16'(16'h0009 * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h0002); +assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001d * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h3e91); endmodule -module affine_controller__U184 ( +module affine_controller__U1908 ( input clk, output valid, - output [15:0] d [4:0] + output [15:0] d [2:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -12670,20 +12670,12 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; -wire d_3_at_max_out; -wire [15:0] d_3_next_value_out; -wire [15:0] d_3_reg_out; -wire d_4_at_max_out; -wire [15:0] d_4_next_value_out; -wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [4:0]; -assign affine_func_d[4] = d_4_reg_out; -assign affine_func_d[3] = d_3_reg_out; +wire [15:0] affine_func_d [2:0]; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; -aff__U185 affine_func ( +aff__U1909 affine_func ( .out(affine_func_out), .d(affine_func_d) ); @@ -12695,7 +12687,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -12704,8 +12696,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h0002; -assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h001b; +assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -12714,8 +12706,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h0002; -assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h001b; +assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -12724,30 +12716,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); -assign d_3_at_max_out = d_3_reg_out == 16'h0007; -assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_3_reg ( - .in(d_3_next_value_out), - .clk(clk), - .out(d_3_reg_out), - .en(cmp_time_out) -); -assign d_4_at_max_out = d_4_reg_out == 16'h0007; -assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; -mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( - .init(16'h0000) -) d_4_reg ( - .in(d_4_next_value_out), - .clk(clk), - .out(d_4_reg_out), - .en(cmp_time_out) -); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; -assign d[4] = d_4_reg_out; -assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; @@ -12861,15 +12831,15 @@ endmodule module aff__U162 ( output [15:0] out, - input [15:0] d [2:0] + input [15:0] d [4:0] ); -assign out = 16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h001f * d[1])))) + (16'(16'h0001 * d[2])))) + 16'h0001); +assign out = 16'((16'((16'((16'((16'((16'(16'h0000 * d[0])) + (16'(16'h00d8 * d[1])))) + (16'(16'h0048 * d[2])))) + (16'(16'h0009 * d[3])))) + (16'(16'h0001 * d[4])))) + 16'h0002); endmodule module affine_controller__U161 ( input clk, output valid, - output [15:0] d [2:0] + output [15:0] d [4:0] ); wire [15:0] affine_func_out; wire cmp_time_out; @@ -12882,8 +12852,16 @@ wire [15:0] d_1_reg_out; wire d_2_at_max_out; wire [15:0] d_2_next_value_out; wire [15:0] d_2_reg_out; +wire d_3_at_max_out; +wire [15:0] d_3_next_value_out; +wire [15:0] d_3_reg_out; +wire d_4_at_max_out; +wire [15:0] d_4_next_value_out; +wire [15:0] d_4_reg_out; wire [15:0] inc_time_out; -wire [15:0] affine_func_d [2:0]; +wire [15:0] affine_func_d [4:0]; +assign affine_func_d[4] = d_4_reg_out; +assign affine_func_d[3] = d_3_reg_out; assign affine_func_d[2] = d_2_reg_out; assign affine_func_d[1] = d_1_reg_out; assign affine_func_d[0] = d_0_reg_out; @@ -12899,7 +12877,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(cycle_time_out) ); -assign d_0_next_value_out = (1'b1 & d_1_at_max_out) & d_2_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; +assign d_0_next_value_out = (((1'b1 & d_1_at_max_out) & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_0_reg_out == 16'h0000 ? 16'h0000 : 16'(d_0_reg_out + 16'h0001) : d_0_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_0_reg ( @@ -12908,8 +12886,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_0_reg_out), .en(cmp_time_out) ); -assign d_1_at_max_out = d_1_reg_out == 16'h001d; -assign d_1_next_value_out = 1'b1 & d_2_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; +assign d_1_at_max_out = d_1_reg_out == 16'h0002; +assign d_1_next_value_out = ((1'b1 & d_2_at_max_out) & d_3_at_max_out) & d_4_at_max_out ? d_1_at_max_out ? 16'h0000 : 16'(d_1_reg_out + 16'h0001) : d_1_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_1_reg ( @@ -12918,8 +12896,8 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_1_reg_out), .en(cmp_time_out) ); -assign d_2_at_max_out = d_2_reg_out == 16'h001d; -assign d_2_next_value_out = 1'b1 ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; +assign d_2_at_max_out = d_2_reg_out == 16'h0002; +assign d_2_next_value_out = (1'b1 & d_3_at_max_out) & d_4_at_max_out ? d_2_at_max_out ? 16'h0000 : 16'(d_2_reg_out + 16'h0001) : d_2_reg_out; mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .init(16'h0000) ) d_2_reg ( @@ -12928,8 +12906,30 @@ mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( .out(d_2_reg_out), .en(cmp_time_out) ); +assign d_3_at_max_out = d_3_reg_out == 16'h0007; +assign d_3_next_value_out = 1'b1 & d_4_at_max_out ? d_3_at_max_out ? 16'h0000 : 16'(d_3_reg_out + 16'h0001) : d_3_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_3_reg ( + .in(d_3_next_value_out), + .clk(clk), + .out(d_3_reg_out), + .en(cmp_time_out) +); +assign d_4_at_max_out = d_4_reg_out == 16'h0007; +assign d_4_next_value_out = 1'b1 ? d_4_at_max_out ? 16'h0000 : 16'(d_4_reg_out + 16'h0001) : d_4_reg_out; +mantle_reg__has_clrFalse__has_enTrue__has_rstFalse__width16 #( + .init(16'h0000) +) d_4_reg ( + .in(d_4_next_value_out), + .clk(clk), + .out(d_4_reg_out), + .en(cmp_time_out) +); assign inc_time_out = 16'(cycle_time_out + 16'h0001); assign valid = cmp_time_out; +assign d[4] = d_4_reg_out; +assign d[3] = d_3_reg_out; assign d[2] = d_2_reg_out; assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; @@ -13481,105 +13481,112 @@ assign d[1] = d_1_reg_out; assign d[0] = d_0_reg_out; endmodule -module _U99_pt__U100 ( +module _U997_pt__U998 ( + input [15:0] in, + output [15:0] out +); +assign out = in; +endmodule + +module _U992_pt__U993 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U997_pt__U998 ( +module _U990_pt__U991 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U989_pt__U990 ( +module _U988_pt__U989 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U980_pt__U981 ( +module _U981_pt__U982 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U970_pt__U971 ( +module _U974_pt__U975 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U967_pt__U968 ( +module _U971_pt__U972 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U961_pt__U962 ( +module _U968_pt__U969 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U954_pt__U955 ( +module _U95_pt__U96 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U941_pt__U942 ( +module _U959_pt__U960 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U939_pt__U940 ( +module _U956_pt__U957 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U936_pt__U937 ( +module _U948_pt__U949 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U923_pt__U924 ( +module _U942_pt__U943 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U916_pt__U917 ( +module _U939_pt__U940 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U910_pt__U911 ( +module _U931_pt__U932 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U90_pt__U91 ( +module _U923_pt__U924 ( input [15:0] in, output [15:0] out ); @@ -13593,6 +13600,13 @@ module _U907_pt__U908 ( assign out = in; endmodule +module _U901_pt__U902 ( + input [15:0] in, + output [15:0] out +); +assign out = in; +endmodule + module _U8_pt__U9 ( input [15:0] in, output [15:0] out @@ -13600,7 +13614,7 @@ module _U8_pt__U9 ( assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_4_pipelined ( +module hcompute_hw_input_global_wrapper_stencil_3_pipelined ( output [15:0] out_hw_input_global_wrapper_stencil, input [15:0] in0_hw_input_stencil [0:0] ); @@ -13610,43 +13624,43 @@ _U8_pt__U9 _U8 ( ); endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil_4 ( +module cu_op_hcompute_hw_input_global_wrapper_stencil_3 ( input clk, - input [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write [0:0] + input [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write [0:0] ); wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read[0]; -hcompute_hw_input_global_wrapper_stencil_4_pipelined inner_compute ( +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read[0]; +hcompute_hw_input_global_wrapper_stencil_3_pipelined inner_compute ( .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) ); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; endmodule -module _U899_pt__U900 ( +module _U889_pt__U890 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U893_pt__U894 ( +module _U885_pt__U886 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U890_pt__U891 ( +module _U87_pt__U88 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U879_pt__U880 ( +module _U876_pt__U877 ( input [15:0] in, output [15:0] out ); @@ -13667,6 +13681,13 @@ module _U870_pt__U871 ( assign out = in; endmodule +module _U868_pt__U869 ( + input [15:0] in, + output [15:0] out +); +assign out = in; +endmodule + module _U854_pt__U855 ( input [15:0] in, output [15:0] out @@ -13716,42 +13737,42 @@ module _U831_pt__U832 ( assign out = in; endmodule -module _U82_pt__U83 ( +module _U825_pt__U826 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U825_pt__U826 ( +module _U822_pt__U823 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U822_pt__U823 ( +module _U814_pt__U815 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U814_pt__U815 ( +module _U811_pt__U812 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U811_pt__U812 ( +module _U801_pt__U802 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U801_pt__U802 ( +module _U79_pt__U80 ( input [15:0] in, output [15:0] out ); @@ -13807,130 +13828,130 @@ module _U761_pt__U762 ( assign out = in; endmodule -module _U74_pt__U75 ( +module _U744_pt__U745 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U744_pt__U745 ( +module _U740_pt__U741 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U740_pt__U741 ( +module _U735_pt__U736 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U735_pt__U736 ( +module _U72_pt__U73 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U732_pt__U733 ( +module _U726_pt__U727 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U726_pt__U727 ( +module _U723_pt__U724 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U721_pt__U722 ( +module _U715_pt__U716 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U705_pt__U706 ( +module _U709_pt__U710 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U6_pt__U7 ( +module _U707_pt__U708 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_3_pipelined ( - output [15:0] out_hw_input_global_wrapper_stencil, - input [15:0] in0_hw_input_stencil [0:0] -); -_U6_pt__U7 _U6 ( - .in(in0_hw_input_stencil[0]), - .out(out_hw_input_global_wrapper_stencil) +module _U701_pt__U702 ( + input [15:0] in, + output [15:0] out ); +assign out = in; endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil_3 ( - input clk, - input [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write [0:0] -); -wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; -wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read[0]; -hcompute_hw_input_global_wrapper_stencil_3_pipelined inner_compute ( - .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), - .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) -); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; -endmodule - -module _U697_pt__U698 ( +module _U6_pt__U7 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U688_pt__U689 ( - input [15:0] in, - output [15:0] out +module hcompute_hw_input_global_wrapper_stencil_1_pipelined ( + output [15:0] out_hw_input_global_wrapper_stencil, + input [15:0] in0_hw_input_stencil [0:0] ); -assign out = in; +_U6_pt__U7 _U6 ( + .in(in0_hw_input_stencil[0]), + .out(out_hw_input_global_wrapper_stencil) +); +endmodule + +module cu_op_hcompute_hw_input_global_wrapper_stencil_1 ( + input clk, + input [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write [0:0] +); +wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; +wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read[0]; +hcompute_hw_input_global_wrapper_stencil_1_pipelined inner_compute ( + .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), + .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) +); +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; endmodule -module _U686_pt__U687 ( +module _U685_pt__U686 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U682_pt__U683 ( +module _U683_pt__U684 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U67_pt__U68 ( +module _U678_pt__U679 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U674_pt__U675 ( +module _U670_pt__U671 ( input [15:0] in, output [15:0] out ); @@ -13944,28 +13965,28 @@ module _U667_pt__U668 ( assign out = in; endmodule -module _U664_pt__U665 ( +module _U663_pt__U664 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U661_pt__U662 ( +module _U660_pt__U661 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U659_pt__U660 ( +module _U65_pt__U66 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U650_pt__U651 ( +module _U651_pt__U652 ( input [15:0] in, output [15:0] out ); @@ -14005,7 +14026,7 @@ wire [15:0] _U647_out; wire [15:0] _U648_out; wire [15:0] _U649_out; wire [15:0] _U650_out; -wire [15:0] _U652_out; +wire [15:0] _U651_out; wire [15:0] _U653_out; wire [15:0] _U654_out; wire [15:0] _U655_out; @@ -14013,28 +14034,29 @@ wire [15:0] _U656_out; wire [15:0] _U657_out; wire [15:0] _U658_out; wire [15:0] _U659_out; -wire [15:0] _U661_out; +wire [15:0] _U660_out; +wire [15:0] _U662_out; wire [15:0] _U663_out; -wire [15:0] _U664_out; +wire [15:0] _U665_out; wire [15:0] _U666_out; wire [15:0] _U667_out; wire [15:0] _U669_out; wire [15:0] _U670_out; -wire [15:0] _U671_out; wire [15:0] _U672_out; wire [15:0] _U673_out; wire [15:0] _U674_out; +wire [15:0] _U675_out; wire [15:0] _U676_out; wire [15:0] _U677_out; wire [15:0] _U678_out; -wire [15:0] _U679_out; wire [15:0] _U680_out; wire [15:0] _U681_out; wire [15:0] _U682_out; -wire [15:0] _U684_out; +wire [15:0] _U683_out; wire [15:0] _U685_out; -wire [15:0] _U686_out; +wire [15:0] _U687_out; wire [15:0] _U688_out; +wire [15:0] _U689_out; wire [15:0] _U690_out; wire [15:0] _U691_out; wire [15:0] _U692_out; @@ -14043,30 +14065,28 @@ wire [15:0] _U694_out; wire [15:0] _U695_out; wire [15:0] _U696_out; wire [15:0] _U697_out; +wire [15:0] _U698_out; wire [15:0] _U699_out; wire [15:0] _U700_out; wire [15:0] _U701_out; -wire [15:0] _U702_out; wire [15:0] _U703_out; wire [15:0] _U704_out; wire [15:0] _U705_out; +wire [15:0] _U706_out; wire [15:0] _U707_out; -wire [15:0] _U708_out; wire [15:0] _U709_out; -wire [15:0] _U710_out; wire [15:0] _U711_out; wire [15:0] _U712_out; wire [15:0] _U713_out; wire [15:0] _U714_out; wire [15:0] _U715_out; -wire [15:0] _U716_out; wire [15:0] _U717_out; wire [15:0] _U718_out; wire [15:0] _U719_out; wire [15:0] _U720_out; wire [15:0] _U721_out; +wire [15:0] _U722_out; wire [15:0] _U723_out; -wire [15:0] _U724_out; wire [15:0] _U725_out; wire [15:0] _U726_out; wire [15:0] _U728_out; @@ -14074,6 +14094,7 @@ wire [15:0] _U729_out; wire [15:0] _U730_out; wire [15:0] _U731_out; wire [15:0] _U732_out; +wire [15:0] _U733_out; wire [15:0] _U734_out; wire [15:0] _U735_out; wire [15:0] _U737_out; @@ -14183,7 +14204,7 @@ _U637_pt__U638 _U637 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U639 ( - .in(in2_hw_kernel_global_wrapper_stencil[5]), + .in(in1_hw_input_global_wrapper_stencil[5]), .clk(clk), .out(_U639_out) ); @@ -14216,13 +14237,13 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U643_out) ); _U644_pt__U645 _U644 ( - .in(_U649_out), + .in(_U650_out), .out(_U644_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U646 ( - .in(in2_hw_kernel_global_wrapper_stencil[4]), + .in(in2_hw_kernel_global_wrapper_stencil[5]), .clk(clk), .out(_U646_out) ); @@ -14247,21 +14268,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U649_out) ); -_U650_pt__U651 _U650 ( - .in(_U658_out), - .out(_U650_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U652 ( - .in(in2_hw_kernel_global_wrapper_stencil[7]), +) _U650 ( + .in(_U649_out), .clk(clk), - .out(_U652_out) + .out(_U650_out) +); +_U651_pt__U652 _U651 ( + .in(_U659_out), + .out(_U651_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U653 ( - .in(_U652_out), + .in(in1_hw_input_global_wrapper_stencil[7]), .clk(clk), .out(_U653_out) ); @@ -14300,61 +14321,61 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U658_out) ); -_U659_pt__U660 _U659 ( - .in(in1_hw_input_global_wrapper_stencil[0]), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U659 ( + .in(_U658_out), + .clk(clk), .out(_U659_out) ); -_U661_pt__U662 _U661 ( - .in(_U663_out), - .out(_U661_out) +_U660_pt__U661 _U660 ( + .in(_U662_out), + .out(_U660_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U663 ( - .in(in1_hw_input_global_wrapper_stencil[1]), +) _U662 ( + .in(in2_hw_kernel_global_wrapper_stencil[1]), .clk(clk), - .out(_U663_out) + .out(_U662_out) ); -_U664_pt__U665 _U664 ( +_U663_pt__U664 _U663 ( .in(_U666_out), - .out(_U664_out) + .out(_U663_out) +); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U665 ( + .in(in2_hw_kernel_global_wrapper_stencil[2]), + .clk(clk), + .out(_U665_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U666 ( - .in(mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926_out), + .in(_U665_out), .clk(clk), .out(_U666_out) ); _U667_pt__U668 _U667 ( - .in(_U673_out), + .in(_U669_out), .out(_U667_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U669 ( - .in(in1_hw_input_global_wrapper_stencil[5]), + .in(mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926_out), .clk(clk), .out(_U669_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U670 ( - .in(_U669_out), - .clk(clk), +_U670_pt__U671 _U670 ( + .in(_U677_out), .out(_U670_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U671 ( - .in(_U670_out), - .clk(clk), - .out(_U671_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U672 ( - .in(_U671_out), + .in(in1_hw_input_global_wrapper_stencil[6]), .clk(clk), .out(_U672_out) ); @@ -14365,14 +14386,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U673_out) ); -_U674_pt__U675 _U674 ( - .in(_U681_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U674 ( + .in(_U673_out), + .clk(clk), .out(_U674_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U675 ( + .in(_U674_out), + .clk(clk), + .out(_U675_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U676 ( - .in(in2_hw_kernel_global_wrapper_stencil[6]), + .in(_U675_out), .clk(clk), .out(_U676_out) ); @@ -14383,24 +14414,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U677_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U678 ( - .in(_U677_out), - .clk(clk), +_U678_pt__U679 _U678 ( + .in(_U682_out), .out(_U678_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U679 ( - .in(_U678_out), - .clk(clk), - .out(_U679_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U680 ( - .in(_U679_out), + .in(in2_hw_kernel_global_wrapper_stencil[3]), .clk(clk), .out(_U680_out) ); @@ -14411,36 +14432,46 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U681_out) ); -_U682_pt__U683 _U682 ( - .in(_U685_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U682 ( + .in(_U681_out), + .clk(clk), .out(_U682_out) ); +_U683_pt__U684 _U683 ( + .in(in2_hw_kernel_global_wrapper_stencil[0]), + .out(_U683_out) +); +_U685_pt__U686 _U685 ( + .in(_U700_out), + .out(_U685_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U684 ( - .in(in1_hw_input_global_wrapper_stencil[2]), +) _U687 ( + .in(in0_conv_stencil[0]), .clk(clk), - .out(_U684_out) + .out(_U687_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U685 ( - .in(_U684_out), +) _U688 ( + .in(_U687_out), .clk(clk), - .out(_U685_out) -); -_U686_pt__U687 _U686 ( - .in(in2_hw_kernel_global_wrapper_stencil[0]), - .out(_U686_out) -); -_U688_pt__U689 _U688 ( - .in(_U696_out), .out(_U688_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U689 ( + .in(_U688_out), + .clk(clk), + .out(_U689_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U690 ( - .in(in1_hw_input_global_wrapper_stencil[7]), + .in(_U689_out), .clk(clk), .out(_U690_out) ); @@ -14486,14 +14517,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U696_out) ); -_U697_pt__U698 _U697 ( - .in(_U704_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U697 ( + .in(_U696_out), + .clk(clk), .out(_U697_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U698 ( + .in(_U697_out), + .clk(clk), + .out(_U698_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U699 ( - .in(in1_hw_input_global_wrapper_stencil[6]), + .in(_U698_out), .clk(clk), .out(_U699_out) ); @@ -14504,24 +14545,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U700_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U701 ( - .in(_U700_out), - .clk(clk), +_U701_pt__U702 _U701 ( + .in(_U706_out), .out(_U701_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U702 ( - .in(_U701_out), - .clk(clk), - .out(_U702_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U703 ( - .in(_U702_out), + .in(in1_hw_input_global_wrapper_stencil[4]), .clk(clk), .out(_U703_out) ); @@ -14532,42 +14563,32 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U704_out) ); -_U705_pt__U706 _U705 ( - .in(_U720_out), - .out(_U705_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U707 ( - .in(in0_conv_stencil[0]), +) _U705 ( + .in(_U704_out), .clk(clk), - .out(_U707_out) + .out(_U705_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U708 ( - .in(_U707_out), +) _U706 ( + .in(_U705_out), .clk(clk), - .out(_U708_out) + .out(_U706_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U709 ( - .in(_U708_out), - .clk(clk), - .out(_U709_out) +_U707_pt__U708 _U707 ( + .in(in1_hw_input_global_wrapper_stencil[0]), + .out(_U707_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U710 ( - .in(_U709_out), - .clk(clk), - .out(_U710_out) +_U709_pt__U710 _U709 ( + .in(_U714_out), + .out(_U709_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U711 ( - .in(_U710_out), + .in(in2_hw_kernel_global_wrapper_stencil[4]), .clk(clk), .out(_U711_out) ); @@ -14592,24 +14613,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U714_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U715 ( - .in(_U714_out), - .clk(clk), +_U715_pt__U716 _U715 ( + .in(_U722_out), .out(_U715_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U716 ( - .in(_U715_out), - .clk(clk), - .out(_U716_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U717 ( - .in(_U716_out), + .in(in2_hw_kernel_global_wrapper_stencil[6]), .clk(clk), .out(_U717_out) ); @@ -14634,39 +14645,39 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U720_out) ); -_U721_pt__U722 _U721 ( - .in(_U725_out), - .out(_U721_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U723 ( - .in(in1_hw_input_global_wrapper_stencil[3]), +) _U721 ( + .in(_U720_out), .clk(clk), - .out(_U723_out) + .out(_U721_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U724 ( - .in(_U723_out), +) _U722 ( + .in(_U721_out), .clk(clk), - .out(_U724_out) + .out(_U722_out) +); +_U723_pt__U724 _U723 ( + .in(_U725_out), + .out(_U723_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U725 ( - .in(_U724_out), + .in(in1_hw_input_global_wrapper_stencil[1]), .clk(clk), .out(_U725_out) ); _U726_pt__U727 _U726 ( - .in(_U731_out), + .in(_U734_out), .out(_U726_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U728 ( - .in(in1_hw_input_global_wrapper_stencil[4]), + .in(in2_hw_kernel_global_wrapper_stencil[7]), .clk(clk), .out(_U728_out) ); @@ -14691,14 +14702,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U731_out) ); -_U732_pt__U733 _U732 ( - .in(_U734_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U732 ( + .in(_U731_out), + .clk(clk), .out(_U732_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U733 ( + .in(_U732_out), + .clk(clk), + .out(_U733_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U734 ( - .in(in2_hw_kernel_global_wrapper_stencil[1]), + .in(_U733_out), .clk(clk), .out(_U734_out) ); @@ -14709,7 +14730,7 @@ _U735_pt__U736 _U735 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U737 ( - .in(in2_hw_kernel_global_wrapper_stencil[3]), + .in(in1_hw_input_global_wrapper_stencil[3]), .clk(clk), .out(_U737_out) ); @@ -14734,7 +14755,7 @@ _U740_pt__U741 _U740 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U742 ( - .in(in2_hw_kernel_global_wrapper_stencil[2]), + .in(in1_hw_input_global_wrapper_stencil[2]), .clk(clk), .out(_U742_out) ); @@ -15259,16 +15280,16 @@ assign add_921_930_931_out = 16'(_U786_out + _U798_out); assign add_922_929_930_out = 16'(_U801_out + _U811_out); assign add_923_928_929_out = 16'(_U814_out + _U822_out); assign add_924_927_928_out = 16'(_U825_out + _U831_out); -assign add_925_926_927_out = 16'(_U834_out + _U664_out); -assign add_conv_stencil_4_932_933_out = 16'(_U705_out + _U783_out); -assign mul_hw_kernel_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_919_out = 16'(_U686_out * _U659_out); -assign mul_hw_kernel_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_920_out = 16'(_U732_out * _U661_out); -assign mul_hw_kernel_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_921_out = 16'(_U740_out * _U682_out); -assign mul_hw_kernel_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_922_out = 16'(_U735_out * _U721_out); -assign mul_hw_kernel_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_923_out = 16'(_U644_out * _U726_out); -assign mul_hw_kernel_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_924_out = 16'(_U637_out * _U667_out); -assign mul_hw_kernel_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_925_out = 16'(_U674_out * _U697_out); -assign mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926_out = 16'(_U650_out * _U688_out); +assign add_925_926_927_out = 16'(_U834_out + _U667_out); +assign add_conv_stencil_4_932_933_out = 16'(_U685_out + _U783_out); +assign mul_hw_kernel_global_wrapper_stencil_25_hw_input_global_wrapper_stencil_25_919_out = 16'(_U683_out * _U707_out); +assign mul_hw_kernel_global_wrapper_stencil_26_hw_input_global_wrapper_stencil_26_920_out = 16'(_U660_out * _U723_out); +assign mul_hw_kernel_global_wrapper_stencil_27_hw_input_global_wrapper_stencil_27_921_out = 16'(_U663_out * _U740_out); +assign mul_hw_kernel_global_wrapper_stencil_28_hw_input_global_wrapper_stencil_28_922_out = 16'(_U678_out * _U735_out); +assign mul_hw_kernel_global_wrapper_stencil_29_hw_input_global_wrapper_stencil_29_923_out = 16'(_U709_out * _U701_out); +assign mul_hw_kernel_global_wrapper_stencil_30_hw_input_global_wrapper_stencil_30_924_out = 16'(_U644_out * _U637_out); +assign mul_hw_kernel_global_wrapper_stencil_31_hw_input_global_wrapper_stencil_31_925_out = 16'(_U715_out * _U670_out); +assign mul_hw_kernel_global_wrapper_stencil_32_hw_input_global_wrapper_stencil_32_926_out = 16'(_U726_out * _U651_out); endmodule module cu_op_hcompute_conv_stencil_11 ( @@ -15330,14 +15351,14 @@ module _U611_pt__U612 ( assign out = in; endmodule -module _U60_pt__U61 ( +module _U603_pt__U604 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U603_pt__U604 ( +module _U59_pt__U60 ( input [15:0] in, output [15:0] out ); @@ -15421,14 +15442,14 @@ module _U551_pt__U552 ( assign out = in; endmodule -module _U54_pt__U55 ( +module _U549_pt__U550 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U549_pt__U550 ( +module _U53_pt__U54 ( input [15:0] in, output [15:0] out ); @@ -15498,7 +15519,7 @@ module _U4_pt__U5 ( assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_2_pipelined ( +module hcompute_hw_input_global_wrapper_stencil_6_pipelined ( output [15:0] out_hw_input_global_wrapper_stencil, input [15:0] in0_hw_input_stencil [0:0] ); @@ -15508,19 +15529,19 @@ _U4_pt__U5 _U4 ( ); endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil_2 ( +module cu_op_hcompute_hw_input_global_wrapper_stencil_6 ( input clk, - input [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write [0:0] + input [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write [0:0] ); wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read[0]; -hcompute_hw_input_global_wrapper_stencil_2_pipelined inner_compute ( +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read[0]; +hcompute_hw_input_global_wrapper_stencil_6_pipelined inner_compute ( .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) ); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; endmodule module _U493_pt__U494 ( @@ -16923,133 +16944,133 @@ hcompute_conv_stencil_10_pipelined inner_compute ( assign conv_stencil_op_hcompute_conv_stencil_10_write[0] = inner_compute_out_conv_stencil; endmodule -module _U432_pt__U433 ( +module _U430_pt__U431 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U428_pt__U429 ( +module _U425_pt__U426 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U425_pt__U426 ( +module _U420_pt__U421 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U422_pt__U423 ( +module _U416_pt__U417 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U420_pt__U421 ( +module _U412_pt__U413 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U418_pt__U419 ( +module _U409_pt__U410 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U409_pt__U410 ( +module _U406_pt__U407 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U400_pt__U401 ( +module _U404_pt__U405 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U392_pt__U393 ( +module _U402_pt__U403 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U38_pt__U39 ( +module _U39_pt__U40 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U384_pt__U385 ( +module _U393_pt__U394 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U377_pt__U378 ( +module _U384_pt__U385 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U370_pt__U371 ( +module _U376_pt__U377 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U364_pt__U365 ( +module _U368_pt__U369 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U358_pt__U359 ( +module _U361_pt__U362 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U353_pt__U354 ( +module _U35_pt__U36 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U34_pt__U35 ( +module _U354_pt__U355 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U348_pt__U349 ( +module _U338_pt__U339 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U332_pt__U333 ( +module _U331_pt__U332 ( input [15:0] in, output [15:0] out ); @@ -17063,26 +17084,6 @@ module _U32_pt__U33 ( assign out = in; endmodule -module hcompute_conv_stencil_7_pipelined ( - output [15:0] out_conv_stencil -); -_U32_pt__U33 _U32 ( - .in(16'h0000), - .out(out_conv_stencil) -); -endmodule - -module cu_op_hcompute_conv_stencil_7 ( - input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_7_write [0:0] -); -wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_7_pipelined inner_compute ( - .out_conv_stencil(inner_compute_out_conv_stencil) -); -assign conv_stencil_op_hcompute_conv_stencil_7_write[0] = inner_compute_out_conv_stencil; -endmodule - module _U323_pt__U324 ( input [15:0] in, output [15:0] out @@ -17090,7 +17091,7 @@ module _U323_pt__U324 ( assign out = in; endmodule -module _U313_pt__U314 ( +module _U320_pt__U321 ( input [15:0] in, output [15:0] out ); @@ -17111,7 +17112,7 @@ module _U30_pt__U31 ( assign out = in; endmodule -module hcompute_conv_stencil_6_pipelined ( +module hcompute_conv_stencil_7_pipelined ( output [15:0] out_conv_stencil ); _U30_pt__U31 _U30 ( @@ -17120,25 +17121,18 @@ _U30_pt__U31 _U30 ( ); endmodule -module cu_op_hcompute_conv_stencil_6 ( +module cu_op_hcompute_conv_stencil_7 ( input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_6_write [0:0] + output [15:0] conv_stencil_op_hcompute_conv_stencil_7_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_6_pipelined inner_compute ( +hcompute_conv_stencil_7_pipelined inner_compute ( .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_6_write[0] = inner_compute_out_conv_stencil; -endmodule - -module _U306_pt__U307 ( - input [15:0] in, - output [15:0] out -); -assign out = in; +assign conv_stencil_op_hcompute_conv_stencil_7_write[0] = inner_compute_out_conv_stencil; endmodule -module _U303_pt__U304 ( +module _U307_pt__U308 ( input [15:0] in, output [15:0] out ); @@ -17152,7 +17146,7 @@ module _U2_pt__U3 ( assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_1_pipelined ( +module hcompute_hw_input_global_wrapper_stencil_5_pipelined ( output [15:0] out_hw_input_global_wrapper_stencil, input [15:0] in0_hw_input_stencil [0:0] ); @@ -17162,29 +17156,29 @@ _U2_pt__U3 _U2 ( ); endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil_1 ( +module cu_op_hcompute_hw_input_global_wrapper_stencil_5 ( input clk, - input [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write [0:0] + input [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write [0:0] ); wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read[0]; -hcompute_hw_input_global_wrapper_stencil_1_pipelined inner_compute ( +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read[0]; +hcompute_hw_input_global_wrapper_stencil_5_pipelined inner_compute ( .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) ); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; endmodule -module _U297_pt__U298 ( +module _U295_pt__U296 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U294_pt__U295 ( +module _U292_pt__U293 ( input [15:0] in, output [15:0] out ); @@ -17198,7 +17192,7 @@ module _U28_pt__U29 ( assign out = in; endmodule -module hcompute_conv_stencil_5_pipelined ( +module hcompute_conv_stencil_6_pipelined ( output [15:0] out_conv_stencil ); _U28_pt__U29 _U28 ( @@ -17207,15 +17201,15 @@ _U28_pt__U29 _U28 ( ); endmodule -module cu_op_hcompute_conv_stencil_5 ( +module cu_op_hcompute_conv_stencil_6 ( input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_5_write [0:0] + output [15:0] conv_stencil_op_hcompute_conv_stencil_6_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_5_pipelined inner_compute ( +hcompute_conv_stencil_6_pipelined inner_compute ( .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_5_write[0] = inner_compute_out_conv_stencil; +assign conv_stencil_op_hcompute_conv_stencil_6_write[0] = inner_compute_out_conv_stencil; endmodule module _U286_pt__U287 ( @@ -17232,14 +17226,14 @@ module _U283_pt__U284 ( assign out = in; endmodule -module _U273_pt__U274 ( +module _U275_pt__U276 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U270_pt__U271 ( +module _U272_pt__U273 ( input [15:0] in, output [15:0] out ); @@ -17253,7 +17247,7 @@ module _U26_pt__U27 ( assign out = in; endmodule -module hcompute_conv_stencil_4_pipelined ( +module hcompute_conv_stencil_5_pipelined ( output [15:0] out_conv_stencil ); _U26_pt__U27 _U26 ( @@ -17262,39 +17256,39 @@ _U26_pt__U27 _U26 ( ); endmodule -module cu_op_hcompute_conv_stencil_4 ( +module cu_op_hcompute_conv_stencil_5 ( input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_4_write [0:0] + output [15:0] conv_stencil_op_hcompute_conv_stencil_5_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_4_pipelined inner_compute ( +hcompute_conv_stencil_5_pipelined inner_compute ( .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_4_write[0] = inner_compute_out_conv_stencil; +assign conv_stencil_op_hcompute_conv_stencil_5_write[0] = inner_compute_out_conv_stencil; endmodule -module _U267_pt__U268 ( +module _U269_pt__U270 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U255_pt__U256 ( +module _U259_pt__U260 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U253_pt__U254 ( +module _U257_pt__U258 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U250_pt__U251 ( +module _U254_pt__U255 ( input [15:0] in, output [15:0] out ); @@ -17308,7 +17302,7 @@ module _U24_pt__U25 ( assign out = in; endmodule -module hcompute_conv_stencil_3_pipelined ( +module hcompute_conv_stencil_4_pipelined ( output [15:0] out_conv_stencil ); _U24_pt__U25 _U24 ( @@ -17317,15 +17311,22 @@ _U24_pt__U25 _U24 ( ); endmodule -module cu_op_hcompute_conv_stencil_3 ( +module cu_op_hcompute_conv_stencil_4 ( input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_3_write [0:0] + output [15:0] conv_stencil_op_hcompute_conv_stencil_4_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_3_pipelined inner_compute ( +hcompute_conv_stencil_4_pipelined inner_compute ( .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_3_write[0] = inner_compute_out_conv_stencil; +assign conv_stencil_op_hcompute_conv_stencil_4_write[0] = inner_compute_out_conv_stencil; +endmodule + +module _U241_pt__U242 ( + input [15:0] in, + output [15:0] out +); +assign out = in; endmodule module _U235_pt__U236 ( @@ -17348,7 +17349,6 @@ wire [15:0] _U238_out; wire [15:0] _U239_out; wire [15:0] _U240_out; wire [15:0] _U241_out; -wire [15:0] _U242_out; wire [15:0] _U243_out; wire [15:0] _U244_out; wire [15:0] _U245_out; @@ -17357,12 +17357,12 @@ wire [15:0] _U247_out; wire [15:0] _U248_out; wire [15:0] _U249_out; wire [15:0] _U250_out; +wire [15:0] _U251_out; wire [15:0] _U252_out; -wire [15:0] _U255_out; -wire [15:0] _U257_out; -wire [15:0] _U258_out; +wire [15:0] _U253_out; +wire [15:0] _U254_out; +wire [15:0] _U256_out; wire [15:0] _U259_out; -wire [15:0] _U260_out; wire [15:0] _U261_out; wire [15:0] _U262_out; wire [15:0] _U263_out; @@ -17370,12 +17370,12 @@ wire [15:0] _U264_out; wire [15:0] _U265_out; wire [15:0] _U266_out; wire [15:0] _U267_out; +wire [15:0] _U268_out; wire [15:0] _U269_out; -wire [15:0] _U270_out; +wire [15:0] _U271_out; wire [15:0] _U272_out; -wire [15:0] _U273_out; +wire [15:0] _U274_out; wire [15:0] _U275_out; -wire [15:0] _U276_out; wire [15:0] _U277_out; wire [15:0] _U278_out; wire [15:0] _U279_out; @@ -17390,29 +17390,30 @@ wire [15:0] _U289_out; wire [15:0] _U290_out; wire [15:0] _U291_out; wire [15:0] _U292_out; -wire [15:0] _U293_out; wire [15:0] _U294_out; -wire [15:0] _U296_out; +wire [15:0] _U295_out; wire [15:0] _U297_out; +wire [15:0] _U298_out; wire [15:0] _U299_out; wire [15:0] _U300_out; wire [15:0] _U301_out; wire [15:0] _U302_out; wire [15:0] _U303_out; +wire [15:0] _U304_out; wire [15:0] _U305_out; wire [15:0] _U306_out; -wire [15:0] _U308_out; +wire [15:0] _U307_out; wire [15:0] _U309_out; wire [15:0] _U310_out; wire [15:0] _U312_out; wire [15:0] _U313_out; +wire [15:0] _U314_out; wire [15:0] _U315_out; wire [15:0] _U316_out; wire [15:0] _U317_out; wire [15:0] _U318_out; wire [15:0] _U319_out; wire [15:0] _U320_out; -wire [15:0] _U321_out; wire [15:0] _U322_out; wire [15:0] _U323_out; wire [15:0] _U325_out; @@ -17422,13 +17423,12 @@ wire [15:0] _U328_out; wire [15:0] _U329_out; wire [15:0] _U330_out; wire [15:0] _U331_out; -wire [15:0] _U332_out; +wire [15:0] _U333_out; wire [15:0] _U334_out; wire [15:0] _U335_out; wire [15:0] _U336_out; wire [15:0] _U337_out; wire [15:0] _U338_out; -wire [15:0] _U339_out; wire [15:0] _U340_out; wire [15:0] _U341_out; wire [15:0] _U342_out; @@ -17438,30 +17438,32 @@ wire [15:0] _U345_out; wire [15:0] _U346_out; wire [15:0] _U347_out; wire [15:0] _U348_out; +wire [15:0] _U349_out; wire [15:0] _U350_out; wire [15:0] _U351_out; wire [15:0] _U352_out; wire [15:0] _U353_out; -wire [15:0] _U355_out; +wire [15:0] _U354_out; wire [15:0] _U356_out; wire [15:0] _U357_out; wire [15:0] _U358_out; +wire [15:0] _U359_out; wire [15:0] _U360_out; wire [15:0] _U361_out; -wire [15:0] _U362_out; wire [15:0] _U363_out; wire [15:0] _U364_out; +wire [15:0] _U365_out; wire [15:0] _U366_out; wire [15:0] _U367_out; wire [15:0] _U368_out; -wire [15:0] _U369_out; wire [15:0] _U370_out; +wire [15:0] _U371_out; wire [15:0] _U372_out; wire [15:0] _U373_out; wire [15:0] _U374_out; wire [15:0] _U375_out; wire [15:0] _U376_out; -wire [15:0] _U377_out; +wire [15:0] _U378_out; wire [15:0] _U379_out; wire [15:0] _U380_out; wire [15:0] _U381_out; @@ -17475,38 +17477,37 @@ wire [15:0] _U389_out; wire [15:0] _U390_out; wire [15:0] _U391_out; wire [15:0] _U392_out; -wire [15:0] _U394_out; +wire [15:0] _U393_out; wire [15:0] _U395_out; wire [15:0] _U396_out; wire [15:0] _U397_out; wire [15:0] _U398_out; wire [15:0] _U399_out; wire [15:0] _U400_out; +wire [15:0] _U401_out; wire [15:0] _U402_out; -wire [15:0] _U403_out; wire [15:0] _U404_out; -wire [15:0] _U405_out; wire [15:0] _U406_out; -wire [15:0] _U407_out; wire [15:0] _U408_out; wire [15:0] _U409_out; wire [15:0] _U411_out; wire [15:0] _U412_out; -wire [15:0] _U413_out; wire [15:0] _U414_out; wire [15:0] _U415_out; wire [15:0] _U416_out; -wire [15:0] _U417_out; wire [15:0] _U418_out; +wire [15:0] _U419_out; wire [15:0] _U420_out; wire [15:0] _U422_out; +wire [15:0] _U423_out; wire [15:0] _U424_out; wire [15:0] _U425_out; wire [15:0] _U427_out; wire [15:0] _U428_out; +wire [15:0] _U429_out; wire [15:0] _U430_out; -wire [15:0] _U431_out; wire [15:0] _U432_out; +wire [15:0] _U433_out; wire [15:0] _U434_out; wire [15:0] _U435_out; wire [15:0] add_785_799_800_out; @@ -17526,13 +17527,13 @@ wire [15:0] mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_sten wire [15:0] mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792_out; wire [15:0] mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785_out; _U235_pt__U236 _U235 ( - .in(_U249_out), + .in(_U240_out), .out(_U235_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U237 ( - .in(mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785_out), + .in(in1_hw_input_global_wrapper_stencil[7]), .clk(clk), .out(_U237_out) ); @@ -17557,24 +17558,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U240_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U241 ( - .in(_U240_out), - .clk(clk), +_U241_pt__U242 _U241 ( + .in(_U253_out), .out(_U241_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U242 ( - .in(_U241_out), - .clk(clk), - .out(_U242_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U243 ( - .in(_U242_out), + .in(mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785_out), .clk(clk), .out(_U243_out) ); @@ -17620,57 +17611,57 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U249_out) ); -_U250_pt__U251 _U250 ( - .in(_U252_out), - .out(_U250_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U252 ( - .in(add_conv_stencil_2_798_799_out), +) _U250 ( + .in(_U249_out), .clk(clk), - .out(_U252_out) -); -_U253_pt__U254 _U253 ( - .in(add_785_799_800_out), - .out(out_conv_stencil) -); -_U255_pt__U256 _U255 ( - .in(_U266_out), - .out(_U255_out) + .out(_U250_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U257 ( - .in(mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786_out), +) _U251 ( + .in(_U250_out), .clk(clk), - .out(_U257_out) + .out(_U251_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U258 ( - .in(_U257_out), +) _U252 ( + .in(_U251_out), .clk(clk), - .out(_U258_out) + .out(_U252_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U259 ( - .in(_U258_out), +) _U253 ( + .in(_U252_out), .clk(clk), - .out(_U259_out) + .out(_U253_out) +); +_U254_pt__U255 _U254 ( + .in(_U256_out), + .out(_U254_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U260 ( - .in(_U259_out), +) _U256 ( + .in(add_conv_stencil_2_798_799_out), .clk(clk), - .out(_U260_out) + .out(_U256_out) +); +_U257_pt__U258 _U257 ( + .in(add_785_799_800_out), + .out(out_conv_stencil) +); +_U259_pt__U260 _U259 ( + .in(_U268_out), + .out(_U259_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U261 ( - .in(_U260_out), + .in(mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786_out), .clk(clk), .out(_U261_out) ); @@ -17709,50 +17700,50 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U266_out) ); -_U267_pt__U268 _U267 ( - .in(_U269_out), - .out(_U267_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U269 ( - .in(add_787_796_797_out), +) _U267 ( + .in(_U266_out), .clk(clk), - .out(_U269_out) -); -_U270_pt__U271 _U270 ( - .in(_U272_out), - .out(_U270_out) + .out(_U267_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U272 ( - .in(add_786_797_798_out), +) _U268 ( + .in(_U267_out), .clk(clk), - .out(_U272_out) + .out(_U268_out) ); -_U273_pt__U274 _U273 ( - .in(_U282_out), - .out(_U273_out) +_U269_pt__U270 _U269 ( + .in(_U271_out), + .out(_U269_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U275 ( - .in(mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787_out), +) _U271 ( + .in(add_787_796_797_out), .clk(clk), - .out(_U275_out) + .out(_U271_out) +); +_U272_pt__U273 _U272 ( + .in(_U274_out), + .out(_U272_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U276 ( - .in(_U275_out), +) _U274 ( + .in(add_786_797_798_out), .clk(clk), - .out(_U276_out) + .out(_U274_out) +); +_U275_pt__U276 _U275 ( + .in(_U282_out), + .out(_U275_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U277 ( - .in(_U276_out), + .in(mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787_out), .clk(clk), .out(_U277_out) ); @@ -17803,7 +17794,7 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U285_out) ); _U286_pt__U287 _U286 ( - .in(_U293_out), + .in(_U291_out), .out(_U286_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( @@ -17834,39 +17825,39 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U291_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U292 ( - .in(_U291_out), - .clk(clk), +_U292_pt__U293 _U292 ( + .in(_U294_out), .out(_U292_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U293 ( - .in(_U292_out), +) _U294 ( + .in(add_789_794_795_out), .clk(clk), - .out(_U293_out) -); -_U294_pt__U295 _U294 ( - .in(_U296_out), .out(_U294_out) ); +_U295_pt__U296 _U295 ( + .in(_U306_out), + .out(_U295_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U296 ( - .in(add_789_794_795_out), +) _U297 ( + .in(mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789_out), .clk(clk), - .out(_U296_out) -); -_U297_pt__U298 _U297 ( - .in(_U302_out), .out(_U297_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U298 ( + .in(_U297_out), + .clk(clk), + .out(_U298_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U299 ( - .in(mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789_out), + .in(_U298_out), .clk(clk), .out(_U299_out) ); @@ -17891,54 +17882,74 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U302_out) ); -_U303_pt__U304 _U303 ( - .in(_U305_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U303 ( + .in(_U302_out), + .clk(clk), .out(_U303_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U304 ( + .in(_U303_out), + .clk(clk), + .out(_U304_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U305 ( - .in(add_790_793_794_out), + .in(_U304_out), .clk(clk), .out(_U305_out) ); -_U306_pt__U307 _U306 ( - .in(_U309_out), - .out(_U306_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U308 ( - .in(mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790_out), +) _U306 ( + .in(_U305_out), .clk(clk), - .out(_U308_out) + .out(_U306_out) +); +_U307_pt__U308 _U307 ( + .in(_U309_out), + .out(_U307_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U309 ( - .in(_U308_out), + .in(add_790_793_794_out), .clk(clk), .out(_U309_out) ); _U310_pt__U311 _U310 ( - .in(_U312_out), + .in(_U319_out), .out(_U310_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U312 ( - .in(add_791_792_793_out), + .in(mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790_out), .clk(clk), .out(_U312_out) ); -_U313_pt__U314 _U313 ( - .in(_U322_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U313 ( + .in(_U312_out), + .clk(clk), .out(_U313_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U314 ( + .in(_U313_out), + .clk(clk), + .out(_U314_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U315 ( - .in(mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791_out), + .in(_U314_out), .clk(clk), .out(_U315_out) ); @@ -17970,35 +17981,25 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U319_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U320 ( - .in(_U319_out), - .clk(clk), +_U320_pt__U321 _U320 ( + .in(_U322_out), .out(_U320_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U321 ( - .in(_U320_out), - .clk(clk), - .out(_U321_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U322 ( - .in(_U321_out), + .in(add_791_792_793_out), .clk(clk), .out(_U322_out) ); _U323_pt__U324 _U323 ( - .in(_U331_out), + .in(_U330_out), .out(_U323_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U325 ( - .in(mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792_out), + .in(mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791_out), .clk(clk), .out(_U325_out) ); @@ -18037,21 +18038,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U330_out) ); +_U331_pt__U332 _U331 ( + .in(_U337_out), + .out(_U331_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U331 ( - .in(_U330_out), +) _U333 ( + .in(mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792_out), .clk(clk), - .out(_U331_out) -); -_U332_pt__U333 _U332 ( - .in(_U347_out), - .out(_U332_out) + .out(_U333_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U334 ( - .in(in0_conv_stencil[0]), + .in(_U333_out), .clk(clk), .out(_U334_out) ); @@ -18076,24 +18077,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U337_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U338 ( - .in(_U337_out), - .clk(clk), +_U338_pt__U339 _U338 ( + .in(_U353_out), .out(_U338_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U339 ( - .in(_U338_out), - .clk(clk), - .out(_U339_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U340 ( - .in(_U339_out), + .in(in0_conv_stencil[0]), .clk(clk), .out(_U340_out) ); @@ -18146,14 +18137,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U347_out) ); -_U348_pt__U349 _U348 ( - .in(_U352_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U348 ( + .in(_U347_out), + .clk(clk), .out(_U348_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U349 ( + .in(_U348_out), + .clk(clk), + .out(_U349_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U350 ( - .in(in2_hw_kernel_global_wrapper_stencil[0]), + .in(_U349_out), .clk(clk), .out(_U350_out) ); @@ -18171,21 +18172,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U352_out) ); -_U353_pt__U354 _U353 ( - .in(_U357_out), - .out(_U353_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U355 ( - .in(in1_hw_input_global_wrapper_stencil[0]), +) _U353 ( + .in(_U352_out), .clk(clk), - .out(_U355_out) + .out(_U353_out) +); +_U354_pt__U355 _U354 ( + .in(_U360_out), + .out(_U354_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U356 ( - .in(_U355_out), + .in(in2_hw_kernel_global_wrapper_stencil[0]), .clk(clk), .out(_U356_out) ); @@ -18196,46 +18197,56 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U357_out) ); -_U358_pt__U359 _U358 ( - .in(_U363_out), - .out(_U358_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U360 ( - .in(in2_hw_kernel_global_wrapper_stencil[1]), +) _U358 ( + .in(_U357_out), .clk(clk), - .out(_U360_out) + .out(_U358_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U361 ( - .in(_U360_out), +) _U359 ( + .in(_U358_out), .clk(clk), - .out(_U361_out) + .out(_U359_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U362 ( - .in(_U361_out), +) _U360 ( + .in(_U359_out), .clk(clk), - .out(_U362_out) + .out(_U360_out) +); +_U361_pt__U362 _U361 ( + .in(_U367_out), + .out(_U361_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U363 ( - .in(_U362_out), + .in(in1_hw_input_global_wrapper_stencil[0]), .clk(clk), .out(_U363_out) ); -_U364_pt__U365 _U364 ( - .in(_U369_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U364 ( + .in(_U363_out), + .clk(clk), .out(_U364_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U365 ( + .in(_U364_out), + .clk(clk), + .out(_U365_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U366 ( - .in(in1_hw_input_global_wrapper_stencil[1]), + .in(_U365_out), .clk(clk), .out(_U366_out) ); @@ -18246,28 +18257,28 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U367_out) ); +_U368_pt__U369 _U368 ( + .in(_U375_out), + .out(_U368_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U368 ( - .in(_U367_out), +) _U370 ( + .in(in2_hw_kernel_global_wrapper_stencil[1]), .clk(clk), - .out(_U368_out) + .out(_U370_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U369 ( - .in(_U368_out), +) _U371 ( + .in(_U370_out), .clk(clk), - .out(_U369_out) -); -_U370_pt__U371 _U370 ( - .in(_U376_out), - .out(_U370_out) + .out(_U371_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U372 ( - .in(in2_hw_kernel_global_wrapper_stencil[2]), + .in(_U371_out), .clk(clk), .out(_U372_out) ); @@ -18292,21 +18303,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U375_out) ); +_U376_pt__U377 _U376 ( + .in(_U383_out), + .out(_U376_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U376 ( - .in(_U375_out), +) _U378 ( + .in(in1_hw_input_global_wrapper_stencil[1]), .clk(clk), - .out(_U376_out) -); -_U377_pt__U378 _U377 ( - .in(_U383_out), - .out(_U377_out) + .out(_U378_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U379 ( - .in(in1_hw_input_global_wrapper_stencil[2]), + .in(_U378_out), .clk(clk), .out(_U379_out) ); @@ -18339,13 +18350,13 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U383_out) ); _U384_pt__U385 _U384 ( - .in(_U391_out), + .in(_U392_out), .out(_U384_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U386 ( - .in(in2_hw_kernel_global_wrapper_stencil[3]), + .in(in2_hw_kernel_global_wrapper_stencil[2]), .clk(clk), .out(_U386_out) ); @@ -18384,21 +18395,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U391_out) ); -_U392_pt__U393 _U392 ( - .in(_U399_out), - .out(_U392_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U394 ( - .in(in1_hw_input_global_wrapper_stencil[3]), +) _U392 ( + .in(_U391_out), .clk(clk), - .out(_U394_out) + .out(_U392_out) +); +_U393_pt__U394 _U393 ( + .in(_U401_out), + .out(_U393_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U395 ( - .in(_U394_out), + .in(in1_hw_input_global_wrapper_stencil[2]), .clk(clk), .out(_U395_out) ); @@ -18430,61 +18441,41 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U399_out) ); -_U400_pt__U401 _U400 ( - .in(_U408_out), - .out(_U400_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U402 ( - .in(in2_hw_kernel_global_wrapper_stencil[4]), +) _U400 ( + .in(_U399_out), .clk(clk), - .out(_U402_out) + .out(_U400_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U403 ( - .in(_U402_out), +) _U401 ( + .in(_U400_out), .clk(clk), - .out(_U403_out) + .out(_U401_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U404 ( - .in(_U403_out), - .clk(clk), - .out(_U404_out) +_U402_pt__U403 _U402 ( + .in(in2_hw_kernel_global_wrapper_stencil[3]), + .out(_U402_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U405 ( - .in(_U404_out), - .clk(clk), - .out(_U405_out) +_U404_pt__U405 _U404 ( + .in(in1_hw_input_global_wrapper_stencil[3]), + .out(_U404_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U406 ( - .in(_U405_out), - .clk(clk), +_U406_pt__U407 _U406 ( + .in(_U408_out), .out(_U406_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U407 ( - .in(_U406_out), - .clk(clk), - .out(_U407_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U408 ( - .in(_U407_out), + .in(in2_hw_kernel_global_wrapper_stencil[4]), .clk(clk), .out(_U408_out) ); _U409_pt__U410 _U409 ( - .in(_U417_out), + .in(_U411_out), .out(_U409_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( @@ -18494,24 +18485,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U411_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U412 ( - .in(_U411_out), - .clk(clk), +_U412_pt__U413 _U412 ( + .in(_U415_out), .out(_U412_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U413 ( - .in(_U412_out), - .clk(clk), - .out(_U413_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U414 ( - .in(_U413_out), + .in(in2_hw_kernel_global_wrapper_stencil[5]), .clk(clk), .out(_U414_out) ); @@ -18522,41 +18503,51 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U415_out) ); +_U416_pt__U417 _U416 ( + .in(_U419_out), + .out(_U416_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U416 ( - .in(_U415_out), +) _U418 ( + .in(in1_hw_input_global_wrapper_stencil[5]), .clk(clk), - .out(_U416_out) + .out(_U418_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U417 ( - .in(_U416_out), +) _U419 ( + .in(_U418_out), .clk(clk), - .out(_U417_out) -); -_U418_pt__U419 _U418 ( - .in(in2_hw_kernel_global_wrapper_stencil[5]), - .out(_U418_out) + .out(_U419_out) ); _U420_pt__U421 _U420 ( - .in(in1_hw_input_global_wrapper_stencil[5]), + .in(_U424_out), .out(_U420_out) ); -_U422_pt__U423 _U422 ( - .in(_U424_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U422 ( + .in(in2_hw_kernel_global_wrapper_stencil[6]), + .clk(clk), .out(_U422_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U423 ( + .in(_U422_out), + .clk(clk), + .out(_U423_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U424 ( - .in(in2_hw_kernel_global_wrapper_stencil[6]), + .in(_U423_out), .clk(clk), .out(_U424_out) ); _U425_pt__U426 _U425 ( - .in(_U427_out), + .in(_U429_out), .out(_U425_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( @@ -18566,32 +18557,42 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U427_out) ); -_U428_pt__U429 _U428 ( - .in(_U431_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U428 ( + .in(_U427_out), + .clk(clk), .out(_U428_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U430 ( - .in(in2_hw_kernel_global_wrapper_stencil[7]), +) _U429 ( + .in(_U428_out), .clk(clk), + .out(_U429_out) +); +_U430_pt__U431 _U430 ( + .in(_U435_out), .out(_U430_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U431 ( - .in(_U430_out), +) _U432 ( + .in(in2_hw_kernel_global_wrapper_stencil[7]), .clk(clk), - .out(_U431_out) -); -_U432_pt__U433 _U432 ( - .in(_U435_out), .out(_U432_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U433 ( + .in(_U432_out), + .clk(clk), + .out(_U433_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U434 ( - .in(in1_hw_input_global_wrapper_stencil[7]), + .in(_U433_out), .clk(clk), .out(_U434_out) ); @@ -18602,22 +18603,22 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U435_out) ); -assign add_785_799_800_out = 16'(_U235_out + _U250_out); -assign add_786_797_798_out = 16'(_U255_out + _U267_out); -assign add_787_796_797_out = 16'(_U273_out + _U283_out); -assign add_788_795_796_out = 16'(_U286_out + _U294_out); -assign add_789_794_795_out = 16'(_U297_out + _U303_out); -assign add_790_793_794_out = 16'(_U306_out + _U310_out); -assign add_791_792_793_out = 16'(_U313_out + _U323_out); -assign add_conv_stencil_2_798_799_out = 16'(_U332_out + _U270_out); -assign mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786_out = 16'(_U348_out * _U353_out); -assign mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787_out = 16'(_U358_out * _U364_out); -assign mul_hw_kernel_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_788_out = 16'(_U370_out * _U377_out); -assign mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789_out = 16'(_U384_out * _U392_out); -assign mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790_out = 16'(_U400_out * _U409_out); -assign mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791_out = 16'(_U418_out * _U420_out); -assign mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792_out = 16'(_U422_out * _U425_out); -assign mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785_out = 16'(_U428_out * _U432_out); +assign add_785_799_800_out = 16'(_U241_out + _U254_out); +assign add_786_797_798_out = 16'(_U259_out + _U269_out); +assign add_787_796_797_out = 16'(_U275_out + _U283_out); +assign add_788_795_796_out = 16'(_U286_out + _U292_out); +assign add_789_794_795_out = 16'(_U295_out + _U307_out); +assign add_790_793_794_out = 16'(_U310_out + _U320_out); +assign add_791_792_793_out = 16'(_U323_out + _U331_out); +assign add_conv_stencil_2_798_799_out = 16'(_U338_out + _U272_out); +assign mul_hw_kernel_global_wrapper_stencil_10_hw_input_global_wrapper_stencil_10_786_out = 16'(_U354_out * _U361_out); +assign mul_hw_kernel_global_wrapper_stencil_11_hw_input_global_wrapper_stencil_11_787_out = 16'(_U368_out * _U376_out); +assign mul_hw_kernel_global_wrapper_stencil_12_hw_input_global_wrapper_stencil_12_788_out = 16'(_U384_out * _U393_out); +assign mul_hw_kernel_global_wrapper_stencil_13_hw_input_global_wrapper_stencil_13_789_out = 16'(_U402_out * _U404_out); +assign mul_hw_kernel_global_wrapper_stencil_14_hw_input_global_wrapper_stencil_14_790_out = 16'(_U406_out * _U409_out); +assign mul_hw_kernel_global_wrapper_stencil_15_hw_input_global_wrapper_stencil_15_791_out = 16'(_U412_out * _U416_out); +assign mul_hw_kernel_global_wrapper_stencil_16_hw_input_global_wrapper_stencil_16_792_out = 16'(_U420_out * _U425_out); +assign mul_hw_kernel_global_wrapper_stencil_9_hw_input_global_wrapper_stencil_9_785_out = 16'(_U430_out * _U235_out); endmodule module cu_op_hcompute_conv_stencil_9 ( @@ -18665,11 +18666,29 @@ module _U233_pt__U234 ( assign out = in; endmodule -module _U230_pt__U231 ( - input [15:0] in, - output [15:0] out +module hcompute_hw_input_global_wrapper_stencil_7_pipelined ( + output [15:0] out_hw_input_global_wrapper_stencil, + input [15:0] in0_hw_input_stencil [0:0] ); -assign out = in; +_U233_pt__U234 _U233 ( + .in(in0_hw_input_stencil[0]), + .out(out_hw_input_global_wrapper_stencil) +); +endmodule + +module cu_op_hcompute_hw_input_global_wrapper_stencil_7 ( + input clk, + input [15:0] hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_write [0:0] +); +wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; +wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read[0]; +hcompute_hw_input_global_wrapper_stencil_7_pipelined inner_compute ( + .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), + .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) +); +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; endmodule module _U22_pt__U23 ( @@ -18679,7 +18698,7 @@ module _U22_pt__U23 ( assign out = in; endmodule -module hcompute_conv_stencil_2_pipelined ( +module hcompute_conv_stencil_3_pipelined ( output [15:0] out_conv_stencil ); _U22_pt__U23 _U22 ( @@ -18688,18 +18707,18 @@ _U22_pt__U23 _U22 ( ); endmodule -module cu_op_hcompute_conv_stencil_2 ( +module cu_op_hcompute_conv_stencil_3 ( input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_2_write [0:0] + output [15:0] conv_stencil_op_hcompute_conv_stencil_3_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_2_pipelined inner_compute ( +hcompute_conv_stencil_3_pipelined inner_compute ( .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_2_write[0] = inner_compute_out_conv_stencil; +assign conv_stencil_op_hcompute_conv_stencil_3_write[0] = inner_compute_out_conv_stencil; endmodule -module _U213_pt__U214 ( +module _U216_pt__U217 ( input [15:0] in, output [15:0] out ); @@ -18713,7 +18732,7 @@ module _U20_pt__U21 ( assign out = in; endmodule -module hcompute_conv_stencil_1_pipelined ( +module hcompute_conv_stencil_2_pipelined ( output [15:0] out_conv_stencil ); _U20_pt__U21 _U20 ( @@ -18722,15 +18741,15 @@ _U20_pt__U21 _U20 ( ); endmodule -module cu_op_hcompute_conv_stencil_1 ( +module cu_op_hcompute_conv_stencil_2 ( input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_1_write [0:0] + output [15:0] conv_stencil_op_hcompute_conv_stencil_2_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_1_pipelined inner_compute ( +hcompute_conv_stencil_2_pipelined inner_compute ( .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_1_write[0] = inner_compute_out_conv_stencil; +assign conv_stencil_op_hcompute_conv_stencil_2_write[0] = inner_compute_out_conv_stencil; endmodule module _U207_pt__U208 ( @@ -18740,21 +18759,14 @@ module _U207_pt__U208 ( assign out = in; endmodule -module _U204_pt__U205 ( - input [15:0] in, - output [15:0] out -); -assign out = in; -endmodule - -module _U196_pt__U197 ( +module _U198_pt__U199 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U193_pt__U194 ( +module _U195_pt__U196 ( input [15:0] in, output [15:0] out ); @@ -18768,7 +18780,7 @@ module _U18_pt__U19 ( assign out = in; endmodule -module hcompute_conv_stencil_pipelined ( +module hcompute_conv_stencil_1_pipelined ( output [15:0] out_conv_stencil ); _U18_pt__U19 _U18 ( @@ -18777,77 +18789,72 @@ _U18_pt__U19 _U18 ( ); endmodule -module cu_op_hcompute_conv_stencil ( +module cu_op_hcompute_conv_stencil_1 ( input clk, - output [15:0] conv_stencil_op_hcompute_conv_stencil_write [0:0] + output [15:0] conv_stencil_op_hcompute_conv_stencil_1_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; -hcompute_conv_stencil_pipelined inner_compute ( +hcompute_conv_stencil_1_pipelined inner_compute ( .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_write[0] = inner_compute_out_conv_stencil; +assign conv_stencil_op_hcompute_conv_stencil_1_write[0] = inner_compute_out_conv_stencil; endmodule -module _U183_pt__U184 ( +module _U187_pt__U188 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U180_pt__U181 ( +module _U184_pt__U185 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U16_pt__U17 ( +module _U174_pt__U175 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module hcompute_hw_kernel_global_wrapper_stencil_pipelined ( - output [15:0] out_hw_kernel_global_wrapper_stencil, - input [15:0] in0_hw_kernel_stencil [0:0] -); -_U16_pt__U17 _U16 ( - .in(in0_hw_kernel_stencil[0]), - .out(out_hw_kernel_global_wrapper_stencil) -); -endmodule - -module cu_op_hcompute_hw_kernel_global_wrapper_stencil ( - input clk, - input [15:0] hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read [0:0], - output [15:0] hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write [0:0] -); -wire [15:0] inner_compute_out_hw_kernel_global_wrapper_stencil; -wire [15:0] inner_compute_in0_hw_kernel_stencil [0:0]; -assign inner_compute_in0_hw_kernel_stencil[0] = hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read[0]; -hcompute_hw_kernel_global_wrapper_stencil_pipelined inner_compute ( - .out_hw_kernel_global_wrapper_stencil(inner_compute_out_hw_kernel_global_wrapper_stencil), - .in0_hw_kernel_stencil(inner_compute_in0_hw_kernel_stencil) -); -assign hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write[0] = inner_compute_out_hw_kernel_global_wrapper_stencil; -endmodule - -module _U168_pt__U169 ( +module _U171_pt__U172 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U165_pt__U166 ( +module _U16_pt__U17 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule +module hcompute_conv_stencil_pipelined ( + output [15:0] out_conv_stencil +); +_U16_pt__U17 _U16 ( + .in(16'h0000), + .out(out_conv_stencil) +); +endmodule + +module cu_op_hcompute_conv_stencil ( + input clk, + output [15:0] conv_stencil_op_hcompute_conv_stencil_write [0:0] +); +wire [15:0] inner_compute_out_conv_stencil; +hcompute_conv_stencil_pipelined inner_compute ( + .out_conv_stencil(inner_compute_out_conv_stencil) +); +assign conv_stencil_op_hcompute_conv_stencil_write[0] = inner_compute_out_conv_stencil; +endmodule + module _U1656_pt__U1657 ( input [15:0] in, output [15:0] out @@ -19104,56 +19111,56 @@ hcompute_hw_output_stencil_pipelined inner_compute ( assign hw_output_stencil_clkwrk_8_op_hcompute_hw_output_stencil_write[0] = inner_compute_out_hw_output_stencil; endmodule -module _U1639_pt__U1640 ( +module _U1632_pt__U1633 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U162_pt__U163 ( +module _U1629_pt__U1630 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1629_pt__U1630 ( +module _U1617_pt__U1618 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1626_pt__U1627 ( +module _U1614_pt__U1615 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1614_pt__U1615 ( +module _U1611_pt__U1612 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1611_pt__U1612 ( +module _U159_pt__U160 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1608_pt__U1609 ( +module _U1597_pt__U1598 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1594_pt__U1595 ( +module _U1595_pt__U1596 ( input [15:0] in, output [15:0] out ); @@ -19167,7 +19174,7 @@ module _U1592_pt__U1593 ( assign out = in; endmodule -module _U1589_pt__U1590 ( +module _U1575_pt__U1576 ( input [15:0] in, output [15:0] out ); @@ -19181,200 +19188,200 @@ module _U1572_pt__U1573 ( assign out = in; endmodule -module _U1568_pt__U1569 ( +module _U156_pt__U157 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1565_pt__U1566 ( +module _U1566_pt__U1567 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1559_pt__U1560 ( +module _U1563_pt__U1564 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1556_pt__U1557 ( +module _U1555_pt__U1556 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1548_pt__U1549 ( +module _U1552_pt__U1553 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1545_pt__U1546 ( +module _U1550_pt__U1551 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1543_pt__U1544 ( +module _U153_pt__U154 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1541_pt__U1542 ( +module _U1534_pt__U1535 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1525_pt__U1526 ( +module _U1531_pt__U1532 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1522_pt__U1523 ( +module _U1527_pt__U1528 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1514_pt__U1515 ( +module _U1520_pt__U1521 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1506_pt__U1507 ( +module _U1513_pt__U1514 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U14_pt__U15 ( +module _U1507_pt__U1508 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_7_pipelined ( - output [15:0] out_hw_input_global_wrapper_stencil, - input [15:0] in0_hw_input_stencil [0:0] -); -_U14_pt__U15 _U14 ( - .in(in0_hw_input_stencil[0]), - .out(out_hw_input_global_wrapper_stencil) +module _U1501_pt__U1502 ( + input [15:0] in, + output [15:0] out ); +assign out = in; endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil_7 ( - input clk, - input [15:0] hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_write [0:0] -); -wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; -wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read[0]; -hcompute_hw_input_global_wrapper_stencil_7_pipelined inner_compute ( - .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), - .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) -); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; -endmodule - -module _U1499_pt__U1500 ( +module _U14_pt__U15 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1492_pt__U1493 ( - input [15:0] in, - output [15:0] out +module hcompute_hw_kernel_global_wrapper_stencil_pipelined ( + output [15:0] out_hw_kernel_global_wrapper_stencil, + input [15:0] in0_hw_kernel_stencil [0:0] ); -assign out = in; +_U14_pt__U15 _U14 ( + .in(in0_hw_kernel_stencil[0]), + .out(out_hw_kernel_global_wrapper_stencil) +); +endmodule + +module cu_op_hcompute_hw_kernel_global_wrapper_stencil ( + input clk, + input [15:0] hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read [0:0], + output [15:0] hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write [0:0] +); +wire [15:0] inner_compute_out_hw_kernel_global_wrapper_stencil; +wire [15:0] inner_compute_in0_hw_kernel_stencil [0:0]; +assign inner_compute_in0_hw_kernel_stencil[0] = hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read[0]; +hcompute_hw_kernel_global_wrapper_stencil_pipelined inner_compute ( + .out_hw_kernel_global_wrapper_stencil(inner_compute_out_hw_kernel_global_wrapper_stencil), + .in0_hw_kernel_stencil(inner_compute_in0_hw_kernel_stencil) +); +assign hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write[0] = inner_compute_out_hw_kernel_global_wrapper_stencil; endmodule -module _U148_pt__U149 ( +module _U1496_pt__U1497 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1486_pt__U1487 ( +module _U1491_pt__U1492 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1480_pt__U1481 ( +module _U1487_pt__U1488 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1475_pt__U1476 ( +module _U1483_pt__U1484 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1470_pt__U1471 ( +module _U1480_pt__U1481 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1466_pt__U1467 ( +module _U1477_pt__U1478 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1462_pt__U1463 ( +module _U1475_pt__U1476 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1459_pt__U1460 ( +module _U1466_pt__U1467 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1450_pt__U1451 ( +module _U1457_pt__U1458 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U144_pt__U145 ( +module _U1449_pt__U1450 ( input [15:0] in, output [15:0] out ); @@ -19403,110 +19410,109 @@ wire [15:0] _U1446_out; wire [15:0] _U1447_out; wire [15:0] _U1448_out; wire [15:0] _U1449_out; -wire [15:0] _U1450_out; +wire [15:0] _U1451_out; wire [15:0] _U1452_out; wire [15:0] _U1453_out; wire [15:0] _U1454_out; wire [15:0] _U1455_out; wire [15:0] _U1456_out; wire [15:0] _U1457_out; -wire [15:0] _U1458_out; wire [15:0] _U1459_out; +wire [15:0] _U1460_out; wire [15:0] _U1461_out; wire [15:0] _U1462_out; +wire [15:0] _U1463_out; wire [15:0] _U1464_out; wire [15:0] _U1465_out; wire [15:0] _U1466_out; wire [15:0] _U1468_out; wire [15:0] _U1469_out; wire [15:0] _U1470_out; +wire [15:0] _U1471_out; wire [15:0] _U1472_out; wire [15:0] _U1473_out; wire [15:0] _U1474_out; wire [15:0] _U1475_out; wire [15:0] _U1477_out; -wire [15:0] _U1478_out; wire [15:0] _U1479_out; wire [15:0] _U1480_out; wire [15:0] _U1482_out; wire [15:0] _U1483_out; -wire [15:0] _U1484_out; wire [15:0] _U1485_out; wire [15:0] _U1486_out; -wire [15:0] _U1488_out; +wire [15:0] _U1487_out; wire [15:0] _U1489_out; wire [15:0] _U1490_out; wire [15:0] _U1491_out; -wire [15:0] _U1492_out; +wire [15:0] _U1493_out; wire [15:0] _U1494_out; wire [15:0] _U1495_out; wire [15:0] _U1496_out; -wire [15:0] _U1497_out; wire [15:0] _U1498_out; wire [15:0] _U1499_out; +wire [15:0] _U1500_out; wire [15:0] _U1501_out; -wire [15:0] _U1502_out; wire [15:0] _U1503_out; wire [15:0] _U1504_out; wire [15:0] _U1505_out; wire [15:0] _U1506_out; -wire [15:0] _U1508_out; +wire [15:0] _U1507_out; wire [15:0] _U1509_out; wire [15:0] _U1510_out; wire [15:0] _U1511_out; wire [15:0] _U1512_out; wire [15:0] _U1513_out; -wire [15:0] _U1514_out; +wire [15:0] _U1515_out; wire [15:0] _U1516_out; wire [15:0] _U1517_out; wire [15:0] _U1518_out; wire [15:0] _U1519_out; wire [15:0] _U1520_out; -wire [15:0] _U1521_out; wire [15:0] _U1522_out; +wire [15:0] _U1523_out; wire [15:0] _U1524_out; wire [15:0] _U1525_out; +wire [15:0] _U1526_out; wire [15:0] _U1527_out; -wire [15:0] _U1528_out; wire [15:0] _U1529_out; wire [15:0] _U1530_out; wire [15:0] _U1531_out; -wire [15:0] _U1532_out; wire [15:0] _U1533_out; wire [15:0] _U1534_out; -wire [15:0] _U1535_out; wire [15:0] _U1536_out; wire [15:0] _U1537_out; wire [15:0] _U1538_out; wire [15:0] _U1539_out; wire [15:0] _U1540_out; wire [15:0] _U1541_out; +wire [15:0] _U1542_out; wire [15:0] _U1543_out; +wire [15:0] _U1544_out; wire [15:0] _U1545_out; +wire [15:0] _U1546_out; wire [15:0] _U1547_out; wire [15:0] _U1548_out; +wire [15:0] _U1549_out; wire [15:0] _U1550_out; -wire [15:0] _U1551_out; wire [15:0] _U1552_out; -wire [15:0] _U1553_out; wire [15:0] _U1554_out; wire [15:0] _U1555_out; -wire [15:0] _U1556_out; +wire [15:0] _U1557_out; wire [15:0] _U1558_out; wire [15:0] _U1559_out; +wire [15:0] _U1560_out; wire [15:0] _U1561_out; wire [15:0] _U1562_out; wire [15:0] _U1563_out; -wire [15:0] _U1564_out; wire [15:0] _U1565_out; -wire [15:0] _U1567_out; +wire [15:0] _U1566_out; wire [15:0] _U1568_out; +wire [15:0] _U1569_out; wire [15:0] _U1570_out; wire [15:0] _U1571_out; wire [15:0] _U1572_out; wire [15:0] _U1574_out; wire [15:0] _U1575_out; -wire [15:0] _U1576_out; wire [15:0] _U1577_out; wire [15:0] _U1578_out; wire [15:0] _U1579_out; @@ -19520,11 +19526,11 @@ wire [15:0] _U1586_out; wire [15:0] _U1587_out; wire [15:0] _U1588_out; wire [15:0] _U1589_out; +wire [15:0] _U1590_out; wire [15:0] _U1591_out; +wire [15:0] _U1592_out; wire [15:0] _U1594_out; -wire [15:0] _U1596_out; wire [15:0] _U1597_out; -wire [15:0] _U1598_out; wire [15:0] _U1599_out; wire [15:0] _U1600_out; wire [15:0] _U1601_out; @@ -19535,13 +19541,13 @@ wire [15:0] _U1605_out; wire [15:0] _U1606_out; wire [15:0] _U1607_out; wire [15:0] _U1608_out; +wire [15:0] _U1609_out; wire [15:0] _U1610_out; wire [15:0] _U1611_out; wire [15:0] _U1613_out; wire [15:0] _U1614_out; wire [15:0] _U1616_out; wire [15:0] _U1617_out; -wire [15:0] _U1618_out; wire [15:0] _U1619_out; wire [15:0] _U1620_out; wire [15:0] _U1621_out; @@ -19550,17 +19556,18 @@ wire [15:0] _U1623_out; wire [15:0] _U1624_out; wire [15:0] _U1625_out; wire [15:0] _U1626_out; +wire [15:0] _U1627_out; wire [15:0] _U1628_out; wire [15:0] _U1629_out; wire [15:0] _U1631_out; wire [15:0] _U1632_out; -wire [15:0] _U1633_out; wire [15:0] _U1634_out; wire [15:0] _U1635_out; wire [15:0] _U1636_out; wire [15:0] _U1637_out; wire [15:0] _U1638_out; wire [15:0] _U1639_out; +wire [15:0] _U1640_out; wire [15:0] _U1641_out; wire [15:0] add_1187_1201_1202_out; wire [15:0] add_1188_1199_1200_out; @@ -19579,13 +19586,13 @@ wire [15:0] mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_sten wire [15:0] mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193_out; wire [15:0] mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194_out; _U1441_pt__U1442 _U1441 ( - .in(_U1449_out), + .in(_U1448_out), .out(_U1441_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1443 ( - .in(in2_hw_kernel_global_wrapper_stencil[7]), + .in(in2_hw_kernel_global_wrapper_stencil[6]), .clk(clk), .out(_U1443_out) ); @@ -19624,21 +19631,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1448_out) ); +_U1449_pt__U1450 _U1449 ( + .in(_U1456_out), + .out(_U1449_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1449 ( - .in(_U1448_out), +) _U1451 ( + .in(in1_hw_input_global_wrapper_stencil[6]), .clk(clk), - .out(_U1449_out) -); -_U1450_pt__U1451 _U1450 ( - .in(_U1458_out), - .out(_U1450_out) + .out(_U1451_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1452 ( - .in(in1_hw_input_global_wrapper_stencil[7]), + .in(_U1451_out), .clk(clk), .out(_U1452_out) ); @@ -19670,39 +19677,49 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1456_out) ); +_U1457_pt__U1458 _U1457 ( + .in(_U1465_out), + .out(_U1457_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1457 ( - .in(_U1456_out), +) _U1459 ( + .in(in2_hw_kernel_global_wrapper_stencil[7]), .clk(clk), - .out(_U1457_out) + .out(_U1459_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1458 ( - .in(_U1457_out), +) _U1460 ( + .in(_U1459_out), .clk(clk), - .out(_U1458_out) -); -_U1459_pt__U1460 _U1459 ( - .in(_U1461_out), - .out(_U1459_out) + .out(_U1460_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1461 ( - .in(in1_hw_input_global_wrapper_stencil[1]), + .in(_U1460_out), .clk(clk), .out(_U1461_out) ); -_U1462_pt__U1463 _U1462 ( - .in(_U1465_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1462 ( + .in(_U1461_out), + .clk(clk), .out(_U1462_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1463 ( + .in(_U1462_out), + .clk(clk), + .out(_U1463_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1464 ( - .in(in2_hw_kernel_global_wrapper_stencil[2]), + .in(_U1463_out), .clk(clk), .out(_U1464_out) ); @@ -19714,13 +19731,13 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U1465_out) ); _U1466_pt__U1467 _U1466 ( - .in(_U1469_out), + .in(_U1474_out), .out(_U1466_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1468 ( - .in(in1_hw_input_global_wrapper_stencil[2]), + .in(in1_hw_input_global_wrapper_stencil[7]), .clk(clk), .out(_U1468_out) ); @@ -19731,14 +19748,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1469_out) ); -_U1470_pt__U1471 _U1470 ( - .in(_U1474_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1470 ( + .in(_U1469_out), + .clk(clk), .out(_U1470_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1471 ( + .in(_U1470_out), + .clk(clk), + .out(_U1471_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1472 ( - .in(in2_hw_kernel_global_wrapper_stencil[3]), + .in(_U1471_out), .clk(clk), .out(_U1472_out) ); @@ -19757,77 +19784,57 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U1474_out) ); _U1475_pt__U1476 _U1475 ( - .in(_U1479_out), + .in(in1_hw_input_global_wrapper_stencil[0]), .out(_U1475_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1477 ( - .in(in1_hw_input_global_wrapper_stencil[3]), - .clk(clk), +_U1477_pt__U1478 _U1477 ( + .in(_U1479_out), .out(_U1477_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1478 ( - .in(_U1477_out), - .clk(clk), - .out(_U1478_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1479 ( - .in(_U1478_out), + .in(in2_hw_kernel_global_wrapper_stencil[1]), .clk(clk), .out(_U1479_out) ); _U1480_pt__U1481 _U1480 ( - .in(_U1485_out), + .in(_U1482_out), .out(_U1480_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1482 ( - .in(in2_hw_kernel_global_wrapper_stencil[4]), + .in(in1_hw_input_global_wrapper_stencil[1]), .clk(clk), .out(_U1482_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1483 ( - .in(_U1482_out), - .clk(clk), +_U1483_pt__U1484 _U1483 ( + .in(_U1486_out), .out(_U1483_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1484 ( - .in(_U1483_out), - .clk(clk), - .out(_U1484_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1485 ( - .in(_U1484_out), + .in(in2_hw_kernel_global_wrapper_stencil[2]), .clk(clk), .out(_U1485_out) ); -_U1486_pt__U1487 _U1486 ( - .in(_U1491_out), - .out(_U1486_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1488 ( - .in(in1_hw_input_global_wrapper_stencil[4]), +) _U1486 ( + .in(_U1485_out), .clk(clk), - .out(_U1488_out) + .out(_U1486_out) +); +_U1487_pt__U1488 _U1487 ( + .in(_U1490_out), + .out(_U1487_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1489 ( - .in(_U1488_out), + .in(in1_hw_input_global_wrapper_stencil[2]), .clk(clk), .out(_U1489_out) ); @@ -19838,21 +19845,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1490_out) ); +_U1491_pt__U1492 _U1491 ( + .in(_U1495_out), + .out(_U1491_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1491 ( - .in(_U1490_out), +) _U1493 ( + .in(in2_hw_kernel_global_wrapper_stencil[3]), .clk(clk), - .out(_U1491_out) -); -_U1492_pt__U1493 _U1492 ( - .in(_U1498_out), - .out(_U1492_out) + .out(_U1493_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1494 ( - .in(in2_hw_kernel_global_wrapper_stencil[5]), + .in(_U1493_out), .clk(clk), .out(_U1494_out) ); @@ -19863,49 +19870,39 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1495_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1496 ( - .in(_U1495_out), - .clk(clk), +_U1496_pt__U1497 _U1496 ( + .in(_U1500_out), .out(_U1496_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1497 ( - .in(_U1496_out), - .clk(clk), - .out(_U1497_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1498 ( - .in(_U1497_out), + .in(in1_hw_input_global_wrapper_stencil[3]), .clk(clk), .out(_U1498_out) ); -_U1499_pt__U1500 _U1499 ( - .in(_U1505_out), - .out(_U1499_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1501 ( - .in(in1_hw_input_global_wrapper_stencil[5]), +) _U1499 ( + .in(_U1498_out), .clk(clk), - .out(_U1501_out) + .out(_U1499_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1502 ( - .in(_U1501_out), +) _U1500 ( + .in(_U1499_out), .clk(clk), - .out(_U1502_out) + .out(_U1500_out) +); +_U1501_pt__U1502 _U1501 ( + .in(_U1506_out), + .out(_U1501_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1503 ( - .in(_U1502_out), + .in(in2_hw_kernel_global_wrapper_stencil[4]), .clk(clk), .out(_U1503_out) ); @@ -19923,21 +19920,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1505_out) ); -_U1506_pt__U1507 _U1506 ( - .in(_U1513_out), - .out(_U1506_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1508 ( - .in(in2_hw_kernel_global_wrapper_stencil[6]), +) _U1506 ( + .in(_U1505_out), .clk(clk), - .out(_U1508_out) + .out(_U1506_out) +); +_U1507_pt__U1508 _U1507 ( + .in(_U1512_out), + .out(_U1507_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1509 ( - .in(_U1508_out), + .in(in1_hw_input_global_wrapper_stencil[4]), .clk(clk), .out(_U1509_out) ); @@ -19962,21 +19959,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1512_out) ); +_U1513_pt__U1514 _U1513 ( + .in(_U1519_out), + .out(_U1513_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1513 ( - .in(_U1512_out), +) _U1515 ( + .in(in2_hw_kernel_global_wrapper_stencil[5]), .clk(clk), - .out(_U1513_out) -); -_U1514_pt__U1515 _U1514 ( - .in(_U1521_out), - .out(_U1514_out) + .out(_U1515_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1516 ( - .in(in1_hw_input_global_wrapper_stencil[6]), + .in(_U1515_out), .clk(clk), .out(_U1516_out) ); @@ -20001,53 +19998,53 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1519_out) ); +_U1520_pt__U1521 _U1520 ( + .in(_U1526_out), + .out(_U1520_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1520 ( - .in(_U1519_out), +) _U1522 ( + .in(in1_hw_input_global_wrapper_stencil[5]), .clk(clk), - .out(_U1520_out) + .out(_U1522_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1521 ( - .in(_U1520_out), +) _U1523 ( + .in(_U1522_out), .clk(clk), - .out(_U1521_out) -); -_U1522_pt__U1523 _U1522 ( - .in(_U1524_out), - .out(_U1522_out) + .out(_U1523_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1524 ( - .in(mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194_out), + .in(_U1523_out), .clk(clk), .out(_U1524_out) ); -_U1525_pt__U1526 _U1525 ( - .in(_U1540_out), - .out(_U1525_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1527 ( - .in(in0_conv_stencil[0]), +) _U1525 ( + .in(_U1524_out), .clk(clk), - .out(_U1527_out) + .out(_U1525_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1528 ( - .in(_U1527_out), +) _U1526 ( + .in(_U1525_out), .clk(clk), - .out(_U1528_out) + .out(_U1526_out) +); +_U1527_pt__U1528 _U1527 ( + .in(_U1530_out), + .out(_U1527_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1529 ( - .in(_U1528_out), + .in(mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193_out), .clk(clk), .out(_U1529_out) ); @@ -20058,45 +20055,25 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1530_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1531 ( - .in(_U1530_out), - .clk(clk), +_U1531_pt__U1532 _U1531 ( + .in(_U1533_out), .out(_U1531_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1532 ( - .in(_U1531_out), - .clk(clk), - .out(_U1532_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1533 ( - .in(_U1532_out), + .in(mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194_out), .clk(clk), .out(_U1533_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1534 ( - .in(_U1533_out), - .clk(clk), +_U1534_pt__U1535 _U1534 ( + .in(_U1549_out), .out(_U1534_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1535 ( - .in(_U1534_out), - .clk(clk), - .out(_U1535_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1536 ( - .in(_U1535_out), + .in(in0_conv_stencil[0]), .clk(clk), .out(_U1536_out) ); @@ -20128,90 +20105,120 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1540_out) ); -_U1541_pt__U1542 _U1541 ( - .in(in2_hw_kernel_global_wrapper_stencil[0]), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1541 ( + .in(_U1540_out), + .clk(clk), .out(_U1541_out) ); -_U1543_pt__U1544 _U1543 ( - .in(in1_hw_input_global_wrapper_stencil[0]), - .out(_U1543_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1542 ( + .in(_U1541_out), + .clk(clk), + .out(_U1542_out) ); -_U1545_pt__U1546 _U1545 ( - .in(_U1547_out), - .out(_U1545_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1543 ( + .in(_U1542_out), + .clk(clk), + .out(_U1543_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1547 ( - .in(in2_hw_kernel_global_wrapper_stencil[1]), +) _U1544 ( + .in(_U1543_out), .clk(clk), - .out(_U1547_out) + .out(_U1544_out) ); -_U1548_pt__U1549 _U1548 ( - .in(_U1555_out), - .out(_U1548_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1545 ( + .in(_U1544_out), + .clk(clk), + .out(_U1545_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1550 ( - .in(mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191_out), +) _U1546 ( + .in(_U1545_out), .clk(clk), - .out(_U1550_out) + .out(_U1546_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1551 ( - .in(_U1550_out), +) _U1547 ( + .in(_U1546_out), .clk(clk), - .out(_U1551_out) + .out(_U1547_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1552 ( - .in(_U1551_out), +) _U1548 ( + .in(_U1547_out), .clk(clk), - .out(_U1552_out) + .out(_U1548_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1553 ( - .in(_U1552_out), +) _U1549 ( + .in(_U1548_out), .clk(clk), - .out(_U1553_out) + .out(_U1549_out) +); +_U1550_pt__U1551 _U1550 ( + .in(in2_hw_kernel_global_wrapper_stencil[0]), + .out(_U1550_out) +); +_U1552_pt__U1553 _U1552 ( + .in(_U1554_out), + .out(_U1552_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1554 ( - .in(_U1553_out), + .in(add_1191_1196_1197_out), .clk(clk), .out(_U1554_out) ); +_U1555_pt__U1556 _U1555 ( + .in(_U1562_out), + .out(_U1555_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1555 ( - .in(_U1554_out), +) _U1557 ( + .in(mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191_out), .clk(clk), - .out(_U1555_out) -); -_U1556_pt__U1557 _U1556 ( - .in(_U1558_out), - .out(_U1556_out) + .out(_U1557_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1558 ( - .in(add_1192_1195_1196_out), + .in(_U1557_out), .clk(clk), .out(_U1558_out) ); -_U1559_pt__U1560 _U1559 ( - .in(_U1564_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1559 ( + .in(_U1558_out), + .clk(clk), .out(_U1559_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1560 ( + .in(_U1559_out), + .clk(clk), + .out(_U1560_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1561 ( - .in(mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192_out), + .in(_U1560_out), .clk(clk), .out(_U1561_out) ); @@ -20222,39 +20229,39 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1562_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1563 ( - .in(_U1562_out), - .clk(clk), +_U1563_pt__U1564 _U1563 ( + .in(_U1565_out), .out(_U1563_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1564 ( - .in(_U1563_out), +) _U1565 ( + .in(add_1192_1195_1196_out), .clk(clk), - .out(_U1564_out) -); -_U1565_pt__U1566 _U1565 ( - .in(_U1567_out), .out(_U1565_out) ); +_U1566_pt__U1567 _U1566 ( + .in(_U1571_out), + .out(_U1566_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1567 ( - .in(add_1193_1194_1195_out), +) _U1568 ( + .in(mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192_out), .clk(clk), - .out(_U1567_out) -); -_U1568_pt__U1569 _U1568 ( - .in(_U1571_out), .out(_U1568_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1569 ( + .in(_U1568_out), + .clk(clk), + .out(_U1569_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1570 ( - .in(mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193_out), + .in(_U1569_out), .clk(clk), .out(_U1570_out) ); @@ -20266,34 +20273,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U1571_out) ); _U1572_pt__U1573 _U1572 ( - .in(_U1588_out), + .in(_U1574_out), .out(_U1572_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1574 ( - .in(mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187_out), + .in(add_1193_1194_1195_out), .clk(clk), .out(_U1574_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1575 ( - .in(_U1574_out), - .clk(clk), +_U1575_pt__U1576 _U1575 ( + .in(_U1591_out), .out(_U1575_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1576 ( - .in(_U1575_out), - .clk(clk), - .out(_U1576_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1577 ( - .in(_U1576_out), + .in(mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187_out), .clk(clk), .out(_U1577_out) ); @@ -20374,50 +20371,50 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1588_out) ); -_U1589_pt__U1590 _U1589 ( - .in(_U1591_out), - .out(_U1589_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1591 ( - .in(add_conv_stencil_8_1200_1201_out), +) _U1589 ( + .in(_U1588_out), .clk(clk), - .out(_U1591_out) -); -_U1592_pt__U1593 _U1592 ( - .in(add_1187_1201_1202_out), - .out(out_conv_stencil) -); -_U1594_pt__U1595 _U1594 ( - .in(_U1607_out), - .out(_U1594_out) + .out(_U1589_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1596 ( - .in(mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188_out), +) _U1590 ( + .in(_U1589_out), .clk(clk), - .out(_U1596_out) + .out(_U1590_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1597 ( - .in(_U1596_out), +) _U1591 ( + .in(_U1590_out), .clk(clk), - .out(_U1597_out) + .out(_U1591_out) +); +_U1592_pt__U1593 _U1592 ( + .in(_U1594_out), + .out(_U1592_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1598 ( - .in(_U1597_out), +) _U1594 ( + .in(add_conv_stencil_8_1200_1201_out), .clk(clk), - .out(_U1598_out) + .out(_U1594_out) +); +_U1595_pt__U1596 _U1595 ( + .in(add_1187_1201_1202_out), + .out(out_conv_stencil) +); +_U1597_pt__U1598 _U1597 ( + .in(_U1610_out), + .out(_U1597_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1599 ( - .in(_U1598_out), + .in(mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188_out), .clk(clk), .out(_U1599_out) ); @@ -20477,14 +20474,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1607_out) ); -_U1608_pt__U1609 _U1608 ( - .in(_U1610_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1608 ( + .in(_U1607_out), + .clk(clk), .out(_U1608_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1609 ( + .in(_U1608_out), + .clk(clk), + .out(_U1609_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1610 ( - .in(add_1189_1198_1199_out), + .in(_U1609_out), .clk(clk), .out(_U1610_out) ); @@ -20495,39 +20502,29 @@ _U1611_pt__U1612 _U1611 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1613 ( - .in(add_1188_1199_1200_out), + .in(add_1189_1198_1199_out), .clk(clk), .out(_U1613_out) ); _U1614_pt__U1615 _U1614 ( - .in(_U1625_out), + .in(_U1616_out), .out(_U1614_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1616 ( - .in(mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189_out), + .in(add_1188_1199_1200_out), .clk(clk), .out(_U1616_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1617 ( - .in(_U1616_out), - .clk(clk), +_U1617_pt__U1618 _U1617 ( + .in(_U1628_out), .out(_U1617_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1618 ( - .in(_U1617_out), - .clk(clk), - .out(_U1618_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1619 ( - .in(_U1618_out), + .in(mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189_out), .clk(clk), .out(_U1619_out) ); @@ -20573,46 +20570,46 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1625_out) ); -_U1626_pt__U1627 _U1626 ( - .in(_U1628_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1626 ( + .in(_U1625_out), + .clk(clk), .out(_U1626_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1627 ( + .in(_U1626_out), + .clk(clk), + .out(_U1627_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1628 ( - .in(add_1190_1197_1198_out), + .in(_U1627_out), .clk(clk), .out(_U1628_out) ); _U1629_pt__U1630 _U1629 ( - .in(_U1638_out), + .in(_U1631_out), .out(_U1629_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1631 ( - .in(mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190_out), + .in(add_1190_1197_1198_out), .clk(clk), .out(_U1631_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1632 ( - .in(_U1631_out), - .clk(clk), +_U1632_pt__U1633 _U1632 ( + .in(_U1641_out), .out(_U1632_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1633 ( - .in(_U1632_out), - .clk(clk), - .out(_U1633_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1634 ( - .in(_U1633_out), + .in(mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190_out), .clk(clk), .out(_U1634_out) ); @@ -20644,33 +20641,43 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1638_out) ); -_U1639_pt__U1640 _U1639 ( - .in(_U1641_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1639 ( + .in(_U1638_out), + .clk(clk), .out(_U1639_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1640 ( + .in(_U1639_out), + .clk(clk), + .out(_U1640_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1641 ( - .in(add_1191_1196_1197_out), + .in(_U1640_out), .clk(clk), .out(_U1641_out) ); -assign add_1187_1201_1202_out = 16'(_U1572_out + _U1589_out); -assign add_1188_1199_1200_out = 16'(_U1594_out + _U1608_out); -assign add_1189_1198_1199_out = 16'(_U1614_out + _U1626_out); -assign add_1190_1197_1198_out = 16'(_U1629_out + _U1639_out); -assign add_1191_1196_1197_out = 16'(_U1548_out + _U1556_out); -assign add_1192_1195_1196_out = 16'(_U1559_out + _U1565_out); -assign add_1193_1194_1195_out = 16'(_U1568_out + _U1522_out); -assign add_conv_stencil_8_1200_1201_out = 16'(_U1525_out + _U1611_out); -assign mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187_out = 16'(_U1541_out * _U1543_out); -assign mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188_out = 16'(_U1545_out * _U1459_out); -assign mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189_out = 16'(_U1462_out * _U1466_out); -assign mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190_out = 16'(_U1470_out * _U1475_out); -assign mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191_out = 16'(_U1480_out * _U1486_out); -assign mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192_out = 16'(_U1492_out * _U1499_out); -assign mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193_out = 16'(_U1506_out * _U1514_out); -assign mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194_out = 16'(_U1441_out * _U1450_out); +assign add_1187_1201_1202_out = 16'(_U1575_out + _U1592_out); +assign add_1188_1199_1200_out = 16'(_U1597_out + _U1611_out); +assign add_1189_1198_1199_out = 16'(_U1617_out + _U1629_out); +assign add_1190_1197_1198_out = 16'(_U1632_out + _U1552_out); +assign add_1191_1196_1197_out = 16'(_U1555_out + _U1563_out); +assign add_1192_1195_1196_out = 16'(_U1566_out + _U1572_out); +assign add_1193_1194_1195_out = 16'(_U1527_out + _U1531_out); +assign add_conv_stencil_8_1200_1201_out = 16'(_U1534_out + _U1614_out); +assign mul_hw_kernel_global_wrapper_stencil_57_hw_input_global_wrapper_stencil_57_1187_out = 16'(_U1550_out * _U1475_out); +assign mul_hw_kernel_global_wrapper_stencil_58_hw_input_global_wrapper_stencil_58_1188_out = 16'(_U1477_out * _U1480_out); +assign mul_hw_kernel_global_wrapper_stencil_59_hw_input_global_wrapper_stencil_59_1189_out = 16'(_U1483_out * _U1487_out); +assign mul_hw_kernel_global_wrapper_stencil_60_hw_input_global_wrapper_stencil_60_1190_out = 16'(_U1491_out * _U1496_out); +assign mul_hw_kernel_global_wrapper_stencil_61_hw_input_global_wrapper_stencil_61_1191_out = 16'(_U1501_out * _U1507_out); +assign mul_hw_kernel_global_wrapper_stencil_62_hw_input_global_wrapper_stencil_62_1192_out = 16'(_U1513_out * _U1520_out); +assign mul_hw_kernel_global_wrapper_stencil_63_hw_input_global_wrapper_stencil_63_1193_out = 16'(_U1441_out * _U1449_out); +assign mul_hw_kernel_global_wrapper_stencil_64_hw_input_global_wrapper_stencil_64_1194_out = 16'(_U1457_out * _U1466_out); endmodule module cu_op_hcompute_conv_stencil_15 ( @@ -20711,70 +20718,77 @@ hcompute_conv_stencil_15_pipelined inner_compute ( assign conv_stencil_op_hcompute_conv_stencil_15_write[0] = inner_compute_out_conv_stencil; endmodule -module _U1425_pt__U1426 ( +module _U1438_pt__U1439 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1422_pt__U1423 ( +module _U1434_pt__U1435 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U141_pt__U142 ( +module _U1431_pt__U1432 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1418_pt__U1419 ( +module _U1429_pt__U1430 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1415_pt__U1416 ( +module _U1426_pt__U1427 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1401_pt__U1402 ( +module _U1409_pt__U1410 ( + input [15:0] in, + output [15:0] out +); +assign out = in; +endmodule + +module _U1405_pt__U1406 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1399_pt__U1400 ( +module _U1401_pt__U1402 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1394_pt__U1395 ( +module _U139_pt__U140 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U138_pt__U139 ( +module _U1398_pt__U1399 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1389_pt__U1390 ( +module _U1388_pt__U1389 ( input [15:0] in, output [15:0] out ); @@ -20788,42 +20802,42 @@ module _U1385_pt__U1386 ( assign out = in; endmodule -module _U1381_pt__U1382 ( +module _U137_pt__U138 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1373_pt__U1374 ( +module _U1378_pt__U1379 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1370_pt__U1371 ( +module _U1372_pt__U1373 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U136_pt__U137 ( +module _U1366_pt__U1367 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1360_pt__U1361 ( +module _U1361_pt__U1362 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1353_pt__U1354 ( +module _U1356_pt__U1357 ( input [15:0] in, output [15:0] out ); @@ -20837,49 +20851,49 @@ module _U134_pt__U135 ( assign out = in; endmodule -module _U1346_pt__U1347 ( +module _U1344_pt__U1345 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1340_pt__U1341 ( +module _U1341_pt__U1342 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1334_pt__U1335 ( +module _U1338_pt__U1339 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1331_pt__U1332 ( +module _U1324_pt__U1325 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1319_pt__U1320 ( +module _U131_pt__U132 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1316_pt__U1317 ( +module _U1315_pt__U1316 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1313_pt__U1314 ( +module _U1307_pt__U1308 ( input [15:0] in, output [15:0] out ); @@ -20893,7 +20907,7 @@ module _U12_pt__U13 ( assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_6_pipelined ( +module hcompute_hw_input_global_wrapper_stencil_pipelined ( output [15:0] out_hw_input_global_wrapper_stencil, input [15:0] in0_hw_input_stencil [0:0] ); @@ -20903,92 +20917,99 @@ _U12_pt__U13 _U12 ( ); endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil_6 ( +module cu_op_hcompute_hw_input_global_wrapper_stencil ( input clk, - input [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write [0:0] + input [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write [0:0] ); wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read[0]; -hcompute_hw_input_global_wrapper_stencil_6_pipelined inner_compute ( +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read[0]; +hcompute_hw_input_global_wrapper_stencil_pipelined inner_compute ( .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) ); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +endmodule + +module _U129_pt__U130 ( + input [15:0] in, + output [15:0] out +); +assign out = in; endmodule -module _U1296_pt__U1297 ( +module _U1299_pt__U1300 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1287_pt__U1288 ( +module _U1292_pt__U1293 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1278_pt__U1279 ( +module _U1283_pt__U1284 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1270_pt__U1271 ( +module _U127_pt__U128 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1262_pt__U1263 ( +module _U1277_pt__U1278 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1259_pt__U1260 ( +module _U1274_pt__U1275 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1253_pt__U1254 ( +module _U1266_pt__U1267 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1250_pt__U1251 ( +module _U1263_pt__U1264 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1247_pt__U1248 ( +module _U1260_pt__U1261 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1244_pt__U1245 ( +module _U1258_pt__U1259 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1242_pt__U1243 ( +module _U1256_pt__U1257 ( input [15:0] in, output [15:0] out ); @@ -21011,53 +21032,54 @@ module hcompute_conv_stencil_14_pipelined ( ); wire [15:0] _U1240_out; wire [15:0] _U1242_out; +wire [15:0] _U1243_out; wire [15:0] _U1244_out; +wire [15:0] _U1245_out; wire [15:0] _U1246_out; wire [15:0] _U1247_out; +wire [15:0] _U1248_out; wire [15:0] _U1249_out; wire [15:0] _U1250_out; +wire [15:0] _U1251_out; wire [15:0] _U1252_out; wire [15:0] _U1253_out; +wire [15:0] _U1254_out; wire [15:0] _U1255_out; wire [15:0] _U1256_out; -wire [15:0] _U1257_out; wire [15:0] _U1258_out; -wire [15:0] _U1259_out; -wire [15:0] _U1261_out; +wire [15:0] _U1260_out; wire [15:0] _U1262_out; -wire [15:0] _U1264_out; +wire [15:0] _U1263_out; wire [15:0] _U1265_out; wire [15:0] _U1266_out; -wire [15:0] _U1267_out; wire [15:0] _U1268_out; wire [15:0] _U1269_out; wire [15:0] _U1270_out; +wire [15:0] _U1271_out; wire [15:0] _U1272_out; wire [15:0] _U1273_out; wire [15:0] _U1274_out; -wire [15:0] _U1275_out; wire [15:0] _U1276_out; wire [15:0] _U1277_out; -wire [15:0] _U1278_out; +wire [15:0] _U1279_out; wire [15:0] _U1280_out; wire [15:0] _U1281_out; wire [15:0] _U1282_out; wire [15:0] _U1283_out; -wire [15:0] _U1284_out; wire [15:0] _U1285_out; wire [15:0] _U1286_out; wire [15:0] _U1287_out; +wire [15:0] _U1288_out; wire [15:0] _U1289_out; wire [15:0] _U1290_out; wire [15:0] _U1291_out; wire [15:0] _U1292_out; -wire [15:0] _U1293_out; wire [15:0] _U1294_out; wire [15:0] _U1295_out; wire [15:0] _U1296_out; +wire [15:0] _U1297_out; wire [15:0] _U1298_out; wire [15:0] _U1299_out; -wire [15:0] _U1300_out; wire [15:0] _U1301_out; wire [15:0] _U1302_out; wire [15:0] _U1303_out; @@ -21065,116 +21087,115 @@ wire [15:0] _U1304_out; wire [15:0] _U1305_out; wire [15:0] _U1306_out; wire [15:0] _U1307_out; -wire [15:0] _U1308_out; wire [15:0] _U1309_out; wire [15:0] _U1310_out; wire [15:0] _U1311_out; wire [15:0] _U1312_out; wire [15:0] _U1313_out; +wire [15:0] _U1314_out; wire [15:0] _U1315_out; -wire [15:0] _U1316_out; +wire [15:0] _U1317_out; wire [15:0] _U1318_out; wire [15:0] _U1319_out; +wire [15:0] _U1320_out; wire [15:0] _U1321_out; wire [15:0] _U1322_out; wire [15:0] _U1323_out; wire [15:0] _U1324_out; -wire [15:0] _U1325_out; wire [15:0] _U1326_out; wire [15:0] _U1327_out; wire [15:0] _U1328_out; wire [15:0] _U1329_out; wire [15:0] _U1330_out; wire [15:0] _U1331_out; +wire [15:0] _U1332_out; wire [15:0] _U1333_out; wire [15:0] _U1334_out; +wire [15:0] _U1335_out; wire [15:0] _U1336_out; wire [15:0] _U1337_out; wire [15:0] _U1338_out; -wire [15:0] _U1339_out; wire [15:0] _U1340_out; -wire [15:0] _U1342_out; +wire [15:0] _U1341_out; wire [15:0] _U1343_out; wire [15:0] _U1344_out; -wire [15:0] _U1345_out; wire [15:0] _U1346_out; +wire [15:0] _U1347_out; wire [15:0] _U1348_out; wire [15:0] _U1349_out; wire [15:0] _U1350_out; wire [15:0] _U1351_out; wire [15:0] _U1352_out; wire [15:0] _U1353_out; +wire [15:0] _U1354_out; wire [15:0] _U1355_out; wire [15:0] _U1356_out; -wire [15:0] _U1357_out; wire [15:0] _U1358_out; wire [15:0] _U1359_out; wire [15:0] _U1360_out; -wire [15:0] _U1362_out; +wire [15:0] _U1361_out; wire [15:0] _U1363_out; wire [15:0] _U1364_out; wire [15:0] _U1365_out; wire [15:0] _U1366_out; -wire [15:0] _U1367_out; wire [15:0] _U1368_out; wire [15:0] _U1369_out; wire [15:0] _U1370_out; +wire [15:0] _U1371_out; wire [15:0] _U1372_out; -wire [15:0] _U1373_out; +wire [15:0] _U1374_out; wire [15:0] _U1375_out; wire [15:0] _U1376_out; wire [15:0] _U1377_out; wire [15:0] _U1378_out; -wire [15:0] _U1379_out; wire [15:0] _U1380_out; wire [15:0] _U1381_out; +wire [15:0] _U1382_out; wire [15:0] _U1383_out; wire [15:0] _U1384_out; wire [15:0] _U1385_out; wire [15:0] _U1387_out; wire [15:0] _U1388_out; -wire [15:0] _U1389_out; +wire [15:0] _U1390_out; wire [15:0] _U1391_out; wire [15:0] _U1392_out; wire [15:0] _U1393_out; wire [15:0] _U1394_out; +wire [15:0] _U1395_out; wire [15:0] _U1396_out; wire [15:0] _U1397_out; wire [15:0] _U1398_out; +wire [15:0] _U1400_out; wire [15:0] _U1401_out; wire [15:0] _U1403_out; wire [15:0] _U1404_out; wire [15:0] _U1405_out; -wire [15:0] _U1406_out; wire [15:0] _U1407_out; wire [15:0] _U1408_out; wire [15:0] _U1409_out; -wire [15:0] _U1410_out; wire [15:0] _U1411_out; wire [15:0] _U1412_out; wire [15:0] _U1413_out; wire [15:0] _U1414_out; wire [15:0] _U1415_out; +wire [15:0] _U1416_out; wire [15:0] _U1417_out; wire [15:0] _U1418_out; +wire [15:0] _U1419_out; wire [15:0] _U1420_out; wire [15:0] _U1421_out; wire [15:0] _U1422_out; +wire [15:0] _U1423_out; wire [15:0] _U1424_out; wire [15:0] _U1425_out; -wire [15:0] _U1427_out; +wire [15:0] _U1426_out; wire [15:0] _U1428_out; -wire [15:0] _U1429_out; -wire [15:0] _U1430_out; wire [15:0] _U1431_out; -wire [15:0] _U1432_out; wire [15:0] _U1433_out; wire [15:0] _U1434_out; -wire [15:0] _U1435_out; wire [15:0] _U1436_out; wire [15:0] _U1437_out; wire [15:0] _U1438_out; -wire [15:0] _U1439_out; wire [15:0] _U1440_out; wire [15:0] add_1120_1134_1135_out; wire [15:0] add_1121_1132_1133_out; @@ -21193,125 +21214,145 @@ wire [15:0] mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_sten wire [15:0] mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126_out; wire [15:0] mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127_out; _U1240_pt__U1241 _U1240 ( - .in(in2_hw_kernel_global_wrapper_stencil[0]), + .in(_U1255_out), .out(_U1240_out) ); -_U1242_pt__U1243 _U1242 ( - .in(in1_hw_input_global_wrapper_stencil[0]), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1242 ( + .in(in0_conv_stencil[0]), + .clk(clk), .out(_U1242_out) ); -_U1244_pt__U1245 _U1244 ( - .in(_U1246_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1243 ( + .in(_U1242_out), + .clk(clk), + .out(_U1243_out) +); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1244 ( + .in(_U1243_out), + .clk(clk), .out(_U1244_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1245 ( + .in(_U1244_out), + .clk(clk), + .out(_U1245_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1246 ( - .in(in2_hw_kernel_global_wrapper_stencil[1]), + .in(_U1245_out), .clk(clk), .out(_U1246_out) ); -_U1247_pt__U1248 _U1247 ( - .in(_U1249_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1247 ( + .in(_U1246_out), + .clk(clk), .out(_U1247_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1248 ( + .in(_U1247_out), + .clk(clk), + .out(_U1248_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1249 ( - .in(in1_hw_input_global_wrapper_stencil[1]), + .in(_U1248_out), .clk(clk), .out(_U1249_out) ); -_U1250_pt__U1251 _U1250 ( - .in(_U1252_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1250 ( + .in(_U1249_out), + .clk(clk), .out(_U1250_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1252 ( - .in(add_1125_1128_1129_out), +) _U1251 ( + .in(_U1250_out), .clk(clk), - .out(_U1252_out) -); -_U1253_pt__U1254 _U1253 ( - .in(_U1258_out), - .out(_U1253_out) + .out(_U1251_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1255 ( - .in(mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125_out), +) _U1252 ( + .in(_U1251_out), .clk(clk), - .out(_U1255_out) + .out(_U1252_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1256 ( - .in(_U1255_out), +) _U1253 ( + .in(_U1252_out), .clk(clk), - .out(_U1256_out) + .out(_U1253_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1257 ( - .in(_U1256_out), +) _U1254 ( + .in(_U1253_out), .clk(clk), - .out(_U1257_out) + .out(_U1254_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1258 ( - .in(_U1257_out), +) _U1255 ( + .in(_U1254_out), .clk(clk), + .out(_U1255_out) +); +_U1256_pt__U1257 _U1256 ( + .in(in2_hw_kernel_global_wrapper_stencil[0]), + .out(_U1256_out) +); +_U1258_pt__U1259 _U1258 ( + .in(in1_hw_input_global_wrapper_stencil[0]), .out(_U1258_out) ); -_U1259_pt__U1260 _U1259 ( - .in(_U1261_out), - .out(_U1259_out) +_U1260_pt__U1261 _U1260 ( + .in(_U1262_out), + .out(_U1260_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1261 ( - .in(add_1126_1127_1128_out), +) _U1262 ( + .in(in2_hw_kernel_global_wrapper_stencil[1]), .clk(clk), - .out(_U1261_out) -); -_U1262_pt__U1263 _U1262 ( - .in(_U1269_out), .out(_U1262_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1264 ( - .in(in2_hw_kernel_global_wrapper_stencil[6]), - .clk(clk), - .out(_U1264_out) +_U1263_pt__U1264 _U1263 ( + .in(_U1265_out), + .out(_U1263_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1265 ( - .in(_U1264_out), + .in(add_1124_1129_1130_out), .clk(clk), .out(_U1265_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1266 ( - .in(_U1265_out), - .clk(clk), +_U1266_pt__U1267 _U1266 ( + .in(_U1273_out), .out(_U1266_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1267 ( - .in(_U1266_out), - .clk(clk), - .out(_U1267_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1268 ( - .in(_U1267_out), + .in(mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124_out), .clk(clk), .out(_U1268_out) ); @@ -21322,14 +21363,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1269_out) ); -_U1270_pt__U1271 _U1270 ( - .in(_U1277_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1270 ( + .in(_U1269_out), + .clk(clk), .out(_U1270_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1271 ( + .in(_U1270_out), + .clk(clk), + .out(_U1271_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1272 ( - .in(in1_hw_input_global_wrapper_stencil[6]), + .in(_U1271_out), .clk(clk), .out(_U1272_out) ); @@ -21340,42 +21391,32 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1273_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1274 ( - .in(_U1273_out), - .clk(clk), +_U1274_pt__U1275 _U1274 ( + .in(_U1276_out), .out(_U1274_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1275 ( - .in(_U1274_out), - .clk(clk), - .out(_U1275_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1276 ( - .in(_U1275_out), + .in(add_1125_1128_1129_out), .clk(clk), .out(_U1276_out) ); +_U1277_pt__U1278 _U1277 ( + .in(_U1282_out), + .out(_U1277_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1277 ( - .in(_U1276_out), +) _U1279 ( + .in(mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125_out), .clk(clk), - .out(_U1277_out) -); -_U1278_pt__U1279 _U1278 ( - .in(_U1286_out), - .out(_U1278_out) + .out(_U1279_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1280 ( - .in(in2_hw_kernel_global_wrapper_stencil[7]), + .in(_U1279_out), .clk(clk), .out(_U1280_out) ); @@ -21393,24 +21434,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1282_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1283 ( - .in(_U1282_out), - .clk(clk), +_U1283_pt__U1284 _U1283 ( + .in(_U1291_out), .out(_U1283_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1284 ( - .in(_U1283_out), - .clk(clk), - .out(_U1284_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1285 ( - .in(_U1284_out), + .in(in1_hw_input_global_wrapper_stencil[7]), .clk(clk), .out(_U1285_out) ); @@ -21421,14 +21452,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1286_out) ); -_U1287_pt__U1288 _U1287 ( - .in(_U1295_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1287 ( + .in(_U1286_out), + .clk(clk), .out(_U1287_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1288 ( + .in(_U1287_out), + .clk(clk), + .out(_U1288_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1289 ( - .in(in1_hw_input_global_wrapper_stencil[7]), + .in(_U1288_out), .clk(clk), .out(_U1289_out) ); @@ -21446,24 +21487,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1291_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1292 ( - .in(_U1291_out), - .clk(clk), +_U1292_pt__U1293 _U1292 ( + .in(_U1298_out), .out(_U1292_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1293 ( - .in(_U1292_out), - .clk(clk), - .out(_U1293_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1294 ( - .in(_U1293_out), + .in(in1_hw_input_global_wrapper_stencil[5]), .clk(clk), .out(_U1294_out) ); @@ -21474,35 +21505,35 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1295_out) ); -_U1296_pt__U1297 _U1296 ( - .in(_U1312_out), - .out(_U1296_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1298 ( - .in(mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120_out), +) _U1296 ( + .in(_U1295_out), .clk(clk), - .out(_U1298_out) + .out(_U1296_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1299 ( - .in(_U1298_out), +) _U1297 ( + .in(_U1296_out), .clk(clk), - .out(_U1299_out) + .out(_U1297_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1300 ( - .in(_U1299_out), +) _U1298 ( + .in(_U1297_out), .clk(clk), - .out(_U1300_out) + .out(_U1298_out) +); +_U1299_pt__U1300 _U1299 ( + .in(_U1306_out), + .out(_U1299_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1301 ( - .in(_U1300_out), + .in(in2_hw_kernel_global_wrapper_stencil[6]), .clk(clk), .out(_U1301_out) ); @@ -21541,24 +21572,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1306_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1307 ( - .in(_U1306_out), - .clk(clk), +_U1307_pt__U1308 _U1307 ( + .in(_U1314_out), .out(_U1307_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1308 ( - .in(_U1307_out), - .clk(clk), - .out(_U1308_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1309 ( - .in(_U1308_out), + .in(in1_hw_input_global_wrapper_stencil[6]), .clk(clk), .out(_U1309_out) ); @@ -21583,36 +21604,56 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1312_out) ); -_U1313_pt__U1314 _U1313 ( - .in(_U1315_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1313 ( + .in(_U1312_out), + .clk(clk), .out(_U1313_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1315 ( - .in(add_conv_stencil_7_1133_1134_out), +) _U1314 ( + .in(_U1313_out), .clk(clk), + .out(_U1314_out) +); +_U1315_pt__U1316 _U1315 ( + .in(_U1323_out), .out(_U1315_out) ); -_U1316_pt__U1317 _U1316 ( - .in(_U1318_out), - .out(_U1316_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1317 ( + .in(in2_hw_kernel_global_wrapper_stencil[7]), + .clk(clk), + .out(_U1317_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1318 ( - .in(add_1121_1132_1133_out), + .in(_U1317_out), .clk(clk), .out(_U1318_out) ); -_U1319_pt__U1320 _U1319 ( - .in(_U1330_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1319 ( + .in(_U1318_out), + .clk(clk), .out(_U1319_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1320 ( + .in(_U1319_out), + .clk(clk), + .out(_U1320_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1321 ( - .in(mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122_out), + .in(_U1320_out), .clk(clk), .out(_U1321_out) ); @@ -21630,24 +21671,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1323_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1324 ( - .in(_U1323_out), - .clk(clk), +_U1324_pt__U1325 _U1324 ( + .in(_U1337_out), .out(_U1324_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1325 ( - .in(_U1324_out), - .clk(clk), - .out(_U1325_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1326 ( - .in(_U1325_out), + .in(mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121_out), .clk(clk), .out(_U1326_out) ); @@ -21679,25 +21710,45 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1330_out) ); -_U1331_pt__U1332 _U1331 ( - .in(_U1333_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1331 ( + .in(_U1330_out), + .clk(clk), .out(_U1331_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1332 ( + .in(_U1331_out), + .clk(clk), + .out(_U1332_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1333 ( - .in(add_1123_1130_1131_out), + .in(_U1332_out), .clk(clk), .out(_U1333_out) ); -_U1334_pt__U1335 _U1334 ( - .in(_U1339_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1334 ( + .in(_U1333_out), + .clk(clk), .out(_U1334_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1335 ( + .in(_U1334_out), + .clk(clk), + .out(_U1335_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1336 ( - .in(in2_hw_kernel_global_wrapper_stencil[4]), + .in(_U1335_out), .clk(clk), .out(_U1336_out) ); @@ -21708,60 +21759,50 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1337_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1338 ( - .in(_U1337_out), - .clk(clk), +_U1338_pt__U1339 _U1338 ( + .in(_U1340_out), .out(_U1338_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1339 ( - .in(_U1338_out), +) _U1340 ( + .in(add_1122_1131_1132_out), .clk(clk), - .out(_U1339_out) -); -_U1340_pt__U1341 _U1340 ( - .in(_U1345_out), .out(_U1340_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1342 ( - .in(in1_hw_input_global_wrapper_stencil[4]), - .clk(clk), - .out(_U1342_out) +_U1341_pt__U1342 _U1341 ( + .in(_U1343_out), + .out(_U1341_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1343 ( - .in(_U1342_out), + .in(add_1121_1132_1133_out), .clk(clk), .out(_U1343_out) ); +_U1344_pt__U1345 _U1344 ( + .in(_U1355_out), + .out(_U1344_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1344 ( - .in(_U1343_out), +) _U1346 ( + .in(mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122_out), .clk(clk), - .out(_U1344_out) + .out(_U1346_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1345 ( - .in(_U1344_out), +) _U1347 ( + .in(_U1346_out), .clk(clk), - .out(_U1345_out) -); -_U1346_pt__U1347 _U1346 ( - .in(_U1352_out), - .out(_U1346_out) + .out(_U1347_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1348 ( - .in(in2_hw_kernel_global_wrapper_stencil[5]), + .in(_U1347_out), .clk(clk), .out(_U1348_out) ); @@ -21793,35 +21834,35 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1352_out) ); -_U1353_pt__U1354 _U1353 ( - .in(_U1359_out), - .out(_U1353_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1355 ( - .in(in1_hw_input_global_wrapper_stencil[5]), +) _U1353 ( + .in(_U1352_out), .clk(clk), - .out(_U1355_out) + .out(_U1353_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1356 ( - .in(_U1355_out), +) _U1354 ( + .in(_U1353_out), .clk(clk), - .out(_U1356_out) + .out(_U1354_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1357 ( - .in(_U1356_out), +) _U1355 ( + .in(_U1354_out), .clk(clk), - .out(_U1357_out) + .out(_U1355_out) +); +_U1356_pt__U1357 _U1356 ( + .in(_U1360_out), + .out(_U1356_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1358 ( - .in(_U1357_out), + .in(in2_hw_kernel_global_wrapper_stencil[3]), .clk(clk), .out(_U1358_out) ); @@ -21832,21 +21873,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1359_out) ); -_U1360_pt__U1361 _U1360 ( - .in(_U1369_out), - .out(_U1360_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1362 ( - .in(mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123_out), +) _U1360 ( + .in(_U1359_out), .clk(clk), - .out(_U1362_out) + .out(_U1360_out) +); +_U1361_pt__U1362 _U1361 ( + .in(_U1365_out), + .out(_U1361_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1363 ( - .in(_U1362_out), + .in(in1_hw_input_global_wrapper_stencil[3]), .clk(clk), .out(_U1363_out) ); @@ -21864,24 +21905,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1365_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1366 ( - .in(_U1365_out), - .clk(clk), +_U1366_pt__U1367 _U1366 ( + .in(_U1371_out), .out(_U1366_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1367 ( - .in(_U1366_out), - .clk(clk), - .out(_U1367_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1368 ( - .in(_U1367_out), + .in(in2_hw_kernel_global_wrapper_stencil[4]), .clk(clk), .out(_U1368_out) ); @@ -21892,25 +21923,35 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1369_out) ); -_U1370_pt__U1371 _U1370 ( - .in(_U1372_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1370 ( + .in(_U1369_out), + .clk(clk), .out(_U1370_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1372 ( - .in(add_1124_1129_1130_out), +) _U1371 ( + .in(_U1370_out), .clk(clk), + .out(_U1371_out) +); +_U1372_pt__U1373 _U1372 ( + .in(_U1377_out), .out(_U1372_out) ); -_U1373_pt__U1374 _U1373 ( - .in(_U1380_out), - .out(_U1373_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1374 ( + .in(in1_hw_input_global_wrapper_stencil[4]), + .clk(clk), + .out(_U1374_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1375 ( - .in(mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124_out), + .in(_U1374_out), .clk(clk), .out(_U1375_out) ); @@ -21928,35 +21969,35 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1377_out) ); +_U1378_pt__U1379 _U1378 ( + .in(_U1384_out), + .out(_U1378_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1378 ( - .in(_U1377_out), +) _U1380 ( + .in(in2_hw_kernel_global_wrapper_stencil[5]), .clk(clk), - .out(_U1378_out) + .out(_U1380_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1379 ( - .in(_U1378_out), +) _U1381 ( + .in(_U1380_out), .clk(clk), - .out(_U1379_out) + .out(_U1381_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1380 ( - .in(_U1379_out), +) _U1382 ( + .in(_U1381_out), .clk(clk), - .out(_U1380_out) -); -_U1381_pt__U1382 _U1381 ( - .in(_U1384_out), - .out(_U1381_out) + .out(_U1382_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1383 ( - .in(in2_hw_kernel_global_wrapper_stencil[2]), + .in(_U1382_out), .clk(clk), .out(_U1383_out) ); @@ -21968,31 +22009,31 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U1384_out) ); _U1385_pt__U1386 _U1385 ( - .in(_U1388_out), + .in(_U1387_out), .out(_U1385_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1387 ( - .in(in1_hw_input_global_wrapper_stencil[2]), + .in(add_1123_1130_1131_out), .clk(clk), .out(_U1387_out) ); +_U1388_pt__U1389 _U1388 ( + .in(_U1397_out), + .out(_U1388_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1388 ( - .in(_U1387_out), +) _U1390 ( + .in(mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123_out), .clk(clk), - .out(_U1388_out) -); -_U1389_pt__U1390 _U1389 ( - .in(_U1393_out), - .out(_U1389_out) + .out(_U1390_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1391 ( - .in(in2_hw_kernel_global_wrapper_stencil[3]), + .in(_U1390_out), .clk(clk), .out(_U1391_out) ); @@ -22010,14 +22051,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1393_out) ); -_U1394_pt__U1395 _U1394 ( - .in(_U1398_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1394 ( + .in(_U1393_out), + .clk(clk), .out(_U1394_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1395 ( + .in(_U1394_out), + .clk(clk), + .out(_U1395_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1396 ( - .in(in1_hw_input_global_wrapper_stencil[3]), + .in(_U1395_out), .clk(clk), .out(_U1396_out) ); @@ -22028,25 +22079,25 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1397_out) ); +_U1398_pt__U1399 _U1398 ( + .in(_U1400_out), + .out(_U1398_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1398 ( - .in(_U1397_out), +) _U1400 ( + .in(in1_hw_input_global_wrapper_stencil[1]), .clk(clk), - .out(_U1398_out) -); -_U1399_pt__U1400 _U1399 ( - .in(add_1120_1134_1135_out), - .out(out_conv_stencil) + .out(_U1400_out) ); _U1401_pt__U1402 _U1401 ( - .in(_U1414_out), + .in(_U1404_out), .out(_U1401_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1403 ( - .in(mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121_out), + .in(in2_hw_kernel_global_wrapper_stencil[2]), .clk(clk), .out(_U1403_out) ); @@ -22057,24 +22108,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1404_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1405 ( - .in(_U1404_out), - .clk(clk), +_U1405_pt__U1406 _U1405 ( + .in(_U1408_out), .out(_U1405_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1406 ( - .in(_U1405_out), - .clk(clk), - .out(_U1406_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1407 ( - .in(_U1406_out), + .in(in1_hw_input_global_wrapper_stencil[2]), .clk(clk), .out(_U1407_out) ); @@ -22085,24 +22126,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1408_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1409 ( - .in(_U1408_out), - .clk(clk), +_U1409_pt__U1410 _U1409 ( + .in(_U1425_out), .out(_U1409_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1410 ( - .in(_U1409_out), - .clk(clk), - .out(_U1410_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1411 ( - .in(_U1410_out), + .in(mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120_out), .clk(clk), .out(_U1411_out) ); @@ -22127,25 +22158,45 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1414_out) ); -_U1415_pt__U1416 _U1415 ( - .in(_U1417_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1415 ( + .in(_U1414_out), + .clk(clk), .out(_U1415_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1416 ( + .in(_U1415_out), + .clk(clk), + .out(_U1416_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1417 ( - .in(add_1122_1131_1132_out), + .in(_U1416_out), .clk(clk), .out(_U1417_out) ); -_U1418_pt__U1419 _U1418 ( - .in(_U1421_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1418 ( + .in(_U1417_out), + .clk(clk), .out(_U1418_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1419 ( + .in(_U1418_out), + .clk(clk), + .out(_U1419_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1420 ( - .in(mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126_out), + .in(_U1419_out), .clk(clk), .out(_U1420_out) ); @@ -22156,88 +22207,68 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1421_out) ); -_U1422_pt__U1423 _U1422 ( - .in(_U1424_out), - .out(_U1422_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1424 ( - .in(mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127_out), +) _U1422 ( + .in(_U1421_out), .clk(clk), - .out(_U1424_out) -); -_U1425_pt__U1426 _U1425 ( - .in(_U1440_out), - .out(_U1425_out) + .out(_U1422_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1427 ( - .in(in0_conv_stencil[0]), +) _U1423 ( + .in(_U1422_out), .clk(clk), - .out(_U1427_out) + .out(_U1423_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1428 ( - .in(_U1427_out), +) _U1424 ( + .in(_U1423_out), .clk(clk), - .out(_U1428_out) + .out(_U1424_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1429 ( - .in(_U1428_out), +) _U1425 ( + .in(_U1424_out), .clk(clk), - .out(_U1429_out) + .out(_U1425_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1430 ( - .in(_U1429_out), - .clk(clk), - .out(_U1430_out) +_U1426_pt__U1427 _U1426 ( + .in(_U1428_out), + .out(_U1426_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1431 ( - .in(_U1430_out), +) _U1428 ( + .in(add_conv_stencil_7_1133_1134_out), .clk(clk), - .out(_U1431_out) + .out(_U1428_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1432 ( - .in(_U1431_out), - .clk(clk), - .out(_U1432_out) +_U1429_pt__U1430 _U1429 ( + .in(add_1120_1134_1135_out), + .out(out_conv_stencil) +); +_U1431_pt__U1432 _U1431 ( + .in(_U1433_out), + .out(_U1431_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1433 ( - .in(_U1432_out), + .in(add_1126_1127_1128_out), .clk(clk), .out(_U1433_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1434 ( - .in(_U1433_out), - .clk(clk), +_U1434_pt__U1435 _U1434 ( + .in(_U1437_out), .out(_U1434_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1435 ( - .in(_U1434_out), - .clk(clk), - .out(_U1435_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1436 ( - .in(_U1435_out), + .in(mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126_out), .clk(clk), .out(_U1436_out) ); @@ -22248,43 +22279,33 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1437_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1438 ( - .in(_U1437_out), - .clk(clk), +_U1438_pt__U1439 _U1438 ( + .in(_U1440_out), .out(_U1438_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1439 ( - .in(_U1438_out), - .clk(clk), - .out(_U1439_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1440 ( - .in(_U1439_out), + .in(mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127_out), .clk(clk), .out(_U1440_out) ); -assign add_1120_1134_1135_out = 16'(_U1296_out + _U1313_out); -assign add_1121_1132_1133_out = 16'(_U1401_out + _U1415_out); -assign add_1122_1131_1132_out = 16'(_U1319_out + _U1331_out); -assign add_1123_1130_1131_out = 16'(_U1360_out + _U1370_out); -assign add_1124_1129_1130_out = 16'(_U1373_out + _U1250_out); -assign add_1125_1128_1129_out = 16'(_U1253_out + _U1259_out); -assign add_1126_1127_1128_out = 16'(_U1418_out + _U1422_out); -assign add_conv_stencil_7_1133_1134_out = 16'(_U1425_out + _U1316_out); -assign mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120_out = 16'(_U1240_out * _U1242_out); -assign mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121_out = 16'(_U1244_out * _U1247_out); -assign mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122_out = 16'(_U1381_out * _U1385_out); -assign mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123_out = 16'(_U1389_out * _U1394_out); -assign mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124_out = 16'(_U1334_out * _U1340_out); -assign mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125_out = 16'(_U1346_out * _U1353_out); -assign mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126_out = 16'(_U1262_out * _U1270_out); -assign mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127_out = 16'(_U1278_out * _U1287_out); +assign add_1120_1134_1135_out = 16'(_U1409_out + _U1426_out); +assign add_1121_1132_1133_out = 16'(_U1324_out + _U1338_out); +assign add_1122_1131_1132_out = 16'(_U1344_out + _U1385_out); +assign add_1123_1130_1131_out = 16'(_U1388_out + _U1263_out); +assign add_1124_1129_1130_out = 16'(_U1266_out + _U1274_out); +assign add_1125_1128_1129_out = 16'(_U1277_out + _U1431_out); +assign add_1126_1127_1128_out = 16'(_U1434_out + _U1438_out); +assign add_conv_stencil_7_1133_1134_out = 16'(_U1240_out + _U1341_out); +assign mul_hw_kernel_global_wrapper_stencil_49_hw_input_global_wrapper_stencil_49_1120_out = 16'(_U1256_out * _U1258_out); +assign mul_hw_kernel_global_wrapper_stencil_50_hw_input_global_wrapper_stencil_50_1121_out = 16'(_U1260_out * _U1398_out); +assign mul_hw_kernel_global_wrapper_stencil_51_hw_input_global_wrapper_stencil_51_1122_out = 16'(_U1401_out * _U1405_out); +assign mul_hw_kernel_global_wrapper_stencil_52_hw_input_global_wrapper_stencil_52_1123_out = 16'(_U1356_out * _U1361_out); +assign mul_hw_kernel_global_wrapper_stencil_53_hw_input_global_wrapper_stencil_53_1124_out = 16'(_U1366_out * _U1372_out); +assign mul_hw_kernel_global_wrapper_stencil_54_hw_input_global_wrapper_stencil_54_1125_out = 16'(_U1378_out * _U1292_out); +assign mul_hw_kernel_global_wrapper_stencil_55_hw_input_global_wrapper_stencil_55_1126_out = 16'(_U1299_out * _U1307_out); +assign mul_hw_kernel_global_wrapper_stencil_56_hw_input_global_wrapper_stencil_56_1127_out = 16'(_U1315_out * _U1283_out); endmodule module cu_op_hcompute_conv_stencil_14 ( @@ -22325,2993 +22346,2972 @@ hcompute_conv_stencil_14_pipelined inner_compute ( assign conv_stencil_op_hcompute_conv_stencil_14_write[0] = inner_compute_out_conv_stencil; endmodule -module _U1236_pt__U1237 ( +module _U1235_pt__U1236 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1233_pt__U1234 ( +module _U1232_pt__U1233 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1231_pt__U1232 ( +module _U1229_pt__U1230 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1228_pt__U1229 ( +module _U1226_pt__U1227 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1223_pt__U1224 ( +module _U1211_pt__U1212 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1220_pt__U1221 ( +module _U1205_pt__U1206 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1212_pt__U1213 ( +module _U1194_pt__U1195 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1209_pt__U1210 ( +module _U1186_pt__U1187 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1206_pt__U1207 ( +module _U1183_pt__U1184 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1199_pt__U1200 ( +module _U1179_pt__U1180 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1193_pt__U1194 ( +module _U1171_pt__U1172 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U118_pt__U119 ( +module _U1166_pt__U1167 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1184_pt__U1185 ( +module _U1162_pt__U1163 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1181_pt__U1182 ( +module _U1153_pt__U1154 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1178_pt__U1179 ( +module _U1147_pt__U1148 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1166_pt__U1167 ( +module _U1144_pt__U1145 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1164_pt__U1165 ( +module _U1138_pt__U1139 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1162_pt__U1163 ( +module _U1135_pt__U1136 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U115_pt__U116 ( +module _U1132_pt__U1133 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1154_pt__U1155 ( +module _U1123_pt__U1124 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1146_pt__U1147 ( +module _U1120_pt__U1121 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1139_pt__U1140 ( +module _U111_pt__U112 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1133_pt__U1134 ( +module _U1118_pt__U1119 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1123_pt__U1124 ( +module _U1116_pt__U1117 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U111_pt__U112 ( +module _U1108_pt__U1109 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1119_pt__U1120 ( +module _U1101_pt__U1102 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1115_pt__U1116 ( +module _U10_pt__U11 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1105_pt__U1106 ( +module hcompute_hw_input_global_wrapper_stencil_2_pipelined ( + output [15:0] out_hw_input_global_wrapper_stencil, + input [15:0] in0_hw_input_stencil [0:0] +); +_U10_pt__U11 _U10 ( + .in(in0_hw_input_stencil[0]), + .out(out_hw_input_global_wrapper_stencil) +); +endmodule + +module cu_op_hcompute_hw_input_global_wrapper_stencil_2 ( + input clk, + input [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write [0:0] +); +wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; +wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read[0]; +hcompute_hw_input_global_wrapper_stencil_2_pipelined inner_compute ( + .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), + .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) +); +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +endmodule + +module _U1094_pt__U1095 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1102_pt__U1103 ( +module _U108_pt__U109 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U10_pt__U11 ( +module _U1085_pt__U1086 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_5_pipelined ( - output [15:0] out_hw_input_global_wrapper_stencil, - input [15:0] in0_hw_input_stencil [0:0] +module _U1075_pt__U1076 ( + input [15:0] in, + output [15:0] out ); -_U10_pt__U11 _U10 ( - .in(in0_hw_input_stencil[0]), - .out(out_hw_input_global_wrapper_stencil) +assign out = in; +endmodule + +module _U1072_pt__U1073 ( + input [15:0] in, + output [15:0] out ); +assign out = in; endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil_5 ( - input clk, - input [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write [0:0] +module _U1070_pt__U1071 ( + input [15:0] in, + output [15:0] out ); -wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; -wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read[0]; -hcompute_hw_input_global_wrapper_stencil_5_pipelined inner_compute ( - .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), - .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) +assign out = in; +endmodule + +module _U1067_pt__U1068 ( + input [15:0] in, + output [15:0] out ); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +assign out = in; endmodule -module _U1096_pt__U1097 ( +module _U1055_pt__U1056 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U108_pt__U109 ( +module _U104_pt__U105 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module hcompute_conv_stencil_8_pipelined ( +module _U1039_pt__U1040 ( + input [15:0] in, + output [15:0] out +); +assign out = in; +endmodule + +module hcompute_conv_stencil_13_pipelined ( input clk, input [15:0] in0_conv_stencil [0:0], input [15:0] in1_hw_input_global_wrapper_stencil [7:0], input [15:0] in2_hw_kernel_global_wrapper_stencil [7:0], output [15:0] out_conv_stencil ); -wire [15:0] _U101_out; -wire [15:0] _U102_out; -wire [15:0] _U103_out; -wire [15:0] _U104_out; -wire [15:0] _U105_out; -wire [15:0] _U106_out; -wire [15:0] _U107_out; -wire [15:0] _U108_out; -wire [15:0] _U110_out; -wire [15:0] _U111_out; -wire [15:0] _U113_out; -wire [15:0] _U114_out; -wire [15:0] _U115_out; -wire [15:0] _U117_out; -wire [15:0] _U118_out; -wire [15:0] _U120_out; -wire [15:0] _U121_out; -wire [15:0] _U122_out; -wire [15:0] _U123_out; -wire [15:0] _U124_out; -wire [15:0] _U125_out; -wire [15:0] _U126_out; -wire [15:0] _U127_out; -wire [15:0] _U128_out; -wire [15:0] _U129_out; -wire [15:0] _U130_out; -wire [15:0] _U131_out; -wire [15:0] _U132_out; -wire [15:0] _U133_out; -wire [15:0] _U134_out; -wire [15:0] _U136_out; -wire [15:0] _U138_out; -wire [15:0] _U140_out; -wire [15:0] _U141_out; -wire [15:0] _U143_out; -wire [15:0] _U144_out; -wire [15:0] _U146_out; -wire [15:0] _U147_out; -wire [15:0] _U148_out; -wire [15:0] _U150_out; -wire [15:0] _U151_out; -wire [15:0] _U152_out; -wire [15:0] _U153_out; -wire [15:0] _U154_out; -wire [15:0] _U155_out; -wire [15:0] _U156_out; -wire [15:0] _U157_out; -wire [15:0] _U158_out; -wire [15:0] _U159_out; -wire [15:0] _U160_out; -wire [15:0] _U161_out; -wire [15:0] _U162_out; -wire [15:0] _U164_out; -wire [15:0] _U165_out; -wire [15:0] _U167_out; -wire [15:0] _U168_out; -wire [15:0] _U170_out; -wire [15:0] _U171_out; -wire [15:0] _U172_out; -wire [15:0] _U173_out; -wire [15:0] _U174_out; -wire [15:0] _U175_out; -wire [15:0] _U176_out; -wire [15:0] _U177_out; -wire [15:0] _U178_out; -wire [15:0] _U179_out; -wire [15:0] _U180_out; -wire [15:0] _U182_out; -wire [15:0] _U183_out; -wire [15:0] _U185_out; -wire [15:0] _U186_out; -wire [15:0] _U187_out; -wire [15:0] _U188_out; -wire [15:0] _U189_out; -wire [15:0] _U190_out; -wire [15:0] _U191_out; -wire [15:0] _U192_out; -wire [15:0] _U193_out; -wire [15:0] _U195_out; -wire [15:0] _U196_out; -wire [15:0] _U198_out; -wire [15:0] _U199_out; -wire [15:0] _U200_out; -wire [15:0] _U201_out; -wire [15:0] _U202_out; -wire [15:0] _U203_out; -wire [15:0] _U204_out; -wire [15:0] _U206_out; -wire [15:0] _U207_out; -wire [15:0] _U209_out; -wire [15:0] _U210_out; -wire [15:0] _U211_out; -wire [15:0] _U212_out; -wire [15:0] _U213_out; -wire [15:0] _U215_out; -wire [15:0] _U216_out; -wire [15:0] _U217_out; -wire [15:0] _U218_out; -wire [15:0] _U219_out; -wire [15:0] _U220_out; -wire [15:0] _U221_out; -wire [15:0] _U222_out; -wire [15:0] _U223_out; -wire [15:0] _U224_out; -wire [15:0] _U225_out; -wire [15:0] _U226_out; -wire [15:0] _U227_out; -wire [15:0] _U228_out; -wire [15:0] _U229_out; -wire [15:0] _U230_out; -wire [15:0] _U232_out; -wire [15:0] _U34_out; -wire [15:0] _U36_out; -wire [15:0] _U37_out; -wire [15:0] _U38_out; -wire [15:0] _U40_out; -wire [15:0] _U41_out; -wire [15:0] _U42_out; -wire [15:0] _U43_out; -wire [15:0] _U45_out; -wire [15:0] _U46_out; -wire [15:0] _U47_out; -wire [15:0] _U48_out; -wire [15:0] _U50_out; -wire [15:0] _U51_out; -wire [15:0] _U52_out; -wire [15:0] _U53_out; -wire [15:0] _U54_out; -wire [15:0] _U56_out; -wire [15:0] _U57_out; -wire [15:0] _U58_out; -wire [15:0] _U59_out; -wire [15:0] _U60_out; -wire [15:0] _U62_out; -wire [15:0] _U63_out; -wire [15:0] _U64_out; -wire [15:0] _U65_out; -wire [15:0] _U66_out; -wire [15:0] _U67_out; -wire [15:0] _U69_out; -wire [15:0] _U70_out; -wire [15:0] _U71_out; -wire [15:0] _U72_out; -wire [15:0] _U73_out; -wire [15:0] _U74_out; -wire [15:0] _U76_out; -wire [15:0] _U77_out; -wire [15:0] _U78_out; -wire [15:0] _U79_out; -wire [15:0] _U80_out; -wire [15:0] _U81_out; -wire [15:0] _U82_out; -wire [15:0] _U84_out; -wire [15:0] _U85_out; -wire [15:0] _U86_out; -wire [15:0] _U87_out; -wire [15:0] _U88_out; -wire [15:0] _U89_out; -wire [15:0] _U90_out; -wire [15:0] _U92_out; -wire [15:0] _U93_out; -wire [15:0] _U94_out; -wire [15:0] _U95_out; -wire [15:0] _U96_out; -wire [15:0] _U97_out; -wire [15:0] _U98_out; -wire [15:0] _U99_out; -wire [15:0] add_718_732_733_out; -wire [15:0] add_719_730_731_out; -wire [15:0] add_720_729_730_out; -wire [15:0] add_721_728_729_out; -wire [15:0] add_722_727_728_out; -wire [15:0] add_723_726_727_out; -wire [15:0] add_724_725_726_out; -wire [15:0] add_conv_stencil_1_731_732_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725_out; -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U101 ( - .in(in1_hw_input_global_wrapper_stencil[7]), - .clk(clk), - .out(_U101_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U102 ( - .in(_U101_out), - .clk(clk), - .out(_U102_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( +wire [15:0] _U1039_out; +wire [15:0] _U1041_out; +wire [15:0] _U1042_out; +wire [15:0] _U1043_out; +wire [15:0] _U1044_out; +wire [15:0] _U1045_out; +wire [15:0] _U1046_out; +wire [15:0] _U1047_out; +wire [15:0] _U1048_out; +wire [15:0] _U1049_out; +wire [15:0] _U1050_out; +wire [15:0] _U1051_out; +wire [15:0] _U1052_out; +wire [15:0] _U1053_out; +wire [15:0] _U1054_out; +wire [15:0] _U1055_out; +wire [15:0] _U1057_out; +wire [15:0] _U1058_out; +wire [15:0] _U1059_out; +wire [15:0] _U1060_out; +wire [15:0] _U1061_out; +wire [15:0] _U1062_out; +wire [15:0] _U1063_out; +wire [15:0] _U1064_out; +wire [15:0] _U1065_out; +wire [15:0] _U1066_out; +wire [15:0] _U1067_out; +wire [15:0] _U1069_out; +wire [15:0] _U1072_out; +wire [15:0] _U1074_out; +wire [15:0] _U1075_out; +wire [15:0] _U1077_out; +wire [15:0] _U1078_out; +wire [15:0] _U1079_out; +wire [15:0] _U1080_out; +wire [15:0] _U1081_out; +wire [15:0] _U1082_out; +wire [15:0] _U1083_out; +wire [15:0] _U1084_out; +wire [15:0] _U1085_out; +wire [15:0] _U1087_out; +wire [15:0] _U1088_out; +wire [15:0] _U1089_out; +wire [15:0] _U1090_out; +wire [15:0] _U1091_out; +wire [15:0] _U1092_out; +wire [15:0] _U1093_out; +wire [15:0] _U1094_out; +wire [15:0] _U1096_out; +wire [15:0] _U1097_out; +wire [15:0] _U1098_out; +wire [15:0] _U1099_out; +wire [15:0] _U1100_out; +wire [15:0] _U1101_out; +wire [15:0] _U1103_out; +wire [15:0] _U1104_out; +wire [15:0] _U1105_out; +wire [15:0] _U1106_out; +wire [15:0] _U1107_out; +wire [15:0] _U1108_out; +wire [15:0] _U1110_out; +wire [15:0] _U1111_out; +wire [15:0] _U1112_out; +wire [15:0] _U1113_out; +wire [15:0] _U1114_out; +wire [15:0] _U1115_out; +wire [15:0] _U1116_out; +wire [15:0] _U1118_out; +wire [15:0] _U1120_out; +wire [15:0] _U1122_out; +wire [15:0] _U1123_out; +wire [15:0] _U1125_out; +wire [15:0] _U1126_out; +wire [15:0] _U1127_out; +wire [15:0] _U1128_out; +wire [15:0] _U1129_out; +wire [15:0] _U1130_out; +wire [15:0] _U1131_out; +wire [15:0] _U1132_out; +wire [15:0] _U1134_out; +wire [15:0] _U1135_out; +wire [15:0] _U1137_out; +wire [15:0] _U1138_out; +wire [15:0] _U1140_out; +wire [15:0] _U1141_out; +wire [15:0] _U1142_out; +wire [15:0] _U1143_out; +wire [15:0] _U1144_out; +wire [15:0] _U1146_out; +wire [15:0] _U1147_out; +wire [15:0] _U1149_out; +wire [15:0] _U1150_out; +wire [15:0] _U1151_out; +wire [15:0] _U1152_out; +wire [15:0] _U1153_out; +wire [15:0] _U1155_out; +wire [15:0] _U1156_out; +wire [15:0] _U1157_out; +wire [15:0] _U1158_out; +wire [15:0] _U1159_out; +wire [15:0] _U1160_out; +wire [15:0] _U1161_out; +wire [15:0] _U1162_out; +wire [15:0] _U1164_out; +wire [15:0] _U1165_out; +wire [15:0] _U1166_out; +wire [15:0] _U1168_out; +wire [15:0] _U1169_out; +wire [15:0] _U1170_out; +wire [15:0] _U1171_out; +wire [15:0] _U1173_out; +wire [15:0] _U1174_out; +wire [15:0] _U1175_out; +wire [15:0] _U1176_out; +wire [15:0] _U1177_out; +wire [15:0] _U1178_out; +wire [15:0] _U1179_out; +wire [15:0] _U1181_out; +wire [15:0] _U1182_out; +wire [15:0] _U1183_out; +wire [15:0] _U1185_out; +wire [15:0] _U1186_out; +wire [15:0] _U1188_out; +wire [15:0] _U1189_out; +wire [15:0] _U1190_out; +wire [15:0] _U1191_out; +wire [15:0] _U1192_out; +wire [15:0] _U1193_out; +wire [15:0] _U1194_out; +wire [15:0] _U1196_out; +wire [15:0] _U1197_out; +wire [15:0] _U1198_out; +wire [15:0] _U1199_out; +wire [15:0] _U1200_out; +wire [15:0] _U1201_out; +wire [15:0] _U1202_out; +wire [15:0] _U1203_out; +wire [15:0] _U1204_out; +wire [15:0] _U1205_out; +wire [15:0] _U1207_out; +wire [15:0] _U1208_out; +wire [15:0] _U1209_out; +wire [15:0] _U1210_out; +wire [15:0] _U1211_out; +wire [15:0] _U1213_out; +wire [15:0] _U1214_out; +wire [15:0] _U1215_out; +wire [15:0] _U1216_out; +wire [15:0] _U1217_out; +wire [15:0] _U1218_out; +wire [15:0] _U1219_out; +wire [15:0] _U1220_out; +wire [15:0] _U1221_out; +wire [15:0] _U1222_out; +wire [15:0] _U1223_out; +wire [15:0] _U1224_out; +wire [15:0] _U1225_out; +wire [15:0] _U1226_out; +wire [15:0] _U1228_out; +wire [15:0] _U1229_out; +wire [15:0] _U1231_out; +wire [15:0] _U1232_out; +wire [15:0] _U1234_out; +wire [15:0] _U1235_out; +wire [15:0] _U1237_out; +wire [15:0] _U1238_out; +wire [15:0] _U1239_out; +wire [15:0] add_1053_1067_1068_out; +wire [15:0] add_1054_1065_1066_out; +wire [15:0] add_1055_1064_1065_out; +wire [15:0] add_1056_1063_1064_out; +wire [15:0] add_1057_1062_1063_out; +wire [15:0] add_1058_1061_1062_out; +wire [15:0] add_1059_1060_1061_out; +wire [15:0] add_conv_stencil_6_1066_1067_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060_out; +_U1039_pt__U1040 _U1039 ( + .in(_U1054_out), + .out(_U1039_out) +); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U103 ( - .in(_U102_out), +) _U1041 ( + .in(in0_conv_stencil[0]), .clk(clk), - .out(_U103_out) + .out(_U1041_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U104 ( - .in(_U103_out), +) _U1042 ( + .in(_U1041_out), .clk(clk), - .out(_U104_out) + .out(_U1042_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U105 ( - .in(_U104_out), +) _U1043 ( + .in(_U1042_out), .clk(clk), - .out(_U105_out) + .out(_U1043_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U106 ( - .in(_U105_out), +) _U1044 ( + .in(_U1043_out), .clk(clk), - .out(_U106_out) + .out(_U1044_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U107 ( - .in(_U106_out), +) _U1045 ( + .in(_U1044_out), .clk(clk), - .out(_U107_out) -); -_U108_pt__U109 _U108 ( - .in(_U110_out), - .out(_U108_out) + .out(_U1045_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U110 ( - .in(add_724_725_726_out), +) _U1046 ( + .in(_U1045_out), .clk(clk), - .out(_U110_out) -); -_U111_pt__U112 _U111 ( - .in(_U114_out), - .out(_U111_out) + .out(_U1046_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U113 ( - .in(mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724_out), +) _U1047 ( + .in(_U1046_out), .clk(clk), - .out(_U113_out) + .out(_U1047_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U114 ( - .in(_U113_out), +) _U1048 ( + .in(_U1047_out), .clk(clk), - .out(_U114_out) -); -_U115_pt__U116 _U115 ( - .in(_U117_out), - .out(_U115_out) + .out(_U1048_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U117 ( - .in(mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725_out), +) _U1049 ( + .in(_U1048_out), .clk(clk), - .out(_U117_out) -); -_U118_pt__U119 _U118 ( - .in(_U133_out), - .out(_U118_out) + .out(_U1049_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U120 ( - .in(in0_conv_stencil[0]), +) _U1050 ( + .in(_U1049_out), .clk(clk), - .out(_U120_out) + .out(_U1050_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U121 ( - .in(_U120_out), +) _U1051 ( + .in(_U1050_out), .clk(clk), - .out(_U121_out) + .out(_U1051_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U122 ( - .in(_U121_out), +) _U1052 ( + .in(_U1051_out), .clk(clk), - .out(_U122_out) + .out(_U1052_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U123 ( - .in(_U122_out), +) _U1053 ( + .in(_U1052_out), .clk(clk), - .out(_U123_out) + .out(_U1053_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U124 ( - .in(_U123_out), +) _U1054 ( + .in(_U1053_out), .clk(clk), - .out(_U124_out) + .out(_U1054_out) +); +_U1055_pt__U1056 _U1055 ( + .in(_U1066_out), + .out(_U1055_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U125 ( - .in(_U124_out), +) _U1057 ( + .in(mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054_out), .clk(clk), - .out(_U125_out) + .out(_U1057_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U126 ( - .in(_U125_out), +) _U1058 ( + .in(_U1057_out), .clk(clk), - .out(_U126_out) + .out(_U1058_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U127 ( - .in(_U126_out), +) _U1059 ( + .in(_U1058_out), .clk(clk), - .out(_U127_out) + .out(_U1059_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U128 ( - .in(_U127_out), +) _U1060 ( + .in(_U1059_out), .clk(clk), - .out(_U128_out) + .out(_U1060_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U129 ( - .in(_U128_out), +) _U1061 ( + .in(_U1060_out), .clk(clk), - .out(_U129_out) + .out(_U1061_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U130 ( - .in(_U129_out), +) _U1062 ( + .in(_U1061_out), .clk(clk), - .out(_U130_out) + .out(_U1062_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U131 ( - .in(_U130_out), +) _U1063 ( + .in(_U1062_out), .clk(clk), - .out(_U131_out) + .out(_U1063_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U132 ( - .in(_U131_out), +) _U1064 ( + .in(_U1063_out), .clk(clk), - .out(_U132_out) + .out(_U1064_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U133 ( - .in(_U132_out), +) _U1065 ( + .in(_U1064_out), .clk(clk), - .out(_U133_out) -); -_U134_pt__U135 _U134 ( - .in(in2_hw_kernel_global_wrapper_stencil[0]), - .out(_U134_out) -); -_U136_pt__U137 _U136 ( - .in(in1_hw_input_global_wrapper_stencil[0]), - .out(_U136_out) -); -_U138_pt__U139 _U138 ( - .in(_U140_out), - .out(_U138_out) + .out(_U1065_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U140 ( - .in(in2_hw_kernel_global_wrapper_stencil[1]), +) _U1066 ( + .in(_U1065_out), .clk(clk), - .out(_U140_out) + .out(_U1066_out) ); -_U141_pt__U142 _U141 ( - .in(_U143_out), - .out(_U141_out) +_U1067_pt__U1068 _U1067 ( + .in(_U1069_out), + .out(_U1067_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U143 ( - .in(in1_hw_input_global_wrapper_stencil[1]), +) _U1069 ( + .in(add_1058_1061_1062_out), .clk(clk), - .out(_U143_out) + .out(_U1069_out) ); -_U144_pt__U145 _U144 ( - .in(_U147_out), - .out(_U144_out) +_U1070_pt__U1071 _U1070 ( + .in(add_1053_1067_1068_out), + .out(out_conv_stencil) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U146 ( - .in(in2_hw_kernel_global_wrapper_stencil[2]), - .clk(clk), - .out(_U146_out) +_U1072_pt__U1073 _U1072 ( + .in(_U1074_out), + .out(_U1072_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U147 ( - .in(_U146_out), +) _U1074 ( + .in(add_1059_1060_1061_out), .clk(clk), - .out(_U147_out) + .out(_U1074_out) ); -_U148_pt__U149 _U148 ( - .in(_U161_out), - .out(_U148_out) +_U1075_pt__U1076 _U1075 ( + .in(_U1084_out), + .out(_U1075_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U150 ( - .in(mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719_out), +) _U1077 ( + .in(mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055_out), .clk(clk), - .out(_U150_out) + .out(_U1077_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U151 ( - .in(_U150_out), +) _U1078 ( + .in(_U1077_out), .clk(clk), - .out(_U151_out) + .out(_U1078_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U152 ( - .in(_U151_out), +) _U1079 ( + .in(_U1078_out), .clk(clk), - .out(_U152_out) + .out(_U1079_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U153 ( - .in(_U152_out), +) _U1080 ( + .in(_U1079_out), .clk(clk), - .out(_U153_out) + .out(_U1080_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U154 ( - .in(_U153_out), +) _U1081 ( + .in(_U1080_out), .clk(clk), - .out(_U154_out) + .out(_U1081_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U155 ( - .in(_U154_out), +) _U1082 ( + .in(_U1081_out), .clk(clk), - .out(_U155_out) + .out(_U1082_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U156 ( - .in(_U155_out), +) _U1083 ( + .in(_U1082_out), .clk(clk), - .out(_U156_out) + .out(_U1083_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U157 ( - .in(_U156_out), +) _U1084 ( + .in(_U1083_out), .clk(clk), - .out(_U157_out) + .out(_U1084_out) +); +_U1085_pt__U1086 _U1085 ( + .in(_U1093_out), + .out(_U1085_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U158 ( - .in(_U157_out), +) _U1087 ( + .in(mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059_out), .clk(clk), - .out(_U158_out) + .out(_U1087_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U159 ( - .in(_U158_out), +) _U1088 ( + .in(_U1087_out), .clk(clk), - .out(_U159_out) + .out(_U1088_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U160 ( - .in(_U159_out), +) _U1089 ( + .in(_U1088_out), .clk(clk), - .out(_U160_out) + .out(_U1089_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U161 ( - .in(_U160_out), +) _U1090 ( + .in(_U1089_out), .clk(clk), - .out(_U161_out) -); -_U162_pt__U163 _U162 ( - .in(_U164_out), - .out(_U162_out) + .out(_U1090_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U164 ( - .in(add_720_729_730_out), +) _U1091 ( + .in(_U1090_out), .clk(clk), - .out(_U164_out) -); -_U165_pt__U166 _U165 ( - .in(_U167_out), - .out(_U165_out) + .out(_U1091_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U167 ( - .in(add_719_730_731_out), +) _U1092 ( + .in(_U1091_out), .clk(clk), - .out(_U167_out) -); -_U168_pt__U169 _U168 ( - .in(_U179_out), - .out(_U168_out) + .out(_U1092_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U170 ( - .in(mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720_out), +) _U1093 ( + .in(_U1092_out), .clk(clk), - .out(_U170_out) + .out(_U1093_out) +); +_U1094_pt__U1095 _U1094 ( + .in(_U1100_out), + .out(_U1094_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U171 ( - .in(_U170_out), +) _U1096 ( + .in(in2_hw_kernel_global_wrapper_stencil[3]), .clk(clk), - .out(_U171_out) + .out(_U1096_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U172 ( - .in(_U171_out), +) _U1097 ( + .in(_U1096_out), .clk(clk), - .out(_U172_out) + .out(_U1097_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U173 ( - .in(_U172_out), +) _U1098 ( + .in(_U1097_out), .clk(clk), - .out(_U173_out) + .out(_U1098_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U174 ( - .in(_U173_out), +) _U1099 ( + .in(_U1098_out), .clk(clk), - .out(_U174_out) + .out(_U1099_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U175 ( - .in(_U174_out), +) _U1100 ( + .in(_U1099_out), .clk(clk), - .out(_U175_out) + .out(_U1100_out) +); +_U1101_pt__U1102 _U1101 ( + .in(_U1107_out), + .out(_U1101_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U176 ( - .in(_U175_out), +) _U1103 ( + .in(in1_hw_input_global_wrapper_stencil[3]), .clk(clk), - .out(_U176_out) + .out(_U1103_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U177 ( - .in(_U176_out), +) _U1104 ( + .in(_U1103_out), .clk(clk), - .out(_U177_out) + .out(_U1104_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U178 ( - .in(_U177_out), +) _U1105 ( + .in(_U1104_out), .clk(clk), - .out(_U178_out) + .out(_U1105_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U179 ( - .in(_U178_out), +) _U1106 ( + .in(_U1105_out), .clk(clk), - .out(_U179_out) -); -_U180_pt__U181 _U180 ( - .in(_U182_out), - .out(_U180_out) + .out(_U1106_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U182 ( - .in(add_721_728_729_out), +) _U1107 ( + .in(_U1106_out), .clk(clk), - .out(_U182_out) + .out(_U1107_out) ); -_U183_pt__U184 _U183 ( - .in(_U192_out), - .out(_U183_out) +_U1108_pt__U1109 _U1108 ( + .in(_U1115_out), + .out(_U1108_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U185 ( - .in(mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721_out), +) _U1110 ( + .in(in2_hw_kernel_global_wrapper_stencil[4]), .clk(clk), - .out(_U185_out) + .out(_U1110_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U186 ( - .in(_U185_out), +) _U1111 ( + .in(_U1110_out), .clk(clk), - .out(_U186_out) + .out(_U1111_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U187 ( - .in(_U186_out), +) _U1112 ( + .in(_U1111_out), .clk(clk), - .out(_U187_out) + .out(_U1112_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U188 ( - .in(_U187_out), +) _U1113 ( + .in(_U1112_out), .clk(clk), - .out(_U188_out) + .out(_U1113_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U189 ( - .in(_U188_out), +) _U1114 ( + .in(_U1113_out), .clk(clk), - .out(_U189_out) + .out(_U1114_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U190 ( - .in(_U189_out), +) _U1115 ( + .in(_U1114_out), .clk(clk), - .out(_U190_out) + .out(_U1115_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U191 ( - .in(_U190_out), - .clk(clk), - .out(_U191_out) +_U1116_pt__U1117 _U1116 ( + .in(in2_hw_kernel_global_wrapper_stencil[5]), + .out(_U1116_out) +); +_U1118_pt__U1119 _U1118 ( + .in(in1_hw_input_global_wrapper_stencil[5]), + .out(_U1118_out) +); +_U1120_pt__U1121 _U1120 ( + .in(_U1122_out), + .out(_U1120_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U192 ( - .in(_U191_out), +) _U1122 ( + .in(in2_hw_kernel_global_wrapper_stencil[6]), .clk(clk), - .out(_U192_out) + .out(_U1122_out) ); -_U193_pt__U194 _U193 ( - .in(_U195_out), - .out(_U193_out) +_U1123_pt__U1124 _U1123 ( + .in(_U1131_out), + .out(_U1123_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U195 ( - .in(add_722_727_728_out), +) _U1125 ( + .in(in2_hw_kernel_global_wrapper_stencil[7]), .clk(clk), - .out(_U195_out) -); -_U196_pt__U197 _U196 ( - .in(_U203_out), - .out(_U196_out) + .out(_U1125_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U198 ( - .in(mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722_out), +) _U1126 ( + .in(_U1125_out), .clk(clk), - .out(_U198_out) + .out(_U1126_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U199 ( - .in(_U198_out), +) _U1127 ( + .in(_U1126_out), .clk(clk), - .out(_U199_out) + .out(_U1127_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U200 ( - .in(_U199_out), +) _U1128 ( + .in(_U1127_out), .clk(clk), - .out(_U200_out) + .out(_U1128_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U201 ( - .in(_U200_out), +) _U1129 ( + .in(_U1128_out), .clk(clk), - .out(_U201_out) + .out(_U1129_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U202 ( - .in(_U201_out), +) _U1130 ( + .in(_U1129_out), .clk(clk), - .out(_U202_out) + .out(_U1130_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U203 ( - .in(_U202_out), +) _U1131 ( + .in(_U1130_out), .clk(clk), - .out(_U203_out) + .out(_U1131_out) ); -_U204_pt__U205 _U204 ( - .in(_U206_out), - .out(_U204_out) +_U1132_pt__U1133 _U1132 ( + .in(_U1134_out), + .out(_U1132_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U206 ( - .in(add_723_726_727_out), +) _U1134 ( + .in(in1_hw_input_global_wrapper_stencil[6]), .clk(clk), - .out(_U206_out) + .out(_U1134_out) ); -_U207_pt__U208 _U207 ( - .in(_U212_out), - .out(_U207_out) +_U1135_pt__U1136 _U1135 ( + .in(_U1137_out), + .out(_U1135_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U209 ( - .in(mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723_out), +) _U1137 ( + .in(add_1054_1065_1066_out), .clk(clk), - .out(_U209_out) + .out(_U1137_out) +); +_U1138_pt__U1139 _U1138 ( + .in(_U1143_out), + .out(_U1138_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U210 ( - .in(_U209_out), +) _U1140 ( + .in(mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057_out), .clk(clk), - .out(_U210_out) + .out(_U1140_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U211 ( - .in(_U210_out), +) _U1141 ( + .in(_U1140_out), .clk(clk), - .out(_U211_out) + .out(_U1141_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U212 ( - .in(_U211_out), +) _U1142 ( + .in(_U1141_out), .clk(clk), - .out(_U212_out) -); -_U213_pt__U214 _U213 ( - .in(_U229_out), - .out(_U213_out) + .out(_U1142_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U215 ( - .in(mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718_out), +) _U1143 ( + .in(_U1142_out), .clk(clk), - .out(_U215_out) + .out(_U1143_out) +); +_U1144_pt__U1145 _U1144 ( + .in(_U1146_out), + .out(_U1144_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U216 ( - .in(_U215_out), +) _U1146 ( + .in(add_1055_1064_1065_out), .clk(clk), - .out(_U216_out) + .out(_U1146_out) +); +_U1147_pt__U1148 _U1147 ( + .in(_U1152_out), + .out(_U1147_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U217 ( - .in(_U216_out), +) _U1149 ( + .in(in2_hw_kernel_global_wrapper_stencil[2]), .clk(clk), - .out(_U217_out) + .out(_U1149_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U218 ( - .in(_U217_out), +) _U1150 ( + .in(_U1149_out), .clk(clk), - .out(_U218_out) + .out(_U1150_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U219 ( - .in(_U218_out), +) _U1151 ( + .in(_U1150_out), .clk(clk), - .out(_U219_out) + .out(_U1151_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U220 ( - .in(_U219_out), +) _U1152 ( + .in(_U1151_out), .clk(clk), - .out(_U220_out) + .out(_U1152_out) +); +_U1153_pt__U1154 _U1153 ( + .in(_U1161_out), + .out(_U1153_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U221 ( - .in(_U220_out), +) _U1155 ( + .in(in1_hw_input_global_wrapper_stencil[7]), .clk(clk), - .out(_U221_out) + .out(_U1155_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U222 ( - .in(_U221_out), +) _U1156 ( + .in(_U1155_out), .clk(clk), - .out(_U222_out) + .out(_U1156_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U223 ( - .in(_U222_out), +) _U1157 ( + .in(_U1156_out), .clk(clk), - .out(_U223_out) + .out(_U1157_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U224 ( - .in(_U223_out), +) _U1158 ( + .in(_U1157_out), .clk(clk), - .out(_U224_out) + .out(_U1158_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U225 ( - .in(_U224_out), +) _U1159 ( + .in(_U1158_out), .clk(clk), - .out(_U225_out) + .out(_U1159_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U226 ( - .in(_U225_out), +) _U1160 ( + .in(_U1159_out), .clk(clk), - .out(_U226_out) + .out(_U1160_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U227 ( - .in(_U226_out), +) _U1161 ( + .in(_U1160_out), .clk(clk), - .out(_U227_out) + .out(_U1161_out) +); +_U1162_pt__U1163 _U1162 ( + .in(_U1165_out), + .out(_U1162_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U228 ( - .in(_U227_out), +) _U1164 ( + .in(in2_hw_kernel_global_wrapper_stencil[0]), .clk(clk), - .out(_U228_out) + .out(_U1164_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U229 ( - .in(_U228_out), +) _U1165 ( + .in(_U1164_out), .clk(clk), - .out(_U229_out) + .out(_U1165_out) ); -_U230_pt__U231 _U230 ( - .in(_U232_out), - .out(_U230_out) +_U1166_pt__U1167 _U1166 ( + .in(_U1170_out), + .out(_U1166_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U232 ( - .in(add_conv_stencil_1_731_732_out), +) _U1168 ( + .in(in2_hw_kernel_global_wrapper_stencil[1]), .clk(clk), - .out(_U232_out) -); -_U233_pt__U234 _U233 ( - .in(add_718_732_733_out), - .out(out_conv_stencil) -); -_U34_pt__U35 _U34 ( - .in(_U37_out), - .out(_U34_out) + .out(_U1168_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U36 ( - .in(in1_hw_input_global_wrapper_stencil[2]), +) _U1169 ( + .in(_U1168_out), .clk(clk), - .out(_U36_out) + .out(_U1169_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U37 ( - .in(_U36_out), +) _U1170 ( + .in(_U1169_out), .clk(clk), - .out(_U37_out) + .out(_U1170_out) ); -_U38_pt__U39 _U38 ( - .in(_U42_out), - .out(_U38_out) +_U1171_pt__U1172 _U1171 ( + .in(_U1178_out), + .out(_U1171_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U40 ( - .in(in2_hw_kernel_global_wrapper_stencil[3]), +) _U1173 ( + .in(in1_hw_input_global_wrapper_stencil[4]), .clk(clk), - .out(_U40_out) + .out(_U1173_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U41 ( - .in(_U40_out), +) _U1174 ( + .in(_U1173_out), .clk(clk), - .out(_U41_out) + .out(_U1174_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U42 ( - .in(_U41_out), +) _U1175 ( + .in(_U1174_out), .clk(clk), - .out(_U42_out) -); -_U43_pt__U44 _U43 ( - .in(_U47_out), - .out(_U43_out) + .out(_U1175_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U45 ( - .in(in1_hw_input_global_wrapper_stencil[3]), +) _U1176 ( + .in(_U1175_out), .clk(clk), - .out(_U45_out) + .out(_U1176_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U46 ( - .in(_U45_out), +) _U1177 ( + .in(_U1176_out), .clk(clk), - .out(_U46_out) + .out(_U1177_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U47 ( - .in(_U46_out), +) _U1178 ( + .in(_U1177_out), .clk(clk), - .out(_U47_out) + .out(_U1178_out) ); -_U48_pt__U49 _U48 ( - .in(_U53_out), - .out(_U48_out) +_U1179_pt__U1180 _U1179 ( + .in(_U1182_out), + .out(_U1179_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U50 ( - .in(in2_hw_kernel_global_wrapper_stencil[4]), +) _U1181 ( + .in(in1_hw_input_global_wrapper_stencil[0]), .clk(clk), - .out(_U50_out) + .out(_U1181_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U51 ( - .in(_U50_out), +) _U1182 ( + .in(_U1181_out), .clk(clk), - .out(_U51_out) + .out(_U1182_out) +); +_U1183_pt__U1184 _U1183 ( + .in(_U1185_out), + .out(_U1183_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U52 ( - .in(_U51_out), +) _U1185 ( + .in(add_1056_1063_1064_out), .clk(clk), - .out(_U52_out) + .out(_U1185_out) +); +_U1186_pt__U1187 _U1186 ( + .in(_U1193_out), + .out(_U1186_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U53 ( - .in(_U52_out), +) _U1188 ( + .in(mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056_out), .clk(clk), - .out(_U53_out) + .out(_U1188_out) ); -_U54_pt__U55 _U54 ( - .in(_U59_out), - .out(_U54_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1189 ( + .in(_U1188_out), + .clk(clk), + .out(_U1189_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U56 ( - .in(in1_hw_input_global_wrapper_stencil[4]), +) _U1190 ( + .in(_U1189_out), .clk(clk), - .out(_U56_out) + .out(_U1190_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U57 ( - .in(_U56_out), +) _U1191 ( + .in(_U1190_out), .clk(clk), - .out(_U57_out) + .out(_U1191_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U58 ( - .in(_U57_out), +) _U1192 ( + .in(_U1191_out), .clk(clk), - .out(_U58_out) + .out(_U1192_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U59 ( - .in(_U58_out), +) _U1193 ( + .in(_U1192_out), .clk(clk), - .out(_U59_out) + .out(_U1193_out) ); -_U60_pt__U61 _U60 ( - .in(_U66_out), - .out(_U60_out) +_U1194_pt__U1195 _U1194 ( + .in(_U1204_out), + .out(_U1194_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U62 ( - .in(in2_hw_kernel_global_wrapper_stencil[5]), +) _U1196 ( + .in(mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058_out), .clk(clk), - .out(_U62_out) + .out(_U1196_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U63 ( - .in(_U62_out), +) _U1197 ( + .in(_U1196_out), .clk(clk), - .out(_U63_out) + .out(_U1197_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U64 ( - .in(_U63_out), +) _U1198 ( + .in(_U1197_out), .clk(clk), - .out(_U64_out) + .out(_U1198_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U65 ( - .in(_U64_out), +) _U1199 ( + .in(_U1198_out), .clk(clk), - .out(_U65_out) + .out(_U1199_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U66 ( - .in(_U65_out), +) _U1200 ( + .in(_U1199_out), .clk(clk), - .out(_U66_out) -); -_U67_pt__U68 _U67 ( - .in(_U73_out), - .out(_U67_out) + .out(_U1200_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U69 ( - .in(in1_hw_input_global_wrapper_stencil[5]), +) _U1201 ( + .in(_U1200_out), .clk(clk), - .out(_U69_out) + .out(_U1201_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U70 ( - .in(_U69_out), +) _U1202 ( + .in(_U1201_out), .clk(clk), - .out(_U70_out) + .out(_U1202_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U71 ( - .in(_U70_out), +) _U1203 ( + .in(_U1202_out), .clk(clk), - .out(_U71_out) + .out(_U1203_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U72 ( - .in(_U71_out), +) _U1204 ( + .in(_U1203_out), .clk(clk), - .out(_U72_out) + .out(_U1204_out) +); +_U1205_pt__U1206 _U1205 ( + .in(_U1210_out), + .out(_U1205_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U73 ( - .in(_U72_out), +) _U1207 ( + .in(in1_hw_input_global_wrapper_stencil[2]), .clk(clk), - .out(_U73_out) -); -_U74_pt__U75 _U74 ( - .in(_U81_out), - .out(_U74_out) + .out(_U1207_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U76 ( - .in(in2_hw_kernel_global_wrapper_stencil[6]), +) _U1208 ( + .in(_U1207_out), .clk(clk), - .out(_U76_out) + .out(_U1208_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U77 ( - .in(_U76_out), +) _U1209 ( + .in(_U1208_out), .clk(clk), - .out(_U77_out) + .out(_U1209_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U78 ( - .in(_U77_out), +) _U1210 ( + .in(_U1209_out), .clk(clk), - .out(_U78_out) + .out(_U1210_out) +); +_U1211_pt__U1212 _U1211 ( + .in(_U1225_out), + .out(_U1211_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U79 ( - .in(_U78_out), +) _U1213 ( + .in(mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053_out), .clk(clk), - .out(_U79_out) + .out(_U1213_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U80 ( - .in(_U79_out), +) _U1214 ( + .in(_U1213_out), .clk(clk), - .out(_U80_out) + .out(_U1214_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U81 ( - .in(_U80_out), +) _U1215 ( + .in(_U1214_out), .clk(clk), - .out(_U81_out) + .out(_U1215_out) ); -_U82_pt__U83 _U82 ( - .in(_U89_out), - .out(_U82_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1216 ( + .in(_U1215_out), + .clk(clk), + .out(_U1216_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U84 ( - .in(in1_hw_input_global_wrapper_stencil[6]), +) _U1217 ( + .in(_U1216_out), .clk(clk), - .out(_U84_out) + .out(_U1217_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U85 ( - .in(_U84_out), +) _U1218 ( + .in(_U1217_out), .clk(clk), - .out(_U85_out) + .out(_U1218_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U86 ( - .in(_U85_out), +) _U1219 ( + .in(_U1218_out), .clk(clk), - .out(_U86_out) + .out(_U1219_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U87 ( - .in(_U86_out), +) _U1220 ( + .in(_U1219_out), .clk(clk), - .out(_U87_out) + .out(_U1220_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U88 ( - .in(_U87_out), +) _U1221 ( + .in(_U1220_out), .clk(clk), - .out(_U88_out) + .out(_U1221_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U89 ( - .in(_U88_out), +) _U1222 ( + .in(_U1221_out), .clk(clk), - .out(_U89_out) + .out(_U1222_out) ); -_U90_pt__U91 _U90 ( - .in(_U98_out), - .out(_U90_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1223 ( + .in(_U1222_out), + .clk(clk), + .out(_U1223_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U92 ( - .in(in2_hw_kernel_global_wrapper_stencil[7]), +) _U1224 ( + .in(_U1223_out), .clk(clk), - .out(_U92_out) + .out(_U1224_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U93 ( - .in(_U92_out), +) _U1225 ( + .in(_U1224_out), .clk(clk), - .out(_U93_out) + .out(_U1225_out) +); +_U1226_pt__U1227 _U1226 ( + .in(_U1228_out), + .out(_U1226_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U94 ( - .in(_U93_out), +) _U1228 ( + .in(add_1057_1062_1063_out), .clk(clk), - .out(_U94_out) + .out(_U1228_out) +); +_U1229_pt__U1230 _U1229 ( + .in(_U1231_out), + .out(_U1229_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U95 ( - .in(_U94_out), +) _U1231 ( + .in(mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060_out), .clk(clk), - .out(_U95_out) + .out(_U1231_out) +); +_U1232_pt__U1233 _U1232 ( + .in(_U1234_out), + .out(_U1232_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U96 ( - .in(_U95_out), +) _U1234 ( + .in(add_conv_stencil_6_1066_1067_out), .clk(clk), - .out(_U96_out) + .out(_U1234_out) +); +_U1235_pt__U1236 _U1235 ( + .in(_U1239_out), + .out(_U1235_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U97 ( - .in(_U96_out), +) _U1237 ( + .in(in1_hw_input_global_wrapper_stencil[1]), .clk(clk), - .out(_U97_out) + .out(_U1237_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U98 ( - .in(_U97_out), +) _U1238 ( + .in(_U1237_out), .clk(clk), - .out(_U98_out) + .out(_U1238_out) ); -_U99_pt__U100 _U99 ( - .in(_U107_out), - .out(_U99_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1239 ( + .in(_U1238_out), + .clk(clk), + .out(_U1239_out) ); -assign add_718_732_733_out = 16'(_U213_out + _U230_out); -assign add_719_730_731_out = 16'(_U148_out + _U162_out); -assign add_720_729_730_out = 16'(_U168_out + _U180_out); -assign add_721_728_729_out = 16'(_U183_out + _U193_out); -assign add_722_727_728_out = 16'(_U196_out + _U204_out); -assign add_723_726_727_out = 16'(_U207_out + _U108_out); -assign add_724_725_726_out = 16'(_U111_out + _U115_out); -assign add_conv_stencil_1_731_732_out = 16'(_U118_out + _U165_out); -assign mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718_out = 16'(_U134_out * _U136_out); -assign mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719_out = 16'(_U138_out * _U141_out); -assign mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720_out = 16'(_U144_out * _U34_out); -assign mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721_out = 16'(_U38_out * _U43_out); -assign mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722_out = 16'(_U48_out * _U54_out); -assign mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723_out = 16'(_U60_out * _U67_out); -assign mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724_out = 16'(_U74_out * _U82_out); -assign mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725_out = 16'(_U90_out * _U99_out); +assign add_1053_1067_1068_out = 16'(_U1211_out + _U1232_out); +assign add_1054_1065_1066_out = 16'(_U1055_out + _U1144_out); +assign add_1055_1064_1065_out = 16'(_U1075_out + _U1183_out); +assign add_1056_1063_1064_out = 16'(_U1186_out + _U1226_out); +assign add_1057_1062_1063_out = 16'(_U1138_out + _U1067_out); +assign add_1058_1061_1062_out = 16'(_U1194_out + _U1072_out); +assign add_1059_1060_1061_out = 16'(_U1085_out + _U1229_out); +assign add_conv_stencil_6_1066_1067_out = 16'(_U1039_out + _U1135_out); +assign mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053_out = 16'(_U1162_out * _U1179_out); +assign mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054_out = 16'(_U1166_out * _U1235_out); +assign mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055_out = 16'(_U1147_out * _U1205_out); +assign mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056_out = 16'(_U1094_out * _U1101_out); +assign mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057_out = 16'(_U1108_out * _U1171_out); +assign mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058_out = 16'(_U1116_out * _U1118_out); +assign mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059_out = 16'(_U1120_out * _U1132_out); +assign mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060_out = 16'(_U1123_out * _U1153_out); endmodule -module cu_op_hcompute_conv_stencil_8 ( +module cu_op_hcompute_conv_stencil_13 ( input clk, - input [15:0] conv_stencil_op_hcompute_conv_stencil_8_read [0:0], - input [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read [7:0], - input [15:0] hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read [7:0], - output [15:0] conv_stencil_op_hcompute_conv_stencil_8_write [0:0] + input [15:0] conv_stencil_op_hcompute_conv_stencil_13_read [0:0], + input [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read [7:0], + input [15:0] hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read [7:0], + output [15:0] conv_stencil_op_hcompute_conv_stencil_13_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; wire [15:0] inner_compute_in0_conv_stencil [0:0]; -assign inner_compute_in0_conv_stencil[0] = conv_stencil_op_hcompute_conv_stencil_8_read[0]; +assign inner_compute_in0_conv_stencil[0] = conv_stencil_op_hcompute_conv_stencil_13_read[0]; wire [15:0] inner_compute_in1_hw_input_global_wrapper_stencil [7:0]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[7] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[7]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[6] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[6]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[5] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[5]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[4] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[4]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[3] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[3]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[2] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[2]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[1] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[1]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[0] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[0]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[7] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[7]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[6] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[6]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[5] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[5]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[4] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[4]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[3] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[3]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[2] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[2]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[1] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[1]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[0] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[0]; wire [15:0] inner_compute_in2_hw_kernel_global_wrapper_stencil [7:0]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[7] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[7]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[6] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[6]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[5] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[5]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[4] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[4]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[3] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[3]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[2] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[2]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[1] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[1]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[0] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[0]; -hcompute_conv_stencil_8_pipelined inner_compute ( +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[7] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[7]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[6] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[6]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[5] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[5]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[4] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[4]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[3] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[3]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[2] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[2]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[1] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[1]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[0] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[0]; +hcompute_conv_stencil_13_pipelined inner_compute ( .clk(clk), .in0_conv_stencil(inner_compute_in0_conv_stencil), .in1_hw_input_global_wrapper_stencil(inner_compute_in1_hw_input_global_wrapper_stencil), .in2_hw_kernel_global_wrapper_stencil(inner_compute_in2_hw_kernel_global_wrapper_stencil), .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_8_write[0] = inner_compute_out_conv_stencil; -endmodule - -module _U1082_pt__U1083 ( - input [15:0] in, - output [15:0] out -); -assign out = in; -endmodule - -module _U1077_pt__U1078 ( - input [15:0] in, - output [15:0] out -); -assign out = in; -endmodule - -module _U1074_pt__U1075 ( - input [15:0] in, - output [15:0] out -); -assign out = in; +assign conv_stencil_op_hcompute_conv_stencil_13_write[0] = inner_compute_out_conv_stencil; endmodule -module _U1065_pt__U1066 ( +module _U1035_pt__U1036 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1049_pt__U1050 ( +module _U1027_pt__U1028 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1039_pt__U1040 ( +module _U101_pt__U102 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module hcompute_conv_stencil_13_pipelined ( +module hcompute_conv_stencil_8_pipelined ( input clk, input [15:0] in0_conv_stencil [0:0], input [15:0] in1_hw_input_global_wrapper_stencil [7:0], input [15:0] in2_hw_kernel_global_wrapper_stencil [7:0], output [15:0] out_conv_stencil ); -wire [15:0] _U1039_out; -wire [15:0] _U1041_out; -wire [15:0] _U1042_out; -wire [15:0] _U1043_out; -wire [15:0] _U1044_out; -wire [15:0] _U1045_out; -wire [15:0] _U1046_out; -wire [15:0] _U1047_out; -wire [15:0] _U1048_out; -wire [15:0] _U1049_out; -wire [15:0] _U1051_out; -wire [15:0] _U1052_out; -wire [15:0] _U1053_out; -wire [15:0] _U1054_out; -wire [15:0] _U1055_out; -wire [15:0] _U1056_out; -wire [15:0] _U1057_out; -wire [15:0] _U1058_out; -wire [15:0] _U1059_out; -wire [15:0] _U1060_out; -wire [15:0] _U1061_out; -wire [15:0] _U1062_out; -wire [15:0] _U1063_out; -wire [15:0] _U1064_out; -wire [15:0] _U1065_out; -wire [15:0] _U1067_out; -wire [15:0] _U1068_out; -wire [15:0] _U1069_out; -wire [15:0] _U1070_out; -wire [15:0] _U1071_out; -wire [15:0] _U1072_out; -wire [15:0] _U1073_out; -wire [15:0] _U1074_out; -wire [15:0] _U1076_out; -wire [15:0] _U1077_out; -wire [15:0] _U1079_out; -wire [15:0] _U1080_out; -wire [15:0] _U1081_out; -wire [15:0] _U1082_out; -wire [15:0] _U1084_out; -wire [15:0] _U1085_out; -wire [15:0] _U1086_out; -wire [15:0] _U1087_out; -wire [15:0] _U1088_out; -wire [15:0] _U1089_out; -wire [15:0] _U1090_out; -wire [15:0] _U1091_out; -wire [15:0] _U1092_out; -wire [15:0] _U1093_out; -wire [15:0] _U1094_out; -wire [15:0] _U1095_out; -wire [15:0] _U1096_out; -wire [15:0] _U1098_out; -wire [15:0] _U1099_out; -wire [15:0] _U1100_out; -wire [15:0] _U1101_out; -wire [15:0] _U1102_out; -wire [15:0] _U1104_out; -wire [15:0] _U1105_out; -wire [15:0] _U1107_out; -wire [15:0] _U1108_out; -wire [15:0] _U1109_out; -wire [15:0] _U1110_out; -wire [15:0] _U1111_out; -wire [15:0] _U1112_out; -wire [15:0] _U1113_out; -wire [15:0] _U1114_out; -wire [15:0] _U1115_out; -wire [15:0] _U1117_out; -wire [15:0] _U1118_out; -wire [15:0] _U1119_out; -wire [15:0] _U1121_out; -wire [15:0] _U1122_out; -wire [15:0] _U1123_out; -wire [15:0] _U1125_out; -wire [15:0] _U1126_out; -wire [15:0] _U1127_out; -wire [15:0] _U1128_out; -wire [15:0] _U1129_out; -wire [15:0] _U1130_out; -wire [15:0] _U1131_out; -wire [15:0] _U1132_out; -wire [15:0] _U1133_out; -wire [15:0] _U1135_out; -wire [15:0] _U1136_out; -wire [15:0] _U1137_out; -wire [15:0] _U1138_out; -wire [15:0] _U1139_out; -wire [15:0] _U1141_out; -wire [15:0] _U1142_out; -wire [15:0] _U1143_out; -wire [15:0] _U1144_out; -wire [15:0] _U1145_out; -wire [15:0] _U1146_out; -wire [15:0] _U1148_out; -wire [15:0] _U1149_out; -wire [15:0] _U1150_out; -wire [15:0] _U1151_out; -wire [15:0] _U1152_out; -wire [15:0] _U1153_out; -wire [15:0] _U1154_out; -wire [15:0] _U1156_out; -wire [15:0] _U1157_out; -wire [15:0] _U1158_out; -wire [15:0] _U1159_out; -wire [15:0] _U1160_out; -wire [15:0] _U1161_out; -wire [15:0] _U1162_out; -wire [15:0] _U1164_out; -wire [15:0] _U1166_out; -wire [15:0] _U1168_out; -wire [15:0] _U1169_out; -wire [15:0] _U1170_out; -wire [15:0] _U1171_out; -wire [15:0] _U1172_out; -wire [15:0] _U1173_out; -wire [15:0] _U1174_out; -wire [15:0] _U1175_out; -wire [15:0] _U1176_out; -wire [15:0] _U1177_out; -wire [15:0] _U1178_out; -wire [15:0] _U1180_out; -wire [15:0] _U1181_out; -wire [15:0] _U1183_out; -wire [15:0] _U1184_out; -wire [15:0] _U1186_out; -wire [15:0] _U1187_out; -wire [15:0] _U1188_out; -wire [15:0] _U1189_out; -wire [15:0] _U1190_out; -wire [15:0] _U1191_out; -wire [15:0] _U1192_out; -wire [15:0] _U1193_out; -wire [15:0] _U1195_out; -wire [15:0] _U1196_out; -wire [15:0] _U1197_out; -wire [15:0] _U1198_out; -wire [15:0] _U1199_out; -wire [15:0] _U1201_out; -wire [15:0] _U1202_out; -wire [15:0] _U1203_out; -wire [15:0] _U1204_out; -wire [15:0] _U1205_out; -wire [15:0] _U1206_out; -wire [15:0] _U1208_out; -wire [15:0] _U1209_out; -wire [15:0] _U1211_out; -wire [15:0] _U1212_out; -wire [15:0] _U1214_out; -wire [15:0] _U1215_out; -wire [15:0] _U1216_out; -wire [15:0] _U1217_out; -wire [15:0] _U1218_out; -wire [15:0] _U1219_out; -wire [15:0] _U1220_out; -wire [15:0] _U1222_out; -wire [15:0] _U1223_out; -wire [15:0] _U1225_out; -wire [15:0] _U1226_out; -wire [15:0] _U1227_out; -wire [15:0] _U1228_out; -wire [15:0] _U1230_out; -wire [15:0] _U1233_out; -wire [15:0] _U1235_out; -wire [15:0] _U1236_out; -wire [15:0] _U1238_out; -wire [15:0] _U1239_out; -wire [15:0] add_1053_1067_1068_out; -wire [15:0] add_1054_1065_1066_out; -wire [15:0] add_1055_1064_1065_out; -wire [15:0] add_1056_1063_1064_out; -wire [15:0] add_1057_1062_1063_out; -wire [15:0] add_1058_1061_1062_out; -wire [15:0] add_1059_1060_1061_out; -wire [15:0] add_conv_stencil_6_1066_1067_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059_out; -wire [15:0] mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060_out; -_U1039_pt__U1040 _U1039 ( - .in(_U1048_out), - .out(_U1039_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1041 ( - .in(mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053_out), - .clk(clk), - .out(_U1041_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1042 ( - .in(_U1041_out), - .clk(clk), - .out(_U1042_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1043 ( - .in(_U1042_out), - .clk(clk), - .out(_U1043_out) -); +wire [15:0] _U100_out; +wire [15:0] _U101_out; +wire [15:0] _U103_out; +wire [15:0] _U104_out; +wire [15:0] _U106_out; +wire [15:0] _U107_out; +wire [15:0] _U108_out; +wire [15:0] _U110_out; +wire [15:0] _U111_out; +wire [15:0] _U113_out; +wire [15:0] _U114_out; +wire [15:0] _U115_out; +wire [15:0] _U116_out; +wire [15:0] _U117_out; +wire [15:0] _U118_out; +wire [15:0] _U119_out; +wire [15:0] _U120_out; +wire [15:0] _U121_out; +wire [15:0] _U122_out; +wire [15:0] _U123_out; +wire [15:0] _U124_out; +wire [15:0] _U125_out; +wire [15:0] _U126_out; +wire [15:0] _U127_out; +wire [15:0] _U129_out; +wire [15:0] _U131_out; +wire [15:0] _U133_out; +wire [15:0] _U134_out; +wire [15:0] _U136_out; +wire [15:0] _U139_out; +wire [15:0] _U141_out; +wire [15:0] _U142_out; +wire [15:0] _U143_out; +wire [15:0] _U144_out; +wire [15:0] _U145_out; +wire [15:0] _U146_out; +wire [15:0] _U147_out; +wire [15:0] _U148_out; +wire [15:0] _U149_out; +wire [15:0] _U150_out; +wire [15:0] _U151_out; +wire [15:0] _U152_out; +wire [15:0] _U153_out; +wire [15:0] _U155_out; +wire [15:0] _U156_out; +wire [15:0] _U158_out; +wire [15:0] _U159_out; +wire [15:0] _U161_out; +wire [15:0] _U162_out; +wire [15:0] _U163_out; +wire [15:0] _U164_out; +wire [15:0] _U165_out; +wire [15:0] _U166_out; +wire [15:0] _U167_out; +wire [15:0] _U168_out; +wire [15:0] _U169_out; +wire [15:0] _U170_out; +wire [15:0] _U171_out; +wire [15:0] _U173_out; +wire [15:0] _U174_out; +wire [15:0] _U176_out; +wire [15:0] _U177_out; +wire [15:0] _U178_out; +wire [15:0] _U179_out; +wire [15:0] _U180_out; +wire [15:0] _U181_out; +wire [15:0] _U182_out; +wire [15:0] _U183_out; +wire [15:0] _U184_out; +wire [15:0] _U186_out; +wire [15:0] _U187_out; +wire [15:0] _U189_out; +wire [15:0] _U190_out; +wire [15:0] _U191_out; +wire [15:0] _U192_out; +wire [15:0] _U193_out; +wire [15:0] _U194_out; +wire [15:0] _U195_out; +wire [15:0] _U197_out; +wire [15:0] _U198_out; +wire [15:0] _U200_out; +wire [15:0] _U201_out; +wire [15:0] _U202_out; +wire [15:0] _U203_out; +wire [15:0] _U204_out; +wire [15:0] _U205_out; +wire [15:0] _U206_out; +wire [15:0] _U207_out; +wire [15:0] _U209_out; +wire [15:0] _U210_out; +wire [15:0] _U211_out; +wire [15:0] _U212_out; +wire [15:0] _U213_out; +wire [15:0] _U214_out; +wire [15:0] _U215_out; +wire [15:0] _U216_out; +wire [15:0] _U218_out; +wire [15:0] _U219_out; +wire [15:0] _U220_out; +wire [15:0] _U221_out; +wire [15:0] _U222_out; +wire [15:0] _U223_out; +wire [15:0] _U224_out; +wire [15:0] _U225_out; +wire [15:0] _U226_out; +wire [15:0] _U227_out; +wire [15:0] _U228_out; +wire [15:0] _U229_out; +wire [15:0] _U230_out; +wire [15:0] _U231_out; +wire [15:0] _U232_out; +wire [15:0] _U32_out; +wire [15:0] _U34_out; +wire [15:0] _U35_out; +wire [15:0] _U37_out; +wire [15:0] _U38_out; +wire [15:0] _U39_out; +wire [15:0] _U41_out; +wire [15:0] _U42_out; +wire [15:0] _U43_out; +wire [15:0] _U45_out; +wire [15:0] _U46_out; +wire [15:0] _U47_out; +wire [15:0] _U48_out; +wire [15:0] _U50_out; +wire [15:0] _U51_out; +wire [15:0] _U52_out; +wire [15:0] _U53_out; +wire [15:0] _U55_out; +wire [15:0] _U56_out; +wire [15:0] _U57_out; +wire [15:0] _U58_out; +wire [15:0] _U59_out; +wire [15:0] _U61_out; +wire [15:0] _U62_out; +wire [15:0] _U63_out; +wire [15:0] _U64_out; +wire [15:0] _U65_out; +wire [15:0] _U67_out; +wire [15:0] _U68_out; +wire [15:0] _U69_out; +wire [15:0] _U70_out; +wire [15:0] _U71_out; +wire [15:0] _U72_out; +wire [15:0] _U74_out; +wire [15:0] _U75_out; +wire [15:0] _U76_out; +wire [15:0] _U77_out; +wire [15:0] _U78_out; +wire [15:0] _U79_out; +wire [15:0] _U81_out; +wire [15:0] _U82_out; +wire [15:0] _U83_out; +wire [15:0] _U84_out; +wire [15:0] _U85_out; +wire [15:0] _U86_out; +wire [15:0] _U87_out; +wire [15:0] _U89_out; +wire [15:0] _U90_out; +wire [15:0] _U91_out; +wire [15:0] _U92_out; +wire [15:0] _U93_out; +wire [15:0] _U94_out; +wire [15:0] _U95_out; +wire [15:0] _U97_out; +wire [15:0] _U98_out; +wire [15:0] _U99_out; +wire [15:0] add_718_732_733_out; +wire [15:0] add_719_730_731_out; +wire [15:0] add_720_729_730_out; +wire [15:0] add_721_728_729_out; +wire [15:0] add_722_727_728_out; +wire [15:0] add_723_726_727_out; +wire [15:0] add_724_725_726_out; +wire [15:0] add_conv_stencil_1_731_732_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724_out; +wire [15:0] mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725_out; mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1044 ( - .in(_U1043_out), +) _U100 ( + .in(_U99_out), .clk(clk), - .out(_U1044_out) + .out(_U100_out) +); +_U101_pt__U102 _U101 ( + .in(_U103_out), + .out(_U101_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1045 ( - .in(_U1044_out), +) _U103 ( + .in(add_724_725_726_out), .clk(clk), - .out(_U1045_out) + .out(_U103_out) +); +_U104_pt__U105 _U104 ( + .in(_U107_out), + .out(_U104_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1046 ( - .in(_U1045_out), +) _U106 ( + .in(mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724_out), .clk(clk), - .out(_U1046_out) + .out(_U106_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1047 ( - .in(_U1046_out), +) _U107 ( + .in(_U106_out), .clk(clk), - .out(_U1047_out) + .out(_U107_out) +); +_U108_pt__U109 _U108 ( + .in(_U110_out), + .out(_U108_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1048 ( - .in(_U1047_out), +) _U110 ( + .in(mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725_out), .clk(clk), - .out(_U1048_out) + .out(_U110_out) ); -_U1049_pt__U1050 _U1049 ( - .in(_U1064_out), - .out(_U1049_out) +_U111_pt__U112 _U111 ( + .in(_U126_out), + .out(_U111_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1051 ( +) _U113 ( .in(in0_conv_stencil[0]), .clk(clk), - .out(_U1051_out) + .out(_U113_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1052 ( - .in(_U1051_out), +) _U114 ( + .in(_U113_out), .clk(clk), - .out(_U1052_out) + .out(_U114_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1053 ( - .in(_U1052_out), +) _U115 ( + .in(_U114_out), .clk(clk), - .out(_U1053_out) + .out(_U115_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1054 ( - .in(_U1053_out), +) _U116 ( + .in(_U115_out), .clk(clk), - .out(_U1054_out) + .out(_U116_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1055 ( - .in(_U1054_out), +) _U117 ( + .in(_U116_out), .clk(clk), - .out(_U1055_out) + .out(_U117_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1056 ( - .in(_U1055_out), +) _U118 ( + .in(_U117_out), .clk(clk), - .out(_U1056_out) + .out(_U118_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1057 ( - .in(_U1056_out), +) _U119 ( + .in(_U118_out), .clk(clk), - .out(_U1057_out) + .out(_U119_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1058 ( - .in(_U1057_out), +) _U120 ( + .in(_U119_out), .clk(clk), - .out(_U1058_out) + .out(_U120_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1059 ( - .in(_U1058_out), +) _U121 ( + .in(_U120_out), .clk(clk), - .out(_U1059_out) + .out(_U121_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1060 ( - .in(_U1059_out), +) _U122 ( + .in(_U121_out), .clk(clk), - .out(_U1060_out) + .out(_U122_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1061 ( - .in(_U1060_out), +) _U123 ( + .in(_U122_out), .clk(clk), - .out(_U1061_out) + .out(_U123_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1062 ( - .in(_U1061_out), +) _U124 ( + .in(_U123_out), .clk(clk), - .out(_U1062_out) + .out(_U124_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1063 ( - .in(_U1062_out), +) _U125 ( + .in(_U124_out), .clk(clk), - .out(_U1063_out) + .out(_U125_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1064 ( - .in(_U1063_out), +) _U126 ( + .in(_U125_out), .clk(clk), - .out(_U1064_out) -); -_U1065_pt__U1066 _U1065 ( - .in(_U1073_out), - .out(_U1065_out) + .out(_U126_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1067 ( +_U127_pt__U128 _U127 ( .in(in2_hw_kernel_global_wrapper_stencil[0]), - .clk(clk), - .out(_U1067_out) + .out(_U127_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1068 ( - .in(_U1067_out), - .clk(clk), - .out(_U1068_out) +_U129_pt__U130 _U129 ( + .in(in1_hw_input_global_wrapper_stencil[0]), + .out(_U129_out) +); +_U131_pt__U132 _U131 ( + .in(_U133_out), + .out(_U131_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1069 ( - .in(_U1068_out), +) _U133 ( + .in(in2_hw_kernel_global_wrapper_stencil[1]), .clk(clk), - .out(_U1069_out) + .out(_U133_out) +); +_U134_pt__U135 _U134 ( + .in(_U136_out), + .out(_U134_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1070 ( - .in(_U1069_out), +) _U136 ( + .in(add_conv_stencil_1_731_732_out), .clk(clk), - .out(_U1070_out) + .out(_U136_out) +); +_U137_pt__U138 _U137 ( + .in(add_718_732_733_out), + .out(out_conv_stencil) +); +_U139_pt__U140 _U139 ( + .in(_U152_out), + .out(_U139_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1071 ( - .in(_U1070_out), +) _U141 ( + .in(mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719_out), .clk(clk), - .out(_U1071_out) + .out(_U141_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1072 ( - .in(_U1071_out), +) _U142 ( + .in(_U141_out), .clk(clk), - .out(_U1072_out) + .out(_U142_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1073 ( - .in(_U1072_out), +) _U143 ( + .in(_U142_out), .clk(clk), - .out(_U1073_out) -); -_U1074_pt__U1075 _U1074 ( - .in(_U1076_out), - .out(_U1074_out) + .out(_U143_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1076 ( - .in(add_1055_1064_1065_out), +) _U144 ( + .in(_U143_out), .clk(clk), - .out(_U1076_out) -); -_U1077_pt__U1078 _U1077 ( - .in(_U1081_out), - .out(_U1077_out) + .out(_U144_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1079 ( - .in(in1_hw_input_global_wrapper_stencil[3]), +) _U145 ( + .in(_U144_out), .clk(clk), - .out(_U1079_out) + .out(_U145_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1080 ( - .in(_U1079_out), +) _U146 ( + .in(_U145_out), .clk(clk), - .out(_U1080_out) + .out(_U146_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1081 ( - .in(_U1080_out), +) _U147 ( + .in(_U146_out), .clk(clk), - .out(_U1081_out) -); -_U1082_pt__U1083 _U1082 ( - .in(_U1095_out), - .out(_U1082_out) + .out(_U147_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1084 ( - .in(mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054_out), +) _U148 ( + .in(_U147_out), .clk(clk), - .out(_U1084_out) + .out(_U148_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1085 ( - .in(_U1084_out), +) _U149 ( + .in(_U148_out), .clk(clk), - .out(_U1085_out) + .out(_U149_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1086 ( - .in(_U1085_out), +) _U150 ( + .in(_U149_out), .clk(clk), - .out(_U1086_out) + .out(_U150_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1087 ( - .in(_U1086_out), +) _U151 ( + .in(_U150_out), .clk(clk), - .out(_U1087_out) + .out(_U151_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1088 ( - .in(_U1087_out), +) _U152 ( + .in(_U151_out), .clk(clk), - .out(_U1088_out) + .out(_U152_out) +); +_U153_pt__U154 _U153 ( + .in(_U155_out), + .out(_U153_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1089 ( - .in(_U1088_out), +) _U155 ( + .in(add_720_729_730_out), .clk(clk), - .out(_U1089_out) + .out(_U155_out) +); +_U156_pt__U157 _U156 ( + .in(_U158_out), + .out(_U156_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1090 ( - .in(_U1089_out), +) _U158 ( + .in(add_719_730_731_out), .clk(clk), - .out(_U1090_out) + .out(_U158_out) +); +_U159_pt__U160 _U159 ( + .in(_U170_out), + .out(_U159_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1091 ( - .in(_U1090_out), +) _U161 ( + .in(mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720_out), .clk(clk), - .out(_U1091_out) + .out(_U161_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1092 ( - .in(_U1091_out), +) _U162 ( + .in(_U161_out), .clk(clk), - .out(_U1092_out) + .out(_U162_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1093 ( - .in(_U1092_out), +) _U163 ( + .in(_U162_out), .clk(clk), - .out(_U1093_out) + .out(_U163_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1094 ( - .in(_U1093_out), +) _U164 ( + .in(_U163_out), .clk(clk), - .out(_U1094_out) + .out(_U164_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1095 ( - .in(_U1094_out), +) _U165 ( + .in(_U164_out), .clk(clk), - .out(_U1095_out) -); -_U1096_pt__U1097 _U1096 ( - .in(_U1101_out), - .out(_U1096_out) + .out(_U165_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1098 ( - .in(mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058_out), +) _U166 ( + .in(_U165_out), .clk(clk), - .out(_U1098_out) + .out(_U166_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1099 ( - .in(_U1098_out), +) _U167 ( + .in(_U166_out), .clk(clk), - .out(_U1099_out) + .out(_U167_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1100 ( - .in(_U1099_out), +) _U168 ( + .in(_U167_out), .clk(clk), - .out(_U1100_out) + .out(_U168_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1101 ( - .in(_U1100_out), +) _U169 ( + .in(_U168_out), .clk(clk), - .out(_U1101_out) -); -_U1102_pt__U1103 _U1102 ( - .in(_U1104_out), - .out(_U1102_out) + .out(_U169_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1104 ( - .in(add_1056_1063_1064_out), +) _U170 ( + .in(_U169_out), .clk(clk), - .out(_U1104_out) + .out(_U170_out) ); -_U1105_pt__U1106 _U1105 ( - .in(_U1114_out), - .out(_U1105_out) +_U171_pt__U172 _U171 ( + .in(_U173_out), + .out(_U171_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1107 ( - .in(mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056_out), +) _U173 ( + .in(add_721_728_729_out), .clk(clk), - .out(_U1107_out) + .out(_U173_out) +); +_U174_pt__U175 _U174 ( + .in(_U183_out), + .out(_U174_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1108 ( - .in(_U1107_out), +) _U176 ( + .in(mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721_out), .clk(clk), - .out(_U1108_out) + .out(_U176_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1109 ( - .in(_U1108_out), +) _U177 ( + .in(_U176_out), .clk(clk), - .out(_U1109_out) + .out(_U177_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1110 ( - .in(_U1109_out), +) _U178 ( + .in(_U177_out), .clk(clk), - .out(_U1110_out) + .out(_U178_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1111 ( - .in(_U1110_out), +) _U179 ( + .in(_U178_out), .clk(clk), - .out(_U1111_out) + .out(_U179_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1112 ( - .in(_U1111_out), +) _U180 ( + .in(_U179_out), .clk(clk), - .out(_U1112_out) + .out(_U180_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1113 ( - .in(_U1112_out), +) _U181 ( + .in(_U180_out), .clk(clk), - .out(_U1113_out) + .out(_U181_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1114 ( - .in(_U1113_out), +) _U182 ( + .in(_U181_out), .clk(clk), - .out(_U1114_out) -); -_U1115_pt__U1116 _U1115 ( - .in(_U1118_out), - .out(_U1115_out) + .out(_U182_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1117 ( - .in(in1_hw_input_global_wrapper_stencil[2]), +) _U183 ( + .in(_U182_out), .clk(clk), - .out(_U1117_out) + .out(_U183_out) +); +_U184_pt__U185 _U184 ( + .in(_U186_out), + .out(_U184_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1118 ( - .in(_U1117_out), +) _U186 ( + .in(add_722_727_728_out), .clk(clk), - .out(_U1118_out) + .out(_U186_out) ); -_U1119_pt__U1120 _U1119 ( - .in(_U1122_out), - .out(_U1119_out) +_U187_pt__U188 _U187 ( + .in(_U194_out), + .out(_U187_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1121 ( - .in(mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059_out), +) _U189 ( + .in(mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722_out), .clk(clk), - .out(_U1121_out) + .out(_U189_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1122 ( - .in(_U1121_out), +) _U190 ( + .in(_U189_out), .clk(clk), - .out(_U1122_out) -); -_U1123_pt__U1124 _U1123 ( - .in(_U1132_out), - .out(_U1123_out) + .out(_U190_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1125 ( - .in(mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060_out), +) _U191 ( + .in(_U190_out), .clk(clk), - .out(_U1125_out) + .out(_U191_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1126 ( - .in(_U1125_out), +) _U192 ( + .in(_U191_out), .clk(clk), - .out(_U1126_out) + .out(_U192_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1127 ( - .in(_U1126_out), +) _U193 ( + .in(_U192_out), .clk(clk), - .out(_U1127_out) + .out(_U193_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1128 ( - .in(_U1127_out), +) _U194 ( + .in(_U193_out), .clk(clk), - .out(_U1128_out) + .out(_U194_out) +); +_U195_pt__U196 _U195 ( + .in(_U197_out), + .out(_U195_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1129 ( - .in(_U1128_out), +) _U197 ( + .in(add_723_726_727_out), .clk(clk), - .out(_U1129_out) + .out(_U197_out) +); +_U198_pt__U199 _U198 ( + .in(_U206_out), + .out(_U198_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1130 ( - .in(_U1129_out), +) _U200 ( + .in(in2_hw_kernel_global_wrapper_stencil[7]), .clk(clk), - .out(_U1130_out) + .out(_U200_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1131 ( - .in(_U1130_out), +) _U201 ( + .in(_U200_out), .clk(clk), - .out(_U1131_out) + .out(_U201_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1132 ( - .in(_U1131_out), +) _U202 ( + .in(_U201_out), .clk(clk), - .out(_U1132_out) -); -_U1133_pt__U1134 _U1133 ( - .in(_U1138_out), - .out(_U1133_out) + .out(_U202_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1135 ( - .in(in2_hw_kernel_global_wrapper_stencil[4]), +) _U203 ( + .in(_U202_out), .clk(clk), - .out(_U1135_out) + .out(_U203_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1136 ( - .in(_U1135_out), +) _U204 ( + .in(_U203_out), .clk(clk), - .out(_U1136_out) + .out(_U204_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1137 ( - .in(_U1136_out), +) _U205 ( + .in(_U204_out), .clk(clk), - .out(_U1137_out) + .out(_U205_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1138 ( - .in(_U1137_out), +) _U206 ( + .in(_U205_out), .clk(clk), - .out(_U1138_out) + .out(_U206_out) ); -_U1139_pt__U1140 _U1139 ( - .in(_U1145_out), - .out(_U1139_out) +_U207_pt__U208 _U207 ( + .in(_U215_out), + .out(_U207_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1141 ( - .in(in1_hw_input_global_wrapper_stencil[5]), +) _U209 ( + .in(in1_hw_input_global_wrapper_stencil[7]), .clk(clk), - .out(_U1141_out) + .out(_U209_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1142 ( - .in(_U1141_out), +) _U210 ( + .in(_U209_out), .clk(clk), - .out(_U1142_out) + .out(_U210_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1143 ( - .in(_U1142_out), +) _U211 ( + .in(_U210_out), .clk(clk), - .out(_U1143_out) + .out(_U211_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1144 ( - .in(_U1143_out), +) _U212 ( + .in(_U211_out), .clk(clk), - .out(_U1144_out) + .out(_U212_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1145 ( - .in(_U1144_out), +) _U213 ( + .in(_U212_out), .clk(clk), - .out(_U1145_out) -); -_U1146_pt__U1147 _U1146 ( - .in(_U1153_out), - .out(_U1146_out) + .out(_U213_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1148 ( - .in(in2_hw_kernel_global_wrapper_stencil[6]), +) _U214 ( + .in(_U213_out), .clk(clk), - .out(_U1148_out) + .out(_U214_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1149 ( - .in(_U1148_out), +) _U215 ( + .in(_U214_out), .clk(clk), - .out(_U1149_out) + .out(_U215_out) +); +_U216_pt__U217 _U216 ( + .in(_U232_out), + .out(_U216_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1150 ( - .in(_U1149_out), +) _U218 ( + .in(mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718_out), .clk(clk), - .out(_U1150_out) + .out(_U218_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1151 ( - .in(_U1150_out), +) _U219 ( + .in(_U218_out), .clk(clk), - .out(_U1151_out) + .out(_U219_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1152 ( - .in(_U1151_out), +) _U220 ( + .in(_U219_out), .clk(clk), - .out(_U1152_out) + .out(_U220_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1153 ( - .in(_U1152_out), +) _U221 ( + .in(_U220_out), .clk(clk), - .out(_U1153_out) -); -_U1154_pt__U1155 _U1154 ( - .in(_U1161_out), - .out(_U1154_out) + .out(_U221_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1156 ( - .in(in1_hw_input_global_wrapper_stencil[6]), +) _U222 ( + .in(_U221_out), .clk(clk), - .out(_U1156_out) + .out(_U222_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1157 ( - .in(_U1156_out), +) _U223 ( + .in(_U222_out), .clk(clk), - .out(_U1157_out) + .out(_U223_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1158 ( - .in(_U1157_out), +) _U224 ( + .in(_U223_out), .clk(clk), - .out(_U1158_out) + .out(_U224_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1159 ( - .in(_U1158_out), +) _U225 ( + .in(_U224_out), .clk(clk), - .out(_U1159_out) + .out(_U225_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1160 ( - .in(_U1159_out), +) _U226 ( + .in(_U225_out), .clk(clk), - .out(_U1160_out) + .out(_U226_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1161 ( - .in(_U1160_out), +) _U227 ( + .in(_U226_out), .clk(clk), - .out(_U1161_out) -); -_U1162_pt__U1163 _U1162 ( - .in(in1_hw_input_global_wrapper_stencil[7]), - .out(_U1162_out) -); -_U1164_pt__U1165 _U1164 ( - .in(in2_hw_kernel_global_wrapper_stencil[7]), - .out(_U1164_out) -); -_U1166_pt__U1167 _U1166 ( - .in(_U1177_out), - .out(_U1166_out) + .out(_U227_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1168 ( - .in(mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055_out), +) _U228 ( + .in(_U227_out), .clk(clk), - .out(_U1168_out) + .out(_U228_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1169 ( - .in(_U1168_out), +) _U229 ( + .in(_U228_out), .clk(clk), - .out(_U1169_out) + .out(_U229_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1170 ( - .in(_U1169_out), +) _U230 ( + .in(_U229_out), .clk(clk), - .out(_U1170_out) + .out(_U230_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1171 ( - .in(_U1170_out), +) _U231 ( + .in(_U230_out), .clk(clk), - .out(_U1171_out) + .out(_U231_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1172 ( - .in(_U1171_out), +) _U232 ( + .in(_U231_out), .clk(clk), - .out(_U1172_out) + .out(_U232_out) +); +_U32_pt__U33 _U32 ( + .in(_U34_out), + .out(_U32_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1173 ( - .in(_U1172_out), +) _U34 ( + .in(in1_hw_input_global_wrapper_stencil[1]), .clk(clk), - .out(_U1173_out) + .out(_U34_out) +); +_U35_pt__U36 _U35 ( + .in(_U38_out), + .out(_U35_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1174 ( - .in(_U1173_out), +) _U37 ( + .in(in2_hw_kernel_global_wrapper_stencil[2]), .clk(clk), - .out(_U1174_out) + .out(_U37_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1175 ( - .in(_U1174_out), +) _U38 ( + .in(_U37_out), .clk(clk), - .out(_U1175_out) + .out(_U38_out) +); +_U39_pt__U40 _U39 ( + .in(_U42_out), + .out(_U39_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1176 ( - .in(_U1175_out), +) _U41 ( + .in(in1_hw_input_global_wrapper_stencil[2]), .clk(clk), - .out(_U1176_out) + .out(_U41_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1177 ( - .in(_U1176_out), +) _U42 ( + .in(_U41_out), .clk(clk), - .out(_U1177_out) + .out(_U42_out) ); -_U1178_pt__U1179 _U1178 ( - .in(_U1180_out), - .out(_U1178_out) +_U43_pt__U44 _U43 ( + .in(_U47_out), + .out(_U43_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1180 ( - .in(add_1054_1065_1066_out), +) _U45 ( + .in(in2_hw_kernel_global_wrapper_stencil[3]), .clk(clk), - .out(_U1180_out) + .out(_U45_out) ); -_U1181_pt__U1182 _U1181 ( - .in(_U1183_out), - .out(_U1181_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U46 ( + .in(_U45_out), + .clk(clk), + .out(_U46_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1183 ( - .in(add_1059_1060_1061_out), +) _U47 ( + .in(_U46_out), .clk(clk), - .out(_U1183_out) + .out(_U47_out) ); -_U1184_pt__U1185 _U1184 ( - .in(_U1192_out), - .out(_U1184_out) +_U48_pt__U49 _U48 ( + .in(_U52_out), + .out(_U48_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1186 ( - .in(in1_hw_input_global_wrapper_stencil[0]), +) _U50 ( + .in(in1_hw_input_global_wrapper_stencil[3]), .clk(clk), - .out(_U1186_out) + .out(_U50_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1187 ( - .in(_U1186_out), +) _U51 ( + .in(_U50_out), .clk(clk), - .out(_U1187_out) + .out(_U51_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1188 ( - .in(_U1187_out), +) _U52 ( + .in(_U51_out), .clk(clk), - .out(_U1188_out) + .out(_U52_out) +); +_U53_pt__U54 _U53 ( + .in(_U58_out), + .out(_U53_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1189 ( - .in(_U1188_out), +) _U55 ( + .in(in2_hw_kernel_global_wrapper_stencil[4]), .clk(clk), - .out(_U1189_out) + .out(_U55_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1190 ( - .in(_U1189_out), +) _U56 ( + .in(_U55_out), .clk(clk), - .out(_U1190_out) + .out(_U56_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1191 ( - .in(_U1190_out), +) _U57 ( + .in(_U56_out), .clk(clk), - .out(_U1191_out) + .out(_U57_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1192 ( - .in(_U1191_out), +) _U58 ( + .in(_U57_out), .clk(clk), - .out(_U1192_out) + .out(_U58_out) ); -_U1193_pt__U1194 _U1193 ( - .in(_U1198_out), - .out(_U1193_out) +_U59_pt__U60 _U59 ( + .in(_U64_out), + .out(_U59_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1195 ( +) _U61 ( .in(in1_hw_input_global_wrapper_stencil[4]), .clk(clk), - .out(_U1195_out) + .out(_U61_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1196 ( - .in(_U1195_out), +) _U62 ( + .in(_U61_out), .clk(clk), - .out(_U1196_out) + .out(_U62_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1197 ( - .in(_U1196_out), +) _U63 ( + .in(_U62_out), .clk(clk), - .out(_U1197_out) + .out(_U63_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1198 ( - .in(_U1197_out), +) _U64 ( + .in(_U63_out), .clk(clk), - .out(_U1198_out) + .out(_U64_out) ); -_U1199_pt__U1200 _U1199 ( - .in(_U1205_out), - .out(_U1199_out) +_U65_pt__U66 _U65 ( + .in(_U71_out), + .out(_U65_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1201 ( +) _U67 ( .in(in2_hw_kernel_global_wrapper_stencil[5]), .clk(clk), - .out(_U1201_out) + .out(_U67_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1202 ( - .in(_U1201_out), +) _U68 ( + .in(_U67_out), .clk(clk), - .out(_U1202_out) + .out(_U68_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1203 ( - .in(_U1202_out), +) _U69 ( + .in(_U68_out), .clk(clk), - .out(_U1203_out) + .out(_U69_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1204 ( - .in(_U1203_out), +) _U70 ( + .in(_U69_out), .clk(clk), - .out(_U1204_out) + .out(_U70_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1205 ( - .in(_U1204_out), +) _U71 ( + .in(_U70_out), .clk(clk), - .out(_U1205_out) + .out(_U71_out) ); -_U1206_pt__U1207 _U1206 ( - .in(_U1208_out), - .out(_U1206_out) +_U72_pt__U73 _U72 ( + .in(_U78_out), + .out(_U72_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1208 ( - .in(in2_hw_kernel_global_wrapper_stencil[1]), +) _U74 ( + .in(in1_hw_input_global_wrapper_stencil[5]), .clk(clk), - .out(_U1208_out) + .out(_U74_out) ); -_U1209_pt__U1210 _U1209 ( - .in(_U1211_out), - .out(_U1209_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U75 ( + .in(_U74_out), + .clk(clk), + .out(_U75_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1211 ( - .in(add_1057_1062_1063_out), +) _U76 ( + .in(_U75_out), .clk(clk), - .out(_U1211_out) + .out(_U76_out) ); -_U1212_pt__U1213 _U1212 ( - .in(_U1219_out), - .out(_U1212_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U77 ( + .in(_U76_out), + .clk(clk), + .out(_U77_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1214 ( - .in(mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057_out), +) _U78 ( + .in(_U77_out), .clk(clk), - .out(_U1214_out) + .out(_U78_out) +); +_U79_pt__U80 _U79 ( + .in(_U86_out), + .out(_U79_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1215 ( - .in(_U1214_out), +) _U81 ( + .in(in2_hw_kernel_global_wrapper_stencil[6]), .clk(clk), - .out(_U1215_out) + .out(_U81_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1216 ( - .in(_U1215_out), +) _U82 ( + .in(_U81_out), .clk(clk), - .out(_U1216_out) + .out(_U82_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1217 ( - .in(_U1216_out), +) _U83 ( + .in(_U82_out), .clk(clk), - .out(_U1217_out) + .out(_U83_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1218 ( - .in(_U1217_out), +) _U84 ( + .in(_U83_out), .clk(clk), - .out(_U1218_out) + .out(_U84_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1219 ( - .in(_U1218_out), +) _U85 ( + .in(_U84_out), .clk(clk), - .out(_U1219_out) + .out(_U85_out) ); -_U1220_pt__U1221 _U1220 ( - .in(_U1222_out), - .out(_U1220_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U86 ( + .in(_U85_out), + .clk(clk), + .out(_U86_out) +); +_U87_pt__U88 _U87 ( + .in(_U94_out), + .out(_U87_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1222 ( - .in(add_1058_1061_1062_out), +) _U89 ( + .in(in1_hw_input_global_wrapper_stencil[6]), .clk(clk), - .out(_U1222_out) + .out(_U89_out) ); -_U1223_pt__U1224 _U1223 ( - .in(_U1227_out), - .out(_U1223_out) +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U90 ( + .in(_U89_out), + .clk(clk), + .out(_U90_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1225 ( - .in(in2_hw_kernel_global_wrapper_stencil[3]), +) _U91 ( + .in(_U90_out), .clk(clk), - .out(_U1225_out) + .out(_U91_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1226 ( - .in(_U1225_out), +) _U92 ( + .in(_U91_out), .clk(clk), - .out(_U1226_out) + .out(_U92_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1227 ( - .in(_U1226_out), +) _U93 ( + .in(_U92_out), .clk(clk), - .out(_U1227_out) -); -_U1228_pt__U1229 _U1228 ( - .in(_U1230_out), - .out(_U1228_out) + .out(_U93_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1230 ( - .in(add_conv_stencil_6_1066_1067_out), +) _U94 ( + .in(_U93_out), .clk(clk), - .out(_U1230_out) -); -_U1231_pt__U1232 _U1231 ( - .in(add_1053_1067_1068_out), - .out(out_conv_stencil) + .out(_U94_out) ); -_U1233_pt__U1234 _U1233 ( - .in(_U1235_out), - .out(_U1233_out) +_U95_pt__U96 _U95 ( + .in(_U100_out), + .out(_U95_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1235 ( - .in(in1_hw_input_global_wrapper_stencil[1]), +) _U97 ( + .in(mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723_out), .clk(clk), - .out(_U1235_out) -); -_U1236_pt__U1237 _U1236 ( - .in(_U1239_out), - .out(_U1236_out) + .out(_U97_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1238 ( - .in(in2_hw_kernel_global_wrapper_stencil[2]), +) _U98 ( + .in(_U97_out), .clk(clk), - .out(_U1238_out) + .out(_U98_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1239 ( - .in(_U1238_out), +) _U99 ( + .in(_U98_out), .clk(clk), - .out(_U1239_out) + .out(_U99_out) ); -assign add_1053_1067_1068_out = 16'(_U1039_out + _U1228_out); -assign add_1054_1065_1066_out = 16'(_U1082_out + _U1074_out); -assign add_1055_1064_1065_out = 16'(_U1166_out + _U1102_out); -assign add_1056_1063_1064_out = 16'(_U1105_out + _U1209_out); -assign add_1057_1062_1063_out = 16'(_U1212_out + _U1220_out); -assign add_1058_1061_1062_out = 16'(_U1096_out + _U1181_out); -assign add_1059_1060_1061_out = 16'(_U1119_out + _U1123_out); -assign add_conv_stencil_6_1066_1067_out = 16'(_U1049_out + _U1178_out); -assign mul_hw_kernel_global_wrapper_stencil_41_hw_input_global_wrapper_stencil_41_1053_out = 16'(_U1065_out * _U1184_out); -assign mul_hw_kernel_global_wrapper_stencil_42_hw_input_global_wrapper_stencil_42_1054_out = 16'(_U1206_out * _U1233_out); -assign mul_hw_kernel_global_wrapper_stencil_43_hw_input_global_wrapper_stencil_43_1055_out = 16'(_U1236_out * _U1115_out); -assign mul_hw_kernel_global_wrapper_stencil_44_hw_input_global_wrapper_stencil_44_1056_out = 16'(_U1223_out * _U1077_out); -assign mul_hw_kernel_global_wrapper_stencil_45_hw_input_global_wrapper_stencil_45_1057_out = 16'(_U1133_out * _U1193_out); -assign mul_hw_kernel_global_wrapper_stencil_46_hw_input_global_wrapper_stencil_46_1058_out = 16'(_U1199_out * _U1139_out); -assign mul_hw_kernel_global_wrapper_stencil_47_hw_input_global_wrapper_stencil_47_1059_out = 16'(_U1146_out * _U1154_out); -assign mul_hw_kernel_global_wrapper_stencil_48_hw_input_global_wrapper_stencil_48_1060_out = 16'(_U1164_out * _U1162_out); +assign add_718_732_733_out = 16'(_U216_out + _U134_out); +assign add_719_730_731_out = 16'(_U139_out + _U153_out); +assign add_720_729_730_out = 16'(_U159_out + _U171_out); +assign add_721_728_729_out = 16'(_U174_out + _U184_out); +assign add_722_727_728_out = 16'(_U187_out + _U195_out); +assign add_723_726_727_out = 16'(_U95_out + _U101_out); +assign add_724_725_726_out = 16'(_U104_out + _U108_out); +assign add_conv_stencil_1_731_732_out = 16'(_U111_out + _U156_out); +assign mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_718_out = 16'(_U127_out * _U129_out); +assign mul_hw_kernel_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_2_719_out = 16'(_U131_out * _U32_out); +assign mul_hw_kernel_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_3_720_out = 16'(_U35_out * _U39_out); +assign mul_hw_kernel_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_4_721_out = 16'(_U43_out * _U48_out); +assign mul_hw_kernel_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_5_722_out = 16'(_U53_out * _U59_out); +assign mul_hw_kernel_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_6_723_out = 16'(_U65_out * _U72_out); +assign mul_hw_kernel_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_7_724_out = 16'(_U79_out * _U87_out); +assign mul_hw_kernel_global_wrapper_stencil_8_hw_input_global_wrapper_stencil_8_725_out = 16'(_U198_out * _U207_out); endmodule -module cu_op_hcompute_conv_stencil_13 ( +module cu_op_hcompute_conv_stencil_8 ( input clk, - input [15:0] conv_stencil_op_hcompute_conv_stencil_13_read [0:0], - input [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read [7:0], - input [15:0] hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read [7:0], - output [15:0] conv_stencil_op_hcompute_conv_stencil_13_write [0:0] + input [15:0] conv_stencil_op_hcompute_conv_stencil_8_read [0:0], + input [15:0] hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read [7:0], + input [15:0] hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read [7:0], + output [15:0] conv_stencil_op_hcompute_conv_stencil_8_write [0:0] ); wire [15:0] inner_compute_out_conv_stencil; wire [15:0] inner_compute_in0_conv_stencil [0:0]; -assign inner_compute_in0_conv_stencil[0] = conv_stencil_op_hcompute_conv_stencil_13_read[0]; +assign inner_compute_in0_conv_stencil[0] = conv_stencil_op_hcompute_conv_stencil_8_read[0]; wire [15:0] inner_compute_in1_hw_input_global_wrapper_stencil [7:0]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[7] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[7]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[6] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[6]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[5] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[5]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[4] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[4]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[3] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[3]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[2] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[2]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[1] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[1]; -assign inner_compute_in1_hw_input_global_wrapper_stencil[0] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[0]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[7] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[7]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[6] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[6]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[5] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[5]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[4] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[4]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[3] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[3]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[2] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[2]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[1] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[1]; +assign inner_compute_in1_hw_input_global_wrapper_stencil[0] = hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[0]; wire [15:0] inner_compute_in2_hw_kernel_global_wrapper_stencil [7:0]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[7] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[7]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[6] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[6]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[5] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[5]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[4] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[4]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[3] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[3]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[2] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[2]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[1] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[1]; -assign inner_compute_in2_hw_kernel_global_wrapper_stencil[0] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_13_read[0]; -hcompute_conv_stencil_13_pipelined inner_compute ( +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[7] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[7]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[6] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[6]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[5] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[5]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[4] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[4]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[3] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[3]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[2] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[2]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[1] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[1]; +assign inner_compute_in2_hw_kernel_global_wrapper_stencil[0] = hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read[0]; +hcompute_conv_stencil_8_pipelined inner_compute ( .clk(clk), .in0_conv_stencil(inner_compute_in0_conv_stencil), .in1_hw_input_global_wrapper_stencil(inner_compute_in1_hw_input_global_wrapper_stencil), .in2_hw_kernel_global_wrapper_stencil(inner_compute_in2_hw_kernel_global_wrapper_stencil), .out_conv_stencil(inner_compute_out_conv_stencil) ); -assign conv_stencil_op_hcompute_conv_stencil_13_write[0] = inner_compute_out_conv_stencil; -endmodule - -module _U1034_pt__U1035 ( - input [15:0] in, - output [15:0] out -); -assign out = in; -endmodule - -module _U1029_pt__U1030 ( - input [15:0] in, - output [15:0] out -); -assign out = in; -endmodule - -module _U1026_pt__U1027 ( - input [15:0] in, - output [15:0] out -); -assign out = in; -endmodule - -module _U1017_pt__U1018 ( - input [15:0] in, - output [15:0] out -); -assign out = in; -endmodule - -module _U1013_pt__U1014 ( - input [15:0] in, - output [15:0] out -); -assign out = in; +assign conv_stencil_op_hcompute_conv_stencil_8_write[0] = inner_compute_out_conv_stencil; endmodule -module _U1011_pt__U1012 ( +module _U1019_pt__U1020 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1007_pt__U1008 ( +module _U1006_pt__U1007 ( input [15:0] in, output [15:0] out ); assign out = in; endmodule -module _U1005_pt__U1006 ( +module _U1002_pt__U1003 ( input [15:0] in, output [15:0] out ); @@ -25328,32 +25328,35 @@ module hcompute_conv_stencil_12_pipelined ( wire [15:0] _U1000_out; wire [15:0] _U1001_out; wire [15:0] _U1002_out; -wire [15:0] _U1003_out; wire [15:0] _U1004_out; wire [15:0] _U1005_out; -wire [15:0] _U1007_out; +wire [15:0] _U1006_out; +wire [15:0] _U1008_out; wire [15:0] _U1009_out; wire [15:0] _U1010_out; wire [15:0] _U1011_out; +wire [15:0] _U1012_out; wire [15:0] _U1013_out; +wire [15:0] _U1014_out; wire [15:0] _U1015_out; wire [15:0] _U1016_out; wire [15:0] _U1017_out; +wire [15:0] _U1018_out; wire [15:0] _U1019_out; -wire [15:0] _U1020_out; wire [15:0] _U1021_out; wire [15:0] _U1022_out; wire [15:0] _U1023_out; wire [15:0] _U1024_out; wire [15:0] _U1025_out; wire [15:0] _U1026_out; -wire [15:0] _U1028_out; +wire [15:0] _U1027_out; wire [15:0] _U1029_out; +wire [15:0] _U1030_out; wire [15:0] _U1031_out; wire [15:0] _U1032_out; wire [15:0] _U1033_out; wire [15:0] _U1034_out; -wire [15:0] _U1036_out; +wire [15:0] _U1035_out; wire [15:0] _U1037_out; wire [15:0] _U1038_out; wire [15:0] _U838_out; @@ -25381,35 +25384,33 @@ wire [15:0] _U864_out; wire [15:0] _U865_out; wire [15:0] _U866_out; wire [15:0] _U867_out; -wire [15:0] _U868_out; -wire [15:0] _U869_out; wire [15:0] _U870_out; wire [15:0] _U872_out; wire [15:0] _U873_out; wire [15:0] _U875_out; wire [15:0] _U876_out; -wire [15:0] _U877_out; wire [15:0] _U878_out; wire [15:0] _U879_out; +wire [15:0] _U880_out; wire [15:0] _U881_out; wire [15:0] _U882_out; wire [15:0] _U883_out; wire [15:0] _U884_out; wire [15:0] _U885_out; -wire [15:0] _U886_out; wire [15:0] _U887_out; wire [15:0] _U888_out; wire [15:0] _U889_out; -wire [15:0] _U890_out; +wire [15:0] _U891_out; wire [15:0] _U892_out; wire [15:0] _U893_out; +wire [15:0] _U894_out; wire [15:0] _U895_out; wire [15:0] _U896_out; wire [15:0] _U897_out; wire [15:0] _U898_out; wire [15:0] _U899_out; +wire [15:0] _U900_out; wire [15:0] _U901_out; -wire [15:0] _U902_out; wire [15:0] _U903_out; wire [15:0] _U904_out; wire [15:0] _U905_out; @@ -25417,11 +25418,13 @@ wire [15:0] _U906_out; wire [15:0] _U907_out; wire [15:0] _U909_out; wire [15:0] _U910_out; +wire [15:0] _U911_out; wire [15:0] _U912_out; wire [15:0] _U913_out; wire [15:0] _U914_out; wire [15:0] _U915_out; wire [15:0] _U916_out; +wire [15:0] _U917_out; wire [15:0] _U918_out; wire [15:0] _U919_out; wire [15:0] _U920_out; @@ -25435,58 +25438,55 @@ wire [15:0] _U928_out; wire [15:0] _U929_out; wire [15:0] _U930_out; wire [15:0] _U931_out; -wire [15:0] _U932_out; wire [15:0] _U933_out; wire [15:0] _U934_out; wire [15:0] _U935_out; wire [15:0] _U936_out; +wire [15:0] _U937_out; wire [15:0] _U938_out; +wire [15:0] _U939_out; wire [15:0] _U941_out; -wire [15:0] _U943_out; +wire [15:0] _U942_out; wire [15:0] _U944_out; wire [15:0] _U945_out; wire [15:0] _U946_out; wire [15:0] _U947_out; wire [15:0] _U948_out; -wire [15:0] _U949_out; wire [15:0] _U950_out; wire [15:0] _U951_out; wire [15:0] _U952_out; wire [15:0] _U953_out; wire [15:0] _U954_out; +wire [15:0] _U955_out; wire [15:0] _U956_out; -wire [15:0] _U957_out; wire [15:0] _U958_out; wire [15:0] _U959_out; -wire [15:0] _U960_out; wire [15:0] _U961_out; +wire [15:0] _U962_out; wire [15:0] _U963_out; wire [15:0] _U964_out; wire [15:0] _U965_out; wire [15:0] _U966_out; wire [15:0] _U967_out; -wire [15:0] _U969_out; +wire [15:0] _U968_out; wire [15:0] _U970_out; -wire [15:0] _U972_out; +wire [15:0] _U971_out; wire [15:0] _U973_out; wire [15:0] _U974_out; -wire [15:0] _U975_out; wire [15:0] _U976_out; wire [15:0] _U977_out; wire [15:0] _U978_out; wire [15:0] _U979_out; wire [15:0] _U980_out; -wire [15:0] _U982_out; +wire [15:0] _U981_out; wire [15:0] _U983_out; wire [15:0] _U984_out; wire [15:0] _U985_out; wire [15:0] _U986_out; wire [15:0] _U987_out; wire [15:0] _U988_out; -wire [15:0] _U989_out; -wire [15:0] _U991_out; +wire [15:0] _U990_out; wire [15:0] _U992_out; -wire [15:0] _U993_out; wire [15:0] _U994_out; wire [15:0] _U995_out; wire [15:0] _U996_out; @@ -25522,39 +25522,39 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1001_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U1002 ( - .in(_U1001_out), - .clk(clk), +_U1002_pt__U1003 _U1002 ( + .in(_U1005_out), .out(_U1002_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1003 ( - .in(_U1002_out), +) _U1004 ( + .in(in2_hw_kernel_global_wrapper_stencil[6]), .clk(clk), - .out(_U1003_out) + .out(_U1004_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1004 ( - .in(_U1003_out), +) _U1005 ( + .in(_U1004_out), .clk(clk), - .out(_U1004_out) -); -_U1005_pt__U1006 _U1005 ( - .in(in1_hw_input_global_wrapper_stencil[5]), .out(_U1005_out) ); -_U1007_pt__U1008 _U1007 ( - .in(_U1010_out), - .out(_U1007_out) +_U1006_pt__U1007 _U1006 ( + .in(_U1018_out), + .out(_U1006_out) +); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1008 ( + .in(mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986_out), + .clk(clk), + .out(_U1008_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1009 ( - .in(in2_hw_kernel_global_wrapper_stencil[6]), + .in(_U1008_out), .clk(clk), .out(_U1009_out) ); @@ -25565,18 +25565,38 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1010_out) ); -_U1011_pt__U1012 _U1011 ( - .in(in2_hw_kernel_global_wrapper_stencil[5]), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1011 ( + .in(_U1010_out), + .clk(clk), .out(_U1011_out) ); -_U1013_pt__U1014 _U1013 ( - .in(_U1016_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1012 ( + .in(_U1011_out), + .clk(clk), + .out(_U1012_out) +); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1013 ( + .in(_U1012_out), + .clk(clk), .out(_U1013_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1014 ( + .in(_U1013_out), + .clk(clk), + .out(_U1014_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1015 ( - .in(in1_hw_input_global_wrapper_stencil[6]), + .in(_U1014_out), .clk(clk), .out(_U1015_out) ); @@ -25587,28 +25607,28 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1016_out) ); -_U1017_pt__U1018 _U1017 ( - .in(_U1025_out), - .out(_U1017_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1019 ( - .in(in2_hw_kernel_global_wrapper_stencil[3]), +) _U1017 ( + .in(_U1016_out), .clk(clk), - .out(_U1019_out) + .out(_U1017_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1020 ( - .in(_U1019_out), +) _U1018 ( + .in(_U1017_out), .clk(clk), - .out(_U1020_out) + .out(_U1018_out) +); +_U1019_pt__U1020 _U1019 ( + .in(_U1026_out), + .out(_U1019_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1021 ( - .in(_U1020_out), + .in(in2_hw_kernel_global_wrapper_stencil[7]), .clk(clk), .out(_U1021_out) ); @@ -25640,25 +25660,35 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1025_out) ); -_U1026_pt__U1027 _U1026 ( - .in(_U1028_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1026 ( + .in(_U1025_out), + .clk(clk), .out(_U1026_out) ); +_U1027_pt__U1028 _U1027 ( + .in(_U1034_out), + .out(_U1027_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1028 ( - .in(in1_hw_input_global_wrapper_stencil[2]), +) _U1029 ( + .in(in1_hw_input_global_wrapper_stencil[7]), .clk(clk), - .out(_U1028_out) -); -_U1029_pt__U1030 _U1029 ( - .in(_U1033_out), .out(_U1029_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U1030 ( + .in(_U1029_out), + .clk(clk), + .out(_U1030_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1031 ( - .in(in1_hw_input_global_wrapper_stencil[7]), + .in(_U1030_out), .clk(clk), .out(_U1031_out) ); @@ -25676,21 +25706,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U1033_out) ); -_U1034_pt__U1035 _U1034 ( - .in(_U1038_out), - .out(_U1034_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U1036 ( - .in(in2_hw_kernel_global_wrapper_stencil[7]), +) _U1034 ( + .in(_U1033_out), .clk(clk), - .out(_U1036_out) + .out(_U1034_out) +); +_U1035_pt__U1036 _U1035 ( + .in(_U1038_out), + .out(_U1035_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U1037 ( - .in(_U1036_out), + .in(in1_hw_input_global_wrapper_stencil[6]), .clk(clk), .out(_U1037_out) ); @@ -25719,7 +25749,7 @@ _U841_pt__U842 _U841 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U843 ( - .in(in1_hw_input_global_wrapper_stencil[1]), + .in(in2_hw_kernel_global_wrapper_stencil[3]), .clk(clk), .out(_U843_out) ); @@ -25758,7 +25788,7 @@ _U848_pt__U849 _U848 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U850 ( - .in(add_988_997_998_out), + .in(add_989_996_997_out), .clk(clk), .out(_U850_out) ); @@ -25769,18 +25799,18 @@ _U851_pt__U852 _U851 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U853 ( - .in(add_992_993_994_out), + .in(in2_hw_kernel_global_wrapper_stencil[1]), .clk(clk), .out(_U853_out) ); _U854_pt__U855 _U854 ( - .in(_U869_out), + .in(_U867_out), .out(_U854_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U856 ( - .in(in0_conv_stencil[0]), + .in(mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987_out), .clk(clk), .out(_U856_out) ); @@ -25861,19 +25891,9 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U867_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U868 ( - .in(_U867_out), - .clk(clk), - .out(_U868_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U869 ( - .in(_U868_out), - .clk(clk), - .out(_U869_out) +_U868_pt__U869 _U868 ( + .in(add_986_1000_1001_out), + .out(out_conv_stencil) ); _U870_pt__U871 _U870 ( .in(_U872_out), @@ -25882,50 +25902,50 @@ _U870_pt__U871 _U870 ( mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U872 ( - .in(in2_hw_kernel_global_wrapper_stencil[2]), + .in(add_conv_stencil_5_999_1000_out), .clk(clk), .out(_U872_out) ); _U873_pt__U874 _U873 ( - .in(_U878_out), + .in(_U875_out), .out(_U873_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U875 ( - .in(in1_hw_input_global_wrapper_stencil[0]), + .in(add_987_998_999_out), .clk(clk), .out(_U875_out) ); +_U876_pt__U877 _U876 ( + .in(_U884_out), + .out(_U876_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U876 ( - .in(_U875_out), +) _U878 ( + .in(in2_hw_kernel_global_wrapper_stencil[2]), .clk(clk), - .out(_U876_out) + .out(_U878_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U877 ( - .in(_U876_out), +) _U879 ( + .in(_U878_out), .clk(clk), - .out(_U877_out) + .out(_U879_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U878 ( - .in(_U877_out), +) _U880 ( + .in(_U879_out), .clk(clk), - .out(_U878_out) -); -_U879_pt__U880 _U879 ( - .in(_U889_out), - .out(_U879_out) + .out(_U880_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U881 ( - .in(mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991_out), + .in(_U880_out), .clk(clk), .out(_U881_out) ); @@ -25950,24 +25970,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U884_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U885 ( - .in(_U884_out), - .clk(clk), +_U885_pt__U886 _U885 ( + .in(_U888_out), .out(_U885_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U886 ( - .in(_U885_out), - .clk(clk), - .out(_U886_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U887 ( - .in(_U886_out), + .in(mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993_out), .clk(clk), .out(_U887_out) ); @@ -25978,32 +25988,42 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U888_out) ); +_U889_pt__U890 _U889 ( + .in(_U900_out), + .out(_U889_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U889 ( - .in(_U888_out), +) _U891 ( + .in(mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990_out), .clk(clk), - .out(_U889_out) -); -_U890_pt__U891 _U890 ( - .in(_U892_out), - .out(_U890_out) + .out(_U891_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U892 ( - .in(add_989_996_997_out), + .in(_U891_out), .clk(clk), .out(_U892_out) ); -_U893_pt__U894 _U893 ( - .in(_U898_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U893 ( + .in(_U892_out), + .clk(clk), .out(_U893_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U894 ( + .in(_U893_out), + .clk(clk), + .out(_U894_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U895 ( - .in(mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989_out), + .in(_U894_out), .clk(clk), .out(_U895_out) ); @@ -26028,28 +26048,28 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U898_out) ); -_U899_pt__U900 _U899 ( - .in(_U906_out), - .out(_U899_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U901 ( - .in(mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992_out), +) _U899 ( + .in(_U898_out), .clk(clk), - .out(_U901_out) + .out(_U899_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U902 ( - .in(_U901_out), +) _U900 ( + .in(_U899_out), .clk(clk), - .out(_U902_out) + .out(_U900_out) +); +_U901_pt__U902 _U901 ( + .in(_U906_out), + .out(_U901_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U903 ( - .in(_U902_out), + .in(in1_hw_input_global_wrapper_stencil[0]), .clk(clk), .out(_U903_out) ); @@ -26075,24 +26095,34 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U906_out) ); _U907_pt__U908 _U907 ( - .in(_U909_out), + .in(_U922_out), .out(_U907_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U909 ( - .in(add_990_995_996_out), + .in(in0_conv_stencil[0]), .clk(clk), .out(_U909_out) ); -_U910_pt__U911 _U910 ( - .in(_U915_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U910 ( + .in(_U909_out), + .clk(clk), .out(_U910_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U911 ( + .in(_U910_out), + .clk(clk), + .out(_U911_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U912 ( - .in(mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990_out), + .in(_U911_out), .clk(clk), .out(_U912_out) ); @@ -26117,14 +26147,24 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U915_out) ); -_U916_pt__U917 _U916 ( - .in(_U922_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U916 ( + .in(_U915_out), + .clk(clk), .out(_U916_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U917 ( + .in(_U916_out), + .clk(clk), + .out(_U917_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U918 ( - .in(mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993_out), + .in(_U917_out), .clk(clk), .out(_U918_out) ); @@ -26157,13 +26197,13 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U922_out) ); _U923_pt__U924 _U923 ( - .in(_U935_out), + .in(_U930_out), .out(_U923_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U925 ( - .in(mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986_out), + .in(mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991_out), .clk(clk), .out(_U925_out) ); @@ -26202,24 +26242,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U930_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U931 ( - .in(_U930_out), - .clk(clk), +_U931_pt__U932 _U931 ( + .in(_U938_out), .out(_U931_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U932 ( - .in(_U931_out), - .clk(clk), - .out(_U932_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U933 ( - .in(_U932_out), + .in(mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992_out), .clk(clk), .out(_U933_out) ); @@ -26237,36 +26267,46 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U935_out) ); -_U936_pt__U937 _U936 ( - .in(_U938_out), +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U936 ( + .in(_U935_out), + .clk(clk), .out(_U936_out) ); +mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( + .init(16'h0000) +) _U937 ( + .in(_U936_out), + .clk(clk), + .out(_U937_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U938 ( - .in(add_987_998_999_out), + .in(_U937_out), .clk(clk), .out(_U938_out) ); _U939_pt__U940 _U939 ( - .in(add_986_1000_1001_out), - .out(out_conv_stencil) -); -_U941_pt__U942 _U941 ( - .in(_U953_out), - .out(_U941_out) + .in(_U941_out), + .out(_U939_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U943 ( - .in(mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988_out), +) _U941 ( + .in(add_992_993_994_out), .clk(clk), - .out(_U943_out) + .out(_U941_out) +); +_U942_pt__U943 _U942 ( + .in(_U947_out), + .out(_U942_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U944 ( - .in(_U943_out), + .in(in2_hw_kernel_global_wrapper_stencil[0]), .clk(clk), .out(_U944_out) ); @@ -26291,24 +26331,14 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U947_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U948 ( - .in(_U947_out), - .clk(clk), +_U948_pt__U949 _U948 ( + .in(_U955_out), .out(_U948_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U949 ( - .in(_U948_out), - .clk(clk), - .out(_U949_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U950 ( - .in(_U949_out), + .in(mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989_out), .clk(clk), .out(_U950_out) ); @@ -26333,53 +26363,53 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U953_out) ); -_U954_pt__U955 _U954 ( - .in(_U960_out), - .out(_U954_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U956 ( - .in(in2_hw_kernel_global_wrapper_stencil[1]), +) _U954 ( + .in(_U953_out), .clk(clk), - .out(_U956_out) + .out(_U954_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U957 ( - .in(_U956_out), +) _U955 ( + .in(_U954_out), .clk(clk), - .out(_U957_out) + .out(_U955_out) +); +_U956_pt__U957 _U956 ( + .in(_U958_out), + .out(_U956_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U958 ( - .in(_U957_out), + .in(add_990_995_996_out), .clk(clk), .out(_U958_out) ); +_U959_pt__U960 _U959 ( + .in(_U967_out), + .out(_U959_out) +); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U959 ( - .in(_U958_out), +) _U961 ( + .in(in1_hw_input_global_wrapper_stencil[2]), .clk(clk), - .out(_U959_out) + .out(_U961_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U960 ( - .in(_U959_out), +) _U962 ( + .in(_U961_out), .clk(clk), - .out(_U960_out) -); -_U961_pt__U962 _U961 ( - .in(_U966_out), - .out(_U961_out) + .out(_U962_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U963 ( - .in(in2_hw_kernel_global_wrapper_stencil[0]), + .in(_U962_out), .clk(clk), .out(_U963_out) ); @@ -26404,53 +26434,43 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U966_out) ); -_U967_pt__U968 _U967 ( - .in(_U969_out), - .out(_U967_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U969 ( - .in(add_conv_stencil_5_999_1000_out), +) _U967 ( + .in(_U966_out), .clk(clk), - .out(_U969_out) + .out(_U967_out) ); -_U970_pt__U971 _U970 ( - .in(_U979_out), - .out(_U970_out) +_U968_pt__U969 _U968 ( + .in(_U970_out), + .out(_U968_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U972 ( - .in(mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987_out), +) _U970 ( + .in(in1_hw_input_global_wrapper_stencil[1]), .clk(clk), - .out(_U972_out) + .out(_U970_out) +); +_U971_pt__U972 _U971 ( + .in(_U973_out), + .out(_U971_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U973 ( - .in(_U972_out), + .in(add_988_997_998_out), .clk(clk), .out(_U973_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U974 ( - .in(_U973_out), - .clk(clk), +_U974_pt__U975 _U974 ( + .in(_U980_out), .out(_U974_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U975 ( - .in(_U974_out), - .clk(clk), - .out(_U975_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U976 ( - .in(_U975_out), + .in(mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988_out), .clk(clk), .out(_U976_out) ); @@ -26475,21 +26495,21 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U979_out) ); -_U980_pt__U981 _U980 ( - .in(_U988_out), - .out(_U980_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) -) _U982 ( - .in(in1_hw_input_global_wrapper_stencil[3]), +) _U980 ( + .in(_U979_out), .clk(clk), - .out(_U982_out) + .out(_U980_out) +); +_U981_pt__U982 _U981 ( + .in(_U987_out), + .out(_U981_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U983 ( - .in(_U982_out), + .in(in1_hw_input_global_wrapper_stencil[3]), .clk(clk), .out(_U983_out) ); @@ -26521,42 +26541,22 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .clk(clk), .out(_U987_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U988 ( - .in(_U987_out), - .clk(clk), +_U988_pt__U989 _U988 ( + .in(in2_hw_kernel_global_wrapper_stencil[4]), .out(_U988_out) ); -_U989_pt__U990 _U989 ( - .in(_U996_out), - .out(_U989_out) -); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U991 ( +_U990_pt__U991 _U990 ( .in(in1_hw_input_global_wrapper_stencil[4]), - .clk(clk), - .out(_U991_out) + .out(_U990_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U992 ( - .in(_U991_out), - .clk(clk), +_U992_pt__U993 _U992 ( + .in(_U996_out), .out(_U992_out) ); -mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( - .init(16'h0000) -) _U993 ( - .in(_U992_out), - .clk(clk), - .out(_U993_out) -); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U994 ( - .in(_U993_out), + .in(in2_hw_kernel_global_wrapper_stencil[5]), .clk(clk), .out(_U994_out) ); @@ -26575,32 +26575,32 @@ mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .out(_U996_out) ); _U997_pt__U998 _U997 ( - .in(_U1004_out), + .in(_U1001_out), .out(_U997_out) ); mantle_reg__has_clrFalse__has_enFalse__has_rstFalse__width16 #( .init(16'h0000) ) _U999 ( - .in(in2_hw_kernel_global_wrapper_stencil[4]), + .in(in1_hw_input_global_wrapper_stencil[5]), .clk(clk), .out(_U999_out) ); -assign add_986_1000_1001_out = 16'(_U923_out + _U967_out); -assign add_987_998_999_out = 16'(_U970_out + _U848_out); -assign add_988_997_998_out = 16'(_U941_out + _U890_out); -assign add_989_996_997_out = 16'(_U893_out + _U907_out); -assign add_990_995_996_out = 16'(_U910_out + _U838_out); -assign add_991_994_995_out = 16'(_U879_out + _U851_out); -assign add_992_993_994_out = 16'(_U899_out + _U916_out); -assign add_conv_stencil_5_999_1000_out = 16'(_U854_out + _U936_out); -assign mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986_out = 16'(_U961_out * _U873_out); -assign mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987_out = 16'(_U954_out * _U841_out); -assign mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988_out = 16'(_U870_out * _U1026_out); -assign mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989_out = 16'(_U1017_out * _U980_out); -assign mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990_out = 16'(_U997_out * _U989_out); -assign mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991_out = 16'(_U1011_out * _U1005_out); -assign mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992_out = 16'(_U1007_out * _U1013_out); -assign mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993_out = 16'(_U1034_out * _U1029_out); +assign add_986_1000_1001_out = 16'(_U1006_out + _U870_out); +assign add_987_998_999_out = 16'(_U854_out + _U971_out); +assign add_988_997_998_out = 16'(_U974_out + _U848_out); +assign add_989_996_997_out = 16'(_U948_out + _U956_out); +assign add_990_995_996_out = 16'(_U889_out + _U838_out); +assign add_991_994_995_out = 16'(_U923_out + _U939_out); +assign add_992_993_994_out = 16'(_U931_out + _U885_out); +assign add_conv_stencil_5_999_1000_out = 16'(_U907_out + _U873_out); +assign mul_hw_kernel_global_wrapper_stencil_33_hw_input_global_wrapper_stencil_33_986_out = 16'(_U942_out * _U901_out); +assign mul_hw_kernel_global_wrapper_stencil_34_hw_input_global_wrapper_stencil_34_987_out = 16'(_U851_out * _U968_out); +assign mul_hw_kernel_global_wrapper_stencil_35_hw_input_global_wrapper_stencil_35_988_out = 16'(_U876_out * _U959_out); +assign mul_hw_kernel_global_wrapper_stencil_36_hw_input_global_wrapper_stencil_36_989_out = 16'(_U841_out * _U981_out); +assign mul_hw_kernel_global_wrapper_stencil_37_hw_input_global_wrapper_stencil_37_990_out = 16'(_U988_out * _U990_out); +assign mul_hw_kernel_global_wrapper_stencil_38_hw_input_global_wrapper_stencil_38_991_out = 16'(_U992_out * _U997_out); +assign mul_hw_kernel_global_wrapper_stencil_39_hw_input_global_wrapper_stencil_39_992_out = 16'(_U1002_out * _U1035_out); +assign mul_hw_kernel_global_wrapper_stencil_40_hw_input_global_wrapper_stencil_40_993_out = 16'(_U1019_out * _U1027_out); endmodule module cu_op_hcompute_conv_stencil_12 ( @@ -26648,7 +26648,7 @@ module _U0_pt__U1 ( assign out = in; endmodule -module hcompute_hw_input_global_wrapper_stencil_pipelined ( +module hcompute_hw_input_global_wrapper_stencil_4_pipelined ( output [15:0] out_hw_input_global_wrapper_stencil, input [15:0] in0_hw_input_stencil [0:0] ); @@ -26658,39 +26658,39 @@ _U0_pt__U1 _U0 ( ); endmodule -module cu_op_hcompute_hw_input_global_wrapper_stencil ( +module cu_op_hcompute_hw_input_global_wrapper_stencil_4 ( input clk, - input [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read [0:0], - output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write [0:0] + input [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read [0:0], + output [15:0] hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write [0:0] ); wire [15:0] inner_compute_out_hw_input_global_wrapper_stencil; wire [15:0] inner_compute_in0_hw_input_stencil [0:0]; -assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read[0]; -hcompute_hw_input_global_wrapper_stencil_pipelined inner_compute ( +assign inner_compute_in0_hw_input_stencil[0] = hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read[0]; +hcompute_hw_input_global_wrapper_stencil_4_pipelined inner_compute ( .out_hw_input_global_wrapper_stencil(inner_compute_out_hw_input_global_wrapper_stencil), .in0_hw_input_stencil(inner_compute_in0_hw_input_stencil) ); -assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; +assign hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write[0] = inner_compute_out_hw_input_global_wrapper_stencil; endmodule module resnet88 ( input clk, input rst_n, input flush, - output hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en, - input [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read [0:0], - output hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en, - input [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read [0:0], - output hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en, - input [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read [0:0], - output hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en, - input [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read [0:0], - output hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en, - input [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read [0:0], - output hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en, - input [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read [0:0], - output hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en, - input [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read [0:0], + output hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en, + input [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read [0:0], + output hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en, + input [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read [0:0], + output hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en, + input [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read [0:0], + output hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en, + input [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read [0:0], + output hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en, + input [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read [0:0], + output hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en, + input [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read [0:0], + output hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en, + input [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read [0:0], output hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en, input [15:0] hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read [0:0], output hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en, @@ -26839,25 +26839,25 @@ wire [15:0] arr__U2260_out [2:0]; wire [15:0] arr__U2265_out [2:0]; wire [15:0] arr__U2274_out [2:0]; wire [15:0] arr__U2279_out [2:0]; -wire [15:0] arr__U440_out [4:0]; -wire [15:0] arr__U447_out [4:0]; -wire [15:0] arr__U473_out [4:0]; -wire [15:0] arr__U480_out [4:0]; -wire [15:0] arr__U487_out [4:0]; -wire [15:0] arr__U494_out [4:0]; -wire [15:0] arr__U501_out [4:0]; -wire [15:0] arr__U508_out [4:0]; -wire [15:0] arr__U515_out [4:0]; -wire [15:0] arr__U522_out [4:0]; -wire [15:0] arr__U529_out [4:0]; -wire [15:0] arr__U536_out [4:0]; -wire [15:0] arr__U543_out [4:0]; -wire [15:0] arr__U550_out [4:0]; -wire [15:0] arr__U557_out [4:0]; -wire [15:0] arr__U564_out [4:0]; -wire [15:0] arr__U571_out [4:0]; -wire [15:0] arr__U578_out [4:0]; -wire [15:0] arr__U585_out [4:0]; +wire [15:0] arr__U417_out [4:0]; +wire [15:0] arr__U424_out [4:0]; +wire [15:0] arr__U450_out [4:0]; +wire [15:0] arr__U457_out [4:0]; +wire [15:0] arr__U464_out [4:0]; +wire [15:0] arr__U471_out [4:0]; +wire [15:0] arr__U478_out [4:0]; +wire [15:0] arr__U485_out [4:0]; +wire [15:0] arr__U492_out [4:0]; +wire [15:0] arr__U499_out [4:0]; +wire [15:0] arr__U506_out [4:0]; +wire [15:0] arr__U513_out [4:0]; +wire [15:0] arr__U520_out [4:0]; +wire [15:0] arr__U527_out [4:0]; +wire [15:0] arr__U534_out [4:0]; +wire [15:0] arr__U541_out [4:0]; +wire [15:0] arr__U548_out [4:0]; +wire [15:0] arr__U555_out [4:0]; +wire [15:0] arr__U562_out [4:0]; wire [15:0] arr__U628_out [4:0]; wire [15:0] arr__U635_out [4:0]; wire [15:0] arr__U661_out [4:0]; @@ -27039,25 +27039,25 @@ wire delay_reg__U2257_out; wire delay_reg__U2258_out; wire delay_reg__U2271_out; wire delay_reg__U2272_out; +wire delay_reg__U414_out; +wire delay_reg__U415_out; +wire delay_reg__U432_out; +wire delay_reg__U433_out; +wire delay_reg__U434_out; +wire delay_reg__U435_out; +wire delay_reg__U436_out; wire delay_reg__U437_out; wire delay_reg__U438_out; -wire delay_reg__U455_out; -wire delay_reg__U456_out; -wire delay_reg__U457_out; -wire delay_reg__U458_out; -wire delay_reg__U459_out; -wire delay_reg__U460_out; -wire delay_reg__U461_out; -wire delay_reg__U462_out; -wire delay_reg__U463_out; -wire delay_reg__U464_out; -wire delay_reg__U465_out; -wire delay_reg__U466_out; -wire delay_reg__U467_out; -wire delay_reg__U468_out; -wire delay_reg__U469_out; -wire delay_reg__U470_out; -wire delay_reg__U471_out; +wire delay_reg__U439_out; +wire delay_reg__U440_out; +wire delay_reg__U441_out; +wire delay_reg__U442_out; +wire delay_reg__U443_out; +wire delay_reg__U444_out; +wire delay_reg__U445_out; +wire delay_reg__U446_out; +wire delay_reg__U447_out; +wire delay_reg__U448_out; wire delay_reg__U625_out; wire delay_reg__U626_out; wire delay_reg__U643_out; @@ -28725,214 +28725,214 @@ array_delay_U2280 arr__U2279 ( .in(arr__U2279_in), .out(arr__U2279_out) ); -wire [15:0] arr__U440_in [4:0]; -assign arr__U440_in[4] = op_hcompute_conv_stencil_8_port_controller_d[4]; -assign arr__U440_in[3] = op_hcompute_conv_stencil_8_port_controller_d[3]; -assign arr__U440_in[2] = op_hcompute_conv_stencil_8_port_controller_d[2]; -assign arr__U440_in[1] = op_hcompute_conv_stencil_8_port_controller_d[1]; -assign arr__U440_in[0] = op_hcompute_conv_stencil_8_port_controller_d[0]; -array_delay_U441 arr__U440 ( - .clk(clk), - .in(arr__U440_in), - .out(arr__U440_out) -); -wire [15:0] arr__U447_in [4:0]; -assign arr__U447_in[4] = arr__U440_out[4]; -assign arr__U447_in[3] = arr__U440_out[3]; -assign arr__U447_in[2] = arr__U440_out[2]; -assign arr__U447_in[1] = arr__U440_out[1]; -assign arr__U447_in[0] = arr__U440_out[0]; -array_delay_U448 arr__U447 ( - .clk(clk), - .in(arr__U447_in), - .out(arr__U447_out) -); -wire [15:0] arr__U473_in [4:0]; -assign arr__U473_in[4] = op_hcompute_conv_stencil_8_port_controller_d[4]; -assign arr__U473_in[3] = op_hcompute_conv_stencil_8_port_controller_d[3]; -assign arr__U473_in[2] = op_hcompute_conv_stencil_8_port_controller_d[2]; -assign arr__U473_in[1] = op_hcompute_conv_stencil_8_port_controller_d[1]; -assign arr__U473_in[0] = op_hcompute_conv_stencil_8_port_controller_d[0]; -array_delay_U474 arr__U473 ( - .clk(clk), - .in(arr__U473_in), - .out(arr__U473_out) -); -wire [15:0] arr__U480_in [4:0]; -assign arr__U480_in[4] = arr__U473_out[4]; -assign arr__U480_in[3] = arr__U473_out[3]; -assign arr__U480_in[2] = arr__U473_out[2]; -assign arr__U480_in[1] = arr__U473_out[1]; -assign arr__U480_in[0] = arr__U473_out[0]; -array_delay_U481 arr__U480 ( - .clk(clk), - .in(arr__U480_in), - .out(arr__U480_out) -); -wire [15:0] arr__U487_in [4:0]; -assign arr__U487_in[4] = arr__U480_out[4]; -assign arr__U487_in[3] = arr__U480_out[3]; -assign arr__U487_in[2] = arr__U480_out[2]; -assign arr__U487_in[1] = arr__U480_out[1]; -assign arr__U487_in[0] = arr__U480_out[0]; -array_delay_U488 arr__U487 ( - .clk(clk), - .in(arr__U487_in), - .out(arr__U487_out) -); -wire [15:0] arr__U494_in [4:0]; -assign arr__U494_in[4] = arr__U487_out[4]; -assign arr__U494_in[3] = arr__U487_out[3]; -assign arr__U494_in[2] = arr__U487_out[2]; -assign arr__U494_in[1] = arr__U487_out[1]; -assign arr__U494_in[0] = arr__U487_out[0]; -array_delay_U495 arr__U494 ( - .clk(clk), - .in(arr__U494_in), - .out(arr__U494_out) -); -wire [15:0] arr__U501_in [4:0]; -assign arr__U501_in[4] = arr__U494_out[4]; -assign arr__U501_in[3] = arr__U494_out[3]; -assign arr__U501_in[2] = arr__U494_out[2]; -assign arr__U501_in[1] = arr__U494_out[1]; -assign arr__U501_in[0] = arr__U494_out[0]; -array_delay_U502 arr__U501 ( - .clk(clk), - .in(arr__U501_in), - .out(arr__U501_out) -); -wire [15:0] arr__U508_in [4:0]; -assign arr__U508_in[4] = arr__U501_out[4]; -assign arr__U508_in[3] = arr__U501_out[3]; -assign arr__U508_in[2] = arr__U501_out[2]; -assign arr__U508_in[1] = arr__U501_out[1]; -assign arr__U508_in[0] = arr__U501_out[0]; -array_delay_U509 arr__U508 ( - .clk(clk), - .in(arr__U508_in), - .out(arr__U508_out) -); -wire [15:0] arr__U515_in [4:0]; -assign arr__U515_in[4] = arr__U508_out[4]; -assign arr__U515_in[3] = arr__U508_out[3]; -assign arr__U515_in[2] = arr__U508_out[2]; -assign arr__U515_in[1] = arr__U508_out[1]; -assign arr__U515_in[0] = arr__U508_out[0]; -array_delay_U516 arr__U515 ( - .clk(clk), - .in(arr__U515_in), - .out(arr__U515_out) -); -wire [15:0] arr__U522_in [4:0]; -assign arr__U522_in[4] = arr__U515_out[4]; -assign arr__U522_in[3] = arr__U515_out[3]; -assign arr__U522_in[2] = arr__U515_out[2]; -assign arr__U522_in[1] = arr__U515_out[1]; -assign arr__U522_in[0] = arr__U515_out[0]; -array_delay_U523 arr__U522 ( - .clk(clk), - .in(arr__U522_in), - .out(arr__U522_out) -); -wire [15:0] arr__U529_in [4:0]; -assign arr__U529_in[4] = arr__U522_out[4]; -assign arr__U529_in[3] = arr__U522_out[3]; -assign arr__U529_in[2] = arr__U522_out[2]; -assign arr__U529_in[1] = arr__U522_out[1]; -assign arr__U529_in[0] = arr__U522_out[0]; -array_delay_U530 arr__U529 ( - .clk(clk), - .in(arr__U529_in), - .out(arr__U529_out) -); -wire [15:0] arr__U536_in [4:0]; -assign arr__U536_in[4] = arr__U529_out[4]; -assign arr__U536_in[3] = arr__U529_out[3]; -assign arr__U536_in[2] = arr__U529_out[2]; -assign arr__U536_in[1] = arr__U529_out[1]; -assign arr__U536_in[0] = arr__U529_out[0]; -array_delay_U537 arr__U536 ( - .clk(clk), - .in(arr__U536_in), - .out(arr__U536_out) -); -wire [15:0] arr__U543_in [4:0]; -assign arr__U543_in[4] = arr__U536_out[4]; -assign arr__U543_in[3] = arr__U536_out[3]; -assign arr__U543_in[2] = arr__U536_out[2]; -assign arr__U543_in[1] = arr__U536_out[1]; -assign arr__U543_in[0] = arr__U536_out[0]; -array_delay_U544 arr__U543 ( - .clk(clk), - .in(arr__U543_in), - .out(arr__U543_out) -); -wire [15:0] arr__U550_in [4:0]; -assign arr__U550_in[4] = arr__U543_out[4]; -assign arr__U550_in[3] = arr__U543_out[3]; -assign arr__U550_in[2] = arr__U543_out[2]; -assign arr__U550_in[1] = arr__U543_out[1]; -assign arr__U550_in[0] = arr__U543_out[0]; -array_delay_U551 arr__U550 ( - .clk(clk), - .in(arr__U550_in), - .out(arr__U550_out) -); -wire [15:0] arr__U557_in [4:0]; -assign arr__U557_in[4] = arr__U550_out[4]; -assign arr__U557_in[3] = arr__U550_out[3]; -assign arr__U557_in[2] = arr__U550_out[2]; -assign arr__U557_in[1] = arr__U550_out[1]; -assign arr__U557_in[0] = arr__U550_out[0]; -array_delay_U558 arr__U557 ( - .clk(clk), - .in(arr__U557_in), - .out(arr__U557_out) -); -wire [15:0] arr__U564_in [4:0]; -assign arr__U564_in[4] = arr__U557_out[4]; -assign arr__U564_in[3] = arr__U557_out[3]; -assign arr__U564_in[2] = arr__U557_out[2]; -assign arr__U564_in[1] = arr__U557_out[1]; -assign arr__U564_in[0] = arr__U557_out[0]; -array_delay_U565 arr__U564 ( - .clk(clk), - .in(arr__U564_in), - .out(arr__U564_out) -); -wire [15:0] arr__U571_in [4:0]; -assign arr__U571_in[4] = arr__U564_out[4]; -assign arr__U571_in[3] = arr__U564_out[3]; -assign arr__U571_in[2] = arr__U564_out[2]; -assign arr__U571_in[1] = arr__U564_out[1]; -assign arr__U571_in[0] = arr__U564_out[0]; -array_delay_U572 arr__U571 ( - .clk(clk), - .in(arr__U571_in), - .out(arr__U571_out) -); -wire [15:0] arr__U578_in [4:0]; -assign arr__U578_in[4] = arr__U571_out[4]; -assign arr__U578_in[3] = arr__U571_out[3]; -assign arr__U578_in[2] = arr__U571_out[2]; -assign arr__U578_in[1] = arr__U571_out[1]; -assign arr__U578_in[0] = arr__U571_out[0]; -array_delay_U579 arr__U578 ( - .clk(clk), - .in(arr__U578_in), - .out(arr__U578_out) -); -wire [15:0] arr__U585_in [4:0]; -assign arr__U585_in[4] = arr__U578_out[4]; -assign arr__U585_in[3] = arr__U578_out[3]; -assign arr__U585_in[2] = arr__U578_out[2]; -assign arr__U585_in[1] = arr__U578_out[1]; -assign arr__U585_in[0] = arr__U578_out[0]; -array_delay_U586 arr__U585 ( - .clk(clk), - .in(arr__U585_in), - .out(arr__U585_out) +wire [15:0] arr__U417_in [4:0]; +assign arr__U417_in[4] = op_hcompute_conv_stencil_8_port_controller_d[4]; +assign arr__U417_in[3] = op_hcompute_conv_stencil_8_port_controller_d[3]; +assign arr__U417_in[2] = op_hcompute_conv_stencil_8_port_controller_d[2]; +assign arr__U417_in[1] = op_hcompute_conv_stencil_8_port_controller_d[1]; +assign arr__U417_in[0] = op_hcompute_conv_stencil_8_port_controller_d[0]; +array_delay_U418 arr__U417 ( + .clk(clk), + .in(arr__U417_in), + .out(arr__U417_out) +); +wire [15:0] arr__U424_in [4:0]; +assign arr__U424_in[4] = arr__U417_out[4]; +assign arr__U424_in[3] = arr__U417_out[3]; +assign arr__U424_in[2] = arr__U417_out[2]; +assign arr__U424_in[1] = arr__U417_out[1]; +assign arr__U424_in[0] = arr__U417_out[0]; +array_delay_U425 arr__U424 ( + .clk(clk), + .in(arr__U424_in), + .out(arr__U424_out) +); +wire [15:0] arr__U450_in [4:0]; +assign arr__U450_in[4] = op_hcompute_conv_stencil_8_port_controller_d[4]; +assign arr__U450_in[3] = op_hcompute_conv_stencil_8_port_controller_d[3]; +assign arr__U450_in[2] = op_hcompute_conv_stencil_8_port_controller_d[2]; +assign arr__U450_in[1] = op_hcompute_conv_stencil_8_port_controller_d[1]; +assign arr__U450_in[0] = op_hcompute_conv_stencil_8_port_controller_d[0]; +array_delay_U451 arr__U450 ( + .clk(clk), + .in(arr__U450_in), + .out(arr__U450_out) +); +wire [15:0] arr__U457_in [4:0]; +assign arr__U457_in[4] = arr__U450_out[4]; +assign arr__U457_in[3] = arr__U450_out[3]; +assign arr__U457_in[2] = arr__U450_out[2]; +assign arr__U457_in[1] = arr__U450_out[1]; +assign arr__U457_in[0] = arr__U450_out[0]; +array_delay_U458 arr__U457 ( + .clk(clk), + .in(arr__U457_in), + .out(arr__U457_out) +); +wire [15:0] arr__U464_in [4:0]; +assign arr__U464_in[4] = arr__U457_out[4]; +assign arr__U464_in[3] = arr__U457_out[3]; +assign arr__U464_in[2] = arr__U457_out[2]; +assign arr__U464_in[1] = arr__U457_out[1]; +assign arr__U464_in[0] = arr__U457_out[0]; +array_delay_U465 arr__U464 ( + .clk(clk), + .in(arr__U464_in), + .out(arr__U464_out) +); +wire [15:0] arr__U471_in [4:0]; +assign arr__U471_in[4] = arr__U464_out[4]; +assign arr__U471_in[3] = arr__U464_out[3]; +assign arr__U471_in[2] = arr__U464_out[2]; +assign arr__U471_in[1] = arr__U464_out[1]; +assign arr__U471_in[0] = arr__U464_out[0]; +array_delay_U472 arr__U471 ( + .clk(clk), + .in(arr__U471_in), + .out(arr__U471_out) +); +wire [15:0] arr__U478_in [4:0]; +assign arr__U478_in[4] = arr__U471_out[4]; +assign arr__U478_in[3] = arr__U471_out[3]; +assign arr__U478_in[2] = arr__U471_out[2]; +assign arr__U478_in[1] = arr__U471_out[1]; +assign arr__U478_in[0] = arr__U471_out[0]; +array_delay_U479 arr__U478 ( + .clk(clk), + .in(arr__U478_in), + .out(arr__U478_out) +); +wire [15:0] arr__U485_in [4:0]; +assign arr__U485_in[4] = arr__U478_out[4]; +assign arr__U485_in[3] = arr__U478_out[3]; +assign arr__U485_in[2] = arr__U478_out[2]; +assign arr__U485_in[1] = arr__U478_out[1]; +assign arr__U485_in[0] = arr__U478_out[0]; +array_delay_U486 arr__U485 ( + .clk(clk), + .in(arr__U485_in), + .out(arr__U485_out) +); +wire [15:0] arr__U492_in [4:0]; +assign arr__U492_in[4] = arr__U485_out[4]; +assign arr__U492_in[3] = arr__U485_out[3]; +assign arr__U492_in[2] = arr__U485_out[2]; +assign arr__U492_in[1] = arr__U485_out[1]; +assign arr__U492_in[0] = arr__U485_out[0]; +array_delay_U493 arr__U492 ( + .clk(clk), + .in(arr__U492_in), + .out(arr__U492_out) +); +wire [15:0] arr__U499_in [4:0]; +assign arr__U499_in[4] = arr__U492_out[4]; +assign arr__U499_in[3] = arr__U492_out[3]; +assign arr__U499_in[2] = arr__U492_out[2]; +assign arr__U499_in[1] = arr__U492_out[1]; +assign arr__U499_in[0] = arr__U492_out[0]; +array_delay_U500 arr__U499 ( + .clk(clk), + .in(arr__U499_in), + .out(arr__U499_out) +); +wire [15:0] arr__U506_in [4:0]; +assign arr__U506_in[4] = arr__U499_out[4]; +assign arr__U506_in[3] = arr__U499_out[3]; +assign arr__U506_in[2] = arr__U499_out[2]; +assign arr__U506_in[1] = arr__U499_out[1]; +assign arr__U506_in[0] = arr__U499_out[0]; +array_delay_U507 arr__U506 ( + .clk(clk), + .in(arr__U506_in), + .out(arr__U506_out) +); +wire [15:0] arr__U513_in [4:0]; +assign arr__U513_in[4] = arr__U506_out[4]; +assign arr__U513_in[3] = arr__U506_out[3]; +assign arr__U513_in[2] = arr__U506_out[2]; +assign arr__U513_in[1] = arr__U506_out[1]; +assign arr__U513_in[0] = arr__U506_out[0]; +array_delay_U514 arr__U513 ( + .clk(clk), + .in(arr__U513_in), + .out(arr__U513_out) +); +wire [15:0] arr__U520_in [4:0]; +assign arr__U520_in[4] = arr__U513_out[4]; +assign arr__U520_in[3] = arr__U513_out[3]; +assign arr__U520_in[2] = arr__U513_out[2]; +assign arr__U520_in[1] = arr__U513_out[1]; +assign arr__U520_in[0] = arr__U513_out[0]; +array_delay_U521 arr__U520 ( + .clk(clk), + .in(arr__U520_in), + .out(arr__U520_out) +); +wire [15:0] arr__U527_in [4:0]; +assign arr__U527_in[4] = arr__U520_out[4]; +assign arr__U527_in[3] = arr__U520_out[3]; +assign arr__U527_in[2] = arr__U520_out[2]; +assign arr__U527_in[1] = arr__U520_out[1]; +assign arr__U527_in[0] = arr__U520_out[0]; +array_delay_U528 arr__U527 ( + .clk(clk), + .in(arr__U527_in), + .out(arr__U527_out) +); +wire [15:0] arr__U534_in [4:0]; +assign arr__U534_in[4] = arr__U527_out[4]; +assign arr__U534_in[3] = arr__U527_out[3]; +assign arr__U534_in[2] = arr__U527_out[2]; +assign arr__U534_in[1] = arr__U527_out[1]; +assign arr__U534_in[0] = arr__U527_out[0]; +array_delay_U535 arr__U534 ( + .clk(clk), + .in(arr__U534_in), + .out(arr__U534_out) +); +wire [15:0] arr__U541_in [4:0]; +assign arr__U541_in[4] = arr__U534_out[4]; +assign arr__U541_in[3] = arr__U534_out[3]; +assign arr__U541_in[2] = arr__U534_out[2]; +assign arr__U541_in[1] = arr__U534_out[1]; +assign arr__U541_in[0] = arr__U534_out[0]; +array_delay_U542 arr__U541 ( + .clk(clk), + .in(arr__U541_in), + .out(arr__U541_out) +); +wire [15:0] arr__U548_in [4:0]; +assign arr__U548_in[4] = arr__U541_out[4]; +assign arr__U548_in[3] = arr__U541_out[3]; +assign arr__U548_in[2] = arr__U541_out[2]; +assign arr__U548_in[1] = arr__U541_out[1]; +assign arr__U548_in[0] = arr__U541_out[0]; +array_delay_U549 arr__U548 ( + .clk(clk), + .in(arr__U548_in), + .out(arr__U548_out) +); +wire [15:0] arr__U555_in [4:0]; +assign arr__U555_in[4] = arr__U548_out[4]; +assign arr__U555_in[3] = arr__U548_out[3]; +assign arr__U555_in[2] = arr__U548_out[2]; +assign arr__U555_in[1] = arr__U548_out[1]; +assign arr__U555_in[0] = arr__U548_out[0]; +array_delay_U556 arr__U555 ( + .clk(clk), + .in(arr__U555_in), + .out(arr__U555_out) +); +wire [15:0] arr__U562_in [4:0]; +assign arr__U562_in[4] = arr__U555_out[4]; +assign arr__U562_in[3] = arr__U555_out[3]; +assign arr__U562_in[2] = arr__U555_out[2]; +assign arr__U562_in[1] = arr__U555_out[1]; +assign arr__U562_in[0] = arr__U555_out[0]; +array_delay_U563 arr__U562 ( + .clk(clk), + .in(arr__U562_in), + .out(arr__U562_out) ); wire [15:0] arr__U628_in [4:0]; assign arr__U628_in[4] = op_hcompute_conv_stencil_9_port_controller_d[4]; @@ -30664,154 +30664,154 @@ corebit_reg #( corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U437 ( +) delay_reg__U414 ( .clk(clk), .in(op_hcompute_conv_stencil_8_port_controller_valid), - .out(delay_reg__U437_out) + .out(delay_reg__U414_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U438 ( +) delay_reg__U415 ( .clk(clk), - .in(delay_reg__U437_out), - .out(delay_reg__U438_out) + .in(delay_reg__U414_out), + .out(delay_reg__U415_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U455 ( +) delay_reg__U432 ( .clk(clk), .in(op_hcompute_conv_stencil_8_port_controller_valid), - .out(delay_reg__U455_out) + .out(delay_reg__U432_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U456 ( +) delay_reg__U433 ( .clk(clk), - .in(delay_reg__U455_out), - .out(delay_reg__U456_out) + .in(delay_reg__U432_out), + .out(delay_reg__U433_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U457 ( +) delay_reg__U434 ( .clk(clk), - .in(delay_reg__U456_out), - .out(delay_reg__U457_out) + .in(delay_reg__U433_out), + .out(delay_reg__U434_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U458 ( +) delay_reg__U435 ( .clk(clk), - .in(delay_reg__U457_out), - .out(delay_reg__U458_out) + .in(delay_reg__U434_out), + .out(delay_reg__U435_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U459 ( +) delay_reg__U436 ( .clk(clk), - .in(delay_reg__U458_out), - .out(delay_reg__U459_out) + .in(delay_reg__U435_out), + .out(delay_reg__U436_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U460 ( +) delay_reg__U437 ( .clk(clk), - .in(delay_reg__U459_out), - .out(delay_reg__U460_out) + .in(delay_reg__U436_out), + .out(delay_reg__U437_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U461 ( +) delay_reg__U438 ( .clk(clk), - .in(delay_reg__U460_out), - .out(delay_reg__U461_out) + .in(delay_reg__U437_out), + .out(delay_reg__U438_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U462 ( +) delay_reg__U439 ( .clk(clk), - .in(delay_reg__U461_out), - .out(delay_reg__U462_out) + .in(delay_reg__U438_out), + .out(delay_reg__U439_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U463 ( +) delay_reg__U440 ( .clk(clk), - .in(delay_reg__U462_out), - .out(delay_reg__U463_out) + .in(delay_reg__U439_out), + .out(delay_reg__U440_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U464 ( +) delay_reg__U441 ( .clk(clk), - .in(delay_reg__U463_out), - .out(delay_reg__U464_out) + .in(delay_reg__U440_out), + .out(delay_reg__U441_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U465 ( +) delay_reg__U442 ( .clk(clk), - .in(delay_reg__U464_out), - .out(delay_reg__U465_out) + .in(delay_reg__U441_out), + .out(delay_reg__U442_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U466 ( +) delay_reg__U443 ( .clk(clk), - .in(delay_reg__U465_out), - .out(delay_reg__U466_out) + .in(delay_reg__U442_out), + .out(delay_reg__U443_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U467 ( +) delay_reg__U444 ( .clk(clk), - .in(delay_reg__U466_out), - .out(delay_reg__U467_out) + .in(delay_reg__U443_out), + .out(delay_reg__U444_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U468 ( +) delay_reg__U445 ( .clk(clk), - .in(delay_reg__U467_out), - .out(delay_reg__U468_out) + .in(delay_reg__U444_out), + .out(delay_reg__U445_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U469 ( +) delay_reg__U446 ( .clk(clk), - .in(delay_reg__U468_out), - .out(delay_reg__U469_out) + .in(delay_reg__U445_out), + .out(delay_reg__U446_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U470 ( +) delay_reg__U447 ( .clk(clk), - .in(delay_reg__U469_out), - .out(delay_reg__U470_out) + .in(delay_reg__U446_out), + .out(delay_reg__U447_out) ); corebit_reg #( .clk_posedge(1'b1), .init(1'b0) -) delay_reg__U471 ( +) delay_reg__U448 ( .clk(clk), - .in(delay_reg__U470_out), - .out(delay_reg__U471_out) + .in(delay_reg__U447_out), + .out(delay_reg__U448_out) ); corebit_reg #( .clk_posedge(1'b1), @@ -31806,7 +31806,7 @@ op_hcompute_conv_stencil_15_write_start_control_vars_pt__U1788 op_hcompute_conv_ .in(op_hcompute_conv_stencil_15_write_start_control_vars_in), .out(op_hcompute_conv_stencil_15_write_start_control_vars_out) ); -op_hcompute_conv_stencil_1_exe_start_pt__U262 op_hcompute_conv_stencil_1_exe_start ( +op_hcompute_conv_stencil_1_exe_start_pt__U239 op_hcompute_conv_stencil_1_exe_start ( .in(op_hcompute_conv_stencil_1_port_controller_valid), .out(op_hcompute_conv_stencil_1_exe_start_out) ); @@ -31814,16 +31814,16 @@ wire [15:0] op_hcompute_conv_stencil_1_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_1_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_1_port_controller_d[2]; assign op_hcompute_conv_stencil_1_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_1_port_controller_d[1]; assign op_hcompute_conv_stencil_1_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_1_port_controller_d[0]; -op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U263 op_hcompute_conv_stencil_1_exe_start_control_vars ( +op_hcompute_conv_stencil_1_exe_start_control_vars_pt__U240 op_hcompute_conv_stencil_1_exe_start_control_vars ( .in(op_hcompute_conv_stencil_1_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_1_exe_start_control_vars_out) ); -affine_controller__U243 op_hcompute_conv_stencil_1_port_controller ( +affine_controller__U220 op_hcompute_conv_stencil_1_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_1_port_controller_valid), .d(op_hcompute_conv_stencil_1_port_controller_d) ); -op_hcompute_conv_stencil_1_read_start_pt__U260 op_hcompute_conv_stencil_1_read_start ( +op_hcompute_conv_stencil_1_read_start_pt__U237 op_hcompute_conv_stencil_1_read_start ( .in(op_hcompute_conv_stencil_1_port_controller_valid), .out(op_hcompute_conv_stencil_1_read_start_out) ); @@ -31831,11 +31831,11 @@ wire [15:0] op_hcompute_conv_stencil_1_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_1_read_start_control_vars_in[2] = op_hcompute_conv_stencil_1_port_controller_d[2]; assign op_hcompute_conv_stencil_1_read_start_control_vars_in[1] = op_hcompute_conv_stencil_1_port_controller_d[1]; assign op_hcompute_conv_stencil_1_read_start_control_vars_in[0] = op_hcompute_conv_stencil_1_port_controller_d[0]; -op_hcompute_conv_stencil_1_read_start_control_vars_pt__U261 op_hcompute_conv_stencil_1_read_start_control_vars ( +op_hcompute_conv_stencil_1_read_start_control_vars_pt__U238 op_hcompute_conv_stencil_1_read_start_control_vars ( .in(op_hcompute_conv_stencil_1_read_start_control_vars_in), .out(op_hcompute_conv_stencil_1_read_start_control_vars_out) ); -op_hcompute_conv_stencil_1_write_start_pt__U264 op_hcompute_conv_stencil_1_write_start ( +op_hcompute_conv_stencil_1_write_start_pt__U241 op_hcompute_conv_stencil_1_write_start ( .in(op_hcompute_conv_stencil_1_port_controller_valid), .out(op_hcompute_conv_stencil_1_write_start_out) ); @@ -31843,7 +31843,7 @@ wire [15:0] op_hcompute_conv_stencil_1_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_1_write_start_control_vars_in[2] = op_hcompute_conv_stencil_1_port_controller_d[2]; assign op_hcompute_conv_stencil_1_write_start_control_vars_in[1] = op_hcompute_conv_stencil_1_port_controller_d[1]; assign op_hcompute_conv_stencil_1_write_start_control_vars_in[0] = op_hcompute_conv_stencil_1_port_controller_d[0]; -op_hcompute_conv_stencil_1_write_start_control_vars_pt__U265 op_hcompute_conv_stencil_1_write_start_control_vars ( +op_hcompute_conv_stencil_1_write_start_control_vars_pt__U242 op_hcompute_conv_stencil_1_write_start_control_vars ( .in(op_hcompute_conv_stencil_1_write_start_control_vars_in), .out(op_hcompute_conv_stencil_1_write_start_control_vars_out) ); @@ -31851,7 +31851,7 @@ cu_op_hcompute_conv_stencil_2 op_hcompute_conv_stencil_2 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_2_write(op_hcompute_conv_stencil_2_conv_stencil_op_hcompute_conv_stencil_2_write) ); -op_hcompute_conv_stencil_2_exe_start_pt__U285 op_hcompute_conv_stencil_2_exe_start ( +op_hcompute_conv_stencil_2_exe_start_pt__U262 op_hcompute_conv_stencil_2_exe_start ( .in(op_hcompute_conv_stencil_2_port_controller_valid), .out(op_hcompute_conv_stencil_2_exe_start_out) ); @@ -31859,16 +31859,16 @@ wire [15:0] op_hcompute_conv_stencil_2_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_2_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_2_port_controller_d[2]; assign op_hcompute_conv_stencil_2_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_2_port_controller_d[1]; assign op_hcompute_conv_stencil_2_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_2_port_controller_d[0]; -op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U286 op_hcompute_conv_stencil_2_exe_start_control_vars ( +op_hcompute_conv_stencil_2_exe_start_control_vars_pt__U263 op_hcompute_conv_stencil_2_exe_start_control_vars ( .in(op_hcompute_conv_stencil_2_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_2_exe_start_control_vars_out) ); -affine_controller__U266 op_hcompute_conv_stencil_2_port_controller ( +affine_controller__U243 op_hcompute_conv_stencil_2_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_2_port_controller_valid), .d(op_hcompute_conv_stencil_2_port_controller_d) ); -op_hcompute_conv_stencil_2_read_start_pt__U283 op_hcompute_conv_stencil_2_read_start ( +op_hcompute_conv_stencil_2_read_start_pt__U260 op_hcompute_conv_stencil_2_read_start ( .in(op_hcompute_conv_stencil_2_port_controller_valid), .out(op_hcompute_conv_stencil_2_read_start_out) ); @@ -31876,11 +31876,11 @@ wire [15:0] op_hcompute_conv_stencil_2_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_2_read_start_control_vars_in[2] = op_hcompute_conv_stencil_2_port_controller_d[2]; assign op_hcompute_conv_stencil_2_read_start_control_vars_in[1] = op_hcompute_conv_stencil_2_port_controller_d[1]; assign op_hcompute_conv_stencil_2_read_start_control_vars_in[0] = op_hcompute_conv_stencil_2_port_controller_d[0]; -op_hcompute_conv_stencil_2_read_start_control_vars_pt__U284 op_hcompute_conv_stencil_2_read_start_control_vars ( +op_hcompute_conv_stencil_2_read_start_control_vars_pt__U261 op_hcompute_conv_stencil_2_read_start_control_vars ( .in(op_hcompute_conv_stencil_2_read_start_control_vars_in), .out(op_hcompute_conv_stencil_2_read_start_control_vars_out) ); -op_hcompute_conv_stencil_2_write_start_pt__U287 op_hcompute_conv_stencil_2_write_start ( +op_hcompute_conv_stencil_2_write_start_pt__U264 op_hcompute_conv_stencil_2_write_start ( .in(op_hcompute_conv_stencil_2_port_controller_valid), .out(op_hcompute_conv_stencil_2_write_start_out) ); @@ -31888,7 +31888,7 @@ wire [15:0] op_hcompute_conv_stencil_2_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_2_write_start_control_vars_in[2] = op_hcompute_conv_stencil_2_port_controller_d[2]; assign op_hcompute_conv_stencil_2_write_start_control_vars_in[1] = op_hcompute_conv_stencil_2_port_controller_d[1]; assign op_hcompute_conv_stencil_2_write_start_control_vars_in[0] = op_hcompute_conv_stencil_2_port_controller_d[0]; -op_hcompute_conv_stencil_2_write_start_control_vars_pt__U288 op_hcompute_conv_stencil_2_write_start_control_vars ( +op_hcompute_conv_stencil_2_write_start_control_vars_pt__U265 op_hcompute_conv_stencil_2_write_start_control_vars ( .in(op_hcompute_conv_stencil_2_write_start_control_vars_in), .out(op_hcompute_conv_stencil_2_write_start_control_vars_out) ); @@ -31896,7 +31896,7 @@ cu_op_hcompute_conv_stencil_3 op_hcompute_conv_stencil_3 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_3_write(op_hcompute_conv_stencil_3_conv_stencil_op_hcompute_conv_stencil_3_write) ); -op_hcompute_conv_stencil_3_exe_start_pt__U308 op_hcompute_conv_stencil_3_exe_start ( +op_hcompute_conv_stencil_3_exe_start_pt__U285 op_hcompute_conv_stencil_3_exe_start ( .in(op_hcompute_conv_stencil_3_port_controller_valid), .out(op_hcompute_conv_stencil_3_exe_start_out) ); @@ -31904,16 +31904,16 @@ wire [15:0] op_hcompute_conv_stencil_3_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; assign op_hcompute_conv_stencil_3_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; -op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U309 op_hcompute_conv_stencil_3_exe_start_control_vars ( +op_hcompute_conv_stencil_3_exe_start_control_vars_pt__U286 op_hcompute_conv_stencil_3_exe_start_control_vars ( .in(op_hcompute_conv_stencil_3_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_3_exe_start_control_vars_out) ); -affine_controller__U289 op_hcompute_conv_stencil_3_port_controller ( +affine_controller__U266 op_hcompute_conv_stencil_3_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_3_port_controller_valid), .d(op_hcompute_conv_stencil_3_port_controller_d) ); -op_hcompute_conv_stencil_3_read_start_pt__U306 op_hcompute_conv_stencil_3_read_start ( +op_hcompute_conv_stencil_3_read_start_pt__U283 op_hcompute_conv_stencil_3_read_start ( .in(op_hcompute_conv_stencil_3_port_controller_valid), .out(op_hcompute_conv_stencil_3_read_start_out) ); @@ -31921,11 +31921,11 @@ wire [15:0] op_hcompute_conv_stencil_3_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_3_read_start_control_vars_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; assign op_hcompute_conv_stencil_3_read_start_control_vars_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; assign op_hcompute_conv_stencil_3_read_start_control_vars_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; -op_hcompute_conv_stencil_3_read_start_control_vars_pt__U307 op_hcompute_conv_stencil_3_read_start_control_vars ( +op_hcompute_conv_stencil_3_read_start_control_vars_pt__U284 op_hcompute_conv_stencil_3_read_start_control_vars ( .in(op_hcompute_conv_stencil_3_read_start_control_vars_in), .out(op_hcompute_conv_stencil_3_read_start_control_vars_out) ); -op_hcompute_conv_stencil_3_write_start_pt__U310 op_hcompute_conv_stencil_3_write_start ( +op_hcompute_conv_stencil_3_write_start_pt__U287 op_hcompute_conv_stencil_3_write_start ( .in(op_hcompute_conv_stencil_3_port_controller_valid), .out(op_hcompute_conv_stencil_3_write_start_out) ); @@ -31933,7 +31933,7 @@ wire [15:0] op_hcompute_conv_stencil_3_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_3_write_start_control_vars_in[2] = op_hcompute_conv_stencil_3_port_controller_d[2]; assign op_hcompute_conv_stencil_3_write_start_control_vars_in[1] = op_hcompute_conv_stencil_3_port_controller_d[1]; assign op_hcompute_conv_stencil_3_write_start_control_vars_in[0] = op_hcompute_conv_stencil_3_port_controller_d[0]; -op_hcompute_conv_stencil_3_write_start_control_vars_pt__U311 op_hcompute_conv_stencil_3_write_start_control_vars ( +op_hcompute_conv_stencil_3_write_start_control_vars_pt__U288 op_hcompute_conv_stencil_3_write_start_control_vars ( .in(op_hcompute_conv_stencil_3_write_start_control_vars_in), .out(op_hcompute_conv_stencil_3_write_start_control_vars_out) ); @@ -31941,7 +31941,7 @@ cu_op_hcompute_conv_stencil_4 op_hcompute_conv_stencil_4 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_4_write(op_hcompute_conv_stencil_4_conv_stencil_op_hcompute_conv_stencil_4_write) ); -op_hcompute_conv_stencil_4_exe_start_pt__U331 op_hcompute_conv_stencil_4_exe_start ( +op_hcompute_conv_stencil_4_exe_start_pt__U308 op_hcompute_conv_stencil_4_exe_start ( .in(op_hcompute_conv_stencil_4_port_controller_valid), .out(op_hcompute_conv_stencil_4_exe_start_out) ); @@ -31949,16 +31949,16 @@ wire [15:0] op_hcompute_conv_stencil_4_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; assign op_hcompute_conv_stencil_4_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; -op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U332 op_hcompute_conv_stencil_4_exe_start_control_vars ( +op_hcompute_conv_stencil_4_exe_start_control_vars_pt__U309 op_hcompute_conv_stencil_4_exe_start_control_vars ( .in(op_hcompute_conv_stencil_4_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_4_exe_start_control_vars_out) ); -affine_controller__U312 op_hcompute_conv_stencil_4_port_controller ( +affine_controller__U289 op_hcompute_conv_stencil_4_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_4_port_controller_valid), .d(op_hcompute_conv_stencil_4_port_controller_d) ); -op_hcompute_conv_stencil_4_read_start_pt__U329 op_hcompute_conv_stencil_4_read_start ( +op_hcompute_conv_stencil_4_read_start_pt__U306 op_hcompute_conv_stencil_4_read_start ( .in(op_hcompute_conv_stencil_4_port_controller_valid), .out(op_hcompute_conv_stencil_4_read_start_out) ); @@ -31966,11 +31966,11 @@ wire [15:0] op_hcompute_conv_stencil_4_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_4_read_start_control_vars_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; assign op_hcompute_conv_stencil_4_read_start_control_vars_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; assign op_hcompute_conv_stencil_4_read_start_control_vars_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; -op_hcompute_conv_stencil_4_read_start_control_vars_pt__U330 op_hcompute_conv_stencil_4_read_start_control_vars ( +op_hcompute_conv_stencil_4_read_start_control_vars_pt__U307 op_hcompute_conv_stencil_4_read_start_control_vars ( .in(op_hcompute_conv_stencil_4_read_start_control_vars_in), .out(op_hcompute_conv_stencil_4_read_start_control_vars_out) ); -op_hcompute_conv_stencil_4_write_start_pt__U333 op_hcompute_conv_stencil_4_write_start ( +op_hcompute_conv_stencil_4_write_start_pt__U310 op_hcompute_conv_stencil_4_write_start ( .in(op_hcompute_conv_stencil_4_port_controller_valid), .out(op_hcompute_conv_stencil_4_write_start_out) ); @@ -31978,7 +31978,7 @@ wire [15:0] op_hcompute_conv_stencil_4_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_4_write_start_control_vars_in[2] = op_hcompute_conv_stencil_4_port_controller_d[2]; assign op_hcompute_conv_stencil_4_write_start_control_vars_in[1] = op_hcompute_conv_stencil_4_port_controller_d[1]; assign op_hcompute_conv_stencil_4_write_start_control_vars_in[0] = op_hcompute_conv_stencil_4_port_controller_d[0]; -op_hcompute_conv_stencil_4_write_start_control_vars_pt__U334 op_hcompute_conv_stencil_4_write_start_control_vars ( +op_hcompute_conv_stencil_4_write_start_control_vars_pt__U311 op_hcompute_conv_stencil_4_write_start_control_vars ( .in(op_hcompute_conv_stencil_4_write_start_control_vars_in), .out(op_hcompute_conv_stencil_4_write_start_control_vars_out) ); @@ -31986,7 +31986,7 @@ cu_op_hcompute_conv_stencil_5 op_hcompute_conv_stencil_5 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_5_write(op_hcompute_conv_stencil_5_conv_stencil_op_hcompute_conv_stencil_5_write) ); -op_hcompute_conv_stencil_5_exe_start_pt__U354 op_hcompute_conv_stencil_5_exe_start ( +op_hcompute_conv_stencil_5_exe_start_pt__U331 op_hcompute_conv_stencil_5_exe_start ( .in(op_hcompute_conv_stencil_5_port_controller_valid), .out(op_hcompute_conv_stencil_5_exe_start_out) ); @@ -31994,16 +31994,16 @@ wire [15:0] op_hcompute_conv_stencil_5_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; assign op_hcompute_conv_stencil_5_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; -op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U355 op_hcompute_conv_stencil_5_exe_start_control_vars ( +op_hcompute_conv_stencil_5_exe_start_control_vars_pt__U332 op_hcompute_conv_stencil_5_exe_start_control_vars ( .in(op_hcompute_conv_stencil_5_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_5_exe_start_control_vars_out) ); -affine_controller__U335 op_hcompute_conv_stencil_5_port_controller ( +affine_controller__U312 op_hcompute_conv_stencil_5_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_5_port_controller_valid), .d(op_hcompute_conv_stencil_5_port_controller_d) ); -op_hcompute_conv_stencil_5_read_start_pt__U352 op_hcompute_conv_stencil_5_read_start ( +op_hcompute_conv_stencil_5_read_start_pt__U329 op_hcompute_conv_stencil_5_read_start ( .in(op_hcompute_conv_stencil_5_port_controller_valid), .out(op_hcompute_conv_stencil_5_read_start_out) ); @@ -32011,11 +32011,11 @@ wire [15:0] op_hcompute_conv_stencil_5_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_5_read_start_control_vars_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; assign op_hcompute_conv_stencil_5_read_start_control_vars_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; assign op_hcompute_conv_stencil_5_read_start_control_vars_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; -op_hcompute_conv_stencil_5_read_start_control_vars_pt__U353 op_hcompute_conv_stencil_5_read_start_control_vars ( +op_hcompute_conv_stencil_5_read_start_control_vars_pt__U330 op_hcompute_conv_stencil_5_read_start_control_vars ( .in(op_hcompute_conv_stencil_5_read_start_control_vars_in), .out(op_hcompute_conv_stencil_5_read_start_control_vars_out) ); -op_hcompute_conv_stencil_5_write_start_pt__U356 op_hcompute_conv_stencil_5_write_start ( +op_hcompute_conv_stencil_5_write_start_pt__U333 op_hcompute_conv_stencil_5_write_start ( .in(op_hcompute_conv_stencil_5_port_controller_valid), .out(op_hcompute_conv_stencil_5_write_start_out) ); @@ -32023,7 +32023,7 @@ wire [15:0] op_hcompute_conv_stencil_5_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_5_write_start_control_vars_in[2] = op_hcompute_conv_stencil_5_port_controller_d[2]; assign op_hcompute_conv_stencil_5_write_start_control_vars_in[1] = op_hcompute_conv_stencil_5_port_controller_d[1]; assign op_hcompute_conv_stencil_5_write_start_control_vars_in[0] = op_hcompute_conv_stencil_5_port_controller_d[0]; -op_hcompute_conv_stencil_5_write_start_control_vars_pt__U357 op_hcompute_conv_stencil_5_write_start_control_vars ( +op_hcompute_conv_stencil_5_write_start_control_vars_pt__U334 op_hcompute_conv_stencil_5_write_start_control_vars ( .in(op_hcompute_conv_stencil_5_write_start_control_vars_in), .out(op_hcompute_conv_stencil_5_write_start_control_vars_out) ); @@ -32031,7 +32031,7 @@ cu_op_hcompute_conv_stencil_6 op_hcompute_conv_stencil_6 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_6_write(op_hcompute_conv_stencil_6_conv_stencil_op_hcompute_conv_stencil_6_write) ); -op_hcompute_conv_stencil_6_exe_start_pt__U377 op_hcompute_conv_stencil_6_exe_start ( +op_hcompute_conv_stencil_6_exe_start_pt__U354 op_hcompute_conv_stencil_6_exe_start ( .in(op_hcompute_conv_stencil_6_port_controller_valid), .out(op_hcompute_conv_stencil_6_exe_start_out) ); @@ -32039,16 +32039,16 @@ wire [15:0] op_hcompute_conv_stencil_6_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_6_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_6_port_controller_d[2]; assign op_hcompute_conv_stencil_6_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_6_port_controller_d[1]; assign op_hcompute_conv_stencil_6_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_6_port_controller_d[0]; -op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U378 op_hcompute_conv_stencil_6_exe_start_control_vars ( +op_hcompute_conv_stencil_6_exe_start_control_vars_pt__U355 op_hcompute_conv_stencil_6_exe_start_control_vars ( .in(op_hcompute_conv_stencil_6_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_6_exe_start_control_vars_out) ); -affine_controller__U358 op_hcompute_conv_stencil_6_port_controller ( +affine_controller__U335 op_hcompute_conv_stencil_6_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_6_port_controller_valid), .d(op_hcompute_conv_stencil_6_port_controller_d) ); -op_hcompute_conv_stencil_6_read_start_pt__U375 op_hcompute_conv_stencil_6_read_start ( +op_hcompute_conv_stencil_6_read_start_pt__U352 op_hcompute_conv_stencil_6_read_start ( .in(op_hcompute_conv_stencil_6_port_controller_valid), .out(op_hcompute_conv_stencil_6_read_start_out) ); @@ -32056,11 +32056,11 @@ wire [15:0] op_hcompute_conv_stencil_6_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_6_read_start_control_vars_in[2] = op_hcompute_conv_stencil_6_port_controller_d[2]; assign op_hcompute_conv_stencil_6_read_start_control_vars_in[1] = op_hcompute_conv_stencil_6_port_controller_d[1]; assign op_hcompute_conv_stencil_6_read_start_control_vars_in[0] = op_hcompute_conv_stencil_6_port_controller_d[0]; -op_hcompute_conv_stencil_6_read_start_control_vars_pt__U376 op_hcompute_conv_stencil_6_read_start_control_vars ( +op_hcompute_conv_stencil_6_read_start_control_vars_pt__U353 op_hcompute_conv_stencil_6_read_start_control_vars ( .in(op_hcompute_conv_stencil_6_read_start_control_vars_in), .out(op_hcompute_conv_stencil_6_read_start_control_vars_out) ); -op_hcompute_conv_stencil_6_write_start_pt__U379 op_hcompute_conv_stencil_6_write_start ( +op_hcompute_conv_stencil_6_write_start_pt__U356 op_hcompute_conv_stencil_6_write_start ( .in(op_hcompute_conv_stencil_6_port_controller_valid), .out(op_hcompute_conv_stencil_6_write_start_out) ); @@ -32068,7 +32068,7 @@ wire [15:0] op_hcompute_conv_stencil_6_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_6_write_start_control_vars_in[2] = op_hcompute_conv_stencil_6_port_controller_d[2]; assign op_hcompute_conv_stencil_6_write_start_control_vars_in[1] = op_hcompute_conv_stencil_6_port_controller_d[1]; assign op_hcompute_conv_stencil_6_write_start_control_vars_in[0] = op_hcompute_conv_stencil_6_port_controller_d[0]; -op_hcompute_conv_stencil_6_write_start_control_vars_pt__U380 op_hcompute_conv_stencil_6_write_start_control_vars ( +op_hcompute_conv_stencil_6_write_start_control_vars_pt__U357 op_hcompute_conv_stencil_6_write_start_control_vars ( .in(op_hcompute_conv_stencil_6_write_start_control_vars_in), .out(op_hcompute_conv_stencil_6_write_start_control_vars_out) ); @@ -32076,7 +32076,7 @@ cu_op_hcompute_conv_stencil_7 op_hcompute_conv_stencil_7 ( .clk(clk), .conv_stencil_op_hcompute_conv_stencil_7_write(op_hcompute_conv_stencil_7_conv_stencil_op_hcompute_conv_stencil_7_write) ); -op_hcompute_conv_stencil_7_exe_start_pt__U400 op_hcompute_conv_stencil_7_exe_start ( +op_hcompute_conv_stencil_7_exe_start_pt__U377 op_hcompute_conv_stencil_7_exe_start ( .in(op_hcompute_conv_stencil_7_port_controller_valid), .out(op_hcompute_conv_stencil_7_exe_start_out) ); @@ -32084,16 +32084,16 @@ wire [15:0] op_hcompute_conv_stencil_7_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_7_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_7_port_controller_d[2]; assign op_hcompute_conv_stencil_7_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_7_port_controller_d[1]; assign op_hcompute_conv_stencil_7_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_7_port_controller_d[0]; -op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U401 op_hcompute_conv_stencil_7_exe_start_control_vars ( +op_hcompute_conv_stencil_7_exe_start_control_vars_pt__U378 op_hcompute_conv_stencil_7_exe_start_control_vars ( .in(op_hcompute_conv_stencil_7_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_7_exe_start_control_vars_out) ); -affine_controller__U381 op_hcompute_conv_stencil_7_port_controller ( +affine_controller__U358 op_hcompute_conv_stencil_7_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_7_port_controller_valid), .d(op_hcompute_conv_stencil_7_port_controller_d) ); -op_hcompute_conv_stencil_7_read_start_pt__U398 op_hcompute_conv_stencil_7_read_start ( +op_hcompute_conv_stencil_7_read_start_pt__U375 op_hcompute_conv_stencil_7_read_start ( .in(op_hcompute_conv_stencil_7_port_controller_valid), .out(op_hcompute_conv_stencil_7_read_start_out) ); @@ -32101,11 +32101,11 @@ wire [15:0] op_hcompute_conv_stencil_7_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_7_read_start_control_vars_in[2] = op_hcompute_conv_stencil_7_port_controller_d[2]; assign op_hcompute_conv_stencil_7_read_start_control_vars_in[1] = op_hcompute_conv_stencil_7_port_controller_d[1]; assign op_hcompute_conv_stencil_7_read_start_control_vars_in[0] = op_hcompute_conv_stencil_7_port_controller_d[0]; -op_hcompute_conv_stencil_7_read_start_control_vars_pt__U399 op_hcompute_conv_stencil_7_read_start_control_vars ( +op_hcompute_conv_stencil_7_read_start_control_vars_pt__U376 op_hcompute_conv_stencil_7_read_start_control_vars ( .in(op_hcompute_conv_stencil_7_read_start_control_vars_in), .out(op_hcompute_conv_stencil_7_read_start_control_vars_out) ); -op_hcompute_conv_stencil_7_write_start_pt__U402 op_hcompute_conv_stencil_7_write_start ( +op_hcompute_conv_stencil_7_write_start_pt__U379 op_hcompute_conv_stencil_7_write_start ( .in(op_hcompute_conv_stencil_7_port_controller_valid), .out(op_hcompute_conv_stencil_7_write_start_out) ); @@ -32113,7 +32113,7 @@ wire [15:0] op_hcompute_conv_stencil_7_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_7_write_start_control_vars_in[2] = op_hcompute_conv_stencil_7_port_controller_d[2]; assign op_hcompute_conv_stencil_7_write_start_control_vars_in[1] = op_hcompute_conv_stencil_7_port_controller_d[1]; assign op_hcompute_conv_stencil_7_write_start_control_vars_in[0] = op_hcompute_conv_stencil_7_port_controller_d[0]; -op_hcompute_conv_stencil_7_write_start_control_vars_pt__U403 op_hcompute_conv_stencil_7_write_start_control_vars ( +op_hcompute_conv_stencil_7_write_start_control_vars_pt__U380 op_hcompute_conv_stencil_7_write_start_control_vars ( .in(op_hcompute_conv_stencil_7_write_start_control_vars_in), .out(op_hcompute_conv_stencil_7_write_start_control_vars_out) ); @@ -32144,26 +32144,26 @@ cu_op_hcompute_conv_stencil_8 op_hcompute_conv_stencil_8 ( .hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read(op_hcompute_conv_stencil_8_hw_kernel_global_wrapper_stencil_op_hcompute_conv_stencil_8_read), .conv_stencil_op_hcompute_conv_stencil_8_write(op_hcompute_conv_stencil_8_conv_stencil_op_hcompute_conv_stencil_8_write) ); -op_hcompute_conv_stencil_8_exe_start_pt__U436 op_hcompute_conv_stencil_8_exe_start ( - .in(delay_reg__U438_out), +op_hcompute_conv_stencil_8_exe_start_pt__U413 op_hcompute_conv_stencil_8_exe_start ( + .in(delay_reg__U415_out), .out(op_hcompute_conv_stencil_8_exe_start_out) ); wire [15:0] op_hcompute_conv_stencil_8_exe_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[4] = arr__U447_out[4]; -assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[3] = arr__U447_out[3]; -assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[2] = arr__U447_out[2]; -assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[1] = arr__U447_out[1]; -assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[0] = arr__U447_out[0]; -op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U439 op_hcompute_conv_stencil_8_exe_start_control_vars ( +assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[4] = arr__U424_out[4]; +assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[3] = arr__U424_out[3]; +assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[2] = arr__U424_out[2]; +assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[1] = arr__U424_out[1]; +assign op_hcompute_conv_stencil_8_exe_start_control_vars_in[0] = arr__U424_out[0]; +op_hcompute_conv_stencil_8_exe_start_control_vars_pt__U416 op_hcompute_conv_stencil_8_exe_start_control_vars ( .in(op_hcompute_conv_stencil_8_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_8_exe_start_control_vars_out) ); -affine_controller__U404 op_hcompute_conv_stencil_8_port_controller ( +affine_controller__U381 op_hcompute_conv_stencil_8_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_8_port_controller_valid), .d(op_hcompute_conv_stencil_8_port_controller_d) ); -op_hcompute_conv_stencil_8_read_start_pt__U434 op_hcompute_conv_stencil_8_read_start ( +op_hcompute_conv_stencil_8_read_start_pt__U411 op_hcompute_conv_stencil_8_read_start ( .in(op_hcompute_conv_stencil_8_port_controller_valid), .out(op_hcompute_conv_stencil_8_read_start_out) ); @@ -32173,21 +32173,21 @@ assign op_hcompute_conv_stencil_8_read_start_control_vars_in[3] = op_hcompute_co assign op_hcompute_conv_stencil_8_read_start_control_vars_in[2] = op_hcompute_conv_stencil_8_port_controller_d[2]; assign op_hcompute_conv_stencil_8_read_start_control_vars_in[1] = op_hcompute_conv_stencil_8_port_controller_d[1]; assign op_hcompute_conv_stencil_8_read_start_control_vars_in[0] = op_hcompute_conv_stencil_8_port_controller_d[0]; -op_hcompute_conv_stencil_8_read_start_control_vars_pt__U435 op_hcompute_conv_stencil_8_read_start_control_vars ( +op_hcompute_conv_stencil_8_read_start_control_vars_pt__U412 op_hcompute_conv_stencil_8_read_start_control_vars ( .in(op_hcompute_conv_stencil_8_read_start_control_vars_in), .out(op_hcompute_conv_stencil_8_read_start_control_vars_out) ); -op_hcompute_conv_stencil_8_write_start_pt__U454 op_hcompute_conv_stencil_8_write_start ( - .in(delay_reg__U471_out), +op_hcompute_conv_stencil_8_write_start_pt__U431 op_hcompute_conv_stencil_8_write_start ( + .in(delay_reg__U448_out), .out(op_hcompute_conv_stencil_8_write_start_out) ); wire [15:0] op_hcompute_conv_stencil_8_write_start_control_vars_in [4:0]; -assign op_hcompute_conv_stencil_8_write_start_control_vars_in[4] = arr__U585_out[4]; -assign op_hcompute_conv_stencil_8_write_start_control_vars_in[3] = arr__U585_out[3]; -assign op_hcompute_conv_stencil_8_write_start_control_vars_in[2] = arr__U585_out[2]; -assign op_hcompute_conv_stencil_8_write_start_control_vars_in[1] = arr__U585_out[1]; -assign op_hcompute_conv_stencil_8_write_start_control_vars_in[0] = arr__U585_out[0]; -op_hcompute_conv_stencil_8_write_start_control_vars_pt__U472 op_hcompute_conv_stencil_8_write_start_control_vars ( +assign op_hcompute_conv_stencil_8_write_start_control_vars_in[4] = arr__U562_out[4]; +assign op_hcompute_conv_stencil_8_write_start_control_vars_in[3] = arr__U562_out[3]; +assign op_hcompute_conv_stencil_8_write_start_control_vars_in[2] = arr__U562_out[2]; +assign op_hcompute_conv_stencil_8_write_start_control_vars_in[1] = arr__U562_out[1]; +assign op_hcompute_conv_stencil_8_write_start_control_vars_in[0] = arr__U562_out[0]; +op_hcompute_conv_stencil_8_write_start_control_vars_pt__U449 op_hcompute_conv_stencil_8_write_start_control_vars ( .in(op_hcompute_conv_stencil_8_write_start_control_vars_in), .out(op_hcompute_conv_stencil_8_write_start_control_vars_out) ); @@ -32265,7 +32265,7 @@ op_hcompute_conv_stencil_9_write_start_control_vars_pt__U660 op_hcompute_conv_st .in(op_hcompute_conv_stencil_9_write_start_control_vars_in), .out(op_hcompute_conv_stencil_9_write_start_control_vars_out) ); -op_hcompute_conv_stencil_exe_start_pt__U239 op_hcompute_conv_stencil_exe_start ( +op_hcompute_conv_stencil_exe_start_pt__U216 op_hcompute_conv_stencil_exe_start ( .in(op_hcompute_conv_stencil_port_controller_valid), .out(op_hcompute_conv_stencil_exe_start_out) ); @@ -32273,16 +32273,16 @@ wire [15:0] op_hcompute_conv_stencil_exe_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_exe_start_control_vars_in[2] = op_hcompute_conv_stencil_port_controller_d[2]; assign op_hcompute_conv_stencil_exe_start_control_vars_in[1] = op_hcompute_conv_stencil_port_controller_d[1]; assign op_hcompute_conv_stencil_exe_start_control_vars_in[0] = op_hcompute_conv_stencil_port_controller_d[0]; -op_hcompute_conv_stencil_exe_start_control_vars_pt__U240 op_hcompute_conv_stencil_exe_start_control_vars ( +op_hcompute_conv_stencil_exe_start_control_vars_pt__U217 op_hcompute_conv_stencil_exe_start_control_vars ( .in(op_hcompute_conv_stencil_exe_start_control_vars_in), .out(op_hcompute_conv_stencil_exe_start_control_vars_out) ); -affine_controller__U220 op_hcompute_conv_stencil_port_controller ( +affine_controller__U197 op_hcompute_conv_stencil_port_controller ( .clk(clk), .valid(op_hcompute_conv_stencil_port_controller_valid), .d(op_hcompute_conv_stencil_port_controller_d) ); -op_hcompute_conv_stencil_read_start_pt__U237 op_hcompute_conv_stencil_read_start ( +op_hcompute_conv_stencil_read_start_pt__U214 op_hcompute_conv_stencil_read_start ( .in(op_hcompute_conv_stencil_port_controller_valid), .out(op_hcompute_conv_stencil_read_start_out) ); @@ -32290,11 +32290,11 @@ wire [15:0] op_hcompute_conv_stencil_read_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_read_start_control_vars_in[2] = op_hcompute_conv_stencil_port_controller_d[2]; assign op_hcompute_conv_stencil_read_start_control_vars_in[1] = op_hcompute_conv_stencil_port_controller_d[1]; assign op_hcompute_conv_stencil_read_start_control_vars_in[0] = op_hcompute_conv_stencil_port_controller_d[0]; -op_hcompute_conv_stencil_read_start_control_vars_pt__U238 op_hcompute_conv_stencil_read_start_control_vars ( +op_hcompute_conv_stencil_read_start_control_vars_pt__U215 op_hcompute_conv_stencil_read_start_control_vars ( .in(op_hcompute_conv_stencil_read_start_control_vars_in), .out(op_hcompute_conv_stencil_read_start_control_vars_out) ); -op_hcompute_conv_stencil_write_start_pt__U241 op_hcompute_conv_stencil_write_start ( +op_hcompute_conv_stencil_write_start_pt__U218 op_hcompute_conv_stencil_write_start ( .in(op_hcompute_conv_stencil_port_controller_valid), .out(op_hcompute_conv_stencil_write_start_out) ); @@ -32302,25 +32302,25 @@ wire [15:0] op_hcompute_conv_stencil_write_start_control_vars_in [2:0]; assign op_hcompute_conv_stencil_write_start_control_vars_in[2] = op_hcompute_conv_stencil_port_controller_d[2]; assign op_hcompute_conv_stencil_write_start_control_vars_in[1] = op_hcompute_conv_stencil_port_controller_d[1]; assign op_hcompute_conv_stencil_write_start_control_vars_in[0] = op_hcompute_conv_stencil_port_controller_d[0]; -op_hcompute_conv_stencil_write_start_control_vars_pt__U242 op_hcompute_conv_stencil_write_start_control_vars ( +op_hcompute_conv_stencil_write_start_control_vars_pt__U219 op_hcompute_conv_stencil_write_start_control_vars ( .in(op_hcompute_conv_stencil_write_start_control_vars_in), .out(op_hcompute_conv_stencil_write_start_control_vars_out) ); -wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read [0:0]; -assign op_hcompute_hw_input_global_wrapper_stencil_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read[0] = hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read[0]; +wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read [0:0]; +assign op_hcompute_hw_input_global_wrapper_stencil_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read[0] = hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read[0]; cu_op_hcompute_hw_input_global_wrapper_stencil op_hcompute_hw_input_global_wrapper_stencil ( .clk(clk), - .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read(op_hcompute_hw_input_global_wrapper_stencil_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read), + .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read(op_hcompute_hw_input_global_wrapper_stencil_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write(op_hcompute_hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_write) ); -wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_1_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read [0:0]; -assign op_hcompute_hw_input_global_wrapper_stencil_1_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] = hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read[0]; +wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_1_hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read [0:0]; +assign op_hcompute_hw_input_global_wrapper_stencil_1_hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] = hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read[0]; cu_op_hcompute_hw_input_global_wrapper_stencil_1 op_hcompute_hw_input_global_wrapper_stencil_1 ( .clk(clk), - .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read(op_hcompute_hw_input_global_wrapper_stencil_1_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read), + .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read(op_hcompute_hw_input_global_wrapper_stencil_1_hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write(op_hcompute_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_write) ); -op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U42 op_hcompute_hw_input_global_wrapper_stencil_1_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_pt__U88 op_hcompute_hw_input_global_wrapper_stencil_1_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_out) ); @@ -32328,28 +32328,28 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U43 op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_pt__U89 op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_1_exe_start_control_vars_out) ); -affine_controller__U23 op_hcompute_hw_input_global_wrapper_stencil_1_port_controller ( +affine_controller__U69 op_hcompute_hw_input_global_wrapper_stencil_1_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U40 op_hcompute_hw_input_global_wrapper_stencil_1_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_1_read_start_pt__U86 op_hcompute_hw_input_global_wrapper_stencil_1_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_valid), - .out(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en) + .out(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en) ); wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_in [2:0]; assign op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U41 op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_pt__U87 op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_1_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U44 op_hcompute_hw_input_global_wrapper_stencil_1_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_1_write_start_pt__U90 op_hcompute_hw_input_global_wrapper_stencil_1_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_1_write_start_out) ); @@ -32357,18 +32357,18 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_va assign op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_1_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U45 op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_pt__U91 op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_1_write_start_control_vars_out) ); -wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_2_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read [0:0]; -assign op_hcompute_hw_input_global_wrapper_stencil_2_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] = hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read[0]; +wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_2_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read [0:0]; +assign op_hcompute_hw_input_global_wrapper_stencil_2_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] = hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read[0]; cu_op_hcompute_hw_input_global_wrapper_stencil_2 op_hcompute_hw_input_global_wrapper_stencil_2 ( .clk(clk), - .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read(op_hcompute_hw_input_global_wrapper_stencil_2_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read), + .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read(op_hcompute_hw_input_global_wrapper_stencil_2_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write(op_hcompute_hw_input_global_wrapper_stencil_2_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_write) ); -op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U65 op_hcompute_hw_input_global_wrapper_stencil_2_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_pt__U134 op_hcompute_hw_input_global_wrapper_stencil_2_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_out) ); @@ -32376,28 +32376,28 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U66 op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_pt__U135 op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_2_exe_start_control_vars_out) ); -affine_controller__U46 op_hcompute_hw_input_global_wrapper_stencil_2_port_controller ( +affine_controller__U115 op_hcompute_hw_input_global_wrapper_stencil_2_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U63 op_hcompute_hw_input_global_wrapper_stencil_2_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_2_read_start_pt__U132 op_hcompute_hw_input_global_wrapper_stencil_2_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_valid), - .out(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en) + .out(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en) ); wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_in [2:0]; assign op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U64 op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_pt__U133 op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_2_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U67 op_hcompute_hw_input_global_wrapper_stencil_2_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_2_write_start_pt__U136 op_hcompute_hw_input_global_wrapper_stencil_2_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_2_write_start_out) ); @@ -32405,18 +32405,18 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_va assign op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_2_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U68 op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_pt__U137 op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_2_write_start_control_vars_out) ); -wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_3_hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read [0:0]; -assign op_hcompute_hw_input_global_wrapper_stencil_3_hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] = hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read[0]; +wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_3_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read [0:0]; +assign op_hcompute_hw_input_global_wrapper_stencil_3_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] = hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read[0]; cu_op_hcompute_hw_input_global_wrapper_stencil_3 op_hcompute_hw_input_global_wrapper_stencil_3 ( .clk(clk), - .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read(op_hcompute_hw_input_global_wrapper_stencil_3_hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read), + .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read(op_hcompute_hw_input_global_wrapper_stencil_3_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write(op_hcompute_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_write) ); -op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U88 op_hcompute_hw_input_global_wrapper_stencil_3_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_pt__U111 op_hcompute_hw_input_global_wrapper_stencil_3_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_out) ); @@ -32424,28 +32424,28 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U89 op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_pt__U112 op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_3_exe_start_control_vars_out) ); -affine_controller__U69 op_hcompute_hw_input_global_wrapper_stencil_3_port_controller ( +affine_controller__U92 op_hcompute_hw_input_global_wrapper_stencil_3_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U86 op_hcompute_hw_input_global_wrapper_stencil_3_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_3_read_start_pt__U109 op_hcompute_hw_input_global_wrapper_stencil_3_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_valid), - .out(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en) + .out(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en) ); wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_in [2:0]; assign op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U87 op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_pt__U110 op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_3_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U90 op_hcompute_hw_input_global_wrapper_stencil_3_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_3_write_start_pt__U113 op_hcompute_hw_input_global_wrapper_stencil_3_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_3_write_start_out) ); @@ -32453,18 +32453,18 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_va assign op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_3_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U91 op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_pt__U114 op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_3_write_start_control_vars_out) ); -wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_4_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read [0:0]; -assign op_hcompute_hw_input_global_wrapper_stencil_4_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] = hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read[0]; +wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_4_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read [0:0]; +assign op_hcompute_hw_input_global_wrapper_stencil_4_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] = hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read[0]; cu_op_hcompute_hw_input_global_wrapper_stencil_4 op_hcompute_hw_input_global_wrapper_stencil_4 ( .clk(clk), - .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read(op_hcompute_hw_input_global_wrapper_stencil_4_hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read), + .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read(op_hcompute_hw_input_global_wrapper_stencil_4_hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write(op_hcompute_hw_input_global_wrapper_stencil_4_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_write) ); -op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U111 op_hcompute_hw_input_global_wrapper_stencil_4_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_pt__U19 op_hcompute_hw_input_global_wrapper_stencil_4_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_out) ); @@ -32472,28 +32472,28 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U112 op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_pt__U20 op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_4_exe_start_control_vars_out) ); -affine_controller__U92 op_hcompute_hw_input_global_wrapper_stencil_4_port_controller ( +affine_controller__U0 op_hcompute_hw_input_global_wrapper_stencil_4_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U109 op_hcompute_hw_input_global_wrapper_stencil_4_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_4_read_start_pt__U17 op_hcompute_hw_input_global_wrapper_stencil_4_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_valid), - .out(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en) + .out(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en) ); wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_in [2:0]; assign op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U110 op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_pt__U18 op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_4_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U113 op_hcompute_hw_input_global_wrapper_stencil_4_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_4_write_start_pt__U21 op_hcompute_hw_input_global_wrapper_stencil_4_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_4_write_start_out) ); @@ -32501,18 +32501,18 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_va assign op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_4_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U114 op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_pt__U22 op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_4_write_start_control_vars_out) ); -wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_5_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read [0:0]; -assign op_hcompute_hw_input_global_wrapper_stencil_5_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] = hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read[0]; +wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_5_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read [0:0]; +assign op_hcompute_hw_input_global_wrapper_stencil_5_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] = hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read[0]; cu_op_hcompute_hw_input_global_wrapper_stencil_5 op_hcompute_hw_input_global_wrapper_stencil_5 ( .clk(clk), - .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read(op_hcompute_hw_input_global_wrapper_stencil_5_hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read), + .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read(op_hcompute_hw_input_global_wrapper_stencil_5_hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write(op_hcompute_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_write) ); -op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U134 op_hcompute_hw_input_global_wrapper_stencil_5_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_pt__U42 op_hcompute_hw_input_global_wrapper_stencil_5_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_out) ); @@ -32520,28 +32520,28 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U135 op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_pt__U43 op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_5_exe_start_control_vars_out) ); -affine_controller__U115 op_hcompute_hw_input_global_wrapper_stencil_5_port_controller ( +affine_controller__U23 op_hcompute_hw_input_global_wrapper_stencil_5_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U132 op_hcompute_hw_input_global_wrapper_stencil_5_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_5_read_start_pt__U40 op_hcompute_hw_input_global_wrapper_stencil_5_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_valid), - .out(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en) + .out(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en) ); wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_in [2:0]; assign op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U133 op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_pt__U41 op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_5_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U136 op_hcompute_hw_input_global_wrapper_stencil_5_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_5_write_start_pt__U44 op_hcompute_hw_input_global_wrapper_stencil_5_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_5_write_start_out) ); @@ -32549,18 +32549,18 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_va assign op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_5_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U137 op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_pt__U45 op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_5_write_start_control_vars_out) ); -wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_6_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read [0:0]; -assign op_hcompute_hw_input_global_wrapper_stencil_6_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] = hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read[0]; +wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_6_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read [0:0]; +assign op_hcompute_hw_input_global_wrapper_stencil_6_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] = hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read[0]; cu_op_hcompute_hw_input_global_wrapper_stencil_6 op_hcompute_hw_input_global_wrapper_stencil_6 ( .clk(clk), - .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read(op_hcompute_hw_input_global_wrapper_stencil_6_hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read), + .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read(op_hcompute_hw_input_global_wrapper_stencil_6_hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write(op_hcompute_hw_input_global_wrapper_stencil_6_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_write) ); -op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U157 op_hcompute_hw_input_global_wrapper_stencil_6_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_pt__U65 op_hcompute_hw_input_global_wrapper_stencil_6_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_out) ); @@ -32568,28 +32568,28 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U158 op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_pt__U66 op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_6_exe_start_control_vars_out) ); -affine_controller__U138 op_hcompute_hw_input_global_wrapper_stencil_6_port_controller ( +affine_controller__U46 op_hcompute_hw_input_global_wrapper_stencil_6_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U155 op_hcompute_hw_input_global_wrapper_stencil_6_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_6_read_start_pt__U63 op_hcompute_hw_input_global_wrapper_stencil_6_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_valid), - .out(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en) + .out(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en) ); wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_in [2:0]; assign op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U156 op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_pt__U64 op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_6_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U159 op_hcompute_hw_input_global_wrapper_stencil_6_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_6_write_start_pt__U67 op_hcompute_hw_input_global_wrapper_stencil_6_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_6_write_start_out) ); @@ -32597,7 +32597,7 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_va assign op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_6_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U160 op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_pt__U68 op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_6_write_start_control_vars_out) ); @@ -32608,7 +32608,7 @@ cu_op_hcompute_hw_input_global_wrapper_stencil_7 op_hcompute_hw_input_global_wra .hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read(op_hcompute_hw_input_global_wrapper_stencil_7_hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read), .hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_write(op_hcompute_hw_input_global_wrapper_stencil_7_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_write) ); -op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U180 op_hcompute_hw_input_global_wrapper_stencil_7_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_pt__U588 op_hcompute_hw_input_global_wrapper_stencil_7_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_out) ); @@ -32616,16 +32616,16 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U181 op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_pt__U589 op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_7_exe_start_control_vars_out) ); -affine_controller__U161 op_hcompute_hw_input_global_wrapper_stencil_7_port_controller ( +affine_controller__U569 op_hcompute_hw_input_global_wrapper_stencil_7_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U178 op_hcompute_hw_input_global_wrapper_stencil_7_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_7_read_start_pt__U586 op_hcompute_hw_input_global_wrapper_stencil_7_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_valid), .out(hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en) ); @@ -32633,11 +32633,11 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_var assign op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U179 op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_pt__U587 op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_7_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U182 op_hcompute_hw_input_global_wrapper_stencil_7_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_7_write_start_pt__U590 op_hcompute_hw_input_global_wrapper_stencil_7_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_7_write_start_out) ); @@ -32645,11 +32645,11 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_va assign op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_7_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U183 op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_pt__U591 op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_7_write_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U19 op_hcompute_hw_input_global_wrapper_stencil_exe_start ( +op_hcompute_hw_input_global_wrapper_stencil_exe_start_pt__U157 op_hcompute_hw_input_global_wrapper_stencil_exe_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_exe_start_out) ); @@ -32657,28 +32657,28 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_i assign op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U20 op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_pt__U158 op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_exe_start_control_vars_out) ); -affine_controller__U0 op_hcompute_hw_input_global_wrapper_stencil_port_controller ( +affine_controller__U138 op_hcompute_hw_input_global_wrapper_stencil_port_controller ( .clk(clk), .valid(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), .d(op_hcompute_hw_input_global_wrapper_stencil_port_controller_d) ); -op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U17 op_hcompute_hw_input_global_wrapper_stencil_read_start ( +op_hcompute_hw_input_global_wrapper_stencil_read_start_pt__U155 op_hcompute_hw_input_global_wrapper_stencil_read_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), - .out(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en) + .out(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en) ); wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in [2:0]; assign op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U18 op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_pt__U156 op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_read_start_control_vars_out) ); -op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U21 op_hcompute_hw_input_global_wrapper_stencil_write_start ( +op_hcompute_hw_input_global_wrapper_stencil_write_start_pt__U159 op_hcompute_hw_input_global_wrapper_stencil_write_start ( .in(op_hcompute_hw_input_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_input_global_wrapper_stencil_write_start_out) ); @@ -32686,7 +32686,7 @@ wire [15:0] op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars assign op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in[2] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in[1] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in[0] = op_hcompute_hw_input_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U22 op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars ( +op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_pt__U160 op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars ( .in(op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_in), .out(op_hcompute_hw_input_global_wrapper_stencil_write_start_control_vars_out) ); @@ -32697,7 +32697,7 @@ cu_op_hcompute_hw_kernel_global_wrapper_stencil op_hcompute_hw_kernel_global_wra .hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read(op_hcompute_hw_kernel_global_wrapper_stencil_hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read), .hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write(op_hcompute_hw_kernel_global_wrapper_stencil_hw_kernel_global_wrapper_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_write) ); -op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U216 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start ( +op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_pt__U193 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_out) ); @@ -32707,16 +32707,16 @@ assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[3] assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[2] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[1] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in[0] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U217 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars ( +op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_pt__U194 op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_in), .out(op_hcompute_hw_kernel_global_wrapper_stencil_exe_start_control_vars_out) ); -affine_controller__U184 op_hcompute_hw_kernel_global_wrapper_stencil_port_controller ( +affine_controller__U161 op_hcompute_hw_kernel_global_wrapper_stencil_port_controller ( .clk(clk), .valid(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .d(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d) ); -op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U214 op_hcompute_hw_kernel_global_wrapper_stencil_read_start ( +op_hcompute_hw_kernel_global_wrapper_stencil_read_start_pt__U191 op_hcompute_hw_kernel_global_wrapper_stencil_read_start ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .out(hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en) ); @@ -32726,11 +32726,11 @@ assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[3 assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[2] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[1] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in[0] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U215 op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars ( +op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_pt__U192 op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_in), .out(op_hcompute_hw_kernel_global_wrapper_stencil_read_start_control_vars_out) ); -op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U218 op_hcompute_hw_kernel_global_wrapper_stencil_write_start ( +op_hcompute_hw_kernel_global_wrapper_stencil_write_start_pt__U195 op_hcompute_hw_kernel_global_wrapper_stencil_write_start ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_valid), .out(op_hcompute_hw_kernel_global_wrapper_stencil_write_start_out) ); @@ -32740,7 +32740,7 @@ assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[ assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[2] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[2]; assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[1] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[1]; assign op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in[0] = op_hcompute_hw_kernel_global_wrapper_stencil_port_controller_d[0]; -op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U219 op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars ( +op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_pt__U196 op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars ( .in(op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_in), .out(op_hcompute_hw_kernel_global_wrapper_stencil_write_start_control_vars_out) ); diff --git a/coreir_apps/platonic_buffer/resnet88/resnet88_deepak_power_flow_tb.sv b/coreir_apps/platonic_buffer/resnet88/resnet88_deepak_power_flow_tb.sv index cddc56d0c..e62d92c12 100644 --- a/coreir_apps/platonic_buffer/resnet88/resnet88_deepak_power_flow_tb.sv +++ b/coreir_apps/platonic_buffer/resnet88/resnet88_deepak_power_flow_tb.sv @@ -36,20 +36,20 @@ initial begin $finish(2); end - logic hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en; - logic [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read [0 :0]; - logic hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en; - logic [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read [0 :0]; - logic hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en; - logic [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read [0 :0]; - logic hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en; - logic [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read [0 :0]; - logic hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en; - logic [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read [0 :0]; - logic hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en; - logic [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read [0 :0]; - logic hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en; - logic [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read [0 :0]; + logic hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en; + logic [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read [0 :0]; + logic hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en; + logic [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read [0 :0]; + logic hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en; + logic [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read [0 :0]; + logic hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en; + logic [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read [0 :0]; + logic hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en; + logic [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read [0 :0]; + logic hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en; + logic [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read [0 :0]; + logic hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en; + logic [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read [0 :0]; logic hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en; logic [15:0] hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read [0 :0]; logic hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en; @@ -75,20 +75,20 @@ initial begin .clk(clk), .flush(flush), .rst_n(rst), - .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en), - .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read), - .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en), - .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read), - .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en), - .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read), - .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en), - .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read), - .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en), - .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read), - .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en), - .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read), - .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en), - .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read), + .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en), + .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read), + .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en), + .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read), + .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en), + .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read), + .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en), + .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read), + .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en), + .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read), + .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en), + .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read), + .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en), + .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read), .hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en(hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en), .hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read(hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read), .hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en(hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en), @@ -113,13 +113,13 @@ initial begin always @(negedge clk) begin - hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read[0] <= #`ASSIGNMENT_DELAY $urandom; - hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] <= #`ASSIGNMENT_DELAY $urandom; - hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] <= #`ASSIGNMENT_DELAY $urandom; - hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] <= #`ASSIGNMENT_DELAY $urandom; - hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] <= #`ASSIGNMENT_DELAY $urandom; - hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] <= #`ASSIGNMENT_DELAY $urandom; - hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] <= #`ASSIGNMENT_DELAY $urandom; + hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] <= #`ASSIGNMENT_DELAY $urandom; + hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] <= #`ASSIGNMENT_DELAY $urandom; + hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] <= #`ASSIGNMENT_DELAY $urandom; + hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] <= #`ASSIGNMENT_DELAY $urandom; + hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] <= #`ASSIGNMENT_DELAY $urandom; + hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] <= #`ASSIGNMENT_DELAY $urandom; + hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read[0] <= #`ASSIGNMENT_DELAY $urandom; hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read[0] <= #`ASSIGNMENT_DELAY $urandom; hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read[0] <= #`ASSIGNMENT_DELAY $urandom; end diff --git a/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_collateral.sv b/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_collateral.sv index fe5a6eb21..c478ae884 100644 --- a/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_collateral.sv +++ b/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_collateral.sv @@ -3476,12 +3476,16 @@ conv_stencil_embarassing_bank_selector conv_stencil_conv_stencil_op_hcompute_hw_ endmodule -// hw_input_global_wrapper_stencil has embarassing partition: 1 +// hw_input_global_wrapper_stencil has embarassing partition: 0 -module hw_input_global_wrapper_stencil_embarassing_bank_selector(input logic [16*3 - 1 :0] d, output logic [15:0] out); +module hw_input_global_wrapper_stencil_bank_selector(input logic [16*3 - 1 :0] d, output logic [15:0] out); + logic [15:0] bank_index_0; + assign bank_index_0 = (d[15:0] % 1); + logic [15:0] bank_index_1; + assign bank_index_1 = (d[31:16] % 1); logic [15:0] bank_index_2; - assign bank_index_2 = (d[47:32]); - assign out = 0+bank_index_2*1; + assign bank_index_2 = (d[47:32] % 1); + assign out = bank_index_0*1+bank_index_1*1+bank_index_2*1; endmodule @@ -6556,522 +6560,515 @@ module hw_input_global_wrapper_stencil_ub( logic [15:0]op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4:0]; logic op_hcompute_conv_stencil_9_read_ren_fsm_out; hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_read_fsm hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_read_fsm_inst (.clk(clk), .flush(flush), .rst_n(rst_n), .op_hcompute_conv_stencil_9_read_ctrl_vars( op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out), .op_hcompute_conv_stencil_9_read_ren(op_hcompute_conv_stencil_9_read_ren_fsm_out)); - // # of banks: 8 - logic [15:0] bank_0 [900]; - logic [15:0] bank_1 [900]; - logic [15:0] bank_2 [900]; - logic [15:0] bank_3 [900]; - logic [15:0] bank_4 [900]; - logic [15:0] bank_5 [900]; - logic [15:0] bank_6 [900]; - logic [15:0] bank_7 [900]; + // # of banks: 1 + logic [15:0] bank_0 [7200]; logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_1_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_1_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_1_30_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_2_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_2_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_2_28_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_32_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_3_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_3_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_3_26_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_4_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_4_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_4_24_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_5_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_5_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_5_22_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_6_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_6_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_6_20_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_0 = (((1*op_hcompute_hw_input_global_wrapper_stencil_7_write_ctrl_vars_fsm_out[1])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_1 = (((1*op_hcompute_hw_input_global_wrapper_stencil_7_write_ctrl_vars_fsm_out[2])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_hw_input_global_wrapper_stencil_7_18_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_168_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_169_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_170_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_171_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_172_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_173_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_174_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_0 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_1 = (((1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_10_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_10_175_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_150_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_151_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_152_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_153_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_154_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_155_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_156_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_0 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_1 = (((1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_11_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_11_157_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_132_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_133_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_134_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_135_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_136_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_137_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_138_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_0 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_1 = (((1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_12_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_12_139_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_114_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_115_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_116_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_117_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_118_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_119_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_120_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_0 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_1 = (((1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_13_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_13_121_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_100_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_101_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_102_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_103_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_96_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_97_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_98_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_0 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_1 = (((1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_14_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_14_99_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_78_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_79_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_80_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_81_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_82_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_83_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_84_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_0 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_1 = (((1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_15_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_15_85_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_54_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_55_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_56_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_57_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_58_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_59_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_60_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_0 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_1 = (((1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_8_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_8_61_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_2 = (((1)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_2 = (((2)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_2 = (((3)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_2 = (((4)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_2 = (((5)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_2 = (((7)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_2 = (((6)) - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_0})); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_0; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_0 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_1; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_1 = (((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0); logic [15:0] hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_2; assign hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_2 = (0 - 0); -hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_0})); +hw_input_global_wrapper_stencil_bank_selector hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_bank_selector(.d({hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_2,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_1,hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_0})); logic [15:0] addr0; - assign addr0 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_1_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_1_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr0 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_1_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_1_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((1)) - 0)>>0)*900); logic [15:0] delay_wire_96; always @(posedge clk) begin delay_wire_96 <= addr0; @@ -7089,7 +7086,7 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_99 <= op_hcompute_hw_input_global_wrapper_stencil_1_write[0]; end logic [15:0] addr1; - assign addr1 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_2_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_2_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr1 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_2_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_2_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((2)) - 0)>>0)*900); logic [15:0] delay_wire_100; always @(posedge clk) begin delay_wire_100 <= addr1; @@ -7107,7 +7104,7 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_103 <= op_hcompute_hw_input_global_wrapper_stencil_2_write[0]; end logic [15:0] addr2; - assign addr2 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr2 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((0 - 0)>>0)*900); logic [15:0] delay_wire_104; always @(posedge clk) begin delay_wire_104 <= addr2; @@ -7125,7 +7122,7 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_107 <= op_hcompute_hw_input_global_wrapper_stencil_write[0]; end logic [15:0] addr3; - assign addr3 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_3_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_3_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr3 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_3_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_3_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((3)) - 0)>>0)*900); logic [15:0] delay_wire_108; always @(posedge clk) begin delay_wire_108 <= addr3; @@ -7143,7 +7140,7 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_111 <= op_hcompute_hw_input_global_wrapper_stencil_3_write[0]; end logic [15:0] addr4; - assign addr4 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_4_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_4_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr4 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_4_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_4_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((4)) - 0)>>0)*900); logic [15:0] delay_wire_112; always @(posedge clk) begin delay_wire_112 <= addr4; @@ -7161,7 +7158,7 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_115 <= op_hcompute_hw_input_global_wrapper_stencil_4_write[0]; end logic [15:0] addr5; - assign addr5 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_5_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_5_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr5 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_5_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_5_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((5)) - 0)>>0)*900); logic [15:0] delay_wire_116; always @(posedge clk) begin delay_wire_116 <= addr5; @@ -7179,7 +7176,7 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_119 <= op_hcompute_hw_input_global_wrapper_stencil_5_write[0]; end logic [15:0] addr6; - assign addr6 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_6_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_6_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr6 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_6_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_6_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((6)) - 0)>>0)*900); logic [15:0] delay_wire_120; always @(posedge clk) begin delay_wire_120 <= addr6; @@ -7197,7 +7194,7 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_123 <= op_hcompute_hw_input_global_wrapper_stencil_6_write[0]; end logic [15:0] addr7; - assign addr7 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_7_write_ctrl_vars_fsm_out[1])) - 0))*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_7_write_ctrl_vars_fsm_out[2])) - 0))*30); + assign addr7 = (((((1*op_hcompute_hw_input_global_wrapper_stencil_7_write_ctrl_vars_fsm_out[1])) - 0)>>0)*1+((((1*op_hcompute_hw_input_global_wrapper_stencil_7_write_ctrl_vars_fsm_out[2])) - 0)>>0)*30+((((7)) - 0)>>0)*900); logic [15:0] delay_wire_124; always @(posedge clk) begin delay_wire_124 <= addr7; @@ -7215,49 +7212,49 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe delay_wire_127 <= op_hcompute_hw_input_global_wrapper_stencil_7_write[0]; end logic [15:0] addr8; - assign addr8 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr8 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((1)) - 0)>>0)*900); logic [15:0] end_delay_wire_128; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[0] <= end_delay_wire_128; end logic [15:0] addr9; - assign addr9 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr9 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((2)) - 0)>>0)*900); logic [15:0] end_delay_wire_129; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[1] <= end_delay_wire_129; end logic [15:0] addr10; - assign addr10 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr10 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((3)) - 0)>>0)*900); logic [15:0] end_delay_wire_130; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[2] <= end_delay_wire_130; end logic [15:0] addr11; - assign addr11 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr11 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((4)) - 0)>>0)*900); logic [15:0] end_delay_wire_131; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[3] <= end_delay_wire_131; end logic [15:0] addr12; - assign addr12 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr12 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((5)) - 0)>>0)*900); logic [15:0] end_delay_wire_132; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[4] <= end_delay_wire_132; end logic [15:0] addr13; - assign addr13 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr13 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((7)) - 0)>>0)*900); logic [15:0] end_delay_wire_133; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[5] <= end_delay_wire_133; end logic [15:0] addr14; - assign addr14 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr14 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((((6)) - 0)>>0)*900); logic [15:0] end_delay_wire_134; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[6] <= end_delay_wire_134; end logic [15:0] addr15; - assign addr15 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0))*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0))*30); + assign addr15 = (((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[1] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[3])) - 0)>>0)*1+((((1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[2] + 1*op_hcompute_conv_stencil_9_read_ctrl_vars_fsm_out[4])) - 0)>>0)*30+((0 - 0)>>0)*900); logic [15:0] end_delay_wire_135; always @(posedge clk) begin op_hcompute_conv_stencil_9_read[7] <= end_delay_wire_135; @@ -7266,105 +7263,49 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe if (delay_wire_98) begin case( delay_wire_97) 0:bank_0[delay_wire_96] <= delay_wire_99; - 1:bank_1[delay_wire_96] <= delay_wire_99; - 2:bank_2[delay_wire_96] <= delay_wire_99; - 3:bank_3[delay_wire_96] <= delay_wire_99; - 4:bank_4[delay_wire_96] <= delay_wire_99; - 5:bank_5[delay_wire_96] <= delay_wire_99; - 6:bank_6[delay_wire_96] <= delay_wire_99; - 7:bank_7[delay_wire_96] <= delay_wire_99; - default:bank_7[delay_wire_96] <= delay_wire_99; + default:bank_0[delay_wire_96] <= delay_wire_99; endcase end if (delay_wire_102) begin case( delay_wire_101) 0:bank_0[delay_wire_100] <= delay_wire_103; - 1:bank_1[delay_wire_100] <= delay_wire_103; - 2:bank_2[delay_wire_100] <= delay_wire_103; - 3:bank_3[delay_wire_100] <= delay_wire_103; - 4:bank_4[delay_wire_100] <= delay_wire_103; - 5:bank_5[delay_wire_100] <= delay_wire_103; - 6:bank_6[delay_wire_100] <= delay_wire_103; - 7:bank_7[delay_wire_100] <= delay_wire_103; - default:bank_7[delay_wire_100] <= delay_wire_103; + default:bank_0[delay_wire_100] <= delay_wire_103; endcase end if (delay_wire_106) begin case( delay_wire_105) 0:bank_0[delay_wire_104] <= delay_wire_107; - 1:bank_1[delay_wire_104] <= delay_wire_107; - 2:bank_2[delay_wire_104] <= delay_wire_107; - 3:bank_3[delay_wire_104] <= delay_wire_107; - 4:bank_4[delay_wire_104] <= delay_wire_107; - 5:bank_5[delay_wire_104] <= delay_wire_107; - 6:bank_6[delay_wire_104] <= delay_wire_107; - 7:bank_7[delay_wire_104] <= delay_wire_107; - default:bank_7[delay_wire_104] <= delay_wire_107; + default:bank_0[delay_wire_104] <= delay_wire_107; endcase end if (delay_wire_110) begin case( delay_wire_109) 0:bank_0[delay_wire_108] <= delay_wire_111; - 1:bank_1[delay_wire_108] <= delay_wire_111; - 2:bank_2[delay_wire_108] <= delay_wire_111; - 3:bank_3[delay_wire_108] <= delay_wire_111; - 4:bank_4[delay_wire_108] <= delay_wire_111; - 5:bank_5[delay_wire_108] <= delay_wire_111; - 6:bank_6[delay_wire_108] <= delay_wire_111; - 7:bank_7[delay_wire_108] <= delay_wire_111; - default:bank_7[delay_wire_108] <= delay_wire_111; + default:bank_0[delay_wire_108] <= delay_wire_111; endcase end if (delay_wire_114) begin case( delay_wire_113) 0:bank_0[delay_wire_112] <= delay_wire_115; - 1:bank_1[delay_wire_112] <= delay_wire_115; - 2:bank_2[delay_wire_112] <= delay_wire_115; - 3:bank_3[delay_wire_112] <= delay_wire_115; - 4:bank_4[delay_wire_112] <= delay_wire_115; - 5:bank_5[delay_wire_112] <= delay_wire_115; - 6:bank_6[delay_wire_112] <= delay_wire_115; - 7:bank_7[delay_wire_112] <= delay_wire_115; - default:bank_7[delay_wire_112] <= delay_wire_115; + default:bank_0[delay_wire_112] <= delay_wire_115; endcase end if (delay_wire_118) begin case( delay_wire_117) 0:bank_0[delay_wire_116] <= delay_wire_119; - 1:bank_1[delay_wire_116] <= delay_wire_119; - 2:bank_2[delay_wire_116] <= delay_wire_119; - 3:bank_3[delay_wire_116] <= delay_wire_119; - 4:bank_4[delay_wire_116] <= delay_wire_119; - 5:bank_5[delay_wire_116] <= delay_wire_119; - 6:bank_6[delay_wire_116] <= delay_wire_119; - 7:bank_7[delay_wire_116] <= delay_wire_119; - default:bank_7[delay_wire_116] <= delay_wire_119; + default:bank_0[delay_wire_116] <= delay_wire_119; endcase end if (delay_wire_122) begin case( delay_wire_121) 0:bank_0[delay_wire_120] <= delay_wire_123; - 1:bank_1[delay_wire_120] <= delay_wire_123; - 2:bank_2[delay_wire_120] <= delay_wire_123; - 3:bank_3[delay_wire_120] <= delay_wire_123; - 4:bank_4[delay_wire_120] <= delay_wire_123; - 5:bank_5[delay_wire_120] <= delay_wire_123; - 6:bank_6[delay_wire_120] <= delay_wire_123; - 7:bank_7[delay_wire_120] <= delay_wire_123; - default:bank_7[delay_wire_120] <= delay_wire_123; + default:bank_0[delay_wire_120] <= delay_wire_123; endcase end if (delay_wire_126) begin case( delay_wire_125) 0:bank_0[delay_wire_124] <= delay_wire_127; - 1:bank_1[delay_wire_124] <= delay_wire_127; - 2:bank_2[delay_wire_124] <= delay_wire_127; - 3:bank_3[delay_wire_124] <= delay_wire_127; - 4:bank_4[delay_wire_124] <= delay_wire_127; - 5:bank_5[delay_wire_124] <= delay_wire_127; - 6:bank_6[delay_wire_124] <= delay_wire_127; - 7:bank_7[delay_wire_124] <= delay_wire_127; - default:bank_7[delay_wire_124] <= delay_wire_127; + default:bank_0[delay_wire_124] <= delay_wire_127; endcase end end @@ -7372,104 +7313,48 @@ hw_input_global_wrapper_stencil_embarassing_bank_selector hw_input_global_wrappe if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_36_bank_selector.out) 0:end_delay_wire_128 <= bank_0[addr8]; - 1:end_delay_wire_128 <= bank_1[addr8]; - 2:end_delay_wire_128 <= bank_2[addr8]; - 3:end_delay_wire_128 <= bank_3[addr8]; - 4:end_delay_wire_128 <= bank_4[addr8]; - 5:end_delay_wire_128 <= bank_5[addr8]; - 6:end_delay_wire_128 <= bank_6[addr8]; - 7:end_delay_wire_128 <= bank_7[addr8]; default:end_delay_wire_128 <= 327; endcase end if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_37_bank_selector.out) 0:end_delay_wire_129 <= bank_0[addr9]; - 1:end_delay_wire_129 <= bank_1[addr9]; - 2:end_delay_wire_129 <= bank_2[addr9]; - 3:end_delay_wire_129 <= bank_3[addr9]; - 4:end_delay_wire_129 <= bank_4[addr9]; - 5:end_delay_wire_129 <= bank_5[addr9]; - 6:end_delay_wire_129 <= bank_6[addr9]; - 7:end_delay_wire_129 <= bank_7[addr9]; default:end_delay_wire_129 <= 327; endcase end if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_38_bank_selector.out) 0:end_delay_wire_130 <= bank_0[addr10]; - 1:end_delay_wire_130 <= bank_1[addr10]; - 2:end_delay_wire_130 <= bank_2[addr10]; - 3:end_delay_wire_130 <= bank_3[addr10]; - 4:end_delay_wire_130 <= bank_4[addr10]; - 5:end_delay_wire_130 <= bank_5[addr10]; - 6:end_delay_wire_130 <= bank_6[addr10]; - 7:end_delay_wire_130 <= bank_7[addr10]; default:end_delay_wire_130 <= 327; endcase end if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_39_bank_selector.out) 0:end_delay_wire_131 <= bank_0[addr11]; - 1:end_delay_wire_131 <= bank_1[addr11]; - 2:end_delay_wire_131 <= bank_2[addr11]; - 3:end_delay_wire_131 <= bank_3[addr11]; - 4:end_delay_wire_131 <= bank_4[addr11]; - 5:end_delay_wire_131 <= bank_5[addr11]; - 6:end_delay_wire_131 <= bank_6[addr11]; - 7:end_delay_wire_131 <= bank_7[addr11]; default:end_delay_wire_131 <= 327; endcase end if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_40_bank_selector.out) 0:end_delay_wire_132 <= bank_0[addr12]; - 1:end_delay_wire_132 <= bank_1[addr12]; - 2:end_delay_wire_132 <= bank_2[addr12]; - 3:end_delay_wire_132 <= bank_3[addr12]; - 4:end_delay_wire_132 <= bank_4[addr12]; - 5:end_delay_wire_132 <= bank_5[addr12]; - 6:end_delay_wire_132 <= bank_6[addr12]; - 7:end_delay_wire_132 <= bank_7[addr12]; default:end_delay_wire_132 <= 327; endcase end if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_41_bank_selector.out) 0:end_delay_wire_133 <= bank_0[addr13]; - 1:end_delay_wire_133 <= bank_1[addr13]; - 2:end_delay_wire_133 <= bank_2[addr13]; - 3:end_delay_wire_133 <= bank_3[addr13]; - 4:end_delay_wire_133 <= bank_4[addr13]; - 5:end_delay_wire_133 <= bank_5[addr13]; - 6:end_delay_wire_133 <= bank_6[addr13]; - 7:end_delay_wire_133 <= bank_7[addr13]; default:end_delay_wire_133 <= 327; endcase end if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_42_bank_selector.out) 0:end_delay_wire_134 <= bank_0[addr14]; - 1:end_delay_wire_134 <= bank_1[addr14]; - 2:end_delay_wire_134 <= bank_2[addr14]; - 3:end_delay_wire_134 <= bank_3[addr14]; - 4:end_delay_wire_134 <= bank_4[addr14]; - 5:end_delay_wire_134 <= bank_5[addr14]; - 6:end_delay_wire_134 <= bank_6[addr14]; - 7:end_delay_wire_134 <= bank_7[addr14]; default:end_delay_wire_134 <= 327; endcase end if (op_hcompute_conv_stencil_9_read_ren_fsm_out) begin case( hw_input_global_wrapper_stencil_hw_input_global_wrapper_stencil_op_hcompute_conv_stencil_9_43_bank_selector.out) 0:end_delay_wire_135 <= bank_0[addr15]; - 1:end_delay_wire_135 <= bank_1[addr15]; - 2:end_delay_wire_135 <= bank_2[addr15]; - 3:end_delay_wire_135 <= bank_3[addr15]; - 4:end_delay_wire_135 <= bank_4[addr15]; - 5:end_delay_wire_135 <= bank_5[addr15]; - 6:end_delay_wire_135 <= bank_6[addr15]; - 7:end_delay_wire_135 <= bank_7[addr15]; default:end_delay_wire_135 <= 327; endcase end diff --git a/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_tb.cpp b/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_tb.cpp index 0042f1978..742d0c925 100644 --- a/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_tb.cpp +++ b/coreir_apps/platonic_buffer/resnet88/resnet88_verilog_tb.cpp @@ -26,9 +26,9 @@ int main() { // Loading input data srand(1); - // cmap : { op_hcompute_hw_input_global_wrapper_stencil[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_0[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 0] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } - // read map: { hw_input_stencil_clkwrk_0[i0, i1, 0] -> op_hcompute_hw_input_global_wrapper_stencil[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } - // rng : { op_hcompute_hw_input_global_wrapper_stencil[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // cmap : { op_hcompute_hw_input_global_wrapper_stencil_4[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_0[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 4] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // read map: { hw_input_stencil_clkwrk_0[i0, i1, 4] -> op_hcompute_hw_input_global_wrapper_stencil_4[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } + // rng : { op_hcompute_hw_input_global_wrapper_stencil_4[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } // rng card: { 900 } for (int i = 0; i < 900; i++) { hw_uint<16 > value; @@ -36,9 +36,9 @@ int main() { hw_input_stencil_clkwrk_0.write(value); } - // cmap : { op_hcompute_hw_input_global_wrapper_stencil_1[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_1[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 1] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } - // read map: { hw_input_stencil_clkwrk_1[i0, i1, 1] -> op_hcompute_hw_input_global_wrapper_stencil_1[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } - // rng : { op_hcompute_hw_input_global_wrapper_stencil_1[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // cmap : { op_hcompute_hw_input_global_wrapper_stencil_5[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_1[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 5] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // read map: { hw_input_stencil_clkwrk_1[i0, i1, 5] -> op_hcompute_hw_input_global_wrapper_stencil_5[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } + // rng : { op_hcompute_hw_input_global_wrapper_stencil_5[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } // rng card: { 900 } for (int i = 0; i < 900; i++) { hw_uint<16 > value; @@ -46,9 +46,9 @@ int main() { hw_input_stencil_clkwrk_1.write(value); } - // cmap : { op_hcompute_hw_input_global_wrapper_stencil_2[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_2[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 2] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } - // read map: { hw_input_stencil_clkwrk_2[i0, i1, 2] -> op_hcompute_hw_input_global_wrapper_stencil_2[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } - // rng : { op_hcompute_hw_input_global_wrapper_stencil_2[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // cmap : { op_hcompute_hw_input_global_wrapper_stencil_6[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_2[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 6] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // read map: { hw_input_stencil_clkwrk_2[i0, i1, 6] -> op_hcompute_hw_input_global_wrapper_stencil_6[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } + // rng : { op_hcompute_hw_input_global_wrapper_stencil_6[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } // rng card: { 900 } for (int i = 0; i < 900; i++) { hw_uint<16 > value; @@ -56,9 +56,9 @@ int main() { hw_input_stencil_clkwrk_2.write(value); } - // cmap : { op_hcompute_hw_input_global_wrapper_stencil_3[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_3[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 3] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } - // read map: { hw_input_stencil_clkwrk_3[i0, i1, 3] -> op_hcompute_hw_input_global_wrapper_stencil_3[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } - // rng : { op_hcompute_hw_input_global_wrapper_stencil_3[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // cmap : { op_hcompute_hw_input_global_wrapper_stencil_1[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_3[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 1] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // read map: { hw_input_stencil_clkwrk_3[i0, i1, 1] -> op_hcompute_hw_input_global_wrapper_stencil_1[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } + // rng : { op_hcompute_hw_input_global_wrapper_stencil_1[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } // rng card: { 900 } for (int i = 0; i < 900; i++) { hw_uint<16 > value; @@ -66,9 +66,9 @@ int main() { hw_input_stencil_clkwrk_3.write(value); } - // cmap : { op_hcompute_hw_input_global_wrapper_stencil_4[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_4[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 4] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } - // read map: { hw_input_stencil_clkwrk_4[i0, i1, 4] -> op_hcompute_hw_input_global_wrapper_stencil_4[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } - // rng : { op_hcompute_hw_input_global_wrapper_stencil_4[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // cmap : { op_hcompute_hw_input_global_wrapper_stencil_3[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_4[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 3] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // read map: { hw_input_stencil_clkwrk_4[i0, i1, 3] -> op_hcompute_hw_input_global_wrapper_stencil_3[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } + // rng : { op_hcompute_hw_input_global_wrapper_stencil_3[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } // rng card: { 900 } for (int i = 0; i < 900; i++) { hw_uint<16 > value; @@ -76,9 +76,9 @@ int main() { hw_input_stencil_clkwrk_4.write(value); } - // cmap : { op_hcompute_hw_input_global_wrapper_stencil_5[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_5[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 5] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } - // read map: { hw_input_stencil_clkwrk_5[i0, i1, 5] -> op_hcompute_hw_input_global_wrapper_stencil_5[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } - // rng : { op_hcompute_hw_input_global_wrapper_stencil_5[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // cmap : { op_hcompute_hw_input_global_wrapper_stencil_2[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_5[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 2] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // read map: { hw_input_stencil_clkwrk_5[i0, i1, 2] -> op_hcompute_hw_input_global_wrapper_stencil_2[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } + // rng : { op_hcompute_hw_input_global_wrapper_stencil_2[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } // rng card: { 900 } for (int i = 0; i < 900; i++) { hw_uint<16 > value; @@ -86,9 +86,9 @@ int main() { hw_input_stencil_clkwrk_5.write(value); } - // cmap : { op_hcompute_hw_input_global_wrapper_stencil_6[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_6[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 6] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } - // read map: { hw_input_stencil_clkwrk_6[i0, i1, 6] -> op_hcompute_hw_input_global_wrapper_stencil_6[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } - // rng : { op_hcompute_hw_input_global_wrapper_stencil_6[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // cmap : { op_hcompute_hw_input_global_wrapper_stencil[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] -> hw_input_stencil_clkwrk_6[hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x, 0] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } + // read map: { hw_input_stencil_clkwrk_6[i0, i1, 0] -> op_hcompute_hw_input_global_wrapper_stencil[root = 0, hw_input_global_wrapper_s0_y = i0, hw_input_global_wrapper_s0_x = i1] : 0 <= i0 <= 29 and 0 <= i1 <= 29 } + // rng : { op_hcompute_hw_input_global_wrapper_stencil[root = 0, hw_input_global_wrapper_s0_y, hw_input_global_wrapper_s0_x] : 0 <= hw_input_global_wrapper_s0_y <= 29 and 0 <= hw_input_global_wrapper_s0_x <= 29 } // rng card: { 900 } for (int i = 0; i < 900; i++) { hw_uint<16 > value; @@ -131,13 +131,13 @@ int main() { dut.flush = 0; dut.clk = 0; dut.eval(); - *(dut.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read) = 0; - *(dut.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read) = 0; - *(dut.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read) = 0; - *(dut.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read) = 0; - *(dut.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read) = 0; - *(dut.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read) = 0; - *(dut.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read) = 0; + *(dut.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read) = 0; + *(dut.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read) = 0; + *(dut.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read) = 0; + *(dut.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read) = 0; + *(dut.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read) = 0; + *(dut.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read) = 0; + *(dut.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read) = 0; *(dut.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read) = 0; *(dut.hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read) = 0; int hw_output_stencil_clkwrk_10_op_hcompute_hw_output_stencil_2_write_valid_count = 0; @@ -152,33 +152,33 @@ int main() { dut.eval(); for (int t = 0; t < (int) pow(2, 16); t++) { cout << "t = " << t << endl; - if (dut.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en) { + if (dut.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en) { cout << "send me data!" << endl; - *(dut.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read) = (int) hw_input_stencil_clkwrk_0.read(); + *(dut.hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read) = (int) hw_input_stencil_clkwrk_0.read(); } - if (dut.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en) { + if (dut.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en) { cout << "send me data!" << endl; - *(dut.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read) = (int) hw_input_stencil_clkwrk_1.read(); + *(dut.hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read) = (int) hw_input_stencil_clkwrk_1.read(); } - if (dut.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en) { + if (dut.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en) { cout << "send me data!" << endl; - *(dut.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read) = (int) hw_input_stencil_clkwrk_2.read(); + *(dut.hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read) = (int) hw_input_stencil_clkwrk_2.read(); } - if (dut.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en) { + if (dut.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en) { cout << "send me data!" << endl; - *(dut.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read) = (int) hw_input_stencil_clkwrk_3.read(); + *(dut.hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read) = (int) hw_input_stencil_clkwrk_3.read(); } - if (dut.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en) { + if (dut.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en) { cout << "send me data!" << endl; - *(dut.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read) = (int) hw_input_stencil_clkwrk_4.read(); + *(dut.hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read) = (int) hw_input_stencil_clkwrk_4.read(); } - if (dut.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en) { + if (dut.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en) { cout << "send me data!" << endl; - *(dut.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read) = (int) hw_input_stencil_clkwrk_5.read(); + *(dut.hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read) = (int) hw_input_stencil_clkwrk_5.read(); } - if (dut.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en) { + if (dut.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en) { cout << "send me data!" << endl; - *(dut.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read) = (int) hw_input_stencil_clkwrk_6.read(); + *(dut.hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read) = (int) hw_input_stencil_clkwrk_6.read(); } if (dut.hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en) { cout << "send me data!" << endl; diff --git a/coreir_apps/platonic_buffer/resnet88/resnet88_vivado_verilog_tb.sv b/coreir_apps/platonic_buffer/resnet88/resnet88_vivado_verilog_tb.sv index e223c085b..db628b200 100644 --- a/coreir_apps/platonic_buffer/resnet88/resnet88_vivado_verilog_tb.sv +++ b/coreir_apps/platonic_buffer/resnet88/resnet88_vivado_verilog_tb.sv @@ -5,20 +5,20 @@ module resnet88_tb; logic flush; - logic hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en; - logic [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read [0 :0]; - logic hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en; - logic [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read [0 :0]; - logic hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en; - logic [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read [0 :0]; - logic hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en; - logic [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read [0 :0]; - logic hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en; - logic [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read [0 :0]; - logic hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en; - logic [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read [0 :0]; - logic hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en; - logic [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read [0 :0]; + logic hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en; + logic [15:0] hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read [0 :0]; + logic hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en; + logic [15:0] hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read [0 :0]; + logic hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en; + logic [15:0] hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read [0 :0]; + logic hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en; + logic [15:0] hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read [0 :0]; + logic hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en; + logic [15:0] hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read [0 :0]; + logic hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en; + logic [15:0] hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read [0 :0]; + logic hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en; + logic [15:0] hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read [0 :0]; logic hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en; logic [15:0] hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read [0 :0]; logic hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en; @@ -44,20 +44,20 @@ resnet88 dut( .clk(clk), .flush(flush), .rst_n(rst), - .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en), - .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read), - .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en), - .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read), - .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en), - .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read), - .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en), - .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read), - .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en), - .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read), - .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en), - .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read), - .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en), - .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read), + .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en), + .hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read(hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read), + .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en), + .hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read(hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read), + .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en), + .hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read(hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read), + .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en), + .hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read(hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read), + .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en), + .hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read(hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read), + .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en), + .hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read(hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read), + .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en), + .hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read(hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read), .hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en(hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en), .hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read(hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read), .hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en(hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read_en), @@ -83,13 +83,13 @@ resnet88 dut( clk = 0; rst = 0; flush = 0; - hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read[0] = 0; - hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] = 0; - hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] = 0; - hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] = 0; - hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] = 0; - hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] = 0; - hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] = 0; + hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] = 0; + hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] = 0; + hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] = 0; + hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] = 0; + hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] = 0; + hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] = 0; + hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read[0] = 0; hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read[0] = 0; hw_kernel_stencil_op_hcompute_hw_kernel_global_wrapper_stencil_read[0] = 0; end @@ -104,26 +104,26 @@ end always @(negedge clk) begin - if (hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read_en) begin - hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read[0] <= hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_read[0] + 1; + if (hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read_en) begin + hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] <= hw_input_stencil_clkwrk_0_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] + 1; end - if (hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read_en) begin - hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] <= hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] + 1; + if (hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read_en) begin + hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] <= hw_input_stencil_clkwrk_1_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] + 1; end - if (hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read_en) begin - hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] <= hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] + 1; + if (hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read_en) begin + hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] <= hw_input_stencil_clkwrk_2_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] + 1; end - if (hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read_en) begin - hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] <= hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] + 1; + if (hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read_en) begin + hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] <= hw_input_stencil_clkwrk_3_op_hcompute_hw_input_global_wrapper_stencil_1_read[0] + 1; end - if (hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read_en) begin - hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] <= hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_4_read[0] + 1; + if (hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read_en) begin + hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] <= hw_input_stencil_clkwrk_4_op_hcompute_hw_input_global_wrapper_stencil_3_read[0] + 1; end - if (hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read_en) begin - hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] <= hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_5_read[0] + 1; + if (hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read_en) begin + hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] <= hw_input_stencil_clkwrk_5_op_hcompute_hw_input_global_wrapper_stencil_2_read[0] + 1; end - if (hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read_en) begin - hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] <= hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_6_read[0] + 1; + if (hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read_en) begin + hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read[0] <= hw_input_stencil_clkwrk_6_op_hcompute_hw_input_global_wrapper_stencil_read[0] + 1; end if (hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read_en) begin hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read[0] <= hw_input_stencil_clkwrk_7_op_hcompute_hw_input_global_wrapper_stencil_7_read[0] + 1; diff --git a/coreir_backend.cpp b/coreir_backend.cpp index 195331d56..b86c6456c 100644 --- a/coreir_backend.cpp +++ b/coreir_backend.cpp @@ -1,9 +1,13 @@ #include "coreir_backend.h" #include "lake_target.h" +#include + #ifdef COREIR #include "cwlib.h" #include "cgralib.h" +#include "coreir/libs/float.h" +#include "coreir/libs/float_DW.h" #include "coreir/passes/analysis/coreirjson.h" @@ -573,20 +577,28 @@ bool all_constant_accesses(UBuffer& buf) { return true; } -pair build_buffer_impl(prog& prg, UBuffer& buf, schedule_info& hwinfo) { - EmbarrassingBankingImpl impl; +EmbarrassingBankingImpl build_buffer_impl(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo) { + UBufferImpl impl; dbhc::maybe > embarassing_banking = embarassing_partition(buf); bool has_embarassing_partition = embarassing_banking.has_value(); - assert(has_embarassing_partition); + if (has_embarassing_partition) { + if (embarassing_banking.get_value().size() == buf.logical_dimension()) { + cout << buf.name << " is really a register file" << endl; + } + auto emb_impl = static_cast(impl); - if (embarassing_banking.get_value().size() == buf.logical_dimension()) { - cout << buf.name << " is really a register file" << endl; + emb_impl.partition_dims = embarassing_banking.get_value(); + auto bank_map = build_buffer_impl_embarrassing_banking(buf, hwinfo, emb_impl); + return emb_impl; + } else { + cout << "Use exhaustive banking! " << endl; + buf.generate_banks_and_merge(options); + buf.parse_exhaustive_banking_into_impl(impl); + cout << "After exhaustive banking:\n " << impl << endl; + return static_cast(impl); + //cout << "CANNOT support by current banking strategies!" << endl; } - - impl.partition_dims = embarassing_banking.get_value(); - auto bank_map = build_buffer_impl_embarrassing_banking(buf, hwinfo, impl); - return {impl, bank_map}; } @@ -737,16 +749,17 @@ void generate_M3_coreir(CodegenOptions& options, CoreIR::ModuleDef* def, prog& p UBuffer buf = delete_ports(done_outpt, orig_buf); if (buf.num_out_ports() > 0) { - auto implm = build_buffer_impl(prg, buf, hwinfo); - auto impl = implm.first; + auto impl = build_buffer_impl(options, prg, buf, hwinfo); + //auto impl = implm.first; map, int> ubuffer_port_and_bank_to_bank_port = build_ubuffer_to_bank_binding(impl); - int num_banks = 1; - for (auto ent : impl.partitioned_dimension_extents) { - num_banks *= ent.second; - } + //int num_banks = 1; + //for (auto ent : impl.partitioned_dimension_extents) { + // num_banks *= ent.second; + //} + int num_banks = impl.get_bank_num(); M1_sanity_check_port_counts(impl); @@ -978,9 +991,9 @@ void load_mem_ext(Context* c) { {"config", Const::make(c, config)}}); //def->addInstance("c1","corebit.const",{{"value",Const::make(c,true)}}); //def->addInstance("c0","corebit.const",{{"value",Const::make(c,false)}}); - def->connect("self.rdata","cgramem.data_out_0"); - def->connect("self.ren","cgramem.ren_in_0"); - def->connect("self.raddr", "cgramem.addr_in_0"); + def->connect("self.rdata","cgramem." + lake_port_map.at("data_out_0")); + def->connect("self.ren","cgramem." + lake_port_map.at("ren_in_0")); + def->connect("self.raddr", "cgramem." + lake_port_map.at("addr_in_0")); }); } @@ -1030,33 +1043,6 @@ void load_commonlib_ext(Context* c) { def->connect("self.out","abs.data.out"); }); - Generator* mult_middle = c->getGenerator("commonlib.mult_middle"); - mult_middle->setGeneratorDefFromFun([](Context* c, Values args, ModuleDef* def) { - uint width = args.at("width")->get(); - ASSERT(width==DATAPATH_WIDTH,"NYI non 16"); - - Values PEArgs({ - {"alu_op",Const::make(c,"mult_1")}, - {"signed",Const::make(c,false)} - }); - def->addInstance("mult_1","cgralib.PE",{{"op_kind",Const::make(c,"alu")}},PEArgs); - def->connect("self.in0","mult_1.data.in.0"); - def->connect("self.in1","mult_1.data.in.1"); - def->connect("self.out","mult_1.data.out"); - }); - Generator* mult_high = c->getGenerator("commonlib.mult_high"); - mult_high->setGeneratorDefFromFun([](Context* c, Values args, ModuleDef* def) { - uint width = args.at("width")->get(); - ASSERT(width==DATAPATH_WIDTH,"NYI non 16"); - Values PEArgs({ - {"alu_op",Const::make(c,"mult_2")}, - {"signed",Const::make(c,false)} - }); - def->addInstance("mult_2","cgralib.PE",{{"op_kind",Const::make(c,"alu")}},PEArgs); - def->connect("self.in0","mult_2.data.in.0"); - def->connect("self.in1","mult_2.data.in.1"); - def->connect("self.out","mult_2.data.out"); - }); } @@ -1541,8 +1527,8 @@ void generate_coreir_compute_unit(CodegenOptions& options, bool found_compute, if (found_compute) { cout << "Found compute file for " << prg.name << endl; Instance* halide_cu = nullptr; - if (hwinfo.use_dse_compute) { - halide_cu = def->addInstance("inner_compute", ns->getModule(op->func + "_mapped")); + if (hwinfo.use_metamapper) { + halide_cu = def->addInstance("inner_compute", ns->getModule(op->func)); } else { if (options.rtl_options.use_pipelined_compute_units) { halide_cu = def->addInstance("inner_compute", ns->getModule(op->func + "_pipelined")); @@ -1612,7 +1598,7 @@ void generate_coreir_compute_unit(CodegenOptions& options, bool found_compute, } assert(found); } - + inlineInstance(halide_cu); } else { // Generate dummy compute logic cout << "generating dummy compute" << endl; @@ -1671,6 +1657,18 @@ Wireable* write_start_wire(ModuleDef* def, const std::string& opname) { return def->sel(write_start_name(opname))->sel("out"); } +CoreIR::Wireable* op_control_wires(Instance* ctrl) { + string mode = ctrl->getMetaData()["mode"]; + if (mode == "lake") { + return ctrl->sel("stencil_valid"); + } else if (mode == "lake_dp") { + return ctrl->sel("valid_out_pond"); + } else { + cout << "Config mode: " << mode << "Not implemented" << endl; + assert(false); + } +} + void connect_op_control_wires(CodegenOptions& options, ModuleDef* def, op* op, schedule_info& hwinfo, Instance* controller) { cout << "Find compute" << endl; //int op_latency = dbhc::map_find(op->name, hwinfo.op_compute_unit_latencies); @@ -1708,7 +1706,8 @@ void connect_op_control_wires(CodegenOptions& options, ModuleDef* def, op* op, s Wireable* write_start_loop_vars = delay_by(def, write_start_control_vars_name(op->name), op_start_loop_vars, read_latency + op_latency); } else { - Wireable* op_start_wire = controller->sel("stencil_valid"); + //Wireable* op_start_wire = controller->sel("stencil_valid"); + Wireable* op_start_wire = op_control_wires(controller); cout << "Delaying read" << endl; Wireable* read_start_wire = delay_by(def, read_start_name(op->name), op_start_wire, 0); @@ -1797,25 +1796,51 @@ void emit_lake_config_collateral(CodegenOptions options, string tile_name, json out.close(); } } +void add_init_code(ofstream& lake_new, string keyword) { + if (contains(keyword, "sp")) { + lake_new << "//Add initial block here" << endl; + lake_new << "initial begin" << endl; + lake_new << tab(1) << "integer i = 0;" << endl; + lake_new << tab(1) << "for(i = 0; i < 512; i ++) begin" << endl; + lake_new << tab(2) << "integer big_addr = i >> 2;" << endl; + lake_new << tab(2) << "integer small_addr = (i & 3) << 4;" << endl; + //lake_new << tab(2) << "data_array[big_addr][small_addr] = i;" << endl; + lake_new << tab(2) << "data_array[big_addr][small_addr +: 8] = i;" << endl; + lake_new << tab(1) << "end" << endl << "end" << endl; + } else { + lake_new << "//Add initial block here" << endl; + lake_new << "initial begin" << endl; + lake_new << tab(1) << "integer i = 0;" << endl; + lake_new << tab(1) << "for(i = 0; i < 512; i ++) begin" << endl; + //lake_new << tab(2) << "data_array[big_addr][small_addr] = i;" << endl; + lake_new << tab(2) << "data_array[i] = i;" << endl; + lake_new << tab(1) << "end" << endl << "end" << endl; + } +} -void add_default_initial_block() { - ifstream lake_top("LakeTop_W.v"); - ofstream lake_new("LakeTop_W_new.v"); +void add_default_initial_block(string filename, string keyword) { + //ifstream lake_top("LakeTop_W.v"); + //ofstream lake_new("LakeTop_W_new.v"); + ifstream lake_top(filename + ".sv"); + ofstream lake_new(filename + "_new.sv"); string loc; + bool find_macro = false; if (lake_top.is_open() && lake_new.is_open()) { - while(getline(lake_top, loc)) { - if (loc == "endmodule // sram_stub") { - lake_new << "//Add initial block here" << endl; - lake_new << "initial begin" << endl; - lake_new << tab(1) << "integer i = 0;" << endl; - lake_new << tab(1) << "for(i = 0; i < 512; i ++) begin" << endl; - lake_new << tab(2) << "integer big_addr = i >> 2;" << endl; - lake_new << tab(2) << "integer small_addr = i & 3;" << endl; - lake_new << tab(2) << "data_array[big_addr][small_addr] = i;" << endl; - lake_new << tab(1) << "end" << endl << "end" << endl; + while(getline(lake_top, loc) ) { + //if (loc == "endmodule // sram_stub") { + //TODO: this is a little hacky, we need to find a better way to init + //if (loc == "endmodule // sram_sp__0") { + if (loc == keyword) { + find_macro = true; + add_init_code(lake_new, keyword); } lake_new << loc << endl; } + if (!find_macro) { + cout << "Cannot find sram macro in the generated laketop.sv" << endl; + assert(false); + } + lake_top.close(); lake_new.close(); } else { @@ -1829,29 +1854,49 @@ void run_lake_verilog_codegen(CodegenOptions& options, string v_name, string ub_ //cout << "Runing cmd$ python /nobackup/joeyliu/aha/lake/tests/wrapper_lake.py -c " + options.dir + "lake_collateral/" + ub_ins_name + " -s True -n " + v_name << endl; ASSERT(getenv("LAKE_PATH"), "Define env var $LAKE_PATH which is the /PathTo/lake"); cmd("echo $LAKE_PATH"); - if (options.mem_hierarchy.at("mem").fetch_width == 4) { - int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper_lake.py -c " + options.dir + "lake_collateral/" + ub_ins_name + " -s True -n " + v_name); - assert(res_lake == 0); - } else { - int res_lake = cmd("python $LAKE_PATH/tests/test_pohan_wrapper.py -f " + options.dir + "lake_collateral/" + ub_ins_name + "/config.json -b LakeWrapper -w " + v_name); - assert(res_lake == 0); - } - cmd("mkdir -p "+options.dir+"verilog"); - cmd("mv LakeWrapper_"+v_name+".v " + options.dir + "verilog"); + //if (options.mem_hierarchy.at("mem").fetch_width == 4) { + // int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper_lake.py -c " + options.dir + "lake_collateral/" + ub_ins_name + " -s True -n " + v_name); + // assert(res_lake == 0); + //} else { + // int res_lake = cmd("python $LAKE_PATH/tests/test_pohan_wrapper.py -f " + options.dir + "lake_collateral/" + ub_ins_name + "/config.json -b LakeWrapper -w " + v_name); + // assert(res_lake == 0); + //} + //cmd("mkdir -p "+options.dir+"verilog"); + //cmd("mv LakeWrapper_"+v_name+".v " + options.dir + "verilog"); + + int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper.py -c " + options.dir + "lake_collateral/" + ub_ins_name + + "/config.json -s -wmn "+ v_name + " -wfn lake_module_wrappers.v -a -v -d 512"); + assert(res_lake == 0); + + +} + +void run_lake_dp_verilog_codegen(CodegenOptions& options, string v_name, string ub_ins_name) { + //cmd("export LAKE_CONTROLLERS=$PWD"); + ASSERT(getenv("LAKE_PATH"), "Define env var $LAKE_PATH which is the /PathTo/lake"); + //int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper_lake.py -c " + options.dir + "lake_collateral/" + ub_ins_name + " -n " + v_name + " -p True -pl 4 -pd 128"); + int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper.py -c " + options.dir + "lake_collateral/" + ub_ins_name + + "/config.json -s -wmn "+ v_name + " -wfn pond_module_wrappers.v -vmn PondTop -vfn pondtop.sv -a -v -dp -ii 6 -oi 6 -rd 0 -d 2048 -mw 16"); + assert(res_lake == 0); + //cmd("mkdir -p "+options.dir+"verilog"); + //cmd("mv LakeWrapper_"+v_name+".v " + options.dir + "verilog"); } void run_pond_verilog_codegen(CodegenOptions& options, string v_name, string ub_ins_name) { //cmd("export LAKE_CONTROLLERS=$PWD"); ASSERT(getenv("LAKE_PATH"), "Define env var $LAKE_PATH which is the /PathTo/lake"); - int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper_lake.py -c " + options.dir + "lake_collateral/" + ub_ins_name + " -n " + v_name + " -p True -pl 4 -pd 128"); + //int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper_lake.py -c " + options.dir + "lake_collateral/" + ub_ins_name + " -n " + v_name + " -p True -pl 4 -pd 128"); + int res_lake = cmd("python $LAKE_PATH/lake/utils/wrapper.py -c " + options.dir + "lake_collateral/" + ub_ins_name + + "/config.json -s -wmn "+ v_name + " -wfn pond_module_wrappers.v -vmn PondTop -vfn pondtop.sv -a -v -dp -ii 4 -oi 4 -rd 0 -d 128 -mw 16"); assert(res_lake == 0); - cmd("mkdir -p "+options.dir+"verilog"); - cmd("mv LakeWrapper_"+v_name+".v " + options.dir + "verilog"); + //cmd("mkdir -p "+options.dir+"verilog"); + //cmd("mv LakeWrapper_"+v_name+".v " + options.dir + "verilog"); } void run_glb_verilog_codegen(CodegenOptions& options, const std::string& long_name, int num_inpt, int num_outpt, int width) { std::ofstream verilog_collateral_file; - verilog_collateral_file.open(long_name + ".v"); + //verilog_collateral_file.open(long_name + ".v"); + verilog_collateral_file.open("lake_module_wrappers.v", std::ios_base::app); vector port_decls = {}; port_decls.push_back("input clk"); @@ -1908,8 +1953,8 @@ void run_glb_verilog_codegen(CodegenOptions& options, const std::string& long_na } verilog_collateral_file << "endmodule" << endl << endl; verilog_collateral_file.close(); - cmd("mkdir -p "+options.dir+"verilog"); - cmd("mv " + long_name+".v " + options.dir + "verilog"); + //cmd("mkdir -p "+options.dir+"verilog_glb"); + //cmd("mv " + long_name+".v " + options.dir + "verilog"); } void generate_lake_tile_verilog(CodegenOptions& options, Instance* buf) { @@ -1918,9 +1963,9 @@ void generate_lake_tile_verilog(CodegenOptions& options, Instance* buf) { string ub_ins_name = buf->toString(); string config_mode = buf->getMetaData()["mode"]; //FIXME: a hack to get correct module name, fix this after coreIR update - //string v_name = get_coreir_genenerator_name(buf->getModuleRef()->toString()); + string v_name = get_coreir_genenerator_name(buf->getModuleRef()->toString()); //string v_name = buf->getModuleRef()->getMetaData()["verilog_name"]; - string v_name = buf->getMetaData()["verilog_name"]; + //string v_name = buf->getMetaData()["verilog_name"]; if (options.config_gen_only) return; //TODO: apply the verilog codegen here @@ -1937,9 +1982,12 @@ void generate_lake_tile_verilog(CodegenOptions& options, Instance* buf) { //run the lake generation cmd if (config_mode == "lake") run_lake_verilog_codegen(options, v_name, ub_ins_name); + else if (config_mode == "lake_dp") + run_lake_dp_verilog_codegen(options, v_name, ub_ins_name); else if (config_mode == "pond") run_pond_verilog_codegen(options, v_name, ub_ins_name); else { + cout << "Config mode: " << config_mode << endl; cout << "Not implemented yet. " << endl; assert(false); } @@ -2253,7 +2301,7 @@ bool load_compute_file(CodegenOptions& options, } else { compute_file = "./coreir_compute/" + prg.name + "_compute.json"; } - if (hwinfo.use_dse_compute) { + if (hwinfo.use_metamapper) { compute_file = "./dse_compute/" + prg.name + "_mapped.json"; } assert(compute_file != ""); @@ -2264,7 +2312,7 @@ bool load_compute_file(CodegenOptions& options, if (!loadFromFile(context, compute_file)) { found_compute = false; cout << "Could not load compute file for: " << prg.name << ", file name = " << compute_file << endl; - if (hwinfo.use_dse_compute) { + if (hwinfo.use_metamapper) { assert(false); } } @@ -2277,7 +2325,8 @@ CoreIR::Module* generate_coreir_without_ctrl(CodegenOptions& options, prog& prg, umap* schedmap, CoreIR::Context* context, - schedule_info& hwinfo) { + schedule_info& hwinfo, + string dse_compute_filename) { Module* ub = coreir_moduledef(options, buffers, prg, schedmap, context, hwinfo); @@ -2287,9 +2336,8 @@ CoreIR::Module* generate_coreir_without_ctrl(CodegenOptions& options, #else string compute_file = "./" + prg.name + "_compute.json"; #endif - if (hwinfo.use_dse_compute) { - compute_file = "./dse_compute/" + prg.name + "_mapped.json"; - //compute_file = "./dse_apps/" + prg.name + ".json"; + if (hwinfo.use_metamapper) { + compute_file = dse_compute_filename; } ifstream cfile(compute_file); if (!cfile.good()) { @@ -2299,7 +2347,7 @@ CoreIR::Module* generate_coreir_without_ctrl(CodegenOptions& options, if (!loadFromFile(context, compute_file)) { found_compute = false; cout << "Could not load compute file for: " << prg.name << ", file name = " << compute_file << endl; - if (hwinfo.use_dse_compute) { + if (hwinfo.use_metamapper) { assert(false); } } @@ -2351,6 +2399,10 @@ CoreIR::Module* generate_coreir_without_ctrl(CodegenOptions& options, //all the memory optimization pass goes here auto impl = generate_optimized_memory_implementation(options, buf.second, prg, hwinfo); + lower_to_garnet_implementation(options, buf.second, impl, hwinfo); + + impl.bank_merging_and_rewrite(options); + //Generate the memory module auto ub_mod = generate_coreir_without_ctrl(options, context, buf.second, impl, hwinfo); def->addInstance(buf.second.name, ub_mod); @@ -2736,7 +2788,7 @@ class GetGLBConfig: public CoreIR::InstanceGraphPass { //There are more than one input GLB map glb2cgra; - json cgra2glb; + map cgra2glb; GetGLBConfig() : latency(0), InstanceGraphPass("getglbconfig", "Find the glb load latency!") {} bool runOnInstanceGraphNode(CoreIR::InstanceGraphNode& node) { @@ -2750,19 +2802,20 @@ class GetGLBConfig: public CoreIR::InstanceGraphPass { if(!genargs.at("has_external_addrgen")->get()) continue; string buf_name = genargs.at("ID")->get(); + cout << "ID buf name: " << buf_name << endl; buf_name = pick(split_at(buf_name, "_")); auto config_file = inst->getMetaData()["config"]; cout << "Buf_name: " << buf_name << endl; cout << "Config file: " << config_file << endl; - if(config_file.count("in2glb_0") && config_file.count("glb2out_0")) { - if (config_file.at("in2glb_0").at("cycle_starting_addr")[0] == 0) { - latency = config_file.at("glb2out_0").at("cycle_starting_addr")[0]; - glb2cgra.insert({buf_name, config_file.at("glb2out_0")}); - } else { - cgra2glb = config_file.at("in2glb_0"); - //cgra2glb.insert({buf_name, config_file.at("in2glb_0")}); - } - } + int write_to_glb = config_file.at("in2glb_0").at("cycle_starting_addr")[0]; + int read_from_glb = config_file.at("glb2out_0").at("cycle_starting_addr")[0]; + if(write_to_glb == 0) { + latency = std::max(latency, (int)config_file.at("glb2out_0").at("cycle_starting_addr")[0]); + glb2cgra.insert({buf_name, config_file.at("glb2out_0")}); + } else { + cgra2glb.insert({buf_name, config_file.at("in2glb_0")}); + //cgra2glb.insert({buf_name, config_file.at("in2glb_0")}); + } } } } @@ -2770,7 +2823,6 @@ class GetGLBConfig: public CoreIR::InstanceGraphPass { } }; - void addIOsWithGLBConfig(Context* c, Module* top, map& buffers, GetGLBConfig* glb_metadata) { ModuleDef* mdef = top->getDef(); @@ -2789,7 +2841,7 @@ void addIOsWithGLBConfig(Context* c, Module* top, map& buffers, //Add the multi-tile glb informations if(glb_metadata->latency != 0) { - cout << "buf name: " << buf_name << endl; + cout << "INPUT GLB buf name: " << buf_name << endl; string key = pick(split_at(buf_name, "_")); inst->getMetaData()["glb2out_0"] = glb_metadata->glb2cgra.at(key); int old_offset = inst->getMetaData()["glb2out_0"]["cycle_starting_addr"][0] ; @@ -2811,10 +2863,10 @@ void addIOsWithGLBConfig(Context* c, Module* top, map& buffers, //Add the multi-tile glb informations if(glb_metadata->latency != 0) { - cout << "buf_name" << buf_name << endl; - //string key = split_at(buf_name, "_").at(1); - //inst->getMetaData()["in2glb_0"] = glb_metadata->cgra2glb.at(key); - inst->getMetaData()["in2glb_0"] = glb_metadata->cgra2glb; + cout << "OUTPUT GLB buf_name: " << buf_name << endl; + string key = (split_at(buf_name, "_")).at(1); + inst->getMetaData()["in2glb_0"] = glb_metadata->cgra2glb.at(key); + //inst->getMetaData()["in2glb_0"] = glb_metadata->cgra2glb; int old_offset = inst->getMetaData()["in2glb_0"]["cycle_starting_addr"][0] ; inst->getMetaData()["in2glb_0"]["cycle_starting_addr"][0] = old_offset - glb_metadata->latency; } @@ -2840,6 +2892,91 @@ void addIOsWithGLBConfig(Context* c, Module* top, map& buffers, inlineInstance(pt); } +void addIOsWithGLBConfigMetaMapper(Context* c, Module* top, map& buffers, GetGLBConfig* glb_metadata) { + ModuleDef* mdef = top->getDef(); + vector loaded; + if (!loadHeader(c, "io_header.json", loaded)) {c->die();} + vector loaded_bit; + if (!loadHeader(c, "bit_io_header.json", loaded_bit)) {c->die();} + Values aWidth({{"width",Const::make(c,16)}}); + IOpaths iopaths; + getAllIOPaths(mdef->getInterface(), iopaths); + Instance* pt = addPassthrough(mdef->getInterface(),"_self"); + mdef->disconnect(mdef->getInterface()); + for (auto path : iopaths.IO16) { + string path_name = *(path.begin()+1); + //TODO: this is a hacky way to parse the buf name + string buf_name = take_until_str(path_name, "_op"); + auto in_buf = buffers.at(buf_name); + string ioname = "io16in_" + join(++path.begin(),path.end(),string("_")); + + auto inst = mdef->addInstance(ioname,(Module*)loaded[0],{{"mode",Const::make(c,"in")}}); + + + inst->getMetaData() = in_buf.config_file; + + //Add the multi-tile glb informations + if(glb_metadata->latency != 0) { + cout << "INPUT GLB buf name: " << buf_name << endl; + string key = pick(split_at(buf_name, "_")); + inst->getMetaData()["glb2out_0"] = glb_metadata->glb2cgra.at(key); + int old_offset = inst->getMetaData()["glb2out_0"]["cycle_starting_addr"][0] ; + inst->getMetaData()["glb2out_0"]["cycle_starting_addr"][0] = old_offset - glb_metadata->latency; + } + + mdef->connect(path, {ioname,"in"}); + + path[0] = "in"; + path.insert(path.begin(),"_self"); + mdef->connect({ioname,"out"},path); + } + for (auto path : iopaths.IO16in) { + string path_name = *(path.begin()+1); + //TODO: this is a hacky way to parse the buf name + string buf_name = take_until_str(path_name, "_op"); + auto out_buf = buffers.at(buf_name); + string ioname = "io16_" + join(++path.begin(),path.end(),string("_")); + + auto inst = mdef->addInstance(ioname,(Module*)loaded[0],{{"mode",Const::make(c,"out")}}); + + inst->getMetaData() = out_buf.config_file; + + //Add the multi-tile glb informations + if(glb_metadata->latency != 0) { + cout << "OUTPUT GLB buf_name: " << buf_name << endl; + string key = (split_at(buf_name, "_")).at(1); + inst->getMetaData()["in2glb_0"] = glb_metadata->cgra2glb.at(key); + //inst->getMetaData()["in2glb_0"] = glb_metadata->cgra2glb; + int old_offset = inst->getMetaData()["in2glb_0"]["cycle_starting_addr"][0] ; + inst->getMetaData()["in2glb_0"]["cycle_starting_addr"][0] = old_offset - glb_metadata->latency; + } + + mdef->connect(path, {ioname,"out"}); + path[0] = "in"; + path.insert(path.begin(),"_self"); + mdef->connect({ioname,"in"},path); + } + for (auto path : iopaths.IO1) { + string ioname = "io1in_" + join(++path.begin(),path.end(),string("_")); + + mdef->addInstance(ioname,(Module*)loaded_bit[0],{{"mode",Const::make(c,"in")}}); + mdef->connect(path, {ioname,"in"}); + path[0] = "in"; + path.insert(path.begin(),"_self"); + mdef->connect({ioname,"out"},path); + } + for (auto path : iopaths.IO1in) { + string ioname = "io1_" + join(++path.begin(),path.end(),string("_")); + + mdef->addInstance(ioname,(Module*)loaded_bit[0],{{"mode",Const::make(c,"out")}}); + mdef->connect(path, {ioname,"out"}); + path[0] = "in"; + path.insert(path.begin(),"_self"); + mdef->connect({ioname,"in"},path); + } + inlineInstance(pt); +} + void addIOs(Context* c, Module* top) { ModuleDef* mdef = top->getDef(); @@ -2881,7 +3018,6 @@ void addIOs(Context* c, Module* top) { } mdef->disconnect(mdef->getInterface()); inlineInstance(pt); - assert(false); } @@ -2893,20 +3029,15 @@ class CustomFlatten : public CoreIR::InstanceGraphPass { bool changed = false; // int i = 0; for (auto inst : node.getInstanceList()) { - cout << "inlining " << inst->toString() << endl; Module* m = inst->getModuleRef(); if (m->isGenerated()) { auto g = m->getGenerator(); - if (g->getName() == "raw_dual_port_sram_tile" || - g->getName() == "raw_quad_port_memtile" || - g->getName() == "rom2") { - continue; - } - } else { - if (m->getName() == "WrappedPE_wrapped") { + if (g->getName() == "rom2") { + cout << "not inlining " << inst->toString() << " " << inst->toString() << endl; continue; } } +cout << "inlining " << inst->toString() << endl; changed |= inlineInstance(inst); } return changed; @@ -2951,6 +3082,30 @@ class SubstructGLBLatency: public CoreIR::InstanceGraphPass { } }; +class RemoveFlush: public CoreIR::InstancePass { + public: +RemoveFlush(): InstancePass( + "removeflush", + "Remove flush wiring for garnet mapping" + ) {} +bool runOnInstance(Instance* inst) { + //define the pass here + if (inst->getModuleRef()->isGenerated()) { + if (inst->getModuleRef()->getGenerator()->getName() == "Mem_amber" && + inst->canSel("flush")) { + auto def= inst->getContainer(); + def->disconnect(inst->sel("flush")); + return true; + } else { + return false; + } + } else { + return false; + } +} + +}; + class ReplaceGLBValid: public CoreIR::InstancePass { public: json valid_config; @@ -2964,14 +3119,17 @@ bool runOnInstance(Instance* inst) { //define the pass here if(latency == 0) return false; + //string sv_name = lake_port_map.at("stencil_valid"); + string sv_name = "stencil_valid"; if (inst->getModuleRef()->isGenerated()) if (inst->getModuleRef()->getGenerator()->getName() == "Mem_amber" && - inst->canSel("stencil_valid")) { - auto conns = inst->sel("stencil_valid")->getConnectedWireables(); + inst->canSel(sv_name)) { + auto conns = inst->sel(sv_name)->getConnectedWireables(); bool connect2IO = false; for (auto conn: conns) { auto inst_conn = dyn_cast(conn->getTopParent()); - if (inst_conn->getModuleRef()->getRefName() == "cgralib.BitIO") { + if (inst_conn->getModuleRef()->getRefName() == "global.BitIO") { + cout << "found cgpl in subtract" << endl; cout << inst_conn->getModuleRef()->toString() << endl; connect2IO = true; break; @@ -2979,7 +3137,8 @@ bool runOnInstance(Instance* inst) { } if (connect2IO) { //valid_config.at("cycle_starting_addr")[0] = (int)valid_config.at("cycle_starting_addr")[0] - latency; - inst->getMetaData()["config"]["stencil_valid"] = valid_config; + //TODO: This is a hack, need to make sure the output always called hw_output + inst->getMetaData()["config"][sv_name] = valid_config.at("output"); return true; } } @@ -3306,9 +3465,12 @@ bool InitMove(Instance* cnst) { //auto pt = addPassthrough(cnst, cnst->getInstname()+"_tmp"); Instance* buf = def->addInstance(cnst->getInstname()+"_rom", "cgralib.Mem", genargs, modargs); - reconnectInWire(def, cnst->sel("raddr"), buf->sel("addr_in_0")); - reconnectInWire(def, cnst->sel("ren"), buf->sel("ren_in_0")); - reconnectOutWire(def, cnst->sel("rdata"), buf->sel("data_out_0")); + reconnectInWire(def, cnst->sel("raddr"), + buf->sel(lake_port_map.at("addr_in_0"))); + reconnectInWire(def, cnst->sel("ren"), + buf->sel(lake_port_map.at("ren_in_0"))); + reconnectOutWire(def, cnst->sel("rdata"), + buf->sel(lake_port_map.at("data_out_0"))); def->removeInstance(cnst); //def->connect(pt->sel("in"), buf); //inlineInstance(pt); @@ -3398,7 +3560,19 @@ bool MemtileReplace(Instance* cnst) { Instance* buf = def->addInstance(cnst->getInstname()+"_garnet", "cgralib.Mem", genargs, modargs); def->removeInstance(cnst); - def->connect(pt->sel("in"), buf); + //def->connect(pt->sel("in"), buf); + auto buf_sel = buf->getSelects(); + for (auto itr: allSels) { + cout << tab(2) << "garnet buf sel: " << itr.first << endl; + string premap_pt_name = itr.first; + if (lake_port_map.count(premap_pt_name)) + def->connect(pt->sel("in")->sel(premap_pt_name), + buf->sel(lake_port_map.at(premap_pt_name))); + else + def->connect(pt->sel("in")->sel(premap_pt_name), + buf->sel(premap_pt_name)); + } + inlineInstance(pt); inlineInstance(buf); @@ -3484,116 +3658,637 @@ void MapperPasses::RegfileSubstitute::setVisitorInfo() { } + namespace MapperPasses { -class ConstDuplication : public CoreIR::InstanceVisitorPass { +class MemSubstituteMetaMapper: public CoreIR::InstanceVisitorPass { public : static std::string ID; - ConstDuplication() : InstanceVisitorPass(ID,"duplicate all constants") {} + MemSubstituteMetaMapper() : InstanceVisitorPass(ID,"replace cgralib.Mem_amber to new coreir header mem") {} void setVisitorInfo() override; }; } -bool ConstDup(Instance* cnst) { - Module* modRef = cnst->getModuleRef(); - auto connSet = cnst->sel("out")->getConnectedWireables(); - if (connSet.size() < 1) { - return false; - } - vector conns(connSet.begin(),connSet.end()); +bool MemtileReplaceMetaMapper(Instance* cnst) { + cout << tab(2) << "new memory syntax transformation!" << endl; + cout << tab(2) << toString(cnst) << endl; + Context* c = cnst->getContext(); + auto allSels = cnst->getSelects(); + for (auto itr: allSels) { + cout << tab(2) << "Sel: " << itr.first << endl; + } ModuleDef* def = cnst->getContainer(); - for (uint i=1; i< conns.size(); ++i) { - Wireable* conn = conns[i]; - cout << "replacing connection to : " << conn->toString() << endl; - Instance* newconst = def->addInstance(cnst->getInstname() + to_string(i),modRef,cnst->getModArgs()); - def->connect(newconst->sel("out"),conn); - def->disconnect(cnst->sel("out"),conn); + auto genargs = cnst->getModuleRef()->getGenArgs(); + + string ID = genargs.at("ID")->get(); + bool has_external_addrgen = genargs.at("has_external_addrgen")->get(); + bool has_flush = genargs.at("has_flush")->get(); + bool has_read_valid = genargs.at("has_read_valid")->get(); + bool has_reset = genargs.at("has_reset")->get(); + bool has_stencil_valid = genargs.at("has_stencil_valid")->get(); + bool has_valid = genargs.at("has_valid")->get(); + bool is_rom = genargs.at("is_rom")->get(); + bool use_prebuilt_mem = genargs.at("use_prebuilt_mem")->get(); + int num_inputs = genargs.at("num_inputs")->get(); + int num_outputs = genargs.at("num_outputs")->get(); + int width = genargs.at("width")->get(); + + auto config_file = cnst->getMetaData(); + + config_file["ID"] = ID; + config_file["has_external_addrgen"] = has_external_addrgen; + config_file["has_flush"] = has_flush; + config_file["has_read_valid"] = has_read_valid; + config_file["has_reset"] = has_reset; + config_file["has_stencil_valid"] = has_stencil_valid; + config_file["has_valid"] = has_valid; + config_file["is_rom"] = is_rom; + config_file["use_prebuilt_mem"] = use_prebuilt_mem; + config_file["num_inputs"] = num_inputs; + config_file["num_outputs"] = num_outputs; + config_file["width"] = width; + + + + std::set routable_ports = {"chain_data_in_0","chain_data_in_1", "flush", "ren_in", "wen_in", "addr_in_0", "addr_in_1", "data_in_0", "data_in_1"}; + + std::vector routable_outputs = {"data_out_1", "empty", "stencil_valid", "full", "data_out_0", "sram_ready_out", "valid_out", "config_data_out_1", "config_data_out_0"}; + + std::vector routable_renamed_outputs = {"output_width_16_num_0", "output_width_16_num_1", "output_width_1_num_1", "output_width_1_num_2", "output_width_1_num_3", "config_data_out_0", "config_data_out_1", "output_width_1_num_0"}; + + vector loaded; + if (!loadHeader(c, "mem_header.json", loaded)) {c->die();} + + Instance* buf = def->addInstance(cnst->getInstname()+"_garnet", (Module*)loaded[0]); + + buf->setMetaData(config_file); + + Module* cnst_mod_ref = cnst->getModuleRef(); + auto pt = addPassthrough(cnst, cnst->getInstname()+"_tmp"); + + vector cnst_ports = cnst_mod_ref->getType()->getFields(); + + string map_name = ""; + + for (auto cnst_port : cnst_ports) { + if (lake_port_map.count(cnst_port)) { + if (routable_ports.count(cnst_port) > 0) { + cout << "Connecting cnst_port: " << cnst_port << endl; + def->connect(pt->sel("in")->sel(cnst_port), buf->sel(lake_port_map.at(cnst_port))); + } else { + map_name = lake_port_map.at(cnst_port); + auto index = find(routable_renamed_outputs.begin(), routable_renamed_outputs.end(), map_name); + if (index != routable_renamed_outputs.end()){ + int port_index = index - routable_renamed_outputs.begin(); + cout << "Connecting output cnst_port: " << cnst_port << " to " << "O" << std::to_string(port_index) << endl; + def->connect(buf->sel("O" + std::to_string(port_index)), pt->sel("in")->sel(cnst_port)); + } else { + cout << "Not Connecting cnst_port: " << cnst_port << endl; + } + } + } else { + if (routable_ports.count(cnst_port) > 0) { + cout << "Connecting cnst_port: " << cnst_port << endl; + def->connect(pt->sel("in")->sel(cnst_port), buf->sel(cnst_port)); + } + } } + + def->removeInstance(cnst); + inlineInstance(pt); + inlineInstance(buf); return true; } -std::string MapperPasses::ConstDuplication::ID = "constduplication"; -void MapperPasses::ConstDuplication::setVisitorInfo() { + +std::string MapperPasses::MemSubstituteMetaMapper::ID = "memsubstitutemetamapper"; +void MapperPasses::MemSubstituteMetaMapper::setVisitorInfo() { Context* c = this->getContext(); - if (c->hasModule("corebit.const")) { - addVisitorFunction(c->getModule("corebit.const"),ConstDup); - } - if (c->hasGenerator("coreir.const")) { - addVisitorFunction(c->getGenerator("coreir.const"),ConstDup); + if (c->hasGenerator("cgralib.Mem_amber")) { + addVisitorFunction(c->getGenerator("cgralib.Mem_amber"), MemtileReplaceMetaMapper); } } -void disconnect_input_enable(Context* c, Module* top) { - ModuleDef* def = top->getDef(); - for (auto it: def->sel("self")->getSelects()) { - string port = it.first; - cout << "Find top interface: " << port << endl; - if (contains(port, "read_en")) { - auto conns = def->sel("self")->sel(port)->getConnectedWireables(); - for (auto conn: conns) { - def->disconnect(def->sel("self")->sel(port), conn); - } - } - } -} -void garnet_map_module(Module* top, bool garnet_syntax_trans = false) { - auto c = top->getContext(); +namespace MapperPasses { +class PondSubstituteMetaMapper: public CoreIR::InstancePass { + public : + Module* topm; + //static std::string ID; - top->print(); + PondSubstituteMetaMapper(Module* top) : InstancePass("pondsubstitutemetamapper", "add global.pond schedules") {topm = top;} + //void setVisitorInfo() override; - //load_cgramapping(c); - LoadDefinition_cgralib(c); - c->runPasses({"rungenerators"}); - //A new pass to remove input enable signal affine controller - disconnect_input_enable(c, top); - c->runPasses({"deletedeadinstances"}); +bool runOnInstance(Instance* cnst) { - c->runPasses({"cullgraph"}); - c->runPasses({"removewires"}); - addIOs(c,top); - c->runPasses({"cullgraph"}); - c->addPass(new CustomFlatten); - c->runPasses({"customflatten"}); - if (garnet_syntax_trans) { - c->addPass(new MapperPasses::MemInitCopy); - c->runPasses({"meminitcopy"}); - c->addPass(new MapperPasses::MemSubstitute); - c->runPasses({"memsubstitute"}); - c->addPass(new MapperPasses::RegfileSubstitute); - c->runPasses({"regfilesubstitute"}); +if (cnst->getModuleRef()->getName() == "Pond") { + + cout << tab(2) << "pond syntax transformation!" << endl; + cout << tab(2) << toString(cnst) << endl; + Context* c = cnst->getContext(); + + + auto allSels = cnst->getSelects(); + for (auto itr: allSels) { + cout << tab(2) << "Sel: " << itr.first << endl; } - c->addPass(new MapperPasses::ConstDuplication); - c->runPasses({"constduplication"}); - c->addPass(new MapperPasses::MemConst); - c->runPasses({"memconst"}); - c->runPasses({"cullgraph"}); - c->getPassManager()->printLog(); - cout << "Trying to save" << endl; - c->runPasses({"coreirjson"},{"global","commonlib","mantle"}); - c->runPasses({"removewires"}); - auto jpass = static_cast(c->getPassManager()->getAnalysisPass("coreirjson")); - string postmap = "after_mapping_" + top->getName() + ".json"; - ////Create file here. - std::ofstream file(postmap); - jpass->writeToStream(file,top->getRefName()); -} + ModuleDef* def = cnst->getContainer(); + //auto genargs = cnst->getModuleRef()->getGenArgs(); -void garnet_map_module(CodegenOptions& options, Module* top, map & buffers, bool garnet_syntax_trans = false) { - auto c = top->getContext(); + //string ID = genargs.at("ID")->get(); + //int num_inputs = genargs.at("num_inputs")->get(); + //int num_outputs = genargs.at("num_outputs")->get(); + //int width = genargs.at("width")->get(); + int num_inputs = 1; + int num_outputs = 1; + int width = 16; + string mode = "pond"; - top->print(); + json config_file; - //load_cgramapping(c); - LoadDefinition_cgralib(c); + //config_file["ID"] = ID; + config_file["num_inputs"] = num_inputs; + config_file["num_outputs"] = num_outputs; + config_file["width"] = width; + config_file["mode"] = mode; - c->runPasses({"rungenerators"}); + json config; + json in2regfile_0; + json regfile2out_0; + + in2regfile_0["cycle_starting_addr"] = {0}; + in2regfile_0["cycle_stride"] = {1}; + in2regfile_0["dimensionality"] = 1; + in2regfile_0["extent"] = {4096}; + in2regfile_0["write_data_starting_addr"] = {0}; + in2regfile_0["write_data_stride"] = {1}; + + + regfile2out_0["cycle_starting_addr"] = {1}; + regfile2out_0["cycle_stride"] = {1}; + regfile2out_0["dimensionality"] = 1; + regfile2out_0["extent"] = {4096}; + regfile2out_0["read_data_starting_addr"] = {0}; + regfile2out_0["read_data_stride"] = {1}; + + config["in2regfile_0"] = in2regfile_0; + config["regfile2out_0"] = regfile2out_0; + + config_file["config"] = config; + + std::set routable_ports = {"data_in_pond_0"}; + + std::vector routable_outputs = {"O0", "O1"}; + + + auto pt = addPassthrough(cnst, cnst->getInstname()+"_tmp"); + + vector loaded; + if (!loadHeader(c, "pond_header.json", loaded)) {c->die();} + + Instance* buf = def->addInstance(cnst->getInstname()+"_garnet", (Module*)loaded[0]); + + buf->setMetaData(config_file); + + Module* cnst_mod_ref = cnst->getModuleRef(); + + vector cnst_ports = cnst_mod_ref->getType()->getFields(); + + for (auto cnst_port : cnst_ports) { + if (routable_ports.count(cnst_port) > 0) { + cout << "Connecting cnst_port: " << cnst_port << endl; + def->connect(pt->sel("in")->sel(cnst_port), buf->sel(cnst_port)); + } else { + auto index = find(routable_outputs.begin(), routable_outputs.end(), cnst_port); + if (index != routable_outputs.end()){ + int port_index = index - routable_outputs.begin(); + cout << "Connecting output cnst_port: " << cnst_port << endl; + def->connect(buf->sel("O" + std::to_string(port_index)), pt->sel("in")->sel(cnst_port)); + } else { + cout << "Not Connecting cnst_port: " << cnst_port << endl; + } + } + } + + + + ModuleDef* mdef = topm->getDef(); + + //if (def == mdef) { + // def->connect(buf->sel("flush"), mdef->sel("io1in_reset.out")); + //} + + def->removeInstance(cnst); + inlineInstance(pt); + inlineInstance(buf); + + + return true; +} +return false; +} + +//void setVisitorInfo() { +// Context* c = this->getContext(); +// if (c->hasModule("global.Pond")) { +// addVisitorFunction(c->getModule("global.Pond"), PondReplaceMetaMapper); +// } + +//} + +}; +} + + +namespace MapperPasses { +class RegfileSubstituteMetaMapper: public CoreIR::InstanceVisitorPass { + public : + static std::string ID; + RegfileSubstituteMetaMapper() : InstanceVisitorPass(ID,"replace cgralib.pond_amber to global.pond") {} + void setVisitorInfo() override; +}; + +} + + +bool RegfileReplaceMetaMapper(Instance* cnst) { + cout << tab(2) << "memory syntax transformation!" << endl; + cout << tab(2) << toString(cnst) << endl; + Context* c = cnst->getContext(); + + + auto allSels = cnst->getSelects(); + for (auto itr: allSels) { + cout << tab(2) << "Sel: " << itr.first << endl; + } + + + ModuleDef* def = cnst->getContainer(); + auto genargs = cnst->getModuleRef()->getGenArgs(); + + string ID = genargs.at("ID")->get(); + int num_inputs = genargs.at("num_inputs")->get(); + int num_outputs = genargs.at("num_outputs")->get(); + int width = genargs.at("width")->get(); + + + auto config_file = cnst->getMetaData(); + + config_file["ID"] = ID; + config_file["num_inputs"] = num_inputs; + config_file["num_outputs"] = num_outputs; + config_file["width"] = width; + + std::set routable_ports = {"flush", "data_in_pond_0"}; + + std::vector routable_outputs = {"data_out_pond_0", "valid_out_pond"}; + + + auto pt = addPassthrough(cnst, cnst->getInstname()+"_tmp"); + + vector loaded; + if (!loadHeader(c, "pond_header.json", loaded)) {c->die();} + + Instance* buf = def->addInstance(cnst->getInstname()+"_garnet", (Module*)loaded[0]); + + buf->setMetaData(config_file); + + Module* cnst_mod_ref = cnst->getModuleRef(); + + vector cnst_ports = cnst_mod_ref->getType()->getFields(); + + for (auto cnst_port : cnst_ports) { + if (routable_ports.count(cnst_port) > 0) { + cout << "Connecting cnst_port: " << cnst_port << endl; + def->connect(pt->sel("in")->sel(cnst_port), buf->sel(cnst_port)); + } else { + auto index = find(routable_outputs.begin(), routable_outputs.end(), cnst_port); + if (index != routable_outputs.end()){ + int port_index = index - routable_outputs.begin(); + cout << "Connecting output cnst_port: " << cnst_port << endl; + def->connect(buf->sel("O" + std::to_string(port_index)), pt->sel("in")->sel(cnst_port)); + } else { + cout << "Not Connecting cnst_port: " << cnst_port << endl; + } + } + } + + + def->removeInstance(cnst); + inlineInstance(pt); + inlineInstance(buf); + + //TODO: possible bug master comment this out + //remove rst_n +/* + auto rst_n_conSet = buf->sel("rst_n")->getConnectedWireables(); + vector conns(rst_n_conSet.begin(), rst_n_conSet.end()); + assert(conns.size() == 1); + auto conn = conns[0]; + def->disconnect(buf->sel("rst_n"),conn); +*/ + return true; +} + +std::string MapperPasses::RegfileSubstituteMetaMapper::ID = "regfilesubstitutemetamapper"; +void MapperPasses::RegfileSubstituteMetaMapper::setVisitorInfo() { + Context* c = this->getContext(); + if (c->hasGenerator("cgralib.Pond_amber")) { + addVisitorFunction(c->getGenerator("cgralib.Pond_amber"), RegfileReplaceMetaMapper); + } + +} + +namespace MapperPasses { +class RomSubstituteMetaMapper: public CoreIR::InstanceVisitorPass { + public : + static std::string ID; + RomSubstituteMetaMapper() : InstanceVisitorPass(ID,"replace memory.rom2 to new coreir header mem") {} + void setVisitorInfo() override; +}; + +} + + +bool RomReplaceMetaMapper(Instance* cnst) { + cout << tab(2) << "new rom syntax transformation!" << endl; + cout << tab(2) << toString(cnst) << endl; + + Context* c = cnst->getContext(); + auto allSels = cnst->getSelects(); + for (auto itr: allSels) { + cout << tab(2) << "Sel: " << itr.first << endl; + } + ModuleDef* def = cnst->getContainer(); + auto genargs = cnst->getModuleRef()->getGenArgs(); + + int depth = genargs.at("depth")->get(); + int width = genargs.at("width")->get(); + + json config_file; + + config_file["mode"] = "sram"; + config_file["is_rom"] = true; + config_file["width"] = width; + config_file["depth"] = depth; + config_file["init"] = cnst->getModArgs().at("init")->get(); + + vector loaded; + if (!loadHeader(c, "mem_header.json", loaded)) {c->die();} + + Instance* buf = def->addInstance(cnst->getInstname()+"_garnet", (Module*)loaded[0]); + + buf->setMetaData(config_file); + + Module* cnst_mod_ref = cnst->getModuleRef(); + auto pt = addPassthrough(cnst, cnst->getInstname()+"_tmp"); + + // vector cnst_ports = cnst_mod_ref->getType()->getFields(); + + cout << "Wiring raddr" << endl; + def->connect(pt->sel("in")->sel("raddr"), buf->sel(lake_port_map.at("addr_in_0"))); + + cout << "Wiring ren" << endl; + def->connect(pt->sel("in")->sel("ren"), buf->sel(lake_port_map.at("ren_in_0"))); + + cout << "Wiring rdata" << endl; + def->connect(buf->sel("O0"), pt->sel("in")->sel("rdata")); + + def->removeInstance(cnst); + inlineInstance(pt); + inlineInstance(buf); + return true; +} + + +std::string MapperPasses::RomSubstituteMetaMapper::ID = "romsubstitutemetamapper"; +void MapperPasses::RomSubstituteMetaMapper::setVisitorInfo() { + Context* c = this->getContext(); + if (c->hasGenerator("memory.rom2")) { + addVisitorFunction(c->getGenerator("memory.rom2"), RomReplaceMetaMapper); + } + +} + + +namespace MapperPasses { +class PeSubstituteMetaMapper: public CoreIR::InstanceVisitorPass { + public : + static std::string ID; + PeSubstituteMetaMapper() : InstanceVisitorPass(ID,"replace PE to new coreir header pe") {} + void setVisitorInfo() override; +}; + +} + + +bool PeReplaceMetaMapper(Instance* cnst) { + cout << tab(2) << "new pe syntax transformation!" << endl; + cout << tab(2) << toString(cnst) << endl; + + Context* c = cnst->getContext(); + auto allSels = cnst->getSelects(); + for (auto itr: allSels) { + cout << tab(2) << "Sel: " << itr.first << endl; + } + ModuleDef* def = cnst->getContainer(); + + // c->getNamespace("global")->eraseModule("PE"); + // c->getNamespace("global")->eraseModule("PE_wrapped"); + + vector loaded; + if (!loadHeader(c, "petile_header.json", loaded)) {c->die();} + + cout << "Loaded header" << endl; + + Instance* buf = def->addInstance(cnst->getInstname()+"_garnet", (Module*)loaded[0]); + + + Module* cnst_mod_ref = cnst->getModuleRef(); + auto pt = addPassthrough(cnst, cnst->getInstname()+"_tmp"); + def->connect(pt->sel("in"), buf); + + def->removeInstance(cnst); + inlineInstance(pt); + inlineInstance(buf); + return true; +} + + +std::string MapperPasses::PeSubstituteMetaMapper::ID = "pesubstitutemetamapper"; +void MapperPasses::PeSubstituteMetaMapper::setVisitorInfo() { + Context* c = this->getContext(); + if (c->hasModule("global.WrappedPE")) { + addVisitorFunction(c->getModule("global.WrappedPE"), PeReplaceMetaMapper); + } + +} + + +namespace MapperPasses { +class ConstDuplication : public CoreIR::InstanceVisitorPass { + public : + static std::string ID; + ConstDuplication() : InstanceVisitorPass(ID,"duplicate all constants") {} + void setVisitorInfo() override; +}; + +} + +bool ConstDup(Instance* cnst) { + Module* modRef = cnst->getModuleRef(); + + auto connSet = cnst->sel("out")->getConnectedWireables(); + if (connSet.size() < 1) { + return false; + } + vector conns(connSet.begin(),connSet.end()); + + ModuleDef* def = cnst->getContainer(); + for (uint i=1; i< conns.size(); ++i) { + Wireable* conn = conns[i]; + cout << "replacing connection to : " << conn->toString() << endl; + Instance* newconst = def->addInstance(cnst->getInstname() + to_string(i),modRef,cnst->getModArgs()); + def->connect(newconst->sel("out"),conn); + def->disconnect(cnst->sel("out"),conn); + } + return true; +} + +std::string MapperPasses::ConstDuplication::ID = "constduplication"; +void MapperPasses::ConstDuplication::setVisitorInfo() { + Context* c = this->getContext(); + if (c->hasModule("corebit.const")) { + addVisitorFunction(c->getModule("corebit.const"),ConstDup); + } + if (c->hasGenerator("coreir.const")) { + addVisitorFunction(c->getGenerator("coreir.const"),ConstDup); + } + +} + +void disconnect_input_enable(Context* c, Module* top) { + ModuleDef* def = top->getDef(); + for (auto it: def->sel("self")->getSelects()) { + string port = it.first; + cout << "Find top interface: " << port << endl; + if (contains(port, "read_en")) { + auto conns = def->sel("self")->sel(port)->getConnectedWireables(); + for (auto conn: conns) { + def->disconnect(def->sel("self")->sel(port), conn); + } + } + } +} + + +// Pass to map Tahoe memory tile intended for metamapper +void map_memory(CodegenOptions& options, Module* top, map & buffers, bool garnet_syntax_trans = false) { + auto c = top->getContext(); + //LoadDefinition_cgralib(c); + disconnect_input_enable(c, top); + + //GLB passes + c->addPass(new ReplaceCoarseGrainedAffCtrl); + c->runPasses({"replacecoarsegrainedaffctrl"}); + + auto glb_pass = new GetGLBConfig(); + c->addPass(glb_pass); + c->runPasses({"getglbconfig"}); + //override latency using the input, + //FIXME: this hack will break stencil apps + if ((options.host2glb_latency != 0) && (glb_pass->latency != 0)) + glb_pass->latency = options.host2glb_latency; + + c->addPass(new MapperPasses::StripGLB); + c->runPasses({"stripglb"}); + addIOsWithGLBConfigMetaMapper(c, top, buffers, glb_pass); + + c->addPass(new CustomFlatten); + c->runPasses({"customflatten"}); + + //Change the stencil valid signal to cgra to glb + c->addPass(new ReplaceGLBValid(glb_pass)); + c->runPasses({"replaceglbvalid"}); + c->addPass(new RemoveFlush()); + c->runPasses({"removeflush"}); + if (garnet_syntax_trans) { + c->addPass(new SubstructGLBLatency(glb_pass->latency)); + c->runPasses({"substractglblatency"}); + } + + c->addPass(new MapperPasses::RomSubstituteMetaMapper); + c->runPasses({"romsubstitutemetamapper"}); + c->addPass(new MapperPasses::MemSubstituteMetaMapper); + c->runPasses({"memsubstitutemetamapper"}); + c->addPass(new MapperPasses::PondSubstituteMetaMapper(top)); + c->runPasses({"pondsubstitutemetamapper"}); + c->addPass(new MapperPasses::RegfileSubstituteMetaMapper); + c->runPasses({"regfilesubstitutemetamapper"}); + +} + + +void garnet_map_module(Module* top, bool garnet_syntax_trans = false) { + auto c = top->getContext(); + + top->print(); + + //load_cgramapping(c); + LoadDefinition_cgralib(c); + + c->runPasses({"rungenerators"}); + //A new pass to remove input enable signal affine controller + disconnect_input_enable(c, top); + c->runPasses({"deletedeadinstances"}); + + c->runPasses({"cullgraph"}); + c->runPasses({"removewires"}); + addIOs(c,top); + c->runPasses({"cullgraph"}); + c->addPass(new CustomFlatten); + c->runPasses({"customflatten"}); + if (garnet_syntax_trans) { + c->addPass(new MapperPasses::MemInitCopy); + c->runPasses({"meminitcopy"}); + c->addPass(new MapperPasses::MemSubstitute); + c->runPasses({"memsubstitute"}); + c->addPass(new MapperPasses::RegfileSubstitute); + c->runPasses({"regfilesubstitute"}); + } + c->addPass(new MapperPasses::ConstDuplication); + c->runPasses({"constduplication"}); + c->addPass(new MapperPasses::MemConst); + c->runPasses({"memconst"}); + + c->runPasses({"cullgraph"}); + c->getPassManager()->printLog(); + cout << "Trying to save" << endl; + c->runPasses({"coreirjson"},{"global","commonlib","mantle"}); + c->runPasses({"removewires"}); + + auto jpass = static_cast(c->getPassManager()->getAnalysisPass("coreirjson")); + string postmap = "after_mapping_" + top->getName() + ".json"; + ////Create file here. + std::ofstream file(postmap); + jpass->writeToStream(file,top->getRefName()); +} + +void garnet_map_module(CodegenOptions& options, Module* top, map & buffers, bool garnet_syntax_trans = false) { + auto c = top->getContext(); + + top->print(); + + //load_cgramapping(c); + LoadDefinition_cgralib(c); + + c->runPasses({"rungenerators"}); //A new pass to remove input enable signal affine controller disconnect_input_enable(c, top); @@ -3630,6 +4325,8 @@ void garnet_map_module(CodegenOptions& options, Module* top, mapaddPass(new ReplaceGLBValid(glb_pass)); c->runPasses({"replaceglbvalid"}); + c->addPass(new RemoveFlush()); + c->runPasses({"removeflush"}); if (garnet_syntax_trans) { c->addPass(new MapperPasses::MemInitCopy); @@ -3769,6 +4466,78 @@ void count_post_mapped_memory_accesses(Module* gmod) { //assert(false); } + +//You should consider +//Max extend bitwidth +//Max cycle stride +//Max starting cycle address +struct MemCtrl{ + map val_map; + map bw_map; + + void init_key(const string & key) { + val_map[key] = 0; + bw_map[key] = 0; + } + + void register_max_val(const string & ctrl_key, json & config) { + for (auto & ctrl: config.items()) { + auto & val = ctrl.value(); + if(val.count(ctrl_key)) { + vector ext = val[ctrl_key].get>(); + cout << ctrl_key << ctrl.key() << "->" << ext << endl; + int this_ctrl_max_ext = *std::max_element(ext.begin(), ext.end()); + val_map.at(ctrl_key) = std::max(val_map.at(ctrl_key), this_ctrl_max_ext); + bw_map.at(ctrl_key) = std::max(bw_map.at(ctrl_key), (int)round(log2(this_ctrl_max_ext))); + } + } + + } + + void dumpToFile(ofstream& out) { + out << tab(1) << "controller value MAX: " << endl; + for (auto it: val_map) { + string key = it.first; + out << tab(2) << key << ": " << val_map.at(key) << ", bitwidth: " << bw_map.at(key) << endl; + } + } +}; + +MemCtrl post_mapped_memory_controller_bitwidth(Module* gmod) { + int min_ext = 0, min_ext_bw = 0; + MemCtrl lakeController; + vector ctrl_names = {"extent", "cycle_starting_addr", "cycle_stride"}; + for (auto inst : gmod->getDef()->getInstances()) { + if (inst.second->getModuleRef()->getName() == "Mem") { + auto config = inst.second->getModArgs().at("config")->get(); + cout << "Metadata...\n\t" << config << endl; + for (string& ctrl_key: ctrl_names) { + lakeController.init_key(ctrl_key); + lakeController.register_max_val(ctrl_key, config); + } + //for (auto & ctrl: config.items()) { + // auto & val = ctrl.value(); + // if(val.count("extent")) { + // vector ext = val["extent"].get>(); + // cout << "ctrl: " << ctrl.key() << "->" << ext << endl; + // int this_ctrl_min_ext = *std::max_element(ext.begin(), ext.end()); + // min_ext = std::max(min_ext, this_ctrl_min_ext); + // min_ext_bw = std::max(min_ext_bw, (int)round(log2(this_ctrl_min_ext))); + // } + //} + } + } + return lakeController; +} + +void analyze_latency(CodegenOptions& options, umap* sched_map) { + auto sched_max = lexmaxval(to_set(range(sched_map))); + ofstream out(options.dir + "/cgra_resource_estimation.csv", std::ios_base::app); + out << "latency, " << str(sched_max) << endl; + cout << "latency, " << str(sched_max) << endl; + out.close(); +} + void analyze_post_mapped_app(CodegenOptions& options, prog& prg, map& buffers, Module* gmod) { //count_post_mapped_memory_use(gmod); //count_post_mapped_memory_accesses(gmod); @@ -3792,6 +4561,85 @@ void analyze_post_mapped_app(CodegenOptions& options, prog& prg, map& buffers, Module* gmod) { + ofstream out("cgra_resource_estimation.csv"); + auto context = gmod->getContext(); + auto ns = context->getNamespace("global"); + //cout << "=== Post mapping instances for " << prg.name << endl; + map affine_controller; + map affine_func; + int mem = 0; + for (auto inst : gmod->getDef()->getInstances()) { + //cout << tab(1) << inst.second->getModuleRef()->getName() << endl; + string module_name = inst.second->getModuleRef()->getName(); + if (contains(module_name, "affine_controller")) { + auto tp = inst.second->sel("d")->getType(); + assert(isa(tp)); + auto atp = dyn_cast(tp); + affine_controller[atp->getLen()] ++; + } + else if (contains(module_name, "_ub")) { + for(auto sub_inst : inst.second->getModuleRef()->getDef()->getInstances()) { + string module_name = sub_inst.second->getModuleRef()->getName(); + if (contains(module_name, "Mem_amber")) { + mem ++; + } else if (contains(module_name, "affine_controller")) { + auto tp = sub_inst.second->sel("d")->getType(); + assert(isa(tp)); + auto atp = dyn_cast(tp); + affine_controller[atp->getLen()] ++; + } else if (contains(module_name, "aff__U")) { + auto tp = sub_inst.second->sel("d")->getType(); + assert(isa(tp)); + auto atp = dyn_cast(tp); + affine_func[atp->getLen()] ++; + } + } + } + } + int aff_ctrl_pe = 0, aff_ctrl_full = 0; + for (auto it: affine_controller) { + aff_ctrl_pe += it.second * (it.first * 2 - 3); + aff_ctrl_full += it.second * (it.first * 8 - 1); + } + int aff_func_pe = 0, aff_func_full = 0; + for (auto it: affine_func) { + aff_func_pe += it.second * (it.first); + aff_func_full += it.second * (2*it.first); + } + //cout << prg.name << " Post Mapping Resource Counts..." << endl; + out << tab(2) << " affine_controller: " << affine_controller << endl; + out << tab(2) << " affine_func: " << affine_func<< endl; + out << tab(2) << " aff_ctrl pe: " << aff_ctrl_pe << endl; + out << tab(2) << " aff_func pe: " << aff_func_pe << endl; + out << tab(2) << " aff_ctrl pe full: " << aff_ctrl_full << endl; + out << tab(2) << " aff_func pe full: " << aff_func_full << endl; + out << tab(2) << " mem: " << mem << endl; +} + +void analyze_post_mapped_app_emit_to_file(CodegenOptions& options, prog& prg, map& buffers, Module* gmod) { + //count_post_mapped_memory_use(gmod); + //count_post_mapped_memory_accesses(gmod); + ofstream out(options.dir + "/cgra_resource_estimation.csv"); + auto context = gmod->getContext(); + auto ns = context->getNamespace("global"); + //cout << "=== Post mapping instances for " << prg.name << endl; + map counts; + for (auto inst : gmod->getDef()->getInstances()) { + //cout << tab(1) << inst.second->getModuleRef()->getName() << endl; + counts[inst.second->getModuleRef()->getName()]++; + } + cout << prg.name << " Post Mapping Resource Counts..." << endl; + for (auto c : counts) { + cout << tab(1) << c.first << " -> " << c.second << endl; + out << tab(1) << c.first << ", " << c.second << endl; + } + auto ctrl_bw_info = post_mapped_memory_controller_bitwidth(gmod); + out << endl; + ctrl_bw_info.dumpToFile(out); + out.close(); +} + //This is the top_level coreIR generation function void generate_coreir(CodegenOptions& options, map& buffers, @@ -3803,6 +4651,9 @@ void generate_coreir(CodegenOptions& options, CoreIRLoadLibrary_commonlib(context); CoreIRLoadLibrary_cgralib(context); CoreIRLoadLibrary_cwlib(context); + CoreIRLoadLibrary_float(context); + CoreIRLoadLibrary_float_DW(context); + //load_float(context); add_delay_tile_generator(context); add_raw_quad_port_memtile_generator(context); add_tahoe_memory_generator(context); @@ -3811,7 +4662,7 @@ void generate_coreir(CodegenOptions& options, CoreIR::Module* prg_mod; if (options.rtl_options.use_prebuilt_memory) { - prg_mod = generate_coreir_without_ctrl(options, buffers, prg, schedmap, context, hwinfo); + prg_mod = generate_coreir_without_ctrl(options, buffers, prg, schedmap, context, hwinfo, ""); } else { prg_mod = generate_coreir(options, buffers, prg, schedmap, context, hwinfo); } @@ -3836,6 +4687,9 @@ void generate_coreir(CodegenOptions& options, garnet_map_module(options, prg_mod, buffers, true); context->runPasses({"rungenerators", "flatten", "removewires", "cullgraph"}); + Module* gmod = ns_new->getModule(prg.name); + analyze_post_mapped_app_emit_to_file(options, prg, buffers, gmod); + analyze_latency(options, schedmap); if(!saveToFile(ns_new, options.dir + prg.name+ "_garnet.json", prg_mod)) { cout << "Could not save ubuffer coreir" << endl; context->die(); @@ -3846,8 +4700,8 @@ void generate_coreir(CodegenOptions& options, options.rtl_options.target_tile == TARGET_TILE_M3) { //count_memory_tiles(prg_mod); //garnet_map_module(prg_mod); - //Module* gmod = ns_new->getModule(prg.name); - //analyze_post_mapped_app(options, prg, buffers, gmod); + Module* gmod = ns_new->getModule(prg.name); + analyze_post_mapped_app_M1(options, prg, buffers, gmod); } prg_mod->print(); //assert(false); @@ -3855,6 +4709,68 @@ void generate_coreir(CodegenOptions& options, deleteContext(context); } +void generate_coreir_without_ctrl(CodegenOptions& options, + map& buffers, + prog& prg, + umap* schedmap, + schedule_info& hwinfo, + string dse_compute_filename) { + + + CoreIR::Context* context = CoreIR::newContext(); + CoreIRLoadLibrary_commonlib(context); + CoreIRLoadLibrary_cgralib(context); + CoreIRLoadLibrary_cwlib(context); + add_delay_tile_generator(context); + add_raw_quad_port_memtile_generator(context); + add_tahoe_memory_generator(context); + ram_module(context, DATAPATH_WIDTH, 2048); + + auto c = context; + + CoreIR::Module* prg_mod; + + prg_mod = generate_coreir_without_ctrl(options, buffers, prg, schedmap, context, hwinfo, dse_compute_filename); + + + auto ns = context->getNamespace("global"); + if(!saveToFile(ns, options.dir + prg.name + ".json", prg_mod)) { + cout << "Could not save ubuffer coreir" << endl; + context->die(); + } + + map_memory(options, prg_mod, buffers, true); + + +// for (auto op : prg.all_ops()) { +// cout << "Inlining " << op->name << endl; +// prg_mod->print(); +// for (auto inst: prg_mod->getDef()->getInstances()){ +// inlineInstance(inst.second); +// } + //CoreIR::Instance* kernel = prg_mod->getDef()->getInstances().at(op->name); + //inlineInstance(kernel); +// } + + c->runPasses({"deletedeadinstances"}); + c->runPasses({"removewires"}); + c->runPasses({"coreirjson"},{"global"}); + + context->runPasses({"rungenerators", "removewires", "cullgraph"}); + c->runPasses({"flatten"}); + c->runPasses({"flattentypes"}); + c->runPasses({"deletedeadinstances"}); + + + auto global = context->getNamespace("global"); + if(!saveToFile(global, options.dir + prg.name+ "_to_metamapper.json", prg_mod)) { + cout << "Could not save ubuffer coreir" << endl; + context->die(); + } + + deleteContext(context); +} + //CoreIR::Context* context = CoreIR::newContext(); CoreIR::Wireable* delaybit(CoreIR::ModuleDef* bdef, @@ -4310,9 +5226,8 @@ CoreIR::Module* affine_controller_primitive(CodegenOptions& options, CoreIR::Con def->connect(cycle_time_reg->sel("reset"), def->sel("self.rst_n")); def->connect(cycle_time_reg->sel("en"), tinc->sel("out")); } else { - cycle_time_reg = def->addInstance("cycle_time", "mantle.reg", - {{"width", CoreIR::Const::make(context, width)}, - {"has_en", CoreIR::Const::make(context, false)}}); + cycle_time_reg = def->addInstance("cycle_time", "coreir.reg", + {{"width", CoreIR::Const::make(context, width)}}); auto inc_time = def->addInstance("inc_time", "coreir.add", {{"width", CoreIR::Const::make(c, width)}}); def->connect(inc_time->sel("in0"), cycle_time_reg->sel("out")); @@ -5087,6 +6002,10 @@ void pipeline_compute_units(prog& prg, schedule_info& hwinfo) { bool found_compute = true; string compute_file = "./coreir_compute/" + prg.name + "_compute.json"; + if (hwinfo.use_metamapper) { + compute_file = hwinfo.dse_compute_filename; + cout << "Compute file dse found" << endl; + } ifstream cfile(compute_file); if (!cfile.good()) { cout << "No compute unit file: " << compute_file << endl; @@ -5684,9 +6603,9 @@ std::set generate_block_shift_register(CodegenOptions& options, CoreIR:: Wireable * delayed_src = delay_by(def, "sr_ito_all_" + c->getUnique(), src_wire, b_sreg.init_delay); def->connect(def->sel(b_sreg.chain_starts.at(0) + "_net.in"), delayed_src); - cout << tab(1) << b_sreg.difference << endl; + cout << tab(1) << "block SR difference: " << b_sreg.difference << endl; for (auto b : b_sreg.chain_starts) { - cout << tab(2) << b << endl; + cout << tab(2) << "b SR chain start: " << b << endl; } assert(b_sreg.chain_starts.size() % 2 == 1); @@ -5825,7 +6744,10 @@ std::set generate_M1_shift_registers(CodegenOptions& options, CoreIR::Mo dgraph shift_registers = build_shift_registers(options, def, prg, buf, hwinfo); block_sreg b_sreg; - auto packed_sr = allow_packed_sr(shift_registers, buf,& b_sreg); + + //FIXME: permanently disable packed shift register do not packed for m1 / m3 + //auto packed_sr = allow_packed_sr(shift_registers, buf,& b_sreg); + auto packed_sr = false; auto c = def->getContext(); @@ -5972,13 +6894,15 @@ void generate_M1_coreir(CodegenOptions& options, CoreIR::ModuleDef* def, prog& p UBuffer buf = delete_ports(done_outpt, orig_buf); if (buf.num_out_ports() > 0) { - auto implm = build_buffer_impl(prg, buf, hwinfo); - auto impl = implm.first; + auto impl = build_buffer_impl(options, prg, buf, hwinfo); + //auto impl = implm.first; - int num_banks = 1; - for (auto ent : impl.partitioned_dimension_extents) { - num_banks *= ent.second; - } + //int num_banks = 1; + //for (auto ent : impl.partitioned_dimension_extents) { + // num_banks *= ent.second; + //} + int num_banks = impl.get_bank_num(); + cout << impl << "\tnum banks: " << num_banks<< endl; M1_sanity_check_port_counts(impl); @@ -6033,7 +6957,7 @@ void generate_M1_coreir(CodegenOptions& options, CoreIR::ModuleDef* def, prog& p control_vars(def, pt, adjusted_buf)); ubuffer_port_agens[pt] = agen; - if (impl.inpt_to_bank[pt].size() > 1) { + if ((impl.inpt_to_bank[pt].size() > 1) && (impl.partition_dims.size())) { auto bank_sel = build_bank_selector(pt, adjusted_buf, impl, def); def->connect(bank_sel->sel("d"), control_vars(def, pt, adjusted_buf)); @@ -6125,22 +7049,34 @@ void generate_M1_coreir(CodegenOptions& options, CoreIR::ModuleDef* def, prog& p if (conds.size() == 1) { def->connect(def->sel(conn.first + "_net.in"), pick(conn.second)); } else { - assert(conds.size() == 3); + // assert(conds.size() == 3); + // Wireable* out = def->sel(conn.first + "_net.in"); + + // auto snd_mux = + // def->addInstance("chain_mux" + c->getUnique(), "coreir.mux", {{"width", CoreIR::Const::make(c, 16)}}); + // def->connect(snd_mux->sel("in0"), vals[1]); + // def->connect(snd_mux->sel("in1"), vals[2]); + // def->connect(snd_mux->sel("sel"), conds[2]); + + // auto last_mux = + // def->addInstance("chain_mux" + c->getUnique(), "coreir.mux", {{"width", CoreIR::Const::make(c, 16)}}); + // def->connect(last_mux->sel("in0"), snd_mux->sel("out")); + // def->connect(last_mux->sel("in1"), vals[0]); + // def->connect(last_mux->sel("sel"), conds[0]); + + // def->connect(last_mux->sel("out"), out); + //} else { Wireable* out = def->sel(conn.first + "_net.in"); - - auto snd_mux = - def->addInstance("chain_mux" + c->getUnique(), "coreir.mux", {{"width", CoreIR::Const::make(c, 16)}}); - def->connect(snd_mux->sel("in0"), vals[1]); - def->connect(snd_mux->sel("in1"), vals[2]); - def->connect(snd_mux->sel("sel"), conds[2]); - - auto last_mux = - def->addInstance("chain_mux" + c->getUnique(), "coreir.mux", {{"width", CoreIR::Const::make(c, 16)}}); - def->connect(last_mux->sel("in0"), snd_mux->sel("out")); - def->connect(last_mux->sel("in1"), vals[0]); - def->connect(last_mux->sel("sel"), conds[0]); - - def->connect(last_mux->sel("out"), out); + CoreIR::Wireable* out_wire = vals.at(0); + for (auto i = 1; i < conds.size(); i ++ ) { + auto mux = def->addInstance("chain_mux" + c->getUnique(), + "coreir.mux", {{"width", CoreIR::Const::make(c, 16)}}); + def->connect(out_wire, mux->sel("in0")); + def->connect(vals[i], mux->sel("in1")); + def->connect(conds[i], mux->sel("sel")); + out_wire = mux->sel("out"); + } + def->connect(out_wire, out); } } @@ -6154,7 +7090,7 @@ void generate_M1_coreir(CodegenOptions& options, CoreIR::ModuleDef* def, prog& p auto agen = ubuffer_port_agens[pt]; Wireable* enable = nullptr; - if (inpt_to_bank[pt].size() > 1) { + if ((inpt_to_bank[pt].size() > 1) && (impl.partition_dims.size() != 0)) { enable = andList(def, {control_en(def, pt, adjusted_buf), eqConst(def, ubuffer_port_bank_selectors[pt], b)}); } else { @@ -6255,11 +7191,20 @@ CoreIR::Instance* build_inner_bank_offset(const std::string& reader, UBuffer& bu int bank_stride = 1; vector dvs; vector coeffs; + //for (int d = 0; d < buf.logical_dimension(); d++) { + // dvs.push_back("d" + str(d)); + // if (!dbhc::elem(d, impl.partition_dims)) { + // coeffs.push_back(str(bank_stride) + "*" + dvs.at(d)); + // bank_stride *= extents.at(d); + // } + //} + + //new linear algorithm accumulate stride from inner most dimension for (int d = 0; d < buf.logical_dimension(); d++) { - dvs.push_back("d" + str(d)); - if (!dbhc::elem(d, impl.partition_dims)) { - coeffs.push_back(str(bank_stride) + "*" + dvs.at(d)); - bank_stride *= extents.at(d); + dvs.insert(dvs.begin(), "d" + str(d)); + if (!dbhc::elem(buf.logical_dimension()-1-d, impl.partition_dims)) { + coeffs.push_back(str(bank_stride) + "*" + dvs.front()); + bank_stride *= extents.at(buf.logical_dimension() - 1- d); } } diff --git a/coreir_backend.h b/coreir_backend.h index 1662343a4..e8e8fc584 100644 --- a/coreir_backend.h +++ b/coreir_backend.h @@ -19,6 +19,7 @@ struct affine_controller_ctrl { isl_set* dom; }; +CoreIR::Wireable* op_control_wires(CoreIR::Instance* ctrl); CoreIR::Wireable* mkConst(CoreIR::ModuleDef* def, const int width, const int val); CoreIR::Wireable* addList(CoreIR::ModuleDef* def, const std::vector& vals, int width); @@ -70,7 +71,8 @@ void generate_coreir_without_ctrl(CodegenOptions& options, map& buffers, prog& prg, umap* schedmap, - schedule_info& hwinfo); + schedule_info& hwinfo, + string dse_compute_filename); CoreIR::Wireable* delaybit(CoreIR::ModuleDef* bdef, CoreIR::Wireable* w); @@ -91,16 +93,6 @@ CoreIR::Wireable* delay_array(CoreIR::ModuleDef* def, int elem_width, int num_elems); -map > determine_shift_reg_map( - prog& prg, - UBuffer& buf, - schedule_info& hwinfo); - -vector >> determine_output_shift_reg_map( - prog& prg, - UBuffer& buf, - schedule_info& hwinfo); - dgraph build_shift_register_graph(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo); @@ -145,7 +137,7 @@ void generate_platonic_ubuffer(CodegenOptions& options, void generate_lake_tile_verilog(CodegenOptions& options, CoreIR::Instance* buf); -void add_default_initial_block(); +void add_default_initial_block(string, string); CoreIR::Wireable* delay_by(CoreIR::ModuleDef* bdef, CoreIR::Wireable* w, diff --git a/coreir_compute/camera_pipeline_2x2_compute.json b/coreir_compute/camera_pipeline_2x2_compute.json new file mode 100644 index 000000000..a77942367 --- /dev/null +++ b/coreir_compute/camera_pipeline_2x2_compute.json @@ -0,0 +1,2946 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_b_b_stencil":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_gb_stencil":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_1_b_b_stencil_2_545":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_1_g_b_stencil_2_549":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_3_547_548":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__546":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__546$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_545_546_547":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_549_546_550":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_548_550_551":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_1_b_b_stencil_2_545.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_1_b_b_stencil_2_545.in1"], + ["lshr_545_546_547.in0","add_b_b_stencil_1_b_b_stencil_2_545.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_1_g_b_stencil_2_549.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_1_g_b_stencil_2_549.in1"], + ["lshr_549_546_550.in0","add_g_b_stencil_1_g_b_stencil_2_549.out"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_3_547_548.in0"], + ["lshr_545_546_547.out","add_g_gb_stencil_3_547_548.in1"], + ["sub_548_550_551.in0","add_g_gb_stencil_3_547_548.out"], + ["lshr_549_546_550.in1","const_p1__546$1.out"], + ["lshr_545_546_547.in1","const_p1__546.out"], + ["sub_548_550_551.in1","lshr_549_546_550.out"], + ["sub_548_550_551.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gr_stencil":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_3_b_b_stencil_4_573":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_3_g_b_stencil_4_577":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_3_575_576":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__574":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__574$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_573_574_575":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_577_574_578":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_576_578_579":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_3_b_b_stencil_4_573.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_3_b_b_stencil_4_573.in1"], + ["lshr_573_574_575.in0","add_b_b_stencil_3_b_b_stencil_4_573.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_3_g_b_stencil_4_577.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_3_g_b_stencil_4_577.in1"], + ["lshr_577_574_578.in0","add_g_b_stencil_3_g_b_stencil_4_577.out"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_3_575_576.in0"], + ["lshr_573_574_575.out","add_g_gr_stencil_3_575_576.in1"], + ["sub_576_578_579.in0","add_g_gr_stencil_3_575_576.out"], + ["lshr_577_574_578.in1","const_p1__574$1.out"], + ["lshr_573_574_575.in1","const_p1__574.out"], + ["sub_576_578_579.in1","lshr_577_574_578.out"], + ["sub_576_578_579.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_r_stencil":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_5_b_b_stencil_6_669":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_7_b_b_stencil_8_670":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_5_b_b_stencil_6_672":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_7_b_b_stencil_8_679":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_5_g_b_stencil_6_676":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_7_g_b_stencil_8_682":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_674_675":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_680_681":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__673":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__673$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__673$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__673$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_672_673_674":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_676_673_677":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_679_673_680":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_682_673_683":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_671_678_684":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_675_677_678":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_681_683_684":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_669_670_671":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_5_b_b_stencil_6_669.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_5_b_b_stencil_6_669.in1"], + ["ult_669_670_671.in0","absd_b_b_stencil_5_b_b_stencil_6_669.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_7_b_b_stencil_8_670.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_7_b_b_stencil_8_670.in1"], + ["ult_669_670_671.in1","absd_b_b_stencil_7_b_b_stencil_8_670.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_5_b_b_stencil_6_672.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_5_b_b_stencil_6_672.in1"], + ["lshr_672_673_674.in0","add_b_b_stencil_5_b_b_stencil_6_672.out"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_7_b_b_stencil_8_679.in0"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_7_b_b_stencil_8_679.in1"], + ["lshr_679_673_680.in0","add_b_b_stencil_7_b_b_stencil_8_679.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_5_g_b_stencil_6_676.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_5_g_b_stencil_6_676.in1"], + ["lshr_676_673_677.in0","add_g_b_stencil_5_g_b_stencil_6_676.out"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_7_g_b_stencil_8_682.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_7_g_b_stencil_8_682.in1"], + ["lshr_682_673_683.in0","add_g_b_stencil_7_g_b_stencil_8_682.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_674_675.in0"], + ["lshr_672_673_674.out","add_g_r_stencil_1_674_675.in1"], + ["sub_675_677_678.in0","add_g_r_stencil_1_674_675.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_680_681.in0"], + ["lshr_679_673_680.out","add_g_r_stencil_1_680_681.in1"], + ["sub_681_683_684.in0","add_g_r_stencil_1_680_681.out"], + ["lshr_676_673_677.in1","const_p1__673$1.out"], + ["lshr_679_673_680.in1","const_p1__673$2.out"], + ["lshr_682_673_683.in1","const_p1__673$3.out"], + ["lshr_672_673_674.in1","const_p1__673.out"], + ["sub_675_677_678.in1","lshr_676_673_677.out"], + ["sub_681_683_684.in1","lshr_682_673_683.out"], + ["sub_681_683_684.out","mux_671_678_684.in0"], + ["sub_675_677_678.out","mux_671_678_684.in1"], + ["self.out_b_r_stencil","mux_671_678_684.out"], + ["ult_669_670_671.out","mux_671_678_684.sel"] + ] + }, + "hcompute_corrected_stencil":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_941_944_945":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_945_948_949":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_949_950_951":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__950":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__938":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__938$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__938$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_940549_941":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_943n103_944":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_9477_948":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_1_938_939":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_2_938_942":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_3_938_946":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_940549_941.out","add_941_944_945.in0"], + ["mult_middle_943n103_944.out","add_941_944_945.in1"], + ["add_945_948_949.in0","add_941_944_945.out"], + ["mult_middle_9477_948.out","add_945_948_949.in1"], + ["add_949_950_951.in0","add_945_948_949.out"], + ["const_n40__950.out","add_949_950_951.in1"], + ["self.out_corrected_stencil","add_949_950_951.out"], + ["mult_middle_943n103_944.in1","const_n103_n103.out"], + ["umin_demosaicked_1_stencil_2_938_942.in1","const_p10000__938$1.out"], + ["umin_demosaicked_1_stencil_3_938_946.in1","const_p10000__938$2.out"], + ["umin_demosaicked_1_stencil_1_938_939.in1","const_p10000__938.out"], + ["mult_middle_940549_941.in1","const_p549_549.out"], + ["mult_middle_9477_948.in1","const_p7_7.out"], + ["umin_demosaicked_1_stencil_1_938_939.out","mult_middle_940549_941.in0"], + ["umin_demosaicked_1_stencil_2_938_942.out","mult_middle_943n103_944.in0"], + ["umin_demosaicked_1_stencil_3_938_946.out","mult_middle_9477_948.in0"], + ["umin_demosaicked_1_stencil_1_938_939.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_2_938_942.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_3_938_946.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_1":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1000_1003_1004":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1004_1007_1008":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1008_1009_1010":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1009":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__997":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__997$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__997$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_1002373_1003":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_100662_1007":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_999n96_1000":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_4_997_998":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_5_997_1001":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_6_997_1005":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_999n96_1000.out","add_1000_1003_1004.in0"], + ["mult_middle_1002373_1003.out","add_1000_1003_1004.in1"], + ["add_1004_1007_1008.in0","add_1000_1003_1004.out"], + ["mult_middle_100662_1007.out","add_1004_1007_1008.in1"], + ["add_1008_1009_1010.in0","add_1004_1007_1008.out"], + ["const_n29__1009.out","add_1008_1009_1010.in1"], + ["self.out_corrected_stencil","add_1008_1009_1010.out"], + ["mult_middle_999n96_1000.in1","const_n96_n96.out"], + ["umin_demosaicked_1_stencil_5_997_1001.in1","const_p10000__997$1.out"], + ["umin_demosaicked_1_stencil_6_997_1005.in1","const_p10000__997$2.out"], + ["umin_demosaicked_1_stencil_4_997_998.in1","const_p10000__997.out"], + ["mult_middle_1002373_1003.in1","const_p373_373.out"], + ["mult_middle_100662_1007.in1","const_p62_62.out"], + ["umin_demosaicked_1_stencil_5_997_1001.out","mult_middle_1002373_1003.in0"], + ["umin_demosaicked_1_stencil_6_997_1005.out","mult_middle_100662_1007.in0"], + ["umin_demosaicked_1_stencil_4_997_998.out","mult_middle_999n96_1000.in0"], + ["umin_demosaicked_1_stencil_4_997_998.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_5_997_1001.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_6_997_1005.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_10":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1539_1542_1543":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1543_1546_1547":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1547_1548_1549":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1548":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__1536":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1536$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1536$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_1538n96_1539":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1541373_1542":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_154562_1546":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_31_1536_1537":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_32_1536_1540":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_33_1536_1544":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1538n96_1539.out","add_1539_1542_1543.in0"], + ["mult_middle_1541373_1542.out","add_1539_1542_1543.in1"], + ["add_1543_1546_1547.in0","add_1539_1542_1543.out"], + ["mult_middle_154562_1546.out","add_1543_1546_1547.in1"], + ["add_1547_1548_1549.in0","add_1543_1546_1547.out"], + ["const_n29__1548.out","add_1547_1548_1549.in1"], + ["self.out_corrected_stencil","add_1547_1548_1549.out"], + ["mult_middle_1538n96_1539.in1","const_n96_n96$3.out"], + ["umin_demosaicked_1_stencil_32_1536_1540.in1","const_p10000__1536$1.out"], + ["umin_demosaicked_1_stencil_33_1536_1544.in1","const_p10000__1536$2.out"], + ["umin_demosaicked_1_stencil_31_1536_1537.in1","const_p10000__1536.out"], + ["mult_middle_1541373_1542.in1","const_p373_373$3.out"], + ["mult_middle_154562_1546.in1","const_p62_62$3.out"], + ["umin_demosaicked_1_stencil_31_1536_1537.out","mult_middle_1538n96_1539.in0"], + ["umin_demosaicked_1_stencil_32_1536_1540.out","mult_middle_1541373_1542.in0"], + ["umin_demosaicked_1_stencil_33_1536_1544.out","mult_middle_154562_1546.in0"], + ["umin_demosaicked_1_stencil_31_1536_1537.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_32_1536_1540.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_33_1536_1544.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_11":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1600_1603_1604":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1604_1607_1608":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1608_1609_1610":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1609":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1597":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1597$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1597$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1599n31_1600":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1602n261_1603":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1606883_1607":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_34_1597_1598":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_35_1597_1601":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_36_1597_1605":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1599n31_1600.out","add_1600_1603_1604.in0"], + ["mult_middle_1602n261_1603.out","add_1600_1603_1604.in1"], + ["add_1604_1607_1608.in0","add_1600_1603_1604.out"], + ["mult_middle_1606883_1607.out","add_1604_1607_1608.in1"], + ["add_1608_1609_1610.in0","add_1604_1607_1608.out"], + ["const_n22__1609.out","add_1608_1609_1610.in1"], + ["self.out_corrected_stencil","add_1608_1609_1610.out"], + ["mult_middle_1602n261_1603.in1","const_n261_n261$3.out"], + ["mult_middle_1599n31_1600.in1","const_n31_n31$3.out"], + ["umin_demosaicked_1_stencil_35_1597_1601.in1","const_p10000__1597$1.out"], + ["umin_demosaicked_1_stencil_36_1597_1605.in1","const_p10000__1597$2.out"], + ["umin_demosaicked_1_stencil_34_1597_1598.in1","const_p10000__1597.out"], + ["mult_middle_1606883_1607.in1","const_p883_883$3.out"], + ["umin_demosaicked_1_stencil_34_1597_1598.out","mult_middle_1599n31_1600.in0"], + ["umin_demosaicked_1_stencil_35_1597_1601.out","mult_middle_1602n261_1603.in0"], + ["umin_demosaicked_1_stencil_36_1597_1605.out","mult_middle_1606883_1607.in0"], + ["umin_demosaicked_1_stencil_34_1597_1598.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_35_1597_1601.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_36_1597_1605.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_2":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1059_1062_1063":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1063_1066_1067":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1067_1068_1069":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1068":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1056":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1056$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1056$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1058n31_1059":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1061n261_1062":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1065883_1066":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_7_1056_1057":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_8_1056_1060":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_9_1056_1064":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1058n31_1059.out","add_1059_1062_1063.in0"], + ["mult_middle_1061n261_1062.out","add_1059_1062_1063.in1"], + ["add_1063_1066_1067.in0","add_1059_1062_1063.out"], + ["mult_middle_1065883_1066.out","add_1063_1066_1067.in1"], + ["add_1067_1068_1069.in0","add_1063_1066_1067.out"], + ["const_n22__1068.out","add_1067_1068_1069.in1"], + ["self.out_corrected_stencil","add_1067_1068_1069.out"], + ["mult_middle_1061n261_1062.in1","const_n261_n261.out"], + ["mult_middle_1058n31_1059.in1","const_n31_n31.out"], + ["umin_demosaicked_1_stencil_8_1056_1060.in1","const_p10000__1056$1.out"], + ["umin_demosaicked_1_stencil_9_1056_1064.in1","const_p10000__1056$2.out"], + ["umin_demosaicked_1_stencil_7_1056_1057.in1","const_p10000__1056.out"], + ["mult_middle_1065883_1066.in1","const_p883_883.out"], + ["umin_demosaicked_1_stencil_7_1056_1057.out","mult_middle_1058n31_1059.in0"], + ["umin_demosaicked_1_stencil_8_1056_1060.out","mult_middle_1061n261_1062.in0"], + ["umin_demosaicked_1_stencil_9_1056_1064.out","mult_middle_1065883_1066.in0"], + ["umin_demosaicked_1_stencil_7_1056_1057.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_8_1056_1060.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_9_1056_1064.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_3":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1118_1121_1122":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1122_1125_1126":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1126_1127_1128":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__1127":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__1115":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1115$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1115$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_1117549_1118":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1120n103_1121":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_11247_1125":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_10_1115_1116":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_11_1115_1119":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_12_1115_1123":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1117549_1118.out","add_1118_1121_1122.in0"], + ["mult_middle_1120n103_1121.out","add_1118_1121_1122.in1"], + ["add_1122_1125_1126.in0","add_1118_1121_1122.out"], + ["mult_middle_11247_1125.out","add_1122_1125_1126.in1"], + ["add_1126_1127_1128.in0","add_1122_1125_1126.out"], + ["const_n40__1127.out","add_1126_1127_1128.in1"], + ["self.out_corrected_stencil","add_1126_1127_1128.out"], + ["mult_middle_1120n103_1121.in1","const_n103_n103$1.out"], + ["umin_demosaicked_1_stencil_11_1115_1119.in1","const_p10000__1115$1.out"], + ["umin_demosaicked_1_stencil_12_1115_1123.in1","const_p10000__1115$2.out"], + ["umin_demosaicked_1_stencil_10_1115_1116.in1","const_p10000__1115.out"], + ["mult_middle_1117549_1118.in1","const_p549_549$1.out"], + ["mult_middle_11247_1125.in1","const_p7_7$1.out"], + ["umin_demosaicked_1_stencil_10_1115_1116.out","mult_middle_1117549_1118.in0"], + ["umin_demosaicked_1_stencil_11_1115_1119.out","mult_middle_1120n103_1121.in0"], + ["umin_demosaicked_1_stencil_12_1115_1123.out","mult_middle_11247_1125.in0"], + ["umin_demosaicked_1_stencil_10_1115_1116.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_11_1115_1119.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_12_1115_1123.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_4":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1178_1181_1182":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1182_1185_1186":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1186_1187_1188":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1187":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__1175":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1175$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1175$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_1177n96_1178":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1180373_1181":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_118462_1185":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_13_1175_1176":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_14_1175_1179":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_15_1175_1183":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1177n96_1178.out","add_1178_1181_1182.in0"], + ["mult_middle_1180373_1181.out","add_1178_1181_1182.in1"], + ["add_1182_1185_1186.in0","add_1178_1181_1182.out"], + ["mult_middle_118462_1185.out","add_1182_1185_1186.in1"], + ["add_1186_1187_1188.in0","add_1182_1185_1186.out"], + ["const_n29__1187.out","add_1186_1187_1188.in1"], + ["self.out_corrected_stencil","add_1186_1187_1188.out"], + ["mult_middle_1177n96_1178.in1","const_n96_n96$1.out"], + ["umin_demosaicked_1_stencil_14_1175_1179.in1","const_p10000__1175$1.out"], + ["umin_demosaicked_1_stencil_15_1175_1183.in1","const_p10000__1175$2.out"], + ["umin_demosaicked_1_stencil_13_1175_1176.in1","const_p10000__1175.out"], + ["mult_middle_1180373_1181.in1","const_p373_373$1.out"], + ["mult_middle_118462_1185.in1","const_p62_62$1.out"], + ["umin_demosaicked_1_stencil_13_1175_1176.out","mult_middle_1177n96_1178.in0"], + ["umin_demosaicked_1_stencil_14_1175_1179.out","mult_middle_1180373_1181.in0"], + ["umin_demosaicked_1_stencil_15_1175_1183.out","mult_middle_118462_1185.in0"], + ["umin_demosaicked_1_stencil_13_1175_1176.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_14_1175_1179.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_15_1175_1183.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_5":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1238_1241_1242":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1242_1245_1246":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1246_1247_1248":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1247":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1235":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1235$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1235$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1237n31_1238":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1240n261_1241":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1244883_1245":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_16_1235_1236":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_17_1235_1239":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_18_1235_1243":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1237n31_1238.out","add_1238_1241_1242.in0"], + ["mult_middle_1240n261_1241.out","add_1238_1241_1242.in1"], + ["add_1242_1245_1246.in0","add_1238_1241_1242.out"], + ["mult_middle_1244883_1245.out","add_1242_1245_1246.in1"], + ["add_1246_1247_1248.in0","add_1242_1245_1246.out"], + ["const_n22__1247.out","add_1246_1247_1248.in1"], + ["self.out_corrected_stencil","add_1246_1247_1248.out"], + ["mult_middle_1240n261_1241.in1","const_n261_n261$1.out"], + ["mult_middle_1237n31_1238.in1","const_n31_n31$1.out"], + ["umin_demosaicked_1_stencil_17_1235_1239.in1","const_p10000__1235$1.out"], + ["umin_demosaicked_1_stencil_18_1235_1243.in1","const_p10000__1235$2.out"], + ["umin_demosaicked_1_stencil_16_1235_1236.in1","const_p10000__1235.out"], + ["mult_middle_1244883_1245.in1","const_p883_883$1.out"], + ["umin_demosaicked_1_stencil_16_1235_1236.out","mult_middle_1237n31_1238.in0"], + ["umin_demosaicked_1_stencil_17_1235_1239.out","mult_middle_1240n261_1241.in0"], + ["umin_demosaicked_1_stencil_18_1235_1243.out","mult_middle_1244883_1245.in0"], + ["umin_demosaicked_1_stencil_16_1235_1236.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_17_1235_1239.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_18_1235_1243.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_6":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1298_1301_1302":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1302_1305_1306":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1306_1307_1308":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__1307":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__1295":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1295$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1295$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_1297549_1298":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1300n103_1301":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_13047_1305":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_19_1295_1296":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_20_1295_1299":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_21_1295_1303":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1297549_1298.out","add_1298_1301_1302.in0"], + ["mult_middle_1300n103_1301.out","add_1298_1301_1302.in1"], + ["add_1302_1305_1306.in0","add_1298_1301_1302.out"], + ["mult_middle_13047_1305.out","add_1302_1305_1306.in1"], + ["add_1306_1307_1308.in0","add_1302_1305_1306.out"], + ["const_n40__1307.out","add_1306_1307_1308.in1"], + ["self.out_corrected_stencil","add_1306_1307_1308.out"], + ["mult_middle_1300n103_1301.in1","const_n103_n103$2.out"], + ["umin_demosaicked_1_stencil_20_1295_1299.in1","const_p10000__1295$1.out"], + ["umin_demosaicked_1_stencil_21_1295_1303.in1","const_p10000__1295$2.out"], + ["umin_demosaicked_1_stencil_19_1295_1296.in1","const_p10000__1295.out"], + ["mult_middle_1297549_1298.in1","const_p549_549$2.out"], + ["mult_middle_13047_1305.in1","const_p7_7$2.out"], + ["umin_demosaicked_1_stencil_19_1295_1296.out","mult_middle_1297549_1298.in0"], + ["umin_demosaicked_1_stencil_20_1295_1299.out","mult_middle_1300n103_1301.in0"], + ["umin_demosaicked_1_stencil_21_1295_1303.out","mult_middle_13047_1305.in0"], + ["umin_demosaicked_1_stencil_19_1295_1296.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_20_1295_1299.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_21_1295_1303.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_7":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1358_1361_1362":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1362_1365_1366":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1366_1367_1368":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1367":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__1355":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1355$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1355$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_1357n96_1358":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1360373_1361":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_136462_1365":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_22_1355_1356":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_23_1355_1359":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_24_1355_1363":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1357n96_1358.out","add_1358_1361_1362.in0"], + ["mult_middle_1360373_1361.out","add_1358_1361_1362.in1"], + ["add_1362_1365_1366.in0","add_1358_1361_1362.out"], + ["mult_middle_136462_1365.out","add_1362_1365_1366.in1"], + ["add_1366_1367_1368.in0","add_1362_1365_1366.out"], + ["const_n29__1367.out","add_1366_1367_1368.in1"], + ["self.out_corrected_stencil","add_1366_1367_1368.out"], + ["mult_middle_1357n96_1358.in1","const_n96_n96$2.out"], + ["umin_demosaicked_1_stencil_23_1355_1359.in1","const_p10000__1355$1.out"], + ["umin_demosaicked_1_stencil_24_1355_1363.in1","const_p10000__1355$2.out"], + ["umin_demosaicked_1_stencil_22_1355_1356.in1","const_p10000__1355.out"], + ["mult_middle_1360373_1361.in1","const_p373_373$2.out"], + ["mult_middle_136462_1365.in1","const_p62_62$2.out"], + ["umin_demosaicked_1_stencil_22_1355_1356.out","mult_middle_1357n96_1358.in0"], + ["umin_demosaicked_1_stencil_23_1355_1359.out","mult_middle_1360373_1361.in0"], + ["umin_demosaicked_1_stencil_24_1355_1363.out","mult_middle_136462_1365.in0"], + ["umin_demosaicked_1_stencil_22_1355_1356.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_23_1355_1359.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_24_1355_1363.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_8":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1418_1421_1422":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1422_1425_1426":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1426_1427_1428":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1427":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1415":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1415$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1415$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1417n31_1418":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1420n261_1421":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1424883_1425":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_25_1415_1416":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_26_1415_1419":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_27_1415_1423":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1417n31_1418.out","add_1418_1421_1422.in0"], + ["mult_middle_1420n261_1421.out","add_1418_1421_1422.in1"], + ["add_1422_1425_1426.in0","add_1418_1421_1422.out"], + ["mult_middle_1424883_1425.out","add_1422_1425_1426.in1"], + ["add_1426_1427_1428.in0","add_1422_1425_1426.out"], + ["const_n22__1427.out","add_1426_1427_1428.in1"], + ["self.out_corrected_stencil","add_1426_1427_1428.out"], + ["mult_middle_1420n261_1421.in1","const_n261_n261$2.out"], + ["mult_middle_1417n31_1418.in1","const_n31_n31$2.out"], + ["umin_demosaicked_1_stencil_26_1415_1419.in1","const_p10000__1415$1.out"], + ["umin_demosaicked_1_stencil_27_1415_1423.in1","const_p10000__1415$2.out"], + ["umin_demosaicked_1_stencil_25_1415_1416.in1","const_p10000__1415.out"], + ["mult_middle_1424883_1425.in1","const_p883_883$2.out"], + ["umin_demosaicked_1_stencil_25_1415_1416.out","mult_middle_1417n31_1418.in0"], + ["umin_demosaicked_1_stencil_26_1415_1419.out","mult_middle_1420n261_1421.in0"], + ["umin_demosaicked_1_stencil_27_1415_1423.out","mult_middle_1424883_1425.in0"], + ["umin_demosaicked_1_stencil_25_1415_1416.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_26_1415_1419.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_27_1415_1423.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_9":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1478_1481_1482":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1482_1485_1486":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1486_1487_1488":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__1487":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__1475":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1475$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1475$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_1477549_1478":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1480n103_1481":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_14847_1485":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_28_1475_1476":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_29_1475_1479":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_30_1475_1483":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1477549_1478.out","add_1478_1481_1482.in0"], + ["mult_middle_1480n103_1481.out","add_1478_1481_1482.in1"], + ["add_1482_1485_1486.in0","add_1478_1481_1482.out"], + ["mult_middle_14847_1485.out","add_1482_1485_1486.in1"], + ["add_1486_1487_1488.in0","add_1482_1485_1486.out"], + ["const_n40__1487.out","add_1486_1487_1488.in1"], + ["self.out_corrected_stencil","add_1486_1487_1488.out"], + ["mult_middle_1480n103_1481.in1","const_n103_n103$3.out"], + ["umin_demosaicked_1_stencil_29_1475_1479.in1","const_p10000__1475$1.out"], + ["umin_demosaicked_1_stencil_30_1475_1483.in1","const_p10000__1475$2.out"], + ["umin_demosaicked_1_stencil_28_1475_1476.in1","const_p10000__1475.out"], + ["mult_middle_1477549_1478.in1","const_p549_549$3.out"], + ["mult_middle_14847_1485.in1","const_p7_7$3.out"], + ["umin_demosaicked_1_stencil_28_1475_1476.out","mult_middle_1477549_1478.in0"], + ["umin_demosaicked_1_stencil_29_1475_1479.out","mult_middle_1480n103_1481.in0"], + ["umin_demosaicked_1_stencil_30_1475_1483.out","mult_middle_14847_1485.in0"], + ["umin_demosaicked_1_stencil_28_1475_1476.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_29_1475_1479.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_30_1475_1483.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_curved_stencil":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__3695":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__3693":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_3694_3695_3696":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_1_3693_3694":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_3694_3695_3696.in1","const_p0__3695.out"], + ["smin_corrected_stencil_1_3693_3694.in1","const_p1023__3693.out"], + ["smax_3694_3695_3696.out","rom_curvea0.raddr"], + ["self.out_curved_stencil","rom_curvea0.rdata"], + ["rom_curvea0_ren.out","rom_curvea0.ren"], + ["smin_corrected_stencil_1_3693_3694.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_1_3693_3694.out","smax_3694_3695_3696.in0"] + ] + }, + "hcompute_curved_stencil_1":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__4742":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__4740":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$1":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$1_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_4741_4742_4743":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_2_4740_4741":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_4741_4742_4743.in1","const_p0__4742.out"], + ["smin_corrected_stencil_2_4740_4741.in1","const_p1023__4740.out"], + ["smax_4741_4742_4743.out","rom_curvea0$1.raddr"], + ["self.out_curved_stencil","rom_curvea0$1.rdata"], + ["rom_curvea0$1_ren.out","rom_curvea0$1.ren"], + ["smin_corrected_stencil_2_4740_4741.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_2_4740_4741.out","smax_4741_4742_4743.in0"] + ] + }, + "hcompute_curved_stencil_10":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__14173":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__14171":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$10":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$10_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_14172_14173_14174":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_11_14171_14172":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_14172_14173_14174.in1","const_p0__14173.out"], + ["smin_corrected_stencil_11_14171_14172.in1","const_p1023__14171.out"], + ["smax_14172_14173_14174.out","rom_curvea0$10.raddr"], + ["self.out_curved_stencil","rom_curvea0$10.rdata"], + ["rom_curvea0$10_ren.out","rom_curvea0$10.ren"], + ["smin_corrected_stencil_11_14171_14172.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_11_14171_14172.out","smax_14172_14173_14174.in0"] + ] + }, + "hcompute_curved_stencil_11":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__15222":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__15220":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$11":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$11_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_15221_15222_15223":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_12_15220_15221":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_15221_15222_15223.in1","const_p0__15222.out"], + ["smin_corrected_stencil_12_15220_15221.in1","const_p1023__15220.out"], + ["smax_15221_15222_15223.out","rom_curvea0$11.raddr"], + ["self.out_curved_stencil","rom_curvea0$11.rdata"], + ["rom_curvea0$11_ren.out","rom_curvea0$11.ren"], + ["smin_corrected_stencil_12_15220_15221.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_12_15220_15221.out","smax_15221_15222_15223.in0"] + ] + }, + "hcompute_curved_stencil_2":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__5789":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__5787":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$2":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$2_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_5788_5789_5790":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_3_5787_5788":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_5788_5789_5790.in1","const_p0__5789.out"], + ["smin_corrected_stencil_3_5787_5788.in1","const_p1023__5787.out"], + ["smax_5788_5789_5790.out","rom_curvea0$2.raddr"], + ["self.out_curved_stencil","rom_curvea0$2.rdata"], + ["rom_curvea0$2_ren.out","rom_curvea0$2.ren"], + ["smin_corrected_stencil_3_5787_5788.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_3_5787_5788.out","smax_5788_5789_5790.in0"] + ] + }, + "hcompute_curved_stencil_3":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__6836":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__6834":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$3":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$3_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_6835_6836_6837":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_4_6834_6835":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_6835_6836_6837.in1","const_p0__6836.out"], + ["smin_corrected_stencil_4_6834_6835.in1","const_p1023__6834.out"], + ["smax_6835_6836_6837.out","rom_curvea0$3.raddr"], + ["self.out_curved_stencil","rom_curvea0$3.rdata"], + ["rom_curvea0$3_ren.out","rom_curvea0$3.ren"], + ["smin_corrected_stencil_4_6834_6835.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_4_6834_6835.out","smax_6835_6836_6837.in0"] + ] + }, + "hcompute_curved_stencil_4":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__7884":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__7882":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$4":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$4_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_7883_7884_7885":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_5_7882_7883":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_7883_7884_7885.in1","const_p0__7884.out"], + ["smin_corrected_stencil_5_7882_7883.in1","const_p1023__7882.out"], + ["smax_7883_7884_7885.out","rom_curvea0$4.raddr"], + ["self.out_curved_stencil","rom_curvea0$4.rdata"], + ["rom_curvea0$4_ren.out","rom_curvea0$4.ren"], + ["smin_corrected_stencil_5_7882_7883.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_5_7882_7883.out","smax_7883_7884_7885.in0"] + ] + }, + "hcompute_curved_stencil_5":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__8932":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__8930":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$5":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$5_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_8931_8932_8933":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_6_8930_8931":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_8931_8932_8933.in1","const_p0__8932.out"], + ["smin_corrected_stencil_6_8930_8931.in1","const_p1023__8930.out"], + ["smax_8931_8932_8933.out","rom_curvea0$5.raddr"], + ["self.out_curved_stencil","rom_curvea0$5.rdata"], + ["rom_curvea0$5_ren.out","rom_curvea0$5.ren"], + ["smin_corrected_stencil_6_8930_8931.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_6_8930_8931.out","smax_8931_8932_8933.in0"] + ] + }, + "hcompute_curved_stencil_6":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__9980":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__9978":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$6":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$6_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_9979_9980_9981":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_7_9978_9979":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_9979_9980_9981.in1","const_p0__9980.out"], + ["smin_corrected_stencil_7_9978_9979.in1","const_p1023__9978.out"], + ["smax_9979_9980_9981.out","rom_curvea0$6.raddr"], + ["self.out_curved_stencil","rom_curvea0$6.rdata"], + ["rom_curvea0$6_ren.out","rom_curvea0$6.ren"], + ["smin_corrected_stencil_7_9978_9979.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_7_9978_9979.out","smax_9979_9980_9981.in0"] + ] + }, + "hcompute_curved_stencil_7":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__11028":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__11026":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$7":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$7_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_11027_11028_11029":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_8_11026_11027":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_11027_11028_11029.in1","const_p0__11028.out"], + ["smin_corrected_stencil_8_11026_11027.in1","const_p1023__11026.out"], + ["smax_11027_11028_11029.out","rom_curvea0$7.raddr"], + ["self.out_curved_stencil","rom_curvea0$7.rdata"], + ["rom_curvea0$7_ren.out","rom_curvea0$7.ren"], + ["smin_corrected_stencil_8_11026_11027.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_8_11026_11027.out","smax_11027_11028_11029.in0"] + ] + }, + "hcompute_curved_stencil_8":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__12076":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__12074":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$8":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$8_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_12075_12076_12077":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_9_12074_12075":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_12075_12076_12077.in1","const_p0__12076.out"], + ["smin_corrected_stencil_9_12074_12075.in1","const_p1023__12074.out"], + ["smax_12075_12076_12077.out","rom_curvea0$8.raddr"], + ["self.out_curved_stencil","rom_curvea0$8.rdata"], + ["rom_curvea0$8_ren.out","rom_curvea0$8.ren"], + ["smin_corrected_stencil_9_12074_12075.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_9_12074_12075.out","smax_12075_12076_12077.in0"] + ] + }, + "hcompute_curved_stencil_9":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__13124":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__13122":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$9":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$9_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_13123_13124_13125":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_10_13122_13123":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_13123_13124_13125.in1","const_p0__13124.out"], + ["smin_corrected_stencil_10_13122_13123.in1","const_p1023__13122.out"], + ["smax_13123_13124_13125.out","rom_curvea0$9.raddr"], + ["self.out_curved_stencil","rom_curvea0$9.rdata"], + ["rom_curvea0$9_ren.out","rom_curvea0$9.ren"], + ["smin_corrected_stencil_10_13122_13123.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_10_13122_13123.out","smax_13123_13124_13125.in0"] + ] + }, + "hcompute_demosaicked_1_stencil":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_gr_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_1":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_gr_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_10":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_gb_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_11":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_gb_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_2":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_gr_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_3":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_b_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_b_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_4":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_b_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_5":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_b_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_6":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_r_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_7":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_r_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_8":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_r_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_9":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_gb_stencil.0"] + ] + }, + "hcompute_denoised_1_stencil":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377.out","umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376.out","umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377.in1"] + ] + }, + "hcompute_denoised_1_stencil_1":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400.out","umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399.out","umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400.in1"] + ] + }, + "hcompute_denoised_1_stencil_2":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424.out","umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423.out","umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424.in1"] + ] + }, + "hcompute_denoised_1_stencil_3":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448.out","umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447.out","umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448.in1"] + ] + }, + "hcompute_g_b_stencil":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_1_g_gb_stencil_2_505":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_1_g_gr_stencil_2_506":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_1_g_gb_stencil_2_508":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_1_g_gr_stencil_2_511":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__509":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__509$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_508_509_510":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_511_509_512":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_507_510_512":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_505_506_507":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_1_g_gb_stencil_2_505.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_1_g_gb_stencil_2_505.in1"], + ["ult_505_506_507.in0","absd_g_gb_stencil_1_g_gb_stencil_2_505.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_1_g_gr_stencil_2_506.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_1_g_gr_stencil_2_506.in1"], + ["ult_505_506_507.in1","absd_g_gr_stencil_1_g_gr_stencil_2_506.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_1_g_gb_stencil_2_508.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_1_g_gb_stencil_2_508.in1"], + ["lshr_508_509_510.in0","add_g_gb_stencil_1_g_gb_stencil_2_508.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_1_g_gr_stencil_2_511.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_1_g_gr_stencil_2_511.in1"], + ["lshr_511_509_512.in0","add_g_gr_stencil_1_g_gr_stencil_2_511.out"], + ["lshr_511_509_512.in1","const_p1__509$1.out"], + ["lshr_508_509_510.in1","const_p1__509.out"], + ["mux_507_510_512.in1","lshr_508_509_510.out"], + ["mux_507_510_512.in0","lshr_511_509_512.out"], + ["self.out_g_b_stencil","mux_507_510_512.out"], + ["ult_505_506_507.out","mux_507_510_512.sel"] + ] + }, + "hcompute_g_gb_stencil":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_r_stencil":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_4_g_gb_stencil_5_612":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_4_g_gr_stencil_5_611":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_4_g_gb_stencil_5_617":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_4_g_gr_stencil_5_614":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__615":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__615$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_614_615_616":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_617_615_618":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_613_616_618":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_611_612_613":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_4_g_gb_stencil_5_612.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_4_g_gb_stencil_5_612.in1"], + ["ult_611_612_613.in1","absd_g_gb_stencil_4_g_gb_stencil_5_612.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_4_g_gr_stencil_5_611.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_4_g_gr_stencil_5_611.in1"], + ["ult_611_612_613.in0","absd_g_gr_stencil_4_g_gr_stencil_5_611.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_4_g_gb_stencil_5_617.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_4_g_gb_stencil_5_617.in1"], + ["lshr_617_615_618.in0","add_g_gb_stencil_4_g_gb_stencil_5_617.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_4_g_gr_stencil_5_614.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_4_g_gr_stencil_5_614.in1"], + ["lshr_614_615_616.in0","add_g_gr_stencil_4_g_gr_stencil_5_614.out"], + ["lshr_617_615_618.in1","const_p1__615$1.out"], + ["lshr_614_615_616.in1","const_p1__615.out"], + ["mux_613_616_618.in1","lshr_614_615_616.out"], + ["mux_613_616_618.in0","lshr_617_615_618.out"], + ["self.out_g_r_stencil","mux_613_616_618.out"], + ["ult_611_612_613.out","mux_613_616_618.sel"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_10":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_11":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_4":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_5":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_6":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_7":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_8":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_9":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_10":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_11":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_4":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_5":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_6":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_7":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_8":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_9":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_r_b_stencil":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_1_r_r_stencil_2_753":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_3_r_r_stencil_4_754":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_758_759":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_764_765":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_2_g_r_stencil_3_760":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_4_g_r_stencil_5_766":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_1_r_r_stencil_2_756":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_3_r_r_stencil_4_763":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__757":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__757$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__757$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__757$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_756_757_758":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_760_757_761":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_763_757_764":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_766_757_767":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_755_762_768":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_759_761_762":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_765_767_768":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_753_754_755":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.0","absd_r_r_stencil_1_r_r_stencil_2_753.in0"], + ["self.in2_r_r_stencil.1","absd_r_r_stencil_1_r_r_stencil_2_753.in1"], + ["ult_753_754_755.in0","absd_r_r_stencil_1_r_r_stencil_2_753.out"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_3_r_r_stencil_4_754.in0"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_3_r_r_stencil_4_754.in1"], + ["ult_753_754_755.in1","absd_r_r_stencil_3_r_r_stencil_4_754.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_758_759.in0"], + ["lshr_756_757_758.out","add_g_b_stencil_9_758_759.in1"], + ["sub_759_761_762.in0","add_g_b_stencil_9_758_759.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_764_765.in0"], + ["lshr_763_757_764.out","add_g_b_stencil_9_764_765.in1"], + ["sub_765_767_768.in0","add_g_b_stencil_9_764_765.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_2_g_r_stencil_3_760.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_2_g_r_stencil_3_760.in1"], + ["lshr_760_757_761.in0","add_g_r_stencil_2_g_r_stencil_3_760.out"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_4_g_r_stencil_5_766.in0"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_4_g_r_stencil_5_766.in1"], + ["lshr_766_757_767.in0","add_g_r_stencil_4_g_r_stencil_5_766.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_1_r_r_stencil_2_756.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_1_r_r_stencil_2_756.in1"], + ["lshr_756_757_758.in0","add_r_r_stencil_1_r_r_stencil_2_756.out"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_3_r_r_stencil_4_763.in0"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_3_r_r_stencil_4_763.in1"], + ["lshr_763_757_764.in0","add_r_r_stencil_3_r_r_stencil_4_763.out"], + ["lshr_760_757_761.in1","const_p1__757$1.out"], + ["lshr_763_757_764.in1","const_p1__757$2.out"], + ["lshr_766_757_767.in1","const_p1__757$3.out"], + ["lshr_756_757_758.in1","const_p1__757.out"], + ["sub_759_761_762.in1","lshr_760_757_761.out"], + ["sub_765_767_768.in1","lshr_766_757_767.out"], + ["sub_765_767_768.out","mux_755_762_768.in0"], + ["sub_759_761_762.out","mux_755_762_768.in1"], + ["self.out_r_b_stencil","mux_755_762_768.out"], + ["ult_753_754_755.out","mux_755_762_768.sel"] + ] + }, + "hcompute_r_gb_stencil":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gb_stencil_6_815_816":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_6_g_r_stencil_7_817":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_5_r_r_stencil_6_813":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__814":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__814$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_813_814_815":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_817_814_818":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_816_818_819":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_6_815_816.in0"], + ["lshr_813_814_815.out","add_g_gb_stencil_6_815_816.in1"], + ["sub_816_818_819.in0","add_g_gb_stencil_6_815_816.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_6_g_r_stencil_7_817.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_6_g_r_stencil_7_817.in1"], + ["lshr_817_814_818.in0","add_g_r_stencil_6_g_r_stencil_7_817.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_5_r_r_stencil_6_813.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_5_r_r_stencil_6_813.in1"], + ["lshr_813_814_815.in0","add_r_r_stencil_5_r_r_stencil_6_813.out"], + ["lshr_817_814_818.in1","const_p1__814$1.out"], + ["lshr_813_814_815.in1","const_p1__814.out"], + ["sub_816_818_819.in1","lshr_817_814_818.out"], + ["sub_816_818_819.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gr_stencil":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gr_stencil_6_843_844":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_8_g_r_stencil_9_845":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_7_r_r_stencil_8_841":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__842":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__842$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_841_842_843":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_845_842_846":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_844_846_847":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_6_843_844.in0"], + ["lshr_841_842_843.out","add_g_gr_stencil_6_843_844.in1"], + ["sub_844_846_847.in0","add_g_gr_stencil_6_843_844.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_8_g_r_stencil_9_845.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_8_g_r_stencil_9_845.in1"], + ["lshr_845_842_846.in0","add_g_r_stencil_8_g_r_stencil_9_845.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_7_r_r_stencil_8_841.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_7_r_r_stencil_8_841.in1"], + ["lshr_841_842_843.in0","add_r_r_stencil_7_r_r_stencil_8_841.out"], + ["lshr_845_842_846.in1","const_p1__842$1.out"], + ["lshr_841_842_843.in1","const_p1__842.out"], + ["sub_844_846_847.in1","lshr_845_842_846.out"], + ["sub_844_846_847.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_r_stencil":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/camera_pipeline_2x2_unroll_compute.json b/coreir_compute/camera_pipeline_2x2_unroll_compute.json new file mode 100644 index 000000000..55bfefef8 --- /dev/null +++ b/coreir_compute/camera_pipeline_2x2_unroll_compute.json @@ -0,0 +1,4968 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_b_b_stencil":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_b_stencil_1":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_b_stencil_2":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_b_stencil_3":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_gb_stencil":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_1_b_b_stencil_2_775":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_1_g_b_stencil_2_779":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_9_777_778":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__776":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__776$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_775_776_777":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_779_776_780":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_778_780_781":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_1_b_b_stencil_2_775.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_1_b_b_stencil_2_775.in1"], + ["lshr_775_776_777.in0","add_b_b_stencil_1_b_b_stencil_2_775.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_1_g_b_stencil_2_779.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_1_g_b_stencil_2_779.in1"], + ["lshr_779_776_780.in0","add_g_b_stencil_1_g_b_stencil_2_779.out"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_9_777_778.in0"], + ["lshr_775_776_777.out","add_g_gb_stencil_9_777_778.in1"], + ["sub_778_780_781.in0","add_g_gb_stencil_9_777_778.out"], + ["lshr_779_776_780.in1","const_p1__776$1.out"], + ["lshr_775_776_777.in1","const_p1__776.out"], + ["sub_778_780_781.in1","lshr_779_776_780.out"], + ["sub_778_780_781.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gb_stencil_1":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_3_b_b_stencil_4_805":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_3_g_b_stencil_4_809":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_10_807_808":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__806":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__806$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_805_806_807":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_809_806_810":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_808_810_811":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_3_b_b_stencil_4_805.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_3_b_b_stencil_4_805.in1"], + ["lshr_805_806_807.in0","add_b_b_stencil_3_b_b_stencil_4_805.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_3_g_b_stencil_4_809.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_3_g_b_stencil_4_809.in1"], + ["lshr_809_806_810.in0","add_g_b_stencil_3_g_b_stencil_4_809.out"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_10_807_808.in0"], + ["lshr_805_806_807.out","add_g_gb_stencil_10_807_808.in1"], + ["sub_808_810_811.in0","add_g_gb_stencil_10_807_808.out"], + ["lshr_809_806_810.in1","const_p1__806$1.out"], + ["lshr_805_806_807.in1","const_p1__806.out"], + ["sub_808_810_811.in1","lshr_809_806_810.out"], + ["sub_808_810_811.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gb_stencil_2":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_5_b_b_stencil_6_836":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_5_g_b_stencil_6_840":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_11_838_839":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__837":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__837$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_836_837_838":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_840_837_841":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_839_841_842":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_5_b_b_stencil_6_836.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_5_b_b_stencil_6_836.in1"], + ["lshr_836_837_838.in0","add_b_b_stencil_5_b_b_stencil_6_836.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_5_g_b_stencil_6_840.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_5_g_b_stencil_6_840.in1"], + ["lshr_840_837_841.in0","add_g_b_stencil_5_g_b_stencil_6_840.out"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_11_838_839.in0"], + ["lshr_836_837_838.out","add_g_gb_stencil_11_838_839.in1"], + ["sub_839_841_842.in0","add_g_gb_stencil_11_838_839.out"], + ["lshr_840_837_841.in1","const_p1__837$1.out"], + ["lshr_836_837_838.in1","const_p1__837.out"], + ["sub_839_841_842.in1","lshr_840_837_841.out"], + ["sub_839_841_842.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gb_stencil_3":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_7_b_b_stencil_8_867":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_7_g_b_stencil_8_871":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_12_869_870":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__868":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__868$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_867_868_869":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_871_868_872":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_870_872_873":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_7_b_b_stencil_8_867.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_7_b_b_stencil_8_867.in1"], + ["lshr_867_868_869.in0","add_b_b_stencil_7_b_b_stencil_8_867.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_7_g_b_stencil_8_871.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_7_g_b_stencil_8_871.in1"], + ["lshr_871_868_872.in0","add_g_b_stencil_7_g_b_stencil_8_871.out"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_12_869_870.in0"], + ["lshr_867_868_869.out","add_g_gb_stencil_12_869_870.in1"], + ["sub_870_872_873.in0","add_g_gb_stencil_12_869_870.out"], + ["lshr_871_868_872.in1","const_p1__868$1.out"], + ["lshr_867_868_869.in1","const_p1__868.out"], + ["sub_870_872_873.in1","lshr_871_868_872.out"], + ["sub_870_872_873.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gr_stencil":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_9_b_b_stencil_10_899":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_g_b_stencil_10_903":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_9_901_902":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__900":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__900$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_899_900_901":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_903_900_904":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_902_904_905":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.1","add_b_b_stencil_9_b_b_stencil_10_899.in0"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_9_b_b_stencil_10_899.in1"], + ["lshr_899_900_901.in0","add_b_b_stencil_9_b_b_stencil_10_899.out"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_9_g_b_stencil_10_903.in0"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_9_g_b_stencil_10_903.in1"], + ["lshr_903_900_904.in0","add_g_b_stencil_9_g_b_stencil_10_903.out"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_9_901_902.in0"], + ["lshr_899_900_901.out","add_g_gr_stencil_9_901_902.in1"], + ["sub_902_904_905.in0","add_g_gr_stencil_9_901_902.out"], + ["lshr_903_900_904.in1","const_p1__900$1.out"], + ["lshr_899_900_901.in1","const_p1__900.out"], + ["sub_902_904_905.in1","lshr_903_900_904.out"], + ["sub_902_904_905.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_gr_stencil_1":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_11_b_b_stencil_12_929":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_11_g_b_stencil_12_933":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_10_931_932":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__930":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__930$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_929_930_931":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_933_930_934":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_932_934_935":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_11_b_b_stencil_12_929.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_11_b_b_stencil_12_929.in1"], + ["lshr_929_930_931.in0","add_b_b_stencil_11_b_b_stencil_12_929.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_11_g_b_stencil_12_933.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_11_g_b_stencil_12_933.in1"], + ["lshr_933_930_934.in0","add_g_b_stencil_11_g_b_stencil_12_933.out"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_10_931_932.in0"], + ["lshr_929_930_931.out","add_g_gr_stencil_10_931_932.in1"], + ["sub_932_934_935.in0","add_g_gr_stencil_10_931_932.out"], + ["lshr_933_930_934.in1","const_p1__930$1.out"], + ["lshr_929_930_931.in1","const_p1__930.out"], + ["sub_932_934_935.in1","lshr_933_930_934.out"], + ["sub_932_934_935.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_gr_stencil_2":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_13_b_b_stencil_14_960":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_13_g_b_stencil_14_964":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_11_962_963":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__961":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__961$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_960_961_962":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_964_961_965":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_963_965_966":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_13_b_b_stencil_14_960.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_13_b_b_stencil_14_960.in1"], + ["lshr_960_961_962.in0","add_b_b_stencil_13_b_b_stencil_14_960.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_13_g_b_stencil_14_964.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_13_g_b_stencil_14_964.in1"], + ["lshr_964_961_965.in0","add_g_b_stencil_13_g_b_stencil_14_964.out"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_11_962_963.in0"], + ["lshr_960_961_962.out","add_g_gr_stencil_11_962_963.in1"], + ["sub_963_965_966.in0","add_g_gr_stencil_11_962_963.out"], + ["lshr_964_961_965.in1","const_p1__961$1.out"], + ["lshr_960_961_962.in1","const_p1__961.out"], + ["sub_963_965_966.in1","lshr_964_961_965.out"], + ["sub_963_965_966.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_gr_stencil_3":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_15_b_b_stencil_16_991":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_15_g_b_stencil_16_995":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_12_993_994":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__992":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__992$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_991_992_993":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_995_992_996":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_994_996_997":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_15_b_b_stencil_16_991.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_15_b_b_stencil_16_991.in1"], + ["lshr_991_992_993.in0","add_b_b_stencil_15_b_b_stencil_16_991.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_15_g_b_stencil_16_995.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_15_g_b_stencil_16_995.in1"], + ["lshr_995_992_996.in0","add_g_b_stencil_15_g_b_stencil_16_995.out"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_12_993_994.in0"], + ["lshr_991_992_993.out","add_g_gr_stencil_12_993_994.in1"], + ["sub_994_996_997.in0","add_g_gr_stencil_12_993_994.out"], + ["lshr_995_992_996.in1","const_p1__992$1.out"], + ["lshr_991_992_993.in1","const_p1__992.out"], + ["sub_994_996_997.in1","lshr_995_992_996.out"], + ["sub_994_996_997.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_r_stencil":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_17_b_b_stencil_18_1249":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_19_b_b_stencil_20_1250":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_17_b_b_stencil_18_1252":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_19_b_b_stencil_20_1259":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_17_g_b_stencil_18_1256":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_19_g_b_stencil_20_1262":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_1254_1255":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_1260_1261":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1253":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1253$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1253$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1253$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1252_1253_1254":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1256_1253_1257":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1259_1253_1260":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1262_1253_1263":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1251_1258_1264":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1255_1257_1258":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1261_1263_1264":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1249_1250_1251":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_17_b_b_stencil_18_1249.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_17_b_b_stencil_18_1249.in1"], + ["ult_1249_1250_1251.in0","absd_b_b_stencil_17_b_b_stencil_18_1249.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_19_b_b_stencil_20_1250.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_19_b_b_stencil_20_1250.in1"], + ["ult_1249_1250_1251.in1","absd_b_b_stencil_19_b_b_stencil_20_1250.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_17_b_b_stencil_18_1252.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_17_b_b_stencil_18_1252.in1"], + ["lshr_1252_1253_1254.in0","add_b_b_stencil_17_b_b_stencil_18_1252.out"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_19_b_b_stencil_20_1259.in0"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_19_b_b_stencil_20_1259.in1"], + ["lshr_1259_1253_1260.in0","add_b_b_stencil_19_b_b_stencil_20_1259.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_17_g_b_stencil_18_1256.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_17_g_b_stencil_18_1256.in1"], + ["lshr_1256_1253_1257.in0","add_g_b_stencil_17_g_b_stencil_18_1256.out"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_19_g_b_stencil_20_1262.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_19_g_b_stencil_20_1262.in1"], + ["lshr_1262_1253_1263.in0","add_g_b_stencil_19_g_b_stencil_20_1262.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_1254_1255.in0"], + ["lshr_1252_1253_1254.out","add_g_r_stencil_1_1254_1255.in1"], + ["sub_1255_1257_1258.in0","add_g_r_stencil_1_1254_1255.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_1260_1261.in0"], + ["lshr_1259_1253_1260.out","add_g_r_stencil_1_1260_1261.in1"], + ["sub_1261_1263_1264.in0","add_g_r_stencil_1_1260_1261.out"], + ["lshr_1256_1253_1257.in1","const_p1__1253$1.out"], + ["lshr_1259_1253_1260.in1","const_p1__1253$2.out"], + ["lshr_1262_1253_1263.in1","const_p1__1253$3.out"], + ["lshr_1252_1253_1254.in1","const_p1__1253.out"], + ["sub_1255_1257_1258.in1","lshr_1256_1253_1257.out"], + ["sub_1261_1263_1264.in1","lshr_1262_1253_1263.out"], + ["sub_1261_1263_1264.out","mux_1251_1258_1264.in0"], + ["sub_1255_1257_1258.out","mux_1251_1258_1264.in1"], + ["self.out_b_r_stencil","mux_1251_1258_1264.out"], + ["ult_1249_1250_1251.out","mux_1251_1258_1264.sel"] + ] + }, + "hcompute_b_r_stencil_1":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_21_b_b_stencil_22_1329":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_23_b_b_stencil_24_1330":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_21_b_b_stencil_22_1332":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_23_b_b_stencil_24_1339":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_21_g_b_stencil_22_1336":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_23_g_b_stencil_24_1342":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_2_1334_1335":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_2_1340_1341":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1333":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1333$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1333$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1333$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1332_1333_1334":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1336_1333_1337":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1339_1333_1340":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1342_1333_1343":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1331_1338_1344":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1335_1337_1338":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1341_1343_1344":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1329_1330_1331":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_21_b_b_stencil_22_1329.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_21_b_b_stencil_22_1329.in1"], + ["ult_1329_1330_1331.in0","absd_b_b_stencil_21_b_b_stencil_22_1329.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_23_b_b_stencil_24_1330.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_23_b_b_stencil_24_1330.in1"], + ["ult_1329_1330_1331.in1","absd_b_b_stencil_23_b_b_stencil_24_1330.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_21_b_b_stencil_22_1332.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_21_b_b_stencil_22_1332.in1"], + ["lshr_1332_1333_1334.in0","add_b_b_stencil_21_b_b_stencil_22_1332.out"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_23_b_b_stencil_24_1339.in0"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_23_b_b_stencil_24_1339.in1"], + ["lshr_1339_1333_1340.in0","add_b_b_stencil_23_b_b_stencil_24_1339.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_21_g_b_stencil_22_1336.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_21_g_b_stencil_22_1336.in1"], + ["lshr_1336_1333_1337.in0","add_g_b_stencil_21_g_b_stencil_22_1336.out"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_23_g_b_stencil_24_1342.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_23_g_b_stencil_24_1342.in1"], + ["lshr_1342_1333_1343.in0","add_g_b_stencil_23_g_b_stencil_24_1342.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_2_1334_1335.in0"], + ["lshr_1332_1333_1334.out","add_g_r_stencil_2_1334_1335.in1"], + ["sub_1335_1337_1338.in0","add_g_r_stencil_2_1334_1335.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_2_1340_1341.in0"], + ["lshr_1339_1333_1340.out","add_g_r_stencil_2_1340_1341.in1"], + ["sub_1341_1343_1344.in0","add_g_r_stencil_2_1340_1341.out"], + ["lshr_1336_1333_1337.in1","const_p1__1333$1.out"], + ["lshr_1339_1333_1340.in1","const_p1__1333$2.out"], + ["lshr_1342_1333_1343.in1","const_p1__1333$3.out"], + ["lshr_1332_1333_1334.in1","const_p1__1333.out"], + ["sub_1335_1337_1338.in1","lshr_1336_1333_1337.out"], + ["sub_1341_1343_1344.in1","lshr_1342_1333_1343.out"], + ["sub_1341_1343_1344.out","mux_1331_1338_1344.in0"], + ["sub_1335_1337_1338.out","mux_1331_1338_1344.in1"], + ["self.out_b_r_stencil","mux_1331_1338_1344.out"], + ["ult_1329_1330_1331.out","mux_1331_1338_1344.sel"] + ] + }, + "hcompute_b_r_stencil_2":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_25_b_b_stencil_26_1410":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_27_b_b_stencil_28_1411":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_25_b_b_stencil_26_1413":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_27_b_b_stencil_28_1420":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_25_g_b_stencil_26_1417":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_27_g_b_stencil_28_1423":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_3_1415_1416":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_3_1421_1422":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1414":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1414$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1414$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1414$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1413_1414_1415":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1417_1414_1418":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1420_1414_1421":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1423_1414_1424":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1412_1419_1425":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1416_1418_1419":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1422_1424_1425":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1410_1411_1412":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_25_b_b_stencil_26_1410.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_25_b_b_stencil_26_1410.in1"], + ["ult_1410_1411_1412.in0","absd_b_b_stencil_25_b_b_stencil_26_1410.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_27_b_b_stencil_28_1411.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_27_b_b_stencil_28_1411.in1"], + ["ult_1410_1411_1412.in1","absd_b_b_stencil_27_b_b_stencil_28_1411.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_25_b_b_stencil_26_1413.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_25_b_b_stencil_26_1413.in1"], + ["lshr_1413_1414_1415.in0","add_b_b_stencil_25_b_b_stencil_26_1413.out"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_27_b_b_stencil_28_1420.in0"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_27_b_b_stencil_28_1420.in1"], + ["lshr_1420_1414_1421.in0","add_b_b_stencil_27_b_b_stencil_28_1420.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_25_g_b_stencil_26_1417.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_25_g_b_stencil_26_1417.in1"], + ["lshr_1417_1414_1418.in0","add_g_b_stencil_25_g_b_stencil_26_1417.out"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_27_g_b_stencil_28_1423.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_27_g_b_stencil_28_1423.in1"], + ["lshr_1423_1414_1424.in0","add_g_b_stencil_27_g_b_stencil_28_1423.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_3_1415_1416.in0"], + ["lshr_1413_1414_1415.out","add_g_r_stencil_3_1415_1416.in1"], + ["sub_1416_1418_1419.in0","add_g_r_stencil_3_1415_1416.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_3_1421_1422.in0"], + ["lshr_1420_1414_1421.out","add_g_r_stencil_3_1421_1422.in1"], + ["sub_1422_1424_1425.in0","add_g_r_stencil_3_1421_1422.out"], + ["lshr_1417_1414_1418.in1","const_p1__1414$1.out"], + ["lshr_1420_1414_1421.in1","const_p1__1414$2.out"], + ["lshr_1423_1414_1424.in1","const_p1__1414$3.out"], + ["lshr_1413_1414_1415.in1","const_p1__1414.out"], + ["sub_1416_1418_1419.in1","lshr_1417_1414_1418.out"], + ["sub_1422_1424_1425.in1","lshr_1423_1414_1424.out"], + ["sub_1422_1424_1425.out","mux_1412_1419_1425.in0"], + ["sub_1416_1418_1419.out","mux_1412_1419_1425.in1"], + ["self.out_b_r_stencil","mux_1412_1419_1425.out"], + ["ult_1410_1411_1412.out","mux_1412_1419_1425.sel"] + ] + }, + "hcompute_b_r_stencil_3":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_29_b_b_stencil_30_1491":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_31_b_b_stencil_32_1492":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_29_b_b_stencil_30_1494":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_31_b_b_stencil_32_1501":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_29_g_b_stencil_30_1498":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_31_g_b_stencil_32_1504":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_4_1496_1497":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_4_1502_1503":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1495":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1495$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1495$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1495$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1494_1495_1496":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1498_1495_1499":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1501_1495_1502":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1504_1495_1505":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1493_1500_1506":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1497_1499_1500":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1503_1505_1506":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1491_1492_1493":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_29_b_b_stencil_30_1491.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_29_b_b_stencil_30_1491.in1"], + ["ult_1491_1492_1493.in0","absd_b_b_stencil_29_b_b_stencil_30_1491.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_31_b_b_stencil_32_1492.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_31_b_b_stencil_32_1492.in1"], + ["ult_1491_1492_1493.in1","absd_b_b_stencil_31_b_b_stencil_32_1492.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_29_b_b_stencil_30_1494.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_29_b_b_stencil_30_1494.in1"], + ["lshr_1494_1495_1496.in0","add_b_b_stencil_29_b_b_stencil_30_1494.out"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_31_b_b_stencil_32_1501.in0"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_31_b_b_stencil_32_1501.in1"], + ["lshr_1501_1495_1502.in0","add_b_b_stencil_31_b_b_stencil_32_1501.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_29_g_b_stencil_30_1498.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_29_g_b_stencil_30_1498.in1"], + ["lshr_1498_1495_1499.in0","add_g_b_stencil_29_g_b_stencil_30_1498.out"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_31_g_b_stencil_32_1504.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_31_g_b_stencil_32_1504.in1"], + ["lshr_1504_1495_1505.in0","add_g_b_stencil_31_g_b_stencil_32_1504.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_4_1496_1497.in0"], + ["lshr_1494_1495_1496.out","add_g_r_stencil_4_1496_1497.in1"], + ["sub_1497_1499_1500.in0","add_g_r_stencil_4_1496_1497.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_4_1502_1503.in0"], + ["lshr_1501_1495_1502.out","add_g_r_stencil_4_1502_1503.in1"], + ["sub_1503_1505_1506.in0","add_g_r_stencil_4_1502_1503.out"], + ["lshr_1498_1495_1499.in1","const_p1__1495$1.out"], + ["lshr_1501_1495_1502.in1","const_p1__1495$2.out"], + ["lshr_1504_1495_1505.in1","const_p1__1495$3.out"], + ["lshr_1494_1495_1496.in1","const_p1__1495.out"], + ["sub_1497_1499_1500.in1","lshr_1498_1495_1499.out"], + ["sub_1503_1505_1506.in1","lshr_1504_1495_1505.out"], + ["sub_1503_1505_1506.out","mux_1493_1500_1506.in0"], + ["sub_1497_1499_1500.out","mux_1493_1500_1506.in1"], + ["self.out_b_r_stencil","mux_1493_1500_1506.out"], + ["ult_1491_1492_1493.out","mux_1493_1500_1506.sel"] + ] + }, + "hcompute_corrected_stencil":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2231_2234_2235":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2235_2238_2239":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2239_2240_2241":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__2240":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__2228":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2228$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2228$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_2230549_2231":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2233n103_2234":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_22377_2238":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_1_2228_2229":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_2_2228_2232":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_3_2228_2236":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2230549_2231.out","add_2231_2234_2235.in0"], + ["mult_middle_2233n103_2234.out","add_2231_2234_2235.in1"], + ["add_2235_2238_2239.in0","add_2231_2234_2235.out"], + ["mult_middle_22377_2238.out","add_2235_2238_2239.in1"], + ["add_2239_2240_2241.in0","add_2235_2238_2239.out"], + ["const_n40__2240.out","add_2239_2240_2241.in1"], + ["self.out_corrected_stencil","add_2239_2240_2241.out"], + ["mult_middle_2233n103_2234.in1","const_n103_n103.out"], + ["umin_demosaicked_1_stencil_2_2228_2232.in1","const_p10000__2228$1.out"], + ["umin_demosaicked_1_stencil_3_2228_2236.in1","const_p10000__2228$2.out"], + ["umin_demosaicked_1_stencil_1_2228_2229.in1","const_p10000__2228.out"], + ["mult_middle_2230549_2231.in1","const_p549_549.out"], + ["mult_middle_22377_2238.in1","const_p7_7.out"], + ["umin_demosaicked_1_stencil_1_2228_2229.out","mult_middle_2230549_2231.in0"], + ["umin_demosaicked_1_stencil_2_2228_2232.out","mult_middle_2233n103_2234.in0"], + ["umin_demosaicked_1_stencil_3_2228_2236.out","mult_middle_22377_2238.in0"], + ["umin_demosaicked_1_stencil_1_2228_2229.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_2_2228_2232.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_3_2228_2236.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_1":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2290_2293_2294":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2294_2297_2298":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2298_2299_2300":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__2299":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__2287":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2287$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2287$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_2289n96_2290":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2292373_2293":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_229662_2297":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_4_2287_2288":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_5_2287_2291":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_6_2287_2295":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2289n96_2290.out","add_2290_2293_2294.in0"], + ["mult_middle_2292373_2293.out","add_2290_2293_2294.in1"], + ["add_2294_2297_2298.in0","add_2290_2293_2294.out"], + ["mult_middle_229662_2297.out","add_2294_2297_2298.in1"], + ["add_2298_2299_2300.in0","add_2294_2297_2298.out"], + ["const_n29__2299.out","add_2298_2299_2300.in1"], + ["self.out_corrected_stencil","add_2298_2299_2300.out"], + ["mult_middle_2289n96_2290.in1","const_n96_n96.out"], + ["umin_demosaicked_1_stencil_5_2287_2291.in1","const_p10000__2287$1.out"], + ["umin_demosaicked_1_stencil_6_2287_2295.in1","const_p10000__2287$2.out"], + ["umin_demosaicked_1_stencil_4_2287_2288.in1","const_p10000__2287.out"], + ["mult_middle_2292373_2293.in1","const_p373_373.out"], + ["mult_middle_229662_2297.in1","const_p62_62.out"], + ["umin_demosaicked_1_stencil_4_2287_2288.out","mult_middle_2289n96_2290.in0"], + ["umin_demosaicked_1_stencil_5_2287_2291.out","mult_middle_2292373_2293.in0"], + ["umin_demosaicked_1_stencil_6_2287_2295.out","mult_middle_229662_2297.in0"], + ["umin_demosaicked_1_stencil_4_2287_2288.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_5_2287_2291.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_6_2287_2295.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_10":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2829_2832_2833":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2833_2836_2837":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2837_2838_2839":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__2838":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__2826":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2826$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2826$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_2828n96_2829":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2831373_2832":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_283562_2836":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_31_2826_2827":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_32_2826_2830":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_33_2826_2834":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2828n96_2829.out","add_2829_2832_2833.in0"], + ["mult_middle_2831373_2832.out","add_2829_2832_2833.in1"], + ["add_2833_2836_2837.in0","add_2829_2832_2833.out"], + ["mult_middle_283562_2836.out","add_2833_2836_2837.in1"], + ["add_2837_2838_2839.in0","add_2833_2836_2837.out"], + ["const_n29__2838.out","add_2837_2838_2839.in1"], + ["self.out_corrected_stencil","add_2837_2838_2839.out"], + ["mult_middle_2828n96_2829.in1","const_n96_n96$3.out"], + ["umin_demosaicked_1_stencil_32_2826_2830.in1","const_p10000__2826$1.out"], + ["umin_demosaicked_1_stencil_33_2826_2834.in1","const_p10000__2826$2.out"], + ["umin_demosaicked_1_stencil_31_2826_2827.in1","const_p10000__2826.out"], + ["mult_middle_2831373_2832.in1","const_p373_373$3.out"], + ["mult_middle_283562_2836.in1","const_p62_62$3.out"], + ["umin_demosaicked_1_stencil_31_2826_2827.out","mult_middle_2828n96_2829.in0"], + ["umin_demosaicked_1_stencil_32_2826_2830.out","mult_middle_2831373_2832.in0"], + ["umin_demosaicked_1_stencil_33_2826_2834.out","mult_middle_283562_2836.in0"], + ["umin_demosaicked_1_stencil_31_2826_2827.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_32_2826_2830.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_33_2826_2834.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_11":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2890_2893_2894":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2894_2897_2898":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2898_2899_2900":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__2899":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__2887":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2887$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2887$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_2889n31_2890":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2892n261_2893":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2896883_2897":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_34_2887_2888":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_35_2887_2891":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_36_2887_2895":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2889n31_2890.out","add_2890_2893_2894.in0"], + ["mult_middle_2892n261_2893.out","add_2890_2893_2894.in1"], + ["add_2894_2897_2898.in0","add_2890_2893_2894.out"], + ["mult_middle_2896883_2897.out","add_2894_2897_2898.in1"], + ["add_2898_2899_2900.in0","add_2894_2897_2898.out"], + ["const_n22__2899.out","add_2898_2899_2900.in1"], + ["self.out_corrected_stencil","add_2898_2899_2900.out"], + ["mult_middle_2892n261_2893.in1","const_n261_n261$3.out"], + ["mult_middle_2889n31_2890.in1","const_n31_n31$3.out"], + ["umin_demosaicked_1_stencil_35_2887_2891.in1","const_p10000__2887$1.out"], + ["umin_demosaicked_1_stencil_36_2887_2895.in1","const_p10000__2887$2.out"], + ["umin_demosaicked_1_stencil_34_2887_2888.in1","const_p10000__2887.out"], + ["mult_middle_2896883_2897.in1","const_p883_883$3.out"], + ["umin_demosaicked_1_stencil_34_2887_2888.out","mult_middle_2889n31_2890.in0"], + ["umin_demosaicked_1_stencil_35_2887_2891.out","mult_middle_2892n261_2893.in0"], + ["umin_demosaicked_1_stencil_36_2887_2895.out","mult_middle_2896883_2897.in0"], + ["umin_demosaicked_1_stencil_34_2887_2888.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_35_2887_2891.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_36_2887_2895.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_2":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2349_2352_2353":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2353_2356_2357":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2357_2358_2359":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__2358":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__2346":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2346$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2346$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_2348n31_2349":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2351n261_2352":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2355883_2356":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_7_2346_2347":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_8_2346_2350":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_9_2346_2354":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2348n31_2349.out","add_2349_2352_2353.in0"], + ["mult_middle_2351n261_2352.out","add_2349_2352_2353.in1"], + ["add_2353_2356_2357.in0","add_2349_2352_2353.out"], + ["mult_middle_2355883_2356.out","add_2353_2356_2357.in1"], + ["add_2357_2358_2359.in0","add_2353_2356_2357.out"], + ["const_n22__2358.out","add_2357_2358_2359.in1"], + ["self.out_corrected_stencil","add_2357_2358_2359.out"], + ["mult_middle_2351n261_2352.in1","const_n261_n261.out"], + ["mult_middle_2348n31_2349.in1","const_n31_n31.out"], + ["umin_demosaicked_1_stencil_8_2346_2350.in1","const_p10000__2346$1.out"], + ["umin_demosaicked_1_stencil_9_2346_2354.in1","const_p10000__2346$2.out"], + ["umin_demosaicked_1_stencil_7_2346_2347.in1","const_p10000__2346.out"], + ["mult_middle_2355883_2356.in1","const_p883_883.out"], + ["umin_demosaicked_1_stencil_7_2346_2347.out","mult_middle_2348n31_2349.in0"], + ["umin_demosaicked_1_stencil_8_2346_2350.out","mult_middle_2351n261_2352.in0"], + ["umin_demosaicked_1_stencil_9_2346_2354.out","mult_middle_2355883_2356.in0"], + ["umin_demosaicked_1_stencil_7_2346_2347.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_8_2346_2350.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_9_2346_2354.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_3":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2408_2411_2412":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2412_2415_2416":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2416_2417_2418":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__2417":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__2405":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2405$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2405$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_2407549_2408":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2410n103_2411":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_24147_2415":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_10_2405_2406":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_11_2405_2409":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_12_2405_2413":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2407549_2408.out","add_2408_2411_2412.in0"], + ["mult_middle_2410n103_2411.out","add_2408_2411_2412.in1"], + ["add_2412_2415_2416.in0","add_2408_2411_2412.out"], + ["mult_middle_24147_2415.out","add_2412_2415_2416.in1"], + ["add_2416_2417_2418.in0","add_2412_2415_2416.out"], + ["const_n40__2417.out","add_2416_2417_2418.in1"], + ["self.out_corrected_stencil","add_2416_2417_2418.out"], + ["mult_middle_2410n103_2411.in1","const_n103_n103$1.out"], + ["umin_demosaicked_1_stencil_11_2405_2409.in1","const_p10000__2405$1.out"], + ["umin_demosaicked_1_stencil_12_2405_2413.in1","const_p10000__2405$2.out"], + ["umin_demosaicked_1_stencil_10_2405_2406.in1","const_p10000__2405.out"], + ["mult_middle_2407549_2408.in1","const_p549_549$1.out"], + ["mult_middle_24147_2415.in1","const_p7_7$1.out"], + ["umin_demosaicked_1_stencil_10_2405_2406.out","mult_middle_2407549_2408.in0"], + ["umin_demosaicked_1_stencil_11_2405_2409.out","mult_middle_2410n103_2411.in0"], + ["umin_demosaicked_1_stencil_12_2405_2413.out","mult_middle_24147_2415.in0"], + ["umin_demosaicked_1_stencil_10_2405_2406.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_11_2405_2409.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_12_2405_2413.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_4":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2468_2471_2472":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2472_2475_2476":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2476_2477_2478":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__2477":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__2465":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2465$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2465$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_2467n96_2468":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2470373_2471":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_247462_2475":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_13_2465_2466":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_14_2465_2469":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_15_2465_2473":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2467n96_2468.out","add_2468_2471_2472.in0"], + ["mult_middle_2470373_2471.out","add_2468_2471_2472.in1"], + ["add_2472_2475_2476.in0","add_2468_2471_2472.out"], + ["mult_middle_247462_2475.out","add_2472_2475_2476.in1"], + ["add_2476_2477_2478.in0","add_2472_2475_2476.out"], + ["const_n29__2477.out","add_2476_2477_2478.in1"], + ["self.out_corrected_stencil","add_2476_2477_2478.out"], + ["mult_middle_2467n96_2468.in1","const_n96_n96$1.out"], + ["umin_demosaicked_1_stencil_14_2465_2469.in1","const_p10000__2465$1.out"], + ["umin_demosaicked_1_stencil_15_2465_2473.in1","const_p10000__2465$2.out"], + ["umin_demosaicked_1_stencil_13_2465_2466.in1","const_p10000__2465.out"], + ["mult_middle_2470373_2471.in1","const_p373_373$1.out"], + ["mult_middle_247462_2475.in1","const_p62_62$1.out"], + ["umin_demosaicked_1_stencil_13_2465_2466.out","mult_middle_2467n96_2468.in0"], + ["umin_demosaicked_1_stencil_14_2465_2469.out","mult_middle_2470373_2471.in0"], + ["umin_demosaicked_1_stencil_15_2465_2473.out","mult_middle_247462_2475.in0"], + ["umin_demosaicked_1_stencil_13_2465_2466.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_14_2465_2469.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_15_2465_2473.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_5":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2528_2531_2532":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2532_2535_2536":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2536_2537_2538":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__2537":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__2525":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2525$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2525$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_2527n31_2528":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2530n261_2531":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2534883_2535":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_16_2525_2526":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_17_2525_2529":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_18_2525_2533":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2527n31_2528.out","add_2528_2531_2532.in0"], + ["mult_middle_2530n261_2531.out","add_2528_2531_2532.in1"], + ["add_2532_2535_2536.in0","add_2528_2531_2532.out"], + ["mult_middle_2534883_2535.out","add_2532_2535_2536.in1"], + ["add_2536_2537_2538.in0","add_2532_2535_2536.out"], + ["const_n22__2537.out","add_2536_2537_2538.in1"], + ["self.out_corrected_stencil","add_2536_2537_2538.out"], + ["mult_middle_2530n261_2531.in1","const_n261_n261$1.out"], + ["mult_middle_2527n31_2528.in1","const_n31_n31$1.out"], + ["umin_demosaicked_1_stencil_17_2525_2529.in1","const_p10000__2525$1.out"], + ["umin_demosaicked_1_stencil_18_2525_2533.in1","const_p10000__2525$2.out"], + ["umin_demosaicked_1_stencil_16_2525_2526.in1","const_p10000__2525.out"], + ["mult_middle_2534883_2535.in1","const_p883_883$1.out"], + ["umin_demosaicked_1_stencil_16_2525_2526.out","mult_middle_2527n31_2528.in0"], + ["umin_demosaicked_1_stencil_17_2525_2529.out","mult_middle_2530n261_2531.in0"], + ["umin_demosaicked_1_stencil_18_2525_2533.out","mult_middle_2534883_2535.in0"], + ["umin_demosaicked_1_stencil_16_2525_2526.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_17_2525_2529.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_18_2525_2533.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_6":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2588_2591_2592":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2592_2595_2596":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2596_2597_2598":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__2597":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__2585":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2585$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2585$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_2587549_2588":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2590n103_2591":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_25947_2595":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_19_2585_2586":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_20_2585_2589":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_21_2585_2593":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2587549_2588.out","add_2588_2591_2592.in0"], + ["mult_middle_2590n103_2591.out","add_2588_2591_2592.in1"], + ["add_2592_2595_2596.in0","add_2588_2591_2592.out"], + ["mult_middle_25947_2595.out","add_2592_2595_2596.in1"], + ["add_2596_2597_2598.in0","add_2592_2595_2596.out"], + ["const_n40__2597.out","add_2596_2597_2598.in1"], + ["self.out_corrected_stencil","add_2596_2597_2598.out"], + ["mult_middle_2590n103_2591.in1","const_n103_n103$2.out"], + ["umin_demosaicked_1_stencil_20_2585_2589.in1","const_p10000__2585$1.out"], + ["umin_demosaicked_1_stencil_21_2585_2593.in1","const_p10000__2585$2.out"], + ["umin_demosaicked_1_stencil_19_2585_2586.in1","const_p10000__2585.out"], + ["mult_middle_2587549_2588.in1","const_p549_549$2.out"], + ["mult_middle_25947_2595.in1","const_p7_7$2.out"], + ["umin_demosaicked_1_stencil_19_2585_2586.out","mult_middle_2587549_2588.in0"], + ["umin_demosaicked_1_stencil_20_2585_2589.out","mult_middle_2590n103_2591.in0"], + ["umin_demosaicked_1_stencil_21_2585_2593.out","mult_middle_25947_2595.in0"], + ["umin_demosaicked_1_stencil_19_2585_2586.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_20_2585_2589.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_21_2585_2593.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_7":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2648_2651_2652":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2652_2655_2656":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2656_2657_2658":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__2657":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__2645":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2645$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2645$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_2647n96_2648":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2650373_2651":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_265462_2655":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_22_2645_2646":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_23_2645_2649":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_24_2645_2653":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2647n96_2648.out","add_2648_2651_2652.in0"], + ["mult_middle_2650373_2651.out","add_2648_2651_2652.in1"], + ["add_2652_2655_2656.in0","add_2648_2651_2652.out"], + ["mult_middle_265462_2655.out","add_2652_2655_2656.in1"], + ["add_2656_2657_2658.in0","add_2652_2655_2656.out"], + ["const_n29__2657.out","add_2656_2657_2658.in1"], + ["self.out_corrected_stencil","add_2656_2657_2658.out"], + ["mult_middle_2647n96_2648.in1","const_n96_n96$2.out"], + ["umin_demosaicked_1_stencil_23_2645_2649.in1","const_p10000__2645$1.out"], + ["umin_demosaicked_1_stencil_24_2645_2653.in1","const_p10000__2645$2.out"], + ["umin_demosaicked_1_stencil_22_2645_2646.in1","const_p10000__2645.out"], + ["mult_middle_2650373_2651.in1","const_p373_373$2.out"], + ["mult_middle_265462_2655.in1","const_p62_62$2.out"], + ["umin_demosaicked_1_stencil_22_2645_2646.out","mult_middle_2647n96_2648.in0"], + ["umin_demosaicked_1_stencil_23_2645_2649.out","mult_middle_2650373_2651.in0"], + ["umin_demosaicked_1_stencil_24_2645_2653.out","mult_middle_265462_2655.in0"], + ["umin_demosaicked_1_stencil_22_2645_2646.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_23_2645_2649.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_24_2645_2653.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_8":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2708_2711_2712":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2712_2715_2716":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2716_2717_2718":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__2717":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__2705":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2705$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2705$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_2707n31_2708":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2710n261_2711":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2714883_2715":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_25_2705_2706":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_26_2705_2709":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_27_2705_2713":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2707n31_2708.out","add_2708_2711_2712.in0"], + ["mult_middle_2710n261_2711.out","add_2708_2711_2712.in1"], + ["add_2712_2715_2716.in0","add_2708_2711_2712.out"], + ["mult_middle_2714883_2715.out","add_2712_2715_2716.in1"], + ["add_2716_2717_2718.in0","add_2712_2715_2716.out"], + ["const_n22__2717.out","add_2716_2717_2718.in1"], + ["self.out_corrected_stencil","add_2716_2717_2718.out"], + ["mult_middle_2710n261_2711.in1","const_n261_n261$2.out"], + ["mult_middle_2707n31_2708.in1","const_n31_n31$2.out"], + ["umin_demosaicked_1_stencil_26_2705_2709.in1","const_p10000__2705$1.out"], + ["umin_demosaicked_1_stencil_27_2705_2713.in1","const_p10000__2705$2.out"], + ["umin_demosaicked_1_stencil_25_2705_2706.in1","const_p10000__2705.out"], + ["mult_middle_2714883_2715.in1","const_p883_883$2.out"], + ["umin_demosaicked_1_stencil_25_2705_2706.out","mult_middle_2707n31_2708.in0"], + ["umin_demosaicked_1_stencil_26_2705_2709.out","mult_middle_2710n261_2711.in0"], + ["umin_demosaicked_1_stencil_27_2705_2713.out","mult_middle_2714883_2715.in0"], + ["umin_demosaicked_1_stencil_25_2705_2706.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_26_2705_2709.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_27_2705_2713.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_9":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2768_2771_2772":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2772_2775_2776":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2776_2777_2778":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__2777":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__2765":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2765$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__2765$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_2767549_2768":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_2770n103_2771":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_27747_2775":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_28_2765_2766":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_29_2765_2769":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_30_2765_2773":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_2767549_2768.out","add_2768_2771_2772.in0"], + ["mult_middle_2770n103_2771.out","add_2768_2771_2772.in1"], + ["add_2772_2775_2776.in0","add_2768_2771_2772.out"], + ["mult_middle_27747_2775.out","add_2772_2775_2776.in1"], + ["add_2776_2777_2778.in0","add_2772_2775_2776.out"], + ["const_n40__2777.out","add_2776_2777_2778.in1"], + ["self.out_corrected_stencil","add_2776_2777_2778.out"], + ["mult_middle_2770n103_2771.in1","const_n103_n103$3.out"], + ["umin_demosaicked_1_stencil_29_2765_2769.in1","const_p10000__2765$1.out"], + ["umin_demosaicked_1_stencil_30_2765_2773.in1","const_p10000__2765$2.out"], + ["umin_demosaicked_1_stencil_28_2765_2766.in1","const_p10000__2765.out"], + ["mult_middle_2767549_2768.in1","const_p549_549$3.out"], + ["mult_middle_27747_2775.in1","const_p7_7$3.out"], + ["umin_demosaicked_1_stencil_28_2765_2766.out","mult_middle_2767549_2768.in0"], + ["umin_demosaicked_1_stencil_29_2765_2769.out","mult_middle_2770n103_2771.in0"], + ["umin_demosaicked_1_stencil_30_2765_2773.out","mult_middle_27747_2775.in0"], + ["umin_demosaicked_1_stencil_28_2765_2766.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_29_2765_2769.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_30_2765_2773.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_curved_stencil":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__4985":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__4983":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_4984_4985_4986":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_1_4983_4984":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_4984_4985_4986.in1","const_p0__4985.out"], + ["smin_corrected_stencil_1_4983_4984.in1","const_p1023__4983.out"], + ["smax_4984_4985_4986.out","rom_curvea0.raddr"], + ["self.out_curved_stencil","rom_curvea0.rdata"], + ["rom_curvea0_ren.out","rom_curvea0.ren"], + ["smin_corrected_stencil_1_4983_4984.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_1_4983_4984.out","smax_4984_4985_4986.in0"] + ] + }, + "hcompute_curved_stencil_1":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__6032":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__6030":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$1":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$1_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_6031_6032_6033":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_2_6030_6031":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_6031_6032_6033.in1","const_p0__6032.out"], + ["smin_corrected_stencil_2_6030_6031.in1","const_p1023__6030.out"], + ["smax_6031_6032_6033.out","rom_curvea0$1.raddr"], + ["self.out_curved_stencil","rom_curvea0$1.rdata"], + ["rom_curvea0$1_ren.out","rom_curvea0$1.ren"], + ["smin_corrected_stencil_2_6030_6031.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_2_6030_6031.out","smax_6031_6032_6033.in0"] + ] + }, + "hcompute_curved_stencil_10":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__15463":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__15461":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$10":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$10_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_15462_15463_15464":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_11_15461_15462":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_15462_15463_15464.in1","const_p0__15463.out"], + ["smin_corrected_stencil_11_15461_15462.in1","const_p1023__15461.out"], + ["smax_15462_15463_15464.out","rom_curvea0$10.raddr"], + ["self.out_curved_stencil","rom_curvea0$10.rdata"], + ["rom_curvea0$10_ren.out","rom_curvea0$10.ren"], + ["smin_corrected_stencil_11_15461_15462.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_11_15461_15462.out","smax_15462_15463_15464.in0"] + ] + }, + "hcompute_curved_stencil_11":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__16512":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__16510":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$11":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$11_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_16511_16512_16513":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_12_16510_16511":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_16511_16512_16513.in1","const_p0__16512.out"], + ["smin_corrected_stencil_12_16510_16511.in1","const_p1023__16510.out"], + ["smax_16511_16512_16513.out","rom_curvea0$11.raddr"], + ["self.out_curved_stencil","rom_curvea0$11.rdata"], + ["rom_curvea0$11_ren.out","rom_curvea0$11.ren"], + ["smin_corrected_stencil_12_16510_16511.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_12_16510_16511.out","smax_16511_16512_16513.in0"] + ] + }, + "hcompute_curved_stencil_2":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__7079":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__7077":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$2":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$2_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_7078_7079_7080":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_3_7077_7078":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_7078_7079_7080.in1","const_p0__7079.out"], + ["smin_corrected_stencil_3_7077_7078.in1","const_p1023__7077.out"], + ["smax_7078_7079_7080.out","rom_curvea0$2.raddr"], + ["self.out_curved_stencil","rom_curvea0$2.rdata"], + ["rom_curvea0$2_ren.out","rom_curvea0$2.ren"], + ["smin_corrected_stencil_3_7077_7078.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_3_7077_7078.out","smax_7078_7079_7080.in0"] + ] + }, + "hcompute_curved_stencil_3":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__8126":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__8124":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$3":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$3_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_8125_8126_8127":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_4_8124_8125":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_8125_8126_8127.in1","const_p0__8126.out"], + ["smin_corrected_stencil_4_8124_8125.in1","const_p1023__8124.out"], + ["smax_8125_8126_8127.out","rom_curvea0$3.raddr"], + ["self.out_curved_stencil","rom_curvea0$3.rdata"], + ["rom_curvea0$3_ren.out","rom_curvea0$3.ren"], + ["smin_corrected_stencil_4_8124_8125.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_4_8124_8125.out","smax_8125_8126_8127.in0"] + ] + }, + "hcompute_curved_stencil_4":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__9174":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__9172":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$4":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$4_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_9173_9174_9175":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_5_9172_9173":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_9173_9174_9175.in1","const_p0__9174.out"], + ["smin_corrected_stencil_5_9172_9173.in1","const_p1023__9172.out"], + ["smax_9173_9174_9175.out","rom_curvea0$4.raddr"], + ["self.out_curved_stencil","rom_curvea0$4.rdata"], + ["rom_curvea0$4_ren.out","rom_curvea0$4.ren"], + ["smin_corrected_stencil_5_9172_9173.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_5_9172_9173.out","smax_9173_9174_9175.in0"] + ] + }, + "hcompute_curved_stencil_5":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__10222":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__10220":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$5":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$5_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_10221_10222_10223":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_6_10220_10221":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_10221_10222_10223.in1","const_p0__10222.out"], + ["smin_corrected_stencil_6_10220_10221.in1","const_p1023__10220.out"], + ["smax_10221_10222_10223.out","rom_curvea0$5.raddr"], + ["self.out_curved_stencil","rom_curvea0$5.rdata"], + ["rom_curvea0$5_ren.out","rom_curvea0$5.ren"], + ["smin_corrected_stencil_6_10220_10221.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_6_10220_10221.out","smax_10221_10222_10223.in0"] + ] + }, + "hcompute_curved_stencil_6":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__11270":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__11268":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$6":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$6_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_11269_11270_11271":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_7_11268_11269":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_11269_11270_11271.in1","const_p0__11270.out"], + ["smin_corrected_stencil_7_11268_11269.in1","const_p1023__11268.out"], + ["smax_11269_11270_11271.out","rom_curvea0$6.raddr"], + ["self.out_curved_stencil","rom_curvea0$6.rdata"], + ["rom_curvea0$6_ren.out","rom_curvea0$6.ren"], + ["smin_corrected_stencil_7_11268_11269.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_7_11268_11269.out","smax_11269_11270_11271.in0"] + ] + }, + "hcompute_curved_stencil_7":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__12318":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__12316":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$7":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$7_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_12317_12318_12319":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_8_12316_12317":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_12317_12318_12319.in1","const_p0__12318.out"], + ["smin_corrected_stencil_8_12316_12317.in1","const_p1023__12316.out"], + ["smax_12317_12318_12319.out","rom_curvea0$7.raddr"], + ["self.out_curved_stencil","rom_curvea0$7.rdata"], + ["rom_curvea0$7_ren.out","rom_curvea0$7.ren"], + ["smin_corrected_stencil_8_12316_12317.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_8_12316_12317.out","smax_12317_12318_12319.in0"] + ] + }, + "hcompute_curved_stencil_8":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__13366":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__13364":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$8":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$8_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_13365_13366_13367":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_9_13364_13365":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_13365_13366_13367.in1","const_p0__13366.out"], + ["smin_corrected_stencil_9_13364_13365.in1","const_p1023__13364.out"], + ["smax_13365_13366_13367.out","rom_curvea0$8.raddr"], + ["self.out_curved_stencil","rom_curvea0$8.rdata"], + ["rom_curvea0$8_ren.out","rom_curvea0$8.ren"], + ["smin_corrected_stencil_9_13364_13365.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_9_13364_13365.out","smax_13365_13366_13367.in0"] + ] + }, + "hcompute_curved_stencil_9":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__14414":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__14412":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$9":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$9_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_14413_14414_14415":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_10_14412_14413":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_14413_14414_14415.in1","const_p0__14414.out"], + ["smin_corrected_stencil_10_14412_14413.in1","const_p1023__14412.out"], + ["smax_14413_14414_14415.out","rom_curvea0$9.raddr"], + ["self.out_curved_stencil","rom_curvea0$9.rdata"], + ["rom_curvea0$9_ren.out","rom_curvea0$9.ren"], + ["smin_corrected_stencil_10_14412_14413.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_10_14412_14413.out","smax_14413_14414_14415.in0"] + ] + }, + "hcompute_demosaicked_1_stencil":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_gr_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_1":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_gr_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_10":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_gb_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_11":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_gb_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_2":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_gr_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_3":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_b_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_b_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_4":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_b_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_5":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_b_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_6":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_r_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_7":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_g_r_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_8":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_b_r_stencil.0"] + ] + }, + "hcompute_demosaicked_1_stencil_9":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_demosaicked_1_stencil","self.in0_r_gb_stencil.0"] + ] + }, + "hcompute_denoised_1_stencil":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377.out","umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_378_379.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_2_377_378.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_376.out","umax_hw_input_global_wrapper_global_wrapper_stencil_3_376_377.in1"] + ] + }, + "hcompute_denoised_1_stencil_1":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400.out","umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_401_402.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_7_400_401.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_399.out","umax_hw_input_global_wrapper_global_wrapper_stencil_8_399_400.in1"] + ] + }, + "hcompute_denoised_1_stencil_2":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424.out","umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_11_425_426.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_12_424_425.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_14_hw_input_global_wrapper_global_wrapper_stencil_15_423.out","umax_hw_input_global_wrapper_global_wrapper_stencil_13_423_424.in1"] + ] + }, + "hcompute_denoised_1_stencil_3":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448.out","umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_16_449_450.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_17_448_449.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_19_hw_input_global_wrapper_global_wrapper_stencil_20_447.out","umax_hw_input_global_wrapper_global_wrapper_stencil_18_447_448.in1"] + ] + }, + "hcompute_g_b_stencil":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_1_g_gb_stencil_2_577":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_1_g_gr_stencil_2_578":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_1_g_gb_stencil_2_580":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_1_g_gr_stencil_2_583":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__581":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__581$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_580_581_582":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_583_581_584":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_579_582_584":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_577_578_579":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_1_g_gb_stencil_2_577.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_1_g_gb_stencil_2_577.in1"], + ["ult_577_578_579.in0","absd_g_gb_stencil_1_g_gb_stencil_2_577.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_1_g_gr_stencil_2_578.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_1_g_gr_stencil_2_578.in1"], + ["ult_577_578_579.in1","absd_g_gr_stencil_1_g_gr_stencil_2_578.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_1_g_gb_stencil_2_580.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_1_g_gb_stencil_2_580.in1"], + ["lshr_580_581_582.in0","add_g_gb_stencil_1_g_gb_stencil_2_580.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_1_g_gr_stencil_2_583.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_1_g_gr_stencil_2_583.in1"], + ["lshr_583_581_584.in0","add_g_gr_stencil_1_g_gr_stencil_2_583.out"], + ["lshr_583_581_584.in1","const_p1__581$1.out"], + ["lshr_580_581_582.in1","const_p1__581.out"], + ["mux_579_582_584.in1","lshr_580_581_582.out"], + ["mux_579_582_584.in0","lshr_583_581_584.out"], + ["self.out_g_b_stencil","mux_579_582_584.out"], + ["ult_577_578_579.out","mux_579_582_584.sel"] + ] + }, + "hcompute_g_b_stencil_1":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_3_g_gb_stencil_4_628":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_3_g_gr_stencil_4_629":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_3_g_gb_stencil_4_631":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_3_g_gr_stencil_4_634":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__632":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__632$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_631_632_633":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_634_632_635":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_630_633_635":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_628_629_630":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_3_g_gb_stencil_4_628.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_3_g_gb_stencil_4_628.in1"], + ["ult_628_629_630.in0","absd_g_gb_stencil_3_g_gb_stencil_4_628.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_3_g_gr_stencil_4_629.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_3_g_gr_stencil_4_629.in1"], + ["ult_628_629_630.in1","absd_g_gr_stencil_3_g_gr_stencil_4_629.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_3_g_gb_stencil_4_631.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_3_g_gb_stencil_4_631.in1"], + ["lshr_631_632_633.in0","add_g_gb_stencil_3_g_gb_stencil_4_631.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_3_g_gr_stencil_4_634.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_3_g_gr_stencil_4_634.in1"], + ["lshr_634_632_635.in0","add_g_gr_stencil_3_g_gr_stencil_4_634.out"], + ["lshr_634_632_635.in1","const_p1__632$1.out"], + ["lshr_631_632_633.in1","const_p1__632.out"], + ["mux_630_633_635.in1","lshr_631_632_633.out"], + ["mux_630_633_635.in0","lshr_634_632_635.out"], + ["self.out_g_b_stencil","mux_630_633_635.out"], + ["ult_628_629_630.out","mux_630_633_635.sel"] + ] + }, + "hcompute_g_b_stencil_2":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_5_g_gb_stencil_6_680":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_5_g_gr_stencil_6_681":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_5_g_gb_stencil_6_683":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_5_g_gr_stencil_6_686":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__684":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__684$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_683_684_685":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_686_684_687":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_682_685_687":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_680_681_682":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_5_g_gb_stencil_6_680.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_5_g_gb_stencil_6_680.in1"], + ["ult_680_681_682.in0","absd_g_gb_stencil_5_g_gb_stencil_6_680.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_5_g_gr_stencil_6_681.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_5_g_gr_stencil_6_681.in1"], + ["ult_680_681_682.in1","absd_g_gr_stencil_5_g_gr_stencil_6_681.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_5_g_gb_stencil_6_683.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_5_g_gb_stencil_6_683.in1"], + ["lshr_683_684_685.in0","add_g_gb_stencil_5_g_gb_stencil_6_683.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_5_g_gr_stencil_6_686.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_5_g_gr_stencil_6_686.in1"], + ["lshr_686_684_687.in0","add_g_gr_stencil_5_g_gr_stencil_6_686.out"], + ["lshr_686_684_687.in1","const_p1__684$1.out"], + ["lshr_683_684_685.in1","const_p1__684.out"], + ["mux_682_685_687.in1","lshr_683_684_685.out"], + ["mux_682_685_687.in0","lshr_686_684_687.out"], + ["self.out_g_b_stencil","mux_682_685_687.out"], + ["ult_680_681_682.out","mux_682_685_687.sel"] + ] + }, + "hcompute_g_b_stencil_3":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_7_g_gb_stencil_8_732":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_7_g_gr_stencil_8_733":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_7_g_gb_stencil_8_735":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_7_g_gr_stencil_8_738":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__736":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__736$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_735_736_737":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_738_736_739":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_734_737_739":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_732_733_734":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_7_g_gb_stencil_8_732.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_7_g_gb_stencil_8_732.in1"], + ["ult_732_733_734.in0","absd_g_gb_stencil_7_g_gb_stencil_8_732.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_7_g_gr_stencil_8_733.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_7_g_gr_stencil_8_733.in1"], + ["ult_732_733_734.in1","absd_g_gr_stencil_7_g_gr_stencil_8_733.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_7_g_gb_stencil_8_735.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_7_g_gb_stencil_8_735.in1"], + ["lshr_735_736_737.in0","add_g_gb_stencil_7_g_gb_stencil_8_735.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_7_g_gr_stencil_8_738.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_7_g_gr_stencil_8_738.in1"], + ["lshr_738_736_739.in0","add_g_gr_stencil_7_g_gr_stencil_8_738.out"], + ["lshr_738_736_739.in1","const_p1__736$1.out"], + ["lshr_735_736_737.in1","const_p1__736.out"], + ["mux_734_737_739.in1","lshr_735_736_737.out"], + ["mux_734_737_739.in0","lshr_738_736_739.out"], + ["self.out_g_b_stencil","mux_734_737_739.out"], + ["ult_732_733_734.out","mux_734_737_739.sel"] + ] + }, + "hcompute_g_gb_stencil":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gb_stencil_1":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gb_stencil_2":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gb_stencil_3":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil_1":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil_2":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil_3":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_r_stencil":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_13_g_gb_stencil_14_1034":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_13_g_gr_stencil_14_1033":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_13_g_gb_stencil_14_1039":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_13_g_gr_stencil_14_1036":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1037":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1037$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1036_1037_1038":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1039_1037_1040":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1035_1038_1040":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_1033_1034_1035":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_13_g_gb_stencil_14_1034.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_13_g_gb_stencil_14_1034.in1"], + ["ult_1033_1034_1035.in1","absd_g_gb_stencil_13_g_gb_stencil_14_1034.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_13_g_gr_stencil_14_1033.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_13_g_gr_stencil_14_1033.in1"], + ["ult_1033_1034_1035.in0","absd_g_gr_stencil_13_g_gr_stencil_14_1033.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_13_g_gb_stencil_14_1039.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_13_g_gb_stencil_14_1039.in1"], + ["lshr_1039_1037_1040.in0","add_g_gb_stencil_13_g_gb_stencil_14_1039.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_13_g_gr_stencil_14_1036.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_13_g_gr_stencil_14_1036.in1"], + ["lshr_1036_1037_1038.in0","add_g_gr_stencil_13_g_gr_stencil_14_1036.out"], + ["lshr_1039_1037_1040.in1","const_p1__1037$1.out"], + ["lshr_1036_1037_1038.in1","const_p1__1037.out"], + ["mux_1035_1038_1040.in1","lshr_1036_1037_1038.out"], + ["mux_1035_1038_1040.in0","lshr_1039_1037_1040.out"], + ["self.out_g_r_stencil","mux_1035_1038_1040.out"], + ["ult_1033_1034_1035.out","mux_1035_1038_1040.sel"] + ] + }, + "hcompute_g_r_stencil_1":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_15_g_gb_stencil_16_1085":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_15_g_gr_stencil_16_1084":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_15_g_gb_stencil_16_1090":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_15_g_gr_stencil_16_1087":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1088":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1088$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1087_1088_1089":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1090_1088_1091":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1086_1089_1091":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_1084_1085_1086":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_15_g_gb_stencil_16_1085.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_15_g_gb_stencil_16_1085.in1"], + ["ult_1084_1085_1086.in1","absd_g_gb_stencil_15_g_gb_stencil_16_1085.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_15_g_gr_stencil_16_1084.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_15_g_gr_stencil_16_1084.in1"], + ["ult_1084_1085_1086.in0","absd_g_gr_stencil_15_g_gr_stencil_16_1084.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_15_g_gb_stencil_16_1090.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_15_g_gb_stencil_16_1090.in1"], + ["lshr_1090_1088_1091.in0","add_g_gb_stencil_15_g_gb_stencil_16_1090.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_15_g_gr_stencil_16_1087.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_15_g_gr_stencil_16_1087.in1"], + ["lshr_1087_1088_1089.in0","add_g_gr_stencil_15_g_gr_stencil_16_1087.out"], + ["lshr_1090_1088_1091.in1","const_p1__1088$1.out"], + ["lshr_1087_1088_1089.in1","const_p1__1088.out"], + ["mux_1086_1089_1091.in1","lshr_1087_1088_1089.out"], + ["mux_1086_1089_1091.in0","lshr_1090_1088_1091.out"], + ["self.out_g_r_stencil","mux_1086_1089_1091.out"], + ["ult_1084_1085_1086.out","mux_1086_1089_1091.sel"] + ] + }, + "hcompute_g_r_stencil_2":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_17_g_gb_stencil_18_1137":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_17_g_gr_stencil_18_1136":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_17_g_gb_stencil_18_1142":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_17_g_gr_stencil_18_1139":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1140":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1140$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1139_1140_1141":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1142_1140_1143":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1138_1141_1143":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_1136_1137_1138":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_17_g_gb_stencil_18_1137.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_17_g_gb_stencil_18_1137.in1"], + ["ult_1136_1137_1138.in1","absd_g_gb_stencil_17_g_gb_stencil_18_1137.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_17_g_gr_stencil_18_1136.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_17_g_gr_stencil_18_1136.in1"], + ["ult_1136_1137_1138.in0","absd_g_gr_stencil_17_g_gr_stencil_18_1136.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_17_g_gb_stencil_18_1142.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_17_g_gb_stencil_18_1142.in1"], + ["lshr_1142_1140_1143.in0","add_g_gb_stencil_17_g_gb_stencil_18_1142.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_17_g_gr_stencil_18_1139.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_17_g_gr_stencil_18_1139.in1"], + ["lshr_1139_1140_1141.in0","add_g_gr_stencil_17_g_gr_stencil_18_1139.out"], + ["lshr_1142_1140_1143.in1","const_p1__1140$1.out"], + ["lshr_1139_1140_1141.in1","const_p1__1140.out"], + ["mux_1138_1141_1143.in1","lshr_1139_1140_1141.out"], + ["mux_1138_1141_1143.in0","lshr_1142_1140_1143.out"], + ["self.out_g_r_stencil","mux_1138_1141_1143.out"], + ["ult_1136_1137_1138.out","mux_1138_1141_1143.sel"] + ] + }, + "hcompute_g_r_stencil_3":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_19_g_gb_stencil_20_1189":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_19_g_gr_stencil_20_1188":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_19_g_gb_stencil_20_1194":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_19_g_gr_stencil_20_1191":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1192":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1192$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1191_1192_1193":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1194_1192_1195":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1190_1193_1195":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_1188_1189_1190":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_19_g_gb_stencil_20_1189.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_19_g_gb_stencil_20_1189.in1"], + ["ult_1188_1189_1190.in1","absd_g_gb_stencil_19_g_gb_stencil_20_1189.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_19_g_gr_stencil_20_1188.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_19_g_gr_stencil_20_1188.in1"], + ["ult_1188_1189_1190.in0","absd_g_gr_stencil_19_g_gr_stencil_20_1188.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_19_g_gb_stencil_20_1194.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_19_g_gb_stencil_20_1194.in1"], + ["lshr_1194_1192_1195.in0","add_g_gb_stencil_19_g_gb_stencil_20_1194.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_19_g_gr_stencil_20_1191.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_19_g_gr_stencil_20_1191.in1"], + ["lshr_1191_1192_1193.in0","add_g_gr_stencil_19_g_gr_stencil_20_1191.out"], + ["lshr_1194_1192_1195.in1","const_p1__1192$1.out"], + ["lshr_1191_1192_1193.in1","const_p1__1192.out"], + ["mux_1190_1193_1195.in1","lshr_1191_1192_1193.out"], + ["mux_1190_1193_1195.in0","lshr_1194_1192_1195.out"], + ["self.out_g_r_stencil","mux_1190_1193_1195.out"], + ["ult_1188_1189_1190.out","mux_1190_1193_1195.sel"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_10":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_11":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_4":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_5":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_6":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_7":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_8":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_9":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_10":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_11":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_4":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_5":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_6":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_7":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_8":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_9":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_r_b_stencil":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_1_r_r_stencil_2_1605":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_3_r_r_stencil_4_1606":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_33_1610_1611":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_33_1616_1617":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_5_g_r_stencil_6_1612":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_7_g_r_stencil_8_1618":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_1_r_r_stencil_2_1608":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_3_r_r_stencil_4_1615":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1609":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1609$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1609$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1609$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1608_1609_1610":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1612_1609_1613":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1615_1609_1616":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1618_1609_1619":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1607_1614_1620":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1611_1613_1614":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1617_1619_1620":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1605_1606_1607":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.0","absd_r_r_stencil_1_r_r_stencil_2_1605.in0"], + ["self.in2_r_r_stencil.1","absd_r_r_stencil_1_r_r_stencil_2_1605.in1"], + ["ult_1605_1606_1607.in0","absd_r_r_stencil_1_r_r_stencil_2_1605.out"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_3_r_r_stencil_4_1606.in0"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_3_r_r_stencil_4_1606.in1"], + ["ult_1605_1606_1607.in1","absd_r_r_stencil_3_r_r_stencil_4_1606.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_33_1610_1611.in0"], + ["lshr_1608_1609_1610.out","add_g_b_stencil_33_1610_1611.in1"], + ["sub_1611_1613_1614.in0","add_g_b_stencil_33_1610_1611.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_33_1616_1617.in0"], + ["lshr_1615_1609_1616.out","add_g_b_stencil_33_1616_1617.in1"], + ["sub_1617_1619_1620.in0","add_g_b_stencil_33_1616_1617.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_5_g_r_stencil_6_1612.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_5_g_r_stencil_6_1612.in1"], + ["lshr_1612_1609_1613.in0","add_g_r_stencil_5_g_r_stencil_6_1612.out"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_7_g_r_stencil_8_1618.in0"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_7_g_r_stencil_8_1618.in1"], + ["lshr_1618_1609_1619.in0","add_g_r_stencil_7_g_r_stencil_8_1618.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_1_r_r_stencil_2_1608.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_1_r_r_stencil_2_1608.in1"], + ["lshr_1608_1609_1610.in0","add_r_r_stencil_1_r_r_stencil_2_1608.out"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_3_r_r_stencil_4_1615.in0"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_3_r_r_stencil_4_1615.in1"], + ["lshr_1615_1609_1616.in0","add_r_r_stencil_3_r_r_stencil_4_1615.out"], + ["lshr_1612_1609_1613.in1","const_p1__1609$1.out"], + ["lshr_1615_1609_1616.in1","const_p1__1609$2.out"], + ["lshr_1618_1609_1619.in1","const_p1__1609$3.out"], + ["lshr_1608_1609_1610.in1","const_p1__1609.out"], + ["sub_1611_1613_1614.in1","lshr_1612_1609_1613.out"], + ["sub_1617_1619_1620.in1","lshr_1618_1609_1619.out"], + ["sub_1617_1619_1620.out","mux_1607_1614_1620.in0"], + ["sub_1611_1613_1614.out","mux_1607_1614_1620.in1"], + ["self.out_r_b_stencil","mux_1607_1614_1620.out"], + ["ult_1605_1606_1607.out","mux_1607_1614_1620.sel"] + ] + }, + "hcompute_r_b_stencil_1":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_5_r_r_stencil_6_1685":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_7_r_r_stencil_8_1686":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_34_1690_1691":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_34_1696_1697":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_11_g_r_stencil_12_1698":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_9_g_r_stencil_10_1692":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_5_r_r_stencil_6_1688":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_7_r_r_stencil_8_1695":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1689":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1689$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1689$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1689$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1688_1689_1690":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1692_1689_1693":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1695_1689_1696":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1698_1689_1699":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1687_1694_1700":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1691_1693_1694":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1697_1699_1700":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1685_1686_1687":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.0","absd_r_r_stencil_5_r_r_stencil_6_1685.in0"], + ["self.in2_r_r_stencil.1","absd_r_r_stencil_5_r_r_stencil_6_1685.in1"], + ["ult_1685_1686_1687.in0","absd_r_r_stencil_5_r_r_stencil_6_1685.out"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_7_r_r_stencil_8_1686.in0"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_7_r_r_stencil_8_1686.in1"], + ["ult_1685_1686_1687.in1","absd_r_r_stencil_7_r_r_stencil_8_1686.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_34_1690_1691.in0"], + ["lshr_1688_1689_1690.out","add_g_b_stencil_34_1690_1691.in1"], + ["sub_1691_1693_1694.in0","add_g_b_stencil_34_1690_1691.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_34_1696_1697.in0"], + ["lshr_1695_1689_1696.out","add_g_b_stencil_34_1696_1697.in1"], + ["sub_1697_1699_1700.in0","add_g_b_stencil_34_1696_1697.out"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_11_g_r_stencil_12_1698.in0"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_11_g_r_stencil_12_1698.in1"], + ["lshr_1698_1689_1699.in0","add_g_r_stencil_11_g_r_stencil_12_1698.out"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_9_g_r_stencil_10_1692.in0"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_9_g_r_stencil_10_1692.in1"], + ["lshr_1692_1689_1693.in0","add_g_r_stencil_9_g_r_stencil_10_1692.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_5_r_r_stencil_6_1688.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_5_r_r_stencil_6_1688.in1"], + ["lshr_1688_1689_1690.in0","add_r_r_stencil_5_r_r_stencil_6_1688.out"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_7_r_r_stencil_8_1695.in0"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_7_r_r_stencil_8_1695.in1"], + ["lshr_1695_1689_1696.in0","add_r_r_stencil_7_r_r_stencil_8_1695.out"], + ["lshr_1692_1689_1693.in1","const_p1__1689$1.out"], + ["lshr_1695_1689_1696.in1","const_p1__1689$2.out"], + ["lshr_1698_1689_1699.in1","const_p1__1689$3.out"], + ["lshr_1688_1689_1690.in1","const_p1__1689.out"], + ["sub_1691_1693_1694.in1","lshr_1692_1689_1693.out"], + ["sub_1697_1699_1700.in1","lshr_1698_1689_1699.out"], + ["sub_1697_1699_1700.out","mux_1687_1694_1700.in0"], + ["sub_1691_1693_1694.out","mux_1687_1694_1700.in1"], + ["self.out_r_b_stencil","mux_1687_1694_1700.out"], + ["ult_1685_1686_1687.out","mux_1687_1694_1700.sel"] + ] + }, + "hcompute_r_b_stencil_2":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_11_r_r_stencil_12_1767":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_9_r_r_stencil_10_1766":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_35_1771_1772":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_35_1777_1778":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_13_g_r_stencil_14_1773":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_15_g_r_stencil_16_1779":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_11_r_r_stencil_12_1776":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_9_r_r_stencil_10_1769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1770":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1770$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1770$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1770$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1769_1770_1771":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1773_1770_1774":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1776_1770_1777":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1779_1770_1780":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1768_1775_1781":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1772_1774_1775":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1778_1780_1781":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1766_1767_1768":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.1","absd_r_r_stencil_11_r_r_stencil_12_1767.in0"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_11_r_r_stencil_12_1767.in1"], + ["ult_1766_1767_1768.in1","absd_r_r_stencil_11_r_r_stencil_12_1767.out"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_9_r_r_stencil_10_1766.in0"], + ["self.in2_r_r_stencil.0","absd_r_r_stencil_9_r_r_stencil_10_1766.in1"], + ["ult_1766_1767_1768.in0","absd_r_r_stencil_9_r_r_stencil_10_1766.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_35_1771_1772.in0"], + ["lshr_1769_1770_1771.out","add_g_b_stencil_35_1771_1772.in1"], + ["sub_1772_1774_1775.in0","add_g_b_stencil_35_1771_1772.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_35_1777_1778.in0"], + ["lshr_1776_1770_1777.out","add_g_b_stencil_35_1777_1778.in1"], + ["sub_1778_1780_1781.in0","add_g_b_stencil_35_1777_1778.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_13_g_r_stencil_14_1773.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_13_g_r_stencil_14_1773.in1"], + ["lshr_1773_1770_1774.in0","add_g_r_stencil_13_g_r_stencil_14_1773.out"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_15_g_r_stencil_16_1779.in0"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_15_g_r_stencil_16_1779.in1"], + ["lshr_1779_1770_1780.in0","add_g_r_stencil_15_g_r_stencil_16_1779.out"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_11_r_r_stencil_12_1776.in0"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_11_r_r_stencil_12_1776.in1"], + ["lshr_1776_1770_1777.in0","add_r_r_stencil_11_r_r_stencil_12_1776.out"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_9_r_r_stencil_10_1769.in0"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_9_r_r_stencil_10_1769.in1"], + ["lshr_1769_1770_1771.in0","add_r_r_stencil_9_r_r_stencil_10_1769.out"], + ["lshr_1773_1770_1774.in1","const_p1__1770$1.out"], + ["lshr_1776_1770_1777.in1","const_p1__1770$2.out"], + ["lshr_1779_1770_1780.in1","const_p1__1770$3.out"], + ["lshr_1769_1770_1771.in1","const_p1__1770.out"], + ["sub_1772_1774_1775.in1","lshr_1773_1770_1774.out"], + ["sub_1778_1780_1781.in1","lshr_1779_1770_1780.out"], + ["sub_1778_1780_1781.out","mux_1768_1775_1781.in0"], + ["sub_1772_1774_1775.out","mux_1768_1775_1781.in1"], + ["self.out_r_b_stencil","mux_1768_1775_1781.out"], + ["ult_1766_1767_1768.out","mux_1768_1775_1781.sel"] + ] + }, + "hcompute_r_b_stencil_3":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_13_r_r_stencil_14_1847":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_15_r_r_stencil_16_1848":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_36_1852_1853":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_36_1858_1859":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_17_g_r_stencil_18_1854":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_19_g_r_stencil_20_1860":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_13_r_r_stencil_14_1850":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_15_r_r_stencil_16_1857":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1851":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1851$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1851$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1851$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1850_1851_1852":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1854_1851_1855":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1857_1851_1858":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1860_1851_1861":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_1849_1856_1862":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_1853_1855_1856":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1859_1861_1862":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_1847_1848_1849":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.0","absd_r_r_stencil_13_r_r_stencil_14_1847.in0"], + ["self.in2_r_r_stencil.1","absd_r_r_stencil_13_r_r_stencil_14_1847.in1"], + ["ult_1847_1848_1849.in0","absd_r_r_stencil_13_r_r_stencil_14_1847.out"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_15_r_r_stencil_16_1848.in0"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_15_r_r_stencil_16_1848.in1"], + ["ult_1847_1848_1849.in1","absd_r_r_stencil_15_r_r_stencil_16_1848.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_36_1852_1853.in0"], + ["lshr_1850_1851_1852.out","add_g_b_stencil_36_1852_1853.in1"], + ["sub_1853_1855_1856.in0","add_g_b_stencil_36_1852_1853.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_36_1858_1859.in0"], + ["lshr_1857_1851_1858.out","add_g_b_stencil_36_1858_1859.in1"], + ["sub_1859_1861_1862.in0","add_g_b_stencil_36_1858_1859.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_17_g_r_stencil_18_1854.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_17_g_r_stencil_18_1854.in1"], + ["lshr_1854_1851_1855.in0","add_g_r_stencil_17_g_r_stencil_18_1854.out"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_19_g_r_stencil_20_1860.in0"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_19_g_r_stencil_20_1860.in1"], + ["lshr_1860_1851_1861.in0","add_g_r_stencil_19_g_r_stencil_20_1860.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_13_r_r_stencil_14_1850.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_13_r_r_stencil_14_1850.in1"], + ["lshr_1850_1851_1852.in0","add_r_r_stencil_13_r_r_stencil_14_1850.out"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_15_r_r_stencil_16_1857.in0"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_15_r_r_stencil_16_1857.in1"], + ["lshr_1857_1851_1858.in0","add_r_r_stencil_15_r_r_stencil_16_1857.out"], + ["lshr_1854_1851_1855.in1","const_p1__1851$1.out"], + ["lshr_1857_1851_1858.in1","const_p1__1851$2.out"], + ["lshr_1860_1851_1861.in1","const_p1__1851$3.out"], + ["lshr_1850_1851_1852.in1","const_p1__1851.out"], + ["sub_1853_1855_1856.in1","lshr_1854_1851_1855.out"], + ["sub_1859_1861_1862.in1","lshr_1860_1851_1861.out"], + ["sub_1859_1861_1862.out","mux_1849_1856_1862.in0"], + ["sub_1853_1855_1856.out","mux_1849_1856_1862.in1"], + ["self.out_r_b_stencil","mux_1849_1856_1862.out"], + ["ult_1847_1848_1849.out","mux_1849_1856_1862.sel"] + ] + }, + "hcompute_r_gb_stencil":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gb_stencil_21_1913_1914":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_21_g_r_stencil_22_1915":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_17_r_r_stencil_18_1911":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1912":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1912$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1911_1912_1913":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1915_1912_1916":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_1914_1916_1917":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_21_1913_1914.in0"], + ["lshr_1911_1912_1913.out","add_g_gb_stencil_21_1913_1914.in1"], + ["sub_1914_1916_1917.in0","add_g_gb_stencil_21_1913_1914.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_21_g_r_stencil_22_1915.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_21_g_r_stencil_22_1915.in1"], + ["lshr_1915_1912_1916.in0","add_g_r_stencil_21_g_r_stencil_22_1915.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_17_r_r_stencil_18_1911.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_17_r_r_stencil_18_1911.in1"], + ["lshr_1911_1912_1913.in0","add_r_r_stencil_17_r_r_stencil_18_1911.out"], + ["lshr_1915_1912_1916.in1","const_p1__1912$1.out"], + ["lshr_1911_1912_1913.in1","const_p1__1912.out"], + ["sub_1914_1916_1917.in1","lshr_1915_1912_1916.out"], + ["sub_1914_1916_1917.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gb_stencil_1":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gb_stencil_22_1943_1944":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_23_g_r_stencil_24_1945":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_19_r_r_stencil_20_1941":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1942":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1942$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1941_1942_1943":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1945_1942_1946":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_1944_1946_1947":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_22_1943_1944.in0"], + ["lshr_1941_1942_1943.out","add_g_gb_stencil_22_1943_1944.in1"], + ["sub_1944_1946_1947.in0","add_g_gb_stencil_22_1943_1944.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_23_g_r_stencil_24_1945.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_23_g_r_stencil_24_1945.in1"], + ["lshr_1945_1942_1946.in0","add_g_r_stencil_23_g_r_stencil_24_1945.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_19_r_r_stencil_20_1941.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_19_r_r_stencil_20_1941.in1"], + ["lshr_1941_1942_1943.in0","add_r_r_stencil_19_r_r_stencil_20_1941.out"], + ["lshr_1945_1942_1946.in1","const_p1__1942$1.out"], + ["lshr_1941_1942_1943.in1","const_p1__1942.out"], + ["sub_1944_1946_1947.in1","lshr_1945_1942_1946.out"], + ["sub_1944_1946_1947.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gb_stencil_2":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gb_stencil_23_1974_1975":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_25_g_r_stencil_26_1976":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_21_r_r_stencil_22_1972":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__1973":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__1973$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_1972_1973_1974":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_1976_1973_1977":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_1975_1977_1978":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_23_1974_1975.in0"], + ["lshr_1972_1973_1974.out","add_g_gb_stencil_23_1974_1975.in1"], + ["sub_1975_1977_1978.in0","add_g_gb_stencil_23_1974_1975.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_25_g_r_stencil_26_1976.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_25_g_r_stencil_26_1976.in1"], + ["lshr_1976_1973_1977.in0","add_g_r_stencil_25_g_r_stencil_26_1976.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_21_r_r_stencil_22_1972.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_21_r_r_stencil_22_1972.in1"], + ["lshr_1972_1973_1974.in0","add_r_r_stencil_21_r_r_stencil_22_1972.out"], + ["lshr_1976_1973_1977.in1","const_p1__1973$1.out"], + ["lshr_1972_1973_1974.in1","const_p1__1973.out"], + ["sub_1975_1977_1978.in1","lshr_1976_1973_1977.out"], + ["sub_1975_1977_1978.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gb_stencil_3":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gb_stencil_24_2005_2006":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_27_g_r_stencil_28_2007":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_23_r_r_stencil_24_2003":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__2004":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__2004$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_2003_2004_2005":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_2007_2004_2008":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_2006_2008_2009":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_24_2005_2006.in0"], + ["lshr_2003_2004_2005.out","add_g_gb_stencil_24_2005_2006.in1"], + ["sub_2006_2008_2009.in0","add_g_gb_stencil_24_2005_2006.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_27_g_r_stencil_28_2007.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_27_g_r_stencil_28_2007.in1"], + ["lshr_2007_2004_2008.in0","add_g_r_stencil_27_g_r_stencil_28_2007.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_23_r_r_stencil_24_2003.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_23_r_r_stencil_24_2003.in1"], + ["lshr_2003_2004_2005.in0","add_r_r_stencil_23_r_r_stencil_24_2003.out"], + ["lshr_2007_2004_2008.in1","const_p1__2004$1.out"], + ["lshr_2003_2004_2005.in1","const_p1__2004.out"], + ["sub_2006_2008_2009.in1","lshr_2007_2004_2008.out"], + ["sub_2006_2008_2009.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gr_stencil":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gr_stencil_21_2037_2038":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_29_g_r_stencil_30_2039":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_25_r_r_stencil_26_2035":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__2036":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__2036$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_2035_2036_2037":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_2039_2036_2040":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_2038_2040_2041":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_21_2037_2038.in0"], + ["lshr_2035_2036_2037.out","add_g_gr_stencil_21_2037_2038.in1"], + ["sub_2038_2040_2041.in0","add_g_gr_stencil_21_2037_2038.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_29_g_r_stencil_30_2039.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_29_g_r_stencil_30_2039.in1"], + ["lshr_2039_2036_2040.in0","add_g_r_stencil_29_g_r_stencil_30_2039.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_25_r_r_stencil_26_2035.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_25_r_r_stencil_26_2035.in1"], + ["lshr_2035_2036_2037.in0","add_r_r_stencil_25_r_r_stencil_26_2035.out"], + ["lshr_2039_2036_2040.in1","const_p1__2036$1.out"], + ["lshr_2035_2036_2037.in1","const_p1__2036.out"], + ["sub_2038_2040_2041.in1","lshr_2039_2036_2040.out"], + ["sub_2038_2040_2041.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_gr_stencil_1":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gr_stencil_22_2067_2068":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_31_g_r_stencil_32_2069":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_27_r_r_stencil_28_2065":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__2066":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__2066$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_2065_2066_2067":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_2069_2066_2070":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_2068_2070_2071":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_22_2067_2068.in0"], + ["lshr_2065_2066_2067.out","add_g_gr_stencil_22_2067_2068.in1"], + ["sub_2068_2070_2071.in0","add_g_gr_stencil_22_2067_2068.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_31_g_r_stencil_32_2069.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_31_g_r_stencil_32_2069.in1"], + ["lshr_2069_2066_2070.in0","add_g_r_stencil_31_g_r_stencil_32_2069.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_27_r_r_stencil_28_2065.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_27_r_r_stencil_28_2065.in1"], + ["lshr_2065_2066_2067.in0","add_r_r_stencil_27_r_r_stencil_28_2065.out"], + ["lshr_2069_2066_2070.in1","const_p1__2066$1.out"], + ["lshr_2065_2066_2067.in1","const_p1__2066.out"], + ["sub_2068_2070_2071.in1","lshr_2069_2066_2070.out"], + ["sub_2068_2070_2071.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_gr_stencil_2":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gr_stencil_23_2098_2099":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_33_g_r_stencil_34_2100":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_29_r_r_stencil_30_2096":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__2097":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__2097$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_2096_2097_2098":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_2100_2097_2101":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_2099_2101_2102":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_23_2098_2099.in0"], + ["lshr_2096_2097_2098.out","add_g_gr_stencil_23_2098_2099.in1"], + ["sub_2099_2101_2102.in0","add_g_gr_stencil_23_2098_2099.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_33_g_r_stencil_34_2100.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_33_g_r_stencil_34_2100.in1"], + ["lshr_2100_2097_2101.in0","add_g_r_stencil_33_g_r_stencil_34_2100.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_29_r_r_stencil_30_2096.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_29_r_r_stencil_30_2096.in1"], + ["lshr_2096_2097_2098.in0","add_r_r_stencil_29_r_r_stencil_30_2096.out"], + ["lshr_2100_2097_2101.in1","const_p1__2097$1.out"], + ["lshr_2096_2097_2098.in1","const_p1__2097.out"], + ["sub_2099_2101_2102.in1","lshr_2100_2097_2101.out"], + ["sub_2099_2101_2102.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_gr_stencil_3":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gr_stencil_24_2129_2130":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_35_g_r_stencil_36_2131":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_31_r_r_stencil_32_2127":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__2128":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__2128$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_2127_2128_2129":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_2131_2128_2132":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_2130_2132_2133":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_24_2129_2130.in0"], + ["lshr_2127_2128_2129.out","add_g_gr_stencil_24_2129_2130.in1"], + ["sub_2130_2132_2133.in0","add_g_gr_stencil_24_2129_2130.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_35_g_r_stencil_36_2131.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_35_g_r_stencil_36_2131.in1"], + ["lshr_2131_2128_2132.in0","add_g_r_stencil_35_g_r_stencil_36_2131.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_31_r_r_stencil_32_2127.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_31_r_r_stencil_32_2127.in1"], + ["lshr_2127_2128_2129.in0","add_r_r_stencil_31_r_r_stencil_32_2127.out"], + ["lshr_2131_2128_2132.in1","const_p1__2128$1.out"], + ["lshr_2127_2128_2129.in1","const_p1__2128.out"], + ["sub_2130_2132_2133.in1","lshr_2131_2128_2132.out"], + ["sub_2130_2132_2133.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_r_stencil":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_r_r_stencil_1":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_r_r_stencil_2":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_r_r_stencil_3":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/camera_pipeline_extra_buf_compute.json b/coreir_compute/camera_pipeline_extra_buf_compute.json new file mode 100644 index 000000000..d77c08ea5 --- /dev/null +++ b/coreir_compute/camera_pipeline_extra_buf_compute.json @@ -0,0 +1,1684 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_b_b_stencil":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_gb_stencil":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_449_450_451":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_454_450_455":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_1_b_b_stencil_2_449":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_1_g_b_stencil_2_454":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_3_452_453":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__450":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__450$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__450$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__450$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_451_450_452":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_455_450_456":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_453_456_457":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["add_b_b_stencil_1_b_b_stencil_2_449.out","add_449_450_451.in0"], + ["const_p1__450.out","add_449_450_451.in1"], + ["lshr_451_450_452.in0","add_449_450_451.out"], + ["add_g_b_stencil_1_g_b_stencil_2_454.out","add_454_450_455.in0"], + ["const_p1__450$2.out","add_454_450_455.in1"], + ["lshr_455_450_456.in0","add_454_450_455.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_1_b_b_stencil_2_449.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_1_b_b_stencil_2_449.in1"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_1_g_b_stencil_2_454.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_1_g_b_stencil_2_454.in1"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_3_452_453.in0"], + ["lshr_451_450_452.out","add_g_gb_stencil_3_452_453.in1"], + ["sub_453_456_457.in0","add_g_gb_stencil_3_452_453.out"], + ["lshr_451_450_452.in1","const_p1__450$1.out"], + ["lshr_455_450_456.in1","const_p1__450$3.out"], + ["sub_453_456_457.in1","lshr_455_450_456.out"], + ["sub_453_456_457.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gr_stencil":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_484_485_486":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_489_485_490":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_3_b_b_stencil_4_484":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_3_g_b_stencil_4_489":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_3_487_488":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__485":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__485$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__485$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__485$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_486_485_487":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_490_485_491":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_488_491_492":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["add_b_b_stencil_3_b_b_stencil_4_484.out","add_484_485_486.in0"], + ["const_p1__485.out","add_484_485_486.in1"], + ["lshr_486_485_487.in0","add_484_485_486.out"], + ["add_g_b_stencil_3_g_b_stencil_4_489.out","add_489_485_490.in0"], + ["const_p1__485$2.out","add_489_485_490.in1"], + ["lshr_490_485_491.in0","add_489_485_490.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_3_b_b_stencil_4_484.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_3_b_b_stencil_4_484.in1"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_3_g_b_stencil_4_489.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_3_g_b_stencil_4_489.in1"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_3_487_488.in0"], + ["lshr_486_485_487.out","add_g_gr_stencil_3_487_488.in1"], + ["sub_488_491_492.in0","add_g_gr_stencil_3_487_488.out"], + ["lshr_486_485_487.in1","const_p1__485$1.out"], + ["lshr_490_485_491.in1","const_p1__485$3.out"], + ["sub_488_491_492.in1","lshr_490_485_491.out"], + ["sub_488_491_492.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_r_stencil":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_5_b_b_stencil_6_598":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_7_b_b_stencil_8_599":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_601_602_603":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_606_602_607":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_610_602_611":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_614_602_615":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_6_b_b_stencil_5_601":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_8_b_b_stencil_7_610":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_5_g_b_stencil_6_606":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_7_g_b_stencil_8_614":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_604_605":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_612_613":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__602":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__602$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__602$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__602$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__602$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__602$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__602$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__602$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_603_602_604":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_607_602_608":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_611_602_612":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_615_602_616":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_600_609_617":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_605_608_609":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_613_616_617":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_598_599_600":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_5_b_b_stencil_6_598.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_5_b_b_stencil_6_598.in1"], + ["ult_598_599_600.in0","absd_b_b_stencil_5_b_b_stencil_6_598.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_7_b_b_stencil_8_599.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_7_b_b_stencil_8_599.in1"], + ["ult_598_599_600.in1","absd_b_b_stencil_7_b_b_stencil_8_599.out"], + ["add_b_b_stencil_6_b_b_stencil_5_601.out","add_601_602_603.in0"], + ["const_p1__602.out","add_601_602_603.in1"], + ["lshr_603_602_604.in0","add_601_602_603.out"], + ["add_g_b_stencil_5_g_b_stencil_6_606.out","add_606_602_607.in0"], + ["const_p1__602$2.out","add_606_602_607.in1"], + ["lshr_607_602_608.in0","add_606_602_607.out"], + ["add_b_b_stencil_8_b_b_stencil_7_610.out","add_610_602_611.in0"], + ["const_p1__602$4.out","add_610_602_611.in1"], + ["lshr_611_602_612.in0","add_610_602_611.out"], + ["add_g_b_stencil_7_g_b_stencil_8_614.out","add_614_602_615.in0"], + ["const_p1__602$6.out","add_614_602_615.in1"], + ["lshr_615_602_616.in0","add_614_602_615.out"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_6_b_b_stencil_5_601.in0"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_6_b_b_stencil_5_601.in1"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_8_b_b_stencil_7_610.in0"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_8_b_b_stencil_7_610.in1"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_5_g_b_stencil_6_606.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_5_g_b_stencil_6_606.in1"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_7_g_b_stencil_8_614.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_7_g_b_stencil_8_614.in1"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_604_605.in0"], + ["lshr_603_602_604.out","add_g_r_stencil_1_604_605.in1"], + ["sub_605_608_609.in0","add_g_r_stencil_1_604_605.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_612_613.in0"], + ["lshr_611_602_612.out","add_g_r_stencil_1_612_613.in1"], + ["sub_613_616_617.in0","add_g_r_stencil_1_612_613.out"], + ["lshr_603_602_604.in1","const_p1__602$1.out"], + ["lshr_607_602_608.in1","const_p1__602$3.out"], + ["lshr_611_602_612.in1","const_p1__602$5.out"], + ["lshr_615_602_616.in1","const_p1__602$7.out"], + ["sub_605_608_609.in1","lshr_607_602_608.out"], + ["sub_613_616_617.in1","lshr_615_602_616.out"], + ["sub_613_616_617.out","mux_600_609_617.in0"], + ["sub_605_608_609.out","mux_600_609_617.in1"], + ["self.out_b_r_stencil","mux_600_609_617.out"], + ["ult_598_599_600.out","mux_600_609_617.sel"] + ] + }, + "hcompute_corrected_stencil":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_936_939_940":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_940_943_944":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_944_945_946":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__945":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__933":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__933$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__933$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_935549_936":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_938n103_939":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_9427_943":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_1_933_934":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_2_933_937":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_3_933_941":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_935549_936.out","add_936_939_940.in0"], + ["mult_middle_938n103_939.out","add_936_939_940.in1"], + ["add_940_943_944.in0","add_936_939_940.out"], + ["mult_middle_9427_943.out","add_940_943_944.in1"], + ["add_944_945_946.in0","add_940_943_944.out"], + ["const_n40__945.out","add_944_945_946.in1"], + ["self.out_corrected_stencil","add_944_945_946.out"], + ["mult_middle_938n103_939.in1","const_n103_n103.out"], + ["umin_demosaicked_1_stencil_2_933_937.in1","const_p10000__933$1.out"], + ["umin_demosaicked_1_stencil_3_933_941.in1","const_p10000__933$2.out"], + ["umin_demosaicked_1_stencil_1_933_934.in1","const_p10000__933.out"], + ["mult_middle_935549_936.in1","const_p549_549.out"], + ["mult_middle_9427_943.in1","const_p7_7.out"], + ["umin_demosaicked_1_stencil_1_933_934.out","mult_middle_935549_936.in0"], + ["umin_demosaicked_1_stencil_2_933_937.out","mult_middle_938n103_939.in0"], + ["umin_demosaicked_1_stencil_3_933_941.out","mult_middle_9427_943.in0"], + ["umin_demosaicked_1_stencil_1_933_934.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_2_933_937.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_3_933_941.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_1":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1001_1002_1003":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_993_996_997":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_997_1000_1001":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1002":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__990":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__990$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__990$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_992n96_993":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_995373_996":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_99962_1000":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_4_990_991":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_5_990_994":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_6_990_998":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["add_997_1000_1001.out","add_1001_1002_1003.in0"], + ["const_n29__1002.out","add_1001_1002_1003.in1"], + ["self.out_corrected_stencil","add_1001_1002_1003.out"], + ["mult_middle_992n96_993.out","add_993_996_997.in0"], + ["mult_middle_995373_996.out","add_993_996_997.in1"], + ["add_997_1000_1001.in0","add_993_996_997.out"], + ["mult_middle_99962_1000.out","add_997_1000_1001.in1"], + ["mult_middle_992n96_993.in1","const_n96_n96.out"], + ["umin_demosaicked_1_stencil_5_990_994.in1","const_p10000__990$1.out"], + ["umin_demosaicked_1_stencil_6_990_998.in1","const_p10000__990$2.out"], + ["umin_demosaicked_1_stencil_4_990_991.in1","const_p10000__990.out"], + ["mult_middle_995373_996.in1","const_p373_373.out"], + ["mult_middle_99962_1000.in1","const_p62_62.out"], + ["umin_demosaicked_1_stencil_4_990_991.out","mult_middle_992n96_993.in0"], + ["umin_demosaicked_1_stencil_5_990_994.out","mult_middle_995373_996.in0"], + ["umin_demosaicked_1_stencil_6_990_998.out","mult_middle_99962_1000.in0"], + ["umin_demosaicked_1_stencil_4_990_991.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_5_990_994.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_6_990_998.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_2":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1050_1053_1054":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1054_1057_1058":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1058_1059_1060":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1059":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1047":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1047$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1047$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1049n31_1050":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1052n261_1053":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1056883_1057":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_7_1047_1048":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_8_1047_1051":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_9_1047_1055":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1049n31_1050.out","add_1050_1053_1054.in0"], + ["mult_middle_1052n261_1053.out","add_1050_1053_1054.in1"], + ["add_1054_1057_1058.in0","add_1050_1053_1054.out"], + ["mult_middle_1056883_1057.out","add_1054_1057_1058.in1"], + ["add_1058_1059_1060.in0","add_1054_1057_1058.out"], + ["const_n22__1059.out","add_1058_1059_1060.in1"], + ["self.out_corrected_stencil","add_1058_1059_1060.out"], + ["mult_middle_1052n261_1053.in1","const_n261_n261.out"], + ["mult_middle_1049n31_1050.in1","const_n31_n31.out"], + ["umin_demosaicked_1_stencil_8_1047_1051.in1","const_p10000__1047$1.out"], + ["umin_demosaicked_1_stencil_9_1047_1055.in1","const_p10000__1047$2.out"], + ["umin_demosaicked_1_stencil_7_1047_1048.in1","const_p10000__1047.out"], + ["mult_middle_1056883_1057.in1","const_p883_883.out"], + ["umin_demosaicked_1_stencil_7_1047_1048.out","mult_middle_1049n31_1050.in0"], + ["umin_demosaicked_1_stencil_8_1047_1051.out","mult_middle_1052n261_1053.in0"], + ["umin_demosaicked_1_stencil_9_1047_1055.out","mult_middle_1056883_1057.in0"], + ["umin_demosaicked_1_stencil_7_1047_1048.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_8_1047_1051.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_9_1047_1055.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_curved_stencil":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__3141":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__3139":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_3140_3141_3142":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_1_3139_3140":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_3140_3141_3142.in1","const_p0__3141.out"], + ["smin_corrected_stencil_1_3139_3140.in1","const_p1023__3139.out"], + ["smax_3140_3141_3142.out","rom_curvea0.raddr"], + ["self.out_curved_stencil","rom_curvea0.rdata"], + ["rom_curvea0_ren.out","rom_curvea0.ren"], + ["smin_corrected_stencil_1_3139_3140.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_1_3139_3140.out","smax_3140_3141_3142.in0"] + ] + }, + "hcompute_curved_stencil_1":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__4186":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__4184":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$1":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$1_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_4185_4186_4187":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_2_4184_4185":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_4185_4186_4187.in1","const_p0__4186.out"], + ["smin_corrected_stencil_2_4184_4185.in1","const_p1023__4184.out"], + ["smax_4185_4186_4187.out","rom_curvea0$1.raddr"], + ["self.out_curved_stencil","rom_curvea0$1.rdata"], + ["rom_curvea0$1_ren.out","rom_curvea0$1.ren"], + ["smin_corrected_stencil_2_4184_4185.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_2_4184_4185.out","smax_4185_4186_4187.in0"] + ] + }, + "hcompute_curved_stencil_2":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__5231":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__5229":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$2":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$2_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_5230_5231_5232":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_3_5229_5230":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_5230_5231_5232.in1","const_p0__5231.out"], + ["smin_corrected_stencil_3_5229_5230.in1","const_p1023__5229.out"], + ["smax_5230_5231_5232.out","rom_curvea0$2.raddr"], + ["self.out_curved_stencil","rom_curvea0$2.rdata"], + ["rom_curvea0$2_ren.out","rom_curvea0$2.ren"], + ["smin_corrected_stencil_3_5229_5230.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_3_5229_5230.out","smax_5230_5231_5232.in0"] + ] + }, + "hcompute_demosaicked_1_stencil":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_r_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_r_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in3_r_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_832_835":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "and_demosaicked_1_s0_y_832_833":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p0_0$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__832":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__832$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8330_834":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "eq_8350_836":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_834_837_838":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "mux_836_r_b_stencil_1_r_gb_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "mux_836_r_gr_stencil_1_r_r_stencil_9":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_832_835.in0"], + ["const_p1__832$1.out","and_demosaicked_1_s0_x_x_832_835.in1"], + ["eq_8350_836.in0","and_demosaicked_1_s0_x_x_832_835.out"], + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_832_833.in0"], + ["const_p1__832.out","and_demosaicked_1_s0_y_832_833.in1"], + ["eq_8330_834.in0","and_demosaicked_1_s0_y_832_833.out"], + ["eq_8350_836.in1","const_p0_0$1.out"], + ["eq_8330_834.in1","const_p0_0.out"], + ["mux_834_837_838.sel","eq_8330_834.out"], + ["mux_836_r_b_stencil_1_r_gb_stencil_1.sel","eq_8350_836.out"], + ["mux_836_r_gr_stencil_1_r_r_stencil_9.sel","eq_8350_836.out"], + ["mux_836_r_b_stencil_1_r_gb_stencil_1.out","mux_834_837_838.in0"], + ["mux_836_r_gr_stencil_1_r_r_stencil_9.out","mux_834_837_838.in1"], + ["self.out_demosaicked_1_stencil","mux_834_837_838.out"], + ["self.in1_r_gb_stencil.0","mux_836_r_b_stencil_1_r_gb_stencil_1.in0"], + ["self.in0_r_b_stencil.0","mux_836_r_b_stencil_1_r_gb_stencil_1.in1"], + ["self.in3_r_r_stencil.0","mux_836_r_gr_stencil_1_r_r_stencil_9.in0"], + ["self.in2_r_gr_stencil.0","mux_836_r_gr_stencil_1_r_r_stencil_9.in1"] + ] + }, + "hcompute_demosaicked_1_stencil_1":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in3_g_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_861_864":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "and_demosaicked_1_s0_y_861_862":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p0_0$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__861$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__861$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8620_863":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "eq_8640_865":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_863_866_867":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "mux_865_g_b_stencil_10_g_gb_stencil_7":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "mux_865_g_gr_stencil_7_g_r_stencil_10":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_861_864.in0"], + ["const_p1__861$2.out","and_demosaicked_1_s0_x_x_861_864.in1"], + ["eq_8640_865.in0","and_demosaicked_1_s0_x_x_861_864.out"], + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_861_862.in0"], + ["const_p1__861$1.out","and_demosaicked_1_s0_y_861_862.in1"], + ["eq_8620_863.in0","and_demosaicked_1_s0_y_861_862.out"], + ["eq_8620_863.in1","const_p0_0$2.out"], + ["eq_8640_865.in1","const_p0_0$3.out"], + ["mux_863_866_867.sel","eq_8620_863.out"], + ["mux_865_g_b_stencil_10_g_gb_stencil_7.sel","eq_8640_865.out"], + ["mux_865_g_gr_stencil_7_g_r_stencil_10.sel","eq_8640_865.out"], + ["mux_865_g_b_stencil_10_g_gb_stencil_7.out","mux_863_866_867.in0"], + ["mux_865_g_gr_stencil_7_g_r_stencil_10.out","mux_863_866_867.in1"], + ["self.out_demosaicked_1_stencil","mux_863_866_867.out"], + ["self.in1_g_gb_stencil.0","mux_865_g_b_stencil_10_g_gb_stencil_7.in0"], + ["self.in0_g_b_stencil.0","mux_865_g_b_stencil_10_g_gb_stencil_7.in1"], + ["self.in3_g_r_stencil.0","mux_865_g_gr_stencil_7_g_r_stencil_10.in0"], + ["self.in2_g_gr_stencil.0","mux_865_g_gr_stencil_7_g_r_stencil_10.in1"] + ] + }, + "hcompute_demosaicked_1_stencil_2":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_b_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_b_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in3_b_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_891_894":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "and_demosaicked_1_s0_y_891_892":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p0_0$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__891":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__891$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8920_893":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "eq_8940_895":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_893_896_897":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "mux_895_b_b_stencil_9_b_gb_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "mux_895_b_gr_stencil_1_b_r_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_891_894.in0"], + ["const_p1__891$1.out","and_demosaicked_1_s0_x_x_891_894.in1"], + ["eq_8940_895.in0","and_demosaicked_1_s0_x_x_891_894.out"], + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_891_892.in0"], + ["const_p1__891.out","and_demosaicked_1_s0_y_891_892.in1"], + ["eq_8920_893.in0","and_demosaicked_1_s0_y_891_892.out"], + ["eq_8920_893.in1","const_p0_0$4.out"], + ["eq_8940_895.in1","const_p0_0$5.out"], + ["mux_893_896_897.sel","eq_8920_893.out"], + ["mux_895_b_b_stencil_9_b_gb_stencil_1.sel","eq_8940_895.out"], + ["mux_895_b_gr_stencil_1_b_r_stencil_1.sel","eq_8940_895.out"], + ["mux_895_b_b_stencil_9_b_gb_stencil_1.out","mux_893_896_897.in0"], + ["mux_895_b_gr_stencil_1_b_r_stencil_1.out","mux_893_896_897.in1"], + ["self.out_demosaicked_1_stencil","mux_893_896_897.out"], + ["self.in1_b_gb_stencil.0","mux_895_b_b_stencil_9_b_gb_stencil_1.in0"], + ["self.in0_b_b_stencil.0","mux_895_b_b_stencil_9_b_gb_stencil_1.in1"], + ["self.in3_b_r_stencil.0","mux_895_b_gr_stencil_1_b_r_stencil_1.in0"], + ["self.in2_b_gr_stencil.0","mux_895_b_gr_stencil_1_b_r_stencil_1.in1"] + ] + }, + "hcompute_denoised_1_stencil":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_2_339_340":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_3_338_339":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_338":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_1_340_341":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_340_341.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_2_339_340.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_338_339.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_338.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_338.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_340_341.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_338_339.out","umax_hw_input_global_wrapper_global_wrapper_stencil_2_339_340.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_340_341.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_2_339_340.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_338.out","umax_hw_input_global_wrapper_global_wrapper_stencil_3_338_339.in1"] + ] + }, + "hcompute_g_b_stencil":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_1_g_gb_stencil_2_401":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_1_g_gr_stencil_2_402":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_404_405_406":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_408_405_409":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_2_g_gb_stencil_1_404":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_2_g_gr_stencil_1_408":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__405":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__405$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__405$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__405$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_406_405_407":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_409_405_410":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_403_407_410":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_401_402_403":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_1_g_gb_stencil_2_401.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_1_g_gb_stencil_2_401.in1"], + ["ult_401_402_403.in0","absd_g_gb_stencil_1_g_gb_stencil_2_401.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_1_g_gr_stencil_2_402.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_1_g_gr_stencil_2_402.in1"], + ["ult_401_402_403.in1","absd_g_gr_stencil_1_g_gr_stencil_2_402.out"], + ["add_g_gb_stencil_2_g_gb_stencil_1_404.out","add_404_405_406.in0"], + ["const_p1__405.out","add_404_405_406.in1"], + ["lshr_406_405_407.in0","add_404_405_406.out"], + ["add_g_gr_stencil_2_g_gr_stencil_1_408.out","add_408_405_409.in0"], + ["const_p1__405$2.out","add_408_405_409.in1"], + ["lshr_409_405_410.in0","add_408_405_409.out"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_2_g_gb_stencil_1_404.in0"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_2_g_gb_stencil_1_404.in1"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_2_g_gr_stencil_1_408.in0"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_2_g_gr_stencil_1_408.in1"], + ["lshr_406_405_407.in1","const_p1__405$1.out"], + ["lshr_409_405_410.in1","const_p1__405$3.out"], + ["mux_403_407_410.in1","lshr_406_405_407.out"], + ["mux_403_407_410.in0","lshr_409_405_410.out"], + ["self.out_g_b_stencil","mux_403_407_410.out"], + ["ult_401_402_403.out","mux_403_407_410.sel"] + ] + }, + "hcompute_g_gb_stencil":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_r_stencil":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_4_g_gb_stencil_5_531":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_4_g_gr_stencil_5_530":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_533_534_535":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_537_534_538":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_5_g_gb_stencil_4_537":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_5_g_gr_stencil_4_533":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__534":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__534$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__534$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__534$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_535_534_536":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_538_534_539":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_532_536_539":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_530_531_532":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_4_g_gb_stencil_5_531.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_4_g_gb_stencil_5_531.in1"], + ["ult_530_531_532.in1","absd_g_gb_stencil_4_g_gb_stencil_5_531.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_4_g_gr_stencil_5_530.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_4_g_gr_stencil_5_530.in1"], + ["ult_530_531_532.in0","absd_g_gr_stencil_4_g_gr_stencil_5_530.out"], + ["add_g_gr_stencil_5_g_gr_stencil_4_533.out","add_533_534_535.in0"], + ["const_p1__534.out","add_533_534_535.in1"], + ["lshr_535_534_536.in0","add_533_534_535.out"], + ["add_g_gb_stencil_5_g_gb_stencil_4_537.out","add_537_534_538.in0"], + ["const_p1__534$2.out","add_537_534_538.in1"], + ["lshr_538_534_539.in0","add_537_534_538.out"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_5_g_gb_stencil_4_537.in0"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_5_g_gb_stencil_4_537.in1"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_5_g_gr_stencil_4_533.in0"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_5_g_gr_stencil_4_533.in1"], + ["lshr_535_534_536.in1","const_p1__534$1.out"], + ["lshr_538_534_539.in1","const_p1__534$3.out"], + ["mux_532_536_539.in1","lshr_535_534_536.out"], + ["mux_532_536_539.in0","lshr_538_534_539.out"], + ["self.out_g_r_stencil","mux_532_536_539.out"], + ["ult_530_531_532.out","mux_532_536_539.sel"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_r_b_stencil":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_1_r_r_stencil_2_694":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_3_r_r_stencil_4_695":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_697_698_699":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_702_698_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_706_698_707":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_710_698_711":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_700_701":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_708_709":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_2_g_r_stencil_3_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_4_g_r_stencil_5_710":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_2_r_r_stencil_1_697":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_4_r_r_stencil_3_706":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__698":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__698$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__698$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__698$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__698$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__698$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__698$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__698$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_699_698_700":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_703_698_704":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_707_698_708":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_711_698_712":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_696_705_713":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_701_704_705":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_709_712_713":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_694_695_696":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.0","absd_r_r_stencil_1_r_r_stencil_2_694.in0"], + ["self.in2_r_r_stencil.1","absd_r_r_stencil_1_r_r_stencil_2_694.in1"], + ["ult_694_695_696.in0","absd_r_r_stencil_1_r_r_stencil_2_694.out"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_3_r_r_stencil_4_695.in0"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_3_r_r_stencil_4_695.in1"], + ["ult_694_695_696.in1","absd_r_r_stencil_3_r_r_stencil_4_695.out"], + ["add_r_r_stencil_2_r_r_stencil_1_697.out","add_697_698_699.in0"], + ["const_p1__698.out","add_697_698_699.in1"], + ["lshr_699_698_700.in0","add_697_698_699.out"], + ["add_g_r_stencil_2_g_r_stencil_3_702.out","add_702_698_703.in0"], + ["const_p1__698$2.out","add_702_698_703.in1"], + ["lshr_703_698_704.in0","add_702_698_703.out"], + ["add_r_r_stencil_4_r_r_stencil_3_706.out","add_706_698_707.in0"], + ["const_p1__698$4.out","add_706_698_707.in1"], + ["lshr_707_698_708.in0","add_706_698_707.out"], + ["add_g_r_stencil_4_g_r_stencil_5_710.out","add_710_698_711.in0"], + ["const_p1__698$6.out","add_710_698_711.in1"], + ["lshr_711_698_712.in0","add_710_698_711.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_700_701.in0"], + ["lshr_699_698_700.out","add_g_b_stencil_9_700_701.in1"], + ["sub_701_704_705.in0","add_g_b_stencil_9_700_701.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_708_709.in0"], + ["lshr_707_698_708.out","add_g_b_stencil_9_708_709.in1"], + ["sub_709_712_713.in0","add_g_b_stencil_9_708_709.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_2_g_r_stencil_3_702.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_2_g_r_stencil_3_702.in1"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_4_g_r_stencil_5_710.in0"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_4_g_r_stencil_5_710.in1"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_2_r_r_stencil_1_697.in0"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_2_r_r_stencil_1_697.in1"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_4_r_r_stencil_3_706.in0"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_4_r_r_stencil_3_706.in1"], + ["lshr_699_698_700.in1","const_p1__698$1.out"], + ["lshr_703_698_704.in1","const_p1__698$3.out"], + ["lshr_707_698_708.in1","const_p1__698$5.out"], + ["lshr_711_698_712.in1","const_p1__698$7.out"], + ["sub_701_704_705.in1","lshr_703_698_704.out"], + ["sub_709_712_713.in1","lshr_711_698_712.out"], + ["sub_709_712_713.out","mux_696_705_713.in0"], + ["sub_701_704_705.out","mux_696_705_713.in1"], + ["self.out_r_b_stencil","mux_696_705_713.out"], + ["ult_694_695_696.out","mux_696_705_713.sel"] + ] + }, + "hcompute_r_gb_stencil":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_765_766_767":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_770_766_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_6_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_6_g_r_stencil_7_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_5_r_r_stencil_6_765":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__766":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__766$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__766$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__766$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_767_766_768":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_771_766_772":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_769_772_773":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["add_r_r_stencil_5_r_r_stencil_6_765.out","add_765_766_767.in0"], + ["const_p1__766.out","add_765_766_767.in1"], + ["lshr_767_766_768.in0","add_765_766_767.out"], + ["add_g_r_stencil_6_g_r_stencil_7_770.out","add_770_766_771.in0"], + ["const_p1__766$2.out","add_770_766_771.in1"], + ["lshr_771_766_772.in0","add_770_766_771.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_6_768_769.in0"], + ["lshr_767_766_768.out","add_g_gb_stencil_6_768_769.in1"], + ["sub_769_772_773.in0","add_g_gb_stencil_6_768_769.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_6_g_r_stencil_7_770.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_6_g_r_stencil_7_770.in1"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_5_r_r_stencil_6_765.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_5_r_r_stencil_6_765.in1"], + ["lshr_767_766_768.in1","const_p1__766$1.out"], + ["lshr_771_766_772.in1","const_p1__766$3.out"], + ["sub_769_772_773.in1","lshr_771_766_772.out"], + ["sub_769_772_773.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gr_stencil":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_800_801_802":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_805_801_806":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_6_803_804":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_8_g_r_stencil_9_805":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_7_r_r_stencil_8_800":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__801":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__801$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__801$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__801$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_802_801_803":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_806_801_807":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_804_807_808":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["add_r_r_stencil_7_r_r_stencil_8_800.out","add_800_801_802.in0"], + ["const_p1__801.out","add_800_801_802.in1"], + ["lshr_802_801_803.in0","add_800_801_802.out"], + ["add_g_r_stencil_8_g_r_stencil_9_805.out","add_805_801_806.in0"], + ["const_p1__801$2.out","add_805_801_806.in1"], + ["lshr_806_801_807.in0","add_805_801_806.out"], + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_6_803_804.in0"], + ["lshr_802_801_803.out","add_g_gr_stencil_6_803_804.in1"], + ["sub_804_807_808.in0","add_g_gr_stencil_6_803_804.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_8_g_r_stencil_9_805.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_8_g_r_stencil_9_805.in1"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_7_r_r_stencil_8_800.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_7_r_r_stencil_8_800.in1"], + ["lshr_802_801_803.in1","const_p1__801$1.out"], + ["lshr_806_801_807.in1","const_p1__801$3.out"], + ["sub_804_807_808.in1","lshr_806_801_807.out"], + ["sub_804_807_808.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_r_stencil":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/camera_pipeline_extra_buf_glb_compute.json b/coreir_compute/camera_pipeline_extra_buf_glb_compute.json new file mode 100644 index 000000000..d4bc0b470 --- /dev/null +++ b/coreir_compute/camera_pipeline_extra_buf_glb_compute.json @@ -0,0 +1,2048 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_b_b_stencil":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_b_stencil_1":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_gb_stencil":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_1_b_b_stencil_2_514":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_1_g_b_stencil_2_518":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_3_516_517":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__515":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__515$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_514_515_516":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_518_515_519":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_517_519_520":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_1_b_b_stencil_2_514.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_1_b_b_stencil_2_514.in1"], + ["lshr_514_515_516.in0","add_b_b_stencil_1_b_b_stencil_2_514.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_1_g_b_stencil_2_518.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_1_g_b_stencil_2_518.in1"], + ["lshr_518_515_519.in0","add_g_b_stencil_1_g_b_stencil_2_518.out"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_3_516_517.in0"], + ["lshr_514_515_516.out","add_g_gb_stencil_3_516_517.in1"], + ["sub_517_519_520.in0","add_g_gb_stencil_3_516_517.out"], + ["lshr_518_515_519.in1","const_p1__515$1.out"], + ["lshr_514_515_516.in1","const_p1__515.out"], + ["sub_517_519_520.in1","lshr_518_515_519.out"], + ["sub_517_519_520.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gr_stencil":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_3_b_b_stencil_4_543":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_3_g_b_stencil_4_547":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_3_545_546":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__544":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__544$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_543_544_545":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_547_544_548":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_546_548_549":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_3_b_b_stencil_4_543.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_3_b_b_stencil_4_543.in1"], + ["lshr_543_544_545.in0","add_b_b_stencil_3_b_b_stencil_4_543.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_3_g_b_stencil_4_547.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_3_g_b_stencil_4_547.in1"], + ["lshr_547_544_548.in0","add_g_b_stencil_3_g_b_stencil_4_547.out"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_3_545_546.in0"], + ["lshr_543_544_545.out","add_g_gr_stencil_3_545_546.in1"], + ["sub_546_548_549.in0","add_g_gr_stencil_3_545_546.out"], + ["lshr_547_544_548.in1","const_p1__544$1.out"], + ["lshr_543_544_545.in1","const_p1__544.out"], + ["sub_546_548_549.in1","lshr_547_544_548.out"], + ["sub_546_548_549.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_r_stencil":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_5_b_b_stencil_6_643":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_7_b_b_stencil_8_644":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_5_b_b_stencil_6_646":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_7_b_b_stencil_8_653":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_5_g_b_stencil_6_650":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_7_g_b_stencil_8_656":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_648_649":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_654_655":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__647":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__647$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__647$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__647$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_646_647_648":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_650_647_651":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_653_647_654":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_656_647_657":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_645_652_658":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_649_651_652":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_655_657_658":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_643_644_645":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_5_b_b_stencil_6_643.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_5_b_b_stencil_6_643.in1"], + ["ult_643_644_645.in0","absd_b_b_stencil_5_b_b_stencil_6_643.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_7_b_b_stencil_8_644.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_7_b_b_stencil_8_644.in1"], + ["ult_643_644_645.in1","absd_b_b_stencil_7_b_b_stencil_8_644.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_5_b_b_stencil_6_646.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_5_b_b_stencil_6_646.in1"], + ["lshr_646_647_648.in0","add_b_b_stencil_5_b_b_stencil_6_646.out"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_7_b_b_stencil_8_653.in0"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_7_b_b_stencil_8_653.in1"], + ["lshr_653_647_654.in0","add_b_b_stencil_7_b_b_stencil_8_653.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_5_g_b_stencil_6_650.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_5_g_b_stencil_6_650.in1"], + ["lshr_650_647_651.in0","add_g_b_stencil_5_g_b_stencil_6_650.out"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_7_g_b_stencil_8_656.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_7_g_b_stencil_8_656.in1"], + ["lshr_656_647_657.in0","add_g_b_stencil_7_g_b_stencil_8_656.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_648_649.in0"], + ["lshr_646_647_648.out","add_g_r_stencil_1_648_649.in1"], + ["sub_649_651_652.in0","add_g_r_stencil_1_648_649.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_654_655.in0"], + ["lshr_653_647_654.out","add_g_r_stencil_1_654_655.in1"], + ["sub_655_657_658.in0","add_g_r_stencil_1_654_655.out"], + ["lshr_650_647_651.in1","const_p1__647$1.out"], + ["lshr_653_647_654.in1","const_p1__647$2.out"], + ["lshr_656_647_657.in1","const_p1__647$3.out"], + ["lshr_646_647_648.in1","const_p1__647.out"], + ["sub_649_651_652.in1","lshr_650_647_651.out"], + ["sub_655_657_658.in1","lshr_656_647_657.out"], + ["sub_655_657_658.out","mux_645_652_658.in0"], + ["sub_649_651_652.out","mux_645_652_658.in1"], + ["self.out_b_r_stencil","mux_645_652_658.out"], + ["ult_643_644_645.out","mux_645_652_658.sel"] + ] + }, + "hcompute_corrected_stencil":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_962_965_966":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_966_969_970":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_970_971_972":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__971":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__959":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__959$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__959$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_961549_962":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_964n103_965":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_9687_969":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_1_959_960":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_2_959_963":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_3_959_967":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_961549_962.out","add_962_965_966.in0"], + ["mult_middle_964n103_965.out","add_962_965_966.in1"], + ["add_966_969_970.in0","add_962_965_966.out"], + ["mult_middle_9687_969.out","add_966_969_970.in1"], + ["add_970_971_972.in0","add_966_969_970.out"], + ["const_n40__971.out","add_970_971_972.in1"], + ["self.out_corrected_stencil","add_970_971_972.out"], + ["mult_middle_964n103_965.in1","const_n103_n103.out"], + ["umin_demosaicked_1_stencil_2_959_963.in1","const_p10000__959$1.out"], + ["umin_demosaicked_1_stencil_3_959_967.in1","const_p10000__959$2.out"], + ["umin_demosaicked_1_stencil_1_959_960.in1","const_p10000__959.out"], + ["mult_middle_961549_962.in1","const_p549_549.out"], + ["mult_middle_9687_969.in1","const_p7_7.out"], + ["umin_demosaicked_1_stencil_1_959_960.out","mult_middle_961549_962.in0"], + ["umin_demosaicked_1_stencil_2_959_963.out","mult_middle_964n103_965.in0"], + ["umin_demosaicked_1_stencil_3_959_967.out","mult_middle_9687_969.in0"], + ["umin_demosaicked_1_stencil_1_959_960.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_2_959_963.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_3_959_967.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_1":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1020_1023_1024":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1024_1027_1028":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1028_1029_1030":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__1029":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__1017":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1017$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1017$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_1019549_1020":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1022n103_1023":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_10267_1027":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_4_1017_1018":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_5_1017_1021":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_6_1017_1025":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1019549_1020.out","add_1020_1023_1024.in0"], + ["mult_middle_1022n103_1023.out","add_1020_1023_1024.in1"], + ["add_1024_1027_1028.in0","add_1020_1023_1024.out"], + ["mult_middle_10267_1027.out","add_1024_1027_1028.in1"], + ["add_1028_1029_1030.in0","add_1024_1027_1028.out"], + ["const_n40__1029.out","add_1028_1029_1030.in1"], + ["self.out_corrected_stencil","add_1028_1029_1030.out"], + ["mult_middle_1022n103_1023.in1","const_n103_n103$1.out"], + ["umin_demosaicked_1_stencil_5_1017_1021.in1","const_p10000__1017$1.out"], + ["umin_demosaicked_1_stencil_6_1017_1025.in1","const_p10000__1017$2.out"], + ["umin_demosaicked_1_stencil_4_1017_1018.in1","const_p10000__1017.out"], + ["mult_middle_1019549_1020.in1","const_p549_549$1.out"], + ["mult_middle_10267_1027.in1","const_p7_7$1.out"], + ["umin_demosaicked_1_stencil_4_1017_1018.out","mult_middle_1019549_1020.in0"], + ["umin_demosaicked_1_stencil_5_1017_1021.out","mult_middle_1022n103_1023.in0"], + ["umin_demosaicked_1_stencil_6_1017_1025.out","mult_middle_10267_1027.in0"], + ["umin_demosaicked_1_stencil_4_1017_1018.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_5_1017_1021.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_6_1017_1025.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_2":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1079_1082_1083":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1083_1086_1087":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1087_1088_1089":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1088":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__1076":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1076$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1076$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_1078n96_1079":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1081373_1082":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_108562_1086":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_7_1076_1077":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_8_1076_1080":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_9_1076_1084":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1078n96_1079.out","add_1079_1082_1083.in0"], + ["mult_middle_1081373_1082.out","add_1079_1082_1083.in1"], + ["add_1083_1086_1087.in0","add_1079_1082_1083.out"], + ["mult_middle_108562_1086.out","add_1083_1086_1087.in1"], + ["add_1087_1088_1089.in0","add_1083_1086_1087.out"], + ["const_n29__1088.out","add_1087_1088_1089.in1"], + ["self.out_corrected_stencil","add_1087_1088_1089.out"], + ["mult_middle_1078n96_1079.in1","const_n96_n96.out"], + ["umin_demosaicked_1_stencil_8_1076_1080.in1","const_p10000__1076$1.out"], + ["umin_demosaicked_1_stencil_9_1076_1084.in1","const_p10000__1076$2.out"], + ["umin_demosaicked_1_stencil_7_1076_1077.in1","const_p10000__1076.out"], + ["mult_middle_1081373_1082.in1","const_p373_373.out"], + ["mult_middle_108562_1086.in1","const_p62_62.out"], + ["umin_demosaicked_1_stencil_7_1076_1077.out","mult_middle_1078n96_1079.in0"], + ["umin_demosaicked_1_stencil_8_1076_1080.out","mult_middle_1081373_1082.in0"], + ["umin_demosaicked_1_stencil_9_1076_1084.out","mult_middle_108562_1086.in0"], + ["umin_demosaicked_1_stencil_7_1076_1077.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_8_1076_1080.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_9_1076_1084.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_3":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1137_1140_1141":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1141_1144_1145":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1145_1146_1147":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1146":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__1134":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1134$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1134$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_1136n96_1137":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1139373_1140":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_114362_1144":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_10_1134_1135":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_11_1134_1138":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_12_1134_1142":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1136n96_1137.out","add_1137_1140_1141.in0"], + ["mult_middle_1139373_1140.out","add_1137_1140_1141.in1"], + ["add_1141_1144_1145.in0","add_1137_1140_1141.out"], + ["mult_middle_114362_1144.out","add_1141_1144_1145.in1"], + ["add_1145_1146_1147.in0","add_1141_1144_1145.out"], + ["const_n29__1146.out","add_1145_1146_1147.in1"], + ["self.out_corrected_stencil","add_1145_1146_1147.out"], + ["mult_middle_1136n96_1137.in1","const_n96_n96$1.out"], + ["umin_demosaicked_1_stencil_11_1134_1138.in1","const_p10000__1134$1.out"], + ["umin_demosaicked_1_stencil_12_1134_1142.in1","const_p10000__1134$2.out"], + ["umin_demosaicked_1_stencil_10_1134_1135.in1","const_p10000__1134.out"], + ["mult_middle_1139373_1140.in1","const_p373_373$1.out"], + ["mult_middle_114362_1144.in1","const_p62_62$1.out"], + ["umin_demosaicked_1_stencil_10_1134_1135.out","mult_middle_1136n96_1137.in0"], + ["umin_demosaicked_1_stencil_11_1134_1138.out","mult_middle_1139373_1140.in0"], + ["umin_demosaicked_1_stencil_12_1134_1142.out","mult_middle_114362_1144.in0"], + ["umin_demosaicked_1_stencil_10_1134_1135.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_11_1134_1138.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_12_1134_1142.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_4":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1196_1199_1200":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1200_1203_1204":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1204_1205_1206":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1205":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1193":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1193$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1193$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1195n31_1196":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1198n261_1199":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1202883_1203":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_13_1193_1194":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_14_1193_1197":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_15_1193_1201":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1195n31_1196.out","add_1196_1199_1200.in0"], + ["mult_middle_1198n261_1199.out","add_1196_1199_1200.in1"], + ["add_1200_1203_1204.in0","add_1196_1199_1200.out"], + ["mult_middle_1202883_1203.out","add_1200_1203_1204.in1"], + ["add_1204_1205_1206.in0","add_1200_1203_1204.out"], + ["const_n22__1205.out","add_1204_1205_1206.in1"], + ["self.out_corrected_stencil","add_1204_1205_1206.out"], + ["mult_middle_1198n261_1199.in1","const_n261_n261.out"], + ["mult_middle_1195n31_1196.in1","const_n31_n31.out"], + ["umin_demosaicked_1_stencil_14_1193_1197.in1","const_p10000__1193$1.out"], + ["umin_demosaicked_1_stencil_15_1193_1201.in1","const_p10000__1193$2.out"], + ["umin_demosaicked_1_stencil_13_1193_1194.in1","const_p10000__1193.out"], + ["mult_middle_1202883_1203.in1","const_p883_883.out"], + ["umin_demosaicked_1_stencil_13_1193_1194.out","mult_middle_1195n31_1196.in0"], + ["umin_demosaicked_1_stencil_14_1193_1197.out","mult_middle_1198n261_1199.in0"], + ["umin_demosaicked_1_stencil_15_1193_1201.out","mult_middle_1202883_1203.in0"], + ["umin_demosaicked_1_stencil_13_1193_1194.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_14_1193_1197.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_15_1193_1201.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_5":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1254_1257_1258":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1258_1261_1262":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1262_1263_1264":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1263":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1251":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1251$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1251$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1253n31_1254":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1256n261_1257":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1260883_1261":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_16_1251_1252":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_17_1251_1255":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_18_1251_1259":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1253n31_1254.out","add_1254_1257_1258.in0"], + ["mult_middle_1256n261_1257.out","add_1254_1257_1258.in1"], + ["add_1258_1261_1262.in0","add_1254_1257_1258.out"], + ["mult_middle_1260883_1261.out","add_1258_1261_1262.in1"], + ["add_1262_1263_1264.in0","add_1258_1261_1262.out"], + ["const_n22__1263.out","add_1262_1263_1264.in1"], + ["self.out_corrected_stencil","add_1262_1263_1264.out"], + ["mult_middle_1256n261_1257.in1","const_n261_n261$1.out"], + ["mult_middle_1253n31_1254.in1","const_n31_n31$1.out"], + ["umin_demosaicked_1_stencil_17_1251_1255.in1","const_p10000__1251$1.out"], + ["umin_demosaicked_1_stencil_18_1251_1259.in1","const_p10000__1251$2.out"], + ["umin_demosaicked_1_stencil_16_1251_1252.in1","const_p10000__1251.out"], + ["mult_middle_1260883_1261.in1","const_p883_883$1.out"], + ["umin_demosaicked_1_stencil_16_1251_1252.out","mult_middle_1253n31_1254.in0"], + ["umin_demosaicked_1_stencil_17_1251_1255.out","mult_middle_1256n261_1257.in0"], + ["umin_demosaicked_1_stencil_18_1251_1259.out","mult_middle_1260883_1261.in0"], + ["umin_demosaicked_1_stencil_16_1251_1252.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_17_1251_1255.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_18_1251_1259.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_curved_stencil":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__3347":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__3345":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_3346_3347_3348":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_1_3345_3346":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_3346_3347_3348.in1","const_p0__3347.out"], + ["smin_corrected_stencil_1_3345_3346.in1","const_p1023__3345.out"], + ["smax_3346_3347_3348.out","rom_curvea0.raddr"], + ["self.out_curved_stencil","rom_curvea0.rdata"], + ["rom_curvea0_ren.out","rom_curvea0.ren"], + ["smin_corrected_stencil_1_3345_3346.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_1_3345_3346.out","smax_3346_3347_3348.in0"] + ] + }, + "hcompute_curved_stencil_1":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__4393":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__4391":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$1":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$1_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_4392_4393_4394":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_2_4391_4392":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_4392_4393_4394.in1","const_p0__4393.out"], + ["smin_corrected_stencil_2_4391_4392.in1","const_p1023__4391.out"], + ["smax_4392_4393_4394.out","rom_curvea0$1.raddr"], + ["self.out_curved_stencil","rom_curvea0$1.rdata"], + ["rom_curvea0$1_ren.out","rom_curvea0$1.ren"], + ["smin_corrected_stencil_2_4391_4392.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_2_4391_4392.out","smax_4392_4393_4394.in0"] + ] + }, + "hcompute_curved_stencil_2":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__5440":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__5438":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$2":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$2_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_5439_5440_5441":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_3_5438_5439":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_5439_5440_5441.in1","const_p0__5440.out"], + ["smin_corrected_stencil_3_5438_5439.in1","const_p1023__5438.out"], + ["smax_5439_5440_5441.out","rom_curvea0$2.raddr"], + ["self.out_curved_stencil","rom_curvea0$2.rdata"], + ["rom_curvea0$2_ren.out","rom_curvea0$2.ren"], + ["smin_corrected_stencil_3_5438_5439.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_3_5438_5439.out","smax_5439_5440_5441.in0"] + ] + }, + "hcompute_curved_stencil_3":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__6486":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__6484":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$3":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$3_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_6485_6486_6487":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_4_6484_6485":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_6485_6486_6487.in1","const_p0__6486.out"], + ["smin_corrected_stencil_4_6484_6485.in1","const_p1023__6484.out"], + ["smax_6485_6486_6487.out","rom_curvea0$3.raddr"], + ["self.out_curved_stencil","rom_curvea0$3.rdata"], + ["rom_curvea0$3_ren.out","rom_curvea0$3.ren"], + ["smin_corrected_stencil_4_6484_6485.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_4_6484_6485.out","smax_6485_6486_6487.in0"] + ] + }, + "hcompute_curved_stencil_4":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__7533":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__7531":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$4":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$4_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_7532_7533_7534":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_5_7531_7532":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_7532_7533_7534.in1","const_p0__7533.out"], + ["smin_corrected_stencil_5_7531_7532.in1","const_p1023__7531.out"], + ["smax_7532_7533_7534.out","rom_curvea0$4.raddr"], + ["self.out_curved_stencil","rom_curvea0$4.rdata"], + ["rom_curvea0$4_ren.out","rom_curvea0$4.ren"], + ["smin_corrected_stencil_5_7531_7532.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_5_7531_7532.out","smax_7532_7533_7534.in0"] + ] + }, + "hcompute_curved_stencil_5":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__8579":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__8577":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$5":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$5_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_8578_8579_8580":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_6_8577_8578":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_8578_8579_8580.in1","const_p0__8579.out"], + ["smin_corrected_stencil_6_8577_8578.in1","const_p1023__8577.out"], + ["smax_8578_8579_8580.out","rom_curvea0$5.raddr"], + ["self.out_curved_stencil","rom_curvea0$5.rdata"], + ["rom_curvea0$5_ren.out","rom_curvea0$5.ren"], + ["smin_corrected_stencil_6_8577_8578.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_6_8577_8578.out","smax_8578_8579_8580.in0"] + ] + }, + "hcompute_demosaicked_1_stencil":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_r_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_y_849_850":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__849":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8500_851":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_851_r_gr_stencil_1_r_b_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_849_850.in0"], + ["const_p1__849.out","and_demosaicked_1_s0_y_849_850.in1"], + ["eq_8500_851.in0","and_demosaicked_1_s0_y_849_850.out"], + ["eq_8500_851.in1","const_p0_0.out"], + ["mux_851_r_gr_stencil_1_r_b_stencil_1.sel","eq_8500_851.out"], + ["self.in0_r_b_stencil.0","mux_851_r_gr_stencil_1_r_b_stencil_1.in0"], + ["self.in1_r_gr_stencil.0","mux_851_r_gr_stencil_1_r_b_stencil_1.in1"], + ["self.out_demosaicked_1_stencil","mux_851_r_gr_stencil_1_r_b_stencil_1.out"] + ] + }, + "hcompute_demosaicked_1_stencil_1":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_y_863_864":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__863":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8640_865":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_865_g_gr_stencil_7_g_b_stencil_10":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_863_864.in0"], + ["const_p1__863.out","and_demosaicked_1_s0_y_863_864.in1"], + ["eq_8640_865.in0","and_demosaicked_1_s0_y_863_864.out"], + ["eq_8640_865.in1","const_p0_0$1.out"], + ["mux_865_g_gr_stencil_7_g_b_stencil_10.sel","eq_8640_865.out"], + ["self.in0_g_b_stencil.0","mux_865_g_gr_stencil_7_g_b_stencil_10.in0"], + ["self.in1_g_gr_stencil.0","mux_865_g_gr_stencil_7_g_b_stencil_10.in1"], + ["self.out_demosaicked_1_stencil","mux_865_g_gr_stencil_7_g_b_stencil_10.out"] + ] + }, + "hcompute_demosaicked_1_stencil_2":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_b_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_y_879_880":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__879":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8800_881":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_881_b_gr_stencil_1_b_b_stencil_9":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_879_880.in0"], + ["const_p1__879.out","and_demosaicked_1_s0_y_879_880.in1"], + ["eq_8800_881.in0","and_demosaicked_1_s0_y_879_880.out"], + ["eq_8800_881.in1","const_p0_0$2.out"], + ["mux_881_b_gr_stencil_1_b_b_stencil_9.sel","eq_8800_881.out"], + ["self.in0_b_b_stencil.0","mux_881_b_gr_stencil_1_b_b_stencil_9.in0"], + ["self.in1_b_gr_stencil.0","mux_881_b_gr_stencil_1_b_b_stencil_9.in1"], + ["self.out_demosaicked_1_stencil","mux_881_b_gr_stencil_1_b_b_stencil_9.out"] + ] + }, + "hcompute_demosaicked_1_stencil_3":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_r_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_y_894_895":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__894":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8950_896":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_896_r_r_stencil_9_r_gb_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_894_895.in0"], + ["const_p1__894.out","and_demosaicked_1_s0_y_894_895.in1"], + ["eq_8950_896.in0","and_demosaicked_1_s0_y_894_895.out"], + ["eq_8950_896.in1","const_p0_0$3.out"], + ["mux_896_r_r_stencil_9_r_gb_stencil_1.sel","eq_8950_896.out"], + ["self.in0_r_gb_stencil.0","mux_896_r_r_stencil_9_r_gb_stencil_1.in0"], + ["self.in1_r_r_stencil.0","mux_896_r_r_stencil_9_r_gb_stencil_1.in1"], + ["self.out_demosaicked_1_stencil","mux_896_r_r_stencil_9_r_gb_stencil_1.out"] + ] + }, + "hcompute_demosaicked_1_stencil_4":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_y_910_911":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__910":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_9110_912":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_912_g_r_stencil_10_g_gb_stencil_7":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_910_911.in0"], + ["const_p1__910.out","and_demosaicked_1_s0_y_910_911.in1"], + ["eq_9110_912.in0","and_demosaicked_1_s0_y_910_911.out"], + ["eq_9110_912.in1","const_p0_0$4.out"], + ["mux_912_g_r_stencil_10_g_gb_stencil_7.sel","eq_9110_912.out"], + ["self.in0_g_gb_stencil.0","mux_912_g_r_stencil_10_g_gb_stencil_7.in0"], + ["self.in1_g_r_stencil.0","mux_912_g_r_stencil_10_g_gb_stencil_7.in1"], + ["self.out_demosaicked_1_stencil","mux_912_g_r_stencil_10_g_gb_stencil_7.out"] + ] + }, + "hcompute_demosaicked_1_stencil_5":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_b_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_y",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_y_927_928":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__927":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_9280_929":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_929_b_r_stencil_1_b_gb_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_y","and_demosaicked_1_s0_y_927_928.in0"], + ["const_p1__927.out","and_demosaicked_1_s0_y_927_928.in1"], + ["eq_9280_929.in0","and_demosaicked_1_s0_y_927_928.out"], + ["eq_9280_929.in1","const_p0_0$5.out"], + ["mux_929_b_r_stencil_1_b_gb_stencil_1.sel","eq_9280_929.out"], + ["self.in0_b_gb_stencil.0","mux_929_b_r_stencil_1_b_gb_stencil_1.in0"], + ["self.in1_b_r_stencil.0","mux_929_b_r_stencil_1_b_gb_stencil_1.in1"], + ["self.out_demosaicked_1_stencil","mux_929_b_r_stencil_1_b_gb_stencil_1.out"] + ] + }, + "hcompute_denoised_1_stencil":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_2_356_357":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_3_355_356":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_355":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_1_357_358":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_357_358.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_2_356_357.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_355_356.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_355.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_355.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_357_358.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_355_356.out","umax_hw_input_global_wrapper_global_wrapper_stencil_2_356_357.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_357_358.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_2_356_357.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_355.out","umax_hw_input_global_wrapper_global_wrapper_stencil_3_355_356.in1"] + ] + }, + "hcompute_denoised_1_stencil_1":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_7_380_381":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_8_379_380":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_379":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_6_381_382":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_379.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_381_382.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_7_380_381.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_379_380.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_379.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_381_382.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_379_380.out","umax_hw_input_global_wrapper_global_wrapper_stencil_7_380_381.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_381_382.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_7_380_381.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_379.out","umax_hw_input_global_wrapper_global_wrapper_stencil_8_379_380.in1"] + ] + }, + "hcompute_g_b_stencil":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_1_g_gb_stencil_2_472":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_1_g_gr_stencil_2_473":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_1_g_gb_stencil_2_475":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_1_g_gr_stencil_2_478":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__476":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__476$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_475_476_477":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_478_476_479":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_474_477_479":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_472_473_474":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_1_g_gb_stencil_2_472.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_1_g_gb_stencil_2_472.in1"], + ["ult_472_473_474.in0","absd_g_gb_stencil_1_g_gb_stencil_2_472.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_1_g_gr_stencil_2_473.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_1_g_gr_stencil_2_473.in1"], + ["ult_472_473_474.in1","absd_g_gr_stencil_1_g_gr_stencil_2_473.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_1_g_gb_stencil_2_475.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_1_g_gb_stencil_2_475.in1"], + ["lshr_475_476_477.in0","add_g_gb_stencil_1_g_gb_stencil_2_475.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_1_g_gr_stencil_2_478.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_1_g_gr_stencil_2_478.in1"], + ["lshr_478_476_479.in0","add_g_gr_stencil_1_g_gr_stencil_2_478.out"], + ["lshr_478_476_479.in1","const_p1__476$1.out"], + ["lshr_475_476_477.in1","const_p1__476.out"], + ["mux_474_477_479.in1","lshr_475_476_477.out"], + ["mux_474_477_479.in0","lshr_478_476_479.out"], + ["self.out_g_b_stencil","mux_474_477_479.out"], + ["ult_472_473_474.out","mux_474_477_479.sel"] + ] + }, + "hcompute_g_gb_stencil":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gb_stencil_1":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil_1":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_r_stencil":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_4_g_gb_stencil_5_584":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_4_g_gr_stencil_5_583":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_4_g_gb_stencil_5_589":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_4_g_gr_stencil_5_586":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__587":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__587$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_586_587_588":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_589_587_590":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_585_588_590":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_583_584_585":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_4_g_gb_stencil_5_584.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_4_g_gb_stencil_5_584.in1"], + ["ult_583_584_585.in1","absd_g_gb_stencil_4_g_gb_stencil_5_584.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_4_g_gr_stencil_5_583.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_4_g_gr_stencil_5_583.in1"], + ["ult_583_584_585.in0","absd_g_gr_stencil_4_g_gr_stencil_5_583.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_4_g_gb_stencil_5_589.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_4_g_gb_stencil_5_589.in1"], + ["lshr_589_587_590.in0","add_g_gb_stencil_4_g_gb_stencil_5_589.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_4_g_gr_stencil_5_586.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_4_g_gr_stencil_5_586.in1"], + ["lshr_586_587_588.in0","add_g_gr_stencil_4_g_gr_stencil_5_586.out"], + ["lshr_589_587_590.in1","const_p1__587$1.out"], + ["lshr_586_587_588.in1","const_p1__587.out"], + ["mux_585_588_590.in1","lshr_586_587_588.out"], + ["mux_585_588_590.in0","lshr_589_587_590.out"], + ["self.out_g_r_stencil","mux_585_588_590.out"], + ["ult_583_584_585.out","mux_585_588_590.sel"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_4":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_5":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_4":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_5":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_r_b_stencil":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_1_r_r_stencil_2_735":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_3_r_r_stencil_4_736":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_740_741":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_746_747":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_2_g_r_stencil_3_742":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_4_g_r_stencil_5_748":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_1_r_r_stencil_2_738":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_3_r_r_stencil_4_745":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__739":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__739$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__739$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__739$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_738_739_740":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_742_739_743":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_745_739_746":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_748_739_749":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_737_744_750":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_741_743_744":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_747_749_750":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_735_736_737":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.0","absd_r_r_stencil_1_r_r_stencil_2_735.in0"], + ["self.in2_r_r_stencil.1","absd_r_r_stencil_1_r_r_stencil_2_735.in1"], + ["ult_735_736_737.in0","absd_r_r_stencil_1_r_r_stencil_2_735.out"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_3_r_r_stencil_4_736.in0"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_3_r_r_stencil_4_736.in1"], + ["ult_735_736_737.in1","absd_r_r_stencil_3_r_r_stencil_4_736.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_740_741.in0"], + ["lshr_738_739_740.out","add_g_b_stencil_9_740_741.in1"], + ["sub_741_743_744.in0","add_g_b_stencil_9_740_741.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_746_747.in0"], + ["lshr_745_739_746.out","add_g_b_stencil_9_746_747.in1"], + ["sub_747_749_750.in0","add_g_b_stencil_9_746_747.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_2_g_r_stencil_3_742.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_2_g_r_stencil_3_742.in1"], + ["lshr_742_739_743.in0","add_g_r_stencil_2_g_r_stencil_3_742.out"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_4_g_r_stencil_5_748.in0"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_4_g_r_stencil_5_748.in1"], + ["lshr_748_739_749.in0","add_g_r_stencil_4_g_r_stencil_5_748.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_1_r_r_stencil_2_738.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_1_r_r_stencil_2_738.in1"], + ["lshr_738_739_740.in0","add_r_r_stencil_1_r_r_stencil_2_738.out"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_3_r_r_stencil_4_745.in0"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_3_r_r_stencil_4_745.in1"], + ["lshr_745_739_746.in0","add_r_r_stencil_3_r_r_stencil_4_745.out"], + ["lshr_742_739_743.in1","const_p1__739$1.out"], + ["lshr_745_739_746.in1","const_p1__739$2.out"], + ["lshr_748_739_749.in1","const_p1__739$3.out"], + ["lshr_738_739_740.in1","const_p1__739.out"], + ["sub_741_743_744.in1","lshr_742_739_743.out"], + ["sub_747_749_750.in1","lshr_748_739_749.out"], + ["sub_747_749_750.out","mux_737_744_750.in0"], + ["sub_741_743_744.out","mux_737_744_750.in1"], + ["self.out_r_b_stencil","mux_737_744_750.out"], + ["ult_735_736_737.out","mux_737_744_750.sel"] + ] + }, + "hcompute_r_gb_stencil":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gb_stencil_6_798_799":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_6_g_r_stencil_7_800":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_5_r_r_stencil_6_796":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__797":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__797$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_796_797_798":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_800_797_801":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_799_801_802":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_6_798_799.in0"], + ["lshr_796_797_798.out","add_g_gb_stencil_6_798_799.in1"], + ["sub_799_801_802.in0","add_g_gb_stencil_6_798_799.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_6_g_r_stencil_7_800.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_6_g_r_stencil_7_800.in1"], + ["lshr_800_797_801.in0","add_g_r_stencil_6_g_r_stencil_7_800.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_5_r_r_stencil_6_796.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_5_r_r_stencil_6_796.in1"], + ["lshr_796_797_798.in0","add_r_r_stencil_5_r_r_stencil_6_796.out"], + ["lshr_800_797_801.in1","const_p1__797$1.out"], + ["lshr_796_797_798.in1","const_p1__797.out"], + ["sub_799_801_802.in1","lshr_800_797_801.out"], + ["sub_799_801_802.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gr_stencil":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gr_stencil_6_827_828":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_8_g_r_stencil_9_829":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_7_r_r_stencil_8_825":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__826":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__826$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_825_826_827":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_829_826_830":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_828_830_831":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_6_827_828.in0"], + ["lshr_825_826_827.out","add_g_gr_stencil_6_827_828.in1"], + ["sub_828_830_831.in0","add_g_gr_stencil_6_827_828.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_8_g_r_stencil_9_829.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_8_g_r_stencil_9_829.in1"], + ["lshr_829_826_830.in0","add_g_r_stencil_8_g_r_stencil_9_829.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_7_r_r_stencil_8_825.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_7_r_r_stencil_8_825.in1"], + ["lshr_825_826_827.in0","add_r_r_stencil_7_r_r_stencil_8_825.out"], + ["lshr_829_826_830.in1","const_p1__826$1.out"], + ["lshr_825_826_827.in1","const_p1__826.out"], + ["sub_828_830_831.in1","lshr_829_826_830.out"], + ["sub_828_830_831.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_r_stencil":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_r_r_stencil_1":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/camera_pipeline_unrolly_compute.json b/coreir_compute/camera_pipeline_unrolly_compute.json new file mode 100644 index 000000000..11021b5b4 --- /dev/null +++ b/coreir_compute/camera_pipeline_unrolly_compute.json @@ -0,0 +1,2012 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_b_b_stencil":{ + "type":["Record",[ + ["out_b_b_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_b_b_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_b_gb_stencil":{ + "type":["Record",[ + ["out_b_gb_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_1_b_b_stencil_2_483":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_1_g_b_stencil_2_487":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_3_485_486":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__484":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__484$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_483_484_485":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_487_484_488":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_486_488_489":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_1_b_b_stencil_2_483.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_1_b_b_stencil_2_483.in1"], + ["lshr_483_484_485.in0","add_b_b_stencil_1_b_b_stencil_2_483.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_1_g_b_stencil_2_487.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_1_g_b_stencil_2_487.in1"], + ["lshr_487_484_488.in0","add_g_b_stencil_1_g_b_stencil_2_487.out"], + ["self.in2_g_gb_stencil.0","add_g_gb_stencil_3_485_486.in0"], + ["lshr_483_484_485.out","add_g_gb_stencil_3_485_486.in1"], + ["sub_486_488_489.in0","add_g_gb_stencil_3_485_486.out"], + ["lshr_487_484_488.in1","const_p1__484$1.out"], + ["lshr_483_484_485.in1","const_p1__484.out"], + ["sub_486_488_489.in1","lshr_487_484_488.out"], + ["sub_486_488_489.out","self.out_b_gb_stencil"] + ] + }, + "hcompute_b_gr_stencil":{ + "type":["Record",[ + ["out_b_gr_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_b_b_stencil_3_b_b_stencil_4_512":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_3_g_b_stencil_4_516":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_3_514_515":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__513":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__513$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_512_513_514":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_516_513_517":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_515_517_518":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","add_b_b_stencil_3_b_b_stencil_4_512.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_3_b_b_stencil_4_512.in1"], + ["lshr_512_513_514.in0","add_b_b_stencil_3_b_b_stencil_4_512.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_3_g_b_stencil_4_516.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_3_g_b_stencil_4_516.in1"], + ["lshr_516_513_517.in0","add_g_b_stencil_3_g_b_stencil_4_516.out"], + ["self.in2_g_gr_stencil.0","add_g_gr_stencil_3_514_515.in0"], + ["lshr_512_513_514.out","add_g_gr_stencil_3_514_515.in1"], + ["sub_515_517_518.in0","add_g_gr_stencil_3_514_515.out"], + ["lshr_516_513_517.in1","const_p1__513$1.out"], + ["lshr_512_513_514.in1","const_p1__513.out"], + ["sub_515_517_518.in1","lshr_516_513_517.out"], + ["sub_515_517_518.out","self.out_b_gr_stencil"] + ] + }, + "hcompute_b_r_stencil":{ + "type":["Record",[ + ["out_b_r_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in1_g_b_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_g_r_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_b_b_stencil_5_b_b_stencil_6_612":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_b_b_stencil_7_b_b_stencil_8_613":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_5_b_b_stencil_6_615":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_b_b_stencil_7_b_b_stencil_8_622":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_5_g_b_stencil_6_619":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_7_g_b_stencil_8_625":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_617_618":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_1_623_624":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__616":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__616$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__616$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__616$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_615_616_617":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_619_616_620":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_622_616_623":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_625_616_626":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_614_621_627":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_618_620_621":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_624_626_627":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_612_613_614":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_b_b_stencil.0","absd_b_b_stencil_5_b_b_stencil_6_612.in0"], + ["self.in0_b_b_stencil.1","absd_b_b_stencil_5_b_b_stencil_6_612.in1"], + ["ult_612_613_614.in0","absd_b_b_stencil_5_b_b_stencil_6_612.out"], + ["self.in0_b_b_stencil.2","absd_b_b_stencil_7_b_b_stencil_8_613.in0"], + ["self.in0_b_b_stencil.3","absd_b_b_stencil_7_b_b_stencil_8_613.in1"], + ["ult_612_613_614.in1","absd_b_b_stencil_7_b_b_stencil_8_613.out"], + ["self.in0_b_b_stencil.0","add_b_b_stencil_5_b_b_stencil_6_615.in0"], + ["self.in0_b_b_stencil.1","add_b_b_stencil_5_b_b_stencil_6_615.in1"], + ["lshr_615_616_617.in0","add_b_b_stencil_5_b_b_stencil_6_615.out"], + ["self.in0_b_b_stencil.2","add_b_b_stencil_7_b_b_stencil_8_622.in0"], + ["self.in0_b_b_stencil.3","add_b_b_stencil_7_b_b_stencil_8_622.in1"], + ["lshr_622_616_623.in0","add_b_b_stencil_7_b_b_stencil_8_622.out"], + ["self.in1_g_b_stencil.0","add_g_b_stencil_5_g_b_stencil_6_619.in0"], + ["self.in1_g_b_stencil.1","add_g_b_stencil_5_g_b_stencil_6_619.in1"], + ["lshr_619_616_620.in0","add_g_b_stencil_5_g_b_stencil_6_619.out"], + ["self.in1_g_b_stencil.2","add_g_b_stencil_7_g_b_stencil_8_625.in0"], + ["self.in1_g_b_stencil.3","add_g_b_stencil_7_g_b_stencil_8_625.in1"], + ["lshr_625_616_626.in0","add_g_b_stencil_7_g_b_stencil_8_625.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_617_618.in0"], + ["lshr_615_616_617.out","add_g_r_stencil_1_617_618.in1"], + ["sub_618_620_621.in0","add_g_r_stencil_1_617_618.out"], + ["self.in2_g_r_stencil.0","add_g_r_stencil_1_623_624.in0"], + ["lshr_622_616_623.out","add_g_r_stencil_1_623_624.in1"], + ["sub_624_626_627.in0","add_g_r_stencil_1_623_624.out"], + ["lshr_619_616_620.in1","const_p1__616$1.out"], + ["lshr_622_616_623.in1","const_p1__616$2.out"], + ["lshr_625_616_626.in1","const_p1__616$3.out"], + ["lshr_615_616_617.in1","const_p1__616.out"], + ["sub_618_620_621.in1","lshr_619_616_620.out"], + ["sub_624_626_627.in1","lshr_625_616_626.out"], + ["sub_624_626_627.out","mux_614_621_627.in0"], + ["sub_618_620_621.out","mux_614_621_627.in1"], + ["self.out_b_r_stencil","mux_614_621_627.out"], + ["ult_612_613_614.out","mux_614_621_627.sel"] + ] + }, + "hcompute_corrected_stencil":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_927_930_931":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_931_934_935":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_935_936_937":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__936":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__924":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__924$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__924$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_926549_927":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_929n103_930":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_9337_934":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_1_924_925":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_2_924_928":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_3_924_932":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_926549_927.out","add_927_930_931.in0"], + ["mult_middle_929n103_930.out","add_927_930_931.in1"], + ["add_931_934_935.in0","add_927_930_931.out"], + ["mult_middle_9337_934.out","add_931_934_935.in1"], + ["add_935_936_937.in0","add_931_934_935.out"], + ["const_n40__936.out","add_935_936_937.in1"], + ["self.out_corrected_stencil","add_935_936_937.out"], + ["mult_middle_929n103_930.in1","const_n103_n103.out"], + ["umin_demosaicked_1_stencil_2_924_928.in1","const_p10000__924$1.out"], + ["umin_demosaicked_1_stencil_3_924_932.in1","const_p10000__924$2.out"], + ["umin_demosaicked_1_stencil_1_924_925.in1","const_p10000__924.out"], + ["mult_middle_926549_927.in1","const_p549_549.out"], + ["mult_middle_9337_934.in1","const_p7_7.out"], + ["umin_demosaicked_1_stencil_1_924_925.out","mult_middle_926549_927.in0"], + ["umin_demosaicked_1_stencil_2_924_928.out","mult_middle_929n103_930.in0"], + ["umin_demosaicked_1_stencil_3_924_932.out","mult_middle_9337_934.in0"], + ["umin_demosaicked_1_stencil_1_924_925.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_2_924_928.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_3_924_932.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_1":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_985_988_989":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_989_992_993":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_993_994_995":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__994":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__982":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__982$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__982$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_984n96_985":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_987373_988":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_99162_992":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_4_982_983":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_5_982_986":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_6_982_990":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_984n96_985.out","add_985_988_989.in0"], + ["mult_middle_987373_988.out","add_985_988_989.in1"], + ["add_989_992_993.in0","add_985_988_989.out"], + ["mult_middle_99162_992.out","add_989_992_993.in1"], + ["add_993_994_995.in0","add_989_992_993.out"], + ["const_n29__994.out","add_993_994_995.in1"], + ["self.out_corrected_stencil","add_993_994_995.out"], + ["mult_middle_984n96_985.in1","const_n96_n96.out"], + ["umin_demosaicked_1_stencil_5_982_986.in1","const_p10000__982$1.out"], + ["umin_demosaicked_1_stencil_6_982_990.in1","const_p10000__982$2.out"], + ["umin_demosaicked_1_stencil_4_982_983.in1","const_p10000__982.out"], + ["mult_middle_987373_988.in1","const_p373_373.out"], + ["mult_middle_99162_992.in1","const_p62_62.out"], + ["umin_demosaicked_1_stencil_4_982_983.out","mult_middle_984n96_985.in0"], + ["umin_demosaicked_1_stencil_5_982_986.out","mult_middle_987373_988.in0"], + ["umin_demosaicked_1_stencil_6_982_990.out","mult_middle_99162_992.in0"], + ["umin_demosaicked_1_stencil_4_982_983.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_5_982_986.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_6_982_990.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_2":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1043_1046_1047":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1047_1050_1051":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1051_1052_1053":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1052":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1040":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1040$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1040$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1042n31_1043":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1045n261_1046":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1049883_1050":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_7_1040_1041":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_8_1040_1044":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_9_1040_1048":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1042n31_1043.out","add_1043_1046_1047.in0"], + ["mult_middle_1045n261_1046.out","add_1043_1046_1047.in1"], + ["add_1047_1050_1051.in0","add_1043_1046_1047.out"], + ["mult_middle_1049883_1050.out","add_1047_1050_1051.in1"], + ["add_1051_1052_1053.in0","add_1047_1050_1051.out"], + ["const_n22__1052.out","add_1051_1052_1053.in1"], + ["self.out_corrected_stencil","add_1051_1052_1053.out"], + ["mult_middle_1045n261_1046.in1","const_n261_n261.out"], + ["mult_middle_1042n31_1043.in1","const_n31_n31.out"], + ["umin_demosaicked_1_stencil_8_1040_1044.in1","const_p10000__1040$1.out"], + ["umin_demosaicked_1_stencil_9_1040_1048.in1","const_p10000__1040$2.out"], + ["umin_demosaicked_1_stencil_7_1040_1041.in1","const_p10000__1040.out"], + ["mult_middle_1049883_1050.in1","const_p883_883.out"], + ["umin_demosaicked_1_stencil_7_1040_1041.out","mult_middle_1042n31_1043.in0"], + ["umin_demosaicked_1_stencil_8_1040_1044.out","mult_middle_1045n261_1046.in0"], + ["umin_demosaicked_1_stencil_9_1040_1048.out","mult_middle_1049883_1050.in0"], + ["umin_demosaicked_1_stencil_7_1040_1041.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_8_1040_1044.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_9_1040_1048.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_3":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1101_1104_1105":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1105_1108_1109":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1109_1110_1111":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n103_n103$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff99"]} + }, + "const_n40__1110":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffd8"]} + }, + "const_p10000__1098":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1098$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1098$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p549_549$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0225"]} + }, + "const_p7_7$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mult_middle_1100549_1101":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1103n103_1104":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_11077_1108":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_10_1098_1099":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_11_1098_1102":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_12_1098_1106":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1100549_1101.out","add_1101_1104_1105.in0"], + ["mult_middle_1103n103_1104.out","add_1101_1104_1105.in1"], + ["add_1105_1108_1109.in0","add_1101_1104_1105.out"], + ["mult_middle_11077_1108.out","add_1105_1108_1109.in1"], + ["add_1109_1110_1111.in0","add_1105_1108_1109.out"], + ["const_n40__1110.out","add_1109_1110_1111.in1"], + ["self.out_corrected_stencil","add_1109_1110_1111.out"], + ["mult_middle_1103n103_1104.in1","const_n103_n103$1.out"], + ["umin_demosaicked_1_stencil_11_1098_1102.in1","const_p10000__1098$1.out"], + ["umin_demosaicked_1_stencil_12_1098_1106.in1","const_p10000__1098$2.out"], + ["umin_demosaicked_1_stencil_10_1098_1099.in1","const_p10000__1098.out"], + ["mult_middle_1100549_1101.in1","const_p549_549$1.out"], + ["mult_middle_11077_1108.in1","const_p7_7$1.out"], + ["umin_demosaicked_1_stencil_10_1098_1099.out","mult_middle_1100549_1101.in0"], + ["umin_demosaicked_1_stencil_11_1098_1102.out","mult_middle_1103n103_1104.in0"], + ["umin_demosaicked_1_stencil_12_1098_1106.out","mult_middle_11077_1108.in0"], + ["umin_demosaicked_1_stencil_10_1098_1099.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_11_1098_1102.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_12_1098_1106.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_4":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1160_1163_1164":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1164_1167_1168":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1168_1169_1170":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n29__1169":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe3"]} + }, + "const_n96_n96$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffa0"]} + }, + "const_p10000__1157":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1157$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1157$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p373_373$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0175"]} + }, + "const_p62_62$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h003e"]} + }, + "mult_middle_1159n96_1160":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1162373_1163":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_116662_1167":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_13_1157_1158":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_14_1157_1161":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_15_1157_1165":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1159n96_1160.out","add_1160_1163_1164.in0"], + ["mult_middle_1162373_1163.out","add_1160_1163_1164.in1"], + ["add_1164_1167_1168.in0","add_1160_1163_1164.out"], + ["mult_middle_116662_1167.out","add_1164_1167_1168.in1"], + ["add_1168_1169_1170.in0","add_1164_1167_1168.out"], + ["const_n29__1169.out","add_1168_1169_1170.in1"], + ["self.out_corrected_stencil","add_1168_1169_1170.out"], + ["mult_middle_1159n96_1160.in1","const_n96_n96$1.out"], + ["umin_demosaicked_1_stencil_14_1157_1161.in1","const_p10000__1157$1.out"], + ["umin_demosaicked_1_stencil_15_1157_1165.in1","const_p10000__1157$2.out"], + ["umin_demosaicked_1_stencil_13_1157_1158.in1","const_p10000__1157.out"], + ["mult_middle_1162373_1163.in1","const_p373_373$1.out"], + ["mult_middle_116662_1167.in1","const_p62_62$1.out"], + ["umin_demosaicked_1_stencil_13_1157_1158.out","mult_middle_1159n96_1160.in0"], + ["umin_demosaicked_1_stencil_14_1157_1161.out","mult_middle_1162373_1163.in0"], + ["umin_demosaicked_1_stencil_15_1157_1165.out","mult_middle_116662_1167.in0"], + ["umin_demosaicked_1_stencil_13_1157_1158.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_14_1157_1161.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_15_1157_1165.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_corrected_stencil_5":{ + "type":["Record",[ + ["out_corrected_stencil",["Array",16,"Bit"]], + ["in0_demosaicked_1_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1219_1222_1223":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1223_1226_1227":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1227_1228_1229":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n22__1228":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffea"]} + }, + "const_n261_n261$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hfefb"]} + }, + "const_n31_n31$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffe1"]} + }, + "const_p10000__1216":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1216$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p10000__1216$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h2710"]} + }, + "const_p883_883$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0373"]} + }, + "mult_middle_1218n31_1219":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1221n261_1222":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "mult_middle_1225883_1226":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_16_1216_1217":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_17_1216_1220":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + }, + "umin_demosaicked_1_stencil_18_1216_1224":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mult_middle_1218n31_1219.out","add_1219_1222_1223.in0"], + ["mult_middle_1221n261_1222.out","add_1219_1222_1223.in1"], + ["add_1223_1226_1227.in0","add_1219_1222_1223.out"], + ["mult_middle_1225883_1226.out","add_1223_1226_1227.in1"], + ["add_1227_1228_1229.in0","add_1223_1226_1227.out"], + ["const_n22__1228.out","add_1227_1228_1229.in1"], + ["self.out_corrected_stencil","add_1227_1228_1229.out"], + ["mult_middle_1221n261_1222.in1","const_n261_n261$1.out"], + ["mult_middle_1218n31_1219.in1","const_n31_n31$1.out"], + ["umin_demosaicked_1_stencil_17_1216_1220.in1","const_p10000__1216$1.out"], + ["umin_demosaicked_1_stencil_18_1216_1224.in1","const_p10000__1216$2.out"], + ["umin_demosaicked_1_stencil_16_1216_1217.in1","const_p10000__1216.out"], + ["mult_middle_1225883_1226.in1","const_p883_883$1.out"], + ["umin_demosaicked_1_stencil_16_1216_1217.out","mult_middle_1218n31_1219.in0"], + ["umin_demosaicked_1_stencil_17_1216_1220.out","mult_middle_1221n261_1222.in0"], + ["umin_demosaicked_1_stencil_18_1216_1224.out","mult_middle_1225883_1226.in0"], + ["umin_demosaicked_1_stencil_16_1216_1217.in0","self.in0_demosaicked_1_stencil.0"], + ["umin_demosaicked_1_stencil_17_1216_1220.in0","self.in0_demosaicked_1_stencil.1"], + ["umin_demosaicked_1_stencil_18_1216_1224.in0","self.in0_demosaicked_1_stencil.2"] + ] + }, + "hcompute_curved_stencil":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__3312":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__3310":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_3311_3312_3313":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_1_3310_3311":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_3311_3312_3313.in1","const_p0__3312.out"], + ["smin_corrected_stencil_1_3310_3311.in1","const_p1023__3310.out"], + ["smax_3311_3312_3313.out","rom_curvea0.raddr"], + ["self.out_curved_stencil","rom_curvea0.rdata"], + ["rom_curvea0_ren.out","rom_curvea0.ren"], + ["smin_corrected_stencil_1_3310_3311.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_1_3310_3311.out","smax_3311_3312_3313.in0"] + ] + }, + "hcompute_curved_stencil_1":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__4358":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__4356":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$1":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$1_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_4357_4358_4359":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_2_4356_4357":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_4357_4358_4359.in1","const_p0__4358.out"], + ["smin_corrected_stencil_2_4356_4357.in1","const_p1023__4356.out"], + ["smax_4357_4358_4359.out","rom_curvea0$1.raddr"], + ["self.out_curved_stencil","rom_curvea0$1.rdata"], + ["rom_curvea0$1_ren.out","rom_curvea0$1.ren"], + ["smin_corrected_stencil_2_4356_4357.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_2_4356_4357.out","smax_4357_4358_4359.in0"] + ] + }, + "hcompute_curved_stencil_2":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__5404":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__5402":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$2":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$2_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_5403_5404_5405":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_3_5402_5403":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_5403_5404_5405.in1","const_p0__5404.out"], + ["smin_corrected_stencil_3_5402_5403.in1","const_p1023__5402.out"], + ["smax_5403_5404_5405.out","rom_curvea0$2.raddr"], + ["self.out_curved_stencil","rom_curvea0$2.rdata"], + ["rom_curvea0$2_ren.out","rom_curvea0$2.ren"], + ["smin_corrected_stencil_3_5402_5403.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_3_5402_5403.out","smax_5403_5404_5405.in0"] + ] + }, + "hcompute_curved_stencil_3":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__6450":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__6448":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$3":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$3_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_6449_6450_6451":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_4_6448_6449":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_6449_6450_6451.in1","const_p0__6450.out"], + ["smin_corrected_stencil_4_6448_6449.in1","const_p1023__6448.out"], + ["smax_6449_6450_6451.out","rom_curvea0$3.raddr"], + ["self.out_curved_stencil","rom_curvea0$3.rdata"], + ["rom_curvea0$3_ren.out","rom_curvea0$3.ren"], + ["smin_corrected_stencil_4_6448_6449.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_4_6448_6449.out","smax_6449_6450_6451.in0"] + ] + }, + "hcompute_curved_stencil_4":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__7497":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__7495":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$4":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$4_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_7496_7497_7498":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_5_7495_7496":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_7496_7497_7498.in1","const_p0__7497.out"], + ["smin_corrected_stencil_5_7495_7496.in1","const_p1023__7495.out"], + ["smax_7496_7497_7498.out","rom_curvea0$4.raddr"], + ["self.out_curved_stencil","rom_curvea0$4.rdata"], + ["rom_curvea0$4_ren.out","rom_curvea0$4.ren"], + ["smin_corrected_stencil_5_7495_7496.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_5_7495_7496.out","smax_7496_7497_7498.in0"] + ] + }, + "hcompute_curved_stencil_5":{ + "type":["Record",[ + ["out_curved_stencil",["Array",16,"Bit"]], + ["in0_corrected_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__8544":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1023__8542":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h03ff"]} + }, + "rom_curvea0$5":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",1024], "width":["Int",16]}, + "modargs":{"init":["Json",[0,4,7,8,10,11,12,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25,26,27,27,28,29,29,30,31,31,32,33,33,34,34,35,36,36,37,37,38,39,39,40,40,41,41,42,42,43,44,44,45,45,46,46,47,47,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55,56,56,57,57,58,58,58,59,59,60,60,61,61,62,62,63,63,64,64,64,65,65,66,66,67,67,68,68,68,69,69,70,70,71,71,71,72,72,73,73,74,74,74,75,75,76,76,77,77,77,78,78,79,79,79,80,80,81,81,82,82,82,83,83,84,84,84,85,85,86,86,86,87,87,88,88,88,89,89,90,90,90,91,91,92,92,92,93,93,93,94,94,95,95,95,96,96,97,97,97,98,98,99,99,99,100,100,100,101,101,102,102,102,103,103,103,104,104,105,105,105,106,106,106,107,107,108,108,108,109,109,109,110,110,111,111,111,112,112,112,113,113,113,114,114,115,115,115,116,116,116,117,117,117,118,118,119,119,119,120,120,120,121,121,121,122,122,123,123,123,124,124,124,125,125,125,126,126,126,127,127,128,128,128,129,129,129,130,130,130,131,131,131,132,132,132,133,133,133,134,134,134,135,135,135,136,136,136,137,137,137,138,138,138,139,139,139,140,140,140,141,141,141,141,142,142,142,143,143,143,144,144,144,145,145,145,145,146,146,146,147,147,147,148,148,148,148,149,149,149,150,150,150,150,151,151,151,152,152,152,152,153,153,153,154,154,154,154,155,155,155,156,156,156,156,157,157,157,157,158,158,158,159,159,159,159,160,160,160,160,161,161,161,161,162,162,162,162,163,163,163,163,164,164,164,164,165,165,165,166,166,166,166,167,167,167,167,167,168,168,168,168,169,169,169,169,170,170,170,170,171,171,171,171,172,172,172,172,173,173,173,173,173,174,174,174,174,175,175,175,175,176,176,176,176,176,177,177,177,177,178,178,178,178,178,179,179,179,179,180,180,180,180,180,181,181,181,181,181,182,182,182,182,183,183,183,183,183,184,184,184,184,184,185,185,185,185,185,186,186,186,186,187,187,187,187,187,188,188,188,188,188,189,189,189,189,189,190,190,190,190,190,190,191,191,191,191,191,192,192,192,192,192,193,193,193,193,193,194,194,194,194,194,195,195,195,195,195,195,196,196,196,196,196,197,197,197,197,197,197,198,198,198,198,198,199,199,199,199,199,199,200,200,200,200,200,200,201,201,201,201,201,202,202,202,202,202,202,203,203,203,203,203,203,204,204,204,204,204,204,205,205,205,205,205,205,206,206,206,206,206,206,207,207,207,207,207,207,208,208,208,208,208,208,209,209,209,209,209,209,209,210,210,210,210,210,210,211,211,211,211,211,211,211,212,212,212,212,212,212,213,213,213,213,213,213,213,214,214,214,214,214,214,214,215,215,215,215,215,215,216,216,216,216,216,216,216,217,217,217,217,217,217,217,218,218,218,218,218,218,218,219,219,219,219,219,219,219,220,220,220,220,220,220,220,220,221,221,221,221,221,221,221,222,222,222,222,222,222,222,223,223,223,223,223,223,223,223,224,224,224,224,224,224,224,224,225,225,225,225,225,225,225,226,226,226,226,226,226,226,226,227,227,227,227,227,227,227,227,228,228,228,228,228,228,228,228,228,229,229,229,229,229,229,229,229,230,230,230,230,230,230,230,230,231,231,231,231,231,231,231,231,231,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,238,239,239,239,239,239,239,239,239,239,239,240,240,240,240,240,240,240,240,240,240,241,241,241,241,241,241,241,241,241,241,242,242,242,242,242,242,242,242,242,242,243,243,243,243,243,243,243,243,243,243,244,244,244,244,244,244,244,244,244,244,244,245,245,245,245,245,245,245,245,245,245,245,246,246,246,246,246,246,246,246,246,246,246,247,247,247,247,247,247,247,247,247,247,247,248,248,248,248,248,248,248,248,248,248,248,249,249,249,249,249,249,249,249,249,249,249,249,250,250,250,250,250,250,250,250,250,250,250,250,251,251,251,251,251,251,251,251,251,251,251,251,252,252,252,252,252,252,252,252,252,252,252,252,252,253,253,253,253,253,253,253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254,254,254,254,254,255,255,255,255,255,255,255,255,255,255,255,255,255]]} + }, + "rom_curvea0$5_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "smax_8543_8544_8545":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_corrected_stencil_6_8542_8543":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_8543_8544_8545.in1","const_p0__8544.out"], + ["smin_corrected_stencil_6_8542_8543.in1","const_p1023__8542.out"], + ["smax_8543_8544_8545.out","rom_curvea0$5.raddr"], + ["self.out_curved_stencil","rom_curvea0$5.rdata"], + ["rom_curvea0$5_ren.out","rom_curvea0$5.ren"], + ["smin_corrected_stencil_6_8542_8543.in0","self.in0_corrected_stencil.0"], + ["smin_corrected_stencil_6_8542_8543.out","smax_8543_8544_8545.in0"] + ] + }, + "hcompute_demosaicked_1_stencil":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_r_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_814_815":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__814":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8150_816":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_816_r_gr_stencil_1_r_r_stencil_9":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_814_815.in0"], + ["const_p1__814.out","and_demosaicked_1_s0_x_x_814_815.in1"], + ["eq_8150_816.in0","and_demosaicked_1_s0_x_x_814_815.out"], + ["eq_8150_816.in1","const_p0_0.out"], + ["mux_816_r_gr_stencil_1_r_r_stencil_9.sel","eq_8150_816.out"], + ["self.in1_r_r_stencil.0","mux_816_r_gr_stencil_1_r_r_stencil_9.in0"], + ["self.in0_r_gr_stencil.0","mux_816_r_gr_stencil_1_r_r_stencil_9.in1"], + ["self.out_demosaicked_1_stencil","mux_816_r_gr_stencil_1_r_r_stencil_9.out"] + ] + }, + "hcompute_demosaicked_1_stencil_1":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_829_830":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__829":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8300_831":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_831_g_gr_stencil_7_g_r_stencil_10":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_829_830.in0"], + ["const_p1__829.out","and_demosaicked_1_s0_x_x_829_830.in1"], + ["eq_8300_831.in0","and_demosaicked_1_s0_x_x_829_830.out"], + ["eq_8300_831.in1","const_p0_0$1.out"], + ["mux_831_g_gr_stencil_7_g_r_stencil_10.sel","eq_8300_831.out"], + ["self.in1_g_r_stencil.0","mux_831_g_gr_stencil_7_g_r_stencil_10.in0"], + ["self.in0_g_gr_stencil.0","mux_831_g_gr_stencil_7_g_r_stencil_10.in1"], + ["self.out_demosaicked_1_stencil","mux_831_g_gr_stencil_7_g_r_stencil_10.out"] + ] + }, + "hcompute_demosaicked_1_stencil_2":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_b_r_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_845_846":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__845":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8460_847":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_847_b_gr_stencil_1_b_r_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_845_846.in0"], + ["const_p1__845.out","and_demosaicked_1_s0_x_x_845_846.in1"], + ["eq_8460_847.in0","and_demosaicked_1_s0_x_x_845_846.out"], + ["eq_8460_847.in1","const_p0_0$2.out"], + ["mux_847_b_gr_stencil_1_b_r_stencil_1.sel","eq_8460_847.out"], + ["self.in1_b_r_stencil.0","mux_847_b_gr_stencil_1_b_r_stencil_1.in0"], + ["self.in0_b_gr_stencil.0","mux_847_b_gr_stencil_1_b_r_stencil_1.in1"], + ["self.out_demosaicked_1_stencil","mux_847_b_gr_stencil_1_b_r_stencil_1.out"] + ] + }, + "hcompute_demosaicked_1_stencil_3":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_r_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_r_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_859_860":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__859":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8600_861":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_861_r_b_stencil_1_r_gb_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_859_860.in0"], + ["const_p1__859.out","and_demosaicked_1_s0_x_x_859_860.in1"], + ["eq_8600_861.in0","and_demosaicked_1_s0_x_x_859_860.out"], + ["eq_8600_861.in1","const_p0_0$3.out"], + ["mux_861_r_b_stencil_1_r_gb_stencil_1.sel","eq_8600_861.out"], + ["self.in1_r_gb_stencil.0","mux_861_r_b_stencil_1_r_gb_stencil_1.in0"], + ["self.in0_r_b_stencil.0","mux_861_r_b_stencil_1_r_gb_stencil_1.in1"], + ["self.out_demosaicked_1_stencil","mux_861_r_b_stencil_1_r_gb_stencil_1.out"] + ] + }, + "hcompute_demosaicked_1_stencil_4":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_874_875":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__874":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8750_876":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_876_g_b_stencil_10_g_gb_stencil_7":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_874_875.in0"], + ["const_p1__874.out","and_demosaicked_1_s0_x_x_874_875.in1"], + ["eq_8750_876.in0","and_demosaicked_1_s0_x_x_874_875.out"], + ["eq_8750_876.in1","const_p0_0$4.out"], + ["mux_876_g_b_stencil_10_g_gb_stencil_7.sel","eq_8750_876.out"], + ["self.in1_g_gb_stencil.0","mux_876_g_b_stencil_10_g_gb_stencil_7.in0"], + ["self.in0_g_b_stencil.0","mux_876_g_b_stencil_10_g_gb_stencil_7.in1"], + ["self.out_demosaicked_1_stencil","mux_876_g_b_stencil_10_g_gb_stencil_7.out"] + ] + }, + "hcompute_demosaicked_1_stencil_5":{ + "type":["Record",[ + ["out_demosaicked_1_stencil",["Array",16,"Bit"]], + ["in0_b_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_b_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["demosaicked_1_s0_x_x",["Array",16,"BitIn"]] + ]], + "instances":{ + "and_demosaicked_1_s0_x_x_891_892":{ + "genref":"coreir.and", + "genargs":{"width":["Int",16]} + }, + "const_p0_0$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__891":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "eq_8920_893":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",16]} + }, + "mux_893_b_b_stencil_9_b_gb_stencil_1":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.demosaicked_1_s0_x_x","and_demosaicked_1_s0_x_x_891_892.in0"], + ["const_p1__891.out","and_demosaicked_1_s0_x_x_891_892.in1"], + ["eq_8920_893.in0","and_demosaicked_1_s0_x_x_891_892.out"], + ["eq_8920_893.in1","const_p0_0$5.out"], + ["mux_893_b_b_stencil_9_b_gb_stencil_1.sel","eq_8920_893.out"], + ["self.in1_b_gb_stencil.0","mux_893_b_b_stencil_9_b_gb_stencil_1.in0"], + ["self.in0_b_b_stencil.0","mux_893_b_b_stencil_9_b_gb_stencil_1.in1"], + ["self.out_demosaicked_1_stencil","mux_893_b_b_stencil_9_b_gb_stencil_1.out"] + ] + }, + "hcompute_denoised_1_stencil":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_2_349_350":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_3_348_349":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_348":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_1_350_351":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_350_351.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_2_349_350.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_348_349.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_348.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_348.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_350_351.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_3_348_349.out","umax_hw_input_global_wrapper_global_wrapper_stencil_2_349_350.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_1_350_351.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_2_349_350.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_4_hw_input_global_wrapper_global_wrapper_stencil_5_348.out","umax_hw_input_global_wrapper_global_wrapper_stencil_3_348_349.in1"] + ] + }, + "hcompute_denoised_1_stencil_1":{ + "type":["Record",[ + ["out_denoised_1_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "umax_hw_input_global_wrapper_global_wrapper_stencil_7_371_372":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_8_370_371":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_370":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + }, + "umin_hw_input_global_wrapper_global_wrapper_stencil_6_372_373":{ + "genref":"commonlib.umin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_370.in1","self.in0_hw_input_global_wrapper_global_wrapper_stencil.0"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_372_373.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.1"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_7_371_372.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.2"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_370_371.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.3"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_370.in0","self.in0_hw_input_global_wrapper_global_wrapper_stencil.4"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_372_373.out","self.out_denoised_1_stencil"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_8_370_371.out","umax_hw_input_global_wrapper_global_wrapper_stencil_7_371_372.in1"], + ["umin_hw_input_global_wrapper_global_wrapper_stencil_6_372_373.in1","umax_hw_input_global_wrapper_global_wrapper_stencil_7_371_372.out"], + ["umax_hw_input_global_wrapper_global_wrapper_stencil_9_hw_input_global_wrapper_global_wrapper_stencil_10_370.out","umax_hw_input_global_wrapper_global_wrapper_stencil_8_370_371.in1"] + ] + }, + "hcompute_g_b_stencil":{ + "type":["Record",[ + ["out_g_b_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_1_g_gb_stencil_2_441":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_1_g_gr_stencil_2_442":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_1_g_gb_stencil_2_444":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_1_g_gr_stencil_2_447":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__445":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__445$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_444_445_446":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_447_445_448":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_443_446_448":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_441_442_443":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_1_g_gb_stencil_2_441.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_1_g_gb_stencil_2_441.in1"], + ["ult_441_442_443.in0","absd_g_gb_stencil_1_g_gb_stencil_2_441.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_1_g_gr_stencil_2_442.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_1_g_gr_stencil_2_442.in1"], + ["ult_441_442_443.in1","absd_g_gr_stencil_1_g_gr_stencil_2_442.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_1_g_gb_stencil_2_444.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_1_g_gb_stencil_2_444.in1"], + ["lshr_444_445_446.in0","add_g_gb_stencil_1_g_gb_stencil_2_444.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_1_g_gr_stencil_2_447.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_1_g_gr_stencil_2_447.in1"], + ["lshr_447_445_448.in0","add_g_gr_stencil_1_g_gr_stencil_2_447.out"], + ["lshr_447_445_448.in1","const_p1__445$1.out"], + ["lshr_444_445_446.in1","const_p1__445.out"], + ["mux_443_446_448.in1","lshr_444_445_446.out"], + ["mux_443_446_448.in0","lshr_447_445_448.out"], + ["self.out_g_b_stencil","mux_443_446_448.out"], + ["ult_441_442_443.out","mux_443_446_448.sel"] + ] + }, + "hcompute_g_gb_stencil":{ + "type":["Record",[ + ["out_g_gb_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gb_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_gr_stencil":{ + "type":["Record",[ + ["out_g_gr_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_g_gr_stencil","self.in0_denoised_1_stencil.0"] + ] + }, + "hcompute_g_r_stencil":{ + "type":["Record",[ + ["out_g_r_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_g_gr_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_g_gb_stencil_4_g_gb_stencil_5_553":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_g_gr_stencil_4_g_gr_stencil_5_552":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_gb_stencil_4_g_gb_stencil_5_558":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_gr_stencil_4_g_gr_stencil_5_555":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__556":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__556$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_555_556_557":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_558_556_559":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_554_557_559":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "ult_552_553_554":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","absd_g_gb_stencil_4_g_gb_stencil_5_553.in0"], + ["self.in0_g_gb_stencil.1","absd_g_gb_stencil_4_g_gb_stencil_5_553.in1"], + ["ult_552_553_554.in1","absd_g_gb_stencil_4_g_gb_stencil_5_553.out"], + ["self.in1_g_gr_stencil.0","absd_g_gr_stencil_4_g_gr_stencil_5_552.in0"], + ["self.in1_g_gr_stencil.1","absd_g_gr_stencil_4_g_gr_stencil_5_552.in1"], + ["ult_552_553_554.in0","absd_g_gr_stencil_4_g_gr_stencil_5_552.out"], + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_4_g_gb_stencil_5_558.in0"], + ["self.in0_g_gb_stencil.1","add_g_gb_stencil_4_g_gb_stencil_5_558.in1"], + ["lshr_558_556_559.in0","add_g_gb_stencil_4_g_gb_stencil_5_558.out"], + ["self.in1_g_gr_stencil.0","add_g_gr_stencil_4_g_gr_stencil_5_555.in0"], + ["self.in1_g_gr_stencil.1","add_g_gr_stencil_4_g_gr_stencil_5_555.in1"], + ["lshr_555_556_557.in0","add_g_gr_stencil_4_g_gr_stencil_5_555.out"], + ["lshr_558_556_559.in1","const_p1__556$1.out"], + ["lshr_555_556_557.in1","const_p1__556.out"], + ["mux_554_557_559.in1","lshr_555_556_557.out"], + ["mux_554_557_559.in0","lshr_558_556_559.out"], + ["self.out_g_r_stencil","mux_554_557_559.out"], + ["ult_552_553_554.out","mux_554_557_559.sel"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_4":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil_5":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_curved_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_glb_stencil","self.in0_curved_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_4":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_5":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_r_b_stencil":{ + "type":["Record",[ + ["out_r_b_stencil",["Array",16,"Bit"]], + ["in0_g_b_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",4,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "absd_r_r_stencil_1_r_r_stencil_2_700":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "absd_r_r_stencil_3_r_r_stencil_4_701":{ + "genref":"commonlib.absd", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_705_706":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_b_stencil_9_711_712":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_2_g_r_stencil_3_707":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_4_g_r_stencil_5_713":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_1_r_r_stencil_2_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_3_r_r_stencil_4_710":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__704":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__704$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__704$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__704$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_703_704_705":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_707_704_708":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_710_704_711":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_713_704_714":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mux_702_709_715":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sub_706_708_709":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_712_714_715":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "ult_700_701_702":{ + "genref":"coreir.ult", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_r_r_stencil.0","absd_r_r_stencil_1_r_r_stencil_2_700.in0"], + ["self.in2_r_r_stencil.1","absd_r_r_stencil_1_r_r_stencil_2_700.in1"], + ["ult_700_701_702.in0","absd_r_r_stencil_1_r_r_stencil_2_700.out"], + ["self.in2_r_r_stencil.2","absd_r_r_stencil_3_r_r_stencil_4_701.in0"], + ["self.in2_r_r_stencil.3","absd_r_r_stencil_3_r_r_stencil_4_701.in1"], + ["ult_700_701_702.in1","absd_r_r_stencil_3_r_r_stencil_4_701.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_705_706.in0"], + ["lshr_703_704_705.out","add_g_b_stencil_9_705_706.in1"], + ["sub_706_708_709.in0","add_g_b_stencil_9_705_706.out"], + ["self.in0_g_b_stencil.0","add_g_b_stencil_9_711_712.in0"], + ["lshr_710_704_711.out","add_g_b_stencil_9_711_712.in1"], + ["sub_712_714_715.in0","add_g_b_stencil_9_711_712.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_2_g_r_stencil_3_707.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_2_g_r_stencil_3_707.in1"], + ["lshr_707_704_708.in0","add_g_r_stencil_2_g_r_stencil_3_707.out"], + ["self.in1_g_r_stencil.2","add_g_r_stencil_4_g_r_stencil_5_713.in0"], + ["self.in1_g_r_stencil.3","add_g_r_stencil_4_g_r_stencil_5_713.in1"], + ["lshr_713_704_714.in0","add_g_r_stencil_4_g_r_stencil_5_713.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_1_r_r_stencil_2_703.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_1_r_r_stencil_2_703.in1"], + ["lshr_703_704_705.in0","add_r_r_stencil_1_r_r_stencil_2_703.out"], + ["self.in2_r_r_stencil.2","add_r_r_stencil_3_r_r_stencil_4_710.in0"], + ["self.in2_r_r_stencil.3","add_r_r_stencil_3_r_r_stencil_4_710.in1"], + ["lshr_710_704_711.in0","add_r_r_stencil_3_r_r_stencil_4_710.out"], + ["lshr_707_704_708.in1","const_p1__704$1.out"], + ["lshr_710_704_711.in1","const_p1__704$2.out"], + ["lshr_713_704_714.in1","const_p1__704$3.out"], + ["lshr_703_704_705.in1","const_p1__704.out"], + ["sub_706_708_709.in1","lshr_707_704_708.out"], + ["sub_712_714_715.in1","lshr_713_704_714.out"], + ["sub_712_714_715.out","mux_702_709_715.in0"], + ["sub_706_708_709.out","mux_702_709_715.in1"], + ["self.out_r_b_stencil","mux_702_709_715.out"], + ["ult_700_701_702.out","mux_702_709_715.sel"] + ] + }, + "hcompute_r_gb_stencil":{ + "type":["Record",[ + ["out_r_gb_stencil",["Array",16,"Bit"]], + ["in0_g_gb_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gb_stencil_6_763_764":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_6_g_r_stencil_7_765":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_5_r_r_stencil_6_761":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__762":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__762$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_761_762_763":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_765_762_766":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_764_766_767":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gb_stencil.0","add_g_gb_stencil_6_763_764.in0"], + ["lshr_761_762_763.out","add_g_gb_stencil_6_763_764.in1"], + ["sub_764_766_767.in0","add_g_gb_stencil_6_763_764.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_6_g_r_stencil_7_765.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_6_g_r_stencil_7_765.in1"], + ["lshr_765_762_766.in0","add_g_r_stencil_6_g_r_stencil_7_765.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_5_r_r_stencil_6_761.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_5_r_r_stencil_6_761.in1"], + ["lshr_761_762_763.in0","add_r_r_stencil_5_r_r_stencil_6_761.out"], + ["lshr_765_762_766.in1","const_p1__762$1.out"], + ["lshr_761_762_763.in1","const_p1__762.out"], + ["sub_764_766_767.in1","lshr_765_762_766.out"], + ["sub_764_766_767.out","self.out_r_gb_stencil"] + ] + }, + "hcompute_r_gr_stencil":{ + "type":["Record",[ + ["out_r_gr_stencil",["Array",16,"Bit"]], + ["in0_g_gr_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_g_r_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_r_r_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_g_gr_stencil_6_792_793":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_g_r_stencil_8_g_r_stencil_9_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_r_r_stencil_7_r_r_stencil_8_790":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p1__791":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p1__791$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "lshr_790_791_792":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "lshr_794_791_795":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "sub_793_795_796":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_g_gr_stencil.0","add_g_gr_stencil_6_792_793.in0"], + ["lshr_790_791_792.out","add_g_gr_stencil_6_792_793.in1"], + ["sub_793_795_796.in0","add_g_gr_stencil_6_792_793.out"], + ["self.in1_g_r_stencil.0","add_g_r_stencil_8_g_r_stencil_9_794.in0"], + ["self.in1_g_r_stencil.1","add_g_r_stencil_8_g_r_stencil_9_794.in1"], + ["lshr_794_791_795.in0","add_g_r_stencil_8_g_r_stencil_9_794.out"], + ["self.in2_r_r_stencil.0","add_r_r_stencil_7_r_r_stencil_8_790.in0"], + ["self.in2_r_r_stencil.1","add_r_r_stencil_7_r_r_stencil_8_790.in1"], + ["lshr_790_791_792.in0","add_r_r_stencil_7_r_r_stencil_8_790.out"], + ["lshr_794_791_795.in1","const_p1__791$1.out"], + ["lshr_790_791_792.in1","const_p1__791.out"], + ["sub_793_795_796.in1","lshr_794_791_795.out"], + ["sub_793_795_796.out","self.out_r_gr_stencil"] + ] + }, + "hcompute_r_r_stencil":{ + "type":["Record",[ + ["out_r_r_stencil",["Array",16,"Bit"]], + ["in0_denoised_1_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_r_r_stencil","self.in0_denoised_1_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/fp_arith_compute.json b/coreir_compute/fp_arith_compute.json new file mode 100644 index 000000000..c17ed53bb --- /dev/null +++ b/coreir_compute/fp_arith_compute.json @@ -0,0 +1,49 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_mult_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_mult_stencil.0"] + ] + }, + "hcompute_mult_stencil":{ + "type":["Record",[ + ["out_mult_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_260_261_262":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst13__261":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h4154"]}, + "metadata":{"float_value":"Equivalent float = 13.250000"} + } + }, + "connections":[ + ["self.in0_hw_input_global_wrapper_stencil.0","dwfp_mul_260_261_262.a"], + ["fconst13__261.out","dwfp_mul_260_261_262.b"], + ["self.out_mult_stencil","dwfp_mul_260_261_262.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/fp_pointwise_compute.json b/coreir_compute/fp_pointwise_compute.json new file mode 100644 index 000000000..c4c9c8cd0 --- /dev/null +++ b/coreir_compute/fp_pointwise_compute.json @@ -0,0 +1,49 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_product_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_product_stencil.0"] + ] + }, + "hcompute_product_stencil":{ + "type":["Record",[ + ["out_product_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_hw_input_global_wrapper_stencil_1_274_275":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst3__274":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h4049"]}, + "metadata":{"float_value":"Equivalent float = 3.140625"} + } + }, + "connections":[ + ["self.in0_hw_input_global_wrapper_stencil.0","dwfp_mul_hw_input_global_wrapper_stencil_1_274_275.a"], + ["fconst3__274.out","dwfp_mul_hw_input_global_wrapper_stencil_1_274_275.b"], + ["self.out_product_stencil","dwfp_mul_hw_input_global_wrapper_stencil_1_274_275.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/harris_color_unroll4_compute.json b/coreir_compute/harris_color_unroll4_compute.json new file mode 100644 index 000000000..90daa97ff --- /dev/null +++ b/coreir_compute/harris_color_unroll4_compute.json @@ -0,0 +1,7352 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_cim_stencil":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2169_2170_2175":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_2176_2177_2178":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_5_2168_2169":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_5_2168_2172":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_5_2168_2170":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__2177":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__2168":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2168$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2168$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_2169_2170_2171":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2172_2172_2173":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2175_2175_2176":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_2171_2173_2174":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_2174_2178_2179":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_5_2168_2169.out","add_2169_2170_2175.in0"], + ["ashr_lgyy_stencil_5_2168_2170.out","add_2169_2170_2175.in1"], + ["mul_2175_2175_2176.in0","add_2169_2170_2175.out"], + ["mul_2175_2175_2176.in1","add_2169_2170_2175.out"], + ["mul_2175_2175_2176.out","ashr_2176_2177_2178.in0"], + ["const_p4__2177.out","ashr_2176_2177_2178.in1"], + ["sub_2174_2178_2179.in1","ashr_2176_2177_2178.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_5_2168_2169.in0"], + ["const_p6__2168.out","ashr_lgxx_stencil_5_2168_2169.in1"], + ["mul_2169_2170_2171.in0","ashr_lgxx_stencil_5_2168_2169.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_5_2168_2172.in0"], + ["const_p6__2168$2.out","ashr_lgxy_stencil_5_2168_2172.in1"], + ["mul_2172_2172_2173.in0","ashr_lgxy_stencil_5_2168_2172.out"], + ["mul_2172_2172_2173.in1","ashr_lgxy_stencil_5_2168_2172.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_5_2168_2170.in0"], + ["const_p6__2168$1.out","ashr_lgyy_stencil_5_2168_2170.in1"], + ["mul_2169_2170_2171.in1","ashr_lgyy_stencil_5_2168_2170.out"], + ["sub_2171_2173_2174.in0","mul_2169_2170_2171.out"], + ["sub_2171_2173_2174.in1","mul_2172_2172_2173.out"], + ["sub_2174_2178_2179.out","self.out_cim_stencil"], + ["sub_2174_2178_2179.in0","sub_2171_2173_2174.out"] + ] + }, + "hcompute_cim_stencil_1":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2211_2212_2217":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_2218_2219_2220":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_6_2210_2211":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_6_2210_2214":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_6_2210_2212":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__2219":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__2210":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2210$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2210$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_2211_2212_2213":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2214_2214_2215":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2217_2217_2218":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_2213_2215_2216":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_2216_2220_2221":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_6_2210_2211.out","add_2211_2212_2217.in0"], + ["ashr_lgyy_stencil_6_2210_2212.out","add_2211_2212_2217.in1"], + ["mul_2217_2217_2218.in0","add_2211_2212_2217.out"], + ["mul_2217_2217_2218.in1","add_2211_2212_2217.out"], + ["mul_2217_2217_2218.out","ashr_2218_2219_2220.in0"], + ["const_p4__2219.out","ashr_2218_2219_2220.in1"], + ["sub_2216_2220_2221.in1","ashr_2218_2219_2220.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_6_2210_2211.in0"], + ["const_p6__2210.out","ashr_lgxx_stencil_6_2210_2211.in1"], + ["mul_2211_2212_2213.in0","ashr_lgxx_stencil_6_2210_2211.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_6_2210_2214.in0"], + ["const_p6__2210$2.out","ashr_lgxy_stencil_6_2210_2214.in1"], + ["mul_2214_2214_2215.in0","ashr_lgxy_stencil_6_2210_2214.out"], + ["mul_2214_2214_2215.in1","ashr_lgxy_stencil_6_2210_2214.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_6_2210_2212.in0"], + ["const_p6__2210$1.out","ashr_lgyy_stencil_6_2210_2212.in1"], + ["mul_2211_2212_2213.in1","ashr_lgyy_stencil_6_2210_2212.out"], + ["sub_2213_2215_2216.in0","mul_2211_2212_2213.out"], + ["sub_2213_2215_2216.in1","mul_2214_2214_2215.out"], + ["sub_2216_2220_2221.out","self.out_cim_stencil"], + ["sub_2216_2220_2221.in0","sub_2213_2215_2216.out"] + ] + }, + "hcompute_cim_stencil_2":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2254_2255_2260":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_2261_2262_2263":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_7_2253_2254":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_7_2253_2257":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_7_2253_2255":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__2262":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__2253":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2253$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2253$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_2254_2255_2256":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2257_2257_2258":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2260_2260_2261":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_2256_2258_2259":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_2259_2263_2264":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_7_2253_2254.out","add_2254_2255_2260.in0"], + ["ashr_lgyy_stencil_7_2253_2255.out","add_2254_2255_2260.in1"], + ["mul_2260_2260_2261.in0","add_2254_2255_2260.out"], + ["mul_2260_2260_2261.in1","add_2254_2255_2260.out"], + ["mul_2260_2260_2261.out","ashr_2261_2262_2263.in0"], + ["const_p4__2262.out","ashr_2261_2262_2263.in1"], + ["sub_2259_2263_2264.in1","ashr_2261_2262_2263.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_7_2253_2254.in0"], + ["const_p6__2253.out","ashr_lgxx_stencil_7_2253_2254.in1"], + ["mul_2254_2255_2256.in0","ashr_lgxx_stencil_7_2253_2254.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_7_2253_2257.in0"], + ["const_p6__2253$2.out","ashr_lgxy_stencil_7_2253_2257.in1"], + ["mul_2257_2257_2258.in0","ashr_lgxy_stencil_7_2253_2257.out"], + ["mul_2257_2257_2258.in1","ashr_lgxy_stencil_7_2253_2257.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_7_2253_2255.in0"], + ["const_p6__2253$1.out","ashr_lgyy_stencil_7_2253_2255.in1"], + ["mul_2254_2255_2256.in1","ashr_lgyy_stencil_7_2253_2255.out"], + ["sub_2256_2258_2259.in0","mul_2254_2255_2256.out"], + ["sub_2256_2258_2259.in1","mul_2257_2257_2258.out"], + ["sub_2259_2263_2264.out","self.out_cim_stencil"], + ["sub_2259_2263_2264.in0","sub_2256_2258_2259.out"] + ] + }, + "hcompute_cim_stencil_3":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2297_2298_2303":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_2304_2305_2306":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_8_2296_2297":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_8_2296_2300":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_8_2296_2298":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__2305":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__2296":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2296$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__2296$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_2297_2298_2299":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2300_2300_2301":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2303_2303_2304":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_2299_2301_2302":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_2302_2306_2307":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_8_2296_2297.out","add_2297_2298_2303.in0"], + ["ashr_lgyy_stencil_8_2296_2298.out","add_2297_2298_2303.in1"], + ["mul_2303_2303_2304.in0","add_2297_2298_2303.out"], + ["mul_2303_2303_2304.in1","add_2297_2298_2303.out"], + ["mul_2303_2303_2304.out","ashr_2304_2305_2306.in0"], + ["const_p4__2305.out","ashr_2304_2305_2306.in1"], + ["sub_2302_2306_2307.in1","ashr_2304_2305_2306.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_8_2296_2297.in0"], + ["const_p6__2296.out","ashr_lgxx_stencil_8_2296_2297.in1"], + ["mul_2297_2298_2299.in0","ashr_lgxx_stencil_8_2296_2297.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_8_2296_2300.in0"], + ["const_p6__2296$2.out","ashr_lgxy_stencil_8_2296_2300.in1"], + ["mul_2300_2300_2301.in0","ashr_lgxy_stencil_8_2296_2300.out"], + ["mul_2300_2300_2301.in1","ashr_lgxy_stencil_8_2296_2300.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_8_2296_2298.in0"], + ["const_p6__2296$1.out","ashr_lgyy_stencil_8_2296_2298.in1"], + ["mul_2297_2298_2299.in1","ashr_lgyy_stencil_8_2296_2298.out"], + ["sub_2299_2301_2302.in0","mul_2297_2298_2299.out"], + ["sub_2299_2301_2302.in1","mul_2300_2300_2301.out"], + ["sub_2302_2306_2307.out","self.out_cim_stencil"], + ["sub_2302_2306_2307.in0","sub_2299_2301_2302.out"] + ] + }, + "hcompute_cim_stencil_4":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_4398_4399_4404":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_4405_4406_4407":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_13_4397_4398":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_13_4397_4401":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_13_4397_4399":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__4406":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__4397":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4397$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4397$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4398_4399_4400":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4401_4401_4402":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4404_4404_4405":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_4400_4402_4403":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_4403_4407_4408":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_13_4397_4398.out","add_4398_4399_4404.in0"], + ["ashr_lgyy_stencil_13_4397_4399.out","add_4398_4399_4404.in1"], + ["mul_4404_4404_4405.in0","add_4398_4399_4404.out"], + ["mul_4404_4404_4405.in1","add_4398_4399_4404.out"], + ["mul_4404_4404_4405.out","ashr_4405_4406_4407.in0"], + ["const_p4__4406.out","ashr_4405_4406_4407.in1"], + ["sub_4403_4407_4408.in1","ashr_4405_4406_4407.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_13_4397_4398.in0"], + ["const_p6__4397.out","ashr_lgxx_stencil_13_4397_4398.in1"], + ["mul_4398_4399_4400.in0","ashr_lgxx_stencil_13_4397_4398.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_13_4397_4401.in0"], + ["const_p6__4397$2.out","ashr_lgxy_stencil_13_4397_4401.in1"], + ["mul_4401_4401_4402.in0","ashr_lgxy_stencil_13_4397_4401.out"], + ["mul_4401_4401_4402.in1","ashr_lgxy_stencil_13_4397_4401.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_13_4397_4399.in0"], + ["const_p6__4397$1.out","ashr_lgyy_stencil_13_4397_4399.in1"], + ["mul_4398_4399_4400.in1","ashr_lgyy_stencil_13_4397_4399.out"], + ["sub_4400_4402_4403.in0","mul_4398_4399_4400.out"], + ["sub_4400_4402_4403.in1","mul_4401_4401_4402.out"], + ["sub_4403_4407_4408.out","self.out_cim_stencil"], + ["sub_4403_4407_4408.in0","sub_4400_4402_4403.out"] + ] + }, + "hcompute_cim_stencil_5":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_4440_4441_4446":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_4447_4448_4449":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_14_4439_4440":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_14_4439_4443":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_14_4439_4441":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__4448":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__4439":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4439$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4439$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4440_4441_4442":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4443_4443_4444":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4446_4446_4447":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_4442_4444_4445":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_4445_4449_4450":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_14_4439_4440.out","add_4440_4441_4446.in0"], + ["ashr_lgyy_stencil_14_4439_4441.out","add_4440_4441_4446.in1"], + ["mul_4446_4446_4447.in0","add_4440_4441_4446.out"], + ["mul_4446_4446_4447.in1","add_4440_4441_4446.out"], + ["mul_4446_4446_4447.out","ashr_4447_4448_4449.in0"], + ["const_p4__4448.out","ashr_4447_4448_4449.in1"], + ["sub_4445_4449_4450.in1","ashr_4447_4448_4449.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_14_4439_4440.in0"], + ["const_p6__4439.out","ashr_lgxx_stencil_14_4439_4440.in1"], + ["mul_4440_4441_4442.in0","ashr_lgxx_stencil_14_4439_4440.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_14_4439_4443.in0"], + ["const_p6__4439$2.out","ashr_lgxy_stencil_14_4439_4443.in1"], + ["mul_4443_4443_4444.in0","ashr_lgxy_stencil_14_4439_4443.out"], + ["mul_4443_4443_4444.in1","ashr_lgxy_stencil_14_4439_4443.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_14_4439_4441.in0"], + ["const_p6__4439$1.out","ashr_lgyy_stencil_14_4439_4441.in1"], + ["mul_4440_4441_4442.in1","ashr_lgyy_stencil_14_4439_4441.out"], + ["sub_4442_4444_4445.in0","mul_4440_4441_4442.out"], + ["sub_4442_4444_4445.in1","mul_4443_4443_4444.out"], + ["sub_4445_4449_4450.out","self.out_cim_stencil"], + ["sub_4445_4449_4450.in0","sub_4442_4444_4445.out"] + ] + }, + "hcompute_cim_stencil_6":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_4483_4484_4489":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_4490_4491_4492":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_15_4482_4483":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_15_4482_4486":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_15_4482_4484":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__4491":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__4482":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4482$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4482$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4483_4484_4485":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4486_4486_4487":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4489_4489_4490":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_4485_4487_4488":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_4488_4492_4493":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_15_4482_4483.out","add_4483_4484_4489.in0"], + ["ashr_lgyy_stencil_15_4482_4484.out","add_4483_4484_4489.in1"], + ["mul_4489_4489_4490.in0","add_4483_4484_4489.out"], + ["mul_4489_4489_4490.in1","add_4483_4484_4489.out"], + ["mul_4489_4489_4490.out","ashr_4490_4491_4492.in0"], + ["const_p4__4491.out","ashr_4490_4491_4492.in1"], + ["sub_4488_4492_4493.in1","ashr_4490_4491_4492.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_15_4482_4483.in0"], + ["const_p6__4482.out","ashr_lgxx_stencil_15_4482_4483.in1"], + ["mul_4483_4484_4485.in0","ashr_lgxx_stencil_15_4482_4483.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_15_4482_4486.in0"], + ["const_p6__4482$2.out","ashr_lgxy_stencil_15_4482_4486.in1"], + ["mul_4486_4486_4487.in0","ashr_lgxy_stencil_15_4482_4486.out"], + ["mul_4486_4486_4487.in1","ashr_lgxy_stencil_15_4482_4486.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_15_4482_4484.in0"], + ["const_p6__4482$1.out","ashr_lgyy_stencil_15_4482_4484.in1"], + ["mul_4483_4484_4485.in1","ashr_lgyy_stencil_15_4482_4484.out"], + ["sub_4485_4487_4488.in0","mul_4483_4484_4485.out"], + ["sub_4485_4487_4488.in1","mul_4486_4486_4487.out"], + ["sub_4488_4492_4493.out","self.out_cim_stencil"], + ["sub_4488_4492_4493.in0","sub_4485_4487_4488.out"] + ] + }, + "hcompute_cim_stencil_7":{ + "type":["Record",[ + ["out_cim_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_4526_4527_4532":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_4533_4534_4535":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxx_stencil_16_4525_4526":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgxy_stencil_16_4525_4529":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "ashr_lgyy_stencil_16_4525_4527":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__4534":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "const_p6__4525":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4525$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__4525$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4526_4527_4528":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4529_4529_4530":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_4532_4532_4533":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_4528_4530_4531":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_4531_4535_4536":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["ashr_lgxx_stencil_16_4525_4526.out","add_4526_4527_4532.in0"], + ["ashr_lgyy_stencil_16_4525_4527.out","add_4526_4527_4532.in1"], + ["mul_4532_4532_4533.in0","add_4526_4527_4532.out"], + ["mul_4532_4532_4533.in1","add_4526_4527_4532.out"], + ["mul_4532_4532_4533.out","ashr_4533_4534_4535.in0"], + ["const_p4__4534.out","ashr_4533_4534_4535.in1"], + ["sub_4531_4535_4536.in1","ashr_4533_4534_4535.out"], + ["self.in0_lgxx_stencil.0","ashr_lgxx_stencil_16_4525_4526.in0"], + ["const_p6__4525.out","ashr_lgxx_stencil_16_4525_4526.in1"], + ["mul_4526_4527_4528.in0","ashr_lgxx_stencil_16_4525_4526.out"], + ["self.in1_lgxy_stencil.0","ashr_lgxy_stencil_16_4525_4529.in0"], + ["const_p6__4525$2.out","ashr_lgxy_stencil_16_4525_4529.in1"], + ["mul_4529_4529_4530.in0","ashr_lgxy_stencil_16_4525_4529.out"], + ["mul_4529_4529_4530.in1","ashr_lgxy_stencil_16_4525_4529.out"], + ["self.in2_lgyy_stencil.0","ashr_lgyy_stencil_16_4525_4527.in0"], + ["const_p6__4525$1.out","ashr_lgyy_stencil_16_4525_4527.in1"], + ["mul_4526_4527_4528.in1","ashr_lgyy_stencil_16_4525_4527.out"], + ["sub_4528_4530_4531.in0","mul_4526_4527_4528.out"], + ["sub_4528_4530_4531.in1","mul_4529_4529_4530.out"], + ["sub_4531_4535_4536.out","self.out_cim_stencil"], + ["sub_4531_4535_4536.in0","sub_4528_4530_4531.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__665":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__665.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_1":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__671":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__671.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_10":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__2907":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__2907.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_11":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__2914":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__2914.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_12":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2941_2942_2943":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2948_2949_2950":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_13_2938_2939":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__2937":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__2937$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_2936_2937_2938":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2944_2937_2945":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_2939_2940_2941":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_2943_2945_2946":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_2946_2947_2948":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_2939_2940_2941.out","add_2941_2942_2943.in0"], + ["self.in1_gray_stencil.2","add_2941_2942_2943.in1"], + ["sub_2943_2945_2946.in0","add_2941_2942_2943.out"], + ["sub_2946_2947_2948.out","add_2948_2949_2950.in0"], + ["self.in1_gray_stencil.5","add_2948_2949_2950.in1"], + ["self.out_grad_x_unclamp_stencil","add_2948_2949_2950.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_13_2938_2939.in0"], + ["mul_2936_2937_2938.out","add_grad_x_unclamp_stencil_13_2938_2939.in1"], + ["sub_2939_2940_2941.in0","add_grad_x_unclamp_stencil_13_2938_2939.out"], + ["mul_2944_2937_2945.in1","const_p2__2937$1.out"], + ["mul_2936_2937_2938.in1","const_p2__2937.out"], + ["self.in1_gray_stencil.0","mul_2936_2937_2938.in0"], + ["self.in1_gray_stencil.3","mul_2944_2937_2945.in0"], + ["sub_2943_2945_2946.in1","mul_2944_2937_2945.out"], + ["sub_2939_2940_2941.in1","self.in1_gray_stencil.1"], + ["sub_2946_2947_2948.in1","self.in1_gray_stencil.4"], + ["sub_2946_2947_2948.in0","sub_2943_2945_2946.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_13":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2999_3000_3001":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_3006_3007_3008":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_14_2996_2997":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__2995":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__2995$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_2994_2995_2996":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_3002_2995_3003":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_2997_2998_2999":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3001_3003_3004":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3004_3005_3006":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_2997_2998_2999.out","add_2999_3000_3001.in0"], + ["self.in1_gray_stencil.2","add_2999_3000_3001.in1"], + ["sub_3001_3003_3004.in0","add_2999_3000_3001.out"], + ["sub_3004_3005_3006.out","add_3006_3007_3008.in0"], + ["self.in1_gray_stencil.5","add_3006_3007_3008.in1"], + ["self.out_grad_x_unclamp_stencil","add_3006_3007_3008.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_14_2996_2997.in0"], + ["mul_2994_2995_2996.out","add_grad_x_unclamp_stencil_14_2996_2997.in1"], + ["sub_2997_2998_2999.in0","add_grad_x_unclamp_stencil_14_2996_2997.out"], + ["mul_3002_2995_3003.in1","const_p2__2995$1.out"], + ["mul_2994_2995_2996.in1","const_p2__2995.out"], + ["self.in1_gray_stencil.0","mul_2994_2995_2996.in0"], + ["self.in1_gray_stencil.3","mul_3002_2995_3003.in0"], + ["sub_3001_3003_3004.in1","mul_3002_2995_3003.out"], + ["sub_2997_2998_2999.in1","self.in1_gray_stencil.1"], + ["sub_3004_3005_3006.in1","self.in1_gray_stencil.4"], + ["sub_3004_3005_3006.in0","sub_3001_3003_3004.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_14":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_3058_3059_3060":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_3065_3066_3067":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_15_3055_3056":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__3054":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__3054$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_3053_3054_3055":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_3061_3054_3062":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_3056_3057_3058":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3060_3062_3063":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3063_3064_3065":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_3056_3057_3058.out","add_3058_3059_3060.in0"], + ["self.in1_gray_stencil.2","add_3058_3059_3060.in1"], + ["sub_3060_3062_3063.in0","add_3058_3059_3060.out"], + ["sub_3063_3064_3065.out","add_3065_3066_3067.in0"], + ["self.in1_gray_stencil.5","add_3065_3066_3067.in1"], + ["self.out_grad_x_unclamp_stencil","add_3065_3066_3067.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_15_3055_3056.in0"], + ["mul_3053_3054_3055.out","add_grad_x_unclamp_stencil_15_3055_3056.in1"], + ["sub_3056_3057_3058.in0","add_grad_x_unclamp_stencil_15_3055_3056.out"], + ["mul_3061_3054_3062.in1","const_p2__3054$1.out"], + ["mul_3053_3054_3055.in1","const_p2__3054.out"], + ["self.in1_gray_stencil.0","mul_3053_3054_3055.in0"], + ["self.in1_gray_stencil.3","mul_3061_3054_3062.in0"], + ["sub_3060_3062_3063.in1","mul_3061_3054_3062.out"], + ["sub_3056_3057_3058.in1","self.in1_gray_stencil.1"], + ["sub_3063_3064_3065.in1","self.in1_gray_stencil.4"], + ["sub_3063_3064_3065.in0","sub_3060_3062_3063.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_15":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_3117_3118_3119":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_3124_3125_3126":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_16_3114_3115":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__3113":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__3113$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_3112_3113_3114":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_3120_3113_3121":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_3115_3116_3117":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3119_3121_3122":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3122_3123_3124":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_3115_3116_3117.out","add_3117_3118_3119.in0"], + ["self.in1_gray_stencil.2","add_3117_3118_3119.in1"], + ["sub_3119_3121_3122.in0","add_3117_3118_3119.out"], + ["sub_3122_3123_3124.out","add_3124_3125_3126.in0"], + ["self.in1_gray_stencil.5","add_3124_3125_3126.in1"], + ["self.out_grad_x_unclamp_stencil","add_3124_3125_3126.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_16_3114_3115.in0"], + ["mul_3112_3113_3114.out","add_grad_x_unclamp_stencil_16_3114_3115.in1"], + ["sub_3115_3116_3117.in0","add_grad_x_unclamp_stencil_16_3114_3115.out"], + ["mul_3120_3113_3121.in1","const_p2__3113$1.out"], + ["mul_3112_3113_3114.in1","const_p2__3113.out"], + ["self.in1_gray_stencil.0","mul_3112_3113_3114.in0"], + ["self.in1_gray_stencil.3","mul_3120_3113_3121.in0"], + ["sub_3119_3121_3122.in1","mul_3120_3113_3121.out"], + ["sub_3115_3116_3117.in1","self.in1_gray_stencil.1"], + ["sub_3122_3123_3124.in1","self.in1_gray_stencil.4"], + ["sub_3122_3123_3124.in0","sub_3119_3121_3122.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_2":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__678":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__678.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_3":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__685":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__685.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_4":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_712_713_714":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_719_720_721":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_1_709_710":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__708":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__708$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_707_708_709":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_715_708_716":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_710_711_712":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_714_716_717":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_717_718_719":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_710_711_712.out","add_712_713_714.in0"], + ["self.in1_gray_stencil.2","add_712_713_714.in1"], + ["sub_714_716_717.in0","add_712_713_714.out"], + ["sub_717_718_719.out","add_719_720_721.in0"], + ["self.in1_gray_stencil.5","add_719_720_721.in1"], + ["self.out_grad_x_unclamp_stencil","add_719_720_721.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_1_709_710.in0"], + ["mul_707_708_709.out","add_grad_x_unclamp_stencil_1_709_710.in1"], + ["sub_710_711_712.in0","add_grad_x_unclamp_stencil_1_709_710.out"], + ["mul_715_708_716.in1","const_p2__708$1.out"], + ["mul_707_708_709.in1","const_p2__708.out"], + ["self.in1_gray_stencil.0","mul_707_708_709.in0"], + ["self.in1_gray_stencil.3","mul_715_708_716.in0"], + ["sub_714_716_717.in1","mul_715_708_716.out"], + ["sub_710_711_712.in1","self.in1_gray_stencil.1"], + ["sub_717_718_719.in1","self.in1_gray_stencil.4"], + ["sub_717_718_719.in0","sub_714_716_717.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_5":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_770_771_772":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_777_778_779":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_2_767_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__766":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__766$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_765_766_767":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_773_766_774":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_768_769_770":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_772_774_775":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_775_776_777":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_768_769_770.out","add_770_771_772.in0"], + ["self.in1_gray_stencil.5","add_770_771_772.in1"], + ["sub_772_774_775.in0","add_770_771_772.out"], + ["sub_775_776_777.out","add_777_778_779.in0"], + ["self.in1_gray_stencil.2","add_777_778_779.in1"], + ["self.out_grad_x_unclamp_stencil","add_777_778_779.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_2_767_768.in0"], + ["mul_765_766_767.out","add_grad_x_unclamp_stencil_2_767_768.in1"], + ["sub_768_769_770.in0","add_grad_x_unclamp_stencil_2_767_768.out"], + ["mul_773_766_774.in1","const_p2__766$1.out"], + ["mul_765_766_767.in1","const_p2__766.out"], + ["self.in1_gray_stencil.3","mul_765_766_767.in0"], + ["self.in1_gray_stencil.0","mul_773_766_774.in0"], + ["sub_772_774_775.in1","mul_773_766_774.out"], + ["sub_775_776_777.in1","self.in1_gray_stencil.1"], + ["sub_768_769_770.in1","self.in1_gray_stencil.4"], + ["sub_775_776_777.in0","sub_772_774_775.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_6":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_829_830_831":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_836_837_838":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_3_826_827":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__825":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__825$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_824_825_826":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_832_825_833":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_827_828_829":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_831_833_834":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_834_835_836":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_827_828_829.out","add_829_830_831.in0"], + ["self.in1_gray_stencil.2","add_829_830_831.in1"], + ["sub_831_833_834.in0","add_829_830_831.out"], + ["sub_834_835_836.out","add_836_837_838.in0"], + ["self.in1_gray_stencil.5","add_836_837_838.in1"], + ["self.out_grad_x_unclamp_stencil","add_836_837_838.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_3_826_827.in0"], + ["mul_824_825_826.out","add_grad_x_unclamp_stencil_3_826_827.in1"], + ["sub_827_828_829.in0","add_grad_x_unclamp_stencil_3_826_827.out"], + ["mul_832_825_833.in1","const_p2__825$1.out"], + ["mul_824_825_826.in1","const_p2__825.out"], + ["self.in1_gray_stencil.0","mul_824_825_826.in0"], + ["self.in1_gray_stencil.3","mul_832_825_833.in0"], + ["sub_831_833_834.in1","mul_832_825_833.out"], + ["sub_827_828_829.in1","self.in1_gray_stencil.1"], + ["sub_834_835_836.in1","self.in1_gray_stencil.4"], + ["sub_834_835_836.in0","sub_831_833_834.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_7":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_888_889_890":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_895_896_897":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_x_unclamp_stencil_4_885_886":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__884":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__884$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_883_884_885":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_891_884_892":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_886_887_888":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_890_892_893":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_893_894_895":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_886_887_888.out","add_888_889_890.in0"], + ["self.in1_gray_stencil.2","add_888_889_890.in1"], + ["sub_890_892_893.in0","add_888_889_890.out"], + ["sub_893_894_895.out","add_895_896_897.in0"], + ["self.in1_gray_stencil.5","add_895_896_897.in1"], + ["self.out_grad_x_unclamp_stencil","add_895_896_897.out"], + ["self.in0_grad_x_unclamp_stencil.0","add_grad_x_unclamp_stencil_4_885_886.in0"], + ["mul_883_884_885.out","add_grad_x_unclamp_stencil_4_885_886.in1"], + ["sub_886_887_888.in0","add_grad_x_unclamp_stencil_4_885_886.out"], + ["mul_891_884_892.in1","const_p2__884$1.out"], + ["mul_883_884_885.in1","const_p2__884.out"], + ["self.in1_gray_stencil.0","mul_883_884_885.in0"], + ["self.in1_gray_stencil.3","mul_891_884_892.in0"], + ["sub_890_892_893.in1","mul_891_884_892.out"], + ["sub_886_887_888.in1","self.in1_gray_stencil.1"], + ["sub_893_894_895.in1","self.in1_gray_stencil.4"], + ["sub_893_894_895.in0","sub_890_892_893.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_8":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__2894":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__2894.out"] + ] + }, + "hcompute_grad_x_unclamp_stencil_9":{ + "type":["Record",[ + ["out_grad_x_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__2900":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_x_unclamp_stencil","const_p0__2900.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1241":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__1241.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_1":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1247":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__1247.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_10":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3483":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__3483.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_11":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3490":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__3490.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_12":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_3522_3523_3524":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_3524_3525_3526":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_13_3514_3515":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__3513":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__3513$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_3512_3513_3514":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_3518_3513_3519":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_3515_3516_3517":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3517_3519_3520":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3520_3521_3522":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_3520_3521_3522.out","add_3522_3523_3524.in0"], + ["self.in1_gray_stencil.4","add_3522_3523_3524.in1"], + ["add_3524_3525_3526.in0","add_3522_3523_3524.out"], + ["self.in1_gray_stencil.5","add_3524_3525_3526.in1"], + ["self.out_grad_y_unclamp_stencil","add_3524_3525_3526.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_13_3514_3515.in0"], + ["mul_3512_3513_3514.out","add_grad_y_unclamp_stencil_13_3514_3515.in1"], + ["sub_3515_3516_3517.in0","add_grad_y_unclamp_stencil_13_3514_3515.out"], + ["mul_3518_3513_3519.in1","const_p2__3513$1.out"], + ["mul_3512_3513_3514.in1","const_p2__3513.out"], + ["self.in1_gray_stencil.0","mul_3512_3513_3514.in0"], + ["self.in1_gray_stencil.2","mul_3518_3513_3519.in0"], + ["sub_3517_3519_3520.in1","mul_3518_3513_3519.out"], + ["sub_3515_3516_3517.in1","self.in1_gray_stencil.1"], + ["sub_3520_3521_3522.in1","self.in1_gray_stencil.3"], + ["sub_3517_3519_3520.in0","sub_3515_3516_3517.out"], + ["sub_3520_3521_3522.in0","sub_3517_3519_3520.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_13":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_3580_3581_3582":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_3582_3583_3584":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_14_3572_3573":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__3571":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__3571$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_3570_3571_3572":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_3576_3571_3577":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_3573_3574_3575":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3575_3577_3578":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3578_3579_3580":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_3578_3579_3580.out","add_3580_3581_3582.in0"], + ["self.in1_gray_stencil.4","add_3580_3581_3582.in1"], + ["add_3582_3583_3584.in0","add_3580_3581_3582.out"], + ["self.in1_gray_stencil.5","add_3582_3583_3584.in1"], + ["self.out_grad_y_unclamp_stencil","add_3582_3583_3584.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_14_3572_3573.in0"], + ["mul_3570_3571_3572.out","add_grad_y_unclamp_stencil_14_3572_3573.in1"], + ["sub_3573_3574_3575.in0","add_grad_y_unclamp_stencil_14_3572_3573.out"], + ["mul_3576_3571_3577.in1","const_p2__3571$1.out"], + ["mul_3570_3571_3572.in1","const_p2__3571.out"], + ["self.in1_gray_stencil.0","mul_3570_3571_3572.in0"], + ["self.in1_gray_stencil.2","mul_3576_3571_3577.in0"], + ["sub_3575_3577_3578.in1","mul_3576_3571_3577.out"], + ["sub_3573_3574_3575.in1","self.in1_gray_stencil.1"], + ["sub_3578_3579_3580.in1","self.in1_gray_stencil.3"], + ["sub_3575_3577_3578.in0","sub_3573_3574_3575.out"], + ["sub_3578_3579_3580.in0","sub_3575_3577_3578.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_14":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_3639_3640_3641":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_3641_3642_3643":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_15_3631_3632":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__3630":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__3630$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_3629_3630_3631":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_3635_3630_3636":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_3632_3633_3634":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3634_3636_3637":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3637_3638_3639":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_3637_3638_3639.out","add_3639_3640_3641.in0"], + ["self.in1_gray_stencil.4","add_3639_3640_3641.in1"], + ["add_3641_3642_3643.in0","add_3639_3640_3641.out"], + ["self.in1_gray_stencil.5","add_3641_3642_3643.in1"], + ["self.out_grad_y_unclamp_stencil","add_3641_3642_3643.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_15_3631_3632.in0"], + ["mul_3629_3630_3631.out","add_grad_y_unclamp_stencil_15_3631_3632.in1"], + ["sub_3632_3633_3634.in0","add_grad_y_unclamp_stencil_15_3631_3632.out"], + ["mul_3635_3630_3636.in1","const_p2__3630$1.out"], + ["mul_3629_3630_3631.in1","const_p2__3630.out"], + ["self.in1_gray_stencil.0","mul_3629_3630_3631.in0"], + ["self.in1_gray_stencil.2","mul_3635_3630_3636.in0"], + ["sub_3634_3636_3637.in1","mul_3635_3630_3636.out"], + ["sub_3632_3633_3634.in1","self.in1_gray_stencil.1"], + ["sub_3637_3638_3639.in1","self.in1_gray_stencil.3"], + ["sub_3634_3636_3637.in0","sub_3632_3633_3634.out"], + ["sub_3637_3638_3639.in0","sub_3634_3636_3637.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_15":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_3698_3699_3700":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_3700_3701_3702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_16_3690_3691":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__3689":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__3689$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_3688_3689_3690":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_3694_3689_3695":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_3691_3692_3693":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3693_3695_3696":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_3696_3697_3698":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_3696_3697_3698.out","add_3698_3699_3700.in0"], + ["self.in1_gray_stencil.4","add_3698_3699_3700.in1"], + ["add_3700_3701_3702.in0","add_3698_3699_3700.out"], + ["self.in1_gray_stencil.5","add_3700_3701_3702.in1"], + ["self.out_grad_y_unclamp_stencil","add_3700_3701_3702.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_16_3690_3691.in0"], + ["mul_3688_3689_3690.out","add_grad_y_unclamp_stencil_16_3690_3691.in1"], + ["sub_3691_3692_3693.in0","add_grad_y_unclamp_stencil_16_3690_3691.out"], + ["mul_3694_3689_3695.in1","const_p2__3689$1.out"], + ["mul_3688_3689_3690.in1","const_p2__3689.out"], + ["self.in1_gray_stencil.0","mul_3688_3689_3690.in0"], + ["self.in1_gray_stencil.2","mul_3694_3689_3695.in0"], + ["sub_3693_3695_3696.in1","mul_3694_3689_3695.out"], + ["sub_3691_3692_3693.in1","self.in1_gray_stencil.1"], + ["sub_3696_3697_3698.in1","self.in1_gray_stencil.3"], + ["sub_3693_3695_3696.in0","sub_3691_3692_3693.out"], + ["sub_3696_3697_3698.in0","sub_3693_3695_3696.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_2":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1254":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__1254.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_3":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1261":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__1261.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_4":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1293_1294_1295":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1295_1296_1297":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_1_1285_1286":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__1284":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1284$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_1283_1284_1285":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_1289_1284_1290":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_1286_1287_1288":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1288_1290_1291":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1291_1292_1293":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_1291_1292_1293.out","add_1293_1294_1295.in0"], + ["self.in1_gray_stencil.4","add_1293_1294_1295.in1"], + ["add_1295_1296_1297.in0","add_1293_1294_1295.out"], + ["self.in1_gray_stencil.5","add_1295_1296_1297.in1"], + ["self.out_grad_y_unclamp_stencil","add_1295_1296_1297.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_1_1285_1286.in0"], + ["mul_1283_1284_1285.out","add_grad_y_unclamp_stencil_1_1285_1286.in1"], + ["sub_1286_1287_1288.in0","add_grad_y_unclamp_stencil_1_1285_1286.out"], + ["mul_1289_1284_1290.in1","const_p2__1284$1.out"], + ["mul_1283_1284_1285.in1","const_p2__1284.out"], + ["self.in1_gray_stencil.0","mul_1283_1284_1285.in0"], + ["self.in1_gray_stencil.2","mul_1289_1284_1290.in0"], + ["sub_1288_1290_1291.in1","mul_1289_1284_1290.out"], + ["sub_1286_1287_1288.in1","self.in1_gray_stencil.1"], + ["sub_1291_1292_1293.in1","self.in1_gray_stencil.3"], + ["sub_1288_1290_1291.in0","sub_1286_1287_1288.out"], + ["sub_1291_1292_1293.in0","sub_1288_1290_1291.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_5":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1351_1352_1353":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1353_1354_1355":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_2_1343_1344":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__1342":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1342$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_1341_1342_1343":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_1347_1342_1348":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_1344_1345_1346":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1346_1348_1349":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1349_1350_1351":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_1349_1350_1351.out","add_1351_1352_1353.in0"], + ["self.in1_gray_stencil.4","add_1351_1352_1353.in1"], + ["add_1353_1354_1355.in0","add_1351_1352_1353.out"], + ["self.in1_gray_stencil.5","add_1353_1354_1355.in1"], + ["self.out_grad_y_unclamp_stencil","add_1353_1354_1355.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_2_1343_1344.in0"], + ["mul_1341_1342_1343.out","add_grad_y_unclamp_stencil_2_1343_1344.in1"], + ["sub_1344_1345_1346.in0","add_grad_y_unclamp_stencil_2_1343_1344.out"], + ["mul_1347_1342_1348.in1","const_p2__1342$1.out"], + ["mul_1341_1342_1343.in1","const_p2__1342.out"], + ["self.in1_gray_stencil.0","mul_1341_1342_1343.in0"], + ["self.in1_gray_stencil.2","mul_1347_1342_1348.in0"], + ["sub_1346_1348_1349.in1","mul_1347_1342_1348.out"], + ["sub_1344_1345_1346.in1","self.in1_gray_stencil.1"], + ["sub_1349_1350_1351.in1","self.in1_gray_stencil.3"], + ["sub_1346_1348_1349.in0","sub_1344_1345_1346.out"], + ["sub_1349_1350_1351.in0","sub_1346_1348_1349.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_6":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1410_1411_1412":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1412_1413_1414":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_3_1402_1403":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__1401":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1401$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_1400_1401_1402":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_1406_1401_1407":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_1403_1404_1405":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1405_1407_1408":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1408_1409_1410":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_1408_1409_1410.out","add_1410_1411_1412.in0"], + ["self.in1_gray_stencil.4","add_1410_1411_1412.in1"], + ["add_1412_1413_1414.in0","add_1410_1411_1412.out"], + ["self.in1_gray_stencil.5","add_1412_1413_1414.in1"], + ["self.out_grad_y_unclamp_stencil","add_1412_1413_1414.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_3_1402_1403.in0"], + ["mul_1400_1401_1402.out","add_grad_y_unclamp_stencil_3_1402_1403.in1"], + ["sub_1403_1404_1405.in0","add_grad_y_unclamp_stencil_3_1402_1403.out"], + ["mul_1406_1401_1407.in1","const_p2__1401$1.out"], + ["mul_1400_1401_1402.in1","const_p2__1401.out"], + ["self.in1_gray_stencil.0","mul_1400_1401_1402.in0"], + ["self.in1_gray_stencil.2","mul_1406_1401_1407.in0"], + ["sub_1405_1407_1408.in1","mul_1406_1401_1407.out"], + ["sub_1403_1404_1405.in1","self.in1_gray_stencil.1"], + ["sub_1408_1409_1410.in1","self.in1_gray_stencil.3"], + ["sub_1405_1407_1408.in0","sub_1403_1404_1405.out"], + ["sub_1408_1409_1410.in0","sub_1405_1407_1408.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_7":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1469_1470_1471":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1471_1472_1473":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_grad_y_unclamp_stencil_4_1461_1462":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p2__1460":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1460$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "mul_1459_1460_1461":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_1465_1460_1466":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_1462_1463_1464":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1464_1466_1467":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_1467_1468_1469":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_1467_1468_1469.out","add_1469_1470_1471.in0"], + ["self.in1_gray_stencil.4","add_1469_1470_1471.in1"], + ["add_1471_1472_1473.in0","add_1469_1470_1471.out"], + ["self.in1_gray_stencil.5","add_1471_1472_1473.in1"], + ["self.out_grad_y_unclamp_stencil","add_1471_1472_1473.out"], + ["self.in0_grad_y_unclamp_stencil.0","add_grad_y_unclamp_stencil_4_1461_1462.in0"], + ["mul_1459_1460_1461.out","add_grad_y_unclamp_stencil_4_1461_1462.in1"], + ["sub_1462_1463_1464.in0","add_grad_y_unclamp_stencil_4_1461_1462.out"], + ["mul_1465_1460_1466.in1","const_p2__1460$1.out"], + ["mul_1459_1460_1461.in1","const_p2__1460.out"], + ["self.in1_gray_stencil.0","mul_1459_1460_1461.in0"], + ["self.in1_gray_stencil.2","mul_1465_1460_1466.in0"], + ["sub_1464_1466_1467.in1","mul_1465_1460_1466.out"], + ["sub_1462_1463_1464.in1","self.in1_gray_stencil.1"], + ["sub_1467_1468_1469.in1","self.in1_gray_stencil.3"], + ["sub_1464_1466_1467.in0","sub_1462_1463_1464.out"], + ["sub_1467_1468_1469.in0","sub_1464_1466_1467.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_8":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3470":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__3470.out"] + ] + }, + "hcompute_grad_y_unclamp_stencil_9":{ + "type":["Record",[ + ["out_grad_y_unclamp_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3476":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_grad_y_unclamp_stencil","const_p0__3476.out"] + ] + }, + "hcompute_gray_stencil":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_495_502_503":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_498_501_502":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__494":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__497":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__500":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__504$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_503_504_505":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_493_494_495":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_496_497_498":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_499_500_501":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_493_494_495.out","add_495_502_503.in0"], + ["add_498_501_502.out","add_495_502_503.in1"], + ["lshr_503_504_505.in0","add_495_502_503.out"], + ["mul_496_497_498.out","add_498_501_502.in0"], + ["mul_499_500_501.out","add_498_501_502.in1"], + ["mul_493_494_495.in1","const_p150__494.out"], + ["mul_496_497_498.in1","const_p29__497.out"], + ["mul_499_500_501.in1","const_p77__500.out"], + ["lshr_503_504_505.in1","const_p8__504$1.out"], + ["self.out_gray_stencil","lshr_503_504_505.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_493_494_495.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_496_497_498.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_499_500_501.in0"] + ] + }, + "hcompute_gray_stencil_1":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_540_547_548":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_543_546_547":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__539":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__542":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__545":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__549":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_548_549_550":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_538_539_540":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_541_542_543":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_544_545_546":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_538_539_540.out","add_540_547_548.in0"], + ["add_543_546_547.out","add_540_547_548.in1"], + ["lshr_548_549_550.in0","add_540_547_548.out"], + ["mul_541_542_543.out","add_543_546_547.in0"], + ["mul_544_545_546.out","add_543_546_547.in1"], + ["mul_538_539_540.in1","const_p150__539.out"], + ["mul_541_542_543.in1","const_p29__542.out"], + ["mul_544_545_546.in1","const_p77__545.out"], + ["lshr_548_549_550.in1","const_p8__549.out"], + ["self.out_gray_stencil","lshr_548_549_550.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_538_539_540.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_541_542_543.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_544_545_546.in0"] + ] + }, + "hcompute_gray_stencil_2":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_586_593_594":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_589_592_593":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__585":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__588":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__591":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__595":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_594_595_596":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_584_585_586":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_587_588_589":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_590_591_592":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_584_585_586.out","add_586_593_594.in0"], + ["add_589_592_593.out","add_586_593_594.in1"], + ["lshr_594_595_596.in0","add_586_593_594.out"], + ["mul_587_588_589.out","add_589_592_593.in0"], + ["mul_590_591_592.out","add_589_592_593.in1"], + ["mul_584_585_586.in1","const_p150__585.out"], + ["mul_587_588_589.in1","const_p29__588.out"], + ["mul_590_591_592.in1","const_p77__591.out"], + ["lshr_594_595_596.in1","const_p8__595.out"], + ["self.out_gray_stencil","lshr_594_595_596.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_584_585_586.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_587_588_589.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_590_591_592.in0"] + ] + }, + "hcompute_gray_stencil_3":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_632_639_640":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_635_638_639":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__631":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__634":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__637":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__641":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_640_641_642":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_630_631_632":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_633_634_635":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_636_637_638":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_630_631_632.out","add_632_639_640.in0"], + ["add_635_638_639.out","add_632_639_640.in1"], + ["lshr_640_641_642.in0","add_632_639_640.out"], + ["mul_633_634_635.out","add_635_638_639.in0"], + ["mul_636_637_638.out","add_635_638_639.in1"], + ["mul_630_631_632.in1","const_p150__631.out"], + ["mul_633_634_635.in1","const_p29__634.out"], + ["mul_636_637_638.in1","const_p77__637.out"], + ["lshr_640_641_642.in1","const_p8__641.out"], + ["self.out_gray_stencil","lshr_640_641_642.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_630_631_632.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_633_634_635.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_636_637_638.in0"] + ] + }, + "hcompute_gray_stencil_4":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2724_2731_2732":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2727_2730_2731":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__2723":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__2726":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__2729":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__2733":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_2732_2733_2734":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_2722_2723_2724":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2725_2726_2727":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2728_2729_2730":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_2722_2723_2724.out","add_2724_2731_2732.in0"], + ["add_2727_2730_2731.out","add_2724_2731_2732.in1"], + ["lshr_2732_2733_2734.in0","add_2724_2731_2732.out"], + ["mul_2725_2726_2727.out","add_2727_2730_2731.in0"], + ["mul_2728_2729_2730.out","add_2727_2730_2731.in1"], + ["mul_2722_2723_2724.in1","const_p150__2723.out"], + ["mul_2725_2726_2727.in1","const_p29__2726.out"], + ["mul_2728_2729_2730.in1","const_p77__2729.out"], + ["lshr_2732_2733_2734.in1","const_p8__2733.out"], + ["self.out_gray_stencil","lshr_2732_2733_2734.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_2722_2723_2724.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_2725_2726_2727.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_2728_2729_2730.in0"] + ] + }, + "hcompute_gray_stencil_5":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2769_2776_2777":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2772_2775_2776":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__2768$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__2771":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__2774":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__2778":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_2777_2778_2779":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_2767_2768_2769":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2770_2771_2772":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2773_2774_2775":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_2767_2768_2769.out","add_2769_2776_2777.in0"], + ["add_2772_2775_2776.out","add_2769_2776_2777.in1"], + ["lshr_2777_2778_2779.in0","add_2769_2776_2777.out"], + ["mul_2770_2771_2772.out","add_2772_2775_2776.in0"], + ["mul_2773_2774_2775.out","add_2772_2775_2776.in1"], + ["mul_2767_2768_2769.in1","const_p150__2768$1.out"], + ["mul_2770_2771_2772.in1","const_p29__2771.out"], + ["mul_2773_2774_2775.in1","const_p77__2774.out"], + ["lshr_2777_2778_2779.in1","const_p8__2778.out"], + ["self.out_gray_stencil","lshr_2777_2778_2779.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_2767_2768_2769.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_2770_2771_2772.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_2773_2774_2775.in0"] + ] + }, + "hcompute_gray_stencil_6":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2815_2822_2823":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2818_2821_2822":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__2814":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__2817":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__2820":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__2824":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_2823_2824_2825":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_2813_2814_2815":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2816_2817_2818":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2819_2820_2821":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_2813_2814_2815.out","add_2815_2822_2823.in0"], + ["add_2818_2821_2822.out","add_2815_2822_2823.in1"], + ["lshr_2823_2824_2825.in0","add_2815_2822_2823.out"], + ["mul_2816_2817_2818.out","add_2818_2821_2822.in0"], + ["mul_2819_2820_2821.out","add_2818_2821_2822.in1"], + ["mul_2813_2814_2815.in1","const_p150__2814.out"], + ["mul_2816_2817_2818.in1","const_p29__2817.out"], + ["mul_2819_2820_2821.in1","const_p77__2820.out"], + ["lshr_2823_2824_2825.in1","const_p8__2824.out"], + ["self.out_gray_stencil","lshr_2823_2824_2825.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_2813_2814_2815.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_2816_2817_2818.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_2819_2820_2821.in0"] + ] + }, + "hcompute_gray_stencil_7":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_2861_2868_2869":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_2864_2867_2868":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__2860":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__2863":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__2866":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__2870":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_2869_2870_2871":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_2859_2860_2861":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2862_2863_2864":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_2865_2866_2867":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_2859_2860_2861.out","add_2861_2868_2869.in0"], + ["add_2864_2867_2868.out","add_2861_2868_2869.in1"], + ["lshr_2869_2870_2871.in0","add_2861_2868_2869.out"], + ["mul_2862_2863_2864.out","add_2864_2867_2868.in0"], + ["mul_2865_2866_2867.out","add_2864_2867_2868.in1"], + ["mul_2859_2860_2861.in1","const_p150__2860.out"], + ["mul_2862_2863_2864.in1","const_p29__2863.out"], + ["mul_2865_2866_2867.in1","const_p77__2866.out"], + ["lshr_2869_2870_2871.in1","const_p8__2870.out"], + ["self.out_gray_stencil","lshr_2869_2870_2871.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_2859_2860_2861.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_2862_2863_2864.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_2865_2866_2867.in0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_10":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_11":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_4":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_5":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_6":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_7":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_8":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_9":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_10":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_11":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_12":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_13":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_14":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_15":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_16":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_17":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_18":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_19":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_20":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_21":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_22":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_23":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_4":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_5":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_6":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_7":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_8":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_9":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_2348_2349_2350":{ + "modref":"corebit.and" + }, + "bitand_2350_2351_2352":{ + "modref":"corebit.and" + }, + "bitand_2352_2353_2354":{ + "modref":"corebit.and" + }, + "bitand_2354_2355_2356":{ + "modref":"corebit.and" + }, + "bitand_2356_2357_2358":{ + "modref":"corebit.and" + }, + "bitand_2358_2359_2360":{ + "modref":"corebit.and" + }, + "bitand_2360_2361_2362":{ + "modref":"corebit.and" + }, + "bitand_2362_2364_2365":{ + "modref":"corebit.and" + }, + "const_p0__2367":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__2363":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__2366":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_2365_2366_2367":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_2363_cim_stencil_2_2364":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_1_cim_stencil_2_2348":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_3_cim_stencil_2_2349":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_4_cim_stencil_2_2351":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_5_cim_stencil_2_2353":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_6_cim_stencil_2_2355":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_7_cim_stencil_2_2357":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_8_cim_stencil_2_2359":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_9_cim_stencil_2_2361":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_1_cim_stencil_2_2348.out","bitand_2348_2349_2350.in0"], + ["slt_cim_stencil_3_cim_stencil_2_2349.out","bitand_2348_2349_2350.in1"], + ["bitand_2350_2351_2352.in0","bitand_2348_2349_2350.out"], + ["slt_cim_stencil_4_cim_stencil_2_2351.out","bitand_2350_2351_2352.in1"], + ["bitand_2352_2353_2354.in0","bitand_2350_2351_2352.out"], + ["slt_cim_stencil_5_cim_stencil_2_2353.out","bitand_2352_2353_2354.in1"], + ["bitand_2354_2355_2356.in0","bitand_2352_2353_2354.out"], + ["slt_cim_stencil_6_cim_stencil_2_2355.out","bitand_2354_2355_2356.in1"], + ["bitand_2356_2357_2358.in0","bitand_2354_2355_2356.out"], + ["slt_cim_stencil_7_cim_stencil_2_2357.out","bitand_2356_2357_2358.in1"], + ["bitand_2358_2359_2360.in0","bitand_2356_2357_2358.out"], + ["slt_cim_stencil_8_cim_stencil_2_2359.out","bitand_2358_2359_2360.in1"], + ["bitand_2360_2361_2362.in0","bitand_2358_2359_2360.out"], + ["slt_cim_stencil_9_cim_stencil_2_2361.out","bitand_2360_2361_2362.in1"], + ["bitand_2362_2364_2365.in0","bitand_2360_2361_2362.out"], + ["sle_2363_cim_stencil_2_2364.out","bitand_2362_2364_2365.in1"], + ["mux_2365_2366_2367.sel","bitand_2362_2364_2365.out"], + ["mux_2365_2366_2367.in0","const_p0__2367.out"], + ["sle_2363_cim_stencil_2_2364.in0","const_p1__2363.out"], + ["mux_2365_2366_2367.in1","const_p255__2366.out"], + ["self.out_hw_output_glb_stencil","mux_2365_2366_2367.out"], + ["slt_cim_stencil_1_cim_stencil_2_2348.in0","self.in0_cim_stencil.0"], + ["sle_2363_cim_stencil_2_2364.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_1_cim_stencil_2_2348.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_3_cim_stencil_2_2349.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_4_cim_stencil_2_2351.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_5_cim_stencil_2_2353.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_6_cim_stencil_2_2355.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_7_cim_stencil_2_2357.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_8_cim_stencil_2_2359.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_9_cim_stencil_2_2361.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_3_cim_stencil_2_2349.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_4_cim_stencil_2_2351.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_5_cim_stencil_2_2353.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_6_cim_stencil_2_2355.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_7_cim_stencil_2_2357.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_8_cim_stencil_2_2359.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_9_cim_stencil_2_2361.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_2425_2426_2427":{ + "modref":"corebit.and" + }, + "bitand_2427_2428_2429":{ + "modref":"corebit.and" + }, + "bitand_2429_2430_2431":{ + "modref":"corebit.and" + }, + "bitand_2431_2432_2433":{ + "modref":"corebit.and" + }, + "bitand_2433_2434_2435":{ + "modref":"corebit.and" + }, + "bitand_2435_2436_2437":{ + "modref":"corebit.and" + }, + "bitand_2437_2438_2439":{ + "modref":"corebit.and" + }, + "bitand_2439_2441_2442":{ + "modref":"corebit.and" + }, + "const_p0__2444":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__2440":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__2443":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_2442_2443_2444":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_2440_cim_stencil_11_2441":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_10_cim_stencil_11_2425":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_12_cim_stencil_11_2426":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_13_cim_stencil_11_2428":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_14_cim_stencil_11_2430":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_15_cim_stencil_11_2432":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_16_cim_stencil_11_2434":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_17_cim_stencil_11_2436":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_18_cim_stencil_11_2438":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_10_cim_stencil_11_2425.out","bitand_2425_2426_2427.in0"], + ["slt_cim_stencil_12_cim_stencil_11_2426.out","bitand_2425_2426_2427.in1"], + ["bitand_2427_2428_2429.in0","bitand_2425_2426_2427.out"], + ["slt_cim_stencil_13_cim_stencil_11_2428.out","bitand_2427_2428_2429.in1"], + ["bitand_2429_2430_2431.in0","bitand_2427_2428_2429.out"], + ["slt_cim_stencil_14_cim_stencil_11_2430.out","bitand_2429_2430_2431.in1"], + ["bitand_2431_2432_2433.in0","bitand_2429_2430_2431.out"], + ["slt_cim_stencil_15_cim_stencil_11_2432.out","bitand_2431_2432_2433.in1"], + ["bitand_2433_2434_2435.in0","bitand_2431_2432_2433.out"], + ["slt_cim_stencil_16_cim_stencil_11_2434.out","bitand_2433_2434_2435.in1"], + ["bitand_2435_2436_2437.in0","bitand_2433_2434_2435.out"], + ["slt_cim_stencil_17_cim_stencil_11_2436.out","bitand_2435_2436_2437.in1"], + ["bitand_2437_2438_2439.in0","bitand_2435_2436_2437.out"], + ["slt_cim_stencil_18_cim_stencil_11_2438.out","bitand_2437_2438_2439.in1"], + ["bitand_2439_2441_2442.in0","bitand_2437_2438_2439.out"], + ["sle_2440_cim_stencil_11_2441.out","bitand_2439_2441_2442.in1"], + ["mux_2442_2443_2444.sel","bitand_2439_2441_2442.out"], + ["mux_2442_2443_2444.in0","const_p0__2444.out"], + ["sle_2440_cim_stencil_11_2441.in0","const_p1__2440.out"], + ["mux_2442_2443_2444.in1","const_p255__2443.out"], + ["self.out_hw_output_glb_stencil","mux_2442_2443_2444.out"], + ["slt_cim_stencil_10_cim_stencil_11_2425.in0","self.in0_cim_stencil.0"], + ["sle_2440_cim_stencil_11_2441.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_10_cim_stencil_11_2425.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_12_cim_stencil_11_2426.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_13_cim_stencil_11_2428.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_14_cim_stencil_11_2430.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_15_cim_stencil_11_2432.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_16_cim_stencil_11_2434.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_17_cim_stencil_11_2436.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_18_cim_stencil_11_2438.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_12_cim_stencil_11_2426.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_13_cim_stencil_11_2428.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_14_cim_stencil_11_2430.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_15_cim_stencil_11_2432.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_16_cim_stencil_11_2434.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_17_cim_stencil_11_2436.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_18_cim_stencil_11_2438.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_2503_2504_2505":{ + "modref":"corebit.and" + }, + "bitand_2505_2506_2507":{ + "modref":"corebit.and" + }, + "bitand_2507_2508_2509":{ + "modref":"corebit.and" + }, + "bitand_2509_2510_2511":{ + "modref":"corebit.and" + }, + "bitand_2511_2512_2513":{ + "modref":"corebit.and" + }, + "bitand_2513_2514_2515":{ + "modref":"corebit.and" + }, + "bitand_2515_2516_2517":{ + "modref":"corebit.and" + }, + "bitand_2517_2519_2520":{ + "modref":"corebit.and" + }, + "const_p0__2522":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__2518":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__2521":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_2520_2521_2522":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_2518_cim_stencil_20_2519":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_19_cim_stencil_20_2503":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_21_cim_stencil_20_2504":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_22_cim_stencil_20_2506":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_23_cim_stencil_20_2508":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_24_cim_stencil_20_2510":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_25_cim_stencil_20_2512":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_26_cim_stencil_20_2514":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_27_cim_stencil_20_2516":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_19_cim_stencil_20_2503.out","bitand_2503_2504_2505.in0"], + ["slt_cim_stencil_21_cim_stencil_20_2504.out","bitand_2503_2504_2505.in1"], + ["bitand_2505_2506_2507.in0","bitand_2503_2504_2505.out"], + ["slt_cim_stencil_22_cim_stencil_20_2506.out","bitand_2505_2506_2507.in1"], + ["bitand_2507_2508_2509.in0","bitand_2505_2506_2507.out"], + ["slt_cim_stencil_23_cim_stencil_20_2508.out","bitand_2507_2508_2509.in1"], + ["bitand_2509_2510_2511.in0","bitand_2507_2508_2509.out"], + ["slt_cim_stencil_24_cim_stencil_20_2510.out","bitand_2509_2510_2511.in1"], + ["bitand_2511_2512_2513.in0","bitand_2509_2510_2511.out"], + ["slt_cim_stencil_25_cim_stencil_20_2512.out","bitand_2511_2512_2513.in1"], + ["bitand_2513_2514_2515.in0","bitand_2511_2512_2513.out"], + ["slt_cim_stencil_26_cim_stencil_20_2514.out","bitand_2513_2514_2515.in1"], + ["bitand_2515_2516_2517.in0","bitand_2513_2514_2515.out"], + ["slt_cim_stencil_27_cim_stencil_20_2516.out","bitand_2515_2516_2517.in1"], + ["bitand_2517_2519_2520.in0","bitand_2515_2516_2517.out"], + ["sle_2518_cim_stencil_20_2519.out","bitand_2517_2519_2520.in1"], + ["mux_2520_2521_2522.sel","bitand_2517_2519_2520.out"], + ["mux_2520_2521_2522.in0","const_p0__2522.out"], + ["sle_2518_cim_stencil_20_2519.in0","const_p1__2518.out"], + ["mux_2520_2521_2522.in1","const_p255__2521.out"], + ["self.out_hw_output_glb_stencil","mux_2520_2521_2522.out"], + ["slt_cim_stencil_19_cim_stencil_20_2503.in0","self.in0_cim_stencil.0"], + ["sle_2518_cim_stencil_20_2519.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_19_cim_stencil_20_2503.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_21_cim_stencil_20_2504.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_22_cim_stencil_20_2506.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_23_cim_stencil_20_2508.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_24_cim_stencil_20_2510.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_25_cim_stencil_20_2512.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_26_cim_stencil_20_2514.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_27_cim_stencil_20_2516.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_21_cim_stencil_20_2504.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_22_cim_stencil_20_2506.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_23_cim_stencil_20_2508.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_24_cim_stencil_20_2510.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_25_cim_stencil_20_2512.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_26_cim_stencil_20_2514.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_27_cim_stencil_20_2516.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_glb_stencil_3":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_2581_2582_2583":{ + "modref":"corebit.and" + }, + "bitand_2583_2584_2585":{ + "modref":"corebit.and" + }, + "bitand_2585_2586_2587":{ + "modref":"corebit.and" + }, + "bitand_2587_2588_2589":{ + "modref":"corebit.and" + }, + "bitand_2589_2590_2591":{ + "modref":"corebit.and" + }, + "bitand_2591_2592_2593":{ + "modref":"corebit.and" + }, + "bitand_2593_2594_2595":{ + "modref":"corebit.and" + }, + "bitand_2595_2597_2598":{ + "modref":"corebit.and" + }, + "const_p0__2600":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__2596":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__2599":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_2598_2599_2600":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_2596_cim_stencil_29_2597":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_28_cim_stencil_29_2581":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_30_cim_stencil_29_2582":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_31_cim_stencil_29_2584":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_32_cim_stencil_29_2586":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_33_cim_stencil_29_2588":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_34_cim_stencil_29_2590":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_35_cim_stencil_29_2592":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_36_cim_stencil_29_2594":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_28_cim_stencil_29_2581.out","bitand_2581_2582_2583.in0"], + ["slt_cim_stencil_30_cim_stencil_29_2582.out","bitand_2581_2582_2583.in1"], + ["bitand_2583_2584_2585.in0","bitand_2581_2582_2583.out"], + ["slt_cim_stencil_31_cim_stencil_29_2584.out","bitand_2583_2584_2585.in1"], + ["bitand_2585_2586_2587.in0","bitand_2583_2584_2585.out"], + ["slt_cim_stencil_32_cim_stencil_29_2586.out","bitand_2585_2586_2587.in1"], + ["bitand_2587_2588_2589.in0","bitand_2585_2586_2587.out"], + ["slt_cim_stencil_33_cim_stencil_29_2588.out","bitand_2587_2588_2589.in1"], + ["bitand_2589_2590_2591.in0","bitand_2587_2588_2589.out"], + ["slt_cim_stencil_34_cim_stencil_29_2590.out","bitand_2589_2590_2591.in1"], + ["bitand_2591_2592_2593.in0","bitand_2589_2590_2591.out"], + ["slt_cim_stencil_35_cim_stencil_29_2592.out","bitand_2591_2592_2593.in1"], + ["bitand_2593_2594_2595.in0","bitand_2591_2592_2593.out"], + ["slt_cim_stencil_36_cim_stencil_29_2594.out","bitand_2593_2594_2595.in1"], + ["bitand_2595_2597_2598.in0","bitand_2593_2594_2595.out"], + ["sle_2596_cim_stencil_29_2597.out","bitand_2595_2597_2598.in1"], + ["mux_2598_2599_2600.sel","bitand_2595_2597_2598.out"], + ["mux_2598_2599_2600.in0","const_p0__2600.out"], + ["sle_2596_cim_stencil_29_2597.in0","const_p1__2596.out"], + ["mux_2598_2599_2600.in1","const_p255__2599.out"], + ["self.out_hw_output_glb_stencil","mux_2598_2599_2600.out"], + ["slt_cim_stencil_28_cim_stencil_29_2581.in0","self.in0_cim_stencil.0"], + ["sle_2596_cim_stencil_29_2597.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_28_cim_stencil_29_2581.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_30_cim_stencil_29_2582.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_31_cim_stencil_29_2584.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_32_cim_stencil_29_2586.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_33_cim_stencil_29_2588.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_34_cim_stencil_29_2590.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_35_cim_stencil_29_2592.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_36_cim_stencil_29_2594.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_30_cim_stencil_29_2582.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_31_cim_stencil_29_2584.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_32_cim_stencil_29_2586.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_33_cim_stencil_29_2588.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_34_cim_stencil_29_2590.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_35_cim_stencil_29_2592.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_36_cim_stencil_29_2594.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_glb_stencil_4":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_4577_4578_4579":{ + "modref":"corebit.and" + }, + "bitand_4579_4580_4581":{ + "modref":"corebit.and" + }, + "bitand_4581_4582_4583":{ + "modref":"corebit.and" + }, + "bitand_4583_4584_4585":{ + "modref":"corebit.and" + }, + "bitand_4585_4586_4587":{ + "modref":"corebit.and" + }, + "bitand_4587_4588_4589":{ + "modref":"corebit.and" + }, + "bitand_4589_4590_4591":{ + "modref":"corebit.and" + }, + "bitand_4591_4593_4594":{ + "modref":"corebit.and" + }, + "const_p0__4596":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__4592":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__4595":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_4594_4595_4596":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_4592_cim_stencil_38_4593":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_37_cim_stencil_38_4577":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_39_cim_stencil_38_4578":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_40_cim_stencil_38_4580":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_41_cim_stencil_38_4582":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_42_cim_stencil_38_4584":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_43_cim_stencil_38_4586":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_44_cim_stencil_38_4588":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_45_cim_stencil_38_4590":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_37_cim_stencil_38_4577.out","bitand_4577_4578_4579.in0"], + ["slt_cim_stencil_39_cim_stencil_38_4578.out","bitand_4577_4578_4579.in1"], + ["bitand_4579_4580_4581.in0","bitand_4577_4578_4579.out"], + ["slt_cim_stencil_40_cim_stencil_38_4580.out","bitand_4579_4580_4581.in1"], + ["bitand_4581_4582_4583.in0","bitand_4579_4580_4581.out"], + ["slt_cim_stencil_41_cim_stencil_38_4582.out","bitand_4581_4582_4583.in1"], + ["bitand_4583_4584_4585.in0","bitand_4581_4582_4583.out"], + ["slt_cim_stencil_42_cim_stencil_38_4584.out","bitand_4583_4584_4585.in1"], + ["bitand_4585_4586_4587.in0","bitand_4583_4584_4585.out"], + ["slt_cim_stencil_43_cim_stencil_38_4586.out","bitand_4585_4586_4587.in1"], + ["bitand_4587_4588_4589.in0","bitand_4585_4586_4587.out"], + ["slt_cim_stencil_44_cim_stencil_38_4588.out","bitand_4587_4588_4589.in1"], + ["bitand_4589_4590_4591.in0","bitand_4587_4588_4589.out"], + ["slt_cim_stencil_45_cim_stencil_38_4590.out","bitand_4589_4590_4591.in1"], + ["bitand_4591_4593_4594.in0","bitand_4589_4590_4591.out"], + ["sle_4592_cim_stencil_38_4593.out","bitand_4591_4593_4594.in1"], + ["mux_4594_4595_4596.sel","bitand_4591_4593_4594.out"], + ["mux_4594_4595_4596.in0","const_p0__4596.out"], + ["sle_4592_cim_stencil_38_4593.in0","const_p1__4592.out"], + ["mux_4594_4595_4596.in1","const_p255__4595.out"], + ["self.out_hw_output_glb_stencil","mux_4594_4595_4596.out"], + ["slt_cim_stencil_37_cim_stencil_38_4577.in0","self.in0_cim_stencil.0"], + ["sle_4592_cim_stencil_38_4593.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_37_cim_stencil_38_4577.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_39_cim_stencil_38_4578.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_40_cim_stencil_38_4580.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_41_cim_stencil_38_4582.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_42_cim_stencil_38_4584.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_43_cim_stencil_38_4586.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_44_cim_stencil_38_4588.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_45_cim_stencil_38_4590.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_39_cim_stencil_38_4578.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_40_cim_stencil_38_4580.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_41_cim_stencil_38_4582.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_42_cim_stencil_38_4584.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_43_cim_stencil_38_4586.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_44_cim_stencil_38_4588.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_45_cim_stencil_38_4590.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_glb_stencil_5":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_4654_4655_4656":{ + "modref":"corebit.and" + }, + "bitand_4656_4657_4658":{ + "modref":"corebit.and" + }, + "bitand_4658_4659_4660":{ + "modref":"corebit.and" + }, + "bitand_4660_4661_4662":{ + "modref":"corebit.and" + }, + "bitand_4662_4663_4664":{ + "modref":"corebit.and" + }, + "bitand_4664_4665_4666":{ + "modref":"corebit.and" + }, + "bitand_4666_4667_4668":{ + "modref":"corebit.and" + }, + "bitand_4668_4670_4671":{ + "modref":"corebit.and" + }, + "const_p0__4673":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__4669":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__4672":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_4671_4672_4673":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_4669_cim_stencil_47_4670":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_46_cim_stencil_47_4654":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_48_cim_stencil_47_4655":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_49_cim_stencil_47_4657":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_50_cim_stencil_47_4659":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_51_cim_stencil_47_4661":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_52_cim_stencil_47_4663":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_53_cim_stencil_47_4665":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_54_cim_stencil_47_4667":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_46_cim_stencil_47_4654.out","bitand_4654_4655_4656.in0"], + ["slt_cim_stencil_48_cim_stencil_47_4655.out","bitand_4654_4655_4656.in1"], + ["bitand_4656_4657_4658.in0","bitand_4654_4655_4656.out"], + ["slt_cim_stencil_49_cim_stencil_47_4657.out","bitand_4656_4657_4658.in1"], + ["bitand_4658_4659_4660.in0","bitand_4656_4657_4658.out"], + ["slt_cim_stencil_50_cim_stencil_47_4659.out","bitand_4658_4659_4660.in1"], + ["bitand_4660_4661_4662.in0","bitand_4658_4659_4660.out"], + ["slt_cim_stencil_51_cim_stencil_47_4661.out","bitand_4660_4661_4662.in1"], + ["bitand_4662_4663_4664.in0","bitand_4660_4661_4662.out"], + ["slt_cim_stencil_52_cim_stencil_47_4663.out","bitand_4662_4663_4664.in1"], + ["bitand_4664_4665_4666.in0","bitand_4662_4663_4664.out"], + ["slt_cim_stencil_53_cim_stencil_47_4665.out","bitand_4664_4665_4666.in1"], + ["bitand_4666_4667_4668.in0","bitand_4664_4665_4666.out"], + ["slt_cim_stencil_54_cim_stencil_47_4667.out","bitand_4666_4667_4668.in1"], + ["bitand_4668_4670_4671.in0","bitand_4666_4667_4668.out"], + ["sle_4669_cim_stencil_47_4670.out","bitand_4668_4670_4671.in1"], + ["mux_4671_4672_4673.sel","bitand_4668_4670_4671.out"], + ["mux_4671_4672_4673.in0","const_p0__4673.out"], + ["sle_4669_cim_stencil_47_4670.in0","const_p1__4669.out"], + ["mux_4671_4672_4673.in1","const_p255__4672.out"], + ["self.out_hw_output_glb_stencil","mux_4671_4672_4673.out"], + ["slt_cim_stencil_46_cim_stencil_47_4654.in0","self.in0_cim_stencil.0"], + ["sle_4669_cim_stencil_47_4670.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_46_cim_stencil_47_4654.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_48_cim_stencil_47_4655.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_49_cim_stencil_47_4657.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_50_cim_stencil_47_4659.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_51_cim_stencil_47_4661.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_52_cim_stencil_47_4663.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_53_cim_stencil_47_4665.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_54_cim_stencil_47_4667.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_48_cim_stencil_47_4655.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_49_cim_stencil_47_4657.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_50_cim_stencil_47_4659.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_51_cim_stencil_47_4661.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_52_cim_stencil_47_4663.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_53_cim_stencil_47_4665.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_54_cim_stencil_47_4667.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_glb_stencil_6":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_4732_4733_4734":{ + "modref":"corebit.and" + }, + "bitand_4734_4735_4736":{ + "modref":"corebit.and" + }, + "bitand_4736_4737_4738":{ + "modref":"corebit.and" + }, + "bitand_4738_4739_4740":{ + "modref":"corebit.and" + }, + "bitand_4740_4741_4742":{ + "modref":"corebit.and" + }, + "bitand_4742_4743_4744":{ + "modref":"corebit.and" + }, + "bitand_4744_4745_4746":{ + "modref":"corebit.and" + }, + "bitand_4746_4748_4749":{ + "modref":"corebit.and" + }, + "const_p0__4751":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__4747":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__4750":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_4749_4750_4751":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_4747_cim_stencil_56_4748":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_55_cim_stencil_56_4732":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_57_cim_stencil_56_4733":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_58_cim_stencil_56_4735":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_59_cim_stencil_56_4737":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_60_cim_stencil_56_4739":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_61_cim_stencil_56_4741":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_62_cim_stencil_56_4743":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_63_cim_stencil_56_4745":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_55_cim_stencil_56_4732.out","bitand_4732_4733_4734.in0"], + ["slt_cim_stencil_57_cim_stencil_56_4733.out","bitand_4732_4733_4734.in1"], + ["bitand_4734_4735_4736.in0","bitand_4732_4733_4734.out"], + ["slt_cim_stencil_58_cim_stencil_56_4735.out","bitand_4734_4735_4736.in1"], + ["bitand_4736_4737_4738.in0","bitand_4734_4735_4736.out"], + ["slt_cim_stencil_59_cim_stencil_56_4737.out","bitand_4736_4737_4738.in1"], + ["bitand_4738_4739_4740.in0","bitand_4736_4737_4738.out"], + ["slt_cim_stencil_60_cim_stencil_56_4739.out","bitand_4738_4739_4740.in1"], + ["bitand_4740_4741_4742.in0","bitand_4738_4739_4740.out"], + ["slt_cim_stencil_61_cim_stencil_56_4741.out","bitand_4740_4741_4742.in1"], + ["bitand_4742_4743_4744.in0","bitand_4740_4741_4742.out"], + ["slt_cim_stencil_62_cim_stencil_56_4743.out","bitand_4742_4743_4744.in1"], + ["bitand_4744_4745_4746.in0","bitand_4742_4743_4744.out"], + ["slt_cim_stencil_63_cim_stencil_56_4745.out","bitand_4744_4745_4746.in1"], + ["bitand_4746_4748_4749.in0","bitand_4744_4745_4746.out"], + ["sle_4747_cim_stencil_56_4748.out","bitand_4746_4748_4749.in1"], + ["mux_4749_4750_4751.sel","bitand_4746_4748_4749.out"], + ["mux_4749_4750_4751.in0","const_p0__4751.out"], + ["sle_4747_cim_stencil_56_4748.in0","const_p1__4747.out"], + ["mux_4749_4750_4751.in1","const_p255__4750.out"], + ["self.out_hw_output_glb_stencil","mux_4749_4750_4751.out"], + ["slt_cim_stencil_55_cim_stencil_56_4732.in0","self.in0_cim_stencil.0"], + ["sle_4747_cim_stencil_56_4748.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_55_cim_stencil_56_4732.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_57_cim_stencil_56_4733.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_58_cim_stencil_56_4735.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_59_cim_stencil_56_4737.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_60_cim_stencil_56_4739.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_61_cim_stencil_56_4741.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_62_cim_stencil_56_4743.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_63_cim_stencil_56_4745.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_57_cim_stencil_56_4733.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_58_cim_stencil_56_4735.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_59_cim_stencil_56_4737.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_60_cim_stencil_56_4739.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_61_cim_stencil_56_4741.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_62_cim_stencil_56_4743.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_63_cim_stencil_56_4745.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_glb_stencil_7":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_cim_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "bitand_4810_4811_4812":{ + "modref":"corebit.and" + }, + "bitand_4812_4813_4814":{ + "modref":"corebit.and" + }, + "bitand_4814_4815_4816":{ + "modref":"corebit.and" + }, + "bitand_4816_4817_4818":{ + "modref":"corebit.and" + }, + "bitand_4818_4819_4820":{ + "modref":"corebit.and" + }, + "bitand_4820_4821_4822":{ + "modref":"corebit.and" + }, + "bitand_4822_4823_4824":{ + "modref":"corebit.and" + }, + "bitand_4824_4826_4827":{ + "modref":"corebit.and" + }, + "const_p0__4829":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p1__4825$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "const_p255__4828":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mux_4827_4828_4829":{ + "genref":"coreir.mux", + "genargs":{"width":["Int",16]} + }, + "sle_4825_cim_stencil_65_4826":{ + "genref":"coreir.sle", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_64_cim_stencil_65_4810":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_66_cim_stencil_65_4811":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_67_cim_stencil_65_4813":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_68_cim_stencil_65_4815":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_69_cim_stencil_65_4817":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_70_cim_stencil_65_4819":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_71_cim_stencil_65_4821":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + }, + "slt_cim_stencil_72_cim_stencil_65_4823":{ + "genref":"coreir.slt", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["slt_cim_stencil_64_cim_stencil_65_4810.out","bitand_4810_4811_4812.in0"], + ["slt_cim_stencil_66_cim_stencil_65_4811.out","bitand_4810_4811_4812.in1"], + ["bitand_4812_4813_4814.in0","bitand_4810_4811_4812.out"], + ["slt_cim_stencil_67_cim_stencil_65_4813.out","bitand_4812_4813_4814.in1"], + ["bitand_4814_4815_4816.in0","bitand_4812_4813_4814.out"], + ["slt_cim_stencil_68_cim_stencil_65_4815.out","bitand_4814_4815_4816.in1"], + ["bitand_4816_4817_4818.in0","bitand_4814_4815_4816.out"], + ["slt_cim_stencil_69_cim_stencil_65_4817.out","bitand_4816_4817_4818.in1"], + ["bitand_4818_4819_4820.in0","bitand_4816_4817_4818.out"], + ["slt_cim_stencil_70_cim_stencil_65_4819.out","bitand_4818_4819_4820.in1"], + ["bitand_4820_4821_4822.in0","bitand_4818_4819_4820.out"], + ["slt_cim_stencil_71_cim_stencil_65_4821.out","bitand_4820_4821_4822.in1"], + ["bitand_4822_4823_4824.in0","bitand_4820_4821_4822.out"], + ["slt_cim_stencil_72_cim_stencil_65_4823.out","bitand_4822_4823_4824.in1"], + ["bitand_4824_4826_4827.in0","bitand_4822_4823_4824.out"], + ["sle_4825_cim_stencil_65_4826.out","bitand_4824_4826_4827.in1"], + ["mux_4827_4828_4829.sel","bitand_4824_4826_4827.out"], + ["mux_4827_4828_4829.in0","const_p0__4829.out"], + ["sle_4825_cim_stencil_65_4826.in0","const_p1__4825$2.out"], + ["mux_4827_4828_4829.in1","const_p255__4828.out"], + ["self.out_hw_output_glb_stencil","mux_4827_4828_4829.out"], + ["slt_cim_stencil_64_cim_stencil_65_4810.in0","self.in0_cim_stencil.0"], + ["sle_4825_cim_stencil_65_4826.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_64_cim_stencil_65_4810.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_66_cim_stencil_65_4811.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_67_cim_stencil_65_4813.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_68_cim_stencil_65_4815.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_69_cim_stencil_65_4817.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_70_cim_stencil_65_4819.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_71_cim_stencil_65_4821.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_72_cim_stencil_65_4823.in1","self.in0_cim_stencil.1"], + ["slt_cim_stencil_66_cim_stencil_65_4811.in0","self.in0_cim_stencil.2"], + ["slt_cim_stencil_67_cim_stencil_65_4813.in0","self.in0_cim_stencil.3"], + ["slt_cim_stencil_68_cim_stencil_65_4815.in0","self.in0_cim_stencil.4"], + ["slt_cim_stencil_69_cim_stencil_65_4817.in0","self.in0_cim_stencil.5"], + ["slt_cim_stencil_70_cim_stencil_65_4819.in0","self.in0_cim_stencil.6"], + ["slt_cim_stencil_71_cim_stencil_65_4821.in0","self.in0_cim_stencil.7"], + ["slt_cim_stencil_72_cim_stencil_65_4823.in0","self.in0_cim_stencil.8"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_3":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_lgxx_stencil":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1033":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__1033.out"] + ] + }, + "hcompute_lgxx_stencil_1":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1039":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__1039.out"] + ] + }, + "hcompute_lgxx_stencil_10":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3275":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__3275.out"] + ] + }, + "hcompute_lgxx_stencil_11":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3282":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__3282.out"] + ] + }, + "hcompute_lgxx_stencil_12":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_9_3304_3305":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_37_3305_3306":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_38_3303_3304":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_39_3302_3303":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_40_3301_3302":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_41_3300_3301":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_42_3299_3300":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_43_3298_3299":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_44_lxx_stencil_45_3298":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_9_3304_3305.in0"], + ["add_lxx_stencil_38_3303_3304.out","add_lgxx_stencil_9_3304_3305.in1"], + ["add_lxx_stencil_37_3305_3306.in1","add_lgxx_stencil_9_3304_3305.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_37_3305_3306.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_37_3305_3306.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_38_3303_3304.in0"], + ["add_lxx_stencil_39_3302_3303.out","add_lxx_stencil_38_3303_3304.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_39_3302_3303.in0"], + ["add_lxx_stencil_40_3301_3302.out","add_lxx_stencil_39_3302_3303.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_40_3301_3302.in0"], + ["add_lxx_stencil_41_3300_3301.out","add_lxx_stencil_40_3301_3302.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_41_3300_3301.in0"], + ["add_lxx_stencil_42_3299_3300.out","add_lxx_stencil_41_3300_3301.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_42_3299_3300.in0"], + ["add_lxx_stencil_43_3298_3299.out","add_lxx_stencil_42_3299_3300.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_43_3298_3299.in0"], + ["add_lxx_stencil_44_lxx_stencil_45_3298.out","add_lxx_stencil_43_3298_3299.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_44_lxx_stencil_45_3298.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_44_lxx_stencil_45_3298.in1"] + ] + }, + "hcompute_lgxx_stencil_13":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_10_3348_3349":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_46_3349_3350":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_47_3347_3348":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_48_3346_3347":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_49_3345_3346":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_50_3344_3345":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_51_3343_3344":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_52_3342_3343":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_53_lxx_stencil_54_3342":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_10_3348_3349.in0"], + ["add_lxx_stencil_47_3347_3348.out","add_lgxx_stencil_10_3348_3349.in1"], + ["add_lxx_stencil_46_3349_3350.in1","add_lgxx_stencil_10_3348_3349.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_46_3349_3350.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_46_3349_3350.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_47_3347_3348.in0"], + ["add_lxx_stencil_48_3346_3347.out","add_lxx_stencil_47_3347_3348.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_48_3346_3347.in0"], + ["add_lxx_stencil_49_3345_3346.out","add_lxx_stencil_48_3346_3347.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_49_3345_3346.in0"], + ["add_lxx_stencil_50_3344_3345.out","add_lxx_stencil_49_3345_3346.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_50_3344_3345.in0"], + ["add_lxx_stencil_51_3343_3344.out","add_lxx_stencil_50_3344_3345.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_51_3343_3344.in0"], + ["add_lxx_stencil_52_3342_3343.out","add_lxx_stencil_51_3343_3344.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_52_3342_3343.in0"], + ["add_lxx_stencil_53_lxx_stencil_54_3342.out","add_lxx_stencil_52_3342_3343.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_53_lxx_stencil_54_3342.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_53_lxx_stencil_54_3342.in1"] + ] + }, + "hcompute_lgxx_stencil_14":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_11_3393_3394":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_55_3394_3395":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_56_3392_3393":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_57_3391_3392":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_58_3390_3391":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_59_3389_3390":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_60_3388_3389":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_61_3387_3388":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_62_lxx_stencil_63_3387":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_11_3393_3394.in0"], + ["add_lxx_stencil_56_3392_3393.out","add_lgxx_stencil_11_3393_3394.in1"], + ["add_lxx_stencil_55_3394_3395.in1","add_lgxx_stencil_11_3393_3394.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_55_3394_3395.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_55_3394_3395.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_56_3392_3393.in0"], + ["add_lxx_stencil_57_3391_3392.out","add_lxx_stencil_56_3392_3393.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_57_3391_3392.in0"], + ["add_lxx_stencil_58_3390_3391.out","add_lxx_stencil_57_3391_3392.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_58_3390_3391.in0"], + ["add_lxx_stencil_59_3389_3390.out","add_lxx_stencil_58_3390_3391.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_59_3389_3390.in0"], + ["add_lxx_stencil_60_3388_3389.out","add_lxx_stencil_59_3389_3390.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_60_3388_3389.in0"], + ["add_lxx_stencil_61_3387_3388.out","add_lxx_stencil_60_3388_3389.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_61_3387_3388.in0"], + ["add_lxx_stencil_62_lxx_stencil_63_3387.out","add_lxx_stencil_61_3387_3388.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_62_lxx_stencil_63_3387.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_62_lxx_stencil_63_3387.in1"] + ] + }, + "hcompute_lgxx_stencil_15":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_12_3438_3439":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_64_3439_3440":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_65_3437_3438":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_66_3436_3437":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_67_3435_3436":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_68_3434_3435":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_69_3433_3434":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_70_3432_3433":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_71_lxx_stencil_72_3432":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_12_3438_3439.in0"], + ["add_lxx_stencil_65_3437_3438.out","add_lgxx_stencil_12_3438_3439.in1"], + ["add_lxx_stencil_64_3439_3440.in1","add_lgxx_stencil_12_3438_3439.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_64_3439_3440.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_64_3439_3440.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_65_3437_3438.in0"], + ["add_lxx_stencil_66_3436_3437.out","add_lxx_stencil_65_3437_3438.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_66_3436_3437.in0"], + ["add_lxx_stencil_67_3435_3436.out","add_lxx_stencil_66_3436_3437.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_67_3435_3436.in0"], + ["add_lxx_stencil_68_3434_3435.out","add_lxx_stencil_67_3435_3436.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_68_3434_3435.in0"], + ["add_lxx_stencil_69_3433_3434.out","add_lxx_stencil_68_3434_3435.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_69_3433_3434.in0"], + ["add_lxx_stencil_70_3432_3433.out","add_lxx_stencil_69_3433_3434.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_70_3432_3433.in0"], + ["add_lxx_stencil_71_lxx_stencil_72_3432.out","add_lxx_stencil_70_3432_3433.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_71_lxx_stencil_72_3432.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_71_lxx_stencil_72_3432.in1"] + ] + }, + "hcompute_lgxx_stencil_2":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1046":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__1046.out"] + ] + }, + "hcompute_lgxx_stencil_3":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1053":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__1053.out"] + ] + }, + "hcompute_lgxx_stencil_4":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_1_1075_1076":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_1_1076_1077":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_2_1074_1075":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_3_1073_1074":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_4_1072_1073":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_5_1071_1072":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_6_1070_1071":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_7_1069_1070":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_8_lxx_stencil_9_1069":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_1_1075_1076.in0"], + ["add_lxx_stencil_2_1074_1075.out","add_lgxx_stencil_1_1075_1076.in1"], + ["add_lxx_stencil_1_1076_1077.in1","add_lgxx_stencil_1_1075_1076.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_1_1076_1077.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_1_1076_1077.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_2_1074_1075.in0"], + ["add_lxx_stencil_3_1073_1074.out","add_lxx_stencil_2_1074_1075.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_3_1073_1074.in0"], + ["add_lxx_stencil_4_1072_1073.out","add_lxx_stencil_3_1073_1074.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_4_1072_1073.in0"], + ["add_lxx_stencil_5_1071_1072.out","add_lxx_stencil_4_1072_1073.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_5_1071_1072.in0"], + ["add_lxx_stencil_6_1070_1071.out","add_lxx_stencil_5_1071_1072.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_6_1070_1071.in0"], + ["add_lxx_stencil_7_1069_1070.out","add_lxx_stencil_6_1070_1071.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_7_1069_1070.in0"], + ["add_lxx_stencil_8_lxx_stencil_9_1069.out","add_lxx_stencil_7_1069_1070.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_8_lxx_stencil_9_1069.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_8_lxx_stencil_9_1069.in1"] + ] + }, + "hcompute_lgxx_stencil_5":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_2_1119_1120":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_10_1120_1121":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_11_1118_1119":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_12_1117_1118":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_13_1116_1117":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_14_1115_1116":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_15_1114_1115":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_16_1113_1114":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_17_lxx_stencil_18_1113":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_2_1119_1120.in0"], + ["add_lxx_stencil_11_1118_1119.out","add_lgxx_stencil_2_1119_1120.in1"], + ["add_lxx_stencil_10_1120_1121.in1","add_lgxx_stencil_2_1119_1120.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_10_1120_1121.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_10_1120_1121.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_11_1118_1119.in0"], + ["add_lxx_stencil_12_1117_1118.out","add_lxx_stencil_11_1118_1119.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_12_1117_1118.in0"], + ["add_lxx_stencil_13_1116_1117.out","add_lxx_stencil_12_1117_1118.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_13_1116_1117.in0"], + ["add_lxx_stencil_14_1115_1116.out","add_lxx_stencil_13_1116_1117.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_14_1115_1116.in0"], + ["add_lxx_stencil_15_1114_1115.out","add_lxx_stencil_14_1115_1116.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_15_1114_1115.in0"], + ["add_lxx_stencil_16_1113_1114.out","add_lxx_stencil_15_1114_1115.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_16_1113_1114.in0"], + ["add_lxx_stencil_17_lxx_stencil_18_1113.out","add_lxx_stencil_16_1113_1114.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_17_lxx_stencil_18_1113.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_17_lxx_stencil_18_1113.in1"] + ] + }, + "hcompute_lgxx_stencil_6":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_3_1164_1165":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_19_1165_1166":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_20_1163_1164":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_21_1162_1163":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_22_1161_1162":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_23_1160_1161":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_24_1159_1160":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_25_1158_1159":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_26_lxx_stencil_27_1158":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_3_1164_1165.in0"], + ["add_lxx_stencil_20_1163_1164.out","add_lgxx_stencil_3_1164_1165.in1"], + ["add_lxx_stencil_19_1165_1166.in1","add_lgxx_stencil_3_1164_1165.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_19_1165_1166.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_19_1165_1166.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_20_1163_1164.in0"], + ["add_lxx_stencil_21_1162_1163.out","add_lxx_stencil_20_1163_1164.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_21_1162_1163.in0"], + ["add_lxx_stencil_22_1161_1162.out","add_lxx_stencil_21_1162_1163.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_22_1161_1162.in0"], + ["add_lxx_stencil_23_1160_1161.out","add_lxx_stencil_22_1161_1162.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_23_1160_1161.in0"], + ["add_lxx_stencil_24_1159_1160.out","add_lxx_stencil_23_1160_1161.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_24_1159_1160.in0"], + ["add_lxx_stencil_25_1158_1159.out","add_lxx_stencil_24_1159_1160.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_25_1158_1159.in0"], + ["add_lxx_stencil_26_lxx_stencil_27_1158.out","add_lxx_stencil_25_1158_1159.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_26_lxx_stencil_27_1158.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_26_lxx_stencil_27_1158.in1"] + ] + }, + "hcompute_lgxx_stencil_7":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]], + ["in0_lgxx_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxx_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxx_stencil_4_1209_1210":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_28_1210_1211":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_29_1208_1209":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_30_1207_1208":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_31_1206_1207":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_32_1205_1206":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_33_1204_1205":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_34_1203_1204":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxx_stencil_35_lxx_stencil_36_1203":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxx_stencil.0","add_lgxx_stencil_4_1209_1210.in0"], + ["add_lxx_stencil_29_1208_1209.out","add_lgxx_stencil_4_1209_1210.in1"], + ["add_lxx_stencil_28_1210_1211.in1","add_lgxx_stencil_4_1209_1210.out"], + ["self.in1_lxx_stencil.0","add_lxx_stencil_28_1210_1211.in0"], + ["self.out_lgxx_stencil","add_lxx_stencil_28_1210_1211.out"], + ["self.in1_lxx_stencil.1","add_lxx_stencil_29_1208_1209.in0"], + ["add_lxx_stencil_30_1207_1208.out","add_lxx_stencil_29_1208_1209.in1"], + ["self.in1_lxx_stencil.2","add_lxx_stencil_30_1207_1208.in0"], + ["add_lxx_stencil_31_1206_1207.out","add_lxx_stencil_30_1207_1208.in1"], + ["self.in1_lxx_stencil.3","add_lxx_stencil_31_1206_1207.in0"], + ["add_lxx_stencil_32_1205_1206.out","add_lxx_stencil_31_1206_1207.in1"], + ["self.in1_lxx_stencil.4","add_lxx_stencil_32_1205_1206.in0"], + ["add_lxx_stencil_33_1204_1205.out","add_lxx_stencil_32_1205_1206.in1"], + ["self.in1_lxx_stencil.5","add_lxx_stencil_33_1204_1205.in0"], + ["add_lxx_stencil_34_1203_1204.out","add_lxx_stencil_33_1204_1205.in1"], + ["self.in1_lxx_stencil.6","add_lxx_stencil_34_1203_1204.in0"], + ["add_lxx_stencil_35_lxx_stencil_36_1203.out","add_lxx_stencil_34_1203_1204.in1"], + ["self.in1_lxx_stencil.7","add_lxx_stencil_35_lxx_stencil_36_1203.in0"], + ["self.in1_lxx_stencil.8","add_lxx_stencil_35_lxx_stencil_36_1203.in1"] + ] + }, + "hcompute_lgxx_stencil_8":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3262":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__3262.out"] + ] + }, + "hcompute_lgxx_stencil_9":{ + "type":["Record",[ + ["out_lgxx_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3268":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxx_stencil","const_p0__3268.out"] + ] + }, + "hcompute_lgxy_stencil":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1637":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__1637.out"] + ] + }, + "hcompute_lgxy_stencil_1":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1643":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__1643.out"] + ] + }, + "hcompute_lgxy_stencil_10":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3879":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__3879.out"] + ] + }, + "hcompute_lgxy_stencil_11":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3886":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__3886.out"] + ] + }, + "hcompute_lgxy_stencil_12":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_9_3908_3909":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_37_3909_3910":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_38_3907_3908":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_39_3906_3907":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_40_3905_3906":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_41_3904_3905":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_42_3903_3904":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_43_3902_3903":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_44_lxy_stencil_45_3902":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_9_3908_3909.in0"], + ["add_lxy_stencil_38_3907_3908.out","add_lgxy_stencil_9_3908_3909.in1"], + ["add_lxy_stencil_37_3909_3910.in1","add_lgxy_stencil_9_3908_3909.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_37_3909_3910.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_37_3909_3910.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_38_3907_3908.in0"], + ["add_lxy_stencil_39_3906_3907.out","add_lxy_stencil_38_3907_3908.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_39_3906_3907.in0"], + ["add_lxy_stencil_40_3905_3906.out","add_lxy_stencil_39_3906_3907.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_40_3905_3906.in0"], + ["add_lxy_stencil_41_3904_3905.out","add_lxy_stencil_40_3905_3906.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_41_3904_3905.in0"], + ["add_lxy_stencil_42_3903_3904.out","add_lxy_stencil_41_3904_3905.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_42_3903_3904.in0"], + ["add_lxy_stencil_43_3902_3903.out","add_lxy_stencil_42_3903_3904.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_43_3902_3903.in0"], + ["add_lxy_stencil_44_lxy_stencil_45_3902.out","add_lxy_stencil_43_3902_3903.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_44_lxy_stencil_45_3902.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_44_lxy_stencil_45_3902.in1"] + ] + }, + "hcompute_lgxy_stencil_13":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_10_3952_3953":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_46_3953_3954":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_47_3951_3952":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_48_3950_3951":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_49_3949_3950":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_50_3948_3949":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_51_3947_3948":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_52_3946_3947":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_53_lxy_stencil_54_3946":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_10_3952_3953.in0"], + ["add_lxy_stencil_47_3951_3952.out","add_lgxy_stencil_10_3952_3953.in1"], + ["add_lxy_stencil_46_3953_3954.in1","add_lgxy_stencil_10_3952_3953.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_46_3953_3954.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_46_3953_3954.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_47_3951_3952.in0"], + ["add_lxy_stencil_48_3950_3951.out","add_lxy_stencil_47_3951_3952.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_48_3950_3951.in0"], + ["add_lxy_stencil_49_3949_3950.out","add_lxy_stencil_48_3950_3951.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_49_3949_3950.in0"], + ["add_lxy_stencil_50_3948_3949.out","add_lxy_stencil_49_3949_3950.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_50_3948_3949.in0"], + ["add_lxy_stencil_51_3947_3948.out","add_lxy_stencil_50_3948_3949.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_51_3947_3948.in0"], + ["add_lxy_stencil_52_3946_3947.out","add_lxy_stencil_51_3947_3948.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_52_3946_3947.in0"], + ["add_lxy_stencil_53_lxy_stencil_54_3946.out","add_lxy_stencil_52_3946_3947.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_53_lxy_stencil_54_3946.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_53_lxy_stencil_54_3946.in1"] + ] + }, + "hcompute_lgxy_stencil_14":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_11_3997_3998":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_55_3998_3999":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_56_3996_3997":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_57_3995_3996":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_58_3994_3995":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_59_3993_3994":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_60_3992_3993":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_61_3991_3992":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_62_lxy_stencil_63_3991":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_11_3997_3998.in0"], + ["add_lxy_stencil_56_3996_3997.out","add_lgxy_stencil_11_3997_3998.in1"], + ["add_lxy_stencil_55_3998_3999.in1","add_lgxy_stencil_11_3997_3998.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_55_3998_3999.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_55_3998_3999.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_56_3996_3997.in0"], + ["add_lxy_stencil_57_3995_3996.out","add_lxy_stencil_56_3996_3997.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_57_3995_3996.in0"], + ["add_lxy_stencil_58_3994_3995.out","add_lxy_stencil_57_3995_3996.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_58_3994_3995.in0"], + ["add_lxy_stencil_59_3993_3994.out","add_lxy_stencil_58_3994_3995.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_59_3993_3994.in0"], + ["add_lxy_stencil_60_3992_3993.out","add_lxy_stencil_59_3993_3994.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_60_3992_3993.in0"], + ["add_lxy_stencil_61_3991_3992.out","add_lxy_stencil_60_3992_3993.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_61_3991_3992.in0"], + ["add_lxy_stencil_62_lxy_stencil_63_3991.out","add_lxy_stencil_61_3991_3992.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_62_lxy_stencil_63_3991.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_62_lxy_stencil_63_3991.in1"] + ] + }, + "hcompute_lgxy_stencil_15":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_12_4042_4043":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_64_4043_4044":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_65_4041_4042":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_66_4040_4041":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_67_4039_4040":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_68_4038_4039":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_69_4037_4038":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_70_4036_4037":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_71_lxy_stencil_72_4036":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_12_4042_4043.in0"], + ["add_lxy_stencil_65_4041_4042.out","add_lgxy_stencil_12_4042_4043.in1"], + ["add_lxy_stencil_64_4043_4044.in1","add_lgxy_stencil_12_4042_4043.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_64_4043_4044.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_64_4043_4044.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_65_4041_4042.in0"], + ["add_lxy_stencil_66_4040_4041.out","add_lxy_stencil_65_4041_4042.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_66_4040_4041.in0"], + ["add_lxy_stencil_67_4039_4040.out","add_lxy_stencil_66_4040_4041.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_67_4039_4040.in0"], + ["add_lxy_stencil_68_4038_4039.out","add_lxy_stencil_67_4039_4040.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_68_4038_4039.in0"], + ["add_lxy_stencil_69_4037_4038.out","add_lxy_stencil_68_4038_4039.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_69_4037_4038.in0"], + ["add_lxy_stencil_70_4036_4037.out","add_lxy_stencil_69_4037_4038.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_70_4036_4037.in0"], + ["add_lxy_stencil_71_lxy_stencil_72_4036.out","add_lxy_stencil_70_4036_4037.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_71_lxy_stencil_72_4036.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_71_lxy_stencil_72_4036.in1"] + ] + }, + "hcompute_lgxy_stencil_2":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1650":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__1650.out"] + ] + }, + "hcompute_lgxy_stencil_3":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1657":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__1657.out"] + ] + }, + "hcompute_lgxy_stencil_4":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_1_1679_1680":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_1_1680_1681":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_2_1678_1679":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_3_1677_1678":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_4_1676_1677":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_5_1675_1676":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_6_1674_1675":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_7_1673_1674":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_8_lxy_stencil_9_1673":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_1_1679_1680.in0"], + ["add_lxy_stencil_2_1678_1679.out","add_lgxy_stencil_1_1679_1680.in1"], + ["add_lxy_stencil_1_1680_1681.in1","add_lgxy_stencil_1_1679_1680.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_1_1680_1681.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_1_1680_1681.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_2_1678_1679.in0"], + ["add_lxy_stencil_3_1677_1678.out","add_lxy_stencil_2_1678_1679.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_3_1677_1678.in0"], + ["add_lxy_stencil_4_1676_1677.out","add_lxy_stencil_3_1677_1678.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_4_1676_1677.in0"], + ["add_lxy_stencil_5_1675_1676.out","add_lxy_stencil_4_1676_1677.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_5_1675_1676.in0"], + ["add_lxy_stencil_6_1674_1675.out","add_lxy_stencil_5_1675_1676.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_6_1674_1675.in0"], + ["add_lxy_stencil_7_1673_1674.out","add_lxy_stencil_6_1674_1675.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_7_1673_1674.in0"], + ["add_lxy_stencil_8_lxy_stencil_9_1673.out","add_lxy_stencil_7_1673_1674.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_8_lxy_stencil_9_1673.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_8_lxy_stencil_9_1673.in1"] + ] + }, + "hcompute_lgxy_stencil_5":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_2_1723_1724":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_10_1724_1725":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_11_1722_1723":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_12_1721_1722":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_13_1720_1721":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_14_1719_1720":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_15_1718_1719":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_16_1717_1718":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_17_lxy_stencil_18_1717":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_2_1723_1724.in0"], + ["add_lxy_stencil_11_1722_1723.out","add_lgxy_stencil_2_1723_1724.in1"], + ["add_lxy_stencil_10_1724_1725.in1","add_lgxy_stencil_2_1723_1724.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_10_1724_1725.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_10_1724_1725.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_11_1722_1723.in0"], + ["add_lxy_stencil_12_1721_1722.out","add_lxy_stencil_11_1722_1723.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_12_1721_1722.in0"], + ["add_lxy_stencil_13_1720_1721.out","add_lxy_stencil_12_1721_1722.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_13_1720_1721.in0"], + ["add_lxy_stencil_14_1719_1720.out","add_lxy_stencil_13_1720_1721.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_14_1719_1720.in0"], + ["add_lxy_stencil_15_1718_1719.out","add_lxy_stencil_14_1719_1720.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_15_1718_1719.in0"], + ["add_lxy_stencil_16_1717_1718.out","add_lxy_stencil_15_1718_1719.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_16_1717_1718.in0"], + ["add_lxy_stencil_17_lxy_stencil_18_1717.out","add_lxy_stencil_16_1717_1718.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_17_lxy_stencil_18_1717.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_17_lxy_stencil_18_1717.in1"] + ] + }, + "hcompute_lgxy_stencil_6":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_3_1768_1769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_19_1769_1770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_20_1767_1768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_21_1766_1767":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_22_1765_1766":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_23_1764_1765":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_24_1763_1764":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_25_1762_1763":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_26_lxy_stencil_27_1762":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_3_1768_1769.in0"], + ["add_lxy_stencil_20_1767_1768.out","add_lgxy_stencil_3_1768_1769.in1"], + ["add_lxy_stencil_19_1769_1770.in1","add_lgxy_stencil_3_1768_1769.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_19_1769_1770.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_19_1769_1770.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_20_1767_1768.in0"], + ["add_lxy_stencil_21_1766_1767.out","add_lxy_stencil_20_1767_1768.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_21_1766_1767.in0"], + ["add_lxy_stencil_22_1765_1766.out","add_lxy_stencil_21_1766_1767.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_22_1765_1766.in0"], + ["add_lxy_stencil_23_1764_1765.out","add_lxy_stencil_22_1765_1766.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_23_1764_1765.in0"], + ["add_lxy_stencil_24_1763_1764.out","add_lxy_stencil_23_1764_1765.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_24_1763_1764.in0"], + ["add_lxy_stencil_25_1762_1763.out","add_lxy_stencil_24_1763_1764.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_25_1762_1763.in0"], + ["add_lxy_stencil_26_lxy_stencil_27_1762.out","add_lxy_stencil_25_1762_1763.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_26_lxy_stencil_27_1762.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_26_lxy_stencil_27_1762.in1"] + ] + }, + "hcompute_lgxy_stencil_7":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]], + ["in0_lgxy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lxy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgxy_stencil_4_1813_1814":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_28_1814_1815":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_29_1812_1813":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_30_1811_1812":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_31_1810_1811":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_32_1809_1810":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_33_1808_1809":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_34_1807_1808":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lxy_stencil_35_lxy_stencil_36_1807":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgxy_stencil.0","add_lgxy_stencil_4_1813_1814.in0"], + ["add_lxy_stencil_29_1812_1813.out","add_lgxy_stencil_4_1813_1814.in1"], + ["add_lxy_stencil_28_1814_1815.in1","add_lgxy_stencil_4_1813_1814.out"], + ["self.in1_lxy_stencil.0","add_lxy_stencil_28_1814_1815.in0"], + ["self.out_lgxy_stencil","add_lxy_stencil_28_1814_1815.out"], + ["self.in1_lxy_stencil.1","add_lxy_stencil_29_1812_1813.in0"], + ["add_lxy_stencil_30_1811_1812.out","add_lxy_stencil_29_1812_1813.in1"], + ["self.in1_lxy_stencil.2","add_lxy_stencil_30_1811_1812.in0"], + ["add_lxy_stencil_31_1810_1811.out","add_lxy_stencil_30_1811_1812.in1"], + ["self.in1_lxy_stencil.3","add_lxy_stencil_31_1810_1811.in0"], + ["add_lxy_stencil_32_1809_1810.out","add_lxy_stencil_31_1810_1811.in1"], + ["self.in1_lxy_stencil.4","add_lxy_stencil_32_1809_1810.in0"], + ["add_lxy_stencil_33_1808_1809.out","add_lxy_stencil_32_1809_1810.in1"], + ["self.in1_lxy_stencil.5","add_lxy_stencil_33_1808_1809.in0"], + ["add_lxy_stencil_34_1807_1808.out","add_lxy_stencil_33_1808_1809.in1"], + ["self.in1_lxy_stencil.6","add_lxy_stencil_34_1807_1808.in0"], + ["add_lxy_stencil_35_lxy_stencil_36_1807.out","add_lxy_stencil_34_1807_1808.in1"], + ["self.in1_lxy_stencil.7","add_lxy_stencil_35_lxy_stencil_36_1807.in0"], + ["self.in1_lxy_stencil.8","add_lxy_stencil_35_lxy_stencil_36_1807.in1"] + ] + }, + "hcompute_lgxy_stencil_8":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3866":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__3866.out"] + ] + }, + "hcompute_lgxy_stencil_9":{ + "type":["Record",[ + ["out_lgxy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__3872":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgxy_stencil","const_p0__3872.out"] + ] + }, + "hcompute_lgyy_stencil":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1949":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__1949.out"] + ] + }, + "hcompute_lgyy_stencil_1":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1955":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__1955.out"] + ] + }, + "hcompute_lgyy_stencil_10":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__4191":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__4191.out"] + ] + }, + "hcompute_lgyy_stencil_11":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__4198":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__4198.out"] + ] + }, + "hcompute_lgyy_stencil_12":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_9_4220_4221":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_37_4221_4222":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_38_4219_4220":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_39_4218_4219":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_40_4217_4218":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_41_4216_4217":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_42_4215_4216":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_43_4214_4215":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_44_lyy_stencil_45_4214":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_9_4220_4221.in0"], + ["add_lyy_stencil_38_4219_4220.out","add_lgyy_stencil_9_4220_4221.in1"], + ["add_lyy_stencil_37_4221_4222.in1","add_lgyy_stencil_9_4220_4221.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_37_4221_4222.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_37_4221_4222.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_38_4219_4220.in0"], + ["add_lyy_stencil_39_4218_4219.out","add_lyy_stencil_38_4219_4220.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_39_4218_4219.in0"], + ["add_lyy_stencil_40_4217_4218.out","add_lyy_stencil_39_4218_4219.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_40_4217_4218.in0"], + ["add_lyy_stencil_41_4216_4217.out","add_lyy_stencil_40_4217_4218.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_41_4216_4217.in0"], + ["add_lyy_stencil_42_4215_4216.out","add_lyy_stencil_41_4216_4217.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_42_4215_4216.in0"], + ["add_lyy_stencil_43_4214_4215.out","add_lyy_stencil_42_4215_4216.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_43_4214_4215.in0"], + ["add_lyy_stencil_44_lyy_stencil_45_4214.out","add_lyy_stencil_43_4214_4215.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_44_lyy_stencil_45_4214.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_44_lyy_stencil_45_4214.in1"] + ] + }, + "hcompute_lgyy_stencil_13":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_10_4264_4265":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_46_4265_4266":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_47_4263_4264":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_48_4262_4263":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_49_4261_4262":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_50_4260_4261":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_51_4259_4260":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_52_4258_4259":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_53_lyy_stencil_54_4258":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_10_4264_4265.in0"], + ["add_lyy_stencil_47_4263_4264.out","add_lgyy_stencil_10_4264_4265.in1"], + ["add_lyy_stencil_46_4265_4266.in1","add_lgyy_stencil_10_4264_4265.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_46_4265_4266.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_46_4265_4266.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_47_4263_4264.in0"], + ["add_lyy_stencil_48_4262_4263.out","add_lyy_stencil_47_4263_4264.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_48_4262_4263.in0"], + ["add_lyy_stencil_49_4261_4262.out","add_lyy_stencil_48_4262_4263.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_49_4261_4262.in0"], + ["add_lyy_stencil_50_4260_4261.out","add_lyy_stencil_49_4261_4262.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_50_4260_4261.in0"], + ["add_lyy_stencil_51_4259_4260.out","add_lyy_stencil_50_4260_4261.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_51_4259_4260.in0"], + ["add_lyy_stencil_52_4258_4259.out","add_lyy_stencil_51_4259_4260.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_52_4258_4259.in0"], + ["add_lyy_stencil_53_lyy_stencil_54_4258.out","add_lyy_stencil_52_4258_4259.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_53_lyy_stencil_54_4258.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_53_lyy_stencil_54_4258.in1"] + ] + }, + "hcompute_lgyy_stencil_14":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_11_4309_4310":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_55_4310_4311":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_56_4308_4309":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_57_4307_4308":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_58_4306_4307":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_59_4305_4306":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_60_4304_4305":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_61_4303_4304":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_62_lyy_stencil_63_4303":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_11_4309_4310.in0"], + ["add_lyy_stencil_56_4308_4309.out","add_lgyy_stencil_11_4309_4310.in1"], + ["add_lyy_stencil_55_4310_4311.in1","add_lgyy_stencil_11_4309_4310.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_55_4310_4311.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_55_4310_4311.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_56_4308_4309.in0"], + ["add_lyy_stencil_57_4307_4308.out","add_lyy_stencil_56_4308_4309.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_57_4307_4308.in0"], + ["add_lyy_stencil_58_4306_4307.out","add_lyy_stencil_57_4307_4308.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_58_4306_4307.in0"], + ["add_lyy_stencil_59_4305_4306.out","add_lyy_stencil_58_4306_4307.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_59_4305_4306.in0"], + ["add_lyy_stencil_60_4304_4305.out","add_lyy_stencil_59_4305_4306.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_60_4304_4305.in0"], + ["add_lyy_stencil_61_4303_4304.out","add_lyy_stencil_60_4304_4305.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_61_4303_4304.in0"], + ["add_lyy_stencil_62_lyy_stencil_63_4303.out","add_lyy_stencil_61_4303_4304.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_62_lyy_stencil_63_4303.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_62_lyy_stencil_63_4303.in1"] + ] + }, + "hcompute_lgyy_stencil_15":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_12_4354_4355":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_64_4355_4356":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_65_4353_4354":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_66_4352_4353":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_67_4351_4352":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_68_4350_4351":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_69_4349_4350":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_70_4348_4349":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_71_lyy_stencil_72_4348":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_12_4354_4355.in0"], + ["add_lyy_stencil_65_4353_4354.out","add_lgyy_stencil_12_4354_4355.in1"], + ["add_lyy_stencil_64_4355_4356.in1","add_lgyy_stencil_12_4354_4355.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_64_4355_4356.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_64_4355_4356.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_65_4353_4354.in0"], + ["add_lyy_stencil_66_4352_4353.out","add_lyy_stencil_65_4353_4354.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_66_4352_4353.in0"], + ["add_lyy_stencil_67_4351_4352.out","add_lyy_stencil_66_4352_4353.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_67_4351_4352.in0"], + ["add_lyy_stencil_68_4350_4351.out","add_lyy_stencil_67_4351_4352.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_68_4350_4351.in0"], + ["add_lyy_stencil_69_4349_4350.out","add_lyy_stencil_68_4350_4351.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_69_4349_4350.in0"], + ["add_lyy_stencil_70_4348_4349.out","add_lyy_stencil_69_4349_4350.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_70_4348_4349.in0"], + ["add_lyy_stencil_71_lyy_stencil_72_4348.out","add_lyy_stencil_70_4348_4349.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_71_lyy_stencil_72_4348.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_71_lyy_stencil_72_4348.in1"] + ] + }, + "hcompute_lgyy_stencil_2":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1962":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__1962.out"] + ] + }, + "hcompute_lgyy_stencil_3":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__1969":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__1969.out"] + ] + }, + "hcompute_lgyy_stencil_4":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_1_1991_1992":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_1_1992_1993":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_2_1990_1991":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_3_1989_1990":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_4_1988_1989":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_5_1987_1988":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_6_1986_1987":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_7_1985_1986":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_8_lyy_stencil_9_1985":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_1_1991_1992.in0"], + ["add_lyy_stencil_2_1990_1991.out","add_lgyy_stencil_1_1991_1992.in1"], + ["add_lyy_stencil_1_1992_1993.in1","add_lgyy_stencil_1_1991_1992.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_1_1992_1993.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_1_1992_1993.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_2_1990_1991.in0"], + ["add_lyy_stencil_3_1989_1990.out","add_lyy_stencil_2_1990_1991.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_3_1989_1990.in0"], + ["add_lyy_stencil_4_1988_1989.out","add_lyy_stencil_3_1989_1990.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_4_1988_1989.in0"], + ["add_lyy_stencil_5_1987_1988.out","add_lyy_stencil_4_1988_1989.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_5_1987_1988.in0"], + ["add_lyy_stencil_6_1986_1987.out","add_lyy_stencil_5_1987_1988.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_6_1986_1987.in0"], + ["add_lyy_stencil_7_1985_1986.out","add_lyy_stencil_6_1986_1987.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_7_1985_1986.in0"], + ["add_lyy_stencil_8_lyy_stencil_9_1985.out","add_lyy_stencil_7_1985_1986.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_8_lyy_stencil_9_1985.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_8_lyy_stencil_9_1985.in1"] + ] + }, + "hcompute_lgyy_stencil_5":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_2_2035_2036":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_10_2036_2037":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_11_2034_2035":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_12_2033_2034":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_13_2032_2033":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_14_2031_2032":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_15_2030_2031":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_16_2029_2030":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_17_lyy_stencil_18_2029":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_2_2035_2036.in0"], + ["add_lyy_stencil_11_2034_2035.out","add_lgyy_stencil_2_2035_2036.in1"], + ["add_lyy_stencil_10_2036_2037.in1","add_lgyy_stencil_2_2035_2036.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_10_2036_2037.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_10_2036_2037.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_11_2034_2035.in0"], + ["add_lyy_stencil_12_2033_2034.out","add_lyy_stencil_11_2034_2035.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_12_2033_2034.in0"], + ["add_lyy_stencil_13_2032_2033.out","add_lyy_stencil_12_2033_2034.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_13_2032_2033.in0"], + ["add_lyy_stencil_14_2031_2032.out","add_lyy_stencil_13_2032_2033.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_14_2031_2032.in0"], + ["add_lyy_stencil_15_2030_2031.out","add_lyy_stencil_14_2031_2032.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_15_2030_2031.in0"], + ["add_lyy_stencil_16_2029_2030.out","add_lyy_stencil_15_2030_2031.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_16_2029_2030.in0"], + ["add_lyy_stencil_17_lyy_stencil_18_2029.out","add_lyy_stencil_16_2029_2030.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_17_lyy_stencil_18_2029.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_17_lyy_stencil_18_2029.in1"] + ] + }, + "hcompute_lgyy_stencil_6":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_3_2080_2081":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_19_2081_2082":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_20_2079_2080":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_21_2078_2079":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_22_2077_2078":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_23_2076_2077":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_24_2075_2076":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_25_2074_2075":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_26_lyy_stencil_27_2074":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_3_2080_2081.in0"], + ["add_lyy_stencil_20_2079_2080.out","add_lgyy_stencil_3_2080_2081.in1"], + ["add_lyy_stencil_19_2081_2082.in1","add_lgyy_stencil_3_2080_2081.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_19_2081_2082.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_19_2081_2082.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_20_2079_2080.in0"], + ["add_lyy_stencil_21_2078_2079.out","add_lyy_stencil_20_2079_2080.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_21_2078_2079.in0"], + ["add_lyy_stencil_22_2077_2078.out","add_lyy_stencil_21_2078_2079.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_22_2077_2078.in0"], + ["add_lyy_stencil_23_2076_2077.out","add_lyy_stencil_22_2077_2078.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_23_2076_2077.in0"], + ["add_lyy_stencil_24_2075_2076.out","add_lyy_stencil_23_2076_2077.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_24_2075_2076.in0"], + ["add_lyy_stencil_25_2074_2075.out","add_lyy_stencil_24_2075_2076.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_25_2074_2075.in0"], + ["add_lyy_stencil_26_lyy_stencil_27_2074.out","add_lyy_stencil_25_2074_2075.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_26_lyy_stencil_27_2074.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_26_lyy_stencil_27_2074.in1"] + ] + }, + "hcompute_lgyy_stencil_7":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]], + ["in0_lgyy_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_lyy_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_lgyy_stencil_4_2125_2126":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_28_2126_2127":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_29_2124_2125":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_30_2123_2124":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_31_2122_2123":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_32_2121_2122":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_33_2120_2121":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_34_2119_2120":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_lyy_stencil_35_lyy_stencil_36_2119":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_lgyy_stencil.0","add_lgyy_stencil_4_2125_2126.in0"], + ["add_lyy_stencil_29_2124_2125.out","add_lgyy_stencil_4_2125_2126.in1"], + ["add_lyy_stencil_28_2126_2127.in1","add_lgyy_stencil_4_2125_2126.out"], + ["self.in1_lyy_stencil.0","add_lyy_stencil_28_2126_2127.in0"], + ["self.out_lgyy_stencil","add_lyy_stencil_28_2126_2127.out"], + ["self.in1_lyy_stencil.1","add_lyy_stencil_29_2124_2125.in0"], + ["add_lyy_stencil_30_2123_2124.out","add_lyy_stencil_29_2124_2125.in1"], + ["self.in1_lyy_stencil.2","add_lyy_stencil_30_2123_2124.in0"], + ["add_lyy_stencil_31_2122_2123.out","add_lyy_stencil_30_2123_2124.in1"], + ["self.in1_lyy_stencil.3","add_lyy_stencil_31_2122_2123.in0"], + ["add_lyy_stencil_32_2121_2122.out","add_lyy_stencil_31_2122_2123.in1"], + ["self.in1_lyy_stencil.4","add_lyy_stencil_32_2121_2122.in0"], + ["add_lyy_stencil_33_2120_2121.out","add_lyy_stencil_32_2121_2122.in1"], + ["self.in1_lyy_stencil.5","add_lyy_stencil_33_2120_2121.in0"], + ["add_lyy_stencil_34_2119_2120.out","add_lyy_stencil_33_2120_2121.in1"], + ["self.in1_lyy_stencil.6","add_lyy_stencil_34_2119_2120.in0"], + ["add_lyy_stencil_35_lyy_stencil_36_2119.out","add_lyy_stencil_34_2119_2120.in1"], + ["self.in1_lyy_stencil.7","add_lyy_stencil_35_lyy_stencil_36_2119.in0"], + ["self.in1_lyy_stencil.8","add_lyy_stencil_35_lyy_stencil_36_2119.in1"] + ] + }, + "hcompute_lgyy_stencil_8":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__4178":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__4178.out"] + ] + }, + "hcompute_lgyy_stencil_9":{ + "type":["Record",[ + ["out_lgyy_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__4184":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_lgyy_stencil","const_p0__4184.out"] + ] + }, + "hcompute_lxx_stencil":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_939_940_941":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__937":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__935":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__940":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_938_938_939":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_936_937_938":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_5_935_936":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_938_938_939.out","ashr_939_940_941.in0"], + ["const_p6__940.out","ashr_939_940_941.in1"], + ["self.out_lxx_stencil","ashr_939_940_941.out"], + ["smax_936_937_938.in1","const_n180__937.out"], + ["smin_grad_x_unclamp_stencil_5_935_936.in1","const_p180__935.out"], + ["smax_936_937_938.out","mul_938_938_939.in0"], + ["smax_936_937_938.out","mul_938_938_939.in1"], + ["smin_grad_x_unclamp_stencil_5_935_936.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_5_935_936.out","smax_936_937_938.in0"] + ] + }, + "hcompute_lxx_stencil_1":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_964_965_966":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__962":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__960":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__965":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_963_963_964":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_961_962_963":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_6_960_961":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_963_963_964.out","ashr_964_965_966.in0"], + ["const_p6__965.out","ashr_964_965_966.in1"], + ["self.out_lxx_stencil","ashr_964_965_966.out"], + ["smax_961_962_963.in1","const_n180__962.out"], + ["smin_grad_x_unclamp_stencil_6_960_961.in1","const_p180__960.out"], + ["smax_961_962_963.out","mul_963_963_964.in0"], + ["smax_961_962_963.out","mul_963_963_964.in1"], + ["smin_grad_x_unclamp_stencil_6_960_961.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_6_960_961.out","smax_961_962_963.in0"] + ] + }, + "hcompute_lxx_stencil_2":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_990_991_992":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__988":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__986":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__991":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_989_989_990":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_987_988_989":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_7_986_987":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_989_989_990.out","ashr_990_991_992.in0"], + ["const_p6__991.out","ashr_990_991_992.in1"], + ["self.out_lxx_stencil","ashr_990_991_992.out"], + ["smax_987_988_989.in1","const_n180__988.out"], + ["smin_grad_x_unclamp_stencil_7_986_987.in1","const_p180__986.out"], + ["smax_987_988_989.out","mul_989_989_990.in0"], + ["smax_987_988_989.out","mul_989_989_990.in1"], + ["smin_grad_x_unclamp_stencil_7_986_987.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_7_986_987.out","smax_987_988_989.in0"] + ] + }, + "hcompute_lxx_stencil_3":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1016_1017_1018":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1014$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1012":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1017":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1015_1015_1016":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1013_1014_1015":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_8_1012_1013":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1015_1015_1016.out","ashr_1016_1017_1018.in0"], + ["const_p6__1017.out","ashr_1016_1017_1018.in1"], + ["self.out_lxx_stencil","ashr_1016_1017_1018.out"], + ["smax_1013_1014_1015.in1","const_n180__1014$1.out"], + ["smin_grad_x_unclamp_stencil_8_1012_1013.in1","const_p180__1012.out"], + ["smax_1013_1014_1015.out","mul_1015_1015_1016.in0"], + ["smax_1013_1014_1015.out","mul_1015_1015_1016.in1"], + ["smin_grad_x_unclamp_stencil_8_1012_1013.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_8_1012_1013.out","smax_1013_1014_1015.in0"] + ] + }, + "hcompute_lxx_stencil_4":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3168_3169_3170":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3166":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3164":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3169$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3167_3167_3168":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3165_3166_3167":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_17_3164_3165":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3167_3167_3168.out","ashr_3168_3169_3170.in0"], + ["const_p6__3169$1.out","ashr_3168_3169_3170.in1"], + ["self.out_lxx_stencil","ashr_3168_3169_3170.out"], + ["smax_3165_3166_3167.in1","const_n180__3166.out"], + ["smin_grad_x_unclamp_stencil_17_3164_3165.in1","const_p180__3164.out"], + ["smax_3165_3166_3167.out","mul_3167_3167_3168.in0"], + ["smax_3165_3166_3167.out","mul_3167_3167_3168.in1"], + ["smin_grad_x_unclamp_stencil_17_3164_3165.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_17_3164_3165.out","smax_3165_3166_3167.in0"] + ] + }, + "hcompute_lxx_stencil_5":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3193_3194_3195":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3191":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3189":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3194":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3192_3192_3193":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3190_3191_3192":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_18_3189_3190":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3192_3192_3193.out","ashr_3193_3194_3195.in0"], + ["const_p6__3194.out","ashr_3193_3194_3195.in1"], + ["self.out_lxx_stencil","ashr_3193_3194_3195.out"], + ["smax_3190_3191_3192.in1","const_n180__3191.out"], + ["smin_grad_x_unclamp_stencil_18_3189_3190.in1","const_p180__3189.out"], + ["smax_3190_3191_3192.out","mul_3192_3192_3193.in0"], + ["smax_3190_3191_3192.out","mul_3192_3192_3193.in1"], + ["smin_grad_x_unclamp_stencil_18_3189_3190.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_18_3189_3190.out","smax_3190_3191_3192.in0"] + ] + }, + "hcompute_lxx_stencil_6":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3219_3220_3221":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3217":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3215":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3220":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3218_3218_3219":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3216_3217_3218":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_19_3215_3216":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3218_3218_3219.out","ashr_3219_3220_3221.in0"], + ["const_p6__3220.out","ashr_3219_3220_3221.in1"], + ["self.out_lxx_stencil","ashr_3219_3220_3221.out"], + ["smax_3216_3217_3218.in1","const_n180__3217.out"], + ["smin_grad_x_unclamp_stencil_19_3215_3216.in1","const_p180__3215.out"], + ["smax_3216_3217_3218.out","mul_3218_3218_3219.in0"], + ["smax_3216_3217_3218.out","mul_3218_3218_3219.in1"], + ["smin_grad_x_unclamp_stencil_19_3215_3216.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_19_3215_3216.out","smax_3216_3217_3218.in0"] + ] + }, + "hcompute_lxx_stencil_7":{ + "type":["Record",[ + ["out_lxx_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3245_3246_3247":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3243":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3241":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3246":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3244_3244_3245":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3242_3243_3244":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_20_3241_3242":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3244_3244_3245.out","ashr_3245_3246_3247.in0"], + ["const_p6__3246.out","ashr_3245_3246_3247.in1"], + ["self.out_lxx_stencil","ashr_3245_3246_3247.out"], + ["smax_3242_3243_3244.in1","const_n180__3243.out"], + ["smin_grad_x_unclamp_stencil_20_3241_3242.in1","const_p180__3241.out"], + ["smax_3242_3243_3244.out","mul_3244_3244_3245.in0"], + ["smax_3242_3243_3244.out","mul_3244_3244_3245.in1"], + ["smin_grad_x_unclamp_stencil_20_3241_3242.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_20_3241_3242.out","smax_3242_3243_3244.in0"] + ] + }, + "hcompute_lxy_stencil":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1519_1520_1521":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1515":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__1515$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1513":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__1513$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1520":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1516_1518_1519":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1514_1515_1516":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_1517_1515_1518":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_9_1513_1514":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_5_1513_1517":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1516_1518_1519.out","ashr_1519_1520_1521.in0"], + ["const_p6__1520.out","ashr_1519_1520_1521.in1"], + ["self.out_lxy_stencil","ashr_1519_1520_1521.out"], + ["smax_1517_1515_1518.in1","const_n180__1515$1.out"], + ["smax_1514_1515_1516.in1","const_n180__1515.out"], + ["smin_grad_y_unclamp_stencil_5_1513_1517.in1","const_p180__1513$1.out"], + ["smin_grad_x_unclamp_stencil_9_1513_1514.in1","const_p180__1513.out"], + ["smax_1514_1515_1516.out","mul_1516_1518_1519.in0"], + ["smax_1517_1515_1518.out","mul_1516_1518_1519.in1"], + ["smin_grad_x_unclamp_stencil_9_1513_1514.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_5_1513_1517.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_9_1513_1514.out","smax_1514_1515_1516.in0"], + ["smin_grad_y_unclamp_stencil_5_1513_1517.out","smax_1517_1515_1518.in0"] + ] + }, + "hcompute_lxy_stencil_1":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1551_1552_1553":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1547":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__1547$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1545":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__1545$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1552":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1548_1550_1551":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1546_1547_1548":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_1549_1547_1550":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_10_1545_1546":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_6_1545_1549":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1548_1550_1551.out","ashr_1551_1552_1553.in0"], + ["const_p6__1552.out","ashr_1551_1552_1553.in1"], + ["self.out_lxy_stencil","ashr_1551_1552_1553.out"], + ["smax_1549_1547_1550.in1","const_n180__1547$1.out"], + ["smax_1546_1547_1548.in1","const_n180__1547.out"], + ["smin_grad_y_unclamp_stencil_6_1545_1549.in1","const_p180__1545$1.out"], + ["smin_grad_x_unclamp_stencil_10_1545_1546.in1","const_p180__1545.out"], + ["smax_1546_1547_1548.out","mul_1548_1550_1551.in0"], + ["smax_1549_1547_1550.out","mul_1548_1550_1551.in1"], + ["smin_grad_x_unclamp_stencil_10_1545_1546.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_6_1545_1549.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_10_1545_1546.out","smax_1546_1547_1548.in0"], + ["smin_grad_y_unclamp_stencil_6_1545_1549.out","smax_1549_1547_1550.in0"] + ] + }, + "hcompute_lxy_stencil_2":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1584_1585_1586":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1580":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__1580$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1578":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__1578$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1585":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1581_1583_1584":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1579_1580_1581":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_1582_1580_1583":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_11_1578_1579":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_7_1578_1582":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1581_1583_1584.out","ashr_1584_1585_1586.in0"], + ["const_p6__1585.out","ashr_1584_1585_1586.in1"], + ["self.out_lxy_stencil","ashr_1584_1585_1586.out"], + ["smax_1582_1580_1583.in1","const_n180__1580$1.out"], + ["smax_1579_1580_1581.in1","const_n180__1580.out"], + ["smin_grad_y_unclamp_stencil_7_1578_1582.in1","const_p180__1578$1.out"], + ["smin_grad_x_unclamp_stencil_11_1578_1579.in1","const_p180__1578.out"], + ["smax_1579_1580_1581.out","mul_1581_1583_1584.in0"], + ["smax_1582_1580_1583.out","mul_1581_1583_1584.in1"], + ["smin_grad_x_unclamp_stencil_11_1578_1579.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_7_1578_1582.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_11_1578_1579.out","smax_1579_1580_1581.in0"], + ["smin_grad_y_unclamp_stencil_7_1578_1582.out","smax_1582_1580_1583.in0"] + ] + }, + "hcompute_lxy_stencil_3":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1617_1618_1619":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1613":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__1613$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1611":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__1611$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1618":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1614_1616_1617":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1612_1613_1614":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_1615_1613_1616":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_12_1611_1612":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_8_1611_1615":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1614_1616_1617.out","ashr_1617_1618_1619.in0"], + ["const_p6__1618.out","ashr_1617_1618_1619.in1"], + ["self.out_lxy_stencil","ashr_1617_1618_1619.out"], + ["smax_1615_1613_1616.in1","const_n180__1613$1.out"], + ["smax_1612_1613_1614.in1","const_n180__1613.out"], + ["smin_grad_y_unclamp_stencil_8_1611_1615.in1","const_p180__1611$1.out"], + ["smin_grad_x_unclamp_stencil_12_1611_1612.in1","const_p180__1611.out"], + ["smax_1612_1613_1614.out","mul_1614_1616_1617.in0"], + ["smax_1615_1613_1616.out","mul_1614_1616_1617.in1"], + ["smin_grad_x_unclamp_stencil_12_1611_1612.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_8_1611_1615.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_12_1611_1612.out","smax_1612_1613_1614.in0"], + ["smin_grad_y_unclamp_stencil_8_1611_1615.out","smax_1615_1613_1616.in0"] + ] + }, + "hcompute_lxy_stencil_4":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3748_3749_3750":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3744":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__3744$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3742":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__3742$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3749":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3745_3747_3748":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3743_3744_3745":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_3746_3744_3747":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_21_3742_3743":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_17_3742_3746":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3745_3747_3748.out","ashr_3748_3749_3750.in0"], + ["const_p6__3749.out","ashr_3748_3749_3750.in1"], + ["self.out_lxy_stencil","ashr_3748_3749_3750.out"], + ["smax_3746_3744_3747.in1","const_n180__3744$1.out"], + ["smax_3743_3744_3745.in1","const_n180__3744.out"], + ["smin_grad_y_unclamp_stencil_17_3742_3746.in1","const_p180__3742$1.out"], + ["smin_grad_x_unclamp_stencil_21_3742_3743.in1","const_p180__3742.out"], + ["smax_3743_3744_3745.out","mul_3745_3747_3748.in0"], + ["smax_3746_3744_3747.out","mul_3745_3747_3748.in1"], + ["smin_grad_x_unclamp_stencil_21_3742_3743.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_17_3742_3746.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_21_3742_3743.out","smax_3743_3744_3745.in0"], + ["smin_grad_y_unclamp_stencil_17_3742_3746.out","smax_3746_3744_3747.in0"] + ] + }, + "hcompute_lxy_stencil_5":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3780_3781_3782":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3776":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__3776$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3774":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__3774$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3781":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3777_3779_3780":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3775_3776_3777":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_3778_3776_3779":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_22_3774_3775":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_18_3774_3778":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3777_3779_3780.out","ashr_3780_3781_3782.in0"], + ["const_p6__3781.out","ashr_3780_3781_3782.in1"], + ["self.out_lxy_stencil","ashr_3780_3781_3782.out"], + ["smax_3778_3776_3779.in1","const_n180__3776$1.out"], + ["smax_3775_3776_3777.in1","const_n180__3776.out"], + ["smin_grad_y_unclamp_stencil_18_3774_3778.in1","const_p180__3774$1.out"], + ["smin_grad_x_unclamp_stencil_22_3774_3775.in1","const_p180__3774.out"], + ["smax_3775_3776_3777.out","mul_3777_3779_3780.in0"], + ["smax_3778_3776_3779.out","mul_3777_3779_3780.in1"], + ["smin_grad_x_unclamp_stencil_22_3774_3775.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_18_3774_3778.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_22_3774_3775.out","smax_3775_3776_3777.in0"], + ["smin_grad_y_unclamp_stencil_18_3774_3778.out","smax_3778_3776_3779.in0"] + ] + }, + "hcompute_lxy_stencil_6":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3813_3814_3815":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3809":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__3809$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3807":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__3807$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3814":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3810_3812_3813":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3808_3809_3810":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_3811_3809_3812":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_23_3807_3808":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_19_3807_3811":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3810_3812_3813.out","ashr_3813_3814_3815.in0"], + ["const_p6__3814.out","ashr_3813_3814_3815.in1"], + ["self.out_lxy_stencil","ashr_3813_3814_3815.out"], + ["smax_3811_3809_3812.in1","const_n180__3809$1.out"], + ["smax_3808_3809_3810.in1","const_n180__3809.out"], + ["smin_grad_y_unclamp_stencil_19_3807_3811.in1","const_p180__3807$1.out"], + ["smin_grad_x_unclamp_stencil_23_3807_3808.in1","const_p180__3807.out"], + ["smax_3808_3809_3810.out","mul_3810_3812_3813.in0"], + ["smax_3811_3809_3812.out","mul_3810_3812_3813.in1"], + ["smin_grad_x_unclamp_stencil_23_3807_3808.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_19_3807_3811.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_23_3807_3808.out","smax_3808_3809_3810.in0"], + ["smin_grad_y_unclamp_stencil_19_3807_3811.out","smax_3811_3809_3812.in0"] + ] + }, + "hcompute_lxy_stencil_7":{ + "type":["Record",[ + ["out_lxy_stencil",["Array",16,"Bit"]], + ["in0_grad_x_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_3846_3847_3848":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__3842":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_n180__3842$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__3840":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p180__3840$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__3847":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_3843_3845_3846":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_3841_3842_3843":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smax_3844_3842_3845":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_x_unclamp_stencil_24_3840_3841":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_20_3840_3844":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_3843_3845_3846.out","ashr_3846_3847_3848.in0"], + ["const_p6__3847.out","ashr_3846_3847_3848.in1"], + ["self.out_lxy_stencil","ashr_3846_3847_3848.out"], + ["smax_3844_3842_3845.in1","const_n180__3842$1.out"], + ["smax_3841_3842_3843.in1","const_n180__3842.out"], + ["smin_grad_y_unclamp_stencil_20_3840_3844.in1","const_p180__3840$1.out"], + ["smin_grad_x_unclamp_stencil_24_3840_3841.in1","const_p180__3840.out"], + ["smax_3841_3842_3843.out","mul_3843_3845_3846.in0"], + ["smax_3844_3842_3845.out","mul_3843_3845_3846.in1"], + ["smin_grad_x_unclamp_stencil_24_3840_3841.in0","self.in0_grad_x_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_20_3840_3844.in0","self.in1_grad_y_unclamp_stencil.0"], + ["smin_grad_x_unclamp_stencil_24_3840_3841.out","smax_3841_3842_3843.in0"], + ["smin_grad_y_unclamp_stencil_20_3840_3844.out","smax_3844_3842_3845.in0"] + ] + }, + "hcompute_lyy_stencil":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1855_1856_1857":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1853":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1851":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1856":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1854_1854_1855":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1852_1853_1854":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_9_1851_1852":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1854_1854_1855.out","ashr_1855_1856_1857.in0"], + ["const_p6__1856.out","ashr_1855_1856_1857.in1"], + ["self.out_lyy_stencil","ashr_1855_1856_1857.out"], + ["smax_1852_1853_1854.in1","const_n180__1853.out"], + ["smin_grad_y_unclamp_stencil_9_1851_1852.in1","const_p180__1851.out"], + ["smax_1852_1853_1854.out","mul_1854_1854_1855.in0"], + ["smax_1852_1853_1854.out","mul_1854_1854_1855.in1"], + ["smin_grad_y_unclamp_stencil_9_1851_1852.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_9_1851_1852.out","smax_1852_1853_1854.in0"] + ] + }, + "hcompute_lyy_stencil_1":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1880_1881_1882":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1878":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1876":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1881":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1879_1879_1880":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1877_1878_1879":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_10_1876_1877":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1879_1879_1880.out","ashr_1880_1881_1882.in0"], + ["const_p6__1881.out","ashr_1880_1881_1882.in1"], + ["self.out_lyy_stencil","ashr_1880_1881_1882.out"], + ["smax_1877_1878_1879.in1","const_n180__1878.out"], + ["smin_grad_y_unclamp_stencil_10_1876_1877.in1","const_p180__1876.out"], + ["smax_1877_1878_1879.out","mul_1879_1879_1880.in0"], + ["smax_1877_1878_1879.out","mul_1879_1879_1880.in1"], + ["smin_grad_y_unclamp_stencil_10_1876_1877.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_10_1876_1877.out","smax_1877_1878_1879.in0"] + ] + }, + "hcompute_lyy_stencil_2":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1906_1907_1908":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1904":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1902":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1907":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1905_1905_1906":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1903_1904_1905":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_11_1902_1903":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1905_1905_1906.out","ashr_1906_1907_1908.in0"], + ["const_p6__1907.out","ashr_1906_1907_1908.in1"], + ["self.out_lyy_stencil","ashr_1906_1907_1908.out"], + ["smax_1903_1904_1905.in1","const_n180__1904.out"], + ["smin_grad_y_unclamp_stencil_11_1902_1903.in1","const_p180__1902.out"], + ["smax_1903_1904_1905.out","mul_1905_1905_1906.in0"], + ["smax_1903_1904_1905.out","mul_1905_1905_1906.in1"], + ["smin_grad_y_unclamp_stencil_11_1902_1903.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_11_1902_1903.out","smax_1903_1904_1905.in0"] + ] + }, + "hcompute_lyy_stencil_3":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_1932_1933_1934":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__1930":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__1928":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__1933":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_1931_1931_1932":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1929_1930_1931":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_12_1928_1929":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_1931_1931_1932.out","ashr_1932_1933_1934.in0"], + ["const_p6__1933.out","ashr_1932_1933_1934.in1"], + ["self.out_lyy_stencil","ashr_1932_1933_1934.out"], + ["smax_1929_1930_1931.in1","const_n180__1930.out"], + ["smin_grad_y_unclamp_stencil_12_1928_1929.in1","const_p180__1928.out"], + ["smax_1929_1930_1931.out","mul_1931_1931_1932.in0"], + ["smax_1929_1930_1931.out","mul_1931_1931_1932.in1"], + ["smin_grad_y_unclamp_stencil_12_1928_1929.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_12_1928_1929.out","smax_1929_1930_1931.in0"] + ] + }, + "hcompute_lyy_stencil_4":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_4084_4085_4086":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__4082":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__4080":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__4085":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4083_4083_4084":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_4081_4082_4083":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_21_4080_4081":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_4083_4083_4084.out","ashr_4084_4085_4086.in0"], + ["const_p6__4085.out","ashr_4084_4085_4086.in1"], + ["self.out_lyy_stencil","ashr_4084_4085_4086.out"], + ["smax_4081_4082_4083.in1","const_n180__4082.out"], + ["smin_grad_y_unclamp_stencil_21_4080_4081.in1","const_p180__4080.out"], + ["smax_4081_4082_4083.out","mul_4083_4083_4084.in0"], + ["smax_4081_4082_4083.out","mul_4083_4083_4084.in1"], + ["smin_grad_y_unclamp_stencil_21_4080_4081.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_21_4080_4081.out","smax_4081_4082_4083.in0"] + ] + }, + "hcompute_lyy_stencil_5":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_4109_4110_4111":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__4107":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__4105":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__4110":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4108_4108_4109":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_4106_4107_4108":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_22_4105_4106":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_4108_4108_4109.out","ashr_4109_4110_4111.in0"], + ["const_p6__4110.out","ashr_4109_4110_4111.in1"], + ["self.out_lyy_stencil","ashr_4109_4110_4111.out"], + ["smax_4106_4107_4108.in1","const_n180__4107.out"], + ["smin_grad_y_unclamp_stencil_22_4105_4106.in1","const_p180__4105.out"], + ["smax_4106_4107_4108.out","mul_4108_4108_4109.in0"], + ["smax_4106_4107_4108.out","mul_4108_4108_4109.in1"], + ["smin_grad_y_unclamp_stencil_22_4105_4106.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_22_4105_4106.out","smax_4106_4107_4108.in0"] + ] + }, + "hcompute_lyy_stencil_6":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_4135_4136_4137":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__4133":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__4131":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__4136":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4134_4134_4135":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_4132_4133_4134":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_23_4131_4132":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_4134_4134_4135.out","ashr_4135_4136_4137.in0"], + ["const_p6__4136.out","ashr_4135_4136_4137.in1"], + ["self.out_lyy_stencil","ashr_4135_4136_4137.out"], + ["smax_4132_4133_4134.in1","const_n180__4133.out"], + ["smin_grad_y_unclamp_stencil_23_4131_4132.in1","const_p180__4131.out"], + ["smax_4132_4133_4134.out","mul_4134_4134_4135.in0"], + ["smax_4132_4133_4134.out","mul_4134_4134_4135.in1"], + ["smin_grad_y_unclamp_stencil_23_4131_4132.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_23_4131_4132.out","smax_4132_4133_4134.in0"] + ] + }, + "hcompute_lyy_stencil_7":{ + "type":["Record",[ + ["out_lyy_stencil",["Array",16,"Bit"]], + ["in0_grad_y_unclamp_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "ashr_4161_4162_4163":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_n180__4159":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hff4c"]} + }, + "const_p180__4157":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00b4"]} + }, + "const_p6__4162":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "mul_4160_4160_4161":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_4158_4159_4160":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_grad_y_unclamp_stencil_24_4157_4158":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_4160_4160_4161.out","ashr_4161_4162_4163.in0"], + ["const_p6__4162.out","ashr_4161_4162_4163.in1"], + ["self.out_lyy_stencil","ashr_4161_4162_4163.out"], + ["smax_4158_4159_4160.in1","const_n180__4159.out"], + ["smin_grad_y_unclamp_stencil_24_4157_4158.in1","const_p180__4157.out"], + ["smax_4158_4159_4160.out","mul_4160_4160_4161.in0"], + ["smax_4158_4159_4160.out","mul_4160_4160_4161.in1"], + ["smin_grad_y_unclamp_stencil_24_4157_4158.in0","self.in0_grad_y_unclamp_stencil.0"], + ["smin_grad_y_unclamp_stencil_24_4157_4158.out","smax_4158_4159_4160.in0"] + ] + } + } + } +} +} diff --git a/coreir_compute/laplacian_pyramid_docker_compute.json b/coreir_compute/laplacian_pyramid_docker_compute.json new file mode 100644 index 000000000..b2dab4284 --- /dev/null +++ b/coreir_compute/laplacian_pyramid_docker_compute.json @@ -0,0 +1,898 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_unnormalized_stencil":{ + "type":["Record",[ + ["out_blur_unnormalized_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__408":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_unnormalized_stencil","const_p0__408.out"] + ] + }, + "hcompute_blur_unnormalized_stencil_1":{ + "type":["Record",[ + ["out_blur_unnormalized_stencil",["Array",16,"Bit"]], + ["in0_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",9,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_434_452_453":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_436_450_451":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_437_449_450":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_438_448_449":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_440_443_444":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_445_447_448":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_unnormalized_stencil_1_451_452":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_hw_input_global_wrapper_stencil_6_442_443":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_hw_input_global_wrapper_stencil_7_441_442":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p158__446":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h009e"]} + }, + "const_p21__435":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p21__435$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p3__433":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__433$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__433$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p7__439":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "const_p7__439$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mul_444_433_445":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_1_433_434":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_2_435_436":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_3_433_437":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_4_435_438":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_5_439_440":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_8_439_441":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_9_446_447":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_hw_input_global_wrapper_stencil_1_433_434.out","add_434_452_453.in0"], + ["add_blur_unnormalized_stencil_1_451_452.out","add_434_452_453.in1"], + ["self.out_blur_unnormalized_stencil","add_434_452_453.out"], + ["mul_hw_input_global_wrapper_stencil_2_435_436.out","add_436_450_451.in0"], + ["add_437_449_450.out","add_436_450_451.in1"], + ["add_blur_unnormalized_stencil_1_451_452.in1","add_436_450_451.out"], + ["mul_hw_input_global_wrapper_stencil_3_433_437.out","add_437_449_450.in0"], + ["add_438_448_449.out","add_437_449_450.in1"], + ["mul_hw_input_global_wrapper_stencil_4_435_438.out","add_438_448_449.in0"], + ["add_445_447_448.out","add_438_448_449.in1"], + ["mul_hw_input_global_wrapper_stencil_5_439_440.out","add_440_443_444.in0"], + ["add_hw_input_global_wrapper_stencil_6_442_443.out","add_440_443_444.in1"], + ["mul_444_433_445.in0","add_440_443_444.out"], + ["mul_444_433_445.out","add_445_447_448.in0"], + ["mul_hw_input_global_wrapper_stencil_9_446_447.out","add_445_447_448.in1"], + ["self.in0_blur_unnormalized_stencil.0","add_blur_unnormalized_stencil_1_451_452.in0"], + ["self.in1_hw_input_global_wrapper_stencil.5","add_hw_input_global_wrapper_stencil_6_442_443.in0"], + ["add_hw_input_global_wrapper_stencil_7_441_442.out","add_hw_input_global_wrapper_stencil_6_442_443.in1"], + ["self.in1_hw_input_global_wrapper_stencil.6","add_hw_input_global_wrapper_stencil_7_441_442.in0"], + ["mul_hw_input_global_wrapper_stencil_8_439_441.out","add_hw_input_global_wrapper_stencil_7_441_442.in1"], + ["mul_hw_input_global_wrapper_stencil_9_446_447.in1","const_p158__446.out"], + ["mul_hw_input_global_wrapper_stencil_4_435_438.in1","const_p21__435$1.out"], + ["mul_hw_input_global_wrapper_stencil_2_435_436.in1","const_p21__435.out"], + ["mul_hw_input_global_wrapper_stencil_3_433_437.in1","const_p3__433$1.out"], + ["mul_444_433_445.in1","const_p3__433$2.out"], + ["mul_hw_input_global_wrapper_stencil_1_433_434.in1","const_p3__433.out"], + ["mul_hw_input_global_wrapper_stencil_8_439_441.in1","const_p7__439$1.out"], + ["mul_hw_input_global_wrapper_stencil_5_439_440.in1","const_p7__439.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_1_433_434.in0"], + ["self.in1_hw_input_global_wrapper_stencil.1","mul_hw_input_global_wrapper_stencil_2_435_436.in0"], + ["self.in1_hw_input_global_wrapper_stencil.2","mul_hw_input_global_wrapper_stencil_3_433_437.in0"], + ["self.in1_hw_input_global_wrapper_stencil.3","mul_hw_input_global_wrapper_stencil_4_435_438.in0"], + ["self.in1_hw_input_global_wrapper_stencil.4","mul_hw_input_global_wrapper_stencil_5_439_440.in0"], + ["self.in1_hw_input_global_wrapper_stencil.7","mul_hw_input_global_wrapper_stencil_8_439_441.in0"], + ["self.in1_hw_input_global_wrapper_stencil.8","mul_hw_input_global_wrapper_stencil_9_446_447.in0"] + ] + }, + "hcompute_f0_up_stencil":{ + "type":["Record",[ + ["out_f0_up_stencil",["Array",16,"Bit"]], + ["in0_h0_0_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_l0_up_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_l0_up_stencil_1_h0_0_stencil_1_833":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in1_l0_up_stencil.0","add_l0_up_stencil_1_h0_0_stencil_1_833.in0"], + ["self.in0_h0_0_stencil.0","add_l0_up_stencil_1_h0_0_stencil_1_833.in1"], + ["self.out_f0_up_stencil","add_l0_up_stencil_1_h0_0_stencil_1_833.out"] + ] + }, + "hcompute_f1_0_stencil":{ + "type":["Record",[ + ["out_f1_0_stencil",["Array",16,"Bit"]], + ["in0_l0_0_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_f1_0_stencil","self.in0_l0_0_stencil.0"] + ] + }, + "hcompute_f1_blur_unnormalized_stencil":{ + "type":["Record",[ + ["out_f1_blur_unnormalized_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__517":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_f1_blur_unnormalized_stencil","const_p0__517.out"] + ] + }, + "hcompute_f1_blur_unnormalized_stencil_1":{ + "type":["Record",[ + ["out_f1_blur_unnormalized_stencil",["Array",16,"Bit"]], + ["in0_f1_0_stencil",["Array",9,["Array",16,"BitIn"]]], + ["in1_f1_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_543_561_562":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_545_559_560":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_546_558_559":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_547_557_558":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_549_552_553":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_554_556_557":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f1_0_stencil_6_551_552":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f1_0_stencil_7_550_551":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f1_blur_unnormalized_stencil_1_560_561":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p158__555":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h009e"]} + }, + "const_p21__544":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p21__544$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p3__542":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__542$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__542$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p7__548":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "const_p7__548$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mul_553_542_554":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_0_stencil_1_542_543":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_0_stencil_2_544_545":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_0_stencil_3_542_546":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_0_stencil_4_544_547":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_0_stencil_5_548_549":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_0_stencil_8_548_550":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_0_stencil_9_555_556":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_f1_0_stencil_1_542_543.out","add_543_561_562.in0"], + ["add_f1_blur_unnormalized_stencil_1_560_561.out","add_543_561_562.in1"], + ["self.out_f1_blur_unnormalized_stencil","add_543_561_562.out"], + ["mul_f1_0_stencil_2_544_545.out","add_545_559_560.in0"], + ["add_546_558_559.out","add_545_559_560.in1"], + ["add_f1_blur_unnormalized_stencil_1_560_561.in1","add_545_559_560.out"], + ["mul_f1_0_stencil_3_542_546.out","add_546_558_559.in0"], + ["add_547_557_558.out","add_546_558_559.in1"], + ["mul_f1_0_stencil_4_544_547.out","add_547_557_558.in0"], + ["add_554_556_557.out","add_547_557_558.in1"], + ["mul_f1_0_stencil_5_548_549.out","add_549_552_553.in0"], + ["add_f1_0_stencil_6_551_552.out","add_549_552_553.in1"], + ["mul_553_542_554.in0","add_549_552_553.out"], + ["mul_553_542_554.out","add_554_556_557.in0"], + ["mul_f1_0_stencil_9_555_556.out","add_554_556_557.in1"], + ["self.in0_f1_0_stencil.5","add_f1_0_stencil_6_551_552.in0"], + ["add_f1_0_stencil_7_550_551.out","add_f1_0_stencil_6_551_552.in1"], + ["self.in0_f1_0_stencil.6","add_f1_0_stencil_7_550_551.in0"], + ["mul_f1_0_stencil_8_548_550.out","add_f1_0_stencil_7_550_551.in1"], + ["self.in1_f1_blur_unnormalized_stencil.0","add_f1_blur_unnormalized_stencil_1_560_561.in0"], + ["mul_f1_0_stencil_9_555_556.in1","const_p158__555.out"], + ["mul_f1_0_stencil_4_544_547.in1","const_p21__544$1.out"], + ["mul_f1_0_stencil_2_544_545.in1","const_p21__544.out"], + ["mul_f1_0_stencil_3_542_546.in1","const_p3__542$1.out"], + ["mul_553_542_554.in1","const_p3__542$2.out"], + ["mul_f1_0_stencil_1_542_543.in1","const_p3__542.out"], + ["mul_f1_0_stencil_8_548_550.in1","const_p7__548$1.out"], + ["mul_f1_0_stencil_5_548_549.in1","const_p7__548.out"], + ["self.in0_f1_0_stencil.0","mul_f1_0_stencil_1_542_543.in0"], + ["self.in0_f1_0_stencil.1","mul_f1_0_stencil_2_544_545.in0"], + ["self.in0_f1_0_stencil.2","mul_f1_0_stencil_3_542_546.in0"], + ["self.in0_f1_0_stencil.3","mul_f1_0_stencil_4_544_547.in0"], + ["self.in0_f1_0_stencil.4","mul_f1_0_stencil_5_548_549.in0"], + ["self.in0_f1_0_stencil.7","mul_f1_0_stencil_8_548_550.in0"], + ["self.in0_f1_0_stencil.8","mul_f1_0_stencil_9_555_556.in0"] + ] + }, + "hcompute_f1_temp_blur_unnormalized_stencil":{ + "type":["Record",[ + ["out_f1_temp_blur_unnormalized_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__742":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_f1_temp_blur_unnormalized_stencil","const_p0__742.out"] + ] + }, + "hcompute_f1_temp_blur_unnormalized_stencil_1":{ + "type":["Record",[ + ["out_f1_temp_blur_unnormalized_stencil",["Array",16,"Bit"]], + ["in0_f1_temp_stencil",["Array",9,["Array",16,"BitIn"]]], + ["in1_f1_temp_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_768_786_787":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_770_784_785":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_771_783_784":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_772_782_783":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_774_777_778":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_779_781_782":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f1_temp_blur_unnormalized_stencil_1_785_786":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f1_temp_stencil_6_776_777":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f1_temp_stencil_7_775_776":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p158__780":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h009e"]} + }, + "const_p21__769":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p21__769$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p3__767":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__767$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__767$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p7__773":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "const_p7__773$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mul_778_767_779":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_temp_stencil_1_767_768":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_temp_stencil_2_769_770":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_temp_stencil_3_767_771":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_temp_stencil_4_769_772":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_temp_stencil_5_773_774":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_temp_stencil_8_773_775":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f1_temp_stencil_9_780_781":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_f1_temp_stencil_1_767_768.out","add_768_786_787.in0"], + ["add_f1_temp_blur_unnormalized_stencil_1_785_786.out","add_768_786_787.in1"], + ["self.out_f1_temp_blur_unnormalized_stencil","add_768_786_787.out"], + ["mul_f1_temp_stencil_2_769_770.out","add_770_784_785.in0"], + ["add_771_783_784.out","add_770_784_785.in1"], + ["add_f1_temp_blur_unnormalized_stencil_1_785_786.in1","add_770_784_785.out"], + ["mul_f1_temp_stencil_3_767_771.out","add_771_783_784.in0"], + ["add_772_782_783.out","add_771_783_784.in1"], + ["mul_f1_temp_stencil_4_769_772.out","add_772_782_783.in0"], + ["add_779_781_782.out","add_772_782_783.in1"], + ["mul_f1_temp_stencil_5_773_774.out","add_774_777_778.in0"], + ["add_f1_temp_stencil_6_776_777.out","add_774_777_778.in1"], + ["mul_778_767_779.in0","add_774_777_778.out"], + ["mul_778_767_779.out","add_779_781_782.in0"], + ["mul_f1_temp_stencil_9_780_781.out","add_779_781_782.in1"], + ["self.in1_f1_temp_blur_unnormalized_stencil.0","add_f1_temp_blur_unnormalized_stencil_1_785_786.in0"], + ["self.in0_f1_temp_stencil.5","add_f1_temp_stencil_6_776_777.in0"], + ["add_f1_temp_stencil_7_775_776.out","add_f1_temp_stencil_6_776_777.in1"], + ["self.in0_f1_temp_stencil.6","add_f1_temp_stencil_7_775_776.in0"], + ["mul_f1_temp_stencil_8_773_775.out","add_f1_temp_stencil_7_775_776.in1"], + ["mul_f1_temp_stencil_9_780_781.in1","const_p158__780.out"], + ["mul_f1_temp_stencil_4_769_772.in1","const_p21__769$1.out"], + ["mul_f1_temp_stencil_2_769_770.in1","const_p21__769.out"], + ["mul_f1_temp_stencil_3_767_771.in1","const_p3__767$1.out"], + ["mul_778_767_779.in1","const_p3__767$2.out"], + ["mul_f1_temp_stencil_1_767_768.in1","const_p3__767.out"], + ["mul_f1_temp_stencil_8_773_775.in1","const_p7__773$1.out"], + ["mul_f1_temp_stencil_5_773_774.in1","const_p7__773.out"], + ["self.in0_f1_temp_stencil.0","mul_f1_temp_stencil_1_767_768.in0"], + ["self.in0_f1_temp_stencil.1","mul_f1_temp_stencil_2_769_770.in0"], + ["self.in0_f1_temp_stencil.2","mul_f1_temp_stencil_3_767_771.in0"], + ["self.in0_f1_temp_stencil.3","mul_f1_temp_stencil_4_769_772.in0"], + ["self.in0_f1_temp_stencil.4","mul_f1_temp_stencil_5_773_774.in0"], + ["self.in0_f1_temp_stencil.7","mul_f1_temp_stencil_8_773_775.in0"], + ["self.in0_f1_temp_stencil.8","mul_f1_temp_stencil_9_780_781.in0"] + ] + }, + "hcompute_f1_temp_stencil":{ + "type":["Record",[ + ["out_f1_temp_stencil",["Array",16,"Bit"]], + ["in0_f1_up_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_f1_temp_stencil","self.in0_f1_up_stencil.0"] + ] + }, + "hcompute_f1_up_stencil_1":{ + "type":["Record",[ + ["out_f1_up_stencil",["Array",16,"Bit"]], + ["in0_h1_0_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_l1_up_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_l1_up_stencil_1_h1_0_stencil_1_728":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in1_l1_up_stencil.0","add_l1_up_stencil_1_h1_0_stencil_1_728.in0"], + ["self.in0_h1_0_stencil.0","add_l1_up_stencil_1_h1_0_stencil_1_728.in1"], + ["self.out_f1_up_stencil","add_l1_up_stencil_1_h1_0_stencil_1_728.out"] + ] + }, + "hcompute_f2_0_stencil":{ + "type":["Record",[ + ["out_f2_0_stencil",["Array",16,"Bit"]], + ["in0_l1_0_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_f2_0_stencil","self.in0_l1_0_stencil.0"] + ] + }, + "hcompute_f2_temp_blur_unnormalized_stencil":{ + "type":["Record",[ + ["out_f2_temp_blur_unnormalized_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__635":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_f2_temp_blur_unnormalized_stencil","const_p0__635.out"] + ] + }, + "hcompute_f2_temp_blur_unnormalized_stencil_1":{ + "type":["Record",[ + ["out_f2_temp_blur_unnormalized_stencil",["Array",16,"Bit"]], + ["in0_f2_temp_stencil",["Array",9,["Array",16,"BitIn"]]], + ["in1_f2_temp_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_661_679_680":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_663_677_678":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_664_676_677":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_665_675_676":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_667_670_671":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_672_674_675":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f2_temp_blur_unnormalized_stencil_1_678_679":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f2_temp_stencil_6_669_670":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_f2_temp_stencil_7_668_669":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p158__673":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h009e"]} + }, + "const_p21__662":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p21__662$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0015"]} + }, + "const_p3__660":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__660$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__660$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p7__666":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "const_p7__666$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mul_671_660_672":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f2_temp_stencil_1_660_661":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f2_temp_stencil_2_662_663":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f2_temp_stencil_3_660_664":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f2_temp_stencil_4_662_665":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f2_temp_stencil_5_666_667":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f2_temp_stencil_8_666_668":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_f2_temp_stencil_9_673_674":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_f2_temp_stencil_1_660_661.out","add_661_679_680.in0"], + ["add_f2_temp_blur_unnormalized_stencil_1_678_679.out","add_661_679_680.in1"], + ["self.out_f2_temp_blur_unnormalized_stencil","add_661_679_680.out"], + ["mul_f2_temp_stencil_2_662_663.out","add_663_677_678.in0"], + ["add_664_676_677.out","add_663_677_678.in1"], + ["add_f2_temp_blur_unnormalized_stencil_1_678_679.in1","add_663_677_678.out"], + ["mul_f2_temp_stencil_3_660_664.out","add_664_676_677.in0"], + ["add_665_675_676.out","add_664_676_677.in1"], + ["mul_f2_temp_stencil_4_662_665.out","add_665_675_676.in0"], + ["add_672_674_675.out","add_665_675_676.in1"], + ["mul_f2_temp_stencil_5_666_667.out","add_667_670_671.in0"], + ["add_f2_temp_stencil_6_669_670.out","add_667_670_671.in1"], + ["mul_671_660_672.in0","add_667_670_671.out"], + ["mul_671_660_672.out","add_672_674_675.in0"], + ["mul_f2_temp_stencil_9_673_674.out","add_672_674_675.in1"], + ["self.in1_f2_temp_blur_unnormalized_stencil.0","add_f2_temp_blur_unnormalized_stencil_1_678_679.in0"], + ["self.in0_f2_temp_stencil.5","add_f2_temp_stencil_6_669_670.in0"], + ["add_f2_temp_stencil_7_668_669.out","add_f2_temp_stencil_6_669_670.in1"], + ["self.in0_f2_temp_stencil.6","add_f2_temp_stencil_7_668_669.in0"], + ["mul_f2_temp_stencil_8_666_668.out","add_f2_temp_stencil_7_668_669.in1"], + ["mul_f2_temp_stencil_9_673_674.in1","const_p158__673.out"], + ["mul_f2_temp_stencil_4_662_665.in1","const_p21__662$1.out"], + ["mul_f2_temp_stencil_2_662_663.in1","const_p21__662.out"], + ["mul_f2_temp_stencil_3_660_664.in1","const_p3__660$1.out"], + ["mul_671_660_672.in1","const_p3__660$2.out"], + ["mul_f2_temp_stencil_1_660_661.in1","const_p3__660.out"], + ["mul_f2_temp_stencil_8_666_668.in1","const_p7__666$1.out"], + ["mul_f2_temp_stencil_5_666_667.in1","const_p7__666.out"], + ["self.in0_f2_temp_stencil.0","mul_f2_temp_stencil_1_660_661.in0"], + ["self.in0_f2_temp_stencil.1","mul_f2_temp_stencil_2_662_663.in0"], + ["self.in0_f2_temp_stencil.2","mul_f2_temp_stencil_3_660_664.in0"], + ["self.in0_f2_temp_stencil.3","mul_f2_temp_stencil_4_662_665.in0"], + ["self.in0_f2_temp_stencil.4","mul_f2_temp_stencil_5_666_667.in0"], + ["self.in0_f2_temp_stencil.7","mul_f2_temp_stencil_8_666_668.in0"], + ["self.in0_f2_temp_stencil.8","mul_f2_temp_stencil_9_673_674.in0"] + ] + }, + "hcompute_f2_temp_stencil":{ + "type":["Record",[ + ["out_f2_temp_stencil",["Array",16,"Bit"]], + ["in0_f2_0_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_f2_temp_stencil","self.in0_f2_0_stencil.0"] + ] + }, + "hcompute_h0_0_stencil":{ + "type":["Record",[ + ["out_h0_0_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_l0_0_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "sub_hw_input_global_wrapper_stencil_10_l0_0_stencil_1_501":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_hw_input_global_wrapper_stencil_10_l0_0_stencil_1_501.in0","self.in0_hw_input_global_wrapper_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_10_l0_0_stencil_1_501.in1","self.in1_l0_0_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_10_l0_0_stencil_1_501.out","self.out_h0_0_stencil"] + ] + }, + "hcompute_h1_0_stencil":{ + "type":["Record",[ + ["out_h1_0_stencil",["Array",16,"Bit"]], + ["in0_f1_0_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_l1_0_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "sub_f1_0_stencil_10_l1_0_stencil_1_610":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["sub_f1_0_stencil_10_l1_0_stencil_1_610.in0","self.in0_f1_0_stencil.0"], + ["sub_f1_0_stencil_10_l1_0_stencil_1_610.in1","self.in1_l1_0_stencil.0"], + ["sub_f1_0_stencil_10_l1_0_stencil_1_610.out","self.out_h1_0_stencil"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_f0_up_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_f0_up_stencil.0"] + ] + }, + "hcompute_l0_0_stencil":{ + "type":["Record",[ + ["out_l0_0_stencil",["Array",16,"Bit"]], + ["in0_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p8__493":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_blur_unnormalized_stencil_2_493_494":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["lshr_blur_unnormalized_stencil_2_493_494.in1","const_p8__493.out"], + ["self.in0_blur_unnormalized_stencil.0","lshr_blur_unnormalized_stencil_2_493_494.in0"], + ["self.out_l0_0_stencil","lshr_blur_unnormalized_stencil_2_493_494.out"] + ] + }, + "hcompute_l0_up_stencil":{ + "type":["Record",[ + ["out_l0_up_stencil",["Array",16,"Bit"]], + ["in0_f1_temp_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p8__827":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_f1_temp_blur_unnormalized_stencil_2_827_828":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["lshr_f1_temp_blur_unnormalized_stencil_2_827_828.in1","const_p8__827.out"], + ["self.in0_f1_temp_blur_unnormalized_stencil.0","lshr_f1_temp_blur_unnormalized_stencil_2_827_828.in0"], + ["self.out_l0_up_stencil","lshr_f1_temp_blur_unnormalized_stencil_2_827_828.out"] + ] + }, + "hcompute_l1_0_stencil":{ + "type":["Record",[ + ["out_l1_0_stencil",["Array",16,"Bit"]], + ["in0_f1_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p8__602":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_f1_blur_unnormalized_stencil_2_602_603":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["lshr_f1_blur_unnormalized_stencil_2_602_603.in1","const_p8__602.out"], + ["self.in0_f1_blur_unnormalized_stencil.0","lshr_f1_blur_unnormalized_stencil_2_602_603.in0"], + ["self.out_l1_0_stencil","lshr_f1_blur_unnormalized_stencil_2_602_603.out"] + ] + }, + "hcompute_l1_up_stencil":{ + "type":["Record",[ + ["out_l1_up_stencil",["Array",16,"Bit"]], + ["in0_f2_temp_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p8__720":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_f2_temp_blur_unnormalized_stencil_2_720_721":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["lshr_f2_temp_blur_unnormalized_stencil_2_720_721.in1","const_p8__720.out"], + ["self.in0_f2_temp_blur_unnormalized_stencil.0","lshr_f2_temp_blur_unnormalized_stencil_2_720_721.in0"], + ["self.out_l1_up_stencil","lshr_f2_temp_blur_unnormalized_stencil_2_720_721.out"] + ] + } + } + } +} +} diff --git a/coreir_compute/matmul_unroll2_compute.json b/coreir_compute/matmul_unroll2_compute.json new file mode 100644 index 000000000..4e6d7a07b --- /dev/null +++ b/coreir_compute/matmul_unroll2_compute.json @@ -0,0 +1,139 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_kernel_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_kernel_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_kernel_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_kernel_global_wrapper_stencil","self.in0_hw_kernel_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_mul_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_mul_stencil.0"] + ] + }, + "hcompute_mul_stencil":{ + "type":["Record",[ + ["out_mul_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__391":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_mul_stencil","const_p0__391.out"] + ] + }, + "hcompute_mul_stencil_1":{ + "type":["Record",[ + ["out_mul_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__395":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_mul_stencil","const_p0__395.out"] + ] + }, + "hcompute_mul_stencil_2":{ + "type":["Record",[ + ["out_mul_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_hw_kernel_global_wrapper_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_mul_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_403_405_406":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_mul_stencil_1_404_405":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_1_hw_kernel_global_wrapper_stencil_1_403":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_2_hw_kernel_global_wrapper_stencil_2_404":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_hw_input_global_wrapper_stencil_1_hw_kernel_global_wrapper_stencil_1_403.out","add_403_405_406.in0"], + ["add_mul_stencil_1_404_405.out","add_403_405_406.in1"], + ["self.out_mul_stencil","add_403_405_406.out"], + ["self.in2_mul_stencil.0","add_mul_stencil_1_404_405.in0"], + ["mul_hw_input_global_wrapper_stencil_2_hw_kernel_global_wrapper_stencil_2_404.out","add_mul_stencil_1_404_405.in1"], + ["self.in0_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_1_hw_kernel_global_wrapper_stencil_1_403.in0"], + ["self.in1_hw_kernel_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_1_hw_kernel_global_wrapper_stencil_1_403.in1"], + ["self.in0_hw_input_global_wrapper_stencil.1","mul_hw_input_global_wrapper_stencil_2_hw_kernel_global_wrapper_stencil_2_404.in0"], + ["self.in1_hw_kernel_global_wrapper_stencil.1","mul_hw_input_global_wrapper_stencil_2_hw_kernel_global_wrapper_stencil_2_404.in1"] + ] + }, + "hcompute_mul_stencil_3":{ + "type":["Record",[ + ["out_mul_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in1_hw_kernel_global_wrapper_stencil",["Array",2,["Array",16,"BitIn"]]], + ["in2_mul_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_423_425_426":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_mul_stencil_2_424_425":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_3_hw_kernel_global_wrapper_stencil_3_423":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_stencil_4_hw_kernel_global_wrapper_stencil_4_424":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_hw_input_global_wrapper_stencil_3_hw_kernel_global_wrapper_stencil_3_423.out","add_423_425_426.in0"], + ["add_mul_stencil_2_424_425.out","add_423_425_426.in1"], + ["self.out_mul_stencil","add_423_425_426.out"], + ["self.in2_mul_stencil.0","add_mul_stencil_2_424_425.in0"], + ["mul_hw_input_global_wrapper_stencil_4_hw_kernel_global_wrapper_stencil_4_424.out","add_mul_stencil_2_424_425.in1"], + ["self.in0_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_3_hw_kernel_global_wrapper_stencil_3_423.in0"], + ["self.in1_hw_kernel_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_3_hw_kernel_global_wrapper_stencil_3_423.in1"], + ["self.in0_hw_input_global_wrapper_stencil.1","mul_hw_input_global_wrapper_stencil_4_hw_kernel_global_wrapper_stencil_4_424.in0"], + ["self.in1_hw_kernel_global_wrapper_stencil.1","mul_hw_input_global_wrapper_stencil_4_hw_kernel_global_wrapper_stencil_4_424.in1"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_compute.json b/coreir_compute/nlmeans_compute.json new file mode 100644 index 000000000..8b9b74066 --- /dev/null +++ b/coreir_compute/nlmeans_compute.json @@ -0,0 +1,641 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__985":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_stencil","fconst0__985.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_2_1001_1002":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_3_1000_1001":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_4_999_1000":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_5_998_999":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_6_997_998":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_7_996_997":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.a"], + ["self.in1_blur_d_y_stencil.6","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.b"], + ["dwfp_add_blur_d_y_stencil_7_996_997.b","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.z"], + ["self.in1_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_2_1001_1002.a"], + ["dwfp_add_blur_d_y_stencil_3_1000_1001.z","dwfp_add_blur_d_y_stencil_2_1001_1002.b"], + ["self.out_blur_d_stencil","dwfp_add_blur_d_y_stencil_2_1001_1002.z"], + ["self.in1_blur_d_y_stencil.1","dwfp_add_blur_d_y_stencil_3_1000_1001.a"], + ["dwfp_add_blur_d_y_stencil_4_999_1000.z","dwfp_add_blur_d_y_stencil_3_1000_1001.b"], + ["self.in1_blur_d_y_stencil.2","dwfp_add_blur_d_y_stencil_4_999_1000.a"], + ["dwfp_add_blur_d_y_stencil_5_998_999.z","dwfp_add_blur_d_y_stencil_4_999_1000.b"], + ["self.in1_blur_d_y_stencil.3","dwfp_add_blur_d_y_stencil_5_998_999.a"], + ["dwfp_add_blur_d_y_stencil_6_997_998.z","dwfp_add_blur_d_y_stencil_5_998_999.b"], + ["self.in1_blur_d_y_stencil.4","dwfp_add_blur_d_y_stencil_6_997_998.a"], + ["dwfp_add_blur_d_y_stencil_7_996_997.z","dwfp_add_blur_d_y_stencil_6_997_998.b"], + ["self.in1_blur_d_y_stencil.5","dwfp_add_blur_d_y_stencil_7_996_997.a"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__941":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","fconst0__941.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_y_stencil_1_d_stencil_8_953":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_2_958_959":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_3_957_958":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_4_956_957":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_5_955_956":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_6_954_955":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_7_953_954":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.a"], + ["self.in1_d_stencil.6","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.b"], + ["dwfp_add_d_stencil_7_953_954.b","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.z"], + ["self.in1_d_stencil.0","dwfp_add_d_stencil_2_958_959.a"], + ["dwfp_add_d_stencil_3_957_958.z","dwfp_add_d_stencil_2_958_959.b"], + ["self.out_blur_d_y_stencil","dwfp_add_d_stencil_2_958_959.z"], + ["self.in1_d_stencil.1","dwfp_add_d_stencil_3_957_958.a"], + ["dwfp_add_d_stencil_4_956_957.z","dwfp_add_d_stencil_3_957_958.b"], + ["self.in1_d_stencil.2","dwfp_add_d_stencil_4_956_957.a"], + ["dwfp_add_d_stencil_5_955_956.z","dwfp_add_d_stencil_4_956_957.b"], + ["self.in1_d_stencil.3","dwfp_add_d_stencil_5_955_956.a"], + ["dwfp_add_d_stencil_6_954_955.z","dwfp_add_d_stencil_5_955_956.b"], + ["self.in1_d_stencil.4","dwfp_add_d_stencil_6_954_955.a"], + ["dwfp_add_d_stencil_7_953_954.z","dwfp_add_d_stencil_6_954_955.b"], + ["self.in1_d_stencil.5","dwfp_add_d_stencil_7_953_954.a"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__890":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_d_stencil","fconst0__890.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_906_912_913":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_908_911_912":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_1_910_911":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_905_905_906":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_907_907_908":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_909_909_910":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_905_905_906.z","dwfp_add_906_912_913.a"], + ["dwfp_add_908_911_912.z","dwfp_add_906_912_913.b"], + ["self.out_d_stencil","dwfp_add_906_912_913.z"], + ["dwfp_mul_907_907_908.z","dwfp_add_908_911_912.a"], + ["dwfp_add_d_stencil_1_910_911.z","dwfp_add_908_911_912.b"], + ["self.in0_d_stencil.0","dwfp_add_d_stencil_1_910_911.a"], + ["dwfp_mul_909_909_910.z","dwfp_add_d_stencil_1_910_911.b"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.a"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.b"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.a"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.b"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.a"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.b"], + ["self.in1_hw_input_global_wrapper_stencil.0","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in0"], + ["self.in1_hw_input_global_wrapper_stencil.1","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in1"], + ["self.in1_hw_input_global_wrapper_stencil.2","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in0"], + ["self.in1_hw_input_global_wrapper_stencil.3","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in1"], + ["self.in1_hw_input_global_wrapper_stencil.4","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in0"], + ["self.in1_hw_input_global_wrapper_stencil.5","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1137_1138_1139":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1136":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1134":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1138":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1135_1136_1137":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1133_1134_1135":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1135_1136_1137.out","dwfp_mul_1137_1138_1139.a"], + ["fconst255__1138.out","dwfp_mul_1137_1138_1139.b"], + ["self.out_hw_output_stencil","dwfp_mul_1137_1138_1139.z"], + ["fmax_1135_1136_1137.in1","fconst0__1136.out"], + ["fmin_1133_1134_1135.in1","fconst1__1134.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133.in1"], + ["fmin_1133_1134_1135.in0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133.out"], + ["fmin_1133_1134_1135.out","fmax_1135_1136_1137.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1160_1161_1162":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1159":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1157":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1161":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1158_1159_1160":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1156_1157_1158":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1158_1159_1160.out","dwfp_mul_1160_1161_1162.a"], + ["fconst255__1161.out","dwfp_mul_1160_1161_1162.b"], + ["self.out_hw_output_stencil","dwfp_mul_1160_1161_1162.z"], + ["fmax_1158_1159_1160.in1","fconst0__1159.out"], + ["fmin_1156_1157_1158.in1","fconst1__1157.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156.in1"], + ["fmin_1156_1157_1158.in0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156.out"], + ["fmin_1156_1157_1158.out","fmax_1158_1159_1160.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1183_1184_1185":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1182":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1180":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1184":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1181_1182_1183":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1179_1180_1181":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1181_1182_1183.out","dwfp_mul_1183_1184_1185.a"], + ["fconst255__1184.out","dwfp_mul_1183_1184_1185.b"], + ["self.out_hw_output_stencil","dwfp_mul_1183_1184_1185.z"], + ["fmax_1181_1182_1183.in1","fconst0__1182.out"], + ["fmin_1179_1180_1181.in1","fconst1__1180.out"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179.in0"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179.in1"], + ["fmin_1179_1180_1181.in0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179.out"], + ["fmin_1179_1180_1181.out","fmax_1181_1182_1183.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1027":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1027.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1030":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1030.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1033":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1033.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1036":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1036.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_1_1046_1047":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_2_1043_1044":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1043":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1044":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_1_1046_1047.a"], + ["dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046.z","dwfp_add_non_local_means_sum_stencil_1_1046_1047.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_1_1046_1047.z"], + ["fexp_1044.out","dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_2_1043_1044.a"], + ["fconst-1__1043.out","dwfp_mul_blur_d_stencil_2_1043_1044.b"], + ["fexp_1044.in","dwfp_mul_blur_d_stencil_2_1043_1044.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_2_1070_1071":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_3_1067_1068":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1067":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1068":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_2_1070_1071.a"], + ["dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070.z","dwfp_add_non_local_means_sum_stencil_2_1070_1071.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_2_1070_1071.z"], + ["fexp_1068.out","dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_3_1067_1068.a"], + ["fconst-1__1067.out","dwfp_mul_blur_d_stencil_3_1067_1068.b"], + ["fexp_1068.in","dwfp_mul_blur_d_stencil_3_1067_1068.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_6":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_3_1094_1095":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_4_1091_1092":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1091":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1092":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_3_1094_1095.a"], + ["dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094.z","dwfp_add_non_local_means_sum_stencil_3_1094_1095.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_3_1094_1095.z"], + ["fexp_1092.out","dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_4_1091_1092.a"], + ["fconst-1__1091.out","dwfp_mul_blur_d_stencil_4_1091_1092.b"], + ["fexp_1092.in","dwfp_mul_blur_d_stencil_4_1091_1092.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_7":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_4_1116_1117":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_5_1114_1115":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1114":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1115":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in1_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_4_1116_1117.a"], + ["fexp_1115.out","dwfp_add_non_local_means_sum_stencil_4_1116_1117.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_4_1116_1117.z"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_5_1114_1115.a"], + ["fconst-1__1114.out","dwfp_mul_blur_d_stencil_5_1114_1115.b"], + ["fexp_1115.in","dwfp_mul_blur_d_stencil_5_1114_1115.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_rolled_7x7_compute.json b/coreir_compute/nlmeans_rolled_7x7_compute.json new file mode 100644 index 000000000..8b9b74066 --- /dev/null +++ b/coreir_compute/nlmeans_rolled_7x7_compute.json @@ -0,0 +1,641 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__985":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_stencil","fconst0__985.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_2_1001_1002":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_3_1000_1001":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_4_999_1000":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_5_998_999":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_6_997_998":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_7_996_997":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.a"], + ["self.in1_blur_d_y_stencil.6","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.b"], + ["dwfp_add_blur_d_y_stencil_7_996_997.b","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.z"], + ["self.in1_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_2_1001_1002.a"], + ["dwfp_add_blur_d_y_stencil_3_1000_1001.z","dwfp_add_blur_d_y_stencil_2_1001_1002.b"], + ["self.out_blur_d_stencil","dwfp_add_blur_d_y_stencil_2_1001_1002.z"], + ["self.in1_blur_d_y_stencil.1","dwfp_add_blur_d_y_stencil_3_1000_1001.a"], + ["dwfp_add_blur_d_y_stencil_4_999_1000.z","dwfp_add_blur_d_y_stencil_3_1000_1001.b"], + ["self.in1_blur_d_y_stencil.2","dwfp_add_blur_d_y_stencil_4_999_1000.a"], + ["dwfp_add_blur_d_y_stencil_5_998_999.z","dwfp_add_blur_d_y_stencil_4_999_1000.b"], + ["self.in1_blur_d_y_stencil.3","dwfp_add_blur_d_y_stencil_5_998_999.a"], + ["dwfp_add_blur_d_y_stencil_6_997_998.z","dwfp_add_blur_d_y_stencil_5_998_999.b"], + ["self.in1_blur_d_y_stencil.4","dwfp_add_blur_d_y_stencil_6_997_998.a"], + ["dwfp_add_blur_d_y_stencil_7_996_997.z","dwfp_add_blur_d_y_stencil_6_997_998.b"], + ["self.in1_blur_d_y_stencil.5","dwfp_add_blur_d_y_stencil_7_996_997.a"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__941":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","fconst0__941.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_y_stencil_1_d_stencil_8_953":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_2_958_959":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_3_957_958":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_4_956_957":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_5_955_956":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_6_954_955":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_7_953_954":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.a"], + ["self.in1_d_stencil.6","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.b"], + ["dwfp_add_d_stencil_7_953_954.b","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.z"], + ["self.in1_d_stencil.0","dwfp_add_d_stencil_2_958_959.a"], + ["dwfp_add_d_stencil_3_957_958.z","dwfp_add_d_stencil_2_958_959.b"], + ["self.out_blur_d_y_stencil","dwfp_add_d_stencil_2_958_959.z"], + ["self.in1_d_stencil.1","dwfp_add_d_stencil_3_957_958.a"], + ["dwfp_add_d_stencil_4_956_957.z","dwfp_add_d_stencil_3_957_958.b"], + ["self.in1_d_stencil.2","dwfp_add_d_stencil_4_956_957.a"], + ["dwfp_add_d_stencil_5_955_956.z","dwfp_add_d_stencil_4_956_957.b"], + ["self.in1_d_stencil.3","dwfp_add_d_stencil_5_955_956.a"], + ["dwfp_add_d_stencil_6_954_955.z","dwfp_add_d_stencil_5_955_956.b"], + ["self.in1_d_stencil.4","dwfp_add_d_stencil_6_954_955.a"], + ["dwfp_add_d_stencil_7_953_954.z","dwfp_add_d_stencil_6_954_955.b"], + ["self.in1_d_stencil.5","dwfp_add_d_stencil_7_953_954.a"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__890":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_d_stencil","fconst0__890.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_906_912_913":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_908_911_912":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_1_910_911":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_905_905_906":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_907_907_908":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_909_909_910":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_905_905_906.z","dwfp_add_906_912_913.a"], + ["dwfp_add_908_911_912.z","dwfp_add_906_912_913.b"], + ["self.out_d_stencil","dwfp_add_906_912_913.z"], + ["dwfp_mul_907_907_908.z","dwfp_add_908_911_912.a"], + ["dwfp_add_d_stencil_1_910_911.z","dwfp_add_908_911_912.b"], + ["self.in0_d_stencil.0","dwfp_add_d_stencil_1_910_911.a"], + ["dwfp_mul_909_909_910.z","dwfp_add_d_stencil_1_910_911.b"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.a"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.b"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.a"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.b"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.a"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.b"], + ["self.in1_hw_input_global_wrapper_stencil.0","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in0"], + ["self.in1_hw_input_global_wrapper_stencil.1","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in1"], + ["self.in1_hw_input_global_wrapper_stencil.2","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in0"], + ["self.in1_hw_input_global_wrapper_stencil.3","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in1"], + ["self.in1_hw_input_global_wrapper_stencil.4","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in0"], + ["self.in1_hw_input_global_wrapper_stencil.5","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1137_1138_1139":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1136":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1134":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1138":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1135_1136_1137":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1133_1134_1135":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1135_1136_1137.out","dwfp_mul_1137_1138_1139.a"], + ["fconst255__1138.out","dwfp_mul_1137_1138_1139.b"], + ["self.out_hw_output_stencil","dwfp_mul_1137_1138_1139.z"], + ["fmax_1135_1136_1137.in1","fconst0__1136.out"], + ["fmin_1133_1134_1135.in1","fconst1__1134.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133.in1"], + ["fmin_1133_1134_1135.in0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1133.out"], + ["fmin_1133_1134_1135.out","fmax_1135_1136_1137.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1160_1161_1162":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1159":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1157":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1161":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1158_1159_1160":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1156_1157_1158":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1158_1159_1160.out","dwfp_mul_1160_1161_1162.a"], + ["fconst255__1161.out","dwfp_mul_1160_1161_1162.b"], + ["self.out_hw_output_stencil","dwfp_mul_1160_1161_1162.z"], + ["fmax_1158_1159_1160.in1","fconst0__1159.out"], + ["fmin_1156_1157_1158.in1","fconst1__1157.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156.in1"], + ["fmin_1156_1157_1158.in0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1156.out"], + ["fmin_1156_1157_1158.out","fmax_1158_1159_1160.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1183_1184_1185":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1182":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1180":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1184":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1181_1182_1183":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1179_1180_1181":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1181_1182_1183.out","dwfp_mul_1183_1184_1185.a"], + ["fconst255__1184.out","dwfp_mul_1183_1184_1185.b"], + ["self.out_hw_output_stencil","dwfp_mul_1183_1184_1185.z"], + ["fmax_1181_1182_1183.in1","fconst0__1182.out"], + ["fmin_1179_1180_1181.in1","fconst1__1180.out"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179.in0"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179.in1"], + ["fmin_1179_1180_1181.in0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1179.out"], + ["fmin_1179_1180_1181.out","fmax_1181_1182_1183.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1027":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1027.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1030":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1030.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1033":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1033.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1036":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1036.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_1_1046_1047":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_2_1043_1044":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1043":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1044":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_1_1046_1047.a"], + ["dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046.z","dwfp_add_non_local_means_sum_stencil_1_1046_1047.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_1_1046_1047.z"], + ["fexp_1044.out","dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1045_hw_input_global_wrapper_stencil_7_1046.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_2_1043_1044.a"], + ["fconst-1__1043.out","dwfp_mul_blur_d_stencil_2_1043_1044.b"], + ["fexp_1044.in","dwfp_mul_blur_d_stencil_2_1043_1044.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_2_1070_1071":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_3_1067_1068":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1067":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1068":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_2_1070_1071.a"], + ["dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070.z","dwfp_add_non_local_means_sum_stencil_2_1070_1071.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_2_1070_1071.z"], + ["fexp_1068.out","dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1069_hw_input_global_wrapper_stencil_8_1070.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_3_1067_1068.a"], + ["fconst-1__1067.out","dwfp_mul_blur_d_stencil_3_1067_1068.b"], + ["fexp_1068.in","dwfp_mul_blur_d_stencil_3_1067_1068.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_6":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_3_1094_1095":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_4_1091_1092":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1091":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1092":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_3_1094_1095.a"], + ["dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094.z","dwfp_add_non_local_means_sum_stencil_3_1094_1095.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_3_1094_1095.z"], + ["fexp_1092.out","dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1093_hw_input_global_wrapper_stencil_9_1094.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_4_1091_1092.a"], + ["fconst-1__1091.out","dwfp_mul_blur_d_stencil_4_1091_1092.b"], + ["fexp_1092.in","dwfp_mul_blur_d_stencil_4_1091_1092.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_7":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_4_1116_1117":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_5_1114_1115":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1114":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1115":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in1_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_4_1116_1117.a"], + ["fexp_1115.out","dwfp_add_non_local_means_sum_stencil_4_1116_1117.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_4_1116_1117.z"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_5_1114_1115.a"], + ["fconst-1__1114.out","dwfp_mul_blur_d_stencil_5_1114_1115.b"], + ["fexp_1115.in","dwfp_mul_blur_d_stencil_5_1114_1115.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_rolled_compute.json b/coreir_compute/nlmeans_rolled_compute.json new file mode 100644 index 000000000..c621c20e0 --- /dev/null +++ b/coreir_compute/nlmeans_rolled_compute.json @@ -0,0 +1,605 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__970":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_stencil","fconst0__970.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_stencil_1_blur_d_y_stencil_5_978":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_2_980_981":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_3_979_980":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_4_978_979":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_5_978.a"], + ["self.in1_blur_d_y_stencil.3","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_5_978.b"], + ["dwfp_add_blur_d_y_stencil_4_978_979.b","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_5_978.z"], + ["self.in1_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_2_980_981.a"], + ["dwfp_add_blur_d_y_stencil_3_979_980.z","dwfp_add_blur_d_y_stencil_2_980_981.b"], + ["self.out_blur_d_stencil","dwfp_add_blur_d_y_stencil_2_980_981.z"], + ["self.in1_blur_d_y_stencil.1","dwfp_add_blur_d_y_stencil_3_979_980.a"], + ["dwfp_add_blur_d_y_stencil_4_978_979.z","dwfp_add_blur_d_y_stencil_3_979_980.b"], + ["self.in1_blur_d_y_stencil.2","dwfp_add_blur_d_y_stencil_4_978_979.a"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__941":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","fconst0__941.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_y_stencil_1_d_stencil_5_950":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_2_952_953":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_3_951_952":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_4_950_951":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_1_d_stencil_5_950.a"], + ["self.in1_d_stencil.3","dwfp_add_blur_d_y_stencil_1_d_stencil_5_950.b"], + ["dwfp_add_d_stencil_4_950_951.b","dwfp_add_blur_d_y_stencil_1_d_stencil_5_950.z"], + ["self.in1_d_stencil.0","dwfp_add_d_stencil_2_952_953.a"], + ["dwfp_add_d_stencil_3_951_952.z","dwfp_add_d_stencil_2_952_953.b"], + ["self.out_blur_d_y_stencil","dwfp_add_d_stencil_2_952_953.z"], + ["self.in1_d_stencil.1","dwfp_add_d_stencil_3_951_952.a"], + ["dwfp_add_d_stencil_4_950_951.z","dwfp_add_d_stencil_3_951_952.b"], + ["self.in1_d_stencil.2","dwfp_add_d_stencil_4_950_951.a"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__890":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_d_stencil","fconst0__890.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_906_912_913":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_908_911_912":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_1_910_911":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_905_905_906":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_907_907_908":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_909_909_910":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_905_905_906.z","dwfp_add_906_912_913.a"], + ["dwfp_add_908_911_912.z","dwfp_add_906_912_913.b"], + ["self.out_d_stencil","dwfp_add_906_912_913.z"], + ["dwfp_mul_907_907_908.z","dwfp_add_908_911_912.a"], + ["dwfp_add_d_stencil_1_910_911.z","dwfp_add_908_911_912.b"], + ["self.in0_d_stencil.0","dwfp_add_d_stencil_1_910_911.a"], + ["dwfp_mul_909_909_910.z","dwfp_add_d_stencil_1_910_911.b"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.a"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.b"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.a"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.b"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.a"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.b"], + ["self.in1_hw_input_global_wrapper_stencil.0","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in0"], + ["self.in1_hw_input_global_wrapper_stencil.1","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in1"], + ["self.in1_hw_input_global_wrapper_stencil.2","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in0"], + ["self.in1_hw_input_global_wrapper_stencil.3","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in1"], + ["self.in1_hw_input_global_wrapper_stencil.4","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in0"], + ["self.in1_hw_input_global_wrapper_stencil.5","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1107_1108_1109":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1106":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1104":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1108":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1103":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1105_1106_1107":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1103_1104_1105":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1105_1106_1107.out","dwfp_mul_1107_1108_1109.a"], + ["fconst255__1108.out","dwfp_mul_1107_1108_1109.b"], + ["self.out_hw_output_stencil","dwfp_mul_1107_1108_1109.z"], + ["fmax_1105_1106_1107.in1","fconst0__1106.out"], + ["fmin_1103_1104_1105.in1","fconst1__1104.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1103.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1103.in1"], + ["fmin_1103_1104_1105.in0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1103.out"], + ["fmin_1103_1104_1105.out","fmax_1105_1106_1107.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1130_1131_1132":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1129":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1127":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1131":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1126":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1128_1129_1130":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1126_1127_1128":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1128_1129_1130.out","dwfp_mul_1130_1131_1132.a"], + ["fconst255__1131.out","dwfp_mul_1130_1131_1132.b"], + ["self.out_hw_output_stencil","dwfp_mul_1130_1131_1132.z"], + ["fmax_1128_1129_1130.in1","fconst0__1129.out"], + ["fmin_1126_1127_1128.in1","fconst1__1127.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1126.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1126.in1"], + ["fmin_1126_1127_1128.in0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1126.out"], + ["fmin_1126_1127_1128.out","fmax_1128_1129_1130.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1153_1154_1155":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1152":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1150":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1154":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1149":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1151_1152_1153":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1149_1150_1151":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1151_1152_1153.out","dwfp_mul_1153_1154_1155.a"], + ["fconst255__1154.out","dwfp_mul_1153_1154_1155.b"], + ["self.out_hw_output_stencil","dwfp_mul_1153_1154_1155.z"], + ["fmax_1151_1152_1153.in1","fconst0__1152.out"], + ["fmin_1149_1150_1151.in1","fconst1__1150.out"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1149.in0"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1149.in1"], + ["fmin_1149_1150_1151.in0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1149.out"], + ["fmin_1149_1150_1151.out","fmax_1151_1152_1153.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__997":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__997.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1000":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1000.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1003":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1003.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1006":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1006.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_1_1016_1017":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1015_hw_input_global_wrapper_stencil_7_1016":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_2_1013_1014":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1013":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1014":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_1_1016_1017.a"], + ["dwfp_mul_1015_hw_input_global_wrapper_stencil_7_1016.z","dwfp_add_non_local_means_sum_stencil_1_1016_1017.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_1_1016_1017.z"], + ["fexp_1014.out","dwfp_mul_1015_hw_input_global_wrapper_stencil_7_1016.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1015_hw_input_global_wrapper_stencil_7_1016.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_2_1013_1014.a"], + ["fconst-1__1013.out","dwfp_mul_blur_d_stencil_2_1013_1014.b"], + ["fexp_1014.in","dwfp_mul_blur_d_stencil_2_1013_1014.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_2_1040_1041":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1039_hw_input_global_wrapper_stencil_8_1040":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_3_1037_1038":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1037":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1038":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_2_1040_1041.a"], + ["dwfp_mul_1039_hw_input_global_wrapper_stencil_8_1040.z","dwfp_add_non_local_means_sum_stencil_2_1040_1041.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_2_1040_1041.z"], + ["fexp_1038.out","dwfp_mul_1039_hw_input_global_wrapper_stencil_8_1040.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1039_hw_input_global_wrapper_stencil_8_1040.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_3_1037_1038.a"], + ["fconst-1__1037.out","dwfp_mul_blur_d_stencil_3_1037_1038.b"], + ["fexp_1038.in","dwfp_mul_blur_d_stencil_3_1037_1038.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_6":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_3_1064_1065":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1063_hw_input_global_wrapper_stencil_9_1064":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_4_1061_1062":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1061":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1062":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_3_1064_1065.a"], + ["dwfp_mul_1063_hw_input_global_wrapper_stencil_9_1064.z","dwfp_add_non_local_means_sum_stencil_3_1064_1065.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_3_1064_1065.z"], + ["fexp_1062.out","dwfp_mul_1063_hw_input_global_wrapper_stencil_9_1064.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1063_hw_input_global_wrapper_stencil_9_1064.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_4_1061_1062.a"], + ["fconst-1__1061.out","dwfp_mul_blur_d_stencil_4_1061_1062.b"], + ["fexp_1062.in","dwfp_mul_blur_d_stencil_4_1061_1062.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_7":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_4_1086_1087":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_5_1084_1085":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1084":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1085":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in1_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_4_1086_1087.a"], + ["fexp_1085.out","dwfp_add_non_local_means_sum_stencil_4_1086_1087.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_4_1086_1087.z"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_5_1084_1085.a"], + ["fconst-1__1084.out","dwfp_mul_blur_d_stencil_5_1084_1085.b"], + ["fexp_1085.in","dwfp_mul_blur_d_stencil_5_1084_1085.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_rolled_int_compute.json b/coreir_compute/nlmeans_rolled_int_compute.json new file mode 100644 index 000000000..b58653727 --- /dev/null +++ b/coreir_compute/nlmeans_rolled_int_compute.json @@ -0,0 +1,532 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__760":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_stencil","const_p0__760.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_stencil_1_769_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_2_770_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_3_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_4_blur_d_y_stencil_5_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","add_blur_d_stencil_1_769_770.in0"], + ["add_blur_d_y_stencil_3_768_769.out","add_blur_d_stencil_1_769_770.in1"], + ["add_blur_d_y_stencil_2_770_771.in1","add_blur_d_stencil_1_769_770.out"], + ["self.in1_blur_d_y_stencil.0","add_blur_d_y_stencil_2_770_771.in0"], + ["self.out_blur_d_stencil","add_blur_d_y_stencil_2_770_771.out"], + ["self.in1_blur_d_y_stencil.1","add_blur_d_y_stencil_3_768_769.in0"], + ["add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.out","add_blur_d_y_stencil_3_768_769.in1"], + ["self.in1_blur_d_y_stencil.2","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in0"], + ["self.in1_blur_d_y_stencil.3","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in1"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__731":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","const_p0__731.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_y_stencil_1_741_742":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_2_742_743":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_3_740_741":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_4_d_stencil_5_740":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","add_blur_d_y_stencil_1_741_742.in0"], + ["add_d_stencil_3_740_741.out","add_blur_d_y_stencil_1_741_742.in1"], + ["add_d_stencil_2_742_743.in1","add_blur_d_y_stencil_1_741_742.out"], + ["self.in1_d_stencil.0","add_d_stencil_2_742_743.in0"], + ["self.out_blur_d_y_stencil","add_d_stencil_2_742_743.out"], + ["self.in1_d_stencil.1","add_d_stencil_3_740_741.in0"], + ["add_d_stencil_4_d_stencil_5_740.out","add_d_stencil_3_740_741.in1"], + ["self.in1_d_stencil.2","add_d_stencil_4_d_stencil_5_740.in0"], + ["self.in1_d_stencil.3","add_d_stencil_4_d_stencil_5_740.in1"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__680":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_d_stencil","const_p0__680.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_696_702_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_698_700_701":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_1_701_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_695_695_696":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_697_697_698":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_699_699_700":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_695_695_696.out","add_696_702_703.in0"], + ["add_d_stencil_1_701_702.out","add_696_702_703.in1"], + ["self.out_d_stencil","add_696_702_703.out"], + ["mul_697_697_698.out","add_698_700_701.in0"], + ["mul_699_699_700.out","add_698_700_701.in1"], + ["add_d_stencil_1_701_702.in1","add_698_700_701.out"], + ["self.in0_d_stencil.0","add_d_stencil_1_701_702.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in0"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in1"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in0"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in1"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in0","self.in1_hw_input_global_wrapper_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in1","self.in1_hw_input_global_wrapper_stencil.1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in0","self.in1_hw_input_global_wrapper_stencil.2"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in1","self.in1_hw_input_global_wrapper_stencil.3"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in0","self.in1_hw_input_global_wrapper_stencil.4"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in1","self.in1_hw_input_global_wrapper_stencil.5"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__895":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__893":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_892":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_894_895_896":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_892_893_894":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_894_895_896.in1","const_p0__895.out"], + ["smin_892_893_894.in1","const_p255__893.out"], + ["self.in0_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_892.in0"], + ["self.in0_non_local_means_sum_stencil.1","mul_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_892.in1"], + ["smin_892_893_894.in0","mul_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_892.out"], + ["smax_894_895_896.out","self.out_hw_output_stencil"], + ["smin_892_893_894.out","smax_894_895_896.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__915":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__913":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_912":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_914_915_916":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_912_913_914":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_914_915_916.in1","const_p0__915.out"], + ["smin_912_913_914.in1","const_p255__913.out"], + ["self.in0_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_912.in0"], + ["self.in0_non_local_means_sum_stencil.1","mul_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_912.in1"], + ["smin_912_913_914.in0","mul_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_912.out"], + ["smax_914_915_916.out","self.out_hw_output_stencil"], + ["smin_912_913_914.out","smax_914_915_916.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__935":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__933":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_932":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_934_935_936":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_932_933_934":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_934_935_936.in1","const_p0__935.out"], + ["smin_932_933_934.in1","const_p255__933.out"], + ["self.in0_non_local_means_sum_stencil.1","mul_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_932.in0"], + ["self.in0_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_932.in1"], + ["smin_932_933_934.in0","mul_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_932.out"], + ["smax_934_935_936.out","self.out_hw_output_stencil"], + ["smin_932_933_934.out","smax_934_935_936.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__787":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__787.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__790":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__790.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__793":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__793.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__796":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__796.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_1_806_807":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p16__804":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0010"]} + }, + "mul_803_804_805":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_blur_d_stencil_2_hw_input_global_wrapper_stencil_7_803":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_1_806_807.in0"], + ["mul_803_804_805.out","add_non_local_means_sum_stencil_1_806_807.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_1_806_807.out"], + ["mul_803_804_805.in1","const_p16__804.out"], + ["mul_blur_d_stencil_2_hw_input_global_wrapper_stencil_7_803.out","mul_803_804_805.in0"], + ["self.in0_blur_d_stencil.0","mul_blur_d_stencil_2_hw_input_global_wrapper_stencil_7_803.in0"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_blur_d_stencil_2_hw_input_global_wrapper_stencil_7_803.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_2_830_831":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p16__828":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0010"]} + }, + "mul_827_828_829":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_blur_d_stencil_3_hw_input_global_wrapper_stencil_8_827":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_2_830_831.in0"], + ["mul_827_828_829.out","add_non_local_means_sum_stencil_2_830_831.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_2_830_831.out"], + ["mul_827_828_829.in1","const_p16__828.out"], + ["mul_blur_d_stencil_3_hw_input_global_wrapper_stencil_8_827.out","mul_827_828_829.in0"], + ["self.in0_blur_d_stencil.0","mul_blur_d_stencil_3_hw_input_global_wrapper_stencil_8_827.in0"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_blur_d_stencil_3_hw_input_global_wrapper_stencil_8_827.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil_6":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_3_854_855":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p16__852":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0010"]} + }, + "mul_851_852_853":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_blur_d_stencil_4_hw_input_global_wrapper_stencil_9_851":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_3_854_855.in0"], + ["mul_851_852_853.out","add_non_local_means_sum_stencil_3_854_855.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_3_854_855.out"], + ["mul_851_852_853.in1","const_p16__852.out"], + ["mul_blur_d_stencil_4_hw_input_global_wrapper_stencil_9_851.out","mul_851_852_853.in0"], + ["self.in0_blur_d_stencil.0","mul_blur_d_stencil_4_hw_input_global_wrapper_stencil_9_851.in0"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_blur_d_stencil_4_hw_input_global_wrapper_stencil_9_851.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil_7":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_4_876_877":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p16__874":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0010"]} + }, + "mul_blur_d_stencil_5_874_875":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in1_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_4_876_877.in0"], + ["mul_blur_d_stencil_5_874_875.out","add_non_local_means_sum_stencil_4_876_877.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_4_876_877.out"], + ["mul_blur_d_stencil_5_874_875.in1","const_p16__874.out"], + ["self.in0_blur_d_stencil.0","mul_blur_d_stencil_5_874_875.in0"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_simple_blur_compute.json b/coreir_compute/nlmeans_simple_blur_compute.json new file mode 100644 index 000000000..821d9612d --- /dev/null +++ b/coreir_compute/nlmeans_simple_blur_compute.json @@ -0,0 +1,544 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__760":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_stencil","const_p0__760.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_stencil_1_769_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_2_770_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_3_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_4_blur_d_y_stencil_5_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","add_blur_d_stencil_1_769_770.in0"], + ["add_blur_d_y_stencil_3_768_769.out","add_blur_d_stencil_1_769_770.in1"], + ["add_blur_d_y_stencil_2_770_771.in1","add_blur_d_stencil_1_769_770.out"], + ["self.in1_blur_d_y_stencil.0","add_blur_d_y_stencil_2_770_771.in0"], + ["self.out_blur_d_stencil","add_blur_d_y_stencil_2_770_771.out"], + ["self.in1_blur_d_y_stencil.1","add_blur_d_y_stencil_3_768_769.in0"], + ["add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.out","add_blur_d_y_stencil_3_768_769.in1"], + ["self.in1_blur_d_y_stencil.2","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in0"], + ["self.in1_blur_d_y_stencil.3","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in1"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__731":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","const_p0__731.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_y_stencil_1_741_742":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_2_742_743":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_3_740_741":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_4_d_stencil_5_740":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","add_blur_d_y_stencil_1_741_742.in0"], + ["add_d_stencil_3_740_741.out","add_blur_d_y_stencil_1_741_742.in1"], + ["add_d_stencil_2_742_743.in1","add_blur_d_y_stencil_1_741_742.out"], + ["self.in1_d_stencil.0","add_d_stencil_2_742_743.in0"], + ["self.out_blur_d_y_stencil","add_d_stencil_2_742_743.out"], + ["self.in1_d_stencil.1","add_d_stencil_3_740_741.in0"], + ["add_d_stencil_4_d_stencil_5_740.out","add_d_stencil_3_740_741.in1"], + ["self.in1_d_stencil.2","add_d_stencil_4_d_stencil_5_740.in0"], + ["self.in1_d_stencil.3","add_d_stencil_4_d_stencil_5_740.in1"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__680":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_d_stencil","const_p0__680.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_696_702_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_698_700_701":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_1_701_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_695_695_696":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_697_697_698":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_699_699_700":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_695_695_696.out","add_696_702_703.in0"], + ["add_d_stencil_1_701_702.out","add_696_702_703.in1"], + ["self.out_d_stencil","add_696_702_703.out"], + ["mul_697_697_698.out","add_698_700_701.in0"], + ["mul_699_699_700.out","add_698_700_701.in1"], + ["add_d_stencil_1_701_702.in1","add_698_700_701.out"], + ["self.in0_d_stencil.0","add_d_stencil_1_701_702.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in0"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in1"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in0"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in1"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in0","self.in1_hw_input_global_wrapper_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in1","self.in1_hw_input_global_wrapper_stencil.1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in0","self.in1_hw_input_global_wrapper_stencil.2"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in1","self.in1_hw_input_global_wrapper_stencil.3"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in0","self.in1_hw_input_global_wrapper_stencil.4"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in1","self.in1_hw_input_global_wrapper_stencil.5"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_d_stencil_2":{ + "type":["Record",[ + ["out_blur_d_stencil_out",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_blur_d_stencil_out","self.in0_non_local_means_div_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__882":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__880":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_881_882_883":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_879_880_881":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_881_882_883.in1","const_p0__882.out"], + ["smin_879_880_881.in1","const_p255__880.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in1"], + ["smin_879_880_881.in0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.out"], + ["smax_881_882_883.out","self.out_hw_output_stencil"], + ["smin_879_880_881.out","smax_881_882_883.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__899":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__897":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_898_899_900":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_896_897_898":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_898_899_900.in1","const_p0__899.out"], + ["smin_896_897_898.in1","const_p255__897.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in1"], + ["smin_896_897_898.in0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.out"], + ["smax_898_899_900.out","self.out_hw_output_stencil"], + ["smin_896_897_898.out","smax_898_899_900.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__916":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__914":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_915_916_917":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_913_914_915":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_915_916_917.in1","const_p0__916.out"], + ["smin_913_914_915.in1","const_p255__914.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in1"], + ["smin_913_914_915.in0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.out"], + ["smax_915_916_917.out","self.out_hw_output_stencil"], + ["smin_913_914_915.out","smax_915_916_917.in0"] + ] + }, + "hcompute_non_local_means_div_stencil":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__787":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_div_stencil","const_p0__787.out"] + ] + }, + "hcompute_non_local_means_div_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_div_stencil_1_793_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_2_792_793":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__792":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + } + }, + "connections":[ + ["self.in1_non_local_means_div_stencil.0","add_non_local_means_div_stencil_1_793_794.in0"], + ["ashr_blur_d_stencil_2_792_793.out","add_non_local_means_div_stencil_1_793_794.in1"], + ["self.out_non_local_means_div_stencil","add_non_local_means_div_stencil_1_793_794.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_2_792_793.in0"], + ["const_p4__792.out","ashr_blur_d_stencil_2_792_793.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__803":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__803.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__806":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__806.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__809":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__809.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_1_817_818":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_3_815_816":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__815":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_7_816_817":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_1_817_818.in0"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.out","add_non_local_means_sum_stencil_1_817_818.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_1_817_818.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_3_815_816.in0"], + ["const_p4__815.out","ashr_blur_d_stencil_3_815_816.in1"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.in1","ashr_blur_d_stencil_3_815_816.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_7_816_817.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_2_838_839":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_4_836_837":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__836":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_8_837_838":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_2_838_839.in0"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.out","add_non_local_means_sum_stencil_2_838_839.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_2_838_839.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_4_836_837.in0"], + ["const_p4__836.out","ashr_blur_d_stencil_4_836_837.in1"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.in1","ashr_blur_d_stencil_4_836_837.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_8_837_838.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_3_859_860":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_5_857_858":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__857":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_9_858_859":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_3_859_860.in0"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.out","add_non_local_means_sum_stencil_3_859_860.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_3_859_860.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_5_857_858.in0"], + ["const_p4__857.out","ashr_blur_d_stencil_5_857_858.in1"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.in1","ashr_blur_d_stencil_5_857_858.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_9_858_859.in0"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_simple_compute.json b/coreir_compute/nlmeans_simple_compute.json new file mode 100644 index 000000000..0df1e44d4 --- /dev/null +++ b/coreir_compute/nlmeans_simple_compute.json @@ -0,0 +1,535 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__760":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_stencil","const_p0__760.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_stencil_1_769_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_2_770_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_3_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_4_blur_d_y_stencil_5_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","add_blur_d_stencil_1_769_770.in0"], + ["add_blur_d_y_stencil_3_768_769.out","add_blur_d_stencil_1_769_770.in1"], + ["add_blur_d_y_stencil_2_770_771.in1","add_blur_d_stencil_1_769_770.out"], + ["self.in1_blur_d_y_stencil.0","add_blur_d_y_stencil_2_770_771.in0"], + ["self.out_blur_d_stencil","add_blur_d_y_stencil_2_770_771.out"], + ["self.in1_blur_d_y_stencil.1","add_blur_d_y_stencil_3_768_769.in0"], + ["add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.out","add_blur_d_y_stencil_3_768_769.in1"], + ["self.in1_blur_d_y_stencil.2","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in0"], + ["self.in1_blur_d_y_stencil.3","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in1"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__731":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","const_p0__731.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_y_stencil_1_741_742":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_2_742_743":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_3_740_741":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_4_d_stencil_5_740":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","add_blur_d_y_stencil_1_741_742.in0"], + ["add_d_stencil_3_740_741.out","add_blur_d_y_stencil_1_741_742.in1"], + ["add_d_stencil_2_742_743.in1","add_blur_d_y_stencil_1_741_742.out"], + ["self.in1_d_stencil.0","add_d_stencil_2_742_743.in0"], + ["self.out_blur_d_y_stencil","add_d_stencil_2_742_743.out"], + ["self.in1_d_stencil.1","add_d_stencil_3_740_741.in0"], + ["add_d_stencil_4_d_stencil_5_740.out","add_d_stencil_3_740_741.in1"], + ["self.in1_d_stencil.2","add_d_stencil_4_d_stencil_5_740.in0"], + ["self.in1_d_stencil.3","add_d_stencil_4_d_stencil_5_740.in1"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__680":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_d_stencil","const_p0__680.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_696_702_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_698_700_701":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_1_701_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_695_695_696":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_697_697_698":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_699_699_700":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_695_695_696.out","add_696_702_703.in0"], + ["add_d_stencil_1_701_702.out","add_696_702_703.in1"], + ["self.out_d_stencil","add_696_702_703.out"], + ["mul_697_697_698.out","add_698_700_701.in0"], + ["mul_699_699_700.out","add_698_700_701.in1"], + ["add_d_stencil_1_701_702.in1","add_698_700_701.out"], + ["self.in0_d_stencil.0","add_d_stencil_1_701_702.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in0"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in1"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in0"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in1"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in0","self.in1_hw_input_global_wrapper_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in1","self.in1_hw_input_global_wrapper_stencil.1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in0","self.in1_hw_input_global_wrapper_stencil.2"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in1","self.in1_hw_input_global_wrapper_stencil.3"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in0","self.in1_hw_input_global_wrapper_stencil.4"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in1","self.in1_hw_input_global_wrapper_stencil.5"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__882":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__880":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_881_882_883":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_879_880_881":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_881_882_883.in1","const_p0__882.out"], + ["smin_879_880_881.in1","const_p255__880.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in1"], + ["smin_879_880_881.in0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.out"], + ["smax_881_882_883.out","self.out_hw_output_stencil"], + ["smin_879_880_881.out","smax_881_882_883.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__899":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__897":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_898_899_900":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_896_897_898":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_898_899_900.in1","const_p0__899.out"], + ["smin_896_897_898.in1","const_p255__897.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in1"], + ["smin_896_897_898.in0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.out"], + ["smax_898_899_900.out","self.out_hw_output_stencil"], + ["smin_896_897_898.out","smax_898_899_900.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__916":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__914":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_915_916_917":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_913_914_915":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_915_916_917.in1","const_p0__916.out"], + ["smin_913_914_915.in1","const_p255__914.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in1"], + ["smin_913_914_915.in0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.out"], + ["smax_915_916_917.out","self.out_hw_output_stencil"], + ["smin_913_914_915.out","smax_915_916_917.in0"] + ] + }, + "hcompute_non_local_means_div_stencil":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__787":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_div_stencil","const_p0__787.out"] + ] + }, + "hcompute_non_local_means_div_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_div_stencil_1_793_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_2_792_793":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__792":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + } + }, + "connections":[ + ["self.in1_non_local_means_div_stencil.0","add_non_local_means_div_stencil_1_793_794.in0"], + ["ashr_blur_d_stencil_2_792_793.out","add_non_local_means_div_stencil_1_793_794.in1"], + ["self.out_non_local_means_div_stencil","add_non_local_means_div_stencil_1_793_794.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_2_792_793.in0"], + ["const_p4__792.out","ashr_blur_d_stencil_2_792_793.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__803":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__803.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__806":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__806.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__809":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__809.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_1_817_818":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_3_815_816":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__815":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_7_816_817":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_1_817_818.in0"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.out","add_non_local_means_sum_stencil_1_817_818.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_1_817_818.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_3_815_816.in0"], + ["const_p4__815.out","ashr_blur_d_stencil_3_815_816.in1"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.in1","ashr_blur_d_stencil_3_815_816.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_7_816_817.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_2_838_839":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_4_836_837":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__836":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_8_837_838":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_2_838_839.in0"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.out","add_non_local_means_sum_stencil_2_838_839.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_2_838_839.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_4_836_837.in0"], + ["const_p4__836.out","ashr_blur_d_stencil_4_836_837.in1"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.in1","ashr_blur_d_stencil_4_836_837.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_8_837_838.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_3_859_860":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_5_857_858":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__857":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_9_858_859":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_3_859_860.in0"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.out","add_non_local_means_sum_stencil_3_859_860.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_3_859_860.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_5_857_858.in0"], + ["const_p4__857.out","ashr_blur_d_stencil_5_857_858.in1"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.in1","ashr_blur_d_stencil_5_857_858.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_9_858_859.in0"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_simple_trunc_compute.json b/coreir_compute/nlmeans_simple_trunc_compute.json new file mode 100644 index 000000000..db91d5283 --- /dev/null +++ b/coreir_compute/nlmeans_simple_trunc_compute.json @@ -0,0 +1,544 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__760":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_stencil","const_p0__760.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_stencil_1_769_770":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_2_770_771":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_3_768_769":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_d_y_stencil_4_blur_d_y_stencil_5_768":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","add_blur_d_stencil_1_769_770.in0"], + ["add_blur_d_y_stencil_3_768_769.out","add_blur_d_stencil_1_769_770.in1"], + ["add_blur_d_y_stencil_2_770_771.in1","add_blur_d_stencil_1_769_770.out"], + ["self.in1_blur_d_y_stencil.0","add_blur_d_y_stencil_2_770_771.in0"], + ["self.out_blur_d_stencil","add_blur_d_y_stencil_2_770_771.out"], + ["self.in1_blur_d_y_stencil.1","add_blur_d_y_stencil_3_768_769.in0"], + ["add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.out","add_blur_d_y_stencil_3_768_769.in1"], + ["self.in1_blur_d_y_stencil.2","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in0"], + ["self.in1_blur_d_y_stencil.3","add_blur_d_y_stencil_4_blur_d_y_stencil_5_768.in1"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__731":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","const_p0__731.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",4,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_blur_d_y_stencil_1_741_742":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_2_742_743":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_3_740_741":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_4_d_stencil_5_740":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","add_blur_d_y_stencil_1_741_742.in0"], + ["add_d_stencil_3_740_741.out","add_blur_d_y_stencil_1_741_742.in1"], + ["add_d_stencil_2_742_743.in1","add_blur_d_y_stencil_1_741_742.out"], + ["self.in1_d_stencil.0","add_d_stencil_2_742_743.in0"], + ["self.out_blur_d_y_stencil","add_d_stencil_2_742_743.out"], + ["self.in1_d_stencil.1","add_d_stencil_3_740_741.in0"], + ["add_d_stencil_4_d_stencil_5_740.out","add_d_stencil_3_740_741.in1"], + ["self.in1_d_stencil.2","add_d_stencil_4_d_stencil_5_740.in0"], + ["self.in1_d_stencil.3","add_d_stencil_4_d_stencil_5_740.in1"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__680":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_d_stencil","const_p0__680.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_696_702_703":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_698_700_701":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_d_stencil_1_701_702":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_695_695_696":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_697_697_698":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_699_699_700":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_695_695_696.out","add_696_702_703.in0"], + ["add_d_stencil_1_701_702.out","add_696_702_703.in1"], + ["self.out_d_stencil","add_696_702_703.out"], + ["mul_697_697_698.out","add_698_700_701.in0"], + ["mul_699_699_700.out","add_698_700_701.in1"], + ["add_d_stencil_1_701_702.in1","add_698_700_701.out"], + ["self.in0_d_stencil.0","add_d_stencil_1_701_702.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.out","mul_695_695_696.in1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in0"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.out","mul_697_697_698.in1"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in0"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.out","mul_699_699_700.in1"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in0","self.in1_hw_input_global_wrapper_stencil.0"], + ["sub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_695.in1","self.in1_hw_input_global_wrapper_stencil.1"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in0","self.in1_hw_input_global_wrapper_stencil.2"], + ["sub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_697.in1","self.in1_hw_input_global_wrapper_stencil.3"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in0","self.in1_hw_input_global_wrapper_stencil.4"], + ["sub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_699.in1","self.in1_hw_input_global_wrapper_stencil.5"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_d_stencil_2":{ + "type":["Record",[ + ["out_d_stencil_out",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_d_stencil_out","self.in0_d_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__882":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__880":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_881_882_883":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_879_880_881":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_881_882_883.in1","const_p0__882.out"], + ["smin_879_880_881.in1","const_p255__880.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.in1"], + ["smin_879_880_881.in0","mul_non_local_means_sum_stencil_4_non_local_means_div_stencil_2_879.out"], + ["smax_881_882_883.out","self.out_hw_output_stencil"], + ["smin_879_880_881.out","smax_881_882_883.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__899":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__897":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_898_899_900":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_896_897_898":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_898_899_900.in1","const_p0__899.out"], + ["smin_896_897_898.in1","const_p255__897.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.in1"], + ["smin_896_897_898.in0","mul_non_local_means_sum_stencil_5_non_local_means_div_stencil_3_896.out"], + ["smax_898_899_900.out","self.out_hw_output_stencil"], + ["smin_896_897_898.out","smax_898_899_900.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__916":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__914":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + }, + "smax_915_916_917":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_913_914_915":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_915_916_917.in1","const_p0__916.out"], + ["smin_913_914_915.in1","const_p255__914.out"], + ["self.in1_non_local_means_sum_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in0"], + ["self.in0_non_local_means_div_stencil.0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.in1"], + ["smin_913_914_915.in0","mul_non_local_means_sum_stencil_6_non_local_means_div_stencil_4_913.out"], + ["smax_915_916_917.out","self.out_hw_output_stencil"], + ["smin_913_914_915.out","smax_915_916_917.in0"] + ] + }, + "hcompute_non_local_means_div_stencil":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__787":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_div_stencil","const_p0__787.out"] + ] + }, + "hcompute_non_local_means_div_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_div_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_non_local_means_div_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_div_stencil_1_793_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_2_792_793":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__792":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + } + }, + "connections":[ + ["self.in1_non_local_means_div_stencil.0","add_non_local_means_div_stencil_1_793_794.in0"], + ["ashr_blur_d_stencil_2_792_793.out","add_non_local_means_div_stencil_1_793_794.in1"], + ["self.out_non_local_means_div_stencil","add_non_local_means_div_stencil_1_793_794.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_2_792_793.in0"], + ["const_p4__792.out","ashr_blur_d_stencil_2_792_793.in1"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__803":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__803.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__806":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__806.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__809":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","const_p0__809.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_1_817_818":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_3_815_816":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__815":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_7_816_817":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_1_817_818.in0"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.out","add_non_local_means_sum_stencil_1_817_818.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_1_817_818.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_3_815_816.in0"], + ["const_p4__815.out","ashr_blur_d_stencil_3_815_816.in1"], + ["mul_hw_input_global_wrapper_stencil_7_816_817.in1","ashr_blur_d_stencil_3_815_816.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_7_816_817.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_2_838_839":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_4_836_837":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__836":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_8_837_838":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_2_838_839.in0"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.out","add_non_local_means_sum_stencil_2_838_839.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_2_838_839.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_4_836_837.in0"], + ["const_p4__836.out","ashr_blur_d_stencil_4_836_837.in1"], + ["mul_hw_input_global_wrapper_stencil_8_837_838.in1","ashr_blur_d_stencil_4_836_837.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_8_837_838.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_non_local_means_sum_stencil_3_859_860":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "ashr_blur_d_stencil_5_857_858":{ + "genref":"coreir.ashr", + "genargs":{"width":["Int",16]} + }, + "const_p4__857":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0004"]} + }, + "mul_hw_input_global_wrapper_stencil_9_858_859":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","add_non_local_means_sum_stencil_3_859_860.in0"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.out","add_non_local_means_sum_stencil_3_859_860.in1"], + ["self.out_non_local_means_sum_stencil","add_non_local_means_sum_stencil_3_859_860.out"], + ["self.in0_blur_d_stencil.0","ashr_blur_d_stencil_5_857_858.in0"], + ["const_p4__857.out","ashr_blur_d_stencil_5_857_858.in1"], + ["mul_hw_input_global_wrapper_stencil_9_858_859.in1","ashr_blur_d_stencil_5_857_858.out"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_input_global_wrapper_stencil_9_858_859.in0"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_small_compute.json b/coreir_compute/nlmeans_small_compute.json new file mode 100644 index 000000000..1c2749cde --- /dev/null +++ b/coreir_compute/nlmeans_small_compute.json @@ -0,0 +1,1169 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__975":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_stencil","fconst0__975.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_stencil_1_blur_d_y_stencil_6_984":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_2_987_988":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_3_986_987":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_4_985_986":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_5_984_985":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_6_984.a"], + ["self.in1_blur_d_y_stencil.4","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_6_984.b"], + ["dwfp_add_blur_d_y_stencil_5_984_985.b","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_6_984.z"], + ["self.in1_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_2_987_988.a"], + ["dwfp_add_blur_d_y_stencil_3_986_987.z","dwfp_add_blur_d_y_stencil_2_987_988.b"], + ["self.out_blur_d_stencil","dwfp_add_blur_d_y_stencil_2_987_988.z"], + ["self.in1_blur_d_y_stencil.1","dwfp_add_blur_d_y_stencil_3_986_987.a"], + ["dwfp_add_blur_d_y_stencil_4_985_986.z","dwfp_add_blur_d_y_stencil_3_986_987.b"], + ["self.in1_blur_d_y_stencil.2","dwfp_add_blur_d_y_stencil_4_985_986.a"], + ["dwfp_add_blur_d_y_stencil_5_984_985.z","dwfp_add_blur_d_y_stencil_4_985_986.b"], + ["self.in1_blur_d_y_stencil.3","dwfp_add_blur_d_y_stencil_5_984_985.a"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__941":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","fconst0__941.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",5,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_y_stencil_1_d_stencil_6_951":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_2_954_955":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_3_953_954":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_4_952_953":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_5_951_952":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_1_d_stencil_6_951.a"], + ["self.in1_d_stencil.4","dwfp_add_blur_d_y_stencil_1_d_stencil_6_951.b"], + ["dwfp_add_d_stencil_5_951_952.b","dwfp_add_blur_d_y_stencil_1_d_stencil_6_951.z"], + ["self.in1_d_stencil.0","dwfp_add_d_stencil_2_954_955.a"], + ["dwfp_add_d_stencil_3_953_954.z","dwfp_add_d_stencil_2_954_955.b"], + ["self.out_blur_d_y_stencil","dwfp_add_d_stencil_2_954_955.z"], + ["self.in1_d_stencil.1","dwfp_add_d_stencil_3_953_954.a"], + ["dwfp_add_d_stencil_4_952_953.z","dwfp_add_d_stencil_3_953_954.b"], + ["self.in1_d_stencil.2","dwfp_add_d_stencil_4_952_953.a"], + ["dwfp_add_d_stencil_5_951_952.z","dwfp_add_d_stencil_4_952_953.b"], + ["self.in1_d_stencil.3","dwfp_add_d_stencil_5_951_952.a"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__890":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_d_stencil","fconst0__890.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_906_912_913":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_908_911_912":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_1_910_911":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_905_905_906":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_907_907_908":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_909_909_910":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_905_905_906.z","dwfp_add_906_912_913.a"], + ["dwfp_add_908_911_912.z","dwfp_add_906_912_913.b"], + ["self.out_d_stencil","dwfp_add_906_912_913.z"], + ["dwfp_mul_907_907_908.z","dwfp_add_908_911_912.a"], + ["dwfp_add_d_stencil_1_910_911.z","dwfp_add_908_911_912.b"], + ["self.in0_d_stencil.0","dwfp_add_d_stencil_1_910_911.a"], + ["dwfp_mul_909_909_910.z","dwfp_add_d_stencil_1_910_911.b"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.a"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.b"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.a"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.b"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.a"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.b"], + ["self.in1_hw_input_global_wrapper_stencil.0","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in0"], + ["self.in1_hw_input_global_wrapper_stencil.1","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in1"], + ["self.in1_hw_input_global_wrapper_stencil.2","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in0"], + ["self.in1_hw_input_global_wrapper_stencil.3","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in1"], + ["self.in1_hw_input_global_wrapper_stencil.4","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in0"], + ["self.in1_hw_input_global_wrapper_stencil.5","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1343_1344_1345":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1342":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1340":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1344":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1339":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1341_1342_1343":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1339_1340_1341":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1341_1342_1343.out","dwfp_mul_1343_1344_1345.a"], + ["fconst255__1344.out","dwfp_mul_1343_1344_1345.b"], + ["self.out_hw_output_stencil","dwfp_mul_1343_1344_1345.z"], + ["fmax_1341_1342_1343.in1","fconst0__1342.out"], + ["fmin_1339_1340_1341.in1","fconst1__1340.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1339.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1339.in1"], + ["fmin_1339_1340_1341.in0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_1339.out"], + ["fmin_1339_1340_1341.out","fmax_1341_1342_1343.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1366_1367_1368":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1365":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1363":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1367":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1362":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1364_1365_1366":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1362_1363_1364":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1364_1365_1366.out","dwfp_mul_1366_1367_1368.a"], + ["fconst255__1367.out","dwfp_mul_1366_1367_1368.b"], + ["self.out_hw_output_stencil","dwfp_mul_1366_1367_1368.z"], + ["fmax_1364_1365_1366.in1","fconst0__1365.out"], + ["fmin_1362_1363_1364.in1","fconst1__1363.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1362.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1362.in1"], + ["fmin_1362_1363_1364.in0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_1362.out"], + ["fmin_1362_1363_1364.out","fmax_1364_1365_1366.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_1389_1390_1391":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__1388":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__1386":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__1390":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1385":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_1387_1388_1389":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_1385_1386_1387":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_1387_1388_1389.out","dwfp_mul_1389_1390_1391.a"], + ["fconst255__1390.out","dwfp_mul_1389_1390_1391.b"], + ["self.out_hw_output_stencil","dwfp_mul_1389_1390_1391.z"], + ["fmax_1387_1388_1389.in1","fconst0__1388.out"], + ["fmin_1385_1386_1387.in1","fconst1__1386.out"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1385.in0"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1385.in1"], + ["fmin_1385_1386_1387.in0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_1385.out"], + ["fmin_1385_1386_1387.out","fmax_1387_1388_1389.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1007":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1007.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1010":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1010.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1013":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1013.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1016":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1016.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_1_1026_1027":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1025_hw_input_global_wrapper_stencil_7_1026":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_2_1023_1024":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1023":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1024":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_1_1026_1027.a"], + ["dwfp_mul_1025_hw_input_global_wrapper_stencil_7_1026.z","dwfp_add_non_local_means_sum_stencil_1_1026_1027.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_1_1026_1027.z"], + ["fexp_1024.out","dwfp_mul_1025_hw_input_global_wrapper_stencil_7_1026.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1025_hw_input_global_wrapper_stencil_7_1026.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_2_1023_1024.a"], + ["fconst-1__1023.out","dwfp_mul_blur_d_stencil_2_1023_1024.b"], + ["fexp_1024.in","dwfp_mul_blur_d_stencil_2_1023_1024.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_2_1046_1047":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1045_hw_input_global_wrapper_stencil_8_1046":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_3_1043_1044":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1043":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1044":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_2_1046_1047.a"], + ["dwfp_mul_1045_hw_input_global_wrapper_stencil_8_1046.z","dwfp_add_non_local_means_sum_stencil_2_1046_1047.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_2_1046_1047.z"], + ["fexp_1044.out","dwfp_mul_1045_hw_input_global_wrapper_stencil_8_1046.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1045_hw_input_global_wrapper_stencil_8_1046.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_3_1043_1044.a"], + ["fconst-1__1043.out","dwfp_mul_blur_d_stencil_3_1043_1044.b"], + ["fexp_1044.in","dwfp_mul_blur_d_stencil_3_1043_1044.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_6":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_non_local_means_sum_stencil_3_1066_1067":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1065_hw_input_global_wrapper_stencil_9_1066":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_4_1063_1064":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1063":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1064":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_3_1066_1067.a"], + ["dwfp_mul_1065_hw_input_global_wrapper_stencil_9_1066.z","dwfp_add_non_local_means_sum_stencil_3_1066_1067.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_non_local_means_sum_stencil_3_1066_1067.z"], + ["fexp_1064.out","dwfp_mul_1065_hw_input_global_wrapper_stencil_9_1066.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1065_hw_input_global_wrapper_stencil_9_1066.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_4_1063_1064.a"], + ["fconst-1__1063.out","dwfp_mul_blur_d_stencil_4_1063_1064.b"], + ["fexp_1064.in","dwfp_mul_blur_d_stencil_4_1063_1064.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_7":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",25,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_1156_1228_1229":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1158_1227_1228":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1160_1226_1227":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1162_1225_1226":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1164_1224_1225":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1166_1223_1224":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1168_1222_1223":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1170_1221_1222":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1172_1220_1221":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1174_1219_1220":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1176_1218_1219":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1178_1217_1218":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1180_1216_1217":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1182_1215_1216":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1184_1214_1215":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1186_1213_1214":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1188_1212_1213":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1190_1211_1212":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1192_1210_1211":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1194_1209_1210":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1196_1208_1209":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1198_1207_1208":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1200_1206_1207":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1202_1205_1206":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_4_1204_1205":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_10_1154_1165":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_11_1154_1167":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_12_1154_1169":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_13_1154_1171":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_14_1154_1173":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_15_1154_1175":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_16_1154_1177":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_17_1154_1179":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_18_1154_1181":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_19_1154_1183":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_20_1154_1185":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_21_1154_1187":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_22_1154_1189":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_23_1154_1191":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_24_1154_1193":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_25_1154_1195":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_26_1154_1197":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_27_1154_1199":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_28_1154_1201":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_29_1154_1203":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_5_1154_1155":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_6_1154_1157":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_7_1154_1159":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_8_1154_1161":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_9_1154_1163":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1154":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1154$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1155":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1157":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1159":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1161":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1163":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1165":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1167":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1169":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1171":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1173":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1175":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1177":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1179":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1181":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1183":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1185":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1187":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1189":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1191":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1193":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1195":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1197":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1199":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1201":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1203":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fexp_1155.out","dwfp_add_1156_1228_1229.a"], + ["dwfp_add_1158_1227_1228.z","dwfp_add_1156_1228_1229.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_1156_1228_1229.z"], + ["fexp_1157.out","dwfp_add_1158_1227_1228.a"], + ["dwfp_add_1160_1226_1227.z","dwfp_add_1158_1227_1228.b"], + ["fexp_1159.out","dwfp_add_1160_1226_1227.a"], + ["dwfp_add_1162_1225_1226.z","dwfp_add_1160_1226_1227.b"], + ["fexp_1161.out","dwfp_add_1162_1225_1226.a"], + ["dwfp_add_1164_1224_1225.z","dwfp_add_1162_1225_1226.b"], + ["fexp_1163.out","dwfp_add_1164_1224_1225.a"], + ["dwfp_add_1166_1223_1224.z","dwfp_add_1164_1224_1225.b"], + ["fexp_1165.out","dwfp_add_1166_1223_1224.a"], + ["dwfp_add_1168_1222_1223.z","dwfp_add_1166_1223_1224.b"], + ["fexp_1167.out","dwfp_add_1168_1222_1223.a"], + ["dwfp_add_1170_1221_1222.z","dwfp_add_1168_1222_1223.b"], + ["fexp_1169.out","dwfp_add_1170_1221_1222.a"], + ["dwfp_add_1172_1220_1221.z","dwfp_add_1170_1221_1222.b"], + ["fexp_1171.out","dwfp_add_1172_1220_1221.a"], + ["dwfp_add_1174_1219_1220.z","dwfp_add_1172_1220_1221.b"], + ["fexp_1173.out","dwfp_add_1174_1219_1220.a"], + ["dwfp_add_1176_1218_1219.z","dwfp_add_1174_1219_1220.b"], + ["fexp_1175.out","dwfp_add_1176_1218_1219.a"], + ["dwfp_add_1178_1217_1218.z","dwfp_add_1176_1218_1219.b"], + ["fexp_1177.out","dwfp_add_1178_1217_1218.a"], + ["dwfp_add_1180_1216_1217.z","dwfp_add_1178_1217_1218.b"], + ["fexp_1179.out","dwfp_add_1180_1216_1217.a"], + ["dwfp_add_1182_1215_1216.z","dwfp_add_1180_1216_1217.b"], + ["fexp_1181.out","dwfp_add_1182_1215_1216.a"], + ["dwfp_add_1184_1214_1215.z","dwfp_add_1182_1215_1216.b"], + ["fexp_1183.out","dwfp_add_1184_1214_1215.a"], + ["dwfp_add_1186_1213_1214.z","dwfp_add_1184_1214_1215.b"], + ["fexp_1185.out","dwfp_add_1186_1213_1214.a"], + ["dwfp_add_1188_1212_1213.z","dwfp_add_1186_1213_1214.b"], + ["fexp_1187.out","dwfp_add_1188_1212_1213.a"], + ["dwfp_add_1190_1211_1212.z","dwfp_add_1188_1212_1213.b"], + ["fexp_1189.out","dwfp_add_1190_1211_1212.a"], + ["dwfp_add_1192_1210_1211.z","dwfp_add_1190_1211_1212.b"], + ["fexp_1191.out","dwfp_add_1192_1210_1211.a"], + ["dwfp_add_1194_1209_1210.z","dwfp_add_1192_1210_1211.b"], + ["fexp_1193.out","dwfp_add_1194_1209_1210.a"], + ["dwfp_add_1196_1208_1209.z","dwfp_add_1194_1209_1210.b"], + ["fexp_1195.out","dwfp_add_1196_1208_1209.a"], + ["dwfp_add_1198_1207_1208.z","dwfp_add_1196_1208_1209.b"], + ["fexp_1197.out","dwfp_add_1198_1207_1208.a"], + ["dwfp_add_1200_1206_1207.z","dwfp_add_1198_1207_1208.b"], + ["fexp_1199.out","dwfp_add_1200_1206_1207.a"], + ["dwfp_add_1202_1205_1206.z","dwfp_add_1200_1206_1207.b"], + ["fexp_1201.out","dwfp_add_1202_1205_1206.a"], + ["dwfp_add_non_local_means_sum_stencil_4_1204_1205.z","dwfp_add_1202_1205_1206.b"], + ["self.in1_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_4_1204_1205.a"], + ["fexp_1203.out","dwfp_add_non_local_means_sum_stencil_4_1204_1205.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_10_1154_1165.a"], + ["fconst-1__1154$5.out","dwfp_mul_blur_d_stencil_10_1154_1165.b"], + ["fexp_1165.in","dwfp_mul_blur_d_stencil_10_1154_1165.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_11_1154_1167.a"], + ["fconst-1__1154$6.out","dwfp_mul_blur_d_stencil_11_1154_1167.b"], + ["fexp_1167.in","dwfp_mul_blur_d_stencil_11_1154_1167.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_12_1154_1169.a"], + ["fconst-1__1154$7.out","dwfp_mul_blur_d_stencil_12_1154_1169.b"], + ["fexp_1169.in","dwfp_mul_blur_d_stencil_12_1154_1169.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_13_1154_1171.a"], + ["fconst-1__1154$8.out","dwfp_mul_blur_d_stencil_13_1154_1171.b"], + ["fexp_1171.in","dwfp_mul_blur_d_stencil_13_1154_1171.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_14_1154_1173.a"], + ["fconst-1__1154$9.out","dwfp_mul_blur_d_stencil_14_1154_1173.b"], + ["fexp_1173.in","dwfp_mul_blur_d_stencil_14_1154_1173.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_15_1154_1175.a"], + ["fconst-1__1154$10.out","dwfp_mul_blur_d_stencil_15_1154_1175.b"], + ["fexp_1175.in","dwfp_mul_blur_d_stencil_15_1154_1175.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_16_1154_1177.a"], + ["fconst-1__1154$11.out","dwfp_mul_blur_d_stencil_16_1154_1177.b"], + ["fexp_1177.in","dwfp_mul_blur_d_stencil_16_1154_1177.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_17_1154_1179.a"], + ["fconst-1__1154$12.out","dwfp_mul_blur_d_stencil_17_1154_1179.b"], + ["fexp_1179.in","dwfp_mul_blur_d_stencil_17_1154_1179.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_18_1154_1181.a"], + ["fconst-1__1154$13.out","dwfp_mul_blur_d_stencil_18_1154_1181.b"], + ["fexp_1181.in","dwfp_mul_blur_d_stencil_18_1154_1181.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_19_1154_1183.a"], + ["fconst-1__1154$14.out","dwfp_mul_blur_d_stencil_19_1154_1183.b"], + ["fexp_1183.in","dwfp_mul_blur_d_stencil_19_1154_1183.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_20_1154_1185.a"], + ["fconst-1__1154$15.out","dwfp_mul_blur_d_stencil_20_1154_1185.b"], + ["fexp_1185.in","dwfp_mul_blur_d_stencil_20_1154_1185.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_21_1154_1187.a"], + ["fconst-1__1154$16.out","dwfp_mul_blur_d_stencil_21_1154_1187.b"], + ["fexp_1187.in","dwfp_mul_blur_d_stencil_21_1154_1187.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_22_1154_1189.a"], + ["fconst-1__1154$17.out","dwfp_mul_blur_d_stencil_22_1154_1189.b"], + ["fexp_1189.in","dwfp_mul_blur_d_stencil_22_1154_1189.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_23_1154_1191.a"], + ["fconst-1__1154$18.out","dwfp_mul_blur_d_stencil_23_1154_1191.b"], + ["fexp_1191.in","dwfp_mul_blur_d_stencil_23_1154_1191.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_24_1154_1193.a"], + ["fconst-1__1154$19.out","dwfp_mul_blur_d_stencil_24_1154_1193.b"], + ["fexp_1193.in","dwfp_mul_blur_d_stencil_24_1154_1193.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_25_1154_1195.a"], + ["fconst-1__1154$20.out","dwfp_mul_blur_d_stencil_25_1154_1195.b"], + ["fexp_1195.in","dwfp_mul_blur_d_stencil_25_1154_1195.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_26_1154_1197.a"], + ["fconst-1__1154$21.out","dwfp_mul_blur_d_stencil_26_1154_1197.b"], + ["fexp_1197.in","dwfp_mul_blur_d_stencil_26_1154_1197.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_27_1154_1199.a"], + ["fconst-1__1154$22.out","dwfp_mul_blur_d_stencil_27_1154_1199.b"], + ["fexp_1199.in","dwfp_mul_blur_d_stencil_27_1154_1199.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_28_1154_1201.a"], + ["fconst-1__1154$23.out","dwfp_mul_blur_d_stencil_28_1154_1201.b"], + ["fexp_1201.in","dwfp_mul_blur_d_stencil_28_1154_1201.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_29_1154_1203.a"], + ["fconst-1__1154$24.out","dwfp_mul_blur_d_stencil_29_1154_1203.b"], + ["fexp_1203.in","dwfp_mul_blur_d_stencil_29_1154_1203.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_5_1154_1155.a"], + ["fconst-1__1154.out","dwfp_mul_blur_d_stencil_5_1154_1155.b"], + ["fexp_1155.in","dwfp_mul_blur_d_stencil_5_1154_1155.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_6_1154_1157.a"], + ["fconst-1__1154$1.out","dwfp_mul_blur_d_stencil_6_1154_1157.b"], + ["fexp_1157.in","dwfp_mul_blur_d_stencil_6_1154_1157.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_7_1154_1159.a"], + ["fconst-1__1154$2.out","dwfp_mul_blur_d_stencil_7_1154_1159.b"], + ["fexp_1159.in","dwfp_mul_blur_d_stencil_7_1154_1159.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_8_1154_1161.a"], + ["fconst-1__1154$3.out","dwfp_mul_blur_d_stencil_8_1154_1161.b"], + ["fexp_1161.in","dwfp_mul_blur_d_stencil_8_1154_1161.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_9_1154_1163.a"], + ["fconst-1__1154$4.out","dwfp_mul_blur_d_stencil_9_1154_1163.b"], + ["fexp_1163.in","dwfp_mul_blur_d_stencil_9_1154_1163.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_unroll_compute.json b/coreir_compute/nlmeans_unroll_compute.json new file mode 100644 index 000000000..4013a499d --- /dev/null +++ b/coreir_compute/nlmeans_unroll_compute.json @@ -0,0 +1,5921 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__985":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_stencil","fconst0__985.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_2_1001_1002":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_3_1000_1001":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_4_999_1000":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_5_998_999":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_6_997_998":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_7_996_997":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.a"], + ["self.in1_blur_d_y_stencil.6","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.b"], + ["dwfp_add_blur_d_y_stencil_7_996_997.b","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.z"], + ["self.in1_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_2_1001_1002.a"], + ["dwfp_add_blur_d_y_stencil_3_1000_1001.z","dwfp_add_blur_d_y_stencil_2_1001_1002.b"], + ["self.out_blur_d_stencil","dwfp_add_blur_d_y_stencil_2_1001_1002.z"], + ["self.in1_blur_d_y_stencil.1","dwfp_add_blur_d_y_stencil_3_1000_1001.a"], + ["dwfp_add_blur_d_y_stencil_4_999_1000.z","dwfp_add_blur_d_y_stencil_3_1000_1001.b"], + ["self.in1_blur_d_y_stencil.2","dwfp_add_blur_d_y_stencil_4_999_1000.a"], + ["dwfp_add_blur_d_y_stencil_5_998_999.z","dwfp_add_blur_d_y_stencil_4_999_1000.b"], + ["self.in1_blur_d_y_stencil.3","dwfp_add_blur_d_y_stencil_5_998_999.a"], + ["dwfp_add_blur_d_y_stencil_6_997_998.z","dwfp_add_blur_d_y_stencil_5_998_999.b"], + ["self.in1_blur_d_y_stencil.4","dwfp_add_blur_d_y_stencil_6_997_998.a"], + ["dwfp_add_blur_d_y_stencil_7_996_997.z","dwfp_add_blur_d_y_stencil_6_997_998.b"], + ["self.in1_blur_d_y_stencil.5","dwfp_add_blur_d_y_stencil_7_996_997.a"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__941":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","fconst0__941.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_y_stencil_1_d_stencil_8_953":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_2_958_959":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_3_957_958":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_4_956_957":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_5_955_956":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_6_954_955":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_7_953_954":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.a"], + ["self.in1_d_stencil.6","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.b"], + ["dwfp_add_d_stencil_7_953_954.b","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.z"], + ["self.in1_d_stencil.0","dwfp_add_d_stencil_2_958_959.a"], + ["dwfp_add_d_stencil_3_957_958.z","dwfp_add_d_stencil_2_958_959.b"], + ["self.out_blur_d_y_stencil","dwfp_add_d_stencil_2_958_959.z"], + ["self.in1_d_stencil.1","dwfp_add_d_stencil_3_957_958.a"], + ["dwfp_add_d_stencil_4_956_957.z","dwfp_add_d_stencil_3_957_958.b"], + ["self.in1_d_stencil.2","dwfp_add_d_stencil_4_956_957.a"], + ["dwfp_add_d_stencil_5_955_956.z","dwfp_add_d_stencil_4_956_957.b"], + ["self.in1_d_stencil.3","dwfp_add_d_stencil_5_955_956.a"], + ["dwfp_add_d_stencil_6_954_955.z","dwfp_add_d_stencil_5_955_956.b"], + ["self.in1_d_stencil.4","dwfp_add_d_stencil_6_954_955.a"], + ["dwfp_add_d_stencil_7_953_954.z","dwfp_add_d_stencil_6_954_955.b"], + ["self.in1_d_stencil.5","dwfp_add_d_stencil_7_953_954.a"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__890":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_d_stencil","fconst0__890.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_906_912_913":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_908_911_912":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_1_910_911":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_905_905_906":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_907_907_908":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_909_909_910":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_905_905_906.z","dwfp_add_906_912_913.a"], + ["dwfp_add_908_911_912.z","dwfp_add_906_912_913.b"], + ["self.out_d_stencil","dwfp_add_906_912_913.z"], + ["dwfp_mul_907_907_908.z","dwfp_add_908_911_912.a"], + ["dwfp_add_d_stencil_1_910_911.z","dwfp_add_908_911_912.b"], + ["self.in0_d_stencil.0","dwfp_add_d_stencil_1_910_911.a"], + ["dwfp_mul_909_909_910.z","dwfp_add_d_stencil_1_910_911.b"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.a"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.b"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.a"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.b"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.a"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.b"], + ["self.in1_hw_input_global_wrapper_stencil.0","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in0"], + ["self.in1_hw_input_global_wrapper_stencil.1","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in1"], + ["self.in1_hw_input_global_wrapper_stencil.2","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in0"], + ["self.in1_hw_input_global_wrapper_stencil.3","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in1"], + ["self.in1_hw_input_global_wrapper_stencil.4","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in0"], + ["self.in1_hw_input_global_wrapper_stencil.5","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_3655_3656_3657":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__3654":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__3652":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__3656":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_3653_3654_3655":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_3651_3652_3653":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_3653_3654_3655.out","dwfp_mul_3655_3656_3657.a"], + ["fconst255__3656.out","dwfp_mul_3655_3656_3657.b"], + ["self.out_hw_output_stencil","dwfp_mul_3655_3656_3657.z"], + ["fmax_3653_3654_3655.in1","fconst0__3654.out"], + ["fmin_3651_3652_3653.in1","fconst1__3652.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651.in1"], + ["fmin_3651_3652_3653.in0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651.out"], + ["fmin_3651_3652_3653.out","fmax_3653_3654_3655.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_3678_3679_3680":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__3677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__3675":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__3679":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_3676_3677_3678":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_3674_3675_3676":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_3676_3677_3678.out","dwfp_mul_3678_3679_3680.a"], + ["fconst255__3679.out","dwfp_mul_3678_3679_3680.b"], + ["self.out_hw_output_stencil","dwfp_mul_3678_3679_3680.z"], + ["fmax_3676_3677_3678.in1","fconst0__3677.out"], + ["fmin_3674_3675_3676.in1","fconst1__3675.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674.in1"], + ["fmin_3674_3675_3676.in0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674.out"], + ["fmin_3674_3675_3676.out","fmax_3676_3677_3678.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_3701_3702_3703":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__3700":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__3698":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__3702":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_3699_3700_3701":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_3697_3698_3699":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_3699_3700_3701.out","dwfp_mul_3701_3702_3703.a"], + ["fconst255__3702.out","dwfp_mul_3701_3702_3703.b"], + ["self.out_hw_output_stencil","dwfp_mul_3701_3702_3703.z"], + ["fmax_3699_3700_3701.in1","fconst0__3700.out"], + ["fmin_3697_3698_3699.in1","fconst1__3698.out"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697.in0"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697.in1"], + ["fmin_3697_3698_3699.in0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697.out"], + ["fmin_3697_3698_3699.out","fmax_3699_3700_3701.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1027":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1027.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1030":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1030.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1033":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1033.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1036":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1036.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_1238_1430_1431":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1241_1429_1430":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1244_1428_1429":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1247_1427_1428":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1250_1426_1427":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1253_1425_1426":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1256_1424_1425":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1259_1423_1424":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1262_1422_1423":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1265_1421_1422":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1268_1420_1421":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1271_1419_1420":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1274_1418_1419":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1277_1417_1418":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1280_1416_1417":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1283_1415_1416":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1286_1414_1415":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1289_1413_1414":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1292_1412_1413":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1295_1411_1412":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1298_1410_1411":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1301_1409_1410":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1304_1408_1409":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1307_1407_1408":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1310_1406_1407":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1313_1405_1406":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1316_1404_1405":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1319_1403_1404":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1322_1402_1403":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1325_1401_1402":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1328_1400_1401":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1331_1399_1400":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1334_1398_1399":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1337_1397_1398":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1340_1396_1397":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1343_1395_1396":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1346_1394_1395":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1349_1393_1394":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1352_1392_1393":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1355_1391_1392":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1358_1390_1391":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1361_1389_1390":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1364_1388_1389":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1367_1387_1388":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1370_1386_1387":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1373_1385_1386":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1376_1384_1385":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1379_1383_1384":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_1_1382_1383":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_10_1235_1260":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_11_1235_1263":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_12_1235_1266":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_13_1235_1269":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_14_1235_1272":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_15_1235_1275":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_16_1235_1278":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_17_1235_1281":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_18_1235_1284":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_19_1235_1287":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_20_1235_1290":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_21_1235_1293":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_22_1235_1296":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_23_1235_1299":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_24_1235_1302":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_25_1235_1305":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_26_1235_1308":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_27_1235_1311":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_28_1235_1314":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_29_1235_1317":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_2_1235_1236":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_30_1235_1320":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_31_1235_1323":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_32_1235_1326":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_33_1235_1329":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_34_1235_1332":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_35_1235_1335":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_36_1235_1338":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_37_1235_1341":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_38_1235_1344":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_39_1235_1347":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_3_1235_1239":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_40_1235_1350":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_41_1235_1353":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_42_1235_1356":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_43_1235_1359":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_44_1235_1362":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_45_1235_1365":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_46_1235_1368":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_47_1235_1371":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_48_1235_1374":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_49_1235_1377":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_4_1235_1242":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_50_1235_1380":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_5_1235_1245":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_6_1235_1248":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_7_1235_1251":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_8_1235_1254":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_9_1235_1257":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1235":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1236":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1239":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1242":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1245":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1248":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1251":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1254":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1257":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1260":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1263":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1266":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1269":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1272":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1275":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1278":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1281":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1284":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1287":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1290":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1293":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1296":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1299":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1302":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1305":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1308":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1311":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1314":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1317":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1320":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1323":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1326":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1329":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1332":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1335":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1338":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1341":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1344":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1347":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1350":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1353":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1356":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1359":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1362":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1365":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1368":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1371":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1374":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1377":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1380":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238.z","dwfp_add_1238_1430_1431.a"], + ["dwfp_add_1241_1429_1430.z","dwfp_add_1238_1430_1431.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_1238_1430_1431.z"], + ["dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241.z","dwfp_add_1241_1429_1430.a"], + ["dwfp_add_1244_1428_1429.z","dwfp_add_1241_1429_1430.b"], + ["dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244.z","dwfp_add_1244_1428_1429.a"], + ["dwfp_add_1247_1427_1428.z","dwfp_add_1244_1428_1429.b"], + ["dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247.z","dwfp_add_1247_1427_1428.a"], + ["dwfp_add_1250_1426_1427.z","dwfp_add_1247_1427_1428.b"], + ["dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250.z","dwfp_add_1250_1426_1427.a"], + ["dwfp_add_1253_1425_1426.z","dwfp_add_1250_1426_1427.b"], + ["dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253.z","dwfp_add_1253_1425_1426.a"], + ["dwfp_add_1256_1424_1425.z","dwfp_add_1253_1425_1426.b"], + ["dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256.z","dwfp_add_1256_1424_1425.a"], + ["dwfp_add_1259_1423_1424.z","dwfp_add_1256_1424_1425.b"], + ["dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259.z","dwfp_add_1259_1423_1424.a"], + ["dwfp_add_1262_1422_1423.z","dwfp_add_1259_1423_1424.b"], + ["dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262.z","dwfp_add_1262_1422_1423.a"], + ["dwfp_add_1265_1421_1422.z","dwfp_add_1262_1422_1423.b"], + ["dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265.z","dwfp_add_1265_1421_1422.a"], + ["dwfp_add_1268_1420_1421.z","dwfp_add_1265_1421_1422.b"], + ["dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268.z","dwfp_add_1268_1420_1421.a"], + ["dwfp_add_1271_1419_1420.z","dwfp_add_1268_1420_1421.b"], + ["dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271.z","dwfp_add_1271_1419_1420.a"], + ["dwfp_add_1274_1418_1419.z","dwfp_add_1271_1419_1420.b"], + ["dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274.z","dwfp_add_1274_1418_1419.a"], + ["dwfp_add_1277_1417_1418.z","dwfp_add_1274_1418_1419.b"], + ["dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277.z","dwfp_add_1277_1417_1418.a"], + ["dwfp_add_1280_1416_1417.z","dwfp_add_1277_1417_1418.b"], + ["dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280.z","dwfp_add_1280_1416_1417.a"], + ["dwfp_add_1283_1415_1416.z","dwfp_add_1280_1416_1417.b"], + ["dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283.z","dwfp_add_1283_1415_1416.a"], + ["dwfp_add_1286_1414_1415.z","dwfp_add_1283_1415_1416.b"], + ["dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286.z","dwfp_add_1286_1414_1415.a"], + ["dwfp_add_1289_1413_1414.z","dwfp_add_1286_1414_1415.b"], + ["dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289.z","dwfp_add_1289_1413_1414.a"], + ["dwfp_add_1292_1412_1413.z","dwfp_add_1289_1413_1414.b"], + ["dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292.z","dwfp_add_1292_1412_1413.a"], + ["dwfp_add_1295_1411_1412.z","dwfp_add_1292_1412_1413.b"], + ["dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295.z","dwfp_add_1295_1411_1412.a"], + ["dwfp_add_1298_1410_1411.z","dwfp_add_1295_1411_1412.b"], + ["dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298.z","dwfp_add_1298_1410_1411.a"], + ["dwfp_add_1301_1409_1410.z","dwfp_add_1298_1410_1411.b"], + ["dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301.z","dwfp_add_1301_1409_1410.a"], + ["dwfp_add_1304_1408_1409.z","dwfp_add_1301_1409_1410.b"], + ["dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304.z","dwfp_add_1304_1408_1409.a"], + ["dwfp_add_1307_1407_1408.z","dwfp_add_1304_1408_1409.b"], + ["dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307.z","dwfp_add_1307_1407_1408.a"], + ["dwfp_add_1310_1406_1407.z","dwfp_add_1307_1407_1408.b"], + ["dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310.z","dwfp_add_1310_1406_1407.a"], + ["dwfp_add_1313_1405_1406.z","dwfp_add_1310_1406_1407.b"], + ["dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313.z","dwfp_add_1313_1405_1406.a"], + ["dwfp_add_1316_1404_1405.z","dwfp_add_1313_1405_1406.b"], + ["dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316.z","dwfp_add_1316_1404_1405.a"], + ["dwfp_add_1319_1403_1404.z","dwfp_add_1316_1404_1405.b"], + ["dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319.z","dwfp_add_1319_1403_1404.a"], + ["dwfp_add_1322_1402_1403.z","dwfp_add_1319_1403_1404.b"], + ["dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322.z","dwfp_add_1322_1402_1403.a"], + ["dwfp_add_1325_1401_1402.z","dwfp_add_1322_1402_1403.b"], + ["dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325.z","dwfp_add_1325_1401_1402.a"], + ["dwfp_add_1328_1400_1401.z","dwfp_add_1325_1401_1402.b"], + ["dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328.z","dwfp_add_1328_1400_1401.a"], + ["dwfp_add_1331_1399_1400.z","dwfp_add_1328_1400_1401.b"], + ["dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331.z","dwfp_add_1331_1399_1400.a"], + ["dwfp_add_1334_1398_1399.z","dwfp_add_1331_1399_1400.b"], + ["dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334.z","dwfp_add_1334_1398_1399.a"], + ["dwfp_add_1337_1397_1398.z","dwfp_add_1334_1398_1399.b"], + ["dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337.z","dwfp_add_1337_1397_1398.a"], + ["dwfp_add_1340_1396_1397.z","dwfp_add_1337_1397_1398.b"], + ["dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340.z","dwfp_add_1340_1396_1397.a"], + ["dwfp_add_1343_1395_1396.z","dwfp_add_1340_1396_1397.b"], + ["dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343.z","dwfp_add_1343_1395_1396.a"], + ["dwfp_add_1346_1394_1395.z","dwfp_add_1343_1395_1396.b"], + ["dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346.z","dwfp_add_1346_1394_1395.a"], + ["dwfp_add_1349_1393_1394.z","dwfp_add_1346_1394_1395.b"], + ["dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349.z","dwfp_add_1349_1393_1394.a"], + ["dwfp_add_1352_1392_1393.z","dwfp_add_1349_1393_1394.b"], + ["dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352.z","dwfp_add_1352_1392_1393.a"], + ["dwfp_add_1355_1391_1392.z","dwfp_add_1352_1392_1393.b"], + ["dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355.z","dwfp_add_1355_1391_1392.a"], + ["dwfp_add_1358_1390_1391.z","dwfp_add_1355_1391_1392.b"], + ["dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358.z","dwfp_add_1358_1390_1391.a"], + ["dwfp_add_1361_1389_1390.z","dwfp_add_1358_1390_1391.b"], + ["dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361.z","dwfp_add_1361_1389_1390.a"], + ["dwfp_add_1364_1388_1389.z","dwfp_add_1361_1389_1390.b"], + ["dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364.z","dwfp_add_1364_1388_1389.a"], + ["dwfp_add_1367_1387_1388.z","dwfp_add_1364_1388_1389.b"], + ["dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367.z","dwfp_add_1367_1387_1388.a"], + ["dwfp_add_1370_1386_1387.z","dwfp_add_1367_1387_1388.b"], + ["dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370.z","dwfp_add_1370_1386_1387.a"], + ["dwfp_add_1373_1385_1386.z","dwfp_add_1370_1386_1387.b"], + ["dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373.z","dwfp_add_1373_1385_1386.a"], + ["dwfp_add_1376_1384_1385.z","dwfp_add_1373_1385_1386.b"], + ["dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376.z","dwfp_add_1376_1384_1385.a"], + ["dwfp_add_1379_1383_1384.z","dwfp_add_1376_1384_1385.b"], + ["dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379.z","dwfp_add_1379_1383_1384.a"], + ["dwfp_add_non_local_means_sum_stencil_1_1382_1383.z","dwfp_add_1379_1383_1384.b"], + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_1_1382_1383.a"], + ["dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382.z","dwfp_add_non_local_means_sum_stencil_1_1382_1383.b"], + ["fexp_1236.out","dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238.a"], + ["self.in1_hw_input_global_wrapper_stencil.46","dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238.b"], + ["fexp_1239.out","dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241.a"], + ["self.in1_hw_input_global_wrapper_stencil.47","dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241.b"], + ["fexp_1242.out","dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244.a"], + ["self.in1_hw_input_global_wrapper_stencil.48","dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244.b"], + ["fexp_1245.out","dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247.b"], + ["fexp_1248.out","dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250.a"], + ["self.in1_hw_input_global_wrapper_stencil.1","dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250.b"], + ["fexp_1251.out","dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253.a"], + ["self.in1_hw_input_global_wrapper_stencil.2","dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253.b"], + ["fexp_1254.out","dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256.a"], + ["self.in1_hw_input_global_wrapper_stencil.3","dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256.b"], + ["fexp_1257.out","dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259.a"], + ["self.in1_hw_input_global_wrapper_stencil.4","dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259.b"], + ["fexp_1260.out","dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262.a"], + ["self.in1_hw_input_global_wrapper_stencil.5","dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262.b"], + ["fexp_1263.out","dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265.a"], + ["self.in1_hw_input_global_wrapper_stencil.6","dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265.b"], + ["fexp_1266.out","dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268.a"], + ["self.in1_hw_input_global_wrapper_stencil.7","dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268.b"], + ["fexp_1269.out","dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271.a"], + ["self.in1_hw_input_global_wrapper_stencil.8","dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271.b"], + ["fexp_1272.out","dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274.a"], + ["self.in1_hw_input_global_wrapper_stencil.9","dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274.b"], + ["fexp_1275.out","dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277.a"], + ["self.in1_hw_input_global_wrapper_stencil.10","dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277.b"], + ["fexp_1278.out","dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280.a"], + ["self.in1_hw_input_global_wrapper_stencil.11","dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280.b"], + ["fexp_1281.out","dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283.a"], + ["self.in1_hw_input_global_wrapper_stencil.12","dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283.b"], + ["fexp_1284.out","dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286.a"], + ["self.in1_hw_input_global_wrapper_stencil.13","dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286.b"], + ["fexp_1287.out","dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289.a"], + ["self.in1_hw_input_global_wrapper_stencil.14","dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289.b"], + ["fexp_1290.out","dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292.a"], + ["self.in1_hw_input_global_wrapper_stencil.15","dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292.b"], + ["fexp_1293.out","dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295.a"], + ["self.in1_hw_input_global_wrapper_stencil.16","dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295.b"], + ["fexp_1296.out","dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298.a"], + ["self.in1_hw_input_global_wrapper_stencil.17","dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298.b"], + ["fexp_1299.out","dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301.a"], + ["self.in1_hw_input_global_wrapper_stencil.18","dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301.b"], + ["fexp_1302.out","dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304.a"], + ["self.in1_hw_input_global_wrapper_stencil.19","dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304.b"], + ["fexp_1305.out","dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307.a"], + ["self.in1_hw_input_global_wrapper_stencil.20","dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307.b"], + ["fexp_1308.out","dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310.a"], + ["self.in1_hw_input_global_wrapper_stencil.21","dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310.b"], + ["fexp_1311.out","dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313.a"], + ["self.in1_hw_input_global_wrapper_stencil.22","dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313.b"], + ["fexp_1314.out","dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316.a"], + ["self.in1_hw_input_global_wrapper_stencil.23","dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316.b"], + ["fexp_1317.out","dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319.a"], + ["self.in1_hw_input_global_wrapper_stencil.24","dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319.b"], + ["fexp_1320.out","dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322.a"], + ["self.in1_hw_input_global_wrapper_stencil.25","dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322.b"], + ["fexp_1323.out","dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325.a"], + ["self.in1_hw_input_global_wrapper_stencil.26","dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325.b"], + ["fexp_1326.out","dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328.a"], + ["self.in1_hw_input_global_wrapper_stencil.27","dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328.b"], + ["fexp_1329.out","dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331.a"], + ["self.in1_hw_input_global_wrapper_stencil.28","dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331.b"], + ["fexp_1332.out","dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334.a"], + ["self.in1_hw_input_global_wrapper_stencil.29","dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334.b"], + ["fexp_1335.out","dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337.a"], + ["self.in1_hw_input_global_wrapper_stencil.30","dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337.b"], + ["fexp_1338.out","dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340.a"], + ["self.in1_hw_input_global_wrapper_stencil.31","dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340.b"], + ["fexp_1341.out","dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343.a"], + ["self.in1_hw_input_global_wrapper_stencil.32","dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343.b"], + ["fexp_1344.out","dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346.a"], + ["self.in1_hw_input_global_wrapper_stencil.33","dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346.b"], + ["fexp_1347.out","dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349.a"], + ["self.in1_hw_input_global_wrapper_stencil.34","dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349.b"], + ["fexp_1350.out","dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352.a"], + ["self.in1_hw_input_global_wrapper_stencil.35","dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352.b"], + ["fexp_1353.out","dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355.a"], + ["self.in1_hw_input_global_wrapper_stencil.36","dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355.b"], + ["fexp_1356.out","dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358.a"], + ["self.in1_hw_input_global_wrapper_stencil.37","dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358.b"], + ["fexp_1359.out","dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361.a"], + ["self.in1_hw_input_global_wrapper_stencil.38","dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361.b"], + ["fexp_1362.out","dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364.a"], + ["self.in1_hw_input_global_wrapper_stencil.39","dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364.b"], + ["fexp_1365.out","dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367.a"], + ["self.in1_hw_input_global_wrapper_stencil.40","dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367.b"], + ["fexp_1368.out","dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370.a"], + ["self.in1_hw_input_global_wrapper_stencil.41","dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370.b"], + ["fexp_1371.out","dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373.a"], + ["self.in1_hw_input_global_wrapper_stencil.42","dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373.b"], + ["fexp_1374.out","dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376.a"], + ["self.in1_hw_input_global_wrapper_stencil.43","dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376.b"], + ["fexp_1377.out","dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379.a"], + ["self.in1_hw_input_global_wrapper_stencil.44","dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379.b"], + ["fexp_1380.out","dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382.a"], + ["self.in1_hw_input_global_wrapper_stencil.45","dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_10_1235_1260.a"], + ["fconst-1__1235$8.out","dwfp_mul_blur_d_stencil_10_1235_1260.b"], + ["fexp_1260.in","dwfp_mul_blur_d_stencil_10_1235_1260.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_11_1235_1263.a"], + ["fconst-1__1235$9.out","dwfp_mul_blur_d_stencil_11_1235_1263.b"], + ["fexp_1263.in","dwfp_mul_blur_d_stencil_11_1235_1263.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_12_1235_1266.a"], + ["fconst-1__1235$10.out","dwfp_mul_blur_d_stencil_12_1235_1266.b"], + ["fexp_1266.in","dwfp_mul_blur_d_stencil_12_1235_1266.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_13_1235_1269.a"], + ["fconst-1__1235$11.out","dwfp_mul_blur_d_stencil_13_1235_1269.b"], + ["fexp_1269.in","dwfp_mul_blur_d_stencil_13_1235_1269.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_14_1235_1272.a"], + ["fconst-1__1235$12.out","dwfp_mul_blur_d_stencil_14_1235_1272.b"], + ["fexp_1272.in","dwfp_mul_blur_d_stencil_14_1235_1272.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_15_1235_1275.a"], + ["fconst-1__1235$13.out","dwfp_mul_blur_d_stencil_15_1235_1275.b"], + ["fexp_1275.in","dwfp_mul_blur_d_stencil_15_1235_1275.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_16_1235_1278.a"], + ["fconst-1__1235$14.out","dwfp_mul_blur_d_stencil_16_1235_1278.b"], + ["fexp_1278.in","dwfp_mul_blur_d_stencil_16_1235_1278.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_17_1235_1281.a"], + ["fconst-1__1235$15.out","dwfp_mul_blur_d_stencil_17_1235_1281.b"], + ["fexp_1281.in","dwfp_mul_blur_d_stencil_17_1235_1281.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_18_1235_1284.a"], + ["fconst-1__1235$16.out","dwfp_mul_blur_d_stencil_18_1235_1284.b"], + ["fexp_1284.in","dwfp_mul_blur_d_stencil_18_1235_1284.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_19_1235_1287.a"], + ["fconst-1__1235$17.out","dwfp_mul_blur_d_stencil_19_1235_1287.b"], + ["fexp_1287.in","dwfp_mul_blur_d_stencil_19_1235_1287.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_20_1235_1290.a"], + ["fconst-1__1235$18.out","dwfp_mul_blur_d_stencil_20_1235_1290.b"], + ["fexp_1290.in","dwfp_mul_blur_d_stencil_20_1235_1290.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_21_1235_1293.a"], + ["fconst-1__1235$19.out","dwfp_mul_blur_d_stencil_21_1235_1293.b"], + ["fexp_1293.in","dwfp_mul_blur_d_stencil_21_1235_1293.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_22_1235_1296.a"], + ["fconst-1__1235$20.out","dwfp_mul_blur_d_stencil_22_1235_1296.b"], + ["fexp_1296.in","dwfp_mul_blur_d_stencil_22_1235_1296.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_23_1235_1299.a"], + ["fconst-1__1235$21.out","dwfp_mul_blur_d_stencil_23_1235_1299.b"], + ["fexp_1299.in","dwfp_mul_blur_d_stencil_23_1235_1299.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_24_1235_1302.a"], + ["fconst-1__1235$22.out","dwfp_mul_blur_d_stencil_24_1235_1302.b"], + ["fexp_1302.in","dwfp_mul_blur_d_stencil_24_1235_1302.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_25_1235_1305.a"], + ["fconst-1__1235$23.out","dwfp_mul_blur_d_stencil_25_1235_1305.b"], + ["fexp_1305.in","dwfp_mul_blur_d_stencil_25_1235_1305.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_26_1235_1308.a"], + ["fconst-1__1235$24.out","dwfp_mul_blur_d_stencil_26_1235_1308.b"], + ["fexp_1308.in","dwfp_mul_blur_d_stencil_26_1235_1308.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_27_1235_1311.a"], + ["fconst-1__1235$25.out","dwfp_mul_blur_d_stencil_27_1235_1311.b"], + ["fexp_1311.in","dwfp_mul_blur_d_stencil_27_1235_1311.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_28_1235_1314.a"], + ["fconst-1__1235$26.out","dwfp_mul_blur_d_stencil_28_1235_1314.b"], + ["fexp_1314.in","dwfp_mul_blur_d_stencil_28_1235_1314.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_29_1235_1317.a"], + ["fconst-1__1235$27.out","dwfp_mul_blur_d_stencil_29_1235_1317.b"], + ["fexp_1317.in","dwfp_mul_blur_d_stencil_29_1235_1317.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_2_1235_1236.a"], + ["fconst-1__1235.out","dwfp_mul_blur_d_stencil_2_1235_1236.b"], + ["fexp_1236.in","dwfp_mul_blur_d_stencil_2_1235_1236.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_30_1235_1320.a"], + ["fconst-1__1235$28.out","dwfp_mul_blur_d_stencil_30_1235_1320.b"], + ["fexp_1320.in","dwfp_mul_blur_d_stencil_30_1235_1320.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_31_1235_1323.a"], + ["fconst-1__1235$29.out","dwfp_mul_blur_d_stencil_31_1235_1323.b"], + ["fexp_1323.in","dwfp_mul_blur_d_stencil_31_1235_1323.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_32_1235_1326.a"], + ["fconst-1__1235$30.out","dwfp_mul_blur_d_stencil_32_1235_1326.b"], + ["fexp_1326.in","dwfp_mul_blur_d_stencil_32_1235_1326.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_33_1235_1329.a"], + ["fconst-1__1235$31.out","dwfp_mul_blur_d_stencil_33_1235_1329.b"], + ["fexp_1329.in","dwfp_mul_blur_d_stencil_33_1235_1329.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_34_1235_1332.a"], + ["fconst-1__1235$32.out","dwfp_mul_blur_d_stencil_34_1235_1332.b"], + ["fexp_1332.in","dwfp_mul_blur_d_stencil_34_1235_1332.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_35_1235_1335.a"], + ["fconst-1__1235$33.out","dwfp_mul_blur_d_stencil_35_1235_1335.b"], + ["fexp_1335.in","dwfp_mul_blur_d_stencil_35_1235_1335.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_36_1235_1338.a"], + ["fconst-1__1235$34.out","dwfp_mul_blur_d_stencil_36_1235_1338.b"], + ["fexp_1338.in","dwfp_mul_blur_d_stencil_36_1235_1338.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_37_1235_1341.a"], + ["fconst-1__1235$35.out","dwfp_mul_blur_d_stencil_37_1235_1341.b"], + ["fexp_1341.in","dwfp_mul_blur_d_stencil_37_1235_1341.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_38_1235_1344.a"], + ["fconst-1__1235$36.out","dwfp_mul_blur_d_stencil_38_1235_1344.b"], + ["fexp_1344.in","dwfp_mul_blur_d_stencil_38_1235_1344.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_39_1235_1347.a"], + ["fconst-1__1235$37.out","dwfp_mul_blur_d_stencil_39_1235_1347.b"], + ["fexp_1347.in","dwfp_mul_blur_d_stencil_39_1235_1347.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_3_1235_1239.a"], + ["fconst-1__1235$1.out","dwfp_mul_blur_d_stencil_3_1235_1239.b"], + ["fexp_1239.in","dwfp_mul_blur_d_stencil_3_1235_1239.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_40_1235_1350.a"], + ["fconst-1__1235$38.out","dwfp_mul_blur_d_stencil_40_1235_1350.b"], + ["fexp_1350.in","dwfp_mul_blur_d_stencil_40_1235_1350.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_41_1235_1353.a"], + ["fconst-1__1235$39.out","dwfp_mul_blur_d_stencil_41_1235_1353.b"], + ["fexp_1353.in","dwfp_mul_blur_d_stencil_41_1235_1353.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_42_1235_1356.a"], + ["fconst-1__1235$40.out","dwfp_mul_blur_d_stencil_42_1235_1356.b"], + ["fexp_1356.in","dwfp_mul_blur_d_stencil_42_1235_1356.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_43_1235_1359.a"], + ["fconst-1__1235$41.out","dwfp_mul_blur_d_stencil_43_1235_1359.b"], + ["fexp_1359.in","dwfp_mul_blur_d_stencil_43_1235_1359.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_44_1235_1362.a"], + ["fconst-1__1235$42.out","dwfp_mul_blur_d_stencil_44_1235_1362.b"], + ["fexp_1362.in","dwfp_mul_blur_d_stencil_44_1235_1362.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_45_1235_1365.a"], + ["fconst-1__1235$43.out","dwfp_mul_blur_d_stencil_45_1235_1365.b"], + ["fexp_1365.in","dwfp_mul_blur_d_stencil_45_1235_1365.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_46_1235_1368.a"], + ["fconst-1__1235$44.out","dwfp_mul_blur_d_stencil_46_1235_1368.b"], + ["fexp_1368.in","dwfp_mul_blur_d_stencil_46_1235_1368.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_47_1235_1371.a"], + ["fconst-1__1235$45.out","dwfp_mul_blur_d_stencil_47_1235_1371.b"], + ["fexp_1371.in","dwfp_mul_blur_d_stencil_47_1235_1371.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_48_1235_1374.a"], + ["fconst-1__1235$46.out","dwfp_mul_blur_d_stencil_48_1235_1374.b"], + ["fexp_1374.in","dwfp_mul_blur_d_stencil_48_1235_1374.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_49_1235_1377.a"], + ["fconst-1__1235$47.out","dwfp_mul_blur_d_stencil_49_1235_1377.b"], + ["fexp_1377.in","dwfp_mul_blur_d_stencil_49_1235_1377.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_4_1235_1242.a"], + ["fconst-1__1235$2.out","dwfp_mul_blur_d_stencil_4_1235_1242.b"], + ["fexp_1242.in","dwfp_mul_blur_d_stencil_4_1235_1242.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_50_1235_1380.a"], + ["fconst-1__1235$48.out","dwfp_mul_blur_d_stencil_50_1235_1380.b"], + ["fexp_1380.in","dwfp_mul_blur_d_stencil_50_1235_1380.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_5_1235_1245.a"], + ["fconst-1__1235$3.out","dwfp_mul_blur_d_stencil_5_1235_1245.b"], + ["fexp_1245.in","dwfp_mul_blur_d_stencil_5_1235_1245.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_6_1235_1248.a"], + ["fconst-1__1235$4.out","dwfp_mul_blur_d_stencil_6_1235_1248.b"], + ["fexp_1248.in","dwfp_mul_blur_d_stencil_6_1235_1248.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_7_1235_1251.a"], + ["fconst-1__1235$5.out","dwfp_mul_blur_d_stencil_7_1235_1251.b"], + ["fexp_1251.in","dwfp_mul_blur_d_stencil_7_1235_1251.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_8_1235_1254.a"], + ["fconst-1__1235$6.out","dwfp_mul_blur_d_stencil_8_1235_1254.b"], + ["fexp_1254.in","dwfp_mul_blur_d_stencil_8_1235_1254.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_9_1235_1257.a"], + ["fconst-1__1235$7.out","dwfp_mul_blur_d_stencil_9_1235_1257.b"], + ["fexp_1257.in","dwfp_mul_blur_d_stencil_9_1235_1257.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_1942_2134_2135":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1945_2133_2134":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1948_2132_2133":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1951_2131_2132":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1954_2130_2131":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1957_2129_2130":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1960_2128_2129":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1963_2127_2128":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1966_2126_2127":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1969_2125_2126":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1972_2124_2125":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1975_2123_2124":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1978_2122_2123":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1981_2121_2122":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1984_2120_2121":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1987_2119_2120":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1990_2118_2119":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1993_2117_2118":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1996_2116_2117":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1999_2115_2116":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2002_2114_2115":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2005_2113_2114":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2008_2112_2113":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2011_2111_2112":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2014_2110_2111":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2017_2109_2110":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2020_2108_2109":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2023_2107_2108":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2026_2106_2107":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2029_2105_2106":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2032_2104_2105":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2035_2103_2104":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2038_2102_2103":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2041_2101_2102":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2044_2100_2101":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2047_2099_2100":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2050_2098_2099":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2053_2097_2098":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2056_2096_2097":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2059_2095_2096":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2062_2094_2095":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2065_2093_2094":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2068_2092_2093":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2071_2091_2092":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2074_2090_2091":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2077_2089_2090":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2080_2088_2089":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2083_2087_2088":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_2_2086_2087":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_51_1939_1940":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_52_1939_1943":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_53_1939_1946":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_54_1939_1949":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_55_1939_1952":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_56_1939_1955":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_57_1939_1958":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_58_1939_1961":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_59_1939_1964":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_60_1939_1967":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_61_1939_1970":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_62_1939_1973":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_63_1939_1976":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_64_1939_1979":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_65_1939_1982":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_66_1939_1985":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_67_1939_1988":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_68_1939_1991":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_69_1939_1994":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_70_1939_1997":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_71_1939_2000":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_72_1939_2003":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_73_1939_2006":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_74_1939_2009":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_75_1939_2012":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_76_1939_2015":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_77_1939_2018":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_78_1939_2021":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_79_1939_2024":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_80_1939_2027":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_81_1939_2030":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_82_1939_2033":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_83_1939_2036":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_84_1939_2039":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_85_1939_2042":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_86_1939_2045":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_87_1939_2048":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_88_1939_2051":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_89_1939_2054":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_90_1939_2057":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_91_1939_2060":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_92_1939_2063":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_93_1939_2066":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_94_1939_2069":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_95_1939_2072":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_96_1939_2075":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_97_1939_2078":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_98_1939_2081":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_99_1939_2084":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1939":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1940":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1943":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1946":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1949":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1952":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1955":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1958":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1961":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1964":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1967":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1970":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1973":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1976":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1979":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1982":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1985":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1988":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1991":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1994":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1997":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2000":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2003":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2006":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2009":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2012":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2015":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2018":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2021":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2024":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2027":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2030":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2033":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2036":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2039":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2042":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2045":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2048":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2051":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2054":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2057":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2060":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2063":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2066":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2069":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2072":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2075":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2078":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2081":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2084":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942.z","dwfp_add_1942_2134_2135.a"], + ["dwfp_add_1945_2133_2134.z","dwfp_add_1942_2134_2135.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_1942_2134_2135.z"], + ["dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945.z","dwfp_add_1945_2133_2134.a"], + ["dwfp_add_1948_2132_2133.z","dwfp_add_1945_2133_2134.b"], + ["dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948.z","dwfp_add_1948_2132_2133.a"], + ["dwfp_add_1951_2131_2132.z","dwfp_add_1948_2132_2133.b"], + ["dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951.z","dwfp_add_1951_2131_2132.a"], + ["dwfp_add_1954_2130_2131.z","dwfp_add_1951_2131_2132.b"], + ["dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954.z","dwfp_add_1954_2130_2131.a"], + ["dwfp_add_1957_2129_2130.z","dwfp_add_1954_2130_2131.b"], + ["dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957.z","dwfp_add_1957_2129_2130.a"], + ["dwfp_add_1960_2128_2129.z","dwfp_add_1957_2129_2130.b"], + ["dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960.z","dwfp_add_1960_2128_2129.a"], + ["dwfp_add_1963_2127_2128.z","dwfp_add_1960_2128_2129.b"], + ["dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963.z","dwfp_add_1963_2127_2128.a"], + ["dwfp_add_1966_2126_2127.z","dwfp_add_1963_2127_2128.b"], + ["dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966.z","dwfp_add_1966_2126_2127.a"], + ["dwfp_add_1969_2125_2126.z","dwfp_add_1966_2126_2127.b"], + ["dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969.z","dwfp_add_1969_2125_2126.a"], + ["dwfp_add_1972_2124_2125.z","dwfp_add_1969_2125_2126.b"], + ["dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972.z","dwfp_add_1972_2124_2125.a"], + ["dwfp_add_1975_2123_2124.z","dwfp_add_1972_2124_2125.b"], + ["dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975.z","dwfp_add_1975_2123_2124.a"], + ["dwfp_add_1978_2122_2123.z","dwfp_add_1975_2123_2124.b"], + ["dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978.z","dwfp_add_1978_2122_2123.a"], + ["dwfp_add_1981_2121_2122.z","dwfp_add_1978_2122_2123.b"], + ["dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981.z","dwfp_add_1981_2121_2122.a"], + ["dwfp_add_1984_2120_2121.z","dwfp_add_1981_2121_2122.b"], + ["dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984.z","dwfp_add_1984_2120_2121.a"], + ["dwfp_add_1987_2119_2120.z","dwfp_add_1984_2120_2121.b"], + ["dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987.z","dwfp_add_1987_2119_2120.a"], + ["dwfp_add_1990_2118_2119.z","dwfp_add_1987_2119_2120.b"], + ["dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990.z","dwfp_add_1990_2118_2119.a"], + ["dwfp_add_1993_2117_2118.z","dwfp_add_1990_2118_2119.b"], + ["dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993.z","dwfp_add_1993_2117_2118.a"], + ["dwfp_add_1996_2116_2117.z","dwfp_add_1993_2117_2118.b"], + ["dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996.z","dwfp_add_1996_2116_2117.a"], + ["dwfp_add_1999_2115_2116.z","dwfp_add_1996_2116_2117.b"], + ["dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999.z","dwfp_add_1999_2115_2116.a"], + ["dwfp_add_2002_2114_2115.z","dwfp_add_1999_2115_2116.b"], + ["dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002.z","dwfp_add_2002_2114_2115.a"], + ["dwfp_add_2005_2113_2114.z","dwfp_add_2002_2114_2115.b"], + ["dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005.z","dwfp_add_2005_2113_2114.a"], + ["dwfp_add_2008_2112_2113.z","dwfp_add_2005_2113_2114.b"], + ["dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008.z","dwfp_add_2008_2112_2113.a"], + ["dwfp_add_2011_2111_2112.z","dwfp_add_2008_2112_2113.b"], + ["dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011.z","dwfp_add_2011_2111_2112.a"], + ["dwfp_add_2014_2110_2111.z","dwfp_add_2011_2111_2112.b"], + ["dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014.z","dwfp_add_2014_2110_2111.a"], + ["dwfp_add_2017_2109_2110.z","dwfp_add_2014_2110_2111.b"], + ["dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017.z","dwfp_add_2017_2109_2110.a"], + ["dwfp_add_2020_2108_2109.z","dwfp_add_2017_2109_2110.b"], + ["dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020.z","dwfp_add_2020_2108_2109.a"], + ["dwfp_add_2023_2107_2108.z","dwfp_add_2020_2108_2109.b"], + ["dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023.z","dwfp_add_2023_2107_2108.a"], + ["dwfp_add_2026_2106_2107.z","dwfp_add_2023_2107_2108.b"], + ["dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026.z","dwfp_add_2026_2106_2107.a"], + ["dwfp_add_2029_2105_2106.z","dwfp_add_2026_2106_2107.b"], + ["dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029.z","dwfp_add_2029_2105_2106.a"], + ["dwfp_add_2032_2104_2105.z","dwfp_add_2029_2105_2106.b"], + ["dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032.z","dwfp_add_2032_2104_2105.a"], + ["dwfp_add_2035_2103_2104.z","dwfp_add_2032_2104_2105.b"], + ["dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035.z","dwfp_add_2035_2103_2104.a"], + ["dwfp_add_2038_2102_2103.z","dwfp_add_2035_2103_2104.b"], + ["dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038.z","dwfp_add_2038_2102_2103.a"], + ["dwfp_add_2041_2101_2102.z","dwfp_add_2038_2102_2103.b"], + ["dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041.z","dwfp_add_2041_2101_2102.a"], + ["dwfp_add_2044_2100_2101.z","dwfp_add_2041_2101_2102.b"], + ["dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044.z","dwfp_add_2044_2100_2101.a"], + ["dwfp_add_2047_2099_2100.z","dwfp_add_2044_2100_2101.b"], + ["dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047.z","dwfp_add_2047_2099_2100.a"], + ["dwfp_add_2050_2098_2099.z","dwfp_add_2047_2099_2100.b"], + ["dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050.z","dwfp_add_2050_2098_2099.a"], + ["dwfp_add_2053_2097_2098.z","dwfp_add_2050_2098_2099.b"], + ["dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053.z","dwfp_add_2053_2097_2098.a"], + ["dwfp_add_2056_2096_2097.z","dwfp_add_2053_2097_2098.b"], + ["dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056.z","dwfp_add_2056_2096_2097.a"], + ["dwfp_add_2059_2095_2096.z","dwfp_add_2056_2096_2097.b"], + ["dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059.z","dwfp_add_2059_2095_2096.a"], + ["dwfp_add_2062_2094_2095.z","dwfp_add_2059_2095_2096.b"], + ["dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062.z","dwfp_add_2062_2094_2095.a"], + ["dwfp_add_2065_2093_2094.z","dwfp_add_2062_2094_2095.b"], + ["dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065.z","dwfp_add_2065_2093_2094.a"], + ["dwfp_add_2068_2092_2093.z","dwfp_add_2065_2093_2094.b"], + ["dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068.z","dwfp_add_2068_2092_2093.a"], + ["dwfp_add_2071_2091_2092.z","dwfp_add_2068_2092_2093.b"], + ["dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071.z","dwfp_add_2071_2091_2092.a"], + ["dwfp_add_2074_2090_2091.z","dwfp_add_2071_2091_2092.b"], + ["dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074.z","dwfp_add_2074_2090_2091.a"], + ["dwfp_add_2077_2089_2090.z","dwfp_add_2074_2090_2091.b"], + ["dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077.z","dwfp_add_2077_2089_2090.a"], + ["dwfp_add_2080_2088_2089.z","dwfp_add_2077_2089_2090.b"], + ["dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080.z","dwfp_add_2080_2088_2089.a"], + ["dwfp_add_2083_2087_2088.z","dwfp_add_2080_2088_2089.b"], + ["dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083.z","dwfp_add_2083_2087_2088.a"], + ["dwfp_add_non_local_means_sum_stencil_2_2086_2087.z","dwfp_add_2083_2087_2088.b"], + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_2_2086_2087.a"], + ["dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086.z","dwfp_add_non_local_means_sum_stencil_2_2086_2087.b"], + ["fexp_1940.out","dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942.a"], + ["self.in1_hw_input_global_wrapper_stencil.5","dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942.b"], + ["fexp_1943.out","dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945.a"], + ["self.in1_hw_input_global_wrapper_stencil.6","dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945.b"], + ["fexp_1946.out","dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948.a"], + ["self.in1_hw_input_global_wrapper_stencil.7","dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948.b"], + ["fexp_1949.out","dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951.a"], + ["self.in1_hw_input_global_wrapper_stencil.8","dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951.b"], + ["fexp_1952.out","dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954.a"], + ["self.in1_hw_input_global_wrapper_stencil.9","dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954.b"], + ["fexp_1955.out","dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957.a"], + ["self.in1_hw_input_global_wrapper_stencil.10","dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957.b"], + ["fexp_1958.out","dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960.a"], + ["self.in1_hw_input_global_wrapper_stencil.11","dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960.b"], + ["fexp_1961.out","dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963.a"], + ["self.in1_hw_input_global_wrapper_stencil.12","dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963.b"], + ["fexp_1964.out","dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966.a"], + ["self.in1_hw_input_global_wrapper_stencil.13","dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966.b"], + ["fexp_1967.out","dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969.a"], + ["self.in1_hw_input_global_wrapper_stencil.14","dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969.b"], + ["fexp_1970.out","dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972.a"], + ["self.in1_hw_input_global_wrapper_stencil.15","dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972.b"], + ["fexp_1973.out","dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975.a"], + ["self.in1_hw_input_global_wrapper_stencil.16","dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975.b"], + ["fexp_1976.out","dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978.a"], + ["self.in1_hw_input_global_wrapper_stencil.17","dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978.b"], + ["fexp_1979.out","dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981.a"], + ["self.in1_hw_input_global_wrapper_stencil.18","dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981.b"], + ["fexp_1982.out","dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984.a"], + ["self.in1_hw_input_global_wrapper_stencil.19","dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984.b"], + ["fexp_1985.out","dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987.a"], + ["self.in1_hw_input_global_wrapper_stencil.20","dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987.b"], + ["fexp_1988.out","dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990.a"], + ["self.in1_hw_input_global_wrapper_stencil.21","dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990.b"], + ["fexp_1991.out","dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993.a"], + ["self.in1_hw_input_global_wrapper_stencil.22","dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993.b"], + ["fexp_1994.out","dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996.a"], + ["self.in1_hw_input_global_wrapper_stencil.23","dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996.b"], + ["fexp_1997.out","dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999.a"], + ["self.in1_hw_input_global_wrapper_stencil.24","dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999.b"], + ["fexp_2000.out","dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002.a"], + ["self.in1_hw_input_global_wrapper_stencil.25","dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002.b"], + ["fexp_2003.out","dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005.a"], + ["self.in1_hw_input_global_wrapper_stencil.26","dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005.b"], + ["fexp_2006.out","dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008.a"], + ["self.in1_hw_input_global_wrapper_stencil.27","dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008.b"], + ["fexp_2009.out","dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011.a"], + ["self.in1_hw_input_global_wrapper_stencil.28","dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011.b"], + ["fexp_2012.out","dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014.a"], + ["self.in1_hw_input_global_wrapper_stencil.29","dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014.b"], + ["fexp_2015.out","dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017.a"], + ["self.in1_hw_input_global_wrapper_stencil.30","dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017.b"], + ["fexp_2018.out","dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020.a"], + ["self.in1_hw_input_global_wrapper_stencil.31","dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020.b"], + ["fexp_2021.out","dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023.a"], + ["self.in1_hw_input_global_wrapper_stencil.32","dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023.b"], + ["fexp_2024.out","dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026.a"], + ["self.in1_hw_input_global_wrapper_stencil.33","dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026.b"], + ["fexp_2027.out","dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029.a"], + ["self.in1_hw_input_global_wrapper_stencil.34","dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029.b"], + ["fexp_2030.out","dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032.a"], + ["self.in1_hw_input_global_wrapper_stencil.35","dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032.b"], + ["fexp_2033.out","dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035.a"], + ["self.in1_hw_input_global_wrapper_stencil.36","dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035.b"], + ["fexp_2036.out","dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038.a"], + ["self.in1_hw_input_global_wrapper_stencil.37","dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038.b"], + ["fexp_2039.out","dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041.a"], + ["self.in1_hw_input_global_wrapper_stencil.38","dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041.b"], + ["fexp_2042.out","dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044.a"], + ["self.in1_hw_input_global_wrapper_stencil.39","dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044.b"], + ["fexp_2045.out","dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047.a"], + ["self.in1_hw_input_global_wrapper_stencil.40","dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047.b"], + ["fexp_2048.out","dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050.a"], + ["self.in1_hw_input_global_wrapper_stencil.41","dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050.b"], + ["fexp_2051.out","dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053.a"], + ["self.in1_hw_input_global_wrapper_stencil.42","dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053.b"], + ["fexp_2054.out","dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056.a"], + ["self.in1_hw_input_global_wrapper_stencil.43","dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056.b"], + ["fexp_2057.out","dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059.a"], + ["self.in1_hw_input_global_wrapper_stencil.44","dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059.b"], + ["fexp_2060.out","dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062.a"], + ["self.in1_hw_input_global_wrapper_stencil.45","dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062.b"], + ["fexp_2063.out","dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065.a"], + ["self.in1_hw_input_global_wrapper_stencil.46","dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065.b"], + ["fexp_2066.out","dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068.a"], + ["self.in1_hw_input_global_wrapper_stencil.47","dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068.b"], + ["fexp_2069.out","dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071.a"], + ["self.in1_hw_input_global_wrapper_stencil.48","dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071.b"], + ["fexp_2072.out","dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074.b"], + ["fexp_2075.out","dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077.a"], + ["self.in1_hw_input_global_wrapper_stencil.1","dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077.b"], + ["fexp_2078.out","dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080.a"], + ["self.in1_hw_input_global_wrapper_stencil.2","dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080.b"], + ["fexp_2081.out","dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083.a"], + ["self.in1_hw_input_global_wrapper_stencil.3","dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083.b"], + ["fexp_2084.out","dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086.a"], + ["self.in1_hw_input_global_wrapper_stencil.4","dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_51_1939_1940.a"], + ["fconst-1__1939.out","dwfp_mul_blur_d_stencil_51_1939_1940.b"], + ["fexp_1940.in","dwfp_mul_blur_d_stencil_51_1939_1940.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_52_1939_1943.a"], + ["fconst-1__1939$1.out","dwfp_mul_blur_d_stencil_52_1939_1943.b"], + ["fexp_1943.in","dwfp_mul_blur_d_stencil_52_1939_1943.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_53_1939_1946.a"], + ["fconst-1__1939$2.out","dwfp_mul_blur_d_stencil_53_1939_1946.b"], + ["fexp_1946.in","dwfp_mul_blur_d_stencil_53_1939_1946.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_54_1939_1949.a"], + ["fconst-1__1939$3.out","dwfp_mul_blur_d_stencil_54_1939_1949.b"], + ["fexp_1949.in","dwfp_mul_blur_d_stencil_54_1939_1949.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_55_1939_1952.a"], + ["fconst-1__1939$4.out","dwfp_mul_blur_d_stencil_55_1939_1952.b"], + ["fexp_1952.in","dwfp_mul_blur_d_stencil_55_1939_1952.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_56_1939_1955.a"], + ["fconst-1__1939$5.out","dwfp_mul_blur_d_stencil_56_1939_1955.b"], + ["fexp_1955.in","dwfp_mul_blur_d_stencil_56_1939_1955.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_57_1939_1958.a"], + ["fconst-1__1939$6.out","dwfp_mul_blur_d_stencil_57_1939_1958.b"], + ["fexp_1958.in","dwfp_mul_blur_d_stencil_57_1939_1958.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_58_1939_1961.a"], + ["fconst-1__1939$7.out","dwfp_mul_blur_d_stencil_58_1939_1961.b"], + ["fexp_1961.in","dwfp_mul_blur_d_stencil_58_1939_1961.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_59_1939_1964.a"], + ["fconst-1__1939$8.out","dwfp_mul_blur_d_stencil_59_1939_1964.b"], + ["fexp_1964.in","dwfp_mul_blur_d_stencil_59_1939_1964.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_60_1939_1967.a"], + ["fconst-1__1939$9.out","dwfp_mul_blur_d_stencil_60_1939_1967.b"], + ["fexp_1967.in","dwfp_mul_blur_d_stencil_60_1939_1967.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_61_1939_1970.a"], + ["fconst-1__1939$10.out","dwfp_mul_blur_d_stencil_61_1939_1970.b"], + ["fexp_1970.in","dwfp_mul_blur_d_stencil_61_1939_1970.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_62_1939_1973.a"], + ["fconst-1__1939$11.out","dwfp_mul_blur_d_stencil_62_1939_1973.b"], + ["fexp_1973.in","dwfp_mul_blur_d_stencil_62_1939_1973.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_63_1939_1976.a"], + ["fconst-1__1939$12.out","dwfp_mul_blur_d_stencil_63_1939_1976.b"], + ["fexp_1976.in","dwfp_mul_blur_d_stencil_63_1939_1976.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_64_1939_1979.a"], + ["fconst-1__1939$13.out","dwfp_mul_blur_d_stencil_64_1939_1979.b"], + ["fexp_1979.in","dwfp_mul_blur_d_stencil_64_1939_1979.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_65_1939_1982.a"], + ["fconst-1__1939$14.out","dwfp_mul_blur_d_stencil_65_1939_1982.b"], + ["fexp_1982.in","dwfp_mul_blur_d_stencil_65_1939_1982.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_66_1939_1985.a"], + ["fconst-1__1939$15.out","dwfp_mul_blur_d_stencil_66_1939_1985.b"], + ["fexp_1985.in","dwfp_mul_blur_d_stencil_66_1939_1985.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_67_1939_1988.a"], + ["fconst-1__1939$16.out","dwfp_mul_blur_d_stencil_67_1939_1988.b"], + ["fexp_1988.in","dwfp_mul_blur_d_stencil_67_1939_1988.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_68_1939_1991.a"], + ["fconst-1__1939$17.out","dwfp_mul_blur_d_stencil_68_1939_1991.b"], + ["fexp_1991.in","dwfp_mul_blur_d_stencil_68_1939_1991.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_69_1939_1994.a"], + ["fconst-1__1939$18.out","dwfp_mul_blur_d_stencil_69_1939_1994.b"], + ["fexp_1994.in","dwfp_mul_blur_d_stencil_69_1939_1994.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_70_1939_1997.a"], + ["fconst-1__1939$19.out","dwfp_mul_blur_d_stencil_70_1939_1997.b"], + ["fexp_1997.in","dwfp_mul_blur_d_stencil_70_1939_1997.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_71_1939_2000.a"], + ["fconst-1__1939$20.out","dwfp_mul_blur_d_stencil_71_1939_2000.b"], + ["fexp_2000.in","dwfp_mul_blur_d_stencil_71_1939_2000.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_72_1939_2003.a"], + ["fconst-1__1939$21.out","dwfp_mul_blur_d_stencil_72_1939_2003.b"], + ["fexp_2003.in","dwfp_mul_blur_d_stencil_72_1939_2003.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_73_1939_2006.a"], + ["fconst-1__1939$22.out","dwfp_mul_blur_d_stencil_73_1939_2006.b"], + ["fexp_2006.in","dwfp_mul_blur_d_stencil_73_1939_2006.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_74_1939_2009.a"], + ["fconst-1__1939$23.out","dwfp_mul_blur_d_stencil_74_1939_2009.b"], + ["fexp_2009.in","dwfp_mul_blur_d_stencil_74_1939_2009.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_75_1939_2012.a"], + ["fconst-1__1939$24.out","dwfp_mul_blur_d_stencil_75_1939_2012.b"], + ["fexp_2012.in","dwfp_mul_blur_d_stencil_75_1939_2012.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_76_1939_2015.a"], + ["fconst-1__1939$25.out","dwfp_mul_blur_d_stencil_76_1939_2015.b"], + ["fexp_2015.in","dwfp_mul_blur_d_stencil_76_1939_2015.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_77_1939_2018.a"], + ["fconst-1__1939$26.out","dwfp_mul_blur_d_stencil_77_1939_2018.b"], + ["fexp_2018.in","dwfp_mul_blur_d_stencil_77_1939_2018.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_78_1939_2021.a"], + ["fconst-1__1939$27.out","dwfp_mul_blur_d_stencil_78_1939_2021.b"], + ["fexp_2021.in","dwfp_mul_blur_d_stencil_78_1939_2021.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_79_1939_2024.a"], + ["fconst-1__1939$28.out","dwfp_mul_blur_d_stencil_79_1939_2024.b"], + ["fexp_2024.in","dwfp_mul_blur_d_stencil_79_1939_2024.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_80_1939_2027.a"], + ["fconst-1__1939$29.out","dwfp_mul_blur_d_stencil_80_1939_2027.b"], + ["fexp_2027.in","dwfp_mul_blur_d_stencil_80_1939_2027.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_81_1939_2030.a"], + ["fconst-1__1939$30.out","dwfp_mul_blur_d_stencil_81_1939_2030.b"], + ["fexp_2030.in","dwfp_mul_blur_d_stencil_81_1939_2030.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_82_1939_2033.a"], + ["fconst-1__1939$31.out","dwfp_mul_blur_d_stencil_82_1939_2033.b"], + ["fexp_2033.in","dwfp_mul_blur_d_stencil_82_1939_2033.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_83_1939_2036.a"], + ["fconst-1__1939$32.out","dwfp_mul_blur_d_stencil_83_1939_2036.b"], + ["fexp_2036.in","dwfp_mul_blur_d_stencil_83_1939_2036.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_84_1939_2039.a"], + ["fconst-1__1939$33.out","dwfp_mul_blur_d_stencil_84_1939_2039.b"], + ["fexp_2039.in","dwfp_mul_blur_d_stencil_84_1939_2039.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_85_1939_2042.a"], + ["fconst-1__1939$34.out","dwfp_mul_blur_d_stencil_85_1939_2042.b"], + ["fexp_2042.in","dwfp_mul_blur_d_stencil_85_1939_2042.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_86_1939_2045.a"], + ["fconst-1__1939$35.out","dwfp_mul_blur_d_stencil_86_1939_2045.b"], + ["fexp_2045.in","dwfp_mul_blur_d_stencil_86_1939_2045.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_87_1939_2048.a"], + ["fconst-1__1939$36.out","dwfp_mul_blur_d_stencil_87_1939_2048.b"], + ["fexp_2048.in","dwfp_mul_blur_d_stencil_87_1939_2048.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_88_1939_2051.a"], + ["fconst-1__1939$37.out","dwfp_mul_blur_d_stencil_88_1939_2051.b"], + ["fexp_2051.in","dwfp_mul_blur_d_stencil_88_1939_2051.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_89_1939_2054.a"], + ["fconst-1__1939$38.out","dwfp_mul_blur_d_stencil_89_1939_2054.b"], + ["fexp_2054.in","dwfp_mul_blur_d_stencil_89_1939_2054.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_90_1939_2057.a"], + ["fconst-1__1939$39.out","dwfp_mul_blur_d_stencil_90_1939_2057.b"], + ["fexp_2057.in","dwfp_mul_blur_d_stencil_90_1939_2057.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_91_1939_2060.a"], + ["fconst-1__1939$40.out","dwfp_mul_blur_d_stencil_91_1939_2060.b"], + ["fexp_2060.in","dwfp_mul_blur_d_stencil_91_1939_2060.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_92_1939_2063.a"], + ["fconst-1__1939$41.out","dwfp_mul_blur_d_stencil_92_1939_2063.b"], + ["fexp_2063.in","dwfp_mul_blur_d_stencil_92_1939_2063.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_93_1939_2066.a"], + ["fconst-1__1939$42.out","dwfp_mul_blur_d_stencil_93_1939_2066.b"], + ["fexp_2066.in","dwfp_mul_blur_d_stencil_93_1939_2066.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_94_1939_2069.a"], + ["fconst-1__1939$43.out","dwfp_mul_blur_d_stencil_94_1939_2069.b"], + ["fexp_2069.in","dwfp_mul_blur_d_stencil_94_1939_2069.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_95_1939_2072.a"], + ["fconst-1__1939$44.out","dwfp_mul_blur_d_stencil_95_1939_2072.b"], + ["fexp_2072.in","dwfp_mul_blur_d_stencil_95_1939_2072.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_96_1939_2075.a"], + ["fconst-1__1939$45.out","dwfp_mul_blur_d_stencil_96_1939_2075.b"], + ["fexp_2075.in","dwfp_mul_blur_d_stencil_96_1939_2075.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_97_1939_2078.a"], + ["fconst-1__1939$46.out","dwfp_mul_blur_d_stencil_97_1939_2078.b"], + ["fexp_2078.in","dwfp_mul_blur_d_stencil_97_1939_2078.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_98_1939_2081.a"], + ["fconst-1__1939$47.out","dwfp_mul_blur_d_stencil_98_1939_2081.b"], + ["fexp_2081.in","dwfp_mul_blur_d_stencil_98_1939_2081.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_99_1939_2084.a"], + ["fconst-1__1939$48.out","dwfp_mul_blur_d_stencil_99_1939_2084.b"], + ["fexp_2084.in","dwfp_mul_blur_d_stencil_99_1939_2084.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_6":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_2646_2838_2839":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2649_2837_2838":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2652_2836_2837":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2655_2835_2836":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2658_2834_2835":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2661_2833_2834":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2664_2832_2833":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2667_2831_2832":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2670_2830_2831":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2673_2829_2830":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2676_2828_2829":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2679_2827_2828":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2682_2826_2827":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2685_2825_2826":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2688_2824_2825":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2691_2823_2824":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2694_2822_2823":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2697_2821_2822":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2700_2820_2821":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2703_2819_2820":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2706_2818_2819":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2709_2817_2818":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2712_2816_2817":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2715_2815_2816":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2718_2814_2815":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2721_2813_2814":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2724_2812_2813":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2727_2811_2812":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2730_2810_2811":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2733_2809_2810":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2736_2808_2809":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2739_2807_2808":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2742_2806_2807":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2745_2805_2806":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2748_2804_2805":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2751_2803_2804":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2754_2802_2803":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2757_2801_2802":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2760_2800_2801":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2763_2799_2800":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2766_2798_2799":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2769_2797_2798":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2772_2796_2797":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2775_2795_2796":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2778_2794_2795":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2781_2793_2794":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2784_2792_2793":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2787_2791_2792":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_3_2790_2791":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_100_2643_2644":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_101_2643_2647":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_102_2643_2650":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_103_2643_2653":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_104_2643_2656":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_105_2643_2659":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_106_2643_2662":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_107_2643_2665":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_108_2643_2668":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_109_2643_2671":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_110_2643_2674":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_111_2643_2677":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_112_2643_2680":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_113_2643_2683":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_114_2643_2686":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_115_2643_2689":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_116_2643_2692":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_117_2643_2695":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_118_2643_2698":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_119_2643_2701":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_120_2643_2704":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_121_2643_2707":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_122_2643_2710":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_123_2643_2713":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_124_2643_2716":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_125_2643_2719":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_126_2643_2722":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_127_2643_2725":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_128_2643_2728":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_129_2643_2731":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_130_2643_2734":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_131_2643_2737":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_132_2643_2740":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_133_2643_2743":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_134_2643_2746":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_135_2643_2749":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_136_2643_2752":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_137_2643_2755":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_138_2643_2758":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_139_2643_2761":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_140_2643_2764":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_141_2643_2767":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_142_2643_2770":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_143_2643_2773":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_144_2643_2776":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_145_2643_2779":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_146_2643_2782":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_147_2643_2785":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_148_2643_2788":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__2643":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_2644":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2647":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2650":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2653":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2656":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2659":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2662":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2665":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2668":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2671":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2674":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2677":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2680":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2683":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2686":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2689":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2692":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2695":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2698":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2701":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2704":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2707":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2710":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2713":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2716":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2719":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2722":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2725":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2728":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2731":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2734":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2737":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2740":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2743":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2746":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2749":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2752":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2755":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2758":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2761":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2764":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2767":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2770":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2773":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2776":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2779":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2782":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2785":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2788":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646.z","dwfp_add_2646_2838_2839.a"], + ["dwfp_add_2649_2837_2838.z","dwfp_add_2646_2838_2839.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_2646_2838_2839.z"], + ["dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649.z","dwfp_add_2649_2837_2838.a"], + ["dwfp_add_2652_2836_2837.z","dwfp_add_2649_2837_2838.b"], + ["dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652.z","dwfp_add_2652_2836_2837.a"], + ["dwfp_add_2655_2835_2836.z","dwfp_add_2652_2836_2837.b"], + ["dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655.z","dwfp_add_2655_2835_2836.a"], + ["dwfp_add_2658_2834_2835.z","dwfp_add_2655_2835_2836.b"], + ["dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658.z","dwfp_add_2658_2834_2835.a"], + ["dwfp_add_2661_2833_2834.z","dwfp_add_2658_2834_2835.b"], + ["dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661.z","dwfp_add_2661_2833_2834.a"], + ["dwfp_add_2664_2832_2833.z","dwfp_add_2661_2833_2834.b"], + ["dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664.z","dwfp_add_2664_2832_2833.a"], + ["dwfp_add_2667_2831_2832.z","dwfp_add_2664_2832_2833.b"], + ["dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667.z","dwfp_add_2667_2831_2832.a"], + ["dwfp_add_2670_2830_2831.z","dwfp_add_2667_2831_2832.b"], + ["dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670.z","dwfp_add_2670_2830_2831.a"], + ["dwfp_add_2673_2829_2830.z","dwfp_add_2670_2830_2831.b"], + ["dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673.z","dwfp_add_2673_2829_2830.a"], + ["dwfp_add_2676_2828_2829.z","dwfp_add_2673_2829_2830.b"], + ["dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676.z","dwfp_add_2676_2828_2829.a"], + ["dwfp_add_2679_2827_2828.z","dwfp_add_2676_2828_2829.b"], + ["dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679.z","dwfp_add_2679_2827_2828.a"], + ["dwfp_add_2682_2826_2827.z","dwfp_add_2679_2827_2828.b"], + ["dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682.z","dwfp_add_2682_2826_2827.a"], + ["dwfp_add_2685_2825_2826.z","dwfp_add_2682_2826_2827.b"], + ["dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685.z","dwfp_add_2685_2825_2826.a"], + ["dwfp_add_2688_2824_2825.z","dwfp_add_2685_2825_2826.b"], + ["dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688.z","dwfp_add_2688_2824_2825.a"], + ["dwfp_add_2691_2823_2824.z","dwfp_add_2688_2824_2825.b"], + ["dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691.z","dwfp_add_2691_2823_2824.a"], + ["dwfp_add_2694_2822_2823.z","dwfp_add_2691_2823_2824.b"], + ["dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694.z","dwfp_add_2694_2822_2823.a"], + ["dwfp_add_2697_2821_2822.z","dwfp_add_2694_2822_2823.b"], + ["dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697.z","dwfp_add_2697_2821_2822.a"], + ["dwfp_add_2700_2820_2821.z","dwfp_add_2697_2821_2822.b"], + ["dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700.z","dwfp_add_2700_2820_2821.a"], + ["dwfp_add_2703_2819_2820.z","dwfp_add_2700_2820_2821.b"], + ["dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703.z","dwfp_add_2703_2819_2820.a"], + ["dwfp_add_2706_2818_2819.z","dwfp_add_2703_2819_2820.b"], + ["dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706.z","dwfp_add_2706_2818_2819.a"], + ["dwfp_add_2709_2817_2818.z","dwfp_add_2706_2818_2819.b"], + ["dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709.z","dwfp_add_2709_2817_2818.a"], + ["dwfp_add_2712_2816_2817.z","dwfp_add_2709_2817_2818.b"], + ["dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712.z","dwfp_add_2712_2816_2817.a"], + ["dwfp_add_2715_2815_2816.z","dwfp_add_2712_2816_2817.b"], + ["dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715.z","dwfp_add_2715_2815_2816.a"], + ["dwfp_add_2718_2814_2815.z","dwfp_add_2715_2815_2816.b"], + ["dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718.z","dwfp_add_2718_2814_2815.a"], + ["dwfp_add_2721_2813_2814.z","dwfp_add_2718_2814_2815.b"], + ["dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721.z","dwfp_add_2721_2813_2814.a"], + ["dwfp_add_2724_2812_2813.z","dwfp_add_2721_2813_2814.b"], + ["dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724.z","dwfp_add_2724_2812_2813.a"], + ["dwfp_add_2727_2811_2812.z","dwfp_add_2724_2812_2813.b"], + ["dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727.z","dwfp_add_2727_2811_2812.a"], + ["dwfp_add_2730_2810_2811.z","dwfp_add_2727_2811_2812.b"], + ["dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730.z","dwfp_add_2730_2810_2811.a"], + ["dwfp_add_2733_2809_2810.z","dwfp_add_2730_2810_2811.b"], + ["dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733.z","dwfp_add_2733_2809_2810.a"], + ["dwfp_add_2736_2808_2809.z","dwfp_add_2733_2809_2810.b"], + ["dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736.z","dwfp_add_2736_2808_2809.a"], + ["dwfp_add_2739_2807_2808.z","dwfp_add_2736_2808_2809.b"], + ["dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739.z","dwfp_add_2739_2807_2808.a"], + ["dwfp_add_2742_2806_2807.z","dwfp_add_2739_2807_2808.b"], + ["dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742.z","dwfp_add_2742_2806_2807.a"], + ["dwfp_add_2745_2805_2806.z","dwfp_add_2742_2806_2807.b"], + ["dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745.z","dwfp_add_2745_2805_2806.a"], + ["dwfp_add_2748_2804_2805.z","dwfp_add_2745_2805_2806.b"], + ["dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748.z","dwfp_add_2748_2804_2805.a"], + ["dwfp_add_2751_2803_2804.z","dwfp_add_2748_2804_2805.b"], + ["dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751.z","dwfp_add_2751_2803_2804.a"], + ["dwfp_add_2754_2802_2803.z","dwfp_add_2751_2803_2804.b"], + ["dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754.z","dwfp_add_2754_2802_2803.a"], + ["dwfp_add_2757_2801_2802.z","dwfp_add_2754_2802_2803.b"], + ["dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757.z","dwfp_add_2757_2801_2802.a"], + ["dwfp_add_2760_2800_2801.z","dwfp_add_2757_2801_2802.b"], + ["dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760.z","dwfp_add_2760_2800_2801.a"], + ["dwfp_add_2763_2799_2800.z","dwfp_add_2760_2800_2801.b"], + ["dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763.z","dwfp_add_2763_2799_2800.a"], + ["dwfp_add_2766_2798_2799.z","dwfp_add_2763_2799_2800.b"], + ["dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766.z","dwfp_add_2766_2798_2799.a"], + ["dwfp_add_2769_2797_2798.z","dwfp_add_2766_2798_2799.b"], + ["dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769.z","dwfp_add_2769_2797_2798.a"], + ["dwfp_add_2772_2796_2797.z","dwfp_add_2769_2797_2798.b"], + ["dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772.z","dwfp_add_2772_2796_2797.a"], + ["dwfp_add_2775_2795_2796.z","dwfp_add_2772_2796_2797.b"], + ["dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775.z","dwfp_add_2775_2795_2796.a"], + ["dwfp_add_2778_2794_2795.z","dwfp_add_2775_2795_2796.b"], + ["dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778.z","dwfp_add_2778_2794_2795.a"], + ["dwfp_add_2781_2793_2794.z","dwfp_add_2778_2794_2795.b"], + ["dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781.z","dwfp_add_2781_2793_2794.a"], + ["dwfp_add_2784_2792_2793.z","dwfp_add_2781_2793_2794.b"], + ["dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784.z","dwfp_add_2784_2792_2793.a"], + ["dwfp_add_2787_2791_2792.z","dwfp_add_2784_2792_2793.b"], + ["dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787.z","dwfp_add_2787_2791_2792.a"], + ["dwfp_add_non_local_means_sum_stencil_3_2790_2791.z","dwfp_add_2787_2791_2792.b"], + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_3_2790_2791.a"], + ["dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790.z","dwfp_add_non_local_means_sum_stencil_3_2790_2791.b"], + ["fexp_2644.out","dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646.b"], + ["fexp_2647.out","dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649.a"], + ["self.in1_hw_input_global_wrapper_stencil.1","dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649.b"], + ["fexp_2650.out","dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652.a"], + ["self.in1_hw_input_global_wrapper_stencil.2","dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652.b"], + ["fexp_2653.out","dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655.a"], + ["self.in1_hw_input_global_wrapper_stencil.3","dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655.b"], + ["fexp_2656.out","dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658.a"], + ["self.in1_hw_input_global_wrapper_stencil.4","dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658.b"], + ["fexp_2659.out","dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661.a"], + ["self.in1_hw_input_global_wrapper_stencil.5","dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661.b"], + ["fexp_2662.out","dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664.a"], + ["self.in1_hw_input_global_wrapper_stencil.6","dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664.b"], + ["fexp_2665.out","dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667.a"], + ["self.in1_hw_input_global_wrapper_stencil.7","dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667.b"], + ["fexp_2668.out","dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670.a"], + ["self.in1_hw_input_global_wrapper_stencil.8","dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670.b"], + ["fexp_2671.out","dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673.a"], + ["self.in1_hw_input_global_wrapper_stencil.9","dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673.b"], + ["fexp_2674.out","dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676.a"], + ["self.in1_hw_input_global_wrapper_stencil.10","dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676.b"], + ["fexp_2677.out","dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679.a"], + ["self.in1_hw_input_global_wrapper_stencil.11","dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679.b"], + ["fexp_2680.out","dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682.a"], + ["self.in1_hw_input_global_wrapper_stencil.12","dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682.b"], + ["fexp_2683.out","dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685.a"], + ["self.in1_hw_input_global_wrapper_stencil.13","dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685.b"], + ["fexp_2686.out","dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688.a"], + ["self.in1_hw_input_global_wrapper_stencil.14","dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688.b"], + ["fexp_2689.out","dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691.a"], + ["self.in1_hw_input_global_wrapper_stencil.15","dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691.b"], + ["fexp_2692.out","dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694.a"], + ["self.in1_hw_input_global_wrapper_stencil.16","dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694.b"], + ["fexp_2695.out","dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697.a"], + ["self.in1_hw_input_global_wrapper_stencil.17","dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697.b"], + ["fexp_2698.out","dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700.a"], + ["self.in1_hw_input_global_wrapper_stencil.18","dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700.b"], + ["fexp_2701.out","dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703.a"], + ["self.in1_hw_input_global_wrapper_stencil.19","dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703.b"], + ["fexp_2704.out","dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706.a"], + ["self.in1_hw_input_global_wrapper_stencil.20","dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706.b"], + ["fexp_2707.out","dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709.a"], + ["self.in1_hw_input_global_wrapper_stencil.21","dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709.b"], + ["fexp_2710.out","dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712.a"], + ["self.in1_hw_input_global_wrapper_stencil.22","dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712.b"], + ["fexp_2713.out","dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715.a"], + ["self.in1_hw_input_global_wrapper_stencil.23","dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715.b"], + ["fexp_2716.out","dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718.a"], + ["self.in1_hw_input_global_wrapper_stencil.24","dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718.b"], + ["fexp_2719.out","dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721.a"], + ["self.in1_hw_input_global_wrapper_stencil.25","dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721.b"], + ["fexp_2722.out","dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724.a"], + ["self.in1_hw_input_global_wrapper_stencil.26","dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724.b"], + ["fexp_2725.out","dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727.a"], + ["self.in1_hw_input_global_wrapper_stencil.27","dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727.b"], + ["fexp_2728.out","dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730.a"], + ["self.in1_hw_input_global_wrapper_stencil.28","dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730.b"], + ["fexp_2731.out","dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733.a"], + ["self.in1_hw_input_global_wrapper_stencil.29","dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733.b"], + ["fexp_2734.out","dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736.a"], + ["self.in1_hw_input_global_wrapper_stencil.30","dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736.b"], + ["fexp_2737.out","dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739.a"], + ["self.in1_hw_input_global_wrapper_stencil.31","dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739.b"], + ["fexp_2740.out","dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742.a"], + ["self.in1_hw_input_global_wrapper_stencil.32","dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742.b"], + ["fexp_2743.out","dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745.a"], + ["self.in1_hw_input_global_wrapper_stencil.33","dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745.b"], + ["fexp_2746.out","dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748.a"], + ["self.in1_hw_input_global_wrapper_stencil.34","dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748.b"], + ["fexp_2749.out","dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751.a"], + ["self.in1_hw_input_global_wrapper_stencil.35","dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751.b"], + ["fexp_2752.out","dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754.a"], + ["self.in1_hw_input_global_wrapper_stencil.36","dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754.b"], + ["fexp_2755.out","dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757.a"], + ["self.in1_hw_input_global_wrapper_stencil.37","dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757.b"], + ["fexp_2758.out","dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760.a"], + ["self.in1_hw_input_global_wrapper_stencil.38","dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760.b"], + ["fexp_2761.out","dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763.a"], + ["self.in1_hw_input_global_wrapper_stencil.39","dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763.b"], + ["fexp_2764.out","dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766.a"], + ["self.in1_hw_input_global_wrapper_stencil.40","dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766.b"], + ["fexp_2767.out","dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769.a"], + ["self.in1_hw_input_global_wrapper_stencil.41","dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769.b"], + ["fexp_2770.out","dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772.a"], + ["self.in1_hw_input_global_wrapper_stencil.42","dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772.b"], + ["fexp_2773.out","dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775.a"], + ["self.in1_hw_input_global_wrapper_stencil.43","dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775.b"], + ["fexp_2776.out","dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778.a"], + ["self.in1_hw_input_global_wrapper_stencil.44","dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778.b"], + ["fexp_2779.out","dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781.a"], + ["self.in1_hw_input_global_wrapper_stencil.45","dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781.b"], + ["fexp_2782.out","dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784.a"], + ["self.in1_hw_input_global_wrapper_stencil.46","dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784.b"], + ["fexp_2785.out","dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787.a"], + ["self.in1_hw_input_global_wrapper_stencil.47","dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787.b"], + ["fexp_2788.out","dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790.a"], + ["self.in1_hw_input_global_wrapper_stencil.48","dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_100_2643_2644.a"], + ["fconst-1__2643.out","dwfp_mul_blur_d_stencil_100_2643_2644.b"], + ["fexp_2644.in","dwfp_mul_blur_d_stencil_100_2643_2644.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_101_2643_2647.a"], + ["fconst-1__2643$1.out","dwfp_mul_blur_d_stencil_101_2643_2647.b"], + ["fexp_2647.in","dwfp_mul_blur_d_stencil_101_2643_2647.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_102_2643_2650.a"], + ["fconst-1__2643$2.out","dwfp_mul_blur_d_stencil_102_2643_2650.b"], + ["fexp_2650.in","dwfp_mul_blur_d_stencil_102_2643_2650.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_103_2643_2653.a"], + ["fconst-1__2643$3.out","dwfp_mul_blur_d_stencil_103_2643_2653.b"], + ["fexp_2653.in","dwfp_mul_blur_d_stencil_103_2643_2653.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_104_2643_2656.a"], + ["fconst-1__2643$4.out","dwfp_mul_blur_d_stencil_104_2643_2656.b"], + ["fexp_2656.in","dwfp_mul_blur_d_stencil_104_2643_2656.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_105_2643_2659.a"], + ["fconst-1__2643$5.out","dwfp_mul_blur_d_stencil_105_2643_2659.b"], + ["fexp_2659.in","dwfp_mul_blur_d_stencil_105_2643_2659.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_106_2643_2662.a"], + ["fconst-1__2643$6.out","dwfp_mul_blur_d_stencil_106_2643_2662.b"], + ["fexp_2662.in","dwfp_mul_blur_d_stencil_106_2643_2662.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_107_2643_2665.a"], + ["fconst-1__2643$7.out","dwfp_mul_blur_d_stencil_107_2643_2665.b"], + ["fexp_2665.in","dwfp_mul_blur_d_stencil_107_2643_2665.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_108_2643_2668.a"], + ["fconst-1__2643$8.out","dwfp_mul_blur_d_stencil_108_2643_2668.b"], + ["fexp_2668.in","dwfp_mul_blur_d_stencil_108_2643_2668.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_109_2643_2671.a"], + ["fconst-1__2643$9.out","dwfp_mul_blur_d_stencil_109_2643_2671.b"], + ["fexp_2671.in","dwfp_mul_blur_d_stencil_109_2643_2671.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_110_2643_2674.a"], + ["fconst-1__2643$10.out","dwfp_mul_blur_d_stencil_110_2643_2674.b"], + ["fexp_2674.in","dwfp_mul_blur_d_stencil_110_2643_2674.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_111_2643_2677.a"], + ["fconst-1__2643$11.out","dwfp_mul_blur_d_stencil_111_2643_2677.b"], + ["fexp_2677.in","dwfp_mul_blur_d_stencil_111_2643_2677.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_112_2643_2680.a"], + ["fconst-1__2643$12.out","dwfp_mul_blur_d_stencil_112_2643_2680.b"], + ["fexp_2680.in","dwfp_mul_blur_d_stencil_112_2643_2680.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_113_2643_2683.a"], + ["fconst-1__2643$13.out","dwfp_mul_blur_d_stencil_113_2643_2683.b"], + ["fexp_2683.in","dwfp_mul_blur_d_stencil_113_2643_2683.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_114_2643_2686.a"], + ["fconst-1__2643$14.out","dwfp_mul_blur_d_stencil_114_2643_2686.b"], + ["fexp_2686.in","dwfp_mul_blur_d_stencil_114_2643_2686.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_115_2643_2689.a"], + ["fconst-1__2643$15.out","dwfp_mul_blur_d_stencil_115_2643_2689.b"], + ["fexp_2689.in","dwfp_mul_blur_d_stencil_115_2643_2689.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_116_2643_2692.a"], + ["fconst-1__2643$16.out","dwfp_mul_blur_d_stencil_116_2643_2692.b"], + ["fexp_2692.in","dwfp_mul_blur_d_stencil_116_2643_2692.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_117_2643_2695.a"], + ["fconst-1__2643$17.out","dwfp_mul_blur_d_stencil_117_2643_2695.b"], + ["fexp_2695.in","dwfp_mul_blur_d_stencil_117_2643_2695.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_118_2643_2698.a"], + ["fconst-1__2643$18.out","dwfp_mul_blur_d_stencil_118_2643_2698.b"], + ["fexp_2698.in","dwfp_mul_blur_d_stencil_118_2643_2698.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_119_2643_2701.a"], + ["fconst-1__2643$19.out","dwfp_mul_blur_d_stencil_119_2643_2701.b"], + ["fexp_2701.in","dwfp_mul_blur_d_stencil_119_2643_2701.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_120_2643_2704.a"], + ["fconst-1__2643$20.out","dwfp_mul_blur_d_stencil_120_2643_2704.b"], + ["fexp_2704.in","dwfp_mul_blur_d_stencil_120_2643_2704.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_121_2643_2707.a"], + ["fconst-1__2643$21.out","dwfp_mul_blur_d_stencil_121_2643_2707.b"], + ["fexp_2707.in","dwfp_mul_blur_d_stencil_121_2643_2707.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_122_2643_2710.a"], + ["fconst-1__2643$22.out","dwfp_mul_blur_d_stencil_122_2643_2710.b"], + ["fexp_2710.in","dwfp_mul_blur_d_stencil_122_2643_2710.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_123_2643_2713.a"], + ["fconst-1__2643$23.out","dwfp_mul_blur_d_stencil_123_2643_2713.b"], + ["fexp_2713.in","dwfp_mul_blur_d_stencil_123_2643_2713.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_124_2643_2716.a"], + ["fconst-1__2643$24.out","dwfp_mul_blur_d_stencil_124_2643_2716.b"], + ["fexp_2716.in","dwfp_mul_blur_d_stencil_124_2643_2716.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_125_2643_2719.a"], + ["fconst-1__2643$25.out","dwfp_mul_blur_d_stencil_125_2643_2719.b"], + ["fexp_2719.in","dwfp_mul_blur_d_stencil_125_2643_2719.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_126_2643_2722.a"], + ["fconst-1__2643$26.out","dwfp_mul_blur_d_stencil_126_2643_2722.b"], + ["fexp_2722.in","dwfp_mul_blur_d_stencil_126_2643_2722.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_127_2643_2725.a"], + ["fconst-1__2643$27.out","dwfp_mul_blur_d_stencil_127_2643_2725.b"], + ["fexp_2725.in","dwfp_mul_blur_d_stencil_127_2643_2725.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_128_2643_2728.a"], + ["fconst-1__2643$28.out","dwfp_mul_blur_d_stencil_128_2643_2728.b"], + ["fexp_2728.in","dwfp_mul_blur_d_stencil_128_2643_2728.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_129_2643_2731.a"], + ["fconst-1__2643$29.out","dwfp_mul_blur_d_stencil_129_2643_2731.b"], + ["fexp_2731.in","dwfp_mul_blur_d_stencil_129_2643_2731.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_130_2643_2734.a"], + ["fconst-1__2643$30.out","dwfp_mul_blur_d_stencil_130_2643_2734.b"], + ["fexp_2734.in","dwfp_mul_blur_d_stencil_130_2643_2734.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_131_2643_2737.a"], + ["fconst-1__2643$31.out","dwfp_mul_blur_d_stencil_131_2643_2737.b"], + ["fexp_2737.in","dwfp_mul_blur_d_stencil_131_2643_2737.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_132_2643_2740.a"], + ["fconst-1__2643$32.out","dwfp_mul_blur_d_stencil_132_2643_2740.b"], + ["fexp_2740.in","dwfp_mul_blur_d_stencil_132_2643_2740.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_133_2643_2743.a"], + ["fconst-1__2643$33.out","dwfp_mul_blur_d_stencil_133_2643_2743.b"], + ["fexp_2743.in","dwfp_mul_blur_d_stencil_133_2643_2743.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_134_2643_2746.a"], + ["fconst-1__2643$34.out","dwfp_mul_blur_d_stencil_134_2643_2746.b"], + ["fexp_2746.in","dwfp_mul_blur_d_stencil_134_2643_2746.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_135_2643_2749.a"], + ["fconst-1__2643$35.out","dwfp_mul_blur_d_stencil_135_2643_2749.b"], + ["fexp_2749.in","dwfp_mul_blur_d_stencil_135_2643_2749.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_136_2643_2752.a"], + ["fconst-1__2643$36.out","dwfp_mul_blur_d_stencil_136_2643_2752.b"], + ["fexp_2752.in","dwfp_mul_blur_d_stencil_136_2643_2752.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_137_2643_2755.a"], + ["fconst-1__2643$37.out","dwfp_mul_blur_d_stencil_137_2643_2755.b"], + ["fexp_2755.in","dwfp_mul_blur_d_stencil_137_2643_2755.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_138_2643_2758.a"], + ["fconst-1__2643$38.out","dwfp_mul_blur_d_stencil_138_2643_2758.b"], + ["fexp_2758.in","dwfp_mul_blur_d_stencil_138_2643_2758.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_139_2643_2761.a"], + ["fconst-1__2643$39.out","dwfp_mul_blur_d_stencil_139_2643_2761.b"], + ["fexp_2761.in","dwfp_mul_blur_d_stencil_139_2643_2761.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_140_2643_2764.a"], + ["fconst-1__2643$40.out","dwfp_mul_blur_d_stencil_140_2643_2764.b"], + ["fexp_2764.in","dwfp_mul_blur_d_stencil_140_2643_2764.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_141_2643_2767.a"], + ["fconst-1__2643$41.out","dwfp_mul_blur_d_stencil_141_2643_2767.b"], + ["fexp_2767.in","dwfp_mul_blur_d_stencil_141_2643_2767.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_142_2643_2770.a"], + ["fconst-1__2643$42.out","dwfp_mul_blur_d_stencil_142_2643_2770.b"], + ["fexp_2770.in","dwfp_mul_blur_d_stencil_142_2643_2770.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_143_2643_2773.a"], + ["fconst-1__2643$43.out","dwfp_mul_blur_d_stencil_143_2643_2773.b"], + ["fexp_2773.in","dwfp_mul_blur_d_stencil_143_2643_2773.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_144_2643_2776.a"], + ["fconst-1__2643$44.out","dwfp_mul_blur_d_stencil_144_2643_2776.b"], + ["fexp_2776.in","dwfp_mul_blur_d_stencil_144_2643_2776.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_145_2643_2779.a"], + ["fconst-1__2643$45.out","dwfp_mul_blur_d_stencil_145_2643_2779.b"], + ["fexp_2779.in","dwfp_mul_blur_d_stencil_145_2643_2779.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_146_2643_2782.a"], + ["fconst-1__2643$46.out","dwfp_mul_blur_d_stencil_146_2643_2782.b"], + ["fexp_2782.in","dwfp_mul_blur_d_stencil_146_2643_2782.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_147_2643_2785.a"], + ["fconst-1__2643$47.out","dwfp_mul_blur_d_stencil_147_2643_2785.b"], + ["fexp_2785.in","dwfp_mul_blur_d_stencil_147_2643_2785.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_148_2643_2788.a"], + ["fconst-1__2643$48.out","dwfp_mul_blur_d_stencil_148_2643_2788.b"], + ["fexp_2788.in","dwfp_mul_blur_d_stencil_148_2643_2788.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_7":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_3300_3444_3445":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3302_3443_3444":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3304_3442_3443":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3306_3441_3442":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3308_3440_3441":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3310_3439_3440":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3312_3438_3439":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3314_3437_3438":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3316_3436_3437":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3318_3435_3436":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3320_3434_3435":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3322_3433_3434":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3324_3432_3433":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3326_3431_3432":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3328_3430_3431":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3330_3429_3430":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3332_3428_3429":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3334_3427_3428":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3336_3426_3427":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3338_3425_3426":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3340_3424_3425":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3342_3423_3424":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3344_3422_3423":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3346_3421_3422":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3348_3420_3421":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3350_3419_3420":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3352_3418_3419":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3354_3417_3418":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3356_3416_3417":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3358_3415_3416":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3360_3414_3415":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3362_3413_3414":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3364_3412_3413":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3366_3411_3412":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3368_3410_3411":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3370_3409_3410":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3372_3408_3409":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3374_3407_3408":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3376_3406_3407":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3378_3405_3406":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3380_3404_3405":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3382_3403_3404":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3384_3402_3403":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3386_3401_3402":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3388_3400_3401":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3390_3399_3400":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3392_3398_3399":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3394_3397_3398":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_4_3396_3397":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_149_3298_3299":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_150_3298_3301":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_151_3298_3303":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_152_3298_3305":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_153_3298_3307":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_154_3298_3309":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_155_3298_3311":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_156_3298_3313":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_157_3298_3315":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_158_3298_3317":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_159_3298_3319":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_160_3298_3321":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_161_3298_3323":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_162_3298_3325":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_163_3298_3327":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_164_3298_3329":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_165_3298_3331":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_166_3298_3333":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_167_3298_3335":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_168_3298_3337":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_169_3298_3339":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_170_3298_3341":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_171_3298_3343":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_172_3298_3345":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_173_3298_3347":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_174_3298_3349":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_175_3298_3351":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_176_3298_3353":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_177_3298_3355":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_178_3298_3357":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_179_3298_3359":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_180_3298_3361":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_181_3298_3363":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_182_3298_3365":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_183_3298_3367":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_184_3298_3369":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_185_3298_3371":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_186_3298_3373":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_187_3298_3375":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_188_3298_3377":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_189_3298_3379":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_190_3298_3381":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_191_3298_3383":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_192_3298_3385":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_193_3298_3387":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_194_3298_3389":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_195_3298_3391":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_196_3298_3393":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_197_3298_3395":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__3298":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_3299":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3301":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3303":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3305":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3307":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3309":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3311":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3313":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3315":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3317":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3319":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3321":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3323":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3325":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3327":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3329":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3331":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3333":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3335":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3337":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3339":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3341":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3343":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3345":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3347":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3349":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3351":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3353":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3355":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3357":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3359":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3361":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3363":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3365":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3367":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3369":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3371":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3373":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3375":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3377":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3379":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3381":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3383":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3385":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3387":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3389":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3391":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3393":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3395":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fexp_3299.out","dwfp_add_3300_3444_3445.a"], + ["dwfp_add_3302_3443_3444.z","dwfp_add_3300_3444_3445.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_3300_3444_3445.z"], + ["fexp_3301.out","dwfp_add_3302_3443_3444.a"], + ["dwfp_add_3304_3442_3443.z","dwfp_add_3302_3443_3444.b"], + ["fexp_3303.out","dwfp_add_3304_3442_3443.a"], + ["dwfp_add_3306_3441_3442.z","dwfp_add_3304_3442_3443.b"], + ["fexp_3305.out","dwfp_add_3306_3441_3442.a"], + ["dwfp_add_3308_3440_3441.z","dwfp_add_3306_3441_3442.b"], + ["fexp_3307.out","dwfp_add_3308_3440_3441.a"], + ["dwfp_add_3310_3439_3440.z","dwfp_add_3308_3440_3441.b"], + ["fexp_3309.out","dwfp_add_3310_3439_3440.a"], + ["dwfp_add_3312_3438_3439.z","dwfp_add_3310_3439_3440.b"], + ["fexp_3311.out","dwfp_add_3312_3438_3439.a"], + ["dwfp_add_3314_3437_3438.z","dwfp_add_3312_3438_3439.b"], + ["fexp_3313.out","dwfp_add_3314_3437_3438.a"], + ["dwfp_add_3316_3436_3437.z","dwfp_add_3314_3437_3438.b"], + ["fexp_3315.out","dwfp_add_3316_3436_3437.a"], + ["dwfp_add_3318_3435_3436.z","dwfp_add_3316_3436_3437.b"], + ["fexp_3317.out","dwfp_add_3318_3435_3436.a"], + ["dwfp_add_3320_3434_3435.z","dwfp_add_3318_3435_3436.b"], + ["fexp_3319.out","dwfp_add_3320_3434_3435.a"], + ["dwfp_add_3322_3433_3434.z","dwfp_add_3320_3434_3435.b"], + ["fexp_3321.out","dwfp_add_3322_3433_3434.a"], + ["dwfp_add_3324_3432_3433.z","dwfp_add_3322_3433_3434.b"], + ["fexp_3323.out","dwfp_add_3324_3432_3433.a"], + ["dwfp_add_3326_3431_3432.z","dwfp_add_3324_3432_3433.b"], + ["fexp_3325.out","dwfp_add_3326_3431_3432.a"], + ["dwfp_add_3328_3430_3431.z","dwfp_add_3326_3431_3432.b"], + ["fexp_3327.out","dwfp_add_3328_3430_3431.a"], + ["dwfp_add_3330_3429_3430.z","dwfp_add_3328_3430_3431.b"], + ["fexp_3329.out","dwfp_add_3330_3429_3430.a"], + ["dwfp_add_3332_3428_3429.z","dwfp_add_3330_3429_3430.b"], + ["fexp_3331.out","dwfp_add_3332_3428_3429.a"], + ["dwfp_add_3334_3427_3428.z","dwfp_add_3332_3428_3429.b"], + ["fexp_3333.out","dwfp_add_3334_3427_3428.a"], + ["dwfp_add_3336_3426_3427.z","dwfp_add_3334_3427_3428.b"], + ["fexp_3335.out","dwfp_add_3336_3426_3427.a"], + ["dwfp_add_3338_3425_3426.z","dwfp_add_3336_3426_3427.b"], + ["fexp_3337.out","dwfp_add_3338_3425_3426.a"], + ["dwfp_add_3340_3424_3425.z","dwfp_add_3338_3425_3426.b"], + ["fexp_3339.out","dwfp_add_3340_3424_3425.a"], + ["dwfp_add_3342_3423_3424.z","dwfp_add_3340_3424_3425.b"], + ["fexp_3341.out","dwfp_add_3342_3423_3424.a"], + ["dwfp_add_3344_3422_3423.z","dwfp_add_3342_3423_3424.b"], + ["fexp_3343.out","dwfp_add_3344_3422_3423.a"], + ["dwfp_add_3346_3421_3422.z","dwfp_add_3344_3422_3423.b"], + ["fexp_3345.out","dwfp_add_3346_3421_3422.a"], + ["dwfp_add_3348_3420_3421.z","dwfp_add_3346_3421_3422.b"], + ["fexp_3347.out","dwfp_add_3348_3420_3421.a"], + ["dwfp_add_3350_3419_3420.z","dwfp_add_3348_3420_3421.b"], + ["fexp_3349.out","dwfp_add_3350_3419_3420.a"], + ["dwfp_add_3352_3418_3419.z","dwfp_add_3350_3419_3420.b"], + ["fexp_3351.out","dwfp_add_3352_3418_3419.a"], + ["dwfp_add_3354_3417_3418.z","dwfp_add_3352_3418_3419.b"], + ["fexp_3353.out","dwfp_add_3354_3417_3418.a"], + ["dwfp_add_3356_3416_3417.z","dwfp_add_3354_3417_3418.b"], + ["fexp_3355.out","dwfp_add_3356_3416_3417.a"], + ["dwfp_add_3358_3415_3416.z","dwfp_add_3356_3416_3417.b"], + ["fexp_3357.out","dwfp_add_3358_3415_3416.a"], + ["dwfp_add_3360_3414_3415.z","dwfp_add_3358_3415_3416.b"], + ["fexp_3359.out","dwfp_add_3360_3414_3415.a"], + ["dwfp_add_3362_3413_3414.z","dwfp_add_3360_3414_3415.b"], + ["fexp_3361.out","dwfp_add_3362_3413_3414.a"], + ["dwfp_add_3364_3412_3413.z","dwfp_add_3362_3413_3414.b"], + ["fexp_3363.out","dwfp_add_3364_3412_3413.a"], + ["dwfp_add_3366_3411_3412.z","dwfp_add_3364_3412_3413.b"], + ["fexp_3365.out","dwfp_add_3366_3411_3412.a"], + ["dwfp_add_3368_3410_3411.z","dwfp_add_3366_3411_3412.b"], + ["fexp_3367.out","dwfp_add_3368_3410_3411.a"], + ["dwfp_add_3370_3409_3410.z","dwfp_add_3368_3410_3411.b"], + ["fexp_3369.out","dwfp_add_3370_3409_3410.a"], + ["dwfp_add_3372_3408_3409.z","dwfp_add_3370_3409_3410.b"], + ["fexp_3371.out","dwfp_add_3372_3408_3409.a"], + ["dwfp_add_3374_3407_3408.z","dwfp_add_3372_3408_3409.b"], + ["fexp_3373.out","dwfp_add_3374_3407_3408.a"], + ["dwfp_add_3376_3406_3407.z","dwfp_add_3374_3407_3408.b"], + ["fexp_3375.out","dwfp_add_3376_3406_3407.a"], + ["dwfp_add_3378_3405_3406.z","dwfp_add_3376_3406_3407.b"], + ["fexp_3377.out","dwfp_add_3378_3405_3406.a"], + ["dwfp_add_3380_3404_3405.z","dwfp_add_3378_3405_3406.b"], + ["fexp_3379.out","dwfp_add_3380_3404_3405.a"], + ["dwfp_add_3382_3403_3404.z","dwfp_add_3380_3404_3405.b"], + ["fexp_3381.out","dwfp_add_3382_3403_3404.a"], + ["dwfp_add_3384_3402_3403.z","dwfp_add_3382_3403_3404.b"], + ["fexp_3383.out","dwfp_add_3384_3402_3403.a"], + ["dwfp_add_3386_3401_3402.z","dwfp_add_3384_3402_3403.b"], + ["fexp_3385.out","dwfp_add_3386_3401_3402.a"], + ["dwfp_add_3388_3400_3401.z","dwfp_add_3386_3401_3402.b"], + ["fexp_3387.out","dwfp_add_3388_3400_3401.a"], + ["dwfp_add_3390_3399_3400.z","dwfp_add_3388_3400_3401.b"], + ["fexp_3389.out","dwfp_add_3390_3399_3400.a"], + ["dwfp_add_3392_3398_3399.z","dwfp_add_3390_3399_3400.b"], + ["fexp_3391.out","dwfp_add_3392_3398_3399.a"], + ["dwfp_add_3394_3397_3398.z","dwfp_add_3392_3398_3399.b"], + ["fexp_3393.out","dwfp_add_3394_3397_3398.a"], + ["dwfp_add_non_local_means_sum_stencil_4_3396_3397.z","dwfp_add_3394_3397_3398.b"], + ["self.in1_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_4_3396_3397.a"], + ["fexp_3395.out","dwfp_add_non_local_means_sum_stencil_4_3396_3397.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_149_3298_3299.a"], + ["fconst-1__3298.out","dwfp_mul_blur_d_stencil_149_3298_3299.b"], + ["fexp_3299.in","dwfp_mul_blur_d_stencil_149_3298_3299.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_150_3298_3301.a"], + ["fconst-1__3298$1.out","dwfp_mul_blur_d_stencil_150_3298_3301.b"], + ["fexp_3301.in","dwfp_mul_blur_d_stencil_150_3298_3301.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_151_3298_3303.a"], + ["fconst-1__3298$2.out","dwfp_mul_blur_d_stencil_151_3298_3303.b"], + ["fexp_3303.in","dwfp_mul_blur_d_stencil_151_3298_3303.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_152_3298_3305.a"], + ["fconst-1__3298$3.out","dwfp_mul_blur_d_stencil_152_3298_3305.b"], + ["fexp_3305.in","dwfp_mul_blur_d_stencil_152_3298_3305.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_153_3298_3307.a"], + ["fconst-1__3298$4.out","dwfp_mul_blur_d_stencil_153_3298_3307.b"], + ["fexp_3307.in","dwfp_mul_blur_d_stencil_153_3298_3307.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_154_3298_3309.a"], + ["fconst-1__3298$5.out","dwfp_mul_blur_d_stencil_154_3298_3309.b"], + ["fexp_3309.in","dwfp_mul_blur_d_stencil_154_3298_3309.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_155_3298_3311.a"], + ["fconst-1__3298$6.out","dwfp_mul_blur_d_stencil_155_3298_3311.b"], + ["fexp_3311.in","dwfp_mul_blur_d_stencil_155_3298_3311.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_156_3298_3313.a"], + ["fconst-1__3298$7.out","dwfp_mul_blur_d_stencil_156_3298_3313.b"], + ["fexp_3313.in","dwfp_mul_blur_d_stencil_156_3298_3313.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_157_3298_3315.a"], + ["fconst-1__3298$8.out","dwfp_mul_blur_d_stencil_157_3298_3315.b"], + ["fexp_3315.in","dwfp_mul_blur_d_stencil_157_3298_3315.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_158_3298_3317.a"], + ["fconst-1__3298$9.out","dwfp_mul_blur_d_stencil_158_3298_3317.b"], + ["fexp_3317.in","dwfp_mul_blur_d_stencil_158_3298_3317.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_159_3298_3319.a"], + ["fconst-1__3298$10.out","dwfp_mul_blur_d_stencil_159_3298_3319.b"], + ["fexp_3319.in","dwfp_mul_blur_d_stencil_159_3298_3319.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_160_3298_3321.a"], + ["fconst-1__3298$11.out","dwfp_mul_blur_d_stencil_160_3298_3321.b"], + ["fexp_3321.in","dwfp_mul_blur_d_stencil_160_3298_3321.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_161_3298_3323.a"], + ["fconst-1__3298$12.out","dwfp_mul_blur_d_stencil_161_3298_3323.b"], + ["fexp_3323.in","dwfp_mul_blur_d_stencil_161_3298_3323.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_162_3298_3325.a"], + ["fconst-1__3298$13.out","dwfp_mul_blur_d_stencil_162_3298_3325.b"], + ["fexp_3325.in","dwfp_mul_blur_d_stencil_162_3298_3325.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_163_3298_3327.a"], + ["fconst-1__3298$14.out","dwfp_mul_blur_d_stencil_163_3298_3327.b"], + ["fexp_3327.in","dwfp_mul_blur_d_stencil_163_3298_3327.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_164_3298_3329.a"], + ["fconst-1__3298$15.out","dwfp_mul_blur_d_stencil_164_3298_3329.b"], + ["fexp_3329.in","dwfp_mul_blur_d_stencil_164_3298_3329.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_165_3298_3331.a"], + ["fconst-1__3298$16.out","dwfp_mul_blur_d_stencil_165_3298_3331.b"], + ["fexp_3331.in","dwfp_mul_blur_d_stencil_165_3298_3331.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_166_3298_3333.a"], + ["fconst-1__3298$17.out","dwfp_mul_blur_d_stencil_166_3298_3333.b"], + ["fexp_3333.in","dwfp_mul_blur_d_stencil_166_3298_3333.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_167_3298_3335.a"], + ["fconst-1__3298$18.out","dwfp_mul_blur_d_stencil_167_3298_3335.b"], + ["fexp_3335.in","dwfp_mul_blur_d_stencil_167_3298_3335.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_168_3298_3337.a"], + ["fconst-1__3298$19.out","dwfp_mul_blur_d_stencil_168_3298_3337.b"], + ["fexp_3337.in","dwfp_mul_blur_d_stencil_168_3298_3337.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_169_3298_3339.a"], + ["fconst-1__3298$20.out","dwfp_mul_blur_d_stencil_169_3298_3339.b"], + ["fexp_3339.in","dwfp_mul_blur_d_stencil_169_3298_3339.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_170_3298_3341.a"], + ["fconst-1__3298$21.out","dwfp_mul_blur_d_stencil_170_3298_3341.b"], + ["fexp_3341.in","dwfp_mul_blur_d_stencil_170_3298_3341.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_171_3298_3343.a"], + ["fconst-1__3298$22.out","dwfp_mul_blur_d_stencil_171_3298_3343.b"], + ["fexp_3343.in","dwfp_mul_blur_d_stencil_171_3298_3343.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_172_3298_3345.a"], + ["fconst-1__3298$23.out","dwfp_mul_blur_d_stencil_172_3298_3345.b"], + ["fexp_3345.in","dwfp_mul_blur_d_stencil_172_3298_3345.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_173_3298_3347.a"], + ["fconst-1__3298$24.out","dwfp_mul_blur_d_stencil_173_3298_3347.b"], + ["fexp_3347.in","dwfp_mul_blur_d_stencil_173_3298_3347.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_174_3298_3349.a"], + ["fconst-1__3298$25.out","dwfp_mul_blur_d_stencil_174_3298_3349.b"], + ["fexp_3349.in","dwfp_mul_blur_d_stencil_174_3298_3349.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_175_3298_3351.a"], + ["fconst-1__3298$26.out","dwfp_mul_blur_d_stencil_175_3298_3351.b"], + ["fexp_3351.in","dwfp_mul_blur_d_stencil_175_3298_3351.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_176_3298_3353.a"], + ["fconst-1__3298$27.out","dwfp_mul_blur_d_stencil_176_3298_3353.b"], + ["fexp_3353.in","dwfp_mul_blur_d_stencil_176_3298_3353.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_177_3298_3355.a"], + ["fconst-1__3298$28.out","dwfp_mul_blur_d_stencil_177_3298_3355.b"], + ["fexp_3355.in","dwfp_mul_blur_d_stencil_177_3298_3355.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_178_3298_3357.a"], + ["fconst-1__3298$29.out","dwfp_mul_blur_d_stencil_178_3298_3357.b"], + ["fexp_3357.in","dwfp_mul_blur_d_stencil_178_3298_3357.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_179_3298_3359.a"], + ["fconst-1__3298$30.out","dwfp_mul_blur_d_stencil_179_3298_3359.b"], + ["fexp_3359.in","dwfp_mul_blur_d_stencil_179_3298_3359.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_180_3298_3361.a"], + ["fconst-1__3298$31.out","dwfp_mul_blur_d_stencil_180_3298_3361.b"], + ["fexp_3361.in","dwfp_mul_blur_d_stencil_180_3298_3361.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_181_3298_3363.a"], + ["fconst-1__3298$32.out","dwfp_mul_blur_d_stencil_181_3298_3363.b"], + ["fexp_3363.in","dwfp_mul_blur_d_stencil_181_3298_3363.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_182_3298_3365.a"], + ["fconst-1__3298$33.out","dwfp_mul_blur_d_stencil_182_3298_3365.b"], + ["fexp_3365.in","dwfp_mul_blur_d_stencil_182_3298_3365.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_183_3298_3367.a"], + ["fconst-1__3298$34.out","dwfp_mul_blur_d_stencil_183_3298_3367.b"], + ["fexp_3367.in","dwfp_mul_blur_d_stencil_183_3298_3367.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_184_3298_3369.a"], + ["fconst-1__3298$35.out","dwfp_mul_blur_d_stencil_184_3298_3369.b"], + ["fexp_3369.in","dwfp_mul_blur_d_stencil_184_3298_3369.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_185_3298_3371.a"], + ["fconst-1__3298$36.out","dwfp_mul_blur_d_stencil_185_3298_3371.b"], + ["fexp_3371.in","dwfp_mul_blur_d_stencil_185_3298_3371.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_186_3298_3373.a"], + ["fconst-1__3298$37.out","dwfp_mul_blur_d_stencil_186_3298_3373.b"], + ["fexp_3373.in","dwfp_mul_blur_d_stencil_186_3298_3373.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_187_3298_3375.a"], + ["fconst-1__3298$38.out","dwfp_mul_blur_d_stencil_187_3298_3375.b"], + ["fexp_3375.in","dwfp_mul_blur_d_stencil_187_3298_3375.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_188_3298_3377.a"], + ["fconst-1__3298$39.out","dwfp_mul_blur_d_stencil_188_3298_3377.b"], + ["fexp_3377.in","dwfp_mul_blur_d_stencil_188_3298_3377.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_189_3298_3379.a"], + ["fconst-1__3298$40.out","dwfp_mul_blur_d_stencil_189_3298_3379.b"], + ["fexp_3379.in","dwfp_mul_blur_d_stencil_189_3298_3379.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_190_3298_3381.a"], + ["fconst-1__3298$41.out","dwfp_mul_blur_d_stencil_190_3298_3381.b"], + ["fexp_3381.in","dwfp_mul_blur_d_stencil_190_3298_3381.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_191_3298_3383.a"], + ["fconst-1__3298$42.out","dwfp_mul_blur_d_stencil_191_3298_3383.b"], + ["fexp_3383.in","dwfp_mul_blur_d_stencil_191_3298_3383.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_192_3298_3385.a"], + ["fconst-1__3298$43.out","dwfp_mul_blur_d_stencil_192_3298_3385.b"], + ["fexp_3385.in","dwfp_mul_blur_d_stencil_192_3298_3385.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_193_3298_3387.a"], + ["fconst-1__3298$44.out","dwfp_mul_blur_d_stencil_193_3298_3387.b"], + ["fexp_3387.in","dwfp_mul_blur_d_stencil_193_3298_3387.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_194_3298_3389.a"], + ["fconst-1__3298$45.out","dwfp_mul_blur_d_stencil_194_3298_3389.b"], + ["fexp_3389.in","dwfp_mul_blur_d_stencil_194_3298_3389.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_195_3298_3391.a"], + ["fconst-1__3298$46.out","dwfp_mul_blur_d_stencil_195_3298_3391.b"], + ["fexp_3391.in","dwfp_mul_blur_d_stencil_195_3298_3391.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_196_3298_3393.a"], + ["fconst-1__3298$47.out","dwfp_mul_blur_d_stencil_196_3298_3393.b"], + ["fexp_3393.in","dwfp_mul_blur_d_stencil_196_3298_3393.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_197_3298_3395.a"], + ["fconst-1__3298$48.out","dwfp_mul_blur_d_stencil_197_3298_3395.b"], + ["fexp_3395.in","dwfp_mul_blur_d_stencil_197_3298_3395.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/nlmeans_unroll_reorder_compute.json b/coreir_compute/nlmeans_unroll_reorder_compute.json new file mode 100644 index 000000000..4013a499d --- /dev/null +++ b/coreir_compute/nlmeans_unroll_reorder_compute.json @@ -0,0 +1,5921 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_d_stencil":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__985":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_stencil","fconst0__985.out"] + ] + }, + "hcompute_blur_d_stencil_1":{ + "type":["Record",[ + ["out_blur_d_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_blur_d_y_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_2_1001_1002":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_3_1000_1001":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_4_999_1000":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_5_998_999":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_6_997_998":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_blur_d_y_stencil_7_996_997":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_stencil.0","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.a"], + ["self.in1_blur_d_y_stencil.6","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.b"], + ["dwfp_add_blur_d_y_stencil_7_996_997.b","dwfp_add_blur_d_stencil_1_blur_d_y_stencil_8_996.z"], + ["self.in1_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_2_1001_1002.a"], + ["dwfp_add_blur_d_y_stencil_3_1000_1001.z","dwfp_add_blur_d_y_stencil_2_1001_1002.b"], + ["self.out_blur_d_stencil","dwfp_add_blur_d_y_stencil_2_1001_1002.z"], + ["self.in1_blur_d_y_stencil.1","dwfp_add_blur_d_y_stencil_3_1000_1001.a"], + ["dwfp_add_blur_d_y_stencil_4_999_1000.z","dwfp_add_blur_d_y_stencil_3_1000_1001.b"], + ["self.in1_blur_d_y_stencil.2","dwfp_add_blur_d_y_stencil_4_999_1000.a"], + ["dwfp_add_blur_d_y_stencil_5_998_999.z","dwfp_add_blur_d_y_stencil_4_999_1000.b"], + ["self.in1_blur_d_y_stencil.3","dwfp_add_blur_d_y_stencil_5_998_999.a"], + ["dwfp_add_blur_d_y_stencil_6_997_998.z","dwfp_add_blur_d_y_stencil_5_998_999.b"], + ["self.in1_blur_d_y_stencil.4","dwfp_add_blur_d_y_stencil_6_997_998.a"], + ["dwfp_add_blur_d_y_stencil_7_996_997.z","dwfp_add_blur_d_y_stencil_6_997_998.b"], + ["self.in1_blur_d_y_stencil.5","dwfp_add_blur_d_y_stencil_7_996_997.a"] + ] + }, + "hcompute_blur_d_y_stencil":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__941":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_blur_d_y_stencil","fconst0__941.out"] + ] + }, + "hcompute_blur_d_y_stencil_1":{ + "type":["Record",[ + ["out_blur_d_y_stencil",["Array",16,"Bit"]], + ["in0_blur_d_y_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_d_stencil",["Array",7,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_blur_d_y_stencil_1_d_stencil_8_953":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_2_958_959":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_3_957_958":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_4_956_957":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_5_955_956":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_6_954_955":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_7_953_954":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + } + }, + "connections":[ + ["self.in0_blur_d_y_stencil.0","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.a"], + ["self.in1_d_stencil.6","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.b"], + ["dwfp_add_d_stencil_7_953_954.b","dwfp_add_blur_d_y_stencil_1_d_stencil_8_953.z"], + ["self.in1_d_stencil.0","dwfp_add_d_stencil_2_958_959.a"], + ["dwfp_add_d_stencil_3_957_958.z","dwfp_add_d_stencil_2_958_959.b"], + ["self.out_blur_d_y_stencil","dwfp_add_d_stencil_2_958_959.z"], + ["self.in1_d_stencil.1","dwfp_add_d_stencil_3_957_958.a"], + ["dwfp_add_d_stencil_4_956_957.z","dwfp_add_d_stencil_3_957_958.b"], + ["self.in1_d_stencil.2","dwfp_add_d_stencil_4_956_957.a"], + ["dwfp_add_d_stencil_5_955_956.z","dwfp_add_d_stencil_4_956_957.b"], + ["self.in1_d_stencil.3","dwfp_add_d_stencil_5_955_956.a"], + ["dwfp_add_d_stencil_6_954_955.z","dwfp_add_d_stencil_5_955_956.b"], + ["self.in1_d_stencil.4","dwfp_add_d_stencil_6_954_955.a"], + ["dwfp_add_d_stencil_7_953_954.z","dwfp_add_d_stencil_6_954_955.b"], + ["self.in1_d_stencil.5","dwfp_add_d_stencil_7_953_954.a"] + ] + }, + "hcompute_d_stencil":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__890":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_d_stencil","fconst0__890.out"] + ] + }, + "hcompute_d_stencil_1":{ + "type":["Record",[ + ["out_d_stencil",["Array",16,"Bit"]], + ["in0_d_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",6,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_906_912_913":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_908_911_912":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_d_stencil_1_910_911":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_905_905_906":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_907_907_908":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_909_909_910":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909":{ + "genref":"float.sub", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_905_905_906.z","dwfp_add_906_912_913.a"], + ["dwfp_add_908_911_912.z","dwfp_add_906_912_913.b"], + ["self.out_d_stencil","dwfp_add_906_912_913.z"], + ["dwfp_mul_907_907_908.z","dwfp_add_908_911_912.a"], + ["dwfp_add_d_stencil_1_910_911.z","dwfp_add_908_911_912.b"], + ["self.in0_d_stencil.0","dwfp_add_d_stencil_1_910_911.a"], + ["dwfp_mul_909_909_910.z","dwfp_add_d_stencil_1_910_911.b"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.a"], + ["fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.out","dwfp_mul_905_905_906.b"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.a"], + ["fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.out","dwfp_mul_907_907_908.b"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.a"], + ["fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.out","dwfp_mul_909_909_910.b"], + ["self.in1_hw_input_global_wrapper_stencil.0","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in0"], + ["self.in1_hw_input_global_wrapper_stencil.1","fsub_hw_input_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_2_905.in1"], + ["self.in1_hw_input_global_wrapper_stencil.2","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in0"], + ["self.in1_hw_input_global_wrapper_stencil.3","fsub_hw_input_global_wrapper_stencil_3_hw_input_global_wrapper_stencil_4_907.in1"], + ["self.in1_hw_input_global_wrapper_stencil.4","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in0"], + ["self.in1_hw_input_global_wrapper_stencil.5","fsub_hw_input_global_wrapper_stencil_5_hw_input_global_wrapper_stencil_6_909.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_3655_3656_3657":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__3654":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__3652":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__3656":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_3653_3654_3655":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_3651_3652_3653":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_3653_3654_3655.out","dwfp_mul_3655_3656_3657.a"], + ["fconst255__3656.out","dwfp_mul_3655_3656_3657.b"], + ["self.out_hw_output_stencil","dwfp_mul_3655_3656_3657.z"], + ["fmax_3653_3654_3655.in1","fconst0__3654.out"], + ["fmin_3651_3652_3653.in1","fconst1__3652.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651.in1"], + ["fmin_3651_3652_3653.in0","fdiv_non_local_means_sum_stencil_5_non_local_means_sum_stencil_6_3651.out"], + ["fmin_3651_3652_3653.out","fmax_3653_3654_3655.in0"] + ] + }, + "hcompute_hw_output_stencil_1":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_3678_3679_3680":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__3677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__3675":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__3679":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_3676_3677_3678":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_3674_3675_3676":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_3676_3677_3678.out","dwfp_mul_3678_3679_3680.a"], + ["fconst255__3679.out","dwfp_mul_3678_3679_3680.b"], + ["self.out_hw_output_stencil","dwfp_mul_3678_3679_3680.z"], + ["fmax_3676_3677_3678.in1","fconst0__3677.out"], + ["fmin_3674_3675_3676.in1","fconst1__3675.out"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674.in0"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674.in1"], + ["fmin_3674_3675_3676.in0","fdiv_non_local_means_sum_stencil_7_non_local_means_sum_stencil_8_3674.out"], + ["fmin_3674_3675_3676.out","fmax_3676_3677_3678.in0"] + ] + }, + "hcompute_hw_output_stencil_2":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_non_local_means_sum_stencil",["Array",2,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_mul_3701_3702_3703":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst0__3700":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + }, + "fconst1__3698":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h3f80"]}, + "metadata":{"float_value":"Equivalent float = 1.000000"} + }, + "fconst255__3702":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h437f"]}, + "metadata":{"float_value":"Equivalent float = 255.000000"} + }, + "fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697":{ + "genref":"float.div", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmax_3699_3700_3701":{ + "genref":"float.max", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fmin_3697_3698_3699":{ + "genref":"float.min", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fmax_3699_3700_3701.out","dwfp_mul_3701_3702_3703.a"], + ["fconst255__3702.out","dwfp_mul_3701_3702_3703.b"], + ["self.out_hw_output_stencil","dwfp_mul_3701_3702_3703.z"], + ["fmax_3699_3700_3701.in1","fconst0__3700.out"], + ["fmin_3697_3698_3699.in1","fconst1__3698.out"], + ["self.in0_non_local_means_sum_stencil.1","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697.in0"], + ["self.in0_non_local_means_sum_stencil.0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697.in1"], + ["fmin_3697_3698_3699.in0","fdiv_non_local_means_sum_stencil_9_non_local_means_sum_stencil_10_3697.out"], + ["fmin_3697_3698_3699.out","fmax_3699_3700_3701.in0"] + ] + }, + "hcompute_non_local_means_sum_stencil":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1027":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1027.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_1":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1030":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1030.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_2":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1033":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1033.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_3":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "fconst0__1036":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]}, + "metadata":{"float_value":"Equivalent float = 0.000000"} + } + }, + "connections":[ + ["self.out_non_local_means_sum_stencil","fconst0__1036.out"] + ] + }, + "hcompute_non_local_means_sum_stencil_4":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_1238_1430_1431":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1241_1429_1430":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1244_1428_1429":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1247_1427_1428":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1250_1426_1427":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1253_1425_1426":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1256_1424_1425":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1259_1423_1424":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1262_1422_1423":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1265_1421_1422":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1268_1420_1421":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1271_1419_1420":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1274_1418_1419":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1277_1417_1418":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1280_1416_1417":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1283_1415_1416":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1286_1414_1415":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1289_1413_1414":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1292_1412_1413":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1295_1411_1412":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1298_1410_1411":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1301_1409_1410":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1304_1408_1409":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1307_1407_1408":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1310_1406_1407":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1313_1405_1406":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1316_1404_1405":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1319_1403_1404":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1322_1402_1403":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1325_1401_1402":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1328_1400_1401":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1331_1399_1400":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1334_1398_1399":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1337_1397_1398":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1340_1396_1397":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1343_1395_1396":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1346_1394_1395":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1349_1393_1394":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1352_1392_1393":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1355_1391_1392":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1358_1390_1391":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1361_1389_1390":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1364_1388_1389":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1367_1387_1388":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1370_1386_1387":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1373_1385_1386":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1376_1384_1385":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1379_1383_1384":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_1_1382_1383":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_10_1235_1260":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_11_1235_1263":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_12_1235_1266":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_13_1235_1269":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_14_1235_1272":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_15_1235_1275":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_16_1235_1278":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_17_1235_1281":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_18_1235_1284":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_19_1235_1287":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_20_1235_1290":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_21_1235_1293":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_22_1235_1296":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_23_1235_1299":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_24_1235_1302":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_25_1235_1305":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_26_1235_1308":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_27_1235_1311":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_28_1235_1314":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_29_1235_1317":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_2_1235_1236":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_30_1235_1320":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_31_1235_1323":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_32_1235_1326":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_33_1235_1329":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_34_1235_1332":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_35_1235_1335":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_36_1235_1338":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_37_1235_1341":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_38_1235_1344":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_39_1235_1347":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_3_1235_1239":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_40_1235_1350":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_41_1235_1353":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_42_1235_1356":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_43_1235_1359":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_44_1235_1362":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_45_1235_1365":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_46_1235_1368":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_47_1235_1371":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_48_1235_1374":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_49_1235_1377":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_4_1235_1242":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_50_1235_1380":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_5_1235_1245":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_6_1235_1248":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_7_1235_1251":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_8_1235_1254":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_9_1235_1257":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1235":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1235$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1236":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1239":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1242":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1245":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1248":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1251":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1254":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1257":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1260":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1263":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1266":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1269":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1272":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1275":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1278":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1281":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1284":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1287":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1290":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1293":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1296":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1299":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1302":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1305":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1308":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1311":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1314":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1317":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1320":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1323":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1326":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1329":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1332":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1335":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1338":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1341":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1344":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1347":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1350":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1353":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1356":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1359":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1362":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1365":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1368":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1371":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1374":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1377":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1380":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238.z","dwfp_add_1238_1430_1431.a"], + ["dwfp_add_1241_1429_1430.z","dwfp_add_1238_1430_1431.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_1238_1430_1431.z"], + ["dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241.z","dwfp_add_1241_1429_1430.a"], + ["dwfp_add_1244_1428_1429.z","dwfp_add_1241_1429_1430.b"], + ["dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244.z","dwfp_add_1244_1428_1429.a"], + ["dwfp_add_1247_1427_1428.z","dwfp_add_1244_1428_1429.b"], + ["dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247.z","dwfp_add_1247_1427_1428.a"], + ["dwfp_add_1250_1426_1427.z","dwfp_add_1247_1427_1428.b"], + ["dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250.z","dwfp_add_1250_1426_1427.a"], + ["dwfp_add_1253_1425_1426.z","dwfp_add_1250_1426_1427.b"], + ["dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253.z","dwfp_add_1253_1425_1426.a"], + ["dwfp_add_1256_1424_1425.z","dwfp_add_1253_1425_1426.b"], + ["dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256.z","dwfp_add_1256_1424_1425.a"], + ["dwfp_add_1259_1423_1424.z","dwfp_add_1256_1424_1425.b"], + ["dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259.z","dwfp_add_1259_1423_1424.a"], + ["dwfp_add_1262_1422_1423.z","dwfp_add_1259_1423_1424.b"], + ["dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262.z","dwfp_add_1262_1422_1423.a"], + ["dwfp_add_1265_1421_1422.z","dwfp_add_1262_1422_1423.b"], + ["dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265.z","dwfp_add_1265_1421_1422.a"], + ["dwfp_add_1268_1420_1421.z","dwfp_add_1265_1421_1422.b"], + ["dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268.z","dwfp_add_1268_1420_1421.a"], + ["dwfp_add_1271_1419_1420.z","dwfp_add_1268_1420_1421.b"], + ["dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271.z","dwfp_add_1271_1419_1420.a"], + ["dwfp_add_1274_1418_1419.z","dwfp_add_1271_1419_1420.b"], + ["dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274.z","dwfp_add_1274_1418_1419.a"], + ["dwfp_add_1277_1417_1418.z","dwfp_add_1274_1418_1419.b"], + ["dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277.z","dwfp_add_1277_1417_1418.a"], + ["dwfp_add_1280_1416_1417.z","dwfp_add_1277_1417_1418.b"], + ["dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280.z","dwfp_add_1280_1416_1417.a"], + ["dwfp_add_1283_1415_1416.z","dwfp_add_1280_1416_1417.b"], + ["dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283.z","dwfp_add_1283_1415_1416.a"], + ["dwfp_add_1286_1414_1415.z","dwfp_add_1283_1415_1416.b"], + ["dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286.z","dwfp_add_1286_1414_1415.a"], + ["dwfp_add_1289_1413_1414.z","dwfp_add_1286_1414_1415.b"], + ["dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289.z","dwfp_add_1289_1413_1414.a"], + ["dwfp_add_1292_1412_1413.z","dwfp_add_1289_1413_1414.b"], + ["dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292.z","dwfp_add_1292_1412_1413.a"], + ["dwfp_add_1295_1411_1412.z","dwfp_add_1292_1412_1413.b"], + ["dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295.z","dwfp_add_1295_1411_1412.a"], + ["dwfp_add_1298_1410_1411.z","dwfp_add_1295_1411_1412.b"], + ["dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298.z","dwfp_add_1298_1410_1411.a"], + ["dwfp_add_1301_1409_1410.z","dwfp_add_1298_1410_1411.b"], + ["dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301.z","dwfp_add_1301_1409_1410.a"], + ["dwfp_add_1304_1408_1409.z","dwfp_add_1301_1409_1410.b"], + ["dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304.z","dwfp_add_1304_1408_1409.a"], + ["dwfp_add_1307_1407_1408.z","dwfp_add_1304_1408_1409.b"], + ["dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307.z","dwfp_add_1307_1407_1408.a"], + ["dwfp_add_1310_1406_1407.z","dwfp_add_1307_1407_1408.b"], + ["dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310.z","dwfp_add_1310_1406_1407.a"], + ["dwfp_add_1313_1405_1406.z","dwfp_add_1310_1406_1407.b"], + ["dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313.z","dwfp_add_1313_1405_1406.a"], + ["dwfp_add_1316_1404_1405.z","dwfp_add_1313_1405_1406.b"], + ["dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316.z","dwfp_add_1316_1404_1405.a"], + ["dwfp_add_1319_1403_1404.z","dwfp_add_1316_1404_1405.b"], + ["dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319.z","dwfp_add_1319_1403_1404.a"], + ["dwfp_add_1322_1402_1403.z","dwfp_add_1319_1403_1404.b"], + ["dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322.z","dwfp_add_1322_1402_1403.a"], + ["dwfp_add_1325_1401_1402.z","dwfp_add_1322_1402_1403.b"], + ["dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325.z","dwfp_add_1325_1401_1402.a"], + ["dwfp_add_1328_1400_1401.z","dwfp_add_1325_1401_1402.b"], + ["dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328.z","dwfp_add_1328_1400_1401.a"], + ["dwfp_add_1331_1399_1400.z","dwfp_add_1328_1400_1401.b"], + ["dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331.z","dwfp_add_1331_1399_1400.a"], + ["dwfp_add_1334_1398_1399.z","dwfp_add_1331_1399_1400.b"], + ["dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334.z","dwfp_add_1334_1398_1399.a"], + ["dwfp_add_1337_1397_1398.z","dwfp_add_1334_1398_1399.b"], + ["dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337.z","dwfp_add_1337_1397_1398.a"], + ["dwfp_add_1340_1396_1397.z","dwfp_add_1337_1397_1398.b"], + ["dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340.z","dwfp_add_1340_1396_1397.a"], + ["dwfp_add_1343_1395_1396.z","dwfp_add_1340_1396_1397.b"], + ["dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343.z","dwfp_add_1343_1395_1396.a"], + ["dwfp_add_1346_1394_1395.z","dwfp_add_1343_1395_1396.b"], + ["dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346.z","dwfp_add_1346_1394_1395.a"], + ["dwfp_add_1349_1393_1394.z","dwfp_add_1346_1394_1395.b"], + ["dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349.z","dwfp_add_1349_1393_1394.a"], + ["dwfp_add_1352_1392_1393.z","dwfp_add_1349_1393_1394.b"], + ["dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352.z","dwfp_add_1352_1392_1393.a"], + ["dwfp_add_1355_1391_1392.z","dwfp_add_1352_1392_1393.b"], + ["dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355.z","dwfp_add_1355_1391_1392.a"], + ["dwfp_add_1358_1390_1391.z","dwfp_add_1355_1391_1392.b"], + ["dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358.z","dwfp_add_1358_1390_1391.a"], + ["dwfp_add_1361_1389_1390.z","dwfp_add_1358_1390_1391.b"], + ["dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361.z","dwfp_add_1361_1389_1390.a"], + ["dwfp_add_1364_1388_1389.z","dwfp_add_1361_1389_1390.b"], + ["dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364.z","dwfp_add_1364_1388_1389.a"], + ["dwfp_add_1367_1387_1388.z","dwfp_add_1364_1388_1389.b"], + ["dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367.z","dwfp_add_1367_1387_1388.a"], + ["dwfp_add_1370_1386_1387.z","dwfp_add_1367_1387_1388.b"], + ["dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370.z","dwfp_add_1370_1386_1387.a"], + ["dwfp_add_1373_1385_1386.z","dwfp_add_1370_1386_1387.b"], + ["dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373.z","dwfp_add_1373_1385_1386.a"], + ["dwfp_add_1376_1384_1385.z","dwfp_add_1373_1385_1386.b"], + ["dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376.z","dwfp_add_1376_1384_1385.a"], + ["dwfp_add_1379_1383_1384.z","dwfp_add_1376_1384_1385.b"], + ["dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379.z","dwfp_add_1379_1383_1384.a"], + ["dwfp_add_non_local_means_sum_stencil_1_1382_1383.z","dwfp_add_1379_1383_1384.b"], + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_1_1382_1383.a"], + ["dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382.z","dwfp_add_non_local_means_sum_stencil_1_1382_1383.b"], + ["fexp_1236.out","dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238.a"], + ["self.in1_hw_input_global_wrapper_stencil.46","dwfp_mul_1237_hw_input_global_wrapper_stencil_7_1238.b"], + ["fexp_1239.out","dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241.a"], + ["self.in1_hw_input_global_wrapper_stencil.47","dwfp_mul_1240_hw_input_global_wrapper_stencil_8_1241.b"], + ["fexp_1242.out","dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244.a"], + ["self.in1_hw_input_global_wrapper_stencil.48","dwfp_mul_1243_hw_input_global_wrapper_stencil_9_1244.b"], + ["fexp_1245.out","dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_1246_hw_input_global_wrapper_stencil_10_1247.b"], + ["fexp_1248.out","dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250.a"], + ["self.in1_hw_input_global_wrapper_stencil.1","dwfp_mul_1249_hw_input_global_wrapper_stencil_11_1250.b"], + ["fexp_1251.out","dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253.a"], + ["self.in1_hw_input_global_wrapper_stencil.2","dwfp_mul_1252_hw_input_global_wrapper_stencil_12_1253.b"], + ["fexp_1254.out","dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256.a"], + ["self.in1_hw_input_global_wrapper_stencil.3","dwfp_mul_1255_hw_input_global_wrapper_stencil_13_1256.b"], + ["fexp_1257.out","dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259.a"], + ["self.in1_hw_input_global_wrapper_stencil.4","dwfp_mul_1258_hw_input_global_wrapper_stencil_14_1259.b"], + ["fexp_1260.out","dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262.a"], + ["self.in1_hw_input_global_wrapper_stencil.5","dwfp_mul_1261_hw_input_global_wrapper_stencil_15_1262.b"], + ["fexp_1263.out","dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265.a"], + ["self.in1_hw_input_global_wrapper_stencil.6","dwfp_mul_1264_hw_input_global_wrapper_stencil_16_1265.b"], + ["fexp_1266.out","dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268.a"], + ["self.in1_hw_input_global_wrapper_stencil.7","dwfp_mul_1267_hw_input_global_wrapper_stencil_17_1268.b"], + ["fexp_1269.out","dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271.a"], + ["self.in1_hw_input_global_wrapper_stencil.8","dwfp_mul_1270_hw_input_global_wrapper_stencil_18_1271.b"], + ["fexp_1272.out","dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274.a"], + ["self.in1_hw_input_global_wrapper_stencil.9","dwfp_mul_1273_hw_input_global_wrapper_stencil_19_1274.b"], + ["fexp_1275.out","dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277.a"], + ["self.in1_hw_input_global_wrapper_stencil.10","dwfp_mul_1276_hw_input_global_wrapper_stencil_20_1277.b"], + ["fexp_1278.out","dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280.a"], + ["self.in1_hw_input_global_wrapper_stencil.11","dwfp_mul_1279_hw_input_global_wrapper_stencil_21_1280.b"], + ["fexp_1281.out","dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283.a"], + ["self.in1_hw_input_global_wrapper_stencil.12","dwfp_mul_1282_hw_input_global_wrapper_stencil_22_1283.b"], + ["fexp_1284.out","dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286.a"], + ["self.in1_hw_input_global_wrapper_stencil.13","dwfp_mul_1285_hw_input_global_wrapper_stencil_23_1286.b"], + ["fexp_1287.out","dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289.a"], + ["self.in1_hw_input_global_wrapper_stencil.14","dwfp_mul_1288_hw_input_global_wrapper_stencil_24_1289.b"], + ["fexp_1290.out","dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292.a"], + ["self.in1_hw_input_global_wrapper_stencil.15","dwfp_mul_1291_hw_input_global_wrapper_stencil_25_1292.b"], + ["fexp_1293.out","dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295.a"], + ["self.in1_hw_input_global_wrapper_stencil.16","dwfp_mul_1294_hw_input_global_wrapper_stencil_26_1295.b"], + ["fexp_1296.out","dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298.a"], + ["self.in1_hw_input_global_wrapper_stencil.17","dwfp_mul_1297_hw_input_global_wrapper_stencil_27_1298.b"], + ["fexp_1299.out","dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301.a"], + ["self.in1_hw_input_global_wrapper_stencil.18","dwfp_mul_1300_hw_input_global_wrapper_stencil_28_1301.b"], + ["fexp_1302.out","dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304.a"], + ["self.in1_hw_input_global_wrapper_stencil.19","dwfp_mul_1303_hw_input_global_wrapper_stencil_29_1304.b"], + ["fexp_1305.out","dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307.a"], + ["self.in1_hw_input_global_wrapper_stencil.20","dwfp_mul_1306_hw_input_global_wrapper_stencil_30_1307.b"], + ["fexp_1308.out","dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310.a"], + ["self.in1_hw_input_global_wrapper_stencil.21","dwfp_mul_1309_hw_input_global_wrapper_stencil_31_1310.b"], + ["fexp_1311.out","dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313.a"], + ["self.in1_hw_input_global_wrapper_stencil.22","dwfp_mul_1312_hw_input_global_wrapper_stencil_32_1313.b"], + ["fexp_1314.out","dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316.a"], + ["self.in1_hw_input_global_wrapper_stencil.23","dwfp_mul_1315_hw_input_global_wrapper_stencil_33_1316.b"], + ["fexp_1317.out","dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319.a"], + ["self.in1_hw_input_global_wrapper_stencil.24","dwfp_mul_1318_hw_input_global_wrapper_stencil_34_1319.b"], + ["fexp_1320.out","dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322.a"], + ["self.in1_hw_input_global_wrapper_stencil.25","dwfp_mul_1321_hw_input_global_wrapper_stencil_35_1322.b"], + ["fexp_1323.out","dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325.a"], + ["self.in1_hw_input_global_wrapper_stencil.26","dwfp_mul_1324_hw_input_global_wrapper_stencil_36_1325.b"], + ["fexp_1326.out","dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328.a"], + ["self.in1_hw_input_global_wrapper_stencil.27","dwfp_mul_1327_hw_input_global_wrapper_stencil_37_1328.b"], + ["fexp_1329.out","dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331.a"], + ["self.in1_hw_input_global_wrapper_stencil.28","dwfp_mul_1330_hw_input_global_wrapper_stencil_38_1331.b"], + ["fexp_1332.out","dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334.a"], + ["self.in1_hw_input_global_wrapper_stencil.29","dwfp_mul_1333_hw_input_global_wrapper_stencil_39_1334.b"], + ["fexp_1335.out","dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337.a"], + ["self.in1_hw_input_global_wrapper_stencil.30","dwfp_mul_1336_hw_input_global_wrapper_stencil_40_1337.b"], + ["fexp_1338.out","dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340.a"], + ["self.in1_hw_input_global_wrapper_stencil.31","dwfp_mul_1339_hw_input_global_wrapper_stencil_41_1340.b"], + ["fexp_1341.out","dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343.a"], + ["self.in1_hw_input_global_wrapper_stencil.32","dwfp_mul_1342_hw_input_global_wrapper_stencil_42_1343.b"], + ["fexp_1344.out","dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346.a"], + ["self.in1_hw_input_global_wrapper_stencil.33","dwfp_mul_1345_hw_input_global_wrapper_stencil_43_1346.b"], + ["fexp_1347.out","dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349.a"], + ["self.in1_hw_input_global_wrapper_stencil.34","dwfp_mul_1348_hw_input_global_wrapper_stencil_44_1349.b"], + ["fexp_1350.out","dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352.a"], + ["self.in1_hw_input_global_wrapper_stencil.35","dwfp_mul_1351_hw_input_global_wrapper_stencil_45_1352.b"], + ["fexp_1353.out","dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355.a"], + ["self.in1_hw_input_global_wrapper_stencil.36","dwfp_mul_1354_hw_input_global_wrapper_stencil_46_1355.b"], + ["fexp_1356.out","dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358.a"], + ["self.in1_hw_input_global_wrapper_stencil.37","dwfp_mul_1357_hw_input_global_wrapper_stencil_47_1358.b"], + ["fexp_1359.out","dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361.a"], + ["self.in1_hw_input_global_wrapper_stencil.38","dwfp_mul_1360_hw_input_global_wrapper_stencil_48_1361.b"], + ["fexp_1362.out","dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364.a"], + ["self.in1_hw_input_global_wrapper_stencil.39","dwfp_mul_1363_hw_input_global_wrapper_stencil_49_1364.b"], + ["fexp_1365.out","dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367.a"], + ["self.in1_hw_input_global_wrapper_stencil.40","dwfp_mul_1366_hw_input_global_wrapper_stencil_50_1367.b"], + ["fexp_1368.out","dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370.a"], + ["self.in1_hw_input_global_wrapper_stencil.41","dwfp_mul_1369_hw_input_global_wrapper_stencil_51_1370.b"], + ["fexp_1371.out","dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373.a"], + ["self.in1_hw_input_global_wrapper_stencil.42","dwfp_mul_1372_hw_input_global_wrapper_stencil_52_1373.b"], + ["fexp_1374.out","dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376.a"], + ["self.in1_hw_input_global_wrapper_stencil.43","dwfp_mul_1375_hw_input_global_wrapper_stencil_53_1376.b"], + ["fexp_1377.out","dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379.a"], + ["self.in1_hw_input_global_wrapper_stencil.44","dwfp_mul_1378_hw_input_global_wrapper_stencil_54_1379.b"], + ["fexp_1380.out","dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382.a"], + ["self.in1_hw_input_global_wrapper_stencil.45","dwfp_mul_1381_hw_input_global_wrapper_stencil_55_1382.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_10_1235_1260.a"], + ["fconst-1__1235$8.out","dwfp_mul_blur_d_stencil_10_1235_1260.b"], + ["fexp_1260.in","dwfp_mul_blur_d_stencil_10_1235_1260.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_11_1235_1263.a"], + ["fconst-1__1235$9.out","dwfp_mul_blur_d_stencil_11_1235_1263.b"], + ["fexp_1263.in","dwfp_mul_blur_d_stencil_11_1235_1263.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_12_1235_1266.a"], + ["fconst-1__1235$10.out","dwfp_mul_blur_d_stencil_12_1235_1266.b"], + ["fexp_1266.in","dwfp_mul_blur_d_stencil_12_1235_1266.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_13_1235_1269.a"], + ["fconst-1__1235$11.out","dwfp_mul_blur_d_stencil_13_1235_1269.b"], + ["fexp_1269.in","dwfp_mul_blur_d_stencil_13_1235_1269.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_14_1235_1272.a"], + ["fconst-1__1235$12.out","dwfp_mul_blur_d_stencil_14_1235_1272.b"], + ["fexp_1272.in","dwfp_mul_blur_d_stencil_14_1235_1272.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_15_1235_1275.a"], + ["fconst-1__1235$13.out","dwfp_mul_blur_d_stencil_15_1235_1275.b"], + ["fexp_1275.in","dwfp_mul_blur_d_stencil_15_1235_1275.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_16_1235_1278.a"], + ["fconst-1__1235$14.out","dwfp_mul_blur_d_stencil_16_1235_1278.b"], + ["fexp_1278.in","dwfp_mul_blur_d_stencil_16_1235_1278.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_17_1235_1281.a"], + ["fconst-1__1235$15.out","dwfp_mul_blur_d_stencil_17_1235_1281.b"], + ["fexp_1281.in","dwfp_mul_blur_d_stencil_17_1235_1281.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_18_1235_1284.a"], + ["fconst-1__1235$16.out","dwfp_mul_blur_d_stencil_18_1235_1284.b"], + ["fexp_1284.in","dwfp_mul_blur_d_stencil_18_1235_1284.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_19_1235_1287.a"], + ["fconst-1__1235$17.out","dwfp_mul_blur_d_stencil_19_1235_1287.b"], + ["fexp_1287.in","dwfp_mul_blur_d_stencil_19_1235_1287.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_20_1235_1290.a"], + ["fconst-1__1235$18.out","dwfp_mul_blur_d_stencil_20_1235_1290.b"], + ["fexp_1290.in","dwfp_mul_blur_d_stencil_20_1235_1290.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_21_1235_1293.a"], + ["fconst-1__1235$19.out","dwfp_mul_blur_d_stencil_21_1235_1293.b"], + ["fexp_1293.in","dwfp_mul_blur_d_stencil_21_1235_1293.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_22_1235_1296.a"], + ["fconst-1__1235$20.out","dwfp_mul_blur_d_stencil_22_1235_1296.b"], + ["fexp_1296.in","dwfp_mul_blur_d_stencil_22_1235_1296.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_23_1235_1299.a"], + ["fconst-1__1235$21.out","dwfp_mul_blur_d_stencil_23_1235_1299.b"], + ["fexp_1299.in","dwfp_mul_blur_d_stencil_23_1235_1299.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_24_1235_1302.a"], + ["fconst-1__1235$22.out","dwfp_mul_blur_d_stencil_24_1235_1302.b"], + ["fexp_1302.in","dwfp_mul_blur_d_stencil_24_1235_1302.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_25_1235_1305.a"], + ["fconst-1__1235$23.out","dwfp_mul_blur_d_stencil_25_1235_1305.b"], + ["fexp_1305.in","dwfp_mul_blur_d_stencil_25_1235_1305.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_26_1235_1308.a"], + ["fconst-1__1235$24.out","dwfp_mul_blur_d_stencil_26_1235_1308.b"], + ["fexp_1308.in","dwfp_mul_blur_d_stencil_26_1235_1308.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_27_1235_1311.a"], + ["fconst-1__1235$25.out","dwfp_mul_blur_d_stencil_27_1235_1311.b"], + ["fexp_1311.in","dwfp_mul_blur_d_stencil_27_1235_1311.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_28_1235_1314.a"], + ["fconst-1__1235$26.out","dwfp_mul_blur_d_stencil_28_1235_1314.b"], + ["fexp_1314.in","dwfp_mul_blur_d_stencil_28_1235_1314.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_29_1235_1317.a"], + ["fconst-1__1235$27.out","dwfp_mul_blur_d_stencil_29_1235_1317.b"], + ["fexp_1317.in","dwfp_mul_blur_d_stencil_29_1235_1317.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_2_1235_1236.a"], + ["fconst-1__1235.out","dwfp_mul_blur_d_stencil_2_1235_1236.b"], + ["fexp_1236.in","dwfp_mul_blur_d_stencil_2_1235_1236.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_30_1235_1320.a"], + ["fconst-1__1235$28.out","dwfp_mul_blur_d_stencil_30_1235_1320.b"], + ["fexp_1320.in","dwfp_mul_blur_d_stencil_30_1235_1320.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_31_1235_1323.a"], + ["fconst-1__1235$29.out","dwfp_mul_blur_d_stencil_31_1235_1323.b"], + ["fexp_1323.in","dwfp_mul_blur_d_stencil_31_1235_1323.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_32_1235_1326.a"], + ["fconst-1__1235$30.out","dwfp_mul_blur_d_stencil_32_1235_1326.b"], + ["fexp_1326.in","dwfp_mul_blur_d_stencil_32_1235_1326.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_33_1235_1329.a"], + ["fconst-1__1235$31.out","dwfp_mul_blur_d_stencil_33_1235_1329.b"], + ["fexp_1329.in","dwfp_mul_blur_d_stencil_33_1235_1329.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_34_1235_1332.a"], + ["fconst-1__1235$32.out","dwfp_mul_blur_d_stencil_34_1235_1332.b"], + ["fexp_1332.in","dwfp_mul_blur_d_stencil_34_1235_1332.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_35_1235_1335.a"], + ["fconst-1__1235$33.out","dwfp_mul_blur_d_stencil_35_1235_1335.b"], + ["fexp_1335.in","dwfp_mul_blur_d_stencil_35_1235_1335.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_36_1235_1338.a"], + ["fconst-1__1235$34.out","dwfp_mul_blur_d_stencil_36_1235_1338.b"], + ["fexp_1338.in","dwfp_mul_blur_d_stencil_36_1235_1338.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_37_1235_1341.a"], + ["fconst-1__1235$35.out","dwfp_mul_blur_d_stencil_37_1235_1341.b"], + ["fexp_1341.in","dwfp_mul_blur_d_stencil_37_1235_1341.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_38_1235_1344.a"], + ["fconst-1__1235$36.out","dwfp_mul_blur_d_stencil_38_1235_1344.b"], + ["fexp_1344.in","dwfp_mul_blur_d_stencil_38_1235_1344.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_39_1235_1347.a"], + ["fconst-1__1235$37.out","dwfp_mul_blur_d_stencil_39_1235_1347.b"], + ["fexp_1347.in","dwfp_mul_blur_d_stencil_39_1235_1347.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_3_1235_1239.a"], + ["fconst-1__1235$1.out","dwfp_mul_blur_d_stencil_3_1235_1239.b"], + ["fexp_1239.in","dwfp_mul_blur_d_stencil_3_1235_1239.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_40_1235_1350.a"], + ["fconst-1__1235$38.out","dwfp_mul_blur_d_stencil_40_1235_1350.b"], + ["fexp_1350.in","dwfp_mul_blur_d_stencil_40_1235_1350.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_41_1235_1353.a"], + ["fconst-1__1235$39.out","dwfp_mul_blur_d_stencil_41_1235_1353.b"], + ["fexp_1353.in","dwfp_mul_blur_d_stencil_41_1235_1353.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_42_1235_1356.a"], + ["fconst-1__1235$40.out","dwfp_mul_blur_d_stencil_42_1235_1356.b"], + ["fexp_1356.in","dwfp_mul_blur_d_stencil_42_1235_1356.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_43_1235_1359.a"], + ["fconst-1__1235$41.out","dwfp_mul_blur_d_stencil_43_1235_1359.b"], + ["fexp_1359.in","dwfp_mul_blur_d_stencil_43_1235_1359.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_44_1235_1362.a"], + ["fconst-1__1235$42.out","dwfp_mul_blur_d_stencil_44_1235_1362.b"], + ["fexp_1362.in","dwfp_mul_blur_d_stencil_44_1235_1362.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_45_1235_1365.a"], + ["fconst-1__1235$43.out","dwfp_mul_blur_d_stencil_45_1235_1365.b"], + ["fexp_1365.in","dwfp_mul_blur_d_stencil_45_1235_1365.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_46_1235_1368.a"], + ["fconst-1__1235$44.out","dwfp_mul_blur_d_stencil_46_1235_1368.b"], + ["fexp_1368.in","dwfp_mul_blur_d_stencil_46_1235_1368.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_47_1235_1371.a"], + ["fconst-1__1235$45.out","dwfp_mul_blur_d_stencil_47_1235_1371.b"], + ["fexp_1371.in","dwfp_mul_blur_d_stencil_47_1235_1371.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_48_1235_1374.a"], + ["fconst-1__1235$46.out","dwfp_mul_blur_d_stencil_48_1235_1374.b"], + ["fexp_1374.in","dwfp_mul_blur_d_stencil_48_1235_1374.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_49_1235_1377.a"], + ["fconst-1__1235$47.out","dwfp_mul_blur_d_stencil_49_1235_1377.b"], + ["fexp_1377.in","dwfp_mul_blur_d_stencil_49_1235_1377.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_4_1235_1242.a"], + ["fconst-1__1235$2.out","dwfp_mul_blur_d_stencil_4_1235_1242.b"], + ["fexp_1242.in","dwfp_mul_blur_d_stencil_4_1235_1242.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_50_1235_1380.a"], + ["fconst-1__1235$48.out","dwfp_mul_blur_d_stencil_50_1235_1380.b"], + ["fexp_1380.in","dwfp_mul_blur_d_stencil_50_1235_1380.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_5_1235_1245.a"], + ["fconst-1__1235$3.out","dwfp_mul_blur_d_stencil_5_1235_1245.b"], + ["fexp_1245.in","dwfp_mul_blur_d_stencil_5_1235_1245.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_6_1235_1248.a"], + ["fconst-1__1235$4.out","dwfp_mul_blur_d_stencil_6_1235_1248.b"], + ["fexp_1248.in","dwfp_mul_blur_d_stencil_6_1235_1248.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_7_1235_1251.a"], + ["fconst-1__1235$5.out","dwfp_mul_blur_d_stencil_7_1235_1251.b"], + ["fexp_1251.in","dwfp_mul_blur_d_stencil_7_1235_1251.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_8_1235_1254.a"], + ["fconst-1__1235$6.out","dwfp_mul_blur_d_stencil_8_1235_1254.b"], + ["fexp_1254.in","dwfp_mul_blur_d_stencil_8_1235_1254.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_9_1235_1257.a"], + ["fconst-1__1235$7.out","dwfp_mul_blur_d_stencil_9_1235_1257.b"], + ["fexp_1257.in","dwfp_mul_blur_d_stencil_9_1235_1257.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_5":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_1942_2134_2135":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1945_2133_2134":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1948_2132_2133":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1951_2131_2132":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1954_2130_2131":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1957_2129_2130":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1960_2128_2129":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1963_2127_2128":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1966_2126_2127":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1969_2125_2126":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1972_2124_2125":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1975_2123_2124":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1978_2122_2123":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1981_2121_2122":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1984_2120_2121":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1987_2119_2120":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1990_2118_2119":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1993_2117_2118":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1996_2116_2117":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_1999_2115_2116":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2002_2114_2115":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2005_2113_2114":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2008_2112_2113":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2011_2111_2112":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2014_2110_2111":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2017_2109_2110":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2020_2108_2109":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2023_2107_2108":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2026_2106_2107":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2029_2105_2106":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2032_2104_2105":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2035_2103_2104":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2038_2102_2103":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2041_2101_2102":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2044_2100_2101":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2047_2099_2100":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2050_2098_2099":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2053_2097_2098":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2056_2096_2097":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2059_2095_2096":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2062_2094_2095":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2065_2093_2094":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2068_2092_2093":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2071_2091_2092":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2074_2090_2091":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2077_2089_2090":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2080_2088_2089":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2083_2087_2088":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_2_2086_2087":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_51_1939_1940":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_52_1939_1943":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_53_1939_1946":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_54_1939_1949":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_55_1939_1952":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_56_1939_1955":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_57_1939_1958":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_58_1939_1961":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_59_1939_1964":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_60_1939_1967":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_61_1939_1970":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_62_1939_1973":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_63_1939_1976":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_64_1939_1979":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_65_1939_1982":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_66_1939_1985":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_67_1939_1988":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_68_1939_1991":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_69_1939_1994":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_70_1939_1997":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_71_1939_2000":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_72_1939_2003":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_73_1939_2006":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_74_1939_2009":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_75_1939_2012":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_76_1939_2015":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_77_1939_2018":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_78_1939_2021":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_79_1939_2024":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_80_1939_2027":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_81_1939_2030":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_82_1939_2033":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_83_1939_2036":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_84_1939_2039":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_85_1939_2042":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_86_1939_2045":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_87_1939_2048":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_88_1939_2051":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_89_1939_2054":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_90_1939_2057":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_91_1939_2060":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_92_1939_2063":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_93_1939_2066":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_94_1939_2069":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_95_1939_2072":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_96_1939_2075":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_97_1939_2078":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_98_1939_2081":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_99_1939_2084":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__1939":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__1939$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_1940":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1943":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1946":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1949":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1952":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1955":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1958":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1961":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1964":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1967":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1970":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1973":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1976":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1979":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1982":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1985":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1988":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1991":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1994":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_1997":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2000":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2003":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2006":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2009":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2012":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2015":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2018":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2021":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2024":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2027":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2030":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2033":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2036":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2039":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2042":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2045":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2048":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2051":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2054":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2057":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2060":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2063":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2066":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2069":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2072":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2075":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2078":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2081":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2084":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942.z","dwfp_add_1942_2134_2135.a"], + ["dwfp_add_1945_2133_2134.z","dwfp_add_1942_2134_2135.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_1942_2134_2135.z"], + ["dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945.z","dwfp_add_1945_2133_2134.a"], + ["dwfp_add_1948_2132_2133.z","dwfp_add_1945_2133_2134.b"], + ["dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948.z","dwfp_add_1948_2132_2133.a"], + ["dwfp_add_1951_2131_2132.z","dwfp_add_1948_2132_2133.b"], + ["dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951.z","dwfp_add_1951_2131_2132.a"], + ["dwfp_add_1954_2130_2131.z","dwfp_add_1951_2131_2132.b"], + ["dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954.z","dwfp_add_1954_2130_2131.a"], + ["dwfp_add_1957_2129_2130.z","dwfp_add_1954_2130_2131.b"], + ["dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957.z","dwfp_add_1957_2129_2130.a"], + ["dwfp_add_1960_2128_2129.z","dwfp_add_1957_2129_2130.b"], + ["dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960.z","dwfp_add_1960_2128_2129.a"], + ["dwfp_add_1963_2127_2128.z","dwfp_add_1960_2128_2129.b"], + ["dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963.z","dwfp_add_1963_2127_2128.a"], + ["dwfp_add_1966_2126_2127.z","dwfp_add_1963_2127_2128.b"], + ["dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966.z","dwfp_add_1966_2126_2127.a"], + ["dwfp_add_1969_2125_2126.z","dwfp_add_1966_2126_2127.b"], + ["dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969.z","dwfp_add_1969_2125_2126.a"], + ["dwfp_add_1972_2124_2125.z","dwfp_add_1969_2125_2126.b"], + ["dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972.z","dwfp_add_1972_2124_2125.a"], + ["dwfp_add_1975_2123_2124.z","dwfp_add_1972_2124_2125.b"], + ["dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975.z","dwfp_add_1975_2123_2124.a"], + ["dwfp_add_1978_2122_2123.z","dwfp_add_1975_2123_2124.b"], + ["dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978.z","dwfp_add_1978_2122_2123.a"], + ["dwfp_add_1981_2121_2122.z","dwfp_add_1978_2122_2123.b"], + ["dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981.z","dwfp_add_1981_2121_2122.a"], + ["dwfp_add_1984_2120_2121.z","dwfp_add_1981_2121_2122.b"], + ["dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984.z","dwfp_add_1984_2120_2121.a"], + ["dwfp_add_1987_2119_2120.z","dwfp_add_1984_2120_2121.b"], + ["dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987.z","dwfp_add_1987_2119_2120.a"], + ["dwfp_add_1990_2118_2119.z","dwfp_add_1987_2119_2120.b"], + ["dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990.z","dwfp_add_1990_2118_2119.a"], + ["dwfp_add_1993_2117_2118.z","dwfp_add_1990_2118_2119.b"], + ["dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993.z","dwfp_add_1993_2117_2118.a"], + ["dwfp_add_1996_2116_2117.z","dwfp_add_1993_2117_2118.b"], + ["dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996.z","dwfp_add_1996_2116_2117.a"], + ["dwfp_add_1999_2115_2116.z","dwfp_add_1996_2116_2117.b"], + ["dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999.z","dwfp_add_1999_2115_2116.a"], + ["dwfp_add_2002_2114_2115.z","dwfp_add_1999_2115_2116.b"], + ["dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002.z","dwfp_add_2002_2114_2115.a"], + ["dwfp_add_2005_2113_2114.z","dwfp_add_2002_2114_2115.b"], + ["dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005.z","dwfp_add_2005_2113_2114.a"], + ["dwfp_add_2008_2112_2113.z","dwfp_add_2005_2113_2114.b"], + ["dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008.z","dwfp_add_2008_2112_2113.a"], + ["dwfp_add_2011_2111_2112.z","dwfp_add_2008_2112_2113.b"], + ["dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011.z","dwfp_add_2011_2111_2112.a"], + ["dwfp_add_2014_2110_2111.z","dwfp_add_2011_2111_2112.b"], + ["dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014.z","dwfp_add_2014_2110_2111.a"], + ["dwfp_add_2017_2109_2110.z","dwfp_add_2014_2110_2111.b"], + ["dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017.z","dwfp_add_2017_2109_2110.a"], + ["dwfp_add_2020_2108_2109.z","dwfp_add_2017_2109_2110.b"], + ["dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020.z","dwfp_add_2020_2108_2109.a"], + ["dwfp_add_2023_2107_2108.z","dwfp_add_2020_2108_2109.b"], + ["dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023.z","dwfp_add_2023_2107_2108.a"], + ["dwfp_add_2026_2106_2107.z","dwfp_add_2023_2107_2108.b"], + ["dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026.z","dwfp_add_2026_2106_2107.a"], + ["dwfp_add_2029_2105_2106.z","dwfp_add_2026_2106_2107.b"], + ["dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029.z","dwfp_add_2029_2105_2106.a"], + ["dwfp_add_2032_2104_2105.z","dwfp_add_2029_2105_2106.b"], + ["dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032.z","dwfp_add_2032_2104_2105.a"], + ["dwfp_add_2035_2103_2104.z","dwfp_add_2032_2104_2105.b"], + ["dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035.z","dwfp_add_2035_2103_2104.a"], + ["dwfp_add_2038_2102_2103.z","dwfp_add_2035_2103_2104.b"], + ["dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038.z","dwfp_add_2038_2102_2103.a"], + ["dwfp_add_2041_2101_2102.z","dwfp_add_2038_2102_2103.b"], + ["dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041.z","dwfp_add_2041_2101_2102.a"], + ["dwfp_add_2044_2100_2101.z","dwfp_add_2041_2101_2102.b"], + ["dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044.z","dwfp_add_2044_2100_2101.a"], + ["dwfp_add_2047_2099_2100.z","dwfp_add_2044_2100_2101.b"], + ["dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047.z","dwfp_add_2047_2099_2100.a"], + ["dwfp_add_2050_2098_2099.z","dwfp_add_2047_2099_2100.b"], + ["dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050.z","dwfp_add_2050_2098_2099.a"], + ["dwfp_add_2053_2097_2098.z","dwfp_add_2050_2098_2099.b"], + ["dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053.z","dwfp_add_2053_2097_2098.a"], + ["dwfp_add_2056_2096_2097.z","dwfp_add_2053_2097_2098.b"], + ["dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056.z","dwfp_add_2056_2096_2097.a"], + ["dwfp_add_2059_2095_2096.z","dwfp_add_2056_2096_2097.b"], + ["dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059.z","dwfp_add_2059_2095_2096.a"], + ["dwfp_add_2062_2094_2095.z","dwfp_add_2059_2095_2096.b"], + ["dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062.z","dwfp_add_2062_2094_2095.a"], + ["dwfp_add_2065_2093_2094.z","dwfp_add_2062_2094_2095.b"], + ["dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065.z","dwfp_add_2065_2093_2094.a"], + ["dwfp_add_2068_2092_2093.z","dwfp_add_2065_2093_2094.b"], + ["dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068.z","dwfp_add_2068_2092_2093.a"], + ["dwfp_add_2071_2091_2092.z","dwfp_add_2068_2092_2093.b"], + ["dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071.z","dwfp_add_2071_2091_2092.a"], + ["dwfp_add_2074_2090_2091.z","dwfp_add_2071_2091_2092.b"], + ["dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074.z","dwfp_add_2074_2090_2091.a"], + ["dwfp_add_2077_2089_2090.z","dwfp_add_2074_2090_2091.b"], + ["dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077.z","dwfp_add_2077_2089_2090.a"], + ["dwfp_add_2080_2088_2089.z","dwfp_add_2077_2089_2090.b"], + ["dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080.z","dwfp_add_2080_2088_2089.a"], + ["dwfp_add_2083_2087_2088.z","dwfp_add_2080_2088_2089.b"], + ["dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083.z","dwfp_add_2083_2087_2088.a"], + ["dwfp_add_non_local_means_sum_stencil_2_2086_2087.z","dwfp_add_2083_2087_2088.b"], + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_2_2086_2087.a"], + ["dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086.z","dwfp_add_non_local_means_sum_stencil_2_2086_2087.b"], + ["fexp_1940.out","dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942.a"], + ["self.in1_hw_input_global_wrapper_stencil.5","dwfp_mul_1941_hw_input_global_wrapper_stencil_56_1942.b"], + ["fexp_1943.out","dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945.a"], + ["self.in1_hw_input_global_wrapper_stencil.6","dwfp_mul_1944_hw_input_global_wrapper_stencil_57_1945.b"], + ["fexp_1946.out","dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948.a"], + ["self.in1_hw_input_global_wrapper_stencil.7","dwfp_mul_1947_hw_input_global_wrapper_stencil_58_1948.b"], + ["fexp_1949.out","dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951.a"], + ["self.in1_hw_input_global_wrapper_stencil.8","dwfp_mul_1950_hw_input_global_wrapper_stencil_59_1951.b"], + ["fexp_1952.out","dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954.a"], + ["self.in1_hw_input_global_wrapper_stencil.9","dwfp_mul_1953_hw_input_global_wrapper_stencil_60_1954.b"], + ["fexp_1955.out","dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957.a"], + ["self.in1_hw_input_global_wrapper_stencil.10","dwfp_mul_1956_hw_input_global_wrapper_stencil_61_1957.b"], + ["fexp_1958.out","dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960.a"], + ["self.in1_hw_input_global_wrapper_stencil.11","dwfp_mul_1959_hw_input_global_wrapper_stencil_62_1960.b"], + ["fexp_1961.out","dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963.a"], + ["self.in1_hw_input_global_wrapper_stencil.12","dwfp_mul_1962_hw_input_global_wrapper_stencil_63_1963.b"], + ["fexp_1964.out","dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966.a"], + ["self.in1_hw_input_global_wrapper_stencil.13","dwfp_mul_1965_hw_input_global_wrapper_stencil_64_1966.b"], + ["fexp_1967.out","dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969.a"], + ["self.in1_hw_input_global_wrapper_stencil.14","dwfp_mul_1968_hw_input_global_wrapper_stencil_65_1969.b"], + ["fexp_1970.out","dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972.a"], + ["self.in1_hw_input_global_wrapper_stencil.15","dwfp_mul_1971_hw_input_global_wrapper_stencil_66_1972.b"], + ["fexp_1973.out","dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975.a"], + ["self.in1_hw_input_global_wrapper_stencil.16","dwfp_mul_1974_hw_input_global_wrapper_stencil_67_1975.b"], + ["fexp_1976.out","dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978.a"], + ["self.in1_hw_input_global_wrapper_stencil.17","dwfp_mul_1977_hw_input_global_wrapper_stencil_68_1978.b"], + ["fexp_1979.out","dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981.a"], + ["self.in1_hw_input_global_wrapper_stencil.18","dwfp_mul_1980_hw_input_global_wrapper_stencil_69_1981.b"], + ["fexp_1982.out","dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984.a"], + ["self.in1_hw_input_global_wrapper_stencil.19","dwfp_mul_1983_hw_input_global_wrapper_stencil_70_1984.b"], + ["fexp_1985.out","dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987.a"], + ["self.in1_hw_input_global_wrapper_stencil.20","dwfp_mul_1986_hw_input_global_wrapper_stencil_71_1987.b"], + ["fexp_1988.out","dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990.a"], + ["self.in1_hw_input_global_wrapper_stencil.21","dwfp_mul_1989_hw_input_global_wrapper_stencil_72_1990.b"], + ["fexp_1991.out","dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993.a"], + ["self.in1_hw_input_global_wrapper_stencil.22","dwfp_mul_1992_hw_input_global_wrapper_stencil_73_1993.b"], + ["fexp_1994.out","dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996.a"], + ["self.in1_hw_input_global_wrapper_stencil.23","dwfp_mul_1995_hw_input_global_wrapper_stencil_74_1996.b"], + ["fexp_1997.out","dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999.a"], + ["self.in1_hw_input_global_wrapper_stencil.24","dwfp_mul_1998_hw_input_global_wrapper_stencil_75_1999.b"], + ["fexp_2000.out","dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002.a"], + ["self.in1_hw_input_global_wrapper_stencil.25","dwfp_mul_2001_hw_input_global_wrapper_stencil_76_2002.b"], + ["fexp_2003.out","dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005.a"], + ["self.in1_hw_input_global_wrapper_stencil.26","dwfp_mul_2004_hw_input_global_wrapper_stencil_77_2005.b"], + ["fexp_2006.out","dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008.a"], + ["self.in1_hw_input_global_wrapper_stencil.27","dwfp_mul_2007_hw_input_global_wrapper_stencil_78_2008.b"], + ["fexp_2009.out","dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011.a"], + ["self.in1_hw_input_global_wrapper_stencil.28","dwfp_mul_2010_hw_input_global_wrapper_stencil_79_2011.b"], + ["fexp_2012.out","dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014.a"], + ["self.in1_hw_input_global_wrapper_stencil.29","dwfp_mul_2013_hw_input_global_wrapper_stencil_80_2014.b"], + ["fexp_2015.out","dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017.a"], + ["self.in1_hw_input_global_wrapper_stencil.30","dwfp_mul_2016_hw_input_global_wrapper_stencil_81_2017.b"], + ["fexp_2018.out","dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020.a"], + ["self.in1_hw_input_global_wrapper_stencil.31","dwfp_mul_2019_hw_input_global_wrapper_stencil_82_2020.b"], + ["fexp_2021.out","dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023.a"], + ["self.in1_hw_input_global_wrapper_stencil.32","dwfp_mul_2022_hw_input_global_wrapper_stencil_83_2023.b"], + ["fexp_2024.out","dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026.a"], + ["self.in1_hw_input_global_wrapper_stencil.33","dwfp_mul_2025_hw_input_global_wrapper_stencil_84_2026.b"], + ["fexp_2027.out","dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029.a"], + ["self.in1_hw_input_global_wrapper_stencil.34","dwfp_mul_2028_hw_input_global_wrapper_stencil_85_2029.b"], + ["fexp_2030.out","dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032.a"], + ["self.in1_hw_input_global_wrapper_stencil.35","dwfp_mul_2031_hw_input_global_wrapper_stencil_86_2032.b"], + ["fexp_2033.out","dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035.a"], + ["self.in1_hw_input_global_wrapper_stencil.36","dwfp_mul_2034_hw_input_global_wrapper_stencil_87_2035.b"], + ["fexp_2036.out","dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038.a"], + ["self.in1_hw_input_global_wrapper_stencil.37","dwfp_mul_2037_hw_input_global_wrapper_stencil_88_2038.b"], + ["fexp_2039.out","dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041.a"], + ["self.in1_hw_input_global_wrapper_stencil.38","dwfp_mul_2040_hw_input_global_wrapper_stencil_89_2041.b"], + ["fexp_2042.out","dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044.a"], + ["self.in1_hw_input_global_wrapper_stencil.39","dwfp_mul_2043_hw_input_global_wrapper_stencil_90_2044.b"], + ["fexp_2045.out","dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047.a"], + ["self.in1_hw_input_global_wrapper_stencil.40","dwfp_mul_2046_hw_input_global_wrapper_stencil_91_2047.b"], + ["fexp_2048.out","dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050.a"], + ["self.in1_hw_input_global_wrapper_stencil.41","dwfp_mul_2049_hw_input_global_wrapper_stencil_92_2050.b"], + ["fexp_2051.out","dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053.a"], + ["self.in1_hw_input_global_wrapper_stencil.42","dwfp_mul_2052_hw_input_global_wrapper_stencil_93_2053.b"], + ["fexp_2054.out","dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056.a"], + ["self.in1_hw_input_global_wrapper_stencil.43","dwfp_mul_2055_hw_input_global_wrapper_stencil_94_2056.b"], + ["fexp_2057.out","dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059.a"], + ["self.in1_hw_input_global_wrapper_stencil.44","dwfp_mul_2058_hw_input_global_wrapper_stencil_95_2059.b"], + ["fexp_2060.out","dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062.a"], + ["self.in1_hw_input_global_wrapper_stencil.45","dwfp_mul_2061_hw_input_global_wrapper_stencil_96_2062.b"], + ["fexp_2063.out","dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065.a"], + ["self.in1_hw_input_global_wrapper_stencil.46","dwfp_mul_2064_hw_input_global_wrapper_stencil_97_2065.b"], + ["fexp_2066.out","dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068.a"], + ["self.in1_hw_input_global_wrapper_stencil.47","dwfp_mul_2067_hw_input_global_wrapper_stencil_98_2068.b"], + ["fexp_2069.out","dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071.a"], + ["self.in1_hw_input_global_wrapper_stencil.48","dwfp_mul_2070_hw_input_global_wrapper_stencil_99_2071.b"], + ["fexp_2072.out","dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_2073_hw_input_global_wrapper_stencil_100_2074.b"], + ["fexp_2075.out","dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077.a"], + ["self.in1_hw_input_global_wrapper_stencil.1","dwfp_mul_2076_hw_input_global_wrapper_stencil_101_2077.b"], + ["fexp_2078.out","dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080.a"], + ["self.in1_hw_input_global_wrapper_stencil.2","dwfp_mul_2079_hw_input_global_wrapper_stencil_102_2080.b"], + ["fexp_2081.out","dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083.a"], + ["self.in1_hw_input_global_wrapper_stencil.3","dwfp_mul_2082_hw_input_global_wrapper_stencil_103_2083.b"], + ["fexp_2084.out","dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086.a"], + ["self.in1_hw_input_global_wrapper_stencil.4","dwfp_mul_2085_hw_input_global_wrapper_stencil_104_2086.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_51_1939_1940.a"], + ["fconst-1__1939.out","dwfp_mul_blur_d_stencil_51_1939_1940.b"], + ["fexp_1940.in","dwfp_mul_blur_d_stencil_51_1939_1940.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_52_1939_1943.a"], + ["fconst-1__1939$1.out","dwfp_mul_blur_d_stencil_52_1939_1943.b"], + ["fexp_1943.in","dwfp_mul_blur_d_stencil_52_1939_1943.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_53_1939_1946.a"], + ["fconst-1__1939$2.out","dwfp_mul_blur_d_stencil_53_1939_1946.b"], + ["fexp_1946.in","dwfp_mul_blur_d_stencil_53_1939_1946.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_54_1939_1949.a"], + ["fconst-1__1939$3.out","dwfp_mul_blur_d_stencil_54_1939_1949.b"], + ["fexp_1949.in","dwfp_mul_blur_d_stencil_54_1939_1949.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_55_1939_1952.a"], + ["fconst-1__1939$4.out","dwfp_mul_blur_d_stencil_55_1939_1952.b"], + ["fexp_1952.in","dwfp_mul_blur_d_stencil_55_1939_1952.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_56_1939_1955.a"], + ["fconst-1__1939$5.out","dwfp_mul_blur_d_stencil_56_1939_1955.b"], + ["fexp_1955.in","dwfp_mul_blur_d_stencil_56_1939_1955.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_57_1939_1958.a"], + ["fconst-1__1939$6.out","dwfp_mul_blur_d_stencil_57_1939_1958.b"], + ["fexp_1958.in","dwfp_mul_blur_d_stencil_57_1939_1958.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_58_1939_1961.a"], + ["fconst-1__1939$7.out","dwfp_mul_blur_d_stencil_58_1939_1961.b"], + ["fexp_1961.in","dwfp_mul_blur_d_stencil_58_1939_1961.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_59_1939_1964.a"], + ["fconst-1__1939$8.out","dwfp_mul_blur_d_stencil_59_1939_1964.b"], + ["fexp_1964.in","dwfp_mul_blur_d_stencil_59_1939_1964.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_60_1939_1967.a"], + ["fconst-1__1939$9.out","dwfp_mul_blur_d_stencil_60_1939_1967.b"], + ["fexp_1967.in","dwfp_mul_blur_d_stencil_60_1939_1967.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_61_1939_1970.a"], + ["fconst-1__1939$10.out","dwfp_mul_blur_d_stencil_61_1939_1970.b"], + ["fexp_1970.in","dwfp_mul_blur_d_stencil_61_1939_1970.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_62_1939_1973.a"], + ["fconst-1__1939$11.out","dwfp_mul_blur_d_stencil_62_1939_1973.b"], + ["fexp_1973.in","dwfp_mul_blur_d_stencil_62_1939_1973.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_63_1939_1976.a"], + ["fconst-1__1939$12.out","dwfp_mul_blur_d_stencil_63_1939_1976.b"], + ["fexp_1976.in","dwfp_mul_blur_d_stencil_63_1939_1976.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_64_1939_1979.a"], + ["fconst-1__1939$13.out","dwfp_mul_blur_d_stencil_64_1939_1979.b"], + ["fexp_1979.in","dwfp_mul_blur_d_stencil_64_1939_1979.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_65_1939_1982.a"], + ["fconst-1__1939$14.out","dwfp_mul_blur_d_stencil_65_1939_1982.b"], + ["fexp_1982.in","dwfp_mul_blur_d_stencil_65_1939_1982.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_66_1939_1985.a"], + ["fconst-1__1939$15.out","dwfp_mul_blur_d_stencil_66_1939_1985.b"], + ["fexp_1985.in","dwfp_mul_blur_d_stencil_66_1939_1985.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_67_1939_1988.a"], + ["fconst-1__1939$16.out","dwfp_mul_blur_d_stencil_67_1939_1988.b"], + ["fexp_1988.in","dwfp_mul_blur_d_stencil_67_1939_1988.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_68_1939_1991.a"], + ["fconst-1__1939$17.out","dwfp_mul_blur_d_stencil_68_1939_1991.b"], + ["fexp_1991.in","dwfp_mul_blur_d_stencil_68_1939_1991.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_69_1939_1994.a"], + ["fconst-1__1939$18.out","dwfp_mul_blur_d_stencil_69_1939_1994.b"], + ["fexp_1994.in","dwfp_mul_blur_d_stencil_69_1939_1994.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_70_1939_1997.a"], + ["fconst-1__1939$19.out","dwfp_mul_blur_d_stencil_70_1939_1997.b"], + ["fexp_1997.in","dwfp_mul_blur_d_stencil_70_1939_1997.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_71_1939_2000.a"], + ["fconst-1__1939$20.out","dwfp_mul_blur_d_stencil_71_1939_2000.b"], + ["fexp_2000.in","dwfp_mul_blur_d_stencil_71_1939_2000.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_72_1939_2003.a"], + ["fconst-1__1939$21.out","dwfp_mul_blur_d_stencil_72_1939_2003.b"], + ["fexp_2003.in","dwfp_mul_blur_d_stencil_72_1939_2003.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_73_1939_2006.a"], + ["fconst-1__1939$22.out","dwfp_mul_blur_d_stencil_73_1939_2006.b"], + ["fexp_2006.in","dwfp_mul_blur_d_stencil_73_1939_2006.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_74_1939_2009.a"], + ["fconst-1__1939$23.out","dwfp_mul_blur_d_stencil_74_1939_2009.b"], + ["fexp_2009.in","dwfp_mul_blur_d_stencil_74_1939_2009.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_75_1939_2012.a"], + ["fconst-1__1939$24.out","dwfp_mul_blur_d_stencil_75_1939_2012.b"], + ["fexp_2012.in","dwfp_mul_blur_d_stencil_75_1939_2012.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_76_1939_2015.a"], + ["fconst-1__1939$25.out","dwfp_mul_blur_d_stencil_76_1939_2015.b"], + ["fexp_2015.in","dwfp_mul_blur_d_stencil_76_1939_2015.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_77_1939_2018.a"], + ["fconst-1__1939$26.out","dwfp_mul_blur_d_stencil_77_1939_2018.b"], + ["fexp_2018.in","dwfp_mul_blur_d_stencil_77_1939_2018.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_78_1939_2021.a"], + ["fconst-1__1939$27.out","dwfp_mul_blur_d_stencil_78_1939_2021.b"], + ["fexp_2021.in","dwfp_mul_blur_d_stencil_78_1939_2021.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_79_1939_2024.a"], + ["fconst-1__1939$28.out","dwfp_mul_blur_d_stencil_79_1939_2024.b"], + ["fexp_2024.in","dwfp_mul_blur_d_stencil_79_1939_2024.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_80_1939_2027.a"], + ["fconst-1__1939$29.out","dwfp_mul_blur_d_stencil_80_1939_2027.b"], + ["fexp_2027.in","dwfp_mul_blur_d_stencil_80_1939_2027.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_81_1939_2030.a"], + ["fconst-1__1939$30.out","dwfp_mul_blur_d_stencil_81_1939_2030.b"], + ["fexp_2030.in","dwfp_mul_blur_d_stencil_81_1939_2030.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_82_1939_2033.a"], + ["fconst-1__1939$31.out","dwfp_mul_blur_d_stencil_82_1939_2033.b"], + ["fexp_2033.in","dwfp_mul_blur_d_stencil_82_1939_2033.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_83_1939_2036.a"], + ["fconst-1__1939$32.out","dwfp_mul_blur_d_stencil_83_1939_2036.b"], + ["fexp_2036.in","dwfp_mul_blur_d_stencil_83_1939_2036.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_84_1939_2039.a"], + ["fconst-1__1939$33.out","dwfp_mul_blur_d_stencil_84_1939_2039.b"], + ["fexp_2039.in","dwfp_mul_blur_d_stencil_84_1939_2039.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_85_1939_2042.a"], + ["fconst-1__1939$34.out","dwfp_mul_blur_d_stencil_85_1939_2042.b"], + ["fexp_2042.in","dwfp_mul_blur_d_stencil_85_1939_2042.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_86_1939_2045.a"], + ["fconst-1__1939$35.out","dwfp_mul_blur_d_stencil_86_1939_2045.b"], + ["fexp_2045.in","dwfp_mul_blur_d_stencil_86_1939_2045.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_87_1939_2048.a"], + ["fconst-1__1939$36.out","dwfp_mul_blur_d_stencil_87_1939_2048.b"], + ["fexp_2048.in","dwfp_mul_blur_d_stencil_87_1939_2048.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_88_1939_2051.a"], + ["fconst-1__1939$37.out","dwfp_mul_blur_d_stencil_88_1939_2051.b"], + ["fexp_2051.in","dwfp_mul_blur_d_stencil_88_1939_2051.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_89_1939_2054.a"], + ["fconst-1__1939$38.out","dwfp_mul_blur_d_stencil_89_1939_2054.b"], + ["fexp_2054.in","dwfp_mul_blur_d_stencil_89_1939_2054.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_90_1939_2057.a"], + ["fconst-1__1939$39.out","dwfp_mul_blur_d_stencil_90_1939_2057.b"], + ["fexp_2057.in","dwfp_mul_blur_d_stencil_90_1939_2057.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_91_1939_2060.a"], + ["fconst-1__1939$40.out","dwfp_mul_blur_d_stencil_91_1939_2060.b"], + ["fexp_2060.in","dwfp_mul_blur_d_stencil_91_1939_2060.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_92_1939_2063.a"], + ["fconst-1__1939$41.out","dwfp_mul_blur_d_stencil_92_1939_2063.b"], + ["fexp_2063.in","dwfp_mul_blur_d_stencil_92_1939_2063.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_93_1939_2066.a"], + ["fconst-1__1939$42.out","dwfp_mul_blur_d_stencil_93_1939_2066.b"], + ["fexp_2066.in","dwfp_mul_blur_d_stencil_93_1939_2066.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_94_1939_2069.a"], + ["fconst-1__1939$43.out","dwfp_mul_blur_d_stencil_94_1939_2069.b"], + ["fexp_2069.in","dwfp_mul_blur_d_stencil_94_1939_2069.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_95_1939_2072.a"], + ["fconst-1__1939$44.out","dwfp_mul_blur_d_stencil_95_1939_2072.b"], + ["fexp_2072.in","dwfp_mul_blur_d_stencil_95_1939_2072.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_96_1939_2075.a"], + ["fconst-1__1939$45.out","dwfp_mul_blur_d_stencil_96_1939_2075.b"], + ["fexp_2075.in","dwfp_mul_blur_d_stencil_96_1939_2075.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_97_1939_2078.a"], + ["fconst-1__1939$46.out","dwfp_mul_blur_d_stencil_97_1939_2078.b"], + ["fexp_2078.in","dwfp_mul_blur_d_stencil_97_1939_2078.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_98_1939_2081.a"], + ["fconst-1__1939$47.out","dwfp_mul_blur_d_stencil_98_1939_2081.b"], + ["fexp_2081.in","dwfp_mul_blur_d_stencil_98_1939_2081.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_99_1939_2084.a"], + ["fconst-1__1939$48.out","dwfp_mul_blur_d_stencil_99_1939_2084.b"], + ["fexp_2084.in","dwfp_mul_blur_d_stencil_99_1939_2084.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_6":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in2_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_2646_2838_2839":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2649_2837_2838":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2652_2836_2837":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2655_2835_2836":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2658_2834_2835":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2661_2833_2834":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2664_2832_2833":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2667_2831_2832":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2670_2830_2831":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2673_2829_2830":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2676_2828_2829":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2679_2827_2828":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2682_2826_2827":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2685_2825_2826":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2688_2824_2825":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2691_2823_2824":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2694_2822_2823":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2697_2821_2822":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2700_2820_2821":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2703_2819_2820":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2706_2818_2819":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2709_2817_2818":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2712_2816_2817":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2715_2815_2816":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2718_2814_2815":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2721_2813_2814":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2724_2812_2813":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2727_2811_2812":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2730_2810_2811":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2733_2809_2810":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2736_2808_2809":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2739_2807_2808":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2742_2806_2807":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2745_2805_2806":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2748_2804_2805":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2751_2803_2804":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2754_2802_2803":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2757_2801_2802":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2760_2800_2801":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2763_2799_2800":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2766_2798_2799":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2769_2797_2798":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2772_2796_2797":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2775_2795_2796":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2778_2794_2795":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2781_2793_2794":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2784_2792_2793":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_2787_2791_2792":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_3_2790_2791":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_100_2643_2644":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_101_2643_2647":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_102_2643_2650":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_103_2643_2653":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_104_2643_2656":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_105_2643_2659":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_106_2643_2662":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_107_2643_2665":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_108_2643_2668":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_109_2643_2671":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_110_2643_2674":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_111_2643_2677":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_112_2643_2680":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_113_2643_2683":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_114_2643_2686":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_115_2643_2689":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_116_2643_2692":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_117_2643_2695":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_118_2643_2698":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_119_2643_2701":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_120_2643_2704":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_121_2643_2707":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_122_2643_2710":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_123_2643_2713":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_124_2643_2716":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_125_2643_2719":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_126_2643_2722":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_127_2643_2725":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_128_2643_2728":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_129_2643_2731":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_130_2643_2734":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_131_2643_2737":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_132_2643_2740":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_133_2643_2743":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_134_2643_2746":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_135_2643_2749":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_136_2643_2752":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_137_2643_2755":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_138_2643_2758":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_139_2643_2761":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_140_2643_2764":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_141_2643_2767":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_142_2643_2770":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_143_2643_2773":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_144_2643_2776":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_145_2643_2779":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_146_2643_2782":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_147_2643_2785":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_148_2643_2788":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__2643":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__2643$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_2644":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2647":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2650":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2653":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2656":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2659":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2662":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2665":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2668":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2671":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2674":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2677":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2680":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2683":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2686":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2689":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2692":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2695":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2698":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2701":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2704":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2707":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2710":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2713":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2716":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2719":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2722":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2725":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2728":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2731":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2734":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2737":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2740":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2743":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2746":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2749":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2752":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2755":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2758":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2761":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2764":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2767":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2770":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2773":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2776":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2779":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2782":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2785":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_2788":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646.z","dwfp_add_2646_2838_2839.a"], + ["dwfp_add_2649_2837_2838.z","dwfp_add_2646_2838_2839.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_2646_2838_2839.z"], + ["dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649.z","dwfp_add_2649_2837_2838.a"], + ["dwfp_add_2652_2836_2837.z","dwfp_add_2649_2837_2838.b"], + ["dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652.z","dwfp_add_2652_2836_2837.a"], + ["dwfp_add_2655_2835_2836.z","dwfp_add_2652_2836_2837.b"], + ["dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655.z","dwfp_add_2655_2835_2836.a"], + ["dwfp_add_2658_2834_2835.z","dwfp_add_2655_2835_2836.b"], + ["dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658.z","dwfp_add_2658_2834_2835.a"], + ["dwfp_add_2661_2833_2834.z","dwfp_add_2658_2834_2835.b"], + ["dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661.z","dwfp_add_2661_2833_2834.a"], + ["dwfp_add_2664_2832_2833.z","dwfp_add_2661_2833_2834.b"], + ["dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664.z","dwfp_add_2664_2832_2833.a"], + ["dwfp_add_2667_2831_2832.z","dwfp_add_2664_2832_2833.b"], + ["dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667.z","dwfp_add_2667_2831_2832.a"], + ["dwfp_add_2670_2830_2831.z","dwfp_add_2667_2831_2832.b"], + ["dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670.z","dwfp_add_2670_2830_2831.a"], + ["dwfp_add_2673_2829_2830.z","dwfp_add_2670_2830_2831.b"], + ["dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673.z","dwfp_add_2673_2829_2830.a"], + ["dwfp_add_2676_2828_2829.z","dwfp_add_2673_2829_2830.b"], + ["dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676.z","dwfp_add_2676_2828_2829.a"], + ["dwfp_add_2679_2827_2828.z","dwfp_add_2676_2828_2829.b"], + ["dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679.z","dwfp_add_2679_2827_2828.a"], + ["dwfp_add_2682_2826_2827.z","dwfp_add_2679_2827_2828.b"], + ["dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682.z","dwfp_add_2682_2826_2827.a"], + ["dwfp_add_2685_2825_2826.z","dwfp_add_2682_2826_2827.b"], + ["dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685.z","dwfp_add_2685_2825_2826.a"], + ["dwfp_add_2688_2824_2825.z","dwfp_add_2685_2825_2826.b"], + ["dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688.z","dwfp_add_2688_2824_2825.a"], + ["dwfp_add_2691_2823_2824.z","dwfp_add_2688_2824_2825.b"], + ["dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691.z","dwfp_add_2691_2823_2824.a"], + ["dwfp_add_2694_2822_2823.z","dwfp_add_2691_2823_2824.b"], + ["dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694.z","dwfp_add_2694_2822_2823.a"], + ["dwfp_add_2697_2821_2822.z","dwfp_add_2694_2822_2823.b"], + ["dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697.z","dwfp_add_2697_2821_2822.a"], + ["dwfp_add_2700_2820_2821.z","dwfp_add_2697_2821_2822.b"], + ["dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700.z","dwfp_add_2700_2820_2821.a"], + ["dwfp_add_2703_2819_2820.z","dwfp_add_2700_2820_2821.b"], + ["dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703.z","dwfp_add_2703_2819_2820.a"], + ["dwfp_add_2706_2818_2819.z","dwfp_add_2703_2819_2820.b"], + ["dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706.z","dwfp_add_2706_2818_2819.a"], + ["dwfp_add_2709_2817_2818.z","dwfp_add_2706_2818_2819.b"], + ["dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709.z","dwfp_add_2709_2817_2818.a"], + ["dwfp_add_2712_2816_2817.z","dwfp_add_2709_2817_2818.b"], + ["dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712.z","dwfp_add_2712_2816_2817.a"], + ["dwfp_add_2715_2815_2816.z","dwfp_add_2712_2816_2817.b"], + ["dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715.z","dwfp_add_2715_2815_2816.a"], + ["dwfp_add_2718_2814_2815.z","dwfp_add_2715_2815_2816.b"], + ["dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718.z","dwfp_add_2718_2814_2815.a"], + ["dwfp_add_2721_2813_2814.z","dwfp_add_2718_2814_2815.b"], + ["dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721.z","dwfp_add_2721_2813_2814.a"], + ["dwfp_add_2724_2812_2813.z","dwfp_add_2721_2813_2814.b"], + ["dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724.z","dwfp_add_2724_2812_2813.a"], + ["dwfp_add_2727_2811_2812.z","dwfp_add_2724_2812_2813.b"], + ["dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727.z","dwfp_add_2727_2811_2812.a"], + ["dwfp_add_2730_2810_2811.z","dwfp_add_2727_2811_2812.b"], + ["dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730.z","dwfp_add_2730_2810_2811.a"], + ["dwfp_add_2733_2809_2810.z","dwfp_add_2730_2810_2811.b"], + ["dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733.z","dwfp_add_2733_2809_2810.a"], + ["dwfp_add_2736_2808_2809.z","dwfp_add_2733_2809_2810.b"], + ["dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736.z","dwfp_add_2736_2808_2809.a"], + ["dwfp_add_2739_2807_2808.z","dwfp_add_2736_2808_2809.b"], + ["dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739.z","dwfp_add_2739_2807_2808.a"], + ["dwfp_add_2742_2806_2807.z","dwfp_add_2739_2807_2808.b"], + ["dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742.z","dwfp_add_2742_2806_2807.a"], + ["dwfp_add_2745_2805_2806.z","dwfp_add_2742_2806_2807.b"], + ["dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745.z","dwfp_add_2745_2805_2806.a"], + ["dwfp_add_2748_2804_2805.z","dwfp_add_2745_2805_2806.b"], + ["dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748.z","dwfp_add_2748_2804_2805.a"], + ["dwfp_add_2751_2803_2804.z","dwfp_add_2748_2804_2805.b"], + ["dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751.z","dwfp_add_2751_2803_2804.a"], + ["dwfp_add_2754_2802_2803.z","dwfp_add_2751_2803_2804.b"], + ["dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754.z","dwfp_add_2754_2802_2803.a"], + ["dwfp_add_2757_2801_2802.z","dwfp_add_2754_2802_2803.b"], + ["dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757.z","dwfp_add_2757_2801_2802.a"], + ["dwfp_add_2760_2800_2801.z","dwfp_add_2757_2801_2802.b"], + ["dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760.z","dwfp_add_2760_2800_2801.a"], + ["dwfp_add_2763_2799_2800.z","dwfp_add_2760_2800_2801.b"], + ["dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763.z","dwfp_add_2763_2799_2800.a"], + ["dwfp_add_2766_2798_2799.z","dwfp_add_2763_2799_2800.b"], + ["dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766.z","dwfp_add_2766_2798_2799.a"], + ["dwfp_add_2769_2797_2798.z","dwfp_add_2766_2798_2799.b"], + ["dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769.z","dwfp_add_2769_2797_2798.a"], + ["dwfp_add_2772_2796_2797.z","dwfp_add_2769_2797_2798.b"], + ["dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772.z","dwfp_add_2772_2796_2797.a"], + ["dwfp_add_2775_2795_2796.z","dwfp_add_2772_2796_2797.b"], + ["dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775.z","dwfp_add_2775_2795_2796.a"], + ["dwfp_add_2778_2794_2795.z","dwfp_add_2775_2795_2796.b"], + ["dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778.z","dwfp_add_2778_2794_2795.a"], + ["dwfp_add_2781_2793_2794.z","dwfp_add_2778_2794_2795.b"], + ["dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781.z","dwfp_add_2781_2793_2794.a"], + ["dwfp_add_2784_2792_2793.z","dwfp_add_2781_2793_2794.b"], + ["dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784.z","dwfp_add_2784_2792_2793.a"], + ["dwfp_add_2787_2791_2792.z","dwfp_add_2784_2792_2793.b"], + ["dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787.z","dwfp_add_2787_2791_2792.a"], + ["dwfp_add_non_local_means_sum_stencil_3_2790_2791.z","dwfp_add_2787_2791_2792.b"], + ["self.in2_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_3_2790_2791.a"], + ["dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790.z","dwfp_add_non_local_means_sum_stencil_3_2790_2791.b"], + ["fexp_2644.out","dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646.a"], + ["self.in1_hw_input_global_wrapper_stencil.0","dwfp_mul_2645_hw_input_global_wrapper_stencil_105_2646.b"], + ["fexp_2647.out","dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649.a"], + ["self.in1_hw_input_global_wrapper_stencil.1","dwfp_mul_2648_hw_input_global_wrapper_stencil_106_2649.b"], + ["fexp_2650.out","dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652.a"], + ["self.in1_hw_input_global_wrapper_stencil.2","dwfp_mul_2651_hw_input_global_wrapper_stencil_107_2652.b"], + ["fexp_2653.out","dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655.a"], + ["self.in1_hw_input_global_wrapper_stencil.3","dwfp_mul_2654_hw_input_global_wrapper_stencil_108_2655.b"], + ["fexp_2656.out","dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658.a"], + ["self.in1_hw_input_global_wrapper_stencil.4","dwfp_mul_2657_hw_input_global_wrapper_stencil_109_2658.b"], + ["fexp_2659.out","dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661.a"], + ["self.in1_hw_input_global_wrapper_stencil.5","dwfp_mul_2660_hw_input_global_wrapper_stencil_110_2661.b"], + ["fexp_2662.out","dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664.a"], + ["self.in1_hw_input_global_wrapper_stencil.6","dwfp_mul_2663_hw_input_global_wrapper_stencil_111_2664.b"], + ["fexp_2665.out","dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667.a"], + ["self.in1_hw_input_global_wrapper_stencil.7","dwfp_mul_2666_hw_input_global_wrapper_stencil_112_2667.b"], + ["fexp_2668.out","dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670.a"], + ["self.in1_hw_input_global_wrapper_stencil.8","dwfp_mul_2669_hw_input_global_wrapper_stencil_113_2670.b"], + ["fexp_2671.out","dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673.a"], + ["self.in1_hw_input_global_wrapper_stencil.9","dwfp_mul_2672_hw_input_global_wrapper_stencil_114_2673.b"], + ["fexp_2674.out","dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676.a"], + ["self.in1_hw_input_global_wrapper_stencil.10","dwfp_mul_2675_hw_input_global_wrapper_stencil_115_2676.b"], + ["fexp_2677.out","dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679.a"], + ["self.in1_hw_input_global_wrapper_stencil.11","dwfp_mul_2678_hw_input_global_wrapper_stencil_116_2679.b"], + ["fexp_2680.out","dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682.a"], + ["self.in1_hw_input_global_wrapper_stencil.12","dwfp_mul_2681_hw_input_global_wrapper_stencil_117_2682.b"], + ["fexp_2683.out","dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685.a"], + ["self.in1_hw_input_global_wrapper_stencil.13","dwfp_mul_2684_hw_input_global_wrapper_stencil_118_2685.b"], + ["fexp_2686.out","dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688.a"], + ["self.in1_hw_input_global_wrapper_stencil.14","dwfp_mul_2687_hw_input_global_wrapper_stencil_119_2688.b"], + ["fexp_2689.out","dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691.a"], + ["self.in1_hw_input_global_wrapper_stencil.15","dwfp_mul_2690_hw_input_global_wrapper_stencil_120_2691.b"], + ["fexp_2692.out","dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694.a"], + ["self.in1_hw_input_global_wrapper_stencil.16","dwfp_mul_2693_hw_input_global_wrapper_stencil_121_2694.b"], + ["fexp_2695.out","dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697.a"], + ["self.in1_hw_input_global_wrapper_stencil.17","dwfp_mul_2696_hw_input_global_wrapper_stencil_122_2697.b"], + ["fexp_2698.out","dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700.a"], + ["self.in1_hw_input_global_wrapper_stencil.18","dwfp_mul_2699_hw_input_global_wrapper_stencil_123_2700.b"], + ["fexp_2701.out","dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703.a"], + ["self.in1_hw_input_global_wrapper_stencil.19","dwfp_mul_2702_hw_input_global_wrapper_stencil_124_2703.b"], + ["fexp_2704.out","dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706.a"], + ["self.in1_hw_input_global_wrapper_stencil.20","dwfp_mul_2705_hw_input_global_wrapper_stencil_125_2706.b"], + ["fexp_2707.out","dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709.a"], + ["self.in1_hw_input_global_wrapper_stencil.21","dwfp_mul_2708_hw_input_global_wrapper_stencil_126_2709.b"], + ["fexp_2710.out","dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712.a"], + ["self.in1_hw_input_global_wrapper_stencil.22","dwfp_mul_2711_hw_input_global_wrapper_stencil_127_2712.b"], + ["fexp_2713.out","dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715.a"], + ["self.in1_hw_input_global_wrapper_stencil.23","dwfp_mul_2714_hw_input_global_wrapper_stencil_128_2715.b"], + ["fexp_2716.out","dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718.a"], + ["self.in1_hw_input_global_wrapper_stencil.24","dwfp_mul_2717_hw_input_global_wrapper_stencil_129_2718.b"], + ["fexp_2719.out","dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721.a"], + ["self.in1_hw_input_global_wrapper_stencil.25","dwfp_mul_2720_hw_input_global_wrapper_stencil_130_2721.b"], + ["fexp_2722.out","dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724.a"], + ["self.in1_hw_input_global_wrapper_stencil.26","dwfp_mul_2723_hw_input_global_wrapper_stencil_131_2724.b"], + ["fexp_2725.out","dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727.a"], + ["self.in1_hw_input_global_wrapper_stencil.27","dwfp_mul_2726_hw_input_global_wrapper_stencil_132_2727.b"], + ["fexp_2728.out","dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730.a"], + ["self.in1_hw_input_global_wrapper_stencil.28","dwfp_mul_2729_hw_input_global_wrapper_stencil_133_2730.b"], + ["fexp_2731.out","dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733.a"], + ["self.in1_hw_input_global_wrapper_stencil.29","dwfp_mul_2732_hw_input_global_wrapper_stencil_134_2733.b"], + ["fexp_2734.out","dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736.a"], + ["self.in1_hw_input_global_wrapper_stencil.30","dwfp_mul_2735_hw_input_global_wrapper_stencil_135_2736.b"], + ["fexp_2737.out","dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739.a"], + ["self.in1_hw_input_global_wrapper_stencil.31","dwfp_mul_2738_hw_input_global_wrapper_stencil_136_2739.b"], + ["fexp_2740.out","dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742.a"], + ["self.in1_hw_input_global_wrapper_stencil.32","dwfp_mul_2741_hw_input_global_wrapper_stencil_137_2742.b"], + ["fexp_2743.out","dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745.a"], + ["self.in1_hw_input_global_wrapper_stencil.33","dwfp_mul_2744_hw_input_global_wrapper_stencil_138_2745.b"], + ["fexp_2746.out","dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748.a"], + ["self.in1_hw_input_global_wrapper_stencil.34","dwfp_mul_2747_hw_input_global_wrapper_stencil_139_2748.b"], + ["fexp_2749.out","dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751.a"], + ["self.in1_hw_input_global_wrapper_stencil.35","dwfp_mul_2750_hw_input_global_wrapper_stencil_140_2751.b"], + ["fexp_2752.out","dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754.a"], + ["self.in1_hw_input_global_wrapper_stencil.36","dwfp_mul_2753_hw_input_global_wrapper_stencil_141_2754.b"], + ["fexp_2755.out","dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757.a"], + ["self.in1_hw_input_global_wrapper_stencil.37","dwfp_mul_2756_hw_input_global_wrapper_stencil_142_2757.b"], + ["fexp_2758.out","dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760.a"], + ["self.in1_hw_input_global_wrapper_stencil.38","dwfp_mul_2759_hw_input_global_wrapper_stencil_143_2760.b"], + ["fexp_2761.out","dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763.a"], + ["self.in1_hw_input_global_wrapper_stencil.39","dwfp_mul_2762_hw_input_global_wrapper_stencil_144_2763.b"], + ["fexp_2764.out","dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766.a"], + ["self.in1_hw_input_global_wrapper_stencil.40","dwfp_mul_2765_hw_input_global_wrapper_stencil_145_2766.b"], + ["fexp_2767.out","dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769.a"], + ["self.in1_hw_input_global_wrapper_stencil.41","dwfp_mul_2768_hw_input_global_wrapper_stencil_146_2769.b"], + ["fexp_2770.out","dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772.a"], + ["self.in1_hw_input_global_wrapper_stencil.42","dwfp_mul_2771_hw_input_global_wrapper_stencil_147_2772.b"], + ["fexp_2773.out","dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775.a"], + ["self.in1_hw_input_global_wrapper_stencil.43","dwfp_mul_2774_hw_input_global_wrapper_stencil_148_2775.b"], + ["fexp_2776.out","dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778.a"], + ["self.in1_hw_input_global_wrapper_stencil.44","dwfp_mul_2777_hw_input_global_wrapper_stencil_149_2778.b"], + ["fexp_2779.out","dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781.a"], + ["self.in1_hw_input_global_wrapper_stencil.45","dwfp_mul_2780_hw_input_global_wrapper_stencil_150_2781.b"], + ["fexp_2782.out","dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784.a"], + ["self.in1_hw_input_global_wrapper_stencil.46","dwfp_mul_2783_hw_input_global_wrapper_stencil_151_2784.b"], + ["fexp_2785.out","dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787.a"], + ["self.in1_hw_input_global_wrapper_stencil.47","dwfp_mul_2786_hw_input_global_wrapper_stencil_152_2787.b"], + ["fexp_2788.out","dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790.a"], + ["self.in1_hw_input_global_wrapper_stencil.48","dwfp_mul_2789_hw_input_global_wrapper_stencil_153_2790.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_100_2643_2644.a"], + ["fconst-1__2643.out","dwfp_mul_blur_d_stencil_100_2643_2644.b"], + ["fexp_2644.in","dwfp_mul_blur_d_stencil_100_2643_2644.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_101_2643_2647.a"], + ["fconst-1__2643$1.out","dwfp_mul_blur_d_stencil_101_2643_2647.b"], + ["fexp_2647.in","dwfp_mul_blur_d_stencil_101_2643_2647.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_102_2643_2650.a"], + ["fconst-1__2643$2.out","dwfp_mul_blur_d_stencil_102_2643_2650.b"], + ["fexp_2650.in","dwfp_mul_blur_d_stencil_102_2643_2650.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_103_2643_2653.a"], + ["fconst-1__2643$3.out","dwfp_mul_blur_d_stencil_103_2643_2653.b"], + ["fexp_2653.in","dwfp_mul_blur_d_stencil_103_2643_2653.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_104_2643_2656.a"], + ["fconst-1__2643$4.out","dwfp_mul_blur_d_stencil_104_2643_2656.b"], + ["fexp_2656.in","dwfp_mul_blur_d_stencil_104_2643_2656.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_105_2643_2659.a"], + ["fconst-1__2643$5.out","dwfp_mul_blur_d_stencil_105_2643_2659.b"], + ["fexp_2659.in","dwfp_mul_blur_d_stencil_105_2643_2659.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_106_2643_2662.a"], + ["fconst-1__2643$6.out","dwfp_mul_blur_d_stencil_106_2643_2662.b"], + ["fexp_2662.in","dwfp_mul_blur_d_stencil_106_2643_2662.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_107_2643_2665.a"], + ["fconst-1__2643$7.out","dwfp_mul_blur_d_stencil_107_2643_2665.b"], + ["fexp_2665.in","dwfp_mul_blur_d_stencil_107_2643_2665.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_108_2643_2668.a"], + ["fconst-1__2643$8.out","dwfp_mul_blur_d_stencil_108_2643_2668.b"], + ["fexp_2668.in","dwfp_mul_blur_d_stencil_108_2643_2668.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_109_2643_2671.a"], + ["fconst-1__2643$9.out","dwfp_mul_blur_d_stencil_109_2643_2671.b"], + ["fexp_2671.in","dwfp_mul_blur_d_stencil_109_2643_2671.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_110_2643_2674.a"], + ["fconst-1__2643$10.out","dwfp_mul_blur_d_stencil_110_2643_2674.b"], + ["fexp_2674.in","dwfp_mul_blur_d_stencil_110_2643_2674.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_111_2643_2677.a"], + ["fconst-1__2643$11.out","dwfp_mul_blur_d_stencil_111_2643_2677.b"], + ["fexp_2677.in","dwfp_mul_blur_d_stencil_111_2643_2677.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_112_2643_2680.a"], + ["fconst-1__2643$12.out","dwfp_mul_blur_d_stencil_112_2643_2680.b"], + ["fexp_2680.in","dwfp_mul_blur_d_stencil_112_2643_2680.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_113_2643_2683.a"], + ["fconst-1__2643$13.out","dwfp_mul_blur_d_stencil_113_2643_2683.b"], + ["fexp_2683.in","dwfp_mul_blur_d_stencil_113_2643_2683.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_114_2643_2686.a"], + ["fconst-1__2643$14.out","dwfp_mul_blur_d_stencil_114_2643_2686.b"], + ["fexp_2686.in","dwfp_mul_blur_d_stencil_114_2643_2686.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_115_2643_2689.a"], + ["fconst-1__2643$15.out","dwfp_mul_blur_d_stencil_115_2643_2689.b"], + ["fexp_2689.in","dwfp_mul_blur_d_stencil_115_2643_2689.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_116_2643_2692.a"], + ["fconst-1__2643$16.out","dwfp_mul_blur_d_stencil_116_2643_2692.b"], + ["fexp_2692.in","dwfp_mul_blur_d_stencil_116_2643_2692.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_117_2643_2695.a"], + ["fconst-1__2643$17.out","dwfp_mul_blur_d_stencil_117_2643_2695.b"], + ["fexp_2695.in","dwfp_mul_blur_d_stencil_117_2643_2695.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_118_2643_2698.a"], + ["fconst-1__2643$18.out","dwfp_mul_blur_d_stencil_118_2643_2698.b"], + ["fexp_2698.in","dwfp_mul_blur_d_stencil_118_2643_2698.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_119_2643_2701.a"], + ["fconst-1__2643$19.out","dwfp_mul_blur_d_stencil_119_2643_2701.b"], + ["fexp_2701.in","dwfp_mul_blur_d_stencil_119_2643_2701.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_120_2643_2704.a"], + ["fconst-1__2643$20.out","dwfp_mul_blur_d_stencil_120_2643_2704.b"], + ["fexp_2704.in","dwfp_mul_blur_d_stencil_120_2643_2704.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_121_2643_2707.a"], + ["fconst-1__2643$21.out","dwfp_mul_blur_d_stencil_121_2643_2707.b"], + ["fexp_2707.in","dwfp_mul_blur_d_stencil_121_2643_2707.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_122_2643_2710.a"], + ["fconst-1__2643$22.out","dwfp_mul_blur_d_stencil_122_2643_2710.b"], + ["fexp_2710.in","dwfp_mul_blur_d_stencil_122_2643_2710.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_123_2643_2713.a"], + ["fconst-1__2643$23.out","dwfp_mul_blur_d_stencil_123_2643_2713.b"], + ["fexp_2713.in","dwfp_mul_blur_d_stencil_123_2643_2713.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_124_2643_2716.a"], + ["fconst-1__2643$24.out","dwfp_mul_blur_d_stencil_124_2643_2716.b"], + ["fexp_2716.in","dwfp_mul_blur_d_stencil_124_2643_2716.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_125_2643_2719.a"], + ["fconst-1__2643$25.out","dwfp_mul_blur_d_stencil_125_2643_2719.b"], + ["fexp_2719.in","dwfp_mul_blur_d_stencil_125_2643_2719.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_126_2643_2722.a"], + ["fconst-1__2643$26.out","dwfp_mul_blur_d_stencil_126_2643_2722.b"], + ["fexp_2722.in","dwfp_mul_blur_d_stencil_126_2643_2722.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_127_2643_2725.a"], + ["fconst-1__2643$27.out","dwfp_mul_blur_d_stencil_127_2643_2725.b"], + ["fexp_2725.in","dwfp_mul_blur_d_stencil_127_2643_2725.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_128_2643_2728.a"], + ["fconst-1__2643$28.out","dwfp_mul_blur_d_stencil_128_2643_2728.b"], + ["fexp_2728.in","dwfp_mul_blur_d_stencil_128_2643_2728.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_129_2643_2731.a"], + ["fconst-1__2643$29.out","dwfp_mul_blur_d_stencil_129_2643_2731.b"], + ["fexp_2731.in","dwfp_mul_blur_d_stencil_129_2643_2731.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_130_2643_2734.a"], + ["fconst-1__2643$30.out","dwfp_mul_blur_d_stencil_130_2643_2734.b"], + ["fexp_2734.in","dwfp_mul_blur_d_stencil_130_2643_2734.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_131_2643_2737.a"], + ["fconst-1__2643$31.out","dwfp_mul_blur_d_stencil_131_2643_2737.b"], + ["fexp_2737.in","dwfp_mul_blur_d_stencil_131_2643_2737.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_132_2643_2740.a"], + ["fconst-1__2643$32.out","dwfp_mul_blur_d_stencil_132_2643_2740.b"], + ["fexp_2740.in","dwfp_mul_blur_d_stencil_132_2643_2740.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_133_2643_2743.a"], + ["fconst-1__2643$33.out","dwfp_mul_blur_d_stencil_133_2643_2743.b"], + ["fexp_2743.in","dwfp_mul_blur_d_stencil_133_2643_2743.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_134_2643_2746.a"], + ["fconst-1__2643$34.out","dwfp_mul_blur_d_stencil_134_2643_2746.b"], + ["fexp_2746.in","dwfp_mul_blur_d_stencil_134_2643_2746.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_135_2643_2749.a"], + ["fconst-1__2643$35.out","dwfp_mul_blur_d_stencil_135_2643_2749.b"], + ["fexp_2749.in","dwfp_mul_blur_d_stencil_135_2643_2749.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_136_2643_2752.a"], + ["fconst-1__2643$36.out","dwfp_mul_blur_d_stencil_136_2643_2752.b"], + ["fexp_2752.in","dwfp_mul_blur_d_stencil_136_2643_2752.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_137_2643_2755.a"], + ["fconst-1__2643$37.out","dwfp_mul_blur_d_stencil_137_2643_2755.b"], + ["fexp_2755.in","dwfp_mul_blur_d_stencil_137_2643_2755.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_138_2643_2758.a"], + ["fconst-1__2643$38.out","dwfp_mul_blur_d_stencil_138_2643_2758.b"], + ["fexp_2758.in","dwfp_mul_blur_d_stencil_138_2643_2758.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_139_2643_2761.a"], + ["fconst-1__2643$39.out","dwfp_mul_blur_d_stencil_139_2643_2761.b"], + ["fexp_2761.in","dwfp_mul_blur_d_stencil_139_2643_2761.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_140_2643_2764.a"], + ["fconst-1__2643$40.out","dwfp_mul_blur_d_stencil_140_2643_2764.b"], + ["fexp_2764.in","dwfp_mul_blur_d_stencil_140_2643_2764.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_141_2643_2767.a"], + ["fconst-1__2643$41.out","dwfp_mul_blur_d_stencil_141_2643_2767.b"], + ["fexp_2767.in","dwfp_mul_blur_d_stencil_141_2643_2767.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_142_2643_2770.a"], + ["fconst-1__2643$42.out","dwfp_mul_blur_d_stencil_142_2643_2770.b"], + ["fexp_2770.in","dwfp_mul_blur_d_stencil_142_2643_2770.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_143_2643_2773.a"], + ["fconst-1__2643$43.out","dwfp_mul_blur_d_stencil_143_2643_2773.b"], + ["fexp_2773.in","dwfp_mul_blur_d_stencil_143_2643_2773.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_144_2643_2776.a"], + ["fconst-1__2643$44.out","dwfp_mul_blur_d_stencil_144_2643_2776.b"], + ["fexp_2776.in","dwfp_mul_blur_d_stencil_144_2643_2776.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_145_2643_2779.a"], + ["fconst-1__2643$45.out","dwfp_mul_blur_d_stencil_145_2643_2779.b"], + ["fexp_2779.in","dwfp_mul_blur_d_stencil_145_2643_2779.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_146_2643_2782.a"], + ["fconst-1__2643$46.out","dwfp_mul_blur_d_stencil_146_2643_2782.b"], + ["fexp_2782.in","dwfp_mul_blur_d_stencil_146_2643_2782.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_147_2643_2785.a"], + ["fconst-1__2643$47.out","dwfp_mul_blur_d_stencil_147_2643_2785.b"], + ["fexp_2785.in","dwfp_mul_blur_d_stencil_147_2643_2785.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_148_2643_2788.a"], + ["fconst-1__2643$48.out","dwfp_mul_blur_d_stencil_148_2643_2788.b"], + ["fexp_2788.in","dwfp_mul_blur_d_stencil_148_2643_2788.z"] + ] + }, + "hcompute_non_local_means_sum_stencil_7":{ + "type":["Record",[ + ["out_non_local_means_sum_stencil",["Array",16,"Bit"]], + ["in0_blur_d_stencil",["Array",49,["Array",16,"BitIn"]]], + ["in1_non_local_means_sum_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "dwfp_add_3300_3444_3445":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3302_3443_3444":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3304_3442_3443":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3306_3441_3442":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3308_3440_3441":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3310_3439_3440":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3312_3438_3439":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3314_3437_3438":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3316_3436_3437":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3318_3435_3436":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3320_3434_3435":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3322_3433_3434":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3324_3432_3433":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3326_3431_3432":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3328_3430_3431":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3330_3429_3430":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3332_3428_3429":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3334_3427_3428":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3336_3426_3427":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3338_3425_3426":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3340_3424_3425":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3342_3423_3424":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3344_3422_3423":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3346_3421_3422":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3348_3420_3421":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3350_3419_3420":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3352_3418_3419":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3354_3417_3418":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3356_3416_3417":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3358_3415_3416":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3360_3414_3415":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3362_3413_3414":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3364_3412_3413":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3366_3411_3412":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3368_3410_3411":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3370_3409_3410":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3372_3408_3409":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3374_3407_3408":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3376_3406_3407":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3378_3405_3406":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3380_3404_3405":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3382_3403_3404":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3384_3402_3403":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3386_3401_3402":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3388_3400_3401":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3390_3399_3400":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3392_3398_3399":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_3394_3397_3398":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_add_non_local_means_sum_stencil_4_3396_3397":{ + "genref":"float_DW.fp_add", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_149_3298_3299":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_150_3298_3301":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_151_3298_3303":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_152_3298_3305":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_153_3298_3307":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_154_3298_3309":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_155_3298_3311":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_156_3298_3313":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_157_3298_3315":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_158_3298_3317":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_159_3298_3319":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_160_3298_3321":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_161_3298_3323":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_162_3298_3325":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_163_3298_3327":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_164_3298_3329":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_165_3298_3331":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_166_3298_3333":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_167_3298_3335":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_168_3298_3337":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_169_3298_3339":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_170_3298_3341":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_171_3298_3343":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_172_3298_3345":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_173_3298_3347":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_174_3298_3349":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_175_3298_3351":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_176_3298_3353":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_177_3298_3355":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_178_3298_3357":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_179_3298_3359":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_180_3298_3361":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_181_3298_3363":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_182_3298_3365":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_183_3298_3367":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_184_3298_3369":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_185_3298_3371":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_186_3298_3373":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_187_3298_3375":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_188_3298_3377":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_189_3298_3379":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_190_3298_3381":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_191_3298_3383":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_192_3298_3385":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_193_3298_3387":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_194_3298_3389":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_195_3298_3391":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_196_3298_3393":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "dwfp_mul_blur_d_stencil_197_3298_3395":{ + "genref":"float_DW.fp_mul", + "genargs":{"exp_width":["Int",8], "ieee_compliance":["Bool",false], "sig_width":["Int",7]} + }, + "fconst-1__3298":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$12":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$13":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$14":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$15":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$16":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$17":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$18":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$19":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$20":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$21":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$22":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$23":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$24":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$25":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$26":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$27":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$28":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$29":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$30":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$31":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$32":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$33":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$34":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$35":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$36":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$37":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$38":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$39":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$40":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$41":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$42":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$43":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$44":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$45":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$46":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$47":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$48":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fconst-1__3298$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hbfb5"]}, + "metadata":{"float_value":"Equivalent float = -1.414062"} + }, + "fexp_3299":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3301":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3303":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3305":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3307":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3309":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3311":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3313":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3315":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3317":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3319":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3321":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3323":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3325":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3327":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3329":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3331":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3333":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3335":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3337":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3339":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3341":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3343":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3345":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3347":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3349":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3351":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3353":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3355":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3357":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3359":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3361":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3363":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3365":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3367":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3369":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3371":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3373":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3375":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3377":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3379":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3381":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3383":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3385":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3387":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3389":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3391":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3393":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + }, + "fexp_3395":{ + "genref":"float.exp", + "genargs":{"exp_bits":["Int",8], "frac_bits":["Int",7]} + } + }, + "connections":[ + ["fexp_3299.out","dwfp_add_3300_3444_3445.a"], + ["dwfp_add_3302_3443_3444.z","dwfp_add_3300_3444_3445.b"], + ["self.out_non_local_means_sum_stencil","dwfp_add_3300_3444_3445.z"], + ["fexp_3301.out","dwfp_add_3302_3443_3444.a"], + ["dwfp_add_3304_3442_3443.z","dwfp_add_3302_3443_3444.b"], + ["fexp_3303.out","dwfp_add_3304_3442_3443.a"], + ["dwfp_add_3306_3441_3442.z","dwfp_add_3304_3442_3443.b"], + ["fexp_3305.out","dwfp_add_3306_3441_3442.a"], + ["dwfp_add_3308_3440_3441.z","dwfp_add_3306_3441_3442.b"], + ["fexp_3307.out","dwfp_add_3308_3440_3441.a"], + ["dwfp_add_3310_3439_3440.z","dwfp_add_3308_3440_3441.b"], + ["fexp_3309.out","dwfp_add_3310_3439_3440.a"], + ["dwfp_add_3312_3438_3439.z","dwfp_add_3310_3439_3440.b"], + ["fexp_3311.out","dwfp_add_3312_3438_3439.a"], + ["dwfp_add_3314_3437_3438.z","dwfp_add_3312_3438_3439.b"], + ["fexp_3313.out","dwfp_add_3314_3437_3438.a"], + ["dwfp_add_3316_3436_3437.z","dwfp_add_3314_3437_3438.b"], + ["fexp_3315.out","dwfp_add_3316_3436_3437.a"], + ["dwfp_add_3318_3435_3436.z","dwfp_add_3316_3436_3437.b"], + ["fexp_3317.out","dwfp_add_3318_3435_3436.a"], + ["dwfp_add_3320_3434_3435.z","dwfp_add_3318_3435_3436.b"], + ["fexp_3319.out","dwfp_add_3320_3434_3435.a"], + ["dwfp_add_3322_3433_3434.z","dwfp_add_3320_3434_3435.b"], + ["fexp_3321.out","dwfp_add_3322_3433_3434.a"], + ["dwfp_add_3324_3432_3433.z","dwfp_add_3322_3433_3434.b"], + ["fexp_3323.out","dwfp_add_3324_3432_3433.a"], + ["dwfp_add_3326_3431_3432.z","dwfp_add_3324_3432_3433.b"], + ["fexp_3325.out","dwfp_add_3326_3431_3432.a"], + ["dwfp_add_3328_3430_3431.z","dwfp_add_3326_3431_3432.b"], + ["fexp_3327.out","dwfp_add_3328_3430_3431.a"], + ["dwfp_add_3330_3429_3430.z","dwfp_add_3328_3430_3431.b"], + ["fexp_3329.out","dwfp_add_3330_3429_3430.a"], + ["dwfp_add_3332_3428_3429.z","dwfp_add_3330_3429_3430.b"], + ["fexp_3331.out","dwfp_add_3332_3428_3429.a"], + ["dwfp_add_3334_3427_3428.z","dwfp_add_3332_3428_3429.b"], + ["fexp_3333.out","dwfp_add_3334_3427_3428.a"], + ["dwfp_add_3336_3426_3427.z","dwfp_add_3334_3427_3428.b"], + ["fexp_3335.out","dwfp_add_3336_3426_3427.a"], + ["dwfp_add_3338_3425_3426.z","dwfp_add_3336_3426_3427.b"], + ["fexp_3337.out","dwfp_add_3338_3425_3426.a"], + ["dwfp_add_3340_3424_3425.z","dwfp_add_3338_3425_3426.b"], + ["fexp_3339.out","dwfp_add_3340_3424_3425.a"], + ["dwfp_add_3342_3423_3424.z","dwfp_add_3340_3424_3425.b"], + ["fexp_3341.out","dwfp_add_3342_3423_3424.a"], + ["dwfp_add_3344_3422_3423.z","dwfp_add_3342_3423_3424.b"], + ["fexp_3343.out","dwfp_add_3344_3422_3423.a"], + ["dwfp_add_3346_3421_3422.z","dwfp_add_3344_3422_3423.b"], + ["fexp_3345.out","dwfp_add_3346_3421_3422.a"], + ["dwfp_add_3348_3420_3421.z","dwfp_add_3346_3421_3422.b"], + ["fexp_3347.out","dwfp_add_3348_3420_3421.a"], + ["dwfp_add_3350_3419_3420.z","dwfp_add_3348_3420_3421.b"], + ["fexp_3349.out","dwfp_add_3350_3419_3420.a"], + ["dwfp_add_3352_3418_3419.z","dwfp_add_3350_3419_3420.b"], + ["fexp_3351.out","dwfp_add_3352_3418_3419.a"], + ["dwfp_add_3354_3417_3418.z","dwfp_add_3352_3418_3419.b"], + ["fexp_3353.out","dwfp_add_3354_3417_3418.a"], + ["dwfp_add_3356_3416_3417.z","dwfp_add_3354_3417_3418.b"], + ["fexp_3355.out","dwfp_add_3356_3416_3417.a"], + ["dwfp_add_3358_3415_3416.z","dwfp_add_3356_3416_3417.b"], + ["fexp_3357.out","dwfp_add_3358_3415_3416.a"], + ["dwfp_add_3360_3414_3415.z","dwfp_add_3358_3415_3416.b"], + ["fexp_3359.out","dwfp_add_3360_3414_3415.a"], + ["dwfp_add_3362_3413_3414.z","dwfp_add_3360_3414_3415.b"], + ["fexp_3361.out","dwfp_add_3362_3413_3414.a"], + ["dwfp_add_3364_3412_3413.z","dwfp_add_3362_3413_3414.b"], + ["fexp_3363.out","dwfp_add_3364_3412_3413.a"], + ["dwfp_add_3366_3411_3412.z","dwfp_add_3364_3412_3413.b"], + ["fexp_3365.out","dwfp_add_3366_3411_3412.a"], + ["dwfp_add_3368_3410_3411.z","dwfp_add_3366_3411_3412.b"], + ["fexp_3367.out","dwfp_add_3368_3410_3411.a"], + ["dwfp_add_3370_3409_3410.z","dwfp_add_3368_3410_3411.b"], + ["fexp_3369.out","dwfp_add_3370_3409_3410.a"], + ["dwfp_add_3372_3408_3409.z","dwfp_add_3370_3409_3410.b"], + ["fexp_3371.out","dwfp_add_3372_3408_3409.a"], + ["dwfp_add_3374_3407_3408.z","dwfp_add_3372_3408_3409.b"], + ["fexp_3373.out","dwfp_add_3374_3407_3408.a"], + ["dwfp_add_3376_3406_3407.z","dwfp_add_3374_3407_3408.b"], + ["fexp_3375.out","dwfp_add_3376_3406_3407.a"], + ["dwfp_add_3378_3405_3406.z","dwfp_add_3376_3406_3407.b"], + ["fexp_3377.out","dwfp_add_3378_3405_3406.a"], + ["dwfp_add_3380_3404_3405.z","dwfp_add_3378_3405_3406.b"], + ["fexp_3379.out","dwfp_add_3380_3404_3405.a"], + ["dwfp_add_3382_3403_3404.z","dwfp_add_3380_3404_3405.b"], + ["fexp_3381.out","dwfp_add_3382_3403_3404.a"], + ["dwfp_add_3384_3402_3403.z","dwfp_add_3382_3403_3404.b"], + ["fexp_3383.out","dwfp_add_3384_3402_3403.a"], + ["dwfp_add_3386_3401_3402.z","dwfp_add_3384_3402_3403.b"], + ["fexp_3385.out","dwfp_add_3386_3401_3402.a"], + ["dwfp_add_3388_3400_3401.z","dwfp_add_3386_3401_3402.b"], + ["fexp_3387.out","dwfp_add_3388_3400_3401.a"], + ["dwfp_add_3390_3399_3400.z","dwfp_add_3388_3400_3401.b"], + ["fexp_3389.out","dwfp_add_3390_3399_3400.a"], + ["dwfp_add_3392_3398_3399.z","dwfp_add_3390_3399_3400.b"], + ["fexp_3391.out","dwfp_add_3392_3398_3399.a"], + ["dwfp_add_3394_3397_3398.z","dwfp_add_3392_3398_3399.b"], + ["fexp_3393.out","dwfp_add_3394_3397_3398.a"], + ["dwfp_add_non_local_means_sum_stencil_4_3396_3397.z","dwfp_add_3394_3397_3398.b"], + ["self.in1_non_local_means_sum_stencil.0","dwfp_add_non_local_means_sum_stencil_4_3396_3397.a"], + ["fexp_3395.out","dwfp_add_non_local_means_sum_stencil_4_3396_3397.b"], + ["self.in0_blur_d_stencil.0","dwfp_mul_blur_d_stencil_149_3298_3299.a"], + ["fconst-1__3298.out","dwfp_mul_blur_d_stencil_149_3298_3299.b"], + ["fexp_3299.in","dwfp_mul_blur_d_stencil_149_3298_3299.z"], + ["self.in0_blur_d_stencil.1","dwfp_mul_blur_d_stencil_150_3298_3301.a"], + ["fconst-1__3298$1.out","dwfp_mul_blur_d_stencil_150_3298_3301.b"], + ["fexp_3301.in","dwfp_mul_blur_d_stencil_150_3298_3301.z"], + ["self.in0_blur_d_stencil.2","dwfp_mul_blur_d_stencil_151_3298_3303.a"], + ["fconst-1__3298$2.out","dwfp_mul_blur_d_stencil_151_3298_3303.b"], + ["fexp_3303.in","dwfp_mul_blur_d_stencil_151_3298_3303.z"], + ["self.in0_blur_d_stencil.3","dwfp_mul_blur_d_stencil_152_3298_3305.a"], + ["fconst-1__3298$3.out","dwfp_mul_blur_d_stencil_152_3298_3305.b"], + ["fexp_3305.in","dwfp_mul_blur_d_stencil_152_3298_3305.z"], + ["self.in0_blur_d_stencil.4","dwfp_mul_blur_d_stencil_153_3298_3307.a"], + ["fconst-1__3298$4.out","dwfp_mul_blur_d_stencil_153_3298_3307.b"], + ["fexp_3307.in","dwfp_mul_blur_d_stencil_153_3298_3307.z"], + ["self.in0_blur_d_stencil.5","dwfp_mul_blur_d_stencil_154_3298_3309.a"], + ["fconst-1__3298$5.out","dwfp_mul_blur_d_stencil_154_3298_3309.b"], + ["fexp_3309.in","dwfp_mul_blur_d_stencil_154_3298_3309.z"], + ["self.in0_blur_d_stencil.6","dwfp_mul_blur_d_stencil_155_3298_3311.a"], + ["fconst-1__3298$6.out","dwfp_mul_blur_d_stencil_155_3298_3311.b"], + ["fexp_3311.in","dwfp_mul_blur_d_stencil_155_3298_3311.z"], + ["self.in0_blur_d_stencil.7","dwfp_mul_blur_d_stencil_156_3298_3313.a"], + ["fconst-1__3298$7.out","dwfp_mul_blur_d_stencil_156_3298_3313.b"], + ["fexp_3313.in","dwfp_mul_blur_d_stencil_156_3298_3313.z"], + ["self.in0_blur_d_stencil.8","dwfp_mul_blur_d_stencil_157_3298_3315.a"], + ["fconst-1__3298$8.out","dwfp_mul_blur_d_stencil_157_3298_3315.b"], + ["fexp_3315.in","dwfp_mul_blur_d_stencil_157_3298_3315.z"], + ["self.in0_blur_d_stencil.9","dwfp_mul_blur_d_stencil_158_3298_3317.a"], + ["fconst-1__3298$9.out","dwfp_mul_blur_d_stencil_158_3298_3317.b"], + ["fexp_3317.in","dwfp_mul_blur_d_stencil_158_3298_3317.z"], + ["self.in0_blur_d_stencil.10","dwfp_mul_blur_d_stencil_159_3298_3319.a"], + ["fconst-1__3298$10.out","dwfp_mul_blur_d_stencil_159_3298_3319.b"], + ["fexp_3319.in","dwfp_mul_blur_d_stencil_159_3298_3319.z"], + ["self.in0_blur_d_stencil.11","dwfp_mul_blur_d_stencil_160_3298_3321.a"], + ["fconst-1__3298$11.out","dwfp_mul_blur_d_stencil_160_3298_3321.b"], + ["fexp_3321.in","dwfp_mul_blur_d_stencil_160_3298_3321.z"], + ["self.in0_blur_d_stencil.12","dwfp_mul_blur_d_stencil_161_3298_3323.a"], + ["fconst-1__3298$12.out","dwfp_mul_blur_d_stencil_161_3298_3323.b"], + ["fexp_3323.in","dwfp_mul_blur_d_stencil_161_3298_3323.z"], + ["self.in0_blur_d_stencil.13","dwfp_mul_blur_d_stencil_162_3298_3325.a"], + ["fconst-1__3298$13.out","dwfp_mul_blur_d_stencil_162_3298_3325.b"], + ["fexp_3325.in","dwfp_mul_blur_d_stencil_162_3298_3325.z"], + ["self.in0_blur_d_stencil.14","dwfp_mul_blur_d_stencil_163_3298_3327.a"], + ["fconst-1__3298$14.out","dwfp_mul_blur_d_stencil_163_3298_3327.b"], + ["fexp_3327.in","dwfp_mul_blur_d_stencil_163_3298_3327.z"], + ["self.in0_blur_d_stencil.15","dwfp_mul_blur_d_stencil_164_3298_3329.a"], + ["fconst-1__3298$15.out","dwfp_mul_blur_d_stencil_164_3298_3329.b"], + ["fexp_3329.in","dwfp_mul_blur_d_stencil_164_3298_3329.z"], + ["self.in0_blur_d_stencil.16","dwfp_mul_blur_d_stencil_165_3298_3331.a"], + ["fconst-1__3298$16.out","dwfp_mul_blur_d_stencil_165_3298_3331.b"], + ["fexp_3331.in","dwfp_mul_blur_d_stencil_165_3298_3331.z"], + ["self.in0_blur_d_stencil.17","dwfp_mul_blur_d_stencil_166_3298_3333.a"], + ["fconst-1__3298$17.out","dwfp_mul_blur_d_stencil_166_3298_3333.b"], + ["fexp_3333.in","dwfp_mul_blur_d_stencil_166_3298_3333.z"], + ["self.in0_blur_d_stencil.18","dwfp_mul_blur_d_stencil_167_3298_3335.a"], + ["fconst-1__3298$18.out","dwfp_mul_blur_d_stencil_167_3298_3335.b"], + ["fexp_3335.in","dwfp_mul_blur_d_stencil_167_3298_3335.z"], + ["self.in0_blur_d_stencil.19","dwfp_mul_blur_d_stencil_168_3298_3337.a"], + ["fconst-1__3298$19.out","dwfp_mul_blur_d_stencil_168_3298_3337.b"], + ["fexp_3337.in","dwfp_mul_blur_d_stencil_168_3298_3337.z"], + ["self.in0_blur_d_stencil.20","dwfp_mul_blur_d_stencil_169_3298_3339.a"], + ["fconst-1__3298$20.out","dwfp_mul_blur_d_stencil_169_3298_3339.b"], + ["fexp_3339.in","dwfp_mul_blur_d_stencil_169_3298_3339.z"], + ["self.in0_blur_d_stencil.21","dwfp_mul_blur_d_stencil_170_3298_3341.a"], + ["fconst-1__3298$21.out","dwfp_mul_blur_d_stencil_170_3298_3341.b"], + ["fexp_3341.in","dwfp_mul_blur_d_stencil_170_3298_3341.z"], + ["self.in0_blur_d_stencil.22","dwfp_mul_blur_d_stencil_171_3298_3343.a"], + ["fconst-1__3298$22.out","dwfp_mul_blur_d_stencil_171_3298_3343.b"], + ["fexp_3343.in","dwfp_mul_blur_d_stencil_171_3298_3343.z"], + ["self.in0_blur_d_stencil.23","dwfp_mul_blur_d_stencil_172_3298_3345.a"], + ["fconst-1__3298$23.out","dwfp_mul_blur_d_stencil_172_3298_3345.b"], + ["fexp_3345.in","dwfp_mul_blur_d_stencil_172_3298_3345.z"], + ["self.in0_blur_d_stencil.24","dwfp_mul_blur_d_stencil_173_3298_3347.a"], + ["fconst-1__3298$24.out","dwfp_mul_blur_d_stencil_173_3298_3347.b"], + ["fexp_3347.in","dwfp_mul_blur_d_stencil_173_3298_3347.z"], + ["self.in0_blur_d_stencil.25","dwfp_mul_blur_d_stencil_174_3298_3349.a"], + ["fconst-1__3298$25.out","dwfp_mul_blur_d_stencil_174_3298_3349.b"], + ["fexp_3349.in","dwfp_mul_blur_d_stencil_174_3298_3349.z"], + ["self.in0_blur_d_stencil.26","dwfp_mul_blur_d_stencil_175_3298_3351.a"], + ["fconst-1__3298$26.out","dwfp_mul_blur_d_stencil_175_3298_3351.b"], + ["fexp_3351.in","dwfp_mul_blur_d_stencil_175_3298_3351.z"], + ["self.in0_blur_d_stencil.27","dwfp_mul_blur_d_stencil_176_3298_3353.a"], + ["fconst-1__3298$27.out","dwfp_mul_blur_d_stencil_176_3298_3353.b"], + ["fexp_3353.in","dwfp_mul_blur_d_stencil_176_3298_3353.z"], + ["self.in0_blur_d_stencil.28","dwfp_mul_blur_d_stencil_177_3298_3355.a"], + ["fconst-1__3298$28.out","dwfp_mul_blur_d_stencil_177_3298_3355.b"], + ["fexp_3355.in","dwfp_mul_blur_d_stencil_177_3298_3355.z"], + ["self.in0_blur_d_stencil.29","dwfp_mul_blur_d_stencil_178_3298_3357.a"], + ["fconst-1__3298$29.out","dwfp_mul_blur_d_stencil_178_3298_3357.b"], + ["fexp_3357.in","dwfp_mul_blur_d_stencil_178_3298_3357.z"], + ["self.in0_blur_d_stencil.30","dwfp_mul_blur_d_stencil_179_3298_3359.a"], + ["fconst-1__3298$30.out","dwfp_mul_blur_d_stencil_179_3298_3359.b"], + ["fexp_3359.in","dwfp_mul_blur_d_stencil_179_3298_3359.z"], + ["self.in0_blur_d_stencil.31","dwfp_mul_blur_d_stencil_180_3298_3361.a"], + ["fconst-1__3298$31.out","dwfp_mul_blur_d_stencil_180_3298_3361.b"], + ["fexp_3361.in","dwfp_mul_blur_d_stencil_180_3298_3361.z"], + ["self.in0_blur_d_stencil.32","dwfp_mul_blur_d_stencil_181_3298_3363.a"], + ["fconst-1__3298$32.out","dwfp_mul_blur_d_stencil_181_3298_3363.b"], + ["fexp_3363.in","dwfp_mul_blur_d_stencil_181_3298_3363.z"], + ["self.in0_blur_d_stencil.33","dwfp_mul_blur_d_stencil_182_3298_3365.a"], + ["fconst-1__3298$33.out","dwfp_mul_blur_d_stencil_182_3298_3365.b"], + ["fexp_3365.in","dwfp_mul_blur_d_stencil_182_3298_3365.z"], + ["self.in0_blur_d_stencil.34","dwfp_mul_blur_d_stencil_183_3298_3367.a"], + ["fconst-1__3298$34.out","dwfp_mul_blur_d_stencil_183_3298_3367.b"], + ["fexp_3367.in","dwfp_mul_blur_d_stencil_183_3298_3367.z"], + ["self.in0_blur_d_stencil.35","dwfp_mul_blur_d_stencil_184_3298_3369.a"], + ["fconst-1__3298$35.out","dwfp_mul_blur_d_stencil_184_3298_3369.b"], + ["fexp_3369.in","dwfp_mul_blur_d_stencil_184_3298_3369.z"], + ["self.in0_blur_d_stencil.36","dwfp_mul_blur_d_stencil_185_3298_3371.a"], + ["fconst-1__3298$36.out","dwfp_mul_blur_d_stencil_185_3298_3371.b"], + ["fexp_3371.in","dwfp_mul_blur_d_stencil_185_3298_3371.z"], + ["self.in0_blur_d_stencil.37","dwfp_mul_blur_d_stencil_186_3298_3373.a"], + ["fconst-1__3298$37.out","dwfp_mul_blur_d_stencil_186_3298_3373.b"], + ["fexp_3373.in","dwfp_mul_blur_d_stencil_186_3298_3373.z"], + ["self.in0_blur_d_stencil.38","dwfp_mul_blur_d_stencil_187_3298_3375.a"], + ["fconst-1__3298$38.out","dwfp_mul_blur_d_stencil_187_3298_3375.b"], + ["fexp_3375.in","dwfp_mul_blur_d_stencil_187_3298_3375.z"], + ["self.in0_blur_d_stencil.39","dwfp_mul_blur_d_stencil_188_3298_3377.a"], + ["fconst-1__3298$39.out","dwfp_mul_blur_d_stencil_188_3298_3377.b"], + ["fexp_3377.in","dwfp_mul_blur_d_stencil_188_3298_3377.z"], + ["self.in0_blur_d_stencil.40","dwfp_mul_blur_d_stencil_189_3298_3379.a"], + ["fconst-1__3298$40.out","dwfp_mul_blur_d_stencil_189_3298_3379.b"], + ["fexp_3379.in","dwfp_mul_blur_d_stencil_189_3298_3379.z"], + ["self.in0_blur_d_stencil.41","dwfp_mul_blur_d_stencil_190_3298_3381.a"], + ["fconst-1__3298$41.out","dwfp_mul_blur_d_stencil_190_3298_3381.b"], + ["fexp_3381.in","dwfp_mul_blur_d_stencil_190_3298_3381.z"], + ["self.in0_blur_d_stencil.42","dwfp_mul_blur_d_stencil_191_3298_3383.a"], + ["fconst-1__3298$42.out","dwfp_mul_blur_d_stencil_191_3298_3383.b"], + ["fexp_3383.in","dwfp_mul_blur_d_stencil_191_3298_3383.z"], + ["self.in0_blur_d_stencil.43","dwfp_mul_blur_d_stencil_192_3298_3385.a"], + ["fconst-1__3298$43.out","dwfp_mul_blur_d_stencil_192_3298_3385.b"], + ["fexp_3385.in","dwfp_mul_blur_d_stencil_192_3298_3385.z"], + ["self.in0_blur_d_stencil.44","dwfp_mul_blur_d_stencil_193_3298_3387.a"], + ["fconst-1__3298$44.out","dwfp_mul_blur_d_stencil_193_3298_3387.b"], + ["fexp_3387.in","dwfp_mul_blur_d_stencil_193_3298_3387.z"], + ["self.in0_blur_d_stencil.45","dwfp_mul_blur_d_stencil_194_3298_3389.a"], + ["fconst-1__3298$45.out","dwfp_mul_blur_d_stencil_194_3298_3389.b"], + ["fexp_3389.in","dwfp_mul_blur_d_stencil_194_3298_3389.z"], + ["self.in0_blur_d_stencil.46","dwfp_mul_blur_d_stencil_195_3298_3391.a"], + ["fconst-1__3298$46.out","dwfp_mul_blur_d_stencil_195_3298_3391.b"], + ["fexp_3391.in","dwfp_mul_blur_d_stencil_195_3298_3391.z"], + ["self.in0_blur_d_stencil.47","dwfp_mul_blur_d_stencil_196_3298_3393.a"], + ["fconst-1__3298$47.out","dwfp_mul_blur_d_stencil_196_3298_3393.b"], + ["fexp_3393.in","dwfp_mul_blur_d_stencil_196_3298_3393.z"], + ["self.in0_blur_d_stencil.48","dwfp_mul_blur_d_stencil_197_3298_3395.a"], + ["fconst-1__3298$48.out","dwfp_mul_blur_d_stencil_197_3298_3395.b"], + ["fexp_3395.in","dwfp_mul_blur_d_stencil_197_3298_3395.z"] + ] + } + } + } +} +} diff --git a/coreir_compute/resnet1_docker_compute.json b/coreir_compute/resnet1_docker_compute.json new file mode 100644 index 000000000..307fb51f3 --- /dev/null +++ b/coreir_compute/resnet1_docker_compute.json @@ -0,0 +1,1086 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_glb_stencil":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__690":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__690.out"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__699":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__699.out"] + ] + }, + "hcompute_output_cgra_stencil_10":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__780":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__780.out"] + ] + }, + "hcompute_output_cgra_stencil_11":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__789":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__789.out"] + ] + }, + "hcompute_output_cgra_stencil_12":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__798":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__798.out"] + ] + }, + "hcompute_output_cgra_stencil_13":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__807":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__807.out"] + ] + }, + "hcompute_output_cgra_stencil_14":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__816":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__816.out"] + ] + }, + "hcompute_output_cgra_stencil_15":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__825":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__825.out"] + ] + }, + "hcompute_output_cgra_stencil_16":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_854_858_859":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_855_856_857":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_1_857_858":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_1_input_cgra_stencil_1_854":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_2_input_cgra_stencil_2_855":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_3_input_cgra_stencil_3_856":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_1_input_cgra_stencil_1_854.out","add_854_858_859.in0"], + ["add_output_cgra_stencil_1_857_858.out","add_854_858_859.in1"], + ["self.out_output_cgra_stencil","add_854_858_859.out"], + ["mul_kernel_cgra_stencil_2_input_cgra_stencil_2_855.out","add_855_856_857.in0"], + ["mul_kernel_cgra_stencil_3_input_cgra_stencil_3_856.out","add_855_856_857.in1"], + ["add_output_cgra_stencil_1_857_858.in1","add_855_856_857.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_1_857_858.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_854.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_854.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_855.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_855.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_856.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_856.in1"] + ] + }, + "hcompute_output_cgra_stencil_17":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_893_897_898":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_894_895_896":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_2_896_897":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_4_input_cgra_stencil_4_893":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_5_input_cgra_stencil_5_894":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_6_input_cgra_stencil_6_895":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_4_input_cgra_stencil_4_893.out","add_893_897_898.in0"], + ["add_output_cgra_stencil_2_896_897.out","add_893_897_898.in1"], + ["self.out_output_cgra_stencil","add_893_897_898.out"], + ["mul_kernel_cgra_stencil_5_input_cgra_stencil_5_894.out","add_894_895_896.in0"], + ["mul_kernel_cgra_stencil_6_input_cgra_stencil_6_895.out","add_894_895_896.in1"], + ["add_output_cgra_stencil_2_896_897.in1","add_894_895_896.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_2_896_897.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_893.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_893.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_894.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_894.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_895.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_895.in1"] + ] + }, + "hcompute_output_cgra_stencil_18":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_932_936_937":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_933_934_935":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_3_935_936":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_7_input_cgra_stencil_7_932":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_8_input_cgra_stencil_8_933":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_9_input_cgra_stencil_9_934":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_7_input_cgra_stencil_7_932.out","add_932_936_937.in0"], + ["add_output_cgra_stencil_3_935_936.out","add_932_936_937.in1"], + ["self.out_output_cgra_stencil","add_932_936_937.out"], + ["mul_kernel_cgra_stencil_8_input_cgra_stencil_8_933.out","add_933_934_935.in0"], + ["mul_kernel_cgra_stencil_9_input_cgra_stencil_9_934.out","add_933_934_935.in1"], + ["add_output_cgra_stencil_3_935_936.in1","add_933_934_935.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_3_935_936.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_932.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_932.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_933.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_933.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_934.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_934.in1"] + ] + }, + "hcompute_output_cgra_stencil_19":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_971_975_976":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_972_973_974":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_4_974_975":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_10_input_cgra_stencil_10_971":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_11_input_cgra_stencil_11_972":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_12_input_cgra_stencil_12_973":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_10_input_cgra_stencil_10_971.out","add_971_975_976.in0"], + ["add_output_cgra_stencil_4_974_975.out","add_971_975_976.in1"], + ["self.out_output_cgra_stencil","add_971_975_976.out"], + ["mul_kernel_cgra_stencil_11_input_cgra_stencil_11_972.out","add_972_973_974.in0"], + ["mul_kernel_cgra_stencil_12_input_cgra_stencil_12_973.out","add_972_973_974.in1"], + ["add_output_cgra_stencil_4_974_975.in1","add_972_973_974.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_4_974_975.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_971.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_971.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_972.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_972.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_973.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_973.in1"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__708":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__708.out"] + ] + }, + "hcompute_output_cgra_stencil_20":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1010_1014_1015":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1011_1012_1013":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_5_1013_1014":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_13_input_cgra_stencil_13_1010":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_14_input_cgra_stencil_14_1011":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_15_input_cgra_stencil_15_1012":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_13_input_cgra_stencil_13_1010.out","add_1010_1014_1015.in0"], + ["add_output_cgra_stencil_5_1013_1014.out","add_1010_1014_1015.in1"], + ["self.out_output_cgra_stencil","add_1010_1014_1015.out"], + ["mul_kernel_cgra_stencil_14_input_cgra_stencil_14_1011.out","add_1011_1012_1013.in0"], + ["mul_kernel_cgra_stencil_15_input_cgra_stencil_15_1012.out","add_1011_1012_1013.in1"], + ["add_output_cgra_stencil_5_1013_1014.in1","add_1011_1012_1013.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_5_1013_1014.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_1010.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_1010.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_1011.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_1011.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_1012.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_1012.in1"] + ] + }, + "hcompute_output_cgra_stencil_21":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1049_1053_1054":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1050_1051_1052":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_6_1052_1053":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_16_input_cgra_stencil_16_1049":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_17_input_cgra_stencil_17_1050":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_18_input_cgra_stencil_18_1051":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_16_input_cgra_stencil_16_1049.out","add_1049_1053_1054.in0"], + ["add_output_cgra_stencil_6_1052_1053.out","add_1049_1053_1054.in1"], + ["self.out_output_cgra_stencil","add_1049_1053_1054.out"], + ["mul_kernel_cgra_stencil_17_input_cgra_stencil_17_1050.out","add_1050_1051_1052.in0"], + ["mul_kernel_cgra_stencil_18_input_cgra_stencil_18_1051.out","add_1050_1051_1052.in1"], + ["add_output_cgra_stencil_6_1052_1053.in1","add_1050_1051_1052.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_6_1052_1053.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_1049.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_1049.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_1050.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_1050.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_1051.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_1051.in1"] + ] + }, + "hcompute_output_cgra_stencil_22":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1088_1092_1093":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1089_1090_1091":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_7_1091_1092":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_19_input_cgra_stencil_19_1088":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_20_input_cgra_stencil_20_1089":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_21_input_cgra_stencil_21_1090":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_19_input_cgra_stencil_19_1088.out","add_1088_1092_1093.in0"], + ["add_output_cgra_stencil_7_1091_1092.out","add_1088_1092_1093.in1"], + ["self.out_output_cgra_stencil","add_1088_1092_1093.out"], + ["mul_kernel_cgra_stencil_20_input_cgra_stencil_20_1089.out","add_1089_1090_1091.in0"], + ["mul_kernel_cgra_stencil_21_input_cgra_stencil_21_1090.out","add_1089_1090_1091.in1"], + ["add_output_cgra_stencil_7_1091_1092.in1","add_1089_1090_1091.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_7_1091_1092.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_1088.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_1088.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_1089.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_1089.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_1090.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_1090.in1"] + ] + }, + "hcompute_output_cgra_stencil_23":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1127_1131_1132":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1128_1129_1130":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_8_1130_1131":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_22_input_cgra_stencil_22_1127":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_23_input_cgra_stencil_23_1128":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_24_input_cgra_stencil_24_1129":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_22_input_cgra_stencil_22_1127.out","add_1127_1131_1132.in0"], + ["add_output_cgra_stencil_8_1130_1131.out","add_1127_1131_1132.in1"], + ["self.out_output_cgra_stencil","add_1127_1131_1132.out"], + ["mul_kernel_cgra_stencil_23_input_cgra_stencil_23_1128.out","add_1128_1129_1130.in0"], + ["mul_kernel_cgra_stencil_24_input_cgra_stencil_24_1129.out","add_1128_1129_1130.in1"], + ["add_output_cgra_stencil_8_1130_1131.in1","add_1128_1129_1130.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_8_1130_1131.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_1127.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_1127.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_1128.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_1128.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_1129.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_1129.in1"] + ] + }, + "hcompute_output_cgra_stencil_24":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1166_1170_1171":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1167_1168_1169":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_9_1169_1170":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1166":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1167":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1168":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1166.out","add_1166_1170_1171.in0"], + ["add_output_cgra_stencil_9_1169_1170.out","add_1166_1170_1171.in1"], + ["self.out_output_cgra_stencil","add_1166_1170_1171.out"], + ["mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1167.out","add_1167_1168_1169.in0"], + ["mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1168.out","add_1167_1168_1169.in1"], + ["add_output_cgra_stencil_9_1169_1170.in1","add_1167_1168_1169.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_9_1169_1170.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1166.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1166.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1167.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1167.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1168.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1168.in1"] + ] + }, + "hcompute_output_cgra_stencil_25":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1205_1209_1210":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1206_1207_1208":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_10_1208_1209":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1205":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1206":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1207":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1205.out","add_1205_1209_1210.in0"], + ["add_output_cgra_stencil_10_1208_1209.out","add_1205_1209_1210.in1"], + ["self.out_output_cgra_stencil","add_1205_1209_1210.out"], + ["mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1206.out","add_1206_1207_1208.in0"], + ["mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1207.out","add_1206_1207_1208.in1"], + ["add_output_cgra_stencil_10_1208_1209.in1","add_1206_1207_1208.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_10_1208_1209.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1205.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1205.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1206.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1206.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1207.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1207.in1"] + ] + }, + "hcompute_output_cgra_stencil_26":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1244_1248_1249":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1245_1246_1247":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_11_1247_1248":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1244":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1245":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1246":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1244.out","add_1244_1248_1249.in0"], + ["add_output_cgra_stencil_11_1247_1248.out","add_1244_1248_1249.in1"], + ["self.out_output_cgra_stencil","add_1244_1248_1249.out"], + ["mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1245.out","add_1245_1246_1247.in0"], + ["mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1246.out","add_1245_1246_1247.in1"], + ["add_output_cgra_stencil_11_1247_1248.in1","add_1245_1246_1247.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_11_1247_1248.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1244.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1244.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1245.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1245.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1246.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1246.in1"] + ] + }, + "hcompute_output_cgra_stencil_27":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1283_1287_1288":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1284_1285_1286":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_12_1286_1287":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1283":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1284":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1285":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1283.out","add_1283_1287_1288.in0"], + ["add_output_cgra_stencil_12_1286_1287.out","add_1283_1287_1288.in1"], + ["self.out_output_cgra_stencil","add_1283_1287_1288.out"], + ["mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1284.out","add_1284_1285_1286.in0"], + ["mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1285.out","add_1284_1285_1286.in1"], + ["add_output_cgra_stencil_12_1286_1287.in1","add_1284_1285_1286.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_12_1286_1287.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1283.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1283.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1284.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1284.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1285.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1285.in1"] + ] + }, + "hcompute_output_cgra_stencil_28":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1322_1326_1327":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1323_1324_1325":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_13_1325_1326":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1322":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1323":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1324":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1322.out","add_1322_1326_1327.in0"], + ["add_output_cgra_stencil_13_1325_1326.out","add_1322_1326_1327.in1"], + ["self.out_output_cgra_stencil","add_1322_1326_1327.out"], + ["mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1323.out","add_1323_1324_1325.in0"], + ["mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1324.out","add_1323_1324_1325.in1"], + ["add_output_cgra_stencil_13_1325_1326.in1","add_1323_1324_1325.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_13_1325_1326.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1322.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1322.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1323.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1323.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1324.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1324.in1"] + ] + }, + "hcompute_output_cgra_stencil_29":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1361_1365_1366":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1362_1363_1364":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_14_1364_1365":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1361":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1362":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1363":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1361.out","add_1361_1365_1366.in0"], + ["add_output_cgra_stencil_14_1364_1365.out","add_1361_1365_1366.in1"], + ["self.out_output_cgra_stencil","add_1361_1365_1366.out"], + ["mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1362.out","add_1362_1363_1364.in0"], + ["mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1363.out","add_1362_1363_1364.in1"], + ["add_output_cgra_stencil_14_1364_1365.in1","add_1362_1363_1364.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_14_1364_1365.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1361.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1361.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1362.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1362.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1363.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1363.in1"] + ] + }, + "hcompute_output_cgra_stencil_3":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__717":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__717.out"] + ] + }, + "hcompute_output_cgra_stencil_30":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1400_1404_1405":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1401_1402_1403":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_15_1403_1404":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1400":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1401":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1402":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1400.out","add_1400_1404_1405.in0"], + ["add_output_cgra_stencil_15_1403_1404.out","add_1400_1404_1405.in1"], + ["self.out_output_cgra_stencil","add_1400_1404_1405.out"], + ["mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1401.out","add_1401_1402_1403.in0"], + ["mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1402.out","add_1401_1402_1403.in1"], + ["add_output_cgra_stencil_15_1403_1404.in1","add_1401_1402_1403.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_15_1403_1404.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1400.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1400.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1401.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1401.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1402.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1402.in1"] + ] + }, + "hcompute_output_cgra_stencil_31":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",3,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1439_1443_1444":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1440_1441_1442":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_16_1442_1443":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1439":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1440":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1441":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1439.out","add_1439_1443_1444.in0"], + ["add_output_cgra_stencil_16_1442_1443.out","add_1439_1443_1444.in1"], + ["self.out_output_cgra_stencil","add_1439_1443_1444.out"], + ["mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1440.out","add_1440_1441_1442.in0"], + ["mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1441.out","add_1440_1441_1442.in1"], + ["add_output_cgra_stencil_16_1442_1443.in1","add_1440_1441_1442.out"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_16_1442_1443.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1439.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1439.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1440.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1440.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1441.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1441.in1"] + ] + }, + "hcompute_output_cgra_stencil_4":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__726":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__726.out"] + ] + }, + "hcompute_output_cgra_stencil_5":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__735":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__735.out"] + ] + }, + "hcompute_output_cgra_stencil_6":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__744":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__744.out"] + ] + }, + "hcompute_output_cgra_stencil_7":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__753":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__753.out"] + ] + }, + "hcompute_output_cgra_stencil_8":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__762":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__762.out"] + ] + }, + "hcompute_output_cgra_stencil_9":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__771":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__771.out"] + ] + }, + "hcompute_output_glb_stencil":{ + "type":["Record",[ + ["out_output_glb_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_glb_stencil","self.in0_output_cgra_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/resnet5_glb_unroll_compute.json b/coreir_compute/resnet5_glb_unroll_compute.json new file mode 100644 index 000000000..6bf59eccb --- /dev/null +++ b/coreir_compute/resnet5_glb_unroll_compute.json @@ -0,0 +1,1090 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil_1":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_glb_stencil":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_glb_stencil_1":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil_1":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil_1":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__696":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__696.out"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__700":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__700.out"] + ] + }, + "hcompute_output_cgra_stencil_10":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_917_931_932":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_918_929_930":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_919_928_929":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_920_927_928":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_921_926_927":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_922_925_926":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_923_924_925":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_3_930_931":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_17_input_cgra_stencil_17_917":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_18_input_cgra_stencil_18_918":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_19_input_cgra_stencil_19_919":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_20_input_cgra_stencil_20_920":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_21_input_cgra_stencil_21_921":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_22_input_cgra_stencil_22_922":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_23_input_cgra_stencil_23_923":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_24_input_cgra_stencil_24_924":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_17_input_cgra_stencil_17_917.out","add_917_931_932.in0"], + ["add_output_cgra_stencil_3_930_931.out","add_917_931_932.in1"], + ["self.out_output_cgra_stencil","add_917_931_932.out"], + ["mul_kernel_cgra_stencil_18_input_cgra_stencil_18_918.out","add_918_929_930.in0"], + ["add_919_928_929.out","add_918_929_930.in1"], + ["add_output_cgra_stencil_3_930_931.in1","add_918_929_930.out"], + ["mul_kernel_cgra_stencil_19_input_cgra_stencil_19_919.out","add_919_928_929.in0"], + ["add_920_927_928.out","add_919_928_929.in1"], + ["mul_kernel_cgra_stencil_20_input_cgra_stencil_20_920.out","add_920_927_928.in0"], + ["add_921_926_927.out","add_920_927_928.in1"], + ["mul_kernel_cgra_stencil_21_input_cgra_stencil_21_921.out","add_921_926_927.in0"], + ["add_922_925_926.out","add_921_926_927.in1"], + ["mul_kernel_cgra_stencil_22_input_cgra_stencil_22_922.out","add_922_925_926.in0"], + ["add_923_924_925.out","add_922_925_926.in1"], + ["mul_kernel_cgra_stencil_23_input_cgra_stencil_23_923.out","add_923_924_925.in0"], + ["mul_kernel_cgra_stencil_24_input_cgra_stencil_24_924.out","add_923_924_925.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_3_930_931.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_917.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_917.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_918.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_918.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_919.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_919.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_920.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_920.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_921.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_921.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_922.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_922.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_923.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_923.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_924.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_924.in1"] + ] + }, + "hcompute_output_cgra_stencil_11":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_988_1002_1003":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_989_1000_1001":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_990_999_1000":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_991_998_999":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_992_997_998":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_993_996_997":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_994_995_996":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_4_1001_1002":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_25_input_cgra_stencil_25_988":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_26_input_cgra_stencil_26_989":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_27_input_cgra_stencil_27_990":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_28_input_cgra_stencil_28_991":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_29_input_cgra_stencil_29_992":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_30_input_cgra_stencil_30_993":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_31_input_cgra_stencil_31_994":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_32_input_cgra_stencil_32_995":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_25_input_cgra_stencil_25_988.out","add_988_1002_1003.in0"], + ["add_output_cgra_stencil_4_1001_1002.out","add_988_1002_1003.in1"], + ["self.out_output_cgra_stencil","add_988_1002_1003.out"], + ["mul_kernel_cgra_stencil_26_input_cgra_stencil_26_989.out","add_989_1000_1001.in0"], + ["add_990_999_1000.out","add_989_1000_1001.in1"], + ["add_output_cgra_stencil_4_1001_1002.in1","add_989_1000_1001.out"], + ["mul_kernel_cgra_stencil_27_input_cgra_stencil_27_990.out","add_990_999_1000.in0"], + ["add_991_998_999.out","add_990_999_1000.in1"], + ["mul_kernel_cgra_stencil_28_input_cgra_stencil_28_991.out","add_991_998_999.in0"], + ["add_992_997_998.out","add_991_998_999.in1"], + ["mul_kernel_cgra_stencil_29_input_cgra_stencil_29_992.out","add_992_997_998.in0"], + ["add_993_996_997.out","add_992_997_998.in1"], + ["mul_kernel_cgra_stencil_30_input_cgra_stencil_30_993.out","add_993_996_997.in0"], + ["add_994_995_996.out","add_993_996_997.in1"], + ["mul_kernel_cgra_stencil_31_input_cgra_stencil_31_994.out","add_994_995_996.in0"], + ["mul_kernel_cgra_stencil_32_input_cgra_stencil_32_995.out","add_994_995_996.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_4_1001_1002.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_988.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_988.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_989.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_989.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_990.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_990.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_991.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_991.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_992.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_992.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_993.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_993.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_994.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_994.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_995.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_995.in1"] + ] + }, + "hcompute_output_cgra_stencil_12":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1059_1073_1074":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1060_1071_1072":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1061_1070_1071":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1062_1069_1070":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1063_1068_1069":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1064_1067_1068":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1065_1066_1067":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_5_1072_1073":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1059":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1060":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1061":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1062":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1063":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1064":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1065":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1066":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1059.out","add_1059_1073_1074.in0"], + ["add_output_cgra_stencil_5_1072_1073.out","add_1059_1073_1074.in1"], + ["self.out_output_cgra_stencil","add_1059_1073_1074.out"], + ["mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1060.out","add_1060_1071_1072.in0"], + ["add_1061_1070_1071.out","add_1060_1071_1072.in1"], + ["add_output_cgra_stencil_5_1072_1073.in1","add_1060_1071_1072.out"], + ["mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1061.out","add_1061_1070_1071.in0"], + ["add_1062_1069_1070.out","add_1061_1070_1071.in1"], + ["mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1062.out","add_1062_1069_1070.in0"], + ["add_1063_1068_1069.out","add_1062_1069_1070.in1"], + ["mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1063.out","add_1063_1068_1069.in0"], + ["add_1064_1067_1068.out","add_1063_1068_1069.in1"], + ["mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1064.out","add_1064_1067_1068.in0"], + ["add_1065_1066_1067.out","add_1064_1067_1068.in1"], + ["mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1065.out","add_1065_1066_1067.in0"], + ["mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1066.out","add_1065_1066_1067.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_5_1072_1073.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1059.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1059.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1060.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1060.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1061.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1061.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1062.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1062.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1063.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1063.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1064.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1064.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1065.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1065.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1066.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1066.in1"] + ] + }, + "hcompute_output_cgra_stencil_13":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1130_1144_1145":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1131_1142_1143":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1132_1141_1142":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1133_1140_1141":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1134_1139_1140":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1135_1138_1139":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1136_1137_1138":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_6_1143_1144":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1130":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1131":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1132":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1133":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1134":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1135":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1136":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1137":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1130.out","add_1130_1144_1145.in0"], + ["add_output_cgra_stencil_6_1143_1144.out","add_1130_1144_1145.in1"], + ["self.out_output_cgra_stencil","add_1130_1144_1145.out"], + ["mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1131.out","add_1131_1142_1143.in0"], + ["add_1132_1141_1142.out","add_1131_1142_1143.in1"], + ["add_output_cgra_stencil_6_1143_1144.in1","add_1131_1142_1143.out"], + ["mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1132.out","add_1132_1141_1142.in0"], + ["add_1133_1140_1141.out","add_1132_1141_1142.in1"], + ["mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1133.out","add_1133_1140_1141.in0"], + ["add_1134_1139_1140.out","add_1133_1140_1141.in1"], + ["mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1134.out","add_1134_1139_1140.in0"], + ["add_1135_1138_1139.out","add_1134_1139_1140.in1"], + ["mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1135.out","add_1135_1138_1139.in0"], + ["add_1136_1137_1138.out","add_1135_1138_1139.in1"], + ["mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1136.out","add_1136_1137_1138.in0"], + ["mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1137.out","add_1136_1137_1138.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_6_1143_1144.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1130.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1130.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1131.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1131.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1132.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1132.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1133.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1133.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1134.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1134.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1135.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1135.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1136.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1136.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1137.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1137.in1"] + ] + }, + "hcompute_output_cgra_stencil_14":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1201_1215_1216":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1202_1213_1214":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1203_1212_1213":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1204_1211_1212":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1205_1210_1211":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1206_1209_1210":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1207_1208_1209":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_7_1214_1215":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1201":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1202":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1203":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1204":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1205":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1206":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1207":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1208":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1201.out","add_1201_1215_1216.in0"], + ["add_output_cgra_stencil_7_1214_1215.out","add_1201_1215_1216.in1"], + ["self.out_output_cgra_stencil","add_1201_1215_1216.out"], + ["mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1202.out","add_1202_1213_1214.in0"], + ["add_1203_1212_1213.out","add_1202_1213_1214.in1"], + ["add_output_cgra_stencil_7_1214_1215.in1","add_1202_1213_1214.out"], + ["mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1203.out","add_1203_1212_1213.in0"], + ["add_1204_1211_1212.out","add_1203_1212_1213.in1"], + ["mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1204.out","add_1204_1211_1212.in0"], + ["add_1205_1210_1211.out","add_1204_1211_1212.in1"], + ["mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1205.out","add_1205_1210_1211.in0"], + ["add_1206_1209_1210.out","add_1205_1210_1211.in1"], + ["mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1206.out","add_1206_1209_1210.in0"], + ["add_1207_1208_1209.out","add_1206_1209_1210.in1"], + ["mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1207.out","add_1207_1208_1209.in0"], + ["mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1208.out","add_1207_1208_1209.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_7_1214_1215.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1201.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1201.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1202.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1202.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1203.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1203.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1204.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1204.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1205.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1205.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1206.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1206.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1207.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1207.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1208.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1208.in1"] + ] + }, + "hcompute_output_cgra_stencil_15":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1272_1286_1287":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1273_1284_1285":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1274_1283_1284":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1275_1282_1283":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1276_1281_1282":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1277_1280_1281":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1278_1279_1280":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_8_1285_1286":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1272":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1273":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1274":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1275":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1276":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1277":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1278":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1279":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1272.out","add_1272_1286_1287.in0"], + ["add_output_cgra_stencil_8_1285_1286.out","add_1272_1286_1287.in1"], + ["self.out_output_cgra_stencil","add_1272_1286_1287.out"], + ["mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1273.out","add_1273_1284_1285.in0"], + ["add_1274_1283_1284.out","add_1273_1284_1285.in1"], + ["add_output_cgra_stencil_8_1285_1286.in1","add_1273_1284_1285.out"], + ["mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1274.out","add_1274_1283_1284.in0"], + ["add_1275_1282_1283.out","add_1274_1283_1284.in1"], + ["mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1275.out","add_1275_1282_1283.in0"], + ["add_1276_1281_1282.out","add_1275_1282_1283.in1"], + ["mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1276.out","add_1276_1281_1282.in0"], + ["add_1277_1280_1281.out","add_1276_1281_1282.in1"], + ["mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1277.out","add_1277_1280_1281.in0"], + ["add_1278_1279_1280.out","add_1277_1280_1281.in1"], + ["mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1278.out","add_1278_1279_1280.in0"], + ["mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1279.out","add_1278_1279_1280.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_8_1285_1286.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1272.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1272.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1273.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1273.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1274.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1274.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1275.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1275.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1276.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1276.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1277.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1277.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1278.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1278.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1279.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1279.in1"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__705":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__705.out"] + ] + }, + "hcompute_output_cgra_stencil_3":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__710":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__710.out"] + ] + }, + "hcompute_output_cgra_stencil_4":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__715":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__715.out"] + ] + }, + "hcompute_output_cgra_stencil_5":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__720":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__720.out"] + ] + }, + "hcompute_output_cgra_stencil_6":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__725":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__725.out"] + ] + }, + "hcompute_output_cgra_stencil_7":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__730":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__730.out"] + ] + }, + "hcompute_output_cgra_stencil_8":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_776_790_791":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_777_788_789":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_778_787_788":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_779_786_787":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_780_785_786":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_781_784_785":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_782_783_784":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_1_789_790":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_1_input_cgra_stencil_1_776":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_2_input_cgra_stencil_2_777":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_3_input_cgra_stencil_3_778":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_4_input_cgra_stencil_4_779":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_5_input_cgra_stencil_5_780":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_6_input_cgra_stencil_6_781":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_7_input_cgra_stencil_7_782":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_8_input_cgra_stencil_8_783":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_1_input_cgra_stencil_1_776.out","add_776_790_791.in0"], + ["add_output_cgra_stencil_1_789_790.out","add_776_790_791.in1"], + ["self.out_output_cgra_stencil","add_776_790_791.out"], + ["mul_kernel_cgra_stencil_2_input_cgra_stencil_2_777.out","add_777_788_789.in0"], + ["add_778_787_788.out","add_777_788_789.in1"], + ["add_output_cgra_stencil_1_789_790.in1","add_777_788_789.out"], + ["mul_kernel_cgra_stencil_3_input_cgra_stencil_3_778.out","add_778_787_788.in0"], + ["add_779_786_787.out","add_778_787_788.in1"], + ["mul_kernel_cgra_stencil_4_input_cgra_stencil_4_779.out","add_779_786_787.in0"], + ["add_780_785_786.out","add_779_786_787.in1"], + ["mul_kernel_cgra_stencil_5_input_cgra_stencil_5_780.out","add_780_785_786.in0"], + ["add_781_784_785.out","add_780_785_786.in1"], + ["mul_kernel_cgra_stencil_6_input_cgra_stencil_6_781.out","add_781_784_785.in0"], + ["add_782_783_784.out","add_781_784_785.in1"], + ["mul_kernel_cgra_stencil_7_input_cgra_stencil_7_782.out","add_782_783_784.in0"], + ["mul_kernel_cgra_stencil_8_input_cgra_stencil_8_783.out","add_782_783_784.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_1_789_790.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_776.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_776.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_777.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_777.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_778.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_778.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_779.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_779.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_780.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_780.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_781.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_781.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_782.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_782.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_783.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_783.in1"] + ] + }, + "hcompute_output_cgra_stencil_9":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_846_860_861":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_847_858_859":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_848_857_858":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_849_856_857":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_850_855_856":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_851_854_855":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_852_853_854":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_2_859_860":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_10_input_cgra_stencil_10_847":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_11_input_cgra_stencil_11_848":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_12_input_cgra_stencil_12_849":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_13_input_cgra_stencil_13_850":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_14_input_cgra_stencil_14_851":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_15_input_cgra_stencil_15_852":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_16_input_cgra_stencil_16_853":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_9_input_cgra_stencil_9_846":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_9_input_cgra_stencil_9_846.out","add_846_860_861.in0"], + ["add_output_cgra_stencil_2_859_860.out","add_846_860_861.in1"], + ["self.out_output_cgra_stencil","add_846_860_861.out"], + ["mul_kernel_cgra_stencil_10_input_cgra_stencil_10_847.out","add_847_858_859.in0"], + ["add_848_857_858.out","add_847_858_859.in1"], + ["add_output_cgra_stencil_2_859_860.in1","add_847_858_859.out"], + ["mul_kernel_cgra_stencil_11_input_cgra_stencil_11_848.out","add_848_857_858.in0"], + ["add_849_856_857.out","add_848_857_858.in1"], + ["mul_kernel_cgra_stencil_12_input_cgra_stencil_12_849.out","add_849_856_857.in0"], + ["add_850_855_856.out","add_849_856_857.in1"], + ["mul_kernel_cgra_stencil_13_input_cgra_stencil_13_850.out","add_850_855_856.in0"], + ["add_851_854_855.out","add_850_855_856.in1"], + ["mul_kernel_cgra_stencil_14_input_cgra_stencil_14_851.out","add_851_854_855.in0"], + ["add_852_853_854.out","add_851_854_855.in1"], + ["mul_kernel_cgra_stencil_15_input_cgra_stencil_15_852.out","add_852_853_854.in0"], + ["mul_kernel_cgra_stencil_16_input_cgra_stencil_16_853.out","add_852_853_854.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_2_859_860.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_847.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_847.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_848.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_848.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_849.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_849.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_850.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_850.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_851.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_851.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_852.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_852.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_853.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_853.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_846.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_846.in1"] + ] + }, + "hcompute_output_glb_stencil":{ + "type":["Record",[ + ["out_output_glb_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_glb_stencil","self.in0_output_cgra_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/resnet5_x_unroll_compute.json b/coreir_compute/resnet5_x_unroll_compute.json new file mode 100644 index 000000000..65dcd70f1 --- /dev/null +++ b/coreir_compute/resnet5_x_unroll_compute.json @@ -0,0 +1,1090 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil_1":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_glb_stencil":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_glb_stencil_1":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil_1":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil_1":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__698":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__698.out"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__702":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__702.out"] + ] + }, + "hcompute_output_cgra_stencil_10":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_922_936_937":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_923_934_935":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_924_933_934":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_925_932_933":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_926_931_932":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_927_930_931":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_928_929_930":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_3_935_936":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_17_input_cgra_stencil_17_922":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_18_input_cgra_stencil_18_923":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_19_input_cgra_stencil_19_924":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_20_input_cgra_stencil_20_925":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_21_input_cgra_stencil_21_926":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_22_input_cgra_stencil_22_927":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_23_input_cgra_stencil_23_928":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_24_input_cgra_stencil_24_929":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_17_input_cgra_stencil_17_922.out","add_922_936_937.in0"], + ["add_output_cgra_stencil_3_935_936.out","add_922_936_937.in1"], + ["self.out_output_cgra_stencil","add_922_936_937.out"], + ["mul_kernel_cgra_stencil_18_input_cgra_stencil_18_923.out","add_923_934_935.in0"], + ["add_924_933_934.out","add_923_934_935.in1"], + ["add_output_cgra_stencil_3_935_936.in1","add_923_934_935.out"], + ["mul_kernel_cgra_stencil_19_input_cgra_stencil_19_924.out","add_924_933_934.in0"], + ["add_925_932_933.out","add_924_933_934.in1"], + ["mul_kernel_cgra_stencil_20_input_cgra_stencil_20_925.out","add_925_932_933.in0"], + ["add_926_931_932.out","add_925_932_933.in1"], + ["mul_kernel_cgra_stencil_21_input_cgra_stencil_21_926.out","add_926_931_932.in0"], + ["add_927_930_931.out","add_926_931_932.in1"], + ["mul_kernel_cgra_stencil_22_input_cgra_stencil_22_927.out","add_927_930_931.in0"], + ["add_928_929_930.out","add_927_930_931.in1"], + ["mul_kernel_cgra_stencil_23_input_cgra_stencil_23_928.out","add_928_929_930.in0"], + ["mul_kernel_cgra_stencil_24_input_cgra_stencil_24_929.out","add_928_929_930.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_3_935_936.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_922.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_922.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_923.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_923.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_924.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_924.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_925.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_925.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_926.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_926.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_927.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_927.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_928.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_928.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_929.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_929.in1"] + ] + }, + "hcompute_output_cgra_stencil_11":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_991_1005_1006":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_992_1003_1004":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_993_1002_1003":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_994_1001_1002":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_995_1000_1001":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_996_999_1000":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_997_998_999":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_4_1004_1005":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_25_input_cgra_stencil_25_991":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_26_input_cgra_stencil_26_992":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_27_input_cgra_stencil_27_993":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_28_input_cgra_stencil_28_994":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_29_input_cgra_stencil_29_995":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_30_input_cgra_stencil_30_996":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_31_input_cgra_stencil_31_997":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_32_input_cgra_stencil_32_998":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_25_input_cgra_stencil_25_991.out","add_991_1005_1006.in0"], + ["add_output_cgra_stencil_4_1004_1005.out","add_991_1005_1006.in1"], + ["self.out_output_cgra_stencil","add_991_1005_1006.out"], + ["mul_kernel_cgra_stencil_26_input_cgra_stencil_26_992.out","add_992_1003_1004.in0"], + ["add_993_1002_1003.out","add_992_1003_1004.in1"], + ["add_output_cgra_stencil_4_1004_1005.in1","add_992_1003_1004.out"], + ["mul_kernel_cgra_stencil_27_input_cgra_stencil_27_993.out","add_993_1002_1003.in0"], + ["add_994_1001_1002.out","add_993_1002_1003.in1"], + ["mul_kernel_cgra_stencil_28_input_cgra_stencil_28_994.out","add_994_1001_1002.in0"], + ["add_995_1000_1001.out","add_994_1001_1002.in1"], + ["mul_kernel_cgra_stencil_29_input_cgra_stencil_29_995.out","add_995_1000_1001.in0"], + ["add_996_999_1000.out","add_995_1000_1001.in1"], + ["mul_kernel_cgra_stencil_30_input_cgra_stencil_30_996.out","add_996_999_1000.in0"], + ["add_997_998_999.out","add_996_999_1000.in1"], + ["mul_kernel_cgra_stencil_31_input_cgra_stencil_31_997.out","add_997_998_999.in0"], + ["mul_kernel_cgra_stencil_32_input_cgra_stencil_32_998.out","add_997_998_999.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_4_1004_1005.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_991.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_991.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_992.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_992.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_993.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_993.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_994.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_994.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_995.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_995.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_996.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_996.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_997.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_997.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_998.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_998.in1"] + ] + }, + "hcompute_output_cgra_stencil_12":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1060_1074_1075":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1061_1072_1073":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1062_1071_1072":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1063_1070_1071":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1064_1069_1070":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1065_1068_1069":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1066_1067_1068":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_5_1073_1074":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1060":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1061":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1062":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1063":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1064":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1065":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1066":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1067":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1060.out","add_1060_1074_1075.in0"], + ["add_output_cgra_stencil_5_1073_1074.out","add_1060_1074_1075.in1"], + ["self.out_output_cgra_stencil","add_1060_1074_1075.out"], + ["mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1061.out","add_1061_1072_1073.in0"], + ["add_1062_1071_1072.out","add_1061_1072_1073.in1"], + ["add_output_cgra_stencil_5_1073_1074.in1","add_1061_1072_1073.out"], + ["mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1062.out","add_1062_1071_1072.in0"], + ["add_1063_1070_1071.out","add_1062_1071_1072.in1"], + ["mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1063.out","add_1063_1070_1071.in0"], + ["add_1064_1069_1070.out","add_1063_1070_1071.in1"], + ["mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1064.out","add_1064_1069_1070.in0"], + ["add_1065_1068_1069.out","add_1064_1069_1070.in1"], + ["mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1065.out","add_1065_1068_1069.in0"], + ["add_1066_1067_1068.out","add_1065_1068_1069.in1"], + ["mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1066.out","add_1066_1067_1068.in0"], + ["mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1067.out","add_1066_1067_1068.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_5_1073_1074.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1060.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1060.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1061.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1061.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1062.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1062.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1063.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1063.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1064.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1064.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1065.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1065.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1066.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1066.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1067.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1067.in1"] + ] + }, + "hcompute_output_cgra_stencil_13":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1129_1143_1144":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1130_1141_1142":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1131_1140_1141":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1132_1139_1140":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1133_1138_1139":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1134_1137_1138":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1135_1136_1137":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_6_1142_1143":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1129":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1130":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1131":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1132":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1133":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1134":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1135":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1136":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1129.out","add_1129_1143_1144.in0"], + ["add_output_cgra_stencil_6_1142_1143.out","add_1129_1143_1144.in1"], + ["self.out_output_cgra_stencil","add_1129_1143_1144.out"], + ["mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1130.out","add_1130_1141_1142.in0"], + ["add_1131_1140_1141.out","add_1130_1141_1142.in1"], + ["add_output_cgra_stencil_6_1142_1143.in1","add_1130_1141_1142.out"], + ["mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1131.out","add_1131_1140_1141.in0"], + ["add_1132_1139_1140.out","add_1131_1140_1141.in1"], + ["mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1132.out","add_1132_1139_1140.in0"], + ["add_1133_1138_1139.out","add_1132_1139_1140.in1"], + ["mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1133.out","add_1133_1138_1139.in0"], + ["add_1134_1137_1138.out","add_1133_1138_1139.in1"], + ["mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1134.out","add_1134_1137_1138.in0"], + ["add_1135_1136_1137.out","add_1134_1137_1138.in1"], + ["mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1135.out","add_1135_1136_1137.in0"], + ["mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1136.out","add_1135_1136_1137.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_6_1142_1143.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1129.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1129.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1130.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1130.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1131.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1131.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1132.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1132.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1133.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1133.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1134.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1134.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1135.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1135.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1136.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1136.in1"] + ] + }, + "hcompute_output_cgra_stencil_14":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1198_1212_1213":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1199_1210_1211":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1200_1209_1210":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1201_1208_1209":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1202_1207_1208":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1203_1206_1207":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1204_1205_1206":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_7_1211_1212":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1198":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1199":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1200":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1201":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1202":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1203":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1204":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1205":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1198.out","add_1198_1212_1213.in0"], + ["add_output_cgra_stencil_7_1211_1212.out","add_1198_1212_1213.in1"], + ["self.out_output_cgra_stencil","add_1198_1212_1213.out"], + ["mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1199.out","add_1199_1210_1211.in0"], + ["add_1200_1209_1210.out","add_1199_1210_1211.in1"], + ["add_output_cgra_stencil_7_1211_1212.in1","add_1199_1210_1211.out"], + ["mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1200.out","add_1200_1209_1210.in0"], + ["add_1201_1208_1209.out","add_1200_1209_1210.in1"], + ["mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1201.out","add_1201_1208_1209.in0"], + ["add_1202_1207_1208.out","add_1201_1208_1209.in1"], + ["mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1202.out","add_1202_1207_1208.in0"], + ["add_1203_1206_1207.out","add_1202_1207_1208.in1"], + ["mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1203.out","add_1203_1206_1207.in0"], + ["add_1204_1205_1206.out","add_1203_1206_1207.in1"], + ["mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1204.out","add_1204_1205_1206.in0"], + ["mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1205.out","add_1204_1205_1206.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_7_1211_1212.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1198.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1198.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1199.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1199.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1200.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1200.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1201.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1201.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1202.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1202.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1203.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1203.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1204.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1204.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1205.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1205.in1"] + ] + }, + "hcompute_output_cgra_stencil_15":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1267_1281_1282":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1268_1279_1280":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1269_1278_1279":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1270_1277_1278":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1271_1276_1277":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1272_1275_1276":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1273_1274_1275":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_8_1280_1281":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1267":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1268":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1269":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1270":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1271":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1272":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1273":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1274":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1267.out","add_1267_1281_1282.in0"], + ["add_output_cgra_stencil_8_1280_1281.out","add_1267_1281_1282.in1"], + ["self.out_output_cgra_stencil","add_1267_1281_1282.out"], + ["mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1268.out","add_1268_1279_1280.in0"], + ["add_1269_1278_1279.out","add_1268_1279_1280.in1"], + ["add_output_cgra_stencil_8_1280_1281.in1","add_1268_1279_1280.out"], + ["mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1269.out","add_1269_1278_1279.in0"], + ["add_1270_1277_1278.out","add_1269_1278_1279.in1"], + ["mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1270.out","add_1270_1277_1278.in0"], + ["add_1271_1276_1277.out","add_1270_1277_1278.in1"], + ["mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1271.out","add_1271_1276_1277.in0"], + ["add_1272_1275_1276.out","add_1271_1276_1277.in1"], + ["mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1272.out","add_1272_1275_1276.in0"], + ["add_1273_1274_1275.out","add_1272_1275_1276.in1"], + ["mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1273.out","add_1273_1274_1275.in0"], + ["mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1274.out","add_1273_1274_1275.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_8_1280_1281.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1267.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1267.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1268.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1268.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1269.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1269.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1270.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1270.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1271.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1271.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1272.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1272.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1273.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1273.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1274.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1274.in1"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__707":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__707.out"] + ] + }, + "hcompute_output_cgra_stencil_3":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__712":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__712.out"] + ] + }, + "hcompute_output_cgra_stencil_4":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__717":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__717.out"] + ] + }, + "hcompute_output_cgra_stencil_5":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__722":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__722.out"] + ] + }, + "hcompute_output_cgra_stencil_6":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__727":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__727.out"] + ] + }, + "hcompute_output_cgra_stencil_7":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__732":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__732.out"] + ] + }, + "hcompute_output_cgra_stencil_8":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_785_799_800":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_786_797_798":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_787_796_797":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_788_795_796":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_789_794_795":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_790_793_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_791_792_793":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_1_798_799":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_1_input_cgra_stencil_1_785":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_2_input_cgra_stencil_2_786":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_3_input_cgra_stencil_3_787":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_4_input_cgra_stencil_4_788":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_5_input_cgra_stencil_5_789":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_6_input_cgra_stencil_6_790":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_7_input_cgra_stencil_7_791":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_8_input_cgra_stencil_8_792":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_1_input_cgra_stencil_1_785.out","add_785_799_800.in0"], + ["add_output_cgra_stencil_1_798_799.out","add_785_799_800.in1"], + ["self.out_output_cgra_stencil","add_785_799_800.out"], + ["mul_kernel_cgra_stencil_2_input_cgra_stencil_2_786.out","add_786_797_798.in0"], + ["add_787_796_797.out","add_786_797_798.in1"], + ["add_output_cgra_stencil_1_798_799.in1","add_786_797_798.out"], + ["mul_kernel_cgra_stencil_3_input_cgra_stencil_3_787.out","add_787_796_797.in0"], + ["add_788_795_796.out","add_787_796_797.in1"], + ["mul_kernel_cgra_stencil_4_input_cgra_stencil_4_788.out","add_788_795_796.in0"], + ["add_789_794_795.out","add_788_795_796.in1"], + ["mul_kernel_cgra_stencil_5_input_cgra_stencil_5_789.out","add_789_794_795.in0"], + ["add_790_793_794.out","add_789_794_795.in1"], + ["mul_kernel_cgra_stencil_6_input_cgra_stencil_6_790.out","add_790_793_794.in0"], + ["add_791_792_793.out","add_790_793_794.in1"], + ["mul_kernel_cgra_stencil_7_input_cgra_stencil_7_791.out","add_791_792_793.in0"], + ["mul_kernel_cgra_stencil_8_input_cgra_stencil_8_792.out","add_791_792_793.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_1_798_799.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_785.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_785.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_786.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_786.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_787.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_787.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_788.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_788.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_789.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_789.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_790.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_790.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_791.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_791.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_792.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_792.in1"] + ] + }, + "hcompute_output_cgra_stencil_9":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_853_867_868":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_854_865_866":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_855_864_865":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_856_863_864":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_857_862_863":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_858_861_862":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_859_860_861":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_2_866_867":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_10_input_cgra_stencil_10_854":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_11_input_cgra_stencil_11_855":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_12_input_cgra_stencil_12_856":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_13_input_cgra_stencil_13_857":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_14_input_cgra_stencil_14_858":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_15_input_cgra_stencil_15_859":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_16_input_cgra_stencil_16_860":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_9_input_cgra_stencil_9_853":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_9_input_cgra_stencil_9_853.out","add_853_867_868.in0"], + ["add_output_cgra_stencil_2_866_867.out","add_853_867_868.in1"], + ["self.out_output_cgra_stencil","add_853_867_868.out"], + ["mul_kernel_cgra_stencil_10_input_cgra_stencil_10_854.out","add_854_865_866.in0"], + ["add_855_864_865.out","add_854_865_866.in1"], + ["add_output_cgra_stencil_2_866_867.in1","add_854_865_866.out"], + ["mul_kernel_cgra_stencil_11_input_cgra_stencil_11_855.out","add_855_864_865.in0"], + ["add_856_863_864.out","add_855_864_865.in1"], + ["mul_kernel_cgra_stencil_12_input_cgra_stencil_12_856.out","add_856_863_864.in0"], + ["add_857_862_863.out","add_856_863_864.in1"], + ["mul_kernel_cgra_stencil_13_input_cgra_stencil_13_857.out","add_857_862_863.in0"], + ["add_858_861_862.out","add_857_862_863.in1"], + ["mul_kernel_cgra_stencil_14_input_cgra_stencil_14_858.out","add_858_861_862.in0"], + ["add_859_860_861.out","add_858_861_862.in1"], + ["mul_kernel_cgra_stencil_15_input_cgra_stencil_15_859.out","add_859_860_861.in0"], + ["mul_kernel_cgra_stencil_16_input_cgra_stencil_16_860.out","add_859_860_861.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_2_866_867.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_854.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_854.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_855.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_855.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_856.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_856.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_857.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_857.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_858.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_858.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_859.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_859.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_860.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_860.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_853.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_853.in1"] + ] + }, + "hcompute_output_glb_stencil":{ + "type":["Record",[ + ["out_output_glb_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_glb_stencil","self.in0_output_cgra_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/resnet5_x_unroll_mic_compute.json b/coreir_compute/resnet5_x_unroll_mic_compute.json new file mode 100644 index 000000000..33e0de86f --- /dev/null +++ b/coreir_compute/resnet5_x_unroll_mic_compute.json @@ -0,0 +1,1108 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil_1":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil_2":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil_3":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_glb_stencil":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_glb_stencil_1":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_glb_stencil_2":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_input_glb_stencil_3":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__696":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__696.out"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__700":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__700.out"] + ] + }, + "hcompute_output_cgra_stencil_10":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_949_963_964":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_950_961_962":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_951_960_961":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_952_959_960":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_953_958_959":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_954_957_958":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_955_956_957":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_3_962_963":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_17_input_cgra_stencil_17_949":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_18_input_cgra_stencil_18_950":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_19_input_cgra_stencil_19_951":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_20_input_cgra_stencil_20_952":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_21_input_cgra_stencil_21_953":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_22_input_cgra_stencil_22_954":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_23_input_cgra_stencil_23_955":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_24_input_cgra_stencil_24_956":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_17_input_cgra_stencil_17_949.out","add_949_963_964.in0"], + ["add_output_cgra_stencil_3_962_963.out","add_949_963_964.in1"], + ["self.out_output_cgra_stencil","add_949_963_964.out"], + ["mul_kernel_cgra_stencil_18_input_cgra_stencil_18_950.out","add_950_961_962.in0"], + ["add_951_960_961.out","add_950_961_962.in1"], + ["add_output_cgra_stencil_3_962_963.in1","add_950_961_962.out"], + ["mul_kernel_cgra_stencil_19_input_cgra_stencil_19_951.out","add_951_960_961.in0"], + ["add_952_959_960.out","add_951_960_961.in1"], + ["mul_kernel_cgra_stencil_20_input_cgra_stencil_20_952.out","add_952_959_960.in0"], + ["add_953_958_959.out","add_952_959_960.in1"], + ["mul_kernel_cgra_stencil_21_input_cgra_stencil_21_953.out","add_953_958_959.in0"], + ["add_954_957_958.out","add_953_958_959.in1"], + ["mul_kernel_cgra_stencil_22_input_cgra_stencil_22_954.out","add_954_957_958.in0"], + ["add_955_956_957.out","add_954_957_958.in1"], + ["mul_kernel_cgra_stencil_23_input_cgra_stencil_23_955.out","add_955_956_957.in0"], + ["mul_kernel_cgra_stencil_24_input_cgra_stencil_24_956.out","add_955_956_957.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_3_962_963.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_949.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_949.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_950.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_950.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_951.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_951.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_952.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_952.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_953.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_953.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_954.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_954.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_955.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_955.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_956.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_956.in1"] + ] + }, + "hcompute_output_cgra_stencil_11":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1026_1040_1041":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1027_1038_1039":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1028_1037_1038":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1029_1036_1037":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1030_1035_1036":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1031_1034_1035":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1032_1033_1034":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_4_1039_1040":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1026":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1027":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1028":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1029":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1030":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1031":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1032":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1033":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1026.out","add_1026_1040_1041.in0"], + ["add_output_cgra_stencil_4_1039_1040.out","add_1026_1040_1041.in1"], + ["self.out_output_cgra_stencil","add_1026_1040_1041.out"], + ["mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1027.out","add_1027_1038_1039.in0"], + ["add_1028_1037_1038.out","add_1027_1038_1039.in1"], + ["add_output_cgra_stencil_4_1039_1040.in1","add_1027_1038_1039.out"], + ["mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1028.out","add_1028_1037_1038.in0"], + ["add_1029_1036_1037.out","add_1028_1037_1038.in1"], + ["mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1029.out","add_1029_1036_1037.in0"], + ["add_1030_1035_1036.out","add_1029_1036_1037.in1"], + ["mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1030.out","add_1030_1035_1036.in0"], + ["add_1031_1034_1035.out","add_1030_1035_1036.in1"], + ["mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1031.out","add_1031_1034_1035.in0"], + ["add_1032_1033_1034.out","add_1031_1034_1035.in1"], + ["mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1032.out","add_1032_1033_1034.in0"], + ["mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1033.out","add_1032_1033_1034.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_4_1039_1040.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1026.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1026.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1027.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1027.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1028.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1028.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1029.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1029.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1030.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1030.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1031.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1031.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1032.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1032.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1033.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1033.in1"] + ] + }, + "hcompute_output_cgra_stencil_12":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1103_1117_1118":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1104_1115_1116":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1105_1114_1115":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1106_1113_1114":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1107_1112_1113":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1108_1111_1112":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1109_1110_1111":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_5_1116_1117":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1103":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1104":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1105":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1106":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1107":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1108":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1109":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1110":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1103.out","add_1103_1117_1118.in0"], + ["add_output_cgra_stencil_5_1116_1117.out","add_1103_1117_1118.in1"], + ["self.out_output_cgra_stencil","add_1103_1117_1118.out"], + ["mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1104.out","add_1104_1115_1116.in0"], + ["add_1105_1114_1115.out","add_1104_1115_1116.in1"], + ["add_output_cgra_stencil_5_1116_1117.in1","add_1104_1115_1116.out"], + ["mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1105.out","add_1105_1114_1115.in0"], + ["add_1106_1113_1114.out","add_1105_1114_1115.in1"], + ["mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1106.out","add_1106_1113_1114.in0"], + ["add_1107_1112_1113.out","add_1106_1113_1114.in1"], + ["mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1107.out","add_1107_1112_1113.in0"], + ["add_1108_1111_1112.out","add_1107_1112_1113.in1"], + ["mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1108.out","add_1108_1111_1112.in0"], + ["add_1109_1110_1111.out","add_1108_1111_1112.in1"], + ["mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1109.out","add_1109_1110_1111.in0"], + ["mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1110.out","add_1109_1110_1111.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_5_1116_1117.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1103.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1103.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1104.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1104.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1105.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1105.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1106.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1106.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1107.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1107.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1108.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1108.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1109.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1109.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1110.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1110.in1"] + ] + }, + "hcompute_output_cgra_stencil_13":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1180_1194_1195":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1181_1192_1193":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1182_1191_1192":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1183_1190_1191":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1184_1189_1190":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1185_1188_1189":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1186_1187_1188":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_6_1193_1194":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1180":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1181":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1182":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1183":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1184":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1185":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1186":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1187":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1180.out","add_1180_1194_1195.in0"], + ["add_output_cgra_stencil_6_1193_1194.out","add_1180_1194_1195.in1"], + ["self.out_output_cgra_stencil","add_1180_1194_1195.out"], + ["mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1181.out","add_1181_1192_1193.in0"], + ["add_1182_1191_1192.out","add_1181_1192_1193.in1"], + ["add_output_cgra_stencil_6_1193_1194.in1","add_1181_1192_1193.out"], + ["mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1182.out","add_1182_1191_1192.in0"], + ["add_1183_1190_1191.out","add_1182_1191_1192.in1"], + ["mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1183.out","add_1183_1190_1191.in0"], + ["add_1184_1189_1190.out","add_1183_1190_1191.in1"], + ["mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1184.out","add_1184_1189_1190.in0"], + ["add_1185_1188_1189.out","add_1184_1189_1190.in1"], + ["mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1185.out","add_1185_1188_1189.in0"], + ["add_1186_1187_1188.out","add_1185_1188_1189.in1"], + ["mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1186.out","add_1186_1187_1188.in0"], + ["mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1187.out","add_1186_1187_1188.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_6_1193_1194.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1180.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1180.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1181.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1181.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1182.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1182.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1183.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1183.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1184.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1184.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1185.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1185.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1186.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1186.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1187.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1187.in1"] + ] + }, + "hcompute_output_cgra_stencil_14":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1257_1271_1272":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1258_1269_1270":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1259_1268_1269":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1260_1267_1268":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1261_1266_1267":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1262_1265_1266":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1263_1264_1265":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_7_1270_1271":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257.out","add_1257_1271_1272.in0"], + ["add_output_cgra_stencil_7_1270_1271.out","add_1257_1271_1272.in1"], + ["self.out_output_cgra_stencil","add_1257_1271_1272.out"], + ["mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258.out","add_1258_1269_1270.in0"], + ["add_1259_1268_1269.out","add_1258_1269_1270.in1"], + ["add_output_cgra_stencil_7_1270_1271.in1","add_1258_1269_1270.out"], + ["mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259.out","add_1259_1268_1269.in0"], + ["add_1260_1267_1268.out","add_1259_1268_1269.in1"], + ["mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260.out","add_1260_1267_1268.in0"], + ["add_1261_1266_1267.out","add_1260_1267_1268.in1"], + ["mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261.out","add_1261_1266_1267.in0"], + ["add_1262_1265_1266.out","add_1261_1266_1267.in1"], + ["mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262.out","add_1262_1265_1266.in0"], + ["add_1263_1264_1265.out","add_1262_1265_1266.in1"], + ["mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263.out","add_1263_1264_1265.in0"], + ["mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264.out","add_1263_1264_1265.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_7_1270_1271.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264.in1"] + ] + }, + "hcompute_output_cgra_stencil_15":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1334_1348_1349":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1335_1346_1347":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1336_1345_1346":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1337_1344_1345":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1338_1343_1344":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1339_1342_1343":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1340_1341_1342":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_8_1347_1348":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1334":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1335":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1336":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1337":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1338":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1339":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1340":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1341":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1334.out","add_1334_1348_1349.in0"], + ["add_output_cgra_stencil_8_1347_1348.out","add_1334_1348_1349.in1"], + ["self.out_output_cgra_stencil","add_1334_1348_1349.out"], + ["mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1335.out","add_1335_1346_1347.in0"], + ["add_1336_1345_1346.out","add_1335_1346_1347.in1"], + ["add_output_cgra_stencil_8_1347_1348.in1","add_1335_1346_1347.out"], + ["mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1336.out","add_1336_1345_1346.in0"], + ["add_1337_1344_1345.out","add_1336_1345_1346.in1"], + ["mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1337.out","add_1337_1344_1345.in0"], + ["add_1338_1343_1344.out","add_1337_1344_1345.in1"], + ["mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1338.out","add_1338_1343_1344.in0"], + ["add_1339_1342_1343.out","add_1338_1343_1344.in1"], + ["mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1339.out","add_1339_1342_1343.in0"], + ["add_1340_1341_1342.out","add_1339_1342_1343.in1"], + ["mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1340.out","add_1340_1341_1342.in0"], + ["mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1341.out","add_1340_1341_1342.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_8_1347_1348.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1334.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1334.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1335.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1335.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1336.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1336.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1337.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1337.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1338.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1338.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1339.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1339.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1340.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1340.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1341.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1341.in1"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__705":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__705.out"] + ] + }, + "hcompute_output_cgra_stencil_3":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__710":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__710.out"] + ] + }, + "hcompute_output_cgra_stencil_4":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__715":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__715.out"] + ] + }, + "hcompute_output_cgra_stencil_5":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__720":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__720.out"] + ] + }, + "hcompute_output_cgra_stencil_6":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__725":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__725.out"] + ] + }, + "hcompute_output_cgra_stencil_7":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__730":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__730.out"] + ] + }, + "hcompute_output_cgra_stencil_8":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_796_810_811":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_797_808_809":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_798_807_808":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_799_806_807":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_800_805_806":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_801_804_805":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_802_803_804":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_1_809_810":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_1_input_cgra_stencil_1_796":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_2_input_cgra_stencil_2_797":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_3_input_cgra_stencil_3_798":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_4_input_cgra_stencil_4_799":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_5_input_cgra_stencil_5_800":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_6_input_cgra_stencil_6_801":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_7_input_cgra_stencil_7_802":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_8_input_cgra_stencil_8_803":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_1_input_cgra_stencil_1_796.out","add_796_810_811.in0"], + ["add_output_cgra_stencil_1_809_810.out","add_796_810_811.in1"], + ["self.out_output_cgra_stencil","add_796_810_811.out"], + ["mul_kernel_cgra_stencil_2_input_cgra_stencil_2_797.out","add_797_808_809.in0"], + ["add_798_807_808.out","add_797_808_809.in1"], + ["add_output_cgra_stencil_1_809_810.in1","add_797_808_809.out"], + ["mul_kernel_cgra_stencil_3_input_cgra_stencil_3_798.out","add_798_807_808.in0"], + ["add_799_806_807.out","add_798_807_808.in1"], + ["mul_kernel_cgra_stencil_4_input_cgra_stencil_4_799.out","add_799_806_807.in0"], + ["add_800_805_806.out","add_799_806_807.in1"], + ["mul_kernel_cgra_stencil_5_input_cgra_stencil_5_800.out","add_800_805_806.in0"], + ["add_801_804_805.out","add_800_805_806.in1"], + ["mul_kernel_cgra_stencil_6_input_cgra_stencil_6_801.out","add_801_804_805.in0"], + ["add_802_803_804.out","add_801_804_805.in1"], + ["mul_kernel_cgra_stencil_7_input_cgra_stencil_7_802.out","add_802_803_804.in0"], + ["mul_kernel_cgra_stencil_8_input_cgra_stencil_8_803.out","add_802_803_804.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_1_809_810.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_796.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_796.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_797.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_797.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_798.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_798.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_799.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_799.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_800.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_800.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_801.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_801.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_802.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_802.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_803.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_803.in1"] + ] + }, + "hcompute_output_cgra_stencil_9":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_872_886_887":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_873_884_885":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_874_883_884":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_875_882_883":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_876_881_882":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_877_880_881":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_878_879_880":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_2_885_886":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_10_input_cgra_stencil_10_873":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_11_input_cgra_stencil_11_874":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_12_input_cgra_stencil_12_875":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_13_input_cgra_stencil_13_876":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_14_input_cgra_stencil_14_877":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_15_input_cgra_stencil_15_878":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_16_input_cgra_stencil_16_879":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_9_input_cgra_stencil_9_872":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_9_input_cgra_stencil_9_872.out","add_872_886_887.in0"], + ["add_output_cgra_stencil_2_885_886.out","add_872_886_887.in1"], + ["self.out_output_cgra_stencil","add_872_886_887.out"], + ["mul_kernel_cgra_stencil_10_input_cgra_stencil_10_873.out","add_873_884_885.in0"], + ["add_874_883_884.out","add_873_884_885.in1"], + ["add_output_cgra_stencil_2_885_886.in1","add_873_884_885.out"], + ["mul_kernel_cgra_stencil_11_input_cgra_stencil_11_874.out","add_874_883_884.in0"], + ["add_875_882_883.out","add_874_883_884.in1"], + ["mul_kernel_cgra_stencil_12_input_cgra_stencil_12_875.out","add_875_882_883.in0"], + ["add_876_881_882.out","add_875_882_883.in1"], + ["mul_kernel_cgra_stencil_13_input_cgra_stencil_13_876.out","add_876_881_882.in0"], + ["add_877_880_881.out","add_876_881_882.in1"], + ["mul_kernel_cgra_stencil_14_input_cgra_stencil_14_877.out","add_877_880_881.in0"], + ["add_878_879_880.out","add_877_880_881.in1"], + ["mul_kernel_cgra_stencil_15_input_cgra_stencil_15_878.out","add_878_879_880.in0"], + ["mul_kernel_cgra_stencil_16_input_cgra_stencil_16_879.out","add_878_879_880.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_2_885_886.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_873.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_873.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_874.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_874.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_875.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_875.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_876.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_876.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_877.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_877.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_878.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_878.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_879.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_879.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_872.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_872.in1"] + ] + }, + "hcompute_output_glb_stencil":{ + "type":["Record",[ + ["out_output_glb_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_glb_stencil","self.in0_output_cgra_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/resnet_1x1_compute.json b/coreir_compute/resnet_1x1_compute.json new file mode 100644 index 000000000..3d434e3cb --- /dev/null +++ b/coreir_compute/resnet_1x1_compute.json @@ -0,0 +1,1054 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_glb_stencil":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__664":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__664.out"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__674":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__674.out"] + ] + }, + "hcompute_output_cgra_stencil_10":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_927_941_942":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_928_939_940":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_929_938_939":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_930_937_938":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_931_936_937":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_932_935_936":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_933_934_935":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_3_940_941":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_17_input_cgra_stencil_17_927":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_18_input_cgra_stencil_18_928":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_19_input_cgra_stencil_19_929":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_20_input_cgra_stencil_20_930":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_21_input_cgra_stencil_21_931":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_22_input_cgra_stencil_22_932":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_23_input_cgra_stencil_23_933":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_24_input_cgra_stencil_24_934":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_17_input_cgra_stencil_17_927.out","add_927_941_942.in0"], + ["add_output_cgra_stencil_3_940_941.out","add_927_941_942.in1"], + ["self.out_output_cgra_stencil","add_927_941_942.out"], + ["mul_kernel_cgra_stencil_18_input_cgra_stencil_18_928.out","add_928_939_940.in0"], + ["add_929_938_939.out","add_928_939_940.in1"], + ["add_output_cgra_stencil_3_940_941.in1","add_928_939_940.out"], + ["mul_kernel_cgra_stencil_19_input_cgra_stencil_19_929.out","add_929_938_939.in0"], + ["add_930_937_938.out","add_929_938_939.in1"], + ["mul_kernel_cgra_stencil_20_input_cgra_stencil_20_930.out","add_930_937_938.in0"], + ["add_931_936_937.out","add_930_937_938.in1"], + ["mul_kernel_cgra_stencil_21_input_cgra_stencil_21_931.out","add_931_936_937.in0"], + ["add_932_935_936.out","add_931_936_937.in1"], + ["mul_kernel_cgra_stencil_22_input_cgra_stencil_22_932.out","add_932_935_936.in0"], + ["add_933_934_935.out","add_932_935_936.in1"], + ["mul_kernel_cgra_stencil_23_input_cgra_stencil_23_933.out","add_933_934_935.in0"], + ["mul_kernel_cgra_stencil_24_input_cgra_stencil_24_934.out","add_933_934_935.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_3_940_941.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_927.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_927.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_928.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_928.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_929.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_929.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_930.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_930.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_931.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_931.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_932.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_932.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_933.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_933.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_934.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_934.in1"] + ] + }, + "hcompute_output_cgra_stencil_11":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1000_1014_1015":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1001_1012_1013":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1002_1011_1012":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1003_1010_1011":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1004_1009_1010":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1005_1008_1009":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1006_1007_1008":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_4_1013_1014":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1000":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1001":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1002":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1003":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1004":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1005":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1006":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1007":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1000.out","add_1000_1014_1015.in0"], + ["add_output_cgra_stencil_4_1013_1014.out","add_1000_1014_1015.in1"], + ["self.out_output_cgra_stencil","add_1000_1014_1015.out"], + ["mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1001.out","add_1001_1012_1013.in0"], + ["add_1002_1011_1012.out","add_1001_1012_1013.in1"], + ["add_output_cgra_stencil_4_1013_1014.in1","add_1001_1012_1013.out"], + ["mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1002.out","add_1002_1011_1012.in0"], + ["add_1003_1010_1011.out","add_1002_1011_1012.in1"], + ["mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1003.out","add_1003_1010_1011.in0"], + ["add_1004_1009_1010.out","add_1003_1010_1011.in1"], + ["mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1004.out","add_1004_1009_1010.in0"], + ["add_1005_1008_1009.out","add_1004_1009_1010.in1"], + ["mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1005.out","add_1005_1008_1009.in0"], + ["add_1006_1007_1008.out","add_1005_1008_1009.in1"], + ["mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1006.out","add_1006_1007_1008.in0"], + ["mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1007.out","add_1006_1007_1008.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_4_1013_1014.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1000.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1000.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1001.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1001.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1002.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1002.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1003.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1003.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1004.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1004.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1005.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1005.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1006.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1006.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1007.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1007.in1"] + ] + }, + "hcompute_output_cgra_stencil_12":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1073_1087_1088":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1074_1085_1086":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1075_1084_1085":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1076_1083_1084":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1077_1082_1083":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1078_1081_1082":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1079_1080_1081":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_5_1086_1087":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1073":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1074":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1075":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1076":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1077":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1078":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1079":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1080":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1073.out","add_1073_1087_1088.in0"], + ["add_output_cgra_stencil_5_1086_1087.out","add_1073_1087_1088.in1"], + ["self.out_output_cgra_stencil","add_1073_1087_1088.out"], + ["mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1074.out","add_1074_1085_1086.in0"], + ["add_1075_1084_1085.out","add_1074_1085_1086.in1"], + ["add_output_cgra_stencil_5_1086_1087.in1","add_1074_1085_1086.out"], + ["mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1075.out","add_1075_1084_1085.in0"], + ["add_1076_1083_1084.out","add_1075_1084_1085.in1"], + ["mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1076.out","add_1076_1083_1084.in0"], + ["add_1077_1082_1083.out","add_1076_1083_1084.in1"], + ["mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1077.out","add_1077_1082_1083.in0"], + ["add_1078_1081_1082.out","add_1077_1082_1083.in1"], + ["mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1078.out","add_1078_1081_1082.in0"], + ["add_1079_1080_1081.out","add_1078_1081_1082.in1"], + ["mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1079.out","add_1079_1080_1081.in0"], + ["mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1080.out","add_1079_1080_1081.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_5_1086_1087.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1073.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1073.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1074.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1074.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1075.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1075.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1076.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1076.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1077.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1077.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1078.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1078.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1079.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1079.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1080.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1080.in1"] + ] + }, + "hcompute_output_cgra_stencil_13":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1146_1160_1161":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1147_1158_1159":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1148_1157_1158":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1149_1156_1157":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1150_1155_1156":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1151_1154_1155":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1152_1153_1154":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_6_1159_1160":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1146":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1147":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1148":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1149":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1150":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1151":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1152":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1153":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1146.out","add_1146_1160_1161.in0"], + ["add_output_cgra_stencil_6_1159_1160.out","add_1146_1160_1161.in1"], + ["self.out_output_cgra_stencil","add_1146_1160_1161.out"], + ["mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1147.out","add_1147_1158_1159.in0"], + ["add_1148_1157_1158.out","add_1147_1158_1159.in1"], + ["add_output_cgra_stencil_6_1159_1160.in1","add_1147_1158_1159.out"], + ["mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1148.out","add_1148_1157_1158.in0"], + ["add_1149_1156_1157.out","add_1148_1157_1158.in1"], + ["mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1149.out","add_1149_1156_1157.in0"], + ["add_1150_1155_1156.out","add_1149_1156_1157.in1"], + ["mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1150.out","add_1150_1155_1156.in0"], + ["add_1151_1154_1155.out","add_1150_1155_1156.in1"], + ["mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1151.out","add_1151_1154_1155.in0"], + ["add_1152_1153_1154.out","add_1151_1154_1155.in1"], + ["mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1152.out","add_1152_1153_1154.in0"], + ["mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1153.out","add_1152_1153_1154.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_6_1159_1160.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1146.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1146.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1147.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1147.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1148.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1148.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1149.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1149.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1150.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1150.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1151.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1151.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1152.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1152.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1153.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1153.in1"] + ] + }, + "hcompute_output_cgra_stencil_14":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1219_1233_1234":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1220_1231_1232":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1221_1230_1231":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1222_1229_1230":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1223_1228_1229":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1224_1227_1228":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1225_1226_1227":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_7_1232_1233":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1219":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1220":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1221":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1222":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1223":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1224":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1225":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1226":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1219.out","add_1219_1233_1234.in0"], + ["add_output_cgra_stencil_7_1232_1233.out","add_1219_1233_1234.in1"], + ["self.out_output_cgra_stencil","add_1219_1233_1234.out"], + ["mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1220.out","add_1220_1231_1232.in0"], + ["add_1221_1230_1231.out","add_1220_1231_1232.in1"], + ["add_output_cgra_stencil_7_1232_1233.in1","add_1220_1231_1232.out"], + ["mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1221.out","add_1221_1230_1231.in0"], + ["add_1222_1229_1230.out","add_1221_1230_1231.in1"], + ["mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1222.out","add_1222_1229_1230.in0"], + ["add_1223_1228_1229.out","add_1222_1229_1230.in1"], + ["mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1223.out","add_1223_1228_1229.in0"], + ["add_1224_1227_1228.out","add_1223_1228_1229.in1"], + ["mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1224.out","add_1224_1227_1228.in0"], + ["add_1225_1226_1227.out","add_1224_1227_1228.in1"], + ["mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1225.out","add_1225_1226_1227.in0"], + ["mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1226.out","add_1225_1226_1227.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_7_1232_1233.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1219.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1219.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1220.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1220.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1221.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1221.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1222.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1222.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1223.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1223.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1224.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1224.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1225.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1225.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1226.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1226.in1"] + ] + }, + "hcompute_output_cgra_stencil_15":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1292_1306_1307":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1293_1304_1305":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1294_1303_1304":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1295_1302_1303":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1296_1301_1302":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1297_1300_1301":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1298_1299_1300":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_8_1305_1306":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1292":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1293":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1294":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1295":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1296":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1297":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1298":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1299":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1292.out","add_1292_1306_1307.in0"], + ["add_output_cgra_stencil_8_1305_1306.out","add_1292_1306_1307.in1"], + ["self.out_output_cgra_stencil","add_1292_1306_1307.out"], + ["mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1293.out","add_1293_1304_1305.in0"], + ["add_1294_1303_1304.out","add_1293_1304_1305.in1"], + ["add_output_cgra_stencil_8_1305_1306.in1","add_1293_1304_1305.out"], + ["mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1294.out","add_1294_1303_1304.in0"], + ["add_1295_1302_1303.out","add_1294_1303_1304.in1"], + ["mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1295.out","add_1295_1302_1303.in0"], + ["add_1296_1301_1302.out","add_1295_1302_1303.in1"], + ["mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1296.out","add_1296_1301_1302.in0"], + ["add_1297_1300_1301.out","add_1296_1301_1302.in1"], + ["mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1297.out","add_1297_1300_1301.in0"], + ["add_1298_1299_1300.out","add_1297_1300_1301.in1"], + ["mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1298.out","add_1298_1299_1300.in0"], + ["mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1299.out","add_1298_1299_1300.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_8_1305_1306.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1292.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1292.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1293.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1293.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1294.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1294.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1295.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1295.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1296.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1296.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1297.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1297.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1298.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1298.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1299.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1299.in1"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__685":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__685.out"] + ] + }, + "hcompute_output_cgra_stencil_3":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__696":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__696.out"] + ] + }, + "hcompute_output_cgra_stencil_4":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__707":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__707.out"] + ] + }, + "hcompute_output_cgra_stencil_5":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__718":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__718.out"] + ] + }, + "hcompute_output_cgra_stencil_6":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__729":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__729.out"] + ] + }, + "hcompute_output_cgra_stencil_7":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__740":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__740.out"] + ] + }, + "hcompute_output_cgra_stencil_8":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_782_796_797":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_783_794_795":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_784_793_794":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_785_792_793":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_786_791_792":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_787_790_791":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_788_789_790":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_1_795_796":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_1_input_cgra_stencil_1_782":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_2_input_cgra_stencil_2_783":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_3_input_cgra_stencil_3_784":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_4_input_cgra_stencil_4_785":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_5_input_cgra_stencil_5_786":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_6_input_cgra_stencil_6_787":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_7_input_cgra_stencil_7_788":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_8_input_cgra_stencil_8_789":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_1_input_cgra_stencil_1_782.out","add_782_796_797.in0"], + ["add_output_cgra_stencil_1_795_796.out","add_782_796_797.in1"], + ["self.out_output_cgra_stencil","add_782_796_797.out"], + ["mul_kernel_cgra_stencil_2_input_cgra_stencil_2_783.out","add_783_794_795.in0"], + ["add_784_793_794.out","add_783_794_795.in1"], + ["add_output_cgra_stencil_1_795_796.in1","add_783_794_795.out"], + ["mul_kernel_cgra_stencil_3_input_cgra_stencil_3_784.out","add_784_793_794.in0"], + ["add_785_792_793.out","add_784_793_794.in1"], + ["mul_kernel_cgra_stencil_4_input_cgra_stencil_4_785.out","add_785_792_793.in0"], + ["add_786_791_792.out","add_785_792_793.in1"], + ["mul_kernel_cgra_stencil_5_input_cgra_stencil_5_786.out","add_786_791_792.in0"], + ["add_787_790_791.out","add_786_791_792.in1"], + ["mul_kernel_cgra_stencil_6_input_cgra_stencil_6_787.out","add_787_790_791.in0"], + ["add_788_789_790.out","add_787_790_791.in1"], + ["mul_kernel_cgra_stencil_7_input_cgra_stencil_7_788.out","add_788_789_790.in0"], + ["mul_kernel_cgra_stencil_8_input_cgra_stencil_8_789.out","add_788_789_790.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_1_795_796.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_782.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_782.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_783.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_783.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_784.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_784.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_785.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_785.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_786.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_786.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_787.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_787.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_788.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_788.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_789.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_789.in1"] + ] + }, + "hcompute_output_cgra_stencil_9":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_854_868_869":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_855_866_867":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_856_865_866":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_857_864_865":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_858_863_864":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_859_862_863":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_860_861_862":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_2_867_868":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_10_input_cgra_stencil_10_855":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_11_input_cgra_stencil_11_856":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_12_input_cgra_stencil_12_857":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_13_input_cgra_stencil_13_858":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_14_input_cgra_stencil_14_859":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_15_input_cgra_stencil_15_860":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_16_input_cgra_stencil_16_861":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_9_input_cgra_stencil_9_854":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_9_input_cgra_stencil_9_854.out","add_854_868_869.in0"], + ["add_output_cgra_stencil_2_867_868.out","add_854_868_869.in1"], + ["self.out_output_cgra_stencil","add_854_868_869.out"], + ["mul_kernel_cgra_stencil_10_input_cgra_stencil_10_855.out","add_855_866_867.in0"], + ["add_856_865_866.out","add_855_866_867.in1"], + ["add_output_cgra_stencil_2_867_868.in1","add_855_866_867.out"], + ["mul_kernel_cgra_stencil_11_input_cgra_stencil_11_856.out","add_856_865_866.in0"], + ["add_857_864_865.out","add_856_865_866.in1"], + ["mul_kernel_cgra_stencil_12_input_cgra_stencil_12_857.out","add_857_864_865.in0"], + ["add_858_863_864.out","add_857_864_865.in1"], + ["mul_kernel_cgra_stencil_13_input_cgra_stencil_13_858.out","add_858_863_864.in0"], + ["add_859_862_863.out","add_858_863_864.in1"], + ["mul_kernel_cgra_stencil_14_input_cgra_stencil_14_859.out","add_859_862_863.in0"], + ["add_860_861_862.out","add_859_862_863.in1"], + ["mul_kernel_cgra_stencil_15_input_cgra_stencil_15_860.out","add_860_861_862.in0"], + ["mul_kernel_cgra_stencil_16_input_cgra_stencil_16_861.out","add_860_861_862.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_2_867_868.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_855.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_855.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_856.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_856.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_857.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_857.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_858.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_858.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_859.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_859.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_860.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_860.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_861.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_861.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_854.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_854.in1"] + ] + }, + "hcompute_output_glb_stencil":{ + "type":["Record",[ + ["out_output_glb_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_glb_stencil","self.in0_output_cgra_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/resnet_last_compute.json b/coreir_compute/resnet_last_compute.json new file mode 100644 index 000000000..c66b8da5a --- /dev/null +++ b/coreir_compute/resnet_last_compute.json @@ -0,0 +1,1054 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_stencil","self.in0_output_glb_stencil.0"] + ] + }, + "hcompute_input_cgra_stencil":{ + "type":["Record",[ + ["out_input_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_cgra_stencil","self.in0_input_glb_stencil.0"] + ] + }, + "hcompute_input_glb_stencil":{ + "type":["Record",[ + ["out_input_glb_stencil",["Array",16,"Bit"]], + ["in0_input_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_input_glb_stencil","self.in0_input_host_stencil.0"] + ] + }, + "hcompute_kernel_cgra_stencil":{ + "type":["Record",[ + ["out_kernel_cgra_stencil",["Array",16,"Bit"]], + ["in0_kernel_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_cgra_stencil","self.in0_kernel_glb_stencil.0"] + ] + }, + "hcompute_kernel_glb_stencil":{ + "type":["Record",[ + ["out_kernel_glb_stencil",["Array",16,"Bit"]], + ["in0_kernel_host_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_kernel_glb_stencil","self.in0_kernel_host_stencil.0"] + ] + }, + "hcompute_output_cgra_stencil":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__701":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__701.out"] + ] + }, + "hcompute_output_cgra_stencil_1":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__710":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__710.out"] + ] + }, + "hcompute_output_cgra_stencil_10":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_957_971_972":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_958_969_970":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_959_968_969":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_960_967_968":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_961_966_967":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_962_965_966":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_963_964_965":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_3_970_971":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_18_input_cgra_stencil_18_958":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_19_input_cgra_stencil_19_959":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_20_input_cgra_stencil_20_960":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_21_input_cgra_stencil_21_961":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_22_input_cgra_stencil_22_962":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_23_input_cgra_stencil_23_963":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_24_input_cgra_stencil_24_964":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957.out","add_957_971_972.in0"], + ["add_output_cgra_stencil_3_970_971.out","add_957_971_972.in1"], + ["self.out_output_cgra_stencil","add_957_971_972.out"], + ["mul_kernel_cgra_stencil_18_input_cgra_stencil_18_958.out","add_958_969_970.in0"], + ["add_959_968_969.out","add_958_969_970.in1"], + ["add_output_cgra_stencil_3_970_971.in1","add_958_969_970.out"], + ["mul_kernel_cgra_stencil_19_input_cgra_stencil_19_959.out","add_959_968_969.in0"], + ["add_960_967_968.out","add_959_968_969.in1"], + ["mul_kernel_cgra_stencil_20_input_cgra_stencil_20_960.out","add_960_967_968.in0"], + ["add_961_966_967.out","add_960_967_968.in1"], + ["mul_kernel_cgra_stencil_21_input_cgra_stencil_21_961.out","add_961_966_967.in0"], + ["add_962_965_966.out","add_961_966_967.in1"], + ["mul_kernel_cgra_stencil_22_input_cgra_stencil_22_962.out","add_962_965_966.in0"], + ["add_963_964_965.out","add_962_965_966.in1"], + ["mul_kernel_cgra_stencil_23_input_cgra_stencil_23_963.out","add_963_964_965.in0"], + ["mul_kernel_cgra_stencil_24_input_cgra_stencil_24_964.out","add_963_964_965.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_3_970_971.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_17_input_cgra_stencil_17_957.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_958.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_18_input_cgra_stencil_18_958.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_959.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_19_input_cgra_stencil_19_959.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_960.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_20_input_cgra_stencil_20_960.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_961.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_21_input_cgra_stencil_21_961.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_962.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_22_input_cgra_stencil_22_962.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_963.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_23_input_cgra_stencil_23_963.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_964.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_24_input_cgra_stencil_24_964.in1"] + ] + }, + "hcompute_output_cgra_stencil_11":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1032_1046_1047":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1033_1044_1045":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1034_1043_1044":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1035_1042_1043":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1036_1041_1042":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1037_1040_1041":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1038_1039_1040":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_4_1045_1046":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1032":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1033":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1034":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1035":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1036":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1037":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1038":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1039":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1032.out","add_1032_1046_1047.in0"], + ["add_output_cgra_stencil_4_1045_1046.out","add_1032_1046_1047.in1"], + ["self.out_output_cgra_stencil","add_1032_1046_1047.out"], + ["mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1033.out","add_1033_1044_1045.in0"], + ["add_1034_1043_1044.out","add_1033_1044_1045.in1"], + ["add_output_cgra_stencil_4_1045_1046.in1","add_1033_1044_1045.out"], + ["mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1034.out","add_1034_1043_1044.in0"], + ["add_1035_1042_1043.out","add_1034_1043_1044.in1"], + ["mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1035.out","add_1035_1042_1043.in0"], + ["add_1036_1041_1042.out","add_1035_1042_1043.in1"], + ["mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1036.out","add_1036_1041_1042.in0"], + ["add_1037_1040_1041.out","add_1036_1041_1042.in1"], + ["mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1037.out","add_1037_1040_1041.in0"], + ["add_1038_1039_1040.out","add_1037_1040_1041.in1"], + ["mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1038.out","add_1038_1039_1040.in0"], + ["mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1039.out","add_1038_1039_1040.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_4_1045_1046.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1032.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_25_input_cgra_stencil_25_1032.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1033.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_26_input_cgra_stencil_26_1033.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1034.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_27_input_cgra_stencil_27_1034.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1035.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_28_input_cgra_stencil_28_1035.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1036.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_29_input_cgra_stencil_29_1036.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1037.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_30_input_cgra_stencil_30_1037.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1038.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_31_input_cgra_stencil_31_1038.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1039.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_32_input_cgra_stencil_32_1039.in1"] + ] + }, + "hcompute_output_cgra_stencil_12":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1107_1121_1122":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1108_1119_1120":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1109_1118_1119":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1110_1117_1118":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1111_1116_1117":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1112_1115_1116":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1113_1114_1115":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_5_1120_1121":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1107":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1108":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1109":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1110":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1111":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1112":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1113":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1114":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1107.out","add_1107_1121_1122.in0"], + ["add_output_cgra_stencil_5_1120_1121.out","add_1107_1121_1122.in1"], + ["self.out_output_cgra_stencil","add_1107_1121_1122.out"], + ["mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1108.out","add_1108_1119_1120.in0"], + ["add_1109_1118_1119.out","add_1108_1119_1120.in1"], + ["add_output_cgra_stencil_5_1120_1121.in1","add_1108_1119_1120.out"], + ["mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1109.out","add_1109_1118_1119.in0"], + ["add_1110_1117_1118.out","add_1109_1118_1119.in1"], + ["mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1110.out","add_1110_1117_1118.in0"], + ["add_1111_1116_1117.out","add_1110_1117_1118.in1"], + ["mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1111.out","add_1111_1116_1117.in0"], + ["add_1112_1115_1116.out","add_1111_1116_1117.in1"], + ["mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1112.out","add_1112_1115_1116.in0"], + ["add_1113_1114_1115.out","add_1112_1115_1116.in1"], + ["mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1113.out","add_1113_1114_1115.in0"], + ["mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1114.out","add_1113_1114_1115.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_5_1120_1121.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1107.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_33_input_cgra_stencil_33_1107.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1108.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_34_input_cgra_stencil_34_1108.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1109.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_35_input_cgra_stencil_35_1109.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1110.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_36_input_cgra_stencil_36_1110.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1111.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_37_input_cgra_stencil_37_1111.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1112.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_38_input_cgra_stencil_38_1112.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1113.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_39_input_cgra_stencil_39_1113.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1114.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_40_input_cgra_stencil_40_1114.in1"] + ] + }, + "hcompute_output_cgra_stencil_13":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1182_1196_1197":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1183_1194_1195":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1184_1193_1194":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1185_1192_1193":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1186_1191_1192":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1187_1190_1191":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1188_1189_1190":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_6_1195_1196":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1182":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1183":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1184":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1185":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1186":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1187":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1188":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1189":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1182.out","add_1182_1196_1197.in0"], + ["add_output_cgra_stencil_6_1195_1196.out","add_1182_1196_1197.in1"], + ["self.out_output_cgra_stencil","add_1182_1196_1197.out"], + ["mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1183.out","add_1183_1194_1195.in0"], + ["add_1184_1193_1194.out","add_1183_1194_1195.in1"], + ["add_output_cgra_stencil_6_1195_1196.in1","add_1183_1194_1195.out"], + ["mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1184.out","add_1184_1193_1194.in0"], + ["add_1185_1192_1193.out","add_1184_1193_1194.in1"], + ["mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1185.out","add_1185_1192_1193.in0"], + ["add_1186_1191_1192.out","add_1185_1192_1193.in1"], + ["mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1186.out","add_1186_1191_1192.in0"], + ["add_1187_1190_1191.out","add_1186_1191_1192.in1"], + ["mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1187.out","add_1187_1190_1191.in0"], + ["add_1188_1189_1190.out","add_1187_1190_1191.in1"], + ["mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1188.out","add_1188_1189_1190.in0"], + ["mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1189.out","add_1188_1189_1190.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_6_1195_1196.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1182.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_41_input_cgra_stencil_41_1182.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1183.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_42_input_cgra_stencil_42_1183.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1184.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_43_input_cgra_stencil_43_1184.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1185.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_44_input_cgra_stencil_44_1185.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1186.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_45_input_cgra_stencil_45_1186.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1187.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_46_input_cgra_stencil_46_1187.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1188.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_47_input_cgra_stencil_47_1188.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1189.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_48_input_cgra_stencil_48_1189.in1"] + ] + }, + "hcompute_output_cgra_stencil_14":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1257_1271_1272":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1258_1269_1270":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1259_1268_1269":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1260_1267_1268":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1261_1266_1267":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1262_1265_1266":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1263_1264_1265":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_7_1270_1271":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257.out","add_1257_1271_1272.in0"], + ["add_output_cgra_stencil_7_1270_1271.out","add_1257_1271_1272.in1"], + ["self.out_output_cgra_stencil","add_1257_1271_1272.out"], + ["mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258.out","add_1258_1269_1270.in0"], + ["add_1259_1268_1269.out","add_1258_1269_1270.in1"], + ["add_output_cgra_stencil_7_1270_1271.in1","add_1258_1269_1270.out"], + ["mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259.out","add_1259_1268_1269.in0"], + ["add_1260_1267_1268.out","add_1259_1268_1269.in1"], + ["mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260.out","add_1260_1267_1268.in0"], + ["add_1261_1266_1267.out","add_1260_1267_1268.in1"], + ["mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261.out","add_1261_1266_1267.in0"], + ["add_1262_1265_1266.out","add_1261_1266_1267.in1"], + ["mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262.out","add_1262_1265_1266.in0"], + ["add_1263_1264_1265.out","add_1262_1265_1266.in1"], + ["mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263.out","add_1263_1264_1265.in0"], + ["mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264.out","add_1263_1264_1265.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_7_1270_1271.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_49_input_cgra_stencil_49_1257.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_50_input_cgra_stencil_50_1258.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_51_input_cgra_stencil_51_1259.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_52_input_cgra_stencil_52_1260.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_53_input_cgra_stencil_53_1261.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_54_input_cgra_stencil_54_1262.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_55_input_cgra_stencil_55_1263.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_56_input_cgra_stencil_56_1264.in1"] + ] + }, + "hcompute_output_cgra_stencil_15":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1332_1346_1347":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1333_1344_1345":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1334_1343_1344":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1335_1342_1343":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1336_1341_1342":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1337_1340_1341":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1338_1339_1340":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_8_1345_1346":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1332":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1333":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1334":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1335":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1336":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1337":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1338":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1339":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1332.out","add_1332_1346_1347.in0"], + ["add_output_cgra_stencil_8_1345_1346.out","add_1332_1346_1347.in1"], + ["self.out_output_cgra_stencil","add_1332_1346_1347.out"], + ["mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1333.out","add_1333_1344_1345.in0"], + ["add_1334_1343_1344.out","add_1333_1344_1345.in1"], + ["add_output_cgra_stencil_8_1345_1346.in1","add_1333_1344_1345.out"], + ["mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1334.out","add_1334_1343_1344.in0"], + ["add_1335_1342_1343.out","add_1334_1343_1344.in1"], + ["mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1335.out","add_1335_1342_1343.in0"], + ["add_1336_1341_1342.out","add_1335_1342_1343.in1"], + ["mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1336.out","add_1336_1341_1342.in0"], + ["add_1337_1340_1341.out","add_1336_1341_1342.in1"], + ["mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1337.out","add_1337_1340_1341.in0"], + ["add_1338_1339_1340.out","add_1337_1340_1341.in1"], + ["mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1338.out","add_1338_1339_1340.in0"], + ["mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1339.out","add_1338_1339_1340.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_8_1345_1346.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1332.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_57_input_cgra_stencil_57_1332.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1333.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_58_input_cgra_stencil_58_1333.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1334.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_59_input_cgra_stencil_59_1334.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1335.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_60_input_cgra_stencil_60_1335.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1336.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_61_input_cgra_stencil_61_1336.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1337.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_62_input_cgra_stencil_62_1337.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1338.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_63_input_cgra_stencil_63_1338.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1339.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_64_input_cgra_stencil_64_1339.in1"] + ] + }, + "hcompute_output_cgra_stencil_2":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__719":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__719.out"] + ] + }, + "hcompute_output_cgra_stencil_3":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__728":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__728.out"] + ] + }, + "hcompute_output_cgra_stencil_4":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__737":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__737.out"] + ] + }, + "hcompute_output_cgra_stencil_5":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__746":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__746.out"] + ] + }, + "hcompute_output_cgra_stencil_6":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__755":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__755.out"] + ] + }, + "hcompute_output_cgra_stencil_7":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__764":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_output_cgra_stencil","const_p0__764.out"] + ] + }, + "hcompute_output_cgra_stencil_8":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_807_821_822":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_808_819_820":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_809_818_819":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_810_817_818":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_811_816_817":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_812_815_816":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_813_814_815":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_1_820_821":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_1_input_cgra_stencil_1_807":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_2_input_cgra_stencil_2_808":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_3_input_cgra_stencil_3_809":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_4_input_cgra_stencil_4_810":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_5_input_cgra_stencil_5_811":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_6_input_cgra_stencil_6_812":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_7_input_cgra_stencil_7_813":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_8_input_cgra_stencil_8_814":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_1_input_cgra_stencil_1_807.out","add_807_821_822.in0"], + ["add_output_cgra_stencil_1_820_821.out","add_807_821_822.in1"], + ["self.out_output_cgra_stencil","add_807_821_822.out"], + ["mul_kernel_cgra_stencil_2_input_cgra_stencil_2_808.out","add_808_819_820.in0"], + ["add_809_818_819.out","add_808_819_820.in1"], + ["add_output_cgra_stencil_1_820_821.in1","add_808_819_820.out"], + ["mul_kernel_cgra_stencil_3_input_cgra_stencil_3_809.out","add_809_818_819.in0"], + ["add_810_817_818.out","add_809_818_819.in1"], + ["mul_kernel_cgra_stencil_4_input_cgra_stencil_4_810.out","add_810_817_818.in0"], + ["add_811_816_817.out","add_810_817_818.in1"], + ["mul_kernel_cgra_stencil_5_input_cgra_stencil_5_811.out","add_811_816_817.in0"], + ["add_812_815_816.out","add_811_816_817.in1"], + ["mul_kernel_cgra_stencil_6_input_cgra_stencil_6_812.out","add_812_815_816.in0"], + ["add_813_814_815.out","add_812_815_816.in1"], + ["mul_kernel_cgra_stencil_7_input_cgra_stencil_7_813.out","add_813_814_815.in0"], + ["mul_kernel_cgra_stencil_8_input_cgra_stencil_8_814.out","add_813_814_815.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_1_820_821.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_807.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_1_input_cgra_stencil_1_807.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_808.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_2_input_cgra_stencil_2_808.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_809.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_3_input_cgra_stencil_3_809.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_810.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_4_input_cgra_stencil_4_810.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_811.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_5_input_cgra_stencil_5_811.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_812.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_6_input_cgra_stencil_6_812.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_813.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_7_input_cgra_stencil_7_813.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_814.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_8_input_cgra_stencil_8_814.in1"] + ] + }, + "hcompute_output_cgra_stencil_9":{ + "type":["Record",[ + ["out_output_cgra_stencil",["Array",16,"Bit"]], + ["in0_input_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in1_kernel_cgra_stencil",["Array",8,["Array",16,"BitIn"]]], + ["in2_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_882_896_897":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_883_894_895":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_884_893_894":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_885_892_893":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_886_891_892":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_887_890_891":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_888_889_890":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_output_cgra_stencil_2_895_896":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_10_input_cgra_stencil_10_883":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_11_input_cgra_stencil_11_884":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_12_input_cgra_stencil_12_885":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_13_input_cgra_stencil_13_886":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_14_input_cgra_stencil_14_887":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_15_input_cgra_stencil_15_888":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_16_input_cgra_stencil_16_889":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_kernel_cgra_stencil_9_input_cgra_stencil_9_882":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_kernel_cgra_stencil_9_input_cgra_stencil_9_882.out","add_882_896_897.in0"], + ["add_output_cgra_stencil_2_895_896.out","add_882_896_897.in1"], + ["self.out_output_cgra_stencil","add_882_896_897.out"], + ["mul_kernel_cgra_stencil_10_input_cgra_stencil_10_883.out","add_883_894_895.in0"], + ["add_884_893_894.out","add_883_894_895.in1"], + ["add_output_cgra_stencil_2_895_896.in1","add_883_894_895.out"], + ["mul_kernel_cgra_stencil_11_input_cgra_stencil_11_884.out","add_884_893_894.in0"], + ["add_885_892_893.out","add_884_893_894.in1"], + ["mul_kernel_cgra_stencil_12_input_cgra_stencil_12_885.out","add_885_892_893.in0"], + ["add_886_891_892.out","add_885_892_893.in1"], + ["mul_kernel_cgra_stencil_13_input_cgra_stencil_13_886.out","add_886_891_892.in0"], + ["add_887_890_891.out","add_886_891_892.in1"], + ["mul_kernel_cgra_stencil_14_input_cgra_stencil_14_887.out","add_887_890_891.in0"], + ["add_888_889_890.out","add_887_890_891.in1"], + ["mul_kernel_cgra_stencil_15_input_cgra_stencil_15_888.out","add_888_889_890.in0"], + ["mul_kernel_cgra_stencil_16_input_cgra_stencil_16_889.out","add_888_889_890.in1"], + ["self.in2_output_cgra_stencil.0","add_output_cgra_stencil_2_895_896.in0"], + ["self.in1_kernel_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_883.in0"], + ["self.in0_input_cgra_stencil.0","mul_kernel_cgra_stencil_10_input_cgra_stencil_10_883.in1"], + ["self.in1_kernel_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_884.in0"], + ["self.in0_input_cgra_stencil.1","mul_kernel_cgra_stencil_11_input_cgra_stencil_11_884.in1"], + ["self.in1_kernel_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_885.in0"], + ["self.in0_input_cgra_stencil.2","mul_kernel_cgra_stencil_12_input_cgra_stencil_12_885.in1"], + ["self.in1_kernel_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_886.in0"], + ["self.in0_input_cgra_stencil.3","mul_kernel_cgra_stencil_13_input_cgra_stencil_13_886.in1"], + ["self.in1_kernel_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_887.in0"], + ["self.in0_input_cgra_stencil.4","mul_kernel_cgra_stencil_14_input_cgra_stencil_14_887.in1"], + ["self.in1_kernel_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_888.in0"], + ["self.in0_input_cgra_stencil.5","mul_kernel_cgra_stencil_15_input_cgra_stencil_15_888.in1"], + ["self.in1_kernel_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_889.in0"], + ["self.in0_input_cgra_stencil.6","mul_kernel_cgra_stencil_16_input_cgra_stencil_16_889.in1"], + ["self.in1_kernel_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_882.in0"], + ["self.in0_input_cgra_stencil.7","mul_kernel_cgra_stencil_9_input_cgra_stencil_9_882.in1"] + ] + }, + "hcompute_output_glb_stencil":{ + "type":["Record",[ + ["out_output_glb_stencil",["Array",16,"Bit"]], + ["in0_output_cgra_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_output_glb_stencil","self.in0_output_cgra_stencil.0"] + ] + } + } + } +} +} diff --git a/coreir_compute/resnet_size_test_compute.json b/coreir_compute/resnet_size_test_compute.json new file mode 100644 index 000000000..30f752a0a --- /dev/null +++ b/coreir_compute/resnet_size_test_compute.json @@ -0,0 +1,88 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_conv_stencil":{ + "type":["Record",[ + ["out_conv_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__662":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_conv_stencil","const_p0__662.out"] + ] + }, + "hcompute_conv_stencil_1":{ + "type":["Record",[ + ["out_conv_stencil",["Array",16,"Bit"]], + ["in0_conv_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_hw_input_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in2_hw_kernel_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_conv_stencil_1_666_667":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in0_conv_stencil.0","add_conv_stencil_1_666_667.in0"], + ["mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666.out","add_conv_stencil_1_666_667.in1"], + ["self.out_conv_stencil","add_conv_stencil_1_666_667.out"], + ["self.in2_hw_kernel_global_wrapper_stencil.0","mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666.in0"], + ["self.in1_hw_input_global_wrapper_stencil.0","mul_hw_kernel_global_wrapper_stencil_1_hw_input_global_wrapper_stencil_1_666.in1"] + ] + }, + "hcompute_hw_input_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_kernel_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_kernel_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_kernel_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_kernel_global_wrapper_stencil","self.in0_hw_kernel_stencil.0"] + ] + }, + "hcompute_hw_output_stencil":{ + "type":["Record",[ + ["out_hw_output_stencil",["Array",16,"Bit"]], + ["in0_conv_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__677":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "smax_conv_stencil_2_677_678":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_conv_stencil_2_677_678.in1","const_p0__677.out"], + ["smax_conv_stencil_2_677_678.in0","self.in0_conv_stencil.0"], + ["smax_conv_stencil_2_677_678.out","self.out_hw_output_stencil"] + ] + } + } + } +} +} diff --git a/coreir_compute/unsharp_large_compute.json b/coreir_compute/unsharp_large_compute.json new file mode 100644 index 000000000..459fedf94 --- /dev/null +++ b/coreir_compute/unsharp_large_compute.json @@ -0,0 +1,1038 @@ +{ +"namespaces":{ + "global":{ + "modules":{ + "hcompute_blur_unnormalized_stencil":{ + "type":["Record",[ + ["out_blur_unnormalized_stencil",["Array",16,"Bit"]] + ]], + "instances":{ + "const_p0__985":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + } + }, + "connections":[ + ["self.out_blur_unnormalized_stencil","const_p0__985.out"] + ] + }, + "hcompute_blur_unnormalized_stencil_1":{ + "type":["Record",[ + ["out_blur_unnormalized_stencil",["Array",16,"Bit"]], + ["in0_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",45,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_1077_1161_1162":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1078_1160_1161":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1079_1159_1160":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1081_1156_1157":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1083_1155_1156":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1085_1154_1155":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1086_1153_1154":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1087_1152_1153":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1088_1150_1151":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1089_1149_1150":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1091_1148_1149":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1093_1147_1148":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1094_1146_1147":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1095_1145_1146":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1096_1144_1145":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1097_1143_1144":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1098_1142_1143":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1099_1141_1142":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1101_1140_1141":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1102_1139_1140":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1103_1138_1139":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1104_1137_1138":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1105_1136_1137":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1106_1135_1136":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1107_1134_1135":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1108_1133_1134":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1109_1132_1133":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1110_1131_1132":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1111_1130_1131":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1112_1128_1129":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1113_1127_1128":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1114_1126_1127":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1115_1125_1126":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1116_1124_1125":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1117_1121_1122":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_1118_1120_1121":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_blur_unnormalized_stencil_1_1162_1163":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_13_1151_1152":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_2_1163_1164":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_35_1129_1130":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_41_1123_1124":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_42_1122_1123":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_45_1119_1120":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_6_1158_1159":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_gray_stencil_7_1157_1158":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p12__1090":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000c"]} + }, + "const_p12__1090$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000c"]} + }, + "const_p12__1090$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000c"]} + }, + "const_p12__1090$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000c"]} + }, + "const_p15__1092":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000f"]} + }, + "const_p15__1092$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000f"]} + }, + "const_p15__1092$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000f"]} + }, + "const_p15__1092$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h000f"]} + }, + "const_p18__1100":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0012"]} + }, + "const_p2__1076":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$10":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$11":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$8":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p2__1076$9":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p3__1080":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__1080$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__1080$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p3__1080$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0003"]} + }, + "const_p6__1082":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__1082$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__1082$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__1082$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__1082$4":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__1082$5":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__1082$6":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p6__1082$7":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0006"]} + }, + "const_p7__1084":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "const_p7__1084$1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "const_p7__1084$2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "const_p7__1084$3":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0007"]} + }, + "mul_gray_stencil_10_1084_1085":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_11_1082_1086":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_12_1080_1087":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_14_1076_1088":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_15_1082_1089":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_16_1090_1091":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_17_1092_1093":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_18_1090_1094":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_19_1082_1095":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_20_1076_1096":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_21_1076_1097":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_22_1084_1098":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_23_1092_1099":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_24_1100_1101":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_25_1092_1102":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_26_1084_1103":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_27_1076_1104":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_28_1076_1105":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_29_1082_1106":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_30_1090_1107":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_31_1092_1108":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_32_1090_1109":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_33_1082_1110":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_34_1076_1111":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_36_1080_1112":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_37_1082_1113":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_38_1084_1114":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_39_1082_1115":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_3_1076_1077":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_40_1080_1116":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_43_1076_1117":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_44_1076_1118":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_46_1076_1119":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_4_1076_1078":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_5_1076_1079":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_8_1080_1081":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_gray_stencil_9_1082_1083":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_gray_stencil_3_1076_1077.out","add_1077_1161_1162.in0"], + ["add_1078_1160_1161.out","add_1077_1161_1162.in1"], + ["add_blur_unnormalized_stencil_1_1162_1163.in1","add_1077_1161_1162.out"], + ["mul_gray_stencil_4_1076_1078.out","add_1078_1160_1161.in0"], + ["add_1079_1159_1160.out","add_1078_1160_1161.in1"], + ["mul_gray_stencil_5_1076_1079.out","add_1079_1159_1160.in0"], + ["add_gray_stencil_6_1158_1159.out","add_1079_1159_1160.in1"], + ["mul_gray_stencil_8_1080_1081.out","add_1081_1156_1157.in0"], + ["add_1083_1155_1156.out","add_1081_1156_1157.in1"], + ["add_gray_stencil_7_1157_1158.in1","add_1081_1156_1157.out"], + ["mul_gray_stencil_9_1082_1083.out","add_1083_1155_1156.in0"], + ["add_1085_1154_1155.out","add_1083_1155_1156.in1"], + ["mul_gray_stencil_10_1084_1085.out","add_1085_1154_1155.in0"], + ["add_1086_1153_1154.out","add_1085_1154_1155.in1"], + ["mul_gray_stencil_11_1082_1086.out","add_1086_1153_1154.in0"], + ["add_1087_1152_1153.out","add_1086_1153_1154.in1"], + ["mul_gray_stencil_12_1080_1087.out","add_1087_1152_1153.in0"], + ["add_gray_stencil_13_1151_1152.out","add_1087_1152_1153.in1"], + ["mul_gray_stencil_14_1076_1088.out","add_1088_1150_1151.in0"], + ["add_1089_1149_1150.out","add_1088_1150_1151.in1"], + ["add_gray_stencil_13_1151_1152.in1","add_1088_1150_1151.out"], + ["mul_gray_stencil_15_1082_1089.out","add_1089_1149_1150.in0"], + ["add_1091_1148_1149.out","add_1089_1149_1150.in1"], + ["mul_gray_stencil_16_1090_1091.out","add_1091_1148_1149.in0"], + ["add_1093_1147_1148.out","add_1091_1148_1149.in1"], + ["mul_gray_stencil_17_1092_1093.out","add_1093_1147_1148.in0"], + ["add_1094_1146_1147.out","add_1093_1147_1148.in1"], + ["mul_gray_stencil_18_1090_1094.out","add_1094_1146_1147.in0"], + ["add_1095_1145_1146.out","add_1094_1146_1147.in1"], + ["mul_gray_stencil_19_1082_1095.out","add_1095_1145_1146.in0"], + ["add_1096_1144_1145.out","add_1095_1145_1146.in1"], + ["mul_gray_stencil_20_1076_1096.out","add_1096_1144_1145.in0"], + ["add_1097_1143_1144.out","add_1096_1144_1145.in1"], + ["mul_gray_stencil_21_1076_1097.out","add_1097_1143_1144.in0"], + ["add_1098_1142_1143.out","add_1097_1143_1144.in1"], + ["mul_gray_stencil_22_1084_1098.out","add_1098_1142_1143.in0"], + ["add_1099_1141_1142.out","add_1098_1142_1143.in1"], + ["mul_gray_stencil_23_1092_1099.out","add_1099_1141_1142.in0"], + ["add_1101_1140_1141.out","add_1099_1141_1142.in1"], + ["mul_gray_stencil_24_1100_1101.out","add_1101_1140_1141.in0"], + ["add_1102_1139_1140.out","add_1101_1140_1141.in1"], + ["mul_gray_stencil_25_1092_1102.out","add_1102_1139_1140.in0"], + ["add_1103_1138_1139.out","add_1102_1139_1140.in1"], + ["mul_gray_stencil_26_1084_1103.out","add_1103_1138_1139.in0"], + ["add_1104_1137_1138.out","add_1103_1138_1139.in1"], + ["mul_gray_stencil_27_1076_1104.out","add_1104_1137_1138.in0"], + ["add_1105_1136_1137.out","add_1104_1137_1138.in1"], + ["mul_gray_stencil_28_1076_1105.out","add_1105_1136_1137.in0"], + ["add_1106_1135_1136.out","add_1105_1136_1137.in1"], + ["mul_gray_stencil_29_1082_1106.out","add_1106_1135_1136.in0"], + ["add_1107_1134_1135.out","add_1106_1135_1136.in1"], + ["mul_gray_stencil_30_1090_1107.out","add_1107_1134_1135.in0"], + ["add_1108_1133_1134.out","add_1107_1134_1135.in1"], + ["mul_gray_stencil_31_1092_1108.out","add_1108_1133_1134.in0"], + ["add_1109_1132_1133.out","add_1108_1133_1134.in1"], + ["mul_gray_stencil_32_1090_1109.out","add_1109_1132_1133.in0"], + ["add_1110_1131_1132.out","add_1109_1132_1133.in1"], + ["mul_gray_stencil_33_1082_1110.out","add_1110_1131_1132.in0"], + ["add_1111_1130_1131.out","add_1110_1131_1132.in1"], + ["mul_gray_stencil_34_1076_1111.out","add_1111_1130_1131.in0"], + ["add_gray_stencil_35_1129_1130.out","add_1111_1130_1131.in1"], + ["mul_gray_stencil_36_1080_1112.out","add_1112_1128_1129.in0"], + ["add_1113_1127_1128.out","add_1112_1128_1129.in1"], + ["add_gray_stencil_35_1129_1130.in1","add_1112_1128_1129.out"], + ["mul_gray_stencil_37_1082_1113.out","add_1113_1127_1128.in0"], + ["add_1114_1126_1127.out","add_1113_1127_1128.in1"], + ["mul_gray_stencil_38_1084_1114.out","add_1114_1126_1127.in0"], + ["add_1115_1125_1126.out","add_1114_1126_1127.in1"], + ["mul_gray_stencil_39_1082_1115.out","add_1115_1125_1126.in0"], + ["add_1116_1124_1125.out","add_1115_1125_1126.in1"], + ["mul_gray_stencil_40_1080_1116.out","add_1116_1124_1125.in0"], + ["add_gray_stencil_41_1123_1124.out","add_1116_1124_1125.in1"], + ["mul_gray_stencil_43_1076_1117.out","add_1117_1121_1122.in0"], + ["add_1118_1120_1121.out","add_1117_1121_1122.in1"], + ["add_gray_stencil_42_1122_1123.in1","add_1117_1121_1122.out"], + ["mul_gray_stencil_44_1076_1118.out","add_1118_1120_1121.in0"], + ["add_gray_stencil_45_1119_1120.out","add_1118_1120_1121.in1"], + ["self.in0_blur_unnormalized_stencil.0","add_blur_unnormalized_stencil_1_1162_1163.in0"], + ["add_gray_stencil_2_1163_1164.in1","add_blur_unnormalized_stencil_1_1162_1163.out"], + ["self.in1_gray_stencil.3","add_gray_stencil_13_1151_1152.in0"], + ["self.in1_gray_stencil.10","add_gray_stencil_2_1163_1164.in0"], + ["self.out_blur_unnormalized_stencil","add_gray_stencil_2_1163_1164.out"], + ["self.in1_gray_stencil.27","add_gray_stencil_35_1129_1130.in0"], + ["self.in1_gray_stencil.34","add_gray_stencil_41_1123_1124.in0"], + ["add_gray_stencil_42_1122_1123.out","add_gray_stencil_41_1123_1124.in1"], + ["self.in1_gray_stencil.35","add_gray_stencil_42_1122_1123.in0"], + ["self.in1_gray_stencil.38","add_gray_stencil_45_1119_1120.in0"], + ["mul_gray_stencil_46_1076_1119.out","add_gray_stencil_45_1119_1120.in1"], + ["self.in1_gray_stencil.41","add_gray_stencil_6_1158_1159.in0"], + ["add_gray_stencil_7_1157_1158.out","add_gray_stencil_6_1158_1159.in1"], + ["self.in1_gray_stencil.42","add_gray_stencil_7_1157_1158.in0"], + ["mul_gray_stencil_18_1090_1094.in1","const_p12__1090$1.out"], + ["mul_gray_stencil_30_1090_1107.in1","const_p12__1090$2.out"], + ["mul_gray_stencil_32_1090_1109.in1","const_p12__1090$3.out"], + ["mul_gray_stencil_16_1090_1091.in1","const_p12__1090.out"], + ["mul_gray_stencil_23_1092_1099.in1","const_p15__1092$1.out"], + ["mul_gray_stencil_25_1092_1102.in1","const_p15__1092$2.out"], + ["mul_gray_stencil_31_1092_1108.in1","const_p15__1092$3.out"], + ["mul_gray_stencil_17_1092_1093.in1","const_p15__1092.out"], + ["mul_gray_stencil_24_1100_1101.in1","const_p18__1100.out"], + ["mul_gray_stencil_4_1076_1078.in1","const_p2__1076$1.out"], + ["mul_gray_stencil_44_1076_1118.in1","const_p2__1076$10.out"], + ["mul_gray_stencil_46_1076_1119.in1","const_p2__1076$11.out"], + ["mul_gray_stencil_5_1076_1079.in1","const_p2__1076$2.out"], + ["mul_gray_stencil_14_1076_1088.in1","const_p2__1076$3.out"], + ["mul_gray_stencil_20_1076_1096.in1","const_p2__1076$4.out"], + ["mul_gray_stencil_21_1076_1097.in1","const_p2__1076$5.out"], + ["mul_gray_stencil_27_1076_1104.in1","const_p2__1076$6.out"], + ["mul_gray_stencil_28_1076_1105.in1","const_p2__1076$7.out"], + ["mul_gray_stencil_34_1076_1111.in1","const_p2__1076$8.out"], + ["mul_gray_stencil_43_1076_1117.in1","const_p2__1076$9.out"], + ["mul_gray_stencil_3_1076_1077.in1","const_p2__1076.out"], + ["mul_gray_stencil_12_1080_1087.in1","const_p3__1080$1.out"], + ["mul_gray_stencil_36_1080_1112.in1","const_p3__1080$2.out"], + ["mul_gray_stencil_40_1080_1116.in1","const_p3__1080$3.out"], + ["mul_gray_stencil_8_1080_1081.in1","const_p3__1080.out"], + ["mul_gray_stencil_11_1082_1086.in1","const_p6__1082$1.out"], + ["mul_gray_stencil_15_1082_1089.in1","const_p6__1082$2.out"], + ["mul_gray_stencil_19_1082_1095.in1","const_p6__1082$3.out"], + ["mul_gray_stencil_29_1082_1106.in1","const_p6__1082$4.out"], + ["mul_gray_stencil_33_1082_1110.in1","const_p6__1082$5.out"], + ["mul_gray_stencil_37_1082_1113.in1","const_p6__1082$6.out"], + ["mul_gray_stencil_39_1082_1115.in1","const_p6__1082$7.out"], + ["mul_gray_stencil_9_1082_1083.in1","const_p6__1082.out"], + ["mul_gray_stencil_22_1084_1098.in1","const_p7__1084$1.out"], + ["mul_gray_stencil_26_1084_1103.in1","const_p7__1084$2.out"], + ["mul_gray_stencil_38_1084_1114.in1","const_p7__1084$3.out"], + ["mul_gray_stencil_10_1084_1085.in1","const_p7__1084.out"], + ["self.in1_gray_stencil.0","mul_gray_stencil_10_1084_1085.in0"], + ["self.in1_gray_stencil.1","mul_gray_stencil_11_1082_1086.in0"], + ["self.in1_gray_stencil.2","mul_gray_stencil_12_1080_1087.in0"], + ["self.in1_gray_stencil.4","mul_gray_stencil_14_1076_1088.in0"], + ["self.in1_gray_stencil.5","mul_gray_stencil_15_1082_1089.in0"], + ["self.in1_gray_stencil.6","mul_gray_stencil_16_1090_1091.in0"], + ["self.in1_gray_stencil.7","mul_gray_stencil_17_1092_1093.in0"], + ["self.in1_gray_stencil.8","mul_gray_stencil_18_1090_1094.in0"], + ["self.in1_gray_stencil.9","mul_gray_stencil_19_1082_1095.in0"], + ["self.in1_gray_stencil.11","mul_gray_stencil_20_1076_1096.in0"], + ["self.in1_gray_stencil.12","mul_gray_stencil_21_1076_1097.in0"], + ["self.in1_gray_stencil.13","mul_gray_stencil_22_1084_1098.in0"], + ["self.in1_gray_stencil.14","mul_gray_stencil_23_1092_1099.in0"], + ["self.in1_gray_stencil.15","mul_gray_stencil_24_1100_1101.in0"], + ["self.in1_gray_stencil.16","mul_gray_stencil_25_1092_1102.in0"], + ["self.in1_gray_stencil.17","mul_gray_stencil_26_1084_1103.in0"], + ["self.in1_gray_stencil.18","mul_gray_stencil_27_1076_1104.in0"], + ["self.in1_gray_stencil.19","mul_gray_stencil_28_1076_1105.in0"], + ["self.in1_gray_stencil.20","mul_gray_stencil_29_1082_1106.in0"], + ["self.in1_gray_stencil.22","mul_gray_stencil_30_1090_1107.in0"], + ["self.in1_gray_stencil.23","mul_gray_stencil_31_1092_1108.in0"], + ["self.in1_gray_stencil.24","mul_gray_stencil_32_1090_1109.in0"], + ["self.in1_gray_stencil.25","mul_gray_stencil_33_1082_1110.in0"], + ["self.in1_gray_stencil.26","mul_gray_stencil_34_1076_1111.in0"], + ["self.in1_gray_stencil.28","mul_gray_stencil_36_1080_1112.in0"], + ["self.in1_gray_stencil.29","mul_gray_stencil_37_1082_1113.in0"], + ["self.in1_gray_stencil.30","mul_gray_stencil_38_1084_1114.in0"], + ["self.in1_gray_stencil.31","mul_gray_stencil_39_1082_1115.in0"], + ["self.in1_gray_stencil.21","mul_gray_stencil_3_1076_1077.in0"], + ["self.in1_gray_stencil.33","mul_gray_stencil_40_1080_1116.in0"], + ["self.in1_gray_stencil.36","mul_gray_stencil_43_1076_1117.in0"], + ["self.in1_gray_stencil.37","mul_gray_stencil_44_1076_1118.in0"], + ["self.in1_gray_stencil.39","mul_gray_stencil_46_1076_1119.in0"], + ["self.in1_gray_stencil.32","mul_gray_stencil_4_1076_1078.in0"], + ["self.in1_gray_stencil.40","mul_gray_stencil_5_1076_1079.in0"], + ["self.in1_gray_stencil.43","mul_gray_stencil_8_1080_1081.in0"], + ["self.in1_gray_stencil.44","mul_gray_stencil_9_1082_1083.in0"] + ] + }, + "hcompute_gray_stencil":{ + "type":["Record",[ + ["out_gray_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",3,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_432_437_438":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "add_434_436_437":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_p150__431":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0096"]} + }, + "const_p29__433":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h001d"]} + }, + "const_p77__435":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h004d"]} + }, + "const_p8__439":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_438_439_440":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_global_wrapper_stencil_1_431_432":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_global_wrapper_stencil_2_433_434":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "mul_hw_input_global_wrapper_global_wrapper_stencil_3_435_436":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["mul_hw_input_global_wrapper_global_wrapper_stencil_1_431_432.out","add_432_437_438.in0"], + ["add_434_436_437.out","add_432_437_438.in1"], + ["lshr_438_439_440.in0","add_432_437_438.out"], + ["mul_hw_input_global_wrapper_global_wrapper_stencil_2_433_434.out","add_434_436_437.in0"], + ["mul_hw_input_global_wrapper_global_wrapper_stencil_3_435_436.out","add_434_436_437.in1"], + ["mul_hw_input_global_wrapper_global_wrapper_stencil_1_431_432.in1","const_p150__431.out"], + ["mul_hw_input_global_wrapper_global_wrapper_stencil_2_433_434.in1","const_p29__433.out"], + ["mul_hw_input_global_wrapper_global_wrapper_stencil_3_435_436.in1","const_p77__435.out"], + ["lshr_438_439_440.in1","const_p8__439.out"], + ["self.out_gray_stencil","lshr_438_439_440.out"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mul_hw_input_global_wrapper_global_wrapper_stencil_1_431_432.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.1","mul_hw_input_global_wrapper_global_wrapper_stencil_2_433_434.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.2","mul_hw_input_global_wrapper_global_wrapper_stencil_3_435_436.in0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_glb_stencil","self.in0_hw_input_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_input_global_wrapper_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_input_global_wrapper_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_input_global_wrapper_global_wrapper_stencil","self.in0_hw_input_global_wrapper_glb_stencil.0"] + ] + }, + "hcompute_hw_output_glb_stencil":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_ratio_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "mult_middle_1365_1366_1367":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in1_ratio_stencil.0","mult_middle_1365_1366_1367.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mult_middle_1365_1366_1367.in1"], + ["self.out_hw_output_glb_stencil","mult_middle_1365_1366_1367.out"] + ] + }, + "hcompute_hw_output_glb_stencil_1":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_ratio_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "mult_middle_1382_1383_1384":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in1_ratio_stencil.0","mult_middle_1382_1383_1384.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mult_middle_1382_1383_1384.in1"], + ["self.out_hw_output_glb_stencil","mult_middle_1382_1383_1384.out"] + ] + }, + "hcompute_hw_output_glb_stencil_2":{ + "type":["Record",[ + ["out_hw_output_glb_stencil",["Array",16,"Bit"]], + ["in0_hw_input_global_wrapper_global_wrapper_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_ratio_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "mult_middle_1399_1400_1401":{ + "genref":"commonlib.mult_middle", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in1_ratio_stencil.0","mult_middle_1399_1400_1401.in0"], + ["self.in0_hw_input_global_wrapper_global_wrapper_stencil.0","mult_middle_1399_1400_1401.in1"], + ["self.out_hw_output_glb_stencil","mult_middle_1399_1400_1401.out"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_1":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_hw_output_global_wrapper_stencil_2":{ + "type":["Record",[ + ["out_hw_output_global_wrapper_stencil",["Array",16,"Bit"]], + ["in0_hw_output_glb_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "connections":[ + ["self.out_hw_output_global_wrapper_stencil","self.in0_hw_output_glb_stencil.0"] + ] + }, + "hcompute_ratio_stencil":{ + "type":["Record",[ + ["out_ratio_stencil",["Array",16,"Bit"]], + ["in0_reciprocal_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_sharpen_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "mul_sharpen_stencil_1_reciprocal_stencil_1_1356":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["self.in1_sharpen_stencil.0","mul_sharpen_stencil_1_reciprocal_stencil_1_1356.in0"], + ["self.in0_reciprocal_stencil.0","mul_sharpen_stencil_1_reciprocal_stencil_1_1356.in1"], + ["self.out_ratio_stencil","mul_sharpen_stencil_1_reciprocal_stencil_1_1356.out"] + ] + }, + "hcompute_reciprocal_stencil":{ + "type":["Record",[ + ["out_reciprocal_stencil",["Array",16,"Bit"]], + ["in0_gray_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "add_973n1_974":{ + "genref":"coreir.add", + "genargs":{"width":["Int",16]} + }, + "const_n1_n1":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'hffff"]} + }, + "const_p1__971":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0001"]} + }, + "rom_rom_div_lookupa0":{ + "genref":"memory.rom2", + "genargs":{"depth":["Int",256], "width":["Int",16]}, + "modargs":{"init":["Json",[256,128,85,64,51,42,36,32,28,25,23,21,19,18,17,16,15,14,13,12,12,11,11,10,10,9,9,9,8,8,8,8,7,7,7,7,6,6,6,6,6,6,5,5,5,5,5,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,153]]} + }, + "rom_rom_div_lookupa0_ren":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "umax_gray_stencil_1_971_972":{ + "genref":"commonlib.umax", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["umax_gray_stencil_1_971_972.out","add_973n1_974.in0"], + ["const_n1_n1.out","add_973n1_974.in1"], + ["rom_rom_div_lookupa0.raddr","add_973n1_974.out"], + ["umax_gray_stencil_1_971_972.in1","const_p1__971.out"], + ["self.out_reciprocal_stencil","rom_rom_div_lookupa0.rdata"], + ["rom_rom_div_lookupa0_ren.out","rom_rom_div_lookupa0.ren"], + ["umax_gray_stencil_1_971_972.in0","self.in0_gray_stencil.0"] + ] + }, + "hcompute_sharpen_stencil":{ + "type":["Record",[ + ["out_sharpen_stencil",["Array",16,"Bit"]], + ["in0_blur_unnormalized_stencil",["Array",1,["Array",16,"BitIn"]]], + ["in1_gray_stencil",["Array",1,["Array",16,"BitIn"]]] + ]], + "instances":{ + "const_p0__1335":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0000"]} + }, + "const_p255__1333":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h00ff"]} + }, + "const_p2__1326":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0002"]} + }, + "const_p8__1328":{ + "genref":"coreir.const", + "genargs":{"width":["Int",16]}, + "modargs":{"value":[["BitVector",16],"16'h0008"]} + }, + "lshr_blur_unnormalized_stencil_2_1328_1329":{ + "genref":"coreir.lshr", + "genargs":{"width":["Int",16]} + }, + "mul_1325_1326_1327":{ + "genref":"coreir.mul", + "genargs":{"width":["Int",16]} + }, + "smax_1334_1335_1336":{ + "genref":"commonlib.smax", + "genargs":{"width":["Int",16]} + }, + "smin_1332_1333_1334":{ + "genref":"commonlib.smin", + "genargs":{"width":["Int",16]} + }, + "sub_1327_1331_1332":{ + "genref":"coreir.sub", + "genargs":{"width":["Int",16]} + } + }, + "connections":[ + ["smax_1334_1335_1336.in1","const_p0__1335.out"], + ["smin_1332_1333_1334.in1","const_p255__1333.out"], + ["mul_1325_1326_1327.in1","const_p2__1326.out"], + ["lshr_blur_unnormalized_stencil_2_1328_1329.in1","const_p8__1328.out"], + ["self.in0_blur_unnormalized_stencil.0","lshr_blur_unnormalized_stencil_2_1328_1329.in0"], + ["sub_1327_1331_1332.in1","lshr_blur_unnormalized_stencil_2_1328_1329.out"], + ["self.in1_gray_stencil.0","mul_1325_1326_1327.in0"], + ["sub_1327_1331_1332.in0","mul_1325_1326_1327.out"], + ["smax_1334_1335_1336.out","self.out_sharpen_stencil"], + ["smin_1332_1333_1334.out","smax_1334_1335_1336.in0"], + ["sub_1327_1331_1332.out","smin_1332_1333_1334.in0"] + ] + } + } + } +} +} diff --git a/dse_flow/Makefile b/dse_flow/Makefile deleted file mode 100755 index c4124f19c..000000000 --- a/dse_flow/Makefile +++ /dev/null @@ -1,64 +0,0 @@ -UNAME = $(shell uname) - -ifeq ($(UNAME), Darwin) -LIB_EXT =dylib -else -LIB_EXT =so -endif - -TARGET = clockwork_dse_flow - -CXX_FLAGS = -std=c++17 -g -O0 -I $(BARVINOK_PATH) -I $(OPT_PATH) - -#ifneq ($(COREIR),1) -#CXX_FLAGS = -std=c++11 -I $(BARVINOK_PATH) -I $(OPT_PATH) -#endif - -ifneq ($(UNAME), Darwin) -CXX_FLAGS += -fPIC -endif - -LINK_FLAGS = -L ../lib -L $(OPT_LIB_PATH) -L $(ISL_PATH) -lclkwrk -lbarvinok -lisl -lntl -lgmp -lpolylibgmp -lpthread - -ifeq ($(COREIR),1) -ifndef COREIR_PATH -$(error COREIR_PATH is not set) -endif -$(info CoreIR Path is [${COREIR_PATH}]) -COREIR_INCLUDE = $(COREIR_PATH)/include -COREIR_LIB = $(COREIR_PATH)/lib - -CXX_FLAGS += -I $(COREIR_INCLUDE) -D COREIR -LINK_FLAGS += -L $(COREIR_LIB) -Wl,-rpath $(COREIR_LIB) -lcoreir -lcoreirsim -lcoreir-commonlib -endif - -TEST_FILES = dse_flow.cpp -TEST_HEADER_FILES = $(patsubst %.cpp,%.h,$(TEST_FILES)) - -LIB_CPP_FILES = ../build_set_test.cpp ../prog_splitting_test.cpp ../qexpr.cpp ../expr.cpp ../app.cpp ../isl_utils.cpp ../prog.cpp ../codegen.cpp ../ubuffer.cpp ../coreir_backend.cpp ../cgralib.cpp ../cwlib.cpp ../options.cpp ../lake_target.cpp ../utils.cpp ../example_progs.cpp ../simple_example_progs.cpp ../rdai_collateral.cpp ../verilog_backend.cpp -LIB_HEADER_FILES = $(patsubst %.cpp,%.h,$(LIB_CPP_FILES)) - -TEST_OBJ_FILES := $(patsubst %.cpp,%.o,$(TEST_FILES)) -OBJ_FILES := $(patsubst %.cpp,%.o,$(LIB_CPP_FILES)) - - -$(TARGET): libclkwrk.$(LIB_EXT) $(TEST_OBJ_FILES) - $(CXX) $(CXX_FLAGS) $(TEST_OBJ_FILES) $(LINK_FLAGS) -o $@ - -$(TARGET).o: $(TEST_FILES) $(LIB_HEADER_FILES) $(TEST_HEADER_FILES) - $(CXX) $(CXX_FLAGS) -c $< -o $@ - -libclkwrk.$(LIB_EXT): $(OBJ_FILES) -ifeq ($(UNAME), Darwin) - $(CXX) $(CXX_FLAGS) -dynamiclib -undefined dynamic_lookup $^ -o ../lib/$@ -else - $(CXX) $(CXX_FLAGS) -g -fPIC -rdynamic -shared $^ -o ../lib/$@ -endif - -%.o: %.cpp $(LIB_HEADER_FILES) - $(CXX) $(CXX_FLAGS) -c -o $@ $< - -clean: - rm -f *.o *.a - - diff --git a/dse_flow/clockwork_dse_flow b/dse_flow/clockwork_dse_flow deleted file mode 100755 index a902fc09a..000000000 Binary files a/dse_flow/clockwork_dse_flow and /dev/null differ diff --git a/dse_flow/dse_flow.cpp b/dse_flow/dse_flow.cpp deleted file mode 100755 index 17fe4cad9..000000000 --- a/dse_flow/dse_flow.cpp +++ /dev/null @@ -1,86 +0,0 @@ -#include "../build_set_test.h" -#include "../coreir_backend.h" -#ifdef COREIR -#include "../cwlib.h" -#include "../cgralib.h" -#endif -#include "../app.h" -#include "../prog_splitting_test.h" -#include "../codegen.h" -#include "../example_progs.h" -#include "../lake_target.h" -#include "../simple_example_progs.h" -// #include "../prog.h" -#include "../ubuffer.h" -#include -#include -using namespace std; - - -int main(int argc, char** argv) { - cout << "Running DSE flow" << endl; - - if (argc != 3) { - cout << "Usage: ./dse_flow app_name dse/lassen" << endl; - return 1; - } - - string app_name = argv[1]; - bool use_dse_compute = !strcmp(argv[2], "dse"); - string dir = use_dse_compute ? "dse_flow/output/dse" : "dse_flow/output/lassen"; - - - std::map func_map; - - func_map["camera_pipeline"] = camera_pipeline; - func_map["unsharp"] = unsharp; - func_map["gaussian"] = gaussian; - func_map["pointwise"] = pointwise; - func_map["harris"] = harris; - func_map["down_sample"] = down_sample; - func_map["cascade"] = cascade; - func_map["stereo"] = stereo; - func_map["resnet"] = resnet; - - auto prg_ptr = func_map[app_name]; - auto prg = prg_ptr(); - - bool gen_config_only = true; - bool multi_accessor = false; - - - cout << "====== Running CGRA Single Port test for " << prg.name << endl; - - prg.sanity_check(); - - break_up_multi_channel_inputs(prg); - break_up_multi_channel_outputs(prg); - dsa_writers(prg); - - auto cpu = unoptimized_result(prg); - - compile_for_garnet_single_port_mem(prg, dir, false, gen_config_only, multi_accessor, use_dse_compute); - generate_regression_testbench(prg); - - cout << "Output name: " << dir << "/" << prg.name << endl; - - //run verilator on all the generated verilog - if (!gen_config_only) { - string name = prg.name; - auto verilog_files = get_files("./" + dir + "/"+name+"/verilog/"); - verilog_files.push_back(name + ".v"); - verilog_files.push_back("LakeWrapper.v"); - bool extra_flag_for_lake = true; - int res = run_verilator_on(name, name + "_verilog_tb.cpp", verilog_files, extra_flag_for_lake); - assert(res == 0); - cmd("rm LakeWrapper.v"); - - auto verilator_res = verilator_results(prg.name); - compare("cgra_" + prg.name + "_cpu_vs_verilog_comparison", verilator_res, cpu); - //string app_type = "dualwithaddr"; - string app_type = "single_port_buffer"; - cpy_app_to_folder(app_type, prg.name); - } - - return 0; -} diff --git a/dse_flow/dse_flow.h b/dse_flow/dse_flow.h deleted file mode 100755 index 3aeb723e5..000000000 --- a/dse_flow/dse_flow.h +++ /dev/null @@ -1 +0,0 @@ -void dse_flow_test(); \ No newline at end of file diff --git a/example_progs.h b/example_progs.h index 7aede2683..32a267722 100644 --- a/example_progs.h +++ b/example_progs.h @@ -1,6 +1,9 @@ #pragma once #include "prog.h" +prog fp_arith(); +prog fp_pointwise(); + prog fft8_unroll0(); prog fft8_unroll2(); prog fft8_unroll4(); @@ -16,6 +19,7 @@ prog strided_conv(); prog accumulation(); //reduce prog unsharp(); prog unsharp_new(); +prog unsharp_large(); prog cascade(); //stencil prog gaussian(); //stencil prog harris(); //stencil @@ -23,6 +27,16 @@ prog harris_remove(); //manually edit prog pointwise(); //point prog brighten_blur(); //stencil prog halide_harris(); + +prog nlmeans(); +prog nlmeans_unroll(); +prog nlmeans_small(); +prog nlmeans_unroll_reorder(); +prog nlmeans_rolled_int(); +prog nlmeans_simple(); +prog nlmeans_simple_trunc(); +prog nlmeans_simple_blur(); +prog nlmeans_rolled_7x7(); prog conv_3_3(); //stencil prog conv_3_3_wide(); //stencil prog conv_3_3_rolled(); //stencil @@ -33,11 +47,23 @@ prog unet_conv_3_3(); //reduce prog resnet(); //reduce prog resnet_simple(); //for regfile debug prog resnet_tiny(); //for regfile debug +prog resnet_size_test(); //for schedule debug prog resnet_multi_tiny(); //for regfile debug //prog mini_conv_halide_fixed(); + +//all camera pipeline variants prog camera_pipeline(); //stencil prog camera_pipeline_new(); //stencil prog camera_pipeline_isscc(); //stencil +prog camera_pipeline_2x2(); //compute demosaic directly from denoised +prog camera_pipeline_2x2_unroll(); //compute demosaic directly from denoised +prog camera_pipeline_2x2_unrollx(); //compute demosaic directly from denoised +prog camera_pipeline_unrolly(); //stencil +prog camera_pipeline_extra_buf(); //stencil + +//This doesn't work in scheduler +prog camera_pipeline_extra_buf_glb(); //stencil + //prog camera_pipeline_new_trunc(); //stencil //prog camera_pipeline_trunc(); //stencil prog up_sample(); @@ -100,10 +126,12 @@ prog unsharp_glb(); prog unsharp_isscc(); prog up_sample_glb(); prog harris_color(); +prog harris_color_unroll4(); prog harris_glb2(); prog camera_pipeline_glb(); prog matmul(); +prog matmul_unroll2(); prog matmul_single(); prog matmul_fpga(); @@ -113,13 +141,19 @@ prog resnet_output_stationary_i8(); prog resnet_init_unroll(); prog resnet_init_unroll_tile(); prog resnet3_1(); +prog resnet_1x1(); prog resnet1(); +prog resnet1_docker(); prog resnet4_x(); prog resnet3_x_tiny(); prog resnet5_x(); prog resnet5_1(); prog resnet5_1_new(); prog resnet5_1_unroll(); +prog resnet5_x_unroll(); +prog resnet5_x_unroll_mic(); +prog resnet5_glb_unroll(); +prog resnet5_1_unroll_cyclic(); prog resnet5_x_new(); prog resnet_multi_channel(); @@ -140,6 +174,7 @@ prog resnet3_x_full(); prog resnet3_1_full(); prog resnet2_x_full(); prog resnet1_full(); +prog resnet_last(); //pond resnet test prog complex_mem_pond_rolled(); diff --git a/example_progs/camera_pipeline.cpp b/example_progs/camera_pipeline.cpp index 1806de858..79a624386 100644 --- a/example_progs/camera_pipeline.cpp +++ b/example_progs/camera_pipeline.cpp @@ -1,5 +1,1720 @@ #include "example_progs.h" +prog camera_pipeline_unrolly() { + prog prg; + prg.compute_unit_file = "camera_pipeline_unrolly_compute.h"; + prg.name = "camera_pipeline_unrolly"; + +// Stencil &hw_input_stencil = arg_2; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_4; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_s0_y_yio", 0, 96); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_s0_x_x", 0, 256); + +//store is: hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_s0_x_x, (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil((hw_input_global_wrapper_s0_x_x + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -4)", "(hw_input_global_wrapper_s0_x_x + -4)"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_s0_y_yio*2)", "hw_input_global_wrapper_s0_x_x"); + +//store is: hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_s0_x_x, ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil((hw_input_global_wrapper_s0_x_x + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_1 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_function("hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -3)", "(hw_input_global_wrapper_s0_x_x + -4)"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_store("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + 1)", "hw_input_global_wrapper_s0_x_x"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y_yio", 0, 96); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 256); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_1 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_load("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_global_wrapper_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing denoised$1.stencil + auto denoised_1_s0_y_yio = prg.add_loop("denoised_1_s0_y_yio", 0, 94); + auto denoised_1_s0_x_x = denoised_1_s0_y_yio->add_loop("denoised_1_s0_x_x", 0, 252); + +//store is: denoised$1.stencil(denoised_1_s0_x_x, (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 4), ((denoised_1_s0_y_yio*2) + 2)))))) + auto hcompute_denoised_1_stencil = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_function("hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 4)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y_yio*2)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "denoised_1_s0_x_x"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "(denoised_1_s0_x_x + 4)"); + prg.buffer_port_widths["denoised_1_stencil"] = 16; + hcompute_denoised_1_stencil->add_store("denoised_1_stencil", "(denoised_1_s0_y_yio*2)", "denoised_1_s0_x_x"); + +//store is: denoised$1.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil(denoised_1_s0_x_x, ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 4), ((denoised_1_s0_y_yio*2) + 3)))))) + auto hcompute_denoised_1_stencil_1 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_function("hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "(denoised_1_s0_x_x + 4)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 5)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 1)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "denoised_1_s0_x_x"); + hcompute_denoised_1_stencil_1->add_store("denoised_1_stencil", "((denoised_1_s0_y_yio*2) + 1)", "denoised_1_s0_x_x"); + +//consuming denoised$1.stencil +////producing b_b.stencil + auto b_b_s0_y = prg.add_loop("b_b_s0_y", 0, 93); + auto b_b_s0_x = b_b_s0_y->add_loop("b_b_s0_x", 0, 125); + +//store is: b_b.stencil(b_b_s0_x, b_b_s0_y) = denoised$1.stencil(((b_b_s0_x*2) + 2), ((b_b_s0_y*2) + 1)) + auto hcompute_b_b_stencil = b_b_s0_x->add_op("op_hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_function("hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_load("denoised_1_stencil", "((b_b_s0_y*2) + 1)", "((b_b_s0_x*2) + 2)"); + prg.buffer_port_widths["b_b_stencil"] = 16; + hcompute_b_b_stencil->add_store("b_b_stencil", "b_b_s0_y", "b_b_s0_x"); + +//consuming b_b.stencil +////producing g_gb.stencil + auto g_gb_s0_y = prg.add_loop("g_gb_s0_y", 0, 94); + auto g_gb_s0_x = g_gb_s0_y->add_loop("g_gb_s0_x", 0, 126); + +//store is: g_gb.stencil(g_gb_s0_x, g_gb_s0_y) = denoised$1.stencil(((g_gb_s0_x*2) + 1), ((g_gb_s0_y*2) + 1)) + auto hcompute_g_gb_stencil = g_gb_s0_x->add_op("op_hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_function("hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_load("denoised_1_stencil", "((g_gb_s0_y*2) + 1)", "((g_gb_s0_x*2) + 1)"); + prg.buffer_port_widths["g_gb_stencil"] = 16; + hcompute_g_gb_stencil->add_store("g_gb_stencil", "g_gb_s0_y", "g_gb_s0_x"); + +//consuming g_gb.stencil +////producing g_gr.stencil + auto g_gr_s0_y = prg.add_loop("g_gr_s0_y", 0, 94); + auto g_gr_s0_x = g_gr_s0_y->add_loop("g_gr_s0_x", 0, 126); + +//store is: g_gr.stencil(g_gr_s0_x, g_gr_s0_y) = denoised$1.stencil((g_gr_s0_x*2), (g_gr_s0_y*2)) + auto hcompute_g_gr_stencil = g_gr_s0_x->add_op("op_hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_function("hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_load("denoised_1_stencil", "(g_gr_s0_y*2)", "(g_gr_s0_x*2)"); + prg.buffer_port_widths["g_gr_stencil"] = 16; + hcompute_g_gr_stencil->add_store("g_gr_stencil", "g_gr_s0_y", "g_gr_s0_x"); + +//consuming g_gr.stencil +////producing g_b.stencil + auto g_b_s0_y = prg.add_loop("g_b_s0_y", 0, 93); + auto g_b_s0_x = g_b_s0_y->add_loop("g_b_s0_x", 0, 125); + +//store is: g_b.stencil(g_b_s0_x, g_b_s0_y) = select((absd(g_gb.stencil(g_b_s0_x, g_b_s0_y), g_gb.stencil((g_b_s0_x + 1), g_b_s0_y)) < absd(g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)), g_gr.stencil((g_b_s0_x + 1), g_b_s0_y))), ((g_gb.stencil(g_b_s0_x, g_b_s0_y) + g_gb.stencil((g_b_s0_x + 1), g_b_s0_y))/(uint16)2), ((g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)) + g_gr.stencil((g_b_s0_x + 1), g_b_s0_y))/(uint16)2)) + auto hcompute_g_b_stencil = g_b_s0_x->add_op("op_hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_function("hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "g_b_s0_x"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + prg.buffer_port_widths["g_b_stencil"] = 16; + hcompute_g_b_stencil->add_store("g_b_stencil", "g_b_s0_y", "g_b_s0_x"); + +//consuming g_b.stencil +////producing b_gb.stencil + auto b_gb_s0_y = prg.add_loop("b_gb_s0_y", 0, 92); + auto b_gb_s0_x = b_gb_s0_y->add_loop("b_gb_s0_x", 0, 124); + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + ((b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) - ((g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_b_gb_stencil = b_gb_s0_x->add_op("op_hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_function("hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_gb_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + prg.buffer_port_widths["b_gb_stencil"] = 16; + hcompute_b_gb_stencil->add_store("b_gb_stencil", "b_gb_s0_y", "b_gb_s0_x"); + +//consuming b_gb.stencil +////producing b_gr.stencil + auto b_gr_s0_y = prg.add_loop("b_gr_s0_y", 0, 92); + auto b_gr_s0_x = b_gr_s0_y->add_loop("b_gr_s0_x", 0, 124); + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + ((b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + b_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) - ((g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + g_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) + auto hcompute_b_gr_stencil = b_gr_s0_x->add_op("op_hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_function("hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_gr_stencil", "(b_gr_s0_y + 1)", "(b_gr_s0_x + 1)"); + prg.buffer_port_widths["b_gr_stencil"] = 16; + hcompute_b_gr_stencil->add_store("b_gr_stencil", "b_gr_s0_y", "b_gr_s0_x"); + +//consuming b_gr.stencil +////producing g_r.stencil + auto g_r_s0_y = prg.add_loop("g_r_s0_y", 0, 93); + auto g_r_s0_x = g_r_s0_y->add_loop("g_r_s0_x", 0, 125); + +//store is: g_r.stencil(g_r_s0_x, g_r_s0_y) = select((absd(g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)), g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1))) < absd(g_gb.stencil(g_r_s0_x, g_r_s0_y), g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)))), ((g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)) + g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1)))/(uint16)2), ((g_gb.stencil(g_r_s0_x, g_r_s0_y) + g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)))/(uint16)2)) + auto hcompute_g_r_stencil = g_r_s0_x->add_op("op_hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_function("hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "g_r_s0_y", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + prg.buffer_port_widths["g_r_stencil"] = 16; + hcompute_g_r_stencil->add_store("g_r_stencil", "g_r_s0_y", "g_r_s0_x"); + +//consuming g_r.stencil +////producing b_r.stencil + auto b_r_s0_y = prg.add_loop("b_r_s0_y", 0, 92); + auto b_r_s0_x = b_r_s0_y->add_loop("b_r_s0_x", 0, 124); + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + b_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)) - ((g_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + g_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + b_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2)) - ((g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + g_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2))) + auto hcompute_b_r_stencil = b_r_s0_x->add_op("op_hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_function("hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_r_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + prg.buffer_port_widths["b_r_stencil"] = 16; + hcompute_b_r_stencil->add_store("b_r_stencil", "b_r_s0_y", "b_r_s0_x"); + +//consuming b_r.stencil +////producing r_r.stencil + auto r_r_s0_y = prg.add_loop("r_r_s0_y", 0, 93); + auto r_r_s0_x = r_r_s0_y->add_loop("r_r_s0_x", 0, 125); + +//store is: r_r.stencil(r_r_s0_x, r_r_s0_y) = denoised$1.stencil(((r_r_s0_x*2) + 1), ((r_r_s0_y*2) + 2)) + auto hcompute_r_r_stencil = r_r_s0_x->add_op("op_hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_function("hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_load("denoised_1_stencil", "((r_r_s0_y*2) + 2)", "((r_r_s0_x*2) + 1)"); + prg.buffer_port_widths["r_r_stencil"] = 16; + hcompute_r_r_stencil->add_store("r_r_stencil", "r_r_s0_y", "r_r_s0_x"); + +//consuming r_r.stencil +////producing r_b.stencil + auto r_b_s0_y = prg.add_loop("r_b_s0_y", 0, 92); + auto r_b_s0_x = r_b_s0_y->add_loop("r_b_s0_x", 0, 124); + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil((r_b_s0_x + 1), r_b_s0_y) + r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x + 1), r_b_s0_y) + g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil(r_b_s0_x, r_b_s0_y) + r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil(r_b_s0_x, r_b_s0_y) + g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2))) + auto hcompute_r_b_stencil = r_b_s0_x->add_op("op_hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_function("hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_load("g_b_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + prg.buffer_port_widths["r_b_stencil"] = 16; + hcompute_r_b_stencil->add_store("r_b_stencil", "r_b_s0_y", "r_b_s0_x"); + +//consuming r_b.stencil +////producing r_gb.stencil + auto r_gb_s0_y = prg.add_loop("r_gb_s0_y", 0, 92); + auto r_gb_s0_x = r_gb_s0_y->add_loop("r_gb_s0_x", 0, 124); + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + ((r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_r_gb_stencil = r_gb_s0_x->add_op("op_hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_function("hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_load("g_gb_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + prg.buffer_port_widths["r_gb_stencil"] = 16; + hcompute_r_gb_stencil->add_store("r_gb_stencil", "r_gb_s0_y", "r_gb_s0_x"); + +//consuming r_gb.stencil +////producing r_gr.stencil + auto r_gr_s0_y = prg.add_loop("r_gr_s0_y", 0, 92); + auto r_gr_s0_x = r_gr_s0_y->add_loop("r_gr_s0_x", 0, 124); + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + ((r_r.stencil(r_gr_s0_x, r_gr_s0_y) + r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y))/(uint16)2)) - ((g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + g_r.stencil(r_gr_s0_x, r_gr_s0_y))/(uint16)2)) + auto hcompute_r_gr_stencil = r_gr_s0_x->add_op("op_hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_function("hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_load("g_gr_stencil", "(r_gr_s0_y + 1)", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + prg.buffer_port_widths["r_gr_stencil"] = 16; + hcompute_r_gr_stencil->add_store("r_gr_stencil", "r_gr_s0_y", "r_gr_s0_x"); + +//consuming r_gr.stencil +////producing demosaicked$1.stencil + auto demosaicked_1_s0_y_yio = prg.add_loop("demosaicked_1_s0_y_yio", 0, 92); + auto demosaicked_1_s0_x_x = demosaicked_1_s0_y_yio->add_loop("demosaicked_1_s0_x_x", 0, 248); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio*2), 0) = select(((demosaicked_1_s0_x_x % 2) == 0), r_gr.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio), r_r.stencil(((demosaicked_1_s0_x_x/2) + 1), demosaicked_1_s0_y_yio)) + auto hcompute_demosaicked_1_stencil = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_function("hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_load("r_gr_stencil", "demosaicked_1_s0_y_yio", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil->add_load("r_r_stencil", "demosaicked_1_s0_y_yio", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + hcompute_demosaicked_1_stencil->add_store("demosaicked_1_stencil", "0", "(demosaicked_1_s0_y_yio*2)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio*2), 1) = select(((demosaicked_1_s0_x_x % 2) == 0), g_gr.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y_yio + 1)), g_r.stencil(((demosaicked_1_s0_x_x/2) + 1), demosaicked_1_s0_y_yio)) + auto hcompute_demosaicked_1_stencil_1 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_function("hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_load("g_gr_stencil", "(demosaicked_1_s0_y_yio + 1)", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_load("g_r_stencil", "demosaicked_1_s0_y_yio", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_store("demosaicked_1_stencil", "1", "(demosaicked_1_s0_y_yio*2)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_1->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio*2), 2) = select(((demosaicked_1_s0_x_x % 2) == 0), b_gr.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio), b_r.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio)) + auto hcompute_demosaicked_1_stencil_2 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_function("hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_load("b_gr_stencil", "demosaicked_1_s0_y_yio", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_load("b_r_stencil", "demosaicked_1_s0_y_yio", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_store("demosaicked_1_stencil", "2", "(demosaicked_1_s0_y_yio*2)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y_yio*2) + 1), 0) = select(((demosaicked_1_s0_x_x % 2) == 0), r_b.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio), r_gb.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio)) + auto hcompute_demosaicked_1_stencil_3 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_function("hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_load("r_b_stencil", "demosaicked_1_s0_y_yio", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_3->add_load("r_gb_stencil", "demosaicked_1_s0_y_yio", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_3->add_store("demosaicked_1_stencil", "0", "((demosaicked_1_s0_y_yio*2) + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_3->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y_yio*2) + 1), 1) = select(((demosaicked_1_s0_x_x % 2) == 0), g_b.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y_yio + 1)), g_gb.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y_yio + 1))) + auto hcompute_demosaicked_1_stencil_4 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_function("hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_load("g_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_4->add_load("g_gb_stencil", "(demosaicked_1_s0_y_yio + 1)", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_4->add_store("demosaicked_1_stencil", "1", "((demosaicked_1_s0_y_yio*2) + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_4->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y_yio*2) + 1), 2) = select(((demosaicked_1_s0_x_x % 2) == 0), b_b.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y_yio + 1)), b_gb.stencil((demosaicked_1_s0_x_x/2), demosaicked_1_s0_y_yio)) + auto hcompute_demosaicked_1_stencil_5 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_function("hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_load("b_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_5->add_load("b_gb_stencil", "demosaicked_1_s0_y_yio", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_5->add_store("demosaicked_1_stencil", "2", "((demosaicked_1_s0_y_yio*2) + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_5->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + +//consuming demosaicked$1.stencil +////producing corrected.stencil + auto corrected_s0_y_yio = prg.add_loop("corrected_s0_y_yio", 0, 92); + auto corrected_s0_x_x = corrected_s0_y_yio->add_loop("corrected_s0_x_x", 0, 248); + +//store is: corrected.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_function("hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + prg.buffer_port_widths["corrected_stencil"] = 16; + hcompute_corrected_stencil->add_store("corrected_stencil", "0", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + +//store is: corrected.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_1 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_function("hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil_1->add_store("corrected_stencil", "1", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + +//store is: corrected.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_2 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_function("hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + hcompute_corrected_stencil_2->add_store("corrected_stencil", "2", "(corrected_s0_y_yio*2)", "corrected_s0_x_x"); + +//store is: corrected.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_3 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_function("hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_3->add_store("corrected_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + +//store is: corrected.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_4 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_function("hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_4->add_store("corrected_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + +//store is: corrected.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_5 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_function("hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + hcompute_corrected_stencil_5->add_store("corrected_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "corrected_s0_x_x"); + +//consuming corrected.stencil +////producing curvea0 + +//consuming curvea0 +////producing curved.stencil + auto curved_s0_y_yio = prg.add_loop("curved_s0_y_yio", 0, 92); + auto curved_s0_x_x = curved_s0_y_yio->add_loop("curved_s0_x_x", 0, 248); + +//store is: curved.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil = curved_s0_x_x->add_op("op_hcompute_curved_stencil"); + hcompute_curved_stencil->add_function("hcompute_curved_stencil"); + hcompute_curved_stencil->add_load("corrected_stencil", "0", "(curved_s0_y_yio*2)", "curved_s0_x_x"); + prg.buffer_port_widths["curved_stencil"] = 16; + hcompute_curved_stencil->add_store("curved_stencil", "0", "(curved_s0_y_yio*2)", "curved_s0_x_x"); + //hcompute_curved_stencil->index_variable_prefetch_cycle(1); + hcompute_curved_stencil->add_latency(1); + +//store is: curved.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_1 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_function("hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_load("corrected_stencil", "1", "(curved_s0_y_yio*2)", "curved_s0_x_x"); + hcompute_curved_stencil_1->add_store("curved_stencil", "1", "(curved_s0_y_yio*2)", "curved_s0_x_x"); + //hcompute_curved_stencil_1->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_1->add_latency(1); + +//store is: curved.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_2 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_function("hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_load("corrected_stencil", "2", "(curved_s0_y_yio*2)", "curved_s0_x_x"); + hcompute_curved_stencil_2->add_store("curved_stencil", "2", "(curved_s0_y_yio*2)", "curved_s0_x_x"); + //hcompute_curved_stencil_2->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_2->add_latency(1); + +//store is: curved.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_3 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_function("hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_load("corrected_stencil", "0", "((curved_s0_y_yio*2) + 1)", "curved_s0_x_x"); + hcompute_curved_stencil_3->add_store("curved_stencil", "0", "((curved_s0_y_yio*2) + 1)", "curved_s0_x_x"); + //hcompute_curved_stencil_3->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_3->add_latency(1); + +//store is: curved.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_4 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_function("hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_load("corrected_stencil", "1", "((curved_s0_y_yio*2) + 1)", "curved_s0_x_x"); + hcompute_curved_stencil_4->add_store("curved_stencil", "1", "((curved_s0_y_yio*2) + 1)", "curved_s0_x_x"); + //hcompute_curved_stencil_4->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_4->add_latency(1); + +//store is: curved.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_5 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_function("hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_load("corrected_stencil", "2", "((curved_s0_y_yio*2) + 1)", "curved_s0_x_x"); + hcompute_curved_stencil_5->add_store("curved_stencil", "2", "((curved_s0_y_yio*2) + 1)", "curved_s0_x_x"); + //hcompute_curved_stencil_5->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_5->add_latency(1); + +//consuming curved.stencil + auto hw_output_s0_y_yi_yio = prg.add_loop("hw_output_s0_y_yi_yio", 0, 92); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi_yio->add_loop("hw_output_s0_x_xi_xi", 0, 248); + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2)) = curved.stencil(hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2), 0) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("curved_stencil", "0", "(hw_output_s0_y_yi_yio*2)", "hw_output_s0_x_xi_xi"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "hw_output_s0_x_xi_xi", "0"); + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2)) = curved.stencil(hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2), 1) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("curved_stencil", "1", "(hw_output_s0_y_yi_yio*2)", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "hw_output_s0_x_xi_xi", "1"); + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2)) = curved.stencil(hw_output_s0_x_xi_xi, (hw_output_s0_y_yi_yio*2), 2) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("curved_stencil", "2", "(hw_output_s0_y_yi_yio*2)", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "hw_output_s0_x_xi_xi", "2"); + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1), 0) + auto hcompute_hw_output_glb_stencil_3 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_function("hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_load("curved_stencil", "0", "((hw_output_s0_y_yi_yio*2) + 1)", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_3->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "hw_output_s0_x_xi_xi", "0"); + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1), 1) + auto hcompute_hw_output_glb_stencil_4 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_function("hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_load("curved_stencil", "1", "((hw_output_s0_y_yi_yio*2) + 1)", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_4->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "hw_output_s0_x_xi_xi", "1"); + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(hw_output_s0_x_xi_xi, ((hw_output_s0_y_yi_yio*2) + 1), 2) + auto hcompute_hw_output_glb_stencil_5 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_function("hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_load("curved_stencil", "2", "((hw_output_s0_y_yi_yio*2) + 1)", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_5->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "hw_output_s0_x_xi_xi", "2"); + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi_yio = prg.add_loop("hw_output_global_wrapper_s0_y_yi_yio", 0, 92); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi_yio->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 248); + +//store is: hw_output_global_wrapper.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + +//store is: hw_output_global_wrapper.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + +//store is: hw_output_global_wrapper.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + +//store is: hw_output_global_wrapper.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_3 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_function("hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + hcompute_hw_output_global_wrapper_stencil_3->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + +//store is: hw_output_global_wrapper.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_4 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_function("hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + hcompute_hw_output_global_wrapper_stencil_4->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + +//store is: hw_output_global_wrapper.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_5 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_function("hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + hcompute_hw_output_global_wrapper_stencil_5->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + + return prg; +} + + +prog camera_pipeline_extra_buf_glb() { + prog prg; + prg.compute_unit_file = "camera_pipeline_extra_buf_glb_compute.h"; + prg.name = "camera_pipeline_extra_buf_glb"; + +// Stencil &hw_input_stencil = arg_2; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_4; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 192); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x_x", 0, 128); + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), hw_input_global_wrapper_s0_y) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), (hw_input_global_wrapper_s0_y + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -4)"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "(hw_input_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), hw_input_global_wrapper_s0_y) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), (hw_input_global_wrapper_s0_y + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil_1 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_function("hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -3)"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y", 0, 192); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 128); + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_1 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing denoised$1.stencil + auto denoised_1_s0_y = prg.add_loop("denoised_1_s0_y", 0, 188); + auto denoised_1_s0_x_x = denoised_1_s0_y->add_loop("denoised_1_s0_x_x", 0, 126); + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), denoised_1_s0_y) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), (denoised_1_s0_y + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), (denoised_1_s0_y + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), denoised_1_s0_y), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), (denoised_1_s0_y + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), (denoised_1_s0_y + 2)))))) + auto hcompute_denoised_1_stencil = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_function("hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 4)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "denoised_1_s0_y", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "(denoised_1_s0_x_x*2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "((denoised_1_s0_x_x*2) + 4)"); + prg.buffer_port_widths["denoised_1_stencil"] = 16; + hcompute_denoised_1_stencil->add_store("denoised_1_stencil", "denoised_1_s0_y", "(denoised_1_s0_x_x*2)"); + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), denoised_1_s0_y) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), (denoised_1_s0_y + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), (denoised_1_s0_y + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), denoised_1_s0_y), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), (denoised_1_s0_y + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), (denoised_1_s0_y + 2)))))) + auto hcompute_denoised_1_stencil_1 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_function("hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "((denoised_1_s0_x_x*2) + 5)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 4)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "denoised_1_s0_y", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "((denoised_1_s0_x_x*2) + 1)"); + hcompute_denoised_1_stencil_1->add_store("denoised_1_stencil", "denoised_1_s0_y", "((denoised_1_s0_x_x*2) + 1)"); + +//consuming denoised$1.stencil +////producing b_b.stencil + auto b_b_s0_y = prg.add_loop("b_b_s0_y", 0, 93); + auto b_b_s0_x_x = b_b_s0_y->add_loop("b_b_s0_x_x", 0, 63); + +//store is: b_b.stencil((b_b_s0_x_x*2), b_b_s0_y) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), ((b_b_s0_y*2) + 1)) + auto hcompute_b_b_stencil = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_function("hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_load("denoised_1_stencil", "((b_b_s0_y*2) + 1)", "((b_b_s0_x_x*4) + 2)"); + prg.buffer_port_widths["b_b_stencil"] = 16; + hcompute_b_b_stencil->add_store("b_b_stencil", "b_b_s0_y", "(b_b_s0_x_x*2)"); + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), b_b_s0_y) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), ((b_b_s0_y*2) + 1)) + auto hcompute_b_b_stencil_1 = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil_1"); + hcompute_b_b_stencil_1->add_function("hcompute_b_b_stencil_1"); + hcompute_b_b_stencil_1->add_load("denoised_1_stencil", "((b_b_s0_y*2) + 1)", "((b_b_s0_x_x*4) + 4)"); + hcompute_b_b_stencil_1->add_store("b_b_stencil", "b_b_s0_y", "((b_b_s0_x_x*2) + 1)"); + +//consuming b_b.stencil +////producing g_gb.stencil + auto g_gb_s0_y = prg.add_loop("g_gb_s0_y", 0, 94); + auto g_gb_s0_x_x = g_gb_s0_y->add_loop("g_gb_s0_x_x", 0, 63); + +//store is: g_gb.stencil((g_gb_s0_x_x*2), g_gb_s0_y) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), ((g_gb_s0_y*2) + 1)) + auto hcompute_g_gb_stencil = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_function("hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_load("denoised_1_stencil", "((g_gb_s0_y*2) + 1)", "((g_gb_s0_x_x*4) + 1)"); + prg.buffer_port_widths["g_gb_stencil"] = 16; + hcompute_g_gb_stencil->add_store("g_gb_stencil", "g_gb_s0_y", "(g_gb_s0_x_x*2)"); + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), g_gb_s0_y) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), ((g_gb_s0_y*2) + 1)) + auto hcompute_g_gb_stencil_1 = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil_1"); + hcompute_g_gb_stencil_1->add_function("hcompute_g_gb_stencil_1"); + hcompute_g_gb_stencil_1->add_load("denoised_1_stencil", "((g_gb_s0_y*2) + 1)", "((g_gb_s0_x_x*4) + 3)"); + hcompute_g_gb_stencil_1->add_store("g_gb_stencil", "g_gb_s0_y", "((g_gb_s0_x_x*2) + 1)"); + +//consuming g_gb.stencil +////producing g_gr.stencil + auto g_gr_s0_y = prg.add_loop("g_gr_s0_y", 0, 94); + auto g_gr_s0_x_x = g_gr_s0_y->add_loop("g_gr_s0_x_x", 0, 63); + +//store is: g_gr.stencil((g_gr_s0_x_x*2), g_gr_s0_y) = denoised$1.stencil((g_gr_s0_x_x*4), (g_gr_s0_y*2)) + auto hcompute_g_gr_stencil = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_function("hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_load("denoised_1_stencil", "(g_gr_s0_y*2)", "(g_gr_s0_x_x*4)"); + prg.buffer_port_widths["g_gr_stencil"] = 16; + hcompute_g_gr_stencil->add_store("g_gr_stencil", "g_gr_s0_y", "(g_gr_s0_x_x*2)"); + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), g_gr_s0_y) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), (g_gr_s0_y*2)) + auto hcompute_g_gr_stencil_1 = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil_1"); + hcompute_g_gr_stencil_1->add_function("hcompute_g_gr_stencil_1"); + hcompute_g_gr_stencil_1->add_load("denoised_1_stencil", "(g_gr_s0_y*2)", "((g_gr_s0_x_x*4) + 2)"); + hcompute_g_gr_stencil_1->add_store("g_gr_stencil", "g_gr_s0_y", "((g_gr_s0_x_x*2) + 1)"); + +//consuming g_gr.stencil +////producing g_b.stencil + auto g_b_s0_y = prg.add_loop("g_b_s0_y", 0, 93); + auto g_b_s0_x = g_b_s0_y->add_loop("g_b_s0_x", 0, 125); + +//store is: g_b.stencil(g_b_s0_x, g_b_s0_y) = select((absd(g_gb.stencil(g_b_s0_x, g_b_s0_y), g_gb.stencil((g_b_s0_x + 1), g_b_s0_y)) < absd(g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)), g_gr.stencil((g_b_s0_x + 1), g_b_s0_y))), ((g_gb.stencil(g_b_s0_x, g_b_s0_y) + g_gb.stencil((g_b_s0_x + 1), g_b_s0_y))/(uint16)2), ((g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)) + g_gr.stencil((g_b_s0_x + 1), g_b_s0_y))/(uint16)2)) + auto hcompute_g_b_stencil = g_b_s0_x->add_op("op_hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_function("hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "g_b_s0_x"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + prg.buffer_port_widths["g_b_stencil"] = 16; + hcompute_g_b_stencil->add_store("g_b_stencil", "g_b_s0_y", "g_b_s0_x"); + +//consuming g_b.stencil +////producing b_gb.stencil + auto b_gb_s0_y = prg.add_loop("b_gb_s0_y", 0, 92); + auto b_gb_s0_x = b_gb_s0_y->add_loop("b_gb_s0_x", 0, 124); + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + ((b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) - ((g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_b_gb_stencil = b_gb_s0_x->add_op("op_hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_function("hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_gb_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + prg.buffer_port_widths["b_gb_stencil"] = 16; + hcompute_b_gb_stencil->add_store("b_gb_stencil", "b_gb_s0_y", "b_gb_s0_x"); + +//consuming b_gb.stencil +////producing b_gr.stencil + auto b_gr_s0_y = prg.add_loop("b_gr_s0_y", 0, 92); + auto b_gr_s0_x = b_gr_s0_y->add_loop("b_gr_s0_x", 0, 124); + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + ((b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + b_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) - ((g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + g_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) + auto hcompute_b_gr_stencil = b_gr_s0_x->add_op("op_hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_function("hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_gr_stencil", "(b_gr_s0_y + 1)", "(b_gr_s0_x + 1)"); + prg.buffer_port_widths["b_gr_stencil"] = 16; + hcompute_b_gr_stencil->add_store("b_gr_stencil", "b_gr_s0_y", "b_gr_s0_x"); + +//consuming b_gr.stencil +////producing g_r.stencil + auto g_r_s0_y = prg.add_loop("g_r_s0_y", 0, 93); + auto g_r_s0_x = g_r_s0_y->add_loop("g_r_s0_x", 0, 125); + +//store is: g_r.stencil(g_r_s0_x, g_r_s0_y) = select((absd(g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)), g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1))) < absd(g_gb.stencil(g_r_s0_x, g_r_s0_y), g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)))), ((g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)) + g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1)))/(uint16)2), ((g_gb.stencil(g_r_s0_x, g_r_s0_y) + g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)))/(uint16)2)) + auto hcompute_g_r_stencil = g_r_s0_x->add_op("op_hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_function("hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "g_r_s0_y", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + prg.buffer_port_widths["g_r_stencil"] = 16; + hcompute_g_r_stencil->add_store("g_r_stencil", "g_r_s0_y", "g_r_s0_x"); + +//consuming g_r.stencil +////producing b_r.stencil + auto b_r_s0_y = prg.add_loop("b_r_s0_y", 0, 92); + auto b_r_s0_x = b_r_s0_y->add_loop("b_r_s0_x", 0, 124); + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + b_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)) - ((g_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + g_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + b_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2)) - ((g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + g_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2))) + auto hcompute_b_r_stencil = b_r_s0_x->add_op("op_hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_function("hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_r_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + prg.buffer_port_widths["b_r_stencil"] = 16; + hcompute_b_r_stencil->add_store("b_r_stencil", "b_r_s0_y", "b_r_s0_x"); + +//consuming b_r.stencil +////producing r_r.stencil + auto r_r_s0_y = prg.add_loop("r_r_s0_y", 0, 93); + auto r_r_s0_x_x = r_r_s0_y->add_loop("r_r_s0_x_x", 0, 63); + +//store is: r_r.stencil((r_r_s0_x_x*2), r_r_s0_y) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y*2) + 2)) + auto hcompute_r_r_stencil = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_function("hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_load("denoised_1_stencil", "((r_r_s0_y*2) + 2)", "((r_r_s0_x_x*4) + 1)"); + prg.buffer_port_widths["r_r_stencil"] = 16; + hcompute_r_r_stencil->add_store("r_r_stencil", "r_r_s0_y", "(r_r_s0_x_x*2)"); + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), r_r_s0_y) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y*2) + 2)) + auto hcompute_r_r_stencil_1 = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil_1"); + hcompute_r_r_stencil_1->add_function("hcompute_r_r_stencil_1"); + hcompute_r_r_stencil_1->add_load("denoised_1_stencil", "((r_r_s0_y*2) + 2)", "((r_r_s0_x_x*4) + 3)"); + hcompute_r_r_stencil_1->add_store("r_r_stencil", "r_r_s0_y", "((r_r_s0_x_x*2) + 1)"); + +//consuming r_r.stencil +////producing r_b.stencil + auto r_b_s0_y = prg.add_loop("r_b_s0_y", 0, 92); + auto r_b_s0_x = r_b_s0_y->add_loop("r_b_s0_x", 0, 124); + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil((r_b_s0_x + 1), r_b_s0_y) + r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x + 1), r_b_s0_y) + g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil(r_b_s0_x, r_b_s0_y) + r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil(r_b_s0_x, r_b_s0_y) + g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2))) + auto hcompute_r_b_stencil = r_b_s0_x->add_op("op_hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_function("hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_load("g_b_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + prg.buffer_port_widths["r_b_stencil"] = 16; + hcompute_r_b_stencil->add_store("r_b_stencil", "r_b_s0_y", "r_b_s0_x"); + +//consuming r_b.stencil +////producing r_gb.stencil + auto r_gb_s0_y = prg.add_loop("r_gb_s0_y", 0, 92); + auto r_gb_s0_x = r_gb_s0_y->add_loop("r_gb_s0_x", 0, 124); + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + ((r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_r_gb_stencil = r_gb_s0_x->add_op("op_hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_function("hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_load("g_gb_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + prg.buffer_port_widths["r_gb_stencil"] = 16; + hcompute_r_gb_stencil->add_store("r_gb_stencil", "r_gb_s0_y", "r_gb_s0_x"); + +//consuming r_gb.stencil +////producing r_gr.stencil + auto r_gr_s0_y = prg.add_loop("r_gr_s0_y", 0, 92); + auto r_gr_s0_x = r_gr_s0_y->add_loop("r_gr_s0_x", 0, 124); + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + ((r_r.stencil(r_gr_s0_x, r_gr_s0_y) + r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y))/(uint16)2)) - ((g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + g_r.stencil(r_gr_s0_x, r_gr_s0_y))/(uint16)2)) + auto hcompute_r_gr_stencil = r_gr_s0_x->add_op("op_hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_function("hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_load("g_gr_stencil", "(r_gr_s0_y + 1)", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + prg.buffer_port_widths["r_gr_stencil"] = 16; + hcompute_r_gr_stencil->add_store("r_gr_stencil", "r_gr_s0_y", "r_gr_s0_x"); + +//consuming r_gr.stencil +////producing demosaicked$1.stencil + auto demosaicked_1_s0_y = prg.add_loop("demosaicked_1_s0_y", 0, 184); + auto demosaicked_1_s0_x_x = demosaicked_1_s0_y->add_loop("demosaicked_1_s0_x_x", 0, 124); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), demosaicked_1_s0_y, 0) = select(((demosaicked_1_s0_y % 2) == 0), r_gr.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2)), r_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2))) + auto hcompute_demosaicked_1_stencil = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_function("hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_load("r_b_stencil", "floor((demosaicked_1_s0_y/2))", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil->add_load("r_gr_stencil", "floor((demosaicked_1_s0_y/2))", "demosaicked_1_s0_x_x"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + hcompute_demosaicked_1_stencil->add_store("demosaicked_1_stencil", "0", "demosaicked_1_s0_y", "(demosaicked_1_s0_x_x*2)"); + hcompute_demosaicked_1_stencil->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), demosaicked_1_s0_y, 1) = select(((demosaicked_1_s0_y % 2) == 0), g_gr.stencil((demosaicked_1_s0_x_x + 1), ((demosaicked_1_s0_y/2) + 1)), g_b.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y/2) + 1))) + auto hcompute_demosaicked_1_stencil_1 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_function("hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_load("g_b_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_1->add_load("g_gr_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_1->add_store("demosaicked_1_stencil", "1", "demosaicked_1_s0_y", "(demosaicked_1_s0_x_x*2)"); + hcompute_demosaicked_1_stencil_1->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), demosaicked_1_s0_y, 2) = select(((demosaicked_1_s0_y % 2) == 0), b_gr.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2)), b_b.stencil(demosaicked_1_s0_x_x, ((demosaicked_1_s0_y/2) + 1))) + auto hcompute_demosaicked_1_stencil_2 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_function("hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_load("b_b_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->add_load("b_gr_stencil", "floor((demosaicked_1_s0_y/2))", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->add_store("demosaicked_1_stencil", "2", "demosaicked_1_s0_y", "(demosaicked_1_s0_x_x*2)"); + hcompute_demosaicked_1_stencil_2->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), demosaicked_1_s0_y, 0) = select(((demosaicked_1_s0_y % 2) == 0), r_r.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y/2)), r_gb.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2))) + auto hcompute_demosaicked_1_stencil_3 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_function("hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_load("r_gb_stencil", "floor((demosaicked_1_s0_y/2))", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_3->add_load("r_r_stencil", "floor((demosaicked_1_s0_y/2))", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_3->add_store("demosaicked_1_stencil", "0", "demosaicked_1_s0_y", "((demosaicked_1_s0_x_x*2) + 1)"); + hcompute_demosaicked_1_stencil_3->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), demosaicked_1_s0_y, 1) = select(((demosaicked_1_s0_y % 2) == 0), g_r.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y/2)), g_gb.stencil((demosaicked_1_s0_x_x + 1), ((demosaicked_1_s0_y/2) + 1))) + auto hcompute_demosaicked_1_stencil_4 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_function("hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_load("g_gb_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_4->add_load("g_r_stencil", "floor((demosaicked_1_s0_y/2))", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_4->add_store("demosaicked_1_stencil", "1", "demosaicked_1_s0_y", "((demosaicked_1_s0_x_x*2) + 1)"); + hcompute_demosaicked_1_stencil_4->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), demosaicked_1_s0_y, 2) = select(((demosaicked_1_s0_y % 2) == 0), b_r.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2)), b_gb.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y/2))) + auto hcompute_demosaicked_1_stencil_5 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_function("hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_load("b_gb_stencil", "floor((demosaicked_1_s0_y/2))", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_5->add_load("b_r_stencil", "floor((demosaicked_1_s0_y/2))", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_5->add_store("demosaicked_1_stencil", "2", "demosaicked_1_s0_y", "((demosaicked_1_s0_x_x*2) + 1)"); + hcompute_demosaicked_1_stencil_5->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//consuming demosaicked$1.stencil +////producing corrected.stencil + auto corrected_s0_y = prg.add_loop("corrected_s0_y", 0, 184); + auto corrected_s0_x_x = corrected_s0_y->add_loop("corrected_s0_x_x", 0, 124); + +//store is: corrected.stencil((corrected_s0_x_x*2), corrected_s0_y, 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), corrected_s0_y, 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), corrected_s0_y, 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), corrected_s0_y, 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_function("hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "0", "corrected_s0_y", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "1", "corrected_s0_y", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "2", "corrected_s0_y", "(corrected_s0_x_x*2)"); + prg.buffer_port_widths["corrected_stencil"] = 16; + hcompute_corrected_stencil->add_store("corrected_stencil", "0", "corrected_s0_y", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), corrected_s0_y, 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_1 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_function("hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "0", "corrected_s0_y", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "1", "corrected_s0_y", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "2", "corrected_s0_y", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_1->add_store("corrected_stencil", "0", "corrected_s0_y", "((corrected_s0_x_x*2) + 1)"); + auto corrected_s0_y_1 = prg.add_loop("corrected_s0_y_1", 0, 184); + auto corrected_s0_x_x_1 = corrected_s0_y_1->add_loop("corrected_s0_x_x_1", 0, 124); + +//store is: corrected.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_1*2), corrected_s0_y_1, 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_2 = corrected_s0_x_x_1->add_op("op_hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_function("hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "0", "corrected_s0_y_1", "(corrected_s0_x_x_1*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "1", "corrected_s0_y_1", "(corrected_s0_x_x_1*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "2", "corrected_s0_y_1", "(corrected_s0_x_x_1*2)"); + hcompute_corrected_stencil_2->add_store("corrected_stencil", "1", "corrected_s0_y_1", "(corrected_s0_x_x_1*2)"); + +//store is: corrected.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_1*2) + 1), corrected_s0_y_1, 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_3 = corrected_s0_x_x_1->add_op("op_hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_function("hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "0", "corrected_s0_y_1", "((corrected_s0_x_x_1*2) + 1)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "1", "corrected_s0_y_1", "((corrected_s0_x_x_1*2) + 1)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "2", "corrected_s0_y_1", "((corrected_s0_x_x_1*2) + 1)"); + hcompute_corrected_stencil_3->add_store("corrected_stencil", "1", "corrected_s0_y_1", "((corrected_s0_x_x_1*2) + 1)"); + auto corrected_s0_y_2 = prg.add_loop("corrected_s0_y_2", 0, 184); + auto corrected_s0_x_x_2 = corrected_s0_y_2->add_loop("corrected_s0_x_x_2", 0, 124); + +//store is: corrected.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x_2*2), corrected_s0_y_2, 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_4 = corrected_s0_x_x_2->add_op("op_hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_function("hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "0", "corrected_s0_y_2", "(corrected_s0_x_x_2*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "1", "corrected_s0_y_2", "(corrected_s0_x_x_2*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "2", "corrected_s0_y_2", "(corrected_s0_x_x_2*2)"); + hcompute_corrected_stencil_4->add_store("corrected_stencil", "2", "corrected_s0_y_2", "(corrected_s0_x_x_2*2)"); + +//store is: corrected.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x_2*2) + 1), corrected_s0_y_2, 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_5 = corrected_s0_x_x_2->add_op("op_hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_function("hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "0", "corrected_s0_y_2", "((corrected_s0_x_x_2*2) + 1)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "1", "corrected_s0_y_2", "((corrected_s0_x_x_2*2) + 1)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "2", "corrected_s0_y_2", "((corrected_s0_x_x_2*2) + 1)"); + hcompute_corrected_stencil_5->add_store("corrected_stencil", "2", "corrected_s0_y_2", "((corrected_s0_x_x_2*2) + 1)"); + +//consuming corrected.stencil +////producing curvea0 + +//consuming curvea0 +////producing curved.stencil + auto curved_s0_y = prg.add_loop("curved_s0_y", 0, 184); + auto curved_s0_x_x = curved_s0_y->add_loop("curved_s0_x_x", 0, 124); + +//store is: curved.stencil((curved_s0_x_x*2), curved_s0_y, 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), curved_s0_y, 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil = curved_s0_x_x->add_op("op_hcompute_curved_stencil"); + hcompute_curved_stencil->add_function("hcompute_curved_stencil"); + hcompute_curved_stencil->add_load("corrected_stencil", "0", "curved_s0_y", "(curved_s0_x_x*2)"); + prg.buffer_port_widths["curved_stencil"] = 16; + hcompute_curved_stencil->add_store("curved_stencil", "0", "curved_s0_y", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil->index_variable_prefetch_cycle(1); + hcompute_curved_stencil->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), curved_s0_y, 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), curved_s0_y, 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_1 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_function("hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_load("corrected_stencil", "0", "curved_s0_y", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_1->add_store("curved_stencil", "0", "curved_s0_y", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_1->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_1->add_latency(1); + auto curved_s0_y_1 = prg.add_loop("curved_s0_y_1", 0, 184); + auto curved_s0_x_x_1 = curved_s0_y_1->add_loop("curved_s0_x_x_1", 0, 124); + +//store is: curved.stencil((curved_s0_x_x_1*2), curved_s0_y_1, 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x_1*2), curved_s0_y_1, 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_2 = curved_s0_x_x_1->add_op("op_hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_function("hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_load("corrected_stencil", "1", "curved_s0_y_1", "(curved_s0_x_x_1*2)"); + hcompute_curved_stencil_2->add_store("curved_stencil", "1", "curved_s0_y_1", "(curved_s0_x_x_1*2)"); + //hcompute_curved_stencil_2->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_2->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x_1*2) + 1), curved_s0_y_1, 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x_1*2) + 1), curved_s0_y_1, 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_3 = curved_s0_x_x_1->add_op("op_hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_function("hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_load("corrected_stencil", "1", "curved_s0_y_1", "((curved_s0_x_x_1*2) + 1)"); + hcompute_curved_stencil_3->add_store("curved_stencil", "1", "curved_s0_y_1", "((curved_s0_x_x_1*2) + 1)"); + //hcompute_curved_stencil_3->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_3->add_latency(1); + auto curved_s0_y_2 = prg.add_loop("curved_s0_y_2", 0, 184); + auto curved_s0_x_x_2 = curved_s0_y_2->add_loop("curved_s0_x_x_2", 0, 124); + +//store is: curved.stencil((curved_s0_x_x_2*2), curved_s0_y_2, 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x_2*2), curved_s0_y_2, 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_4 = curved_s0_x_x_2->add_op("op_hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_function("hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_load("corrected_stencil", "2", "curved_s0_y_2", "(curved_s0_x_x_2*2)"); + hcompute_curved_stencil_4->add_store("curved_stencil", "2", "curved_s0_y_2", "(curved_s0_x_x_2*2)"); + //hcompute_curved_stencil_4->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_4->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x_2*2) + 1), curved_s0_y_2, 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x_2*2) + 1), curved_s0_y_2, 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_5 = curved_s0_x_x_2->add_op("op_hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_function("hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_load("corrected_stencil", "2", "curved_s0_y_2", "((curved_s0_x_x_2*2) + 1)"); + hcompute_curved_stencil_5->add_store("curved_stencil", "2", "curved_s0_y_2", "((curved_s0_x_x_2*2) + 1)"); + //hcompute_curved_stencil_5->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_5->add_latency(1); + +//consuming curved.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 184); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi_xi", 0, 124); + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi) = curved.stencil((hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi, 0) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("curved_stencil", "0", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*2)"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*2)", "0"); + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi) = curved.stencil((hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi, 1) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("curved_stencil", "1", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*2)", "1"); + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi) = curved.stencil((hw_output_s0_x_xi_xi*2), hw_output_s0_y_yi, 2) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("curved_stencil", "2", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*2)", "2"); + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi, 0) + auto hcompute_hw_output_glb_stencil_3 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_function("hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_load("curved_stencil", "0", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_3->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi, 1) + auto hcompute_hw_output_glb_stencil_4 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_function("hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_load("curved_stencil", "1", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_4->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), hw_output_s0_y_yi, 2) + auto hcompute_hw_output_glb_stencil_5 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_function("hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_load("curved_stencil", "2", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_5->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*2) + 1)", "2"); + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi = prg.add_loop("hw_output_global_wrapper_s0_y_yi", 0, 184); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 124); + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_3 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_function("hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + hcompute_hw_output_global_wrapper_stencil_3->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_4 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_function("hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + hcompute_hw_output_global_wrapper_stencil_4->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_5 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_function("hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + hcompute_hw_output_global_wrapper_stencil_5->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + + return prg; +} + +prog camera_pipeline_extra_buf_trunc() { + prog prg; + prg.compute_unit_file = "camera_pipeline_extra_buf_compute.h"; + prg.name = "camera_pipeline_extra_buf"; + +// Stencil &hw_input_stencil = arg_2; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_4; + //prg.add_output("hw_output_global_wrapper_stencil"); + //prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + prg.add_output("demosaicked_1_stencil"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + //prg.add_output("b_gb_stencil"); + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 192); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x_x", 0, 256); + +//store is: hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_s0_x_x, hw_input_global_wrapper_s0_y) = hw_input.stencil((hw_input_global_wrapper_s0_x_x + -4), (hw_input_global_wrapper_s0_y + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -4)", "(hw_input_global_wrapper_s0_x_x + -4)"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x_x"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y", 0, 192); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 256); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing denoised$1.stencil + auto denoised_1_s0_y = prg.add_loop("denoised_1_s0_y", 0, 188); + auto denoised_1_s0_x_x = denoised_1_s0_y->add_loop("denoised_1_s0_x_x", 0, 252); + +//store is: denoised$1.stencil(denoised_1_s0_x_x, denoised_1_s0_y) = min(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), (denoised_1_s0_y + 2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), (denoised_1_s0_y + 4)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), denoised_1_s0_y), max(hw_input_global_wrapper_global_wrapper.stencil(denoised_1_s0_x_x, (denoised_1_s0_y + 2)), hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 4), (denoised_1_s0_y + 2)))))) + auto hcompute_denoised_1_stencil = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_function("hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 4)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "denoised_1_s0_y", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "denoised_1_s0_x_x"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "(denoised_1_s0_x_x + 4)"); + prg.buffer_port_widths["denoised_1_stencil"] = 16; + hcompute_denoised_1_stencil->add_store("denoised_1_stencil", "denoised_1_s0_y", "denoised_1_s0_x_x"); + +//consuming denoised$1.stencil +////producing b_b.stencil + auto b_b_s0_y = prg.add_loop("b_b_s0_y", 0, 93); + auto b_b_s0_x_x = b_b_s0_y->add_loop("b_b_s0_x_x", 0, 125); + +//store is: b_b.stencil(b_b_s0_x_x, b_b_s0_y) = denoised$1.stencil(((b_b_s0_x_x*2) + 2), ((b_b_s0_y*2) + 1)) + auto hcompute_b_b_stencil = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_function("hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_load("denoised_1_stencil", "((b_b_s0_y*2) + 1)", "((b_b_s0_x_x*2) + 2)"); + prg.buffer_port_widths["b_b_stencil"] = 16; + hcompute_b_b_stencil->add_store("b_b_stencil", "b_b_s0_y", "b_b_s0_x_x"); + +//consuming b_b.stencil +////producing g_gb.stencil + auto g_gb_s0_y = prg.add_loop("g_gb_s0_y", 0, 94); + auto g_gb_s0_x_x = g_gb_s0_y->add_loop("g_gb_s0_x_x", 0, 126); + +//store is: g_gb.stencil(g_gb_s0_x_x, g_gb_s0_y) = denoised$1.stencil(((g_gb_s0_x_x*2) + 1), ((g_gb_s0_y*2) + 1)) + auto hcompute_g_gb_stencil = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_function("hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_load("denoised_1_stencil", "((g_gb_s0_y*2) + 1)", "((g_gb_s0_x_x*2) + 1)"); + prg.buffer_port_widths["g_gb_stencil"] = 16; + hcompute_g_gb_stencil->add_store("g_gb_stencil", "g_gb_s0_y", "g_gb_s0_x_x"); + +//consuming g_gb.stencil +////producing g_gr.stencil + auto g_gr_s0_y = prg.add_loop("g_gr_s0_y", 0, 94); + auto g_gr_s0_x_x = g_gr_s0_y->add_loop("g_gr_s0_x_x", 0, 126); + +//store is: g_gr.stencil(g_gr_s0_x_x, g_gr_s0_y) = denoised$1.stencil((g_gr_s0_x_x*2), (g_gr_s0_y*2)) + auto hcompute_g_gr_stencil = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_function("hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_load("denoised_1_stencil", "(g_gr_s0_y*2)", "(g_gr_s0_x_x*2)"); + prg.buffer_port_widths["g_gr_stencil"] = 16; + hcompute_g_gr_stencil->add_store("g_gr_stencil", "g_gr_s0_y", "g_gr_s0_x_x"); + +//consuming g_gr.stencil +////producing g_b.stencil + auto g_b_s0_y = prg.add_loop("g_b_s0_y", 0, 93); + auto g_b_s0_x = g_b_s0_y->add_loop("g_b_s0_x", 0, 125); + +//store is: g_b.stencil(g_b_s0_x, g_b_s0_y) = select((absd(g_gb.stencil(g_b_s0_x, g_b_s0_y), g_gb.stencil((g_b_s0_x + 1), g_b_s0_y)) < absd(g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)), g_gr.stencil((g_b_s0_x + 1), g_b_s0_y))), (((g_gb.stencil((g_b_s0_x + 1), g_b_s0_y) + g_gb.stencil(g_b_s0_x, g_b_s0_y)) + (uint16)1)/(uint16)2), (((g_gr.stencil((g_b_s0_x + 1), g_b_s0_y) + g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1))) + (uint16)1)/(uint16)2)) + auto hcompute_g_b_stencil = g_b_s0_x->add_op("op_hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_function("hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "g_b_s0_x"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + prg.buffer_port_widths["g_b_stencil"] = 16; + hcompute_g_b_stencil->add_store("g_b_stencil", "g_b_s0_y", "g_b_s0_x"); + +//consuming g_b.stencil +////producing b_gb.stencil + auto b_gb_s0_y = prg.add_loop("b_gb_s0_y", 0, 92); + auto b_gb_s0_x = b_gb_s0_y->add_loop("b_gb_s0_x", 0, 124); + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + (((b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1))) + (uint16)1)/(uint16)2)) + auto hcompute_b_gb_stencil = b_gb_s0_x->add_op("op_hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_function("hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_gb_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + prg.buffer_port_widths["b_gb_stencil"] = 16; + hcompute_b_gb_stencil->add_store("b_gb_stencil", "b_gb_s0_y", "b_gb_s0_x"); + +//consuming b_gb.stencil +////producing b_gr.stencil + auto b_gr_s0_y = prg.add_loop("b_gr_s0_y", 0, 92); + auto b_gr_s0_x = b_gr_s0_y->add_loop("b_gr_s0_x", 0, 124); + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + (((b_b.stencil(b_gr_s0_x, b_gr_s0_y) + b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil(b_gr_s0_x, b_gr_s0_y) + g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1))) + (uint16)1)/(uint16)2)) + auto hcompute_b_gr_stencil = b_gr_s0_x->add_op("op_hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_function("hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_gr_stencil", "(b_gr_s0_y + 1)", "(b_gr_s0_x + 1)"); + prg.buffer_port_widths["b_gr_stencil"] = 16; + hcompute_b_gr_stencil->add_store("b_gr_stencil", "b_gr_s0_y", "b_gr_s0_x"); + +//consuming b_gr.stencil +////producing g_r.stencil + auto g_r_s0_y = prg.add_loop("g_r_s0_y", 0, 93); + auto g_r_s0_x = g_r_s0_y->add_loop("g_r_s0_x", 0, 125); + +//store is: g_r.stencil(g_r_s0_x, g_r_s0_y) = select((absd(g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)), g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1))) < absd(g_gb.stencil(g_r_s0_x, g_r_s0_y), g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)))), (((g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1)) + g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1))) + (uint16)1)/(uint16)2), (((g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)) + g_gb.stencil(g_r_s0_x, g_r_s0_y)) + (uint16)1)/(uint16)2)) + auto hcompute_g_r_stencil = g_r_s0_x->add_op("op_hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_function("hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "g_r_s0_y", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + prg.buffer_port_widths["g_r_stencil"] = 16; + hcompute_g_r_stencil->add_store("g_r_stencil", "g_r_s0_y", "g_r_s0_x"); + +//consuming g_r.stencil +////producing b_r.stencil + auto b_r_s0_y = prg.add_loop("b_r_s0_y", 0, 92); + auto b_r_s0_x = b_r_s0_y->add_loop("b_r_s0_x", 0, 124); + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + (((b_b.stencil((b_r_s0_x + 1), b_r_s0_y) + b_b.stencil(b_r_s0_x, (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil((b_r_s0_x + 1), b_r_s0_y) + g_b.stencil(b_r_s0_x, (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + (((b_b.stencil(b_r_s0_x, b_r_s0_y) + b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil(b_r_s0_x, b_r_s0_y) + g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1))) + (uint16)1)/(uint16)2))) + auto hcompute_b_r_stencil = b_r_s0_x->add_op("op_hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_function("hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_r_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + prg.buffer_port_widths["b_r_stencil"] = 16; + hcompute_b_r_stencil->add_store("b_r_stencil", "b_r_s0_y", "b_r_s0_x"); + +//consuming b_r.stencil +////producing r_r.stencil + auto r_r_s0_y = prg.add_loop("r_r_s0_y", 0, 93); + auto r_r_s0_x_x = r_r_s0_y->add_loop("r_r_s0_x_x", 0, 125); + +//store is: r_r.stencil(r_r_s0_x_x, r_r_s0_y) = denoised$1.stencil(((r_r_s0_x_x*2) + 1), ((r_r_s0_y*2) + 2)) + auto hcompute_r_r_stencil = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_function("hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_load("denoised_1_stencil", "((r_r_s0_y*2) + 2)", "((r_r_s0_x_x*2) + 1)"); + prg.buffer_port_widths["r_r_stencil"] = 16; + hcompute_r_r_stencil->add_store("r_r_stencil", "r_r_s0_y", "r_r_s0_x_x"); + +//consuming r_r.stencil +////producing r_b.stencil + auto r_b_s0_y = prg.add_loop("r_b_s0_y", 0, 92); + auto r_b_s0_x = r_b_s0_y->add_loop("r_b_s0_x", 0, 124); + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + (((r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)) + r_r.stencil((r_b_s0_x + 1), r_b_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)) + g_r.stencil((r_b_s0_x + 1), r_b_s0_y)) + (uint16)1)/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + (((r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)) + r_r.stencil(r_b_s0_x, r_b_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)) + g_r.stencil(r_b_s0_x, r_b_s0_y)) + (uint16)1)/(uint16)2))) + auto hcompute_r_b_stencil = r_b_s0_x->add_op("op_hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_function("hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_load("g_b_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + prg.buffer_port_widths["r_b_stencil"] = 16; + hcompute_r_b_stencil->add_store("r_b_stencil", "r_b_s0_y", "r_b_s0_x"); + +//consuming r_b.stencil +////producing r_gb.stencil + auto r_gb_s0_y = prg.add_loop("r_gb_s0_y", 0, 92); + auto r_gb_s0_x = r_gb_s0_y->add_loop("r_gb_s0_x", 0, 124); + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + (((r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y)) + (uint16)1)/(uint16)2)) + auto hcompute_r_gb_stencil = r_gb_s0_x->add_op("op_hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_function("hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_load("g_gb_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + prg.buffer_port_widths["r_gb_stencil"] = 16; + hcompute_r_gb_stencil->add_store("r_gb_stencil", "r_gb_s0_y", "r_gb_s0_x"); + +//consuming r_gb.stencil +////producing r_gr.stencil + auto r_gr_s0_y = prg.add_loop("r_gr_s0_y", 0, 92); + auto r_gr_s0_x = r_gr_s0_y->add_loop("r_gr_s0_x", 0, 124); + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + (((r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + r_r.stencil(r_gr_s0_x, r_gr_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil(r_gr_s0_x, r_gr_s0_y) + g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y)) + (uint16)1)/(uint16)2)) + auto hcompute_r_gr_stencil = r_gr_s0_x->add_op("op_hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_function("hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_load("g_gr_stencil", "(r_gr_s0_y + 1)", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + prg.buffer_port_widths["r_gr_stencil"] = 16; + hcompute_r_gr_stencil->add_store("r_gr_stencil", "r_gr_s0_y", "r_gr_s0_x"); + +//consuming r_gr.stencil +////producing demosaicked$1.stencil + auto demosaicked_1_s0_y = prg.add_loop("demosaicked_1_s0_y", 0, 184); + auto demosaicked_1_s0_x_x = demosaicked_1_s0_y->add_loop("demosaicked_1_s0_x_x", 0, 248); + +//ore is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 0) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), r_gr.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), r_r.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), r_b.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), r_gb.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)))) + auto hcompute_demosaicked_1_stencil = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_function("hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_load("r_b_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil->add_load("r_gb_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil->add_load("r_gr_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil->add_load("r_r_stencil", "floor((demosaicked_1_s0_y/2))", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + hcompute_demosaicked_1_stencil->add_store("demosaicked_1_stencil", "0", "demosaicked_1_s0_y", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 1) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), g_gr.stencil(((demosaicked_1_s0_x_x/2) + 1), ((demosaicked_1_s0_y/2) + 1)), g_r.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), g_b.stencil((demosaicked_1_s0_x_x/2), ((demosaicked_1_s0_y/2) + 1)), g_gb.stencil(((demosaicked_1_s0_x_x/2) + 1), ((demosaicked_1_s0_y/2) + 1)))) + auto hcompute_demosaicked_1_stencil_1 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_function("hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_load("g_b_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_1->add_load("g_gb_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_load("g_gr_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_load("g_r_stencil", "floor((demosaicked_1_s0_y/2))", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_store("demosaicked_1_stencil", "1", "demosaicked_1_s0_y", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_1->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_1->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 2) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), b_gr.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), b_r.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), b_b.stencil((demosaicked_1_s0_x_x/2), ((demosaicked_1_s0_y/2) + 1)), b_gb.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)))) + auto hcompute_demosaicked_1_stencil_2 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_function("hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_load("b_b_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_load("b_gb_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_load("b_gr_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_load("b_r_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_store("demosaicked_1_stencil", "2", "demosaicked_1_s0_y", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + + + return prg; +} + +prog camera_pipeline_extra_buf() { + prog prg; + prg.compute_unit_file = "camera_pipeline_extra_buf_compute.h"; + prg.name = "camera_pipeline_extra_buf"; + +// Stencil &hw_input_stencil = arg_2; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_4; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 192); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x_x", 0, 256); + +//store is: hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_s0_x_x, hw_input_global_wrapper_s0_y) = hw_input.stencil((hw_input_global_wrapper_s0_x_x + -4), (hw_input_global_wrapper_s0_y + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -4)", "(hw_input_global_wrapper_s0_x_x + -4)"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x_x"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y", 0, 192); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 256); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing denoised$1.stencil + auto denoised_1_s0_y = prg.add_loop("denoised_1_s0_y", 0, 188); + auto denoised_1_s0_x_x = denoised_1_s0_y->add_loop("denoised_1_s0_x_x", 0, 252); + +//store is: denoised$1.stencil(denoised_1_s0_x_x, denoised_1_s0_y) = min(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), (denoised_1_s0_y + 2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), (denoised_1_s0_y + 4)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 2), denoised_1_s0_y), max(hw_input_global_wrapper_global_wrapper.stencil(denoised_1_s0_x_x, (denoised_1_s0_y + 2)), hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x + 4), (denoised_1_s0_y + 2)))))) + auto hcompute_denoised_1_stencil = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_function("hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 4)", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "denoised_1_s0_y", "(denoised_1_s0_x_x + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "denoised_1_s0_x_x"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y + 2)", "(denoised_1_s0_x_x + 4)"); + prg.buffer_port_widths["denoised_1_stencil"] = 16; + hcompute_denoised_1_stencil->add_store("denoised_1_stencil", "denoised_1_s0_y", "denoised_1_s0_x_x"); + +//consuming denoised$1.stencil +////producing b_b.stencil + auto b_b_s0_y = prg.add_loop("b_b_s0_y", 0, 93); + auto b_b_s0_x_x = b_b_s0_y->add_loop("b_b_s0_x_x", 0, 125); + +//store is: b_b.stencil(b_b_s0_x_x, b_b_s0_y) = denoised$1.stencil(((b_b_s0_x_x*2) + 2), ((b_b_s0_y*2) + 1)) + auto hcompute_b_b_stencil = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_function("hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_load("denoised_1_stencil", "((b_b_s0_y*2) + 1)", "((b_b_s0_x_x*2) + 2)"); + prg.buffer_port_widths["b_b_stencil"] = 16; + hcompute_b_b_stencil->add_store("b_b_stencil", "b_b_s0_y", "b_b_s0_x_x"); + +//consuming b_b.stencil +////producing g_gb.stencil + auto g_gb_s0_y = prg.add_loop("g_gb_s0_y", 0, 94); + auto g_gb_s0_x_x = g_gb_s0_y->add_loop("g_gb_s0_x_x", 0, 126); + +//store is: g_gb.stencil(g_gb_s0_x_x, g_gb_s0_y) = denoised$1.stencil(((g_gb_s0_x_x*2) + 1), ((g_gb_s0_y*2) + 1)) + auto hcompute_g_gb_stencil = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_function("hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_load("denoised_1_stencil", "((g_gb_s0_y*2) + 1)", "((g_gb_s0_x_x*2) + 1)"); + prg.buffer_port_widths["g_gb_stencil"] = 16; + hcompute_g_gb_stencil->add_store("g_gb_stencil", "g_gb_s0_y", "g_gb_s0_x_x"); + +//consuming g_gb.stencil +////producing g_gr.stencil + auto g_gr_s0_y = prg.add_loop("g_gr_s0_y", 0, 94); + auto g_gr_s0_x_x = g_gr_s0_y->add_loop("g_gr_s0_x_x", 0, 126); + +//store is: g_gr.stencil(g_gr_s0_x_x, g_gr_s0_y) = denoised$1.stencil((g_gr_s0_x_x*2), (g_gr_s0_y*2)) + auto hcompute_g_gr_stencil = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_function("hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_load("denoised_1_stencil", "(g_gr_s0_y*2)", "(g_gr_s0_x_x*2)"); + prg.buffer_port_widths["g_gr_stencil"] = 16; + hcompute_g_gr_stencil->add_store("g_gr_stencil", "g_gr_s0_y", "g_gr_s0_x_x"); + +//consuming g_gr.stencil +////producing g_b.stencil + auto g_b_s0_y = prg.add_loop("g_b_s0_y", 0, 93); + auto g_b_s0_x = g_b_s0_y->add_loop("g_b_s0_x", 0, 125); + +//store is: g_b.stencil(g_b_s0_x, g_b_s0_y) = select((absd(g_gb.stencil(g_b_s0_x, g_b_s0_y), g_gb.stencil((g_b_s0_x + 1), g_b_s0_y)) < absd(g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)), g_gr.stencil((g_b_s0_x + 1), g_b_s0_y))), (((g_gb.stencil((g_b_s0_x + 1), g_b_s0_y) + g_gb.stencil(g_b_s0_x, g_b_s0_y)) + (uint16)1)/(uint16)2), (((g_gr.stencil((g_b_s0_x + 1), g_b_s0_y) + g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1))) + (uint16)1)/(uint16)2)) + auto hcompute_g_b_stencil = g_b_s0_x->add_op("op_hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_function("hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "g_b_s0_x"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "g_b_s0_y", "(g_b_s0_x + 1)"); + prg.buffer_port_widths["g_b_stencil"] = 16; + hcompute_g_b_stencil->add_store("g_b_stencil", "g_b_s0_y", "g_b_s0_x"); + +//consuming g_b.stencil +////producing b_gb.stencil + auto b_gb_s0_y = prg.add_loop("b_gb_s0_y", 0, 92); + auto b_gb_s0_x = b_gb_s0_y->add_loop("b_gb_s0_x", 0, 124); + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + (((b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1))) + (uint16)1)/(uint16)2)) + auto hcompute_b_gb_stencil = b_gb_s0_x->add_op("op_hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_function("hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_gb_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + prg.buffer_port_widths["b_gb_stencil"] = 16; + hcompute_b_gb_stencil->add_store("b_gb_stencil", "b_gb_s0_y", "b_gb_s0_x"); + +//consuming b_gb.stencil +////producing b_gr.stencil + auto b_gr_s0_y = prg.add_loop("b_gr_s0_y", 0, 92); + auto b_gr_s0_x = b_gr_s0_y->add_loop("b_gr_s0_x", 0, 124); + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + (((b_b.stencil(b_gr_s0_x, b_gr_s0_y) + b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil(b_gr_s0_x, b_gr_s0_y) + g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1))) + (uint16)1)/(uint16)2)) + auto hcompute_b_gr_stencil = b_gr_s0_x->add_op("op_hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_function("hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_gr_stencil", "(b_gr_s0_y + 1)", "(b_gr_s0_x + 1)"); + prg.buffer_port_widths["b_gr_stencil"] = 16; + hcompute_b_gr_stencil->add_store("b_gr_stencil", "b_gr_s0_y", "b_gr_s0_x"); + +//consuming b_gr.stencil +////producing g_r.stencil + auto g_r_s0_y = prg.add_loop("g_r_s0_y", 0, 93); + auto g_r_s0_x = g_r_s0_y->add_loop("g_r_s0_x", 0, 125); + +//store is: g_r.stencil(g_r_s0_x, g_r_s0_y) = select((absd(g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)), g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1))) < absd(g_gb.stencil(g_r_s0_x, g_r_s0_y), g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)))), (((g_gr.stencil(g_r_s0_x, (g_r_s0_y + 1)) + g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1))) + (uint16)1)/(uint16)2), (((g_gb.stencil(g_r_s0_x, (g_r_s0_y + 1)) + g_gb.stencil(g_r_s0_x, g_r_s0_y)) + (uint16)1)/(uint16)2)) + auto hcompute_g_r_stencil = g_r_s0_x->add_op("op_hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_function("hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "g_r_s0_y", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "g_r_s0_x"); + prg.buffer_port_widths["g_r_stencil"] = 16; + hcompute_g_r_stencil->add_store("g_r_stencil", "g_r_s0_y", "g_r_s0_x"); + +//consuming g_r.stencil +////producing b_r.stencil + auto b_r_s0_y = prg.add_loop("b_r_s0_y", 0, 92); + auto b_r_s0_x = b_r_s0_y->add_loop("b_r_s0_x", 0, 124); + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + (((b_b.stencil((b_r_s0_x + 1), b_r_s0_y) + b_b.stencil(b_r_s0_x, (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil((b_r_s0_x + 1), b_r_s0_y) + g_b.stencil(b_r_s0_x, (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + (((b_b.stencil(b_r_s0_x, b_r_s0_y) + b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1))) + (uint16)1)/(uint16)2)) - (((g_b.stencil(b_r_s0_x, b_r_s0_y) + g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1))) + (uint16)1)/(uint16)2))) + auto hcompute_b_r_stencil = b_r_s0_x->add_op("op_hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_function("hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_r_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + prg.buffer_port_widths["b_r_stencil"] = 16; + hcompute_b_r_stencil->add_store("b_r_stencil", "b_r_s0_y", "b_r_s0_x"); + +//consuming b_r.stencil +////producing r_r.stencil + auto r_r_s0_y = prg.add_loop("r_r_s0_y", 0, 93); + auto r_r_s0_x_x = r_r_s0_y->add_loop("r_r_s0_x_x", 0, 125); + +//store is: r_r.stencil(r_r_s0_x_x, r_r_s0_y) = denoised$1.stencil(((r_r_s0_x_x*2) + 1), ((r_r_s0_y*2) + 2)) + auto hcompute_r_r_stencil = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_function("hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_load("denoised_1_stencil", "((r_r_s0_y*2) + 2)", "((r_r_s0_x_x*2) + 1)"); + prg.buffer_port_widths["r_r_stencil"] = 16; + hcompute_r_r_stencil->add_store("r_r_stencil", "r_r_s0_y", "r_r_s0_x_x"); + +//consuming r_r.stencil +////producing r_b.stencil + auto r_b_s0_y = prg.add_loop("r_b_s0_y", 0, 92); + auto r_b_s0_x = r_b_s0_y->add_loop("r_b_s0_x", 0, 124); + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + (((r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)) + r_r.stencil((r_b_s0_x + 1), r_b_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)) + g_r.stencil((r_b_s0_x + 1), r_b_s0_y)) + (uint16)1)/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + (((r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)) + r_r.stencil(r_b_s0_x, r_b_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)) + g_r.stencil(r_b_s0_x, r_b_s0_y)) + (uint16)1)/(uint16)2))) + auto hcompute_r_b_stencil = r_b_s0_x->add_op("op_hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_function("hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_load("g_b_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + prg.buffer_port_widths["r_b_stencil"] = 16; + hcompute_r_b_stencil->add_store("r_b_stencil", "r_b_s0_y", "r_b_s0_x"); + +//consuming r_b.stencil +////producing r_gb.stencil + auto r_gb_s0_y = prg.add_loop("r_gb_s0_y", 0, 92); + auto r_gb_s0_x = r_gb_s0_y->add_loop("r_gb_s0_x", 0, 124); + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + (((r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y)) + (uint16)1)/(uint16)2)) + auto hcompute_r_gb_stencil = r_gb_s0_x->add_op("op_hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_function("hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_load("g_gb_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + prg.buffer_port_widths["r_gb_stencil"] = 16; + hcompute_r_gb_stencil->add_store("r_gb_stencil", "r_gb_s0_y", "r_gb_s0_x"); + +//consuming r_gb.stencil +////producing r_gr.stencil + auto r_gr_s0_y = prg.add_loop("r_gr_s0_y", 0, 92); + auto r_gr_s0_x = r_gr_s0_y->add_loop("r_gr_s0_x", 0, 124); + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + (((r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + r_r.stencil(r_gr_s0_x, r_gr_s0_y)) + (uint16)1)/(uint16)2)) - (((g_r.stencil(r_gr_s0_x, r_gr_s0_y) + g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y)) + (uint16)1)/(uint16)2)) + auto hcompute_r_gr_stencil = r_gr_s0_x->add_op("op_hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_function("hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_load("g_gr_stencil", "(r_gr_s0_y + 1)", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + prg.buffer_port_widths["r_gr_stencil"] = 16; + hcompute_r_gr_stencil->add_store("r_gr_stencil", "r_gr_s0_y", "r_gr_s0_x"); + +//consuming r_gr.stencil +////producing demosaicked$1.stencil + auto demosaicked_1_s0_y = prg.add_loop("demosaicked_1_s0_y", 0, 184); + auto demosaicked_1_s0_x_x = demosaicked_1_s0_y->add_loop("demosaicked_1_s0_x_x", 0, 248); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 0) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), r_gr.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), r_r.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), r_b.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), r_gb.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)))) + auto hcompute_demosaicked_1_stencil = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_function("hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_load("r_b_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil->add_load("r_gb_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil->add_load("r_gr_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil->add_load("r_r_stencil", "floor((demosaicked_1_s0_y/2))", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + hcompute_demosaicked_1_stencil->add_store("demosaicked_1_stencil", "0", "demosaicked_1_s0_y", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 1) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), g_gr.stencil(((demosaicked_1_s0_x_x/2) + 1), ((demosaicked_1_s0_y/2) + 1)), g_r.stencil(((demosaicked_1_s0_x_x/2) + 1), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), g_b.stencil((demosaicked_1_s0_x_x/2), ((demosaicked_1_s0_y/2) + 1)), g_gb.stencil(((demosaicked_1_s0_x_x/2) + 1), ((demosaicked_1_s0_y/2) + 1)))) + auto hcompute_demosaicked_1_stencil_1 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_function("hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_load("g_b_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_1->add_load("g_gb_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_load("g_gr_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_load("g_r_stencil", "floor((demosaicked_1_s0_y/2))", "(floor((demosaicked_1_s0_x_x/2)) + 1)"); + hcompute_demosaicked_1_stencil_1->add_store("demosaicked_1_stencil", "1", "demosaicked_1_s0_y", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_1->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_1->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//store is: demosaicked$1.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y, 2) = select(((demosaicked_1_s0_y % 2) == 0), select(((demosaicked_1_s0_x_x % 2) == 0), b_gr.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)), b_r.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2))), select(((demosaicked_1_s0_x_x % 2) == 0), b_b.stencil((demosaicked_1_s0_x_x/2), ((demosaicked_1_s0_y/2) + 1)), b_gb.stencil((demosaicked_1_s0_x_x/2), (demosaicked_1_s0_y/2)))) + auto hcompute_demosaicked_1_stencil_2 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_function("hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_load("b_b_stencil", "(floor((demosaicked_1_s0_y/2)) + 1)", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_load("b_gb_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_load("b_gr_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_load("b_r_stencil", "floor((demosaicked_1_s0_y/2))", "floor((demosaicked_1_s0_x_x/2))"); + hcompute_demosaicked_1_stencil_2->add_store("demosaicked_1_stencil", "2", "demosaicked_1_s0_y", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->compute_unit_needs_index_variable("demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->compute_unit_needs_index_variable("demosaicked_1_s0_y"); + +//consuming demosaicked$1.stencil +////producing corrected.stencil + auto corrected_s0_y = prg.add_loop("corrected_s0_y", 0, 184); + auto corrected_s0_x_x = corrected_s0_y->add_loop("corrected_s0_x_x", 0, 248); + +//store is: corrected.stencil(corrected_s0_x_x, corrected_s0_y, 0) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, corrected_s0_y, 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, corrected_s0_y, 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x, corrected_s0_y, 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_function("hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "0", "corrected_s0_y", "corrected_s0_x_x"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "1", "corrected_s0_y", "corrected_s0_x_x"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "2", "corrected_s0_y", "corrected_s0_x_x"); + prg.buffer_port_widths["corrected_stencil"] = 16; + hcompute_corrected_stencil->add_store("corrected_stencil", "0", "corrected_s0_y", "corrected_s0_x_x"); + auto corrected_s0_y_1 = prg.add_loop("corrected_s0_y_1", 0, 184); + auto corrected_s0_x_x_1 = corrected_s0_y_1->add_loop("corrected_s0_x_x_1", 0, 248); + +//store is: corrected.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 1) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_1, corrected_s0_y_1, 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_1 = corrected_s0_x_x_1->add_op("op_hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_function("hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "0", "corrected_s0_y_1", "corrected_s0_x_x_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "1", "corrected_s0_y_1", "corrected_s0_x_x_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "2", "corrected_s0_y_1", "corrected_s0_x_x_1"); + hcompute_corrected_stencil_1->add_store("corrected_stencil", "1", "corrected_s0_y_1", "corrected_s0_x_x_1"); + auto corrected_s0_y_2 = prg.add_loop("corrected_s0_y_2", 0, 184); + auto corrected_s0_x_x_2 = corrected_s0_y_2->add_loop("corrected_s0_x_x_2", 0, 248); + +//store is: corrected.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 2) = (((int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(corrected_s0_x_x_2, corrected_s0_y_2, 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_2 = corrected_s0_x_x_2->add_op("op_hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_function("hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "0", "corrected_s0_y_2", "corrected_s0_x_x_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "1", "corrected_s0_y_2", "corrected_s0_x_x_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "2", "corrected_s0_y_2", "corrected_s0_x_x_2"); + hcompute_corrected_stencil_2->add_store("corrected_stencil", "2", "corrected_s0_y_2", "corrected_s0_x_x_2"); + +//consuming corrected.stencil +////producing curvea0 + +//consuming curvea0 +////producing curved.stencil + auto curved_s0_y = prg.add_loop("curved_s0_y", 0, 184); + auto curved_s0_x_x = curved_s0_y->add_loop("curved_s0_x_x", 0, 248); + +//store is: curved.stencil(curved_s0_x_x, curved_s0_y, 0) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x, curved_s0_y, 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil = curved_s0_x_x->add_op("op_hcompute_curved_stencil"); + hcompute_curved_stencil->add_function("hcompute_curved_stencil"); + hcompute_curved_stencil->add_load("corrected_stencil", "0", "curved_s0_y", "curved_s0_x_x"); + prg.buffer_port_widths["curved_stencil"] = 16; + hcompute_curved_stencil->add_store("curved_stencil", "0", "curved_s0_y", "curved_s0_x_x"); + //hcompute_curved_stencil->index_variable_prefetch_cycle(1); + hcompute_curved_stencil->add_latency(1); + auto curved_s0_y_1 = prg.add_loop("curved_s0_y_1", 0, 184); + auto curved_s0_x_x_1 = curved_s0_y_1->add_loop("curved_s0_x_x_1", 0, 248); + +//store is: curved.stencil(curved_s0_x_x_1, curved_s0_y_1, 1) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x_1, curved_s0_y_1, 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_1 = curved_s0_x_x_1->add_op("op_hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_function("hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_load("corrected_stencil", "1", "curved_s0_y_1", "curved_s0_x_x_1"); + hcompute_curved_stencil_1->add_store("curved_stencil", "1", "curved_s0_y_1", "curved_s0_x_x_1"); + //hcompute_curved_stencil_1->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_1->add_latency(1); + auto curved_s0_y_2 = prg.add_loop("curved_s0_y_2", 0, 184); + auto curved_s0_x_x_2 = curved_s0_y_2->add_loop("curved_s0_x_x_2", 0, 248); + +//store is: curved.stencil(curved_s0_x_x_2, curved_s0_y_2, 2) = curvea0[int32(uint16(max(min(corrected.stencil(curved_s0_x_x_2, curved_s0_y_2, 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_2 = curved_s0_x_x_2->add_op("op_hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_function("hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_load("corrected_stencil", "2", "curved_s0_y_2", "curved_s0_x_x_2"); + hcompute_curved_stencil_2->add_store("curved_stencil", "2", "curved_s0_y_2", "curved_s0_x_x_2"); + //hcompute_curved_stencil_2->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_2->add_latency(1); + +//consuming curved.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 184); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi_xi", 0, 248); + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = curved.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi, 0) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("curved_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi", "0"); + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = curved.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi, 1) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("curved_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi", "1"); + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = curved.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi, 2) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("curved_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi", "2"); + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi = prg.add_loop("hw_output_global_wrapper_s0_y_yi", 0, 184); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 248); + +//store is: hw_output_global_wrapper.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + +//store is: hw_output_global_wrapper.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + +//store is: hw_output_global_wrapper.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + + return prg; +} + prog camera_pipeline_isscc() { prog prg; prg.compute_unit_file = "camera_pipeline_isscc_compute.h"; diff --git a/example_progs/camera_pipeline_2x2_memory.cpp b/example_progs/camera_pipeline_2x2_memory.cpp new file mode 100644 index 000000000..39419b327 --- /dev/null +++ b/example_progs/camera_pipeline_2x2_memory.cpp @@ -0,0 +1,1561 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog camera_pipeline_2x2() { + prog prg; + prg.compute_unit_file = "camera_pipeline_2x2_compute.h"; + prg.name = "camera_pipeline_2x2"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_1; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_s0_y_yio", 0, 100); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -4)"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_1 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_function("hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -3)", "((hw_input_global_wrapper_s0_x_x*2) + -4)"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_store("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil_2 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_function("hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -3)"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_store("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_s0_x_x*2) + 1)"); + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_3 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_function("hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -3)", "((hw_input_global_wrapper_s0_x_x*2) + -3)"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_store("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y_yio", 0, 100); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_1 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_load("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_global_wrapper_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_2 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_load("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_global_wrapper_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_3 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_load("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_store("hw_input_global_wrapper_global_wrapper_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing denoised$1.stencil + auto denoised_1_s0_y_yio = prg.add_loop("denoised_1_s0_y_yio", 0, 98); + auto denoised_1_s0_x_x = denoised_1_s0_y_yio->add_loop("denoised_1_s0_x_x", 0, 130); + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 2)))))) + auto hcompute_denoised_1_stencil = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_function("hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 4)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "(denoised_1_s0_x_x*2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 4)"); + prg.buffer_port_widths["denoised_1_stencil"] = 16; + hcompute_denoised_1_stencil->add_store("denoised_1_stencil", "(denoised_1_s0_y_yio*2)", "(denoised_1_s0_x_x*2)"); + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 3)))))) + auto hcompute_denoised_1_stencil_1 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_function("hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 4)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 5)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "(denoised_1_s0_x_x*2)"); + hcompute_denoised_1_stencil_1->add_store("denoised_1_stencil", "((denoised_1_s0_y_yio*2) + 1)", "(denoised_1_s0_x_x*2)"); + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 2)))))) + auto hcompute_denoised_1_stencil_2 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_2"); + hcompute_denoised_1_stencil_2->add_function("hcompute_denoised_1_stencil_2"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 4)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 1)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 5)"); + hcompute_denoised_1_stencil_2->add_store("denoised_1_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 1)"); + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 3)))))) + auto hcompute_denoised_1_stencil_3 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_3"); + hcompute_denoised_1_stencil_3->add_function("hcompute_denoised_1_stencil_3"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 5)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 1)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 5)"); + hcompute_denoised_1_stencil_3->add_store("denoised_1_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 1)"); + +//consuming denoised$1.stencil +////producing b_b.stencil + auto b_b_s0_y = prg.add_loop("b_b_s0_y", -1, 96); + auto b_b_s0_x = b_b_s0_y->add_loop("b_b_s0_x", 0, 129); + +//store is: b_b.stencil(b_b_s0_x, (b_b_s0_y + 1)) = denoised$1.stencil(((b_b_s0_x*2) + 2), ((b_b_s0_y*2) + 3)) + auto hcompute_b_b_stencil = b_b_s0_x->add_op("op_hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_function("hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_load("denoised_1_stencil", "((b_b_s0_y*2) + 3)", "((b_b_s0_x*2) + 2)"); + prg.buffer_port_widths["b_b_stencil"] = 16; + hcompute_b_b_stencil->add_store("b_b_stencil", "(b_b_s0_y + 1)", "b_b_s0_x"); + +//consuming b_b.stencil +////producing g_gb.stencil + auto g_gb_s0_y = prg.add_loop("g_gb_s0_y", -1, 97); + auto g_gb_s0_x = g_gb_s0_y->add_loop("g_gb_s0_x", -1, 129); + +//store is: g_gb.stencil((g_gb_s0_x + 1), (g_gb_s0_y + 1)) = denoised$1.stencil(((g_gb_s0_x*2) + 3), ((g_gb_s0_y*2) + 3)) + auto hcompute_g_gb_stencil = g_gb_s0_x->add_op("op_hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_function("hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_load("denoised_1_stencil", "((g_gb_s0_y*2) + 3)", "((g_gb_s0_x*2) + 3)"); + prg.buffer_port_widths["g_gb_stencil"] = 16; + hcompute_g_gb_stencil->add_store("g_gb_stencil", "(g_gb_s0_y + 1)", "(g_gb_s0_x + 1)"); + +//consuming g_gb.stencil +////producing g_gr.stencil + auto g_gr_s0_y = prg.add_loop("g_gr_s0_y", -1, 97); + auto g_gr_s0_x = g_gr_s0_y->add_loop("g_gr_s0_x", -1, 129); + +//store is: g_gr.stencil((g_gr_s0_x + 1), (g_gr_s0_y + 1)) = denoised$1.stencil(((g_gr_s0_x*2) + 2), ((g_gr_s0_y*2) + 2)) + auto hcompute_g_gr_stencil = g_gr_s0_x->add_op("op_hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_function("hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_load("denoised_1_stencil", "((g_gr_s0_y*2) + 2)", "((g_gr_s0_x*2) + 2)"); + prg.buffer_port_widths["g_gr_stencil"] = 16; + hcompute_g_gr_stencil->add_store("g_gr_stencil", "(g_gr_s0_y + 1)", "(g_gr_s0_x + 1)"); + +//consuming g_gr.stencil +////producing g_b.stencil + auto g_b_s0_y = prg.add_loop("g_b_s0_y", -1, 96); + auto g_b_s0_x = g_b_s0_y->add_loop("g_b_s0_x", 0, 129); + +//store is: g_b.stencil(g_b_s0_x, (g_b_s0_y + 1)) = select((absd(g_gb.stencil(g_b_s0_x, (g_b_s0_y + 1)), g_gb.stencil((g_b_s0_x + 1), (g_b_s0_y + 1))) < absd(g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 2)), g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))), ((g_gb.stencil(g_b_s0_x, (g_b_s0_y + 1)) + g_gb.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))/(uint16)2), ((g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 2)) + g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))/(uint16)2)) + auto hcompute_g_b_stencil = g_b_s0_x->add_op("op_hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_function("hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "(g_b_s0_y + 1)", "g_b_s0_x"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 2)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + prg.buffer_port_widths["g_b_stencil"] = 16; + hcompute_g_b_stencil->add_store("g_b_stencil", "(g_b_s0_y + 1)", "g_b_s0_x"); + +//consuming g_b.stencil +////producing b_gb.stencil + auto b_gb_s0_y = prg.add_loop("b_gb_s0_y", 0, 96); + auto b_gb_s0_x = b_gb_s0_y->add_loop("b_gb_s0_x", 0, 128); + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + ((b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) - ((g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_b_gb_stencil = b_gb_s0_x->add_op("op_hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_function("hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_gb_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + prg.buffer_port_widths["b_gb_stencil"] = 16; + hcompute_b_gb_stencil->add_store("b_gb_stencil", "b_gb_s0_y", "b_gb_s0_x"); + +//consuming b_gb.stencil +////producing b_gr.stencil + auto b_gr_s0_y = prg.add_loop("b_gr_s0_y", 0, 96); + auto b_gr_s0_x = b_gr_s0_y->add_loop("b_gr_s0_x", 0, 128); + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + ((b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + b_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) - ((g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + g_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) + auto hcompute_b_gr_stencil = b_gr_s0_x->add_op("op_hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_function("hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_gr_stencil", "(b_gr_s0_y + 1)", "(b_gr_s0_x + 1)"); + prg.buffer_port_widths["b_gr_stencil"] = 16; + hcompute_b_gr_stencil->add_store("b_gr_stencil", "b_gr_s0_y", "b_gr_s0_x"); + +//consuming b_gr.stencil +////producing g_r.stencil + auto g_r_s0_y = prg.add_loop("g_r_s0_y", 0, 97); + auto g_r_s0_x = g_r_s0_y->add_loop("g_r_s0_x", -1, 128); + +//store is: g_r.stencil((g_r_s0_x + 1), g_r_s0_y) = select((absd(g_gr.stencil((g_r_s0_x + 2), (g_r_s0_y + 1)), g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1))) < absd(g_gb.stencil((g_r_s0_x + 1), g_r_s0_y), g_gb.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))), ((g_gr.stencil((g_r_s0_x + 2), (g_r_s0_y + 1)) + g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))/(uint16)2), ((g_gb.stencil((g_r_s0_x + 1), g_r_s0_y) + g_gb.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))/(uint16)2)) + auto hcompute_g_r_stencil = g_r_s0_x->add_op("op_hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_function("hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "g_r_s0_y", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 2)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + prg.buffer_port_widths["g_r_stencil"] = 16; + hcompute_g_r_stencil->add_store("g_r_stencil", "g_r_s0_y", "(g_r_s0_x + 1)"); + +//consuming g_r.stencil +////producing b_r.stencil + auto b_r_s0_y = prg.add_loop("b_r_s0_y", 0, 96); + auto b_r_s0_x = b_r_s0_y->add_loop("b_r_s0_x", 0, 128); + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + b_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)) - ((g_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + g_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + b_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2)) - ((g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + g_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2))) + auto hcompute_b_r_stencil = b_r_s0_x->add_op("op_hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_function("hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_r_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + prg.buffer_port_widths["b_r_stencil"] = 16; + hcompute_b_r_stencil->add_store("b_r_stencil", "b_r_s0_y", "b_r_s0_x"); + +//consuming b_r.stencil +////producing r_r.stencil + auto r_r_s0_y = prg.add_loop("r_r_s0_y", 0, 97); + auto r_r_s0_x = r_r_s0_y->add_loop("r_r_s0_x", -1, 128); + +//store is: r_r.stencil((r_r_s0_x + 1), r_r_s0_y) = denoised$1.stencil(((r_r_s0_x*2) + 3), ((r_r_s0_y*2) + 2)) + auto hcompute_r_r_stencil = r_r_s0_x->add_op("op_hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_function("hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_load("denoised_1_stencil", "((r_r_s0_y*2) + 2)", "((r_r_s0_x*2) + 3)"); + prg.buffer_port_widths["r_r_stencil"] = 16; + hcompute_r_r_stencil->add_store("r_r_stencil", "r_r_s0_y", "(r_r_s0_x + 1)"); + +//consuming r_r.stencil +////producing r_b.stencil + auto r_b_s0_y = prg.add_loop("r_b_s0_y", 0, 96); + auto r_b_s0_x = r_b_s0_y->add_loop("r_b_s0_x", 0, 128); + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil((r_b_s0_x + 1), r_b_s0_y) + r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x + 1), r_b_s0_y) + g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil(r_b_s0_x, r_b_s0_y) + r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil(r_b_s0_x, r_b_s0_y) + g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2))) + auto hcompute_r_b_stencil = r_b_s0_x->add_op("op_hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_function("hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_load("g_b_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + prg.buffer_port_widths["r_b_stencil"] = 16; + hcompute_r_b_stencil->add_store("r_b_stencil", "r_b_s0_y", "r_b_s0_x"); + +//consuming r_b.stencil +////producing r_gb.stencil + auto r_gb_s0_y = prg.add_loop("r_gb_s0_y", 0, 96); + auto r_gb_s0_x = r_gb_s0_y->add_loop("r_gb_s0_x", 0, 128); + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + ((r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_r_gb_stencil = r_gb_s0_x->add_op("op_hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_function("hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_load("g_gb_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + prg.buffer_port_widths["r_gb_stencil"] = 16; + hcompute_r_gb_stencil->add_store("r_gb_stencil", "r_gb_s0_y", "r_gb_s0_x"); + +//consuming r_gb.stencil +////producing r_gr.stencil + auto r_gr_s0_y = prg.add_loop("r_gr_s0_y", 0, 96); + auto r_gr_s0_x = r_gr_s0_y->add_loop("r_gr_s0_x", 0, 128); + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + ((r_r.stencil(r_gr_s0_x, r_gr_s0_y) + r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y))/(uint16)2)) - ((g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + g_r.stencil(r_gr_s0_x, r_gr_s0_y))/(uint16)2)) + auto hcompute_r_gr_stencil = r_gr_s0_x->add_op("op_hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_function("hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_load("g_gr_stencil", "(r_gr_s0_y + 1)", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + prg.buffer_port_widths["r_gr_stencil"] = 16; + hcompute_r_gr_stencil->add_store("r_gr_stencil", "r_gr_s0_y", "r_gr_s0_x"); + +//consuming r_gr.stencil +////producing demosaicked$1.stencil + auto demosaicked_1_s0_y_yio = prg.add_loop("demosaicked_1_s0_y_yio", 0, 96); + auto demosaicked_1_s0_x_x = demosaicked_1_s0_y_yio->add_loop("demosaicked_1_s0_x_x", 0, 128); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 0) = r_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_function("hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_load("r_gr_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + hcompute_demosaicked_1_stencil->add_store("demosaicked_1_stencil", "0", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 1) = g_gr.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_1 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_function("hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_load("g_gr_stencil", "(demosaicked_1_s0_y_yio + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_1->add_store("demosaicked_1_stencil", "1", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 2) = b_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_2 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_function("hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_load("b_gr_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->add_store("demosaicked_1_stencil", "2", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_b.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_3 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_function("hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_load("r_b_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_3->add_store("demosaicked_1_stencil", "0", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_4 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_function("hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_load("g_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_4->add_store("demosaicked_1_stencil", "1", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_5 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_function("hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_load("b_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_5->add_store("demosaicked_1_stencil", "2", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 0) = r_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_6 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_6"); + hcompute_demosaicked_1_stencil_6->add_function("hcompute_demosaicked_1_stencil_6"); + hcompute_demosaicked_1_stencil_6->add_load("r_r_stencil", "demosaicked_1_s0_y_yio", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_6->add_store("demosaicked_1_stencil", "0", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 1) = g_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_7 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_7"); + hcompute_demosaicked_1_stencil_7->add_function("hcompute_demosaicked_1_stencil_7"); + hcompute_demosaicked_1_stencil_7->add_load("g_r_stencil", "demosaicked_1_s0_y_yio", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_7->add_store("demosaicked_1_stencil", "1", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 2) = b_r.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_8 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_8"); + hcompute_demosaicked_1_stencil_8->add_function("hcompute_demosaicked_1_stencil_8"); + hcompute_demosaicked_1_stencil_8->add_load("b_r_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_8->add_store("demosaicked_1_stencil", "2", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_9 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_9"); + hcompute_demosaicked_1_stencil_9->add_function("hcompute_demosaicked_1_stencil_9"); + hcompute_demosaicked_1_stencil_9->add_load("r_gb_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_9->add_store("demosaicked_1_stencil", "0", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_gb.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_10 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_10"); + hcompute_demosaicked_1_stencil_10->add_function("hcompute_demosaicked_1_stencil_10"); + hcompute_demosaicked_1_stencil_10->add_load("g_gb_stencil", "(demosaicked_1_s0_y_yio + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_10->add_store("demosaicked_1_stencil", "1", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_11 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_11"); + hcompute_demosaicked_1_stencil_11->add_function("hcompute_demosaicked_1_stencil_11"); + hcompute_demosaicked_1_stencil_11->add_load("b_gb_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_11->add_store("demosaicked_1_stencil", "2", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//consuming demosaicked$1.stencil +////producing corrected.stencil + auto corrected_s0_y_yio = prg.add_loop("corrected_s0_y_yio", 0, 96); + auto corrected_s0_x_x = corrected_s0_y_yio->add_loop("corrected_s0_x_x", 0, 128); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_function("hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + prg.buffer_port_widths["corrected_stencil"] = 16; + hcompute_corrected_stencil->add_store("corrected_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_1 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_function("hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_store("corrected_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_2 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_function("hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_store("corrected_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_3 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_function("hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_store("corrected_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_4 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_function("hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_store("corrected_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_5 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_function("hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_store("corrected_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_6 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_6"); + hcompute_corrected_stencil_6->add_function("hcompute_corrected_stencil_6"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_store("corrected_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_7 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_7"); + hcompute_corrected_stencil_7->add_function("hcompute_corrected_stencil_7"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_store("corrected_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_8 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_8"); + hcompute_corrected_stencil_8->add_function("hcompute_corrected_stencil_8"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_store("corrected_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_9 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_9"); + hcompute_corrected_stencil_9->add_function("hcompute_corrected_stencil_9"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_store("corrected_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_10 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_10"); + hcompute_corrected_stencil_10->add_function("hcompute_corrected_stencil_10"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_store("corrected_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_11 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_11"); + hcompute_corrected_stencil_11->add_function("hcompute_corrected_stencil_11"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_store("corrected_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//consuming corrected.stencil +////producing curvea0 + +//consuming curvea0 +////producing curved.stencil + auto curved_s0_y_yio = prg.add_loop("curved_s0_y_yio", 0, 96); + auto curved_s0_x_x = curved_s0_y_yio->add_loop("curved_s0_x_x", 0, 128); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil = curved_s0_x_x->add_op("op_hcompute_curved_stencil"); + hcompute_curved_stencil->add_function("hcompute_curved_stencil"); + hcompute_curved_stencil->add_load("corrected_stencil", "0", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + prg.buffer_port_widths["curved_stencil"] = 16; + hcompute_curved_stencil->add_store("curved_stencil", "0", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil->index_variable_prefetch_cycle(1); + hcompute_curved_stencil->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_1 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_function("hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_load("corrected_stencil", "1", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_1->add_store("curved_stencil", "1", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_1->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_1->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_2 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_function("hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_load("corrected_stencil", "2", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_2->add_store("curved_stencil", "2", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_2->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_2->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_3 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_function("hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_load("corrected_stencil", "0", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_3->add_store("curved_stencil", "0", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_3->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_3->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_4 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_function("hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_load("corrected_stencil", "1", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_4->add_store("curved_stencil", "1", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_4->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_4->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_5 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_function("hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_load("corrected_stencil", "2", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_5->add_store("curved_stencil", "2", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_5->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_5->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_6 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_6"); + hcompute_curved_stencil_6->add_function("hcompute_curved_stencil_6"); + hcompute_curved_stencil_6->add_load("corrected_stencil", "0", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_6->add_store("curved_stencil", "0", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_6->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_6->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_7 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_7"); + hcompute_curved_stencil_7->add_function("hcompute_curved_stencil_7"); + hcompute_curved_stencil_7->add_load("corrected_stencil", "1", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_7->add_store("curved_stencil", "1", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_7->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_7->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_8 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_8"); + hcompute_curved_stencil_8->add_function("hcompute_curved_stencil_8"); + hcompute_curved_stencil_8->add_load("corrected_stencil", "2", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_8->add_store("curved_stencil", "2", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_8->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_8->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_9 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_9"); + hcompute_curved_stencil_9->add_function("hcompute_curved_stencil_9"); + hcompute_curved_stencil_9->add_load("corrected_stencil", "0", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_9->add_store("curved_stencil", "0", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_9->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_9->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_10 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_10"); + hcompute_curved_stencil_10->add_function("hcompute_curved_stencil_10"); + hcompute_curved_stencil_10->add_load("corrected_stencil", "1", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_10->add_store("curved_stencil", "1", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_10->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_10->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_11 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_11"); + hcompute_curved_stencil_11->add_function("hcompute_curved_stencil_11"); + hcompute_curved_stencil_11->add_load("corrected_stencil", "2", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_11->add_store("curved_stencil", "2", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_11->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_11->add_latency(1); + +//consuming curved.stencil + auto hw_output_s0_y_yi_yio = prg.add_loop("hw_output_s0_y_yi_yio", 0, 96); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi_yio->add_loop("hw_output_s0_x_xi_xi", 0, 128); + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 0) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("curved_stencil", "0", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "0"); + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 1) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("curved_stencil", "1", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "1"); + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 2) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("curved_stencil", "2", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "2"); + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 0) + auto hcompute_hw_output_glb_stencil_3 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_function("hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_load("curved_stencil", "0", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_3->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "0"); + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 1) + auto hcompute_hw_output_glb_stencil_4 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_function("hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_load("curved_stencil", "1", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_4->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "1"); + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 2) + auto hcompute_hw_output_glb_stencil_5 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_function("hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_load("curved_stencil", "2", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_5->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "2"); + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 0) + auto hcompute_hw_output_glb_stencil_6 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_6"); + hcompute_hw_output_glb_stencil_6->add_function("hcompute_hw_output_glb_stencil_6"); + hcompute_hw_output_glb_stencil_6->add_load("curved_stencil", "0", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_6->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 1) + auto hcompute_hw_output_glb_stencil_7 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_7"); + hcompute_hw_output_glb_stencil_7->add_function("hcompute_hw_output_glb_stencil_7"); + hcompute_hw_output_glb_stencil_7->add_load("curved_stencil", "1", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_7->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 2) + auto hcompute_hw_output_glb_stencil_8 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_8"); + hcompute_hw_output_glb_stencil_8->add_function("hcompute_hw_output_glb_stencil_8"); + hcompute_hw_output_glb_stencil_8->add_load("curved_stencil", "2", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_8->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "2"); + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 0) + auto hcompute_hw_output_glb_stencil_9 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_9"); + hcompute_hw_output_glb_stencil_9->add_function("hcompute_hw_output_glb_stencil_9"); + hcompute_hw_output_glb_stencil_9->add_load("curved_stencil", "0", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_9->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 1) + auto hcompute_hw_output_glb_stencil_10 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_10"); + hcompute_hw_output_glb_stencil_10->add_function("hcompute_hw_output_glb_stencil_10"); + hcompute_hw_output_glb_stencil_10->add_load("curved_stencil", "1", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_10->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 2) + auto hcompute_hw_output_glb_stencil_11 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_11"); + hcompute_hw_output_glb_stencil_11->add_function("hcompute_hw_output_glb_stencil_11"); + hcompute_hw_output_glb_stencil_11->add_load("curved_stencil", "2", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_11->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "2"); + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi_yio = prg.add_loop("hw_output_global_wrapper_s0_y_yi_yio", 0, 96); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi_yio->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 128); + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_3 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_function("hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + hcompute_hw_output_global_wrapper_stencil_3->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_4 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_function("hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + hcompute_hw_output_global_wrapper_stencil_4->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_5 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_function("hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + hcompute_hw_output_global_wrapper_stencil_5->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_6 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_6"); + hcompute_hw_output_global_wrapper_stencil_6->add_function("hcompute_hw_output_global_wrapper_stencil_6"); + hcompute_hw_output_global_wrapper_stencil_6->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + hcompute_hw_output_global_wrapper_stencil_6->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_7 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_7"); + hcompute_hw_output_global_wrapper_stencil_7->add_function("hcompute_hw_output_global_wrapper_stencil_7"); + hcompute_hw_output_global_wrapper_stencil_7->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + hcompute_hw_output_global_wrapper_stencil_7->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_8 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_8"); + hcompute_hw_output_global_wrapper_stencil_8->add_function("hcompute_hw_output_global_wrapper_stencil_8"); + hcompute_hw_output_global_wrapper_stencil_8->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + hcompute_hw_output_global_wrapper_stencil_8->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_9 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_9"); + hcompute_hw_output_global_wrapper_stencil_9->add_function("hcompute_hw_output_global_wrapper_stencil_9"); + hcompute_hw_output_global_wrapper_stencil_9->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + hcompute_hw_output_global_wrapper_stencil_9->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_10 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_10"); + hcompute_hw_output_global_wrapper_stencil_10->add_function("hcompute_hw_output_global_wrapper_stencil_10"); + hcompute_hw_output_global_wrapper_stencil_10->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + hcompute_hw_output_global_wrapper_stencil_10->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_11 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_11"); + hcompute_hw_output_global_wrapper_stencil_11->add_function("hcompute_hw_output_global_wrapper_stencil_11"); + hcompute_hw_output_global_wrapper_stencil_11->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + hcompute_hw_output_global_wrapper_stencil_11->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + + return prg; +} + +prog camera_pipeline_2x2_unroll_partial() { + prog prg; + prg.compute_unit_file = "camera_pipeline_2x2_unroll_compute.h"; + prg.name = "camera_pipeline_2x2_unroll_partial"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_1; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_s0_y_yio", 0, 100); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -4)"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_1 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_function("hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -3)", "((hw_input_global_wrapper_s0_x_x*2) + -4)"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_store("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil_2 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_function("hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -3)"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_store("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_s0_x_x*2) + 1)"); + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_3 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_function("hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -3)", "((hw_input_global_wrapper_s0_x_x*2) + -3)"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_store("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y_yio", 0, 100); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_1 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_load("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_global_wrapper_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_2 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_load("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_global_wrapper_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_3 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_load("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_store("hw_input_global_wrapper_global_wrapper_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing denoised$1.stencil + auto denoised_1_s0_y_yio = prg.add_loop("denoised_1_s0_y_yio", 0, 98); + auto denoised_1_s0_x_x = denoised_1_s0_y_yio->add_loop("denoised_1_s0_x_x", 0, 130); + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 2)))))) + auto hcompute_denoised_1_stencil = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_function("hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 4)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "(denoised_1_s0_x_x*2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 4)"); + prg.buffer_port_widths["denoised_1_stencil"] = 16; + hcompute_denoised_1_stencil->add_store("denoised_1_stencil", "(denoised_1_s0_y_yio*2)", "(denoised_1_s0_x_x*2)"); + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 3)))))) + auto hcompute_denoised_1_stencil_1 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_function("hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 4)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 5)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "(denoised_1_s0_x_x*2)"); + hcompute_denoised_1_stencil_1->add_store("denoised_1_stencil", "((denoised_1_s0_y_yio*2) + 1)", "(denoised_1_s0_x_x*2)"); + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 2)))))) + auto hcompute_denoised_1_stencil_2 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_2"); + hcompute_denoised_1_stencil_2->add_function("hcompute_denoised_1_stencil_2"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 4)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 1)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 5)"); + hcompute_denoised_1_stencil_2->add_store("denoised_1_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 1)"); + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 3)))))) + auto hcompute_denoised_1_stencil_3 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_3"); + hcompute_denoised_1_stencil_3->add_function("hcompute_denoised_1_stencil_3"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 5)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 1)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 5)"); + hcompute_denoised_1_stencil_3->add_store("denoised_1_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 1)"); + +//consuming denoised$1.stencil +////producing b_b.stencil + auto b_b_s0_y_yio = prg.add_loop("b_b_s0_y_yio", 0, 49); + auto b_b_s0_x_x = b_b_s0_y_yio->add_loop("b_b_s0_x_x", 0, 65); + +//store is: b_b.stencil((b_b_s0_x_x*2), (b_b_s0_y_yio*2)) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), ((b_b_s0_y_yio*4) + 1)) + auto hcompute_b_b_stencil = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_function("hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 1)", "((b_b_s0_x_x*4) + 2)"); + prg.buffer_port_widths["b_b_stencil"] = 16; + hcompute_b_b_stencil->add_store("b_b_stencil", "(b_b_s0_y_yio*2)", "(b_b_s0_x_x*2)"); + +//store is: b_b.stencil((b_b_s0_x_x*2), ((b_b_s0_y_yio*2) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), ((b_b_s0_y_yio*4) + 3)) + auto hcompute_b_b_stencil_1 = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil_1"); + hcompute_b_b_stencil_1->add_function("hcompute_b_b_stencil_1"); + hcompute_b_b_stencil_1->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 3)", "((b_b_s0_x_x*4) + 2)"); + hcompute_b_b_stencil_1->add_store("b_b_stencil", "((b_b_s0_y_yio*2) + 1)", "(b_b_s0_x_x*2)"); + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), (b_b_s0_y_yio*2)) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), ((b_b_s0_y_yio*4) + 1)) + auto hcompute_b_b_stencil_2 = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil_2"); + hcompute_b_b_stencil_2->add_function("hcompute_b_b_stencil_2"); + hcompute_b_b_stencil_2->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 1)", "((b_b_s0_x_x*4) + 4)"); + hcompute_b_b_stencil_2->add_store("b_b_stencil", "(b_b_s0_y_yio*2)", "((b_b_s0_x_x*2) + 1)"); + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), ((b_b_s0_y_yio*2) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), ((b_b_s0_y_yio*4) + 3)) + auto hcompute_b_b_stencil_3 = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil_3"); + hcompute_b_b_stencil_3->add_function("hcompute_b_b_stencil_3"); + hcompute_b_b_stencil_3->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 3)", "((b_b_s0_x_x*4) + 4)"); + hcompute_b_b_stencil_3->add_store("b_b_stencil", "((b_b_s0_y_yio*2) + 1)", "((b_b_s0_x_x*2) + 1)"); + +//consuming b_b.stencil +////producing g_gb.stencil + auto g_gb_s0_y_yio = prg.add_loop("g_gb_s0_y_yio", 0, 49); + auto g_gb_s0_x_x = g_gb_s0_y_yio->add_loop("g_gb_s0_x_x", 0, 65); + +//store is: g_gb.stencil((g_gb_s0_x_x*2), (g_gb_s0_y_yio*2)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), ((g_gb_s0_y_yio*4) + 1)) + auto hcompute_g_gb_stencil = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_function("hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 1)", "((g_gb_s0_x_x*4) + 1)"); + prg.buffer_port_widths["g_gb_stencil"] = 16; + hcompute_g_gb_stencil->add_store("g_gb_stencil", "(g_gb_s0_y_yio*2)", "(g_gb_s0_x_x*2)"); + +//store is: g_gb.stencil((g_gb_s0_x_x*2), ((g_gb_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), ((g_gb_s0_y_yio*4) + 3)) + auto hcompute_g_gb_stencil_1 = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil_1"); + hcompute_g_gb_stencil_1->add_function("hcompute_g_gb_stencil_1"); + hcompute_g_gb_stencil_1->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 3)", "((g_gb_s0_x_x*4) + 1)"); + hcompute_g_gb_stencil_1->add_store("g_gb_stencil", "((g_gb_s0_y_yio*2) + 1)", "(g_gb_s0_x_x*2)"); + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), (g_gb_s0_y_yio*2)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), ((g_gb_s0_y_yio*4) + 1)) + auto hcompute_g_gb_stencil_2 = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil_2"); + hcompute_g_gb_stencil_2->add_function("hcompute_g_gb_stencil_2"); + hcompute_g_gb_stencil_2->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 1)", "((g_gb_s0_x_x*4) + 3)"); + hcompute_g_gb_stencil_2->add_store("g_gb_stencil", "(g_gb_s0_y_yio*2)", "((g_gb_s0_x_x*2) + 1)"); + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), ((g_gb_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), ((g_gb_s0_y_yio*4) + 3)) + auto hcompute_g_gb_stencil_3 = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil_3"); + hcompute_g_gb_stencil_3->add_function("hcompute_g_gb_stencil_3"); + hcompute_g_gb_stencil_3->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 3)", "((g_gb_s0_x_x*4) + 3)"); + hcompute_g_gb_stencil_3->add_store("g_gb_stencil", "((g_gb_s0_y_yio*2) + 1)", "((g_gb_s0_x_x*2) + 1)"); + +//consuming g_gb.stencil +////producing g_gr.stencil + auto g_gr_s0_y_yio = prg.add_loop("g_gr_s0_y_yio", 0, 49); + auto g_gr_s0_x_x = g_gr_s0_y_yio->add_loop("g_gr_s0_x_x", 0, 65); + +//store is: g_gr.stencil((g_gr_s0_x_x*2), (g_gr_s0_y_yio*2)) = denoised$1.stencil((g_gr_s0_x_x*4), (g_gr_s0_y_yio*4)) + auto hcompute_g_gr_stencil = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_function("hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_load("denoised_1_stencil", "(g_gr_s0_y_yio*4)", "(g_gr_s0_x_x*4)"); + prg.buffer_port_widths["g_gr_stencil"] = 16; + hcompute_g_gr_stencil->add_store("g_gr_stencil", "(g_gr_s0_y_yio*2)", "(g_gr_s0_x_x*2)"); + +//store is: g_gr.stencil((g_gr_s0_x_x*2), ((g_gr_s0_y_yio*2) + 1)) = denoised$1.stencil((g_gr_s0_x_x*4), ((g_gr_s0_y_yio*4) + 2)) + auto hcompute_g_gr_stencil_1 = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil_1"); + hcompute_g_gr_stencil_1->add_function("hcompute_g_gr_stencil_1"); + hcompute_g_gr_stencil_1->add_load("denoised_1_stencil", "((g_gr_s0_y_yio*4) + 2)", "(g_gr_s0_x_x*4)"); + hcompute_g_gr_stencil_1->add_store("g_gr_stencil", "((g_gr_s0_y_yio*2) + 1)", "(g_gr_s0_x_x*2)"); + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), (g_gr_s0_y_yio*2)) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), (g_gr_s0_y_yio*4)) + auto hcompute_g_gr_stencil_2 = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil_2"); + hcompute_g_gr_stencil_2->add_function("hcompute_g_gr_stencil_2"); + hcompute_g_gr_stencil_2->add_load("denoised_1_stencil", "(g_gr_s0_y_yio*4)", "((g_gr_s0_x_x*4) + 2)"); + hcompute_g_gr_stencil_2->add_store("g_gr_stencil", "(g_gr_s0_y_yio*2)", "((g_gr_s0_x_x*2) + 1)"); + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), ((g_gr_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), ((g_gr_s0_y_yio*4) + 2)) + auto hcompute_g_gr_stencil_3 = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil_3"); + hcompute_g_gr_stencil_3->add_function("hcompute_g_gr_stencil_3"); + hcompute_g_gr_stencil_3->add_load("denoised_1_stencil", "((g_gr_s0_y_yio*4) + 2)", "((g_gr_s0_x_x*4) + 2)"); + hcompute_g_gr_stencil_3->add_store("g_gr_stencil", "((g_gr_s0_y_yio*2) + 1)", "((g_gr_s0_x_x*2) + 1)"); + +//consuming g_gr.stencil +////producing g_b.stencil + auto g_b_s0_y = prg.add_loop("g_b_s0_y", -1, 96); + auto g_b_s0_x = g_b_s0_y->add_loop("g_b_s0_x", 0, 129); + +//store is: g_b.stencil(g_b_s0_x, (g_b_s0_y + 1)) = select((absd(g_gb.stencil(g_b_s0_x, (g_b_s0_y + 1)), g_gb.stencil((g_b_s0_x + 1), (g_b_s0_y + 1))) < absd(g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 2)), g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))), ((g_gb.stencil(g_b_s0_x, (g_b_s0_y + 1)) + g_gb.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))/(uint16)2), ((g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 2)) + g_gr.stencil((g_b_s0_x + 1), (g_b_s0_y + 1)))/(uint16)2)) + auto hcompute_g_b_stencil = g_b_s0_x->add_op("op_hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_function("hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "(g_b_s0_y + 1)", "g_b_s0_x"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 2)", "(g_b_s0_x + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y + 1)", "(g_b_s0_x + 1)"); + prg.buffer_port_widths["g_b_stencil"] = 16; + hcompute_g_b_stencil->add_store("g_b_stencil", "(g_b_s0_y + 1)", "g_b_s0_x"); + +//consuming g_b.stencil +////producing b_gb.stencil + auto b_gb_s0_y = prg.add_loop("b_gb_s0_y", 0, 96); + auto b_gb_s0_x = b_gb_s0_y->add_loop("b_gb_s0_x", 0, 128); + +//store is: b_gb.stencil(b_gb_s0_x, b_gb_s0_y) = ((g_gb.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)) + ((b_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + b_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) - ((g_b.stencil(b_gb_s0_x, (b_gb_s0_y + 1)) + g_b.stencil((b_gb_s0_x + 1), (b_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_b_gb_stencil = b_gb_s0_x->add_op("op_hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_function("hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "b_gb_s0_x"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + hcompute_b_gb_stencil->add_load("g_gb_stencil", "(b_gb_s0_y + 1)", "(b_gb_s0_x + 1)"); + prg.buffer_port_widths["b_gb_stencil"] = 16; + hcompute_b_gb_stencil->add_store("b_gb_stencil", "b_gb_s0_y", "b_gb_s0_x"); + +//consuming b_gb.stencil +////producing b_gr.stencil + auto b_gr_s0_y = prg.add_loop("b_gr_s0_y", 0, 96); + auto b_gr_s0_x = b_gr_s0_y->add_loop("b_gr_s0_x", 0, 128); + +//store is: b_gr.stencil(b_gr_s0_x, b_gr_s0_y) = ((g_gr.stencil((b_gr_s0_x + 1), (b_gr_s0_y + 1)) + ((b_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + b_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) - ((g_b.stencil(b_gr_s0_x, (b_gr_s0_y + 1)) + g_b.stencil(b_gr_s0_x, b_gr_s0_y))/(uint16)2)) + auto hcompute_b_gr_stencil = b_gr_s0_x->add_op("op_hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_function("hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "(b_gr_s0_y + 1)", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "b_gr_s0_y", "b_gr_s0_x"); + hcompute_b_gr_stencil->add_load("g_gr_stencil", "(b_gr_s0_y + 1)", "(b_gr_s0_x + 1)"); + prg.buffer_port_widths["b_gr_stencil"] = 16; + hcompute_b_gr_stencil->add_store("b_gr_stencil", "b_gr_s0_y", "b_gr_s0_x"); + +//consuming b_gr.stencil +////producing g_r.stencil + auto g_r_s0_y = prg.add_loop("g_r_s0_y", 0, 97); + auto g_r_s0_x = g_r_s0_y->add_loop("g_r_s0_x", -1, 128); + +//store is: g_r.stencil((g_r_s0_x + 1), g_r_s0_y) = select((absd(g_gr.stencil((g_r_s0_x + 2), (g_r_s0_y + 1)), g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1))) < absd(g_gb.stencil((g_r_s0_x + 1), g_r_s0_y), g_gb.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))), ((g_gr.stencil((g_r_s0_x + 2), (g_r_s0_y + 1)) + g_gr.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))/(uint16)2), ((g_gb.stencil((g_r_s0_x + 1), g_r_s0_y) + g_gb.stencil((g_r_s0_x + 1), (g_r_s0_y + 1)))/(uint16)2)) + auto hcompute_g_r_stencil = g_r_s0_x->add_op("op_hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_function("hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "g_r_s0_y", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 2)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "(g_r_s0_y + 1)", "(g_r_s0_x + 1)"); + prg.buffer_port_widths["g_r_stencil"] = 16; + hcompute_g_r_stencil->add_store("g_r_stencil", "g_r_s0_y", "(g_r_s0_x + 1)"); + +//consuming g_r.stencil +////producing b_r.stencil + auto b_r_s0_y = prg.add_loop("b_r_s0_y", 0, 96); + auto b_r_s0_x = b_r_s0_y->add_loop("b_r_s0_x", 0, 128); + +//store is: b_r.stencil(b_r_s0_x, b_r_s0_y) = select((absd(b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)), b_b.stencil((b_r_s0_x + 1), b_r_s0_y)) < absd(b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)), b_b.stencil(b_r_s0_x, b_r_s0_y))), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + b_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)) - ((g_b.stencil(b_r_s0_x, (b_r_s0_y + 1)) + g_b.stencil((b_r_s0_x + 1), b_r_s0_y))/(uint16)2)), ((g_r.stencil((b_r_s0_x + 1), b_r_s0_y) + ((b_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + b_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2)) - ((g_b.stencil((b_r_s0_x + 1), (b_r_s0_y + 1)) + g_b.stencil(b_r_s0_x, b_r_s0_y))/(uint16)2))) + auto hcompute_b_r_stencil = b_r_s0_x->add_op("op_hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_function("hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y + 1)", "(b_r_s0_x + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "b_r_s0_y", "b_r_s0_x"); + hcompute_b_r_stencil->add_load("g_r_stencil", "b_r_s0_y", "(b_r_s0_x + 1)"); + prg.buffer_port_widths["b_r_stencil"] = 16; + hcompute_b_r_stencil->add_store("b_r_stencil", "b_r_s0_y", "b_r_s0_x"); + +//consuming b_r.stencil +////producing r_r.stencil + auto r_r_s0_y_yio = prg.add_loop("r_r_s0_y_yio", 0, 49); + auto r_r_s0_x_x = r_r_s0_y_yio->add_loop("r_r_s0_x_x", 0, 65); + +//store is: r_r.stencil((r_r_s0_x_x*2), (r_r_s0_y_yio*2)) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y_yio*4) + 2)) + auto hcompute_r_r_stencil = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_function("hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 2)", "((r_r_s0_x_x*4) + 1)"); + prg.buffer_port_widths["r_r_stencil"] = 16; + hcompute_r_r_stencil->add_store("r_r_stencil", "(r_r_s0_y_yio*2)", "(r_r_s0_x_x*2)"); + +//store is: r_r.stencil((r_r_s0_x_x*2), ((r_r_s0_y_yio*2) + 1)) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y_yio*4) + 4)) + auto hcompute_r_r_stencil_1 = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil_1"); + hcompute_r_r_stencil_1->add_function("hcompute_r_r_stencil_1"); + hcompute_r_r_stencil_1->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 4)", "((r_r_s0_x_x*4) + 1)"); + hcompute_r_r_stencil_1->add_store("r_r_stencil", "((r_r_s0_y_yio*2) + 1)", "(r_r_s0_x_x*2)"); + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), (r_r_s0_y_yio*2)) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y_yio*4) + 2)) + auto hcompute_r_r_stencil_2 = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil_2"); + hcompute_r_r_stencil_2->add_function("hcompute_r_r_stencil_2"); + hcompute_r_r_stencil_2->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 2)", "((r_r_s0_x_x*4) + 3)"); + hcompute_r_r_stencil_2->add_store("r_r_stencil", "(r_r_s0_y_yio*2)", "((r_r_s0_x_x*2) + 1)"); + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), ((r_r_s0_y_yio*2) + 1)) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y_yio*4) + 4)) + auto hcompute_r_r_stencil_3 = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil_3"); + hcompute_r_r_stencil_3->add_function("hcompute_r_r_stencil_3"); + hcompute_r_r_stencil_3->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 4)", "((r_r_s0_x_x*4) + 3)"); + hcompute_r_r_stencil_3->add_store("r_r_stencil", "((r_r_s0_y_yio*2) + 1)", "((r_r_s0_x_x*2) + 1)"); + +//consuming r_r.stencil +////producing r_b.stencil + auto r_b_s0_y = prg.add_loop("r_b_s0_y", 0, 96); + auto r_b_s0_x = r_b_s0_y->add_loop("r_b_s0_x", 0, 128); + +//store is: r_b.stencil(r_b_s0_x, r_b_s0_y) = select((absd(r_r.stencil((r_b_s0_x + 1), r_b_s0_y), r_r.stencil(r_b_s0_x, (r_b_s0_y + 1))) < absd(r_r.stencil(r_b_s0_x, r_b_s0_y), r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil((r_b_s0_x + 1), r_b_s0_y) + r_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x + 1), r_b_s0_y) + g_r.stencil(r_b_s0_x, (r_b_s0_y + 1)))/(uint16)2)), ((g_b.stencil(r_b_s0_x, (r_b_s0_y + 1)) + ((r_r.stencil(r_b_s0_x, r_b_s0_y) + r_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2)) - ((g_r.stencil(r_b_s0_x, r_b_s0_y) + g_r.stencil((r_b_s0_x + 1), (r_b_s0_y + 1)))/(uint16)2))) + auto hcompute_r_b_stencil = r_b_s0_x->add_op("op_hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_function("hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_load("g_b_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "(r_b_s0_x + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "r_b_s0_y", "r_b_s0_x"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y + 1)", "(r_b_s0_x + 1)"); + prg.buffer_port_widths["r_b_stencil"] = 16; + hcompute_r_b_stencil->add_store("r_b_stencil", "r_b_s0_y", "r_b_s0_x"); + +//consuming r_b.stencil +////producing r_gb.stencil + auto r_gb_s0_y = prg.add_loop("r_gb_s0_y", 0, 96); + auto r_gb_s0_x = r_gb_s0_y->add_loop("r_gb_s0_x", 0, 128); + +//store is: r_gb.stencil(r_gb_s0_x, r_gb_s0_y) = ((g_gb.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)) + ((r_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + r_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) - ((g_r.stencil((r_gb_s0_x + 1), r_gb_s0_y) + g_r.stencil((r_gb_s0_x + 1), (r_gb_s0_y + 1)))/(uint16)2)) + auto hcompute_r_gb_stencil = r_gb_s0_x->add_op("op_hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_function("hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_load("g_gb_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "r_gb_s0_y", "(r_gb_s0_x + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "(r_gb_s0_y + 1)", "(r_gb_s0_x + 1)"); + prg.buffer_port_widths["r_gb_stencil"] = 16; + hcompute_r_gb_stencil->add_store("r_gb_stencil", "r_gb_s0_y", "r_gb_s0_x"); + +//consuming r_gb.stencil +////producing r_gr.stencil + auto r_gr_s0_y = prg.add_loop("r_gr_s0_y", 0, 96); + auto r_gr_s0_x = r_gr_s0_y->add_loop("r_gr_s0_x", 0, 128); + +//store is: r_gr.stencil(r_gr_s0_x, r_gr_s0_y) = ((g_gr.stencil((r_gr_s0_x + 1), (r_gr_s0_y + 1)) + ((r_r.stencil(r_gr_s0_x, r_gr_s0_y) + r_r.stencil((r_gr_s0_x + 1), r_gr_s0_y))/(uint16)2)) - ((g_r.stencil((r_gr_s0_x + 1), r_gr_s0_y) + g_r.stencil(r_gr_s0_x, r_gr_s0_y))/(uint16)2)) + auto hcompute_r_gr_stencil = r_gr_s0_x->add_op("op_hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_function("hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_load("g_gr_stencil", "(r_gr_s0_y + 1)", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "r_gr_s0_x"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "r_gr_s0_y", "(r_gr_s0_x + 1)"); + prg.buffer_port_widths["r_gr_stencil"] = 16; + hcompute_r_gr_stencil->add_store("r_gr_stencil", "r_gr_s0_y", "r_gr_s0_x"); + +//consuming r_gr.stencil +////producing demosaicked$1.stencil + auto demosaicked_1_s0_y_yio = prg.add_loop("demosaicked_1_s0_y_yio", 0, 96); + auto demosaicked_1_s0_x_x = demosaicked_1_s0_y_yio->add_loop("demosaicked_1_s0_x_x", 0, 128); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 0) = r_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_function("hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_load("r_gr_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + hcompute_demosaicked_1_stencil->add_store("demosaicked_1_stencil", "0", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 1) = g_gr.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_1 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_function("hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_load("g_gr_stencil", "(demosaicked_1_s0_y_yio + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_1->add_store("demosaicked_1_stencil", "1", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 2) = b_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_2 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_function("hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_load("b_gr_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->add_store("demosaicked_1_stencil", "2", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_b.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_3 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_function("hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_load("r_b_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_3->add_store("demosaicked_1_stencil", "0", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_4 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_function("hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_load("g_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_4->add_store("demosaicked_1_stencil", "1", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_5 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_function("hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_load("b_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_5->add_store("demosaicked_1_stencil", "2", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 0) = r_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_6 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_6"); + hcompute_demosaicked_1_stencil_6->add_function("hcompute_demosaicked_1_stencil_6"); + hcompute_demosaicked_1_stencil_6->add_load("r_r_stencil", "demosaicked_1_s0_y_yio", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_6->add_store("demosaicked_1_stencil", "0", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 1) = g_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_7 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_7"); + hcompute_demosaicked_1_stencil_7->add_function("hcompute_demosaicked_1_stencil_7"); + hcompute_demosaicked_1_stencil_7->add_load("g_r_stencil", "demosaicked_1_s0_y_yio", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_7->add_store("demosaicked_1_stencil", "1", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 2) = b_r.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_8 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_8"); + hcompute_demosaicked_1_stencil_8->add_function("hcompute_demosaicked_1_stencil_8"); + hcompute_demosaicked_1_stencil_8->add_load("b_r_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_8->add_store("demosaicked_1_stencil", "2", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_9 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_9"); + hcompute_demosaicked_1_stencil_9->add_function("hcompute_demosaicked_1_stencil_9"); + hcompute_demosaicked_1_stencil_9->add_load("r_gb_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_9->add_store("demosaicked_1_stencil", "0", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_gb.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_10 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_10"); + hcompute_demosaicked_1_stencil_10->add_function("hcompute_demosaicked_1_stencil_10"); + hcompute_demosaicked_1_stencil_10->add_load("g_gb_stencil", "(demosaicked_1_s0_y_yio + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_10->add_store("demosaicked_1_stencil", "1", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_11 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_11"); + hcompute_demosaicked_1_stencil_11->add_function("hcompute_demosaicked_1_stencil_11"); + hcompute_demosaicked_1_stencil_11->add_load("b_gb_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_11->add_store("demosaicked_1_stencil", "2", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//consuming demosaicked$1.stencil +////producing corrected.stencil + auto corrected_s0_y_yio = prg.add_loop("corrected_s0_y_yio", 0, 96); + auto corrected_s0_x_x = corrected_s0_y_yio->add_loop("corrected_s0_x_x", 0, 128); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_function("hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + prg.buffer_port_widths["corrected_stencil"] = 16; + hcompute_corrected_stencil->add_store("corrected_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_1 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_function("hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_store("corrected_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_2 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_function("hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_store("corrected_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_3 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_function("hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_store("corrected_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_4 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_function("hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_store("corrected_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_5 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_function("hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_store("corrected_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_6 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_6"); + hcompute_corrected_stencil_6->add_function("hcompute_corrected_stencil_6"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_store("corrected_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_7 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_7"); + hcompute_corrected_stencil_7->add_function("hcompute_corrected_stencil_7"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_store("corrected_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_8 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_8"); + hcompute_corrected_stencil_8->add_function("hcompute_corrected_stencil_8"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_store("corrected_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_9 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_9"); + hcompute_corrected_stencil_9->add_function("hcompute_corrected_stencil_9"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_store("corrected_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_10 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_10"); + hcompute_corrected_stencil_10->add_function("hcompute_corrected_stencil_10"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_store("corrected_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_11 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_11"); + hcompute_corrected_stencil_11->add_function("hcompute_corrected_stencil_11"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_store("corrected_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//consuming corrected.stencil +////producing curvea0 + +//consuming curvea0 +////producing curved.stencil + auto curved_s0_y_yio = prg.add_loop("curved_s0_y_yio", 0, 96); + auto curved_s0_x_x = curved_s0_y_yio->add_loop("curved_s0_x_x", 0, 128); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil = curved_s0_x_x->add_op("op_hcompute_curved_stencil"); + hcompute_curved_stencil->add_function("hcompute_curved_stencil"); + hcompute_curved_stencil->add_load("corrected_stencil", "0", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + prg.buffer_port_widths["curved_stencil"] = 16; + hcompute_curved_stencil->add_store("curved_stencil", "0", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil->index_variable_prefetch_cycle(1); + hcompute_curved_stencil->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_1 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_function("hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_load("corrected_stencil", "1", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_1->add_store("curved_stencil", "1", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_1->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_1->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_2 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_function("hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_load("corrected_stencil", "2", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_2->add_store("curved_stencil", "2", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_2->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_2->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_3 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_function("hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_load("corrected_stencil", "0", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_3->add_store("curved_stencil", "0", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_3->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_3->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_4 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_function("hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_load("corrected_stencil", "1", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_4->add_store("curved_stencil", "1", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_4->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_4->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_5 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_function("hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_load("corrected_stencil", "2", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_5->add_store("curved_stencil", "2", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_5->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_5->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_6 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_6"); + hcompute_curved_stencil_6->add_function("hcompute_curved_stencil_6"); + hcompute_curved_stencil_6->add_load("corrected_stencil", "0", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_6->add_store("curved_stencil", "0", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_6->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_6->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_7 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_7"); + hcompute_curved_stencil_7->add_function("hcompute_curved_stencil_7"); + hcompute_curved_stencil_7->add_load("corrected_stencil", "1", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_7->add_store("curved_stencil", "1", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_7->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_7->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_8 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_8"); + hcompute_curved_stencil_8->add_function("hcompute_curved_stencil_8"); + hcompute_curved_stencil_8->add_load("corrected_stencil", "2", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_8->add_store("curved_stencil", "2", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_8->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_8->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_9 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_9"); + hcompute_curved_stencil_9->add_function("hcompute_curved_stencil_9"); + hcompute_curved_stencil_9->add_load("corrected_stencil", "0", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_9->add_store("curved_stencil", "0", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_9->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_9->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_10 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_10"); + hcompute_curved_stencil_10->add_function("hcompute_curved_stencil_10"); + hcompute_curved_stencil_10->add_load("corrected_stencil", "1", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_10->add_store("curved_stencil", "1", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_10->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_10->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_11 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_11"); + hcompute_curved_stencil_11->add_function("hcompute_curved_stencil_11"); + hcompute_curved_stencil_11->add_load("corrected_stencil", "2", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_11->add_store("curved_stencil", "2", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_11->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_11->add_latency(1); + +//consuming curved.stencil + auto hw_output_s0_y_yi_yio = prg.add_loop("hw_output_s0_y_yi_yio", 0, 96); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi_yio->add_loop("hw_output_s0_x_xi_xi", 0, 128); + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 0) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("curved_stencil", "0", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "0"); + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 1) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("curved_stencil", "1", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "1"); + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 2) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("curved_stencil", "2", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "2"); + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 0) + auto hcompute_hw_output_glb_stencil_3 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_function("hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_load("curved_stencil", "0", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_3->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "0"); + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 1) + auto hcompute_hw_output_glb_stencil_4 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_function("hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_load("curved_stencil", "1", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_4->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "1"); + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 2) + auto hcompute_hw_output_glb_stencil_5 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_function("hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_load("curved_stencil", "2", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_5->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "2"); + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 0) + auto hcompute_hw_output_glb_stencil_6 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_6"); + hcompute_hw_output_glb_stencil_6->add_function("hcompute_hw_output_glb_stencil_6"); + hcompute_hw_output_glb_stencil_6->add_load("curved_stencil", "0", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_6->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 1) + auto hcompute_hw_output_glb_stencil_7 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_7"); + hcompute_hw_output_glb_stencil_7->add_function("hcompute_hw_output_glb_stencil_7"); + hcompute_hw_output_glb_stencil_7->add_load("curved_stencil", "1", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_7->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 2) + auto hcompute_hw_output_glb_stencil_8 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_8"); + hcompute_hw_output_glb_stencil_8->add_function("hcompute_hw_output_glb_stencil_8"); + hcompute_hw_output_glb_stencil_8->add_load("curved_stencil", "2", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_8->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "2"); + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 0) + auto hcompute_hw_output_glb_stencil_9 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_9"); + hcompute_hw_output_glb_stencil_9->add_function("hcompute_hw_output_glb_stencil_9"); + hcompute_hw_output_glb_stencil_9->add_load("curved_stencil", "0", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_9->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 1) + auto hcompute_hw_output_glb_stencil_10 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_10"); + hcompute_hw_output_glb_stencil_10->add_function("hcompute_hw_output_glb_stencil_10"); + hcompute_hw_output_glb_stencil_10->add_load("curved_stencil", "1", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_10->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 2) + auto hcompute_hw_output_glb_stencil_11 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_11"); + hcompute_hw_output_glb_stencil_11->add_function("hcompute_hw_output_glb_stencil_11"); + hcompute_hw_output_glb_stencil_11->add_load("curved_stencil", "2", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_11->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "2"); + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi_yio = prg.add_loop("hw_output_global_wrapper_s0_y_yi_yio", 0, 96); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi_yio->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 128); + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_3 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_function("hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + hcompute_hw_output_global_wrapper_stencil_3->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_4 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_function("hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + hcompute_hw_output_global_wrapper_stencil_4->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_5 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_function("hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + hcompute_hw_output_global_wrapper_stencil_5->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_6 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_6"); + hcompute_hw_output_global_wrapper_stencil_6->add_function("hcompute_hw_output_global_wrapper_stencil_6"); + hcompute_hw_output_global_wrapper_stencil_6->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + hcompute_hw_output_global_wrapper_stencil_6->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_7 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_7"); + hcompute_hw_output_global_wrapper_stencil_7->add_function("hcompute_hw_output_global_wrapper_stencil_7"); + hcompute_hw_output_global_wrapper_stencil_7->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + hcompute_hw_output_global_wrapper_stencil_7->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_8 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_8"); + hcompute_hw_output_global_wrapper_stencil_8->add_function("hcompute_hw_output_global_wrapper_stencil_8"); + hcompute_hw_output_global_wrapper_stencil_8->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + hcompute_hw_output_global_wrapper_stencil_8->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_9 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_9"); + hcompute_hw_output_global_wrapper_stencil_9->add_function("hcompute_hw_output_global_wrapper_stencil_9"); + hcompute_hw_output_global_wrapper_stencil_9->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + hcompute_hw_output_global_wrapper_stencil_9->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_10 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_10"); + hcompute_hw_output_global_wrapper_stencil_10->add_function("hcompute_hw_output_global_wrapper_stencil_10"); + hcompute_hw_output_global_wrapper_stencil_10->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + hcompute_hw_output_global_wrapper_stencil_10->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_11 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_11"); + hcompute_hw_output_global_wrapper_stencil_11->add_function("hcompute_hw_output_global_wrapper_stencil_11"); + hcompute_hw_output_global_wrapper_stencil_11->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + hcompute_hw_output_global_wrapper_stencil_11->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + + return prg; +} + + +// empty diff --git a/example_progs/camera_pipeline_2x2_unroll_memory.cpp b/example_progs/camera_pipeline_2x2_unroll_memory.cpp new file mode 100644 index 000000000..d2a38392a --- /dev/null +++ b/example_progs/camera_pipeline_2x2_unroll_memory.cpp @@ -0,0 +1,1078 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog camera_pipeline_2x2_unroll() { + prog prg; + prg.compute_unit_file = "camera_pipeline_2x2_unroll_compute.h"; + prg.name = "camera_pipeline_2x2_unroll"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_1; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_s0_y_yio", 0, 100); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -4)"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -4), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_1 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_function("hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -3)", "((hw_input_global_wrapper_s0_x_x*2) + -4)"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_store("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_s0_y_yio*2)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -4)) + auto hcompute_hw_input_global_wrapper_glb_stencil_2 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_function("hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -4)", "((hw_input_global_wrapper_s0_x_x*2) + -3)"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_store("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_s0_x_x*2) + 1)"); + +//store is: hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_s0_y_yio*2) + 1)) = hw_input.stencil(((hw_input_global_wrapper_s0_x_x*2) + -3), ((hw_input_global_wrapper_s0_y_yio*2) + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_3 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_function("hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_load("hw_input_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + -3)", "((hw_input_global_wrapper_s0_x_x*2) + -3)"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_store("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y_yio = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y_yio", 0, 100); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y_yio->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil((hw_input_global_wrapper_global_wrapper_s0_x_x*2), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_1 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_load("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_global_wrapper_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "(hw_input_global_wrapper_global_wrapper_s0_x_x*2)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), (hw_input_global_wrapper_global_wrapper_s0_y_yio*2)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_2 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_load("hw_input_global_wrapper_glb_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_global_wrapper_stencil", "(hw_input_global_wrapper_global_wrapper_s0_y_yio*2)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) = hw_input_global_wrapper.glb.stencil(((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_3 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_load("hw_input_global_wrapper_glb_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_store("hw_input_global_wrapper_global_wrapper_stencil", "((hw_input_global_wrapper_global_wrapper_s0_y_yio*2) + 1)", "((hw_input_global_wrapper_global_wrapper_s0_x_x*2) + 1)"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing denoised$1.stencil + auto denoised_1_s0_y_yio = prg.add_loop("denoised_1_s0_y_yio", 0, 98); + auto denoised_1_s0_x_x = denoised_1_s0_y_yio->add_loop("denoised_1_s0_x_x", 0, 130); + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 2)))))) + auto hcompute_denoised_1_stencil = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_function("hcompute_denoised_1_stencil"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 4)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "(denoised_1_s0_x_x*2)"); + hcompute_denoised_1_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 4)"); + prg.buffer_port_widths["denoised_1_stencil"] = 16; + hcompute_denoised_1_stencil->add_store("denoised_1_stencil", "(denoised_1_s0_y_yio*2)", "(denoised_1_s0_x_x*2)"); + +//store is: denoised$1.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 2), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil((denoised_1_s0_x_x*2), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 4), ((denoised_1_s0_y_yio*2) + 3)))))) + auto hcompute_denoised_1_stencil_1 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_function("hcompute_denoised_1_stencil_1"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 4)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 5)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 2)"); + hcompute_denoised_1_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "(denoised_1_s0_x_x*2)"); + hcompute_denoised_1_stencil_1->add_store("denoised_1_stencil", "((denoised_1_s0_y_yio*2) + 1)", "(denoised_1_s0_x_x*2)"); + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), (denoised_1_s0_y_yio*2)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 4)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), (denoised_1_s0_y_yio*2)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 2)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 2)))))) + auto hcompute_denoised_1_stencil_2 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_2"); + hcompute_denoised_1_stencil_2->add_function("hcompute_denoised_1_stencil_2"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 4)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 1)"); + hcompute_denoised_1_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 2)", "((denoised_1_s0_x_x*2) + 5)"); + hcompute_denoised_1_stencil_2->add_store("denoised_1_stencil", "(denoised_1_s0_y_yio*2)", "((denoised_1_s0_x_x*2) + 1)"); + +//store is: denoised$1.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 1)) = min(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 3)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 5)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 3), ((denoised_1_s0_y_yio*2) + 1)), max(hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 1), ((denoised_1_s0_y_yio*2) + 3)), hw_input_global_wrapper_global_wrapper.stencil(((denoised_1_s0_x_x*2) + 5), ((denoised_1_s0_y_yio*2) + 3)))))) + auto hcompute_denoised_1_stencil_3 = denoised_1_s0_x_x->add_op("op_hcompute_denoised_1_stencil_3"); + hcompute_denoised_1_stencil_3->add_function("hcompute_denoised_1_stencil_3"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 5)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 3)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 1)"); + hcompute_denoised_1_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "((denoised_1_s0_y_yio*2) + 3)", "((denoised_1_s0_x_x*2) + 5)"); + hcompute_denoised_1_stencil_3->add_store("denoised_1_stencil", "((denoised_1_s0_y_yio*2) + 1)", "((denoised_1_s0_x_x*2) + 1)"); + +//consuming denoised$1.stencil +////producing b_b.stencil + auto b_b_s0_y_yio = prg.add_loop("b_b_s0_y_yio", 0, 49); + auto b_b_s0_x_x = b_b_s0_y_yio->add_loop("b_b_s0_x_x", 0, 65); + +//store is: b_b.stencil((b_b_s0_x_x*2), (b_b_s0_y_yio*2)) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), ((b_b_s0_y_yio*4) + 1)) + auto hcompute_b_b_stencil = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_function("hcompute_b_b_stencil"); + hcompute_b_b_stencil->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 1)", "((b_b_s0_x_x*4) + 2)"); + prg.buffer_port_widths["b_b_stencil"] = 16; + hcompute_b_b_stencil->add_store("b_b_stencil", "(b_b_s0_y_yio*2)", "(b_b_s0_x_x*2)"); + +//store is: b_b.stencil((b_b_s0_x_x*2), ((b_b_s0_y_yio*2) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 2), ((b_b_s0_y_yio*4) + 3)) + auto hcompute_b_b_stencil_1 = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil_1"); + hcompute_b_b_stencil_1->add_function("hcompute_b_b_stencil_1"); + hcompute_b_b_stencil_1->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 3)", "((b_b_s0_x_x*4) + 2)"); + hcompute_b_b_stencil_1->add_store("b_b_stencil", "((b_b_s0_y_yio*2) + 1)", "(b_b_s0_x_x*2)"); + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), (b_b_s0_y_yio*2)) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), ((b_b_s0_y_yio*4) + 1)) + auto hcompute_b_b_stencil_2 = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil_2"); + hcompute_b_b_stencil_2->add_function("hcompute_b_b_stencil_2"); + hcompute_b_b_stencil_2->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 1)", "((b_b_s0_x_x*4) + 4)"); + hcompute_b_b_stencil_2->add_store("b_b_stencil", "(b_b_s0_y_yio*2)", "((b_b_s0_x_x*2) + 1)"); + +//store is: b_b.stencil(((b_b_s0_x_x*2) + 1), ((b_b_s0_y_yio*2) + 1)) = denoised$1.stencil(((b_b_s0_x_x*4) + 4), ((b_b_s0_y_yio*4) + 3)) + auto hcompute_b_b_stencil_3 = b_b_s0_x_x->add_op("op_hcompute_b_b_stencil_3"); + hcompute_b_b_stencil_3->add_function("hcompute_b_b_stencil_3"); + hcompute_b_b_stencil_3->add_load("denoised_1_stencil", "((b_b_s0_y_yio*4) + 3)", "((b_b_s0_x_x*4) + 4)"); + hcompute_b_b_stencil_3->add_store("b_b_stencil", "((b_b_s0_y_yio*2) + 1)", "((b_b_s0_x_x*2) + 1)"); + +//consuming b_b.stencil +////producing g_gb.stencil + auto g_gb_s0_y_yio = prg.add_loop("g_gb_s0_y_yio", 0, 49); + auto g_gb_s0_x_x = g_gb_s0_y_yio->add_loop("g_gb_s0_x_x", 0, 65); + +//store is: g_gb.stencil((g_gb_s0_x_x*2), (g_gb_s0_y_yio*2)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), ((g_gb_s0_y_yio*4) + 1)) + auto hcompute_g_gb_stencil = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_function("hcompute_g_gb_stencil"); + hcompute_g_gb_stencil->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 1)", "((g_gb_s0_x_x*4) + 1)"); + prg.buffer_port_widths["g_gb_stencil"] = 16; + hcompute_g_gb_stencil->add_store("g_gb_stencil", "(g_gb_s0_y_yio*2)", "(g_gb_s0_x_x*2)"); + +//store is: g_gb.stencil((g_gb_s0_x_x*2), ((g_gb_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 1), ((g_gb_s0_y_yio*4) + 3)) + auto hcompute_g_gb_stencil_1 = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil_1"); + hcompute_g_gb_stencil_1->add_function("hcompute_g_gb_stencil_1"); + hcompute_g_gb_stencil_1->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 3)", "((g_gb_s0_x_x*4) + 1)"); + hcompute_g_gb_stencil_1->add_store("g_gb_stencil", "((g_gb_s0_y_yio*2) + 1)", "(g_gb_s0_x_x*2)"); + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), (g_gb_s0_y_yio*2)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), ((g_gb_s0_y_yio*4) + 1)) + auto hcompute_g_gb_stencil_2 = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil_2"); + hcompute_g_gb_stencil_2->add_function("hcompute_g_gb_stencil_2"); + hcompute_g_gb_stencil_2->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 1)", "((g_gb_s0_x_x*4) + 3)"); + hcompute_g_gb_stencil_2->add_store("g_gb_stencil", "(g_gb_s0_y_yio*2)", "((g_gb_s0_x_x*2) + 1)"); + +//store is: g_gb.stencil(((g_gb_s0_x_x*2) + 1), ((g_gb_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gb_s0_x_x*4) + 3), ((g_gb_s0_y_yio*4) + 3)) + auto hcompute_g_gb_stencil_3 = g_gb_s0_x_x->add_op("op_hcompute_g_gb_stencil_3"); + hcompute_g_gb_stencil_3->add_function("hcompute_g_gb_stencil_3"); + hcompute_g_gb_stencil_3->add_load("denoised_1_stencil", "((g_gb_s0_y_yio*4) + 3)", "((g_gb_s0_x_x*4) + 3)"); + hcompute_g_gb_stencil_3->add_store("g_gb_stencil", "((g_gb_s0_y_yio*2) + 1)", "((g_gb_s0_x_x*2) + 1)"); + +//consuming g_gb.stencil +////producing g_gr.stencil + auto g_gr_s0_y_yio = prg.add_loop("g_gr_s0_y_yio", 0, 49); + auto g_gr_s0_x_x = g_gr_s0_y_yio->add_loop("g_gr_s0_x_x", 0, 65); + +//store is: g_gr.stencil((g_gr_s0_x_x*2), (g_gr_s0_y_yio*2)) = denoised$1.stencil((g_gr_s0_x_x*4), (g_gr_s0_y_yio*4)) + auto hcompute_g_gr_stencil = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_function("hcompute_g_gr_stencil"); + hcompute_g_gr_stencil->add_load("denoised_1_stencil", "(g_gr_s0_y_yio*4)", "(g_gr_s0_x_x*4)"); + prg.buffer_port_widths["g_gr_stencil"] = 16; + hcompute_g_gr_stencil->add_store("g_gr_stencil", "(g_gr_s0_y_yio*2)", "(g_gr_s0_x_x*2)"); + +//store is: g_gr.stencil((g_gr_s0_x_x*2), ((g_gr_s0_y_yio*2) + 1)) = denoised$1.stencil((g_gr_s0_x_x*4), ((g_gr_s0_y_yio*4) + 2)) + auto hcompute_g_gr_stencil_1 = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil_1"); + hcompute_g_gr_stencil_1->add_function("hcompute_g_gr_stencil_1"); + hcompute_g_gr_stencil_1->add_load("denoised_1_stencil", "((g_gr_s0_y_yio*4) + 2)", "(g_gr_s0_x_x*4)"); + hcompute_g_gr_stencil_1->add_store("g_gr_stencil", "((g_gr_s0_y_yio*2) + 1)", "(g_gr_s0_x_x*2)"); + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), (g_gr_s0_y_yio*2)) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), (g_gr_s0_y_yio*4)) + auto hcompute_g_gr_stencil_2 = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil_2"); + hcompute_g_gr_stencil_2->add_function("hcompute_g_gr_stencil_2"); + hcompute_g_gr_stencil_2->add_load("denoised_1_stencil", "(g_gr_s0_y_yio*4)", "((g_gr_s0_x_x*4) + 2)"); + hcompute_g_gr_stencil_2->add_store("g_gr_stencil", "(g_gr_s0_y_yio*2)", "((g_gr_s0_x_x*2) + 1)"); + +//store is: g_gr.stencil(((g_gr_s0_x_x*2) + 1), ((g_gr_s0_y_yio*2) + 1)) = denoised$1.stencil(((g_gr_s0_x_x*4) + 2), ((g_gr_s0_y_yio*4) + 2)) + auto hcompute_g_gr_stencil_3 = g_gr_s0_x_x->add_op("op_hcompute_g_gr_stencil_3"); + hcompute_g_gr_stencil_3->add_function("hcompute_g_gr_stencil_3"); + hcompute_g_gr_stencil_3->add_load("denoised_1_stencil", "((g_gr_s0_y_yio*4) + 2)", "((g_gr_s0_x_x*4) + 2)"); + hcompute_g_gr_stencil_3->add_store("g_gr_stencil", "((g_gr_s0_y_yio*2) + 1)", "((g_gr_s0_x_x*2) + 1)"); + +//consuming g_gr.stencil +////producing g_b.stencil + auto g_b_s0_y_yio = prg.add_loop("g_b_s0_y_yio", 0, 49); + auto g_b_s0_x_x = g_b_s0_y_yio->add_loop("g_b_s0_x_x", 0, 65); + +//store is: g_b.stencil((g_b_s0_x_x*2), (g_b_s0_y_yio*2)) = select((absd(g_gb.stencil((g_b_s0_x_x*2), (g_b_s0_y_yio*2)), g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)), g_gr.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)))), ((g_gb.stencil((g_b_s0_x_x*2), (g_b_s0_y_yio*2)) + g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)) + g_gr.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)))/(uint16)2)) + auto hcompute_g_b_stencil = g_b_s0_x_x->add_op("op_hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_function("hcompute_g_b_stencil"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "(g_b_s0_y_yio*2)", "(g_b_s0_x_x*2)"); + hcompute_g_b_stencil->add_load("g_gb_stencil", "(g_b_s0_y_yio*2)", "((g_b_s0_x_x*2) + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 1)"); + hcompute_g_b_stencil->add_load("g_gr_stencil", "(g_b_s0_y_yio*2)", "((g_b_s0_x_x*2) + 1)"); + prg.buffer_port_widths["g_b_stencil"] = 16; + hcompute_g_b_stencil->add_store("g_b_stencil", "(g_b_s0_y_yio*2)", "(g_b_s0_x_x*2)"); + +//store is: g_b.stencil((g_b_s0_x_x*2), ((g_b_s0_y_yio*2) + 1)) = select((absd(g_gb.stencil((g_b_s0_x_x*2), ((g_b_s0_y_yio*2) + 1)), g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 2)), g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)))), ((g_gb.stencil((g_b_s0_x_x*2), ((g_b_s0_y_yio*2) + 1)) + g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 2)) + g_gr.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_g_b_stencil_1 = g_b_s0_x_x->add_op("op_hcompute_g_b_stencil_1"); + hcompute_g_b_stencil_1->add_function("hcompute_g_b_stencil_1"); + hcompute_g_b_stencil_1->add_load("g_gb_stencil", "((g_b_s0_y_yio*2) + 1)", "(g_b_s0_x_x*2)"); + hcompute_g_b_stencil_1->add_load("g_gb_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 1)"); + hcompute_g_b_stencil_1->add_load("g_gr_stencil", "((g_b_s0_y_yio*2) + 2)", "((g_b_s0_x_x*2) + 1)"); + hcompute_g_b_stencil_1->add_load("g_gr_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 1)"); + hcompute_g_b_stencil_1->add_store("g_b_stencil", "((g_b_s0_y_yio*2) + 1)", "(g_b_s0_x_x*2)"); + +//store is: g_b.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)) = select((absd(g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)), g_gb.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)), g_gr.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2)))), ((g_gb.stencil(((g_b_s0_x_x*2) + 1), (g_b_s0_y_yio*2)) + g_gb.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)) + g_gr.stencil(((g_b_s0_x_x*2) + 2), (g_b_s0_y_yio*2)))/(uint16)2)) + auto hcompute_g_b_stencil_2 = g_b_s0_x_x->add_op("op_hcompute_g_b_stencil_2"); + hcompute_g_b_stencil_2->add_function("hcompute_g_b_stencil_2"); + hcompute_g_b_stencil_2->add_load("g_gb_stencil", "(g_b_s0_y_yio*2)", "((g_b_s0_x_x*2) + 1)"); + hcompute_g_b_stencil_2->add_load("g_gb_stencil", "(g_b_s0_y_yio*2)", "((g_b_s0_x_x*2) + 2)"); + hcompute_g_b_stencil_2->add_load("g_gr_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 2)"); + hcompute_g_b_stencil_2->add_load("g_gr_stencil", "(g_b_s0_y_yio*2)", "((g_b_s0_x_x*2) + 2)"); + hcompute_g_b_stencil_2->add_store("g_b_stencil", "(g_b_s0_y_yio*2)", "((g_b_s0_x_x*2) + 1)"); + +//store is: g_b.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)) = select((absd(g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)), g_gb.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1))) < absd(g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 2)), g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)))), ((g_gb.stencil(((g_b_s0_x_x*2) + 1), ((g_b_s0_y_yio*2) + 1)) + g_gb.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)))/(uint16)2), ((g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 2)) + g_gr.stencil(((g_b_s0_x_x*2) + 2), ((g_b_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_g_b_stencil_3 = g_b_s0_x_x->add_op("op_hcompute_g_b_stencil_3"); + hcompute_g_b_stencil_3->add_function("hcompute_g_b_stencil_3"); + hcompute_g_b_stencil_3->add_load("g_gb_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 1)"); + hcompute_g_b_stencil_3->add_load("g_gb_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 2)"); + hcompute_g_b_stencil_3->add_load("g_gr_stencil", "((g_b_s0_y_yio*2) + 2)", "((g_b_s0_x_x*2) + 2)"); + hcompute_g_b_stencil_3->add_load("g_gr_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 2)"); + hcompute_g_b_stencil_3->add_store("g_b_stencil", "((g_b_s0_y_yio*2) + 1)", "((g_b_s0_x_x*2) + 1)"); + +//consuming g_b.stencil +////producing b_gb.stencil + auto b_gb_s0_y_yio = prg.add_loop("b_gb_s0_y_yio", 0, 48); + auto b_gb_s0_x_x = b_gb_s0_y_yio->add_loop("b_gb_s0_x_x", 0, 64); + +//store is: b_gb.stencil((b_gb_s0_x_x*2), (b_gb_s0_y_yio*2)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) + ((b_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 1)) + b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 1)) + g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_b_gb_stencil = b_gb_s0_x_x->add_op("op_hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_function("hcompute_b_gb_stencil"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "(b_gb_s0_x_x*2)"); + hcompute_b_gb_stencil->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "(b_gb_s0_x_x*2)"); + hcompute_b_gb_stencil->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil->add_load("g_gb_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 1)"); + prg.buffer_port_widths["b_gb_stencil"] = 16; + hcompute_b_gb_stencil->add_store("b_gb_stencil", "(b_gb_s0_y_yio*2)", "(b_gb_s0_x_x*2)"); + +//store is: b_gb.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)) + ((b_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 2)) + b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_b.stencil((b_gb_s0_x_x*2), ((b_gb_s0_y_yio*2) + 2)) + g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) + auto hcompute_b_gb_stencil_1 = b_gb_s0_x_x->add_op("op_hcompute_b_gb_stencil_1"); + hcompute_b_gb_stencil_1->add_function("hcompute_b_gb_stencil_1"); + hcompute_b_gb_stencil_1->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "(b_gb_s0_x_x*2)"); + hcompute_b_gb_stencil_1->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil_1->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "(b_gb_s0_x_x*2)"); + hcompute_b_gb_stencil_1->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil_1->add_load("g_gb_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil_1->add_store("b_gb_stencil", "((b_gb_s0_y_yio*2) + 1)", "(b_gb_s0_x_x*2)"); + +//store is: b_gb.stencil(((b_gb_s0_x_x*2) + 1), (b_gb_s0_y_yio*2)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) + b_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) + g_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_b_gb_stencil_2 = b_gb_s0_x_x->add_op("op_hcompute_b_gb_stencil_2"); + hcompute_b_gb_stencil_2->add_function("hcompute_b_gb_stencil_2"); + hcompute_b_gb_stencil_2->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil_2->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 2)"); + hcompute_b_gb_stencil_2->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil_2->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 2)"); + hcompute_b_gb_stencil_2->add_load("g_gb_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 2)"); + hcompute_b_gb_stencil_2->add_store("b_gb_stencil", "(b_gb_s0_y_yio*2)", "((b_gb_s0_x_x*2) + 1)"); + +//store is: b_gb.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 2)) + ((b_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)) + b_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_b.stencil(((b_gb_s0_x_x*2) + 1), ((b_gb_s0_y_yio*2) + 2)) + g_b.stencil(((b_gb_s0_x_x*2) + 2), ((b_gb_s0_y_yio*2) + 2)))/(uint16)2)) + auto hcompute_b_gb_stencil_3 = b_gb_s0_x_x->add_op("op_hcompute_b_gb_stencil_3"); + hcompute_b_gb_stencil_3->add_function("hcompute_b_gb_stencil_3"); + hcompute_b_gb_stencil_3->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil_3->add_load("b_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 2)"); + hcompute_b_gb_stencil_3->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 1)"); + hcompute_b_gb_stencil_3->add_load("g_b_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 2)"); + hcompute_b_gb_stencil_3->add_load("g_gb_stencil", "((b_gb_s0_y_yio*2) + 2)", "((b_gb_s0_x_x*2) + 2)"); + hcompute_b_gb_stencil_3->add_store("b_gb_stencil", "((b_gb_s0_y_yio*2) + 1)", "((b_gb_s0_x_x*2) + 1)"); + +//consuming b_gb.stencil +////producing b_gr.stencil + auto b_gr_s0_y_yio = prg.add_loop("b_gr_s0_y_yio", 0, 48); + auto b_gr_s0_x_x = b_gr_s0_y_yio->add_loop("b_gr_s0_x_x", 0, 64); + +//store is: b_gr.stencil((b_gr_s0_x_x*2), (b_gr_s0_y_yio*2)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) + ((b_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)) + b_b.stencil((b_gr_s0_x_x*2), (b_gr_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)) + g_b.stencil((b_gr_s0_x_x*2), (b_gr_s0_y_yio*2)))/(uint16)2)) + auto hcompute_b_gr_stencil = b_gr_s0_x_x->add_op("op_hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_function("hcompute_b_gr_stencil"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "(b_gr_s0_y_yio*2)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil->add_load("b_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "(b_gr_s0_y_yio*2)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil->add_load("g_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil->add_load("g_gr_stencil", "((b_gr_s0_y_yio*2) + 1)", "((b_gr_s0_x_x*2) + 1)"); + prg.buffer_port_widths["b_gr_stencil"] = 16; + hcompute_b_gr_stencil->add_store("b_gr_stencil", "(b_gr_s0_y_yio*2)", "(b_gr_s0_x_x*2)"); + +//store is: b_gr.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 2)) + ((b_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 2)) + b_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 2)) + g_b.stencil((b_gr_s0_x_x*2), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_b_gr_stencil_1 = b_gr_s0_x_x->add_op("op_hcompute_b_gr_stencil_1"); + hcompute_b_gr_stencil_1->add_function("hcompute_b_gr_stencil_1"); + hcompute_b_gr_stencil_1->add_load("b_b_stencil", "((b_gr_s0_y_yio*2) + 2)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil_1->add_load("b_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil_1->add_load("g_b_stencil", "((b_gr_s0_y_yio*2) + 2)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil_1->add_load("g_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "(b_gr_s0_x_x*2)"); + hcompute_b_gr_stencil_1->add_load("g_gr_stencil", "((b_gr_s0_y_yio*2) + 2)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_1->add_store("b_gr_stencil", "((b_gr_s0_y_yio*2) + 1)", "(b_gr_s0_x_x*2)"); + +//store is: b_gr.stencil(((b_gr_s0_x_x*2) + 1), (b_gr_s0_y_yio*2)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 2), ((b_gr_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) + b_b.stencil(((b_gr_s0_x_x*2) + 1), (b_gr_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) + g_b.stencil(((b_gr_s0_x_x*2) + 1), (b_gr_s0_y_yio*2)))/(uint16)2)) + auto hcompute_b_gr_stencil_2 = b_gr_s0_x_x->add_op("op_hcompute_b_gr_stencil_2"); + hcompute_b_gr_stencil_2->add_function("hcompute_b_gr_stencil_2"); + hcompute_b_gr_stencil_2->add_load("b_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_2->add_load("b_b_stencil", "(b_gr_s0_y_yio*2)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_2->add_load("g_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_2->add_load("g_b_stencil", "(b_gr_s0_y_yio*2)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_2->add_load("g_gr_stencil", "((b_gr_s0_y_yio*2) + 1)", "((b_gr_s0_x_x*2) + 2)"); + hcompute_b_gr_stencil_2->add_store("b_gr_stencil", "(b_gr_s0_y_yio*2)", "((b_gr_s0_x_x*2) + 1)"); + +//store is: b_gr.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((b_gr_s0_x_x*2) + 2), ((b_gr_s0_y_yio*2) + 2)) + ((b_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 2)) + b_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 2)) + g_b.stencil(((b_gr_s0_x_x*2) + 1), ((b_gr_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_b_gr_stencil_3 = b_gr_s0_x_x->add_op("op_hcompute_b_gr_stencil_3"); + hcompute_b_gr_stencil_3->add_function("hcompute_b_gr_stencil_3"); + hcompute_b_gr_stencil_3->add_load("b_b_stencil", "((b_gr_s0_y_yio*2) + 2)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_3->add_load("b_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_3->add_load("g_b_stencil", "((b_gr_s0_y_yio*2) + 2)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_3->add_load("g_b_stencil", "((b_gr_s0_y_yio*2) + 1)", "((b_gr_s0_x_x*2) + 1)"); + hcompute_b_gr_stencil_3->add_load("g_gr_stencil", "((b_gr_s0_y_yio*2) + 2)", "((b_gr_s0_x_x*2) + 2)"); + hcompute_b_gr_stencil_3->add_store("b_gr_stencil", "((b_gr_s0_y_yio*2) + 1)", "((b_gr_s0_x_x*2) + 1)"); + +//consuming b_gr.stencil +////producing g_r.stencil + auto g_r_s0_y_yio = prg.add_loop("g_r_s0_y_yio", 0, 49); + auto g_r_s0_x_x = g_r_s0_y_yio->add_loop("g_r_s0_x_x", 0, 65); + +//store is: g_r.stencil((g_r_s0_x_x*2), (g_r_s0_y_yio*2)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)), g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1))) < absd(g_gb.stencil((g_r_s0_x_x*2), (g_r_s0_y_yio*2)), g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)) + g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)))/(uint16)2), ((g_gb.stencil((g_r_s0_x_x*2), (g_r_s0_y_yio*2)) + g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_g_r_stencil = g_r_s0_x_x->add_op("op_hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_function("hcompute_g_r_stencil"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "(g_r_s0_y_yio*2)", "(g_r_s0_x_x*2)"); + hcompute_g_r_stencil->add_load("g_gb_stencil", "((g_r_s0_y_yio*2) + 1)", "(g_r_s0_x_x*2)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 1)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 1)", "(g_r_s0_x_x*2)"); + prg.buffer_port_widths["g_r_stencil"] = 16; + hcompute_g_r_stencil->add_store("g_r_stencil", "(g_r_s0_y_yio*2)", "(g_r_s0_x_x*2)"); + +//store is: g_r.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)), g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2))) < absd(g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)), g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)) + g_gr.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2)))/(uint16)2), ((g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 1)) + g_gb.stencil((g_r_s0_x_x*2), ((g_r_s0_y_yio*2) + 2)))/(uint16)2)) + auto hcompute_g_r_stencil_1 = g_r_s0_x_x->add_op("op_hcompute_g_r_stencil_1"); + hcompute_g_r_stencil_1->add_function("hcompute_g_r_stencil_1"); + hcompute_g_r_stencil_1->add_load("g_gb_stencil", "((g_r_s0_y_yio*2) + 1)", "(g_r_s0_x_x*2)"); + hcompute_g_r_stencil_1->add_load("g_gb_stencil", "((g_r_s0_y_yio*2) + 2)", "(g_r_s0_x_x*2)"); + hcompute_g_r_stencil_1->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 2)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil_1->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 2)", "(g_r_s0_x_x*2)"); + hcompute_g_r_stencil_1->add_store("g_r_stencil", "((g_r_s0_y_yio*2) + 1)", "(g_r_s0_x_x*2)"); + +//store is: g_r.stencil(((g_r_s0_x_x*2) + 1), (g_r_s0_y_yio*2)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 1)), g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1))) < absd(g_gb.stencil(((g_r_s0_x_x*2) + 1), (g_r_s0_y_yio*2)), g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 1)) + g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)))/(uint16)2), ((g_gb.stencil(((g_r_s0_x_x*2) + 1), (g_r_s0_y_yio*2)) + g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_g_r_stencil_2 = g_r_s0_x_x->add_op("op_hcompute_g_r_stencil_2"); + hcompute_g_r_stencil_2->add_function("hcompute_g_r_stencil_2"); + hcompute_g_r_stencil_2->add_load("g_gb_stencil", "(g_r_s0_y_yio*2)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil_2->add_load("g_gb_stencil", "((g_r_s0_y_yio*2) + 1)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil_2->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 1)", "((g_r_s0_x_x*2) + 2)"); + hcompute_g_r_stencil_2->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 1)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil_2->add_store("g_r_stencil", "(g_r_s0_y_yio*2)", "((g_r_s0_x_x*2) + 1)"); + +//store is: g_r.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)) = select((absd(g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 2)), g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2))) < absd(g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)), g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)))), ((g_gr.stencil(((g_r_s0_x_x*2) + 2), ((g_r_s0_y_yio*2) + 2)) + g_gr.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)))/(uint16)2), ((g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 1)) + g_gb.stencil(((g_r_s0_x_x*2) + 1), ((g_r_s0_y_yio*2) + 2)))/(uint16)2)) + auto hcompute_g_r_stencil_3 = g_r_s0_x_x->add_op("op_hcompute_g_r_stencil_3"); + hcompute_g_r_stencil_3->add_function("hcompute_g_r_stencil_3"); + hcompute_g_r_stencil_3->add_load("g_gb_stencil", "((g_r_s0_y_yio*2) + 1)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil_3->add_load("g_gb_stencil", "((g_r_s0_y_yio*2) + 2)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil_3->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 2)", "((g_r_s0_x_x*2) + 2)"); + hcompute_g_r_stencil_3->add_load("g_gr_stencil", "((g_r_s0_y_yio*2) + 2)", "((g_r_s0_x_x*2) + 1)"); + hcompute_g_r_stencil_3->add_store("g_r_stencil", "((g_r_s0_y_yio*2) + 1)", "((g_r_s0_x_x*2) + 1)"); + +//consuming g_r.stencil +////producing b_r.stencil + auto b_r_s0_y_yio = prg.add_loop("b_r_s0_y_yio", 0, 48); + auto b_r_s0_x_x = b_r_s0_y_yio->add_loop("b_r_s0_x_x", 0, 64); + +//store is: b_r.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)) = select((absd(b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)), b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)), b_b.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)))), ((g_r.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)) + ((b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil((b_r_s0_x_x*2), (b_r_s0_y_yio*2)))/(uint16)2))) + auto hcompute_b_r_stencil = b_r_s0_x_x->add_op("op_hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_function("hcompute_b_r_stencil"); + hcompute_b_r_stencil->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil->add_load("b_b_stencil", "(b_r_s0_y_yio*2)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil->add_load("g_b_stencil", "(b_r_s0_y_yio*2)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil->add_load("g_r_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 1)"); + prg.buffer_port_widths["b_r_stencil"] = 16; + hcompute_b_r_stencil->add_store("b_r_stencil", "(b_r_s0_y_yio*2)", "(b_r_s0_x_x*2)"); + +//store is: b_r.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)) = select((absd(b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 2)), b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)), b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)))), ((g_r.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil((b_r_s0_x_x*2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2))) + auto hcompute_b_r_stencil_1 = b_r_s0_x_x->add_op("op_hcompute_b_r_stencil_1"); + hcompute_b_r_stencil_1->add_function("hcompute_b_r_stencil_1"); + hcompute_b_r_stencil_1->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 2)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil_1->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_1->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_1->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil_1->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 2)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil_1->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_1->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_1->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "(b_r_s0_x_x*2)"); + hcompute_b_r_stencil_1->add_load("g_r_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_1->add_store("b_r_stencil", "((b_r_s0_y_yio*2) + 1)", "(b_r_s0_x_x*2)"); + +//store is: b_r.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)) = select((absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)), b_b.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)), b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))), ((g_r.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 2), (b_r_s0_y_yio*2)) + ((b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + b_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + g_b.stencil(((b_r_s0_x_x*2) + 1), (b_r_s0_y_yio*2)))/(uint16)2))) + auto hcompute_b_r_stencil_2 = b_r_s0_x_x->add_op("op_hcompute_b_r_stencil_2"); + hcompute_b_r_stencil_2->add_function("hcompute_b_r_stencil_2"); + hcompute_b_r_stencil_2->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_2->add_load("b_b_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_2->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_2->add_load("b_b_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_2->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_2->add_load("g_b_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_2->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_2->add_load("g_b_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_2->add_load("g_r_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_2->add_store("b_r_stencil", "(b_r_s0_y_yio*2)", "((b_r_s0_x_x*2) + 1)"); + +//store is: b_r.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)) = select((absd(b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)), b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1))) < absd(b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 2)), b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))), ((g_r.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)), ((g_r.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 1)) + ((b_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 2)) + b_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_b.stencil(((b_r_s0_x_x*2) + 2), ((b_r_s0_y_yio*2) + 2)) + g_b.stencil(((b_r_s0_x_x*2) + 1), ((b_r_s0_y_yio*2) + 1)))/(uint16)2))) + auto hcompute_b_r_stencil_3 = b_r_s0_x_x->add_op("op_hcompute_b_r_stencil_3"); + hcompute_b_r_stencil_3->add_function("hcompute_b_r_stencil_3"); + hcompute_b_r_stencil_3->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_3->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_3->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 2)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_3->add_load("b_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_3->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 2)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_3->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_3->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 2)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_3->add_load("g_b_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + hcompute_b_r_stencil_3->add_load("g_r_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 2)"); + hcompute_b_r_stencil_3->add_store("b_r_stencil", "((b_r_s0_y_yio*2) + 1)", "((b_r_s0_x_x*2) + 1)"); + +//consuming b_r.stencil +////producing r_r.stencil + auto r_r_s0_y_yio = prg.add_loop("r_r_s0_y_yio", 0, 49); + auto r_r_s0_x_x = r_r_s0_y_yio->add_loop("r_r_s0_x_x", 0, 65); + +//store is: r_r.stencil((r_r_s0_x_x*2), (r_r_s0_y_yio*2)) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y_yio*4) + 2)) + auto hcompute_r_r_stencil = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_function("hcompute_r_r_stencil"); + hcompute_r_r_stencil->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 2)", "((r_r_s0_x_x*4) + 1)"); + prg.buffer_port_widths["r_r_stencil"] = 16; + hcompute_r_r_stencil->add_store("r_r_stencil", "(r_r_s0_y_yio*2)", "(r_r_s0_x_x*2)"); + +//store is: r_r.stencil((r_r_s0_x_x*2), ((r_r_s0_y_yio*2) + 1)) = denoised$1.stencil(((r_r_s0_x_x*4) + 1), ((r_r_s0_y_yio*4) + 4)) + auto hcompute_r_r_stencil_1 = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil_1"); + hcompute_r_r_stencil_1->add_function("hcompute_r_r_stencil_1"); + hcompute_r_r_stencil_1->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 4)", "((r_r_s0_x_x*4) + 1)"); + hcompute_r_r_stencil_1->add_store("r_r_stencil", "((r_r_s0_y_yio*2) + 1)", "(r_r_s0_x_x*2)"); + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), (r_r_s0_y_yio*2)) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y_yio*4) + 2)) + auto hcompute_r_r_stencil_2 = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil_2"); + hcompute_r_r_stencil_2->add_function("hcompute_r_r_stencil_2"); + hcompute_r_r_stencil_2->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 2)", "((r_r_s0_x_x*4) + 3)"); + hcompute_r_r_stencil_2->add_store("r_r_stencil", "(r_r_s0_y_yio*2)", "((r_r_s0_x_x*2) + 1)"); + +//store is: r_r.stencil(((r_r_s0_x_x*2) + 1), ((r_r_s0_y_yio*2) + 1)) = denoised$1.stencil(((r_r_s0_x_x*4) + 3), ((r_r_s0_y_yio*4) + 4)) + auto hcompute_r_r_stencil_3 = r_r_s0_x_x->add_op("op_hcompute_r_r_stencil_3"); + hcompute_r_r_stencil_3->add_function("hcompute_r_r_stencil_3"); + hcompute_r_r_stencil_3->add_load("denoised_1_stencil", "((r_r_s0_y_yio*4) + 4)", "((r_r_s0_x_x*4) + 3)"); + hcompute_r_r_stencil_3->add_store("r_r_stencil", "((r_r_s0_y_yio*2) + 1)", "((r_r_s0_x_x*2) + 1)"); + +//consuming r_r.stencil +////producing r_b.stencil + auto r_b_s0_y_yio = prg.add_loop("r_b_s0_y_yio", 0, 48); + auto r_b_s0_x_x = r_b_s0_y_yio->add_loop("r_b_s0_x_x", 0, 64); + +//store is: r_b.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)), r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1))) < absd(r_r.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + g_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x_x*2), (r_b_s0_y_yio*2)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2))) + auto hcompute_r_b_stencil = r_b_s0_x_x->add_op("op_hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_function("hcompute_r_b_stencil"); + hcompute_r_b_stencil->add_load("g_b_stencil", "((r_b_s0_y_yio*2) + 1)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y_yio*2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "(r_b_s0_y_yio*2)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y_yio*2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "(r_b_s0_y_yio*2)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + prg.buffer_port_widths["r_b_stencil"] = 16; + hcompute_r_b_stencil->add_store("r_b_stencil", "(r_b_s0_y_yio*2)", "(r_b_s0_x_x*2)"); + +//store is: r_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)), r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2))) < absd(r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)), ((g_b.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil((r_b_s0_x_x*2), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2))) + auto hcompute_r_b_stencil_1 = r_b_s0_x_x->add_op("op_hcompute_r_b_stencil_1"); + hcompute_r_b_stencil_1->add_function("hcompute_r_b_stencil_1"); + hcompute_r_b_stencil_1->add_load("g_b_stencil", "((r_b_s0_y_yio*2) + 2)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil_1->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 2)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil_1->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil_1->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_1->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_1->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_1->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 2)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil_1->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "(r_b_s0_x_x*2)"); + hcompute_r_b_stencil_1->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_1->add_store("r_b_stencil", "((r_b_s0_y_yio*2) + 1)", "(r_b_s0_x_x*2)"); + +//store is: r_b.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 2), (r_b_s0_y_yio*2)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1))) < absd(r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)), r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)))), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_b_s0_x_x*2) + 2), (r_b_s0_y_yio*2)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 2), (r_b_s0_y_yio*2)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), (r_b_s0_y_yio*2)) + g_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)))/(uint16)2))) + auto hcompute_r_b_stencil_2 = r_b_s0_x_x->add_op("op_hcompute_r_b_stencil_2"); + hcompute_r_b_stencil_2->add_function("hcompute_r_b_stencil_2"); + hcompute_r_b_stencil_2->add_load("g_b_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_2->add_load("g_r_stencil", "(r_b_s0_y_yio*2)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_2->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_2->add_load("g_r_stencil", "(r_b_s0_y_yio*2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_2->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_2->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_2->add_load("r_r_stencil", "(r_b_s0_y_yio*2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_2->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_2->add_load("r_r_stencil", "(r_b_s0_y_yio*2)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_2->add_store("r_b_stencil", "(r_b_s0_y_yio*2)", "((r_b_s0_x_x*2) + 1)"); + +//store is: r_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) = select((absd(r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)), r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2))) < absd(r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)), r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 2)))), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)), ((g_b.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + r_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_b_s0_x_x*2) + 1), ((r_b_s0_y_yio*2) + 1)) + g_r.stencil(((r_b_s0_x_x*2) + 2), ((r_b_s0_y_yio*2) + 2)))/(uint16)2))) + auto hcompute_r_b_stencil_3 = r_b_s0_x_x->add_op("op_hcompute_r_b_stencil_3"); + hcompute_r_b_stencil_3->add_function("hcompute_r_b_stencil_3"); + hcompute_r_b_stencil_3->add_load("g_b_stencil", "((r_b_s0_y_yio*2) + 2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_3->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_3->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_3->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_3->add_load("g_r_stencil", "((r_b_s0_y_yio*2) + 2)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_3->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_3->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 2)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_3->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + hcompute_r_b_stencil_3->add_load("r_r_stencil", "((r_b_s0_y_yio*2) + 2)", "((r_b_s0_x_x*2) + 2)"); + hcompute_r_b_stencil_3->add_store("r_b_stencil", "((r_b_s0_y_yio*2) + 1)", "((r_b_s0_x_x*2) + 1)"); + +//consuming r_b.stencil +////producing r_gb.stencil + auto r_gb_s0_y_yio = prg.add_loop("r_gb_s0_y_yio", 0, 48); + auto r_gb_s0_x_x = r_gb_s0_y_yio->add_loop("r_gb_s0_x_x", 0, 64); + +//store is: r_gb.stencil((r_gb_s0_x_x*2), (r_gb_s0_y_yio*2)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 1), (r_gb_s0_y_yio*2)) + r_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 1), (r_gb_s0_y_yio*2)) + g_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_r_gb_stencil = r_gb_s0_x_x->add_op("op_hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_function("hcompute_r_gb_stencil"); + hcompute_r_gb_stencil->add_load("g_gb_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "(r_gb_s0_y_yio*2)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil->add_load("g_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "(r_gb_s0_y_yio*2)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil->add_load("r_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 1)"); + prg.buffer_port_widths["r_gb_stencil"] = 16; + hcompute_r_gb_stencil->add_store("r_gb_stencil", "(r_gb_s0_y_yio*2)", "(r_gb_s0_x_x*2)"); + +//store is: r_gb.stencil((r_gb_s0_x_x*2), ((r_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) + r_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) + g_r.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) + auto hcompute_r_gb_stencil_1 = r_gb_s0_x_x->add_op("op_hcompute_r_gb_stencil_1"); + hcompute_r_gb_stencil_1->add_function("hcompute_r_gb_stencil_1"); + hcompute_r_gb_stencil_1->add_load("g_gb_stencil", "((r_gb_s0_y_yio*2) + 2)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil_1->add_load("g_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil_1->add_load("g_r_stencil", "((r_gb_s0_y_yio*2) + 2)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil_1->add_load("r_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil_1->add_load("r_r_stencil", "((r_gb_s0_y_yio*2) + 2)", "((r_gb_s0_x_x*2) + 1)"); + hcompute_r_gb_stencil_1->add_store("r_gb_stencil", "((r_gb_s0_y_yio*2) + 1)", "(r_gb_s0_x_x*2)"); + +//store is: r_gb.stencil(((r_gb_s0_x_x*2) + 1), (r_gb_s0_y_yio*2)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 2), (r_gb_s0_y_yio*2)) + r_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 2), (r_gb_s0_y_yio*2)) + g_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_r_gb_stencil_2 = r_gb_s0_x_x->add_op("op_hcompute_r_gb_stencil_2"); + hcompute_r_gb_stencil_2->add_function("hcompute_r_gb_stencil_2"); + hcompute_r_gb_stencil_2->add_load("g_gb_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_2->add_load("g_r_stencil", "(r_gb_s0_y_yio*2)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_2->add_load("g_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_2->add_load("r_r_stencil", "(r_gb_s0_y_yio*2)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_2->add_load("r_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_2->add_store("r_gb_stencil", "(r_gb_s0_y_yio*2)", "((r_gb_s0_x_x*2) + 1)"); + +//store is: r_gb.stencil(((r_gb_s0_x_x*2) + 1), ((r_gb_s0_y_yio*2) + 1)) = ((g_gb.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)) + r_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) - ((g_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 1)) + g_r.stencil(((r_gb_s0_x_x*2) + 2), ((r_gb_s0_y_yio*2) + 2)))/(uint16)2)) + auto hcompute_r_gb_stencil_3 = r_gb_s0_x_x->add_op("op_hcompute_r_gb_stencil_3"); + hcompute_r_gb_stencil_3->add_function("hcompute_r_gb_stencil_3"); + hcompute_r_gb_stencil_3->add_load("g_gb_stencil", "((r_gb_s0_y_yio*2) + 2)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_3->add_load("g_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_3->add_load("g_r_stencil", "((r_gb_s0_y_yio*2) + 2)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_3->add_load("r_r_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_3->add_load("r_r_stencil", "((r_gb_s0_y_yio*2) + 2)", "((r_gb_s0_x_x*2) + 2)"); + hcompute_r_gb_stencil_3->add_store("r_gb_stencil", "((r_gb_s0_y_yio*2) + 1)", "((r_gb_s0_x_x*2) + 1)"); + +//consuming r_gb.stencil +////producing r_gr.stencil + auto r_gr_s0_y_yio = prg.add_loop("r_gr_s0_y_yio", 0, 48); + auto r_gr_s0_x_x = r_gr_s0_y_yio->add_loop("r_gr_s0_x_x", 0, 64); + +//store is: r_gr.stencil((r_gr_s0_x_x*2), (r_gr_s0_y_yio*2)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) + ((r_r.stencil((r_gr_s0_x_x*2), (r_gr_s0_y_yio*2)) + r_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)) + g_r.stencil((r_gr_s0_x_x*2), (r_gr_s0_y_yio*2)))/(uint16)2)) + auto hcompute_r_gr_stencil = r_gr_s0_x_x->add_op("op_hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_function("hcompute_r_gr_stencil"); + hcompute_r_gr_stencil->add_load("g_gr_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "(r_gr_s0_y_yio*2)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil->add_load("g_r_stencil", "(r_gr_s0_y_yio*2)", "(r_gr_s0_x_x*2)"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "(r_gr_s0_y_yio*2)", "(r_gr_s0_x_x*2)"); + hcompute_r_gr_stencil->add_load("r_r_stencil", "(r_gr_s0_y_yio*2)", "((r_gr_s0_x_x*2) + 1)"); + prg.buffer_port_widths["r_gr_stencil"] = 16; + hcompute_r_gr_stencil->add_store("r_gr_stencil", "(r_gr_s0_y_yio*2)", "(r_gr_s0_x_x*2)"); + +//store is: r_gr.stencil((r_gr_s0_x_x*2), ((r_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 2)) + ((r_r.stencil((r_gr_s0_x_x*2), ((r_gr_s0_y_yio*2) + 1)) + r_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) + g_r.stencil((r_gr_s0_x_x*2), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_r_gr_stencil_1 = r_gr_s0_x_x->add_op("op_hcompute_r_gr_stencil_1"); + hcompute_r_gr_stencil_1->add_function("hcompute_r_gr_stencil_1"); + hcompute_r_gr_stencil_1->add_load("g_gr_stencil", "((r_gr_s0_y_yio*2) + 2)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil_1->add_load("g_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil_1->add_load("g_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "(r_gr_s0_x_x*2)"); + hcompute_r_gr_stencil_1->add_load("r_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "(r_gr_s0_x_x*2)"); + hcompute_r_gr_stencil_1->add_load("r_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil_1->add_store("r_gr_stencil", "((r_gr_s0_y_yio*2) + 1)", "(r_gr_s0_x_x*2)"); + +//store is: r_gr.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 1)) + ((r_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)) + r_r.stencil(((r_gr_s0_x_x*2) + 2), (r_gr_s0_y_yio*2)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 2), (r_gr_s0_y_yio*2)) + g_r.stencil(((r_gr_s0_x_x*2) + 1), (r_gr_s0_y_yio*2)))/(uint16)2)) + auto hcompute_r_gr_stencil_2 = r_gr_s0_x_x->add_op("op_hcompute_r_gr_stencil_2"); + hcompute_r_gr_stencil_2->add_function("hcompute_r_gr_stencil_2"); + hcompute_r_gr_stencil_2->add_load("g_gr_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 2)"); + hcompute_r_gr_stencil_2->add_load("g_r_stencil", "(r_gr_s0_y_yio*2)", "((r_gr_s0_x_x*2) + 2)"); + hcompute_r_gr_stencil_2->add_load("g_r_stencil", "(r_gr_s0_y_yio*2)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil_2->add_load("r_r_stencil", "(r_gr_s0_y_yio*2)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil_2->add_load("r_r_stencil", "(r_gr_s0_y_yio*2)", "((r_gr_s0_x_x*2) + 2)"); + hcompute_r_gr_stencil_2->add_store("r_gr_stencil", "(r_gr_s0_y_yio*2)", "((r_gr_s0_x_x*2) + 1)"); + +//store is: r_gr.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) = ((g_gr.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 2)) + ((r_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)) + r_r.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) - ((g_r.stencil(((r_gr_s0_x_x*2) + 2), ((r_gr_s0_y_yio*2) + 1)) + g_r.stencil(((r_gr_s0_x_x*2) + 1), ((r_gr_s0_y_yio*2) + 1)))/(uint16)2)) + auto hcompute_r_gr_stencil_3 = r_gr_s0_x_x->add_op("op_hcompute_r_gr_stencil_3"); + hcompute_r_gr_stencil_3->add_function("hcompute_r_gr_stencil_3"); + hcompute_r_gr_stencil_3->add_load("g_gr_stencil", "((r_gr_s0_y_yio*2) + 2)", "((r_gr_s0_x_x*2) + 2)"); + hcompute_r_gr_stencil_3->add_load("g_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 2)"); + hcompute_r_gr_stencil_3->add_load("g_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil_3->add_load("r_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 1)"); + hcompute_r_gr_stencil_3->add_load("r_r_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 2)"); + hcompute_r_gr_stencil_3->add_store("r_gr_stencil", "((r_gr_s0_y_yio*2) + 1)", "((r_gr_s0_x_x*2) + 1)"); + +//consuming r_gr.stencil +////producing demosaicked$1.stencil + auto demosaicked_1_s0_y_yio = prg.add_loop("demosaicked_1_s0_y_yio", 0, 96); + auto demosaicked_1_s0_x_x = demosaicked_1_s0_y_yio->add_loop("demosaicked_1_s0_x_x", 0, 128); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 0) = r_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_function("hcompute_demosaicked_1_stencil"); + hcompute_demosaicked_1_stencil->add_load("r_gr_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + prg.buffer_port_widths["demosaicked_1_stencil"] = 16; + hcompute_demosaicked_1_stencil->add_store("demosaicked_1_stencil", "0", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 1) = g_gr.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_1 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_function("hcompute_demosaicked_1_stencil_1"); + hcompute_demosaicked_1_stencil_1->add_load("g_gr_stencil", "(demosaicked_1_s0_y_yio + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_1->add_store("demosaicked_1_stencil", "1", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), (demosaicked_1_s0_y_yio*2), 2) = b_gr.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_2 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_function("hcompute_demosaicked_1_stencil_2"); + hcompute_demosaicked_1_stencil_2->add_load("b_gr_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_2->add_store("demosaicked_1_stencil", "2", "(demosaicked_1_s0_y_yio*2)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_b.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_3 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_function("hcompute_demosaicked_1_stencil_3"); + hcompute_demosaicked_1_stencil_3->add_load("r_b_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_3->add_store("demosaicked_1_stencil", "0", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_4 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_function("hcompute_demosaicked_1_stencil_4"); + hcompute_demosaicked_1_stencil_4->add_load("g_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_4->add_store("demosaicked_1_stencil", "1", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil((demosaicked_1_s0_x_x*2), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_b.stencil(demosaicked_1_s0_x_x, (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_5 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_function("hcompute_demosaicked_1_stencil_5"); + hcompute_demosaicked_1_stencil_5->add_load("b_b_stencil", "(demosaicked_1_s0_y_yio + 1)", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_5->add_store("demosaicked_1_stencil", "2", "((demosaicked_1_s0_y_yio*2) + 1)", "(demosaicked_1_s0_x_x*2)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 0) = r_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_6 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_6"); + hcompute_demosaicked_1_stencil_6->add_function("hcompute_demosaicked_1_stencil_6"); + hcompute_demosaicked_1_stencil_6->add_load("r_r_stencil", "demosaicked_1_s0_y_yio", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_6->add_store("demosaicked_1_stencil", "0", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 1) = g_r.stencil((demosaicked_1_s0_x_x + 1), demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_7 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_7"); + hcompute_demosaicked_1_stencil_7->add_function("hcompute_demosaicked_1_stencil_7"); + hcompute_demosaicked_1_stencil_7->add_load("g_r_stencil", "demosaicked_1_s0_y_yio", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_7->add_store("demosaicked_1_stencil", "1", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), (demosaicked_1_s0_y_yio*2), 2) = b_r.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_8 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_8"); + hcompute_demosaicked_1_stencil_8->add_function("hcompute_demosaicked_1_stencil_8"); + hcompute_demosaicked_1_stencil_8->add_load("b_r_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_8->add_store("demosaicked_1_stencil", "2", "(demosaicked_1_s0_y_yio*2)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 0) = r_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_9 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_9"); + hcompute_demosaicked_1_stencil_9->add_function("hcompute_demosaicked_1_stencil_9"); + hcompute_demosaicked_1_stencil_9->add_load("r_gb_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_9->add_store("demosaicked_1_stencil", "0", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 1) = g_gb.stencil((demosaicked_1_s0_x_x + 1), (demosaicked_1_s0_y_yio + 1)) + auto hcompute_demosaicked_1_stencil_10 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_10"); + hcompute_demosaicked_1_stencil_10->add_function("hcompute_demosaicked_1_stencil_10"); + hcompute_demosaicked_1_stencil_10->add_load("g_gb_stencil", "(demosaicked_1_s0_y_yio + 1)", "(demosaicked_1_s0_x_x + 1)"); + hcompute_demosaicked_1_stencil_10->add_store("demosaicked_1_stencil", "1", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//store is: demosaicked$1.stencil(((demosaicked_1_s0_x_x*2) + 1), ((demosaicked_1_s0_y_yio*2) + 1), 2) = b_gb.stencil(demosaicked_1_s0_x_x, demosaicked_1_s0_y_yio) + auto hcompute_demosaicked_1_stencil_11 = demosaicked_1_s0_x_x->add_op("op_hcompute_demosaicked_1_stencil_11"); + hcompute_demosaicked_1_stencil_11->add_function("hcompute_demosaicked_1_stencil_11"); + hcompute_demosaicked_1_stencil_11->add_load("b_gb_stencil", "demosaicked_1_s0_y_yio", "demosaicked_1_s0_x_x"); + hcompute_demosaicked_1_stencil_11->add_store("demosaicked_1_stencil", "2", "((demosaicked_1_s0_y_yio*2) + 1)", "((demosaicked_1_s0_x_x*2) + 1)"); + +//consuming demosaicked$1.stencil +////producing corrected.stencil + auto corrected_s0_y_yio = prg.add_loop("corrected_s0_y_yio", 0, 96); + auto corrected_s0_x_x = corrected_s0_y_yio->add_loop("corrected_s0_x_x", 0, 128); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_function("hcompute_corrected_stencil"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + prg.buffer_port_widths["corrected_stencil"] = 16; + hcompute_corrected_stencil->add_store("corrected_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_1 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_function("hcompute_corrected_stencil_1"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_1->add_store("corrected_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_2 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_function("hcompute_corrected_stencil_2"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_2->add_store("corrected_stencil", "2", "(corrected_s0_y_yio*2)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_3 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_function("hcompute_corrected_stencil_3"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_3->add_store("corrected_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_4 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_function("hcompute_corrected_stencil_4"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_4->add_store("corrected_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil((corrected_s0_x_x*2), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_5 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_function("hcompute_corrected_stencil_5"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + hcompute_corrected_stencil_5->add_store("corrected_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "(corrected_s0_x_x*2)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_6 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_6"); + hcompute_corrected_stencil_6->add_function("hcompute_corrected_stencil_6"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_6->add_store("corrected_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_7 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_7"); + hcompute_corrected_stencil_7->add_function("hcompute_corrected_stencil_7"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_7->add_store("corrected_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), (corrected_s0_y_yio*2), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_8 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_8"); + hcompute_corrected_stencil_8->add_function("hcompute_corrected_stencil_8"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "0", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "1", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_load("demosaicked_1_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_8->add_store("corrected_stencil", "2", "(corrected_s0_y_yio*2)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*549)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-103)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*7)/256))) + (int16)-40) + auto hcompute_corrected_stencil_9 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_9"); + hcompute_corrected_stencil_9->add_function("hcompute_corrected_stencil_9"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_9->add_store("corrected_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-96)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*373)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*62)/256))) + (int16)-29) + auto hcompute_corrected_stencil_10 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_10"); + hcompute_corrected_stencil_10->add_function("hcompute_corrected_stencil_10"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_10->add_store("corrected_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//store is: corrected.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2) = (((int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 0), (uint16)10000))*-31)/256)) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 1), (uint16)10000))*-261)/256))) + int16(((int32(min(demosaicked$1.stencil(((corrected_s0_x_x*2) + 1), ((corrected_s0_y_yio*2) + 1), 2), (uint16)10000))*883)/256))) + (int16)-22) + auto hcompute_corrected_stencil_11 = corrected_s0_x_x->add_op("op_hcompute_corrected_stencil_11"); + hcompute_corrected_stencil_11->add_function("hcompute_corrected_stencil_11"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "0", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "1", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_load("demosaicked_1_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + hcompute_corrected_stencil_11->add_store("corrected_stencil", "2", "((corrected_s0_y_yio*2) + 1)", "((corrected_s0_x_x*2) + 1)"); + +//consuming corrected.stencil +////producing curvea0 + +//consuming curvea0 +////producing curved.stencil + auto curved_s0_y_yio = prg.add_loop("curved_s0_y_yio", 0, 96); + auto curved_s0_x_x = curved_s0_y_yio->add_loop("curved_s0_x_x", 0, 128); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil = curved_s0_x_x->add_op("op_hcompute_curved_stencil"); + hcompute_curved_stencil->add_function("hcompute_curved_stencil"); + hcompute_curved_stencil->add_load("corrected_stencil", "0", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + prg.buffer_port_widths["curved_stencil"] = 16; + hcompute_curved_stencil->add_store("curved_stencil", "0", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil->index_variable_prefetch_cycle(1); + hcompute_curved_stencil->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_1 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_function("hcompute_curved_stencil_1"); + hcompute_curved_stencil_1->add_load("corrected_stencil", "1", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_1->add_store("curved_stencil", "1", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_1->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_1->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_2 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_function("hcompute_curved_stencil_2"); + hcompute_curved_stencil_2->add_load("corrected_stencil", "2", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_2->add_store("curved_stencil", "2", "(curved_s0_y_yio*2)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_2->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_2->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_3 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_function("hcompute_curved_stencil_3"); + hcompute_curved_stencil_3->add_load("corrected_stencil", "0", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_3->add_store("curved_stencil", "0", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_3->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_3->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_4 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_function("hcompute_curved_stencil_4"); + hcompute_curved_stencil_4->add_load("corrected_stencil", "1", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_4->add_store("curved_stencil", "1", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_4->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_4->add_latency(1); + +//store is: curved.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil((curved_s0_x_x*2), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_5 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_function("hcompute_curved_stencil_5"); + hcompute_curved_stencil_5->add_load("corrected_stencil", "2", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + hcompute_curved_stencil_5->add_store("curved_stencil", "2", "((curved_s0_y_yio*2) + 1)", "(curved_s0_x_x*2)"); + //hcompute_curved_stencil_5->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_5->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_6 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_6"); + hcompute_curved_stencil_6->add_function("hcompute_curved_stencil_6"); + hcompute_curved_stencil_6->add_load("corrected_stencil", "0", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_6->add_store("curved_stencil", "0", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_6->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_6->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_7 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_7"); + hcompute_curved_stencil_7->add_function("hcompute_curved_stencil_7"); + hcompute_curved_stencil_7->add_load("corrected_stencil", "1", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_7->add_store("curved_stencil", "1", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_7->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_7->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), (curved_s0_y_yio*2), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_8 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_8"); + hcompute_curved_stencil_8->add_function("hcompute_curved_stencil_8"); + hcompute_curved_stencil_8->add_load("corrected_stencil", "2", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_8->add_store("curved_stencil", "2", "(curved_s0_y_yio*2)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_8->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_8->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 0), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_9 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_9"); + hcompute_curved_stencil_9->add_function("hcompute_curved_stencil_9"); + hcompute_curved_stencil_9->add_load("corrected_stencil", "0", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_9->add_store("curved_stencil", "0", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_9->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_9->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 1), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_10 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_10"); + hcompute_curved_stencil_10->add_function("hcompute_curved_stencil_10"); + hcompute_curved_stencil_10->add_load("corrected_stencil", "1", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_10->add_store("curved_stencil", "1", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_10->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_10->add_latency(1); + +//store is: curved.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2) = curvea0[int32(uint16(max(min(corrected.stencil(((curved_s0_x_x*2) + 1), ((curved_s0_y_yio*2) + 1), 2), (int16)1023), (int16)0)))] + auto hcompute_curved_stencil_11 = curved_s0_x_x->add_op("op_hcompute_curved_stencil_11"); + hcompute_curved_stencil_11->add_function("hcompute_curved_stencil_11"); + hcompute_curved_stencil_11->add_load("corrected_stencil", "2", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + hcompute_curved_stencil_11->add_store("curved_stencil", "2", "((curved_s0_y_yio*2) + 1)", "((curved_s0_x_x*2) + 1)"); + //hcompute_curved_stencil_11->index_variable_prefetch_cycle(1); + hcompute_curved_stencil_11->add_latency(1); + +//consuming curved.stencil + auto hw_output_s0_y_yi_yio = prg.add_loop("hw_output_s0_y_yi_yio", 0, 96); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi_yio->add_loop("hw_output_s0_x_xi_xi", 0, 128); + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 0) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("curved_stencil", "0", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "0"); + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 1) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("curved_stencil", "1", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "1"); + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2)) = curved.stencil((hw_output_s0_x_xi_xi*2), (hw_output_s0_y_yi_yio*2), 2) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("curved_stencil", "2", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "(hw_output_s0_x_xi_xi*2)", "2"); + +//store is: hw_output.glb.stencil(0, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 0) + auto hcompute_hw_output_glb_stencil_3 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_function("hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_load("curved_stencil", "0", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_3->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "0"); + +//store is: hw_output.glb.stencil(1, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 1) + auto hcompute_hw_output_glb_stencil_4 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_function("hcompute_hw_output_glb_stencil_4"); + hcompute_hw_output_glb_stencil_4->add_load("curved_stencil", "1", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_4->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "1"); + +//store is: hw_output.glb.stencil(2, (hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil((hw_output_s0_x_xi_xi*2), ((hw_output_s0_y_yi_yio*2) + 1), 2) + auto hcompute_hw_output_glb_stencil_5 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_function("hcompute_hw_output_glb_stencil_5"); + hcompute_hw_output_glb_stencil_5->add_load("curved_stencil", "2", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)"); + hcompute_hw_output_glb_stencil_5->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "(hw_output_s0_x_xi_xi*2)", "2"); + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 0) + auto hcompute_hw_output_glb_stencil_6 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_6"); + hcompute_hw_output_glb_stencil_6->add_function("hcompute_hw_output_glb_stencil_6"); + hcompute_hw_output_glb_stencil_6->add_load("curved_stencil", "0", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_6->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 1) + auto hcompute_hw_output_glb_stencil_7 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_7"); + hcompute_hw_output_glb_stencil_7->add_function("hcompute_hw_output_glb_stencil_7"); + hcompute_hw_output_glb_stencil_7->add_load("curved_stencil", "1", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_7->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), (hw_output_s0_y_yi_yio*2), 2) + auto hcompute_hw_output_glb_stencil_8 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_8"); + hcompute_hw_output_glb_stencil_8->add_function("hcompute_hw_output_glb_stencil_8"); + hcompute_hw_output_glb_stencil_8->add_load("curved_stencil", "2", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_8->add_store("hw_output_glb_stencil", "(hw_output_s0_y_yi_yio*2)", "((hw_output_s0_x_xi_xi*2) + 1)", "2"); + +//store is: hw_output.glb.stencil(0, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 0) + auto hcompute_hw_output_glb_stencil_9 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_9"); + hcompute_hw_output_glb_stencil_9->add_function("hcompute_hw_output_glb_stencil_9"); + hcompute_hw_output_glb_stencil_9->add_load("curved_stencil", "0", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_9->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output.glb.stencil(1, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 1) + auto hcompute_hw_output_glb_stencil_10 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_10"); + hcompute_hw_output_glb_stencil_10->add_function("hcompute_hw_output_glb_stencil_10"); + hcompute_hw_output_glb_stencil_10->add_load("curved_stencil", "1", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_10->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output.glb.stencil(2, ((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1)) = curved.stencil(((hw_output_s0_x_xi_xi*2) + 1), ((hw_output_s0_y_yi_yio*2) + 1), 2) + auto hcompute_hw_output_glb_stencil_11 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_11"); + hcompute_hw_output_glb_stencil_11->add_function("hcompute_hw_output_glb_stencil_11"); + hcompute_hw_output_glb_stencil_11->add_load("curved_stencil", "2", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)"); + hcompute_hw_output_glb_stencil_11->add_store("hw_output_glb_stencil", "((hw_output_s0_y_yi_yio*2) + 1)", "((hw_output_s0_x_xi_xi*2) + 1)", "2"); + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi_yio = prg.add_loop("hw_output_global_wrapper_s0_y_yi_yio", 0, 96); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi_yio->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 128); + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_3 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_function("hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + hcompute_hw_output_global_wrapper_stencil_3->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_4 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_function("hcompute_hw_output_global_wrapper_stencil_4"); + hcompute_hw_output_global_wrapper_stencil_4->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + hcompute_hw_output_global_wrapper_stencil_4->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi*2), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_5 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_function("hcompute_hw_output_global_wrapper_stencil_5"); + hcompute_hw_output_global_wrapper_stencil_5->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + hcompute_hw_output_global_wrapper_stencil_5->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "(hw_output_global_wrapper_s0_x_xi_xi*2)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_6 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_6"); + hcompute_hw_output_global_wrapper_stencil_6->add_function("hcompute_hw_output_global_wrapper_stencil_6"); + hcompute_hw_output_global_wrapper_stencil_6->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + hcompute_hw_output_global_wrapper_stencil_6->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_7 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_7"); + hcompute_hw_output_global_wrapper_stencil_7->add_function("hcompute_hw_output_global_wrapper_stencil_7"); + hcompute_hw_output_global_wrapper_stencil_7->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + hcompute_hw_output_global_wrapper_stencil_7->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), (hw_output_global_wrapper_s0_y_yi_yio*2)) + auto hcompute_hw_output_global_wrapper_stencil_8 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_8"); + hcompute_hw_output_global_wrapper_stencil_8->add_function("hcompute_hw_output_global_wrapper_stencil_8"); + hcompute_hw_output_global_wrapper_stencil_8->add_load("hw_output_glb_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + hcompute_hw_output_global_wrapper_stencil_8->add_store("hw_output_global_wrapper_stencil", "(hw_output_global_wrapper_s0_y_yi_yio*2)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + +//store is: hw_output_global_wrapper.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(0, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_9 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_9"); + hcompute_hw_output_global_wrapper_stencil_9->add_function("hcompute_hw_output_global_wrapper_stencil_9"); + hcompute_hw_output_global_wrapper_stencil_9->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + hcompute_hw_output_global_wrapper_stencil_9->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "0"); + +//store is: hw_output_global_wrapper.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(1, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_10 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_10"); + hcompute_hw_output_global_wrapper_stencil_10->add_function("hcompute_hw_output_global_wrapper_stencil_10"); + hcompute_hw_output_global_wrapper_stencil_10->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + hcompute_hw_output_global_wrapper_stencil_10->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "1"); + +//store is: hw_output_global_wrapper.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) = hw_output.glb.stencil(2, ((hw_output_global_wrapper_s0_x_xi_xi*2) + 1), ((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)) + auto hcompute_hw_output_global_wrapper_stencil_11 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_11"); + hcompute_hw_output_global_wrapper_stencil_11->add_function("hcompute_hw_output_global_wrapper_stencil_11"); + hcompute_hw_output_global_wrapper_stencil_11->add_load("hw_output_glb_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + hcompute_hw_output_global_wrapper_stencil_11->add_store("hw_output_global_wrapper_stencil", "((hw_output_global_wrapper_s0_y_yi_yio*2) + 1)", "((hw_output_global_wrapper_s0_x_xi_xi*2) + 1)", "2"); + + return prg; +} + + +// empty diff --git a/example_progs/complex_mem_pond_memory.cpp b/example_progs/complex_mem_pond_memory.cpp index 0ca4933af..12f27e1f7 100644 --- a/example_progs/complex_mem_pond_memory.cpp +++ b/example_progs/complex_mem_pond_memory.cpp @@ -85,9 +85,9 @@ prog complex_mem_pond() { hcompute_kernel_pond_stencil->add_store("kernel_pond_stencil", "kernel_pond_s0_y", "kernel_pond_s0_x", "kernel_pond_s0_w_w_cgra", "kernel_pond_s0_z", "kernel_pond_s0_zz"); //consuming kernel_pond.stencil - auto output_pond_s1_r_z = output_cgra_s0_x->add_loop("output_pond_s1_r_z", 0, 8); - auto output_pond_s1_r_y = output_pond_s1_r_z->add_loop("output_pond_s1_r_y", 0, 3); - auto output_pond_s1_r_x = output_pond_s1_r_y->add_loop("output_pond_s1_r_x", 0, 3); + auto output_pond_s1_r_z = output_cgra_s0_x->add_loop("output_pond_s1_r_y", 0, 3); + auto output_pond_s1_r_y = output_pond_s1_r_z->add_loop("output_pond_s1_r_x", 0, 3); + auto output_pond_s1_r_x = output_pond_s1_r_y->add_loop("output_pond_s1_r_z", 0, 8); //store is: output_pond.stencil(0, 0, 0) = ((kernel_pond.stencil(0, output_pond_s1_r_z, 0, output_pond_s1_r_x, output_pond_s1_r_y)*input_pond.stencil(0, output_pond_s1_r_z, output_pond_s1_r_x, output_pond_s1_r_y)) + ((kernel_pond.stencil(1, output_pond_s1_r_z, 0, output_pond_s1_r_x, output_pond_s1_r_y)*input_pond.stencil(1, output_pond_s1_r_z, output_pond_s1_r_x, output_pond_s1_r_y)) + ((kernel_pond.stencil(2, output_pond_s1_r_z, 0, output_pond_s1_r_x, output_pond_s1_r_y)*input_pond.stencil(2, output_pond_s1_r_z, output_pond_s1_r_x, output_pond_s1_r_y)) + (output_pond.stencil(0, 0, 0) + (kernel_pond.stencil(3, output_pond_s1_r_z, 0, output_pond_s1_r_x, output_pond_s1_r_y)*input_pond.stencil(3, output_pond_s1_r_z, output_pond_s1_r_x, output_pond_s1_r_y)))))) auto hcompute_output_pond_stencil_1 = output_pond_s1_r_x->add_op("op_hcompute_output_pond_stencil_1"); diff --git a/example_progs/fp_arith_memory.cpp b/example_progs/fp_arith_memory.cpp new file mode 100644 index 000000000..f5c65b61e --- /dev/null +++ b/example_progs/fp_arith_memory.cpp @@ -0,0 +1,55 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog fp_arith() { + prog prg; + prg.compute_unit_file = "fp_arith_compute.h"; + prg.name = "fp_arith"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 64); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", 0, 64); + +//store is: hw_input_global_wrapper.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x"); + +//consuming hw_input_global_wrapper.stencil +////producing mult.stencil + auto mult_s0_y = prg.add_loop("mult_s0_y", 0, 64); + auto mult_s0_x = mult_s0_y->add_loop("mult_s0_x", 0, 64); + +//store is: mult.stencil(mult_s0_x, mult_s0_y) = (bfloat16(hw_input_global_wrapper.stencil(mult_s0_x, mult_s0_y))*13.250000h) + auto hcompute_mult_stencil = mult_s0_x->add_op("op_hcompute_mult_stencil"); + hcompute_mult_stencil->add_function("hcompute_mult_stencil"); + hcompute_mult_stencil->add_load("hw_input_global_wrapper_stencil", "mult_s0_y", "mult_s0_x"); + prg.buffer_port_widths["mult_stencil"] = 16; + hcompute_mult_stencil->add_store("mult_stencil", "mult_s0_y", "mult_s0_x"); + +//consuming mult.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 64); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 64); + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(mult.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("mult_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + + return prg; +} + + +// empty diff --git a/example_progs/fp_pointwise_memory.cpp b/example_progs/fp_pointwise_memory.cpp new file mode 100644 index 000000000..86ca75969 --- /dev/null +++ b/example_progs/fp_pointwise_memory.cpp @@ -0,0 +1,55 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog fp_pointwise() { + prog prg; + prg.compute_unit_file = "fp_pointwise_compute.h"; + prg.name = "fp_pointwise"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 64); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", 0, 64); + +//store is: hw_input_global_wrapper.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x"); + +//consuming hw_input_global_wrapper.stencil +////producing product.stencil + auto product_s0_y = prg.add_loop("product_s0_y", 0, 64); + auto product_s0_x = product_s0_y->add_loop("product_s0_x", 0, 64); + +//store is: product.stencil(product_s0_x, product_s0_y) = (hw_input_global_wrapper.stencil(product_s0_x, product_s0_y)*3.140625h) + auto hcompute_product_stencil = product_s0_x->add_op("op_hcompute_product_stencil"); + hcompute_product_stencil->add_function("hcompute_product_stencil"); + hcompute_product_stencil->add_load("hw_input_global_wrapper_stencil", "product_s0_y", "product_s0_x"); + prg.buffer_port_widths["product_stencil"] = 16; + hcompute_product_stencil->add_store("product_stencil", "product_s0_y", "product_s0_x"); + +//consuming product.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 64); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 64); + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) = product.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("product_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + + return prg; +} + + +// empty diff --git a/example_progs/harris_color_memory.cpp b/example_progs/harris_color_memory.cpp new file mode 100644 index 000000000..d6bf2cc30 --- /dev/null +++ b/example_progs/harris_color_memory.cpp @@ -0,0 +1,899 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog harris_color_unroll4() { + prog prg; + prg.compute_unit_file = "harris_color_unroll4_compute.h"; + prg.name = "harris_color_unroll4"; + +// Stencil &hw_input_stencil = arg_1; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_3; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 261); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x_x", 0, 76); + +//store is: hw_input_global_wrapper.glb.stencil(0, (hw_input_global_wrapper_s0_x_x*4), hw_input_global_wrapper_s0_y) = hw_input.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + -3), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -3)", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "(hw_input_global_wrapper_s0_x_x*4)", "0"); + +//store is: hw_input_global_wrapper.glb.stencil(1, (hw_input_global_wrapper_s0_x_x*4), hw_input_global_wrapper_s0_y) = hw_input.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + -3), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_1 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_function("hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -3)", "1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "(hw_input_global_wrapper_s0_x_x*4)", "1"); + +//store is: hw_input_global_wrapper.glb.stencil(2, (hw_input_global_wrapper_s0_x_x*4), hw_input_global_wrapper_s0_y) = hw_input.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + -3), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_2 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_function("hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -3)", "2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "(hw_input_global_wrapper_s0_x_x*4)", "2"); + +//store is: hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_s0_y) = hw_input.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + -2), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_3 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_function("hcompute_hw_input_global_wrapper_glb_stencil_3"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -2)", "0"); + hcompute_hw_input_global_wrapper_glb_stencil_3->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 1)", "0"); + +//store is: hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_s0_y) = hw_input.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + -2), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_4 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_4"); + hcompute_hw_input_global_wrapper_glb_stencil_4->add_function("hcompute_hw_input_global_wrapper_glb_stencil_4"); + hcompute_hw_input_global_wrapper_glb_stencil_4->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -2)", "1"); + hcompute_hw_input_global_wrapper_glb_stencil_4->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 1)", "1"); + +//store is: hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_s0_y) = hw_input.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + -2), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_5 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_5"); + hcompute_hw_input_global_wrapper_glb_stencil_5->add_function("hcompute_hw_input_global_wrapper_glb_stencil_5"); + hcompute_hw_input_global_wrapper_glb_stencil_5->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -2)", "2"); + hcompute_hw_input_global_wrapper_glb_stencil_5->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 1)", "2"); + +//store is: hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_s0_y) = hw_input.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + -1), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_6 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_6"); + hcompute_hw_input_global_wrapper_glb_stencil_6->add_function("hcompute_hw_input_global_wrapper_glb_stencil_6"); + hcompute_hw_input_global_wrapper_glb_stencil_6->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -1)", "0"); + hcompute_hw_input_global_wrapper_glb_stencil_6->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 2)", "0"); + +//store is: hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_s0_y) = hw_input.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + -1), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_7 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_7"); + hcompute_hw_input_global_wrapper_glb_stencil_7->add_function("hcompute_hw_input_global_wrapper_glb_stencil_7"); + hcompute_hw_input_global_wrapper_glb_stencil_7->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -1)", "1"); + hcompute_hw_input_global_wrapper_glb_stencil_7->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 2)", "1"); + +//store is: hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_s0_y) = hw_input.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + -1), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_8 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_8"); + hcompute_hw_input_global_wrapper_glb_stencil_8->add_function("hcompute_hw_input_global_wrapper_glb_stencil_8"); + hcompute_hw_input_global_wrapper_glb_stencil_8->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "((hw_input_global_wrapper_s0_x_x*4) + -1)", "2"); + hcompute_hw_input_global_wrapper_glb_stencil_8->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 2)", "2"); + +//store is: hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_s0_y) = hw_input.stencil(0, (hw_input_global_wrapper_s0_x_x*4), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_9 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_9"); + hcompute_hw_input_global_wrapper_glb_stencil_9->add_function("hcompute_hw_input_global_wrapper_glb_stencil_9"); + hcompute_hw_input_global_wrapper_glb_stencil_9->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "(hw_input_global_wrapper_s0_x_x*4)", "0"); + hcompute_hw_input_global_wrapper_glb_stencil_9->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 3)", "0"); + +//store is: hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_s0_y) = hw_input.stencil(1, (hw_input_global_wrapper_s0_x_x*4), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_10 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_10"); + hcompute_hw_input_global_wrapper_glb_stencil_10->add_function("hcompute_hw_input_global_wrapper_glb_stencil_10"); + hcompute_hw_input_global_wrapper_glb_stencil_10->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "(hw_input_global_wrapper_s0_x_x*4)", "1"); + hcompute_hw_input_global_wrapper_glb_stencil_10->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 3)", "1"); + +//store is: hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_s0_y) = hw_input.stencil(2, (hw_input_global_wrapper_s0_x_x*4), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_11 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_11"); + hcompute_hw_input_global_wrapper_glb_stencil_11->add_function("hcompute_hw_input_global_wrapper_glb_stencil_11"); + hcompute_hw_input_global_wrapper_glb_stencil_11->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "(hw_input_global_wrapper_s0_x_x*4)", "2"); + hcompute_hw_input_global_wrapper_glb_stencil_11->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "((hw_input_global_wrapper_s0_x_x*4) + 3)", "2"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y", 0, 261); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 76); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(0, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*4)", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*4)", "0"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(1, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_1 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*4)", "1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*4)", "1"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(2, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_2 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*4)", "2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "(hw_input_global_wrapper_global_wrapper_s0_x_x*4)", "2"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_3 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_3"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1)", "0"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_3->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1)", "0"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_4 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_4"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_4->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_4"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_4->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1)", "1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_4->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1)", "1"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_5 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_5"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_5->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_5"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_5->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1)", "2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_5->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1)", "2"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_6 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_6"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_6->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_6"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_6->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2)", "0"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_6->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2)", "0"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_7 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_7"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_7->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_7"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_7->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2)", "1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_7->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2)", "1"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_8 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_8"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_8->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_8"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_8->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2)", "2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_8->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2)", "2"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_9 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_9"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_9->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_9"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_9->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3)", "0"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_9->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3)", "0"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_10 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_10"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_10->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_10"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_10->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3)", "1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_10->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3)", "1"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_11 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_11"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_11->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_11"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_11->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3)", "2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_11->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3)", "2"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing gray.stencil + auto gray_s0_y = prg.add_loop("gray_s0_y", 0, 261); + auto gray_s0_x_x = gray_s0_y->add_loop("gray_s0_x_x", 0, 76); + +//store is: gray.stencil((gray_s0_x_x*4), gray_s0_y) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, (gray_s0_x_x*4), gray_s0_y))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, (gray_s0_x_x*4), gray_s0_y))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, (gray_s0_x_x*4), gray_s0_y))*(uint16)77)))/(uint16)256) + auto hcompute_gray_stencil = gray_s0_x_x->add_op("op_hcompute_gray_stencil"); + hcompute_gray_stencil->add_function("hcompute_gray_stencil"); + hcompute_gray_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "(gray_s0_x_x*4)", "1"); + hcompute_gray_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "(gray_s0_x_x*4)", "2"); + hcompute_gray_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "(gray_s0_x_x*4)", "0"); + prg.buffer_port_widths["gray_stencil"] = 16; + hcompute_gray_stencil->add_store("gray_stencil", "gray_s0_y", "(gray_s0_x_x*4)"); + +//store is: gray.stencil(((gray_s0_x_x*4) + 1), gray_s0_y) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x*4) + 1), gray_s0_y))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x*4) + 1), gray_s0_y))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x*4) + 1), gray_s0_y))*(uint16)77)))/(uint16)256) + auto hcompute_gray_stencil_1 = gray_s0_x_x->add_op("op_hcompute_gray_stencil_1"); + hcompute_gray_stencil_1->add_function("hcompute_gray_stencil_1"); + hcompute_gray_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 1)", "1"); + hcompute_gray_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 1)", "2"); + hcompute_gray_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 1)", "0"); + hcompute_gray_stencil_1->add_store("gray_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 1)"); + +//store is: gray.stencil(((gray_s0_x_x*4) + 2), gray_s0_y) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x*4) + 2), gray_s0_y))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x*4) + 2), gray_s0_y))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x*4) + 2), gray_s0_y))*(uint16)77)))/(uint16)256) + auto hcompute_gray_stencil_2 = gray_s0_x_x->add_op("op_hcompute_gray_stencil_2"); + hcompute_gray_stencil_2->add_function("hcompute_gray_stencil_2"); + hcompute_gray_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 2)", "1"); + hcompute_gray_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 2)", "2"); + hcompute_gray_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 2)", "0"); + hcompute_gray_stencil_2->add_store("gray_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 2)"); + +//store is: gray.stencil(((gray_s0_x_x*4) + 3), gray_s0_y) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x*4) + 3), gray_s0_y))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x*4) + 3), gray_s0_y))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x*4) + 3), gray_s0_y))*(uint16)77)))/(uint16)256) + auto hcompute_gray_stencil_3 = gray_s0_x_x->add_op("op_hcompute_gray_stencil_3"); + hcompute_gray_stencil_3->add_function("hcompute_gray_stencil_3"); + hcompute_gray_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 3)", "1"); + hcompute_gray_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 3)", "2"); + hcompute_gray_stencil_3->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 3)", "0"); + hcompute_gray_stencil_3->add_store("gray_stencil", "gray_s0_y", "((gray_s0_x_x*4) + 3)"); + +//consuming gray.stencil +////producing grad_x_unclamp.stencil + auto grad_x_unclamp_s0_y = prg.add_loop("grad_x_unclamp_s0_y", 0, 259); + auto grad_x_unclamp_s0_x_x = grad_x_unclamp_s0_y->add_loop("grad_x_unclamp_s0_x_x", 0, 75); + +//store is: grad_x_unclamp.stencil((grad_x_unclamp_s0_x_x*4), grad_x_unclamp_s0_y) = (int16)0 + auto hcompute_grad_x_unclamp_stencil = grad_x_unclamp_s0_x_x->add_op("op_hcompute_grad_x_unclamp_stencil"); + hcompute_grad_x_unclamp_stencil->add_function("hcompute_grad_x_unclamp_stencil"); + prg.buffer_port_widths["grad_x_unclamp_stencil"] = 16; + hcompute_grad_x_unclamp_stencil->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s0_y", "(grad_x_unclamp_s0_x_x*4)"); + + auto grad_x_unclamp_s0_y_1 = prg.add_loop("grad_x_unclamp_s0_y_1", 0, 259); + auto grad_x_unclamp_s0_x_x_1 = grad_x_unclamp_s0_y_1->add_loop("grad_x_unclamp_s0_x_x_1", 0, 75); +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x*4) + 1), grad_x_unclamp_s0_y) = (int16)0 + auto hcompute_grad_x_unclamp_stencil_1 = grad_x_unclamp_s0_x_x_1->add_op("op_hcompute_grad_x_unclamp_stencil_1"); + hcompute_grad_x_unclamp_stencil_1->add_function("hcompute_grad_x_unclamp_stencil_1"); + hcompute_grad_x_unclamp_stencil_1->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s0_y_1", "((grad_x_unclamp_s0_x_x_1*4) + 1)"); + + auto grad_x_unclamp_s0_y_2 = prg.add_loop("grad_x_unclamp_s0_y_2", 0, 259); + auto grad_x_unclamp_s0_x_x_2 = grad_x_unclamp_s0_y_2->add_loop("grad_x_unclamp_s0_x_x_2", 0, 75); +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x*4) + 2), grad_x_unclamp_s0_y) = (int16)0 + auto hcompute_grad_x_unclamp_stencil_2 = grad_x_unclamp_s0_x_x_2->add_op("op_hcompute_grad_x_unclamp_stencil_2"); + hcompute_grad_x_unclamp_stencil_2->add_function("hcompute_grad_x_unclamp_stencil_2"); + hcompute_grad_x_unclamp_stencil_2->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s0_y_2", "((grad_x_unclamp_s0_x_x_2*4) + 2)"); + + auto grad_x_unclamp_s0_y_3 = prg.add_loop("grad_x_unclamp_s0_y_3", 0, 259); + auto grad_x_unclamp_s0_x_x_3 = grad_x_unclamp_s0_y_3->add_loop("grad_x_unclamp_s0_x_x_3", 0, 75); +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x*4) + 3), grad_x_unclamp_s0_y) = (int16)0 + auto hcompute_grad_x_unclamp_stencil_3 = grad_x_unclamp_s0_x_x_3->add_op("op_hcompute_grad_x_unclamp_stencil_3"); + hcompute_grad_x_unclamp_stencil_3->add_function("hcompute_grad_x_unclamp_stencil_3"); + hcompute_grad_x_unclamp_stencil_3->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s0_y_3", "((grad_x_unclamp_s0_x_x_3*4) + 3)"); + auto grad_x_unclamp_s1_y = prg.add_loop("grad_x_unclamp_s1_y", 0, 259); + auto grad_x_unclamp_s1_x_x = grad_x_unclamp_s1_y->add_loop("grad_x_unclamp_s1_x_x", 0, 75); + +//store is: grad_x_unclamp.stencil((grad_x_unclamp_s1_x_x*4), grad_x_unclamp_s1_y) = ((((((grad_x_unclamp.stencil((grad_x_unclamp_s1_x_x*4), grad_x_unclamp_s1_y) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil((grad_x_unclamp_s1_x_x*4), grad_x_unclamp_s1_y))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), grad_x_unclamp_s1_y))) - (int16(gray.stencil((grad_x_unclamp_s1_x_x*4), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil((grad_x_unclamp_s1_x_x*4), (grad_x_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), (grad_x_unclamp_s1_y + 2)))) + auto hcompute_grad_x_unclamp_stencil_4 = grad_x_unclamp_s1_x_x->add_op("op_hcompute_grad_x_unclamp_stencil_4"); + hcompute_grad_x_unclamp_stencil_4->add_function("hcompute_grad_x_unclamp_stencil_4"); + hcompute_grad_x_unclamp_stencil_4->add_load("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y", "(grad_x_unclamp_s1_x_x*4)"); + hcompute_grad_x_unclamp_stencil_4->add_load("gray_stencil", "(grad_x_unclamp_s1_y + 1)", "((grad_x_unclamp_s1_x_x*4) + 2)"); + hcompute_grad_x_unclamp_stencil_4->add_load("gray_stencil", "grad_x_unclamp_s1_y", "(grad_x_unclamp_s1_x_x*4)"); + hcompute_grad_x_unclamp_stencil_4->add_load("gray_stencil", "grad_x_unclamp_s1_y", "((grad_x_unclamp_s1_x_x*4) + 2)"); + hcompute_grad_x_unclamp_stencil_4->add_load("gray_stencil", "(grad_x_unclamp_s1_y + 1)", "(grad_x_unclamp_s1_x_x*4)"); + hcompute_grad_x_unclamp_stencil_4->add_load("gray_stencil", "(grad_x_unclamp_s1_y + 2)", "(grad_x_unclamp_s1_x_x*4)"); + hcompute_grad_x_unclamp_stencil_4->add_load("gray_stencil", "(grad_x_unclamp_s1_y + 2)", "((grad_x_unclamp_s1_x_x*4) + 2)"); + hcompute_grad_x_unclamp_stencil_4->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y", "(grad_x_unclamp_s1_x_x*4)"); + + auto grad_x_unclamp_s1_y_1 = prg.add_loop("grad_x_unclamp_s1_y_1", 0, 259); + auto grad_x_unclamp_s1_x_x_1 = grad_x_unclamp_s1_y_1->add_loop("grad_x_unclamp_s1_x_x_1", 0, 75); +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 1), grad_x_unclamp_s1_y) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 1), grad_x_unclamp_s1_y) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 1), grad_x_unclamp_s1_y))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), grad_x_unclamp_s1_y))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 1), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 1), (grad_x_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), (grad_x_unclamp_s1_y + 2)))) + auto hcompute_grad_x_unclamp_stencil_5 = grad_x_unclamp_s1_x_x_1->add_op("op_hcompute_grad_x_unclamp_stencil_5"); + hcompute_grad_x_unclamp_stencil_5->add_function("hcompute_grad_x_unclamp_stencil_5"); + hcompute_grad_x_unclamp_stencil_5->add_load("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y_1", "((grad_x_unclamp_s1_x_x_1*4) + 1)"); + hcompute_grad_x_unclamp_stencil_5->add_load("gray_stencil", "(grad_x_unclamp_s1_y_1 + 1)", "((grad_x_unclamp_s1_x_x_1*4) + 1)"); + hcompute_grad_x_unclamp_stencil_5->add_load("gray_stencil", "(grad_x_unclamp_s1_y_1 + 2)", "((grad_x_unclamp_s1_x_x_1*4) + 1)"); + hcompute_grad_x_unclamp_stencil_5->add_load("gray_stencil", "(grad_x_unclamp_s1_y_1 + 2)", "((grad_x_unclamp_s1_x_x_1*4) + 3)"); + hcompute_grad_x_unclamp_stencil_5->add_load("gray_stencil", "(grad_x_unclamp_s1_y_1 + 1)", "((grad_x_unclamp_s1_x_x_1*4) + 3)"); + hcompute_grad_x_unclamp_stencil_5->add_load("gray_stencil", "grad_x_unclamp_s1_y_1", "((grad_x_unclamp_s1_x_x_1*4) + 1)"); + hcompute_grad_x_unclamp_stencil_5->add_load("gray_stencil", "grad_x_unclamp_s1_y_1", "((grad_x_unclamp_s1_x_x_1*4) + 3)"); + hcompute_grad_x_unclamp_stencil_5->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y_1", "((grad_x_unclamp_s1_x_x_1*4) + 1)"); + + auto grad_x_unclamp_s1_y_2 = prg.add_loop("grad_x_unclamp_s1_y_2", 0, 259); + auto grad_x_unclamp_s1_x_x_2 = grad_x_unclamp_s1_y_2->add_loop("grad_x_unclamp_s1_x_x_2", 0, 75); +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 2), grad_x_unclamp_s1_y) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 2), grad_x_unclamp_s1_y) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 4), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), grad_x_unclamp_s1_y))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 4), grad_x_unclamp_s1_y))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), (grad_x_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 4), (grad_x_unclamp_s1_y + 2)))) + auto hcompute_grad_x_unclamp_stencil_6 = grad_x_unclamp_s1_x_x_2->add_op("op_hcompute_grad_x_unclamp_stencil_6"); + hcompute_grad_x_unclamp_stencil_6->add_function("hcompute_grad_x_unclamp_stencil_6"); + hcompute_grad_x_unclamp_stencil_6->add_load("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y_2", "((grad_x_unclamp_s1_x_x_2*4) + 2)"); + hcompute_grad_x_unclamp_stencil_6->add_load("gray_stencil", "(grad_x_unclamp_s1_y_2 + 1)", "((grad_x_unclamp_s1_x_x_2*4) + 4)"); + hcompute_grad_x_unclamp_stencil_6->add_load("gray_stencil", "grad_x_unclamp_s1_y_2", "((grad_x_unclamp_s1_x_x_2*4) + 2)"); + hcompute_grad_x_unclamp_stencil_6->add_load("gray_stencil", "grad_x_unclamp_s1_y_2", "((grad_x_unclamp_s1_x_x_2*4) + 4)"); + hcompute_grad_x_unclamp_stencil_6->add_load("gray_stencil", "(grad_x_unclamp_s1_y_2 + 1)", "((grad_x_unclamp_s1_x_x_2*4) + 2)"); + hcompute_grad_x_unclamp_stencil_6->add_load("gray_stencil", "(grad_x_unclamp_s1_y_2 + 2)", "((grad_x_unclamp_s1_x_x_2*4) + 2)"); + hcompute_grad_x_unclamp_stencil_6->add_load("gray_stencil", "(grad_x_unclamp_s1_y_2 + 2)", "((grad_x_unclamp_s1_x_x_2*4) + 4)"); + hcompute_grad_x_unclamp_stencil_6->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y_2", "((grad_x_unclamp_s1_x_x_2*4) + 2)"); + + auto grad_x_unclamp_s1_y_3 = prg.add_loop("grad_x_unclamp_s1_y_3", 0, 259); + auto grad_x_unclamp_s1_x_x_3 = grad_x_unclamp_s1_y_3->add_loop("grad_x_unclamp_s1_x_x_3", 0, 75); +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 3), grad_x_unclamp_s1_y) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 3), grad_x_unclamp_s1_y) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 5), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), grad_x_unclamp_s1_y))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 5), grad_x_unclamp_s1_y))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), (grad_x_unclamp_s1_y + 1)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), (grad_x_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 5), (grad_x_unclamp_s1_y + 2)))) + auto hcompute_grad_x_unclamp_stencil_7 = grad_x_unclamp_s1_x_x_3->add_op("op_hcompute_grad_x_unclamp_stencil_7"); + hcompute_grad_x_unclamp_stencil_7->add_function("hcompute_grad_x_unclamp_stencil_7"); + hcompute_grad_x_unclamp_stencil_7->add_load("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y_3", "((grad_x_unclamp_s1_x_x_3*4) + 3)"); + hcompute_grad_x_unclamp_stencil_7->add_load("gray_stencil", "(grad_x_unclamp_s1_y_3 + 1)", "((grad_x_unclamp_s1_x_x_3*4) + 5)"); + hcompute_grad_x_unclamp_stencil_7->add_load("gray_stencil", "grad_x_unclamp_s1_y_3", "((grad_x_unclamp_s1_x_x_3*4) + 3)"); + hcompute_grad_x_unclamp_stencil_7->add_load("gray_stencil", "grad_x_unclamp_s1_y_3", "((grad_x_unclamp_s1_x_x_3*4) + 5)"); + hcompute_grad_x_unclamp_stencil_7->add_load("gray_stencil", "(grad_x_unclamp_s1_y_3 + 1)", "((grad_x_unclamp_s1_x_x_3*4) + 3)"); + hcompute_grad_x_unclamp_stencil_7->add_load("gray_stencil", "(grad_x_unclamp_s1_y_3 + 2)", "((grad_x_unclamp_s1_x_x_3*4) + 3)"); + hcompute_grad_x_unclamp_stencil_7->add_load("gray_stencil", "(grad_x_unclamp_s1_y_3 + 2)", "((grad_x_unclamp_s1_x_x_3*4) + 5)"); + hcompute_grad_x_unclamp_stencil_7->add_store("grad_x_unclamp_stencil", "grad_x_unclamp_s1_y_3", "((grad_x_unclamp_s1_x_x_3*4) + 3)"); + +//consuming grad_x_unclamp.stencil +////producing lxx.stencil + auto lxx_s0_y = prg.add_loop("lxx_s0_y", 0, 259); + auto lxx_s0_x_x = lxx_s0_y->add_loop("lxx_s0_x_x", 0, 75); + +//store is: lxx.stencil((lxx_s0_x_x*4), lxx_s0_y) = ((max(min(grad_x_unclamp.stencil((lxx_s0_x_x*4), lxx_s0_y), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil((lxx_s0_x_x*4), lxx_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxx_stencil = lxx_s0_x_x->add_op("op_hcompute_lxx_stencil"); + hcompute_lxx_stencil->add_function("hcompute_lxx_stencil"); + hcompute_lxx_stencil->add_load("grad_x_unclamp_stencil", "lxx_s0_y", "(lxx_s0_x_x*4)"); + prg.buffer_port_widths["lxx_stencil"] = 16; + hcompute_lxx_stencil->add_store("lxx_stencil", "lxx_s0_y", "(lxx_s0_x_x*4)"); + + auto lxx_s0_y_1 = prg.add_loop("lxx_s0_y_1", 0, 259); + auto lxx_s0_x_x_1 = lxx_s0_y_1->add_loop("lxx_s0_x_x_1", 0, 75); +//store is: lxx.stencil(((lxx_s0_x_x*4) + 1), lxx_s0_y) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 1), lxx_s0_y), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 1), lxx_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxx_stencil_1 = lxx_s0_x_x_1->add_op("op_hcompute_lxx_stencil_1"); + hcompute_lxx_stencil_1->add_function("hcompute_lxx_stencil_1"); + hcompute_lxx_stencil_1->add_load("grad_x_unclamp_stencil", "lxx_s0_y_1", "((lxx_s0_x_x_1*4) + 1)"); + hcompute_lxx_stencil_1->add_store("lxx_stencil", "lxx_s0_y_1", "((lxx_s0_x_x_1*4) + 1)"); + + auto lxx_s0_y_2 = prg.add_loop("lxx_s0_y_2", 0, 259); + auto lxx_s0_x_x_2 = lxx_s0_y_2->add_loop("lxx_s0_x_x_2", 0, 75); +//store is: lxx.stencil(((lxx_s0_x_x*4) + 2), lxx_s0_y) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 2), lxx_s0_y), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 2), lxx_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxx_stencil_2 = lxx_s0_x_x_2->add_op("op_hcompute_lxx_stencil_2"); + hcompute_lxx_stencil_2->add_function("hcompute_lxx_stencil_2"); + hcompute_lxx_stencil_2->add_load("grad_x_unclamp_stencil", "lxx_s0_y_2", "((lxx_s0_x_x_2*4) + 2)"); + hcompute_lxx_stencil_2->add_store("lxx_stencil", "lxx_s0_y_2", "((lxx_s0_x_x_2*4) + 2)"); + + auto lxx_s0_y_3 = prg.add_loop("lxx_s0_y_3", 0, 259); + auto lxx_s0_x_x_3 = lxx_s0_y_3->add_loop("lxx_s0_x_x_3", 0, 75); +//store is: lxx.stencil(((lxx_s0_x_x*4) + 3), lxx_s0_y) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 3), lxx_s0_y), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 3), lxx_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxx_stencil_3 = lxx_s0_x_x_3->add_op("op_hcompute_lxx_stencil_3"); + hcompute_lxx_stencil_3->add_function("hcompute_lxx_stencil_3"); + hcompute_lxx_stencil_3->add_load("grad_x_unclamp_stencil", "lxx_s0_y_3", "((lxx_s0_x_x_3*4) + 3)"); + hcompute_lxx_stencil_3->add_store("lxx_stencil", "lxx_s0_y_3", "((lxx_s0_x_x_3*4) + 3)"); + +//consuming lxx.stencil +////producing lgxx.stencil + auto lgxx_s0_y = prg.add_loop("lgxx_s0_y", 0, 257); + auto lgxx_s0_x_x = lgxx_s0_y->add_loop("lgxx_s0_x_x", 0, 75); + +//store is: lgxx.stencil((lgxx_s0_x_x*4), lgxx_s0_y) = (int16)0 + auto hcompute_lgxx_stencil = lgxx_s0_x_x->add_op("op_hcompute_lgxx_stencil"); + hcompute_lgxx_stencil->add_function("hcompute_lgxx_stencil"); + prg.buffer_port_widths["lgxx_stencil"] = 16; + hcompute_lgxx_stencil->add_store("lgxx_stencil", "lgxx_s0_y", "(lgxx_s0_x_x*4)"); + +//store is: lgxx.stencil(((lgxx_s0_x_x*4) + 1), lgxx_s0_y) = (int16)0 + auto hcompute_lgxx_stencil_1 = lgxx_s0_x_x->add_op("op_hcompute_lgxx_stencil_1"); + hcompute_lgxx_stencil_1->add_function("hcompute_lgxx_stencil_1"); + hcompute_lgxx_stencil_1->add_store("lgxx_stencil", "lgxx_s0_y", "((lgxx_s0_x_x*4) + 1)"); + +//store is: lgxx.stencil(((lgxx_s0_x_x*4) + 2), lgxx_s0_y) = (int16)0 + auto hcompute_lgxx_stencil_2 = lgxx_s0_x_x->add_op("op_hcompute_lgxx_stencil_2"); + hcompute_lgxx_stencil_2->add_function("hcompute_lgxx_stencil_2"); + hcompute_lgxx_stencil_2->add_store("lgxx_stencil", "lgxx_s0_y", "((lgxx_s0_x_x*4) + 2)"); + +//store is: lgxx.stencil(((lgxx_s0_x_x*4) + 3), lgxx_s0_y) = (int16)0 + auto hcompute_lgxx_stencil_3 = lgxx_s0_x_x->add_op("op_hcompute_lgxx_stencil_3"); + hcompute_lgxx_stencil_3->add_function("hcompute_lgxx_stencil_3"); + hcompute_lgxx_stencil_3->add_store("lgxx_stencil", "lgxx_s0_y", "((lgxx_s0_x_x*4) + 3)"); + auto lgxx_s1_y = prg.add_loop("lgxx_s1_y", 0, 257); + auto lgxx_s1_x_x = lgxx_s1_y->add_loop("lgxx_s1_x_x", 0, 75); + +//store is: lgxx.stencil((lgxx_s1_x_x*4), lgxx_s1_y) = (lxx.stencil((lgxx_s1_x_x*4), lgxx_s1_y) + (lgxx.stencil((lgxx_s1_x_x*4), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), lgxx_s1_y) + (lxx.stencil((lgxx_s1_x_x*4), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), (lgxx_s1_y + 1)) + (lxx.stencil((lgxx_s1_x_x*4), (lgxx_s1_y + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), (lgxx_s1_y + 2)) + lxx.stencil(((lgxx_s1_x_x*4) + 1), (lgxx_s1_y + 2))))))))))) + auto hcompute_lgxx_stencil_4 = lgxx_s1_x_x->add_op("op_hcompute_lgxx_stencil_4"); + hcompute_lgxx_stencil_4->add_function("hcompute_lgxx_stencil_4"); + hcompute_lgxx_stencil_4->add_load("lgxx_stencil", "lgxx_s1_y", "(lgxx_s1_x_x*4)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "lgxx_s1_y", "(lgxx_s1_x_x*4)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 1)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "(lgxx_s1_x_x*4)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 1)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "(lgxx_s1_x_x*4)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_4->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 1)"); + hcompute_lgxx_stencil_4->add_store("lgxx_stencil", "lgxx_s1_y", "(lgxx_s1_x_x*4)"); + +//store is: lgxx.stencil(((lgxx_s1_x_x*4) + 1), lgxx_s1_y) = (lxx.stencil(((lgxx_s1_x_x*4) + 1), lgxx_s1_y) + (lgxx.stencil(((lgxx_s1_x_x*4) + 1), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), (lgxx_s1_y + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), (lgxx_s1_y + 2)) + lxx.stencil(((lgxx_s1_x_x*4) + 2), (lgxx_s1_y + 2))))))))))) + auto hcompute_lgxx_stencil_5 = lgxx_s1_x_x->add_op("op_hcompute_lgxx_stencil_5"); + hcompute_lgxx_stencil_5->add_function("hcompute_lgxx_stencil_5"); + hcompute_lgxx_stencil_5->add_load("lgxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 1)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 1)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 1)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 1)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_5->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_5->add_store("lgxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 1)"); + +//store is: lgxx.stencil(((lgxx_s1_x_x*4) + 2), lgxx_s1_y) = (lxx.stencil(((lgxx_s1_x_x*4) + 2), lgxx_s1_y) + (lgxx.stencil(((lgxx_s1_x_x*4) + 2), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), (lgxx_s1_y + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), (lgxx_s1_y + 2)) + lxx.stencil(((lgxx_s1_x_x*4) + 3), (lgxx_s1_y + 2))))))))))) + auto hcompute_lgxx_stencil_6 = lgxx_s1_x_x->add_op("op_hcompute_lgxx_stencil_6"); + hcompute_lgxx_stencil_6->add_function("hcompute_lgxx_stencil_6"); + hcompute_lgxx_stencil_6->add_load("lgxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 4)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 4)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 2)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 4)"); + hcompute_lgxx_stencil_6->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_6->add_store("lgxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 2)"); + +//store is: lgxx.stencil(((lgxx_s1_x_x*4) + 3), lgxx_s1_y) = (lxx.stencil(((lgxx_s1_x_x*4) + 3), lgxx_s1_y) + (lgxx.stencil(((lgxx_s1_x_x*4) + 3), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 5), lgxx_s1_y) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 5), (lgxx_s1_y + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), (lgxx_s1_y + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 5), (lgxx_s1_y + 2)) + lxx.stencil(((lgxx_s1_x_x*4) + 4), (lgxx_s1_y + 2))))))))))) + auto hcompute_lgxx_stencil_7 = lgxx_s1_x_x->add_op("op_hcompute_lgxx_stencil_7"); + hcompute_lgxx_stencil_7->add_function("hcompute_lgxx_stencil_7"); + hcompute_lgxx_stencil_7->add_load("lgxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 4)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 5)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 4)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "(lgxx_s1_y + 1)", "((lgxx_s1_x_x*4) + 5)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 3)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 5)"); + hcompute_lgxx_stencil_7->add_load("lxx_stencil", "(lgxx_s1_y + 2)", "((lgxx_s1_x_x*4) + 4)"); + hcompute_lgxx_stencil_7->add_store("lgxx_stencil", "lgxx_s1_y", "((lgxx_s1_x_x*4) + 3)"); + +//consuming lgxx.stencil +////producing grad_y_unclamp.stencil + auto grad_y_unclamp_s0_y = prg.add_loop("grad_y_unclamp_s0_y", 0, 259); + auto grad_y_unclamp_s0_x_x = grad_y_unclamp_s0_y->add_loop("grad_y_unclamp_s0_x_x", 0, 75); + +//store is: grad_y_unclamp.stencil((grad_y_unclamp_s0_x_x*4), grad_y_unclamp_s0_y) = (int16)0 + auto hcompute_grad_y_unclamp_stencil = grad_y_unclamp_s0_x_x->add_op("op_hcompute_grad_y_unclamp_stencil"); + hcompute_grad_y_unclamp_stencil->add_function("hcompute_grad_y_unclamp_stencil"); + prg.buffer_port_widths["grad_y_unclamp_stencil"] = 16; + hcompute_grad_y_unclamp_stencil->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s0_y", "(grad_y_unclamp_s0_x_x*4)"); + + auto grad_y_unclamp_s0_y_1 = prg.add_loop("grad_y_unclamp_s0_y_1", 0, 259); + auto grad_y_unclamp_s0_x_x_1 = grad_y_unclamp_s0_y_1->add_loop("grad_y_unclamp_s0_x_x_1", 0, 75); +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x*4) + 1), grad_y_unclamp_s0_y) = (int16)0 + auto hcompute_grad_y_unclamp_stencil_1 = grad_y_unclamp_s0_x_x_1->add_op("op_hcompute_grad_y_unclamp_stencil_1"); + hcompute_grad_y_unclamp_stencil_1->add_function("hcompute_grad_y_unclamp_stencil_1"); + hcompute_grad_y_unclamp_stencil_1->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s0_y_1", "((grad_y_unclamp_s0_x_x_1*4) + 1)"); + + auto grad_y_unclamp_s0_y_2 = prg.add_loop("grad_y_unclamp_s0_y_2", 0, 259); + auto grad_y_unclamp_s0_x_x_2 = grad_y_unclamp_s0_y_2->add_loop("grad_y_unclamp_s0_x_x_2", 0, 75); +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x*4) + 2), grad_y_unclamp_s0_y) = (int16)0 + auto hcompute_grad_y_unclamp_stencil_2 = grad_y_unclamp_s0_x_x_2->add_op("op_hcompute_grad_y_unclamp_stencil_2"); + hcompute_grad_y_unclamp_stencil_2->add_function("hcompute_grad_y_unclamp_stencil_2"); + hcompute_grad_y_unclamp_stencil_2->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s0_y_2", "((grad_y_unclamp_s0_x_x_2*4) + 2)"); + + auto grad_y_unclamp_s0_y_3 = prg.add_loop("grad_y_unclamp_s0_y_3", 0, 259); + auto grad_y_unclamp_s0_x_x_3 = grad_y_unclamp_s0_y_3->add_loop("grad_y_unclamp_s0_x_x_3", 0, 75); +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x*4) + 3), grad_y_unclamp_s0_y) = (int16)0 + auto hcompute_grad_y_unclamp_stencil_3 = grad_y_unclamp_s0_x_x_3->add_op("op_hcompute_grad_y_unclamp_stencil_3"); + hcompute_grad_y_unclamp_stencil_3->add_function("hcompute_grad_y_unclamp_stencil_3"); + hcompute_grad_y_unclamp_stencil_3->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s0_y_3", "((grad_y_unclamp_s0_x_x_3*4) + 3)"); + auto grad_y_unclamp_s1_y = prg.add_loop("grad_y_unclamp_s1_y", 0, 259); + auto grad_y_unclamp_s1_x_x = grad_y_unclamp_s1_y->add_loop("grad_y_unclamp_s1_x_x", 0, 75); + +//store is: grad_y_unclamp.stencil((grad_y_unclamp_s1_x_x*4), grad_y_unclamp_s1_y) = ((((((grad_y_unclamp.stencil((grad_y_unclamp_s1_x_x*4), grad_y_unclamp_s1_y) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), (grad_y_unclamp_s1_y + 2)))*(int16)2)) - int16(gray.stencil((grad_y_unclamp_s1_x_x*4), grad_y_unclamp_s1_y))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), grad_y_unclamp_s1_y))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), grad_y_unclamp_s1_y))) + int16(gray.stencil((grad_y_unclamp_s1_x_x*4), (grad_y_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), (grad_y_unclamp_s1_y + 2)))) + auto hcompute_grad_y_unclamp_stencil_4 = grad_y_unclamp_s1_x_x->add_op("op_hcompute_grad_y_unclamp_stencil_4"); + hcompute_grad_y_unclamp_stencil_4->add_function("hcompute_grad_y_unclamp_stencil_4"); + hcompute_grad_y_unclamp_stencil_4->add_load("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y", "(grad_y_unclamp_s1_x_x*4)"); + hcompute_grad_y_unclamp_stencil_4->add_load("gray_stencil", "(grad_y_unclamp_s1_y + 2)", "((grad_y_unclamp_s1_x_x*4) + 1)"); + hcompute_grad_y_unclamp_stencil_4->add_load("gray_stencil", "grad_y_unclamp_s1_y", "(grad_y_unclamp_s1_x_x*4)"); + hcompute_grad_y_unclamp_stencil_4->add_load("gray_stencil", "grad_y_unclamp_s1_y", "((grad_y_unclamp_s1_x_x*4) + 1)"); + hcompute_grad_y_unclamp_stencil_4->add_load("gray_stencil", "grad_y_unclamp_s1_y", "((grad_y_unclamp_s1_x_x*4) + 2)"); + hcompute_grad_y_unclamp_stencil_4->add_load("gray_stencil", "(grad_y_unclamp_s1_y + 2)", "(grad_y_unclamp_s1_x_x*4)"); + hcompute_grad_y_unclamp_stencil_4->add_load("gray_stencil", "(grad_y_unclamp_s1_y + 2)", "((grad_y_unclamp_s1_x_x*4) + 2)"); + hcompute_grad_y_unclamp_stencil_4->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y", "(grad_y_unclamp_s1_x_x*4)"); + + auto grad_y_unclamp_s1_y_1 = prg.add_loop("grad_y_unclamp_s1_y_1", 0, 259); + auto grad_y_unclamp_s1_x_x_1 = grad_y_unclamp_s1_y_1->add_loop("grad_y_unclamp_s1_x_x_1", 0, 75); +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 1), grad_y_unclamp_s1_y) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 1), grad_y_unclamp_s1_y) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), (grad_y_unclamp_s1_y + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), grad_y_unclamp_s1_y))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), grad_y_unclamp_s1_y))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), grad_y_unclamp_s1_y))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), (grad_y_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), (grad_y_unclamp_s1_y + 2)))) + auto hcompute_grad_y_unclamp_stencil_5 = grad_y_unclamp_s1_x_x_1->add_op("op_hcompute_grad_y_unclamp_stencil_5"); + hcompute_grad_y_unclamp_stencil_5->add_function("hcompute_grad_y_unclamp_stencil_5"); + hcompute_grad_y_unclamp_stencil_5->add_load("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y_1", "((grad_y_unclamp_s1_x_x_1*4) + 1)"); + hcompute_grad_y_unclamp_stencil_5->add_load("gray_stencil", "(grad_y_unclamp_s1_y_1 + 2)", "((grad_y_unclamp_s1_x_x_1*4) + 2)"); + hcompute_grad_y_unclamp_stencil_5->add_load("gray_stencil", "grad_y_unclamp_s1_y_1", "((grad_y_unclamp_s1_x_x_1*4) + 1)"); + hcompute_grad_y_unclamp_stencil_5->add_load("gray_stencil", "grad_y_unclamp_s1_y_1", "((grad_y_unclamp_s1_x_x_1*4) + 2)"); + hcompute_grad_y_unclamp_stencil_5->add_load("gray_stencil", "grad_y_unclamp_s1_y_1", "((grad_y_unclamp_s1_x_x_1*4) + 3)"); + hcompute_grad_y_unclamp_stencil_5->add_load("gray_stencil", "(grad_y_unclamp_s1_y_1 + 2)", "((grad_y_unclamp_s1_x_x_1*4) + 1)"); + hcompute_grad_y_unclamp_stencil_5->add_load("gray_stencil", "(grad_y_unclamp_s1_y_1 + 2)", "((grad_y_unclamp_s1_x_x_1*4) + 3)"); + hcompute_grad_y_unclamp_stencil_5->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y_1", "((grad_y_unclamp_s1_x_x_1*4) + 1)"); + + + auto grad_y_unclamp_s1_y_2 = prg.add_loop("grad_y_unclamp_s1_y_2", 0, 259); + auto grad_y_unclamp_s1_x_x_2 = grad_y_unclamp_s1_y_2->add_loop("grad_y_unclamp_s1_x_x_2", 0, 75); +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 2), grad_y_unclamp_s1_y) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 2), grad_y_unclamp_s1_y) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), (grad_y_unclamp_s1_y + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), grad_y_unclamp_s1_y))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), grad_y_unclamp_s1_y))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), grad_y_unclamp_s1_y))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), (grad_y_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), (grad_y_unclamp_s1_y + 2)))) + auto hcompute_grad_y_unclamp_stencil_6 = grad_y_unclamp_s1_x_x_2->add_op("op_hcompute_grad_y_unclamp_stencil_6"); + hcompute_grad_y_unclamp_stencil_6->add_function("hcompute_grad_y_unclamp_stencil_6"); + hcompute_grad_y_unclamp_stencil_6->add_load("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y_2", "((grad_y_unclamp_s1_x_x_2*4) + 2)"); + hcompute_grad_y_unclamp_stencil_6->add_load("gray_stencil", "(grad_y_unclamp_s1_y_2 + 2)", "((grad_y_unclamp_s1_x_x_2*4) + 3)"); + hcompute_grad_y_unclamp_stencil_6->add_load("gray_stencil", "grad_y_unclamp_s1_y_2", "((grad_y_unclamp_s1_x_x_2*4) + 2)"); + hcompute_grad_y_unclamp_stencil_6->add_load("gray_stencil", "grad_y_unclamp_s1_y_2", "((grad_y_unclamp_s1_x_x_2*4) + 3)"); + hcompute_grad_y_unclamp_stencil_6->add_load("gray_stencil", "grad_y_unclamp_s1_y_2", "((grad_y_unclamp_s1_x_x_2*4) + 4)"); + hcompute_grad_y_unclamp_stencil_6->add_load("gray_stencil", "(grad_y_unclamp_s1_y_2 + 2)", "((grad_y_unclamp_s1_x_x_2*4) + 2)"); + hcompute_grad_y_unclamp_stencil_6->add_load("gray_stencil", "(grad_y_unclamp_s1_y_2 + 2)", "((grad_y_unclamp_s1_x_x_2*4) + 4)"); + hcompute_grad_y_unclamp_stencil_6->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y_2", "((grad_y_unclamp_s1_x_x_2*4) + 2)"); + + + auto grad_y_unclamp_s1_y_3 = prg.add_loop("grad_y_unclamp_s1_y_3", 0, 259); + auto grad_y_unclamp_s1_x_x_3 = grad_y_unclamp_s1_y_3->add_loop("grad_y_unclamp_s1_x_x_3", 0, 75); +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 3), grad_y_unclamp_s1_y) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 3), grad_y_unclamp_s1_y) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), (grad_y_unclamp_s1_y + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), grad_y_unclamp_s1_y))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), grad_y_unclamp_s1_y))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 5), grad_y_unclamp_s1_y))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), (grad_y_unclamp_s1_y + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 5), (grad_y_unclamp_s1_y + 2)))) + auto hcompute_grad_y_unclamp_stencil_7 = grad_y_unclamp_s1_x_x_3->add_op("op_hcompute_grad_y_unclamp_stencil_7"); + hcompute_grad_y_unclamp_stencil_7->add_function("hcompute_grad_y_unclamp_stencil_7"); + hcompute_grad_y_unclamp_stencil_7->add_load("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y_3", "((grad_y_unclamp_s1_x_x_3*4) + 3)"); + hcompute_grad_y_unclamp_stencil_7->add_load("gray_stencil", "(grad_y_unclamp_s1_y_3 + 2)", "((grad_y_unclamp_s1_x_x_3*4) + 4)"); + hcompute_grad_y_unclamp_stencil_7->add_load("gray_stencil", "grad_y_unclamp_s1_y_3", "((grad_y_unclamp_s1_x_x_3*4) + 3)"); + hcompute_grad_y_unclamp_stencil_7->add_load("gray_stencil", "grad_y_unclamp_s1_y_3", "((grad_y_unclamp_s1_x_x_3*4) + 4)"); + hcompute_grad_y_unclamp_stencil_7->add_load("gray_stencil", "grad_y_unclamp_s1_y_3", "((grad_y_unclamp_s1_x_x_3*4) + 5)"); + hcompute_grad_y_unclamp_stencil_7->add_load("gray_stencil", "(grad_y_unclamp_s1_y_3 + 2)", "((grad_y_unclamp_s1_x_x_3*4) + 3)"); + hcompute_grad_y_unclamp_stencil_7->add_load("gray_stencil", "(grad_y_unclamp_s1_y_3 + 2)", "((grad_y_unclamp_s1_x_x_3*4) + 5)"); + hcompute_grad_y_unclamp_stencil_7->add_store("grad_y_unclamp_stencil", "grad_y_unclamp_s1_y_3", "((grad_y_unclamp_s1_x_x_3*4) + 3)"); + +//consuming grad_y_unclamp.stencil +////producing lxy.stencil + auto lxy_s0_y = prg.add_loop("lxy_s0_y", 0, 259); + auto lxy_s0_x_x = lxy_s0_y->add_loop("lxy_s0_x_x", 0, 75); + +//store is: lxy.stencil((lxy_s0_x_x*4), lxy_s0_y) = ((max(min(grad_x_unclamp.stencil((lxy_s0_x_x*4), lxy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil((lxy_s0_x_x*4), lxy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxy_stencil = lxy_s0_x_x->add_op("op_hcompute_lxy_stencil"); + hcompute_lxy_stencil->add_function("hcompute_lxy_stencil"); + hcompute_lxy_stencil->add_load("grad_x_unclamp_stencil", "lxy_s0_y", "(lxy_s0_x_x*4)"); + hcompute_lxy_stencil->add_load("grad_y_unclamp_stencil", "lxy_s0_y", "(lxy_s0_x_x*4)"); + prg.buffer_port_widths["lxy_stencil"] = 16; + hcompute_lxy_stencil->add_store("lxy_stencil", "lxy_s0_y", "(lxy_s0_x_x*4)"); + + auto lxy_s0_y_1 = prg.add_loop("lxy_s0_y_1", 0, 259); + auto lxy_s0_x_x_1 = lxy_s0_y_1->add_loop("lxy_s0_x_x_1", 0, 75); + +//store is: lxy.stencil(((lxy_s0_x_x*4) + 1), lxy_s0_y) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x*4) + 1), lxy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x*4) + 1), lxy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxy_stencil_1 = lxy_s0_x_x_1->add_op("op_hcompute_lxy_stencil_1"); + hcompute_lxy_stencil_1->add_function("hcompute_lxy_stencil_1"); + hcompute_lxy_stencil_1->add_load("grad_x_unclamp_stencil", "lxy_s0_y_1", "((lxy_s0_x_x_1*4) + 1)"); + hcompute_lxy_stencil_1->add_load("grad_y_unclamp_stencil", "lxy_s0_y_1", "((lxy_s0_x_x_1*4) + 1)"); + hcompute_lxy_stencil_1->add_store("lxy_stencil", "lxy_s0_y_1", "((lxy_s0_x_x_1*4) + 1)"); + + auto lxy_s0_y_2 = prg.add_loop("lxy_s0_y_2", 0, 259); + auto lxy_s0_x_x_2 = lxy_s0_y_2->add_loop("lxy_s0_x_x_2", 0, 75); +//store is: lxy.stencil(((lxy_s0_x_x*4) + 2), lxy_s0_y) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x*4) + 2), lxy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x*4) + 2), lxy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxy_stencil_2 = lxy_s0_x_x_2->add_op("op_hcompute_lxy_stencil_2"); + hcompute_lxy_stencil_2->add_function("hcompute_lxy_stencil_2"); + hcompute_lxy_stencil_2->add_load("grad_x_unclamp_stencil", "lxy_s0_y_2", "((lxy_s0_x_x_2*4) + 2)"); + hcompute_lxy_stencil_2->add_load("grad_y_unclamp_stencil", "lxy_s0_y_2", "((lxy_s0_x_x_2*4) + 2)"); + hcompute_lxy_stencil_2->add_store("lxy_stencil", "lxy_s0_y_2", "((lxy_s0_x_x_2*4) + 2)"); + + auto lxy_s0_y_3 = prg.add_loop("lxy_s0_y_3", 0, 259); + auto lxy_s0_x_x_3 = lxy_s0_y_3->add_loop("lxy_s0_x_x_3", 0, 75); +//store is: lxy.stencil(((lxy_s0_x_x*4) + 3), lxy_s0_y) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x*4) + 3), lxy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x*4) + 3), lxy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lxy_stencil_3 = lxy_s0_x_x_3->add_op("op_hcompute_lxy_stencil_3"); + hcompute_lxy_stencil_3->add_function("hcompute_lxy_stencil_3"); + hcompute_lxy_stencil_3->add_load("grad_x_unclamp_stencil", "lxy_s0_y_3", "((lxy_s0_x_x_3*4) + 3)"); + hcompute_lxy_stencil_3->add_load("grad_y_unclamp_stencil", "lxy_s0_y_3", "((lxy_s0_x_x_3*4) + 3)"); + hcompute_lxy_stencil_3->add_store("lxy_stencil", "lxy_s0_y_3", "((lxy_s0_x_x_3*4) + 3)"); + +//consuming lxy.stencil +////producing lgxy.stencil + auto lgxy_s0_y = prg.add_loop("lgxy_s0_y", 0, 257); + auto lgxy_s0_x_x = lgxy_s0_y->add_loop("lgxy_s0_x_x", 0, 75); + +//store is: lgxy.stencil((lgxy_s0_x_x*4), lgxy_s0_y) = (int16)0 + auto hcompute_lgxy_stencil = lgxy_s0_x_x->add_op("op_hcompute_lgxy_stencil"); + hcompute_lgxy_stencil->add_function("hcompute_lgxy_stencil"); + prg.buffer_port_widths["lgxy_stencil"] = 16; + hcompute_lgxy_stencil->add_store("lgxy_stencil", "lgxy_s0_y", "(lgxy_s0_x_x*4)"); + +//store is: lgxy.stencil(((lgxy_s0_x_x*4) + 1), lgxy_s0_y) = (int16)0 + auto hcompute_lgxy_stencil_1 = lgxy_s0_x_x->add_op("op_hcompute_lgxy_stencil_1"); + hcompute_lgxy_stencil_1->add_function("hcompute_lgxy_stencil_1"); + hcompute_lgxy_stencil_1->add_store("lgxy_stencil", "lgxy_s0_y", "((lgxy_s0_x_x*4) + 1)"); + +//store is: lgxy.stencil(((lgxy_s0_x_x*4) + 2), lgxy_s0_y) = (int16)0 + auto hcompute_lgxy_stencil_2 = lgxy_s0_x_x->add_op("op_hcompute_lgxy_stencil_2"); + hcompute_lgxy_stencil_2->add_function("hcompute_lgxy_stencil_2"); + hcompute_lgxy_stencil_2->add_store("lgxy_stencil", "lgxy_s0_y", "((lgxy_s0_x_x*4) + 2)"); + +//store is: lgxy.stencil(((lgxy_s0_x_x*4) + 3), lgxy_s0_y) = (int16)0 + auto hcompute_lgxy_stencil_3 = lgxy_s0_x_x->add_op("op_hcompute_lgxy_stencil_3"); + hcompute_lgxy_stencil_3->add_function("hcompute_lgxy_stencil_3"); + hcompute_lgxy_stencil_3->add_store("lgxy_stencil", "lgxy_s0_y", "((lgxy_s0_x_x*4) + 3)"); + auto lgxy_s1_y = prg.add_loop("lgxy_s1_y", 0, 257); + auto lgxy_s1_x_x = lgxy_s1_y->add_loop("lgxy_s1_x_x", 0, 75); + +//store is: lgxy.stencil((lgxy_s1_x_x*4), lgxy_s1_y) = (lxy.stencil((lgxy_s1_x_x*4), lgxy_s1_y) + (lgxy.stencil((lgxy_s1_x_x*4), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), lgxy_s1_y) + (lxy.stencil((lgxy_s1_x_x*4), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), (lgxy_s1_y + 1)) + (lxy.stencil((lgxy_s1_x_x*4), (lgxy_s1_y + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), (lgxy_s1_y + 2)) + lxy.stencil(((lgxy_s1_x_x*4) + 1), (lgxy_s1_y + 2))))))))))) + auto hcompute_lgxy_stencil_4 = lgxy_s1_x_x->add_op("op_hcompute_lgxy_stencil_4"); + hcompute_lgxy_stencil_4->add_function("hcompute_lgxy_stencil_4"); + hcompute_lgxy_stencil_4->add_load("lgxy_stencil", "lgxy_s1_y", "(lgxy_s1_x_x*4)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "lgxy_s1_y", "(lgxy_s1_x_x*4)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 1)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "(lgxy_s1_x_x*4)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 1)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "(lgxy_s1_x_x*4)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_4->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 1)"); + hcompute_lgxy_stencil_4->add_store("lgxy_stencil", "lgxy_s1_y", "(lgxy_s1_x_x*4)"); + +//store is: lgxy.stencil(((lgxy_s1_x_x*4) + 1), lgxy_s1_y) = (lxy.stencil(((lgxy_s1_x_x*4) + 1), lgxy_s1_y) + (lgxy.stencil(((lgxy_s1_x_x*4) + 1), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), (lgxy_s1_y + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), (lgxy_s1_y + 2)) + lxy.stencil(((lgxy_s1_x_x*4) + 2), (lgxy_s1_y + 2))))))))))) + auto hcompute_lgxy_stencil_5 = lgxy_s1_x_x->add_op("op_hcompute_lgxy_stencil_5"); + hcompute_lgxy_stencil_5->add_function("hcompute_lgxy_stencil_5"); + hcompute_lgxy_stencil_5->add_load("lgxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 1)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 1)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 1)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 1)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_5->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_5->add_store("lgxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 1)"); + +//store is: lgxy.stencil(((lgxy_s1_x_x*4) + 2), lgxy_s1_y) = (lxy.stencil(((lgxy_s1_x_x*4) + 2), lgxy_s1_y) + (lgxy.stencil(((lgxy_s1_x_x*4) + 2), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), (lgxy_s1_y + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), (lgxy_s1_y + 2)) + lxy.stencil(((lgxy_s1_x_x*4) + 3), (lgxy_s1_y + 2))))))))))) + auto hcompute_lgxy_stencil_6 = lgxy_s1_x_x->add_op("op_hcompute_lgxy_stencil_6"); + hcompute_lgxy_stencil_6->add_function("hcompute_lgxy_stencil_6"); + hcompute_lgxy_stencil_6->add_load("lgxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 4)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 4)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 2)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 4)"); + hcompute_lgxy_stencil_6->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_6->add_store("lgxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 2)"); + +//store is: lgxy.stencil(((lgxy_s1_x_x*4) + 3), lgxy_s1_y) = (lxy.stencil(((lgxy_s1_x_x*4) + 3), lgxy_s1_y) + (lgxy.stencil(((lgxy_s1_x_x*4) + 3), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 5), lgxy_s1_y) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 5), (lgxy_s1_y + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), (lgxy_s1_y + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 5), (lgxy_s1_y + 2)) + lxy.stencil(((lgxy_s1_x_x*4) + 4), (lgxy_s1_y + 2))))))))))) + auto hcompute_lgxy_stencil_7 = lgxy_s1_x_x->add_op("op_hcompute_lgxy_stencil_7"); + hcompute_lgxy_stencil_7->add_function("hcompute_lgxy_stencil_7"); + hcompute_lgxy_stencil_7->add_load("lgxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 4)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 5)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 4)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "(lgxy_s1_y + 1)", "((lgxy_s1_x_x*4) + 5)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 3)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 5)"); + hcompute_lgxy_stencil_7->add_load("lxy_stencil", "(lgxy_s1_y + 2)", "((lgxy_s1_x_x*4) + 4)"); + hcompute_lgxy_stencil_7->add_store("lgxy_stencil", "lgxy_s1_y", "((lgxy_s1_x_x*4) + 3)"); + +//consuming lgxy.stencil +////producing lyy.stencil + auto lyy_s0_y = prg.add_loop("lyy_s0_y", 0, 259); + auto lyy_s0_x_x = lyy_s0_y->add_loop("lyy_s0_x_x", 0, 75); + +//store is: lyy.stencil((lyy_s0_x_x*4), lyy_s0_y) = ((max(min(grad_y_unclamp.stencil((lyy_s0_x_x*4), lyy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil((lyy_s0_x_x*4), lyy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lyy_stencil = lyy_s0_x_x->add_op("op_hcompute_lyy_stencil"); + hcompute_lyy_stencil->add_function("hcompute_lyy_stencil"); + hcompute_lyy_stencil->add_load("grad_y_unclamp_stencil", "lyy_s0_y", "(lyy_s0_x_x*4)"); + prg.buffer_port_widths["lyy_stencil"] = 16; + hcompute_lyy_stencil->add_store("lyy_stencil", "lyy_s0_y", "(lyy_s0_x_x*4)"); + + auto lyy_s0_y_1 = prg.add_loop("lyy_s0_y_1", 0, 259); + auto lyy_s0_x_x_1 = lyy_s0_y_1->add_loop("lyy_s0_x_x_1", 0, 75); +//store is: lyy.stencil(((lyy_s0_x_x*4) + 1), lyy_s0_y) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 1), lyy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 1), lyy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lyy_stencil_1 = lyy_s0_x_x_1->add_op("op_hcompute_lyy_stencil_1"); + hcompute_lyy_stencil_1->add_function("hcompute_lyy_stencil_1"); + hcompute_lyy_stencil_1->add_load("grad_y_unclamp_stencil", "lyy_s0_y_1", "((lyy_s0_x_x_1*4) + 1)"); + hcompute_lyy_stencil_1->add_store("lyy_stencil", "lyy_s0_y_1", "((lyy_s0_x_x_1*4) + 1)"); + + auto lyy_s0_y_2 = prg.add_loop("lyy_s0_y_2", 0, 259); + auto lyy_s0_x_x_2 = lyy_s0_y_2->add_loop("lyy_s0_x_x_2", 0, 75); +//store is: lyy.stencil(((lyy_s0_x_x*4) + 2), lyy_s0_y) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 2), lyy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 2), lyy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lyy_stencil_2 = lyy_s0_x_x_2->add_op("op_hcompute_lyy_stencil_2"); + hcompute_lyy_stencil_2->add_function("hcompute_lyy_stencil_2"); + hcompute_lyy_stencil_2->add_load("grad_y_unclamp_stencil", "lyy_s0_y_2", "((lyy_s0_x_x_2*4) + 2)"); + hcompute_lyy_stencil_2->add_store("lyy_stencil", "lyy_s0_y_2", "((lyy_s0_x_x_2*4) + 2)"); + + auto lyy_s0_y_3 = prg.add_loop("lyy_s0_y_3", 0, 259); + auto lyy_s0_x_x_3 = lyy_s0_y_3->add_loop("lyy_s0_x_x_3", 0, 75); +//store is: lyy.stencil(((lyy_s0_x_x*4) + 3), lyy_s0_y) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 3), lyy_s0_y), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 3), lyy_s0_y), (int16)180), (int16)-180))/(int16)64) + auto hcompute_lyy_stencil_3 = lyy_s0_x_x_3->add_op("op_hcompute_lyy_stencil_3"); + hcompute_lyy_stencil_3->add_function("hcompute_lyy_stencil_3"); + hcompute_lyy_stencil_3->add_load("grad_y_unclamp_stencil", "lyy_s0_y_3", "((lyy_s0_x_x_3*4) + 3)"); + hcompute_lyy_stencil_3->add_store("lyy_stencil", "lyy_s0_y_3", "((lyy_s0_x_x_3*4) + 3)"); + +//consuming lyy.stencil +////producing lgyy.stencil + auto lgyy_s0_y = prg.add_loop("lgyy_s0_y", 0, 257); + auto lgyy_s0_x_x = lgyy_s0_y->add_loop("lgyy_s0_x_x", 0, 75); + +//store is: lgyy.stencil((lgyy_s0_x_x*4), lgyy_s0_y) = (int16)0 + auto hcompute_lgyy_stencil = lgyy_s0_x_x->add_op("op_hcompute_lgyy_stencil"); + hcompute_lgyy_stencil->add_function("hcompute_lgyy_stencil"); + prg.buffer_port_widths["lgyy_stencil"] = 16; + hcompute_lgyy_stencil->add_store("lgyy_stencil", "lgyy_s0_y", "(lgyy_s0_x_x*4)"); + +//store is: lgyy.stencil(((lgyy_s0_x_x*4) + 1), lgyy_s0_y) = (int16)0 + auto hcompute_lgyy_stencil_1 = lgyy_s0_x_x->add_op("op_hcompute_lgyy_stencil_1"); + hcompute_lgyy_stencil_1->add_function("hcompute_lgyy_stencil_1"); + hcompute_lgyy_stencil_1->add_store("lgyy_stencil", "lgyy_s0_y", "((lgyy_s0_x_x*4) + 1)"); + +//store is: lgyy.stencil(((lgyy_s0_x_x*4) + 2), lgyy_s0_y) = (int16)0 + auto hcompute_lgyy_stencil_2 = lgyy_s0_x_x->add_op("op_hcompute_lgyy_stencil_2"); + hcompute_lgyy_stencil_2->add_function("hcompute_lgyy_stencil_2"); + hcompute_lgyy_stencil_2->add_store("lgyy_stencil", "lgyy_s0_y", "((lgyy_s0_x_x*4) + 2)"); + +//store is: lgyy.stencil(((lgyy_s0_x_x*4) + 3), lgyy_s0_y) = (int16)0 + auto hcompute_lgyy_stencil_3 = lgyy_s0_x_x->add_op("op_hcompute_lgyy_stencil_3"); + hcompute_lgyy_stencil_3->add_function("hcompute_lgyy_stencil_3"); + hcompute_lgyy_stencil_3->add_store("lgyy_stencil", "lgyy_s0_y", "((lgyy_s0_x_x*4) + 3)"); + auto lgyy_s1_y = prg.add_loop("lgyy_s1_y", 0, 257); + auto lgyy_s1_x_x = lgyy_s1_y->add_loop("lgyy_s1_x_x", 0, 75); + +//store is: lgyy.stencil((lgyy_s1_x_x*4), lgyy_s1_y) = (lyy.stencil((lgyy_s1_x_x*4), lgyy_s1_y) + (lgyy.stencil((lgyy_s1_x_x*4), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), lgyy_s1_y) + (lyy.stencil((lgyy_s1_x_x*4), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), (lgyy_s1_y + 1)) + (lyy.stencil((lgyy_s1_x_x*4), (lgyy_s1_y + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), (lgyy_s1_y + 2)) + lyy.stencil(((lgyy_s1_x_x*4) + 1), (lgyy_s1_y + 2))))))))))) + auto hcompute_lgyy_stencil_4 = lgyy_s1_x_x->add_op("op_hcompute_lgyy_stencil_4"); + hcompute_lgyy_stencil_4->add_function("hcompute_lgyy_stencil_4"); + hcompute_lgyy_stencil_4->add_load("lgyy_stencil", "lgyy_s1_y", "(lgyy_s1_x_x*4)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "lgyy_s1_y", "(lgyy_s1_x_x*4)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 1)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "(lgyy_s1_x_x*4)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 1)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "(lgyy_s1_x_x*4)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_4->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 1)"); + hcompute_lgyy_stencil_4->add_store("lgyy_stencil", "lgyy_s1_y", "(lgyy_s1_x_x*4)"); + +//store is: lgyy.stencil(((lgyy_s1_x_x*4) + 1), lgyy_s1_y) = (lyy.stencil(((lgyy_s1_x_x*4) + 1), lgyy_s1_y) + (lgyy.stencil(((lgyy_s1_x_x*4) + 1), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), (lgyy_s1_y + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), (lgyy_s1_y + 2)) + lyy.stencil(((lgyy_s1_x_x*4) + 2), (lgyy_s1_y + 2))))))))))) + auto hcompute_lgyy_stencil_5 = lgyy_s1_x_x->add_op("op_hcompute_lgyy_stencil_5"); + hcompute_lgyy_stencil_5->add_function("hcompute_lgyy_stencil_5"); + hcompute_lgyy_stencil_5->add_load("lgyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 1)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 1)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 1)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 1)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_5->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_5->add_store("lgyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 1)"); + +//store is: lgyy.stencil(((lgyy_s1_x_x*4) + 2), lgyy_s1_y) = (lyy.stencil(((lgyy_s1_x_x*4) + 2), lgyy_s1_y) + (lgyy.stencil(((lgyy_s1_x_x*4) + 2), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), (lgyy_s1_y + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), (lgyy_s1_y + 2)) + lyy.stencil(((lgyy_s1_x_x*4) + 3), (lgyy_s1_y + 2))))))))))) + auto hcompute_lgyy_stencil_6 = lgyy_s1_x_x->add_op("op_hcompute_lgyy_stencil_6"); + hcompute_lgyy_stencil_6->add_function("hcompute_lgyy_stencil_6"); + hcompute_lgyy_stencil_6->add_load("lgyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 4)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 4)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 2)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 4)"); + hcompute_lgyy_stencil_6->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_6->add_store("lgyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 2)"); + +//store is: lgyy.stencil(((lgyy_s1_x_x*4) + 3), lgyy_s1_y) = (lyy.stencil(((lgyy_s1_x_x*4) + 3), lgyy_s1_y) + (lgyy.stencil(((lgyy_s1_x_x*4) + 3), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 5), lgyy_s1_y) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 5), (lgyy_s1_y + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), (lgyy_s1_y + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 5), (lgyy_s1_y + 2)) + lyy.stencil(((lgyy_s1_x_x*4) + 4), (lgyy_s1_y + 2))))))))))) + auto hcompute_lgyy_stencil_7 = lgyy_s1_x_x->add_op("op_hcompute_lgyy_stencil_7"); + hcompute_lgyy_stencil_7->add_function("hcompute_lgyy_stencil_7"); + hcompute_lgyy_stencil_7->add_load("lgyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 4)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 5)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 4)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "(lgyy_s1_y + 1)", "((lgyy_s1_x_x*4) + 5)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 3)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 5)"); + hcompute_lgyy_stencil_7->add_load("lyy_stencil", "(lgyy_s1_y + 2)", "((lgyy_s1_x_x*4) + 4)"); + hcompute_lgyy_stencil_7->add_store("lgyy_stencil", "lgyy_s1_y", "((lgyy_s1_x_x*4) + 3)"); + +//consuming lgyy.stencil +////producing cim.stencil + auto cim_s0_y = prg.add_loop("cim_s0_y", 0, 257); + auto cim_s0_x_x = cim_s0_y->add_loop("cim_s0_x_x", 0, 75); + +//store is: cim.stencil((cim_s0_x_x*4), cim_s0_y) = ((((lgxx.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64)*(lgyy.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64)) - ((lgxy.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64)*(lgxy.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64))) - ((((lgxx.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64) + (lgyy.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64))*((lgxx.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64) + (lgyy.stencil((cim_s0_x_x*4), cim_s0_y)/(int16)64)))/(int16)16)) + auto hcompute_cim_stencil = cim_s0_x_x->add_op("op_hcompute_cim_stencil"); + hcompute_cim_stencil->add_function("hcompute_cim_stencil"); + hcompute_cim_stencil->add_load("lgxx_stencil", "cim_s0_y", "(cim_s0_x_x*4)"); + hcompute_cim_stencil->add_load("lgxy_stencil", "cim_s0_y", "(cim_s0_x_x*4)"); + hcompute_cim_stencil->add_load("lgyy_stencil", "cim_s0_y", "(cim_s0_x_x*4)"); + prg.buffer_port_widths["cim_stencil"] = 16; + hcompute_cim_stencil->add_store("cim_stencil", "cim_s0_y", "(cim_s0_x_x*4)"); + +//store is: cim.stencil(((cim_s0_x_x*4) + 1), cim_s0_y) = ((((lgxx.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64)*(lgyy.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64)*(lgxy.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64))*((lgxx.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 1), cim_s0_y)/(int16)64)))/(int16)16)) + auto hcompute_cim_stencil_1 = cim_s0_x_x->add_op("op_hcompute_cim_stencil_1"); + hcompute_cim_stencil_1->add_function("hcompute_cim_stencil_1"); + hcompute_cim_stencil_1->add_load("lgxx_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 1)"); + hcompute_cim_stencil_1->add_load("lgxy_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 1)"); + hcompute_cim_stencil_1->add_load("lgyy_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 1)"); + hcompute_cim_stencil_1->add_store("cim_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 1)"); + +//store is: cim.stencil(((cim_s0_x_x*4) + 2), cim_s0_y) = ((((lgxx.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64)*(lgyy.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64)*(lgxy.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64))*((lgxx.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 2), cim_s0_y)/(int16)64)))/(int16)16)) + auto hcompute_cim_stencil_2 = cim_s0_x_x->add_op("op_hcompute_cim_stencil_2"); + hcompute_cim_stencil_2->add_function("hcompute_cim_stencil_2"); + hcompute_cim_stencil_2->add_load("lgxx_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 2)"); + hcompute_cim_stencil_2->add_load("lgxy_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 2)"); + hcompute_cim_stencil_2->add_load("lgyy_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 2)"); + hcompute_cim_stencil_2->add_store("cim_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 2)"); + +//store is: cim.stencil(((cim_s0_x_x*4) + 3), cim_s0_y) = ((((lgxx.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64)*(lgyy.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64)*(lgxy.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64))*((lgxx.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 3), cim_s0_y)/(int16)64)))/(int16)16)) + auto hcompute_cim_stencil_3 = cim_s0_x_x->add_op("op_hcompute_cim_stencil_3"); + hcompute_cim_stencil_3->add_function("hcompute_cim_stencil_3"); + hcompute_cim_stencil_3->add_load("lgxx_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 3)"); + hcompute_cim_stencil_3->add_load("lgxy_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 3)"); + hcompute_cim_stencil_3->add_load("lgyy_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 3)"); + hcompute_cim_stencil_3->add_store("cim_stencil", "cim_s0_y", "((cim_s0_x_x*4) + 3)"); + +//consuming cim.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 255); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi_xi", 0, 74); + +//store is: hw_output.glb.stencil((hw_output_s0_x_xi_xi*4), hw_output_s0_y_yi) = select((((((((((cim.stencil((hw_output_s0_x_xi_xi*4), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil((hw_output_s0_x_xi_xi*4), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil((hw_output_s0_x_xi_xi*4), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*4)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 1)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 1)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "(hw_output_s0_x_xi_xi*4)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "(hw_output_s0_x_xi_xi*4)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 1)"); + hcompute_hw_output_glb_stencil->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 2)"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "(hw_output_s0_x_xi_xi*4)"); + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi*4) + 1), hw_output_s0_y_yi) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 1)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 1)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 1)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil_1->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 1)"); + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 4)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 4)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_2->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 4)"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 2)"); + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 5), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 5), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 5), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) + auto hcompute_hw_output_glb_stencil_3 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_function("hcompute_hw_output_glb_stencil_3"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 4)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 4)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 5)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "(hw_output_s0_y_yi + 1)", "((hw_output_s0_x_xi_xi*4) + 5)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 4)"); + hcompute_hw_output_glb_stencil_3->add_load("cim_stencil", "(hw_output_s0_y_yi + 2)", "((hw_output_s0_x_xi_xi*4) + 5)"); + hcompute_hw_output_glb_stencil_3->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "((hw_output_s0_x_xi_xi*4) + 3)"); +////producing hw_input_global_wrapper_global_wrapper.stencil + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi = prg.add_loop("hw_output_global_wrapper_s0_y_yi", 0, 255); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 74); + +//store is: hw_output_global_wrapper.stencil((hw_output_global_wrapper_s0_x_xi_xi*4), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil((hw_output_global_wrapper_s0_x_xi_xi*4), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*4)"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "(hw_output_global_wrapper_s0_x_xi_xi*4)"); + +//store is: hw_output_global_wrapper.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 1), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 1), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*4) + 1)"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*4) + 1)"); + +//store is: hw_output_global_wrapper.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 2), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 2), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*4) + 2)"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*4) + 2)"); + +//store is: hw_output_global_wrapper.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 3), hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 3), hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_3 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_function("hcompute_hw_output_global_wrapper_stencil_3"); + hcompute_hw_output_global_wrapper_stencil_3->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*4) + 3)"); + hcompute_hw_output_global_wrapper_stencil_3->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "((hw_output_global_wrapper_s0_x_xi_xi*4) + 3)"); + + return prg; +} + + +// schedule=3 myunroll=4 diff --git a/example_progs/matmul.cpp b/example_progs/matmul.cpp index cacafeff0..1a4655a27 100644 --- a/example_progs/matmul.cpp +++ b/example_progs/matmul.cpp @@ -1,5 +1,95 @@ #include "prog.h" +prog matmul_unroll2() { + prog prg; + prg.compute_unit_file = "matmul_unroll2_compute.h"; + prg.name = "matmul_unroll2"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_kernel_stencil = arg_1; + prg.add_input("hw_kernel_stencil"); + prg.buffer_port_widths["hw_kernel_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 32); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", 0, 32); + +//store is: hw_input_global_wrapper.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x"); + +//consuming hw_input_global_wrapper.stencil +////producing hw_kernel_global_wrapper.stencil + auto hw_kernel_global_wrapper_s0_y = prg.add_loop("hw_kernel_global_wrapper_s0_y", 0, 32); + auto hw_kernel_global_wrapper_s0_x = hw_kernel_global_wrapper_s0_y->add_loop("hw_kernel_global_wrapper_s0_x", 0, 32); + +//store is: hw_kernel_global_wrapper.stencil(hw_kernel_global_wrapper_s0_x, hw_kernel_global_wrapper_s0_y) = hw_kernel.stencil(hw_kernel_global_wrapper_s0_x, hw_kernel_global_wrapper_s0_y) + auto hcompute_hw_kernel_global_wrapper_stencil = hw_kernel_global_wrapper_s0_x->add_op("op_hcompute_hw_kernel_global_wrapper_stencil"); + hcompute_hw_kernel_global_wrapper_stencil->add_function("hcompute_hw_kernel_global_wrapper_stencil"); + hcompute_hw_kernel_global_wrapper_stencil->add_load("hw_kernel_stencil", "hw_kernel_global_wrapper_s0_y", "hw_kernel_global_wrapper_s0_x"); + prg.buffer_port_widths["hw_kernel_global_wrapper_stencil"] = 16; + hcompute_hw_kernel_global_wrapper_stencil->add_store("hw_kernel_global_wrapper_stencil", "hw_kernel_global_wrapper_s0_y", "hw_kernel_global_wrapper_s0_x"); + +//consuming hw_kernel_global_wrapper.stencil +////producing mul.stencil + auto mul_s0_y = prg.add_loop("mul_s0_y", 0, 32); + auto mul_s0_x_x = mul_s0_y->add_loop("mul_s0_x_x", 0, 32); + +//store is: mul.stencil((mul_s0_x_x*2), mul_s0_y) = (int16)0 + auto hcompute_mul_stencil = mul_s0_x_x->add_op("op_hcompute_mul_stencil"); + hcompute_mul_stencil->add_function("hcompute_mul_stencil"); + prg.buffer_port_widths["mul_stencil"] = 16; + hcompute_mul_stencil->add_store("mul_stencil", "mul_s0_y", "(mul_s0_x_x*2)"); + +//store is: mul.stencil(((mul_s0_x_x*2) + 1), mul_s0_y) = (int16)0 + auto hcompute_mul_stencil_1 = mul_s0_x_x->add_op("op_hcompute_mul_stencil_1"); + hcompute_mul_stencil_1->add_function("hcompute_mul_stencil_1"); + hcompute_mul_stencil_1->add_store("mul_stencil", "mul_s0_y", "((mul_s0_x_x*2) + 1)"); + auto mul_s1_y = prg.add_loop("mul_s1_y", 0, 32); + auto mul_s1_r_x_rxo = mul_s1_y->add_loop("mul_s1_r_x_rxo", 0, 32); + auto mul_s1_x_xo = mul_s1_r_x_rxo->add_loop("mul_s1_x_xo", 0, 32); + +//store is: mul.stencil((mul_s1_x_xo*2), mul_s1_y) = ((hw_input_global_wrapper.stencil((mul_s1_r_x_rxo*2), mul_s1_y)*hw_kernel_global_wrapper.stencil((mul_s1_x_xo*2), (mul_s1_r_x_rxo*2))) + (mul.stencil((mul_s1_x_xo*2), mul_s1_y) + (hw_input_global_wrapper.stencil(((mul_s1_r_x_rxo*2) + 1), mul_s1_y)*hw_kernel_global_wrapper.stencil((mul_s1_x_xo*2), ((mul_s1_r_x_rxo*2) + 1))))) + auto hcompute_mul_stencil_2 = mul_s1_x_xo->add_op("op_hcompute_mul_stencil_2"); + hcompute_mul_stencil_2->add_function("hcompute_mul_stencil_2"); + hcompute_mul_stencil_2->add_load("hw_input_global_wrapper_stencil", "mul_s1_y", "(mul_s1_r_x_rxo*2)"); + hcompute_mul_stencil_2->add_load("hw_input_global_wrapper_stencil", "mul_s1_y", "((mul_s1_r_x_rxo*2) + 1)"); + hcompute_mul_stencil_2->add_load("hw_kernel_global_wrapper_stencil", "(mul_s1_r_x_rxo*2)", "(mul_s1_x_xo*2)"); + hcompute_mul_stencil_2->add_load("hw_kernel_global_wrapper_stencil", "((mul_s1_r_x_rxo*2) + 1)", "(mul_s1_x_xo*2)"); + hcompute_mul_stencil_2->add_load("mul_stencil", "mul_s1_y", "(mul_s1_x_xo*2)"); + hcompute_mul_stencil_2->add_store("mul_stencil", "mul_s1_y", "(mul_s1_x_xo*2)"); + +//store is: mul.stencil(((mul_s1_x_xo*2) + 1), mul_s1_y) = ((hw_input_global_wrapper.stencil((mul_s1_r_x_rxo*2), mul_s1_y)*hw_kernel_global_wrapper.stencil(((mul_s1_x_xo*2) + 1), (mul_s1_r_x_rxo*2))) + (mul.stencil(((mul_s1_x_xo*2) + 1), mul_s1_y) + (hw_input_global_wrapper.stencil(((mul_s1_r_x_rxo*2) + 1), mul_s1_y)*hw_kernel_global_wrapper.stencil(((mul_s1_x_xo*2) + 1), ((mul_s1_r_x_rxo*2) + 1))))) + auto hcompute_mul_stencil_3 = mul_s1_x_xo->add_op("op_hcompute_mul_stencil_3"); + hcompute_mul_stencil_3->add_function("hcompute_mul_stencil_3"); + hcompute_mul_stencil_3->add_load("hw_input_global_wrapper_stencil", "mul_s1_y", "(mul_s1_r_x_rxo*2)"); + hcompute_mul_stencil_3->add_load("hw_input_global_wrapper_stencil", "mul_s1_y", "((mul_s1_r_x_rxo*2) + 1)"); + hcompute_mul_stencil_3->add_load("hw_kernel_global_wrapper_stencil", "(mul_s1_r_x_rxo*2)", "((mul_s1_x_xo*2) + 1)"); + hcompute_mul_stencil_3->add_load("hw_kernel_global_wrapper_stencil", "((mul_s1_r_x_rxo*2) + 1)", "((mul_s1_x_xo*2) + 1)"); + hcompute_mul_stencil_3->add_load("mul_stencil", "mul_s1_y", "((mul_s1_x_xo*2) + 1)"); + hcompute_mul_stencil_3->add_store("mul_stencil", "mul_s1_y", "((mul_s1_x_xo*2) + 1)"); + +//consuming mul.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 32); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 32); + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) = mul.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("mul_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + + return prg; +} + //Single tile matmul apps prog matmul_single() { prog prg; diff --git a/example_progs/nlmeans_memory.cpp b/example_progs/nlmeans_memory.cpp new file mode 100644 index 000000000..53056a0ce --- /dev/null +++ b/example_progs/nlmeans_memory.cpp @@ -0,0 +1,1544 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog nlmeans() { + prog prg; + prg.compute_unit_file = "nlmeans_compute.h"; + prg.name = "nlmeans"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -6, 68); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -6, 68); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_dy = prg.add_loop("d_s0_dy", -3, 4); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -3, 4); + auto d_s0_y = d_s0_dx->add_loop("d_s0_y", -3, 65); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -3, 65); + +//store is: d.stencil((d_s0_x + 3), (d_s0_y + 3), (d_s0_dx + 3), (d_s0_dy + 3)) = 0.000000h + auto hcompute_d_stencil = d_s0_x->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_dy + 3)", "(d_s0_dx + 3)", "(d_s0_y + 3)", "(d_s0_x + 3)"); + auto d_s1_dy = prg.add_loop("d_s1_dy", -3, 4); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -3, 4); + auto d_s1_y = d_s1_dx->add_loop("d_s1_y", -3, 65); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -3, 65); + +//store is: d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6))))))) + auto hcompute_d_stencil_1 = d_s1_x->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_dy + 3)", "(d_s1_dx + 3)", "(d_s1_y + 3)", "(d_s1_x + 3)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "0"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_dy + 3)", "(d_s1_dx + 3)", "(d_s1_y + 3)", "(d_s1_x + 3)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_dy = prg.add_loop("blur_d_y_s0_dy", -3, 4); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -3, 4); + auto blur_d_y_s0_y = blur_d_y_s0_dx->add_loop("blur_d_y_s0_y", 0, 62); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -3, 65); + +//store is: blur_d_y.stencil((blur_d_y_s0_x + 3), blur_d_y_s0_y, (blur_d_y_s0_dx + 3), (blur_d_y_s0_dy + 3)) = 0.000000h + auto hcompute_blur_d_y_stencil = blur_d_y_s0_x->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "(blur_d_y_s0_dy + 3)", "(blur_d_y_s0_dx + 3)", "blur_d_y_s0_y", "(blur_d_y_s0_x + 3)"); + auto blur_d_y_s1_dy = prg.add_loop("blur_d_y_s1_dy", -3, 4); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -3, 4); + auto blur_d_y_s1_y = blur_d_y_s1_dx->add_loop("blur_d_y_s1_y", 0, 62); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -3, 65); + +//store is: blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) = (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 6), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 5), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 4), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 3), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 2), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 1), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + d.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3))))))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_x->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 6)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 5)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 4)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_dy = prg.add_loop("blur_d_s0_dy", -3, 4); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -3, 4); + auto blur_d_s0_y = blur_d_s0_dx->add_loop("blur_d_s0_y", 0, 62); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 62); + +//store is: blur_d.stencil(blur_d_s0_x, blur_d_s0_y, (blur_d_s0_dx + 3), (blur_d_s0_dy + 3)) = 0.000000h + auto hcompute_blur_d_stencil = blur_d_s0_x->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "(blur_d_s0_dy + 3)", "(blur_d_s0_dx + 3)", "blur_d_s0_y", "blur_d_s0_x"); + auto blur_d_s1_dy = prg.add_loop("blur_d_s1_dy", -3, 4); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -3, 4); + auto blur_d_s1_y = blur_d_s1_dx->add_loop("blur_d_s1_y", 0, 62); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 62); + +//store is: blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) = (blur_d_y.stencil((blur_d_s1_x + 6), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 5), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 4), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 3), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 2), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 1), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + blur_d_y.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3))))))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_x->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "blur_d_s1_x"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 6)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 5)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 4)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 1)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "blur_d_s1_x"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "blur_d_s1_x"); + +//consuming blur_d.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 62); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 62); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 1) = 0.000000h + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 2) = 0.000000h + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 3) = 0.000000h + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s1_s_dom_y = prg.add_loop("non_local_means_sum_s1_s_dom_y", -3, 4); + auto non_local_means_sum_s1_s_dom_x = non_local_means_sum_s1_s_dom_y->add_loop("non_local_means_sum_s1_s_dom_x", -3, 4); + auto non_local_means_sum_s1_y = non_local_means_sum_s1_s_dom_x->add_loop("non_local_means_sum_s1_y", 0, 62); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 62); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "(non_local_means_sum_s1_s_dom_y + 3)", "(non_local_means_sum_s1_s_dom_x + 3)", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)", "((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "(non_local_means_sum_s1_s_dom_y + 3)", "(non_local_means_sum_s1_s_dom_x + 3)", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)", "((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) + auto hcompute_non_local_means_sum_stencil_6 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_function("hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "(non_local_means_sum_s1_s_dom_y + 3)", "(non_local_means_sum_s1_s_dom_x + 3)", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)", "((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) + exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))) + auto hcompute_non_local_means_sum_stencil_7 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_function("hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "(non_local_means_sum_s1_s_dom_y + 3)", "(non_local_means_sum_s1_s_dom_x + 3)", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 62); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 62); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + +prog nlmeans_unroll() { + prog prg; + prg.compute_unit_file = "nlmeans_unroll_compute.h"; + prg.name = "nlmeans_unroll"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -6, 68); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -6, 68); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_dy = prg.add_loop("d_s0_dy", -3, 4); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -3, 4); + auto d_s0_y = d_s0_dx->add_loop("d_s0_y", -3, 65); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -3, 65); + +//store is: d.stencil((d_s0_x + 3), (d_s0_y + 3), (d_s0_dx + 3), (d_s0_dy + 3)) = 0.000000h + auto hcompute_d_stencil = d_s0_x->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_dy + 3)", "(d_s0_dx + 3)", "(d_s0_y + 3)", "(d_s0_x + 3)"); + auto d_s1_dy = prg.add_loop("d_s1_dy", -3, 4); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -3, 4); + auto d_s1_y = d_s1_dx->add_loop("d_s1_y", -3, 65); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -3, 65); + +//store is: d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6))))))) + auto hcompute_d_stencil_1 = d_s1_x->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_dy + 3)", "(d_s1_dx + 3)", "(d_s1_y + 3)", "(d_s1_x + 3)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "0"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_dy + 3)", "(d_s1_dx + 3)", "(d_s1_y + 3)", "(d_s1_x + 3)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_dy = prg.add_loop("blur_d_y_s0_dy", -3, 4); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -3, 4); + auto blur_d_y_s0_y = blur_d_y_s0_dx->add_loop("blur_d_y_s0_y", 0, 62); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -3, 65); + +//store is: blur_d_y.stencil((blur_d_y_s0_x + 3), blur_d_y_s0_y, (blur_d_y_s0_dx + 3), (blur_d_y_s0_dy + 3)) = 0.000000h + auto hcompute_blur_d_y_stencil = blur_d_y_s0_x->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "(blur_d_y_s0_dy + 3)", "(blur_d_y_s0_dx + 3)", "blur_d_y_s0_y", "(blur_d_y_s0_x + 3)"); + auto blur_d_y_s1_dy = prg.add_loop("blur_d_y_s1_dy", -3, 4); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -3, 4); + auto blur_d_y_s1_y = blur_d_y_s1_dx->add_loop("blur_d_y_s1_y", 0, 62); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -3, 65); + +//store is: blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) = (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 6), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 5), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 4), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 3), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 2), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 1), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + d.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3))))))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_x->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 6)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 5)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 4)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_dy = prg.add_loop("blur_d_s0_dy", -3, 4); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -3, 4); + auto blur_d_s0_y = blur_d_s0_dx->add_loop("blur_d_s0_y", 0, 62); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 62); + +//store is: blur_d.stencil(blur_d_s0_x, blur_d_s0_y, (blur_d_s0_dx + 3), (blur_d_s0_dy + 3)) = 0.000000h + auto hcompute_blur_d_stencil = blur_d_s0_x->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "(blur_d_s0_dy + 3)", "(blur_d_s0_dx + 3)", "blur_d_s0_y", "blur_d_s0_x"); + auto blur_d_s1_dy = prg.add_loop("blur_d_s1_dy", -3, 4); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -3, 4); + auto blur_d_s1_y = blur_d_s1_dx->add_loop("blur_d_s1_y", 0, 62); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 62); + +//store is: blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) = (blur_d_y.stencil((blur_d_s1_x + 6), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 5), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 4), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 3), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 2), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 1), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + blur_d_y.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3))))))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_x->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "blur_d_s1_x"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 6)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 5)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 4)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "(blur_d_s1_x + 1)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "blur_d_s1_x"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)", "blur_d_s1_y", "blur_d_s1_x"); + +//consuming blur_d.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 62); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 62); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 1) = 0.000000h + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 2) = 0.000000h + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 3) = 0.000000h + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s1_y = prg.add_loop("non_local_means_sum_s1_y", 0, 62); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 62); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "5", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "5", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "5", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "5", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "5", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "5", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "6", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "3", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "3", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "3", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "3", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "3", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "3", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "3", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "6", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "2", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "2", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "2", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "2", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "2", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "2", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "2", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "1", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "1", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "1", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "6", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "1", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "1", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "1", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "1", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "0", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "0", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "0", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "0", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "0", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "0", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "6", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "0", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "6", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "6", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "6", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "5", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) = ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "6", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "6", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "6", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "6", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "6", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "6", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "6", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "5", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "5", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "5", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "5", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "5", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "5", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "5", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "3", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "3", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "3", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "3", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "3", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "3", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "3", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "2", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "2", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "2", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "2", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "2", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "2", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "2", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "1", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "1", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "1", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "1", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "1", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "1", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "1", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "0", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "0", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "0", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "0", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "0", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "0", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "0", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) = ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_6 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_function("hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "6", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "6", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "6", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "6", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "6", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "6", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "6", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "5", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "5", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "5", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "5", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "5", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "5", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "5", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "3", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "3", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "3", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "3", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "3", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "3", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "3", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "2", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "2", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "2", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "2", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "2", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "2", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "2", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "1", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "1", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "1", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "1", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "1", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "1", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "1", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "0", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "0", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "0", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "0", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "0", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "0", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "0", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) = (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h)) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) + exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_7 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_function("hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "6", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "6", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "6", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "6", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "6", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "6", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "6", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "5", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "5", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "5", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "5", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "5", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "5", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "5", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "6", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "5", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 62); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 62); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + +prog nlmeans_small() { + prog prg; + prg.compute_unit_file = "nlmeans_small_compute.h"; + prg.name = "nlmeans_small"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -4, 36); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -4, 36); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_dy = prg.add_loop("d_s0_dy", -2, 3); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -2, 3); + auto d_s0_y = d_s0_dx->add_loop("d_s0_y", -2, 34); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -2, 34); + +//store is: d.stencil((d_s0_x + 2), (d_s0_y + 2), (d_s0_dx + 2), (d_s0_dy + 2)) = 0.000000h + auto hcompute_d_stencil = d_s0_x->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_dy + 2)", "(d_s0_dx + 2)", "(d_s0_y + 2)", "(d_s0_x + 2)"); + auto d_s1_dy = prg.add_loop("d_s1_dy", -2, 3); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -2, 3); + auto d_s1_y = d_s1_dx->add_loop("d_s1_y", -2, 34); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -2, 34); + +//store is: d.stencil((d_s1_x + 2), (d_s1_y + 2), (d_s1_dx + 2), (d_s1_dy + 2)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_x + 2), (d_s1_y + 2), (d_s1_dx + 2), (d_s1_dy + 2)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) + auto hcompute_d_stencil_1 = d_s1_x->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_dy + 2)", "(d_s1_dx + 2)", "(d_s1_y + 2)", "(d_s1_x + 2)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "0"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_dy + 2)", "(d_s1_dx + 2)", "(d_s1_y + 2)", "(d_s1_x + 2)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_dy = prg.add_loop("blur_d_y_s0_dy", -2, 3); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -2, 3); + auto blur_d_y_s0_y = blur_d_y_s0_dx->add_loop("blur_d_y_s0_y", 0, 32); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -2, 34); + +//store is: blur_d_y.stencil((blur_d_y_s0_x + 2), blur_d_y_s0_y, (blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2)) = 0.000000h + auto hcompute_blur_d_y_stencil = blur_d_y_s0_x->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "(blur_d_y_s0_dy + 2)", "(blur_d_y_s0_dx + 2)", "blur_d_y_s0_y", "(blur_d_y_s0_x + 2)"); + auto blur_d_y_s1_dy = prg.add_loop("blur_d_y_s1_dy", -2, 3); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -2, 3); + auto blur_d_y_s1_y = blur_d_y_s1_dx->add_loop("blur_d_y_s1_y", 0, 32); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -2, 34); + +//store is: blur_d_y.stencil((blur_d_y_s1_x + 2), blur_d_y_s1_y, (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) = (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 4), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (blur_d_y.stencil((blur_d_y_s1_x + 2), blur_d_y_s1_y, (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + d.stencil((blur_d_y_s1_x + 2), blur_d_y_s1_y, (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2))))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_x->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)", "(blur_d_y_s1_y + 4)", "(blur_d_y_s1_x + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_dy = prg.add_loop("blur_d_s0_dy", -2, 3); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -2, 3); + auto blur_d_s0_y = blur_d_s0_dx->add_loop("blur_d_s0_y", 0, 32); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 32); + +//store is: blur_d.stencil(blur_d_s0_x, blur_d_s0_y, (blur_d_s0_dx + 2), (blur_d_s0_dy + 2)) = 0.000000h + auto hcompute_blur_d_stencil = blur_d_s0_x->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "(blur_d_s0_dy + 2)", "(blur_d_s0_dx + 2)", "blur_d_s0_y", "blur_d_s0_x"); + auto blur_d_s1_dy = prg.add_loop("blur_d_s1_dy", -2, 3); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -2, 3); + auto blur_d_s1_y = blur_d_s1_dx->add_loop("blur_d_s1_y", 0, 32); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 32); + +//store is: blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) = (blur_d_y.stencil((blur_d_s1_x + 4), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d_y.stencil((blur_d_s1_x + 3), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d_y.stencil((blur_d_s1_x + 2), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d_y.stencil((blur_d_s1_x + 1), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + blur_d_y.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2))))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_x->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)", "blur_d_s1_y", "blur_d_s1_x"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)", "blur_d_s1_y", "(blur_d_s1_x + 4)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)", "blur_d_s1_y", "(blur_d_s1_x + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)", "blur_d_s1_y", "(blur_d_s1_x + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)", "blur_d_s1_y", "(blur_d_s1_x + 1)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)", "blur_d_s1_y", "blur_d_s1_x"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)", "blur_d_s1_y", "blur_d_s1_x"); + +//consuming blur_d.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 32); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 1) = 0.000000h + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 2) = 0.000000h + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 3) = 0.000000h + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s1_y = prg.add_loop("non_local_means_sum_s1_y", 0, 32); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6)))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6)))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6)))) + auto hcompute_non_local_means_sum_stencil_6 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_function("hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) = (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h)) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) + exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_7 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_function("hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "3", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "2", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "1", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "0", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "4", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "4", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_load("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 32); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 32); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + +prog nlmeans_unroll_reorder() { + prog prg; + prg.compute_unit_file = "nlmeans_unroll_compute.h"; + prg.name = "nlmeans_unroll_reorder"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -6, 68); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -6, 68); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_y = prg.add_loop("d_s0_y", -3, 65); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -3, 65); + auto d_s0_dy = d_s0_x->add_loop("d_s0_dy", -3, 4); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -3, 4); + +//store is: d.stencil((d_s0_dx + 3), (d_s0_dy + 3), (d_s0_x + 3), (d_s0_y + 3)) = 0.000000h + auto hcompute_d_stencil = d_s0_dx->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_y + 3)", "(d_s0_x + 3)", "(d_s0_dy + 3)", "(d_s0_dx + 3)"); + auto d_s1_y = prg.add_loop("d_s1_y", -3, 65); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -3, 65); + auto d_s1_dy = d_s1_x->add_loop("d_s1_dy", -3, 4); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -3, 4); + +//store is: d.stencil((d_s1_dx + 3), (d_s1_dy + 3), (d_s1_x + 3), (d_s1_y + 3)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (d.stencil((d_s1_dx + 3), (d_s1_dy + 3), (d_s1_x + 3), (d_s1_y + 3)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6))))))) + auto hcompute_d_stencil_1 = d_s1_dx->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_y + 3)", "(d_s1_x + 3)", "(d_s1_dy + 3)", "(d_s1_dx + 3)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "0"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_y + 3)", "(d_s1_x + 3)", "(d_s1_dy + 3)", "(d_s1_dx + 3)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_y = prg.add_loop("blur_d_y_s0_y", 0, 62); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -3, 65); + auto blur_d_y_s0_dy = blur_d_y_s0_x->add_loop("blur_d_y_s0_dy", -3, 4); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -3, 4); + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 3), (blur_d_y_s0_dy + 3), (blur_d_y_s0_x + 3), blur_d_y_s0_y) = 0.000000h + auto hcompute_blur_d_y_stencil = blur_d_y_s0_dx->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "blur_d_y_s0_y", "(blur_d_y_s0_x + 3)", "(blur_d_y_s0_dy + 3)", "(blur_d_y_s0_dx + 3)"); + auto blur_d_y_s1_y = prg.add_loop("blur_d_y_s1_y", 0, 62); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -3, 65); + auto blur_d_y_s1_dy = blur_d_y_s1_x->add_loop("blur_d_y_s1_dy", -3, 4); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -3, 4); + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 6)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 5)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 4)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 3)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 2)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 1)) + (blur_d_y.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y) + d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y)))))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_dx->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 6)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 5)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 4)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_y = prg.add_loop("blur_d_s0_y", 0, 62); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 62); + auto blur_d_s0_dy = blur_d_s0_x->add_loop("blur_d_s0_dy", -3, 4); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -3, 4); + +//store is: blur_d.stencil((blur_d_s0_dx + 3), (blur_d_s0_dy + 3), blur_d_s0_x, blur_d_s0_y) = 0.000000h + auto hcompute_blur_d_stencil = blur_d_s0_dx->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "blur_d_s0_y", "blur_d_s0_x", "(blur_d_s0_dy + 3)", "(blur_d_s0_dx + 3)"); + auto blur_d_s1_y = prg.add_loop("blur_d_s1_y", 0, 62); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 62); + auto blur_d_s1_dy = blur_d_s1_x->add_loop("blur_d_s1_dy", -3, 4); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -3, 4); + +//store is: blur_d.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 6), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 5), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 4), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 3), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 2), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y)))))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_dx->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 6)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 5)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 4)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 3)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 2)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 1)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + +//consuming blur_d.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 62); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 62); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 1) = 0.000000h + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 2) = 0.000000h + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 3) = 0.000000h + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s1_y = prg.add_loop("non_local_means_sum_s1_y", 0, 62); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 62); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = ((exp_bf16((blur_d.stencil(6, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(5, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(4, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(3, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(2, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(1, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(0, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(6, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(5, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(4, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(3, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(2, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(1, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(0, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(6, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(5, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(4, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(3, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(2, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(1, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(0, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(6, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(5, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(4, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(3, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(2, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(1, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(0, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(6, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(5, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(4, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(3, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(2, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(1, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(0, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(6, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(5, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(4, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(3, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(2, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(1, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(0, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(6, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(5, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(4, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(3, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(2, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(1, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil(0, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "5"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "3"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "2"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "6"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "5"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "3"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "6"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "2"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "6"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "5"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "3"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "2"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "5"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "6"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "5"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "3"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "2"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "6"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "5"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "3"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "2"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "6"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "5"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "3"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "2"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "3"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "2"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "6"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 5)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 3)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 9)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 8)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 7)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) = ((exp_bf16((blur_d.stencil(6, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(5, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(4, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(3, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(2, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(1, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(0, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(6, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(5, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(4, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(3, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(2, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(1, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(0, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(6, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(5, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(4, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(3, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(2, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(1, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(0, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(6, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(5, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(4, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(3, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(2, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(1, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(0, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(6, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(5, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(4, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(3, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(2, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(1, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(0, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(6, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(5, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(4, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(3, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(2, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(1, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(0, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(6, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(5, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(4, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(3, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(2, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(1, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) + (exp_bf16((blur_d.stencil(0, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "6"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "4"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "3"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "0"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "6"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "4"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "3"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "0"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "6"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "4"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "3"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "0"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "6"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "4"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "3"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "0"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "6"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "4"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "3"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "0"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "6"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "4"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "3"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "0"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "6"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "4"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "3"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "0"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 7)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 5)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 3)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 9)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 8)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) = ((exp_bf16((blur_d.stencil(6, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(5, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(4, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(3, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(2, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(1, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(0, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(6, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(5, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(4, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(3, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(2, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(1, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(0, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(6, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(5, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(4, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(3, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(2, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(1, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(0, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(6, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(5, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(4, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(3, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(2, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(1, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(0, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(6, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(5, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(4, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(3, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(2, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(1, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(0, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(6, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(5, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(4, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(3, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(2, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(1, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(0, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(6, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(5, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(4, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(3, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(2, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(1, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) + (exp_bf16((blur_d.stencil(0, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_6 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_function("hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "5"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "4"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "3"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "1"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "0"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "5"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "4"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "3"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "1"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "0"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "5"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "4"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "3"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "1"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "0"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "5"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "4"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "3"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "1"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "0"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "5"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "4"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "3"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "1"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "0"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "5"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "4"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "3"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "1"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "0"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "5"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "4"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "3"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "1"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "0"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 9)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 8)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 7)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 6)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 5)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 4)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 9)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 8)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 7)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 5)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "(non_local_means_sum_s1_y + 3)", "(non_local_means_sum_s1_x + 3)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_6->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) = (exp_bf16((blur_d.stencil(6, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(5, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(4, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(3, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(2, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(1, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(0, 6, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(6, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(5, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(4, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(3, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(2, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(1, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(0, 5, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(6, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(5, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(4, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(3, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(2, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(1, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(0, 4, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(6, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(5, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(4, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(3, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(2, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(1, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(0, 3, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(6, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(5, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(4, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(3, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(2, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(1, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(0, 2, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(6, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(5, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(4, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(3, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(2, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(1, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(0, 1, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(6, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(5, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(4, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(3, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(2, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (exp_bf16((blur_d.stencil(1, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h)) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) + exp_bf16((blur_d.stencil(0, 0, non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))))))))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_non_local_means_sum_stencil_7 = non_local_means_sum_s1_x->add_op("op_hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_function("hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "6"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "5"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "4"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "3"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "2"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "1"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "6", "0"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "6"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "5"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "4"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "3"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "2"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "1"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "5", "0"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "6"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "5"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "4"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "3"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "2"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "1"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "4", "0"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "6"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "5"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "4"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "3"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "2"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "1"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "3", "0"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "6"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "5"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "4"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "3"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "2"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "1"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "2", "0"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "6"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "5"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "4"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "3"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "2"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "1"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "1", "0"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "6"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "5"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "4"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "3"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "2"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "1"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "0", "0"); + hcompute_non_local_means_sum_stencil_7->add_load("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_7->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 62); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 62); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + +// empty diff --git a/example_progs/nlmeans_rolled.cpp b/example_progs/nlmeans_rolled.cpp new file mode 100644 index 000000000..4a8c855fc --- /dev/null +++ b/example_progs/nlmeans_rolled.cpp @@ -0,0 +1,457 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog nlmeans_rolled_int() { + prog prg; + prg.compute_unit_file = "nlmeans_rolled_int_compute.h"; + prg.name = "nlmeans_rolled_int"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -4, 34); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -4, 34); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_y = prg.add_loop("d_s0_y", -2, 33); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -2, 33); + auto d_s0_dy = d_s0_x->add_loop("d_s0_dy", -2, 2); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -2, 2); + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = 0.000000h + auto hcompute_d_stencil = d_s0_dx->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_y + 2)", "(d_s0_x + 2)", "(d_s0_dy + 2)", "(d_s0_dx + 2)"); + auto d_s1_y = prg.add_loop("d_s1_y", -2, 33); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -2, 33); + auto d_s1_dy = d_s1_x->add_loop("d_s1_dy", -2, 2); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -2, 2); + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) + auto hcompute_d_stencil_1 = d_s1_dx->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "0"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_y = prg.add_loop("blur_d_y_s0_y", 0, 32); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -2, 33); + auto blur_d_y_s0_dy = blur_d_y_s0_x->add_loop("blur_d_y_s0_dy", -2, 2); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = 0.000000h + auto hcompute_blur_d_y_stencil = blur_d_y_s0_dx->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "blur_d_y_s0_y", "(blur_d_y_s0_x + 2)", "(blur_d_y_s0_dy + 2)", "(blur_d_y_s0_dx + 2)"); + auto blur_d_y_s1_y = prg.add_loop("blur_d_y_s1_y", 0, 32); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -2, 33); + auto blur_d_y_s1_dy = blur_d_y_s1_x->add_loop("blur_d_y_s1_dy", -2, 2); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_dx->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_y = prg.add_loop("blur_d_s0_y", 0, 32); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 32); + auto blur_d_s0_dy = blur_d_s0_x->add_loop("blur_d_s0_dy", -2, 2); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = 0.000000h + auto hcompute_blur_d_stencil = blur_d_s0_dx->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "blur_d_s0_y", "blur_d_s0_x", "(blur_d_s0_dy + 2)", "(blur_d_s0_dx + 2)"); + auto blur_d_s1_y = prg.add_loop("blur_d_s1_y", 0, 32); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 32); + auto blur_d_s1_dy = blur_d_s1_x->add_loop("blur_d_s1_dy", -2, 2); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_dx->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 3)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 2)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 1)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + +//consuming blur_d.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 32); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s0_y_1 = prg.add_loop("non_local_means_sum_s0_y_1", 0, 32); + auto non_local_means_sum_s0_x_1 = non_local_means_sum_s0_y_1->add_loop("non_local_means_sum_s0_x_1", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = 0.000000h + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x_1->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y_1", "non_local_means_sum_s0_x_1"); + auto non_local_means_sum_s0_y_2 = prg.add_loop("non_local_means_sum_s0_y_2", 0, 32); + auto non_local_means_sum_s0_x_2 = non_local_means_sum_s0_y_2->add_loop("non_local_means_sum_s0_x_2", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = 0.000000h + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x_2->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y_2", "non_local_means_sum_s0_x_2"); + auto non_local_means_sum_s0_y_3 = prg.add_loop("non_local_means_sum_s0_y_3", 0, 32); + auto non_local_means_sum_s0_x_3 = non_local_means_sum_s0_y_3->add_loop("non_local_means_sum_s0_x_3", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_3, non_local_means_sum_s0_y_3, 3) = 0.000000h + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s0_x_3->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s0_y_3", "non_local_means_sum_s0_x_3"); + auto non_local_means_sum_s1_y = prg.add_loop("non_local_means_sum_s1_y", 0, 32); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 32); + auto non_local_means_sum_s1_s_dom_y = non_local_means_sum_s1_x->add_loop("non_local_means_sum_s1_s_dom_y", -2, 2); + auto non_local_means_sum_s1_s_dom_x = non_local_means_sum_s1_s_dom_y->add_loop("non_local_means_sum_s1_s_dom_x", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_s_dom_x->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "(non_local_means_sum_s1_s_dom_y + 2)", "(non_local_means_sum_s1_s_dom_x + 2)"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)", "((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + auto non_local_means_sum_s1_y_1 = prg.add_loop("non_local_means_sum_s1_y_1", 0, 32); + auto non_local_means_sum_s1_x_1 = non_local_means_sum_s1_y_1->add_loop("non_local_means_sum_s1_x_1", 0, 32); + auto non_local_means_sum_s1_s_dom_y_1 = non_local_means_sum_s1_x_1->add_loop("non_local_means_sum_s1_s_dom_y_1", -2, 2); + auto non_local_means_sum_s1_s_dom_x_1 = non_local_means_sum_s1_s_dom_y_1->add_loop("non_local_means_sum_s1_s_dom_x_1", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)*-1.414062h))*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_s_dom_x_1->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1", "(non_local_means_sum_s1_s_dom_y_1 + 2)", "(non_local_means_sum_s1_s_dom_x_1 + 2)"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)", "((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + auto non_local_means_sum_s1_y_2 = prg.add_loop("non_local_means_sum_s1_y_2", 0, 32); + auto non_local_means_sum_s1_x_2 = non_local_means_sum_s1_y_2->add_loop("non_local_means_sum_s1_x_2", 0, 32); + auto non_local_means_sum_s1_s_dom_y_2 = non_local_means_sum_s1_x_2->add_loop("non_local_means_sum_s1_s_dom_y_2", -2, 2); + auto non_local_means_sum_s1_s_dom_x_2 = non_local_means_sum_s1_s_dom_y_2->add_loop("non_local_means_sum_s1_s_dom_x_2", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)*-1.414062h))*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)))) + auto hcompute_non_local_means_sum_stencil_6 = non_local_means_sum_s1_s_dom_x_2->add_op("op_hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_function("hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2", "(non_local_means_sum_s1_s_dom_y_2 + 2)", "(non_local_means_sum_s1_s_dom_x_2 + 2)"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)", "((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + hcompute_non_local_means_sum_stencil_6->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + auto non_local_means_sum_s1_y_3 = prg.add_loop("non_local_means_sum_s1_y_3", 0, 32); + auto non_local_means_sum_s1_x_3 = non_local_means_sum_s1_y_3->add_loop("non_local_means_sum_s1_x_3", 0, 32); + auto non_local_means_sum_s1_s_dom_y_3 = non_local_means_sum_s1_x_3->add_loop("non_local_means_sum_s1_s_dom_y_3", -2, 2); + auto non_local_means_sum_s1_s_dom_x_3 = non_local_means_sum_s1_s_dom_y_3->add_loop("non_local_means_sum_s1_s_dom_x_3", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) + exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_3 + 2), (non_local_means_sum_s1_s_dom_y_3 + 2), non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3)*-1.414062h))) + auto hcompute_non_local_means_sum_stencil_7 = non_local_means_sum_s1_s_dom_x_3->add_op("op_hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_function("hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3", "(non_local_means_sum_s1_s_dom_y_3 + 2)", "(non_local_means_sum_s1_s_dom_x_3 + 2)"); + hcompute_non_local_means_sum_stencil_7->add_load("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3"); + hcompute_non_local_means_sum_stencil_7->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 32); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 32); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + +prog nlmeans_rolled() { + prog prg; + prg.compute_unit_file = "nlmeans_rolled_compute.h"; + prg.name = "nlmeans_rolled"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -4, 34); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -4, 34); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_y = prg.add_loop("d_s0_y", -2, 33); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -2, 33); + auto d_s0_dy = d_s0_x->add_loop("d_s0_dy", -2, 2); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -2, 2); + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = 0.000000h + auto hcompute_d_stencil = d_s0_dx->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_y + 2)", "(d_s0_x + 2)", "(d_s0_dy + 2)", "(d_s0_dx + 2)"); + auto d_s1_y = prg.add_loop("d_s1_y", -2, 33); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -2, 33); + auto d_s1_dy = d_s1_x->add_loop("d_s1_dy", -2, 2); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -2, 2); + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) + auto hcompute_d_stencil_1 = d_s1_dx->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "0"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_y = prg.add_loop("blur_d_y_s0_y", 0, 32); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -2, 33); + auto blur_d_y_s0_dy = blur_d_y_s0_x->add_loop("blur_d_y_s0_dy", -2, 2); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = 0.000000h + auto hcompute_blur_d_y_stencil = blur_d_y_s0_dx->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "blur_d_y_s0_y", "(blur_d_y_s0_x + 2)", "(blur_d_y_s0_dy + 2)", "(blur_d_y_s0_dx + 2)"); + auto blur_d_y_s1_y = prg.add_loop("blur_d_y_s1_y", 0, 32); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -2, 33); + auto blur_d_y_s1_dy = blur_d_y_s1_x->add_loop("blur_d_y_s1_dy", -2, 2); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_dx->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_y = prg.add_loop("blur_d_s0_y", 0, 32); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 32); + auto blur_d_s0_dy = blur_d_s0_x->add_loop("blur_d_s0_dy", -2, 2); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = 0.000000h + auto hcompute_blur_d_stencil = blur_d_s0_dx->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "blur_d_s0_y", "blur_d_s0_x", "(blur_d_s0_dy + 2)", "(blur_d_s0_dx + 2)"); + auto blur_d_s1_y = prg.add_loop("blur_d_s1_y", 0, 32); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 32); + auto blur_d_s1_dy = blur_d_s1_x->add_loop("blur_d_s1_dy", -2, 2); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_dx->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 3)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 2)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 1)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + +//consuming blur_d.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 32); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s0_y_1 = prg.add_loop("non_local_means_sum_s0_y_1", 0, 32); + auto non_local_means_sum_s0_x_1 = non_local_means_sum_s0_y_1->add_loop("non_local_means_sum_s0_x_1", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = 0.000000h + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x_1->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y_1", "non_local_means_sum_s0_x_1"); + auto non_local_means_sum_s0_y_2 = prg.add_loop("non_local_means_sum_s0_y_2", 0, 32); + auto non_local_means_sum_s0_x_2 = non_local_means_sum_s0_y_2->add_loop("non_local_means_sum_s0_x_2", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = 0.000000h + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x_2->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y_2", "non_local_means_sum_s0_x_2"); + auto non_local_means_sum_s0_y_3 = prg.add_loop("non_local_means_sum_s0_y_3", 0, 32); + auto non_local_means_sum_s0_x_3 = non_local_means_sum_s0_y_3->add_loop("non_local_means_sum_s0_x_3", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_3, non_local_means_sum_s0_y_3, 3) = 0.000000h + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s0_x_3->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s0_y_3", "non_local_means_sum_s0_x_3"); + auto non_local_means_sum_s1_y = prg.add_loop("non_local_means_sum_s1_y", 0, 32); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 32); + auto non_local_means_sum_s1_s_dom_y = non_local_means_sum_s1_x->add_loop("non_local_means_sum_s1_s_dom_y", -2, 2); + auto non_local_means_sum_s1_s_dom_x = non_local_means_sum_s1_s_dom_y->add_loop("non_local_means_sum_s1_s_dom_x", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_s_dom_x->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "(non_local_means_sum_s1_s_dom_y + 2)", "(non_local_means_sum_s1_s_dom_x + 2)"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)", "((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + auto non_local_means_sum_s1_y_1 = prg.add_loop("non_local_means_sum_s1_y_1", 0, 32); + auto non_local_means_sum_s1_x_1 = non_local_means_sum_s1_y_1->add_loop("non_local_means_sum_s1_x_1", 0, 32); + auto non_local_means_sum_s1_s_dom_y_1 = non_local_means_sum_s1_x_1->add_loop("non_local_means_sum_s1_s_dom_y_1", -2, 2); + auto non_local_means_sum_s1_s_dom_x_1 = non_local_means_sum_s1_s_dom_y_1->add_loop("non_local_means_sum_s1_s_dom_x_1", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)*-1.414062h))*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_s_dom_x_1->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1", "(non_local_means_sum_s1_s_dom_y_1 + 2)", "(non_local_means_sum_s1_s_dom_x_1 + 2)"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)", "((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + auto non_local_means_sum_s1_y_2 = prg.add_loop("non_local_means_sum_s1_y_2", 0, 32); + auto non_local_means_sum_s1_x_2 = non_local_means_sum_s1_y_2->add_loop("non_local_means_sum_s1_x_2", 0, 32); + auto non_local_means_sum_s1_s_dom_y_2 = non_local_means_sum_s1_x_2->add_loop("non_local_means_sum_s1_s_dom_y_2", -2, 2); + auto non_local_means_sum_s1_s_dom_x_2 = non_local_means_sum_s1_s_dom_y_2->add_loop("non_local_means_sum_s1_s_dom_x_2", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)*-1.414062h))*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)))) + auto hcompute_non_local_means_sum_stencil_6 = non_local_means_sum_s1_s_dom_x_2->add_op("op_hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_function("hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2", "(non_local_means_sum_s1_s_dom_y_2 + 2)", "(non_local_means_sum_s1_s_dom_x_2 + 2)"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)", "((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + hcompute_non_local_means_sum_stencil_6->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + auto non_local_means_sum_s1_y_3 = prg.add_loop("non_local_means_sum_s1_y_3", 0, 32); + auto non_local_means_sum_s1_x_3 = non_local_means_sum_s1_y_3->add_loop("non_local_means_sum_s1_x_3", 0, 32); + auto non_local_means_sum_s1_s_dom_y_3 = non_local_means_sum_s1_x_3->add_loop("non_local_means_sum_s1_s_dom_y_3", -2, 2); + auto non_local_means_sum_s1_s_dom_x_3 = non_local_means_sum_s1_s_dom_y_3->add_loop("non_local_means_sum_s1_s_dom_x_3", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) + exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_3 + 2), (non_local_means_sum_s1_s_dom_y_3 + 2), non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3)*-1.414062h))) + auto hcompute_non_local_means_sum_stencil_7 = non_local_means_sum_s1_s_dom_x_3->add_op("op_hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_function("hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3", "(non_local_means_sum_s1_s_dom_y_3 + 2)", "(non_local_means_sum_s1_s_dom_x_3 + 2)"); + hcompute_non_local_means_sum_stencil_7->add_load("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3"); + hcompute_non_local_means_sum_stencil_7->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 32); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 32); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + + +// empty diff --git a/example_progs/nlmeans_rolled7x7.cpp b/example_progs/nlmeans_rolled7x7.cpp new file mode 100644 index 000000000..0a93e7bd4 --- /dev/null +++ b/example_progs/nlmeans_rolled7x7.cpp @@ -0,0 +1,238 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog nlmeans_rolled_7x7() { + prog prg; + prg.compute_unit_file = "nlmeans_rolled_7x7_compute.h"; + prg.name = "nlmeans_rolled_7x7"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -6, 38); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -6, 38); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 6)", "(hw_input_global_wrapper_s0_x + 6)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_y = prg.add_loop("d_s0_y", -3, 35); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -3, 35); + auto d_s0_dy = d_s0_x->add_loop("d_s0_dy", -3, 4); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -3, 4); + +//store is: d.stencil((d_s0_dx + 3), (d_s0_dy + 3), (d_s0_x + 3), (d_s0_y + 3)) = 0.000000h + auto hcompute_d_stencil = d_s0_dx->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_y + 3)", "(d_s0_x + 3)", "(d_s0_dy + 3)", "(d_s0_dx + 3)"); + auto d_s1_y = prg.add_loop("d_s1_y", -3, 35); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -3, 35); + auto d_s1_dy = d_s1_x->add_loop("d_s1_dy", -3, 4); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -3, 4); + +//store is: d.stencil((d_s1_dx + 3), (d_s1_dy + 3), (d_s1_x + 3), (d_s1_y + 3)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (d.stencil((d_s1_dx + 3), (d_s1_dy + 3), (d_s1_x + 3), (d_s1_y + 3)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6))))))) + auto hcompute_d_stencil_1 = d_s1_dx->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_y + 3)", "(d_s1_x + 3)", "(d_s1_dy + 3)", "(d_s1_dx + 3)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 6)", "(d_s1_x + 6)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 6)", "((d_s1_dx + d_s1_x) + 6)", "0"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_y + 3)", "(d_s1_x + 3)", "(d_s1_dy + 3)", "(d_s1_dx + 3)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_y = prg.add_loop("blur_d_y_s0_y", 0, 32); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -3, 35); + auto blur_d_y_s0_dy = blur_d_y_s0_x->add_loop("blur_d_y_s0_dy", -3, 4); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -3, 4); + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 3), (blur_d_y_s0_dy + 3), (blur_d_y_s0_x + 3), blur_d_y_s0_y) = 0.000000h + auto hcompute_blur_d_y_stencil = blur_d_y_s0_dx->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "blur_d_y_s0_y", "(blur_d_y_s0_x + 3)", "(blur_d_y_s0_dy + 3)", "(blur_d_y_s0_dx + 3)"); + auto blur_d_y_s1_y = prg.add_loop("blur_d_y_s1_y", 0, 32); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -3, 35); + auto blur_d_y_s1_dy = blur_d_y_s1_x->add_loop("blur_d_y_s1_dy", -3, 4); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -3, 4); + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 6)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 5)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 4)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 3)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 2)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 1)) + (blur_d_y.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y) + d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y)))))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_dx->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 6)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 5)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 4)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 3)", "(blur_d_y_s1_dy + 3)", "(blur_d_y_s1_dx + 3)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_y = prg.add_loop("blur_d_s0_y", 0, 32); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 32); + auto blur_d_s0_dy = blur_d_s0_x->add_loop("blur_d_s0_dy", -3, 4); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -3, 4); + +//store is: blur_d.stencil((blur_d_s0_dx + 3), (blur_d_s0_dy + 3), blur_d_s0_x, blur_d_s0_y) = 0.000000h + auto hcompute_blur_d_stencil = blur_d_s0_dx->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "blur_d_s0_y", "blur_d_s0_x", "(blur_d_s0_dy + 3)", "(blur_d_s0_dx + 3)"); + auto blur_d_s1_y = prg.add_loop("blur_d_s1_y", 0, 32); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 32); + auto blur_d_s1_dy = blur_d_s1_x->add_loop("blur_d_s1_dy", -3, 4); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -3, 4); + +//store is: blur_d.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 6), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 5), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 4), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 3), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 2), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y)))))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_dx->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 6)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 5)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 4)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 3)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 2)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 1)", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 3)", "(blur_d_s1_dx + 3)"); + +//consuming blur_d.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 32); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s0_y_1 = prg.add_loop("non_local_means_sum_s0_y_1", 0, 32); + auto non_local_means_sum_s0_x_1 = non_local_means_sum_s0_y_1->add_loop("non_local_means_sum_s0_x_1", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = 0.000000h + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x_1->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y_1", "non_local_means_sum_s0_x_1"); + auto non_local_means_sum_s0_y_2 = prg.add_loop("non_local_means_sum_s0_y_2", 0, 32); + auto non_local_means_sum_s0_x_2 = non_local_means_sum_s0_y_2->add_loop("non_local_means_sum_s0_x_2", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = 0.000000h + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x_2->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y_2", "non_local_means_sum_s0_x_2"); + auto non_local_means_sum_s0_y_3 = prg.add_loop("non_local_means_sum_s0_y_3", 0, 32); + auto non_local_means_sum_s0_x_3 = non_local_means_sum_s0_y_3->add_loop("non_local_means_sum_s0_x_3", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_3, non_local_means_sum_s0_y_3, 3) = 0.000000h + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s0_x_3->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s0_y_3", "non_local_means_sum_s0_x_3"); + auto non_local_means_sum_s1_y = prg.add_loop("non_local_means_sum_s1_y", 0, 32); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 32); + auto non_local_means_sum_s1_s_dom_y = non_local_means_sum_s1_x->add_loop("non_local_means_sum_s1_s_dom_y", -3, 4); + auto non_local_means_sum_s1_s_dom_x = non_local_means_sum_s1_s_dom_y->add_loop("non_local_means_sum_s1_s_dom_x", -3, 4); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3), non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_s_dom_x->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "(non_local_means_sum_s1_s_dom_y + 3)", "(non_local_means_sum_s1_s_dom_x + 3)"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)", "((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6)", "0"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + auto non_local_means_sum_s1_y_1 = prg.add_loop("non_local_means_sum_s1_y_1", 0, 32); + auto non_local_means_sum_s1_x_1 = non_local_means_sum_s1_y_1->add_loop("non_local_means_sum_s1_x_1", 0, 32); + auto non_local_means_sum_s1_s_dom_y_1 = non_local_means_sum_s1_x_1->add_loop("non_local_means_sum_s1_s_dom_y_1", -3, 4); + auto non_local_means_sum_s1_s_dom_x_1 = non_local_means_sum_s1_s_dom_y_1->add_loop("non_local_means_sum_s1_s_dom_x_1", -3, 4); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 3), (non_local_means_sum_s1_s_dom_y_1 + 3), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)*-1.414062h))*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 6), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 6)))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_s_dom_x_1->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1", "(non_local_means_sum_s1_s_dom_y_1 + 3)", "(non_local_means_sum_s1_s_dom_x_1 + 3)"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 6)", "((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 6)", "1"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + auto non_local_means_sum_s1_y_2 = prg.add_loop("non_local_means_sum_s1_y_2", 0, 32); + auto non_local_means_sum_s1_x_2 = non_local_means_sum_s1_y_2->add_loop("non_local_means_sum_s1_x_2", 0, 32); + auto non_local_means_sum_s1_s_dom_y_2 = non_local_means_sum_s1_x_2->add_loop("non_local_means_sum_s1_s_dom_y_2", -3, 4); + auto non_local_means_sum_s1_s_dom_x_2 = non_local_means_sum_s1_s_dom_y_2->add_loop("non_local_means_sum_s1_s_dom_x_2", -3, 4); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 3), (non_local_means_sum_s1_s_dom_y_2 + 3), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)*-1.414062h))*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 6), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 6)))) + auto hcompute_non_local_means_sum_stencil_6 = non_local_means_sum_s1_s_dom_x_2->add_op("op_hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_function("hcompute_non_local_means_sum_stencil_6"); + hcompute_non_local_means_sum_stencil_6->add_load("blur_d_stencil", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2", "(non_local_means_sum_s1_s_dom_y_2 + 3)", "(non_local_means_sum_s1_s_dom_x_2 + 3)"); + hcompute_non_local_means_sum_stencil_6->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 6)", "((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 6)", "2"); + hcompute_non_local_means_sum_stencil_6->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + hcompute_non_local_means_sum_stencil_6->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + auto non_local_means_sum_s1_y_3 = prg.add_loop("non_local_means_sum_s1_y_3", 0, 32); + auto non_local_means_sum_s1_x_3 = non_local_means_sum_s1_y_3->add_loop("non_local_means_sum_s1_x_3", 0, 32); + auto non_local_means_sum_s1_s_dom_y_3 = non_local_means_sum_s1_x_3->add_loop("non_local_means_sum_s1_s_dom_y_3", -3, 4); + auto non_local_means_sum_s1_s_dom_x_3 = non_local_means_sum_s1_s_dom_y_3->add_loop("non_local_means_sum_s1_s_dom_x_3", -3, 4); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) + exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_3 + 3), (non_local_means_sum_s1_s_dom_y_3 + 3), non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3)*-1.414062h))) + auto hcompute_non_local_means_sum_stencil_7 = non_local_means_sum_s1_s_dom_x_3->add_op("op_hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_function("hcompute_non_local_means_sum_stencil_7"); + hcompute_non_local_means_sum_stencil_7->add_load("blur_d_stencil", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3", "(non_local_means_sum_s1_s_dom_y_3 + 3)", "(non_local_means_sum_s1_s_dom_x_3 + 3)"); + hcompute_non_local_means_sum_stencil_7->add_load("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3"); + hcompute_non_local_means_sum_stencil_7->add_store("non_local_means_sum_stencil", "3", "non_local_means_sum_s1_y_3", "non_local_means_sum_s1_x_3"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 32); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 32); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "3", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + + +// empty diff --git a/example_progs/nlmeans_simple_memory.cpp b/example_progs/nlmeans_simple_memory.cpp new file mode 100644 index 000000000..340fcea45 --- /dev/null +++ b/example_progs/nlmeans_simple_memory.cpp @@ -0,0 +1,464 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog nlmeans_simple_trunc() { + prog prg; + prg.compute_unit_file = "nlmeans_simple_trunc_compute.h"; + prg.name = "nlmeans_simple_trunc"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("d_stencil_out"); + prg.buffer_port_widths["d_stencil_out"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -4, 36); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -4, 36); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_y = prg.add_loop("d_s0_y", -2, 33); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -2, 34); + auto d_s0_dy = d_s0_x->add_loop("d_s0_dy", -2, 2); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -2, 2); + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = (uint16)0 + auto hcompute_d_stencil = d_s0_dx->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_y + 2)", "(d_s0_x + 2)", "(d_s0_dy + 2)", "(d_s0_dx + 2)"); + auto d_s1_y = prg.add_loop("d_s1_y", -2, 33); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -2, 34); + auto d_s1_dy = d_s1_x->add_loop("d_s1_dy", -2, 2); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -2, 2); + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + ((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) + auto hcompute_d_stencil_1 = d_s1_dx->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "1"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + + auto do_s0_y = prg.add_loop("do_s0_y", -2, 33); + auto do_s0_x = do_s0_y->add_loop("do_s0_x", -2, 34); + auto do_s0_dy = do_s0_x->add_loop("do_s0_dy", -2, 2); + auto do_s0_dx = do_s0_dy->add_loop("do_s0_dx", -2, 2); + + auto hcompute_d_stencil_2 = do_s0_dx->add_op("op_hcompute_d_stencil_2"); + hcompute_d_stencil_2->add_function("hcompute_d_stencil_2"); + hcompute_d_stencil_2->add_load("d_stencil", "(do_s0_y + 2)", "(do_s0_x + 2)", "(do_s0_dy + 2)", "(do_s0_dx + 2)"); + hcompute_d_stencil_2->add_store("d_stencil_out", "(do_s0_y + 2)", "(do_s0_x + 2)", "(do_s0_dy + 2)", "(do_s0_dx + 2)"); + + return prg; +} + +prog nlmeans_simple_blur() { + prog prg; + prg.compute_unit_file = "nlmeans_simple_blur_compute.h"; + prg.name = "nlmeans_simple_blur"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("blur_d_stencil_out"); + prg.buffer_port_widths["blur_d_stencil_out"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -4, 36); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -4, 36); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_y = prg.add_loop("d_s0_y", -2, 33); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -2, 34); + auto d_s0_dy = d_s0_x->add_loop("d_s0_dy", -2, 2); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -2, 2); + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = (uint16)0 + auto hcompute_d_stencil = d_s0_dx->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_y + 2)", "(d_s0_x + 2)", "(d_s0_dy + 2)", "(d_s0_dx + 2)"); + auto d_s1_y = prg.add_loop("d_s1_y", -2, 33); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -2, 34); + auto d_s1_dy = d_s1_x->add_loop("d_s1_dy", -2, 2); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -2, 2); + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + ((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) + auto hcompute_d_stencil_1 = d_s1_dx->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "1"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_y = prg.add_loop("blur_d_y_s0_y", 0, 32); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -2, 34); + auto blur_d_y_s0_dy = blur_d_y_s0_x->add_loop("blur_d_y_s0_dy", -2, 2); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = (uint16)0 + auto hcompute_blur_d_y_stencil = blur_d_y_s0_dx->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "blur_d_y_s0_y", "(blur_d_y_s0_x + 2)", "(blur_d_y_s0_dy + 2)", "(blur_d_y_s0_dx + 2)"); + auto blur_d_y_s1_y = prg.add_loop("blur_d_y_s1_y", 0, 32); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -2, 34); + auto blur_d_y_s1_dy = blur_d_y_s1_x->add_loop("blur_d_y_s1_dy", -2, 2); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_dx->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_y = prg.add_loop("blur_d_s0_y", 0, 32); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 32); + auto blur_d_s0_dy = blur_d_s0_x->add_loop("blur_d_s0_dy", -2, 2); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = (uint16)0 + auto hcompute_blur_d_stencil = blur_d_s0_dx->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "blur_d_s0_y", "blur_d_s0_x", "(blur_d_s0_dy + 2)", "(blur_d_s0_dx + 2)"); + auto blur_d_s1_y = prg.add_loop("blur_d_s1_y", 0, 32); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 32); + auto blur_d_s1_dy = blur_d_s1_x->add_loop("blur_d_s1_dy", -2, 2); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_dx->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 1)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 3)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 2)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + +//consuming blur_d.stencil +////producing non_local_means_div.stencil + auto non_local_means_div_s0_y = prg.add_loop("non_local_means_div_s0_y", 0, 32); + auto non_local_means_div_s0_x = non_local_means_div_s0_y->add_loop("non_local_means_div_s0_x", 0, 32); + +//store is: non_local_means_div.stencil(non_local_means_div_s0_x, non_local_means_div_s0_y) = (uint16)0 + auto hcompute_non_local_means_div_stencil = non_local_means_div_s0_x->add_op("op_hcompute_non_local_means_div_stencil"); + hcompute_non_local_means_div_stencil->add_function("hcompute_non_local_means_div_stencil"); + prg.buffer_port_widths["non_local_means_div_stencil"] = 16; + hcompute_non_local_means_div_stencil->add_store("non_local_means_div_stencil", "non_local_means_div_s0_y", "non_local_means_div_s0_x"); + auto non_local_means_div_s1_y = prg.add_loop("non_local_means_div_s1_y", 0, 32); + auto non_local_means_div_s1_x = non_local_means_div_s1_y->add_loop("non_local_means_div_s1_x", 0, 32); + auto non_local_means_div_s1_s_dom_y = non_local_means_div_s1_x->add_loop("non_local_means_div_s1_s_dom_y", -2, 2); + auto non_local_means_div_s1_s_dom_x = non_local_means_div_s1_s_dom_y->add_loop("non_local_means_div_s1_s_dom_x", -2, 2); + +//store is: non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) = (non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) + (blur_d.stencil((non_local_means_div_s1_s_dom_x + 2), (non_local_means_div_s1_s_dom_y + 2), non_local_means_div_s1_x, non_local_means_div_s1_y)*(uint16)16)) + auto hcompute_non_local_means_div_stencil_1 = non_local_means_div_s1_s_dom_x->add_op("op_hcompute_non_local_means_div_stencil_1"); + hcompute_non_local_means_div_stencil_1->add_function("hcompute_non_local_means_div_stencil_1"); + hcompute_non_local_means_div_stencil_1->add_load("blur_d_stencil", "non_local_means_div_s1_y", "non_local_means_div_s1_x", "(non_local_means_div_s1_s_dom_y + 2)", "(non_local_means_div_s1_s_dom_x + 2)"); + hcompute_non_local_means_div_stencil_1->add_load("non_local_means_div_stencil", "non_local_means_div_s1_y", "non_local_means_div_s1_x"); + hcompute_non_local_means_div_stencil_1->add_store("non_local_means_div_stencil", "non_local_means_div_s1_y", "non_local_means_div_s1_x"); + + auto do_s0_y = prg.add_loop("do_s0_y", 0, 32); + auto do_s0_x = do_s0_y->add_loop("do_s0_x", 0, 32); + + auto hcompute_d_stencil_2 = do_s0_x->add_op("op_hcompute_d_stencil_2"); + hcompute_d_stencil_2->add_function("hcompute_d_stencil_2"); + hcompute_d_stencil_2->add_load("non_local_means_div_stencil", "(do_s0_y)", "(do_s0_x )"); + hcompute_d_stencil_2->add_store("blur_d_stencil_out", "(do_s0_y )", "(do_s0_x )"); + + return prg; +} + +prog nlmeans_simple() { + prog prg; + prg.compute_unit_file = "nlmeans_simple_compute.h"; + prg.name = "nlmeans_simple"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_stencil = arg_1; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", -4, 36); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", -4, 36); + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "0"); + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_1 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_stencil_1->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "1"); + hcompute_hw_input_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "1"); + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil_2 = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_stencil_2->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "2"); + hcompute_hw_input_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_stencil", "(hw_input_global_wrapper_s0_y + 4)", "(hw_input_global_wrapper_s0_x + 4)", "2"); + +//consuming hw_input_global_wrapper.stencil +////producing d.stencil + auto d_s0_y = prg.add_loop("d_s0_y", -2, 33); + auto d_s0_x = d_s0_y->add_loop("d_s0_x", -2, 34); + auto d_s0_dy = d_s0_x->add_loop("d_s0_dy", -2, 2); + auto d_s0_dx = d_s0_dy->add_loop("d_s0_dx", -2, 2); + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = (uint16)0 + auto hcompute_d_stencil = d_s0_dx->add_op("op_hcompute_d_stencil"); + hcompute_d_stencil->add_function("hcompute_d_stencil"); + prg.buffer_port_widths["d_stencil"] = 16; + hcompute_d_stencil->add_store("d_stencil", "(d_s0_y + 2)", "(d_s0_x + 2)", "(d_s0_dy + 2)", "(d_s0_dx + 2)"); + auto d_s1_y = prg.add_loop("d_s1_y", -2, 33); + auto d_s1_x = d_s1_y->add_loop("d_s1_x", -2, 34); + auto d_s1_dy = d_s1_x->add_loop("d_s1_dy", -2, 2); + auto d_s1_dx = d_s1_dy->add_loop("d_s1_dx", -2, 2); + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + ((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) + auto hcompute_d_stencil_1 = d_s1_dx->add_op("op_hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_function("hcompute_d_stencil_1"); + hcompute_d_stencil_1->add_load("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "0"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "2"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "(d_s1_y + 4)", "(d_s1_x + 4)", "1"); + hcompute_d_stencil_1->add_load("hw_input_global_wrapper_stencil", "((d_s1_dy + d_s1_y) + 4)", "((d_s1_dx + d_s1_x) + 4)", "1"); + hcompute_d_stencil_1->add_store("d_stencil", "(d_s1_y + 2)", "(d_s1_x + 2)", "(d_s1_dy + 2)", "(d_s1_dx + 2)"); + +//consuming d.stencil +////producing blur_d_y.stencil + auto blur_d_y_s0_y = prg.add_loop("blur_d_y_s0_y", 0, 32); + auto blur_d_y_s0_x = blur_d_y_s0_y->add_loop("blur_d_y_s0_x", -2, 34); + auto blur_d_y_s0_dy = blur_d_y_s0_x->add_loop("blur_d_y_s0_dy", -2, 2); + auto blur_d_y_s0_dx = blur_d_y_s0_dy->add_loop("blur_d_y_s0_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = (uint16)0 + auto hcompute_blur_d_y_stencil = blur_d_y_s0_dx->add_op("op_hcompute_blur_d_y_stencil"); + hcompute_blur_d_y_stencil->add_function("hcompute_blur_d_y_stencil"); + prg.buffer_port_widths["blur_d_y_stencil"] = 16; + hcompute_blur_d_y_stencil->add_store("blur_d_y_stencil", "blur_d_y_s0_y", "(blur_d_y_s0_x + 2)", "(blur_d_y_s0_dy + 2)", "(blur_d_y_s0_dx + 2)"); + auto blur_d_y_s1_y = prg.add_loop("blur_d_y_s1_y", 0, 32); + auto blur_d_y_s1_x = blur_d_y_s1_y->add_loop("blur_d_y_s1_x", -2, 34); + auto blur_d_y_s1_dy = blur_d_y_s1_x->add_loop("blur_d_y_s1_dy", -2, 2); + auto blur_d_y_s1_dx = blur_d_y_s1_dy->add_loop("blur_d_y_s1_dx", -2, 2); + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)))))) + auto hcompute_blur_d_y_stencil_1 = blur_d_y_s1_dx->add_op("op_hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_function("hcompute_blur_d_y_stencil_1"); + hcompute_blur_d_y_stencil_1->add_load("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 1)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 3)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_load("d_stencil", "(blur_d_y_s1_y + 2)", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + hcompute_blur_d_y_stencil_1->add_store("blur_d_y_stencil", "blur_d_y_s1_y", "(blur_d_y_s1_x + 2)", "(blur_d_y_s1_dy + 2)", "(blur_d_y_s1_dx + 2)"); + +//consuming blur_d_y.stencil +////producing blur_d.stencil + auto blur_d_s0_y = prg.add_loop("blur_d_s0_y", 0, 32); + auto blur_d_s0_x = blur_d_s0_y->add_loop("blur_d_s0_x", 0, 32); + auto blur_d_s0_dy = blur_d_s0_x->add_loop("blur_d_s0_dy", -2, 2); + auto blur_d_s0_dx = blur_d_s0_dy->add_loop("blur_d_s0_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = (uint16)0 + auto hcompute_blur_d_stencil = blur_d_s0_dx->add_op("op_hcompute_blur_d_stencil"); + hcompute_blur_d_stencil->add_function("hcompute_blur_d_stencil"); + prg.buffer_port_widths["blur_d_stencil"] = 16; + hcompute_blur_d_stencil->add_store("blur_d_stencil", "blur_d_s0_y", "blur_d_s0_x", "(blur_d_s0_dy + 2)", "(blur_d_s0_dx + 2)"); + auto blur_d_s1_y = prg.add_loop("blur_d_s1_y", 0, 32); + auto blur_d_s1_x = blur_d_s1_y->add_loop("blur_d_s1_x", 0, 32); + auto blur_d_s1_dy = blur_d_s1_x->add_loop("blur_d_s1_dy", -2, 2); + auto blur_d_s1_dx = blur_d_s1_dy->add_loop("blur_d_s1_dx", -2, 2); + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y))))) + auto hcompute_blur_d_stencil_1 = blur_d_s1_dx->add_op("op_hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_function("hcompute_blur_d_stencil_1"); + hcompute_blur_d_stencil_1->add_load("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 1)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 3)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_load("blur_d_y_stencil", "blur_d_s1_y", "(blur_d_s1_x + 2)", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + hcompute_blur_d_stencil_1->add_store("blur_d_stencil", "blur_d_s1_y", "blur_d_s1_x", "(blur_d_s1_dy + 2)", "(blur_d_s1_dx + 2)"); + +//consuming blur_d.stencil +////producing non_local_means_div.stencil + auto non_local_means_div_s0_y = prg.add_loop("non_local_means_div_s0_y", 0, 32); + auto non_local_means_div_s0_x = non_local_means_div_s0_y->add_loop("non_local_means_div_s0_x", 0, 32); + +//store is: non_local_means_div.stencil(non_local_means_div_s0_x, non_local_means_div_s0_y) = (uint16)0 + auto hcompute_non_local_means_div_stencil = non_local_means_div_s0_x->add_op("op_hcompute_non_local_means_div_stencil"); + hcompute_non_local_means_div_stencil->add_function("hcompute_non_local_means_div_stencil"); + prg.buffer_port_widths["non_local_means_div_stencil"] = 16; + hcompute_non_local_means_div_stencil->add_store("non_local_means_div_stencil", "non_local_means_div_s0_y", "non_local_means_div_s0_x"); + auto non_local_means_div_s1_y = prg.add_loop("non_local_means_div_s1_y", 0, 32); + auto non_local_means_div_s1_x = non_local_means_div_s1_y->add_loop("non_local_means_div_s1_x", 0, 32); + auto non_local_means_div_s1_s_dom_y = non_local_means_div_s1_x->add_loop("non_local_means_div_s1_s_dom_y", -2, 2); + auto non_local_means_div_s1_s_dom_x = non_local_means_div_s1_s_dom_y->add_loop("non_local_means_div_s1_s_dom_x", -2, 2); + +//store is: non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) = (non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) + (blur_d.stencil((non_local_means_div_s1_s_dom_x + 2), (non_local_means_div_s1_s_dom_y + 2), non_local_means_div_s1_x, non_local_means_div_s1_y)*(uint16)16)) + auto hcompute_non_local_means_div_stencil_1 = non_local_means_div_s1_s_dom_x->add_op("op_hcompute_non_local_means_div_stencil_1"); + hcompute_non_local_means_div_stencil_1->add_function("hcompute_non_local_means_div_stencil_1"); + hcompute_non_local_means_div_stencil_1->add_load("blur_d_stencil", "non_local_means_div_s1_y", "non_local_means_div_s1_x", "(non_local_means_div_s1_s_dom_y + 2)", "(non_local_means_div_s1_s_dom_x + 2)"); + hcompute_non_local_means_div_stencil_1->add_load("non_local_means_div_stencil", "non_local_means_div_s1_y", "non_local_means_div_s1_x"); + hcompute_non_local_means_div_stencil_1->add_store("non_local_means_div_stencil", "non_local_means_div_s1_y", "non_local_means_div_s1_x"); + +//consuming non_local_means_div.stencil +////producing non_local_means_sum.stencil + auto non_local_means_sum_s0_y = prg.add_loop("non_local_means_sum_s0_y", 0, 32); + auto non_local_means_sum_s0_x = non_local_means_sum_s0_y->add_loop("non_local_means_sum_s0_x", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = (int16)0 + auto hcompute_non_local_means_sum_stencil = non_local_means_sum_s0_x->add_op("op_hcompute_non_local_means_sum_stencil"); + hcompute_non_local_means_sum_stencil->add_function("hcompute_non_local_means_sum_stencil"); + prg.buffer_port_widths["non_local_means_sum_stencil"] = 16; + hcompute_non_local_means_sum_stencil->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s0_y", "non_local_means_sum_s0_x"); + auto non_local_means_sum_s0_y_1 = prg.add_loop("non_local_means_sum_s0_y_1", 0, 32); + auto non_local_means_sum_s0_x_1 = non_local_means_sum_s0_y_1->add_loop("non_local_means_sum_s0_x_1", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = (int16)0 + auto hcompute_non_local_means_sum_stencil_1 = non_local_means_sum_s0_x_1->add_op("op_hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_function("hcompute_non_local_means_sum_stencil_1"); + hcompute_non_local_means_sum_stencil_1->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s0_y_1", "non_local_means_sum_s0_x_1"); + auto non_local_means_sum_s0_y_2 = prg.add_loop("non_local_means_sum_s0_y_2", 0, 32); + auto non_local_means_sum_s0_x_2 = non_local_means_sum_s0_y_2->add_loop("non_local_means_sum_s0_x_2", 0, 32); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = (int16)0 + auto hcompute_non_local_means_sum_stencil_2 = non_local_means_sum_s0_x_2->add_op("op_hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_function("hcompute_non_local_means_sum_stencil_2"); + hcompute_non_local_means_sum_stencil_2->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s0_y_2", "non_local_means_sum_s0_x_2"); + auto non_local_means_sum_s1_y = prg.add_loop("non_local_means_sum_s1_y", 0, 32); + auto non_local_means_sum_s1_x = non_local_means_sum_s1_y->add_loop("non_local_means_sum_s1_x", 0, 32); + auto non_local_means_sum_s1_s_dom_y = non_local_means_sum_s1_x->add_loop("non_local_means_sum_s1_s_dom_y", -2, 2); + auto non_local_means_sum_s1_s_dom_x = non_local_means_sum_s1_s_dom_y->add_loop("non_local_means_sum_s1_s_dom_x", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + int16(((blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)))*(uint16)16))) + auto hcompute_non_local_means_sum_stencil_3 = non_local_means_sum_s1_s_dom_x->add_op("op_hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_function("hcompute_non_local_means_sum_stencil_3"); + hcompute_non_local_means_sum_stencil_3->add_load("blur_d_stencil", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x", "(non_local_means_sum_s1_s_dom_y + 2)", "(non_local_means_sum_s1_s_dom_x + 2)"); + hcompute_non_local_means_sum_stencil_3->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)", "((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 2)", "0"); + hcompute_non_local_means_sum_stencil_3->add_load("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + hcompute_non_local_means_sum_stencil_3->add_store("non_local_means_sum_stencil", "0", "non_local_means_sum_s1_y", "non_local_means_sum_s1_x"); + auto non_local_means_sum_s1_y_1 = prg.add_loop("non_local_means_sum_s1_y_1", 0, 32); + auto non_local_means_sum_s1_x_1 = non_local_means_sum_s1_y_1->add_loop("non_local_means_sum_s1_x_1", 0, 32); + auto non_local_means_sum_s1_s_dom_y_1 = non_local_means_sum_s1_x_1->add_loop("non_local_means_sum_s1_s_dom_y_1", -2, 2); + auto non_local_means_sum_s1_s_dom_x_1 = non_local_means_sum_s1_s_dom_y_1->add_loop("non_local_means_sum_s1_s_dom_x_1", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + int16(((blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)))*(uint16)16))) + auto hcompute_non_local_means_sum_stencil_4 = non_local_means_sum_s1_s_dom_x_1->add_op("op_hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_function("hcompute_non_local_means_sum_stencil_4"); + hcompute_non_local_means_sum_stencil_4->add_load("blur_d_stencil", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1", "(non_local_means_sum_s1_s_dom_y_1 + 2)", "(non_local_means_sum_s1_s_dom_x_1 + 2)"); + hcompute_non_local_means_sum_stencil_4->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)", "((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 2)", "1"); + hcompute_non_local_means_sum_stencil_4->add_load("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + hcompute_non_local_means_sum_stencil_4->add_store("non_local_means_sum_stencil", "1", "non_local_means_sum_s1_y_1", "non_local_means_sum_s1_x_1"); + auto non_local_means_sum_s1_y_2 = prg.add_loop("non_local_means_sum_s1_y_2", 0, 32); + auto non_local_means_sum_s1_x_2 = non_local_means_sum_s1_y_2->add_loop("non_local_means_sum_s1_x_2", 0, 32); + auto non_local_means_sum_s1_s_dom_y_2 = non_local_means_sum_s1_x_2->add_loop("non_local_means_sum_s1_s_dom_y_2", -2, 2); + auto non_local_means_sum_s1_s_dom_x_2 = non_local_means_sum_s1_s_dom_y_2->add_loop("non_local_means_sum_s1_s_dom_x_2", -2, 2); + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + int16(((blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)))*(uint16)16))) + auto hcompute_non_local_means_sum_stencil_5 = non_local_means_sum_s1_s_dom_x_2->add_op("op_hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_function("hcompute_non_local_means_sum_stencil_5"); + hcompute_non_local_means_sum_stencil_5->add_load("blur_d_stencil", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2", "(non_local_means_sum_s1_s_dom_y_2 + 2)", "(non_local_means_sum_s1_s_dom_x_2 + 2)"); + hcompute_non_local_means_sum_stencil_5->add_load("hw_input_global_wrapper_stencil", "((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)", "((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 2)", "2"); + hcompute_non_local_means_sum_stencil_5->add_load("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + hcompute_non_local_means_sum_stencil_5->add_store("non_local_means_sum_stencil", "2", "non_local_means_sum_s1_y_2", "non_local_means_sum_s1_x_2"); + +//consuming non_local_means_sum.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 32); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 32); + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)*int16(non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi))), (int16)255), (int16)0)) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("non_local_means_div_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_load("non_local_means_sum_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "0"); + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)*int16(non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi))), (int16)255), (int16)0)) + auto hcompute_hw_output_stencil_1 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_function("hcompute_hw_output_stencil_1"); + hcompute_hw_output_stencil_1->add_load("non_local_means_div_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_load("non_local_means_sum_stencil", "1", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_1->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "1"); + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)*int16(non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi))), (int16)255), (int16)0)) + auto hcompute_hw_output_stencil_2 = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_function("hcompute_hw_output_stencil_2"); + hcompute_hw_output_stencil_2->add_load("non_local_means_div_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_load("non_local_means_sum_stencil", "2", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil_2->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "2"); + + return prg; +} + + +// empty diff --git a/example_progs/resnet1.cpp b/example_progs/resnet1.cpp index a1c4aa751..1811f6247 100644 --- a/example_progs/resnet1.cpp +++ b/example_progs/resnet1.cpp @@ -1,5 +1,385 @@ #include "prog.h" +prog resnet1_docker() { + prog prg; + prg.compute_unit_file = "resnet1_compute.h"; + prg.name = "resnet1_docker"; + +// Stencil &input_host_stencil = arg_0; + prg.add_input("input_host_stencil"); + prg.buffer_port_widths["input_host_stencil"] = 16; +// Stencil &kernel_host_stencil = arg_1; + prg.add_input("kernel_host_stencil"); + prg.buffer_port_widths["kernel_host_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing input_glb.stencil + auto input_glb_s0_y = prg.add_loop("input_glb_s0_y", 0, 53); + auto input_glb_s0_x = input_glb_s0_y->add_loop("input_glb_s0_x", 0, 61); + auto input_glb_s0_z = input_glb_s0_x->add_loop("input_glb_s0_z", 0, 3); + +//store is: input_glb.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) = input_host.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil = input_glb_s0_z->add_op("op_hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_function("hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z"); + prg.buffer_port_widths["input_glb_stencil"] = 16; + hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z"); + +//consuming input_glb.stencil +////producing kernel_glb.stencil + auto kernel_glb_s0_y = prg.add_loop("kernel_glb_s0_y", 0, 7); + auto kernel_glb_s0_x = kernel_glb_s0_y->add_loop("kernel_glb_s0_x", 0, 7); + auto kernel_glb_s0_w = kernel_glb_s0_x->add_loop("kernel_glb_s0_w", 0, 64); + auto kernel_glb_s0_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z", 0, 3); + +//store is: kernel_glb.stencil(kernel_glb_s0_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(kernel_glb_s0_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) + auto hcompute_kernel_glb_stencil = kernel_glb_s0_z->add_op("op_hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_function("hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z"); + prg.buffer_port_widths["kernel_glb_stencil"] = 16; + hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z"); + +//consuming kernel_glb.stencil +////producing output_glb.stencil + auto output_glb_s0_y_y_glb = prg.add_loop("output_glb_s0_y_y_glb", 0, 2); + auto output_glb_s0_x_x_glb = output_glb_s0_y_y_glb->add_loop("output_glb_s0_x_x_glb", 0, 2); + auto output_glb_s0_w_w_glb = output_glb_s0_x_x_glb->add_loop("output_glb_s0_w_w_glb", 0, 4); +////producing output_cgra.stencil + auto output_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("output_cgra_s0_y", 0, 12); + auto output_cgra_s0_x = output_cgra_s0_y->add_loop("output_cgra_s0_x", 0, 14); + +//store is: output_cgra.stencil(0, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil"); + hcompute_output_cgra_stencil->add_function("hcompute_output_cgra_stencil"); + prg.buffer_port_widths["output_cgra_stencil"] = 16; + hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "0"); + +//store is: output_cgra.stencil(1, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_1 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_function("hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "1"); + +//store is: output_cgra.stencil(2, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_2 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_function("hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "2"); + +//store is: output_cgra.stencil(3, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_3 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_function("hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "3"); + +//store is: output_cgra.stencil(4, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_4 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_function("hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "4"); + +//store is: output_cgra.stencil(5, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_5 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_function("hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "5"); + +//store is: output_cgra.stencil(6, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_6 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_function("hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "6"); + +//store is: output_cgra.stencil(7, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_7 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_function("hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "7"); + +//store is: output_cgra.stencil(8, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_8 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_function("hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8"); + +//store is: output_cgra.stencil(9, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_9 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_function("hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "9"); + +//store is: output_cgra.stencil(10, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_10 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_function("hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "10"); + +//store is: output_cgra.stencil(11, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_11 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_function("hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "11"); + +//store is: output_cgra.stencil(12, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_12 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_function("hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "12"); + +//store is: output_cgra.stencil(13, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_13 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_function("hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "13"); + +//store is: output_cgra.stencil(14, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_14 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_function("hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "14"); + +//store is: output_cgra.stencil(15, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_15 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_function("hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "15"); +////producing input_cgra.stencil + auto input_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("input_cgra_s0_y", 0, 29); + auto input_cgra_s0_x = input_cgra_s0_y->add_loop("input_cgra_s0_x", 0, 33); + auto input_cgra_s0_z_z_cgra = input_cgra_s0_x->add_loop("input_cgra_s0_z_z_cgra", 0, 3); + +//store is: input_cgra.stencil(input_cgra_s0_z_z_cgra, input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(input_cgra_s0_z_z_cgra, ((output_glb_s0_x_x_glb*28) + input_cgra_s0_x), ((output_glb_s0_y_y_glb*28) + input_cgra_s0_y)) + auto hcompute_input_cgra_stencil = input_cgra_s0_z_z_cgra->add_op("op_hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_function("hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_load("input_glb_stencil", "((output_glb_s0_y_y_glb*24) + input_cgra_s0_y)", "((output_glb_s0_x_x_glb*28) + input_cgra_s0_x)", "input_cgra_s0_z_z_cgra"); + prg.buffer_port_widths["input_cgra_stencil"] = 16; + hcompute_input_cgra_stencil->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "input_cgra_s0_z_z_cgra"); + +//consuming input_cgra.stencil +////producing kernel_cgra.stencil + auto kernel_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("kernel_cgra_s0_y", 0, 7); + auto kernel_cgra_s0_x = kernel_cgra_s0_y->add_loop("kernel_cgra_s0_x", 0, 7); + auto kernel_cgra_s0_w_w_cgra = kernel_cgra_s0_x->add_loop("kernel_cgra_s0_w_w_cgra", 0, 16); + auto kernel_cgra_s0_z_z_cgra = kernel_cgra_s0_w_w_cgra->add_loop("kernel_cgra_s0_z_z_cgra", 0, 3); + +//store is: kernel_cgra.stencil(kernel_cgra_s0_z_z_cgra, kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(kernel_cgra_s0_z_z_cgra, ((output_glb_s0_w_w_glb*16) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) + auto hcompute_kernel_cgra_stencil = kernel_cgra_s0_z_z_cgra->add_op("op_hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_function("hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "((output_glb_s0_w_w_glb*16) + kernel_cgra_s0_w_w_cgra)", "kernel_cgra_s0_z_z_cgra"); + prg.buffer_port_widths["kernel_cgra_stencil"] = 16; + hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "kernel_cgra_s0_z_z_cgra"); + +//consuming kernel_cgra.stencil + auto output_cgra_s1_r_y = output_glb_s0_w_w_glb->add_loop("output_cgra_s1_r_y", 0, 7); + auto output_cgra_s1_r_x = output_cgra_s1_r_y->add_loop("output_cgra_s1_r_x", 0, 7); + auto output_cgra_s1_y = output_cgra_s1_r_x->add_loop("output_cgra_s1_y", 0, 12); + auto output_cgra_s1_x = output_cgra_s1_y->add_loop("output_cgra_s1_x", 0, 14); + +//store is: output_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_16 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_16"); + hcompute_output_cgra_stencil_16->add_function("hcompute_output_cgra_stencil_16"); + hcompute_output_cgra_stencil_16->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_16->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_16->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_16->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "0"); + hcompute_output_cgra_stencil_16->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "2"); + hcompute_output_cgra_stencil_16->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "1"); + hcompute_output_cgra_stencil_16->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_16->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + +//store is: output_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_17 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_17"); + hcompute_output_cgra_stencil_17->add_function("hcompute_output_cgra_stencil_17"); + hcompute_output_cgra_stencil_17->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_17->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_17->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_17->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "0"); + hcompute_output_cgra_stencil_17->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "2"); + hcompute_output_cgra_stencil_17->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "1"); + hcompute_output_cgra_stencil_17->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_17->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + +//store is: output_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_18 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_18"); + hcompute_output_cgra_stencil_18->add_function("hcompute_output_cgra_stencil_18"); + hcompute_output_cgra_stencil_18->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_18->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_18->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_18->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "0"); + hcompute_output_cgra_stencil_18->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "2"); + hcompute_output_cgra_stencil_18->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "1"); + hcompute_output_cgra_stencil_18->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_18->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + +//store is: output_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_19 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_19"); + hcompute_output_cgra_stencil_19->add_function("hcompute_output_cgra_stencil_19"); + hcompute_output_cgra_stencil_19->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_19->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_19->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_19->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "0"); + hcompute_output_cgra_stencil_19->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "2"); + hcompute_output_cgra_stencil_19->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "1"); + hcompute_output_cgra_stencil_19->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_19->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + +//store is: output_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_20 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_20"); + hcompute_output_cgra_stencil_20->add_function("hcompute_output_cgra_stencil_20"); + hcompute_output_cgra_stencil_20->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_20->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_20->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_20->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "0"); + hcompute_output_cgra_stencil_20->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "2"); + hcompute_output_cgra_stencil_20->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "1"); + hcompute_output_cgra_stencil_20->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_20->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + +//store is: output_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_21 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_21"); + hcompute_output_cgra_stencil_21->add_function("hcompute_output_cgra_stencil_21"); + hcompute_output_cgra_stencil_21->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_21->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_21->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_21->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "0"); + hcompute_output_cgra_stencil_21->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "2"); + hcompute_output_cgra_stencil_21->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "1"); + hcompute_output_cgra_stencil_21->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_21->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + +//store is: output_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_22 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_22"); + hcompute_output_cgra_stencil_22->add_function("hcompute_output_cgra_stencil_22"); + hcompute_output_cgra_stencil_22->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_22->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_22->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_22->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "0"); + hcompute_output_cgra_stencil_22->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "2"); + hcompute_output_cgra_stencil_22->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "1"); + hcompute_output_cgra_stencil_22->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_22->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + +//store is: output_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_23 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_23"); + hcompute_output_cgra_stencil_23->add_function("hcompute_output_cgra_stencil_23"); + hcompute_output_cgra_stencil_23->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_23->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_23->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_23->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "0"); + hcompute_output_cgra_stencil_23->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "2"); + hcompute_output_cgra_stencil_23->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "1"); + hcompute_output_cgra_stencil_23->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_23->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + +//store is: output_cgra.stencil(8, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 8, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(8, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 8, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 8, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_24 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_24"); + hcompute_output_cgra_stencil_24->add_function("hcompute_output_cgra_stencil_24"); + hcompute_output_cgra_stencil_24->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_24->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_24->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_24->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8", "0"); + hcompute_output_cgra_stencil_24->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8", "2"); + hcompute_output_cgra_stencil_24->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8", "1"); + hcompute_output_cgra_stencil_24->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8"); + hcompute_output_cgra_stencil_24->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8"); + +//store is: output_cgra.stencil(9, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 9, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(9, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 9, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 9, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_25 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_25"); + hcompute_output_cgra_stencil_25->add_function("hcompute_output_cgra_stencil_25"); + hcompute_output_cgra_stencil_25->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_25->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_25->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_25->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "9", "0"); + hcompute_output_cgra_stencil_25->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "9", "2"); + hcompute_output_cgra_stencil_25->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "9", "1"); + hcompute_output_cgra_stencil_25->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "9"); + hcompute_output_cgra_stencil_25->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "9"); + +//store is: output_cgra.stencil(10, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 10, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(10, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 10, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 10, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_26 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_26"); + hcompute_output_cgra_stencil_26->add_function("hcompute_output_cgra_stencil_26"); + hcompute_output_cgra_stencil_26->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_26->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_26->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_26->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "10", "0"); + hcompute_output_cgra_stencil_26->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "10", "2"); + hcompute_output_cgra_stencil_26->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "10", "1"); + hcompute_output_cgra_stencil_26->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "10"); + hcompute_output_cgra_stencil_26->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "10"); + +//store is: output_cgra.stencil(11, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 11, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(11, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 11, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 11, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_27 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_27"); + hcompute_output_cgra_stencil_27->add_function("hcompute_output_cgra_stencil_27"); + hcompute_output_cgra_stencil_27->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_27->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_27->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_27->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "11", "0"); + hcompute_output_cgra_stencil_27->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "11", "2"); + hcompute_output_cgra_stencil_27->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "11", "1"); + hcompute_output_cgra_stencil_27->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "11"); + hcompute_output_cgra_stencil_27->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "11"); + +//store is: output_cgra.stencil(12, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 12, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(12, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 12, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 12, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_28 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_28"); + hcompute_output_cgra_stencil_28->add_function("hcompute_output_cgra_stencil_28"); + hcompute_output_cgra_stencil_28->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_28->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_28->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_28->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "12", "0"); + hcompute_output_cgra_stencil_28->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "12", "2"); + hcompute_output_cgra_stencil_28->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "12", "1"); + hcompute_output_cgra_stencil_28->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "12"); + hcompute_output_cgra_stencil_28->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "12"); + +//store is: output_cgra.stencil(13, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 13, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(13, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 13, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 13, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_29 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_29"); + hcompute_output_cgra_stencil_29->add_function("hcompute_output_cgra_stencil_29"); + hcompute_output_cgra_stencil_29->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_29->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_29->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_29->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "13", "0"); + hcompute_output_cgra_stencil_29->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "13", "2"); + hcompute_output_cgra_stencil_29->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "13", "1"); + hcompute_output_cgra_stencil_29->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "13"); + hcompute_output_cgra_stencil_29->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "13"); + +//store is: output_cgra.stencil(14, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 14, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(14, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 14, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 14, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_30 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_30"); + hcompute_output_cgra_stencil_30->add_function("hcompute_output_cgra_stencil_30"); + hcompute_output_cgra_stencil_30->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_30->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_30->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_30->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "14", "0"); + hcompute_output_cgra_stencil_30->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "14", "2"); + hcompute_output_cgra_stencil_30->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "14", "1"); + hcompute_output_cgra_stencil_30->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "14"); + hcompute_output_cgra_stencil_30->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "14"); + +//store is: output_cgra.stencil(15, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 15, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(15, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(2, 15, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(1, 15, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y)))))) + auto hcompute_output_cgra_stencil_31 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_31"); + hcompute_output_cgra_stencil_31->add_function("hcompute_output_cgra_stencil_31"); + hcompute_output_cgra_stencil_31->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_31->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_31->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_31->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "15", "0"); + hcompute_output_cgra_stencil_31->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "15", "2"); + hcompute_output_cgra_stencil_31->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "15", "1"); + hcompute_output_cgra_stencil_31->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "15"); + hcompute_output_cgra_stencil_31->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "15"); + +//consuming output_cgra.stencil + auto output_glb_s0_y_y_cgra = output_glb_s0_w_w_glb->add_loop("output_glb_s0_y_y_cgra", 0, 12); + auto output_glb_s0_x_x_cgra = output_glb_s0_y_y_cgra->add_loop("output_glb_s0_x_x_cgra", 0, 14); + auto output_glb_s0_w_w_cgra = output_glb_s0_x_x_cgra->add_loop("output_glb_s0_w_w_cgra", 0, 16); + +//store is: output_glb.stencil(((output_glb_s0_w_w_glb*16) + output_glb_s0_w_w_cgra), ((output_glb_s0_x_x_glb*14) + output_glb_s0_x_x_cgra), ((output_glb_s0_y_y_glb*14) + output_glb_s0_y_y_cgra)) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) + auto hcompute_output_glb_stencil = output_glb_s0_w_w_cgra->add_op("op_hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_function("hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "output_glb_s0_w_w_cgra"); + prg.buffer_port_widths["output_glb_stencil"] = 16; + hcompute_output_glb_stencil->add_store("output_glb_stencil", "((output_glb_s0_y_y_glb*12) + output_glb_s0_y_y_cgra)", "((output_glb_s0_x_x_glb*14) + output_glb_s0_x_x_cgra)", "((output_glb_s0_w_w_glb*16) + output_glb_s0_w_w_cgra)"); + +//consuming output_glb.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 24); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 28); + auto hw_output_s0_w = hw_output_s0_x_xi->add_loop("hw_output_s0_w", 0, 64); + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_w->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + + return prg; +} + prog resnet1() { prog prg; prg.compute_unit_file = "resnet1_compute.h"; diff --git a/example_progs/resnet5_glb_unroll.cpp b/example_progs/resnet5_glb_unroll.cpp new file mode 100644 index 000000000..f1f81613f --- /dev/null +++ b/example_progs/resnet5_glb_unroll.cpp @@ -0,0 +1,352 @@ +#include "prog.h" + +prog resnet5_glb_unroll() { + prog prg; + prg.compute_unit_file = "resnet5_glb_unroll_compute.h"; + prg.name = "resnet5_glb_unroll"; + +// Stencil &input_host_stencil = arg_0; + prg.add_input("input_host_stencil"); + prg.buffer_port_widths["input_host_stencil"] = 16; +// Stencil &kernel_host_stencil = arg_1; + prg.add_input("kernel_host_stencil"); + prg.buffer_port_widths["kernel_host_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing input_glb.stencil + auto input_glb_s0_y = prg.add_loop("input_glb_s0_y", 0, 15); + auto input_glb_s0_x = input_glb_s0_y->add_loop("input_glb_s0_x", 0, 15); + auto input_glb_s0_z_z = input_glb_s0_x->add_loop("input_glb_s0_z_z", 0, 8); + +//store is: input_glb.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) = input_host.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_function("hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z_z*2)"); + prg.buffer_port_widths["input_glb_stencil"] = 16; + hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z_z*2)"); + +//store is: input_glb.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil_1 = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil_1"); + hcompute_input_glb_stencil_1->add_function("hcompute_input_glb_stencil_1"); + hcompute_input_glb_stencil_1->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*2) + 1)"); + hcompute_input_glb_stencil_1->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*2) + 1)"); + +//consuming input_glb.stencil +////producing kernel_glb.stencil + auto kernel_glb_s0_y = prg.add_loop("kernel_glb_s0_y", 0, 3); + auto kernel_glb_s0_x = kernel_glb_s0_y->add_loop("kernel_glb_s0_x", 0, 3); + auto kernel_glb_s0_w = kernel_glb_s0_x->add_loop("kernel_glb_s0_w", 0, 64); + auto kernel_glb_s0_z_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z_z", 0, 8); + +//store is: kernel_glb.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) + auto hcompute_kernel_glb_stencil = kernel_glb_s0_z_z->add_op("op_hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_function("hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "(kernel_glb_s0_z_z*2)"); + prg.buffer_port_widths["kernel_glb_stencil"] = 16; + hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "(kernel_glb_s0_z_z*2)"); + +//store is: kernel_glb.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) + auto hcompute_kernel_glb_stencil_1 = kernel_glb_s0_z_z->add_op("op_hcompute_kernel_glb_stencil_1"); + hcompute_kernel_glb_stencil_1->add_function("hcompute_kernel_glb_stencil_1"); + hcompute_kernel_glb_stencil_1->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "((kernel_glb_s0_z_z*2) + 1)"); + hcompute_kernel_glb_stencil_1->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "((kernel_glb_s0_z_z*2) + 1)"); + +//consuming kernel_glb.stencil +////producing output_glb.stencil +////producing output_cgra.stencil + auto output_cgra_s0_y = prg.add_loop("output_cgra_s0_y", 0, 7); + auto output_cgra_s0_x = output_cgra_s0_y->add_loop("output_cgra_s0_x", 0, 7); + auto output_cgra_s0_w_w = output_cgra_s0_x->add_loop("output_cgra_s0_w_w", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil"); + hcompute_output_cgra_stencil->add_function("hcompute_output_cgra_stencil"); + prg.buffer_port_widths["output_cgra_stencil"] = 16; + hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "(output_cgra_s0_w_w*8)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_1 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_function("hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_2 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_function("hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_3 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_function("hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_4 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_function("hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_5 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_function("hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_6 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_function("hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_7 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_function("hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 7)"); + auto output_cgra_s1_r_z_rz_glb = prg.add_loop("output_cgra_s1_r_z_rz_glb", 0, 2); +////producing input_cgra.stencil + auto input_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("input_cgra_s0_y", 0, 15); + auto input_cgra_s0_x = input_cgra_s0_y->add_loop("input_cgra_s0_x", 0, 15); + auto input_cgra_s0_z_z_cgra_z_cgra = input_cgra_s0_x->add_loop("input_cgra_s0_z_z_cgra_z_cgra", 0, 4); + +//store is: input_cgra.stencil((input_cgra_s0_z_z_cgra_z_cgra*2), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_function("hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "(((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2)"); + prg.buffer_port_widths["input_cgra_stencil"] = 16; + hcompute_input_cgra_stencil->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "(input_cgra_s0_z_z_cgra_z_cgra*2)"); + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*2) + 1), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2) + 1), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil_1 = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil_1"); + hcompute_input_cgra_stencil_1->add_function("hcompute_input_cgra_stencil_1"); + hcompute_input_cgra_stencil_1->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2) + 1)"); + hcompute_input_cgra_stencil_1->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((input_cgra_s0_z_z_cgra_z_cgra*2) + 1)"); + +//consuming input_cgra.stencil +////producing kernel_cgra.stencil + auto kernel_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("kernel_cgra_s0_y", 0, 3); + auto kernel_cgra_s0_x = kernel_cgra_s0_y->add_loop("kernel_cgra_s0_x", 0, 3); + auto kernel_cgra_s0_w_w_cgra = kernel_cgra_s0_x->add_loop("kernel_cgra_s0_w_w_cgra", 0, 64); + auto kernel_cgra_s0_z_z_cgra_z_cgra = kernel_cgra_s0_w_w_cgra->add_loop("kernel_cgra_s0_z_z_cgra_z_cgra", 0, 4); + +//store is: kernel_cgra.stencil((kernel_cgra_s0_z_z_cgra_z_cgra*2), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) + auto hcompute_kernel_cgra_stencil = kernel_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_function("hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "(((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2)"); + prg.buffer_port_widths["kernel_cgra_stencil"] = 16; + hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "(kernel_cgra_s0_z_z_cgra_z_cgra*2)"); + +//store is: kernel_cgra.stencil(((kernel_cgra_s0_z_z_cgra_z_cgra*2) + 1), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2) + 1), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) + auto hcompute_kernel_cgra_stencil_1 = kernel_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_kernel_cgra_stencil_1"); + hcompute_kernel_cgra_stencil_1->add_function("hcompute_kernel_cgra_stencil_1"); + hcompute_kernel_cgra_stencil_1->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2) + 1)"); + hcompute_kernel_cgra_stencil_1->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "((kernel_cgra_s0_z_z_cgra_z_cgra*2) + 1)"); + +//consuming kernel_cgra.stencil + auto output_cgra_s1_r_y = output_cgra_s1_r_z_rz_glb->add_loop("output_cgra_s1_r_y", 0, 3); + auto output_cgra_s1_r_x = output_cgra_s1_r_y->add_loop("output_cgra_s1_r_x", 0, 3); + auto output_cgra_s1_y = output_cgra_s1_r_x->add_loop("output_cgra_s1_y", 0, 7); + auto output_cgra_s1_x = output_cgra_s1_y->add_loop("output_cgra_s1_x", 0, 7); + auto output_cgra_s1_w_w = output_cgra_s1_x->add_loop("output_cgra_s1_w_w", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_8 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_function("hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "0"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "1"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "2"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "3"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "4"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "5"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "7"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "6"); + hcompute_output_cgra_stencil_8->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w*8)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_9 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_function("hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "1"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "2"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "3"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "4"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "5"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "7"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "6"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "0"); + hcompute_output_cgra_stencil_9->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_10 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_function("hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "0"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "1"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "2"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "3"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "4"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "5"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "7"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "6"); + hcompute_output_cgra_stencil_10->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_11 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_function("hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "0"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "1"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "2"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "3"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "4"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "5"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "7"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "6"); + hcompute_output_cgra_stencil_11->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_12 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_function("hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "0"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "1"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "2"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "3"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "4"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "5"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "7"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "6"); + hcompute_output_cgra_stencil_12->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_13 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_function("hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "0"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "1"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "2"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "3"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "4"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "5"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "7"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "6"); + hcompute_output_cgra_stencil_13->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_14 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_function("hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "0"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "1"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "2"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "3"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "4"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "5"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "7"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "6"); + hcompute_output_cgra_stencil_14->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) + auto hcompute_output_cgra_stencil_15 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_function("hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "0"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "1"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "2"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "3"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "4"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "0"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "1"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "2"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "3"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "4"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "5"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "7"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "6"); + hcompute_output_cgra_stencil_15->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 7)"); + +//consuming output_cgra.stencil + auto output_glb_s0_y_y_cgra = prg.add_loop("output_glb_s0_y_y_cgra", 0, 7); + auto output_glb_s0_x_x_cgra = output_glb_s0_y_y_cgra->add_loop("output_glb_s0_x_x_cgra", 0, 7); + auto output_glb_s0_w_w_cgra = output_glb_s0_x_x_cgra->add_loop("output_glb_s0_w_w_cgra", 0, 64); + +//store is: output_glb.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) + auto hcompute_output_glb_stencil = output_glb_s0_w_w_cgra->add_op("op_hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_function("hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "output_glb_s0_w_w_cgra"); + prg.buffer_port_widths["output_glb_stencil"] = 16; + hcompute_output_glb_stencil->add_store("output_glb_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "output_glb_s0_w_w_cgra"); + +//consuming output_glb.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 7); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 7); + auto hw_output_s0_w = hw_output_s0_x_xi->add_loop("hw_output_s0_w", 0, 64); + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_w->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + + return prg; +} + + +// in_img=14 pad=1 ksize=3 stride=2 n_ic=16 n_oc=64 k_ic=8 k_oc=8 m_ic=1 m_oc=8 diff --git a/example_progs/resnet5_unroll.cpp b/example_progs/resnet5_unroll.cpp index 88b44465d..15c1da8b2 100644 --- a/example_progs/resnet5_unroll.cpp +++ b/example_progs/resnet5_unroll.cpp @@ -18,30 +18,28 @@ prog resnet5_1_unroll_cyclic() { ////producing input_glb.stencil auto input_glb_s0_y = prg.add_loop("input_glb_s0_y", 0, 16); auto input_glb_s0_x = input_glb_s0_y->add_loop("input_glb_s0_x", 0, 16); - auto input_glb_s0_z = input_glb_s0_x->add_loop("input_glb_s0_z", 0, 8); - auto input_glb_s0_z_z = input_glb_s0_z->add_loop("input_glb_s0_z_z", 0, 2); + auto input_glb_s0_z = input_glb_s0_x->add_loop("input_glb_s0_z", 0, 16); //store is: input_glb.stencil((input_glb_s0_z + 256), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) - auto hcompute_input_glb_stencil = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil"); + auto hcompute_input_glb_stencil = input_glb_s0_z->add_op("op_hcompute_input_glb_stencil"); hcompute_input_glb_stencil->add_function("hcompute_input_glb_stencil"); - hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z", "input_glb_s0_z_z"); + hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z"); prg.buffer_port_widths["input_glb_stencil"] = 16; - hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z)", "input_glb_s0_z_z"); + hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z)"); //consuming input_glb.stencil ////producing kernel_glb.stencil auto kernel_glb_s0_y = prg.add_loop("kernel_glb_s0_y", 0, 3); auto kernel_glb_s0_x = kernel_glb_s0_y->add_loop("kernel_glb_s0_x", 0, 3); auto kernel_glb_s0_w = kernel_glb_s0_x->add_loop("kernel_glb_s0_w", 0, 64); - auto kernel_glb_s0_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z", 0, 8); - auto kernel_glb_s0_z_z = kernel_glb_s0_z->add_loop("kernel_glb_s0_z_z", 0, 2); + auto kernel_glb_s0_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z", 0, 16); //store is: kernel_glb.stencil(kernel_glb_s0_z, (kernel_glb_s0_w + 504), kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(kernel_glb_s0_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) - auto hcompute_kernel_glb_stencil = kernel_glb_s0_z_z->add_op("op_hcompute_kernel_glb_stencil"); + auto hcompute_kernel_glb_stencil = kernel_glb_s0_z->add_op("op_hcompute_kernel_glb_stencil"); hcompute_kernel_glb_stencil->add_function("hcompute_kernel_glb_stencil"); - hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z", "kernel_glb_s0_z_z"); + hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z"); prg.buffer_port_widths["kernel_glb_stencil"] = 16; - hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "(kernel_glb_s0_w)", "kernel_glb_s0_z", "kernel_glb_s0_z_z"); + hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "(kernel_glb_s0_w)", "kernel_glb_s0_z"); //consuming kernel_glb.stencil ////producing output_glb.stencil @@ -49,48 +47,48 @@ prog resnet5_1_unroll_cyclic() { ////producing output_cgra.stencil auto output_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("output_cgra_s0_y", 0, 7); auto output_cgra_s0_x = output_cgra_s0_y->add_loop("output_cgra_s0_x", 0, 7); - auto output_cgra_s0_w = output_cgra_s0_x->add_loop("output_cgra_s0_w", 0, 4); + auto output_cgra_s0_w = output_cgra_s0_x->add_loop("output_cgra_s0_w", 0, 8); //store is: output_cgra.stencil(0, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil"); hcompute_output_cgra_stencil->add_function("hcompute_output_cgra_stencil"); prg.buffer_port_widths["output_cgra_stencil"] = 16; - hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "0"); + hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w"); //store is: output_cgra.stencil(1, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil_1 = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil_1"); hcompute_output_cgra_stencil_1->add_function("hcompute_output_cgra_stencil_1"); - hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "1"); + hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w+1"); //store is: output_cgra.stencil(2, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil_2 = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil_2"); hcompute_output_cgra_stencil_2->add_function("hcompute_output_cgra_stencil_2"); - hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "2"); + hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w+2"); //store is: output_cgra.stencil(3, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil_3 = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil_3"); hcompute_output_cgra_stencil_3->add_function("hcompute_output_cgra_stencil_3"); - hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "3"); + hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w+3"); //store is: output_cgra.stencil(4, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil_4 = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil_4"); hcompute_output_cgra_stencil_4->add_function("hcompute_output_cgra_stencil_4"); - hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "4"); + hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w+4"); //store is: output_cgra.stencil(5, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil_5 = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil_5"); hcompute_output_cgra_stencil_5->add_function("hcompute_output_cgra_stencil_5"); - hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "5"); + hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w+5"); //store is: output_cgra.stencil(6, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil_6 = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil_6"); hcompute_output_cgra_stencil_6->add_function("hcompute_output_cgra_stencil_6"); - hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "6"); + hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w+6"); //store is: output_cgra.stencil(7, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 auto hcompute_output_cgra_stencil_7 = output_cgra_s0_w->add_op("op_hcompute_output_cgra_stencil_7"); hcompute_output_cgra_stencil_7->add_function("hcompute_output_cgra_stencil_7"); - hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "output_cgra_s0_w", "7"); + hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "8*output_cgra_s0_w+7"); auto output_cgra_s1_r_z_rz_glb = output_glb_s0_w_w_glb->add_loop("output_cgra_s1_r_z_rz_glb", 0, 2); ////producing input_cgra.stencil auto input_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("input_cgra_s0_y", 0, 16); @@ -100,14 +98,14 @@ prog resnet5_1_unroll_cyclic() { //store is: input_cgra.stencil((input_cgra_s0_z_z_z_cgra*2), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_z_cgra)*2) + 248), input_cgra_s0_x, input_cgra_s0_y) auto hcompute_input_cgra_stencil = input_cgra_s0_z_z_z_cgra->add_op("op_hcompute_input_cgra_stencil"); hcompute_input_cgra_stencil->add_function("hcompute_input_cgra_stencil"); - hcompute_input_cgra_stencil->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_z_cgra)", "0"); + hcompute_input_cgra_stencil->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_z_cgra*2)"); prg.buffer_port_widths["input_cgra_stencil"] = 16; hcompute_input_cgra_stencil->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "input_cgra_s0_z_z_z_cgra*2" ); //store is: input_cgra.stencil(((input_cgra_s0_z_z_z_cgra*2) + 1), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_z_cgra)*2) + 249), input_cgra_s0_x, input_cgra_s0_y) auto hcompute_input_cgra_stencil_1 = input_cgra_s0_z_z_z_cgra->add_op("op_hcompute_input_cgra_stencil_1"); hcompute_input_cgra_stencil_1->add_function("hcompute_input_cgra_stencil_1"); - hcompute_input_cgra_stencil_1->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_z_cgra)))", "1"); + hcompute_input_cgra_stencil_1->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_z_cgra*2)+1"); hcompute_input_cgra_stencil_1->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((input_cgra_s0_z_z_z_cgra*2 + 1))"); //consuming input_cgra.stencil @@ -115,21 +113,21 @@ prog resnet5_1_unroll_cyclic() { auto kernel_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("kernel_cgra_s0_y", 0, 3); auto kernel_cgra_s0_x = kernel_cgra_s0_y->add_loop("kernel_cgra_s0_x", 0, 3); auto kernel_cgra_s0_w_cgra = kernel_cgra_s0_x->add_loop("kernel_cgra_s0_w_cgra", 0, 4); - auto kernel_cgra_s0_w_w_cgra = kernel_cgra_s0_w_cgra->add_loop("kernel_cgra_s0_w_w_cgra", 0, 4); + auto kernel_cgra_s0_w_w_cgra = kernel_cgra_s0_w_cgra->add_loop("kernel_cgra_s0_w_w_cgra", 0, 8); auto kernel_cgra_s0_z_z_z_cgra = kernel_cgra_s0_w_w_cgra->add_loop("kernel_cgra_s0_z_z_z_cgra", 0, 4); //store is: kernel_cgra.stencil((kernel_cgra_s0_z_z_z_cgra*2), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_z_cgra)*2) + -8), (((output_glb_s0_w_w_glb*8) + kernel_cgra_s0_w_w_cgra) + 504), kernel_cgra_s0_x, kernel_cgra_s0_y) auto hcompute_kernel_cgra_stencil = kernel_cgra_s0_z_z_z_cgra->add_op("op_hcompute_kernel_cgra_stencil"); hcompute_kernel_cgra_stencil->add_function("hcompute_kernel_cgra_stencil"); - hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "(((output_glb_s0_w_w_glb*32) + (kernel_cgra_s0_w_cgra*8) + kernel_cgra_s0_w_w_cgra))", "((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_z_cgra)))", "0"); + hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "(((output_glb_s0_w_w_glb*32) + (kernel_cgra_s0_w_cgra*8) + kernel_cgra_s0_w_w_cgra))", "((output_cgra_s1_r_z_rz_glb*8) + kernel_cgra_s0_z_z_z_cgra*2)"); prg.buffer_port_widths["kernel_cgra_stencil"] = 16; - hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_cgra", "kernel_cgra_s0_w_w_cgra", "(kernel_cgra_s0_z_z_z_cgra*2)" ); + hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "8*kernel_cgra_s0_w_cgra + kernel_cgra_s0_w_w_cgra", "(kernel_cgra_s0_z_z_z_cgra*2)" ); //store is: kernel_cgra.stencil(((kernel_cgra_s0_z_z_z_cgra*2) + 1), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_z_cgra)*2) + -7), (((output_glb_s0_w_w_glb*8) + kernel_cgra_s0_w_w_cgra) + 504), kernel_cgra_s0_x, kernel_cgra_s0_y) auto hcompute_kernel_cgra_stencil_1 = kernel_cgra_s0_z_z_z_cgra->add_op("op_hcompute_kernel_cgra_stencil_1"); hcompute_kernel_cgra_stencil_1->add_function("hcompute_kernel_cgra_stencil_1"); - hcompute_kernel_cgra_stencil_1->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "(((output_glb_s0_w_w_glb*32) + (kernel_cgra_s0_w_cgra*8) + kernel_cgra_s0_w_w_cgra))", "((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_z_cgra)))", "1"); - hcompute_kernel_cgra_stencil_1->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_cgra", "kernel_cgra_s0_w_w_cgra", "((kernel_cgra_s0_z_z_z_cgra*2) + 1)"); + hcompute_kernel_cgra_stencil_1->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "(((output_glb_s0_w_w_glb*32) + (kernel_cgra_s0_w_cgra*8) + kernel_cgra_s0_w_w_cgra))", "((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_z_cgra*2) + 1"); + hcompute_kernel_cgra_stencil_1->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "8*kernel_cgra_s0_w_cgra + kernel_cgra_s0_w_w_cgra", "((kernel_cgra_s0_z_z_z_cgra*2) + 1)"); //consuming kernel_cgra.stencil auto output_cgra_s1_r_y = output_cgra_s1_r_z_rz_glb->add_loop("output_cgra_s1_r_y", 0, 3); @@ -149,16 +147,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "0"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "1"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "2"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "3"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "4"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "5"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "7"); - hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","0", "6"); - hcompute_output_cgra_stencil_8->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w","0"); - hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","output_cgra_s1_w", "0"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "0"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "1"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "2"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "3"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "4"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "5"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "7"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w", "6"); + hcompute_output_cgra_stencil_8->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w"); + hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","8*output_cgra_s1_w"); //store is: output_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(8, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(8, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(9, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(9, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(10, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(10, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(11, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(11, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(12, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(12, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(13, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(13, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(15, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(15, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(14, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(14, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) auto hcompute_output_cgra_stencil_9 = output_cgra_s1_w->add_op("op_hcompute_output_cgra_stencil_9"); @@ -171,16 +169,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "0"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "1"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "2"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "3"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "4"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "5"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "7"); - hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","1", "6"); - hcompute_output_cgra_stencil_9->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w", "1"); - hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s1_y","output_cgra_s1_x", "output_cgra_s1_w", "1"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "0"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "1"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "2"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "3"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "4"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "5"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "7"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+1", "6"); + hcompute_output_cgra_stencil_9->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w+1"); + hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s1_y","output_cgra_s1_x", "8*output_cgra_s1_w+1"); //store is: output_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(8, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(8, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(9, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(9, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(10, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(10, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(11, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(11, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(12, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(12, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(13, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(13, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(15, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(15, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(14, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(14, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) auto hcompute_output_cgra_stencil_10 = output_cgra_s1_w->add_op("op_hcompute_output_cgra_stencil_10"); @@ -193,16 +191,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "0"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "1"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "2"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "3"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "4"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "5"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "7"); - hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","2", "6"); - hcompute_output_cgra_stencil_10->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w", "2"); - hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","output_cgra_s1_w", "2"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "0"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "1"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "2"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "3"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "4"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "5"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "7"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+2", "6"); + hcompute_output_cgra_stencil_10->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w+2"); + hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","8*output_cgra_s1_w+2"); //store is: output_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(8, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(8, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(9, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(9, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(10, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(10, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(11, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(11, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(12, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(12, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(13, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(13, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(15, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(15, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(14, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(14, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) auto hcompute_output_cgra_stencil_11 = output_cgra_s1_w->add_op("op_hcompute_output_cgra_stencil_11"); @@ -215,16 +213,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "0"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "1"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "2"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "3"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "4"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "5"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "7"); - hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","3", "6"); - hcompute_output_cgra_stencil_11->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w", "3"); - hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","output_cgra_s1_w", "3"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "0"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "1"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "2"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "3"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "4"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "5"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "7"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+3", "6"); + hcompute_output_cgra_stencil_11->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w+3"); + hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","8*output_cgra_s1_w+3"); //store is: output_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(8, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(8, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(9, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(9, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(10, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(10, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(11, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(11, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(12, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(12, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(13, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(13, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(15, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(15, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(14, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(14, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) auto hcompute_output_cgra_stencil_12 = output_cgra_s1_w->add_op("op_hcompute_output_cgra_stencil_12"); @@ -237,16 +235,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "0"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "1"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "2"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "3"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "4"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "5"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "7"); - hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","output_cgra_s1_w", "4", "6"); - hcompute_output_cgra_stencil_12->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w","4"); - hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","output_cgra_s1_w", "4"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "0"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "1"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "2"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "3"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "4"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "5"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "7"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x","8*output_cgra_s1_w+4", "6"); + hcompute_output_cgra_stencil_12->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w+4"); + hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","8*output_cgra_s1_w+4"); //store is: output_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(8, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(8, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(9, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(9, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(10, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(10, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(11, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(11, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(12, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(12, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(13, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(13, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(15, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(15, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(14, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(14, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) auto hcompute_output_cgra_stencil_13 = output_cgra_s1_w->add_op("op_hcompute_output_cgra_stencil_13"); @@ -259,16 +257,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "0"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "1"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "2"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "3"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "4"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "5"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "7"); - hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","5", "6"); - hcompute_output_cgra_stencil_13->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w", "5"); - hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","output_cgra_s1_w", "5"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "0"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "1"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "2"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "3"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "4"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "5"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "7"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+5", "6"); + hcompute_output_cgra_stencil_13->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w+5"); + hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","8*output_cgra_s1_w+5"); //store is: output_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(8, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(8, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(9, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(9, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(10, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(10, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(11, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(11, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(12, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(12, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(13, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(13, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(15, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(15, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(14, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(14, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) auto hcompute_output_cgra_stencil_14 = output_cgra_s1_w->add_op("op_hcompute_output_cgra_stencil_14"); @@ -281,16 +279,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "0"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "1"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "2"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "3"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "4"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "5"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "7"); - hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w","6", "6"); - hcompute_output_cgra_stencil_14->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","output_cgra_s1_w", "6"); - hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w" , "6"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "0"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "1"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "2"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "3"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "4"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "5"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "7"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+6", "6"); + hcompute_output_cgra_stencil_14->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","8*output_cgra_s1_w+6"); + hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w+6"); //store is: output_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(8, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(8, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(9, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(9, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(10, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(10, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(11, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(11, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(12, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(12, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(13, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(13, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(15, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(15, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(14, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(14, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) auto hcompute_output_cgra_stencil_15 = output_cgra_s1_w->add_op("op_hcompute_output_cgra_stencil_15"); @@ -303,16 +301,16 @@ prog resnet5_1_unroll_cyclic() { hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "5"); hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "7"); hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "((output_cgra_s1_y*2) + output_cgra_s1_r_y)", "((output_cgra_s1_x*2) + output_cgra_s1_r_x)", "6"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "0"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "1"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "2"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "3"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "4"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "5"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "7"); - hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "output_cgra_s1_w", "7", "6"); - hcompute_output_cgra_stencil_15->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "output_cgra_s1_w", "7"); - hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","output_cgra_s1_w", "7"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "0"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "1"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "2"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "3"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "4"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "5"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "7"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "8*output_cgra_s1_w+7", "6"); + hcompute_output_cgra_stencil_15->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "8*output_cgra_s1_w+7"); + hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x","8*output_cgra_s1_w+7"); //consuming output_cgra.stencil auto output_glb_s0_y_y_cgra = output_glb_s0_w_w_glb->add_loop("output_glb_s0_y_y_cgra", 0, 7); @@ -323,7 +321,7 @@ prog resnet5_1_unroll_cyclic() { //store is: output_glb.stencil(((output_glb_s0_w_w_glb*8) + output_glb_s0_w_w_cgra), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) auto hcompute_output_glb_stencil = output_glb_s0_w_w_cgra->add_op("op_hcompute_output_glb_stencil"); hcompute_output_glb_stencil->add_function("hcompute_output_glb_stencil"); - hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "output_glb_s0_w_cgra", "output_glb_s0_w_w_cgra"); + hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "8*output_glb_s0_w_cgra+output_glb_s0_w_w_cgra"); prg.buffer_port_widths["output_glb_stencil"] = 16; hcompute_output_glb_stencil->add_store("output_glb_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "((output_glb_s0_w_w_glb*32) + (output_glb_s0_w_cgra*8) + output_glb_s0_w_w_cgra)"); diff --git a/example_progs/resnet5_x_unroll.cpp b/example_progs/resnet5_x_unroll.cpp new file mode 100644 index 000000000..d9fd764d6 --- /dev/null +++ b/example_progs/resnet5_x_unroll.cpp @@ -0,0 +1,718 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog resnet5_x_unroll_mic() { + prog prg; + prg.compute_unit_file = "resnet5_x_unroll_mic_compute.h"; + prg.name = "resnet5_x_unroll_mic"; + +// Stencil &input_host_stencil = arg_0; + prg.add_input("input_host_stencil"); + prg.buffer_port_widths["input_host_stencil"] = 16; +// Stencil &kernel_host_stencil = arg_1; + prg.add_input("kernel_host_stencil"); + prg.buffer_port_widths["kernel_host_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing input_glb.stencil + auto input_glb_s0_y = prg.add_loop("input_glb_s0_y", 0, 9); + auto input_glb_s0_x = input_glb_s0_y->add_loop("input_glb_s0_x", 0, 9); + auto input_glb_s0_z_z = input_glb_s0_x->add_loop("input_glb_s0_z_z", 0, 16); + +//store is: input_glb.stencil((input_glb_s0_z_z*4), input_glb_s0_x, input_glb_s0_y) = input_host.stencil((input_glb_s0_z_z*4), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_function("hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z_z*4)"); + prg.buffer_port_widths["input_glb_stencil"] = 16; + hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z_z*4)"); + +//store is: input_glb.stencil(((input_glb_s0_z_z*4) + 1), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*4) + 1), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil_1 = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil_1"); + hcompute_input_glb_stencil_1->add_function("hcompute_input_glb_stencil_1"); + hcompute_input_glb_stencil_1->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*4) + 1)"); + hcompute_input_glb_stencil_1->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*4) + 1)"); + +//store is: input_glb.stencil(((input_glb_s0_z_z*4) + 2), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*4) + 2), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil_2 = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil_2"); + hcompute_input_glb_stencil_2->add_function("hcompute_input_glb_stencil_2"); + hcompute_input_glb_stencil_2->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*4) + 2)"); + hcompute_input_glb_stencil_2->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*4) + 2)"); + +//store is: input_glb.stencil(((input_glb_s0_z_z*4) + 3), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*4) + 3), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil_3 = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil_3"); + hcompute_input_glb_stencil_3->add_function("hcompute_input_glb_stencil_3"); + hcompute_input_glb_stencil_3->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*4) + 3)"); + hcompute_input_glb_stencil_3->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*4) + 3)"); + +//consuming input_glb.stencil +////producing kernel_glb.stencil + auto kernel_glb_s0_y = prg.add_loop("kernel_glb_s0_y", 0, 3); + auto kernel_glb_s0_x = kernel_glb_s0_y->add_loop("kernel_glb_s0_x", 0, 3); + auto kernel_glb_s0_w = kernel_glb_s0_x->add_loop("kernel_glb_s0_w", 0, 128); + auto kernel_glb_s0_z_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z_z", 0, 64); + +//store is: kernel_glb.stencil(kernel_glb_s0_z_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(kernel_glb_s0_z_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) + auto hcompute_kernel_glb_stencil = kernel_glb_s0_z_z->add_op("op_hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_function("hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z_z"); + prg.buffer_port_widths["kernel_glb_stencil"] = 16; + hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z_z"); + +//consuming kernel_glb.stencil +////producing output_glb.stencil + auto output_glb_s0_w_w_glb = prg.add_loop("output_glb_s0_w_w_glb", 0, 2); +////producing output_cgra.stencil + auto output_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("output_cgra_s0_y", 0, 7); + auto output_cgra_s0_x = output_cgra_s0_y->add_loop("output_cgra_s0_x", 0, 7); + auto output_cgra_s0_w_w = output_cgra_s0_x->add_loop("output_cgra_s0_w_w", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil"); + hcompute_output_cgra_stencil->add_function("hcompute_output_cgra_stencil"); + prg.buffer_port_widths["output_cgra_stencil"] = 16; + hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "(output_cgra_s0_w_w*8)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_1 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_function("hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_2 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_function("hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_3 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_function("hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_4 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_function("hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_5 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_function("hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_6 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_function("hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_7 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_function("hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 7)"); + auto output_cgra_s1_r_z_rz_glb = output_glb_s0_w_w_glb->add_loop("output_cgra_s1_r_z_rz_glb", 0, 2); +////producing input_cgra.stencil + auto input_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("input_cgra_s0_y", 0, 9); + auto input_cgra_s0_x = input_cgra_s0_y->add_loop("input_cgra_s0_x", 0, 9); + auto input_cgra_s0_z_z_cgra_z_cgra = input_cgra_s0_x->add_loop("input_cgra_s0_z_z_cgra_z_cgra", 0, 8); + +//store is: input_cgra.stencil((input_cgra_s0_z_z_cgra_z_cgra*4), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_function("hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "(((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4)"); + prg.buffer_port_widths["input_cgra_stencil"] = 16; + hcompute_input_cgra_stencil->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "(input_cgra_s0_z_z_cgra_z_cgra*4)"); + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*4) + 1), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 1), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil_1 = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil_1"); + hcompute_input_cgra_stencil_1->add_function("hcompute_input_cgra_stencil_1"); + hcompute_input_cgra_stencil_1->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 1)"); + hcompute_input_cgra_stencil_1->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((input_cgra_s0_z_z_cgra_z_cgra*4) + 1)"); + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*4) + 2), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 2), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil_2 = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil_2"); + hcompute_input_cgra_stencil_2->add_function("hcompute_input_cgra_stencil_2"); + hcompute_input_cgra_stencil_2->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 2)"); + hcompute_input_cgra_stencil_2->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((input_cgra_s0_z_z_cgra_z_cgra*4) + 2)"); + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*4) + 3), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 3), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil_3 = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil_3"); + hcompute_input_cgra_stencil_3->add_function("hcompute_input_cgra_stencil_3"); + hcompute_input_cgra_stencil_3->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 3)"); + hcompute_input_cgra_stencil_3->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((input_cgra_s0_z_z_cgra_z_cgra*4) + 3)"); + +//consuming input_cgra.stencil +////producing kernel_cgra.stencil + auto kernel_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("kernel_cgra_s0_y", 0, 3); + auto kernel_cgra_s0_x = kernel_cgra_s0_y->add_loop("kernel_cgra_s0_x", 0, 3); + auto kernel_cgra_s0_z_z_cgra_z_cgra = kernel_cgra_s0_x->add_loop("kernel_cgra_s0_z_z_cgra_z_cgra", 0, 32); + auto kernel_cgra_s0_w_w_cgra = kernel_cgra_s0_z_z_cgra_z_cgra->add_loop("kernel_cgra_s0_w_w_cgra", 0, 64); + +//store is: kernel_cgra.stencil(kernel_cgra_s0_z_z_cgra_z_cgra, kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((output_cgra_s1_r_z_rz_glb*32) + kernel_cgra_s0_z_z_cgra_z_cgra), ((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) + auto hcompute_kernel_cgra_stencil = kernel_cgra_s0_w_w_cgra->add_op("op_hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_function("hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra)", "((output_cgra_s1_r_z_rz_glb*32) + kernel_cgra_s0_z_z_cgra_z_cgra)"); + prg.buffer_port_widths["kernel_cgra_stencil"] = 16; + hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_z_z_cgra_z_cgra", "kernel_cgra_s0_w_w_cgra"); + +//consuming kernel_cgra.stencil + auto output_cgra_s1_r_y = output_cgra_s1_r_z_rz_glb->add_loop("output_cgra_s1_r_y", 0, 3); + auto output_cgra_s1_r_x = output_cgra_s1_r_y->add_loop("output_cgra_s1_r_x", 0, 3); + auto output_cgra_s1_y = output_cgra_s1_r_x->add_loop("output_cgra_s1_y", 0, 7); + auto output_cgra_s1_x = output_cgra_s1_y->add_loop("output_cgra_s1_x", 0, 7); + auto output_cgra_s1_r_z_rz_cgra_rz_cgra = output_cgra_s1_x->add_loop("output_cgra_s1_r_z_rz_cgra_rz_cgra", 0, 4); + auto output_cgra_s1_w_w = output_cgra_s1_r_z_rz_cgra_rz_cgra->add_loop("output_cgra_s1_w_w", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_8 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_function("hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w*8)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_9 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_function("hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_10 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_function("hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_11 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_function("hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_12 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_function("hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_13 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_function("hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_14 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_function("hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_15 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_function("hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_r_z_rz_cgra_rz_cgra*8)" , "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1)", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2)", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3)", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4)", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5)", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7)", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6)", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 7)"); + +//consuming output_cgra.stencil + auto output_glb_s0_y_y_cgra = output_glb_s0_w_w_glb->add_loop("output_glb_s0_y_y_cgra", 0, 7); + auto output_glb_s0_x_x_cgra = output_glb_s0_y_y_cgra->add_loop("output_glb_s0_x_x_cgra", 0, 7); + auto output_glb_s0_w_w_cgra = output_glb_s0_x_x_cgra->add_loop("output_glb_s0_w_w_cgra", 0, 64); + +//store is: output_glb.stencil(((output_glb_s0_w_w_glb*64) + output_glb_s0_w_w_cgra), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) + auto hcompute_output_glb_stencil = output_glb_s0_w_w_cgra->add_op("op_hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_function("hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "output_glb_s0_w_w_cgra"); + prg.buffer_port_widths["output_glb_stencil"] = 16; + hcompute_output_glb_stencil->add_store("output_glb_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "((output_glb_s0_w_w_glb*64) + output_glb_s0_w_w_cgra)"); + +//consuming output_glb.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 7); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 7); + auto hw_output_s0_w = hw_output_s0_x_xi->add_loop("hw_output_s0_w", 0, 128); + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_w->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + + return prg; +} + +prog resnet5_x_unroll() { + prog prg; + prg.compute_unit_file = "resnet5_x_unroll_compute.h"; + prg.name = "resnet5_x_unroll"; + +// Stencil &input_host_stencil = arg_0; + prg.add_input("input_host_stencil"); + prg.buffer_port_widths["input_host_stencil"] = 16; +// Stencil &kernel_host_stencil = arg_1; + prg.add_input("kernel_host_stencil"); + prg.buffer_port_widths["kernel_host_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing input_glb.stencil + auto input_glb_s0_y = prg.add_loop("input_glb_s0_y", 0, 9); + auto input_glb_s0_x = input_glb_s0_y->add_loop("input_glb_s0_x", 0, 9); + auto input_glb_s0_z_z = input_glb_s0_x->add_loop("input_glb_s0_z_z", 0, 16); + +//store is: input_glb.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) = input_host.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_function("hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z_z*2)"); + prg.buffer_port_widths["input_glb_stencil"] = 16; + hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "(input_glb_s0_z_z*2)"); + +//store is: input_glb.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil_1 = input_glb_s0_z_z->add_op("op_hcompute_input_glb_stencil_1"); + hcompute_input_glb_stencil_1->add_function("hcompute_input_glb_stencil_1"); + hcompute_input_glb_stencil_1->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*2) + 1)"); + hcompute_input_glb_stencil_1->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "((input_glb_s0_z_z*2) + 1)"); + +//consuming input_glb.stencil +////producing kernel_glb.stencil + auto kernel_glb_s0_y = prg.add_loop("kernel_glb_s0_y", 0, 3); + auto kernel_glb_s0_x = kernel_glb_s0_y->add_loop("kernel_glb_s0_x", 0, 3); + auto kernel_glb_s0_w = kernel_glb_s0_x->add_loop("kernel_glb_s0_w", 0, 128); + auto kernel_glb_s0_z_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z_z", 0, 16); + +//store is: kernel_glb.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) + auto hcompute_kernel_glb_stencil = kernel_glb_s0_z_z->add_op("op_hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_function("hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "(kernel_glb_s0_z_z*2)"); + prg.buffer_port_widths["kernel_glb_stencil"] = 16; + hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "(kernel_glb_s0_z_z*2)"); + +//store is: kernel_glb.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) + auto hcompute_kernel_glb_stencil_1 = kernel_glb_s0_z_z->add_op("op_hcompute_kernel_glb_stencil_1"); + hcompute_kernel_glb_stencil_1->add_function("hcompute_kernel_glb_stencil_1"); + hcompute_kernel_glb_stencil_1->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "((kernel_glb_s0_z_z*2) + 1)"); + hcompute_kernel_glb_stencil_1->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "((kernel_glb_s0_z_z*2) + 1)"); + +//consuming kernel_glb.stencil +////producing output_glb.stencil + auto output_glb_s0_w_w_glb = prg.add_loop("output_glb_s0_w_w_glb", 0, 2); +////producing output_cgra.stencil + auto output_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("output_cgra_s0_y", 0, 7); + auto output_cgra_s0_x = output_cgra_s0_y->add_loop("output_cgra_s0_x", 0, 7); + auto output_cgra_s0_w_w = output_cgra_s0_x->add_loop("output_cgra_s0_w_w", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil"); + hcompute_output_cgra_stencil->add_function("hcompute_output_cgra_stencil"); + prg.buffer_port_widths["output_cgra_stencil"] = 16; + hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "(output_cgra_s0_w_w*8)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_1 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_function("hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_2 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_function("hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_3 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_function("hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_4 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_function("hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_5 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_function("hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_6 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_function("hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_7 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_function("hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 7)"); + auto output_cgra_s1_r_z_rz_glb = output_glb_s0_w_w_glb->add_loop("output_cgra_s1_r_z_rz_glb", 0, 4); +////producing input_cgra.stencil + auto input_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("input_cgra_s0_y", 0, 9); + auto input_cgra_s0_x = input_cgra_s0_y->add_loop("input_cgra_s0_x", 0, 9); + auto input_cgra_s0_z_z_cgra_z_cgra = input_cgra_s0_x->add_loop("input_cgra_s0_z_z_cgra_z_cgra", 0, 4); + +//store is: input_cgra.stencil((input_cgra_s0_z_z_cgra_z_cgra*2), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_function("hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "(((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2)"); + prg.buffer_port_widths["input_cgra_stencil"] = 16; + hcompute_input_cgra_stencil->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "(input_cgra_s0_z_z_cgra_z_cgra*2)"); + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*2) + 1), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2) + 1), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil_1 = input_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_input_cgra_stencil_1"); + hcompute_input_cgra_stencil_1->add_function("hcompute_input_cgra_stencil_1"); + hcompute_input_cgra_stencil_1->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2) + 1)"); + hcompute_input_cgra_stencil_1->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((input_cgra_s0_z_z_cgra_z_cgra*2) + 1)"); + +//consuming input_cgra.stencil +////producing kernel_cgra.stencil + auto kernel_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("kernel_cgra_s0_y", 0, 3); + auto kernel_cgra_s0_x = kernel_cgra_s0_y->add_loop("kernel_cgra_s0_x", 0, 3); + auto kernel_cgra_s0_w_w_cgra = kernel_cgra_s0_x->add_loop("kernel_cgra_s0_w_w_cgra", 0, 64); + auto kernel_cgra_s0_z_z_cgra_z_cgra = kernel_cgra_s0_w_w_cgra->add_loop("kernel_cgra_s0_z_z_cgra_z_cgra", 0, 4); + +//store is: kernel_cgra.stencil((kernel_cgra_s0_z_z_cgra_z_cgra*2), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2), ((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) + auto hcompute_kernel_cgra_stencil = kernel_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_function("hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra)", "(((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2)"); + prg.buffer_port_widths["kernel_cgra_stencil"] = 16; + hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "(kernel_cgra_s0_z_z_cgra_z_cgra*2)"); + +//store is: kernel_cgra.stencil(((kernel_cgra_s0_z_z_cgra_z_cgra*2) + 1), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2) + 1), ((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) + auto hcompute_kernel_cgra_stencil_1 = kernel_cgra_s0_z_z_cgra_z_cgra->add_op("op_hcompute_kernel_cgra_stencil_1"); + hcompute_kernel_cgra_stencil_1->add_function("hcompute_kernel_cgra_stencil_1"); + hcompute_kernel_cgra_stencil_1->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra)", "((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2) + 1)"); + hcompute_kernel_cgra_stencil_1->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "((kernel_cgra_s0_z_z_cgra_z_cgra*2) + 1)"); + +//consuming kernel_cgra.stencil + auto output_cgra_s1_r_y = output_cgra_s1_r_z_rz_glb->add_loop("output_cgra_s1_r_y", 0, 3); + auto output_cgra_s1_r_x = output_cgra_s1_r_y->add_loop("output_cgra_s1_r_x", 0, 3); + auto output_cgra_s1_y = output_cgra_s1_r_x->add_loop("output_cgra_s1_y", 0, 7); + auto output_cgra_s1_x = output_cgra_s1_y->add_loop("output_cgra_s1_x", 0, 7); + auto output_cgra_s1_w_w = output_cgra_s1_x->add_loop("output_cgra_s1_w_w", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_8 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_function("hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "0"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "1"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "2"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "3"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "4"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "5"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "7"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "(output_cgra_s1_w_w*8)", "6"); + hcompute_output_cgra_stencil_8->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w*8)"); + hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w*8)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_9 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_function("hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "1"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "2"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "3"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "4"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "5"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "7"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "6"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 1)", "0"); + hcompute_output_cgra_stencil_9->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 1)"); + hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_10 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_function("hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "0"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "1"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "2"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "3"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "4"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "5"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "7"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 2)", "6"); + hcompute_output_cgra_stencil_10->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 2)"); + hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_11 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_function("hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "0"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "1"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "2"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "3"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "4"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "5"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "7"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 3)", "6"); + hcompute_output_cgra_stencil_11->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 3)"); + hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_12 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_function("hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "0"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "1"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "2"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "3"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "4"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "5"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "7"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 4)", "6"); + hcompute_output_cgra_stencil_12->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 4)"); + hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_13 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_function("hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "0"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "1"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "2"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "3"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "4"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "5"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "7"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 5)", "6"); + hcompute_output_cgra_stencil_13->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 5)"); + hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_14 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_function("hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "0"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "1"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "2"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "3"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "4"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "5"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "7"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 6)", "6"); + hcompute_output_cgra_stencil_14->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 6)"); + hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_15 = output_cgra_s1_w_w->add_op("op_hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_function("hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "0"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "1"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "2"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "3"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "4"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "5"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "7"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "((output_cgra_s1_w_w*8) + 7)", "6"); + hcompute_output_cgra_stencil_15->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 7)"); + hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w*8) + 7)"); + +//consuming output_cgra.stencil + auto output_glb_s0_y_y_cgra = output_glb_s0_w_w_glb->add_loop("output_glb_s0_y_y_cgra", 0, 7); + auto output_glb_s0_x_x_cgra = output_glb_s0_y_y_cgra->add_loop("output_glb_s0_x_x_cgra", 0, 7); + auto output_glb_s0_w_w_cgra = output_glb_s0_x_x_cgra->add_loop("output_glb_s0_w_w_cgra", 0, 64); + +//store is: output_glb.stencil(((output_glb_s0_w_w_glb*64) + output_glb_s0_w_w_cgra), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) + auto hcompute_output_glb_stencil = output_glb_s0_w_w_cgra->add_op("op_hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_function("hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "output_glb_s0_w_w_cgra"); + prg.buffer_port_widths["output_glb_stencil"] = 16; + hcompute_output_glb_stencil->add_store("output_glb_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "((output_glb_s0_w_w_glb*64) + output_glb_s0_w_w_cgra)"); + +//consuming output_glb.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 7); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 7); + auto hw_output_s0_w = hw_output_s0_x_xi->add_loop("hw_output_s0_w", 0, 128); + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_w->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + + return prg; +} + + +// in_img=7 pad=1 ksize=3 stride=1 n_ic=32 n_oc=128 k_ic=8 k_oc=8 m_oc=8 diff --git a/example_progs/resnet_1x1.cpp b/example_progs/resnet_1x1.cpp new file mode 100644 index 000000000..9c3abf361 --- /dev/null +++ b/example_progs/resnet_1x1.cpp @@ -0,0 +1,328 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog resnet_1x1() { + prog prg; + prg.compute_unit_file = "resnet_1x1_compute.h"; + prg.name = "resnet_1x1"; + +// Stencil &input_host_stencil = arg_0; + prg.add_input("input_host_stencil"); + prg.buffer_port_widths["input_host_stencil"] = 16; +// Stencil &kernel_host_stencil = arg_1; + prg.add_input("kernel_host_stencil"); + prg.buffer_port_widths["kernel_host_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing input_glb.stencil + auto input_glb_s0_y = prg.add_loop("input_glb_s0_y", 0, 28); + auto input_glb_s0_x = input_glb_s0_y->add_loop("input_glb_s0_x", 0, 28); + auto input_glb_s0_z = input_glb_s0_x->add_loop("input_glb_s0_z", 0, 16); + +//store is: input_glb.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) = input_host.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil = input_glb_s0_z->add_op("op_hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_function("hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z"); + prg.buffer_port_widths["input_glb_stencil"] = 16; + hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z"); + +//consuming input_glb.stencil +////producing kernel_glb.stencil + auto kernel_glb_s0_w = prg.add_loop("kernel_glb_s0_w", 0, 128); + auto kernel_glb_s0_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z", 0, 16); + +//store is: kernel_glb.stencil(kernel_glb_s0_z, kernel_glb_s0_w, 0, 0) = kernel_host.stencil(kernel_glb_s0_z, kernel_glb_s0_w, 0, 0) + auto hcompute_kernel_glb_stencil = kernel_glb_s0_z->add_op("op_hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_function("hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "0", "0", "kernel_glb_s0_w", "kernel_glb_s0_z"); + prg.buffer_port_widths["kernel_glb_stencil"] = 16; + hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "0", "0", "kernel_glb_s0_w", "kernel_glb_s0_z"); + +//consuming kernel_glb.stencil +////producing output_glb.stencil + auto output_glb_s0_y_y_glb = prg.add_loop("output_glb_s0_y_y_glb", 0, 2); + auto output_glb_s0_x_x_glb = output_glb_s0_y_y_glb->add_loop("output_glb_s0_x_x_glb", 0, 2); + auto output_glb_s0_w_w_glb = output_glb_s0_x_x_glb->add_loop("output_glb_s0_w_w_glb", 0, 2); +////producing output_cgra.stencil + auto output_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("output_cgra_s0_y", 0, 14); + auto output_cgra_s0_x = output_cgra_s0_y->add_loop("output_cgra_s0_x", 0, 14); + auto output_cgra_s0_w_w = output_cgra_s0_x->add_loop("output_cgra_s0_w_w", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil"); + hcompute_output_cgra_stencil->add_function("hcompute_output_cgra_stencil"); + prg.buffer_port_widths["output_cgra_stencil"] = 16; + hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "(output_cgra_s0_w_w*8)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_1 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_function("hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_2 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_function("hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_3 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_function("hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_4 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_function("hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_5 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_function("hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_6 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_function("hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_7 = output_cgra_s0_w_w->add_op("op_hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_function("hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "((output_cgra_s0_w_w*8) + 7)"); + auto output_cgra_s1_r_z_rz_glb = output_glb_s0_w_w_glb->add_loop("output_cgra_s1_r_z_rz_glb", 0, 2); +////producing input_cgra.stencil + auto input_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("input_cgra_s0_y", 0, 14); + auto input_cgra_s0_x = input_cgra_s0_y->add_loop("input_cgra_s0_x", 0, 14); + auto input_cgra_s0_z_z_cgra = input_cgra_s0_x->add_loop("input_cgra_s0_z_z_cgra", 0, 8); + +//store is: input_cgra.stencil(input_cgra_s0_z_z_cgra, input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra), ((output_glb_s0_x_x_glb*14) + input_cgra_s0_x), ((output_glb_s0_y_y_glb*14) + input_cgra_s0_y)) + auto hcompute_input_cgra_stencil = input_cgra_s0_z_z_cgra->add_op("op_hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_function("hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_load("input_glb_stencil", "((output_glb_s0_y_y_glb*14) + input_cgra_s0_y)", "((output_glb_s0_x_x_glb*14) + input_cgra_s0_x)", "((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra)"); + prg.buffer_port_widths["input_cgra_stencil"] = 16; + hcompute_input_cgra_stencil->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "input_cgra_s0_z_z_cgra"); + +//consuming input_cgra.stencil +////producing kernel_cgra.stencil + auto kernel_cgra_s0_w_w_cgra = output_cgra_s1_r_z_rz_glb->add_loop("kernel_cgra_s0_w_w_cgra", 0, 64); + auto kernel_cgra_s0_z_z_cgra = kernel_cgra_s0_w_w_cgra->add_loop("kernel_cgra_s0_z_z_cgra", 0, 8); + +//store is: kernel_cgra.stencil(kernel_cgra_s0_z_z_cgra, kernel_cgra_s0_w_w_cgra, 0, 0) = kernel_glb.stencil(((output_cgra_s1_r_z_rz_glb*8) + kernel_cgra_s0_z_z_cgra), kernel_cgra_s0_w_w_cgra, 0, 0) + auto hcompute_kernel_cgra_stencil = kernel_cgra_s0_z_z_cgra->add_op("op_hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_function("hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "0", "0", "kernel_cgra_s0_w_w_cgra + (output_glb_s0_w_w_glb*64)", "((output_cgra_s1_r_z_rz_glb*8) + kernel_cgra_s0_z_z_cgra)"); + prg.buffer_port_widths["kernel_cgra_stencil"] = 16; + hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "0", "0", "kernel_cgra_s0_w_w_cgra", "kernel_cgra_s0_z_z_cgra"); + +//consuming kernel_cgra.stencil + auto output_cgra_s1_y = output_cgra_s1_r_z_rz_glb->add_loop("output_cgra_s1_y", 0, 14); + auto output_cgra_s1_x = output_cgra_s1_y->add_loop("output_cgra_s1_x", 0, 14); + auto output_cgra_s1_w_w_cgra = output_cgra_s1_x->add_loop("output_cgra_s1_w_w_cgra", 0, 8); + +//store is: output_cgra.stencil((output_cgra_s1_w_w_cgra*8), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil((output_cgra_s1_w_w_cgra*8), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_8 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_function("hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "0"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "1"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "2"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "3"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "4"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "5"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "7"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "0", "0", "(output_cgra_s1_w_w_cgra*8)", "6"); + hcompute_output_cgra_stencil_8->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w_cgra*8)"); + hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "(output_cgra_s1_w_w_cgra*8)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 1), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 1), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_9 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_function("hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "1"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "2"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "3"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "4"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "5"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "7"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "6"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 1)", "0"); + hcompute_output_cgra_stencil_9->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 1)"); + hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 1)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 2), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 2), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_10 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_function("hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "0"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "1"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "2"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "3"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "4"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "5"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "7"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 2)", "6"); + hcompute_output_cgra_stencil_10->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 2)"); + hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 2)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 3), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 3), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_11 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_function("hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "0"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "1"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "2"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "3"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "4"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "5"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "7"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 3)", "6"); + hcompute_output_cgra_stencil_11->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 3)"); + hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 3)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 4), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 4), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_12 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_function("hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "0"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "1"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "2"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "3"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "4"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "5"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "7"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 4)", "6"); + hcompute_output_cgra_stencil_12->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 4)"); + hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 4)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 5), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 5), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_13 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_function("hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "0"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "1"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "2"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "3"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "4"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "5"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "7"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 5)", "6"); + hcompute_output_cgra_stencil_13->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 5)"); + hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 5)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 6), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 6), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_14 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_function("hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "0"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "1"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "2"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "3"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "4"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "5"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "7"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 6)", "6"); + hcompute_output_cgra_stencil_14->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 6)"); + hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 6)"); + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 7), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y)) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 7), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y)) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y)) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y)))))))))) + auto hcompute_output_cgra_stencil_15 = output_cgra_s1_w_w_cgra->add_op("op_hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_function("hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "0"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "1"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "2"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "3"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "4"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "5"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "7"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "0", "0", "((output_cgra_s1_w_w_cgra*8) + 7)", "6"); + hcompute_output_cgra_stencil_15->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 7)"); + hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "((output_cgra_s1_w_w_cgra*8) + 7)"); + +//consuming output_cgra.stencil + auto output_glb_s0_y_y_cgra = output_glb_s0_w_w_glb->add_loop("output_glb_s0_y_y_cgra", 0, 14); + auto output_glb_s0_x_x_cgra = output_glb_s0_y_y_cgra->add_loop("output_glb_s0_x_x_cgra", 0, 14); + auto output_glb_s0_w_w_cgra_w_cgra = output_glb_s0_x_x_cgra->add_loop("output_glb_s0_w_w_cgra_w_cgra", 0, 8); + auto output_glb_s0_w_w_cgra_w_unroll = output_glb_s0_w_w_cgra_w_cgra->add_loop("output_glb_s0_w_w_cgra_w_unroll", 0, 8); + +//store is: output_glb.stencil(((output_glb_s0_w_w_cgra_w_cgra*8) + output_glb_s0_w_w_cgra_w_unroll), ((output_glb_s0_x_x_glb*14) + output_glb_s0_x_x_cgra), ((output_glb_s0_y_y_glb*14) + output_glb_s0_y_y_cgra)) = output_cgra.stencil(((output_glb_s0_w_w_cgra_w_cgra*8) + output_glb_s0_w_w_cgra_w_unroll), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) + auto hcompute_output_glb_stencil = output_glb_s0_w_w_cgra_w_unroll->add_op("op_hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_function("hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "((output_glb_s0_w_w_cgra_w_cgra*8) + output_glb_s0_w_w_cgra_w_unroll)"); + prg.buffer_port_widths["output_glb_stencil"] = 16; + hcompute_output_glb_stencil->add_store("output_glb_stencil", "((output_glb_s0_y_y_glb*14) + output_glb_s0_y_y_cgra)", "((output_glb_s0_x_x_glb*14) + output_glb_s0_x_x_cgra)", "((output_glb_s0_w_w_cgra_w_cgra*8) + output_glb_s0_w_w_cgra_w_unroll)"); + +//consuming output_glb.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 28); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 28); + auto hw_output_s0_w = hw_output_s0_x_xi->add_loop("hw_output_s0_w", 0, 128); + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_w->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + + return prg; +} + + diff --git a/example_progs/resnet_debug.cpp b/example_progs/resnet_debug.cpp new file mode 100644 index 000000000..52ebd90aa --- /dev/null +++ b/example_progs/resnet_debug.cpp @@ -0,0 +1,329 @@ +#include "app.h" +#include "ubuffer.h" +#include "codegen.h" +#include "prog.h" + +prog resnet_last() { + prog prg; + prg.compute_unit_file = "resnet_init_unroll_tile_compute.h"; + prg.name = "resnet_last"; + +// Stencil &input_host_stencil = arg_0; + prg.add_input("input_host_stencil"); + prg.buffer_port_widths["input_host_stencil"] = 16; +// Stencil &kernel_host_stencil = arg_1; + prg.add_input("kernel_host_stencil"); + prg.buffer_port_widths["kernel_host_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing input_glb.stencil + auto input_glb_s0_y = prg.add_loop("input_glb_s0_y", 0, 9); + auto input_glb_s0_x = input_glb_s0_y->add_loop("input_glb_s0_x", 0, 9); + auto input_glb_s0_z = input_glb_s0_x->add_loop("input_glb_s0_z", 0, 16); + +//store is: input_glb.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) = input_host.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) + auto hcompute_input_glb_stencil = input_glb_s0_z->add_op("op_hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_function("hcompute_input_glb_stencil"); + hcompute_input_glb_stencil->add_load("input_host_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z"); + prg.buffer_port_widths["input_glb_stencil"] = 16; + hcompute_input_glb_stencil->add_store("input_glb_stencil", "input_glb_s0_y", "input_glb_s0_x", "input_glb_s0_z"); + +//consuming input_glb.stencil +////producing kernel_glb.stencil + auto kernel_glb_s0_y = prg.add_loop("kernel_glb_s0_y", 0, 3); + auto kernel_glb_s0_x = kernel_glb_s0_y->add_loop("kernel_glb_s0_x", 0, 3); + auto kernel_glb_s0_w = kernel_glb_s0_x->add_loop("kernel_glb_s0_w", 0, 16); + auto kernel_glb_s0_z = kernel_glb_s0_w->add_loop("kernel_glb_s0_z", 0, 16); + +//store is: kernel_glb.stencil(kernel_glb_s0_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(kernel_glb_s0_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) + auto hcompute_kernel_glb_stencil = kernel_glb_s0_z->add_op("op_hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_function("hcompute_kernel_glb_stencil"); + hcompute_kernel_glb_stencil->add_load("kernel_host_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z"); + prg.buffer_port_widths["kernel_glb_stencil"] = 16; + hcompute_kernel_glb_stencil->add_store("kernel_glb_stencil", "kernel_glb_s0_y", "kernel_glb_s0_x", "kernel_glb_s0_w", "kernel_glb_s0_z"); + +//consuming kernel_glb.stencil +////producing output_glb.stencil + auto output_glb_s0_w_w_glb = prg.add_loop("output_glb_s0_w_w_glb", 0, 2); +////producing output_cgra.stencil + auto output_cgra_s0_y = output_glb_s0_w_w_glb->add_loop("output_cgra_s0_y", 0, 7); + auto output_cgra_s0_x = output_cgra_s0_y->add_loop("output_cgra_s0_x", 0, 7); + +//store is: output_cgra.stencil(0, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil"); + hcompute_output_cgra_stencil->add_function("hcompute_output_cgra_stencil"); + prg.buffer_port_widths["output_cgra_stencil"] = 16; + hcompute_output_cgra_stencil->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "0"); + +//store is: output_cgra.stencil(1, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_1 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_function("hcompute_output_cgra_stencil_1"); + hcompute_output_cgra_stencil_1->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "1"); + +//store is: output_cgra.stencil(2, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_2 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_function("hcompute_output_cgra_stencil_2"); + hcompute_output_cgra_stencil_2->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "2"); + +//store is: output_cgra.stencil(3, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_3 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_function("hcompute_output_cgra_stencil_3"); + hcompute_output_cgra_stencil_3->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "3"); + +//store is: output_cgra.stencil(4, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_4 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_function("hcompute_output_cgra_stencil_4"); + hcompute_output_cgra_stencil_4->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "4"); + +//store is: output_cgra.stencil(5, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_5 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_function("hcompute_output_cgra_stencil_5"); + hcompute_output_cgra_stencil_5->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "5"); + +//store is: output_cgra.stencil(6, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_6 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_function("hcompute_output_cgra_stencil_6"); + hcompute_output_cgra_stencil_6->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "6"); + +//store is: output_cgra.stencil(7, output_cgra_s0_x, output_cgra_s0_y) = (int16)0 + auto hcompute_output_cgra_stencil_7 = output_cgra_s0_x->add_op("op_hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_function("hcompute_output_cgra_stencil_7"); + hcompute_output_cgra_stencil_7->add_store("output_cgra_stencil", "output_cgra_s0_y", "output_cgra_s0_x", "7"); + auto output_cgra_s1_r_z_rz_glb = output_glb_s0_w_w_glb->add_loop("output_cgra_s1_r_z_rz_glb", 0, 2); +////producing input_cgra.stencil + auto input_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("input_cgra_s0_y", 0, 9); + auto input_cgra_s0_x = input_cgra_s0_y->add_loop("input_cgra_s0_x", 0, 9); + auto input_cgra_s0_z_z_cgra = input_cgra_s0_x->add_loop("input_cgra_s0_z_z_cgra", 0, 8); + +//store is: input_cgra.stencil(input_cgra_s0_z_z_cgra, input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra), input_cgra_s0_x, input_cgra_s0_y) + auto hcompute_input_cgra_stencil = input_cgra_s0_z_z_cgra->add_op("op_hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_function("hcompute_input_cgra_stencil"); + hcompute_input_cgra_stencil->add_load("input_glb_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra)"); + prg.buffer_port_widths["input_cgra_stencil"] = 16; + hcompute_input_cgra_stencil->add_store("input_cgra_stencil", "input_cgra_s0_y", "input_cgra_s0_x", "input_cgra_s0_z_z_cgra"); + +//consuming input_cgra.stencil +////producing kernel_cgra.stencil + auto kernel_cgra_s0_y = output_cgra_s1_r_z_rz_glb->add_loop("kernel_cgra_s0_y", 0, 3); + auto kernel_cgra_s0_x = kernel_cgra_s0_y->add_loop("kernel_cgra_s0_x", 0, 3); + auto kernel_cgra_s0_w_w_cgra = kernel_cgra_s0_x->add_loop("kernel_cgra_s0_w_w_cgra", 0, 8); + auto kernel_cgra_s0_z_z_cgra = kernel_cgra_s0_w_w_cgra->add_loop("kernel_cgra_s0_z_z_cgra", 0, 8); + +//store is: kernel_cgra.stencil(kernel_cgra_s0_z_z_cgra, kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((output_cgra_s1_r_z_rz_glb*8) + kernel_cgra_s0_z_z_cgra), ((output_glb_s0_w_w_glb*8) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) + auto hcompute_kernel_cgra_stencil = kernel_cgra_s0_z_z_cgra->add_op("op_hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_function("hcompute_kernel_cgra_stencil"); + hcompute_kernel_cgra_stencil->add_load("kernel_glb_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "((output_glb_s0_w_w_glb*8) + kernel_cgra_s0_w_w_cgra)", "((output_cgra_s1_r_z_rz_glb*8) + kernel_cgra_s0_z_z_cgra)"); + prg.buffer_port_widths["kernel_cgra_stencil"] = 16; + hcompute_kernel_cgra_stencil->add_store("kernel_cgra_stencil", "kernel_cgra_s0_y", "kernel_cgra_s0_x", "kernel_cgra_s0_w_w_cgra", "kernel_cgra_s0_z_z_cgra"); + +//consuming kernel_cgra.stencil + auto output_cgra_s1_r_y = output_cgra_s1_r_z_rz_glb->add_loop("output_cgra_s1_r_y", 0, 3); + auto output_cgra_s1_r_x = output_cgra_s1_r_y->add_loop("output_cgra_s1_r_x", 0, 3); + auto output_cgra_s1_y = output_cgra_s1_r_x->add_loop("output_cgra_s1_y", 0, 7); + auto output_cgra_s1_x = output_cgra_s1_y->add_loop("output_cgra_s1_x", 0, 7); + +//store is: output_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(0, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 0, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_8 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_function("hcompute_output_cgra_stencil_8"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_8->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "0"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "1"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "2"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "3"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "4"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "5"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "7"); + hcompute_output_cgra_stencil_8->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "0", "6"); + hcompute_output_cgra_stencil_8->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + hcompute_output_cgra_stencil_8->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "0"); + +//store is: output_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(1, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 1, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_9 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_function("hcompute_output_cgra_stencil_9"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_9->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "1"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "2"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "3"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "4"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "5"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "7"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "6"); + hcompute_output_cgra_stencil_9->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "1", "0"); + hcompute_output_cgra_stencil_9->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + hcompute_output_cgra_stencil_9->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "1"); + +//store is: output_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(2, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 2, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_10 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_function("hcompute_output_cgra_stencil_10"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_10->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "0"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "1"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "2"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "3"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "4"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "5"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "7"); + hcompute_output_cgra_stencil_10->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "2", "6"); + hcompute_output_cgra_stencil_10->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + hcompute_output_cgra_stencil_10->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "2"); + +//store is: output_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(3, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 3, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_11 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_function("hcompute_output_cgra_stencil_11"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_11->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "0"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "1"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "2"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "3"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "4"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "5"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "7"); + hcompute_output_cgra_stencil_11->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "3", "6"); + hcompute_output_cgra_stencil_11->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + hcompute_output_cgra_stencil_11->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "3"); + +//store is: output_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(4, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 4, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_12 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_function("hcompute_output_cgra_stencil_12"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_12->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "0"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "1"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "2"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "3"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "4"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "5"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "7"); + hcompute_output_cgra_stencil_12->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "4", "6"); + hcompute_output_cgra_stencil_12->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + hcompute_output_cgra_stencil_12->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "4"); + +//store is: output_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(5, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 5, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_13 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_function("hcompute_output_cgra_stencil_13"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_13->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "0"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "1"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "2"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "3"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "4"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "5"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "7"); + hcompute_output_cgra_stencil_13->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "5", "6"); + hcompute_output_cgra_stencil_13->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + hcompute_output_cgra_stencil_13->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "5"); + +//store is: output_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(6, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 6, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_14 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_function("hcompute_output_cgra_stencil_14"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_14->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "0"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "1"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "2"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "3"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "4"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "5"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "7"); + hcompute_output_cgra_stencil_14->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "6", "6"); + hcompute_output_cgra_stencil_14->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + hcompute_output_cgra_stencil_14->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "6"); + +//store is: output_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(7, output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, 7, output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) + auto hcompute_output_cgra_stencil_15 = output_cgra_s1_x->add_op("op_hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_function("hcompute_output_cgra_stencil_15"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "0"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "1"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "2"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "3"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "4"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "5"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "7"); + hcompute_output_cgra_stencil_15->add_load("input_cgra_stencil", "(output_cgra_s1_r_y + output_cgra_s1_y)", "(output_cgra_s1_r_x + output_cgra_s1_x)", "6"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "0"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "1"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "2"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "3"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "4"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "5"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "7"); + hcompute_output_cgra_stencil_15->add_load("kernel_cgra_stencil", "output_cgra_s1_r_y", "output_cgra_s1_r_x", "7", "6"); + hcompute_output_cgra_stencil_15->add_load("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + hcompute_output_cgra_stencil_15->add_store("output_cgra_stencil", "output_cgra_s1_y", "output_cgra_s1_x", "7"); + +//consuming output_cgra.stencil + auto output_glb_s0_y_y_cgra = output_glb_s0_w_w_glb->add_loop("output_glb_s0_y_y_cgra", 0, 7); + auto output_glb_s0_x_x_cgra = output_glb_s0_y_y_cgra->add_loop("output_glb_s0_x_x_cgra", 0, 7); + auto output_glb_s0_w_w_cgra = output_glb_s0_x_x_cgra->add_loop("output_glb_s0_w_w_cgra", 0, 8); + +//store is: output_glb.stencil(((output_glb_s0_w_w_glb*8) + output_glb_s0_w_w_cgra), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) + auto hcompute_output_glb_stencil = output_glb_s0_w_w_cgra->add_op("op_hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_function("hcompute_output_glb_stencil"); + hcompute_output_glb_stencil->add_load("output_cgra_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "output_glb_s0_w_w_cgra"); + prg.buffer_port_widths["output_glb_stencil"] = 16; + hcompute_output_glb_stencil->add_store("output_glb_stencil", "output_glb_s0_y_y_cgra", "output_glb_s0_x_x_cgra", "((output_glb_s0_w_w_glb*8) + output_glb_s0_w_w_cgra)"); + +//consuming output_glb.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 7); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 7); + auto hw_output_s0_w = hw_output_s0_x_xi->add_loop("hw_output_s0_w", 0, 16); + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) + auto hcompute_hw_output_stencil = hw_output_s0_w->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi", "hw_output_s0_w"); + + return prg; +} + + diff --git a/example_progs/resnet_single_channel.cpp b/example_progs/resnet_single_channel.cpp index 139467191..061e1d87a 100644 --- a/example_progs/resnet_single_channel.cpp +++ b/example_progs/resnet_single_channel.cpp @@ -1,5 +1,79 @@ #include "example_progs.h" +prog resnet_size_test() { + prog prg; + prg.compute_unit_file = "resnet_simple_compute.h"; + prg.name = "resnet_size_test"; + +// Stencil &hw_input_stencil = arg_0; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_kernel_stencil = arg_1; + prg.add_input("hw_kernel_stencil"); + prg.buffer_port_widths["hw_kernel_stencil"] = 16; +// Stencil &hw_output_stencil = arg_2; + prg.add_output("hw_output_stencil"); + prg.buffer_port_widths["hw_output_stencil"] = 16; + +////producing hw_input_global_wrapper.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 9); + auto hw_input_global_wrapper_s0_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x", 0, 9); + +//store is: hw_input_global_wrapper.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_stencil = hw_input_global_wrapper_s0_x->add_op("op_hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_stencil->add_load("hw_input_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_stencil->add_store("hw_input_global_wrapper_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x", "0"); + +//consuming hw_input_global_wrapper.stencil +////producing hw_kernel_global_wrapper.stencil + auto hw_kernel_global_wrapper_s0_y = prg.add_loop("hw_kernel_global_wrapper_s0_y", 0, 3); + auto hw_kernel_global_wrapper_s0_x = hw_kernel_global_wrapper_s0_y->add_loop("hw_kernel_global_wrapper_s0_x", 0, 3); + +//store is: hw_kernel_global_wrapper.stencil(0, 0, hw_kernel_global_wrapper_s0_x, hw_kernel_global_wrapper_s0_y) = hw_kernel.stencil(0, 0, hw_kernel_global_wrapper_s0_x, hw_kernel_global_wrapper_s0_y) + auto hcompute_hw_kernel_global_wrapper_stencil = hw_kernel_global_wrapper_s0_x->add_op("op_hcompute_hw_kernel_global_wrapper_stencil"); + hcompute_hw_kernel_global_wrapper_stencil->add_function("hcompute_hw_kernel_global_wrapper_stencil"); + hcompute_hw_kernel_global_wrapper_stencil->add_load("hw_kernel_stencil", "hw_kernel_global_wrapper_s0_y", "hw_kernel_global_wrapper_s0_x", "0", "0"); + prg.buffer_port_widths["hw_kernel_global_wrapper_stencil"] = 16; + hcompute_hw_kernel_global_wrapper_stencil->add_store("hw_kernel_global_wrapper_stencil", "hw_kernel_global_wrapper_s0_y", "hw_kernel_global_wrapper_s0_x", "0", "0"); + +//consuming hw_kernel_global_wrapper.stencil +////producing conv.stencil + auto conv_s0_y = prg.add_loop("conv_s0_y", 0, 7); + auto conv_s0_x = conv_s0_y->add_loop("conv_s0_x", 0, 7); + +//store is: conv.stencil(conv_s0_x, conv_s0_y, 0) = (int16)0 + auto hcompute_conv_stencil = conv_s0_x->add_op("op_hcompute_conv_stencil"); + hcompute_conv_stencil->add_function("hcompute_conv_stencil"); + prg.buffer_port_widths["conv_stencil"] = 16; + hcompute_conv_stencil->add_store("conv_stencil", "0", "conv_s0_y", "conv_s0_x"); + auto conv_s1_r_y = prg.add_loop("conv_s1_r_y", 0, 3); + auto conv_s1_r_x = conv_s1_r_y->add_loop("conv_s1_r_x", 0, 3); + auto conv_s1_y = conv_s1_r_x->add_loop("conv_s1_y", 0, 7); + auto conv_s1_x = conv_s1_y->add_loop("conv_s1_x", 0, 7); + +//store is: conv.stencil(conv_s1_x, conv_s1_y, 0) = (conv.stencil(conv_s1_x, conv_s1_y, 0) + (hw_kernel_global_wrapper.stencil(0, 0, conv_s1_r_x, conv_s1_r_y)*hw_input_global_wrapper.stencil(0, (conv_s1_r_x + conv_s1_x), (conv_s1_r_y + conv_s1_y)))) + auto hcompute_conv_stencil_1 = conv_s1_x->add_op("op_hcompute_conv_stencil_1"); + hcompute_conv_stencil_1->add_function("hcompute_conv_stencil_1"); + hcompute_conv_stencil_1->add_load("conv_stencil", "0", "conv_s1_y", "conv_s1_x"); + hcompute_conv_stencil_1->add_load("hw_input_global_wrapper_stencil", "(conv_s1_r_y + conv_s1_y)", "(conv_s1_r_x + conv_s1_x)", "0"); + hcompute_conv_stencil_1->add_load("hw_kernel_global_wrapper_stencil", "conv_s1_r_y", "conv_s1_r_x", "0", "0"); + hcompute_conv_stencil_1->add_store("conv_stencil", "0", "conv_s1_y", "conv_s1_x"); + +//consuming conv.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 7); + auto hw_output_s0_x_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi", 0, 7); + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0) = conv.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0) + auto hcompute_hw_output_stencil = hw_output_s0_x_xi->add_op("op_hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_function("hcompute_hw_output_stencil"); + hcompute_hw_output_stencil->add_load("conv_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + hcompute_hw_output_stencil->add_store("hw_output_stencil", "0", "hw_output_s0_y_yi", "hw_output_s0_x_xi"); + + return prg; +} + prog resnet_tiny() { prog prg; prg.compute_unit_file = "resnet_simple_compute.h"; diff --git a/example_progs/unsharp.cpp b/example_progs/unsharp.cpp index db95d8ae8..9b9a0edc8 100644 --- a/example_progs/unsharp.cpp +++ b/example_progs/unsharp.cpp @@ -1,5 +1,239 @@ #include "example_progs.h" +prog unsharp_large() { + prog prg; + prg.compute_unit_file = "unsharp_large_compute.h"; + prg.name = "unsharp_large"; + +// Stencil &hw_input_stencil = arg_1; + prg.add_input("hw_input_stencil"); + prg.buffer_port_widths["hw_input_stencil"] = 16; +// Stencil &hw_output_global_wrapper_stencil = arg_3; + prg.add_output("hw_output_global_wrapper_stencil"); + prg.buffer_port_widths["hw_output_global_wrapper_stencil"] = 16; + +////producing hw_input_global_wrapper.glb.stencil + auto hw_input_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_s0_y", 0, 256); + auto hw_input_global_wrapper_s0_x_x = hw_input_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper.glb.stencil(0, hw_input_global_wrapper_s0_x_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(0, (hw_input_global_wrapper_s0_x_x + -3), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_function("hcompute_hw_input_global_wrapper_glb_stencil"); + hcompute_hw_input_global_wrapper_glb_stencil->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "(hw_input_global_wrapper_s0_x_x + -3)", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_glb_stencil"] = 16; + hcompute_hw_input_global_wrapper_glb_stencil->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x_x", "0"); + +//store is: hw_input_global_wrapper.glb.stencil(1, hw_input_global_wrapper_s0_x_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(1, (hw_input_global_wrapper_s0_x_x + -3), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_1 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_function("hcompute_hw_input_global_wrapper_glb_stencil_1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "(hw_input_global_wrapper_s0_x_x + -3)", "1"); + hcompute_hw_input_global_wrapper_glb_stencil_1->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x_x", "1"); + +//store is: hw_input_global_wrapper.glb.stencil(2, hw_input_global_wrapper_s0_x_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(2, (hw_input_global_wrapper_s0_x_x + -3), (hw_input_global_wrapper_s0_y + -3)) + auto hcompute_hw_input_global_wrapper_glb_stencil_2 = hw_input_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_function("hcompute_hw_input_global_wrapper_glb_stencil_2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_load("hw_input_stencil", "(hw_input_global_wrapper_s0_y + -3)", "(hw_input_global_wrapper_s0_x_x + -3)", "2"); + hcompute_hw_input_global_wrapper_glb_stencil_2->add_store("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_s0_y", "hw_input_global_wrapper_s0_x_x", "2"); + +//consuming hw_input_global_wrapper.glb.stencil +////producing hw_output.glb.stencil +////producing hw_input_global_wrapper_global_wrapper.stencil + auto hw_input_global_wrapper_global_wrapper_s0_y = prg.add_loop("hw_input_global_wrapper_global_wrapper_s0_y", 0, 256); + auto hw_input_global_wrapper_global_wrapper_s0_x_x = hw_input_global_wrapper_global_wrapper_s0_y->add_loop("hw_input_global_wrapper_global_wrapper_s0_x_x", 0, 132); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(0, hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x", "0"); + prg.buffer_port_widths["hw_input_global_wrapper_global_wrapper_stencil"] = 16; + hcompute_hw_input_global_wrapper_global_wrapper_stencil->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x", "0"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(1, hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_1 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x", "1"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_1->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x", "1"); + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) = hw_input_global_wrapper.glb.stencil(2, hw_input_global_wrapper_global_wrapper_s0_x_x, hw_input_global_wrapper_global_wrapper_s0_y) + auto hcompute_hw_input_global_wrapper_global_wrapper_stencil_2 = hw_input_global_wrapper_global_wrapper_s0_x_x->add_op("op_hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_function("hcompute_hw_input_global_wrapper_global_wrapper_stencil_2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_load("hw_input_global_wrapper_glb_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x", "2"); + hcompute_hw_input_global_wrapper_global_wrapper_stencil_2->add_store("hw_input_global_wrapper_global_wrapper_stencil", "hw_input_global_wrapper_global_wrapper_s0_y", "hw_input_global_wrapper_global_wrapper_s0_x_x", "2"); + +//consuming hw_input_global_wrapper_global_wrapper.stencil +////producing gray.stencil + auto gray_s0_y = prg.add_loop("gray_s0_y", 0, 256); + auto gray_s0_x_x = gray_s0_y->add_loop("gray_s0_x_x", 0, 132); + +//store is: gray.stencil(gray_s0_x_x, gray_s0_y) = (((hw_input_global_wrapper_global_wrapper.stencil(1, gray_s0_x_x, gray_s0_y)*(uint16)150) + ((hw_input_global_wrapper_global_wrapper.stencil(2, gray_s0_x_x, gray_s0_y)*(uint16)29) + (hw_input_global_wrapper_global_wrapper.stencil(0, gray_s0_x_x, gray_s0_y)*(uint16)77)))/(uint16)256) + auto hcompute_gray_stencil = gray_s0_x_x->add_op("op_hcompute_gray_stencil"); + hcompute_gray_stencil->add_function("hcompute_gray_stencil"); + hcompute_gray_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "gray_s0_x_x", "1"); + hcompute_gray_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "gray_s0_x_x", "2"); + hcompute_gray_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "gray_s0_y", "gray_s0_x_x", "0"); + prg.buffer_port_widths["gray_stencil"] = 16; + hcompute_gray_stencil->add_store("gray_stencil", "gray_s0_y", "gray_s0_x_x"); + +//consuming gray.stencil +////producing rom_div_lookupa0 + +//consuming rom_div_lookupa0 +////producing reciprocal.stencil + auto reciprocal_s0_y = prg.add_loop("reciprocal_s0_y", 0, 250); + auto reciprocal_s0_x_x = reciprocal_s0_y->add_loop("reciprocal_s0_x_x", 0, 126); + +//store is: reciprocal.stencil(reciprocal_s0_x_x, reciprocal_s0_y) = rom_div_lookupa0[(int32(max(gray.stencil((reciprocal_s0_x_x + 3), (reciprocal_s0_y + 3)), (uint16)1)) + -1)] + auto hcompute_reciprocal_stencil = reciprocal_s0_x_x->add_op("op_hcompute_reciprocal_stencil"); + hcompute_reciprocal_stencil->add_function("hcompute_reciprocal_stencil"); + hcompute_reciprocal_stencil->add_load("gray_stencil", "(reciprocal_s0_y + 3)", "(reciprocal_s0_x_x + 3)"); + prg.buffer_port_widths["reciprocal_stencil"] = 16; + hcompute_reciprocal_stencil->add_store("reciprocal_stencil", "reciprocal_s0_y", "reciprocal_s0_x_x"); + //hcompute_reciprocal_stencil->index_variable_prefetch_cycle(1); + hcompute_reciprocal_stencil->add_latency(1); + +//consuming reciprocal.stencil +////producing blur_unnormalized.stencil + auto blur_unnormalized_s0_y = prg.add_loop("blur_unnormalized_s0_y", 0, 250); + auto blur_unnormalized_s0_x_x = blur_unnormalized_s0_y->add_loop("blur_unnormalized_s0_x_x", 0, 126); + +//store is: blur_unnormalized.stencil(blur_unnormalized_s0_x_x, blur_unnormalized_s0_y) = (uint16)0 + auto hcompute_blur_unnormalized_stencil = blur_unnormalized_s0_x_x->add_op("op_hcompute_blur_unnormalized_stencil"); + hcompute_blur_unnormalized_stencil->add_function("hcompute_blur_unnormalized_stencil"); + prg.buffer_port_widths["blur_unnormalized_stencil"] = 16; + hcompute_blur_unnormalized_stencil->add_store("blur_unnormalized_stencil", "blur_unnormalized_s0_y", "blur_unnormalized_s0_x_x"); + auto blur_unnormalized_s1_y = prg.add_loop("blur_unnormalized_s1_y", 0, 250); + auto blur_unnormalized_s1_x_x = blur_unnormalized_s1_y->add_loop("blur_unnormalized_s1_x_x", 0, 126); + +//store is: blur_unnormalized.stencil(blur_unnormalized_s1_x_x, blur_unnormalized_s1_y) = (gray.stencil((blur_unnormalized_s1_x_x + 1), blur_unnormalized_s1_y) + (blur_unnormalized.stencil(blur_unnormalized_s1_x_x, blur_unnormalized_s1_y) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), blur_unnormalized_s1_y)*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), blur_unnormalized_s1_y)*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), blur_unnormalized_s1_y)*(uint16)2) + (gray.stencil((blur_unnormalized_s1_x_x + 5), blur_unnormalized_s1_y) + (gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 1)) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 1))*(uint16)3) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 1))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 1))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 1))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 1))*(uint16)3) + (gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 1)) + ((gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 2))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 2))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 2))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 2))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 2))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 2))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 2))*(uint16)2) + ((gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 3))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 3))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 3))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 3))*(uint16)18) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 3))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 3))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 3))*(uint16)2) + ((gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 4))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 4))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 4))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 4))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 4))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 4))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 4))*(uint16)2) + (gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 5)) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 5))*(uint16)3) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 5))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 5))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 5))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 5))*(uint16)3) + (gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 5)) + (gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 6)) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 6))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 6))*(uint16)2) + (gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 6)) + (gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 6))*(uint16)2)))))))))))))))))))))))))))))))))))))))))))))) + auto hcompute_blur_unnormalized_stencil_1 = blur_unnormalized_s1_x_x->add_op("op_hcompute_blur_unnormalized_stencil_1"); + hcompute_blur_unnormalized_stencil_1->add_function("hcompute_blur_unnormalized_stencil_1"); + hcompute_blur_unnormalized_stencil_1->add_load("blur_unnormalized_stencil", "blur_unnormalized_s1_y", "blur_unnormalized_s1_x_x"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 1)", "(blur_unnormalized_s1_x_x + 3)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 1)", "(blur_unnormalized_s1_x_x + 4)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 1)", "(blur_unnormalized_s1_x_x + 5)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 1)", "(blur_unnormalized_s1_x_x + 6)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 2)", "blur_unnormalized_s1_x_x"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 2)", "(blur_unnormalized_s1_x_x + 1)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 2)", "(blur_unnormalized_s1_x_x + 2)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 2)", "(blur_unnormalized_s1_x_x + 3)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 2)", "(blur_unnormalized_s1_x_x + 4)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 2)", "(blur_unnormalized_s1_x_x + 5)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "blur_unnormalized_s1_y", "(blur_unnormalized_s1_x_x + 1)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 2)", "(blur_unnormalized_s1_x_x + 6)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 3)", "blur_unnormalized_s1_x_x"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 3)", "(blur_unnormalized_s1_x_x + 1)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 3)", "(blur_unnormalized_s1_x_x + 2)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 3)", "(blur_unnormalized_s1_x_x + 3)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 3)", "(blur_unnormalized_s1_x_x + 4)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 3)", "(blur_unnormalized_s1_x_x + 5)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 3)", "(blur_unnormalized_s1_x_x + 6)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 4)", "blur_unnormalized_s1_x_x"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 4)", "(blur_unnormalized_s1_x_x + 1)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "blur_unnormalized_s1_y", "(blur_unnormalized_s1_x_x + 2)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 4)", "(blur_unnormalized_s1_x_x + 2)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 4)", "(blur_unnormalized_s1_x_x + 3)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 4)", "(blur_unnormalized_s1_x_x + 4)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 4)", "(blur_unnormalized_s1_x_x + 5)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 4)", "(blur_unnormalized_s1_x_x + 6)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 5)", "blur_unnormalized_s1_x_x"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 5)", "(blur_unnormalized_s1_x_x + 1)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 5)", "(blur_unnormalized_s1_x_x + 2)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 5)", "(blur_unnormalized_s1_x_x + 3)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 5)", "(blur_unnormalized_s1_x_x + 4)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "blur_unnormalized_s1_y", "(blur_unnormalized_s1_x_x + 3)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 5)", "(blur_unnormalized_s1_x_x + 5)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 5)", "(blur_unnormalized_s1_x_x + 6)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 6)", "(blur_unnormalized_s1_x_x + 1)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 6)", "(blur_unnormalized_s1_x_x + 2)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 6)", "(blur_unnormalized_s1_x_x + 3)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 6)", "(blur_unnormalized_s1_x_x + 5)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 6)", "(blur_unnormalized_s1_x_x + 4)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "blur_unnormalized_s1_y", "(blur_unnormalized_s1_x_x + 4)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "blur_unnormalized_s1_y", "(blur_unnormalized_s1_x_x + 5)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 1)", "blur_unnormalized_s1_x_x"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 1)", "(blur_unnormalized_s1_x_x + 1)"); + hcompute_blur_unnormalized_stencil_1->add_load("gray_stencil", "(blur_unnormalized_s1_y + 1)", "(blur_unnormalized_s1_x_x + 2)"); + hcompute_blur_unnormalized_stencil_1->add_store("blur_unnormalized_stencil", "blur_unnormalized_s1_y", "blur_unnormalized_s1_x_x"); + +//consuming blur_unnormalized.stencil +////producing sharpen.stencil + auto sharpen_s0_y = prg.add_loop("sharpen_s0_y", 0, 250); + auto sharpen_s0_x_x = sharpen_s0_y->add_loop("sharpen_s0_x_x", 0, 126); + +//store is: sharpen.stencil(sharpen_s0_x_x, sharpen_s0_y) = uint16(max(min(((int16(gray.stencil((sharpen_s0_x_x + 3), (sharpen_s0_y + 3)))*(int16)2) - int16(uint8((blur_unnormalized.stencil(sharpen_s0_x_x, sharpen_s0_y)/(uint16)256)))), (int16)255), (int16)0)) + auto hcompute_sharpen_stencil = sharpen_s0_x_x->add_op("op_hcompute_sharpen_stencil"); + hcompute_sharpen_stencil->add_function("hcompute_sharpen_stencil"); + hcompute_sharpen_stencil->add_load("blur_unnormalized_stencil", "sharpen_s0_y", "sharpen_s0_x_x"); + hcompute_sharpen_stencil->add_load("gray_stencil", "(sharpen_s0_y + 3)", "(sharpen_s0_x_x + 3)"); + prg.buffer_port_widths["sharpen_stencil"] = 16; + hcompute_sharpen_stencil->add_store("sharpen_stencil", "sharpen_s0_y", "sharpen_s0_x_x"); + +//consuming sharpen.stencil +////producing ratio.stencil + auto ratio_s0_y = prg.add_loop("ratio_s0_y", 0, 250); + auto ratio_s0_x_x = ratio_s0_y->add_loop("ratio_s0_x_x", 0, 126); + +//store is: ratio.stencil(ratio_s0_x_x, ratio_s0_y) = (sharpen.stencil(ratio_s0_x_x, ratio_s0_y)*reciprocal.stencil(ratio_s0_x_x, ratio_s0_y)) + auto hcompute_ratio_stencil = ratio_s0_x_x->add_op("op_hcompute_ratio_stencil"); + hcompute_ratio_stencil->add_function("hcompute_ratio_stencil"); + hcompute_ratio_stencil->add_load("reciprocal_stencil", "ratio_s0_y", "ratio_s0_x_x"); + hcompute_ratio_stencil->add_load("sharpen_stencil", "ratio_s0_y", "ratio_s0_x_x"); + prg.buffer_port_widths["ratio_stencil"] = 16; + hcompute_ratio_stencil->add_store("ratio_stencil", "ratio_s0_y", "ratio_s0_x_x"); + +//consuming ratio.stencil + auto hw_output_s0_y_yi = prg.add_loop("hw_output_s0_y_yi", 0, 250); + auto hw_output_s0_x_xi_xi = hw_output_s0_y_yi->add_loop("hw_output_s0_x_xi_xi", 0, 126); + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = int16(((int32(ratio.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi))*int32(hw_input_global_wrapper_global_wrapper.stencil(0, (hw_output_s0_x_xi_xi + 3), (hw_output_s0_y_yi + 3))))/256)) + auto hcompute_hw_output_glb_stencil = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_function("hcompute_hw_output_glb_stencil"); + hcompute_hw_output_glb_stencil->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(hw_output_s0_y_yi + 3)", "(hw_output_s0_x_xi_xi + 3)", "0"); + hcompute_hw_output_glb_stencil->add_load("ratio_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi"); + prg.buffer_port_widths["hw_output_glb_stencil"] = 16; + hcompute_hw_output_glb_stencil->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi", "0"); + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = int16(((int32(ratio.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi))*int32(hw_input_global_wrapper_global_wrapper.stencil(1, (hw_output_s0_x_xi_xi + 3), (hw_output_s0_y_yi + 3))))/256)) + auto hcompute_hw_output_glb_stencil_1 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_function("hcompute_hw_output_glb_stencil_1"); + hcompute_hw_output_glb_stencil_1->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(hw_output_s0_y_yi + 3)", "(hw_output_s0_x_xi_xi + 3)", "1"); + hcompute_hw_output_glb_stencil_1->add_load("ratio_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_1->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi", "1"); + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = int16(((int32(ratio.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi))*int32(hw_input_global_wrapper_global_wrapper.stencil(2, (hw_output_s0_x_xi_xi + 3), (hw_output_s0_y_yi + 3))))/256)) + auto hcompute_hw_output_glb_stencil_2 = hw_output_s0_x_xi_xi->add_op("op_hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_function("hcompute_hw_output_glb_stencil_2"); + hcompute_hw_output_glb_stencil_2->add_load("hw_input_global_wrapper_global_wrapper_stencil", "(hw_output_s0_y_yi + 3)", "(hw_output_s0_x_xi_xi + 3)", "2"); + hcompute_hw_output_glb_stencil_2->add_load("ratio_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi"); + hcompute_hw_output_glb_stencil_2->add_store("hw_output_glb_stencil", "hw_output_s0_y_yi", "hw_output_s0_x_xi_xi", "2"); + +//consuming hw_output.glb.stencil + auto hw_output_global_wrapper_s0_y_yi = prg.add_loop("hw_output_global_wrapper_s0_y_yi", 0, 250); + auto hw_output_global_wrapper_s0_x_xi_xi = hw_output_global_wrapper_s0_y_yi->add_loop("hw_output_global_wrapper_s0_x_xi_xi", 0, 126); + +//store is: hw_output_global_wrapper.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_function("hcompute_hw_output_global_wrapper_stencil"); + hcompute_hw_output_global_wrapper_stencil->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + hcompute_hw_output_global_wrapper_stencil->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "0"); + +//store is: hw_output_global_wrapper.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_1 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_function("hcompute_hw_output_global_wrapper_stencil_1"); + hcompute_hw_output_global_wrapper_stencil_1->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + hcompute_hw_output_global_wrapper_stencil_1->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "1"); + +//store is: hw_output_global_wrapper.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) + auto hcompute_hw_output_global_wrapper_stencil_2 = hw_output_global_wrapper_s0_x_xi_xi->add_op("op_hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_function("hcompute_hw_output_global_wrapper_stencil_2"); + hcompute_hw_output_global_wrapper_stencil_2->add_load("hw_output_glb_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + hcompute_hw_output_global_wrapper_stencil_2->add_store("hw_output_global_wrapper_stencil", "hw_output_global_wrapper_s0_y_yi", "hw_output_global_wrapper_s0_x_xi_xi", "2"); + + return prg; +} + + + prog unsharp_isscc() { prog prg; prg.compute_unit_file = "unsharp_isscc_compute.h"; diff --git a/fp_arith_compute.h b/fp_arith_compute.h new file mode 100644 index 000000000..df222cd3a --- /dev/null +++ b/fp_arith_compute.h @@ -0,0 +1,29 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_1; +} + +//store is: mult.stencil(mult_s0_x, mult_s0_y) = (bfloat16(hw_input_global_wrapper.stencil(mult_s0_x, mult_s0_y))*13.250000h) +hw_uint<16> hcompute_mult_stencil(hw_uint<16>& hw_input_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_stencil_1 = (uint16_t) hw_input_global_wrapper_stencil.extract<0, 15>(); + + bfloat16_t _257 = (bfloat16_t)(_hw_input_global_wrapper_stencil_1); + bfloat16_t _258 = bfloat_from_bits(1096024064 /* 13.25 */); + bfloat16_t _259 = _257 * _258; + return _259; +} + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(mult.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& mult_stencil) { + uint16_t _mult_stencil_1 = (uint16_t) mult_stencil.extract<0, 15>(); + + return _mult_stencil_1; +} + diff --git a/fp_pointwise_compute.h b/fp_pointwise_compute.h new file mode 100644 index 000000000..0a1fff39b --- /dev/null +++ b/fp_pointwise_compute.h @@ -0,0 +1,28 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_1 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: product.stencil(product_s0_x, product_s0_y) = (hw_input_global_wrapper.stencil(product_s0_x, product_s0_y)*3.140625h) +hw_uint<16> hcompute_product_stencil(hw_uint<16>& hw_input_global_wrapper_stencil) { + bfloat16_t _hw_input_global_wrapper_stencil_1 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _272 = bfloat_from_bits(1078525952 /* 3.14062 */); + bfloat16_t _273 = _hw_input_global_wrapper_stencil_1 * _272; + return _273; +} + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) = product.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& product_stencil) { + bfloat16_t _product_stencil_1 = bfloat16_t::make_from_bits(product_stencil.extract<0, 15>()); + + return _product_stencil_1; +} + diff --git a/harris_color_unroll4_compute.h b/harris_color_unroll4_compute.h new file mode 100644 index 000000000..0bd36b4c6 --- /dev/null +++ b/harris_color_unroll4_compute.h @@ -0,0 +1,2629 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.glb.stencil(0, (hw_input_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(0, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -3), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_1 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.glb.stencil(1, (hw_input_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(1, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -3), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_1(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_2 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.glb.stencil(2, (hw_input_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(2, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -3), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_2(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_3 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(0, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -2), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_3(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_4 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_4; +} + +//store is: hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(1, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -2), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_4(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_5 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_5; +} + +//store is: hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(2, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -2), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_5(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_6 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_6; +} + +//store is: hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(0, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -1), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_6(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_7 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_7; +} + +//store is: hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(1, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -1), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_7(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_8 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_8; +} + +//store is: hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(2, (((hw_input_global_wrapper_s0_x_x*4) + (0*294)) + -1), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_8(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_9 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_9; +} + +//store is: hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(0, ((hw_input_global_wrapper_s0_x_x*4) + (0*294)), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_9(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_10 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_10; +} + +//store is: hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(1, ((hw_input_global_wrapper_s0_x_x*4) + (0*294)), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_10(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_11 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_11; +} + +//store is: hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(2, ((hw_input_global_wrapper_s0_x_x*4) + (0*294)), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_11(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_12 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_12; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_1 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_1; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_1(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_2 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_2; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, (hw_input_global_wrapper_global_wrapper_s0_x_x*4), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_2(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_3 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_3; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_3(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_4 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_4; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_4(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_5 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_5; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_5(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_6 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_6; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_6(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_7 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_7; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_7(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_8 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_8; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_8(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_9 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_9; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_9(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_10 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_10; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_10(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_11 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_11; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_11(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_12 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_12; +} + +//store is: gray.stencil((gray_s0_x_x*4), ((gray_s0_y + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, (gray_s0_x_x*4), ((gray_s0_y + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, (gray_s0_x_x*4), ((gray_s0_y + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, (gray_s0_x_x*4), ((gray_s0_y + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_1 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_2 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_3 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _480 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_1); + uint16_t _481 = (uint16_t)(150); + uint16_t _482 = _480 * _481; + uint16_t _483 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_2); + uint16_t _484 = (uint16_t)(29); + uint16_t _485 = _483 * _484; + uint16_t _486 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_3); + uint16_t _487 = (uint16_t)(77); + uint16_t _488 = _486 * _487; + uint16_t _489 = _485 + _488; + uint16_t _490 = _482 + _489; + uint16_t _491 = (uint16_t)(8); + uint16_t _492 = _490 >> _491; + return _492; +} + +//store is: gray.stencil(((gray_s0_x_x*4) + 1), ((gray_s0_y + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x*4) + 1), ((gray_s0_y + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x*4) + 1), ((gray_s0_y + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x*4) + 1), ((gray_s0_y + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil_1(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_4 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_5 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_6 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _525 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_4); + uint16_t _526 = (uint16_t)(150); + uint16_t _527 = _525 * _526; + uint16_t _528 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_5); + uint16_t _529 = (uint16_t)(29); + uint16_t _530 = _528 * _529; + uint16_t _531 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_6); + uint16_t _532 = (uint16_t)(77); + uint16_t _533 = _531 * _532; + uint16_t _534 = _530 + _533; + uint16_t _535 = _527 + _534; + uint16_t _536 = (uint16_t)(8); + uint16_t _537 = _535 >> _536; + return _537; +} + +//store is: gray.stencil(((gray_s0_x_x*4) + 2), ((gray_s0_y + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x*4) + 2), ((gray_s0_y + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x*4) + 2), ((gray_s0_y + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x*4) + 2), ((gray_s0_y + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil_2(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_7 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_8 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_9 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _571 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_7); + uint16_t _572 = (uint16_t)(150); + uint16_t _573 = _571 * _572; + uint16_t _574 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_8); + uint16_t _575 = (uint16_t)(29); + uint16_t _576 = _574 * _575; + uint16_t _577 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_9); + uint16_t _578 = (uint16_t)(77); + uint16_t _579 = _577 * _578; + uint16_t _580 = _576 + _579; + uint16_t _581 = _573 + _580; + uint16_t _582 = (uint16_t)(8); + uint16_t _583 = _581 >> _582; + return _583; +} + +//store is: gray.stencil(((gray_s0_x_x*4) + 3), ((gray_s0_y + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x*4) + 3), ((gray_s0_y + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x*4) + 3), ((gray_s0_y + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x*4) + 3), ((gray_s0_y + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil_3(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_10 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_11 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_12 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _617 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_10); + uint16_t _618 = (uint16_t)(150); + uint16_t _619 = _617 * _618; + uint16_t _620 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_11); + uint16_t _621 = (uint16_t)(29); + uint16_t _622 = _620 * _621; + uint16_t _623 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_12); + uint16_t _624 = (uint16_t)(77); + uint16_t _625 = _623 * _624; + uint16_t _626 = _622 + _625; + uint16_t _627 = _619 + _626; + uint16_t _628 = (uint16_t)(8); + uint16_t _629 = _627 >> _628; + return _629; +} + +//store is: grad_x_unclamp.stencil((grad_x_unclamp_s0_x_x*4), ((grad_x_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil() { + int16_t _664 = (int16_t)(0); + return _664; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x*4) + 1), ((grad_x_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil_1() { + int16_t _670 = (int16_t)(0); + return _670; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x*4) + 2), ((grad_x_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil_2() { + int16_t _677 = (int16_t)(0); + return _677; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x*4) + 3), ((grad_x_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil_3() { + int16_t _684 = (int16_t)(0); + return _684; +} + +//store is: grad_x_unclamp.stencil((grad_x_unclamp_s1_x_x*4), ((grad_x_unclamp_s1_y + -2) + 2)) = ((((((grad_x_unclamp.stencil((grad_x_unclamp_s1_x_x*4), ((grad_x_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil((grad_x_unclamp_s1_x_x*4), ((grad_x_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil((grad_x_unclamp_s1_x_x*4), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil((grad_x_unclamp_s1_x_x*4), ((grad_x_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_4(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_1 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_1 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_2 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_3 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_4 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_5 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_6 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _692 = (int16_t)(_gray_stencil_1); + int16_t _693 = (int16_t)(2); + int16_t _694 = _692 * _693; + int16_t _695 = _grad_x_unclamp_stencil_1 + _694; + int16_t _696 = (int16_t)(_gray_stencil_2); + int16_t _697 = _695 - _696; + int16_t _698 = (int16_t)(_gray_stencil_3); + int16_t _699 = _697 + _698; + int16_t _700 = (int16_t)(_gray_stencil_4); + int16_t _701 = _700 * _693; + int16_t _702 = _699 - _701; + int16_t _703 = (int16_t)(_gray_stencil_5); + int16_t _704 = _702 - _703; + int16_t _705 = (int16_t)(_gray_stencil_6); + int16_t _706 = _704 + _705; + return _706; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 1), ((grad_x_unclamp_s1_y + -2) + 2)) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 1), ((grad_x_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 1), ((grad_x_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 1), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 1), ((grad_x_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_5(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_2 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_10 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_11 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_12 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_7 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_8 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_9 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _750 = (int16_t)(_gray_stencil_7); + int16_t _751 = (int16_t)(2); + int16_t _752 = _750 * _751; + int16_t _753 = _grad_x_unclamp_stencil_2 + _752; + int16_t _754 = (int16_t)(_gray_stencil_8); + int16_t _755 = _753 - _754; + int16_t _756 = (int16_t)(_gray_stencil_9); + int16_t _757 = _755 + _756; + int16_t _758 = (int16_t)(_gray_stencil_10); + int16_t _759 = _758 * _751; + int16_t _760 = _757 - _759; + int16_t _761 = (int16_t)(_gray_stencil_11); + int16_t _762 = _760 - _761; + int16_t _763 = (int16_t)(_gray_stencil_12); + int16_t _764 = _762 + _763; + return _764; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 2)) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 4), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 4), ((grad_x_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 2), ((grad_x_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 4), ((grad_x_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_6(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_3 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_13 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_14 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_15 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_16 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_17 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_18 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _809 = (int16_t)(_gray_stencil_13); + int16_t _810 = (int16_t)(2); + int16_t _811 = _809 * _810; + int16_t _812 = _grad_x_unclamp_stencil_3 + _811; + int16_t _813 = (int16_t)(_gray_stencil_14); + int16_t _814 = _812 - _813; + int16_t _815 = (int16_t)(_gray_stencil_15); + int16_t _816 = _814 + _815; + int16_t _817 = (int16_t)(_gray_stencil_16); + int16_t _818 = _817 * _810; + int16_t _819 = _816 - _818; + int16_t _820 = (int16_t)(_gray_stencil_17); + int16_t _821 = _819 - _820; + int16_t _822 = (int16_t)(_gray_stencil_18); + int16_t _823 = _821 + _822; + return _823; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 2)) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 5), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 5), ((grad_x_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 3), ((grad_x_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x*4) + 5), ((grad_x_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_7(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_4 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_19 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_20 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_21 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_22 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_23 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_24 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _868 = (int16_t)(_gray_stencil_19); + int16_t _869 = (int16_t)(2); + int16_t _870 = _868 * _869; + int16_t _871 = _grad_x_unclamp_stencil_4 + _870; + int16_t _872 = (int16_t)(_gray_stencil_20); + int16_t _873 = _871 - _872; + int16_t _874 = (int16_t)(_gray_stencil_21); + int16_t _875 = _873 + _874; + int16_t _876 = (int16_t)(_gray_stencil_22); + int16_t _877 = _876 * _869; + int16_t _878 = _875 - _877; + int16_t _879 = (int16_t)(_gray_stencil_23); + int16_t _880 = _878 - _879; + int16_t _881 = (int16_t)(_gray_stencil_24); + int16_t _882 = _880 + _881; + return _882; +} + +//store is: lxx.stencil((lxx_s0_x_x*4), ((lxx_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil((lxx_s0_x_x*4), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil((lxx_s0_x_x*4), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_5 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _928 = (int16_t)(180); + int16_t _929 = min(_grad_x_unclamp_stencil_5, _928); + int16_t _930 = (int16_t)(-180); + int16_t _931 = max(_929, _930); + int16_t _932 = _931 * _931; + int16_t _933 = (int16_t)(6); + int16_t _934 = _932 >> _933; + return _934; +} + +//store is: lxx.stencil(((lxx_s0_x_x*4) + 1), ((lxx_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 1), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 1), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil_1(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_6 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _953 = (int16_t)(180); + int16_t _954 = min(_grad_x_unclamp_stencil_6, _953); + int16_t _955 = (int16_t)(-180); + int16_t _956 = max(_954, _955); + int16_t _957 = _956 * _956; + int16_t _958 = (int16_t)(6); + int16_t _959 = _957 >> _958; + return _959; +} + +//store is: lxx.stencil(((lxx_s0_x_x*4) + 2), ((lxx_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 2), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 2), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil_2(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_7 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _979 = (int16_t)(180); + int16_t _980 = min(_grad_x_unclamp_stencil_7, _979); + int16_t _981 = (int16_t)(-180); + int16_t _982 = max(_980, _981); + int16_t _983 = _982 * _982; + int16_t _984 = (int16_t)(6); + int16_t _985 = _983 >> _984; + return _985; +} + +//store is: lxx.stencil(((lxx_s0_x_x*4) + 3), ((lxx_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 3), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x*4) + 3), ((lxx_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil_3(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_8 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _1005 = (int16_t)(180); + int16_t _1006 = min(_grad_x_unclamp_stencil_8, _1005); + int16_t _1007 = (int16_t)(-180); + int16_t _1008 = max(_1006, _1007); + int16_t _1009 = _1008 * _1008; + int16_t _1010 = (int16_t)(6); + int16_t _1011 = _1009 >> _1010; + return _1011; +} + +//store is: lgxx.stencil((lgxx_s0_x_x*4), ((lgxx_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil() { + int16_t _1032 = (int16_t)(0); + return _1032; +} + +//store is: lgxx.stencil(((lgxx_s0_x_x*4) + 1), ((lgxx_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil_1() { + int16_t _1038 = (int16_t)(0); + return _1038; +} + +//store is: lgxx.stencil(((lgxx_s0_x_x*4) + 2), ((lgxx_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil_2() { + int16_t _1045 = (int16_t)(0); + return _1045; +} + +//store is: lgxx.stencil(((lgxx_s0_x_x*4) + 3), ((lgxx_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil_3() { + int16_t _1052 = (int16_t)(0); + return _1052; +} + +//store is: lgxx.stencil((lgxx_s1_x_x*4), ((lgxx_s1_y + -1) + 1)) = (lxx.stencil((lgxx_s1_x_x*4), ((lgxx_s1_y + -1) + 1)) + (lgxx.stencil((lgxx_s1_x_x*4), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil((lgxx_s1_x_x*4), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil((lgxx_s1_x_x*4), ((lgxx_s1_y + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_4(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_1 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_1 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_2 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_3 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_4 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_5 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_6 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_7 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_8 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_9 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _1060 = _lxx_stencil_8 + _lxx_stencil_9; + int16_t _1061 = _lxx_stencil_7 + _1060; + int16_t _1062 = _lxx_stencil_6 + _1061; + int16_t _1063 = _lxx_stencil_5 + _1062; + int16_t _1064 = _lxx_stencil_4 + _1063; + int16_t _1065 = _lxx_stencil_3 + _1064; + int16_t _1066 = _lxx_stencil_2 + _1065; + int16_t _1067 = _lgxx_stencil_1 + _1066; + int16_t _1068 = _lxx_stencil_1 + _1067; + return _1068; +} + +//store is: lgxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 1)) = (lxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 1)) + (lgxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 1), ((lgxx_s1_y + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_5(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_2 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_10 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_11 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_12 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_13 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_14 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_15 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_16 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_17 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_18 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _1104 = _lxx_stencil_17 + _lxx_stencil_18; + int16_t _1105 = _lxx_stencil_16 + _1104; + int16_t _1106 = _lxx_stencil_15 + _1105; + int16_t _1107 = _lxx_stencil_14 + _1106; + int16_t _1108 = _lxx_stencil_13 + _1107; + int16_t _1109 = _lxx_stencil_12 + _1108; + int16_t _1110 = _lxx_stencil_11 + _1109; + int16_t _1111 = _lgxx_stencil_2 + _1110; + int16_t _1112 = _lxx_stencil_10 + _1111; + return _1112; +} + +//store is: lgxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 1)) = (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 1)) + (lgxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 2), ((lgxx_s1_y + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), ((lgxx_s1_y + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_6(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_3 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_19 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_20 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_21 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_22 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_23 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_24 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_25 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_26 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_27 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _1149 = _lxx_stencil_26 + _lxx_stencil_27; + int16_t _1150 = _lxx_stencil_25 + _1149; + int16_t _1151 = _lxx_stencil_24 + _1150; + int16_t _1152 = _lxx_stencil_23 + _1151; + int16_t _1153 = _lxx_stencil_22 + _1152; + int16_t _1154 = _lxx_stencil_21 + _1153; + int16_t _1155 = _lxx_stencil_20 + _1154; + int16_t _1156 = _lgxx_stencil_3 + _1155; + int16_t _1157 = _lxx_stencil_19 + _1156; + return _1157; +} + +//store is: lgxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 1)) = (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 1)) + (lgxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 5), ((lgxx_s1_y + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 4), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 5), ((lgxx_s1_y + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x*4) + 3), ((lgxx_s1_y + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x*4) + 5), ((lgxx_s1_y + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x*4) + 4), ((lgxx_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_7(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_4 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_28 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_29 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_30 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_31 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_32 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_33 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_34 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_35 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_36 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _1194 = _lxx_stencil_35 + _lxx_stencil_36; + int16_t _1195 = _lxx_stencil_34 + _1194; + int16_t _1196 = _lxx_stencil_33 + _1195; + int16_t _1197 = _lxx_stencil_32 + _1196; + int16_t _1198 = _lxx_stencil_31 + _1197; + int16_t _1199 = _lxx_stencil_30 + _1198; + int16_t _1200 = _lxx_stencil_29 + _1199; + int16_t _1201 = _lgxx_stencil_4 + _1200; + int16_t _1202 = _lxx_stencil_28 + _1201; + return _1202; +} + +//store is: grad_y_unclamp.stencil((grad_y_unclamp_s0_x_x*4), ((grad_y_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil() { + int16_t _1240 = (int16_t)(0); + return _1240; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x*4) + 1), ((grad_y_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil_1() { + int16_t _1246 = (int16_t)(0); + return _1246; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x*4) + 2), ((grad_y_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil_2() { + int16_t _1253 = (int16_t)(0); + return _1253; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x*4) + 3), ((grad_y_unclamp_s0_y + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil_3() { + int16_t _1260 = (int16_t)(0); + return _1260; +} + +//store is: grad_y_unclamp.stencil((grad_y_unclamp_s1_x_x*4), ((grad_y_unclamp_s1_y + -2) + 2)) = ((((((grad_y_unclamp.stencil((grad_y_unclamp_s1_x_x*4), ((grad_y_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), ((grad_y_unclamp_s1_y + -2) + 4)))*(int16)2)) - int16(gray.stencil((grad_y_unclamp_s1_x_x*4), ((grad_y_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), ((grad_y_unclamp_s1_y + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil((grad_y_unclamp_s1_x_x*4), ((grad_y_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_4(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_1 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_25 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_26 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_27 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_28 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_29 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_30 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _1268 = (int16_t)(_gray_stencil_25); + int16_t _1269 = (int16_t)(2); + int16_t _1270 = _1268 * _1269; + int16_t _1271 = _grad_y_unclamp_stencil_1 + _1270; + int16_t _1272 = (int16_t)(_gray_stencil_26); + int16_t _1273 = _1271 - _1272; + int16_t _1274 = (int16_t)(_gray_stencil_27); + int16_t _1275 = _1274 * _1269; + int16_t _1276 = _1273 - _1275; + int16_t _1277 = (int16_t)(_gray_stencil_28); + int16_t _1278 = _1276 - _1277; + int16_t _1279 = (int16_t)(_gray_stencil_29); + int16_t _1280 = _1278 + _1279; + int16_t _1281 = (int16_t)(_gray_stencil_30); + int16_t _1282 = _1280 + _1281; + return _1282; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 1), ((grad_y_unclamp_s1_y + -2) + 2)) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 1), ((grad_y_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 4)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), ((grad_y_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 1), ((grad_y_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_5(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_2 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_31 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_32 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_33 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_34 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_35 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_36 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _1326 = (int16_t)(_gray_stencil_31); + int16_t _1327 = (int16_t)(2); + int16_t _1328 = _1326 * _1327; + int16_t _1329 = _grad_y_unclamp_stencil_2 + _1328; + int16_t _1330 = (int16_t)(_gray_stencil_32); + int16_t _1331 = _1329 - _1330; + int16_t _1332 = (int16_t)(_gray_stencil_33); + int16_t _1333 = _1332 * _1327; + int16_t _1334 = _1331 - _1333; + int16_t _1335 = (int16_t)(_gray_stencil_34); + int16_t _1336 = _1334 - _1335; + int16_t _1337 = (int16_t)(_gray_stencil_35); + int16_t _1338 = _1336 + _1337; + int16_t _1339 = (int16_t)(_gray_stencil_36); + int16_t _1340 = _1338 + _1339; + return _1340; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 2)) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 4)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), ((grad_y_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 2), ((grad_y_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), ((grad_y_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_6(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_3 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_37 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_38 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_39 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_40 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_41 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_42 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _1385 = (int16_t)(_gray_stencil_37); + int16_t _1386 = (int16_t)(2); + int16_t _1387 = _1385 * _1386; + int16_t _1388 = _grad_y_unclamp_stencil_3 + _1387; + int16_t _1389 = (int16_t)(_gray_stencil_38); + int16_t _1390 = _1388 - _1389; + int16_t _1391 = (int16_t)(_gray_stencil_39); + int16_t _1392 = _1391 * _1386; + int16_t _1393 = _1390 - _1392; + int16_t _1394 = (int16_t)(_gray_stencil_40); + int16_t _1395 = _1393 - _1394; + int16_t _1396 = (int16_t)(_gray_stencil_41); + int16_t _1397 = _1395 + _1396; + int16_t _1398 = (int16_t)(_gray_stencil_42); + int16_t _1399 = _1397 + _1398; + return _1399; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 2)) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), ((grad_y_unclamp_s1_y + -2) + 4)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 4), ((grad_y_unclamp_s1_y + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 5), ((grad_y_unclamp_s1_y + -2) + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 3), ((grad_y_unclamp_s1_y + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x*4) + 5), ((grad_y_unclamp_s1_y + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_7(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_4 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_43 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_44 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_45 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_46 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_47 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_48 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _1444 = (int16_t)(_gray_stencil_43); + int16_t _1445 = (int16_t)(2); + int16_t _1446 = _1444 * _1445; + int16_t _1447 = _grad_y_unclamp_stencil_4 + _1446; + int16_t _1448 = (int16_t)(_gray_stencil_44); + int16_t _1449 = _1447 - _1448; + int16_t _1450 = (int16_t)(_gray_stencil_45); + int16_t _1451 = _1450 * _1445; + int16_t _1452 = _1449 - _1451; + int16_t _1453 = (int16_t)(_gray_stencil_46); + int16_t _1454 = _1452 - _1453; + int16_t _1455 = (int16_t)(_gray_stencil_47); + int16_t _1456 = _1454 + _1455; + int16_t _1457 = (int16_t)(_gray_stencil_48); + int16_t _1458 = _1456 + _1457; + return _1458; +} + +//store is: lxy.stencil((lxy_s0_x_x*4), ((lxy_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil((lxy_s0_x_x*4), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil((lxy_s0_x_x*4), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_9 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_5 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1504 = (int16_t)(180); + int16_t _1505 = min(_grad_x_unclamp_stencil_9, _1504); + int16_t _1506 = (int16_t)(-180); + int16_t _1507 = max(_1505, _1506); + int16_t _1508 = min(_grad_y_unclamp_stencil_5, _1504); + int16_t _1509 = max(_1508, _1506); + int16_t _1510 = _1507 * _1509; + int16_t _1511 = (int16_t)(6); + int16_t _1512 = _1510 >> _1511; + return _1512; +} + +//store is: lxy.stencil(((lxy_s0_x_x*4) + 1), ((lxy_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x*4) + 1), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x*4) + 1), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil_1(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_10 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_6 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1536 = (int16_t)(180); + int16_t _1537 = min(_grad_x_unclamp_stencil_10, _1536); + int16_t _1538 = (int16_t)(-180); + int16_t _1539 = max(_1537, _1538); + int16_t _1540 = min(_grad_y_unclamp_stencil_6, _1536); + int16_t _1541 = max(_1540, _1538); + int16_t _1542 = _1539 * _1541; + int16_t _1543 = (int16_t)(6); + int16_t _1544 = _1542 >> _1543; + return _1544; +} + +//store is: lxy.stencil(((lxy_s0_x_x*4) + 2), ((lxy_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x*4) + 2), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x*4) + 2), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil_2(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_11 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_7 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1569 = (int16_t)(180); + int16_t _1570 = min(_grad_x_unclamp_stencil_11, _1569); + int16_t _1571 = (int16_t)(-180); + int16_t _1572 = max(_1570, _1571); + int16_t _1573 = min(_grad_y_unclamp_stencil_7, _1569); + int16_t _1574 = max(_1573, _1571); + int16_t _1575 = _1572 * _1574; + int16_t _1576 = (int16_t)(6); + int16_t _1577 = _1575 >> _1576; + return _1577; +} + +//store is: lxy.stencil(((lxy_s0_x_x*4) + 3), ((lxy_s0_y + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x*4) + 3), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x*4) + 3), ((lxy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil_3(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_12 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_8 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1602 = (int16_t)(180); + int16_t _1603 = min(_grad_x_unclamp_stencil_12, _1602); + int16_t _1604 = (int16_t)(-180); + int16_t _1605 = max(_1603, _1604); + int16_t _1606 = min(_grad_y_unclamp_stencil_8, _1602); + int16_t _1607 = max(_1606, _1604); + int16_t _1608 = _1605 * _1607; + int16_t _1609 = (int16_t)(6); + int16_t _1610 = _1608 >> _1609; + return _1610; +} + +//store is: lgxy.stencil((lgxy_s0_x_x*4), ((lgxy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil() { + int16_t _1636 = (int16_t)(0); + return _1636; +} + +//store is: lgxy.stencil(((lgxy_s0_x_x*4) + 1), ((lgxy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil_1() { + int16_t _1642 = (int16_t)(0); + return _1642; +} + +//store is: lgxy.stencil(((lgxy_s0_x_x*4) + 2), ((lgxy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil_2() { + int16_t _1649 = (int16_t)(0); + return _1649; +} + +//store is: lgxy.stencil(((lgxy_s0_x_x*4) + 3), ((lgxy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil_3() { + int16_t _1656 = (int16_t)(0); + return _1656; +} + +//store is: lgxy.stencil((lgxy_s1_x_x*4), ((lgxy_s1_y + -1) + 1)) = (lxy.stencil((lgxy_s1_x_x*4), ((lgxy_s1_y + -1) + 1)) + (lgxy.stencil((lgxy_s1_x_x*4), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil((lgxy_s1_x_x*4), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil((lgxy_s1_x_x*4), ((lgxy_s1_y + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_4(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_1 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_1 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_2 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_3 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_4 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_5 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_6 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_7 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_8 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_9 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _1664 = _lxy_stencil_8 + _lxy_stencil_9; + int16_t _1665 = _lxy_stencil_7 + _1664; + int16_t _1666 = _lxy_stencil_6 + _1665; + int16_t _1667 = _lxy_stencil_5 + _1666; + int16_t _1668 = _lxy_stencil_4 + _1667; + int16_t _1669 = _lxy_stencil_3 + _1668; + int16_t _1670 = _lxy_stencil_2 + _1669; + int16_t _1671 = _lgxy_stencil_1 + _1670; + int16_t _1672 = _lxy_stencil_1 + _1671; + return _1672; +} + +//store is: lgxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 1)) = (lxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 1)) + (lgxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 1), ((lgxy_s1_y + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_5(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_2 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_10 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_11 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_12 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_13 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_14 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_15 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_16 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_17 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_18 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _1708 = _lxy_stencil_17 + _lxy_stencil_18; + int16_t _1709 = _lxy_stencil_16 + _1708; + int16_t _1710 = _lxy_stencil_15 + _1709; + int16_t _1711 = _lxy_stencil_14 + _1710; + int16_t _1712 = _lxy_stencil_13 + _1711; + int16_t _1713 = _lxy_stencil_12 + _1712; + int16_t _1714 = _lxy_stencil_11 + _1713; + int16_t _1715 = _lgxy_stencil_2 + _1714; + int16_t _1716 = _lxy_stencil_10 + _1715; + return _1716; +} + +//store is: lgxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 1)) = (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 1)) + (lgxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 2), ((lgxy_s1_y + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), ((lgxy_s1_y + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_6(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_3 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_19 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_20 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_21 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_22 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_23 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_24 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_25 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_26 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_27 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _1753 = _lxy_stencil_26 + _lxy_stencil_27; + int16_t _1754 = _lxy_stencil_25 + _1753; + int16_t _1755 = _lxy_stencil_24 + _1754; + int16_t _1756 = _lxy_stencil_23 + _1755; + int16_t _1757 = _lxy_stencil_22 + _1756; + int16_t _1758 = _lxy_stencil_21 + _1757; + int16_t _1759 = _lxy_stencil_20 + _1758; + int16_t _1760 = _lgxy_stencil_3 + _1759; + int16_t _1761 = _lxy_stencil_19 + _1760; + return _1761; +} + +//store is: lgxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 1)) = (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 1)) + (lgxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 5), ((lgxy_s1_y + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 4), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 5), ((lgxy_s1_y + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x*4) + 3), ((lgxy_s1_y + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x*4) + 5), ((lgxy_s1_y + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x*4) + 4), ((lgxy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_7(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_4 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_28 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_29 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_30 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_31 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_32 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_33 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_34 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_35 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_36 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _1798 = _lxy_stencil_35 + _lxy_stencil_36; + int16_t _1799 = _lxy_stencil_34 + _1798; + int16_t _1800 = _lxy_stencil_33 + _1799; + int16_t _1801 = _lxy_stencil_32 + _1800; + int16_t _1802 = _lxy_stencil_31 + _1801; + int16_t _1803 = _lxy_stencil_30 + _1802; + int16_t _1804 = _lxy_stencil_29 + _1803; + int16_t _1805 = _lgxy_stencil_4 + _1804; + int16_t _1806 = _lxy_stencil_28 + _1805; + return _1806; +} + +//store is: lyy.stencil((lyy_s0_x_x*4), ((lyy_s0_y + -2) + 2)) = ((max(min(grad_y_unclamp.stencil((lyy_s0_x_x*4), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil((lyy_s0_x_x*4), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_9 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1844 = (int16_t)(180); + int16_t _1845 = min(_grad_y_unclamp_stencil_9, _1844); + int16_t _1846 = (int16_t)(-180); + int16_t _1847 = max(_1845, _1846); + int16_t _1848 = _1847 * _1847; + int16_t _1849 = (int16_t)(6); + int16_t _1850 = _1848 >> _1849; + return _1850; +} + +//store is: lyy.stencil(((lyy_s0_x_x*4) + 1), ((lyy_s0_y + -2) + 2)) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 1), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 1), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil_1(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_10 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1869 = (int16_t)(180); + int16_t _1870 = min(_grad_y_unclamp_stencil_10, _1869); + int16_t _1871 = (int16_t)(-180); + int16_t _1872 = max(_1870, _1871); + int16_t _1873 = _1872 * _1872; + int16_t _1874 = (int16_t)(6); + int16_t _1875 = _1873 >> _1874; + return _1875; +} + +//store is: lyy.stencil(((lyy_s0_x_x*4) + 2), ((lyy_s0_y + -2) + 2)) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 2), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 2), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil_2(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_11 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1895 = (int16_t)(180); + int16_t _1896 = min(_grad_y_unclamp_stencil_11, _1895); + int16_t _1897 = (int16_t)(-180); + int16_t _1898 = max(_1896, _1897); + int16_t _1899 = _1898 * _1898; + int16_t _1900 = (int16_t)(6); + int16_t _1901 = _1899 >> _1900; + return _1901; +} + +//store is: lyy.stencil(((lyy_s0_x_x*4) + 3), ((lyy_s0_y + -2) + 2)) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 3), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x*4) + 3), ((lyy_s0_y + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil_3(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_12 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _1921 = (int16_t)(180); + int16_t _1922 = min(_grad_y_unclamp_stencil_12, _1921); + int16_t _1923 = (int16_t)(-180); + int16_t _1924 = max(_1922, _1923); + int16_t _1925 = _1924 * _1924; + int16_t _1926 = (int16_t)(6); + int16_t _1927 = _1925 >> _1926; + return _1927; +} + +//store is: lgyy.stencil((lgyy_s0_x_x*4), ((lgyy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil() { + int16_t _1948 = (int16_t)(0); + return _1948; +} + +//store is: lgyy.stencil(((lgyy_s0_x_x*4) + 1), ((lgyy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil_1() { + int16_t _1954 = (int16_t)(0); + return _1954; +} + +//store is: lgyy.stencil(((lgyy_s0_x_x*4) + 2), ((lgyy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil_2() { + int16_t _1961 = (int16_t)(0); + return _1961; +} + +//store is: lgyy.stencil(((lgyy_s0_x_x*4) + 3), ((lgyy_s0_y + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil_3() { + int16_t _1968 = (int16_t)(0); + return _1968; +} + +//store is: lgyy.stencil((lgyy_s1_x_x*4), ((lgyy_s1_y + -1) + 1)) = (lyy.stencil((lgyy_s1_x_x*4), ((lgyy_s1_y + -1) + 1)) + (lgyy.stencil((lgyy_s1_x_x*4), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil((lgyy_s1_x_x*4), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil((lgyy_s1_x_x*4), ((lgyy_s1_y + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_4(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_1 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_1 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_2 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_3 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_4 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_5 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_6 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_7 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_8 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_9 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _1976 = _lyy_stencil_8 + _lyy_stencil_9; + int16_t _1977 = _lyy_stencil_7 + _1976; + int16_t _1978 = _lyy_stencil_6 + _1977; + int16_t _1979 = _lyy_stencil_5 + _1978; + int16_t _1980 = _lyy_stencil_4 + _1979; + int16_t _1981 = _lyy_stencil_3 + _1980; + int16_t _1982 = _lyy_stencil_2 + _1981; + int16_t _1983 = _lgyy_stencil_1 + _1982; + int16_t _1984 = _lyy_stencil_1 + _1983; + return _1984; +} + +//store is: lgyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 1)) = (lyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 1)) + (lgyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 1), ((lgyy_s1_y + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_5(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_2 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_10 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_11 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_12 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_13 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_14 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_15 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_16 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_17 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_18 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _2020 = _lyy_stencil_17 + _lyy_stencil_18; + int16_t _2021 = _lyy_stencil_16 + _2020; + int16_t _2022 = _lyy_stencil_15 + _2021; + int16_t _2023 = _lyy_stencil_14 + _2022; + int16_t _2024 = _lyy_stencil_13 + _2023; + int16_t _2025 = _lyy_stencil_12 + _2024; + int16_t _2026 = _lyy_stencil_11 + _2025; + int16_t _2027 = _lgyy_stencil_2 + _2026; + int16_t _2028 = _lyy_stencil_10 + _2027; + return _2028; +} + +//store is: lgyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 1)) = (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 1)) + (lgyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 2), ((lgyy_s1_y + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), ((lgyy_s1_y + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_6(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_3 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_19 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_20 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_21 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_22 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_23 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_24 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_25 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_26 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_27 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _2065 = _lyy_stencil_26 + _lyy_stencil_27; + int16_t _2066 = _lyy_stencil_25 + _2065; + int16_t _2067 = _lyy_stencil_24 + _2066; + int16_t _2068 = _lyy_stencil_23 + _2067; + int16_t _2069 = _lyy_stencil_22 + _2068; + int16_t _2070 = _lyy_stencil_21 + _2069; + int16_t _2071 = _lyy_stencil_20 + _2070; + int16_t _2072 = _lgyy_stencil_3 + _2071; + int16_t _2073 = _lyy_stencil_19 + _2072; + return _2073; +} + +//store is: lgyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 1)) = (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 1)) + (lgyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 5), ((lgyy_s1_y + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 4), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 5), ((lgyy_s1_y + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x*4) + 3), ((lgyy_s1_y + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x*4) + 5), ((lgyy_s1_y + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x*4) + 4), ((lgyy_s1_y + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_7(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_4 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_28 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_29 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_30 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_31 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_32 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_33 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_34 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_35 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_36 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _2110 = _lyy_stencil_35 + _lyy_stencil_36; + int16_t _2111 = _lyy_stencil_34 + _2110; + int16_t _2112 = _lyy_stencil_33 + _2111; + int16_t _2113 = _lyy_stencil_32 + _2112; + int16_t _2114 = _lyy_stencil_31 + _2113; + int16_t _2115 = _lyy_stencil_30 + _2114; + int16_t _2116 = _lyy_stencil_29 + _2115; + int16_t _2117 = _lgyy_stencil_4 + _2116; + int16_t _2118 = _lyy_stencil_28 + _2117; + return _2118; +} + +//store is: cim.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1)) = ((((lgxx.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64)*(lgyy.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64)) - ((lgxy.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64)*(lgxy.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64))) - ((((lgxx.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64))*((lgxx.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil((cim_s0_x_x*4), ((cim_s0_y + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_5 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_5 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_5 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _2156 = (int16_t)(6); + int16_t _2157 = _lgxx_stencil_5 >> _2156; + int16_t _2158 = _lgyy_stencil_5 >> _2156; + int16_t _2159 = _2157 * _2158; + int16_t _2160 = _lgxy_stencil_5 >> _2156; + int16_t _2161 = _2160 * _2160; + int16_t _2162 = _2159 - _2161; + int16_t _2163 = _2157 + _2158; + int16_t _2164 = _2163 * _2163; + int16_t _2165 = (int16_t)(4); + int16_t _2166 = _2164 >> _2165; + int16_t _2167 = _2162 - _2166; + return _2167; +} + +//store is: cim.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1)) = ((((lgxx.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64)*(lgyy.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64)*(lgxy.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64))*((lgxx.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 1), ((cim_s0_y + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil_1(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_6 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_6 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_6 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _2198 = (int16_t)(6); + int16_t _2199 = _lgxx_stencil_6 >> _2198; + int16_t _2200 = _lgyy_stencil_6 >> _2198; + int16_t _2201 = _2199 * _2200; + int16_t _2202 = _lgxy_stencil_6 >> _2198; + int16_t _2203 = _2202 * _2202; + int16_t _2204 = _2201 - _2203; + int16_t _2205 = _2199 + _2200; + int16_t _2206 = _2205 * _2205; + int16_t _2207 = (int16_t)(4); + int16_t _2208 = _2206 >> _2207; + int16_t _2209 = _2204 - _2208; + return _2209; +} + +//store is: cim.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1)) = ((((lgxx.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64)*(lgyy.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64)*(lgxy.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64))*((lgxx.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 2), ((cim_s0_y + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil_2(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_7 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_7 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_7 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _2241 = (int16_t)(6); + int16_t _2242 = _lgxx_stencil_7 >> _2241; + int16_t _2243 = _lgyy_stencil_7 >> _2241; + int16_t _2244 = _2242 * _2243; + int16_t _2245 = _lgxy_stencil_7 >> _2241; + int16_t _2246 = _2245 * _2245; + int16_t _2247 = _2244 - _2246; + int16_t _2248 = _2242 + _2243; + int16_t _2249 = _2248 * _2248; + int16_t _2250 = (int16_t)(4); + int16_t _2251 = _2249 >> _2250; + int16_t _2252 = _2247 - _2251; + return _2252; +} + +//store is: cim.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1)) = ((((lgxx.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64)*(lgyy.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64)*(lgxy.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64))*((lgxx.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x*4) + 3), ((cim_s0_y + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil_3(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_8 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_8 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_8 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _2284 = (int16_t)(6); + int16_t _2285 = _lgxx_stencil_8 >> _2284; + int16_t _2286 = _lgyy_stencil_8 >> _2284; + int16_t _2287 = _2285 * _2286; + int16_t _2288 = _lgxy_stencil_8 >> _2284; + int16_t _2289 = _2288 * _2288; + int16_t _2290 = _2287 - _2289; + int16_t _2291 = _2285 + _2286; + int16_t _2292 = _2291 * _2291; + int16_t _2293 = (int16_t)(4); + int16_t _2294 = _2292 >> _2293; + int16_t _2295 = _2290 - _2294; + return _2295; +} + +//store is: hw_output.glb.stencil((hw_output_s0_x_xi_xi*4), hw_output_s0_y_yi) = select((((((((((cim.stencil((hw_output_s0_x_xi_xi*4), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil((hw_output_s0_x_xi_xi*4), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil((hw_output_s0_x_xi_xi*4), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_1 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_2 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_3 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_4 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_5 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_6 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_7 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_8 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_9 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _2327 = (int16_t)(255); + int16_t _2328 = (int16_t)(0); + bool _2329 = _cim_stencil_1 < _cim_stencil_2; + bool _2330 = _cim_stencil_3 < _cim_stencil_2; + bool _2331 = _2329 && _2330; + bool _2332 = _cim_stencil_4 < _cim_stencil_2; + bool _2333 = _2331 && _2332; + bool _2334 = _cim_stencil_5 < _cim_stencil_2; + bool _2335 = _2333 && _2334; + bool _2336 = _cim_stencil_6 < _cim_stencil_2; + bool _2337 = _2335 && _2336; + bool _2338 = _cim_stencil_7 < _cim_stencil_2; + bool _2339 = _2337 && _2338; + bool _2340 = _cim_stencil_8 < _cim_stencil_2; + bool _2341 = _2339 && _2340; + bool _2342 = _cim_stencil_9 < _cim_stencil_2; + bool _2343 = _2341 && _2342; + int16_t _2344 = (int16_t)(1); + bool _2345 = _2344 <= _cim_stencil_2; + bool _2346 = _2343 && _2345; + int16_t _2347 = (int16_t)(_2346 ? _2327 : _2328); + return _2347; +} + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi*4) + 1), hw_output_s0_y_yi) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 1), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil_1(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_10 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_11 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_12 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_13 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_14 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_15 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_16 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_17 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_18 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _2404 = (int16_t)(255); + int16_t _2405 = (int16_t)(0); + bool _2406 = _cim_stencil_10 < _cim_stencil_11; + bool _2407 = _cim_stencil_12 < _cim_stencil_11; + bool _2408 = _2406 && _2407; + bool _2409 = _cim_stencil_13 < _cim_stencil_11; + bool _2410 = _2408 && _2409; + bool _2411 = _cim_stencil_14 < _cim_stencil_11; + bool _2412 = _2410 && _2411; + bool _2413 = _cim_stencil_15 < _cim_stencil_11; + bool _2414 = _2412 && _2413; + bool _2415 = _cim_stencil_16 < _cim_stencil_11; + bool _2416 = _2414 && _2415; + bool _2417 = _cim_stencil_17 < _cim_stencil_11; + bool _2418 = _2416 && _2417; + bool _2419 = _cim_stencil_18 < _cim_stencil_11; + bool _2420 = _2418 && _2419; + int16_t _2421 = (int16_t)(1); + bool _2422 = _2421 <= _cim_stencil_11; + bool _2423 = _2420 && _2422; + int16_t _2424 = (int16_t)(_2423 ? _2404 : _2405); + return _2424; +} + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 2), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil_2(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_19 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_20 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_21 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_22 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_23 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_24 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_25 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_26 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_27 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _2482 = (int16_t)(255); + int16_t _2483 = (int16_t)(0); + bool _2484 = _cim_stencil_19 < _cim_stencil_20; + bool _2485 = _cim_stencil_21 < _cim_stencil_20; + bool _2486 = _2484 && _2485; + bool _2487 = _cim_stencil_22 < _cim_stencil_20; + bool _2488 = _2486 && _2487; + bool _2489 = _cim_stencil_23 < _cim_stencil_20; + bool _2490 = _2488 && _2489; + bool _2491 = _cim_stencil_24 < _cim_stencil_20; + bool _2492 = _2490 && _2491; + bool _2493 = _cim_stencil_25 < _cim_stencil_20; + bool _2494 = _2492 && _2493; + bool _2495 = _cim_stencil_26 < _cim_stencil_20; + bool _2496 = _2494 && _2495; + bool _2497 = _cim_stencil_27 < _cim_stencil_20; + bool _2498 = _2496 && _2497; + int16_t _2499 = (int16_t)(1); + bool _2500 = _2499 <= _cim_stencil_20; + bool _2501 = _2498 && _2500; + int16_t _2502 = (int16_t)(_2501 ? _2482 : _2483); + return _2502; +} + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 5), hw_output_s0_y_yi) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 5), (hw_output_s0_y_yi + 1)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 3), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi*4) + 5), (hw_output_s0_y_yi + 2)) < cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi*4) + 4), (hw_output_s0_y_yi + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil_3(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_28 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_29 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_30 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_31 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_32 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_33 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_34 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_35 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_36 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _2560 = (int16_t)(255); + int16_t _2561 = (int16_t)(0); + bool _2562 = _cim_stencil_28 < _cim_stencil_29; + bool _2563 = _cim_stencil_30 < _cim_stencil_29; + bool _2564 = _2562 && _2563; + bool _2565 = _cim_stencil_31 < _cim_stencil_29; + bool _2566 = _2564 && _2565; + bool _2567 = _cim_stencil_32 < _cim_stencil_29; + bool _2568 = _2566 && _2567; + bool _2569 = _cim_stencil_33 < _cim_stencil_29; + bool _2570 = _2568 && _2569; + bool _2571 = _cim_stencil_34 < _cim_stencil_29; + bool _2572 = _2570 && _2571; + bool _2573 = _cim_stencil_35 < _cim_stencil_29; + bool _2574 = _2572 && _2573; + bool _2575 = _cim_stencil_36 < _cim_stencil_29; + bool _2576 = _2574 && _2575; + int16_t _2577 = (int16_t)(1); + bool _2578 = _2577 <= _cim_stencil_29; + bool _2579 = _2576 && _2578; + int16_t _2580 = (int16_t)(_2579 ? _2560 : _2561); + return _2580; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, (hw_input_global_wrapper_global_wrapper_s0_x_x_1*4), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_12(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_13 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_13; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, (hw_input_global_wrapper_global_wrapper_s0_x_x_1*4), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_13(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_14 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_14; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, (hw_input_global_wrapper_global_wrapper_s0_x_x_1*4), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_14(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_15 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_15; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_15(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_16 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_16; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_16(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_17 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_17; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 1), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_17(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_18 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_18; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 4), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_18(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_19 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_19; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 4), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_19(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_20 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_20; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 2), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 4), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_20(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_21 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_21; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 5), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_21(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_22 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_22; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 5), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_22(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_23 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_23; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 3), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, ((hw_input_global_wrapper_global_wrapper_s0_x_x_1*4) + 5), ((hw_input_global_wrapper_global_wrapper_s0_y_1 + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_23(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + int16_t _hw_input_global_wrapper_glb_stencil_24 = (int16_t) (hw_input_global_wrapper_glb_stencil.extract<0, 15>()); + + return _hw_input_global_wrapper_glb_stencil_24; +} + +//store is: gray.stencil((gray_s0_x_x_1*4), ((gray_s0_y_1 + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, (gray_s0_x_x_1*4), ((gray_s0_y_1 + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, (gray_s0_x_x_1*4), ((gray_s0_y_1 + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, (gray_s0_x_x_1*4), ((gray_s0_y_1 + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil_4(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_13 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_14 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_15 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _2709 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_13); + uint16_t _2710 = (uint16_t)(150); + uint16_t _2711 = _2709 * _2710; + uint16_t _2712 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_14); + uint16_t _2713 = (uint16_t)(29); + uint16_t _2714 = _2712 * _2713; + uint16_t _2715 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_15); + uint16_t _2716 = (uint16_t)(77); + uint16_t _2717 = _2715 * _2716; + uint16_t _2718 = _2714 + _2717; + uint16_t _2719 = _2711 + _2718; + uint16_t _2720 = (uint16_t)(8); + uint16_t _2721 = _2719 >> _2720; + return _2721; +} + +//store is: gray.stencil(((gray_s0_x_x_1*4) + 1), ((gray_s0_y_1 + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x_1*4) + 1), ((gray_s0_y_1 + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x_1*4) + 1), ((gray_s0_y_1 + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x_1*4) + 1), ((gray_s0_y_1 + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil_5(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_16 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_17 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_18 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _2754 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_16); + uint16_t _2755 = (uint16_t)(150); + uint16_t _2756 = _2754 * _2755; + uint16_t _2757 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_17); + uint16_t _2758 = (uint16_t)(29); + uint16_t _2759 = _2757 * _2758; + uint16_t _2760 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_18); + uint16_t _2761 = (uint16_t)(77); + uint16_t _2762 = _2760 * _2761; + uint16_t _2763 = _2759 + _2762; + uint16_t _2764 = _2756 + _2763; + uint16_t _2765 = (uint16_t)(8); + uint16_t _2766 = _2764 >> _2765; + return _2766; +} + +//store is: gray.stencil(((gray_s0_x_x_1*4) + 2), ((gray_s0_y_1 + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x_1*4) + 2), ((gray_s0_y_1 + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x_1*4) + 2), ((gray_s0_y_1 + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x_1*4) + 2), ((gray_s0_y_1 + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil_6(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_19 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_20 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_21 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _2800 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_19); + uint16_t _2801 = (uint16_t)(150); + uint16_t _2802 = _2800 * _2801; + uint16_t _2803 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_20); + uint16_t _2804 = (uint16_t)(29); + uint16_t _2805 = _2803 * _2804; + uint16_t _2806 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_21); + uint16_t _2807 = (uint16_t)(77); + uint16_t _2808 = _2806 * _2807; + uint16_t _2809 = _2805 + _2808; + uint16_t _2810 = _2802 + _2809; + uint16_t _2811 = (uint16_t)(8); + uint16_t _2812 = _2810 >> _2811; + return _2812; +} + +//store is: gray.stencil(((gray_s0_x_x_1*4) + 3), ((gray_s0_y_1 + -3) + 3)) = (((uint16(hw_input_global_wrapper_global_wrapper.stencil(1, ((gray_s0_x_x_1*4) + 3), ((gray_s0_y_1 + -3) + 3)))*(uint16)150) + ((uint16(hw_input_global_wrapper_global_wrapper.stencil(2, ((gray_s0_x_x_1*4) + 3), ((gray_s0_y_1 + -3) + 3)))*(uint16)29) + (uint16(hw_input_global_wrapper_global_wrapper.stencil(0, ((gray_s0_x_x_1*4) + 3), ((gray_s0_y_1 + -3) + 3)))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil_7(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + int16_t _hw_input_global_wrapper_global_wrapper_stencil_22 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_23 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_global_wrapper_stencil_24 = (int16_t) (hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>()); + + uint16_t _2846 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_22); + uint16_t _2847 = (uint16_t)(150); + uint16_t _2848 = _2846 * _2847; + uint16_t _2849 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_23); + uint16_t _2850 = (uint16_t)(29); + uint16_t _2851 = _2849 * _2850; + uint16_t _2852 = (uint16_t)(_hw_input_global_wrapper_global_wrapper_stencil_24); + uint16_t _2853 = (uint16_t)(77); + uint16_t _2854 = _2852 * _2853; + uint16_t _2855 = _2851 + _2854; + uint16_t _2856 = _2848 + _2855; + uint16_t _2857 = (uint16_t)(8); + uint16_t _2858 = _2856 >> _2857; + return _2858; +} + +//store is: grad_x_unclamp.stencil((grad_x_unclamp_s0_x_x_1*4), ((grad_x_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil_8() { + int16_t _2893 = (int16_t)(0); + return _2893; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x_1*4) + 1), ((grad_x_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil_9() { + int16_t _2899 = (int16_t)(0); + return _2899; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x_1*4) + 2), ((grad_x_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil_10() { + int16_t _2906 = (int16_t)(0); + return _2906; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s0_x_x_1*4) + 3), ((grad_x_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_x_unclamp_stencil_11() { + int16_t _2913 = (int16_t)(0); + return _2913; +} + +//store is: grad_x_unclamp.stencil((grad_x_unclamp_s1_x_x_1*4), ((grad_x_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_x_unclamp.stencil((grad_x_unclamp_s1_x_x_1*4), ((grad_x_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil((grad_x_unclamp_s1_x_x_1*4), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil((grad_x_unclamp_s1_x_x_1*4), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil((grad_x_unclamp_s1_x_x_1*4), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_12(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_13 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_49 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_50 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_51 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_52 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_53 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_54 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _2921 = (int16_t)(_gray_stencil_49); + int16_t _2922 = (int16_t)(2); + int16_t _2923 = _2921 * _2922; + int16_t _2924 = _grad_x_unclamp_stencil_13 + _2923; + int16_t _2925 = (int16_t)(_gray_stencil_50); + int16_t _2926 = _2924 - _2925; + int16_t _2927 = (int16_t)(_gray_stencil_51); + int16_t _2928 = _2926 + _2927; + int16_t _2929 = (int16_t)(_gray_stencil_52); + int16_t _2930 = _2929 * _2922; + int16_t _2931 = _2928 - _2930; + int16_t _2932 = (int16_t)(_gray_stencil_53); + int16_t _2933 = _2931 - _2932; + int16_t _2934 = (int16_t)(_gray_stencil_54); + int16_t _2935 = _2933 + _2934; + return _2935; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x_1*4) + 1), ((grad_x_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x_1*4) + 1), ((grad_x_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 1), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 1), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 1), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_13(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_14 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_55 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_56 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_57 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_58 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_59 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_60 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _2979 = (int16_t)(_gray_stencil_55); + int16_t _2980 = (int16_t)(2); + int16_t _2981 = _2979 * _2980; + int16_t _2982 = _grad_x_unclamp_stencil_14 + _2981; + int16_t _2983 = (int16_t)(_gray_stencil_56); + int16_t _2984 = _2982 - _2983; + int16_t _2985 = (int16_t)(_gray_stencil_57); + int16_t _2986 = _2984 + _2985; + int16_t _2987 = (int16_t)(_gray_stencil_58); + int16_t _2988 = _2987 * _2980; + int16_t _2989 = _2986 - _2988; + int16_t _2990 = (int16_t)(_gray_stencil_59); + int16_t _2991 = _2989 - _2990; + int16_t _2992 = (int16_t)(_gray_stencil_60); + int16_t _2993 = _2991 + _2992; + return _2993; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 4), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 4), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 2), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 4), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_14(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_15 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_61 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_62 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_63 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_64 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_65 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_66 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _3038 = (int16_t)(_gray_stencil_61); + int16_t _3039 = (int16_t)(2); + int16_t _3040 = _3038 * _3039; + int16_t _3041 = _grad_x_unclamp_stencil_15 + _3040; + int16_t _3042 = (int16_t)(_gray_stencil_62); + int16_t _3043 = _3041 - _3042; + int16_t _3044 = (int16_t)(_gray_stencil_63); + int16_t _3045 = _3043 + _3044; + int16_t _3046 = (int16_t)(_gray_stencil_64); + int16_t _3047 = _3046 * _3039; + int16_t _3048 = _3045 - _3047; + int16_t _3049 = (int16_t)(_gray_stencil_65); + int16_t _3050 = _3048 - _3049; + int16_t _3051 = (int16_t)(_gray_stencil_66); + int16_t _3052 = _3050 + _3051; + return _3052; +} + +//store is: grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_x_unclamp.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 5), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 5), ((grad_x_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 3)))*(int16)2)) - int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 3), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_x_unclamp_s1_x_x_1*4) + 5), ((grad_x_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_x_unclamp_stencil_15(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_x_unclamp_stencil_16 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_67 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_68 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_69 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_70 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_71 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_72 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _3097 = (int16_t)(_gray_stencil_67); + int16_t _3098 = (int16_t)(2); + int16_t _3099 = _3097 * _3098; + int16_t _3100 = _grad_x_unclamp_stencil_16 + _3099; + int16_t _3101 = (int16_t)(_gray_stencil_68); + int16_t _3102 = _3100 - _3101; + int16_t _3103 = (int16_t)(_gray_stencil_69); + int16_t _3104 = _3102 + _3103; + int16_t _3105 = (int16_t)(_gray_stencil_70); + int16_t _3106 = _3105 * _3098; + int16_t _3107 = _3104 - _3106; + int16_t _3108 = (int16_t)(_gray_stencil_71); + int16_t _3109 = _3107 - _3108; + int16_t _3110 = (int16_t)(_gray_stencil_72); + int16_t _3111 = _3109 + _3110; + return _3111; +} + +//store is: lxx.stencil((lxx_s0_x_x_1*4), ((lxx_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil((lxx_s0_x_x_1*4), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil((lxx_s0_x_x_1*4), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil_4(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_17 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _3157 = (int16_t)(180); + int16_t _3158 = min(_grad_x_unclamp_stencil_17, _3157); + int16_t _3159 = (int16_t)(-180); + int16_t _3160 = max(_3158, _3159); + int16_t _3161 = _3160 * _3160; + int16_t _3162 = (int16_t)(6); + int16_t _3163 = _3161 >> _3162; + return _3163; +} + +//store is: lxx.stencil(((lxx_s0_x_x_1*4) + 1), ((lxx_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x_1*4) + 1), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x_1*4) + 1), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil_5(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_18 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _3182 = (int16_t)(180); + int16_t _3183 = min(_grad_x_unclamp_stencil_18, _3182); + int16_t _3184 = (int16_t)(-180); + int16_t _3185 = max(_3183, _3184); + int16_t _3186 = _3185 * _3185; + int16_t _3187 = (int16_t)(6); + int16_t _3188 = _3186 >> _3187; + return _3188; +} + +//store is: lxx.stencil(((lxx_s0_x_x_1*4) + 2), ((lxx_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x_1*4) + 2), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x_1*4) + 2), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil_6(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_19 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _3208 = (int16_t)(180); + int16_t _3209 = min(_grad_x_unclamp_stencil_19, _3208); + int16_t _3210 = (int16_t)(-180); + int16_t _3211 = max(_3209, _3210); + int16_t _3212 = _3211 * _3211; + int16_t _3213 = (int16_t)(6); + int16_t _3214 = _3212 >> _3213; + return _3214; +} + +//store is: lxx.stencil(((lxx_s0_x_x_1*4) + 3), ((lxx_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxx_s0_x_x_1*4) + 3), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_x_unclamp.stencil(((lxx_s0_x_x_1*4) + 3), ((lxx_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxx_stencil_7(hw_uint<16>& grad_x_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_20 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _3234 = (int16_t)(180); + int16_t _3235 = min(_grad_x_unclamp_stencil_20, _3234); + int16_t _3236 = (int16_t)(-180); + int16_t _3237 = max(_3235, _3236); + int16_t _3238 = _3237 * _3237; + int16_t _3239 = (int16_t)(6); + int16_t _3240 = _3238 >> _3239; + return _3240; +} + +//store is: lgxx.stencil((lgxx_s0_x_x_1*4), ((lgxx_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil_8() { + int16_t _3261 = (int16_t)(0); + return _3261; +} + +//store is: lgxx.stencil(((lgxx_s0_x_x_1*4) + 1), ((lgxx_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil_9() { + int16_t _3267 = (int16_t)(0); + return _3267; +} + +//store is: lgxx.stencil(((lgxx_s0_x_x_1*4) + 2), ((lgxx_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil_10() { + int16_t _3274 = (int16_t)(0); + return _3274; +} + +//store is: lgxx.stencil(((lgxx_s0_x_x_1*4) + 3), ((lgxx_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxx_stencil_11() { + int16_t _3281 = (int16_t)(0); + return _3281; +} + +//store is: lgxx.stencil((lgxx_s1_x_x_1*4), ((lgxx_s1_y_1 + -1) + 1)) = (lxx.stencil((lgxx_s1_x_x_1*4), ((lgxx_s1_y_1 + -1) + 1)) + (lgxx.stencil((lgxx_s1_x_x_1*4), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil((lgxx_s1_x_x_1*4), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil((lgxx_s1_x_x_1*4), ((lgxx_s1_y_1 + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_12(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_9 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_37 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_38 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_39 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_40 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_41 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_42 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_43 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_44 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_45 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _3289 = _lxx_stencil_44 + _lxx_stencil_45; + int16_t _3290 = _lxx_stencil_43 + _3289; + int16_t _3291 = _lxx_stencil_42 + _3290; + int16_t _3292 = _lxx_stencil_41 + _3291; + int16_t _3293 = _lxx_stencil_40 + _3292; + int16_t _3294 = _lxx_stencil_39 + _3293; + int16_t _3295 = _lxx_stencil_38 + _3294; + int16_t _3296 = _lgxx_stencil_9 + _3295; + int16_t _3297 = _lxx_stencil_37 + _3296; + return _3297; +} + +//store is: lgxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 1)) = (lxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 1)) + (lgxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 1), ((lgxx_s1_y_1 + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_13(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_10 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_46 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_47 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_48 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_49 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_50 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_51 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_52 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_53 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_54 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _3333 = _lxx_stencil_53 + _lxx_stencil_54; + int16_t _3334 = _lxx_stencil_52 + _3333; + int16_t _3335 = _lxx_stencil_51 + _3334; + int16_t _3336 = _lxx_stencil_50 + _3335; + int16_t _3337 = _lxx_stencil_49 + _3336; + int16_t _3338 = _lxx_stencil_48 + _3337; + int16_t _3339 = _lxx_stencil_47 + _3338; + int16_t _3340 = _lgxx_stencil_10 + _3339; + int16_t _3341 = _lxx_stencil_46 + _3340; + return _3341; +} + +//store is: lgxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 1)) = (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 1)) + (lgxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 4), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 4), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 2), ((lgxx_s1_y_1 + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 4), ((lgxx_s1_y_1 + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_14(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_11 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_55 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_56 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_57 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_58 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_59 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_60 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_61 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_62 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_63 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _3378 = _lxx_stencil_62 + _lxx_stencil_63; + int16_t _3379 = _lxx_stencil_61 + _3378; + int16_t _3380 = _lxx_stencil_60 + _3379; + int16_t _3381 = _lxx_stencil_59 + _3380; + int16_t _3382 = _lxx_stencil_58 + _3381; + int16_t _3383 = _lxx_stencil_57 + _3382; + int16_t _3384 = _lxx_stencil_56 + _3383; + int16_t _3385 = _lgxx_stencil_11 + _3384; + int16_t _3386 = _lxx_stencil_55 + _3385; + return _3386; +} + +//store is: lgxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 1)) = (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 1)) + (lgxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 4), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 5), ((lgxx_s1_y_1 + -1) + 1)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 4), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 5), ((lgxx_s1_y_1 + -1) + 2)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 3), ((lgxx_s1_y_1 + -1) + 3)) + (lxx.stencil(((lgxx_s1_x_x_1*4) + 5), ((lgxx_s1_y_1 + -1) + 3)) + lxx.stencil(((lgxx_s1_x_x_1*4) + 4), ((lgxx_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxx_stencil_15(hw_uint<16>& lgxx_stencil, hw_uint<144>& lxx_stencil) { + int16_t _lgxx_stencil_12 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lxx_stencil_64 = (int16_t) (lxx_stencil.extract<0, 15>()); + int16_t _lxx_stencil_65 = (int16_t) (lxx_stencil.extract<16, 31>()); + int16_t _lxx_stencil_66 = (int16_t) (lxx_stencil.extract<32, 47>()); + int16_t _lxx_stencil_67 = (int16_t) (lxx_stencil.extract<48, 63>()); + int16_t _lxx_stencil_68 = (int16_t) (lxx_stencil.extract<64, 79>()); + int16_t _lxx_stencil_69 = (int16_t) (lxx_stencil.extract<80, 95>()); + int16_t _lxx_stencil_70 = (int16_t) (lxx_stencil.extract<96, 111>()); + int16_t _lxx_stencil_71 = (int16_t) (lxx_stencil.extract<112, 127>()); + int16_t _lxx_stencil_72 = (int16_t) (lxx_stencil.extract<128, 143>()); + + int16_t _3423 = _lxx_stencil_71 + _lxx_stencil_72; + int16_t _3424 = _lxx_stencil_70 + _3423; + int16_t _3425 = _lxx_stencil_69 + _3424; + int16_t _3426 = _lxx_stencil_68 + _3425; + int16_t _3427 = _lxx_stencil_67 + _3426; + int16_t _3428 = _lxx_stencil_66 + _3427; + int16_t _3429 = _lxx_stencil_65 + _3428; + int16_t _3430 = _lgxx_stencil_12 + _3429; + int16_t _3431 = _lxx_stencil_64 + _3430; + return _3431; +} + +//store is: grad_y_unclamp.stencil((grad_y_unclamp_s0_x_x_1*4), ((grad_y_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil_8() { + int16_t _3469 = (int16_t)(0); + return _3469; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x_1*4) + 1), ((grad_y_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil_9() { + int16_t _3475 = (int16_t)(0); + return _3475; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x_1*4) + 2), ((grad_y_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil_10() { + int16_t _3482 = (int16_t)(0); + return _3482; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s0_x_x_1*4) + 3), ((grad_y_unclamp_s0_y_1 + -2) + 2)) = (int16)0 +hw_uint<16> hcompute_grad_y_unclamp_stencil_11() { + int16_t _3489 = (int16_t)(0); + return _3489; +} + +//store is: grad_y_unclamp.stencil((grad_y_unclamp_s1_x_x_1*4), ((grad_y_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_y_unclamp.stencil((grad_y_unclamp_s1_x_x_1*4), ((grad_y_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 1), ((grad_y_unclamp_s1_y_1 + -2) + 4)))*(int16)2)) - int16(gray.stencil((grad_y_unclamp_s1_x_x_1*4), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 1), ((grad_y_unclamp_s1_y_1 + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil((grad_y_unclamp_s1_x_x_1*4), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_12(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_13 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_73 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_74 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_75 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_76 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_77 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_78 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _3497 = (int16_t)(_gray_stencil_73); + int16_t _3498 = (int16_t)(2); + int16_t _3499 = _3497 * _3498; + int16_t _3500 = _grad_y_unclamp_stencil_13 + _3499; + int16_t _3501 = (int16_t)(_gray_stencil_74); + int16_t _3502 = _3500 - _3501; + int16_t _3503 = (int16_t)(_gray_stencil_75); + int16_t _3504 = _3503 * _3498; + int16_t _3505 = _3502 - _3504; + int16_t _3506 = (int16_t)(_gray_stencil_76); + int16_t _3507 = _3505 - _3506; + int16_t _3508 = (int16_t)(_gray_stencil_77); + int16_t _3509 = _3507 + _3508; + int16_t _3510 = (int16_t)(_gray_stencil_78); + int16_t _3511 = _3509 + _3510; + return _3511; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x_1*4) + 1), ((grad_y_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x_1*4) + 1), ((grad_y_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 4)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 1), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 1), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_13(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_14 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_79 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_80 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_81 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_82 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_83 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_84 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _3555 = (int16_t)(_gray_stencil_79); + int16_t _3556 = (int16_t)(2); + int16_t _3557 = _3555 * _3556; + int16_t _3558 = _grad_y_unclamp_stencil_14 + _3557; + int16_t _3559 = (int16_t)(_gray_stencil_80); + int16_t _3560 = _3558 - _3559; + int16_t _3561 = (int16_t)(_gray_stencil_81); + int16_t _3562 = _3561 * _3556; + int16_t _3563 = _3560 - _3562; + int16_t _3564 = (int16_t)(_gray_stencil_82); + int16_t _3565 = _3563 - _3564; + int16_t _3566 = (int16_t)(_gray_stencil_83); + int16_t _3567 = _3565 + _3566; + int16_t _3568 = (int16_t)(_gray_stencil_84); + int16_t _3569 = _3567 + _3568; + return _3569; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 4)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 4), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 2), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 4), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_14(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_15 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_85 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_86 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_87 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_88 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_89 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_90 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _3614 = (int16_t)(_gray_stencil_85); + int16_t _3615 = (int16_t)(2); + int16_t _3616 = _3614 * _3615; + int16_t _3617 = _grad_y_unclamp_stencil_15 + _3616; + int16_t _3618 = (int16_t)(_gray_stencil_86); + int16_t _3619 = _3617 - _3618; + int16_t _3620 = (int16_t)(_gray_stencil_87); + int16_t _3621 = _3620 * _3615; + int16_t _3622 = _3619 - _3621; + int16_t _3623 = (int16_t)(_gray_stencil_88); + int16_t _3624 = _3622 - _3623; + int16_t _3625 = (int16_t)(_gray_stencil_89); + int16_t _3626 = _3624 + _3625; + int16_t _3627 = (int16_t)(_gray_stencil_90); + int16_t _3628 = _3626 + _3627; + return _3628; +} + +//store is: grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 2)) = ((((((grad_y_unclamp.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 2)) + (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 4), ((grad_y_unclamp_s1_y_1 + -2) + 4)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) - (int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 4), ((grad_y_unclamp_s1_y_1 + -2) + 2)))*(int16)2)) - int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 5), ((grad_y_unclamp_s1_y_1 + -2) + 2)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 3), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) + int16(gray.stencil(((grad_y_unclamp_s1_x_x_1*4) + 5), ((grad_y_unclamp_s1_y_1 + -2) + 4)))) +hw_uint<16> hcompute_grad_y_unclamp_stencil_15(hw_uint<16>& grad_y_unclamp_stencil, hw_uint<96>& gray_stencil) { + int16_t _grad_y_unclamp_stencil_16 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + uint16_t _gray_stencil_91 = (uint16_t) (gray_stencil.extract<0, 15>()); + uint16_t _gray_stencil_92 = (uint16_t) (gray_stencil.extract<16, 31>()); + uint16_t _gray_stencil_93 = (uint16_t) (gray_stencil.extract<32, 47>()); + uint16_t _gray_stencil_94 = (uint16_t) (gray_stencil.extract<48, 63>()); + uint16_t _gray_stencil_95 = (uint16_t) (gray_stencil.extract<64, 79>()); + uint16_t _gray_stencil_96 = (uint16_t) (gray_stencil.extract<80, 95>()); + + int16_t _3673 = (int16_t)(_gray_stencil_91); + int16_t _3674 = (int16_t)(2); + int16_t _3675 = _3673 * _3674; + int16_t _3676 = _grad_y_unclamp_stencil_16 + _3675; + int16_t _3677 = (int16_t)(_gray_stencil_92); + int16_t _3678 = _3676 - _3677; + int16_t _3679 = (int16_t)(_gray_stencil_93); + int16_t _3680 = _3679 * _3674; + int16_t _3681 = _3678 - _3680; + int16_t _3682 = (int16_t)(_gray_stencil_94); + int16_t _3683 = _3681 - _3682; + int16_t _3684 = (int16_t)(_gray_stencil_95); + int16_t _3685 = _3683 + _3684; + int16_t _3686 = (int16_t)(_gray_stencil_96); + int16_t _3687 = _3685 + _3686; + return _3687; +} + +//store is: lxy.stencil((lxy_s0_x_x_1*4), ((lxy_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil((lxy_s0_x_x_1*4), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil((lxy_s0_x_x_1*4), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil_4(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_21 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_17 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _3733 = (int16_t)(180); + int16_t _3734 = min(_grad_x_unclamp_stencil_21, _3733); + int16_t _3735 = (int16_t)(-180); + int16_t _3736 = max(_3734, _3735); + int16_t _3737 = min(_grad_y_unclamp_stencil_17, _3733); + int16_t _3738 = max(_3737, _3735); + int16_t _3739 = _3736 * _3738; + int16_t _3740 = (int16_t)(6); + int16_t _3741 = _3739 >> _3740; + return _3741; +} + +//store is: lxy.stencil(((lxy_s0_x_x_1*4) + 1), ((lxy_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x_1*4) + 1), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x_1*4) + 1), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil_5(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_22 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_18 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _3765 = (int16_t)(180); + int16_t _3766 = min(_grad_x_unclamp_stencil_22, _3765); + int16_t _3767 = (int16_t)(-180); + int16_t _3768 = max(_3766, _3767); + int16_t _3769 = min(_grad_y_unclamp_stencil_18, _3765); + int16_t _3770 = max(_3769, _3767); + int16_t _3771 = _3768 * _3770; + int16_t _3772 = (int16_t)(6); + int16_t _3773 = _3771 >> _3772; + return _3773; +} + +//store is: lxy.stencil(((lxy_s0_x_x_1*4) + 2), ((lxy_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x_1*4) + 2), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x_1*4) + 2), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil_6(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_23 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_19 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _3798 = (int16_t)(180); + int16_t _3799 = min(_grad_x_unclamp_stencil_23, _3798); + int16_t _3800 = (int16_t)(-180); + int16_t _3801 = max(_3799, _3800); + int16_t _3802 = min(_grad_y_unclamp_stencil_19, _3798); + int16_t _3803 = max(_3802, _3800); + int16_t _3804 = _3801 * _3803; + int16_t _3805 = (int16_t)(6); + int16_t _3806 = _3804 >> _3805; + return _3806; +} + +//store is: lxy.stencil(((lxy_s0_x_x_1*4) + 3), ((lxy_s0_y_1 + -2) + 2)) = ((max(min(grad_x_unclamp.stencil(((lxy_s0_x_x_1*4) + 3), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lxy_s0_x_x_1*4) + 3), ((lxy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lxy_stencil_7(hw_uint<16>& grad_x_unclamp_stencil, hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_x_unclamp_stencil_24 = (int16_t) (grad_x_unclamp_stencil.extract<0, 15>()); + + int16_t _grad_y_unclamp_stencil_20 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _3831 = (int16_t)(180); + int16_t _3832 = min(_grad_x_unclamp_stencil_24, _3831); + int16_t _3833 = (int16_t)(-180); + int16_t _3834 = max(_3832, _3833); + int16_t _3835 = min(_grad_y_unclamp_stencil_20, _3831); + int16_t _3836 = max(_3835, _3833); + int16_t _3837 = _3834 * _3836; + int16_t _3838 = (int16_t)(6); + int16_t _3839 = _3837 >> _3838; + return _3839; +} + +//store is: lgxy.stencil((lgxy_s0_x_x_1*4), ((lgxy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil_8() { + int16_t _3865 = (int16_t)(0); + return _3865; +} + +//store is: lgxy.stencil(((lgxy_s0_x_x_1*4) + 1), ((lgxy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil_9() { + int16_t _3871 = (int16_t)(0); + return _3871; +} + +//store is: lgxy.stencil(((lgxy_s0_x_x_1*4) + 2), ((lgxy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil_10() { + int16_t _3878 = (int16_t)(0); + return _3878; +} + +//store is: lgxy.stencil(((lgxy_s0_x_x_1*4) + 3), ((lgxy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgxy_stencil_11() { + int16_t _3885 = (int16_t)(0); + return _3885; +} + +//store is: lgxy.stencil((lgxy_s1_x_x_1*4), ((lgxy_s1_y_1 + -1) + 1)) = (lxy.stencil((lgxy_s1_x_x_1*4), ((lgxy_s1_y_1 + -1) + 1)) + (lgxy.stencil((lgxy_s1_x_x_1*4), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil((lgxy_s1_x_x_1*4), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil((lgxy_s1_x_x_1*4), ((lgxy_s1_y_1 + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_12(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_9 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_37 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_38 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_39 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_40 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_41 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_42 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_43 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_44 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_45 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _3893 = _lxy_stencil_44 + _lxy_stencil_45; + int16_t _3894 = _lxy_stencil_43 + _3893; + int16_t _3895 = _lxy_stencil_42 + _3894; + int16_t _3896 = _lxy_stencil_41 + _3895; + int16_t _3897 = _lxy_stencil_40 + _3896; + int16_t _3898 = _lxy_stencil_39 + _3897; + int16_t _3899 = _lxy_stencil_38 + _3898; + int16_t _3900 = _lgxy_stencil_9 + _3899; + int16_t _3901 = _lxy_stencil_37 + _3900; + return _3901; +} + +//store is: lgxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 1)) = (lxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 1)) + (lgxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 1), ((lgxy_s1_y_1 + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_13(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_10 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_46 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_47 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_48 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_49 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_50 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_51 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_52 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_53 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_54 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _3937 = _lxy_stencil_53 + _lxy_stencil_54; + int16_t _3938 = _lxy_stencil_52 + _3937; + int16_t _3939 = _lxy_stencil_51 + _3938; + int16_t _3940 = _lxy_stencil_50 + _3939; + int16_t _3941 = _lxy_stencil_49 + _3940; + int16_t _3942 = _lxy_stencil_48 + _3941; + int16_t _3943 = _lxy_stencil_47 + _3942; + int16_t _3944 = _lgxy_stencil_10 + _3943; + int16_t _3945 = _lxy_stencil_46 + _3944; + return _3945; +} + +//store is: lgxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 1)) = (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 1)) + (lgxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 4), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 4), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 2), ((lgxy_s1_y_1 + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 4), ((lgxy_s1_y_1 + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_14(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_11 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_55 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_56 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_57 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_58 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_59 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_60 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_61 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_62 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_63 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _3982 = _lxy_stencil_62 + _lxy_stencil_63; + int16_t _3983 = _lxy_stencil_61 + _3982; + int16_t _3984 = _lxy_stencil_60 + _3983; + int16_t _3985 = _lxy_stencil_59 + _3984; + int16_t _3986 = _lxy_stencil_58 + _3985; + int16_t _3987 = _lxy_stencil_57 + _3986; + int16_t _3988 = _lxy_stencil_56 + _3987; + int16_t _3989 = _lgxy_stencil_11 + _3988; + int16_t _3990 = _lxy_stencil_55 + _3989; + return _3990; +} + +//store is: lgxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 1)) = (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 1)) + (lgxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 4), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 5), ((lgxy_s1_y_1 + -1) + 1)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 4), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 5), ((lgxy_s1_y_1 + -1) + 2)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 3), ((lgxy_s1_y_1 + -1) + 3)) + (lxy.stencil(((lgxy_s1_x_x_1*4) + 5), ((lgxy_s1_y_1 + -1) + 3)) + lxy.stencil(((lgxy_s1_x_x_1*4) + 4), ((lgxy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgxy_stencil_15(hw_uint<16>& lgxy_stencil, hw_uint<144>& lxy_stencil) { + int16_t _lgxy_stencil_12 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lxy_stencil_64 = (int16_t) (lxy_stencil.extract<0, 15>()); + int16_t _lxy_stencil_65 = (int16_t) (lxy_stencil.extract<16, 31>()); + int16_t _lxy_stencil_66 = (int16_t) (lxy_stencil.extract<32, 47>()); + int16_t _lxy_stencil_67 = (int16_t) (lxy_stencil.extract<48, 63>()); + int16_t _lxy_stencil_68 = (int16_t) (lxy_stencil.extract<64, 79>()); + int16_t _lxy_stencil_69 = (int16_t) (lxy_stencil.extract<80, 95>()); + int16_t _lxy_stencil_70 = (int16_t) (lxy_stencil.extract<96, 111>()); + int16_t _lxy_stencil_71 = (int16_t) (lxy_stencil.extract<112, 127>()); + int16_t _lxy_stencil_72 = (int16_t) (lxy_stencil.extract<128, 143>()); + + int16_t _4027 = _lxy_stencil_71 + _lxy_stencil_72; + int16_t _4028 = _lxy_stencil_70 + _4027; + int16_t _4029 = _lxy_stencil_69 + _4028; + int16_t _4030 = _lxy_stencil_68 + _4029; + int16_t _4031 = _lxy_stencil_67 + _4030; + int16_t _4032 = _lxy_stencil_66 + _4031; + int16_t _4033 = _lxy_stencil_65 + _4032; + int16_t _4034 = _lgxy_stencil_12 + _4033; + int16_t _4035 = _lxy_stencil_64 + _4034; + return _4035; +} + +//store is: lyy.stencil((lyy_s0_x_x_1*4), ((lyy_s0_y_1 + -2) + 2)) = ((max(min(grad_y_unclamp.stencil((lyy_s0_x_x_1*4), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil((lyy_s0_x_x_1*4), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil_4(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_21 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _4073 = (int16_t)(180); + int16_t _4074 = min(_grad_y_unclamp_stencil_21, _4073); + int16_t _4075 = (int16_t)(-180); + int16_t _4076 = max(_4074, _4075); + int16_t _4077 = _4076 * _4076; + int16_t _4078 = (int16_t)(6); + int16_t _4079 = _4077 >> _4078; + return _4079; +} + +//store is: lyy.stencil(((lyy_s0_x_x_1*4) + 1), ((lyy_s0_y_1 + -2) + 2)) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x_1*4) + 1), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x_1*4) + 1), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil_5(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_22 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _4098 = (int16_t)(180); + int16_t _4099 = min(_grad_y_unclamp_stencil_22, _4098); + int16_t _4100 = (int16_t)(-180); + int16_t _4101 = max(_4099, _4100); + int16_t _4102 = _4101 * _4101; + int16_t _4103 = (int16_t)(6); + int16_t _4104 = _4102 >> _4103; + return _4104; +} + +//store is: lyy.stencil(((lyy_s0_x_x_1*4) + 2), ((lyy_s0_y_1 + -2) + 2)) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x_1*4) + 2), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x_1*4) + 2), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil_6(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_23 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _4124 = (int16_t)(180); + int16_t _4125 = min(_grad_y_unclamp_stencil_23, _4124); + int16_t _4126 = (int16_t)(-180); + int16_t _4127 = max(_4125, _4126); + int16_t _4128 = _4127 * _4127; + int16_t _4129 = (int16_t)(6); + int16_t _4130 = _4128 >> _4129; + return _4130; +} + +//store is: lyy.stencil(((lyy_s0_x_x_1*4) + 3), ((lyy_s0_y_1 + -2) + 2)) = ((max(min(grad_y_unclamp.stencil(((lyy_s0_x_x_1*4) + 3), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180)*max(min(grad_y_unclamp.stencil(((lyy_s0_x_x_1*4) + 3), ((lyy_s0_y_1 + -2) + 2)), (int16)180), (int16)-180))/(int16)64) +hw_uint<16> hcompute_lyy_stencil_7(hw_uint<16>& grad_y_unclamp_stencil) { + int16_t _grad_y_unclamp_stencil_24 = (int16_t) (grad_y_unclamp_stencil.extract<0, 15>()); + + int16_t _4150 = (int16_t)(180); + int16_t _4151 = min(_grad_y_unclamp_stencil_24, _4150); + int16_t _4152 = (int16_t)(-180); + int16_t _4153 = max(_4151, _4152); + int16_t _4154 = _4153 * _4153; + int16_t _4155 = (int16_t)(6); + int16_t _4156 = _4154 >> _4155; + return _4156; +} + +//store is: lgyy.stencil((lgyy_s0_x_x_1*4), ((lgyy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil_8() { + int16_t _4177 = (int16_t)(0); + return _4177; +} + +//store is: lgyy.stencil(((lgyy_s0_x_x_1*4) + 1), ((lgyy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil_9() { + int16_t _4183 = (int16_t)(0); + return _4183; +} + +//store is: lgyy.stencil(((lgyy_s0_x_x_1*4) + 2), ((lgyy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil_10() { + int16_t _4190 = (int16_t)(0); + return _4190; +} + +//store is: lgyy.stencil(((lgyy_s0_x_x_1*4) + 3), ((lgyy_s0_y_1 + -1) + 1)) = (int16)0 +hw_uint<16> hcompute_lgyy_stencil_11() { + int16_t _4197 = (int16_t)(0); + return _4197; +} + +//store is: lgyy.stencil((lgyy_s1_x_x_1*4), ((lgyy_s1_y_1 + -1) + 1)) = (lyy.stencil((lgyy_s1_x_x_1*4), ((lgyy_s1_y_1 + -1) + 1)) + (lgyy.stencil((lgyy_s1_x_x_1*4), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil((lgyy_s1_x_x_1*4), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil((lgyy_s1_x_x_1*4), ((lgyy_s1_y_1 + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_12(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_9 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_37 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_38 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_39 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_40 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_41 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_42 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_43 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_44 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_45 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _4205 = _lyy_stencil_44 + _lyy_stencil_45; + int16_t _4206 = _lyy_stencil_43 + _4205; + int16_t _4207 = _lyy_stencil_42 + _4206; + int16_t _4208 = _lyy_stencil_41 + _4207; + int16_t _4209 = _lyy_stencil_40 + _4208; + int16_t _4210 = _lyy_stencil_39 + _4209; + int16_t _4211 = _lyy_stencil_38 + _4210; + int16_t _4212 = _lgyy_stencil_9 + _4211; + int16_t _4213 = _lyy_stencil_37 + _4212; + return _4213; +} + +//store is: lgyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 1)) = (lyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 1)) + (lgyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 1), ((lgyy_s1_y_1 + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_13(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_10 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_46 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_47 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_48 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_49 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_50 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_51 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_52 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_53 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_54 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _4249 = _lyy_stencil_53 + _lyy_stencil_54; + int16_t _4250 = _lyy_stencil_52 + _4249; + int16_t _4251 = _lyy_stencil_51 + _4250; + int16_t _4252 = _lyy_stencil_50 + _4251; + int16_t _4253 = _lyy_stencil_49 + _4252; + int16_t _4254 = _lyy_stencil_48 + _4253; + int16_t _4255 = _lyy_stencil_47 + _4254; + int16_t _4256 = _lgyy_stencil_10 + _4255; + int16_t _4257 = _lyy_stencil_46 + _4256; + return _4257; +} + +//store is: lgyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 1)) = (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 1)) + (lgyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 4), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 4), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 2), ((lgyy_s1_y_1 + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 4), ((lgyy_s1_y_1 + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_14(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_11 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_55 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_56 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_57 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_58 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_59 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_60 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_61 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_62 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_63 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _4294 = _lyy_stencil_62 + _lyy_stencil_63; + int16_t _4295 = _lyy_stencil_61 + _4294; + int16_t _4296 = _lyy_stencil_60 + _4295; + int16_t _4297 = _lyy_stencil_59 + _4296; + int16_t _4298 = _lyy_stencil_58 + _4297; + int16_t _4299 = _lyy_stencil_57 + _4298; + int16_t _4300 = _lyy_stencil_56 + _4299; + int16_t _4301 = _lgyy_stencil_11 + _4300; + int16_t _4302 = _lyy_stencil_55 + _4301; + return _4302; +} + +//store is: lgyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 1)) = (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 1)) + (lgyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 4), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 5), ((lgyy_s1_y_1 + -1) + 1)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 4), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 5), ((lgyy_s1_y_1 + -1) + 2)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 3), ((lgyy_s1_y_1 + -1) + 3)) + (lyy.stencil(((lgyy_s1_x_x_1*4) + 5), ((lgyy_s1_y_1 + -1) + 3)) + lyy.stencil(((lgyy_s1_x_x_1*4) + 4), ((lgyy_s1_y_1 + -1) + 3))))))))))) +hw_uint<16> hcompute_lgyy_stencil_15(hw_uint<16>& lgyy_stencil, hw_uint<144>& lyy_stencil) { + int16_t _lgyy_stencil_12 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _lyy_stencil_64 = (int16_t) (lyy_stencil.extract<0, 15>()); + int16_t _lyy_stencil_65 = (int16_t) (lyy_stencil.extract<16, 31>()); + int16_t _lyy_stencil_66 = (int16_t) (lyy_stencil.extract<32, 47>()); + int16_t _lyy_stencil_67 = (int16_t) (lyy_stencil.extract<48, 63>()); + int16_t _lyy_stencil_68 = (int16_t) (lyy_stencil.extract<64, 79>()); + int16_t _lyy_stencil_69 = (int16_t) (lyy_stencil.extract<80, 95>()); + int16_t _lyy_stencil_70 = (int16_t) (lyy_stencil.extract<96, 111>()); + int16_t _lyy_stencil_71 = (int16_t) (lyy_stencil.extract<112, 127>()); + int16_t _lyy_stencil_72 = (int16_t) (lyy_stencil.extract<128, 143>()); + + int16_t _4339 = _lyy_stencil_71 + _lyy_stencil_72; + int16_t _4340 = _lyy_stencil_70 + _4339; + int16_t _4341 = _lyy_stencil_69 + _4340; + int16_t _4342 = _lyy_stencil_68 + _4341; + int16_t _4343 = _lyy_stencil_67 + _4342; + int16_t _4344 = _lyy_stencil_66 + _4343; + int16_t _4345 = _lyy_stencil_65 + _4344; + int16_t _4346 = _lgyy_stencil_12 + _4345; + int16_t _4347 = _lyy_stencil_64 + _4346; + return _4347; +} + +//store is: cim.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1)) = ((((lgxx.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgyy.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64)) - ((lgxy.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgxy.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64))) - ((((lgxx.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64))*((lgxx.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil((cim_s0_x_x_1*4), ((cim_s0_y_1 + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil_4(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_13 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_13 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_13 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _4385 = (int16_t)(6); + int16_t _4386 = _lgxx_stencil_13 >> _4385; + int16_t _4387 = _lgyy_stencil_13 >> _4385; + int16_t _4388 = _4386 * _4387; + int16_t _4389 = _lgxy_stencil_13 >> _4385; + int16_t _4390 = _4389 * _4389; + int16_t _4391 = _4388 - _4390; + int16_t _4392 = _4386 + _4387; + int16_t _4393 = _4392 * _4392; + int16_t _4394 = (int16_t)(4); + int16_t _4395 = _4393 >> _4394; + int16_t _4396 = _4391 - _4395; + return _4396; +} + +//store is: cim.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1)) = ((((lgxx.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgyy.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgxy.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64))*((lgxx.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x_1*4) + 1), ((cim_s0_y_1 + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil_5(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_14 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_14 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_14 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _4427 = (int16_t)(6); + int16_t _4428 = _lgxx_stencil_14 >> _4427; + int16_t _4429 = _lgyy_stencil_14 >> _4427; + int16_t _4430 = _4428 * _4429; + int16_t _4431 = _lgxy_stencil_14 >> _4427; + int16_t _4432 = _4431 * _4431; + int16_t _4433 = _4430 - _4432; + int16_t _4434 = _4428 + _4429; + int16_t _4435 = _4434 * _4434; + int16_t _4436 = (int16_t)(4); + int16_t _4437 = _4435 >> _4436; + int16_t _4438 = _4433 - _4437; + return _4438; +} + +//store is: cim.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1)) = ((((lgxx.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgyy.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgxy.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64))*((lgxx.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x_1*4) + 2), ((cim_s0_y_1 + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil_6(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_15 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_15 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_15 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _4470 = (int16_t)(6); + int16_t _4471 = _lgxx_stencil_15 >> _4470; + int16_t _4472 = _lgyy_stencil_15 >> _4470; + int16_t _4473 = _4471 * _4472; + int16_t _4474 = _lgxy_stencil_15 >> _4470; + int16_t _4475 = _4474 * _4474; + int16_t _4476 = _4473 - _4475; + int16_t _4477 = _4471 + _4472; + int16_t _4478 = _4477 * _4477; + int16_t _4479 = (int16_t)(4); + int16_t _4480 = _4478 >> _4479; + int16_t _4481 = _4476 - _4480; + return _4481; +} + +//store is: cim.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1)) = ((((lgxx.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgyy.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64)) - ((lgxy.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64)*(lgxy.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64))) - ((((lgxx.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64))*((lgxx.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64) + (lgyy.stencil(((cim_s0_x_x_1*4) + 3), ((cim_s0_y_1 + -1) + 1))/(int16)64)))/(int16)16)) +hw_uint<16> hcompute_cim_stencil_7(hw_uint<16>& lgxx_stencil, hw_uint<16>& lgxy_stencil, hw_uint<16>& lgyy_stencil) { + int16_t _lgxx_stencil_16 = (int16_t) (lgxx_stencil.extract<0, 15>()); + + int16_t _lgxy_stencil_16 = (int16_t) (lgxy_stencil.extract<0, 15>()); + + int16_t _lgyy_stencil_16 = (int16_t) (lgyy_stencil.extract<0, 15>()); + + int16_t _4513 = (int16_t)(6); + int16_t _4514 = _lgxx_stencil_16 >> _4513; + int16_t _4515 = _lgyy_stencil_16 >> _4513; + int16_t _4516 = _4514 * _4515; + int16_t _4517 = _lgxy_stencil_16 >> _4513; + int16_t _4518 = _4517 * _4517; + int16_t _4519 = _4516 - _4518; + int16_t _4520 = _4514 + _4515; + int16_t _4521 = _4520 * _4520; + int16_t _4522 = (int16_t)(4); + int16_t _4523 = _4521 >> _4522; + int16_t _4524 = _4519 - _4523; + return _4524; +} + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), hw_output_s0_y_yi_1) = select((((((((((cim.stencil((hw_output_s0_x_xi_xi_1*4), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil((hw_output_s0_x_xi_xi_1*4), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil((hw_output_s0_x_xi_xi_1*4), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil_4(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_37 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_38 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_39 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_40 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_41 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_42 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_43 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_44 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_45 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _4556 = (int16_t)(255); + int16_t _4557 = (int16_t)(0); + bool _4558 = _cim_stencil_37 < _cim_stencil_38; + bool _4559 = _cim_stencil_39 < _cim_stencil_38; + bool _4560 = _4558 && _4559; + bool _4561 = _cim_stencil_40 < _cim_stencil_38; + bool _4562 = _4560 && _4561; + bool _4563 = _cim_stencil_41 < _cim_stencil_38; + bool _4564 = _4562 && _4563; + bool _4565 = _cim_stencil_42 < _cim_stencil_38; + bool _4566 = _4564 && _4565; + bool _4567 = _cim_stencil_43 < _cim_stencil_38; + bool _4568 = _4566 && _4567; + bool _4569 = _cim_stencil_44 < _cim_stencil_38; + bool _4570 = _4568 && _4569; + bool _4571 = _cim_stencil_45 < _cim_stencil_38; + bool _4572 = _4570 && _4571; + int16_t _4573 = (int16_t)(1); + bool _4574 = _4573 <= _cim_stencil_38; + bool _4575 = _4572 && _4574; + int16_t _4576 = (int16_t)(_4575 ? _4556 : _4557); + return _4576; +} + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), hw_output_s0_y_yi_1) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 1), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil_5(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_46 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_47 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_48 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_49 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_50 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_51 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_52 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_53 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_54 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _4633 = (int16_t)(255); + int16_t _4634 = (int16_t)(0); + bool _4635 = _cim_stencil_46 < _cim_stencil_47; + bool _4636 = _cim_stencil_48 < _cim_stencil_47; + bool _4637 = _4635 && _4636; + bool _4638 = _cim_stencil_49 < _cim_stencil_47; + bool _4639 = _4637 && _4638; + bool _4640 = _cim_stencil_50 < _cim_stencil_47; + bool _4641 = _4639 && _4640; + bool _4642 = _cim_stencil_51 < _cim_stencil_47; + bool _4643 = _4641 && _4642; + bool _4644 = _cim_stencil_52 < _cim_stencil_47; + bool _4645 = _4643 && _4644; + bool _4646 = _cim_stencil_53 < _cim_stencil_47; + bool _4647 = _4645 && _4646; + bool _4648 = _cim_stencil_54 < _cim_stencil_47; + bool _4649 = _4647 && _4648; + int16_t _4650 = (int16_t)(1); + bool _4651 = _4650 <= _cim_stencil_47; + bool _4652 = _4649 && _4651; + int16_t _4653 = (int16_t)(_4652 ? _4633 : _4634); + return _4653; +} + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), hw_output_s0_y_yi_1) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 2), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil_6(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_55 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_56 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_57 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_58 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_59 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_60 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_61 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_62 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_63 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _4711 = (int16_t)(255); + int16_t _4712 = (int16_t)(0); + bool _4713 = _cim_stencil_55 < _cim_stencil_56; + bool _4714 = _cim_stencil_57 < _cim_stencil_56; + bool _4715 = _4713 && _4714; + bool _4716 = _cim_stencil_58 < _cim_stencil_56; + bool _4717 = _4715 && _4716; + bool _4718 = _cim_stencil_59 < _cim_stencil_56; + bool _4719 = _4717 && _4718; + bool _4720 = _cim_stencil_60 < _cim_stencil_56; + bool _4721 = _4719 && _4720; + bool _4722 = _cim_stencil_61 < _cim_stencil_56; + bool _4723 = _4721 && _4722; + bool _4724 = _cim_stencil_62 < _cim_stencil_56; + bool _4725 = _4723 && _4724; + bool _4726 = _cim_stencil_63 < _cim_stencil_56; + bool _4727 = _4725 && _4726; + int16_t _4728 = (int16_t)(1); + bool _4729 = _4728 <= _cim_stencil_56; + bool _4730 = _4727 && _4729; + int16_t _4731 = (int16_t)(_4730 ? _4711 : _4712); + return _4731; +} + +//store is: hw_output.glb.stencil(((hw_output_s0_x_xi_xi_1*4) + 5), hw_output_s0_y_yi_1) = select((((((((((cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 5), hw_output_s0_y_yi_1) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 5), (hw_output_s0_y_yi_1 + 1)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 3), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))) && (cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 5), (hw_output_s0_y_yi_1 + 2)) < cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))) && ((int16)1 <= cim.stencil(((hw_output_s0_x_xi_xi_1*4) + 4), (hw_output_s0_y_yi_1 + 1)))), (int16)255, (int16)0) +hw_uint<16> hcompute_hw_output_glb_stencil_7(hw_uint<144>& cim_stencil) { + int16_t _cim_stencil_64 = (int16_t) (cim_stencil.extract<0, 15>()); + int16_t _cim_stencil_65 = (int16_t) (cim_stencil.extract<16, 31>()); + int16_t _cim_stencil_66 = (int16_t) (cim_stencil.extract<32, 47>()); + int16_t _cim_stencil_67 = (int16_t) (cim_stencil.extract<48, 63>()); + int16_t _cim_stencil_68 = (int16_t) (cim_stencil.extract<64, 79>()); + int16_t _cim_stencil_69 = (int16_t) (cim_stencil.extract<80, 95>()); + int16_t _cim_stencil_70 = (int16_t) (cim_stencil.extract<96, 111>()); + int16_t _cim_stencil_71 = (int16_t) (cim_stencil.extract<112, 127>()); + int16_t _cim_stencil_72 = (int16_t) (cim_stencil.extract<128, 143>()); + + int16_t _4789 = (int16_t)(255); + int16_t _4790 = (int16_t)(0); + bool _4791 = _cim_stencil_64 < _cim_stencil_65; + bool _4792 = _cim_stencil_66 < _cim_stencil_65; + bool _4793 = _4791 && _4792; + bool _4794 = _cim_stencil_67 < _cim_stencil_65; + bool _4795 = _4793 && _4794; + bool _4796 = _cim_stencil_68 < _cim_stencil_65; + bool _4797 = _4795 && _4796; + bool _4798 = _cim_stencil_69 < _cim_stencil_65; + bool _4799 = _4797 && _4798; + bool _4800 = _cim_stencil_70 < _cim_stencil_65; + bool _4801 = _4799 && _4800; + bool _4802 = _cim_stencil_71 < _cim_stencil_65; + bool _4803 = _4801 && _4802; + bool _4804 = _cim_stencil_72 < _cim_stencil_65; + bool _4805 = _4803 && _4804; + int16_t _4806 = (int16_t)(1); + bool _4807 = _4806 <= _cim_stencil_65; + bool _4808 = _4805 && _4807; + int16_t _4809 = (int16_t)(_4808 ? _4789 : _4790); + return _4809; +} + +//store is: hw_output_global_wrapper.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + (0*294)), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil((hw_output_global_wrapper_s0_x_xi_xi*4), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil(hw_uint<16>& hw_output_glb_stencil) { + int16_t _hw_output_glb_stencil_1 = (int16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_1; +} + +//store is: hw_output_global_wrapper.stencil((((hw_output_global_wrapper_s0_x_xi_xi*4) + (0*294)) + 1), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 1), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_1(hw_uint<16>& hw_output_glb_stencil) { + int16_t _hw_output_glb_stencil_2 = (int16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_2; +} + +//store is: hw_output_global_wrapper.stencil((((hw_output_global_wrapper_s0_x_xi_xi*4) + (0*294)) + 2), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 2), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_2(hw_uint<16>& hw_output_glb_stencil) { + int16_t _hw_output_glb_stencil_3 = (int16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_3; +} + +//store is: hw_output_global_wrapper.stencil((((hw_output_global_wrapper_s0_x_xi_xi*4) + (0*294)) + 3), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(((hw_output_global_wrapper_s0_x_xi_xi*4) + 3), hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_3(hw_uint<16>& hw_output_glb_stencil) { + int16_t _hw_output_glb_stencil_4 = (int16_t) (hw_output_glb_stencil.extract<0, 15>()); + + return _hw_output_glb_stencil_4; +} + diff --git a/io_header.json b/io_header.json new file mode 100644 index 000000000..bfbc80bff --- /dev/null +++ b/io_header.json @@ -0,0 +1,14 @@ +{"namespaces":{ + "global":{ + "modules":{ + "IO":{ + "type":["Record",[ + ["in",["Array",16,"BitIn"]], + ["out",["Array",16,"Bit"]] + ]], + "modparams":{"mode":"String"} + } + } + } +} +} diff --git a/isl_utils.cpp b/isl_utils.cpp index e28a30d3e..4483c58b5 100644 --- a/isl_utils.cpp +++ b/isl_utils.cpp @@ -1786,7 +1786,9 @@ isl_union_set* simplify(uset* const m) { } isl_map* simplify(isl_map* const m) { - return isl_map_remove_redundancies(cpy(m)); + auto tmp = isl_map_remove_redundancies(cpy(m)); + isl_map_detect_equalities(tmp); + return tmp; } isl_set* simplify(isl_set* const m) { @@ -1887,7 +1889,9 @@ int common_max_stride(isl_map* const m, int out_dim) { //Skip root start from 1 for (int in_dim=1; in_dim < num_in_dims(m); in_dim++){ int s = stride_in_dim(m, in_dim, out_dim); - if (s > 0) + int domain_range = get_domain_range(::domain(m), in_dim); + // only count the stride with domain range large than 1 + if ((s > 0) && (domain_range > 1)) cms = std::gcd(cms, s); } return cms; @@ -2514,6 +2518,41 @@ isl_map* delay_schedule_inner_most(isl_map* m, int delay) { return isl_map_from_basic_map(b_ret); } +isl_map* double_schedule_rate(isl_map* m, int in_dim, int fetch_width) { + cout << "schedule before double the rate: " << str(m) << endl; + auto c_vec = constraints(m); + int new_stride = -1; + for (auto & c: c_vec) { + bool involve = isl_constraint_involves_dims(c, isl_dim_in, in_dim-1, 1); + if (involve && isl_constraint_is_equality(c)) { + int upper_stride = -to_int(isl_constraint_get_coefficient_val(c, isl_dim_in, in_dim - 1)); + new_stride = upper_stride / 2; + if(new_stride < fetch_width/2) { + cout << "rate after double: " << new_stride << endl; + cout << "ERROR: rate is too high, need to relax the inner loop ii, or change halide schedule" < remove_dims) { + //cout << "map need to remove in dim: " << str(m) << endl; std::sort(remove_dims.begin(), remove_dims.end(), std::greater()); auto tmp = cpy(m); for (int dim: remove_dims) { @@ -2791,9 +2831,31 @@ isl_map* pad_to_domain_left_ubuf_map(isl_map* m, int dom_dim_id, int depth) { return isl_map_from_basic_map(b_ret); } +isl_map* add_relation_ubuf_map(isl_map* m, int dom_dim_id, int range_dim_id) { + + auto c_vec = constraints(m); + auto rel_map = relation_map(m); + assert(rel_map.at(dom_dim_id) == false); + auto b_ret = isl_basic_map_universe(get_space(m)); + for (auto & c: c_vec) { + bool involve; + involve = isl_constraint_involves_dims(c, isl_dim_out, range_dim_id, 1); + if (involve) { + int stride = to_int(isl_constraint_get_coefficient_val(c, isl_dim_out, range_dim_id)); + c = isl_constraint_set_coefficient_si(c, isl_dim_in, dom_dim_id, -stride); + } + } + for (auto c: c_vec) { + b_ret = isl_basic_map_add_constraint(b_ret, c); + } + + return isl_map_from_basic_map(b_ret); +} + isl_map* pad_to_domain_ubuf_map(isl_map* m, int dom_dim_id, int depth) { auto c_vec = constraints(m); + vector new_cons; for (auto & c: c_vec) { bool involve; @@ -2803,17 +2865,35 @@ isl_map* pad_to_domain_ubuf_map(isl_map* m, int dom_dim_id, int depth) { if (involve) { auto val = isl_val_get_num_si(isl_constraint_get_constant_val(c)); if (isl_constraint_is_equality(c)) { - //c = isl_constraint_set_constant_si(c, val + depth); + bool involve_range = false; + for (int i = 0; i < get_out_dim(m); i ++) { + involve_range = involve_range || isl_constraint_involves_dims(c, isl_dim_out, i, 1); + } + + if (involve_range) { + new_cons.push_back(c); + continue; + } + auto c_min = isl_constraint_alloc_inequality(get_local_space(c)); + c_min = isl_constraint_set_constant_si(c_min, val); + c_min = isl_constraint_set_coefficient_si(c_min, isl_dim_in, dom_dim_id, 1); + auto c_max = isl_constraint_alloc_inequality(get_local_space(c)); + c_max = isl_constraint_set_constant_si(c_max, val+1); + c_max = isl_constraint_set_coefficient_si(c_max, isl_dim_in, dom_dim_id, -1); + new_cons.push_back(c_max); + new_cons.push_back(c_min); } else { if (isl_constraint_is_upper_bound(c, isl_dim_in, dom_dim_id)) c = isl_constraint_set_constant_si(c , val+depth); + new_cons.push_back(c); } + } else { + new_cons.push_back(c); } } auto b_ret = isl_basic_map_universe(get_space(m)); - for (auto c: c_vec) { + for (auto c: new_cons) b_ret = isl_basic_map_add_constraint(b_ret, c); - } return isl_map_from_basic_map(b_ret); } @@ -3243,7 +3323,9 @@ isl_map* add_more_dim_to_map_with_stride(isl_map* const um, int in_dim, int out_ //pad the space for the original constraints for (auto c : c_vec) { + //cout << "\tconstraints before padding: " << str(c) << endl; auto tmp = pad_dim_to_constraint_domain(c, in_dim, out_dim, stride); + //cout << "\tconstraints after padding: " << str(tmp) << endl; new_c.push_back(tmp); } @@ -3261,6 +3343,7 @@ isl_map* add_more_dim_to_map_with_stride(isl_map* const um, int in_dim, int out_ auto ret = isl_basic_map_universe(sp); for (auto c : new_c) { ret = isl_basic_map_add_constraint(ret, c); + //cout << "new map in construction: " << str(ret) << endl; } auto ret_m = isl_map_from_basic_map(ret); @@ -4297,6 +4380,46 @@ vector> get_all_domain_merge_dims(isl_map* m) { return ret; } +map get_all_domain_pad_dims(isl_map* sched, isl_map* acc) { + int sched_in_dims = num_in_dims(sched); + int acc_in_dims = num_in_dims(acc); + assert(sched_in_dims == acc_in_dims); + + map dim2pad; + if (acc_in_dims < 3) + return dim2pad; + + //skip the root loop + for (int dim = 2; dim < acc_in_dims; dim ++) { + int sched_dom_range = get_dim_extent(domain(sched), dim); + int acc_dom_range = get_dim_extent(domain(acc), dim); + int sched_stride = stride_in_dim(sched, dim); + int acc_stride = stride_in_dim(acc, dim); + int sched_up_level_stride = stride_in_dim(sched, dim-1); + int acc_up_level_stride = stride_in_dim(acc, dim-1); + cout << tab(1)<< "Dim: " << dim << endl; + cout << tab(2)<< "Schedule dom range: " << sched_dom_range + << ", current_level_stride : "<< sched_stride + << ", up_level_stride : "<< sched_up_level_stride + << endl; + cout << tab(2)<< "Address dom range: " << acc_dom_range + << ", current_level_stride : "<< acc_stride + << ", up_level_stride : "<< acc_up_level_stride + << endl; + //TODO: why span range = 0 cannot be merged? + if ((sched_dom_range*sched_stride != sched_up_level_stride))// && (span_range != 0)) + { + int pad = sched_up_level_stride / sched_stride - sched_dom_range; + cout << "Find dim: " << dim << " pad = "<& bank_factors, isl_multi_aff* ma, isl_se //return isl_aff_floor(div(flat, 2)); } +pair +extract_div_free_linear_rational_approximation(isl_aff* aff_bound) { + int in_dims = num_in_dims(aff_bound); + int out_dims = num_out_dims(aff_bound); + int div_dims = num_div_dims(aff_bound); + + //cout << "in_dims = " << in_dims << endl; + //cout << "out_dims = " << out_dims << endl; + //cout << "div_dims = " << div_dims << endl; + + assert(in_dims == 1); + assert(out_dims == 1); + //assert(div_dims == 0); + + for (int i = 0; i < div_dims; i++) { + auto dc = isl_aff_get_coefficient_val(aff_bound, isl_dim_div, i); + assert(isl_val_is_zero(dc)); + } + + isl_val* b = isl_aff_get_constant_val(aff_bound); + isl_val* k = isl_aff_get_coefficient_val(aff_bound, isl_dim_in, 0); + //cout << "b = " << str(b) << endl; + //cout << "k = " << str(k) << endl; + + return {k, b}; +} + +isl_aff* remove_div(isl_aff* aff_bound) { + cout << "Extracting linear rational approximation for multi-in-dim affine: " << str(aff_bound) << endl; + + int in_dims = num_in_dims(aff_bound); + int out_dims = num_out_dims(aff_bound); + int div_dims = num_div_dims(aff_bound); + + //cout << "in_dims = " << in_dims << endl; + //cout << "out_dims = " << out_dims << endl; + //cout << "div_dims = " << div_dims << endl; + + //assert(in_dims == 1); + assert(out_dims == 1); + //cout << "div dims = " << div_dims << endl; + + if (div_dims == 0) { + return aff_bound; + } else { + //cout << "Getting div bound for: " << str(aff_bound) << endl; + //cout << "Div exprs..." << endl; + for (int i = 0; i < div_dims; i++) { + auto dexpr = isl_aff_get_div(aff_bound, i); + cout << tab(1) << str(dexpr) << endl; + } + assert(div_dims == 1); + + //set div coefficient to 0 + isl_aff* aff_rem_div = cpy(aff_bound); + aff_rem_div = isl_aff_set_coefficient_si(aff_rem_div, isl_dim_div, 0, 0); + + return aff_rem_div; + } +} + +isl_map* remove_div(isl_map* m, int out_dim) { + auto aff_vec = get_aff_vec(m); + isl_aff_list* list = isl_aff_list_alloc(ctx(m), aff_vec.size()); + for (int i = 0; i < aff_vec.size(); i ++) { + auto aff = aff_vec.at(i); + if (i == out_dim) { + auto aff_rem = remove_div(aff); + cout << "after removal: " << str(aff_rem) << endl; + list = isl_aff_list_add(list, isl_aff_copy(aff_rem)); + } else { + list = isl_aff_list_add(list, isl_aff_copy(aff)); + } + } + auto map_rem = to_map(isl_basic_map_from_aff_list(get_space(domain(m)), list)); + map_rem = isl_map_set_tuple_id(map_rem, isl_dim_out, id(ctx(m), range_name(m))); + + return map_rem; +} + +pair +extract_linear_rational_approximation(isl_aff* aff_bound) { + cout << "Extracting linear rational approximation: " << str(aff_bound) << endl; + + int in_dims = num_in_dims(aff_bound); + int out_dims = num_out_dims(aff_bound); + int div_dims = num_div_dims(aff_bound); + + //cout << "in_dims = " << in_dims << endl; + //cout << "out_dims = " << out_dims << endl; + //cout << "div_dims = " << div_dims << endl; + + assert(in_dims == 1); + assert(out_dims == 1); + //cout << "div dims = " << div_dims << endl; + + if (div_dims == 0) { + auto dkb = extract_div_free_linear_rational_approximation(aff_bound); + auto k = dkb.first; + auto b = dkb.second; + //cout << "b = " << str(b) << endl; + //cout << "k = " << str(k) << endl; + + return {k, b}; + } else { + //cout << "Getting div bound for: " << str(aff_bound) << endl; + //cout << "Div exprs..." << endl; + for (int i = 0; i < div_dims; i++) { + auto dexpr = isl_aff_get_div(aff_bound, i); + //cout << tab(1) << str(dexpr) << endl; + } + assert(div_dims == 1); + + isl_val* k = isl_aff_get_coefficient_val(aff_bound, isl_dim_in, 0); + isl_val* k_div = isl_aff_get_coefficient_val(aff_bound, isl_dim_div, 0); + isl_val* b = isl_aff_get_constant_val(aff_bound); + cout << "aff k = " << str(k) << endl; + cout << "aff k_div = " << str(k_div) << endl; + cout << "aff b = " << str(b) << endl; + + isl_aff* div_expr = isl_aff_get_div(aff_bound, 0); + cout << "Div: " << str(div_expr) << endl; + auto dkb = extract_div_free_linear_rational_approximation(div_expr); + cout << "div k = " << str(dkb.first) << endl; + cout << "div b = " << str(dkb.second) << endl; + + //assert(isl_val_is_zero(dkb.second)); + + isl_val* final_b = add(mul(dkb.second, k_div), b); + isl_val* final_k = add(mul(dkb.first, k_div), k); + cout << "final k = " << str(final_k) << endl; + cout << "final b = " << str(final_b) << endl; + //assert(isl_val_is_zero(k)); + + assert(k_div != 0); + if (k_div > 0) { + return {final_k, final_b}; + } else { + return {final_k, add(one(ctx(final_b)), final_b)}; + } + } +} + + isl_map* cyclic_function(isl_ctx* ctx, const std::string& name, const std::vector& bank_factors) { vector dvs; diff --git a/isl_utils.h b/isl_utils.h index 98ecc05ba..c1df7700d 100644 --- a/isl_utils.h +++ b/isl_utils.h @@ -388,7 +388,8 @@ pair get_domain_merge_dims(isl_map* m ); vector> get_all_domain_merge_dims(isl_map* m ); isl_map* merge_domain_dim(isl_map* m); - +map get_all_domain_pad_dims(isl_map* sched, isl_map* acc) +; //vectorization transformation isl_map* get_domain_mask(isl_map* m, int vec_dim); //For checking loop bound @@ -400,8 +401,17 @@ isl_map* get_domain_trans_with_reaccess_mask(isl_set* dom, int pos, int fetch_wi isl_set* get_domain_trans_sched_domain(isl_set* dom, int pos, int fetch_width); isl_set* get_domain_trans_sched_domain(isl_map* dom, int pos, int fetch_width); + + isl_map* get_div_trans(isl_map* am, map split_dims); +isl_map* remove_div(isl_map* m, int out_dim); + + +isl_aff* remove_div(isl_aff*); +pair extract_linear_rational_approximation(isl_aff*); +pair extract_div_free_linear_rational_approximation(isl_aff*); + isl_map* get_set_slice(isl_set* dom, int pos, int fetch_width); isl_map* get_set_slice(isl_set* dom, int pos, int offset, int fetch_width); vector get_vectorize_interpolate(isl_set* dom, int pos, int fetch_width); @@ -446,6 +456,7 @@ isl_map* retrive_map_domain_with_dim(isl_map*, isl_set*); isl_map* get_domain_ii_transform(isl_ctx* ctx, isl_set* const s, int ii); isl_map* get_shift_map(isl_map* s); +isl_map* double_schedule_rate(isl_map* m, int in_dim, int fetch_width); isl_map* delay_schedule_inner_most(isl_map* s, int delay); isl_map* set_schedule_delay(isl_map* m, int delay); isl_map* delay_schedule_domain_dim(isl_map* s, int dom_dim, int delay); @@ -468,6 +479,7 @@ int get_pad_remainder(isl_map*, int, int); isl_map* reset_domain_coeff(isl_map* m, int dom_dim_id, int val); isl_map* pad_to_domain_map(isl_map* s, int depth); isl_map* pad_to_domain_ubuf_map(isl_map* s, int dom_dim_id, int depth); +isl_map* add_relation_ubuf_map(isl_map* m, int dom_dim_id, int range_dim_id); isl_map* pad_to_domain_left_ubuf_map(isl_map* m, int dom_dim_id, int shift_depth); isl_map* pad_to_domain_begin_ubuf_map(isl_map* m, int dom_dim_id, int shift_depth); isl_map* shift_domain_map(isl_map* s, vector shift_depth); diff --git a/laplacian_pyramid_docker_compute.h b/laplacian_pyramid_docker_compute.h new file mode 100644 index 000000000..f787556f5 --- /dev/null +++ b/laplacian_pyramid_docker_compute.h @@ -0,0 +1,299 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil((hw_input_global_wrapper_s0_x + 7), (hw_input_global_wrapper_s0_y + 7)) = hw_input.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_1; +} + +//store is: blur_unnormalized.stencil((blur_unnormalized_s0_x + 7), (blur_unnormalized_s0_y + 7)) = (uint16)0 +hw_uint<16> hcompute_blur_unnormalized_stencil() { + uint16_t _407 = (uint16_t)(0); + return _407; +} + +//store is: blur_unnormalized.stencil((blur_unnormalized_s1_x + 7), (blur_unnormalized_s1_y + 7)) = ((hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 7), (blur_unnormalized_s1_y + 7))*(uint16)3) + (blur_unnormalized.stencil((blur_unnormalized_s1_x + 7), (blur_unnormalized_s1_y + 7)) + ((hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 8), (blur_unnormalized_s1_y + 7))*(uint16)21) + ((hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 9), (blur_unnormalized_s1_y + 7))*(uint16)3) + ((hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 7), (blur_unnormalized_s1_y + 8))*(uint16)21) + ((((hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 9), (blur_unnormalized_s1_y + 8))*(uint16)7) + (hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 7), (blur_unnormalized_s1_y + 9)) + (hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 9), (blur_unnormalized_s1_y + 9)) + (hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 8), (blur_unnormalized_s1_y + 9))*(uint16)7))))*(uint16)3) + (hw_input_global_wrapper.stencil((blur_unnormalized_s1_x + 8), (blur_unnormalized_s1_y + 8))*(uint16)158))))))) +hw_uint<16> hcompute_blur_unnormalized_stencil_1(hw_uint<16>& blur_unnormalized_stencil, hw_uint<144>& hw_input_global_wrapper_stencil) { + uint16_t _blur_unnormalized_stencil_1 = (uint16_t) blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _hw_input_global_wrapper_stencil_1 = (uint16_t) hw_input_global_wrapper_stencil.extract<0, 15>(); + uint16_t _hw_input_global_wrapper_stencil_2 = (uint16_t) hw_input_global_wrapper_stencil.extract<16, 31>(); + uint16_t _hw_input_global_wrapper_stencil_3 = (uint16_t) hw_input_global_wrapper_stencil.extract<32, 47>(); + uint16_t _hw_input_global_wrapper_stencil_4 = (uint16_t) hw_input_global_wrapper_stencil.extract<48, 63>(); + uint16_t _hw_input_global_wrapper_stencil_5 = (uint16_t) hw_input_global_wrapper_stencil.extract<64, 79>(); + uint16_t _hw_input_global_wrapper_stencil_6 = (uint16_t) hw_input_global_wrapper_stencil.extract<80, 95>(); + uint16_t _hw_input_global_wrapper_stencil_7 = (uint16_t) hw_input_global_wrapper_stencil.extract<96, 111>(); + uint16_t _hw_input_global_wrapper_stencil_8 = (uint16_t) hw_input_global_wrapper_stencil.extract<112, 127>(); + uint16_t _hw_input_global_wrapper_stencil_9 = (uint16_t) hw_input_global_wrapper_stencil.extract<128, 143>(); + + uint16_t _412 = (uint16_t)(3); + uint16_t _413 = _hw_input_global_wrapper_stencil_1 * _412; + uint16_t _414 = (uint16_t)(21); + uint16_t _415 = _hw_input_global_wrapper_stencil_2 * _414; + uint16_t _416 = _hw_input_global_wrapper_stencil_3 * _412; + uint16_t _417 = _hw_input_global_wrapper_stencil_4 * _414; + uint16_t _418 = (uint16_t)(7); + uint16_t _419 = _hw_input_global_wrapper_stencil_5 * _418; + uint16_t _420 = _hw_input_global_wrapper_stencil_8 * _418; + uint16_t _421 = _hw_input_global_wrapper_stencil_7 + _420; + uint16_t _422 = _hw_input_global_wrapper_stencil_6 + _421; + uint16_t _423 = _419 + _422; + uint16_t _424 = _423 * _412; + uint16_t _425 = (uint16_t)(158); + uint16_t _426 = _hw_input_global_wrapper_stencil_9 * _425; + uint16_t _427 = _424 + _426; + uint16_t _428 = _417 + _427; + uint16_t _429 = _416 + _428; + uint16_t _430 = _415 + _429; + uint16_t _431 = _blur_unnormalized_stencil_1 + _430; + uint16_t _432 = _413 + _431; + return _432; +} + +//store is: l0$0.stencil((l0_0_s0_x + 6), (l0_0_s0_y + 6)) = (blur_unnormalized.stencil((l0_0_s0_x + 6), (l0_0_s0_y + 6))/(uint16)256) +hw_uint<16> hcompute_l0_0_stencil(hw_uint<16>& blur_unnormalized_stencil) { + uint16_t _blur_unnormalized_stencil_2 = (uint16_t) blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _491 = (uint16_t)(8); + uint16_t _492 = _blur_unnormalized_stencil_2 >> _491; + return _492; +} + +//store is: h0$0.stencil(h0_0_s0_x, h0_0_s0_y) = (hw_input_global_wrapper.stencil((h0_0_s0_x + 7), (h0_0_s0_y + 7)) - l0$0.stencil((h0_0_s0_x + 6), (h0_0_s0_y + 6))) +hw_uint<16> hcompute_h0_0_stencil(hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& l0_0_stencil) { + uint16_t _hw_input_global_wrapper_stencil_10 = (uint16_t) hw_input_global_wrapper_stencil.extract<0, 15>(); + + uint16_t _l0_0_stencil_1 = (uint16_t) l0_0_stencil.extract<0, 15>(); + + uint16_t _500 = _hw_input_global_wrapper_stencil_10 - _l0_0_stencil_1; + return _500; +} + +//store is: f1$0.stencil((f1_0_s0_x + 3), (f1_0_s0_y + 3)) = l0$0.stencil(((f1_0_s0_x*2) + 6), ((f1_0_s0_y*2) + 6)) +hw_uint<16> hcompute_f1_0_stencil(hw_uint<16>& l0_0_stencil) { + uint16_t _l0_0_stencil_2 = (uint16_t) l0_0_stencil.extract<0, 15>(); + + return _l0_0_stencil_2; +} + +//store is: f1_blur_unnormalized.stencil((f1_blur_unnormalized_s0_x + 3), (f1_blur_unnormalized_s0_y + 3)) = (uint16)0 +hw_uint<16> hcompute_f1_blur_unnormalized_stencil() { + uint16_t _516 = (uint16_t)(0); + return _516; +} + +//store is: f1_blur_unnormalized.stencil((f1_blur_unnormalized_s1_x + 3), (f1_blur_unnormalized_s1_y + 3)) = ((f1$0.stencil((f1_blur_unnormalized_s1_x + 3), (f1_blur_unnormalized_s1_y + 3))*(uint16)3) + (f1_blur_unnormalized.stencil((f1_blur_unnormalized_s1_x + 3), (f1_blur_unnormalized_s1_y + 3)) + ((f1$0.stencil((f1_blur_unnormalized_s1_x + 4), (f1_blur_unnormalized_s1_y + 3))*(uint16)21) + ((f1$0.stencil((f1_blur_unnormalized_s1_x + 5), (f1_blur_unnormalized_s1_y + 3))*(uint16)3) + ((f1$0.stencil((f1_blur_unnormalized_s1_x + 3), (f1_blur_unnormalized_s1_y + 4))*(uint16)21) + ((((f1$0.stencil((f1_blur_unnormalized_s1_x + 5), (f1_blur_unnormalized_s1_y + 4))*(uint16)7) + (f1$0.stencil((f1_blur_unnormalized_s1_x + 3), (f1_blur_unnormalized_s1_y + 5)) + (f1$0.stencil((f1_blur_unnormalized_s1_x + 5), (f1_blur_unnormalized_s1_y + 5)) + (f1$0.stencil((f1_blur_unnormalized_s1_x + 4), (f1_blur_unnormalized_s1_y + 5))*(uint16)7))))*(uint16)3) + (f1$0.stencil((f1_blur_unnormalized_s1_x + 4), (f1_blur_unnormalized_s1_y + 4))*(uint16)158))))))) +hw_uint<16> hcompute_f1_blur_unnormalized_stencil_1(hw_uint<144>& f1_0_stencil, hw_uint<16>& f1_blur_unnormalized_stencil) { + uint16_t _f1_0_stencil_1 = (uint16_t) f1_0_stencil.extract<0, 15>(); + uint16_t _f1_0_stencil_2 = (uint16_t) f1_0_stencil.extract<16, 31>(); + uint16_t _f1_0_stencil_3 = (uint16_t) f1_0_stencil.extract<32, 47>(); + uint16_t _f1_0_stencil_4 = (uint16_t) f1_0_stencil.extract<48, 63>(); + uint16_t _f1_0_stencil_5 = (uint16_t) f1_0_stencil.extract<64, 79>(); + uint16_t _f1_0_stencil_6 = (uint16_t) f1_0_stencil.extract<80, 95>(); + uint16_t _f1_0_stencil_7 = (uint16_t) f1_0_stencil.extract<96, 111>(); + uint16_t _f1_0_stencil_8 = (uint16_t) f1_0_stencil.extract<112, 127>(); + uint16_t _f1_0_stencil_9 = (uint16_t) f1_0_stencil.extract<128, 143>(); + + uint16_t _f1_blur_unnormalized_stencil_1 = (uint16_t) f1_blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _521 = (uint16_t)(3); + uint16_t _522 = _f1_0_stencil_1 * _521; + uint16_t _523 = (uint16_t)(21); + uint16_t _524 = _f1_0_stencil_2 * _523; + uint16_t _525 = _f1_0_stencil_3 * _521; + uint16_t _526 = _f1_0_stencil_4 * _523; + uint16_t _527 = (uint16_t)(7); + uint16_t _528 = _f1_0_stencil_5 * _527; + uint16_t _529 = _f1_0_stencil_8 * _527; + uint16_t _530 = _f1_0_stencil_7 + _529; + uint16_t _531 = _f1_0_stencil_6 + _530; + uint16_t _532 = _528 + _531; + uint16_t _533 = _532 * _521; + uint16_t _534 = (uint16_t)(158); + uint16_t _535 = _f1_0_stencil_9 * _534; + uint16_t _536 = _533 + _535; + uint16_t _537 = _526 + _536; + uint16_t _538 = _525 + _537; + uint16_t _539 = _524 + _538; + uint16_t _540 = _f1_blur_unnormalized_stencil_1 + _539; + uint16_t _541 = _522 + _540; + return _541; +} + +//store is: l1$0.stencil((l1_0_s0_x + 2), (l1_0_s0_y + 2)) = (f1_blur_unnormalized.stencil((l1_0_s0_x + 2), (l1_0_s0_y + 2))/(uint16)256) +hw_uint<16> hcompute_l1_0_stencil(hw_uint<16>& f1_blur_unnormalized_stencil) { + uint16_t _f1_blur_unnormalized_stencil_2 = (uint16_t) f1_blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _600 = (uint16_t)(8); + uint16_t _601 = _f1_blur_unnormalized_stencil_2 >> _600; + return _601; +} + +//store is: h1$0.stencil((h1_0_s0_x + 1), (h1_0_s0_y + 1)) = (f1$0.stencil((h1_0_s0_x + 3), (h1_0_s0_y + 3)) - l1$0.stencil((h1_0_s0_x + 2), (h1_0_s0_y + 2))) +hw_uint<16> hcompute_h1_0_stencil(hw_uint<16>& f1_0_stencil, hw_uint<16>& l1_0_stencil) { + uint16_t _f1_0_stencil_10 = (uint16_t) f1_0_stencil.extract<0, 15>(); + + uint16_t _l1_0_stencil_1 = (uint16_t) l1_0_stencil.extract<0, 15>(); + + uint16_t _609 = _f1_0_stencil_10 - _l1_0_stencil_1; + return _609; +} + +//store is: f2$0.stencil((f2_0_s0_x + 1), (f2_0_s0_y + 1)) = l1$0.stencil(((f2_0_s0_x*2) + 2), ((f2_0_s0_y*2) + 2)) +hw_uint<16> hcompute_f2_0_stencil(hw_uint<16>& l1_0_stencil) { + uint16_t _l1_0_stencil_2 = (uint16_t) l1_0_stencil.extract<0, 15>(); + + return _l1_0_stencil_2; +} + +//store is: f2_temp.stencil((f2_temp_s0_x + 2), (f2_temp_s0_y + 2)) = f2$0.stencil(((f2_temp_s0_x/2) + 1), ((f2_temp_s0_y/2) + 1)) +hw_uint<16> hcompute_f2_temp_stencil(hw_uint<16>& f2_0_stencil) { + uint16_t _f2_0_stencil_1 = (uint16_t) f2_0_stencil.extract<0, 15>(); + + return _f2_0_stencil_1; +} + +//store is: f2_temp_blur_unnormalized.stencil((f2_temp_blur_unnormalized_s0_x + 2), (f2_temp_blur_unnormalized_s0_y + 2)) = (uint16)0 +hw_uint<16> hcompute_f2_temp_blur_unnormalized_stencil() { + uint16_t _634 = (uint16_t)(0); + return _634; +} + +//store is: f2_temp_blur_unnormalized.stencil((f2_temp_blur_unnormalized_s1_x + 2), (f2_temp_blur_unnormalized_s1_y + 2)) = ((f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 2), (f2_temp_blur_unnormalized_s1_y + 2))*(uint16)3) + (f2_temp_blur_unnormalized.stencil((f2_temp_blur_unnormalized_s1_x + 2), (f2_temp_blur_unnormalized_s1_y + 2)) + ((f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 3), (f2_temp_blur_unnormalized_s1_y + 2))*(uint16)21) + ((f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 4), (f2_temp_blur_unnormalized_s1_y + 2))*(uint16)3) + ((f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 2), (f2_temp_blur_unnormalized_s1_y + 3))*(uint16)21) + ((((f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 4), (f2_temp_blur_unnormalized_s1_y + 3))*(uint16)7) + (f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 2), (f2_temp_blur_unnormalized_s1_y + 4)) + (f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 4), (f2_temp_blur_unnormalized_s1_y + 4)) + (f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 3), (f2_temp_blur_unnormalized_s1_y + 4))*(uint16)7))))*(uint16)3) + (f2_temp.stencil((f2_temp_blur_unnormalized_s1_x + 3), (f2_temp_blur_unnormalized_s1_y + 3))*(uint16)158))))))) +hw_uint<16> hcompute_f2_temp_blur_unnormalized_stencil_1(hw_uint<144>& f2_temp_stencil, hw_uint<16>& f2_temp_blur_unnormalized_stencil) { + uint16_t _f2_temp_stencil_1 = (uint16_t) f2_temp_stencil.extract<0, 15>(); + uint16_t _f2_temp_stencil_2 = (uint16_t) f2_temp_stencil.extract<16, 31>(); + uint16_t _f2_temp_stencil_3 = (uint16_t) f2_temp_stencil.extract<32, 47>(); + uint16_t _f2_temp_stencil_4 = (uint16_t) f2_temp_stencil.extract<48, 63>(); + uint16_t _f2_temp_stencil_5 = (uint16_t) f2_temp_stencil.extract<64, 79>(); + uint16_t _f2_temp_stencil_6 = (uint16_t) f2_temp_stencil.extract<80, 95>(); + uint16_t _f2_temp_stencil_7 = (uint16_t) f2_temp_stencil.extract<96, 111>(); + uint16_t _f2_temp_stencil_8 = (uint16_t) f2_temp_stencil.extract<112, 127>(); + uint16_t _f2_temp_stencil_9 = (uint16_t) f2_temp_stencil.extract<128, 143>(); + + uint16_t _f2_temp_blur_unnormalized_stencil_1 = (uint16_t) f2_temp_blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _639 = (uint16_t)(3); + uint16_t _640 = _f2_temp_stencil_1 * _639; + uint16_t _641 = (uint16_t)(21); + uint16_t _642 = _f2_temp_stencil_2 * _641; + uint16_t _643 = _f2_temp_stencil_3 * _639; + uint16_t _644 = _f2_temp_stencil_4 * _641; + uint16_t _645 = (uint16_t)(7); + uint16_t _646 = _f2_temp_stencil_5 * _645; + uint16_t _647 = _f2_temp_stencil_8 * _645; + uint16_t _648 = _f2_temp_stencil_7 + _647; + uint16_t _649 = _f2_temp_stencil_6 + _648; + uint16_t _650 = _646 + _649; + uint16_t _651 = _650 * _639; + uint16_t _652 = (uint16_t)(158); + uint16_t _653 = _f2_temp_stencil_9 * _652; + uint16_t _654 = _651 + _653; + uint16_t _655 = _644 + _654; + uint16_t _656 = _643 + _655; + uint16_t _657 = _642 + _656; + uint16_t _658 = _f2_temp_blur_unnormalized_stencil_1 + _657; + uint16_t _659 = _640 + _658; + return _659; +} + +//store is: l1_up.stencil((l1_up_s0_x + 1), (l1_up_s0_y + 1)) = (f2_temp_blur_unnormalized.stencil((l1_up_s0_x + 1), (l1_up_s0_y + 1))/(uint16)256) +hw_uint<16> hcompute_l1_up_stencil(hw_uint<16>& f2_temp_blur_unnormalized_stencil) { + uint16_t _f2_temp_blur_unnormalized_stencil_2 = (uint16_t) f2_temp_blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _718 = (uint16_t)(8); + uint16_t _719 = _f2_temp_blur_unnormalized_stencil_2 >> _718; + return _719; +} + +//store is: f1_up.stencil((f1_up_s0_x + 1), (f1_up_s0_y + 1)) = (l1_up.stencil((f1_up_s0_x + 1), (f1_up_s0_y + 1)) + h1$0.stencil((f1_up_s0_x + 1), (f1_up_s0_y + 1))) +hw_uint<16> hcompute_f1_up_stencil_1(hw_uint<16>& h1_0_stencil, hw_uint<16>& l1_up_stencil) { + uint16_t _h1_0_stencil_1 = (uint16_t) h1_0_stencil.extract<0, 15>(); + + uint16_t _l1_up_stencil_1 = (uint16_t) l1_up_stencil.extract<0, 15>(); + + uint16_t _727 = _l1_up_stencil_1 + _h1_0_stencil_1; + return _727; +} + +//store is: f1_temp.stencil((f1_temp_s0_x + 1), (f1_temp_s0_y + 1)) = f1_up.stencil(((f1_temp_s0_x/2) + 1), ((f1_temp_s0_y/2) + 1)) +hw_uint<16> hcompute_f1_temp_stencil(hw_uint<16>& f1_up_stencil) { + uint16_t _f1_up_stencil_1 = (uint16_t) f1_up_stencil.extract<0, 15>(); + + return _f1_up_stencil_1; +} + +//store is: f1_temp_blur_unnormalized.stencil((f1_temp_blur_unnormalized_s0_x + 1), (f1_temp_blur_unnormalized_s0_y + 1)) = (uint16)0 +hw_uint<16> hcompute_f1_temp_blur_unnormalized_stencil() { + uint16_t _741 = (uint16_t)(0); + return _741; +} + +//store is: f1_temp_blur_unnormalized.stencil((f1_temp_blur_unnormalized_s1_x + 1), (f1_temp_blur_unnormalized_s1_y + 1)) = ((f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 1), (f1_temp_blur_unnormalized_s1_y + 1))*(uint16)3) + (f1_temp_blur_unnormalized.stencil((f1_temp_blur_unnormalized_s1_x + 1), (f1_temp_blur_unnormalized_s1_y + 1)) + ((f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 2), (f1_temp_blur_unnormalized_s1_y + 1))*(uint16)21) + ((f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 3), (f1_temp_blur_unnormalized_s1_y + 1))*(uint16)3) + ((f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 1), (f1_temp_blur_unnormalized_s1_y + 2))*(uint16)21) + ((((f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 3), (f1_temp_blur_unnormalized_s1_y + 2))*(uint16)7) + (f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 1), (f1_temp_blur_unnormalized_s1_y + 3)) + (f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 3), (f1_temp_blur_unnormalized_s1_y + 3)) + (f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 2), (f1_temp_blur_unnormalized_s1_y + 3))*(uint16)7))))*(uint16)3) + (f1_temp.stencil((f1_temp_blur_unnormalized_s1_x + 2), (f1_temp_blur_unnormalized_s1_y + 2))*(uint16)158))))))) +hw_uint<16> hcompute_f1_temp_blur_unnormalized_stencil_1(hw_uint<144>& f1_temp_stencil, hw_uint<16>& f1_temp_blur_unnormalized_stencil) { + uint16_t _f1_temp_stencil_1 = (uint16_t) f1_temp_stencil.extract<0, 15>(); + uint16_t _f1_temp_stencil_2 = (uint16_t) f1_temp_stencil.extract<16, 31>(); + uint16_t _f1_temp_stencil_3 = (uint16_t) f1_temp_stencil.extract<32, 47>(); + uint16_t _f1_temp_stencil_4 = (uint16_t) f1_temp_stencil.extract<48, 63>(); + uint16_t _f1_temp_stencil_5 = (uint16_t) f1_temp_stencil.extract<64, 79>(); + uint16_t _f1_temp_stencil_6 = (uint16_t) f1_temp_stencil.extract<80, 95>(); + uint16_t _f1_temp_stencil_7 = (uint16_t) f1_temp_stencil.extract<96, 111>(); + uint16_t _f1_temp_stencil_8 = (uint16_t) f1_temp_stencil.extract<112, 127>(); + uint16_t _f1_temp_stencil_9 = (uint16_t) f1_temp_stencil.extract<128, 143>(); + + uint16_t _f1_temp_blur_unnormalized_stencil_1 = (uint16_t) f1_temp_blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _746 = (uint16_t)(3); + uint16_t _747 = _f1_temp_stencil_1 * _746; + uint16_t _748 = (uint16_t)(21); + uint16_t _749 = _f1_temp_stencil_2 * _748; + uint16_t _750 = _f1_temp_stencil_3 * _746; + uint16_t _751 = _f1_temp_stencil_4 * _748; + uint16_t _752 = (uint16_t)(7); + uint16_t _753 = _f1_temp_stencil_5 * _752; + uint16_t _754 = _f1_temp_stencil_8 * _752; + uint16_t _755 = _f1_temp_stencil_7 + _754; + uint16_t _756 = _f1_temp_stencil_6 + _755; + uint16_t _757 = _753 + _756; + uint16_t _758 = _757 * _746; + uint16_t _759 = (uint16_t)(158); + uint16_t _760 = _f1_temp_stencil_9 * _759; + uint16_t _761 = _758 + _760; + uint16_t _762 = _751 + _761; + uint16_t _763 = _750 + _762; + uint16_t _764 = _749 + _763; + uint16_t _765 = _f1_temp_blur_unnormalized_stencil_1 + _764; + uint16_t _766 = _747 + _765; + return _766; +} + +//store is: l0_up.stencil(l0_up_s0_x, l0_up_s0_y) = (f1_temp_blur_unnormalized.stencil(l0_up_s0_x, l0_up_s0_y)/(uint16)256) +hw_uint<16> hcompute_l0_up_stencil(hw_uint<16>& f1_temp_blur_unnormalized_stencil) { + uint16_t _f1_temp_blur_unnormalized_stencil_2 = (uint16_t) f1_temp_blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _825 = (uint16_t)(8); + uint16_t _826 = _f1_temp_blur_unnormalized_stencil_2 >> _825; + return _826; +} + +//store is: f0_up.stencil(f0_up_s0_x, f0_up_s0_y) = (l0_up.stencil(f0_up_s0_x, f0_up_s0_y) + h0$0.stencil(f0_up_s0_x, f0_up_s0_y)) +hw_uint<16> hcompute_f0_up_stencil(hw_uint<16>& h0_0_stencil, hw_uint<16>& l0_up_stencil) { + uint16_t _h0_0_stencil_1 = (uint16_t) h0_0_stencil.extract<0, 15>(); + + uint16_t _l0_up_stencil_1 = (uint16_t) l0_up_stencil.extract<0, 15>(); + + uint16_t _832 = _l0_up_stencil_1 + _h0_0_stencil_1; + return _832; +} + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) = f0_up.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& f0_up_stencil) { + uint16_t _f0_up_stencil_1 = (uint16_t) f0_up_stencil.extract<0, 15>(); + + return _f0_up_stencil_1; +} + diff --git a/lassen_header.json b/lassen_header.json new file mode 100644 index 000000000..a1fdbb850 --- /dev/null +++ b/lassen_header.json @@ -0,0 +1,26 @@ +{"namespaces":{ + "global":{ + "modules":{ + "PE":{ + "type":["Record",[ + ["inst",["Array",67,"BitIn"]], + ["data0",["Array",16,"BitIn"]], + ["data1",["Array",16,"BitIn"]], + ["bit0","BitIn"], + ["bit1","BitIn"], + ["bit2","BitIn"], + ["clk_en","BitIn"], + ["config_addr",["Array",8,"BitIn"]], + ["config_data",["Array",32,"BitIn"]], + ["config_en","BitIn"], + ["O0",["Array",16,"Bit"]], + ["O1","Bit"], + ["O2",["Array",32,"Bit"]], + ["CLK",["Named","coreir.clkIn"]], + ["ASYNCRESET",["Named","coreir.arstIn"]] + ]] + } + } + } +} +} diff --git a/matmul_unroll2_compute.h b/matmul_unroll2_compute.h new file mode 100644 index 000000000..d216b434a --- /dev/null +++ b/matmul_unroll2_compute.h @@ -0,0 +1,72 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) = hw_input.stencil(hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_1 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_kernel_global_wrapper.stencil(hw_kernel_global_wrapper_s0_x, hw_kernel_global_wrapper_s0_y) = hw_kernel.stencil(hw_kernel_global_wrapper_s0_x, hw_kernel_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_kernel_global_wrapper_stencil(hw_uint<16>& hw_kernel_stencil) { + int16_t _hw_kernel_stencil_1 = (int16_t) (hw_kernel_stencil.extract<0, 15>()); + + return _hw_kernel_stencil_1; +} + +//store is: mul.stencil((mul_s0_x_x*2), mul_s0_y) = (int16)0 +hw_uint<16> hcompute_mul_stencil() { + int16_t _390 = (int16_t)(0); + return _390; +} + +//store is: mul.stencil(((mul_s0_x_x*2) + 1), mul_s0_y) = (int16)0 +hw_uint<16> hcompute_mul_stencil_1() { + int16_t _394 = (int16_t)(0); + return _394; +} + +//store is: mul.stencil((mul_s1_x_xo*2), mul_s1_y) = ((hw_input_global_wrapper.stencil((mul_s1_r_x_rxo*2), mul_s1_y)*hw_kernel_global_wrapper.stencil((mul_s1_x_xo*2), (mul_s1_r_x_rxo*2))) + (mul.stencil((mul_s1_x_xo*2), mul_s1_y) + (hw_input_global_wrapper.stencil(((mul_s1_r_x_rxo*2) + 1), mul_s1_y)*hw_kernel_global_wrapper.stencil((mul_s1_x_xo*2), ((mul_s1_r_x_rxo*2) + 1))))) +hw_uint<16> hcompute_mul_stencil_2(hw_uint<32>& hw_input_global_wrapper_stencil, hw_uint<32>& hw_kernel_global_wrapper_stencil, hw_uint<16>& mul_stencil) { + int16_t _hw_input_global_wrapper_stencil_1 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_stencil_2 = (int16_t) (hw_input_global_wrapper_stencil.extract<16, 31>()); + + int16_t _hw_kernel_global_wrapper_stencil_1 = (int16_t) (hw_kernel_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_kernel_global_wrapper_stencil_2 = (int16_t) (hw_kernel_global_wrapper_stencil.extract<16, 31>()); + + int16_t _mul_stencil_1 = (int16_t) (mul_stencil.extract<0, 15>()); + + int16_t _399 = _hw_input_global_wrapper_stencil_1 * _hw_kernel_global_wrapper_stencil_1; + int16_t _400 = _hw_input_global_wrapper_stencil_2 * _hw_kernel_global_wrapper_stencil_2; + int16_t _401 = _mul_stencil_1 + _400; + int16_t _402 = _399 + _401; + return _402; +} + +//store is: mul.stencil(((mul_s1_x_xo*2) + 1), mul_s1_y) = ((hw_input_global_wrapper.stencil((mul_s1_r_x_rxo*2), mul_s1_y)*hw_kernel_global_wrapper.stencil(((mul_s1_x_xo*2) + 1), (mul_s1_r_x_rxo*2))) + (mul.stencil(((mul_s1_x_xo*2) + 1), mul_s1_y) + (hw_input_global_wrapper.stencil(((mul_s1_r_x_rxo*2) + 1), mul_s1_y)*hw_kernel_global_wrapper.stencil(((mul_s1_x_xo*2) + 1), ((mul_s1_r_x_rxo*2) + 1))))) +hw_uint<16> hcompute_mul_stencil_3(hw_uint<32>& hw_input_global_wrapper_stencil, hw_uint<32>& hw_kernel_global_wrapper_stencil, hw_uint<16>& mul_stencil) { + int16_t _hw_input_global_wrapper_stencil_3 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_stencil_4 = (int16_t) (hw_input_global_wrapper_stencil.extract<16, 31>()); + + int16_t _hw_kernel_global_wrapper_stencil_3 = (int16_t) (hw_kernel_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_kernel_global_wrapper_stencil_4 = (int16_t) (hw_kernel_global_wrapper_stencil.extract<16, 31>()); + + int16_t _mul_stencil_2 = (int16_t) (mul_stencil.extract<0, 15>()); + + int16_t _419 = _hw_input_global_wrapper_stencil_3 * _hw_kernel_global_wrapper_stencil_3; + int16_t _420 = _hw_input_global_wrapper_stencil_4 * _hw_kernel_global_wrapper_stencil_4; + int16_t _421 = _mul_stencil_2 + _420; + int16_t _422 = _419 + _421; + return _422; +} + +//store is: hw_output.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) = mul.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& mul_stencil) { + int16_t _mul_stencil_3 = (int16_t) (mul_stencil.extract<0, 15>()); + + return _mul_stencil_3; +} + diff --git a/mem_header.json b/mem_header.json new file mode 100644 index 000000000..cca69050b --- /dev/null +++ b/mem_header.json @@ -0,0 +1,39 @@ +{"namespaces":{ + "global":{ + "modules":{ + "MEM":{ + "type":["Record",[ + ["configs",["Array",2413,"BitIn"]], + ["chain_data_in_0",["Array",16,"BitIn"]], + ["chain_data_in_1",["Array",16,"BitIn"]], + ["flush","BitIn"], + ["config_read","BitIn"], + ["ren_in_0","BitIn"], + ["ren_in_1","BitIn"], + ["config_en",["Array",2,"BitIn"]], + ["config_write","BitIn"], + ["config_data_in",["Array",32,"BitIn"]], + ["clk_en","BitIn"], + ["wen_in",["Array",2,"BitIn"]], + ["config_addr_in",["Array",8,"BitIn"]], + ["addr_in_0",["Array",16,"BitIn"]], + ["addr_in_1",["Array",16,"BitIn"]], + ["data_in_0",["Array",16,"BitIn"]], + ["data_in_1",["Array",16,"BitIn"]], + ["O0",["Array",16,"Bit"]], + ["O1","Bit"], + ["O2","Bit"], + ["O3","Bit"], + ["O4",["Array",16,"Bit"]], + ["O5","Bit"], + ["O6","Bit"], + ["O7","Bit"], + ["O8",["Array",32,"Bit"]], + ["CLK",["Named","coreir.clkIn"]], + ["ASYNCRESET",["Named","coreir.arstIn"]] + ]] + } + } + } +} +} diff --git a/memtile_header.json b/memtile_header.json new file mode 100644 index 000000000..cca69050b --- /dev/null +++ b/memtile_header.json @@ -0,0 +1,39 @@ +{"namespaces":{ + "global":{ + "modules":{ + "MEM":{ + "type":["Record",[ + ["configs",["Array",2413,"BitIn"]], + ["chain_data_in_0",["Array",16,"BitIn"]], + ["chain_data_in_1",["Array",16,"BitIn"]], + ["flush","BitIn"], + ["config_read","BitIn"], + ["ren_in_0","BitIn"], + ["ren_in_1","BitIn"], + ["config_en",["Array",2,"BitIn"]], + ["config_write","BitIn"], + ["config_data_in",["Array",32,"BitIn"]], + ["clk_en","BitIn"], + ["wen_in",["Array",2,"BitIn"]], + ["config_addr_in",["Array",8,"BitIn"]], + ["addr_in_0",["Array",16,"BitIn"]], + ["addr_in_1",["Array",16,"BitIn"]], + ["data_in_0",["Array",16,"BitIn"]], + ["data_in_1",["Array",16,"BitIn"]], + ["O0",["Array",16,"Bit"]], + ["O1","Bit"], + ["O2","Bit"], + ["O3","Bit"], + ["O4",["Array",16,"Bit"]], + ["O5","Bit"], + ["O6","Bit"], + ["O7","Bit"], + ["O8",["Array",32,"Bit"]], + ["CLK",["Named","coreir.clkIn"]], + ["ASYNCRESET",["Named","coreir.arstIn"]] + ]] + } + } + } +} +} diff --git a/nlmeans_compute.h b/nlmeans_compute.h new file mode 100644 index 000000000..6372f7c1a --- /dev/null +++ b/nlmeans_compute.h @@ -0,0 +1,241 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_1 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_2 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_3 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_x + 3), (d_s0_y + 3), (d_s0_dx + 3), (d_s0_dy + 3)) = 0.000000h +hw_uint<16> hcompute_d_stencil() { + bfloat16_t _889 = bfloat_from_bits(0 /* 0 */); + return _889; +} + +//store is: d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + bfloat16_t _d_stencil_1 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_1 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_2 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_3 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_4 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_5 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_6 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + + bfloat16_t _896 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + bfloat16_t _897 = _896 * _896; + bfloat16_t _898 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + bfloat16_t _899 = _898 * _898; + bfloat16_t _900 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + bfloat16_t _901 = _900 * _900; + bfloat16_t _902 = _d_stencil_1 + _901; + bfloat16_t _903 = _899 + _902; + bfloat16_t _904 = _897 + _903; + return _904; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_x + 3), blur_d_y_s0_y, (blur_d_y_s0_dx + 3), (blur_d_y_s0_dy + 3)) = 0.000000h +hw_uint<16> hcompute_blur_d_y_stencil() { + bfloat16_t _940 = bfloat_from_bits(0 /* 0 */); + return _940; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) = (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 6), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 5), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 4), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 3), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 2), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 1), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + d.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3))))))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<112>& d_stencil) { + bfloat16_t _blur_d_y_stencil_1 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + + bfloat16_t _d_stencil_2 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + bfloat16_t _d_stencil_3 = bfloat16_t::make_from_bits(d_stencil.extract<16, 31>()); + bfloat16_t _d_stencil_4 = bfloat16_t::make_from_bits(d_stencil.extract<32, 47>()); + bfloat16_t _d_stencil_5 = bfloat16_t::make_from_bits(d_stencil.extract<48, 63>()); + bfloat16_t _d_stencil_6 = bfloat16_t::make_from_bits(d_stencil.extract<64, 79>()); + bfloat16_t _d_stencil_7 = bfloat16_t::make_from_bits(d_stencil.extract<80, 95>()); + bfloat16_t _d_stencil_8 = bfloat16_t::make_from_bits(d_stencil.extract<96, 111>()); + + bfloat16_t _946 = _blur_d_y_stencil_1 + _d_stencil_8; + bfloat16_t _947 = _d_stencil_7 + _946; + bfloat16_t _948 = _d_stencil_6 + _947; + bfloat16_t _949 = _d_stencil_5 + _948; + bfloat16_t _950 = _d_stencil_4 + _949; + bfloat16_t _951 = _d_stencil_3 + _950; + bfloat16_t _952 = _d_stencil_2 + _951; + return _952; +} + +//store is: blur_d.stencil(blur_d_s0_x, blur_d_s0_y, (blur_d_s0_dx + 3), (blur_d_s0_dy + 3)) = 0.000000h +hw_uint<16> hcompute_blur_d_stencil() { + bfloat16_t _984 = bfloat_from_bits(0 /* 0 */); + return _984; +} + +//store is: blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) = (blur_d_y.stencil((blur_d_s1_x + 6), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 5), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 4), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 3), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 2), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 1), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + blur_d_y.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3))))))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<112>& blur_d_y_stencil) { + bfloat16_t _blur_d_stencil_1 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _blur_d_y_stencil_2 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + bfloat16_t _blur_d_y_stencil_3 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<16, 31>()); + bfloat16_t _blur_d_y_stencil_4 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<32, 47>()); + bfloat16_t _blur_d_y_stencil_5 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<48, 63>()); + bfloat16_t _blur_d_y_stencil_6 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<64, 79>()); + bfloat16_t _blur_d_y_stencil_7 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<80, 95>()); + bfloat16_t _blur_d_y_stencil_8 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<96, 111>()); + + bfloat16_t _989 = _blur_d_stencil_1 + _blur_d_y_stencil_8; + bfloat16_t _990 = _blur_d_y_stencil_7 + _989; + bfloat16_t _991 = _blur_d_y_stencil_6 + _990; + bfloat16_t _992 = _blur_d_y_stencil_5 + _991; + bfloat16_t _993 = _blur_d_y_stencil_4 + _992; + bfloat16_t _994 = _blur_d_y_stencil_3 + _993; + bfloat16_t _995 = _blur_d_y_stencil_2 + _994; + return _995; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil() { + bfloat16_t _1026 = bfloat_from_bits(0 /* 0 */); + return _1026; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 1) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + bfloat16_t _1029 = bfloat_from_bits(0 /* 0 */); + return _1029; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 2) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + bfloat16_t _1032 = bfloat_from_bits(0 /* 0 */); + return _1032; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 3) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_3() { + bfloat16_t _1035 = bfloat_from_bits(0 /* 0 */); + return _1035; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_2 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_7 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_1 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1038 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1039 = _blur_d_stencil_2 * _1038; + bfloat16_t _1040 = exp_bf16(_1039); + bfloat16_t _1041 = _1040 * _hw_input_global_wrapper_stencil_7; + bfloat16_t _1042 = _non_local_means_sum_stencil_1 + _1041; + return _1042; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_3 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_8 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_2 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1062 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1063 = _blur_d_stencil_3 * _1062; + bfloat16_t _1064 = exp_bf16(_1063); + bfloat16_t _1065 = _1064 * _hw_input_global_wrapper_stencil_8; + bfloat16_t _1066 = _non_local_means_sum_stencil_2 + _1065; + return _1066; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_6(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_4 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_9 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_3 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1086 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1087 = _blur_d_stencil_4 * _1086; + bfloat16_t _1088 = exp_bf16(_1087); + bfloat16_t _1089 = _1088 * _hw_input_global_wrapper_stencil_9; + bfloat16_t _1090 = _non_local_means_sum_stencil_3 + _1089; + return _1090; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) + exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, (non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3))*-1.414062h))) +hw_uint<16> hcompute_non_local_means_sum_stencil_7(hw_uint<16>& blur_d_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_5 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_4 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1110 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1111 = _blur_d_stencil_5 * _1110; + bfloat16_t _1112 = exp_bf16(_1111); + bfloat16_t _1113 = _non_local_means_sum_stencil_4 + _1112; + return _1113; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_5 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_6 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1126 = _non_local_means_sum_stencil_5 / _non_local_means_sum_stencil_6; + bfloat16_t _1127 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1128 = min(_1126, _1127); + bfloat16_t _1129 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1130 = max(_1128, _1129); + bfloat16_t _1131 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1132 = _1130 * _1131; + return _1132; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_7 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_8 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1149 = _non_local_means_sum_stencil_7 / _non_local_means_sum_stencil_8; + bfloat16_t _1150 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1151 = min(_1149, _1150); + bfloat16_t _1152 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1153 = max(_1151, _1152); + bfloat16_t _1154 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1155 = _1153 * _1154; + return _1155; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_10 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_9 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1172 = _non_local_means_sum_stencil_9 / _non_local_means_sum_stencil_10; + bfloat16_t _1173 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1174 = min(_1172, _1173); + bfloat16_t _1175 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1176 = max(_1174, _1175); + bfloat16_t _1177 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1178 = _1176 * _1177; + return _1178; +} + diff --git a/nlmeans_rolled_7x7_compute.h b/nlmeans_rolled_7x7_compute.h new file mode 100644 index 000000000..9e1f2e435 --- /dev/null +++ b/nlmeans_rolled_7x7_compute.h @@ -0,0 +1,241 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_1 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_2 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_3 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_dx + 3), (d_s0_dy + 3), (d_s0_x + 3), (d_s0_y + 3)) = 0.000000h +hw_uint<16> hcompute_d_stencil() { + bfloat16_t _889 = bfloat_from_bits(0 /* 0 */); + return _889; +} + +//store is: d.stencil((d_s1_dx + 3), (d_s1_dy + 3), (d_s1_x + 3), (d_s1_y + 3)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (d.stencil((d_s1_dx + 3), (d_s1_dy + 3), (d_s1_x + 3), (d_s1_y + 3)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + bfloat16_t _d_stencil_1 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_1 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_2 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_3 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_4 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_5 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_6 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + + bfloat16_t _896 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + bfloat16_t _897 = _896 * _896; + bfloat16_t _898 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + bfloat16_t _899 = _898 * _898; + bfloat16_t _900 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + bfloat16_t _901 = _900 * _900; + bfloat16_t _902 = _d_stencil_1 + _901; + bfloat16_t _903 = _899 + _902; + bfloat16_t _904 = _897 + _903; + return _904; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 3), (blur_d_y_s0_dy + 3), (blur_d_y_s0_x + 3), blur_d_y_s0_y) = 0.000000h +hw_uint<16> hcompute_blur_d_y_stencil() { + bfloat16_t _940 = bfloat_from_bits(0 /* 0 */); + return _940; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 6)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 5)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 4)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 3)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 2)) + (d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), (blur_d_y_s1_y + 1)) + (blur_d_y.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y) + d.stencil((blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3), (blur_d_y_s1_x + 3), blur_d_y_s1_y)))))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<112>& d_stencil) { + bfloat16_t _blur_d_y_stencil_1 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + + bfloat16_t _d_stencil_2 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + bfloat16_t _d_stencil_3 = bfloat16_t::make_from_bits(d_stencil.extract<16, 31>()); + bfloat16_t _d_stencil_4 = bfloat16_t::make_from_bits(d_stencil.extract<32, 47>()); + bfloat16_t _d_stencil_5 = bfloat16_t::make_from_bits(d_stencil.extract<48, 63>()); + bfloat16_t _d_stencil_6 = bfloat16_t::make_from_bits(d_stencil.extract<64, 79>()); + bfloat16_t _d_stencil_7 = bfloat16_t::make_from_bits(d_stencil.extract<80, 95>()); + bfloat16_t _d_stencil_8 = bfloat16_t::make_from_bits(d_stencil.extract<96, 111>()); + + bfloat16_t _946 = _blur_d_y_stencil_1 + _d_stencil_8; + bfloat16_t _947 = _d_stencil_7 + _946; + bfloat16_t _948 = _d_stencil_6 + _947; + bfloat16_t _949 = _d_stencil_5 + _948; + bfloat16_t _950 = _d_stencil_4 + _949; + bfloat16_t _951 = _d_stencil_3 + _950; + bfloat16_t _952 = _d_stencil_2 + _951; + return _952; +} + +//store is: blur_d.stencil((blur_d_s0_dx + 3), (blur_d_s0_dy + 3), blur_d_s0_x, blur_d_s0_y) = 0.000000h +hw_uint<16> hcompute_blur_d_stencil() { + bfloat16_t _984 = bfloat_from_bits(0 /* 0 */); + return _984; +} + +//store is: blur_d.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 6), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 5), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 4), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 3), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 2), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 3), (blur_d_s1_dy + 3), blur_d_s1_x, blur_d_s1_y)))))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<112>& blur_d_y_stencil) { + bfloat16_t _blur_d_stencil_1 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _blur_d_y_stencil_2 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + bfloat16_t _blur_d_y_stencil_3 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<16, 31>()); + bfloat16_t _blur_d_y_stencil_4 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<32, 47>()); + bfloat16_t _blur_d_y_stencil_5 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<48, 63>()); + bfloat16_t _blur_d_y_stencil_6 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<64, 79>()); + bfloat16_t _blur_d_y_stencil_7 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<80, 95>()); + bfloat16_t _blur_d_y_stencil_8 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<96, 111>()); + + bfloat16_t _989 = _blur_d_stencil_1 + _blur_d_y_stencil_8; + bfloat16_t _990 = _blur_d_y_stencil_7 + _989; + bfloat16_t _991 = _blur_d_y_stencil_6 + _990; + bfloat16_t _992 = _blur_d_y_stencil_5 + _991; + bfloat16_t _993 = _blur_d_y_stencil_4 + _992; + bfloat16_t _994 = _blur_d_y_stencil_3 + _993; + bfloat16_t _995 = _blur_d_y_stencil_2 + _994; + return _995; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil() { + bfloat16_t _1026 = bfloat_from_bits(0 /* 0 */); + return _1026; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + bfloat16_t _1029 = bfloat_from_bits(0 /* 0 */); + return _1029; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + bfloat16_t _1032 = bfloat_from_bits(0 /* 0 */); + return _1032; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_3, non_local_means_sum_s0_y_3, 3) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_3() { + bfloat16_t _1035 = bfloat_from_bits(0 /* 0 */); + return _1035; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x + 3), (non_local_means_sum_s1_s_dom_y + 3), non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 6), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_2 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_7 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_1 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1038 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1039 = _blur_d_stencil_2 * _1038; + bfloat16_t _1040 = exp_bf16(_1039); + bfloat16_t _1041 = _1040 * _hw_input_global_wrapper_stencil_7; + bfloat16_t _1042 = _non_local_means_sum_stencil_1 + _1041; + return _1042; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 3), (non_local_means_sum_s1_s_dom_y_1 + 3), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)*-1.414062h))*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 6), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_3 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_8 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_2 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1062 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1063 = _blur_d_stencil_3 * _1062; + bfloat16_t _1064 = exp_bf16(_1063); + bfloat16_t _1065 = _1064 * _hw_input_global_wrapper_stencil_8; + bfloat16_t _1066 = _non_local_means_sum_stencil_2 + _1065; + return _1066; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 3), (non_local_means_sum_s1_s_dom_y_2 + 3), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)*-1.414062h))*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 6), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_6(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_4 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_9 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_3 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1086 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1087 = _blur_d_stencil_4 * _1086; + bfloat16_t _1088 = exp_bf16(_1087); + bfloat16_t _1089 = _1088 * _hw_input_global_wrapper_stencil_9; + bfloat16_t _1090 = _non_local_means_sum_stencil_3 + _1089; + return _1090; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) + exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_3 + 3), (non_local_means_sum_s1_s_dom_y_3 + 3), non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3)*-1.414062h))) +hw_uint<16> hcompute_non_local_means_sum_stencil_7(hw_uint<16>& blur_d_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_5 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_4 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1110 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1111 = _blur_d_stencil_5 * _1110; + bfloat16_t _1112 = exp_bf16(_1111); + bfloat16_t _1113 = _non_local_means_sum_stencil_4 + _1112; + return _1113; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_5 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_6 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1126 = _non_local_means_sum_stencil_5 / _non_local_means_sum_stencil_6; + bfloat16_t _1127 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1128 = min(_1126, _1127); + bfloat16_t _1129 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1130 = max(_1128, _1129); + bfloat16_t _1131 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1132 = _1130 * _1131; + return _1132; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_7 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_8 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1149 = _non_local_means_sum_stencil_7 / _non_local_means_sum_stencil_8; + bfloat16_t _1150 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1151 = min(_1149, _1150); + bfloat16_t _1152 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1153 = max(_1151, _1152); + bfloat16_t _1154 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1155 = _1153 * _1154; + return _1155; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_10 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_9 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1172 = _non_local_means_sum_stencil_9 / _non_local_means_sum_stencil_10; + bfloat16_t _1173 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1174 = min(_1172, _1173); + bfloat16_t _1175 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1176 = max(_1174, _1175); + bfloat16_t _1177 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1178 = _1176 * _1177; + return _1178; +} + diff --git a/nlmeans_rolled_compute.h b/nlmeans_rolled_compute.h new file mode 100644 index 000000000..a0226579a --- /dev/null +++ b/nlmeans_rolled_compute.h @@ -0,0 +1,229 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_1 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_2 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_3 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = 0.000000h +hw_uint<16> hcompute_d_stencil() { + bfloat16_t _889 = bfloat_from_bits(0 /* 0 */); + return _889; +} + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + bfloat16_t _d_stencil_1 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_1 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_2 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_3 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_4 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_5 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_6 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + + bfloat16_t _896 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + bfloat16_t _897 = _896 * _896; + bfloat16_t _898 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + bfloat16_t _899 = _898 * _898; + bfloat16_t _900 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + bfloat16_t _901 = _900 * _900; + bfloat16_t _902 = _d_stencil_1 + _901; + bfloat16_t _903 = _899 + _902; + bfloat16_t _904 = _897 + _903; + return _904; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = 0.000000h +hw_uint<16> hcompute_blur_d_y_stencil() { + bfloat16_t _940 = bfloat_from_bits(0 /* 0 */); + return _940; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<64>& d_stencil) { + bfloat16_t _blur_d_y_stencil_1 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + + bfloat16_t _d_stencil_2 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + bfloat16_t _d_stencil_3 = bfloat16_t::make_from_bits(d_stencil.extract<16, 31>()); + bfloat16_t _d_stencil_4 = bfloat16_t::make_from_bits(d_stencil.extract<32, 47>()); + bfloat16_t _d_stencil_5 = bfloat16_t::make_from_bits(d_stencil.extract<48, 63>()); + + bfloat16_t _946 = _blur_d_y_stencil_1 + _d_stencil_5; + bfloat16_t _947 = _d_stencil_4 + _946; + bfloat16_t _948 = _d_stencil_3 + _947; + bfloat16_t _949 = _d_stencil_2 + _948; + return _949; +} + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = 0.000000h +hw_uint<16> hcompute_blur_d_stencil() { + bfloat16_t _969 = bfloat_from_bits(0 /* 0 */); + return _969; +} + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<64>& blur_d_y_stencil) { + bfloat16_t _blur_d_stencil_1 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _blur_d_y_stencil_2 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + bfloat16_t _blur_d_y_stencil_3 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<16, 31>()); + bfloat16_t _blur_d_y_stencil_4 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<32, 47>()); + bfloat16_t _blur_d_y_stencil_5 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<48, 63>()); + + bfloat16_t _974 = _blur_d_stencil_1 + _blur_d_y_stencil_5; + bfloat16_t _975 = _blur_d_y_stencil_4 + _974; + bfloat16_t _976 = _blur_d_y_stencil_3 + _975; + bfloat16_t _977 = _blur_d_y_stencil_2 + _976; + return _977; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil() { + bfloat16_t _996 = bfloat_from_bits(0 /* 0 */); + return _996; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + bfloat16_t _999 = bfloat_from_bits(0 /* 0 */); + return _999; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + bfloat16_t _1002 = bfloat_from_bits(0 /* 0 */); + return _1002; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_3, non_local_means_sum_s0_y_3, 3) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_3() { + bfloat16_t _1005 = bfloat_from_bits(0 /* 0 */); + return _1005; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)*-1.414062h))*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_2 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_7 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_1 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1008 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1009 = _blur_d_stencil_2 * _1008; + bfloat16_t _1010 = exp_bf16(_1009); + bfloat16_t _1011 = _1010 * _hw_input_global_wrapper_stencil_7; + bfloat16_t _1012 = _non_local_means_sum_stencil_1 + _1011; + return _1012; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)*-1.414062h))*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_3 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_8 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_2 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1032 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1033 = _blur_d_stencil_3 * _1032; + bfloat16_t _1034 = exp_bf16(_1033); + bfloat16_t _1035 = _1034 * _hw_input_global_wrapper_stencil_8; + bfloat16_t _1036 = _non_local_means_sum_stencil_2 + _1035; + return _1036; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)*-1.414062h))*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_6(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_4 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_9 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_3 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1056 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1057 = _blur_d_stencil_4 * _1056; + bfloat16_t _1058 = exp_bf16(_1057); + bfloat16_t _1059 = _1058 * _hw_input_global_wrapper_stencil_9; + bfloat16_t _1060 = _non_local_means_sum_stencil_3 + _1059; + return _1060; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) + exp_bf16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_3 + 2), (non_local_means_sum_s1_s_dom_y_3 + 2), non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3)*-1.414062h))) +hw_uint<16> hcompute_non_local_means_sum_stencil_7(hw_uint<16>& blur_d_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_5 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_4 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1080 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1081 = _blur_d_stencil_5 * _1080; + bfloat16_t _1082 = exp_bf16(_1081); + bfloat16_t _1083 = _non_local_means_sum_stencil_4 + _1082; + return _1083; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_5 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_6 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1096 = _non_local_means_sum_stencil_5 / _non_local_means_sum_stencil_6; + bfloat16_t _1097 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1098 = min(_1096, _1097); + bfloat16_t _1099 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1100 = max(_1098, _1099); + bfloat16_t _1101 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1102 = _1100 * _1101; + return _1102; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_7 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_8 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1119 = _non_local_means_sum_stencil_7 / _non_local_means_sum_stencil_8; + bfloat16_t _1120 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1121 = min(_1119, _1120); + bfloat16_t _1122 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1123 = max(_1121, _1122); + bfloat16_t _1124 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1125 = _1123 * _1124; + return _1125; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_10 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_9 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1142 = _non_local_means_sum_stencil_9 / _non_local_means_sum_stencil_10; + bfloat16_t _1143 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1144 = min(_1142, _1143); + bfloat16_t _1145 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1146 = max(_1144, _1145); + bfloat16_t _1147 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1148 = _1146 * _1147; + return _1148; +} + diff --git a/nlmeans_rolled_int_compute.h b/nlmeans_rolled_int_compute.h new file mode 100644 index 000000000..7fde0f0d5 --- /dev/null +++ b/nlmeans_rolled_int_compute.h @@ -0,0 +1,226 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_2 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_3 = (uint16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = (uint16)0 +hw_uint<16> hcompute_d_stencil() { + uint16_t _679 = (uint16_t)(0); + return _679; +} + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + ((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + uint16_t _d_stencil_1 = (uint16_t) (d_stencil.extract<0, 15>()); + + uint16_t _hw_input_global_wrapper_stencil_1 = (uint16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + uint16_t _hw_input_global_wrapper_stencil_2 = (uint16_t) (hw_input_global_wrapper_stencil.extract<16, 31>()); + uint16_t _hw_input_global_wrapper_stencil_3 = (uint16_t) (hw_input_global_wrapper_stencil.extract<32, 47>()); + uint16_t _hw_input_global_wrapper_stencil_4 = (uint16_t) (hw_input_global_wrapper_stencil.extract<48, 63>()); + uint16_t _hw_input_global_wrapper_stencil_5 = (uint16_t) (hw_input_global_wrapper_stencil.extract<64, 79>()); + uint16_t _hw_input_global_wrapper_stencil_6 = (uint16_t) (hw_input_global_wrapper_stencil.extract<80, 95>()); + + uint16_t _686 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + uint16_t _687 = _686 * _686; + uint16_t _688 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + uint16_t _689 = _688 * _688; + uint16_t _690 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + uint16_t _691 = _690 * _690; + uint16_t _692 = _689 + _691; + uint16_t _693 = _d_stencil_1 + _692; + uint16_t _694 = _687 + _693; + return _694; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = (uint16)0 +hw_uint<16> hcompute_blur_d_y_stencil() { + uint16_t _730 = (uint16_t)(0); + return _730; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<64>& d_stencil) { + uint16_t _blur_d_y_stencil_1 = (uint16_t) (blur_d_y_stencil.extract<0, 15>()); + + uint16_t _d_stencil_2 = (uint16_t) (d_stencil.extract<0, 15>()); + uint16_t _d_stencil_3 = (uint16_t) (d_stencil.extract<16, 31>()); + uint16_t _d_stencil_4 = (uint16_t) (d_stencil.extract<32, 47>()); + uint16_t _d_stencil_5 = (uint16_t) (d_stencil.extract<48, 63>()); + + uint16_t _736 = _d_stencil_4 + _d_stencil_5; + uint16_t _737 = _d_stencil_3 + _736; + uint16_t _738 = _blur_d_y_stencil_1 + _737; + uint16_t _739 = _d_stencil_2 + _738; + return _739; +} + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = (uint16)0 +hw_uint<16> hcompute_blur_d_stencil() { + uint16_t _759 = (uint16_t)(0); + return _759; +} + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<64>& blur_d_y_stencil) { + uint16_t _blur_d_stencil_1 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + uint16_t _blur_d_y_stencil_2 = (uint16_t) (blur_d_y_stencil.extract<0, 15>()); + uint16_t _blur_d_y_stencil_3 = (uint16_t) (blur_d_y_stencil.extract<16, 31>()); + uint16_t _blur_d_y_stencil_4 = (uint16_t) (blur_d_y_stencil.extract<32, 47>()); + uint16_t _blur_d_y_stencil_5 = (uint16_t) (blur_d_y_stencil.extract<48, 63>()); + + uint16_t _764 = _blur_d_y_stencil_4 + _blur_d_y_stencil_5; + uint16_t _765 = _blur_d_y_stencil_3 + _764; + uint16_t _766 = _blur_d_stencil_1 + _765; + uint16_t _767 = _blur_d_y_stencil_2 + _766; + return _767; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil() { + int16_t _786 = (int16_t)(0); + return _786; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + int16_t _789 = (int16_t)(0); + return _789; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + int16_t _792 = (int16_t)(0); + return _792; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_3, non_local_means_sum_s0_y_3, 3) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_3() { + int16_t _795 = (int16_t)(0); + return _795; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + int16(((blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)*hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4)))*(uint16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + uint16_t _blur_d_stencil_2 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + uint16_t _hw_input_global_wrapper_stencil_7 = (uint16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_1 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + uint16_t _798 = _blur_d_stencil_2 * _hw_input_global_wrapper_stencil_7; + uint16_t _799 = (uint16_t)(16); + uint16_t _800 = _798 * _799; + int16_t _801 = (int16_t)(_800); + int16_t _802 = _non_local_means_sum_stencil_1 + _801; + return _802; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + int16(((blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)*hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4)))*(uint16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + uint16_t _blur_d_stencil_3 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + uint16_t _hw_input_global_wrapper_stencil_8 = (uint16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_2 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + uint16_t _822 = _blur_d_stencil_3 * _hw_input_global_wrapper_stencil_8; + uint16_t _823 = (uint16_t)(16); + uint16_t _824 = _822 * _823; + int16_t _825 = (int16_t)(_824); + int16_t _826 = _non_local_means_sum_stencil_2 + _825; + return _826; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + int16(((blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)*hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4)))*(uint16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_6(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + uint16_t _blur_d_stencil_4 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + uint16_t _hw_input_global_wrapper_stencil_9 = (uint16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_3 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + uint16_t _846 = _blur_d_stencil_4 * _hw_input_global_wrapper_stencil_9; + uint16_t _847 = (uint16_t)(16); + uint16_t _848 = _846 * _847; + int16_t _849 = (int16_t)(_848); + int16_t _850 = _non_local_means_sum_stencil_3 + _849; + return _850; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3, 3) + int16((blur_d.stencil((non_local_means_sum_s1_s_dom_x_3 + 2), (non_local_means_sum_s1_s_dom_y_3 + 2), non_local_means_sum_s1_x_3, non_local_means_sum_s1_y_3)*(uint16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_7(hw_uint<16>& blur_d_stencil, hw_uint<16>& non_local_means_sum_stencil) { + uint16_t _blur_d_stencil_5 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_4 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + uint16_t _870 = (uint16_t)(16); + uint16_t _871 = _blur_d_stencil_5 * _870; + int16_t _872 = (int16_t)(_871); + int16_t _873 = _non_local_means_sum_stencil_4 + _872; + return _873; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)*non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), (int16)255), (int16)0)) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<32>& non_local_means_sum_stencil) { + int16_t _non_local_means_sum_stencil_5 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + int16_t _non_local_means_sum_stencil_6 = (int16_t) (non_local_means_sum_stencil.extract<16, 31>()); + + int16_t _886 = _non_local_means_sum_stencil_5 * _non_local_means_sum_stencil_6; + int16_t _887 = (int16_t)(255); + int16_t _888 = min(_886, _887); + int16_t _889 = (int16_t)(0); + int16_t _890 = max(_888, _889); + uint16_t _891 = (uint16_t)(_890); + return _891; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)*non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), (int16)255), (int16)0)) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<32>& non_local_means_sum_stencil) { + int16_t _non_local_means_sum_stencil_7 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + int16_t _non_local_means_sum_stencil_8 = (int16_t) (non_local_means_sum_stencil.extract<16, 31>()); + + int16_t _906 = _non_local_means_sum_stencil_7 * _non_local_means_sum_stencil_8; + int16_t _907 = (int16_t)(255); + int16_t _908 = min(_906, _907); + int16_t _909 = (int16_t)(0); + int16_t _910 = max(_908, _909); + uint16_t _911 = (uint16_t)(_910); + return _911; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = uint16(max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)*non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), (int16)255), (int16)0)) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<32>& non_local_means_sum_stencil) { + int16_t _non_local_means_sum_stencil_10 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + int16_t _non_local_means_sum_stencil_9 = (int16_t) (non_local_means_sum_stencil.extract<16, 31>()); + + int16_t _926 = _non_local_means_sum_stencil_9 * _non_local_means_sum_stencil_10; + int16_t _927 = (int16_t)(255); + int16_t _928 = min(_926, _927); + int16_t _929 = (int16_t)(0); + int16_t _930 = max(_928, _929); + uint16_t _931 = (uint16_t)(_930); + return _931; +} + diff --git a/nlmeans_simple_blur_compute.h b/nlmeans_simple_blur_compute.h new file mode 100644 index 000000000..987f824bc --- /dev/null +++ b/nlmeans_simple_blur_compute.h @@ -0,0 +1,227 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_1 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_2 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_3 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = (int16)0 +hw_uint<16> hcompute_d_stencil() { + int16_t _679 = (int16_t)(0); + return _679; +} + +hw_uint<16> hcompute_d_stencil_2(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_2 = (int16_t) (hw_input_stencil.extract<0, 15>()); + return _hw_input_stencil_2; +} + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + ((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + int16_t _d_stencil_1 = (int16_t) (d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_1 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_stencil_2 = (int16_t) (hw_input_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_stencil_3 = (int16_t) (hw_input_global_wrapper_stencil.extract<32, 47>()); + int16_t _hw_input_global_wrapper_stencil_4 = (int16_t) (hw_input_global_wrapper_stencil.extract<48, 63>()); + int16_t _hw_input_global_wrapper_stencil_5 = (int16_t) (hw_input_global_wrapper_stencil.extract<64, 79>()); + int16_t _hw_input_global_wrapper_stencil_6 = (int16_t) (hw_input_global_wrapper_stencil.extract<80, 95>()); + + int16_t _686 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + int16_t _687 = _686 * _686; + int16_t _688 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + int16_t _689 = _688 * _688; + int16_t _690 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + int16_t _691 = _690 * _690; + int16_t _692 = _689 + _691; + int16_t _693 = _d_stencil_1 + _692; + int16_t _694 = _687 + _693; + return _694; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = (int16)0 +hw_uint<16> hcompute_blur_d_y_stencil() { + int16_t _730 = (int16_t)(0); + return _730; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<64>& d_stencil) { + int16_t _blur_d_y_stencil_1 = (int16_t) (blur_d_y_stencil.extract<0, 15>()); + + int16_t _d_stencil_2 = (int16_t) (d_stencil.extract<0, 15>()); + int16_t _d_stencil_3 = (int16_t) (d_stencil.extract<16, 31>()); + int16_t _d_stencil_4 = (int16_t) (d_stencil.extract<32, 47>()); + int16_t _d_stencil_5 = (int16_t) (d_stencil.extract<48, 63>()); + + int16_t _736 = _d_stencil_4 + _d_stencil_5; + int16_t _737 = _d_stencil_3 + _736; + int16_t _738 = _blur_d_y_stencil_1 + _737; + int16_t _739 = _d_stencil_2 + _738; + return _739; +} + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = (int16)0 +hw_uint<16> hcompute_blur_d_stencil() { + int16_t _759 = (int16_t)(0); + return _759; +} + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<64>& blur_d_y_stencil) { + int16_t _blur_d_stencil_1 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _blur_d_y_stencil_2 = (int16_t) (blur_d_y_stencil.extract<0, 15>()); + int16_t _blur_d_y_stencil_3 = (int16_t) (blur_d_y_stencil.extract<16, 31>()); + int16_t _blur_d_y_stencil_4 = (int16_t) (blur_d_y_stencil.extract<32, 47>()); + int16_t _blur_d_y_stencil_5 = (int16_t) (blur_d_y_stencil.extract<48, 63>()); + + int16_t _764 = _blur_d_y_stencil_4 + _blur_d_y_stencil_5; + int16_t _765 = _blur_d_y_stencil_3 + _764; + int16_t _766 = _blur_d_stencil_1 + _765; + int16_t _767 = _blur_d_y_stencil_2 + _766; + return _767; +} + +//store is: non_local_means_div.stencil(non_local_means_div_s0_x, non_local_means_div_s0_y) = (int16)0 +hw_uint<16> hcompute_non_local_means_div_stencil() { + int16_t _786 = (int16_t)(0); + return _786; +} + +//store is: non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) = (non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) + (blur_d.stencil((non_local_means_div_s1_s_dom_x + 2), (non_local_means_div_s1_s_dom_y + 2), non_local_means_div_s1_x, non_local_means_div_s1_y)/(int16)16)) +hw_uint<16> hcompute_non_local_means_div_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<16>& non_local_means_div_stencil) { + uint16_t _blur_d_stencil_2 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _non_local_means_div_stencil_1 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _789 = (int16_t)(4); + uint16_t _790 = _blur_d_stencil_2 >> _789; + int16_t _791 = _non_local_means_div_stencil_1 + (int16_t)_790; + return _791; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil() { + int16_t _802 = (int16_t)(0); + return _802; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + int16_t _805 = (int16_t)(0); + return _805; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + int16_t _808 = (int16_t)(0); + return _808; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_3(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _blur_d_stencil_3 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_7 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_1 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _811 = (int16_t)(4); + int16_t _812 = _blur_d_stencil_3 >> _811; + int16_t _813 = _hw_input_global_wrapper_stencil_7 * _812; + int16_t _814 = _non_local_means_sum_stencil_1 + _813; + return _814; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _blur_d_stencil_4 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_8 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_2 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _832 = (int16_t)(4); + int16_t _833 = _blur_d_stencil_4 >> _832; + int16_t _834 = _hw_input_global_wrapper_stencil_8 * _833; + int16_t _835 = _non_local_means_sum_stencil_2 + _834; + return _835; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _blur_d_stencil_5 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_9 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_3 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _853 = (int16_t)(4); + int16_t _854 = _blur_d_stencil_5 >> _853; + int16_t _855 = _hw_input_global_wrapper_stencil_9 * _854; + int16_t _856 = _non_local_means_sum_stencil_3 + _855; + return _856; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_2 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_4 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _874 = _non_local_means_sum_stencil_4 - _non_local_means_div_stencil_2; + int16_t _875 = (int16_t)(255); + int16_t _876 = min(_874, _875); + int16_t _877 = (int16_t)(0); + int16_t _878 = max(_876, _877); + return _878; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_3 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_5 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _891 = _non_local_means_sum_stencil_5 - _non_local_means_div_stencil_3; + int16_t _892 = (int16_t)(255); + int16_t _893 = min(_891, _892); + int16_t _894 = (int16_t)(0); + int16_t _895 = max(_893, _894); + return _895; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_4 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_6 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _908 = _non_local_means_sum_stencil_6 - _non_local_means_div_stencil_4; + int16_t _909 = (int16_t)(255); + int16_t _910 = min(_908, _909); + int16_t _911 = (int16_t)(0); + int16_t _912 = max(_910, _911); + return _912; +} + diff --git a/nlmeans_simple_compute.h b/nlmeans_simple_compute.h new file mode 100644 index 000000000..135f8628a --- /dev/null +++ b/nlmeans_simple_compute.h @@ -0,0 +1,222 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_1 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_2 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_3 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = (int16)0 +hw_uint<16> hcompute_d_stencil() { + int16_t _679 = (int16_t)(0); + return _679; +} + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + ((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + int16_t _d_stencil_1 = (int16_t) (d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_1 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_stencil_2 = (int16_t) (hw_input_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_stencil_3 = (int16_t) (hw_input_global_wrapper_stencil.extract<32, 47>()); + int16_t _hw_input_global_wrapper_stencil_4 = (int16_t) (hw_input_global_wrapper_stencil.extract<48, 63>()); + int16_t _hw_input_global_wrapper_stencil_5 = (int16_t) (hw_input_global_wrapper_stencil.extract<64, 79>()); + int16_t _hw_input_global_wrapper_stencil_6 = (int16_t) (hw_input_global_wrapper_stencil.extract<80, 95>()); + + int16_t _686 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + int16_t _687 = _686 * _686; + int16_t _688 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + int16_t _689 = _688 * _688; + int16_t _690 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + int16_t _691 = _690 * _690; + int16_t _692 = _689 + _691; + int16_t _693 = _d_stencil_1 + _692; + int16_t _694 = _687 + _693; + return _694; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = (int16)0 +hw_uint<16> hcompute_blur_d_y_stencil() { + int16_t _730 = (int16_t)(0); + return _730; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<64>& d_stencil) { + int16_t _blur_d_y_stencil_1 = (int16_t) (blur_d_y_stencil.extract<0, 15>()); + + int16_t _d_stencil_2 = (int16_t) (d_stencil.extract<0, 15>()); + int16_t _d_stencil_3 = (int16_t) (d_stencil.extract<16, 31>()); + int16_t _d_stencil_4 = (int16_t) (d_stencil.extract<32, 47>()); + int16_t _d_stencil_5 = (int16_t) (d_stencil.extract<48, 63>()); + + int16_t _736 = _d_stencil_4 + _d_stencil_5; + int16_t _737 = _d_stencil_3 + _736; + int16_t _738 = _blur_d_y_stencil_1 + _737; + int16_t _739 = _d_stencil_2 + _738; + return _739; +} + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = (int16)0 +hw_uint<16> hcompute_blur_d_stencil() { + int16_t _759 = (int16_t)(0); + return _759; +} + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<64>& blur_d_y_stencil) { + int16_t _blur_d_stencil_1 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _blur_d_y_stencil_2 = (int16_t) (blur_d_y_stencil.extract<0, 15>()); + int16_t _blur_d_y_stencil_3 = (int16_t) (blur_d_y_stencil.extract<16, 31>()); + int16_t _blur_d_y_stencil_4 = (int16_t) (blur_d_y_stencil.extract<32, 47>()); + int16_t _blur_d_y_stencil_5 = (int16_t) (blur_d_y_stencil.extract<48, 63>()); + + int16_t _764 = _blur_d_y_stencil_4 + _blur_d_y_stencil_5; + int16_t _765 = _blur_d_y_stencil_3 + _764; + int16_t _766 = _blur_d_stencil_1 + _765; + int16_t _767 = _blur_d_y_stencil_2 + _766; + return _767; +} + +//store is: non_local_means_div.stencil(non_local_means_div_s0_x, non_local_means_div_s0_y) = (int16)0 +hw_uint<16> hcompute_non_local_means_div_stencil() { + int16_t _786 = (int16_t)(0); + return _786; +} + +//store is: non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) = (non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) + (blur_d.stencil((non_local_means_div_s1_s_dom_x + 2), (non_local_means_div_s1_s_dom_y + 2), non_local_means_div_s1_x, non_local_means_div_s1_y)/(int16)16)) +hw_uint<16> hcompute_non_local_means_div_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<16>& non_local_means_div_stencil) { + uint16_t _blur_d_stencil_2 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _non_local_means_div_stencil_1 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _789 = (int16_t)(4); + uint16_t _790 = _blur_d_stencil_2 >> _789; + int16_t _791 = _non_local_means_div_stencil_1 + (int16_t)_790; + return _791; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil() { + int16_t _802 = (int16_t)(0); + return _802; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + int16_t _805 = (int16_t)(0); + return _805; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + int16_t _808 = (int16_t)(0); + return _808; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_3(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + uint16_t _blur_d_stencil_3 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_7 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_1 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _811 = (int16_t)(4); + uint16_t _812 = _blur_d_stencil_3 >> _811; + int16_t _813 = _hw_input_global_wrapper_stencil_7 * (int16_t)_812; + int16_t _814 = _non_local_means_sum_stencil_1 + _813; + return _814; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + uint16_t _blur_d_stencil_4 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_8 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_2 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _832 = (int16_t)(4); + uint16_t _833 = _blur_d_stencil_4 >> _832; + int16_t _834 = _hw_input_global_wrapper_stencil_8 * (int16_t)_833; + int16_t _835 = _non_local_means_sum_stencil_2 + _834; + return _835; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + uint16_t _blur_d_stencil_5 = (uint16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_9 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_3 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _853 = (int16_t)(4); + uint16_t _854 = _blur_d_stencil_5 >> _853; + int16_t _855 = _hw_input_global_wrapper_stencil_9 * (int16_t)_854; + int16_t _856 = _non_local_means_sum_stencil_3 + _855; + return _856; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_2 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_4 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _874 = _non_local_means_sum_stencil_4 - _non_local_means_div_stencil_2; + int16_t _875 = (int16_t)(255); + int16_t _876 = min(_874, _875); + int16_t _877 = (int16_t)(0); + int16_t _878 = max(_876, _877); + return _878; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_3 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_5 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _891 = _non_local_means_sum_stencil_5 - _non_local_means_div_stencil_3; + int16_t _892 = (int16_t)(255); + int16_t _893 = min(_891, _892); + int16_t _894 = (int16_t)(0); + int16_t _895 = max(_893, _894); + return _895; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_4 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_6 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _908 = _non_local_means_sum_stencil_6 - _non_local_means_div_stencil_4; + int16_t _909 = (int16_t)(255); + int16_t _910 = min(_908, _909); + int16_t _911 = (int16_t)(0); + int16_t _912 = max(_910, _911); + return _912; +} + diff --git a/nlmeans_simple_trunc_compute.h b/nlmeans_simple_trunc_compute.h new file mode 100644 index 000000000..3af533288 --- /dev/null +++ b/nlmeans_simple_trunc_compute.h @@ -0,0 +1,227 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_1 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_2 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_3 = (int16_t) (hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_dx + 2), (d_s0_dy + 2), (d_s0_x + 2), (d_s0_y + 2)) = (int16)0 +hw_uint<16> hcompute_d_stencil() { + int16_t _679 = (int16_t)(0); + return _679; +} + +hw_uint<16> hcompute_d_stencil_2(hw_uint<16>& hw_input_stencil) { + int16_t _hw_input_stencil_2 = (int16_t) (hw_input_stencil.extract<0, 15>()); + return _hw_input_stencil_2; +} + +//store is: d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) = (((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_dx + 2), (d_s1_dy + 2), (d_s1_x + 2), (d_s1_y + 2)) + (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + ((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + int16_t _d_stencil_1 = (int16_t) (d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_1 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + int16_t _hw_input_global_wrapper_stencil_2 = (int16_t) (hw_input_global_wrapper_stencil.extract<16, 31>()); + int16_t _hw_input_global_wrapper_stencil_3 = (int16_t) (hw_input_global_wrapper_stencil.extract<32, 47>()); + int16_t _hw_input_global_wrapper_stencil_4 = (int16_t) (hw_input_global_wrapper_stencil.extract<48, 63>()); + int16_t _hw_input_global_wrapper_stencil_5 = (int16_t) (hw_input_global_wrapper_stencil.extract<64, 79>()); + int16_t _hw_input_global_wrapper_stencil_6 = (int16_t) (hw_input_global_wrapper_stencil.extract<80, 95>()); + + int16_t _686 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + int16_t _687 = _686 * _686; + int16_t _688 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + int16_t _689 = _688 * _688; + int16_t _690 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + int16_t _691 = _690 * _690; + int16_t _692 = _689 + _691; + int16_t _693 = _d_stencil_1 + _692; + int16_t _694 = _687 + _693; + return _694; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2), (blur_d_y_s0_x + 2), blur_d_y_s0_y) = (int16)0 +hw_uint<16> hcompute_blur_d_y_stencil() { + int16_t _730 = (int16_t)(0); + return _730; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) = (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (blur_d_y.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), blur_d_y_s1_y) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1)) + (d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3)) + d.stencil((blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2), (blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2)))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<64>& d_stencil) { + int16_t _blur_d_y_stencil_1 = (int16_t) (blur_d_y_stencil.extract<0, 15>()); + + int16_t _d_stencil_2 = (int16_t) (d_stencil.extract<0, 15>()); + int16_t _d_stencil_3 = (int16_t) (d_stencil.extract<16, 31>()); + int16_t _d_stencil_4 = (int16_t) (d_stencil.extract<32, 47>()); + int16_t _d_stencil_5 = (int16_t) (d_stencil.extract<48, 63>()); + + int16_t _736 = _d_stencil_4 + _d_stencil_5; + int16_t _737 = _d_stencil_3 + _736; + int16_t _738 = _blur_d_y_stencil_1 + _737; + int16_t _739 = _d_stencil_2 + _738; + return _739; +} + +//store is: blur_d.stencil((blur_d_s0_dx + 2), (blur_d_s0_dy + 2), blur_d_s0_x, blur_d_s0_y) = (int16)0 +hw_uint<16> hcompute_blur_d_stencil() { + int16_t _759 = (int16_t)(0); + return _759; +} + +//store is: blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) = (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), blur_d_s1_x, blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 1), blur_d_s1_y) + (blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 3), blur_d_s1_y) + blur_d_y.stencil((blur_d_s1_dx + 2), (blur_d_s1_dy + 2), (blur_d_s1_x + 2), blur_d_s1_y))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<64>& blur_d_y_stencil) { + int16_t _blur_d_stencil_1 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _blur_d_y_stencil_2 = (int16_t) (blur_d_y_stencil.extract<0, 15>()); + int16_t _blur_d_y_stencil_3 = (int16_t) (blur_d_y_stencil.extract<16, 31>()); + int16_t _blur_d_y_stencil_4 = (int16_t) (blur_d_y_stencil.extract<32, 47>()); + int16_t _blur_d_y_stencil_5 = (int16_t) (blur_d_y_stencil.extract<48, 63>()); + + int16_t _764 = _blur_d_y_stencil_4 + _blur_d_y_stencil_5; + int16_t _765 = _blur_d_y_stencil_3 + _764; + int16_t _766 = _blur_d_stencil_1 + _765; + int16_t _767 = _blur_d_y_stencil_2 + _766; + return _767; +} + +//store is: non_local_means_div.stencil(non_local_means_div_s0_x, non_local_means_div_s0_y) = (int16)0 +hw_uint<16> hcompute_non_local_means_div_stencil() { + int16_t _786 = (int16_t)(0); + return _786; +} + +//store is: non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) = (non_local_means_div.stencil(non_local_means_div_s1_x, non_local_means_div_s1_y) + (blur_d.stencil((non_local_means_div_s1_s_dom_x + 2), (non_local_means_div_s1_s_dom_y + 2), non_local_means_div_s1_x, non_local_means_div_s1_y)/(int16)16)) +hw_uint<16> hcompute_non_local_means_div_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<16>& non_local_means_div_stencil) { + int16_t _blur_d_stencil_2 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _non_local_means_div_stencil_1 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _789 = (int16_t)(4); + int16_t _790 = _blur_d_stencil_2 >> _789; + int16_t _791 = _non_local_means_div_stencil_1 + _790; + return _791; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil() { + int16_t _802 = (int16_t)(0); + return _802; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_1, non_local_means_sum_s0_y_1, 1) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + int16_t _805 = (int16_t)(0); + return _805; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x_2, non_local_means_sum_s0_y_2, 2) = (int16)0 +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + int16_t _808 = (int16_t)(0); + return _808; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (hw_input_global_wrapper.stencil(0, ((non_local_means_sum_s1_s_dom_x + non_local_means_sum_s1_x) + 4), ((non_local_means_sum_s1_s_dom_y + non_local_means_sum_s1_y) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x + 2), (non_local_means_sum_s1_s_dom_y + 2), non_local_means_sum_s1_x, non_local_means_sum_s1_y)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_3(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _blur_d_stencil_3 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_7 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_1 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _811 = (int16_t)(4); + int16_t _812 = _blur_d_stencil_3 >> _811; + int16_t _813 = _hw_input_global_wrapper_stencil_7 * _812; + int16_t _814 = _non_local_means_sum_stencil_1 + _813; + return _814; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1, 1) + (hw_input_global_wrapper.stencil(1, ((non_local_means_sum_s1_s_dom_x_1 + non_local_means_sum_s1_x_1) + 4), ((non_local_means_sum_s1_s_dom_y_1 + non_local_means_sum_s1_y_1) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x_1 + 2), (non_local_means_sum_s1_s_dom_y_1 + 2), non_local_means_sum_s1_x_1, non_local_means_sum_s1_y_1)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _blur_d_stencil_4 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_8 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_2 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _832 = (int16_t)(4); + int16_t _833 = _blur_d_stencil_4 >> _832; + int16_t _834 = _hw_input_global_wrapper_stencil_8 * _833; + int16_t _835 = _non_local_means_sum_stencil_2 + _834; + return _835; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2, 2) + (hw_input_global_wrapper.stencil(2, ((non_local_means_sum_s1_s_dom_x_2 + non_local_means_sum_s1_x_2) + 4), ((non_local_means_sum_s1_s_dom_y_2 + non_local_means_sum_s1_y_2) + 4))*(blur_d.stencil((non_local_means_sum_s1_s_dom_x_2 + 2), (non_local_means_sum_s1_s_dom_y_2 + 2), non_local_means_sum_s1_x_2, non_local_means_sum_s1_y_2)/(int16)16))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _blur_d_stencil_5 = (int16_t) (blur_d_stencil.extract<0, 15>()); + + int16_t _hw_input_global_wrapper_stencil_9 = (int16_t) (hw_input_global_wrapper_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_3 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _853 = (int16_t)(4); + int16_t _854 = _blur_d_stencil_5 >> _853; + int16_t _855 = _hw_input_global_wrapper_stencil_9 * _854; + int16_t _856 = _non_local_means_sum_stencil_3 + _855; + return _856; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_2 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_4 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _874 = _non_local_means_sum_stencil_4 - _non_local_means_div_stencil_2; + int16_t _875 = (int16_t)(255); + int16_t _876 = min(_874, _875); + int16_t _877 = (int16_t)(0); + int16_t _878 = max(_876, _877); + return _878; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_3 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_5 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _891 = _non_local_means_sum_stencil_5 - _non_local_means_div_stencil_3; + int16_t _892 = (int16_t)(255); + int16_t _893 = min(_891, _892); + int16_t _894 = (int16_t)(0); + int16_t _895 = max(_893, _894); + return _895; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)*non_local_means_div.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi)), (int16)255), (int16)0) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<16>& non_local_means_div_stencil, hw_uint<16>& non_local_means_sum_stencil) { + int16_t _non_local_means_div_stencil_4 = (int16_t) (non_local_means_div_stencil.extract<0, 15>()); + + int16_t _non_local_means_sum_stencil_6 = (int16_t) (non_local_means_sum_stencil.extract<0, 15>()); + + int16_t _908 = _non_local_means_sum_stencil_6 - _non_local_means_div_stencil_4; + int16_t _909 = (int16_t)(255); + int16_t _910 = min(_908, _909); + int16_t _911 = (int16_t)(0); + int16_t _912 = max(_910, _911); + return _912; +} + diff --git a/nlmeans_small_compute.h b/nlmeans_small_compute.h new file mode 100644 index 000000000..f44620867 --- /dev/null +++ b/nlmeans_small_compute.h @@ -0,0 +1,329 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_1 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_2 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 4), (hw_input_global_wrapper_s0_y + 4)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_3 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_x + 2), (d_s0_y + 2), (d_s0_dx + 2), (d_s0_dy + 2)) = 0.000000h +hw_uint<16> hcompute_d_stencil() { + bfloat16_t _889 = bfloat_from_bits(0 /* 0 */); + return _889; +} + +//store is: d.stencil((d_s1_x + 2), (d_s1_y + 2), (d_s1_dx + 2), (d_s1_dy + 2)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))) + (d.stencil((d_s1_x + 2), (d_s1_y + 2), (d_s1_dx + 2), (d_s1_dy + 2)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 4), (d_s1_y + 4)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 4), ((d_s1_dy + d_s1_y) + 4))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + bfloat16_t _d_stencil_1 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_1 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_2 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_3 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_4 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_5 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_6 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + + bfloat16_t _896 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + bfloat16_t _897 = _896 * _896; + bfloat16_t _898 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + bfloat16_t _899 = _898 * _898; + bfloat16_t _900 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + bfloat16_t _901 = _900 * _900; + bfloat16_t _902 = _d_stencil_1 + _901; + bfloat16_t _903 = _899 + _902; + bfloat16_t _904 = _897 + _903; + return _904; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_x + 2), blur_d_y_s0_y, (blur_d_y_s0_dx + 2), (blur_d_y_s0_dy + 2)) = 0.000000h +hw_uint<16> hcompute_blur_d_y_stencil() { + bfloat16_t _940 = bfloat_from_bits(0 /* 0 */); + return _940; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_x + 2), blur_d_y_s1_y, (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) = (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 4), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 3), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 2), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (d.stencil((blur_d_y_s1_x + 2), (blur_d_y_s1_y + 1), (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + (blur_d_y.stencil((blur_d_y_s1_x + 2), blur_d_y_s1_y, (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2)) + d.stencil((blur_d_y_s1_x + 2), blur_d_y_s1_y, (blur_d_y_s1_dx + 2), (blur_d_y_s1_dy + 2))))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<80>& d_stencil) { + bfloat16_t _blur_d_y_stencil_1 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + + bfloat16_t _d_stencil_2 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + bfloat16_t _d_stencil_3 = bfloat16_t::make_from_bits(d_stencil.extract<16, 31>()); + bfloat16_t _d_stencil_4 = bfloat16_t::make_from_bits(d_stencil.extract<32, 47>()); + bfloat16_t _d_stencil_5 = bfloat16_t::make_from_bits(d_stencil.extract<48, 63>()); + bfloat16_t _d_stencil_6 = bfloat16_t::make_from_bits(d_stencil.extract<64, 79>()); + + bfloat16_t _946 = _blur_d_y_stencil_1 + _d_stencil_6; + bfloat16_t _947 = _d_stencil_5 + _946; + bfloat16_t _948 = _d_stencil_4 + _947; + bfloat16_t _949 = _d_stencil_3 + _948; + bfloat16_t _950 = _d_stencil_2 + _949; + return _950; +} + +//store is: blur_d.stencil(blur_d_s0_x, blur_d_s0_y, (blur_d_s0_dx + 2), (blur_d_s0_dy + 2)) = 0.000000h +hw_uint<16> hcompute_blur_d_stencil() { + bfloat16_t _974 = bfloat_from_bits(0 /* 0 */); + return _974; +} + +//store is: blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) = (blur_d_y.stencil((blur_d_s1_x + 4), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d_y.stencil((blur_d_s1_x + 3), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d_y.stencil((blur_d_s1_x + 2), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d_y.stencil((blur_d_s1_x + 1), blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + (blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2)) + blur_d_y.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 2), (blur_d_s1_dy + 2))))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<80>& blur_d_y_stencil) { + bfloat16_t _blur_d_stencil_1 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _blur_d_y_stencil_2 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + bfloat16_t _blur_d_y_stencil_3 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<16, 31>()); + bfloat16_t _blur_d_y_stencil_4 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<32, 47>()); + bfloat16_t _blur_d_y_stencil_5 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<48, 63>()); + bfloat16_t _blur_d_y_stencil_6 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<64, 79>()); + + bfloat16_t _979 = _blur_d_stencil_1 + _blur_d_y_stencil_6; + bfloat16_t _980 = _blur_d_y_stencil_5 + _979; + bfloat16_t _981 = _blur_d_y_stencil_4 + _980; + bfloat16_t _982 = _blur_d_y_stencil_3 + _981; + bfloat16_t _983 = _blur_d_y_stencil_2 + _982; + return _983; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil() { + bfloat16_t _1006 = bfloat_from_bits(0 /* 0 */); + return _1006; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 1) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + bfloat16_t _1009 = bfloat_from_bits(0 /* 0 */); + return _1009; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 2) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + bfloat16_t _1012 = bfloat_from_bits(0 /* 0 */); + return _1012; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 3) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_3() { + bfloat16_t _1015 = bfloat_from_bits(0 /* 0 */); + return _1015; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_2 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_7 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_1 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1018 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1019 = _blur_d_stencil_2 * _1018; + bfloat16_t _1020 = exp_bf16(_1019); + bfloat16_t _1021 = _1020 * _hw_input_global_wrapper_stencil_7; + bfloat16_t _1022 = _non_local_means_sum_stencil_1 + _1021; + return _1022; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_3 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_8 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_2 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1038 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1039 = _blur_d_stencil_3 * _1038; + bfloat16_t _1040 = exp_bf16(_1039); + bfloat16_t _1041 = _1040 * _hw_input_global_wrapper_stencil_8; + bfloat16_t _1042 = _non_local_means_sum_stencil_2 + _1041; + return _1042; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) = (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6)))) +hw_uint<16> hcompute_non_local_means_sum_stencil_6(hw_uint<16>& blur_d_stencil, hw_uint<16>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_4 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_9 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + + bfloat16_t _non_local_means_sum_stencil_3 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1058 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1059 = _blur_d_stencil_4 * _1058; + bfloat16_t _1060 = exp_bf16(_1059); + bfloat16_t _1061 = _1060 * _hw_input_global_wrapper_stencil_9; + bfloat16_t _1062 = _non_local_means_sum_stencil_3 + _1061; + return _1062; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) = (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h)) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) + exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))))))))))))))))))))))))))) +hw_uint<16> hcompute_non_local_means_sum_stencil_7(hw_uint<400>& blur_d_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_10 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + bfloat16_t _blur_d_stencil_11 = bfloat16_t::make_from_bits(blur_d_stencil.extract<16, 31>()); + bfloat16_t _blur_d_stencil_12 = bfloat16_t::make_from_bits(blur_d_stencil.extract<32, 47>()); + bfloat16_t _blur_d_stencil_13 = bfloat16_t::make_from_bits(blur_d_stencil.extract<48, 63>()); + bfloat16_t _blur_d_stencil_14 = bfloat16_t::make_from_bits(blur_d_stencil.extract<64, 79>()); + bfloat16_t _blur_d_stencil_15 = bfloat16_t::make_from_bits(blur_d_stencil.extract<80, 95>()); + bfloat16_t _blur_d_stencil_16 = bfloat16_t::make_from_bits(blur_d_stencil.extract<96, 111>()); + bfloat16_t _blur_d_stencil_17 = bfloat16_t::make_from_bits(blur_d_stencil.extract<112, 127>()); + bfloat16_t _blur_d_stencil_18 = bfloat16_t::make_from_bits(blur_d_stencil.extract<128, 143>()); + bfloat16_t _blur_d_stencil_19 = bfloat16_t::make_from_bits(blur_d_stencil.extract<144, 159>()); + bfloat16_t _blur_d_stencil_20 = bfloat16_t::make_from_bits(blur_d_stencil.extract<160, 175>()); + bfloat16_t _blur_d_stencil_21 = bfloat16_t::make_from_bits(blur_d_stencil.extract<176, 191>()); + bfloat16_t _blur_d_stencil_22 = bfloat16_t::make_from_bits(blur_d_stencil.extract<192, 207>()); + bfloat16_t _blur_d_stencil_23 = bfloat16_t::make_from_bits(blur_d_stencil.extract<208, 223>()); + bfloat16_t _blur_d_stencil_24 = bfloat16_t::make_from_bits(blur_d_stencil.extract<224, 239>()); + bfloat16_t _blur_d_stencil_25 = bfloat16_t::make_from_bits(blur_d_stencil.extract<240, 255>()); + bfloat16_t _blur_d_stencil_26 = bfloat16_t::make_from_bits(blur_d_stencil.extract<256, 271>()); + bfloat16_t _blur_d_stencil_27 = bfloat16_t::make_from_bits(blur_d_stencil.extract<272, 287>()); + bfloat16_t _blur_d_stencil_28 = bfloat16_t::make_from_bits(blur_d_stencil.extract<288, 303>()); + bfloat16_t _blur_d_stencil_29 = bfloat16_t::make_from_bits(blur_d_stencil.extract<304, 319>()); + bfloat16_t _blur_d_stencil_5 = bfloat16_t::make_from_bits(blur_d_stencil.extract<320, 335>()); + bfloat16_t _blur_d_stencil_6 = bfloat16_t::make_from_bits(blur_d_stencil.extract<336, 351>()); + bfloat16_t _blur_d_stencil_7 = bfloat16_t::make_from_bits(blur_d_stencil.extract<352, 367>()); + bfloat16_t _blur_d_stencil_8 = bfloat16_t::make_from_bits(blur_d_stencil.extract<368, 383>()); + bfloat16_t _blur_d_stencil_9 = bfloat16_t::make_from_bits(blur_d_stencil.extract<384, 399>()); + + bfloat16_t _non_local_means_sum_stencil_4 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1078 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1079 = _blur_d_stencil_5 * _1078; + bfloat16_t _1080 = exp_bf16(_1079); + bfloat16_t _1081 = _blur_d_stencil_6 * _1078; + bfloat16_t _1082 = exp_bf16(_1081); + bfloat16_t _1083 = _blur_d_stencil_7 * _1078; + bfloat16_t _1084 = exp_bf16(_1083); + bfloat16_t _1085 = _blur_d_stencil_8 * _1078; + bfloat16_t _1086 = exp_bf16(_1085); + bfloat16_t _1087 = _blur_d_stencil_9 * _1078; + bfloat16_t _1088 = exp_bf16(_1087); + bfloat16_t _1089 = _blur_d_stencil_10 * _1078; + bfloat16_t _1090 = exp_bf16(_1089); + bfloat16_t _1091 = _blur_d_stencil_11 * _1078; + bfloat16_t _1092 = exp_bf16(_1091); + bfloat16_t _1093 = _blur_d_stencil_12 * _1078; + bfloat16_t _1094 = exp_bf16(_1093); + bfloat16_t _1095 = _blur_d_stencil_13 * _1078; + bfloat16_t _1096 = exp_bf16(_1095); + bfloat16_t _1097 = _blur_d_stencil_14 * _1078; + bfloat16_t _1098 = exp_bf16(_1097); + bfloat16_t _1099 = _blur_d_stencil_15 * _1078; + bfloat16_t _1100 = exp_bf16(_1099); + bfloat16_t _1101 = _blur_d_stencil_16 * _1078; + bfloat16_t _1102 = exp_bf16(_1101); + bfloat16_t _1103 = _blur_d_stencil_17 * _1078; + bfloat16_t _1104 = exp_bf16(_1103); + bfloat16_t _1105 = _blur_d_stencil_18 * _1078; + bfloat16_t _1106 = exp_bf16(_1105); + bfloat16_t _1107 = _blur_d_stencil_19 * _1078; + bfloat16_t _1108 = exp_bf16(_1107); + bfloat16_t _1109 = _blur_d_stencil_20 * _1078; + bfloat16_t _1110 = exp_bf16(_1109); + bfloat16_t _1111 = _blur_d_stencil_21 * _1078; + bfloat16_t _1112 = exp_bf16(_1111); + bfloat16_t _1113 = _blur_d_stencil_22 * _1078; + bfloat16_t _1114 = exp_bf16(_1113); + bfloat16_t _1115 = _blur_d_stencil_23 * _1078; + bfloat16_t _1116 = exp_bf16(_1115); + bfloat16_t _1117 = _blur_d_stencil_24 * _1078; + bfloat16_t _1118 = exp_bf16(_1117); + bfloat16_t _1119 = _blur_d_stencil_25 * _1078; + bfloat16_t _1120 = exp_bf16(_1119); + bfloat16_t _1121 = _blur_d_stencil_26 * _1078; + bfloat16_t _1122 = exp_bf16(_1121); + bfloat16_t _1123 = _blur_d_stencil_27 * _1078; + bfloat16_t _1124 = exp_bf16(_1123); + bfloat16_t _1125 = _blur_d_stencil_28 * _1078; + bfloat16_t _1126 = exp_bf16(_1125); + bfloat16_t _1127 = _blur_d_stencil_29 * _1078; + bfloat16_t _1128 = exp_bf16(_1127); + bfloat16_t _1129 = _non_local_means_sum_stencil_4 + _1128; + bfloat16_t _1130 = _1126 + _1129; + bfloat16_t _1131 = _1124 + _1130; + bfloat16_t _1132 = _1122 + _1131; + bfloat16_t _1133 = _1120 + _1132; + bfloat16_t _1134 = _1118 + _1133; + bfloat16_t _1135 = _1116 + _1134; + bfloat16_t _1136 = _1114 + _1135; + bfloat16_t _1137 = _1112 + _1136; + bfloat16_t _1138 = _1110 + _1137; + bfloat16_t _1139 = _1108 + _1138; + bfloat16_t _1140 = _1106 + _1139; + bfloat16_t _1141 = _1104 + _1140; + bfloat16_t _1142 = _1102 + _1141; + bfloat16_t _1143 = _1100 + _1142; + bfloat16_t _1144 = _1098 + _1143; + bfloat16_t _1145 = _1096 + _1144; + bfloat16_t _1146 = _1094 + _1145; + bfloat16_t _1147 = _1092 + _1146; + bfloat16_t _1148 = _1090 + _1147; + bfloat16_t _1149 = _1088 + _1148; + bfloat16_t _1150 = _1086 + _1149; + bfloat16_t _1151 = _1084 + _1150; + bfloat16_t _1152 = _1082 + _1151; + bfloat16_t _1153 = _1080 + _1152; + return _1153; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_5 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_6 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1332 = _non_local_means_sum_stencil_5 / _non_local_means_sum_stencil_6; + bfloat16_t _1333 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1334 = min(_1332, _1333); + bfloat16_t _1335 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1336 = max(_1334, _1335); + bfloat16_t _1337 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1338 = _1336 * _1337; + return _1338; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_7 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_8 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1355 = _non_local_means_sum_stencil_7 / _non_local_means_sum_stencil_8; + bfloat16_t _1356 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1357 = min(_1355, _1356); + bfloat16_t _1358 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1359 = max(_1357, _1358); + bfloat16_t _1360 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1361 = _1359 * _1360; + return _1361; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_10 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_9 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _1378 = _non_local_means_sum_stencil_9 / _non_local_means_sum_stencil_10; + bfloat16_t _1379 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _1380 = min(_1378, _1379); + bfloat16_t _1381 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _1382 = max(_1380, _1381); + bfloat16_t _1383 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _1384 = _1382 * _1383; + return _1384; +} + diff --git a/nlmeans_unroll_compute.h b/nlmeans_unroll_compute.h new file mode 100644 index 000000000..ad1ea4f89 --- /dev/null +++ b/nlmeans_unroll_compute.h @@ -0,0 +1,1297 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.stencil(0, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(0, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_1 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.stencil(1, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(1, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_1(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_2 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.stencil(2, (hw_input_global_wrapper_s0_x + 6), (hw_input_global_wrapper_s0_y + 6)) = hw_input.stencil(2, hw_input_global_wrapper_s0_x, hw_input_global_wrapper_s0_y) +hw_uint<16> hcompute_hw_input_global_wrapper_stencil_2(hw_uint<16>& hw_input_stencil) { + bfloat16_t _hw_input_stencil_3 = bfloat16_t::make_from_bits(hw_input_stencil.extract<0, 15>()); + + return _hw_input_stencil_3; +} + +//store is: d.stencil((d_s0_x + 3), (d_s0_y + 3), (d_s0_dx + 3), (d_s0_dy + 3)) = 0.000000h +hw_uint<16> hcompute_d_stencil() { + bfloat16_t _889 = bfloat_from_bits(0 /* 0 */); + return _889; +} + +//store is: d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) = (((hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(2, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(2, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (((hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(1, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(1, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))) + (d.stencil((d_s1_x + 3), (d_s1_y + 3), (d_s1_dx + 3), (d_s1_dy + 3)) + ((hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6)))*(hw_input_global_wrapper.stencil(0, (d_s1_x + 6), (d_s1_y + 6)) - hw_input_global_wrapper.stencil(0, ((d_s1_dx + d_s1_x) + 6), ((d_s1_dy + d_s1_y) + 6))))))) +hw_uint<16> hcompute_d_stencil_1(hw_uint<16>& d_stencil, hw_uint<96>& hw_input_global_wrapper_stencil) { + bfloat16_t _d_stencil_1 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + + bfloat16_t _hw_input_global_wrapper_stencil_1 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_2 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_3 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_4 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_5 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_6 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + + bfloat16_t _896 = _hw_input_global_wrapper_stencil_1 - _hw_input_global_wrapper_stencil_2; + bfloat16_t _897 = _896 * _896; + bfloat16_t _898 = _hw_input_global_wrapper_stencil_3 - _hw_input_global_wrapper_stencil_4; + bfloat16_t _899 = _898 * _898; + bfloat16_t _900 = _hw_input_global_wrapper_stencil_5 - _hw_input_global_wrapper_stencil_6; + bfloat16_t _901 = _900 * _900; + bfloat16_t _902 = _d_stencil_1 + _901; + bfloat16_t _903 = _899 + _902; + bfloat16_t _904 = _897 + _903; + return _904; +} + +//store is: blur_d_y.stencil((blur_d_y_s0_x + 3), blur_d_y_s0_y, (blur_d_y_s0_dx + 3), (blur_d_y_s0_dy + 3)) = 0.000000h +hw_uint<16> hcompute_blur_d_y_stencil() { + bfloat16_t _940 = bfloat_from_bits(0 /* 0 */); + return _940; +} + +//store is: blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) = (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 6), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 5), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 4), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 3), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 2), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (d.stencil((blur_d_y_s1_x + 3), (blur_d_y_s1_y + 1), (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + (blur_d_y.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3)) + d.stencil((blur_d_y_s1_x + 3), blur_d_y_s1_y, (blur_d_y_s1_dx + 3), (blur_d_y_s1_dy + 3))))))))) +hw_uint<16> hcompute_blur_d_y_stencil_1(hw_uint<16>& blur_d_y_stencil, hw_uint<112>& d_stencil) { + bfloat16_t _blur_d_y_stencil_1 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + + bfloat16_t _d_stencil_2 = bfloat16_t::make_from_bits(d_stencil.extract<0, 15>()); + bfloat16_t _d_stencil_3 = bfloat16_t::make_from_bits(d_stencil.extract<16, 31>()); + bfloat16_t _d_stencil_4 = bfloat16_t::make_from_bits(d_stencil.extract<32, 47>()); + bfloat16_t _d_stencil_5 = bfloat16_t::make_from_bits(d_stencil.extract<48, 63>()); + bfloat16_t _d_stencil_6 = bfloat16_t::make_from_bits(d_stencil.extract<64, 79>()); + bfloat16_t _d_stencil_7 = bfloat16_t::make_from_bits(d_stencil.extract<80, 95>()); + bfloat16_t _d_stencil_8 = bfloat16_t::make_from_bits(d_stencil.extract<96, 111>()); + + bfloat16_t _946 = _blur_d_y_stencil_1 + _d_stencil_8; + bfloat16_t _947 = _d_stencil_7 + _946; + bfloat16_t _948 = _d_stencil_6 + _947; + bfloat16_t _949 = _d_stencil_5 + _948; + bfloat16_t _950 = _d_stencil_4 + _949; + bfloat16_t _951 = _d_stencil_3 + _950; + bfloat16_t _952 = _d_stencil_2 + _951; + return _952; +} + +//store is: blur_d.stencil(blur_d_s0_x, blur_d_s0_y, (blur_d_s0_dx + 3), (blur_d_s0_dy + 3)) = 0.000000h +hw_uint<16> hcompute_blur_d_stencil() { + bfloat16_t _984 = bfloat_from_bits(0 /* 0 */); + return _984; +} + +//store is: blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) = (blur_d_y.stencil((blur_d_s1_x + 6), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 5), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 4), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 3), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 2), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d_y.stencil((blur_d_s1_x + 1), blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + (blur_d.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3)) + blur_d_y.stencil(blur_d_s1_x, blur_d_s1_y, (blur_d_s1_dx + 3), (blur_d_s1_dy + 3))))))))) +hw_uint<16> hcompute_blur_d_stencil_1(hw_uint<16>& blur_d_stencil, hw_uint<112>& blur_d_y_stencil) { + bfloat16_t _blur_d_stencil_1 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + + bfloat16_t _blur_d_y_stencil_2 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<0, 15>()); + bfloat16_t _blur_d_y_stencil_3 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<16, 31>()); + bfloat16_t _blur_d_y_stencil_4 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<32, 47>()); + bfloat16_t _blur_d_y_stencil_5 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<48, 63>()); + bfloat16_t _blur_d_y_stencil_6 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<64, 79>()); + bfloat16_t _blur_d_y_stencil_7 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<80, 95>()); + bfloat16_t _blur_d_y_stencil_8 = bfloat16_t::make_from_bits(blur_d_y_stencil.extract<96, 111>()); + + bfloat16_t _989 = _blur_d_stencil_1 + _blur_d_y_stencil_8; + bfloat16_t _990 = _blur_d_y_stencil_7 + _989; + bfloat16_t _991 = _blur_d_y_stencil_6 + _990; + bfloat16_t _992 = _blur_d_y_stencil_5 + _991; + bfloat16_t _993 = _blur_d_y_stencil_4 + _992; + bfloat16_t _994 = _blur_d_y_stencil_3 + _993; + bfloat16_t _995 = _blur_d_y_stencil_2 + _994; + return _995; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 0) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil() { + bfloat16_t _1026 = bfloat_from_bits(0 /* 0 */); + return _1026; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 1) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_1() { + bfloat16_t _1029 = bfloat_from_bits(0 /* 0 */); + return _1029; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 2) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_2() { + bfloat16_t _1032 = bfloat_from_bits(0 /* 0 */); + return _1032; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s0_x, non_local_means_sum_s0_y, 3) = 0.000000h +hw_uint<16> hcompute_non_local_means_sum_stencil_3() { + bfloat16_t _1035 = bfloat_from_bits(0 /* 0 */); + return _1035; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) = ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))*hw_input_global_wrapper.stencil(0, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) +hw_uint<16> hcompute_non_local_means_sum_stencil_4(hw_uint<784>& blur_d_stencil, hw_uint<784>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_10 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + bfloat16_t _blur_d_stencil_11 = bfloat16_t::make_from_bits(blur_d_stencil.extract<16, 31>()); + bfloat16_t _blur_d_stencil_12 = bfloat16_t::make_from_bits(blur_d_stencil.extract<32, 47>()); + bfloat16_t _blur_d_stencil_13 = bfloat16_t::make_from_bits(blur_d_stencil.extract<48, 63>()); + bfloat16_t _blur_d_stencil_14 = bfloat16_t::make_from_bits(blur_d_stencil.extract<64, 79>()); + bfloat16_t _blur_d_stencil_15 = bfloat16_t::make_from_bits(blur_d_stencil.extract<80, 95>()); + bfloat16_t _blur_d_stencil_16 = bfloat16_t::make_from_bits(blur_d_stencil.extract<96, 111>()); + bfloat16_t _blur_d_stencil_17 = bfloat16_t::make_from_bits(blur_d_stencil.extract<112, 127>()); + bfloat16_t _blur_d_stencil_18 = bfloat16_t::make_from_bits(blur_d_stencil.extract<128, 143>()); + bfloat16_t _blur_d_stencil_19 = bfloat16_t::make_from_bits(blur_d_stencil.extract<144, 159>()); + bfloat16_t _blur_d_stencil_2 = bfloat16_t::make_from_bits(blur_d_stencil.extract<160, 175>()); + bfloat16_t _blur_d_stencil_20 = bfloat16_t::make_from_bits(blur_d_stencil.extract<176, 191>()); + bfloat16_t _blur_d_stencil_21 = bfloat16_t::make_from_bits(blur_d_stencil.extract<192, 207>()); + bfloat16_t _blur_d_stencil_22 = bfloat16_t::make_from_bits(blur_d_stencil.extract<208, 223>()); + bfloat16_t _blur_d_stencil_23 = bfloat16_t::make_from_bits(blur_d_stencil.extract<224, 239>()); + bfloat16_t _blur_d_stencil_24 = bfloat16_t::make_from_bits(blur_d_stencil.extract<240, 255>()); + bfloat16_t _blur_d_stencil_25 = bfloat16_t::make_from_bits(blur_d_stencil.extract<256, 271>()); + bfloat16_t _blur_d_stencil_26 = bfloat16_t::make_from_bits(blur_d_stencil.extract<272, 287>()); + bfloat16_t _blur_d_stencil_27 = bfloat16_t::make_from_bits(blur_d_stencil.extract<288, 303>()); + bfloat16_t _blur_d_stencil_28 = bfloat16_t::make_from_bits(blur_d_stencil.extract<304, 319>()); + bfloat16_t _blur_d_stencil_29 = bfloat16_t::make_from_bits(blur_d_stencil.extract<320, 335>()); + bfloat16_t _blur_d_stencil_3 = bfloat16_t::make_from_bits(blur_d_stencil.extract<336, 351>()); + bfloat16_t _blur_d_stencil_30 = bfloat16_t::make_from_bits(blur_d_stencil.extract<352, 367>()); + bfloat16_t _blur_d_stencil_31 = bfloat16_t::make_from_bits(blur_d_stencil.extract<368, 383>()); + bfloat16_t _blur_d_stencil_32 = bfloat16_t::make_from_bits(blur_d_stencil.extract<384, 399>()); + bfloat16_t _blur_d_stencil_33 = bfloat16_t::make_from_bits(blur_d_stencil.extract<400, 415>()); + bfloat16_t _blur_d_stencil_34 = bfloat16_t::make_from_bits(blur_d_stencil.extract<416, 431>()); + bfloat16_t _blur_d_stencil_35 = bfloat16_t::make_from_bits(blur_d_stencil.extract<432, 447>()); + bfloat16_t _blur_d_stencil_36 = bfloat16_t::make_from_bits(blur_d_stencil.extract<448, 463>()); + bfloat16_t _blur_d_stencil_37 = bfloat16_t::make_from_bits(blur_d_stencil.extract<464, 479>()); + bfloat16_t _blur_d_stencil_38 = bfloat16_t::make_from_bits(blur_d_stencil.extract<480, 495>()); + bfloat16_t _blur_d_stencil_39 = bfloat16_t::make_from_bits(blur_d_stencil.extract<496, 511>()); + bfloat16_t _blur_d_stencil_4 = bfloat16_t::make_from_bits(blur_d_stencil.extract<512, 527>()); + bfloat16_t _blur_d_stencil_40 = bfloat16_t::make_from_bits(blur_d_stencil.extract<528, 543>()); + bfloat16_t _blur_d_stencil_41 = bfloat16_t::make_from_bits(blur_d_stencil.extract<544, 559>()); + bfloat16_t _blur_d_stencil_42 = bfloat16_t::make_from_bits(blur_d_stencil.extract<560, 575>()); + bfloat16_t _blur_d_stencil_43 = bfloat16_t::make_from_bits(blur_d_stencil.extract<576, 591>()); + bfloat16_t _blur_d_stencil_44 = bfloat16_t::make_from_bits(blur_d_stencil.extract<592, 607>()); + bfloat16_t _blur_d_stencil_45 = bfloat16_t::make_from_bits(blur_d_stencil.extract<608, 623>()); + bfloat16_t _blur_d_stencil_46 = bfloat16_t::make_from_bits(blur_d_stencil.extract<624, 639>()); + bfloat16_t _blur_d_stencil_47 = bfloat16_t::make_from_bits(blur_d_stencil.extract<640, 655>()); + bfloat16_t _blur_d_stencil_48 = bfloat16_t::make_from_bits(blur_d_stencil.extract<656, 671>()); + bfloat16_t _blur_d_stencil_49 = bfloat16_t::make_from_bits(blur_d_stencil.extract<672, 687>()); + bfloat16_t _blur_d_stencil_5 = bfloat16_t::make_from_bits(blur_d_stencil.extract<688, 703>()); + bfloat16_t _blur_d_stencil_50 = bfloat16_t::make_from_bits(blur_d_stencil.extract<704, 719>()); + bfloat16_t _blur_d_stencil_6 = bfloat16_t::make_from_bits(blur_d_stencil.extract<720, 735>()); + bfloat16_t _blur_d_stencil_7 = bfloat16_t::make_from_bits(blur_d_stencil.extract<736, 751>()); + bfloat16_t _blur_d_stencil_8 = bfloat16_t::make_from_bits(blur_d_stencil.extract<752, 767>()); + bfloat16_t _blur_d_stencil_9 = bfloat16_t::make_from_bits(blur_d_stencil.extract<768, 783>()); + + bfloat16_t _hw_input_global_wrapper_stencil_10 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_11 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_12 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_13 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_14 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_15 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + bfloat16_t _hw_input_global_wrapper_stencil_16 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<96, 111>()); + bfloat16_t _hw_input_global_wrapper_stencil_17 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<112, 127>()); + bfloat16_t _hw_input_global_wrapper_stencil_18 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<128, 143>()); + bfloat16_t _hw_input_global_wrapper_stencil_19 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<144, 159>()); + bfloat16_t _hw_input_global_wrapper_stencil_20 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<160, 175>()); + bfloat16_t _hw_input_global_wrapper_stencil_21 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<176, 191>()); + bfloat16_t _hw_input_global_wrapper_stencil_22 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<192, 207>()); + bfloat16_t _hw_input_global_wrapper_stencil_23 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<208, 223>()); + bfloat16_t _hw_input_global_wrapper_stencil_24 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<224, 239>()); + bfloat16_t _hw_input_global_wrapper_stencil_25 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<240, 255>()); + bfloat16_t _hw_input_global_wrapper_stencil_26 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<256, 271>()); + bfloat16_t _hw_input_global_wrapper_stencil_27 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<272, 287>()); + bfloat16_t _hw_input_global_wrapper_stencil_28 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<288, 303>()); + bfloat16_t _hw_input_global_wrapper_stencil_29 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<304, 319>()); + bfloat16_t _hw_input_global_wrapper_stencil_30 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<320, 335>()); + bfloat16_t _hw_input_global_wrapper_stencil_31 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<336, 351>()); + bfloat16_t _hw_input_global_wrapper_stencil_32 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<352, 367>()); + bfloat16_t _hw_input_global_wrapper_stencil_33 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<368, 383>()); + bfloat16_t _hw_input_global_wrapper_stencil_34 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<384, 399>()); + bfloat16_t _hw_input_global_wrapper_stencil_35 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<400, 415>()); + bfloat16_t _hw_input_global_wrapper_stencil_36 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<416, 431>()); + bfloat16_t _hw_input_global_wrapper_stencil_37 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<432, 447>()); + bfloat16_t _hw_input_global_wrapper_stencil_38 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<448, 463>()); + bfloat16_t _hw_input_global_wrapper_stencil_39 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<464, 479>()); + bfloat16_t _hw_input_global_wrapper_stencil_40 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<480, 495>()); + bfloat16_t _hw_input_global_wrapper_stencil_41 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<496, 511>()); + bfloat16_t _hw_input_global_wrapper_stencil_42 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<512, 527>()); + bfloat16_t _hw_input_global_wrapper_stencil_43 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<528, 543>()); + bfloat16_t _hw_input_global_wrapper_stencil_44 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<544, 559>()); + bfloat16_t _hw_input_global_wrapper_stencil_45 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<560, 575>()); + bfloat16_t _hw_input_global_wrapper_stencil_46 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<576, 591>()); + bfloat16_t _hw_input_global_wrapper_stencil_47 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<592, 607>()); + bfloat16_t _hw_input_global_wrapper_stencil_48 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<608, 623>()); + bfloat16_t _hw_input_global_wrapper_stencil_49 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<624, 639>()); + bfloat16_t _hw_input_global_wrapper_stencil_50 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<640, 655>()); + bfloat16_t _hw_input_global_wrapper_stencil_51 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<656, 671>()); + bfloat16_t _hw_input_global_wrapper_stencil_52 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<672, 687>()); + bfloat16_t _hw_input_global_wrapper_stencil_53 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<688, 703>()); + bfloat16_t _hw_input_global_wrapper_stencil_54 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<704, 719>()); + bfloat16_t _hw_input_global_wrapper_stencil_55 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<720, 735>()); + bfloat16_t _hw_input_global_wrapper_stencil_7 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<736, 751>()); + bfloat16_t _hw_input_global_wrapper_stencil_8 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<752, 767>()); + bfloat16_t _hw_input_global_wrapper_stencil_9 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<768, 783>()); + + bfloat16_t _non_local_means_sum_stencil_1 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1038 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1039 = _blur_d_stencil_2 * _1038; + bfloat16_t _1040 = exp_bf16(_1039); + bfloat16_t _1041 = _1040 * _hw_input_global_wrapper_stencil_7; + bfloat16_t _1042 = _blur_d_stencil_3 * _1038; + bfloat16_t _1043 = exp_bf16(_1042); + bfloat16_t _1044 = _1043 * _hw_input_global_wrapper_stencil_8; + bfloat16_t _1045 = _blur_d_stencil_4 * _1038; + bfloat16_t _1046 = exp_bf16(_1045); + bfloat16_t _1047 = _1046 * _hw_input_global_wrapper_stencil_9; + bfloat16_t _1048 = _blur_d_stencil_5 * _1038; + bfloat16_t _1049 = exp_bf16(_1048); + bfloat16_t _1050 = _1049 * _hw_input_global_wrapper_stencil_10; + bfloat16_t _1051 = _blur_d_stencil_6 * _1038; + bfloat16_t _1052 = exp_bf16(_1051); + bfloat16_t _1053 = _1052 * _hw_input_global_wrapper_stencil_11; + bfloat16_t _1054 = _blur_d_stencil_7 * _1038; + bfloat16_t _1055 = exp_bf16(_1054); + bfloat16_t _1056 = _1055 * _hw_input_global_wrapper_stencil_12; + bfloat16_t _1057 = _blur_d_stencil_8 * _1038; + bfloat16_t _1058 = exp_bf16(_1057); + bfloat16_t _1059 = _1058 * _hw_input_global_wrapper_stencil_13; + bfloat16_t _1060 = _blur_d_stencil_9 * _1038; + bfloat16_t _1061 = exp_bf16(_1060); + bfloat16_t _1062 = _1061 * _hw_input_global_wrapper_stencil_14; + bfloat16_t _1063 = _blur_d_stencil_10 * _1038; + bfloat16_t _1064 = exp_bf16(_1063); + bfloat16_t _1065 = _1064 * _hw_input_global_wrapper_stencil_15; + bfloat16_t _1066 = _blur_d_stencil_11 * _1038; + bfloat16_t _1067 = exp_bf16(_1066); + bfloat16_t _1068 = _1067 * _hw_input_global_wrapper_stencil_16; + bfloat16_t _1069 = _blur_d_stencil_12 * _1038; + bfloat16_t _1070 = exp_bf16(_1069); + bfloat16_t _1071 = _1070 * _hw_input_global_wrapper_stencil_17; + bfloat16_t _1072 = _blur_d_stencil_13 * _1038; + bfloat16_t _1073 = exp_bf16(_1072); + bfloat16_t _1074 = _1073 * _hw_input_global_wrapper_stencil_18; + bfloat16_t _1075 = _blur_d_stencil_14 * _1038; + bfloat16_t _1076 = exp_bf16(_1075); + bfloat16_t _1077 = _1076 * _hw_input_global_wrapper_stencil_19; + bfloat16_t _1078 = _blur_d_stencil_15 * _1038; + bfloat16_t _1079 = exp_bf16(_1078); + bfloat16_t _1080 = _1079 * _hw_input_global_wrapper_stencil_20; + bfloat16_t _1081 = _blur_d_stencil_16 * _1038; + bfloat16_t _1082 = exp_bf16(_1081); + bfloat16_t _1083 = _1082 * _hw_input_global_wrapper_stencil_21; + bfloat16_t _1084 = _blur_d_stencil_17 * _1038; + bfloat16_t _1085 = exp_bf16(_1084); + bfloat16_t _1086 = _1085 * _hw_input_global_wrapper_stencil_22; + bfloat16_t _1087 = _blur_d_stencil_18 * _1038; + bfloat16_t _1088 = exp_bf16(_1087); + bfloat16_t _1089 = _1088 * _hw_input_global_wrapper_stencil_23; + bfloat16_t _1090 = _blur_d_stencil_19 * _1038; + bfloat16_t _1091 = exp_bf16(_1090); + bfloat16_t _1092 = _1091 * _hw_input_global_wrapper_stencil_24; + bfloat16_t _1093 = _blur_d_stencil_20 * _1038; + bfloat16_t _1094 = exp_bf16(_1093); + bfloat16_t _1095 = _1094 * _hw_input_global_wrapper_stencil_25; + bfloat16_t _1096 = _blur_d_stencil_21 * _1038; + bfloat16_t _1097 = exp_bf16(_1096); + bfloat16_t _1098 = _1097 * _hw_input_global_wrapper_stencil_26; + bfloat16_t _1099 = _blur_d_stencil_22 * _1038; + bfloat16_t _1100 = exp_bf16(_1099); + bfloat16_t _1101 = _1100 * _hw_input_global_wrapper_stencil_27; + bfloat16_t _1102 = _blur_d_stencil_23 * _1038; + bfloat16_t _1103 = exp_bf16(_1102); + bfloat16_t _1104 = _1103 * _hw_input_global_wrapper_stencil_28; + bfloat16_t _1105 = _blur_d_stencil_24 * _1038; + bfloat16_t _1106 = exp_bf16(_1105); + bfloat16_t _1107 = _1106 * _hw_input_global_wrapper_stencil_29; + bfloat16_t _1108 = _blur_d_stencil_25 * _1038; + bfloat16_t _1109 = exp_bf16(_1108); + bfloat16_t _1110 = _1109 * _hw_input_global_wrapper_stencil_30; + bfloat16_t _1111 = _blur_d_stencil_26 * _1038; + bfloat16_t _1112 = exp_bf16(_1111); + bfloat16_t _1113 = _1112 * _hw_input_global_wrapper_stencil_31; + bfloat16_t _1114 = _blur_d_stencil_27 * _1038; + bfloat16_t _1115 = exp_bf16(_1114); + bfloat16_t _1116 = _1115 * _hw_input_global_wrapper_stencil_32; + bfloat16_t _1117 = _blur_d_stencil_28 * _1038; + bfloat16_t _1118 = exp_bf16(_1117); + bfloat16_t _1119 = _1118 * _hw_input_global_wrapper_stencil_33; + bfloat16_t _1120 = _blur_d_stencil_29 * _1038; + bfloat16_t _1121 = exp_bf16(_1120); + bfloat16_t _1122 = _1121 * _hw_input_global_wrapper_stencil_34; + bfloat16_t _1123 = _blur_d_stencil_30 * _1038; + bfloat16_t _1124 = exp_bf16(_1123); + bfloat16_t _1125 = _1124 * _hw_input_global_wrapper_stencil_35; + bfloat16_t _1126 = _blur_d_stencil_31 * _1038; + bfloat16_t _1127 = exp_bf16(_1126); + bfloat16_t _1128 = _1127 * _hw_input_global_wrapper_stencil_36; + bfloat16_t _1129 = _blur_d_stencil_32 * _1038; + bfloat16_t _1130 = exp_bf16(_1129); + bfloat16_t _1131 = _1130 * _hw_input_global_wrapper_stencil_37; + bfloat16_t _1132 = _blur_d_stencil_33 * _1038; + bfloat16_t _1133 = exp_bf16(_1132); + bfloat16_t _1134 = _1133 * _hw_input_global_wrapper_stencil_38; + bfloat16_t _1135 = _blur_d_stencil_34 * _1038; + bfloat16_t _1136 = exp_bf16(_1135); + bfloat16_t _1137 = _1136 * _hw_input_global_wrapper_stencil_39; + bfloat16_t _1138 = _blur_d_stencil_35 * _1038; + bfloat16_t _1139 = exp_bf16(_1138); + bfloat16_t _1140 = _1139 * _hw_input_global_wrapper_stencil_40; + bfloat16_t _1141 = _blur_d_stencil_36 * _1038; + bfloat16_t _1142 = exp_bf16(_1141); + bfloat16_t _1143 = _1142 * _hw_input_global_wrapper_stencil_41; + bfloat16_t _1144 = _blur_d_stencil_37 * _1038; + bfloat16_t _1145 = exp_bf16(_1144); + bfloat16_t _1146 = _1145 * _hw_input_global_wrapper_stencil_42; + bfloat16_t _1147 = _blur_d_stencil_38 * _1038; + bfloat16_t _1148 = exp_bf16(_1147); + bfloat16_t _1149 = _1148 * _hw_input_global_wrapper_stencil_43; + bfloat16_t _1150 = _blur_d_stencil_39 * _1038; + bfloat16_t _1151 = exp_bf16(_1150); + bfloat16_t _1152 = _1151 * _hw_input_global_wrapper_stencil_44; + bfloat16_t _1153 = _blur_d_stencil_40 * _1038; + bfloat16_t _1154 = exp_bf16(_1153); + bfloat16_t _1155 = _1154 * _hw_input_global_wrapper_stencil_45; + bfloat16_t _1156 = _blur_d_stencil_41 * _1038; + bfloat16_t _1157 = exp_bf16(_1156); + bfloat16_t _1158 = _1157 * _hw_input_global_wrapper_stencil_46; + bfloat16_t _1159 = _blur_d_stencil_42 * _1038; + bfloat16_t _1160 = exp_bf16(_1159); + bfloat16_t _1161 = _1160 * _hw_input_global_wrapper_stencil_47; + bfloat16_t _1162 = _blur_d_stencil_43 * _1038; + bfloat16_t _1163 = exp_bf16(_1162); + bfloat16_t _1164 = _1163 * _hw_input_global_wrapper_stencil_48; + bfloat16_t _1165 = _blur_d_stencil_44 * _1038; + bfloat16_t _1166 = exp_bf16(_1165); + bfloat16_t _1167 = _1166 * _hw_input_global_wrapper_stencil_49; + bfloat16_t _1168 = _blur_d_stencil_45 * _1038; + bfloat16_t _1169 = exp_bf16(_1168); + bfloat16_t _1170 = _1169 * _hw_input_global_wrapper_stencil_50; + bfloat16_t _1171 = _blur_d_stencil_46 * _1038; + bfloat16_t _1172 = exp_bf16(_1171); + bfloat16_t _1173 = _1172 * _hw_input_global_wrapper_stencil_51; + bfloat16_t _1174 = _blur_d_stencil_47 * _1038; + bfloat16_t _1175 = exp_bf16(_1174); + bfloat16_t _1176 = _1175 * _hw_input_global_wrapper_stencil_52; + bfloat16_t _1177 = _blur_d_stencil_48 * _1038; + bfloat16_t _1178 = exp_bf16(_1177); + bfloat16_t _1179 = _1178 * _hw_input_global_wrapper_stencil_53; + bfloat16_t _1180 = _blur_d_stencil_49 * _1038; + bfloat16_t _1181 = exp_bf16(_1180); + bfloat16_t _1182 = _1181 * _hw_input_global_wrapper_stencil_54; + bfloat16_t _1183 = _blur_d_stencil_50 * _1038; + bfloat16_t _1184 = exp_bf16(_1183); + bfloat16_t _1185 = _1184 * _hw_input_global_wrapper_stencil_55; + bfloat16_t _1186 = _non_local_means_sum_stencil_1 + _1185; + bfloat16_t _1187 = _1182 + _1186; + bfloat16_t _1188 = _1179 + _1187; + bfloat16_t _1189 = _1176 + _1188; + bfloat16_t _1190 = _1173 + _1189; + bfloat16_t _1191 = _1170 + _1190; + bfloat16_t _1192 = _1167 + _1191; + bfloat16_t _1193 = _1164 + _1192; + bfloat16_t _1194 = _1161 + _1193; + bfloat16_t _1195 = _1158 + _1194; + bfloat16_t _1196 = _1155 + _1195; + bfloat16_t _1197 = _1152 + _1196; + bfloat16_t _1198 = _1149 + _1197; + bfloat16_t _1199 = _1146 + _1198; + bfloat16_t _1200 = _1143 + _1199; + bfloat16_t _1201 = _1140 + _1200; + bfloat16_t _1202 = _1137 + _1201; + bfloat16_t _1203 = _1134 + _1202; + bfloat16_t _1204 = _1131 + _1203; + bfloat16_t _1205 = _1128 + _1204; + bfloat16_t _1206 = _1125 + _1205; + bfloat16_t _1207 = _1122 + _1206; + bfloat16_t _1208 = _1119 + _1207; + bfloat16_t _1209 = _1116 + _1208; + bfloat16_t _1210 = _1113 + _1209; + bfloat16_t _1211 = _1110 + _1210; + bfloat16_t _1212 = _1107 + _1211; + bfloat16_t _1213 = _1104 + _1212; + bfloat16_t _1214 = _1101 + _1213; + bfloat16_t _1215 = _1098 + _1214; + bfloat16_t _1216 = _1095 + _1215; + bfloat16_t _1217 = _1092 + _1216; + bfloat16_t _1218 = _1089 + _1217; + bfloat16_t _1219 = _1086 + _1218; + bfloat16_t _1220 = _1083 + _1219; + bfloat16_t _1221 = _1080 + _1220; + bfloat16_t _1222 = _1077 + _1221; + bfloat16_t _1223 = _1074 + _1222; + bfloat16_t _1224 = _1071 + _1223; + bfloat16_t _1225 = _1068 + _1224; + bfloat16_t _1226 = _1065 + _1225; + bfloat16_t _1227 = _1062 + _1226; + bfloat16_t _1228 = _1059 + _1227; + bfloat16_t _1229 = _1056 + _1228; + bfloat16_t _1230 = _1053 + _1229; + bfloat16_t _1231 = _1050 + _1230; + bfloat16_t _1232 = _1047 + _1231; + bfloat16_t _1233 = _1044 + _1232; + bfloat16_t _1234 = _1041 + _1233; + return _1234; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) = ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))*hw_input_global_wrapper.stencil(1, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) +hw_uint<16> hcompute_non_local_means_sum_stencil_5(hw_uint<784>& blur_d_stencil, hw_uint<784>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_51 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + bfloat16_t _blur_d_stencil_52 = bfloat16_t::make_from_bits(blur_d_stencil.extract<16, 31>()); + bfloat16_t _blur_d_stencil_53 = bfloat16_t::make_from_bits(blur_d_stencil.extract<32, 47>()); + bfloat16_t _blur_d_stencil_54 = bfloat16_t::make_from_bits(blur_d_stencil.extract<48, 63>()); + bfloat16_t _blur_d_stencil_55 = bfloat16_t::make_from_bits(blur_d_stencil.extract<64, 79>()); + bfloat16_t _blur_d_stencil_56 = bfloat16_t::make_from_bits(blur_d_stencil.extract<80, 95>()); + bfloat16_t _blur_d_stencil_57 = bfloat16_t::make_from_bits(blur_d_stencil.extract<96, 111>()); + bfloat16_t _blur_d_stencil_58 = bfloat16_t::make_from_bits(blur_d_stencil.extract<112, 127>()); + bfloat16_t _blur_d_stencil_59 = bfloat16_t::make_from_bits(blur_d_stencil.extract<128, 143>()); + bfloat16_t _blur_d_stencil_60 = bfloat16_t::make_from_bits(blur_d_stencil.extract<144, 159>()); + bfloat16_t _blur_d_stencil_61 = bfloat16_t::make_from_bits(blur_d_stencil.extract<160, 175>()); + bfloat16_t _blur_d_stencil_62 = bfloat16_t::make_from_bits(blur_d_stencil.extract<176, 191>()); + bfloat16_t _blur_d_stencil_63 = bfloat16_t::make_from_bits(blur_d_stencil.extract<192, 207>()); + bfloat16_t _blur_d_stencil_64 = bfloat16_t::make_from_bits(blur_d_stencil.extract<208, 223>()); + bfloat16_t _blur_d_stencil_65 = bfloat16_t::make_from_bits(blur_d_stencil.extract<224, 239>()); + bfloat16_t _blur_d_stencil_66 = bfloat16_t::make_from_bits(blur_d_stencil.extract<240, 255>()); + bfloat16_t _blur_d_stencil_67 = bfloat16_t::make_from_bits(blur_d_stencil.extract<256, 271>()); + bfloat16_t _blur_d_stencil_68 = bfloat16_t::make_from_bits(blur_d_stencil.extract<272, 287>()); + bfloat16_t _blur_d_stencil_69 = bfloat16_t::make_from_bits(blur_d_stencil.extract<288, 303>()); + bfloat16_t _blur_d_stencil_70 = bfloat16_t::make_from_bits(blur_d_stencil.extract<304, 319>()); + bfloat16_t _blur_d_stencil_71 = bfloat16_t::make_from_bits(blur_d_stencil.extract<320, 335>()); + bfloat16_t _blur_d_stencil_72 = bfloat16_t::make_from_bits(blur_d_stencil.extract<336, 351>()); + bfloat16_t _blur_d_stencil_73 = bfloat16_t::make_from_bits(blur_d_stencil.extract<352, 367>()); + bfloat16_t _blur_d_stencil_74 = bfloat16_t::make_from_bits(blur_d_stencil.extract<368, 383>()); + bfloat16_t _blur_d_stencil_75 = bfloat16_t::make_from_bits(blur_d_stencil.extract<384, 399>()); + bfloat16_t _blur_d_stencil_76 = bfloat16_t::make_from_bits(blur_d_stencil.extract<400, 415>()); + bfloat16_t _blur_d_stencil_77 = bfloat16_t::make_from_bits(blur_d_stencil.extract<416, 431>()); + bfloat16_t _blur_d_stencil_78 = bfloat16_t::make_from_bits(blur_d_stencil.extract<432, 447>()); + bfloat16_t _blur_d_stencil_79 = bfloat16_t::make_from_bits(blur_d_stencil.extract<448, 463>()); + bfloat16_t _blur_d_stencil_80 = bfloat16_t::make_from_bits(blur_d_stencil.extract<464, 479>()); + bfloat16_t _blur_d_stencil_81 = bfloat16_t::make_from_bits(blur_d_stencil.extract<480, 495>()); + bfloat16_t _blur_d_stencil_82 = bfloat16_t::make_from_bits(blur_d_stencil.extract<496, 511>()); + bfloat16_t _blur_d_stencil_83 = bfloat16_t::make_from_bits(blur_d_stencil.extract<512, 527>()); + bfloat16_t _blur_d_stencil_84 = bfloat16_t::make_from_bits(blur_d_stencil.extract<528, 543>()); + bfloat16_t _blur_d_stencil_85 = bfloat16_t::make_from_bits(blur_d_stencil.extract<544, 559>()); + bfloat16_t _blur_d_stencil_86 = bfloat16_t::make_from_bits(blur_d_stencil.extract<560, 575>()); + bfloat16_t _blur_d_stencil_87 = bfloat16_t::make_from_bits(blur_d_stencil.extract<576, 591>()); + bfloat16_t _blur_d_stencil_88 = bfloat16_t::make_from_bits(blur_d_stencil.extract<592, 607>()); + bfloat16_t _blur_d_stencil_89 = bfloat16_t::make_from_bits(blur_d_stencil.extract<608, 623>()); + bfloat16_t _blur_d_stencil_90 = bfloat16_t::make_from_bits(blur_d_stencil.extract<624, 639>()); + bfloat16_t _blur_d_stencil_91 = bfloat16_t::make_from_bits(blur_d_stencil.extract<640, 655>()); + bfloat16_t _blur_d_stencil_92 = bfloat16_t::make_from_bits(blur_d_stencil.extract<656, 671>()); + bfloat16_t _blur_d_stencil_93 = bfloat16_t::make_from_bits(blur_d_stencil.extract<672, 687>()); + bfloat16_t _blur_d_stencil_94 = bfloat16_t::make_from_bits(blur_d_stencil.extract<688, 703>()); + bfloat16_t _blur_d_stencil_95 = bfloat16_t::make_from_bits(blur_d_stencil.extract<704, 719>()); + bfloat16_t _blur_d_stencil_96 = bfloat16_t::make_from_bits(blur_d_stencil.extract<720, 735>()); + bfloat16_t _blur_d_stencil_97 = bfloat16_t::make_from_bits(blur_d_stencil.extract<736, 751>()); + bfloat16_t _blur_d_stencil_98 = bfloat16_t::make_from_bits(blur_d_stencil.extract<752, 767>()); + bfloat16_t _blur_d_stencil_99 = bfloat16_t::make_from_bits(blur_d_stencil.extract<768, 783>()); + + bfloat16_t _hw_input_global_wrapper_stencil_100 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_101 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_102 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_103 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_104 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_56 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + bfloat16_t _hw_input_global_wrapper_stencil_57 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<96, 111>()); + bfloat16_t _hw_input_global_wrapper_stencil_58 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<112, 127>()); + bfloat16_t _hw_input_global_wrapper_stencil_59 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<128, 143>()); + bfloat16_t _hw_input_global_wrapper_stencil_60 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<144, 159>()); + bfloat16_t _hw_input_global_wrapper_stencil_61 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<160, 175>()); + bfloat16_t _hw_input_global_wrapper_stencil_62 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<176, 191>()); + bfloat16_t _hw_input_global_wrapper_stencil_63 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<192, 207>()); + bfloat16_t _hw_input_global_wrapper_stencil_64 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<208, 223>()); + bfloat16_t _hw_input_global_wrapper_stencil_65 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<224, 239>()); + bfloat16_t _hw_input_global_wrapper_stencil_66 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<240, 255>()); + bfloat16_t _hw_input_global_wrapper_stencil_67 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<256, 271>()); + bfloat16_t _hw_input_global_wrapper_stencil_68 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<272, 287>()); + bfloat16_t _hw_input_global_wrapper_stencil_69 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<288, 303>()); + bfloat16_t _hw_input_global_wrapper_stencil_70 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<304, 319>()); + bfloat16_t _hw_input_global_wrapper_stencil_71 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<320, 335>()); + bfloat16_t _hw_input_global_wrapper_stencil_72 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<336, 351>()); + bfloat16_t _hw_input_global_wrapper_stencil_73 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<352, 367>()); + bfloat16_t _hw_input_global_wrapper_stencil_74 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<368, 383>()); + bfloat16_t _hw_input_global_wrapper_stencil_75 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<384, 399>()); + bfloat16_t _hw_input_global_wrapper_stencil_76 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<400, 415>()); + bfloat16_t _hw_input_global_wrapper_stencil_77 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<416, 431>()); + bfloat16_t _hw_input_global_wrapper_stencil_78 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<432, 447>()); + bfloat16_t _hw_input_global_wrapper_stencil_79 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<448, 463>()); + bfloat16_t _hw_input_global_wrapper_stencil_80 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<464, 479>()); + bfloat16_t _hw_input_global_wrapper_stencil_81 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<480, 495>()); + bfloat16_t _hw_input_global_wrapper_stencil_82 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<496, 511>()); + bfloat16_t _hw_input_global_wrapper_stencil_83 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<512, 527>()); + bfloat16_t _hw_input_global_wrapper_stencil_84 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<528, 543>()); + bfloat16_t _hw_input_global_wrapper_stencil_85 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<544, 559>()); + bfloat16_t _hw_input_global_wrapper_stencil_86 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<560, 575>()); + bfloat16_t _hw_input_global_wrapper_stencil_87 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<576, 591>()); + bfloat16_t _hw_input_global_wrapper_stencil_88 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<592, 607>()); + bfloat16_t _hw_input_global_wrapper_stencil_89 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<608, 623>()); + bfloat16_t _hw_input_global_wrapper_stencil_90 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<624, 639>()); + bfloat16_t _hw_input_global_wrapper_stencil_91 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<640, 655>()); + bfloat16_t _hw_input_global_wrapper_stencil_92 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<656, 671>()); + bfloat16_t _hw_input_global_wrapper_stencil_93 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<672, 687>()); + bfloat16_t _hw_input_global_wrapper_stencil_94 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<688, 703>()); + bfloat16_t _hw_input_global_wrapper_stencil_95 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<704, 719>()); + bfloat16_t _hw_input_global_wrapper_stencil_96 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<720, 735>()); + bfloat16_t _hw_input_global_wrapper_stencil_97 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<736, 751>()); + bfloat16_t _hw_input_global_wrapper_stencil_98 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<752, 767>()); + bfloat16_t _hw_input_global_wrapper_stencil_99 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<768, 783>()); + + bfloat16_t _non_local_means_sum_stencil_2 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _1742 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _1743 = _blur_d_stencil_51 * _1742; + bfloat16_t _1744 = exp_bf16(_1743); + bfloat16_t _1745 = _1744 * _hw_input_global_wrapper_stencil_56; + bfloat16_t _1746 = _blur_d_stencil_52 * _1742; + bfloat16_t _1747 = exp_bf16(_1746); + bfloat16_t _1748 = _1747 * _hw_input_global_wrapper_stencil_57; + bfloat16_t _1749 = _blur_d_stencil_53 * _1742; + bfloat16_t _1750 = exp_bf16(_1749); + bfloat16_t _1751 = _1750 * _hw_input_global_wrapper_stencil_58; + bfloat16_t _1752 = _blur_d_stencil_54 * _1742; + bfloat16_t _1753 = exp_bf16(_1752); + bfloat16_t _1754 = _1753 * _hw_input_global_wrapper_stencil_59; + bfloat16_t _1755 = _blur_d_stencil_55 * _1742; + bfloat16_t _1756 = exp_bf16(_1755); + bfloat16_t _1757 = _1756 * _hw_input_global_wrapper_stencil_60; + bfloat16_t _1758 = _blur_d_stencil_56 * _1742; + bfloat16_t _1759 = exp_bf16(_1758); + bfloat16_t _1760 = _1759 * _hw_input_global_wrapper_stencil_61; + bfloat16_t _1761 = _blur_d_stencil_57 * _1742; + bfloat16_t _1762 = exp_bf16(_1761); + bfloat16_t _1763 = _1762 * _hw_input_global_wrapper_stencil_62; + bfloat16_t _1764 = _blur_d_stencil_58 * _1742; + bfloat16_t _1765 = exp_bf16(_1764); + bfloat16_t _1766 = _1765 * _hw_input_global_wrapper_stencil_63; + bfloat16_t _1767 = _blur_d_stencil_59 * _1742; + bfloat16_t _1768 = exp_bf16(_1767); + bfloat16_t _1769 = _1768 * _hw_input_global_wrapper_stencil_64; + bfloat16_t _1770 = _blur_d_stencil_60 * _1742; + bfloat16_t _1771 = exp_bf16(_1770); + bfloat16_t _1772 = _1771 * _hw_input_global_wrapper_stencil_65; + bfloat16_t _1773 = _blur_d_stencil_61 * _1742; + bfloat16_t _1774 = exp_bf16(_1773); + bfloat16_t _1775 = _1774 * _hw_input_global_wrapper_stencil_66; + bfloat16_t _1776 = _blur_d_stencil_62 * _1742; + bfloat16_t _1777 = exp_bf16(_1776); + bfloat16_t _1778 = _1777 * _hw_input_global_wrapper_stencil_67; + bfloat16_t _1779 = _blur_d_stencil_63 * _1742; + bfloat16_t _1780 = exp_bf16(_1779); + bfloat16_t _1781 = _1780 * _hw_input_global_wrapper_stencil_68; + bfloat16_t _1782 = _blur_d_stencil_64 * _1742; + bfloat16_t _1783 = exp_bf16(_1782); + bfloat16_t _1784 = _1783 * _hw_input_global_wrapper_stencil_69; + bfloat16_t _1785 = _blur_d_stencil_65 * _1742; + bfloat16_t _1786 = exp_bf16(_1785); + bfloat16_t _1787 = _1786 * _hw_input_global_wrapper_stencil_70; + bfloat16_t _1788 = _blur_d_stencil_66 * _1742; + bfloat16_t _1789 = exp_bf16(_1788); + bfloat16_t _1790 = _1789 * _hw_input_global_wrapper_stencil_71; + bfloat16_t _1791 = _blur_d_stencil_67 * _1742; + bfloat16_t _1792 = exp_bf16(_1791); + bfloat16_t _1793 = _1792 * _hw_input_global_wrapper_stencil_72; + bfloat16_t _1794 = _blur_d_stencil_68 * _1742; + bfloat16_t _1795 = exp_bf16(_1794); + bfloat16_t _1796 = _1795 * _hw_input_global_wrapper_stencil_73; + bfloat16_t _1797 = _blur_d_stencil_69 * _1742; + bfloat16_t _1798 = exp_bf16(_1797); + bfloat16_t _1799 = _1798 * _hw_input_global_wrapper_stencil_74; + bfloat16_t _1800 = _blur_d_stencil_70 * _1742; + bfloat16_t _1801 = exp_bf16(_1800); + bfloat16_t _1802 = _1801 * _hw_input_global_wrapper_stencil_75; + bfloat16_t _1803 = _blur_d_stencil_71 * _1742; + bfloat16_t _1804 = exp_bf16(_1803); + bfloat16_t _1805 = _1804 * _hw_input_global_wrapper_stencil_76; + bfloat16_t _1806 = _blur_d_stencil_72 * _1742; + bfloat16_t _1807 = exp_bf16(_1806); + bfloat16_t _1808 = _1807 * _hw_input_global_wrapper_stencil_77; + bfloat16_t _1809 = _blur_d_stencil_73 * _1742; + bfloat16_t _1810 = exp_bf16(_1809); + bfloat16_t _1811 = _1810 * _hw_input_global_wrapper_stencil_78; + bfloat16_t _1812 = _blur_d_stencil_74 * _1742; + bfloat16_t _1813 = exp_bf16(_1812); + bfloat16_t _1814 = _1813 * _hw_input_global_wrapper_stencil_79; + bfloat16_t _1815 = _blur_d_stencil_75 * _1742; + bfloat16_t _1816 = exp_bf16(_1815); + bfloat16_t _1817 = _1816 * _hw_input_global_wrapper_stencil_80; + bfloat16_t _1818 = _blur_d_stencil_76 * _1742; + bfloat16_t _1819 = exp_bf16(_1818); + bfloat16_t _1820 = _1819 * _hw_input_global_wrapper_stencil_81; + bfloat16_t _1821 = _blur_d_stencil_77 * _1742; + bfloat16_t _1822 = exp_bf16(_1821); + bfloat16_t _1823 = _1822 * _hw_input_global_wrapper_stencil_82; + bfloat16_t _1824 = _blur_d_stencil_78 * _1742; + bfloat16_t _1825 = exp_bf16(_1824); + bfloat16_t _1826 = _1825 * _hw_input_global_wrapper_stencil_83; + bfloat16_t _1827 = _blur_d_stencil_79 * _1742; + bfloat16_t _1828 = exp_bf16(_1827); + bfloat16_t _1829 = _1828 * _hw_input_global_wrapper_stencil_84; + bfloat16_t _1830 = _blur_d_stencil_80 * _1742; + bfloat16_t _1831 = exp_bf16(_1830); + bfloat16_t _1832 = _1831 * _hw_input_global_wrapper_stencil_85; + bfloat16_t _1833 = _blur_d_stencil_81 * _1742; + bfloat16_t _1834 = exp_bf16(_1833); + bfloat16_t _1835 = _1834 * _hw_input_global_wrapper_stencil_86; + bfloat16_t _1836 = _blur_d_stencil_82 * _1742; + bfloat16_t _1837 = exp_bf16(_1836); + bfloat16_t _1838 = _1837 * _hw_input_global_wrapper_stencil_87; + bfloat16_t _1839 = _blur_d_stencil_83 * _1742; + bfloat16_t _1840 = exp_bf16(_1839); + bfloat16_t _1841 = _1840 * _hw_input_global_wrapper_stencil_88; + bfloat16_t _1842 = _blur_d_stencil_84 * _1742; + bfloat16_t _1843 = exp_bf16(_1842); + bfloat16_t _1844 = _1843 * _hw_input_global_wrapper_stencil_89; + bfloat16_t _1845 = _blur_d_stencil_85 * _1742; + bfloat16_t _1846 = exp_bf16(_1845); + bfloat16_t _1847 = _1846 * _hw_input_global_wrapper_stencil_90; + bfloat16_t _1848 = _blur_d_stencil_86 * _1742; + bfloat16_t _1849 = exp_bf16(_1848); + bfloat16_t _1850 = _1849 * _hw_input_global_wrapper_stencil_91; + bfloat16_t _1851 = _blur_d_stencil_87 * _1742; + bfloat16_t _1852 = exp_bf16(_1851); + bfloat16_t _1853 = _1852 * _hw_input_global_wrapper_stencil_92; + bfloat16_t _1854 = _blur_d_stencil_88 * _1742; + bfloat16_t _1855 = exp_bf16(_1854); + bfloat16_t _1856 = _1855 * _hw_input_global_wrapper_stencil_93; + bfloat16_t _1857 = _blur_d_stencil_89 * _1742; + bfloat16_t _1858 = exp_bf16(_1857); + bfloat16_t _1859 = _1858 * _hw_input_global_wrapper_stencil_94; + bfloat16_t _1860 = _blur_d_stencil_90 * _1742; + bfloat16_t _1861 = exp_bf16(_1860); + bfloat16_t _1862 = _1861 * _hw_input_global_wrapper_stencil_95; + bfloat16_t _1863 = _blur_d_stencil_91 * _1742; + bfloat16_t _1864 = exp_bf16(_1863); + bfloat16_t _1865 = _1864 * _hw_input_global_wrapper_stencil_96; + bfloat16_t _1866 = _blur_d_stencil_92 * _1742; + bfloat16_t _1867 = exp_bf16(_1866); + bfloat16_t _1868 = _1867 * _hw_input_global_wrapper_stencil_97; + bfloat16_t _1869 = _blur_d_stencil_93 * _1742; + bfloat16_t _1870 = exp_bf16(_1869); + bfloat16_t _1871 = _1870 * _hw_input_global_wrapper_stencil_98; + bfloat16_t _1872 = _blur_d_stencil_94 * _1742; + bfloat16_t _1873 = exp_bf16(_1872); + bfloat16_t _1874 = _1873 * _hw_input_global_wrapper_stencil_99; + bfloat16_t _1875 = _blur_d_stencil_95 * _1742; + bfloat16_t _1876 = exp_bf16(_1875); + bfloat16_t _1877 = _1876 * _hw_input_global_wrapper_stencil_100; + bfloat16_t _1878 = _blur_d_stencil_96 * _1742; + bfloat16_t _1879 = exp_bf16(_1878); + bfloat16_t _1880 = _1879 * _hw_input_global_wrapper_stencil_101; + bfloat16_t _1881 = _blur_d_stencil_97 * _1742; + bfloat16_t _1882 = exp_bf16(_1881); + bfloat16_t _1883 = _1882 * _hw_input_global_wrapper_stencil_102; + bfloat16_t _1884 = _blur_d_stencil_98 * _1742; + bfloat16_t _1885 = exp_bf16(_1884); + bfloat16_t _1886 = _1885 * _hw_input_global_wrapper_stencil_103; + bfloat16_t _1887 = _blur_d_stencil_99 * _1742; + bfloat16_t _1888 = exp_bf16(_1887); + bfloat16_t _1889 = _1888 * _hw_input_global_wrapper_stencil_104; + bfloat16_t _1890 = _non_local_means_sum_stencil_2 + _1889; + bfloat16_t _1891 = _1886 + _1890; + bfloat16_t _1892 = _1883 + _1891; + bfloat16_t _1893 = _1880 + _1892; + bfloat16_t _1894 = _1877 + _1893; + bfloat16_t _1895 = _1874 + _1894; + bfloat16_t _1896 = _1871 + _1895; + bfloat16_t _1897 = _1868 + _1896; + bfloat16_t _1898 = _1865 + _1897; + bfloat16_t _1899 = _1862 + _1898; + bfloat16_t _1900 = _1859 + _1899; + bfloat16_t _1901 = _1856 + _1900; + bfloat16_t _1902 = _1853 + _1901; + bfloat16_t _1903 = _1850 + _1902; + bfloat16_t _1904 = _1847 + _1903; + bfloat16_t _1905 = _1844 + _1904; + bfloat16_t _1906 = _1841 + _1905; + bfloat16_t _1907 = _1838 + _1906; + bfloat16_t _1908 = _1835 + _1907; + bfloat16_t _1909 = _1832 + _1908; + bfloat16_t _1910 = _1829 + _1909; + bfloat16_t _1911 = _1826 + _1910; + bfloat16_t _1912 = _1823 + _1911; + bfloat16_t _1913 = _1820 + _1912; + bfloat16_t _1914 = _1817 + _1913; + bfloat16_t _1915 = _1814 + _1914; + bfloat16_t _1916 = _1811 + _1915; + bfloat16_t _1917 = _1808 + _1916; + bfloat16_t _1918 = _1805 + _1917; + bfloat16_t _1919 = _1802 + _1918; + bfloat16_t _1920 = _1799 + _1919; + bfloat16_t _1921 = _1796 + _1920; + bfloat16_t _1922 = _1793 + _1921; + bfloat16_t _1923 = _1790 + _1922; + bfloat16_t _1924 = _1787 + _1923; + bfloat16_t _1925 = _1784 + _1924; + bfloat16_t _1926 = _1781 + _1925; + bfloat16_t _1927 = _1778 + _1926; + bfloat16_t _1928 = _1775 + _1927; + bfloat16_t _1929 = _1772 + _1928; + bfloat16_t _1930 = _1769 + _1929; + bfloat16_t _1931 = _1766 + _1930; + bfloat16_t _1932 = _1763 + _1931; + bfloat16_t _1933 = _1760 + _1932; + bfloat16_t _1934 = _1757 + _1933; + bfloat16_t _1935 = _1754 + _1934; + bfloat16_t _1936 = _1751 + _1935; + bfloat16_t _1937 = _1748 + _1936; + bfloat16_t _1938 = _1745 + _1937; + return _1938; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) = ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 9))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 8))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 7))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 6))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 5))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 4))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 9), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 8), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 7), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 6), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 5), (non_local_means_sum_s1_y + 3))) + ((exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 4), (non_local_means_sum_s1_y + 3))) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))*hw_input_global_wrapper.stencil(2, (non_local_means_sum_s1_x + 3), (non_local_means_sum_s1_y + 3)))))))))))))))))))))))))))))))))))))))))))))))))))) +hw_uint<16> hcompute_non_local_means_sum_stencil_6(hw_uint<784>& blur_d_stencil, hw_uint<784>& hw_input_global_wrapper_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_100 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + bfloat16_t _blur_d_stencil_101 = bfloat16_t::make_from_bits(blur_d_stencil.extract<16, 31>()); + bfloat16_t _blur_d_stencil_102 = bfloat16_t::make_from_bits(blur_d_stencil.extract<32, 47>()); + bfloat16_t _blur_d_stencil_103 = bfloat16_t::make_from_bits(blur_d_stencil.extract<48, 63>()); + bfloat16_t _blur_d_stencil_104 = bfloat16_t::make_from_bits(blur_d_stencil.extract<64, 79>()); + bfloat16_t _blur_d_stencil_105 = bfloat16_t::make_from_bits(blur_d_stencil.extract<80, 95>()); + bfloat16_t _blur_d_stencil_106 = bfloat16_t::make_from_bits(blur_d_stencil.extract<96, 111>()); + bfloat16_t _blur_d_stencil_107 = bfloat16_t::make_from_bits(blur_d_stencil.extract<112, 127>()); + bfloat16_t _blur_d_stencil_108 = bfloat16_t::make_from_bits(blur_d_stencil.extract<128, 143>()); + bfloat16_t _blur_d_stencil_109 = bfloat16_t::make_from_bits(blur_d_stencil.extract<144, 159>()); + bfloat16_t _blur_d_stencil_110 = bfloat16_t::make_from_bits(blur_d_stencil.extract<160, 175>()); + bfloat16_t _blur_d_stencil_111 = bfloat16_t::make_from_bits(blur_d_stencil.extract<176, 191>()); + bfloat16_t _blur_d_stencil_112 = bfloat16_t::make_from_bits(blur_d_stencil.extract<192, 207>()); + bfloat16_t _blur_d_stencil_113 = bfloat16_t::make_from_bits(blur_d_stencil.extract<208, 223>()); + bfloat16_t _blur_d_stencil_114 = bfloat16_t::make_from_bits(blur_d_stencil.extract<224, 239>()); + bfloat16_t _blur_d_stencil_115 = bfloat16_t::make_from_bits(blur_d_stencil.extract<240, 255>()); + bfloat16_t _blur_d_stencil_116 = bfloat16_t::make_from_bits(blur_d_stencil.extract<256, 271>()); + bfloat16_t _blur_d_stencil_117 = bfloat16_t::make_from_bits(blur_d_stencil.extract<272, 287>()); + bfloat16_t _blur_d_stencil_118 = bfloat16_t::make_from_bits(blur_d_stencil.extract<288, 303>()); + bfloat16_t _blur_d_stencil_119 = bfloat16_t::make_from_bits(blur_d_stencil.extract<304, 319>()); + bfloat16_t _blur_d_stencil_120 = bfloat16_t::make_from_bits(blur_d_stencil.extract<320, 335>()); + bfloat16_t _blur_d_stencil_121 = bfloat16_t::make_from_bits(blur_d_stencil.extract<336, 351>()); + bfloat16_t _blur_d_stencil_122 = bfloat16_t::make_from_bits(blur_d_stencil.extract<352, 367>()); + bfloat16_t _blur_d_stencil_123 = bfloat16_t::make_from_bits(blur_d_stencil.extract<368, 383>()); + bfloat16_t _blur_d_stencil_124 = bfloat16_t::make_from_bits(blur_d_stencil.extract<384, 399>()); + bfloat16_t _blur_d_stencil_125 = bfloat16_t::make_from_bits(blur_d_stencil.extract<400, 415>()); + bfloat16_t _blur_d_stencil_126 = bfloat16_t::make_from_bits(blur_d_stencil.extract<416, 431>()); + bfloat16_t _blur_d_stencil_127 = bfloat16_t::make_from_bits(blur_d_stencil.extract<432, 447>()); + bfloat16_t _blur_d_stencil_128 = bfloat16_t::make_from_bits(blur_d_stencil.extract<448, 463>()); + bfloat16_t _blur_d_stencil_129 = bfloat16_t::make_from_bits(blur_d_stencil.extract<464, 479>()); + bfloat16_t _blur_d_stencil_130 = bfloat16_t::make_from_bits(blur_d_stencil.extract<480, 495>()); + bfloat16_t _blur_d_stencil_131 = bfloat16_t::make_from_bits(blur_d_stencil.extract<496, 511>()); + bfloat16_t _blur_d_stencil_132 = bfloat16_t::make_from_bits(blur_d_stencil.extract<512, 527>()); + bfloat16_t _blur_d_stencil_133 = bfloat16_t::make_from_bits(blur_d_stencil.extract<528, 543>()); + bfloat16_t _blur_d_stencil_134 = bfloat16_t::make_from_bits(blur_d_stencil.extract<544, 559>()); + bfloat16_t _blur_d_stencil_135 = bfloat16_t::make_from_bits(blur_d_stencil.extract<560, 575>()); + bfloat16_t _blur_d_stencil_136 = bfloat16_t::make_from_bits(blur_d_stencil.extract<576, 591>()); + bfloat16_t _blur_d_stencil_137 = bfloat16_t::make_from_bits(blur_d_stencil.extract<592, 607>()); + bfloat16_t _blur_d_stencil_138 = bfloat16_t::make_from_bits(blur_d_stencil.extract<608, 623>()); + bfloat16_t _blur_d_stencil_139 = bfloat16_t::make_from_bits(blur_d_stencil.extract<624, 639>()); + bfloat16_t _blur_d_stencil_140 = bfloat16_t::make_from_bits(blur_d_stencil.extract<640, 655>()); + bfloat16_t _blur_d_stencil_141 = bfloat16_t::make_from_bits(blur_d_stencil.extract<656, 671>()); + bfloat16_t _blur_d_stencil_142 = bfloat16_t::make_from_bits(blur_d_stencil.extract<672, 687>()); + bfloat16_t _blur_d_stencil_143 = bfloat16_t::make_from_bits(blur_d_stencil.extract<688, 703>()); + bfloat16_t _blur_d_stencil_144 = bfloat16_t::make_from_bits(blur_d_stencil.extract<704, 719>()); + bfloat16_t _blur_d_stencil_145 = bfloat16_t::make_from_bits(blur_d_stencil.extract<720, 735>()); + bfloat16_t _blur_d_stencil_146 = bfloat16_t::make_from_bits(blur_d_stencil.extract<736, 751>()); + bfloat16_t _blur_d_stencil_147 = bfloat16_t::make_from_bits(blur_d_stencil.extract<752, 767>()); + bfloat16_t _blur_d_stencil_148 = bfloat16_t::make_from_bits(blur_d_stencil.extract<768, 783>()); + + bfloat16_t _hw_input_global_wrapper_stencil_105 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<0, 15>()); + bfloat16_t _hw_input_global_wrapper_stencil_106 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<16, 31>()); + bfloat16_t _hw_input_global_wrapper_stencil_107 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<32, 47>()); + bfloat16_t _hw_input_global_wrapper_stencil_108 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<48, 63>()); + bfloat16_t _hw_input_global_wrapper_stencil_109 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<64, 79>()); + bfloat16_t _hw_input_global_wrapper_stencil_110 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<80, 95>()); + bfloat16_t _hw_input_global_wrapper_stencil_111 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<96, 111>()); + bfloat16_t _hw_input_global_wrapper_stencil_112 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<112, 127>()); + bfloat16_t _hw_input_global_wrapper_stencil_113 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<128, 143>()); + bfloat16_t _hw_input_global_wrapper_stencil_114 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<144, 159>()); + bfloat16_t _hw_input_global_wrapper_stencil_115 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<160, 175>()); + bfloat16_t _hw_input_global_wrapper_stencil_116 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<176, 191>()); + bfloat16_t _hw_input_global_wrapper_stencil_117 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<192, 207>()); + bfloat16_t _hw_input_global_wrapper_stencil_118 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<208, 223>()); + bfloat16_t _hw_input_global_wrapper_stencil_119 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<224, 239>()); + bfloat16_t _hw_input_global_wrapper_stencil_120 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<240, 255>()); + bfloat16_t _hw_input_global_wrapper_stencil_121 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<256, 271>()); + bfloat16_t _hw_input_global_wrapper_stencil_122 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<272, 287>()); + bfloat16_t _hw_input_global_wrapper_stencil_123 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<288, 303>()); + bfloat16_t _hw_input_global_wrapper_stencil_124 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<304, 319>()); + bfloat16_t _hw_input_global_wrapper_stencil_125 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<320, 335>()); + bfloat16_t _hw_input_global_wrapper_stencil_126 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<336, 351>()); + bfloat16_t _hw_input_global_wrapper_stencil_127 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<352, 367>()); + bfloat16_t _hw_input_global_wrapper_stencil_128 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<368, 383>()); + bfloat16_t _hw_input_global_wrapper_stencil_129 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<384, 399>()); + bfloat16_t _hw_input_global_wrapper_stencil_130 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<400, 415>()); + bfloat16_t _hw_input_global_wrapper_stencil_131 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<416, 431>()); + bfloat16_t _hw_input_global_wrapper_stencil_132 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<432, 447>()); + bfloat16_t _hw_input_global_wrapper_stencil_133 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<448, 463>()); + bfloat16_t _hw_input_global_wrapper_stencil_134 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<464, 479>()); + bfloat16_t _hw_input_global_wrapper_stencil_135 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<480, 495>()); + bfloat16_t _hw_input_global_wrapper_stencil_136 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<496, 511>()); + bfloat16_t _hw_input_global_wrapper_stencil_137 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<512, 527>()); + bfloat16_t _hw_input_global_wrapper_stencil_138 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<528, 543>()); + bfloat16_t _hw_input_global_wrapper_stencil_139 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<544, 559>()); + bfloat16_t _hw_input_global_wrapper_stencil_140 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<560, 575>()); + bfloat16_t _hw_input_global_wrapper_stencil_141 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<576, 591>()); + bfloat16_t _hw_input_global_wrapper_stencil_142 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<592, 607>()); + bfloat16_t _hw_input_global_wrapper_stencil_143 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<608, 623>()); + bfloat16_t _hw_input_global_wrapper_stencil_144 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<624, 639>()); + bfloat16_t _hw_input_global_wrapper_stencil_145 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<640, 655>()); + bfloat16_t _hw_input_global_wrapper_stencil_146 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<656, 671>()); + bfloat16_t _hw_input_global_wrapper_stencil_147 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<672, 687>()); + bfloat16_t _hw_input_global_wrapper_stencil_148 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<688, 703>()); + bfloat16_t _hw_input_global_wrapper_stencil_149 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<704, 719>()); + bfloat16_t _hw_input_global_wrapper_stencil_150 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<720, 735>()); + bfloat16_t _hw_input_global_wrapper_stencil_151 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<736, 751>()); + bfloat16_t _hw_input_global_wrapper_stencil_152 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<752, 767>()); + bfloat16_t _hw_input_global_wrapper_stencil_153 = bfloat16_t::make_from_bits(hw_input_global_wrapper_stencil.extract<768, 783>()); + + bfloat16_t _non_local_means_sum_stencil_3 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _2446 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _2447 = _blur_d_stencil_100 * _2446; + bfloat16_t _2448 = exp_bf16(_2447); + bfloat16_t _2449 = _2448 * _hw_input_global_wrapper_stencil_105; + bfloat16_t _2450 = _blur_d_stencil_101 * _2446; + bfloat16_t _2451 = exp_bf16(_2450); + bfloat16_t _2452 = _2451 * _hw_input_global_wrapper_stencil_106; + bfloat16_t _2453 = _blur_d_stencil_102 * _2446; + bfloat16_t _2454 = exp_bf16(_2453); + bfloat16_t _2455 = _2454 * _hw_input_global_wrapper_stencil_107; + bfloat16_t _2456 = _blur_d_stencil_103 * _2446; + bfloat16_t _2457 = exp_bf16(_2456); + bfloat16_t _2458 = _2457 * _hw_input_global_wrapper_stencil_108; + bfloat16_t _2459 = _blur_d_stencil_104 * _2446; + bfloat16_t _2460 = exp_bf16(_2459); + bfloat16_t _2461 = _2460 * _hw_input_global_wrapper_stencil_109; + bfloat16_t _2462 = _blur_d_stencil_105 * _2446; + bfloat16_t _2463 = exp_bf16(_2462); + bfloat16_t _2464 = _2463 * _hw_input_global_wrapper_stencil_110; + bfloat16_t _2465 = _blur_d_stencil_106 * _2446; + bfloat16_t _2466 = exp_bf16(_2465); + bfloat16_t _2467 = _2466 * _hw_input_global_wrapper_stencil_111; + bfloat16_t _2468 = _blur_d_stencil_107 * _2446; + bfloat16_t _2469 = exp_bf16(_2468); + bfloat16_t _2470 = _2469 * _hw_input_global_wrapper_stencil_112; + bfloat16_t _2471 = _blur_d_stencil_108 * _2446; + bfloat16_t _2472 = exp_bf16(_2471); + bfloat16_t _2473 = _2472 * _hw_input_global_wrapper_stencil_113; + bfloat16_t _2474 = _blur_d_stencil_109 * _2446; + bfloat16_t _2475 = exp_bf16(_2474); + bfloat16_t _2476 = _2475 * _hw_input_global_wrapper_stencil_114; + bfloat16_t _2477 = _blur_d_stencil_110 * _2446; + bfloat16_t _2478 = exp_bf16(_2477); + bfloat16_t _2479 = _2478 * _hw_input_global_wrapper_stencil_115; + bfloat16_t _2480 = _blur_d_stencil_111 * _2446; + bfloat16_t _2481 = exp_bf16(_2480); + bfloat16_t _2482 = _2481 * _hw_input_global_wrapper_stencil_116; + bfloat16_t _2483 = _blur_d_stencil_112 * _2446; + bfloat16_t _2484 = exp_bf16(_2483); + bfloat16_t _2485 = _2484 * _hw_input_global_wrapper_stencil_117; + bfloat16_t _2486 = _blur_d_stencil_113 * _2446; + bfloat16_t _2487 = exp_bf16(_2486); + bfloat16_t _2488 = _2487 * _hw_input_global_wrapper_stencil_118; + bfloat16_t _2489 = _blur_d_stencil_114 * _2446; + bfloat16_t _2490 = exp_bf16(_2489); + bfloat16_t _2491 = _2490 * _hw_input_global_wrapper_stencil_119; + bfloat16_t _2492 = _blur_d_stencil_115 * _2446; + bfloat16_t _2493 = exp_bf16(_2492); + bfloat16_t _2494 = _2493 * _hw_input_global_wrapper_stencil_120; + bfloat16_t _2495 = _blur_d_stencil_116 * _2446; + bfloat16_t _2496 = exp_bf16(_2495); + bfloat16_t _2497 = _2496 * _hw_input_global_wrapper_stencil_121; + bfloat16_t _2498 = _blur_d_stencil_117 * _2446; + bfloat16_t _2499 = exp_bf16(_2498); + bfloat16_t _2500 = _2499 * _hw_input_global_wrapper_stencil_122; + bfloat16_t _2501 = _blur_d_stencil_118 * _2446; + bfloat16_t _2502 = exp_bf16(_2501); + bfloat16_t _2503 = _2502 * _hw_input_global_wrapper_stencil_123; + bfloat16_t _2504 = _blur_d_stencil_119 * _2446; + bfloat16_t _2505 = exp_bf16(_2504); + bfloat16_t _2506 = _2505 * _hw_input_global_wrapper_stencil_124; + bfloat16_t _2507 = _blur_d_stencil_120 * _2446; + bfloat16_t _2508 = exp_bf16(_2507); + bfloat16_t _2509 = _2508 * _hw_input_global_wrapper_stencil_125; + bfloat16_t _2510 = _blur_d_stencil_121 * _2446; + bfloat16_t _2511 = exp_bf16(_2510); + bfloat16_t _2512 = _2511 * _hw_input_global_wrapper_stencil_126; + bfloat16_t _2513 = _blur_d_stencil_122 * _2446; + bfloat16_t _2514 = exp_bf16(_2513); + bfloat16_t _2515 = _2514 * _hw_input_global_wrapper_stencil_127; + bfloat16_t _2516 = _blur_d_stencil_123 * _2446; + bfloat16_t _2517 = exp_bf16(_2516); + bfloat16_t _2518 = _2517 * _hw_input_global_wrapper_stencil_128; + bfloat16_t _2519 = _blur_d_stencil_124 * _2446; + bfloat16_t _2520 = exp_bf16(_2519); + bfloat16_t _2521 = _2520 * _hw_input_global_wrapper_stencil_129; + bfloat16_t _2522 = _blur_d_stencil_125 * _2446; + bfloat16_t _2523 = exp_bf16(_2522); + bfloat16_t _2524 = _2523 * _hw_input_global_wrapper_stencil_130; + bfloat16_t _2525 = _blur_d_stencil_126 * _2446; + bfloat16_t _2526 = exp_bf16(_2525); + bfloat16_t _2527 = _2526 * _hw_input_global_wrapper_stencil_131; + bfloat16_t _2528 = _blur_d_stencil_127 * _2446; + bfloat16_t _2529 = exp_bf16(_2528); + bfloat16_t _2530 = _2529 * _hw_input_global_wrapper_stencil_132; + bfloat16_t _2531 = _blur_d_stencil_128 * _2446; + bfloat16_t _2532 = exp_bf16(_2531); + bfloat16_t _2533 = _2532 * _hw_input_global_wrapper_stencil_133; + bfloat16_t _2534 = _blur_d_stencil_129 * _2446; + bfloat16_t _2535 = exp_bf16(_2534); + bfloat16_t _2536 = _2535 * _hw_input_global_wrapper_stencil_134; + bfloat16_t _2537 = _blur_d_stencil_130 * _2446; + bfloat16_t _2538 = exp_bf16(_2537); + bfloat16_t _2539 = _2538 * _hw_input_global_wrapper_stencil_135; + bfloat16_t _2540 = _blur_d_stencil_131 * _2446; + bfloat16_t _2541 = exp_bf16(_2540); + bfloat16_t _2542 = _2541 * _hw_input_global_wrapper_stencil_136; + bfloat16_t _2543 = _blur_d_stencil_132 * _2446; + bfloat16_t _2544 = exp_bf16(_2543); + bfloat16_t _2545 = _2544 * _hw_input_global_wrapper_stencil_137; + bfloat16_t _2546 = _blur_d_stencil_133 * _2446; + bfloat16_t _2547 = exp_bf16(_2546); + bfloat16_t _2548 = _2547 * _hw_input_global_wrapper_stencil_138; + bfloat16_t _2549 = _blur_d_stencil_134 * _2446; + bfloat16_t _2550 = exp_bf16(_2549); + bfloat16_t _2551 = _2550 * _hw_input_global_wrapper_stencil_139; + bfloat16_t _2552 = _blur_d_stencil_135 * _2446; + bfloat16_t _2553 = exp_bf16(_2552); + bfloat16_t _2554 = _2553 * _hw_input_global_wrapper_stencil_140; + bfloat16_t _2555 = _blur_d_stencil_136 * _2446; + bfloat16_t _2556 = exp_bf16(_2555); + bfloat16_t _2557 = _2556 * _hw_input_global_wrapper_stencil_141; + bfloat16_t _2558 = _blur_d_stencil_137 * _2446; + bfloat16_t _2559 = exp_bf16(_2558); + bfloat16_t _2560 = _2559 * _hw_input_global_wrapper_stencil_142; + bfloat16_t _2561 = _blur_d_stencil_138 * _2446; + bfloat16_t _2562 = exp_bf16(_2561); + bfloat16_t _2563 = _2562 * _hw_input_global_wrapper_stencil_143; + bfloat16_t _2564 = _blur_d_stencil_139 * _2446; + bfloat16_t _2565 = exp_bf16(_2564); + bfloat16_t _2566 = _2565 * _hw_input_global_wrapper_stencil_144; + bfloat16_t _2567 = _blur_d_stencil_140 * _2446; + bfloat16_t _2568 = exp_bf16(_2567); + bfloat16_t _2569 = _2568 * _hw_input_global_wrapper_stencil_145; + bfloat16_t _2570 = _blur_d_stencil_141 * _2446; + bfloat16_t _2571 = exp_bf16(_2570); + bfloat16_t _2572 = _2571 * _hw_input_global_wrapper_stencil_146; + bfloat16_t _2573 = _blur_d_stencil_142 * _2446; + bfloat16_t _2574 = exp_bf16(_2573); + bfloat16_t _2575 = _2574 * _hw_input_global_wrapper_stencil_147; + bfloat16_t _2576 = _blur_d_stencil_143 * _2446; + bfloat16_t _2577 = exp_bf16(_2576); + bfloat16_t _2578 = _2577 * _hw_input_global_wrapper_stencil_148; + bfloat16_t _2579 = _blur_d_stencil_144 * _2446; + bfloat16_t _2580 = exp_bf16(_2579); + bfloat16_t _2581 = _2580 * _hw_input_global_wrapper_stencil_149; + bfloat16_t _2582 = _blur_d_stencil_145 * _2446; + bfloat16_t _2583 = exp_bf16(_2582); + bfloat16_t _2584 = _2583 * _hw_input_global_wrapper_stencil_150; + bfloat16_t _2585 = _blur_d_stencil_146 * _2446; + bfloat16_t _2586 = exp_bf16(_2585); + bfloat16_t _2587 = _2586 * _hw_input_global_wrapper_stencil_151; + bfloat16_t _2588 = _blur_d_stencil_147 * _2446; + bfloat16_t _2589 = exp_bf16(_2588); + bfloat16_t _2590 = _2589 * _hw_input_global_wrapper_stencil_152; + bfloat16_t _2591 = _blur_d_stencil_148 * _2446; + bfloat16_t _2592 = exp_bf16(_2591); + bfloat16_t _2593 = _2592 * _hw_input_global_wrapper_stencil_153; + bfloat16_t _2594 = _non_local_means_sum_stencil_3 + _2593; + bfloat16_t _2595 = _2590 + _2594; + bfloat16_t _2596 = _2587 + _2595; + bfloat16_t _2597 = _2584 + _2596; + bfloat16_t _2598 = _2581 + _2597; + bfloat16_t _2599 = _2578 + _2598; + bfloat16_t _2600 = _2575 + _2599; + bfloat16_t _2601 = _2572 + _2600; + bfloat16_t _2602 = _2569 + _2601; + bfloat16_t _2603 = _2566 + _2602; + bfloat16_t _2604 = _2563 + _2603; + bfloat16_t _2605 = _2560 + _2604; + bfloat16_t _2606 = _2557 + _2605; + bfloat16_t _2607 = _2554 + _2606; + bfloat16_t _2608 = _2551 + _2607; + bfloat16_t _2609 = _2548 + _2608; + bfloat16_t _2610 = _2545 + _2609; + bfloat16_t _2611 = _2542 + _2610; + bfloat16_t _2612 = _2539 + _2611; + bfloat16_t _2613 = _2536 + _2612; + bfloat16_t _2614 = _2533 + _2613; + bfloat16_t _2615 = _2530 + _2614; + bfloat16_t _2616 = _2527 + _2615; + bfloat16_t _2617 = _2524 + _2616; + bfloat16_t _2618 = _2521 + _2617; + bfloat16_t _2619 = _2518 + _2618; + bfloat16_t _2620 = _2515 + _2619; + bfloat16_t _2621 = _2512 + _2620; + bfloat16_t _2622 = _2509 + _2621; + bfloat16_t _2623 = _2506 + _2622; + bfloat16_t _2624 = _2503 + _2623; + bfloat16_t _2625 = _2500 + _2624; + bfloat16_t _2626 = _2497 + _2625; + bfloat16_t _2627 = _2494 + _2626; + bfloat16_t _2628 = _2491 + _2627; + bfloat16_t _2629 = _2488 + _2628; + bfloat16_t _2630 = _2485 + _2629; + bfloat16_t _2631 = _2482 + _2630; + bfloat16_t _2632 = _2479 + _2631; + bfloat16_t _2633 = _2476 + _2632; + bfloat16_t _2634 = _2473 + _2633; + bfloat16_t _2635 = _2470 + _2634; + bfloat16_t _2636 = _2467 + _2635; + bfloat16_t _2637 = _2464 + _2636; + bfloat16_t _2638 = _2461 + _2637; + bfloat16_t _2639 = _2458 + _2638; + bfloat16_t _2640 = _2455 + _2639; + bfloat16_t _2641 = _2452 + _2640; + bfloat16_t _2642 = _2449 + _2641; + return _2642; +} + +//store is: non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) = (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 6)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 5)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 4)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 3)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 2)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 1)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 6, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 5, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 4, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 2, 0)*-1.414062h)) + (exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 1, 0)*-1.414062h)) + (non_local_means_sum.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 3) + exp_bf16((blur_d.stencil(non_local_means_sum_s1_x, non_local_means_sum_s1_y, 0, 0)*-1.414062h))))))))))))))))))))))))))))))))))))))))))))))))))) +hw_uint<16> hcompute_non_local_means_sum_stencil_7(hw_uint<784>& blur_d_stencil, hw_uint<16>& non_local_means_sum_stencil) { + bfloat16_t _blur_d_stencil_149 = bfloat16_t::make_from_bits(blur_d_stencil.extract<0, 15>()); + bfloat16_t _blur_d_stencil_150 = bfloat16_t::make_from_bits(blur_d_stencil.extract<16, 31>()); + bfloat16_t _blur_d_stencil_151 = bfloat16_t::make_from_bits(blur_d_stencil.extract<32, 47>()); + bfloat16_t _blur_d_stencil_152 = bfloat16_t::make_from_bits(blur_d_stencil.extract<48, 63>()); + bfloat16_t _blur_d_stencil_153 = bfloat16_t::make_from_bits(blur_d_stencil.extract<64, 79>()); + bfloat16_t _blur_d_stencil_154 = bfloat16_t::make_from_bits(blur_d_stencil.extract<80, 95>()); + bfloat16_t _blur_d_stencil_155 = bfloat16_t::make_from_bits(blur_d_stencil.extract<96, 111>()); + bfloat16_t _blur_d_stencil_156 = bfloat16_t::make_from_bits(blur_d_stencil.extract<112, 127>()); + bfloat16_t _blur_d_stencil_157 = bfloat16_t::make_from_bits(blur_d_stencil.extract<128, 143>()); + bfloat16_t _blur_d_stencil_158 = bfloat16_t::make_from_bits(blur_d_stencil.extract<144, 159>()); + bfloat16_t _blur_d_stencil_159 = bfloat16_t::make_from_bits(blur_d_stencil.extract<160, 175>()); + bfloat16_t _blur_d_stencil_160 = bfloat16_t::make_from_bits(blur_d_stencil.extract<176, 191>()); + bfloat16_t _blur_d_stencil_161 = bfloat16_t::make_from_bits(blur_d_stencil.extract<192, 207>()); + bfloat16_t _blur_d_stencil_162 = bfloat16_t::make_from_bits(blur_d_stencil.extract<208, 223>()); + bfloat16_t _blur_d_stencil_163 = bfloat16_t::make_from_bits(blur_d_stencil.extract<224, 239>()); + bfloat16_t _blur_d_stencil_164 = bfloat16_t::make_from_bits(blur_d_stencil.extract<240, 255>()); + bfloat16_t _blur_d_stencil_165 = bfloat16_t::make_from_bits(blur_d_stencil.extract<256, 271>()); + bfloat16_t _blur_d_stencil_166 = bfloat16_t::make_from_bits(blur_d_stencil.extract<272, 287>()); + bfloat16_t _blur_d_stencil_167 = bfloat16_t::make_from_bits(blur_d_stencil.extract<288, 303>()); + bfloat16_t _blur_d_stencil_168 = bfloat16_t::make_from_bits(blur_d_stencil.extract<304, 319>()); + bfloat16_t _blur_d_stencil_169 = bfloat16_t::make_from_bits(blur_d_stencil.extract<320, 335>()); + bfloat16_t _blur_d_stencil_170 = bfloat16_t::make_from_bits(blur_d_stencil.extract<336, 351>()); + bfloat16_t _blur_d_stencil_171 = bfloat16_t::make_from_bits(blur_d_stencil.extract<352, 367>()); + bfloat16_t _blur_d_stencil_172 = bfloat16_t::make_from_bits(blur_d_stencil.extract<368, 383>()); + bfloat16_t _blur_d_stencil_173 = bfloat16_t::make_from_bits(blur_d_stencil.extract<384, 399>()); + bfloat16_t _blur_d_stencil_174 = bfloat16_t::make_from_bits(blur_d_stencil.extract<400, 415>()); + bfloat16_t _blur_d_stencil_175 = bfloat16_t::make_from_bits(blur_d_stencil.extract<416, 431>()); + bfloat16_t _blur_d_stencil_176 = bfloat16_t::make_from_bits(blur_d_stencil.extract<432, 447>()); + bfloat16_t _blur_d_stencil_177 = bfloat16_t::make_from_bits(blur_d_stencil.extract<448, 463>()); + bfloat16_t _blur_d_stencil_178 = bfloat16_t::make_from_bits(blur_d_stencil.extract<464, 479>()); + bfloat16_t _blur_d_stencil_179 = bfloat16_t::make_from_bits(blur_d_stencil.extract<480, 495>()); + bfloat16_t _blur_d_stencil_180 = bfloat16_t::make_from_bits(blur_d_stencil.extract<496, 511>()); + bfloat16_t _blur_d_stencil_181 = bfloat16_t::make_from_bits(blur_d_stencil.extract<512, 527>()); + bfloat16_t _blur_d_stencil_182 = bfloat16_t::make_from_bits(blur_d_stencil.extract<528, 543>()); + bfloat16_t _blur_d_stencil_183 = bfloat16_t::make_from_bits(blur_d_stencil.extract<544, 559>()); + bfloat16_t _blur_d_stencil_184 = bfloat16_t::make_from_bits(blur_d_stencil.extract<560, 575>()); + bfloat16_t _blur_d_stencil_185 = bfloat16_t::make_from_bits(blur_d_stencil.extract<576, 591>()); + bfloat16_t _blur_d_stencil_186 = bfloat16_t::make_from_bits(blur_d_stencil.extract<592, 607>()); + bfloat16_t _blur_d_stencil_187 = bfloat16_t::make_from_bits(blur_d_stencil.extract<608, 623>()); + bfloat16_t _blur_d_stencil_188 = bfloat16_t::make_from_bits(blur_d_stencil.extract<624, 639>()); + bfloat16_t _blur_d_stencil_189 = bfloat16_t::make_from_bits(blur_d_stencil.extract<640, 655>()); + bfloat16_t _blur_d_stencil_190 = bfloat16_t::make_from_bits(blur_d_stencil.extract<656, 671>()); + bfloat16_t _blur_d_stencil_191 = bfloat16_t::make_from_bits(blur_d_stencil.extract<672, 687>()); + bfloat16_t _blur_d_stencil_192 = bfloat16_t::make_from_bits(blur_d_stencil.extract<688, 703>()); + bfloat16_t _blur_d_stencil_193 = bfloat16_t::make_from_bits(blur_d_stencil.extract<704, 719>()); + bfloat16_t _blur_d_stencil_194 = bfloat16_t::make_from_bits(blur_d_stencil.extract<720, 735>()); + bfloat16_t _blur_d_stencil_195 = bfloat16_t::make_from_bits(blur_d_stencil.extract<736, 751>()); + bfloat16_t _blur_d_stencil_196 = bfloat16_t::make_from_bits(blur_d_stencil.extract<752, 767>()); + bfloat16_t _blur_d_stencil_197 = bfloat16_t::make_from_bits(blur_d_stencil.extract<768, 783>()); + + bfloat16_t _non_local_means_sum_stencil_4 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + + bfloat16_t _3150 = bfloat_from_bits(3216310272 /* -1.41406 */); + bfloat16_t _3151 = _blur_d_stencil_149 * _3150; + bfloat16_t _3152 = exp_bf16(_3151); + bfloat16_t _3153 = _blur_d_stencil_150 * _3150; + bfloat16_t _3154 = exp_bf16(_3153); + bfloat16_t _3155 = _blur_d_stencil_151 * _3150; + bfloat16_t _3156 = exp_bf16(_3155); + bfloat16_t _3157 = _blur_d_stencil_152 * _3150; + bfloat16_t _3158 = exp_bf16(_3157); + bfloat16_t _3159 = _blur_d_stencil_153 * _3150; + bfloat16_t _3160 = exp_bf16(_3159); + bfloat16_t _3161 = _blur_d_stencil_154 * _3150; + bfloat16_t _3162 = exp_bf16(_3161); + bfloat16_t _3163 = _blur_d_stencil_155 * _3150; + bfloat16_t _3164 = exp_bf16(_3163); + bfloat16_t _3165 = _blur_d_stencil_156 * _3150; + bfloat16_t _3166 = exp_bf16(_3165); + bfloat16_t _3167 = _blur_d_stencil_157 * _3150; + bfloat16_t _3168 = exp_bf16(_3167); + bfloat16_t _3169 = _blur_d_stencil_158 * _3150; + bfloat16_t _3170 = exp_bf16(_3169); + bfloat16_t _3171 = _blur_d_stencil_159 * _3150; + bfloat16_t _3172 = exp_bf16(_3171); + bfloat16_t _3173 = _blur_d_stencil_160 * _3150; + bfloat16_t _3174 = exp_bf16(_3173); + bfloat16_t _3175 = _blur_d_stencil_161 * _3150; + bfloat16_t _3176 = exp_bf16(_3175); + bfloat16_t _3177 = _blur_d_stencil_162 * _3150; + bfloat16_t _3178 = exp_bf16(_3177); + bfloat16_t _3179 = _blur_d_stencil_163 * _3150; + bfloat16_t _3180 = exp_bf16(_3179); + bfloat16_t _3181 = _blur_d_stencil_164 * _3150; + bfloat16_t _3182 = exp_bf16(_3181); + bfloat16_t _3183 = _blur_d_stencil_165 * _3150; + bfloat16_t _3184 = exp_bf16(_3183); + bfloat16_t _3185 = _blur_d_stencil_166 * _3150; + bfloat16_t _3186 = exp_bf16(_3185); + bfloat16_t _3187 = _blur_d_stencil_167 * _3150; + bfloat16_t _3188 = exp_bf16(_3187); + bfloat16_t _3189 = _blur_d_stencil_168 * _3150; + bfloat16_t _3190 = exp_bf16(_3189); + bfloat16_t _3191 = _blur_d_stencil_169 * _3150; + bfloat16_t _3192 = exp_bf16(_3191); + bfloat16_t _3193 = _blur_d_stencil_170 * _3150; + bfloat16_t _3194 = exp_bf16(_3193); + bfloat16_t _3195 = _blur_d_stencil_171 * _3150; + bfloat16_t _3196 = exp_bf16(_3195); + bfloat16_t _3197 = _blur_d_stencil_172 * _3150; + bfloat16_t _3198 = exp_bf16(_3197); + bfloat16_t _3199 = _blur_d_stencil_173 * _3150; + bfloat16_t _3200 = exp_bf16(_3199); + bfloat16_t _3201 = _blur_d_stencil_174 * _3150; + bfloat16_t _3202 = exp_bf16(_3201); + bfloat16_t _3203 = _blur_d_stencil_175 * _3150; + bfloat16_t _3204 = exp_bf16(_3203); + bfloat16_t _3205 = _blur_d_stencil_176 * _3150; + bfloat16_t _3206 = exp_bf16(_3205); + bfloat16_t _3207 = _blur_d_stencil_177 * _3150; + bfloat16_t _3208 = exp_bf16(_3207); + bfloat16_t _3209 = _blur_d_stencil_178 * _3150; + bfloat16_t _3210 = exp_bf16(_3209); + bfloat16_t _3211 = _blur_d_stencil_179 * _3150; + bfloat16_t _3212 = exp_bf16(_3211); + bfloat16_t _3213 = _blur_d_stencil_180 * _3150; + bfloat16_t _3214 = exp_bf16(_3213); + bfloat16_t _3215 = _blur_d_stencil_181 * _3150; + bfloat16_t _3216 = exp_bf16(_3215); + bfloat16_t _3217 = _blur_d_stencil_182 * _3150; + bfloat16_t _3218 = exp_bf16(_3217); + bfloat16_t _3219 = _blur_d_stencil_183 * _3150; + bfloat16_t _3220 = exp_bf16(_3219); + bfloat16_t _3221 = _blur_d_stencil_184 * _3150; + bfloat16_t _3222 = exp_bf16(_3221); + bfloat16_t _3223 = _blur_d_stencil_185 * _3150; + bfloat16_t _3224 = exp_bf16(_3223); + bfloat16_t _3225 = _blur_d_stencil_186 * _3150; + bfloat16_t _3226 = exp_bf16(_3225); + bfloat16_t _3227 = _blur_d_stencil_187 * _3150; + bfloat16_t _3228 = exp_bf16(_3227); + bfloat16_t _3229 = _blur_d_stencil_188 * _3150; + bfloat16_t _3230 = exp_bf16(_3229); + bfloat16_t _3231 = _blur_d_stencil_189 * _3150; + bfloat16_t _3232 = exp_bf16(_3231); + bfloat16_t _3233 = _blur_d_stencil_190 * _3150; + bfloat16_t _3234 = exp_bf16(_3233); + bfloat16_t _3235 = _blur_d_stencil_191 * _3150; + bfloat16_t _3236 = exp_bf16(_3235); + bfloat16_t _3237 = _blur_d_stencil_192 * _3150; + bfloat16_t _3238 = exp_bf16(_3237); + bfloat16_t _3239 = _blur_d_stencil_193 * _3150; + bfloat16_t _3240 = exp_bf16(_3239); + bfloat16_t _3241 = _blur_d_stencil_194 * _3150; + bfloat16_t _3242 = exp_bf16(_3241); + bfloat16_t _3243 = _blur_d_stencil_195 * _3150; + bfloat16_t _3244 = exp_bf16(_3243); + bfloat16_t _3245 = _blur_d_stencil_196 * _3150; + bfloat16_t _3246 = exp_bf16(_3245); + bfloat16_t _3247 = _blur_d_stencil_197 * _3150; + bfloat16_t _3248 = exp_bf16(_3247); + bfloat16_t _3249 = _non_local_means_sum_stencil_4 + _3248; + bfloat16_t _3250 = _3246 + _3249; + bfloat16_t _3251 = _3244 + _3250; + bfloat16_t _3252 = _3242 + _3251; + bfloat16_t _3253 = _3240 + _3252; + bfloat16_t _3254 = _3238 + _3253; + bfloat16_t _3255 = _3236 + _3254; + bfloat16_t _3256 = _3234 + _3255; + bfloat16_t _3257 = _3232 + _3256; + bfloat16_t _3258 = _3230 + _3257; + bfloat16_t _3259 = _3228 + _3258; + bfloat16_t _3260 = _3226 + _3259; + bfloat16_t _3261 = _3224 + _3260; + bfloat16_t _3262 = _3222 + _3261; + bfloat16_t _3263 = _3220 + _3262; + bfloat16_t _3264 = _3218 + _3263; + bfloat16_t _3265 = _3216 + _3264; + bfloat16_t _3266 = _3214 + _3265; + bfloat16_t _3267 = _3212 + _3266; + bfloat16_t _3268 = _3210 + _3267; + bfloat16_t _3269 = _3208 + _3268; + bfloat16_t _3270 = _3206 + _3269; + bfloat16_t _3271 = _3204 + _3270; + bfloat16_t _3272 = _3202 + _3271; + bfloat16_t _3273 = _3200 + _3272; + bfloat16_t _3274 = _3198 + _3273; + bfloat16_t _3275 = _3196 + _3274; + bfloat16_t _3276 = _3194 + _3275; + bfloat16_t _3277 = _3192 + _3276; + bfloat16_t _3278 = _3190 + _3277; + bfloat16_t _3279 = _3188 + _3278; + bfloat16_t _3280 = _3186 + _3279; + bfloat16_t _3281 = _3184 + _3280; + bfloat16_t _3282 = _3182 + _3281; + bfloat16_t _3283 = _3180 + _3282; + bfloat16_t _3284 = _3178 + _3283; + bfloat16_t _3285 = _3176 + _3284; + bfloat16_t _3286 = _3174 + _3285; + bfloat16_t _3287 = _3172 + _3286; + bfloat16_t _3288 = _3170 + _3287; + bfloat16_t _3289 = _3168 + _3288; + bfloat16_t _3290 = _3166 + _3289; + bfloat16_t _3291 = _3164 + _3290; + bfloat16_t _3292 = _3162 + _3291; + bfloat16_t _3293 = _3160 + _3292; + bfloat16_t _3294 = _3158 + _3293; + bfloat16_t _3295 = _3156 + _3294; + bfloat16_t _3296 = _3154 + _3295; + bfloat16_t _3297 = _3152 + _3296; + return _3297; +} + +//store is: hw_output.stencil(0, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 0)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_5 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_6 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _3644 = _non_local_means_sum_stencil_5 / _non_local_means_sum_stencil_6; + bfloat16_t _3645 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _3646 = min(_3644, _3645); + bfloat16_t _3647 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _3648 = max(_3646, _3647); + bfloat16_t _3649 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _3650 = _3648 * _3649; + return _3650; +} + +//store is: hw_output.stencil(1, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 1)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_1(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_7 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_8 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _3667 = _non_local_means_sum_stencil_7 / _non_local_means_sum_stencil_8; + bfloat16_t _3668 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _3669 = min(_3667, _3668); + bfloat16_t _3670 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _3671 = max(_3669, _3670); + bfloat16_t _3672 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _3673 = _3671 * _3672; + return _3673; +} + +//store is: hw_output.stencil(2, hw_output_s0_x_xi, hw_output_s0_y_yi) = (max(min((non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 2)/non_local_means_sum.stencil(hw_output_s0_x_xi, hw_output_s0_y_yi, 3)), 1.000000h), 0.000000h)*255.000000h) +hw_uint<16> hcompute_hw_output_stencil_2(hw_uint<32>& non_local_means_sum_stencil) { + bfloat16_t _non_local_means_sum_stencil_10 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<0, 15>()); + bfloat16_t _non_local_means_sum_stencil_9 = bfloat16_t::make_from_bits(non_local_means_sum_stencil.extract<16, 31>()); + + bfloat16_t _3690 = _non_local_means_sum_stencil_9 / _non_local_means_sum_stencil_10; + bfloat16_t _3691 = bfloat_from_bits(1065353216 /* 1 */); + bfloat16_t _3692 = min(_3690, _3691); + bfloat16_t _3693 = bfloat_from_bits(0 /* 0 */); + bfloat16_t _3694 = max(_3692, _3693); + bfloat16_t _3695 = bfloat_from_bits(1132396544 /* 255 */); + bfloat16_t _3696 = _3694 * _3695; + return _3696; +} + diff --git a/options.cpp b/options.cpp index 035fd86f5..a348aa508 100644 --- a/options.cpp +++ b/options.cpp @@ -14,3 +14,72 @@ void CodegenOptions::add_memory_hierarchy(const std::string& level) { LakeCollateral mem(level); mem_hierarchy.insert({level, mem}); } + +string CodegenOptions::get_hierarchy_level(int capacity) { + map capacity2level; + for (auto it: mem_hierarchy) { + string level = it.first; + capacity2level[it.second.get_single_tile_capacity()] = level; + } + return capacity2level.lower_bound(capacity)->second; + +} + +LakeCollateral create_single_port_wide_fetch_memory(int fetch_width, int capacity, int SIPO_num) { + LakeCollateral mem; + + //Misc information + mem.set_fetch_width(fetch_width); + mem.set_max_chaining(4); + mem.set_iteration_level(6); + mem.set_counter_ub(65535); + mem.set_multi_sram_accessor(true); + mem.set_dual_port_sram(false); + mem.set_wire_chain_en(true); + + mem.add_memory_component("agg", false); + mem.add_read_port("agg", fetch_width); + mem.add_write_port("agg", 1); + mem.set_capacity("agg", 16); + mem.make_duplication("agg", SIPO_num); + + mem.add_memory_component("tb", false); + mem.add_read_port("tb", 1); + mem.add_write_port("tb", fetch_width); + mem.set_capacity("tb", 16); + mem.make_duplication("tb", fetch_width - SIPO_num); + + mem.add_memory_component("sram", true); + mem.add_read_port("sram", fetch_width); + mem.add_write_port("sram", fetch_width); + mem.set_capacity("sram", capacity); + + mem.wire_together("agg", "sram"); + mem.wire_together("sram", "tb"); + + mem.infer_word_width(); + + return mem; +} + +LakeCollateral create_dual_port_memory(int capacity) { + LakeCollateral mem; + + //Misc information + mem.set_fetch_width(1); + mem.set_max_chaining(4); + mem.set_iteration_level(6); + mem.set_counter_ub(65535); + mem.set_multi_sram_accessor(true); + mem.set_dual_port_sram(false); + mem.set_wire_chain_en(true); + + mem.add_memory_component("mem", false); + mem.add_read_port("mem", 1); + mem.add_write_port("mem", 1); + mem.set_capacity("mem", capacity); + + mem.infer_word_width(); + + return mem; +} diff --git a/options.h b/options.h index 7d45dc781..a2d0ba6e7 100644 --- a/options.h +++ b/options.h @@ -50,8 +50,8 @@ enum ScheduleAlgorithm { enum DNNScheduleAlgorithm { ASPLOS_SCHEDULE, //An over optimized schedule which will be refactored - ISCA_SCHEDULE, //new schedule with refactor VANILLA_DB_SCHEDULE, + ISCA_SCHEDULE, //new schedule with refactor SEQUENTIAL_SCHEDULE }; @@ -105,12 +105,19 @@ struct RTLOptions { hls_clock_target_Hz(250000000) {} }; + struct LakeCollateral { std::unordered_map word_width; std::unordered_map bank_num; std::unordered_map capacity; std::unordered_map in_port_width; std::unordered_map out_port_width; + std::unordered_map read_port; + std::unordered_map write_port; + + //Single port means read write share the same physical port + std::unordered_map single_port; + std::set controller_name; //use for identify the controller name in configuration int fetch_width; int max_chaining; int iteration_level; @@ -119,21 +126,27 @@ struct LakeCollateral { bool dual_port_sram; bool wire_chain_en; + LakeCollateral() {} + //TODO: use the collateral kavya generated - LakeCollateral(string level = "mem"): - fetch_width(4), + LakeCollateral(string level): max_chaining(4), iteration_level(6), counter_ub(65535), multi_sram_accessor(true), dual_port_sram(false), - wire_chain_en(true), - word_width({{"agg", 1}, {"sram", 4}, {"tb", 1}}), - in_port_width({{"agg", 1}, {"sram", 4}, {"tb", 4}}), - out_port_width({{"agg", 4}, {"sram", 4}, {"tb", 1}}), - bank_num({{"agg", 2}, {"sram", 1}, {"tb", 2}}), - capacity({{"agg", 16}, {"sram", 512}, {"tb", 16}}) { - if (level == "regfile") { + wire_chain_en(false) { + if (level == "mem") { + fetch_width = 4; + max_chaining = 4; + iteration_level = 6; + capacity = {{"agg", 16}, {"sram", 512}, {"tb", 16}}; + in_port_width = {{"agg", 1}, {"sram", 4}, {"tb", 4}}; + out_port_width = {{"agg", 4}, {"sram", 4}, {"tb", 1}}; + word_width = {{"agg", 1}, {"sram", 4}, {"tb", 1}}; + controller_name = {"agg", "sram", "tb"}; + bank_num = {{"agg", 2}, {"sram", 1}, {"tb", 2}}; + } else if (level == "regfile") { fetch_width = 1; max_chaining = 1; word_width = {{"regfile", 1}}; @@ -141,6 +154,7 @@ struct LakeCollateral { out_port_width = {{"regfile", 1}}; bank_num = {{"regfile", 1}}; capacity = {{"regfile", 32}}; + controller_name = {"regfile"}; iteration_level = 3; } else if (level == "glb") { @@ -151,11 +165,155 @@ struct LakeCollateral { out_port_width = {{"glb", 1}}; bank_num = {{"glb", 1}}; capacity = {{"glb", 131072}}; + controller_name = {"glb"}; } else if (level != "mem") { cout << "\t\tERROR: Memory component not identified" << endl; assert(false); } + } + + void add_memory_component(string name, bool is_single_port) { + controller_name.insert(name); + single_port.insert({name, is_single_port}); + bank_num.insert({name, 1}); + }; + + void add_read_port(string name, int port_width) { + assert(controller_name.count(name)); + assert(out_port_width.count(name) == 0); + out_port_width.insert({name, port_width}); + } + + void add_write_port(string name, int port_width) { + assert(controller_name.count(name)); + assert(in_port_width.count(name) == 0); + in_port_width.insert({name, port_width}); + } + + void make_duplication(string name, int num) { + assert(controller_name.count(name)); + assert(bank_num.at(name) == 1); + bank_num.insert({name, num}); + } + + void set_capacity(string name, int size) { + assert(controller_name.count(name)); + assert(bank_num.at(name) == 1); + capacity.insert({name, size}); + } + + void infer_word_width() { + for (auto mem: controller_name) { + int width = + std::gcd(in_port_width.at(mem), out_port_width.at(mem)); + word_width.insert({mem, width}); } + } + + void wire_together(string prod, string cons) { + read_port[prod] = cons; + write_port[cons] = prod; + } + + + void set_fetch_width(int a){ + fetch_width = a; + } + void set_max_chaining(int a){ + max_chaining= a; + } + void set_iteration_level(int a){ + iteration_level = a; + } + void set_counter_ub(int a){ + counter_ub = a; + } + + void set_multi_sram_accessor(bool a){ + multi_sram_accessor = a; + } + void set_dual_port_sram(bool a){ + dual_port_sram = a; + } + void set_wire_chain_en(bool a){ + wire_chain_en = a; + } + + void set_word_width(std::unordered_map a){ + word_width = a; + } + + void set_capacity(std::unordered_map a){ + capacity = a; + } + void set_in_port_width(std::unordered_map a){ + in_port_width = a; + } + void set_out_port_width(std::unordered_map a){ + out_port_width = a; + } + void set_controller_name(std::set a){ + controller_name = a; + } + + + void print_points(){ + cout << " # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ## 3 ## # # 3 3 # 3 # # 3 3 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # " << endl; +// cout << " # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ## 3 ## # # 3 3 # 3 # # 3 3 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # " << endl; +// cout << " # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ## 3 ## # # 3 3 # 3 # # 3 3 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # " << endl; + cout << tab(2) << "fetch-width " << fetch_width << endl; + cout << tab(2) << "max-chaining " << max_chaining << endl; + cout << tab(2) << "iteration-level " << iteration_level << endl; + cout << tab(2) << "counter-ub " << counter_ub << endl; + cout << tab(2) << "multi-sram-accessor " << multi_sram_accessor << endl; + cout << tab(2) << "dual-port-sram " << dual_port_sram << endl; + cout << tab(2) << "wire-chain-en " << wire_chain_en << endl; + cout << "=======================================" << endl; + cout << tab(2) << "word-width " << endl; + for(auto i: word_width) + cout << tab(4) << i.first << " " << i.second << endl; + cout << tab(2) << "capacity " << endl; + for(auto i: capacity) + cout << tab(4) << i.first << " " << i.second << endl; + cout << tab(2) << "in-port-width " << endl; + for(auto i: in_port_width) + cout << tab(4) << i.first << " " << i.second << endl; + cout << tab(2) << "out-port-width " << endl; + for(auto i: out_port_width) + cout << tab(4) << i.first << " " << i.second << endl; + cout << tab(2) << "controller-name " << endl; + for(auto i: controller_name) + cout << tab(4) << i << " " << endl; + } + + void print_points(string a){ + ofstream fout(a); + fout << "fetch-width " << fetch_width << endl; + fout << "max-chaining " << max_chaining << endl; + fout << "iteration-level " << iteration_level << endl; + fout << "counter-ub " << counter_ub << endl; + fout << "multi-sram-accessor " << multi_sram_accessor << endl; + fout << "dual-port-sram " << dual_port_sram << endl; + fout << "wire-chain-en " << wire_chain_en << endl; + fout << "word-width " << endl; + for(auto i: word_width) + fout << i.first << " " << i.second << endl; + fout << "capacity " << endl; + for(auto i: capacity) + fout << i.first << " " << i.second << endl; + fout << "in-port-width " << endl; + for(auto i: in_port_width) + fout << i.first << " " << i.second << endl; + fout << "out-port-width " << endl; + for(auto i: out_port_width) + fout << i.first << " " << i.second << endl; + fout << "controller-name " << endl; + for(auto i: controller_name) + fout << i << endl; + fout.close(); + } + + void set_config_fetch2() { fetch_width = 2; max_chaining = 4; @@ -168,6 +326,18 @@ struct LakeCollateral { capacity = {{"agg", 8}, {"sram", 512}, {"tb", 8}}; } + void set_config_dp() { + fetch_width = 1; + dual_port_sram = true; + wire_chain_en = false; + word_width = {{"mem", 1}}; + in_port_width = {{"mem", 1}}; + out_port_width = {{"mem", 1}}; + bank_num = {{"mem", 1}}; + capacity = {{"mem", 512}}; + controller_name = {"regfile"}; + } + int get_max_capacity() const { int c = 0; for (auto it: capacity) { @@ -200,6 +370,7 @@ struct LakeCollateral { return bank_num.at("tb"); } } + }; enum HLSLoopCodegen { @@ -274,6 +445,7 @@ struct CodegenOptions { void add_memory_hierarchy(const std::string& level); banking_strategy get_banking_strategy(const std::string& buffer); + string get_hierarchy_level(int capacity); }; @@ -296,3 +468,5 @@ struct mem_access_cnt { map > write_cnt; }; +LakeCollateral create_single_port_wide_fetch_memory(int fetch_width, int capacity, int SIPO_num); +LakeCollateral create_dual_port_memory(int capacity); diff --git a/pe_header.json b/pe_header.json new file mode 100644 index 000000000..c9eb436bb --- /dev/null +++ b/pe_header.json @@ -0,0 +1,22 @@ +{"namespaces":{ + "global":{ + "modules":{ + "PE":{ + "type":["Record",[ + ["inst",["Array",31,"BitIn"]], + ["inputs0",["Array",16,"BitIn"]], + ["inputs1",["Array",16,"BitIn"]], + ["inputs2",["Array",16,"BitIn"]], + ["inputs3",["Array",16,"BitIn"]], + ["inputs4",["Array",16,"BitIn"]], + ["clk_en","BitIn"], + ["O0",["Array",16,"Bit"]], + ["O1","Bit"], + ["CLK",["Named","coreir.clkIn"]], + ["ASYNCRESET",["Named","coreir.arstIn"]] + ]] + } + } + } +} +} diff --git a/pond_header.json b/pond_header.json new file mode 100644 index 000000000..289cc1b4f --- /dev/null +++ b/pond_header.json @@ -0,0 +1,18 @@ +{"namespaces":{ + "global":{ + "modules":{ + "Pond":{ + "type":["Record",[ + ["flush","BitIn"], + ["clk_en","BitIn"], + ["data_in_pond_0",["Array",16,"BitIn"]], + ["O0",["Array",16,"Bit"]], + ["O1","Bit"], + ["CLK",["Named","coreir.clkIn"]], + ["ASYNCRESET",["Named","coreir.arstIn"]] + ]] + } + } + } +} +} diff --git a/prog.cpp b/prog.cpp index c1b996110..9f9bbe588 100644 --- a/prog.cpp +++ b/prog.cpp @@ -613,13 +613,16 @@ void make_constant_dd(const std::string& target_op, const std::string& target_bu } } + std::vector topologically_sort( std::set not_yet_sorted, map > other_producers) { std::vector topologically_sorted_kernels; while(not_yet_sorted.size() > 0){ + bool add_new_kernel = false; for(auto next_kernel : not_yet_sorted){ bool all_producers_sorted = true; + cout << "sorted kernel: " << topologically_sorted_kernels << endl; for (auto producer : other_producers.at(next_kernel)) { if(!elem(producer, topologically_sorted_kernels)) { all_producers_sorted = false; @@ -629,9 +632,16 @@ std::vector topologically_sort( if(all_producers_sorted){ topologically_sorted_kernels.push_back(next_kernel); not_yet_sorted.erase(next_kernel); + add_new_kernel = true; break; } } + if (!add_new_kernel) { + cout << "\tIs topologically symmetric:\n\t" << not_yet_sorted << endl; + auto kernel_picked = pick(not_yet_sorted); + not_yet_sorted.erase(kernel_picked); + topologically_sorted_kernels.push_back(kernel_picked); + } } return topologically_sorted_kernels; } @@ -2066,6 +2076,39 @@ void infer_bounds_and_unroll(const std::string& out, const std::vector& bou merge_basic_block_ops(prg); } +void halide_check_rate_mismatch(const std::string& out, const std::vector& bounds, const int unroll_factor, prog& prg) { + + prg.reset_context(); + prg.pretty_print(); + cout << endl; + + cout << "Ritvik_reduce_loop_unroll : " << endl << endl << endl; + unroll_reduce_loops(prg); + cout << endl << endl; + prg.pretty_print(); + cout << endl; + + cout << "Ritvik_ormalize_bounds : " << endl << endl << endl; + normalize_bounds(prg); + cout << endl << endl; + prg.pretty_print(); + cout << endl; + + cout << "Ritvik_merge_basic_block : " << endl << endl << endl; + prg.pretty_print(); + cout << endl; + + cout << "Ritvik_Unroll_producer_matching : " << endl << endl; + rate_checking_pass(out, unroll_factor, prg); + cout << endl << endl; + prg.pretty_print(); + cout << endl; + +} + + + + void normalize_bounds(prog& prg) { auto loops = prg.all_loops(); for (auto l : loops) { @@ -2174,6 +2217,52 @@ map compute_unroll_factors(const std::string& buf, const int unroll return factors; } +void rate_checking_pass(const std::string& buf, const int unroll_factor, prog& prg) { + prg.pretty_print(); + umap* deps = pad_map(prg.validity_deps()); //Padd with dimension? + + cout << "Done padding validity deps" << endl; + auto umaps = get_maps(deps); // Get all maps + vector projected_deps; + for (auto m : umaps) { + cout << "Projection: Domain & range = {" << domain_name(m) << " " << range_name(m) << "} " << num_in_dims(m) << " " << num_out_dims(m) << endl; + isl_map* projected = project_all_but(m, num_in_dims(m) - 1); // Donno what + projected_deps.push_back(projected); + cout << "Projection: Domain & range = {" << domain_name(projected) << " " << range_name(projected) << "} " << num_in_dims(m) << " " << num_out_dims(m) << endl; + + } + + cout << "Computing qfactors... " << projected_deps.size() << " " << endl; + map qfs = compute_qfactors(projected_deps);//Main step + cout << "Got qfactors..." << endl; + int temp_standard = 1; + int flag = 0; + for (auto q : qfs) { + int temp = std::stoi(str(q.second)); + if(temp != temp_standard) + { + if(flag ==0) + flag = 1; + + + if(flag ==1) + { + cout << "WARNING: THE GIVEN APPLICATION IS NOT RATE MATCHED, APPLICATION WILL UNDERUTILIZE HARDWARE" << endl; + flag= -1; + } + cout << q.first << " is too much unrolled by a factor of " << (int) temp/temp_standard << endl; + } + } + if(flag == flag) // fpag = -1 + { + cout << "LOCAL ITERATION INTERVAL OF ALL LOOPS IS" << endl; + for (auto q : qfs) { + cout << tab(1) << q.first << " -> " << str(q.second) << endl; + } + } +} + + bool inner_loops_unrollable(const std::string& buf, const int unroll_factor, prog& prg) { std::set inner_loops = get_inner_loops(prg); @@ -2960,6 +3049,21 @@ int loop_depth(op* op) { } +vector loop_depth_vector(op* op) { + if( op->is_loop()){ + int depth = op->trip_count(); + + vector vec = loop_depth_vector(pick(op->children)); + vec.insert(vec.begin(), depth); + return vec; + } else if (op->is_if()) { + vector vec = loop_depth_vector(pick(op->children)); + return vec; + } else { + return {}; + } +} + bool all_loop_nests_same_depth(prog& prg) { auto ops = prg.all_ops(); @@ -3414,11 +3518,11 @@ bool is_op_scheduled(op* op, schedule_info& sched, prog& prg) { //return has_latency && has_ii && has_offset; return has_ii && has_offset; } - //return has_latency && has_offset; return has_offset; } + bool share_resource(const std::string& op0, const std::string& op1, schedule_info& sched) { resource_instance i0; for (auto r : sched.resource_assignment) { @@ -3458,6 +3562,60 @@ bool no_violated_resource_assignments(schedule_info& sched, prog& prg) { return true; } +bool share_buf_write_port(const std::string& op0, const std::string& op1, schedule_info& sched, prog& prg) { + string buf0, buf1; + for (auto r : sched.buf_write_assignment) { + if (r.first->name == op0) { + buf0 = r.second; + } + } + for (auto r : sched.buf_write_assignment) { + if (r.first->name == op1) { + buf1 = r.second; + } + } + if (buf0 == buf1) { + //Check if those two op can partition + umap* pmap0 = producer_umap(prg.find_op(op0), prg); + umap* pmap1 = producer_umap(prg.find_op(op1), prg); + cout << "buf " << buf0 << endl; + bool is_pond = + sched.buf2level.at(buf0) == "regfile"; + return is_pond && !empty(its(range(pmap0), range(pmap1))); + } else { + return false; + } +} + +bool no_violated_buf_write_port_assignments(CodegenOptions& options, schedule_info& sched, prog& prg) { + auto sched_exprs = + its(op_times_map(sched, prg), prg.whole_iteration_domain()); + //cout << "Times: " << str(sched_exprs) << endl; + for (auto op0 : get_maps(sched_exprs)) { + for (auto op1 : get_maps(sched_exprs)) { + string name0 = domain_name(op0); + string name1 = domain_name(op1); + cout << "name0: " << name0 << endl; + cout << "name1: " << name1 << endl; + + if (name0 != name1 && share_buf_write_port(name0, name1, sched, prg)) { + auto times = range(op0); + auto times1 = range(op1); + auto overlap = its(times, times1); + cout << "name0: " << name0 << endl; + cout << "name1: " << name1 << endl; + cout << "overlap: " << str(overlap) << endl; + if (!empty(overlap)) { + cout << tab(1) << name0 << " and " << name1 << " use the same resource" << endl; + cout << tab(2) << "Overlap: " << str(overlap) << endl; + return false; + } + } + } + } + return true; + +} void ir_node::replace_writes_to(const std::string& source_buf, const std::string& replacement) { @@ -4250,6 +4408,23 @@ op* find_coarse_grained_pipeline_loop(op* lp) { return find_coarse_grained_pipeline_loop(lp->children.back()); } +void find_split_inner_perfect_loop(op* lp_visit, vector & cgpl_lp, prog& prg) { + //this is the new cgpl loop finding function + //we traverse the AST in post order + //If a loop with more than one children + //Then this is a cgpli loop node. + // + //Post order visit guarantee that descendant is ahead of its ancestor + + for (auto child: lp_visit->children) { + find_split_inner_perfect_loop(child, cgpl_lp, prg); + } + if ((lp_visit->children).size() > 1 && is_inner_loop(lp_visit)) { + if (lp_visit != prg.root) + cgpl_lp.push_back(lp_visit); + } +} + void find_coarse_grained_pipeline_loops(op* lp_visit, vector & cgpl_lp, prog& prg) { //this is the new cgpl loop finding function //we traverse the AST in post order @@ -4388,6 +4563,52 @@ void loop_perfection(prog& prg) { } } +void loop_perfection_without_glb_op(op* target_lp, op* inner_most_cgpl_lp, prog& prg) { + //pc id is the location of loop child that will subsume all the other children + int pc_id = -1; + int child_count = 0; + for (auto child: target_lp->children) { + if (!is_perfect(child, prg)) { + //Can only has one child exist + assert(pc_id == -1); + pc_id = child_count; + } + child_count ++; + } + assert(pc_id != -1); + for (int i = pc_id-1; i >= 0; i --) { + op* move_op = target_lp->children.at(i); + auto name = move_op->name; + if (contains(name, "glb")) + continue; + cout << "\tADD Prelogue op: " << name << endl; + add_prelogue_op(move_op, target_lp->children.at(pc_id), inner_most_cgpl_lp); + //Move one loop inside need to decrease the index + pc_id --; + } + cout << "pc id: " << pc_id << endl; + cout << "kernel need to be consider: " << target_lp->children << endl; + for (int i = pc_id+1; i < target_lp->children.size(); i ++) { + op* move_op = target_lp->children.at(i); + auto name = move_op->name; + cout << "\tepilogue op: " << name << endl; + add_epilogue_op(move_op, target_lp->children.at(pc_id), inner_most_cgpl_lp); + } +} + +void loop_perfection_with_root_op(prog& prg) { + vector cgpl_lps; + find_coarse_grained_pipeline_loops(prg.root, cgpl_lps, prg); + if (cgpl_lps.size() == 0) + return; + cgpl_lps.push_back(prg.root); + op* inner_most_cgpl_lp = cgpl_lps.front(); + for(auto it = cgpl_lps.begin() + 1; it != cgpl_lps.end(); it ++) { + //Move the ir node under *it into the inner most coarse grained pipeline loop + loop_perfection_without_glb_op(*it, inner_most_cgpl_lp, prg); + } +} + bool single_coarse_pipeline_loop_nests(prog& prg) { vector cgpl_lps; find_coarse_grained_pipeline_loops(prg.root, cgpl_lps, prg); @@ -4456,6 +4677,18 @@ int logical_dimension(const std::string& buf, prog& prg) { } } +int logical_capacity(const std::string& buf, prog& prg) { + + uset* addr_range; + if (!prg.is_input(buf)) { + addr_range = range(prg.producer_map(buf)); + } else { + addr_range = range(prg.consumer_map(buf)); + } + auto range_card = card(addr_range); + return int_upper_bound(range_card); +} + vector fully_scheduled_nodes(schedule_info& sched, prog& prg) { vector ops; for (auto op : prg.all_nodes()) { @@ -4606,6 +4839,52 @@ int op_latency(op* op, schedule_info& hwinfo) { return total_latency; } + +//Binary search the smallest outer delay +void adjust_outer_delays_exhaustively(schedule_info& sched, prog& prg, int glb_load_latency) { + auto deps = cycle_accurate_deps(prg); + cout << "Adjusting delays of " << prg.name << endl; + //for (auto lp : prg.root->children) { + // string name = lp->name; + for (auto name : topologically_sort_kernels(prg)) { + auto lp = prg.find_loop(name); + cout << "Adjusting delay of " << lp->name << endl; + + int earliest_possible_delay = 0; + int latest_legal_delay = + map_find(lp, sched.op_offset_within_parent); + + int current_delay = latest_legal_delay; + + assert(latest_legal_delay >= earliest_possible_delay); + while (latest_legal_delay - earliest_possible_delay > 0) { + assert(latest_legal_delay >= earliest_possible_delay); + int try_delay = (latest_legal_delay + earliest_possible_delay) / 2; + sched.op_offset_within_parent[lp] = try_delay; + if (no_violated_cycle_accurate_dependencies(deps, sched, prg)) { + latest_legal_delay = try_delay; + } else { + earliest_possible_delay = try_delay + 1; + } + cout << "Earliest legal: " << earliest_possible_delay << endl; + cout << "Latest legal : " << latest_legal_delay << endl; + } + + if (!contains(name, "glb_s0")) + latest_legal_delay = std::max(latest_legal_delay, glb_load_latency); + if (contains(name, "hw_output")){ + //FIXME: override GLB output latency with sequential schedule + latest_legal_delay = 0; + for (string prod: get_producers(name, prg)) { + op* prod_op = prg.find_loop(prod); + latest_legal_delay = std::max(latest_legal_delay, + sched.total_latency(prod_op) + sched.op_offset_within_parent.at(prod_op)); + } + } + sched.op_offset_within_parent[lp] = latest_legal_delay; + } +} + void adjust_outer_delays(schedule_info& sched, prog& prg) { auto deps = cycle_accurate_deps(prg); cout << "Adjusting delays of " << prg.name << endl; @@ -4734,6 +5013,76 @@ void move_node(op* node_to_be_moved, op* dst, prog& prg) { node_to_be_moved->parent = dst; } + +void loop_split(prog& prg) { + vector cgpl_lp; + find_split_inner_perfect_loop(prg.root, cgpl_lp, prg); + for (auto lp: cgpl_lp) { + cout << tab(4) << lp->name << endl; + perfect_loop_split(lp, prg); + } +} + +void remove_loop(op* lp) { + auto p = lp->parent; + vector new_children; + for (auto c: p->children) { + if( c != lp) { + new_children.push_back(c); + } + } + p->children = new_children; +} + +bool share_index_var(vector & children) { + std::set shared_vars; + for(auto child: children) { + for (auto idx: child->index_variables_needed_by_compute) { + if (shared_vars.count(idx)) { + return true; + } else { + shared_vars.insert(idx); + } + } + } + return false; +} + +//Before we calling this function, we have check lp is a perfect loop nest +void perfect_loop_split(op* lp, prog& prg) { + //lp is the loop level that has multiple children, + //we will duplicate the loop level from lp to root and add each child into the splitted loop nest + int child_cnt = 0; + op* outtest_lp = prg.root->container_child(lp); + auto child_list = lp->children; + + //Cannot split loop if they share index variable + if (share_index_var(child_list)) + return; + for (op* child: child_list) { + //Get surrounding loops from root to leave + cout << "\tVisiting child: " << child->name << endl; + vector surrounding_loops = surrounding_vars(child, prg); + vector loop_nest = surrounding_vars_ops(child, prg); + loop_nest.erase(loop_nest.begin()); + + auto new_lp = prg.root->add_loop_before(outtest_lp, + outtest_lp->name + "_split_"+str(child_cnt), + outtest_lp->start, outtest_lp->end_exclusive); + for (auto it = loop_nest.begin()+1; it != loop_nest.end(); it ++) { + new_lp = new_lp->add_loop((*it)->name + "_split_" + str(child_cnt), + (*it)->start, (*it)->end_exclusive); + } + move_node(child, new_lp, prg); + child->add_var_suffix_to_writes("_split_" + str(child_cnt), surrounding_loops); + child->add_var_suffix_to_reads("_split_" + str(child_cnt), surrounding_loops); + child_cnt ++; + } + cout << "container child: " << prg.root->container_child(lp)->name << endl; + remove_loop(outtest_lp); +} + + void pad_bottom_level_ops_with_loops(prog& prg) { int max_depth = max_loop_depth(prg); for (auto c : prg.all_ops()) { @@ -4758,6 +5107,154 @@ int max_loop_depth(prog& prg) { return maxl; } +std::set reduce_op(prog & prg) { + std::set reduce_op; + vector rvars = reduce_vars(prg); + for (string var: rvars) { + op* loop = prg.find_loop(var); + auto lower_ops = loop->descendant_ops(); + for (auto lower_op: lower_ops) + reduce_op.insert(lower_op); + } + return reduce_op; +} + +//This should apply to the kernel that fully unrolled +// +void dsa_writers_new(prog& prg) { + std::set r_ops = reduce_op(prg); + + std::set all_buffers; + std::set multi_write_buffers; + map > producer_kernels; + std::set reduced_kernels; + for (auto op : prg.all_ops()) { + //should not rewrite the real reduce kernel + if (r_ops.count(op)) + continue; + auto read = op->buffers_read(); + auto written = op->buffers_written(); + for (auto b : intersection(read, written)) { + reduced_kernels.insert(b); + cout << "reduced kernel : " << b << endl; + } + } + + for (auto k : get_kernels(prg)) { + for (auto b : get_produced_buffers(k, prg)) { + all_buffers.insert(b); + producer_kernels[b].insert(k); + cout << "insert kernel: " << k << " to producer buffer: " << b << endl; + } + } + + cout << "Producer kernels..." << endl; + for (auto p : producer_kernels) { + cout << tab(1) << p.first << " -> "; + for (auto k : p.second) { + cout << k << " "; + } + cout << endl; + if (p.second.size() > 1) { + cout << tab(2) << "MULTIPLE PRODUCERS" << endl; + } + } + for (auto k : get_kernels(prg)) { + for (auto b : get_produced_buffers(k, prg)) { + auto producers = producer_kernels[b]; + + if (elem(b, reduced_kernels) && producers.size() >= 1) { + cout << b << " has " << producers.size() << " producers" << endl; + for (auto p : producers) { + cout << tab(1) << p << endl; + } + auto writers = find_writers(b, prg); + prg.pretty_print(); + //assert(writers.size() <= 2); + if (writers.size() > 1) { + multi_write_buffers.insert(b); + } + } + + } + } + + cout << "Multi-write buffers" << endl; + map >initializers; + map > updaters; + for (auto b : multi_write_buffers) { + cout << tab(1) << b << endl; + auto writers = find_writers(b, prg); + vector ws; + for (auto w : writers) { + ws.push_back(w); + } + + for (auto w : ws) { + if (w->read_addrs().size() == 0) { + initializers[b].insert(w); + } else { + updaters[b].insert(w); + } + + } + //op* w0 = ws.at(0); + //op* w1 = ws.at(1); + + //if (w0->read_addrs().size() == 0) { + //initializers[b] = w0; + //updaters[b] = w1; + //} else { + //initializers[b] = w1; + //updaters[b] = w0; + //} + } + + cout << "Built initializer / update maps" << endl; + cout << tab(1) << "# multi_write buffers = " << multi_write_buffers.size() << endl; + //assert(false); + for (auto b : multi_write_buffers) { + string init_buffer = prg.un(b + "_clkwrk_dsa"); + for (auto init : initializers[b]) { + init->replace_writes_to(b, init_buffer); + } + for (auto updated : updaters[b]) { + updated->replace_reads_from(b, init_buffer); + } + //auto init = initializers[b]; + //assert(init != 0); + //auto updated = updaters[b]; + //assert(updated != 0); + //cout << "Replacing writes" << endl; + //init->replace_writes_to(b, init_buffer); + //cout << "Replacing reads from " << b << " in " << updated->name << endl; + //updated->replace_reads_from(b, init_buffer); + prg.buffer_port_widths[init_buffer] = prg.buffer_port_width(b); + } + + prg.pretty_print(); + //assert(false); + + // Split up buffers that are read at constants in one of their components + for (auto b : all_buffers) { + auto writers = find_writers(b, prg); + auto readers = find_readers(b, prg); + + if (writers.size() > 1 && readers.size() == 0) { + cout << b << " has " << writers.size() << " writers and " << readers.size() << " readers" << endl; + assert(prg.is_output(b)); + for (auto writer : writers) { + string init_buffer = prg.un(b + "_clkwrk_write_duplicate"); + writer->replace_writes_to(b, init_buffer); + prg.add_output(init_buffer); + prg.buffer_port_widths[init_buffer] = prg.buffer_port_width(b); + } + + prg.outs.erase(b); + } + } +} + void dsa_writers(prog& prg) { if (is_rate_matchable(prg)) { prg.pretty_print(); diff --git a/prog.h b/prog.h index cb52d06ca..3cd259ab3 100644 --- a/prog.h +++ b/prog.h @@ -168,6 +168,58 @@ struct ir_node { return end_exclusive - start; } + void add_var_suffix_to_writes(const std::string& suffix, vector & loop_var) { + for (auto& b : produce_locs) { + //buffer, piecese loc + for (auto& p : b.second) { + //condition, address expr + cout << "orgin expr: " << p.second << endl; + auto expr_list = split_at(p.second, ","); + vector new_expr_list; + for (auto expr: expr_list) { + cout << "\t"<< expr << endl; + string new_expr = expr; + for (auto var: loop_var) { + if (contains(expr, var)) { + new_expr = ReplaceString(expr, var, var + suffix); + cout << "\tnew expr: " << new_expr << endl; + } + } + new_expr_list.push_back(new_expr); + } + p.second = sep_list(new_expr_list, "", "", ","); + cout << "new expr list: " << p.second << endl; + } + + } + } + + void add_var_suffix_to_reads(const std::string& suffix, vector & loop_var) { + for (auto& b : consume_locs_pair) { + //buffer, piecese loc + for (auto& p : b.second) { + //condition, address expr + cout << "orgin expr: " << p.second << endl; + auto expr_list = split_at(p.second, ","); + vector new_expr_list; + for (auto expr: expr_list) { + cout << "\t"<< expr << endl; + string new_expr = expr; + for (auto var: loop_var) { + if (contains(expr, var)) { + new_expr = ReplaceString(expr, var, var + suffix); + cout << "\tnew expr: " << new_expr << endl; + } + } + new_expr_list.push_back(new_expr); + } + p.second = sep_list(new_expr_list, "", "", ","); + cout << "new expr list: " << p.second << endl; + } + + } + } + void add_prefix_to_writes(const std::string& prefix, const std::string& buf) { for (auto& b : produce_locs) { @@ -323,6 +375,12 @@ struct ir_node { index_variables_prefetch_cycle = v; } + void add_index_var_suffix(const std::string & suffix) { + for (auto & compute_var : index_variables_needed_by_compute) { + compute_var += suffix; + } + } + map get_domain_boxes() { Box empty; map domain_map; @@ -481,6 +539,7 @@ struct ir_node { op* sr = container_child(source); assert(sr != nullptr); + cout << sr->name << endl; cout << "Before inserting " << name << " we have " << children.size() << " children" << endl; auto lp = new op(); @@ -1294,13 +1353,13 @@ struct prog { root->populate_iter_vars(ivars, act); //Check what's all the domain - for (auto it: idoms) { - cout << "OP name: " << it.first->name << endl; - cout << "dom bd: " << it.second << endl << endl; - } + //for (auto it: idoms) { + // cout << "OP name: " << it.first->name << endl; + // cout << "dom bd: " << it.second << endl << endl; + //} for (auto op : vecs) { - cout << op.first->name << endl; + //cout << op.first->name << endl; auto iters = map_find(op.first, ivars); auto vars = sep_list(iters, "[", "]", ", "); @@ -1625,7 +1684,8 @@ void extend_bounds_to_multiple_of(const int factor, const std::string& buf, prog void infer_bounds_and_unroll(const std::string& out, const std::vector& bounds, const int unroll_factor, prog& prg); - +void halide_check_rate_mismatch(const std::string& out, const std::vector& bounds, const int unroll_factor, prog& prg); +void rate_checking_pass(const std::string& buf, const int unroll_factor, prog& prg); void unroll_producer_matching(const std::string& buf, const int unroll_factor, prog& prg); op* strip_mine(const int factor, op* loop, prog& prg); @@ -1698,6 +1758,8 @@ umap* consumer_umap(op* loop, prog& prg); isl_map* consumer_map(op* loop, const std::string& b, prog& prg); isl_map* producer_map(op* loop, const std::string& b, prog& prg); +int logical_capacity(const std::string& buf, prog& prg); + umap* read_at(const std::string& level, const std::string& buffer, prog& prg); umap* read_at(const std::string& level, prog& prg); @@ -1742,8 +1804,11 @@ bool operator==(const resource_instance& a, const resource_instance& b) { struct schedule_info { // Miscellaneous - bool use_dse_compute; - + bool use_metamapper; + //Memory constraints + map buf_write_assignment; + map buf2level; + string dse_compute_filename; // Schedule constraints map buffer_load_latencies; map buffer_store_latencies; @@ -1793,6 +1858,19 @@ struct schedule_info { return last_delay; } + int starting_delay_to_leaf(op* op) { + if (!op->is_loop()) { + return offset_in_parent(op); + } else { + int min_delay = INT_MAX; + for (auto c: op->children) { + min_delay = std::min(min_delay, starting_delay_to_leaf(c)); + } + return offset_in_parent(op) + min_delay; + + } + } + //Above the Coarse grained loop, the II will follow the db update delay //We do not need to wait for the latency, since we have N buffer int doublebuffer_update_delay(op* op) { @@ -1826,6 +1904,11 @@ struct schedule_info { return map_find(op->name, loop_iis); } + void assign_memory_write_resource(CodegenOptions& options, op* op_, string buf) { + buf_write_assignment[op_] = buf; + } + + }; std::set all_buffers(prog& prg); @@ -1837,6 +1920,7 @@ int num_read_ports(const std::string& b, prog& prg); bool is_rate_matchable(prog& prg); int loop_depth(op* op); +vector loop_depth_vector(op* op); bool all_loop_nests_same_depth(prog& prg); bool is_perfect(op* loop, prog& prg); @@ -1887,6 +1971,7 @@ op* find_coarse_grained_pipeline_loop(op* lp, prog& prg); void find_coarse_grained_pipeline_loops(op* lp, vector & cgpl_lps, prog& prg); void loop_perfection(prog& prg); +void loop_perfection_with_root_op(prog& prg); void sanity_check_iis(schedule_info& sched); int logical_dimension(const std::string& buf, prog& prg); @@ -1905,23 +1990,29 @@ bool all_ops_scheduled(schedule_info& sched, prog& prg); int op_latency(op* op, schedule_info& hwinfo); void adjust_outer_delays(schedule_info& sched, prog& prg); +void adjust_outer_delays_exhaustively(schedule_info& sched, prog& prg, int glb_load_latency); void adjust_outer_pipeline_delays(schedule_info& sched, prog& prg); bool no_violated_cycle_accurate_dependencies(schedule_info& sched, prog& prg); bool sw_schedule_respects_deps(umap* schedule, umap* deps); bool no_violated_dependencies(umap* schedule, umap* deps); +bool no_violated_buf_write_port_assignments(CodegenOptions& options, schedule_info& sched, prog& prg); bool schedule_bounds_fit_controller_bitwidth(const int bitwidth, schedule_info& sched, prog& prg); void adjust_inner_iis(schedule_info& sched, prog& prg); +void loop_split(prog& prg); +void perfect_loop_split(op*, prog& ); + void pad_top_level_ops_with_loops(prog& prg); void pad_bottom_level_ops_with_loops(prog& prg); int max_loop_depth(prog& prg); void dsa_writers(prog& prg); +void dsa_writers_new(prog& prg); void dsa_readers(prog& prg); diff --git a/resnet5_glb_unroll_compute.h b/resnet5_glb_unroll_compute.h new file mode 100644 index 000000000..eb7e3b836 --- /dev/null +++ b/resnet5_glb_unroll_compute.h @@ -0,0 +1,451 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: input_glb.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) = input_host.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_1 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_1; +} + +//store is: input_glb.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil_1(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_2 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_2; +} + +//store is: kernel_glb.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) +hw_uint<16> hcompute_kernel_glb_stencil(hw_uint<16>& kernel_host_stencil) { + int16_t _kernel_host_stencil_1 = (int16_t) kernel_host_stencil.extract<0, 15>(); + + return _kernel_host_stencil_1; +} + +//store is: kernel_glb.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) +hw_uint<16> hcompute_kernel_glb_stencil_1(hw_uint<16>& kernel_host_stencil) { + int16_t _kernel_host_stencil_2 = (int16_t) kernel_host_stencil.extract<0, 15>(); + + return _kernel_host_stencil_2; +} + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil() { + int16_t _695 = (int16_t)(0); + return _695; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_1() { + int16_t _699 = (int16_t)(0); + return _699; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_2() { + int16_t _704 = (int16_t)(0); + return _704; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_3() { + int16_t _709 = (int16_t)(0); + return _709; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_4() { + int16_t _714 = (int16_t)(0); + return _714; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_5() { + int16_t _719 = (int16_t)(0); + return _719; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_6() { + int16_t _724 = (int16_t)(0); + return _724; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_7() { + int16_t _729 = (int16_t)(0); + return _729; +} + +//store is: input_cgra.stencil((input_cgra_s0_z_z_cgra_z_cgra*2), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_1 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_1; +} + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*2) + 1), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2) + 1), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil_1(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_2 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_2; +} + +//store is: kernel_cgra.stencil((kernel_cgra_s0_z_z_cgra_z_cgra*2), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) +hw_uint<16> hcompute_kernel_cgra_stencil(hw_uint<16>& kernel_glb_stencil) { + int16_t _kernel_glb_stencil_1 = (int16_t) kernel_glb_stencil.extract<0, 15>(); + + return _kernel_glb_stencil_1; +} + +//store is: kernel_cgra.stencil(((kernel_cgra_s0_z_z_cgra_z_cgra*2) + 1), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2) + 1), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) +hw_uint<16> hcompute_kernel_cgra_stencil_1(hw_uint<16>& kernel_glb_stencil) { + int16_t _kernel_glb_stencil_2 = (int16_t) kernel_glb_stencil.extract<0, 15>(); + + return _kernel_glb_stencil_2; +} + +//store is: output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_8(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_1 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_2 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_3 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_4 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_5 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_6 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_7 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_8 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_1 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_2 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_3 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_4 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_5 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_6 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_7 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_8 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_1 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _760 = _kernel_cgra_stencil_1 * _input_cgra_stencil_1; + int16_t _761 = _kernel_cgra_stencil_2 * _input_cgra_stencil_2; + int16_t _762 = _kernel_cgra_stencil_3 * _input_cgra_stencil_3; + int16_t _763 = _kernel_cgra_stencil_4 * _input_cgra_stencil_4; + int16_t _764 = _kernel_cgra_stencil_5 * _input_cgra_stencil_5; + int16_t _765 = _kernel_cgra_stencil_6 * _input_cgra_stencil_6; + int16_t _766 = _kernel_cgra_stencil_7 * _input_cgra_stencil_7; + int16_t _767 = _kernel_cgra_stencil_8 * _input_cgra_stencil_8; + int16_t _768 = _766 + _767; + int16_t _769 = _765 + _768; + int16_t _770 = _764 + _769; + int16_t _771 = _763 + _770; + int16_t _772 = _762 + _771; + int16_t _773 = _761 + _772; + int16_t _774 = _output_cgra_stencil_1 + _773; + int16_t _775 = _760 + _774; + return _775; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_9(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_10 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_11 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_12 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_13 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_14 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_15 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_16 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_9 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_10 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_11 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_12 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_13 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_14 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_15 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_16 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_9 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_2 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _830 = _kernel_cgra_stencil_9 * _input_cgra_stencil_9; + int16_t _831 = _kernel_cgra_stencil_10 * _input_cgra_stencil_10; + int16_t _832 = _kernel_cgra_stencil_11 * _input_cgra_stencil_11; + int16_t _833 = _kernel_cgra_stencil_12 * _input_cgra_stencil_12; + int16_t _834 = _kernel_cgra_stencil_13 * _input_cgra_stencil_13; + int16_t _835 = _kernel_cgra_stencil_14 * _input_cgra_stencil_14; + int16_t _836 = _kernel_cgra_stencil_15 * _input_cgra_stencil_15; + int16_t _837 = _kernel_cgra_stencil_16 * _input_cgra_stencil_16; + int16_t _838 = _836 + _837; + int16_t _839 = _835 + _838; + int16_t _840 = _834 + _839; + int16_t _841 = _833 + _840; + int16_t _842 = _832 + _841; + int16_t _843 = _831 + _842; + int16_t _844 = _output_cgra_stencil_2 + _843; + int16_t _845 = _830 + _844; + return _845; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_10(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_17 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_18 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_19 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_20 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_21 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_22 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_23 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_24 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_17 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_18 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_19 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_20 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_21 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_22 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_23 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_24 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_3 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _901 = _kernel_cgra_stencil_17 * _input_cgra_stencil_17; + int16_t _902 = _kernel_cgra_stencil_18 * _input_cgra_stencil_18; + int16_t _903 = _kernel_cgra_stencil_19 * _input_cgra_stencil_19; + int16_t _904 = _kernel_cgra_stencil_20 * _input_cgra_stencil_20; + int16_t _905 = _kernel_cgra_stencil_21 * _input_cgra_stencil_21; + int16_t _906 = _kernel_cgra_stencil_22 * _input_cgra_stencil_22; + int16_t _907 = _kernel_cgra_stencil_23 * _input_cgra_stencil_23; + int16_t _908 = _kernel_cgra_stencil_24 * _input_cgra_stencil_24; + int16_t _909 = _907 + _908; + int16_t _910 = _906 + _909; + int16_t _911 = _905 + _910; + int16_t _912 = _904 + _911; + int16_t _913 = _903 + _912; + int16_t _914 = _902 + _913; + int16_t _915 = _output_cgra_stencil_3 + _914; + int16_t _916 = _901 + _915; + return _916; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_11(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_25 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_26 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_27 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_28 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_29 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_30 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_31 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_32 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_25 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_26 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_27 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_28 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_29 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_30 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_31 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_32 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_4 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _972 = _kernel_cgra_stencil_25 * _input_cgra_stencil_25; + int16_t _973 = _kernel_cgra_stencil_26 * _input_cgra_stencil_26; + int16_t _974 = _kernel_cgra_stencil_27 * _input_cgra_stencil_27; + int16_t _975 = _kernel_cgra_stencil_28 * _input_cgra_stencil_28; + int16_t _976 = _kernel_cgra_stencil_29 * _input_cgra_stencil_29; + int16_t _977 = _kernel_cgra_stencil_30 * _input_cgra_stencil_30; + int16_t _978 = _kernel_cgra_stencil_31 * _input_cgra_stencil_31; + int16_t _979 = _kernel_cgra_stencil_32 * _input_cgra_stencil_32; + int16_t _980 = _978 + _979; + int16_t _981 = _977 + _980; + int16_t _982 = _976 + _981; + int16_t _983 = _975 + _982; + int16_t _984 = _974 + _983; + int16_t _985 = _973 + _984; + int16_t _986 = _output_cgra_stencil_4 + _985; + int16_t _987 = _972 + _986; + return _987; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_12(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_33 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_34 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_35 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_36 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_37 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_38 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_39 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_40 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_33 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_34 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_35 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_36 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_37 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_38 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_39 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_40 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_5 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1043 = _kernel_cgra_stencil_33 * _input_cgra_stencil_33; + int16_t _1044 = _kernel_cgra_stencil_34 * _input_cgra_stencil_34; + int16_t _1045 = _kernel_cgra_stencil_35 * _input_cgra_stencil_35; + int16_t _1046 = _kernel_cgra_stencil_36 * _input_cgra_stencil_36; + int16_t _1047 = _kernel_cgra_stencil_37 * _input_cgra_stencil_37; + int16_t _1048 = _kernel_cgra_stencil_38 * _input_cgra_stencil_38; + int16_t _1049 = _kernel_cgra_stencil_39 * _input_cgra_stencil_39; + int16_t _1050 = _kernel_cgra_stencil_40 * _input_cgra_stencil_40; + int16_t _1051 = _1049 + _1050; + int16_t _1052 = _1048 + _1051; + int16_t _1053 = _1047 + _1052; + int16_t _1054 = _1046 + _1053; + int16_t _1055 = _1045 + _1054; + int16_t _1056 = _1044 + _1055; + int16_t _1057 = _output_cgra_stencil_5 + _1056; + int16_t _1058 = _1043 + _1057; + return _1058; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_13(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_41 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_42 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_43 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_44 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_45 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_46 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_47 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_48 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_41 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_42 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_43 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_44 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_45 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_46 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_47 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_48 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_6 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1114 = _kernel_cgra_stencil_41 * _input_cgra_stencil_41; + int16_t _1115 = _kernel_cgra_stencil_42 * _input_cgra_stencil_42; + int16_t _1116 = _kernel_cgra_stencil_43 * _input_cgra_stencil_43; + int16_t _1117 = _kernel_cgra_stencil_44 * _input_cgra_stencil_44; + int16_t _1118 = _kernel_cgra_stencil_45 * _input_cgra_stencil_45; + int16_t _1119 = _kernel_cgra_stencil_46 * _input_cgra_stencil_46; + int16_t _1120 = _kernel_cgra_stencil_47 * _input_cgra_stencil_47; + int16_t _1121 = _kernel_cgra_stencil_48 * _input_cgra_stencil_48; + int16_t _1122 = _1120 + _1121; + int16_t _1123 = _1119 + _1122; + int16_t _1124 = _1118 + _1123; + int16_t _1125 = _1117 + _1124; + int16_t _1126 = _1116 + _1125; + int16_t _1127 = _1115 + _1126; + int16_t _1128 = _output_cgra_stencil_6 + _1127; + int16_t _1129 = _1114 + _1128; + return _1129; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_14(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_49 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_50 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_51 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_52 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_53 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_54 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_55 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_56 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_49 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_50 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_51 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_52 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_53 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_54 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_55 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_56 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_7 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1185 = _kernel_cgra_stencil_49 * _input_cgra_stencil_49; + int16_t _1186 = _kernel_cgra_stencil_50 * _input_cgra_stencil_50; + int16_t _1187 = _kernel_cgra_stencil_51 * _input_cgra_stencil_51; + int16_t _1188 = _kernel_cgra_stencil_52 * _input_cgra_stencil_52; + int16_t _1189 = _kernel_cgra_stencil_53 * _input_cgra_stencil_53; + int16_t _1190 = _kernel_cgra_stencil_54 * _input_cgra_stencil_54; + int16_t _1191 = _kernel_cgra_stencil_55 * _input_cgra_stencil_55; + int16_t _1192 = _kernel_cgra_stencil_56 * _input_cgra_stencil_56; + int16_t _1193 = _1191 + _1192; + int16_t _1194 = _1190 + _1193; + int16_t _1195 = _1189 + _1194; + int16_t _1196 = _1188 + _1195; + int16_t _1197 = _1187 + _1196; + int16_t _1198 = _1186 + _1197; + int16_t _1199 = _output_cgra_stencil_7 + _1198; + int16_t _1200 = _1185 + _1199; + return _1200; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, ((output_cgra_s1_x*2) + output_cgra_s1_r_x), ((output_cgra_s1_y*2) + output_cgra_s1_r_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_15(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_57 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_58 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_59 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_60 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_61 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_62 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_63 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_64 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_57 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_58 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_59 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_60 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_61 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_62 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_63 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_64 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_8 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1256 = _kernel_cgra_stencil_57 * _input_cgra_stencil_57; + int16_t _1257 = _kernel_cgra_stencil_58 * _input_cgra_stencil_58; + int16_t _1258 = _kernel_cgra_stencil_59 * _input_cgra_stencil_59; + int16_t _1259 = _kernel_cgra_stencil_60 * _input_cgra_stencil_60; + int16_t _1260 = _kernel_cgra_stencil_61 * _input_cgra_stencil_61; + int16_t _1261 = _kernel_cgra_stencil_62 * _input_cgra_stencil_62; + int16_t _1262 = _kernel_cgra_stencil_63 * _input_cgra_stencil_63; + int16_t _1263 = _kernel_cgra_stencil_64 * _input_cgra_stencil_64; + int16_t _1264 = _1262 + _1263; + int16_t _1265 = _1261 + _1264; + int16_t _1266 = _1260 + _1265; + int16_t _1267 = _1259 + _1266; + int16_t _1268 = _1258 + _1267; + int16_t _1269 = _1257 + _1268; + int16_t _1270 = _output_cgra_stencil_8 + _1269; + int16_t _1271 = _1256 + _1270; + return _1271; +} + +//store is: output_glb.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) +hw_uint<16> hcompute_output_glb_stencil(hw_uint<16>& output_cgra_stencil) { + int16_t _output_cgra_stencil_9 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + return _output_cgra_stencil_9; +} + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& output_glb_stencil) { + int16_t _output_glb_stencil_1 = (int16_t) output_glb_stencil.extract<0, 15>(); + + return _output_glb_stencil_1; +} + diff --git a/resnet5_x_unroll_compute.h b/resnet5_x_unroll_compute.h new file mode 100644 index 000000000..036a4be1a --- /dev/null +++ b/resnet5_x_unroll_compute.h @@ -0,0 +1,451 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: input_glb.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) = input_host.stencil((input_glb_s0_z_z*2), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_1 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_1; +} + +//store is: input_glb.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*2) + 1), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil_1(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_2 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_2; +} + +//store is: kernel_glb.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil((kernel_glb_s0_z_z*2), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) +hw_uint<16> hcompute_kernel_glb_stencil(hw_uint<16>& kernel_host_stencil) { + int16_t _kernel_host_stencil_1 = (int16_t) kernel_host_stencil.extract<0, 15>(); + + return _kernel_host_stencil_1; +} + +//store is: kernel_glb.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(((kernel_glb_s0_z_z*2) + 1), kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) +hw_uint<16> hcompute_kernel_glb_stencil_1(hw_uint<16>& kernel_host_stencil) { + int16_t _kernel_host_stencil_2 = (int16_t) kernel_host_stencil.extract<0, 15>(); + + return _kernel_host_stencil_2; +} + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil() { + int16_t _697 = (int16_t)(0); + return _697; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_1() { + int16_t _701 = (int16_t)(0); + return _701; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_2() { + int16_t _706 = (int16_t)(0); + return _706; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_3() { + int16_t _711 = (int16_t)(0); + return _711; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_4() { + int16_t _716 = (int16_t)(0); + return _716; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_5() { + int16_t _721 = (int16_t)(0); + return _721; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_6() { + int16_t _726 = (int16_t)(0); + return _726; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_7() { + int16_t _731 = (int16_t)(0); + return _731; +} + +//store is: input_cgra.stencil((input_cgra_s0_z_z_cgra_z_cgra*2), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_1 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_1; +} + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*2) + 1), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + input_cgra_s0_z_z_cgra_z_cgra)*2) + 1), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil_1(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_2 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_2; +} + +//store is: kernel_cgra.stencil((kernel_cgra_s0_z_z_cgra_z_cgra*2), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2), ((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) +hw_uint<16> hcompute_kernel_cgra_stencil(hw_uint<16>& kernel_glb_stencil) { + int16_t _kernel_glb_stencil_1 = (int16_t) kernel_glb_stencil.extract<0, 15>(); + + return _kernel_glb_stencil_1; +} + +//store is: kernel_cgra.stencil(((kernel_cgra_s0_z_z_cgra_z_cgra*2) + 1), kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((((output_cgra_s1_r_z_rz_glb*4) + kernel_cgra_s0_z_z_cgra_z_cgra)*2) + 1), ((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) +hw_uint<16> hcompute_kernel_cgra_stencil_1(hw_uint<16>& kernel_glb_stencil) { + int16_t _kernel_glb_stencil_2 = (int16_t) kernel_glb_stencil.extract<0, 15>(); + + return _kernel_glb_stencil_2; +} + +//store is: output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_8(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_1 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_2 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_3 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_4 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_5 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_6 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_7 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_8 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_1 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_2 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_3 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_4 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_5 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_6 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_7 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_8 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_1 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _769 = _kernel_cgra_stencil_1 * _input_cgra_stencil_1; + int16_t _770 = _kernel_cgra_stencil_2 * _input_cgra_stencil_2; + int16_t _771 = _kernel_cgra_stencil_3 * _input_cgra_stencil_3; + int16_t _772 = _kernel_cgra_stencil_4 * _input_cgra_stencil_4; + int16_t _773 = _kernel_cgra_stencil_5 * _input_cgra_stencil_5; + int16_t _774 = _kernel_cgra_stencil_6 * _input_cgra_stencil_6; + int16_t _775 = _kernel_cgra_stencil_7 * _input_cgra_stencil_7; + int16_t _776 = _kernel_cgra_stencil_8 * _input_cgra_stencil_8; + int16_t _777 = _775 + _776; + int16_t _778 = _774 + _777; + int16_t _779 = _773 + _778; + int16_t _780 = _772 + _779; + int16_t _781 = _771 + _780; + int16_t _782 = _770 + _781; + int16_t _783 = _output_cgra_stencil_1 + _782; + int16_t _784 = _769 + _783; + return _784; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_9(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_10 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_11 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_12 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_13 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_14 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_15 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_16 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_9 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_10 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_11 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_12 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_13 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_14 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_15 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_16 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_9 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_2 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _837 = _kernel_cgra_stencil_9 * _input_cgra_stencil_9; + int16_t _838 = _kernel_cgra_stencil_10 * _input_cgra_stencil_10; + int16_t _839 = _kernel_cgra_stencil_11 * _input_cgra_stencil_11; + int16_t _840 = _kernel_cgra_stencil_12 * _input_cgra_stencil_12; + int16_t _841 = _kernel_cgra_stencil_13 * _input_cgra_stencil_13; + int16_t _842 = _kernel_cgra_stencil_14 * _input_cgra_stencil_14; + int16_t _843 = _kernel_cgra_stencil_15 * _input_cgra_stencil_15; + int16_t _844 = _kernel_cgra_stencil_16 * _input_cgra_stencil_16; + int16_t _845 = _843 + _844; + int16_t _846 = _842 + _845; + int16_t _847 = _841 + _846; + int16_t _848 = _840 + _847; + int16_t _849 = _839 + _848; + int16_t _850 = _838 + _849; + int16_t _851 = _output_cgra_stencil_2 + _850; + int16_t _852 = _837 + _851; + return _852; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_10(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_17 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_18 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_19 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_20 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_21 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_22 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_23 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_24 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_17 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_18 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_19 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_20 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_21 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_22 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_23 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_24 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_3 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _906 = _kernel_cgra_stencil_17 * _input_cgra_stencil_17; + int16_t _907 = _kernel_cgra_stencil_18 * _input_cgra_stencil_18; + int16_t _908 = _kernel_cgra_stencil_19 * _input_cgra_stencil_19; + int16_t _909 = _kernel_cgra_stencil_20 * _input_cgra_stencil_20; + int16_t _910 = _kernel_cgra_stencil_21 * _input_cgra_stencil_21; + int16_t _911 = _kernel_cgra_stencil_22 * _input_cgra_stencil_22; + int16_t _912 = _kernel_cgra_stencil_23 * _input_cgra_stencil_23; + int16_t _913 = _kernel_cgra_stencil_24 * _input_cgra_stencil_24; + int16_t _914 = _912 + _913; + int16_t _915 = _911 + _914; + int16_t _916 = _910 + _915; + int16_t _917 = _909 + _916; + int16_t _918 = _908 + _917; + int16_t _919 = _907 + _918; + int16_t _920 = _output_cgra_stencil_3 + _919; + int16_t _921 = _906 + _920; + return _921; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_11(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_25 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_26 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_27 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_28 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_29 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_30 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_31 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_32 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_25 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_26 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_27 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_28 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_29 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_30 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_31 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_32 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_4 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _975 = _kernel_cgra_stencil_25 * _input_cgra_stencil_25; + int16_t _976 = _kernel_cgra_stencil_26 * _input_cgra_stencil_26; + int16_t _977 = _kernel_cgra_stencil_27 * _input_cgra_stencil_27; + int16_t _978 = _kernel_cgra_stencil_28 * _input_cgra_stencil_28; + int16_t _979 = _kernel_cgra_stencil_29 * _input_cgra_stencil_29; + int16_t _980 = _kernel_cgra_stencil_30 * _input_cgra_stencil_30; + int16_t _981 = _kernel_cgra_stencil_31 * _input_cgra_stencil_31; + int16_t _982 = _kernel_cgra_stencil_32 * _input_cgra_stencil_32; + int16_t _983 = _981 + _982; + int16_t _984 = _980 + _983; + int16_t _985 = _979 + _984; + int16_t _986 = _978 + _985; + int16_t _987 = _977 + _986; + int16_t _988 = _976 + _987; + int16_t _989 = _output_cgra_stencil_4 + _988; + int16_t _990 = _975 + _989; + return _990; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_12(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_33 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_34 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_35 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_36 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_37 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_38 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_39 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_40 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_33 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_34 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_35 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_36 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_37 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_38 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_39 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_40 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_5 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1044 = _kernel_cgra_stencil_33 * _input_cgra_stencil_33; + int16_t _1045 = _kernel_cgra_stencil_34 * _input_cgra_stencil_34; + int16_t _1046 = _kernel_cgra_stencil_35 * _input_cgra_stencil_35; + int16_t _1047 = _kernel_cgra_stencil_36 * _input_cgra_stencil_36; + int16_t _1048 = _kernel_cgra_stencil_37 * _input_cgra_stencil_37; + int16_t _1049 = _kernel_cgra_stencil_38 * _input_cgra_stencil_38; + int16_t _1050 = _kernel_cgra_stencil_39 * _input_cgra_stencil_39; + int16_t _1051 = _kernel_cgra_stencil_40 * _input_cgra_stencil_40; + int16_t _1052 = _1050 + _1051; + int16_t _1053 = _1049 + _1052; + int16_t _1054 = _1048 + _1053; + int16_t _1055 = _1047 + _1054; + int16_t _1056 = _1046 + _1055; + int16_t _1057 = _1045 + _1056; + int16_t _1058 = _output_cgra_stencil_5 + _1057; + int16_t _1059 = _1044 + _1058; + return _1059; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_13(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_41 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_42 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_43 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_44 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_45 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_46 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_47 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_48 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_41 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_42 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_43 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_44 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_45 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_46 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_47 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_48 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_6 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1113 = _kernel_cgra_stencil_41 * _input_cgra_stencil_41; + int16_t _1114 = _kernel_cgra_stencil_42 * _input_cgra_stencil_42; + int16_t _1115 = _kernel_cgra_stencil_43 * _input_cgra_stencil_43; + int16_t _1116 = _kernel_cgra_stencil_44 * _input_cgra_stencil_44; + int16_t _1117 = _kernel_cgra_stencil_45 * _input_cgra_stencil_45; + int16_t _1118 = _kernel_cgra_stencil_46 * _input_cgra_stencil_46; + int16_t _1119 = _kernel_cgra_stencil_47 * _input_cgra_stencil_47; + int16_t _1120 = _kernel_cgra_stencil_48 * _input_cgra_stencil_48; + int16_t _1121 = _1119 + _1120; + int16_t _1122 = _1118 + _1121; + int16_t _1123 = _1117 + _1122; + int16_t _1124 = _1116 + _1123; + int16_t _1125 = _1115 + _1124; + int16_t _1126 = _1114 + _1125; + int16_t _1127 = _output_cgra_stencil_6 + _1126; + int16_t _1128 = _1113 + _1127; + return _1128; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_14(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_49 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_50 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_51 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_52 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_53 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_54 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_55 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_56 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_49 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_50 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_51 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_52 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_53 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_54 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_55 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_56 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_7 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1182 = _kernel_cgra_stencil_49 * _input_cgra_stencil_49; + int16_t _1183 = _kernel_cgra_stencil_50 * _input_cgra_stencil_50; + int16_t _1184 = _kernel_cgra_stencil_51 * _input_cgra_stencil_51; + int16_t _1185 = _kernel_cgra_stencil_52 * _input_cgra_stencil_52; + int16_t _1186 = _kernel_cgra_stencil_53 * _input_cgra_stencil_53; + int16_t _1187 = _kernel_cgra_stencil_54 * _input_cgra_stencil_54; + int16_t _1188 = _kernel_cgra_stencil_55 * _input_cgra_stencil_55; + int16_t _1189 = _kernel_cgra_stencil_56 * _input_cgra_stencil_56; + int16_t _1190 = _1188 + _1189; + int16_t _1191 = _1187 + _1190; + int16_t _1192 = _1186 + _1191; + int16_t _1193 = _1185 + _1192; + int16_t _1194 = _1184 + _1193; + int16_t _1195 = _1183 + _1194; + int16_t _1196 = _output_cgra_stencil_7 + _1195; + int16_t _1197 = _1182 + _1196; + return _1197; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(0, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(1, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(2, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(3, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(4, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(5, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(7, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(6, (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_15(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_57 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_58 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_59 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_60 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_61 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_62 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_63 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_64 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_57 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_58 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_59 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_60 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_61 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_62 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_63 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_64 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_8 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1251 = _kernel_cgra_stencil_57 * _input_cgra_stencil_57; + int16_t _1252 = _kernel_cgra_stencil_58 * _input_cgra_stencil_58; + int16_t _1253 = _kernel_cgra_stencil_59 * _input_cgra_stencil_59; + int16_t _1254 = _kernel_cgra_stencil_60 * _input_cgra_stencil_60; + int16_t _1255 = _kernel_cgra_stencil_61 * _input_cgra_stencil_61; + int16_t _1256 = _kernel_cgra_stencil_62 * _input_cgra_stencil_62; + int16_t _1257 = _kernel_cgra_stencil_63 * _input_cgra_stencil_63; + int16_t _1258 = _kernel_cgra_stencil_64 * _input_cgra_stencil_64; + int16_t _1259 = _1257 + _1258; + int16_t _1260 = _1256 + _1259; + int16_t _1261 = _1255 + _1260; + int16_t _1262 = _1254 + _1261; + int16_t _1263 = _1253 + _1262; + int16_t _1264 = _1252 + _1263; + int16_t _1265 = _output_cgra_stencil_8 + _1264; + int16_t _1266 = _1251 + _1265; + return _1266; +} + +//store is: output_glb.stencil(((output_glb_s0_w_w_glb*64) + output_glb_s0_w_w_cgra), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) +hw_uint<16> hcompute_output_glb_stencil(hw_uint<16>& output_cgra_stencil) { + int16_t _output_cgra_stencil_9 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + return _output_cgra_stencil_9; +} + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& output_glb_stencil) { + int16_t _output_glb_stencil_1 = (int16_t) output_glb_stencil.extract<0, 15>(); + + return _output_glb_stencil_1; +} + diff --git a/resnet5_x_unroll_mic_compute.h b/resnet5_x_unroll_mic_compute.h new file mode 100644 index 000000000..c0637735f --- /dev/null +++ b/resnet5_x_unroll_mic_compute.h @@ -0,0 +1,465 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: input_glb.stencil((input_glb_s0_z_z*4), input_glb_s0_x, input_glb_s0_y) = input_host.stencil((input_glb_s0_z_z*4), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_1 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_1; +} + +//store is: input_glb.stencil(((input_glb_s0_z_z*4) + 1), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*4) + 1), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil_1(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_2 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_2; +} + +//store is: input_glb.stencil(((input_glb_s0_z_z*4) + 2), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*4) + 2), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil_2(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_3 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_3; +} + +//store is: input_glb.stencil(((input_glb_s0_z_z*4) + 3), input_glb_s0_x, input_glb_s0_y) = input_host.stencil(((input_glb_s0_z_z*4) + 3), input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil_3(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_4 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_4; +} + +//store is: kernel_glb.stencil(kernel_glb_s0_z_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) = kernel_host.stencil(kernel_glb_s0_z_z, kernel_glb_s0_w, kernel_glb_s0_x, kernel_glb_s0_y) +hw_uint<16> hcompute_kernel_glb_stencil(hw_uint<16>& kernel_host_stencil) { + int16_t _kernel_host_stencil_1 = (int16_t) kernel_host_stencil.extract<0, 15>(); + + return _kernel_host_stencil_1; +} + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil() { + int16_t _695 = (int16_t)(0); + return _695; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_1() { + int16_t _699 = (int16_t)(0); + return _699; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_2() { + int16_t _704 = (int16_t)(0); + return _704; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_3() { + int16_t _709 = (int16_t)(0); + return _709; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_4() { + int16_t _714 = (int16_t)(0); + return _714; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_5() { + int16_t _719 = (int16_t)(0); + return _719; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_6() { + int16_t _724 = (int16_t)(0); + return _724; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), output_cgra_s0_x, output_cgra_s0_y) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_7() { + int16_t _729 = (int16_t)(0); + return _729; +} + +//store is: input_cgra.stencil((input_cgra_s0_z_z_cgra_z_cgra*4), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_1 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_1; +} + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*4) + 1), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 1), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil_1(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_2 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_2; +} + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*4) + 2), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 2), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil_2(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_3 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_3; +} + +//store is: input_cgra.stencil(((input_cgra_s0_z_z_cgra_z_cgra*4) + 3), input_cgra_s0_x, input_cgra_s0_y) = input_glb.stencil(((((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra_z_cgra)*4) + 3), input_cgra_s0_x, input_cgra_s0_y) +hw_uint<16> hcompute_input_cgra_stencil_3(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_4 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_4; +} + +//store is: kernel_cgra.stencil(kernel_cgra_s0_z_z_cgra_z_cgra, kernel_cgra_s0_w_w_cgra, kernel_cgra_s0_x, kernel_cgra_s0_y) = kernel_glb.stencil(((output_cgra_s1_r_z_rz_glb*32) + kernel_cgra_s0_z_z_cgra_z_cgra), ((output_glb_s0_w_w_glb*64) + kernel_cgra_s0_w_w_cgra), kernel_cgra_s0_x, kernel_cgra_s0_y) +hw_uint<16> hcompute_kernel_cgra_stencil(hw_uint<16>& kernel_glb_stencil) { + int16_t _kernel_glb_stencil_1 = (int16_t) kernel_glb_stencil.extract<0, 15>(); + + return _kernel_glb_stencil_1; +} + +//store is: output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil((output_cgra_s1_w_w*8), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_w_w*8), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_8(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_1 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_2 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_3 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_4 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_5 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_6 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_7 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_8 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_1 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_2 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_3 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_4 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_5 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_6 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_7 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_8 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_1 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _780 = _kernel_cgra_stencil_1 * _input_cgra_stencil_1; + int16_t _781 = _kernel_cgra_stencil_2 * _input_cgra_stencil_2; + int16_t _782 = _kernel_cgra_stencil_3 * _input_cgra_stencil_3; + int16_t _783 = _kernel_cgra_stencil_4 * _input_cgra_stencil_4; + int16_t _784 = _kernel_cgra_stencil_5 * _input_cgra_stencil_5; + int16_t _785 = _kernel_cgra_stencil_6 * _input_cgra_stencil_6; + int16_t _786 = _kernel_cgra_stencil_7 * _input_cgra_stencil_7; + int16_t _787 = _kernel_cgra_stencil_8 * _input_cgra_stencil_8; + int16_t _788 = _786 + _787; + int16_t _789 = _785 + _788; + int16_t _790 = _784 + _789; + int16_t _791 = _783 + _790; + int16_t _792 = _782 + _791; + int16_t _793 = _781 + _792; + int16_t _794 = _output_cgra_stencil_1 + _793; + int16_t _795 = _780 + _794; + return _795; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 1), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 1), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_9(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_10 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_11 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_12 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_13 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_14 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_15 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_16 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_9 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_10 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_11 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_12 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_13 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_14 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_15 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_16 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_9 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_2 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _856 = _kernel_cgra_stencil_9 * _input_cgra_stencil_9; + int16_t _857 = _kernel_cgra_stencil_10 * _input_cgra_stencil_10; + int16_t _858 = _kernel_cgra_stencil_11 * _input_cgra_stencil_11; + int16_t _859 = _kernel_cgra_stencil_12 * _input_cgra_stencil_12; + int16_t _860 = _kernel_cgra_stencil_13 * _input_cgra_stencil_13; + int16_t _861 = _kernel_cgra_stencil_14 * _input_cgra_stencil_14; + int16_t _862 = _kernel_cgra_stencil_15 * _input_cgra_stencil_15; + int16_t _863 = _kernel_cgra_stencil_16 * _input_cgra_stencil_16; + int16_t _864 = _862 + _863; + int16_t _865 = _861 + _864; + int16_t _866 = _860 + _865; + int16_t _867 = _859 + _866; + int16_t _868 = _858 + _867; + int16_t _869 = _857 + _868; + int16_t _870 = _output_cgra_stencil_2 + _869; + int16_t _871 = _856 + _870; + return _871; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 2), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 2), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_10(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_17 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_18 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_19 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_20 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_21 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_22 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_23 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_24 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_17 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_18 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_19 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_20 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_21 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_22 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_23 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_24 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_3 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _933 = _kernel_cgra_stencil_17 * _input_cgra_stencil_17; + int16_t _934 = _kernel_cgra_stencil_18 * _input_cgra_stencil_18; + int16_t _935 = _kernel_cgra_stencil_19 * _input_cgra_stencil_19; + int16_t _936 = _kernel_cgra_stencil_20 * _input_cgra_stencil_20; + int16_t _937 = _kernel_cgra_stencil_21 * _input_cgra_stencil_21; + int16_t _938 = _kernel_cgra_stencil_22 * _input_cgra_stencil_22; + int16_t _939 = _kernel_cgra_stencil_23 * _input_cgra_stencil_23; + int16_t _940 = _kernel_cgra_stencil_24 * _input_cgra_stencil_24; + int16_t _941 = _939 + _940; + int16_t _942 = _938 + _941; + int16_t _943 = _937 + _942; + int16_t _944 = _936 + _943; + int16_t _945 = _935 + _944; + int16_t _946 = _934 + _945; + int16_t _947 = _output_cgra_stencil_3 + _946; + int16_t _948 = _933 + _947; + return _948; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 3), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 3), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_11(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_25 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_26 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_27 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_28 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_29 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_30 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_31 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_32 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_25 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_26 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_27 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_28 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_29 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_30 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_31 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_32 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_4 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1010 = _kernel_cgra_stencil_25 * _input_cgra_stencil_25; + int16_t _1011 = _kernel_cgra_stencil_26 * _input_cgra_stencil_26; + int16_t _1012 = _kernel_cgra_stencil_27 * _input_cgra_stencil_27; + int16_t _1013 = _kernel_cgra_stencil_28 * _input_cgra_stencil_28; + int16_t _1014 = _kernel_cgra_stencil_29 * _input_cgra_stencil_29; + int16_t _1015 = _kernel_cgra_stencil_30 * _input_cgra_stencil_30; + int16_t _1016 = _kernel_cgra_stencil_31 * _input_cgra_stencil_31; + int16_t _1017 = _kernel_cgra_stencil_32 * _input_cgra_stencil_32; + int16_t _1018 = _1016 + _1017; + int16_t _1019 = _1015 + _1018; + int16_t _1020 = _1014 + _1019; + int16_t _1021 = _1013 + _1020; + int16_t _1022 = _1012 + _1021; + int16_t _1023 = _1011 + _1022; + int16_t _1024 = _output_cgra_stencil_4 + _1023; + int16_t _1025 = _1010 + _1024; + return _1025; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 4), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 4), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_12(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_33 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_34 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_35 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_36 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_37 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_38 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_39 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_40 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_33 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_34 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_35 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_36 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_37 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_38 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_39 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_40 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_5 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1087 = _kernel_cgra_stencil_33 * _input_cgra_stencil_33; + int16_t _1088 = _kernel_cgra_stencil_34 * _input_cgra_stencil_34; + int16_t _1089 = _kernel_cgra_stencil_35 * _input_cgra_stencil_35; + int16_t _1090 = _kernel_cgra_stencil_36 * _input_cgra_stencil_36; + int16_t _1091 = _kernel_cgra_stencil_37 * _input_cgra_stencil_37; + int16_t _1092 = _kernel_cgra_stencil_38 * _input_cgra_stencil_38; + int16_t _1093 = _kernel_cgra_stencil_39 * _input_cgra_stencil_39; + int16_t _1094 = _kernel_cgra_stencil_40 * _input_cgra_stencil_40; + int16_t _1095 = _1093 + _1094; + int16_t _1096 = _1092 + _1095; + int16_t _1097 = _1091 + _1096; + int16_t _1098 = _1090 + _1097; + int16_t _1099 = _1089 + _1098; + int16_t _1100 = _1088 + _1099; + int16_t _1101 = _output_cgra_stencil_5 + _1100; + int16_t _1102 = _1087 + _1101; + return _1102; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 5), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 5), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_13(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_41 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_42 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_43 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_44 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_45 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_46 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_47 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_48 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_41 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_42 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_43 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_44 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_45 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_46 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_47 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_48 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_6 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1164 = _kernel_cgra_stencil_41 * _input_cgra_stencil_41; + int16_t _1165 = _kernel_cgra_stencil_42 * _input_cgra_stencil_42; + int16_t _1166 = _kernel_cgra_stencil_43 * _input_cgra_stencil_43; + int16_t _1167 = _kernel_cgra_stencil_44 * _input_cgra_stencil_44; + int16_t _1168 = _kernel_cgra_stencil_45 * _input_cgra_stencil_45; + int16_t _1169 = _kernel_cgra_stencil_46 * _input_cgra_stencil_46; + int16_t _1170 = _kernel_cgra_stencil_47 * _input_cgra_stencil_47; + int16_t _1171 = _kernel_cgra_stencil_48 * _input_cgra_stencil_48; + int16_t _1172 = _1170 + _1171; + int16_t _1173 = _1169 + _1172; + int16_t _1174 = _1168 + _1173; + int16_t _1175 = _1167 + _1174; + int16_t _1176 = _1166 + _1175; + int16_t _1177 = _1165 + _1176; + int16_t _1178 = _output_cgra_stencil_6 + _1177; + int16_t _1179 = _1164 + _1178; + return _1179; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 6), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 6), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_14(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_49 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_50 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_51 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_52 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_53 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_54 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_55 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_56 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_49 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_50 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_51 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_52 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_53 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_54 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_55 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_56 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_7 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1241 = _kernel_cgra_stencil_49 * _input_cgra_stencil_49; + int16_t _1242 = _kernel_cgra_stencil_50 * _input_cgra_stencil_50; + int16_t _1243 = _kernel_cgra_stencil_51 * _input_cgra_stencil_51; + int16_t _1244 = _kernel_cgra_stencil_52 * _input_cgra_stencil_52; + int16_t _1245 = _kernel_cgra_stencil_53 * _input_cgra_stencil_53; + int16_t _1246 = _kernel_cgra_stencil_54 * _input_cgra_stencil_54; + int16_t _1247 = _kernel_cgra_stencil_55 * _input_cgra_stencil_55; + int16_t _1248 = _kernel_cgra_stencil_56 * _input_cgra_stencil_56; + int16_t _1249 = _1247 + _1248; + int16_t _1250 = _1246 + _1249; + int16_t _1251 = _1245 + _1250; + int16_t _1252 = _1244 + _1251; + int16_t _1253 = _1243 + _1252; + int16_t _1254 = _1242 + _1253; + int16_t _1255 = _output_cgra_stencil_7 + _1254; + int16_t _1256 = _1241 + _1255; + return _1256; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) = ((kernel_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil((output_cgra_s1_r_z_rz_cgra_rz_cgra*8), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (output_cgra.stencil(((output_cgra_s1_w_w*8) + 7), output_cgra_s1_x, output_cgra_s1_y) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 1), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 2), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 3), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 4), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 5), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + ((kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 7), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))) + (kernel_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), ((output_cgra_s1_w_w*8) + 7), output_cgra_s1_r_x, output_cgra_s1_r_y)*input_cgra.stencil(((output_cgra_s1_r_z_rz_cgra_rz_cgra*8) + 6), (output_cgra_s1_r_x + output_cgra_s1_x), (output_cgra_s1_r_y + output_cgra_s1_y))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_15(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_57 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_58 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_59 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_60 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_61 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_62 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_63 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_64 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_57 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_58 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_59 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_60 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_61 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_62 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_63 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_64 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_8 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1318 = _kernel_cgra_stencil_57 * _input_cgra_stencil_57; + int16_t _1319 = _kernel_cgra_stencil_58 * _input_cgra_stencil_58; + int16_t _1320 = _kernel_cgra_stencil_59 * _input_cgra_stencil_59; + int16_t _1321 = _kernel_cgra_stencil_60 * _input_cgra_stencil_60; + int16_t _1322 = _kernel_cgra_stencil_61 * _input_cgra_stencil_61; + int16_t _1323 = _kernel_cgra_stencil_62 * _input_cgra_stencil_62; + int16_t _1324 = _kernel_cgra_stencil_63 * _input_cgra_stencil_63; + int16_t _1325 = _kernel_cgra_stencil_64 * _input_cgra_stencil_64; + int16_t _1326 = _1324 + _1325; + int16_t _1327 = _1323 + _1326; + int16_t _1328 = _1322 + _1327; + int16_t _1329 = _1321 + _1328; + int16_t _1330 = _1320 + _1329; + int16_t _1331 = _1319 + _1330; + int16_t _1332 = _output_cgra_stencil_8 + _1331; + int16_t _1333 = _1318 + _1332; + return _1333; +} + +//store is: output_glb.stencil(((output_glb_s0_w_w_glb*64) + output_glb_s0_w_w_cgra), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) = output_cgra.stencil(output_glb_s0_w_w_cgra, output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) +hw_uint<16> hcompute_output_glb_stencil(hw_uint<16>& output_cgra_stencil) { + int16_t _output_cgra_stencil_9 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + return _output_cgra_stencil_9; +} + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& output_glb_stencil) { + int16_t _output_glb_stencil_1 = (int16_t) output_glb_stencil.extract<0, 15>(); + + return _output_glb_stencil_1; +} + diff --git a/resnet_1x1_compute.h b/resnet_1x1_compute.h new file mode 100644 index 000000000..2534690e2 --- /dev/null +++ b/resnet_1x1_compute.h @@ -0,0 +1,423 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: input_glb.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) = input_host.stencil(input_glb_s0_z, input_glb_s0_x, input_glb_s0_y) +hw_uint<16> hcompute_input_glb_stencil(hw_uint<16>& input_host_stencil) { + int16_t _input_host_stencil_1 = (int16_t) input_host_stencil.extract<0, 15>(); + + return _input_host_stencil_1; +} + +//store is: kernel_glb.stencil(kernel_glb_s0_z, kernel_glb_s0_w, 0, 0) = kernel_host.stencil(kernel_glb_s0_z, kernel_glb_s0_w, 0, 0) +hw_uint<16> hcompute_kernel_glb_stencil(hw_uint<16>& kernel_host_stencil) { + int16_t _kernel_host_stencil_1 = (int16_t) kernel_host_stencil.extract<0, 15>(); + + return _kernel_host_stencil_1; +} + +//store is: output_cgra.stencil((output_cgra_s0_w_w*8), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil() { + int16_t _663 = (int16_t)(0); + return _663; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 1), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_1() { + int16_t _673 = (int16_t)(0); + return _673; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 2), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_2() { + int16_t _684 = (int16_t)(0); + return _684; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 3), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_3() { + int16_t _695 = (int16_t)(0); + return _695; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 4), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_4() { + int16_t _706 = (int16_t)(0); + return _706; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 5), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_5() { + int16_t _717 = (int16_t)(0); + return _717; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 6), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_6() { + int16_t _728 = (int16_t)(0); + return _728; +} + +//store is: output_cgra.stencil(((output_cgra_s0_w_w*8) + 7), (((output_glb_s0_x_x_glb*14) + output_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = (int16)0 +hw_uint<16> hcompute_output_cgra_stencil_7() { + int16_t _739 = (int16_t)(0); + return _739; +} + +//store is: input_cgra.stencil(input_cgra_s0_z_z_cgra, (((output_glb_s0_x_x_glb*14) + input_cgra_s0_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + input_cgra_s0_y) - (output_glb_s0_y_y_glb*14))) = input_glb.stencil(((output_cgra_s1_r_z_rz_glb*8) + input_cgra_s0_z_z_cgra), ((output_glb_s0_x_x_glb*14) + input_cgra_s0_x), ((output_glb_s0_y_y_glb*14) + input_cgra_s0_y)) +hw_uint<16> hcompute_input_cgra_stencil(hw_uint<16>& input_glb_stencil) { + int16_t _input_glb_stencil_1 = (int16_t) input_glb_stencil.extract<0, 15>(); + + return _input_glb_stencil_1; +} + +//store is: kernel_cgra.stencil(kernel_cgra_s0_z_z_cgra, kernel_cgra_s0_w_w_cgra, 0, 0) = kernel_glb.stencil(((output_cgra_s1_r_z_rz_glb*8) + kernel_cgra_s0_z_z_cgra), kernel_cgra_s0_w_w_cgra, 0, 0) +hw_uint<16> hcompute_kernel_cgra_stencil(hw_uint<16>& kernel_glb_stencil) { + int16_t _kernel_glb_stencil_1 = (int16_t) kernel_glb_stencil.extract<0, 15>(); + + return _kernel_glb_stencil_1; +} + +//store is: output_cgra.stencil((output_cgra_s1_w_w_cgra*8), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil((output_cgra_s1_w_w_cgra*8), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, (output_cgra_s1_w_w_cgra*8), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_8(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_1 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_2 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_3 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_4 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_5 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_6 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_7 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_8 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_1 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_2 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_3 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_4 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_5 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_6 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_7 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_8 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_1 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _766 = _kernel_cgra_stencil_1 * _input_cgra_stencil_1; + int16_t _767 = _kernel_cgra_stencil_2 * _input_cgra_stencil_2; + int16_t _768 = _kernel_cgra_stencil_3 * _input_cgra_stencil_3; + int16_t _769 = _kernel_cgra_stencil_4 * _input_cgra_stencil_4; + int16_t _770 = _kernel_cgra_stencil_5 * _input_cgra_stencil_5; + int16_t _771 = _kernel_cgra_stencil_6 * _input_cgra_stencil_6; + int16_t _772 = _kernel_cgra_stencil_7 * _input_cgra_stencil_7; + int16_t _773 = _kernel_cgra_stencil_8 * _input_cgra_stencil_8; + int16_t _774 = _772 + _773; + int16_t _775 = _771 + _774; + int16_t _776 = _770 + _775; + int16_t _777 = _769 + _776; + int16_t _778 = _768 + _777; + int16_t _779 = _767 + _778; + int16_t _780 = _output_cgra_stencil_1 + _779; + int16_t _781 = _766 + _780; + return _781; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 1), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 1), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 1), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_9(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_10 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_11 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_12 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_13 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_14 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_15 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_16 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_9 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_10 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_11 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_12 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_13 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_14 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_15 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_16 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_9 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_2 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _838 = _kernel_cgra_stencil_9 * _input_cgra_stencil_9; + int16_t _839 = _kernel_cgra_stencil_10 * _input_cgra_stencil_10; + int16_t _840 = _kernel_cgra_stencil_11 * _input_cgra_stencil_11; + int16_t _841 = _kernel_cgra_stencil_12 * _input_cgra_stencil_12; + int16_t _842 = _kernel_cgra_stencil_13 * _input_cgra_stencil_13; + int16_t _843 = _kernel_cgra_stencil_14 * _input_cgra_stencil_14; + int16_t _844 = _kernel_cgra_stencil_15 * _input_cgra_stencil_15; + int16_t _845 = _kernel_cgra_stencil_16 * _input_cgra_stencil_16; + int16_t _846 = _844 + _845; + int16_t _847 = _843 + _846; + int16_t _848 = _842 + _847; + int16_t _849 = _841 + _848; + int16_t _850 = _840 + _849; + int16_t _851 = _839 + _850; + int16_t _852 = _output_cgra_stencil_2 + _851; + int16_t _853 = _838 + _852; + return _853; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 2), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 2), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 2), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_10(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_17 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_18 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_19 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_20 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_21 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_22 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_23 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_24 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_17 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_18 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_19 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_20 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_21 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_22 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_23 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_24 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_3 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _911 = _kernel_cgra_stencil_17 * _input_cgra_stencil_17; + int16_t _912 = _kernel_cgra_stencil_18 * _input_cgra_stencil_18; + int16_t _913 = _kernel_cgra_stencil_19 * _input_cgra_stencil_19; + int16_t _914 = _kernel_cgra_stencil_20 * _input_cgra_stencil_20; + int16_t _915 = _kernel_cgra_stencil_21 * _input_cgra_stencil_21; + int16_t _916 = _kernel_cgra_stencil_22 * _input_cgra_stencil_22; + int16_t _917 = _kernel_cgra_stencil_23 * _input_cgra_stencil_23; + int16_t _918 = _kernel_cgra_stencil_24 * _input_cgra_stencil_24; + int16_t _919 = _917 + _918; + int16_t _920 = _916 + _919; + int16_t _921 = _915 + _920; + int16_t _922 = _914 + _921; + int16_t _923 = _913 + _922; + int16_t _924 = _912 + _923; + int16_t _925 = _output_cgra_stencil_3 + _924; + int16_t _926 = _911 + _925; + return _926; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 3), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 3), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 3), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_11(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_25 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_26 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_27 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_28 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_29 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_30 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_31 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_32 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_25 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_26 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_27 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_28 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_29 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_30 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_31 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_32 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_4 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _984 = _kernel_cgra_stencil_25 * _input_cgra_stencil_25; + int16_t _985 = _kernel_cgra_stencil_26 * _input_cgra_stencil_26; + int16_t _986 = _kernel_cgra_stencil_27 * _input_cgra_stencil_27; + int16_t _987 = _kernel_cgra_stencil_28 * _input_cgra_stencil_28; + int16_t _988 = _kernel_cgra_stencil_29 * _input_cgra_stencil_29; + int16_t _989 = _kernel_cgra_stencil_30 * _input_cgra_stencil_30; + int16_t _990 = _kernel_cgra_stencil_31 * _input_cgra_stencil_31; + int16_t _991 = _kernel_cgra_stencil_32 * _input_cgra_stencil_32; + int16_t _992 = _990 + _991; + int16_t _993 = _989 + _992; + int16_t _994 = _988 + _993; + int16_t _995 = _987 + _994; + int16_t _996 = _986 + _995; + int16_t _997 = _985 + _996; + int16_t _998 = _output_cgra_stencil_4 + _997; + int16_t _999 = _984 + _998; + return _999; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 4), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 4), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 4), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_12(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_33 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_34 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_35 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_36 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_37 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_38 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_39 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_40 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_33 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_34 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_35 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_36 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_37 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_38 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_39 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_40 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_5 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1057 = _kernel_cgra_stencil_33 * _input_cgra_stencil_33; + int16_t _1058 = _kernel_cgra_stencil_34 * _input_cgra_stencil_34; + int16_t _1059 = _kernel_cgra_stencil_35 * _input_cgra_stencil_35; + int16_t _1060 = _kernel_cgra_stencil_36 * _input_cgra_stencil_36; + int16_t _1061 = _kernel_cgra_stencil_37 * _input_cgra_stencil_37; + int16_t _1062 = _kernel_cgra_stencil_38 * _input_cgra_stencil_38; + int16_t _1063 = _kernel_cgra_stencil_39 * _input_cgra_stencil_39; + int16_t _1064 = _kernel_cgra_stencil_40 * _input_cgra_stencil_40; + int16_t _1065 = _1063 + _1064; + int16_t _1066 = _1062 + _1065; + int16_t _1067 = _1061 + _1066; + int16_t _1068 = _1060 + _1067; + int16_t _1069 = _1059 + _1068; + int16_t _1070 = _1058 + _1069; + int16_t _1071 = _output_cgra_stencil_5 + _1070; + int16_t _1072 = _1057 + _1071; + return _1072; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 5), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 5), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 5), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_13(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_41 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_42 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_43 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_44 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_45 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_46 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_47 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_48 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_41 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_42 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_43 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_44 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_45 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_46 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_47 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_48 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_6 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1130 = _kernel_cgra_stencil_41 * _input_cgra_stencil_41; + int16_t _1131 = _kernel_cgra_stencil_42 * _input_cgra_stencil_42; + int16_t _1132 = _kernel_cgra_stencil_43 * _input_cgra_stencil_43; + int16_t _1133 = _kernel_cgra_stencil_44 * _input_cgra_stencil_44; + int16_t _1134 = _kernel_cgra_stencil_45 * _input_cgra_stencil_45; + int16_t _1135 = _kernel_cgra_stencil_46 * _input_cgra_stencil_46; + int16_t _1136 = _kernel_cgra_stencil_47 * _input_cgra_stencil_47; + int16_t _1137 = _kernel_cgra_stencil_48 * _input_cgra_stencil_48; + int16_t _1138 = _1136 + _1137; + int16_t _1139 = _1135 + _1138; + int16_t _1140 = _1134 + _1139; + int16_t _1141 = _1133 + _1140; + int16_t _1142 = _1132 + _1141; + int16_t _1143 = _1131 + _1142; + int16_t _1144 = _output_cgra_stencil_6 + _1143; + int16_t _1145 = _1130 + _1144; + return _1145; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 6), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 6), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 6), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_14(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_49 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_50 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_51 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_52 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_53 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_54 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_55 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_56 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_49 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_50 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_51 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_52 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_53 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_54 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_55 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_56 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_7 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1203 = _kernel_cgra_stencil_49 * _input_cgra_stencil_49; + int16_t _1204 = _kernel_cgra_stencil_50 * _input_cgra_stencil_50; + int16_t _1205 = _kernel_cgra_stencil_51 * _input_cgra_stencil_51; + int16_t _1206 = _kernel_cgra_stencil_52 * _input_cgra_stencil_52; + int16_t _1207 = _kernel_cgra_stencil_53 * _input_cgra_stencil_53; + int16_t _1208 = _kernel_cgra_stencil_54 * _input_cgra_stencil_54; + int16_t _1209 = _kernel_cgra_stencil_55 * _input_cgra_stencil_55; + int16_t _1210 = _kernel_cgra_stencil_56 * _input_cgra_stencil_56; + int16_t _1211 = _1209 + _1210; + int16_t _1212 = _1208 + _1211; + int16_t _1213 = _1207 + _1212; + int16_t _1214 = _1206 + _1213; + int16_t _1215 = _1205 + _1214; + int16_t _1216 = _1204 + _1215; + int16_t _1217 = _output_cgra_stencil_7 + _1216; + int16_t _1218 = _1203 + _1217; + return _1218; +} + +//store is: output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 7), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) = ((kernel_cgra.stencil(0, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(0, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (output_cgra.stencil(((output_cgra_s1_w_w_cgra*8) + 7), (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14))) + ((kernel_cgra.stencil(1, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(1, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(2, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(2, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(3, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(3, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(4, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(4, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(5, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(5, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + ((kernel_cgra.stencil(7, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(7, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))) + (kernel_cgra.stencil(6, ((output_cgra_s1_w_w_cgra*8) + 7), 0, 0)*input_cgra.stencil(6, (((output_glb_s0_x_x_glb*14) + output_cgra_s1_x) - (output_glb_s0_x_x_glb*14)), (((output_glb_s0_y_y_glb*14) + output_cgra_s1_y) - (output_glb_s0_y_y_glb*14)))))))))))) +hw_uint<16> hcompute_output_cgra_stencil_15(hw_uint<128>& input_cgra_stencil, hw_uint<128>& kernel_cgra_stencil, hw_uint<16>& output_cgra_stencil) { + int16_t _input_cgra_stencil_57 = (int16_t) input_cgra_stencil.extract<0, 15>(); + int16_t _input_cgra_stencil_58 = (int16_t) input_cgra_stencil.extract<16, 31>(); + int16_t _input_cgra_stencil_59 = (int16_t) input_cgra_stencil.extract<32, 47>(); + int16_t _input_cgra_stencil_60 = (int16_t) input_cgra_stencil.extract<48, 63>(); + int16_t _input_cgra_stencil_61 = (int16_t) input_cgra_stencil.extract<64, 79>(); + int16_t _input_cgra_stencil_62 = (int16_t) input_cgra_stencil.extract<80, 95>(); + int16_t _input_cgra_stencil_63 = (int16_t) input_cgra_stencil.extract<96, 111>(); + int16_t _input_cgra_stencil_64 = (int16_t) input_cgra_stencil.extract<112, 127>(); + + int16_t _kernel_cgra_stencil_57 = (int16_t) kernel_cgra_stencil.extract<0, 15>(); + int16_t _kernel_cgra_stencil_58 = (int16_t) kernel_cgra_stencil.extract<16, 31>(); + int16_t _kernel_cgra_stencil_59 = (int16_t) kernel_cgra_stencil.extract<32, 47>(); + int16_t _kernel_cgra_stencil_60 = (int16_t) kernel_cgra_stencil.extract<48, 63>(); + int16_t _kernel_cgra_stencil_61 = (int16_t) kernel_cgra_stencil.extract<64, 79>(); + int16_t _kernel_cgra_stencil_62 = (int16_t) kernel_cgra_stencil.extract<80, 95>(); + int16_t _kernel_cgra_stencil_63 = (int16_t) kernel_cgra_stencil.extract<96, 111>(); + int16_t _kernel_cgra_stencil_64 = (int16_t) kernel_cgra_stencil.extract<112, 127>(); + + int16_t _output_cgra_stencil_8 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + int16_t _1276 = _kernel_cgra_stencil_57 * _input_cgra_stencil_57; + int16_t _1277 = _kernel_cgra_stencil_58 * _input_cgra_stencil_58; + int16_t _1278 = _kernel_cgra_stencil_59 * _input_cgra_stencil_59; + int16_t _1279 = _kernel_cgra_stencil_60 * _input_cgra_stencil_60; + int16_t _1280 = _kernel_cgra_stencil_61 * _input_cgra_stencil_61; + int16_t _1281 = _kernel_cgra_stencil_62 * _input_cgra_stencil_62; + int16_t _1282 = _kernel_cgra_stencil_63 * _input_cgra_stencil_63; + int16_t _1283 = _kernel_cgra_stencil_64 * _input_cgra_stencil_64; + int16_t _1284 = _1282 + _1283; + int16_t _1285 = _1281 + _1284; + int16_t _1286 = _1280 + _1285; + int16_t _1287 = _1279 + _1286; + int16_t _1288 = _1278 + _1287; + int16_t _1289 = _1277 + _1288; + int16_t _1290 = _output_cgra_stencil_8 + _1289; + int16_t _1291 = _1276 + _1290; + return _1291; +} + +//store is: output_glb.stencil(((output_glb_s0_w_w_cgra_w_cgra*8) + output_glb_s0_w_w_cgra_w_unroll), ((output_glb_s0_x_x_glb*14) + output_glb_s0_x_x_cgra), ((output_glb_s0_y_y_glb*14) + output_glb_s0_y_y_cgra)) = output_cgra.stencil(((output_glb_s0_w_w_cgra_w_cgra*8) + output_glb_s0_w_w_cgra_w_unroll), output_glb_s0_x_x_cgra, output_glb_s0_y_y_cgra) +hw_uint<16> hcompute_output_glb_stencil(hw_uint<16>& output_cgra_stencil) { + int16_t _output_cgra_stencil_9 = (int16_t) output_cgra_stencil.extract<0, 15>(); + + return _output_cgra_stencil_9; +} + +//store is: hw_output.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) = output_glb.stencil(hw_output_s0_w, hw_output_s0_x_xi, hw_output_s0_y_yi) +hw_uint<16> hcompute_hw_output_stencil(hw_uint<16>& output_glb_stencil) { + int16_t _output_glb_stencil_1 = (int16_t) output_glb_stencil.extract<0, 15>(); + + return _output_glb_stencil_1; +} + diff --git a/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048.cpp b/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048.cpp index 76b0e2d02..e98ac098c 100644 --- a/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048.cpp +++ b/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048.cpp @@ -2216,14 +2216,14 @@ inline void lp_in_on_chip_0_buf48_reconstruct_lp70_buf73_rc78_write_bundle_write struct lp_in_on_chip_1_buf40_diff43_110_to_lp_in_on_chip_1_buf40_load_to_lp_in_on_chip_1_buf40_to_gp_6236239_34_cache { // RAM Box: {[0, 31], [0, 31]} - // Capacity: 67 - // # of read delays: 67 - // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66 - fifo , 67> f; + // Capacity: 3 + // # of read delays: 3 + // 0, 1, 2 + fifo , 3> f; inline hw_uint<32> peek(const int offset) { #ifdef __VIVADO_SYNTH__ #endif //__VIVADO_SYNTH__ - return f.peek(66 - offset); + return f.peek(2 - offset); } @@ -2253,9 +2253,9 @@ inline hw_uint<32> lp_in_on_chip_1_buf40_load_to_lp_in_on_chip_1_buf40_to_gp_62 #ifdef __VIVADO_SYNTH__ #endif //__VIVADO_SYNTH__ // lp_in_on_chip_1_buf40_load_to_lp_in_on_chip_1_buf40_to_gp_6236239_34 read pattern: { load_to_lp_in_on_chip_1_buf40_to_gp_6236239[root = 0, lp_in_on_chip_1_buf40_ld238, lp_in_on_chip_1_buf40_ld237] -> lp_in_on_chip_1_buf40[lp_in_on_chip_1_buf40_ld237, lp_in_on_chip_1_buf40_ld238] : 0 <= lp_in_on_chip_1_buf40_ld238 <= 31 and 0 <= lp_in_on_chip_1_buf40_ld237 <= 31 } - // Read schedule : { load_to_lp_in_on_chip_1_buf40_to_gp_6236239[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 27] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } + // Read schedule : { load_to_lp_in_on_chip_1_buf40_to_gp_6236239[d0 = 0, d1, d2] -> [0, 10 + 2d1, 14 + 2d2, 27] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } // Write schedule: { diff43[d0 = 0, d1, d2] -> [0, 10 + 2d1, 10 + 2d2, 26] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } - auto value_lp_in_on_chip_1_buf40_diff43_110 = lp_in_on_chip_1_buf40.lp_in_on_chip_1_buf40_diff43_110_to_lp_in_on_chip_1_buf40_load_to_lp_in_on_chip_1_buf40_to_gp_6236239_34.peek(/* one reader or all rams */ (-31 + lp_in_on_chip_1_buf40_ld237 == 0 && -30 + lp_in_on_chip_1_buf40_ld238 == 0) ? (32) : (-31 + lp_in_on_chip_1_buf40_ld237 == 0 && 29 - lp_in_on_chip_1_buf40_ld238 >= 0) ? (64) : (-30 + lp_in_on_chip_1_buf40_ld237 == 0 && 29 - lp_in_on_chip_1_buf40_ld238 >= 0) ? (65) : (29 - lp_in_on_chip_1_buf40_ld237 >= 0 && 29 - lp_in_on_chip_1_buf40_ld238 >= 0) ? (66) : (-31 + lp_in_on_chip_1_buf40_ld238 == 0 && 30 - lp_in_on_chip_1_buf40_ld237 >= 0) ? ((31 - lp_in_on_chip_1_buf40_ld237)) : (-30 + lp_in_on_chip_1_buf40_ld238 == 0 && 30 - lp_in_on_chip_1_buf40_ld237 >= 0) ? ((63 - lp_in_on_chip_1_buf40_ld237)) : 0); + auto value_lp_in_on_chip_1_buf40_diff43_110 = lp_in_on_chip_1_buf40.lp_in_on_chip_1_buf40_diff43_110_to_lp_in_on_chip_1_buf40_load_to_lp_in_on_chip_1_buf40_to_gp_6236239_34.peek(/* one reader or all rams */ (-30 + lp_in_on_chip_1_buf40_ld237 == 0) ? (1) : (29 - lp_in_on_chip_1_buf40_ld237 >= 0) ? (2) : 0); return value_lp_in_on_chip_1_buf40_diff43_110; return 0; } @@ -2282,14 +2282,14 @@ inline hw_uint<32> lp_in_on_chip_1_buf40_load_to_lp_in_on_chip_1_buf40_to_gp_623 struct lp_in_on_chip_1_buf40_FIFO_buf240_load_to_lp_in_on_chip_1_buf40_FIFO_buf240243_39_to_lp_in_on_chip_1_buf40_FIFO_buf240_rc69_16_cache { // RAM Box: {[0, 31], [0, 31]} - // Capacity: 1 - // # of read delays: 2 - // 0, 0 - fifo , 1> f; + // Capacity: 65 + // # of read delays: 65 + // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 + fifo , 65> f; inline hw_uint<32> peek(const int offset) { #ifdef __VIVADO_SYNTH__ #endif //__VIVADO_SYNTH__ - return f.peek(0 - offset); + return f.peek(64 - offset); } @@ -2320,8 +2320,8 @@ inline hw_uint<32> lp_in_on_chip_1_buf40_FIFO_buf240_rc69_16_select(lp_in_on_ch #endif //__VIVADO_SYNTH__ // lp_in_on_chip_1_buf40_FIFO_buf240_rc69_16 read pattern: { rc69[root = 0, lp_in_on_chip_1_buf40_reconstruct_lp6162, lp_in_on_chip_1_buf40_reconstruct_lp6163] -> lp_in_on_chip_1_buf40_FIFO_buf240[lp_in_on_chip_1_buf40_reconstruct_lp6163, lp_in_on_chip_1_buf40_reconstruct_lp6162] : 0 <= lp_in_on_chip_1_buf40_reconstruct_lp6162 <= 31 and 0 <= lp_in_on_chip_1_buf40_reconstruct_lp6163 <= 31 } // Read schedule : { rc69[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 37] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } - // Write schedule: { load_to_lp_in_on_chip_1_buf40_FIFO_buf240243[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 28] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } - auto value_lp_in_on_chip_1_buf40_FIFO_buf240_load_to_lp_in_on_chip_1_buf40_FIFO_buf240243_39 = lp_in_on_chip_1_buf40_FIFO_buf240.lp_in_on_chip_1_buf40_FIFO_buf240_load_to_lp_in_on_chip_1_buf40_FIFO_buf240243_39_to_lp_in_on_chip_1_buf40_FIFO_buf240_rc69_16.peek(/* one reader or all rams */ 0); + // Write schedule: { load_to_lp_in_on_chip_1_buf40_FIFO_buf240243[d0 = 0, d1, d2] -> [0, 10 + 2d1, 14 + 2d2, 28] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } + auto value_lp_in_on_chip_1_buf40_FIFO_buf240_load_to_lp_in_on_chip_1_buf40_FIFO_buf240243_39 = lp_in_on_chip_1_buf40_FIFO_buf240.lp_in_on_chip_1_buf40_FIFO_buf240_load_to_lp_in_on_chip_1_buf40_FIFO_buf240243_39_to_lp_in_on_chip_1_buf40_FIFO_buf240_rc69_16.peek(/* one reader or all rams */ (-31 + lp_in_on_chip_1_buf40_reconstruct_lp6163 == 0 && -30 + lp_in_on_chip_1_buf40_reconstruct_lp6162 == 0) ? (32) : (30 - lp_in_on_chip_1_buf40_reconstruct_lp6163 >= 0 && 29 - lp_in_on_chip_1_buf40_reconstruct_lp6162 >= 0) ? (64) : (-31 + lp_in_on_chip_1_buf40_reconstruct_lp6162 == 0 && 30 - lp_in_on_chip_1_buf40_reconstruct_lp6163 >= 0) ? ((31 - lp_in_on_chip_1_buf40_reconstruct_lp6163)) : (-31 + lp_in_on_chip_1_buf40_reconstruct_lp6163 == 0 && 29 - lp_in_on_chip_1_buf40_reconstruct_lp6162 >= 0) ? (64) : (-30 + lp_in_on_chip_1_buf40_reconstruct_lp6162 == 0 && 30 - lp_in_on_chip_1_buf40_reconstruct_lp6163 >= 0) ? ((63 - lp_in_on_chip_1_buf40_reconstruct_lp6163)) : 0); return value_lp_in_on_chip_1_buf40_FIFO_buf240_load_to_lp_in_on_chip_1_buf40_FIFO_buf240243_39; return 0; } @@ -2876,19 +2876,6 @@ inline hw_uint<32> lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264 // Total re-use buffer capacity: 17600 bits // Operation logic -inline void load_to_gp_in_on_chip_2_buf12_FIFO_buf184187(HWStream >& /* buffer_args num ports = 1 */gp_in_on_chip_2_buf12_to_gp_2180, gp_in_on_chip_2_buf12_FIFO_buf184_cache& gp_in_on_chip_2_buf12_FIFO_buf184, int d0, int d1, int d2) { - // Dynamic address computation - - // Consume: gp_in_on_chip_2_buf12_to_gp_2180 - auto gp_in_on_chip_2_buf12_to_gp_2180_gp_in_on_chip_2_buf12_to_gp_2180_ld185_c__gp_in_on_chip_2_buf12_to_gp_2180_ld186_value = gp_in_on_chip_2_buf12_to_gp_2180.read(); - // Produce: gp_in_on_chip_2_buf12_FIFO_buf184 - gp_in_on_chip_2_buf12_FIFO_buf184_load_to_gp_in_on_chip_2_buf12_FIFO_buf184187_write_bundle_write(/* arg names */gp_in_on_chip_2_buf12_to_gp_2180_gp_in_on_chip_2_buf12_to_gp_2180_ld185_c__gp_in_on_chip_2_buf12_to_gp_2180_ld186_value, gp_in_on_chip_2_buf12_FIFO_buf184, d0, d1, d2, 0); - -#ifndef __VIVADO_SYNTH__ -#endif //__VIVADO_SYNTH__ - -} - inline void gp_in_on_chip_322_merged160(gp_in_on_chip_2_buf12_FIFO_buf184_cache& gp_in_on_chip_2_buf12_FIFO_buf184, gp_in_on_chip_3_buf20_cache& gp_in_on_chip_3_buf20, int d0, int d1, int d2) { // Dynamic address computation @@ -2907,6 +2894,19 @@ inline void gp_in_on_chip_322_merged160(gp_in_on_chip_2_buf12_FIFO_buf184_cache& } +inline void load_to_gp_in_on_chip_2_buf12_FIFO_buf184187(HWStream >& /* buffer_args num ports = 1 */gp_in_on_chip_2_buf12_to_gp_2180, gp_in_on_chip_2_buf12_FIFO_buf184_cache& gp_in_on_chip_2_buf12_FIFO_buf184, int d0, int d1, int d2) { + // Dynamic address computation + + // Consume: gp_in_on_chip_2_buf12_to_gp_2180 + auto gp_in_on_chip_2_buf12_to_gp_2180_gp_in_on_chip_2_buf12_to_gp_2180_ld185_c__gp_in_on_chip_2_buf12_to_gp_2180_ld186_value = gp_in_on_chip_2_buf12_to_gp_2180.read(); + // Produce: gp_in_on_chip_2_buf12_FIFO_buf184 + gp_in_on_chip_2_buf12_FIFO_buf184_load_to_gp_in_on_chip_2_buf12_FIFO_buf184187_write_bundle_write(/* arg names */gp_in_on_chip_2_buf12_to_gp_2180_gp_in_on_chip_2_buf12_to_gp_2180_ld185_c__gp_in_on_chip_2_buf12_to_gp_2180_ld186_value, gp_in_on_chip_2_buf12_FIFO_buf184, d0, d1, d2, 0); + +#ifndef __VIVADO_SYNTH__ +#endif //__VIVADO_SYNTH__ + +} + inline void us31(gp_in_on_chip_3_buf20_cache& gp_in_on_chip_3_buf20, gp_in_on_chip_3_buf20_us28_cache& gp_in_on_chip_3_buf20_us28, int d0, int d1, int d2) { // Dynamic address computation @@ -3433,9 +3433,9 @@ void Extracted_gp_in_on_chip_1_buf4_to_gp_5164_ld170_gp_in_on_chip_2_buf12_us36_ #pragma HLS inline recursive #endif // __VIVADO_SYNTH__ -// schedule: { load_to_lp_in_on_chip_1_buf40_to_gp_6236239[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 27] : 0 <= d1 <= 31 and 0 <= d2 <= 31; load_to_gp_in_on_chip_1_buf4_FIFO_buf168171[d0 = 0, d1, d2] -> [0, 4 + 2d1, 4 + 2d2, 3] : 3 <= d1 <= 34 and 3 <= d2 <= 34; load_to_gp_in_on_chip_2_buf12_us36_FIFO_buf200203[d0 = 0, d1, d2] -> [0, 10 + 2d1, 10 + 2d2, 22] : 0 <= d1 <= 31 and 0 <= d2 <= 31; diff43[d0 = 0, d1, d2] -> [0, 10 + 2d1, 10 + 2d2, 26] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } -// { load_to_lp_in_on_chip_1_buf40_to_gp_6236239[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 27] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } -// Condition for load_to_lp_in_on_chip_1_buf40_to_gp_6236239(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-27 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-14 + 1*i1)) >= 0) && (((76 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((76 + -1*i2)) >= 0))) +// schedule: { load_to_lp_in_on_chip_1_buf40_to_gp_6236239[d0 = 0, d1, d2] -> [0, 10 + 2d1, 14 + 2d2, 27] : 0 <= d1 <= 31 and 0 <= d2 <= 31; load_to_gp_in_on_chip_1_buf4_FIFO_buf168171[d0 = 0, d1, d2] -> [0, 4 + 2d1, 4 + 2d2, 3] : 3 <= d1 <= 34 and 3 <= d2 <= 34; load_to_gp_in_on_chip_2_buf12_us36_FIFO_buf200203[d0 = 0, d1, d2] -> [0, 10 + 2d1, 10 + 2d2, 22] : 0 <= d1 <= 31 and 0 <= d2 <= 31; diff43[d0 = 0, d1, d2] -> [0, 10 + 2d1, 10 + 2d2, 26] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } +// { load_to_lp_in_on_chip_1_buf40_to_gp_6236239[d0 = 0, d1, d2] -> [0, 10 + 2d1, 14 + 2d2, 27] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } +// Condition for load_to_lp_in_on_chip_1_buf40_to_gp_6236239(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-27 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-10 + 1*i1)) >= 0) && (((72 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((76 + -1*i2)) >= 0))) // { load_to_gp_in_on_chip_1_buf4_FIFO_buf168171[d0 = 0, d1, d2] -> [0, 4 + 2d1, 4 + 2d2, 3] : 3 <= d1 <= 34 and 3 <= d2 <= 34 } // Condition for load_to_gp_in_on_chip_1_buf4_FIFO_buf168171(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-3 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-10 + 1*i1)) >= 0) && (((72 + -1*i1)) >= 0) && (((-10 + 1*i2)) >= 0) && (((72 + -1*i2)) >= 0))) // { load_to_gp_in_on_chip_2_buf12_us36_FIFO_buf200203[d0 = 0, d1, d2] -> [0, 10 + 2d1, 10 + 2d2, 22] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } @@ -3443,47 +3443,43 @@ void Extracted_gp_in_on_chip_1_buf4_to_gp_5164_ld170_gp_in_on_chip_2_buf12_us36_ // { diff43[d0 = 0, d1, d2] -> [0, 10 + 2d1, 10 + 2d2, 26] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } // Condition for diff43(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-26 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-10 + 1*i1)) >= 0) && (((72 + -1*i1)) >= 0) && (((-10 + 1*i2)) >= 0) && (((72 + -1*i2)) >= 0))) - // time range: { [0, i1, i2, 27] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 14 <= i1 <= 76 and 14 <= i2 <= 76; [0, i1, i2, 26] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 10 <= i2 <= 72; [0, i1, i2, 22] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 10 <= i2 <= 72; [0, i1, i2, 3] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 10 <= i2 <= 72 } + // time range: { [0, i1, i2, 27] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 14 <= i2 <= 76; [0, i1, i2, 26] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 10 <= i2 <= 72; [0, i1, i2, 22] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 10 <= i2 <= 72; [0, i1, i2, 3] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 10 <= i2 <= 72 } // # sets: 1 int i0 = 0; - for (int i1 = 10; i1 <= 76; i1++) { + for (int i1 = 10; i1 <= 72; i1++) { for (int i2 = 10; i2 <= 76; i2++) { #pragma HLS pipeline II=1 - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 and i2 <= 72 } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 and i2 <= 72 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 <= 72 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 <= 72 } // { [i0, i1, i2] : -i2 + 2*floor((i2)/2) = 0 } // { [i0, i1, i2] : -i1 + 2*floor((i1)/2) = 0 } - // { [i0, i1, i2] : 72 - i1 >= 0 } // { [i0, i1, i2] : 72 - i2 >= 0 } - if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((72 + -1*i1)) >= 0) && (((72 + -1*i2)) >= 0)))) { + if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((72 + -1*i2)) >= 0)))) { load_to_gp_in_on_chip_1_buf4_FIFO_buf168171(gp_in_on_chip_1_buf4_to_gp_5164 /* buf name */, gp_in_on_chip_1_buf4_FIFO_buf168, 0, ((-2 + (1*(((1*i1)) >> 1)))), ((-2 + (1*(((1*i2)) >> 1))))); } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 and i2 <= 72 } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 and i2 <= 72 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 <= 72 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 <= 72 } // { [i0, i1, i2] : -i2 + 2*floor((i2)/2) = 0 } // { [i0, i1, i2] : -i1 + 2*floor((i1)/2) = 0 } - // { [i0, i1, i2] : 72 - i1 >= 0 } // { [i0, i1, i2] : 72 - i2 >= 0 } - if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((72 + -1*i1)) >= 0) && (((72 + -1*i2)) >= 0)))) { + if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((72 + -1*i2)) >= 0)))) { load_to_gp_in_on_chip_2_buf12_us36_FIFO_buf200203(gp_in_on_chip_2_buf12_us36_to_gp_5196 /* buf name */, gp_in_on_chip_2_buf12_us36_FIFO_buf200, 0, ((-5 + (1*(((1*i1)) >> 1)))), ((-5 + (1*(((1*i2)) >> 1))))); } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 and i2 <= 72 } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 and i2 <= 72 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 <= 72 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 <= 72 } // { [i0, i1, i2] : -i2 + 2*floor((i2)/2) = 0 } // { [i0, i1, i2] : -i1 + 2*floor((i1)/2) = 0 } - // { [i0, i1, i2] : 72 - i1 >= 0 } // { [i0, i1, i2] : 72 - i2 >= 0 } - if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((72 + -1*i1)) >= 0) && (((72 + -1*i2)) >= 0)))) { + if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((72 + -1*i2)) >= 0)))) { diff43(gp_in_on_chip_1_buf4_FIFO_buf168 /* buf name */, gp_in_on_chip_2_buf12_us36_FIFO_buf200 /* buf name */, lp_in_on_chip_1_buf40, 0, ((-5 + (1*(((1*i1)) >> 1)))), ((-5 + (1*(((1*i2)) >> 1))))); } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 >= 14 and i2 >= 14 } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 >= 14 and i2 >= 14 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 >= 14 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i2 >= 14 } // { [i0, i1, i2] : -i2 + 2*floor((i2)/2) = 0 } // { [i0, i1, i2] : -i1 + 2*floor((i1)/2) = 0 } - // { [i0, i1, i2] : -14 + i1 >= 0 } // { [i0, i1, i2] : -14 + i2 >= 0 } - if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-14 + 1*i1)) >= 0) && (((-14 + 1*i2)) >= 0)))) { - load_to_lp_in_on_chip_1_buf40_to_gp_6236239(lp_in_on_chip_1_buf40 /* buf name */, lp_in_on_chip_1_buf40_to_gp_6236, 0, ((-7 + (1*(((1*i1)) >> 1)))), ((-7 + (1*(((1*i2)) >> 1))))); + if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-14 + 1*i2)) >= 0)))) { + load_to_lp_in_on_chip_1_buf40_to_gp_6236239(lp_in_on_chip_1_buf40 /* buf name */, lp_in_on_chip_1_buf40_to_gp_6236, 0, ((-5 + (1*(((1*i1)) >> 1)))), ((-7 + (1*(((1*i2)) >> 1))))); } } } @@ -3601,53 +3597,58 @@ void Extracted_lp_in_on_chip_1_buf40_reconstruct_lp6162_lp_in_on_chip_1_buf40_re #pragma HLS inline recursive #endif // __VIVADO_SYNTH__ -// schedule: { rc69[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 37] : 0 <= d1 <= 31 and 0 <= d2 <= 31; us77[d0 = 0, d1, d2] -> [0, 14 + d1, 14 + d2, 38] : 0 <= d1 <= 63 and 0 <= d2 <= 63; load_to_lp_in_on_chip_1_buf40_FIFO_buf240243[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 28] : 0 <= d1 <= 31 and 0 <= d2 <= 31; load_to_lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74_to_gp_4244247[d0 = 0, d1, d2] -> [0, 14 + d1, 14 + d2, 39] : 0 <= d1 <= 63 and 0 <= d2 <= 63; load_to_lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264267[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 36] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } +// schedule: { rc69[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 37] : 0 <= d1 <= 31 and 0 <= d2 <= 31; us77[d0 = 0, d1, d2] -> [0, 14 + d1, 14 + d2, 38] : 0 <= d1 <= 63 and 0 <= d2 <= 63; load_to_lp_in_on_chip_1_buf40_FIFO_buf240243[d0 = 0, d1, d2] -> [0, 10 + 2d1, 14 + 2d2, 28] : 0 <= d1 <= 31 and 0 <= d2 <= 31; load_to_lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74_to_gp_4244247[d0 = 0, d1, d2] -> [0, 14 + d1, 14 + d2, 39] : 0 <= d1 <= 63 and 0 <= d2 <= 63; load_to_lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264267[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 36] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } // { rc69[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 37] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } // Condition for rc69(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-37 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-14 + 1*i1)) >= 0) && (((76 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((76 + -1*i2)) >= 0))) // { us77[d0 = 0, d1, d2] -> [0, 14 + d1, 14 + d2, 38] : 0 <= d1 <= 63 and 0 <= d2 <= 63 } // Condition for us77(((((-38 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-14 + 1*i1)) >= 0) && (((77 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((77 + -1*i2)) >= 0))) -// { load_to_lp_in_on_chip_1_buf40_FIFO_buf240243[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 28] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } -// Condition for load_to_lp_in_on_chip_1_buf40_FIFO_buf240243(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-28 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-14 + 1*i1)) >= 0) && (((76 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((76 + -1*i2)) >= 0))) +// { load_to_lp_in_on_chip_1_buf40_FIFO_buf240243[d0 = 0, d1, d2] -> [0, 10 + 2d1, 14 + 2d2, 28] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } +// Condition for load_to_lp_in_on_chip_1_buf40_FIFO_buf240243(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-28 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-10 + 1*i1)) >= 0) && (((72 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((76 + -1*i2)) >= 0))) // { load_to_lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74_to_gp_4244247[d0 = 0, d1, d2] -> [0, 14 + d1, 14 + d2, 39] : 0 <= d1 <= 63 and 0 <= d2 <= 63 } // Condition for load_to_lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74_to_gp_4244247(((((-39 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-14 + 1*i1)) >= 0) && (((77 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((77 + -1*i2)) >= 0))) // { load_to_lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264267[d0 = 0, d1, d2] -> [0, 14 + 2d1, 14 + 2d2, 36] : 0 <= d1 <= 31 and 0 <= d2 <= 31 } // Condition for load_to_lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264267(((((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-36 + 1*i3)) == 0) && (((1*i0)) == 0) && (((-14 + 1*i1)) >= 0) && (((76 + -1*i1)) >= 0) && (((-14 + 1*i2)) >= 0) && (((76 + -1*i2)) >= 0))) - // time range: { [0, i1, i2, i3] : 14 <= i1 <= 77 and 14 <= i2 <= 77 and 36 <= i3 <= 39 and (i3 >= 38 or ((i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 76 and i2 <= 76 and i3 <= 37)); [0, i1, i2, 28] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 14 <= i1 <= 76 and 14 <= i2 <= 76 } + // time range: { [0, i1, i2, i3] : 14 <= i1 <= 77 and 14 <= i2 <= 77 and 36 <= i3 <= 39 and (i3 >= 38 or ((i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 76 and i2 <= 76 and i3 <= 37)); [0, i1, i2, 28] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and 10 <= i1 <= 72 and 14 <= i2 <= 76 } // # sets: 1 int i0 = 0; - for (int i1 = 14; i1 <= 77; i1++) { + for (int i1 = 10; i1 <= 77; i1++) { for (int i2 = 14; i2 <= 77; i2++) { #pragma HLS pipeline II=1 - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 <= 72 } // { [i0, i1, i2] : -i2 + 2*floor((i2)/2) = 0 } // { [i0, i1, i2] : -i1 + 2*floor((i1)/2) = 0 } - if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0)))) { - load_to_lp_in_on_chip_1_buf40_FIFO_buf240243(lp_in_on_chip_1_buf40_to_gp_6236 /* buf name */, lp_in_on_chip_1_buf40_FIFO_buf240, 0, ((-7 + (1*(((1*i1)) >> 1)))), ((-7 + (1*(((1*i2)) >> 1))))); + // { [i0, i1, i2] : 72 - i1 >= 0 } + if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((72 + -1*i1)) >= 0)))) { + load_to_lp_in_on_chip_1_buf40_FIFO_buf240243(lp_in_on_chip_1_buf40_to_gp_6236 /* buf name */, lp_in_on_chip_1_buf40_FIFO_buf240, 0, ((-5 + (1*(((1*i1)) >> 1)))), ((-7 + (1*(((1*i2)) >> 1))))); } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 >= 14 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 >= 14 } // { [i0, i1, i2] : -i2 + 2*floor((i2)/2) = 0 } // { [i0, i1, i2] : -i1 + 2*floor((i1)/2) = 0 } - if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0)))) { + // { [i0, i1, i2] : -14 + i1 >= 0 } + if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-14 + 1*i1)) >= 0)))) { load_to_lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264267(lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_to_gp_6260 /* buf name */, lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264, 0, ((-7 + (1*(((1*i1)) >> 1)))), ((-7 + (1*(((1*i2)) >> 1))))); } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 } - // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 >= 14 } + // { [i0, i1, i2] : (i1) mod 2 = 0 and (i2) mod 2 = 0 and i1 >= 14 } // { [i0, i1, i2] : -i2 + 2*floor((i2)/2) = 0 } // { [i0, i1, i2] : -i1 + 2*floor((i1)/2) = 0 } - if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0)))) { + // { [i0, i1, i2] : -14 + i1 >= 0 } + if ((((((-1*i2 + (2*(((1*i2)) >> 1)))) == 0) && (((-1*i1 + (2*(((1*i1)) >> 1)))) == 0) && (((-14 + 1*i1)) >= 0)))) { rc69(lp_in_on_chip_1_buf40_FIFO_buf240 /* buf name */, lp_in_on_chip_2_buf32_reconstruct_lp52_buf55_us65_FIFO_buf264 /* buf name */, lp_in_on_chip_1_buf40_reconstruct_lp61_buf64, 0, ((-7 + (1*(((1*i1)) >> 1)))), ((-7 + (1*(((1*i2)) >> 1))))); } - // { [i0, i1, i2] } - // { [i0, i1, i2] : } - if ((true)) { + // { [i0, i1, i2] : i1 >= 14 } + // { [i0, i1, i2] : i1 >= 14 } + // { [i0, i1, i2] : -14 + i1 >= 0 } + if ((((((-14 + 1*i1)) >= 0)))) { us77(lp_in_on_chip_1_buf40_reconstruct_lp61_buf64 /* buf name */, lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74, 0, ((-14 + 1*i1)), ((-14 + 1*i2))); } - // { [i0, i1, i2] } - // { [i0, i1, i2] : } - if ((true)) { + // { [i0, i1, i2] : i1 >= 14 } + // { [i0, i1, i2] : i1 >= 14 } + // { [i0, i1, i2] : -14 + i1 >= 0 } + if ((((((-14 + 1*i1)) >= 0)))) { load_to_lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74_to_gp_4244247(lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74 /* buf name */, lp_in_on_chip_1_buf40_reconstruct_lp61_buf64_us74_to_gp_4244, 0, ((-14 + 1*i1)), ((-14 + 1*i2))); } } diff --git a/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048_sw_bmp_test_harness.cpp b/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048_sw_bmp_test_harness.cpp index ea9f5c5ec..e05f0a9b2 100644 --- a/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048_sw_bmp_test_harness.cpp +++ b/soda_codes/pyr_blnd2d500_2048/our_code/pyr_blnd2d500_2048_sw_bmp_test_harness.cpp @@ -10,8 +10,8 @@ int main(int argc, char **argv) { HWStream > pw_math_in03_read_channel; HWStream > pw_math_lp_in_on_chip_0_buf48_reconstruct_lp70_buf737982_write_channel; // In lanes = 1 - for (int r = 0; r < 67; r++) { - for (int cl = 0; cl < 67 / 1; cl++) { + for (int r = 0; r < 71; r++) { + for (int cl = 0; cl < 71 / 1; cl++) { hw_uint<32> packed; { int c = 1*cl + 0; diff --git a/soda_codes/pyr_blnd2d500_2048/soda_code/soda_pyr_blnd2d500_2048_host.cpp b/soda_codes/pyr_blnd2d500_2048/soda_code/soda_pyr_blnd2d500_2048_host.cpp index c1e9aefab..68a951b0a 100644 --- a/soda_codes/pyr_blnd2d500_2048/soda_code/soda_pyr_blnd2d500_2048_host.cpp +++ b/soda_codes/pyr_blnd2d500_2048/soda_code/soda_pyr_blnd2d500_2048_host.cpp @@ -22,13 +22,13 @@ int main(int argc, char **argv) { size_t total_size_bytes = 0; size_t total_size_bytes_read = 0; size_t total_size_bytes_written = 0; - const int pw_math_in03_read_pipe0_DATA_SIZE = num_epochs*4489; + const int pw_math_in03_read_pipe0_DATA_SIZE = num_epochs*5041; const int pw_math_in03_read_BYTES_PER_PIXEL = 32 / 8; size_t pw_math_in03_read_size_bytes = pw_math_in03_read_BYTES_PER_PIXEL * pw_math_in03_read_pipe0_DATA_SIZE; total_size_bytes += pw_math_in03_read_size_bytes; total_size_bytes_read += pw_math_in03_read_size_bytes; - const int pw_math_lp_in_on_chip_0_buf48_reconstruct_lp70_buf737982_write_pipe0_DATA_SIZE = num_epochs*4489; + const int pw_math_lp_in_on_chip_0_buf48_reconstruct_lp70_buf737982_write_pipe0_DATA_SIZE = num_epochs*5041; const int pw_math_lp_in_on_chip_0_buf48_reconstruct_lp70_buf737982_write_BYTES_PER_PIXEL = 32 / 8; size_t pw_math_lp_in_on_chip_0_buf48_reconstruct_lp70_buf737982_write_size_bytes = pw_math_lp_in_on_chip_0_buf48_reconstruct_lp70_buf737982_write_BYTES_PER_PIXEL * pw_math_lp_in_on_chip_0_buf48_reconstruct_lp70_buf737982_write_pipe0_DATA_SIZE; @@ -108,7 +108,7 @@ int main(int argc, char **argv) { OCL_CHECK(err, cl::Buffer pw_math_in03_read_pipe0_ocl_buf(context, CL_MEM_USE_HOST_PTR | CL_MEM_WRITE_ONLY, pw_math_in03_read_size_bytes, pw_math_in03_read_pipe0.data(), &err)); OCL_CHECK(err, err = krnl_vector_add.setArg(1, pw_math_in03_read_pipe0_ocl_buf)); - uint64_t transfer_size = num_epochs*(4489 / 1); + uint64_t transfer_size = num_epochs*(5041 / 1); OCL_CHECK(err, err = krnl_vector_add.setArg(2, transfer_size)); std::cout << "Migrating memory" << std::endl; diff --git a/soda_codes/pyr_blnd2d500_2048/soda_code/tb_soda_pyr_blnd2d500_2048.cpp b/soda_codes/pyr_blnd2d500_2048/soda_code/tb_soda_pyr_blnd2d500_2048.cpp index 12cb1107e..efe71ac9c 100644 --- a/soda_codes/pyr_blnd2d500_2048/soda_code/tb_soda_pyr_blnd2d500_2048.cpp +++ b/soda_codes/pyr_blnd2d500_2048/soda_code/tb_soda_pyr_blnd2d500_2048.cpp @@ -12,8 +12,8 @@ using namespace std; int main() { srand(234); - const int nrows = 67; - const int ncols = 67; + const int nrows = 71; + const int ncols = 71; uint64_t img_pixels = nrows*ncols; const uint64_t bits_per_pixel = PIXEL_WIDTH; uint64_t img_bits = bits_per_pixel*img_pixels; diff --git a/ubuffer.cpp b/ubuffer.cpp index 17b49c651..af166146f 100644 --- a/ubuffer.cpp +++ b/ubuffer.cpp @@ -1,7 +1,9 @@ #include "ubuffer.h" #include "codegen.h" +#include "app.h" #ifdef COREIR #include "cwlib.h" +#include "cgralib.h" #include "coreir_backend.h" #include "lake_target.h" @@ -778,7 +780,7 @@ isl_map* UBuffer::get_coarse_grained_pipeline_schedule(CodegenOptions& options, isl_map* merged_sched; if (need_double_buffer) { //TODO: only implement double buffer for lake - assert(config_mode == "lake"); + //assert(config_mode == "lake"); //optimize the double buffer isl_set* cgpl_dom = ::domain(cgpl_sched); int stripmine_ext = get_dim_extent(cgpl_dom, coarse_grained_pipeline_loop_level); @@ -810,6 +812,11 @@ isl_map* UBuffer::get_coarse_grained_pipeline_schedule(CodegenOptions& options, auto new_pt_sched = remove_in_dims(sched, cgpl_levels); auto new_acc_map = remove_in_dims(acc_map, cgpl_levels); + //Thanks GOD! this function save my life!! can remove the implicit division and turn it into equality + //TODO: move this into simplify + isl_map_detect_equalities(new_pt_sched); + isl_map_detect_equalities(new_acc_map); + cout << "\tnew pt schedule: " << str(new_pt_sched) << endl; cout << "\tnew acc_pattern: " << str(new_acc_map) << endl; @@ -996,69 +1003,273 @@ maybe> get_project_dim(UBuffer & buf, bool is_read) { } void UBufferImpl::remove_bank(int bank_id) { + + lowering_info.erase(bank_id); + bank_rddom.erase(bank_id); - for(auto it = bank_rddom.begin(); it != bank_rddom.end(); it ++){ - if (it->first > bank_id) { - auto node = bank_rddom.extract(it->first); - node.key() = it->first - 1; - bank_rddom.insert(std::move(node)); - } - } + //for(auto it = bank_rddom.begin(); it != bank_rddom.end(); it ++){ + // if (it->first > bank_id) { + // auto node = bank_rddom.extract(it->first); + // node.key() = it->first - 1; + // bank_rddom.insert(std::move(node)); + // } + //} bank_readers.erase(bank_id); - for(auto it = bank_readers.begin(); it != bank_readers.end(); it ++){ - if (it->first > bank_id) { - auto node = bank_readers.extract(it->first); - node.key() = it->first - 1; - bank_readers.insert(std::move(node)); - } - } + //for(auto it = bank_readers.begin(); it != bank_readers.end(); it ++){ + // if (it->first > bank_id) { + // auto node = bank_readers.extract(it->first); + // node.key() = it->first - 1; + // bank_readers.insert(std::move(node)); + // } + //} bank_writers.erase(bank_id); - for(auto it = bank_writers.begin(); it != bank_writers.end(); it ++){ - if (it->first > bank_id) { - auto node = bank_writers.extract(it->first); - node.key() = it->first - 1; - bank_writers.insert(std::move(node)); - } - } + //for(auto it = bank_writers.begin(); it != bank_writers.end(); it ++){ + // if (it->first > bank_id) { + // auto node = bank_writers.extract(it->first); + // node.key() = it->first - 1; + // bank_writers.insert(std::move(node)); + // } + //} bank_outpt2readers.erase(bank_id); - for(auto it = bank_outpt2readers.begin(); it != bank_outpt2readers.end(); it ++){ - if (it->first > bank_id) { - auto node = bank_outpt2readers.extract(it->first); - node.key() = it->first - 1; - bank_outpt2readers.insert(std::move(node)); - } - } + //for(auto it = bank_outpt2readers.begin(); it != bank_outpt2readers.end(); it ++){ + // if (it->first > bank_id) { + // auto node = bank_outpt2readers.extract(it->first); + // node.key() = it->first - 1; + // bank_outpt2readers.insert(std::move(node)); + // } + //} bank_inpt2writers.erase(bank_id); - for(auto it = bank_inpt2writers.begin(); it != bank_inpt2writers.end(); it ++){ - if (it->first > bank_id) { - auto node = bank_inpt2writers.extract(it->first); - node.key() = it->first - 1; - bank_inpt2writers.insert(std::move(node)); - } - } + //for(auto it = bank_inpt2writers.begin(); it != bank_inpt2writers.end(); it ++){ + // if (it->first > bank_id) { + // auto node = bank_inpt2writers.extract(it->first); + // node.key() = it->first - 1; + // bank_inpt2writers.insert(std::move(node)); + // } + //} for (auto& it: outpt_to_bank) { it.second.erase(bank_id); - for (auto bk: it.second) { - if (bk > bank_id) { - auto val = it.second.extract(bk); - val.value() = bk - 1; - it.second.insert(std::move(val)); - } - } + // for (auto bk: it.second) { + // if (bk > bank_id) { + // auto val = it.second.extract(bk); + // val.value() = bk - 1; + // it.second.insert(std::move(val)); + // } + // } } for (auto& it: inpt_to_bank) { it.second.erase(bank_id); - for (auto bk: it.second) { - if (bk > bank_id) { - auto val = it.second.extract(bk); - val.value() = bk - 1; - it.second.insert(std::move(val)); - } + // for (auto bk: it.second) { + // if (bk > bank_id) { + // auto val = it.second.extract(bk); + // val.value() = bk - 1; + // it.second.insert(std::move(val)); + // } + // } + } +} + +UBuffer merge_sram_with_different_outpt(vector & buffers, string new_name) { + //Merge buffers into one + UBuffer merge_buf; + auto buf = pick(buffers); + merge_buf.port_widths = buf.port_widths; + merge_buf.ctx = buf.ctx; + merge_buf.name = new_name + "_sram"; + + + map sched_record_map; + for (auto sram: buffers){ + for (auto bd: sram.port_bundles) { + //All ports in the same bundle have the same schedule + string unique_pt = pick(bd.second); + if (!merge_buf.port_bundles.count(bd.first)) { + merge_buf.port_bundles.insert(bd); + for (string pt: bd.second) { + merge_buf.isIn[pt] = sram.isIn.at(pt); + merge_buf.domain[pt] = sram.domain.at(pt); + auto am = to_map(sram.access_map.at(pt)); + merge_buf.access_map[pt] = to_umap(set_range_name(am, new_name + "_sram")); + } + //Add the schedule + isl_map* sched_map = to_map(sram.schedule.at(unique_pt)); + cout << "get SRAM port schedule: " << str(sched_map) << endl; + + //need to rename the domain name if the same stmt are loading the data + if(sched_record_map.count(domain_name(sched_map))) { + string dname = domain_name(sched_map); + vector substr = + split_at(dname, "_"); + int idx = safe_stoi(substr.back()); + substr.back() = str(idx+1); + string new_dname = sep_list(substr, "", "", "_"); + sched_map = set_domain_name(sched_map, new_dname); + cout << str(sched_map) << endl; + } + + if (!violate_deps(sched_map, sched_record_map)) { + + // Input port should not violate dependency + sched_record_map.insert({domain_name(sched_map), sched_map}); + + //All sram ports should share the same schedule + for (string pt: bd.second) { + merge_buf.schedule[pt] = to_umap(sched_map); + } + } else { + assert(!sram.is_in_pt(unique_pt)); + isl_map* adjust_schedule = + get_sram2tb_schedule_with_check(sched_map, sched_record_map, 0/*ahead step*/, num_in_dims(sched_map) - 1/**/, 0, false/*is_dual_port*/); + sched_record_map.insert({domain_name(adjust_schedule), adjust_schedule}); + + //All sram ports should share the same schedule + for (string pt: bd.second) { + merge_buf.schedule[pt] = to_umap(adjust_schedule); + } + } + } + + } + } + + //Add another pass to rename the port name + merge_buf.sequentially_rename_output_domain_suffix(0); + + cout << merge_buf << endl; + return merge_buf; +} + +UBuffer merge_buf_with_different_outpt(vector & buffers, string new_name) { + //Merge buffers into one + UBuffer merge_buf; + auto buf = pick(buffers); + merge_buf.port_widths = buf.port_widths; + merge_buf.name = new_name ; + + + map sched_record_map; + for (auto sram: buffers){ + for (auto bd: sram.port_bundles) { + //All ports in the same bundle have the same schedule + string unique_pt = pick(bd.second); + if (!merge_buf.port_bundles.count(bd.first)) { + merge_buf.port_bundles.insert(bd); + for (string pt: bd.second) { + merge_buf.isIn[pt] = sram.isIn.at(pt); + merge_buf.domain[pt] = sram.domain.at(pt); + auto am = to_map(sram.access_map.at(pt)); + merge_buf.access_map[pt] = to_umap(set_range_name(am, new_name)); + merge_buf.schedule[pt] = sram.schedule.at(pt); + } + } + } + } + cout << merge_buf << endl; + return merge_buf; +} + +void UBufferImpl::merge_banks_and_rewrite(vector & banks_tobe_merged) { + vector srams, target_buffers; + for (auto bank_id: banks_tobe_merged) { + UBuffer sram; + for (auto it: lowering_info.at(bank_id).sub_component) { + cout << "\tsubcomponent keys:" << it.first << endl; + if (contains(it.first, "sram")) { + sram = it.second; } + } + cout << sram << endl; + srams.push_back(sram); + target_buffers.push_back(lowering_info.at(bank_id).target_buf); + } + + //TODO check the other impl are the same + GarnetImpl merged_impl; + int bank_id_0 = pick(banks_tobe_merged); + merged_impl = lowering_info.at(bank_id_0); + merged_impl.sub_component.clear(); + + + std::set merge_inpts, merge_outpts; + for (int bank_id: banks_tobe_merged) { + assert(bank_writers.at(bank_id).size() == 1); + assert(bank_readers.at(bank_id).size() == 1); + merge_inpts.merge(bank_writers.at(bank_id)); + merge_outpts.merge(bank_readers.at(bank_id)); + } + //TODO: may need an extra check if we can merge more port + //assert(merge_inpts.size() <= options.rtl_options.max_inpt); + //assert(merge_outpts.size() <= options.rtl_options.max_outpt); + int new_bk = add_new_bank_between(merge_inpts, merge_outpts, + bank_rddom.at(banks_tobe_merged.front())); + for (string inpt: merge_inpts) { + map_insert(bank_inpt2writers, new_bk, {inpt}); + } + for (string outpt: merge_outpts) { + map_insert(bank_outpt2readers, new_bk, {outpt}); + } + + cout << "new banks id: " << new_bk << endl;; + + string new_sram_name = get_buf_name() + "_bank_" + str(new_bk); + + auto sram_merged = merge_sram_with_different_outpt(srams, new_sram_name); + + //Also merge target buffer + merged_impl.target_buf = merge_buf_with_different_outpt(target_buffers, new_sram_name); + + + merged_impl.sub_component.insert({new_sram_name, sram_merged}); + auto stmt2sched = sram_merged.get_stmt2sched(); + + int tb_cnt = 0; + map outpt2tb; + for (auto bank_id: banks_tobe_merged) { + for (auto it: lowering_info.at(bank_id).sub_component) { + cout << "sub component buf: " << get_micro_buf_name(it.first) << endl; + if (get_micro_buf_name(it.first) == "agg") { + auto micro_buf = it.second; + string new_agg_name = new_sram_name + "_0_agg"; + micro_buf.remap_access_to_new_buffer_name(new_agg_name); + merged_impl.sub_component.insert({new_agg_name, micro_buf}); + } + // sort the tb name by it's bundle + if (get_micro_buf_name(it.first) == "tb") { + auto micro_buf = it.second; + assert(micro_buf.get_out_bundles().size() == 1); + string outbd = pick(micro_buf.get_out_bundles()); + outpt2tb.insert({outbd, micro_buf}); + } + } + } + for (auto it: outpt2tb) { + string new_tb_name = new_sram_name + "_" + str(tb_cnt) + "_tb"; + it.second.remap_access_to_new_buffer_name(new_tb_name); + it.second.sequentially_rename_input_domain_suffix(tb_cnt); + it.second.sequentially_rename_output_domain_suffix(tb_cnt); + //update tb in schedule with + for (auto& schedule_it: it.second.schedule) { + string dname = domain_name(schedule_it.second); + if (stmt2sched.count(dname)) + schedule_it.second = stmt2sched.at(dname); + } + merged_impl.sub_component.insert({new_tb_name, it.second}); + tb_cnt++; + cout << "micor buf: " << it.second << endl; + } + for (auto bk: banks_tobe_merged) { + remove_bank(bk); } + lowering_info[new_bk] = merged_impl; + + cout << *this << endl; + + //TODO: add new banks sub component + } + void UBufferImpl::merge_banks(vector banks_tobe_merged) { + assert(banks_tobe_merged.size() > 0); std::set merge_inpts, merge_outpts; for (int bank_id: banks_tobe_merged) { assert(bank_writers.at(bank_id).size() == 1); @@ -1103,10 +1314,12 @@ void UBufferImpl::conditional_merging(CodegenOptions & options, const vector merging_banks; while(true) { //full condition + //cout << "Merging banks: " << merging_banks << endl; if(get_banks_inpts_num(merging_banks) > max_inpt || get_banks_outpts_num(merging_banks) > max_outpt) { auto last_bank = merging_banks.back(); merging_banks.pop_back(); + //cout << merging_banks << endl; merge_banks(merging_banks); merging_banks.clear(); merging_banks.push_back(last_bank); @@ -1119,6 +1332,99 @@ void UBufferImpl::conditional_merging(CodegenOptions & options, const vectorbank_rddom.at(a), this->bank_rddom.at(b)); + }; + //std::set merge_inpts, merge_outpts; + //vector> merge_banks; + map, decltype(comp)> merge_map(comp); + + int max_inpt = options.mem_hierarchy.at("mem").get_inpt_num(); + int max_outpt = options.mem_hierarchy.at("mem").get_outpt_num(); + for (auto it: bank_rddom) { + int bank_id = it.first; + cout << "bank id: " << bank_id << endl; + cout << "rd dom: " << str(it.second) << endl; + string mem = lowering_info.at(bank_id).config_mode; + //Only do bank merging for lake + if (mem != "lake") + continue; + + + + //cout << "BANK ID: " << bank_id << "\n\tbank_map:" << str(it.second) << endl; + + //Not merge this buffer if it decouple the control or + //need shift register optimization + if (lowering_info.at(bank_id).decouple_ctrl || + lowering_info.at(bank_id).insert_shift_register) + continue; + + //TODO: check the rate less than 1 / 4 cycle otherwise cannot merge + //check_rate_ + if (get_sram_read_rate(lowering_info.at(bank_id)) < options.mem_hierarchy.at("mem").fetch_width) { + continue; + } + + if ((bank_readers.at(bank_id).size() < max_outpt) && + (bank_writers.at(bank_id).size() < max_inpt)) { + if (merge_map.count(bank_id)) { + merge_map[bank_id].push_back(it.first); + } else { + merge_map[bank_id] = {bank_id}; + } + } + } + for (auto it: merge_map) { + cout << "bank id: " << it.first << ", to be merged: " << it.second << endl; + if (it.second.size() > 1) { + cout << "\tGroup: " << it.first << ": " << it.second << endl; + cout << "\tPerform bank merging!" << endl; + vector banks_tobe_merged = it.second; + sort(banks_tobe_merged.begin(), banks_tobe_merged.end(), std::greater()); + + //put some banks into the merging list + vector merging_banks; + auto bk_it = banks_tobe_merged.begin(); + while (true) { + if(get_banks_inpts_num(merging_banks) > max_inpt || + get_banks_outpts_num(merging_banks) > max_outpt) { + auto last_bank = merging_banks.back(); + merging_banks.pop_back(); + //cout << merging_banks << endl; + merge_banks_and_rewrite(merging_banks); + merging_banks.clear(); + merging_banks.push_back(last_bank); + } else if (bk_it == banks_tobe_merged.end()) { + merge_banks_and_rewrite(merging_banks); + break; + } else { + merging_banks.push_back(*bk_it); + bk_it ++; + } + } + } + } +} void UBufferImpl::bank_merging(CodegenOptions & options) { auto comp = [this](const int& a, const int& b) { @@ -1128,14 +1434,23 @@ void UBufferImpl::bank_merging(CodegenOptions & options) { //vector> merge_banks; map, decltype(comp)> merge_map(comp); for (auto it: bank_rddom) { - int bank_id = it.first; + int bank_id = it.first; + string mem = get_memory_hierarchy(options, bank_id); + int max_inpt = options.mem_hierarchy.at(mem).get_inpt_num(); + int max_outpt = options.mem_hierarchy.at(mem).get_outpt_num(); + //cout << "BANK ID: " << bank_id << "\n\tbank_map:" << str(it.second) << endl; + if ((bank_readers.at(bank_id).size() < max_outpt) && + (bank_writers.at(bank_id).size() < max_inpt)) { if (merge_map.count(bank_id)) { - merge_map[bank_id].push_back(it.first); + merge_map[bank_id].push_back(it.first); } else { - merge_map[bank_id] = {bank_id}; + merge_map[bank_id] = {bank_id}; } + } } + for (auto it: merge_map) { + //cout << "Merge map: " << it.first << ", " << it.second << endl; if (it.second.size() > 1) { cout << "\tGroup: " << it.first << ": " << it.second << endl; cout << "\tPerform bank merging!" << endl; @@ -1148,6 +1463,23 @@ void UBufferImpl::bank_merging(CodegenOptions & options) { } } +//A post processing make sure each banks' port are sorted by its name +void UBufferImpl::sort_bank_port() { + for (auto& it: bank_outpt2readers) { + vector>& outpt2readers = it.second; + sort(outpt2readers.begin(), outpt2readers.end(), + [](std::set& l, std::set& r) + { return pick(l) < pick(r); }); + } + + for (auto& it: bank_inpt2writers) { + vector>& in2writers = it.second; + sort(in2writers.begin(), in2writers.end(), + [](std::set& l, std::set& r) + { return pick(l) < pick(r); }); + } +} + #ifdef COREIR //helper function to get schedule for port @@ -1189,7 +1521,8 @@ UBuffer UBuffer::generate_ubuffer(UBufferImpl& impl, schedule_info & info, int b auto inpts = impl.get_unique_inpts(bank); auto outpts = impl.get_unique_outpts(bank); cout <<"impl inputs: "<< inpts << endl; - cout <<"impl outpts: "<< inpts << endl; + cout <<"impl outpts: "<< outpts << endl; + cout << "rddom: " << str(rddom) << endl; //TODO: may need a sort //add a sort of output make sure we have positive stride when coalesce @@ -1208,7 +1541,7 @@ UBuffer UBuffer::generate_ubuffer(UBufferImpl& impl, schedule_info & info, int b auto acc_map = to_map(access_map.at(inpt)); //get the bank specific access map - acc_map = coalesce(its_range(acc_map, rddom)); + acc_map = simplify(coalesce(its_range(acc_map, rddom))); auto dom = ::domain(acc_map); @@ -1224,7 +1557,8 @@ UBuffer UBuffer::generate_ubuffer(UBufferImpl& impl, schedule_info & info, int b //buf.port_bundles[get_bundle(inpt)].push_back(pt_name); //Put into separate bundle if we have different domain name - buf.port_bundles[::name(dom) + "_write"].push_back(inpt); + buf.port_bundles[inpt + "_write"].push_back(inpt); + //buf.port_bundles[::name(dom)+ "_write"].push_back(inpt); if (impl.is_shift_register_input(inpt)) { //rewrite for shift register //TODO pass codegenoptions @@ -1246,7 +1580,7 @@ UBuffer UBuffer::generate_ubuffer(UBufferImpl& impl, schedule_info & info, int b for (string outpt: outpts) { auto acc_map = to_map(access_map.at(outpt)); //get the bank specific access map - acc_map = coalesce(its_range(acc_map, rddom)); + acc_map = simplify(coalesce(its_range(acc_map, rddom))); auto sched = schedule.at(outpt); acc_map = set_range_name(acc_map, bname); @@ -1261,6 +1595,7 @@ UBuffer UBuffer::generate_ubuffer(UBufferImpl& impl, schedule_info & info, int b //string pt_name = bname + "_" + ::name(dom) + "_" + to_string(usuffix); if (impl.is_shift_register_output(outpt)) { + cout << impl << endl; int delay = impl.shift_registered_outputs.at(outpt).second;; string inpt = impl.shift_registered_outputs.at(outpt).first; @@ -1293,12 +1628,14 @@ UBuffer UBuffer::generate_ubuffer(UBufferImpl& impl, schedule_info & info, int b //buf.port_bundles[get_bundle(outpt)].push_back(pt_name); //Put into separate bundle if we have different domain name - buf.port_bundles[::name(dom) + "_read"].push_back(outpt); + buf.port_bundles[outpt + "_read"].push_back(outpt); + //buf.port_bundles[::name(dom)+ "_read"].push_back(outpt); buf.add_out_pt(outpt, dom, acc_map, its(sched, dom)); } usuffix ++; } + cout << buf << endl; buf.simplify_address_space(); if (sr) { @@ -1324,7 +1661,7 @@ void UBuffer::generate_coreir(CodegenOptions& options, CoreIR::ModuleDef* def, s } void UBuffer::generate_coreir_without_ctrl(CodegenOptions& options, UBufferImpl& impl, CoreIR::ModuleDef* def, schedule_info & info) { - generate_coreir(options, impl, def, info, false); + generate_coreir_refactor(options, impl, def, info, false); } vector get_multi_bank_domain_set(isl_map* origin_map, int project_out_domain) { @@ -1724,6 +2061,7 @@ void add_lake_config(Json& jdata, ConfigMap data, int dimensionality, string dom ConfigMap generate_addressor_config_from_access_map(umap* acc_map, LakeCollateral mem, bool is_read) { string buf_name = range_name(to_map(acc_map)); string micro_buf_name = get_micro_buf_name(buf_name); + cout << "\tMicro buf name: " << micro_buf_name << endl; int word_width = mem.word_width.at(micro_buf_name); int capacity = mem.capacity.at(micro_buf_name); int port_width; @@ -1836,14 +2174,14 @@ Json UBuffer::generate_ubuf_args(CodegenOptions& options, map & op2sched[op_name] = its(sched_remove_dom, dom); } } - } //Go through all the ops and produce the read and write for (auto it: op2sched) { string op_name = it.first; auto sched = op2sched.at(op_name); - cout << "\tSched: " << str(sched) << endl; + cout << "\top name: " << op_name << endl; + cout << "\tSched: " << str(sched) << endl << endl; string ctrl_name = get_ctrl_name(op_name); //Check if we have loop iteration larger than hardware limit, @@ -1893,6 +2231,19 @@ Json UBuffer::generate_ubuf_args(CodegenOptions& options, map & return ret; } + +//Helper function to optimize the pond dimension +pair pad_domain( isl_map* sched, isl_map* acc) { + map dim2pad = get_all_domain_pad_dims(sched, acc); + for (auto it: dim2pad) { + int dim = it.first; + int pad_depth = it.second; + sched = pad_to_domain_ubuf_map(sched, dim, pad_depth); + acc = pad_to_domain_ubuf_map(acc, dim, pad_depth); + } + return {sched, acc}; +} + //Simplify the single fetch width memory codegen Json UBuffer::generate_ubuf_args(CodegenOptions& options, UBuffer& ubuf, string mem_name) { @@ -1934,6 +2285,7 @@ Json UBuffer::generate_ubuf_args(CodegenOptions& options, UBuffer& ubuf, string int word_width = mem.word_width.at(mem_name); int capacity = mem.capacity.at(mem_name); int in_cnt = 0, out_cnt = 0; + string ctrl_name = pick(mem.controller_name); for (auto op_name: ops) { auto sched = op2sched.at(op_name); if(op2write_map.count(op_name)) { @@ -1949,7 +2301,8 @@ Json UBuffer::generate_ubuf_args(CodegenOptions& options, UBuffer& ubuf, string cout << tab(2) << "1d acc map: " << str(linear_acc_map) << endl; //add a simplify optimization pass, //reutrn: pair(schedulem access_map) - auto m_pair = merge_dom_dim(sched, to_map(linear_acc_map)); + auto pad_pair = pad_domain(sched, to_map(linear_acc_map)); + auto m_pair = merge_dom_dim(pad_pair.first, pad_pair.second); auto new_sched = m_pair.first; cout << tab(1) << "After Merge: " << endl; cout << tab(2) << "schedule: " << str(new_sched) << endl; @@ -1963,7 +2316,7 @@ Json UBuffer::generate_ubuf_args(CodegenOptions& options, UBuffer& ubuf, string //get_aff(to_map(linear_acc_map)), false, false, word_width, capacity, port_width); config_info.merge(addressor); cout << "\tWrite map: " << str(acc_map) << endl; - add_lake_config(ret, config_info, num_in_dims(aff), "in2"+mem_name +"_" + str(in_cnt)); + add_lake_config(ret, config_info, num_in_dims(aff), "in2"+ctrl_name+"_" + str(in_cnt)); in_cnt ++; } if(op2read_map.count(op_name)) { @@ -1976,7 +2329,8 @@ Json UBuffer::generate_ubuf_args(CodegenOptions& options, UBuffer& ubuf, string cout << tab(2) << "acc map: " << str(acc_map) << endl; cout << tab(2) << "sched: " << str(sched) << endl; cout << tab(2) << "reduce_map: " << str(reduce_map) << endl; - auto m_pair = merge_dom_dim(sched, to_map(linear_acc_map)); + auto pad_pair = pad_domain(sched, to_map(linear_acc_map)); + auto m_pair = merge_dom_dim(pad_pair.first, pad_pair.second); auto new_sched = m_pair.first; cout << tab(1) << "After Merge: " << endl; cout << tab(2) << "schedule: " << str(new_sched) << endl; @@ -1990,7 +2344,7 @@ Json UBuffer::generate_ubuf_args(CodegenOptions& options, UBuffer& ubuf, string //get_aff(linear_acc_map), true, false, word_width, capacity, port_width); config_info.merge(addressor); cout << "\tRead map: " << str(acc_map) << endl; - add_lake_config(ret, config_info, num_in_dims(aff), mem_name +"2out_" + str(out_cnt)); + add_lake_config(ret, config_info, num_in_dims(aff), ctrl_name+"2out_" + str(out_cnt)); out_cnt ++; } } @@ -2218,6 +2572,49 @@ Json UBuffer::generate_ubuf_args_old(CodegenOptions& options, mapgetContext(); + CoreIR::Instance* buf; + CoreIR::Values genargs = { + {"width", CoreIR::Const::make(context, 16)}, + {"num_inputs", CoreIR::Const::make(context, input_num)}, + {"num_outputs", CoreIR::Const::make(context, output_num)}, + {"ID", CoreIR::Const::make(context, context->getUnique())}, + }; + cout << "Add pond node with input_num = " << input_num + << ", output_num = " << output_num << endl; + auto* g = context->getGenerator("cgralib.Pond_amber"); + //auto* generatedModule = g->getModule(genargs); + //g->getMetaData()["verilog_name"] = + // "pond_"+genargs.at("ID")->get(); + buf = def->addInstance(ub_ins_name, "cgralib.Pond_amber", genargs); + buf->getMetaData()["config"] = config_file; + buf->getMetaData()["mode"] = config_mode; + //buf->getModuleRef()->getMetaData()["verilog_name"] = "pond_"+genargs.at("ID")->get(); + //buf->getMetaData()["verilog_name"] = "pond_"+genargs.at("ID")->get(); + + auto clk_en_const = def->addInstance(ub_ins_name+"_clk_en_const", "corebit.const", + {{"value", CoreIR::Const::make(context, true)}}); + + //garnet wire reset to flush of memory + def->connect(buf->sel("flush"), def->sel("self." + rst_name)); + //def->connect(buf->sel("flush"), def->sel("self.flush")); + //def->connect(buf->sel("rst_n"), def->sel("self.rst_n")); + def->connect(buf->sel("clk"), def->sel("self.clk")); + def->connect(buf->sel("clk_en"), clk_en_const->sel("out")); + def->connect(buf->sel("rst_n"), clk_en_const->sel("out")); + + return buf; +} + CoreIR::Module* affine_controller_use_lake_tile_counter( CodegenOptions& options, CoreIR::Context* context, @@ -2282,99 +2679,132 @@ CoreIR::Module* affine_controller_use_lake_tile_counter( add_lake_config(config_file, stencil_valid, num_in_dims(aff), "stencil_valid"); } - //generate tb accessor - auto config_tb2out = generate_accessor_config_from_aff_expr(dom, aff); auto mem = options.mem_hierarchy.at("mem"); //generate tb address auto index_addr = project_all_out_but(cpy(addr), dim); cout << "Index address: " << str(index_addr) << endl; - { - int word_width = mem.word_width.at("tb"); - int capacity = mem.capacity.at("tb"); - int port_width = mem.out_port_width.at("tb"); - //is_read = true, is_mux = false - auto addressor_tb2out = generate_addressor_config_from_aff_expr(get_aff(index_addr), true, false, word_width, capacity, port_width); - config_tb2out.merge(addressor_tb2out); - } - add_lake_config(config_file, config_tb2out, num_dims(dom), "tb2out_0"); - //generate sram2tb controller - //TODO: change 4 to fetch width - auto trans = get_domain_trans(dom, dim, 4); - cout << "Vectorization Trans: " << str(trans) << endl; + if (mem.fetch_width > 1) { + //generate tb accessor + auto config_tb2out = generate_accessor_config_from_aff_expr(dom, aff); + { + int word_width = mem.word_width.at("tb"); + int capacity = mem.capacity.at("tb"); + int port_width = mem.out_port_width.at("tb"); + //is_read = true, is_mux = false + auto addressor_tb2out = generate_addressor_config_from_aff_expr(get_aff(index_addr), true, false, word_width, capacity, port_width); + config_tb2out.merge(addressor_tb2out); + } + add_lake_config(config_file, config_tb2out, num_dims(dom), "tb2out_0"); - //Apply the vectorization trans on both accessor and addressor - auto acc_0 = its(to_map(aff), dom); - auto res = dot(trans, acc_0); - auto vec_index_addr = dot(trans, index_addr); + //generate sram2tb controller + //TODO: change 4 to fetch width + auto trans = get_domain_trans(dom, dim, 4); + cout << "Vectorization Trans: " << str(trans) << endl; - //project all the inner dim - for (int reset_dim = dim+1; reset_dim < num_in_dims(acc_0); reset_dim ++) { - res = reset_domain_coeff(res, reset_dim, 0); - cout << "\treset: " << str(res) << endl; - } + //Apply the vectorization trans on both accessor and addressor + auto acc_0 = its(to_map(aff), dom); + auto res = dot(trans, acc_0); + auto vec_index_addr = dot(trans, index_addr); - if (dim < num_in_dims(acc_0) - 1) { - vec_index_addr = isl_map_project_out(cpy(vec_index_addr), isl_dim_in, dim+1, num_in_dims(acc_0) - dim - 1); - res = isl_map_project_out(cpy(res), isl_dim_in, dim+1, num_in_dims(acc_0) - dim - 1); - } - cout << "\tAfter trans: " << str(res) << endl; - cout << "\tVec index address: " << str(vec_index_addr) << endl; + //project all the inner dim + for (int reset_dim = dim+1; reset_dim < num_in_dims(acc_0); reset_dim ++) { + res = reset_domain_coeff(res, reset_dim, 0); + cout << "\treset: " << str(res) << endl; + } - //bring the sram2tb forward for 3 cycle - res = shift_range_map(res, {-3}); - auto config_sram2tb = generate_accessor_config_from_aff_expr(domain(res), get_aff(res)); + if (dim < num_in_dims(acc_0) - 1) { + vec_index_addr = isl_map_project_out(cpy(vec_index_addr), isl_dim_in, dim+1, num_in_dims(acc_0) - dim - 1); + res = isl_map_project_out(cpy(res), isl_dim_in, dim+1, num_in_dims(acc_0) - dim - 1); + } + cout << "\tAfter trans: " << str(res) << endl; + cout << "\tVec index address: " << str(vec_index_addr) << endl; - //Getthe addressor - { - int word_width = mem.word_width.at("tb"); - int capacity = mem.capacity.at("tb"); - int port_width = mem.in_port_width.at("tb"); - auto addressor_sram2tb_write = generate_addressor_config_from_aff_expr(get_aff(vec_index_addr), false, false, word_width, capacity, port_width); - config_sram2tb.merge(addressor_sram2tb_write); - } + //bring the sram2tb forward for 3 cycle + res = shift_range_map(res, {-3}); + auto config_sram2tb = generate_accessor_config_from_aff_expr(domain(res), get_aff(res)); - { - int word_width = mem.word_width.at("sram"); - int capacity = mem.capacity.at("sram"); - int port_width = mem.out_port_width.at("sram"); - auto addressor_sram2tb_read = generate_addressor_config_from_aff_expr(get_aff(vec_index_addr), true, false, word_width, capacity, port_width); - config_sram2tb.merge(addressor_sram2tb_read); - } - add_lake_config(config_file, config_sram2tb, num_dims(domain(res)), "sram2tb_0"); + //Getthe addressor + { + int word_width = mem.word_width.at("tb"); + int capacity = mem.capacity.at("tb"); + int port_width = mem.in_port_width.at("tb"); + auto addressor_sram2tb_write = generate_addressor_config_from_aff_expr(get_aff(vec_index_addr), false, false, word_width, capacity, port_width); + config_sram2tb.merge(addressor_sram2tb_write); + } - auto* g = context->getGenerator("cgralib.Mem_amber"); - //auto* generatedModule = g->getModule(genargs); - //g->getMetaData()["verilog_name"] = - // "aff_ctrl_"+genargs.at("ID")->get(); - buf = def->addInstance(ub_ins_name + "_Counter_" + str(dim), "cgralib.Mem_amber", genargs); - //assign the init value - //TODO change 4 to fetch width - std::vector v(round_up_to_multiple_of(get_domain_range(dom, dim), 4)); - std::iota(v.begin(), v.end(), 0); + { + int word_width = mem.word_width.at("sram"); + int capacity = mem.capacity.at("sram"); + int port_width = mem.out_port_width.at("sram"); + auto addressor_sram2tb_read = generate_addressor_config_from_aff_expr(get_aff(vec_index_addr), true, false, word_width, capacity, port_width); + config_sram2tb.merge(addressor_sram2tb_read); + } + add_lake_config(config_file, config_sram2tb, num_dims(domain(res)), "sram2tb_0"); + + auto* g = context->getGenerator("cgralib.Mem_amber"); + //auto* generatedModule = g->getModule(genargs); + //g->getMetaData()["verilog_name"] = + // "aff_ctrl_"+genargs.at("ID")->get(); + buf = def->addInstance(ub_ins_name + "_Counter_" + str(dim), "cgralib.Mem_amber", genargs); + //assign the init value + //TODO change 4 to fetch width + std::vector v(round_up_to_multiple_of(get_domain_range(dom, dim), 4)); + std::iota(v.begin(), v.end(), 0); + + //TODO: this is a temporary fix for lake counter, need to move to the root level + //buf->getMetaData()["init"] = v; + config_file["init"] = v; + + buf->getMetaData()["config"] = config_file; + buf->getMetaData()["mode"] = "lake"; + //buf->getModuleRef()->getMetaData()["verilog_name"] = "aff_ctrl_"+genargs.at("ID")->get(); + //buf->getMetaData()["verilog_name"] = "aff_ctrl_"+genargs.at("ID")->get(); + + + //garnet wire reset to flush of memory + def->connect(buf->sel("flush"), def->sel("self.rst_n")); + def->connect(buf->sel("clk"), def->sel("self.clk")); + def->connect(buf->sel("clk_en"), clk_en_const->sel("out")); + def->connect(buf->sel("rst_n"), clk_en_const->sel("out")); + def->connect(buf->sel("data_out_0"), def->sel("self")->sel("d")->sel(dim)); + if (has_stencil_valid) { + def->connect(buf->sel("stencil_valid"), def->sel("self.valid")); + } + generate_lake_tile_verilog(options, buf); - //TODO: this is a temporary fix for lake counter, need to move to the root level - //buf->getMetaData()["init"] = v; - config_file["init"] = v; + } else { + //This is the dual port version + auto config_mem2out = generate_accessor_config_from_aff_expr(dom, aff); + { + int word_width = mem.word_width.at("mem"); + int capacity = mem.capacity.at("mem"); + int port_width = mem.out_port_width.at("mem"); + //is_read = true, is_mux = false + auto addressor_mem2out = generate_addressor_config_from_aff_expr(get_aff(index_addr), true, false, word_width, capacity, port_width); + config_mem2out.merge(addressor_mem2out); + } + add_lake_config(config_file, config_mem2out, num_dims(dom), pick(mem.controller_name)+"2out_0"); - buf->getMetaData()["config"] = config_file; - buf->getMetaData()["mode"] = "lake"; - //buf->getModuleRef()->getMetaData()["verilog_name"] = "aff_ctrl_"+genargs.at("ID")->get(); - buf->getMetaData()["verilog_name"] = "aff_ctrl_"+genargs.at("ID")->get(); + std::vector v(get_domain_range(dom, dim)); + std::iota(v.begin(), v.end(), 0); + //TODO: this is a temporary fix for lake counter, need to move to the root level + //buf->getMetaData()["init"] = v; + config_file["init"] = v; + auto dp_buf_for_counter = generate_pond_instance(def, options, ub_ins_name + "_counter_" + str(dim), + "rst_n", "lake_dp", config_file, 1, 1); + + //Wire the output data + def->connect(dp_buf_for_counter->sel("data_out_pond_0"), def->sel("self")->sel("d")->sel(dim)); + generate_lake_tile_verilog(options, dp_buf_for_counter); + if (has_stencil_valid) { + def->connect(dp_buf_for_counter->sel("valid_out_pond"), def->sel("self.valid")); + } - //garnet wire reset to flush of memory - def->connect(buf->sel("flush"), def->sel("self.rst_n")); - def->connect(buf->sel("clk"), def->sel("self.clk")); - def->connect(buf->sel("clk_en"), clk_en_const->sel("out")); - def->connect(buf->sel("rst_n"), clk_en_const->sel("out")); - def->connect(buf->sel("data_out_0"), def->sel("self")->sel("d")->sel(dim)); - if (has_stencil_valid) { - def->connect(buf->sel("stencil_valid"), def->sel("self.valid")); } - generate_lake_tile_verilog(options, buf); } m->setDef(def); @@ -2407,40 +2837,60 @@ CoreIR::Instance* affine_controller_use_lake_tile( isl_aff* aff, string ub_ins_name) { - CoreIR::Instance* buf; - bool has_chain_en = options.mem_hierarchy.at("mem").wire_chain_en; - CoreIR::Values genargs = { - {"width", CoreIR::Const::make(context, 16)}, - {"num_inputs", CoreIR::Const::make(context, 0)}, - {"num_outputs", CoreIR::Const::make(context, 0)}, - {"has_stencil_valid", CoreIR::Const::make(context, true)}, - {"has_chain_en", CoreIR::Const::make(context, has_chain_en)}, - {"ID", CoreIR::Const::make(context, context->getUnique())}, - {"has_flush", CoreIR::Const::make(context, true)}, - {"use_prebuilt_mem", CoreIR::Const::make(context, true)} - }; + cout << "Add ub node to be aff ctrl" << endl; + + //Generate the configuration auto stencil_valid = generate_accessor_config_from_aff_expr(dom, aff); - //FIXME:possible bug if one ubuffer contains more than one tile json config_file; add_lake_config(config_file, stencil_valid, num_in_dims(aff), "stencil_valid"); - cout << "Add ub node to be aff ctrl" << endl; - auto* g = context->getGenerator("cgralib.Mem_amber"); - //auto* generatedModule = g->getModule(genargs); - // "aff_ctrl_counter_"+genargs.at("ID")->get(); - buf = def->addInstance(ub_ins_name, "cgralib.Mem_amber", genargs); - buf->getMetaData()["config"] = config_file; - buf->getMetaData()["mode"] = "lake"; - //buf->getModuleRef()->getMetaData()["verilog_name"] = "aff_ctrl_counter_"+genargs.at("ID")->get(); - buf->getMetaData()["verilog_name"] = "aff_ctrl_counter_"+genargs.at("ID")->get(); + CoreIR::Instance* buf; + auto mem = options.mem_hierarchy.at("mem"); + if (mem.fetch_width > 1) { + //TODO: put this into a function + bool has_chain_en = options.mem_hierarchy.at("mem").wire_chain_en; + CoreIR::Values genargs = { + {"width", CoreIR::Const::make(context, 16)}, + {"num_inputs", CoreIR::Const::make(context, 1)}, + {"num_outputs", CoreIR::Const::make(context, 1)}, + {"has_stencil_valid", CoreIR::Const::make(context, true)}, + {"has_chain_en", CoreIR::Const::make(context, has_chain_en)}, + {"ID", CoreIR::Const::make(context, context->getUnique())}, + {"has_flush", CoreIR::Const::make(context, true)}, + {"use_prebuilt_mem", CoreIR::Const::make(context, true)} + }; + auto* g = context->getGenerator("cgralib.Mem_amber"); + buf = def->addInstance(ub_ins_name, "cgralib.Mem_amber", genargs); + buf->getMetaData()["config"] = config_file; + buf->getMetaData()["mode"] = "lake"; + //buf->getModuleRef()->getMetaData()["verilog_name"] = "aff_ctrl_counter_"+genargs.at("ID")->get(); + //buf->getMetaData()["verilog_name"] = "aff_ctrl_counter_"+genargs.at("ID")->get(); + + } else { + CoreIR::Values genargs = { + {"width", CoreIR::Const::make(context, 16)}, + {"num_inputs", CoreIR::Const::make(context, 1)}, + {"num_outputs", CoreIR::Const::make(context, 1)}, + {"ID", CoreIR::Const::make(context, context->getUnique())}, + }; + auto* g = context->getGenerator("cgralib.Pond_amber"); + //auto* generatedModule = g->getModule(genargs); + //g->getMetaData()["verilog_name"] = + // "pond_"+genargs.at("ID")->get(); + buf = def->addInstance(ub_ins_name, "cgralib.Pond_amber", genargs); + buf->getMetaData()["config"] = config_file; + buf->getMetaData()["mode"] = "lake_dp"; + //buf->getModuleRef()->getMetaData()["verilog_name"] = "pond_"+genargs.at("ID")->get(); + //buf->getMetaData()["verilog_name"] = "pond_"+genargs.at("ID")->get(); + + } + auto clk_en_const = def->addInstance(ub_ins_name+"_clk_en_const", "corebit.const", {{"value", CoreIR::Const::make(context, true)}}); - //garnet wire reset to flush of memory + //Wire some default logic def->connect(buf->sel("flush"), def->sel("self.reset")); - //def->connect(buf->sel("flush"), def->sel("self.flush")); - //def->connect(buf->sel("rst_n"), def->sel("self.rst_n")); def->connect(buf->sel("clk"), def->sel("self.clk")); def->connect(buf->sel("clk_en"), clk_en_const->sel("out")); def->connect(buf->sel("rst_n"), clk_en_const->sel("out")); @@ -2448,10 +2898,12 @@ CoreIR::Instance* affine_controller_use_lake_tile( return buf; } +//TODO: we should rewrite this function to include both dp memory and sp memory CoreIR::Instance* UBuffer::generate_pond_instance( ModuleDef* def, CodegenOptions options, string ub_ins_name, + string config_mode, size_t input_num, size_t output_num) { auto context = def->getContext(); @@ -2470,9 +2922,9 @@ CoreIR::Instance* UBuffer::generate_pond_instance( // "pond_"+genargs.at("ID")->get(); buf = def->addInstance(ub_ins_name, "cgralib.Pond_amber", genargs); buf->getMetaData()["config"] = config_file; - buf->getMetaData()["mode"] = "pond"; + buf->getMetaData()["mode"] = config_mode; //buf->getModuleRef()->getMetaData()["verilog_name"] = "pond_"+genargs.at("ID")->get(); - buf->getMetaData()["verilog_name"] = "pond_"+genargs.at("ID")->get(); + //buf->getMetaData()["verilog_name"] = "pond_"+genargs.at("ID")->get(); auto clk_en_const = def->addInstance(ub_ins_name+"_clk_en_const", "corebit.const", {{"value", CoreIR::Const::make(context, true)}}); @@ -2515,7 +2967,7 @@ CoreIR::Instance* UBuffer::generate_lake_tile_instance( cout << "Generate stencil valid signal" << endl; generate_stencil_valid_config(options, bank_name); } - cout << "Add ub node with input_num = " << input_num + cout << "Add lake node:" << ub_ins_name << " with input_num = " << input_num << ", output_num = " << output_num << endl; if (options.pass_through_valid) { //modargs["config"] = CoreIR::Const::make(context, config_file); @@ -2527,7 +2979,7 @@ CoreIR::Instance* UBuffer::generate_lake_tile_instance( buf->getMetaData()["config"] = config_file; buf->getMetaData()["mode"] = string("lake"); //buf->getModuleRef()->getMetaData()["verilog_name"] = "lake_"+genargs.at("ID")->get(); - buf->getMetaData()["verilog_name"] = "lake_"+genargs.at("ID")->get(); + //buf->getMetaData()["verilog_name"] = "lake_"+genargs.at("ID")->get(); } else { //TODO: remove cwlib in the future genargs["config"] = CoreIR::Const::make(context, config_file); @@ -2569,9 +3021,9 @@ void UBuffer::generate_stencil_valid_config(CodegenOptions& options, string bank } string memDatainPort(string mode, int pt_cnt) { - if (mode == "lake" || mode == "glb") + if (mode == "lake" || mode == "glb") return "data_in_" + to_string(pt_cnt); - else if (mode == "pond") { + else if (mode == "pond" || mode == "lake_dp") { return "data_in_pond_" + to_string(pt_cnt); } else { cout << "Mode: " << mode << " is not implemented yet" << endl; @@ -2582,7 +3034,7 @@ string memDatainPort(string mode, int pt_cnt) { string memDataoutPort(string mode, int pt_cnt) { if (mode == "lake" || mode == "glb") return "data_out_" + to_string(pt_cnt); - else if (mode == "pond") { + else if (mode == "pond" || mode == "lake_dp") { return "data_out_pond_" + to_string(pt_cnt); } else { cout << "Mode: " << mode << " is not implemented yet" << endl; @@ -2593,6 +3045,7 @@ string memDataoutPort(string mode, int pt_cnt) { //Helper function to find the last port in chaining path CoreIR::Wireable* findChainDataIn(CoreIR::Wireable* mem_data_out, int port_id) { auto last_bank = mem_data_out->getTopParent(); + cout << "Last bank in chain data in" << last_bank->toString() << endl; auto chain_in = last_bank->sel("chain_data_in_" + str(port_id)); auto conns = getConnectWires(chain_in); if (conns.size() == 0) { @@ -2654,12 +3107,13 @@ void UBuffer::wire_ubuf_IO(CodegenOptions& options,CoreIR::ModuleDef* def, mapconnect(buf->sel(memDataoutPort(config_mode, outpt_cnt)), pt2wire.at(outpt)); } else { assert(conns.size() == 1); + cout << "pt count: " << outpt_cnt << endl; CoreIR::Wireable* last_dangling_chain_data_in = findChainDataIn(pick(conns), outpt_cnt); def->connect(buf->sel(memDataoutPort(config_mode, outpt_cnt)), last_dangling_chain_data_in); } - } else if (config_mode == "pond") { + } else if (config_mode == "pond" || config_mode == "lake_dp") { if (bank_id == impl.outpt_to_bank.at(outpt).size() - 1) { //last port directly connec to the wire def->connect(buf->sel(memDataoutPort(config_mode, outpt_cnt)), pt2wire.at(outpt)); @@ -2682,7 +3136,7 @@ void UBuffer::wire_ubuf_IO(CodegenOptions& options,CoreIR::ModuleDef* def, mapport_widths)}}); def->connect(dataout_pth->sel("out"), next_val->sel("out")); def->connect(buf->sel(memDataoutPort(config_mode, outpt_cnt)), next_val->sel("in1")); - def->connect(mux_ctrl->sel("stencil_valid"), next_val->sel("sel")); + def->connect(op_control_wires(mux_ctrl), next_val->sel("sel")); inlineInstance(dataout_pth); pt2wire.at(outpt) = next_val->sel("in0"); } @@ -2741,10 +3195,17 @@ void UBuffer::generate_sreg_and_wire(CodegenOptions& options, UBufferImpl& impl, last_out = wire; else { auto conns = getConnectWires(wire); + //cout << "src: " << src << endl; + //for (auto conn: conns) { + // cout << conn->toString() << endl; + //} assert(conns.size() == 1); last_out = pick(conns); } - CoreIR::Wireable* final_out = pt2wire.at(dst); + //CoreIR::Wireable* final_out = pt2wire.at(dst); + + //cout << *this << endl; + CoreIR::Wireable* final_out = def->sel("self." + container_bundle(dst) + "." + str(bundle_offset(dst))); for (size_t i = 0; i < delay; i ++) { auto reg = def->addInstance("d_reg_"+context->getUnique(), "mantle.reg", {{"width", CoreIR::Const::make(context, port_widths)}, @@ -2756,6 +3217,54 @@ void UBuffer::generate_sreg_and_wire(CodegenOptions& options, UBufferImpl& impl, } } +//Take the fanin structure and generate the wiring +void UBuffer::generate_fanin_connection(CodegenOptions& options, UBufferImpl& impl, CoreIR::ModuleDef* def, map & pt2wire){ + auto context = def->getContext(); + for (auto it: impl.fanin_outputs) { + map output_map; + for (auto in_delay: it.second) { + string src = in_delay.first; + int delay = in_delay.second; + CoreIR::Wireable* last_out = + pt2wire.at(src); + for (size_t i = 0; i < delay; i ++) { + auto reg = def->addInstance("d_reg_"+context->getUnique(), "mantle.reg", + {{"width", CoreIR::Const::make(context, port_widths)}, + {"has_en", CoreIR::Const::make(context, false)}}); + def->connect(reg->sel("in"), last_out); + last_out = reg->sel("out"); + } + output_map[src] = last_out; + } + string outpt = it.first; + + auto mux_output = pt2wire.at(outpt); + for (auto src: output_map) { + + //Add a pass through for the mux output + Instance* dataout_pth = addPassthrough( + mux_output, "dataout_pt_" + context->getUnique()); + //Creating the input selection logic + isl_aff* sched_aff = get_aff(to_map(schedule.at(src.first))); + cout << "pt schedule: " << str(sched_aff) << endl; + auto mux_ctrl = affine_controller_use_lake_tile( + options, def, context, domain.at(src.first), + sched_aff, "dataout_pt_mux_ctrl_" + context->getUnique()); + generate_lake_tile_verilog(options, mux_ctrl); + //create a mux + auto next_val = def->addInstance( + def->getContext()->getUnique() + "_mux", + "coreir.mux", + {{"width", CoreIR::Const::make(context, this->port_widths)}}); + def->connect(dataout_pth->sel("out"), next_val->sel("out")); + def->connect(src.second, next_val->sel("in1")); + def->connect(op_control_wires(mux_ctrl), next_val->sel("sel")); + inlineInstance(dataout_pth); + mux_output = next_val->sel("in0"); + } + } +} + string UBuffer::determine_config_mode(CodegenOptions& options, UBuffer& target_buf) { auto capacity = total_capacity(target_buf); @@ -2766,42 +3275,110 @@ string UBuffer::determine_config_mode(CodegenOptions& options, UBuffer& target_b //Changing the size of pond threshold if (contains(target_buf.name, "_glb_stencil")) { config_mode = "glb"; - } else if (capacity <= 96 && multi_level_mem ) { + } else if (capacity <= 32 && multi_level_mem ) { cout << "Generate config for register file!" << endl; config_mode = "pond"; + + } else if (options.mem_hierarchy.at("mem").fetch_width == 1) { + config_mode = "lake_dp"; } else { config_mode = "lake"; } return config_mode; } -CoreIR::Instance* UBuffer::map_ubuffer_to_cgra(CodegenOptions& options, CoreIR::ModuleDef* def, UBuffer& target_buf, string config_mode) { - - map vectorized_buf; +CoreIR::Instance* UBuffer::map_ubuffer_to_cgra(CodegenOptions& options, CoreIR::ModuleDef* def, GarnetImpl& hw_impl) { + UBuffer target_buf = hw_impl.target_buf; string ub_ins_name = "ub_" + target_buf.name; - vectorized_buf.insert( - {target_buf.name+ "_ubuf", target_buf}); - auto capacity = total_capacity(target_buf); - - cout << "Vectorization buffer capacity: " << capacity << endl; - bool multi_level_mem = options.mem_hierarchy.count("regfile"); - /*if (capacity <= 32 && multi_level_mem ) { - cout << "Generate config for register file!" << endl; + CoreIR::Instance* buf; + if (hw_impl.config_mode == "lake") { + //auto vectorized_buf = hw_impl.sub_component; + //for (auto buf: vectorized_buf) { + // cout << "After vectorization codegen: " << buf.first << endl << buf.second << endl; + //} //TODO generate the config file on the fly + assert(hw_impl.sub_component.size()); + config_file = generate_ubuf_args(options, hw_impl.sub_component); + buf = generate_lake_tile_instance(def, options, + ub_ins_name, target_buf.name, + target_buf.num_in_ports(), + target_buf.num_out_ports(), + false/*TODO: exclude stencil valid signal*/, true); + + } else if (hw_impl.config_mode == "lake_dp") { + config_file = generate_ubuf_args(options, target_buf, "mem"); + buf = generate_pond_instance(def, options, ub_ins_name, "lake_dp", + target_buf.num_in_ports(), target_buf.num_out_ports()); + } else if (hw_impl.config_mode == "pond") { config_file = generate_ubuf_args(options, target_buf, "regfile"); - config_mode = "pond"; - } else { - //buffer_vectorization(options.iis, bk.name + "_ubuf", 1, 4, rewrite_buffer); - cout << "vectorization buf name: " << target_buf.name << endl; - buffer_vectorization(options, {target_buf.name+ "_ubuf"}, vectorized_buf); - vectorized_buf = decouple_multi_tile_ubuffer(options, vectorized_buf); - for (auto buf: vectorized_buf) { - cout << "After vectorization codegen: " << buf.first << endl << buf.second << endl; + buf = generate_pond_instance(def, options, ub_ins_name, "pond", + target_buf.num_in_ports(), target_buf.num_out_ports()); + } else if (hw_impl.config_mode == "glb") { + + //TODO: put this info a function + auto c = def->getContext(); + config_file = generate_ubuf_args(options, target_buf, "glb"); + Values tile_params{ + {"width", COREMK(c, 16)}, + {"ctrl_width", COREMK(c, 32)}, + {"ID", COREMK(c, target_buf.name)}, + {"has_external_addrgen", COREMK(c, true)}, + {"num_inputs",COREMK(c,target_buf.num_in_ports())}, + {"num_outputs",COREMK(c,target_buf.num_out_ports())}}; + + buf = def->addInstance( + target_buf.name + "_ubuf", + "cgralib.Mem_amber", tile_params); + buf->getMetaData()["mode"] = "glb"; + buf->getMetaData()["config"] = config_file; + //buf->getModuleRef()->getMetaData()["verilog_name"] = "glb_"+ c->getUnique(); + //buf->getMetaData()["verilog_name"] = "glb_"+ c->getUnique(); + int count = 0; + target_buf.remove_bank_dim(); + cout << "After simplify: " << target_buf << endl; + for (auto inpt: target_buf.get_in_ports()) { + isl_set* dom = target_buf.domain.at(inpt); + isl_aff* aff = get_aff(to_map(target_buf.schedule.at(inpt))); + auto accessor = ::affine_controller(def, dom, aff, 32); + accessor->getMetaData()["garnet_remove"] = true; + auto agen = build_addrgen(inpt, target_buf, def, 32); + def->connect(agen->sel("d"), accessor->sel("d")); + def->connect(accessor->sel("rst_n"), def->sel("self.reset")); + def->connect(agen->sel("out"), buf->sel("write_addr_" + str(count))); + def->connect(buf->sel("wen_" + str(count)), + accessor->sel("valid")); + count ++; } - //TODO generate the config file on the fly - config_file = generate_ubuf_args(options, vectorized_buf); - config_mode = "lake"; - }*/ + count = 0; + for (auto outpt: target_buf.get_out_ports()) { + isl_set* dom = target_buf.domain.at(outpt); + isl_aff* aff = get_aff(to_map(target_buf.schedule.at(outpt))); + //read have one cycle latency + aff = add(aff, -1); + auto accessor = ::affine_controller(def, dom, aff, 32); + accessor->getMetaData()["garnet_remove"] = true; + auto agen = build_addrgen(outpt, target_buf, def, 32); + def->connect(agen->sel("d"), accessor->sel("d")); + def->connect(accessor->sel("rst_n"), def->sel("self.reset")); + def->connect(agen->sel("out"), buf->sel("read_addr_" + str(count))); + def->connect(buf->sel("ren_" + str(count)), + accessor->sel("valid")); + count ++; + } + def->connect(buf->sel("rst_n"), def->sel("self.reset")); + } + return buf; +} + +CoreIR::Instance* UBuffer::map_ubuffer_to_cgra(CodegenOptions& options, CoreIR::ModuleDef* def, UBuffer& target_buf, string config_mode) { + + map vectorized_buf; + string ub_ins_name = "ub_" + target_buf.name; + vectorized_buf.insert( + {target_buf.name+ "_ubuf", target_buf}); + auto capacity = total_capacity(target_buf); + + cout << "Vectorization buffer capacity: " << capacity << endl; CoreIR::Instance* buf; if (config_mode == "lake") { cout << "vectorization buf name: " << target_buf.name << endl; @@ -2817,9 +3394,13 @@ CoreIR::Instance* UBuffer::map_ubuffer_to_cgra(CodegenOptions& options, CoreIR:: target_buf.num_in_ports(), target_buf.num_out_ports(), false/*TODO: exclude stencil valid signal*/, true); + } else if (config_mode == "lake_dp") { + config_file = generate_ubuf_args(options, target_buf, "mem"); + buf = generate_pond_instance(def, options, ub_ins_name, "lake_dp", + target_buf.num_in_ports(), target_buf.num_out_ports()); } else if (config_mode == "pond") { config_file = generate_ubuf_args(options, target_buf, "regfile"); - buf = generate_pond_instance(def, options, ub_ins_name, + buf = generate_pond_instance(def, options, ub_ins_name, "pond", target_buf.num_in_ports(), target_buf.num_out_ports()); } else if (config_mode == "glb") { auto c = def->getContext(); @@ -2838,7 +3419,7 @@ CoreIR::Instance* UBuffer::map_ubuffer_to_cgra(CodegenOptions& options, CoreIR:: buf->getMetaData()["mode"] = "glb"; buf->getMetaData()["config"] = config_file; //buf->getModuleRef()->getMetaData()["verilog_name"] = "glb_"+ c->getUnique(); - buf->getMetaData()["verilog_name"] = "glb_"+ c->getUnique(); + //buf->getMetaData()["verilog_name"] = "glb_"+ c->getUnique(); int count = 0; target_buf.remove_bank_dim(); cout << "After simplify: " << target_buf << endl; @@ -2910,7 +3491,7 @@ CoreIR::Instance* generate_cgpl_ctrl(CodegenOptions& options, CoreIR::ModuleDef* return cgpl_ctrl; } -void cgpl_ctrl_optimization(CodegenOptions& options, CoreIR::ModuleDef* def, UBuffer& target_buf, string config_mode, +void cgpl_ctrl_optimization(CodegenOptions& options, UBuffer& target_buf, string config_mode, isl_map*& cgpl_schedule, bool& decouple_ctrl, bool& substract_glb_latency) { string ub_ins_name = "ub_" + target_buf.name; decouple_ctrl = @@ -2926,6 +3507,25 @@ void cgpl_ctrl_optimization(CodegenOptions& options, CoreIR::ModuleDef* def, UBu } } +void cgpl_post_processing(CodegenOptions& options, + CoreIR::ModuleDef* def, CoreIR::Instance*buf, GarnetImpl & hw_impl) { + if (hw_impl.decouple_ctrl) { + CoreIR::Instance* cgpl_ctrl = generate_cgpl_ctrl(options, def, hw_impl.cgpl_schedule); + buf->getMetaData()["drive_by_cgpl_ctrl"] = true; + //Disconnect the original connection from flush port + auto conns = buf->sel("flush")->getConnectedWireables(); + for (auto conn: conns) { + def->disconnect(buf->sel("flush"), conn); + } + //Use lake tile to generate control + if (cgpl_ctrl->getModuleRef()->isGenerated()) + def->connect(cgpl_ctrl->sel("stencil_valid"), buf->sel("flush")); + //Use coreir built affine control + else + def->connect(cgpl_ctrl->sel("valid"), buf->sel("flush")); + } +} + void cgpl_post_processing(CodegenOptions& options, CoreIR::ModuleDef* def, CoreIR::Instance*buf, isl_map* cgpl_schedule, bool decouple_ctrl) { if (decouple_ctrl) { @@ -2986,18 +3586,176 @@ void host2glb_optimization(CodegenOptions& options, } } + +void host2glb_optimization(CodegenOptions& options, + CoreIR::ModuleDef* def, CoreIR::Instance*buf, GarnetImpl& hw_impl) { + if (hw_impl.substract_glb_latency) { + buf->getMetaData()["drive_by_cgpl_ctrl"] = true; + assert(options.host2glb_latency != 0); + int glb_load_latency= options.host2glb_latency; + //Substract all the cycle starting address in configuration + + auto config_file = buf->getMetaData()["config"]; + substract_glb_latency_in_config_file(config_file, glb_load_latency); + buf->getMetaData()["config"] = config_file; + + isl_ctx* ctx = isl_ctx_alloc(); + isl_map* cgpl_sched = isl_map_read_from_str(ctx, ("{op[root=0, i0]->["+str(glb_load_latency-1)+" + i0]: i0=0}").c_str()); + auto sched_aff = get_aff(cgpl_sched); + auto dom = ::domain(cgpl_sched); + + //Add one because we did not wire reset + auto cgpl_ctrl = affine_controller(def, dom, add(sched_aff, 1), 32); + //cgpl_ctrl->getMetaData()["garnet_remove"] = true; + cgpl_ctrl->getMetaData()["garnet_rewire_flush"] = true; + + //Disconnect the original connection from flush port + auto conns = buf->sel("flush")->getConnectedWireables(); + for (auto conn: conns) { + def->disconnect(buf->sel("flush"), conn); + } + //connect the new flush + def->connect(cgpl_ctrl->sel("valid"), buf->sel("flush")); + } +} CoreIR::Instance* UBuffer::generate_accum_reg_instance(CodegenOptions& options, CoreIR::ModuleDef* def) { //Save the config argument in ubuffer data structure config_file = generate_ubuf_args(options, *this, "regfile"); //TODO: check we define pond - auto buf_ins = generate_pond_instance(def, options, "ub_"+name, + auto buf_ins = generate_pond_instance(def, options, "ub_"+name, "pond", num_in_ports(), num_out_ports()); return buf_ins; } -void insert_accumulation_register(CodegenOptions & options, CoreIR::ModuleDef* def, UBuffer & buf, - map & pt2wire, string config_mode) { +void create_accumulation_register_and_rewrite_buf(CodegenOptions & options, UBuffer & buf, GarnetImpl& hw_impl) { + //only evoke this opitimization for lake + if (hw_impl.config_mode != "lake") { + return ; + } + + vector update_ops; + for(auto op: buf.get_ops()) { + if (buf.is_update_op(op)) { + update_ops.push_back(op); + } + } + if (update_ops.size() == 0) { + return ; + } + assert(update_ops.size() == 1); + string op_name = pick(update_ops); + auto am = buf.get_access_map_from_op(op_name); + auto sched = buf.get_schedule_from_op(op_name); + cout << "\tupdate op access map: " << str(am) << endl + << "\tupdate op schedule: " << str(sched) << endl; + vector reaccess_dims = relation_map(am); + int mask_until = reaccess_dims.size(); + for(auto it = reaccess_dims.rbegin(); it < reaccess_dims.rend(); it ++) + if ((*it) ) { + mask_until = (int)(reaccess_dims.rend() - 1 - it) ; + break; + } + cout <<"MASK dim: "<< mask_until << endl; + if (mask_until == reaccess_dims.size() - 1) + return ; + isl_map* mask_map = get_domain_mask(am, mask_until); + auto am_mask = dot(mask_map, am); + auto sched_mask = dot(mask_map, sched); + cout << "\tupdate op access map: " << str(am_mask) << endl + << "\tupdate op schedule: " << str(sched_mask) << endl; + + vector domain_ext = extents(::domain(am)); + cout << domain_ext << endl; + int accum_time = 1; + for(int i = mask_until + 1; i < num_in_dims(am); i ++) { + accum_time *= domain_ext.at(i); + } + + cout << "Accumulation time: " << accum_time << endl; + + //TODO double check this value make sense + auto in_sched_reg = linear_schedule(sched_mask, {1}, -1, false); + auto out_sched_reg = linear_schedule(sched_mask, {1}, accum_time - 1, false); + + //Create the pond reg + UBuffer accum_reg; + accum_reg.name = buf.name + "_accum_reg"; + accum_reg.ctx = buf.ctx; + accum_reg.port_widths = buf.port_widths; + + vector inpts, outpts; + + for(string inpt: buf.get_in_ports()) { + if (::name(buf.domain.at(inpt)) == op_name) { + inpts.push_back(inpt); + string pt_name = inpt + "_accum_in_0"; + auto reg_in_am = add_domain_suffix(am_mask, "_write"); + auto reg_in_sched= add_domain_suffix(in_sched_reg, "_write"); + accum_reg.port_bundles[op_name + "_write_0"].push_back(pt_name); + accum_reg.add_in_pt(pt_name, ::domain(reg_in_am), reg_in_am, reg_in_sched); + + pt_name = inpt + "_accum_in_1"; + reg_in_am = add_domain_suffix(am, "_write_pe"); + reg_in_sched= add_domain_suffix(sched, "_write_pe"); + accum_reg.port_bundles[op_name + "_write_1"].push_back(pt_name); + accum_reg.add_in_pt(pt_name, ::domain(reg_in_am), reg_in_am, reg_in_sched); + } + } + + for(string outpt: buf.get_out_ports()) { + if (::name(buf.domain.at(outpt)) == op_name) { + outpts.push_back(outpt); + //string pt_name = outpt + "_accum_out_0"; + //auto reg_out_am = add_domain_suffix(am_mask, "_read"); + //auto reg_out_sched= add_domain_suffix(out_sched_reg, "_read"); + //accum_reg.port_bundles[op_name + "_read_0"].push_back(pt_name); + //accum_reg.add_out_pt(pt_name, ::domain(reg_out_am), reg_out_am, reg_out_sched); + + auto pt_name = outpt + "_accum_out_1"; + auto reg_out_am = add_domain_suffix(am, "_read_pe"); + auto reg_out_sched= add_domain_suffix(sched, "_read_pe"); + accum_reg.port_bundles[op_name + "_read_1"].push_back(pt_name); + accum_reg.add_out_pt(pt_name, ::domain(reg_out_am), reg_out_am, reg_out_sched); + } + } + assert(inpts.size()==1); + buf.replace_pt(pick(inpts), simplify(am_mask), simplify(out_sched_reg)); + assert(outpts.size()==1); + buf.replace_pt(pick(outpts), simplify(am_mask), simplify(in_sched_reg)); + cout <<"\tFinal accum register: \n" << accum_reg << endl; + cout << "\tbuffer after accumu reg insert: \n" << buf << endl; + + //save the impl information + hw_impl.reduce_PE_inpt = pick(inpts); + hw_impl.reduce_PE_outpt = pick(outpts); + hw_impl.accum_reg = accum_reg; + hw_impl.insert_shift_register = true; +} + +void insert_accumulation_register(CodegenOptions& options, CoreIR::ModuleDef* def, GarnetImpl & hw_impl, map & pt2wire) { + + if (!hw_impl.insert_shift_register) + return; + + //Check if we get the ubuffer instance + UBuffer accum_reg = hw_impl.accum_reg; + + + //Generate the coreIR module + CoreIR::Instance* accum_reg_ins = accum_reg.generate_accum_reg_instance(options, def); + generate_lake_tile_verilog(options, accum_reg_ins); + string config_mode_ = accum_reg_ins->getMetaData()["mode"]; + + //Wire the PE interface with accumulation register + def->connect(accum_reg_ins->sel(memDatainPort(config_mode_, 1)), pt2wire.at(hw_impl.reduce_PE_inpt)); + //pt2wire.at(pick(inpts)) = accum_reg_ins->sel(memDataoutPort(config_mode, 0)); + def->connect(accum_reg_ins->sel(memDataoutPort(config_mode_, 0)), pt2wire.at(hw_impl.reduce_PE_outpt)); + pt2wire.at(hw_impl.reduce_PE_outpt) = accum_reg_ins->sel(memDatainPort(config_mode_, 0)); +} + + +void insert_accumulation_register(CodegenOptions & options, CoreIR::ModuleDef* def, UBuffer & buf, map & pt2wire, string config_mode) { //only evoke this opitimization for lake if (config_mode != "lake") { return; @@ -3090,9 +3848,9 @@ void insert_accumulation_register(CodegenOptions & options, CoreIR::ModuleDef* d } cout << accum_reg << endl; assert(inpts.size()==1); - buf.replace_pt(pick(inpts), am_mask, out_sched_reg); + buf.replace_pt(pick(inpts), simplify(am_mask), simplify(out_sched_reg)); assert(outpts.size()==1); - buf.replace_pt(pick(outpts), am_mask, in_sched_reg); + buf.replace_pt(pick(outpts), simplify(am_mask), simplify(in_sched_reg)); //Wire the datapath CoreIR::Instance* accum_reg_ins = accum_reg.generate_accum_reg_instance(options, def); @@ -3105,7 +3863,127 @@ void insert_accumulation_register(CodegenOptions & options, CoreIR::ModuleDef* d def->connect(accum_reg_ins->sel(memDataoutPort(config_mode_, 0)), pt2wire.at(pick(outpts))); pt2wire.at(pick(outpts)) = accum_reg_ins->sel(memDatainPort(config_mode_, 0)); - cout << "original buffer for rewrite: " << buf << endl; + cout << "buffer after accumu reg insert: " << buf << endl; + +} + +//FIXME: this function is buggy +//double check if we can use wire after inserting accumulation register +//UBuffer port_reduction(CodegenOptions & options, CoreIR::ModuleDef* def, UBuffer & buf, +// map & pt2wire, UBufferImpl& impl, int bank_id) { +// std::set remove_pt; +// std::set remove_in_set, remove_out_set; +// auto & inpt_broadcast_set = impl.bank_inpt2writers.at(bank_id); +// auto & outpt_broadcast_set = impl.bank_outpt2readers.at(bank_id); +// for (auto outpt : buf.get_out_ports()) { +// auto reads = range(buf.access_map.at(outpt)); +// for (auto inpt : buf.get_in_ports()) { +// auto writes = range(buf.access_map.at(inpt)); +// auto overlap = its(writes, reads); +// //compute dd when write overlap with read +// bool decouple = isl_map_is_injective(to_map(buf.access_map.at(inpt))) && +// isl_map_is_injective(to_map(buf.access_map.at(outpt))); +// if (empty(overlap) || !decouple) +// continue; +// auto dd = buf.dependence_distance_min(inpt, outpt); +// if (dd.has_value()) { +// int dd_raw = dd.get_value(); +// if (dd_raw == 0) { +// cout << "\tRemove port: " << inpt << endl; +// cout << "\tRemove port: " << outpt << endl; +// //Remove pt from ubuf +// remove_pt.insert(inpt); +// remove_pt.insert(outpt); +// +// //remove pt from impl +// for (size_t i = 0; i < inpt_broadcast_set.size(); i ++) { +// if (inpt_broadcast_set.at(i).count(inpt)) { +// remove_in_set.insert(i); +// } +// } +// for (size_t i = 0; i < outpt_broadcast_set.size(); i ++) { +// if (outpt_broadcast_set.at(i).count(outpt)) { +// remove_out_set.insert(i); +// for (string pt: outpt_broadcast_set.at(i)) { +// def->connect(pt2wire.at(inpt), pt2wire.at(pt)); +// } +// } +// } +// } +// } +// } +// } +// +// for (size_t id: remove_in_set) { +// inpt_broadcast_set.erase(inpt_broadcast_set.begin() + id); +// } +// +// for (size_t id: remove_out_set) { +// outpt_broadcast_set.erase(outpt_broadcast_set.begin() + id); +// } +// +// return delete_ports(remove_pt, buf); +//} + +//This is the new coreIR generation pass use the lowering information +//separate optimization from codegen +void UBuffer::generate_coreir_refactor(CodegenOptions& options, + UBufferImpl& impl, + CoreIR::ModuleDef* def, + schedule_info& info, //TODO:remove this + bool with_ctrl) { + auto context = def->getContext(); + map pt2wire; + + //Sequence of port is based on name of bundle + for (auto b : get_in_bundles()) { + int pix_width = port_widths; + int pt_cnt = 0; + auto inpt_bd_wire = def->sel("self." + b); + for (auto inpt : port_bundles.at(b)) { + pt2wire[inpt] = inpt_bd_wire->sel(pt_cnt); + cout << "add input: " << inpt << " to pt2wire" << endl; + pt_cnt ++; + } + } + for (auto b : get_out_bundles()) { + int pix_width = port_widths; + int pt_cnt = 0; + auto outpt_bd_wire = def->sel("self." + b); + for (auto outpt : port_bundles.at(b)) { + pt2wire[outpt] = outpt_bd_wire->sel(pt_cnt); + cout << "add output: " << outpt << " to pt2wire" << endl; + pt_cnt ++; + } + } + + //Go through the banks and generate connection and config + for (auto it: impl.bank_rddom) { + auto bank_id = it.first; + auto target_buf_impl = impl.lowering_info.at(bank_id); + + + insert_accumulation_register(options, def, target_buf_impl, pt2wire); + CoreIR::Instance* buf = map_ubuffer_to_cgra(options, def, target_buf_impl); + + //Wire the stencil valid to flush of ubuffer module + //if we can optmize for coarse grained pipeline scheduler + cgpl_post_processing(options, def, buf, target_buf_impl); + + //add a flush for memory tile if have glb load latency + host2glb_optimization(options, def, buf, target_buf_impl); + + //Wiring the port after generate verilog + wire_ubuf_IO(options, def, pt2wire, buf, impl, info, bank_id, with_ctrl); + + //generate verilog collateral + generate_lake_tile_verilog(options, buf); + } + + //Generate the shift register connection + generate_sreg_and_wire(options, impl, def, pt2wire); + + generate_fanin_connection(options, impl, def, pt2wire); } @@ -3148,6 +4026,9 @@ void UBuffer::generate_coreir(CodegenOptions& options, //This is used for tighten the cyclic banking space target_buf.tighten_iteration_domain(); target_buf.tighten_address_space(); + target_buf.set_dim_id(); + + cout << "\n\tUBuffer after address tighten" << target_buf << endl; //An optimization for coarse grained pipeline, save the iterator level //CoreIR::Instance* cgpl_ctrl; @@ -3161,14 +4042,18 @@ void UBuffer::generate_coreir(CodegenOptions& options, isl_map* cgpl_schedule; bool decouple_ctrl = false; bool substract_glb_latency = false; - cgpl_ctrl_optimization(options, def, target_buf, config_mode, + cgpl_ctrl_optimization(options, target_buf, config_mode, cgpl_schedule, decouple_ctrl, substract_glb_latency); + cout << "\n\tUBuffer after cgpl optimization" << target_buf << endl; insert_accumulation_register(options, def, target_buf, pt2wire, config_mode); + target_buf.remove_redundant_dim(); + //target_buf = port_reduction(options, def, target_buf, pt2wire, impl, bank_id); //Generate the ubuffer module for CGRA //Lake/Pond coreir generation + target_buf.simplify_floor_div_expr(); CoreIR::Instance* buf = map_ubuffer_to_cgra(options, def, target_buf, config_mode); //Wire the stencil valid to flush of ubuffer module @@ -4981,6 +5866,8 @@ void generate_hls_code(std::ostream& out, UBuffer& buf) { void generate_hls_code_unit_test(std::ostream& out, UBuffer& buf) { CodegenOptions options; options.internal = true; + //for compute bank info + options.rtl_options.use_external_controllers = false; options.inner_bank_offset_mode = INNER_BANK_OFFSET_MULTILINEAR; generate_hls_code(options, out, buf); @@ -5461,14 +6348,15 @@ umap* UBuffer::get_lexmax_events(const std::string& outpt) const { //cout << "\tafter: " << str(after) << endl; src_map = its(src_map, after); - //cout << "\tsrc map after its after: " << str(src_map) << endl; + cout << "\tsrc map after its after: " << str(src_map) << endl; src_map = lexmax(src_map); - //cout << "\tsrc map final: " << str(src_map) << endl; + cout << "\tsrc map final: " << str(src_map) << endl; - auto time_to_event = inv(sched); + auto time_to_event = inv(global_in_schedule_with_guard()); + auto lmm = lexmax(dot(src_map, sched)); auto lex_max_events = - dot(lexmax(dot(src_map, sched)), time_to_event); + its(src_map, ::domain(lmm)); release(time_to_event); release(src_map); @@ -5613,7 +6501,10 @@ isl_union_pw_qpolynomial* UBuffer::compute_dd(const std::string& read_port, cons int UBuffer::compute_dd_bound(const std::string& read_port, const std::string& write_port, bool is_max) { auto c = compute_dd(read_port, write_port); - //cout << "DD: " << str(c) << endl; + cout << "DD: " << str(c) << endl; + cout << *this << endl; + cout << "\tread: " << read_port << endl; + cout << "\twrite: " << write_port << endl; int tight; int* b = &tight; @@ -6209,7 +7100,7 @@ void UBuffer::generate_banks(CodegenOptions& options) { for (auto outpt : get_out_ports()) { cout << "Generating banks for port: " << outpt << " on buffer " << name << endl; cout << tab(1) << "access map: " << str(access_map.at(outpt)) << endl; - cout << endl << endl << *this << endl << endl; + //cout << endl << endl << *this << endl << endl; umap* reads_to_sources = get_lexmax_events(outpt); cout << tab(1) << "lexmax events: " << str(reads_to_sources) << endl; uset* producers_for_outpt = range(reads_to_sources); @@ -6222,8 +7113,16 @@ void UBuffer::generate_banks(CodegenOptions& options) { auto overlap = its(range(access_map.at(inpt)), range(access_map.at(outpt))); + cout << "\tinpt: " << inpt << endl; + cout << "\toverlap: " << str(overlap) << endl; + cout << "\toverlap ops: " << str(ops_overlap) << endl; + if (!empty(ops_overlap) && !empty(overlap)) { - stack_bank bank = compute_bank_info(options, inpt, outpt); + stack_bank bank; + if (options.rtl_options.use_external_controllers) + bank = compute_bank_info(options, inpt, outpt); + else + bank = compute_bank_info(inpt, outpt, INT_MAX); add_bank_between(inpt, outpt, bank); } } @@ -6304,6 +7203,7 @@ void UBuffer::generate_banks(CodegenOptions& options) { for(auto bank: get_banks()) { auto inpts = banks_to_inputs.at(bank.name); auto outpts = banks_to_outputs.at(bank.name); + cout << banks_to_outputs.at(bank.name) << endl; assert(banks_to_inputs.at(bank.name).size() == 1); assert(banks_to_outputs.at(bank.name).size() == 1); //int impl_bank = impl.add_new_bank_between(inpts, outpts, to_set(bank.rddom)); @@ -6340,6 +7240,7 @@ void UBuffer::generate_banks(CodegenOptions& options) { // assert(false); //} } else { + assert(inpts.size() <= options.rtl_options.max_inpt); //This is used for broadcasting the output port //use this customized cmp to sort the pt by bundle name @@ -6352,15 +7253,31 @@ void UBuffer::generate_banks(CodegenOptions& options) { outpt_partitions.insert(it); } - for (string inpt: inpts) { - for (auto it : outpt_partitions) { - ret.push_back(make_pair(std::set({inpt}), it.second)); - int bank = impl.add_new_bank_between({inpt}, it.second, to_set(rddom)); - map_insert(impl.bank_inpt2writers, bank, {inpt}); - map_insert(impl.bank_outpt2readers, bank, it.second); + //One bank will work + if (outpt_partitions.size() <= options.rtl_options.max_outpt) { + ret.push_back(make_pair(inpts, outpts)); + int bank = impl.add_new_bank_between(inpts, outpts, to_set(rddom)); + for (auto it : outpt_partitions) { + map_insert(impl.bank_outpt2readers, bank, it.second); + } + for (auto inpt: inpts) { + map_insert(impl.bank_inpt2writers, bank, {inpt}); + } + + //need to put into separate banks + } else { + for (string inpt: inpts) { + for (auto it : outpt_partitions) { + ret.push_back(make_pair(std::set({inpt}), it.second)); + int bank = impl.add_new_bank_between({inpt}, it.second, to_set(rddom)); + map_insert(impl.bank_inpt2writers, bank, {inpt}); + map_insert(impl.bank_outpt2readers, bank, it.second); + } + } } - } + } + return ret; } @@ -7025,6 +7942,7 @@ void UBuffer::generate_banks(CodegenOptions& options) { return base; } + //This is the interface we are using in garnet mapping vector buffer_vectorization( CodegenOptions& options, vector buf_name_vec, @@ -7044,8 +7962,10 @@ void UBuffer::generate_banks(CodegenOptions& options) { //Input must be take care //need to first pad the buffer output to the multiplier of target_buffer.merge_small_dim(fetch_width); + + //comment out dimension padding, only pad the cycle ctride //target_buffer.pad_read_dom_inner_most(fetch_width); - target_buffer.pad_write_dom_inner_most(fetch_width); + //target_buffer.pad_write_dom_inner_most(fetch_width); int dim_id = target_buffer.get_vectorized_dim(fetch_width); if (dim_id == -1) { @@ -7534,11 +8454,12 @@ void UBuffer::generate_banks(CodegenOptions& options) { } //New method to find dynamic schedule - isl_map* get_sram2tb_schedule_with_check(isl_map* out_sched, map sched_map, int ahead_step, int vectorize_loop_dim, bool is_dual_port) { + isl_map* get_sram2tb_schedule_with_check(isl_map* out_sched, map sched_map, int ahead_step, int vectorize_loop_dim, int offset, bool is_dual_port) { cout << "\t output sched: " << str(out_sched)<< endl; + cout << "vectorized dim: " << vectorize_loop_dim << endl; int fetch_ii = stride_in_dim(out_sched, vectorize_loop_dim); //TODO: may need to adjust the delay, /2 is made resnet work - auto temp_sched = linear_schedule(out_sched, {1}, - 2 - ahead_step * fetch_ii/2, false); + auto temp_sched = linear_schedule(out_sched, {1}, - offset - ahead_step * fetch_ii/2, false); cout << "\t temp sched: " << str(temp_sched) << endl; //GET SRAM2TB list and AGG2SRAM list @@ -8339,11 +9260,20 @@ void UBuffer::generate_banks(CodegenOptions& options) { } cout << "rem: " << str(acc_vec_rem) << endl; cout << "new: " << str(acc_vec_new) << endl; + + //TODO: document this. //Go through each iteration domain point for div dimension - for(isl_set* s: get_domain_unmask_set(acc_vec_new, vectorized_dim, unmask_dims)){ - cout << "\t" << str(s) << endl; - int origin_max = get_dim_max(range(its(acc_vec_new, s)), addr_dim); - int trans_max = get_dim_max(range(its(acc_vec_rem, s)), addr_dim); + //Get the first value to see if we need to wait extra fetch to start in the stripmined dimension + auto new_dom_set = get_domain_unmask_set(acc_vec_new, vectorized_dim, unmask_dims); + auto rem_dom_set = get_domain_unmask_set(acc_vec_rem, vectorized_dim, unmask_dims); + assert(new_dom_set.size() == rem_dom_set.size()); + for (auto i = 0; i < new_dom_set.size(); i ++) { + isl_set* s_new = new_dom_set.at(i); + isl_set* s_rem = rem_dom_set.at(i); + cout << "\tnew: " << str(s_new) << endl; + cout << "\trem: " << str(s_rem) << endl; + int origin_max = get_dim_max(range(its(acc_vec_new, s_new)), addr_dim); + int trans_max = get_dim_max(range(its(acc_vec_rem, s_rem)), addr_dim); cout << "origin max: " << str(origin_max) << endl; cout << "trans max: " << str(trans_max) << endl; ahead_step = max(ahead_step, origin_max - trans_max); @@ -8352,7 +9282,82 @@ void UBuffer::generate_banks(CodegenOptions& options) { return ahead_step; } - pair get_vectorized_read_simplified(isl_map* acc_0, isl_map* sched, map sched_record_map, int fetch_width, int addr_dim, bool is_dual_port) { + void UBuffer::simplify_floor_div_expr() { + for (auto bd_name: get_out_bundles()) { + for (auto out_pt_name : port_bundles.at(bd_name) ) { + + auto am = to_map(access_map.at(out_pt_name)); + auto sched = to_map(schedule.at(out_pt_name)); + + + //map from input dim to denominator + map split_dims = get_dim2denom(am); + if (split_dims.size()) { + cout << "\tSimplify output port: " << out_pt_name << endl; + auto trans_map = get_div_trans(am, split_dims); + + auto stripmining_am = dot(inv(trans_map), am); + cout << "\t\t After strip mining: " << str(simplify_expr(stripmining_am)) << endl; + access_map.at(out_pt_name) = to_umap(simplify(stripmining_am)); + domain.at(out_pt_name) = ::domain(stripmining_am); + + cout << "\t\tsched before rewrite: " << str(sched) << endl; + sched = dot(inv(trans_map), sched); + cout << "\t\tsplit new sched: " << str(sched) << endl; + + //update the original schedule for output port schedule generation + schedule.at(out_pt_name) = to_umap(sched); + } + } + } + } + + bool check_back_to_back_access(map & dim2denom) { + if (dim2denom.size() <2) { + return false; + } + int dim_diff = dim2denom.rbegin()->first - (std::next(dim2denom.rbegin()))->first; + return dim_diff <= 1; + } + +bool pad_range_one_vec_dim(map & dim2denom, + isl_map* & acc_vec_new, isl_map* & sched_vec_new, + isl_map* & acc_vec_after_pad, int addr_dim, int fetch_width) { + + //We need to check the sched_vec_new, + //if the stripmined inner most dimension is under the outer loop, + //Then we do not need to pad, but there are loops between the outer loop and inner loop, we need to pad the inner most dimension + bool back_to_back_access = check_back_to_back_access(dim2denom); + int pvec_dim = get_inner_most_related_dom_dim_debug(acc_vec_new, addr_dim, fetch_width); + cout << "Preliminary vectorization dim: " << pvec_dim << endl; + vector rel_map = relation_map(acc_vec_new); + + bool pad_zero_iteration =false; + //TODO male this more formal + if ((!(rel_map.at(pvec_dim-1))) && (dim2denom.size() > 1) + && (!back_to_back_access) && (pvec_dim-1)) { + //Find the iteration dimension and pad 0 to 1 + cout << str(acc_vec_new) << endl; + int in_dim = num_in_dims(acc_vec_new); + cout << in_dim << endl; + auto pad_acc_map = pad_to_domain_ubuf_map(acc_vec_new, pvec_dim - 1, 1); + pad_acc_map = add_relation_ubuf_map(pad_acc_map, pvec_dim - 1, addr_dim); + cout << "\tAfter padding the disappear dimension : " << str(pad_acc_map) << endl; + acc_vec_after_pad = simplify(pad_acc_map); + + //Also need to check the II, basically double the rate + auto pad_sched = pad_to_domain_ubuf_map(sched_vec_new, pvec_dim - 1, 1); + pad_sched= add_relation_ubuf_map(pad_sched, pvec_dim - 1, 0); + cout <<"Before double rate: "<< str(pad_sched) << endl; + pad_sched = double_schedule_rate(pad_sched, pvec_dim - 1, fetch_width); + cout << "After double rate: "<< str(pad_sched) << endl; + sched_vec_new = pad_sched; + pad_zero_iteration = true; + } + return pad_zero_iteration; +} + + pair get_vectorized_read_simplified(isl_map* acc_0, isl_map* sched, map sched_record_map, int fetch_width, int addr_dim, int& vectorized_dim, bool is_dual_port) { isl_ctx* ctx = ::ctx(acc_0); @@ -8368,16 +9373,25 @@ void UBuffer::generate_banks(CodegenOptions& options) { cout << str(div_trans) << endl; auto acc_vec_new = simplify_expr(dot(inv(div_trans), acc_slice)); auto sched_vec_new = simplify_expr(dot(inv(div_trans), sched)); + auto acc_vec_after_pad = cpy(acc_vec_new); + + bool pad_zero_iteration = pad_range_one_vec_dim(dim2denom, + acc_vec_new, sched_vec_new, acc_vec_after_pad, addr_dim, fetch_width); + + auto acc_vec_rem = remove_div(acc_vec_after_pad, addr_dim); + acc_vec_rem = its(acc_vec_rem, ::domain(acc_vec_after_pad)); + //chances are that we have floor div in the new expression, //We need to remove the floor div, that this the acc_vec_rem - auto acc_pattern = AccessPattern(acc_vec_new, ctx); - auto acc_vec_rem = acc_pattern.get_access_map(ctx); - cout << str(get_aff(acc_vec_new)) << endl; - cout << str(get_aff(acc_vec_rem)) << endl; + //This is not a precise way to remove the floor + //auto acc_pattern = AccessPattern(acc_vec_new, ctx); + //auto acc_vec_rem = acc_pattern.get_access_map(ctx); + cout << "new: " << str((acc_vec_new)) << endl; + cout << "remove: " << str((acc_vec_rem)) << endl; //Get the vectorized dimension - int vectorized_dim = + vectorized_dim = get_inner_most_related_dom_dim_debug(acc_vec_rem, addr_dim, fetch_width); cout << "Vectorization dimension: " << vectorized_dim << endl; //cout << "Relation map: " << relation_map(acc_vec_rem) << endl; @@ -8431,6 +9445,7 @@ void UBuffer::generate_banks(CodegenOptions& options) { //} //Move the schedule ahead and pad the domain + //fetch extra to cover the whole iteration domain after vectorization //if (ahead_step) { if (get_dim_max(range(acc_vec_rem), addr_dim) < get_dim_max(range(acc_slice), addr_dim) ) { @@ -8438,15 +9453,105 @@ void UBuffer::generate_banks(CodegenOptions& options) { sched_vec_new = pad_to_domain_ubuf_map(sched_vec_new, vectorized_dim, ahead_step); } cout << "sched before adjust: " << str(sched_vec_new) << endl; + cout << "schedule adjust forward step: " << ahead_step << endl; + + //No need to pad, it is handled by prefetch step + //if (pad_zero_iteration) { + // ahead_step += 1; + // assert(false); + //} //Get final schedule auto final_sched = - get_sram2tb_schedule_with_check(sched_vec_new, sched_record_map, ahead_step, vectorized_dim, false); + get_sram2tb_schedule_with_check(sched_vec_new, sched_record_map, ahead_step, vectorized_dim, 2/*1 cycle read latency, 1 extra cycle */, false); + cout << "final schedule: " << str(final_sched) << endl; cout << "final access: " << str(acc_vec_rem) << endl; return make_pair(acc_vec_rem, final_sched); } + std::set get_decouple_tb_in_dim(isl_map* acc_0, int fetch_width, int addr_dim) { + isl_ctx* ctx = ::ctx(acc_0); + + //First slice the range get the access range transform + auto slice = get_set_slice(range(acc_0), addr_dim, 0/*offset*/, fetch_width); + auto acc_slice = dot(acc_0, slice); + + //From the range transform get the domain transform + auto dim2denom = get_dim2denom(acc_slice); + + isl_map* tb_out_access_map; + std::set proj_dims; + if(dim2denom.size() > 1) { + int proj_dim_cnt = 0; + //only stripmine the outter strip loop + cout << dim2denom << endl; + cout << str(acc_0) << endl; + dim2denom.erase(std::prev(dim2denom.end())); + + //Look at the extent it must need multiple fetch + for (auto it: dim2denom) { + if(get_dim_extent(::domain(acc_0), it.first) > fetch_width) { + proj_dims.insert(it.first + proj_dim_cnt); + proj_dim_cnt ++; + } + } + } + return proj_dims; + } + + pair get_stripmined_read(isl_map* acc_0, isl_map* sched, int fetch_width, int addr_dim, int vectorized_dim) { + + isl_ctx* ctx = ::ctx(acc_0); + + //First slice the range get the access range transform + auto slice = get_set_slice(range(acc_0), addr_dim, 0/*offset*/, fetch_width); + auto acc_slice = dot(acc_0, slice); + + //From the range transform get the domain transform + auto dim2denom = get_dim2denom(acc_slice); + + isl_map* tb_out_access_map; + isl_map* tb_out_sched; + std::set proj_dims; + + //TODO back_to back access is just a heuristic what we should do is to caculate dd + if ((dim2denom.size() > 1) && (!check_back_to_back_access(dim2denom))) { + int proj_dim_cnt = 0; + //only stripmine the outter strip loop + cout << dim2denom << endl; + cout << str(acc_0) << endl; + dim2denom.erase(std::prev(dim2denom.end())); + for (auto it: dim2denom) { + cout << "domain: " << str(::domain(acc_0)) << endl; + cout << "dim extent: " << get_dim_extent(::domain(acc_0), it.first) << endl; + if(get_dim_extent(::domain(acc_0), it.first) > fetch_width) { + proj_dims.insert(it.first + proj_dim_cnt); + proj_dim_cnt ++; + } + } + } + if (proj_dims.size() > 0) { + + auto div_trans = get_div_trans(acc_slice, dim2denom); + //Find the tb output + auto acc_stripmine = simplify_expr(dot(inv(div_trans), acc_0)); + tb_out_sched= simplify_expr(dot(inv(div_trans), sched)); + cout << "\taccess map for tb out: " << str(acc_stripmine) << endl; + cout << "\tproj dim: " << proj_dims << endl;; + auto ap_tb = AccessPattern(acc_stripmine, ctx); + tb_out_access_map = ap_tb.get_access_map_and_decouple_reuse(ctx, addr_dim, proj_dims); + } else { + auto acc_pattern = AccessPattern(acc_0, ctx); + tb_out_access_map= acc_pattern.get_access_map_and_decouple_reuse(ctx, addr_dim , false); + tb_out_sched = sched; + } + + cout << "tb output access map: " << str(tb_out_access_map) << endl; + + return make_pair(tb_out_access_map, tb_out_sched); + } + pair get_vectorized_read(isl_map* acc_0, isl_map* sched, map sched_record_map, int fetch_width, int addr_dim, bool is_dual_port) { int vectorize_loop_dim = get_inner_most_related_dom_dim(acc_0, addr_dim, fetch_width); int vectorize_loop_dim_origin = vectorize_loop_dim; @@ -8535,7 +9640,7 @@ void UBuffer::generate_banks(CodegenOptions& options) { cout << "\tsched vec before moving: "<< str(sched_vec) << endl; //Adjust the sram2tb fetch based on the schedule - auto final_sched = get_sram2tb_schedule_with_check(sched_vec, sched_record_map, ahead_step, vectorize_loop_dim, is_dual_port); + auto final_sched = get_sram2tb_schedule_with_check(sched_vec, sched_record_map, ahead_step, vectorize_loop_dim, 2, is_dual_port); cout << "\tfinal access: " << str(acc_vec) << endl; cout << "\tfinal sched: " << str(final_sched) << endl; return make_pair(acc_vec, final_sched); @@ -8718,36 +9823,12 @@ void UBuffer::generate_banks(CodegenOptions& options) { auto sched = to_map(schedule.at(out_pt_name)); - //map from input dim to denominator - //TODO: move this into a function, and also move into vectorization preprocessing - map split_dims = get_dim2denom(am); - if (split_dims.size()) { - auto trans_map = get_div_trans(am, split_dims); - - auto stripmining_am = dot(inv(trans_map), am); - cout << "\t After strip mining: " << str(simplify_expr(stripmining_am)) << endl; - access_map.at(out_pt_name) = to_umap(simplify(stripmining_am)); - domain.at(out_pt_name) = ::domain(stripmining_am); - string dom_name = domain_name(am) + "_sram2tb"; - - cout << "before rewrite: " << str(sched) << endl; - sched = dot(inv(trans_map), sched); - cout << "split new sched: " << str(sched) << endl; - - //update the original schedule for output port schedule generation - schedule.at(out_pt_name) = to_umap(sched); - - //update the access name - am = to_map(access_map.at(out_pt_name)); - } - - - //New method for sram read schedule + int vectorized_dim = 0; auto sram_ir = get_vectorized_read_simplified( to_map(access_map.at(out_pt_name)), to_map(schedule.at(out_pt_name)), - sched_record_map, fetch_width, dim_id, is_dual_port); + sched_record_map, fetch_width, dim_id, vectorized_dim, is_dual_port); isl_map* vectorized_access = add_domain_suffix(sram_ir.first, "_sram2tb_" + str(tb_cnt)); isl_set* dom = ::domain(vectorized_access); @@ -8805,6 +9886,8 @@ void UBuffer::generate_banks(CodegenOptions& options) { auto range_interpolation_maps = get_vectorize_interpolate( range(vectorized_access), dim_id, fetch_width); int pt_cnt = 0; + std::set proj_dim = + get_decouple_tb_in_dim(to_map(access_map.at(out_pt_name)), fetch_width, dim_id); for (auto interpolation: range_interpolation_maps) { string tb_pt_name = out_pt_name + "_out_" + std::to_string(pt_cnt); tb.port_bundles[bd_name + "_tb_in"].push_back(tb_pt_name); @@ -8815,7 +9898,15 @@ void UBuffer::generate_banks(CodegenOptions& options) { //always decouple the output access, and remove refetch from SRAM auto acc_pt = AccessPattern(tb_in_access_map, ctx); - tb_in_access_map = acc_pt.get_access_map_and_decouple_reuse(ctx, dim_id, false); + + if (proj_dim.size() == 0) { + //old method to get tb in access pattern + tb_in_access_map = acc_pt.get_access_map_and_decouple_reuse(ctx, dim_id, false); + } else { + //new method for get tb in access pattern + tb_in_access_map = acc_pt.get_access_map_and_decouple_reuse(ctx, dim_id, vectorized_dim); + } + //tb.access_map[tb_pt_name] = to_umap(decouple_acc_map); auto sram_out_access_map = add_range_suffix(rewrite_access_map, "_sram"); @@ -8843,49 +9934,76 @@ void UBuffer::generate_banks(CodegenOptions& options) { cout << "\tAdd TB output port: " << out_pt_name << endl; - auto outpt_acc_map = remap_access_to_new_buffer(out_pt_name, "_" + to_string(tb_cnt) + "_tb"); - outpt_acc_map = acc_pattern.get_access_map_and_decouple_reuse(ctx, dim_id, false); - outpt_acc_map = add_range_suffix(outpt_acc_map, "_" + to_string(tb_cnt) + "_tb"); - - //Strip mining the output loop - //TODO: remove stripmining - //Strip mining is needed for unit test - //if (acc_pattern.can_stripmining(ctx, dim_id, fetch_width)) { - if (false) { - //if (true) { - isl_map* op_stripmining = acc_pattern.get_op_stripmining(ctx, dim_id, fetch_width, ""); - std::cout << "\ttransform stripmining: " << str(op_stripmining) << endl; - isl_set* sm_domain = range(its(op_stripmining, domain.at(out_pt_name))); - std::cout << "\tdomain stripmining: " << str(sm_domain) << endl; - auto sm_access_map = dot(inv(op_stripmining), outpt_acc_map); - auto sm_sched = dot(inv(op_stripmining), to_map(schedule.at(out_pt_name))); - sm_domain = add_suffix(sm_domain, "_tb2out_" + str(tb_cnt)); - sm_access_map = add_domain_suffix(sm_access_map, "_tb2out_" + str(tb_cnt)); - sm_sched = add_domain_suffix(sm_sched, "_tb2out_" + str(tb_cnt)); - cout << "\tAccess map decouple reuse: " << str(outpt_acc_map) << endl; - //tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, sm_sched); - tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, its(sm_sched, sm_domain)); - tb.port_bundles[bd_name+"_tb_out"].push_back(out_pt_name + "_out"); - - } else { - isl_set* sm_domain = domain.at(out_pt_name); - auto sm_access_map = outpt_acc_map; - auto sm_sched = to_map(schedule.at(out_pt_name)); - sm_domain = add_suffix(sm_domain, "_tb2out_" + str(tb_cnt)); - sm_access_map = add_domain_suffix(sm_access_map, "_tb2out_" + str(tb_cnt)); - sm_sched = add_domain_suffix(sm_sched, "_tb2out_" + str(tb_cnt)); - cout << "\tAccess map decouple reuse: " << str(outpt_acc_map) << endl; - //tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, sm_sched); - tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, its(sm_sched, sm_domain)); - tb.port_bundles[bd_name+"_tb_out"].push_back(out_pt_name + "_out"); - } - - cout << "TB : " << tb << endl; - //Add one more step to pad reacess dimension - //tb.pad_reaccess_dimension(fetch_width); - - ////Check capacity of tb - //auto capacity = tb.capacity(); + pair tb_ir = get_stripmined_read( + to_map(access_map.at(out_pt_name)), + to_map(schedule.at(out_pt_name)), + fetch_width, dim_id, vectorized_dim); + + auto outpt_acc_map = add_range_suffix(tb_ir.first, "_" + to_string(tb_cnt) + "_tb"); + isl_set* sm_domain = ::domain(outpt_acc_map); + auto sm_access_map = outpt_acc_map; + auto sm_sched = tb_ir.second; + sm_domain = add_suffix(sm_domain, "_tb2out_" + str(tb_cnt)); + sm_access_map = add_domain_suffix(sm_access_map, "_tb2out_" + str(tb_cnt)); + sm_sched = add_domain_suffix(sm_sched, "_tb2out_" + str(tb_cnt)); + cout << "\tAccess map decouple reuse: " << str(outpt_acc_map) << endl; + //tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, sm_sched); + tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, its(sm_sched, sm_domain)); + tb.port_bundles[bd_name+"_tb_out"].push_back(out_pt_name + "_out"); + + + + //int dim_added = num_in_dims(vectorized_access) - num_in_dims(am); + //cout << "vec access: " << str(vectorized_access) << endl; + //cout << "original access: " << str(am) << endl; + //cout << "\tvec dim: " << vectorized_dim << endl; + //if(dim_added > 0) { + // vectorized_dim -= dim_added; + //} + //outpt_acc_map = acc_pattern.get_access_map_and_decouple_reuse(ctx, dim_id, vectorized_dim); + //auto outpt_acc_map = acc_pattern.get_access_map_and_decouple_reuse(ctx, dim_id, false); + //outpt_acc_map = add_range_suffix(outpt_acc_map, "_" + to_string(tb_cnt) + "_tb"); + + ////assert(dim_added <= 0); + ////Strip mining the output loop + ////TODO: remove stripmining + ////Strip mining is needed for unit test + ////if (acc_pattern.can_stripmining(ctx, dim_id, fetch_width)) { + //if (false) { + // isl_map* op_stripmining = acc_pattern.get_op_stripmining(ctx, dim_id, fetch_width, ""); + // std::cout << "\ttransform stripmining: " << str(op_stripmining) << endl; + // isl_set* sm_domain = range(its(op_stripmining, domain.at(out_pt_name))); + // std::cout << "\tdomain stripmining: " << str(sm_domain) << endl; + // auto sm_access_map = dot(inv(op_stripmining), outpt_acc_map); + // auto sm_sched = dot(inv(op_stripmining), to_map(schedule.at(out_pt_name))); + // sm_domain = add_suffix(sm_domain, "_tb2out_" + str(tb_cnt)); + // sm_access_map = add_domain_suffix(sm_access_map, "_tb2out_" + str(tb_cnt)); + // sm_sched = add_domain_suffix(sm_sched, "_tb2out_" + str(tb_cnt)); + // cout << "\tAccess map decouple reuse: " << str(outpt_acc_map) << endl; + // //tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, sm_sched); + // tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, its(sm_sched, sm_domain)); + // tb.port_bundles[bd_name+"_tb_out"].push_back(out_pt_name + "_out"); + // assert(false); + + //} else { + // isl_set* sm_domain = domain.at(out_pt_name); + // auto sm_access_map = outpt_acc_map; + // auto sm_sched = to_map(schedule.at(out_pt_name)); + // sm_domain = add_suffix(sm_domain, "_tb2out_" + str(tb_cnt)); + // sm_access_map = add_domain_suffix(sm_access_map, "_tb2out_" + str(tb_cnt)); + // sm_sched = add_domain_suffix(sm_sched, "_tb2out_" + str(tb_cnt)); + // cout << "\tAccess map decouple reuse: " << str(outpt_acc_map) << endl; + // //tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, sm_sched); + // tb.add_out_pt(out_pt_name+"_out", sm_domain, sm_access_map, its(sm_sched, sm_domain)); + // tb.port_bundles[bd_name+"_tb_out"].push_back(out_pt_name + "_out"); + //} + + //cout << "TB : " << tb << endl; + ////Add one more step to pad reacess dimension + ////tb.pad_reaccess_dimension(fetch_width); + + //////Check capacity of tb + ////auto capacity = tb.capacity(); //cout << "TB size: " << capacity << endl; //auto mem = options.mem_hierarchy.at("mem"); //assert(capacity <= mem.capacity.at("tb") / mem.in_port_width.at("tb")); @@ -9157,14 +10275,30 @@ void UBuffer::generate_banks(CodegenOptions& options) { // at that component typedef std::map fixed_subaddress; - map find_fixed_subaddresses(const vector& ports, UBuffer& buf) { - map addrs; + //This is not correct + //map find_fixed_subaddresses(const vector& ports, UBuffer& buf) { + // map addrs; + // for (auto pt : ports) { + // isl_multi_aff* access = get_multi_aff(buf.access_map.at(pt)); + // map constant_offsets = constant_components(access); + // for (auto ent : constant_offsets) { + // addrs[pt][ent.first] = to_int(ent.second); + // } + // } + // return addrs; + //} + + + map> find_fixed_subaddresses(const vector& ports, UBuffer& buf) { + map> addrs; for (auto pt : ports) { isl_multi_aff* access = get_multi_aff(buf.access_map.at(pt)); map constant_offsets = constant_components(access); + fixed_subaddress tmp; for (auto ent : constant_offsets) { - addrs[pt][ent.first] = to_int(ent.second); + tmp.insert({ent.first, to_int(ent.second)}); } + dbhc::map_insert(addrs, tmp, pt); } return addrs; } @@ -9249,23 +10383,28 @@ void UBuffer::generate_banks(CodegenOptions& options) { vector > filtered_io_groups; for (auto& g : overlapping) { vector ins; - vector outs; + std::set outs; for (auto pt : g) { if (buf.is_in_pt(pt)) { ins.push_back(pt); } else { assert(buf.is_out_pt(pt)); - outs.push_back(pt); + outs.insert(pt); } } + auto out_unique_map = buf.get_unique_ports(outs); + vector unique_outs; + for (auto it: out_unique_map) { + unique_outs.push_back(it.first); + } cout << "overlapping input:" << ins << endl; - cout << "overlapping output:" << outs << endl << endl; + cout << "overlapping output:" << unique_outs << endl << endl; //TODO should take conside the hardware constraint here if (ins.size() > 1) { filtered_io_groups.push_back(ins); } - if (outs.size() > 1) { - filtered_io_groups.push_back(outs); + if (unique_outs.size() > 1) { + filtered_io_groups.push_back(unique_outs); } } @@ -9315,6 +10454,60 @@ void UBuffer::generate_banks(CodegenOptions& options) { return cyclic_partition_factor; } + //This is the cyclic partition was used in garnet mapping + maybe > cyclic_partition(CodegenOptions& options, UBuffer& buf) { + vector > filtered_io_groups = + overlapping_large_io_port_groups(options, buf); + + if (filtered_io_groups.size() == 0) { + std::vector empty; + return maybe >(empty); + } + + //get_banking factors + vector bk_factors = buf.get_cyclic_banking_factors(); + int bank_num = std::accumulate( + begin(bk_factors), end(bk_factors), 1, std::multiplies()); + std::vector dims; + for (auto g : filtered_io_groups) { + assert(g.size() > 0); + + //cout << "Error: No viable banking strategy for " << buf.name << endl; + //cout << tab(1) << "Cannot partition group: " << endl; + //for (auto pt : g) { + // cout << tab(2) << pt << endl; + // cout << tab(3) << str(buf.access_map.at(pt)) << endl; + // cout << tab(3) << str(buf.schedule.at(pt)) << endl; + //} + cout << "\tpart size:" < > embarassing_partition(CodegenOptions& options, UBuffer& buf) { vector > filtered_io_groups = @@ -9339,15 +10532,23 @@ void UBuffer::generate_banks(CodegenOptions& options) { } cout << "\tpart size:" < + total_banks * (options.rtl_options.max_inpt + options.rtl_options.max_outpt)) { + cout << "Cannot merge port although they did not overlap" << endl; + return {}; } isl_multi_aff* bank_func = embarassing_partition_function(buf, dims); @@ -9392,7 +10603,8 @@ void UBuffer::generate_banks(CodegenOptions& options) { return {}; } for (auto ent : parts) { - for (auto d : ent.second) { + //for (auto d : ent.second) { + for (auto d : ent.first) { dims.insert(d.first); } } @@ -9790,8 +11002,16 @@ void UBuffer::generate_banks(CodegenOptions& options) { out << "# nodes: " << dg.nodes.size() << endl; out << "# edges: " << dg.weights.size() << endl; for (auto e : dg.out_edges) { + out << "Group: "<< tab(2) << e.first << endl; for (auto dst : e.second) { - out << tab(1) << e.first << " -> (" << dg.weight(e.first, dst) << ") " << dst << endl; + out << tab(4) << e.first << " -> (" << dg.weight(e.first, dst) << ") " << dst << endl; + } + } + + for (auto e : dg.out_edges) { + out << "Fanin Group: "<< tab(2) << e.first << endl; + for (auto src: e.second) { + out << tab(4) << src << " -> (" << dg.weight(src, e.first) << ") " << e.first << endl; } } return out; @@ -9842,7 +11062,7 @@ vector analyze_memory_demands(prog& prg, UBuffer& buf, schedule_info& hwinf cout << buf << endl; - map> shift_registered_outputs = determine_shift_reg_map(prg, buf, hwinfo); + map>> shift_registered_outputs = determine_shift_reg_map_new(prg, buf, hwinfo); vector>> shift_registered_outputs_to_outputs = determine_output_shift_reg_map(prg, buf,hwinfo); std::set sr_ports; for (auto port : shift_registered_outputs) { @@ -9860,7 +11080,8 @@ vector analyze_memory_demands(prog& prg, UBuffer& buf, schedule_info& hwinf cout << "In prg: " << prg.name << " a buffer is not a shift register!" << endl; cout << "Shift registered in -> out..." << endl; for (auto e : shift_registered_outputs) { - cout << tab(1) << e.first << " -> " << e.second.second << endl; + for (auto pt_delay_pair: e.second) + cout << tab(1) << e.first << " -> " << pt_delay_pair.second<< endl; } //assert(false); //auto eb = embarassing_partition(reduced, hwinfo); @@ -9975,8 +11196,8 @@ vector >> determine_output_shift_reg_map( auto reads = buf.access_map.at(outpt); auto reads_src = buf.access_map.at(outpt_src); - cout << "reads: " << str(reads) << endl; - cout << "reads_src: " << str(reads_src) << endl; + //cout << "reads: " << str(reads) << endl; + //cout << "reads_src: " << str(reads_src) << endl; auto outpt_read_data = range(reads); auto outpt_src_read_data = range(reads_src); @@ -9990,8 +11211,8 @@ vector >> determine_output_shift_reg_map( continue; } - cout << str(buf.schedule.at(outpt)) << endl; - cout << str(buf.schedule.at(outpt_src)) << endl; + //cout << str(buf.schedule.at(outpt)) << endl; + //cout << str(buf.schedule.at(outpt_src)) << endl; isl_aff * outpt_sched = get_aff(buf.schedule.at(outpt)); isl_aff * outpt_src_sched = get_aff(buf.schedule.at(outpt_src)); outpt_sched = set_name(outpt_sched,"bump"); @@ -10003,7 +11224,7 @@ vector >> determine_output_shift_reg_map( reads_src_aff = set_name(reads_src_aff,"bump"); isl_aff * diff_loc = sub(reads_aff, reads_src_aff); - cout << str(diff) << endl; + //cout << str(diff) << endl; if(!isl_aff_is_cst(diff) || to_int(const_coeff(diff)) < 0) { @@ -10030,13 +11251,15 @@ vector >> determine_output_shift_reg_map( return shift_registered_outputs; } -map > determine_shift_reg_map( +map > determine_shift_reg_map( prog& prg, UBuffer& buf, schedule_info& hwinfo) { auto sc = buf.global_schedule(); bool any_reduce_ops_on_buffer = false; + + //from output port to a vector of input port delay pair map > shift_registered_outputs; for (auto op : prg.all_ops()) { if (elem(buf.name, op->buffers_read()) && elem(buf.name, op->buffers_written())) { @@ -10057,12 +11280,94 @@ map > determine_shift_reg_map( auto written = read_op->buffers_written(); string writer_name = domain_name(pick(get_maps(buf.access_map.at(inpt)))); - //cout << "Writer name: " << writer_name << endl; + cout << "Writer name: " << writer_name << endl; + op* write_op = prg.find_op(writer_name); + + cout << "read_op read: " << read << endl; + cout << "read_op write: " << read_op->buffers_written() << endl; + + cout << "write_op write: " << written << endl; + cout << "write_op read: " << write_op->buffers_read() << endl; + //prg.pretty_print(); + auto read_op_rolled_reduce_bufs = intersection(read, written); + auto write_op_rolled_reduce_bufs = + intersection(write_op->buffers_read(), write_op->buffers_written()); + + // Dont shift register rolled-reduces + // If it's not rolled reduce on the buffer trying to optimize, it's fine + if (read_op_rolled_reduce_bufs.count(buf.name) == 0 && + write_op_rolled_reduce_bufs.count(buf.name) == 0) { + cout << "Calculate DDs for creating shift registers." << endl; + auto dd = + dependence_distance_singleton(buf, inpt, outpt, sc); + if (dd.has_value()) { + int dd_raw = dd.get_value(); + dd_raw -= hwinfo.compute_latency(write_op); + if (write_op->buffers_read().size() > 0) { + dd_raw -= hwinfo.load_latency(pick(write_op->buffers_read())); + } + dd_raw += hwinfo.load_latency(buf.name); + + if (!(dd_raw >= 0)) { + cout << "Error: Negative dependence distance: " << dd_raw << endl; + } + assert(dd_raw >= 0); + shift_registered_outputs[ outpt] = {inpt, dd_raw}; + } + } + } + } + } + return shift_registered_outputs; +} + +map > > determine_shift_reg_map_new( + prog& prg, + UBuffer& buf, + schedule_info& hwinfo) +{ + auto sc = buf.global_schedule(); + bool any_reduce_ops_on_buffer = false; + + //from output port to a vector of input port delay pair + map > > shift_registered_outputs; + for (auto op : prg.all_ops()) { + if (elem(buf.name, op->buffers_read()) && elem(buf.name, op->buffers_written())) { + //if (intersection(op->buffers_read(), op->buffers_written()).size() != 0) { + any_reduce_ops_on_buffer = true; + break; + } + } + + if (!any_reduce_ops_on_buffer) { + cout << "==== No reduce ops on this buffer" << endl; + for (auto outpt : buf.get_out_ports()) { + for (auto inpt : buf.get_in_ports()) { + string reader_name = domain_name(pick(get_maps(buf.access_map.at(outpt)))); + op* read_op = prg.find_op(reader_name); + + auto read = read_op->buffers_read(); + auto written = read_op->buffers_written(); + + string writer_name = domain_name(pick(get_maps(buf.access_map.at(inpt)))); + cout << "Writer name: " << writer_name << endl; op* write_op = prg.find_op(writer_name); + cout << "read_op read: " << read << endl; + cout << "read_op write: " << read_op->buffers_written() << endl; + + cout << "write_op write: " << written << endl; + cout << "write_op read: " << write_op->buffers_read() << endl; + //prg.pretty_print(); + auto read_op_rolled_reduce_bufs = intersection(read, written); + auto write_op_rolled_reduce_bufs = + intersection(write_op->buffers_read(), write_op->buffers_written()); + // Dont shift register rolled-reduces - if (intersection(read, written).size() == 0 && - intersection(write_op->buffers_read(), write_op->buffers_written()).size() == 0) { + // If it's not rolled reduce on the buffer trying to optimize, it's fine + if (read_op_rolled_reduce_bufs.count(buf.name) == 0 && + write_op_rolled_reduce_bufs.count(buf.name) == 0) { + cout << "Calculate DDs for creating shift registers." << endl; auto dd = dependence_distance_singleton(buf, inpt, outpt, sc); if (dd.has_value()) { @@ -10077,7 +11382,7 @@ map > determine_shift_reg_map( cout << "Error: Negative dependence distance: " << dd_raw << endl; } assert(dd_raw >= 0); - shift_registered_outputs[outpt] = {inpt, dd_raw}; + map_insert(shift_registered_outputs, outpt, {inpt, dd_raw}); } } } @@ -10089,11 +11394,28 @@ map > determine_shift_reg_map( dgraph build_in_to_out_shift_register_graph(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo) { - map> shift_registered_outputs = determine_shift_reg_map(prg, buf, hwinfo); + map>> shift_registered_outputs = determine_shift_reg_map_new(prg, buf, hwinfo); dgraph dg; + bool fanin_node = false; for (auto pt : shift_registered_outputs) { - dg.add_edge(pt.second.first, pt.first, pt.second.second); + string outpt = pt.first; + if (pt.second.size() > 1) { + //handle this case specially + for (auto pt_delay_pair: pt.second) { + string inpt = pt_delay_pair.first; + int delay = pt_delay_pair.second; + dg.add_fanin_edge(inpt, outpt, delay); + } + fanin_node = true; + } else { + for (auto pt_delay_pair: pt.second) { + string inpt = pt_delay_pair.first; + int delay = pt_delay_pair.second; + dg.add_edge(inpt, outpt, delay); + } + + } } cout << "DG: ..." << endl; @@ -10101,6 +11423,59 @@ dgraph build_in_to_out_shift_register_graph(CodegenOptions& options, prog& prg, return dg; } +//This pass will be called after shift register optimization, in order to find the port reuse, +//now we only find the ports with same schedule, +//but we give the threshold to give user a capability to find extra port sharing opportunity +dgraph build_out_to_out_shift_register_graph(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo, int threshold) { + + dgraph dg; + vector>> shift_registered_outputs_to_outputs = determine_output_shift_reg_map(prg, buf, hwinfo); + + cout << "out -> out srs: " << shift_registered_outputs_to_outputs.size() << endl; + for (auto pt : shift_registered_outputs_to_outputs) { + if (pt.second.second <= threshold) { + dg.add_edge(pt.second.first, pt.first, pt.second.second); + } + } + + cout << "out2out DG: ..." << endl; + cout << dg << endl; + return dg; +} + +std::set output_port_sharing(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo, UBufferImpl& impl) { + std::set done_pt = impl.get_sr_outpts(); + if (done_pt.size()) + return done_pt; + dgraph dg = build_out_to_out_shift_register_graph(options, prg, buf, hwinfo, 0); + vector> port_groups; + for (auto it: dg.out_edges) { + bool added = false; + for (auto& group: port_groups) { + if (group.count(it.first)) { + group.insert(it.second.begin(), it.second.end()); + added = true; + break; + } + } + if (!added) { + std::set tmp = it.second; + tmp.insert(it.first); + port_groups.push_back(it.second); + } + } + for (auto grp: port_groups) { + cout << "port sharing groups: " << grp << endl; + for (auto it = grp.begin(); it != grp.end(); it ++) { + if (it != grp.begin()) { + impl.add_o2o_info(*grp.begin(), *it, 0); + done_pt.insert(*it); + } + } + } + return done_pt; +} + //helper function to create all the shift registered port void create_subbranch(const std::string& out_pt, dgraph& sr_graph, UBuffer& buf, UBufferImpl &impl) { auto src2dst = sr_graph.get_sub_branch(out_pt); @@ -10121,15 +11496,38 @@ void create_subbranch(const std::string& out_pt, dgraph& sr_graph, UBuffer& buf, dgraph build_shift_registers(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo) { dgraph shift_registers = build_in_to_out_shift_register_graph(options, prg, buf, hwinfo); - cout << "Shift registers..." << endl; + cout << "Naive Shift registers..." << endl; cout << shift_registers << endl; + //cout << buf << endl; dgraph dg; + for (auto it: shift_registers.fanin_edges) { + string dst = it.first; + cout << tab(2) << "get dst: " << it.first << endl; + for (auto src: it.second) { + int delay = shift_registers.weight(src, dst); + dg.add_fanin_edge(src, dst, delay); + cout << tab(4) << "src: " << src << ", weight = " << delay << endl; + } + } + //dg.fanin_edges = shift_registers.fanin_edges; + //for (auto it: dg.fanin_edges) { + // cout << tab(2) << "get dst: " << it.first << endl; + // string dst = it.first; + // for (auto src: it.second) { + // cout << tab(4) << "src: " << src << ", weight = " << shift_registers.weights.at({src, dst}); + // dg.weights[{src, dst}] = shift_registers.weights.at({src, dst}); + // } + //} if (!shift_registers.has_nodes()) { return dg; } for (auto inpt : buf.get_in_ports()) { + cout << "inpt: " << inpt << endl; vector > vals; + //chances are that we only have fanin input in shift register and give up. + if (!shift_registers.out_edges.count(inpt)) + continue; for (auto v : shift_registers.out_edges.at(inpt)) { vals.push_back({v, shift_registers.weight(inpt, v)}); } @@ -10138,6 +11536,7 @@ dgraph build_shift_registers(CodegenOptions& options, prog& prg, UBuffer& buf, s cout << tab(1) << v.first << " -(" << v.second << ")-> " << v.second << endl; } + //TODO use option.threshold, this is the place to separate shift reg and row buffer vector > > reg_chains; split_by(vals, reg_chains, [](const pair& a, const pair& b) { return abs(a.second - b.second) < 20; @@ -10168,37 +11567,133 @@ UBufferImpl generate_optimized_memory_implementation( //if (prg.is_boundary(buf.name)) // return impl; + + //create ubufferimpl from analysis ubuffer data structure + cout << "create shift register for " << buf << endl; auto impl = port_group2bank(options, prg, buf, hwinfo); + cout << impl << endl; + std::set done_outpt= output_port_sharing(options, prg, buf, hwinfo, impl); + auto new_buf = delete_ports(done_outpt, buf); cout << "After shift register optimization: " << impl << endl; - if (!impl.is_pure_shift_register(buf.get_out_ports())) - generate_banks_garnet(options, buf, impl, hwinfo); + cout << "Done ports: " << done_outpt << endl; + cout << "reduced buffer: " << new_buf << endl; + + if (!impl.is_pure_shift_register(new_buf.get_out_ports())) + generate_banks_garnet(options, new_buf, impl, hwinfo); cout << "After banking optimization: " << impl << endl; - impl.bank_merging(options); + //impl.bank_merging(options); + impl.sort_bank_port(); cout << "After bank merging: " << impl << endl; return impl; } +//This function will go through the ubufferimpl data type +//and create some essenstial information for garnet mapping + +void lower_to_garnet_implementation(CodegenOptions& options, + UBuffer& buf, UBufferImpl& impl, schedule_info& info) { + + + for (auto it: impl.bank_rddom) { + GarnetImpl CGRAImpl; + auto bank_id = it.first; + UBuffer target_buf = buf.generate_ubuffer(impl, info, bank_id); + + //This is used for tighten the cyclic banking space + target_buf.tighten_iteration_domain(); + target_buf.tighten_address_space(); + target_buf.set_dim_id(); + + cout << "\n\tUBuffer after address tighten" << target_buf << endl; + + //Determine the config mode + CGRAImpl.config_mode = buf.determine_config_mode(options, target_buf); + + //If this is memory do double buffer optimization + //rewrite the ubuffer IR and change the cgpl control + isl_map* cgpl_schedule; + bool decouple_ctrl = false; + bool substract_glb_latency = false; + cgpl_ctrl_optimization(options, target_buf, CGRAImpl.config_mode, + cgpl_schedule, decouple_ctrl, substract_glb_latency); + CGRAImpl.decouple_ctrl = decouple_ctrl; + CGRAImpl.substract_glb_latency = substract_glb_latency; + CGRAImpl.cgpl_schedule = cgpl_schedule; + + cout << "\n\tUBuffer after cgpl optimization" << target_buf << endl; + + //Fisrt create the shift register + create_accumulation_register_and_rewrite_buf(options, target_buf, CGRAImpl); + + target_buf.remove_redundant_dim(); + //Generate the ubuffer module for CGRA + target_buf.simplify_floor_div_expr(); + + if (CGRAImpl.config_mode == "lake") { + map vectorized_buf; + string ub_ins_name = "ub_" + target_buf.name; + vectorized_buf.insert( + {target_buf.name+ "_ubuf", target_buf}); + auto capacity = total_capacity(target_buf); + + cout << "vectorization buffer capacity: " << capacity << endl; + CoreIR::Instance* buf; + cout << "vectorization buf name: " << target_buf.name << endl; + buffer_vectorization(options, {target_buf.name+ "_ubuf"}, vectorized_buf); + //This function is not needed + //vectorized_buf = decouple_multi_tile_ubuffer(options, vectorized_buf); + for (auto buf: vectorized_buf) { + cout << "after vectorization codegen: " << buf.first << endl << buf.second << endl; + CGRAImpl.sub_component.insert(buf); + } + } + CGRAImpl.target_buf = target_buf; + + //Save the lower information into ubuffer impl + impl.lowering_info[bank_id] = CGRAImpl; + } +} + + UBufferImpl port_group2bank(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo) { UBufferImpl impl; - int in_port_width = options.rtl_options.max_inpt; - int out_port_width = options.rtl_options.max_outpt; + //int in_port_width = options.rtl_options.max_inpt; + //int out_port_width = options.rtl_options.max_outpt; auto sr_graph = build_shift_registers(options, prg, buf, hwinfo); if (!sr_graph.has_nodes()) return impl; + for (auto it: sr_graph.fanin_edges) { + for (auto src: it.second) { + cout << "dst: " << it.first << endl; + cout << "src: " << src << endl; + int delay = sr_graph.weights.at({src, it.first}); + if (delay < options.merge_threshold) { + impl.add_fanin_info(src, it.first, delay); + } else { + //TODO: add support for row buffer + assert(false); + } + } + } //Currently only group output port //TODO: support input port grouping in the future for (auto src: buf.get_in_ports()) { vector > out_delays; + + //chances are that we have only fanin + if (sr_graph.out_edges.count(src) == 0) + continue; + for (auto dst: sr_graph.out_edges.at(src)) { cout << "edge: " << src << "=>" << dst << ", w=" << sr_graph.weight(src, dst) << endl; out_delays.push_back({dst, sr_graph.weight(src, dst)}); @@ -10317,13 +11812,46 @@ isl_map* build_buffer_impl_embarrassing_banking(UBuffer& buf, schedule_info& hwi cout << "Bank map: " << bank_func << endl; //assert(false); isl_map* m = isl_map_read_from_str(buf.ctx, bank_func.c_str()); + + //There could have been some banks for shift register + int cur_bank_number = impl.get_bank_num(); + + //TODO: think a more systematic way to keep both delay buffer and banking + //TODO: should move this into a separate function + if (cur_bank_number != 0) { + //move the shift register back in banking, from large to small + for (int b = cur_bank_number -1; b >= 0; b --) { + impl.bank_readers[b + num_banks] = impl.bank_readers.at(b); + impl.bank_readers.erase(b); + impl.bank_writers[b + num_banks] = impl.bank_writers.at(b); + impl.bank_writers.erase(b); + impl.bank_rddom[b+num_banks] = impl.bank_rddom.at(b); + for (auto& it: impl.outpt_to_bank) { + if (it.second.count(b)) { + it.second.erase(b); + it.second.insert(b+num_banks); + } + } + for (auto& it: impl.inpt_to_bank) { + if (it.second.count(b)) { + it.second.erase(b); + it.second.insert(b+num_banks); + } + } + } + } + for (auto pt : buf.get_all_ports()) { + //cout << "pt :" << pt << endl; for (int b = 0; b < num_banks; b++) { isl_set* bnk = isl_set_read_from_str(buf.ctx, curlies("Bank[" + str(b) + "]").c_str()); assert(!empty(bnk)); isl_map* bnk_map = dot(to_map(buf.access_map.at(pt)), m); + //cout << "\tBank map NO: " << b << " is " << str(bnk_map) << endl; isl_set* accesses_to_bank = its(range(bnk_map), bnk); + + //cout << "\taccess to_ bank: " << str(accesses_to_bank) << endl; if (!empty(accesses_to_bank)) { if (buf.is_out_pt(pt)) { impl.bank_readers[b].insert(pt); @@ -10361,7 +11889,7 @@ void generate_banks_garnet(CodegenOptions& options, UBuffer& buf, UBufferImpl& i cout << "After banking: " << bank_impl << endl; //take the ubuffer implementation add bank to ubuffer - for (int bank_id = 0; bank_id < bank_impl.get_bank_num(); bank_id ++) { + for (int bank_id = 0; bank_id < bank_impl.get_partition_bank_num(); bank_id ++) { isl_set* bnk = isl_set_read_from_str(buf.ctx, curlies("Bank["+str(bank_id) + "]").c_str()); auto rddom = to_uset(domain(its_range(bank_func, bnk))); cout << "rddom before its: " << str(rddom) << endl; @@ -10371,6 +11899,9 @@ void generate_banks_garnet(CodegenOptions& options, UBuffer& buf, UBufferImpl& i cout << "ADD BANK!\n Bank id: " << str(point) << endl; std::set input_sets = bank_impl.bank_writers.at(bank_id); std::set output_sets = bank_impl.bank_readers.at(bank_id); + cout << "Before grouping: " << endl; + cout << "\tinput set: " << input_sets << endl; + cout << "\toutput set: " << output_sets << endl; auto bank_IOs = buf.port_grouping(options, impl, rddom, input_sets, output_sets); for (auto bank_IO_pair: bank_IOs) { cout << "input group: " << bank_IO_pair.first << endl; @@ -10378,23 +11909,25 @@ void generate_banks_garnet(CodegenOptions& options, UBuffer& buf, UBufferImpl& i //TODO potential bug for multi bank with broad casting case //TODO bank is not a good intermediate representation and contains too much internal data // use buffer impl then - if ((bank_IO_pair.first.size() == 1) && (bank_IO_pair.second.size() == 1)) { - string inpt = pick(bank_IO_pair.first); - string outpt = pick(bank_IO_pair.second); - maybe delay_info = buf.dependence_distance_max(inpt, outpt); - assert(delay_info.has_value()); - auto bnk_info = buf.compute_bank_info(inpt, outpt, delay_info.get_value()); - buf.add_bank_between(inpt, outpt, bnk_info); - - //impl.add_new_bank_between({inpt}, {outpt}, to_set(rddom)); - } else { - auto input_sets = bank_IO_pair.first; - auto output_sets = bank_IO_pair.second; - auto bnk_info = buf.compute_bank_info(rddom, point, input_sets, output_sets); - buf.add_bank_between(input_sets, output_sets, bnk_info); - - //impl.add_new_bank_between(input_sets, output_sets, to_set(rddom)); - } + //if ((bank_IO_pair.first.size() == 1) && (bank_IO_pair.second.size() == 1)) { + // string inpt = pick(bank_IO_pair.first); + // string outpt = pick(bank_IO_pair.second); + // maybe delay_info = buf.dependence_distance_max(inpt, outpt); + // assert(delay_info.has_value()); + // auto bnk_info = buf.compute_bank_info(inpt, outpt, delay_info.get_value()); + // buf.add_bank_between(inpt, outpt, bnk_info); + + // //impl.add_new_bank_between({inpt}, {outpt}, to_set(rddom)); + //} else { + // auto input_sets = bank_IO_pair.first; + // auto output_sets = bank_IO_pair.second; + // cout << "input sets: " << input_sets << endl; + // cout << "output sets: " << output_sets << endl; + // auto bnk_info = buf.compute_bank_info(rddom, point, input_sets, output_sets); + // buf.add_bank_between(input_sets, output_sets, bnk_info); + + // //impl.add_new_bank_between(input_sets, output_sets, to_set(rddom)); + //} } //if (buf.overlap_schedule(input_sets) || buf.overlap_schedule(output_sets)) { // cout << "inputs for bank: " << input_sets << endl; @@ -10416,17 +11949,26 @@ void generate_banks_garnet(CodegenOptions& options, UBuffer& buf, UBufferImpl& i //} } } - else if (auto bank_impl = buf.get_cyclic_banking_implement(impl); - bank_impl.get_bank_num() > 1) { - //false) { + //else if (auto bank_impl = buf.get_cyclic_banking_implement(impl); + // bank_impl.get_bank_num() > 1) { + // //false) { + + else if (auto cyclic_bank = cyclic_partition(options, buf); + cyclic_bank.has_value()) { + + cout << "Use cyclic banking algorithm " << endl; + CyclicBankingImpl bank_impl(impl, cyclic_bank.get_value()); + buf.banking.partition = "cyclic"; isl_map* bank_partition_map = bank_impl.get_bank_map(buf); for (int b = 0; b < bank_impl.get_bank_num(); b++) { isl_set* bnk = isl_set_read_from_str(buf.ctx, curlies("Bank[" + str(b) + "]").c_str()); //This is rddom - isl_set* accesses_to_bank =::domain( its_range(bank_partition_map, bnk)); + isl_set* accesses_to_bank = simplify(::domain( its_range(bank_partition_map, bnk))); cout << "rddom: " << str(accesses_to_bank) << endl; //Add port + std::set input_sets;// = impl.bank_writers.at(b); + std::set output_sets;// = impl.bank_readers.at(b); for (auto pt : buf.get_all_ports()) { assert(!empty(bnk)); @@ -10435,20 +11977,24 @@ void generate_banks_garnet(CodegenOptions& options, UBuffer& buf, UBufferImpl& i //cout << "bank map: " << str(bnk_map) << endl; if (!empty(bnk_map)) { if (buf.is_out_pt(pt)) { - impl.bank_readers[b].insert(pt); - impl.outpt_to_bank[pt].insert(b); + output_sets.insert(pt); + //impl.bank_readers[b].insert(pt); + //impl.outpt_to_bank[pt].insert(b); } else { - impl.bank_writers[b].insert(pt); - impl.inpt_to_bank[pt].insert(b); + input_sets.insert(pt); + //impl.bank_writers[b].insert(pt); + //impl.inpt_to_bank[pt].insert(b); } } } cout << "ADD BANK!\n Bank id: " << b << endl; - std::set input_sets = impl.bank_writers.at(b); - std::set output_sets = impl.bank_readers.at(b); + cout << "bank impl before port group: " << impl << endl; + cout << "Before grouping: " << endl; + cout << "\tinput set: " << input_sets << endl; + cout << "\toutput set: " << output_sets << endl; + auto rddom = coalesce(its(to_uset(accesses_to_bank), buf.global_range())); auto bank_IOs = buf.port_grouping(options, impl, - to_uset(accesses_to_bank), - input_sets, output_sets); + rddom, input_sets, output_sets); } cout << impl << endl; } @@ -10461,8 +12007,8 @@ void generate_banks_garnet(CodegenOptions& options, UBuffer& buf, UBufferImpl& i auto outpts = buf.get_out_ports(); std::set in_port_set = std::set(inpts.begin(), inpts.end()); std::set out_port_set = std::set(outpts.begin(), outpts.end()); - auto bnk_info = buf.compute_bank_info(in_port_set, out_port_set); - buf.add_bank_between(in_port_set, out_port_set, bnk_info); + //auto bnk_info = buf.compute_bank_info(in_port_set, out_port_set); + //buf.add_bank_between(in_port_set, out_port_set, bnk_info); int impl_bank = impl.add_new_bank_between(in_port_set, out_port_set, to_set(buf.global_range())); cout << "IO of ubuffer: " << in_port_set << out_port_set << endl; impl.sequentially_assign_inpt(buf.sort_pt_by_bundle(in_port_set), impl_bank); @@ -10471,7 +12017,9 @@ void generate_banks_garnet(CodegenOptions& options, UBuffer& buf, UBufferImpl& i else { cout << "Use exhaustive banking! " << endl; - buf.generate_banks_and_merge(options); + + //This function may stuck in double buffer case + buf.generate_banks(options); buf.parse_exhaustive_banking_into_impl(impl); cout << "After exhaustive banking:\n " << impl << endl; //cout << "CANNOT support by current banking strategies!" << endl; diff --git a/ubuffer.h b/ubuffer.h index 09c0faf46..251cffe5f 100644 --- a/ubuffer.h +++ b/ubuffer.h @@ -10,46 +10,6 @@ using namespace std; -template -std::ostream& operator<< (std::ostream& out, const std::pair& v) { - out << "{" << v.first << ", " << v.second << "} "; - return out; -} - -template -std::ostream& operator<< (std::ostream& out, const std::vector& v) { - if ( !v.empty() ) { - out << '['; - std::copy (v.begin(), v.end(), std::ostream_iterator(out, ", ")); - out << "\b\b]"; - } - return out; -} - -template -std::ostream& operator<< (std::ostream& out, const std::set& v) { - if ( !v.empty() ) { - out << '{'; - std::copy (v.begin(), v.end(), std::ostream_iterator(out, ", ")); - out << "\b\b}"; - } - return out; -} - -template -std::ostream& operator<< (std::ostream& out, const std::map& m) { - if ( !m.empty() ) { - for (const auto &p : m) - { - out << p.first << ": "; - out << p.second << ' '; - out << std::endl; - } - - } - return out; -} - //This is assuming read after write if they are scheduled //for the same hardware cycle umap* schedule_guard(umap* sched, bool is_rd); @@ -395,6 +355,180 @@ class AccessPattern { return ret; } + //A dimension that project out should be captured in the next level memory + isl_map* get_access_map_and_decouple_reuse(isl_ctx* ctx, int dim_id, std::set proj_dim) { + vector var_list(var_dim-1); + for (auto itr: name2idx) { + if (itr.first == "const") + continue; + var_list[itr.second-1] = itr.first; + } + var_list[0] = "root=0"; + auto vars = sep_list(var_list, "[", "]", "," ); + vector nd_expr; + for (size_t row_cnt = 0; row_cnt < access_matrix.size(); row_cnt ++) { + auto row = access_matrix[row_cnt]; + vector sum_list; + for(auto itr = row.begin() + 1; itr != row.end(); itr ++) { + //skip const. + int item = *itr; + int cnt = itr - row.begin() - 1; + if (item == 0) + continue; + //all dimension above the vectorization dimension should be factor out + if (row_cnt < dim_id) { + nd_expr.push_back(get_expr(item, cnt, var_list)); + } + else { + if(proj_dim.count(cnt)) { + cout << "\t push var in decouple dimension: " << cnt << get_expr(item, cnt, var_list) << endl; + nd_expr.push_back(get_expr(item, cnt, var_list)); + } else { + sum_list.push_back(get_expr(item, cnt, var_list)); + } + } + } + if (row_cnt >= dim_id) { + //only add const offset when it inside the vectorize dimension const + if (sum_list.size() == 0 || (row.front() != 0)) { + sum_list.push_back(std::to_string(row.front())); + } + nd_expr.push_back(sep_list(sum_list, "", "", "+")); + } + else { + if (sum_list.size() == 0 || (row.front() != 0)) + //TODO: check the following expr may work + //if ( row.front() != 0) + nd_expr.push_back(std::to_string(row.front())); + } + } + string nd_expr_str = sep_list(nd_expr, "[", "]", ", "); + cout << "access map expr:" << nd_expr_str << endl; + auto access_map = isl_map_read_from_str(ctx, string("{ " + op_name + vars + " -> " + buf_name + nd_expr_str + "}").c_str()); + auto domain = get_domain(ctx); + cout << "domain: " << str(domain) << "\naccess map: " << str(access_map) << endl; + return its(access_map, domain); + } + + //A dimension that project out should be captured in the next level memory + isl_map* get_access_map_and_decouple_reuse(isl_ctx* ctx, int dim_id, int vec_dim, std::set proj_dim) { + vector var_list(var_dim-1); + for (auto itr: name2idx) { + if (itr.first == "const") + continue; + var_list[itr.second-1] = itr.first; + } + var_list[0] = "root=0"; + auto vars = sep_list(var_list, "[", "]", "," ); + vector nd_expr; + for (size_t row_cnt = 0; row_cnt < access_matrix.size(); row_cnt ++) { + auto row = access_matrix[row_cnt]; + vector sum_list; + for(auto itr = row.begin() + 1; itr != row.end(); itr ++) { + //skip const. + int item = *itr; + int cnt = itr - row.begin() - 1; + if (item == 0) + continue; + //all dimension above the vectorization dimension should be factor out + if (row_cnt < dim_id) { + nd_expr.push_back(get_expr(item, cnt, var_list)); + } + else { + if (cnt >= vec_dim) { + sum_list.push_back(get_expr(item, cnt, var_list)); + } else if(proj_dim.count(cnt)) { + cout << "\t push var in accumulate list: " << cnt << get_expr(item, cnt, var_list) << endl; + sum_list.push_back(get_expr(item, cnt, var_list)); + } else { + nd_expr.push_back(get_expr(item, cnt, var_list)); + } + } + } + if (row_cnt >= dim_id) { + //only add const offset when it inside the vectorize dimension const + if (sum_list.size() == 0 || (row.front() != 0)) { + sum_list.push_back(std::to_string(row.front())); + } + nd_expr.push_back(sep_list(sum_list, "", "", "+")); + } + else { + if (sum_list.size() == 0 || (row.front() != 0)) + //TODO: check the following expr may work + //if ( row.front() != 0) + nd_expr.push_back(std::to_string(row.front())); + } + } + string nd_expr_str = sep_list(nd_expr, "[", "]", ", "); + cout << "access map expr:" << nd_expr_str << endl; + auto access_map = isl_map_read_from_str(ctx, string("{ " + op_name + vars + " -> " + buf_name + nd_expr_str + "}").c_str()); + auto domain = get_domain(ctx); + cout << "domain: " << str(domain) << "\naccess map: " << str(access_map) << endl; + return its(access_map, domain); + } + + isl_map* get_access_map_and_decouple_reuse(isl_ctx* ctx, int dim_id, int vec_dim) { + vector var_list(var_dim-1); + for (auto itr: name2idx) { + if (itr.first == "const") + continue; + var_list[itr.second-1] = itr.first; + } + var_list[0] = "root=0"; + auto vars = sep_list(var_list, "[", "]", "," ); + vector nd_expr; + for (size_t row_cnt = 0; row_cnt < access_matrix.size(); row_cnt ++) { + auto row = access_matrix[row_cnt]; + vector sum_list; + for(auto itr = row.begin() + 1; itr != row.end(); itr ++) { + //skip const. + int item = *itr; + int cnt = itr - row.begin() - 1; + if (item == 0) + continue; + if (row_cnt < dim_id) { + nd_expr.push_back(get_expr(item, cnt, var_list)); + } + else { + if (cnt < vec_dim) { + nd_expr.push_back(get_expr(item, cnt, var_list)); + } else { + sum_list.push_back(get_expr(item, cnt, var_list)); + } + } + } + if (row_cnt >= dim_id) { + //only add const offset when it inside the vectorize dimension const + if (sum_list.size() == 0 || (row.front() != 0)) { + sum_list.push_back(std::to_string(row.front())); + } + nd_expr.push_back(sep_list(sum_list, "", "", "+")); + } + else { + if (sum_list.size() == 0 || (row.front() != 0)) + //TODO: check the following expr may work + //if ( row.front() != 0) + nd_expr.push_back(std::to_string(row.front())); + } + } + ////auto tb_pad = get_reaccess_dim_non_vectorized(dim_id); + //auto tb_pad = get_non_inner_most_reaccess_dim(); + //cout << "tb pad dim: " << tb_pad << endl; + //for (auto cnt: tb_pad) { + // if (cnt == 0) + // continue; + // auto it = nd_expr.begin(); + // //get_expr(stride, id, all the var) + // nd_expr.insert(it, get_expr(1, cnt, var_list)); + //} + string nd_expr_str = sep_list(nd_expr, "[", "]", ", "); + cout << "access map expr:" << nd_expr_str << endl; + auto access_map = isl_map_read_from_str(ctx, string("{ " + op_name + vars + " -> " + buf_name + nd_expr_str + "}").c_str()); + auto domain = get_domain(ctx); + cout << "domain: " << str(domain) << "\naccess map: " << str(access_map) << endl; + return its(access_map, domain); + } + isl_map* get_access_map_and_decouple_reuse(isl_ctx* ctx, int dim_id, bool rm_const=false) { vector var_list(var_dim-1); for (auto itr: name2idx) { @@ -920,6 +1054,7 @@ struct MemConnSch { //TODO put this into separate header struct UBufferImpl; +struct GarnetImpl; struct EmbarrassingBankingImpl; struct CyclicBankingImpl; struct dgraph; @@ -1072,6 +1207,46 @@ class UBuffer { return pt_vec; } + void sequentially_rename_output_domain_suffix(int starting_idx) { + int outbd_cnt = starting_idx; + for (string outbd: get_out_bundles()) { + for (string pt: port_bundles.at(outbd)) { + auto dom = domain.at(pt); + string dom_name = ::name(dom); + vector substr = + split_at(dom_name, "_"); + substr.pop_back(); + substr.push_back(str(outbd_cnt)); + string new_name = sep_list(substr, "", "", "_"); + domain.at(pt) = set_name(dom, new_name); + schedule.at(pt) = set_domain_name(schedule.at(pt), new_name); + access_map.at(pt) = set_domain_name(access_map.at(pt), new_name); + } + outbd_cnt ++; + } + + } + + void sequentially_rename_input_domain_suffix(int starting_idx) { + int inbd_cnt = starting_idx; + for (string inbd: get_in_bundles()) { + for (string pt: port_bundles.at(inbd)) { + auto dom = domain.at(pt); + string dom_name = ::name(dom); + vector substr = + split_at(dom_name, "_"); + substr.pop_back(); + substr.push_back(str(inbd_cnt)); + string new_name = sep_list(substr, "", "", "_"); + domain.at(pt) = set_name(dom, new_name); + schedule.at(pt) = set_domain_name(schedule.at(pt), new_name); + access_map.at(pt) = set_domain_name(access_map.at(pt), new_name); + } + inbd_cnt ++; + } + + } + size_t get_wr_cycle() { auto pt_vec = get_bd_in_ports(); return pt_vec.size() / hardware.in_port_width; @@ -1935,6 +2110,8 @@ std::set get_bank_unique_outputs(const std::string& name) const { } } + + //FIXME: this is a heuristic, it's overaproximation, may not be the unroll std::set get_unroll_dimensions() { //Find the unrolling dimension std::set addr_need_tight; @@ -1951,30 +2128,61 @@ std::set get_bank_unique_outputs(const std::string& name) const { return addr_need_tight; } + //dimension are fully unrolled + std::set get_fully_unroll_dimensions() { + //Find the unrolling dimension + std::set fully_unrolled_dim; + for (auto it: access_map) { + auto am = to_map(it.second); + isl_set* addr_range = range(am); + int addr_dim = ::num_dims(addr_range); + for (int i = 0; i < addr_dim; i ++) { + int dom_rng = get_domain_range(addr_range, i); + if (dom_rng == 1) + fully_unrolled_dim.insert(i); + } + } + cout << "addr dim fully unrolled: " << fully_unrolled_dim << endl; + return fully_unrolled_dim; + } + CyclicBankingImpl get_cyclic_banking_implement(UBufferImpl & impl); //return a vector size equals to dimension vector get_cyclic_banking_factors() { vector cyclic_banking_factors(num_dims(), 1); + std::set addr_need_tight = get_unroll_dimensions(); for (int addr_dim: addr_need_tight) { int cms_in = 0, cms_out = 0; for (auto inpt: get_in_ports()) { auto am = to_map(access_map.at(inpt)); - cout << str(am) << endl; + //cout << str(am) << endl; cms_in = std::gcd(cms_in, common_max_stride(am, addr_dim)); - cout << "cms in: " << cms_out << endl; + //cout << "cms in: " << cms_out << endl; } for (auto outpt: get_out_ports()) { auto am = to_map(access_map.at(outpt)); - cout << str(am) << endl; + //cout << str(am) << endl; cms_out = std::gcd(cms_out, common_max_stride(am, addr_dim)); - cout << "cms out: " << cms_out << endl; + //cout << "cms out: " << cms_out << endl; } cyclic_banking_factors.at(addr_dim) = std::max(cms_in, cms_out); } - cout << cyclic_banking_factors << endl; + + //TODO: Fully unrolled dimension should be caught by cyclic banking, + //we may not need embarassing banking at all + std::set addr_fully_unrolled = get_fully_unroll_dimensions(); + auto gb_domain= to_set(global_range()); + for (int addr_dim: addr_fully_unrolled) { + int banking_factor = get_domain_range(gb_domain, addr_dim); + if (banking_factor != 1) { + cyclic_banking_factors.at(addr_dim) = banking_factor; + } + } + + cout << "Cyclic banking factors: " << cyclic_banking_factors << endl; return cyclic_banking_factors; } @@ -1984,8 +2192,10 @@ void tighten_address_space() { for(int addr_dim: addr_need_tight) { int cms = 0; for (auto it: access_map) { - auto am = to_map(it.second); - cms = std::gcd(cms, common_max_stride(am, addr_dim)); + auto am = coalesce(to_map(it.second)); + auto am_cms = common_max_stride(am, addr_dim); + //cout << "\t common max stride for am: " << str(am) << endl << "\t" << am_cms << endl; + cms = std::gcd(cms, am_cms); } cout << "common max stride = " << cms << endl; if (cms > 1) { @@ -2168,6 +2378,7 @@ void tighten_address_space() { isl_union_map* global_schedule() const { umap* s = isl_union_map_read_from_str(ctx, "{ }"); + //umap* s = (pick(schedule).second); for (auto other : schedule) { s = unn(s, (cpy(other.second))); } @@ -2194,6 +2405,16 @@ void tighten_address_space() { return s; } + isl_union_map* global_in_schedule_with_guard() const { + umap* s = isl_union_map_read_from_str(ctx, "{ }"); + for (auto other : schedule) { + if (isIn.at(other.first)) { + s = unn(s, (schedule_guard(cpy(other.second), false))); + } + } + return s; + } + isl_union_map* producer_map() { umap* s = isl_union_map_read_from_str(ctx, "{ }"); for (auto pt: get_in_ports()) { @@ -2535,6 +2756,23 @@ void tighten_address_space() { return to_map(dot(origin_map, buf_map)); } + void remap_access_to_new_buffer_name(string new_name) { + for (auto it: access_map) { + access_map.at(it.first) = + to_umap(set_range_name(to_map(it.second), new_name)); + } + name = new_name; + } + + map get_stmt2sched() const { + map ret; + for (auto it: schedule) { + auto sched = it.second; + ret[domain_name(sched)] = sched; + } + return ret; + } + map > get_stmt2bd() const { map > stmt2bd; for (auto it: schedule) { @@ -2546,6 +2784,24 @@ void tighten_address_space() { return stmt2bd; } + bool has_update_op() const { + map > stmt2bd = get_stmt2bd(); + for (auto it: stmt2bd) { + int in_bd = 0, out_bd = 0; + for (string bd: it.second) { + if (is_input_bundle(bd)) { + in_bd ++; + } else if (is_output_bundle(bd)) { + out_bd ++; + } + + } + if (in_bd && out_bd) + return true; + } + return false; + } + bool is_update_op(string op_name) const { //update stmt has 2 bundles auto stmt2bd = get_stmt2bd(); @@ -2634,6 +2890,19 @@ void tighten_address_space() { return cap; } + void remove_redundant_dim() { + for (auto pt: get_all_ports()) { + auto am = to_map(access_map.at(pt)); + am = remove_irrelevant_in_dim(am); + access_map.at(pt) = to_umap(am); + domain.at(pt) = ::domain(am); + + auto sched = to_map(schedule.at(pt)); + sched = remove_irrelevant_in_dim(sched); + schedule.at(pt) = to_umap(sched); + } + } + umap* pad_dom_buf2op(AccessPattern , umap* , int); isl_map* pad_dom_sched(AccessPattern , isl_map* , int); @@ -2646,6 +2915,9 @@ void tighten_address_space() { bool merge_small_dim(int fetch_width); void merge_out_bundle(); + //Preprocessing pass for generate configuration + void simplify_floor_div_expr(); + bool overlap_schedule(std::set & ptset); //change the input and output and return the agg and tb ubuffer stucture @@ -2715,13 +2987,16 @@ void tighten_address_space() { //kernel function for generate coreir void generate_coreir(CodegenOptions& options, UBufferImpl& impl, CoreIR::ModuleDef* def, schedule_info& info, bool with_ctrl=true); + void generate_coreir_refactor(CodegenOptions& options, UBufferImpl& impl, CoreIR::ModuleDef* def, schedule_info& info, bool with_ctrl=true); //helper function for sreg generation void generate_sreg_and_wire(CodegenOptions& options, UBufferImpl& impl, CoreIR::ModuleDef* def, map & pt2wire); + void generate_fanin_connection(CodegenOptions& options, UBufferImpl& impl, CoreIR::ModuleDef* def, map & pt2wire); //helper function for wire IO connection void wire_ubuf_IO(CodegenOptions& options, CoreIR::ModuleDef* def, map & pt2wire, CoreIR::Instance* buf, UBufferImpl & impl, schedule_info& info, int bank_id, bool with_ctrl); //Helper function for generate cgra mem instance CoreIR::Instance* map_ubuffer_to_cgra(CodegenOptions& options, CoreIR::ModuleDef* def, UBuffer& target_buf, string config_mode); + CoreIR::Instance* map_ubuffer_to_cgra(CodegenOptions& options, CoreIR::ModuleDef* def, GarnetImpl& hw_impl); //Helper function for generate pond instance //optimization pass for accumulation register insert @@ -2751,6 +3026,7 @@ void tighten_address_space() { CoreIR::ModuleDef* def, CodegenOptions options, string ub_ins_name, + string config_mode, size_t input_num, size_t output_num); void emit_lake_config_collateral(CodegenOptions options, string dir); @@ -2920,6 +3196,9 @@ void emit_lake_address_stream2file_new(CodegenOptions &options, map read_cycle, vector write_cycle, vector > read_addr, vector > write_addr, int input_width, int output_width); +void lower_to_garnet_implementation(CodegenOptions& options, + UBuffer& buf, UBufferImpl& impl, schedule_info& info); + int compute_max_dd(UBuffer& buf, const string& inpt); //The current vectorization method that was using @@ -2949,9 +3228,9 @@ vector buffer_vectorization(vector buf_name_vec, int dim_id, int //helper function for the new vectorization pass pair get_vectorized_write(isl_map* acc_0, isl_map* sched, map sched_record_map, int fetch_width, int addr_dim, int agg_cnt=0); pair get_vectorized_read(isl_map* acc_0, isl_map* sched, map sched_record_map, int fetch_width, int addr_dim, bool is_dual_port = false); -pair get_vectorized_read_simplified(isl_map* acc_0, isl_map* sched, map sched_record_map, int fetch_width, int addr_dim, bool is_dual_port = false); +pair get_vectorized_read_simplified(isl_map* acc_0, isl_map* sched, map sched_record_map, int fetch_width, int addr_dim, int& vectorized_dim, bool is_dual_port = false); //Helper function to get schedule -isl_map* get_sram2tb_schedule_with_check(isl_map* out_sched, map sched_map, int ahead_step, int vectorize_loop_dim, bool is_dual_port); +isl_map* get_sram2tb_schedule_with_check(isl_map* out_sched, map sched_map, int ahead_step, int vectorize_loop_dim, int offset, bool is_dual_port); @@ -3073,6 +3352,7 @@ UBuffer delete_ports(std::set& sr_ports, UBuffer& buf); struct dgraph { std::set nodes; + map > fanin_edges; map > out_edges; map, int> weights; @@ -3083,6 +3363,14 @@ struct dgraph { weights[{src, dst}] = weight; } + void add_fanin_edge(const std::string& src, const std::string& dst, const int weight) { + nodes.insert(dst); + nodes.insert(src); + fanin_edges[dst].insert(src); + weights[{src, dst}] = weight; + cout << "Add weight from " << src << "->" << dst << ": " << weight << endl; + } + int weight(const std::string& src, const std::string& dst) { if(weights.find({src,dst}) == weights.end()){ return -1; @@ -3153,6 +3441,19 @@ struct dgraph { } }; +struct GarnetImpl { + string config_mode; + UBuffer target_buf; + map sub_component; //if we do vectorization + + bool insert_shift_register = false; + UBuffer accum_reg; + string reduce_PE_inpt, reduce_PE_outpt; + + bool substract_glb_latency; + bool decouple_ctrl; + isl_map* cgpl_schedule; +}; struct UBufferImpl { @@ -3166,18 +3467,29 @@ struct UBufferImpl { //input selection(TODO: did not support this feature) map> > bank_inpt2writers; + map lowering_info; + map> outpt_to_bank; //output chaining map> inpt_to_bank; //input broadcasting //Shift register data map shift_depth; map> shift_registered_outputs; + map>> fanin_outputs; vector>> shift_registered_outputs_to_outputs; int get_new_bank_id() { - return bank_rddom.size(); + //Get the max bank id, nothing inside will return 0 + int max_id = -1; + for (auto it: bank_rddom) { + max_id = std::max(max_id, it.first); + } + return max_id + 1; } + string get_buf_name() { + return ::name(pick(bank_rddom).second); + } void sequentially_assign_inpt(vector inpts, int b) { vector> partition; @@ -3245,6 +3557,10 @@ struct UBufferImpl { ); } + void add_fanin_info(const string& inpt, const string& outpt, const int& delay) { + map_insert(fanin_outputs, outpt, {inpt, delay}); + } + void add_i2o_info(const string& inpt, const string& outpt, const int& delay) { shift_registered_outputs[outpt] = make_pair(inpt, delay); } @@ -3279,15 +3595,38 @@ struct UBufferImpl { //Banking merging related function void remove_bank(int bank_id); void merge_banks(vector banks_tobe_merged); + void merge_banks_and_rewrite(vector & banks_tobe_merged); void conditional_merging(CodegenOptions & options, const vector & banks_tobe_merged); void bank_merging(CodegenOptions & options); + void bank_merging_and_rewrite(CodegenOptions & options); + void sort_bank_port(); void sanity_check_memory_hierarchy(CodegenOptions& options, const vector & banks); + int get_bank_capacity(int bank_id) const { + int capacity_without_circular_buf = + int_upper_bound(card(to_uset(bank_rddom.at(bank_id)))); + auto bank_read_set = bank_readers.at(bank_id); + int shift_register_depth = -1; + for (string read_pt: bank_read_set) { + if (shift_registered_outputs.count(read_pt)) { + shift_register_depth = std::max(shift_register_depth, + shift_registered_outputs.at(read_pt).second); + } + } + if ((shift_register_depth != -1) + && (shift_register_depth < capacity_without_circular_buf)) { + return shift_register_depth; + } else { + return capacity_without_circular_buf; + } + } + string get_memory_hierarchy(CodegenOptions& options, int bank_id) { - int capacity = int_upper_bound(card(to_uset(bank_rddom.at(bank_id)))); + //int capacity = int_upper_bound(card(to_uset(bank_rddom.at(bank_id)))); + int capacity = get_bank_capacity(bank_id); auto mem_hierarchy = options.mem_hierarchy; - cout << "mem hierarchy size: " << mem_hierarchy.size() << endl; + //cout << "mem hierarchy size: " << mem_hierarchy.size() << endl; if (mem_hierarchy.count("regfile") == 0) return "mem"; vector > mem_vec(mem_hierarchy.begin(), mem_hierarchy.end()); @@ -3319,6 +3658,14 @@ struct UBufferImpl { outpts.insert(it.first); } + for (auto it: fanin_outputs) { + outpts.insert(it.first); + cout << tab(2) << it.first << " has fanin: " << endl; + for (auto p : it.second) { + cout << tab(4) << p.first << "->" << p.second << endl; + } + } + return outpts; } @@ -3348,13 +3695,10 @@ struct UBufferImpl { } int get_bank_num() const { - int cnt = 0; - for (auto it: bank_readers) { - cnt ++; - } - return cnt; + return bank_readers.size(); } + void print_info(std::ostream& out) const { out << "Bank writers: " << endl; for (auto it: bank_writers) { @@ -3388,7 +3732,8 @@ struct EmbarrassingBankingImpl: public UBufferImpl { EmbarrassingBankingImpl() {} EmbarrassingBankingImpl(UBufferImpl const & impl) : UBufferImpl(impl) {} - int get_bank_num() const { + //Embarrassing banking intialize from exhaustive banking + int get_partition_bank_num() const { int bank_num = 1; for (auto it: partitioned_dimension_extents) { bank_num *= it.second; @@ -3423,6 +3768,7 @@ struct CyclicBankingImpl: public UBufferImpl { return bank_num; } + isl_map* get_bank_map(UBuffer& buf) const { //iteration domain to bank id vector dvs; @@ -3475,6 +3821,14 @@ map > determine_shift_reg_map( UBuffer& buf, schedule_info& hwinfo); +//This method consider multiple input port feed into one output +map > > determine_shift_reg_map_new( + prog& prg, + UBuffer& buf, + schedule_info& hwinfo); + +int get_vector_fetch_loop_ii(umap* in_sched); +bool violate_deps(isl_map* temp_sched, map sched_map); dgraph build_in_to_out_shift_register_graph(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo); dgraph build_shift_registers(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo); UBufferImpl port_group2bank(CodegenOptions& options, prog& prg, UBuffer& buf, schedule_info& hwinfo); diff --git a/unsharp_large_compute.h b/unsharp_large_compute.h new file mode 100644 index 000000000..4b257dd31 --- /dev/null +++ b/unsharp_large_compute.h @@ -0,0 +1,834 @@ +#pragma once +#include "hw_classes.h" +#include "clockwork_standard_compute_units.h" + + +//store is: hw_input_global_wrapper.glb.stencil(0, hw_input_global_wrapper_s0_x_x, ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(0, (hw_input_global_wrapper_s0_x_x + ((0*126) + -3)), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_1 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_1; +} + +//store is: hw_input_global_wrapper.glb.stencil(1, hw_input_global_wrapper_s0_x_x, ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(1, (hw_input_global_wrapper_s0_x_x + ((0*126) + -3)), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_1(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_2 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_2; +} + +//store is: hw_input_global_wrapper.glb.stencil(2, hw_input_global_wrapper_s0_x_x, ((hw_input_global_wrapper_s0_y + -3) + 3)) = hw_input.stencil(2, (hw_input_global_wrapper_s0_x_x + ((0*126) + -3)), (hw_input_global_wrapper_s0_y + -3)) +hw_uint<16> hcompute_hw_input_global_wrapper_glb_stencil_2(hw_uint<16>& hw_input_stencil) { + uint16_t _hw_input_stencil_3 = (uint16_t) hw_input_stencil.extract<0, 15>(); + + return _hw_input_stencil_3; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(0, hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(0, hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_1 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_1; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(1, hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(1, hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_1(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_2 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_2; +} + +//store is: hw_input_global_wrapper_global_wrapper.stencil(2, hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) = hw_input_global_wrapper.glb.stencil(2, hw_input_global_wrapper_global_wrapper_s0_x_x, ((hw_input_global_wrapper_global_wrapper_s0_y + -3) + 3)) +hw_uint<16> hcompute_hw_input_global_wrapper_global_wrapper_stencil_2(hw_uint<16>& hw_input_global_wrapper_glb_stencil) { + uint16_t _hw_input_global_wrapper_glb_stencil_3 = (uint16_t) hw_input_global_wrapper_glb_stencil.extract<0, 15>(); + + return _hw_input_global_wrapper_glb_stencil_3; +} + +//store is: gray.stencil(gray_s0_x_x, ((gray_s0_y + -3) + 3)) = (((hw_input_global_wrapper_global_wrapper.stencil(1, gray_s0_x_x, ((gray_s0_y + -3) + 3))*(uint16)150) + ((hw_input_global_wrapper_global_wrapper.stencil(2, gray_s0_x_x, ((gray_s0_y + -3) + 3))*(uint16)29) + (hw_input_global_wrapper_global_wrapper.stencil(0, gray_s0_x_x, ((gray_s0_y + -3) + 3))*(uint16)77)))/(uint16)256) +hw_uint<16> hcompute_gray_stencil(hw_uint<48>& hw_input_global_wrapper_global_wrapper_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_1 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_2 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<16, 31>(); + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_3 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<32, 47>(); + + uint16_t _421 = (uint16_t)(150); + uint16_t _422 = _hw_input_global_wrapper_global_wrapper_stencil_1 * _421; + uint16_t _423 = (uint16_t)(29); + uint16_t _424 = _hw_input_global_wrapper_global_wrapper_stencil_2 * _423; + uint16_t _425 = (uint16_t)(77); + uint16_t _426 = _hw_input_global_wrapper_global_wrapper_stencil_3 * _425; + uint16_t _427 = _424 + _426; + uint16_t _428 = _422 + _427; + uint16_t _429 = (uint16_t)(8); + uint16_t _430 = _428 >> _429; + return _430; +} + +//store is: reciprocal.stencil(reciprocal_s0_x_x, reciprocal_s0_y) = rom_div_lookupa0[(int32(max(gray.stencil((reciprocal_s0_x_x + 3), (reciprocal_s0_y + 3)), (uint16)1)) + -1)] +hw_uint<16> hcompute_reciprocal_stencil(hw_uint<16>& gray_stencil) { + uint16_t _gray_stencil_1 = (uint16_t) gray_stencil.extract<0, 15>(); + + uint16_t _rom_div_lookupa0[255]; + // produce rom_div_lookupa0 + uint16_t _711 = (uint16_t)(256); + _rom_div_lookupa0[0] = _711; + uint16_t _712 = (uint16_t)(128); + _rom_div_lookupa0[1] = _712; + uint16_t _713 = (uint16_t)(85); + _rom_div_lookupa0[2] = _713; + uint16_t _714 = (uint16_t)(64); + _rom_div_lookupa0[3] = _714; + uint16_t _715 = (uint16_t)(51); + _rom_div_lookupa0[4] = _715; + uint16_t _716 = (uint16_t)(42); + _rom_div_lookupa0[5] = _716; + uint16_t _717 = (uint16_t)(36); + _rom_div_lookupa0[6] = _717; + uint16_t _718 = (uint16_t)(32); + _rom_div_lookupa0[7] = _718; + uint16_t _719 = (uint16_t)(28); + _rom_div_lookupa0[8] = _719; + uint16_t _720 = (uint16_t)(25); + _rom_div_lookupa0[9] = _720; + uint16_t _721 = (uint16_t)(23); + _rom_div_lookupa0[10] = _721; + uint16_t _722 = (uint16_t)(21); + _rom_div_lookupa0[11] = _722; + uint16_t _723 = (uint16_t)(19); + _rom_div_lookupa0[12] = _723; + uint16_t _724 = (uint16_t)(18); + _rom_div_lookupa0[13] = _724; + uint16_t _725 = (uint16_t)(17); + _rom_div_lookupa0[14] = _725; + uint16_t _726 = (uint16_t)(16); + _rom_div_lookupa0[15] = _726; + uint16_t _727 = (uint16_t)(15); + _rom_div_lookupa0[16] = _727; + uint16_t _728 = (uint16_t)(14); + _rom_div_lookupa0[17] = _728; + uint16_t _729 = (uint16_t)(13); + _rom_div_lookupa0[18] = _729; + uint16_t _730 = (uint16_t)(12); + _rom_div_lookupa0[19] = _730; + uint16_t _731 = (uint16_t)(12); + _rom_div_lookupa0[20] = _731; + uint16_t _732 = (uint16_t)(11); + _rom_div_lookupa0[21] = _732; + uint16_t _733 = (uint16_t)(11); + _rom_div_lookupa0[22] = _733; + uint16_t _734 = (uint16_t)(10); + _rom_div_lookupa0[23] = _734; + uint16_t _735 = (uint16_t)(10); + _rom_div_lookupa0[24] = _735; + uint16_t _736 = (uint16_t)(9); + _rom_div_lookupa0[25] = _736; + uint16_t _737 = (uint16_t)(9); + _rom_div_lookupa0[26] = _737; + uint16_t _738 = (uint16_t)(9); + _rom_div_lookupa0[27] = _738; + uint16_t _739 = (uint16_t)(8); + _rom_div_lookupa0[28] = _739; + uint16_t _740 = (uint16_t)(8); + _rom_div_lookupa0[29] = _740; + uint16_t _741 = (uint16_t)(8); + _rom_div_lookupa0[30] = _741; + uint16_t _742 = (uint16_t)(8); + _rom_div_lookupa0[31] = _742; + uint16_t _743 = (uint16_t)(7); + _rom_div_lookupa0[32] = _743; + uint16_t _744 = (uint16_t)(7); + _rom_div_lookupa0[33] = _744; + uint16_t _745 = (uint16_t)(7); + _rom_div_lookupa0[34] = _745; + uint16_t _746 = (uint16_t)(7); + _rom_div_lookupa0[35] = _746; + uint16_t _747 = (uint16_t)(6); + _rom_div_lookupa0[36] = _747; + uint16_t _748 = (uint16_t)(6); + _rom_div_lookupa0[37] = _748; + uint16_t _749 = (uint16_t)(6); + _rom_div_lookupa0[38] = _749; + uint16_t _750 = (uint16_t)(6); + _rom_div_lookupa0[39] = _750; + uint16_t _751 = (uint16_t)(6); + _rom_div_lookupa0[40] = _751; + uint16_t _752 = (uint16_t)(6); + _rom_div_lookupa0[41] = _752; + uint16_t _753 = (uint16_t)(5); + _rom_div_lookupa0[42] = _753; + uint16_t _754 = (uint16_t)(5); + _rom_div_lookupa0[43] = _754; + uint16_t _755 = (uint16_t)(5); + _rom_div_lookupa0[44] = _755; + uint16_t _756 = (uint16_t)(5); + _rom_div_lookupa0[45] = _756; + uint16_t _757 = (uint16_t)(5); + _rom_div_lookupa0[46] = _757; + uint16_t _758 = (uint16_t)(5); + _rom_div_lookupa0[47] = _758; + uint16_t _759 = (uint16_t)(5); + _rom_div_lookupa0[48] = _759; + uint16_t _760 = (uint16_t)(5); + _rom_div_lookupa0[49] = _760; + uint16_t _761 = (uint16_t)(5); + _rom_div_lookupa0[50] = _761; + uint16_t _762 = (uint16_t)(4); + _rom_div_lookupa0[51] = _762; + uint16_t _763 = (uint16_t)(4); + _rom_div_lookupa0[52] = _763; + uint16_t _764 = (uint16_t)(4); + _rom_div_lookupa0[53] = _764; + uint16_t _765 = (uint16_t)(4); + _rom_div_lookupa0[54] = _765; + uint16_t _766 = (uint16_t)(4); + _rom_div_lookupa0[55] = _766; + uint16_t _767 = (uint16_t)(4); + _rom_div_lookupa0[56] = _767; + uint16_t _768 = (uint16_t)(4); + _rom_div_lookupa0[57] = _768; + uint16_t _769 = (uint16_t)(4); + _rom_div_lookupa0[58] = _769; + uint16_t _770 = (uint16_t)(4); + _rom_div_lookupa0[59] = _770; + uint16_t _771 = (uint16_t)(4); + _rom_div_lookupa0[60] = _771; + uint16_t _772 = (uint16_t)(4); + _rom_div_lookupa0[61] = _772; + uint16_t _773 = (uint16_t)(4); + _rom_div_lookupa0[62] = _773; + uint16_t _774 = (uint16_t)(4); + _rom_div_lookupa0[63] = _774; + uint16_t _775 = (uint16_t)(3); + _rom_div_lookupa0[64] = _775; + uint16_t _776 = (uint16_t)(3); + _rom_div_lookupa0[65] = _776; + uint16_t _777 = (uint16_t)(3); + _rom_div_lookupa0[66] = _777; + uint16_t _778 = (uint16_t)(3); + _rom_div_lookupa0[67] = _778; + uint16_t _779 = (uint16_t)(3); + _rom_div_lookupa0[68] = _779; + uint16_t _780 = (uint16_t)(3); + _rom_div_lookupa0[69] = _780; + uint16_t _781 = (uint16_t)(3); + _rom_div_lookupa0[70] = _781; + uint16_t _782 = (uint16_t)(3); + _rom_div_lookupa0[71] = _782; + uint16_t _783 = (uint16_t)(3); + _rom_div_lookupa0[72] = _783; + uint16_t _784 = (uint16_t)(3); + _rom_div_lookupa0[73] = _784; + uint16_t _785 = (uint16_t)(3); + _rom_div_lookupa0[74] = _785; + uint16_t _786 = (uint16_t)(3); + _rom_div_lookupa0[75] = _786; + uint16_t _787 = (uint16_t)(3); + _rom_div_lookupa0[76] = _787; + uint16_t _788 = (uint16_t)(3); + _rom_div_lookupa0[77] = _788; + uint16_t _789 = (uint16_t)(3); + _rom_div_lookupa0[78] = _789; + uint16_t _790 = (uint16_t)(3); + _rom_div_lookupa0[79] = _790; + uint16_t _791 = (uint16_t)(3); + _rom_div_lookupa0[80] = _791; + uint16_t _792 = (uint16_t)(3); + _rom_div_lookupa0[81] = _792; + uint16_t _793 = (uint16_t)(3); + _rom_div_lookupa0[82] = _793; + uint16_t _794 = (uint16_t)(3); + _rom_div_lookupa0[83] = _794; + uint16_t _795 = (uint16_t)(3); + _rom_div_lookupa0[84] = _795; + uint16_t _796 = (uint16_t)(2); + _rom_div_lookupa0[85] = _796; + uint16_t _797 = (uint16_t)(2); + _rom_div_lookupa0[86] = _797; + uint16_t _798 = (uint16_t)(2); + _rom_div_lookupa0[87] = _798; + uint16_t _799 = (uint16_t)(2); + _rom_div_lookupa0[88] = _799; + uint16_t _800 = (uint16_t)(2); + _rom_div_lookupa0[89] = _800; + uint16_t _801 = (uint16_t)(2); + _rom_div_lookupa0[90] = _801; + uint16_t _802 = (uint16_t)(2); + _rom_div_lookupa0[91] = _802; + uint16_t _803 = (uint16_t)(2); + _rom_div_lookupa0[92] = _803; + uint16_t _804 = (uint16_t)(2); + _rom_div_lookupa0[93] = _804; + uint16_t _805 = (uint16_t)(2); + _rom_div_lookupa0[94] = _805; + uint16_t _806 = (uint16_t)(2); + _rom_div_lookupa0[95] = _806; + uint16_t _807 = (uint16_t)(2); + _rom_div_lookupa0[96] = _807; + uint16_t _808 = (uint16_t)(2); + _rom_div_lookupa0[97] = _808; + uint16_t _809 = (uint16_t)(2); + _rom_div_lookupa0[98] = _809; + uint16_t _810 = (uint16_t)(2); + _rom_div_lookupa0[99] = _810; + uint16_t _811 = (uint16_t)(2); + _rom_div_lookupa0[100] = _811; + uint16_t _812 = (uint16_t)(2); + _rom_div_lookupa0[101] = _812; + uint16_t _813 = (uint16_t)(2); + _rom_div_lookupa0[102] = _813; + uint16_t _814 = (uint16_t)(2); + _rom_div_lookupa0[103] = _814; + uint16_t _815 = (uint16_t)(2); + _rom_div_lookupa0[104] = _815; + uint16_t _816 = (uint16_t)(2); + _rom_div_lookupa0[105] = _816; + uint16_t _817 = (uint16_t)(2); + _rom_div_lookupa0[106] = _817; + uint16_t _818 = (uint16_t)(2); + _rom_div_lookupa0[107] = _818; + uint16_t _819 = (uint16_t)(2); + _rom_div_lookupa0[108] = _819; + uint16_t _820 = (uint16_t)(2); + _rom_div_lookupa0[109] = _820; + uint16_t _821 = (uint16_t)(2); + _rom_div_lookupa0[110] = _821; + uint16_t _822 = (uint16_t)(2); + _rom_div_lookupa0[111] = _822; + uint16_t _823 = (uint16_t)(2); + _rom_div_lookupa0[112] = _823; + uint16_t _824 = (uint16_t)(2); + _rom_div_lookupa0[113] = _824; + uint16_t _825 = (uint16_t)(2); + _rom_div_lookupa0[114] = _825; + uint16_t _826 = (uint16_t)(2); + _rom_div_lookupa0[115] = _826; + uint16_t _827 = (uint16_t)(2); + _rom_div_lookupa0[116] = _827; + uint16_t _828 = (uint16_t)(2); + _rom_div_lookupa0[117] = _828; + uint16_t _829 = (uint16_t)(2); + _rom_div_lookupa0[118] = _829; + uint16_t _830 = (uint16_t)(2); + _rom_div_lookupa0[119] = _830; + uint16_t _831 = (uint16_t)(2); + _rom_div_lookupa0[120] = _831; + uint16_t _832 = (uint16_t)(2); + _rom_div_lookupa0[121] = _832; + uint16_t _833 = (uint16_t)(2); + _rom_div_lookupa0[122] = _833; + uint16_t _834 = (uint16_t)(2); + _rom_div_lookupa0[123] = _834; + uint16_t _835 = (uint16_t)(2); + _rom_div_lookupa0[124] = _835; + uint16_t _836 = (uint16_t)(2); + _rom_div_lookupa0[125] = _836; + uint16_t _837 = (uint16_t)(2); + _rom_div_lookupa0[126] = _837; + uint16_t _838 = (uint16_t)(2); + _rom_div_lookupa0[127] = _838; + uint16_t _839 = (uint16_t)(1); + _rom_div_lookupa0[128] = _839; + uint16_t _840 = (uint16_t)(1); + _rom_div_lookupa0[129] = _840; + uint16_t _841 = (uint16_t)(1); + _rom_div_lookupa0[130] = _841; + uint16_t _842 = (uint16_t)(1); + _rom_div_lookupa0[131] = _842; + uint16_t _843 = (uint16_t)(1); + _rom_div_lookupa0[132] = _843; + uint16_t _844 = (uint16_t)(1); + _rom_div_lookupa0[133] = _844; + uint16_t _845 = (uint16_t)(1); + _rom_div_lookupa0[134] = _845; + uint16_t _846 = (uint16_t)(1); + _rom_div_lookupa0[135] = _846; + uint16_t _847 = (uint16_t)(1); + _rom_div_lookupa0[136] = _847; + uint16_t _848 = (uint16_t)(1); + _rom_div_lookupa0[137] = _848; + uint16_t _849 = (uint16_t)(1); + _rom_div_lookupa0[138] = _849; + uint16_t _850 = (uint16_t)(1); + _rom_div_lookupa0[139] = _850; + uint16_t _851 = (uint16_t)(1); + _rom_div_lookupa0[140] = _851; + uint16_t _852 = (uint16_t)(1); + _rom_div_lookupa0[141] = _852; + uint16_t _853 = (uint16_t)(1); + _rom_div_lookupa0[142] = _853; + uint16_t _854 = (uint16_t)(1); + _rom_div_lookupa0[143] = _854; + uint16_t _855 = (uint16_t)(1); + _rom_div_lookupa0[144] = _855; + uint16_t _856 = (uint16_t)(1); + _rom_div_lookupa0[145] = _856; + uint16_t _857 = (uint16_t)(1); + _rom_div_lookupa0[146] = _857; + uint16_t _858 = (uint16_t)(1); + _rom_div_lookupa0[147] = _858; + uint16_t _859 = (uint16_t)(1); + _rom_div_lookupa0[148] = _859; + uint16_t _860 = (uint16_t)(1); + _rom_div_lookupa0[149] = _860; + uint16_t _861 = (uint16_t)(1); + _rom_div_lookupa0[150] = _861; + uint16_t _862 = (uint16_t)(1); + _rom_div_lookupa0[151] = _862; + uint16_t _863 = (uint16_t)(1); + _rom_div_lookupa0[152] = _863; + uint16_t _864 = (uint16_t)(1); + _rom_div_lookupa0[153] = _864; + uint16_t _865 = (uint16_t)(1); + _rom_div_lookupa0[154] = _865; + uint16_t _866 = (uint16_t)(1); + _rom_div_lookupa0[155] = _866; + uint16_t _867 = (uint16_t)(1); + _rom_div_lookupa0[156] = _867; + uint16_t _868 = (uint16_t)(1); + _rom_div_lookupa0[157] = _868; + uint16_t _869 = (uint16_t)(1); + _rom_div_lookupa0[158] = _869; + uint16_t _870 = (uint16_t)(1); + _rom_div_lookupa0[159] = _870; + uint16_t _871 = (uint16_t)(1); + _rom_div_lookupa0[160] = _871; + uint16_t _872 = (uint16_t)(1); + _rom_div_lookupa0[161] = _872; + uint16_t _873 = (uint16_t)(1); + _rom_div_lookupa0[162] = _873; + uint16_t _874 = (uint16_t)(1); + _rom_div_lookupa0[163] = _874; + uint16_t _875 = (uint16_t)(1); + _rom_div_lookupa0[164] = _875; + uint16_t _876 = (uint16_t)(1); + _rom_div_lookupa0[165] = _876; + uint16_t _877 = (uint16_t)(1); + _rom_div_lookupa0[166] = _877; + uint16_t _878 = (uint16_t)(1); + _rom_div_lookupa0[167] = _878; + uint16_t _879 = (uint16_t)(1); + _rom_div_lookupa0[168] = _879; + uint16_t _880 = (uint16_t)(1); + _rom_div_lookupa0[169] = _880; + uint16_t _881 = (uint16_t)(1); + _rom_div_lookupa0[170] = _881; + uint16_t _882 = (uint16_t)(1); + _rom_div_lookupa0[171] = _882; + uint16_t _883 = (uint16_t)(1); + _rom_div_lookupa0[172] = _883; + uint16_t _884 = (uint16_t)(1); + _rom_div_lookupa0[173] = _884; + uint16_t _885 = (uint16_t)(1); + _rom_div_lookupa0[174] = _885; + uint16_t _886 = (uint16_t)(1); + _rom_div_lookupa0[175] = _886; + uint16_t _887 = (uint16_t)(1); + _rom_div_lookupa0[176] = _887; + uint16_t _888 = (uint16_t)(1); + _rom_div_lookupa0[177] = _888; + uint16_t _889 = (uint16_t)(1); + _rom_div_lookupa0[178] = _889; + uint16_t _890 = (uint16_t)(1); + _rom_div_lookupa0[179] = _890; + uint16_t _891 = (uint16_t)(1); + _rom_div_lookupa0[180] = _891; + uint16_t _892 = (uint16_t)(1); + _rom_div_lookupa0[181] = _892; + uint16_t _893 = (uint16_t)(1); + _rom_div_lookupa0[182] = _893; + uint16_t _894 = (uint16_t)(1); + _rom_div_lookupa0[183] = _894; + uint16_t _895 = (uint16_t)(1); + _rom_div_lookupa0[184] = _895; + uint16_t _896 = (uint16_t)(1); + _rom_div_lookupa0[185] = _896; + uint16_t _897 = (uint16_t)(1); + _rom_div_lookupa0[186] = _897; + uint16_t _898 = (uint16_t)(1); + _rom_div_lookupa0[187] = _898; + uint16_t _899 = (uint16_t)(1); + _rom_div_lookupa0[188] = _899; + uint16_t _900 = (uint16_t)(1); + _rom_div_lookupa0[189] = _900; + uint16_t _901 = (uint16_t)(1); + _rom_div_lookupa0[190] = _901; + uint16_t _902 = (uint16_t)(1); + _rom_div_lookupa0[191] = _902; + uint16_t _903 = (uint16_t)(1); + _rom_div_lookupa0[192] = _903; + uint16_t _904 = (uint16_t)(1); + _rom_div_lookupa0[193] = _904; + uint16_t _905 = (uint16_t)(1); + _rom_div_lookupa0[194] = _905; + uint16_t _906 = (uint16_t)(1); + _rom_div_lookupa0[195] = _906; + uint16_t _907 = (uint16_t)(1); + _rom_div_lookupa0[196] = _907; + uint16_t _908 = (uint16_t)(1); + _rom_div_lookupa0[197] = _908; + uint16_t _909 = (uint16_t)(1); + _rom_div_lookupa0[198] = _909; + uint16_t _910 = (uint16_t)(1); + _rom_div_lookupa0[199] = _910; + uint16_t _911 = (uint16_t)(1); + _rom_div_lookupa0[200] = _911; + uint16_t _912 = (uint16_t)(1); + _rom_div_lookupa0[201] = _912; + uint16_t _913 = (uint16_t)(1); + _rom_div_lookupa0[202] = _913; + uint16_t _914 = (uint16_t)(1); + _rom_div_lookupa0[203] = _914; + uint16_t _915 = (uint16_t)(1); + _rom_div_lookupa0[204] = _915; + uint16_t _916 = (uint16_t)(1); + _rom_div_lookupa0[205] = _916; + uint16_t _917 = (uint16_t)(1); + _rom_div_lookupa0[206] = _917; + uint16_t _918 = (uint16_t)(1); + _rom_div_lookupa0[207] = _918; + uint16_t _919 = (uint16_t)(1); + _rom_div_lookupa0[208] = _919; + uint16_t _920 = (uint16_t)(1); + _rom_div_lookupa0[209] = _920; + uint16_t _921 = (uint16_t)(1); + _rom_div_lookupa0[210] = _921; + uint16_t _922 = (uint16_t)(1); + _rom_div_lookupa0[211] = _922; + uint16_t _923 = (uint16_t)(1); + _rom_div_lookupa0[212] = _923; + uint16_t _924 = (uint16_t)(1); + _rom_div_lookupa0[213] = _924; + uint16_t _925 = (uint16_t)(1); + _rom_div_lookupa0[214] = _925; + uint16_t _926 = (uint16_t)(1); + _rom_div_lookupa0[215] = _926; + uint16_t _927 = (uint16_t)(1); + _rom_div_lookupa0[216] = _927; + uint16_t _928 = (uint16_t)(1); + _rom_div_lookupa0[217] = _928; + uint16_t _929 = (uint16_t)(1); + _rom_div_lookupa0[218] = _929; + uint16_t _930 = (uint16_t)(1); + _rom_div_lookupa0[219] = _930; + uint16_t _931 = (uint16_t)(1); + _rom_div_lookupa0[220] = _931; + uint16_t _932 = (uint16_t)(1); + _rom_div_lookupa0[221] = _932; + uint16_t _933 = (uint16_t)(1); + _rom_div_lookupa0[222] = _933; + uint16_t _934 = (uint16_t)(1); + _rom_div_lookupa0[223] = _934; + uint16_t _935 = (uint16_t)(1); + _rom_div_lookupa0[224] = _935; + uint16_t _936 = (uint16_t)(1); + _rom_div_lookupa0[225] = _936; + uint16_t _937 = (uint16_t)(1); + _rom_div_lookupa0[226] = _937; + uint16_t _938 = (uint16_t)(1); + _rom_div_lookupa0[227] = _938; + uint16_t _939 = (uint16_t)(1); + _rom_div_lookupa0[228] = _939; + uint16_t _940 = (uint16_t)(1); + _rom_div_lookupa0[229] = _940; + uint16_t _941 = (uint16_t)(1); + _rom_div_lookupa0[230] = _941; + uint16_t _942 = (uint16_t)(1); + _rom_div_lookupa0[231] = _942; + uint16_t _943 = (uint16_t)(1); + _rom_div_lookupa0[232] = _943; + uint16_t _944 = (uint16_t)(1); + _rom_div_lookupa0[233] = _944; + uint16_t _945 = (uint16_t)(1); + _rom_div_lookupa0[234] = _945; + uint16_t _946 = (uint16_t)(1); + _rom_div_lookupa0[235] = _946; + uint16_t _947 = (uint16_t)(1); + _rom_div_lookupa0[236] = _947; + uint16_t _948 = (uint16_t)(1); + _rom_div_lookupa0[237] = _948; + uint16_t _949 = (uint16_t)(1); + _rom_div_lookupa0[238] = _949; + uint16_t _950 = (uint16_t)(1); + _rom_div_lookupa0[239] = _950; + uint16_t _951 = (uint16_t)(1); + _rom_div_lookupa0[240] = _951; + uint16_t _952 = (uint16_t)(1); + _rom_div_lookupa0[241] = _952; + uint16_t _953 = (uint16_t)(1); + _rom_div_lookupa0[242] = _953; + uint16_t _954 = (uint16_t)(1); + _rom_div_lookupa0[243] = _954; + uint16_t _955 = (uint16_t)(1); + _rom_div_lookupa0[244] = _955; + uint16_t _956 = (uint16_t)(1); + _rom_div_lookupa0[245] = _956; + uint16_t _957 = (uint16_t)(1); + _rom_div_lookupa0[246] = _957; + uint16_t _958 = (uint16_t)(1); + _rom_div_lookupa0[247] = _958; + uint16_t _959 = (uint16_t)(1); + _rom_div_lookupa0[248] = _959; + uint16_t _960 = (uint16_t)(1); + _rom_div_lookupa0[249] = _960; + uint16_t _961 = (uint16_t)(1); + _rom_div_lookupa0[250] = _961; + uint16_t _962 = (uint16_t)(1); + _rom_div_lookupa0[251] = _962; + uint16_t _963 = (uint16_t)(1); + _rom_div_lookupa0[252] = _963; + uint16_t _964 = (uint16_t)(1); + _rom_div_lookupa0[253] = _964; + uint16_t _965 = (uint16_t)(1); + _rom_div_lookupa0[254] = _965; + + uint16_t _966 = (uint16_t)(1); + uint16_t _967 = max(_gray_stencil_1, _966); + int32_t _968 = (int32_t)(_967); + int32_t _969 = _968 + -1; + uint16_t _970 = ((const uint16_t *)_rom_div_lookupa0)[_969]; + return _970; +} + +//store is: blur_unnormalized.stencil(blur_unnormalized_s0_x_x, blur_unnormalized_s0_y) = (uint16)0 +hw_uint<16> hcompute_blur_unnormalized_stencil() { + uint16_t _984 = (uint16_t)(0); + return _984; +} + +//store is: blur_unnormalized.stencil(blur_unnormalized_s1_x_x, blur_unnormalized_s1_y) = (gray.stencil((blur_unnormalized_s1_x_x + 1), blur_unnormalized_s1_y) + (blur_unnormalized.stencil(blur_unnormalized_s1_x_x, blur_unnormalized_s1_y) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), blur_unnormalized_s1_y)*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), blur_unnormalized_s1_y)*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), blur_unnormalized_s1_y)*(uint16)2) + (gray.stencil((blur_unnormalized_s1_x_x + 5), blur_unnormalized_s1_y) + (gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 1)) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 1))*(uint16)3) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 1))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 1))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 1))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 1))*(uint16)3) + (gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 1)) + ((gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 2))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 2))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 2))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 2))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 2))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 2))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 2))*(uint16)2) + ((gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 3))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 3))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 3))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 3))*(uint16)18) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 3))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 3))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 3))*(uint16)2) + ((gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 4))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 4))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 4))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 4))*(uint16)15) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 4))*(uint16)12) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 4))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 4))*(uint16)2) + (gray.stencil(blur_unnormalized_s1_x_x, (blur_unnormalized_s1_y + 5)) + ((gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 5))*(uint16)3) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 5))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 5))*(uint16)7) + ((gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 5))*(uint16)6) + ((gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 5))*(uint16)3) + (gray.stencil((blur_unnormalized_s1_x_x + 6), (blur_unnormalized_s1_y + 5)) + (gray.stencil((blur_unnormalized_s1_x_x + 1), (blur_unnormalized_s1_y + 6)) + ((gray.stencil((blur_unnormalized_s1_x_x + 2), (blur_unnormalized_s1_y + 6))*(uint16)2) + ((gray.stencil((blur_unnormalized_s1_x_x + 3), (blur_unnormalized_s1_y + 6))*(uint16)2) + (gray.stencil((blur_unnormalized_s1_x_x + 5), (blur_unnormalized_s1_y + 6)) + (gray.stencil((blur_unnormalized_s1_x_x + 4), (blur_unnormalized_s1_y + 6))*(uint16)2)))))))))))))))))))))))))))))))))))))))))))))) +hw_uint<16> hcompute_blur_unnormalized_stencil_1(hw_uint<16>& blur_unnormalized_stencil, hw_uint<720>& gray_stencil) { + uint16_t _blur_unnormalized_stencil_1 = (uint16_t) blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _gray_stencil_10 = (uint16_t) gray_stencil.extract<0, 15>(); + uint16_t _gray_stencil_11 = (uint16_t) gray_stencil.extract<16, 31>(); + uint16_t _gray_stencil_12 = (uint16_t) gray_stencil.extract<32, 47>(); + uint16_t _gray_stencil_13 = (uint16_t) gray_stencil.extract<48, 63>(); + uint16_t _gray_stencil_14 = (uint16_t) gray_stencil.extract<64, 79>(); + uint16_t _gray_stencil_15 = (uint16_t) gray_stencil.extract<80, 95>(); + uint16_t _gray_stencil_16 = (uint16_t) gray_stencil.extract<96, 111>(); + uint16_t _gray_stencil_17 = (uint16_t) gray_stencil.extract<112, 127>(); + uint16_t _gray_stencil_18 = (uint16_t) gray_stencil.extract<128, 143>(); + uint16_t _gray_stencil_19 = (uint16_t) gray_stencil.extract<144, 159>(); + uint16_t _gray_stencil_2 = (uint16_t) gray_stencil.extract<160, 175>(); + uint16_t _gray_stencil_20 = (uint16_t) gray_stencil.extract<176, 191>(); + uint16_t _gray_stencil_21 = (uint16_t) gray_stencil.extract<192, 207>(); + uint16_t _gray_stencil_22 = (uint16_t) gray_stencil.extract<208, 223>(); + uint16_t _gray_stencil_23 = (uint16_t) gray_stencil.extract<224, 239>(); + uint16_t _gray_stencil_24 = (uint16_t) gray_stencil.extract<240, 255>(); + uint16_t _gray_stencil_25 = (uint16_t) gray_stencil.extract<256, 271>(); + uint16_t _gray_stencil_26 = (uint16_t) gray_stencil.extract<272, 287>(); + uint16_t _gray_stencil_27 = (uint16_t) gray_stencil.extract<288, 303>(); + uint16_t _gray_stencil_28 = (uint16_t) gray_stencil.extract<304, 319>(); + uint16_t _gray_stencil_29 = (uint16_t) gray_stencil.extract<320, 335>(); + uint16_t _gray_stencil_3 = (uint16_t) gray_stencil.extract<336, 351>(); + uint16_t _gray_stencil_30 = (uint16_t) gray_stencil.extract<352, 367>(); + uint16_t _gray_stencil_31 = (uint16_t) gray_stencil.extract<368, 383>(); + uint16_t _gray_stencil_32 = (uint16_t) gray_stencil.extract<384, 399>(); + uint16_t _gray_stencil_33 = (uint16_t) gray_stencil.extract<400, 415>(); + uint16_t _gray_stencil_34 = (uint16_t) gray_stencil.extract<416, 431>(); + uint16_t _gray_stencil_35 = (uint16_t) gray_stencil.extract<432, 447>(); + uint16_t _gray_stencil_36 = (uint16_t) gray_stencil.extract<448, 463>(); + uint16_t _gray_stencil_37 = (uint16_t) gray_stencil.extract<464, 479>(); + uint16_t _gray_stencil_38 = (uint16_t) gray_stencil.extract<480, 495>(); + uint16_t _gray_stencil_39 = (uint16_t) gray_stencil.extract<496, 511>(); + uint16_t _gray_stencil_4 = (uint16_t) gray_stencil.extract<512, 527>(); + uint16_t _gray_stencil_40 = (uint16_t) gray_stencil.extract<528, 543>(); + uint16_t _gray_stencil_41 = (uint16_t) gray_stencil.extract<544, 559>(); + uint16_t _gray_stencil_42 = (uint16_t) gray_stencil.extract<560, 575>(); + uint16_t _gray_stencil_43 = (uint16_t) gray_stencil.extract<576, 591>(); + uint16_t _gray_stencil_44 = (uint16_t) gray_stencil.extract<592, 607>(); + uint16_t _gray_stencil_45 = (uint16_t) gray_stencil.extract<608, 623>(); + uint16_t _gray_stencil_46 = (uint16_t) gray_stencil.extract<624, 639>(); + uint16_t _gray_stencil_5 = (uint16_t) gray_stencil.extract<640, 655>(); + uint16_t _gray_stencil_6 = (uint16_t) gray_stencil.extract<656, 671>(); + uint16_t _gray_stencil_7 = (uint16_t) gray_stencil.extract<672, 687>(); + uint16_t _gray_stencil_8 = (uint16_t) gray_stencil.extract<688, 703>(); + uint16_t _gray_stencil_9 = (uint16_t) gray_stencil.extract<704, 719>(); + + uint16_t _987 = (uint16_t)(2); + uint16_t _988 = _gray_stencil_3 * _987; + uint16_t _989 = _gray_stencil_4 * _987; + uint16_t _990 = _gray_stencil_5 * _987; + uint16_t _991 = (uint16_t)(3); + uint16_t _992 = _gray_stencil_8 * _991; + uint16_t _993 = (uint16_t)(6); + uint16_t _994 = _gray_stencil_9 * _993; + uint16_t _995 = (uint16_t)(7); + uint16_t _996 = _gray_stencil_10 * _995; + uint16_t _997 = _gray_stencil_11 * _993; + uint16_t _998 = _gray_stencil_12 * _991; + uint16_t _999 = _gray_stencil_14 * _987; + uint16_t _1000 = _gray_stencil_15 * _993; + uint16_t _1001 = (uint16_t)(12); + uint16_t _1002 = _gray_stencil_16 * _1001; + uint16_t _1003 = (uint16_t)(15); + uint16_t _1004 = _gray_stencil_17 * _1003; + uint16_t _1005 = _gray_stencil_18 * _1001; + uint16_t _1006 = _gray_stencil_19 * _993; + uint16_t _1007 = _gray_stencil_20 * _987; + uint16_t _1008 = _gray_stencil_21 * _987; + uint16_t _1009 = _gray_stencil_22 * _995; + uint16_t _1010 = _gray_stencil_23 * _1003; + uint16_t _1011 = (uint16_t)(18); + uint16_t _1012 = _gray_stencil_24 * _1011; + uint16_t _1013 = _gray_stencil_25 * _1003; + uint16_t _1014 = _gray_stencil_26 * _995; + uint16_t _1015 = _gray_stencil_27 * _987; + uint16_t _1016 = _gray_stencil_28 * _987; + uint16_t _1017 = _gray_stencil_29 * _993; + uint16_t _1018 = _gray_stencil_30 * _1001; + uint16_t _1019 = _gray_stencil_31 * _1003; + uint16_t _1020 = _gray_stencil_32 * _1001; + uint16_t _1021 = _gray_stencil_33 * _993; + uint16_t _1022 = _gray_stencil_34 * _987; + uint16_t _1023 = _gray_stencil_36 * _991; + uint16_t _1024 = _gray_stencil_37 * _993; + uint16_t _1025 = _gray_stencil_38 * _995; + uint16_t _1026 = _gray_stencil_39 * _993; + uint16_t _1027 = _gray_stencil_40 * _991; + uint16_t _1028 = _gray_stencil_43 * _987; + uint16_t _1029 = _gray_stencil_44 * _987; + uint16_t _1030 = _gray_stencil_46 * _987; + uint16_t _1031 = _gray_stencil_45 + _1030; + uint16_t _1032 = _1029 + _1031; + uint16_t _1033 = _1028 + _1032; + uint16_t _1034 = _gray_stencil_42 + _1033; + uint16_t _1035 = _gray_stencil_41 + _1034; + uint16_t _1036 = _1027 + _1035; + uint16_t _1037 = _1026 + _1036; + uint16_t _1038 = _1025 + _1037; + uint16_t _1039 = _1024 + _1038; + uint16_t _1040 = _1023 + _1039; + uint16_t _1041 = _gray_stencil_35 + _1040; + uint16_t _1042 = _1022 + _1041; + uint16_t _1043 = _1021 + _1042; + uint16_t _1044 = _1020 + _1043; + uint16_t _1045 = _1019 + _1044; + uint16_t _1046 = _1018 + _1045; + uint16_t _1047 = _1017 + _1046; + uint16_t _1048 = _1016 + _1047; + uint16_t _1049 = _1015 + _1048; + uint16_t _1050 = _1014 + _1049; + uint16_t _1051 = _1013 + _1050; + uint16_t _1052 = _1012 + _1051; + uint16_t _1053 = _1010 + _1052; + uint16_t _1054 = _1009 + _1053; + uint16_t _1055 = _1008 + _1054; + uint16_t _1056 = _1007 + _1055; + uint16_t _1057 = _1006 + _1056; + uint16_t _1058 = _1005 + _1057; + uint16_t _1059 = _1004 + _1058; + uint16_t _1060 = _1002 + _1059; + uint16_t _1061 = _1000 + _1060; + uint16_t _1062 = _999 + _1061; + uint16_t _1063 = _gray_stencil_13 + _1062; + uint16_t _1064 = _998 + _1063; + uint16_t _1065 = _997 + _1064; + uint16_t _1066 = _996 + _1065; + uint16_t _1067 = _994 + _1066; + uint16_t _1068 = _992 + _1067; + uint16_t _1069 = _gray_stencil_7 + _1068; + uint16_t _1070 = _gray_stencil_6 + _1069; + uint16_t _1071 = _990 + _1070; + uint16_t _1072 = _989 + _1071; + uint16_t _1073 = _988 + _1072; + uint16_t _1074 = _blur_unnormalized_stencil_1 + _1073; + uint16_t _1075 = _gray_stencil_2 + _1074; + return _1075; +} + +//store is: sharpen.stencil(sharpen_s0_x_x, sharpen_s0_y) = uint16(max(min(((int16(gray.stencil((sharpen_s0_x_x + 3), (sharpen_s0_y + 3)))*(int16)2) - int16(uint8((blur_unnormalized.stencil(sharpen_s0_x_x, sharpen_s0_y)/(uint16)256)))), (int16)255), (int16)0)) +hw_uint<16> hcompute_sharpen_stencil(hw_uint<16>& blur_unnormalized_stencil, hw_uint<16>& gray_stencil) { + uint16_t _blur_unnormalized_stencil_2 = (uint16_t) blur_unnormalized_stencil.extract<0, 15>(); + + uint16_t _gray_stencil_47 = (uint16_t) gray_stencil.extract<0, 15>(); + + int16_t _1312 = (int16_t)(_gray_stencil_47); + int16_t _1313 = (int16_t)(2); + int16_t _1314 = _1312 * _1313; + uint16_t _1315 = (uint16_t)(8); + uint16_t _1316 = _blur_unnormalized_stencil_2 >> _1315; + uint8_t _1317 = (uint8_t)(_1316); + int16_t _1318 = (int16_t)(_1317); + int16_t _1319 = _1314 - _1318; + int16_t _1320 = (int16_t)(255); + int16_t _1321 = min(_1319, _1320); + int16_t _1322 = (int16_t)(0); + int16_t _1323 = max(_1321, _1322); + uint16_t _1324 = (uint16_t)(_1323); + return _1324; +} + +//store is: ratio.stencil(ratio_s0_x_x, ratio_s0_y) = (sharpen.stencil(ratio_s0_x_x, ratio_s0_y)*reciprocal.stencil(ratio_s0_x_x, ratio_s0_y)) +hw_uint<16> hcompute_ratio_stencil(hw_uint<16>& reciprocal_stencil, hw_uint<16>& sharpen_stencil) { + uint16_t _reciprocal_stencil_1 = (uint16_t) reciprocal_stencil.extract<0, 15>(); + + uint16_t _sharpen_stencil_1 = (uint16_t) sharpen_stencil.extract<0, 15>(); + + uint16_t _1355 = _sharpen_stencil_1 * _reciprocal_stencil_1; + return _1355; +} + +//store is: hw_output.glb.stencil(0, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = int16(((int32(ratio.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi))*int32(hw_input_global_wrapper_global_wrapper.stencil(0, (hw_output_s0_x_xi_xi + 3), (hw_output_s0_y_yi + 3))))/256)) +hw_uint<16> hcompute_hw_output_glb_stencil(hw_uint<16>& hw_input_global_wrapper_global_wrapper_stencil, hw_uint<16>& ratio_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_4 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + + uint16_t _ratio_stencil_1 = (uint16_t) ratio_stencil.extract<0, 15>(); + + int32_t _1360 = (int32_t)(_ratio_stencil_1); + int32_t _1361 = (int32_t)(_hw_input_global_wrapper_global_wrapper_stencil_4); + int32_t _1362 = _1360 * _1361; + int32_t _1363 = _1362 >> 8; + int16_t _1364 = (int16_t)(_1363); + return _1364; +} + +//store is: hw_output.glb.stencil(1, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = int16(((int32(ratio.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi))*int32(hw_input_global_wrapper_global_wrapper.stencil(1, (hw_output_s0_x_xi_xi + 3), (hw_output_s0_y_yi + 3))))/256)) +hw_uint<16> hcompute_hw_output_glb_stencil_1(hw_uint<16>& hw_input_global_wrapper_global_wrapper_stencil, hw_uint<16>& ratio_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_5 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + + uint16_t _ratio_stencil_2 = (uint16_t) ratio_stencil.extract<0, 15>(); + + int32_t _1377 = (int32_t)(_ratio_stencil_2); + int32_t _1378 = (int32_t)(_hw_input_global_wrapper_global_wrapper_stencil_5); + int32_t _1379 = _1377 * _1378; + int32_t _1380 = _1379 >> 8; + int16_t _1381 = (int16_t)(_1380); + return _1381; +} + +//store is: hw_output.glb.stencil(2, hw_output_s0_x_xi_xi, hw_output_s0_y_yi) = int16(((int32(ratio.stencil(hw_output_s0_x_xi_xi, hw_output_s0_y_yi))*int32(hw_input_global_wrapper_global_wrapper.stencil(2, (hw_output_s0_x_xi_xi + 3), (hw_output_s0_y_yi + 3))))/256)) +hw_uint<16> hcompute_hw_output_glb_stencil_2(hw_uint<16>& hw_input_global_wrapper_global_wrapper_stencil, hw_uint<16>& ratio_stencil) { + uint16_t _hw_input_global_wrapper_global_wrapper_stencil_6 = (uint16_t) hw_input_global_wrapper_global_wrapper_stencil.extract<0, 15>(); + + uint16_t _ratio_stencil_3 = (uint16_t) ratio_stencil.extract<0, 15>(); + + int32_t _1394 = (int32_t)(_ratio_stencil_3); + int32_t _1395 = (int32_t)(_hw_input_global_wrapper_global_wrapper_stencil_6); + int32_t _1396 = _1394 * _1395; + int32_t _1397 = _1396 >> 8; + int16_t _1398 = (int16_t)(_1397); + return _1398; +} + +//store is: hw_output_global_wrapper.stencil(0, (hw_output_global_wrapper_s0_x_xi_xi + (0*126)), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(0, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil(hw_uint<16>& hw_output_glb_stencil) { + int16_t _hw_output_glb_stencil_1 = (int16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_1; +} + +//store is: hw_output_global_wrapper.stencil(1, (hw_output_global_wrapper_s0_x_xi_xi + (0*126)), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(1, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_1(hw_uint<16>& hw_output_glb_stencil) { + int16_t _hw_output_glb_stencil_2 = (int16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_2; +} + +//store is: hw_output_global_wrapper.stencil(2, (hw_output_global_wrapper_s0_x_xi_xi + (0*126)), (hw_output_global_wrapper_s0_y_yi + 0)) = hw_output.glb.stencil(2, hw_output_global_wrapper_s0_x_xi_xi, hw_output_global_wrapper_s0_y_yi) +hw_uint<16> hcompute_hw_output_global_wrapper_stencil_2(hw_uint<16>& hw_output_glb_stencil) { + int16_t _hw_output_glb_stencil_3 = (int16_t) hw_output_glb_stencil.extract<0, 15>(); + + return _hw_output_glb_stencil_3; +} + diff --git a/utils.h b/utils.h index f06c3edfa..06a058043 100644 --- a/utils.h +++ b/utils.h @@ -10,6 +10,66 @@ using namespace dbhc; using namespace std; + +template +static inline +std::ostream& operator<< (std::ostream& out, const std::pair& v) { + out << "{" << v.first << ", " << v.second << "} "; + return out; +} + +template +static inline +std::ostream& operator<< (std::ostream& out, const std::vector& v) { + if ( !v.empty() ) { + out << '['; + std::copy (v.begin(), v.end(), std::ostream_iterator(out, ", ")); + out << "\b\b]"; + } + return out; +} + +template +static inline +std::ostream& operator<< (std::ostream& out, const std::set& v) { + if ( !v.empty() ) { + out << '{'; + std::copy (v.begin(), v.end(), std::ostream_iterator(out, ", ")); + out << "\b\b}"; + } + return out; +} + +template +static inline +std::ostream& operator<< (std::ostream& out, const std::map& m) { + if ( !m.empty() ) { + for (const auto &p : m) + { + out << p.first << ": "; + out << p.second << ' '; + out << std::endl; + } + + } + return out; +} + +template +static inline +std::ostream& operator<< (std::ostream& out, const std::map& m) { + if ( !m.empty() ) { + for (const auto &p : m) + { + out << p.first << ": "; + out << p.second << ' '; + out << '\t'; + } + + } + return out; +} + template static inline T pop(deque& d) {